STM32F10x Standard Peripherals Firmware Library: STM32F10x Standard Peripherals Library

STM32F10x Standard Peripherals Firmware Library
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STM32F10x Standard Peripherals Library

STM32F10x Standard Peripherals Library

Copyright 2011 STMicroelectronics

The STM32F10x Standard Peripherals Library is a complete package, consisting of device drivers for all of the standard device peripherals, for STM32 Value line(High, Medium and Low), Connectivity line, XL-, High-, Medium- and Low- Density Devices 32-bit Flash microcontrollers.

This library is a firmware package which contains a collection of routines, data structures and macros covering the features of STM32 peripherals. It includes a description of the device drivers plus a set of examples for each peripheral. The firmware library allows any device to be used in the user application without the need for in-depth study of each peripheral’s specifications.

Using the Standard Peripherals Library has two advantages: it saves significant time that would otherwise be spent in coding, while simultaneously reducing application development and integration costs.

The STM32F10x Standard Peripherals Library is full CMSIS compliant.

The manual is structured as follows:

Standard Peripherals Library

Overview

MISRA-C 2004 Compliance

Run-time Checking

Coding rules and conventions

Acronyms

Naming conventions

Coding rules

Bit-Banding

Description of Peripheral's driver and CMSIS files

Architecture

STM32F10x Standard Peripheral's Drivers

STM32F10x CMSIS files

Supported devices and toolchains

STM32 device peripherals overview

Supported STM32 devices

Supported toolchains

How to use the Library

How to use the Standard Peripherals Library

Peripheral initialization and configuration

Package description

Peripheral Examples
STM32F10x StdPeriph_Lib Examples?

What do I need to start successfully with Examples?

How to proceed?

Manual tab sheets description:

Modules: Lists the different modules that compose this Library.

Data Structures: Lists the variables, defines, structures, ...

Files: Lists all the files and global.

Directories: List of directories.

Release Notes for STM32F10x Standard Peripherals Library

Limitations: STM32F10x Standard Peripherals Library Limitations.

STM32F10xxx FWLib V2.0.3 legacy: STM32F10x FWLib V2.0.3 Legacy.

License

The enclosed firmware and all the related documentation are not covered by a License Agreement, if you need such License you can contact your local STMicroelectronics office.

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: STM32F10x Standard Peripheral's Drivers

  • Modules
  • Data Structures
  • Files
  • Directories

STM32F10x Standard Peripheral's Drivers

src

  • misc.c
  • stm32f10x_adc.c
  • stm32f10x_bkp.c
  • stm32f10x_can.c
  • stm32f10x_cec.c
  • stm32f10x_crc.c
  • stm32f10x_dac.c
  • stm32f10x_dbgmcu.c
  • stm32f10x_dma.c
  • stm32f10x_exti.c
  • stm32f10x_flash.c
  • stm32f10x_fsmc.c
  • stm32f10x_gpio.c
  • stm32f10x_i2c.c
  • stm32f10x_iwdg.c
  • stm32f10x_pwr.c
  • stm32f10x_rcc.c
  • stm32f10x_rtc.c
  • stm32f10x_sdio.c
  • stm32f10x_spi.c
  • stm32f10x_tim.c
  • stm32f10x_usart.c
  • stm32f10x_iwdg.c

inc

  • misc.h
  • stm32f10x_adc.h
  • stm32f10x_bkp.h
  • stm32f10x_can.h
  • stm32f10x_cec.h
  • stm32f10x_crc.h
  • stm32f10x_dac.h
  • stm32f10x_dbgmcu.h
  • stm32f10x_dma.h
  • stm32f10x_exti.h
  • stm32f10x_flash.h
  • stm32f10x_fsmc.h
  • stm32f10x_gpio.h
  • stm32f10x_i2c.h
  • stm32f10x_iwdg.h
  • stm32f10x_pwr.h
  • stm32f10x_rcc.h
  • stm32f10x_rtc.h
  • stm32f10x_sdio.h
  • stm32f10x_spi.h
  • stm32f10x_tim.h
  • stm32f10x_usart.h
  • stm32f10x_iwdg.h


STM32F10x Standard Peripherals Firmware Library: 3 ADCs DMA example

  • Directories
  • STM32F10x Standard Peripheral's Examples
  • DMA_EXAMPLES

3 ADCs DMA example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    ADC/3ADCs_DMA/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the 3ADCs DMA example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example describes how to use the 3 ADCs in independent conversions. Two of them; ADC1 and ADC3 are transferring continuously converted data using DMA while ADC2 converted data are stored using End of conversion interrupt.

ADC1 is configured to convert continuously ADC channel14. Each time an end of conversion occurs the DMA1 transfers, in circular mode, the converted data from ADC1 DR register to the ADC1_ConvertedValue variable.

ADC2 is configured to convert continuously ADC channel13. Each time an end of conversion occurs an end of conversion interrupt is generated and inside the interrupt routine the converted data are read from ADC2 DR register and stored into the ADC2_ConvertedValue variable.

ADC3 is configured to convert continuously ADC channel12. Each time an end of conversion occurs the DMA2 transfers, in circular mode, the converted data from ADC3 DR register to the ADC3_ConvertedValue variable.

The ADCs clocks are set to 14 MHz.

The result of ADC1, ADC2 and ADC3 conversion is monitored through the three variables: ADC1ConvertedValue, ADC2ConvertedValue and ADC3ConvertedValue.

Directory contents
  • ADC/3ADCs_DMA/stm32f10x_conf.h Library Configuration file
  • ADC/3ADCs_DMA/stm32f10x_it.c Interrupt handlers
  • ADC/3ADCs_DMA/stm32f10x_it.h Interrupt handlers header file
  • ADC/3ADCs_DMA/system_stm32f10x.c STM32F10x system source file
  • ADC/3ADCs_DMA/main.c Main program
Hardware and Software environment
  • This example runs only on STM32F10x High-Density and XL-Density Devices.
  • This example has been tested with STMicroelectronics STM3210E-EVAL (High-Density and XL-Density) evaluation board and can be easily tailored to any other supported device and development board.
  • STM3210E-EVAL Set-up
    • Connect a variable power supply 0-3.3V to ADC3 Channel12 mapped on pin PC.02
    • Connect a variable power supply 0-3.3V to ADC2 Channel13 mapped on pin PC.03
    • Connect a variable power supply 0-3.3V to ADC1 Channel14 mapped on pin PC.04 (potentiometer RV1 on STM3210E-EVAL board)
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: ADC1 DMA example

  • STM32F10x Standard Peripheral's Examples
  • DMA_EXAMPLES

ADC1 DMA example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    ADC/ADC1_DMA/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the ADC1 DMA example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example describes how to use the ADC1 and DMA to transfer continuously converted data from ADC1 to memory. The ADC1 is configured to convert continuously channel14. Each time an end of conversion occurs the DMA transfers, in circular mode, the converted data from ADC1 DR register to the ADCConvertedValue variable. The ADC1 clock is set to 12 MHz on Value line devices and to 14MHz on other devices.

Directory contents
  • ADC/ADC1_DMA/stm32f10x_conf.h Library Configuration file
  • ADC/ADC1_DMA/stm32f10x_it.c Interrupt handlers
  • ADC/ADC1_DMA/stm32f10x_it.h Interrupt handlers header file
  • ADC/ADC1_DMA/system_stm32f10x.c STM32F10x system source file
  • ADC/ADC1_DMA/main.c Main program
Hardware and Software environment
  • This example runs on STM32F10x Connectivity line, High-Density, High-Density Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density and Low-Density Value line Devices.
  • This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) evaluation boards and can be easily tailored to any other supported device and development board.
  • STM32100E-EVAL Set-up
    • Connect a variable power supply 0-3.3V to ADC Channel14 mapped on pin PC.04 (potentiometer RV2)
  • STM32100B-EVAL Set-up
    • Connect a variable power supply 0-3.3V to ADC Channel14 mapped on pin PC.04 (potentiometer RV1)
  • STM3210C-EVAL Set-up
    • Connect a variable power supply 0-3.3V to ADC Channel14 mapped on pin PC.04 (potentiometer RV1)
  • STM3210E-EVAL Set-up
    • Connect a variable power supply 0-3.3V to ADC Channel14 mapped on pin PC.04 (potentiometer RV1)
  • STM3210B-EVAL Set-up
    • Connect a variable power supply 0-3.3V to ADC Channel14 mapped on pin PC.04 (potentiometer RV1)
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: ADC analog watchdog example

  • STM32F10x Standard Peripheral's Examples

ADC analog watchdog example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    ADC/AnalogWatchdog/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the ADC analog watchdog example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example describes how to use the ADC analog watchdog to guard continuously an ADC channel. The ADC1 is configured to convert continuously ADC channel14. The analog watchdog is configured and enabled to guard a single regular channel. Each time the channel14 converted value exceeds programmed analog watchdog high threshold (value 0x0B00) or goes down analog watchdog low threshold (value 0x0300) an AWD interrupt is generated and the output pin connected to LED1 is toggled. The LED will bright as long as the AWD interrupt is generated which means that the converted value of regular ADC channel14 is outside the range limited by high and low analog watchdog thresholds. The ADC1 clock is set to 12 MHz on Value line devices and to 14 MHz on other devices.

Directory contents
  • ADC/AnalogWatchdog/stm32f10x_conf.h Library Configuration file
  • ADC/AnalogWatchdog/stm32f10x_it.c Interrupt handlers
  • ADC/AnalogWatchdog/stm32f10x_it.h Interrupt handlers header file
  • ADC/AnalogWatchdog/system_stm32f10x.c STM32F10x system source file
  • ADC/AnalogWatchdog/main.c Main program
Hardware and Software environment
  • This example runs on STM32F10x Connectivity line, High-Density, High-Density Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density and Low-Density Value line Devices.
  • This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) evaluation boards and can be easily tailored to any other supported device and development board. To select the STMicroelectronics evaluation board used to run the example, uncomment the corresponding line in stm32_eval.h file (under Utilities)
  • STM32100E-EVAL
    • Use LD1 led connected to PF.06 pin
    • Connect a variable power supply 0-3.3V to ADC Channel14 mapped on pin PC.04 (potentiometer RV1)
  • STM32100B-EVAL Set-up
    • Use LED1 led connected to PC.06 pin
    • Connect a variable power supply 0-3.3V to ADC Channel14 mapped on pin PC.04 (potentiometer RV2)
  • STM3210C-EVAL Set-up
    • Use LED1 led connected to PD.07 pin
    • Connect a variable power supply 0-3.3V to ADC Channel14 mapped on pin PC.04 (potentiometer RV1)
  • STM3210E-EVAL Set-up
    • Use LD1 led connected to PF.06 pin
    • Connect a variable power supply 0-3.3V to ADC Channel14 mapped on pin PC.04 (potentiometer RV1)
  • STM3210B-EVAL
    • Use LD1 led connected to PC.06 pin
    • Connect a variable power supply 0-3.3V to ADC Channel14 mapped on pin PC.04 (potentiometer RV1)
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: ADC external lines trigger example

  • STM32F10x Standard Peripheral's Examples
  • DMA_EXAMPLES

ADC external lines trigger example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    ADC/ExtLinesTrigger/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the ADC external lines trigger example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example describes how to trigger ADC regular and injected groups channels conversion using two external line events. Discontinuous mode is enabled for regular group channel conversion and configured to convert one regular channel on each external trigger.

ADC1 is configured to start regular group channel conversion on EXTI11 event. On detection of the first rising edge on PE.11 pin (PF.11 pin for High-Density Value line), the conversion of the first regular channel (ADC channel4) is done and its converted value is transferred by DMA to ADC_RegularConvertedValueTab table. On the following edge detection, the second regular channel (ADC channel14) is automatically converted and its converted value is stored by DMA in the same table. The number of transmitted data by DMA, in this example is limited to 64 data.

The procedure is repeated for both regular channels on each EXTI11 event. ADC1 is configured to start injected group channel conversion on EXTI15 event. On detection of the first rising edge on PE.15 pin all selected injected channels, which are two in this example (ADC channel11 and channel12), are converted and an interrupt is generated on JEOC flag rising at the end of all injected channels conversion. Both injected channels converted results are stored in ADC_InjectedConvertedValueTab table inside the interrupt routine. The procedure is repeated for injected channels on each EXTI15 event. The ADC1 clock is set to 12 MHz on Value line devices and to 14MHz on other devices.

Directory contents
  • ADC/ExtLinesTrigger/stm32f10x_conf.h Library Configuration file
  • ADC/ExtLinesTrigger/stm32f10x_it.c Interrupt handlers
  • ADC/ExtLinesTrigger/stm32f10x_it.h Interrupt handlers header file
  • ADC/ExtLinesTrigger/system_stm32f10x.c STM32F10x system source file
  • ADC/ExtLinesTrigger/main.c Main program
Hardware and Software environment
  • This example runs on STM32F10x Connectivity line, High-Density, Medium-Density, XL-Density, Medium-Density Value line, Low-Density and Low-Density Value line Devices.
  • This example has been tested with STMicroelectronics STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) evaluation boards and can be easily tailored to any other supported device and development board.
  • STM32100B-EVAL Set-up
    • Connect a known voltage, between 0-3.3V, to ADC Channel14 mapped on pin PC.04 (potentiometer RV2), ADC Channel4 mapped on pin PA.04, ADC Channel11 mapped on pin PC.01 and ADC Channel12 mapped on pin PC.02.
    • Connect a push-button to pin PE.11 (EXTI Line11) and another push-button to pin PE.15 (EXTI Line15).
      Note:
      Make shure that jumper JP3 is open.
  • STM32100E-EVAL Set-up
    • Connect a known voltage, between 0-3.3V, to ADC Channel14 mapped on pin PC.04 (potentiometer RV1), ADC Channel4 mapped on pin PA.04, ADC Channel11 mapped on pin PC.01 and ADC Channel12 mapped on pin PC.02.
    • Connect a push-button to pin PF.11 (EXTI Line11) and another push-button to pin PE.15 (EXTI Line15).
  • STM3210C-EVAL Set-up
    • Connect a known voltage, between 0-3.3V, to ADC Channel14 mapped on pin PC.04 (potentiometer RV1), ADC Channel4 mapped on pin PA.04, ADC Channel11 mapped on pin PC.01 and ADC Channel12 mapped on pin PC.02.
    • Connect a push-button to pin PE.11 (EXTI Line11) and another push-button to pin PE.15 (EXTI Line15).
  • STM3210E-EVAL Set-up
    • Connect a known voltage, between 0-3.3V, to ADC Channel14 mapped on pin PC.04 (potentiometer RV1), ADC Channel4 mapped on pin PA.04, ADC Channel11 mapped on pin PC.01 and ADC Channel12 mapped on pin PC.02.
    • Connect a push-button to pin PE.11 (EXTI Line11) and another push-button to pin PE.15 (EXTI Line15).
  • STM3210B-EVAL Set-up
    • Connect a known voltage, between 0-3.3V, to ADC Channel14 mapped on pin PC.04 (potentiometer RV1), ADC Channel4 mapped on pin PA.04, ADC Channel11 mapped on pin PC.01 and ADC Channel12 mapped on pin PC.02.
    • Connect a push-button to pin PE.11 (EXTI Line11) and another push-button to pin PE.15 (EXTI Line15).
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: ADC regular simultaneous dual mode example

  • STM32F10x Standard Peripheral's Examples
  • DMA_EXAMPLES

ADC regular simultaneous dual mode example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    ADC/RegSimul_DualMode/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the ADC regular simultaneous dual mode example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example describes how to use ADC1 and ADC2 in regular simultaneous dual mode. ADC1 is configured to convert channel14 and channel17 regular channels continuously. ADC2 is configured to convert channel11 and channel12 regular channels continuously. The connection between internal Vref and channel17 is enabled for ADC1.

Once the regular channels conversion is started by software, channel14 is converted on ADC1 and channel11 is converted on ADC2 on the same time. The 32bits conversion result is then stored on ADC1 DR register. The DMA will transfer this data which will be stored ADC_DualConvertedValueTab table. Consecutively to those conversion, channel17 is converted on ADC1 and channel12 on ADC2. The combined conversion result is also transferred by DMA to the same destination buffer.

The same procedure is repeated until the specified number of data to be transferred by DMA is reached.

The ADCs clocks are set to 14 MHz.

Directory contents
  • ADC/RegSimul_DualMode/stm32f10x_conf.h Library Configuration file
  • ADC/RegSimul_DualMode/stm32f10x_it.c Interrupt handlers
  • ADC/RegSimul_DualMode/stm32f10x_it.h Interrupt handlers header file
  • ADC/RegSimul_DualMode/system_stm32f10x.c STM32F10x system source file
  • ADC/RegSimul_DualMode/main.c Main program
Hardware and Software environment
  • This example runs on STM32F10x Connectivity line, High-Density, Medium-Density, XL-Density and Low-Density Devices.
  • This example has been tested with STMicroelectronics STM3210C-EVAL (Connectivity line), STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) evaluation boards and can be easily tailored to any other supported device and development board.
  • STM3210C-EVAL Set-up
    • Connect a known voltage, between 0-3.3V, to ADC Channel14 mapped on pin PC.04 (potentiometer RV1), ADC Channel11 mapped on pin PC.01 and ADC Channel12 mapped on pin PC.02.
  • STM3210E-EVAL Set-up
    • Connect a known voltage, between 0-3.3V, to ADC Channel14 mapped on pin PC.04 (potentiometer RV1), ADC Channel11 mapped on pin PC.01 and ADC Channel12 mapped on pin PC.02.
  • STM3210B-EVAL Set-up
    • Connect a known voltage, between 0-3.3V, to ADC Channel14 mapped on pin PC.04 (potentiometer RV1), ADC Channel11 mapped on pin PC.01 and ADC Channel12 mapped on pin PC.02.
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: ADC TIM trigger and auto-injection example

  • STM32F10x Standard Peripheral's Examples
  • DMA_EXAMPLES

ADC TIM trigger and auto-injection example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    ADC/TIMTrigger_AutoInjection/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the ADC TIM trigger and auto-injection example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example describes how to convert ADC regular group channels continuously using TIM1 external trigger and injected group channels using the auto-injected feature.

ADC1 is configured to convert on each TIM1 capture compare event ADC channel14. Each time an end of regular conversion occurs the DMA transfers the converted data from ADC1 DR register to the ADC_RegularConvertedValueTab table. Enabling the auto-injected feature, allows to convert automatically the injected channel ADC channel11 after the end of the regular channel14. An ADC interrupt is generated then by JEOC flag at the end of the injected channel conversion and in the interrupt routine the result is stored in the ADC_InjectedConvertedValueTab table. The procedure is repeated 32 times then the TIM1 peripheral is disabled and thus, no conversion will be done neither regular nor injected. TIM1 start conversion triggers can be visualized on oscilloscope on PA.08 and at the same time the toggle of pin PC.06 which indicates the automatic auto-injection conversion.

The ADC1 clock is set to 12 MHz on Value line devices and to 14MHz on other devices.

Directory contents
  • ADC/TIMTrigger_AutoInjection/stm32f10x_conf.h Library Configuration file
  • ADC/TIMTrigger_AutoInjection/stm32f10x_it.c Interrupt handlers
  • ADC/TIMTrigger_AutoInjection/stm32f10x_it.h Interrupt handlers header file
  • ADC/TIMTrigger_AutoInjection/system_stm32f10x.c STM32F10x system source file
  • ADC/TIMTrigger_AutoInjection/main.c Main program
Hardware and Software environment
  • This example runs on STM32F10x Connectivity line, High-Density, High-Density Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density and Low-Density Value line Devices.
  • This example has been tested with STMicroelectronics STM32100E-EVAL(High-Density Value line) STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) evaluation boards and can be easily tailored to any other supported device and development board.
  • STM32100E-EVAL Set-up
    • Connect a known voltage, between 0-3.3V, to ADC Channel14 mapped on pin PC.04 (potentiometer RV1) and ADC Channel11 mapped on pin PC.01
    • Connect PA.08 and PC.06 pins to an oscilloscope
  • STM32100B-EVAL Set-up
    • Connect a variable power supply 0-3.3V to ADC Channel14 mapped on pin PC.04 (potentiometer RV2) and ADC Channel11 mapped on pin PC.01
    • Connect PA.08 and PC.06 pins to an oscilloscope
  • STM3210C-EVAL Set-up
    • Connect a known voltage, between 0-3.3V, to ADC Channel14 mapped on pin PC.04 (potentiometer RV1) and ADC Channel11 mapped on pin PC.01
    • Connect PA.08 and PC.06 pins to an oscilloscope
  • STM3210E-EVAL Set-up
    • Connect a known voltage, between 0-3.3V, to ADC Channel14 mapped on pin PC.04 (potentiometer RV1) and ADC Channel11 mapped on pin PC.01
    • Connect PA.08 and PC.06 pins to an oscilloscope
  • STM3210B-EVAL Set-up
    • Connect a known voltage, between 0-3.3V, to ADC Channel14 mapped on pin PC.04 (potentiometer RV1) and ADC Channel11 mapped on pin PC.01
    • Connect PA.08 and PC.06 pins to an oscilloscope
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: Backup Data example

  • STM32F10x Standard Peripheral's Examples

Backup Data example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    BKP/Backup_Data/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the Backup Data example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example shows how to store user data in the Backup data registers. As the Backup (BKP) domain still powered by VBAT when VDD is switched off, its contents are not lost if a battery is connected to VBAT pin.

The program behaves as follows:

1. After startup the program checks if the board has been powered up. If yes, the values in the BKP data registers are checked:

  • if a battery is connected to the VBAT pin, the values in the BKP data registers are retained
  • if no battery is connected to the VBAT pin, the values in the BKP data registers are lost

2. After an external reset, the BKP data registers contents are not checked.

Four LEDs are used to monitor the system state as follows: 1. LD3 on / LD1 on: a Power On Reset occurred and the values in the BKP data registers are correct

2. LD3 on / LD2 on: a Power On Reset occurred and the values in the BKP data registers are not correct or they have not yet been programmed (if it is the first time the program is executed)

3. LD3 off / LD1 off / LD2 off: no Power On Reset occurred

4. LD4 on: program running

Directory contents
  • BKP/Backup_Data/stm32f10x_conf.h Library Configuration file
  • BKP/Backup_Data/stm32f10x_it.c Interrupt handlers
  • BKP/Backup_Data/stm32f10x_it.h Header for stm32f10x_it.c
  • BKP/Backup_Data/system_stm32f10x.c STM32F10x system source file
  • BKP/Backup_Data/main.c Main program
Hardware and Software environment
  • This example runs on STM32F10x Connectivity line, High-Density, Medium-Density, XL-Density, High-Density Value line, Medium-Density Value line, Low-Density and Low-Density Value line Devices.
  • This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) evaluation boards and can be easily tailored to any other supported device and development board. To select the STMicroelectronics evaluation board used to run the example, uncomment the corresponding line in stm32_eval.h file (under Utilities)
  • STM32100B-EVAL Set-up
    • Use LD1, LD2, LD3 and LD4 leds connected respectively to PC.06, PC.07, PC.08 and PC.09 pins
    • Use 3V battery on VBAT pin (set jumper JP9 in position 1-2)
  • STM3210C-EVAL Set-up
    • Use LD1, LD2, LD3 and LD4 leds connected respectively to PD.07, PD.13, PF.03 and PD.04 pins
    • Use 3V battery on VBAT pin (set jumper JP24 in position 1-2)
  • STM3210E-EVAL Set-up
    • Use LD1, LD2, LD3 and LD4 leds connected respectively to PF.06, PF0.7, PF.08 and PF.09 pins
    • Use 3V battery on VBAT pin (set jumper JP1 in position 1-2)
  • STM3210B-EVAL Set-up
    • Use LD1, LD2, LD3 and LD4 leds connected respectively to PC.06, PC.07, PC.08 and PC.09 pins
    • Use 3V battery on VBAT pin (set jumper JP11 in position 1-2)
  • STM32100E-EVAL Set-up
    • Use LD1, LD2, LD3 and LD4 leds connected respectively to PF.06, PF0.7, PF.08 and PF.09 pins
    • Use 3V battery on VBAT pin (set jumper JP1 in position 1-2)
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example
  • Power on/off the board and check that the BKP contents are not lost
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: BKP Tamper example

  • STM32F10x Standard Peripheral's Examples

BKP Tamper example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    BKP/Tamper/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the BKP Tamper example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example shows how to write/read data to/from Backup data registers and demonstrates the Tamper detection feature.

The associated firmware performs the following:

1. It configures the ANTI_TAMP pin to be active low, and enables the Tamper interrupt.

2. It writes the data to all Backup data registers, then check whether the data were correctly written. If yes, LED1 turns on, otherwise LED2 turns on.

3. On applying a low level on the ANTI_TAMP pin (PC.13), the Backup data registers are reset and the Tamper interrupt is generated. The corresponding ISR then checks whether the Backup data registers are cleared. If yes, LED3 on, otherwise LED4 turns on.

Directory contents
  • BKP/Tamper/stm32f10x_conf.h Library Configuration file
  • BKP/Tamper/stm32f10x_it.h Interrupt handlers header file
  • BKP/Tamper/stm32f10x_it.c Interrupt handlers
  • BKP/Tamper/main.h Main header file
  • BKP/Tamper/main.c Main program
  • BKP/Tamper/system_stm32f10x.c STM32F10x system source file
Hardware and Software environment
  • This example runs on STM32F10x Connectivity line, High-Density, Medium-Density, High-Density Value line, XL-Density, Medium-Density Value line, Low-Density and Low-Density Value line Devices.
  • This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) evaluation boards and can be easily tailored to any other supported device and development board. To select the STMicroelectronics evaluation board used to run the example, uncomment the corresponding line in stm32_eval.h file (under Utilities)
  • STM32100B-EVAL Set-up
    • Use LD1, LD2, LD3 and LD4 leds connected respectively to PC.06, PC.07, PC.08 and PC.09 pins
    • Use the Tamper push-button connected to pin PC.13. PC13 is already connected to VDD on the eval board.
  • STM3210C-EVAL Set-up
    • Use LD1, LD2, LD3 and LD4 leds connected respectively to PD.07, PD.13, PF.03 and PD.04 pins
    • Use the Tamper push-button connected to pin PC.13 (set jumper JP1 in position 2-3). PC13 is already connected to VDD on the eval board.
  • STM3210E-EVAL Set-up
    • Use LD1, LD2, LD3 and LD4 leds connected respectively to PF.06, PF0.7, PF.08 and PF.09 pins
    • Use the Tamper push-button connected to pin PC.13. PC13 is already connected to VDD on the eval board.
  • STM3210B-EVAL Set-up
    • Use LD1, LD2, LD3 and LD4 leds connected respectively to PC.06, PC.07, PC.08 and PC.09 pins
    • Use the Tamper push-button connected to pin PC.13. PC13 is already connected to VDD on the eval board.
  • STM32100E-EVAL Set-up
    • Use LD1, LD2, LD3 and LD4 leds connected respectively to PF.06, PF0.7, PF.08 and PF.09 pins
    • Use the Tamper push-button connected to pin PC.13. PC13 is already connected to VDD on the eval board.
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: Dual CAN example

  • STM32F10x Standard Peripheral's Examples

Dual CAN example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    CAN/DualCAN/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the Dual CAN example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example shows how to configure the CAN1 and CAN2 peripherals to send and receive CAN frames in normal mode. The sent frames are used to control Leds by pressing KEY or TAMPER push buttons:

  • When KEY button is pressed, LED1 is turned ON and CAN1 sends a message to CAN2, when CAN2 receives correctly this message LED4 is turned ON.
  • When TAMPER button is pressed, LED2 is turned ON and CAN2 sends a message to CAN1, when CAN1 receives correctly this message LED3 is turned ON.

The CAN1 and CAN2 are configured as follow:

  • Bit Rate = 1 Mbit/s
  • CAN Clock = external clock (HSE)
  • ID Filter = All identifiers are allowed
  • RTR = Data
  • DLC = 1 byte
  • Data: Led number that should be turned ON
    Note:
    user can select one from the preconfigured CAN baud rates from the private defines in main.c by uncommenting the desired define:
      #define CAN_BAUDRATE  1000      /* CAN baudrate = 1MBps   */
/* #define CAN_BAUDRATE  500*/  /* CAN baudrate = 500kBps */
/* #define CAN_BAUDRATE  250*/  /* CAN baudrate = 250kBps */
/* #define CAN_BAUDRATE  125*/  /* CAN baudrate = 125kBps */
/* #define CAN_BAUDRATE  100*/  /* CAN baudrate = 100kBps */
/* #define CAN_BAUDRATE  50*/   /* CAN baudrate = 50kBps  */
/* #define CAN_BAUDRATE  20*/   /* CAN baudrate = 20kBps  */
/* #define CAN_BAUDRATE  10*/   /* CAN baudrate = 10kBps  */
Directory contents
  • CAN/DualCAN/stm32f10x_conf.h Library Configuration file
  • CAN/DualCAN/stm32f10x_it.c Interrupt handlers
  • CAN/DualCAN/stm32f10x_it.h Interrupt handlers header file
  • CAN/DualCAN/main.c Main program
  • CAN/DualCAN/system_stm32f10x.c STM32F10x system source file
Hardware and Software environment
  • This example runs on STM32F10x Connectivity line Devices.
  • This example has been tested with STMicroelectronics STM3210C-EVAL (STM32F10x Connectivity line) evaluation board and can be easily tailored to any other supported device and development board. To select the STMicroelectronics evaluation board used to run the example, uncomment the corresponding line in stm32_eval.h file
  • STM3210C-EVAL Set-up
    • Use LED1, LED2, LED3 and LED4 connected respectively to PD.07, PD.13, PF.03 and PD.04 pins
    • Use Key Push Button connected to PB9
    • Use Tamper Push Button connected to PC13
    • Connect a female/female CAN cable between the CAN connectors (CN4 and CN3 on STM3210C-EVAL boards)
    • Connector 1 DB9_PIN2 to Connector 2 DB9_PIN2 (CAN_L)
    • Connector 1 DB9_PIN5 to Connector 2 DB9_PIN5 ( GND )
    • Connector 1 DB9_PIN7 to Connector 2 DB9_PIN7 (CAN_H)
    • JP6 or JP5 must be fitted.
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: CAN LoopBack example

  • STM32F10x Standard Peripheral's Examples

CAN LoopBack example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    CAN/LoopBack/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the CAN LoopBack example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example provides a description of how to set a communication with the CAN in loopback mode.

The CAN cell first performs a transmission and a reception of a standard data frame by polling at 125 Kbps. The received frame is checked and some LEDs light up to indicate whether the communication was successful. Then, an extended data frame is transmitted at 500 Kbps. Reception is done in the interrupt handler when the message becomes pending in the FIFO. Finally, the LEDs indicate if both transmission and reception have been successful.

User can select CAN1 or CAN2 cell using the private defines in main.c :

#define __CAN1_USED__
/* #define __CAN2_USED__*/
Note:
When using CAN2, please check that your device is Connectivity line.
Directory contents
  • CAN/LoopBack/stm32f10x_conf.h Library Configuration file
  • CAN/LoopBack/stm32f10x_it.c Interrupt handlers
  • CAN/LoopBack/stm32f10x_it.h Interrupt handlers header file
  • CAN/LoopBack/main.c Main program
  • CAN/LoopBack/system_stm32f10x.c STM32F10x system source file
Hardware and Software environment
  • This example runs on STM32F10x Connectivity line, High-Density, Medium-Density, XL-Density and Low-Density Devices.
  • This example has been tested with STMicroelectronics STM3210C-EVAL (Connectivity line), STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) evaluation boards and can be easily tailored to any other supported device and development board. To select the STMicroelectronics evaluation board used to run the example, uncomment the corresponding line in stm32_eval.h file
  • STM3210C-EVAL Set-up
    • Use LED1, LED2, LED3 and LED4 connected respectively to PD.07, PD.13, PF.03 and PD.04 pins
  • STM3210E-EVAL Set-up
    • Use LD1, LD2, LD3 and LD4 leds connected respectively to PF.06, PF0.7, PF.08 and PF.09 pins
  • STM3210B-EVAL Set-up
    • Use LD1, LD2, LD3 and LD4 leds connected respectively to PC.06, PC.07, PC.08 and PC.09 pins
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: CAN Networking example

  • STM32F10x Standard Peripheral's Examples

CAN Networking example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    CAN/Networking/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the CAN Networking example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example shows how to configure the CAN peripheral to send and receive CAN frames in normal mode. The sent frames are used to control Leds by pressing key push button.

The CAN serial communication link is a bus to which a number of units may be connected. This number has no theoretical limit. Practically the total number of units will be limited by delay times and/or electrical loads on the bus line.

This program behaves as follows:

  • After reset LED1 is ON
  • By Pressing on KEY Button : LED2 turns ON and all other Leds are OFF, on the N eval boards connected to the bus.
  • Press on KEY Button again to send CAN Frame to command LEDn+1 ON, all other Leds are OFF on the N eval boards.
Note:
This example is tested with a bus of 3 units. The same program example is loaded in all units to send and receive frames.
Any unit in the CAN bus may play the role of sender (by pressing KEY button) or receiver.

The CAN is configured as follow:

  • Bit Rate = 1 Mbit/s
  • CAN Clock = external clock (HSE)
    • ID Filter = All identifiers are allowed
    • RTR = Data
    • DLC = 1 byte
    • Data: Led number that should be turned ON

User can select CAN1 or CAN2 cell using the private defines in main.c :

#define __CAN1_USED__
/* #define __CAN2_USED__*/
Note:
When using CAN2, please check that you device is Connectivity line.
Directory contents
  • CAN/Networking/platform_config.h Hardware configuration header file
  • CAN/Networking/stm32f10x_conf.h Library Configuration file
  • CAN/Networking/stm32f10x_it.c Interrupt handlers
  • CAN/Networking/stm32f10x_it.h Interrupt handlers header file
  • CAN/Networking/main.c Main program
  • CAN/Networking/system_stm32f10x.c STM32F10x system source file
Hardware and Software environment
  • This example runs on STM32F10x Connectivity line, High-Density, Medium-Density, XL-Density and Low-Density Devices.
  • This example has been tested with STMicroelectronics STM3210C-EVAL (Connectivity line), STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) evaluation boards and can be easily tailored to any other supported device and development board. To select the STMicroelectronics evaluation board used to run the example, uncomment the corresponding line in CAN/Networking/platform_config.h or stm32_eval.h file
  • STM3210C-EVAL Set-up
    • Use LED1, LED2, LED3 and LED4 connected respectively to PD.07, PD.13, PF.03 and PD.04 pins
    • Use Key Push Button connected to PB9
    • Connect a female/female CAN cable between at least 2 EVAL CAN connectors (on STM3210E-EVAL (CN2)/ STM3210C-EVAL (CN3 or CN4) boards)
      • Connector 1 DB9_PIN2 to Connector 2 DB9_PIN2 (CAN_L)
        • Connector 1 DB9_PIN5 to Connector 2 DB9_PIN5 ( GND )
        • Connector 1 DB9_PIN7 to Connector 2 DB9_PIN7 (CAN_H)
          Note:
          JP6 or JP5 must be fitted.
  • STM3210E-EVAL Set-up
    • Use LED1, LD2, LED3 and LED4 leds connected respectively to PF.06, PF0.7, PF.08 and PF.09 pins
    • Use Key Push Button connected to PG8
    • Connect a female/female CAN cable between at least 2 EVAL CAN connectors (on STM3210B-EVAL (CN2)/ STM3210E-EVAL (CN4) boards)
      • Connector 1 DB9_PIN2 to Connector 2 DB9_PIN2 (CAN_L)
        • Connector 1 DB9_PIN5 to Connector 2 DB9_PIN5 ( GND )
        • Connector 1 DB9_PIN7 to Connector 2 DB9_PIN7 (CAN_H)
          Note:
          JP6 must be fitted.
  • STM3210B-EVAL Set-up
    • Use LED1, LED2, LED3 and LED4 leds connected respectively to PC.06, PC.07, PC.08 and PC.09 pins
    • Use Key Push Button connected to PB9
    • Connect a female/female CAN cable between at least 2 EVAL CAN connectors (on STM3210B-EVAL (CN2)/ STM3210E-EVAL (CN4) boards)
      • Connector 1 DB9_PIN2 to Connector 2 DB9_PIN2 (CAN_L)
        • Connector 1 DB9_PIN5 to Connector 2 DB9_PIN5 ( GND )
        • Connector 1 DB9_PIN7 to Connector 2 DB9_PIN7 (CAN_H)
          Note:
          JP3 must be fitted.
          Any unit in the CAN bus may play the role of sender (by pressing on the key) or receiver.
          How to use it ?
          In order to make the program work, you must do the following :

Copy all source files from this example folder to the template folder under Project

  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example
  • In the first time the all leds are OFF.
  • By Pressing on Key Button : LED1 turn ON and all other Leds are OFF, on the N eval-boards connected to the bus.
  • Press on Key Button again to send CAN Frame to command LEDn+1 ON, all other Leds are OFF on the N eval-boards.
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: CEC Data Exchange using Interrupt example

  • STM32F10x Standard Peripheral's Examples

CEC Data Exchange using Interrupt example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    CEC/DataExchangeInterrupt/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the CEC Data Exchange using Interrupt example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Description

This example provides a basic communication between two HDMI-CEC devices using interrupts. The first and second CEC device send TransmitBuffer to the CEC other device. The data received by the first and second CEC device are stored respectively in ReceiveBuffer. The data transfer is managed in CEC_IRQHandler in stm32f10x_it.c file.

The example illustrates the use of the CEC communication between two devices (2 x STM32100B-EVAL boards). Each device can send a frame to the other device by pressing the user key button on the EVAL board.

  • Edit CEC/stm32f10x_conf.h to select the the corresponding device (CEC_DEVICE1, CEC_DEVICE2).
Directory contents
  • CEC/DataExchangeInterrupt/stm32f10x_conf.h Library Configuration file
  • CEC/DataExchangeInterrupt/stm32f10x_it.h Interrupt handlers header file
  • CEC/DataExchangeInterrupt/stm32f10x_it.c Interrupt handlers
  • CEC/DataExchangeInterrupt/main.c Main program
  • CEC/DataExchangeInterrupt/system_stm32f10x.c STM32F10x system source file
Hardware and Software environment
  • This example runs on STM32F10x High-Density Value line, Medium-Density Value line and Low-Density Value line Devices.
  • This example has been tested with STMicroelectronics STM32100E-EVAL (STM32F10x High-Density Value line), STM32100B-EVAL (STM32F10x Medium-Density Value line) evaluation boards and can be easily tailored to any other supported device and development board.
  • Connect the boards by using one of the two following alternatives:
  • A HDMI Cables between all boards HDMI-CEC connectors (CN15 or CN16) on STM32100B-EVAL or between connectors (CN3 or CN4) on STM32100E-EVAL board.
  • Use a simple wire between all devices CEC Lines (PB.08), in this case don't forget to connect all boards grounds together.
Note:
  • You can also use more than two CEC devices as much as you want by changing only the Device address and selecting the corresponding followers.
  • You can use also the STM3210B-EVAL with the UM0685 associated firmware as a CEC device. This configuration is available only when use a simple wire connected between STM3210B-EVAL PA.00 and STM32100B-EVAL PB.08 or STM32100E-EVAL PB.08 pins. Don't forget to add a 27KOhm pull-up resistor on the STM3210B-EVAL PA.00 and to to connect all boards grounds together.
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Load the project image of First_Device (choose CEC_DEVICE1 when compiling) to the first board.
  • Load the project image of Second_Device (choose CEC_DEVICE2 when compiling) to the second board.
  • Run the example
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: CortexM3 BitBand example

  • STM32F10x Standard Peripheral's Examples

CortexM3 BitBand example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    CortexM3/BitBand/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the CortexM3 BitBand example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example shows how to use CortexM3 Bit-Band access to perform atomic read-modify-write and read operations on a variable in SRAM.

Directory contents
  • CortexM3/BitBand/stm32f10x_conf.h Library Configuration file
  • CortexM3/BitBand/stm32f10x_it.c Interrupt handlers
  • CortexM3/BitBand/stm32f10x_it.h Header for stm32f10x_it.c
  • CortexM3/BitBand/main.c Main program
  • CortexM3/BitBand/system_stm32f10x.c STM32F10x system source file
Hardware and Software environment
  • This example runs on STM32F10x Connectivity line, High-Density, Medium-Density, XL-Density, High-Density Value line, Medium-Density Value line, Low-Density and Low-Density Value line Devices.
  • This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) evaluation boards and can be easily tailored to any other supported device and development board.
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: CortexM3 Mode Privilege example

  • STM32F10x Standard Peripheral's Examples

CortexM3 Mode Privilege example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    CortexM3/Mode_Privilege/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the CortexM3 Mode Privilege example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example shows how to modify CortexM3 Thread mode privilege access and stack. CortexM3 Thread mode is entered on Reset, and can be entered as a result of an exception return.

The associated program is used to:

1. Switch the Thread mode stack from Main stack to Process stack

2. Switch the Thread mode from Privileged to Unprivileged

3. Switch the Thread mode from Unprivileged back to Privileged

To monitor the stack used and the privileged or unprivileged access level of code in Thread mode, a set of variables is available within the program. It is also possible to use the 'Cortex register' window of the debugger.

Directory contents
  • CortexM3/Mode_Privilege/stm32f10x_conf.h Library Configuration file
  • CortexM3/Mode_Privilege/stm32f10x_it.c Interrupt handlers
  • CortexM3/Mode_Privilege/stm32f10x_it.h Header for stm32f10x_it.c
  • CortexM3/Mode_Privilege/main.c Main program
  • CortexM3/Mode_Privilege/system_stm32f10x.c STM32F10x system source file
Hardware and Software environment
  • This example runs on STM32F10x Connectivity line, High-Density, Medium-Density, High-Density Value line, XL-Density, Medium-Density Value line, Low-Density and Low-Density Value line Devices.
  • This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) evaluation boards and can be easily tailored to any other supported device and development board.
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: CortexM3 MPU example

  • STM32F10x Standard Peripheral's Examples

CortexM3 MPU example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    CortexM3/MPU/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the CortexM3 MPU example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example presents the MPU features on STM32F10x XL-density devices and it can be easily ported to any other STM32 device supporting MPU.

The example purpose (ACCESS_PERMISSION) is to configure a memory region as privileged read only region and tries to perform read and write operation in different mode. If the access is permitted LED1 is toggling. If the access is not permitted, a memory management fault is generated and LED2 is ON. To generate an MPU memory fault exception due to an access right error, uncomment the following line "privilegedreadonlyarray[0] = 'e';" in the "accesspermission.c " file.

Directory contents
  • CortexM3/MPU/stm32f10x_conf.h Library Configuration file
  • CortexM3/MPU/stm32f10x_it.c Interrupt handlers
  • CortexM3/MPU/stm32f10x_it.h Header for stm32f10x_it.c
  • CortexM3/MPU/main.c Main program
  • CortexM3/MPU/system_stm32f10x.c STM32F10x system source file
  • CortexM3/MPU/accesspermission.c Cortex-M3 MPU regions Access rights file
Hardware and Software environment
  • This example runs on STM32F10x XL-density Devices.
  • This example has been tested with STMicroelectronics STM3210E-EVAL (High-Density and XL-Density) evaluation board and can be easily tailored to any other supported device and development board.
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain and setup your project configuration as follows
  • Add the required example files
    • accesspermission.c
      For RIDE and TrueSTUDIO toolchains you have to follow these instructions

RIDE

  • In the Application options -> script menu, set "Use Default Script File" to "No" and use "stm32f_flash_ROAarray.ld" as Script File. This linker is configured for STM32F. To use it with other STM32 devices. This linker should be updated.

TrueSTUDIO

  • In the project properties window, select C/C++ Build->settings node then the C Linker->General node and use "stm32f10x_flash_ROArray.ld" as Script File. This linker is configured for XL-density devices. To use it with other STM32 devices, this linker should be updated.
  • Rebuild all files and load your image into target memory
  • Run the example
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: CRC Calculation example

  • STM32F10x Standard Peripheral's Examples

CRC Calculation example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    CRC/CRC_Calculation/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the CRC Calculation example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example shows how to use CRC (cyclic redundancy check) calculation unit to get a CRC code of a given buffer of data word(32-bit), based on a fixed generator polynomial(0x4C11DB7).

Directory contents
  • CRC/CRC_Calculation/stm32f10x_conf.h Library Configuration file
  • CRC/CRC_Calculation/stm32f10x_it.c Interrupt handlers
  • CRC/CRC_Calculation/stm32f10x_it.h Header for stm32f10x_it.c
  • CRC/CRC_Calculation/main.c Main program
  • CRC/CRC_Calculation/system_stm32f10x.c STM32F10x system source file
Hardware and Software environment
  • This example runs on STM32F10x Connectivity line, High-Density, Medium-Density, High-Density Value line, XL-Density, Medium-Density Value line, Low-Density and Low-Density Value line Devices.
  • This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) evaluation boards and can be easily tailored to any other supported device and development board. To select the STMicroelectronics evaluation board used to run the example, uncomment the corresponding line in stm32_eval.h file (under Utilities)
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: DAC dual mode sine wave example

  • STM32F10x Standard Peripheral's Examples
  • DMA_EXAMPLES

DAC dual mode sine wave example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    DAC/DualModeDMA_SineWave/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the DAC dual mode sine wave example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example describes how to use DAC dual channel mode with DMA to generate sine waves on both DAC channels outputs.

Both DAC channels conversions are configured to be triggered by TIM2 TRGO triggers and without noise/triangle wave generation. 12bit right data alignment is selected since we choose to access DAC_DHR12RD register. DMA2 channel4 is configured to transfer continuously, word by word, a 32-word buffer to the dual DAC register DAC_DHR12RD.

The transferred 32buffer is made to have a sine wave generation on each DAC channel output. Both DAC channels are then enabled. Only DAC channel2 DMA capability is enabled.

Once TIM2 is enabled, each TIM2 TRGO update event generate a DMA request which transfer data to the dual DAC register and DAC conversion is started. The sine waves can be visualized by connecting both PA.04 and PA.05 pins to an oscilloscope.

Directory contents
  • DAC/DualModeDMA_SineWave/stm32f10x_conf.h Library Configuration file
  • DAC/DualModeDMA_SineWave/stm32f10x_it.c Interrupt handlers
  • DAC/DualModeDMA_SineWave/stm32f10x_it.h Header for stm32f10x_it.c
  • DAC/DualModeDMA_SineWave/main.c Main program
  • DAC/DualModeDMA_SineWave/system_stm32f10x.c STM32F10x system source file
Hardware and Software environment
  • This example runs on STM32F10x Connectivity line, High-Density, High-Density Value line, XL-Density, Medium-Density Value line and Low-Density Value line Devices.
  • This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line) and STM3210E-EVAL (High-Density and XL-Density) evaluation boards and can be easily tailored to any other supported device and development board.
  • STM32100E-EVAL Set-up
    • Connect PA.04 and PA.05 pins to an oscilloscope
  • STM32100B-EVAL Set-up
    • Connect PA.04 and PA.05 pins to an oscilloscope
  • STM3210C-EVAL Set-up
    • Only PA.04 can be monitored on an oscilloscope, PA.05 is used by other module (Motor control connector) that prevents to have DAC channel output on it. However, if you don't use Motor control connector, you can remove the 0ohm resistor R84 and thus PA.05 can be used for DAC output.
      Note:
      Make shure that jumper JP15 is open.
  • STM3210E-EVAL Set-up
    • Connect PA.04 and PA.05 pins to an oscilloscope
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: DAC one channel noise wave example

  • STM32F10x Standard Peripheral's Examples

DAC one channel noise wave example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    DAC/OneChannel_NoiseWave/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the DAC one channel noise wave example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example describes how to use one DAC channel to generate a signal with noise waves on DAC Channel1 output.

DAC channel1 conversion are configured to be triggered by software with noise wave generation.12bit left data alignment is selected since we choose to access DAC_DHR12L1 register. Bits 0 to 8 are masked for the Linear feedback shift register. DAC channel1 is then enabled. DAC Channel1 DHR12L1 register is configured to have an output voltage of VREF/2.

Software triggers are generated continuously in an infinite loop, and on each trigger the DAC channel1 start the conversion and calculate the noise value to apply on the DAC channel1 output.

The output signal with noise waves can be visualized by connecting PA.04 pin to an oscilloscope.

Directory contents
  • DAC/OneChannel_NoiseWave/stm32f10x_conf.h Library Configuration file
  • DAC/OneChannel_NoiseWave/stm32f10x_it.c Interrupt handlers
  • DAC/OneChannel_NoiseWave/stm32f10x_it.h Header for stm32f10x_it.c
  • DAC/OneChannel_NoiseWave/main.c Main program
  • DAC/OneChannel_NoiseWave/system_stm32f10x.c STM32F10x system source file
Hardware and Software environment
  • This example runs on STM32F10x Connectivity line, High-Density, XL-Density, High-Density Value line, Medium-Density Value line and Low-Density Value line Devices.
  • This example has been tested with STMicroelectronics STM32100B-EVAL (Medium-Density Value line),STM32100E-EVAL (High-Density Value line), STM3210C-EVAL (Connectivity line) and STM3210E-EVAL (High-Density and XL-Density) evaluation boards and can be easily tailored to any other supported device and development board.
  • STM32100B-EVAL Set-up
    • Connect PA.04 pin to an oscilloscope
      Note:
      JP2 should be open
  • STM3210C-EVAL Set-up
    • Connect PA.04 pin to an oscilloscope
  • STM3210E-EVAL Set-up
    • Connect PA.04 pin to an oscilloscope
  • STM32100E-EVAL Set-up
    • Connect PA.04 pin to an oscilloscope
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: DAC one channel DMA escalator example

  • STM32F10x Standard Peripheral's Examples
  • DMA_EXAMPLES

DAC one channel DMA escalator example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    DAC/OneChannelDMA_Escalator/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the DAC one channel DMA escalator example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example describes how to use one DAC channel mode with DMA to generate an escalator signal on DAC channel1 output.

DAC channel1 conversion is configured to be triggered by TIM6 TRGO triggers and without noise/triangle wave generation. 8bit right data alignment is selected since we choose to access DAC_DHR8R1 register. DMA2 channel3 is configured to transfer continuously, byte by byte, a 6-byte buffer to the DAC1 register DAC_DHR8R1.

The transferred 6bytes buffer is made to have an escalator signal on DAC channel1 output. DAC channel1 is then enabled. Once TIM6 is enabled, each TIM6 TRGO update event generate a DMA request which transfer data to the DAC1 register and DAC conversion is started. The escalator signal can be visualized by connecting PA.04 pin to an oscilloscope.

Directory contents
  • DAC/OneChannelDMA_Escalator/stm32f10x_conf.h Library Configuration file
  • DAC/OneChannelDMA_Escalator/stm32f10x_it.c Interrupt handlers
  • DAC/OneChannelDMA_Escalator/stm32f10x_it.h Header for stm32f10x_it.c
  • DAC/OneChannelDMA_Escalator/main.c Main program
  • DAC/OneChannelDMA_Escalator/system_stm32f10x.c STM32F10x system source file
Hardware and Software environment
  • This example runs on STM32F10x Connectivity line, High-Density, XL-Density, High-Density Value line, Medium-Density Value line and Low-Density Value line Devices.
  • This example has been tested with STMicroelectronics STM32100B-EVAL (Medium-Density Value line),STM32100E-EVAL (High-Density Value line), STM3210C-EVAL (Connectivity line) and STM3210E-EVAL (High-Density and XL-Density) evaluation boards and can be easily tailored to any other supported device and development board.
  • STM32100B-EVAL Set-up
    • Connect PA.04 pin to an oscilloscope
      Note:
      Make shure that jumper JP2 is open.
  • STM3210C-EVAL Set-up
    • Connect PA.04 pin to an oscilloscope
      Note:
      Make shure that jumper JP15 is open.
  • STM3210E-EVAL Set-up
    • Connect PA.04 pin to an oscilloscope
  • STM32100E-EVAL Set-up
    • Connect PA.04 pin to an oscilloscope
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: DAC two channels triangle wave example

  • STM32F10x Standard Peripheral's Examples

DAC two channels triangle wave example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    DAC/TwoChannels_TriangleWave/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the DAC two channels triangle wave example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example describes how to use two DAC channels to generate two different signals with triangle waves on each DAC Channel output.

DAC channels conversion are configured to be triggered by TIM2 TRGO with triangle wave generation. 12bit right data alignment is selected since we choose to access both DAC_DHR12R1 and DAC_DHR12R2 registers. A triangle amplitude of 2047 is selected for DAC channel1 and 1023 for DAC channel2. Both DAC channels are then enabled. DAC Channel1 DHR12R1 and DAC channel2 DHR12R2 registers are set to have a base output voltage of VREF/16 on each output.

Once TIM2 is enabled, each TIM2 TRGO update event trigger both DAC channels start of conversion. The triangle counter is incremented, added to the base value and applied to the corresponding DAC channel output. The same calculation is repeated on each trigger. The triangle waves can be visualized by connecting both PA.04 and PA.05 pins to an oscilloscope.

Directory contents
  • DAC/TwoChannels_TriangleWave/stm32f10x_conf.h Library Configuration file
  • DAC/TwoChannels_TriangleWave/stm32f10x_it.c Interrupt handlers
  • DAC/TwoChannels_TriangleWave/stm32f10x_it.h Header for stm32f10x_it.c
  • DAC/TwoChannels_TriangleWave/main.c Main program
  • DAC/TwoChannels_TriangleWave/system_stm32f10x.c STM32F10x system source file
Hardware and Software environment
  • This example runs on STM32F10x Connectivity line, High-Density, XL-Density, Medium-Density Value line, High-Density Value line and Low-Density Value line Devices.
  • This example has been tested with STMicroelectronics STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), STM32100E-EVAL (High-Density Value line) and STM3210E-EVAL (High-Density and XL-Density) evaluation boards and can be easily tailored to any other supported device and development board.
  • STM32100B-EVAL Set-up
    • Connect PA.04 and PA.05 pins to an oscilloscope
      Note:
      JP2 should be open
  • STM3210C-EVAL Set-up
    • Only PA.04 can be monitored on an oscilloscope, PA.05 is used by other module (Motor control connector) that prevents to have DAC channel output on it. However, if you don't use Motor control connector, you can remove the 0ohm resistor R84 and thus PA.05 can be used for DAC output.
      Note:
      Make shure that jumper JP15 is open.
  • STM3210E-EVAL Set-up
    • Connect PA.04 and PA.05 pins to an oscilloscope
  • STM32100E-EVAL Set-up
    • Connect PA.04 and PA.05 pins to an oscilloscope
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: I2C and M24CXX EEPROM communication example

  • STM32F10x Standard Peripheral's Examples
  • DMA_EXAMPLES

I2C and M24CXX EEPROM communication example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    I2C/EEPROM/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the I2C and M24CXX EEPROM communication example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example provides a basic example of how to use the I2C firmware library and an associate I2C EEPROM driver to communicate with an I2C EEPROM device (here the example is interfacing with M24CXX EEPROMs where XX={01, 02, 04, 08, 16, 32, 64}.

I2C peripheral is configured in Master transmitter during write operation and in Master receiver during read operation from I2C EEPROM.

The peripheral used is I2C1 but can be configured by modifying the defines values in stm32_eval_i2c_ee.c file. The speed is set to 200kHz and can be configured to other values by setting the define I2C_SPEED in stm32_eval_i2c_ee.h file. All transfers are performed through DMA access (except for One Byte Receiving case) which allows user application to perform parallel tasks while transfer to/from EEPROM is ongoing.

For M24C02 to M24C16 devices, one I2C EEPROM Block address where the program will write the buffer have to be selected from the four address available and defined in the stm32_eval_i2c_ee.h file.

For M24C32 and M24C64 devices all the memory is accessible through the two-bytes addressing mode and need to define block addresses. In this case, only the physical address has to be defined (according to the address pins (E0,E1 and E2) connection). This address is defined in stm32_eval_i2c_ee.c.h (default is 0xA0: E0, E1 and E2 tied to ground). The EEPROM addresses where the program start the write and the read operations is defined in the main.c file.

First, the content of Tx1_Buffer is written to the EEPROM_WriteAddress1 and the written data are read. The written and the read buffers data are then compared. Following the read operation, the program waits that the EEPROM reverts to its Standby state. A second write operation is, then, performed and this time, Tx2_Buffer is written to EEPROM_WriteAddress2, which represents the address just after the last written one in the first write. After completion of the second write operation, the written data are read. The contents of the written and the read buffers are compared.

Directory contents
  • I2C/EEPROM/stm32f10x_conf.h Library Configuration file
  • I2C/EEPROM/stm32f10x_it.c Interrupt handlers
  • I2C/EEPROM/stm32f10x_it.h Interrupt handlers header file
  • I2C/EEPROM/main.c Main program
  • I2C/EEPROM/system_stm32f10x.c STM32F10x system source file
Hardware and Software environment
  • This example runs on STM32F10x Connectivity line, High-Density, High-Density Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density and Low-Density Value line Devices.
  • This example has been tested with STM32100E-EVAL (STM32F10x High-Density Value line) evaluation board (implemented EEPROM is M24C64) and STM3210C-EVAL (STM32F10x Connectivity-Line) evaluation board (implemented EEPROM is M24C64) with no additional hardware, and can be easily tailored to any other supported device and development board.
  • STM32100E-EVAL Set-up
    • Make sure the jumper JP14 "ROM_WP" is fitted on the board.
    • No additional Hardware connections are needed.
  • STM3210C-EVAL Set-up
    • Make sure the Jumper JP17 "I2C_SCK" is fitted on the board.
    • Make sure the jumper JP9 "ROM_WP" is fitted on the board.
    • No additional Hardware connections are needed.
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: I2C and LM75 Temperature Sensor communication example

  • STM32F10x Standard Peripheral's Examples
  • DMA_EXAMPLES

I2C and LM75 Temperature Sensor communication example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    I2C/I2C_TSENSOR/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the I2C and LM75 Temperature Sensor communication
  *          example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example provides a description of how to use the I2C to communicate with an STLM75 (or a compatible device) I2C temperature sensor is mounted on the evaluation board and used to get instantaneous external temperature (-55ÝC to +125ÝC). Thanks to STM32 I2C SMBus feature, we can easily monitor the temperature variations. This is managed by the SMBus Alert which is generating a dedicated interrupt informing the system that the temperature is out of the selected ranges. The user can configure the TOS and THYS thanks to a dedicated define values in the code.

#define TEMPERATURE_THYS 31 #define TEMPERATURE_TOS 32

Directory contents
  • I2C/I2C_TSENSOR/stm32f10x_conf.h Library Configuration file
  • I2C/I2C_TSENSOR/stm32f10x_it.c Interrupt handlers
  • I2C/I2C_TSENSOR/stm32f10x_it.h Interrupt handlers header file
  • I2C/I2C_TSENSOR/main.c Main program
  • I2C/I2C_TSENSOR/system_stm32f10x.c STM32F10x system source file
Hardware and Software environment
  • This example runs on STM32F10x Connectivity line, High-Density, High-Density Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density and Low-Density Value line Devices.
  • This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density Value line), STM32100B-EVAL (Medium-Density Value line), STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) evaluation boards and can be easily tailored to any other supported device and development board.
  • STM3210E-EVAL Set-up
    Note:
    The jumper 11 must be fitted.
  • STM32100E-EVAL Set-up
    • Make sure that jumper 6 must be set in position 2<->3
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: I2C and STMPE811 IO Expander communication example

  • STM32F10x Standard Peripheral's Examples
  • DMA_EXAMPLES

I2C and STMPE811 IO Expander communication example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    I2C/IOExpander/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the I2C and STMPE811 IO Expander communication
  *          example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This firmware provides an example of configuring and using the IO Expander STMPE811 in order to control input Joystick IOs, output IOs and the Touch Screen feature. This example provides the elementary steps to control the following modules and use them in an application: The IO pins are used for:

  • Getting Joystick pins status (Polling and interrupt) only for STM3210C-EVAL.
  • The Touch Screen controller is used to get the Touched area detection information in a single point mode (Polling and interrupt).

The input information can be used either in Polling mode (uncomment the define #define IOE_POLLING_MODE) or in Interrupt mode (uncomment the define #define IOE_INTERRUPT_MODE). These defines are in main.h file.

After configuring the IO Expander modules and Interrupts (if needed), the output IOs are set to their default state. These operations are done by the functions: IOE_Config() and IOE_ITConfig(). If the IO Expander is not operational (or the I2C pins are not in the correct level) the IOE_Config() function returns a value different from 0 and a message is displayed on the LCD screen.

To get the status of an input:

  • IOE_JoyStickGetState() function is used for Joystick and returns a JOY_State_TypeDef value indicating the currently pressed key. This information is used to update the LCD display (the Joystick pressed key name is displayed) (only for STM3210C-EVAL).
  • IOE_TS_GetState() function is used for Touch Screen and returns a pointer to a structure holding the Touch Screen status (did a Touch Detection happened, X, Y, and Z positions). Only detection into the drawn rectangles areas is considered and used to update the LEDs status and LCD display (corresponding LED turned ON when its rectangle is touched, and the LED name is displayed on the LCD screen).

Besides, the examples checks the status of the other Push-Buttons implemented on the board (Key, Tamper and WakeUp push-buttons). They are checked in parallel with the IO Expander IOs and the LCD display and LEDs are updated according to the push buttons state.

Directory contents
  • I2C/IOExpander/stm32f10x_conf.h Library Configuration file
  • I2C/IOExpander/stm32f10x_it.c Interrupt handlers
  • I2C/IOExpander/stm32f10x_it.h Header for stm32f10x_it.c
  • I2C/IOExpander/main.c Main program
  • I2C/IOExpander/main.h Header for main.c
  • I2C/IOExpander/system_stm32f10x.c STM32F10x system source file
Hardware and Software environment
  • This example runs on STM32F10x Connectivity line, High-Density, High-Density Value line, Medium-Density, XL-Density, High-Density Value line, Medium-Density Value line, Low-Density and Low-Density Value line Devices.
  • This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density Value line) and STM3210C-EVAL (Connectivity line) evaluation boards and can be easily tailored to any other supported device and development board.
  • STM32100E-EVAL Set-up
    • Use two IO Expanders connected to I2C2 SCL and SDA pins PB10 and PB11 and interrupt output pin connected to PA12 (EXTI mode). IO Expander 1 address pins is connected to Gnd (address is 0x82).
    • Use LED1, LED2, LED3 and LED4 connected respectively to PF.06, PF.07, PF.08 and PF.09 pins
    • Use LCD connected to SPI3 remapped pins SCK, MISO and MOSI: PC10, PC11, PC12 and the CS pin PB2.
    • Use LCD Touch Screen module connected to IO Expander 1 pins IO_Pin_1, IO_Pin_2, IO_Pin_3 and IO_Pin_4 (respectively Y-, X-, Y+, X+ lines).
  • STM3210C-EVAL Set-up
    • Use two IO Expanders connected to I2C1 SCL and SDA pins PB6 and PB7 and interrupt output pin connected to PB14 (EXTI mode). IO Expander 1 address pins is connected to Gnd (address is 0x82) and IO Expander 2 address pins is connected to Vcc (address is 0x88).
    • Use LED1, LED2, LED3 and LED4 connected respectively to PD.07, PD.13, PF.03 and PD.04 pins
    • Use LCD connected to SPI3 remapped pins SCK, MISO and MOSI: PC10, PC11, PC12 and the CS pin PB2.
    • Use LCD Touch Screen module connected to IO Expander 1 pins IO_Pin_1, IO_Pin_2, IO_Pin_3 and IO_Pin_4 (respectively Y-, X-, Y+, X+ lines).
    • Use Joystick module connected to IO Expander 2 pins IO_Pin_3, IO_Pin_4, IO_Pin_5, IO_Pin_6 and IO_Pin_7 (respectively UP, Right, Left, Down and Center)
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: DMA in WFI mode example

  • STM32F10x Standard Peripheral's Examples
  • DMA_EXAMPLES

DMA in WFI mode example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    NVIC/DMA_WFIMode/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the NVIC DMA in WFI mode example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example shows how to enters the system to WFI mode with DMA transfer enabled and wake-up from this mode by the DMA End of Transfer interrupt.

In the associated software, the system clock is set to 72 MHz (24MHz on Value line), the DMA1 Channely is configured to transfer 10 data from the EVAL COM1 USART data register to a predefined buffer, DST_Buffer, and to generate an interrupt at the end of the transfer. The EVAL COM1 USART receives data from HyperTerminal. A LED1 is toggled with a frequency depending on the system clock, this is used to indicate whether the MCU is in WFI or RUN mode.

A falling edge on the selected EXTI Line will put the core in the WFI mode, causing the led pin to stop toggling. To wake-up from WFI mode you have to send the sequence (0, 1, 2, 3, 4, 5, 6, 7, 8, 9) from the Hyperterminal to the EVAL COM1 USART. These bytes will be transferred by the DMA from the EVAL COM1 receive data register to the predefined buffer, then generates an interrupt which exits the system from WFI mode. The LED1 restarts toggling and a LED2 will toggle if the buffer is correctly received else a LED3 is toggled.

Directory contents
  • NVIC/DMA_WFIMode/stm32f10x_conf.h Library Configuration file
  • NVIC/DMA_WFIMode/stm32f10x_it.c Interrupt handlers
  • NVIC/DMA_WFIMode/stm32f10x_it.h Interrupt handlers header file
  • NVIC/DMA_WFIMode/main.c Main program
  • NVIC/DMA_WFIMode/system_stm32f10x.c STM32F10x system source file
Hardware and Software environment
  • This example runs on STM32F10x Connectivity line, High-Density, High-Density Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density and Low-Density Value line Devices.
  • This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) evaluation boards and can be easily tailored to any other supported device and development board. To select the STMicroelectronics evaluation board used to run the example, uncomment the corresponding line in stm32_eval.h file (under Utilities)
  • STM32100E-EVAL Set-up
    • Use LED1, LED2, LED3 and LED4 leds connected respectively to PF.06, PF0.7, PF.08 and PF.09 pins
    • The USART1 signals (Rx, Tx) must be connected to a DB9 connector using a RS232 transceiver.
    • Connect a null-modem female/female RS232 cable between the DB9 connector, CN12 on STM3210E-EVAL board, and PC serial port.
    • Hyperterminal configuration:
      • Word Length = 8 Bits
      • One Stop Bit
      • No parity
      • BaudRate = 115200 baud
      • flow control: None
    • Use the Key push-button connected to pin PG.08 (EXTI Line8).
  • STM32100B-EVAL Set-up
    • Use LED1, LED2, LED3 and LED4 leds connected respectively to PC.06, PC.07, PC.08 and PC.09 pins
    • The USART1 signals (Rx, Tx) must be connected to a DB9 connector using a RS232 transceiver.
    • Connect a null-modem female/female RS232 cable between the DB9 connector, CN10 on STM32100B-EVAL board, and PC serial port.
    • Hyperterminal configuration:
      • Word Length = 8 Bits
      • One Stop Bit
      • No parity
      • BaudRate = 115200 baud
      • flow control: None
    • Use the Key push-button connected to pin PB.09 (EXTI Line9).
  • STM3210C-EVAL Set-up
    • Use LED1, LED2, LED3 and LED4 connected respectively to PD.07, PD.13, PF.03 and PD.04 pins
    • The USART2 signals (Rx, Tx) must be connected to a DB9 connector using a RS232 transceiver.
    • Connect a null-modem female/female RS232 cable between the DB9 connector, CN6 on STM3210C-EVAL board, and PC serial port.
    • Hyperterminal configuration:
      • Word Length = 8 Bits
      • One Stop Bit
      • No parity
      • BaudRate = 115200 baud
      • flow control: None
    • Use the Key push-button connected to pin PB.09 (EXTI Line9).
  • STM3210E-EVAL Set-up
    • Use LED1, LED2, LED3 and LED4 leds connected respectively to PF.06, PF0.7, PF.08 and PF.09 pins
    • The USART1 signals (Rx, Tx) must be connected to a DB9 connector using a RS232 transceiver.
    • Connect a null-modem female/female RS232 cable between the DB9 connector, CN12 on STM3210E-EVAL board, and PC serial port.
    • Hyperterminal configuration:
      • Word Length = 8 Bits
      • One Stop Bit
      • No parity
      • BaudRate = 115200 baud
      • flow control: None
    • Use the Key push-button connected to pin PG.08 (EXTI Line8).
  • STM3210B-EVAL Set-up
    • Use LED1, LED2, LED3 and LED4 leds connected respectively to PC.06, PC.07, PC.08 and PC.09 pins
    • The USART1 signals (Rx, Tx) must be connected to a DB9 connector using a RS232 transceiver.
    • Connect a null-modem female/female RS232 cable between the DB9 connector, CN6 on STM3210B-EVAL board, and PC serial port.
    • Hyperterminal configuration:
      • Word Length = 8 Bits
      • One Stop Bit
      • No parity
      • BaudRate = 115200 baud
      • flow control: None
    • Use the Key push-button connected to pin PB.09 (EXTI Line9).
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: SPI DMA example

  • STM32F10x Standard Peripheral's Examples
  • DMA_EXAMPLES

SPI DMA example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    SPI/DMA/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the SPI DMA example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example provides a description of how to set a communication between the two SPIs in simplex mode and performs a transfer from SPI_MASTER in polling mode to the SPI_SLAVE in DMA receive mode.

SPI_MASTER and SPI_SLAVE can be SPI1 and SPI2 or SPI3 and SPI2, depending on the STMicroelectronics EVAL board you are using.

Both SPIs are configured with 8bit data frame and a 18Mbit/s communication speed. SPI_MASTER is configured in bidirectional mode as transmitter only, while SPI_SLAVE is configured in bidirectional mode but as receiver only. Both master and slave NSS pins are managed by hardware. A dedicated DMA channel is configured for SPI_SLAVE Rx request to store received data in SPI_SLAVE_Buffer_Rx.

SPI_MASTER starts by transferring the first data, once this data is received by the SPI_SLAVE the RxNE request will trigger the DMA to transfer this data and store it into SPI_SLAVE_Buffer_Rx. The same action is done for the rest of the buffer.

Once the transfer is completed a comparison is done and TransferStatus gives the data transfer status where it is PASSED if transmitted and received data are the same otherwise it is FAILED.

Directory contents
  • SPI/DMA/platform_config.h Evaluation board specific configuration file
  • SPI/DMA/stm32f10x_conf.h Library Configuration file
  • SPI/DMA/stm32f10x_it.c Interrupt handlers
  • SPI/DMA/stm32f10x_it.h Interrupt handlers header file
  • SPI/DMA/main.c Main program
  • SPI/DMA/system_stm32f10x.c STM32F10x system source file
Hardware and Software environment
  • This example runs on STM32F10x Connectivity line, High-Density, High-Density Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density and Low-Density Value line Devices.
  • This example has been tested with STMicroelectronics STM3210C-EVAL (Connectivity line), STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) evaluation boards and can be easily tailored to any other supported device and development board. This example can't be tested with STMicroelectronics STM32100E-EVAL (STM32F10x High-Density Value line) and STM32100B-EVAL (STM32F10x Medium-Density Value line) evaluation boards. To select the STMicroelectronics evaluation board used to run the example,uncomment the corresponding line in SPI/DMA/platform_config.h file.
  • STM3210C-EVAL Set-up
    • Connect SPI2 NSS pin (PB.12) to SPI3 NSS pin (PA.04)
    • Connect SPI2 SCK pin (PB.13) to SPI3 SCK pin (PC.10)
    • Connect SPI2 MISO pin (PB.14) to SPI3 MOSI pin (PC.12)
      Note:
      In this case SPI3 pins are remapped by software.
  • STM3210E-EVAL Set-up
    • Connect SPI2 NSS pin (PB.12) to SPI1 NSS pin (PA.04)
    • Connect SPI2 SCK pin (PB.13) to SPI1 SCK pin (PA.05)
    • Connect SPI2 MISO pin (PB.14) to SPI1 MOSI pin (PA.07)
      Note:
      The jumper 14 (USB Disconnect) must be set in position 1<->2 in order to not interfer with SPI2 MISO pin PB14.
  • STM3210B-EVAL Set-up
    • Connect SPI2 NSS pin (PB.12) to SPI1 NSS pin (PA.04)
    • Connect SPI2 SCK pin (PB.13) to SPI1 SCK pin (PA.05)
    • Connect SPI2 MISO pin (PB.14) to SPI1 MOSI pin (PA.07)
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: TIM DMA example

  • STM32F10x Standard Peripheral's Examples
  • DMA_EXAMPLES

TIM DMA example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    TIM/DMA/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the TIM DMA example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example provides a description of how to use DMA with TIM1 Update request to transfer Data from memory to TIM1 Capture Compare Register3.

TIM1CLK = SystemCoreClock, Prescaler = 0, TIM1 counter clock = SystemCoreClock SystemCoreClock is set to 72 MHz for Low-density, Medium-density, High-density and Connectivity line devices. For Low-Density Value line, Medium-Density and High-Density Value line devices, SystemCoreClock is set to 24 MHz.

The objective is to configure TIM1 channel 3 to generate complementary PWM signal with a frequency equal to 17.57 KHz:

  • TIM1_Period = (SystemCoreClock / 17570) - 1 and a variable duty cycle that is changed by the DMA after a specific number of Update DMA request.

The number of this repetitive requests is defined by the TIM1 Repetion counter, each 3 Update Requests, the TIM1 Channel 3 Duty Cycle changes to the next new value defined by the SRC_Buffer.

Directory contents
  • TIM/DMA/stm32f10x_conf.h Library Configuration file
  • TIM/DMA/stm32f10x_it.c Interrupt handlers
  • TIM/DMA/stm32f10x_it.h Interrupt handlers header file
  • TIM/DMA/main.c Main program
  • TIM/DMA/system_stm32f10x.c STM32F10x system source file
Hardware and Software environment
  • This example runs on STM32F10x Connectivity line, High-Density, High-Density Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density and Low-Density Value line Devices.
  • This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) evaluation boards and can be easily tailored to any other supported device and development board.
  • STM32100E-EVAL, STM32100B-EVAL, STM3210C-EVAL, STM3210E-EVAL, STM32100E-EVAL and STM3210B-EVAL Set-up
    • Connect the following pins to an oscilloscope to monitor the different waveforms:
      • TIM1 CH3 (PA.10)
      • TIM1 CH3N (PB.15)
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: USART DMA Interrupt example

  • STM32F10x Standard Peripheral's Examples
  • DMA_EXAMPLES

USART DMA Interrupt example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    USART/DMA_Interrupt/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the USART DMA Interrupt example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example provides a basic communication between USARTy and USARTz using DMA capability, flags and interrupts. USARTy and USARTz can be USART1 and USART2 or USART2 and USART3, depending on the STMicroelectronics EVAL board you are using.

First, the DMA transfers data from TxBuffer2 buffer to USARTz Transmit data register, then this data is sent to USARTy. Data received by USARTy is transferred using RXNE flag and stored in RxBuffer1 then compared with the sent ones and the result of this comparison is stored in the "TransferStatus1" variable.

In the same time, the DMA transfers data from TxBuffer1 buffer to USARTy Transmit data register, then this data is sent to USARTz. Data received by USARTz is transferred using Receive interrupt and stored in RxBuffer2 then compared with the sent ones and the result of this comparison is stored in the "TransferStatus2" variable.

USARTy and USARTz configured as follow:

  • BaudRate = 230400 baud
  • Word Length = 8 Bits
  • One Stop Bit
  • No parity
  • Hardware flow control disabled (RTS and CTS signals)
  • Receive and transmit enabled
Directory contents
  • USART/DMA_Interrupt/platform_config.h Evaluation board specific configuration file
  • USART/DMA_Interrupt/stm32f10x_conf.h Library Configuration file
  • USART/DMA_Interrupt/stm32f10x_it.h Interrupt handlers header file
  • USART/DMA_Interrupt/stm32f10x_it.c Interrupt handlers
  • USART/DMA_Interrupt/main.c Main program
  • USART/DMA_Interrupt/system_stm32f10x.c STM32F10x system source file
Hardware and Software environment
  • This example runs on STM32F10x Connectivity line, High-Density, High-Density Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density and Low-Density Value line Devices.
  • This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) evaluation boards and can be easily tailored to any other supported device and development board. To select the STMicroelectronics evaluation board used to run the example, uncomment the corresponding line in USART/DMA_Interrupt/platform_config.h file
  • STM32100E-EVAL Set-up
    • Connect a null-modem female/female RS232 cable between CN10 (USART1) and CN5 (USART2).
      Note:
      Make sure that jumper JP5 is not open.
  • STM32100B-EVAL Set-up
    • Connect a null-modem female/female RS232 cable between CN10 (USART1) and CN9 (USART2).
      Note:
      In this case USART2 Tx and Rx pins are remapped by software on PD.05 and PD.06 respectively.
  • STM3210C-EVAL Set-up
    • Connect USART2 Tx pin (PD.05) to USART3 Rx pin (PC.11)
    • Connect USART2 Rx pin (PD.06) to USART3 Tx pin (PC.10)
      Note:
      In this case USART3 Tx and Rx pins are remapped by software. Make sure that jumpers JP19 and JP18 are open.
  • STM3210E-EVAL Set-up
    • Connect a null-modem female/female RS232 cable between CN12 (USART1) and CN8 (USART2).
  • STM3210B-EVAL Set-up
    • Connect a null-modem female/female RS232 cable between CN6 (USART1) and CN5 (USART2).
      • In this case USART2 Tx and Rx pins are remapped by software on PD.05 and PD.06 respectively.
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: USART DMA Polling example

  • STM32F10x Standard Peripheral's Examples
  • DMA_EXAMPLES

USART DMA Polling example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    USART/DMA_Polling/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the USART DMA Polling example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example provides a basic communication between USARTy and USARTz using DMA capability. USARTy and USARTz can be USART1 and USART2 or USART2 and USART3, depending on the STMicroelectronics EVAL board you are using.

First, the DMA transfers data from TxBuffer2 buffer to USARTz Transmit data register, then this data is sent to USARTy. Data received by USARTy is transferred by DMA and stored in RxBuffer1 then compared with the send ones and the result of this comparison is stored in the "TransferStatus1" variable.

In the same time, the DMA transfers data from TxBuffer1 buffer to USARTy Transmit data register, then this data is sent to USARTz. Data received by USARTz is transferred by DMA and stored in RxBuffer2 then compared with the send ones and the result of this comparison is stored in the "TransferStatus2" variable.

USARTy and USARTz configured as follow:

  • BaudRate = 230400 baud
  • Word Length = 8 Bits
  • One Stop Bit
  • No parity
  • Hardware flow control disabled (RTS and CTS signals)
  • Receive and transmit enabled
Directory contents
  • USART/DMA_Polling/platform_config.h Evaluation board specific configuration file
  • USART/DMA_Polling/stm32f10x_conf.h Library Configuration file
  • USART/DMA_Polling/stm32f10x_it.h Interrupt handlers header file
  • USART/DMA_Polling/stm32f10x_it.c Interrupt handlers
  • USART/DMA_Polling/main.c Main program
  • USART/DMA_Polling/system_stm32f10x.c STM32F10x system source file
Hardware and Software environment
  • This example runs on STM32F10x Connectivity line, High-Density, High-Density Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density and Low-Density Value line Devices.
  • This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) evaluation boards and can be easily tailored to any other supported device and development board. To select the STMicroelectronics evaluation board used to run the example, uncomment the corresponding line in USART/DMA_Polling/platform_config.h file
  • STM32100E-EVAL Set-up
    • Connect a null-modem female/female RS232 cable between CN10 (USART1) and CN5 (USART2).
      Note:
      Make sure that jumper JP5 is not open.
  • STM32100B-EVAL Set-up
    • Connect a null-modem female/female RS232 cable between CN10 (USART1) and CN9 (USART2).
      Note:
      In this case USART2 Tx and Rx pins are remapped by software on PD.05 and PD.06 respectively.
  • STM3210C-EVAL Set-up
    • Connect USART2 Tx pin (PD.05) to USART3 Rx pin (PC.11)
    • Connect USART2 Rx pin (PD.06) to USART3 Tx pin (PC.10)
      Note:
      In this case USART3 Tx and Rx pins are remapped by software. Make sure that jumpers JP19 and JP18 are open.
  • STM3210E-EVAL Set-up
    • Connect a null-modem female/female RS232 cable between CN12 (USART1) and CN8 (USART2).
  • STM3210B-EVAL Set-up
    • Connect a null-modem female/female RS232 cable between CN6 (USART1) and CN5 (USART2).
      • In this case USART2 Tx and Rx pins are remapped by software on PD.05 and PD.06 respectively.
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: DMA ADC1 TIM1 example

  • STM32F10x Standard Peripheral's Examples

DMA ADC1 TIM1 example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    DMA/ADC_TIM1/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the DMA ADC1 TIM1 example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example provides a description of how to use a DMA channel to transfer continuously a data from a peripheral (ADC1) to another peripheral (TIM1) supporting DMA transfer. The ADC channel14 is configured to be converted continuously. TIM1_CH1 is configured to generate a PWM signal on its output. The dedicated DMA1 channel5 is configured to transfer in circular mode the last ADC channel14 converted value to the TIM1_CCR1 register. The DMA channel request is driven by the TIM1 update event. The duty cycle of TIM1_CH1 output signal is then changed each time the input voltage value on ADC channel14 pin is modified. The duty cycle variation can be visualized on oscilloscope on the TIM1_CH1 pin PA.08 while changing the analog input on ADC channel14 using the potentiometer.

Directory contents
  • DMA/ADC_TIM1/stm32f10x_conf.h Library Configuration file
  • DMA/ADC_TIM1/stm32f10x_it.c Interrupt handlers
  • DMA/ADC_TIM1/stm32f10x_it.h Interrupt handlers header file
  • DMA/ADC_TIM1/main.c Main program
  • DMA/ADC_TIM1/system_stm32f10x.c STM32F10x system source file
Hardware and Software environment
  • This example runs on STM32F10x Connectivity line, High-Density, Medium-Density, XL-Density, High-Density Value line, Medium-Density Value line, Low-Density and Low-Density Value line Devices.
  • This example has been tested with STMicroelectronics STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) evaluation boards and can be easily tailored to any other supported device and development board.
  • STM32100B-EVAL Set-up
    • Connect a variable power supply 0-3.3V to ADC Channel14 mapped on pin PC.04 (potentiometer RV2)
    • Connect an oscilloscope to TIM1_CH1 (PA.08) pin
  • STM3210C-EVAL Set-up
    • Connect a variable power supply 0-3.3V to ADC Channel14 mapped on pin PC.04 (potentiometer RV1)
    • Connect an oscilloscope to TIM1_CH1 (PA.08) pin
  • STM3210E-EVAL Set-up
    • Connect a variable power supply 0-3.3V to ADC Channel14 mapped on pin PC.04 (potentiometer RV1)
    • Connect an oscilloscope to TIM1_CH1 (PA.08) pin
  • STM3210B-EVAL Set-up
    • Connect a variable power supply 0-3.3V to ADC Channel14 mapped on pin PC.04 (potentiometer RV1)
    • Connect an oscilloscope to TIM1_CH1 (PA.08) pin
  • STM32100E-EVAL Set-up
    • Connect a variable power supply 0-3.3V to ADC Channel14 mapped on pin PC.04 (potentiometer RV1)
    • Connect an oscilloscope to TIM1_CH1 (PA.08) pin
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: DMA FLASH to RAM example

  • STM32F10x Standard Peripheral's Examples

DMA FLASH to RAM example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    DMA/FLASH_RAM/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the DMA FLASH to RAM example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example provides a description of how to use a DMA channel to transfer a word data buffer from FLASH memory to embedded SRAM memory.

DMA1 Channel6 is configured to transfer the contents of a 32-word data buffer stored in Flash memory to the reception buffer declared in RAM.

The start of transfer is triggered by software. DMA1 Channel6 memory-to-memory transfer is enabled. Source and destination addresses incrementing is also enabled. The transfer is started by setting the Channel enable bit for DMA1 Channel6. At the end of the transfer a Transfer Complete interrupt is generated since it is enabled. Once interrupt is generated, the remaining data to be transferred is read which must be equal to 0. The Transfer Complete Interrupt pending bit is then cleared. A comparison between the source and destination buffers is done to check that all data have been correctly transferred.

Directory contents
  • DMA/FLASH_RAM/stm32f10x_conf.h Library Configuration file
  • DMA/FLASH_RAM/stm32f10x_it.c Interrupt handlers
  • DMA/FLASH_RAM/stm32f10x_it.h Interrupt handlers header file
  • DMA/FLASH_RAM/main.c Main program
  • DMA/FLASH_RAM/system_stm32f10x.c STM32F10x system source file
Hardware and Software environment
  • This example runs on STM32F10x Connectivity line, High-Density, Medium-Density, XL-Density,High-Density Value line, Medium-Density Value line, Low-Density and Low-Density Value line Devices.
  • This example has been tested with STMicroelectronics STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), STM3210E-EVAL (High-Density and XL-Density), STM32100E-EVAL (High-Density Value line) and STM3210B-EVAL (Medium-Density) evaluation boards and can be easily tailored to any other supported device and development board.
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: DMA FSMC example

  • STM32F10x Standard Peripheral's Examples

DMA FSMC example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    DMA/FSMC/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the DMA FSMC example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example provides a description of how to use two DMA channels to transfer a word data buffer from Flash memory to external SRAM memory and to recuperate the written data from external SRAM to be stored in internal SRAM.

DMA2 Channel5 is configured to transfer, word by word, the contents of a 32-word data buffer stored in Flash memory to the external SRAM memory interfaced by FSMC. The start of transfer is triggered by software. DMA2 Channel5 memory-to-memory transfer is enabled. Source and destination address incrementing is also enabled. The transfer is started by setting the Channel enable bit for DMA2 Channel5. A polling on the Transfer Complete flag is done to check the end of transfer. The DMA2 Channel5 Transfer complete flag is then cleared.

DMA1 Channel3 is configured to transfer, byte by byte, the contents of the first 128Bytes of external SRAM to the internal SRAM memory. The start of transfer is triggered by software. DMA1 Channel3 memory-to-memory transfer is enabled. Source and destination address incrementing is also enabled. The transfer is started by setting the Channel enable bit for DMA1 Channel3. A polling on the Transfer Complete flag is done to check the end of transfer.

A comparison between the source and destination buffers is done to check that all data have been correctly transferred.

Directory contents
  • DMA/FSMC/stm32f10x_conf.h Library Configuration file
  • DMA/FSMC/stm32f10x_it.c Interrupt handlers
  • DMA/FSMC/stm32f10x_it.h Interrupt handlers header file
  • DMA/FSMC/main.c Main program
  • DMA/FSMC/system_stm32f10x.c STM32F10x system source file
Hardware and Software environment
  • This example runs only on STM32F10x High-Density, High-Density Value line and XL-Density Devices.
  • This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density Value line) and STM3210E-EVAL (High-Density and XL-Density) evaluation boards and can be easily tailored to any other supported device and development board.
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: DMA I2C to RAM example

  • STM32F10x Standard Peripheral's Examples

DMA I2C to RAM example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    DMA/I2C_RAM/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the DMA I2C to RAM example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example provides a description of how to use two DMA channels to transfer a data buffer from memory to I2C2 through I2C1.

I2C1 is set as the master transmitter and I2C2 as the slave receiver. DMA1 Channel5 is configured to store the data received from I2C2 into the Rx buffer (reception buffer). DMA1 Channel6 is configured to transfer data from the Tx buffer (transmission buffer) to the I2C1 DR register. After the generation of the Start condition and once the slave address has been acknowledged, DMA capability is enabled for both I2C1 and I2C2. As soon as the two I2C DMAEN bits are set in the I2C1_CR2 and I2C2_CR2 registers, the transmission of the Tx buffer is started by DMA1 Channel5 and at the same time the data received on I2C2 is stored in Rx buffer using DMA1 Channel6 . The transmitted and the received buffers are compared to check that all data have been correctly transferred.

Directory contents
  • DMA/I2C_RAM/stm32f10x_conf.h Library Configuration file
  • DMA/I2C_RAM/stm32f10x_it.c Interrupt handlers
  • DMA/I2C_RAM/stm32f10x_it.h Interrupt handlers header file
  • DMA/I2C_RAM/main.c Main program
  • DMA/I2C_RAM/system_stm32f10x.c STM32F10x system source file
Hardware and Software environment
  • This example runs on STM32F10x Connectivity line, High-Density, Medium-Density, XL-Density, High-Density Value line, Medium-Density Value line, Low-Density and Low-Density Value line Devices.
  • This example has been tested with STMicroelectronics STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) evaluation boards and can be easily tailored to any other supported device and development board. This example can't be tested with STMicroelectronics STM3210C-EVAL (STM32F10x Connectivity-Line) evaluation boards since the I2C2 pins (PB10 and PB11) are already used by Ethernet PHY module. This example can't be tested with STMicroelectronics STM32100B-EVAL (STM32F10x Medium-Density Value line) and STM32100E-EVAL (High-Density Value line) evaluation boards since the I2C1/I2C2 pins (PB6/PB10 and PB7/PB11) are already used by HDMI-CEC module.
  • STM3210E-EVAL Set-up
    • Connect I2C1 SCL pin (PB.06) to I2C2 SCL pin (PB.10)
    • Connect I2C1 SDA pin (PB.07) to I2C2 SDA pin (PB.11)
    • Check that a pull-up resistor is connected on one I2C SDA pin
    • Check that a pull-up resistor is connected on one I2C SCL pin
  • STM3210B-EVAL Set-up
    • Connect I2C1 SCL pin (PB.06) to I2C2 SCL pin (PB.10)
    • Connect I2C1 SDA pin (PB.07) to I2C2 SDA pin (PB.11)
    • Check that a pull-up resistor is connected on one I2C SDA pin
    • Check that a pull-up resistor is connected on one I2C SCL pin
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: DMA SPI to RAM example

  • STM32F10x Standard Peripheral's Examples

DMA SPI to RAM example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    DMA/SPI_RAM/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the DMA SPI to RAM example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example provides a description of how to use four DMA channels to transfer a data buffer from memory to SPI_SLAVE through SPI_MASTER and a second data buffer from memory to SPI_MASTER through SPI_SLAVE in full-duplex mode. SPI_MASTER and SPI_SLAVE can be SPI1 and SPI2 or SPI3 and SPI2, depending on the STMicroelectronics EVAL board you are using.

For each SPI the NSS pin is configured by software (thus NSS pin is free for GPIO use) and DMA Tx/Rx requests are enabled.

In this example both transmission and reception are managed through DMA and the received data are stored into buffers declared in the SRAM. The DMA channels involved in this transfer depend on the used SPIs (for more details please refer to platform_config.h file).

A polling on all Transfer complete flags are done for all used DMA channels to check the end of all DMA channels transfers. The last received data on SPI_MASTER and SPI_SLAVE are the CRC values sent by each SPI to the other. The transmitted and received buffers are compared to check that all data have been correctly transferred.

Directory contents
  • DMA/SPI_RAM/platform_config.h Evaluation board specific configuration file
  • DMA/SPI_RAM/stm32f10x_conf.h Library Configuration file
  • DMA/SPI_RAM/stm32f10x_it.c Interrupt handlers
  • DMA/SPI_RAM/stm32f10x_it.h Interrupt handlers header file
  • DMA/SPI_RAM/main.c Main program
  • DMA/SPI_RAM/system_stm32f10x.c STM32F10x system source file
Hardware and Software environment
  • This example runs on STM32F10x Connectivity line, High-Density, Medium-Density, XL-Density, High-Density Value line, Medium-Density Value line, Low-Density and Low-Density Value line Devices.
  • This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density Value line) STM32100B-EVAL (Medium-Density Value line), STM32100E-EVAL (High-Density Value line), STM3210C-EVAL (Connectivity line), STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) evaluation boards and can be easily tailored to any other supported device and development board.
  • STM32100E-EVAL Set-up
    • Connect SPI1 SCK pin (PA.05) to SPI2 SCK pin (PB.13)
    • Connect SPI1 MISO pin (PA.06) to SPI2 MISO pin (PB.14)
    • Connect SPI1 MOSI pin (PA.07) to SPI2 MOSI pin (PB.15)
  • STM32100B-EVAL Set-up
    • Connect SPI1 SCK pin (PA.05) to SPI2 SCK pin (PB.13)
    • Connect SPI1 MISO pin (PA.06) to SPI2 MISO pin (PB.14)
    • Connect SPI1 MOSI pin (PA.07) to SPI2 MOSI pin (PB.15)
  • STM3210C-EVAL Set-up
    • Connect SPI3 SCK pin (PC.10) to SPI2 SCK pin (PB.13)
    • Connect SPI3 MISO pin (PC.11) to SPI2 MISO pin (PB.14)
    • Connect SPI3 MOSI pin (PC.12) to SPI2 MOSI pin (PB.15)
      Note:
      In this case SPI3 pins are remapped by software.
  • STM3210E-EVAL Set-up
    • Connect SPI1 SCK pin (PA.05) to SPI2 SCK pin (PB.13)
    • Connect SPI1 MISO pin (PA.06) to SPI2 MISO pin (PB.14)
    • Connect SPI1 MOSI pin (PA.07) to SPI2 MOSI pin (PB.15)
      Note:
      The jumper 14 (USB Disconnect) must be set in position 1<->2 in order to not interfer with SPI2 MISO pin PB14.
  • STM3210B-EVAL Set-up
    • Connect SPI1 SCK pin (PA.05) to SPI2 SCK pin (PB.13)
    • Connect SPI1 MISO pin (PA.06) to SPI2 MISO pin (PB.14)
    • Connect SPI1 MOSI pin (PA.07) to SPI2 MOSI pin (PB.15)
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: EXTI configuration example

  • STM32F10x Standard Peripheral's Examples

EXTI configuration example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    EXTI/EXTI_Config/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the EXTI configuration example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example shows how to configure external interrupt lines. In this example, 2 EXTI lines (EXTI0 and EXTI8 or EXTI9) are configured to generate an interrupt on each rising or falling edge. In the interrupt routine a led connected to a specific GPIO pin is toggled.

In this example:

  • EXTI0 is mapped to PA.00
  • EXTI8 is mapped to PG.08
  • EXTI9 is mapped to PB.09

After EXTI configuration, a software interrupt is generated on the EXTI0 toggles LED1. After that, when rising edge is detected on EXTI0, LED1 toggles when falling edge is detected on EXTI8, LED2 toggles when falling edge is detected on EXTI9, LED2 toggles

If any STM3210XX-EVAL is used, when Wakeup push-button is pressed, LED1 toggles when Key push-button is pressed, LED2 toggles

In this example, EXTI0_Config() function can be substituted by STM_EVAL_PBInit(Button_WAKEUP, Mode_EXTI) and EXTI9_5_Config() by STM_EVAL_PBInit(Button_KEY, Mode_EXTI) provided in the STM3210XX-EVAL driver.

Directory contents
  • EXTI/EXTI_Config/stm32f10x_conf.h Library Configuration file
  • EXTI/EXTI_Config/stm32f10x_it.h Interrupt handlers header file
  • EXTI/EXTI_Config/stm32f10x_it.c Interrupt handlers
  • EXTI/EXTI_Config/main.c Main program
  • EXTI/EXTI_Config/system_stm32f10x.c STM32F10x system source file
Hardware and Software environment
  • This example runs on STM32F10x Connectivity line, High-Density, High-Density Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density and Low-Density Value line Devices.
  • This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) evaluation boards and can be easily tailored to any other supported device and development board. To select the STMicroelectronics evaluation board used to run the example, uncomment the corresponding line in stm32_eval.h file (under Utilities)
  • STM32100E-EVAL Set-up
    • Use LED1 and LED2 connected to PF.06 and PF.07 pin
    • Use the Key push-button connected to pin PG.08 (EXTI Line8).
    • Use the Wakeup push-button connected to pin PA.00 (EXTI Line0).
      Note:
      the jumper JP4 must be not fit to be able to use the Wakeup push-button
  • STM32100B-EVAL Set-up
    • Use LED1 and LED2 connected to PC.06 and PC.07 pin
    • Use the Key push-button connected to pin PB.09 (EXTI Line9).
    • Use the Wakeup push-button connected to pin PA.00 (EXTI Line0).
  • STM3210C-EVAL Set-up
    • Use LED1 and LED2 connected to PD.07 and PD.13 pin
    • Use the Key push-button connected to pin PB.09 (EXTI Line9).
    • Use the Wakeup push-button connected to pin PA.00 (EXTI Line0). Make sure that the Jumper 14 is in position 2<->3.
  • STM3210E-EVAL Set-up
    • Use LED1 and LED2 connected to PF.06 and PF.07 pin
    • Use the Key push-button connected to pin PG.08 (EXTI Line8).
    • Use the Wakeup push-button connected to pin PA.00 (EXTI Line0).
      Note:
      the jumper JP4 must be not fit to be able to use the Wakeup push-button
  • STM3210B-EVAL Set-up
    • Use LED1 and LED2 connected to PC.06 and PC.07 pin
    • Use the Key push-button connected to pin PB.09 (EXTI Line9).
    • Use the Wakeup push-button connected to pin PA.00 (EXTI Line0).
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: FLASH Program example

  • STM32F10x Standard Peripheral's Examples

FLASH Program example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    FLASH/Program/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the FLASH Program example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example provides a description of how to program the STM32F10x FLASH.

After Reset, the Flash memory Program/Erase Controller is locked. To unlock it, the FLASH_Unlock function is used. Before programming the desired addresses, an erase operation is performed using the flash erase page feature. The erase procedure starts with the calculation of the number of pages to be used. Then all these pages will be erased one by one by calling FLASH_ErasePage function.

Once this operation is finished, the programming operation will be performed by using the FLASH_ProgramWord function. The written data is then checked and the result of the programming operation is stored into the MemoryProgramStatus variable.

Directory contents
  • FLASH/Program/stm32f10x_conf.h Library Configuration file
  • FLASH/Program/stm32f10x_it.h Interrupt handlers header file
  • FLASH/Program/stm32f10x_it.c Interrupt handlers
  • FLASH/Program/main.c Main program
  • FLASH/Program/system_stm32f10x.c STM32F10x system source file
Hardware and Software environment
  • This example runs on STM32F10x Connectivity line, High-Density, Medium-Density, XL-Density, High-Density Value line, Medium-Density Value line, Low-Density and Low-Density Value line Devices.
  • This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) evaluation boards and can be easily tailored to any other supported device and development board.
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: XL-Density devices FLASH Dual Boot capability example

  • STM32F10x Standard Peripheral's Examples

XL-Density devices FLASH Dual Boot capability example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    FLASH/Dual_Boot/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the XL-Density devices FLASH Dual Boot capability example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example demonstrates the dual Flash boot capability of XL-Density devices: boot from Flash memory Bank1 or Bank2.

At startup, if BFB2 option bit is reset and the boot pins are in the boot from main Flash memory configuration, the device boots from Flash memory Bank1 or Bank2, depending on the activation of the bank. The active banks are checked in the following order: Bank2, followed by Bank1. The active bank is identified by the value programmed at the base address of the bank (corresponding to the initial stack pointer value in the interrupt vector table). For further details, please refer to AN2606 "STM32 microcontroller system memory boot mode."

To demonstrate this feature, this example provides two programs:

  • 1st program will be loaded in Flash Bank1 (starting from @ 0x08000000), for this you have to enable BOOT_FROM_BANK1 define in main.c
  • 2nd program will be loaded in Flash Bank2 (starting from @ 0x08080000), for this you have to enable BOOT_FROM_BANK2 define in main.c

Once these two programs are loaded and boot pins set in boot from Flash memory, after reset the device will boot from Bank1 (default). Then you have to follow the instructions provided on the LCD:

  • "Joystick-DOWN: reset BFB2 bit to Boot from Bank2" => when pushing the Joystick DOWN button, BFB2 option bit will be reset then a system (SW) reset will be generated. After startup from reset, the device will boot from Bank2.
    • Note: when booting from Bank2 the same menu will be displayed
  • "Joystick-UP: set BFB2 bit to Boot from Bank1" => when pushing the Joystick UP button, BFB2 option bit will be set then a system (SW) reset will be generated. After startup from reset, the device will boot from Bank1.
  • "Joystick-SEL: program to 0x0 the base @ of Bank1/2" => when pushing the Joystick SEL button, the content of address 0x08080000 and 0x08000000 will be programmed to 0x0.
    • If the program was previously booting from Bank2 (i.e. BFB2 bit is reset), in this case after reset no program is executed and the Bootloader code is executed instead.
    • If the program was previously booting from Bank1 (i.e. BFB2 bit is set), in this case after reset no program is executed.
    • You have to load again the two programs to Bank1 and Bank2.

Important Note ================= When BFB2 bit is cleared and Bank2 or/and Bank1 contain valid user application code, the Bootloader will always jump to this code and never continue normal code execution (i.e. it’s no more possible to use the Bootloader for code upgrade and option bytes programming). As consequence, if the user has cleared BFB2 bit (to boot from Bank2), in order to be able to execute the embedded Bootloader code he has to:

  • either, set BFB2 bit to 1
  • or, program the content of address 0x08080000 and 0x08000000 to 0x0 => This example allows performing the two actions described above.
Directory contents
  • FLASH/Dual_Boot/stm32f10x_conf.h Library Configuration file
  • FLASH/Dual_Boot/stm32f10x_it.h Interrupt handlers header file
  • FLASH/Dual_Boot/stm32f10x_it.c Interrupt handlers
  • FLASH/Dual_Boot/main.c Main program
  • FLASH/Dual_Boot/system_stm32f10x.c STM32F10x system source file
Hardware and Software environment
  • This example runs only on STM32F10x XL-Density Devices.
  • This example has been tested with STMicroelectronics STM3210E-EVAL (XL-Density) evaluation board and can be easily tailored to any development board.
How to use it ?

In order to load the IAP code, you have to do the following:

  • EWARM:
    • Open the Project.eww workspace
    • In the workspace toolbar select the project config:
      • STM32F10X_XL_BANK1: to load the program in Flash bank1 (BOOT_FROM_BANK1 already defined in the project preprocessor)
      • STM32F10X_XL_BANK2: to load the program in Flash bank2 (BOOT_FROM_BANK2 already defined in the project preprocessor)
    • Rebuild all files: Project->Rebuild all
    • Load project image: Project->Debug
    • Run program: Debug->Go(F5)
  • HiTOP
    • Open the HiTOP toolchain.
    • Browse to open: -STM32F10X_XL_BANK1.htp: to load the program in Flash bank1 (BOOT_FROM_BANK1 already defined in the project preprocessor) -STM32F10X_XL_BANK2.htp: to load the program in Flash bank2 (BOOT_FROM_BANK2 already defined in the project preprocessor)
      • A "Download application" window is displayed, click "cancel".
      • Rebuild all files: Project->Rebuild all
      • Load project image : Click "ok" in the "Download application" window.
      • Run the "RESET_GO_MAIN" script to set the PC at the "main"
      • Run program: Debug->Go(F5).
  • MDK-ARM
    • Open Project.uvproj project
    • In the build toolbar select the project config:
      • STM32F10X_XL_BANK1: to load the program in Flash bank1 (BOOT_FROM_BANK1 already defined in the project preprocessor)
      • STM32F10X_XL_BANK2: to load the program in Flash bank2 (BOOT_FROM_BANK2 already defined in the project preprocessor)
    • Rebuild all files: Project->Rebuild all target files
    • Load project image: Debug->Start/Stop Debug Session
    • Run program: Debug->Run (F5)
  • TrueSTUDIO
    • Open the TrueSTUDIO toolchain.
    • Click on File->Switch Workspace->Other and browse to TrueSTUDIO workspace directory.
    • Click on File->Import, select General->'Existing Projects into Workspace' and then click "Next".
    • Browse to the TrueSTUDIO workspace directory and select the project:
      • STM32F10X_XL_BANK1: to load the program in Flash bank1 (BOOT_FROM_BANK1 already defined in the project preprocessor)
      • STM32F10X_XL_BANK2: to load the program in Flash bank2 (BOOT_FROM_BANK2 already defined in the project preprocessor)
    • Under Windows->Preferences->General->Workspace->Linked Resources, add a variable path named "CurPath" which points to the folder containing "Libraries", "Project" and "Utilities" folders.
    • Rebuild all project files: Select the project in the "Project explorer" window then click on Project->build project menu.
    • Run program: Select the project in the "Project explorer" window then click Run->Debug (F11)
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: FLASH Write Protection example

  • STM32F10x Standard Peripheral's Examples

FLASH Write Protection example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    FLASH/Write_Protection/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the FLASH Write Protection example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example provides a description of how to enable and disable the write protection for the STM32F10x FLASH:

  • Enable Write protection: To enable the Write Protection, uncomment the line "#define WRITE_PROTECTION_ENABLE" in main.c file. To protect a set of pages, the user has to call the function FLASH_EraseOptionBytes to erase all the option bytes then to call the function FLASH_EnableWriteProtection. The parameter of the later function will define the number of pages to be protected (The desired pages and already protected pages). To load the new option byte values, a system Reset is necessary, for this, the function NVIC_SystemReset() is used.
  • Disable Write protection: To disable the Write Protection, uncomment the line "#define WRITE_PROTECTION_DISABLE" in main.c file. To disable the write protection of the STM32F10x Flash, an erase of the Option Bytes is necessary by the function FLASH_EraseOptionBytes, then call the function FLASH_EnableWriteProtection to protect the pags that are already protected. To load the new option byte values, a system Reset is necessary, for this, the function NVIC_SystemReset() is used.
  • Program the selected pages: To program the desired pages (if the flash is not write protected) uncomment the line "#define FLASH_PAGE_PROGRAM" in main.c file.

If the desired pages are not write protected, an erase and a write operation are performed.

Directory contents
  • FLASH/Write_Protection/stm32f10x_conf.h Library Configuration file
  • FLASH/Write_Protection/stm32f10x_it.h Interrupt handlers header file
  • FLASH/Write_Protection/stm32f10x_it.c Interrupt handlers
  • FLASH/Write_Protection/main.c Main program
  • FLASH/Write_Protection/system_stm32f10x.c STM32F10x system source file
Hardware and Software environment
  • This example runs on STM32F10x Connectivity line, High-Density, Medium-Density, High-Density Value line, XL-Density, Medium-Density Value line, Low-Density and Low-Density Value line Devices.
  • This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) evaluation boards and can be easily tailored to any other supported device and development board.
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: FSMC NAND example

  • STM32F10x Standard Peripheral's Examples

FSMC NAND example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    FSMC/NAND/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the FSMC NAND example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example provides a basic example of how to use the FSMC firmware library and an associate driver to perform erase/read/write operations on the NAND512W3A2 memory mounted on STM3210E-EVAL board.

Directory contents
  • FSMC/NAND/stm32f10x_conf.h Library Configuration file
  • FSMC/NAND/stm32f10x_it.c Interrupt handlers
  • FSMC/NAND/stm32f10x_it.h Header for stm32f10x_it.c
  • FSMC/NAND/main.c Main program
  • FSMC/NAND/system_stm32f10x.c STM32F10x system source file
Hardware and Software environment
  • This example runs only on STM32F10x High-Density and XL-Density Devices.
  • This example has been tested with STMicroelectronics STM3210E-EVAL (High-Density and XL-Density) evaluation board. To select the STMicroelectronics evaluation board used to run the example, uncomment the corresponding line in stm32_eval.h file (under Utilities)
  • STM3210E-EVAL Set-up
    • This example runs on STMicroelectronics STM3210E-EVAL evaluation board RevD.
Note:
make sure that the Jumper 7 (JP7) is in position 1<-->2.
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: FSMC NOR example

  • STM32F10x Standard Peripheral's Examples

FSMC NOR example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    FSMC/NOR/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the FSMC NOR example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example provides a basic example of how to use the FSMC firmware library and an associate driver to perform erase/read/write operations on the M29W128FL, M29W128GL or S29GL128P NOR memories mounted on the STM3210E-EVAL board.

Directory contents
  • FSMC/NOR/stm32f10x_conf.h Library Configuration file
  • FSMC/NOR/stm32f10x_it.c Interrupt handlers
  • FSMC/NOR/stm32f10x_it.h Header for stm32f10x_it.c
  • FSMC/NOR/main.c Main program
  • FSMC/NOR/system_stm32f10x.c STM32F10x system source file
Hardware and Software environment
  • This example runs only on STM32F10x High-Density and XL-Density Devices.
  • This example has been tested with STMicroelectronics STM3210E-EVAL (High-Density and XL-Density) evaluation board. To select the STMicroelectronics evaluation board used to run the example, uncomment the corresponding line in stm32_eval.h file (under Utilities)
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: FSMC NOR CodeExecute example

  • STM32F10x Standard Peripheral's Examples

FSMC NOR CodeExecute example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    FSMC/NOR_CodeExecute/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the FSMC NOR CodeExecute example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This directory contains a set of sources files that describes how to build an application to be loaded into the NOR memory mounted on STM3210E-EVAL board then execute it from internal Flash.

Directory contents
  • FSMC/NOR_CodeExecute/binary: Contains a set of sources files that build the application to be loaded into the NOR memory mounted on STM3210E-EVAL board.
  • FSMC/NOR_CodeExecute/stm32f10x_conf.h Library Configuration file
  • FSMC/NOR_CodeExecute/stm32f10x_it.c Interrupt handlers
  • FSMC/NOR_CodeExecute/stm32f10x_it.h Header for stm32f10x_it.c
  • FSMC/NOR_CodeExecute/main.c Main program
  • FSMC/NOR_CodeExecute/system_stm32f10x.c STM32F10x system source file
Hardware and Software environment
  • This example runs only on STM32F10x High-Density and XL-Density Devices.
  • This example has been tested with STMicroelectronics STM3210E-EVAL (High-Density and XL-Density) evaluation board and can be easily tailored to any other supported device and development board.
How to use it ?

In order to make the program work, you must do the following:

1. Program the NOR memory with the example provided in the "binary" directory

2. Program the internal Flash with the code that will jump to the NOR memory to execute the loaded example, for this you have to:

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: FSMC NOR CodeExecute example binary directory

  • STM32F10x Standard Peripheral's Examples

FSMC NOR CodeExecute example binary directory

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    FSMC/NOR_CodeExecute/binary/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the FSMC NOR CodeExecute example binary directory.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This directory contains a set of sources files that build the application to be loaded into the NOR memory mounted on STM3210E-EVAL board.

The GPIO IOToggle example provided within the STM32F10x Firmware library is used as illustration. In this example four LEDs: LED1, LED2, LED3 and LED4 are toggled in an infinite loop.

Directory contents
  • FSMC/NOR_CodeExecute/binary/stm32f10x_conf.h Library Configuration file
  • FSMC/NOR_CodeExecute/binary/stm32f10x_it.c Interrupt handlers
  • FSMC/NOR_CodeExecute/binary/stm32f10x_it.h Header for stm32f10x_it.c
  • FSMC/NOR_CodeExecute/binary/main.c Main program
  • FSMC/NOR_CodeExecute/binary/FLASH_NOR.ini NOR Initialization File for MDK-ARM toolchain.
  • FSMC/NOR_CodeExecute/binary/STM3210E-EVAL_NOR.FLM STM3210E-EVAL board NOR flasher for MDK-ARM toolchain.
  • FSMC/NOR_CodeExecute/binary/system_stm32f10x.c STM32F10x system source file
Hardware and Software environment
  • This example runs only on STM32F10x High-Density and XL-Density Devices.
  • This example has been tested with STMicroelectronics STM3210E-EVAL (High-Density and XL-Density) evaluation board. To select the STMicroelectronics evaluation board used to run the example, uncomment the corresponding line in stm32_eval.h file (under Utilities)
How to use it ?

In order to make the program work, you must do the following:

  • Create a project and setup all project configuration:

    • MDK-ARM

      • copy "STM3210E-EVAL_NOR.FLM" file under "C:\Keil\ARM\Flash" directory
      • in Project->Options->Target window, select 'ROM1', enter 0x64000000 as start address with size of 0x1000000 and check "Startup" option (IROM1 must be un-checked)
      • in Project->Options->Linker window, uncheck "Use memory Layout from Target Dialog" then enter 0x64000000 as R/O base address and chek again "Use memory Layout from Target Dialog"
      • in Project->Options->Utilities window, select "Use Target Driver for Flash Programming"
      • Click on 'Settings' button then select "STM3210E_EVAL NOR Flash" as Programming Algorithms (start:0x64000000, size:0x1000000)
      • in Project->Options->Debug select "FLASH_NOR.ini" provided within this example directory as initialization file.

    • EWARM
      • use "stm32f10x_nor.icf" as linker file
      • in project->options ->debugger-> setup , the "run to main" option should be un-checked
      • in project->options ->J-Link/J-Trace-> setup , set the "Reset" to "Normal"
      • in project->options ->debugger->download, click on "edit" button ("Use flash loader(s)" option should be checked)
      • select the default flash loader then click on "edit" button
      • check "override default flash loader path" option and select "FlashSTM32F10x_NOR.xml" as flash loader ($TOOLKIT_DIR$.xml)
  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example
  • Link all compiled files and load your image into NOR memory
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: FSMC OneNAND example

  • STM32F10x Standard Peripheral's Examples

FSMC OneNAND example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    FSMC/OneNAND/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the FSMC OneNAND example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example shows how to configure the FSMC to drive the OneNAND memory mounted on STM32100E-EVAL board.

In this example a basic example of how to use the FSMC firmware library and an associate driver to perform read/write operations on the KFG1216U2A/B-DIB6 OneNAND memory.

The different OneNAND memory operations (Unlock, Erase, Write, Read) results are signalled using four LEDs as follows:

  • LED2, LED3 and LED4 are ON: OneNAND ID read failed
  • LED3 and LED4 ON: Unlock Block failed
  • LED2 and LED4 ON: Erase Block failed
  • LED4 ON: Write Buffer failed
  • LED2 ON: Asynchronous Read failed
  • LED3 ON: Synchronous Read
  • LED1 ON: All OneNAND memory operations are OK
Directory contents
  • FSMC/OneNAND/stm32f10x_conf.h Library Configuration file
  • FSMC/OneNAND/stm32f10x_it.c Interrupt handlers
  • FSMC/OneNAND/stm32f10x_it.h Header for stm32f10x_it.c
  • FSMC/OneNAND/main.c Main program
  • FSMC/OneNAND/system_stm32f10x.c STM32F10x system source file
Hardware and Software environment
  • This example runs on STM32F10x High-density value line Devices.
  • This example has been tested with STM32100E-EVAL and can be easily tailored to any other development board. Make sure that the jumper JP6 is in position 2<->3
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: FSMC SRAM example

  • STM32F10x Standard Peripheral's Examples

FSMC SRAM example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    FSMC/SRAM/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the FSMC SRAM example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example provides a basic example of how to use the FSMC firmware library and an associate driver to perform read/write operations on the IS61WV51216BLL SRAM memory mounted on STM3210E-EVAL board.

Directory contents
  • FSMC/SRAM/stm32f10x_conf.h Library Configuration file
  • FSMC/SRAM/stm32f10x_it.c Interrupt handlers
  • FSMC/SRAM/stm32f10x_it.h Header for stm32f10x_it.c
  • FSMC/SRAM/main.c Main program
  • FSMC/SRAM/system_stm32f10x.c STM32F10x system source file
Hardware and Software environment
  • This example runs only on STM32F10x High-Density, High-Density Value line and XL-Density Devices.
  • This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density Value line) and STM3210E-EVAL (High-Density and XL-Density) evaluation boards. To select the STMicroelectronics evaluation board used to run the example, uncomment the corresponding line in stm32_eval.h file (under Utilities)
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: FSMC SRAM DataMemory example

  • STM32F10x Standard Peripheral's Examples

FSMC SRAM DataMemory example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    FSMC/SRAM_DataMemory/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the FSMC SRAM DataMemory example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example shows how to use the external SRAM mounted on STM3210E-EVAL or STM32100E-EVAL board as program data memory and internal SRAM for Stack. This example doesn't use the default library startup files. Use the EWARM, MDK-ARM, HiTOP, RIDE or TrueSTUDIO startup files provided within this folder.

Directory contents
  • FSMC/SRAM_DataMemory/stm32f10x_conf.h Library Configuration file
  • FSMC/SRAM_DataMemory/stm32f10x_it.c Interrupt handlers
  • FSMC/SRAM_DataMemory/stm32f10x_it.h Header for stm32f10x_it.c
  • FSMC/SRAM_DataMemory/main.c Main program
  • FSMC/SRAM_DataMemory/system_stm32f10x.c STM32F10x system source file
  • FSMC/SRAM_DataMemory/EWARM/startup_stm32f10x_hd.s STM32F10x High-density EWARM startup file
  • FSMC/SRAM_DataMemory/EWARM/startup_stm32f10x_hd_vl.s STM32F10x High-density Value line EWARM startup file
  • FSMC/SRAM_DataMemory/EWARM/startup_stm32f10x_xl.s STM32F10x XL-density EWARM startup file
  • FSMC/SRAM_DataMemory/HiTOP/cstart_thumb2.asm STM32F10x XL-density EWARM startup file
  • FSMC/SRAM_DataMemory/MDK-ARM/startup_stm32f10x_hd.s STM32F10x High-density MDK-ARM startup file
  • FSMC/SRAM_DataMemory/MDK-ARM/startup_stm32f10x_hd_vl.s STM32F10x High-density Value line MDK-ARM startup file
  • FSMC/SRAM_DataMemory/MDK-ARM/startup_stm32f10x_xl.s STM32F10x XL-density MDK-ARM startup file
  • FSMC/SRAM_DataMemory/RIDE/startup_stm32f10x_hd.s STM32F10x High-density RIDE startup file
  • FSMC/SRAM_DataMemory/RIDE/startup_stm32f10x_hd_vl.s STM32F10x High-density Value line RIDE startup file
  • FSMC/SRAM_DataMemory/RIDE/startup_stm32f10x_xl.s STM32F10x XL-density RIDE startup file
  • FSMC/SRAM_DataMemory/TrueSTUDIO/startup_stm32f10x_hd.s STM32F10x High-density TrueSTUDIO startup file
  • FSMC/SRAM_DataMemory/TrueSTUDIO/startup_stm32f10x_hd_vl.s STM32F10x High-density Value line TrueSTUDIO startup file
  • FSMC/SRAM_DataMemory/TrueSTUDIO/startup_stm32f10x_xl.s STM32F10x XL-density TrueSTUDIO startup file
Hardware and Software environment
  • This example runs only on STM32F10x High-Density and XL-Density Devices.
  • This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density Value line) and STM3210E-EVAL (High-Density and XL-Density) evaluation boards and can be easily tailored to any other supported device and development board.
How to use it ?

In order to make the program work, you must do the following:

  • Create a project and setup all project configuration:

    • MDK-ARM

      • in Project->Options for Target window, select 'RAM1'and enter 0x68000000 as start address with size of 0x100000 (IRAM1 must be un-checked)
      • uncomment "#define DATA_IN_ExtSRAM " in the "system_stm32f10x.c" file

    • EWARM

      • use "stm32f10x_flash_extsram.icf" as linker file
      • uncomment "#define DATA_IN_ExtSRAM " in the "system_stm32f10x.c" file

    • RIDE

      • In the Application options -> script menu, set "Use Default Script File" to "No" and use "stm32f10x_flash_extsram.ld" as Script File.
      • uncomment "#define DATA_IN_ExtSRAM " in the "system_stm32f10x.c" file

    • HiTOP

      • use "link_extsram" as linker file
      • Add the file "setstack.asm" to the workspace.
      • Use the "cstart_thumb2.asm" file provided with this example instead of the default one in the workspace.
      • uncomment "#define DATA_IN_ExtSRAM " in the "system_stm32f10x.c" file

    • TrueSTUDIO

      • In the project properties window, select 'C/C++ Build'->settings node then the 'C Linker'->General node and use "stm32f10x_flash_extsram.ld" as Script File.
      • uncomment "#define DATA_IN_ExtSRAM " in the "system_stm32f10x.c" file

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: GPIO IO Toggle example

  • STM32F10x Standard Peripheral's Examples

GPIO IO Toggle example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    GPIO/IOToggle/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the GPIO IO Toggle example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

GPIO ports are connected on APB2 bus, using BSRRH and BSRRL registers 2 cycles are required to set a pin and another cycle to reset it. So GPIO pins can toggle at AHB clock divided by 4.

This example describes how to use BSRR and BRR (Port Bit Set/Reset Register and Port Bit Reset Register) for maximum IO toggling.

PD0 and PD2 (configured in output pushpull mode) toggles in a forever loop:

  • Set PD0 and PD2 by setting corresponding bits in BSRR register
  • Reset PD0 and PD2 by setting corresponding bits in BRR register

In this example, HCLK is configured at 72 MHz so PD0 and PD2 toggles at 18MHz. To achieve the maximum IO toggling frequency, you have to configure your compiler options for high speed optimization.

Directory contents
  • GPIO/IOToggle/stm32f10x_conf.h Library Configuration file
  • GPIO/IOToggle/stm32f10x_it.c Interrupt handlers
  • GPIO/IOToggle/stm32f10x_it.h Header for stm32f10x_it.c
  • GPIO/IOToggle/main.c Main program
  • GPIO/IOToggle/system_stm32f10x.c STM32F10x system source file
Hardware and Software environment
  • This example runs on STM32F10x Connectivity line, High-Density, High-Density Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density and Low-Density Value line Devices.
  • This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) evaluation boards and can be easily tailored to any other supported device and development board. To select the STMicroelectronics evaluation board used to run the example, uncomment the corresponding line in stm32_eval.h file (under Utilities)
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: GPIO JTAG Remap example

  • STM32F10x Standard Peripheral's Examples

GPIO JTAG Remap example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    GPIO/JTAG_Remap/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the GPIO JTAG Remap example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example provides a short description of how to use the JTAG IOs as standard GPIOs and gives a configuration sequence.

First, the SWJ-DP is disabled. The SWJ-DP pins are configured as output push-pull. Five LEDs connected to the PA.13(JTMS/SWDAT), PA.14(JTCK/SWCLK), PA.15(JTDI), PB.03(JTDO) and PB.04(JTRST) pins are toggled in an infinite loop.

Note that once the JTAG IOs are disabled, the connection with the host debugger is lost and cannot be re-established as long as the JTAG IOs remain disabled.

To avoid this situation, a specified pin is connected to a push-button that is used to disable or not the JTAG IOs: 1. push-button pressed at reset: JTAG IOs disabled and LED1 turned on 2. push-button not pressed at reset: JTAG IOs unchanged and LED2 turned on

Before starting this example, you should disconnect your tool chain debugging probe and run the example in standalone mode.

Directory contents
  • GPIO/JTAG_Remap/stm32f10x_conf.h Library Configuration file
  • GPIO/JTAG_Remap/stm32f10x_it.c Interrupt handlers
  • GPIO/JTAG_Remap/stm32f10x_it.h Header for stm32f10x_it.c
  • GPIO/JTAG_Remap/main.c Main program
  • GPIO/JTAG_Remap/system_stm32f10x.c STM32F10x system source file
Hardware and Software environment
  • This example runs on STM32F10x Connectivity line, High-Density, High-Density Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density and Low-Density Value line Devices.
  • This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) evaluation boards and can be easily tailored to any other supported device and development board. To select the STMicroelectronics evaluation board used to run the example, uncomment the corresponding line in stm32_eval.h file (under Utilities)
  • STM32100E-EVAL Set-up
    • Connect five leds to pins PA.13, PA.14, PA.15, PB.03 and PB.04.
    • Use the Key push-button connected to pin PG.08 (EXTI Line8).
    • Use LD1 and LD2 connected respectively to PF.06 and PF.07
  • STM32100B-EVAL Set-up
    • Connect five leds to pins PA.13, PA.14, PA.15, PB.03 and PB.04.
    • Use the Key push-button connected to pin PB.09 (EXTI Line9).
    • Use LD1 and LD2 connected respectively to PC.06 and PC.07
  • STM3210C-EVAL Set-up
    • Connect five leds to pins PA.13, PA.14, PA.15, PB.03 and PB.04.
    • Use the Key push-button connected to pin PB.09 (EXTI Line9).
    • Use LD1 and LD2 connected respectively to PC.06 and PC.07
  • STM3210E-EVAL Set-up
    • Connect five leds to pins PA.13, PA.14, PA.15, PB.03 and PB.04.
    • Use the Key push-button connected to pin PG.08 (EXTI Line8).
    • Use LD1 and LD2 connected respectively to PF.06 and PF.07
  • STM3210B-EVAL Set-up
    • Connect five leds to pins PA.13, PA.14, PA.15, PB.03 and PB.04.
    • Use the Key push-button connected to pin PB.09 (EXTI Line9).
    • Use LD1 and LD2 connected respectively to PC.06 and PC.07
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: I2S Interrupt example

  • STM32F10x Standard Peripheral's Examples

I2S Interrupt example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    I2S/Interrupt/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the I2S Interrupt example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example provides a description of how to set a communication between two SPIs in I2S mode using interrupts and performing a transfer from Master to Slave.

In the first step, I2S3 is configured as master transmitter and I2S2 as slave reliever and both are in Philips standard configuration with 16bit extended to 32 bit data packet and 48KHz audio frequency.

The I2S3 transmit interrupt and the I2S2 receive interrupt are both enabled. And in these interrupts subroutines, the I2S3_Buffer_Tx is transmitted and the received values are loaded in the I2S2_Buffer_Rx buffer. Only the significant 16 MSBs are sent and received, while the 32 packet remaining 16 LSBs are filled with 0 values and don't generate any interrupt.

Once the transfer is completed a comparison is done and TransferStatus1 gives the data transfer status where it is PASSED if transmitted and received data are the same otherwise it is FAILED.

In the second step both peripherals are configured in I2S Philips standard 24 bits data length in 32 bits packets and 16KHz audio frequency. The interrupts are enabled and the transfer is performed from the I2S3 master to the I2S2 slave. The 24 bits are transmitted then the 8 remaining LSBs are filled automatically with 0 values.

Once the transfer is completed a comparison is done (on the 24 MSBs only, the 8 LSBs are replaced by 0) and TransferStatus2 gives the data transfer status where it is PASSED if transmitted and received data are the same otherwise it is FAILED.

Directory contents
  • I2S/Interrupt/stm32f10x_conf.h Library Configuration file
  • I2S/Interrupt/stm32f10x_it.c Interrupt handlers
  • I2S/Interrupt/stm32f10x_it.h Header for stm32f10x_it.c
  • I2S/Interrupt/main.c Main program
  • I2S/Interrupt/system_stm32f10x.c STM32F10x system source file
Hardware and Software environment
  • This example runs on STM32F10x High-Density, XL-Density and Connectivity Line Devices.
  • This example has been tested with STMicroelectronics STM3210E-EVAL (High-Density and XL-Density) and STM3210C-EVAL (Connectivity Line) evaluation boards and can be easily tailored to any other supported device and development board.
  • STM3210C-EVAL Set-up
    • Connect I2S2 WS (PB.12) pin to I2S3 WS (PA.04) pin
    • Connect I2S2 CK (PB.13) pin to I2S3 CK (PC.10) pin
    • Connect I2S2 SD (PB.15) pin to I2S3 SD (PC.12) pin
  • STM3210E-EVAL Set-up
    • Connect I2S2 WS (PB.12) pin to I2S3 WS (PA.15) pin
    • Connect I2S2 CK (PB.13) pin to I2S3 CK (PB.03) pin
    • Connect I2S2 SD (PB.15) pin to I2S3 SD (PB.05) pin

Since some SPI3/I2S3 pins are shared with JTAG pins (SPI3_NSS/I2S3_WS with JTDI and SPI3_SCK/I2S3_CK with JTDO), they are not controlled by the I/O controller and are reserved for JTAG usage (after each Reset). For this purpose prior to configure the SPI3/I2S3 pins:

  • For STM32F10x High-Density devices, the user has to disable the JTAG and use the SWD interface (when debugging the application), or disable both JTAG/SWD interfaces (for standalone application).
  • For STM32F10x Connectivity Line devices, the user can use the solution above (SWD or disable both JTAG and SWD), or it is possible to remap the SPI3 pins on {PC10, PC11, PC12, PA4} GPIO pins in order to avoid the conflict with JTAG pins (and it is possible in this case to use JTAG interface). This remap is used for STM3210C-EVAL evaluation boards in this example.
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: SPI_I2S_Switch example

  • STM32F10x Standard Peripheral's Examples

SPI_I2S_Switch example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    I2S/SPI_I2S_Switch/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the SPI_I2S_Switch example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example provides a description of how to set a communication between two SPIs in I2S mode, and how to switch between SPI and I2S modes, performing a transfer from Master to Slave in I2S modes then a transfer from master to slave in SPI mode and finally a transfer from Slave to Master in I2S mode.

I2S2 is configured as master transmitter and I2S3 as slave receiver and both are in Philips standard configuration with 16bit data size in 32bit packet length and 48KHz audio frequency.

In the first phase, the master I2S2 starts the I2S2_Buffer_Tx transfer while the slave I2S3 receives and loads the values in I2S3_Buffer_Rx. Once the transfer is completed a comparison is done and TransferStatus1 gives the data transfer status where it is PASSED if transmitted and received data are the same otherwise it is FAILED.

In the second step, both peripherals are configured in SPI modes (simplex communication) and SPI2_Buffer_Tx transfer is performed in simplex mode from SPI2 to SPI3.Once the transfer is completed a comparison is done and TransferStatus2 gives the data transfer status where it is PASSED if transmitted and received data are the same otherwise it is FAILED. As the master/slave mode is managed by software (the master is the clock (CK and WS) generator), this allows to I2S2 to become slave transmitter and I2S3 to become master receiver without hardware modification.

In the third step, the slave I2S2 prepares the first data to be sent before the master is enabled. Once the master is enabled, the clocks are released from the master and the data are released on the slave. Once the transfer is completed a comparison is done and TransferStatus3 gives the data transfer status where it is PASSED if transmitted and received data are the same otherwise it is FAILED.

Directory contents
  • I2S/SPI_I2S_Switch/stm32f10x_conf.h Library Configuration file
  • I2S/SPI_I2S_Switch/stm32f10x_it.c Interrupt handlers
  • I2S/SPI_I2S_Switch/stm32f10x_it.h Header for stm32f10x_it.c
  • I2S/SPI_I2S_Switch/main.c Main program
  • I2S/SPI_I2S_Switch/system_stm32f10x.c STM32F10x system source file
Hardware and Software environment
  • This example runs on STM32F10x High-Density, XL-Density and Connectivity Line Devices.
  • This example has been tested with STMicroelectronics STM3210E-EVAL (High-Density and XL-Density) and STM3210C-EVAL (Connectivity Line) evaluation boards and can be easily tailored to any other supported device and development board.
  • STM3210C-EVAL Set-up
    • Connect I2S2 WS (PB.12) pin to I2S3 WS (PA.04) pin
    • Connect I2S2 CK (PB.13) pin to I2S3 CK (PC.10) pin
    • Connect I2S2 SD (PB.15) pin to I2S3 SD (PC.12) pin
  • STM3210E-EVAL Set-up
    • Connect I2S2 WS (PB.12) pin to I2S3 WS (PA.15) pin
    • Connect I2S2 CK (PB.13) pin to I2S3 CK (PB.03) pin
    • Connect I2S2 SD (PB.15) pin to I2S3 SD (PB.05) pin

Since some SPI3/I2S3 pins are shared with JTAG pins (SPI3_NSS/I2S3_WS with JTDI and SPI3_SCK/I2S3_CK with JTDO), they are not controlled by the I/O controller and are reserved for JTAG usage (after each Reset). For this purpose prior to configure the SPI3/I2S3 pins:

  • For STM32F10x High-Density devices, the user has to disable the JTAG and use the SWD interface (when debugging the application), or disable both JTAG/SWD interfaces (for standalone application).
  • For STM32F10x Connectivity Line devices, the user can use the solution above (SWD or disable bothe JTAG and SWD), or it is possible to remap the SPI3 pins on {PC10, PC11, PC12, PA4} GPIO pins in order to avoid the conflict with JTAG pins (and it is possible in this case to use JTAG interface). This remap is used for STM3210C-EVAL evaluation boards in this example.
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: IWDG Reset example

  • STM32F10x Standard Peripheral's Examples

IWDG Reset example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    IWDG/IWDG_Reset/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the IWDG Reset example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example shows how to update at regular period the IWDG reload counter and how to simulate a software fault generating an MCU IWDG reset on expiry of a programmed time period.

The IWDG timeout is set to 250 ms (the timeout may varies due to LSI frequency dispersion).

First, the TIM5 timer is configured to measure the LSI frequency as the LSI is internally connected to TIM5 CH4, in order to adjust the IWDG clock.

The LSI measurement using the TIM5 is described below:

  • Configure the TIM5 to remap internally the TIM5 Channel 4 Input Capture to the LSI clock output.
  • Enable the TIM5 Input Capture interrupt: after one cycle of LSI clock, the period value is stored in a variable and compared to the HCLK clock to get its real value.
Note:
The LSI is internally connected to TIM5 IC4 only on STM32F10x Connectivity line, High-Density Value line, High-Density and XL-Density Devices. When using other devices, you should comment the "#define LSI_TIM_MEASURE" in main.c file and in this case the LSI frequency is set by default to 40KHz.

Then, the IWDG reload counter is configured to obtain 240ms according to the measured LSI frequency.

The IWDG reload counter is refreshed each 240ms in the main program infinite loop to prevent a IWDG reset. LED2 is also toggled each 240ms indicating that the program is running.

An EXTI Line is connected to a GPIO pin, and configured to generate an interrupt on the rising edge of the signal.

The EXTI Line is used to simulate a software failure: once the EXTI Line event occurs, by pressing the Key push-button, the corresponding interrupt is served. In the ISR, a write to invalid address generates a Hardfault exception containing an infinite loop and preventing to return to main program (the IWDG reload counter is not refreshed). As a result, when the IWDG counter reaches 00h, the IWDG reset occurs. If the IWDG reset is generated, after the system resumes from reset, LED1 turns on.

If the EXTI Line event does not occur, the IWDG counter is indefinitely refreshed in the main program infinite loop, and there is no IWDG reset.

In this example the system clock is set to 24 MHz on Value line devices and to 72MHz on other devices.

Note:
The IWDG Counter can be only written when the RVU flag is reset. In this example, as the SysTick period is too higher than the IWDG Counter Update timing (5 Cycles 40KHz RC), the Reload Value Update "RVU" flag is not checked before reloading the counter.
Directory contents
  • IWDG/IWDG_Reset/stm32f10x_conf.h Library Configuration file
  • IWDG/IWDG_Reset/stm32f10x_it.c Interrupt handlers
  • IWDG/IWDG_Reset/stm32f10x_it.h Header for stm32f10x_it.c
  • IWDG/IWDG_Reset/main.c Main program
  • IWDG/IWDG_Reset/system_stm32f10x.c STM32F10x system source file
Hardware and Software environment
  • This example runs on STM32F10x Connectivity line, High-Density, High-Density Value line, Medium-Density, XL-Density, High-Density Value line, Medium-Density Value line, Low-Density and Low-Density Value line Devices.
  • This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), STM3210E-EVAL (High-Density and XL-Density), STM32100E-EVAL (High-Density Value line) and STM3210B-EVAL (Medium-Density) evaluation boards and can be easily tailored to any other supported device and development board. To select the STMicroelectronics evaluation board used to run the example, uncomment the corresponding line in stm32_eval.h file (under Utilities)
  • STM32100E-EVAL Set-up
    • Use LD1 and LD2 leds connected respectively to PF.06 and PF.07 pins
    • Use the KEY push button connected to PG.08 pin (EXTI Line8).
  • STM32100B-EVAL Set-up
    • Use LD1 and LD2 leds connected respectively to PC.06 and PC.07 pins
    • Use the KEY push button connected to PB.09 pin (EXTI Line9).
  • STM3210C-EVAL Set-up
    • Use LD1 and LD2 connected respectively to PD.07 and PD.13 pins
    • Use the Key push-button connected to pin PB.09 (EXTI Line9).
  • STM3210E-EVAL Set-up
    • Use LD1 and LD2 leds connected respectively to PF.06 and PF.07 pins
    • Use the KEY push button connected to PG.08 pin (EXTI Line8).
  • STM3210B-EVAL Set-up
    • Use LD1 and LD2 leds connected respectively to PC.06 and PC.07 pins
    • Use the KEY push button connected to PB.09 pin (EXTI Line9).
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Link all compiled files and load your image into target memory
  • Run the example in standalone mode (without debugger connection)
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: Lib_DEBUG Run Time Checking example

  • STM32F10x Standard Peripheral's Examples

Lib_DEBUG Run Time Checking example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    Lib_DEBUG/RunTime_Check/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the Lib_DEBUG Run Time Checking example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example demonstrates how to declare a dynamic peripherals pointers used for Debug mode.

To use Debug mode you have to add the stm32f10x_ip_dbg.c file to your application. This creates a pointer to the peripheral structure in SRAM. Debugging consequently becomes easier and all register settings can be obtained by dumping a peripheral variable.

When the "USE_FULL_ASSERT" label is uncommented (in stm32f10x_conf.h file), the assert_param macro is expanded and runtime checking is enabled in the firmware library code. The runtime checking allows checking that all the library functions input value lies within the parameter allowed values.

The associated program simulates wrong parameter passed to library function and the source of the error is printed on HyperTerminal (through USART).

Note:
The Debug mode increases the code size and reduces the code performance. For this reason, it is recommended to used it only when debugging the application and to remove it from the final application code.
Directory contents
  • Lib_DEBUG/RunTime_Check/stm32f10x_conf.h Library Configuration file
  • Lib_DEBUG/RunTime_Check/stm32f10x_it.c Interrupt handlers
  • Lib_DEBUG/RunTime_Check/stm32f10x_it.h Header for stm32f10x_it.c
  • Lib_DEBUG/RunTime_Check/main.c Main program
  • Lib_DEBUG/RunTime_Check/stm32f10x_ip_dbg.c Peripherals pointers initialization
  • Lib_DEBUG/RunTime_Check/stm32f10x_ip_dbg.h Header for lib_dbg.c
  • Lib_DEBUG/RunTime_Check/system_stm32f10x.c STM32F10x system source file
Hardware and Software environment
  • This example runs on STM32F10x Connectivity line, High-Density, High-Density Value line, Medium-Density, XL-Density, High-Density Value line, Medium-Density Value line, Low-Density and Low-Density Value line Devices.
  • This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) evaluation boards and can be easily tailored to any other supported device and development board. To select the STMicroelectronics evaluation board used to run the example, uncomment the corresponding line in stm32_eval.h file (under Utilities)
  • STM32100E-EVAL Set-up
    • Connect a null-modem female/female RS232 cable between the DB9 connector CN10 and PC serial port.
  • STM32100B-EVAL Set-up
    • Connect a null-modem female/female RS232 cable between the DB9 connector CN10 and PC serial port.
  • STM3210C-EVAL Set-up
    • Connect a null-modem female/female RS232 cable between the DB9 connector CN6 and PC serial port.
      Note:
      Make sure that jumpers JP19 and JP18 are open.
  • STM3210E-EVAL Set-up
    • Connect a null-modem female/female RS232 cable between the DB9 connector CN12 and PC serial port.
  • STM3210B-EVAL Set-up
    • Connect a null-modem female/female RS232 cable between the DB9 connector CN6 and PC serial port.
  • Hyperterminal configuration:
    • Word Length = 8 Bits
    • One Stop Bit
    • No parity
    • BaudRate = 115200 baud
    • flow control: None
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Add the required example files
    • stm32f10x_ip_dbg.c
Note:
  • The free Lite version of TrueSTUDIO do not support printf() redirection. For more information, see "note.txt" under "STM32F10x_StdPeriph_Template\TrueSTUDIO".
  • Rebuild all files and load your image into target memory
  • Run the example
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: NVIC IRQ Mask example

  • STM32F10x Standard Peripheral's Examples

NVIC IRQ Mask example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    NVIC/IRQ_Mask/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the NVIC IRQ Mask example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example demontrates the use of the Nested Vectored Interrupt Controller (NVIC) IRQ Channels configuration and how to mask/activate different IRQs:

  • Configuration of 3 TIM (TIM2..TIM4)timers to generate an interrupt on each counter update event.
  • The three timers are linked to their correspondant Update IRQ channel.
  • Assignment of a ascendant IRQ priority for each IRQ channel :
    • TIM2 has a preemption priority of 0
    • TIM3 has a preemption priority of 1
    • TIM4 has a preemption priority of 2
  • In each interrupt routine:
    • TIM2 toggles a LED1 each 1s
    • TIM3 toggles a LED2 each 2s
    • TIM4 toggles a LED3 each 3s
  • The KEY and WAKEUP buttons are used to boost the execution priority as follows:
  • The KEY button is used in GPIO mode and at each KEY button press, the execution priority is raised to 0 and turn LED4 ON. This prevents all exceptions with configurable priority from activating, other than through the HardFault fault escalation mechanism. As consequence, all LEDs stop toggling as TIM2, TIM3 and TIM4 IRQs are prevented from activation.

Pressing again the KEY button will release the priority boosting, turn LED4 OFF and will allow all exceptions with configurable priority to be activated and TIM2, TIM3 and TIM4 can be generated again and the LEDs restart toggling.

This execution priority is made using the CMSIS functions "__disable_irq()" and "__enable_irq()". These two functions are managing the Cortex-M3 PRIMASK special register.

  • The WAKEUP button is used in EXTI mode and at each WAKEUP button press, the execution priority is masked to 0x40 using the BASEPRI register. A non-zero value will act as a priority mask, affecting the execution priority when the priority defined by BASEPRI is the same or higher than the current executing priority. As consequence, LED2 and LED3 stop toggling as TIM3 and TIM4 IRQs are prevented from activation. Pressing again the WAKEUP button will configure the BASEPRI register to 0, thus it has no effect on the current priority and TIM3 and TIM4 can be generated again and LED2 and LED3 restart toggling.

This execution priority is made using the CMSIS functions "__set_BASEPRI()". This function is managing the Cortex-M3 BASEPRI special register. Setting the BASEPRI register has no effect when the execution priority is raised to 0 using the "__disable_irq()" function.

Note:
These mechanisms only affect the group priority. They have no effect on the sub-priority. The sub-priority is only used to sort pending exception priorities, and does not affect active exceptions.
Directory contents
  • NVIC/IRQ_Mask/stm32f10x_conf.h Library Configuration file
  • NVIC/IRQ_Mask/stm32f10x_it.c Interrupt handlers
  • NVIC/IRQ_Mask/stm32f10x_it.h Interrupt handlers header file
  • NVIC/IRQ_Mask/main.c Main program
  • NVIC/IRQ_Mask/system_stm32f10x.c STM32F10x system source file
Hardware and Software environment
  • This example runs on STM32F10x Connectivity line, High-Density, High-Density Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density and Low-Density Value line Devices.
  • This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) evaluation boards and can be easily tailored to any other supported device and development board. To select the STMicroelectronics evaluation board used to run the example, uncomment the corresponding line in stm32_eval.h file (under Utilities)
  • STM32100E-EVAL Set-up
    • Use LED1, LED2, LED3 and LED4 leds connected respectively to PF.06, PF.07 PF.08 and PF.09
    • Use the Key push-button connected to pin PG.08 (EXTI Line8).
    • Use the Wakeup push-button connected to pin PA.00 (EXTI Line0).
      Note:
      the jumper JP4 must be not fit to be able to use the Wakeup push-button
  • STM32100B-EVAL Set-up
    • Use LED1, LED2, LED3 and LED4 leds connected respectively to PC.06, PC.07, PC.08 and PC.09
    • Use the Key push-button connected to pin PB.09 (EXTI Line9).
    • Use the Wakeup push-button connected to pin PA.00 (EXTI Line0).
  • STM3210C-EVAL Set-up
    • Use LED1, LED2, LED3 and LED4 connected respectively to PD.07, PD.13, PF.03 and PD.04 pins
    • Use the Key push-button connected to pin PB.09 (EXTI Line9).
    • Use the Wakeup push-button connected to pin PA.00 (EXTI Line0).
      Note:
      Make sure that the Jumper 14 is in position 2<->3.
  • STM3210E-EVAL Set-up
    • Use LED1, LED2, LED3 and LED4 leds connected respectively to PF.06, PF.07 PF.08 and PF.09
    • Use the Key push-button connected to pin PG.08 (EXTI Line8).
    • Use the Wakeup push-button connected to pin PA.00 (EXTI Line0).
      Note:
      the jumper JP4 must be not fit to be able to use the Wakeup push-button
  • STM3210B-EVAL Set-up
    • Use LED1, LED2, LED3 and LED4 leds connected respectively to PC.06, PC.07, PC.08 and PC.09
    • Use the Key push-button connected to pin PB.09 (EXTI Line9).
    • Use the Wakeup push-button connected to pin PA.00 (EXTI Line0).
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: NVIC IRQ Priority example

  • STM32F10x Standard Peripheral's Examples

NVIC IRQ Priority example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    NVIC/IRQ_Priority/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the NVIC IRQ Priority example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example demonstrates the use of the Nested Vectored Interrupt Controller (NVIC):

  • Configuration of 2 EXTI Lines (Wakeup button EXTI Line & Key button EXTI Line) to generate an interrupt on each falling edge and use the SysTick interrupt.
  • These interrupts are configured with the following parameters:
    • Wakeup button EXTI Line:
      • PreemptionPriority = PreemptionPriorityValue
      • SubPriority = 0
    • Key button EXTI Line:
      • PreemptionPriority = 0
      • SubPriority = 1
    • SysTick Handler:
      • PreemptionPriority = !PreemptionPriorityValue
      • SubPriority = 0 First, the PreemptionPriorityValue is equal to 0, the Wakeup button EXTI Line has higher preemption priority than the SysTick handler.

In the key button EXTI Line interrupt routine the Wakeup button EXTI Line and SysTick preemption priorities are inverted. In the Wakeup button EXTI Line interrupt routine the pending bit of the SysTick interrupt is set this will cause SysTick ISR to preempt the Wakeup button EXTI Line ISR only if it has higher preemption priority.

The system behaves as following:

1) The first time Key button EXTI Line interrupt occurs the SysTick preemption become higher than Wakeup button EXTI Line one. So when the Wakeup button EXTI Line interrupt occurs, the SysTick ISR is executed and the PreemptionOccured variable become TRUE and the four leds (LED1, LED2, LED3, LED4) start toggling.

2) When the next Key button EXTI Line interrupt occurs the SysTick preemption become lower than Wakeup button EXTI Line one. So when the Wakeup button EXTI Line interrupt occurs, the PreemptionOccured variable became FALSE and the four leds (LED1, LED2, LED3, LED4) stop toggling.

Then this behavior is repeated from point 1) in an infinite loop.

Directory contents
  • NVIC/IRQ_Priority/stm32f10x_conf.h Library Configuration file
  • NVIC/IRQ_Priority/stm32f10x_it.c Interrupt handlers
  • NVIC/IRQ_Priority/stm32f10x_it.h Interrupt handlers header file
  • NVIC/IRQ_Priority/main.c Main program
  • NVIC/IRQ_Priority/system_stm32f10x.c STM32F10x system source file
Hardware and Software environment
  • This example runs on STM32F10x Connectivity line, High-Density, High-Density Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density and Low-Density Value line Devices.
  • This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) evaluation boards and can be easily tailored to any other supported device and development board. To select the STMicroelectronics evaluation board used to run the example, uncomment the corresponding line in stm32_eval.h file (under Utilities)
  • STM32100E-EVAL Set-up
    • Use LED1, LED2, LED3 and LED4 connected respectively to PF.06, PF0.7, PF.08 and PF.09 pins
    • Use the Key push-button connected to pin PG.08 (EXTI Line8).
    • Use the Wakeup push-button connected to pin PA.00 (EXTI Line0).
      Note:
      the jumper JP4 must be not fit to be able to use the Wakeup push-button
  • STM32100B-EVAL Set-up
    • Use LED1, LED2, LED3 and LED4 connected respectively to PC.06, PC.07, PC.08 and PC.09 pins
    • Use the Key push-button connected to pin PB.09 (EXTI Line9).
    • Use the Wakeup push-button connected to pin PA.00 (EXTI Line0).
  • STM3210C-EVAL Set-up
    • Use LED1, LED2, LED3 and LED4 connected respectively to PD.07, PD.13, PF.03 and PD.04 pins
    • Use the Key push-button connected to pin PB.09 (EXTI Line9).
    • Use the Wakeup push-button connected to pin PA.00 (EXTI Line0). Make sure that the Jumper 14 is in position 2<->3.
  • STM3210E-EVAL Set-up
    • Use LED1, LED2, LED3 and LED4 connected respectively to PF.06, PF0.7, PF.08 and PF.09 pins
    • Use the Key push-button connected to pin PG.08 (EXTI Line8).
    • Use the Wakeup push-button connected to pin PA.00 (EXTI Line0).
      Note:
      the jumper JP4 must be not fit to be able to use the Wakeup push-button
  • STM3210B-EVAL Set-up
    • Use LED1, LED2, LED3 and LED4 connected respectively to PC.06, PC.07, PC.08 and PC.09 pins
    • Use the Key push-button connected to pin PB.09 (EXTI Line9).
    • Use the Wakeup push-button connected to pin PA.00 (EXTI Line0).
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: NVIC VectorTable Relocation example

  • STM32F10x Standard Peripheral's Examples

NVIC VectorTable Relocation example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    NVIC/VectorTable_Relocation/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the NVIC VectorTable Relocation example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example describes how to set the CortexM3 vector table in a specific address other than default using the NVIC_SetVectorTable function from the misc.h/.c driver.

This can be used to build program which will be loaded into Flash memory by an application previously programmed from the Flash memory base address. Such application can be In-Application Programming (IAP, through USART) or Device Firmware Upgrade (DFU, through USB).

These applications are available for download from the ST microcontrollers website: www.st.com/stm32

The associated program implements a "Delay" function based on SysTick end of count interrupt, and toggles four leds with timing defined by the "Delay" function.

When using the IAP to load your porgram, the vector table must be relocated at address 0x08003000.

When using the DFU to load your porgram, the vector table must be relocated at address 0x08003000.

Directory contents
  • NVIC/VectorTable_Relocation/linker: modified linker to be used for this project
  • NVIC/VectorTable_Relocation/stm32f10x_conf.h Library Configuration file
  • NVIC/VectorTable_Relocation/stm32f10x_it.c Interrupt handlers
  • NVIC/VectorTable_Relocation/stm32f10x_it.h Interrupt handlers header file
  • NVIC/VectorTable_Relocation/main.c Main program
  • NVIC/VectorTable_Relocation/main.h Header for main.c
  • NVIC/VectorTable_Relocation/system_stm32f10x.c STM32F10x system source file
Hardware and Software environment
  • This example runs on STM32F10x Connectivity line, High-Density, High-Density Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density and Low-Density Value line Devices.
  • This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) evaluation boards and can be easily tailored to any other supported device and development board. To select the STMicroelectronics evaluation board used to run the example, uncomment the corresponding line in stm32_eval.h file (under Utilities)
  • STM32100E-EVAL Set-up
    • Use LD1, LD2, LD3 and LD4 leds connected respectively to PF.06, PF0.7, PF.08 and PF.09 pins
  • STM32100B-EVAL Set-up
    • Use LD1, LD2, LD3 and LD4 leds connected respectively to PC.06, PC.07, PC.08 and PC.09 pins
  • STM3210C-EVAL Set-up
    • Use LED1, LED2, LED3 and LED4 leds connected respectively to PD.07, PD.13, PF.03 and PD.04 pins
  • STM3210E-EVAL Set-up
    • Use LD1, LD2, LD3 and LD4 leds connected respectively to PF.06, PF0.7, PF.08 and PF.09 pins
  • STM3210B-EVAL Set-up
    • Use LD1, LD2, LD3 and LD4 leds connected respectively to PC.06, PC.07, PC.08 and PC.09 pins
How to use it ?

In order to make the program work, you must do the following :

  • Create a project and setup all project configuration:

    • MDK-ARM

      • In the project option menu, select 'Target' window and enter 0x08003000 as IROM start address
      • In the project option menu, select 'Linker' window and enter 0x08003000 as R/O base address

    • EWARM

      • Use "stm32f10x_flash_offset.icf" as linker file

    • RIDE

      • In the Application options -> script menu, set "Use Default Script File" to "No" and use "stm32f10x_flash_offset.ld" as Script File. This linker is configured for STM32 XL-density devices. To use it with other STM32 devices, this linker should be updated.

    • HiTOP

      • From linker\[target], copy the "link_offset" and "STM32F10x_offset.lsl" to "Settings" folder.
      • In project -> settings -> project -> tool settings ->linker use "link_offset.lnk" as linker file.
      • Add the "setstack.asm" to the workspace.

    • TrueSTUDIO

      • In the project properties window, select 'C/C++ Build'->settings node then the 'C Linker'->General node and use "stm32f10x_flash_offset.ld" as Script File. This linker is configured for STM32 STM32F10x XL-density devices. To use it with other STM32 devices, this linker should be updated.

  • Copy all source files from this example folder to the template folder under Project
  • In the main.c and linker files, the vector table is relocated at address 0x08003000. You can modify this address depending on the requirement of your application.
  • Rebuild all files
  • Convert the program image to a binary file, *.bin, then you can download and run it using the IAP or DFU application.
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: PWR PVD example

  • STM32F10x Standard Peripheral's Examples

PWR PVD example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    PWR/PVD/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the PWR PVD example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example shows how to configure the programmable voltage detector using an external interrupt line. In this example, EXTI line 16 is configured to generate an interrupt on each rising or falling edge of the PVD output signal (which indicates that the Vdd voltage is below the PVD threshold). In the interrupt routine a led connected to a specific GPIO pin is toggled every time the voltage drops below or the target threshold.

Directory contents
  • PWR/PVD/stm32f10x_conf.h Library Configuration file
  • PWR/PVD/stm32f10x_it.c Interrupt handlers
  • PWR/PVD/stm32f10x_it.h Header for stm32f10x_it.c
  • PWR/PVD/main.c Main program
  • PWR/PVD/system_stm32f10x.c STM32F10x system source file
Hardware and Software environment
  • This example runs on STM32F10x Connectivity line, High-Density, High-Density Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density and Low-Density Value line Devices.
  • This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) evaluation boards and can be easily tailored to any other supported device and development board. To select the STMicroelectronics evaluation board used to run the example, uncomment the corresponding line in stm32_eval.h file (under Utilities)
  • STM32100E-EVAL Set-up
    • Use LED1 led connected to PC.06 pin
  • STM32100B-EVAL Set-up
    • Use LED1 led connected to PC.06 pin
  • STM3210C-EVAL Set-up
    • Use LED1 led connected to PD.07 pin
  • STM3210E-EVAL Set-up
    • Use LED1 led connected to PF.06 pin
  • STM3210B-EVAL Set-up
    • Use LED1 led connected to PC.06 pin
Note:
  • Use a variable DC power supply connected to the 3V3 input to the evaluation board and dropping the voltage below 2.7V.
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example in standalone mode (without debugger connection)
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: PWR STANDBY example

  • STM32F10x Standard Peripheral's Examples

PWR STANDBY example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    PWR/STANDBY/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the PWR STANDBY example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example shows how to enters the system to STANDBY mode and wake-up from this mode using: external RESET, RTC Alarm or WKUP pin.

In the associated software, the system clock is set to 24 MHz on Value line devices and to 72 MHz on other devices using the external high speed oscillator(HSE), an EXTI line is configured to generate an interrupt on falling edge and the SysTick is programmed to generate an interrupt each 250 ms. In the SysTick interrupt handler, the LED1 is toggled, this is used to indicate whether the MCU is in STANDBY or RUN mode.

When a falling edge is detected on the EXTI line an interrupt is generated. In the EXTI handler routine the RTC is configured to generate an Alarm event in 3 second then the system enters STANDBY mode causing the LED1 to stop toggling. A rising edge on WKUP pin or an external RESET will wake-up the system from STANDBY. If within 3 second neither rising edge on WKUP pin nor external RESET are generated, the RTC Alarm will wake-up the system.

After wake-up from STANDBY mode, program execution restarts in the same way as after a RESET, the LED1 restarts toggling, LED2 is turned on and the RTC configuration (clock source, enable, prescaler,...) is kept. As result there is no need to configure the RTC.

Two leds LED1 and LED2 are used to monitor the system state as following:

  • LED1 toggling: system in RUN mode
  • LED1 off / LED2 off: system in STANDBY mode
  • LED2 on: system resumed from STANDBY mode
Directory contents
  • PWR/STANDBY/stm32f10x_conf.h Library Configuration file
  • PWR/STANDBY/stm32f10x_it.c Interrupt handlers
  • PWR/STANDBY/stm32f10x_it.h Header for stm32f10x_it.c
  • PWR/STANDBY/main.c Main program
  • PWR/STANDBY/system_stm32f10x.c STM32F10x system source file
Hardware and Software environment
  • This example runs on STM32F10x Connectivity line, High-Density, High-Density Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density and Low-Density Value line Devices.
  • This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) evaluation boards and can be easily tailored to any other supported device and development board. To select the STMicroelectronics evaluation board used to run the example, uncomment the corresponding line in stm32_eval.h file (under Utilities)
  • STM32100E-EVAL Set-up
    • Use LED1 and LED2 connected respectively to PF.06 and PF.07 pins
    • Use the Key push-button connected to pin PG.08 (EXTI Line8).
    • Use the Wakeup push-button connected to WKUP(PA.00) pin
  • STM32100B-EVAL Set-up
    • Use LED1 and LED2 connected respectively to PC.06 and PC.07 pins
    • Use the Key push-button connected to pin PB.09 (EXTI Line9).
    • Use the Wakeup push-button connected to WKUP(PA.00) pin
  • STM3210C-EVAL Set-up
    • Use LED1 and LED2 connected respectively to PD.07 and PD.13 pins
    • Use the Key push-button connected to pin PB.09 (EXTI Line9).
    • Use the Wakeup push-button connected to WKUP(PA.00) pin, make sure that jumper JP14 is in position 2-3.
  • STM3210E-EVAL Set-up
    • Use LED1 and LED2 connected respectively to PF.06 and PF.07 pins
    • Use the Key push-button connected to pin PG.08 (EXTI Line8).
    • Use the Wakeup push-button connected to WKUP(PA.00) pin
      Note:
      the jumper JP4 must be not fit to be able to use the Wakeup push-button
  • STM3210B-EVAL Set-up
    • Use LED1 and LED2 connected respectively to PC.06 and PC.07 pins
    • Use the Key push-button connected to pin PB.09 (EXTI Line9).
    • Use the Wakeup push-button connected to WKUP(PA.00) pin
Note:
For power consumption measurement in STANDBY mode, you have to replace jumper JP9 in the STM3210B-EVAL board, JP12 in the STM3210E-EVAL or JP23 (position 1-2) in the STM3210C-EVAL board by an amperemeter.
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example in standalone mode (without debugger connection)
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: PWR STOP example

  • STM32F10x Standard Peripheral's Examples

PWR STOP example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    PWR/STOP/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the PWR STOP example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example shows how to enter the system to STOP mode and wake-up using EXTI Line interrupts. The EXTI Line sources are PB.09/PG.08 and RTC Alarm.

The EXTI line9/8 is configured to generate interrupt on falling edge. The EXTI line17(RTC Alarm) is configured to generate interrupt on rising edge and the RTC time base is set to 1 second using the external low speed oscillator(LSE).

The system clock is set to 24 MHz on Value line devices and to 72 MHz on other devices using the external high speed oscillator(HSE).

The system enters and exits STOP mode as following: After 2 second from system start-up, the RTC is configured to generate an Alarm event in 3 second then the system enters STOP mode. To wake-up from STOP mode you have to apply a rising edge on EXTI line9/8, otherwise the RTC Alarm will wake-up the system within 3 second. After exit from STOP the system clock is reconfigured to its previous state (as HSE and PLL are disabled in STOP mode). Then after a delay the system will enter again in STOP mode and exit in the way described above. This behavior is repeated in an infinite loop.

Three leds LED1, LED2 and LED3 are used to monitor the system state as following:

  • LED1 on: system in RUN mode
  • LED1 off: system in STOP mode
  • LED2 is toggled if EXTI Line9/8 is used to exit from STOP
  • LED3 is toggled if EXTI line17(RTC Alarm) is used to exit from STOP
Directory contents
  • PWR/STOP/stm32f10x_conf.h Library Configuration file
  • PWR/STOP/stm32f10x_it.c Interrupt handlers
  • PWR/STOP/stm32f10x_it.h Header for stm32f10x_it.c
  • PWR/STOP/main.c Main program
  • PWR/STOP/system_stm32f10x.c STM32F10x system source file
Hardware and Software environment
  • This example runs on STM32F10x Connectivity line, High-Density, High-Density Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density and Low-Density Value line Devices.
  • This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density Value line),STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) evaluation boards and can be easily tailored to any other supported device and development board. To select the STMicroelectronics evaluation board used to run the example, uncomment the corresponding line in stm32_eval.h file (under Utilities)
  • STM32100E-EVAL Set-up
    • Use LED1, LED2 and LED3 leds connected respectively to PF.06, PF0.7 and PF.08 pins
    • Use the Key push-button connected to pin PG.08 (EXTI Line8).
  • STM32100B-EVAL Set-up
    • Use LED1, LED2 and LED3 leds connected respectively to PC.06, PC.07 and PC.08 pins
    • Use the Key push-button connected to pin PB.09 (EXTI Line9).
  • STM3210C-EVAL Set-up
    • Use LED1, LED2 and LED3 leds connected respectively to PD.07, PD.13 and PF.03 pins
    • Use the Key push-button connected to pin PB.09 (EXTI Line9).
  • STM3210E-EVAL Set-up
    • Use LED1, LED2 and LED3 leds connected respectively to PF.06, PF0.7 and PF.08 pins
    • Use the Key push-button connected to pin PG.08 (EXTI Line8).
  • STM3210B-EVAL Set-up
    • Use LED1, LED2 and LED3 leds connected respectively to PC.06, PC.07 and PC.08 pins
    • Use the Key push-button connected to pin PB.09 (EXTI Line9).
Note:
For power consumption measurement in STOP mode you have to:
  • Modify the example to configure all unused GPIO port pins in Analog Input mode (floating input trigger OFF). Refer to GPIO example for more details.
  • Replace jumper JP9 in the STM3210B-EVAL board, JP12 in the STM3210E-EVAL, JP23 (position 1-2) in the STM3210C-EVAL board or JP8 (position 1-2) in the STM32100B-EVAL board by an amperemeter.
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example in standalone mode (without debugger connection)
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: RCC Clock configuration example

  • STM32F10x Standard Peripheral's Examples

RCC Clock configuration example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    RCC/RCC_ClockConfig/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the RCC Clock configuration example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example shows how to configure the System clock(SYSCLK) to have different frequencies: 24MHz, 36MHz, 48MHz, 56MHz and 72MHz (common frequencies that covers the major of the applications). The SYSCLK frequency is selected by user in main.h file.

It shows how to use, for debug purpose, the RCC_GetClocksFreq function to retrieve the current status and frequencies of different on chip clocks. You can see the RCC_ClockFreq structure content, which hold the frequencies of different on chip clocks, using your toolchain debugger.

This example handles also the High Speed External clock (HSE) failure detection: when the HSE clock disappears (broken or disconnected external Quartz); HSE, PLL are disabled (but no change on PLL config), HSI selected as system clock source and an interrupt (NMI) is generated. In the NMI ISR, the HSE, HSE ready interrupt are enabled and once HSE clock recover, the HSERDY interrupt is generated and in the RCC ISR routine the system clock is reconfigured to its previous state (before HSE clock failure). You can monitor the HSE clock on the MCO pin (PA.08).

Four LEDs are toggled with a timing defined by the Delay function.

Note:
To adjust the External High Speed oscillator (HSE) Startup Timeout value, use HSEStartUp_TimeOut variable defined in the stm32f10x.h file.
Directory contents
  • RCC/RCC_ClockConfig/stm32f10x_conf.h Library Configuration file
  • RCC/RCC_ClockConfig/stm32f10x_it.c Interrupt handlers
  • RCC/RCC_ClockConfig/stm32f10x_it.h Header for stm32f10x_it.c
  • RCC/RCC_ClockConfig/main.h Main header file
  • RCC/RCC_ClockConfig/main.c Main program
  • RCC/RCC_ClockConfig/system_stm32f10x.c STM32F10x system source file
Hardware and Software environment
  • This example runs on STM32F10x Connectivity line, High-Density, High-Density Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density and Low-Density Value line Devices.
  • This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density Value line),STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) evaluation boards and can be easily tailored to any other supported device and development board. To select the STMicroelectronics evaluation board used to run the example, uncomment the corresponding line in stm32_eval.h file (under Utilities)
  • STM32100E-EVAL Set-up
    • Use LED1, LED2, LED3 and LED4 connected respectively to PF.06, PF0.7, PF.08 and PF.09 pins
  • STM32100B-EVAL Set-up
    • Use LED1, LED2, LED3 and LED4 connected respectively to PC.06, PC.07, PC.08 and PC.09 pins
  • STM3210C-EVAL Set-up
    • Use LED1, LED2, LED3 and LED4 connected respectively to PD.07, PD.13, PF.03 and PD.04 pins
  • STM3210E-EVAL Set-up
    • Use LED1, LED2, LED3 and LED4 connected respectively to PF.06, PF0.7, PF.08 and PF.09 pins
  • STM3210B-EVAL Set-up
    • Use LED1, LED2, LED3 and LED4 connected respectively to PC.06, PC.07, PC.08 and PC.09 pins
  • STM32100E-EVAL Set-up
    • Use LED1, LED2, LED3 and LED4 connected respectively to PF.06, PF0.7, PF.08 and PF.09 pins
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: RTC Calendar example

  • STM32F10x Standard Peripheral's Examples

RTC Calendar example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    RTC/Calendar/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the RTC Calendar example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example demonstrates and explains how to use the RTC peripheral. As an application example, it demonstrates how to setup the RTC peripheral, in terms of prescaler and interrupts, to be used to keep time and to generate Second interrupt.

The Low Speed External (LSE) clock is used as RTC clock source. The RTC clock can be output on the Tamper pin (PC.13). To enable this functionality, uncomment the corresponding line: #define RTCClockOutput_Enable in the main.c file.

The RTC is in the backup (BKP) domain, still powered by VBAT when VDD is switched off, so the RTC configuration is not lost if a battery is connected to the VBAT pin. A key value is written in backup data register1 (BKP_DR1) to indicate if the RTC is already configured.

The program behaves as follows:

1. After startup the program checks the backup data register1 value:

  • register1 value not correct: (BKP_DR1 value is not correct or has not yet been programmed when the program is executed for the first time) the RTC is configured and the user is asked to set the time (entered on HyperTerminal).
  • register1 value correct: this means that the RTC is configured and the time is displayed on HyperTerminal.

2. When an External Reset occurs the BKP domain is not reset and the RTC configuration is not lost.

3. When power on reset occurs:

  • If a battery is connected to the VBAT pin: the BKP domain is not reset and the RTC configuration is not lost.
  • If no battery is connected to the VBAT pin: the BKP domain is reset and the RTC configuration is lost.

In the RTC interrupt service routine, the LED1 toggles every 1 s. The C library printf function is retargeted to the USART, that is, the printf message is output to the HyperTerminal using USART1 or USART2 depending on the EVAL board you are using.

Directory contents
  • RTC/Calendar/stm32f10x_conf.h Library Configuration file
  • RTC/Calendar/stm32f10x_it.c Interrupt handlers
  • RTC/Calendar/stm32f10x_it.h Header for stm32f10x_it.c
  • RTC/Calendar/main.c Main program
  • RTC/Calendar/system_stm32f10x.c STM32F10x system source file
Hardware and Software environment
  • This example runs on STM32F10x Connectivity line, High-Density, High-Density Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density and Low-Density Value line Devices.
  • This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) evaluation boards and can be easily tailored to any other supported device and development board. To select the STMicroelectronics evaluation board used to run the example, uncomment the corresponding line in stm32_eval.h file (under Utilities)
  • STM32100E-EVAL Set-up
    • Use LED1 connected to PF.06.
    • Connect a null-modem female/female RS232 cable between the DB9 connector CN10(when USART1 is used) and PC serial port.
    • Make sure that jumper JP1 is in position 1-2 to connect the 3V battery to VBAT pin
  • STM32100B-EVAL Set-up
    • Use LED1 connected to PC.06.
    • Connect a null-modem female/female RS232 cable between the DB9 connector CN10(when USART1 is used) and PC serial port.
    • Make sure that jumper JP9 is in position 1-2 to connect the 3V battery to VBAT pin
  • STM3210C-EVAL Set-up
    • Use LED1 connected to PD.07.
    • Connect a null-modem female/female RS232 cable between the DB9 connector CN6 (USART2) and PC serial port .
      Note:
      Make sure that jumpers JP19 and JP18 are open.
    • Make sure that jumper JP24 is in position 1-2 to connect the 3V battery to VBAT pin
  • STM3210E-EVAL Set-up
    • Use LED1 connected to PF.06.
    • Connect a null-modem female/female RS232 cable between the DB9 connector CN12(when USART1 is used) and PC serial port.
    • Make sure that jumper JP1 is in position 1-2 to connect the 3V battery to VBAT pin
  • STM3210B-EVAL Set-up
    • Use LED1 connected to PC.06.
    • Connect a null-modem female/female RS232 cable between the DB9 connector CN6(when USART1 is used) and PC serial port.
    • Make sure that jumper JP11 is in position 1-2 to connect the 3V battery to VBAT pin
  • Hyperterminal configuration:
    • Word Length = 8 Bits
    • One Stop Bit
    • No parity
    • BaudRate = 115200 baud
    • flow control: None
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: RTC LSI_Calib example

  • STM32F10x Standard Peripheral's Examples

RTC LSI_Calib example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    RTC/LSI_Calib/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the RTC LSI_Calib example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example demonstrates and explains how to use the LSI clock source auto calibration to get a precise RTC clock. As an application example, it demonstrates how to configure the TIM5 timer internally connected to LSI clock output, in order to adjust the RTC prescaler.

The Low Speed External (LSI) clock is used as RTC clock source. After reset, the RTC prescaler is set with the default value (40000). The inaccuracy of the LSI clock causes the RTC Second signal to be inaccurate. This signal is output on the Tamper pin (PC.13) and can be measured by on oscilloscope or a frequencymeter.

The program waits until Key Push button is pressed to begin the auto calibration procedure:

  • Configure the TIM5 to remap internally the TIM5 Channel 4 Input Capture to the LSI clock output.
  • Enable the TIM5 Input Capture interrupt: after one cycle of LSI clock, the period value is stored in a variable and compared to the HCLK clock to get its real value.
  • The RTC prescaler is adjusted with this LSI frequency value so that the RTC Second value become more accurate.
  • When calibration is done a led connected to PF.07 is turned ON to indicate the end of this operation. At this moment, you can monitor the Second signal on an oscilloscope to measure its accuracy again.

The RTC Second signal can be monitored either on Tamper pin or on LED1 which is toggled into the RTC Second interrupt service routine.

Directory contents
  • RTC/LSI_Calib/stm32f10x_conf.h Library Configuration file
  • RTC/LSI_Calib/stm32f10x_it.c Interrupt handlers
  • RTC/LSI_Calib/stm32f10x_it.h Header for stm32f10x_it.c
  • RTC/LSI_Calib/main.h Main header file
  • RTC/LSI_Calib/main.c Main program
  • RTC/LSI_Calib/system_stm32f10x.c STM32F10x system source file
Hardware and Software environment
  • This example runs on STM32F10x Connectivity line, High-Density Value line, High-Density and XL-Density Devices.
  • This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density Value line), STM3210E-EVAL (High-Density and XL-Density) and STM3210C-EVAL (Connectivity Line) evaluation boards and can be easily tailored to any other supported device and development board. To select the STMicroelectronics evaluation board used to run the example, uncomment the corresponding line in stm32_eval.h file (under Utilities)
  • STM32100E-EVAL Set-up
    • Use LD1 and LD2 leds connected respectively to PF.06 and PF.07 pins
    • Use the Key push button connected to PG.08 pin
  • STM3210C-EVAL Set-up
    • Use LD1 and LD2 leds connected respectively to PD.07 and PD.13 pins
    • Use the Key push-button connected to PB.09 pin
  • STM3210E-EVAL Set-up
    • Use LD1 and LD2 leds connected respectively to PF.06 and PF.07 pins
    • Use the Key push button connected to PG.08 pin
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: SDIO Micro SD Card example

  • STM32F10x Standard Peripheral's Examples

SDIO Micro SD Card example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    SDIO/uSDCard/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the SDIO Micro SD Card example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example provides a basic example of how to use the SDIO firmware library and an associate driver to perform read/write operations on the SD Card memory (SD Card V1.0, V1.1, V2.0 and SDHC (High Capacity) protocol)that could be mounted on the STM3210E-EVAL board.

The example provides different SD Card transfer states and operations and here below a description of each step:

  • First the SDIO peripheral and SD Card are initialized using the SD_Init() function:
    • Configure the SDIO according to the desired SDIO_CK clock frequency.
    • Reset the SD Card
    • Identify the SD Card
    • Initializes the SD Card
    • Get the SD Card Info
    • Select the SD Card
    • Enable the Wide Bus mode (4-bit data)
  • SD Card Erase Operation
    • Starts an Erase operation: Erase the corresponding blocks using the SD_Erase() function
    • Read the Erased blocks using the SD_ReadMultiBlocks() function
    • Test if the corresponding Blocks are well erased: check if the EraseStatus variable is equal to PASSED. If the erase operation is passed LED1 is turned ON.
  • SD Card Single Block Operation
    • Starts a Write operation: Write a single Block using the SD_WriteBlock() function
    • Read a single Block using the SD_ReadBlock() function
    • Compare the written Block and the read one: check if the TransferStatus1 variable is equal to PASSED. If the Single Block Read/write operation is passed LED2 is turned ON.
  • SD Card Multiple Block Operation
    • Starts a Multiple Write operation: Write a multi Blocks using the SD_WriteMultiBlocks() function.
    • Read a multiple Blocks using the SD_ReadMultiBlocks() function
    • Compare the written Blocks and the read one: check if the TransferStatus2 variable is equal to PASSED. If the Multiple Blocks Read/Write operation is passed LED3 is turned ON.

All data transfers are made by DMA. At each operation, the SD Card presence and status is checked using the SD_GetStatus() function and a global variable "Status" storing the results of the last operation.

SD Card Operations and Written/Read data correctness is signaled by LED lightening and though as follow:

  • If the Erase operation is PASSED then LED1 ON else the LED4 is ON and LED1 is OFF
  • If the Single Block Write/Read operation is PASSED then LED2 ON else the LED4 is ON and LED2 is OFF
  • If the Multi Blocks Write/Read operation is PASSED then LED3 ON else the LED4 is ON and LED3 is OFF
  • Any SD Card operation including the SD Initialization error is signaled by LED4 ON.
Directory contents
  • SDIO/uSDCard/stm32f10x_conf.h Library Configuration file
  • SDIO/uSDCard/stm32f10x_it.c Interrupt handlers
  • SDIO/uSDCard/stm32f10x_it.h Header for stm32f10x_it.c
  • SDIO/uSDCard/main.c Main program
  • SDIO/uSDCard/system_stm32f10x.c STM32F10x system source file
Hardware and Software environment
  • This example runs only on STM32F10x High-Density and XL-Density Devices.
  • This example has been tested with STMicroelectronics STM3210E-EVAL (High-Density and XL-Density) evaluation board and can be easily tailored to any other supported device and development board.
Note:
Make sure that the Jumper 17 (JP17) is closed and Jumper 20 (JP20) is open in STM3210E-EVAL
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: SPI CRC example

  • STM32F10x Standard Peripheral's Examples

SPI CRC example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    SPI/CRC/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the SPI CRC example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example provides a description of how to set a communication between two SPIs in full-duplex mode and performs a transfer from Master to Slave and Slave to Master followed by CRC transmission.

SPI1 is configured as master and SPI2 as slave and both are in full-duplex configuration mode with 16bit data size and a 4.5 Mbit/s communication speed (for Value line devices the speed is set at 1.5 Mbit/s). CRC calculation is enabled for both SPIs.

After enabling both SPIs, the first data from SPI2_Buffer_Tx is transmitted from slave followed by the first data from SPI1_Buffer_Tx send by the master. A test on RxNE flag is done for both master and slave to check the reception of data on their respective data register. The same procedure is done for the remaining data to transfer except the last ones.

Last data from SPI1_Buffer_Tx is transmitted followed by enabling CRC transmission for SPI1 and the last data from SPI2_Buffer_Tx is transmitted followed by enabling CRC transmission for SPI2: user must take care to reduce code on this phase for high speed communication.

Last transmitted buffer data and CRC value are then received successively on master and slave data registers. The received CRC value are stored on CRC1Value and CRC2Value respectively for SPI1 and SPI2.

Once the transfer is completed a comparison is done and TransferStatus1 and TransferStatus2 gives the data transfer status for each data transfer direction where it is PASSED if transmitted and received data are the same otherwise it is FAILED. A check of CRC error flag, for the master and the salve, is done after receiving CRC data.

Directory contents
  • SPI/CRC/stm32f10x_conf.h Library Configuration file
  • SPI/CRC/stm32f10x_it.c Interrupt handlers
  • SPI/CRC/stm32f10x_it.h Header for stm32f10x_it.c
  • SPI/CRC/main.c Main program
  • SPI/CRC/system_stm32f10x.c STM32F10x system source file
Hardware and Software environment
  • This example runs on STM32F10x Connectivity line, High-Density, High-Density Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density and Low-Density Value line Devices.
  • This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density Value line), STM32100B-EVAL(STM32F10x Medium-Density Value line), STM3210E-EVAL (STM32F10x High-Density) and STM3210B-EVAL (STM32F10x Medium-Density) evaluation boards and can be easily tailored to any other supported device and development board. This example can't be tested with STMicroelectronics STM3210C-EVAL (STM32F10x Connectivity Line) evaluation board.
  • STM32100E-EVAL Set-up
    • Connect SPI1 SCK (PA.05) pin to SPI2 SCK (PB.13) pin
    • Connect SPI1 MISO (PA.06) pin to SPI2 MISO (PB.14) pin
    • Connect SPI1 MOSI (PA.07) pin to SPI2 MOSI (PB.15) pin
  • STM32100B-EVAL Set-up
    • Connect SPI1 SCK (PA.05) pin to SPI2 SCK (PB.13) pin
    • Connect SPI1 MISO (PA.06) pin to SPI2 MISO (PB.14) pin
    • Connect SPI1 MOSI (PA.07) pin to SPI2 MOSI (PB.15) pin
  • STM3210E-EVAL Set-up
    • Connect SPI1 SCK (PA.05) pin to SPI2 SCK (PB.13) pin
    • Connect SPI1 MISO (PA.06) pin to SPI2 MISO (PB.14) pin
    • Connect SPI1 MOSI (PA.07) pin to SPI2 MOSI (PB.15) pin
      Note:
      The jumper 14 (USB Disconnect) must be set in position 1<->2 in order to not interfer with SPI2 MISO pin PB14.
  • STM3210B-EVAL Set-up
    • Connect SPI1 SCK (PA.05) pin to SPI2 SCK (PB.13) pin
    • Connect SPI1 MISO (PA.06) pin to SPI2 MISO (PB.14) pin
    • Connect SPI1 MOSI (PA.07) pin to SPI2 MOSI (PB.15) pin
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: SPI Full Duplex Software NSS example

  • STM32F10x Standard Peripheral's Examples

SPI Full Duplex Software NSS example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    SPI/FullDuplex_SoftNSS/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the SPI Full Duplex Software NSS example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example provides a description of how to set a communication between SPIy and SPIz in full-duplex mode and performs a transfer from Master to Slave and then Slave to Master in the same application with software NSS management. SPIy and SPIz can be SPI1 and SPI2 or SPI3 and SPI2, depending on the STMicroelectronics EVAL board you are using.

Both SPIs are configured with 8bit data frame and a 9Mbit/s communication speed. (for Value line devices the speed is set at 6Mbit/s). In the first phase, the master SPIy starts the SPIy_Buffer_Tx transfer while the slave SPIz transmit SPIz_Buffer_Tx. Once the transfer is completed a comparison is done and TransferStatus1 and TransferStatus2 gives the data transfer status for each data transfer direction where it is PASSED if transmitted and received data are the same otherwise it is FAILED.

As the NSS pin is managed by software, this permit to SPIy to become slave and SPIz to become master without hardware modification. In the second step, the slave SPIy starts the SPIy_Buffer_Tx transfer while the master SPIz transmit SPIz_Buffer_Tx. Once the transfer is completed a comparison is done and TransferStatus3 and TransferStatus4 gives the data transfer status for each data transfer direction where it is PASSED if transmitted and received data are the same otherwise it is FAILED.

Directory contents
  • SPI/FullDuplex_SoftNSS/platform_config.h Evaluation board specific configuration file
  • SPI/FullDuplex_SoftNSS/stm32f10x_conf.h Library Configuration file
  • SPI/FullDuplex_SoftNSS/stm32f10x_it.c Interrupt handlers
  • SPI/FullDuplex_SoftNSS/stm32f10x_it.h Interrupt handlers header file
  • SPI/FullDuplex_SoftNSS/main.c Main program
  • SPI/FullDuplex_SoftNSS/system_stm32f10x.c STM32F10x system source file
Hardware and Software environment
  • This example runs on STM32F10x Connectivity line, High-Density, High-Density Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density and Low-Density Value line Devices.
  • This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) evaluation boards and can be easily tailored to any other supported device and development board. To select the STMicroelectronics evaluation board used to run the example, uncomment the corresponding line in SPI/FullDuplex_SoftNSS/platform_config.h file.
  • STM32100E-EVAL Set-up
    • Connect SPI1 SCK pin (PA.05) to SPI2 SCK pin (PB.13)
    • Connect SPI1 MISO pin (PA.06) to SPI2 MISO pin (PB.14)
    • Connect SPI1 MOSI pin (PA.07) to SPI2 MOSI pin (PB.15)
  • STM32100B-EVAL Set-up
    • Connect SPI1 SCK pin (PA.05) to SPI2 SCK pin (PB.13)
    • Connect SPI1 MISO pin (PA.06) to SPI2 MISO pin (PB.14)
    • Connect SPI1 MOSI pin (PA.07) to SPI2 MOSI pin (PB.15)
  • STM3210C-EVAL Set-up
    • Connect SPI3 SCK pin (PC.10) to SPI2 SCK pin (PB.13)
    • Connect SPI3 MISO pin (PC.11) to SPI2 MISO pin (PB.14)
    • Connect SPI3 MOSI pin (PC.12) to SPI2 MOSI pin (PB.15)
      Note:
      In this case SPI3 pins are remapped by software.
  • STM3210E-EVAL Set-up
    • Connect SPI1 SCK pin (PA.05) to SPI2 SCK pin (PB.13)
    • Connect SPI1 MISO pin (PA.06) to SPI2 MISO pin (PB.14)
    • Connect SPI1 MOSI pin (PA.07) to SPI2 MOSI pin (PB.15)
      Note:
      The jumper 14 (USB Disconnect) must be set in position 1<->2 in order to not interfer with SPI2 MISO pin PB14.
  • STM3210B-EVAL Set-up
    • Connect SPI1 SCK pin (PA.05) to SPI2 SCK pin (PB.13)
    • Connect SPI1 MISO pin (PA.06) to SPI2 MISO pin (PB.14)
    • Connect SPI1 MOSI pin (PA.07) to SPI2 MOSI pin (PB.15)
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: SPI SPI_FLASH example

  • STM32F10x Standard Peripheral's Examples

SPI SPI_FLASH example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    SPI/SPI_FLASH/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the SPI SPI_FLASH example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example provides a basic example of how to use the SPI firmware library and an associate SPI FLASH driver to communicate with an M25P64 or M25P128 FLASH.

The first step consist in reading the SPI Flash ID. A comparison between the ID read from SPI flash and the expected one is done and LED1 is turned on in case of success otherwise LED2 is turned on.

Using this driver the program performs an erase of the sector to be accessed, a write of a Tx_Buffer, defined in the main.c file, to the memory followed by a read of the written data. Then data read from the memory stored in the Rx_Buffer are compared with the expected values of the Tx_Buffer. The result of this comparison is stored in the "TransferStatus1" variable.

A second erase of the same sector is done at the end, and a test is done to be sure that all the data written there are erased further to the sector erase. All the data location are read and checked with 0xFF value. The result of this test is stored in "TransferStatus2" variable which is FAILED in case of error.

The SPI1 is configured as Master with an 8-bit data size. The SPI1 baudrate is set to 18 Mbit/s (for Value line devices the baudrate is set to 12 Mbit/s). The FLASH_WriteAddress and the FLASH_ReadAddress where the program start the write and the read operations are defined in the main.c file.

Directory contents
  • SPI/SPI_FLASH/stm32f10x_conf.h Library Configuration file
  • SPI/SPI_FLASH/stm32f10x_it.c Interrupt handlers
  • SPI/SPI_FLASH/stm32f10x_it.h Header for stm32f10x_it.c
  • SPI/SPI_FLASH/main.c Main program
  • SPI/SPI_FLASH/system_stm32f10x.c STM32F10x system source file
Hardware and Software environment
  • This example runs on STM32F10x Connectivity line, High-Density, High-Density Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density and Low-Density Value line Devices.
  • This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density Value line), STM32100B-EVAL (Medium-Density Value line), STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) evaluation boards and can be easily tailored to any other supported device and development board. This example can't be tested with STM3210C-EVAL (Connectivity Line) evaluation board (no SPI FLASH available). To select the STMicroelectronics evaluation board used to run the example, uncomment the corresponding line in stm32_eval.h file.
  • STM32100E-EVAL Set-up
    • Use LED1 and LED2 connected respectively to PF.06 and PF.07 pins
    • M25P128 FLASH is already available on this board.
      Note:
  • The SPI FLASH example is only working on STM32100E-EVAL Rev B.
  • STM32100B-EVAL Set-up
    • Use LED1 and LED2 connected respectively to PC.06 and PC.07 pins
    • M25P128 FLASH is already available on this board.
  • STM3210E-EVAL Set-up
    • Use LED1 and LED2 connected respectively to PF.06 and PF.07 pins
    • M25P64 FLASH is already available on this board.
      Note:
      The jumper 14 (USB Disconnect) must be set in position 1<->2 in order to not interfere with SPI2 MISO pin PB14.
  • STM3210B-EVAL Set-up
    • Use LED1 and LED2 connected respectively to PC.06 and PC.07 pins
    • M25P64 FLASH is already available on this board.
  • Other platform Set-up
    • Use STM3210B-EVAL hardware configuration defines.
    • Connect LED1 and LED2 respectively to PD.07 and PD.13 pins
    • Connect both SPI1 and SPI FLASH pins as following:
      • Connect SPI1_NSS (PA.04) pin to SPI Flash chip select (pin1)
      • Connect SPI1_SCLK (PA.05) pin to SPI Flash serial clock (pin6)
      • Connect SPI1_MISO (PA.06) pin to SPI Flash serial data output (pin2)
      • Connect SPI1_MOSI (PA.07) pin to SPI Flash serial data input (pin5)
      • Connect SPI Flash Write Protect (pin3) to Vdd
      • Connect SPI Flash Hold (pin7) to Vdd
      • Connect SPI Flash Vcc (pin8) to Vdd
      • Connect SPI Flash Vss (pin4) to Vss
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: SPI Simplex Interrupt example

  • STM32F10x Standard Peripheral's Examples

SPI Simplex Interrupt example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    SPI/Simplex_Interrupt/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the SPI Simplex Interrupt example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example provides a description of how to set a communication between two SPIs in simplex mode and performs a data buffer transfer from SPI_MASTER to SPI_SLAVE using TxE interrupt for master and RxNE interrupt for slave. SPI_MASTER and SPI_SLAVE can be SPI1 and SPI2 or SPI3 and SPI2, depending on the STMicroelectronics EVAL board you are using.

Both SPIs are configured with 8bit data frame and a 9Mbit/s communication speed (for Value line devices the communication speed is set to 3Mbit/s). The TxE interrupt is enabled for the master and the RxNE interrupt is enabled for the slave.

Once both SPIs are enabled, first TxE interrupt is generated for the master and in its interrupt service routine the first data is sent from SPI_MASTER_Buffer_Tx. Once this data is received by the slave the RxNE interrupt is generated and in the routine this data is stored in the SPI_SLAVE_Buffer_Rx.

The same procedure is followed for the remaining SPI_MASTER_Buffer_Tx data. Once all data buffer are received by the slave the TxE interrupt is disabled. A comparison is done and TransferStatus variable gives the data transfer status where it is PASSED if transmitted and received data are the same otherwise it is FAILED.

Directory contents
  • SPI/Simplex_Interrupt/platform_config.h Evaluation board specific configuration file
  • SPI/Simplex_Interrupt/stm32f10x_conf.h Library Configuration file
  • SPI/Simplex_Interrupt/stm32f10x_it.c Interrupt handlers
  • SPI/Simplex_Interrupt/stm32f10x_it.h Header for stm32f10x_it.c
  • SPI/Simplex_Interrupt/main.c Main program
  • SPI/Simplex_Interrupt/system_stm32f10x.c STM32F10x system source file
Hardware and Software environment
  • This example runs on STM32F10x Connectivity line, High-Density, High-Density Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density and Low-Density Value line Devices.
  • This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) evaluation boards and can be easily tailored to any other supported device and development board. To select the STMicroelectronics evaluation board used to run the example, uncomment the corresponding line in SPI/Simplex_Interrupt/platform_config.h file.
  • STM32100E-EVAL Set-up
    • Connect SPI1 SCK pin (PA.05) to SPI2 SCK pin (PB.13)
    • Connect SPI1 MOSI pin (PA.07) to SPI2 MISO pin (PB.14)
  • STM32100B-EVAL Set-up
    • Connect SPI1 SCK pin (PA.05) to SPI2 SCK pin (PB.13)
    • Connect SPI1 MOSI pin (PA.07) to SPI2 MISO pin (PB.14)
  • STM3210C-EVAL Set-up
    • Connect SPI3 SCK pin (PC.10) to SPI2 SCK pin (PB.13)
    • Connect SPI3 MOSI pin (PC.12) to SPI2 MISO pin (PB.14)
      Note:
      In this case SPI3 pins are remapped by software.
  • STM3210E-EVAL Set-up
    • Connect SPI1 SCK pin (PA.05) to SPI2 SCK pin (PB.13)
    • Connect SPI1 MOSI pin (PA.07) to SPI2 MISO pin (PB.14)
      Note:
      The jumper 14 (USB Disconnect) must be set in position 1<->2 in order to not interfer with SPI2 MISO pin PB14.
  • STM3210B-EVAL Set-up
    • Connect SPI1 SCK pin (PA.05) to SPI2 SCK pin (PB.13)
    • Connect SPI1 MOSI pin (PA.07) to SPI2 MISO pin (PB.14)
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: SysTick Time Base example

  • STM32F10x Standard Peripheral's Examples

SysTick Time Base example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    SysTick/TimeBase/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the SysTick Time Base example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example shows how to configure the SysTick to generate a time base equal to 1 ms. The system clock is set to 24 MHz on Value line devices and to 72 MHz on other devices, the SysTick is clocked by the AHB clock (HCLK).

A "Delay" function is implemented based on the SysTick end-of-count event. Four LEDs are toggled with a timing defined by the Delay function.

Directory contents
  • SysTick/TimeBase/stm32f10x_conf.h Library Configuration file
  • SysTick/TimeBase/stm32f10x_it.c Interrupt handlers
  • SysTick/TimeBase/stm32f10x_it.h Header for stm32f10x_it.c
  • SysTick/TimeBase/main.c Main program
  • SysTick/TimeBase/main.h Header for main.c
  • SysTick/TimeBase/system_stm32f10x.c STM32F10x system source file
Hardware and Software environment
  • This example runs on STM32F10x Connectivity line, High-Density, High-Density Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density and Low-Density Value line Devices.
  • This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) evaluation boards and can be easily tailored to any other supported device and development board. To select the STMicroelectronics evaluation board used to run the example, uncomment the corresponding line in stm32_eval.h file (under Utilities)
  • STM32100E-EVAL Set-up
    • Use LED1, LED2, LED3 and LED4 connected respectively to PF.06, PF0.7, PF.08 and PF.09 pins
  • STM32100B-EVAL Set-up
    • Use LED1, LED2, LED3 and LED4 connected respectively to PC.06, PC.07, PC.08 and PC.09 pins
  • STM3210C-EVAL Set-up
    • Use LED1, LED2, LED3 and LED4 connected respectively to PD.07, PD.13, PF.03 and PD.04 pins
  • STM3210E-EVAL Set-up
    • Use LED1, LED2, LED3 and LED4 connected respectively to PF.06, PF0.7, PF.08 and PF.09 pins
  • STM3210B-EVAL Set-up
    • Use LED1, LED2, LED3 and LED4 connected respectively to PC.06, PC.07, PC.08 and PC.09 pins
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: TIM 6 Steps example

  • STM32F10x Standard Peripheral's Examples

TIM 6 Steps example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    TIM/6Steps/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the TIM 6 Steps example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example shows how to configure the TIM1 peripheral to generate 6 Steps. The STM32F10x TIM1 peripheral offers the possibility to program in advance the configuration for the next TIM1 outputs behaviour (step) and change the configuration of all the channels at the same time. This operation is possible when the COM (commutation) event is used. The COM event can be generated by software by setting the COM bit in the TIM1_EGR register or by hardware (on TRC rising edge). In this example, a software COM event is generated each 100 ms: using the SysTick interrupt. The TIM1 is configured in Timing Mode, each time a COM event occurs, a new TIM1 configuration will be set in advance.

The break Polarity is used at High level.

The following Table describes the TIM1 Channels states:

              -----------------------------------------------
             | Step1 | Step2 | Step3 | Step4 | Step5 | Step6 |
   ----------------------------------------------------------
  |Channel1  |   1   |   0   |   0   |   0   |   0   |   1   |
   ----------------------------------------------------------
  |Channel1N |   0   |   0   |   1   |   1   |   0   |   0   |
   ----------------------------------------------------------
  |Channel2  |   0   |   0   |   0   |   1   |   1   |   0   |
   ----------------------------------------------------------
  |Channel2N |   1   |   1   |   0   |   0   |   0   |   0   |
   ----------------------------------------------------------
  |Channel3  |   0   |   1   |   1   |   0   |   0   |   0   |
   ----------------------------------------------------------
  |Channel3N |   0   |   0   |   0   |   0   |   1   |   1   |
   ----------------------------------------------------------
Directory contents
  • TIM/6Steps/stm32f10x_conf.h Library Configuration file
  • TIM/6Steps/stm32f10x_it.c Interrupt handlers
  • TIM/6Steps/stm32f10x_it.h Interrupt handlers header file
  • TIM/6Steps/main.c Main program
  • TIM/6Steps/system_stm32f10x.c STM32F10x system source file
Hardware and Software environment
  • This example runs on STM32F10x Connectivity line, High-Density, High-Density Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density and Low-Density Value line Devices.
  • This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) evaluation boards and can be easily tailored to any other supported device and development board.
  • STM3210C-EVAL Set-up
    • Connect the TIM1 pins(TIM1 full remapped pins) to an oscilloscope to monitor the different waveforms:
      • TIM1_CH3 pin (PE.13)
      • TIM1_CH1N pin (PE.08)
      • TIM1_CH2 pin (PE.11)
      • TIM1_CH3N pin (PE.12)
      • TIM1_CH1 pin (PE.09)
      • TIM1_CH2N pin (PE.10)
    • Connect the TIM1 break pin TIM1_BKIN pin (PE.15) to the GND. To generate a break event, switch this pin level from 0V to 3.3V.
  • STM3210E-EVAL, STM3210B-EVAL, STM32100B-EVAL and STM32100E-EVAL Set-up
    • Connect the TIM1 pins to an oscilloscope to monitor the different waveforms:
      • TIM1_CH3 pin (PA.10)
      • TIM1_CH1N pin (PB.13)
      • TIM1_CH2 pin (PA.09)
      • TIM1_CH3N pin (PB.15)
      • TIM1_CH1 pin (PA.08)
      • TIM1_CH2N pin (PB.14)
    • Connect the TIM1 break pin TIM1_BKIN pin (PB.12) to the GND. To generate a break event, switch this pin level from 0V to 3.3V.
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: TIM 7 PWM Output example

  • STM32F10x Standard Peripheral's Examples

TIM 7 PWM Output example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    TIM/7PWM_Output/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the TIM 7 PWM Output example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example shows how to configure the TIM1 peripheral to generate 7 PWM signals with 4 different duty cycles (50%, 37.5%, 25% and 12.5%).

TIM1CLK = SystemCoreClock, Prescaler = 0, TIM1 counter clock = SystemCoreClock SystemCoreClock is set to 72 MHz for Low-density, Medium-density, High-density and Connectivity line devices. For Low-Density Value line, Medium-Density and High-density Value line devices, SystemCoreClock is set to 24 MHz.

The objective is to generate 7 PWM signal at 17.57 KHz:

  • TIM1_Period = (SystemCoreClock / 17570) - 1 The channel 1 and channel 1N duty cycle is set to 50% The channel 2 and channel 2N duty cycle is set to 37.5% The channel 3 and channel 3N duty cycle is set to 25% The channel 4 duty cycle is set to 12.5% The Timer pulse is calculated as follows:
  • ChannelxPulse = DutyCycle * (TIM1_Period - 1) / 100

The TIM1 waveform can be displayed using an oscilloscope.

Directory contents
  • TIM/7PWM_Output/stm32f10x_conf.h Library Configuration file
  • TIM/7PWM_Output/stm32f10x_it.c Interrupt handlers
  • TIM/7PWM_Output/stm32f10x_it.h Interrupt handlers header file
  • TIM/7PWM_Output/main.c Main program
  • TIM/7PWM_Output/system_stm32f10x.c STM32F10x system source file
Hardware and Software environment
  • This example runs on STM32F10x Connectivity line, High-Density, High-Density Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density and Low-Density Value line Devices.
  • This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) evaluation boards and can be easily tailored to any other supported device and development board.
  • STM3210C-EVAL Set-up
    • Connect the TIM1 pins(TIM1 full remapped pins) to an oscilloscope to monitor the different waveforms:
      • TIM1_CH1 pin (PE.08)
      • TIM1_CH1N pin (PE.09)
      • TIM1_CH2 pin (PE.10)
      • TIM1_CH2N pin (PE.11)
      • TIM1_CH3 pin (PE.12)
      • TIM1_CH3N pin (PE.13)
      • TIM1_CH4 pin (PE.14)
  • STM3210E-EVAL, STM3210B-EVAL, STM32100B-EVAL and STM32100E-EVAL Set-up
    • Connect the TIM1 pins to an oscilloscope to monitor the different waveforms:
      • TIM1_CH1 pin (PA.08)
      • TIM1_CH1N pin (PB.13)
      • TIM1_CH2 pin (PA.09)
      • TIM1_CH2N pin (PB.14)
      • TIM1_CH3 pin (PA.10)
      • TIM1_CH3N pin (PB.15)
      • TIM1_CH4 pin (PA.11)
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: TIM Cascade Synchro example

  • STM32F10x Standard Peripheral's Examples

TIM Cascade Synchro example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    TIM/Cascade_Synchro/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the TIM Cascade Synchro example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example shows how to synchronize TIM peripherals in cascade mode. In this example three timers are used:

Timers synchronisation in cascade mode:

1/TIM2 is configured as Master Timer:

  • PWM Mode is used
  • The TIM2 Update event is used as Trigger Output

2/TIM3 is slave for TIM2 and Master for TIM4,

  • PWM Mode is used
  • The ITR1(TIM2) is used as input trigger
  • Gated mode is used, so start and stop of slave counter are controlled by the Master trigger output signal(TIM2 update event).
  • The TIM3 Update event is used as Trigger Output.

3/TIM4 is slave for TIM3,

  • PWM Mode is used
  • The ITR2(TIM3) is used as input trigger
  • Gated mode is used, so start and stop of slave counter are controlled by the Master trigger output signal(TIM3 update event).

o For Low-density, Medium-density, High-density and Connectivity line devices: The TIMxCLK is fixed to 72 MHz, the TIM2 counter clock is 72 MHz.

The Master Timer TIM2 is running at TIM2 frequency : TIM2 frequency = (TIM2 counter clock)/ (TIM2 period + 1) = 281.250 KHz and the duty cycle = TIM2_CCR1/(TIM2_ARR + 1) = 25%.

The TIM3 is running at: (TIM2 frequency)/ (TIM3 period + 1) = 70.312 KHz and a duty cycle equal to TIM3_CCR1/(TIM3_ARR + 1) = 25%

The TIM4 is running at: (TIM3 frequency)/ (TIM4 period + 1) = 17.578 Hz and a duty cycle equal to TIM4_CCR1/(TIM4_ARR + 1) = 25%

o For Low-Density Value line, Medium-Density and High-Density Value line devices: The TIMxCLK is fixed to 24 MHz, the TIM2 counter clock is 24 MHz. So TIM2 frequency = 93.750 KHz, TIM3 is running at 23.437 KHz, and TIM4 is running at 5.85 KHz

Directory contents
  • TIM/Cascade_Synchro/stm32f10x_conf.h Library Configuration file
  • TIM/Cascade_Synchro/stm32f10x_it.c Interrupt handlers
  • TIM/Cascade_Synchro/stm32f10x_it.h Interrupt handlers header file
  • TIM/Cascade_Synchro/main.c Main program
  • TIM/Cascade_Synchro/system_stm32f10x.c STM32F10x system source file
Hardware and Software environment
  • This example runs on STM32F10x Connectivity line, High-Density, High-Density Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density and Low-Density Value line Devices.
  • This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) evaluation boards and can be easily tailored to any other supported device and development board.
  • STM3210C-EVAL Set-up
    • Connect the following pins to an oscilloscope to monitor the different waveforms:
      • TIM2 CH1 (PA.00)
      • TIM3 CH1 (PC.06) Remapped pin
      • TIM4 CH1 (PB.06)
  • STM3210E-EVAL, STM3210B-EVAL, STM32100B-EVAL and STM32100E-EVAL Set-up
    • Connect the following pins to an oscilloscope to monitor the different waveforms:
      • TIM2 CH1 (PA.00)
      • TIM3 CH1 (PA.06)
      • TIM4 CH1 (PB.06)
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: TIM Complementary Signals example

  • STM32F10x Standard Peripheral's Examples

TIM Complementary Signals example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    TIM/ComplementarySignals/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the TIM Complementary Signals example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example shows how to configure the TIM1 peripheral to generate three complementary TIM1 signals, to insert a defined dead time value, to use the break feature and to lock the desired parameters.

TIM1CLK is fixed to SystemCoreClock, the TIM1 Prescaler is equal to 0 so the TIM1 counter clock used is SystemCoreClock. SystemCoreClock is set to 72 MHz for Low-density, Medium-density, High-density and Connectivity line devices. For Low-Density Value line, Medium-Density and High-Density Value line devices, SystemCoreClock is set to 24 MHz.

The objective is to generate PWM signal at 17.57 KHz:

  • TIM1_Period = (SystemCoreClock / 17570) - 1

The Three Duty cycles are computed as the following description: The channel 1 duty cycle is set to 50% so channel 1N is set to 50%. The channel 2 duty cycle is set to 25% so channel 2N is set to 75%. The channel 3 duty cycle is set to 12.5% so channel 3N is set to 87.5%. The Timer pulse is calculated as follows:

  • ChannelxPulse = DutyCycle * (TIM1_Period - 1) / 100

A dead time equal to 11/SystemCoreClock is inserted between the different complementary signals, and the Lock level 1 is selected. The break Polarity is used at High level.

The TIM1 waveform can be displayed using an oscilloscope.

Directory contents
  • TIM/ComplementarySignals/stm32f10x_conf.h Library Configuration file
  • TIM/ComplementarySignals/stm32f10x_it.c Interrupt handlers
  • TIM/ComplementarySignals/stm32f10x_it.h Interrupt handlers header file
  • TIM/ComplementarySignals/main.c Main program
  • TIM/ComplementarySignals/system_stm32f10x.c STM32F10x system source file
Hardware and Software environment
  • This example runs on STM32F10x Connectivity line, High-Density, High-Density Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density and Low-Density Value line Devices.
  • This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) evaluation boards and can be easily tailored to any other supported device and development board.
  • STM3210C-EVAL Set-up
    • Connect the TIM1 pins(TIM1 full remapped pins) to an oscilloscope to monitor the different waveforms:
      • TIM1_CH1 pin (PE.09)
      • TIM1_CH1N pin (PE.08)
      • TIM1_CH2 pin (PE.11)
      • TIM1_CH1N pin (PE.10)
      • TIM1_CH3 pin (PE.13)
      • TIM1_CH3N pin (PE.12)
    • Connect the TIM1 break pin TIM1_BKIN pin (PE.15) to the GND. To generate a break event, switch this pin level from 0V to 3.3V.
  • STM3210E-EVAL, STM3210B-EVAL, STM32100B-EVAL and STM32100E-EVAL Set-up
    • Connect the TIM1 pins to an oscilloscope to monitor the different waveforms:
      • TIM1_CH1 pin (PA.08)
      • TIM1_CH1N pin (PB.13)
      • TIM1_CH2 pin (PA.09)
      • TIM1_CH2N pin (PB.14)
      • TIM1_CH3 pin (PA.10)
      • TIM1_CH3N pin (PB.15)
  • Connect the TIM1 break pin TIM1_BKIN pin (PB.12) to the GND. To generate a break event, switch this pin level from 0V to 3.3V.
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: TIM1 DMA Burst transfer example

  • STM32F10x Standard Peripheral's Examples

TIM1 DMA Burst transfer example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    TIM/DMABurst/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the TIM1 DMA Burst transfer example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example shows how to update the TIM1 channel1 period and the duty cycle using the TIM1 DMA burst feature.

Every update DMA request, the DMA will do 3 transfers of half words into Timer registers beginning from ARR register. On the DMA update request, 0x0FFF will be transferred into ARR, 0x0000 will be transferred into RCR, 0x0555 will be transferred into CCR1.

The TIM1CLK frequency is set to SystemCoreClock (Hz), to get TIM1 counter clock at 24 MHz the Prescaler is computed as following:

  • Prescaler = (TIM1CLK / TIM1 counter clock) - 1 SystemCoreClock is set to 72 MHz for Low-density, Medium-density, High-density and Connectivity line devices and to 24 MHz for Value line devices.

The TIM1 period is 5.8 KHz: TIM1 Frequency = TIM1 counter clock/(ARR + 1) = 24 MHz / 4096 = 5.8 KHz The TIM1 CCR1 register value is equal to 0x555, so the TIM1 Channel 1 generates a PWM signal with a frequency equal to 5.8 KHz and a duty cycle equal to 33.33%: TIM1 Channel1 duty cycle = (TIM1_CCR1/ TIM1_ARR + 1)* 100 = 33.33%

The PWM waveform can be displayed using an oscilloscope.

Note:
No need of RCR update, but we should do it because of the ARR and CCR1 mapping.
Directory contents
  • TIM/DMABurst/stm32f10x_conf.h Library Configuration file
  • TIM/DMABurst/stm32f10x_it.c Interrupt handlers
  • TIM/DMABurst/stm32f10x_it.h Interrupt handlers header file
  • TIM/DMABurst/main.c Main program
  • TIM/DMABurst/system_stm32f10x.c STM32F10x system source file
Hardware and Software environment
  • This example runs on STM32F10x Connectivity line, High-Density, High-Density Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density and Low-Density Value line Devices.
  • This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) evaluation boards and can be easily tailored to any other supported device and development board.
  • STM32100E-EVAL, STM32100B-EVAL, STM3210C-EVAL, STM3210E-EVAL, STM32100E-EVAL and STM3210B-EVAL Set-up
    • Connect the following pins to an oscilloscope to monitor the different waveforms:
      • TIM1 CH1 (PA.08)
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: TIM External Trigger Synchro example

  • STM32F10x Standard Peripheral's Examples

TIM External Trigger Synchro example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    TIM/ExtTrigger_Synchro/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the TIM External Trigger Synchro example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example shows how to synchronize TIM peripherals in cascade mode with an external trigger. In this example three timers are used:

1/TIM1 is configured as Master Timer:

  • Toggle Mode is used
  • The TIM1 Enable event is used as Trigger Output

2/TIM1 is configured as Slave Timer for an external Trigger connected to TIM1 TI2 pin (TIM1 CH2 configured as input pin):

  • The TIM1 TI2FP2 is used as Trigger Input
  • Rising edge is used to start and stop the TIM1: Gated Mode.

3/TIM3 is slave for TIM1 and Master for TIM4,

  • Toggle Mode is used
  • The ITR1(TIM1) is used as input trigger
  • Gated mode is used, so start and stop of slave counter are controlled by the Master trigger output signal(TIM1 enable event).
  • The TIM3 enable event is used as Trigger Output.

4/TIM4 is slave for TIM3,

  • Toggle Mode is used
  • The ITR2(TIM3) is used as input trigger
  • Gated mode is used, so start and stop of slave counter are controlled by the Master trigger output signal(TIM3 enable event).

For Low-density, Medium-density, High-density and Connectivity line devices: The TIMxCLK is fixed to 72 MHZ, the Prescaler is equal to 2 so the TIMx clock counter is equal to 24 MHz. The Three Timers are running at: TIMx frequency = TIMx clock counter/ 2*(TIMx_Period + 1) = 162.1 KHz.

For Low-Density Value line, Medium-Density Value line and High-Density Value line devices: The TIMxCLK is fixed to 24 MHz, the Prescaler is equal to 2 so the TIMx clock counter is equal to 8 MHz. TIMx frequency = TIMx clock counter/ 2*(TIMx_Period + 1) = 54 KHz.

The starts and stops of the TIM1 counters are controlled by the external trigger. The TIM3 starts and stops are controlled by the TIM1, and the TIM4 starts and stops are controlled by the TIM3.

Directory contents
  • TIM/ExtTrigger_Synchro/stm32f10x_conf.h Library Configuration file
  • TIM/ExtTrigger_Synchro/stm32f10x_it.c Interrupt handlers
  • TIM/ExtTrigger_Synchro/stm32f10x_it.h Interrupt handlers header file
  • TIM/ExtTrigger_Synchro/main.c Main program
  • TIM/ExtTrigger_Synchro/system_stm32f10x.c STM32F10x system source file
Hardware and Software environment
  • This example runs on STM32F10x Connectivity line, High-Density, High-Density Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density and Low-Density Value line Devices.
  • This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) evaluation boards and can be easily tailored to any other supported device and development board.
  • STM32100B-EVAL Set-up
    • Connect an external trigger, with a frequency <= xx KHz, to the TIM1 CH2 pin (PA.09). In this example the frequency is equal to x KHz.
  • Connect the following pins to an oscilloscope to monitor the different waveforms:
    • TIM1 CH1 (PA.08)
    • TIM3 CH1 (PA.06)
    • TIM4 CH1 (PB.06)
  • STM3210C-EVAL Set-up
    • Connect an external trigger, with a frequency <= 40KHz, to the TIM1 CH2 pin (PE.11). In this example the frequency is equal to 5 KHz.
  • Connect the following pins to an oscilloscope to monitor the different waveforms:
    • TIM1 CH1 (PE.09)
    • TIM3 CH1 (PC.06)
    • TIM4 CH1 (PB.06)
  • STM3210E-EVAL, STM32100E-EVAL and STM3210B-EVAL Set-up
    • Connect an external trigger, with a frequency <= 40KHz, to the TIM1 CH2 pin (PA.09). In this example the frequency is equal to 5 KHz.
  • Connect the following pins to an oscilloscope to monitor the different waveforms:
    • TIM1 CH1 (PA.08)
    • TIM3 CH1 (PA.06)
    • TIM4 CH1 (PB.06)
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: TIM Input Capture example

  • STM32F10x Standard Peripheral's Examples

TIM Input Capture example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    TIM/InputCapture/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the TIM Input Capture example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example shows how to use the TIM peripheral to measure the frequency of an external signal.

The TIMxCLK frequency is set to SystemCoreClock (Hz), the Prescaler is 0 so the TIM3 counter clock is SystemCoreClock (Hz). SystemCoreClock is set to 72 MHz for Low-density, Medium-density, High-density and Connectivity line devices. For Low-Density Value line and Medium-Density Value line devices, SystemCoreClock is set to 24 MHz.

TIM3 is configured in Input Capture Mode: the external signal is connected to TIM3 Channel2 used as input pin. To measure the frequency we use the TIM3 CC2 interrupt request, so In the TIM3_IRQHandler routine, the frequency of the external signal is computed. The "TIM3Freq" variable contains the external signal frequency: TIM3Freq = TIM3 counter clock / Capture in Hz, where the Capture is the difference between two consecutive TIM3 captures.

For Low-density, Medium-density, High-density and Connectivity line devices, the minimum frequency value to measure is 1100 Hz. For Low-Density Value line, Medium-Density and High-Density Value line devices, the minimum frequency value to measure is 366 Hz.

Directory contents
  • TIM/InputCapture/stm32f10x_conf.h Library Configuration file
  • TIM/InputCapture/stm32f10x_it.c Interrupt handlers
  • TIM/InputCapture/stm32f10x_it.h Interrupt handlers header file
  • TIM/InputCapture/main.c Main program
  • TIM/InputCapture/system_stm32f10x.c STM32F10x system source file
Hardware and Software environment
  • This example runs on STM32F10x Connectivity line, High-Density, High-Density Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density and Low-Density Value line Devices.
  • This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) evaluation boards and can be easily tailored to any other supported device and development board.
  • STM32100E-EVAL, STM32100B-EVAL, STM3210C-EVAL, STM3210E-EVAL and STM3210B-EVAL Set-up
    • Connect the external signal to measure to the TIM3 CH2 pin (PA.07).
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: TIM OC Active example

  • STM32F10x Standard Peripheral's Examples

TIM OC Active example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    TIM/OCActive/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the TIM OC Active example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example shows how to configure the TIM peripheral to generate four different signals with four different delays.

The TIM3CLK frequency is set to SystemCoreClock / 2 (Hz), and the objective is to get TIM3 counter clock at 1 KHz so the Prescaler is computed as following:

  • Prescaler = (TIM3CLK / TIM3 counter clock) - 1 SystemCoreClock is set to 72 MHz for Low-density, Medium-density, High-density and Connectivity line devices and to 24 MHz for Low-Density Value line, Medium-Density Value line and High-Density Value line devices.

The TIM3 CCR1 register value is equal to 1000: TIM3_CH1 delay = CCR1_Val/TIM3 counter clock = 1000 ms so the TIM3 Channel 1 generates a signal with a delay equal to 1000 ms.

The TIM3 CCR2 register value is equal to 500: TIM3_CH2 delay = CCR2_Val/TIM3 counter clock = 500 ms so the TIM3 Channel 2 generates a signal with a delay equal to 500 ms.

The TIM3 CCR3 register value is equal to 250: TIM3_CH3 delay = CCR3_Val/TIM3 counter clock = 250 ms so the TIM3 Channel 3 generates a signal with a delay equal to 250 ms.

The TIM3 CCR4 register value is equal to 125: TIM3_CH4 delay = CCR4_Val/TIM3 counter clock = 125 ms so the TIM3 Channel 4 generates a signal with a delay equal to 125 ms.

The delay correspond to the time difference between PC.06 and TIM3_CHx signal rising edges in case of STM32100E-EVAL, STM32100B-EVAL, STM3210E-EVAL and STM3210B-EVAL

The delay correspond to the time difference between PD.07 and TIM3_CHx signal rising edges in case of STM3210C-EVAL

Directory contents
  • TIM/OCActive/stm32f10x_conf.h Library Configuration file
  • TIM/OCActive/stm32f10x_it.c Interrupt handlers
  • TIM/OCActive/stm32f10x_it.h Interrupt handlers header file
  • TIM/OCActive/main.c Main program
  • TIM/OCActive/system_stm32f10x.c STM32F10x system source file
Hardware and Software environment
  • This example runs on STM32F10x Connectivity line, High-Density, High-Density Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density and Low-Density Value line Devices.
  • This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) evaluation boards and can be easily tailored to any other supported device and development board.
  • STM3210C-EVAL Set-up
    • Connect the TIM3 pins(TIM3 full remapped pins) to an oscilloscope to monitor the different waveforms:
      • PD.07
      • PC.06 (TIM3_CH1)
      • PC.07 (TIM3_CH2)
      • PC.08 (TIM3_CH3)
      • PC.09 (TIM3_CH4)
  • STM32100E-EVAL, STM32100B-EVAL, STM3210E-EVAL and STM3210B-EVAL Set-up
    • Connect the following pins to an oscilloscope to monitor the different waveforms:
      • PC.06
      • PA.06 (TIM3_CH1)
      • PA.07 (TIM3_CH2)
      • PB.00 (TIM3_CH3)
      • PB.01 (TIM3_CH4)
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: TIM OC Inactive example

  • STM32F10x Standard Peripheral's Examples

TIM OC Inactive example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    TIM/OCInactive/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the TIM OC Inactive example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example shows how to configure the TIM peripheral in Output Compare Inactive mode with the corresponding Interrupt requests for each channel.

The TIM2CLK frequency is set to SystemCoreClock / 2 (Hz), and the objective is to get TIM2 counter clock at 1 KHz so the Prescaler is computed as following:

  • Prescaler = (TIM2CLK / TIM2 counter clock) - 1 SystemCoreClock is set to 72 MHz for Low-density, Medium-density, High-density and Connectivity line devices and to 24 MHz for Value line devices.

The TIM2 CCR1 register value is equal to 1000: TIM2_CC1 delay = CCR1_Val/TIM2 counter clock = 1000 ms so the PC.06 is reset after a delay equal to 1000 ms.

The TIM2 CCR2 register value is equal to 500: TIM2_CC2 delay = CCR2_Val/TIM2 counter clock = 500 ms so the PC.07 is reset after a delay equal to 500 ms.

The TIM2 CCR3 register value is equal to 250: TIM2_CC3 delay = CCR3_Val/TIM2 counter clock = 250 ms so the PC.08 is reset after a delay equal to 250 ms.

The TIM2 CCR4 register value is equal to 125: TIM2_CC4 delay = CCR4_Val/TIM2 counter clock = 125 ms so the PC.09 is reset after a delay equal to 125 ms.

While the counter is lower than the Output compare registers values, which determines the Output delay, the PC.06, PC.07, PC.08 and PC.09 pin are turned on.

When the counter value reaches the Output compare registers values, the Output Compare interrupts are generated and, in the handler routine, these pins are turned off.

Directory contents
  • TIM/OCInactive/stm32f10x_conf.h Library Configuration file
  • TIM/OCInactive/stm32f10x_it.c Interrupt handlers
  • TIM/OCInactive/stm32f10x_it.h Interrupt handlers header file
  • TIM/OCInactive/main.c Main program
  • TIM/OCInactive/system_stm32f10x.c STM32F10x system source file
Hardware and Software environment
  • This example runs on STM32F10x Connectivity line, High-Density, High-Density Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density and Low-Density Value line Devices.
  • This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) evaluation boards and can be easily tailored to any other supported device and development board.
  • STM32100B-EVAL, STM3210E-EVAL, STM32100E-EVAL STM3210B-EVAL and STM3210C-EVAL Set-up
    • Connect the following pins to an oscilloscope to monitor the different waveforms:
      • PC.06
      • PC.07
      • PC.08
      • PC.09
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: TIM OC Toggle example

  • STM32F10x Standard Peripheral's Examples

TIM OC Toggle example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    TIM/OCToggle/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the TIM OC Toggle example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example shows how to configure the TIM3 peripheral to generate four different signals with four different frequencies.

The TIM3CLK frequency is set to SystemCoreClock / 2 (Hz), and we want to get TIM3 counter clock at 12 MHz so the Prescaler is computed as following:

  • Prescaler = (TIM3CLK / TIM3 counter clock) - 1 SystemCoreClock is set to 72 MHz for Low-density, Medium-density, High-density and Connectivity line devices and to 24 MHz for Low-Density Value line, Medium-Density Value line and High-Density devices.

The TIM3 CCR1 register value is equal to 32768: CC1 update rate = TIM3 counter clock / CCR1_Val = 366.2 Hz, so the TIM3 Channel 1 generates a periodic signal with a frequency equal to 183.1 Hz.

The TIM3 CCR2 register is equal to 16384: CC2 update rate = TIM3 counter clock / CCR2_Val = 732.4 Hz so the TIM3 channel 2 generates a periodic signal with a frequency equal to 366.3 Hz.

The TIM3 CCR3 register is equal to 8192: CC3 update rate = TIM3 counter clock / CCR3_Val = 1464.8 Hz so the TIM3 channel 3 generates a periodic signal with a frequency equal to 732.4 Hz.

The TIM3 CCR4 register is equal to 4096: CC4 update rate = TIM3 counter clock / CCR4_Val = 2929.6 Hz so the TIM3 channel 4 generates a periodic signal with a frequency equal to 1464.8 Hz.

Directory contents
  • TIM/OCToggle/stm32f10x_conf.h Library Configuration file
  • TIM/OCToggle/stm32f10x_it.c Interrupt handlers
  • TIM/OCToggle/stm32f10x_it.h Interrupt handlers header file
  • TIM/OCToggle/main.c Main program
  • TIM/OCToggle/system_stm32f10x.c STM32F10x system source file
Hardware and Software environment
  • This example runs on STM32F10x Connectivity line, High-Density, High-Density Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density and Low-Density Value line Devices.
  • This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) evaluation boards and can be easily tailored to any other supported device and development board.
  • STM3210C-EVAL Set-up
    • Connect the TIM1 pins(TIM3 full remapped pins) to an oscilloscope to monitor the different waveforms:
      • PC.06 (TIM3_CH1)
      • PC.07 (TIM3_CH2)
      • PC.08 (TIM3_CH3)
      • PC.09 (TIM3_CH4)
  • STM32100B-EVAL, STM3210E-EVAL, STM32100E-EVAL and STM3210B-EVAL Set-up
    • Connect the following pins to an oscilloscope to monitor the different waveforms:
      • PA.06 (TIM3_CH1)
      • PA.07 (TIM3_CH2)
      • PB.00 (TIM3_CH3)
      • PB.01 (TIM3_CH4)
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: TIM One Pulse example

  • STM32F10x Standard Peripheral's Examples

TIM One Pulse example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    TIM/OnePulse/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the TIM One Pulse example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example shows how to use the TIM peripheral to generate a One pulse Mode after a Rising edge of an external signal is received in Timer Input pin.

TIM2CLK = SystemCoreClock, we want to get TIM2 counter clock at 24 MHz:

  • Prescaler = (TIM2CLK / TIM2 counter clock) - 1 SystemCoreClock is set to 72 MHz for Low-density, Medium-density, High-density and Connectivity line devices and to 24 MHz for Low-Density Value line, Medium-Density Value line and High-Density devices.

The Autoreload value is 65535 (TIM4->ARR), so the maximum frequency value to trigger the TIM4 input is 24000000/65535 = 300 Hz.

The TIM4 is configured as follows: The One Pulse mode is used, the external signal is connected to TIM4 CH2 pin (PB.07), the rising edge is used as active edge, the One Pulse signal is output on TIM4_CH1 (PB.06).

The TIM_Pulse defines the delay value, the delay value is fixed to: delay = CCR1/TIM4 counter clock = 16383 / 24000000 = 682.6 us. The (TIM_Period - TIM_Pulse) defines the One Pulse value, the pulse value is fixed to: One Pulse value = (TIM_Period - TIM_Pulse)/TIM4 counter clock = (65535 - 16383) / 24000000 = 2.048 ms.

Directory contents
  • TIM/OnePulse/stm32f10x_conf.h Library Configuration file
  • TIM/OnePulse/stm32f10x_it.c Interrupt handlers
  • TIM/OnePulse/stm32f10x_it.h Interrupt handlers header file
  • TIM/OnePulse/main.c Main program
  • TIM/OnePulse/system_stm32f10x.c STM32F10x system source file
Hardware and Software environment
  • This example runs on STM32F10x Connectivity line, High-Density, High-Density Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density and Low-Density Value line Devices.
  • This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) evaluation boards and can be easily tailored to any other supported device and development board.
  • STM32100B-EVAL, STM3210E-EVAL, STM3210B-EVAL, STM32100E-EVAL and STM3210C-EVAL Set-up
    • Connect the external signal to the TIM4_CH2 pin (PB.07)
    • Connect the TIM4_CH1 (PB.06) pin to an oscilloscope to monitor the waveform.
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: TIM Parallel Synchro example

  • STM32F10x Standard Peripheral's Examples

TIM Parallel Synchro example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    TIM/Parallel_Synchro/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the TIM Parallel Synchro example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example shows how to synchronize TIM peripherals in parallel mode. In this example three timers are used:

Timers synchronisation in parallel mode:

1/TIM2 is configured as Master Timer:

  • PWM Mode is used
  • The TIM2 Update event is used as Trigger Output

2/TIM3 and TIM4 are slaves for TIM2,

  • PWM Mode is used
  • The ITR1(TIM2) is used as input trigger for both slaves
  • Gated mode is used, so starts and stops of slaves counters are controlled by the Master trigger output signal(update event).

o For Low-density, Medium-density, High-density and Connectivity line devices: The TIMxCLK is fixed to 72 MHz, the TIM2 counter clock is 72 MHz. The Master Timer TIM2 is running at TIM2 frequency: TIM2 frequency = TIM2 counter clock/ (TIM2 period + 1) = 281.250 KHz and the duty cycle is equal to TIM2_CCR1/(TIM2_ARR + 1) = 25%.

The TIM3 is running at: (TIM2 frequency)/ (TIM3 period + 1) = 28.1250 KHz and a duty cycle equal to TIM3_CCR1/(TIM3_ARR + 1) = 30%

The TIM4 is running at: (TIM2 frequency)/ (TIM4 period + 1) = 56.250 KHz and a duty cycle equal to TIM4_CCR1/(TIM4_ARR + 1) = 60%

o For Low-Density Value line, Medium-Density Value line and High-Density Value line devices: The TIMxCLK is fixed to 24 MHz, the TIM2 counter clock is 24 MHz. TIM2 frequency = 93.75 KHz TIM3 frequency = 9.375 KHz TIM4 frequency = 18.75 KHz

Directory contents
  • TIM/Parallel_Synchro/stm32f10x_conf.h Library Configuration file
  • TIM/Parallel_Synchro/stm32f10x_it.c Interrupt handlers
  • TIM/Parallel_Synchro/stm32f10x_it.h Interrupt handlers header file
  • TIM/Parallel_Synchro/main.c Main program
  • TIM/Parallel_Synchro/system_stm32f10x.c STM32F10x system source file
Hardware and Software environment
  • This example runs on STM32F10x Connectivity line, High-Density, High-Density Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density and Low-Density Value line Devices.
  • This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) evaluation boards and can be easily tailored to any other supported device and development board.
  • STM3210C-EVAL Set-up
    • Connect the pins to an oscilloscope to monitor the different waveforms:
      • TIM2 CH1 (PA.00)
      • TIM3 CH1 (PC.06) Remapped pin
      • TIM4 CH1 (PB.06)
  • STM32100B-EVAL, STM3210E-EVAL, STM32100E-EVAL and STM3210B-EVAL Set-up
    • Connect the pins to an oscilloscope to monitor the different waveforms:
      • TIM2 CH1 (PA.00)
      • TIM3 CH1 (PA.06)
      • TIM4 CH1 (PB.06)
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: TIM PWM Input example

  • STM32F10x Standard Peripheral's Examples

TIM PWM Input example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    TIM/PWM_Input/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the TIM PWM Input example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example shows how to use the TIM peripheral to measure the frequency and duty cycle of an external signal.

The TIMxCLK frequency is set to SystemCoreClock (Hz), the Prescaler is 0 so the TIM3 counter clock is SystemCoreClock (Hz). SystemCoreClock is set to 72 MHz for Low-density, Medium-density, High-density and Connectivity line devices. For Low-Density Value line, Medium-Density Value line and High-Density devices, SystemCoreClock is set to 24 MHz.

TIM3 is configured in PWM Input Mode: the external signal is connected to TIM3 Channel2 used as input pin. To measure the frequency and the duty cycle we use the TIM3 CC2 interrupt request, so In the TIM3_IRQHandler routine, the frequency and the duty cycle of the external signal are computed. The "Frequency" variable contains the external signal frequency: Frequency = TIM3 counter clock / TIM3_CCR2 in Hz, The "DutyCycle" variable contains the external signal duty cycle: DutyCycle = (TIM3_CCR1*100)/(TIM3_CCR2) in %.

For Low-density, Medium-density, High-density and Connectivity line devices, the minimum frequency value to measure is 1100 Hz. For Low-Density Value line and Medium-Density Value line devices, the minimum frequency value to measure is 366 Hz.

Directory contents
  • TIM/PWM_Input/stm32f10x_conf.h Library Configuration file
  • TIM/PWM_Input/stm32f10x_it.c Interrupt handlers
  • TIM/PWM_Input/stm32f10x_it.h Interrupt handlers header file
  • TIM/PWM_Input/main.c Main program
  • TIM/PWM_Input/system_stm32f10x.c STM32F10x system source file
Hardware and Software environment
  • This example runs on STM32F10x Connectivity line, High-Density, High-Density Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density and Low-Density Value line Devices.
  • This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) evaluation boards and can be easily tailored to any other supported device and development board.
  • STM32100B-EVAL, STM3210E-EVAL, STM32100E-EVAL, STM3210B-EVAL and STM3210C-EVAL Set-up
    • Connect the external signal to measure to the TIM3 CH2 pin (PA.07).
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: TIM PWM Output example

  • STM32F10x Standard Peripheral's Examples

TIM PWM Output example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    TIM/PWM_Output/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the TIM PWM Output example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example shows how to configure the TIM peripheral in PWM (Pulse Width Modulation) mode.

The TIM3CLK frequency is set to SystemCoreClock / 2 (Hz), to get TIM3 counter clock at 24 MHz the Prescaler is computed as following:

  • Prescaler = (TIM3CLK / TIM3 counter clock) - 1 SystemCoreClock is set to 72 MHz for Low-density, Medium-density, High-density and Connectivity line devices and to 24 MHz for Value line devices.

The TIM3 is running at 36 KHz: TIM3 Frequency = TIM3 counter clock/(ARR + 1) = 24 MHz / 666 = 36 KHz The TIM3 CCR1 register value is equal to 500, so the TIM3 Channel 1 generates a PWM signal with a frequency equal to 36 KHz and a duty cycle equal to 50%: TIM3 Channel1 duty cycle = (TIM3_CCR1/ TIM3_ARR + 1)* 100 = 50%

The TIM3 CCR2 register value is equal to 375, so the TIM3 Channel 2 generates a PWM signal with a frequency equal to 36 KHz and a duty cycle equal to 37.5%: TIM3 Channel2 duty cycle = (TIM3_CCR2/ TIM3_ARR + 1)* 100 = 37.5%

The TIM3 CCR3 register value is equal to 250, so the TIM3 Channel 3 generates a PWM signal with a frequency equal to 36 KHz and a duty cycle equal to 25%: TIM3 Channel3 duty cycle = (TIM3_CCR3/ TIM3_ARR + 1)* 100 = 25%

The TIM3 CCR4 register value is equal to 125, so the TIM3 Channel 4 generates a PWM signal with a frequency equal to 36 KHz and a duty cycle equal to 12.5%: TIM3 Channel4 duty cycle = (TIM3_CCR4/ TIM3_ARR + 1)* 100 = 12.5%

The PWM waveform can be displayed using an oscilloscope.

Directory contents
  • TIM/PWM_Output/stm32f10x_conf.h Library Configuration file
  • TIM/PWM_Output/stm32f10x_it.c Interrupt handlers
  • TIM/PWM_Output/stm32f10x_it.h Interrupt handlers header file
  • TIM/PWM_Output/main.c Main program
  • TIM/PWM_Output/system_stm32f10x.c STM32F10x system source file
Hardware and Software environment
  • This example runs on STM32F10x Connectivity line, High-Density, High-Density Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density and Low-Density Value line Devices.
  • This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) evaluation boards and can be easily tailored to any other supported device and development board.
  • STM3210C-EVAL Set-up
    • Connect the following pins(TIM3 full remapping pins) to an oscilloscope to monitor the different waveforms:
      • PC.06: (TIM3_CH1)
      • PC.07: (TIM3_CH2)
      • PC.08: (TIM3_CH3)
      • PC.09: (TIM3_CH4)
  • STM32100B-EVAL, STM3210E-EVAL, STM32100E-EVAL and STM3210B-EVAL Set-up
    • Connect the following pins to an oscilloscope to monitor the different waveforms:
      • PA.06: (TIM3_CH1)
      • PA.07: (TIM3_CH2)
      • PB.00: (TIM3_CH3)
      • PB.01: (TIM3_CH4)
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: TIM1 Synchro example

  • STM32F10x Standard Peripheral's Examples

TIM1 Synchro example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    TIM/TIM1_Synchro/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the TIM TIM1 Synchro example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example shows how to synchronize TIM1 and Timers (TIM3 and TIM4) in parallel mode.

Timers synchronisation in parallel mode:

1/ TIM1 is configured as Master Timer:

  • PWM Mode is used
  • The TIM1 Update event is used as Trigger Output

2/ TIM3 and TIM4 are slaves for TIM1,

  • PWM Mode is used
  • The ITR0(TIM1) is used as input trigger for both slaves
  • Gated mode is used, so starts and stops of slaves counters are controlled by the Master trigger output signal(update event).

o For Low-density, Medium-density, High-density and Connectivity line devices: The TIMxCLK is fixed to 72 MHz, Prescaler = 0 so the TIM1 counter clock is 72 MHz.

The Master Timer TIM1 is running at: TIM1 frequency = TIM1 counter clock / (TIM1_Period + 1) = 281.250 KHz and the duty cycle is equal to: TIM1_CCR1/(TIM1_ARR + 1) = 50%

The TIM3 is running at: (TIM1 frequency)/ ((TIM3 period +1)* (Repetition_Counter+1)) = 18.750 KHz and a duty cycle equal to TIM3_CCR1/(TIM3_ARR + 1) = 33.3%

The TIM4 is running at: (TIM1 frequency)/ ((TIM4 period +1)* (Repetition_Counter+1)) = 28.125 KHz and a duty cycle equal to TIM4_CCR1/(TIM4_ARR + 1) = 50%

o For Value line devices: The TIMxCLK is fixed to 24 MHz, Prescaler = 0 so the TIM1 counter clock is 24 MHz. TIM1 frequency = 93.75 KHz TIM3 frequency = 6.25 KHz TIM4 frequency = 9.375 KHz

Directory contents
  • TIM/TIM1_Synchro/stm32f10x_conf.h Library Configuration file
  • TIM/TIM1_Synchro/stm32f10x_it.c Interrupt handlers
  • TIM/TIM1_Synchro/stm32f10x_it.h Interrupt handlers header file
  • TIM/TIM1_Synchro/main.c Main program
  • TIM/TIM1_Synchro/system_stm32f10x.c STM32F10x system source file
Hardware and Software environment
  • This example runs on STM32F10x Connectivity line, High-Density, High-Density Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density and Low-Density Value line Devices.
  • This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) evaluation boards and can be easily tailored to any other supported device and development board.
  • STM3210C-EVAL Set-up
    • Connect the following pins to an oscilloscope to monitor the different waveforms:
      • TIM1 CH1 (PE.08) Remapped pin
      • TIM3 CH1 (PC.06) Remapped pin
      • TIM4 CH1 (PB.06)
  • STM32100B-EVAL, STM3210E-EVAL, STM32100E-EVAL and STM3210B-EVAL Set-up
    • Connect the following pins to an oscilloscope to monitor the different waveforms:
      • TIM1 CH1 (PA.08)
      • TIM3 CH1 (PA.06)
      • TIM4 CH1 (PB.06)
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: TIM15 Complementary Signals example

  • STM32F10x Standard Peripheral's Examples

TIM15 Complementary Signals example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    TIM/TIM15_ComplementarySignals/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the TIM15 Complementary Signals example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example shows how to configure the TIM15 peripheral to generate one complementary TIM15 signal, to insert a defined dead time value, to use the break feature and to lock the desired parameters.

TIM15CLK is fixed to 24 MHz, the TIM15 Prescaler is equal to 0 so the TIM15 counter clock used is 24 MHz.

TIM15 frequency is defined as follow: TIM15 frequency = TIM15 counter clock / (TIM15_Period + 1) = 366 Hz.

The Duty cycles is computed as the following description:

  • TIM15 Channel1 duty cycle = TIM15_CCR1 / (TIM15_Period + 1) = 50%
  • TIM15 Channel1N duty cycle = (TIM15_Period - TIM15_CCR1) / (TIM15_Period + 1) = 50%

A dead time of 1.62 us is inserted between the different complementary signals, and the Lock level 1 is selected. The break Polarity is used at High level.

The TIM15 waveform can be displayed using an oscilloscope.

Directory contents
  • TIM/TIM15_ComplementarySignals/stm32f10x_conf.h Library Configuration file
  • TIM/TIM15_ComplementarySignals/stm32f10x_it.c Interrupt handlers
  • TIM/TIM15_ComplementarySignals/stm32f10x_it.h Interrupt handlers header file
  • TIM/TIM15_ComplementarySignals/main.c Main program
  • TIM/TIM15_ComplementarySignals/system_stm32f10x.c STM32F10x system source file
Hardware and Software environment
  • This example runs on High-Density Value line, STM32F10x Medium-Density Value line and Low-Density Value line Devices.
  • This example has been tested with STMicroelectronics STM32100E-EVAL (STM32F10x High-Density Value line) and STM32100B-EVAL (Medium-Density Value line) evaluation boards and can be easily tailored to any other supported device and development board.
  • STM32100E-EVAL and STM32100B-EVAL Set-up
    • Connect the TIM15 pins to an oscilloscope to monitor the different waveforms:
      • TIM15_CH1 pin (PA.02)
      • TIM15_CH1N pin (PB.15)
  • Connect the TIM15 break pin TIM15_BKIN pin (PA.09) to the GND. To generate a break event, switch this pin level from 0V to 3.3V.
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: TIM9 OC Toggle example

  • STM32F10x Standard Peripheral's Examples

TIM9 OC Toggle example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    TIM/TIM9_OCToggle/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the TIM9 OC Toggle example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example shows how to configure the TIM9 peripheral to generate two different signals with two different frequencies.

The TIM9CLK frequency is set to SystemCoreClock (72 MHz), and we want to get TIM9 counter clock at 24 MHz so the Prescaler is computed as following:

  • Prescaler = (TIM9CLK / TIM9 counter clock) - 1

The TIM9 CCR1 register value is equal to 32768: CC1 update rate = TIM9 counter clock / CCR1Val = 732.4 Hz, so the TIM9 Channel 1 generates a periodic signal with a frequency equal to 366.2 Hz.

The TIM9 CCR2 register is equal to 16384: CC2 update rate = TIM9 counter clock / CCR2Val = 1464.8 so the TIM9 channel 2 generates a periodic signal with a frequency equal to 732.4 Hz.

Directory contents
  • TIM/TIM9_OCToggle/stm32f10x_conf.h Library Configuration file
  • TIM/TIM9_OCToggle/stm32f10x_it.c Interrupt handlers
  • TIM/TIM9_OCToggle/stm32f10x_it.h Interrupt handlers header file
  • TIM/TIM9_OCToggle/main.c Main program
  • TIM/TIM9_OCToggle/system_stm32f10x.c STM32F10x system source file
Hardware and Software environment
  • This example runs only on STM32F10x XL-Density Devices.
  • This example has been tested with STMicroelectronics STM3210E-EVAL (XL-Density) evaluation board and can be easily tailored to any development board.
  • STM3210E-EVAL Set-up
    • Connect the TIM9 pins to an oscilloscope to monitor the different waveforms:
      • PA.02 (TIM9_CH1)
      • PA.03 (TIM9_CH2)
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: TIM10 PWM Output example

  • STM32F10x Standard Peripheral's Examples

TIM10 PWM Output example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    TIM/TIM10_PWMOutput/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the  TIM10 PWM Output example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example shows how to configure the TIM10 peripheral in PWM (Pulse Width Modulation) mode.

The TIM10CLK frequency is set to SystemCoreClock (72 MHz), to get TIM10 counter clock at 24 MHz the Prescaler is computed as following:

  • Prescaler = (TIM10CLK / TIM10 counter clock) - 1

The TIM10 is running at 36 KHz: TIM10 Frequency = TIM10 counter clock/(ARR + 1) = 24 MHz / 666 = 36 KHz The TIM10 CCR1 register value is equal to 500, so the TIM10 Channel 1 generates a PWM signal with a frequency equal to 36 KHz and a duty cycle equal to 37.5%: TIM10 Channel1 duty cycle = (TIM10_CCR1/ TIM10_ARR + 1)* 100 = 37.5%

The PWM waveform can be displayed using an oscilloscope.

Directory contents
  • TIM/TIM10_PWMOutput/stm32f10x_conf.h Library Configuration file
  • TIM/TIM10_PWMOutput/stm32f10x_it.c Interrupt handlers
  • TIM/TIM10_PWMOutput/stm32f10x_it.h Interrupt handlers header file
  • TIM/TIM10_PWMOutput/main.c Main program
  • TIM/TIM10_PWMOutput/system_stm32f10x.c STM32F10x system source file
Hardware and Software environment
  • This example runs only on STM32F10x XL-Density Devices.
  • This example has been tested with STMicroelectronics STM3210E-EVAL (XL-Density) evaluation board and can be easily tailored to any development board.
  • STM3210E-EVAL Set-up
    • Connect PF.06 (TIM10_CH1 remapped pin) to an oscilloscope to monitor the PWM waveform
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: TIM Time Base example

  • STM32F10x Standard Peripheral's Examples

TIM Time Base example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    TIM/TimeBase/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the TIM Time Base example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example shows how to configure the TIM peripheral in Output Compare Timing mode with the corresponding Interrupt requests for each channel in order to generate 4 different time bases.

The TIM2CLK frequency is set to SystemCoreClock / 2 (Hz), to get TIM2 counter clock at 6 MHz so the Prescaler is computed as following:

  • Prescaler = (TIM2CLK / TIM2 counter clock) - 1 SystemCoreClock is set to 72 MHz for Low-density, Medium-density, High-density and Connectivity line devices and to 24 MHz for Low-Density Value line, Medium-Density Value line and High-Density devices.

The TIM2 CC1 register value is equal to 40961, CC1 update rate = TIM2 counter clock / CCR1_Val = 146.48 Hz, so the TIM2 Channel 1 generates an interrupt each 6.8ms

The TIM2 CC2 register is equal to 27309, CC2 update rate = TIM2 counter clock / CCR2_Val = 219.7 Hz so the TIM2 Channel 2 generates an interrupt each 4.55ms

The TIM2 CC3 register is equal to 13654, CC3 update rate = TIM2 counter clock / CCR3_Val = 439.4Hz so the TIM2 Channel 3 generates an interrupt each 2.27ms

The TIM2 CC4 register is equal to 6826, CC4 update rate = TIM2 counter clock / CCR4_Val = 878.9 Hz so the TIM2 Channel 4 generates an interrupt each 1.13ms.

When the counter value reaches the Output compare registers values, the Output Compare interrupts are generated and, in the handler routine, 4 pins(PC.06, PC.07, PC.08 and PC.09) are toggled with the following frequencies:

  • PC.06: 73.24Hz (CC1)
  • PC.07: 109.8Hz (CC2)
  • PC.08: 219.7Hz (CC3)
  • PC.09: 439.4Hz (CC4)
Directory contents
  • TIM/TimeBase/stm32f10x_conf.h Library Configuration file
  • TIM/TimeBase/stm32f10x_it.c Interrupt handlers
  • TIM/TimeBase/stm32f10x_it.h Interrupt handlers header file
  • TIM/TimeBase/main.c Main program
  • TIM/TimeBase/system_stm32f10x.c STM32F10x system source file
Hardware and Software environment
  • This example runs on STM32F10x Connectivity line, High-Density, High-Density Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density and Low-Density Value line Devices.
  • This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) evaluation boards and can be easily tailored to any other supported device and development board.
  • STM32100E-EVAL, STM3210E-EVAL, STM32100E-EVAL, STM3210B-EVAL and STM3210C-EVAL Set-up
    • Connect an oscilloscope on PC.06, PC.07, PC.08 and PC.09 to show the different Time Base signals.
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: USART Half Duplex example

  • STM32F10x Standard Peripheral's Examples

USART Half Duplex example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    USART/HalfDuplex/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the USART Half Duplex example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example provides a basic communication between USARTy and USARTz in Half-Duplex mode using flags. USARTy and USARTz can be USART1 and USART2 or USART2 and USART3, depending on the STMicroelectronics EVAL board you are using.

First, the USARTy sends data from TxBuffer1 buffer to USARTz using TXE flag. Data received using RXNE flag by USARTz is stored in RxBuffer2 then compared with the sent ones and the result of this comparison is stored in the "TransferStatus1" variable.

Then, the USARTz sends data from TxBuffer2 buffer to USARTy using TXE flag. Data received using RXNE flag by USARTy is stored in RxBuffer1 then compared with the sent ones and the result of this comparison is stored in the "TransferStatus2" variable.

USARTy and USARTz configured as follow:

  • BaudRate = 230400 baud
  • Word Length = 8 Bits
  • One Stop Bit
  • Even parity
  • Hardware flow control disabled (RTS and CTS signals)
  • Receive and transmit enabled
Directory contents
  • USART/HalfDuplex/platform_config.h Evaluation board specific configuration file
  • USART/HalfDuplex/stm32f10x_conf.h Library Configuration file
  • USART/HalfDuplex/stm32f10x_it.h Interrupt handlers header file
  • USART/HalfDuplex/stm32f10x_it.c Interrupt handlers
  • USART/HalfDuplex/main.c Main program
  • USART/HalfDuplex/system_stm32f10x.c STM32F10x system source file
Hardware and Software environment
  • This example runs on STM32F10x Connectivity line, High-Density, High-Density Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density and Low-Density Value line Devices.
  • This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) evaluation boards and can be easily tailored to any other supported device and development board. To select the STMicroelectronics evaluation board used to run the example, uncomment the corresponding line in USART/HalfDuplex/platform_config.h file
  • STM32100E-EVAL Set-up
    • Connect USART1_Tx(PA.09) to USART2_Tx(PA.02).
  • STM32100B-EVAL Set-up
    • Connect USART1_Tx(PA.09) to USART2_Tx(PD.05).
  • STM3210C-EVAL Set-up
    • Connect USART2 Tx pin (PD.05) to USART3 Tx pin (PC.10) and connect a pull-up resistor to this line (10K).
      Note:
      In this case USART3 Tx pin is remapped by software. Make sure that jumpers JP19 and JP18 are open.
  • STM3210E-EVAL Set-up
    • Connect USART1_Tx(PA.09) to USART2_Tx(PA.02) and connect a pull-up resistor to this line (10K).
  • STM3210B-EVAL Set-up
    • Connect USART1_Tx(PA.09) to USART2_Tx(PD.05) and connect a pull-up resistor to this line (10K).
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: USART Hyperterminal Hardware Flow Control example

  • STM32F10x Standard Peripheral's Examples

USART Hyperterminal Hardware Flow Control example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    USART/HyperTerminal_HwFlowControl/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the USART Hyperterminal Hardware Flow Control
  *          example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example provides a description of how to use the USART with hardware flow control and communicate with the Hyperterminal. First, the USART2 sends the TxBuffer to the hyperterminal and still waiting for a string from the hyperterminal that you must enter which must end by '' character (keypad ENTER button). The communication will end if received data exceed 255 without sending the '' character. Each byte received is retransmitted to the Hyperterminal. The string that you have entered is stored in the RxBuffer array. The receive buffer have a RxBufferSize bytes as maximum.

The USART2 is configured as follow:

  • BaudRate = 115200 baud
  • Word Length = 8 Bits
  • One Stop Bit
  • No parity
  • Hardware flow control enabled (RTS and CTS signals)
  • Receive and transmit enabled
Directory contents
  • USART/HyperTerminal_HwFlowControl/platform_config.h Evaluation board specific configuration file
  • USART/HyperTerminal_HwFlowControl/stm32f10x_conf.h Library Configuration file
  • USART/HyperTerminal_HwFlowControl/stm32f10x_it.h Interrupt handlers header file
  • USART/HyperTerminal_HwFlowControl/stm32f10x_it.c Interrupt handlers
  • USART/HyperTerminal_HwFlowControl/main.c Main program
  • USART/HyperTerminal_HwFlowControl/system_stm32f10x.c STM32F10x system source file
Hardware and Software environment
  • This example runs on STM32F10x Connectivity line, High-Density, High-Density Value line,Medium-Density, XL-Density, Medium-Density Value line, Low-Density and Low-Density Value line Devices.
  • This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density Value line), STM32100B-EVAL (Medium-Density Value line), STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) evaluation boards and can be easily tailored to any other supported device and development board. This example can't be tested with STM3210C-EVAL (Connectivity Line) evaluation board. To select the STMicroelectronics evaluation board used to run the example, uncomment the corresponding line in USART/HyperTerminal_HwFlowControl/platform_config.h file
  • STM32100E-EVAL Set-up
    • Connect a null-modem female/female RS232 cable between CN10 and PC serial port.
      Note:
      Make sure the Jumper 5 (JP5) is not open.
  • STM32100B-EVAL Set-up
    • Connect a null-modem female/female RS232 cable between CN9 and PC serial port.
      Note:
      In this case USART2 Tx, Rx, RTS and CTS pins are remapped by software on PD.05, PD.06, PD.04 and PD.03 respectively.
  • STM3210E-EVAL Set-up
    • Connect a null-modem female/female RS232 cable between CN8 and PC serial port.
      Note:
      Make sure the Jumper 4 (JP4) is in position 2<-->3.
  • STM3210B-EVAL Set-up
    • Connect a null-modem female/female RS232 cable between CN5 and PC serial port.
      Note:
      In this case USART2 Tx, Rx, RTS and CTS pins are remapped by software on PD.05, PD.06, PD.04 and PD.03 respectively.
  • Hyperterminal configuration:
    • Word Length = 8 Bits
    • One Stop Bit
    • No parity
    • BaudRate = 115200 baud
    • flow control: Hardware
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: USART Hyperterminal interrupt example

  • STM32F10x Standard Peripheral's Examples

USART Hyperterminal interrupt example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    USART/HyperTerminal_Interrupt/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the USART Hyperterminal interrupt example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example provides a description of how to use the EVAL_COM1 Transmit and Receive interrupts to communicate with the hyperterminal. EVAL_COM1 can be USART1 or USART2 depending on the STMicroelectronics EVAL board you are using.

First, the EVAL_COM1 sends the TxBuffer to the hyperterminal and still waiting for a string from the hyperterminal that you must enter. The string that you have entered is stored in the RxBuffer array. The receive buffer have a RxBufferSize bytes as maximum (the reception is stopped when this maximum receive value is reached).

The EVAL_COM1 is configured as follow:

  • BaudRate = 9600 baud
  • Word Length = 8 Bits (7 data bit + 1 parity bit)
  • Two Stop Bit
  • Odd parity
  • Hardware flow control disabled (RTS and CTS signals)
  • Receive and transmit enabled
Note:
When the parity is enabled, the computed parity is inserted at the MSB position of the transmitted data.
Directory contents
  • USART/HyperTerminal_Interrupt/stm32f10x_conf.h Library Configuration file
  • USART/HyperTerminal_Interrupt/stm32f10x_it.h Interrupt handlers header file
  • USART/HyperTerminal_Interrupt/stm32f10x_it.c Interrupt handlers source file
  • USART/HyperTerminal_Interrupt/main.c Main program
  • USART/HyperTerminal_Interrupt/system_stm32f10x.c STM32F10x system source file
Hardware and Software environment
  • This example runs on STM32F10x Connectivity line, High-Density, High-Density Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density and Low-Density Value line Devices.
  • This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) evaluation boards and can be easily tailored to any other supported device and development board. To select the STMicroelectronics evaluation board used to run the example, uncomment the corresponding line in stm32_eval.h file
  • STM32100B-EVAL Set-up
    • Connect a null-modem female/female RS232 cable between the DB9 connector CN10 and PC serial port.
  • STM3210C-EVAL Set-up
    • Connect a null-modem female/female RS232 cable between the DB9 connector CN6 and PC serial port.
      Note:
      Make sure that jumpers JP19 and JP18 are open.
  • STM3210E-EVAL Set-up
    • Connect a null-modem female/female RS232 cable between the DB9 connector CN12 and PC serial port.
  • STM3210B-EVAL Set-up
    • Connect a null-modem female/female RS232 cable between the DB9 connector CN6 and PC serial port.
  • STM32100E-EVAL Set-up
    • Connect a null-modem female/female RS232 cable between the DB9 connector CN10 and PC serial port.
  • Hyperterminal configuration:
    • Word Length = 7 Bits
    • Two Stop Bit
    • Odd parity
    • BaudRate = 9600 baud
    • flow control: None
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: USART Interrupts example

  • STM32F10x Standard Peripheral's Examples

USART Interrupts example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    USART/Interrupt/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the USART Interrupts example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example provides a basic communication between USARTy and USARTz using interrupts. USARTy and USARTz can be USART1 and USART2 or USART2 and USART3, depending on the STMicroelectronics EVAL board you are using.

USARTz sends TxBuffer2 to USARTy which sends TxBuffer1 to USARTz. The data received by USARTy and USARTz are stored respectively in RxBuffer1 and RxBuffer2. The data transfer is managed in USARTy_IRQHandler and USARTz_IRQHandler in stm32f10x_it.c file.

USARTy and USARTz configured as follow:

  • BaudRate = 9600 baud
  • Word Length = 8 Bits
  • One Stop Bit
  • No parity
  • Hardware flow control disabled (RTS and CTS signals)
  • Receive and transmit enabled
Directory contents
  • USART/Interrupt/platform_config.h Evaluation board specific configuration file
  • USART/Interrupt/stm32f10x_conf.h Library Configuration file
  • USART/Interrupt/stm32f10x_it.h Interrupt handlers header file
  • USART/Interrupt/stm32f10x_it.c Interrupt handlers
  • USART/Interrupt/main.c Main program
  • USART/Interrupt/system_stm32f10x.c STM32F10x system source file
Hardware and Software environment
  • This example runs on STM32F10x Connectivity line, High-Density, High-Density Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density and Low-Density Value line Devices.
  • This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) evaluation boards and can be easily tailored to any other supported device and development board. To select the STMicroelectronics evaluation board used to run the example, uncomment the corresponding line in USART/Interrupt/platform_config.h file
  • STM32100E-EVAL Set-up
    • Connect a null-modem female/female RS232 cable between CN10 (USART1) and CN5 (USART2).
      Note:
      Make sure that jumper JP5 is not open.
  • STM32100B-EVAL Set-up
    • Connect a null-modem female/female RS232 cable between CN10 (USART1) and CN9 (USART2).
      Note:
      In this case USART2 Tx and Rx pins are remapped by software on PD.05 and PD.06 respectively.
  • STM3210C-EVAL Set-up
    • Connect USART2 Tx pin (PD.05) to USART3 Rx pin (PC.11)
    • Connect USART2 Rx pin (PD.06) to USART3 Tx pin (PC.10)
      Note:
      In this case USART3 Tx and Rx pins are remapped by software. Make sure that jumpers JP19 and JP18 are open.
  • STM3210E-EVAL Set-up
    • Connect a null-modem female/female RS232 cable between CN12 (USART1) and CN8 (USART2).
  • STM3210B-EVAL Set-up
    • Connect a null-modem female/female RS232 cable between CN6 (USART1) and CN5 (USART2).
      • In this case USART2 Tx and Rx pins are remapped by software on PD.05 and PD.06 respectively.
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: USART IrDA Receive example

  • STM32F10x Standard Peripheral's Examples

USART IrDA Receive example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    USART/IrDA/Receive/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the USART IrDA Receive example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example provides a basic communication USARTy IrDA receive mode. Four leds are used to show which byte is received. USARTy can be USART3 or USART2 depending on the STMicroelectronics EVAL board you are using.

  • LED1 toggles when 0x05 is received
  • LED2 toggles when 0x02 is received
  • LED3 toggles when 0x03 is received
  • LED4 toggles when 0x04 is received
  • LED1, LED2, LED3 and LED4 toggle when 0x01 is received

USARTy configured as follow:

  • BaudRate = 115200 baud
  • Word Length = 8 Bits
  • One Stop Bit
  • No parity
  • Hardware flow control disabled (RTS and CTS signals)
  • Receive and transmit enabled

The USART IrDA example provides two IrDA program: transmitter&receiver and requires two boards to be able to run the full demonstration:

  • one board will act as IrDA transmitter
  • one board will act as IrDA receiver
Directory contents
  • USART/IrDA/Receive/platform_config.h Evaluation board specific configuration file
  • USART/IrDA/Receive/stm32f10x_conf.h Library Configuration file
  • USART/IrDA/Receive/stm32f10x_it.h Interrupt handlers header file
  • USART/IrDA/Receive/stm32f10x_it.c Interrupt handlers
  • USART/IrDA/Receive/main.c Main program
  • USART/IrDA/Receive/system_stm32f10x.c STM32F10x system source file
Hardware and Software environment
  • This example runs on STM32F10x Connectivity line, High-Density, High-Density Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density and Low-Density Value line Devices.
  • This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) evaluation boards and can be easily tailored to any other supported device and development board. To select the STMicroelectronics evaluation board used to run the example, uncomment the corresponding line in USART/IrDA/Receive/platform_config.h or stm32_eval.h file
  • STM32100E-EVAL Set-up
    • Use an IrDA transceiver connected to the USART3 Tx pin (U16 connector, JP15 jumper must be fitted).
    • Use LED1, LED2, LED3 and LED4 leds connected respectively to PC.06, PC.07, PC.08 and PC.09 pins
      Note:
      In this case USART3 Tx and Rx pins are remapped by software on PC.10 and PC.11 respectively.
  • STM32100B-EVAL Set-up
    • Use an IrDA transceiver connected to the USART3 Tx pin (U14 connector, JP11 jumper must be fitted).
    • Use LED1, LED2, LED3 and LED4 leds connected respectively to PC.06, PC.07, PC.08 and PC.09 pins
      Note:
      In this case USART3 Tx and Rx pins are remapped by software on PC.10 and PC.11 respectively.
  • STM3210C-EVAL Set-up
    • Use an IrDA transceiver connected to the USART2 Tx and Rx pins (U12 connector, JP16 should be in position 1<-->2).
    • Use LED1, LED2, LED3 and LED4 connected respectively to PD.07, PD.13, PF.03 and PD.04 pins
  • STM3210E-EVAL Set-up
    • Use an IrDA transceiver connected to the USART3 Tx pin (U13 connector, JP21 and JP22 jumper must be fitted).
    • Use LED1, LED2, LED3 and LED4 leds connected respectively to PF.06, PF0.7, PF.08 and PF.09 pins
  • STM3210B-EVAL Set-up
    • Use an IrDA transceiver connected to the USART3 Tx pin (U11 connector, JP5 jumper must be fitted).
    • Use LED1, LED2, LED3 and LED4 leds connected respectively to PC.06, PC.07, PC.08 and PC.09 pins
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: USART IrDA Transmit example

  • STM32F10x Standard Peripheral's Examples

USART IrDA Transmit example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    USART/IrDA/Transmit/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the USART IrDA Transmit example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example provides a basic communication USARTy IrDA transmit mode. Five pins, configured in input floating mode, are used to select the byte to be send at each pin state change. USARTy can be USART3 or USART2 depending on the STMicroelectronics EVAL board you are using.

These bytes are:

  • 0x00 if no key (JOY_NONE) pressed
  • 0x01 if JOY_SEL pin state change
  • 0x02 if JOY_DOWN pin state change
  • 0x03 if JOY_LEFT pin state change
  • 0x04 if JOY_RIGHT pin state change
  • 0x05 if JOY_UP pin state change

USARTy configured as follow:

  • BaudRate = 115200 baud
  • Word Length = 8 Bits
  • One Stop Bit
  • No parity
  • Hardware flow control disabled (RTS and CTS signals)
  • Receive and transmit enabled

The USART IrDA example provides two IrDA program: transmitter&receiver and requires two boards to be able to run the full demonstration:

  • one board will act as IrDA transmitter
  • one board will act as IrDA receiver
Directory contents
  • USART/IrDA/Transmit/platform_config.h Evaluation board specific configuration file
  • USART/IrDA/Transmit/stm32f10x_conf.h Library Configuration file
  • USART/IrDA/Transmit/stm32f10x_it.h Interrupt handlers header file
  • USART/IrDA/Transmit/stm32f10x_it.c Interrupt handlers
  • USART/IrDA/Transmit/main.c Main program
  • USART/IrDA/Transmit/system_stm32f10x.c STM32F10x system source file
Hardware and Software environment
  • This example runs on STM32F10x Connectivity line, High-Density, High-Density Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density and Low-Density Value line Devices.
  • This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) evaluation boards and can be easily tailored to any other supported device and development board. To select the STMicroelectronics evaluation board used to run the example, uncomment the corresponding line in USART/IrDA/Transmit/platform_config.h or the stm32_eval.h file
  • STM32100E-EVAL Set-up
    • Use DOWN push-button connected to pin PD.03
    • Use UP push-button connected to pin PG.15
    • Use SEL push-button connected to pin PG.07
    • Use RIGHT push-button connected to pin PG.13
    • Use RIGHT push-button connected to pin PG.14
    • Use an IrDA transceiver connected to the USART3 Tx and Rx pins (U16 connector, JP15 jumper must be fitted).
  • STM32100B-EVAL Set-up
    • Use DOWN push-button connected to pin PD.14
    • Use UP push-button connected to pin PD.08
    • Use SEL push-button connected to pin PD.12
    • Use RIGHT push-button connected to pin PE.01
    • Use RIGHT push-button connected to pin PE.00
    • Use an IrDA transceiver connected to the USART3 Tx and Rx pins (U14 connector, JP11 jumper must be fitted).
  • STM3210C-EVAL Set-up
    • The JoyStick push buttons are connected to the IO Expander on I2C.
    • Use an IrDA transceiver connected to the USART2 Tx and Rx pins (U12 connector, JP16 should be in position 1<-->2).
  • STM3210E-EVAL Set-up
    • Use DOWN push-button connected to pin PD.03
    • Use UP push-button connected to pin PG.15
    • Use SEL push-button connected to pin PG.07
    • Use RIGHT push-button connected to pin PG.13
    • Use RIGHT push-button connected to pin PG.14
    • Use an IrDA transceiver connected to the USART3 Tx and Rx pins (U13 connector, JP21 and JP22 jumper must be fitted).
  • STM3210B-EVAL Set-up
    • Use DOWN push-button connected to pin PD.14
    • Use UP push-button connected to pin PD.08
    • Use SEL push-button connected to pin PD.12
    • Use RIGHT push-button connected to pin PE.00
    • Use RIGHT push-button connected to pin PE.01
    • Use an IrDA transceiver connected to the USART3 Tx and Rx pins (U11 connector, JP5 jumper must be fitted).
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: USART Multi Processor example

  • STM32F10x Standard Peripheral's Examples

USART Multi Processor example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    USART/MultiProcessor/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the USART Multi Processor example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example provides a description of how to use the USART in multi-processor mode. USARTy and USARTz can be USART1 and USART2 or USART2 and USART3 respectively, depending on the STMicroelectronics EVAL board you are using.

First, the USARTy and USARTz address are set to 0x1 and 0x2. The USARTy send continuously the character 0x33 to the USARTz. The USARTz toggle LED1, LED2, LED3 and LED4 pins while receiving 0x33.

When a falling edge is applied on BUTTON_KEY EXTI line, an interrupt is generated and in the EXTI9_5_IRQHandler routine, the USARTz is entered in mute mode and still in this mode (no LED toggling) until a rising edge is applied on BUTTON_WAKEUP EXTI Line 0. In this interrupt routine the USARTy send the character of address mark (0x102) to wakeup USARTz. The LED restart toggling.

USARTy and USARTz configured as follow:

  • BaudRate = 9600 baud
  • Word Length = 9 Bits
  • One Stop Bit
  • No parity
  • Hardware flow control disabled (RTS and CTS signals)
  • Receive and transmit enabled
Directory contents
  • USART/MultiProcessor/platform_config.h Evaluation board specific configuration file
  • USART/MultiProcessor/stm32f10x_conf.h Library Configuration file
  • USART/MultiProcessor/stm32f10x_it.h Interrupt handlers header file
  • USART/MultiProcessor/stm32f10x_it.c Interrupt handlers
  • USART/MultiProcessor/main.c Main program
  • USART/MultiProcessor/system_stm32f10x.c STM32F10x system source file
Hardware and Software environment
  • This example runs on STM32F10x Connectivity line, High-Density, High-Density Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density and Low-Density Value line Devices.
  • This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) evaluation boards and can be easily tailored to any other supported device and development board. To select the STMicroelectronics evaluation board used to run the example, uncomment the corresponding line in USART/MultiProcessor/platform_config.h or stm32_eval.h file.
  • STM32100E-EVAL Set-up
    • Connect a null-modem female/female RS232 cable between CN5 and CN10.
    • Use Key push-button connected to pin PG.08 (EXTI Line8)
    • Use Wakeup push-button connected to pin PA.00 (EXTI Line0)
    • Use LED1, LED2, LED3 and LED4 leds connected respectively to PF.06, PF.07, PF.08 and PF.09 pins
      Note:
      Make sure that jumper JP5 is not open. Make sure that jumper JP4 is in position 1<-->2.
  • STM32100B-EVAL Set-up
    • Connect a null-modem female/female RS232 cable between CN9 and CN10.
      Note:
      In this case USART2 Tx and Rx pins are remapped by software on PD.05 and PD.06 respectively.
    • Use Key push-button connected to pin PB.09 (EXTI Line9)
    • Use Wakeup push-button connected to pin PA.00 (EXTI Line0)
    • Use LED1, LED2, LED3 and LED4 leds connected respectively to PC.06, PC.07, PC.08 and PC.09 pins
  • STM3210C-EVAL Set-up
    • Connect USART2 Tx pin (PD.05) to USART3 Rx pin (PC.11)
    • Connect USART2 Rx pin (PD.06) to USART3 Tx pin (PC.10)
    • Use Key push-button connected to pin PB.09 (EXTI Line9)
    • Use Wakeup push-button connected to pin PA.00 (EXTI Line0)
    • Use LED1, LED2, LED3 and LED4 connected respectively to PD.07, PD.13, PF.03 and PD.04 pins
      Note:
      In this case USART3 Tx and Rx pins are remapped by software. Make sure that jumpers JP19 and JP18 are open. Make sure that the Jumper 14 (JP14) is in position 2<-->3.
  • STM3210E-EVAL Set-up
    • Connect a null-modem female/female RS232 cable between CN12 and CN8.
    • Use Key push-button connected to pin PG.08 (EXTI Line8)
    • Use Wakeup push-button connected to pin PA.00 (EXTI Line0)
    • Use LED1, LED2, LED3 and LED4 leds connected respectively to PF.06, PF0.7, PF.08 and PF.09 pins
      Note:
      Make sure that the Jumper 4 (JP4) is in position 1<-->2.
  • STM3210B-EVAL Set-up
    • Connect a null-modem female/female RS232 cable between CN5 and CN6.
      Note:
      In this case USART2 Tx and Rx pins are remapped by software on PD.05 and PD.06 respectively.
    • Use Key push-button connected to pin PB.09 (EXTI Line9)
    • Use Wakeup push-button connected to pin PA.00 (EXTI Line0)
    • Use LED1, LED2, LED3 and LED4 leds connected respectively to PC.06, PC.07, PC.08 and PC.09 pins
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: USART Polling example

  • STM32F10x Standard Peripheral's Examples

USART Polling example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    USART/Polling/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the USART Polling example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example provides a basic communication between USARTy and USARTz using flags. USARTy and USARTz can be USART1 and USART2 or USART2 and USART3, depending on the STMicroelectronics EVAL board you are using.

First, the USARTy sends TxBuffer to USARTz. The USARTz reads the received data and store it into RxBuffer. The received data is then compared with the send ones and the result of this comparison is stored in the "TransferStatus" variable.

USARTy and USARTz configured as follow:

  • BaudRate = 230400 baud
  • Word Length = 8 Bits
  • One Stop Bit
  • Even parity
  • Hardware flow control disabled (RTS and CTS signals)
  • Receive and transmit enabled
Directory contents
  • USART/Polling/platform_config.h Evaluation board specific configuration file
  • USART/Polling/stm32f10x_conf.h Library Configuration file
  • USART/Polling/stm32f10x_it.h Interrupt handlers header file
  • USART/Polling/stm32f10x_it.c Interrupt handlers
  • USART/Polling/main.c Main program
  • USART/Polling/system_stm32f10x.c STM32F10x system source file
Hardware and Software environment
  • This example runs on STM32F10x Connectivity line, High-Density, High-Density Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density and Low-Density Value line Devices.
  • This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) evaluation boards and can be easily tailored to any other supported device and development board. To select the STMicroelectronics evaluation board used to run the example, uncomment the corresponding line in USART/Polling/platform_config.h file
  • STM32100E-EVAL Set-up
    • Connect a null-modem female/female RS232 cable between CN10 (USART1) and CN5 (USART2). @ note Make sure that jumper JP5 is not open.
  • STM32100B-EVAL Set-up
    • Connect a null-modem female/female RS232 cable between CN10 (USART1) and CN9 (USART2).
      Note:
      In this case USART2 Tx and Rx pins are remapped by software on PD.05 and PD.06 respectively.
  • STM3210C-EVAL Set-up
    • Connect USART2 Tx pin (PD.05) to USART3 Rx pin (PC.11)
    • Connect USART2 Rx pin (PD.06) to USART3 Tx pin (PC.10)
      Note:
      In this case USART3 Tx and Rx pins are remapped by software. Make sure that jumpers JP19 and JP18 are open.
  • STM3210E-EVAL Set-up
    • Connect a null-modem female/female RS232 cable between CN12 (USART1) and CN8 (USART2).
  • STM3210B-EVAL Set-up
    • Connect a null-modem female/female RS232 cable between CN6 (USART1) and CN5 (USART2).
      • In this case USART2 Tx and Rx pins are remapped by software on PD.05 and PD.06 respectively.
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: USART Printf example

  • STM32F10x Standard Peripheral's Examples

USART Printf example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    USART/Printf/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the USART Printf example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example shows how to retarget the C library printf function to the USART. This implementation output the printf message on the Hyperterminal using USARTx. USARTx can be USART1 or USART2 depending on the EVAL board you are using.

The USARTx is configured as follow:

  • BaudRate = 115200 baud
  • Word Length = 8 Bits
  • One Stop Bit
  • No parity
  • Hardware flow control disabled (RTS and CTS signals)
  • Receive and transmit enabled
Directory contents
  • USART/Printf/stm32f10x_conf.h Library Configuration file
  • USART/Printf/stm32f10x_it.h Interrupt handlers header file
  • USART/Printf/stm32f10x_it.c Interrupt handlers
  • USART/Printf/main.c Main program
  • USART/Printf/system_stm32f10x.c STM32F10x system source file
Hardware and Software environment
  • This example runs on STM32F10x Connectivity line, High-Density, High-Density Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density and Low-Density Value line Devices.
  • This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) evaluation boards and can be easily tailored to any other supported device and development board. To select the STMicroelectronics evaluation board used to run the example, uncomment the corresponding line in stm32_eval.h file (under Utilities)
  • STM32100E-EVAL Set-up
    • Connect a null-modem female/female RS232 cable between the DB9 connector CN10 and PC serial port.
  • STM32100B-EVAL Set-up
    • Connect a null-modem female/female RS232 cable between the DB9 connector CN10 and PC serial port.
  • STM3210C-EVAL Set-up
    • Connect a null-modem female/female RS232 cable between the DB9 connector CN6 (USART2) and PC serial port.
      Note:
      Make sure that jumpers JP19 and JP18 are open.
  • STM3210E-EVAL Set-up
    • Connect a null-modem female/female RS232 cable between the DB9 connector CN12(when USART1 is used) and PC serial port.
  • STM3210B-EVAL Set-up
    • Connect a null-modem female/female RS232 cable between the DB9 connector CN6(when USART1 is used) and PC serial port.
  • Hyperterminal configuration:
    • Word Length = 8 Bits
    • One Stop Bit
    • No parity
    • BaudRate = 115200 baud
    • flow control: None
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: USART Smartcard example

  • STM32F10x Standard Peripheral's Examples

USART Smartcard example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    USART/Smartcard/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the USART Smartcard example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example provides a description of how to use the USART in Smartcard mode. The example gives only the possibility to read the ATR and decode it into predefined buffer. First, the code is waiting for an card insertion. If a card is detected through the EXTI Line interrupt (connected to the Smartcard detect pin), a reset signal is applied to the card through its reset pin. As response to this reset, the card transmit the ATR which will be stored in predefined buffer. Once the ATR is received, it is decoded and stored in a specific structure (SC_A2R) and the card protocol type is stored in a variable. ATRDecodeStatus variable must be equal to 1 (PASSED) when the sequence succeed.

The used Smartcard should be ISO7816-3 T=0 compatible.

SC_USART configured as follow:

  • Word Length = 9 Bits
  • 0.5 Stop Bit
  • Even parity
  • BaudRate = 12096 baud
  • Hardware flow control disabled (RTS and CTS signals)
  • Tx and Rx enabled
  • USART Clock enabled
  • USART CPOL: Clock is active low
  • USART CPHA: Data is captured on the second edge
  • USART LastBit: The clock pulse of the last data bit is not output to the SCLK pin
Directory contents
  • USART/Smartcard/platform_config.h Evaluation board specific configuration file
  • USART/Smartcard/stm32f10x_conf.h Library Configuration file
  • USART/Smartcard/stm32f10x_it.h Interrupt handlers header file
  • USART/Smartcard/stm32f10x_it.c Interrupt handlers
  • USART/Smartcard/main.c Main program
  • USART/Smartcard/system_stm32f10x.c STM32F10x system source file
Hardware and Software environment
  • This example runs on STM32F10x Connectivity line, High-Density, High-Density Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density and Low-Density Value line Devices.
  • This example has been tested with STMicroelectronics STM3210C-EVAL (Connectivity line), STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) evaluation boards and can be easily tailored to any other supported device and development board. To select the STMicroelectronics evaluation board used to run the example, uncomment the corresponding line in USART/Smartcard/platform_config.h file
  • STM3210C-EVAL Set-up
    • Plug a Smartcard (ISO7816-3 T=0 compatible) into the dedicated Smartcard connector CN5.
      Note:
      In this case USART3 Tx and CK pins are full remapped by software. Make sure that Jumper 11 (JP11), Jumper 12 (JP12) and Jumper 13 (JP13) are in position 1<-->2.
  • STM3210E-EVAL Set-up
    • Plug a Smartcard (ISO7816-3 T=0 compatible) into the dedicated Smartcard connector CN18.
      Note:
      Make sure that Jumper 15 (JP15) and Jumper 16 (JP16) are fitted.
  • STM3210B-EVAL Set-up
    • Plug a Smartcard (ISO7816-3 T=0 compatible) into the dedicated Smartcard connector CN16.
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: USART Synchronous example

  • STM32F10x Standard Peripheral's Examples

USART Synchronous example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    USART/Synchronous/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the USART Synchronous example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example provides a basic communication between USARTy (Synchronous mode) and SPIy using flags. USARTy and SPIy can be USART1 and SPI1 or USART2 and SPI3, depending on the STMicroelectronics EVAL board you are using.

First, the USARTy sends data from TxBuffer1 buffer to SPIy using USARTy TXE flag. Data received, using RXNE flag, by SPIy is stored in RxBuffer2 then compared with the sent ones and the result of this comparison is stored in the "TransferStatus1" variable.

Then, the SPIy sends data from TxBuffer2 buffer to USARTy using SPIy TXE flag. Data received, using RXNE flag, by USARTy is stored in RxBuffer1 then compared with the sent ones and the result of this comparison is stored in the "TransferStatus2" variable.

USARTy configured as follow:

  • BaudRate = 115200 baud
  • Word Length = 8 Bits
  • One Stop Bit
  • No parity
  • Hardware flow control disabled (RTS and CTS signals)
  • Receive and transmit enabled
  • USART Clock enabled
  • USART CPOL: Clock is active high
  • USART CPHA: Data is captured on the second edge
  • USART LastBit: The clock pulse of the last data bit is output to the SCLK pin

SPIy configured as follow:

  • Direction = 2 Lines FullDuplex
  • Mode = Slave Mode
  • DataSize = 8 Bits
  • CPOL = Clock is active high
  • CPHA = Data is captured on the second edge
  • NSS = NSS Software
  • First Bit = First Bit is the LSB
Directory contents
  • USART/Synchronous/platform_config.h Evaluation board specific configuration file
  • USART/Synchronous/stm32f10x_conf.h Library Configuration file
  • USART/Synchronous/stm32f10x_it.h Interrupt handlers header file
  • USART/Synchronous/stm32f10x_it.c Interrupt handlers
  • USART/Synchronous/main.c Main program
  • USART/Synchronous/system_stm32f10x.c STM32F10x system source file
Hardware and Software environment
  • This example runs on STM32F10x Connectivity line, High-Density, High-Density Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density and Low-Density Value line Devices.
  • This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density Value line), STM32100B-EVAL (Medium-Density Value line), STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) evaluation boards and can be easily tailored to any other supported device and development board. This example can't be tested with STM3210C-EVAL (Connectivity Line) evaluation board since the USART CK pins are already used by other on-board modules. To select the STMicroelectronics evaluation board used to run the example, uncomment the corresponding line in USART/Synchronous/platform_config.h file
  • STM32100E-EVAL Set-up
    • Connect USART1_Tx(PA.09) to SPI1_MOSI(PA.07), USART1_Rx(PA.10) to SPI1_MISO(PA.06) and USART1_CK(PA.08) to SPI1_SCK(PA.05).
  • STM32100B-EVAL Set-up
    • Connect USART1_Tx(PA.09) to SPI1_MOSI(PA.07), USART1_Rx(PA.10) to SPI1_MISO(PA.06) and USART1_CK(PA.08) to SPI1_SCK(PA.05).
  • STM3210E-EVAL Set-up
    • Connect USART1_Tx(PA.09) to SPI1_MOSI(PA.07), USART1_Rx(PA.10) to SPI1_MISO(PA.06) and USART1_CK(PA.08) to SPI1_SCK(PA.05).
  • STM3210B-EVAL Set-up
    • Connect USART1_Tx(PA.09) to SPI1_MOSI(PA.07), USART1_Rx(PA.10) to SPI1_MISO(PA.06) and USART1_CK(PA.08) to SPI1_SCK(PA.05).
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: WWDG Reset example

  • STM32F10x Standard Peripheral's Examples

WWDG Reset example

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    WWDG/WWDG_Reset/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   Description of the WWDG Reset example.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Example Description

This example shows how to update at regular period the WWDG counter and how to simulate a software fault generating an MCU WWDG reset on expiry of a programmed time period.

The WWDG timeout is set to 65.53ms and the refresh window is set to 80. The WWDG counter is refreshed each 50ms in the main program infinite loop to prevent a WWDG reset. LED2 is also toggled each 50ms indicating that the program is running.

An EXTI Line is connected to a GPIO pin, and configured to generate an interrupt on the rising edge of the signal.

The EXTI Line is used to simulate a software failure: once the EXTI Line event occurs, by pressing the Key push-button, the corresponding interrupt is served. In the ISR, a write to invalid address generates a Hardfault exception containing an infinite loop and preventing to return to main program (the WWDG counter is not refreshed). As a result, when the WWDG counter falls to 63, the WWDG reset occurs. If the WWDG reset is generated, after the system resumes from reset, LED1 turns on.

If the EXTI Line event does not occur, the WWDG counter is indefinitely refreshed in the main program infinite loop, and there is no WWDG reset.

In this example the system clock is set to 24 MHz on Value line devices and to 72 MHz on other devices.

Directory contents
  • WWDG/WWDG_Reset/stm32f10x_conf.h Library Configuration file
  • WWDG/WWDG_Reset/stm32f10x_it.c Interrupt handlers
  • WWDG/WWDG_Reset/stm32f10x_it.h Header for stm32f10x_it.c
  • WWDG/WWDG_Reset/main.c Main program
  • WWDG/WWDG_Reset/system_stm32f10x.c STM32F10x system source file
Hardware and Software environment
  • This example runs on STM32F10x Connectivity line, High-Density, High-Density Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density and Low-Density Value line Devices.
  • This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), STM3210E-EVAL (High-Density and XL-Density)and STM3210B-EVAL (Medium-Density) evaluation boards and can be easily tailored to any other supported device and development board. To select the STMicroelectronics evaluation board used to run the example, uncomment the corresponding line in stm32_eval.h file (under Utilities)
  • STM32100E-EVAL Set-up
    • Use LD1 and LD2 leds connected respectively to PF.06 and PF.07 pins
    • Use the KEY push button connected to PG.08 pin (EXTI Line8).
  • STM32100B-EVAL Set-up
    • Use LD1 and LD2 leds connected respectively to PC.06 and PC.07 pins
    • Use the KEY push button connected to PB.09 pin (EXTI Line9).
  • STM3210C-EVAL Set-up
    • Use LD1 and LD2 connected respectively to PD.07 and PD.13 pins
    • Use the Key push-button connected to pin PB.09 (EXTI Line9).
  • STM3210E-EVAL Set-up
    • Use LD1 and LD2 leds connected respectively to PF.06 and PF.07 pins
    • Use the KEY push button connected to PG.08 pin (EXTI Line8).
  • STM3210B-EVAL Set-up
    • Use LD1 and LD2 leds connected respectively to PC.06 and PC.07 pins
    • Use the KEY push button connected to PB.09 pin (EXTI Line9).
How to use it ?

In order to make the program work, you must do the following :

  • Copy all source files from this example folder to the template folder under Project
  • Open your preferred toolchain
  • Rebuild all files and load your image into target memory
  • Run the example
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: EWARM Project Template

  • STM32F10x Standard Peripherals Project Template

EWARM Project Template

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   This sub directory contains all the user modifiable files needed
  *          to create a new project linked with the STM32F10x Standard Peripheral
  *          Library and working with IAR Embedded Workbench for ARM (EWARM)
  *          software toolchain (version 5.50 and later).
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
  * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
  * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
  * CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
  * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Directory contents
  • project .ewd/.eww/.ewp: A pre-configured project file with the provided library structure that produces an executable image with IAR Embedded Workbench.
  • stm32f10x_flash.icf : This file is the IAR Linker configuration file used to place program code (readonly) in internal FLASH and data (readwrite, Stack and Heap)in internal SRAM. You can customize this file to your need.
  • stm32f10x_flash_extsram.icf: This file is the IAR Linker configuration file used to place program code (readonly) in internal FLASH and data (readwrite, Stack and Heap)in external SRAM. You can customize this file to your need. This file is used only with STM32 High-density devices.
  • stm32f10x_nor.icf: This file is the IAR Linker configuration file used to place program code (readonly) in external NOR FLASH and data (readwrite, Stack and Heap)in internal SRAM. You can customize this file to your need. This file is used only with STM32 High-density devices.
  • stm32f10x_ram.icf: This file is the IAR Linker configuration file used to place program code (readonly) and data (readwrite, Stack and Heap)in internal SRAM. You can customize this file to your need.
How to use it ?
  • Open the Project.eww workspace.
  • In the workspace toolbar select the project config:
    • STM32100B-EVAL: to configure the project for STM32 Medium-density Value line devices
      Note:
      The needed define symbols for this config are already declared in the preprocessor section: USE_STDPERIPH_DRIVER, STM32F10X_MD_VL, USE_STM32100B_EVAL
    • STM3210C-EVAL: to configure the project for STM32 Connectivity line devices
      Note:
      The needed define symbols for this config are already declared in the preprocessor section: USE_STDPERIPH_DRIVER, STM32F10X_CL, USE_STM3210C_EVAL
    • STM3210B-EVAL: to configure the project for STM32 Medium-density devices
      Note:
      The needed define symbols for this config are already declared in the preprocessor section: USE_STDPERIPH_DRIVER, STM32F10X_MD, USE_STM3210B_EVAL
    • STM3210E-EVAL: to configure the project for STM32 High-density devices
      Note:
      The needed define symbols for this config are already declared in the preprocessor section: USE_STDPERIPH_DRIVER, STM32F10X_HD, USE_STM3210E_EVAL
    • STM3210E-EVAL_XL: to configure the project for STM32 XL-density devices
      Note:
      The needed define symbols for this config are already declared in the preprocessor section: USE_STDPERIPH_DRIVER, STM32F10X_XL, USE_STM3210E_EVAL
    • STM32100E-EVAL: to configure the project for STM32 High-density Value line devices
      Note:
      The needed define symbols for this config are already declared in the preprocessor section: USE_STDPERIPH_DRIVER, STM32F10X_HD_VL, USE_STM32100E_EVAL
  • Rebuild all files: Project->Rebuild all
  • Load project image: Project->Debug
  • Run program: Debug->Go(F5)
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 32 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 32 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: HiTOP Project Template for STM32F10x High-density Value line devices

  • STM32F10x Standard Peripherals Project Template
  • HiTop Project Template

HiTOP Project Template for STM32F10x High-density Value line devices

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   This sub directory contains all the user modifiable files needed
  *          to create a new project linked with the STM32F10x Standard Peripheral
  *          Library and working with HiTOP software toolchain (version 5.40 and later).
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
  * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
  * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
  * CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
  * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Directory contents
  • Project.htp: A pre-configured project file with the provided library structure that produces an executable image with HiTOP
  • cstart_thumb2.asm: This file initializes the stack pointer and copy initialized sections from ROM to RAM.
  • Objects: This mandatory directory contains the executable images.
  • Settings: This directory contains the linker and script files.
    • arm_arch.lsl: This file is used to place program code (readonly) in internal FLASH and data (readwrite, Stack and Heap) in internal SRAM.
  • link.lnk: This file is the HiTOP linker it invokes the stm32f10x_hd_vl.lsl
  • linkextsram.lnk: This file is the HiTOP linker it invokes the stm32f10x_hd_vl_extsram.lsl
  • reset_appl.scr: This file is a HiTOP script it performs a target reset.
  • reset_go_main.scr: This file is a HiTOP script and it sets the Program Counter at the "main" instruction.
  • StartupScript.scr: This file is a HiTOP script and it performs a target reset before loading The executable image.
  • stm32f10x_hd_vl.lsl: This file is used to place program code (readonly) in internal FLASH and data (readwrite, Stack and Heap) in internal SRAM. It contains also the vector table of the STM32 High-density Value line devices. You can customize this file to your need.
  • stm32f10x_hd_vl_extsram.lsl: This file used to place program code (readonly) in internal FLASH and data (readwrite, Stack and Heap) in external SRAM. It contains also the vector table of the STM32 High-density Value line devices. You can customize this file to your need. This file is used only with STM32 High-density Value line devices.
How to use it ?
  • Open the HiTOP toolchain.
  • Browse to open the project.htp
  • A "Download application" window is displayed, click "cancel".
  • Rebuild all files: Project->Rebuild all
  • Load project image : Click "ok" in the "Download application" window.
  • Run the "RESET_GO_MAIN" script to set the PC at the "main"
  • Run program: Debug->Go(F5).
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: HiTOP Project Template for STM32F10x Medium-density Value line devices

  • STM32F10x Standard Peripherals Project Template
  • HiTop Project Template

HiTOP Project Template for STM32F10x Medium-density Value line devices

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   This sub directory contains all the user modifiable files needed
  *          to create a new project linked with the STM32F10x Standard Peripheral
  *          Library and working with HiTOP software toolchain (version 5.40 and later).
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
  * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
  * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
  * CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
  * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Directory contents
  • Project.htp: A pre-configured project file with the provided library structure that produces an executable image with HiTOP
  • cstart_thumb2.asm: This file initializes the stack pointer and copy initialized sections from ROM to RAM.
  • Objects: This mandatory directory contains the executable images.
  • Settings: This directory contains the linker and script files.
    • arm_arch.lsl: This file is used to place program code (readonly) in internal FLASH and data (readwrite, Stack and Heap) in internal SRAM.
  • link.lnk: This file is the HiTOP linker it invokes the stm32f10x_MD_VL.lsl.
  • reset_appl.scr: This file is a HiTOP script it performs a target reset.
  • reset_go_main.scr: This file is a HiTOP script and it sets the Program Counter at the "main" instruction.
  • StartupScript.scr: This file is a HiTOP script and it performs a target reset before loading The executable image.
  • stm32f10x_MD_VL.lsl: This file is used to place program code (readonly) in internal FLASH and data (readwrite, Stack and Heap) in internal SRAM. It contains also the vector table of the STM32 Medium-density Value line devices. You can customize this file to your need.
How to use it ?
  • Open the HiTOP toolchain.
  • Browse to open the project.htp
  • A "Download application" window is displayed, click "cancel".
  • Rebuild all files: Project->Rebuild all
  • Load project image : Click "ok" in the "Download application" window.
  • Run the "RESET_GO_MAIN" script to set the PC at the "main"
  • Run program: Debug->Go(F5).
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: HiTOP Project Template for STM32F10x Medium-density devices

  • STM32F10x Standard Peripherals Project Template
  • HiTop Project Template

HiTOP Project Template for STM32F10x Medium-density devices

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   This sub directory contains all the user modifiable files needed
  *          to create a new project linked with the STM32F10x Standard Peripheral
  *          Library and working with HiTOP software toolchain (version 5.40 and later).
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
  * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
  * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
  * CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
  * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Directory contents
  • Project.htp: A pre-configured project file with the provided library structure that produces an executable image with HiTOP
  • cstart_thumb2.asm: This file initializes the stack pointer and copy initialized sections from ROM to RAM.
  • Objects: This mandatory directory contains the executable images.
  • Settings: This directory contains the linker and script files.
    • arm_arch.lsl: This file is used to place program code (readonly) in internal FLASH and data (readwrite, Stack and Heap) in internal SRAM.
  • link.lnk: This file is the HiTOP linker it invokes the STM32F10x_md.lsl.
  • reset_appl.scr: This file is a HiTOP script it performs a target reset.
  • reset_go_main.scr: This file is a HiTOP script and it sets the Program Counter at the "main" instruction.
  • StartupScript.scr: This file is a HiTOP script and it performs a target reset before loading The executable image.
  • STM32F10x_md.lsl: This file is used to place program code (readonly) in internal FLASH and data (readwrite, Stack and Heap) in internal SRAM. It contains also the vector table of the STM32 Medium-density devices. You can customize this file to your need.
How to use it ?
  • Open the HiTOP toolchain.
  • Browse to open the project.htp
  • A "Download application" window is displayed, click "cancel".
  • Rebuild all files: Project->Rebuild all
  • Load project image : Click "ok" in the "Download application" window.
  • Run the "RESET_GO_MAIN" script to set the PC at the "main"
  • Run program: Debug->Go(F5).
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: HiTOP Project Template for STM32F10x Connectivity line devices

  • STM32F10x Standard Peripherals Project Template
  • HiTop Project Template

HiTOP Project Template for STM32F10x Connectivity line devices

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   This sub directory contains all the user modifiable files needed
  *          to create a new project linked with the STM32F10x Standard Peripheral
  *          Library and working with HiTOP software toolchain (version 5.40 and later).
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
  * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
  * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
  * CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
  * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Directory contents
  • Project.htp: A pre-configured project file with the provided library structure that produces an executable image with HiTOP
  • cstart_thumb2.asm: This file initializes the stack pointer and copy initialized sections from ROM to RAM.
  • Objects: This mandatory directory contains the executable images.
  • Settings: This directory contains the linker and script files.
    • arm_arch.lsl: This file is used to place program code (readonly) in internal FLASH and data (readwrite, Stack and Heap) in internal SRAM.
  • link.lnk: This file is the HiTOP linker it invokes the STM32F10x_cl.lsl.
  • reset_appl.scr: This file is a HiTOP script it performs a target reset.
  • reset_go_main.scr: This file is a HiTOP script and it sets the Program Counter at the "main" instruction.
  • StartupScript.scr: This file is a HiTOP script and it performs a target reset before loading The executable image.
  • STM32F10x_cl.lsl: This file is used to place program code (readonly) in internal FLASH and data (readwrite, Stack and Heap) in internal SRAM. It contains also the vector table of the STM32 Connectivity line devices. You can customize this file to your need.
How to use it ?
  • Open the HiTOP toolchain.
  • Browse to open the project.htp
  • A "Download application" window is displayed, click "cancel".
  • Rebuild all files: Project->Rebuild all
  • Load project image : Click "ok" in the "Download application" window.
  • Run the "RESET_GO_MAIN" script to set the PC at the "main"
  • Run program: Debug->Go(F5).
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: HiTOP Project Template for STM32F10x High-density devices

  • STM32F10x Standard Peripherals Project Template
  • HiTop Project Template

HiTOP Project Template for STM32F10x High-density devices

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   This sub directory contains all the user modifiable files needed
  *          to create a new project linked with the STM32F10x Standard Peripherals
  *          Library and working with HiTOP software toolchain (version 5.40 and later).
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
  * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
  * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
  * CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
  * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Directory contents
  • Project.htp: A pre-configured project file with the provided library structure that produces an executable image with HiTOP
  • cstart_thumb2.asm: This file initializes the stack pointer and copy initialized sections from ROM to RAM.
  • Objects: This mandatory directory contains the executable images.
  • Settings: This directory contains the linker and script files.
    • arm_arch.lsl: This file is used to place program code (readonly) in internal FLASH and data (readwrite, Stack and Heap) in internal SRAM.
  • flash_nor.scr: This file is a HiTOP script allowing the FSMC configuration. It should be executed before programming the NOR flash of the STM32 High-density devices.
  • link.lnk: This file is the HiTOP linker it invokes the STM32F10x_hd.lsl.
  • linkextsram.lnk: This file is the HiTOP linker it invokes the STM32F10x_extsram.lsl.
  • linknor.lnk: This file is the HiTOP linker it invokes the STM32F10xnor.lsl.
  • reset_appl.scr: This file is a HiTOP script it performs a target reset.
  • reset_go_main.scr: This file is a HiTOP script and it sets the Program Counter at the "main" instruction.
  • StartupScript.scr: This file is a HiTOP script and it performs a target reset before loading The executable image.
  • STM32F10x_extsram.lsl: This file used to place program code (readonly) in internal FLASH and data (readwrite, Stack and Heap) in external SRAM. It contains also the vector table of the STM32 high-density devices. You can customize this file to your need. This file is used only with STM32 High-density devices.
  • STM32F10x_hd.lsl: This file is used to place program code (readonly) in internal FLASH and data (readwrite, Stack and Heap) in internal SRAM. It contains also the vector table of the STM32 High-Density devices. You can customize this file to your need.
  • STM32F10xnor.lsl: This file used to place program code (readonly) in external NOR FLASH and data (readwrite, Stack and Heap) in internal SRAM. It contains also the vector table of the STM32 high-density devices. You can customize this file to your need. This file is used only with STM32 High-density devices.
How to use it ?
  • Open the HiTOP toolchain.
  • Browse to open the project.htp
  • A "Download application" window is displayed, click "cancel".
  • Rebuild all files: Project->Rebuild all
  • Load project image : Click "ok" in the "Download application" window.
  • Run the "RESET_GO_MAIN" script to set the PC at the "main"
  • Run program: Debug->Go(F5).
  • When using High-density devices, it is mandatory to reset the target before loading the project into target
  • It is recommended to run the reset script ( click on TR button in the toolbar menu) after loading the project into target.
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: HiTOP Project Template for STM32F10x XL-density devices

  • STM32F10x Standard Peripherals Project Template
  • HiTop Project Template

HiTOP Project Template for STM32F10x XL-density devices

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   This sub directory contains all the user modifiable files needed
  *          to create a new project linked with the STM32F10x Standard Peripheral
  *          Library and working with HiTOP software toolchain (version 5.40 and later).
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
  * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
  * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
  * CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
  * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Directory contents
  • Project.htp: A pre-configured project file with the provided library structure that produces an executable image with HiTOP
  • cstart_thumb2.asm: This file initializes the stack pointer and copy initialized sections from ROM to RAM.
  • Objects: This mandatory directory contains the executable images.
  • Settings: This directory contains the linker and script files.
    • arm_arch.lsl: This file is used to place program code (readonly) in internal FLASH and data (readwrite, Stack and Heap) in internal SRAM.
  • link.lnk: This file is the HiTOP linker it invokes the STM32F10x_XL.lsl.
  • reset_appl.scr: This file is a HiTOP script it performs a target reset.
  • reset_go_main.scr: This file is a HiTOP script and it sets the Program Counter at the "main" instruction.
  • StartupScript.scr: This file is a HiTOP script and it performs a target reset before loading The executable image.
  • STM32F10x_Xl.lsl: This file is used to place program code (readonly) in internal FLASH and data (readwrite, Stack and Heap) in internal SRAM. It contains also the vector table of the STM32 XL-density line devices. You can customize this file to your need.
How to use it ?
  • Open the HiTOP toolchain.
  • Browse to open the project.htp
  • A "Download application" window is displayed, click "cancel".
  • Rebuild all files: Project->Rebuild all
  • Load project image : Click "ok" in the "Download application" window.
  • Run the "RESET_GO_MAIN" script to set the PC at the "main"
  • Run program: Debug->Go(F5).
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: RIDE Project Template

  • STM32F10x Standard Peripherals Project Template

RIDE Project Template

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   This sub directory contains all the user modifiable files
  *          needed to create a new project linked with the STM32F10x
  *          Standard Peripheral Library and working with RIDE7 software
  *          toolchain (RIDE7 IDE:7.30.10, RKitARM for RIDE7:1.30.10)
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
  * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
  * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
  * CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
  * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Directory contents
  • project .rprj/.rapp: A pre-configured project file with the provided library structure that produces an executable image with RIDE7.
  • stm32f10x_flash_extsram.ld: This file is the RAISONANCE linker script used to place program code (readonly) in internal FLASH and data (readwrite, Stack and Heap)in external SRAM. You can customize this file to your need.
How to use it ?
  • Open the Project.rprj project.
  • In the configuration toolbar(Project->properties) select the project config:
    • STM32100E-EVAL: to configure the project for STM32 Value Line High-density devices
    • STM32100B-EVAL: to configure the project for STM32 Medium-density Value line devices
    • STM3210C-EVAL: to configure the project for STM32 Connectivity line devices
    • STM3210B-EVAL: to configure the project for STM32 Medium-density devices
    • STM3210E-EVAL: to configure the project for STM32 High-density devices
    • STM3210E-EVAL_XL: to configure the project for STM32 XL-density devices
  • Rebuild all files: Project->build project
  • Load project image: Debug->start(ctrl+D)
  • Run program: Debug->Run(ctrl+F9)
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 32 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 32 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: Note for MDK-ARM

  • STM32F10x Standard Peripherals Project Template
  • MDK-ARM Project Template

Note for MDK-ARM

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    note.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   This file contains the needed steps to use the default startup file
  *          provided by RealView Microcontroller Development Kit(MDK-ARM).
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
  * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
  * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
  * CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
  * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************

With MDK-ARM toolchain, a simple putchar function executes a SWI and activates
a low level putchar function.
You have to redirect the low level to your own implementation of these functions.

To guarantee that no functions using the semihosting SWI are included in your
application, either:

1. Ensure that the MicroLib option is checked since the microlib does not support
semihosting
or
2. Use
- IMPORT __use_no_semihosting_swi from assembly language
- #pragma import(__use_no_semihosting_swi) from C.
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 32 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 32 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

  ******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
  * @file    note.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   This file contains the needed step to use "printf" with TrueSTUDIO
  *          toolchain.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
  * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
  * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
  * CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
  * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************

The C runtime library include many functions, including some that typically handle I/O. The I/O related runtime functions include printf(), fopen(), fclose(), and many others.

It is common to redirect the I/O from these functions to the actual embedded platform, such as redirecting printf() output to an LCD display or a serial cable, or to redirect file operations like fopen() and fclose() to some Flash file system middleware.

The free Lite version of TrueSTUDIO do not support I/O redirection, and instead have do-nothing stubs compiled into the C runtime library.

To support printf() redirection in the professional version, you should do the following:

  • Open TrueSTUDIO professional and load your project.
  • In the Project explorer, Right click on the project and select New->Other...
  • Expand System calls
  • Select Minimal System Calls Implementation and click next.
  • Click on Finish and verify that "syscalls.c" is added to your project.
  • Add the following code in the _write() function in "syscalls.c".
   /*****************************************/
   int Index;

   for (Index = 0; Index < len; Index++)
   {
      __io_putchar( *ptr++ );
   }

   return len;
   /*****************************************/
  • Finally, Rebuild your project.
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 32 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 32 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: TrueSTUDIO Project Template for High-density Value line devices

  • STM32F10x Standard Peripherals Project Template
  • TrueSTUDIO Project Template

TrueSTUDIO Project Template for High-density Value line devices

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   This sub directory contains all the user modifiable files
  *          needed to create a new project linked with the STM32F10x
  *          Standard Peripheral Library and working with TrueSTUDIO software
  *          toolchain (Version 2.0.1 and later)
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
  * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
  * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
  * CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
  * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Directory contents
  • project .cproject/.project: A pre-configured project file with the provided library structure that produces an executable image with TrueSTUDIO.
  • stm32_flash.ld: This file is the TrueSTUDIO linker script used to place program code (readonly) in internal FLASH and data (readwrite, Stack and Heap)in internal SRAM. You can customize this file to your need.
How to use it ?
  • Open the TrueSTUDIO toolchain.
  • Click on File->Switch Workspace->Other and browse to TrueSTUDIO workspace directory.
  • Click on File->Import, select General->'Existing Projects into Workspace' and then click "Next".
  • Browse to the TrueSTUDIO workspace directory and select the project:
    • STM32100E-EVAL: to configure the project for STM32 High-density Value line devices.
  • Under Windows->Preferences->General->Workspace->Linked Resources, add a variable path named "CurPath" which points to the folder containing "Libraries", "Project" and "Utilities" folders.
  • Rebuild all project files: Select the project in the "Project explorer" window then click on Project->build project menu.
  • Run program: Select the project in the "Project explorer" window then click Run->Debug (F11)
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 32 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 32 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: TrueSTUDIO Project Template for Medium-density Value line devices

  • STM32F10x Standard Peripherals Project Template
  • TrueSTUDIO Project Template

TrueSTUDIO Project Template for Medium-density Value line devices

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   This sub directory contains all the user modifiable files
  *          needed to create a new project linked with the STM32F10x
  *          Standard Peripheral Library and working with TrueSTUDIO software
  *          toolchain (Version 2.0.1 and later)
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
  * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
  * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
  * CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
  * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Directory contents
  • project .cproject/.project: A pre-configured project file with the provided library structure that produces an executable image with TrueSTUDIO.
  • stm32_flash.ld: This file is the TrueSTUDIO linker script used to place program code (readonly) in internal FLASH and data (readwrite, Stack and Heap)in internal SRAM. You can customize this file to your need.
How to use it ?
  • Open the TrueSTUDIO toolchain.
  • Click on File->Switch Workspace->Other and browse to TrueSTUDIO workspace directory.
  • Click on File->Import, select General->'Existing Projects into Workspace' and then click "Next".
  • Browse to the TrueSTUDIO workspace directory and select the project:
    • STM32100B-EVAL: to configure the project for STM32 Medium-density Value line devices.
  • Under Windows->Preferences->General->Workspace->Linked Resources, add a variable path named "CurPath" which points to the folder containing "Libraries", "Project" and "Utilities" folders.
  • Rebuild all project files: Select the project in the "Project explorer" window then click on Project->build project menu.
  • Run program: Select the project in the "Project explorer" window then click Run->Debug (F11)
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 32 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 32 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: TrueSTUDIO Project Template for Medium-density devices

  • STM32F10x Standard Peripherals Project Template
  • TrueSTUDIO Project Template

TrueSTUDIO Project Template for Medium-density devices

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   This sub directory contains all the user modifiable files
  *          needed to create a new project linked with the STM32F10x
  *          Standard Peripheral Library and working with TrueSTUDIO software
  *          toolchain (Version 2.0.1 and later)
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
  * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
  * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
  * CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
  * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Directory contents
  • project .cproject/.project: A pre-configured project file with the provided library structure that produces an executable image with TrueSTUDIO.
  • stm32_flash.ld: This file is the TrueSTUDIO linker script used to place program code (readonly) in internal FLASH and data (readwrite, Stack and Heap)in internal SRAM. You can customize this file to your need.
How to use it ?
  • Open the TrueSTUDIO toolchain.
  • Click on File->Switch Workspace->Other and browse to TrueSTUDIO workspace directory.
  • Click on File->Import, select General->'Existing Projects into Workspace' and then click "Next".
  • Browse to the TrueSTUDIO workspace directory and select the project:
    • STM3210B-EVAL: to configure the project for STM32 Medium-density devices.
  • Under Windows->Preferences->General->Workspace->Linked Resources, add a variable path named "CurPath" which points to the folder containing "Libraries", "Project" and "Utilities" folders.
  • Rebuild all project files: Select the project in the "Project explorer" window then click on Project->build project menu.
  • Run program: Select the project in the "Project explorer" window then click Run->Debug (F11)
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 32 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 32 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: TrueSTUDIO Project Template for Connectivity line devices

  • STM32F10x Standard Peripherals Project Template
  • TrueSTUDIO Project Template

TrueSTUDIO Project Template for Connectivity line devices

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   This sub directory contains all the user modifiable files
  *          needed to create a new project linked with the STM32F10x
  *          Standard Peripheral Library and working with TrueSTUDIO software
  *          toolchain (Version 2.0.1 and later)
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
  * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
  * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
  * CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
  * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Directory contents
  • project .cproject/.project: A pre-configured project file with the provided library structure that produces an executable image with TrueSTUDIO.
  • stm32_flash.ld: This file is the TrueSTUDIO linker script used to place program code (readonly) in internal FLASH and data (readwrite, Stack and Heap)in internal SRAM. You can customize this file to your need.
How to use it ?
  • Open the TrueSTUDIO toolchain.
  • Click on File->Switch Workspace->Other and browse to TrueSTUDIO workspace directory.
  • Click on File->Import, select General->'Existing Projects into Workspace' and then click "Next".
  • Browse to the TrueSTUDIO workspace directory and select the project:
    • STM3210C-EVAL: to configure the project for STM32 Connectivity line devices.
  • Under Windows->Preferences->General->Workspace->Linked Resources, add a variable path named "CurPath" which points to the folder containing "Libraries", "Project" and "Utilities" folders.
  • Rebuild all project files: Select the project in the "Project explorer" window then click on Project->build project menu.
  • Run program: Select the project in the "Project explorer" window then click Run->Debug (F11)
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 32 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 32 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: TrueSTUDIO Project Template for High-density devices

  • STM32F10x Standard Peripherals Project Template
  • TrueSTUDIO Project Template

TrueSTUDIO Project Template for High-density devices

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   This sub directory contains all the user modifiable files
  *          needed to create a new project linked with the STM32F10x
  *          Standard Peripheral Library and working with TrueSTUDIO software
  *          toolchain (Version 2.0.1 and later)
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
  * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
  * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
  * CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
  * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Directory contents
  • project .cproject/.project: A pre-configured project file with the provided library structure that produces an executable image with TrueSTUDIO.
  • stm32_flash.ld: This file is the TrueSTUDIO linker script used to place program code (readonly) in internal FLASH and data (readwrite, Stack and Heap)in internal SRAM. You can customize this file to your need.
How to use it ?
  • Open the TrueSTUDIO toolchain.
  • Click on File->Switch Workspace->Other and browse to TrueSTUDIO workspace directory.
  • Click on File->Import, select General->'Existing Projects into Workspace' and then click "Next".
  • Browse to the TrueSTUDIO workspace directory and select the project:
    • STM3210E-EVAL: to configure the project for STM32 High-density devices.
  • Under Windows->Preferences->General->Workspace->Linked Resources, add a variable path named "CurPath" which points to the folder containing "Libraries", "Project" and "Utilities" folders.
  • Rebuild all project files: Select the project in the "Project explorer" window then click on Project->build project menu.
  • Run program: Select the project in the "Project explorer" window then click Run->Debug (F11)
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 32 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 32 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: TrueSTUDIO Project Template for XL-density devices

  • STM32F10x Standard Peripherals Project Template
  • TrueSTUDIO Project Template

TrueSTUDIO Project Template for XL-density devices

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   This sub directory contains all the user modifiable files
  *          needed to create a new project linked with the STM32F10x
  *          Standard Peripheral Library and working with TrueSTUDIO software
  *          toolchain (Version 2.0.1 and later)
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
  * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
  * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
  * CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
  * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Directory contents
  • project .cproject/.project: A pre-configured project file with the provided library structure that produces an executable image with TrueSTUDIO.
  • stm32_flash.ld: This file is the TrueSTUDIO linker script used to place program code (readonly) in internal FLASH and data (readwrite, Stack and Heap)in internal SRAM. You can customize this file to your need.
How to use it ?
  • Open the TrueSTUDIO toolchain.
  • Click on File->Switch Workspace->Other and browse to TrueSTUDIO workspace directory.
  • Click on File->Import, select General->'Existing Projects into Workspace' and then click "Next".
  • Browse to the TrueSTUDIO workspace directory and select the project:
    • STM3210E-EVAL_XL: to configure the project for STM32 XL-density devices.
  • Under Windows->Preferences->General->Workspace->Linked Resources, add a variable path named "CurPath" which points to the folder containing "Libraries", "Project" and "Utilities" folders.
  • Rebuild all project files: Select the project in the "Project explorer" window then click on Project->build project menu.
  • Run program: Select the project in the "Project explorer" window then click Run->Debug (F11)
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 32 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 32 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: STMicroelectronics STM32 Evaluation Boards Drivers

STMicroelectronics STM32 Evaluation Boards Drivers

  • STM32 EVAL Driver
    • STM32_EVAL
  • STM32 EVAL Common
    • FONTS
    • STM32_EVAL_I2C_EE
    • STM32_EVAL_I2C_TSENSOR
    • STM32_EVAL_SDIO_SD
    • STM32_EVAL_SPI_FLASH
    • STM32_EVAL_SPI_SD
  • STM32100E EVAL Board
    • STM3210E_EVAL
    • STM32100E_EVAL_LCD
    • STM32100E_EVAL_CEC
    • STM32100E_EVAL_FSMC_ONENAND
    • STM32100E_EVAL_FSMC_SRAM
  • STM32100B EVAL Board
    • STM32100B_EVAL
    • STM32100B_EVAL_LCD
    • STM32100B_EVAL_CEC
  • STM3210B EVAL Board
    • STM3210B_EVAL
    • STM3210B_EVAL_LCD
  • STM3210C EVAL Board
    • STM3210C_EVAL
    • STM3210C_EVAL_LCD
    • STM3210C_EVAL_IOE
  • STM3210E EVAL Board
    • STM3210E_EVAL
    • STM3210E_EVAL_LCD
    • STM3210E_EVAL_FSMC_NAND
    • STM3210E_EVAL_FSMC_NOR
    • STM3210E_EVAL_FSMC_SRAM


STM32F10x Standard Peripherals Firmware Library: Library_configuration_section

Defines

Library_configuration_section

Stm32f10x

Defines

#define | __STM32F10X_STDPERIPH_VERSION
#define | __STM32F10X_STDPERIPH_VERSION_MAIN (0x03)
STM32F10x Standard Peripheral Library version number.
#define | __STM32F10X_STDPERIPH_VERSION_RC (0x00)
#define | __STM32F10X_STDPERIPH_VERSION_SUB1 (0x05)
#define | __STM32F10X_STDPERIPH_VERSION_SUB2 (0x00)
#define | HSE_STARTUP_TIMEOUT ((uint16_t)0x0500)
In the following line adjust the External High Speed oscillator (HSE) Startup Timeout value.
#define | HSE_VALUE ((uint32_t)8000000)
Comment the line below if you will not use the peripherals drivers.
#define | HSI_VALUE ((uint32_t)8000000)

Define Documentation

#define __STM32F10X_STDPERIPH_VERSION
Value:
( (__STM32F10X_STDPERIPH_VERSION_MAIN << 24)\
                                             |(__STM32F10X_STDPERIPH_VERSION_SUB1 << 16)\
                                             |(__STM32F10X_STDPERIPH_VERSION_SUB2 << 8)\
                                             |(__STM32F10X_STDPERIPH_VERSION_RC))

Definition at line 139 of file stm32f10x.h.

#define __STM32F10X_STDPERIPH_VERSION_MAIN (0x03)

STM32F10x Standard Peripheral Library version number.

[31:24] main version

Definition at line 135 of file stm32f10x.h.

#define __STM32F10X_STDPERIPH_VERSION_RC (0x00)

[7:0] release candidate

Definition at line 138 of file stm32f10x.h.

#define __STM32F10X_STDPERIPH_VERSION_SUB1 (0x05)

[23:16] sub1 version

Definition at line 136 of file stm32f10x.h.

#define __STM32F10X_STDPERIPH_VERSION_SUB2 (0x00)

[15:8] sub2 version

Definition at line 137 of file stm32f10x.h.

#define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500)

In the following line adjust the External High Speed oscillator (HSE) Startup Timeout value.

Time out for HSE start up

Definition at line 128 of file stm32f10x.h.

Referenced by RCC_WaitForHSEStartUp(), SetSysClockTo56(), and SetSysClockTo72().

#define HSE_VALUE ((uint32_t)8000000)

Comment the line below if you will not use the peripherals drivers.

< STM32F10X_LD: STM32 Low density devices

< STM32F10X_LD_VL: STM32 Low density Value Line devices

< STM32F10X_MD: STM32 Medium density devices

< STM32F10X_MD_VL: STM32 Medium density Value Line devices

< STM32F10X_HD: STM32 High density devices

< STM32F10X_HD_VL: STM32 High density value line devices

< STM32F10X_XL: STM32 XL-density devices

< STM32F10X_CL: STM32 Connectivity line devices In this case, these drivers will not be included and the application code will be based on direct access to peripherals registers In the following line adjust the value of External High Speed oscillator (HSE) used in your application

Tip: To avoid modifying this file each time you need to use different HSE, you can define the HSE value in your toolchain compiler preprocessor. Value of the External oscillator in Hz

Definition at line 119 of file stm32f10x.h.

Referenced by RCC_GetClocksFreq(), and SystemCoreClockUpdate().

#define HSI_VALUE ((uint32_t)8000000)

Value of the Internal oscillator in Hz

Definition at line 130 of file stm32f10x.h.

Referenced by RCC_GetClocksFreq(), and SystemCoreClockUpdate().


STM32F10x Standard Peripherals Firmware Library: Configuration_section_for_CMSIS

Defines | Typedefs | Enumerations

Configuration_section_for_CMSIS

Stm32f10x

Defines

#define | __MPU_PRESENT 0
Configuration of the Cortex-M3 Processor and Core Peripherals.
#define | __NVIC_PRIO_BITS 4
#define | __Vendor_SysTickConfig 0

Typedefs

typedef enum IRQn | IRQn_Type
STM32F10x Interrupt Number Definition, according to the selected device in Library_configuration_section.

Enumerations

enum IRQn {
NonMaskableInt_IRQn = -14, MemoryManagement_IRQn = -12, BusFault_IRQn = -11, UsageFault_IRQn = -10,
SVCall_IRQn = -5, DebugMonitor_IRQn = -4, PendSV_IRQn = -2, SysTick_IRQn = -1,
WWDG_IRQn = 0, PVD_IRQn = 1, TAMPER_IRQn = 2, RTC_IRQn = 3,
FLASH_IRQn = 4, RCC_IRQn = 5, EXTI0_IRQn = 6, EXTI1_IRQn = 7,
EXTI2_IRQn = 8, EXTI3_IRQn = 9, EXTI4_IRQn = 10, DMA1_Channel1_IRQn = 11,
DMA1_Channel2_IRQn = 12, DMA1_Channel3_IRQn = 13, DMA1_Channel4_IRQn = 14, DMA1_Channel5_IRQn = 15,
DMA1_Channel6_IRQn = 16, DMA1_Channel7_IRQn = 17
}

STM32F10x Interrupt Number Definition, according to the selected device in Library_configuration_section.

More...

Define Documentation

#define __MPU_PRESENT 0

Configuration of the Cortex-M3 Processor and Core Peripherals.

Other STM32 devices does not provide an MPU

Definition at line 158 of file stm32f10x.h.

#define __NVIC_PRIO_BITS 4

STM32 uses 4 Bits for the Priority Levels

Definition at line 160 of file stm32f10x.h.

#define __Vendor_SysTickConfig 0

Set to 1 if different SysTick Config is used

Definition at line 161 of file stm32f10x.h.

Typedef Documentation

typedef enum IRQn IRQn_Type

STM32F10x Interrupt Number Definition, according to the selected device in Library_configuration_section.

Enumeration Type Documentation

enum IRQn

STM32F10x Interrupt Number Definition, according to the selected device in Library_configuration_section.

Enumerator:
NonMaskableInt_IRQn

2 Non Maskable Interrupt

MemoryManagement_IRQn

4 Cortex-M3 Memory Management Interrupt

BusFault_IRQn

5 Cortex-M3 Bus Fault Interrupt

UsageFault_IRQn

6 Cortex-M3 Usage Fault Interrupt

SVCall_IRQn

11 Cortex-M3 SV Call Interrupt

DebugMonitor_IRQn

12 Cortex-M3 Debug Monitor Interrupt

PendSV_IRQn

14 Cortex-M3 Pend SV Interrupt

SysTick_IRQn

15 Cortex-M3 System Tick Interrupt

WWDG_IRQn

Window WatchDog Interrupt

PVD_IRQn

PVD through EXTI Line detection Interrupt

TAMPER_IRQn

Tamper Interrupt

RTC_IRQn

RTC global Interrupt

FLASH_IRQn

FLASH global Interrupt

RCC_IRQn

RCC global Interrupt

EXTI0_IRQn

EXTI Line0 Interrupt

EXTI1_IRQn

EXTI Line1 Interrupt

EXTI2_IRQn

EXTI Line2 Interrupt

EXTI3_IRQn

EXTI Line3 Interrupt

EXTI4_IRQn

EXTI Line4 Interrupt

DMA1_Channel1_IRQn

DMA1 Channel 1 global Interrupt

DMA1_Channel2_IRQn

DMA1 Channel 2 global Interrupt

DMA1_Channel3_IRQn

DMA1 Channel 3 global Interrupt

DMA1_Channel4_IRQn

DMA1 Channel 4 global Interrupt

DMA1_Channel5_IRQn

DMA1 Channel 5 global Interrupt

DMA1_Channel6_IRQn

DMA1 Channel 6 global Interrupt

DMA1_Channel7_IRQn

DMA1 Channel 7 global Interrupt

Definition at line 167 of file stm32f10x.h.


STM32F10x Standard Peripherals Firmware Library: Exported_types

Defines | Typedefs | Enumerations

Exported_types

Stm32f10x

Defines

#define | HSE_Value HSE_VALUE
#define | HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT
#define | HSI_Value HSI_VALUE
#define | IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))

Typedefs

typedef enum FlagStatus | ITStatus
typedef int16_t | s16
typedef int32_t | s32
typedef int8_t | s8
typedef const int16_t | sc16
typedef const int32_t | sc32
typedef const int8_t | sc8
typedef uint16_t | u16
typedef uint32_t | u32
typedef uint8_t | u8
typedef const uint16_t | uc16
typedef const uint32_t | uc32
typedef const uint8_t | uc8
typedef __IO int16_t | vs16
typedef __IO int32_t | vs32
typedef __IO int8_t | vs8
typedef __I int16_t | vsc16
typedef __I int32_t | vsc32
typedef __I int8_t | vsc8
typedef __IO uint16_t | vu16
typedef __IO uint32_t | vu32
typedef __IO uint8_t | vu8
typedef __I uint16_t | vuc16
typedef __I uint32_t | vuc32
typedef __I uint8_t | vuc8

Enumerations

enum | ErrorStatus { ERROR = 0, SUCCESS = !ERROR }
enum | FlagStatus { RESET = 0, SET = !RESET }
enum | FunctionalState { DISABLE = 0, ENABLE = !DISABLE }

Define Documentation

#define HSE_Value HSE_VALUE

Definition at line 528 of file stm32f10x.h.

Referenced by I2S_Init(), and SetSysClockToHSE().

#define HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT

Definition at line 527 of file stm32f10x.h.

#define HSI_Value HSI_VALUE

Definition at line 529 of file stm32f10x.h.

#define IS_FUNCTIONAL_STATE ( STATE ) (((STATE) == DISABLE) || ((STATE) == ENABLE))

Definition at line 522 of file stm32f10x.h.

Referenced by ADC_AutoInjectedConvCmd(), ADC_Cmd(), ADC_DiscModeCmd(), ADC_DMACmd(), ADC_ExternalTrigConvCmd(), ADC_ExternalTrigInjectedConvCmd(), ADC_Init(), ADC_InjectedDiscModeCmd(), ADC_ITConfig(), ADC_SoftwareStartConvCmd(), ADC_SoftwareStartInjectedConvCmd(), ADC_TempSensorVrefintCmd(), BKP_ITConfig(), BKP_TamperPinCmd(), CAN_DBGFreeze(), CAN_FilterInit(), CAN_Init(), CAN_ITConfig(), CAN_TTComModeCmd(), CEC_Cmd(), CEC_EndOfMessageCmd(), CEC_ITConfig(), DAC_Cmd(), DAC_DMACmd(), DAC_DualSoftwareTriggerCmd(), DAC_SoftwareTriggerCmd(), DAC_WaveGenerationCmd(), DBGMCU_Config(), DMA_Cmd(), DMA_ITConfig(), EXTI_Init(), FLASH_ITConfig(), FLASH_ReadOutProtection(), FSMC_ITConfig(), FSMC_NANDCmd(), FSMC_NANDECCCmd(), FSMC_NORSRAMCmd(), FSMC_PCCARDCmd(), GPIO_EventOutputCmd(), GPIO_PinRemapConfig(), I2C_AcknowledgeConfig(), I2C_ARPCmd(), I2C_CalculatePEC(), I2C_Cmd(), I2C_DMACmd(), I2C_DMALastTransferCmd(), I2C_DualAddressCmd(), I2C_GeneralCallCmd(), I2C_GenerateSTART(), I2C_GenerateSTOP(), I2C_ITConfig(), I2C_SoftwareResetCmd(), I2C_StretchClockCmd(), I2C_TransmitPEC(), I2S_Cmd(), NVIC_Init(), NVIC_SystemLPConfig(), PWR_BackupAccessCmd(), PWR_PVDCmd(), PWR_WakeUpPinCmd(), RCC_AHBPeriphClockCmd(), RCC_APB1PeriphClockCmd(), RCC_APB1PeriphResetCmd(), RCC_APB2PeriphClockCmd(), RCC_APB2PeriphResetCmd(), RCC_BackupResetCmd(), RCC_ClockSecuritySystemCmd(), RCC_HSICmd(), RCC_ITConfig(), RCC_LSICmd(), RCC_PLLCmd(), RCC_RTCCLKCmd(), RTC_ITConfig(), SDIO_CEATAITCmd(), SDIO_ClockCmd(), SDIO_CommandCompletionCmd(), SDIO_DMACmd(), SDIO_ITConfig(), SDIO_SendCEATACmd(), SDIO_SendSDIOSuspendCmd(), SDIO_SetSDIOOperation(), SDIO_StartSDIOReadWait(), SDIO_StopSDIOReadWait(), SPI_CalculateCRC(), SPI_Cmd(), SPI_I2S_DMACmd(), SPI_I2S_ITConfig(), SPI_SSOutputCmd(), TIM_ARRPreloadConfig(), TIM_CCPreloadControl(), TIM_Cmd(), TIM_CtrlPWMOutputs(), TIM_DMACmd(), TIM_ITConfig(), TIM_SelectCCDMA(), TIM_SelectCOM(), TIM_SelectHallSensor(), TIM_UpdateDisableConfig(), USART_Cmd(), USART_DMACmd(), USART_HalfDuplexCmd(), USART_IrDACmd(), USART_ITConfig(), USART_LINCmd(), USART_OneBitMethodCmd(), USART_OverSampling8Cmd(), USART_ReceiverWakeUpCmd(), USART_SmartCardCmd(), and USART_SmartCardNACKCmd().

Typedef Documentation

typedef enum FlagStatus ITStatus
typedef int16_t s16

Definition at line 488 of file stm32f10x.h.

typedef int32_t s32

< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose)

Definition at line 487 of file stm32f10x.h.

typedef int8_t s8

Definition at line 489 of file stm32f10x.h.

typedef const int16_t sc16

Read Only

Definition at line 492 of file stm32f10x.h.

typedef const int32_t sc32

Read Only

Definition at line 491 of file stm32f10x.h.

typedef const int8_t sc8

Read Only

Definition at line 493 of file stm32f10x.h.

typedef uint16_t u16

Definition at line 504 of file stm32f10x.h.

typedef uint32_t u32

Definition at line 503 of file stm32f10x.h.

typedef uint8_t u8

Definition at line 505 of file stm32f10x.h.

typedef const uint16_t uc16

Read Only

Definition at line 508 of file stm32f10x.h.

typedef const uint32_t uc32

Read Only

Definition at line 507 of file stm32f10x.h.

typedef const uint8_t uc8

Read Only

Definition at line 509 of file stm32f10x.h.

typedef __IO int16_t vs16

Definition at line 496 of file stm32f10x.h.

typedef __IO int32_t vs32

Definition at line 495 of file stm32f10x.h.

typedef __IO int8_t vs8

Definition at line 497 of file stm32f10x.h.

typedef __I int16_t vsc16

Read Only

Definition at line 500 of file stm32f10x.h.

typedef __I int32_t vsc32

Read Only

Definition at line 499 of file stm32f10x.h.

typedef __I int8_t vsc8

Read Only

Definition at line 501 of file stm32f10x.h.

typedef __IO uint16_t vu16

Definition at line 512 of file stm32f10x.h.

typedef __IO uint32_t vu32

Definition at line 511 of file stm32f10x.h.

typedef __IO uint8_t vu8

Definition at line 513 of file stm32f10x.h.

typedef __I uint16_t vuc16

Read Only

Definition at line 516 of file stm32f10x.h.

typedef __I uint32_t vuc32

Read Only

Definition at line 515 of file stm32f10x.h.

typedef __I uint8_t vuc8

Read Only

Definition at line 517 of file stm32f10x.h.

Enumeration Type Documentation

enum ErrorStatus
Enumerator:
ERROR
SUCCESS

Definition at line 524 of file stm32f10x.h.

enum FlagStatus
Enumerator:
RESET
SET

Definition at line 519 of file stm32f10x.h.

enum FunctionalState
Enumerator:
DISABLE
ENABLE

Definition at line 521 of file stm32f10x.h.


STM32F10x Standard Peripherals Firmware Library: ADC_TypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

ADC_TypeDef Struct Reference
Peripheral_registers_structures

Analog to Digital Converter. More...

#include <stm32f10x.h>

Data Fields

__IO uint32_t | CR1
__IO uint32_t | CR2
__IO uint32_t | DR
__IO uint32_t | HTR
__IO uint32_t | JDR1
__IO uint32_t | JDR2
__IO uint32_t | JDR3
__IO uint32_t | JDR4
__IO uint32_t | JOFR1
__IO uint32_t | JOFR2
__IO uint32_t | JOFR3
__IO uint32_t | JOFR4
__IO uint32_t | JSQR
__IO uint32_t | LTR
__IO uint32_t | SMPR1
__IO uint32_t | SMPR2
__IO uint32_t | SQR1
__IO uint32_t | SQR2
__IO uint32_t | SQR3
__IO uint32_t | SR

Detailed Description

Analog to Digital Converter.

Definition at line 542 of file stm32f10x.h.

Field Documentation

__IO uint32_t ADC_TypeDef::CR1

Definition at line 545 of file stm32f10x.h.

Referenced by ADC_AnalogWatchdogCmd(), ADC_AnalogWatchdogSingleChannelConfig(), ADC_AutoInjectedConvCmd(), ADC_DiscModeChannelCountConfig(), ADC_DiscModeCmd(), ADC_GetITStatus(), ADC_Init(), ADC_InjectedDiscModeCmd(), and ADC_ITConfig().

__IO uint32_t ADC_TypeDef::CR2

Definition at line 546 of file stm32f10x.h.

Referenced by ADC_Cmd(), ADC_DMACmd(), ADC_ExternalTrigConvCmd(), ADC_ExternalTrigInjectedConvCmd(), ADC_ExternalTrigInjectedConvConfig(), ADC_GetCalibrationStatus(), ADC_GetResetCalibrationStatus(), ADC_GetSoftwareStartConvStatus(), ADC_GetSoftwareStartInjectedConvCmdStatus(), ADC_Init(), ADC_ResetCalibration(), ADC_SoftwareStartConvCmd(), ADC_SoftwareStartInjectedConvCmd(), and ADC_StartCalibration().

__IO uint32_t ADC_TypeDef::DR

Definition at line 563 of file stm32f10x.h.

Referenced by ADC_GetConversionValue().

__IO uint32_t ADC_TypeDef::HTR

Definition at line 553 of file stm32f10x.h.

Referenced by ADC_AnalogWatchdogThresholdsConfig().

__IO uint32_t ADC_TypeDef::JDR1

Definition at line 559 of file stm32f10x.h.

__IO uint32_t ADC_TypeDef::JDR2

Definition at line 560 of file stm32f10x.h.

__IO uint32_t ADC_TypeDef::JDR3

Definition at line 561 of file stm32f10x.h.

__IO uint32_t ADC_TypeDef::JDR4

Definition at line 562 of file stm32f10x.h.

__IO uint32_t ADC_TypeDef::JOFR1

Definition at line 549 of file stm32f10x.h.

__IO uint32_t ADC_TypeDef::JOFR2

Definition at line 550 of file stm32f10x.h.

__IO uint32_t ADC_TypeDef::JOFR3

Definition at line 551 of file stm32f10x.h.

__IO uint32_t ADC_TypeDef::JOFR4

Definition at line 552 of file stm32f10x.h.

__IO uint32_t ADC_TypeDef::JSQR

Definition at line 558 of file stm32f10x.h.

Referenced by ADC_InjectedChannelConfig(), and ADC_InjectedSequencerLengthConfig().

__IO uint32_t ADC_TypeDef::LTR

Definition at line 554 of file stm32f10x.h.

Referenced by ADC_AnalogWatchdogThresholdsConfig().

__IO uint32_t ADC_TypeDef::SMPR1

Definition at line 547 of file stm32f10x.h.

Referenced by ADC_InjectedChannelConfig(), and ADC_RegularChannelConfig().

__IO uint32_t ADC_TypeDef::SMPR2

Definition at line 548 of file stm32f10x.h.

Referenced by ADC_InjectedChannelConfig(), and ADC_RegularChannelConfig().

__IO uint32_t ADC_TypeDef::SQR1

Definition at line 555 of file stm32f10x.h.

Referenced by ADC_Init(), and ADC_RegularChannelConfig().

__IO uint32_t ADC_TypeDef::SQR2

Definition at line 556 of file stm32f10x.h.

Referenced by ADC_RegularChannelConfig().

__IO uint32_t ADC_TypeDef::SQR3

Definition at line 557 of file stm32f10x.h.

Referenced by ADC_RegularChannelConfig().

__IO uint32_t ADC_TypeDef::SR

Definition at line 544 of file stm32f10x.h.

Referenced by ADC_ClearFlag(), ADC_ClearITPendingBit(), ADC_GetFlagStatus(), and ADC_GetITStatus().

The documentation for this struct was generated from the following file:
  • stm32f10x.h


STM32F10x Standard Peripherals Firmware Library: AFIO_TypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

AFIO_TypeDef Struct Reference
Peripheral_registers_structures

Alternate Function I/O. More...

#include <stm32f10x.h>

Data Fields

__IO uint32_t | EVCR
__IO uint32_t | EXTICR [4]
__IO uint32_t | MAPR
__IO uint32_t | MAPR2
uint32_t | RESERVED0

Detailed Description

Alternate Function I/O.

Definition at line 1016 of file stm32f10x.h.

Field Documentation

__IO uint32_t AFIO_TypeDef::EVCR

Definition at line 1018 of file stm32f10x.h.

__IO uint32_t AFIO_TypeDef::EXTICR[4]

Definition at line 1020 of file stm32f10x.h.

__IO uint32_t AFIO_TypeDef::MAPR

Definition at line 1019 of file stm32f10x.h.

__IO uint32_t AFIO_TypeDef::MAPR2

Definition at line 1022 of file stm32f10x.h.

uint32_t AFIO_TypeDef::RESERVED0

Definition at line 1021 of file stm32f10x.h.

The documentation for this struct was generated from the following file:
  • stm32f10x.h


STM32F10x Standard Peripherals Firmware Library: BKP_TypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

BKP_TypeDef Struct Reference
Peripheral_registers_structures

Backup Registers. More...

#include <stm32f10x.h>

Data Fields

__IO uint16_t | CR
__IO uint16_t | CSR
__IO uint16_t | DR1
__IO uint16_t | DR10
__IO uint16_t | DR11
__IO uint16_t | DR12
__IO uint16_t | DR13
__IO uint16_t | DR14
__IO uint16_t | DR15
__IO uint16_t | DR16
__IO uint16_t | DR17
__IO uint16_t | DR18
__IO uint16_t | DR19
__IO uint16_t | DR2
__IO uint16_t | DR20
__IO uint16_t | DR21
__IO uint16_t | DR22
__IO uint16_t | DR23
__IO uint16_t | DR24
__IO uint16_t | DR25
__IO uint16_t | DR26
__IO uint16_t | DR27
__IO uint16_t | DR28
__IO uint16_t | DR29
__IO uint16_t | DR3
__IO uint16_t | DR30
__IO uint16_t | DR31
__IO uint16_t | DR32
__IO uint16_t | DR33
__IO uint16_t | DR34
__IO uint16_t | DR35
__IO uint16_t | DR36
__IO uint16_t | DR37
__IO uint16_t | DR38
__IO uint16_t | DR39
__IO uint16_t | DR4
__IO uint16_t | DR40
__IO uint16_t | DR41
__IO uint16_t | DR42
__IO uint16_t | DR5
__IO uint16_t | DR6
__IO uint16_t | DR7
__IO uint16_t | DR8
__IO uint16_t | DR9
uint32_t | RESERVED0
uint16_t | RESERVED1
uint16_t | RESERVED10
uint16_t | RESERVED11
uint16_t | RESERVED12
uint16_t | RESERVED13 [5]
uint16_t | RESERVED14
uint16_t | RESERVED15
uint16_t | RESERVED16
uint16_t | RESERVED17
uint16_t | RESERVED18
uint16_t | RESERVED19
uint16_t | RESERVED2
uint16_t | RESERVED20
uint16_t | RESERVED21
uint16_t | RESERVED22
uint16_t | RESERVED23
uint16_t | RESERVED24
uint16_t | RESERVED25
uint16_t | RESERVED26
uint16_t | RESERVED27
uint16_t | RESERVED28
uint16_t | RESERVED29
uint16_t | RESERVED3
uint16_t | RESERVED30
uint16_t | RESERVED31
uint16_t | RESERVED32
uint16_t | RESERVED33
uint16_t | RESERVED34
uint16_t | RESERVED35
uint16_t | RESERVED36
uint16_t | RESERVED37
uint16_t | RESERVED38
uint16_t | RESERVED39
uint16_t | RESERVED4
uint16_t | RESERVED40
uint16_t | RESERVED41
uint16_t | RESERVED42
uint16_t | RESERVED43
uint16_t | RESERVED44
uint16_t | RESERVED45
uint16_t | RESERVED5
uint16_t | RESERVED6
uint16_t | RESERVED7
uint16_t | RESERVED8
uint16_t | RESERVED9
__IO uint16_t | RTCCR

Detailed Description

Backup Registers.

Definition at line 570 of file stm32f10x.h.

Field Documentation

__IO uint16_t BKP_TypeDef::CR

Definition at line 595 of file stm32f10x.h.

__IO uint16_t BKP_TypeDef::CSR

Definition at line 597 of file stm32f10x.h.

__IO uint16_t BKP_TypeDef::DR1

Definition at line 573 of file stm32f10x.h.

__IO uint16_t BKP_TypeDef::DR10

Definition at line 591 of file stm32f10x.h.

__IO uint16_t BKP_TypeDef::DR11

Definition at line 599 of file stm32f10x.h.

__IO uint16_t BKP_TypeDef::DR12

Definition at line 601 of file stm32f10x.h.

__IO uint16_t BKP_TypeDef::DR13

Definition at line 603 of file stm32f10x.h.

__IO uint16_t BKP_TypeDef::DR14

Definition at line 605 of file stm32f10x.h.

__IO uint16_t BKP_TypeDef::DR15

Definition at line 607 of file stm32f10x.h.

__IO uint16_t BKP_TypeDef::DR16

Definition at line 609 of file stm32f10x.h.

__IO uint16_t BKP_TypeDef::DR17

Definition at line 611 of file stm32f10x.h.

__IO uint16_t BKP_TypeDef::DR18

Definition at line 613 of file stm32f10x.h.

__IO uint16_t BKP_TypeDef::DR19

Definition at line 615 of file stm32f10x.h.

__IO uint16_t BKP_TypeDef::DR2

Definition at line 575 of file stm32f10x.h.

__IO uint16_t BKP_TypeDef::DR20

Definition at line 617 of file stm32f10x.h.

__IO uint16_t BKP_TypeDef::DR21

Definition at line 619 of file stm32f10x.h.

__IO uint16_t BKP_TypeDef::DR22

Definition at line 621 of file stm32f10x.h.

__IO uint16_t BKP_TypeDef::DR23

Definition at line 623 of file stm32f10x.h.

__IO uint16_t BKP_TypeDef::DR24

Definition at line 625 of file stm32f10x.h.

__IO uint16_t BKP_TypeDef::DR25

Definition at line 627 of file stm32f10x.h.

__IO uint16_t BKP_TypeDef::DR26

Definition at line 629 of file stm32f10x.h.

__IO uint16_t BKP_TypeDef::DR27

Definition at line 631 of file stm32f10x.h.

__IO uint16_t BKP_TypeDef::DR28

Definition at line 633 of file stm32f10x.h.

__IO uint16_t BKP_TypeDef::DR29

Definition at line 635 of file stm32f10x.h.

__IO uint16_t BKP_TypeDef::DR3

Definition at line 577 of file stm32f10x.h.

__IO uint16_t BKP_TypeDef::DR30

Definition at line 637 of file stm32f10x.h.

__IO uint16_t BKP_TypeDef::DR31

Definition at line 639 of file stm32f10x.h.

__IO uint16_t BKP_TypeDef::DR32

Definition at line 641 of file stm32f10x.h.

__IO uint16_t BKP_TypeDef::DR33

Definition at line 643 of file stm32f10x.h.

__IO uint16_t BKP_TypeDef::DR34

Definition at line 645 of file stm32f10x.h.

__IO uint16_t BKP_TypeDef::DR35

Definition at line 647 of file stm32f10x.h.

__IO uint16_t BKP_TypeDef::DR36

Definition at line 649 of file stm32f10x.h.

__IO uint16_t BKP_TypeDef::DR37

Definition at line 651 of file stm32f10x.h.

__IO uint16_t BKP_TypeDef::DR38

Definition at line 653 of file stm32f10x.h.

__IO uint16_t BKP_TypeDef::DR39

Definition at line 655 of file stm32f10x.h.

__IO uint16_t BKP_TypeDef::DR4

Definition at line 579 of file stm32f10x.h.

__IO uint16_t BKP_TypeDef::DR40

Definition at line 657 of file stm32f10x.h.

__IO uint16_t BKP_TypeDef::DR41

Definition at line 659 of file stm32f10x.h.

__IO uint16_t BKP_TypeDef::DR42

Definition at line 661 of file stm32f10x.h.

__IO uint16_t BKP_TypeDef::DR5

Definition at line 581 of file stm32f10x.h.

__IO uint16_t BKP_TypeDef::DR6

Definition at line 583 of file stm32f10x.h.

__IO uint16_t BKP_TypeDef::DR7

Definition at line 585 of file stm32f10x.h.

__IO uint16_t BKP_TypeDef::DR8

Definition at line 587 of file stm32f10x.h.

__IO uint16_t BKP_TypeDef::DR9

Definition at line 589 of file stm32f10x.h.

uint32_t BKP_TypeDef::RESERVED0

Definition at line 572 of file stm32f10x.h.

uint16_t BKP_TypeDef::RESERVED1

Definition at line 574 of file stm32f10x.h.

uint16_t BKP_TypeDef::RESERVED10

Definition at line 592 of file stm32f10x.h.

uint16_t BKP_TypeDef::RESERVED11

Definition at line 594 of file stm32f10x.h.

uint16_t BKP_TypeDef::RESERVED12

Definition at line 596 of file stm32f10x.h.

uint16_t BKP_TypeDef::RESERVED13[5]

Definition at line 598 of file stm32f10x.h.

uint16_t BKP_TypeDef::RESERVED14

Definition at line 600 of file stm32f10x.h.

uint16_t BKP_TypeDef::RESERVED15

Definition at line 602 of file stm32f10x.h.

uint16_t BKP_TypeDef::RESERVED16

Definition at line 604 of file stm32f10x.h.

uint16_t BKP_TypeDef::RESERVED17

Definition at line 606 of file stm32f10x.h.

uint16_t BKP_TypeDef::RESERVED18

Definition at line 608 of file stm32f10x.h.

uint16_t BKP_TypeDef::RESERVED19

Definition at line 610 of file stm32f10x.h.

uint16_t BKP_TypeDef::RESERVED2

Definition at line 576 of file stm32f10x.h.

uint16_t BKP_TypeDef::RESERVED20

Definition at line 612 of file stm32f10x.h.

uint16_t BKP_TypeDef::RESERVED21

Definition at line 614 of file stm32f10x.h.

uint16_t BKP_TypeDef::RESERVED22

Definition at line 616 of file stm32f10x.h.

uint16_t BKP_TypeDef::RESERVED23

Definition at line 618 of file stm32f10x.h.

uint16_t BKP_TypeDef::RESERVED24

Definition at line 620 of file stm32f10x.h.

uint16_t BKP_TypeDef::RESERVED25

Definition at line 622 of file stm32f10x.h.

uint16_t BKP_TypeDef::RESERVED26

Definition at line 624 of file stm32f10x.h.

uint16_t BKP_TypeDef::RESERVED27

Definition at line 626 of file stm32f10x.h.

uint16_t BKP_TypeDef::RESERVED28

Definition at line 628 of file stm32f10x.h.

uint16_t BKP_TypeDef::RESERVED29

Definition at line 630 of file stm32f10x.h.

uint16_t BKP_TypeDef::RESERVED3

Definition at line 578 of file stm32f10x.h.

uint16_t BKP_TypeDef::RESERVED30

Definition at line 632 of file stm32f10x.h.

uint16_t BKP_TypeDef::RESERVED31

Definition at line 634 of file stm32f10x.h.

uint16_t BKP_TypeDef::RESERVED32

Definition at line 636 of file stm32f10x.h.

uint16_t BKP_TypeDef::RESERVED33

Definition at line 638 of file stm32f10x.h.

uint16_t BKP_TypeDef::RESERVED34

Definition at line 640 of file stm32f10x.h.

uint16_t BKP_TypeDef::RESERVED35

Definition at line 642 of file stm32f10x.h.

uint16_t BKP_TypeDef::RESERVED36

Definition at line 644 of file stm32f10x.h.

uint16_t BKP_TypeDef::RESERVED37

Definition at line 646 of file stm32f10x.h.

uint16_t BKP_TypeDef::RESERVED38

Definition at line 648 of file stm32f10x.h.

uint16_t BKP_TypeDef::RESERVED39

Definition at line 650 of file stm32f10x.h.

uint16_t BKP_TypeDef::RESERVED4

Definition at line 580 of file stm32f10x.h.

uint16_t BKP_TypeDef::RESERVED40

Definition at line 652 of file stm32f10x.h.

uint16_t BKP_TypeDef::RESERVED41

Definition at line 654 of file stm32f10x.h.

uint16_t BKP_TypeDef::RESERVED42

Definition at line 656 of file stm32f10x.h.

uint16_t BKP_TypeDef::RESERVED43

Definition at line 658 of file stm32f10x.h.

uint16_t BKP_TypeDef::RESERVED44

Definition at line 660 of file stm32f10x.h.

uint16_t BKP_TypeDef::RESERVED45

Definition at line 662 of file stm32f10x.h.

uint16_t BKP_TypeDef::RESERVED5

Definition at line 582 of file stm32f10x.h.

uint16_t BKP_TypeDef::RESERVED6

Definition at line 584 of file stm32f10x.h.

uint16_t BKP_TypeDef::RESERVED7

Definition at line 586 of file stm32f10x.h.

uint16_t BKP_TypeDef::RESERVED8

Definition at line 588 of file stm32f10x.h.

uint16_t BKP_TypeDef::RESERVED9

Definition at line 590 of file stm32f10x.h.

__IO uint16_t BKP_TypeDef::RTCCR

Definition at line 593 of file stm32f10x.h.

The documentation for this struct was generated from the following file:
  • stm32f10x.h


STM32F10x Standard Peripherals Firmware Library: CAN_FIFOMailBox_TypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

CAN_FIFOMailBox_TypeDef Struct Reference
Peripheral_registers_structures

Controller Area Network FIFOMailBox. More...

#include <stm32f10x.h>

Data Fields

__IO uint32_t | RDHR
__IO uint32_t | RDLR
__IO uint32_t | RDTR
__IO uint32_t | RIR

Detailed Description

Controller Area Network FIFOMailBox.

Definition at line 681 of file stm32f10x.h.

Field Documentation

__IO uint32_t CAN_FIFOMailBox_TypeDef::RDHR

Definition at line 686 of file stm32f10x.h.

Referenced by CAN_Receive().

__IO uint32_t CAN_FIFOMailBox_TypeDef::RDLR

Definition at line 685 of file stm32f10x.h.

Referenced by CAN_Receive().

__IO uint32_t CAN_FIFOMailBox_TypeDef::RDTR

Definition at line 684 of file stm32f10x.h.

Referenced by CAN_Receive().

__IO uint32_t CAN_FIFOMailBox_TypeDef::RIR

Definition at line 683 of file stm32f10x.h.

Referenced by CAN_Receive().

The documentation for this struct was generated from the following file:
  • stm32f10x.h


STM32F10x Standard Peripherals Firmware Library: CAN_FilterRegister_TypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

CAN_FilterRegister_TypeDef Struct Reference
Peripheral_registers_structures

Controller Area Network FilterRegister. More...

#include <stm32f10x.h>

Data Fields

__IO uint32_t | FR1
__IO uint32_t | FR2

Detailed Description

Controller Area Network FilterRegister.

Definition at line 693 of file stm32f10x.h.

Field Documentation

__IO uint32_t CAN_FilterRegister_TypeDef::FR1

Definition at line 695 of file stm32f10x.h.

__IO uint32_t CAN_FilterRegister_TypeDef::FR2

Definition at line 696 of file stm32f10x.h.

The documentation for this struct was generated from the following file:
  • stm32f10x.h


STM32F10x Standard Peripherals Firmware Library: CAN_TxMailBox_TypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

CAN_TxMailBox_TypeDef Struct Reference
Peripheral_registers_structures

Controller Area Network TxMailBox. More...

#include <stm32f10x.h>

Data Fields

__IO uint32_t | TDHR
__IO uint32_t | TDLR
__IO uint32_t | TDTR
__IO uint32_t | TIR

Detailed Description

Controller Area Network TxMailBox.

Definition at line 669 of file stm32f10x.h.

Field Documentation

__IO uint32_t CAN_TxMailBox_TypeDef::TDHR

Definition at line 674 of file stm32f10x.h.

Referenced by CAN_Transmit().

__IO uint32_t CAN_TxMailBox_TypeDef::TDLR

Definition at line 673 of file stm32f10x.h.

Referenced by CAN_Transmit().

__IO uint32_t CAN_TxMailBox_TypeDef::TDTR

Definition at line 672 of file stm32f10x.h.

Referenced by CAN_Transmit(), and CAN_TTComModeCmd().

__IO uint32_t CAN_TxMailBox_TypeDef::TIR

Definition at line 671 of file stm32f10x.h.

Referenced by CAN_Transmit().

The documentation for this struct was generated from the following file:
  • stm32f10x.h


STM32F10x Standard Peripherals Firmware Library: CAN_TypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

CAN_TypeDef Struct Reference
Peripheral_registers_structures

Controller Area Network. More...

#include <stm32f10x.h>

Data Fields

__IO uint32_t | BTR
__IO uint32_t | ESR
__IO uint32_t | FA1R
__IO uint32_t | FFA1R
__IO uint32_t | FM1R
__IO uint32_t | FMR
__IO uint32_t | FS1R
__IO uint32_t | IER
__IO uint32_t | MCR
__IO uint32_t | MSR
uint32_t | RESERVED0 [88]
uint32_t | RESERVED1 [12]
uint32_t | RESERVED2
uint32_t | RESERVED3
uint32_t | RESERVED4
uint32_t | RESERVED5 [8]
__IO uint32_t | RF0R
__IO uint32_t | RF1R
CAN_FIFOMailBox_TypeDef | sFIFOMailBox [2]
CAN_FilterRegister_TypeDef | sFilterRegister [14]
CAN_TxMailBox_TypeDef | sTxMailBox [3]
__IO uint32_t | TSR

Detailed Description

Controller Area Network.

Definition at line 703 of file stm32f10x.h.

Field Documentation

__IO uint32_t CAN_TypeDef::BTR

Definition at line 712 of file stm32f10x.h.

Referenced by CAN_Init().

__IO uint32_t CAN_TypeDef::ESR

Definition at line 711 of file stm32f10x.h.

Referenced by CAN_ClearFlag(), CAN_ClearITPendingBit(), CAN_GetFlagStatus(), CAN_GetITStatus(), CAN_GetLastErrorCode(), CAN_GetLSBTransmitErrorCounter(), and CAN_GetReceiveErrorCounter().

__IO uint32_t CAN_TypeDef::FA1R

Definition at line 724 of file stm32f10x.h.

__IO uint32_t CAN_TypeDef::FFA1R

Definition at line 722 of file stm32f10x.h.

__IO uint32_t CAN_TypeDef::FM1R

Definition at line 718 of file stm32f10x.h.

__IO uint32_t CAN_TypeDef::FMR

Definition at line 717 of file stm32f10x.h.

__IO uint32_t CAN_TypeDef::FS1R

Definition at line 720 of file stm32f10x.h.

__IO uint32_t CAN_TypeDef::IER

Definition at line 710 of file stm32f10x.h.

Referenced by CAN_GetITStatus(), and CAN_ITConfig().

__IO uint32_t CAN_TypeDef::MCR

Definition at line 705 of file stm32f10x.h.

Referenced by CAN_DBGFreeze(), CAN_Init(), CAN_OperatingModeRequest(), CAN_Sleep(), CAN_TTComModeCmd(), and CAN_WakeUp().

__IO uint32_t CAN_TypeDef::MSR

Definition at line 706 of file stm32f10x.h.

Referenced by CAN_ClearFlag(), CAN_ClearITPendingBit(), CAN_GetFlagStatus(), CAN_GetITStatus(), CAN_Init(), CAN_OperatingModeRequest(), CAN_Sleep(), and CAN_WakeUp().

uint32_t CAN_TypeDef::RESERVED0[88]

Definition at line 713 of file stm32f10x.h.

uint32_t CAN_TypeDef::RESERVED1[12]

Definition at line 716 of file stm32f10x.h.

uint32_t CAN_TypeDef::RESERVED2

Definition at line 719 of file stm32f10x.h.

uint32_t CAN_TypeDef::RESERVED3

Definition at line 721 of file stm32f10x.h.

uint32_t CAN_TypeDef::RESERVED4

Definition at line 723 of file stm32f10x.h.

uint32_t CAN_TypeDef::RESERVED5[8]

Definition at line 725 of file stm32f10x.h.

__IO uint32_t CAN_TypeDef::RF0R

Definition at line 708 of file stm32f10x.h.

Referenced by CAN_ClearFlag(), CAN_ClearITPendingBit(), CAN_FIFORelease(), CAN_GetFlagStatus(), CAN_GetITStatus(), CAN_MessagePending(), and CAN_Receive().

__IO uint32_t CAN_TypeDef::RF1R

Definition at line 709 of file stm32f10x.h.

Referenced by CAN_ClearFlag(), CAN_ClearITPendingBit(), CAN_FIFORelease(), CAN_GetFlagStatus(), CAN_GetITStatus(), CAN_MessagePending(), and CAN_Receive().

CAN_FIFOMailBox_TypeDef CAN_TypeDef::sFIFOMailBox[2]

Definition at line 715 of file stm32f10x.h.

Referenced by CAN_Receive().

CAN_FilterRegister_TypeDef CAN_TypeDef::sFilterRegister[14]

Definition at line 727 of file stm32f10x.h.

CAN_TxMailBox_TypeDef CAN_TypeDef::sTxMailBox[3]

Definition at line 714 of file stm32f10x.h.

Referenced by CAN_Transmit(), and CAN_TTComModeCmd().

__IO uint32_t CAN_TypeDef::TSR

Definition at line 707 of file stm32f10x.h.

Referenced by CAN_CancelTransmit(), CAN_ClearFlag(), CAN_ClearITPendingBit(), CAN_GetFlagStatus(), CAN_GetITStatus(), CAN_Transmit(), and CAN_TransmitStatus().

The documentation for this struct was generated from the following file:
  • stm32f10x.h


STM32F10x Standard Peripherals Firmware Library: CEC_TypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

CEC_TypeDef Struct Reference
Peripheral_registers_structures

Consumer Electronics Control (CEC) More...

#include <stm32f10x.h>

Data Fields

__IO uint32_t | CFGR
__IO uint32_t | CSR
__IO uint32_t | ESR
__IO uint32_t | OAR
__IO uint32_t | PRES
__IO uint32_t | RXD
__IO uint32_t | TXD

Detailed Description

Consumer Electronics Control (CEC)

Definition at line 736 of file stm32f10x.h.

Field Documentation

__IO uint32_t CEC_TypeDef::CFGR

Definition at line 738 of file stm32f10x.h.

__IO uint32_t CEC_TypeDef::CSR

Definition at line 742 of file stm32f10x.h.

__IO uint32_t CEC_TypeDef::ESR

Definition at line 741 of file stm32f10x.h.

__IO uint32_t CEC_TypeDef::OAR

Definition at line 739 of file stm32f10x.h.

__IO uint32_t CEC_TypeDef::PRES

Definition at line 740 of file stm32f10x.h.

__IO uint32_t CEC_TypeDef::RXD

Definition at line 744 of file stm32f10x.h.

__IO uint32_t CEC_TypeDef::TXD

Definition at line 743 of file stm32f10x.h.

The documentation for this struct was generated from the following file:
  • stm32f10x.h


STM32F10x Standard Peripherals Firmware Library: CRC_TypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

CRC_TypeDef Struct Reference
Peripheral_registers_structures

CRC calculation unit. More...

#include <stm32f10x.h>

Data Fields

__IO uint32_t | CR
__IO uint32_t | DR
__IO uint8_t | IDR
uint8_t | RESERVED0
uint16_t | RESERVED1

Detailed Description

CRC calculation unit.

Definition at line 751 of file stm32f10x.h.

Field Documentation

__IO uint32_t CRC_TypeDef::CR

Definition at line 757 of file stm32f10x.h.

__IO uint32_t CRC_TypeDef::DR

Definition at line 753 of file stm32f10x.h.

__IO uint8_t CRC_TypeDef::IDR

Definition at line 754 of file stm32f10x.h.

uint8_t CRC_TypeDef::RESERVED0

Definition at line 755 of file stm32f10x.h.

uint16_t CRC_TypeDef::RESERVED1

Definition at line 756 of file stm32f10x.h.

The documentation for this struct was generated from the following file:
  • stm32f10x.h


STM32F10x Standard Peripherals Firmware Library: DAC_TypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

DAC_TypeDef Struct Reference
Peripheral_registers_structures

Digital to Analog Converter. More...

#include <stm32f10x.h>

Data Fields

__IO uint32_t | CR
__IO uint32_t | DHR12L1
__IO uint32_t | DHR12L2
__IO uint32_t | DHR12LD
__IO uint32_t | DHR12R1
__IO uint32_t | DHR12R2
__IO uint32_t | DHR12RD
__IO uint32_t | DHR8R1
__IO uint32_t | DHR8R2
__IO uint32_t | DHR8RD
__IO uint32_t | DOR1
__IO uint32_t | DOR2
__IO uint32_t | SWTRIGR

Detailed Description

Digital to Analog Converter.

Definition at line 764 of file stm32f10x.h.

Field Documentation

__IO uint32_t DAC_TypeDef::CR

Definition at line 766 of file stm32f10x.h.

__IO uint32_t DAC_TypeDef::DHR12L1

Definition at line 769 of file stm32f10x.h.

__IO uint32_t DAC_TypeDef::DHR12L2

Definition at line 772 of file stm32f10x.h.

__IO uint32_t DAC_TypeDef::DHR12LD

Definition at line 775 of file stm32f10x.h.

__IO uint32_t DAC_TypeDef::DHR12R1

Definition at line 768 of file stm32f10x.h.

__IO uint32_t DAC_TypeDef::DHR12R2

Definition at line 771 of file stm32f10x.h.

__IO uint32_t DAC_TypeDef::DHR12RD

Definition at line 774 of file stm32f10x.h.

__IO uint32_t DAC_TypeDef::DHR8R1

Definition at line 770 of file stm32f10x.h.

__IO uint32_t DAC_TypeDef::DHR8R2

Definition at line 773 of file stm32f10x.h.

__IO uint32_t DAC_TypeDef::DHR8RD

Definition at line 776 of file stm32f10x.h.

__IO uint32_t DAC_TypeDef::DOR1

Definition at line 777 of file stm32f10x.h.

__IO uint32_t DAC_TypeDef::DOR2

Definition at line 778 of file stm32f10x.h.

__IO uint32_t DAC_TypeDef::SWTRIGR

Definition at line 767 of file stm32f10x.h.

The documentation for this struct was generated from the following file:
  • stm32f10x.h


STM32F10x Standard Peripherals Firmware Library: DBGMCU_TypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

DBGMCU_TypeDef Struct Reference
Peripheral_registers_structures

Debug MCU. More...

#include <stm32f10x.h>

Data Fields

__IO uint32_t | CR
__IO uint32_t | IDCODE

Detailed Description

Debug MCU.

Definition at line 788 of file stm32f10x.h.

Field Documentation

__IO uint32_t DBGMCU_TypeDef::CR

Definition at line 791 of file stm32f10x.h.

__IO uint32_t DBGMCU_TypeDef::IDCODE

Definition at line 790 of file stm32f10x.h.

The documentation for this struct was generated from the following file:
  • stm32f10x.h


STM32F10x Standard Peripherals Firmware Library: DMA_Channel_TypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

DMA_Channel_TypeDef Struct Reference
Peripheral_registers_structures

DMA Controller. More...

#include <stm32f10x.h>

Data Fields

__IO uint32_t | CCR
__IO uint32_t | CMAR
__IO uint32_t | CNDTR
__IO uint32_t | CPAR

Detailed Description

DMA Controller.

Definition at line 798 of file stm32f10x.h.

Field Documentation

__IO uint32_t DMA_Channel_TypeDef::CCR

Definition at line 800 of file stm32f10x.h.

Referenced by DMA_Cmd(), DMA_DeInit(), DMA_Init(), and DMA_ITConfig().

__IO uint32_t DMA_Channel_TypeDef::CMAR

Definition at line 803 of file stm32f10x.h.

Referenced by DMA_DeInit(), and DMA_Init().

__IO uint32_t DMA_Channel_TypeDef::CNDTR

Definition at line 801 of file stm32f10x.h.

Referenced by DMA_DeInit(), DMA_GetCurrDataCounter(), DMA_Init(), and DMA_SetCurrDataCounter().

__IO uint32_t DMA_Channel_TypeDef::CPAR

Definition at line 802 of file stm32f10x.h.

Referenced by DMA_DeInit(), and DMA_Init().

The documentation for this struct was generated from the following file:
  • stm32f10x.h


STM32F10x Standard Peripherals Firmware Library: DMA_TypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

DMA_TypeDef Struct Reference
Peripheral_registers_structures

#include <stm32f10x.h>

Data Fields

__IO uint32_t | IFCR
__IO uint32_t | ISR

Detailed Description

Definition at line 806 of file stm32f10x.h.

Field Documentation

__IO uint32_t DMA_TypeDef::IFCR

Definition at line 809 of file stm32f10x.h.

__IO uint32_t DMA_TypeDef::ISR

Definition at line 808 of file stm32f10x.h.

The documentation for this struct was generated from the following file:
  • stm32f10x.h


STM32F10x Standard Peripherals Firmware Library: ETH_TypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

ETH_TypeDef Struct Reference
Peripheral_registers_structures

Ethernet MAC. More...

#include <stm32f10x.h>

Data Fields

__IO uint32_t | DMABMR
__IO uint32_t | DMACHRBAR
__IO uint32_t | DMACHRDR
__IO uint32_t | DMACHTBAR
__IO uint32_t | DMACHTDR
__IO uint32_t | DMAIER
__IO uint32_t | DMAMFBOCR
__IO uint32_t | DMAOMR
__IO uint32_t | DMARDLAR
__IO uint32_t | DMARPDR
__IO uint32_t | DMASR
__IO uint32_t | DMATDLAR
__IO uint32_t | DMATPDR
__IO uint32_t | MACA0HR
__IO uint32_t | MACA0LR
__IO uint32_t | MACA1HR
__IO uint32_t | MACA1LR
__IO uint32_t | MACA2HR
__IO uint32_t | MACA2LR
__IO uint32_t | MACA3HR
__IO uint32_t | MACA3LR
__IO uint32_t | MACCR
__IO uint32_t | MACFCR
__IO uint32_t | MACFFR
__IO uint32_t | MACHTHR
__IO uint32_t | MACHTLR
__IO uint32_t | MACIMR
__IO uint32_t | MACMIIAR
__IO uint32_t | MACMIIDR
__IO uint32_t | MACPMTCSR
__IO uint32_t | MACRWUFFR
__IO uint32_t | MACSR
__IO uint32_t | MACVLANTR
__IO uint32_t | MMCCR
__IO uint32_t | MMCRFAECR
__IO uint32_t | MMCRFCECR
__IO uint32_t | MMCRGUFCR
__IO uint32_t | MMCRIMR
__IO uint32_t | MMCRIR
__IO uint32_t | MMCTGFCR
__IO uint32_t | MMCTGFMSCCR
__IO uint32_t | MMCTGFSCCR
__IO uint32_t | MMCTIMR
__IO uint32_t | MMCTIR
__IO uint32_t | PTPSSIR
__IO uint32_t | PTPTSAR
__IO uint32_t | PTPTSCR
__IO uint32_t | PTPTSHR
__IO uint32_t | PTPTSHUR
__IO uint32_t | PTPTSLR
__IO uint32_t | PTPTSLUR
__IO uint32_t | PTPTTHR
__IO uint32_t | PTPTTLR
uint32_t | RESERVED0 [2]
uint32_t | RESERVED1 [2]
uint32_t | RESERVED2 [40]
uint32_t | RESERVED3 [14]
uint32_t | RESERVED4 [5]
uint32_t | RESERVED5 [10]
uint32_t | RESERVED6 [10]
uint32_t | RESERVED7 [334]
uint32_t | RESERVED8 [567]
uint32_t | RESERVED9 [9]

Detailed Description

Ethernet MAC.

Definition at line 816 of file stm32f10x.h.

Field Documentation

__IO uint32_t ETH_TypeDef::DMABMR

Definition at line 867 of file stm32f10x.h.

__IO uint32_t ETH_TypeDef::DMACHRBAR

Definition at line 880 of file stm32f10x.h.

__IO uint32_t ETH_TypeDef::DMACHRDR

Definition at line 878 of file stm32f10x.h.

__IO uint32_t ETH_TypeDef::DMACHTBAR

Definition at line 879 of file stm32f10x.h.

__IO uint32_t ETH_TypeDef::DMACHTDR

Definition at line 877 of file stm32f10x.h.

__IO uint32_t ETH_TypeDef::DMAIER

Definition at line 874 of file stm32f10x.h.

__IO uint32_t ETH_TypeDef::DMAMFBOCR

Definition at line 875 of file stm32f10x.h.

__IO uint32_t ETH_TypeDef::DMAOMR

Definition at line 873 of file stm32f10x.h.

__IO uint32_t ETH_TypeDef::DMARDLAR

Definition at line 870 of file stm32f10x.h.

__IO uint32_t ETH_TypeDef::DMARPDR

Definition at line 869 of file stm32f10x.h.

__IO uint32_t ETH_TypeDef::DMASR

Definition at line 872 of file stm32f10x.h.

__IO uint32_t ETH_TypeDef::DMATDLAR

Definition at line 871 of file stm32f10x.h.

__IO uint32_t ETH_TypeDef::DMATPDR

Definition at line 868 of file stm32f10x.h.

__IO uint32_t ETH_TypeDef::MACA0HR

Definition at line 832 of file stm32f10x.h.

__IO uint32_t ETH_TypeDef::MACA0LR

Definition at line 833 of file stm32f10x.h.

__IO uint32_t ETH_TypeDef::MACA1HR

Definition at line 834 of file stm32f10x.h.

__IO uint32_t ETH_TypeDef::MACA1LR

Definition at line 835 of file stm32f10x.h.

__IO uint32_t ETH_TypeDef::MACA2HR

Definition at line 836 of file stm32f10x.h.

__IO uint32_t ETH_TypeDef::MACA2LR

Definition at line 837 of file stm32f10x.h.

__IO uint32_t ETH_TypeDef::MACA3HR

Definition at line 838 of file stm32f10x.h.

__IO uint32_t ETH_TypeDef::MACA3LR

Definition at line 839 of file stm32f10x.h.

__IO uint32_t ETH_TypeDef::MACCR

Definition at line 818 of file stm32f10x.h.

__IO uint32_t ETH_TypeDef::MACFCR

Definition at line 824 of file stm32f10x.h.

__IO uint32_t ETH_TypeDef::MACFFR

Definition at line 819 of file stm32f10x.h.

__IO uint32_t ETH_TypeDef::MACHTHR

Definition at line 820 of file stm32f10x.h.

__IO uint32_t ETH_TypeDef::MACHTLR

Definition at line 821 of file stm32f10x.h.

__IO uint32_t ETH_TypeDef::MACIMR

Definition at line 831 of file stm32f10x.h.

__IO uint32_t ETH_TypeDef::MACMIIAR

Definition at line 822 of file stm32f10x.h.

__IO uint32_t ETH_TypeDef::MACMIIDR

Definition at line 823 of file stm32f10x.h.

__IO uint32_t ETH_TypeDef::MACPMTCSR

Definition at line 828 of file stm32f10x.h.

__IO uint32_t ETH_TypeDef::MACRWUFFR

Definition at line 827 of file stm32f10x.h.

__IO uint32_t ETH_TypeDef::MACSR

Definition at line 830 of file stm32f10x.h.

__IO uint32_t ETH_TypeDef::MACVLANTR

Definition at line 825 of file stm32f10x.h.

__IO uint32_t ETH_TypeDef::MMCCR

Definition at line 841 of file stm32f10x.h.

__IO uint32_t ETH_TypeDef::MMCRFAECR

Definition at line 853 of file stm32f10x.h.

__IO uint32_t ETH_TypeDef::MMCRFCECR

Definition at line 852 of file stm32f10x.h.

__IO uint32_t ETH_TypeDef::MMCRGUFCR

Definition at line 855 of file stm32f10x.h.

__IO uint32_t ETH_TypeDef::MMCRIMR

Definition at line 844 of file stm32f10x.h.

__IO uint32_t ETH_TypeDef::MMCRIR

Definition at line 842 of file stm32f10x.h.

__IO uint32_t ETH_TypeDef::MMCTGFCR

Definition at line 850 of file stm32f10x.h.

__IO uint32_t ETH_TypeDef::MMCTGFMSCCR

Definition at line 848 of file stm32f10x.h.

__IO uint32_t ETH_TypeDef::MMCTGFSCCR

Definition at line 847 of file stm32f10x.h.

__IO uint32_t ETH_TypeDef::MMCTIMR

Definition at line 845 of file stm32f10x.h.

__IO uint32_t ETH_TypeDef::MMCTIR

Definition at line 843 of file stm32f10x.h.

__IO uint32_t ETH_TypeDef::PTPSSIR

Definition at line 858 of file stm32f10x.h.

__IO uint32_t ETH_TypeDef::PTPTSAR

Definition at line 863 of file stm32f10x.h.

__IO uint32_t ETH_TypeDef::PTPTSCR

Definition at line 857 of file stm32f10x.h.

__IO uint32_t ETH_TypeDef::PTPTSHR

Definition at line 859 of file stm32f10x.h.

__IO uint32_t ETH_TypeDef::PTPTSHUR

Definition at line 861 of file stm32f10x.h.

__IO uint32_t ETH_TypeDef::PTPTSLR

Definition at line 860 of file stm32f10x.h.

__IO uint32_t ETH_TypeDef::PTPTSLUR

Definition at line 862 of file stm32f10x.h.

__IO uint32_t ETH_TypeDef::PTPTTHR

Definition at line 864 of file stm32f10x.h.

__IO uint32_t ETH_TypeDef::PTPTTLR

Definition at line 865 of file stm32f10x.h.

uint32_t ETH_TypeDef::RESERVED0[2]

Definition at line 826 of file stm32f10x.h.

uint32_t ETH_TypeDef::RESERVED1[2]

Definition at line 829 of file stm32f10x.h.

uint32_t ETH_TypeDef::RESERVED2[40]

Definition at line 840 of file stm32f10x.h.

uint32_t ETH_TypeDef::RESERVED3[14]

Definition at line 846 of file stm32f10x.h.

uint32_t ETH_TypeDef::RESERVED4[5]

Definition at line 849 of file stm32f10x.h.

uint32_t ETH_TypeDef::RESERVED5[10]

Definition at line 851 of file stm32f10x.h.

uint32_t ETH_TypeDef::RESERVED6[10]

Definition at line 854 of file stm32f10x.h.

uint32_t ETH_TypeDef::RESERVED7[334]

Definition at line 856 of file stm32f10x.h.

uint32_t ETH_TypeDef::RESERVED8[567]

Definition at line 866 of file stm32f10x.h.

uint32_t ETH_TypeDef::RESERVED9[9]

Definition at line 876 of file stm32f10x.h.

The documentation for this struct was generated from the following file:
  • stm32f10x.h


STM32F10x Standard Peripherals Firmware Library: EXTI_TypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

EXTI_TypeDef Struct Reference
Peripheral_registers_structures

External Interrupt/Event Controller. More...

#include <stm32f10x.h>

Data Fields

__IO uint32_t | EMR
__IO uint32_t | FTSR
__IO uint32_t | IMR
__IO uint32_t | PR
__IO uint32_t | RTSR
__IO uint32_t | SWIER

Detailed Description

External Interrupt/Event Controller.

Definition at line 887 of file stm32f10x.h.

Field Documentation

__IO uint32_t EXTI_TypeDef::EMR

Definition at line 890 of file stm32f10x.h.

__IO uint32_t EXTI_TypeDef::FTSR

Definition at line 892 of file stm32f10x.h.

__IO uint32_t EXTI_TypeDef::IMR

Definition at line 889 of file stm32f10x.h.

__IO uint32_t EXTI_TypeDef::PR

Definition at line 894 of file stm32f10x.h.

__IO uint32_t EXTI_TypeDef::RTSR

Definition at line 891 of file stm32f10x.h.

__IO uint32_t EXTI_TypeDef::SWIER

Definition at line 893 of file stm32f10x.h.

The documentation for this struct was generated from the following file:
  • stm32f10x.h


STM32F10x Standard Peripherals Firmware Library: FLASH_TypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

FLASH_TypeDef Struct Reference
Peripheral_registers_structures

FLASH Registers. More...

#include <stm32f10x.h>

Data Fields

__IO uint32_t | ACR
__IO uint32_t | AR
__IO uint32_t | CR
__IO uint32_t | KEYR
__IO uint32_t | OBR
__IO uint32_t | OPTKEYR
__IO uint32_t | RESERVED
__IO uint32_t | SR
__IO uint32_t | WRPR

Detailed Description

FLASH Registers.

Definition at line 901 of file stm32f10x.h.

Field Documentation

__IO uint32_t FLASH_TypeDef::ACR

Definition at line 903 of file stm32f10x.h.

__IO uint32_t FLASH_TypeDef::AR

Definition at line 908 of file stm32f10x.h.

__IO uint32_t FLASH_TypeDef::CR

Definition at line 907 of file stm32f10x.h.

__IO uint32_t FLASH_TypeDef::KEYR

Definition at line 904 of file stm32f10x.h.

__IO uint32_t FLASH_TypeDef::OBR

Definition at line 910 of file stm32f10x.h.

__IO uint32_t FLASH_TypeDef::OPTKEYR

Definition at line 905 of file stm32f10x.h.

__IO uint32_t FLASH_TypeDef::RESERVED

Definition at line 909 of file stm32f10x.h.

__IO uint32_t FLASH_TypeDef::SR

Definition at line 906 of file stm32f10x.h.

__IO uint32_t FLASH_TypeDef::WRPR

Definition at line 911 of file stm32f10x.h.

The documentation for this struct was generated from the following file:
  • stm32f10x.h


STM32F10x Standard Peripherals Firmware Library: FSMC_Bank1_TypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

FSMC_Bank1_TypeDef Struct Reference
Peripheral_registers_structures

Flexible Static Memory Controller. More...

#include <stm32f10x.h>

Data Fields

__IO uint32_t BTCR [8]

Detailed Description

Flexible Static Memory Controller.

Definition at line 942 of file stm32f10x.h.

Field Documentation

__IO uint32_t FSMC_Bank1_TypeDef::BTCR[8]

Definition at line 944 of file stm32f10x.h.

The documentation for this struct was generated from the following file:
  • stm32f10x.h


STM32F10x Standard Peripherals Firmware Library: FSMC_Bank1E_TypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

FSMC_Bank1E_TypeDef Struct Reference
Peripheral_registers_structures

Flexible Static Memory Controller Bank1E. More...

#include <stm32f10x.h>

Data Fields

__IO uint32_t BWTR [7]

Detailed Description

Flexible Static Memory Controller Bank1E.

Definition at line 951 of file stm32f10x.h.

Field Documentation

__IO uint32_t FSMC_Bank1E_TypeDef::BWTR[7]

Definition at line 953 of file stm32f10x.h.

The documentation for this struct was generated from the following file:
  • stm32f10x.h


STM32F10x Standard Peripherals Firmware Library: FSMC_Bank2_TypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

FSMC_Bank2_TypeDef Struct Reference
Peripheral_registers_structures

Flexible Static Memory Controller Bank2. More...

#include <stm32f10x.h>

Data Fields

__IO uint32_t | ECCR2
__IO uint32_t | PATT2
__IO uint32_t | PCR2
__IO uint32_t | PMEM2
uint32_t | RESERVED0
__IO uint32_t | SR2

Detailed Description

Flexible Static Memory Controller Bank2.

Definition at line 960 of file stm32f10x.h.

Field Documentation

__IO uint32_t FSMC_Bank2_TypeDef::ECCR2

Definition at line 967 of file stm32f10x.h.

__IO uint32_t FSMC_Bank2_TypeDef::PATT2

Definition at line 965 of file stm32f10x.h.

__IO uint32_t FSMC_Bank2_TypeDef::PCR2

Definition at line 962 of file stm32f10x.h.

__IO uint32_t FSMC_Bank2_TypeDef::PMEM2

Definition at line 964 of file stm32f10x.h.

uint32_t FSMC_Bank2_TypeDef::RESERVED0

Definition at line 966 of file stm32f10x.h.

__IO uint32_t FSMC_Bank2_TypeDef::SR2

Definition at line 963 of file stm32f10x.h.

The documentation for this struct was generated from the following file:
  • stm32f10x.h


STM32F10x Standard Peripherals Firmware Library: FSMC_Bank3_TypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

FSMC_Bank3_TypeDef Struct Reference
Peripheral_registers_structures

Flexible Static Memory Controller Bank3. More...

#include <stm32f10x.h>

Data Fields

__IO uint32_t | ECCR3
__IO uint32_t | PATT3
__IO uint32_t | PCR3
__IO uint32_t | PMEM3
uint32_t | RESERVED0
__IO uint32_t | SR3

Detailed Description

Flexible Static Memory Controller Bank3.

Definition at line 974 of file stm32f10x.h.

Field Documentation

__IO uint32_t FSMC_Bank3_TypeDef::ECCR3

Definition at line 981 of file stm32f10x.h.

__IO uint32_t FSMC_Bank3_TypeDef::PATT3

Definition at line 979 of file stm32f10x.h.

__IO uint32_t FSMC_Bank3_TypeDef::PCR3

Definition at line 976 of file stm32f10x.h.

__IO uint32_t FSMC_Bank3_TypeDef::PMEM3

Definition at line 978 of file stm32f10x.h.

uint32_t FSMC_Bank3_TypeDef::RESERVED0

Definition at line 980 of file stm32f10x.h.

__IO uint32_t FSMC_Bank3_TypeDef::SR3

Definition at line 977 of file stm32f10x.h.

The documentation for this struct was generated from the following file:
  • stm32f10x.h


STM32F10x Standard Peripherals Firmware Library: FSMC_Bank4_TypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

FSMC_Bank4_TypeDef Struct Reference
Peripheral_registers_structures

Flexible Static Memory Controller Bank4. More...

#include <stm32f10x.h>

Data Fields

__IO uint32_t | PATT4
__IO uint32_t | PCR4
__IO uint32_t | PIO4
__IO uint32_t | PMEM4
__IO uint32_t | SR4

Detailed Description

Flexible Static Memory Controller Bank4.

Definition at line 988 of file stm32f10x.h.

Field Documentation

__IO uint32_t FSMC_Bank4_TypeDef::PATT4

Definition at line 993 of file stm32f10x.h.

__IO uint32_t FSMC_Bank4_TypeDef::PCR4

Definition at line 990 of file stm32f10x.h.

__IO uint32_t FSMC_Bank4_TypeDef::PIO4

Definition at line 994 of file stm32f10x.h.

__IO uint32_t FSMC_Bank4_TypeDef::PMEM4

Definition at line 992 of file stm32f10x.h.

__IO uint32_t FSMC_Bank4_TypeDef::SR4

Definition at line 991 of file stm32f10x.h.

The documentation for this struct was generated from the following file:
  • stm32f10x.h


STM32F10x Standard Peripherals Firmware Library: GPIO_TypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

GPIO_TypeDef Struct Reference
Peripheral_registers_structures

General Purpose I/O. More...

#include <stm32f10x.h>

Data Fields

__IO uint32_t | BRR
__IO uint32_t | BSRR
__IO uint32_t | CRH
__IO uint32_t | CRL
__IO uint32_t | IDR
__IO uint32_t | LCKR
__IO uint32_t | ODR

Detailed Description

General Purpose I/O.

Definition at line 1001 of file stm32f10x.h.

Field Documentation

__IO uint32_t GPIO_TypeDef::BRR

Definition at line 1008 of file stm32f10x.h.

Referenced by GPIO_Init(), GPIO_ResetBits(), GPIO_WriteBit(), and STM_EVAL_LEDOff().

__IO uint32_t GPIO_TypeDef::BSRR

Definition at line 1007 of file stm32f10x.h.

Referenced by GPIO_Init(), GPIO_SetBits(), GPIO_WriteBit(), and STM_EVAL_LEDOn().

__IO uint32_t GPIO_TypeDef::CRH

Definition at line 1004 of file stm32f10x.h.

Referenced by GPIO_Init().

__IO uint32_t GPIO_TypeDef::CRL

Definition at line 1003 of file stm32f10x.h.

Referenced by GPIO_Init().

__IO uint32_t GPIO_TypeDef::IDR

Definition at line 1005 of file stm32f10x.h.

Referenced by GPIO_ReadInputData(), and GPIO_ReadInputDataBit().

__IO uint32_t GPIO_TypeDef::LCKR

Definition at line 1009 of file stm32f10x.h.

Referenced by GPIO_PinLockConfig().

__IO uint32_t GPIO_TypeDef::ODR

Definition at line 1006 of file stm32f10x.h.

Referenced by GPIO_ReadOutputData(), GPIO_ReadOutputDataBit(), GPIO_Write(), and STM_EVAL_LEDToggle().

The documentation for this struct was generated from the following file:
  • stm32f10x.h


STM32F10x Standard Peripherals Firmware Library: I2C_TypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

I2C_TypeDef Struct Reference
Peripheral_registers_structures

Inter Integrated Circuit Interface. More...

#include <stm32f10x.h>

Data Fields

__IO uint16_t | CCR
__IO uint16_t | CR1
__IO uint16_t | CR2
__IO uint16_t | DR
__IO uint16_t | OAR1
__IO uint16_t | OAR2
uint16_t | RESERVED0
uint16_t | RESERVED1
uint16_t | RESERVED2
uint16_t | RESERVED3
uint16_t | RESERVED4
uint16_t | RESERVED5
uint16_t | RESERVED6
uint16_t | RESERVED7
uint16_t | RESERVED8
__IO uint16_t | SR1
__IO uint16_t | SR2
__IO uint16_t | TRISE

Detailed Description

Inter Integrated Circuit Interface.

Definition at line 1028 of file stm32f10x.h.

Field Documentation

__IO uint16_t I2C_TypeDef::CCR

Definition at line 1044 of file stm32f10x.h.

Referenced by I2C_FastModeDutyCycleConfig(), and I2C_Init().

__IO uint16_t I2C_TypeDef::CR1

Definition at line 1030 of file stm32f10x.h.

Referenced by I2C_AcknowledgeConfig(), I2C_ARPCmd(), I2C_CalculatePEC(), I2C_Cmd(), I2C_GeneralCallCmd(), I2C_GenerateSTART(), I2C_GenerateSTOP(), I2C_Init(), I2C_NACKPositionConfig(), I2C_PECPositionConfig(), I2C_SMBusAlertConfig(), I2C_SoftwareResetCmd(), I2C_StretchClockCmd(), and I2C_TransmitPEC().

__IO uint16_t I2C_TypeDef::CR2

Definition at line 1032 of file stm32f10x.h.

Referenced by I2C_DMACmd(), I2C_DMALastTransferCmd(), I2C_GetITStatus(), I2C_Init(), and I2C_ITConfig().

__IO uint16_t I2C_TypeDef::DR

Definition at line 1038 of file stm32f10x.h.

Referenced by I2C_ReceiveData(), I2C_Send7bitAddress(), and I2C_SendData().

__IO uint16_t I2C_TypeDef::OAR1

Definition at line 1034 of file stm32f10x.h.

Referenced by I2C_Init().

__IO uint16_t I2C_TypeDef::OAR2

Definition at line 1036 of file stm32f10x.h.

Referenced by I2C_DualAddressCmd(), and I2C_OwnAddress2Config().

uint16_t I2C_TypeDef::RESERVED0

Definition at line 1031 of file stm32f10x.h.

uint16_t I2C_TypeDef::RESERVED1

Definition at line 1033 of file stm32f10x.h.

uint16_t I2C_TypeDef::RESERVED2

Definition at line 1035 of file stm32f10x.h.

uint16_t I2C_TypeDef::RESERVED3

Definition at line 1037 of file stm32f10x.h.

uint16_t I2C_TypeDef::RESERVED4

Definition at line 1039 of file stm32f10x.h.

uint16_t I2C_TypeDef::RESERVED5

Definition at line 1041 of file stm32f10x.h.

uint16_t I2C_TypeDef::RESERVED6

Definition at line 1043 of file stm32f10x.h.

uint16_t I2C_TypeDef::RESERVED7

Definition at line 1045 of file stm32f10x.h.

uint16_t I2C_TypeDef::RESERVED8

Definition at line 1047 of file stm32f10x.h.

__IO uint16_t I2C_TypeDef::SR1

Definition at line 1040 of file stm32f10x.h.

Referenced by I2C_CheckEvent(), I2C_ClearFlag(), I2C_ClearITPendingBit(), I2C_GetITStatus(), and I2C_GetLastEvent().

__IO uint16_t I2C_TypeDef::SR2

Definition at line 1042 of file stm32f10x.h.

Referenced by I2C_CheckEvent(), I2C_GetLastEvent(), and I2C_GetPEC().

__IO uint16_t I2C_TypeDef::TRISE

Definition at line 1046 of file stm32f10x.h.

Referenced by I2C_Init().

The documentation for this struct was generated from the following file:
  • stm32f10x.h


STM32F10x Standard Peripherals Firmware Library: IWDG_TypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

IWDG_TypeDef Struct Reference
Peripheral_registers_structures

Independent WATCHDOG. More...

#include <stm32f10x.h>

Data Fields

__IO uint32_t | KR
__IO uint32_t | PR
__IO uint32_t | RLR
__IO uint32_t | SR

Detailed Description

Independent WATCHDOG.

Definition at line 1054 of file stm32f10x.h.

Field Documentation

__IO uint32_t IWDG_TypeDef::KR

Definition at line 1056 of file stm32f10x.h.

__IO uint32_t IWDG_TypeDef::PR

Definition at line 1057 of file stm32f10x.h.

__IO uint32_t IWDG_TypeDef::RLR

Definition at line 1058 of file stm32f10x.h.

__IO uint32_t IWDG_TypeDef::SR

Definition at line 1059 of file stm32f10x.h.

The documentation for this struct was generated from the following file:
  • stm32f10x.h


STM32F10x Standard Peripherals Firmware Library: OB_TypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

OB_TypeDef Struct Reference
Peripheral_registers_structures

Option Bytes Registers. More...

#include <stm32f10x.h>

Data Fields

__IO uint16_t | Data0
__IO uint16_t | Data1
__IO uint16_t | RDP
__IO uint16_t | USER
__IO uint16_t | WRP0
__IO uint16_t | WRP1
__IO uint16_t | WRP2
__IO uint16_t | WRP3

Detailed Description

Option Bytes Registers.

Definition at line 926 of file stm32f10x.h.

Field Documentation

__IO uint16_t OB_TypeDef::Data0

Definition at line 930 of file stm32f10x.h.

__IO uint16_t OB_TypeDef::Data1

Definition at line 931 of file stm32f10x.h.

__IO uint16_t OB_TypeDef::RDP

Definition at line 928 of file stm32f10x.h.

__IO uint16_t OB_TypeDef::USER

Definition at line 929 of file stm32f10x.h.

__IO uint16_t OB_TypeDef::WRP0

Definition at line 932 of file stm32f10x.h.

__IO uint16_t OB_TypeDef::WRP1

Definition at line 933 of file stm32f10x.h.

__IO uint16_t OB_TypeDef::WRP2

Definition at line 934 of file stm32f10x.h.

__IO uint16_t OB_TypeDef::WRP3

Definition at line 935 of file stm32f10x.h.

The documentation for this struct was generated from the following file:
  • stm32f10x.h


STM32F10x Standard Peripherals Firmware Library: PWR_TypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

PWR_TypeDef Struct Reference
Peripheral_registers_structures

Power Control. More...

#include <stm32f10x.h>

Data Fields

__IO uint32_t | CR
__IO uint32_t | CSR

Detailed Description

Power Control.

Definition at line 1066 of file stm32f10x.h.

Field Documentation

__IO uint32_t PWR_TypeDef::CR

Definition at line 1068 of file stm32f10x.h.

__IO uint32_t PWR_TypeDef::CSR

Definition at line 1069 of file stm32f10x.h.

The documentation for this struct was generated from the following file:
  • stm32f10x.h


STM32F10x Standard Peripherals Firmware Library: RCC_TypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

RCC_TypeDef Struct Reference
Peripheral_registers_structures

Reset and Clock Control. More...

#include <stm32f10x.h>

Data Fields

__IO uint32_t | AHBENR
__IO uint32_t | APB1ENR
__IO uint32_t | APB1RSTR
__IO uint32_t | APB2ENR
__IO uint32_t | APB2RSTR
__IO uint32_t | BDCR
__IO uint32_t | CFGR
__IO uint32_t | CIR
__IO uint32_t | CR
__IO uint32_t | CSR

Detailed Description

Reset and Clock Control.

Definition at line 1076 of file stm32f10x.h.

Field Documentation

__IO uint32_t RCC_TypeDef::AHBENR

Definition at line 1083 of file stm32f10x.h.

__IO uint32_t RCC_TypeDef::APB1ENR

Definition at line 1085 of file stm32f10x.h.

__IO uint32_t RCC_TypeDef::APB1RSTR

Definition at line 1082 of file stm32f10x.h.

__IO uint32_t RCC_TypeDef::APB2ENR

Definition at line 1084 of file stm32f10x.h.

__IO uint32_t RCC_TypeDef::APB2RSTR

Definition at line 1081 of file stm32f10x.h.

__IO uint32_t RCC_TypeDef::BDCR

Definition at line 1086 of file stm32f10x.h.

__IO uint32_t RCC_TypeDef::CFGR

Definition at line 1079 of file stm32f10x.h.

__IO uint32_t RCC_TypeDef::CIR

Definition at line 1080 of file stm32f10x.h.

__IO uint32_t RCC_TypeDef::CR

Definition at line 1078 of file stm32f10x.h.

__IO uint32_t RCC_TypeDef::CSR

Definition at line 1087 of file stm32f10x.h.

The documentation for this struct was generated from the following file:
  • stm32f10x.h


STM32F10x Standard Peripherals Firmware Library: RTC_TypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

RTC_TypeDef Struct Reference
Peripheral_registers_structures

Real-Time Clock. More...

#include <stm32f10x.h>

Data Fields

__IO uint16_t | ALRH
__IO uint16_t | ALRL
__IO uint16_t | CNTH
__IO uint16_t | CNTL
__IO uint16_t | CRH
__IO uint16_t | CRL
__IO uint16_t | DIVH
__IO uint16_t | DIVL
__IO uint16_t | PRLH
__IO uint16_t | PRLL
uint16_t | RESERVED0
uint16_t | RESERVED1
uint16_t | RESERVED2
uint16_t | RESERVED3
uint16_t | RESERVED4
uint16_t | RESERVED5
uint16_t | RESERVED6
uint16_t | RESERVED7
uint16_t | RESERVED8
uint16_t | RESERVED9

Detailed Description

Real-Time Clock.

Definition at line 1104 of file stm32f10x.h.

Field Documentation

__IO uint16_t RTC_TypeDef::ALRH

Definition at line 1122 of file stm32f10x.h.

__IO uint16_t RTC_TypeDef::ALRL

Definition at line 1124 of file stm32f10x.h.

__IO uint16_t RTC_TypeDef::CNTH

Definition at line 1118 of file stm32f10x.h.

__IO uint16_t RTC_TypeDef::CNTL

Definition at line 1120 of file stm32f10x.h.

__IO uint16_t RTC_TypeDef::CRH

Definition at line 1106 of file stm32f10x.h.

__IO uint16_t RTC_TypeDef::CRL

Definition at line 1108 of file stm32f10x.h.

__IO uint16_t RTC_TypeDef::DIVH

Definition at line 1114 of file stm32f10x.h.

__IO uint16_t RTC_TypeDef::DIVL

Definition at line 1116 of file stm32f10x.h.

__IO uint16_t RTC_TypeDef::PRLH

Definition at line 1110 of file stm32f10x.h.

__IO uint16_t RTC_TypeDef::PRLL

Definition at line 1112 of file stm32f10x.h.

uint16_t RTC_TypeDef::RESERVED0

Definition at line 1107 of file stm32f10x.h.

uint16_t RTC_TypeDef::RESERVED1

Definition at line 1109 of file stm32f10x.h.

uint16_t RTC_TypeDef::RESERVED2

Definition at line 1111 of file stm32f10x.h.

uint16_t RTC_TypeDef::RESERVED3

Definition at line 1113 of file stm32f10x.h.

uint16_t RTC_TypeDef::RESERVED4

Definition at line 1115 of file stm32f10x.h.

uint16_t RTC_TypeDef::RESERVED5

Definition at line 1117 of file stm32f10x.h.

uint16_t RTC_TypeDef::RESERVED6

Definition at line 1119 of file stm32f10x.h.

uint16_t RTC_TypeDef::RESERVED7

Definition at line 1121 of file stm32f10x.h.

uint16_t RTC_TypeDef::RESERVED8

Definition at line 1123 of file stm32f10x.h.

uint16_t RTC_TypeDef::RESERVED9

Definition at line 1125 of file stm32f10x.h.

The documentation for this struct was generated from the following file:
  • stm32f10x.h


STM32F10x Standard Peripherals Firmware Library: SDIO_TypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

SDIO_TypeDef Struct Reference
Peripheral_registers_structures

SD host Interface. More...

#include <stm32f10x.h>

Data Fields

__IO uint32_t | ARG
__IO uint32_t | CLKCR
__IO uint32_t | CMD
__I uint32_t | DCOUNT
__IO uint32_t | DCTRL
__IO uint32_t | DLEN
__IO uint32_t | DTIMER
__IO uint32_t | FIFO
__I uint32_t | FIFOCNT
__IO uint32_t | ICR
__IO uint32_t | MASK
__IO uint32_t | POWER
uint32_t | RESERVED0 [2]
uint32_t | RESERVED1 [13]
__I uint32_t | RESP1
__I uint32_t | RESP2
__I uint32_t | RESP3
__I uint32_t | RESP4
__I uint32_t | RESPCMD
__I uint32_t | STA

Detailed Description

SD host Interface.

Definition at line 1132 of file stm32f10x.h.

Field Documentation

__IO uint32_t SDIO_TypeDef::ARG

Definition at line 1136 of file stm32f10x.h.

__IO uint32_t SDIO_TypeDef::CLKCR

Definition at line 1135 of file stm32f10x.h.

__IO uint32_t SDIO_TypeDef::CMD

Definition at line 1137 of file stm32f10x.h.

__I uint32_t SDIO_TypeDef::DCOUNT

Definition at line 1146 of file stm32f10x.h.

__IO uint32_t SDIO_TypeDef::DCTRL

Definition at line 1145 of file stm32f10x.h.

__IO uint32_t SDIO_TypeDef::DLEN

Definition at line 1144 of file stm32f10x.h.

__IO uint32_t SDIO_TypeDef::DTIMER

Definition at line 1143 of file stm32f10x.h.

__IO uint32_t SDIO_TypeDef::FIFO

Definition at line 1153 of file stm32f10x.h.

__I uint32_t SDIO_TypeDef::FIFOCNT

Definition at line 1151 of file stm32f10x.h.

__IO uint32_t SDIO_TypeDef::ICR

Definition at line 1148 of file stm32f10x.h.

__IO uint32_t SDIO_TypeDef::MASK

Definition at line 1149 of file stm32f10x.h.

__IO uint32_t SDIO_TypeDef::POWER

Definition at line 1134 of file stm32f10x.h.

uint32_t SDIO_TypeDef::RESERVED0[2]

Definition at line 1150 of file stm32f10x.h.

uint32_t SDIO_TypeDef::RESERVED1[13]

Definition at line 1152 of file stm32f10x.h.

__I uint32_t SDIO_TypeDef::RESP1

Definition at line 1139 of file stm32f10x.h.

__I uint32_t SDIO_TypeDef::RESP2

Definition at line 1140 of file stm32f10x.h.

__I uint32_t SDIO_TypeDef::RESP3

Definition at line 1141 of file stm32f10x.h.

__I uint32_t SDIO_TypeDef::RESP4

Definition at line 1142 of file stm32f10x.h.

__I uint32_t SDIO_TypeDef::RESPCMD

Definition at line 1138 of file stm32f10x.h.

__I uint32_t SDIO_TypeDef::STA

Definition at line 1147 of file stm32f10x.h.

The documentation for this struct was generated from the following file:
  • stm32f10x.h


STM32F10x Standard Peripherals Firmware Library: SPI_TypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

SPI_TypeDef Struct Reference
Peripheral_registers_structures

Serial Peripheral Interface. More...

#include <stm32f10x.h>

Data Fields

__IO uint16_t | CR1
__IO uint16_t | CR2
__IO uint16_t | CRCPR
__IO uint16_t | DR
__IO uint16_t | I2SCFGR
__IO uint16_t | I2SPR
uint16_t | RESERVED0
uint16_t | RESERVED1
uint16_t | RESERVED2
uint16_t | RESERVED3
uint16_t | RESERVED4
uint16_t | RESERVED5
uint16_t | RESERVED6
uint16_t | RESERVED7
uint16_t | RESERVED8
__IO uint16_t | RXCRCR
__IO uint16_t | SR
__IO uint16_t | TXCRCR

Detailed Description

Serial Peripheral Interface.

Definition at line 1160 of file stm32f10x.h.

Field Documentation

__IO uint16_t SPI_TypeDef::CR1

Definition at line 1162 of file stm32f10x.h.

Referenced by SPI_BiDirectionalLineConfig(), SPI_CalculateCRC(), SPI_Cmd(), SPI_DataSizeConfig(), SPI_Init(), SPI_NSSInternalSoftwareConfig(), and SPI_TransmitCRC().

__IO uint16_t SPI_TypeDef::CR2

Definition at line 1164 of file stm32f10x.h.

Referenced by SPI_I2S_DMACmd(), SPI_I2S_GetITStatus(), SPI_I2S_ITConfig(), and SPI_SSOutputCmd().

__IO uint16_t SPI_TypeDef::CRCPR

Definition at line 1170 of file stm32f10x.h.

Referenced by SPI_GetCRCPolynomial(), and SPI_Init().

__IO uint16_t SPI_TypeDef::DR

Definition at line 1168 of file stm32f10x.h.

Referenced by SPI_I2S_ReceiveData(), and SPI_I2S_SendData().

__IO uint16_t SPI_TypeDef::I2SCFGR

Definition at line 1176 of file stm32f10x.h.

Referenced by I2S_Cmd(), I2S_Init(), and SPI_Init().

__IO uint16_t SPI_TypeDef::I2SPR

Definition at line 1178 of file stm32f10x.h.

Referenced by I2S_Init().

uint16_t SPI_TypeDef::RESERVED0

Definition at line 1163 of file stm32f10x.h.

uint16_t SPI_TypeDef::RESERVED1

Definition at line 1165 of file stm32f10x.h.

uint16_t SPI_TypeDef::RESERVED2

Definition at line 1167 of file stm32f10x.h.

uint16_t SPI_TypeDef::RESERVED3

Definition at line 1169 of file stm32f10x.h.

uint16_t SPI_TypeDef::RESERVED4

Definition at line 1171 of file stm32f10x.h.

uint16_t SPI_TypeDef::RESERVED5

Definition at line 1173 of file stm32f10x.h.

uint16_t SPI_TypeDef::RESERVED6

Definition at line 1175 of file stm32f10x.h.

uint16_t SPI_TypeDef::RESERVED7

Definition at line 1177 of file stm32f10x.h.

uint16_t SPI_TypeDef::RESERVED8

Definition at line 1179 of file stm32f10x.h.

__IO uint16_t SPI_TypeDef::RXCRCR

Definition at line 1172 of file stm32f10x.h.

Referenced by SPI_GetCRC().

__IO uint16_t SPI_TypeDef::SR

Definition at line 1166 of file stm32f10x.h.

Referenced by SPI_I2S_ClearFlag(), SPI_I2S_ClearITPendingBit(), SPI_I2S_GetFlagStatus(), and SPI_I2S_GetITStatus().

__IO uint16_t SPI_TypeDef::TXCRCR

Definition at line 1174 of file stm32f10x.h.

Referenced by SPI_GetCRC().

The documentation for this struct was generated from the following file:
  • stm32f10x.h


STM32F10x Standard Peripherals Firmware Library: TIM_TypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

TIM_TypeDef Struct Reference
Peripheral_registers_structures

TIM. More...

#include <stm32f10x.h>

Data Fields

__IO uint16_t | ARR
__IO uint16_t | BDTR
__IO uint16_t | CCER
__IO uint16_t | CCMR1
__IO uint16_t | CCMR2
__IO uint16_t | CCR1
__IO uint16_t | CCR2
__IO uint16_t | CCR3
__IO uint16_t | CCR4
__IO uint16_t | CNT
__IO uint16_t | CR1
__IO uint16_t | CR2
__IO uint16_t | DCR
__IO uint16_t | DIER
__IO uint16_t | DMAR
__IO uint16_t | EGR
__IO uint16_t | PSC
__IO uint16_t | RCR
uint16_t | RESERVED0
uint16_t | RESERVED1
uint16_t | RESERVED10
uint16_t | RESERVED11
uint16_t | RESERVED12
uint16_t | RESERVED13
uint16_t | RESERVED14
uint16_t | RESERVED15
uint16_t | RESERVED16
uint16_t | RESERVED17
uint16_t | RESERVED18
uint16_t | RESERVED19
uint16_t | RESERVED2
uint16_t | RESERVED3
uint16_t | RESERVED4
uint16_t | RESERVED5
uint16_t | RESERVED6
uint16_t | RESERVED7
uint16_t | RESERVED8
uint16_t | RESERVED9
__IO uint16_t | SMCR
__IO uint16_t | SR

Detailed Description

TIM.

Definition at line 1186 of file stm32f10x.h.

Field Documentation

__IO uint16_t TIM_TypeDef::ARR

Definition at line 1210 of file stm32f10x.h.

Referenced by TIM_SetAutoreload(), and TIM_TimeBaseInit().

__IO uint16_t TIM_TypeDef::BDTR

Definition at line 1222 of file stm32f10x.h.

Referenced by TIM_BDTRConfig(), and TIM_CtrlPWMOutputs().

__IO uint16_t TIM_TypeDef::CCER

Definition at line 1204 of file stm32f10x.h.

Referenced by TI1_Config(), TI2_Config(), TI3_Config(), TI4_Config(), TIM_CCxCmd(), TIM_CCxNCmd(), TIM_EncoderInterfaceConfig(), TIM_OC1Init(), TIM_OC1NPolarityConfig(), TIM_OC1PolarityConfig(), TIM_OC2Init(), TIM_OC2NPolarityConfig(), TIM_OC2PolarityConfig(), TIM_OC3Init(), TIM_OC3NPolarityConfig(), TIM_OC3PolarityConfig(), TIM_OC4Init(), TIM_OC4PolarityConfig(), and TIM_SelectOCxM().

__IO uint16_t TIM_TypeDef::CCMR1

Definition at line 1200 of file stm32f10x.h.

Referenced by TI1_Config(), TI2_Config(), TIM_ClearOC1Ref(), TIM_ClearOC2Ref(), TIM_EncoderInterfaceConfig(), TIM_ForcedOC1Config(), TIM_ForcedOC2Config(), TIM_OC1FastConfig(), TIM_OC1Init(), TIM_OC1PreloadConfig(), TIM_OC2FastConfig(), TIM_OC2Init(), TIM_OC2PreloadConfig(), TIM_SetIC1Prescaler(), and TIM_SetIC2Prescaler().

__IO uint16_t TIM_TypeDef::CCMR2

Definition at line 1202 of file stm32f10x.h.

Referenced by TI3_Config(), TI4_Config(), TIM_ClearOC3Ref(), TIM_ClearOC4Ref(), TIM_ForcedOC3Config(), TIM_ForcedOC4Config(), TIM_OC3FastConfig(), TIM_OC3Init(), TIM_OC3PreloadConfig(), TIM_OC4FastConfig(), TIM_OC4Init(), TIM_OC4PreloadConfig(), TIM_SetIC3Prescaler(), and TIM_SetIC4Prescaler().

__IO uint16_t TIM_TypeDef::CCR1

Definition at line 1214 of file stm32f10x.h.

Referenced by TIM_GetCapture1(), TIM_OC1Init(), and TIM_SetCompare1().

__IO uint16_t TIM_TypeDef::CCR2

Definition at line 1216 of file stm32f10x.h.

Referenced by TIM_GetCapture2(), TIM_OC2Init(), and TIM_SetCompare2().

__IO uint16_t TIM_TypeDef::CCR3

Definition at line 1218 of file stm32f10x.h.

Referenced by TIM_GetCapture3(), TIM_OC3Init(), and TIM_SetCompare3().

__IO uint16_t TIM_TypeDef::CCR4

Definition at line 1220 of file stm32f10x.h.

Referenced by TIM_GetCapture4(), TIM_OC4Init(), and TIM_SetCompare4().

__IO uint16_t TIM_TypeDef::CNT

Definition at line 1206 of file stm32f10x.h.

Referenced by TIM_GetCounter(), and TIM_SetCounter().

__IO uint16_t TIM_TypeDef::CR1

Definition at line 1188 of file stm32f10x.h.

Referenced by TIM_ARRPreloadConfig(), TIM_Cmd(), TIM_CounterModeConfig(), TIM_SelectOnePulseMode(), TIM_SetClockDivision(), TIM_TimeBaseInit(), TIM_UpdateDisableConfig(), and TIM_UpdateRequestConfig().

__IO uint16_t TIM_TypeDef::CR2

Definition at line 1190 of file stm32f10x.h.

Referenced by TIM_CCPreloadControl(), TIM_OC1Init(), TIM_OC2Init(), TIM_OC3Init(), TIM_OC4Init(), TIM_SelectCCDMA(), TIM_SelectCOM(), TIM_SelectHallSensor(), and TIM_SelectOutputTrigger().

__IO uint16_t TIM_TypeDef::DCR

Definition at line 1224 of file stm32f10x.h.

Referenced by TIM_DMAConfig().

__IO uint16_t TIM_TypeDef::DIER

Definition at line 1194 of file stm32f10x.h.

Referenced by TIM_DMACmd(), TIM_GetITStatus(), and TIM_ITConfig().

__IO uint16_t TIM_TypeDef::DMAR

Definition at line 1226 of file stm32f10x.h.

__IO uint16_t TIM_TypeDef::EGR

Definition at line 1198 of file stm32f10x.h.

Referenced by TIM_GenerateEvent(), TIM_PrescalerConfig(), and TIM_TimeBaseInit().

__IO uint16_t TIM_TypeDef::PSC

Definition at line 1208 of file stm32f10x.h.

Referenced by TIM_GetPrescaler(), TIM_PrescalerConfig(), and TIM_TimeBaseInit().

__IO uint16_t TIM_TypeDef::RCR

Definition at line 1212 of file stm32f10x.h.

Referenced by TIM_TimeBaseInit().

uint16_t TIM_TypeDef::RESERVED0

Definition at line 1189 of file stm32f10x.h.

uint16_t TIM_TypeDef::RESERVED1

Definition at line 1191 of file stm32f10x.h.

uint16_t TIM_TypeDef::RESERVED10

Definition at line 1209 of file stm32f10x.h.

uint16_t TIM_TypeDef::RESERVED11

Definition at line 1211 of file stm32f10x.h.

uint16_t TIM_TypeDef::RESERVED12

Definition at line 1213 of file stm32f10x.h.

uint16_t TIM_TypeDef::RESERVED13

Definition at line 1215 of file stm32f10x.h.

uint16_t TIM_TypeDef::RESERVED14

Definition at line 1217 of file stm32f10x.h.

uint16_t TIM_TypeDef::RESERVED15

Definition at line 1219 of file stm32f10x.h.

uint16_t TIM_TypeDef::RESERVED16

Definition at line 1221 of file stm32f10x.h.

uint16_t TIM_TypeDef::RESERVED17

Definition at line 1223 of file stm32f10x.h.

uint16_t TIM_TypeDef::RESERVED18

Definition at line 1225 of file stm32f10x.h.

uint16_t TIM_TypeDef::RESERVED19

Definition at line 1227 of file stm32f10x.h.

uint16_t TIM_TypeDef::RESERVED2

Definition at line 1193 of file stm32f10x.h.

uint16_t TIM_TypeDef::RESERVED3

Definition at line 1195 of file stm32f10x.h.

uint16_t TIM_TypeDef::RESERVED4

Definition at line 1197 of file stm32f10x.h.

uint16_t TIM_TypeDef::RESERVED5

Definition at line 1199 of file stm32f10x.h.

uint16_t TIM_TypeDef::RESERVED6

Definition at line 1201 of file stm32f10x.h.

uint16_t TIM_TypeDef::RESERVED7

Definition at line 1203 of file stm32f10x.h.

uint16_t TIM_TypeDef::RESERVED8

Definition at line 1205 of file stm32f10x.h.

uint16_t TIM_TypeDef::RESERVED9

Definition at line 1207 of file stm32f10x.h.

__IO uint16_t TIM_TypeDef::SMCR

Definition at line 1192 of file stm32f10x.h.

Referenced by TIM_EncoderInterfaceConfig(), TIM_ETRClockMode1Config(), TIM_ETRClockMode2Config(), TIM_ETRConfig(), TIM_InternalClockConfig(), TIM_ITRxExternalClockConfig(), TIM_SelectInputTrigger(), TIM_SelectMasterSlaveMode(), TIM_SelectSlaveMode(), and TIM_TIxExternalClockConfig().

__IO uint16_t TIM_TypeDef::SR

Definition at line 1196 of file stm32f10x.h.

Referenced by TIM_ClearFlag(), TIM_ClearITPendingBit(), TIM_GetFlagStatus(), and TIM_GetITStatus().

The documentation for this struct was generated from the following file:
  • stm32f10x.h


STM32F10x Standard Peripherals Firmware Library: USART_TypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

USART_TypeDef Struct Reference
Peripheral_registers_structures

Universal Synchronous Asynchronous Receiver Transmitter. More...

#include <stm32f10x.h>

Data Fields

__IO uint16_t | BRR
__IO uint16_t | CR1
__IO uint16_t | CR2
__IO uint16_t | CR3
__IO uint16_t | DR
__IO uint16_t | GTPR
uint16_t | RESERVED0
uint16_t | RESERVED1
uint16_t | RESERVED2
uint16_t | RESERVED3
uint16_t | RESERVED4
uint16_t | RESERVED5
uint16_t | RESERVED6
__IO uint16_t | SR

Detailed Description

Universal Synchronous Asynchronous Receiver Transmitter.

Definition at line 1234 of file stm32f10x.h.

Field Documentation

__IO uint16_t USART_TypeDef::BRR

Definition at line 1240 of file stm32f10x.h.

Referenced by USART_Init().

__IO uint16_t USART_TypeDef::CR1

Definition at line 1242 of file stm32f10x.h.

Referenced by USART_Cmd(), USART_GetITStatus(), USART_Init(), USART_OverSampling8Cmd(), USART_ReceiverWakeUpCmd(), USART_SendBreak(), and USART_WakeUpConfig().

__IO uint16_t USART_TypeDef::CR2

Definition at line 1244 of file stm32f10x.h.

Referenced by USART_ClockInit(), USART_GetITStatus(), USART_Init(), USART_LINBreakDetectLengthConfig(), USART_LINCmd(), and USART_SetAddress().

__IO uint16_t USART_TypeDef::CR3

Definition at line 1246 of file stm32f10x.h.

Referenced by USART_DMACmd(), USART_GetITStatus(), USART_HalfDuplexCmd(), USART_Init(), USART_IrDACmd(), USART_IrDAConfig(), USART_OneBitMethodCmd(), USART_SmartCardCmd(), and USART_SmartCardNACKCmd().

__IO uint16_t USART_TypeDef::DR

Definition at line 1238 of file stm32f10x.h.

Referenced by USART_ReceiveData(), and USART_SendData().

__IO uint16_t USART_TypeDef::GTPR

Definition at line 1248 of file stm32f10x.h.

Referenced by USART_SetGuardTime(), and USART_SetPrescaler().

uint16_t USART_TypeDef::RESERVED0

Definition at line 1237 of file stm32f10x.h.

uint16_t USART_TypeDef::RESERVED1

Definition at line 1239 of file stm32f10x.h.

uint16_t USART_TypeDef::RESERVED2

Definition at line 1241 of file stm32f10x.h.

uint16_t USART_TypeDef::RESERVED3

Definition at line 1243 of file stm32f10x.h.

uint16_t USART_TypeDef::RESERVED4

Definition at line 1245 of file stm32f10x.h.

uint16_t USART_TypeDef::RESERVED5

Definition at line 1247 of file stm32f10x.h.

uint16_t USART_TypeDef::RESERVED6

Definition at line 1249 of file stm32f10x.h.

__IO uint16_t USART_TypeDef::SR

Definition at line 1236 of file stm32f10x.h.

Referenced by USART_ClearFlag(), USART_ClearITPendingBit(), USART_GetFlagStatus(), and USART_GetITStatus().

The documentation for this struct was generated from the following file:
  • stm32f10x.h


STM32F10x Standard Peripherals Firmware Library: WWDG_TypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

WWDG_TypeDef Struct Reference
Peripheral_registers_structures

Window WATCHDOG. More...

#include <stm32f10x.h>

Data Fields

__IO uint32_t | CFR
__IO uint32_t | CR
__IO uint32_t | SR

Detailed Description

Window WATCHDOG.

Definition at line 1256 of file stm32f10x.h.

Field Documentation

__IO uint32_t WWDG_TypeDef::CFR

Definition at line 1259 of file stm32f10x.h.

__IO uint32_t WWDG_TypeDef::CR

Definition at line 1258 of file stm32f10x.h.

__IO uint32_t WWDG_TypeDef::SR

Definition at line 1260 of file stm32f10x.h.

The documentation for this struct was generated from the following file:
  • stm32f10x.h


STM32F10x Standard Peripherals Firmware Library: Peripheral_memory_map

Defines

Peripheral_memory_map

Stm32f10x

Defines

#define | ADC1_BASE (APB2PERIPH_BASE + 0x2400)
#define | ADC2_BASE (APB2PERIPH_BASE + 0x2800)
#define | ADC3_BASE (APB2PERIPH_BASE + 0x3C00)
#define | AFIO_BASE (APB2PERIPH_BASE + 0x0000)
#define | AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
#define | APB1PERIPH_BASE PERIPH_BASE
#define | APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
#define | BKP_BASE (APB1PERIPH_BASE + 0x6C00)
#define | CAN1_BASE (APB1PERIPH_BASE + 0x6400)
#define | CAN2_BASE (APB1PERIPH_BASE + 0x6800)
#define | CEC_BASE (APB1PERIPH_BASE + 0x7800)
#define | CRC_BASE (AHBPERIPH_BASE + 0x3000)
#define | DAC_BASE (APB1PERIPH_BASE + 0x7400)
#define | DBGMCU_BASE ((uint32_t)0xE0042000)
#define | DMA1_BASE (AHBPERIPH_BASE + 0x0000)
#define | DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008)
#define | DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C)
#define | DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030)
#define | DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044)
#define | DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058)
#define | DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C)
#define | DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080)
#define | DMA2_BASE (AHBPERIPH_BASE + 0x0400)
#define | DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408)
#define | DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C)
#define | DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430)
#define | DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444)
#define | DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458)
#define | ETH_BASE (AHBPERIPH_BASE + 0x8000)
#define | ETH_DMA_BASE (ETH_BASE + 0x1000)
#define | ETH_MAC_BASE (ETH_BASE)
#define | ETH_MMC_BASE (ETH_BASE + 0x0100)
#define | ETH_PTP_BASE (ETH_BASE + 0x0700)
#define | EXTI_BASE (APB2PERIPH_BASE + 0x0400)
#define | FLASH_BASE ((uint32_t)0x08000000)
#define | FLASH_R_BASE (AHBPERIPH_BASE + 0x2000)
#define | FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000)
#define | FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104)
#define | FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060)
#define | FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080)
#define | FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0)
#define | FSMC_R_BASE ((uint32_t)0xA0000000)
#define | GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
#define | GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
#define | GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
#define | GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
#define | GPIOE_BASE (APB2PERIPH_BASE + 0x1800)
#define | GPIOF_BASE (APB2PERIPH_BASE + 0x1C00)
#define | GPIOG_BASE (APB2PERIPH_BASE + 0x2000)
#define | I2C1_BASE (APB1PERIPH_BASE + 0x5400)
#define | I2C2_BASE (APB1PERIPH_BASE + 0x5800)
#define | IWDG_BASE (APB1PERIPH_BASE + 0x3000)
#define | OB_BASE ((uint32_t)0x1FFFF800)
#define | PERIPH_BASE ((uint32_t)0x40000000)
#define | PERIPH_BB_BASE ((uint32_t)0x42000000)
#define | PWR_BASE (APB1PERIPH_BASE + 0x7000)
#define | RCC_BASE (AHBPERIPH_BASE + 0x1000)
#define | RTC_BASE (APB1PERIPH_BASE + 0x2800)
#define | SDIO_BASE (PERIPH_BASE + 0x18000)
#define | SPI1_BASE (APB2PERIPH_BASE + 0x3000)
#define | SPI2_BASE (APB1PERIPH_BASE + 0x3800)
#define | SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
#define | SRAM_BASE ((uint32_t)0x20000000)
#define | SRAM_BB_BASE ((uint32_t)0x22000000)
#define | TIM10_BASE (APB2PERIPH_BASE + 0x5000)
#define | TIM11_BASE (APB2PERIPH_BASE + 0x5400)
#define | TIM12_BASE (APB1PERIPH_BASE + 0x1800)
#define | TIM13_BASE (APB1PERIPH_BASE + 0x1C00)
#define | TIM14_BASE (APB1PERIPH_BASE + 0x2000)
#define | TIM15_BASE (APB2PERIPH_BASE + 0x4000)
#define | TIM16_BASE (APB2PERIPH_BASE + 0x4400)
#define | TIM17_BASE (APB2PERIPH_BASE + 0x4800)
#define | TIM1_BASE (APB2PERIPH_BASE + 0x2C00)
#define | TIM2_BASE (APB1PERIPH_BASE + 0x0000)
#define | TIM3_BASE (APB1PERIPH_BASE + 0x0400)
#define | TIM4_BASE (APB1PERIPH_BASE + 0x0800)
#define | TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
#define | TIM6_BASE (APB1PERIPH_BASE + 0x1000)
#define | TIM7_BASE (APB1PERIPH_BASE + 0x1400)
#define | TIM8_BASE (APB2PERIPH_BASE + 0x3400)
#define | TIM9_BASE (APB2PERIPH_BASE + 0x4C00)
#define | UART4_BASE (APB1PERIPH_BASE + 0x4C00)
#define | UART5_BASE (APB1PERIPH_BASE + 0x5000)
#define | USART1_BASE (APB2PERIPH_BASE + 0x3800)
#define | USART2_BASE (APB1PERIPH_BASE + 0x4400)
#define | USART3_BASE (APB1PERIPH_BASE + 0x4800)
#define | WWDG_BASE (APB1PERIPH_BASE + 0x2C00)

Define Documentation

#define ADC1_BASE (APB2PERIPH_BASE + 0x2400)

Definition at line 1322 of file stm32f10x.h.

Referenced by debug().

#define ADC2_BASE (APB2PERIPH_BASE + 0x2800)

Definition at line 1323 of file stm32f10x.h.

Referenced by debug().

#define ADC3_BASE (APB2PERIPH_BASE + 0x3C00)

Definition at line 1328 of file stm32f10x.h.

Referenced by debug().

#define AFIO_BASE (APB2PERIPH_BASE + 0x0000)

Definition at line 1313 of file stm32f10x.h.

Referenced by debug().

#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)

Definition at line 1284 of file stm32f10x.h.

#define APB1PERIPH_BASE PERIPH_BASE

Definition at line 1282 of file stm32f10x.h.

#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)

Definition at line 1283 of file stm32f10x.h.

#define BKP_BASE (APB1PERIPH_BASE + 0x6C00)

Definition at line 1308 of file stm32f10x.h.

Referenced by BKP_ReadBackupRegister(), BKP_WriteBackupRegister(), and debug().

#define CAN1_BASE (APB1PERIPH_BASE + 0x6400)

Definition at line 1306 of file stm32f10x.h.

Referenced by debug().

#define CAN2_BASE (APB1PERIPH_BASE + 0x6800)

Definition at line 1307 of file stm32f10x.h.

#define CEC_BASE (APB1PERIPH_BASE + 0x7800)

Definition at line 1311 of file stm32f10x.h.

Referenced by CEC_GetFlagStatus(), and debug().

#define CRC_BASE (AHBPERIPH_BASE + 0x3000)

Definition at line 1353 of file stm32f10x.h.

Referenced by debug().

#define DAC_BASE (APB1PERIPH_BASE + 0x7400)

Definition at line 1310 of file stm32f10x.h.

Referenced by DAC_GetDataOutputValue(), DAC_SetChannel1Data(), DAC_SetChannel2Data(), DAC_SetDualChannelData(), and debug().

#define DBGMCU_BASE ((uint32_t)0xE0042000)

Debug MCU registers base address

Definition at line 1370 of file stm32f10x.h.

Referenced by debug().

#define DMA1_BASE (AHBPERIPH_BASE + 0x0000)

Definition at line 1338 of file stm32f10x.h.

Referenced by debug().

#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008)

Definition at line 1339 of file stm32f10x.h.

Referenced by debug().

#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C)

Definition at line 1340 of file stm32f10x.h.

Referenced by debug().

#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030)

Definition at line 1341 of file stm32f10x.h.

Referenced by debug().

#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044)

Definition at line 1342 of file stm32f10x.h.

Referenced by debug().

#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058)

Definition at line 1343 of file stm32f10x.h.

Referenced by debug().

#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C)

Definition at line 1344 of file stm32f10x.h.

Referenced by debug().

#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080)

Definition at line 1345 of file stm32f10x.h.

Referenced by debug().

#define DMA2_BASE (AHBPERIPH_BASE + 0x0400)

Definition at line 1346 of file stm32f10x.h.

Referenced by debug().

#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408)

Definition at line 1347 of file stm32f10x.h.

Referenced by debug().

#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C)

Definition at line 1348 of file stm32f10x.h.

Referenced by debug().

#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430)

Definition at line 1349 of file stm32f10x.h.

Referenced by debug().

#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444)

Definition at line 1350 of file stm32f10x.h.

Referenced by debug().

#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458)

Definition at line 1351 of file stm32f10x.h.

Referenced by debug().

#define ETH_BASE (AHBPERIPH_BASE + 0x8000)

Definition at line 1358 of file stm32f10x.h.

#define ETH_DMA_BASE (ETH_BASE + 0x1000)

Definition at line 1362 of file stm32f10x.h.

#define ETH_MAC_BASE (ETH_BASE)

Definition at line 1359 of file stm32f10x.h.

#define ETH_MMC_BASE (ETH_BASE + 0x0100)

Definition at line 1360 of file stm32f10x.h.

#define ETH_PTP_BASE (ETH_BASE + 0x0700)

Definition at line 1361 of file stm32f10x.h.

#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)

Definition at line 1314 of file stm32f10x.h.

Referenced by debug(), and EXTI_Init().

#define FLASH_BASE ((uint32_t)0x08000000)

FLASH base address in the alias region

Definition at line 1272 of file stm32f10x.h.

Referenced by SystemInit().

#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000)

Flash registers base address

Definition at line 1355 of file stm32f10x.h.

Referenced by debug().

#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000)

FSMC Bank1 registers base address

Definition at line 1364 of file stm32f10x.h.

Referenced by debug().

#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104)

FSMC Bank1E registers base address

Definition at line 1365 of file stm32f10x.h.

Referenced by debug().

#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060)

FSMC Bank2 registers base address

Definition at line 1366 of file stm32f10x.h.

Referenced by debug().

#define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080)

FSMC Bank3 registers base address

Definition at line 1367 of file stm32f10x.h.

Referenced by debug().

#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0)

FSMC Bank4 registers base address

Definition at line 1368 of file stm32f10x.h.

Referenced by debug().

#define FSMC_R_BASE ((uint32_t)0xA0000000)

FSMC registers base address Peripheral memory map

Definition at line 1279 of file stm32f10x.h.

#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)

Definition at line 1315 of file stm32f10x.h.

Referenced by debug().

#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)

Definition at line 1316 of file stm32f10x.h.

Referenced by debug().

#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)

Definition at line 1317 of file stm32f10x.h.

Referenced by debug().

#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)

Definition at line 1318 of file stm32f10x.h.

Referenced by debug().

#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)

Definition at line 1319 of file stm32f10x.h.

Referenced by debug().

#define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00)

Definition at line 1320 of file stm32f10x.h.

Referenced by debug().

#define GPIOG_BASE (APB2PERIPH_BASE + 0x2000)

Definition at line 1321 of file stm32f10x.h.

Referenced by debug().

#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)

Definition at line 1304 of file stm32f10x.h.

Referenced by debug().

#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)

Definition at line 1305 of file stm32f10x.h.

Referenced by debug().

#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)

Definition at line 1297 of file stm32f10x.h.

Referenced by debug().

#define OB_BASE ((uint32_t)0x1FFFF800)

Flash Option Bytes base address

Definition at line 1356 of file stm32f10x.h.

Referenced by debug().

#define PERIPH_BASE ((uint32_t)0x40000000)

Peripheral base address in the alias region

Definition at line 1274 of file stm32f10x.h.

#define PERIPH_BB_BASE ((uint32_t)0x42000000)

Peripheral base address in the bit-band region

Definition at line 1277 of file stm32f10x.h.

#define PWR_BASE (APB1PERIPH_BASE + 0x7000)

Definition at line 1309 of file stm32f10x.h.

Referenced by debug().

#define RCC_BASE (AHBPERIPH_BASE + 0x1000)

Definition at line 1352 of file stm32f10x.h.

Referenced by debug().

#define RTC_BASE (APB1PERIPH_BASE + 0x2800)

Definition at line 1295 of file stm32f10x.h.

Referenced by debug().

#define SDIO_BASE (PERIPH_BASE + 0x18000)

Definition at line 1336 of file stm32f10x.h.

Referenced by debug().

#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)

Definition at line 1325 of file stm32f10x.h.

Referenced by debug().

#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)

Definition at line 1298 of file stm32f10x.h.

Referenced by debug(), and I2S_Init().

#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)

Definition at line 1299 of file stm32f10x.h.

Referenced by debug().

#define SRAM_BASE ((uint32_t)0x20000000)

SRAM base address in the alias region

Definition at line 1273 of file stm32f10x.h.

Referenced by SystemInit().

#define SRAM_BB_BASE ((uint32_t)0x22000000)

SRAM base address in the bit-band region

Definition at line 1276 of file stm32f10x.h.

#define TIM10_BASE (APB2PERIPH_BASE + 0x5000)

Definition at line 1333 of file stm32f10x.h.

#define TIM11_BASE (APB2PERIPH_BASE + 0x5400)

Definition at line 1334 of file stm32f10x.h.

#define TIM12_BASE (APB1PERIPH_BASE + 0x1800)

Definition at line 1292 of file stm32f10x.h.

#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00)

Definition at line 1293 of file stm32f10x.h.

#define TIM14_BASE (APB1PERIPH_BASE + 0x2000)

Definition at line 1294 of file stm32f10x.h.

#define TIM15_BASE (APB2PERIPH_BASE + 0x4000)

Definition at line 1329 of file stm32f10x.h.

Referenced by debug().

#define TIM16_BASE (APB2PERIPH_BASE + 0x4400)

Definition at line 1330 of file stm32f10x.h.

Referenced by debug().

#define TIM17_BASE (APB2PERIPH_BASE + 0x4800)

Definition at line 1331 of file stm32f10x.h.

Referenced by debug().

#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00)

Definition at line 1324 of file stm32f10x.h.

Referenced by debug().

#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)

Definition at line 1286 of file stm32f10x.h.

Referenced by debug().

#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)

Definition at line 1287 of file stm32f10x.h.

Referenced by debug().

#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)

Definition at line 1288 of file stm32f10x.h.

Referenced by debug().

#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)

Definition at line 1289 of file stm32f10x.h.

Referenced by debug().

#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)

Definition at line 1290 of file stm32f10x.h.

Referenced by debug().

#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)

Definition at line 1291 of file stm32f10x.h.

Referenced by debug().

#define TIM8_BASE (APB2PERIPH_BASE + 0x3400)

Definition at line 1326 of file stm32f10x.h.

Referenced by debug().

#define TIM9_BASE (APB2PERIPH_BASE + 0x4C00)

Definition at line 1332 of file stm32f10x.h.

#define UART4_BASE (APB1PERIPH_BASE + 0x4C00)

Definition at line 1302 of file stm32f10x.h.

Referenced by debug().

#define UART5_BASE (APB1PERIPH_BASE + 0x5000)

Definition at line 1303 of file stm32f10x.h.

Referenced by debug().

#define USART1_BASE (APB2PERIPH_BASE + 0x3800)

Definition at line 1327 of file stm32f10x.h.

Referenced by debug(), and USART_Init().

#define USART2_BASE (APB1PERIPH_BASE + 0x4400)

Definition at line 1300 of file stm32f10x.h.

Referenced by debug().

#define USART3_BASE (APB1PERIPH_BASE + 0x4800)

Definition at line 1301 of file stm32f10x.h.

Referenced by debug().

#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)

Definition at line 1296 of file stm32f10x.h.

Referenced by debug().


STM32F10x Standard Peripherals Firmware Library: Peripheral_declaration

Defines

Peripheral_declaration

Stm32f10x

Defines

#define | ADC1 ((ADC_TypeDef *) ADC1_BASE)
#define | ADC2 ((ADC_TypeDef *) ADC2_BASE)
#define | ADC3 ((ADC_TypeDef *) ADC3_BASE)
#define | AFIO ((AFIO_TypeDef *) AFIO_BASE)
#define | BKP ((BKP_TypeDef *) BKP_BASE)
#define | CAN1 ((CAN_TypeDef *) CAN1_BASE)
#define | CAN2 ((CAN_TypeDef *) CAN2_BASE)
#define | CEC ((CEC_TypeDef *) CEC_BASE)
#define | CRC ((CRC_TypeDef *) CRC_BASE)
#define | DAC ((DAC_TypeDef *) DAC_BASE)
#define | DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
#define | DMA1 ((DMA_TypeDef *) DMA1_BASE)
#define | DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
#define | DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
#define | DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
#define | DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
#define | DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
#define | DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
#define | DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
#define | DMA2 ((DMA_TypeDef *) DMA2_BASE)
#define | DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
#define | DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
#define | DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
#define | DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
#define | DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
#define | ETH ((ETH_TypeDef *) ETH_BASE)
#define | EXTI ((EXTI_TypeDef *) EXTI_BASE)
#define | FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
#define | FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
#define | FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
#define | FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE)
#define | FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE)
#define | FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
#define | GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
#define | GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
#define | GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
#define | GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
#define | GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
#define | GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
#define | GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
#define | I2C1 ((I2C_TypeDef *) I2C1_BASE)
#define | I2C2 ((I2C_TypeDef *) I2C2_BASE)
#define | IWDG ((IWDG_TypeDef *) IWDG_BASE)
#define | OB ((OB_TypeDef *) OB_BASE)
#define | PWR ((PWR_TypeDef *) PWR_BASE)
#define | RCC ((RCC_TypeDef *) RCC_BASE)
#define | RTC ((RTC_TypeDef *) RTC_BASE)
#define | SDIO ((SDIO_TypeDef *) SDIO_BASE)
#define | SPI1 ((SPI_TypeDef *) SPI1_BASE)
#define | SPI2 ((SPI_TypeDef *) SPI2_BASE)
#define | SPI3 ((SPI_TypeDef *) SPI3_BASE)
#define | TIM1 ((TIM_TypeDef *) TIM1_BASE)
#define | TIM10 ((TIM_TypeDef *) TIM10_BASE)
#define | TIM11 ((TIM_TypeDef *) TIM11_BASE)
#define | TIM12 ((TIM_TypeDef *) TIM12_BASE)
#define | TIM13 ((TIM_TypeDef *) TIM13_BASE)
#define | TIM14 ((TIM_TypeDef *) TIM14_BASE)
#define | TIM15 ((TIM_TypeDef *) TIM15_BASE)
#define | TIM16 ((TIM_TypeDef *) TIM16_BASE)
#define | TIM17 ((TIM_TypeDef *) TIM17_BASE)
#define | TIM2 ((TIM_TypeDef *) TIM2_BASE)
#define | TIM3 ((TIM_TypeDef *) TIM3_BASE)
#define | TIM4 ((TIM_TypeDef *) TIM4_BASE)
#define | TIM5 ((TIM_TypeDef *) TIM5_BASE)
#define | TIM6 ((TIM_TypeDef *) TIM6_BASE)
#define | TIM7 ((TIM_TypeDef *) TIM7_BASE)
#define | TIM8 ((TIM_TypeDef *) TIM8_BASE)
#define | TIM9 ((TIM_TypeDef *) TIM9_BASE)
#define | UART4 ((USART_TypeDef *) UART4_BASE)
#define | UART5 ((USART_TypeDef *) UART5_BASE)
#define | USART1 ((USART_TypeDef *) USART1_BASE)
#define | USART2 ((USART_TypeDef *) USART2_BASE)
#define | USART3 ((USART_TypeDef *) USART3_BASE)
#define | WWDG ((WWDG_TypeDef *) WWDG_BASE)

Define Documentation

#define ADC1 ((ADC_TypeDef *) ADC1_BASE)

Definition at line 1415 of file stm32f10x.h.

Referenced by ADC1_2_IRQHandler(), ADC_DeInit(), ADC_TempSensorVrefintCmd(), and main().

#define ADC2 ((ADC_TypeDef *) ADC2_BASE)

Definition at line 1416 of file stm32f10x.h.

Referenced by ADC1_2_IRQHandler(), ADC_DeInit(), and main().

#define ADC3 ((ADC_TypeDef *) ADC3_BASE)

Definition at line 1421 of file stm32f10x.h.

Referenced by ADC_DeInit(), and main().

#define AFIO ((AFIO_TypeDef *) AFIO_BASE)

Definition at line 1406 of file stm32f10x.h.

Referenced by GPIO_EventOutputConfig(), GPIO_EXTILineConfig(), and GPIO_PinRemapConfig().

#define BKP ((BKP_TypeDef *) BKP_BASE)

Definition at line 1402 of file stm32f10x.h.

Referenced by BKP_ClearFlag(), BKP_ClearITPendingBit(), BKP_RTCOutputConfig(), and BKP_SetRTCCalibrationValue().

#define CAN1 ((CAN_TypeDef *) CAN1_BASE)

Definition at line 1400 of file stm32f10x.h.

Referenced by CAN1_RX0_IRQHandler(), CAN_Config(), CAN_DeInit(), CAN_FilterInit(), CAN_SlaveStartBank(), main(), and USB_LP_CAN1_RX0_IRQHandler().

#define CAN2 ((CAN_TypeDef *) CAN2_BASE)

Definition at line 1401 of file stm32f10x.h.

Referenced by CAN2_RX0_IRQHandler(), CAN_Config(), and main().

#define CEC ((CEC_TypeDef *) CEC_BASE)

Definition at line 1405 of file stm32f10x.h.

Referenced by CEC_ClearFlag(), CEC_ClearITPendingBit(), CEC_Cmd(), CEC_GetITStatus(), CEC_Init(), CEC_IRQHandler(), CEC_OwnAddressConfig(), CEC_ReceiveDataByte(), CEC_SendDataByte(), and CEC_SetPrescaler().

#define CRC ((CRC_TypeDef *) CRC_BASE)

Definition at line 1444 of file stm32f10x.h.

Referenced by CRC_CalcBlockCRC(), CRC_CalcCRC(), CRC_GetCRC(), CRC_GetIDRegister(), CRC_ResetDR(), and CRC_SetIDRegister().

#define DAC ((DAC_TypeDef *) DAC_BASE)

Definition at line 1404 of file stm32f10x.h.

Referenced by DAC_Cmd(), DAC_DMACmd(), DAC_DualSoftwareTriggerCmd(), DAC_Init(), DAC_SoftwareTriggerCmd(), and DAC_WaveGenerationCmd().

#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)

Definition at line 1453 of file stm32f10x.h.

Referenced by DBGMCU_Config(), DBGMCU_GetDEVID(), and DBGMCU_GetREVID().

#define DMA1 ((DMA_TypeDef *) DMA1_BASE)

Definition at line 1429 of file stm32f10x.h.

Referenced by DMA_ClearFlag(), DMA_ClearITPendingBit(), DMA_DeInit(), DMA_GetFlagStatus(), and DMA_GetITStatus().

#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)

Definition at line 1431 of file stm32f10x.h.

Referenced by DMA_DeInit(), and main().

#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)

Definition at line 1432 of file stm32f10x.h.

Referenced by DMA_DeInit().

#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)

Definition at line 1433 of file stm32f10x.h.

Referenced by DMA_DeInit(), and main().

#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)

Definition at line 1434 of file stm32f10x.h.

Referenced by DMA_DeInit(), and main().

#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)

Definition at line 1435 of file stm32f10x.h.

Referenced by DMA_DeInit(), and main().

#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)

Definition at line 1436 of file stm32f10x.h.

Referenced by DMA1_Channel6_IRQHandler(), DMA_DeInit(), and main().

#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)

Definition at line 1437 of file stm32f10x.h.

Referenced by DMA_DeInit().

#define DMA2 ((DMA_TypeDef *) DMA2_BASE)

Definition at line 1430 of file stm32f10x.h.

Referenced by DMA_ClearFlag(), DMA_ClearITPendingBit(), DMA_DeInit(), DMA_GetFlagStatus(), and DMA_GetITStatus().

#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)

Definition at line 1438 of file stm32f10x.h.

Referenced by DMA_DeInit().

#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)

Definition at line 1439 of file stm32f10x.h.

Referenced by DMA_DeInit().

#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)

Definition at line 1440 of file stm32f10x.h.

Referenced by DMA_DeInit(), and main().

#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)

Definition at line 1441 of file stm32f10x.h.

Referenced by DMA_DeInit(), main(), SD_LowLevel_DMA_RxConfig(), and SD_LowLevel_DMA_TxConfig().

#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)

Definition at line 1442 of file stm32f10x.h.

Referenced by DMA_DeInit(), and main().

#define ETH ((ETH_TypeDef *) ETH_BASE)

Definition at line 1447 of file stm32f10x.h.

#define EXTI ((EXTI_TypeDef *) EXTI_BASE)

Definition at line 1407 of file stm32f10x.h.

Referenced by EXTI_ClearFlag(), EXTI_ClearITPendingBit(), EXTI_DeInit(), EXTI_GenerateSWInterrupt(), EXTI_GetFlagStatus(), EXTI_GetITStatus(), and EXTI_Init().

#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)

Definition at line 1445 of file stm32f10x.h.

Referenced by FLASH_ClearFlag(), FLASH_EnableWriteProtection(), FLASH_EraseAllBank1Pages(), FLASH_EraseAllPages(), FLASH_EraseOptionBytes(), FLASH_ErasePage(), FLASH_GetBank1Status(), FLASH_GetFlagStatus(), FLASH_GetPrefetchBufferStatus(), FLASH_GetReadOutProtectionStatus(), FLASH_GetStatus(), FLASH_GetUserOptionByte(), FLASH_GetWriteProtectionOptionByte(), FLASH_HalfCycleAccessCmd(), FLASH_ITConfig(), FLASH_Lock(), FLASH_LockBank1(), FLASH_PrefetchBufferCmd(), FLASH_ProgramHalfWord(), FLASH_ProgramOptionByteData(), FLASH_ProgramWord(), FLASH_ReadOutProtection(), FLASH_SetLatency(), FLASH_Unlock(), FLASH_UnlockBank1(), FLASH_UserOptionByteConfig(), SetSysClockTo56(), and SetSysClockTo72().

#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)

Definition at line 1448 of file stm32f10x.h.

Referenced by FSMC_NORSRAMCmd(), FSMC_NORSRAMDeInit(), and FSMC_NORSRAMInit().

#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)

Definition at line 1449 of file stm32f10x.h.

Referenced by FSMC_NORSRAMDeInit(), and FSMC_NORSRAMInit().

#define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE)

Definition at line 1450 of file stm32f10x.h.

Referenced by FSMC_ClearFlag(), FSMC_ClearITPendingBit(), FSMC_GetECC(), FSMC_GetFlagStatus(), FSMC_GetITStatus(), FSMC_ITConfig(), FSMC_NANDCmd(), FSMC_NANDDeInit(), FSMC_NANDECCCmd(), and FSMC_NANDInit().

#define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE)

Definition at line 1451 of file stm32f10x.h.

Referenced by FSMC_ClearFlag(), FSMC_ClearITPendingBit(), FSMC_GetECC(), FSMC_GetFlagStatus(), FSMC_GetITStatus(), FSMC_ITConfig(), FSMC_NANDCmd(), FSMC_NANDDeInit(), FSMC_NANDECCCmd(), and FSMC_NANDInit().

#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)

Definition at line 1452 of file stm32f10x.h.

Referenced by FSMC_ClearFlag(), FSMC_ClearITPendingBit(), FSMC_GetFlagStatus(), FSMC_GetITStatus(), FSMC_ITConfig(), FSMC_PCCARDCmd(), FSMC_PCCARDDeInit(), and FSMC_PCCARDInit().

#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)

Definition at line 1408 of file stm32f10x.h.

Referenced by EXTI0_Config(), GPIO_DeInit(), LCD_GPIOConfig(), and main().

#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)

Definition at line 1409 of file stm32f10x.h.

Referenced by CAN_Config(), EXTI9_5_Config(), GPIO_DeInit(), LCD_GPIOConfig(), main(), and OneNAND_Init().

#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)

Definition at line 1410 of file stm32f10x.h.

Referenced by ADC1_2_IRQHandler(), GPIO_Configuration(), GPIO_DeInit(), LCD_GPIOConfig(), main(), SD_LowLevel_DeInit(), SD_LowLevel_Init(), and TIM2_IRQHandler().

#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)

Definition at line 1411 of file stm32f10x.h.

Referenced by CAN_Config(), GPIO_DeInit(), LCD_CtrlLinesConfig(), LCD_DeInit(), LCD_GPIOConfig(), main(), NAND_Init(), NOR_GetStatus(), NOR_Init(), OneNAND_Init(), SD_LowLevel_DeInit(), SD_LowLevel_Init(), and SRAM_Init().

#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)

Definition at line 1412 of file stm32f10x.h.

Referenced by GPIO_DeInit(), LCD_CtrlLinesConfig(), LCD_DeInit(), LCD_GPIOConfig(), NAND_Init(), NOR_Init(), OneNAND_Init(), and SRAM_Init().

#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)

Definition at line 1413 of file stm32f10x.h.

Referenced by GPIO_DeInit(), LCD_CtrlLinesConfig(), LCD_DeInit(), NOR_Init(), OneNAND_Init(), and SRAM_Init().

#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)

Definition at line 1414 of file stm32f10x.h.

Referenced by EXTI9_5_Config(), GPIO_DeInit(), LCD_CtrlLinesConfig(), LCD_DeInit(), NAND_Init(), NOR_Init(), OneNAND_Init(), and SRAM_Init().

#define I2C1 ((I2C_TypeDef *) I2C1_BASE)

Definition at line 1398 of file stm32f10x.h.

Referenced by I2C_DeInit(), and main().

#define I2C2 ((I2C_TypeDef *) I2C2_BASE)

Definition at line 1399 of file stm32f10x.h.

Referenced by main().

#define IWDG ((IWDG_TypeDef *) IWDG_BASE)

Definition at line 1391 of file stm32f10x.h.

Referenced by IWDG_Enable(), IWDG_GetFlagStatus(), IWDG_ReloadCounter(), IWDG_SetPrescaler(), IWDG_SetReload(), and IWDG_WriteAccessCmd().

#define OB ((OB_TypeDef *) OB_BASE)

Definition at line 1446 of file stm32f10x.h.

Referenced by FLASH_EnableWriteProtection(), FLASH_EraseOptionBytes(), FLASH_ReadOutProtection(), and FLASH_UserOptionByteConfig().

#define PWR ((PWR_TypeDef *) PWR_BASE)

Definition at line 1403 of file stm32f10x.h.

Referenced by PWR_ClearFlag(), PWR_EnterSTANDBYMode(), PWR_EnterSTOPMode(), PWR_GetFlagStatus(), and PWR_PVDLevelConfig().

#define RCC ((RCC_TypeDef *) RCC_BASE)

Definition at line 1443 of file stm32f10x.h.

Referenced by I2S_Init(), RCC_ADCCLKConfig(), RCC_AdjustHSICalibrationValue(), RCC_AHBPeriphClockCmd(), RCC_APB1PeriphClockCmd(), RCC_APB1PeriphResetCmd(), RCC_APB2PeriphClockCmd(), RCC_APB2PeriphResetCmd(), RCC_ClearFlag(), RCC_DeInit(), RCC_GetClocksFreq(), RCC_GetFlagStatus(), RCC_GetITStatus(), RCC_GetSYSCLKSource(), RCC_HCLKConfig(), RCC_HSEConfig(), RCC_PCLK1Config(), RCC_PCLK2Config(), RCC_PLLConfig(), RCC_RTCCLKConfig(), RCC_SYSCLKConfig(), SetSysClockTo56(), SetSysClockTo72(), SystemCoreClockUpdate(), and SystemInit().

#define RTC ((RTC_TypeDef *) RTC_BASE)

Definition at line 1389 of file stm32f10x.h.

Referenced by RTC_ClearFlag(), RTC_ClearITPendingBit(), RTC_EnterConfigMode(), RTC_ExitConfigMode(), RTC_GetCounter(), RTC_GetDivider(), RTC_GetFlagStatus(), RTC_GetITStatus(), RTC_ITConfig(), RTC_SetAlarm(), RTC_SetCounter(), RTC_SetPrescaler(), RTC_WaitForLastTask(), and RTC_WaitForSynchro().

#define SDIO ((SDIO_TypeDef *) SDIO_BASE)

Definition at line 1428 of file stm32f10x.h.

Referenced by CmdResp1Error(), CmdResp2Error(), CmdResp3Error(), CmdResp6Error(), CmdResp7Error(), FindSCR(), IsCardProgramming(), SD_Erase(), SD_GetTransferState(), SD_ProcessIRQSrc(), SD_ReadBlock(), SD_ReadMultiBlocks(), SD_SendSDStatus(), SD_SendStatus(), SD_StopTransfer(), SD_WriteBlock(), SD_WriteMultiBlocks(), SDIO_ClearFlag(), SDIO_ClearITPendingBit(), SDIO_DataConfig(), SDIO_DeInit(), SDIO_GetCommandResponse(), SDIO_GetDataCounter(), SDIO_GetFIFOCount(), SDIO_GetFlagStatus(), SDIO_GetITStatus(), SDIO_GetPowerState(), SDIO_Init(), SDIO_ITConfig(), SDIO_ReadData(), SDIO_SendCommand(), SDIO_SetPowerState(), and SDIO_WriteData().

#define SPI1 ((SPI_TypeDef *) SPI1_BASE)

Definition at line 1418 of file stm32f10x.h.

Referenced by main(), and SPI_I2S_DeInit().

#define SPI2 ((SPI_TypeDef *) SPI2_BASE)

Definition at line 1392 of file stm32f10x.h.

Referenced by main(), SPI2_IRQHandler(), and SPI_I2S_DeInit().

#define SPI3 ((SPI_TypeDef *) SPI3_BASE)

Definition at line 1393 of file stm32f10x.h.

Referenced by main(), SPI3_IRQHandler(), and SPI_I2S_DeInit().

#define TIM1 ((TIM_TypeDef *) TIM1_BASE)

Definition at line 1417 of file stm32f10x.h.

Referenced by main(), SysTick_Handler(), TI1_Config(), TI2_Config(), TI3_Config(), TI4_Config(), TIM1_TRG_COM_IRQHandler(), TIM_DeInit(), TIM_ICInit(), TIM_OC1Init(), TIM_OC2Init(), TIM_OC3Init(), TIM_OC4Init(), and TIM_TimeBaseInit().

#define TIM10 ((TIM_TypeDef *) TIM10_BASE)

Definition at line 1426 of file stm32f10x.h.

Referenced by main(), and TIM_DeInit().

#define TIM11 ((TIM_TypeDef *) TIM11_BASE)

Definition at line 1427 of file stm32f10x.h.

Referenced by TIM_DeInit().

#define TIM12 ((TIM_TypeDef *) TIM12_BASE)

Definition at line 1386 of file stm32f10x.h.

Referenced by TIM_DeInit().

#define TIM13 ((TIM_TypeDef *) TIM13_BASE)

Definition at line 1387 of file stm32f10x.h.

Referenced by TIM_DeInit().

#define TIM14 ((TIM_TypeDef *) TIM14_BASE)

Definition at line 1388 of file stm32f10x.h.

Referenced by TIM_DeInit().

#define TIM15 ((TIM_TypeDef *) TIM15_BASE)

Definition at line 1422 of file stm32f10x.h.

Referenced by main(), TIM_DeInit(), TIM_OC1Init(), and TIM_TimeBaseInit().

#define TIM16 ((TIM_TypeDef *) TIM16_BASE)

Definition at line 1423 of file stm32f10x.h.

Referenced by TIM_DeInit(), TIM_OC1Init(), and TIM_TimeBaseInit().

#define TIM17 ((TIM_TypeDef *) TIM17_BASE)

Definition at line 1424 of file stm32f10x.h.

Referenced by TIM_DeInit(), TIM_OC1Init(), and TIM_TimeBaseInit().

#define TIM2 ((TIM_TypeDef *) TIM2_BASE)

Definition at line 1380 of file stm32f10x.h.

Referenced by main(), TI1_Config(), TI2_Config(), TI3_Config(), TI4_Config(), TIM2_IRQHandler(), TIM_Config(), TIM_DeInit(), TIM_ICInit(), and TIM_TimeBaseInit().

#define TIM3 ((TIM_TypeDef *) TIM3_BASE)

Definition at line 1381 of file stm32f10x.h.

Referenced by main(), TI1_Config(), TI2_Config(), TI3_Config(), TI4_Config(), TIM3_IRQHandler(), TIM_Config(), TIM_DeInit(), TIM_ICInit(), and TIM_TimeBaseInit().

#define TIM4 ((TIM_TypeDef *) TIM4_BASE)

Definition at line 1382 of file stm32f10x.h.

Referenced by main(), TI1_Config(), TI2_Config(), TI3_Config(), TI4_Config(), TIM4_IRQHandler(), TIM_Config(), TIM_DeInit(), TIM_ICInit(), and TIM_TimeBaseInit().

#define TIM5 ((TIM_TypeDef *) TIM5_BASE)

Definition at line 1383 of file stm32f10x.h.

Referenced by main(), TI1_Config(), TI2_Config(), TI3_Config(), TI4_Config(), TIM5_ConfigForLSI(), TIM5_IRQHandler(), TIM_DeInit(), TIM_ICInit(), and TIM_TimeBaseInit().

#define TIM6 ((TIM_TypeDef *) TIM6_BASE)

Definition at line 1384 of file stm32f10x.h.

Referenced by main(), TIM_DeInit(), and TIM_TimeBaseInit().

#define TIM7 ((TIM_TypeDef *) TIM7_BASE)

Definition at line 1385 of file stm32f10x.h.

Referenced by TIM_DeInit(), and TIM_TimeBaseInit().

#define TIM8 ((TIM_TypeDef *) TIM8_BASE)

Definition at line 1419 of file stm32f10x.h.

Referenced by TI1_Config(), TI2_Config(), TI3_Config(), TI4_Config(), TIM_DeInit(), TIM_ICInit(), TIM_OC1Init(), TIM_OC2Init(), TIM_OC3Init(), TIM_OC4Init(), and TIM_TimeBaseInit().

#define TIM9 ((TIM_TypeDef *) TIM9_BASE)

Definition at line 1425 of file stm32f10x.h.

Referenced by main(), TIM1_BRK_TIM9_IRQHandler(), and TIM_DeInit().

#define UART4 ((USART_TypeDef *) UART4_BASE)

Definition at line 1396 of file stm32f10x.h.

Referenced by USART_DeInit().

#define UART5 ((USART_TypeDef *) UART5_BASE)

Definition at line 1397 of file stm32f10x.h.

Referenced by USART_DeInit().

#define USART1 ((USART_TypeDef *) USART1_BASE)

Definition at line 1420 of file stm32f10x.h.

Referenced by USART_DeInit().

#define USART2 ((USART_TypeDef *) USART2_BASE)

Definition at line 1394 of file stm32f10x.h.

Referenced by main(), USART2_IRQHandler(), and USART_DeInit().

#define USART3 ((USART_TypeDef *) USART3_BASE)

Definition at line 1395 of file stm32f10x.h.

Referenced by USART3_IRQHandler(), and USART_DeInit().

#define WWDG ((WWDG_TypeDef *) WWDG_BASE)

Definition at line 1390 of file stm32f10x.h.

Referenced by WWDG_ClearFlag(), WWDG_Enable(), WWDG_GetFlagStatus(), WWDG_SetCounter(), WWDG_SetPrescaler(), and WWDG_SetWindowValue().


STM32F10x Standard Peripherals Firmware Library: Peripheral_Registers_Bits_Definition

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Peripheral_Registers_Bits_Definition

Exported_constants

Defines

#define

ADC_CR1_AWDCH ((uint32_t)0x0000001F)

#define

ADC_CR1_AWDCH_0 ((uint32_t)0x00000001)

#define

ADC_CR1_AWDCH_1 ((uint32_t)0x00000002)

#define

ADC_CR1_AWDCH_2 ((uint32_t)0x00000004)

#define

ADC_CR1_AWDCH_3 ((uint32_t)0x00000008)

#define

ADC_CR1_AWDCH_4 ((uint32_t)0x00000010)

#define

ADC_CR1_AWDEN ((uint32_t)0x00800000)

#define

ADC_CR1_AWDIE ((uint32_t)0x00000040)

#define

ADC_CR1_AWDSGL ((uint32_t)0x00000200)

#define

ADC_CR1_DISCEN ((uint32_t)0x00000800)

#define

ADC_CR1_DISCNUM ((uint32_t)0x0000E000)

#define

ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000)

#define

ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000)

#define

ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000)

#define

ADC_CR1_DUALMOD ((uint32_t)0x000F0000)

#define

ADC_CR1_DUALMOD_0 ((uint32_t)0x00010000)

#define

ADC_CR1_DUALMOD_1 ((uint32_t)0x00020000)

#define

ADC_CR1_DUALMOD_2 ((uint32_t)0x00040000)

#define

ADC_CR1_DUALMOD_3 ((uint32_t)0x00080000)

#define

ADC_CR1_EOCIE ((uint32_t)0x00000020)

#define

ADC_CR1_JAUTO ((uint32_t)0x00000400)

#define

ADC_CR1_JAWDEN ((uint32_t)0x00400000)

#define

ADC_CR1_JDISCEN ((uint32_t)0x00001000)

#define

ADC_CR1_JEOCIE ((uint32_t)0x00000080)

#define

ADC_CR1_SCAN ((uint32_t)0x00000100)

#define

ADC_CR2_ADON ((uint32_t)0x00000001)

#define

ADC_CR2_ALIGN ((uint32_t)0x00000800)

#define

ADC_CR2_CAL ((uint32_t)0x00000004)

#define

ADC_CR2_CONT ((uint32_t)0x00000002)

#define

ADC_CR2_DMA ((uint32_t)0x00000100)

#define

ADC_CR2_EXTSEL ((uint32_t)0x000E0000)

#define

ADC_CR2_EXTSEL_0 ((uint32_t)0x00020000)

#define

ADC_CR2_EXTSEL_1 ((uint32_t)0x00040000)

#define

ADC_CR2_EXTSEL_2 ((uint32_t)0x00080000)

#define

ADC_CR2_EXTTRIG ((uint32_t)0x00100000)

#define

ADC_CR2_JEXTSEL ((uint32_t)0x00007000)

#define

ADC_CR2_JEXTSEL_0 ((uint32_t)0x00001000)

#define

ADC_CR2_JEXTSEL_1 ((uint32_t)0x00002000)

#define

ADC_CR2_JEXTSEL_2 ((uint32_t)0x00004000)

#define

ADC_CR2_JEXTTRIG ((uint32_t)0x00008000)

#define

ADC_CR2_JSWSTART ((uint32_t)0x00200000)

#define

ADC_CR2_RSTCAL ((uint32_t)0x00000008)

#define

ADC_CR2_SWSTART ((uint32_t)0x00400000)

#define

ADC_CR2_TSVREFE ((uint32_t)0x00800000)

#define

ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000)

#define

ADC_DR_DATA ((uint32_t)0x0000FFFF)

#define

ADC_HTR_HT ((uint16_t)0x0FFF)

#define

ADC_JDR1_JDATA ((uint16_t)0xFFFF)

#define

ADC_JDR2_JDATA ((uint16_t)0xFFFF)

#define

ADC_JDR3_JDATA ((uint16_t)0xFFFF)

#define

ADC_JDR4_JDATA ((uint16_t)0xFFFF)

#define

ADC_JOFR1_JOFFSET1 ((uint16_t)0x0FFF)

#define

ADC_JOFR2_JOFFSET2 ((uint16_t)0x0FFF)

#define

ADC_JOFR3_JOFFSET3 ((uint16_t)0x0FFF)

#define

ADC_JOFR4_JOFFSET4 ((uint16_t)0x0FFF)

#define

ADC_JSQR_JL ((uint32_t)0x00300000)

#define

ADC_JSQR_JL_0 ((uint32_t)0x00100000)

#define

ADC_JSQR_JL_1 ((uint32_t)0x00200000)

#define

ADC_JSQR_JSQ1 ((uint32_t)0x0000001F)

#define

ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001)

#define

ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002)

#define

ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004)

#define

ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008)

#define

ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010)

#define

ADC_JSQR_JSQ2 ((uint32_t)0x000003E0)

#define

ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020)

#define

ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040)

#define

ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080)

#define

ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100)

#define

ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200)

#define

ADC_JSQR_JSQ3 ((uint32_t)0x00007C00)

#define

ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400)

#define

ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800)

#define

ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000)

#define

ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000)

#define

ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000)

#define

ADC_JSQR_JSQ4 ((uint32_t)0x000F8000)

#define

ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000)

#define

ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000)

#define

ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000)

#define

ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000)

#define

ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000)

#define

ADC_LTR_LT ((uint16_t)0x0FFF)

#define

ADC_SMPR1_SMP10 ((uint32_t)0x00000007)

#define

ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001)

#define

ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002)

#define

ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004)

#define

ADC_SMPR1_SMP11 ((uint32_t)0x00000038)

#define

ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008)

#define

ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010)

#define

ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020)

#define

ADC_SMPR1_SMP12 ((uint32_t)0x000001C0)

#define

ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040)

#define

ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080)

#define

ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100)

#define

ADC_SMPR1_SMP13 ((uint32_t)0x00000E00)

#define

ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200)

#define

ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400)

#define

ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800)

#define

ADC_SMPR1_SMP14 ((uint32_t)0x00007000)

#define

ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000)

#define

ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000)

#define

ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000)

#define

ADC_SMPR1_SMP15 ((uint32_t)0x00038000)

#define

ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000)

#define

ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000)

#define

ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000)

#define

ADC_SMPR1_SMP16 ((uint32_t)0x001C0000)

#define

ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000)

#define

ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000)

#define

ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000)

#define

ADC_SMPR1_SMP17 ((uint32_t)0x00E00000)

#define

ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000)

#define

ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000)

#define

ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000)

#define

ADC_SMPR2_SMP0 ((uint32_t)0x00000007)

#define

ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001)

#define

ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002)

#define

ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004)

#define

ADC_SMPR2_SMP1 ((uint32_t)0x00000038)

#define

ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008)

#define

ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010)

#define

ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020)

#define

ADC_SMPR2_SMP2 ((uint32_t)0x000001C0)

#define

ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040)

#define

ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080)

#define

ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100)

#define

ADC_SMPR2_SMP3 ((uint32_t)0x00000E00)

#define

ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200)

#define

ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400)

#define

ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800)

#define

ADC_SMPR2_SMP4 ((uint32_t)0x00007000)

#define

ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000)

#define

ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000)

#define

ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000)

#define

ADC_SMPR2_SMP5 ((uint32_t)0x00038000)

#define

ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000)

#define

ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000)

#define

ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000)

#define

ADC_SMPR2_SMP6 ((uint32_t)0x001C0000)

#define

ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000)

#define

ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000)

#define

ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000)

#define

ADC_SMPR2_SMP7 ((uint32_t)0x00E00000)

#define

ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000)

#define

ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000)

#define

ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000)

#define

ADC_SMPR2_SMP8 ((uint32_t)0x07000000)

#define

ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000)

#define

ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000)

#define

ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000)

#define

ADC_SMPR2_SMP9 ((uint32_t)0x38000000)

#define

ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000)

#define

ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000)

#define

ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000)

#define

ADC_SQR1_L ((uint32_t)0x00F00000)

#define

ADC_SQR1_L_0 ((uint32_t)0x00100000)

#define

ADC_SQR1_L_1 ((uint32_t)0x00200000)

#define

ADC_SQR1_L_2 ((uint32_t)0x00400000)

#define

ADC_SQR1_L_3 ((uint32_t)0x00800000)

#define

ADC_SQR1_SQ13 ((uint32_t)0x0000001F)

#define

ADC_SQR1_SQ13_0 ((uint32_t)0x00000001)

#define

ADC_SQR1_SQ13_1 ((uint32_t)0x00000002)

#define

ADC_SQR1_SQ13_2 ((uint32_t)0x00000004)

#define

ADC_SQR1_SQ13_3 ((uint32_t)0x00000008)

#define

ADC_SQR1_SQ13_4 ((uint32_t)0x00000010)

#define

ADC_SQR1_SQ14 ((uint32_t)0x000003E0)

#define

ADC_SQR1_SQ14_0 ((uint32_t)0x00000020)

#define

ADC_SQR1_SQ14_1 ((uint32_t)0x00000040)

#define

ADC_SQR1_SQ14_2 ((uint32_t)0x00000080)

#define

ADC_SQR1_SQ14_3 ((uint32_t)0x00000100)

#define

ADC_SQR1_SQ14_4 ((uint32_t)0x00000200)

#define

ADC_SQR1_SQ15 ((uint32_t)0x00007C00)

#define

ADC_SQR1_SQ15_0 ((uint32_t)0x00000400)

#define

ADC_SQR1_SQ15_1 ((uint32_t)0x00000800)

#define

ADC_SQR1_SQ15_2 ((uint32_t)0x00001000)

#define

ADC_SQR1_SQ15_3 ((uint32_t)0x00002000)

#define

ADC_SQR1_SQ15_4 ((uint32_t)0x00004000)

#define

ADC_SQR1_SQ16 ((uint32_t)0x000F8000)

#define

ADC_SQR1_SQ16_0 ((uint32_t)0x00008000)

#define

ADC_SQR1_SQ16_1 ((uint32_t)0x00010000)

#define

ADC_SQR1_SQ16_2 ((uint32_t)0x00020000)

#define

ADC_SQR1_SQ16_3 ((uint32_t)0x00040000)

#define

ADC_SQR1_SQ16_4 ((uint32_t)0x00080000)

#define

ADC_SQR2_SQ10 ((uint32_t)0x000F8000)

#define

ADC_SQR2_SQ10_0 ((uint32_t)0x00008000)

#define

ADC_SQR2_SQ10_1 ((uint32_t)0x00010000)

#define

ADC_SQR2_SQ10_2 ((uint32_t)0x00020000)

#define

ADC_SQR2_SQ10_3 ((uint32_t)0x00040000)

#define

ADC_SQR2_SQ10_4 ((uint32_t)0x00080000)

#define

ADC_SQR2_SQ11 ((uint32_t)0x01F00000)

#define

ADC_SQR2_SQ11_0 ((uint32_t)0x00100000)

#define

ADC_SQR2_SQ11_1 ((uint32_t)0x00200000)

#define

ADC_SQR2_SQ11_2 ((uint32_t)0x00400000)

#define

ADC_SQR2_SQ11_3 ((uint32_t)0x00800000)

#define

ADC_SQR2_SQ11_4 ((uint32_t)0x01000000)

#define

ADC_SQR2_SQ12 ((uint32_t)0x3E000000)

#define

ADC_SQR2_SQ12_0 ((uint32_t)0x02000000)

#define

ADC_SQR2_SQ12_1 ((uint32_t)0x04000000)

#define

ADC_SQR2_SQ12_2 ((uint32_t)0x08000000)

#define

ADC_SQR2_SQ12_3 ((uint32_t)0x10000000)

#define

ADC_SQR2_SQ12_4 ((uint32_t)0x20000000)

#define

ADC_SQR2_SQ7 ((uint32_t)0x0000001F)

#define

ADC_SQR2_SQ7_0 ((uint32_t)0x00000001)

#define

ADC_SQR2_SQ7_1 ((uint32_t)0x00000002)

#define

ADC_SQR2_SQ7_2 ((uint32_t)0x00000004)

#define

ADC_SQR2_SQ7_3 ((uint32_t)0x00000008)

#define

ADC_SQR2_SQ7_4 ((uint32_t)0x00000010)

#define

ADC_SQR2_SQ8 ((uint32_t)0x000003E0)

#define

ADC_SQR2_SQ8_0 ((uint32_t)0x00000020)

#define

ADC_SQR2_SQ8_1 ((uint32_t)0x00000040)

#define

ADC_SQR2_SQ8_2 ((uint32_t)0x00000080)

#define

ADC_SQR2_SQ8_3 ((uint32_t)0x00000100)

#define

ADC_SQR2_SQ8_4 ((uint32_t)0x00000200)

#define

ADC_SQR2_SQ9 ((uint32_t)0x00007C00)

#define

ADC_SQR2_SQ9_0 ((uint32_t)0x00000400)

#define

ADC_SQR2_SQ9_1 ((uint32_t)0x00000800)

#define

ADC_SQR2_SQ9_2 ((uint32_t)0x00001000)

#define

ADC_SQR2_SQ9_3 ((uint32_t)0x00002000)

#define

ADC_SQR2_SQ9_4 ((uint32_t)0x00004000)

#define

ADC_SQR3_SQ1 ((uint32_t)0x0000001F)

#define

ADC_SQR3_SQ1_0 ((uint32_t)0x00000001)

#define

ADC_SQR3_SQ1_1 ((uint32_t)0x00000002)

#define

ADC_SQR3_SQ1_2 ((uint32_t)0x00000004)

#define

ADC_SQR3_SQ1_3 ((uint32_t)0x00000008)

#define

ADC_SQR3_SQ1_4 ((uint32_t)0x00000010)

#define

ADC_SQR3_SQ2 ((uint32_t)0x000003E0)

#define

ADC_SQR3_SQ2_0 ((uint32_t)0x00000020)

#define

ADC_SQR3_SQ2_1 ((uint32_t)0x00000040)

#define

ADC_SQR3_SQ2_2 ((uint32_t)0x00000080)

#define

ADC_SQR3_SQ2_3 ((uint32_t)0x00000100)

#define

ADC_SQR3_SQ2_4 ((uint32_t)0x00000200)

#define

ADC_SQR3_SQ3 ((uint32_t)0x00007C00)

#define

ADC_SQR3_SQ3_0 ((uint32_t)0x00000400)

#define

ADC_SQR3_SQ3_1 ((uint32_t)0x00000800)

#define

ADC_SQR3_SQ3_2 ((uint32_t)0x00001000)

#define

ADC_SQR3_SQ3_3 ((uint32_t)0x00002000)

#define

ADC_SQR3_SQ3_4 ((uint32_t)0x00004000)

#define

ADC_SQR3_SQ4 ((uint32_t)0x000F8000)

#define

ADC_SQR3_SQ4_0 ((uint32_t)0x00008000)

#define

ADC_SQR3_SQ4_1 ((uint32_t)0x00010000)

#define

ADC_SQR3_SQ4_2 ((uint32_t)0x00020000)

#define

ADC_SQR3_SQ4_3 ((uint32_t)0x00040000)

#define

ADC_SQR3_SQ4_4 ((uint32_t)0x00080000)

#define

ADC_SQR3_SQ5 ((uint32_t)0x01F00000)

#define

ADC_SQR3_SQ5_0 ((uint32_t)0x00100000)

#define

ADC_SQR3_SQ5_1 ((uint32_t)0x00200000)

#define

ADC_SQR3_SQ5_2 ((uint32_t)0x00400000)

#define

ADC_SQR3_SQ5_3 ((uint32_t)0x00800000)

#define

ADC_SQR3_SQ5_4 ((uint32_t)0x01000000)

#define

ADC_SQR3_SQ6 ((uint32_t)0x3E000000)

#define

ADC_SQR3_SQ6_0 ((uint32_t)0x02000000)

#define

ADC_SQR3_SQ6_1 ((uint32_t)0x04000000)

#define

ADC_SQR3_SQ6_2 ((uint32_t)0x08000000)

#define

ADC_SQR3_SQ6_3 ((uint32_t)0x10000000)

#define

ADC_SQR3_SQ6_4 ((uint32_t)0x20000000)

#define

ADC_SR_AWD ((uint8_t)0x01)

#define

ADC_SR_EOC ((uint8_t)0x02)

#define

ADC_SR_JEOC ((uint8_t)0x04)

#define

ADC_SR_JSTRT ((uint8_t)0x08)

#define

ADC_SR_STRT ((uint8_t)0x10)

#define

AFIO_EVCR_EVOE ((uint8_t)0x80)

#define

AFIO_EVCR_PIN ((uint8_t)0x0F)

#define

AFIO_EVCR_PIN_0 ((uint8_t)0x01)

#define

AFIO_EVCR_PIN_1 ((uint8_t)0x02)

#define

AFIO_EVCR_PIN_2 ((uint8_t)0x04)

#define

AFIO_EVCR_PIN_3 ((uint8_t)0x08)

#define

AFIO_EVCR_PIN_PX0 ((uint8_t)0x00)

#define

AFIO_EVCR_PIN_PX1 ((uint8_t)0x01)

#define

AFIO_EVCR_PIN_PX10 ((uint8_t)0x0A)

#define

AFIO_EVCR_PIN_PX11 ((uint8_t)0x0B)

#define

AFIO_EVCR_PIN_PX12 ((uint8_t)0x0C)

#define

AFIO_EVCR_PIN_PX13 ((uint8_t)0x0D)

#define

AFIO_EVCR_PIN_PX14 ((uint8_t)0x0E)

#define

AFIO_EVCR_PIN_PX15 ((uint8_t)0x0F)

#define

AFIO_EVCR_PIN_PX2 ((uint8_t)0x02)

#define

AFIO_EVCR_PIN_PX3 ((uint8_t)0x03)

#define

AFIO_EVCR_PIN_PX4 ((uint8_t)0x04)

#define

AFIO_EVCR_PIN_PX5 ((uint8_t)0x05)

#define

AFIO_EVCR_PIN_PX6 ((uint8_t)0x06)

#define

AFIO_EVCR_PIN_PX7 ((uint8_t)0x07)

#define

AFIO_EVCR_PIN_PX8 ((uint8_t)0x08)

#define

AFIO_EVCR_PIN_PX9 ((uint8_t)0x09)

#define

AFIO_EVCR_PORT ((uint8_t)0x70)

#define

AFIO_EVCR_PORT_0 ((uint8_t)0x10)

#define

AFIO_EVCR_PORT_1 ((uint8_t)0x20)

#define

AFIO_EVCR_PORT_2 ((uint8_t)0x40)

#define

AFIO_EVCR_PORT_PA ((uint8_t)0x00)

#define

AFIO_EVCR_PORT_PB ((uint8_t)0x10)

#define

AFIO_EVCR_PORT_PC ((uint8_t)0x20)

#define

AFIO_EVCR_PORT_PD ((uint8_t)0x30)

#define

AFIO_EVCR_PORT_PE ((uint8_t)0x40)

#define

AFIO_EXTICR1_EXTI0 ((uint16_t)0x000F)

#define

AFIO_EXTICR1_EXTI0_PA ((uint16_t)0x0000)

#define

AFIO_EXTICR1_EXTI0_PB ((uint16_t)0x0001)

#define

AFIO_EXTICR1_EXTI0_PC ((uint16_t)0x0002)

#define

AFIO_EXTICR1_EXTI0_PD ((uint16_t)0x0003)

#define

AFIO_EXTICR1_EXTI0_PE ((uint16_t)0x0004)

#define

AFIO_EXTICR1_EXTI0_PF ((uint16_t)0x0005)

#define

AFIO_EXTICR1_EXTI0_PG ((uint16_t)0x0006)

#define

AFIO_EXTICR1_EXTI1 ((uint16_t)0x00F0)

#define

AFIO_EXTICR1_EXTI1_PA ((uint16_t)0x0000)

#define

AFIO_EXTICR1_EXTI1_PB ((uint16_t)0x0010)

#define

AFIO_EXTICR1_EXTI1_PC ((uint16_t)0x0020)

#define

AFIO_EXTICR1_EXTI1_PD ((uint16_t)0x0030)

#define

AFIO_EXTICR1_EXTI1_PE ((uint16_t)0x0040)

#define

AFIO_EXTICR1_EXTI1_PF ((uint16_t)0x0050)

#define

AFIO_EXTICR1_EXTI1_PG ((uint16_t)0x0060)

#define

AFIO_EXTICR1_EXTI2 ((uint16_t)0x0F00)

#define

AFIO_EXTICR1_EXTI2_PA ((uint16_t)0x0000)

#define

AFIO_EXTICR1_EXTI2_PB ((uint16_t)0x0100)

#define

AFIO_EXTICR1_EXTI2_PC ((uint16_t)0x0200)

#define

AFIO_EXTICR1_EXTI2_PD ((uint16_t)0x0300)

#define

AFIO_EXTICR1_EXTI2_PE ((uint16_t)0x0400)

#define

AFIO_EXTICR1_EXTI2_PF ((uint16_t)0x0500)

#define

AFIO_EXTICR1_EXTI2_PG ((uint16_t)0x0600)

#define

AFIO_EXTICR1_EXTI3 ((uint16_t)0xF000)

#define

AFIO_EXTICR1_EXTI3_PA ((uint16_t)0x0000)

#define

AFIO_EXTICR1_EXTI3_PB ((uint16_t)0x1000)

#define

AFIO_EXTICR1_EXTI3_PC ((uint16_t)0x2000)

#define

AFIO_EXTICR1_EXTI3_PD ((uint16_t)0x3000)

#define

AFIO_EXTICR1_EXTI3_PE ((uint16_t)0x4000)

#define

AFIO_EXTICR1_EXTI3_PF ((uint16_t)0x5000)

#define

AFIO_EXTICR1_EXTI3_PG ((uint16_t)0x6000)

#define

AFIO_EXTICR2_EXTI4 ((uint16_t)0x000F)

#define

AFIO_EXTICR2_EXTI4_PA ((uint16_t)0x0000)

#define

AFIO_EXTICR2_EXTI4_PB ((uint16_t)0x0001)

#define

AFIO_EXTICR2_EXTI4_PC ((uint16_t)0x0002)

#define

AFIO_EXTICR2_EXTI4_PD ((uint16_t)0x0003)

#define

AFIO_EXTICR2_EXTI4_PE ((uint16_t)0x0004)

#define

AFIO_EXTICR2_EXTI4_PF ((uint16_t)0x0005)

#define

AFIO_EXTICR2_EXTI4_PG ((uint16_t)0x0006)

#define

AFIO_EXTICR2_EXTI5 ((uint16_t)0x00F0)

#define

AFIO_EXTICR2_EXTI5_PA ((uint16_t)0x0000)

#define

AFIO_EXTICR2_EXTI5_PB ((uint16_t)0x0010)

#define

AFIO_EXTICR2_EXTI5_PC ((uint16_t)0x0020)

#define

AFIO_EXTICR2_EXTI5_PD ((uint16_t)0x0030)

#define

AFIO_EXTICR2_EXTI5_PE ((uint16_t)0x0040)

#define

AFIO_EXTICR2_EXTI5_PF ((uint16_t)0x0050)

#define

AFIO_EXTICR2_EXTI5_PG ((uint16_t)0x0060)

#define

AFIO_EXTICR2_EXTI6 ((uint16_t)0x0F00)

#define

AFIO_EXTICR2_EXTI6_PA ((uint16_t)0x0000)

#define

AFIO_EXTICR2_EXTI6_PB ((uint16_t)0x0100)

#define

AFIO_EXTICR2_EXTI6_PC ((uint16_t)0x0200)

#define

AFIO_EXTICR2_EXTI6_PD ((uint16_t)0x0300)

#define

AFIO_EXTICR2_EXTI6_PE ((uint16_t)0x0400)

#define

AFIO_EXTICR2_EXTI6_PF ((uint16_t)0x0500)

#define

AFIO_EXTICR2_EXTI6_PG ((uint16_t)0x0600)

#define

AFIO_EXTICR2_EXTI7 ((uint16_t)0xF000)

#define

AFIO_EXTICR2_EXTI7_PA ((uint16_t)0x0000)

#define

AFIO_EXTICR2_EXTI7_PB ((uint16_t)0x1000)

#define

AFIO_EXTICR2_EXTI7_PC ((uint16_t)0x2000)

#define

AFIO_EXTICR2_EXTI7_PD ((uint16_t)0x3000)

#define

AFIO_EXTICR2_EXTI7_PE ((uint16_t)0x4000)

#define

AFIO_EXTICR2_EXTI7_PF ((uint16_t)0x5000)

#define

AFIO_EXTICR2_EXTI7_PG ((uint16_t)0x6000)

#define

AFIO_EXTICR3_EXTI10 ((uint16_t)0x0F00)

#define

AFIO_EXTICR3_EXTI10_PA ((uint16_t)0x0000)

#define

AFIO_EXTICR3_EXTI10_PB ((uint16_t)0x0100)

#define

AFIO_EXTICR3_EXTI10_PC ((uint16_t)0x0200)

#define

AFIO_EXTICR3_EXTI10_PD ((uint16_t)0x0300)

#define

AFIO_EXTICR3_EXTI10_PE ((uint16_t)0x0400)

#define

AFIO_EXTICR3_EXTI10_PF ((uint16_t)0x0500)

#define

AFIO_EXTICR3_EXTI10_PG ((uint16_t)0x0600)

#define

AFIO_EXTICR3_EXTI11 ((uint16_t)0xF000)

#define

AFIO_EXTICR3_EXTI11_PA ((uint16_t)0x0000)

#define

AFIO_EXTICR3_EXTI11_PB ((uint16_t)0x1000)

#define

AFIO_EXTICR3_EXTI11_PC ((uint16_t)0x2000)

#define

AFIO_EXTICR3_EXTI11_PD ((uint16_t)0x3000)

#define

AFIO_EXTICR3_EXTI11_PE ((uint16_t)0x4000)

#define

AFIO_EXTICR3_EXTI11_PF ((uint16_t)0x5000)

#define

AFIO_EXTICR3_EXTI11_PG ((uint16_t)0x6000)

#define

AFIO_EXTICR3_EXTI8 ((uint16_t)0x000F)

#define

AFIO_EXTICR3_EXTI8_PA ((uint16_t)0x0000)

#define

AFIO_EXTICR3_EXTI8_PB ((uint16_t)0x0001)

#define

AFIO_EXTICR3_EXTI8_PC ((uint16_t)0x0002)

#define

AFIO_EXTICR3_EXTI8_PD ((uint16_t)0x0003)

#define

AFIO_EXTICR3_EXTI8_PE ((uint16_t)0x0004)

#define

AFIO_EXTICR3_EXTI8_PF ((uint16_t)0x0005)

#define

AFIO_EXTICR3_EXTI8_PG ((uint16_t)0x0006)

#define

AFIO_EXTICR3_EXTI9 ((uint16_t)0x00F0)

#define

AFIO_EXTICR3_EXTI9_PA ((uint16_t)0x0000)

#define

AFIO_EXTICR3_EXTI9_PB ((uint16_t)0x0010)

#define

AFIO_EXTICR3_EXTI9_PC ((uint16_t)0x0020)

#define

AFIO_EXTICR3_EXTI9_PD ((uint16_t)0x0030)

#define

AFIO_EXTICR3_EXTI9_PE ((uint16_t)0x0040)

#define

AFIO_EXTICR3_EXTI9_PF ((uint16_t)0x0050)

#define

AFIO_EXTICR3_EXTI9_PG ((uint16_t)0x0060)

#define

AFIO_EXTICR4_EXTI12 ((uint16_t)0x000F)

#define

AFIO_EXTICR4_EXTI12_PA ((uint16_t)0x0000)

#define

AFIO_EXTICR4_EXTI12_PB ((uint16_t)0x0001)

#define

AFIO_EXTICR4_EXTI12_PC ((uint16_t)0x0002)

#define

AFIO_EXTICR4_EXTI12_PD ((uint16_t)0x0003)

#define

AFIO_EXTICR4_EXTI12_PE ((uint16_t)0x0004)

#define

AFIO_EXTICR4_EXTI12_PF ((uint16_t)0x0005)

#define

AFIO_EXTICR4_EXTI12_PG ((uint16_t)0x0006)

#define

AFIO_EXTICR4_EXTI13 ((uint16_t)0x00F0)

#define

AFIO_EXTICR4_EXTI13_PA ((uint16_t)0x0000)

#define

AFIO_EXTICR4_EXTI13_PB ((uint16_t)0x0010)

#define

AFIO_EXTICR4_EXTI13_PC ((uint16_t)0x0020)

#define

AFIO_EXTICR4_EXTI13_PD ((uint16_t)0x0030)

#define

AFIO_EXTICR4_EXTI13_PE ((uint16_t)0x0040)

#define

AFIO_EXTICR4_EXTI13_PF ((uint16_t)0x0050)

#define

AFIO_EXTICR4_EXTI13_PG ((uint16_t)0x0060)

#define

AFIO_EXTICR4_EXTI14 ((uint16_t)0x0F00)

#define

AFIO_EXTICR4_EXTI14_PA ((uint16_t)0x0000)

#define

AFIO_EXTICR4_EXTI14_PB ((uint16_t)0x0100)

#define

AFIO_EXTICR4_EXTI14_PC ((uint16_t)0x0200)

#define

AFIO_EXTICR4_EXTI14_PD ((uint16_t)0x0300)

#define

AFIO_EXTICR4_EXTI14_PE ((uint16_t)0x0400)

#define

AFIO_EXTICR4_EXTI14_PF ((uint16_t)0x0500)

#define

AFIO_EXTICR4_EXTI14_PG ((uint16_t)0x0600)

#define

AFIO_EXTICR4_EXTI15 ((uint16_t)0xF000)

#define

AFIO_EXTICR4_EXTI15_PA ((uint16_t)0x0000)

#define

AFIO_EXTICR4_EXTI15_PB ((uint16_t)0x1000)

#define

AFIO_EXTICR4_EXTI15_PC ((uint16_t)0x2000)

#define

AFIO_EXTICR4_EXTI15_PD ((uint16_t)0x3000)

#define

AFIO_EXTICR4_EXTI15_PE ((uint16_t)0x4000)

#define

AFIO_EXTICR4_EXTI15_PF ((uint16_t)0x5000)

#define

AFIO_EXTICR4_EXTI15_PG ((uint16_t)0x6000)

#define

AFIO_MAPR_ADC1_ETRGINJ_REMAP ((uint32_t)0x00020000)

#define

AFIO_MAPR_ADC1_ETRGREG_REMAP ((uint32_t)0x00040000)

#define

AFIO_MAPR_ADC2_ETRGINJ_REMAP ((uint32_t)0x00080000)

#define

AFIO_MAPR_ADC2_ETRGREG_REMAP ((uint32_t)0x00100000)

#define

AFIO_MAPR_CAN_REMAP ((uint32_t)0x00006000)

#define

AFIO_MAPR_CAN_REMAP_0 ((uint32_t)0x00002000)

#define

AFIO_MAPR_CAN_REMAP_1 ((uint32_t)0x00004000)

#define

AFIO_MAPR_CAN_REMAP_REMAP1 ((uint32_t)0x00000000)

#define

AFIO_MAPR_CAN_REMAP_REMAP2 ((uint32_t)0x00004000)

#define

AFIO_MAPR_CAN_REMAP_REMAP3 ((uint32_t)0x00006000)

#define

AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002)

#define

AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000)

#define

AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001)

#define

AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000)

#define

AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000)

#define

AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000)

#define

AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000)

#define

AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000)

#define

AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000)

#define

AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000)

#define

AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000)

#define

AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0)

#define

AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040)

#define

AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080)

#define

AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0)

#define

AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000)

#define

AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040)

#define

AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300)

#define

AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100)

#define

AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200)

#define

AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300)

#define

AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000)

#define

AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100)

#define

AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200)

#define

AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00)

#define

AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400)

#define

AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800)

#define

AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00)

#define

AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000)

#define

AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800)

#define

AFIO_MAPR_TIM4_REMAP ((uint32_t)0x00001000)

#define

AFIO_MAPR_TIM5CH4_IREMAP ((uint32_t)0x00010000)

#define

AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004)

#define

AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008)

#define

AFIO_MAPR_USART3_REMAP ((uint32_t)0x00000030)

#define

AFIO_MAPR_USART3_REMAP_0 ((uint32_t)0x00000010)

#define

AFIO_MAPR_USART3_REMAP_1 ((uint32_t)0x00000020)

#define

AFIO_MAPR_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030)

#define

AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000)

#define

AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010)

#define

BKP_CR_TPAL ((uint8_t)0x02)

#define

BKP_CR_TPE ((uint8_t)0x01)

#define

BKP_CSR_CTE ((uint16_t)0x0001)

#define

BKP_CSR_CTI ((uint16_t)0x0002)

#define

BKP_CSR_TEF ((uint16_t)0x0100)

#define

BKP_CSR_TIF ((uint16_t)0x0200)

#define

BKP_CSR_TPIE ((uint16_t)0x0004)

#define

BKP_DR10_D ((uint16_t)0xFFFF)

#define

BKP_DR11_D ((uint16_t)0xFFFF)

#define

BKP_DR12_D ((uint16_t)0xFFFF)

#define

BKP_DR13_D ((uint16_t)0xFFFF)

#define

BKP_DR14_D ((uint16_t)0xFFFF)

#define

BKP_DR15_D ((uint16_t)0xFFFF)

#define

BKP_DR16_D ((uint16_t)0xFFFF)

#define

BKP_DR17_D ((uint16_t)0xFFFF)

#define

BKP_DR18_D ((uint16_t)0xFFFF)

#define

BKP_DR19_D ((uint16_t)0xFFFF)

#define

BKP_DR1_D ((uint16_t)0xFFFF)

#define

BKP_DR20_D ((uint16_t)0xFFFF)

#define

BKP_DR21_D ((uint16_t)0xFFFF)

#define

BKP_DR22_D ((uint16_t)0xFFFF)

#define

BKP_DR23_D ((uint16_t)0xFFFF)

#define

BKP_DR24_D ((uint16_t)0xFFFF)

#define

BKP_DR25_D ((uint16_t)0xFFFF)

#define

BKP_DR26_D ((uint16_t)0xFFFF)

#define

BKP_DR27_D ((uint16_t)0xFFFF)

#define

BKP_DR28_D ((uint16_t)0xFFFF)

#define

BKP_DR29_D ((uint16_t)0xFFFF)

#define

BKP_DR2_D ((uint16_t)0xFFFF)

#define

BKP_DR30_D ((uint16_t)0xFFFF)

#define

BKP_DR31_D ((uint16_t)0xFFFF)

#define

BKP_DR32_D ((uint16_t)0xFFFF)

#define

BKP_DR33_D ((uint16_t)0xFFFF)

#define

BKP_DR34_D ((uint16_t)0xFFFF)

#define

BKP_DR35_D ((uint16_t)0xFFFF)

#define

BKP_DR36_D ((uint16_t)0xFFFF)

#define

BKP_DR37_D ((uint16_t)0xFFFF)

#define

BKP_DR38_D ((uint16_t)0xFFFF)

#define

BKP_DR39_D ((uint16_t)0xFFFF)

#define

BKP_DR3_D ((uint16_t)0xFFFF)

#define

BKP_DR40_D ((uint16_t)0xFFFF)

#define

BKP_DR41_D ((uint16_t)0xFFFF)

#define

BKP_DR42_D ((uint16_t)0xFFFF)

#define

BKP_DR4_D ((uint16_t)0xFFFF)

#define

BKP_DR5_D ((uint16_t)0xFFFF)

#define

BKP_DR6_D ((uint16_t)0xFFFF)

#define

BKP_DR7_D ((uint16_t)0xFFFF)

#define

BKP_DR8_D ((uint16_t)0xFFFF)

#define

BKP_DR9_D ((uint16_t)0xFFFF)

#define

BKP_RTCCR_ASOE ((uint16_t)0x0100)

#define

BKP_RTCCR_ASOS ((uint16_t)0x0200)

#define

BKP_RTCCR_CAL ((uint16_t)0x007F)

#define

BKP_RTCCR_CCO ((uint16_t)0x0080)

#define

CAN_BTR_BRP ((uint32_t)0x000003FF)

#define

CAN_BTR_LBKM ((uint32_t)0x40000000)

#define

CAN_BTR_SILM ((uint32_t)0x80000000)

#define

CAN_BTR_SJW ((uint32_t)0x03000000)

#define

CAN_BTR_TS1 ((uint32_t)0x000F0000)

#define

CAN_BTR_TS2 ((uint32_t)0x00700000)

#define

CAN_ESR_BOFF ((uint32_t)0x00000004)

#define

CAN_ESR_EPVF ((uint32_t)0x00000002)

#define

CAN_ESR_EWGF ((uint32_t)0x00000001)

#define

CAN_ESR_LEC ((uint32_t)0x00000070)

#define

CAN_ESR_LEC_0 ((uint32_t)0x00000010)

#define

CAN_ESR_LEC_1 ((uint32_t)0x00000020)

#define

CAN_ESR_LEC_2 ((uint32_t)0x00000040)

#define

CAN_ESR_REC ((uint32_t)0xFF000000)

#define

CAN_ESR_TEC ((uint32_t)0x00FF0000)

#define

CAN_F0R1_FB0 ((uint32_t)0x00000001)

#define

CAN_F0R1_FB1 ((uint32_t)0x00000002)

#define

CAN_F0R1_FB10 ((uint32_t)0x00000400)

#define

CAN_F0R1_FB11 ((uint32_t)0x00000800)

#define

CAN_F0R1_FB12 ((uint32_t)0x00001000)

#define

CAN_F0R1_FB13 ((uint32_t)0x00002000)

#define

CAN_F0R1_FB14 ((uint32_t)0x00004000)

#define

CAN_F0R1_FB15 ((uint32_t)0x00008000)

#define

CAN_F0R1_FB16 ((uint32_t)0x00010000)

#define

CAN_F0R1_FB17 ((uint32_t)0x00020000)

#define

CAN_F0R1_FB18 ((uint32_t)0x00040000)

#define

CAN_F0R1_FB19 ((uint32_t)0x00080000)

#define

CAN_F0R1_FB2 ((uint32_t)0x00000004)

#define

CAN_F0R1_FB20 ((uint32_t)0x00100000)

#define

CAN_F0R1_FB21 ((uint32_t)0x00200000)

#define

CAN_F0R1_FB22 ((uint32_t)0x00400000)

#define

CAN_F0R1_FB23 ((uint32_t)0x00800000)

#define

CAN_F0R1_FB24 ((uint32_t)0x01000000)

#define

CAN_F0R1_FB25 ((uint32_t)0x02000000)

#define

CAN_F0R1_FB26 ((uint32_t)0x04000000)

#define

CAN_F0R1_FB27 ((uint32_t)0x08000000)

#define

CAN_F0R1_FB28 ((uint32_t)0x10000000)

#define

CAN_F0R1_FB29 ((uint32_t)0x20000000)

#define

CAN_F0R1_FB3 ((uint32_t)0x00000008)

#define

CAN_F0R1_FB30 ((uint32_t)0x40000000)

#define

CAN_F0R1_FB31 ((uint32_t)0x80000000)

#define

CAN_F0R1_FB4 ((uint32_t)0x00000010)

#define

CAN_F0R1_FB5 ((uint32_t)0x00000020)

#define

CAN_F0R1_FB6 ((uint32_t)0x00000040)

#define

CAN_F0R1_FB7 ((uint32_t)0x00000080)

#define

CAN_F0R1_FB8 ((uint32_t)0x00000100)

#define

CAN_F0R1_FB9 ((uint32_t)0x00000200)

#define

CAN_F0R2_FB0 ((uint32_t)0x00000001)

#define

CAN_F0R2_FB1 ((uint32_t)0x00000002)

#define

CAN_F0R2_FB10 ((uint32_t)0x00000400)

#define

CAN_F0R2_FB11 ((uint32_t)0x00000800)

#define

CAN_F0R2_FB12 ((uint32_t)0x00001000)

#define

CAN_F0R2_FB13 ((uint32_t)0x00002000)

#define

CAN_F0R2_FB14 ((uint32_t)0x00004000)

#define

CAN_F0R2_FB15 ((uint32_t)0x00008000)

#define

CAN_F0R2_FB16 ((uint32_t)0x00010000)

#define

CAN_F0R2_FB17 ((uint32_t)0x00020000)

#define

CAN_F0R2_FB18 ((uint32_t)0x00040000)

#define

CAN_F0R2_FB19 ((uint32_t)0x00080000)

#define

CAN_F0R2_FB2 ((uint32_t)0x00000004)

#define

CAN_F0R2_FB20 ((uint32_t)0x00100000)

#define

CAN_F0R2_FB21 ((uint32_t)0x00200000)

#define

CAN_F0R2_FB22 ((uint32_t)0x00400000)

#define

CAN_F0R2_FB23 ((uint32_t)0x00800000)

#define

CAN_F0R2_FB24 ((uint32_t)0x01000000)

#define

CAN_F0R2_FB25 ((uint32_t)0x02000000)

#define

CAN_F0R2_FB26 ((uint32_t)0x04000000)

#define

CAN_F0R2_FB27 ((uint32_t)0x08000000)

#define

CAN_F0R2_FB28 ((uint32_t)0x10000000)

#define

CAN_F0R2_FB29 ((uint32_t)0x20000000)

#define

CAN_F0R2_FB3 ((uint32_t)0x00000008)

#define

CAN_F0R2_FB30 ((uint32_t)0x40000000)

#define

CAN_F0R2_FB31 ((uint32_t)0x80000000)

#define

CAN_F0R2_FB4 ((uint32_t)0x00000010)

#define

CAN_F0R2_FB5 ((uint32_t)0x00000020)

#define

CAN_F0R2_FB6 ((uint32_t)0x00000040)

#define

CAN_F0R2_FB7 ((uint32_t)0x00000080)

#define

CAN_F0R2_FB8 ((uint32_t)0x00000100)

#define

CAN_F0R2_FB9 ((uint32_t)0x00000200)

#define

CAN_F10R1_FB0 ((uint32_t)0x00000001)

#define

CAN_F10R1_FB1 ((uint32_t)0x00000002)

#define

CAN_F10R1_FB10 ((uint32_t)0x00000400)

#define

CAN_F10R1_FB11 ((uint32_t)0x00000800)

#define

CAN_F10R1_FB12 ((uint32_t)0x00001000)

#define

CAN_F10R1_FB13 ((uint32_t)0x00002000)

#define

CAN_F10R1_FB14 ((uint32_t)0x00004000)

#define

CAN_F10R1_FB15 ((uint32_t)0x00008000)

#define

CAN_F10R1_FB16 ((uint32_t)0x00010000)

#define

CAN_F10R1_FB17 ((uint32_t)0x00020000)

#define

CAN_F10R1_FB18 ((uint32_t)0x00040000)

#define

CAN_F10R1_FB19 ((uint32_t)0x00080000)

#define

CAN_F10R1_FB2 ((uint32_t)0x00000004)

#define

CAN_F10R1_FB20 ((uint32_t)0x00100000)

#define

CAN_F10R1_FB21 ((uint32_t)0x00200000)

#define

CAN_F10R1_FB22 ((uint32_t)0x00400000)

#define

CAN_F10R1_FB23 ((uint32_t)0x00800000)

#define

CAN_F10R1_FB24 ((uint32_t)0x01000000)

#define

CAN_F10R1_FB25 ((uint32_t)0x02000000)

#define

CAN_F10R1_FB26 ((uint32_t)0x04000000)

#define

CAN_F10R1_FB27 ((uint32_t)0x08000000)

#define

CAN_F10R1_FB28 ((uint32_t)0x10000000)

#define

CAN_F10R1_FB29 ((uint32_t)0x20000000)

#define

CAN_F10R1_FB3 ((uint32_t)0x00000008)

#define

CAN_F10R1_FB30 ((uint32_t)0x40000000)

#define

CAN_F10R1_FB31 ((uint32_t)0x80000000)

#define

CAN_F10R1_FB4 ((uint32_t)0x00000010)

#define

CAN_F10R1_FB5 ((uint32_t)0x00000020)

#define

CAN_F10R1_FB6 ((uint32_t)0x00000040)

#define

CAN_F10R1_FB7 ((uint32_t)0x00000080)

#define

CAN_F10R1_FB8 ((uint32_t)0x00000100)

#define

CAN_F10R1_FB9 ((uint32_t)0x00000200)

#define

CAN_F10R2_FB0 ((uint32_t)0x00000001)

#define

CAN_F10R2_FB1 ((uint32_t)0x00000002)

#define

CAN_F10R2_FB10 ((uint32_t)0x00000400)

#define

CAN_F10R2_FB11 ((uint32_t)0x00000800)

#define

CAN_F10R2_FB12 ((uint32_t)0x00001000)

#define

CAN_F10R2_FB13 ((uint32_t)0x00002000)

#define

CAN_F10R2_FB14 ((uint32_t)0x00004000)

#define

CAN_F10R2_FB15 ((uint32_t)0x00008000)

#define

CAN_F10R2_FB16 ((uint32_t)0x00010000)

#define

CAN_F10R2_FB17 ((uint32_t)0x00020000)

#define

CAN_F10R2_FB18 ((uint32_t)0x00040000)

#define

CAN_F10R2_FB19 ((uint32_t)0x00080000)

#define

CAN_F10R2_FB2 ((uint32_t)0x00000004)

#define

CAN_F10R2_FB20 ((uint32_t)0x00100000)

#define

CAN_F10R2_FB21 ((uint32_t)0x00200000)

#define

CAN_F10R2_FB22 ((uint32_t)0x00400000)

#define

CAN_F10R2_FB23 ((uint32_t)0x00800000)

#define

CAN_F10R2_FB24 ((uint32_t)0x01000000)

#define

CAN_F10R2_FB25 ((uint32_t)0x02000000)

#define

CAN_F10R2_FB26 ((uint32_t)0x04000000)

#define

CAN_F10R2_FB27 ((uint32_t)0x08000000)

#define

CAN_F10R2_FB28 ((uint32_t)0x10000000)

#define

CAN_F10R2_FB29 ((uint32_t)0x20000000)

#define

CAN_F10R2_FB3 ((uint32_t)0x00000008)

#define

CAN_F10R2_FB30 ((uint32_t)0x40000000)

#define

CAN_F10R2_FB31 ((uint32_t)0x80000000)

#define

CAN_F10R2_FB4 ((uint32_t)0x00000010)

#define

CAN_F10R2_FB5 ((uint32_t)0x00000020)

#define

CAN_F10R2_FB6 ((uint32_t)0x00000040)

#define

CAN_F10R2_FB7 ((uint32_t)0x00000080)

#define

CAN_F10R2_FB8 ((uint32_t)0x00000100)

#define

CAN_F10R2_FB9 ((uint32_t)0x00000200)

#define

CAN_F11R1_FB0 ((uint32_t)0x00000001)

#define

CAN_F11R1_FB1 ((uint32_t)0x00000002)

#define

CAN_F11R1_FB10 ((uint32_t)0x00000400)

#define

CAN_F11R1_FB11 ((uint32_t)0x00000800)

#define

CAN_F11R1_FB12 ((uint32_t)0x00001000)

#define

CAN_F11R1_FB13 ((uint32_t)0x00002000)

#define

CAN_F11R1_FB14 ((uint32_t)0x00004000)

#define

CAN_F11R1_FB15 ((uint32_t)0x00008000)

#define

CAN_F11R1_FB16 ((uint32_t)0x00010000)

#define

CAN_F11R1_FB17 ((uint32_t)0x00020000)

#define

CAN_F11R1_FB18 ((uint32_t)0x00040000)

#define

CAN_F11R1_FB19 ((uint32_t)0x00080000)

#define

CAN_F11R1_FB2 ((uint32_t)0x00000004)

#define

CAN_F11R1_FB20 ((uint32_t)0x00100000)

#define

CAN_F11R1_FB21 ((uint32_t)0x00200000)

#define

CAN_F11R1_FB22 ((uint32_t)0x00400000)

#define

CAN_F11R1_FB23 ((uint32_t)0x00800000)

#define

CAN_F11R1_FB24 ((uint32_t)0x01000000)

#define

CAN_F11R1_FB25 ((uint32_t)0x02000000)

#define

CAN_F11R1_FB26 ((uint32_t)0x04000000)

#define

CAN_F11R1_FB27 ((uint32_t)0x08000000)

#define

CAN_F11R1_FB28 ((uint32_t)0x10000000)

#define

CAN_F11R1_FB29 ((uint32_t)0x20000000)

#define

CAN_F11R1_FB3 ((uint32_t)0x00000008)

#define

CAN_F11R1_FB30 ((uint32_t)0x40000000)

#define

CAN_F11R1_FB31 ((uint32_t)0x80000000)

#define

CAN_F11R1_FB4 ((uint32_t)0x00000010)

#define

CAN_F11R1_FB5 ((uint32_t)0x00000020)

#define

CAN_F11R1_FB6 ((uint32_t)0x00000040)

#define

CAN_F11R1_FB7 ((uint32_t)0x00000080)

#define

CAN_F11R1_FB8 ((uint32_t)0x00000100)

#define

CAN_F11R1_FB9 ((uint32_t)0x00000200)

#define

CAN_F11R2_FB0 ((uint32_t)0x00000001)

#define

CAN_F11R2_FB1 ((uint32_t)0x00000002)

#define

CAN_F11R2_FB10 ((uint32_t)0x00000400)

#define

CAN_F11R2_FB11 ((uint32_t)0x00000800)

#define

CAN_F11R2_FB12 ((uint32_t)0x00001000)

#define

CAN_F11R2_FB13 ((uint32_t)0x00002000)

#define

CAN_F11R2_FB14 ((uint32_t)0x00004000)

#define

CAN_F11R2_FB15 ((uint32_t)0x00008000)

#define

CAN_F11R2_FB16 ((uint32_t)0x00010000)

#define

CAN_F11R2_FB17 ((uint32_t)0x00020000)

#define

CAN_F11R2_FB18 ((uint32_t)0x00040000)

#define

CAN_F11R2_FB19 ((uint32_t)0x00080000)

#define

CAN_F11R2_FB2 ((uint32_t)0x00000004)

#define

CAN_F11R2_FB20 ((uint32_t)0x00100000)

#define

CAN_F11R2_FB21 ((uint32_t)0x00200000)

#define

CAN_F11R2_FB22 ((uint32_t)0x00400000)

#define

CAN_F11R2_FB23 ((uint32_t)0x00800000)

#define

CAN_F11R2_FB24 ((uint32_t)0x01000000)

#define

CAN_F11R2_FB25 ((uint32_t)0x02000000)

#define

CAN_F11R2_FB26 ((uint32_t)0x04000000)

#define

CAN_F11R2_FB27 ((uint32_t)0x08000000)

#define

CAN_F11R2_FB28 ((uint32_t)0x10000000)

#define

CAN_F11R2_FB29 ((uint32_t)0x20000000)

#define

CAN_F11R2_FB3 ((uint32_t)0x00000008)

#define

CAN_F11R2_FB30 ((uint32_t)0x40000000)

#define

CAN_F11R2_FB31 ((uint32_t)0x80000000)

#define

CAN_F11R2_FB4 ((uint32_t)0x00000010)

#define

CAN_F11R2_FB5 ((uint32_t)0x00000020)

#define

CAN_F11R2_FB6 ((uint32_t)0x00000040)

#define

CAN_F11R2_FB7 ((uint32_t)0x00000080)

#define

CAN_F11R2_FB8 ((uint32_t)0x00000100)

#define

CAN_F11R2_FB9 ((uint32_t)0x00000200)

#define

CAN_F12R1_FB0 ((uint32_t)0x00000001)

#define

CAN_F12R1_FB1 ((uint32_t)0x00000002)

#define

CAN_F12R1_FB10 ((uint32_t)0x00000400)

#define

CAN_F12R1_FB11 ((uint32_t)0x00000800)

#define

CAN_F12R1_FB12 ((uint32_t)0x00001000)

#define

CAN_F12R1_FB13 ((uint32_t)0x00002000)

#define

CAN_F12R1_FB14 ((uint32_t)0x00004000)

#define

CAN_F12R1_FB15 ((uint32_t)0x00008000)

#define

CAN_F12R1_FB16 ((uint32_t)0x00010000)

#define

CAN_F12R1_FB17 ((uint32_t)0x00020000)

#define

CAN_F12R1_FB18 ((uint32_t)0x00040000)

#define

CAN_F12R1_FB19 ((uint32_t)0x00080000)

#define

CAN_F12R1_FB2 ((uint32_t)0x00000004)

#define

CAN_F12R1_FB20 ((uint32_t)0x00100000)

#define

CAN_F12R1_FB21 ((uint32_t)0x00200000)

#define

CAN_F12R1_FB22 ((uint32_t)0x00400000)

#define

CAN_F12R1_FB23 ((uint32_t)0x00800000)

#define

CAN_F12R1_FB24 ((uint32_t)0x01000000)

#define

CAN_F12R1_FB25 ((uint32_t)0x02000000)

#define

CAN_F12R1_FB26 ((uint32_t)0x04000000)

#define

CAN_F12R1_FB27 ((uint32_t)0x08000000)

#define

CAN_F12R1_FB28 ((uint32_t)0x10000000)

#define

CAN_F12R1_FB29 ((uint32_t)0x20000000)

#define

CAN_F12R1_FB3 ((uint32_t)0x00000008)

#define

CAN_F12R1_FB30 ((uint32_t)0x40000000)

#define

CAN_F12R1_FB31 ((uint32_t)0x80000000)

#define

CAN_F12R1_FB4 ((uint32_t)0x00000010)

#define

CAN_F12R1_FB5 ((uint32_t)0x00000020)

#define

CAN_F12R1_FB6 ((uint32_t)0x00000040)

#define

CAN_F12R1_FB7 ((uint32_t)0x00000080)

#define

CAN_F12R1_FB8 ((uint32_t)0x00000100)

#define

CAN_F12R1_FB9 ((uint32_t)0x00000200)

#define

CAN_F12R2_FB0 ((uint32_t)0x00000001)

#define

CAN_F12R2_FB1 ((uint32_t)0x00000002)

#define

CAN_F12R2_FB10 ((uint32_t)0x00000400)

#define

CAN_F12R2_FB11 ((uint32_t)0x00000800)

#define

CAN_F12R2_FB12 ((uint32_t)0x00001000)

#define

CAN_F12R2_FB13 ((uint32_t)0x00002000)

#define

CAN_F12R2_FB14 ((uint32_t)0x00004000)

#define

CAN_F12R2_FB15 ((uint32_t)0x00008000)

#define

CAN_F12R2_FB16 ((uint32_t)0x00010000)

#define

CAN_F12R2_FB17 ((uint32_t)0x00020000)

#define

CAN_F12R2_FB18 ((uint32_t)0x00040000)

#define

CAN_F12R2_FB19 ((uint32_t)0x00080000)

#define

CAN_F12R2_FB2 ((uint32_t)0x00000004)

#define

CAN_F12R2_FB20 ((uint32_t)0x00100000)

#define

CAN_F12R2_FB21 ((uint32_t)0x00200000)

#define

CAN_F12R2_FB22 ((uint32_t)0x00400000)

#define

CAN_F12R2_FB23 ((uint32_t)0x00800000)

#define

CAN_F12R2_FB24 ((uint32_t)0x01000000)

#define

CAN_F12R2_FB25 ((uint32_t)0x02000000)

#define

CAN_F12R2_FB26 ((uint32_t)0x04000000)

#define

CAN_F12R2_FB27 ((uint32_t)0x08000000)

#define

CAN_F12R2_FB28 ((uint32_t)0x10000000)

#define

CAN_F12R2_FB29 ((uint32_t)0x20000000)

#define

CAN_F12R2_FB3 ((uint32_t)0x00000008)

#define

CAN_F12R2_FB30 ((uint32_t)0x40000000)

#define

CAN_F12R2_FB31 ((uint32_t)0x80000000)

#define

CAN_F12R2_FB4 ((uint32_t)0x00000010)

#define

CAN_F12R2_FB5 ((uint32_t)0x00000020)

#define

CAN_F12R2_FB6 ((uint32_t)0x00000040)

#define

CAN_F12R2_FB7 ((uint32_t)0x00000080)

#define

CAN_F12R2_FB8 ((uint32_t)0x00000100)

#define

CAN_F12R2_FB9 ((uint32_t)0x00000200)

#define

CAN_F13R1_FB0 ((uint32_t)0x00000001)

#define

CAN_F13R1_FB1 ((uint32_t)0x00000002)

#define

CAN_F13R1_FB10 ((uint32_t)0x00000400)

#define

CAN_F13R1_FB11 ((uint32_t)0x00000800)

#define

CAN_F13R1_FB12 ((uint32_t)0x00001000)

#define

CAN_F13R1_FB13 ((uint32_t)0x00002000)

#define

CAN_F13R1_FB14 ((uint32_t)0x00004000)

#define

CAN_F13R1_FB15 ((uint32_t)0x00008000)

#define

CAN_F13R1_FB16 ((uint32_t)0x00010000)

#define

CAN_F13R1_FB17 ((uint32_t)0x00020000)

#define

CAN_F13R1_FB18 ((uint32_t)0x00040000)

#define

CAN_F13R1_FB19 ((uint32_t)0x00080000)

#define

CAN_F13R1_FB2 ((uint32_t)0x00000004)

#define

CAN_F13R1_FB20 ((uint32_t)0x00100000)

#define

CAN_F13R1_FB21 ((uint32_t)0x00200000)

#define

CAN_F13R1_FB22 ((uint32_t)0x00400000)

#define

CAN_F13R1_FB23 ((uint32_t)0x00800000)

#define

CAN_F13R1_FB24 ((uint32_t)0x01000000)

#define

CAN_F13R1_FB25 ((uint32_t)0x02000000)

#define

CAN_F13R1_FB26 ((uint32_t)0x04000000)

#define

CAN_F13R1_FB27 ((uint32_t)0x08000000)

#define

CAN_F13R1_FB28 ((uint32_t)0x10000000)

#define

CAN_F13R1_FB29 ((uint32_t)0x20000000)

#define

CAN_F13R1_FB3 ((uint32_t)0x00000008)

#define

CAN_F13R1_FB30 ((uint32_t)0x40000000)

#define

CAN_F13R1_FB31 ((uint32_t)0x80000000)

#define

CAN_F13R1_FB4 ((uint32_t)0x00000010)

#define

CAN_F13R1_FB5 ((uint32_t)0x00000020)

#define

CAN_F13R1_FB6 ((uint32_t)0x00000040)

#define

CAN_F13R1_FB7 ((uint32_t)0x00000080)

#define

CAN_F13R1_FB8 ((uint32_t)0x00000100)

#define

CAN_F13R1_FB9 ((uint32_t)0x00000200)

#define

CAN_F13R2_FB0 ((uint32_t)0x00000001)

#define

CAN_F13R2_FB1 ((uint32_t)0x00000002)

#define

CAN_F13R2_FB10 ((uint32_t)0x00000400)

#define

CAN_F13R2_FB11 ((uint32_t)0x00000800)

#define

CAN_F13R2_FB12 ((uint32_t)0x00001000)

#define

CAN_F13R2_FB13 ((uint32_t)0x00002000)

#define

CAN_F13R2_FB14 ((uint32_t)0x00004000)

#define

CAN_F13R2_FB15 ((uint32_t)0x00008000)

#define

CAN_F13R2_FB16 ((uint32_t)0x00010000)

#define

CAN_F13R2_FB17 ((uint32_t)0x00020000)

#define

CAN_F13R2_FB18 ((uint32_t)0x00040000)

#define

CAN_F13R2_FB19 ((uint32_t)0x00080000)

#define

CAN_F13R2_FB2 ((uint32_t)0x00000004)

#define

CAN_F13R2_FB20 ((uint32_t)0x00100000)

#define

CAN_F13R2_FB21 ((uint32_t)0x00200000)

#define

CAN_F13R2_FB22 ((uint32_t)0x00400000)

#define

CAN_F13R2_FB23 ((uint32_t)0x00800000)

#define

CAN_F13R2_FB24 ((uint32_t)0x01000000)

#define

CAN_F13R2_FB25 ((uint32_t)0x02000000)

#define

CAN_F13R2_FB26 ((uint32_t)0x04000000)

#define

CAN_F13R2_FB27 ((uint32_t)0x08000000)

#define

CAN_F13R2_FB28 ((uint32_t)0x10000000)

#define

CAN_F13R2_FB29 ((uint32_t)0x20000000)

#define

CAN_F13R2_FB3 ((uint32_t)0x00000008)

#define

CAN_F13R2_FB30 ((uint32_t)0x40000000)

#define

CAN_F13R2_FB31 ((uint32_t)0x80000000)

#define

CAN_F13R2_FB4 ((uint32_t)0x00000010)

#define

CAN_F13R2_FB5 ((uint32_t)0x00000020)

#define

CAN_F13R2_FB6 ((uint32_t)0x00000040)

#define

CAN_F13R2_FB7 ((uint32_t)0x00000080)

#define

CAN_F13R2_FB8 ((uint32_t)0x00000100)

#define

CAN_F13R2_FB9 ((uint32_t)0x00000200)

#define

CAN_F1R1_FB0 ((uint32_t)0x00000001)

#define

CAN_F1R1_FB1 ((uint32_t)0x00000002)

#define

CAN_F1R1_FB10 ((uint32_t)0x00000400)

#define

CAN_F1R1_FB11 ((uint32_t)0x00000800)

#define

CAN_F1R1_FB12 ((uint32_t)0x00001000)

#define

CAN_F1R1_FB13 ((uint32_t)0x00002000)

#define

CAN_F1R1_FB14 ((uint32_t)0x00004000)

#define

CAN_F1R1_FB15 ((uint32_t)0x00008000)

#define

CAN_F1R1_FB16 ((uint32_t)0x00010000)

#define

CAN_F1R1_FB17 ((uint32_t)0x00020000)

#define

CAN_F1R1_FB18 ((uint32_t)0x00040000)

#define

CAN_F1R1_FB19 ((uint32_t)0x00080000)

#define

CAN_F1R1_FB2 ((uint32_t)0x00000004)

#define

CAN_F1R1_FB20 ((uint32_t)0x00100000)

#define

CAN_F1R1_FB21 ((uint32_t)0x00200000)

#define

CAN_F1R1_FB22 ((uint32_t)0x00400000)

#define

CAN_F1R1_FB23 ((uint32_t)0x00800000)

#define

CAN_F1R1_FB24 ((uint32_t)0x01000000)

#define

CAN_F1R1_FB25 ((uint32_t)0x02000000)

#define

CAN_F1R1_FB26 ((uint32_t)0x04000000)

#define

CAN_F1R1_FB27 ((uint32_t)0x08000000)

#define

CAN_F1R1_FB28 ((uint32_t)0x10000000)

#define

CAN_F1R1_FB29 ((uint32_t)0x20000000)

#define

CAN_F1R1_FB3 ((uint32_t)0x00000008)

#define

CAN_F1R1_FB30 ((uint32_t)0x40000000)

#define

CAN_F1R1_FB31 ((uint32_t)0x80000000)

#define

CAN_F1R1_FB4 ((uint32_t)0x00000010)

#define

CAN_F1R1_FB5 ((uint32_t)0x00000020)

#define

CAN_F1R1_FB6 ((uint32_t)0x00000040)

#define

CAN_F1R1_FB7 ((uint32_t)0x00000080)

#define

CAN_F1R1_FB8 ((uint32_t)0x00000100)

#define

CAN_F1R1_FB9 ((uint32_t)0x00000200)

#define

CAN_F1R2_FB0 ((uint32_t)0x00000001)

#define

CAN_F1R2_FB1 ((uint32_t)0x00000002)

#define

CAN_F1R2_FB10 ((uint32_t)0x00000400)

#define

CAN_F1R2_FB11 ((uint32_t)0x00000800)

#define

CAN_F1R2_FB12 ((uint32_t)0x00001000)

#define

CAN_F1R2_FB13 ((uint32_t)0x00002000)

#define

CAN_F1R2_FB14 ((uint32_t)0x00004000)

#define

CAN_F1R2_FB15 ((uint32_t)0x00008000)

#define

CAN_F1R2_FB16 ((uint32_t)0x00010000)

#define

CAN_F1R2_FB17 ((uint32_t)0x00020000)

#define

CAN_F1R2_FB18 ((uint32_t)0x00040000)

#define

CAN_F1R2_FB19 ((uint32_t)0x00080000)

#define

CAN_F1R2_FB2 ((uint32_t)0x00000004)

#define

CAN_F1R2_FB20 ((uint32_t)0x00100000)

#define

CAN_F1R2_FB21 ((uint32_t)0x00200000)

#define

CAN_F1R2_FB22 ((uint32_t)0x00400000)

#define

CAN_F1R2_FB23 ((uint32_t)0x00800000)

#define

CAN_F1R2_FB24 ((uint32_t)0x01000000)

#define

CAN_F1R2_FB25 ((uint32_t)0x02000000)

#define

CAN_F1R2_FB26 ((uint32_t)0x04000000)

#define

CAN_F1R2_FB27 ((uint32_t)0x08000000)

#define

CAN_F1R2_FB28 ((uint32_t)0x10000000)

#define

CAN_F1R2_FB29 ((uint32_t)0x20000000)

#define

CAN_F1R2_FB3 ((uint32_t)0x00000008)

#define

CAN_F1R2_FB30 ((uint32_t)0x40000000)

#define

CAN_F1R2_FB31 ((uint32_t)0x80000000)

#define

CAN_F1R2_FB4 ((uint32_t)0x00000010)

#define

CAN_F1R2_FB5 ((uint32_t)0x00000020)

#define

CAN_F1R2_FB6 ((uint32_t)0x00000040)

#define

CAN_F1R2_FB7 ((uint32_t)0x00000080)

#define

CAN_F1R2_FB8 ((uint32_t)0x00000100)

#define

CAN_F1R2_FB9 ((uint32_t)0x00000200)

#define

CAN_F2R1_FB0 ((uint32_t)0x00000001)

#define

CAN_F2R1_FB1 ((uint32_t)0x00000002)

#define

CAN_F2R1_FB10 ((uint32_t)0x00000400)

#define

CAN_F2R1_FB11 ((uint32_t)0x00000800)

#define

CAN_F2R1_FB12 ((uint32_t)0x00001000)

#define

CAN_F2R1_FB13 ((uint32_t)0x00002000)

#define

CAN_F2R1_FB14 ((uint32_t)0x00004000)

#define

CAN_F2R1_FB15 ((uint32_t)0x00008000)

#define

CAN_F2R1_FB16 ((uint32_t)0x00010000)

#define

CAN_F2R1_FB17 ((uint32_t)0x00020000)

#define

CAN_F2R1_FB18 ((uint32_t)0x00040000)

#define

CAN_F2R1_FB19 ((uint32_t)0x00080000)

#define

CAN_F2R1_FB2 ((uint32_t)0x00000004)

#define

CAN_F2R1_FB20 ((uint32_t)0x00100000)

#define

CAN_F2R1_FB21 ((uint32_t)0x00200000)

#define

CAN_F2R1_FB22 ((uint32_t)0x00400000)

#define

CAN_F2R1_FB23 ((uint32_t)0x00800000)

#define

CAN_F2R1_FB24 ((uint32_t)0x01000000)

#define

CAN_F2R1_FB25 ((uint32_t)0x02000000)

#define

CAN_F2R1_FB26 ((uint32_t)0x04000000)

#define

CAN_F2R1_FB27 ((uint32_t)0x08000000)

#define

CAN_F2R1_FB28 ((uint32_t)0x10000000)

#define

CAN_F2R1_FB29 ((uint32_t)0x20000000)

#define

CAN_F2R1_FB3 ((uint32_t)0x00000008)

#define

CAN_F2R1_FB30 ((uint32_t)0x40000000)

#define

CAN_F2R1_FB31 ((uint32_t)0x80000000)

#define

CAN_F2R1_FB4 ((uint32_t)0x00000010)

#define

CAN_F2R1_FB5 ((uint32_t)0x00000020)

#define

CAN_F2R1_FB6 ((uint32_t)0x00000040)

#define

CAN_F2R1_FB7 ((uint32_t)0x00000080)

#define

CAN_F2R1_FB8 ((uint32_t)0x00000100)

#define

CAN_F2R1_FB9 ((uint32_t)0x00000200)

#define

CAN_F2R2_FB0 ((uint32_t)0x00000001)

#define

CAN_F2R2_FB1 ((uint32_t)0x00000002)

#define

CAN_F2R2_FB10 ((uint32_t)0x00000400)

#define

CAN_F2R2_FB11 ((uint32_t)0x00000800)

#define

CAN_F2R2_FB12 ((uint32_t)0x00001000)

#define

CAN_F2R2_FB13 ((uint32_t)0x00002000)

#define

CAN_F2R2_FB14 ((uint32_t)0x00004000)

#define

CAN_F2R2_FB15 ((uint32_t)0x00008000)

#define

CAN_F2R2_FB16 ((uint32_t)0x00010000)

#define

CAN_F2R2_FB17 ((uint32_t)0x00020000)

#define

CAN_F2R2_FB18 ((uint32_t)0x00040000)

#define

CAN_F2R2_FB19 ((uint32_t)0x00080000)

#define

CAN_F2R2_FB2 ((uint32_t)0x00000004)

#define

CAN_F2R2_FB20 ((uint32_t)0x00100000)

#define

CAN_F2R2_FB21 ((uint32_t)0x00200000)

#define

CAN_F2R2_FB22 ((uint32_t)0x00400000)

#define

CAN_F2R2_FB23 ((uint32_t)0x00800000)

#define

CAN_F2R2_FB24 ((uint32_t)0x01000000)

#define

CAN_F2R2_FB25 ((uint32_t)0x02000000)

#define

CAN_F2R2_FB26 ((uint32_t)0x04000000)

#define

CAN_F2R2_FB27 ((uint32_t)0x08000000)

#define

CAN_F2R2_FB28 ((uint32_t)0x10000000)

#define

CAN_F2R2_FB29 ((uint32_t)0x20000000)

#define

CAN_F2R2_FB3 ((uint32_t)0x00000008)

#define

CAN_F2R2_FB30 ((uint32_t)0x40000000)

#define

CAN_F2R2_FB31 ((uint32_t)0x80000000)

#define

CAN_F2R2_FB4 ((uint32_t)0x00000010)

#define

CAN_F2R2_FB5 ((uint32_t)0x00000020)

#define

CAN_F2R2_FB6 ((uint32_t)0x00000040)

#define

CAN_F2R2_FB7 ((uint32_t)0x00000080)

#define

CAN_F2R2_FB8 ((uint32_t)0x00000100)

#define

CAN_F2R2_FB9 ((uint32_t)0x00000200)

#define

CAN_F3R1_FB0 ((uint32_t)0x00000001)

#define

CAN_F3R1_FB1 ((uint32_t)0x00000002)

#define

CAN_F3R1_FB10 ((uint32_t)0x00000400)

#define

CAN_F3R1_FB11 ((uint32_t)0x00000800)

#define

CAN_F3R1_FB12 ((uint32_t)0x00001000)

#define

CAN_F3R1_FB13 ((uint32_t)0x00002000)

#define

CAN_F3R1_FB14 ((uint32_t)0x00004000)

#define

CAN_F3R1_FB15 ((uint32_t)0x00008000)

#define

CAN_F3R1_FB16 ((uint32_t)0x00010000)

#define

CAN_F3R1_FB17 ((uint32_t)0x00020000)

#define

CAN_F3R1_FB18 ((uint32_t)0x00040000)

#define

CAN_F3R1_FB19 ((uint32_t)0x00080000)

#define

CAN_F3R1_FB2 ((uint32_t)0x00000004)

#define

CAN_F3R1_FB20 ((uint32_t)0x00100000)

#define

CAN_F3R1_FB21 ((uint32_t)0x00200000)

#define

CAN_F3R1_FB22 ((uint32_t)0x00400000)

#define

CAN_F3R1_FB23 ((uint32_t)0x00800000)

#define

CAN_F3R1_FB24 ((uint32_t)0x01000000)

#define

CAN_F3R1_FB25 ((uint32_t)0x02000000)

#define

CAN_F3R1_FB26 ((uint32_t)0x04000000)

#define

CAN_F3R1_FB27 ((uint32_t)0x08000000)

#define

CAN_F3R1_FB28 ((uint32_t)0x10000000)

#define

CAN_F3R1_FB29 ((uint32_t)0x20000000)

#define

CAN_F3R1_FB3 ((uint32_t)0x00000008)

#define

CAN_F3R1_FB30 ((uint32_t)0x40000000)

#define

CAN_F3R1_FB31 ((uint32_t)0x80000000)

#define

CAN_F3R1_FB4 ((uint32_t)0x00000010)

#define

CAN_F3R1_FB5 ((uint32_t)0x00000020)

#define

CAN_F3R1_FB6 ((uint32_t)0x00000040)

#define

CAN_F3R1_FB7 ((uint32_t)0x00000080)

#define

CAN_F3R1_FB8 ((uint32_t)0x00000100)

#define

CAN_F3R1_FB9 ((uint32_t)0x00000200)

#define

CAN_F3R2_FB0 ((uint32_t)0x00000001)

#define

CAN_F3R2_FB1 ((uint32_t)0x00000002)

#define

CAN_F3R2_FB10 ((uint32_t)0x00000400)

#define

CAN_F3R2_FB11 ((uint32_t)0x00000800)

#define

CAN_F3R2_FB12 ((uint32_t)0x00001000)

#define

CAN_F3R2_FB13 ((uint32_t)0x00002000)

#define

CAN_F3R2_FB14 ((uint32_t)0x00004000)

#define

CAN_F3R2_FB15 ((uint32_t)0x00008000)

#define

CAN_F3R2_FB16 ((uint32_t)0x00010000)

#define

CAN_F3R2_FB17 ((uint32_t)0x00020000)

#define

CAN_F3R2_FB18 ((uint32_t)0x00040000)

#define

CAN_F3R2_FB19 ((uint32_t)0x00080000)

#define

CAN_F3R2_FB2 ((uint32_t)0x00000004)

#define

CAN_F3R2_FB20 ((uint32_t)0x00100000)

#define

CAN_F3R2_FB21 ((uint32_t)0x00200000)

#define

CAN_F3R2_FB22 ((uint32_t)0x00400000)

#define

CAN_F3R2_FB23 ((uint32_t)0x00800000)

#define

CAN_F3R2_FB24 ((uint32_t)0x01000000)

#define

CAN_F3R2_FB25 ((uint32_t)0x02000000)

#define

CAN_F3R2_FB26 ((uint32_t)0x04000000)

#define

CAN_F3R2_FB27 ((uint32_t)0x08000000)

#define

CAN_F3R2_FB28 ((uint32_t)0x10000000)

#define

CAN_F3R2_FB29 ((uint32_t)0x20000000)

#define

CAN_F3R2_FB3 ((uint32_t)0x00000008)

#define

CAN_F3R2_FB30 ((uint32_t)0x40000000)

#define

CAN_F3R2_FB31 ((uint32_t)0x80000000)

#define

CAN_F3R2_FB4 ((uint32_t)0x00000010)

#define

CAN_F3R2_FB5 ((uint32_t)0x00000020)

#define

CAN_F3R2_FB6 ((uint32_t)0x00000040)

#define

CAN_F3R2_FB7 ((uint32_t)0x00000080)

#define

CAN_F3R2_FB8 ((uint32_t)0x00000100)

#define

CAN_F3R2_FB9 ((uint32_t)0x00000200)

#define

CAN_F4R1_FB0 ((uint32_t)0x00000001)

#define

CAN_F4R1_FB1 ((uint32_t)0x00000002)

#define

CAN_F4R1_FB10 ((uint32_t)0x00000400)

#define

CAN_F4R1_FB11 ((uint32_t)0x00000800)

#define

CAN_F4R1_FB12 ((uint32_t)0x00001000)

#define

CAN_F4R1_FB13 ((uint32_t)0x00002000)

#define

CAN_F4R1_FB14 ((uint32_t)0x00004000)

#define

CAN_F4R1_FB15 ((uint32_t)0x00008000)

#define

CAN_F4R1_FB16 ((uint32_t)0x00010000)

#define

CAN_F4R1_FB17 ((uint32_t)0x00020000)

#define

CAN_F4R1_FB18 ((uint32_t)0x00040000)

#define

CAN_F4R1_FB19 ((uint32_t)0x00080000)

#define

CAN_F4R1_FB2 ((uint32_t)0x00000004)

#define

CAN_F4R1_FB20 ((uint32_t)0x00100000)

#define

CAN_F4R1_FB21 ((uint32_t)0x00200000)

#define

CAN_F4R1_FB22 ((uint32_t)0x00400000)

#define

CAN_F4R1_FB23 ((uint32_t)0x00800000)

#define

CAN_F4R1_FB24 ((uint32_t)0x01000000)

#define

CAN_F4R1_FB25 ((uint32_t)0x02000000)

#define

CAN_F4R1_FB26 ((uint32_t)0x04000000)

#define

CAN_F4R1_FB27 ((uint32_t)0x08000000)

#define

CAN_F4R1_FB28 ((uint32_t)0x10000000)

#define

CAN_F4R1_FB29 ((uint32_t)0x20000000)

#define

CAN_F4R1_FB3 ((uint32_t)0x00000008)

#define

CAN_F4R1_FB30 ((uint32_t)0x40000000)

#define

CAN_F4R1_FB31 ((uint32_t)0x80000000)

#define

CAN_F4R1_FB4 ((uint32_t)0x00000010)

#define

CAN_F4R1_FB5 ((uint32_t)0x00000020)

#define

CAN_F4R1_FB6 ((uint32_t)0x00000040)

#define

CAN_F4R1_FB7 ((uint32_t)0x00000080)

#define

CAN_F4R1_FB8 ((uint32_t)0x00000100)

#define

CAN_F4R1_FB9 ((uint32_t)0x00000200)

#define

CAN_F4R2_FB0 ((uint32_t)0x00000001)

#define

CAN_F4R2_FB1 ((uint32_t)0x00000002)

#define

CAN_F4R2_FB10 ((uint32_t)0x00000400)

#define

CAN_F4R2_FB11 ((uint32_t)0x00000800)

#define

CAN_F4R2_FB12 ((uint32_t)0x00001000)

#define

CAN_F4R2_FB13 ((uint32_t)0x00002000)

#define

CAN_F4R2_FB14 ((uint32_t)0x00004000)

#define

CAN_F4R2_FB15 ((uint32_t)0x00008000)

#define

CAN_F4R2_FB16 ((uint32_t)0x00010000)

#define

CAN_F4R2_FB17 ((uint32_t)0x00020000)

#define

CAN_F4R2_FB18 ((uint32_t)0x00040000)

#define

CAN_F4R2_FB19 ((uint32_t)0x00080000)

#define

CAN_F4R2_FB2 ((uint32_t)0x00000004)

#define

CAN_F4R2_FB20 ((uint32_t)0x00100000)

#define

CAN_F4R2_FB21 ((uint32_t)0x00200000)

#define

CAN_F4R2_FB22 ((uint32_t)0x00400000)

#define

CAN_F4R2_FB23 ((uint32_t)0x00800000)

#define

CAN_F4R2_FB24 ((uint32_t)0x01000000)

#define

CAN_F4R2_FB25 ((uint32_t)0x02000000)

#define

CAN_F4R2_FB26 ((uint32_t)0x04000000)

#define

CAN_F4R2_FB27 ((uint32_t)0x08000000)

#define

CAN_F4R2_FB28 ((uint32_t)0x10000000)

#define

CAN_F4R2_FB29 ((uint32_t)0x20000000)

#define

CAN_F4R2_FB3 ((uint32_t)0x00000008)

#define

CAN_F4R2_FB30 ((uint32_t)0x40000000)

#define

CAN_F4R2_FB31 ((uint32_t)0x80000000)

#define

CAN_F4R2_FB4 ((uint32_t)0x00000010)

#define

CAN_F4R2_FB5 ((uint32_t)0x00000020)

#define

CAN_F4R2_FB6 ((uint32_t)0x00000040)

#define

CAN_F4R2_FB7 ((uint32_t)0x00000080)

#define

CAN_F4R2_FB8 ((uint32_t)0x00000100)

#define

CAN_F4R2_FB9 ((uint32_t)0x00000200)

#define

CAN_F5R1_FB0 ((uint32_t)0x00000001)

#define

CAN_F5R1_FB1 ((uint32_t)0x00000002)

#define

CAN_F5R1_FB10 ((uint32_t)0x00000400)

#define

CAN_F5R1_FB11 ((uint32_t)0x00000800)

#define

CAN_F5R1_FB12 ((uint32_t)0x00001000)

#define

CAN_F5R1_FB13 ((uint32_t)0x00002000)

#define

CAN_F5R1_FB14 ((uint32_t)0x00004000)

#define

CAN_F5R1_FB15 ((uint32_t)0x00008000)

#define

CAN_F5R1_FB16 ((uint32_t)0x00010000)

#define

CAN_F5R1_FB17 ((uint32_t)0x00020000)

#define

CAN_F5R1_FB18 ((uint32_t)0x00040000)

#define

CAN_F5R1_FB19 ((uint32_t)0x00080000)

#define

CAN_F5R1_FB2 ((uint32_t)0x00000004)

#define

CAN_F5R1_FB20 ((uint32_t)0x00100000)

#define

CAN_F5R1_FB21 ((uint32_t)0x00200000)

#define

CAN_F5R1_FB22 ((uint32_t)0x00400000)

#define

CAN_F5R1_FB23 ((uint32_t)0x00800000)

#define

CAN_F5R1_FB24 ((uint32_t)0x01000000)

#define

CAN_F5R1_FB25 ((uint32_t)0x02000000)

#define

CAN_F5R1_FB26 ((uint32_t)0x04000000)

#define

CAN_F5R1_FB27 ((uint32_t)0x08000000)

#define

CAN_F5R1_FB28 ((uint32_t)0x10000000)

#define

CAN_F5R1_FB29 ((uint32_t)0x20000000)

#define

CAN_F5R1_FB3 ((uint32_t)0x00000008)

#define

CAN_F5R1_FB30 ((uint32_t)0x40000000)

#define

CAN_F5R1_FB31 ((uint32_t)0x80000000)

#define

CAN_F5R1_FB4 ((uint32_t)0x00000010)

#define

CAN_F5R1_FB5 ((uint32_t)0x00000020)

#define

CAN_F5R1_FB6 ((uint32_t)0x00000040)

#define

CAN_F5R1_FB7 ((uint32_t)0x00000080)

#define

CAN_F5R1_FB8 ((uint32_t)0x00000100)

#define

CAN_F5R1_FB9 ((uint32_t)0x00000200)

#define

CAN_F5R2_FB0 ((uint32_t)0x00000001)

#define

CAN_F5R2_FB1 ((uint32_t)0x00000002)

#define

CAN_F5R2_FB10 ((uint32_t)0x00000400)

#define

CAN_F5R2_FB11 ((uint32_t)0x00000800)

#define

CAN_F5R2_FB12 ((uint32_t)0x00001000)

#define

CAN_F5R2_FB13 ((uint32_t)0x00002000)

#define

CAN_F5R2_FB14 ((uint32_t)0x00004000)

#define

CAN_F5R2_FB15 ((uint32_t)0x00008000)

#define

CAN_F5R2_FB16 ((uint32_t)0x00010000)

#define

CAN_F5R2_FB17 ((uint32_t)0x00020000)

#define

CAN_F5R2_FB18 ((uint32_t)0x00040000)

#define

CAN_F5R2_FB19 ((uint32_t)0x00080000)

#define

CAN_F5R2_FB2 ((uint32_t)0x00000004)

#define

CAN_F5R2_FB20 ((uint32_t)0x00100000)

#define

CAN_F5R2_FB21 ((uint32_t)0x00200000)

#define

CAN_F5R2_FB22 ((uint32_t)0x00400000)

#define

CAN_F5R2_FB23 ((uint32_t)0x00800000)

#define

CAN_F5R2_FB24 ((uint32_t)0x01000000)

#define

CAN_F5R2_FB25 ((uint32_t)0x02000000)

#define

CAN_F5R2_FB26 ((uint32_t)0x04000000)

#define

CAN_F5R2_FB27 ((uint32_t)0x08000000)

#define

CAN_F5R2_FB28 ((uint32_t)0x10000000)

#define

CAN_F5R2_FB29 ((uint32_t)0x20000000)

#define

CAN_F5R2_FB3 ((uint32_t)0x00000008)

#define

CAN_F5R2_FB30 ((uint32_t)0x40000000)

#define

CAN_F5R2_FB31 ((uint32_t)0x80000000)

#define

CAN_F5R2_FB4 ((uint32_t)0x00000010)

#define

CAN_F5R2_FB5 ((uint32_t)0x00000020)

#define

CAN_F5R2_FB6 ((uint32_t)0x00000040)

#define

CAN_F5R2_FB7 ((uint32_t)0x00000080)

#define

CAN_F5R2_FB8 ((uint32_t)0x00000100)

#define

CAN_F5R2_FB9 ((uint32_t)0x00000200)

#define

CAN_F6R1_FB0 ((uint32_t)0x00000001)

#define

CAN_F6R1_FB1 ((uint32_t)0x00000002)

#define

CAN_F6R1_FB10 ((uint32_t)0x00000400)

#define

CAN_F6R1_FB11 ((uint32_t)0x00000800)

#define

CAN_F6R1_FB12 ((uint32_t)0x00001000)

#define

CAN_F6R1_FB13 ((uint32_t)0x00002000)

#define

CAN_F6R1_FB14 ((uint32_t)0x00004000)

#define

CAN_F6R1_FB15 ((uint32_t)0x00008000)

#define

CAN_F6R1_FB16 ((uint32_t)0x00010000)

#define

CAN_F6R1_FB17 ((uint32_t)0x00020000)

#define

CAN_F6R1_FB18 ((uint32_t)0x00040000)

#define

CAN_F6R1_FB19 ((uint32_t)0x00080000)

#define

CAN_F6R1_FB2 ((uint32_t)0x00000004)

#define

CAN_F6R1_FB20 ((uint32_t)0x00100000)

#define

CAN_F6R1_FB21 ((uint32_t)0x00200000)

#define

CAN_F6R1_FB22 ((uint32_t)0x00400000)

#define

CAN_F6R1_FB23 ((uint32_t)0x00800000)

#define

CAN_F6R1_FB24 ((uint32_t)0x01000000)

#define

CAN_F6R1_FB25 ((uint32_t)0x02000000)

#define

CAN_F6R1_FB26 ((uint32_t)0x04000000)

#define

CAN_F6R1_FB27 ((uint32_t)0x08000000)

#define

CAN_F6R1_FB28 ((uint32_t)0x10000000)

#define

CAN_F6R1_FB29 ((uint32_t)0x20000000)

#define

CAN_F6R1_FB3 ((uint32_t)0x00000008)

#define

CAN_F6R1_FB30 ((uint32_t)0x40000000)

#define

CAN_F6R1_FB31 ((uint32_t)0x80000000)

#define

CAN_F6R1_FB4 ((uint32_t)0x00000010)

#define

CAN_F6R1_FB5 ((uint32_t)0x00000020)

#define

CAN_F6R1_FB6 ((uint32_t)0x00000040)

#define

CAN_F6R1_FB7 ((uint32_t)0x00000080)

#define

CAN_F6R1_FB8 ((uint32_t)0x00000100)

#define

CAN_F6R1_FB9 ((uint32_t)0x00000200)

#define

CAN_F6R2_FB0 ((uint32_t)0x00000001)

#define

CAN_F6R2_FB1 ((uint32_t)0x00000002)

#define

CAN_F6R2_FB10 ((uint32_t)0x00000400)

#define

CAN_F6R2_FB11 ((uint32_t)0x00000800)

#define

CAN_F6R2_FB12 ((uint32_t)0x00001000)

#define

CAN_F6R2_FB13 ((uint32_t)0x00002000)

#define

CAN_F6R2_FB14 ((uint32_t)0x00004000)

#define

CAN_F6R2_FB15 ((uint32_t)0x00008000)

#define

CAN_F6R2_FB16 ((uint32_t)0x00010000)

#define

CAN_F6R2_FB17 ((uint32_t)0x00020000)

#define

CAN_F6R2_FB18 ((uint32_t)0x00040000)

#define

CAN_F6R2_FB19 ((uint32_t)0x00080000)

#define

CAN_F6R2_FB2 ((uint32_t)0x00000004)

#define

CAN_F6R2_FB20 ((uint32_t)0x00100000)

#define

CAN_F6R2_FB21 ((uint32_t)0x00200000)

#define

CAN_F6R2_FB22 ((uint32_t)0x00400000)

#define

CAN_F6R2_FB23 ((uint32_t)0x00800000)

#define

CAN_F6R2_FB24 ((uint32_t)0x01000000)

#define

CAN_F6R2_FB25 ((uint32_t)0x02000000)

#define

CAN_F6R2_FB26 ((uint32_t)0x04000000)

#define

CAN_F6R2_FB27 ((uint32_t)0x08000000)

#define

CAN_F6R2_FB28 ((uint32_t)0x10000000)

#define

CAN_F6R2_FB29 ((uint32_t)0x20000000)

#define

CAN_F6R2_FB3 ((uint32_t)0x00000008)

#define

CAN_F6R2_FB30 ((uint32_t)0x40000000)

#define

CAN_F6R2_FB31 ((uint32_t)0x80000000)

#define

CAN_F6R2_FB4 ((uint32_t)0x00000010)

#define

CAN_F6R2_FB5 ((uint32_t)0x00000020)

#define

CAN_F6R2_FB6 ((uint32_t)0x00000040)

#define

CAN_F6R2_FB7 ((uint32_t)0x00000080)

#define

CAN_F6R2_FB8 ((uint32_t)0x00000100)

#define

CAN_F6R2_FB9 ((uint32_t)0x00000200)

#define

CAN_F7R1_FB0 ((uint32_t)0x00000001)

#define

CAN_F7R1_FB1 ((uint32_t)0x00000002)

#define

CAN_F7R1_FB10 ((uint32_t)0x00000400)

#define

CAN_F7R1_FB11 ((uint32_t)0x00000800)

#define

CAN_F7R1_FB12 ((uint32_t)0x00001000)

#define

CAN_F7R1_FB13 ((uint32_t)0x00002000)

#define

CAN_F7R1_FB14 ((uint32_t)0x00004000)

#define

CAN_F7R1_FB15 ((uint32_t)0x00008000)

#define

CAN_F7R1_FB16 ((uint32_t)0x00010000)

#define

CAN_F7R1_FB17 ((uint32_t)0x00020000)

#define

CAN_F7R1_FB18 ((uint32_t)0x00040000)

#define

CAN_F7R1_FB19 ((uint32_t)0x00080000)

#define

CAN_F7R1_FB2 ((uint32_t)0x00000004)

#define

CAN_F7R1_FB20 ((uint32_t)0x00100000)

#define

CAN_F7R1_FB21 ((uint32_t)0x00200000)

#define

CAN_F7R1_FB22 ((uint32_t)0x00400000)

#define

CAN_F7R1_FB23 ((uint32_t)0x00800000)

#define

CAN_F7R1_FB24 ((uint32_t)0x01000000)

#define

CAN_F7R1_FB25 ((uint32_t)0x02000000)

#define

CAN_F7R1_FB26 ((uint32_t)0x04000000)

#define

CAN_F7R1_FB27 ((uint32_t)0x08000000)

#define

CAN_F7R1_FB28 ((uint32_t)0x10000000)

#define

CAN_F7R1_FB29 ((uint32_t)0x20000000)

#define

CAN_F7R1_FB3 ((uint32_t)0x00000008)

#define

CAN_F7R1_FB30 ((uint32_t)0x40000000)

#define

CAN_F7R1_FB31 ((uint32_t)0x80000000)

#define

CAN_F7R1_FB4 ((uint32_t)0x00000010)

#define

CAN_F7R1_FB5 ((uint32_t)0x00000020)

#define

CAN_F7R1_FB6 ((uint32_t)0x00000040)

#define

CAN_F7R1_FB7 ((uint32_t)0x00000080)

#define

CAN_F7R1_FB8 ((uint32_t)0x00000100)

#define

CAN_F7R1_FB9 ((uint32_t)0x00000200)

#define

CAN_F7R2_FB0 ((uint32_t)0x00000001)

#define

CAN_F7R2_FB1 ((uint32_t)0x00000002)

#define

CAN_F7R2_FB10 ((uint32_t)0x00000400)

#define

CAN_F7R2_FB11 ((uint32_t)0x00000800)

#define

CAN_F7R2_FB12 ((uint32_t)0x00001000)

#define

CAN_F7R2_FB13 ((uint32_t)0x00002000)

#define

CAN_F7R2_FB14 ((uint32_t)0x00004000)

#define

CAN_F7R2_FB15 ((uint32_t)0x00008000)

#define

CAN_F7R2_FB16 ((uint32_t)0x00010000)

#define

CAN_F7R2_FB17 ((uint32_t)0x00020000)

#define

CAN_F7R2_FB18 ((uint32_t)0x00040000)

#define

CAN_F7R2_FB19 ((uint32_t)0x00080000)

#define

CAN_F7R2_FB2 ((uint32_t)0x00000004)

#define

CAN_F7R2_FB20 ((uint32_t)0x00100000)

#define

CAN_F7R2_FB21 ((uint32_t)0x00200000)

#define

CAN_F7R2_FB22 ((uint32_t)0x00400000)

#define

CAN_F7R2_FB23 ((uint32_t)0x00800000)

#define

CAN_F7R2_FB24 ((uint32_t)0x01000000)

#define

CAN_F7R2_FB25 ((uint32_t)0x02000000)

#define

CAN_F7R2_FB26 ((uint32_t)0x04000000)

#define

CAN_F7R2_FB27 ((uint32_t)0x08000000)

#define

CAN_F7R2_FB28 ((uint32_t)0x10000000)

#define

CAN_F7R2_FB29 ((uint32_t)0x20000000)

#define

CAN_F7R2_FB3 ((uint32_t)0x00000008)

#define

CAN_F7R2_FB30 ((uint32_t)0x40000000)

#define

CAN_F7R2_FB31 ((uint32_t)0x80000000)

#define

CAN_F7R2_FB4 ((uint32_t)0x00000010)

#define

CAN_F7R2_FB5 ((uint32_t)0x00000020)

#define

CAN_F7R2_FB6 ((uint32_t)0x00000040)

#define

CAN_F7R2_FB7 ((uint32_t)0x00000080)

#define

CAN_F7R2_FB8 ((uint32_t)0x00000100)

#define

CAN_F7R2_FB9 ((uint32_t)0x00000200)

#define

CAN_F8R1_FB0 ((uint32_t)0x00000001)

#define

CAN_F8R1_FB1 ((uint32_t)0x00000002)

#define

CAN_F8R1_FB10 ((uint32_t)0x00000400)

#define

CAN_F8R1_FB11 ((uint32_t)0x00000800)

#define

CAN_F8R1_FB12 ((uint32_t)0x00001000)

#define

CAN_F8R1_FB13 ((uint32_t)0x00002000)

#define

CAN_F8R1_FB14 ((uint32_t)0x00004000)

#define

CAN_F8R1_FB15 ((uint32_t)0x00008000)

#define

CAN_F8R1_FB16 ((uint32_t)0x00010000)

#define

CAN_F8R1_FB17 ((uint32_t)0x00020000)

#define

CAN_F8R1_FB18 ((uint32_t)0x00040000)

#define

CAN_F8R1_FB19 ((uint32_t)0x00080000)

#define

CAN_F8R1_FB2 ((uint32_t)0x00000004)

#define

CAN_F8R1_FB20 ((uint32_t)0x00100000)

#define

CAN_F8R1_FB21 ((uint32_t)0x00200000)

#define

CAN_F8R1_FB22 ((uint32_t)0x00400000)

#define

CAN_F8R1_FB23 ((uint32_t)0x00800000)

#define

CAN_F8R1_FB24 ((uint32_t)0x01000000)

#define

CAN_F8R1_FB25 ((uint32_t)0x02000000)

#define

CAN_F8R1_FB26 ((uint32_t)0x04000000)

#define

CAN_F8R1_FB27 ((uint32_t)0x08000000)

#define

CAN_F8R1_FB28 ((uint32_t)0x10000000)

#define

CAN_F8R1_FB29 ((uint32_t)0x20000000)

#define

CAN_F8R1_FB3 ((uint32_t)0x00000008)

#define

CAN_F8R1_FB30 ((uint32_t)0x40000000)

#define

CAN_F8R1_FB31 ((uint32_t)0x80000000)

#define

CAN_F8R1_FB4 ((uint32_t)0x00000010)

#define

CAN_F8R1_FB5 ((uint32_t)0x00000020)

#define

CAN_F8R1_FB6 ((uint32_t)0x00000040)

#define

CAN_F8R1_FB7 ((uint32_t)0x00000080)

#define

CAN_F8R1_FB8 ((uint32_t)0x00000100)

#define

CAN_F8R1_FB9 ((uint32_t)0x00000200)

#define

CAN_F8R2_FB0 ((uint32_t)0x00000001)

#define

CAN_F8R2_FB1 ((uint32_t)0x00000002)

#define

CAN_F8R2_FB10 ((uint32_t)0x00000400)

#define

CAN_F8R2_FB11 ((uint32_t)0x00000800)

#define

CAN_F8R2_FB12 ((uint32_t)0x00001000)

#define

CAN_F8R2_FB13 ((uint32_t)0x00002000)

#define

CAN_F8R2_FB14 ((uint32_t)0x00004000)

#define

CAN_F8R2_FB15 ((uint32_t)0x00008000)

#define

CAN_F8R2_FB16 ((uint32_t)0x00010000)

#define

CAN_F8R2_FB17 ((uint32_t)0x00020000)

#define

CAN_F8R2_FB18 ((uint32_t)0x00040000)

#define

CAN_F8R2_FB19 ((uint32_t)0x00080000)

#define

CAN_F8R2_FB2 ((uint32_t)0x00000004)

#define

CAN_F8R2_FB20 ((uint32_t)0x00100000)

#define

CAN_F8R2_FB21 ((uint32_t)0x00200000)

#define

CAN_F8R2_FB22 ((uint32_t)0x00400000)

#define

CAN_F8R2_FB23 ((uint32_t)0x00800000)

#define

CAN_F8R2_FB24 ((uint32_t)0x01000000)

#define

CAN_F8R2_FB25 ((uint32_t)0x02000000)

#define

CAN_F8R2_FB26 ((uint32_t)0x04000000)

#define

CAN_F8R2_FB27 ((uint32_t)0x08000000)

#define

CAN_F8R2_FB28 ((uint32_t)0x10000000)

#define

CAN_F8R2_FB29 ((uint32_t)0x20000000)

#define

CAN_F8R2_FB3 ((uint32_t)0x00000008)

#define

CAN_F8R2_FB30 ((uint32_t)0x40000000)

#define

CAN_F8R2_FB31 ((uint32_t)0x80000000)

#define

CAN_F8R2_FB4 ((uint32_t)0x00000010)

#define

CAN_F8R2_FB5 ((uint32_t)0x00000020)

#define

CAN_F8R2_FB6 ((uint32_t)0x00000040)

#define

CAN_F8R2_FB7 ((uint32_t)0x00000080)

#define

CAN_F8R2_FB8 ((uint32_t)0x00000100)

#define

CAN_F8R2_FB9 ((uint32_t)0x00000200)

#define

CAN_F9R1_FB0 ((uint32_t)0x00000001)

#define

CAN_F9R1_FB1 ((uint32_t)0x00000002)

#define

CAN_F9R1_FB10 ((uint32_t)0x00000400)

#define

CAN_F9R1_FB11 ((uint32_t)0x00000800)

#define

CAN_F9R1_FB12 ((uint32_t)0x00001000)

#define

CAN_F9R1_FB13 ((uint32_t)0x00002000)

#define

CAN_F9R1_FB14 ((uint32_t)0x00004000)

#define

CAN_F9R1_FB15 ((uint32_t)0x00008000)

#define

CAN_F9R1_FB16 ((uint32_t)0x00010000)

#define

CAN_F9R1_FB17 ((uint32_t)0x00020000)

#define

CAN_F9R1_FB18 ((uint32_t)0x00040000)

#define

CAN_F9R1_FB19 ((uint32_t)0x00080000)

#define

CAN_F9R1_FB2 ((uint32_t)0x00000004)

#define

CAN_F9R1_FB20 ((uint32_t)0x00100000)

#define

CAN_F9R1_FB21 ((uint32_t)0x00200000)

#define

CAN_F9R1_FB22 ((uint32_t)0x00400000)

#define

CAN_F9R1_FB23 ((uint32_t)0x00800000)

#define

CAN_F9R1_FB24 ((uint32_t)0x01000000)

#define

CAN_F9R1_FB25 ((uint32_t)0x02000000)

#define

CAN_F9R1_FB26 ((uint32_t)0x04000000)

#define

CAN_F9R1_FB27 ((uint32_t)0x08000000)

#define

CAN_F9R1_FB28 ((uint32_t)0x10000000)

#define

CAN_F9R1_FB29 ((uint32_t)0x20000000)

#define

CAN_F9R1_FB3 ((uint32_t)0x00000008)

#define

CAN_F9R1_FB30 ((uint32_t)0x40000000)

#define

CAN_F9R1_FB31 ((uint32_t)0x80000000)

#define

CAN_F9R1_FB4 ((uint32_t)0x00000010)

#define

CAN_F9R1_FB5 ((uint32_t)0x00000020)

#define

CAN_F9R1_FB6 ((uint32_t)0x00000040)

#define

CAN_F9R1_FB7 ((uint32_t)0x00000080)

#define

CAN_F9R1_FB8 ((uint32_t)0x00000100)

#define

CAN_F9R1_FB9 ((uint32_t)0x00000200)

#define

CAN_F9R2_FB0 ((uint32_t)0x00000001)

#define

CAN_F9R2_FB1 ((uint32_t)0x00000002)

#define

CAN_F9R2_FB10 ((uint32_t)0x00000400)

#define

CAN_F9R2_FB11 ((uint32_t)0x00000800)

#define

CAN_F9R2_FB12 ((uint32_t)0x00001000)

#define

CAN_F9R2_FB13 ((uint32_t)0x00002000)

#define

CAN_F9R2_FB14 ((uint32_t)0x00004000)

#define

CAN_F9R2_FB15 ((uint32_t)0x00008000)

#define

CAN_F9R2_FB16 ((uint32_t)0x00010000)

#define

CAN_F9R2_FB17 ((uint32_t)0x00020000)

#define

CAN_F9R2_FB18 ((uint32_t)0x00040000)

#define

CAN_F9R2_FB19 ((uint32_t)0x00080000)

#define

CAN_F9R2_FB2 ((uint32_t)0x00000004)

#define

CAN_F9R2_FB20 ((uint32_t)0x00100000)

#define

CAN_F9R2_FB21 ((uint32_t)0x00200000)

#define

CAN_F9R2_FB22 ((uint32_t)0x00400000)

#define

CAN_F9R2_FB23 ((uint32_t)0x00800000)

#define

CAN_F9R2_FB24 ((uint32_t)0x01000000)

#define

CAN_F9R2_FB25 ((uint32_t)0x02000000)

#define

CAN_F9R2_FB26 ((uint32_t)0x04000000)

#define

CAN_F9R2_FB27 ((uint32_t)0x08000000)

#define

CAN_F9R2_FB28 ((uint32_t)0x10000000)

#define

CAN_F9R2_FB29 ((uint32_t)0x20000000)

#define

CAN_F9R2_FB3 ((uint32_t)0x00000008)

#define

CAN_F9R2_FB30 ((uint32_t)0x40000000)

#define

CAN_F9R2_FB31 ((uint32_t)0x80000000)

#define

CAN_F9R2_FB4 ((uint32_t)0x00000010)

#define

CAN_F9R2_FB5 ((uint32_t)0x00000020)

#define

CAN_F9R2_FB6 ((uint32_t)0x00000040)

#define

CAN_F9R2_FB7 ((uint32_t)0x00000080)

#define

CAN_F9R2_FB8 ((uint32_t)0x00000100)

#define

CAN_F9R2_FB9 ((uint32_t)0x00000200)

#define

CAN_FA1R_FACT ((uint16_t)0x3FFF)

#define

CAN_FA1R_FACT0 ((uint16_t)0x0001)

#define

CAN_FA1R_FACT1 ((uint16_t)0x0002)

#define

CAN_FA1R_FACT10 ((uint16_t)0x0400)

#define

CAN_FA1R_FACT11 ((uint16_t)0x0800)

#define

CAN_FA1R_FACT12 ((uint16_t)0x1000)

#define

CAN_FA1R_FACT13 ((uint16_t)0x2000)

#define

CAN_FA1R_FACT2 ((uint16_t)0x0004)

#define

CAN_FA1R_FACT3 ((uint16_t)0x0008)

#define

CAN_FA1R_FACT4 ((uint16_t)0x0010)

#define

CAN_FA1R_FACT5 ((uint16_t)0x0020)

#define

CAN_FA1R_FACT6 ((uint16_t)0x0040)

#define

CAN_FA1R_FACT7 ((uint16_t)0x0080)

#define

CAN_FA1R_FACT8 ((uint16_t)0x0100)

#define

CAN_FA1R_FACT9 ((uint16_t)0x0200)

#define

CAN_FFA1R_FFA ((uint16_t)0x3FFF)

#define

CAN_FFA1R_FFA0 ((uint16_t)0x0001)

#define

CAN_FFA1R_FFA1 ((uint16_t)0x0002)

#define

CAN_FFA1R_FFA10 ((uint16_t)0x0400)

#define

CAN_FFA1R_FFA11 ((uint16_t)0x0800)

#define

CAN_FFA1R_FFA12 ((uint16_t)0x1000)

#define

CAN_FFA1R_FFA13 ((uint16_t)0x2000)

#define

CAN_FFA1R_FFA2 ((uint16_t)0x0004)

#define

CAN_FFA1R_FFA3 ((uint16_t)0x0008)

#define

CAN_FFA1R_FFA4 ((uint16_t)0x0010)

#define

CAN_FFA1R_FFA5 ((uint16_t)0x0020)

#define

CAN_FFA1R_FFA6 ((uint16_t)0x0040)

#define

CAN_FFA1R_FFA7 ((uint16_t)0x0080)

#define

CAN_FFA1R_FFA8 ((uint16_t)0x0100)

#define

CAN_FFA1R_FFA9 ((uint16_t)0x0200)

#define

CAN_FM1R_FBM ((uint16_t)0x3FFF)

#define

CAN_FM1R_FBM0 ((uint16_t)0x0001)

#define

CAN_FM1R_FBM1 ((uint16_t)0x0002)

#define

CAN_FM1R_FBM10 ((uint16_t)0x0400)

#define

CAN_FM1R_FBM11 ((uint16_t)0x0800)

#define

CAN_FM1R_FBM12 ((uint16_t)0x1000)

#define

CAN_FM1R_FBM13 ((uint16_t)0x2000)

#define

CAN_FM1R_FBM2 ((uint16_t)0x0004)

#define

CAN_FM1R_FBM3 ((uint16_t)0x0008)

#define

CAN_FM1R_FBM4 ((uint16_t)0x0010)

#define

CAN_FM1R_FBM5 ((uint16_t)0x0020)

#define

CAN_FM1R_FBM6 ((uint16_t)0x0040)

#define

CAN_FM1R_FBM7 ((uint16_t)0x0080)

#define

CAN_FM1R_FBM8 ((uint16_t)0x0100)

#define

CAN_FM1R_FBM9 ((uint16_t)0x0200)

#define

CAN_FMR_FINIT ((uint8_t)0x01)

#define

CAN_FS1R_FSC ((uint16_t)0x3FFF)

#define

CAN_FS1R_FSC0 ((uint16_t)0x0001)

#define

CAN_FS1R_FSC1 ((uint16_t)0x0002)

#define

CAN_FS1R_FSC10 ((uint16_t)0x0400)

#define

CAN_FS1R_FSC11 ((uint16_t)0x0800)

#define

CAN_FS1R_FSC12 ((uint16_t)0x1000)

#define

CAN_FS1R_FSC13 ((uint16_t)0x2000)

#define

CAN_FS1R_FSC2 ((uint16_t)0x0004)

#define

CAN_FS1R_FSC3 ((uint16_t)0x0008)

#define

CAN_FS1R_FSC4 ((uint16_t)0x0010)

#define

CAN_FS1R_FSC5 ((uint16_t)0x0020)

#define

CAN_FS1R_FSC6 ((uint16_t)0x0040)

#define

CAN_FS1R_FSC7 ((uint16_t)0x0080)

#define

CAN_FS1R_FSC8 ((uint16_t)0x0100)

#define

CAN_FS1R_FSC9 ((uint16_t)0x0200)

#define

CAN_IER_BOFIE ((uint32_t)0x00000400)

#define

CAN_IER_EPVIE ((uint32_t)0x00000200)

#define

CAN_IER_ERRIE ((uint32_t)0x00008000)

#define

CAN_IER_EWGIE ((uint32_t)0x00000100)

#define

CAN_IER_FFIE0 ((uint32_t)0x00000004)

#define

CAN_IER_FFIE1 ((uint32_t)0x00000020)

#define

CAN_IER_FMPIE0 ((uint32_t)0x00000002)

#define

CAN_IER_FMPIE1 ((uint32_t)0x00000010)

#define

CAN_IER_FOVIE0 ((uint32_t)0x00000008)

#define

CAN_IER_FOVIE1 ((uint32_t)0x00000040)

#define

CAN_IER_LECIE ((uint32_t)0x00000800)

#define

CAN_IER_SLKIE ((uint32_t)0x00020000)

#define

CAN_IER_TMEIE ((uint32_t)0x00000001)

#define

CAN_IER_WKUIE ((uint32_t)0x00010000)

#define

CAN_MCR_ABOM ((uint16_t)0x0040)

#define

CAN_MCR_AWUM ((uint16_t)0x0020)

#define

CAN_MCR_INRQ ((uint16_t)0x0001)

#define

CAN_MCR_NART ((uint16_t)0x0010)

#define

CAN_MCR_RESET ((uint16_t)0x8000)

#define

CAN_MCR_RFLM ((uint16_t)0x0008)

#define

CAN_MCR_SLEEP ((uint16_t)0x0002)

#define

CAN_MCR_TTCM ((uint16_t)0x0080)

#define

CAN_MCR_TXFP ((uint16_t)0x0004)

#define

CAN_MSR_ERRI ((uint16_t)0x0004)

#define

CAN_MSR_INAK ((uint16_t)0x0001)

#define

CAN_MSR_RX ((uint16_t)0x0800)

#define

CAN_MSR_RXM ((uint16_t)0x0200)

#define

CAN_MSR_SAMP ((uint16_t)0x0400)

#define

CAN_MSR_SLAK ((uint16_t)0x0002)

#define

CAN_MSR_SLAKI ((uint16_t)0x0010)

#define

CAN_MSR_TXM ((uint16_t)0x0100)

#define

CAN_MSR_WKUI ((uint16_t)0x0008)

#define

CAN_RDH0R_DATA4 ((uint32_t)0x000000FF)

#define

CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00)

#define

CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000)

#define

CAN_RDH0R_DATA7 ((uint32_t)0xFF000000)

#define

CAN_RDH1R_DATA4 ((uint32_t)0x000000FF)

#define

CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00)

#define

CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000)

#define

CAN_RDH1R_DATA7 ((uint32_t)0xFF000000)

#define

CAN_RDL0R_DATA0 ((uint32_t)0x000000FF)

#define

CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00)

#define

CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000)

#define

CAN_RDL0R_DATA3 ((uint32_t)0xFF000000)

#define

CAN_RDL1R_DATA0 ((uint32_t)0x000000FF)

#define

CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00)

#define

CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000)

#define

CAN_RDL1R_DATA3 ((uint32_t)0xFF000000)

#define

CAN_RDT0R_DLC ((uint32_t)0x0000000F)

#define

CAN_RDT0R_FMI ((uint32_t)0x0000FF00)

#define

CAN_RDT0R_TIME ((uint32_t)0xFFFF0000)

#define

CAN_RDT1R_DLC ((uint32_t)0x0000000F)

#define

CAN_RDT1R_FMI ((uint32_t)0x0000FF00)

#define

CAN_RDT1R_TIME ((uint32_t)0xFFFF0000)

#define

CAN_RF0R_FMP0 ((uint8_t)0x03)

#define

CAN_RF0R_FOVR0 ((uint8_t)0x10)

#define

CAN_RF0R_FULL0 ((uint8_t)0x08)

#define

CAN_RF0R_RFOM0 ((uint8_t)0x20)

#define

CAN_RF1R_FMP1 ((uint8_t)0x03)

#define

CAN_RF1R_FOVR1 ((uint8_t)0x10)

#define

CAN_RF1R_FULL1 ((uint8_t)0x08)

#define

CAN_RF1R_RFOM1 ((uint8_t)0x20)

#define

CAN_RI0R_EXID ((uint32_t)0x001FFFF8)

#define

CAN_RI0R_IDE ((uint32_t)0x00000004)

#define

CAN_RI0R_RTR ((uint32_t)0x00000002)

#define

CAN_RI0R_STID ((uint32_t)0xFFE00000)

#define

CAN_RI1R_EXID ((uint32_t)0x001FFFF8)

#define

CAN_RI1R_IDE ((uint32_t)0x00000004)

#define

CAN_RI1R_RTR ((uint32_t)0x00000002)

#define

CAN_RI1R_STID ((uint32_t)0xFFE00000)

#define

CAN_TDH0R_DATA4 ((uint32_t)0x000000FF)

#define

CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00)

#define

CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000)

#define

CAN_TDH0R_DATA7 ((uint32_t)0xFF000000)

#define

CAN_TDH1R_DATA4 ((uint32_t)0x000000FF)

#define

CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00)

#define

CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000)

#define

CAN_TDH1R_DATA7 ((uint32_t)0xFF000000)

#define

CAN_TDH2R_DATA4 ((uint32_t)0x000000FF)

#define

CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00)

#define

CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000)

#define

CAN_TDH2R_DATA7 ((uint32_t)0xFF000000)

#define

CAN_TDL0R_DATA0 ((uint32_t)0x000000FF)

#define

CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00)

#define

CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000)

#define

CAN_TDL0R_DATA3 ((uint32_t)0xFF000000)

#define

CAN_TDL1R_DATA0 ((uint32_t)0x000000FF)

#define

CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00)

#define

CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000)

#define

CAN_TDL1R_DATA3 ((uint32_t)0xFF000000)

#define

CAN_TDL2R_DATA0 ((uint32_t)0x000000FF)

#define

CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00)

#define

CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000)

#define

CAN_TDL2R_DATA3 ((uint32_t)0xFF000000)

#define

CAN_TDT0R_DLC ((uint32_t)0x0000000F)

#define

CAN_TDT0R_TGT ((uint32_t)0x00000100)

#define

CAN_TDT0R_TIME ((uint32_t)0xFFFF0000)

#define

CAN_TDT1R_DLC ((uint32_t)0x0000000F)

#define

CAN_TDT1R_TGT ((uint32_t)0x00000100)

#define

CAN_TDT1R_TIME ((uint32_t)0xFFFF0000)

#define

CAN_TDT2R_DLC ((uint32_t)0x0000000F)

#define

CAN_TDT2R_TGT ((uint32_t)0x00000100)

#define

CAN_TDT2R_TIME ((uint32_t)0xFFFF0000)

#define

CAN_TI0R_EXID ((uint32_t)0x001FFFF8)

#define

CAN_TI0R_IDE ((uint32_t)0x00000004)

#define

CAN_TI0R_RTR ((uint32_t)0x00000002)

#define

CAN_TI0R_STID ((uint32_t)0xFFE00000)

#define

CAN_TI0R_TXRQ ((uint32_t)0x00000001)

#define

CAN_TI1R_EXID ((uint32_t)0x001FFFF8)

#define

CAN_TI1R_IDE ((uint32_t)0x00000004)

#define

CAN_TI1R_RTR ((uint32_t)0x00000002)

#define

CAN_TI1R_STID ((uint32_t)0xFFE00000)

#define

CAN_TI1R_TXRQ ((uint32_t)0x00000001)

#define

CAN_TI2R_EXID ((uint32_t)0x001FFFF8)

#define

CAN_TI2R_IDE ((uint32_t)0x00000004)

#define

CAN_TI2R_RTR ((uint32_t)0x00000002)

#define

CAN_TI2R_STID ((uint32_t)0xFFE00000)

#define

CAN_TI2R_TXRQ ((uint32_t)0x00000001)

#define

CAN_TSR_ABRQ0 ((uint32_t)0x00000080)

#define

CAN_TSR_ABRQ1 ((uint32_t)0x00008000)

#define

CAN_TSR_ABRQ2 ((uint32_t)0x00800000)

#define

CAN_TSR_ALST0 ((uint32_t)0x00000004)

#define

CAN_TSR_ALST1 ((uint32_t)0x00000400)

#define

CAN_TSR_ALST2 ((uint32_t)0x00040000)

#define

CAN_TSR_CODE ((uint32_t)0x03000000)

#define

CAN_TSR_LOW ((uint32_t)0xE0000000)

#define

CAN_TSR_LOW0 ((uint32_t)0x20000000)

#define

CAN_TSR_LOW1 ((uint32_t)0x40000000)

#define

CAN_TSR_LOW2 ((uint32_t)0x80000000)

#define

CAN_TSR_RQCP0 ((uint32_t)0x00000001)

#define

CAN_TSR_RQCP1 ((uint32_t)0x00000100)

#define

CAN_TSR_RQCP2 ((uint32_t)0x00010000)

#define

CAN_TSR_TERR0 ((uint32_t)0x00000008)

#define

CAN_TSR_TERR1 ((uint32_t)0x00000800)

#define

CAN_TSR_TERR2 ((uint32_t)0x00080000)

#define

CAN_TSR_TME ((uint32_t)0x1C000000)

#define

CAN_TSR_TME0 ((uint32_t)0x04000000)

#define

CAN_TSR_TME1 ((uint32_t)0x08000000)

#define

CAN_TSR_TME2 ((uint32_t)0x10000000)

#define

CAN_TSR_TXOK0 ((uint32_t)0x00000002)

#define

CAN_TSR_TXOK1 ((uint32_t)0x00000200)

#define

CAN_TSR_TXOK2 ((uint32_t)0x00020000)

#define

CEC_CFGR_BPEM ((uint16_t)0x0008)

#define

CEC_CFGR_BTEM ((uint16_t)0x0004)

#define

CEC_CFGR_IE ((uint16_t)0x0002)

#define

CEC_CFGR_PE ((uint16_t)0x0001)

#define

CEC_CSR_RBTF ((uint16_t)0x0080)

#define

CEC_CSR_REOM ((uint16_t)0x0020)

#define

CEC_CSR_RERR ((uint16_t)0x0040)

#define

CEC_CSR_RSOM ((uint16_t)0x0010)

#define

CEC_CSR_TBTRF ((uint16_t)0x0008)

#define

CEC_CSR_TEOM ((uint16_t)0x0002)

#define

CEC_CSR_TERR ((uint16_t)0x0004)

#define

CEC_CSR_TSOM ((uint16_t)0x0001)

#define

CEC_ESR_ACKE ((uint16_t)0x0010)

#define

CEC_ESR_BPE ((uint16_t)0x0002)

#define

CEC_ESR_BTE ((uint16_t)0x0001)

#define

CEC_ESR_LINE ((uint16_t)0x0020)

#define

CEC_ESR_RBTFE ((uint16_t)0x0004)

#define

CEC_ESR_SBE ((uint16_t)0x0008)

#define

CEC_ESR_TBTFE ((uint16_t)0x0040)

#define

CEC_OAR_OA ((uint16_t)0x000F)

#define

CEC_OAR_OA_0 ((uint16_t)0x0001)

#define

CEC_OAR_OA_1 ((uint16_t)0x0002)

#define

CEC_OAR_OA_2 ((uint16_t)0x0004)

#define

CEC_OAR_OA_3 ((uint16_t)0x0008)

#define

CEC_PRES_PRES ((uint16_t)0x3FFF)

#define

CEC_RXD_RXD ((uint16_t)0x00FF)

#define

CEC_TXD_TXD ((uint16_t)0x00FF)

#define

CRC_CR_RESET ((uint8_t)0x01)

#define

CRC_DR_DR ((uint32_t)0xFFFFFFFF)

#define

CRC_IDR_IDR ((uint8_t)0xFF)

#define

DAC_CR_BOFF1 ((uint32_t)0x00000002)

#define

DAC_CR_BOFF2 ((uint32_t)0x00020000)

#define

DAC_CR_DMAEN1 ((uint32_t)0x00001000)

#define

DAC_CR_DMAEN2 ((uint32_t)0x10000000)

#define

DAC_CR_EN1 ((uint32_t)0x00000001)

#define

DAC_CR_EN2 ((uint32_t)0x00010000)

#define

DAC_CR_MAMP1 ((uint32_t)0x00000F00)

#define

DAC_CR_MAMP1_0 ((uint32_t)0x00000100)

#define

DAC_CR_MAMP1_1 ((uint32_t)0x00000200)

#define

DAC_CR_MAMP1_2 ((uint32_t)0x00000400)

#define

DAC_CR_MAMP1_3 ((uint32_t)0x00000800)

#define

DAC_CR_MAMP2 ((uint32_t)0x0F000000)

#define

DAC_CR_MAMP2_0 ((uint32_t)0x01000000)

#define

DAC_CR_MAMP2_1 ((uint32_t)0x02000000)

#define

DAC_CR_MAMP2_2 ((uint32_t)0x04000000)

#define

DAC_CR_MAMP2_3 ((uint32_t)0x08000000)

#define

DAC_CR_TEN1 ((uint32_t)0x00000004)

#define

DAC_CR_TEN2 ((uint32_t)0x00040000)

#define

DAC_CR_TSEL1 ((uint32_t)0x00000038)

#define

DAC_CR_TSEL1_0 ((uint32_t)0x00000008)

#define

DAC_CR_TSEL1_1 ((uint32_t)0x00000010)

#define

DAC_CR_TSEL1_2 ((uint32_t)0x00000020)

#define

DAC_CR_TSEL2 ((uint32_t)0x00380000)

#define

DAC_CR_TSEL2_0 ((uint32_t)0x00080000)

#define

DAC_CR_TSEL2_1 ((uint32_t)0x00100000)

#define

DAC_CR_TSEL2_2 ((uint32_t)0x00200000)

#define

DAC_CR_WAVE1 ((uint32_t)0x000000C0)

#define

DAC_CR_WAVE1_0 ((uint32_t)0x00000040)

#define

DAC_CR_WAVE1_1 ((uint32_t)0x00000080)

#define

DAC_CR_WAVE2 ((uint32_t)0x00C00000)

#define

DAC_CR_WAVE2_0 ((uint32_t)0x00400000)

#define

DAC_CR_WAVE2_1 ((uint32_t)0x00800000)

#define

DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0)

#define

DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0)

#define

DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0)

#define

DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000)

#define

DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF)

#define

DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF)

#define

DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF)

#define

DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000)

#define

DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF)

#define

DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF)

#define

DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF)

#define

DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00)

#define

DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF)

#define

DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF)

#define

DAC_SR_DMAUDR1 ((uint32_t)0x00002000)

#define

DAC_SR_DMAUDR2 ((uint32_t)0x20000000)

#define

DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01)

#define

DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02)

#define

DBGMCU_CR_DBG_CAN1_STOP ((uint32_t)0x00004000)

#define

DBGMCU_CR_DBG_CAN2_STOP ((uint32_t)0x00200000)

#define

DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000)

#define

DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000)

#define

DBGMCU_CR_DBG_IWDG_STOP ((uint32_t)0x00000100)

#define

DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001)

#define

DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004)

#define

DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002)

#define

DBGMCU_CR_DBG_TIM10_STOP ((uint32_t)0x20000000)

#define

DBGMCU_CR_DBG_TIM11_STOP ((uint32_t)0x40000000)

#define

DBGMCU_CR_DBG_TIM12_STOP ((uint32_t)0x02000000)

#define

DBGMCU_CR_DBG_TIM13_STOP ((uint32_t)0x04000000)

#define

DBGMCU_CR_DBG_TIM14_STOP ((uint32_t)0x08000000)

#define

DBGMCU_CR_DBG_TIM15_STOP ((uint32_t)0x00400000)

#define

DBGMCU_CR_DBG_TIM16_STOP ((uint32_t)0x00800000)

#define

DBGMCU_CR_DBG_TIM17_STOP ((uint32_t)0x01000000)

#define

DBGMCU_CR_DBG_TIM1_STOP ((uint32_t)0x00000400)

#define

DBGMCU_CR_DBG_TIM2_STOP ((uint32_t)0x00000800)

#define

DBGMCU_CR_DBG_TIM3_STOP ((uint32_t)0x00001000)

#define

DBGMCU_CR_DBG_TIM4_STOP ((uint32_t)0x00002000)

#define

DBGMCU_CR_DBG_TIM5_STOP ((uint32_t)0x00040000)

#define

DBGMCU_CR_DBG_TIM6_STOP ((uint32_t)0x00080000)

#define

DBGMCU_CR_DBG_TIM7_STOP ((uint32_t)0x00100000)

#define

DBGMCU_CR_DBG_TIM8_STOP ((uint32_t)0x00020000)

#define

DBGMCU_CR_DBG_TIM9_STOP ((uint32_t)0x10000000)

#define

DBGMCU_CR_DBG_WWDG_STOP ((uint32_t)0x00000200)

#define

DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020)

#define

DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0)

#define

DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040)

#define

DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080)

#define

DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF)

#define

DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000)

#define

DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000)

#define

DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000)

#define

DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000)

#define

DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000)

#define

DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000)

#define

DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000)

#define

DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000)

#define

DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000)

#define

DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000)

#define

DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000)

#define

DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000)

#define

DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000)

#define

DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000)

#define

DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000)

#define

DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000)

#define

DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000)

#define

DMA_CCR1_CIRC ((uint16_t)0x0020)

#define

DMA_CCR1_DIR ((uint16_t)0x0010)

#define

DMA_CCR1_EN ((uint16_t)0x0001)

#define

DMA_CCR1_HTIE ((uint16_t)0x0004)

#define

DMA_CCR1_MEM2MEM ((uint16_t)0x4000)

#define

DMA_CCR1_MINC ((uint16_t)0x0080)

#define

DMA_CCR1_MSIZE ((uint16_t)0x0C00)

#define

DMA_CCR1_MSIZE_0 ((uint16_t)0x0400)

#define

DMA_CCR1_MSIZE_1 ((uint16_t)0x0800)

#define

DMA_CCR1_PINC ((uint16_t)0x0040)

#define

DMA_CCR1_PL ((uint16_t)0x3000)

#define

DMA_CCR1_PL_0 ((uint16_t)0x1000)

#define

DMA_CCR1_PL_1 ((uint16_t)0x2000)

#define

DMA_CCR1_PSIZE ((uint16_t)0x0300)

#define

DMA_CCR1_PSIZE_0 ((uint16_t)0x0100)

#define

DMA_CCR1_PSIZE_1 ((uint16_t)0x0200)

#define

DMA_CCR1_TCIE ((uint16_t)0x0002)

#define

DMA_CCR1_TEIE ((uint16_t)0x0008)

#define

DMA_CCR2_CIRC ((uint16_t)0x0020)

#define

DMA_CCR2_DIR ((uint16_t)0x0010)

#define

DMA_CCR2_EN ((uint16_t)0x0001)

#define

DMA_CCR2_HTIE ((uint16_t)0x0004)

#define

DMA_CCR2_MEM2MEM ((uint16_t)0x4000)

#define

DMA_CCR2_MINC ((uint16_t)0x0080)

#define

DMA_CCR2_MSIZE ((uint16_t)0x0C00)

#define

DMA_CCR2_MSIZE_0 ((uint16_t)0x0400)

#define

DMA_CCR2_MSIZE_1 ((uint16_t)0x0800)

#define

DMA_CCR2_PINC ((uint16_t)0x0040)

#define

DMA_CCR2_PL ((uint16_t)0x3000)

#define

DMA_CCR2_PL_0 ((uint16_t)0x1000)

#define

DMA_CCR2_PL_1 ((uint16_t)0x2000)

#define

DMA_CCR2_PSIZE ((uint16_t)0x0300)

#define

DMA_CCR2_PSIZE_0 ((uint16_t)0x0100)

#define

DMA_CCR2_PSIZE_1 ((uint16_t)0x0200)

#define

DMA_CCR2_TCIE ((uint16_t)0x0002)

#define

DMA_CCR2_TEIE ((uint16_t)0x0008)

#define

DMA_CCR3_CIRC ((uint16_t)0x0020)

#define

DMA_CCR3_DIR ((uint16_t)0x0010)

#define

DMA_CCR3_EN ((uint16_t)0x0001)

#define

DMA_CCR3_HTIE ((uint16_t)0x0004)

#define

DMA_CCR3_MEM2MEM ((uint16_t)0x4000)

#define

DMA_CCR3_MINC ((uint16_t)0x0080)

#define

DMA_CCR3_MSIZE ((uint16_t)0x0C00)

#define

DMA_CCR3_MSIZE_0 ((uint16_t)0x0400)

#define

DMA_CCR3_MSIZE_1 ((uint16_t)0x0800)

#define

DMA_CCR3_PINC ((uint16_t)0x0040)

#define

DMA_CCR3_PL ((uint16_t)0x3000)

#define

DMA_CCR3_PL_0 ((uint16_t)0x1000)

#define

DMA_CCR3_PL_1 ((uint16_t)0x2000)

#define

DMA_CCR3_PSIZE ((uint16_t)0x0300)

#define

DMA_CCR3_PSIZE_0 ((uint16_t)0x0100)

#define

DMA_CCR3_PSIZE_1 ((uint16_t)0x0200)

#define

DMA_CCR3_TCIE ((uint16_t)0x0002)

#define

DMA_CCR3_TEIE ((uint16_t)0x0008)

#define

DMA_CCR4_CIRC ((uint16_t)0x0020)

#define

DMA_CCR4_DIR ((uint16_t)0x0010)

#define

DMA_CCR4_EN ((uint16_t)0x0001)

#define

DMA_CCR4_HTIE ((uint16_t)0x0004)

#define

DMA_CCR4_MEM2MEM ((uint16_t)0x4000)

#define

DMA_CCR4_MINC ((uint16_t)0x0080)

#define

DMA_CCR4_MSIZE ((uint16_t)0x0C00)

#define

DMA_CCR4_MSIZE_0 ((uint16_t)0x0400)

#define

DMA_CCR4_MSIZE_1 ((uint16_t)0x0800)

#define

DMA_CCR4_PINC ((uint16_t)0x0040)

#define

DMA_CCR4_PL ((uint16_t)0x3000)

#define

DMA_CCR4_PL_0 ((uint16_t)0x1000)

#define

DMA_CCR4_PL_1 ((uint16_t)0x2000)

#define

DMA_CCR4_PSIZE ((uint16_t)0x0300)

#define

DMA_CCR4_PSIZE_0 ((uint16_t)0x0100)

#define

DMA_CCR4_PSIZE_1 ((uint16_t)0x0200)

#define

DMA_CCR4_TCIE ((uint16_t)0x0002)

#define

DMA_CCR4_TEIE ((uint16_t)0x0008)

#define

DMA_CCR5_CIRC ((uint16_t)0x0020)

#define

DMA_CCR5_DIR ((uint16_t)0x0010)

#define

DMA_CCR5_EN ((uint16_t)0x0001)

#define

DMA_CCR5_HTIE ((uint16_t)0x0004)

#define

DMA_CCR5_MEM2MEM ((uint16_t)0x4000)

#define

DMA_CCR5_MINC ((uint16_t)0x0080)

#define

DMA_CCR5_MSIZE ((uint16_t)0x0C00)

#define

DMA_CCR5_MSIZE_0 ((uint16_t)0x0400)

#define

DMA_CCR5_MSIZE_1 ((uint16_t)0x0800)

#define

DMA_CCR5_PINC ((uint16_t)0x0040)

#define

DMA_CCR5_PL ((uint16_t)0x3000)

#define

DMA_CCR5_PL_0 ((uint16_t)0x1000)

#define

DMA_CCR5_PL_1 ((uint16_t)0x2000)

#define

DMA_CCR5_PSIZE ((uint16_t)0x0300)

#define

DMA_CCR5_PSIZE_0 ((uint16_t)0x0100)

#define

DMA_CCR5_PSIZE_1 ((uint16_t)0x0200)

#define

DMA_CCR5_TCIE ((uint16_t)0x0002)

#define

DMA_CCR5_TEIE ((uint16_t)0x0008)

#define

DMA_CCR6_CIRC ((uint16_t)0x0020)

#define

DMA_CCR6_DIR ((uint16_t)0x0010)

#define

DMA_CCR6_EN ((uint16_t)0x0001)

#define

DMA_CCR6_HTIE ((uint16_t)0x0004)

#define

DMA_CCR6_MEM2MEM ((uint16_t)0x4000)

#define

DMA_CCR6_MINC ((uint16_t)0x0080)

#define

DMA_CCR6_MSIZE ((uint16_t)0x0C00)

#define

DMA_CCR6_MSIZE_0 ((uint16_t)0x0400)

#define

DMA_CCR6_MSIZE_1 ((uint16_t)0x0800)

#define

DMA_CCR6_PINC ((uint16_t)0x0040)

#define

DMA_CCR6_PL ((uint16_t)0x3000)

#define

DMA_CCR6_PL_0 ((uint16_t)0x1000)

#define

DMA_CCR6_PL_1 ((uint16_t)0x2000)

#define

DMA_CCR6_PSIZE ((uint16_t)0x0300)

#define

DMA_CCR6_PSIZE_0 ((uint16_t)0x0100)

#define

DMA_CCR6_PSIZE_1 ((uint16_t)0x0200)

#define

DMA_CCR6_TCIE ((uint16_t)0x0002)

#define

DMA_CCR6_TEIE ((uint16_t)0x0008)

#define

DMA_CCR7_CIRC ((uint16_t)0x0020)

#define

DMA_CCR7_DIR ((uint16_t)0x0010)

#define

DMA_CCR7_EN ((uint16_t)0x0001)

#define

DMA_CCR7_HTIE ((uint16_t)0x0004)

#define

DMA_CCR7_MEM2MEM ((uint16_t)0x4000)

#define

DMA_CCR7_MINC ((uint16_t)0x0080)

#define

DMA_CCR7_MSIZE ((uint16_t)0x0C00)

#define

DMA_CCR7_MSIZE_0 ((uint16_t)0x0400)

#define

DMA_CCR7_MSIZE_1 ((uint16_t)0x0800)

#define

DMA_CCR7_PINC ((uint16_t)0x0040)

#define

DMA_CCR7_PL ((uint16_t)0x3000)

#define

DMA_CCR7_PL_0 ((uint16_t)0x1000)

#define

DMA_CCR7_PL_1 ((uint16_t)0x2000)

#define

DMA_CCR7_PSIZE , ((uint16_t)0x0300)

#define

DMA_CCR7_PSIZE_0 ((uint16_t)0x0100)

#define

DMA_CCR7_PSIZE_1 ((uint16_t)0x0200)

#define

DMA_CCR7_TCIE ((uint16_t)0x0002)

#define

DMA_CCR7_TEIE ((uint16_t)0x0008)

#define

DMA_CMAR1_MA ((uint32_t)0xFFFFFFFF)

#define

DMA_CMAR2_MA ((uint32_t)0xFFFFFFFF)

#define

DMA_CMAR3_MA ((uint32_t)0xFFFFFFFF)

#define

DMA_CMAR4_MA ((uint32_t)0xFFFFFFFF)

#define

DMA_CMAR5_MA ((uint32_t)0xFFFFFFFF)

#define

DMA_CMAR6_MA ((uint32_t)0xFFFFFFFF)

#define

DMA_CMAR7_MA ((uint32_t)0xFFFFFFFF)

#define

DMA_CNDTR1_NDT ((uint16_t)0xFFFF)

#define

DMA_CNDTR2_NDT ((uint16_t)0xFFFF)

#define

DMA_CNDTR3_NDT ((uint16_t)0xFFFF)

#define

DMA_CNDTR4_NDT ((uint16_t)0xFFFF)

#define

DMA_CNDTR5_NDT ((uint16_t)0xFFFF)

#define

DMA_CNDTR6_NDT ((uint16_t)0xFFFF)

#define

DMA_CNDTR7_NDT ((uint16_t)0xFFFF)

#define

DMA_CPAR1_PA ((uint32_t)0xFFFFFFFF)

#define

DMA_CPAR2_PA ((uint32_t)0xFFFFFFFF)

#define

DMA_CPAR3_PA ((uint32_t)0xFFFFFFFF)

#define

DMA_CPAR4_PA ((uint32_t)0xFFFFFFFF)

#define

DMA_CPAR5_PA ((uint32_t)0xFFFFFFFF)

#define

DMA_CPAR6_PA ((uint32_t)0xFFFFFFFF)

#define

DMA_CPAR7_PA ((uint32_t)0xFFFFFFFF)

#define

DMA_IFCR_CGIF1 ((uint32_t)0x00000001)

#define

DMA_IFCR_CGIF2 ((uint32_t)0x00000010)

#define

DMA_IFCR_CGIF3 ((uint32_t)0x00000100)

#define

DMA_IFCR_CGIF4 ((uint32_t)0x00001000)

#define

DMA_IFCR_CGIF5 ((uint32_t)0x00010000)

#define

DMA_IFCR_CGIF6 ((uint32_t)0x00100000)

#define

DMA_IFCR_CGIF7 ((uint32_t)0x01000000)

#define

DMA_IFCR_CHTIF1 ((uint32_t)0x00000004)

#define

DMA_IFCR_CHTIF2 ((uint32_t)0x00000040)

#define

DMA_IFCR_CHTIF3 ((uint32_t)0x00000400)

#define

DMA_IFCR_CHTIF4 ((uint32_t)0x00004000)

#define

DMA_IFCR_CHTIF5 ((uint32_t)0x00040000)

#define

DMA_IFCR_CHTIF6 ((uint32_t)0x00400000)

#define

DMA_IFCR_CHTIF7 ((uint32_t)0x04000000)

#define

DMA_IFCR_CTCIF1 ((uint32_t)0x00000002)

#define

DMA_IFCR_CTCIF2 ((uint32_t)0x00000020)

#define

DMA_IFCR_CTCIF3 ((uint32_t)0x00000200)

#define

DMA_IFCR_CTCIF4 ((uint32_t)0x00002000)

#define

DMA_IFCR_CTCIF5 ((uint32_t)0x00020000)

#define

DMA_IFCR_CTCIF6 ((uint32_t)0x00200000)

#define

DMA_IFCR_CTCIF7 ((uint32_t)0x02000000)

#define

DMA_IFCR_CTEIF1 ((uint32_t)0x00000008)

#define

DMA_IFCR_CTEIF2 ((uint32_t)0x00000080)

#define

DMA_IFCR_CTEIF3 ((uint32_t)0x00000800)

#define

DMA_IFCR_CTEIF4 ((uint32_t)0x00008000)

#define

DMA_IFCR_CTEIF5 ((uint32_t)0x00080000)

#define

DMA_IFCR_CTEIF6 ((uint32_t)0x00800000)

#define

DMA_IFCR_CTEIF7 ((uint32_t)0x08000000)

#define

DMA_ISR_GIF1 ((uint32_t)0x00000001)

#define

DMA_ISR_GIF2 ((uint32_t)0x00000010)

#define

DMA_ISR_GIF3 ((uint32_t)0x00000100)

#define

DMA_ISR_GIF4 ((uint32_t)0x00001000)

#define

DMA_ISR_GIF5 ((uint32_t)0x00010000)

#define

DMA_ISR_GIF6 ((uint32_t)0x00100000)

#define

DMA_ISR_GIF7 ((uint32_t)0x01000000)

#define

DMA_ISR_HTIF1 ((uint32_t)0x00000004)

#define

DMA_ISR_HTIF2 ((uint32_t)0x00000040)

#define

DMA_ISR_HTIF3 ((uint32_t)0x00000400)

#define

DMA_ISR_HTIF4 ((uint32_t)0x00004000)

#define

DMA_ISR_HTIF5 ((uint32_t)0x00040000)

#define

DMA_ISR_HTIF6 ((uint32_t)0x00400000)

#define

DMA_ISR_HTIF7 ((uint32_t)0x04000000)

#define

DMA_ISR_TCIF1 ((uint32_t)0x00000002)

#define

DMA_ISR_TCIF2 ((uint32_t)0x00000020)

#define

DMA_ISR_TCIF3 ((uint32_t)0x00000200)

#define

DMA_ISR_TCIF4 ((uint32_t)0x00002000)

#define

DMA_ISR_TCIF5 ((uint32_t)0x00020000)

#define

DMA_ISR_TCIF6 ((uint32_t)0x00200000)

#define

DMA_ISR_TCIF7 ((uint32_t)0x02000000)

#define

DMA_ISR_TEIF1 ((uint32_t)0x00000008)

#define

DMA_ISR_TEIF2 ((uint32_t)0x00000080)

#define

DMA_ISR_TEIF3 ((uint32_t)0x00000800)

#define

DMA_ISR_TEIF4 ((uint32_t)0x00008000)

#define

DMA_ISR_TEIF5 ((uint32_t)0x00080000)

#define

DMA_ISR_TEIF6 ((uint32_t)0x00800000)

#define

DMA_ISR_TEIF7 ((uint32_t)0x08000000)

#define

EXTI_EMR_MR0 ((uint32_t)0x00000001)

#define

EXTI_EMR_MR1 ((uint32_t)0x00000002)

#define

EXTI_EMR_MR10 ((uint32_t)0x00000400)

#define

EXTI_EMR_MR11 ((uint32_t)0x00000800)

#define

EXTI_EMR_MR12 ((uint32_t)0x00001000)

#define

EXTI_EMR_MR13 ((uint32_t)0x00002000)

#define

EXTI_EMR_MR14 ((uint32_t)0x00004000)

#define

EXTI_EMR_MR15 ((uint32_t)0x00008000)

#define

EXTI_EMR_MR16 ((uint32_t)0x00010000)

#define

EXTI_EMR_MR17 ((uint32_t)0x00020000)

#define

EXTI_EMR_MR18 ((uint32_t)0x00040000)

#define

EXTI_EMR_MR19 ((uint32_t)0x00080000)

#define

EXTI_EMR_MR2 ((uint32_t)0x00000004)

#define

EXTI_EMR_MR3 ((uint32_t)0x00000008)

#define

EXTI_EMR_MR4 ((uint32_t)0x00000010)

#define

EXTI_EMR_MR5 ((uint32_t)0x00000020)

#define

EXTI_EMR_MR6 ((uint32_t)0x00000040)

#define

EXTI_EMR_MR7 ((uint32_t)0x00000080)

#define

EXTI_EMR_MR8 ((uint32_t)0x00000100)

#define

EXTI_EMR_MR9 ((uint32_t)0x00000200)

#define

EXTI_FTSR_TR0 ((uint32_t)0x00000001)

#define

EXTI_FTSR_TR1 ((uint32_t)0x00000002)

#define

EXTI_FTSR_TR10 ((uint32_t)0x00000400)

#define

EXTI_FTSR_TR11 ((uint32_t)0x00000800)

#define

EXTI_FTSR_TR12 ((uint32_t)0x00001000)

#define

EXTI_FTSR_TR13 ((uint32_t)0x00002000)

#define

EXTI_FTSR_TR14 ((uint32_t)0x00004000)

#define

EXTI_FTSR_TR15 ((uint32_t)0x00008000)

#define

EXTI_FTSR_TR16 ((uint32_t)0x00010000)

#define

EXTI_FTSR_TR17 ((uint32_t)0x00020000)

#define

EXTI_FTSR_TR18 ((uint32_t)0x00040000)

#define

EXTI_FTSR_TR19 ((uint32_t)0x00080000)

#define

EXTI_FTSR_TR2 ((uint32_t)0x00000004)

#define

EXTI_FTSR_TR3 ((uint32_t)0x00000008)

#define

EXTI_FTSR_TR4 ((uint32_t)0x00000010)

#define

EXTI_FTSR_TR5 ((uint32_t)0x00000020)

#define

EXTI_FTSR_TR6 ((uint32_t)0x00000040)

#define

EXTI_FTSR_TR7 ((uint32_t)0x00000080)

#define

EXTI_FTSR_TR8 ((uint32_t)0x00000100)

#define

EXTI_FTSR_TR9 ((uint32_t)0x00000200)

#define

EXTI_IMR_MR0 ((uint32_t)0x00000001)

#define

EXTI_IMR_MR1 ((uint32_t)0x00000002)

#define

EXTI_IMR_MR10 ((uint32_t)0x00000400)

#define

EXTI_IMR_MR11 ((uint32_t)0x00000800)

#define

EXTI_IMR_MR12 ((uint32_t)0x00001000)

#define

EXTI_IMR_MR13 ((uint32_t)0x00002000)

#define

EXTI_IMR_MR14 ((uint32_t)0x00004000)

#define

EXTI_IMR_MR15 ((uint32_t)0x00008000)

#define

EXTI_IMR_MR16 ((uint32_t)0x00010000)

#define

EXTI_IMR_MR17 ((uint32_t)0x00020000)

#define

EXTI_IMR_MR18 ((uint32_t)0x00040000)

#define

EXTI_IMR_MR19 ((uint32_t)0x00080000)

#define

EXTI_IMR_MR2 ((uint32_t)0x00000004)

#define

EXTI_IMR_MR3 ((uint32_t)0x00000008)

#define

EXTI_IMR_MR4 ((uint32_t)0x00000010)

#define

EXTI_IMR_MR5 ((uint32_t)0x00000020)

#define

EXTI_IMR_MR6 ((uint32_t)0x00000040)

#define

EXTI_IMR_MR7 ((uint32_t)0x00000080)

#define

EXTI_IMR_MR8 ((uint32_t)0x00000100)

#define

EXTI_IMR_MR9 ((uint32_t)0x00000200)

#define

EXTI_PR_PR0 ((uint32_t)0x00000001)

#define

EXTI_PR_PR1 ((uint32_t)0x00000002)

#define

EXTI_PR_PR10 ((uint32_t)0x00000400)

#define

EXTI_PR_PR11 ((uint32_t)0x00000800)

#define

EXTI_PR_PR12 ((uint32_t)0x00001000)

#define

EXTI_PR_PR13 ((uint32_t)0x00002000)

#define

EXTI_PR_PR14 ((uint32_t)0x00004000)

#define

EXTI_PR_PR15 ((uint32_t)0x00008000)

#define

EXTI_PR_PR16 ((uint32_t)0x00010000)

#define

EXTI_PR_PR17 ((uint32_t)0x00020000)

#define

EXTI_PR_PR18 ((uint32_t)0x00040000)

#define

EXTI_PR_PR19 ((uint32_t)0x00080000)

#define

EXTI_PR_PR2 ((uint32_t)0x00000004)

#define

EXTI_PR_PR3 ((uint32_t)0x00000008)

#define

EXTI_PR_PR4 ((uint32_t)0x00000010)

#define

EXTI_PR_PR5 ((uint32_t)0x00000020)

#define

EXTI_PR_PR6 ((uint32_t)0x00000040)

#define

EXTI_PR_PR7 ((uint32_t)0x00000080)

#define

EXTI_PR_PR8 ((uint32_t)0x00000100)

#define

EXTI_PR_PR9 ((uint32_t)0x00000200)

#define

EXTI_RTSR_TR0 ((uint32_t)0x00000001)

#define

EXTI_RTSR_TR1 ((uint32_t)0x00000002)

#define

EXTI_RTSR_TR10 ((uint32_t)0x00000400)

#define

EXTI_RTSR_TR11 ((uint32_t)0x00000800)

#define

EXTI_RTSR_TR12 ((uint32_t)0x00001000)

#define

EXTI_RTSR_TR13 ((uint32_t)0x00002000)

#define

EXTI_RTSR_TR14 ((uint32_t)0x00004000)

#define

EXTI_RTSR_TR15 ((uint32_t)0x00008000)

#define

EXTI_RTSR_TR16 ((uint32_t)0x00010000)

#define

EXTI_RTSR_TR17 ((uint32_t)0x00020000)

#define

EXTI_RTSR_TR18 ((uint32_t)0x00040000)

#define

EXTI_RTSR_TR19 ((uint32_t)0x00080000)

#define

EXTI_RTSR_TR2 ((uint32_t)0x00000004)

#define

EXTI_RTSR_TR3 ((uint32_t)0x00000008)

#define

EXTI_RTSR_TR4 ((uint32_t)0x00000010)

#define

EXTI_RTSR_TR5 ((uint32_t)0x00000020)

#define

EXTI_RTSR_TR6 ((uint32_t)0x00000040)

#define

EXTI_RTSR_TR7 ((uint32_t)0x00000080)

#define

EXTI_RTSR_TR8 ((uint32_t)0x00000100)

#define

EXTI_RTSR_TR9 ((uint32_t)0x00000200)

#define

EXTI_SWIER_SWIER0 ((uint32_t)0x00000001)

#define

EXTI_SWIER_SWIER1 ((uint32_t)0x00000002)

#define

EXTI_SWIER_SWIER10 ((uint32_t)0x00000400)

#define

EXTI_SWIER_SWIER11 ((uint32_t)0x00000800)

#define

EXTI_SWIER_SWIER12 ((uint32_t)0x00001000)

#define

EXTI_SWIER_SWIER13 ((uint32_t)0x00002000)

#define

EXTI_SWIER_SWIER14 ((uint32_t)0x00004000)

#define

EXTI_SWIER_SWIER15 ((uint32_t)0x00008000)

#define

EXTI_SWIER_SWIER16 ((uint32_t)0x00010000)

#define

EXTI_SWIER_SWIER17 ((uint32_t)0x00020000)

#define

EXTI_SWIER_SWIER18 ((uint32_t)0x00040000)

#define

EXTI_SWIER_SWIER19 ((uint32_t)0x00080000)

#define

EXTI_SWIER_SWIER2 ((uint32_t)0x00000004)

#define

EXTI_SWIER_SWIER3 ((uint32_t)0x00000008)

#define

EXTI_SWIER_SWIER4 ((uint32_t)0x00000010)

#define

EXTI_SWIER_SWIER5 ((uint32_t)0x00000020)

#define

EXTI_SWIER_SWIER6 ((uint32_t)0x00000040)

#define

EXTI_SWIER_SWIER7 ((uint32_t)0x00000080)

#define

EXTI_SWIER_SWIER8 ((uint32_t)0x00000100)

#define

EXTI_SWIER_SWIER9 ((uint32_t)0x00000200)

#define

FLASH_ACR_HLFCYA ((uint8_t)0x08)

#define

FLASH_ACR_LATENCY ((uint8_t)0x03)

#define

FLASH_ACR_LATENCY_0 ((uint8_t)0x00)

#define

FLASH_ACR_LATENCY_1 ((uint8_t)0x01)

#define

FLASH_ACR_LATENCY_2 ((uint8_t)0x02)

#define

FLASH_ACR_PRFTBE ((uint8_t)0x10)

#define

FLASH_ACR_PRFTBS ((uint8_t)0x20)

#define

FLASH_AR_FAR ((uint32_t)0xFFFFFFFF)

#define

FLASH_CR_EOPIE ((uint16_t)0x1000)

#define

FLASH_CR_ERRIE ((uint16_t)0x0400)

#define

FLASH_CR_LOCK ((uint16_t)0x0080)

#define

FLASH_CR_MER ((uint16_t)0x0004)

#define

FLASH_CR_OPTER ((uint16_t)0x0020)

#define

FLASH_CR_OPTPG ((uint16_t)0x0010)

#define

FLASH_CR_OPTWRE ((uint16_t)0x0200)

#define

FLASH_CR_PER ((uint16_t)0x0002)

#define

FLASH_CR_PG ((uint16_t)0x0001)

#define

FLASH_CR_STRT ((uint16_t)0x0040)

#define

FLASH_Data0_Data0 ((uint32_t)0x000000FF)

#define

FLASH_Data0_nData0 ((uint32_t)0x0000FF00)

#define

FLASH_Data1_Data1 ((uint32_t)0x00FF0000)

#define

FLASH_Data1_nData1 ((uint32_t)0xFF000000)

#define

FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF)

#define

FLASH_OBR_BFB2 ((uint16_t)0x0020)

#define

FLASH_OBR_nRST_STDBY ((uint16_t)0x0010)

#define

FLASH_OBR_nRST_STOP ((uint16_t)0x0008)

#define

FLASH_OBR_OPTERR ((uint16_t)0x0001)

#define

FLASH_OBR_RDPRT ((uint16_t)0x0002)

#define

FLASH_OBR_USER ((uint16_t)0x03FC)

#define

FLASH_OBR_WDG_SW ((uint16_t)0x0004)

#define

FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF)

#define

FLASH_RDP_nRDP ((uint32_t)0x0000FF00)

#define

FLASH_RDP_RDP ((uint32_t)0x000000FF)

#define

FLASH_SR_BSY ((uint8_t)0x01)

#define

FLASH_SR_EOP ((uint8_t)0x20)

#define

FLASH_SR_PGERR ((uint8_t)0x04)

#define

FLASH_SR_WRPRTERR ((uint8_t)0x10)

#define

FLASH_USER_nUSER ((uint32_t)0xFF000000)

#define

FLASH_USER_USER ((uint32_t)0x00FF0000)

#define

FLASH_WRP0_nWRP0 ((uint32_t)0x0000FF00)

#define

FLASH_WRP0_WRP0 ((uint32_t)0x000000FF)

#define

FLASH_WRP1_nWRP1 ((uint32_t)0xFF000000)

#define

FLASH_WRP1_WRP1 ((uint32_t)0x00FF0000)

#define

FLASH_WRP2_nWRP2 ((uint32_t)0x0000FF00)

#define

FLASH_WRP2_WRP2 ((uint32_t)0x000000FF)

#define

FLASH_WRP3_nWRP3 ((uint32_t)0xFF000000)

#define

FLASH_WRP3_WRP3 ((uint32_t)0x00FF0000)

#define

FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF)

#define

FSMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000)

#define

FSMC_BCR1_BURSTEN ((uint32_t)0x00000100)

#define

FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000)

#define

FSMC_BCR1_EXTMOD ((uint32_t)0x00004000)

#define

FSMC_BCR1_FACCEN ((uint32_t)0x00000040)

#define

FSMC_BCR1_MBKEN ((uint32_t)0x00000001)

#define

FSMC_BCR1_MTYP ((uint32_t)0x0000000C)

#define

FSMC_BCR1_MTYP_0 ((uint32_t)0x00000004)

#define

FSMC_BCR1_MTYP_1 ((uint32_t)0x00000008)

#define

FSMC_BCR1_MUXEN ((uint32_t)0x00000002)

#define

FSMC_BCR1_MWID ((uint32_t)0x00000030)

#define

FSMC_BCR1_MWID_0 ((uint32_t)0x00000010)

#define

FSMC_BCR1_MWID_1 ((uint32_t)0x00000020)

#define

FSMC_BCR1_WAITCFG ((uint32_t)0x00000800)

#define

FSMC_BCR1_WAITEN ((uint32_t)0x00002000)

#define

FSMC_BCR1_WAITPOL ((uint32_t)0x00000200)

#define

FSMC_BCR1_WRAPMOD ((uint32_t)0x00000400)

#define

FSMC_BCR1_WREN ((uint32_t)0x00001000)

#define

FSMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000)

#define

FSMC_BCR2_BURSTEN ((uint32_t)0x00000100)

#define

FSMC_BCR2_CBURSTRW ((uint32_t)0x00080000)

#define

FSMC_BCR2_EXTMOD ((uint32_t)0x00004000)

#define

FSMC_BCR2_FACCEN ((uint32_t)0x00000040)

#define

FSMC_BCR2_MBKEN ((uint32_t)0x00000001)

#define

FSMC_BCR2_MTYP ((uint32_t)0x0000000C)

#define

FSMC_BCR2_MTYP_0 ((uint32_t)0x00000004)

#define

FSMC_BCR2_MTYP_1 ((uint32_t)0x00000008)

#define

FSMC_BCR2_MUXEN ((uint32_t)0x00000002)

#define

FSMC_BCR2_MWID ((uint32_t)0x00000030)

#define

FSMC_BCR2_MWID_0 ((uint32_t)0x00000010)

#define

FSMC_BCR2_MWID_1 ((uint32_t)0x00000020)

#define

FSMC_BCR2_WAITCFG ((uint32_t)0x00000800)

#define

FSMC_BCR2_WAITEN ((uint32_t)0x00002000)

#define

FSMC_BCR2_WAITPOL ((uint32_t)0x00000200)

#define

FSMC_BCR2_WRAPMOD ((uint32_t)0x00000400)

#define

FSMC_BCR2_WREN ((uint32_t)0x00001000)

#define

FSMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000)

#define

FSMC_BCR3_BURSTEN ((uint32_t)0x00000100)

#define

FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000)

#define

FSMC_BCR3_EXTMOD ((uint32_t)0x00004000)

#define

FSMC_BCR3_FACCEN ((uint32_t)0x00000040)

#define

FSMC_BCR3_MBKEN ((uint32_t)0x00000001)

#define

FSMC_BCR3_MTYP ((uint32_t)0x0000000C)

#define

FSMC_BCR3_MTYP_0 ((uint32_t)0x00000004)

#define

FSMC_BCR3_MTYP_1 ((uint32_t)0x00000008)

#define

FSMC_BCR3_MUXEN ((uint32_t)0x00000002)

#define

FSMC_BCR3_MWID ((uint32_t)0x00000030)

#define

FSMC_BCR3_MWID_0 ((uint32_t)0x00000010)

#define

FSMC_BCR3_MWID_1 ((uint32_t)0x00000020)

#define

FSMC_BCR3_WAITCFG ((uint32_t)0x00000800)

#define

FSMC_BCR3_WAITEN ((uint32_t)0x00002000)

#define

FSMC_BCR3_WAITPOL ((uint32_t)0x00000200)

#define

FSMC_BCR3_WRAPMOD ((uint32_t)0x00000400)

#define

FSMC_BCR3_WREN ((uint32_t)0x00001000)

#define

FSMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000)

#define

FSMC_BCR4_BURSTEN ((uint32_t)0x00000100)

#define

FSMC_BCR4_CBURSTRW ((uint32_t)0x00080000)

#define

FSMC_BCR4_EXTMOD ((uint32_t)0x00004000)

#define

FSMC_BCR4_FACCEN ((uint32_t)0x00000040)

#define

FSMC_BCR4_MBKEN ((uint32_t)0x00000001)

#define

FSMC_BCR4_MTYP ((uint32_t)0x0000000C)

#define

FSMC_BCR4_MTYP_0 ((uint32_t)0x00000004)

#define

FSMC_BCR4_MTYP_1 ((uint32_t)0x00000008)

#define

FSMC_BCR4_MUXEN ((uint32_t)0x00000002)

#define

FSMC_BCR4_MWID ((uint32_t)0x00000030)

#define

FSMC_BCR4_MWID_0 ((uint32_t)0x00000010)

#define

FSMC_BCR4_MWID_1 ((uint32_t)0x00000020)

#define

FSMC_BCR4_WAITCFG ((uint32_t)0x00000800)

#define

FSMC_BCR4_WAITEN ((uint32_t)0x00002000)

#define

FSMC_BCR4_WAITPOL ((uint32_t)0x00000200)

#define

FSMC_BCR4_WRAPMOD ((uint32_t)0x00000400)

#define

FSMC_BCR4_WREN ((uint32_t)0x00001000)

#define

FSMC_BTR1_ACCMOD ((uint32_t)0x30000000)

#define

FSMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000)

#define

FSMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000)

#define

FSMC_BTR1_ADDHLD ((uint32_t)0x000000F0)

#define

FSMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010)

#define

FSMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020)

#define

FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040)

#define

FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080)

#define

FSMC_BTR1_ADDSET ((uint32_t)0x0000000F)

#define

FSMC_BTR1_ADDSET_0 ((uint32_t)0x00000001)

#define

FSMC_BTR1_ADDSET_1 ((uint32_t)0x00000002)

#define

FSMC_BTR1_ADDSET_2 ((uint32_t)0x00000004)

#define

FSMC_BTR1_ADDSET_3 ((uint32_t)0x00000008)

#define

FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000)

#define

FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000)

#define

FSMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000)

#define

FSMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000)

#define

FSMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000)

#define

FSMC_BTR1_CLKDIV ((uint32_t)0x00F00000)

#define

FSMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000)

#define

FSMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000)

#define

FSMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000)

#define

FSMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000)

#define

FSMC_BTR1_DATAST ((uint32_t)0x0000FF00)

#define

FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100)

#define

FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200)

#define

FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400)

#define

FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800)

#define

FSMC_BTR1_DATLAT ((uint32_t)0x0F000000)

#define

FSMC_BTR1_DATLAT_0 ((uint32_t)0x01000000)

#define

FSMC_BTR1_DATLAT_1 ((uint32_t)0x02000000)

#define

FSMC_BTR1_DATLAT_2 ((uint32_t)0x04000000)

#define

FSMC_BTR1_DATLAT_3 ((uint32_t)0x08000000)

#define

FSMC_BTR2_ACCMOD ((uint32_t)0x30000000)

#define

FSMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000)

#define

FSMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000)

#define

FSMC_BTR2_ADDHLD ((uint32_t)0x000000F0)

#define

FSMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010)

#define

FSMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020)

#define

FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040)

#define

FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080)

#define

FSMC_BTR2_ADDSET ((uint32_t)0x0000000F)

#define

FSMC_BTR2_ADDSET_0 ((uint32_t)0x00000001)

#define

FSMC_BTR2_ADDSET_1 ((uint32_t)0x00000002)

#define

FSMC_BTR2_ADDSET_2 ((uint32_t)0x00000004)

#define

FSMC_BTR2_ADDSET_3 ((uint32_t)0x00000008)

#define

FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000)

#define

FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000)

#define

FSMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000)

#define

FSMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000)

#define

FSMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000)

#define

FSMC_BTR2_CLKDIV ((uint32_t)0x00F00000)

#define

FSMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000)

#define

FSMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000)

#define

FSMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000)

#define

FSMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000)

#define

FSMC_BTR2_DATAST ((uint32_t)0x0000FF00)

#define

FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100)

#define

FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200)

#define

FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400)

#define

FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800)

#define

FSMC_BTR2_DATLAT ((uint32_t)0x0F000000)

#define

FSMC_BTR2_DATLAT_0 ((uint32_t)0x01000000)

#define

FSMC_BTR2_DATLAT_1 ((uint32_t)0x02000000)

#define

FSMC_BTR2_DATLAT_2 ((uint32_t)0x04000000)

#define

FSMC_BTR2_DATLAT_3 ((uint32_t)0x08000000)

#define

FSMC_BTR3_ACCMOD ((uint32_t)0x30000000)

#define

FSMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000)

#define

FSMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000)

#define

FSMC_BTR3_ADDHLD ((uint32_t)0x000000F0)

#define

FSMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010)

#define

FSMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020)

#define

FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040)

#define

FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080)

#define

FSMC_BTR3_ADDSET ((uint32_t)0x0000000F)

#define

FSMC_BTR3_ADDSET_0 ((uint32_t)0x00000001)

#define

FSMC_BTR3_ADDSET_1 ((uint32_t)0x00000002)

#define

FSMC_BTR3_ADDSET_2 ((uint32_t)0x00000004)

#define

FSMC_BTR3_ADDSET_3 ((uint32_t)0x00000008)

#define

FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000)

#define

FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000)

#define

FSMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000)

#define

FSMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000)

#define

FSMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000)

#define

FSMC_BTR3_CLKDIV ((uint32_t)0x00F00000)

#define

FSMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000)

#define

FSMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000)

#define

FSMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000)

#define

FSMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000)

#define

FSMC_BTR3_DATAST ((uint32_t)0x0000FF00)

#define

FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100)

#define

FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200)

#define

FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400)

#define

FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800)

#define

FSMC_BTR3_DATLAT ((uint32_t)0x0F000000)

#define

FSMC_BTR3_DATLAT_0 ((uint32_t)0x01000000)

#define

FSMC_BTR3_DATLAT_1 ((uint32_t)0x02000000)

#define

FSMC_BTR3_DATLAT_2 ((uint32_t)0x04000000)

#define

FSMC_BTR3_DATLAT_3 ((uint32_t)0x08000000)

#define

FSMC_BTR4_ACCMOD ((uint32_t)0x30000000)

#define

FSMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000)

#define

FSMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000)

#define

FSMC_BTR4_ADDHLD ((uint32_t)0x000000F0)

#define

FSMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010)

#define

FSMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020)

#define

FSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040)

#define

FSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080)

#define

FSMC_BTR4_ADDSET ((uint32_t)0x0000000F)

#define

FSMC_BTR4_ADDSET_0 ((uint32_t)0x00000001)

#define

FSMC_BTR4_ADDSET_1 ((uint32_t)0x00000002)

#define

FSMC_BTR4_ADDSET_2 ((uint32_t)0x00000004)

#define

FSMC_BTR4_ADDSET_3 ((uint32_t)0x00000008)

#define

FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000)

#define

FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000)

#define

FSMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000)

#define

FSMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000)

#define

FSMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000)

#define

FSMC_BTR4_CLKDIV ((uint32_t)0x00F00000)

#define

FSMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000)

#define

FSMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000)

#define

FSMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000)

#define

FSMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000)

#define

FSMC_BTR4_DATAST ((uint32_t)0x0000FF00)

#define

FSMC_BTR4_DATAST_0 ((uint32_t)0x00000100)

#define

FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200)

#define

FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400)

#define

FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800)

#define

FSMC_BTR4_DATLAT ((uint32_t)0x0F000000)

#define

FSMC_BTR4_DATLAT_0 ((uint32_t)0x01000000)

#define

FSMC_BTR4_DATLAT_1 ((uint32_t)0x02000000)

#define

FSMC_BTR4_DATLAT_2 ((uint32_t)0x04000000)

#define

FSMC_BTR4_DATLAT_3 ((uint32_t)0x08000000)

#define

FSMC_BWTR1_ACCMOD ((uint32_t)0x30000000)

#define

FSMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000)

#define

FSMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000)

#define

FSMC_BWTR1_ADDHLD ((uint32_t)0x000000F0)

#define

FSMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010)

#define

FSMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020)

#define

FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040)

#define

FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080)

#define

FSMC_BWTR1_ADDSET ((uint32_t)0x0000000F)

#define

FSMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001)

#define

FSMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002)

#define

FSMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004)

#define

FSMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008)

#define

FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000)

#define

FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000)

#define

FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000)

#define

FSMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000)

#define

FSMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000)

#define

FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00)

#define

FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100)

#define

FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200)

#define

FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400)

#define

FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800)

#define

FSMC_BWTR1_DATLAT ((uint32_t)0x0F000000)

#define

FSMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000)

#define

FSMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000)

#define

FSMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000)

#define

FSMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000)

#define

FSMC_BWTR2_ACCMOD ((uint32_t)0x30000000)

#define

FSMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000)

#define

FSMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000)

#define

FSMC_BWTR2_ADDHLD ((uint32_t)0x000000F0)

#define

FSMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010)

#define

FSMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020)

#define

FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040)

#define

FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080)

#define

FSMC_BWTR2_ADDSET ((uint32_t)0x0000000F)

#define

FSMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001)

#define

FSMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002)

#define

FSMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004)

#define

FSMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008)

#define

FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000)

#define

FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000)

#define

FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000)

#define

FSMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000)

#define

FSMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000)

#define

FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00)

#define

FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100)

#define

FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200)

#define

FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400)

#define

FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800)

#define

FSMC_BWTR2_DATLAT ((uint32_t)0x0F000000)

#define

FSMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000)

#define

FSMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000)

#define

FSMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000)

#define

FSMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000)

#define

FSMC_BWTR3_ACCMOD ((uint32_t)0x30000000)

#define

FSMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000)

#define

FSMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000)

#define

FSMC_BWTR3_ADDHLD ((uint32_t)0x000000F0)

#define

FSMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010)

#define

FSMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020)

#define

FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040)

#define

FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080)

#define

FSMC_BWTR3_ADDSET ((uint32_t)0x0000000F)

#define

FSMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001)

#define

FSMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002)

#define

FSMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004)

#define

FSMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008)

#define

FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000)

#define

FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000)

#define

FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000)

#define

FSMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000)

#define

FSMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000)

#define

FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00)

#define

FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100)

#define

FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200)

#define

FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400)

#define

FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800)

#define

FSMC_BWTR3_DATLAT ((uint32_t)0x0F000000)

#define

FSMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000)

#define

FSMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000)

#define

FSMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000)

#define

FSMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000)

#define

FSMC_BWTR4_ACCMOD ((uint32_t)0x30000000)

#define

FSMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000)

#define

FSMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000)

#define

FSMC_BWTR4_ADDHLD ((uint32_t)0x000000F0)

#define

FSMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010)

#define

FSMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020)

#define

FSMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040)

#define

FSMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080)

#define

FSMC_BWTR4_ADDSET ((uint32_t)0x0000000F)

#define

FSMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001)

#define

FSMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002)

#define

FSMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004)

#define

FSMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008)

#define

FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000)

#define

FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000)

#define

FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000)

#define

FSMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000)

#define

FSMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000)

#define

FSMC_BWTR4_DATAST ((uint32_t)0x0000FF00)

#define

FSMC_BWTR4_DATAST_0 ((uint32_t)0x00000100)

#define

FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200)

#define

FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400)

#define

FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800)

#define

FSMC_BWTR4_DATLAT ((uint32_t)0x0F000000)

#define

FSMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000)

#define

FSMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000)

#define

FSMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000)

#define

FSMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000)

#define

FSMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF)

#define

FSMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF)

#define

FSMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000)

#define

FSMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000)

#define

FSMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000)

#define

FSMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000)

#define

FSMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000)

#define

FSMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000)

#define

FSMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000)

#define

FSMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000)

#define

FSMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000)

#define

FSMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000)

#define

FSMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000)

#define

FSMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000)

#define

FSMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000)

#define

FSMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000)

#define

FSMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000)

#define

FSMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000)

#define

FSMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000)

#define

FSMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000)

#define

FSMC_PATT2_ATTSET2 ((uint32_t)0x000000FF)

#define

FSMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001)

#define

FSMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002)

#define

FSMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004)

#define

FSMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008)

#define

FSMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010)

#define

FSMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020)

#define

FSMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040)

#define

FSMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080)

#define

FSMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00)

#define

FSMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100)

#define

FSMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200)

#define

FSMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400)

#define

FSMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800)

#define

FSMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000)

#define

FSMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000)

#define

FSMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000)

#define

FSMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000)

#define

FSMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000)

#define

FSMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000)

#define

FSMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000)

#define

FSMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000)

#define

FSMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000)

#define

FSMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000)

#define

FSMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000)

#define

FSMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000)

#define

FSMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000)

#define

FSMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000)

#define

FSMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000)

#define

FSMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000)

#define

FSMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000)

#define

FSMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000)

#define

FSMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000)

#define

FSMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000)

#define

FSMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000)

#define

FSMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000)

#define

FSMC_PATT3_ATTSET3 ((uint32_t)0x000000FF)

#define

FSMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001)

#define

FSMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002)

#define

FSMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004)

#define

FSMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008)

#define

FSMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010)

#define

FSMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020)

#define

FSMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040)

#define

FSMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080)

#define

FSMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00)

#define

FSMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100)

#define

FSMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200)

#define

FSMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400)

#define

FSMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800)

#define

FSMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000)

#define

FSMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000)

#define

FSMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000)

#define

FSMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000)

#define

FSMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000)

#define

FSMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000)

#define

FSMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000)

#define

FSMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000)

#define

FSMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000)

#define

FSMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000)

#define

FSMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000)

#define

FSMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000)

#define

FSMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000)

#define

FSMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000)

#define

FSMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000)

#define

FSMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000)

#define

FSMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000)

#define

FSMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000)

#define

FSMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000)

#define

FSMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000)

#define

FSMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000)

#define

FSMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000)

#define

FSMC_PATT4_ATTSET4 ((uint32_t)0x000000FF)

#define

FSMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001)

#define

FSMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002)

#define

FSMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004)

#define

FSMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008)

#define

FSMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010)

#define

FSMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020)

#define

FSMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040)

#define

FSMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080)

#define

FSMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00)

#define

FSMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100)

#define

FSMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200)

#define

FSMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400)

#define

FSMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800)

#define

FSMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000)

#define

FSMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000)

#define

FSMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000)

#define

FSMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000)

#define

FSMC_PCR2_ECCEN ((uint32_t)0x00000040)

#define

FSMC_PCR2_ECCPS ((uint32_t)0x000E0000)

#define

FSMC_PCR2_ECCPS_0 ((uint32_t)0x00020000)

#define

FSMC_PCR2_ECCPS_1 ((uint32_t)0x00040000)

#define

FSMC_PCR2_ECCPS_2 ((uint32_t)0x00080000)

#define

FSMC_PCR2_PBKEN ((uint32_t)0x00000004)

#define

FSMC_PCR2_PTYP ((uint32_t)0x00000008)

#define

FSMC_PCR2_PWAITEN ((uint32_t)0x00000002)

#define

FSMC_PCR2_PWID ((uint32_t)0x00000030)

#define

FSMC_PCR2_PWID_0 ((uint32_t)0x00000010)

#define

FSMC_PCR2_PWID_1 ((uint32_t)0x00000020)

#define

FSMC_PCR2_TAR ((uint32_t)0x0001E000)

#define

FSMC_PCR2_TAR_0 ((uint32_t)0x00002000)

#define

FSMC_PCR2_TAR_1 ((uint32_t)0x00004000)

#define

FSMC_PCR2_TAR_2 ((uint32_t)0x00008000)

#define

FSMC_PCR2_TAR_3 ((uint32_t)0x00010000)

#define

FSMC_PCR2_TCLR ((uint32_t)0x00001E00)

#define

FSMC_PCR2_TCLR_0 ((uint32_t)0x00000200)

#define

FSMC_PCR2_TCLR_1 ((uint32_t)0x00000400)

#define

FSMC_PCR2_TCLR_2 ((uint32_t)0x00000800)

#define

FSMC_PCR2_TCLR_3 ((uint32_t)0x00001000)

#define

FSMC_PCR3_ECCEN ((uint32_t)0x00000040)

#define

FSMC_PCR3_ECCPS ((uint32_t)0x000E0000)

#define

FSMC_PCR3_ECCPS_0 ((uint32_t)0x00020000)

#define

FSMC_PCR3_ECCPS_1 ((uint32_t)0x00040000)

#define

FSMC_PCR3_ECCPS_2 ((uint32_t)0x00080000)

#define

FSMC_PCR3_PBKEN ((uint32_t)0x00000004)

#define

FSMC_PCR3_PTYP ((uint32_t)0x00000008)

#define

FSMC_PCR3_PWAITEN ((uint32_t)0x00000002)

#define

FSMC_PCR3_PWID ((uint32_t)0x00000030)

#define

FSMC_PCR3_PWID_0 ((uint32_t)0x00000010)

#define

FSMC_PCR3_PWID_1 ((uint32_t)0x00000020)

#define

FSMC_PCR3_TAR ((uint32_t)0x0001E000)

#define

FSMC_PCR3_TAR_0 ((uint32_t)0x00002000)

#define

FSMC_PCR3_TAR_1 ((uint32_t)0x00004000)

#define

FSMC_PCR3_TAR_2 ((uint32_t)0x00008000)

#define

FSMC_PCR3_TAR_3 ((uint32_t)0x00010000)

#define

FSMC_PCR3_TCLR ((uint32_t)0x00001E00)

#define

FSMC_PCR3_TCLR_0 ((uint32_t)0x00000200)

#define

FSMC_PCR3_TCLR_1 ((uint32_t)0x00000400)

#define

FSMC_PCR3_TCLR_2 ((uint32_t)0x00000800)

#define

FSMC_PCR3_TCLR_3 ((uint32_t)0x00001000)

#define

FSMC_PCR4_ECCEN ((uint32_t)0x00000040)

#define

FSMC_PCR4_ECCPS ((uint32_t)0x000E0000)

#define

FSMC_PCR4_ECCPS_0 ((uint32_t)0x00020000)

#define

FSMC_PCR4_ECCPS_1 ((uint32_t)0x00040000)

#define

FSMC_PCR4_ECCPS_2 ((uint32_t)0x00080000)

#define

FSMC_PCR4_PBKEN ((uint32_t)0x00000004)

#define

FSMC_PCR4_PTYP ((uint32_t)0x00000008)

#define

FSMC_PCR4_PWAITEN ((uint32_t)0x00000002)

#define

FSMC_PCR4_PWID ((uint32_t)0x00000030)

#define

FSMC_PCR4_PWID_0 ((uint32_t)0x00000010)

#define

FSMC_PCR4_PWID_1 ((uint32_t)0x00000020)

#define

FSMC_PCR4_TAR ((uint32_t)0x0001E000)

#define

FSMC_PCR4_TAR_0 ((uint32_t)0x00002000)

#define

FSMC_PCR4_TAR_1 ((uint32_t)0x00004000)

#define

FSMC_PCR4_TAR_2 ((uint32_t)0x00008000)

#define

FSMC_PCR4_TAR_3 ((uint32_t)0x00010000)

#define

FSMC_PCR4_TCLR ((uint32_t)0x00001E00)

#define

FSMC_PCR4_TCLR_0 ((uint32_t)0x00000200)

#define

FSMC_PCR4_TCLR_1 ((uint32_t)0x00000400)

#define

FSMC_PCR4_TCLR_2 ((uint32_t)0x00000800)

#define

FSMC_PCR4_TCLR_3 ((uint32_t)0x00001000)

#define

FSMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000)

#define

FSMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000)

#define

FSMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000)

#define

FSMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000)

#define

FSMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000)

#define

FSMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000)

#define

FSMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000)

#define

FSMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000)

#define

FSMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000)

#define

FSMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000)

#define

FSMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000)

#define

FSMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000)

#define

FSMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000)

#define

FSMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000)

#define

FSMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000)

#define

FSMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000)

#define

FSMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000)

#define

FSMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000)

#define

FSMC_PIO4_IOSET4 ((uint32_t)0x000000FF)

#define

FSMC_PIO4_IOSET4_0 ((uint32_t)0x00000001)

#define

FSMC_PIO4_IOSET4_1 ((uint32_t)0x00000002)

#define

FSMC_PIO4_IOSET4_2 ((uint32_t)0x00000004)

#define

FSMC_PIO4_IOSET4_3 ((uint32_t)0x00000008)

#define

FSMC_PIO4_IOSET4_4 ((uint32_t)0x00000010)

#define

FSMC_PIO4_IOSET4_5 ((uint32_t)0x00000020)

#define

FSMC_PIO4_IOSET4_6 ((uint32_t)0x00000040)

#define

FSMC_PIO4_IOSET4_7 ((uint32_t)0x00000080)

#define

FSMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00)

#define

FSMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100)

#define

FSMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200)

#define

FSMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400)

#define

FSMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800)

#define

FSMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000)

#define

FSMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000)

#define

FSMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000)

#define

FSMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000)

#define

FSMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000)

#define

FSMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000)

#define

FSMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000)

#define

FSMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000)

#define

FSMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000)

#define

FSMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000)

#define

FSMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000)

#define

FSMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000)

#define

FSMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000)

#define

FSMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000)

#define

FSMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000)

#define

FSMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000)

#define

FSMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000)

#define

FSMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000)

#define

FSMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000)

#define

FSMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000)

#define

FSMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000)

#define

FSMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000)

#define

FSMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF)

#define

FSMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001)

#define

FSMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002)

#define

FSMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004)

#define

FSMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008)

#define

FSMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010)

#define

FSMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020)

#define

FSMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040)

#define

FSMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080)

#define

FSMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00)

#define

FSMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100)

#define

FSMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200)

#define

FSMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400)

#define

FSMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800)

#define

FSMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000)

#define

FSMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000)

#define

FSMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000)

#define

FSMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000)

#define

FSMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000)

#define

FSMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000)

#define

FSMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000)

#define

FSMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000)

#define

FSMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000)

#define

FSMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000)

#define

FSMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000)

#define

FSMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000)

#define

FSMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000)

#define

FSMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000)

#define

FSMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000)

#define

FSMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000)

#define

FSMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000)

#define

FSMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000)

#define

FSMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000)

#define

FSMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000)

#define

FSMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000)

#define

FSMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000)

#define

FSMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF)

#define

FSMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001)

#define

FSMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002)

#define

FSMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004)

#define

FSMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008)

#define

FSMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010)

#define

FSMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020)

#define

FSMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040)

#define

FSMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080)

#define

FSMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00)

#define

FSMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100)

#define

FSMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200)

#define

FSMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400)

#define

FSMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800)

#define

FSMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000)

#define

FSMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000)

#define

FSMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000)

#define

FSMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000)

#define

FSMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000)

#define

FSMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000)

#define

FSMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000)

#define

FSMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000)

#define

FSMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000)

#define

FSMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000)

#define

FSMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000)

#define

FSMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000)

#define

FSMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000)

#define

FSMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000)

#define

FSMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000)

#define

FSMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000)

#define

FSMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000)

#define

FSMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000)

#define

FSMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000)

#define

FSMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000)

#define

FSMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000)

#define

FSMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000)

#define

FSMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF)

#define

FSMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001)

#define

FSMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002)

#define

FSMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004)

#define

FSMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008)

#define

FSMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010)

#define

FSMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020)

#define

FSMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040)

#define

FSMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080)

#define

FSMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00)

#define

FSMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100)

#define

FSMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200)

#define

FSMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400)

#define

FSMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800)

#define

FSMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000)

#define

FSMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000)

#define

FSMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000)

#define

FSMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000)

#define

FSMC_SR2_FEMPT ((uint8_t)0x40)

#define

FSMC_SR2_IFEN ((uint8_t)0x20)

#define

FSMC_SR2_IFS ((uint8_t)0x04)

#define

FSMC_SR2_ILEN ((uint8_t)0x10)

#define

FSMC_SR2_ILS ((uint8_t)0x02)

#define

FSMC_SR2_IREN ((uint8_t)0x08)

#define

FSMC_SR2_IRS ((uint8_t)0x01)

#define

FSMC_SR3_FEMPT ((uint8_t)0x40)

#define

FSMC_SR3_IFEN ((uint8_t)0x20)

#define

FSMC_SR3_IFS ((uint8_t)0x04)

#define

FSMC_SR3_ILEN ((uint8_t)0x10)

#define

FSMC_SR3_ILS ((uint8_t)0x02)

#define

FSMC_SR3_IREN ((uint8_t)0x08)

#define

FSMC_SR3_IRS ((uint8_t)0x01)

#define

FSMC_SR4_FEMPT ((uint8_t)0x40)

#define

FSMC_SR4_IFEN ((uint8_t)0x20)

#define

FSMC_SR4_IFS ((uint8_t)0x04)

#define

FSMC_SR4_ILEN ((uint8_t)0x10)

#define

FSMC_SR4_ILS ((uint8_t)0x02)

#define

FSMC_SR4_IREN ((uint8_t)0x08)

#define

FSMC_SR4_IRS ((uint8_t)0x01)

#define

GPIO_BRR_BR0 ((uint16_t)0x0001)

#define

GPIO_BRR_BR1 ((uint16_t)0x0002)

#define

GPIO_BRR_BR10 ((uint16_t)0x0400)

#define

GPIO_BRR_BR11 ((uint16_t)0x0800)

#define

GPIO_BRR_BR12 ((uint16_t)0x1000)

#define

GPIO_BRR_BR13 ((uint16_t)0x2000)

#define

GPIO_BRR_BR14 ((uint16_t)0x4000)

#define

GPIO_BRR_BR15 ((uint16_t)0x8000)

#define

GPIO_BRR_BR2 ((uint16_t)0x0004)

#define

GPIO_BRR_BR3 ((uint16_t)0x0008)

#define

GPIO_BRR_BR4 ((uint16_t)0x0010)

#define

GPIO_BRR_BR5 ((uint16_t)0x0020)

#define

GPIO_BRR_BR6 ((uint16_t)0x0040)

#define

GPIO_BRR_BR7 ((uint16_t)0x0080)

#define

GPIO_BRR_BR8 ((uint16_t)0x0100)

#define

GPIO_BRR_BR9 ((uint16_t)0x0200)

#define

GPIO_BSRR_BR0 ((uint32_t)0x00010000)

#define

GPIO_BSRR_BR1 ((uint32_t)0x00020000)

#define

GPIO_BSRR_BR10 ((uint32_t)0x04000000)

#define

GPIO_BSRR_BR11 ((uint32_t)0x08000000)

#define

GPIO_BSRR_BR12 ((uint32_t)0x10000000)

#define

GPIO_BSRR_BR13 ((uint32_t)0x20000000)

#define

GPIO_BSRR_BR14 ((uint32_t)0x40000000)

#define

GPIO_BSRR_BR15 ((uint32_t)0x80000000)

#define

GPIO_BSRR_BR2 ((uint32_t)0x00040000)

#define

GPIO_BSRR_BR3 ((uint32_t)0x00080000)

#define

GPIO_BSRR_BR4 ((uint32_t)0x00100000)

#define

GPIO_BSRR_BR5 ((uint32_t)0x00200000)

#define

GPIO_BSRR_BR6 ((uint32_t)0x00400000)

#define

GPIO_BSRR_BR7 ((uint32_t)0x00800000)

#define

GPIO_BSRR_BR8 ((uint32_t)0x01000000)

#define

GPIO_BSRR_BR9 ((uint32_t)0x02000000)

#define

GPIO_BSRR_BS0 ((uint32_t)0x00000001)

#define

GPIO_BSRR_BS1 ((uint32_t)0x00000002)

#define

GPIO_BSRR_BS10 ((uint32_t)0x00000400)

#define

GPIO_BSRR_BS11 ((uint32_t)0x00000800)

#define

GPIO_BSRR_BS12 ((uint32_t)0x00001000)

#define

GPIO_BSRR_BS13 ((uint32_t)0x00002000)

#define

GPIO_BSRR_BS14 ((uint32_t)0x00004000)

#define

GPIO_BSRR_BS15 ((uint32_t)0x00008000)

#define

GPIO_BSRR_BS2 ((uint32_t)0x00000004)

#define

GPIO_BSRR_BS3 ((uint32_t)0x00000008)

#define

GPIO_BSRR_BS4 ((uint32_t)0x00000010)

#define

GPIO_BSRR_BS5 ((uint32_t)0x00000020)

#define

GPIO_BSRR_BS6 ((uint32_t)0x00000040)

#define

GPIO_BSRR_BS7 ((uint32_t)0x00000080)

#define

GPIO_BSRR_BS8 ((uint32_t)0x00000100)

#define

GPIO_BSRR_BS9 ((uint32_t)0x00000200)

#define

GPIO_CRH_CNF ((uint32_t)0xCCCCCCCC)

#define

GPIO_CRH_CNF10 ((uint32_t)0x00000C00)

#define

GPIO_CRH_CNF10_0 ((uint32_t)0x00000400)

#define

GPIO_CRH_CNF10_1 ((uint32_t)0x00000800)

#define

GPIO_CRH_CNF11 ((uint32_t)0x0000C000)

#define

GPIO_CRH_CNF11_0 ((uint32_t)0x00004000)

#define

GPIO_CRH_CNF11_1 ((uint32_t)0x00008000)

#define

GPIO_CRH_CNF12 ((uint32_t)0x000C0000)

#define

GPIO_CRH_CNF12_0 ((uint32_t)0x00040000)

#define

GPIO_CRH_CNF12_1 ((uint32_t)0x00080000)

#define

GPIO_CRH_CNF13 ((uint32_t)0x00C00000)

#define

GPIO_CRH_CNF13_0 ((uint32_t)0x00400000)

#define

GPIO_CRH_CNF13_1 ((uint32_t)0x00800000)

#define

GPIO_CRH_CNF14 ((uint32_t)0x0C000000)

#define

GPIO_CRH_CNF14_0 ((uint32_t)0x04000000)

#define

GPIO_CRH_CNF14_1 ((uint32_t)0x08000000)

#define

GPIO_CRH_CNF15 ((uint32_t)0xC0000000)

#define

GPIO_CRH_CNF15_0 ((uint32_t)0x40000000)

#define

GPIO_CRH_CNF15_1 ((uint32_t)0x80000000)

#define

GPIO_CRH_CNF8 ((uint32_t)0x0000000C)

#define

GPIO_CRH_CNF8_0 ((uint32_t)0x00000004)

#define

GPIO_CRH_CNF8_1 ((uint32_t)0x00000008)

#define

GPIO_CRH_CNF9 ((uint32_t)0x000000C0)

#define

GPIO_CRH_CNF9_0 ((uint32_t)0x00000040)

#define

GPIO_CRH_CNF9_1 ((uint32_t)0x00000080)

#define

GPIO_CRH_MODE ((uint32_t)0x33333333)

#define

GPIO_CRH_MODE10 ((uint32_t)0x00000300)

#define

GPIO_CRH_MODE10_0 ((uint32_t)0x00000100)

#define

GPIO_CRH_MODE10_1 ((uint32_t)0x00000200)

#define

GPIO_CRH_MODE11 ((uint32_t)0x00003000)

#define

GPIO_CRH_MODE11_0 ((uint32_t)0x00001000)

#define

GPIO_CRH_MODE11_1 ((uint32_t)0x00002000)

#define

GPIO_CRH_MODE12 ((uint32_t)0x00030000)

#define

GPIO_CRH_MODE12_0 ((uint32_t)0x00010000)

#define

GPIO_CRH_MODE12_1 ((uint32_t)0x00020000)

#define

GPIO_CRH_MODE13 ((uint32_t)0x00300000)

#define

GPIO_CRH_MODE13_0 ((uint32_t)0x00100000)

#define

GPIO_CRH_MODE13_1 ((uint32_t)0x00200000)

#define

GPIO_CRH_MODE14 ((uint32_t)0x03000000)

#define

GPIO_CRH_MODE14_0 ((uint32_t)0x01000000)

#define

GPIO_CRH_MODE14_1 ((uint32_t)0x02000000)

#define

GPIO_CRH_MODE15 ((uint32_t)0x30000000)

#define

GPIO_CRH_MODE15_0 ((uint32_t)0x10000000)

#define

GPIO_CRH_MODE15_1 ((uint32_t)0x20000000)

#define

GPIO_CRH_MODE8 ((uint32_t)0x00000003)

#define

GPIO_CRH_MODE8_0 ((uint32_t)0x00000001)

#define

GPIO_CRH_MODE8_1 ((uint32_t)0x00000002)

#define

GPIO_CRH_MODE9 ((uint32_t)0x00000030)

#define

GPIO_CRH_MODE9_0 ((uint32_t)0x00000010)

#define

GPIO_CRH_MODE9_1 ((uint32_t)0x00000020)

#define

GPIO_CRL_CNF ((uint32_t)0xCCCCCCCC)

#define

GPIO_CRL_CNF0 ((uint32_t)0x0000000C)

#define

GPIO_CRL_CNF0_0 ((uint32_t)0x00000004)

#define

GPIO_CRL_CNF0_1 ((uint32_t)0x00000008)

#define

GPIO_CRL_CNF1 ((uint32_t)0x000000C0)

#define

GPIO_CRL_CNF1_0 ((uint32_t)0x00000040)

#define

GPIO_CRL_CNF1_1 ((uint32_t)0x00000080)

#define

GPIO_CRL_CNF2 ((uint32_t)0x00000C00)

#define

GPIO_CRL_CNF2_0 ((uint32_t)0x00000400)

#define

GPIO_CRL_CNF2_1 ((uint32_t)0x00000800)

#define

GPIO_CRL_CNF3 ((uint32_t)0x0000C000)

#define

GPIO_CRL_CNF3_0 ((uint32_t)0x00004000)

#define

GPIO_CRL_CNF3_1 ((uint32_t)0x00008000)

#define

GPIO_CRL_CNF4 ((uint32_t)0x000C0000)

#define

GPIO_CRL_CNF4_0 ((uint32_t)0x00040000)

#define

GPIO_CRL_CNF4_1 ((uint32_t)0x00080000)

#define

GPIO_CRL_CNF5 ((uint32_t)0x00C00000)

#define

GPIO_CRL_CNF5_0 ((uint32_t)0x00400000)

#define

GPIO_CRL_CNF5_1 ((uint32_t)0x00800000)

#define

GPIO_CRL_CNF6 ((uint32_t)0x0C000000)

#define

GPIO_CRL_CNF6_0 ((uint32_t)0x04000000)

#define

GPIO_CRL_CNF6_1 ((uint32_t)0x08000000)

#define

GPIO_CRL_CNF7 ((uint32_t)0xC0000000)

#define

GPIO_CRL_CNF7_0 ((uint32_t)0x40000000)

#define

GPIO_CRL_CNF7_1 ((uint32_t)0x80000000)

#define

GPIO_CRL_MODE ((uint32_t)0x33333333)

#define

GPIO_CRL_MODE0 ((uint32_t)0x00000003)

#define

GPIO_CRL_MODE0_0 ((uint32_t)0x00000001)

#define

GPIO_CRL_MODE0_1 ((uint32_t)0x00000002)

#define

GPIO_CRL_MODE1 ((uint32_t)0x00000030)

#define

GPIO_CRL_MODE1_0 ((uint32_t)0x00000010)

#define

GPIO_CRL_MODE1_1 ((uint32_t)0x00000020)

#define

GPIO_CRL_MODE2 ((uint32_t)0x00000300)

#define

GPIO_CRL_MODE2_0 ((uint32_t)0x00000100)

#define

GPIO_CRL_MODE2_1 ((uint32_t)0x00000200)

#define

GPIO_CRL_MODE3 ((uint32_t)0x00003000)

#define

GPIO_CRL_MODE3_0 ((uint32_t)0x00001000)

#define

GPIO_CRL_MODE3_1 ((uint32_t)0x00002000)

#define

GPIO_CRL_MODE4 ((uint32_t)0x00030000)

#define

GPIO_CRL_MODE4_0 ((uint32_t)0x00010000)

#define

GPIO_CRL_MODE4_1 ((uint32_t)0x00020000)

#define

GPIO_CRL_MODE5 ((uint32_t)0x00300000)

#define

GPIO_CRL_MODE5_0 ((uint32_t)0x00100000)

#define

GPIO_CRL_MODE5_1 ((uint32_t)0x00200000)

#define

GPIO_CRL_MODE6 ((uint32_t)0x03000000)

#define

GPIO_CRL_MODE6_0 ((uint32_t)0x01000000)

#define

GPIO_CRL_MODE6_1 ((uint32_t)0x02000000)

#define

GPIO_CRL_MODE7 ((uint32_t)0x30000000)

#define

GPIO_CRL_MODE7_0 ((uint32_t)0x10000000)

#define

GPIO_CRL_MODE7_1 ((uint32_t)0x20000000)

#define

GPIO_IDR_IDR0 ((uint16_t)0x0001)

#define

GPIO_IDR_IDR1 ((uint16_t)0x0002)

#define

GPIO_IDR_IDR10 ((uint16_t)0x0400)

#define

GPIO_IDR_IDR11 ((uint16_t)0x0800)

#define

GPIO_IDR_IDR12 ((uint16_t)0x1000)

#define

GPIO_IDR_IDR13 ((uint16_t)0x2000)

#define

GPIO_IDR_IDR14 ((uint16_t)0x4000)

#define

GPIO_IDR_IDR15 ((uint16_t)0x8000)

#define

GPIO_IDR_IDR2 ((uint16_t)0x0004)

#define

GPIO_IDR_IDR3 ((uint16_t)0x0008)

#define

GPIO_IDR_IDR4 ((uint16_t)0x0010)

#define

GPIO_IDR_IDR5 ((uint16_t)0x0020)

#define

GPIO_IDR_IDR6 ((uint16_t)0x0040)

#define

GPIO_IDR_IDR7 ((uint16_t)0x0080)

#define

GPIO_IDR_IDR8 ((uint16_t)0x0100)

#define

GPIO_IDR_IDR9 ((uint16_t)0x0200)

#define

GPIO_LCKR_LCK0 ((uint32_t)0x00000001)

#define

GPIO_LCKR_LCK1 ((uint32_t)0x00000002)

#define

GPIO_LCKR_LCK10 ((uint32_t)0x00000400)

#define

GPIO_LCKR_LCK11 ((uint32_t)0x00000800)

#define

GPIO_LCKR_LCK12 ((uint32_t)0x00001000)

#define

GPIO_LCKR_LCK13 ((uint32_t)0x00002000)

#define

GPIO_LCKR_LCK14 ((uint32_t)0x00004000)

#define

GPIO_LCKR_LCK15 ((uint32_t)0x00008000)

#define

GPIO_LCKR_LCK2 ((uint32_t)0x00000004)

#define

GPIO_LCKR_LCK3 ((uint32_t)0x00000008)

#define

GPIO_LCKR_LCK4 ((uint32_t)0x00000010)

#define

GPIO_LCKR_LCK5 ((uint32_t)0x00000020)

#define

GPIO_LCKR_LCK6 ((uint32_t)0x00000040)

#define

GPIO_LCKR_LCK7 ((uint32_t)0x00000080)

#define

GPIO_LCKR_LCK8 ((uint32_t)0x00000100)

#define

GPIO_LCKR_LCK9 ((uint32_t)0x00000200)

#define

GPIO_LCKR_LCKK ((uint32_t)0x00010000)

#define

GPIO_ODR_ODR0 ((uint16_t)0x0001)

#define

GPIO_ODR_ODR1 ((uint16_t)0x0002)

#define

GPIO_ODR_ODR10 ((uint16_t)0x0400)

#define

GPIO_ODR_ODR11 ((uint16_t)0x0800)

#define

GPIO_ODR_ODR12 ((uint16_t)0x1000)

#define

GPIO_ODR_ODR13 ((uint16_t)0x2000)

#define

GPIO_ODR_ODR14 ((uint16_t)0x4000)

#define

GPIO_ODR_ODR15 ((uint16_t)0x8000)

#define

GPIO_ODR_ODR2 ((uint16_t)0x0004)

#define

GPIO_ODR_ODR3 ((uint16_t)0x0008)

#define

GPIO_ODR_ODR4 ((uint16_t)0x0010)

#define

GPIO_ODR_ODR5 ((uint16_t)0x0020)

#define

GPIO_ODR_ODR6 ((uint16_t)0x0040)

#define

GPIO_ODR_ODR7 ((uint16_t)0x0080)

#define

GPIO_ODR_ODR8 ((uint16_t)0x0100)

#define

GPIO_ODR_ODR9 ((uint16_t)0x0200)

#define

I2C_CCR_CCR ((uint16_t)0x0FFF)

#define

I2C_CCR_DUTY ((uint16_t)0x4000)

#define

I2C_CCR_FS ((uint16_t)0x8000)

#define

I2C_CR1_ACK ((uint16_t)0x0400)

#define

I2C_CR1_ALERT ((uint16_t)0x2000)

#define

I2C_CR1_ENARP ((uint16_t)0x0010)

#define

I2C_CR1_ENGC ((uint16_t)0x0040)

#define

I2C_CR1_ENPEC ((uint16_t)0x0020)

#define

I2C_CR1_NOSTRETCH ((uint16_t)0x0080)

#define

I2C_CR1_PE ((uint16_t)0x0001)

#define

I2C_CR1_PEC ((uint16_t)0x1000)

#define

I2C_CR1_POS ((uint16_t)0x0800)

#define

I2C_CR1_SMBTYPE ((uint16_t)0x0008)

#define

I2C_CR1_SMBUS ((uint16_t)0x0002)

#define

I2C_CR1_START ((uint16_t)0x0100)

#define

I2C_CR1_STOP ((uint16_t)0x0200)

#define

I2C_CR1_SWRST ((uint16_t)0x8000)

#define

I2C_CR2_DMAEN ((uint16_t)0x0800)

#define

I2C_CR2_FREQ ((uint16_t)0x003F)

#define

I2C_CR2_FREQ_0 ((uint16_t)0x0001)

#define

I2C_CR2_FREQ_1 ((uint16_t)0x0002)

#define

I2C_CR2_FREQ_2 ((uint16_t)0x0004)

#define

I2C_CR2_FREQ_3 ((uint16_t)0x0008)

#define

I2C_CR2_FREQ_4 ((uint16_t)0x0010)

#define

I2C_CR2_FREQ_5 ((uint16_t)0x0020)

#define

I2C_CR2_ITBUFEN ((uint16_t)0x0400)

#define

I2C_CR2_ITERREN ((uint16_t)0x0100)

#define

I2C_CR2_ITEVTEN ((uint16_t)0x0200)

#define

I2C_CR2_LAST ((uint16_t)0x1000)

#define

I2C_DR_DR ((uint8_t)0xFF)

#define

I2C_OAR1_ADD0 ((uint16_t)0x0001)

#define

I2C_OAR1_ADD1 ((uint16_t)0x0002)

#define

I2C_OAR1_ADD1_7 ((uint16_t)0x00FE)

#define

I2C_OAR1_ADD2 ((uint16_t)0x0004)

#define

I2C_OAR1_ADD3 ((uint16_t)0x0008)

#define

I2C_OAR1_ADD4 ((uint16_t)0x0010)

#define

I2C_OAR1_ADD5 ((uint16_t)0x0020)

#define

I2C_OAR1_ADD6 ((uint16_t)0x0040)

#define

I2C_OAR1_ADD7 ((uint16_t)0x0080)

#define

I2C_OAR1_ADD8 ((uint16_t)0x0100)

#define

I2C_OAR1_ADD8_9 ((uint16_t)0x0300)

#define

I2C_OAR1_ADD9 ((uint16_t)0x0200)

#define

I2C_OAR1_ADDMODE ((uint16_t)0x8000)

#define

I2C_OAR2_ADD2 ((uint8_t)0xFE)

#define

I2C_OAR2_ENDUAL ((uint8_t)0x01)

#define

I2C_SR1_ADD10 ((uint16_t)0x0008)

#define

I2C_SR1_ADDR ((uint16_t)0x0002)

#define

I2C_SR1_AF ((uint16_t)0x0400)

#define

I2C_SR1_ARLO ((uint16_t)0x0200)

#define

I2C_SR1_BERR ((uint16_t)0x0100)

#define

I2C_SR1_BTF ((uint16_t)0x0004)

#define

I2C_SR1_OVR ((uint16_t)0x0800)

#define

I2C_SR1_PECERR ((uint16_t)0x1000)

#define

I2C_SR1_RXNE ((uint16_t)0x0040)

#define

I2C_SR1_SB ((uint16_t)0x0001)

#define

I2C_SR1_SMBALERT ((uint16_t)0x8000)

#define

I2C_SR1_STOPF ((uint16_t)0x0010)

#define

I2C_SR1_TIMEOUT ((uint16_t)0x4000)

#define

I2C_SR1_TXE ((uint16_t)0x0080)

#define

I2C_SR2_BUSY ((uint16_t)0x0002)

#define

I2C_SR2_DUALF ((uint16_t)0x0080)

#define

I2C_SR2_GENCALL ((uint16_t)0x0010)

#define

I2C_SR2_MSL ((uint16_t)0x0001)

#define

I2C_SR2_PEC ((uint16_t)0xFF00)

#define

I2C_SR2_SMBDEFAULT ((uint16_t)0x0020)

#define

I2C_SR2_SMBHOST ((uint16_t)0x0040)

#define

I2C_SR2_TRA ((uint16_t)0x0004)

#define

I2C_TRISE_TRISE ((uint8_t)0x3F)

#define

IWDG_KR_KEY ((uint16_t)0xFFFF)

#define

IWDG_PR_PR ((uint8_t)0x07)

#define

IWDG_PR_PR_0 ((uint8_t)0x01)

#define

IWDG_PR_PR_1 ((uint8_t)0x02)

#define

IWDG_PR_PR_2 ((uint8_t)0x04)

#define

IWDG_RLR_RL ((uint16_t)0x0FFF)

#define

IWDG_SR_PVU ((uint8_t)0x01)

#define

IWDG_SR_RVU ((uint8_t)0x02)

#define

NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF)

#define

NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001)

#define

NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002)

#define

NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400)

#define

NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800)

#define

NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000)

#define

NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000)

#define

NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000)

#define

NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000)

#define

NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000)

#define

NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000)

#define

NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000)

#define

NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000)

#define

NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004)

#define

NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000)

#define

NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000)

#define

NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000)

#define

NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000)

#define

NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000)

#define

NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000)

#define

NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000)

#define

NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000)

#define

NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000)

#define

NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000)

#define

NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008)

#define

NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000)

#define

NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000)

#define

NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010)

#define

NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020)

#define

NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040)

#define

NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080)

#define

NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100)

#define

NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200)

#define

NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF)

#define

NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001)

#define

NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002)

#define

NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400)

#define

NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800)

#define

NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000)

#define

NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000)

#define

NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000)

#define

NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000)

#define

NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000)

#define

NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000)

#define

NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000)

#define

NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000)

#define

NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004)

#define

NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000)

#define

NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000)

#define

NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000)

#define

NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000)

#define

NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000)

#define

NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000)

#define

NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000)

#define

NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000)

#define

NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000)

#define

NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000)

#define

NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008)

#define

NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000)

#define

NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000)

#define

NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010)

#define

NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020)

#define

NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040)

#define

NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080)

#define

NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100)

#define

NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200)

#define

NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF)

#define

NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001)

#define

NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002)

#define

NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400)

#define

NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800)

#define

NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000)

#define

NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000)

#define

NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000)

#define

NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000)

#define

NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000)

#define

NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000)

#define

NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000)

#define

NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000)

#define

NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004)

#define

NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000)

#define

NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000)

#define

NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000)

#define

NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000)

#define

NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000)

#define

NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000)

#define

NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000)

#define

NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000)

#define

NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000)

#define

NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000)

#define

NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008)

#define

NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000)

#define

NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000)

#define

NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010)

#define

NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020)

#define

NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040)

#define

NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080)

#define

NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100)

#define

NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200)

#define

NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF)

#define

NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00)

#define

NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000)

#define

NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000)

#define

NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF)

#define

NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00)

#define

NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000)

#define

NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000)

#define

NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000)

#define

NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000)

#define

NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF)

#define

NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00)

#define

NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF)

#define

NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00)

#define

NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000)

#define

NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000)

#define

NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF)

#define

NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00)

#define

NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000)

#define

NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000)

#define

NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF)

#define

NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00)

#define

NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000)

#define

NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000)

#define

NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF)

#define

NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00)

#define

NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000)

#define

NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000)

#define

NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF)

#define

NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00)

#define

NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000)

#define

NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000)

#define

NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF)

#define

NVIC_ISER_SETENA_0 ((uint32_t)0x00000001)

#define

NVIC_ISER_SETENA_1 ((uint32_t)0x00000002)

#define

NVIC_ISER_SETENA_10 ((uint32_t)0x00000400)

#define

NVIC_ISER_SETENA_11 ((uint32_t)0x00000800)

#define

NVIC_ISER_SETENA_12 ((uint32_t)0x00001000)

#define

NVIC_ISER_SETENA_13 ((uint32_t)0x00002000)

#define

NVIC_ISER_SETENA_14 ((uint32_t)0x00004000)

#define

NVIC_ISER_SETENA_15 ((uint32_t)0x00008000)

#define

NVIC_ISER_SETENA_16 ((uint32_t)0x00010000)

#define

NVIC_ISER_SETENA_17 ((uint32_t)0x00020000)

#define

NVIC_ISER_SETENA_18 ((uint32_t)0x00040000)

#define

NVIC_ISER_SETENA_19 ((uint32_t)0x00080000)

#define

NVIC_ISER_SETENA_2 ((uint32_t)0x00000004)

#define

NVIC_ISER_SETENA_20 ((uint32_t)0x00100000)

#define

NVIC_ISER_SETENA_21 ((uint32_t)0x00200000)

#define

NVIC_ISER_SETENA_22 ((uint32_t)0x00400000)

#define

NVIC_ISER_SETENA_23 ((uint32_t)0x00800000)

#define

NVIC_ISER_SETENA_24 ((uint32_t)0x01000000)

#define

NVIC_ISER_SETENA_25 ((uint32_t)0x02000000)

#define

NVIC_ISER_SETENA_26 ((uint32_t)0x04000000)

#define

NVIC_ISER_SETENA_27 ((uint32_t)0x08000000)

#define

NVIC_ISER_SETENA_28 ((uint32_t)0x10000000)

#define

NVIC_ISER_SETENA_29 ((uint32_t)0x20000000)

#define

NVIC_ISER_SETENA_3 ((uint32_t)0x00000008)

#define

NVIC_ISER_SETENA_30 ((uint32_t)0x40000000)

#define

NVIC_ISER_SETENA_31 ((uint32_t)0x80000000)

#define

NVIC_ISER_SETENA_4 ((uint32_t)0x00000010)

#define

NVIC_ISER_SETENA_5 ((uint32_t)0x00000020)

#define

NVIC_ISER_SETENA_6 ((uint32_t)0x00000040)

#define

NVIC_ISER_SETENA_7 ((uint32_t)0x00000080)

#define

NVIC_ISER_SETENA_8 ((uint32_t)0x00000100)

#define

NVIC_ISER_SETENA_9 ((uint32_t)0x00000200)

#define

NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF)

#define

NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001)

#define

NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002)

#define

NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400)

#define

NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800)

#define

NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000)

#define

NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000)

#define

NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000)

#define

NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000)

#define

NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000)

#define

NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000)

#define

NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000)

#define

NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000)

#define

NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004)

#define

NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000)

#define

NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000)

#define

NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000)

#define

NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000)

#define

NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000)

#define

NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000)

#define

NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000)

#define

NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000)

#define

NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000)

#define

NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000)

#define

NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008)

#define

NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000)

#define

NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000)

#define

NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010)

#define

NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020)

#define

NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040)

#define

NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080)

#define

NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100)

#define

NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200)

#define

PWR_CR_CSBF ((uint16_t)0x0008)

#define

PWR_CR_CWUF ((uint16_t)0x0004)

#define

PWR_CR_DBP ((uint16_t)0x0100)

#define

PWR_CR_LPDS ((uint16_t)0x0001)

#define

PWR_CR_PDDS ((uint16_t)0x0002)

#define

PWR_CR_PLS ((uint16_t)0x00E0)

#define

PWR_CR_PLS_0 ((uint16_t)0x0020)

#define

PWR_CR_PLS_1 ((uint16_t)0x0040)

#define

PWR_CR_PLS_2 ((uint16_t)0x0080)

#define

PWR_CR_PLS_2V2 ((uint16_t)0x0000)

#define

PWR_CR_PLS_2V3 ((uint16_t)0x0020)

#define

PWR_CR_PLS_2V4 ((uint16_t)0x0040)

#define

PWR_CR_PLS_2V5 ((uint16_t)0x0060)

#define

PWR_CR_PLS_2V6 ((uint16_t)0x0080)

#define

PWR_CR_PLS_2V7 ((uint16_t)0x00A0)

#define

PWR_CR_PLS_2V8 ((uint16_t)0x00C0)

#define

PWR_CR_PLS_2V9 ((uint16_t)0x00E0)

#define

PWR_CR_PVDE ((uint16_t)0x0010)

#define

PWR_CSR_EWUP ((uint16_t)0x0100)

#define

PWR_CSR_PVDO ((uint16_t)0x0004)

#define

PWR_CSR_SBF ((uint16_t)0x0002)

#define

PWR_CSR_WUF ((uint16_t)0x0001)

#define

RCC_AHBENR_CRCEN ((uint16_t)0x0040)

#define

RCC_AHBENR_DMA1EN ((uint16_t)0x0001)

#define

RCC_AHBENR_FLITFEN ((uint16_t)0x0010)

#define

RCC_AHBENR_SRAMEN ((uint16_t)0x0004)

#define

RCC_APB1ENR_BKPEN ((uint32_t)0x08000000)

#define

RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000)

#define

RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000)

#define

RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000)

#define

RCC_APB1ENR_PWREN ((uint32_t)0x10000000)

#define

RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000)

#define

RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001)

#define

RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002)

#define

RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004)

#define

RCC_APB1ENR_USART2EN ((uint32_t)0x00020000)

#define

RCC_APB1ENR_USART3EN ((uint32_t)0x00040000)

#define

RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800)

#define

RCC_APB1RSTR_BKPRST ((uint32_t)0x08000000)

#define

RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000)

#define

RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000)

#define

RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000)

#define

RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000)

#define

RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000)

#define

RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001)

#define

RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002)

#define

RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004)

#define

RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000)

#define

RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000)

#define

RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800)

#define

RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200)

#define

RCC_APB2ENR_ADC2EN ((uint32_t)0x00000400)

#define

RCC_APB2ENR_AFIOEN ((uint32_t)0x00000001)

#define

RCC_APB2ENR_IOPAEN ((uint32_t)0x00000004)

#define

RCC_APB2ENR_IOPBEN ((uint32_t)0x00000008)

#define

RCC_APB2ENR_IOPCEN ((uint32_t)0x00000010)

#define

RCC_APB2ENR_IOPDEN ((uint32_t)0x00000020)

#define

RCC_APB2ENR_IOPEEN ((uint32_t)0x00000040)

#define

RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000)

#define

RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800)

#define

RCC_APB2ENR_USART1EN ((uint32_t)0x00004000)

#define

RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200)

#define

RCC_APB2RSTR_ADC2RST ((uint32_t)0x00000400)

#define

RCC_APB2RSTR_AFIORST ((uint32_t)0x00000001)

#define

RCC_APB2RSTR_IOPARST ((uint32_t)0x00000004)

#define

RCC_APB2RSTR_IOPBRST ((uint32_t)0x00000008)

#define

RCC_APB2RSTR_IOPCRST ((uint32_t)0x00000010)

#define

RCC_APB2RSTR_IOPDRST ((uint32_t)0x00000020)

#define

RCC_APB2RSTR_IOPERST ((uint32_t)0x00000040)

#define

RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000)

#define

RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800)

#define

RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000)

#define

RCC_BDCR_BDRST ((uint32_t)0x00010000)

#define

RCC_BDCR_LSEBYP ((uint32_t)0x00000004)

#define

RCC_BDCR_LSEON ((uint32_t)0x00000001)

#define

RCC_BDCR_LSERDY ((uint32_t)0x00000002)

#define

RCC_BDCR_RTCEN ((uint32_t)0x00008000)

#define

RCC_BDCR_RTCSEL ((uint32_t)0x00000300)

#define

RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100)

#define

RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200)

#define

RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300)

#define

RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100)

#define

RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200)

#define

RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000)

#define

RCC_CFGR_ADCPRE ((uint32_t)0x0000C000)

#define

RCC_CFGR_ADCPRE_0 ((uint32_t)0x00004000)

#define

RCC_CFGR_ADCPRE_1 ((uint32_t)0x00008000)

#define

RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000)

#define

RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000)

#define

RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000)

#define

RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000)

#define

RCC_CFGR_HPRE ((uint32_t)0x000000F0)

#define

RCC_CFGR_HPRE_0 ((uint32_t)0x00000010)

#define

RCC_CFGR_HPRE_1 ((uint32_t)0x00000020)

#define

RCC_CFGR_HPRE_2 ((uint32_t)0x00000040)

#define

RCC_CFGR_HPRE_3 ((uint32_t)0x00000080)

#define

RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000)

#define

RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0)

#define

RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0)

#define

RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080)

#define

RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0)

#define

RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090)

#define

RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0)

#define

RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0)

#define

RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0)

#define

RCC_CFGR_MCO ((uint32_t)0x07000000)

#define

RCC_CFGR_MCO_0 ((uint32_t)0x01000000)

#define

RCC_CFGR_MCO_1 ((uint32_t)0x02000000)

#define

RCC_CFGR_MCO_2 ((uint32_t)0x04000000)

#define

RCC_CFGR_MCO_HSE ((uint32_t)0x06000000)

#define

RCC_CFGR_MCO_HSI ((uint32_t)0x05000000)

#define

RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000)

#define

RCC_CFGR_MCO_PLL ((uint32_t)0x07000000)

#define

RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000)

#define

RCC_CFGR_PLLMULL ((uint32_t)0x003C0000)

#define

RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000)

#define

RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000)

#define

RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000)

#define

RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000)

#define

RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000)

#define

RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000)

#define

RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000)

#define

RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000)

#define

RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000)

#define

RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000)

#define

RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000)

#define

RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000)

#define

RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000)

#define

RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000)

#define

RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000)

#define

RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000)

#define

RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000)

#define

RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000)

#define

RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000)

#define

RCC_CFGR_PLLSRC ((uint32_t)0x00010000)

#define

RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000)

#define

RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000)

#define

RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000)

#define

RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000)

#define

RCC_CFGR_PLLXTPRE_HSE_Div2 ((uint32_t)0x00020000)

#define

RCC_CFGR_PPRE1 ((uint32_t)0x00000700)

#define

RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100)

#define

RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200)

#define

RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400)

#define

RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000)

#define

RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700)

#define

RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400)

#define

RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500)

#define

RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600)

#define

RCC_CFGR_PPRE2 ((uint32_t)0x00003800)

#define

RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800)

#define

RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000)

#define

RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000)

#define

RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000)

#define

RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800)

#define

RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000)

#define

RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800)

#define

RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000)

#define

RCC_CFGR_SW ((uint32_t)0x00000003)

#define

RCC_CFGR_SW_0 ((uint32_t)0x00000001)

#define

RCC_CFGR_SW_1 ((uint32_t)0x00000002)

#define

RCC_CFGR_SW_HSE ((uint32_t)0x00000001)

#define

RCC_CFGR_SW_HSI ((uint32_t)0x00000000)

#define

RCC_CFGR_SW_PLL ((uint32_t)0x00000002)

#define

RCC_CFGR_SWS ((uint32_t)0x0000000C)

#define

RCC_CFGR_SWS_0 ((uint32_t)0x00000004)

#define

RCC_CFGR_SWS_1 ((uint32_t)0x00000008)

#define

RCC_CFGR_SWS_HSE ((uint32_t)0x00000004)

#define

RCC_CFGR_SWS_HSI ((uint32_t)0x00000000)

#define

RCC_CFGR_SWS_PLL ((uint32_t)0x00000008)

#define

RCC_CFGR_USBPRE ((uint32_t)0x00400000)

#define

RCC_CIR_CSSC ((uint32_t)0x00800000)

#define

RCC_CIR_CSSF ((uint32_t)0x00000080)

#define

RCC_CIR_HSERDYC ((uint32_t)0x00080000)

#define

RCC_CIR_HSERDYF ((uint32_t)0x00000008)

#define

RCC_CIR_HSERDYIE ((uint32_t)0x00000800)

#define

RCC_CIR_HSIRDYC ((uint32_t)0x00040000)

#define

RCC_CIR_HSIRDYF ((uint32_t)0x00000004)

#define

RCC_CIR_HSIRDYIE ((uint32_t)0x00000400)

#define

RCC_CIR_LSERDYC ((uint32_t)0x00020000)

#define

RCC_CIR_LSERDYF ((uint32_t)0x00000002)

#define

RCC_CIR_LSERDYIE ((uint32_t)0x00000200)

#define

RCC_CIR_LSIRDYC ((uint32_t)0x00010000)

#define

RCC_CIR_LSIRDYF ((uint32_t)0x00000001)

#define

RCC_CIR_LSIRDYIE ((uint32_t)0x00000100)

#define

RCC_CIR_PLLRDYC ((uint32_t)0x00100000)

#define

RCC_CIR_PLLRDYF ((uint32_t)0x00000010)

#define

RCC_CIR_PLLRDYIE ((uint32_t)0x00001000)

#define

RCC_CR_CSSON ((uint32_t)0x00080000)

#define

RCC_CR_HSEBYP ((uint32_t)0x00040000)

#define

RCC_CR_HSEON ((uint32_t)0x00010000)

#define

RCC_CR_HSERDY ((uint32_t)0x00020000)

#define

RCC_CR_HSICAL ((uint32_t)0x0000FF00)

#define

RCC_CR_HSION ((uint32_t)0x00000001)

#define

RCC_CR_HSIRDY ((uint32_t)0x00000002)

#define

RCC_CR_HSITRIM ((uint32_t)0x000000F8)

#define

RCC_CR_PLLON ((uint32_t)0x01000000)

#define

RCC_CR_PLLRDY ((uint32_t)0x02000000)

#define

RCC_CSR_IWDGRSTF ((uint32_t)0x20000000)

#define

RCC_CSR_LPWRRSTF ((uint32_t)0x80000000)

#define

RCC_CSR_LSION ((uint32_t)0x00000001)

#define

RCC_CSR_LSIRDY ((uint32_t)0x00000002)

#define

RCC_CSR_PINRSTF ((uint32_t)0x04000000)

#define

RCC_CSR_PORRSTF ((uint32_t)0x08000000)

#define

RCC_CSR_RMVF ((uint32_t)0x01000000)

#define

RCC_CSR_SFTRSTF ((uint32_t)0x10000000)

#define

RCC_CSR_WWDGRSTF ((uint32_t)0x40000000)

#define

RTC_ALRH_RTC_ALR ((uint16_t)0xFFFF)

#define

RTC_ALRL_RTC_ALR ((uint16_t)0xFFFF)

#define

RTC_CNTH_RTC_CNT ((uint16_t)0xFFFF)

#define

RTC_CNTL_RTC_CNT ((uint16_t)0xFFFF)

#define

RTC_CRH_ALRIE ((uint8_t)0x02)

#define

RTC_CRH_OWIE ((uint8_t)0x04)

#define

RTC_CRH_SECIE ((uint8_t)0x01)

#define

RTC_CRL_ALRF ((uint8_t)0x02)

#define

RTC_CRL_CNF ((uint8_t)0x10)

#define

RTC_CRL_OWF ((uint8_t)0x04)

#define

RTC_CRL_RSF ((uint8_t)0x08)

#define

RTC_CRL_RTOFF ((uint8_t)0x20)

#define

RTC_CRL_SECF ((uint8_t)0x01)

#define

RTC_DIVH_RTC_DIV ((uint16_t)0x000F)

#define

RTC_DIVL_RTC_DIV ((uint16_t)0xFFFF)

#define

RTC_PRLH_PRL ((uint16_t)0x000F)

#define

RTC_PRLL_PRL ((uint16_t)0xFFFF)

#define

SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF)

#define

SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000)

#define

SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700)

#define

SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000)

#define

SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100)

#define

SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200)

#define

SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300)

#define

SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400)

#define

SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500)

#define

SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600)

#define

SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700)

#define

SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100)

#define

SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200)

#define

SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400)

#define

SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004)

#define

SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002)

#define

SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000)

#define

SCB_AIRCR_VECTRESET ((uint32_t)0x00000001)

#define

SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF)

#define

SCB_CCR_BFHFNMIGN ((uint16_t)0x0100)

#define

SCB_CCR_DIV_0_TRP ((uint16_t)0x0010)

#define

SCB_CCR_NONBASETHRDENA ((uint16_t)0x0001)

#define

SCB_CCR_STKALIGN ((uint16_t)0x0200)

#define

SCB_CCR_UNALIGN_TRP ((uint16_t)0x0008)

#define

SCB_CCR_USERSETMPEND ((uint16_t)0x0002)

#define

SCB_CFSR_BFARVALID ((uint32_t)0x00008000)

#define

SCB_CFSR_DACCVIOL ((uint32_t)0x00000002)

#define

SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000)

#define

SCB_CFSR_IACCVIOL ((uint32_t)0x00000001)

#define

SCB_CFSR_IBUSERR ((uint32_t)0x00000100)

#define

SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400)

#define

SCB_CFSR_INVPC ((uint32_t)0x00040000)

#define

SCB_CFSR_INVSTATE ((uint32_t)0x00020000)

#define

SCB_CFSR_MMARVALID ((uint32_t)0x00000080)

#define

SCB_CFSR_MSTKERR ((uint32_t)0x00000010)

#define

SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008)

#define

SCB_CFSR_NOCP ((uint32_t)0x00080000)

#define

SCB_CFSR_PRECISERR ((uint32_t)0x00000200)

#define

SCB_CFSR_STKERR ((uint32_t)0x00001000)

#define

SCB_CFSR_UNALIGNED ((uint32_t)0x01000000)

#define

SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000)

#define

SCB_CFSR_UNSTKERR ((uint32_t)0x00000800)

#define

SCB_CPUID_Constant ((uint32_t)0x000F0000)

#define

SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000)

#define

SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0)

#define

SCB_CPUID_REVISION ((uint32_t)0x0000000F)

#define

SCB_CPUID_VARIANT ((uint32_t)0x00F00000)

#define

SCB_DFSR_BKPT ((uint8_t)0x02)

#define

SCB_DFSR_DWTTRAP ((uint8_t)0x04)

#define

SCB_DFSR_EXTERNAL ((uint8_t)0x10)

#define

SCB_DFSR_HALTED ((uint8_t)0x01)

#define

SCB_DFSR_VCATCH ((uint8_t)0x08)

#define

SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000)

#define

SCB_HFSR_FORCED ((uint32_t)0x40000000)

#define

SCB_HFSR_VECTTBL ((uint32_t)0x00000002)

#define

SCB_ICSR_ISRPENDING ((uint32_t)0x00400000)

#define

SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000)

#define

SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000)

#define

SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000)

#define

SCB_ICSR_PENDSTSET ((uint32_t)0x04000000)

#define

SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000)

#define

SCB_ICSR_PENDSVSET ((uint32_t)0x10000000)

#define

SCB_ICSR_RETTOBASE ((uint32_t)0x00000800)

#define

SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF)

#define

SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000)

#define

SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF)

#define

SCB_SCR_SEVONPEND ((uint8_t)0x10)

#define

SCB_SCR_SLEEPDEEP ((uint8_t)0x04)

#define

SCB_SCR_SLEEPONEXIT ((uint8_t)0x02)

#define

SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002)

#define

SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000)

#define

SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000)

#define

SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001)

#define

SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000)

#define

SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000)

#define

SCB_SHCSR_MONITORACT ((uint32_t)0x00000100)

#define

SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400)

#define

SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080)

#define

SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000)

#define

SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800)

#define

SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008)

#define

SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000)

#define

SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000)

#define

SCB_SHPR_PRI_N ((uint32_t)0x000000FF)

#define

SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00)

#define

SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000)

#define

SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000)

#define

SCB_VTOR_TBLBASE ((uint32_t)0x20000000)

#define

SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80)

#define

SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF)

#define

SDIO_CLKCR_BYPASS ((uint16_t)0x0400)

#define

SDIO_CLKCR_CLKDIV ((uint16_t)0x00FF)

#define

SDIO_CLKCR_CLKEN ((uint16_t)0x0100)

#define

SDIO_CLKCR_HWFC_EN ((uint16_t)0x4000)

#define

SDIO_CLKCR_NEGEDGE ((uint16_t)0x2000)

#define

SDIO_CLKCR_PWRSAV ((uint16_t)0x0200)

#define

SDIO_CLKCR_WIDBUS ((uint16_t)0x1800)

#define

SDIO_CLKCR_WIDBUS_0 ((uint16_t)0x0800)

#define

SDIO_CLKCR_WIDBUS_1 ((uint16_t)0x1000)

#define

SDIO_CMD_CEATACMD ((uint16_t)0x4000)

#define

SDIO_CMD_CMDINDEX ((uint16_t)0x003F)

#define

SDIO_CMD_CPSMEN ((uint16_t)0x0400)

#define

SDIO_CMD_ENCMDCOMPL ((uint16_t)0x1000)

#define

SDIO_CMD_NIEN ((uint16_t)0x2000)

#define

SDIO_CMD_SDIOSUSPEND ((uint16_t)0x0800)

#define

SDIO_CMD_WAITINT ((uint16_t)0x0100)

#define

SDIO_CMD_WAITPEND ((uint16_t)0x0200)

#define

SDIO_CMD_WAITRESP ((uint16_t)0x00C0)

#define

SDIO_CMD_WAITRESP_0 ((uint16_t)0x0040)

#define

SDIO_CMD_WAITRESP_1 ((uint16_t)0x0080)

#define

SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF)

#define

SDIO_DCTRL_DBLOCKSIZE ((uint16_t)0x00F0)

#define

SDIO_DCTRL_DBLOCKSIZE_0 ((uint16_t)0x0010)

#define

SDIO_DCTRL_DBLOCKSIZE_1 ((uint16_t)0x0020)

#define

SDIO_DCTRL_DBLOCKSIZE_2 ((uint16_t)0x0040)

#define

SDIO_DCTRL_DBLOCKSIZE_3 ((uint16_t)0x0080)

#define

SDIO_DCTRL_DMAEN ((uint16_t)0x0008)

#define

SDIO_DCTRL_DTDIR ((uint16_t)0x0002)

#define

SDIO_DCTRL_DTEN ((uint16_t)0x0001)

#define

SDIO_DCTRL_DTMODE ((uint16_t)0x0004)

#define

SDIO_DCTRL_RWMOD ((uint16_t)0x0400)

#define

SDIO_DCTRL_RWSTART ((uint16_t)0x0100)

#define

SDIO_DCTRL_RWSTOP ((uint16_t)0x0200)

#define

SDIO_DCTRL_SDIOEN ((uint16_t)0x0800)

#define

SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF)

#define

SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF)

#define

SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF)

#define

SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF)

#define

SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001)

#define

SDIO_ICR_CEATAENDC ((uint32_t)0x00800000)

#define

SDIO_ICR_CMDRENDC ((uint32_t)0x00000040)

#define

SDIO_ICR_CMDSENTC ((uint32_t)0x00000080)

#define

SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004)

#define

SDIO_ICR_DATAENDC ((uint32_t)0x00000100)

#define

SDIO_ICR_DBCKENDC ((uint32_t)0x00000400)

#define

SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002)

#define

SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008)

#define

SDIO_ICR_RXOVERRC ((uint32_t)0x00000020)

#define

SDIO_ICR_SDIOITC ((uint32_t)0x00400000)

#define

SDIO_ICR_STBITERRC ((uint32_t)0x00000200)

#define

SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010)

#define

SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001)

#define

SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000)

#define

SDIO_MASK_CMDACTIE ((uint32_t)0x00000800)

#define

SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040)

#define

SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080)

#define

SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004)

#define

SDIO_MASK_DATAENDIE ((uint32_t)0x00000100)

#define

SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400)

#define

SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002)

#define

SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008)

#define

SDIO_MASK_RXACTIE ((uint32_t)0x00002000)

#define

SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000)

#define

SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000)

#define

SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000)

#define

SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000)

#define

SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020)

#define

SDIO_MASK_SDIOITIE ((uint32_t)0x00400000)

#define

SDIO_MASK_STBITERRIE ((uint32_t)0x00000200)

#define

SDIO_MASK_TXACTIE ((uint32_t)0x00001000)

#define

SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000)

#define

SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000)

#define

SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000)

#define

SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000)

#define

SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010)

#define

SDIO_POWER_PWRCTRL ((uint8_t)0x03)

#define

SDIO_POWER_PWRCTRL_0 ((uint8_t)0x01)

#define

SDIO_POWER_PWRCTRL_1 ((uint8_t)0x02)

#define

SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF)

#define

SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF)

#define

SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF)

#define

SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF)

#define

SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF)

#define

SDIO_RESPCMD_RESPCMD ((uint8_t)0x3F)

#define

SDIO_STA_CCRCFAIL ((uint32_t)0x00000001)

#define

SDIO_STA_CEATAEND ((uint32_t)0x00800000)

#define

SDIO_STA_CMDACT ((uint32_t)0x00000800)

#define

SDIO_STA_CMDREND ((uint32_t)0x00000040)

#define

SDIO_STA_CMDSENT ((uint32_t)0x00000080)

#define

SDIO_STA_CTIMEOUT ((uint32_t)0x00000004)

#define

SDIO_STA_DATAEND ((uint32_t)0x00000100)

#define

SDIO_STA_DBCKEND ((uint32_t)0x00000400)

#define

SDIO_STA_DCRCFAIL ((uint32_t)0x00000002)

#define

SDIO_STA_DTIMEOUT ((uint32_t)0x00000008)

#define

SDIO_STA_RXACT ((uint32_t)0x00002000)

#define

SDIO_STA_RXDAVL ((uint32_t)0x00200000)

#define

SDIO_STA_RXFIFOE ((uint32_t)0x00080000)

#define

SDIO_STA_RXFIFOF ((uint32_t)0x00020000)

#define

SDIO_STA_RXFIFOHF ((uint32_t)0x00008000)

#define

SDIO_STA_RXOVERR ((uint32_t)0x00000020)

#define

SDIO_STA_SDIOIT ((uint32_t)0x00400000)

#define

SDIO_STA_STBITERR ((uint32_t)0x00000200)

#define

SDIO_STA_TXACT ((uint32_t)0x00001000)

#define

SDIO_STA_TXDAVL ((uint32_t)0x00100000)

#define

SDIO_STA_TXFIFOE ((uint32_t)0x00040000)

#define

SDIO_STA_TXFIFOF ((uint32_t)0x00010000)

#define

SDIO_STA_TXFIFOHE ((uint32_t)0x00004000)

#define

SDIO_STA_TXUNDERR ((uint32_t)0x00000010)

#define

SPI_CR1_BIDIMODE ((uint16_t)0x8000)

#define

SPI_CR1_BIDIOE ((uint16_t)0x4000)

#define

SPI_CR1_BR ((uint16_t)0x0038)

#define

SPI_CR1_BR_0 ((uint16_t)0x0008)

#define

SPI_CR1_BR_1 ((uint16_t)0x0010)

#define

SPI_CR1_BR_2 ((uint16_t)0x0020)

#define

SPI_CR1_CPHA ((uint16_t)0x0001)

#define

SPI_CR1_CPOL ((uint16_t)0x0002)

#define

SPI_CR1_CRCEN ((uint16_t)0x2000)

#define

SPI_CR1_CRCNEXT ((uint16_t)0x1000)

#define

SPI_CR1_DFF ((uint16_t)0x0800)

#define

SPI_CR1_LSBFIRST ((uint16_t)0x0080)

#define

SPI_CR1_MSTR ((uint16_t)0x0004)

#define

SPI_CR1_RXONLY ((uint16_t)0x0400)

#define

SPI_CR1_SPE ((uint16_t)0x0040)

#define

SPI_CR1_SSI ((uint16_t)0x0100)

#define

SPI_CR1_SSM ((uint16_t)0x0200)

#define

SPI_CR2_ERRIE ((uint8_t)0x20)

#define

SPI_CR2_RXDMAEN ((uint8_t)0x01)

#define

SPI_CR2_RXNEIE ((uint8_t)0x40)

#define

SPI_CR2_SSOE ((uint8_t)0x04)

#define

SPI_CR2_TXDMAEN ((uint8_t)0x02)

#define

SPI_CR2_TXEIE ((uint8_t)0x80)

#define

SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF)

#define

SPI_DR_DR ((uint16_t)0xFFFF)

#define

SPI_I2SCFGR_CHLEN ((uint16_t)0x0001)

#define

SPI_I2SCFGR_CKPOL ((uint16_t)0x0008)

#define

SPI_I2SCFGR_DATLEN ((uint16_t)0x0006)

#define

SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002)

#define

SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004)

#define

SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300)

#define

SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100)

#define

SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200)

#define

SPI_I2SCFGR_I2SE ((uint16_t)0x0400)

#define

SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800)

#define

SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030)

#define

SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010)

#define

SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020)

#define

SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080)

#define

SPI_I2SPR_I2SDIV ((uint16_t)0x00FF)

#define

SPI_I2SPR_MCKOE ((uint16_t)0x0200)

#define

SPI_I2SPR_ODD ((uint16_t)0x0100)

#define

SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF)

#define

SPI_SR_BSY ((uint8_t)0x80)

#define

SPI_SR_CHSIDE ((uint8_t)0x04)

#define

SPI_SR_CRCERR ((uint8_t)0x10)

#define

SPI_SR_MODF ((uint8_t)0x20)

#define

SPI_SR_OVR ((uint8_t)0x40)

#define

SPI_SR_RXNE ((uint8_t)0x01)

#define

SPI_SR_TXE ((uint8_t)0x02)

#define

SPI_SR_UDR ((uint8_t)0x08)

#define

SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF)

#define

SysTick_CALIB_NOREF ((uint32_t)0x80000000)

#define

SysTick_CALIB_SKEW ((uint32_t)0x40000000)

#define

SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF)

#define

SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004)

#define

SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000)

#define

SysTick_CTRL_ENABLE ((uint32_t)0x00000001)

#define

SysTick_CTRL_TICKINT ((uint32_t)0x00000002)

#define

SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF)

#define

SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF)

#define

TIM_ARR_ARR ((uint16_t)0xFFFF)

#define

TIM_BDTR_AOE ((uint16_t)0x4000)

#define

TIM_BDTR_BKE ((uint16_t)0x1000)

#define

TIM_BDTR_BKP ((uint16_t)0x2000)

#define

TIM_BDTR_DTG ((uint16_t)0x00FF)

#define

TIM_BDTR_DTG_0 ((uint16_t)0x0001)

#define

TIM_BDTR_DTG_1 ((uint16_t)0x0002)

#define

TIM_BDTR_DTG_2 ((uint16_t)0x0004)

#define

TIM_BDTR_DTG_3 ((uint16_t)0x0008)

#define

TIM_BDTR_DTG_4 ((uint16_t)0x0010)

#define

TIM_BDTR_DTG_5 ((uint16_t)0x0020)

#define

TIM_BDTR_DTG_6 ((uint16_t)0x0040)

#define

TIM_BDTR_DTG_7 ((uint16_t)0x0080)

#define

TIM_BDTR_LOCK ((uint16_t)0x0300)

#define

TIM_BDTR_LOCK_0 ((uint16_t)0x0100)

#define

TIM_BDTR_LOCK_1 ((uint16_t)0x0200)

#define

TIM_BDTR_MOE ((uint16_t)0x8000)

#define

TIM_BDTR_OSSI ((uint16_t)0x0400)

#define

TIM_BDTR_OSSR ((uint16_t)0x0800)

#define

TIM_CCER_CC1E ((uint16_t)0x0001)

#define

TIM_CCER_CC1NE ((uint16_t)0x0004)

#define

TIM_CCER_CC1NP ((uint16_t)0x0008)

#define

TIM_CCER_CC1P ((uint16_t)0x0002)

#define

TIM_CCER_CC2E ((uint16_t)0x0010)

#define

TIM_CCER_CC2NE ((uint16_t)0x0040)

#define

TIM_CCER_CC2NP ((uint16_t)0x0080)

#define

TIM_CCER_CC2P ((uint16_t)0x0020)

#define

TIM_CCER_CC3E ((uint16_t)0x0100)

#define

TIM_CCER_CC3NE ((uint16_t)0x0400)

#define

TIM_CCER_CC3NP ((uint16_t)0x0800)

#define

TIM_CCER_CC3P ((uint16_t)0x0200)

#define

TIM_CCER_CC4E ((uint16_t)0x1000)

#define

TIM_CCER_CC4NP ((uint16_t)0x8000)

#define

TIM_CCER_CC4P ((uint16_t)0x2000)

#define

TIM_CCMR1_CC1S ((uint16_t)0x0003)

#define

TIM_CCMR1_CC1S_0 ((uint16_t)0x0001)

#define

TIM_CCMR1_CC1S_1 ((uint16_t)0x0002)

#define

TIM_CCMR1_CC2S ((uint16_t)0x0300)

#define

TIM_CCMR1_CC2S_0 ((uint16_t)0x0100)

#define

TIM_CCMR1_CC2S_1 ((uint16_t)0x0200)

#define

TIM_CCMR1_IC1F ((uint16_t)0x00F0)

#define

TIM_CCMR1_IC1F_0 ((uint16_t)0x0010)

#define

TIM_CCMR1_IC1F_1 ((uint16_t)0x0020)

#define

TIM_CCMR1_IC1F_2 ((uint16_t)0x0040)

#define

TIM_CCMR1_IC1F_3 ((uint16_t)0x0080)

#define

TIM_CCMR1_IC1PSC ((uint16_t)0x000C)

#define

TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004)

#define

TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008)

#define

TIM_CCMR1_IC2F ((uint16_t)0xF000)

#define

TIM_CCMR1_IC2F_0 ((uint16_t)0x1000)

#define

TIM_CCMR1_IC2F_1 ((uint16_t)0x2000)

#define

TIM_CCMR1_IC2F_2 ((uint16_t)0x4000)

#define

TIM_CCMR1_IC2F_3 ((uint16_t)0x8000)

#define

TIM_CCMR1_IC2PSC ((uint16_t)0x0C00)

#define

TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400)

#define

TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800)

#define

TIM_CCMR1_OC1CE ((uint16_t)0x0080)

#define

TIM_CCMR1_OC1FE ((uint16_t)0x0004)

#define

TIM_CCMR1_OC1M ((uint16_t)0x0070)

#define

TIM_CCMR1_OC1M_0 ((uint16_t)0x0010)

#define

TIM_CCMR1_OC1M_1 ((uint16_t)0x0020)

#define

TIM_CCMR1_OC1M_2 ((uint16_t)0x0040)

#define

TIM_CCMR1_OC1PE ((uint16_t)0x0008)

#define

TIM_CCMR1_OC2CE ((uint16_t)0x8000)

#define

TIM_CCMR1_OC2FE ((uint16_t)0x0400)

#define

TIM_CCMR1_OC2M ((uint16_t)0x7000)

#define

TIM_CCMR1_OC2M_0 ((uint16_t)0x1000)

#define

TIM_CCMR1_OC2M_1 ((uint16_t)0x2000)

#define

TIM_CCMR1_OC2M_2 ((uint16_t)0x4000)

#define

TIM_CCMR1_OC2PE ((uint16_t)0x0800)

#define

TIM_CCMR2_CC3S ((uint16_t)0x0003)

#define

TIM_CCMR2_CC3S_0 ((uint16_t)0x0001)

#define

TIM_CCMR2_CC3S_1 ((uint16_t)0x0002)

#define

TIM_CCMR2_CC4S ((uint16_t)0x0300)

#define

TIM_CCMR2_CC4S_0 ((uint16_t)0x0100)

#define

TIM_CCMR2_CC4S_1 ((uint16_t)0x0200)

#define

TIM_CCMR2_IC3F ((uint16_t)0x00F0)

#define

TIM_CCMR2_IC3F_0 ((uint16_t)0x0010)

#define

TIM_CCMR2_IC3F_1 ((uint16_t)0x0020)

#define

TIM_CCMR2_IC3F_2 ((uint16_t)0x0040)

#define

TIM_CCMR2_IC3F_3 ((uint16_t)0x0080)

#define

TIM_CCMR2_IC3PSC ((uint16_t)0x000C)

#define

TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004)

#define

TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008)

#define

TIM_CCMR2_IC4F ((uint16_t)0xF000)

#define

TIM_CCMR2_IC4F_0 ((uint16_t)0x1000)

#define

TIM_CCMR2_IC4F_1 ((uint16_t)0x2000)

#define

TIM_CCMR2_IC4F_2 ((uint16_t)0x4000)

#define

TIM_CCMR2_IC4F_3 ((uint16_t)0x8000)

#define

TIM_CCMR2_IC4PSC ((uint16_t)0x0C00)

#define

TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400)

#define

TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800)

#define

TIM_CCMR2_OC3CE ((uint16_t)0x0080)

#define

TIM_CCMR2_OC3FE ((uint16_t)0x0004)

#define

TIM_CCMR2_OC3M ((uint16_t)0x0070)

#define

TIM_CCMR2_OC3M_0 ((uint16_t)0x0010)

#define

TIM_CCMR2_OC3M_1 ((uint16_t)0x0020)

#define

TIM_CCMR2_OC3M_2 ((uint16_t)0x0040)

#define

TIM_CCMR2_OC3PE ((uint16_t)0x0008)

#define

TIM_CCMR2_OC4CE ((uint16_t)0x8000)

#define

TIM_CCMR2_OC4FE ((uint16_t)0x0400)

#define

TIM_CCMR2_OC4M ((uint16_t)0x7000)

#define

TIM_CCMR2_OC4M_0 ((uint16_t)0x1000)

#define

TIM_CCMR2_OC4M_1 ((uint16_t)0x2000)

#define

TIM_CCMR2_OC4M_2 ((uint16_t)0x4000)

#define

TIM_CCMR2_OC4PE ((uint16_t)0x0800)

#define

TIM_CCR1_CCR1 ((uint16_t)0xFFFF)

#define

TIM_CCR2_CCR2 ((uint16_t)0xFFFF)

#define

TIM_CCR3_CCR3 ((uint16_t)0xFFFF)

#define

TIM_CCR4_CCR4 ((uint16_t)0xFFFF)

#define

TIM_CNT_CNT ((uint16_t)0xFFFF)

#define

TIM_CR1_ARPE ((uint16_t)0x0080)

#define

TIM_CR1_CEN ((uint16_t)0x0001)

#define

TIM_CR1_CKD ((uint16_t)0x0300)

#define

TIM_CR1_CKD_0 ((uint16_t)0x0100)

#define

TIM_CR1_CKD_1 ((uint16_t)0x0200)

#define

TIM_CR1_CMS ((uint16_t)0x0060)

#define

TIM_CR1_CMS_0 ((uint16_t)0x0020)

#define

TIM_CR1_CMS_1 ((uint16_t)0x0040)

#define

TIM_CR1_DIR ((uint16_t)0x0010)

#define

TIM_CR1_OPM ((uint16_t)0x0008)

#define

TIM_CR1_UDIS ((uint16_t)0x0002)

#define

TIM_CR1_URS ((uint16_t)0x0004)

#define

TIM_CR2_CCDS ((uint16_t)0x0008)

#define

TIM_CR2_CCPC ((uint16_t)0x0001)

#define

TIM_CR2_CCUS ((uint16_t)0x0004)

#define

TIM_CR2_MMS ((uint16_t)0x0070)

#define

TIM_CR2_MMS_0 ((uint16_t)0x0010)

#define

TIM_CR2_MMS_1 ((uint16_t)0x0020)

#define

TIM_CR2_MMS_2 ((uint16_t)0x0040)

#define

TIM_CR2_OIS1 ((uint16_t)0x0100)

#define

TIM_CR2_OIS1N ((uint16_t)0x0200)

#define

TIM_CR2_OIS2 ((uint16_t)0x0400)

#define

TIM_CR2_OIS2N ((uint16_t)0x0800)

#define

TIM_CR2_OIS3 ((uint16_t)0x1000)

#define

TIM_CR2_OIS3N ((uint16_t)0x2000)

#define

TIM_CR2_OIS4 ((uint16_t)0x4000)

#define

TIM_CR2_TI1S ((uint16_t)0x0080)

#define

TIM_DCR_DBA ((uint16_t)0x001F)

#define

TIM_DCR_DBA_0 ((uint16_t)0x0001)

#define

TIM_DCR_DBA_1 ((uint16_t)0x0002)

#define

TIM_DCR_DBA_2 ((uint16_t)0x0004)

#define

TIM_DCR_DBA_3 ((uint16_t)0x0008)

#define

TIM_DCR_DBA_4 ((uint16_t)0x0010)

#define

TIM_DCR_DBL ((uint16_t)0x1F00)

#define

TIM_DCR_DBL_0 ((uint16_t)0x0100)

#define

TIM_DCR_DBL_1 ((uint16_t)0x0200)

#define

TIM_DCR_DBL_2 ((uint16_t)0x0400)

#define

TIM_DCR_DBL_3 ((uint16_t)0x0800)

#define

TIM_DCR_DBL_4 ((uint16_t)0x1000)

#define

TIM_DIER_BIE ((uint16_t)0x0080)

#define

TIM_DIER_CC1DE ((uint16_t)0x0200)

#define

TIM_DIER_CC1IE ((uint16_t)0x0002)

#define

TIM_DIER_CC2DE ((uint16_t)0x0400)

#define

TIM_DIER_CC2IE ((uint16_t)0x0004)

#define

TIM_DIER_CC3DE ((uint16_t)0x0800)

#define

TIM_DIER_CC3IE ((uint16_t)0x0008)

#define

TIM_DIER_CC4DE ((uint16_t)0x1000)

#define

TIM_DIER_CC4IE ((uint16_t)0x0010)

#define

TIM_DIER_COMDE ((uint16_t)0x2000)

#define

TIM_DIER_COMIE ((uint16_t)0x0020)

#define

TIM_DIER_TDE ((uint16_t)0x4000)

#define

TIM_DIER_TIE ((uint16_t)0x0040)

#define

TIM_DIER_UDE ((uint16_t)0x0100)

#define

TIM_DIER_UIE ((uint16_t)0x0001)

#define

TIM_DMAR_DMAB ((uint16_t)0xFFFF)

#define

TIM_EGR_BG ((uint8_t)0x80)

#define

TIM_EGR_CC1G ((uint8_t)0x02)

#define

TIM_EGR_CC2G ((uint8_t)0x04)

#define

TIM_EGR_CC3G ((uint8_t)0x08)

#define

TIM_EGR_CC4G ((uint8_t)0x10)

#define

TIM_EGR_COMG ((uint8_t)0x20)

#define

TIM_EGR_TG ((uint8_t)0x40)

#define

TIM_EGR_UG ((uint8_t)0x01)

#define

TIM_PSC_PSC ((uint16_t)0xFFFF)

#define

TIM_RCR_REP ((uint8_t)0xFF)

#define

TIM_SMCR_ECE ((uint16_t)0x4000)

#define

TIM_SMCR_ETF ((uint16_t)0x0F00)

#define

TIM_SMCR_ETF_0 ((uint16_t)0x0100)

#define

TIM_SMCR_ETF_1 ((uint16_t)0x0200)

#define

TIM_SMCR_ETF_2 ((uint16_t)0x0400)

#define

TIM_SMCR_ETF_3 ((uint16_t)0x0800)

#define

TIM_SMCR_ETP ((uint16_t)0x8000)

#define

TIM_SMCR_ETPS ((uint16_t)0x3000)

#define

TIM_SMCR_ETPS_0 ((uint16_t)0x1000)

#define

TIM_SMCR_ETPS_1 ((uint16_t)0x2000)

#define

TIM_SMCR_MSM ((uint16_t)0x0080)

#define

TIM_SMCR_SMS ((uint16_t)0x0007)

#define

TIM_SMCR_SMS_0 ((uint16_t)0x0001)

#define

TIM_SMCR_SMS_1 ((uint16_t)0x0002)

#define

TIM_SMCR_SMS_2 ((uint16_t)0x0004)

#define

TIM_SMCR_TS ((uint16_t)0x0070)

#define

TIM_SMCR_TS_0 ((uint16_t)0x0010)

#define

TIM_SMCR_TS_1 ((uint16_t)0x0020)

#define

TIM_SMCR_TS_2 ((uint16_t)0x0040)

#define

TIM_SR_BIF ((uint16_t)0x0080)

#define

TIM_SR_CC1IF ((uint16_t)0x0002)

#define

TIM_SR_CC1OF ((uint16_t)0x0200)

#define

TIM_SR_CC2IF ((uint16_t)0x0004)

#define

TIM_SR_CC2OF ((uint16_t)0x0400)

#define

TIM_SR_CC3IF ((uint16_t)0x0008)

#define

TIM_SR_CC3OF ((uint16_t)0x0800)

#define

TIM_SR_CC4IF ((uint16_t)0x0010)

#define

TIM_SR_CC4OF ((uint16_t)0x1000)

#define

TIM_SR_COMIF ((uint16_t)0x0020)

#define

TIM_SR_TIF ((uint16_t)0x0040)

#define

TIM_SR_UIF ((uint16_t)0x0001)

#define

USART_BRR_DIV_Fraction ((uint16_t)0x000F)

#define

USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0)

#define

USART_CR1_IDLEIE ((uint16_t)0x0010)

#define

USART_CR1_M ((uint16_t)0x1000)

#define

USART_CR1_OVER8 ((uint16_t)0x8000)

#define

USART_CR1_PCE ((uint16_t)0x0400)

#define

USART_CR1_PEIE ((uint16_t)0x0100)

#define

USART_CR1_PS ((uint16_t)0x0200)

#define

USART_CR1_RE ((uint16_t)0x0004)

#define

USART_CR1_RWU ((uint16_t)0x0002)

#define

USART_CR1_RXNEIE ((uint16_t)0x0020)

#define

USART_CR1_SBK ((uint16_t)0x0001)

#define

USART_CR1_TCIE ((uint16_t)0x0040)

#define

USART_CR1_TE ((uint16_t)0x0008)

#define

USART_CR1_TXEIE ((uint16_t)0x0080)

#define

USART_CR1_UE ((uint16_t)0x2000)

#define

USART_CR1_WAKE ((uint16_t)0x0800)

#define

USART_CR2_ADD ((uint16_t)0x000F)

#define

USART_CR2_CLKEN ((uint16_t)0x0800)

#define

USART_CR2_CPHA ((uint16_t)0x0200)

#define

USART_CR2_CPOL ((uint16_t)0x0400)

#define

USART_CR2_LBCL ((uint16_t)0x0100)

#define

USART_CR2_LBDIE ((uint16_t)0x0040)

#define

USART_CR2_LBDL ((uint16_t)0x0020)

#define

USART_CR2_LINEN ((uint16_t)0x4000)

#define

USART_CR2_STOP ((uint16_t)0x3000)

#define

USART_CR2_STOP_0 ((uint16_t)0x1000)

#define

USART_CR2_STOP_1 ((uint16_t)0x2000)

#define

USART_CR3_CTSE ((uint16_t)0x0200)

#define

USART_CR3_CTSIE ((uint16_t)0x0400)

#define

USART_CR3_DMAR ((uint16_t)0x0040)

#define

USART_CR3_DMAT ((uint16_t)0x0080)

#define

USART_CR3_EIE ((uint16_t)0x0001)

#define

USART_CR3_HDSEL ((uint16_t)0x0008)

#define

USART_CR3_IREN ((uint16_t)0x0002)

#define

USART_CR3_IRLP ((uint16_t)0x0004)

#define

USART_CR3_NACK ((uint16_t)0x0010)

#define

USART_CR3_ONEBIT ((uint16_t)0x0800)

#define

USART_CR3_RTSE ((uint16_t)0x0100)

#define

USART_CR3_SCEN ((uint16_t)0x0020)

#define

USART_DR_DR ((uint16_t)0x01FF)

#define

USART_GTPR_GT ((uint16_t)0xFF00)

#define

USART_GTPR_PSC ((uint16_t)0x00FF)

#define

USART_GTPR_PSC_0 ((uint16_t)0x0001)

#define

USART_GTPR_PSC_1 ((uint16_t)0x0002)

#define

USART_GTPR_PSC_2 ((uint16_t)0x0004)

#define

USART_GTPR_PSC_3 ((uint16_t)0x0008)

#define

USART_GTPR_PSC_4 ((uint16_t)0x0010)

#define

USART_GTPR_PSC_5 ((uint16_t)0x0020)

#define

USART_GTPR_PSC_6 ((uint16_t)0x0040)

#define

USART_GTPR_PSC_7 ((uint16_t)0x0080)

#define

USART_SR_CTS ((uint16_t)0x0200)

#define

USART_SR_FE ((uint16_t)0x0002)

#define

USART_SR_IDLE ((uint16_t)0x0010)

#define

USART_SR_LBD ((uint16_t)0x0100)

#define

USART_SR_NE ((uint16_t)0x0004)

#define

USART_SR_ORE ((uint16_t)0x0008)

#define

USART_SR_PE ((uint16_t)0x0001)

#define

USART_SR_RXNE ((uint16_t)0x0020)

#define

USART_SR_TC ((uint16_t)0x0040)

#define

USART_SR_TXE ((uint16_t)0x0080)

#define

USB_ADDR0_RX_ADDR0_RX ((uint16_t)0xFFFE)

#define

USB_ADDR0_TX_ADDR0_TX ((uint16_t)0xFFFE)

#define

USB_ADDR1_RX_ADDR1_RX ((uint16_t)0xFFFE)

#define

USB_ADDR1_TX_ADDR1_TX ((uint16_t)0xFFFE)

#define

USB_ADDR2_RX_ADDR2_RX ((uint16_t)0xFFFE)

#define

USB_ADDR2_TX_ADDR2_TX ((uint16_t)0xFFFE)

#define

USB_ADDR3_RX_ADDR3_RX ((uint16_t)0xFFFE)

#define

USB_ADDR3_TX_ADDR3_TX ((uint16_t)0xFFFE)

#define

USB_ADDR4_RX_ADDR4_RX ((uint16_t)0xFFFE)

#define

USB_ADDR4_TX_ADDR4_TX ((uint16_t)0xFFFE)

#define

USB_ADDR5_RX_ADDR5_RX ((uint16_t)0xFFFE)

#define

USB_ADDR5_TX_ADDR5_TX ((uint16_t)0xFFFE)

#define

USB_ADDR6_RX_ADDR6_RX ((uint16_t)0xFFFE)

#define

USB_ADDR6_TX_ADDR6_TX ((uint16_t)0xFFFE)

#define

USB_ADDR7_RX_ADDR7_RX ((uint16_t)0xFFFE)

#define

USB_ADDR7_TX_ADDR7_TX ((uint16_t)0xFFFE)

#define

USB_BTABLE_BTABLE ((uint16_t)0xFFF8)

#define

USB_CNTR_CTRM ((uint16_t)0x8000)

#define

USB_CNTR_ERRM ((uint16_t)0x2000)

#define

USB_CNTR_ESOFM ((uint16_t)0x0100)

#define

USB_CNTR_FRES ((uint16_t)0x0001)

#define

USB_CNTR_FSUSP ((uint16_t)0x0008)

#define

USB_CNTR_LP_MODE ((uint16_t)0x0004)

#define

USB_CNTR_PDWN ((uint16_t)0x0002)

#define

USB_CNTR_PMAOVRM ((uint16_t)0x4000)

#define

USB_CNTR_RESETM ((uint16_t)0x0400)

#define

USB_CNTR_RESUME ((uint16_t)0x0010)

#define

USB_CNTR_SOFM ((uint16_t)0x0200)

#define

USB_CNTR_SUSPM ((uint16_t)0x0800)

#define

USB_CNTR_WKUPM ((uint16_t)0x1000)

#define

USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000)

#define

USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF)

#define

USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00)

#define

USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400)

#define

USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800)

#define

USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000)

#define

USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000)

#define

USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000)

#define

USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000)

#define

USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000)

#define

USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000)

#define

USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000)

#define

USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000)

#define

USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000)

#define

USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000)

#define

USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000)

#define

USB_COUNT0_RX_BLSIZE ((uint16_t)0x8000)

#define

USB_COUNT0_RX_COUNT0_RX ((uint16_t)0x03FF)

#define

USB_COUNT0_RX_NUM_BLOCK ((uint16_t)0x7C00)

#define

USB_COUNT0_RX_NUM_BLOCK_0 ((uint16_t)0x0400)

#define

USB_COUNT0_RX_NUM_BLOCK_1 ((uint16_t)0x0800)

#define

USB_COUNT0_RX_NUM_BLOCK_2 ((uint16_t)0x1000)

#define

USB_COUNT0_RX_NUM_BLOCK_3 ((uint16_t)0x2000)

#define

USB_COUNT0_RX_NUM_BLOCK_4 ((uint16_t)0x4000)

#define

USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF)

#define

USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000)

#define

USB_COUNT0_TX_COUNT0_TX ((uint16_t)0x03FF)

#define

USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000)

#define

USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF)

#define

USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00)

#define

USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400)

#define

USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800)

#define

USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000)

#define

USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000)

#define

USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000)

#define

USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000)

#define

USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000)

#define

USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000)

#define

USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000)

#define

USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000)

#define

USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000)

#define

USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000)

#define

USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000)

#define

USB_COUNT1_RX_BLSIZE ((uint16_t)0x8000)

#define

USB_COUNT1_RX_COUNT1_RX ((uint16_t)0x03FF)

#define

USB_COUNT1_RX_NUM_BLOCK ((uint16_t)0x7C00)

#define

USB_COUNT1_RX_NUM_BLOCK_0 ((uint16_t)0x0400)

#define

USB_COUNT1_RX_NUM_BLOCK_1 ((uint16_t)0x0800)

#define

USB_COUNT1_RX_NUM_BLOCK_2 ((uint16_t)0x1000)

#define

USB_COUNT1_RX_NUM_BLOCK_3 ((uint16_t)0x2000)

#define

USB_COUNT1_RX_NUM_BLOCK_4 ((uint16_t)0x4000)

#define

USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF)

#define

USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000)

#define

USB_COUNT1_TX_COUNT1_TX ((uint16_t)0x03FF)

#define

USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000)

#define

USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF)

#define

USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00)

#define

USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400)

#define

USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800)

#define

USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000)

#define

USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000)

#define

USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000)

#define

USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000)

#define

USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000)

#define

USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000)

#define

USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000)

#define

USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000)

#define

USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000)

#define

USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000)

#define

USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000)

#define

USB_COUNT2_RX_BLSIZE ((uint16_t)0x8000)

#define

USB_COUNT2_RX_COUNT2_RX ((uint16_t)0x03FF)

#define

USB_COUNT2_RX_NUM_BLOCK ((uint16_t)0x7C00)

#define

USB_COUNT2_RX_NUM_BLOCK_0 ((uint16_t)0x0400)

#define

USB_COUNT2_RX_NUM_BLOCK_1 ((uint16_t)0x0800)

#define

USB_COUNT2_RX_NUM_BLOCK_2 ((uint16_t)0x1000)

#define

USB_COUNT2_RX_NUM_BLOCK_3 ((uint16_t)0x2000)

#define

USB_COUNT2_RX_NUM_BLOCK_4 ((uint16_t)0x4000)

#define

USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF)

#define

USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000)

#define

USB_COUNT2_TX_COUNT2_TX ((uint16_t)0x03FF)

#define

USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000)

#define

USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF)

#define

USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00)

#define

USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400)

#define

USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800)

#define

USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000)

#define

USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000)

#define

USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000)

#define

USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000)

#define

USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000)

#define

USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000)

#define

USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000)

#define

USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000)

#define

USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000)

#define

USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000)

#define

USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000)

#define

USB_COUNT3_RX_BLSIZE ((uint16_t)0x8000)

#define

USB_COUNT3_RX_COUNT3_RX ((uint16_t)0x03FF)

#define

USB_COUNT3_RX_NUM_BLOCK ((uint16_t)0x7C00)

#define

USB_COUNT3_RX_NUM_BLOCK_0 ((uint16_t)0x0400)

#define

USB_COUNT3_RX_NUM_BLOCK_1 ((uint16_t)0x0800)

#define

USB_COUNT3_RX_NUM_BLOCK_2 ((uint16_t)0x1000)

#define

USB_COUNT3_RX_NUM_BLOCK_3 ((uint16_t)0x2000)

#define

USB_COUNT3_RX_NUM_BLOCK_4 ((uint16_t)0x4000)

#define

USB_COUNT3_TX_0_COUNT3_TX_0 ((uint16_t)0x000003FF)

#define

USB_COUNT3_TX_1_COUNT3_TX_1 ((uint16_t)0x03FF0000)

#define

USB_COUNT3_TX_COUNT3_TX ((uint16_t)0x03FF)

#define

USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000)

#define

USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF)

#define

USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00)

#define

USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400)

#define

USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800)

#define

USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000)

#define

USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000)

#define

USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000)

#define

USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000)

#define

USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000)

#define

USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000)

#define

USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000)

#define

USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000)

#define

USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000)

#define

USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000)

#define

USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000)

#define

USB_COUNT4_RX_BLSIZE ((uint16_t)0x8000)

#define

USB_COUNT4_RX_COUNT4_RX ((uint16_t)0x03FF)

#define

USB_COUNT4_RX_NUM_BLOCK ((uint16_t)0x7C00)

#define

USB_COUNT4_RX_NUM_BLOCK_0 ((uint16_t)0x0400)

#define

USB_COUNT4_RX_NUM_BLOCK_1 ((uint16_t)0x0800)

#define

USB_COUNT4_RX_NUM_BLOCK_2 ((uint16_t)0x1000)

#define

USB_COUNT4_RX_NUM_BLOCK_3 ((uint16_t)0x2000)

#define

USB_COUNT4_RX_NUM_BLOCK_4 ((uint16_t)0x4000)

#define

USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF)

#define

USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000)

#define

USB_COUNT4_TX_COUNT4_TX ((uint16_t)0x03FF)

#define

USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000)

#define

USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF)

#define

USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00)

#define

USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400)

#define

USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800)

#define

USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000)

#define

USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000)

#define

USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000)

#define

USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000)

#define

USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000)

#define

USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000)

#define

USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000)

#define

USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000)

#define

USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000)

#define

USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000)

#define

USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000)

#define

USB_COUNT5_RX_BLSIZE ((uint16_t)0x8000)

#define

USB_COUNT5_RX_COUNT5_RX ((uint16_t)0x03FF)

#define

USB_COUNT5_RX_NUM_BLOCK ((uint16_t)0x7C00)

#define

USB_COUNT5_RX_NUM_BLOCK_0 ((uint16_t)0x0400)

#define

USB_COUNT5_RX_NUM_BLOCK_1 ((uint16_t)0x0800)

#define

USB_COUNT5_RX_NUM_BLOCK_2 ((uint16_t)0x1000)

#define

USB_COUNT5_RX_NUM_BLOCK_3 ((uint16_t)0x2000)

#define

USB_COUNT5_RX_NUM_BLOCK_4 ((uint16_t)0x4000)

#define

USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF)

#define

USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000)

#define

USB_COUNT5_TX_COUNT5_TX ((uint16_t)0x03FF)

#define

USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000)

#define

USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF)

#define

USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00)

#define

USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400)

#define

USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800)

#define

USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000)

#define

USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000)

#define

USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000)

#define

USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000)

#define

USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000)

#define

USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000)

#define

USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000)

#define

USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000)

#define

USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000)

#define

USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000)

#define

USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000)

#define

USB_COUNT6_RX_BLSIZE ((uint16_t)0x8000)

#define

USB_COUNT6_RX_COUNT6_RX ((uint16_t)0x03FF)

#define

USB_COUNT6_RX_NUM_BLOCK ((uint16_t)0x7C00)

#define

USB_COUNT6_RX_NUM_BLOCK_0 ((uint16_t)0x0400)

#define

USB_COUNT6_RX_NUM_BLOCK_1 ((uint16_t)0x0800)

#define

USB_COUNT6_RX_NUM_BLOCK_2 ((uint16_t)0x1000)

#define

USB_COUNT6_RX_NUM_BLOCK_3 ((uint16_t)0x2000)

#define

USB_COUNT6_RX_NUM_BLOCK_4 ((uint16_t)0x4000)

#define

USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF)

#define

USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000)

#define

USB_COUNT6_TX_COUNT6_TX ((uint16_t)0x03FF)

#define

USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000)

#define

USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF)

#define

USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00)

#define

USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400)

#define

USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800)

#define

USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000)

#define

USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000)

#define

USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000)

#define

USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000)

#define

USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000)

#define

USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000)

#define

USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000)

#define

USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000)

#define

USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000)

#define

USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000)

#define

USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000)

#define

USB_COUNT7_RX_BLSIZE ((uint16_t)0x8000)

#define

USB_COUNT7_RX_COUNT7_RX ((uint16_t)0x03FF)

#define

USB_COUNT7_RX_NUM_BLOCK ((uint16_t)0x7C00)

#define

USB_COUNT7_RX_NUM_BLOCK_0 ((uint16_t)0x0400)

#define

USB_COUNT7_RX_NUM_BLOCK_1 ((uint16_t)0x0800)

#define

USB_COUNT7_RX_NUM_BLOCK_2 ((uint16_t)0x1000)

#define

USB_COUNT7_RX_NUM_BLOCK_3 ((uint16_t)0x2000)

#define

USB_COUNT7_RX_NUM_BLOCK_4 ((uint16_t)0x4000)

#define

USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF)

#define

USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000)

#define

USB_COUNT7_TX_COUNT7_TX ((uint16_t)0x03FF)

#define

USB_DADDR_ADD ((uint8_t)0x7F)

#define

USB_DADDR_ADD0 ((uint8_t)0x01)

#define

USB_DADDR_ADD1 ((uint8_t)0x02)

#define

USB_DADDR_ADD2 ((uint8_t)0x04)

#define

USB_DADDR_ADD3 ((uint8_t)0x08)

#define

USB_DADDR_ADD4 ((uint8_t)0x10)

#define

USB_DADDR_ADD5 ((uint8_t)0x20)

#define

USB_DADDR_ADD6 ((uint8_t)0x40)

#define

USB_DADDR_EF ((uint8_t)0x80)

#define

USB_EP0R_CTR_RX ((uint16_t)0x8000)

#define

USB_EP0R_CTR_TX ((uint16_t)0x0080)

#define

USB_EP0R_DTOG_RX ((uint16_t)0x4000)

#define

USB_EP0R_DTOG_TX ((uint16_t)0x0040)

#define

USB_EP0R_EA ((uint16_t)0x000F)

#define

USB_EP0R_EP_KIND ((uint16_t)0x0100)

#define

USB_EP0R_EP_TYPE ((uint16_t)0x0600)

#define

USB_EP0R_EP_TYPE_0 ((uint16_t)0x0200)

#define

USB_EP0R_EP_TYPE_1 ((uint16_t)0x0400)

#define

USB_EP0R_SETUP ((uint16_t)0x0800)

#define

USB_EP0R_STAT_RX ((uint16_t)0x3000)

#define

USB_EP0R_STAT_RX_0 ((uint16_t)0x1000)

#define

USB_EP0R_STAT_RX_1 ((uint16_t)0x2000)

#define

USB_EP0R_STAT_TX ((uint16_t)0x0030)

#define

USB_EP0R_STAT_TX_0 ((uint16_t)0x0010)

#define

USB_EP0R_STAT_TX_1 ((uint16_t)0x0020)

#define

USB_EP1R_CTR_RX ((uint16_t)0x8000)

#define

USB_EP1R_CTR_TX ((uint16_t)0x0080)

#define

USB_EP1R_DTOG_RX ((uint16_t)0x4000)

#define

USB_EP1R_DTOG_TX ((uint16_t)0x0040)

#define

USB_EP1R_EA ((uint16_t)0x000F)

#define

USB_EP1R_EP_KIND ((uint16_t)0x0100)

#define

USB_EP1R_EP_TYPE ((uint16_t)0x0600)

#define

USB_EP1R_EP_TYPE_0 ((uint16_t)0x0200)

#define

USB_EP1R_EP_TYPE_1 ((uint16_t)0x0400)

#define

USB_EP1R_SETUP ((uint16_t)0x0800)

#define

USB_EP1R_STAT_RX ((uint16_t)0x3000)

#define

USB_EP1R_STAT_RX_0 ((uint16_t)0x1000)

#define

USB_EP1R_STAT_RX_1 ((uint16_t)0x2000)

#define

USB_EP1R_STAT_TX ((uint16_t)0x0030)

#define

USB_EP1R_STAT_TX_0 ((uint16_t)0x0010)

#define

USB_EP1R_STAT_TX_1 ((uint16_t)0x0020)

#define

USB_EP2R_CTR_RX ((uint16_t)0x8000)

#define

USB_EP2R_CTR_TX ((uint16_t)0x0080)

#define

USB_EP2R_DTOG_RX ((uint16_t)0x4000)

#define

USB_EP2R_DTOG_TX ((uint16_t)0x0040)

#define

USB_EP2R_EA ((uint16_t)0x000F)

#define

USB_EP2R_EP_KIND ((uint16_t)0x0100)

#define

USB_EP2R_EP_TYPE ((uint16_t)0x0600)

#define

USB_EP2R_EP_TYPE_0 ((uint16_t)0x0200)

#define

USB_EP2R_EP_TYPE_1 ((uint16_t)0x0400)

#define

USB_EP2R_SETUP ((uint16_t)0x0800)

#define

USB_EP2R_STAT_RX ((uint16_t)0x3000)

#define

USB_EP2R_STAT_RX_0 ((uint16_t)0x1000)

#define

USB_EP2R_STAT_RX_1 ((uint16_t)0x2000)

#define

USB_EP2R_STAT_TX ((uint16_t)0x0030)

#define

USB_EP2R_STAT_TX_0 ((uint16_t)0x0010)

#define

USB_EP2R_STAT_TX_1 ((uint16_t)0x0020)

#define

USB_EP3R_CTR_RX ((uint16_t)0x8000)

#define

USB_EP3R_CTR_TX ((uint16_t)0x0080)

#define

USB_EP3R_DTOG_RX ((uint16_t)0x4000)

#define

USB_EP3R_DTOG_TX ((uint16_t)0x0040)

#define

USB_EP3R_EA ((uint16_t)0x000F)

#define

USB_EP3R_EP_KIND ((uint16_t)0x0100)

#define

USB_EP3R_EP_TYPE ((uint16_t)0x0600)

#define

USB_EP3R_EP_TYPE_0 ((uint16_t)0x0200)

#define

USB_EP3R_EP_TYPE_1 ((uint16_t)0x0400)

#define

USB_EP3R_SETUP ((uint16_t)0x0800)

#define

USB_EP3R_STAT_RX ((uint16_t)0x3000)

#define

USB_EP3R_STAT_RX_0 ((uint16_t)0x1000)

#define

USB_EP3R_STAT_RX_1 ((uint16_t)0x2000)

#define

USB_EP3R_STAT_TX ((uint16_t)0x0030)

#define

USB_EP3R_STAT_TX_0 ((uint16_t)0x0010)

#define

USB_EP3R_STAT_TX_1 ((uint16_t)0x0020)

#define

USB_EP4R_CTR_RX ((uint16_t)0x8000)

#define

USB_EP4R_CTR_TX ((uint16_t)0x0080)

#define

USB_EP4R_DTOG_RX ((uint16_t)0x4000)

#define

USB_EP4R_DTOG_TX ((uint16_t)0x0040)

#define

USB_EP4R_EA ((uint16_t)0x000F)

#define

USB_EP4R_EP_KIND ((uint16_t)0x0100)

#define

USB_EP4R_EP_TYPE ((uint16_t)0x0600)

#define

USB_EP4R_EP_TYPE_0 ((uint16_t)0x0200)

#define

USB_EP4R_EP_TYPE_1 ((uint16_t)0x0400)

#define

USB_EP4R_SETUP ((uint16_t)0x0800)

#define

USB_EP4R_STAT_RX ((uint16_t)0x3000)

#define

USB_EP4R_STAT_RX_0 ((uint16_t)0x1000)

#define

USB_EP4R_STAT_RX_1 ((uint16_t)0x2000)

#define

USB_EP4R_STAT_TX ((uint16_t)0x0030)

#define

USB_EP4R_STAT_TX_0 ((uint16_t)0x0010)

#define

USB_EP4R_STAT_TX_1 ((uint16_t)0x0020)

#define

USB_EP5R_CTR_RX ((uint16_t)0x8000)

#define

USB_EP5R_CTR_TX ((uint16_t)0x0080)

#define

USB_EP5R_DTOG_RX ((uint16_t)0x4000)

#define

USB_EP5R_DTOG_TX ((uint16_t)0x0040)

#define

USB_EP5R_EA ((uint16_t)0x000F)

#define

USB_EP5R_EP_KIND ((uint16_t)0x0100)

#define

USB_EP5R_EP_TYPE ((uint16_t)0x0600)

#define

USB_EP5R_EP_TYPE_0 ((uint16_t)0x0200)

#define

USB_EP5R_EP_TYPE_1 ((uint16_t)0x0400)

#define

USB_EP5R_SETUP ((uint16_t)0x0800)

#define

USB_EP5R_STAT_RX ((uint16_t)0x3000)

#define

USB_EP5R_STAT_RX_0 ((uint16_t)0x1000)

#define

USB_EP5R_STAT_RX_1 ((uint16_t)0x2000)

#define

USB_EP5R_STAT_TX ((uint16_t)0x0030)

#define

USB_EP5R_STAT_TX_0 ((uint16_t)0x0010)

#define

USB_EP5R_STAT_TX_1 ((uint16_t)0x0020)

#define

USB_EP6R_CTR_RX ((uint16_t)0x8000)

#define

USB_EP6R_CTR_TX ((uint16_t)0x0080)

#define

USB_EP6R_DTOG_RX ((uint16_t)0x4000)

#define

USB_EP6R_DTOG_TX ((uint16_t)0x0040)

#define

USB_EP6R_EA ((uint16_t)0x000F)

#define

USB_EP6R_EP_KIND ((uint16_t)0x0100)

#define

USB_EP6R_EP_TYPE ((uint16_t)0x0600)

#define

USB_EP6R_EP_TYPE_0 ((uint16_t)0x0200)

#define

USB_EP6R_EP_TYPE_1 ((uint16_t)0x0400)

#define

USB_EP6R_SETUP ((uint16_t)0x0800)

#define

USB_EP6R_STAT_RX ((uint16_t)0x3000)

#define

USB_EP6R_STAT_RX_0 ((uint16_t)0x1000)

#define

USB_EP6R_STAT_RX_1 ((uint16_t)0x2000)

#define

USB_EP6R_STAT_TX ((uint16_t)0x0030)

#define

USB_EP6R_STAT_TX_0 ((uint16_t)0x0010)

#define

USB_EP6R_STAT_TX_1 ((uint16_t)0x0020)

#define

USB_EP7R_CTR_RX ((uint16_t)0x8000)

#define

USB_EP7R_CTR_TX ((uint16_t)0x0080)

#define

USB_EP7R_DTOG_RX ((uint16_t)0x4000)

#define

USB_EP7R_DTOG_TX ((uint16_t)0x0040)

#define

USB_EP7R_EA ((uint16_t)0x000F)

#define

USB_EP7R_EP_KIND ((uint16_t)0x0100)

#define

USB_EP7R_EP_TYPE ((uint16_t)0x0600)

#define

USB_EP7R_EP_TYPE_0 ((uint16_t)0x0200)

#define

USB_EP7R_EP_TYPE_1 ((uint16_t)0x0400)

#define

USB_EP7R_SETUP ((uint16_t)0x0800)

#define

USB_EP7R_STAT_RX ((uint16_t)0x3000)

#define

USB_EP7R_STAT_RX_0 ((uint16_t)0x1000)

#define

USB_EP7R_STAT_RX_1 ((uint16_t)0x2000)

#define

USB_EP7R_STAT_TX ((uint16_t)0x0030)

#define

USB_EP7R_STAT_TX_0 ((uint16_t)0x0010)

#define

USB_EP7R_STAT_TX_1 ((uint16_t)0x0020)

#define

USB_FNR_FN ((uint16_t)0x07FF)

#define

USB_FNR_LCK ((uint16_t)0x2000)

#define

USB_FNR_LSOF ((uint16_t)0x1800)

#define

USB_FNR_RXDM ((uint16_t)0x4000)

#define

USB_FNR_RXDP ((uint16_t)0x8000)

#define

USB_ISTR_CTR ((uint16_t)0x8000)

#define

USB_ISTR_DIR ((uint16_t)0x0010)

#define

USB_ISTR_EP_ID ((uint16_t)0x000F)

#define

USB_ISTR_ERR ((uint16_t)0x2000)

#define

USB_ISTR_ESOF ((uint16_t)0x0100)

#define

USB_ISTR_PMAOVR ((uint16_t)0x4000)

#define

USB_ISTR_RESET ((uint16_t)0x0400)

#define

USB_ISTR_SOF ((uint16_t)0x0200)

#define

USB_ISTR_SUSP ((uint16_t)0x0800)

#define

USB_ISTR_WKUP ((uint16_t)0x1000)

#define

WWDG_CFR_EWI ((uint16_t)0x0200)

#define

WWDG_CFR_W ((uint16_t)0x007F)

#define

WWDG_CFR_W0 ((uint16_t)0x0001)

#define

WWDG_CFR_W1 ((uint16_t)0x0002)

#define

WWDG_CFR_W2 ((uint16_t)0x0004)

#define

WWDG_CFR_W3 ((uint16_t)0x0008)

#define

WWDG_CFR_W4 ((uint16_t)0x0010)

#define

WWDG_CFR_W5 ((uint16_t)0x0020)

#define

WWDG_CFR_W6 ((uint16_t)0x0040)

#define

WWDG_CFR_WDGTB ((uint16_t)0x0180)

#define

WWDG_CFR_WDGTB0 ((uint16_t)0x0080)

#define

WWDG_CFR_WDGTB1 ((uint16_t)0x0100)

#define

WWDG_CR_T ((uint8_t)0x7F)

#define

WWDG_CR_T0 ((uint8_t)0x01)

#define

WWDG_CR_T1 ((uint8_t)0x02)

#define

WWDG_CR_T2 ((uint8_t)0x04)

#define

WWDG_CR_T3 ((uint8_t)0x08)

#define

WWDG_CR_T4 ((uint8_t)0x10)

#define

WWDG_CR_T5 ((uint8_t)0x20)

#define

WWDG_CR_T6 ((uint8_t)0x40)

#define

WWDG_CR_WDGA ((uint8_t)0x80)

#define

WWDG_SR_EWIF ((uint8_t)0x01)

Define Documentation

#define ADC_CR1_AWDCH ((uint32_t)0x0000001F)

AWDCH[4:0] bits (Analog watchdog channel select bits)

Definition at line 3710 of file stm32f10x.h.

#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001)

Bit 0

Definition at line 3711 of file stm32f10x.h.

#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002)

Bit 1

Definition at line 3712 of file stm32f10x.h.

#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004)

Bit 2

Definition at line 3713 of file stm32f10x.h.

#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008)

Bit 3

Definition at line 3714 of file stm32f10x.h.

#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010)

Bit 4

Definition at line 3715 of file stm32f10x.h.

#define ADC_CR1_AWDEN ((uint32_t)0x00800000)

Analog watchdog enable on regular channels

Definition at line 3738 of file stm32f10x.h.

#define ADC_CR1_AWDIE ((uint32_t)0x00000040)

Analog Watchdog interrupt enable

Definition at line 3718 of file stm32f10x.h.

#define ADC_CR1_AWDSGL ((uint32_t)0x00000200)

Enable the watchdog on a single channel in scan mode

Definition at line 3721 of file stm32f10x.h.

#define ADC_CR1_DISCEN ((uint32_t)0x00000800)

Discontinuous mode on regular channels

Definition at line 3723 of file stm32f10x.h.

#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000)

DISCNUM[2:0] bits (Discontinuous mode channel count)

Definition at line 3726 of file stm32f10x.h.

#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000)

Bit 0

Definition at line 3727 of file stm32f10x.h.

#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000)

Bit 1

Definition at line 3728 of file stm32f10x.h.

#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000)

Bit 2

Definition at line 3729 of file stm32f10x.h.

#define ADC_CR1_DUALMOD ((uint32_t)0x000F0000)

DUALMOD[3:0] bits (Dual mode selection)

Definition at line 3731 of file stm32f10x.h.

#define ADC_CR1_DUALMOD_0 ((uint32_t)0x00010000)

Bit 0

Definition at line 3732 of file stm32f10x.h.

#define ADC_CR1_DUALMOD_1 ((uint32_t)0x00020000)

Bit 1

Definition at line 3733 of file stm32f10x.h.

#define ADC_CR1_DUALMOD_2 ((uint32_t)0x00040000)

Bit 2

Definition at line 3734 of file stm32f10x.h.

#define ADC_CR1_DUALMOD_3 ((uint32_t)0x00080000)

Bit 3

Definition at line 3735 of file stm32f10x.h.

#define ADC_CR1_EOCIE ((uint32_t)0x00000020)

Interrupt enable for EOC

Definition at line 3717 of file stm32f10x.h.

#define ADC_CR1_JAUTO ((uint32_t)0x00000400)

Automatic injected group conversion

Definition at line 3722 of file stm32f10x.h.

#define ADC_CR1_JAWDEN ((uint32_t)0x00400000)

Analog watchdog enable on injected channels

Definition at line 3737 of file stm32f10x.h.

#define ADC_CR1_JDISCEN ((uint32_t)0x00001000)

Discontinuous mode on injected channels

Definition at line 3724 of file stm32f10x.h.

#define ADC_CR1_JEOCIE ((uint32_t)0x00000080)

Interrupt enable for injected channels

Definition at line 3719 of file stm32f10x.h.

#define ADC_CR1_SCAN ((uint32_t)0x00000100)

Scan mode

Definition at line 3720 of file stm32f10x.h.

#define ADC_CR2_ADON ((uint32_t)0x00000001)

A/D Converter ON / OFF

Definition at line 3742 of file stm32f10x.h.

#define ADC_CR2_ALIGN ((uint32_t)0x00000800)

Data Alignment

Definition at line 3747 of file stm32f10x.h.

#define ADC_CR2_CAL ((uint32_t)0x00000004)

A/D Calibration

Definition at line 3744 of file stm32f10x.h.

#define ADC_CR2_CONT ((uint32_t)0x00000002)

Continuous Conversion

Definition at line 3743 of file stm32f10x.h.

#define ADC_CR2_DMA ((uint32_t)0x00000100)

Direct Memory access mode

Definition at line 3746 of file stm32f10x.h.

#define ADC_CR2_EXTSEL ((uint32_t)0x000E0000)

EXTSEL[2:0] bits (External Event Select for regular group)

Definition at line 3756 of file stm32f10x.h.

#define ADC_CR2_EXTSEL_0 ((uint32_t)0x00020000)

Bit 0

Definition at line 3757 of file stm32f10x.h.

#define ADC_CR2_EXTSEL_1 ((uint32_t)0x00040000)

Bit 1

Definition at line 3758 of file stm32f10x.h.

#define ADC_CR2_EXTSEL_2 ((uint32_t)0x00080000)

Bit 2

Definition at line 3759 of file stm32f10x.h.

#define ADC_CR2_EXTTRIG ((uint32_t)0x00100000)

External Trigger Conversion mode for regular channels

Definition at line 3761 of file stm32f10x.h.

#define ADC_CR2_JEXTSEL ((uint32_t)0x00007000)

JEXTSEL[2:0] bits (External event select for injected group)

Definition at line 3749 of file stm32f10x.h.

#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00001000)

Bit 0

Definition at line 3750 of file stm32f10x.h.

#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00002000)

Bit 1

Definition at line 3751 of file stm32f10x.h.

#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00004000)

Bit 2

Definition at line 3752 of file stm32f10x.h.

#define ADC_CR2_JEXTTRIG ((uint32_t)0x00008000)

External Trigger Conversion mode for injected channels

Definition at line 3754 of file stm32f10x.h.

#define ADC_CR2_JSWSTART ((uint32_t)0x00200000)

Start Conversion of injected channels

Definition at line 3762 of file stm32f10x.h.

#define ADC_CR2_RSTCAL ((uint32_t)0x00000008)

Reset Calibration

Definition at line 3745 of file stm32f10x.h.

#define ADC_CR2_SWSTART ((uint32_t)0x00400000)

Start Conversion of regular channels

Definition at line 3763 of file stm32f10x.h.

#define ADC_CR2_TSVREFE ((uint32_t)0x00800000)

Temperature Sensor and VREFINT Enable

Definition at line 3764 of file stm32f10x.h.

#define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000)

ADC2 data

Definition at line 4044 of file stm32f10x.h.

#define ADC_DR_DATA ((uint32_t)0x0000FFFF)

Regular data

Definition at line 4043 of file stm32f10x.h.

#define ADC_HTR_HT ((uint16_t)0x0FFF)

Analog watchdog high threshold

Definition at line 3871 of file stm32f10x.h.

#define ADC_JDR1_JDATA ((uint16_t)0xFFFF)

Injected data

Definition at line 4031 of file stm32f10x.h.

#define ADC_JDR2_JDATA ((uint16_t)0xFFFF)

Injected data

Definition at line 4034 of file stm32f10x.h.

#define ADC_JDR3_JDATA ((uint16_t)0xFFFF)

Injected data

Definition at line 4037 of file stm32f10x.h.

#define ADC_JDR4_JDATA ((uint16_t)0xFFFF)

Injected data

Definition at line 4040 of file stm32f10x.h.

#define ADC_JOFR1_JOFFSET1 ((uint16_t)0x0FFF)

Data offset for injected channel 1

Definition at line 3859 of file stm32f10x.h.

#define ADC_JOFR2_JOFFSET2 ((uint16_t)0x0FFF)

Data offset for injected channel 2

Definition at line 3862 of file stm32f10x.h.

#define ADC_JOFR3_JOFFSET3 ((uint16_t)0x0FFF)

Data offset for injected channel 3

Definition at line 3865 of file stm32f10x.h.

#define ADC_JOFR4_JOFFSET4 ((uint16_t)0x0FFF)

Data offset for injected channel 4

Definition at line 3868 of file stm32f10x.h.

#define ADC_JSQR_JL ((uint32_t)0x00300000)

JL[1:0] bits (Injected Sequence length)

Definition at line 4026 of file stm32f10x.h.

#define ADC_JSQR_JL_0 ((uint32_t)0x00100000)

Bit 0

Definition at line 4027 of file stm32f10x.h.

#define ADC_JSQR_JL_1 ((uint32_t)0x00200000)

Bit 1

Definition at line 4028 of file stm32f10x.h.

#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F)

JSQ1[4:0] bits (1st conversion in injected sequence)

Definition at line 3998 of file stm32f10x.h.

#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001)

Bit 0

Definition at line 3999 of file stm32f10x.h.

#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002)

Bit 1

Definition at line 4000 of file stm32f10x.h.

#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004)

Bit 2

Definition at line 4001 of file stm32f10x.h.

#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008)

Bit 3

Definition at line 4002 of file stm32f10x.h.

#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010)

Bit 4

Definition at line 4003 of file stm32f10x.h.

#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0)

JSQ2[4:0] bits (2nd conversion in injected sequence)

Definition at line 4005 of file stm32f10x.h.

#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020)

Bit 0

Definition at line 4006 of file stm32f10x.h.

#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040)

Bit 1

Definition at line 4007 of file stm32f10x.h.

#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080)

Bit 2

Definition at line 4008 of file stm32f10x.h.

#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100)

Bit 3

Definition at line 4009 of file stm32f10x.h.

#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200)

Bit 4

Definition at line 4010 of file stm32f10x.h.

#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00)

JSQ3[4:0] bits (3rd conversion in injected sequence)

Definition at line 4012 of file stm32f10x.h.

#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400)

Bit 0

Definition at line 4013 of file stm32f10x.h.

#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800)

Bit 1

Definition at line 4014 of file stm32f10x.h.

#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000)

Bit 2

Definition at line 4015 of file stm32f10x.h.

#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000)

Bit 3

Definition at line 4016 of file stm32f10x.h.

#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000)

Bit 4

Definition at line 4017 of file stm32f10x.h.

#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000)

JSQ4[4:0] bits (4th conversion in injected sequence)

Definition at line 4019 of file stm32f10x.h.

#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000)

Bit 0

Definition at line 4020 of file stm32f10x.h.

#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000)

Bit 1

Definition at line 4021 of file stm32f10x.h.

#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000)

Bit 2

Definition at line 4022 of file stm32f10x.h.

#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000)

Bit 3

Definition at line 4023 of file stm32f10x.h.

#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000)

Bit 4

Definition at line 4024 of file stm32f10x.h.

#define ADC_LTR_LT ((uint16_t)0x0FFF)

Analog watchdog low threshold

Definition at line 3874 of file stm32f10x.h.

#define ADC_SMPR1_SMP10 ((uint32_t)0x00000007)

SMP10[2:0] bits (Channel 10 Sample time selection)

Definition at line 3767 of file stm32f10x.h.

#define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001)

Bit 0

Definition at line 3768 of file stm32f10x.h.

#define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002)

Bit 1

Definition at line 3769 of file stm32f10x.h.

#define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004)

Bit 2

Definition at line 3770 of file stm32f10x.h.

#define ADC_SMPR1_SMP11 ((uint32_t)0x00000038)

SMP11[2:0] bits (Channel 11 Sample time selection)

Definition at line 3772 of file stm32f10x.h.

#define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008)

Bit 0

Definition at line 3773 of file stm32f10x.h.

#define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010)

Bit 1

Definition at line 3774 of file stm32f10x.h.

#define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020)

Bit 2

Definition at line 3775 of file stm32f10x.h.

#define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0)

SMP12[2:0] bits (Channel 12 Sample time selection)

Definition at line 3777 of file stm32f10x.h.

#define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040)

Bit 0

Definition at line 3778 of file stm32f10x.h.

#define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080)

Bit 1

Definition at line 3779 of file stm32f10x.h.

#define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100)

Bit 2

Definition at line 3780 of file stm32f10x.h.

#define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00)

SMP13[2:0] bits (Channel 13 Sample time selection)

Definition at line 3782 of file stm32f10x.h.

#define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200)

Bit 0

Definition at line 3783 of file stm32f10x.h.

#define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400)

Bit 1

Definition at line 3784 of file stm32f10x.h.

#define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800)

Bit 2

Definition at line 3785 of file stm32f10x.h.

#define ADC_SMPR1_SMP14 ((uint32_t)0x00007000)

SMP14[2:0] bits (Channel 14 Sample time selection)

Definition at line 3787 of file stm32f10x.h.

#define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000)

Bit 0

Definition at line 3788 of file stm32f10x.h.

#define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000)

Bit 1

Definition at line 3789 of file stm32f10x.h.

#define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000)

Bit 2

Definition at line 3790 of file stm32f10x.h.

#define ADC_SMPR1_SMP15 ((uint32_t)0x00038000)

SMP15[2:0] bits (Channel 15 Sample time selection)

Definition at line 3792 of file stm32f10x.h.

#define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000)

Bit 0

Definition at line 3793 of file stm32f10x.h.

#define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000)

Bit 1

Definition at line 3794 of file stm32f10x.h.

#define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000)

Bit 2

Definition at line 3795 of file stm32f10x.h.

#define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000)

SMP16[2:0] bits (Channel 16 Sample time selection)

Definition at line 3797 of file stm32f10x.h.

#define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000)

Bit 0

Definition at line 3798 of file stm32f10x.h.

#define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000)

Bit 1

Definition at line 3799 of file stm32f10x.h.

#define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000)

Bit 2

Definition at line 3800 of file stm32f10x.h.

#define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000)

SMP17[2:0] bits (Channel 17 Sample time selection)

Definition at line 3802 of file stm32f10x.h.

#define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000)

Bit 0

Definition at line 3803 of file stm32f10x.h.

#define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000)

Bit 1

Definition at line 3804 of file stm32f10x.h.

#define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000)

Bit 2

Definition at line 3805 of file stm32f10x.h.

#define ADC_SMPR2_SMP0 ((uint32_t)0x00000007)

SMP0[2:0] bits (Channel 0 Sample time selection)

Definition at line 3808 of file stm32f10x.h.

#define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001)

Bit 0

Definition at line 3809 of file stm32f10x.h.

#define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002)

Bit 1

Definition at line 3810 of file stm32f10x.h.

#define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004)

Bit 2

Definition at line 3811 of file stm32f10x.h.

#define ADC_SMPR2_SMP1 ((uint32_t)0x00000038)

SMP1[2:0] bits (Channel 1 Sample time selection)

Definition at line 3813 of file stm32f10x.h.

#define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008)

Bit 0

Definition at line 3814 of file stm32f10x.h.

#define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010)

Bit 1

Definition at line 3815 of file stm32f10x.h.

#define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020)

Bit 2

Definition at line 3816 of file stm32f10x.h.

#define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0)

SMP2[2:0] bits (Channel 2 Sample time selection)

Definition at line 3818 of file stm32f10x.h.

#define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040)

Bit 0

Definition at line 3819 of file stm32f10x.h.

#define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080)

Bit 1

Definition at line 3820 of file stm32f10x.h.

#define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100)

Bit 2

Definition at line 3821 of file stm32f10x.h.

#define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00)

SMP3[2:0] bits (Channel 3 Sample time selection)

Definition at line 3823 of file stm32f10x.h.

#define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200)

Bit 0

Definition at line 3824 of file stm32f10x.h.

#define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400)

Bit 1

Definition at line 3825 of file stm32f10x.h.

#define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800)

Bit 2

Definition at line 3826 of file stm32f10x.h.

#define ADC_SMPR2_SMP4 ((uint32_t)0x00007000)

SMP4[2:0] bits (Channel 4 Sample time selection)

Definition at line 3828 of file stm32f10x.h.

#define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000)

Bit 0

Definition at line 3829 of file stm32f10x.h.

#define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000)

Bit 1

Definition at line 3830 of file stm32f10x.h.

#define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000)

Bit 2

Definition at line 3831 of file stm32f10x.h.

#define ADC_SMPR2_SMP5 ((uint32_t)0x00038000)

SMP5[2:0] bits (Channel 5 Sample time selection)

Definition at line 3833 of file stm32f10x.h.

#define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000)

Bit 0

Definition at line 3834 of file stm32f10x.h.

#define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000)

Bit 1

Definition at line 3835 of file stm32f10x.h.

#define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000)

Bit 2

Definition at line 3836 of file stm32f10x.h.

#define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000)

SMP6[2:0] bits (Channel 6 Sample time selection)

Definition at line 3838 of file stm32f10x.h.

#define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000)

Bit 0

Definition at line 3839 of file stm32f10x.h.

#define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000)

Bit 1

Definition at line 3840 of file stm32f10x.h.

#define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000)

Bit 2

Definition at line 3841 of file stm32f10x.h.

#define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000)

SMP7[2:0] bits (Channel 7 Sample time selection)

Definition at line 3843 of file stm32f10x.h.

#define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000)

Bit 0

Definition at line 3844 of file stm32f10x.h.

#define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000)

Bit 1

Definition at line 3845 of file stm32f10x.h.

#define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000)

Bit 2

Definition at line 3846 of file stm32f10x.h.

#define ADC_SMPR2_SMP8 ((uint32_t)0x07000000)

SMP8[2:0] bits (Channel 8 Sample time selection)

Definition at line 3848 of file stm32f10x.h.

#define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000)

Bit 0

Definition at line 3849 of file stm32f10x.h.

#define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000)

Bit 1

Definition at line 3850 of file stm32f10x.h.

#define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000)

Bit 2

Definition at line 3851 of file stm32f10x.h.

#define ADC_SMPR2_SMP9 ((uint32_t)0x38000000)

SMP9[2:0] bits (Channel 9 Sample time selection)

Definition at line 3853 of file stm32f10x.h.

#define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000)

Bit 0

Definition at line 3854 of file stm32f10x.h.

#define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000)

Bit 1

Definition at line 3855 of file stm32f10x.h.

#define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000)

Bit 2

Definition at line 3856 of file stm32f10x.h.

#define ADC_SQR1_L ((uint32_t)0x00F00000)

L[3:0] bits (Regular channel sequence length)

Definition at line 3905 of file stm32f10x.h.

#define ADC_SQR1_L_0 ((uint32_t)0x00100000)

Bit 0

Definition at line 3906 of file stm32f10x.h.

#define ADC_SQR1_L_1 ((uint32_t)0x00200000)

Bit 1

Definition at line 3907 of file stm32f10x.h.

#define ADC_SQR1_L_2 ((uint32_t)0x00400000)

Bit 2

Definition at line 3908 of file stm32f10x.h.

#define ADC_SQR1_L_3 ((uint32_t)0x00800000)

Bit 3

Definition at line 3909 of file stm32f10x.h.

#define ADC_SQR1_SQ13 ((uint32_t)0x0000001F)

SQ13[4:0] bits (13th conversion in regular sequence)

Definition at line 3877 of file stm32f10x.h.

#define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001)

Bit 0

Definition at line 3878 of file stm32f10x.h.

#define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002)

Bit 1

Definition at line 3879 of file stm32f10x.h.

#define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004)

Bit 2

Definition at line 3880 of file stm32f10x.h.

#define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008)

Bit 3

Definition at line 3881 of file stm32f10x.h.

#define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010)

Bit 4

Definition at line 3882 of file stm32f10x.h.

#define ADC_SQR1_SQ14 ((uint32_t)0x000003E0)

SQ14[4:0] bits (14th conversion in regular sequence)

Definition at line 3884 of file stm32f10x.h.

#define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020)

Bit 0

Definition at line 3885 of file stm32f10x.h.

#define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040)

Bit 1

Definition at line 3886 of file stm32f10x.h.

#define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080)

Bit 2

Definition at line 3887 of file stm32f10x.h.

#define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100)

Bit 3

Definition at line 3888 of file stm32f10x.h.

#define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200)

Bit 4

Definition at line 3889 of file stm32f10x.h.

#define ADC_SQR1_SQ15 ((uint32_t)0x00007C00)

SQ15[4:0] bits (15th conversion in regular sequence)

Definition at line 3891 of file stm32f10x.h.

#define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400)

Bit 0

Definition at line 3892 of file stm32f10x.h.

#define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800)

Bit 1

Definition at line 3893 of file stm32f10x.h.

#define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000)

Bit 2

Definition at line 3894 of file stm32f10x.h.

#define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000)

Bit 3

Definition at line 3895 of file stm32f10x.h.

#define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000)

Bit 4

Definition at line 3896 of file stm32f10x.h.

#define ADC_SQR1_SQ16 ((uint32_t)0x000F8000)

SQ16[4:0] bits (16th conversion in regular sequence)

Definition at line 3898 of file stm32f10x.h.

#define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000)

Bit 0

Definition at line 3899 of file stm32f10x.h.

#define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000)

Bit 1

Definition at line 3900 of file stm32f10x.h.

#define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000)

Bit 2

Definition at line 3901 of file stm32f10x.h.

#define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000)

Bit 3

Definition at line 3902 of file stm32f10x.h.

#define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000)

Bit 4

Definition at line 3903 of file stm32f10x.h.

#define ADC_SQR2_SQ10 ((uint32_t)0x000F8000)

SQ10[4:0] bits (10th conversion in regular sequence)

Definition at line 3933 of file stm32f10x.h.

#define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000)

Bit 0

Definition at line 3934 of file stm32f10x.h.

#define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000)

Bit 1

Definition at line 3935 of file stm32f10x.h.

#define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000)

Bit 2

Definition at line 3936 of file stm32f10x.h.

#define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000)

Bit 3

Definition at line 3937 of file stm32f10x.h.

#define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000)

Bit 4

Definition at line 3938 of file stm32f10x.h.

#define ADC_SQR2_SQ11 ((uint32_t)0x01F00000)

SQ11[4:0] bits (11th conversion in regular sequence)

Definition at line 3940 of file stm32f10x.h.

#define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000)

Bit 0

Definition at line 3941 of file stm32f10x.h.

#define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000)

Bit 1

Definition at line 3942 of file stm32f10x.h.

#define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000)

Bit 2

Definition at line 3943 of file stm32f10x.h.

#define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000)

Bit 3

Definition at line 3944 of file stm32f10x.h.

#define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000)

Bit 4

Definition at line 3945 of file stm32f10x.h.

#define ADC_SQR2_SQ12 ((uint32_t)0x3E000000)

SQ12[4:0] bits (12th conversion in regular sequence)

Definition at line 3947 of file stm32f10x.h.

#define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000)

Bit 0

Definition at line 3948 of file stm32f10x.h.

#define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000)

Bit 1

Definition at line 3949 of file stm32f10x.h.

#define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000)

Bit 2

Definition at line 3950 of file stm32f10x.h.

#define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000)

Bit 3

Definition at line 3951 of file stm32f10x.h.

#define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000)

Bit 4

Definition at line 3952 of file stm32f10x.h.

#define ADC_SQR2_SQ7 ((uint32_t)0x0000001F)

SQ7[4:0] bits (7th conversion in regular sequence)

Definition at line 3912 of file stm32f10x.h.

#define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001)

Bit 0

Definition at line 3913 of file stm32f10x.h.

#define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002)

Bit 1

Definition at line 3914 of file stm32f10x.h.

#define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004)

Bit 2

Definition at line 3915 of file stm32f10x.h.

#define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008)

Bit 3

Definition at line 3916 of file stm32f10x.h.

#define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010)

Bit 4

Definition at line 3917 of file stm32f10x.h.

#define ADC_SQR2_SQ8 ((uint32_t)0x000003E0)

SQ8[4:0] bits (8th conversion in regular sequence)

Definition at line 3919 of file stm32f10x.h.

#define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020)

Bit 0

Definition at line 3920 of file stm32f10x.h.

#define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040)

Bit 1

Definition at line 3921 of file stm32f10x.h.

#define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080)

Bit 2

Definition at line 3922 of file stm32f10x.h.

#define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100)

Bit 3

Definition at line 3923 of file stm32f10x.h.

#define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200)

Bit 4

Definition at line 3924 of file stm32f10x.h.

#define ADC_SQR2_SQ9 ((uint32_t)0x00007C00)

SQ9[4:0] bits (9th conversion in regular sequence)

Definition at line 3926 of file stm32f10x.h.

#define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400)

Bit 0

Definition at line 3927 of file stm32f10x.h.

#define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800)

Bit 1

Definition at line 3928 of file stm32f10x.h.

#define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000)

Bit 2

Definition at line 3929 of file stm32f10x.h.

#define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000)

Bit 3

Definition at line 3930 of file stm32f10x.h.

#define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000)

Bit 4

Definition at line 3931 of file stm32f10x.h.

#define ADC_SQR3_SQ1 ((uint32_t)0x0000001F)

SQ1[4:0] bits (1st conversion in regular sequence)

Definition at line 3955 of file stm32f10x.h.

#define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001)

Bit 0

Definition at line 3956 of file stm32f10x.h.

#define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002)

Bit 1

Definition at line 3957 of file stm32f10x.h.

#define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004)

Bit 2

Definition at line 3958 of file stm32f10x.h.

#define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008)

Bit 3

Definition at line 3959 of file stm32f10x.h.

#define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010)

Bit 4

Definition at line 3960 of file stm32f10x.h.

#define ADC_SQR3_SQ2 ((uint32_t)0x000003E0)

SQ2[4:0] bits (2nd conversion in regular sequence)

Definition at line 3962 of file stm32f10x.h.

#define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020)

Bit 0

Definition at line 3963 of file stm32f10x.h.

#define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040)

Bit 1

Definition at line 3964 of file stm32f10x.h.

#define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080)

Bit 2

Definition at line 3965 of file stm32f10x.h.

#define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100)

Bit 3

Definition at line 3966 of file stm32f10x.h.

#define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200)

Bit 4

Definition at line 3967 of file stm32f10x.h.

#define ADC_SQR3_SQ3 ((uint32_t)0x00007C00)

SQ3[4:0] bits (3rd conversion in regular sequence)

Definition at line 3969 of file stm32f10x.h.

#define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400)

Bit 0

Definition at line 3970 of file stm32f10x.h.

#define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800)

Bit 1

Definition at line 3971 of file stm32f10x.h.

#define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000)

Bit 2

Definition at line 3972 of file stm32f10x.h.

#define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000)

Bit 3

Definition at line 3973 of file stm32f10x.h.

#define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000)

Bit 4

Definition at line 3974 of file stm32f10x.h.

#define ADC_SQR3_SQ4 ((uint32_t)0x000F8000)

SQ4[4:0] bits (4th conversion in regular sequence)

Definition at line 3976 of file stm32f10x.h.

#define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000)

Bit 0

Definition at line 3977 of file stm32f10x.h.

#define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000)

Bit 1

Definition at line 3978 of file stm32f10x.h.

#define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000)

Bit 2

Definition at line 3979 of file stm32f10x.h.

#define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000)

Bit 3

Definition at line 3980 of file stm32f10x.h.

#define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000)

Bit 4

Definition at line 3981 of file stm32f10x.h.

#define ADC_SQR3_SQ5 ((uint32_t)0x01F00000)

SQ5[4:0] bits (5th conversion in regular sequence)

Definition at line 3983 of file stm32f10x.h.

#define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000)

Bit 0

Definition at line 3984 of file stm32f10x.h.

#define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000)

Bit 1

Definition at line 3985 of file stm32f10x.h.

#define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000)

Bit 2

Definition at line 3986 of file stm32f10x.h.

#define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000)

Bit 3

Definition at line 3987 of file stm32f10x.h.

#define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000)

Bit 4

Definition at line 3988 of file stm32f10x.h.

#define ADC_SQR3_SQ6 ((uint32_t)0x3E000000)

SQ6[4:0] bits (6th conversion in regular sequence)

Definition at line 3990 of file stm32f10x.h.

#define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000)

Bit 0

Definition at line 3991 of file stm32f10x.h.

#define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000)

Bit 1

Definition at line 3992 of file stm32f10x.h.

#define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000)

Bit 2

Definition at line 3993 of file stm32f10x.h.

#define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000)

Bit 3

Definition at line 3994 of file stm32f10x.h.

#define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000)

Bit 4

Definition at line 3995 of file stm32f10x.h.

#define ADC_SR_AWD ((uint8_t)0x01)

Analog watchdog flag

Definition at line 3703 of file stm32f10x.h.

#define ADC_SR_EOC ((uint8_t)0x02)

End of conversion

Definition at line 3704 of file stm32f10x.h.

#define ADC_SR_JEOC ((uint8_t)0x04)

Injected channel end of conversion

Definition at line 3705 of file stm32f10x.h.

#define ADC_SR_JSTRT ((uint8_t)0x08)

Injected channel Start flag

Definition at line 3706 of file stm32f10x.h.

#define ADC_SR_STRT ((uint8_t)0x10)

Regular channel Start flag

Definition at line 3707 of file stm32f10x.h.

#define AFIO_EVCR_EVOE ((uint8_t)0x80)

Event Output Enable

Definition at line 2592 of file stm32f10x.h.

#define AFIO_EVCR_PIN ((uint8_t)0x0F)

PIN[3:0] bits (Pin selection)

Definition at line 2556 of file stm32f10x.h.

#define AFIO_EVCR_PIN_0 ((uint8_t)0x01)

Bit 0

Definition at line 2557 of file stm32f10x.h.

#define AFIO_EVCR_PIN_1 ((uint8_t)0x02)

Bit 1

Definition at line 2558 of file stm32f10x.h.

#define AFIO_EVCR_PIN_2 ((uint8_t)0x04)

Bit 2

Definition at line 2559 of file stm32f10x.h.

#define AFIO_EVCR_PIN_3 ((uint8_t)0x08)

Bit 3 PIN configuration

Definition at line 2560 of file stm32f10x.h.

#define AFIO_EVCR_PIN_PX0 ((uint8_t)0x00)

Pin 0 selected

Definition at line 2563 of file stm32f10x.h.

#define AFIO_EVCR_PIN_PX1 ((uint8_t)0x01)

Pin 1 selected

Definition at line 2564 of file stm32f10x.h.

#define AFIO_EVCR_PIN_PX10 ((uint8_t)0x0A)

Pin 10 selected

Definition at line 2573 of file stm32f10x.h.

#define AFIO_EVCR_PIN_PX11 ((uint8_t)0x0B)

Pin 11 selected

Definition at line 2574 of file stm32f10x.h.

#define AFIO_EVCR_PIN_PX12 ((uint8_t)0x0C)

Pin 12 selected

Definition at line 2575 of file stm32f10x.h.

#define AFIO_EVCR_PIN_PX13 ((uint8_t)0x0D)

Pin 13 selected

Definition at line 2576 of file stm32f10x.h.

#define AFIO_EVCR_PIN_PX14 ((uint8_t)0x0E)

Pin 14 selected

Definition at line 2577 of file stm32f10x.h.

#define AFIO_EVCR_PIN_PX15 ((uint8_t)0x0F)

Pin 15 selected

Definition at line 2578 of file stm32f10x.h.

#define AFIO_EVCR_PIN_PX2 ((uint8_t)0x02)

Pin 2 selected

Definition at line 2565 of file stm32f10x.h.

#define AFIO_EVCR_PIN_PX3 ((uint8_t)0x03)

Pin 3 selected

Definition at line 2566 of file stm32f10x.h.

#define AFIO_EVCR_PIN_PX4 ((uint8_t)0x04)

Pin 4 selected

Definition at line 2567 of file stm32f10x.h.

#define AFIO_EVCR_PIN_PX5 ((uint8_t)0x05)

Pin 5 selected

Definition at line 2568 of file stm32f10x.h.

#define AFIO_EVCR_PIN_PX6 ((uint8_t)0x06)

Pin 6 selected

Definition at line 2569 of file stm32f10x.h.

#define AFIO_EVCR_PIN_PX7 ((uint8_t)0x07)

Pin 7 selected

Definition at line 2570 of file stm32f10x.h.

#define AFIO_EVCR_PIN_PX8 ((uint8_t)0x08)

Pin 8 selected

Definition at line 2571 of file stm32f10x.h.

#define AFIO_EVCR_PIN_PX9 ((uint8_t)0x09)

Pin 9 selected

Definition at line 2572 of file stm32f10x.h.

#define AFIO_EVCR_PORT ((uint8_t)0x70)

PORT[2:0] bits (Port selection)

Definition at line 2580 of file stm32f10x.h.

#define AFIO_EVCR_PORT_0 ((uint8_t)0x10)

Bit 0

Definition at line 2581 of file stm32f10x.h.

#define AFIO_EVCR_PORT_1 ((uint8_t)0x20)

Bit 1

Definition at line 2582 of file stm32f10x.h.

#define AFIO_EVCR_PORT_2 ((uint8_t)0x40)

Bit 2 PORT configuration

Definition at line 2583 of file stm32f10x.h.

#define AFIO_EVCR_PORT_PA ((uint8_t)0x00)

Port A selected

Definition at line 2586 of file stm32f10x.h.

#define AFIO_EVCR_PORT_PB ((uint8_t)0x10)

Port B selected

Definition at line 2587 of file stm32f10x.h.

#define AFIO_EVCR_PORT_PC ((uint8_t)0x20)

Port C selected

Definition at line 2588 of file stm32f10x.h.

#define AFIO_EVCR_PORT_PD ((uint8_t)0x30)

Port D selected

Definition at line 2589 of file stm32f10x.h.

#define AFIO_EVCR_PORT_PE ((uint8_t)0x40)

Port E selected

Definition at line 2590 of file stm32f10x.h.

#define AFIO_EXTICR1_EXTI0 ((uint16_t)0x000F)

EXTI 0 configuration

Definition at line 2687 of file stm32f10x.h.

#define AFIO_EXTICR1_EXTI0_PA ((uint16_t)0x0000)

PA[0] pin

Definition at line 2693 of file stm32f10x.h.

#define AFIO_EXTICR1_EXTI0_PB ((uint16_t)0x0001)

PB[0] pin

Definition at line 2694 of file stm32f10x.h.

#define AFIO_EXTICR1_EXTI0_PC ((uint16_t)0x0002)

PC[0] pin

Definition at line 2695 of file stm32f10x.h.

#define AFIO_EXTICR1_EXTI0_PD ((uint16_t)0x0003)

PD[0] pin

Definition at line 2696 of file stm32f10x.h.

#define AFIO_EXTICR1_EXTI0_PE ((uint16_t)0x0004)

PE[0] pin

Definition at line 2697 of file stm32f10x.h.

#define AFIO_EXTICR1_EXTI0_PF ((uint16_t)0x0005)

PF[0] pin

Definition at line 2698 of file stm32f10x.h.

#define AFIO_EXTICR1_EXTI0_PG ((uint16_t)0x0006)

PG[0] pin EXTI1 configuration

Definition at line 2699 of file stm32f10x.h.

#define AFIO_EXTICR1_EXTI1 ((uint16_t)0x00F0)

EXTI 1 configuration

Definition at line 2688 of file stm32f10x.h.

#define AFIO_EXTICR1_EXTI1_PA ((uint16_t)0x0000)

PA[1] pin

Definition at line 2702 of file stm32f10x.h.

#define AFIO_EXTICR1_EXTI1_PB ((uint16_t)0x0010)

PB[1] pin

Definition at line 2703 of file stm32f10x.h.

#define AFIO_EXTICR1_EXTI1_PC ((uint16_t)0x0020)

PC[1] pin

Definition at line 2704 of file stm32f10x.h.

#define AFIO_EXTICR1_EXTI1_PD ((uint16_t)0x0030)

PD[1] pin

Definition at line 2705 of file stm32f10x.h.

#define AFIO_EXTICR1_EXTI1_PE ((uint16_t)0x0040)

PE[1] pin

Definition at line 2706 of file stm32f10x.h.

#define AFIO_EXTICR1_EXTI1_PF ((uint16_t)0x0050)

PF[1] pin

Definition at line 2707 of file stm32f10x.h.

#define AFIO_EXTICR1_EXTI1_PG ((uint16_t)0x0060)

PG[1] pin EXTI2 configuration

Definition at line 2708 of file stm32f10x.h.

#define AFIO_EXTICR1_EXTI2 ((uint16_t)0x0F00)

EXTI 2 configuration

Definition at line 2689 of file stm32f10x.h.

#define AFIO_EXTICR1_EXTI2_PA ((uint16_t)0x0000)

PA[2] pin

Definition at line 2711 of file stm32f10x.h.

#define AFIO_EXTICR1_EXTI2_PB ((uint16_t)0x0100)

PB[2] pin

Definition at line 2712 of file stm32f10x.h.

#define AFIO_EXTICR1_EXTI2_PC ((uint16_t)0x0200)

PC[2] pin

Definition at line 2713 of file stm32f10x.h.

#define AFIO_EXTICR1_EXTI2_PD ((uint16_t)0x0300)

PD[2] pin

Definition at line 2714 of file stm32f10x.h.

#define AFIO_EXTICR1_EXTI2_PE ((uint16_t)0x0400)

PE[2] pin

Definition at line 2715 of file stm32f10x.h.

#define AFIO_EXTICR1_EXTI2_PF ((uint16_t)0x0500)

PF[2] pin

Definition at line 2716 of file stm32f10x.h.

#define AFIO_EXTICR1_EXTI2_PG ((uint16_t)0x0600)

PG[2] pin EXTI3 configuration

Definition at line 2717 of file stm32f10x.h.

#define AFIO_EXTICR1_EXTI3 ((uint16_t)0xF000)

EXTI 3 configuration EXTI0 configuration

Definition at line 2690 of file stm32f10x.h.

#define AFIO_EXTICR1_EXTI3_PA ((uint16_t)0x0000)

PA[3] pin

Definition at line 2720 of file stm32f10x.h.

#define AFIO_EXTICR1_EXTI3_PB ((uint16_t)0x1000)

PB[3] pin

Definition at line 2721 of file stm32f10x.h.

#define AFIO_EXTICR1_EXTI3_PC ((uint16_t)0x2000)

PC[3] pin

Definition at line 2722 of file stm32f10x.h.

#define AFIO_EXTICR1_EXTI3_PD ((uint16_t)0x3000)

PD[3] pin

Definition at line 2723 of file stm32f10x.h.

#define AFIO_EXTICR1_EXTI3_PE ((uint16_t)0x4000)

PE[3] pin

Definition at line 2724 of file stm32f10x.h.

#define AFIO_EXTICR1_EXTI3_PF ((uint16_t)0x5000)

PF[3] pin

Definition at line 2725 of file stm32f10x.h.

#define AFIO_EXTICR1_EXTI3_PG ((uint16_t)0x6000)

PG[3] pin

Definition at line 2726 of file stm32f10x.h.

#define AFIO_EXTICR2_EXTI4 ((uint16_t)0x000F)

EXTI 4 configuration

Definition at line 2729 of file stm32f10x.h.

#define AFIO_EXTICR2_EXTI4_PA ((uint16_t)0x0000)

PA[4] pin

Definition at line 2735 of file stm32f10x.h.

#define AFIO_EXTICR2_EXTI4_PB ((uint16_t)0x0001)

PB[4] pin

Definition at line 2736 of file stm32f10x.h.

#define AFIO_EXTICR2_EXTI4_PC ((uint16_t)0x0002)

PC[4] pin

Definition at line 2737 of file stm32f10x.h.

#define AFIO_EXTICR2_EXTI4_PD ((uint16_t)0x0003)

PD[4] pin

Definition at line 2738 of file stm32f10x.h.

#define AFIO_EXTICR2_EXTI4_PE ((uint16_t)0x0004)

PE[4] pin

Definition at line 2739 of file stm32f10x.h.

#define AFIO_EXTICR2_EXTI4_PF ((uint16_t)0x0005)

PF[4] pin

Definition at line 2740 of file stm32f10x.h.

#define AFIO_EXTICR2_EXTI4_PG ((uint16_t)0x0006)

PG[4] pin

Definition at line 2741 of file stm32f10x.h.

#define AFIO_EXTICR2_EXTI5 ((uint16_t)0x00F0)

EXTI 5 configuration

Definition at line 2730 of file stm32f10x.h.

#define AFIO_EXTICR2_EXTI5_PA ((uint16_t)0x0000)

PA[5] pin

Definition at line 2744 of file stm32f10x.h.

#define AFIO_EXTICR2_EXTI5_PB ((uint16_t)0x0010)

PB[5] pin

Definition at line 2745 of file stm32f10x.h.

#define AFIO_EXTICR2_EXTI5_PC ((uint16_t)0x0020)

PC[5] pin

Definition at line 2746 of file stm32f10x.h.

#define AFIO_EXTICR2_EXTI5_PD ((uint16_t)0x0030)

PD[5] pin

Definition at line 2747 of file stm32f10x.h.

#define AFIO_EXTICR2_EXTI5_PE ((uint16_t)0x0040)

PE[5] pin

Definition at line 2748 of file stm32f10x.h.

#define AFIO_EXTICR2_EXTI5_PF ((uint16_t)0x0050)

PF[5] pin

Definition at line 2749 of file stm32f10x.h.

#define AFIO_EXTICR2_EXTI5_PG ((uint16_t)0x0060)

PG[5] pin EXTI6 configuration

Definition at line 2750 of file stm32f10x.h.

#define AFIO_EXTICR2_EXTI6 ((uint16_t)0x0F00)

EXTI 6 configuration

Definition at line 2731 of file stm32f10x.h.

#define AFIO_EXTICR2_EXTI6_PA ((uint16_t)0x0000)

PA[6] pin

Definition at line 2753 of file stm32f10x.h.

#define AFIO_EXTICR2_EXTI6_PB ((uint16_t)0x0100)

PB[6] pin

Definition at line 2754 of file stm32f10x.h.

#define AFIO_EXTICR2_EXTI6_PC ((uint16_t)0x0200)

PC[6] pin

Definition at line 2755 of file stm32f10x.h.

#define AFIO_EXTICR2_EXTI6_PD ((uint16_t)0x0300)

PD[6] pin

Definition at line 2756 of file stm32f10x.h.

#define AFIO_EXTICR2_EXTI6_PE ((uint16_t)0x0400)

PE[6] pin

Definition at line 2757 of file stm32f10x.h.

#define AFIO_EXTICR2_EXTI6_PF ((uint16_t)0x0500)

PF[6] pin

Definition at line 2758 of file stm32f10x.h.

#define AFIO_EXTICR2_EXTI6_PG ((uint16_t)0x0600)

PG[6] pin EXTI7 configuration

Definition at line 2759 of file stm32f10x.h.

#define AFIO_EXTICR2_EXTI7 ((uint16_t)0xF000)

EXTI 7 configuration EXTI4 configuration

Definition at line 2732 of file stm32f10x.h.

#define AFIO_EXTICR2_EXTI7_PA ((uint16_t)0x0000)

PA[7] pin

Definition at line 2762 of file stm32f10x.h.

#define AFIO_EXTICR2_EXTI7_PB ((uint16_t)0x1000)

PB[7] pin

Definition at line 2763 of file stm32f10x.h.

#define AFIO_EXTICR2_EXTI7_PC ((uint16_t)0x2000)

PC[7] pin

Definition at line 2764 of file stm32f10x.h.

#define AFIO_EXTICR2_EXTI7_PD ((uint16_t)0x3000)

PD[7] pin

Definition at line 2765 of file stm32f10x.h.

#define AFIO_EXTICR2_EXTI7_PE ((uint16_t)0x4000)

PE[7] pin

Definition at line 2766 of file stm32f10x.h.

#define AFIO_EXTICR2_EXTI7_PF ((uint16_t)0x5000)

PF[7] pin

Definition at line 2767 of file stm32f10x.h.

#define AFIO_EXTICR2_EXTI7_PG ((uint16_t)0x6000)

PG[7] pin

Definition at line 2768 of file stm32f10x.h.

#define AFIO_EXTICR3_EXTI10 ((uint16_t)0x0F00)

EXTI 10 configuration

Definition at line 2773 of file stm32f10x.h.

#define AFIO_EXTICR3_EXTI10_PA ((uint16_t)0x0000)

PA[10] pin

Definition at line 2795 of file stm32f10x.h.

#define AFIO_EXTICR3_EXTI10_PB ((uint16_t)0x0100)

PB[10] pin

Definition at line 2796 of file stm32f10x.h.

#define AFIO_EXTICR3_EXTI10_PC ((uint16_t)0x0200)

PC[10] pin

Definition at line 2797 of file stm32f10x.h.

#define AFIO_EXTICR3_EXTI10_PD ((uint16_t)0x0300)

PD[10] pin

Definition at line 2798 of file stm32f10x.h.

#define AFIO_EXTICR3_EXTI10_PE ((uint16_t)0x0400)

PE[10] pin

Definition at line 2799 of file stm32f10x.h.

#define AFIO_EXTICR3_EXTI10_PF ((uint16_t)0x0500)

PF[10] pin

Definition at line 2800 of file stm32f10x.h.

#define AFIO_EXTICR3_EXTI10_PG ((uint16_t)0x0600)

PG[10] pin EXTI11 configuration

Definition at line 2801 of file stm32f10x.h.

#define AFIO_EXTICR3_EXTI11 ((uint16_t)0xF000)

EXTI 11 configuration EXTI8 configuration

Definition at line 2774 of file stm32f10x.h.

#define AFIO_EXTICR3_EXTI11_PA ((uint16_t)0x0000)

PA[11] pin

Definition at line 2804 of file stm32f10x.h.

#define AFIO_EXTICR3_EXTI11_PB ((uint16_t)0x1000)

PB[11] pin

Definition at line 2805 of file stm32f10x.h.

#define AFIO_EXTICR3_EXTI11_PC ((uint16_t)0x2000)

PC[11] pin

Definition at line 2806 of file stm32f10x.h.

#define AFIO_EXTICR3_EXTI11_PD ((uint16_t)0x3000)

PD[11] pin

Definition at line 2807 of file stm32f10x.h.

#define AFIO_EXTICR3_EXTI11_PE ((uint16_t)0x4000)

PE[11] pin

Definition at line 2808 of file stm32f10x.h.

#define AFIO_EXTICR3_EXTI11_PF ((uint16_t)0x5000)

PF[11] pin

Definition at line 2809 of file stm32f10x.h.

#define AFIO_EXTICR3_EXTI11_PG ((uint16_t)0x6000)

PG[11] pin

Definition at line 2810 of file stm32f10x.h.

#define AFIO_EXTICR3_EXTI8 ((uint16_t)0x000F)

EXTI 8 configuration

Definition at line 2771 of file stm32f10x.h.

#define AFIO_EXTICR3_EXTI8_PA ((uint16_t)0x0000)

PA[8] pin

Definition at line 2777 of file stm32f10x.h.

#define AFIO_EXTICR3_EXTI8_PB ((uint16_t)0x0001)

PB[8] pin

Definition at line 2778 of file stm32f10x.h.

#define AFIO_EXTICR3_EXTI8_PC ((uint16_t)0x0002)

PC[8] pin

Definition at line 2779 of file stm32f10x.h.

#define AFIO_EXTICR3_EXTI8_PD ((uint16_t)0x0003)

PD[8] pin

Definition at line 2780 of file stm32f10x.h.

#define AFIO_EXTICR3_EXTI8_PE ((uint16_t)0x0004)

PE[8] pin

Definition at line 2781 of file stm32f10x.h.

#define AFIO_EXTICR3_EXTI8_PF ((uint16_t)0x0005)

PF[8] pin

Definition at line 2782 of file stm32f10x.h.

#define AFIO_EXTICR3_EXTI8_PG ((uint16_t)0x0006)

PG[8] pin EXTI9 configuration

Definition at line 2783 of file stm32f10x.h.

#define AFIO_EXTICR3_EXTI9 ((uint16_t)0x00F0)

EXTI 9 configuration

Definition at line 2772 of file stm32f10x.h.

#define AFIO_EXTICR3_EXTI9_PA ((uint16_t)0x0000)

PA[9] pin

Definition at line 2786 of file stm32f10x.h.

#define AFIO_EXTICR3_EXTI9_PB ((uint16_t)0x0010)

PB[9] pin

Definition at line 2787 of file stm32f10x.h.

#define AFIO_EXTICR3_EXTI9_PC ((uint16_t)0x0020)

PC[9] pin

Definition at line 2788 of file stm32f10x.h.

#define AFIO_EXTICR3_EXTI9_PD ((uint16_t)0x0030)

PD[9] pin

Definition at line 2789 of file stm32f10x.h.

#define AFIO_EXTICR3_EXTI9_PE ((uint16_t)0x0040)

PE[9] pin

Definition at line 2790 of file stm32f10x.h.

#define AFIO_EXTICR3_EXTI9_PF ((uint16_t)0x0050)

PF[9] pin

Definition at line 2791 of file stm32f10x.h.

#define AFIO_EXTICR3_EXTI9_PG ((uint16_t)0x0060)

PG[9] pin EXTI10 configuration

Definition at line 2792 of file stm32f10x.h.

#define AFIO_EXTICR4_EXTI12 ((uint16_t)0x000F)

EXTI 12 configuration

Definition at line 2813 of file stm32f10x.h.

#define AFIO_EXTICR4_EXTI12_PA ((uint16_t)0x0000)

PA[12] pin

Definition at line 2819 of file stm32f10x.h.

#define AFIO_EXTICR4_EXTI12_PB ((uint16_t)0x0001)

PB[12] pin

Definition at line 2820 of file stm32f10x.h.

#define AFIO_EXTICR4_EXTI12_PC ((uint16_t)0x0002)

PC[12] pin

Definition at line 2821 of file stm32f10x.h.

#define AFIO_EXTICR4_EXTI12_PD ((uint16_t)0x0003)

PD[12] pin

Definition at line 2822 of file stm32f10x.h.

#define AFIO_EXTICR4_EXTI12_PE ((uint16_t)0x0004)

PE[12] pin

Definition at line 2823 of file stm32f10x.h.

#define AFIO_EXTICR4_EXTI12_PF ((uint16_t)0x0005)

PF[12] pin

Definition at line 2824 of file stm32f10x.h.

#define AFIO_EXTICR4_EXTI12_PG ((uint16_t)0x0006)

PG[12] pin

Definition at line 2825 of file stm32f10x.h.

#define AFIO_EXTICR4_EXTI13 ((uint16_t)0x00F0)

EXTI 13 configuration

Definition at line 2814 of file stm32f10x.h.

#define AFIO_EXTICR4_EXTI13_PA ((uint16_t)0x0000)

PA[13] pin

Definition at line 2828 of file stm32f10x.h.

#define AFIO_EXTICR4_EXTI13_PB ((uint16_t)0x0010)

PB[13] pin

Definition at line 2829 of file stm32f10x.h.

#define AFIO_EXTICR4_EXTI13_PC ((uint16_t)0x0020)

PC[13] pin

Definition at line 2830 of file stm32f10x.h.

#define AFIO_EXTICR4_EXTI13_PD ((uint16_t)0x0030)

PD[13] pin

Definition at line 2831 of file stm32f10x.h.

#define AFIO_EXTICR4_EXTI13_PE ((uint16_t)0x0040)

PE[13] pin

Definition at line 2832 of file stm32f10x.h.

#define AFIO_EXTICR4_EXTI13_PF ((uint16_t)0x0050)

PF[13] pin

Definition at line 2833 of file stm32f10x.h.

#define AFIO_EXTICR4_EXTI13_PG ((uint16_t)0x0060)

PG[13] pin EXTI14 configuration

Definition at line 2834 of file stm32f10x.h.

#define AFIO_EXTICR4_EXTI14 ((uint16_t)0x0F00)

EXTI 14 configuration

Definition at line 2815 of file stm32f10x.h.

#define AFIO_EXTICR4_EXTI14_PA ((uint16_t)0x0000)

PA[14] pin

Definition at line 2837 of file stm32f10x.h.

#define AFIO_EXTICR4_EXTI14_PB ((uint16_t)0x0100)

PB[14] pin

Definition at line 2838 of file stm32f10x.h.

#define AFIO_EXTICR4_EXTI14_PC ((uint16_t)0x0200)

PC[14] pin

Definition at line 2839 of file stm32f10x.h.

#define AFIO_EXTICR4_EXTI14_PD ((uint16_t)0x0300)

PD[14] pin

Definition at line 2840 of file stm32f10x.h.

#define AFIO_EXTICR4_EXTI14_PE ((uint16_t)0x0400)

PE[14] pin

Definition at line 2841 of file stm32f10x.h.

#define AFIO_EXTICR4_EXTI14_PF ((uint16_t)0x0500)

PF[14] pin

Definition at line 2842 of file stm32f10x.h.

#define AFIO_EXTICR4_EXTI14_PG ((uint16_t)0x0600)

PG[14] pin EXTI15 configuration

Definition at line 2843 of file stm32f10x.h.

#define AFIO_EXTICR4_EXTI15 ((uint16_t)0xF000)

EXTI 15 configuration

Definition at line 2816 of file stm32f10x.h.

#define AFIO_EXTICR4_EXTI15_PA ((uint16_t)0x0000)

PA[15] pin

Definition at line 2846 of file stm32f10x.h.

#define AFIO_EXTICR4_EXTI15_PB ((uint16_t)0x1000)

PB[15] pin

Definition at line 2847 of file stm32f10x.h.

#define AFIO_EXTICR4_EXTI15_PC ((uint16_t)0x2000)

PC[15] pin

Definition at line 2848 of file stm32f10x.h.

#define AFIO_EXTICR4_EXTI15_PD ((uint16_t)0x3000)

PD[15] pin

Definition at line 2849 of file stm32f10x.h.

#define AFIO_EXTICR4_EXTI15_PE ((uint16_t)0x4000)

PE[15] pin

Definition at line 2850 of file stm32f10x.h.

#define AFIO_EXTICR4_EXTI15_PF ((uint16_t)0x5000)

PF[15] pin

Definition at line 2851 of file stm32f10x.h.

#define AFIO_EXTICR4_EXTI15_PG ((uint16_t)0x6000)

PG[15] pin

Definition at line 2852 of file stm32f10x.h.

#define AFIO_MAPR_ADC1_ETRGINJ_REMAP ((uint32_t)0x00020000)

ADC 1 External Trigger Injected Conversion remapping

Definition at line 2650 of file stm32f10x.h.

#define AFIO_MAPR_ADC1_ETRGREG_REMAP ((uint32_t)0x00040000)

ADC 1 External Trigger Regular Conversion remapping

Definition at line 2651 of file stm32f10x.h.

#define AFIO_MAPR_ADC2_ETRGINJ_REMAP ((uint32_t)0x00080000)

ADC 2 External Trigger Injected Conversion remapping

Definition at line 2652 of file stm32f10x.h.

#define AFIO_MAPR_ADC2_ETRGREG_REMAP ((uint32_t)0x00100000)

ADC 2 External Trigger Regular Conversion remapping SWJ_CFG configuration

Definition at line 2653 of file stm32f10x.h.

#define AFIO_MAPR_CAN_REMAP ((uint32_t)0x00006000)

CAN_REMAP[1:0] bits (CAN Alternate function remapping)

Definition at line 2639 of file stm32f10x.h.

#define AFIO_MAPR_CAN_REMAP_0 ((uint32_t)0x00002000)

Bit 0

Definition at line 2640 of file stm32f10x.h.

#define AFIO_MAPR_CAN_REMAP_1 ((uint32_t)0x00004000)

Bit 1 CAN_REMAP configuration

Definition at line 2641 of file stm32f10x.h.

#define AFIO_MAPR_CAN_REMAP_REMAP1 ((uint32_t)0x00000000)

CANRX mapped to PA11, CANTX mapped to PA12

Definition at line 2644 of file stm32f10x.h.

#define AFIO_MAPR_CAN_REMAP_REMAP2 ((uint32_t)0x00004000)

CANRX mapped to PB8, CANTX mapped to PB9

Definition at line 2645 of file stm32f10x.h.

#define AFIO_MAPR_CAN_REMAP_REMAP3 ((uint32_t)0x00006000)

CANRX mapped to PD0, CANTX mapped to PD1

Definition at line 2646 of file stm32f10x.h.

#define AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002)

I2C1 remapping

Definition at line 2596 of file stm32f10x.h.

#define AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000)

Port D0/Port D1 mapping on OSC_IN/OSC_OUT

Definition at line 2648 of file stm32f10x.h.

#define AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001)

SPI1 remapping

Definition at line 2595 of file stm32f10x.h.

#define AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000)

SWJ_CFG[2:0] bits (Serial Wire JTAG configuration)

Definition at line 2656 of file stm32f10x.h.

#define AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000)

Bit 0

Definition at line 2657 of file stm32f10x.h.

#define AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000)

Bit 1

Definition at line 2658 of file stm32f10x.h.

#define AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000)

Bit 2

Definition at line 2659 of file stm32f10x.h.

#define AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000)

JTAG-DP Disabled and SW-DP Disabled

Definition at line 2664 of file stm32f10x.h.

#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000)

JTAG-DP Disabled and SW-DP Enabled

Definition at line 2663 of file stm32f10x.h.

#define AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000)

Full SWJ (JTAG-DP + SW-DP) but without JNTRST

Definition at line 2662 of file stm32f10x.h.

#define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000)

Full SWJ (JTAG-DP + SW-DP) : Reset State

Definition at line 2661 of file stm32f10x.h.

#define AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0)

TIM1_REMAP[1:0] bits (TIM1 remapping)

Definition at line 2609 of file stm32f10x.h.

#define AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040)

Bit 0

Definition at line 2610 of file stm32f10x.h.

#define AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080)

Bit 1 TIM1_REMAP configuration

Definition at line 2611 of file stm32f10x.h.

#define AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0)

Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12)

Definition at line 2616 of file stm32f10x.h.

#define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000)

No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15)

Definition at line 2614 of file stm32f10x.h.

#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040)

Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1)

Definition at line 2615 of file stm32f10x.h.

#define AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300)

TIM2_REMAP[1:0] bits (TIM2 remapping)

Definition at line 2618 of file stm32f10x.h.

#define AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100)

Bit 0

Definition at line 2619 of file stm32f10x.h.

#define AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200)

Bit 1 TIM2_REMAP configuration

Definition at line 2620 of file stm32f10x.h.

#define AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300)

Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11)

Definition at line 2626 of file stm32f10x.h.

#define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000)

No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3)

Definition at line 2623 of file stm32f10x.h.

#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100)

Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3)

Definition at line 2624 of file stm32f10x.h.

#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200)

Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11)

Definition at line 2625 of file stm32f10x.h.

#define AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00)

TIM3_REMAP[1:0] bits (TIM3 remapping)

Definition at line 2628 of file stm32f10x.h.

#define AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400)

Bit 0

Definition at line 2629 of file stm32f10x.h.

#define AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800)

Bit 1 TIM3_REMAP configuration

Definition at line 2630 of file stm32f10x.h.

#define AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00)

Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9)

Definition at line 2635 of file stm32f10x.h.

#define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000)

No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1)

Definition at line 2633 of file stm32f10x.h.

#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800)

Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1)

Definition at line 2634 of file stm32f10x.h.

#define AFIO_MAPR_TIM4_REMAP ((uint32_t)0x00001000)

TIM4_REMAP bit (TIM4 remapping)

Definition at line 2637 of file stm32f10x.h.

#define AFIO_MAPR_TIM5CH4_IREMAP ((uint32_t)0x00010000)

TIM5 Channel4 Internal Remap

Definition at line 2649 of file stm32f10x.h.

#define AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004)

USART1 remapping

Definition at line 2597 of file stm32f10x.h.

#define AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008)

USART2 remapping

Definition at line 2598 of file stm32f10x.h.

#define AFIO_MAPR_USART3_REMAP ((uint32_t)0x00000030)

USART3_REMAP[1:0] bits (USART3 remapping)

Definition at line 2600 of file stm32f10x.h.

#define AFIO_MAPR_USART3_REMAP_0 ((uint32_t)0x00000010)

Bit 0

Definition at line 2601 of file stm32f10x.h.

#define AFIO_MAPR_USART3_REMAP_1 ((uint32_t)0x00000020)

Bit 1

Definition at line 2602 of file stm32f10x.h.

#define AFIO_MAPR_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030)

Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12)

Definition at line 2607 of file stm32f10x.h.

#define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000)

No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14)

Definition at line 2605 of file stm32f10x.h.

#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010)

Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14)

Definition at line 2606 of file stm32f10x.h.

#define BKP_CR_TPAL ((uint8_t)0x02)

TAMPER pin active level

Definition at line 1665 of file stm32f10x.h.

#define BKP_CR_TPE ((uint8_t)0x01)

TAMPER pin enable

Definition at line 1664 of file stm32f10x.h.

#define BKP_CSR_CTE ((uint16_t)0x0001)

Clear Tamper event

Definition at line 1668 of file stm32f10x.h.

Referenced by BKP_ClearFlag().

#define BKP_CSR_CTI ((uint16_t)0x0002)

Clear Tamper Interrupt

Definition at line 1669 of file stm32f10x.h.

Referenced by BKP_ClearITPendingBit().

#define BKP_CSR_TEF ((uint16_t)0x0100)

Tamper Event Flag

Definition at line 1671 of file stm32f10x.h.

#define BKP_CSR_TIF ((uint16_t)0x0200)

Tamper Interrupt Flag

Definition at line 1672 of file stm32f10x.h.

#define BKP_CSR_TPIE ((uint16_t)0x0004)

TAMPER Pin interrupt enable

Definition at line 1670 of file stm32f10x.h.

#define BKP_DR10_D ((uint16_t)0xFFFF)

Backup data

Definition at line 1559 of file stm32f10x.h.

#define BKP_DR11_D ((uint16_t)0xFFFF)

Backup data

Definition at line 1562 of file stm32f10x.h.

#define BKP_DR12_D ((uint16_t)0xFFFF)

Backup data

Definition at line 1565 of file stm32f10x.h.

#define BKP_DR13_D ((uint16_t)0xFFFF)

Backup data

Definition at line 1568 of file stm32f10x.h.

#define BKP_DR14_D ((uint16_t)0xFFFF)

Backup data

Definition at line 1571 of file stm32f10x.h.

#define BKP_DR15_D ((uint16_t)0xFFFF)

Backup data

Definition at line 1574 of file stm32f10x.h.

#define BKP_DR16_D ((uint16_t)0xFFFF)

Backup data

Definition at line 1577 of file stm32f10x.h.

#define BKP_DR17_D ((uint16_t)0xFFFF)

Backup data

Definition at line 1580 of file stm32f10x.h.

#define BKP_DR18_D ((uint16_t)0xFFFF)

Backup data

Definition at line 1583 of file stm32f10x.h.

#define BKP_DR19_D ((uint16_t)0xFFFF)

Backup data

Definition at line 1586 of file stm32f10x.h.

#define BKP_DR1_D ((uint16_t)0xFFFF)

Backup data

Definition at line 1532 of file stm32f10x.h.

#define BKP_DR20_D ((uint16_t)0xFFFF)

Backup data

Definition at line 1589 of file stm32f10x.h.

#define BKP_DR21_D ((uint16_t)0xFFFF)

Backup data

Definition at line 1592 of file stm32f10x.h.

#define BKP_DR22_D ((uint16_t)0xFFFF)

Backup data

Definition at line 1595 of file stm32f10x.h.

#define BKP_DR23_D ((uint16_t)0xFFFF)

Backup data

Definition at line 1598 of file stm32f10x.h.

#define BKP_DR24_D ((uint16_t)0xFFFF)

Backup data

Definition at line 1601 of file stm32f10x.h.

#define BKP_DR25_D ((uint16_t)0xFFFF)

Backup data

Definition at line 1604 of file stm32f10x.h.

#define BKP_DR26_D ((uint16_t)0xFFFF)

Backup data

Definition at line 1607 of file stm32f10x.h.

#define BKP_DR27_D ((uint16_t)0xFFFF)

Backup data

Definition at line 1610 of file stm32f10x.h.

#define BKP_DR28_D ((uint16_t)0xFFFF)

Backup data

Definition at line 1613 of file stm32f10x.h.

#define BKP_DR29_D ((uint16_t)0xFFFF)

Backup data

Definition at line 1616 of file stm32f10x.h.

#define BKP_DR2_D ((uint16_t)0xFFFF)

Backup data

Definition at line 1535 of file stm32f10x.h.

#define BKP_DR30_D ((uint16_t)0xFFFF)

Backup data

Definition at line 1619 of file stm32f10x.h.

#define BKP_DR31_D ((uint16_t)0xFFFF)

Backup data

Definition at line 1622 of file stm32f10x.h.

#define BKP_DR32_D ((uint16_t)0xFFFF)

Backup data

Definition at line 1625 of file stm32f10x.h.

#define BKP_DR33_D ((uint16_t)0xFFFF)

Backup data

Definition at line 1628 of file stm32f10x.h.

#define BKP_DR34_D ((uint16_t)0xFFFF)

Backup data

Definition at line 1631 of file stm32f10x.h.

#define BKP_DR35_D ((uint16_t)0xFFFF)

Backup data

Definition at line 1634 of file stm32f10x.h.

#define BKP_DR36_D ((uint16_t)0xFFFF)

Backup data

Definition at line 1637 of file stm32f10x.h.

#define BKP_DR37_D ((uint16_t)0xFFFF)

Backup data

Definition at line 1640 of file stm32f10x.h.

#define BKP_DR38_D ((uint16_t)0xFFFF)

Backup data

Definition at line 1643 of file stm32f10x.h.

#define BKP_DR39_D ((uint16_t)0xFFFF)

Backup data

Definition at line 1646 of file stm32f10x.h.

#define BKP_DR3_D ((uint16_t)0xFFFF)

Backup data

Definition at line 1538 of file stm32f10x.h.

#define BKP_DR40_D ((uint16_t)0xFFFF)

Backup data

Definition at line 1649 of file stm32f10x.h.

#define BKP_DR41_D ((uint16_t)0xFFFF)

Backup data

Definition at line 1652 of file stm32f10x.h.

#define BKP_DR42_D ((uint16_t)0xFFFF)

Backup data

Definition at line 1655 of file stm32f10x.h.

#define BKP_DR4_D ((uint16_t)0xFFFF)

Backup data

Definition at line 1541 of file stm32f10x.h.

#define BKP_DR5_D ((uint16_t)0xFFFF)

Backup data

Definition at line 1544 of file stm32f10x.h.

#define BKP_DR6_D ((uint16_t)0xFFFF)

Backup data

Definition at line 1547 of file stm32f10x.h.

#define BKP_DR7_D ((uint16_t)0xFFFF)

Backup data

Definition at line 1550 of file stm32f10x.h.

#define BKP_DR8_D ((uint16_t)0xFFFF)

Backup data

Definition at line 1553 of file stm32f10x.h.

#define BKP_DR9_D ((uint16_t)0xFFFF)

Backup data

Definition at line 1556 of file stm32f10x.h.

#define BKP_RTCCR_ASOE ((uint16_t)0x0100)

Alarm or Second Output Enable

Definition at line 1660 of file stm32f10x.h.

#define BKP_RTCCR_ASOS ((uint16_t)0x0200)

Alarm or Second Output Selection

Definition at line 1661 of file stm32f10x.h.

#define BKP_RTCCR_CAL ((uint16_t)0x007F)

Calibration value

Definition at line 1658 of file stm32f10x.h.

#define BKP_RTCCR_CCO ((uint16_t)0x0080)

Calibration Clock Output

Definition at line 1659 of file stm32f10x.h.

#define CAN_BTR_BRP ((uint32_t)0x000003FF)

Baud Rate Prescaler

Definition at line 6310 of file stm32f10x.h.

#define CAN_BTR_LBKM ((uint32_t)0x40000000)

Loop Back Mode (Debug)

Definition at line 6314 of file stm32f10x.h.

#define CAN_BTR_SILM ((uint32_t)0x80000000)

Silent Mode Mailbox registers

Definition at line 6315 of file stm32f10x.h.

#define CAN_BTR_SJW ((uint32_t)0x03000000)

Resynchronization Jump Width

Definition at line 6313 of file stm32f10x.h.

#define CAN_BTR_TS1 ((uint32_t)0x000F0000)

Time Segment 1

Definition at line 6311 of file stm32f10x.h.

#define CAN_BTR_TS2 ((uint32_t)0x00700000)

Time Segment 2

Definition at line 6312 of file stm32f10x.h.

#define CAN_ESR_BOFF ((uint32_t)0x00000004)

Bus-Off Flag

Definition at line 6299 of file stm32f10x.h.

Referenced by CAN_GetITStatus().

#define CAN_ESR_EPVF ((uint32_t)0x00000002)

Error Passive Flag

Definition at line 6298 of file stm32f10x.h.

Referenced by CAN_GetITStatus().

#define CAN_ESR_EWGF ((uint32_t)0x00000001)

Error Warning Flag

Definition at line 6297 of file stm32f10x.h.

Referenced by CAN_GetITStatus().

#define CAN_ESR_LEC ((uint32_t)0x00000070)

LEC[2:0] bits (Last Error Code)

Definition at line 6301 of file stm32f10x.h.

Referenced by CAN_GetITStatus(), and CAN_GetLastErrorCode().

#define CAN_ESR_LEC_0 ((uint32_t)0x00000010)

Bit 0

Definition at line 6302 of file stm32f10x.h.

#define CAN_ESR_LEC_1 ((uint32_t)0x00000020)

Bit 1

Definition at line 6303 of file stm32f10x.h.

#define CAN_ESR_LEC_2 ((uint32_t)0x00000040)

Bit 2

Definition at line 6304 of file stm32f10x.h.

#define CAN_ESR_REC ((uint32_t)0xFF000000)

Receive Error Counter

Definition at line 6307 of file stm32f10x.h.

Referenced by CAN_GetReceiveErrorCounter().

#define CAN_ESR_TEC ((uint32_t)0x00FF0000)

Least significant byte of the 9-bit Transmit Error Counter

Definition at line 6306 of file stm32f10x.h.

Referenced by CAN_GetLSBTransmitErrorCounter().

#define CAN_F0R1_FB0 ((uint32_t)0x00000001)

Filter bit 0

Definition at line 6509 of file stm32f10x.h.

#define CAN_F0R1_FB1 ((uint32_t)0x00000002)

Filter bit 1

Definition at line 6510 of file stm32f10x.h.

#define CAN_F0R1_FB10 ((uint32_t)0x00000400)

Filter bit 10

Definition at line 6519 of file stm32f10x.h.

#define CAN_F0R1_FB11 ((uint32_t)0x00000800)

Filter bit 11

Definition at line 6520 of file stm32f10x.h.

#define CAN_F0R1_FB12 ((uint32_t)0x00001000)

Filter bit 12

Definition at line 6521 of file stm32f10x.h.

#define CAN_F0R1_FB13 ((uint32_t)0x00002000)

Filter bit 13

Definition at line 6522 of file stm32f10x.h.

#define CAN_F0R1_FB14 ((uint32_t)0x00004000)

Filter bit 14

Definition at line 6523 of file stm32f10x.h.

#define CAN_F0R1_FB15 ((uint32_t)0x00008000)

Filter bit 15

Definition at line 6524 of file stm32f10x.h.

#define CAN_F0R1_FB16 ((uint32_t)0x00010000)

Filter bit 16

Definition at line 6525 of file stm32f10x.h.

#define CAN_F0R1_FB17 ((uint32_t)0x00020000)

Filter bit 17

Definition at line 6526 of file stm32f10x.h.

#define CAN_F0R1_FB18 ((uint32_t)0x00040000)

Filter bit 18

Definition at line 6527 of file stm32f10x.h.

#define CAN_F0R1_FB19 ((uint32_t)0x00080000)

Filter bit 19

Definition at line 6528 of file stm32f10x.h.

#define CAN_F0R1_FB2 ((uint32_t)0x00000004)

Filter bit 2

Definition at line 6511 of file stm32f10x.h.

#define CAN_F0R1_FB20 ((uint32_t)0x00100000)

Filter bit 20

Definition at line 6529 of file stm32f10x.h.

#define CAN_F0R1_FB21 ((uint32_t)0x00200000)

Filter bit 21

Definition at line 6530 of file stm32f10x.h.

#define CAN_F0R1_FB22 ((uint32_t)0x00400000)

Filter bit 22

Definition at line 6531 of file stm32f10x.h.

#define CAN_F0R1_FB23 ((uint32_t)0x00800000)

Filter bit 23

Definition at line 6532 of file stm32f10x.h.

#define CAN_F0R1_FB24 ((uint32_t)0x01000000)

Filter bit 24

Definition at line 6533 of file stm32f10x.h.

#define CAN_F0R1_FB25 ((uint32_t)0x02000000)

Filter bit 25

Definition at line 6534 of file stm32f10x.h.

#define CAN_F0R1_FB26 ((uint32_t)0x04000000)

Filter bit 26

Definition at line 6535 of file stm32f10x.h.

#define CAN_F0R1_FB27 ((uint32_t)0x08000000)

Filter bit 27

Definition at line 6536 of file stm32f10x.h.

#define CAN_F0R1_FB28 ((uint32_t)0x10000000)

Filter bit 28

Definition at line 6537 of file stm32f10x.h.

#define CAN_F0R1_FB29 ((uint32_t)0x20000000)

Filter bit 29

Definition at line 6538 of file stm32f10x.h.

#define CAN_F0R1_FB3 ((uint32_t)0x00000008)

Filter bit 3

Definition at line 6512 of file stm32f10x.h.

#define CAN_F0R1_FB30 ((uint32_t)0x40000000)

Filter bit 30

Definition at line 6539 of file stm32f10x.h.

#define CAN_F0R1_FB31 ((uint32_t)0x80000000)

Filter bit 31

Definition at line 6540 of file stm32f10x.h.

#define CAN_F0R1_FB4 ((uint32_t)0x00000010)

Filter bit 4

Definition at line 6513 of file stm32f10x.h.

#define CAN_F0R1_FB5 ((uint32_t)0x00000020)

Filter bit 5

Definition at line 6514 of file stm32f10x.h.

#define CAN_F0R1_FB6 ((uint32_t)0x00000040)

Filter bit 6

Definition at line 6515 of file stm32f10x.h.

#define CAN_F0R1_FB7 ((uint32_t)0x00000080)

Filter bit 7

Definition at line 6516 of file stm32f10x.h.

#define CAN_F0R1_FB8 ((uint32_t)0x00000100)

Filter bit 8

Definition at line 6517 of file stm32f10x.h.

#define CAN_F0R1_FB9 ((uint32_t)0x00000200)

Filter bit 9

Definition at line 6518 of file stm32f10x.h.

#define CAN_F0R2_FB0 ((uint32_t)0x00000001)

Filter bit 0

Definition at line 6985 of file stm32f10x.h.

#define CAN_F0R2_FB1 ((uint32_t)0x00000002)

Filter bit 1

Definition at line 6986 of file stm32f10x.h.

#define CAN_F0R2_FB10 ((uint32_t)0x00000400)

Filter bit 10

Definition at line 6995 of file stm32f10x.h.

#define CAN_F0R2_FB11 ((uint32_t)0x00000800)

Filter bit 11

Definition at line 6996 of file stm32f10x.h.

#define CAN_F0R2_FB12 ((uint32_t)0x00001000)

Filter bit 12

Definition at line 6997 of file stm32f10x.h.

#define CAN_F0R2_FB13 ((uint32_t)0x00002000)

Filter bit 13

Definition at line 6998 of file stm32f10x.h.

#define CAN_F0R2_FB14 ((uint32_t)0x00004000)

Filter bit 14

Definition at line 6999 of file stm32f10x.h.

#define CAN_F0R2_FB15 ((uint32_t)0x00008000)

Filter bit 15

Definition at line 7000 of file stm32f10x.h.

#define CAN_F0R2_FB16 ((uint32_t)0x00010000)

Filter bit 16

Definition at line 7001 of file stm32f10x.h.

#define CAN_F0R2_FB17 ((uint32_t)0x00020000)

Filter bit 17

Definition at line 7002 of file stm32f10x.h.

#define CAN_F0R2_FB18 ((uint32_t)0x00040000)

Filter bit 18

Definition at line 7003 of file stm32f10x.h.

#define CAN_F0R2_FB19 ((uint32_t)0x00080000)

Filter bit 19

Definition at line 7004 of file stm32f10x.h.

#define CAN_F0R2_FB2 ((uint32_t)0x00000004)

Filter bit 2

Definition at line 6987 of file stm32f10x.h.

#define CAN_F0R2_FB20 ((uint32_t)0x00100000)

Filter bit 20

Definition at line 7005 of file stm32f10x.h.

#define CAN_F0R2_FB21 ((uint32_t)0x00200000)

Filter bit 21

Definition at line 7006 of file stm32f10x.h.

#define CAN_F0R2_FB22 ((uint32_t)0x00400000)

Filter bit 22

Definition at line 7007 of file stm32f10x.h.

#define CAN_F0R2_FB23 ((uint32_t)0x00800000)

Filter bit 23

Definition at line 7008 of file stm32f10x.h.

#define CAN_F0R2_FB24 ((uint32_t)0x01000000)

Filter bit 24

Definition at line 7009 of file stm32f10x.h.

#define CAN_F0R2_FB25 ((uint32_t)0x02000000)

Filter bit 25

Definition at line 7010 of file stm32f10x.h.

#define CAN_F0R2_FB26 ((uint32_t)0x04000000)

Filter bit 26

Definition at line 7011 of file stm32f10x.h.

#define CAN_F0R2_FB27 ((uint32_t)0x08000000)

Filter bit 27

Definition at line 7012 of file stm32f10x.h.

#define CAN_F0R2_FB28 ((uint32_t)0x10000000)

Filter bit 28

Definition at line 7013 of file stm32f10x.h.

#define CAN_F0R2_FB29 ((uint32_t)0x20000000)

Filter bit 29

Definition at line 7014 of file stm32f10x.h.

#define CAN_F0R2_FB3 ((uint32_t)0x00000008)

Filter bit 3

Definition at line 6988 of file stm32f10x.h.

#define CAN_F0R2_FB30 ((uint32_t)0x40000000)

Filter bit 30

Definition at line 7015 of file stm32f10x.h.

#define CAN_F0R2_FB31 ((uint32_t)0x80000000)

Filter bit 31

Definition at line 7016 of file stm32f10x.h.

#define CAN_F0R2_FB4 ((uint32_t)0x00000010)

Filter bit 4

Definition at line 6989 of file stm32f10x.h.

#define CAN_F0R2_FB5 ((uint32_t)0x00000020)

Filter bit 5

Definition at line 6990 of file stm32f10x.h.

#define CAN_F0R2_FB6 ((uint32_t)0x00000040)

Filter bit 6

Definition at line 6991 of file stm32f10x.h.

#define CAN_F0R2_FB7 ((uint32_t)0x00000080)

Filter bit 7

Definition at line 6992 of file stm32f10x.h.

#define CAN_F0R2_FB8 ((uint32_t)0x00000100)

Filter bit 8

Definition at line 6993 of file stm32f10x.h.

#define CAN_F0R2_FB9 ((uint32_t)0x00000200)

Filter bit 9

Definition at line 6994 of file stm32f10x.h.

#define CAN_F10R1_FB0 ((uint32_t)0x00000001)

Filter bit 0

Definition at line 6849 of file stm32f10x.h.

#define CAN_F10R1_FB1 ((uint32_t)0x00000002)

Filter bit 1

Definition at line 6850 of file stm32f10x.h.

#define CAN_F10R1_FB10 ((uint32_t)0x00000400)

Filter bit 10

Definition at line 6859 of file stm32f10x.h.

#define CAN_F10R1_FB11 ((uint32_t)0x00000800)

Filter bit 11

Definition at line 6860 of file stm32f10x.h.

#define CAN_F10R1_FB12 ((uint32_t)0x00001000)

Filter bit 12

Definition at line 6861 of file stm32f10x.h.

#define CAN_F10R1_FB13 ((uint32_t)0x00002000)

Filter bit 13

Definition at line 6862 of file stm32f10x.h.

#define CAN_F10R1_FB14 ((uint32_t)0x00004000)

Filter bit 14

Definition at line 6863 of file stm32f10x.h.

#define CAN_F10R1_FB15 ((uint32_t)0x00008000)

Filter bit 15

Definition at line 6864 of file stm32f10x.h.

#define CAN_F10R1_FB16 ((uint32_t)0x00010000)

Filter bit 16

Definition at line 6865 of file stm32f10x.h.

#define CAN_F10R1_FB17 ((uint32_t)0x00020000)

Filter bit 17

Definition at line 6866 of file stm32f10x.h.

#define CAN_F10R1_FB18 ((uint32_t)0x00040000)

Filter bit 18

Definition at line 6867 of file stm32f10x.h.

#define CAN_F10R1_FB19 ((uint32_t)0x00080000)

Filter bit 19

Definition at line 6868 of file stm32f10x.h.

#define CAN_F10R1_FB2 ((uint32_t)0x00000004)

Filter bit 2

Definition at line 6851 of file stm32f10x.h.

#define CAN_F10R1_FB20 ((uint32_t)0x00100000)

Filter bit 20

Definition at line 6869 of file stm32f10x.h.

#define CAN_F10R1_FB21 ((uint32_t)0x00200000)

Filter bit 21

Definition at line 6870 of file stm32f10x.h.

#define CAN_F10R1_FB22 ((uint32_t)0x00400000)

Filter bit 22

Definition at line 6871 of file stm32f10x.h.

#define CAN_F10R1_FB23 ((uint32_t)0x00800000)

Filter bit 23

Definition at line 6872 of file stm32f10x.h.

#define CAN_F10R1_FB24 ((uint32_t)0x01000000)

Filter bit 24

Definition at line 6873 of file stm32f10x.h.

#define CAN_F10R1_FB25 ((uint32_t)0x02000000)

Filter bit 25

Definition at line 6874 of file stm32f10x.h.

#define CAN_F10R1_FB26 ((uint32_t)0x04000000)

Filter bit 26

Definition at line 6875 of file stm32f10x.h.

#define CAN_F10R1_FB27 ((uint32_t)0x08000000)

Filter bit 27

Definition at line 6876 of file stm32f10x.h.

#define CAN_F10R1_FB28 ((uint32_t)0x10000000)

Filter bit 28

Definition at line 6877 of file stm32f10x.h.

#define CAN_F10R1_FB29 ((uint32_t)0x20000000)

Filter bit 29

Definition at line 6878 of file stm32f10x.h.

#define CAN_F10R1_FB3 ((uint32_t)0x00000008)

Filter bit 3

Definition at line 6852 of file stm32f10x.h.

#define CAN_F10R1_FB30 ((uint32_t)0x40000000)

Filter bit 30

Definition at line 6879 of file stm32f10x.h.

#define CAN_F10R1_FB31 ((uint32_t)0x80000000)

Filter bit 31

Definition at line 6880 of file stm32f10x.h.

#define CAN_F10R1_FB4 ((uint32_t)0x00000010)

Filter bit 4

Definition at line 6853 of file stm32f10x.h.

#define CAN_F10R1_FB5 ((uint32_t)0x00000020)

Filter bit 5

Definition at line 6854 of file stm32f10x.h.

#define CAN_F10R1_FB6 ((uint32_t)0x00000040)

Filter bit 6

Definition at line 6855 of file stm32f10x.h.

#define CAN_F10R1_FB7 ((uint32_t)0x00000080)

Filter bit 7

Definition at line 6856 of file stm32f10x.h.

#define CAN_F10R1_FB8 ((uint32_t)0x00000100)

Filter bit 8

Definition at line 6857 of file stm32f10x.h.

#define CAN_F10R1_FB9 ((uint32_t)0x00000200)

Filter bit 9

Definition at line 6858 of file stm32f10x.h.

#define CAN_F10R2_FB0 ((uint32_t)0x00000001)

Filter bit 0

Definition at line 7325 of file stm32f10x.h.

#define CAN_F10R2_FB1 ((uint32_t)0x00000002)

Filter bit 1

Definition at line 7326 of file stm32f10x.h.

#define CAN_F10R2_FB10 ((uint32_t)0x00000400)

Filter bit 10

Definition at line 7335 of file stm32f10x.h.

#define CAN_F10R2_FB11 ((uint32_t)0x00000800)

Filter bit 11

Definition at line 7336 of file stm32f10x.h.

#define CAN_F10R2_FB12 ((uint32_t)0x00001000)

Filter bit 12

Definition at line 7337 of file stm32f10x.h.

#define CAN_F10R2_FB13 ((uint32_t)0x00002000)

Filter bit 13

Definition at line 7338 of file stm32f10x.h.

#define CAN_F10R2_FB14 ((uint32_t)0x00004000)

Filter bit 14

Definition at line 7339 of file stm32f10x.h.

#define CAN_F10R2_FB15 ((uint32_t)0x00008000)

Filter bit 15

Definition at line 7340 of file stm32f10x.h.

#define CAN_F10R2_FB16 ((uint32_t)0x00010000)

Filter bit 16

Definition at line 7341 of file stm32f10x.h.

#define CAN_F10R2_FB17 ((uint32_t)0x00020000)

Filter bit 17

Definition at line 7342 of file stm32f10x.h.

#define CAN_F10R2_FB18 ((uint32_t)0x00040000)

Filter bit 18

Definition at line 7343 of file stm32f10x.h.

#define CAN_F10R2_FB19 ((uint32_t)0x00080000)

Filter bit 19

Definition at line 7344 of file stm32f10x.h.

#define CAN_F10R2_FB2 ((uint32_t)0x00000004)

Filter bit 2

Definition at line 7327 of file stm32f10x.h.

#define CAN_F10R2_FB20 ((uint32_t)0x00100000)

Filter bit 20

Definition at line 7345 of file stm32f10x.h.

#define CAN_F10R2_FB21 ((uint32_t)0x00200000)

Filter bit 21

Definition at line 7346 of file stm32f10x.h.

#define CAN_F10R2_FB22 ((uint32_t)0x00400000)

Filter bit 22

Definition at line 7347 of file stm32f10x.h.

#define CAN_F10R2_FB23 ((uint32_t)0x00800000)

Filter bit 23

Definition at line 7348 of file stm32f10x.h.

#define CAN_F10R2_FB24 ((uint32_t)0x01000000)

Filter bit 24

Definition at line 7349 of file stm32f10x.h.

#define CAN_F10R2_FB25 ((uint32_t)0x02000000)

Filter bit 25

Definition at line 7350 of file stm32f10x.h.

#define CAN_F10R2_FB26 ((uint32_t)0x04000000)

Filter bit 26

Definition at line 7351 of file stm32f10x.h.

#define CAN_F10R2_FB27 ((uint32_t)0x08000000)

Filter bit 27

Definition at line 7352 of file stm32f10x.h.

#define CAN_F10R2_FB28 ((uint32_t)0x10000000)

Filter bit 28

Definition at line 7353 of file stm32f10x.h.

#define CAN_F10R2_FB29 ((uint32_t)0x20000000)

Filter bit 29

Definition at line 7354 of file stm32f10x.h.

#define CAN_F10R2_FB3 ((uint32_t)0x00000008)

Filter bit 3

Definition at line 7328 of file stm32f10x.h.

#define CAN_F10R2_FB30 ((uint32_t)0x40000000)

Filter bit 30

Definition at line 7355 of file stm32f10x.h.

#define CAN_F10R2_FB31 ((uint32_t)0x80000000)

Filter bit 31

Definition at line 7356 of file stm32f10x.h.

#define CAN_F10R2_FB4 ((uint32_t)0x00000010)

Filter bit 4

Definition at line 7329 of file stm32f10x.h.

#define CAN_F10R2_FB5 ((uint32_t)0x00000020)

Filter bit 5

Definition at line 7330 of file stm32f10x.h.

#define CAN_F10R2_FB6 ((uint32_t)0x00000040)

Filter bit 6

Definition at line 7331 of file stm32f10x.h.

#define CAN_F10R2_FB7 ((uint32_t)0x00000080)

Filter bit 7

Definition at line 7332 of file stm32f10x.h.

#define CAN_F10R2_FB8 ((uint32_t)0x00000100)

Filter bit 8

Definition at line 7333 of file stm32f10x.h.

#define CAN_F10R2_FB9 ((uint32_t)0x00000200)

Filter bit 9

Definition at line 7334 of file stm32f10x.h.

#define CAN_F11R1_FB0 ((uint32_t)0x00000001)

Filter bit 0

Definition at line 6883 of file stm32f10x.h.

#define CAN_F11R1_FB1 ((uint32_t)0x00000002)

Filter bit 1

Definition at line 6884 of file stm32f10x.h.

#define CAN_F11R1_FB10 ((uint32_t)0x00000400)

Filter bit 10

Definition at line 6893 of file stm32f10x.h.

#define CAN_F11R1_FB11 ((uint32_t)0x00000800)

Filter bit 11

Definition at line 6894 of file stm32f10x.h.

#define CAN_F11R1_FB12 ((uint32_t)0x00001000)

Filter bit 12

Definition at line 6895 of file stm32f10x.h.

#define CAN_F11R1_FB13 ((uint32_t)0x00002000)

Filter bit 13

Definition at line 6896 of file stm32f10x.h.

#define CAN_F11R1_FB14 ((uint32_t)0x00004000)

Filter bit 14

Definition at line 6897 of file stm32f10x.h.

#define CAN_F11R1_FB15 ((uint32_t)0x00008000)

Filter bit 15

Definition at line 6898 of file stm32f10x.h.

#define CAN_F11R1_FB16 ((uint32_t)0x00010000)

Filter bit 16

Definition at line 6899 of file stm32f10x.h.

#define CAN_F11R1_FB17 ((uint32_t)0x00020000)

Filter bit 17

Definition at line 6900 of file stm32f10x.h.

#define CAN_F11R1_FB18 ((uint32_t)0x00040000)

Filter bit 18

Definition at line 6901 of file stm32f10x.h.

#define CAN_F11R1_FB19 ((uint32_t)0x00080000)

Filter bit 19

Definition at line 6902 of file stm32f10x.h.

#define CAN_F11R1_FB2 ((uint32_t)0x00000004)

Filter bit 2

Definition at line 6885 of file stm32f10x.h.

#define CAN_F11R1_FB20 ((uint32_t)0x00100000)

Filter bit 20

Definition at line 6903 of file stm32f10x.h.

#define CAN_F11R1_FB21 ((uint32_t)0x00200000)

Filter bit 21

Definition at line 6904 of file stm32f10x.h.

#define CAN_F11R1_FB22 ((uint32_t)0x00400000)

Filter bit 22

Definition at line 6905 of file stm32f10x.h.

#define CAN_F11R1_FB23 ((uint32_t)0x00800000)

Filter bit 23

Definition at line 6906 of file stm32f10x.h.

#define CAN_F11R1_FB24 ((uint32_t)0x01000000)

Filter bit 24

Definition at line 6907 of file stm32f10x.h.

#define CAN_F11R1_FB25 ((uint32_t)0x02000000)

Filter bit 25

Definition at line 6908 of file stm32f10x.h.

#define CAN_F11R1_FB26 ((uint32_t)0x04000000)

Filter bit 26

Definition at line 6909 of file stm32f10x.h.

#define CAN_F11R1_FB27 ((uint32_t)0x08000000)

Filter bit 27

Definition at line 6910 of file stm32f10x.h.

#define CAN_F11R1_FB28 ((uint32_t)0x10000000)

Filter bit 28

Definition at line 6911 of file stm32f10x.h.

#define CAN_F11R1_FB29 ((uint32_t)0x20000000)

Filter bit 29

Definition at line 6912 of file stm32f10x.h.

#define CAN_F11R1_FB3 ((uint32_t)0x00000008)

Filter bit 3

Definition at line 6886 of file stm32f10x.h.

#define CAN_F11R1_FB30 ((uint32_t)0x40000000)

Filter bit 30

Definition at line 6913 of file stm32f10x.h.

#define CAN_F11R1_FB31 ((uint32_t)0x80000000)

Filter bit 31

Definition at line 6914 of file stm32f10x.h.

#define CAN_F11R1_FB4 ((uint32_t)0x00000010)

Filter bit 4

Definition at line 6887 of file stm32f10x.h.

#define CAN_F11R1_FB5 ((uint32_t)0x00000020)

Filter bit 5

Definition at line 6888 of file stm32f10x.h.

#define CAN_F11R1_FB6 ((uint32_t)0x00000040)

Filter bit 6

Definition at line 6889 of file stm32f10x.h.

#define CAN_F11R1_FB7 ((uint32_t)0x00000080)

Filter bit 7

Definition at line 6890 of file stm32f10x.h.

#define CAN_F11R1_FB8 ((uint32_t)0x00000100)

Filter bit 8

Definition at line 6891 of file stm32f10x.h.

#define CAN_F11R1_FB9 ((uint32_t)0x00000200)

Filter bit 9

Definition at line 6892 of file stm32f10x.h.

#define CAN_F11R2_FB0 ((uint32_t)0x00000001)

Filter bit 0

Definition at line 7359 of file stm32f10x.h.

#define CAN_F11R2_FB1 ((uint32_t)0x00000002)

Filter bit 1

Definition at line 7360 of file stm32f10x.h.

#define CAN_F11R2_FB10 ((uint32_t)0x00000400)

Filter bit 10

Definition at line 7369 of file stm32f10x.h.

#define CAN_F11R2_FB11 ((uint32_t)0x00000800)

Filter bit 11

Definition at line 7370 of file stm32f10x.h.

#define CAN_F11R2_FB12 ((uint32_t)0x00001000)

Filter bit 12

Definition at line 7371 of file stm32f10x.h.

#define CAN_F11R2_FB13 ((uint32_t)0x00002000)

Filter bit 13

Definition at line 7372 of file stm32f10x.h.

#define CAN_F11R2_FB14 ((uint32_t)0x00004000)

Filter bit 14

Definition at line 7373 of file stm32f10x.h.

#define CAN_F11R2_FB15 ((uint32_t)0x00008000)

Filter bit 15

Definition at line 7374 of file stm32f10x.h.

#define CAN_F11R2_FB16 ((uint32_t)0x00010000)

Filter bit 16

Definition at line 7375 of file stm32f10x.h.

#define CAN_F11R2_FB17 ((uint32_t)0x00020000)

Filter bit 17

Definition at line 7376 of file stm32f10x.h.

#define CAN_F11R2_FB18 ((uint32_t)0x00040000)

Filter bit 18

Definition at line 7377 of file stm32f10x.h.

#define CAN_F11R2_FB19 ((uint32_t)0x00080000)

Filter bit 19

Definition at line 7378 of file stm32f10x.h.

#define CAN_F11R2_FB2 ((uint32_t)0x00000004)

Filter bit 2

Definition at line 7361 of file stm32f10x.h.

#define CAN_F11R2_FB20 ((uint32_t)0x00100000)

Filter bit 20

Definition at line 7379 of file stm32f10x.h.

#define CAN_F11R2_FB21 ((uint32_t)0x00200000)

Filter bit 21

Definition at line 7380 of file stm32f10x.h.

#define CAN_F11R2_FB22 ((uint32_t)0x00400000)

Filter bit 22

Definition at line 7381 of file stm32f10x.h.

#define CAN_F11R2_FB23 ((uint32_t)0x00800000)

Filter bit 23

Definition at line 7382 of file stm32f10x.h.

#define CAN_F11R2_FB24 ((uint32_t)0x01000000)

Filter bit 24

Definition at line 7383 of file stm32f10x.h.

#define CAN_F11R2_FB25 ((uint32_t)0x02000000)

Filter bit 25

Definition at line 7384 of file stm32f10x.h.

#define CAN_F11R2_FB26 ((uint32_t)0x04000000)

Filter bit 26

Definition at line 7385 of file stm32f10x.h.

#define CAN_F11R2_FB27 ((uint32_t)0x08000000)

Filter bit 27

Definition at line 7386 of file stm32f10x.h.

#define CAN_F11R2_FB28 ((uint32_t)0x10000000)

Filter bit 28

Definition at line 7387 of file stm32f10x.h.

#define CAN_F11R2_FB29 ((uint32_t)0x20000000)

Filter bit 29

Definition at line 7388 of file stm32f10x.h.

#define CAN_F11R2_FB3 ((uint32_t)0x00000008)

Filter bit 3

Definition at line 7362 of file stm32f10x.h.

#define CAN_F11R2_FB30 ((uint32_t)0x40000000)

Filter bit 30

Definition at line 7389 of file stm32f10x.h.

#define CAN_F11R2_FB31 ((uint32_t)0x80000000)

Filter bit 31

Definition at line 7390 of file stm32f10x.h.

#define CAN_F11R2_FB4 ((uint32_t)0x00000010)

Filter bit 4

Definition at line 7363 of file stm32f10x.h.

#define CAN_F11R2_FB5 ((uint32_t)0x00000020)

Filter bit 5

Definition at line 7364 of file stm32f10x.h.

#define CAN_F11R2_FB6 ((uint32_t)0x00000040)

Filter bit 6

Definition at line 7365 of file stm32f10x.h.

#define CAN_F11R2_FB7 ((uint32_t)0x00000080)

Filter bit 7

Definition at line 7366 of file stm32f10x.h.

#define CAN_F11R2_FB8 ((uint32_t)0x00000100)

Filter bit 8

Definition at line 7367 of file stm32f10x.h.

#define CAN_F11R2_FB9 ((uint32_t)0x00000200)

Filter bit 9

Definition at line 7368 of file stm32f10x.h.

#define CAN_F12R1_FB0 ((uint32_t)0x00000001)

Filter bit 0

Definition at line 6917 of file stm32f10x.h.

#define CAN_F12R1_FB1 ((uint32_t)0x00000002)

Filter bit 1

Definition at line 6918 of file stm32f10x.h.

#define CAN_F12R1_FB10 ((uint32_t)0x00000400)

Filter bit 10

Definition at line 6927 of file stm32f10x.h.

#define CAN_F12R1_FB11 ((uint32_t)0x00000800)

Filter bit 11

Definition at line 6928 of file stm32f10x.h.

#define CAN_F12R1_FB12 ((uint32_t)0x00001000)

Filter bit 12

Definition at line 6929 of file stm32f10x.h.

#define CAN_F12R1_FB13 ((uint32_t)0x00002000)

Filter bit 13

Definition at line 6930 of file stm32f10x.h.

#define CAN_F12R1_FB14 ((uint32_t)0x00004000)

Filter bit 14

Definition at line 6931 of file stm32f10x.h.

#define CAN_F12R1_FB15 ((uint32_t)0x00008000)

Filter bit 15

Definition at line 6932 of file stm32f10x.h.

#define CAN_F12R1_FB16 ((uint32_t)0x00010000)

Filter bit 16

Definition at line 6933 of file stm32f10x.h.

#define CAN_F12R1_FB17 ((uint32_t)0x00020000)

Filter bit 17

Definition at line 6934 of file stm32f10x.h.

#define CAN_F12R1_FB18 ((uint32_t)0x00040000)

Filter bit 18

Definition at line 6935 of file stm32f10x.h.

#define CAN_F12R1_FB19 ((uint32_t)0x00080000)

Filter bit 19

Definition at line 6936 of file stm32f10x.h.

#define CAN_F12R1_FB2 ((uint32_t)0x00000004)

Filter bit 2

Definition at line 6919 of file stm32f10x.h.

#define CAN_F12R1_FB20 ((uint32_t)0x00100000)

Filter bit 20

Definition at line 6937 of file stm32f10x.h.

#define CAN_F12R1_FB21 ((uint32_t)0x00200000)

Filter bit 21

Definition at line 6938 of file stm32f10x.h.

#define CAN_F12R1_FB22 ((uint32_t)0x00400000)

Filter bit 22

Definition at line 6939 of file stm32f10x.h.

#define CAN_F12R1_FB23 ((uint32_t)0x00800000)

Filter bit 23

Definition at line 6940 of file stm32f10x.h.

#define CAN_F12R1_FB24 ((uint32_t)0x01000000)

Filter bit 24

Definition at line 6941 of file stm32f10x.h.

#define CAN_F12R1_FB25 ((uint32_t)0x02000000)

Filter bit 25

Definition at line 6942 of file stm32f10x.h.

#define CAN_F12R1_FB26 ((uint32_t)0x04000000)

Filter bit 26

Definition at line 6943 of file stm32f10x.h.

#define CAN_F12R1_FB27 ((uint32_t)0x08000000)

Filter bit 27

Definition at line 6944 of file stm32f10x.h.

#define CAN_F12R1_FB28 ((uint32_t)0x10000000)

Filter bit 28

Definition at line 6945 of file stm32f10x.h.

#define CAN_F12R1_FB29 ((uint32_t)0x20000000)

Filter bit 29

Definition at line 6946 of file stm32f10x.h.

#define CAN_F12R1_FB3 ((uint32_t)0x00000008)

Filter bit 3

Definition at line 6920 of file stm32f10x.h.

#define CAN_F12R1_FB30 ((uint32_t)0x40000000)

Filter bit 30

Definition at line 6947 of file stm32f10x.h.

#define CAN_F12R1_FB31 ((uint32_t)0x80000000)

Filter bit 31

Definition at line 6948 of file stm32f10x.h.

#define CAN_F12R1_FB4 ((uint32_t)0x00000010)

Filter bit 4

Definition at line 6921 of file stm32f10x.h.

#define CAN_F12R1_FB5 ((uint32_t)0x00000020)

Filter bit 5

Definition at line 6922 of file stm32f10x.h.

#define CAN_F12R1_FB6 ((uint32_t)0x00000040)

Filter bit 6

Definition at line 6923 of file stm32f10x.h.

#define CAN_F12R1_FB7 ((uint32_t)0x00000080)

Filter bit 7

Definition at line 6924 of file stm32f10x.h.

#define CAN_F12R1_FB8 ((uint32_t)0x00000100)

Filter bit 8

Definition at line 6925 of file stm32f10x.h.

#define CAN_F12R1_FB9 ((uint32_t)0x00000200)

Filter bit 9

Definition at line 6926 of file stm32f10x.h.

#define CAN_F12R2_FB0 ((uint32_t)0x00000001)

Filter bit 0

Definition at line 7393 of file stm32f10x.h.

#define CAN_F12R2_FB1 ((uint32_t)0x00000002)

Filter bit 1

Definition at line 7394 of file stm32f10x.h.

#define CAN_F12R2_FB10 ((uint32_t)0x00000400)

Filter bit 10

Definition at line 7403 of file stm32f10x.h.

#define CAN_F12R2_FB11 ((uint32_t)0x00000800)

Filter bit 11

Definition at line 7404 of file stm32f10x.h.

#define CAN_F12R2_FB12 ((uint32_t)0x00001000)

Filter bit 12

Definition at line 7405 of file stm32f10x.h.

#define CAN_F12R2_FB13 ((uint32_t)0x00002000)

Filter bit 13

Definition at line 7406 of file stm32f10x.h.

#define CAN_F12R2_FB14 ((uint32_t)0x00004000)

Filter bit 14

Definition at line 7407 of file stm32f10x.h.

#define CAN_F12R2_FB15 ((uint32_t)0x00008000)

Filter bit 15

Definition at line 7408 of file stm32f10x.h.

#define CAN_F12R2_FB16 ((uint32_t)0x00010000)

Filter bit 16

Definition at line 7409 of file stm32f10x.h.

#define CAN_F12R2_FB17 ((uint32_t)0x00020000)

Filter bit 17

Definition at line 7410 of file stm32f10x.h.

#define CAN_F12R2_FB18 ((uint32_t)0x00040000)

Filter bit 18

Definition at line 7411 of file stm32f10x.h.

#define CAN_F12R2_FB19 ((uint32_t)0x00080000)

Filter bit 19

Definition at line 7412 of file stm32f10x.h.

#define CAN_F12R2_FB2 ((uint32_t)0x00000004)

Filter bit 2

Definition at line 7395 of file stm32f10x.h.

#define CAN_F12R2_FB20 ((uint32_t)0x00100000)

Filter bit 20

Definition at line 7413 of file stm32f10x.h.

#define CAN_F12R2_FB21 ((uint32_t)0x00200000)

Filter bit 21

Definition at line 7414 of file stm32f10x.h.

#define CAN_F12R2_FB22 ((uint32_t)0x00400000)

Filter bit 22

Definition at line 7415 of file stm32f10x.h.

#define CAN_F12R2_FB23 ((uint32_t)0x00800000)

Filter bit 23

Definition at line 7416 of file stm32f10x.h.

#define CAN_F12R2_FB24 ((uint32_t)0x01000000)

Filter bit 24

Definition at line 7417 of file stm32f10x.h.

#define CAN_F12R2_FB25 ((uint32_t)0x02000000)

Filter bit 25

Definition at line 7418 of file stm32f10x.h.

#define CAN_F12R2_FB26 ((uint32_t)0x04000000)

Filter bit 26

Definition at line 7419 of file stm32f10x.h.

#define CAN_F12R2_FB27 ((uint32_t)0x08000000)

Filter bit 27

Definition at line 7420 of file stm32f10x.h.

#define CAN_F12R2_FB28 ((uint32_t)0x10000000)

Filter bit 28

Definition at line 7421 of file stm32f10x.h.

#define CAN_F12R2_FB29 ((uint32_t)0x20000000)

Filter bit 29

Definition at line 7422 of file stm32f10x.h.

#define CAN_F12R2_FB3 ((uint32_t)0x00000008)

Filter bit 3

Definition at line 7396 of file stm32f10x.h.

#define CAN_F12R2_FB30 ((uint32_t)0x40000000)

Filter bit 30

Definition at line 7423 of file stm32f10x.h.

#define CAN_F12R2_FB31 ((uint32_t)0x80000000)

Filter bit 31

Definition at line 7424 of file stm32f10x.h.

#define CAN_F12R2_FB4 ((uint32_t)0x00000010)

Filter bit 4

Definition at line 7397 of file stm32f10x.h.

#define CAN_F12R2_FB5 ((uint32_t)0x00000020)

Filter bit 5

Definition at line 7398 of file stm32f10x.h.

#define CAN_F12R2_FB6 ((uint32_t)0x00000040)

Filter bit 6

Definition at line 7399 of file stm32f10x.h.

#define CAN_F12R2_FB7 ((uint32_t)0x00000080)

Filter bit 7

Definition at line 7400 of file stm32f10x.h.

#define CAN_F12R2_FB8 ((uint32_t)0x00000100)

Filter bit 8

Definition at line 7401 of file stm32f10x.h.

#define CAN_F12R2_FB9 ((uint32_t)0x00000200)

Filter bit 9

Definition at line 7402 of file stm32f10x.h.

#define CAN_F13R1_FB0 ((uint32_t)0x00000001)

Filter bit 0

Definition at line 6951 of file stm32f10x.h.

#define CAN_F13R1_FB1 ((uint32_t)0x00000002)

Filter bit 1

Definition at line 6952 of file stm32f10x.h.

#define CAN_F13R1_FB10 ((uint32_t)0x00000400)

Filter bit 10

Definition at line 6961 of file stm32f10x.h.

#define CAN_F13R1_FB11 ((uint32_t)0x00000800)

Filter bit 11

Definition at line 6962 of file stm32f10x.h.

#define CAN_F13R1_FB12 ((uint32_t)0x00001000)

Filter bit 12

Definition at line 6963 of file stm32f10x.h.

#define CAN_F13R1_FB13 ((uint32_t)0x00002000)

Filter bit 13

Definition at line 6964 of file stm32f10x.h.

#define CAN_F13R1_FB14 ((uint32_t)0x00004000)

Filter bit 14

Definition at line 6965 of file stm32f10x.h.

#define CAN_F13R1_FB15 ((uint32_t)0x00008000)

Filter bit 15

Definition at line 6966 of file stm32f10x.h.

#define CAN_F13R1_FB16 ((uint32_t)0x00010000)

Filter bit 16

Definition at line 6967 of file stm32f10x.h.

#define CAN_F13R1_FB17 ((uint32_t)0x00020000)

Filter bit 17

Definition at line 6968 of file stm32f10x.h.

#define CAN_F13R1_FB18 ((uint32_t)0x00040000)

Filter bit 18

Definition at line 6969 of file stm32f10x.h.

#define CAN_F13R1_FB19 ((uint32_t)0x00080000)

Filter bit 19

Definition at line 6970 of file stm32f10x.h.

#define CAN_F13R1_FB2 ((uint32_t)0x00000004)

Filter bit 2

Definition at line 6953 of file stm32f10x.h.

#define CAN_F13R1_FB20 ((uint32_t)0x00100000)

Filter bit 20

Definition at line 6971 of file stm32f10x.h.

#define CAN_F13R1_FB21 ((uint32_t)0x00200000)

Filter bit 21

Definition at line 6972 of file stm32f10x.h.

#define CAN_F13R1_FB22 ((uint32_t)0x00400000)

Filter bit 22

Definition at line 6973 of file stm32f10x.h.

#define CAN_F13R1_FB23 ((uint32_t)0x00800000)

Filter bit 23

Definition at line 6974 of file stm32f10x.h.

#define CAN_F13R1_FB24 ((uint32_t)0x01000000)

Filter bit 24

Definition at line 6975 of file stm32f10x.h.

#define CAN_F13R1_FB25 ((uint32_t)0x02000000)

Filter bit 25

Definition at line 6976 of file stm32f10x.h.

#define CAN_F13R1_FB26 ((uint32_t)0x04000000)

Filter bit 26

Definition at line 6977 of file stm32f10x.h.

#define CAN_F13R1_FB27 ((uint32_t)0x08000000)

Filter bit 27

Definition at line 6978 of file stm32f10x.h.

#define CAN_F13R1_FB28 ((uint32_t)0x10000000)

Filter bit 28

Definition at line 6979 of file stm32f10x.h.

#define CAN_F13R1_FB29 ((uint32_t)0x20000000)

Filter bit 29

Definition at line 6980 of file stm32f10x.h.

#define CAN_F13R1_FB3 ((uint32_t)0x00000008)

Filter bit 3

Definition at line 6954 of file stm32f10x.h.

#define CAN_F13R1_FB30 ((uint32_t)0x40000000)

Filter bit 30

Definition at line 6981 of file stm32f10x.h.

#define CAN_F13R1_FB31 ((uint32_t)0x80000000)

Filter bit 31

Definition at line 6982 of file stm32f10x.h.

#define CAN_F13R1_FB4 ((uint32_t)0x00000010)

Filter bit 4

Definition at line 6955 of file stm32f10x.h.

#define CAN_F13R1_FB5 ((uint32_t)0x00000020)

Filter bit 5

Definition at line 6956 of file stm32f10x.h.

#define CAN_F13R1_FB6 ((uint32_t)0x00000040)

Filter bit 6

Definition at line 6957 of file stm32f10x.h.

#define CAN_F13R1_FB7 ((uint32_t)0x00000080)

Filter bit 7

Definition at line 6958 of file stm32f10x.h.

#define CAN_F13R1_FB8 ((uint32_t)0x00000100)

Filter bit 8

Definition at line 6959 of file stm32f10x.h.

#define CAN_F13R1_FB9 ((uint32_t)0x00000200)

Filter bit 9

Definition at line 6960 of file stm32f10x.h.

#define CAN_F13R2_FB0 ((uint32_t)0x00000001)

Filter bit 0

Definition at line 7427 of file stm32f10x.h.

#define CAN_F13R2_FB1 ((uint32_t)0x00000002)

Filter bit 1

Definition at line 7428 of file stm32f10x.h.

#define CAN_F13R2_FB10 ((uint32_t)0x00000400)

Filter bit 10

Definition at line 7437 of file stm32f10x.h.

#define CAN_F13R2_FB11 ((uint32_t)0x00000800)

Filter bit 11

Definition at line 7438 of file stm32f10x.h.

#define CAN_F13R2_FB12 ((uint32_t)0x00001000)

Filter bit 12

Definition at line 7439 of file stm32f10x.h.

#define CAN_F13R2_FB13 ((uint32_t)0x00002000)

Filter bit 13

Definition at line 7440 of file stm32f10x.h.

#define CAN_F13R2_FB14 ((uint32_t)0x00004000)

Filter bit 14

Definition at line 7441 of file stm32f10x.h.

#define CAN_F13R2_FB15 ((uint32_t)0x00008000)

Filter bit 15

Definition at line 7442 of file stm32f10x.h.

#define CAN_F13R2_FB16 ((uint32_t)0x00010000)

Filter bit 16

Definition at line 7443 of file stm32f10x.h.

#define CAN_F13R2_FB17 ((uint32_t)0x00020000)

Filter bit 17

Definition at line 7444 of file stm32f10x.h.

#define CAN_F13R2_FB18 ((uint32_t)0x00040000)

Filter bit 18

Definition at line 7445 of file stm32f10x.h.

#define CAN_F13R2_FB19 ((uint32_t)0x00080000)

Filter bit 19

Definition at line 7446 of file stm32f10x.h.

#define CAN_F13R2_FB2 ((uint32_t)0x00000004)

Filter bit 2

Definition at line 7429 of file stm32f10x.h.

#define CAN_F13R2_FB20 ((uint32_t)0x00100000)

Filter bit 20

Definition at line 7447 of file stm32f10x.h.

#define CAN_F13R2_FB21 ((uint32_t)0x00200000)

Filter bit 21

Definition at line 7448 of file stm32f10x.h.

#define CAN_F13R2_FB22 ((uint32_t)0x00400000)

Filter bit 22

Definition at line 7449 of file stm32f10x.h.

#define CAN_F13R2_FB23 ((uint32_t)0x00800000)

Filter bit 23

Definition at line 7450 of file stm32f10x.h.

#define CAN_F13R2_FB24 ((uint32_t)0x01000000)

Filter bit 24

Definition at line 7451 of file stm32f10x.h.

#define CAN_F13R2_FB25 ((uint32_t)0x02000000)

Filter bit 25

Definition at line 7452 of file stm32f10x.h.

#define CAN_F13R2_FB26 ((uint32_t)0x04000000)

Filter bit 26

Definition at line 7453 of file stm32f10x.h.

#define CAN_F13R2_FB27 ((uint32_t)0x08000000)

Filter bit 27

Definition at line 7454 of file stm32f10x.h.

#define CAN_F13R2_FB28 ((uint32_t)0x10000000)

Filter bit 28

Definition at line 7455 of file stm32f10x.h.

#define CAN_F13R2_FB29 ((uint32_t)0x20000000)

Filter bit 29

Definition at line 7456 of file stm32f10x.h.

#define CAN_F13R2_FB3 ((uint32_t)0x00000008)

Filter bit 3

Definition at line 7430 of file stm32f10x.h.

#define CAN_F13R2_FB30 ((uint32_t)0x40000000)

Filter bit 30

Definition at line 7457 of file stm32f10x.h.

#define CAN_F13R2_FB31 ((uint32_t)0x80000000)

Filter bit 31

Definition at line 7458 of file stm32f10x.h.

#define CAN_F13R2_FB4 ((uint32_t)0x00000010)

Filter bit 4

Definition at line 7431 of file stm32f10x.h.

#define CAN_F13R2_FB5 ((uint32_t)0x00000020)

Filter bit 5

Definition at line 7432 of file stm32f10x.h.

#define CAN_F13R2_FB6 ((uint32_t)0x00000040)

Filter bit 6

Definition at line 7433 of file stm32f10x.h.

#define CAN_F13R2_FB7 ((uint32_t)0x00000080)

Filter bit 7

Definition at line 7434 of file stm32f10x.h.

#define CAN_F13R2_FB8 ((uint32_t)0x00000100)

Filter bit 8

Definition at line 7435 of file stm32f10x.h.

#define CAN_F13R2_FB9 ((uint32_t)0x00000200)

Filter bit 9

Definition at line 7436 of file stm32f10x.h.

#define CAN_F1R1_FB0 ((uint32_t)0x00000001)

Filter bit 0

Definition at line 6543 of file stm32f10x.h.

#define CAN_F1R1_FB1 ((uint32_t)0x00000002)

Filter bit 1

Definition at line 6544 of file stm32f10x.h.

#define CAN_F1R1_FB10 ((uint32_t)0x00000400)

Filter bit 10

Definition at line 6553 of file stm32f10x.h.

#define CAN_F1R1_FB11 ((uint32_t)0x00000800)

Filter bit 11

Definition at line 6554 of file stm32f10x.h.

#define CAN_F1R1_FB12 ((uint32_t)0x00001000)

Filter bit 12

Definition at line 6555 of file stm32f10x.h.

#define CAN_F1R1_FB13 ((uint32_t)0x00002000)

Filter bit 13

Definition at line 6556 of file stm32f10x.h.

#define CAN_F1R1_FB14 ((uint32_t)0x00004000)

Filter bit 14

Definition at line 6557 of file stm32f10x.h.

#define CAN_F1R1_FB15 ((uint32_t)0x00008000)

Filter bit 15

Definition at line 6558 of file stm32f10x.h.

#define CAN_F1R1_FB16 ((uint32_t)0x00010000)

Filter bit 16

Definition at line 6559 of file stm32f10x.h.

#define CAN_F1R1_FB17 ((uint32_t)0x00020000)

Filter bit 17

Definition at line 6560 of file stm32f10x.h.

#define CAN_F1R1_FB18 ((uint32_t)0x00040000)

Filter bit 18

Definition at line 6561 of file stm32f10x.h.

#define CAN_F1R1_FB19 ((uint32_t)0x00080000)

Filter bit 19

Definition at line 6562 of file stm32f10x.h.

#define CAN_F1R1_FB2 ((uint32_t)0x00000004)

Filter bit 2

Definition at line 6545 of file stm32f10x.h.

#define CAN_F1R1_FB20 ((uint32_t)0x00100000)

Filter bit 20

Definition at line 6563 of file stm32f10x.h.

#define CAN_F1R1_FB21 ((uint32_t)0x00200000)

Filter bit 21

Definition at line 6564 of file stm32f10x.h.

#define CAN_F1R1_FB22 ((uint32_t)0x00400000)

Filter bit 22

Definition at line 6565 of file stm32f10x.h.

#define CAN_F1R1_FB23 ((uint32_t)0x00800000)

Filter bit 23

Definition at line 6566 of file stm32f10x.h.

#define CAN_F1R1_FB24 ((uint32_t)0x01000000)

Filter bit 24

Definition at line 6567 of file stm32f10x.h.

#define CAN_F1R1_FB25 ((uint32_t)0x02000000)

Filter bit 25

Definition at line 6568 of file stm32f10x.h.

#define CAN_F1R1_FB26 ((uint32_t)0x04000000)

Filter bit 26

Definition at line 6569 of file stm32f10x.h.

#define CAN_F1R1_FB27 ((uint32_t)0x08000000)

Filter bit 27

Definition at line 6570 of file stm32f10x.h.

#define CAN_F1R1_FB28 ((uint32_t)0x10000000)

Filter bit 28

Definition at line 6571 of file stm32f10x.h.

#define CAN_F1R1_FB29 ((uint32_t)0x20000000)

Filter bit 29

Definition at line 6572 of file stm32f10x.h.

#define CAN_F1R1_FB3 ((uint32_t)0x00000008)

Filter bit 3

Definition at line 6546 of file stm32f10x.h.

#define CAN_F1R1_FB30 ((uint32_t)0x40000000)

Filter bit 30

Definition at line 6573 of file stm32f10x.h.

#define CAN_F1R1_FB31 ((uint32_t)0x80000000)

Filter bit 31

Definition at line 6574 of file stm32f10x.h.

#define CAN_F1R1_FB4 ((uint32_t)0x00000010)

Filter bit 4

Definition at line 6547 of file stm32f10x.h.

#define CAN_F1R1_FB5 ((uint32_t)0x00000020)

Filter bit 5

Definition at line 6548 of file stm32f10x.h.

#define CAN_F1R1_FB6 ((uint32_t)0x00000040)

Filter bit 6

Definition at line 6549 of file stm32f10x.h.

#define CAN_F1R1_FB7 ((uint32_t)0x00000080)

Filter bit 7

Definition at line 6550 of file stm32f10x.h.

#define CAN_F1R1_FB8 ((uint32_t)0x00000100)

Filter bit 8

Definition at line 6551 of file stm32f10x.h.

#define CAN_F1R1_FB9 ((uint32_t)0x00000200)

Filter bit 9

Definition at line 6552 of file stm32f10x.h.

#define CAN_F1R2_FB0 ((uint32_t)0x00000001)

Filter bit 0

Definition at line 7019 of file stm32f10x.h.

#define CAN_F1R2_FB1 ((uint32_t)0x00000002)

Filter bit 1

Definition at line 7020 of file stm32f10x.h.

#define CAN_F1R2_FB10 ((uint32_t)0x00000400)

Filter bit 10

Definition at line 7029 of file stm32f10x.h.

#define CAN_F1R2_FB11 ((uint32_t)0x00000800)

Filter bit 11

Definition at line 7030 of file stm32f10x.h.

#define CAN_F1R2_FB12 ((uint32_t)0x00001000)

Filter bit 12

Definition at line 7031 of file stm32f10x.h.

#define CAN_F1R2_FB13 ((uint32_t)0x00002000)

Filter bit 13

Definition at line 7032 of file stm32f10x.h.

#define CAN_F1R2_FB14 ((uint32_t)0x00004000)

Filter bit 14

Definition at line 7033 of file stm32f10x.h.

#define CAN_F1R2_FB15 ((uint32_t)0x00008000)

Filter bit 15

Definition at line 7034 of file stm32f10x.h.

#define CAN_F1R2_FB16 ((uint32_t)0x00010000)

Filter bit 16

Definition at line 7035 of file stm32f10x.h.

#define CAN_F1R2_FB17 ((uint32_t)0x00020000)

Filter bit 17

Definition at line 7036 of file stm32f10x.h.

#define CAN_F1R2_FB18 ((uint32_t)0x00040000)

Filter bit 18

Definition at line 7037 of file stm32f10x.h.

#define CAN_F1R2_FB19 ((uint32_t)0x00080000)

Filter bit 19

Definition at line 7038 of file stm32f10x.h.

#define CAN_F1R2_FB2 ((uint32_t)0x00000004)

Filter bit 2

Definition at line 7021 of file stm32f10x.h.

#define CAN_F1R2_FB20 ((uint32_t)0x00100000)

Filter bit 20

Definition at line 7039 of file stm32f10x.h.

#define CAN_F1R2_FB21 ((uint32_t)0x00200000)

Filter bit 21

Definition at line 7040 of file stm32f10x.h.

#define CAN_F1R2_FB22 ((uint32_t)0x00400000)

Filter bit 22

Definition at line 7041 of file stm32f10x.h.

#define CAN_F1R2_FB23 ((uint32_t)0x00800000)

Filter bit 23

Definition at line 7042 of file stm32f10x.h.

#define CAN_F1R2_FB24 ((uint32_t)0x01000000)

Filter bit 24

Definition at line 7043 of file stm32f10x.h.

#define CAN_F1R2_FB25 ((uint32_t)0x02000000)

Filter bit 25

Definition at line 7044 of file stm32f10x.h.

#define CAN_F1R2_FB26 ((uint32_t)0x04000000)

Filter bit 26

Definition at line 7045 of file stm32f10x.h.

#define CAN_F1R2_FB27 ((uint32_t)0x08000000)

Filter bit 27

Definition at line 7046 of file stm32f10x.h.

#define CAN_F1R2_FB28 ((uint32_t)0x10000000)

Filter bit 28

Definition at line 7047 of file stm32f10x.h.

#define CAN_F1R2_FB29 ((uint32_t)0x20000000)

Filter bit 29

Definition at line 7048 of file stm32f10x.h.

#define CAN_F1R2_FB3 ((uint32_t)0x00000008)

Filter bit 3

Definition at line 7022 of file stm32f10x.h.

#define CAN_F1R2_FB30 ((uint32_t)0x40000000)

Filter bit 30

Definition at line 7049 of file stm32f10x.h.

#define CAN_F1R2_FB31 ((uint32_t)0x80000000)

Filter bit 31

Definition at line 7050 of file stm32f10x.h.

#define CAN_F1R2_FB4 ((uint32_t)0x00000010)

Filter bit 4

Definition at line 7023 of file stm32f10x.h.

#define CAN_F1R2_FB5 ((uint32_t)0x00000020)

Filter bit 5

Definition at line 7024 of file stm32f10x.h.

#define CAN_F1R2_FB6 ((uint32_t)0x00000040)

Filter bit 6

Definition at line 7025 of file stm32f10x.h.

#define CAN_F1R2_FB7 ((uint32_t)0x00000080)

Filter bit 7

Definition at line 7026 of file stm32f10x.h.

#define CAN_F1R2_FB8 ((uint32_t)0x00000100)

Filter bit 8

Definition at line 7027 of file stm32f10x.h.

#define CAN_F1R2_FB9 ((uint32_t)0x00000200)

Filter bit 9

Definition at line 7028 of file stm32f10x.h.

#define CAN_F2R1_FB0 ((uint32_t)0x00000001)

Filter bit 0

Definition at line 6577 of file stm32f10x.h.

#define CAN_F2R1_FB1 ((uint32_t)0x00000002)

Filter bit 1

Definition at line 6578 of file stm32f10x.h.

#define CAN_F2R1_FB10 ((uint32_t)0x00000400)

Filter bit 10

Definition at line 6587 of file stm32f10x.h.

#define CAN_F2R1_FB11 ((uint32_t)0x00000800)

Filter bit 11

Definition at line 6588 of file stm32f10x.h.

#define CAN_F2R1_FB12 ((uint32_t)0x00001000)

Filter bit 12

Definition at line 6589 of file stm32f10x.h.

#define CAN_F2R1_FB13 ((uint32_t)0x00002000)

Filter bit 13

Definition at line 6590 of file stm32f10x.h.

#define CAN_F2R1_FB14 ((uint32_t)0x00004000)

Filter bit 14

Definition at line 6591 of file stm32f10x.h.

#define CAN_F2R1_FB15 ((uint32_t)0x00008000)

Filter bit 15

Definition at line 6592 of file stm32f10x.h.

#define CAN_F2R1_FB16 ((uint32_t)0x00010000)

Filter bit 16

Definition at line 6593 of file stm32f10x.h.

#define CAN_F2R1_FB17 ((uint32_t)0x00020000)

Filter bit 17

Definition at line 6594 of file stm32f10x.h.

#define CAN_F2R1_FB18 ((uint32_t)0x00040000)

Filter bit 18

Definition at line 6595 of file stm32f10x.h.

#define CAN_F2R1_FB19 ((uint32_t)0x00080000)

Filter bit 19

Definition at line 6596 of file stm32f10x.h.

#define CAN_F2R1_FB2 ((uint32_t)0x00000004)

Filter bit 2

Definition at line 6579 of file stm32f10x.h.

#define CAN_F2R1_FB20 ((uint32_t)0x00100000)

Filter bit 20

Definition at line 6597 of file stm32f10x.h.

#define CAN_F2R1_FB21 ((uint32_t)0x00200000)

Filter bit 21

Definition at line 6598 of file stm32f10x.h.

#define CAN_F2R1_FB22 ((uint32_t)0x00400000)

Filter bit 22

Definition at line 6599 of file stm32f10x.h.

#define CAN_F2R1_FB23 ((uint32_t)0x00800000)

Filter bit 23

Definition at line 6600 of file stm32f10x.h.

#define CAN_F2R1_FB24 ((uint32_t)0x01000000)

Filter bit 24

Definition at line 6601 of file stm32f10x.h.

#define CAN_F2R1_FB25 ((uint32_t)0x02000000)

Filter bit 25

Definition at line 6602 of file stm32f10x.h.

#define CAN_F2R1_FB26 ((uint32_t)0x04000000)

Filter bit 26

Definition at line 6603 of file stm32f10x.h.

#define CAN_F2R1_FB27 ((uint32_t)0x08000000)

Filter bit 27

Definition at line 6604 of file stm32f10x.h.

#define CAN_F2R1_FB28 ((uint32_t)0x10000000)

Filter bit 28

Definition at line 6605 of file stm32f10x.h.

#define CAN_F2R1_FB29 ((uint32_t)0x20000000)

Filter bit 29

Definition at line 6606 of file stm32f10x.h.

#define CAN_F2R1_FB3 ((uint32_t)0x00000008)

Filter bit 3

Definition at line 6580 of file stm32f10x.h.

#define CAN_F2R1_FB30 ((uint32_t)0x40000000)

Filter bit 30

Definition at line 6607 of file stm32f10x.h.

#define CAN_F2R1_FB31 ((uint32_t)0x80000000)

Filter bit 31

Definition at line 6608 of file stm32f10x.h.

#define CAN_F2R1_FB4 ((uint32_t)0x00000010)

Filter bit 4

Definition at line 6581 of file stm32f10x.h.

#define CAN_F2R1_FB5 ((uint32_t)0x00000020)

Filter bit 5

Definition at line 6582 of file stm32f10x.h.

#define CAN_F2R1_FB6 ((uint32_t)0x00000040)

Filter bit 6

Definition at line 6583 of file stm32f10x.h.

#define CAN_F2R1_FB7 ((uint32_t)0x00000080)

Filter bit 7

Definition at line 6584 of file stm32f10x.h.

#define CAN_F2R1_FB8 ((uint32_t)0x00000100)

Filter bit 8

Definition at line 6585 of file stm32f10x.h.

#define CAN_F2R1_FB9 ((uint32_t)0x00000200)

Filter bit 9

Definition at line 6586 of file stm32f10x.h.

#define CAN_F2R2_FB0 ((uint32_t)0x00000001)

Filter bit 0

Definition at line 7053 of file stm32f10x.h.

#define CAN_F2R2_FB1 ((uint32_t)0x00000002)

Filter bit 1

Definition at line 7054 of file stm32f10x.h.

#define CAN_F2R2_FB10 ((uint32_t)0x00000400)

Filter bit 10

Definition at line 7063 of file stm32f10x.h.

#define CAN_F2R2_FB11 ((uint32_t)0x00000800)

Filter bit 11

Definition at line 7064 of file stm32f10x.h.

#define CAN_F2R2_FB12 ((uint32_t)0x00001000)

Filter bit 12

Definition at line 7065 of file stm32f10x.h.

#define CAN_F2R2_FB13 ((uint32_t)0x00002000)

Filter bit 13

Definition at line 7066 of file stm32f10x.h.

#define CAN_F2R2_FB14 ((uint32_t)0x00004000)

Filter bit 14

Definition at line 7067 of file stm32f10x.h.

#define CAN_F2R2_FB15 ((uint32_t)0x00008000)

Filter bit 15

Definition at line 7068 of file stm32f10x.h.

#define CAN_F2R2_FB16 ((uint32_t)0x00010000)

Filter bit 16

Definition at line 7069 of file stm32f10x.h.

#define CAN_F2R2_FB17 ((uint32_t)0x00020000)

Filter bit 17

Definition at line 7070 of file stm32f10x.h.

#define CAN_F2R2_FB18 ((uint32_t)0x00040000)

Filter bit 18

Definition at line 7071 of file stm32f10x.h.

#define CAN_F2R2_FB19 ((uint32_t)0x00080000)

Filter bit 19

Definition at line 7072 of file stm32f10x.h.

#define CAN_F2R2_FB2 ((uint32_t)0x00000004)

Filter bit 2

Definition at line 7055 of file stm32f10x.h.

#define CAN_F2R2_FB20 ((uint32_t)0x00100000)

Filter bit 20

Definition at line 7073 of file stm32f10x.h.

#define CAN_F2R2_FB21 ((uint32_t)0x00200000)

Filter bit 21

Definition at line 7074 of file stm32f10x.h.

#define CAN_F2R2_FB22 ((uint32_t)0x00400000)

Filter bit 22

Definition at line 7075 of file stm32f10x.h.

#define CAN_F2R2_FB23 ((uint32_t)0x00800000)

Filter bit 23

Definition at line 7076 of file stm32f10x.h.

#define CAN_F2R2_FB24 ((uint32_t)0x01000000)

Filter bit 24

Definition at line 7077 of file stm32f10x.h.

#define CAN_F2R2_FB25 ((uint32_t)0x02000000)

Filter bit 25

Definition at line 7078 of file stm32f10x.h.

#define CAN_F2R2_FB26 ((uint32_t)0x04000000)

Filter bit 26

Definition at line 7079 of file stm32f10x.h.

#define CAN_F2R2_FB27 ((uint32_t)0x08000000)

Filter bit 27

Definition at line 7080 of file stm32f10x.h.

#define CAN_F2R2_FB28 ((uint32_t)0x10000000)

Filter bit 28

Definition at line 7081 of file stm32f10x.h.

#define CAN_F2R2_FB29 ((uint32_t)0x20000000)

Filter bit 29

Definition at line 7082 of file stm32f10x.h.

#define CAN_F2R2_FB3 ((uint32_t)0x00000008)

Filter bit 3

Definition at line 7056 of file stm32f10x.h.

#define CAN_F2R2_FB30 ((uint32_t)0x40000000)

Filter bit 30

Definition at line 7083 of file stm32f10x.h.

#define CAN_F2R2_FB31 ((uint32_t)0x80000000)

Filter bit 31

Definition at line 7084 of file stm32f10x.h.

#define CAN_F2R2_FB4 ((uint32_t)0x00000010)

Filter bit 4

Definition at line 7057 of file stm32f10x.h.

#define CAN_F2R2_FB5 ((uint32_t)0x00000020)

Filter bit 5

Definition at line 7058 of file stm32f10x.h.

#define CAN_F2R2_FB6 ((uint32_t)0x00000040)

Filter bit 6

Definition at line 7059 of file stm32f10x.h.

#define CAN_F2R2_FB7 ((uint32_t)0x00000080)

Filter bit 7

Definition at line 7060 of file stm32f10x.h.

#define CAN_F2R2_FB8 ((uint32_t)0x00000100)

Filter bit 8

Definition at line 7061 of file stm32f10x.h.

#define CAN_F2R2_FB9 ((uint32_t)0x00000200)

Filter bit 9

Definition at line 7062 of file stm32f10x.h.

#define CAN_F3R1_FB0 ((uint32_t)0x00000001)

Filter bit 0

Definition at line 6611 of file stm32f10x.h.

#define CAN_F3R1_FB1 ((uint32_t)0x00000002)

Filter bit 1

Definition at line 6612 of file stm32f10x.h.

#define CAN_F3R1_FB10 ((uint32_t)0x00000400)

Filter bit 10

Definition at line 6621 of file stm32f10x.h.

#define CAN_F3R1_FB11 ((uint32_t)0x00000800)

Filter bit 11

Definition at line 6622 of file stm32f10x.h.

#define CAN_F3R1_FB12 ((uint32_t)0x00001000)

Filter bit 12

Definition at line 6623 of file stm32f10x.h.

#define CAN_F3R1_FB13 ((uint32_t)0x00002000)

Filter bit 13

Definition at line 6624 of file stm32f10x.h.

#define CAN_F3R1_FB14 ((uint32_t)0x00004000)

Filter bit 14

Definition at line 6625 of file stm32f10x.h.

#define CAN_F3R1_FB15 ((uint32_t)0x00008000)

Filter bit 15

Definition at line 6626 of file stm32f10x.h.

#define CAN_F3R1_FB16 ((uint32_t)0x00010000)

Filter bit 16

Definition at line 6627 of file stm32f10x.h.

#define CAN_F3R1_FB17 ((uint32_t)0x00020000)

Filter bit 17

Definition at line 6628 of file stm32f10x.h.

#define CAN_F3R1_FB18 ((uint32_t)0x00040000)

Filter bit 18

Definition at line 6629 of file stm32f10x.h.

#define CAN_F3R1_FB19 ((uint32_t)0x00080000)

Filter bit 19

Definition at line 6630 of file stm32f10x.h.

#define CAN_F3R1_FB2 ((uint32_t)0x00000004)

Filter bit 2

Definition at line 6613 of file stm32f10x.h.

#define CAN_F3R1_FB20 ((uint32_t)0x00100000)

Filter bit 20

Definition at line 6631 of file stm32f10x.h.

#define CAN_F3R1_FB21 ((uint32_t)0x00200000)

Filter bit 21

Definition at line 6632 of file stm32f10x.h.

#define CAN_F3R1_FB22 ((uint32_t)0x00400000)

Filter bit 22

Definition at line 6633 of file stm32f10x.h.

#define CAN_F3R1_FB23 ((uint32_t)0x00800000)

Filter bit 23

Definition at line 6634 of file stm32f10x.h.

#define CAN_F3R1_FB24 ((uint32_t)0x01000000)

Filter bit 24

Definition at line 6635 of file stm32f10x.h.

#define CAN_F3R1_FB25 ((uint32_t)0x02000000)

Filter bit 25

Definition at line 6636 of file stm32f10x.h.

#define CAN_F3R1_FB26 ((uint32_t)0x04000000)

Filter bit 26

Definition at line 6637 of file stm32f10x.h.

#define CAN_F3R1_FB27 ((uint32_t)0x08000000)

Filter bit 27

Definition at line 6638 of file stm32f10x.h.

#define CAN_F3R1_FB28 ((uint32_t)0x10000000)

Filter bit 28

Definition at line 6639 of file stm32f10x.h.

#define CAN_F3R1_FB29 ((uint32_t)0x20000000)

Filter bit 29

Definition at line 6640 of file stm32f10x.h.

#define CAN_F3R1_FB3 ((uint32_t)0x00000008)

Filter bit 3

Definition at line 6614 of file stm32f10x.h.

#define CAN_F3R1_FB30 ((uint32_t)0x40000000)

Filter bit 30

Definition at line 6641 of file stm32f10x.h.

#define CAN_F3R1_FB31 ((uint32_t)0x80000000)

Filter bit 31

Definition at line 6642 of file stm32f10x.h.

#define CAN_F3R1_FB4 ((uint32_t)0x00000010)

Filter bit 4

Definition at line 6615 of file stm32f10x.h.

#define CAN_F3R1_FB5 ((uint32_t)0x00000020)

Filter bit 5

Definition at line 6616 of file stm32f10x.h.

#define CAN_F3R1_FB6 ((uint32_t)0x00000040)

Filter bit 6

Definition at line 6617 of file stm32f10x.h.

#define CAN_F3R1_FB7 ((uint32_t)0x00000080)

Filter bit 7

Definition at line 6618 of file stm32f10x.h.

#define CAN_F3R1_FB8 ((uint32_t)0x00000100)

Filter bit 8

Definition at line 6619 of file stm32f10x.h.

#define CAN_F3R1_FB9 ((uint32_t)0x00000200)

Filter bit 9

Definition at line 6620 of file stm32f10x.h.

#define CAN_F3R2_FB0 ((uint32_t)0x00000001)

Filter bit 0

Definition at line 7087 of file stm32f10x.h.

#define CAN_F3R2_FB1 ((uint32_t)0x00000002)

Filter bit 1

Definition at line 7088 of file stm32f10x.h.

#define CAN_F3R2_FB10 ((uint32_t)0x00000400)

Filter bit 10

Definition at line 7097 of file stm32f10x.h.

#define CAN_F3R2_FB11 ((uint32_t)0x00000800)

Filter bit 11

Definition at line 7098 of file stm32f10x.h.

#define CAN_F3R2_FB12 ((uint32_t)0x00001000)

Filter bit 12

Definition at line 7099 of file stm32f10x.h.

#define CAN_F3R2_FB13 ((uint32_t)0x00002000)

Filter bit 13

Definition at line 7100 of file stm32f10x.h.

#define CAN_F3R2_FB14 ((uint32_t)0x00004000)

Filter bit 14

Definition at line 7101 of file stm32f10x.h.

#define CAN_F3R2_FB15 ((uint32_t)0x00008000)

Filter bit 15

Definition at line 7102 of file stm32f10x.h.

#define CAN_F3R2_FB16 ((uint32_t)0x00010000)

Filter bit 16

Definition at line 7103 of file stm32f10x.h.

#define CAN_F3R2_FB17 ((uint32_t)0x00020000)

Filter bit 17

Definition at line 7104 of file stm32f10x.h.

#define CAN_F3R2_FB18 ((uint32_t)0x00040000)

Filter bit 18

Definition at line 7105 of file stm32f10x.h.

#define CAN_F3R2_FB19 ((uint32_t)0x00080000)

Filter bit 19

Definition at line 7106 of file stm32f10x.h.

#define CAN_F3R2_FB2 ((uint32_t)0x00000004)

Filter bit 2

Definition at line 7089 of file stm32f10x.h.

#define CAN_F3R2_FB20 ((uint32_t)0x00100000)

Filter bit 20

Definition at line 7107 of file stm32f10x.h.

#define CAN_F3R2_FB21 ((uint32_t)0x00200000)

Filter bit 21

Definition at line 7108 of file stm32f10x.h.

#define CAN_F3R2_FB22 ((uint32_t)0x00400000)

Filter bit 22

Definition at line 7109 of file stm32f10x.h.

#define CAN_F3R2_FB23 ((uint32_t)0x00800000)

Filter bit 23

Definition at line 7110 of file stm32f10x.h.

#define CAN_F3R2_FB24 ((uint32_t)0x01000000)

Filter bit 24

Definition at line 7111 of file stm32f10x.h.

#define CAN_F3R2_FB25 ((uint32_t)0x02000000)

Filter bit 25

Definition at line 7112 of file stm32f10x.h.

#define CAN_F3R2_FB26 ((uint32_t)0x04000000)

Filter bit 26

Definition at line 7113 of file stm32f10x.h.

#define CAN_F3R2_FB27 ((uint32_t)0x08000000)

Filter bit 27

Definition at line 7114 of file stm32f10x.h.

#define CAN_F3R2_FB28 ((uint32_t)0x10000000)

Filter bit 28

Definition at line 7115 of file stm32f10x.h.

#define CAN_F3R2_FB29 ((uint32_t)0x20000000)

Filter bit 29

Definition at line 7116 of file stm32f10x.h.

#define CAN_F3R2_FB3 ((uint32_t)0x00000008)

Filter bit 3

Definition at line 7090 of file stm32f10x.h.

#define CAN_F3R2_FB30 ((uint32_t)0x40000000)

Filter bit 30

Definition at line 7117 of file stm32f10x.h.

#define CAN_F3R2_FB31 ((uint32_t)0x80000000)

Filter bit 31

Definition at line 7118 of file stm32f10x.h.

#define CAN_F3R2_FB4 ((uint32_t)0x00000010)

Filter bit 4

Definition at line 7091 of file stm32f10x.h.

#define CAN_F3R2_FB5 ((uint32_t)0x00000020)

Filter bit 5

Definition at line 7092 of file stm32f10x.h.

#define CAN_F3R2_FB6 ((uint32_t)0x00000040)

Filter bit 6

Definition at line 7093 of file stm32f10x.h.

#define CAN_F3R2_FB7 ((uint32_t)0x00000080)

Filter bit 7

Definition at line 7094 of file stm32f10x.h.

#define CAN_F3R2_FB8 ((uint32_t)0x00000100)

Filter bit 8

Definition at line 7095 of file stm32f10x.h.

#define CAN_F3R2_FB9 ((uint32_t)0x00000200)

Filter bit 9

Definition at line 7096 of file stm32f10x.h.

#define CAN_F4R1_FB0 ((uint32_t)0x00000001)

Filter bit 0

Definition at line 6645 of file stm32f10x.h.

#define CAN_F4R1_FB1 ((uint32_t)0x00000002)

Filter bit 1

Definition at line 6646 of file stm32f10x.h.

#define CAN_F4R1_FB10 ((uint32_t)0x00000400)

Filter bit 10

Definition at line 6655 of file stm32f10x.h.

#define CAN_F4R1_FB11 ((uint32_t)0x00000800)

Filter bit 11

Definition at line 6656 of file stm32f10x.h.

#define CAN_F4R1_FB12 ((uint32_t)0x00001000)

Filter bit 12

Definition at line 6657 of file stm32f10x.h.

#define CAN_F4R1_FB13 ((uint32_t)0x00002000)

Filter bit 13

Definition at line 6658 of file stm32f10x.h.

#define CAN_F4R1_FB14 ((uint32_t)0x00004000)

Filter bit 14

Definition at line 6659 of file stm32f10x.h.

#define CAN_F4R1_FB15 ((uint32_t)0x00008000)

Filter bit 15

Definition at line 6660 of file stm32f10x.h.

#define CAN_F4R1_FB16 ((uint32_t)0x00010000)

Filter bit 16

Definition at line 6661 of file stm32f10x.h.

#define CAN_F4R1_FB17 ((uint32_t)0x00020000)

Filter bit 17

Definition at line 6662 of file stm32f10x.h.

#define CAN_F4R1_FB18 ((uint32_t)0x00040000)

Filter bit 18

Definition at line 6663 of file stm32f10x.h.

#define CAN_F4R1_FB19 ((uint32_t)0x00080000)

Filter bit 19

Definition at line 6664 of file stm32f10x.h.

#define CAN_F4R1_FB2 ((uint32_t)0x00000004)

Filter bit 2

Definition at line 6647 of file stm32f10x.h.

#define CAN_F4R1_FB20 ((uint32_t)0x00100000)

Filter bit 20

Definition at line 6665 of file stm32f10x.h.

#define CAN_F4R1_FB21 ((uint32_t)0x00200000)

Filter bit 21

Definition at line 6666 of file stm32f10x.h.

#define CAN_F4R1_FB22 ((uint32_t)0x00400000)

Filter bit 22

Definition at line 6667 of file stm32f10x.h.

#define CAN_F4R1_FB23 ((uint32_t)0x00800000)

Filter bit 23

Definition at line 6668 of file stm32f10x.h.

#define CAN_F4R1_FB24 ((uint32_t)0x01000000)

Filter bit 24

Definition at line 6669 of file stm32f10x.h.

#define CAN_F4R1_FB25 ((uint32_t)0x02000000)

Filter bit 25

Definition at line 6670 of file stm32f10x.h.

#define CAN_F4R1_FB26 ((uint32_t)0x04000000)

Filter bit 26

Definition at line 6671 of file stm32f10x.h.

#define CAN_F4R1_FB27 ((uint32_t)0x08000000)

Filter bit 27

Definition at line 6672 of file stm32f10x.h.

#define CAN_F4R1_FB28 ((uint32_t)0x10000000)

Filter bit 28

Definition at line 6673 of file stm32f10x.h.

#define CAN_F4R1_FB29 ((uint32_t)0x20000000)

Filter bit 29

Definition at line 6674 of file stm32f10x.h.

#define CAN_F4R1_FB3 ((uint32_t)0x00000008)

Filter bit 3

Definition at line 6648 of file stm32f10x.h.

#define CAN_F4R1_FB30 ((uint32_t)0x40000000)

Filter bit 30

Definition at line 6675 of file stm32f10x.h.

#define CAN_F4R1_FB31 ((uint32_t)0x80000000)

Filter bit 31

Definition at line 6676 of file stm32f10x.h.

#define CAN_F4R1_FB4 ((uint32_t)0x00000010)

Filter bit 4

Definition at line 6649 of file stm32f10x.h.

#define CAN_F4R1_FB5 ((uint32_t)0x00000020)

Filter bit 5

Definition at line 6650 of file stm32f10x.h.

#define CAN_F4R1_FB6 ((uint32_t)0x00000040)

Filter bit 6

Definition at line 6651 of file stm32f10x.h.

#define CAN_F4R1_FB7 ((uint32_t)0x00000080)

Filter bit 7

Definition at line 6652 of file stm32f10x.h.

#define CAN_F4R1_FB8 ((uint32_t)0x00000100)

Filter bit 8

Definition at line 6653 of file stm32f10x.h.

#define CAN_F4R1_FB9 ((uint32_t)0x00000200)

Filter bit 9

Definition at line 6654 of file stm32f10x.h.

#define CAN_F4R2_FB0 ((uint32_t)0x00000001)

Filter bit 0

Definition at line 7121 of file stm32f10x.h.

#define CAN_F4R2_FB1 ((uint32_t)0x00000002)

Filter bit 1

Definition at line 7122 of file stm32f10x.h.

#define CAN_F4R2_FB10 ((uint32_t)0x00000400)

Filter bit 10

Definition at line 7131 of file stm32f10x.h.

#define CAN_F4R2_FB11 ((uint32_t)0x00000800)

Filter bit 11

Definition at line 7132 of file stm32f10x.h.

#define CAN_F4R2_FB12 ((uint32_t)0x00001000)

Filter bit 12

Definition at line 7133 of file stm32f10x.h.

#define CAN_F4R2_FB13 ((uint32_t)0x00002000)

Filter bit 13

Definition at line 7134 of file stm32f10x.h.

#define CAN_F4R2_FB14 ((uint32_t)0x00004000)

Filter bit 14

Definition at line 7135 of file stm32f10x.h.

#define CAN_F4R2_FB15 ((uint32_t)0x00008000)

Filter bit 15

Definition at line 7136 of file stm32f10x.h.

#define CAN_F4R2_FB16 ((uint32_t)0x00010000)

Filter bit 16

Definition at line 7137 of file stm32f10x.h.

#define CAN_F4R2_FB17 ((uint32_t)0x00020000)

Filter bit 17

Definition at line 7138 of file stm32f10x.h.

#define CAN_F4R2_FB18 ((uint32_t)0x00040000)

Filter bit 18

Definition at line 7139 of file stm32f10x.h.

#define CAN_F4R2_FB19 ((uint32_t)0x00080000)

Filter bit 19

Definition at line 7140 of file stm32f10x.h.

#define CAN_F4R2_FB2 ((uint32_t)0x00000004)

Filter bit 2

Definition at line 7123 of file stm32f10x.h.

#define CAN_F4R2_FB20 ((uint32_t)0x00100000)

Filter bit 20

Definition at line 7141 of file stm32f10x.h.

#define CAN_F4R2_FB21 ((uint32_t)0x00200000)

Filter bit 21

Definition at line 7142 of file stm32f10x.h.

#define CAN_F4R2_FB22 ((uint32_t)0x00400000)

Filter bit 22

Definition at line 7143 of file stm32f10x.h.

#define CAN_F4R2_FB23 ((uint32_t)0x00800000)

Filter bit 23

Definition at line 7144 of file stm32f10x.h.

#define CAN_F4R2_FB24 ((uint32_t)0x01000000)

Filter bit 24

Definition at line 7145 of file stm32f10x.h.

#define CAN_F4R2_FB25 ((uint32_t)0x02000000)

Filter bit 25

Definition at line 7146 of file stm32f10x.h.

#define CAN_F4R2_FB26 ((uint32_t)0x04000000)

Filter bit 26

Definition at line 7147 of file stm32f10x.h.

#define CAN_F4R2_FB27 ((uint32_t)0x08000000)

Filter bit 27

Definition at line 7148 of file stm32f10x.h.

#define CAN_F4R2_FB28 ((uint32_t)0x10000000)

Filter bit 28

Definition at line 7149 of file stm32f10x.h.

#define CAN_F4R2_FB29 ((uint32_t)0x20000000)

Filter bit 29

Definition at line 7150 of file stm32f10x.h.

#define CAN_F4R2_FB3 ((uint32_t)0x00000008)

Filter bit 3

Definition at line 7124 of file stm32f10x.h.

#define CAN_F4R2_FB30 ((uint32_t)0x40000000)

Filter bit 30

Definition at line 7151 of file stm32f10x.h.

#define CAN_F4R2_FB31 ((uint32_t)0x80000000)

Filter bit 31

Definition at line 7152 of file stm32f10x.h.

#define CAN_F4R2_FB4 ((uint32_t)0x00000010)

Filter bit 4

Definition at line 7125 of file stm32f10x.h.

#define CAN_F4R2_FB5 ((uint32_t)0x00000020)

Filter bit 5

Definition at line 7126 of file stm32f10x.h.

#define CAN_F4R2_FB6 ((uint32_t)0x00000040)

Filter bit 6

Definition at line 7127 of file stm32f10x.h.

#define CAN_F4R2_FB7 ((uint32_t)0x00000080)

Filter bit 7

Definition at line 7128 of file stm32f10x.h.

#define CAN_F4R2_FB8 ((uint32_t)0x00000100)

Filter bit 8

Definition at line 7129 of file stm32f10x.h.

#define CAN_F4R2_FB9 ((uint32_t)0x00000200)

Filter bit 9

Definition at line 7130 of file stm32f10x.h.

#define CAN_F5R1_FB0 ((uint32_t)0x00000001)

Filter bit 0

Definition at line 6679 of file stm32f10x.h.

#define CAN_F5R1_FB1 ((uint32_t)0x00000002)

Filter bit 1

Definition at line 6680 of file stm32f10x.h.

#define CAN_F5R1_FB10 ((uint32_t)0x00000400)

Filter bit 10

Definition at line 6689 of file stm32f10x.h.

#define CAN_F5R1_FB11 ((uint32_t)0x00000800)

Filter bit 11

Definition at line 6690 of file stm32f10x.h.

#define CAN_F5R1_FB12 ((uint32_t)0x00001000)

Filter bit 12

Definition at line 6691 of file stm32f10x.h.

#define CAN_F5R1_FB13 ((uint32_t)0x00002000)

Filter bit 13

Definition at line 6692 of file stm32f10x.h.

#define CAN_F5R1_FB14 ((uint32_t)0x00004000)

Filter bit 14

Definition at line 6693 of file stm32f10x.h.

#define CAN_F5R1_FB15 ((uint32_t)0x00008000)

Filter bit 15

Definition at line 6694 of file stm32f10x.h.

#define CAN_F5R1_FB16 ((uint32_t)0x00010000)

Filter bit 16

Definition at line 6695 of file stm32f10x.h.

#define CAN_F5R1_FB17 ((uint32_t)0x00020000)

Filter bit 17

Definition at line 6696 of file stm32f10x.h.

#define CAN_F5R1_FB18 ((uint32_t)0x00040000)

Filter bit 18

Definition at line 6697 of file stm32f10x.h.

#define CAN_F5R1_FB19 ((uint32_t)0x00080000)

Filter bit 19

Definition at line 6698 of file stm32f10x.h.

#define CAN_F5R1_FB2 ((uint32_t)0x00000004)

Filter bit 2

Definition at line 6681 of file stm32f10x.h.

#define CAN_F5R1_FB20 ((uint32_t)0x00100000)

Filter bit 20

Definition at line 6699 of file stm32f10x.h.

#define CAN_F5R1_FB21 ((uint32_t)0x00200000)

Filter bit 21

Definition at line 6700 of file stm32f10x.h.

#define CAN_F5R1_FB22 ((uint32_t)0x00400000)

Filter bit 22

Definition at line 6701 of file stm32f10x.h.

#define CAN_F5R1_FB23 ((uint32_t)0x00800000)

Filter bit 23

Definition at line 6702 of file stm32f10x.h.

#define CAN_F5R1_FB24 ((uint32_t)0x01000000)

Filter bit 24

Definition at line 6703 of file stm32f10x.h.

#define CAN_F5R1_FB25 ((uint32_t)0x02000000)

Filter bit 25

Definition at line 6704 of file stm32f10x.h.

#define CAN_F5R1_FB26 ((uint32_t)0x04000000)

Filter bit 26

Definition at line 6705 of file stm32f10x.h.

#define CAN_F5R1_FB27 ((uint32_t)0x08000000)

Filter bit 27

Definition at line 6706 of file stm32f10x.h.

#define CAN_F5R1_FB28 ((uint32_t)0x10000000)

Filter bit 28

Definition at line 6707 of file stm32f10x.h.

#define CAN_F5R1_FB29 ((uint32_t)0x20000000)

Filter bit 29

Definition at line 6708 of file stm32f10x.h.

#define CAN_F5R1_FB3 ((uint32_t)0x00000008)

Filter bit 3

Definition at line 6682 of file stm32f10x.h.

#define CAN_F5R1_FB30 ((uint32_t)0x40000000)

Filter bit 30

Definition at line 6709 of file stm32f10x.h.

#define CAN_F5R1_FB31 ((uint32_t)0x80000000)

Filter bit 31

Definition at line 6710 of file stm32f10x.h.

#define CAN_F5R1_FB4 ((uint32_t)0x00000010)

Filter bit 4

Definition at line 6683 of file stm32f10x.h.

#define CAN_F5R1_FB5 ((uint32_t)0x00000020)

Filter bit 5

Definition at line 6684 of file stm32f10x.h.

#define CAN_F5R1_FB6 ((uint32_t)0x00000040)

Filter bit 6

Definition at line 6685 of file stm32f10x.h.

#define CAN_F5R1_FB7 ((uint32_t)0x00000080)

Filter bit 7

Definition at line 6686 of file stm32f10x.h.

#define CAN_F5R1_FB8 ((uint32_t)0x00000100)

Filter bit 8

Definition at line 6687 of file stm32f10x.h.

#define CAN_F5R1_FB9 ((uint32_t)0x00000200)

Filter bit 9

Definition at line 6688 of file stm32f10x.h.

#define CAN_F5R2_FB0 ((uint32_t)0x00000001)

Filter bit 0

Definition at line 7155 of file stm32f10x.h.

#define CAN_F5R2_FB1 ((uint32_t)0x00000002)

Filter bit 1

Definition at line 7156 of file stm32f10x.h.

#define CAN_F5R2_FB10 ((uint32_t)0x00000400)

Filter bit 10

Definition at line 7165 of file stm32f10x.h.

#define CAN_F5R2_FB11 ((uint32_t)0x00000800)

Filter bit 11

Definition at line 7166 of file stm32f10x.h.

#define CAN_F5R2_FB12 ((uint32_t)0x00001000)

Filter bit 12

Definition at line 7167 of file stm32f10x.h.

#define CAN_F5R2_FB13 ((uint32_t)0x00002000)

Filter bit 13

Definition at line 7168 of file stm32f10x.h.

#define CAN_F5R2_FB14 ((uint32_t)0x00004000)

Filter bit 14

Definition at line 7169 of file stm32f10x.h.

#define CAN_F5R2_FB15 ((uint32_t)0x00008000)

Filter bit 15

Definition at line 7170 of file stm32f10x.h.

#define CAN_F5R2_FB16 ((uint32_t)0x00010000)

Filter bit 16

Definition at line 7171 of file stm32f10x.h.

#define CAN_F5R2_FB17 ((uint32_t)0x00020000)

Filter bit 17

Definition at line 7172 of file stm32f10x.h.

#define CAN_F5R2_FB18 ((uint32_t)0x00040000)

Filter bit 18

Definition at line 7173 of file stm32f10x.h.

#define CAN_F5R2_FB19 ((uint32_t)0x00080000)

Filter bit 19

Definition at line 7174 of file stm32f10x.h.

#define CAN_F5R2_FB2 ((uint32_t)0x00000004)

Filter bit 2

Definition at line 7157 of file stm32f10x.h.

#define CAN_F5R2_FB20 ((uint32_t)0x00100000)

Filter bit 20

Definition at line 7175 of file stm32f10x.h.

#define CAN_F5R2_FB21 ((uint32_t)0x00200000)

Filter bit 21

Definition at line 7176 of file stm32f10x.h.

#define CAN_F5R2_FB22 ((uint32_t)0x00400000)

Filter bit 22

Definition at line 7177 of file stm32f10x.h.

#define CAN_F5R2_FB23 ((uint32_t)0x00800000)

Filter bit 23

Definition at line 7178 of file stm32f10x.h.

#define CAN_F5R2_FB24 ((uint32_t)0x01000000)

Filter bit 24

Definition at line 7179 of file stm32f10x.h.

#define CAN_F5R2_FB25 ((uint32_t)0x02000000)

Filter bit 25

Definition at line 7180 of file stm32f10x.h.

#define CAN_F5R2_FB26 ((uint32_t)0x04000000)

Filter bit 26

Definition at line 7181 of file stm32f10x.h.

#define CAN_F5R2_FB27 ((uint32_t)0x08000000)

Filter bit 27

Definition at line 7182 of file stm32f10x.h.

#define CAN_F5R2_FB28 ((uint32_t)0x10000000)

Filter bit 28

Definition at line 7183 of file stm32f10x.h.

#define CAN_F5R2_FB29 ((uint32_t)0x20000000)

Filter bit 29

Definition at line 7184 of file stm32f10x.h.

#define CAN_F5R2_FB3 ((uint32_t)0x00000008)

Filter bit 3

Definition at line 7158 of file stm32f10x.h.

#define CAN_F5R2_FB30 ((uint32_t)0x40000000)

Filter bit 30

Definition at line 7185 of file stm32f10x.h.

#define CAN_F5R2_FB31 ((uint32_t)0x80000000)

Filter bit 31

Definition at line 7186 of file stm32f10x.h.

#define CAN_F5R2_FB4 ((uint32_t)0x00000010)

Filter bit 4

Definition at line 7159 of file stm32f10x.h.

#define CAN_F5R2_FB5 ((uint32_t)0x00000020)

Filter bit 5

Definition at line 7160 of file stm32f10x.h.

#define CAN_F5R2_FB6 ((uint32_t)0x00000040)

Filter bit 6

Definition at line 7161 of file stm32f10x.h.

#define CAN_F5R2_FB7 ((uint32_t)0x00000080)

Filter bit 7

Definition at line 7162 of file stm32f10x.h.

#define CAN_F5R2_FB8 ((uint32_t)0x00000100)

Filter bit 8

Definition at line 7163 of file stm32f10x.h.

#define CAN_F5R2_FB9 ((uint32_t)0x00000200)

Filter bit 9

Definition at line 7164 of file stm32f10x.h.

#define CAN_F6R1_FB0 ((uint32_t)0x00000001)

Filter bit 0

Definition at line 6713 of file stm32f10x.h.

#define CAN_F6R1_FB1 ((uint32_t)0x00000002)

Filter bit 1

Definition at line 6714 of file stm32f10x.h.

#define CAN_F6R1_FB10 ((uint32_t)0x00000400)

Filter bit 10

Definition at line 6723 of file stm32f10x.h.

#define CAN_F6R1_FB11 ((uint32_t)0x00000800)

Filter bit 11

Definition at line 6724 of file stm32f10x.h.

#define CAN_F6R1_FB12 ((uint32_t)0x00001000)

Filter bit 12

Definition at line 6725 of file stm32f10x.h.

#define CAN_F6R1_FB13 ((uint32_t)0x00002000)

Filter bit 13

Definition at line 6726 of file stm32f10x.h.

#define CAN_F6R1_FB14 ((uint32_t)0x00004000)

Filter bit 14

Definition at line 6727 of file stm32f10x.h.

#define CAN_F6R1_FB15 ((uint32_t)0x00008000)

Filter bit 15

Definition at line 6728 of file stm32f10x.h.

#define CAN_F6R1_FB16 ((uint32_t)0x00010000)

Filter bit 16

Definition at line 6729 of file stm32f10x.h.

#define CAN_F6R1_FB17 ((uint32_t)0x00020000)

Filter bit 17

Definition at line 6730 of file stm32f10x.h.

#define CAN_F6R1_FB18 ((uint32_t)0x00040000)

Filter bit 18

Definition at line 6731 of file stm32f10x.h.

#define CAN_F6R1_FB19 ((uint32_t)0x00080000)

Filter bit 19

Definition at line 6732 of file stm32f10x.h.

#define CAN_F6R1_FB2 ((uint32_t)0x00000004)

Filter bit 2

Definition at line 6715 of file stm32f10x.h.

#define CAN_F6R1_FB20 ((uint32_t)0x00100000)

Filter bit 20

Definition at line 6733 of file stm32f10x.h.

#define CAN_F6R1_FB21 ((uint32_t)0x00200000)

Filter bit 21

Definition at line 6734 of file stm32f10x.h.

#define CAN_F6R1_FB22 ((uint32_t)0x00400000)

Filter bit 22

Definition at line 6735 of file stm32f10x.h.

#define CAN_F6R1_FB23 ((uint32_t)0x00800000)

Filter bit 23

Definition at line 6736 of file stm32f10x.h.

#define CAN_F6R1_FB24 ((uint32_t)0x01000000)

Filter bit 24

Definition at line 6737 of file stm32f10x.h.

#define CAN_F6R1_FB25 ((uint32_t)0x02000000)

Filter bit 25

Definition at line 6738 of file stm32f10x.h.

#define CAN_F6R1_FB26 ((uint32_t)0x04000000)

Filter bit 26

Definition at line 6739 of file stm32f10x.h.

#define CAN_F6R1_FB27 ((uint32_t)0x08000000)

Filter bit 27

Definition at line 6740 of file stm32f10x.h.

#define CAN_F6R1_FB28 ((uint32_t)0x10000000)

Filter bit 28

Definition at line 6741 of file stm32f10x.h.

#define CAN_F6R1_FB29 ((uint32_t)0x20000000)

Filter bit 29

Definition at line 6742 of file stm32f10x.h.

#define CAN_F6R1_FB3 ((uint32_t)0x00000008)

Filter bit 3

Definition at line 6716 of file stm32f10x.h.

#define CAN_F6R1_FB30 ((uint32_t)0x40000000)

Filter bit 30

Definition at line 6743 of file stm32f10x.h.

#define CAN_F6R1_FB31 ((uint32_t)0x80000000)

Filter bit 31

Definition at line 6744 of file stm32f10x.h.

#define CAN_F6R1_FB4 ((uint32_t)0x00000010)

Filter bit 4

Definition at line 6717 of file stm32f10x.h.

#define CAN_F6R1_FB5 ((uint32_t)0x00000020)

Filter bit 5

Definition at line 6718 of file stm32f10x.h.

#define CAN_F6R1_FB6 ((uint32_t)0x00000040)

Filter bit 6

Definition at line 6719 of file stm32f10x.h.

#define CAN_F6R1_FB7 ((uint32_t)0x00000080)

Filter bit 7

Definition at line 6720 of file stm32f10x.h.

#define CAN_F6R1_FB8 ((uint32_t)0x00000100)

Filter bit 8

Definition at line 6721 of file stm32f10x.h.

#define CAN_F6R1_FB9 ((uint32_t)0x00000200)

Filter bit 9

Definition at line 6722 of file stm32f10x.h.

#define CAN_F6R2_FB0 ((uint32_t)0x00000001)

Filter bit 0

Definition at line 7189 of file stm32f10x.h.

#define CAN_F6R2_FB1 ((uint32_t)0x00000002)

Filter bit 1

Definition at line 7190 of file stm32f10x.h.

#define CAN_F6R2_FB10 ((uint32_t)0x00000400)

Filter bit 10

Definition at line 7199 of file stm32f10x.h.

#define CAN_F6R2_FB11 ((uint32_t)0x00000800)

Filter bit 11

Definition at line 7200 of file stm32f10x.h.

#define CAN_F6R2_FB12 ((uint32_t)0x00001000)

Filter bit 12

Definition at line 7201 of file stm32f10x.h.

#define CAN_F6R2_FB13 ((uint32_t)0x00002000)

Filter bit 13

Definition at line 7202 of file stm32f10x.h.

#define CAN_F6R2_FB14 ((uint32_t)0x00004000)

Filter bit 14

Definition at line 7203 of file stm32f10x.h.

#define CAN_F6R2_FB15 ((uint32_t)0x00008000)

Filter bit 15

Definition at line 7204 of file stm32f10x.h.

#define CAN_F6R2_FB16 ((uint32_t)0x00010000)

Filter bit 16

Definition at line 7205 of file stm32f10x.h.

#define CAN_F6R2_FB17 ((uint32_t)0x00020000)

Filter bit 17

Definition at line 7206 of file stm32f10x.h.

#define CAN_F6R2_FB18 ((uint32_t)0x00040000)

Filter bit 18

Definition at line 7207 of file stm32f10x.h.

#define CAN_F6R2_FB19 ((uint32_t)0x00080000)

Filter bit 19

Definition at line 7208 of file stm32f10x.h.

#define CAN_F6R2_FB2 ((uint32_t)0x00000004)

Filter bit 2

Definition at line 7191 of file stm32f10x.h.

#define CAN_F6R2_FB20 ((uint32_t)0x00100000)

Filter bit 20

Definition at line 7209 of file stm32f10x.h.

#define CAN_F6R2_FB21 ((uint32_t)0x00200000)

Filter bit 21

Definition at line 7210 of file stm32f10x.h.

#define CAN_F6R2_FB22 ((uint32_t)0x00400000)

Filter bit 22

Definition at line 7211 of file stm32f10x.h.

#define CAN_F6R2_FB23 ((uint32_t)0x00800000)

Filter bit 23

Definition at line 7212 of file stm32f10x.h.

#define CAN_F6R2_FB24 ((uint32_t)0x01000000)

Filter bit 24

Definition at line 7213 of file stm32f10x.h.

#define CAN_F6R2_FB25 ((uint32_t)0x02000000)

Filter bit 25

Definition at line 7214 of file stm32f10x.h.

#define CAN_F6R2_FB26 ((uint32_t)0x04000000)

Filter bit 26

Definition at line 7215 of file stm32f10x.h.

#define CAN_F6R2_FB27 ((uint32_t)0x08000000)

Filter bit 27

Definition at line 7216 of file stm32f10x.h.

#define CAN_F6R2_FB28 ((uint32_t)0x10000000)

Filter bit 28

Definition at line 7217 of file stm32f10x.h.

#define CAN_F6R2_FB29 ((uint32_t)0x20000000)

Filter bit 29

Definition at line 7218 of file stm32f10x.h.

#define CAN_F6R2_FB3 ((uint32_t)0x00000008)

Filter bit 3

Definition at line 7192 of file stm32f10x.h.

#define CAN_F6R2_FB30 ((uint32_t)0x40000000)

Filter bit 30

Definition at line 7219 of file stm32f10x.h.

#define CAN_F6R2_FB31 ((uint32_t)0x80000000)

Filter bit 31

Definition at line 7220 of file stm32f10x.h.

#define CAN_F6R2_FB4 ((uint32_t)0x00000010)

Filter bit 4

Definition at line 7193 of file stm32f10x.h.

#define CAN_F6R2_FB5 ((uint32_t)0x00000020)

Filter bit 5

Definition at line 7194 of file stm32f10x.h.

#define CAN_F6R2_FB6 ((uint32_t)0x00000040)

Filter bit 6

Definition at line 7195 of file stm32f10x.h.

#define CAN_F6R2_FB7 ((uint32_t)0x00000080)

Filter bit 7

Definition at line 7196 of file stm32f10x.h.

#define CAN_F6R2_FB8 ((uint32_t)0x00000100)

Filter bit 8

Definition at line 7197 of file stm32f10x.h.

#define CAN_F6R2_FB9 ((uint32_t)0x00000200)

Filter bit 9

Definition at line 7198 of file stm32f10x.h.

#define CAN_F7R1_FB0 ((uint32_t)0x00000001)

Filter bit 0

Definition at line 6747 of file stm32f10x.h.

#define CAN_F7R1_FB1 ((uint32_t)0x00000002)

Filter bit 1

Definition at line 6748 of file stm32f10x.h.

#define CAN_F7R1_FB10 ((uint32_t)0x00000400)

Filter bit 10

Definition at line 6757 of file stm32f10x.h.

#define CAN_F7R1_FB11 ((uint32_t)0x00000800)

Filter bit 11

Definition at line 6758 of file stm32f10x.h.

#define CAN_F7R1_FB12 ((uint32_t)0x00001000)

Filter bit 12

Definition at line 6759 of file stm32f10x.h.

#define CAN_F7R1_FB13 ((uint32_t)0x00002000)

Filter bit 13

Definition at line 6760 of file stm32f10x.h.

#define CAN_F7R1_FB14 ((uint32_t)0x00004000)

Filter bit 14

Definition at line 6761 of file stm32f10x.h.

#define CAN_F7R1_FB15 ((uint32_t)0x00008000)

Filter bit 15

Definition at line 6762 of file stm32f10x.h.

#define CAN_F7R1_FB16 ((uint32_t)0x00010000)

Filter bit 16

Definition at line 6763 of file stm32f10x.h.

#define CAN_F7R1_FB17 ((uint32_t)0x00020000)

Filter bit 17

Definition at line 6764 of file stm32f10x.h.

#define CAN_F7R1_FB18 ((uint32_t)0x00040000)

Filter bit 18

Definition at line 6765 of file stm32f10x.h.

#define CAN_F7R1_FB19 ((uint32_t)0x00080000)

Filter bit 19

Definition at line 6766 of file stm32f10x.h.

#define CAN_F7R1_FB2 ((uint32_t)0x00000004)

Filter bit 2

Definition at line 6749 of file stm32f10x.h.

#define CAN_F7R1_FB20 ((uint32_t)0x00100000)

Filter bit 20

Definition at line 6767 of file stm32f10x.h.

#define CAN_F7R1_FB21 ((uint32_t)0x00200000)

Filter bit 21

Definition at line 6768 of file stm32f10x.h.

#define CAN_F7R1_FB22 ((uint32_t)0x00400000)

Filter bit 22

Definition at line 6769 of file stm32f10x.h.

#define CAN_F7R1_FB23 ((uint32_t)0x00800000)

Filter bit 23

Definition at line 6770 of file stm32f10x.h.

#define CAN_F7R1_FB24 ((uint32_t)0x01000000)

Filter bit 24

Definition at line 6771 of file stm32f10x.h.

#define CAN_F7R1_FB25 ((uint32_t)0x02000000)

Filter bit 25

Definition at line 6772 of file stm32f10x.h.

#define CAN_F7R1_FB26 ((uint32_t)0x04000000)

Filter bit 26

Definition at line 6773 of file stm32f10x.h.

#define CAN_F7R1_FB27 ((uint32_t)0x08000000)

Filter bit 27

Definition at line 6774 of file stm32f10x.h.

#define CAN_F7R1_FB28 ((uint32_t)0x10000000)

Filter bit 28

Definition at line 6775 of file stm32f10x.h.

#define CAN_F7R1_FB29 ((uint32_t)0x20000000)

Filter bit 29

Definition at line 6776 of file stm32f10x.h.

#define CAN_F7R1_FB3 ((uint32_t)0x00000008)

Filter bit 3

Definition at line 6750 of file stm32f10x.h.

#define CAN_F7R1_FB30 ((uint32_t)0x40000000)

Filter bit 30

Definition at line 6777 of file stm32f10x.h.

#define CAN_F7R1_FB31 ((uint32_t)0x80000000)

Filter bit 31

Definition at line 6778 of file stm32f10x.h.

#define CAN_F7R1_FB4 ((uint32_t)0x00000010)

Filter bit 4

Definition at line 6751 of file stm32f10x.h.

#define CAN_F7R1_FB5 ((uint32_t)0x00000020)

Filter bit 5

Definition at line 6752 of file stm32f10x.h.

#define CAN_F7R1_FB6 ((uint32_t)0x00000040)

Filter bit 6

Definition at line 6753 of file stm32f10x.h.

#define CAN_F7R1_FB7 ((uint32_t)0x00000080)

Filter bit 7

Definition at line 6754 of file stm32f10x.h.

#define CAN_F7R1_FB8 ((uint32_t)0x00000100)

Filter bit 8

Definition at line 6755 of file stm32f10x.h.

#define CAN_F7R1_FB9 ((uint32_t)0x00000200)

Filter bit 9

Definition at line 6756 of file stm32f10x.h.

#define CAN_F7R2_FB0 ((uint32_t)0x00000001)

Filter bit 0

Definition at line 7223 of file stm32f10x.h.

#define CAN_F7R2_FB1 ((uint32_t)0x00000002)

Filter bit 1

Definition at line 7224 of file stm32f10x.h.

#define CAN_F7R2_FB10 ((uint32_t)0x00000400)

Filter bit 10

Definition at line 7233 of file stm32f10x.h.

#define CAN_F7R2_FB11 ((uint32_t)0x00000800)

Filter bit 11

Definition at line 7234 of file stm32f10x.h.

#define CAN_F7R2_FB12 ((uint32_t)0x00001000)

Filter bit 12

Definition at line 7235 of file stm32f10x.h.

#define CAN_F7R2_FB13 ((uint32_t)0x00002000)

Filter bit 13

Definition at line 7236 of file stm32f10x.h.

#define CAN_F7R2_FB14 ((uint32_t)0x00004000)

Filter bit 14

Definition at line 7237 of file stm32f10x.h.

#define CAN_F7R2_FB15 ((uint32_t)0x00008000)

Filter bit 15

Definition at line 7238 of file stm32f10x.h.

#define CAN_F7R2_FB16 ((uint32_t)0x00010000)

Filter bit 16

Definition at line 7239 of file stm32f10x.h.

#define CAN_F7R2_FB17 ((uint32_t)0x00020000)

Filter bit 17

Definition at line 7240 of file stm32f10x.h.

#define CAN_F7R2_FB18 ((uint32_t)0x00040000)

Filter bit 18

Definition at line 7241 of file stm32f10x.h.

#define CAN_F7R2_FB19 ((uint32_t)0x00080000)

Filter bit 19

Definition at line 7242 of file stm32f10x.h.

#define CAN_F7R2_FB2 ((uint32_t)0x00000004)

Filter bit 2

Definition at line 7225 of file stm32f10x.h.

#define CAN_F7R2_FB20 ((uint32_t)0x00100000)

Filter bit 20

Definition at line 7243 of file stm32f10x.h.

#define CAN_F7R2_FB21 ((uint32_t)0x00200000)

Filter bit 21

Definition at line 7244 of file stm32f10x.h.

#define CAN_F7R2_FB22 ((uint32_t)0x00400000)

Filter bit 22

Definition at line 7245 of file stm32f10x.h.

#define CAN_F7R2_FB23 ((uint32_t)0x00800000)

Filter bit 23

Definition at line 7246 of file stm32f10x.h.

#define CAN_F7R2_FB24 ((uint32_t)0x01000000)

Filter bit 24

Definition at line 7247 of file stm32f10x.h.

#define CAN_F7R2_FB25 ((uint32_t)0x02000000)

Filter bit 25

Definition at line 7248 of file stm32f10x.h.

#define CAN_F7R2_FB26 ((uint32_t)0x04000000)

Filter bit 26

Definition at line 7249 of file stm32f10x.h.

#define CAN_F7R2_FB27 ((uint32_t)0x08000000)

Filter bit 27

Definition at line 7250 of file stm32f10x.h.

#define CAN_F7R2_FB28 ((uint32_t)0x10000000)

Filter bit 28

Definition at line 7251 of file stm32f10x.h.

#define CAN_F7R2_FB29 ((uint32_t)0x20000000)

Filter bit 29

Definition at line 7252 of file stm32f10x.h.

#define CAN_F7R2_FB3 ((uint32_t)0x00000008)

Filter bit 3

Definition at line 7226 of file stm32f10x.h.

#define CAN_F7R2_FB30 ((uint32_t)0x40000000)

Filter bit 30

Definition at line 7253 of file stm32f10x.h.

#define CAN_F7R2_FB31 ((uint32_t)0x80000000)

Filter bit 31

Definition at line 7254 of file stm32f10x.h.

#define CAN_F7R2_FB4 ((uint32_t)0x00000010)

Filter bit 4

Definition at line 7227 of file stm32f10x.h.

#define CAN_F7R2_FB5 ((uint32_t)0x00000020)

Filter bit 5

Definition at line 7228 of file stm32f10x.h.

#define CAN_F7R2_FB6 ((uint32_t)0x00000040)

Filter bit 6

Definition at line 7229 of file stm32f10x.h.

#define CAN_F7R2_FB7 ((uint32_t)0x00000080)

Filter bit 7

Definition at line 7230 of file stm32f10x.h.

#define CAN_F7R2_FB8 ((uint32_t)0x00000100)

Filter bit 8

Definition at line 7231 of file stm32f10x.h.

#define CAN_F7R2_FB9 ((uint32_t)0x00000200)

Filter bit 9

Definition at line 7232 of file stm32f10x.h.

#define CAN_F8R1_FB0 ((uint32_t)0x00000001)

Filter bit 0

Definition at line 6781 of file stm32f10x.h.

#define CAN_F8R1_FB1 ((uint32_t)0x00000002)

Filter bit 1

Definition at line 6782 of file stm32f10x.h.

#define CAN_F8R1_FB10 ((uint32_t)0x00000400)

Filter bit 10

Definition at line 6791 of file stm32f10x.h.

#define CAN_F8R1_FB11 ((uint32_t)0x00000800)

Filter bit 11

Definition at line 6792 of file stm32f10x.h.

#define CAN_F8R1_FB12 ((uint32_t)0x00001000)

Filter bit 12

Definition at line 6793 of file stm32f10x.h.

#define CAN_F8R1_FB13 ((uint32_t)0x00002000)

Filter bit 13

Definition at line 6794 of file stm32f10x.h.

#define CAN_F8R1_FB14 ((uint32_t)0x00004000)

Filter bit 14

Definition at line 6795 of file stm32f10x.h.

#define CAN_F8R1_FB15 ((uint32_t)0x00008000)

Filter bit 15

Definition at line 6796 of file stm32f10x.h.

#define CAN_F8R1_FB16 ((uint32_t)0x00010000)

Filter bit 16

Definition at line 6797 of file stm32f10x.h.

#define CAN_F8R1_FB17 ((uint32_t)0x00020000)

Filter bit 17

Definition at line 6798 of file stm32f10x.h.

#define CAN_F8R1_FB18 ((uint32_t)0x00040000)

Filter bit 18

Definition at line 6799 of file stm32f10x.h.

#define CAN_F8R1_FB19 ((uint32_t)0x00080000)

Filter bit 19

Definition at line 6800 of file stm32f10x.h.

#define CAN_F8R1_FB2 ((uint32_t)0x00000004)

Filter bit 2

Definition at line 6783 of file stm32f10x.h.

#define CAN_F8R1_FB20 ((uint32_t)0x00100000)

Filter bit 20

Definition at line 6801 of file stm32f10x.h.

#define CAN_F8R1_FB21 ((uint32_t)0x00200000)

Filter bit 21

Definition at line 6802 of file stm32f10x.h.

#define CAN_F8R1_FB22 ((uint32_t)0x00400000)

Filter bit 22

Definition at line 6803 of file stm32f10x.h.

#define CAN_F8R1_FB23 ((uint32_t)0x00800000)

Filter bit 23

Definition at line 6804 of file stm32f10x.h.

#define CAN_F8R1_FB24 ((uint32_t)0x01000000)

Filter bit 24

Definition at line 6805 of file stm32f10x.h.

#define CAN_F8R1_FB25 ((uint32_t)0x02000000)

Filter bit 25

Definition at line 6806 of file stm32f10x.h.

#define CAN_F8R1_FB26 ((uint32_t)0x04000000)

Filter bit 26

Definition at line 6807 of file stm32f10x.h.

#define CAN_F8R1_FB27 ((uint32_t)0x08000000)

Filter bit 27

Definition at line 6808 of file stm32f10x.h.

#define CAN_F8R1_FB28 ((uint32_t)0x10000000)

Filter bit 28

Definition at line 6809 of file stm32f10x.h.

#define CAN_F8R1_FB29 ((uint32_t)0x20000000)

Filter bit 29

Definition at line 6810 of file stm32f10x.h.

#define CAN_F8R1_FB3 ((uint32_t)0x00000008)

Filter bit 3

Definition at line 6784 of file stm32f10x.h.

#define CAN_F8R1_FB30 ((uint32_t)0x40000000)

Filter bit 30

Definition at line 6811 of file stm32f10x.h.

#define CAN_F8R1_FB31 ((uint32_t)0x80000000)

Filter bit 31

Definition at line 6812 of file stm32f10x.h.

#define CAN_F8R1_FB4 ((uint32_t)0x00000010)

Filter bit 4

Definition at line 6785 of file stm32f10x.h.

#define CAN_F8R1_FB5 ((uint32_t)0x00000020)

Filter bit 5

Definition at line 6786 of file stm32f10x.h.

#define CAN_F8R1_FB6 ((uint32_t)0x00000040)

Filter bit 6

Definition at line 6787 of file stm32f10x.h.

#define CAN_F8R1_FB7 ((uint32_t)0x00000080)

Filter bit 7

Definition at line 6788 of file stm32f10x.h.

#define CAN_F8R1_FB8 ((uint32_t)0x00000100)

Filter bit 8

Definition at line 6789 of file stm32f10x.h.

#define CAN_F8R1_FB9 ((uint32_t)0x00000200)

Filter bit 9

Definition at line 6790 of file stm32f10x.h.

#define CAN_F8R2_FB0 ((uint32_t)0x00000001)

Filter bit 0

Definition at line 7257 of file stm32f10x.h.

#define CAN_F8R2_FB1 ((uint32_t)0x00000002)

Filter bit 1

Definition at line 7258 of file stm32f10x.h.

#define CAN_F8R2_FB10 ((uint32_t)0x00000400)

Filter bit 10

Definition at line 7267 of file stm32f10x.h.

#define CAN_F8R2_FB11 ((uint32_t)0x00000800)

Filter bit 11

Definition at line 7268 of file stm32f10x.h.

#define CAN_F8R2_FB12 ((uint32_t)0x00001000)

Filter bit 12

Definition at line 7269 of file stm32f10x.h.

#define CAN_F8R2_FB13 ((uint32_t)0x00002000)

Filter bit 13

Definition at line 7270 of file stm32f10x.h.

#define CAN_F8R2_FB14 ((uint32_t)0x00004000)

Filter bit 14

Definition at line 7271 of file stm32f10x.h.

#define CAN_F8R2_FB15 ((uint32_t)0x00008000)

Filter bit 15

Definition at line 7272 of file stm32f10x.h.

#define CAN_F8R2_FB16 ((uint32_t)0x00010000)

Filter bit 16

Definition at line 7273 of file stm32f10x.h.

#define CAN_F8R2_FB17 ((uint32_t)0x00020000)

Filter bit 17

Definition at line 7274 of file stm32f10x.h.

#define CAN_F8R2_FB18 ((uint32_t)0x00040000)

Filter bit 18

Definition at line 7275 of file stm32f10x.h.

#define CAN_F8R2_FB19 ((uint32_t)0x00080000)

Filter bit 19

Definition at line 7276 of file stm32f10x.h.

#define CAN_F8R2_FB2 ((uint32_t)0x00000004)

Filter bit 2

Definition at line 7259 of file stm32f10x.h.

#define CAN_F8R2_FB20 ((uint32_t)0x00100000)

Filter bit 20

Definition at line 7277 of file stm32f10x.h.

#define CAN_F8R2_FB21 ((uint32_t)0x00200000)

Filter bit 21

Definition at line 7278 of file stm32f10x.h.

#define CAN_F8R2_FB22 ((uint32_t)0x00400000)

Filter bit 22

Definition at line 7279 of file stm32f10x.h.

#define CAN_F8R2_FB23 ((uint32_t)0x00800000)

Filter bit 23

Definition at line 7280 of file stm32f10x.h.

#define CAN_F8R2_FB24 ((uint32_t)0x01000000)

Filter bit 24

Definition at line 7281 of file stm32f10x.h.

#define CAN_F8R2_FB25 ((uint32_t)0x02000000)

Filter bit 25

Definition at line 7282 of file stm32f10x.h.

#define CAN_F8R2_FB26 ((uint32_t)0x04000000)

Filter bit 26

Definition at line 7283 of file stm32f10x.h.

#define CAN_F8R2_FB27 ((uint32_t)0x08000000)

Filter bit 27

Definition at line 7284 of file stm32f10x.h.

#define CAN_F8R2_FB28 ((uint32_t)0x10000000)

Filter bit 28

Definition at line 7285 of file stm32f10x.h.

#define CAN_F8R2_FB29 ((uint32_t)0x20000000)

Filter bit 29

Definition at line 7286 of file stm32f10x.h.

#define CAN_F8R2_FB3 ((uint32_t)0x00000008)

Filter bit 3

Definition at line 7260 of file stm32f10x.h.

#define CAN_F8R2_FB30 ((uint32_t)0x40000000)

Filter bit 30

Definition at line 7287 of file stm32f10x.h.

#define CAN_F8R2_FB31 ((uint32_t)0x80000000)

Filter bit 31

Definition at line 7288 of file stm32f10x.h.

#define CAN_F8R2_FB4 ((uint32_t)0x00000010)

Filter bit 4

Definition at line 7261 of file stm32f10x.h.

#define CAN_F8R2_FB5 ((uint32_t)0x00000020)

Filter bit 5

Definition at line 7262 of file stm32f10x.h.

#define CAN_F8R2_FB6 ((uint32_t)0x00000040)

Filter bit 6

Definition at line 7263 of file stm32f10x.h.

#define CAN_F8R2_FB7 ((uint32_t)0x00000080)

Filter bit 7

Definition at line 7264 of file stm32f10x.h.

#define CAN_F8R2_FB8 ((uint32_t)0x00000100)

Filter bit 8

Definition at line 7265 of file stm32f10x.h.

#define CAN_F8R2_FB9 ((uint32_t)0x00000200)

Filter bit 9

Definition at line 7266 of file stm32f10x.h.

#define CAN_F9R1_FB0 ((uint32_t)0x00000001)

Filter bit 0

Definition at line 6815 of file stm32f10x.h.

#define CAN_F9R1_FB1 ((uint32_t)0x00000002)

Filter bit 1

Definition at line 6816 of file stm32f10x.h.

#define CAN_F9R1_FB10 ((uint32_t)0x00000400)

Filter bit 10

Definition at line 6825 of file stm32f10x.h.

#define CAN_F9R1_FB11 ((uint32_t)0x00000800)

Filter bit 11

Definition at line 6826 of file stm32f10x.h.

#define CAN_F9R1_FB12 ((uint32_t)0x00001000)

Filter bit 12

Definition at line 6827 of file stm32f10x.h.

#define CAN_F9R1_FB13 ((uint32_t)0x00002000)

Filter bit 13

Definition at line 6828 of file stm32f10x.h.

#define CAN_F9R1_FB14 ((uint32_t)0x00004000)

Filter bit 14

Definition at line 6829 of file stm32f10x.h.

#define CAN_F9R1_FB15 ((uint32_t)0x00008000)

Filter bit 15

Definition at line 6830 of file stm32f10x.h.

#define CAN_F9R1_FB16 ((uint32_t)0x00010000)

Filter bit 16

Definition at line 6831 of file stm32f10x.h.

#define CAN_F9R1_FB17 ((uint32_t)0x00020000)

Filter bit 17

Definition at line 6832 of file stm32f10x.h.

#define CAN_F9R1_FB18 ((uint32_t)0x00040000)

Filter bit 18

Definition at line 6833 of file stm32f10x.h.

#define CAN_F9R1_FB19 ((uint32_t)0x00080000)

Filter bit 19

Definition at line 6834 of file stm32f10x.h.

#define CAN_F9R1_FB2 ((uint32_t)0x00000004)

Filter bit 2

Definition at line 6817 of file stm32f10x.h.

#define CAN_F9R1_FB20 ((uint32_t)0x00100000)

Filter bit 20

Definition at line 6835 of file stm32f10x.h.

#define CAN_F9R1_FB21 ((uint32_t)0x00200000)

Filter bit 21

Definition at line 6836 of file stm32f10x.h.

#define CAN_F9R1_FB22 ((uint32_t)0x00400000)

Filter bit 22

Definition at line 6837 of file stm32f10x.h.

#define CAN_F9R1_FB23 ((uint32_t)0x00800000)

Filter bit 23

Definition at line 6838 of file stm32f10x.h.

#define CAN_F9R1_FB24 ((uint32_t)0x01000000)

Filter bit 24

Definition at line 6839 of file stm32f10x.h.

#define CAN_F9R1_FB25 ((uint32_t)0x02000000)

Filter bit 25

Definition at line 6840 of file stm32f10x.h.

#define CAN_F9R1_FB26 ((uint32_t)0x04000000)

Filter bit 26

Definition at line 6841 of file stm32f10x.h.

#define CAN_F9R1_FB27 ((uint32_t)0x08000000)

Filter bit 27

Definition at line 6842 of file stm32f10x.h.

#define CAN_F9R1_FB28 ((uint32_t)0x10000000)

Filter bit 28

Definition at line 6843 of file stm32f10x.h.

#define CAN_F9R1_FB29 ((uint32_t)0x20000000)

Filter bit 29

Definition at line 6844 of file stm32f10x.h.

#define CAN_F9R1_FB3 ((uint32_t)0x00000008)

Filter bit 3

Definition at line 6818 of file stm32f10x.h.

#define CAN_F9R1_FB30 ((uint32_t)0x40000000)

Filter bit 30

Definition at line 6845 of file stm32f10x.h.

#define CAN_F9R1_FB31 ((uint32_t)0x80000000)

Filter bit 31

Definition at line 6846 of file stm32f10x.h.

#define CAN_F9R1_FB4 ((uint32_t)0x00000010)

Filter bit 4

Definition at line 6819 of file stm32f10x.h.

#define CAN_F9R1_FB5 ((uint32_t)0x00000020)

Filter bit 5

Definition at line 6820 of file stm32f10x.h.

#define CAN_F9R1_FB6 ((uint32_t)0x00000040)

Filter bit 6

Definition at line 6821 of file stm32f10x.h.

#define CAN_F9R1_FB7 ((uint32_t)0x00000080)

Filter bit 7

Definition at line 6822 of file stm32f10x.h.

#define CAN_F9R1_FB8 ((uint32_t)0x00000100)

Filter bit 8

Definition at line 6823 of file stm32f10x.h.

#define CAN_F9R1_FB9 ((uint32_t)0x00000200)

Filter bit 9

Definition at line 6824 of file stm32f10x.h.

#define CAN_F9R2_FB0 ((uint32_t)0x00000001)

Filter bit 0

Definition at line 7291 of file stm32f10x.h.

#define CAN_F9R2_FB1 ((uint32_t)0x00000002)

Filter bit 1

Definition at line 7292 of file stm32f10x.h.

#define CAN_F9R2_FB10 ((uint32_t)0x00000400)

Filter bit 10

Definition at line 7301 of file stm32f10x.h.

#define CAN_F9R2_FB11 ((uint32_t)0x00000800)

Filter bit 11

Definition at line 7302 of file stm32f10x.h.

#define CAN_F9R2_FB12 ((uint32_t)0x00001000)

Filter bit 12

Definition at line 7303 of file stm32f10x.h.

#define CAN_F9R2_FB13 ((uint32_t)0x00002000)

Filter bit 13

Definition at line 7304 of file stm32f10x.h.

#define CAN_F9R2_FB14 ((uint32_t)0x00004000)

Filter bit 14

Definition at line 7305 of file stm32f10x.h.

#define CAN_F9R2_FB15 ((uint32_t)0x00008000)

Filter bit 15

Definition at line 7306 of file stm32f10x.h.

#define CAN_F9R2_FB16 ((uint32_t)0x00010000)

Filter bit 16

Definition at line 7307 of file stm32f10x.h.

#define CAN_F9R2_FB17 ((uint32_t)0x00020000)

Filter bit 17

Definition at line 7308 of file stm32f10x.h.

#define CAN_F9R2_FB18 ((uint32_t)0x00040000)

Filter bit 18

Definition at line 7309 of file stm32f10x.h.

#define CAN_F9R2_FB19 ((uint32_t)0x00080000)

Filter bit 19

Definition at line 7310 of file stm32f10x.h.

#define CAN_F9R2_FB2 ((uint32_t)0x00000004)

Filter bit 2

Definition at line 7293 of file stm32f10x.h.

#define CAN_F9R2_FB20 ((uint32_t)0x00100000)

Filter bit 20

Definition at line 7311 of file stm32f10x.h.

#define CAN_F9R2_FB21 ((uint32_t)0x00200000)

Filter bit 21

Definition at line 7312 of file stm32f10x.h.

#define CAN_F9R2_FB22 ((uint32_t)0x00400000)

Filter bit 22

Definition at line 7313 of file stm32f10x.h.

#define CAN_F9R2_FB23 ((uint32_t)0x00800000)

Filter bit 23

Definition at line 7314 of file stm32f10x.h.

#define CAN_F9R2_FB24 ((uint32_t)0x01000000)

Filter bit 24

Definition at line 7315 of file stm32f10x.h.

#define CAN_F9R2_FB25 ((uint32_t)0x02000000)

Filter bit 25

Definition at line 7316 of file stm32f10x.h.

#define CAN_F9R2_FB26 ((uint32_t)0x04000000)

Filter bit 26

Definition at line 7317 of file stm32f10x.h.

#define CAN_F9R2_FB27 ((uint32_t)0x08000000)

Filter bit 27

Definition at line 7318 of file stm32f10x.h.

#define CAN_F9R2_FB28 ((uint32_t)0x10000000)

Filter bit 28

Definition at line 7319 of file stm32f10x.h.

#define CAN_F9R2_FB29 ((uint32_t)0x20000000)

Filter bit 29

Definition at line 7320 of file stm32f10x.h.

#define CAN_F9R2_FB3 ((uint32_t)0x00000008)

Filter bit 3

Definition at line 7294 of file stm32f10x.h.

#define CAN_F9R2_FB30 ((uint32_t)0x40000000)

Filter bit 30

Definition at line 7321 of file stm32f10x.h.

#define CAN_F9R2_FB31 ((uint32_t)0x80000000)

Filter bit 31

Definition at line 7322 of file stm32f10x.h.

#define CAN_F9R2_FB4 ((uint32_t)0x00000010)

Filter bit 4

Definition at line 7295 of file stm32f10x.h.

#define CAN_F9R2_FB5 ((uint32_t)0x00000020)

Filter bit 5

Definition at line 7296 of file stm32f10x.h.

#define CAN_F9R2_FB6 ((uint32_t)0x00000040)

Filter bit 6

Definition at line 7297 of file stm32f10x.h.

#define CAN_F9R2_FB7 ((uint32_t)0x00000080)

Filter bit 7

Definition at line 7298 of file stm32f10x.h.

#define CAN_F9R2_FB8 ((uint32_t)0x00000100)

Filter bit 8

Definition at line 7299 of file stm32f10x.h.

#define CAN_F9R2_FB9 ((uint32_t)0x00000200)

Filter bit 9

Definition at line 7300 of file stm32f10x.h.

#define CAN_FA1R_FACT ((uint16_t)0x3FFF)

Filter Active

Definition at line 6492 of file stm32f10x.h.

#define CAN_FA1R_FACT0 ((uint16_t)0x0001)

Filter 0 Active

Definition at line 6493 of file stm32f10x.h.

#define CAN_FA1R_FACT1 ((uint16_t)0x0002)

Filter 1 Active

Definition at line 6494 of file stm32f10x.h.

#define CAN_FA1R_FACT10 ((uint16_t)0x0400)

Filter 10 Active

Definition at line 6503 of file stm32f10x.h.

#define CAN_FA1R_FACT11 ((uint16_t)0x0800)

Filter 11 Active

Definition at line 6504 of file stm32f10x.h.

#define CAN_FA1R_FACT12 ((uint16_t)0x1000)

Filter 12 Active

Definition at line 6505 of file stm32f10x.h.

#define CAN_FA1R_FACT13 ((uint16_t)0x2000)

Filter 13 Active

Definition at line 6506 of file stm32f10x.h.

#define CAN_FA1R_FACT2 ((uint16_t)0x0004)

Filter 2 Active

Definition at line 6495 of file stm32f10x.h.

#define CAN_FA1R_FACT3 ((uint16_t)0x0008)

Filter 3 Active

Definition at line 6496 of file stm32f10x.h.

#define CAN_FA1R_FACT4 ((uint16_t)0x0010)

Filter 4 Active

Definition at line 6497 of file stm32f10x.h.

#define CAN_FA1R_FACT5 ((uint16_t)0x0020)

Filter 5 Active

Definition at line 6498 of file stm32f10x.h.

#define CAN_FA1R_FACT6 ((uint16_t)0x0040)

Filter 6 Active

Definition at line 6499 of file stm32f10x.h.

#define CAN_FA1R_FACT7 ((uint16_t)0x0080)

Filter 7 Active

Definition at line 6500 of file stm32f10x.h.

#define CAN_FA1R_FACT8 ((uint16_t)0x0100)

Filter 8 Active

Definition at line 6501 of file stm32f10x.h.

#define CAN_FA1R_FACT9 ((uint16_t)0x0200)

Filter 9 Active

Definition at line 6502 of file stm32f10x.h.

#define CAN_FFA1R_FFA ((uint16_t)0x3FFF)

Filter FIFO Assignment

Definition at line 6475 of file stm32f10x.h.

#define CAN_FFA1R_FFA0 ((uint16_t)0x0001)

Filter FIFO Assignment for Filter 0

Definition at line 6476 of file stm32f10x.h.

#define CAN_FFA1R_FFA1 ((uint16_t)0x0002)

Filter FIFO Assignment for Filter 1

Definition at line 6477 of file stm32f10x.h.

#define CAN_FFA1R_FFA10 ((uint16_t)0x0400)

Filter FIFO Assignment for Filter 10

Definition at line 6486 of file stm32f10x.h.

#define CAN_FFA1R_FFA11 ((uint16_t)0x0800)

Filter FIFO Assignment for Filter 11

Definition at line 6487 of file stm32f10x.h.

#define CAN_FFA1R_FFA12 ((uint16_t)0x1000)

Filter FIFO Assignment for Filter 12

Definition at line 6488 of file stm32f10x.h.

#define CAN_FFA1R_FFA13 ((uint16_t)0x2000)

Filter FIFO Assignment for Filter 13

Definition at line 6489 of file stm32f10x.h.

#define CAN_FFA1R_FFA2 ((uint16_t)0x0004)

Filter FIFO Assignment for Filter 2

Definition at line 6478 of file stm32f10x.h.

#define CAN_FFA1R_FFA3 ((uint16_t)0x0008)

Filter FIFO Assignment for Filter 3

Definition at line 6479 of file stm32f10x.h.

#define CAN_FFA1R_FFA4 ((uint16_t)0x0010)

Filter FIFO Assignment for Filter 4

Definition at line 6480 of file stm32f10x.h.

#define CAN_FFA1R_FFA5 ((uint16_t)0x0020)

Filter FIFO Assignment for Filter 5

Definition at line 6481 of file stm32f10x.h.

#define CAN_FFA1R_FFA6 ((uint16_t)0x0040)

Filter FIFO Assignment for Filter 6

Definition at line 6482 of file stm32f10x.h.

#define CAN_FFA1R_FFA7 ((uint16_t)0x0080)

Filter FIFO Assignment for Filter 7

Definition at line 6483 of file stm32f10x.h.

#define CAN_FFA1R_FFA8 ((uint16_t)0x0100)

Filter FIFO Assignment for Filter 8

Definition at line 6484 of file stm32f10x.h.

#define CAN_FFA1R_FFA9 ((uint16_t)0x0200)

Filter FIFO Assignment for Filter 9

Definition at line 6485 of file stm32f10x.h.

#define CAN_FM1R_FBM ((uint16_t)0x3FFF)

Filter Mode

Definition at line 6441 of file stm32f10x.h.

#define CAN_FM1R_FBM0 ((uint16_t)0x0001)

Filter Init Mode bit 0

Definition at line 6442 of file stm32f10x.h.

#define CAN_FM1R_FBM1 ((uint16_t)0x0002)

Filter Init Mode bit 1

Definition at line 6443 of file stm32f10x.h.

#define CAN_FM1R_FBM10 ((uint16_t)0x0400)

Filter Init Mode bit 10

Definition at line 6452 of file stm32f10x.h.

#define CAN_FM1R_FBM11 ((uint16_t)0x0800)

Filter Init Mode bit 11

Definition at line 6453 of file stm32f10x.h.

#define CAN_FM1R_FBM12 ((uint16_t)0x1000)

Filter Init Mode bit 12

Definition at line 6454 of file stm32f10x.h.

#define CAN_FM1R_FBM13 ((uint16_t)0x2000)

Filter Init Mode bit 13

Definition at line 6455 of file stm32f10x.h.

#define CAN_FM1R_FBM2 ((uint16_t)0x0004)

Filter Init Mode bit 2

Definition at line 6444 of file stm32f10x.h.

#define CAN_FM1R_FBM3 ((uint16_t)0x0008)

Filter Init Mode bit 3

Definition at line 6445 of file stm32f10x.h.

#define CAN_FM1R_FBM4 ((uint16_t)0x0010)

Filter Init Mode bit 4

Definition at line 6446 of file stm32f10x.h.

#define CAN_FM1R_FBM5 ((uint16_t)0x0020)

Filter Init Mode bit 5

Definition at line 6447 of file stm32f10x.h.

#define CAN_FM1R_FBM6 ((uint16_t)0x0040)

Filter Init Mode bit 6

Definition at line 6448 of file stm32f10x.h.

#define CAN_FM1R_FBM7 ((uint16_t)0x0080)

Filter Init Mode bit 7

Definition at line 6449 of file stm32f10x.h.

#define CAN_FM1R_FBM8 ((uint16_t)0x0100)

Filter Init Mode bit 8

Definition at line 6450 of file stm32f10x.h.

#define CAN_FM1R_FBM9 ((uint16_t)0x0200)

Filter Init Mode bit 9

Definition at line 6451 of file stm32f10x.h.

#define CAN_FMR_FINIT ((uint8_t)0x01)

Filter Init Mode

Definition at line 6438 of file stm32f10x.h.

#define CAN_FS1R_FSC ((uint16_t)0x3FFF)

Filter Scale Configuration

Definition at line 6458 of file stm32f10x.h.

#define CAN_FS1R_FSC0 ((uint16_t)0x0001)

Filter Scale Configuration bit 0

Definition at line 6459 of file stm32f10x.h.

#define CAN_FS1R_FSC1 ((uint16_t)0x0002)

Filter Scale Configuration bit 1

Definition at line 6460 of file stm32f10x.h.

#define CAN_FS1R_FSC10 ((uint16_t)0x0400)

Filter Scale Configuration bit 10

Definition at line 6469 of file stm32f10x.h.

#define CAN_FS1R_FSC11 ((uint16_t)0x0800)

Filter Scale Configuration bit 11

Definition at line 6470 of file stm32f10x.h.

#define CAN_FS1R_FSC12 ((uint16_t)0x1000)

Filter Scale Configuration bit 12

Definition at line 6471 of file stm32f10x.h.

#define CAN_FS1R_FSC13 ((uint16_t)0x2000)

Filter Scale Configuration bit 13

Definition at line 6472 of file stm32f10x.h.

#define CAN_FS1R_FSC2 ((uint16_t)0x0004)

Filter Scale Configuration bit 2

Definition at line 6461 of file stm32f10x.h.

#define CAN_FS1R_FSC3 ((uint16_t)0x0008)

Filter Scale Configuration bit 3

Definition at line 6462 of file stm32f10x.h.

#define CAN_FS1R_FSC4 ((uint16_t)0x0010)

Filter Scale Configuration bit 4

Definition at line 6463 of file stm32f10x.h.

#define CAN_FS1R_FSC5 ((uint16_t)0x0020)

Filter Scale Configuration bit 5

Definition at line 6464 of file stm32f10x.h.

#define CAN_FS1R_FSC6 ((uint16_t)0x0040)

Filter Scale Configuration bit 6

Definition at line 6465 of file stm32f10x.h.

#define CAN_FS1R_FSC7 ((uint16_t)0x0080)

Filter Scale Configuration bit 7

Definition at line 6466 of file stm32f10x.h.

#define CAN_FS1R_FSC8 ((uint16_t)0x0100)

Filter Scale Configuration bit 8

Definition at line 6467 of file stm32f10x.h.

#define CAN_FS1R_FSC9 ((uint16_t)0x0200)

Filter Scale Configuration bit 9

Definition at line 6468 of file stm32f10x.h.

#define CAN_IER_BOFIE ((uint32_t)0x00000400)

Bus-Off Interrupt Enable

Definition at line 6290 of file stm32f10x.h.

#define CAN_IER_EPVIE ((uint32_t)0x00000200)

Error Passive Interrupt Enable

Definition at line 6289 of file stm32f10x.h.

#define CAN_IER_ERRIE ((uint32_t)0x00008000)

Error Interrupt Enable

Definition at line 6292 of file stm32f10x.h.

#define CAN_IER_EWGIE ((uint32_t)0x00000100)

Error Warning Interrupt Enable

Definition at line 6288 of file stm32f10x.h.

#define CAN_IER_FFIE0 ((uint32_t)0x00000004)

FIFO Full Interrupt Enable

Definition at line 6283 of file stm32f10x.h.

#define CAN_IER_FFIE1 ((uint32_t)0x00000020)

FIFO Full Interrupt Enable

Definition at line 6286 of file stm32f10x.h.

#define CAN_IER_FMPIE0 ((uint32_t)0x00000002)

FIFO Message Pending Interrupt Enable

Definition at line 6282 of file stm32f10x.h.

#define CAN_IER_FMPIE1 ((uint32_t)0x00000010)

FIFO Message Pending Interrupt Enable

Definition at line 6285 of file stm32f10x.h.

#define CAN_IER_FOVIE0 ((uint32_t)0x00000008)

FIFO Overrun Interrupt Enable

Definition at line 6284 of file stm32f10x.h.

#define CAN_IER_FOVIE1 ((uint32_t)0x00000040)

FIFO Overrun Interrupt Enable

Definition at line 6287 of file stm32f10x.h.

#define CAN_IER_LECIE ((uint32_t)0x00000800)

Last Error Code Interrupt Enable

Definition at line 6291 of file stm32f10x.h.

#define CAN_IER_SLKIE ((uint32_t)0x00020000)

Sleep Interrupt Enable

Definition at line 6294 of file stm32f10x.h.

#define CAN_IER_TMEIE ((uint32_t)0x00000001)

Transmit Mailbox Empty Interrupt Enable

Definition at line 6281 of file stm32f10x.h.

#define CAN_IER_WKUIE ((uint32_t)0x00010000)

Wakeup Interrupt Enable

Definition at line 6293 of file stm32f10x.h.

#define CAN_MCR_ABOM ((uint16_t)0x0040)

Automatic Bus-Off Management

Definition at line 6225 of file stm32f10x.h.

Referenced by CAN_Init().

#define CAN_MCR_AWUM ((uint16_t)0x0020)

Automatic Wakeup Mode

Definition at line 6224 of file stm32f10x.h.

Referenced by CAN_Init().

#define CAN_MCR_INRQ ((uint16_t)0x0001)

< CAN control and status registers Initialization Request

Definition at line 6219 of file stm32f10x.h.

Referenced by CAN_Init(), CAN_OperatingModeRequest(), and CAN_Sleep().

#define CAN_MCR_NART ((uint16_t)0x0010)

No Automatic Retransmission

Definition at line 6223 of file stm32f10x.h.

Referenced by CAN_Init().

#define CAN_MCR_RESET ((uint16_t)0x8000)

CAN software master reset

Definition at line 6227 of file stm32f10x.h.

#define CAN_MCR_RFLM ((uint16_t)0x0008)

Receive FIFO Locked Mode

Definition at line 6222 of file stm32f10x.h.

Referenced by CAN_Init().

#define CAN_MCR_SLEEP ((uint16_t)0x0002)

Sleep Mode Request

Definition at line 6220 of file stm32f10x.h.

Referenced by CAN_Init(), CAN_OperatingModeRequest(), CAN_Sleep(), and CAN_WakeUp().

#define CAN_MCR_TTCM ((uint16_t)0x0080)

Time Triggered Communication Mode

Definition at line 6226 of file stm32f10x.h.

Referenced by CAN_Init(), and CAN_TTComModeCmd().

#define CAN_MCR_TXFP ((uint16_t)0x0004)

Transmit FIFO Priority

Definition at line 6221 of file stm32f10x.h.

Referenced by CAN_Init().

#define CAN_MSR_ERRI ((uint16_t)0x0004)

Error Interrupt

Definition at line 6232 of file stm32f10x.h.

Referenced by CAN_ClearITPendingBit(), and CAN_GetITStatus().

#define CAN_MSR_INAK ((uint16_t)0x0001)

Initialization Acknowledge

Definition at line 6230 of file stm32f10x.h.

Referenced by CAN_Init(), CAN_OperatingModeRequest(), and CAN_Sleep().

#define CAN_MSR_RX ((uint16_t)0x0800)

CAN Rx Signal

Definition at line 6238 of file stm32f10x.h.

#define CAN_MSR_RXM ((uint16_t)0x0200)

Receive Mode

Definition at line 6236 of file stm32f10x.h.

#define CAN_MSR_SAMP ((uint16_t)0x0400)

Last Sample Point

Definition at line 6237 of file stm32f10x.h.

#define CAN_MSR_SLAK ((uint16_t)0x0002)

Sleep Acknowledge

Definition at line 6231 of file stm32f10x.h.

Referenced by CAN_OperatingModeRequest(), CAN_Sleep(), and CAN_WakeUp().

#define CAN_MSR_SLAKI ((uint16_t)0x0010)

Sleep Acknowledge Interrupt

Definition at line 6234 of file stm32f10x.h.

Referenced by CAN_ClearITPendingBit(), and CAN_GetITStatus().

#define CAN_MSR_TXM ((uint16_t)0x0100)

Transmit Mode

Definition at line 6235 of file stm32f10x.h.

#define CAN_MSR_WKUI ((uint16_t)0x0008)

Wakeup Interrupt

Definition at line 6233 of file stm32f10x.h.

Referenced by CAN_ClearITPendingBit(), and CAN_GetITStatus().

#define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF)

Data byte 4

Definition at line 6408 of file stm32f10x.h.

#define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00)

Data byte 5

Definition at line 6409 of file stm32f10x.h.

#define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000)

Data byte 6

Definition at line 6410 of file stm32f10x.h.

#define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000)

Data byte 7

Definition at line 6411 of file stm32f10x.h.

#define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF)

Data byte 4

Definition at line 6431 of file stm32f10x.h.

#define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00)

Data byte 5

Definition at line 6432 of file stm32f10x.h.

#define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000)

Data byte 6

Definition at line 6433 of file stm32f10x.h.

#define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000)

Data byte 7 CAN filter registers

Definition at line 6434 of file stm32f10x.h.

#define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF)

Data byte 0

Definition at line 6402 of file stm32f10x.h.

#define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00)

Data byte 1

Definition at line 6403 of file stm32f10x.h.

#define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000)

Data byte 2

Definition at line 6404 of file stm32f10x.h.

#define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000)

Data byte 3

Definition at line 6405 of file stm32f10x.h.

#define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF)

Data byte 0

Definition at line 6425 of file stm32f10x.h.

#define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00)

Data byte 1

Definition at line 6426 of file stm32f10x.h.

#define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000)

Data byte 2

Definition at line 6427 of file stm32f10x.h.

#define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000)

Data byte 3

Definition at line 6428 of file stm32f10x.h.

#define CAN_RDT0R_DLC ((uint32_t)0x0000000F)

Data Length Code

Definition at line 6397 of file stm32f10x.h.

#define CAN_RDT0R_FMI ((uint32_t)0x0000FF00)

Filter Match Index

Definition at line 6398 of file stm32f10x.h.

#define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000)

Message Time Stamp

Definition at line 6399 of file stm32f10x.h.

#define CAN_RDT1R_DLC ((uint32_t)0x0000000F)

Data Length Code

Definition at line 6420 of file stm32f10x.h.

#define CAN_RDT1R_FMI ((uint32_t)0x0000FF00)

Filter Match Index

Definition at line 6421 of file stm32f10x.h.

#define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000)

Message Time Stamp

Definition at line 6422 of file stm32f10x.h.

#define CAN_RF0R_FMP0 ((uint8_t)0x03)

FIFO 0 Message Pending

Definition at line 6269 of file stm32f10x.h.

Referenced by CAN_GetITStatus().

#define CAN_RF0R_FOVR0 ((uint8_t)0x10)

FIFO 0 Overrun

Definition at line 6271 of file stm32f10x.h.

Referenced by CAN_ClearITPendingBit(), and CAN_GetITStatus().

#define CAN_RF0R_FULL0 ((uint8_t)0x08)

FIFO 0 Full

Definition at line 6270 of file stm32f10x.h.

Referenced by CAN_ClearITPendingBit(), and CAN_GetITStatus().

#define CAN_RF0R_RFOM0 ((uint8_t)0x20)

Release FIFO 0 Output Mailbox

Definition at line 6272 of file stm32f10x.h.

Referenced by CAN_FIFORelease(), and CAN_Receive().

#define CAN_RF1R_FMP1 ((uint8_t)0x03)

FIFO 1 Message Pending

Definition at line 6275 of file stm32f10x.h.

Referenced by CAN_GetITStatus().

#define CAN_RF1R_FOVR1 ((uint8_t)0x10)

FIFO 1 Overrun

Definition at line 6277 of file stm32f10x.h.

Referenced by CAN_ClearITPendingBit(), and CAN_GetITStatus().

#define CAN_RF1R_FULL1 ((uint8_t)0x08)

FIFO 1 Full

Definition at line 6276 of file stm32f10x.h.

Referenced by CAN_ClearITPendingBit(), and CAN_GetITStatus().

#define CAN_RF1R_RFOM1 ((uint8_t)0x20)

Release FIFO 1 Output Mailbox

Definition at line 6278 of file stm32f10x.h.

Referenced by CAN_FIFORelease(), and CAN_Receive().

#define CAN_RI0R_EXID ((uint32_t)0x001FFFF8)

Extended Identifier

Definition at line 6393 of file stm32f10x.h.

#define CAN_RI0R_IDE ((uint32_t)0x00000004)

Identifier Extension

Definition at line 6392 of file stm32f10x.h.

#define CAN_RI0R_RTR ((uint32_t)0x00000002)

Remote Transmission Request

Definition at line 6391 of file stm32f10x.h.

#define CAN_RI0R_STID ((uint32_t)0xFFE00000)

Standard Identifier or Extended Identifier

Definition at line 6394 of file stm32f10x.h.

#define CAN_RI1R_EXID ((uint32_t)0x001FFFF8)

Extended identifier

Definition at line 6416 of file stm32f10x.h.

#define CAN_RI1R_IDE ((uint32_t)0x00000004)

Identifier Extension

Definition at line 6415 of file stm32f10x.h.

#define CAN_RI1R_RTR ((uint32_t)0x00000002)

Remote Transmission Request

Definition at line 6414 of file stm32f10x.h.

#define CAN_RI1R_STID ((uint32_t)0xFFE00000)

Standard Identifier or Extended Identifier

Definition at line 6417 of file stm32f10x.h.

#define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF)

Data byte 4

Definition at line 6337 of file stm32f10x.h.

#define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00)

Data byte 5

Definition at line 6338 of file stm32f10x.h.

#define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000)

Data byte 6

Definition at line 6339 of file stm32f10x.h.

#define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000)

Data byte 7

Definition at line 6340 of file stm32f10x.h.

#define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF)

Data byte 4

Definition at line 6361 of file stm32f10x.h.

#define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00)

Data byte 5

Definition at line 6362 of file stm32f10x.h.

#define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000)

Data byte 6

Definition at line 6363 of file stm32f10x.h.

#define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000)

Data byte 7

Definition at line 6364 of file stm32f10x.h.

#define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF)

Data byte 4

Definition at line 6385 of file stm32f10x.h.

#define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00)

Data byte 5

Definition at line 6386 of file stm32f10x.h.

#define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000)

Data byte 6

Definition at line 6387 of file stm32f10x.h.

#define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000)

Data byte 7

Definition at line 6388 of file stm32f10x.h.

#define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF)

Data byte 0

Definition at line 6331 of file stm32f10x.h.

#define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00)

Data byte 1

Definition at line 6332 of file stm32f10x.h.

#define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000)

Data byte 2

Definition at line 6333 of file stm32f10x.h.

#define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000)

Data byte 3

Definition at line 6334 of file stm32f10x.h.

#define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF)

Data byte 0

Definition at line 6355 of file stm32f10x.h.

#define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00)

Data byte 1

Definition at line 6356 of file stm32f10x.h.

#define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000)

Data byte 2

Definition at line 6357 of file stm32f10x.h.

#define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000)

Data byte 3

Definition at line 6358 of file stm32f10x.h.

#define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF)

Data byte 0

Definition at line 6379 of file stm32f10x.h.

#define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00)

Data byte 1

Definition at line 6380 of file stm32f10x.h.

#define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000)

Data byte 2

Definition at line 6381 of file stm32f10x.h.

#define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000)

Data byte 3

Definition at line 6382 of file stm32f10x.h.

#define CAN_TDT0R_DLC ((uint32_t)0x0000000F)

Data Length Code

Definition at line 6326 of file stm32f10x.h.

#define CAN_TDT0R_TGT ((uint32_t)0x00000100)

Transmit Global Time

Definition at line 6327 of file stm32f10x.h.

Referenced by CAN_TTComModeCmd().

#define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000)

Message Time Stamp

Definition at line 6328 of file stm32f10x.h.

#define CAN_TDT1R_DLC ((uint32_t)0x0000000F)

Data Length Code

Definition at line 6350 of file stm32f10x.h.

#define CAN_TDT1R_TGT ((uint32_t)0x00000100)

Transmit Global Time

Definition at line 6351 of file stm32f10x.h.

Referenced by CAN_TTComModeCmd().

#define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000)

Message Time Stamp

Definition at line 6352 of file stm32f10x.h.

#define CAN_TDT2R_DLC ((uint32_t)0x0000000F)

Data Length Code

Definition at line 6374 of file stm32f10x.h.

#define CAN_TDT2R_TGT ((uint32_t)0x00000100)

Transmit Global Time

Definition at line 6375 of file stm32f10x.h.

Referenced by CAN_TTComModeCmd().

#define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000)

Message Time Stamp

Definition at line 6376 of file stm32f10x.h.

#define CAN_TI0R_EXID ((uint32_t)0x001FFFF8)

Extended Identifier

Definition at line 6322 of file stm32f10x.h.

#define CAN_TI0R_IDE ((uint32_t)0x00000004)

Identifier Extension

Definition at line 6321 of file stm32f10x.h.

#define CAN_TI0R_RTR ((uint32_t)0x00000002)

Remote Transmission Request

Definition at line 6320 of file stm32f10x.h.

#define CAN_TI0R_STID ((uint32_t)0xFFE00000)

Standard Identifier or Extended Identifier

Definition at line 6323 of file stm32f10x.h.

#define CAN_TI0R_TXRQ ((uint32_t)0x00000001)

Transmit Mailbox Request

Definition at line 6319 of file stm32f10x.h.

#define CAN_TI1R_EXID ((uint32_t)0x001FFFF8)

Extended Identifier

Definition at line 6346 of file stm32f10x.h.

#define CAN_TI1R_IDE ((uint32_t)0x00000004)

Identifier Extension

Definition at line 6345 of file stm32f10x.h.

#define CAN_TI1R_RTR ((uint32_t)0x00000002)

Remote Transmission Request

Definition at line 6344 of file stm32f10x.h.

#define CAN_TI1R_STID ((uint32_t)0xFFE00000)

Standard Identifier or Extended Identifier

Definition at line 6347 of file stm32f10x.h.

#define CAN_TI1R_TXRQ ((uint32_t)0x00000001)

Transmit Mailbox Request

Definition at line 6343 of file stm32f10x.h.

#define CAN_TI2R_EXID ((uint32_t)0x001FFFF8)

Extended identifier

Definition at line 6370 of file stm32f10x.h.

#define CAN_TI2R_IDE ((uint32_t)0x00000004)

Identifier Extension

Definition at line 6369 of file stm32f10x.h.

#define CAN_TI2R_RTR ((uint32_t)0x00000002)

Remote Transmission Request

Definition at line 6368 of file stm32f10x.h.

#define CAN_TI2R_STID ((uint32_t)0xFFE00000)

Standard Identifier or Extended Identifier

Definition at line 6371 of file stm32f10x.h.

#define CAN_TI2R_TXRQ ((uint32_t)0x00000001)

Transmit Mailbox Request

Definition at line 6367 of file stm32f10x.h.

#define CAN_TSR_ABRQ0 ((uint32_t)0x00000080)

Abort Request for Mailbox0

Definition at line 6245 of file stm32f10x.h.

Referenced by CAN_CancelTransmit().

#define CAN_TSR_ABRQ1 ((uint32_t)0x00008000)

Abort Request for Mailbox 1

Definition at line 6250 of file stm32f10x.h.

Referenced by CAN_CancelTransmit().

#define CAN_TSR_ABRQ2 ((uint32_t)0x00800000)

Abort Request for Mailbox 2

Definition at line 6255 of file stm32f10x.h.

Referenced by CAN_CancelTransmit().

#define CAN_TSR_ALST0 ((uint32_t)0x00000004)

Arbitration Lost for Mailbox0

Definition at line 6243 of file stm32f10x.h.

#define CAN_TSR_ALST1 ((uint32_t)0x00000400)

Arbitration Lost for Mailbox1

Definition at line 6248 of file stm32f10x.h.

#define CAN_TSR_ALST2 ((uint32_t)0x00040000)

Arbitration Lost for mailbox 2

Definition at line 6253 of file stm32f10x.h.

#define CAN_TSR_CODE ((uint32_t)0x03000000)

Mailbox Code

Definition at line 6256 of file stm32f10x.h.

#define CAN_TSR_LOW ((uint32_t)0xE0000000)

LOW[2:0] bits

Definition at line 6263 of file stm32f10x.h.

#define CAN_TSR_LOW0 ((uint32_t)0x20000000)

Lowest Priority Flag for Mailbox 0

Definition at line 6264 of file stm32f10x.h.

#define CAN_TSR_LOW1 ((uint32_t)0x40000000)

Lowest Priority Flag for Mailbox 1

Definition at line 6265 of file stm32f10x.h.

#define CAN_TSR_LOW2 ((uint32_t)0x80000000)

Lowest Priority Flag for Mailbox 2

Definition at line 6266 of file stm32f10x.h.

#define CAN_TSR_RQCP0 ((uint32_t)0x00000001)

Request Completed Mailbox0

Definition at line 6241 of file stm32f10x.h.

Referenced by CAN_ClearITPendingBit(), CAN_GetITStatus(), and CAN_TransmitStatus().

#define CAN_TSR_RQCP1 ((uint32_t)0x00000100)

Request Completed Mailbox1

Definition at line 6246 of file stm32f10x.h.

Referenced by CAN_ClearITPendingBit(), CAN_GetITStatus(), and CAN_TransmitStatus().

#define CAN_TSR_RQCP2 ((uint32_t)0x00010000)

Request Completed Mailbox2

Definition at line 6251 of file stm32f10x.h.

Referenced by CAN_ClearITPendingBit(), CAN_GetITStatus(), and CAN_TransmitStatus().

#define CAN_TSR_TERR0 ((uint32_t)0x00000008)

Transmission Error of Mailbox0

Definition at line 6244 of file stm32f10x.h.

#define CAN_TSR_TERR1 ((uint32_t)0x00000800)

Transmission Error of Mailbox1

Definition at line 6249 of file stm32f10x.h.

#define CAN_TSR_TERR2 ((uint32_t)0x00080000)

Transmission Error of Mailbox 2

Definition at line 6254 of file stm32f10x.h.

#define CAN_TSR_TME ((uint32_t)0x1C000000)

TME[2:0] bits

Definition at line 6258 of file stm32f10x.h.

#define CAN_TSR_TME0 ((uint32_t)0x04000000)

Transmit Mailbox 0 Empty

Definition at line 6259 of file stm32f10x.h.

Referenced by CAN_Transmit(), and CAN_TransmitStatus().

#define CAN_TSR_TME1 ((uint32_t)0x08000000)

Transmit Mailbox 1 Empty

Definition at line 6260 of file stm32f10x.h.

Referenced by CAN_Transmit(), and CAN_TransmitStatus().

#define CAN_TSR_TME2 ((uint32_t)0x10000000)

Transmit Mailbox 2 Empty

Definition at line 6261 of file stm32f10x.h.

Referenced by CAN_Transmit(), and CAN_TransmitStatus().

#define CAN_TSR_TXOK0 ((uint32_t)0x00000002)

Transmission OK of Mailbox0

Definition at line 6242 of file stm32f10x.h.

Referenced by CAN_TransmitStatus().

#define CAN_TSR_TXOK1 ((uint32_t)0x00000200)

Transmission OK of Mailbox1

Definition at line 6247 of file stm32f10x.h.

Referenced by CAN_TransmitStatus().

#define CAN_TSR_TXOK2 ((uint32_t)0x00020000)

Transmission OK of Mailbox 2

Definition at line 6252 of file stm32f10x.h.

Referenced by CAN_TransmitStatus().

#define CEC_CFGR_BPEM ((uint16_t)0x0008)

Bit Period Error Mode

Definition at line 4147 of file stm32f10x.h.

#define CEC_CFGR_BTEM ((uint16_t)0x0004)

Bit Timing Error Mode

Definition at line 4146 of file stm32f10x.h.

#define CEC_CFGR_IE ((uint16_t)0x0002)

Interrupt Enable

Definition at line 4145 of file stm32f10x.h.

Referenced by CEC_GetITStatus().

#define CEC_CFGR_PE ((uint16_t)0x0001)

Peripheral Enable

Definition at line 4144 of file stm32f10x.h.

Referenced by CEC_Cmd().

#define CEC_CSR_RBTF ((uint16_t)0x0080)

Rx Block Transfer Finished

Definition at line 4176 of file stm32f10x.h.

#define CEC_CSR_REOM ((uint16_t)0x0020)

Rx End Of Message

Definition at line 4174 of file stm32f10x.h.

#define CEC_CSR_RERR ((uint16_t)0x0040)

Rx Error

Definition at line 4175 of file stm32f10x.h.

#define CEC_CSR_RSOM ((uint16_t)0x0010)

Rx Start Of Message

Definition at line 4173 of file stm32f10x.h.

#define CEC_CSR_TBTRF ((uint16_t)0x0008)

Tx Byte Transfer Request or Block Transfer Finished

Definition at line 4172 of file stm32f10x.h.

#define CEC_CSR_TEOM ((uint16_t)0x0002)

Tx End Of Message

Definition at line 4170 of file stm32f10x.h.

#define CEC_CSR_TERR ((uint16_t)0x0004)

Tx Error

Definition at line 4171 of file stm32f10x.h.

#define CEC_CSR_TSOM ((uint16_t)0x0001)

Tx Start Of Message

Definition at line 4169 of file stm32f10x.h.

#define CEC_ESR_ACKE ((uint16_t)0x0010)

Block Acknowledge Error

Definition at line 4164 of file stm32f10x.h.

#define CEC_ESR_BPE ((uint16_t)0x0002)

Bit Period Error

Definition at line 4161 of file stm32f10x.h.

#define CEC_ESR_BTE ((uint16_t)0x0001)

Bit Timing Error

Definition at line 4160 of file stm32f10x.h.

#define CEC_ESR_LINE ((uint16_t)0x0020)

Line Error

Definition at line 4165 of file stm32f10x.h.

#define CEC_ESR_RBTFE ((uint16_t)0x0004)

Rx Block Transfer Finished Error

Definition at line 4162 of file stm32f10x.h.

#define CEC_ESR_SBE ((uint16_t)0x0008)

Start Bit Error

Definition at line 4163 of file stm32f10x.h.

#define CEC_ESR_TBTFE ((uint16_t)0x0040)

Tx Block Transfer Finished Error

Definition at line 4166 of file stm32f10x.h.

#define CEC_OAR_OA ((uint16_t)0x000F)

OA[3:0]: Own Address

Definition at line 4150 of file stm32f10x.h.

#define CEC_OAR_OA_0 ((uint16_t)0x0001)

Bit 0

Definition at line 4151 of file stm32f10x.h.

#define CEC_OAR_OA_1 ((uint16_t)0x0002)

Bit 1

Definition at line 4152 of file stm32f10x.h.

#define CEC_OAR_OA_2 ((uint16_t)0x0004)

Bit 2

Definition at line 4153 of file stm32f10x.h.

#define CEC_OAR_OA_3 ((uint16_t)0x0008)

Bit 3

Definition at line 4154 of file stm32f10x.h.

#define CEC_PRES_PRES ((uint16_t)0x3FFF)

Prescaler Counter Value

Definition at line 4157 of file stm32f10x.h.

#define CEC_RXD_RXD ((uint16_t)0x00FF)

Rx Data register

Definition at line 4182 of file stm32f10x.h.

#define CEC_TXD_TXD ((uint16_t)0x00FF)

Tx Data register

Definition at line 4179 of file stm32f10x.h.

#define CRC_CR_RESET ((uint8_t)0x01)

RESET bit

Definition at line 1486 of file stm32f10x.h.

Referenced by CRC_ResetDR().

#define CRC_DR_DR ((uint32_t)0xFFFFFFFF)

Data register bits

Definition at line 1478 of file stm32f10x.h.

#define CRC_IDR_IDR ((uint8_t)0xFF)

General-purpose 8-bit data register bits

Definition at line 1482 of file stm32f10x.h.

#define DAC_CR_BOFF1 ((uint32_t)0x00000002)

DAC channel1 output buffer disable

Definition at line 4054 of file stm32f10x.h.

#define DAC_CR_BOFF2 ((uint32_t)0x00020000)

DAC channel2 output buffer disable

Definition at line 4074 of file stm32f10x.h.

#define DAC_CR_DMAEN1 ((uint32_t)0x00001000)

DAC channel1 DMA enable

Definition at line 4072 of file stm32f10x.h.

Referenced by DAC_DMACmd().

#define DAC_CR_DMAEN2 ((uint32_t)0x10000000)

DAC channel2 DMA enabled

Definition at line 4092 of file stm32f10x.h.

#define DAC_CR_EN1 ((uint32_t)0x00000001)

DAC channel1 enable

Definition at line 4053 of file stm32f10x.h.

Referenced by DAC_Cmd().

#define DAC_CR_EN2 ((uint32_t)0x00010000)

DAC channel2 enable

Definition at line 4073 of file stm32f10x.h.

#define DAC_CR_MAMP1 ((uint32_t)0x00000F00)

MAMP1[3:0] (DAC channel1 Mask/Amplitude selector)

Definition at line 4066 of file stm32f10x.h.

#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100)

Bit 0

Definition at line 4067 of file stm32f10x.h.

#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200)

Bit 1

Definition at line 4068 of file stm32f10x.h.

#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400)

Bit 2

Definition at line 4069 of file stm32f10x.h.

#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800)

Bit 3

Definition at line 4070 of file stm32f10x.h.

#define DAC_CR_MAMP2 ((uint32_t)0x0F000000)

MAMP2[3:0] (DAC channel2 Mask/Amplitude selector)

Definition at line 4086 of file stm32f10x.h.

#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000)

Bit 0

Definition at line 4087 of file stm32f10x.h.

#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000)

Bit 1

Definition at line 4088 of file stm32f10x.h.

#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000)

Bit 2

Definition at line 4089 of file stm32f10x.h.

#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000)

Bit 3

Definition at line 4090 of file stm32f10x.h.

#define DAC_CR_TEN1 ((uint32_t)0x00000004)

DAC channel1 Trigger enable

Definition at line 4055 of file stm32f10x.h.

#define DAC_CR_TEN2 ((uint32_t)0x00040000)

DAC channel2 Trigger enable

Definition at line 4075 of file stm32f10x.h.

#define DAC_CR_TSEL1 ((uint32_t)0x00000038)

TSEL1[2:0] (DAC channel1 Trigger selection)

Definition at line 4057 of file stm32f10x.h.

#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008)

Bit 0

Definition at line 4058 of file stm32f10x.h.

#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010)

Bit 1

Definition at line 4059 of file stm32f10x.h.

#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020)

Bit 2

Definition at line 4060 of file stm32f10x.h.

#define DAC_CR_TSEL2 ((uint32_t)0x00380000)

TSEL2[2:0] (DAC channel2 Trigger selection)

Definition at line 4077 of file stm32f10x.h.

#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000)

Bit 0

Definition at line 4078 of file stm32f10x.h.

#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000)

Bit 1

Definition at line 4079 of file stm32f10x.h.

#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000)

Bit 2

Definition at line 4080 of file stm32f10x.h.

#define DAC_CR_WAVE1 ((uint32_t)0x000000C0)

WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable)

Definition at line 4062 of file stm32f10x.h.

#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040)

Bit 0

Definition at line 4063 of file stm32f10x.h.

#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080)

Bit 1

Definition at line 4064 of file stm32f10x.h.

#define DAC_CR_WAVE2 ((uint32_t)0x00C00000)

WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable)

Definition at line 4082 of file stm32f10x.h.

#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000)

Bit 0

Definition at line 4083 of file stm32f10x.h.

#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000)

Bit 1

Definition at line 4084 of file stm32f10x.h.

#define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0)

DAC channel1 12-bit Left aligned data

Definition at line 4102 of file stm32f10x.h.

#define DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0)

DAC channel2 12-bit Left aligned data

Definition at line 4111 of file stm32f10x.h.

#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0)

DAC channel1 12-bit Left aligned data

Definition at line 4121 of file stm32f10x.h.

#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000)

DAC channel2 12-bit Left aligned data

Definition at line 4122 of file stm32f10x.h.

#define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF)

DAC channel1 12-bit Right aligned data

Definition at line 4099 of file stm32f10x.h.

#define DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF)

DAC channel2 12-bit Right aligned data

Definition at line 4108 of file stm32f10x.h.

#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF)

DAC channel1 12-bit Right aligned data

Definition at line 4117 of file stm32f10x.h.

#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000)

DAC channel2 12-bit Right aligned data

Definition at line 4118 of file stm32f10x.h.

#define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF)

DAC channel1 8-bit Right aligned data

Definition at line 4105 of file stm32f10x.h.

#define DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF)

DAC channel2 8-bit Right aligned data

Definition at line 4114 of file stm32f10x.h.

#define DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF)

DAC channel1 8-bit Right aligned data

Definition at line 4125 of file stm32f10x.h.

#define DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00)

DAC channel2 8-bit Right aligned data

Definition at line 4126 of file stm32f10x.h.

#define DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF)

DAC channel1 data output

Definition at line 4129 of file stm32f10x.h.

#define DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF)

DAC channel2 data output

Definition at line 4132 of file stm32f10x.h.

#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000)

DAC channel1 DMA underrun flag

Definition at line 4135 of file stm32f10x.h.

#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000)

DAC channel2 DMA underrun flag

Definition at line 4136 of file stm32f10x.h.

#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01)

DAC channel1 software trigger

Definition at line 4095 of file stm32f10x.h.

Referenced by DAC_SoftwareTriggerCmd().

#define DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02)

DAC channel2 software trigger

Definition at line 4096 of file stm32f10x.h.

#define DBGMCU_CR_DBG_CAN1_STOP ((uint32_t)0x00004000)

Debug CAN1 stopped when Core is halted

Definition at line 7766 of file stm32f10x.h.

#define DBGMCU_CR_DBG_CAN2_STOP ((uint32_t)0x00200000)

Debug CAN2 stopped when Core is halted

Definition at line 7773 of file stm32f10x.h.

#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000)

SMBUS timeout mode stopped when Core is halted

Definition at line 7767 of file stm32f10x.h.

#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000)

SMBUS timeout mode stopped when Core is halted

Definition at line 7768 of file stm32f10x.h.

#define DBGMCU_CR_DBG_IWDG_STOP ((uint32_t)0x00000100)

Debug Independent Watchdog stopped when Core is halted

Definition at line 7760 of file stm32f10x.h.

#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001)

Debug Sleep Mode

Definition at line 7751 of file stm32f10x.h.

#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004)

Debug Standby mode

Definition at line 7753 of file stm32f10x.h.

#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002)

Debug Stop Mode

Definition at line 7752 of file stm32f10x.h.

#define DBGMCU_CR_DBG_TIM10_STOP ((uint32_t)0x20000000)

Debug TIM10 stopped when Core is halted

Definition at line 7781 of file stm32f10x.h.

#define DBGMCU_CR_DBG_TIM11_STOP ((uint32_t)0x40000000)

Debug TIM11 stopped when Core is halted

Definition at line 7782 of file stm32f10x.h.

#define DBGMCU_CR_DBG_TIM12_STOP ((uint32_t)0x02000000)

Debug TIM12 stopped when Core is halted

Definition at line 7777 of file stm32f10x.h.

#define DBGMCU_CR_DBG_TIM13_STOP ((uint32_t)0x04000000)

Debug TIM13 stopped when Core is halted

Definition at line 7778 of file stm32f10x.h.

#define DBGMCU_CR_DBG_TIM14_STOP ((uint32_t)0x08000000)

Debug TIM14 stopped when Core is halted

Definition at line 7779 of file stm32f10x.h.

#define DBGMCU_CR_DBG_TIM15_STOP ((uint32_t)0x00400000)

Debug TIM15 stopped when Core is halted

Definition at line 7774 of file stm32f10x.h.

#define DBGMCU_CR_DBG_TIM16_STOP ((uint32_t)0x00800000)

Debug TIM16 stopped when Core is halted

Definition at line 7775 of file stm32f10x.h.

#define DBGMCU_CR_DBG_TIM17_STOP ((uint32_t)0x01000000)

Debug TIM17 stopped when Core is halted

Definition at line 7776 of file stm32f10x.h.

#define DBGMCU_CR_DBG_TIM1_STOP ((uint32_t)0x00000400)

TIM1 counter stopped when core is halted

Definition at line 7762 of file stm32f10x.h.

#define DBGMCU_CR_DBG_TIM2_STOP ((uint32_t)0x00000800)

TIM2 counter stopped when core is halted

Definition at line 7763 of file stm32f10x.h.

#define DBGMCU_CR_DBG_TIM3_STOP ((uint32_t)0x00001000)

TIM3 counter stopped when core is halted

Definition at line 7764 of file stm32f10x.h.

#define DBGMCU_CR_DBG_TIM4_STOP ((uint32_t)0x00002000)

TIM4 counter stopped when core is halted

Definition at line 7765 of file stm32f10x.h.

#define DBGMCU_CR_DBG_TIM5_STOP ((uint32_t)0x00040000)

TIM5 counter stopped when core is halted

Definition at line 7770 of file stm32f10x.h.

#define DBGMCU_CR_DBG_TIM6_STOP ((uint32_t)0x00080000)

TIM6 counter stopped when core is halted

Definition at line 7771 of file stm32f10x.h.

#define DBGMCU_CR_DBG_TIM7_STOP ((uint32_t)0x00100000)

TIM7 counter stopped when core is halted

Definition at line 7772 of file stm32f10x.h.

#define DBGMCU_CR_DBG_TIM8_STOP ((uint32_t)0x00020000)

TIM8 counter stopped when core is halted

Definition at line 7769 of file stm32f10x.h.

#define DBGMCU_CR_DBG_TIM9_STOP ((uint32_t)0x10000000)

Debug TIM9 stopped when Core is halted

Definition at line 7780 of file stm32f10x.h.

#define DBGMCU_CR_DBG_WWDG_STOP ((uint32_t)0x00000200)

Debug Window Watchdog stopped when Core is halted

Definition at line 7761 of file stm32f10x.h.

#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020)

Trace Pin Assignment Control

Definition at line 7754 of file stm32f10x.h.

#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0)

TRACE_MODE[1:0] bits (Trace Pin Assignment Control)

Definition at line 7756 of file stm32f10x.h.

#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040)

Bit 0

Definition at line 7757 of file stm32f10x.h.

#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080)

Bit 1

Definition at line 7758 of file stm32f10x.h.

#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF)

Device Identifier

Definition at line 7730 of file stm32f10x.h.

#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000)

REV_ID[15:0] bits (Revision Identifier)

Definition at line 7732 of file stm32f10x.h.

#define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000)

Bit 0

Definition at line 7733 of file stm32f10x.h.

#define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000)

Bit 1

Definition at line 7734 of file stm32f10x.h.

#define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000)

Bit 10

Definition at line 7743 of file stm32f10x.h.

#define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000)

Bit 11

Definition at line 7744 of file stm32f10x.h.

#define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000)

Bit 12

Definition at line 7745 of file stm32f10x.h.

#define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000)

Bit 13

Definition at line 7746 of file stm32f10x.h.

#define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000)

Bit 14

Definition at line 7747 of file stm32f10x.h.

#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000)

Bit 15

Definition at line 7748 of file stm32f10x.h.

#define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000)

Bit 2

Definition at line 7735 of file stm32f10x.h.

#define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000)

Bit 3

Definition at line 7736 of file stm32f10x.h.

#define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000)

Bit 4

Definition at line 7737 of file stm32f10x.h.

#define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000)

Bit 5

Definition at line 7738 of file stm32f10x.h.

#define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000)

Bit 6

Definition at line 7739 of file stm32f10x.h.

#define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000)

Bit 7

Definition at line 7740 of file stm32f10x.h.

#define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000)

Bit 8

Definition at line 7741 of file stm32f10x.h.

#define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000)

Bit 9

Definition at line 7742 of file stm32f10x.h.

#define DMA_CCR1_CIRC ((uint16_t)0x0020)

Circular mode

Definition at line 3468 of file stm32f10x.h.

#define DMA_CCR1_DIR ((uint16_t)0x0010)

Data transfer direction

Definition at line 3467 of file stm32f10x.h.

#define DMA_CCR1_EN ((uint16_t)0x0001)

Channel enable

Definition at line 3463 of file stm32f10x.h.

Referenced by DMA_Cmd(), and DMA_DeInit().

#define DMA_CCR1_HTIE ((uint16_t)0x0004)

Half Transfer interrupt enable

Definition at line 3465 of file stm32f10x.h.

#define DMA_CCR1_MEM2MEM ((uint16_t)0x4000)

Memory to memory mode

Definition at line 3484 of file stm32f10x.h.

#define DMA_CCR1_MINC ((uint16_t)0x0080)

Memory increment mode

Definition at line 3470 of file stm32f10x.h.

#define DMA_CCR1_MSIZE ((uint16_t)0x0C00)

MSIZE[1:0] bits (Memory size)

Definition at line 3476 of file stm32f10x.h.

#define DMA_CCR1_MSIZE_0 ((uint16_t)0x0400)

Bit 0

Definition at line 3477 of file stm32f10x.h.

#define DMA_CCR1_MSIZE_1 ((uint16_t)0x0800)

Bit 1

Definition at line 3478 of file stm32f10x.h.

#define DMA_CCR1_PINC ((uint16_t)0x0040)

Peripheral increment mode

Definition at line 3469 of file stm32f10x.h.

#define DMA_CCR1_PL ((uint16_t)0x3000)

PL[1:0] bits(Channel Priority level)

Definition at line 3480 of file stm32f10x.h.

#define DMA_CCR1_PL_0 ((uint16_t)0x1000)

Bit 0

Definition at line 3481 of file stm32f10x.h.

#define DMA_CCR1_PL_1 ((uint16_t)0x2000)

Bit 1

Definition at line 3482 of file stm32f10x.h.

#define DMA_CCR1_PSIZE ((uint16_t)0x0300)

PSIZE[1:0] bits (Peripheral size)

Definition at line 3472 of file stm32f10x.h.

#define DMA_CCR1_PSIZE_0 ((uint16_t)0x0100)

Bit 0

Definition at line 3473 of file stm32f10x.h.

#define DMA_CCR1_PSIZE_1 ((uint16_t)0x0200)

Bit 1

Definition at line 3474 of file stm32f10x.h.

#define DMA_CCR1_TCIE ((uint16_t)0x0002)

Transfer complete interrupt enable

Definition at line 3464 of file stm32f10x.h.

#define DMA_CCR1_TEIE ((uint16_t)0x0008)

Transfer error interrupt enable

Definition at line 3466 of file stm32f10x.h.

#define DMA_CCR2_CIRC ((uint16_t)0x0020)

Circular mode

Definition at line 3492 of file stm32f10x.h.

#define DMA_CCR2_DIR ((uint16_t)0x0010)

Data transfer direction

Definition at line 3491 of file stm32f10x.h.

#define DMA_CCR2_EN ((uint16_t)0x0001)

Channel enable

Definition at line 3487 of file stm32f10x.h.

#define DMA_CCR2_HTIE ((uint16_t)0x0004)

Half Transfer interrupt enable

Definition at line 3489 of file stm32f10x.h.

#define DMA_CCR2_MEM2MEM ((uint16_t)0x4000)

Memory to memory mode

Definition at line 3508 of file stm32f10x.h.

#define DMA_CCR2_MINC ((uint16_t)0x0080)

Memory increment mode

Definition at line 3494 of file stm32f10x.h.

#define DMA_CCR2_MSIZE ((uint16_t)0x0C00)

MSIZE[1:0] bits (Memory size)

Definition at line 3500 of file stm32f10x.h.

#define DMA_CCR2_MSIZE_0 ((uint16_t)0x0400)

Bit 0

Definition at line 3501 of file stm32f10x.h.

#define DMA_CCR2_MSIZE_1 ((uint16_t)0x0800)

Bit 1

Definition at line 3502 of file stm32f10x.h.

#define DMA_CCR2_PINC ((uint16_t)0x0040)

Peripheral increment mode

Definition at line 3493 of file stm32f10x.h.

#define DMA_CCR2_PL ((uint16_t)0x3000)

PL[1:0] bits (Channel Priority level)

Definition at line 3504 of file stm32f10x.h.

#define DMA_CCR2_PL_0 ((uint16_t)0x1000)

Bit 0

Definition at line 3505 of file stm32f10x.h.

#define DMA_CCR2_PL_1 ((uint16_t)0x2000)

Bit 1

Definition at line 3506 of file stm32f10x.h.

#define DMA_CCR2_PSIZE ((uint16_t)0x0300)

PSIZE[1:0] bits (Peripheral size)

Definition at line 3496 of file stm32f10x.h.

#define DMA_CCR2_PSIZE_0 ((uint16_t)0x0100)

Bit 0

Definition at line 3497 of file stm32f10x.h.

#define DMA_CCR2_PSIZE_1 ((uint16_t)0x0200)

Bit 1

Definition at line 3498 of file stm32f10x.h.

#define DMA_CCR2_TCIE ((uint16_t)0x0002)

Transfer complete interrupt enable

Definition at line 3488 of file stm32f10x.h.

#define DMA_CCR2_TEIE ((uint16_t)0x0008)

Transfer error interrupt enable

Definition at line 3490 of file stm32f10x.h.

#define DMA_CCR3_CIRC ((uint16_t)0x0020)

Circular mode

Definition at line 3516 of file stm32f10x.h.

#define DMA_CCR3_DIR ((uint16_t)0x0010)

Data transfer direction

Definition at line 3515 of file stm32f10x.h.

#define DMA_CCR3_EN ((uint16_t)0x0001)

Channel enable

Definition at line 3511 of file stm32f10x.h.

#define DMA_CCR3_HTIE ((uint16_t)0x0004)

Half Transfer interrupt enable

Definition at line 3513 of file stm32f10x.h.

#define DMA_CCR3_MEM2MEM ((uint16_t)0x4000)

Memory to memory mode ****************** Bit definition for DMA_CCR4 register

Definition at line 3532 of file stm32f10x.h.

#define DMA_CCR3_MINC ((uint16_t)0x0080)

Memory increment mode

Definition at line 3518 of file stm32f10x.h.

#define DMA_CCR3_MSIZE ((uint16_t)0x0C00)

MSIZE[1:0] bits (Memory size)

Definition at line 3524 of file stm32f10x.h.

#define DMA_CCR3_MSIZE_0 ((uint16_t)0x0400)

Bit 0

Definition at line 3525 of file stm32f10x.h.

#define DMA_CCR3_MSIZE_1 ((uint16_t)0x0800)

Bit 1

Definition at line 3526 of file stm32f10x.h.

#define DMA_CCR3_PINC ((uint16_t)0x0040)

Peripheral increment mode

Definition at line 3517 of file stm32f10x.h.

#define DMA_CCR3_PL ((uint16_t)0x3000)

PL[1:0] bits (Channel Priority level)

Definition at line 3528 of file stm32f10x.h.

#define DMA_CCR3_PL_0 ((uint16_t)0x1000)

Bit 0

Definition at line 3529 of file stm32f10x.h.

#define DMA_CCR3_PL_1 ((uint16_t)0x2000)

Bit 1

Definition at line 3530 of file stm32f10x.h.

#define DMA_CCR3_PSIZE ((uint16_t)0x0300)

PSIZE[1:0] bits (Peripheral size)

Definition at line 3520 of file stm32f10x.h.

#define DMA_CCR3_PSIZE_0 ((uint16_t)0x0100)

Bit 0

Definition at line 3521 of file stm32f10x.h.

#define DMA_CCR3_PSIZE_1 ((uint16_t)0x0200)

Bit 1

Definition at line 3522 of file stm32f10x.h.

#define DMA_CCR3_TCIE ((uint16_t)0x0002)

Transfer complete interrupt enable

Definition at line 3512 of file stm32f10x.h.

#define DMA_CCR3_TEIE ((uint16_t)0x0008)

Transfer error interrupt enable

Definition at line 3514 of file stm32f10x.h.

#define DMA_CCR4_CIRC ((uint16_t)0x0020)

Circular mode

Definition at line 3540 of file stm32f10x.h.

#define DMA_CCR4_DIR ((uint16_t)0x0010)

Data transfer direction

Definition at line 3539 of file stm32f10x.h.

#define DMA_CCR4_EN ((uint16_t)0x0001)

Channel enable

Definition at line 3535 of file stm32f10x.h.

#define DMA_CCR4_HTIE ((uint16_t)0x0004)

Half Transfer interrupt enable

Definition at line 3537 of file stm32f10x.h.

#define DMA_CCR4_MEM2MEM ((uint16_t)0x4000)

Memory to memory mode

Definition at line 3556 of file stm32f10x.h.

#define DMA_CCR4_MINC ((uint16_t)0x0080)

Memory increment mode

Definition at line 3542 of file stm32f10x.h.

#define DMA_CCR4_MSIZE ((uint16_t)0x0C00)

MSIZE[1:0] bits (Memory size)

Definition at line 3548 of file stm32f10x.h.

#define DMA_CCR4_MSIZE_0 ((uint16_t)0x0400)

Bit 0

Definition at line 3549 of file stm32f10x.h.

#define DMA_CCR4_MSIZE_1 ((uint16_t)0x0800)

Bit 1

Definition at line 3550 of file stm32f10x.h.

#define DMA_CCR4_PINC ((uint16_t)0x0040)

Peripheral increment mode

Definition at line 3541 of file stm32f10x.h.

#define DMA_CCR4_PL ((uint16_t)0x3000)

PL[1:0] bits (Channel Priority level)

Definition at line 3552 of file stm32f10x.h.

#define DMA_CCR4_PL_0 ((uint16_t)0x1000)

Bit 0

Definition at line 3553 of file stm32f10x.h.

#define DMA_CCR4_PL_1 ((uint16_t)0x2000)

Bit 1

Definition at line 3554 of file stm32f10x.h.

#define DMA_CCR4_PSIZE ((uint16_t)0x0300)

PSIZE[1:0] bits (Peripheral size)

Definition at line 3544 of file stm32f10x.h.

#define DMA_CCR4_PSIZE_0 ((uint16_t)0x0100)

Bit 0

Definition at line 3545 of file stm32f10x.h.

#define DMA_CCR4_PSIZE_1 ((uint16_t)0x0200)

Bit 1

Definition at line 3546 of file stm32f10x.h.

#define DMA_CCR4_TCIE ((uint16_t)0x0002)

Transfer complete interrupt enable

Definition at line 3536 of file stm32f10x.h.

#define DMA_CCR4_TEIE ((uint16_t)0x0008)

Transfer error interrupt enable

Definition at line 3538 of file stm32f10x.h.

#define DMA_CCR5_CIRC ((uint16_t)0x0020)

Circular mode

Definition at line 3564 of file stm32f10x.h.

#define DMA_CCR5_DIR ((uint16_t)0x0010)

Data transfer direction

Definition at line 3563 of file stm32f10x.h.

#define DMA_CCR5_EN ((uint16_t)0x0001)

Channel enable

Definition at line 3559 of file stm32f10x.h.

#define DMA_CCR5_HTIE ((uint16_t)0x0004)

Half Transfer interrupt enable

Definition at line 3561 of file stm32f10x.h.

#define DMA_CCR5_MEM2MEM ((uint16_t)0x4000)

Memory to memory mode enable

Definition at line 3580 of file stm32f10x.h.

#define DMA_CCR5_MINC ((uint16_t)0x0080)

Memory increment mode

Definition at line 3566 of file stm32f10x.h.

#define DMA_CCR5_MSIZE ((uint16_t)0x0C00)

MSIZE[1:0] bits (Memory size)

Definition at line 3572 of file stm32f10x.h.

#define DMA_CCR5_MSIZE_0 ((uint16_t)0x0400)

Bit 0

Definition at line 3573 of file stm32f10x.h.

#define DMA_CCR5_MSIZE_1 ((uint16_t)0x0800)

Bit 1

Definition at line 3574 of file stm32f10x.h.

#define DMA_CCR5_PINC ((uint16_t)0x0040)

Peripheral increment mode

Definition at line 3565 of file stm32f10x.h.

#define DMA_CCR5_PL ((uint16_t)0x3000)

PL[1:0] bits (Channel Priority level)

Definition at line 3576 of file stm32f10x.h.

#define DMA_CCR5_PL_0 ((uint16_t)0x1000)

Bit 0

Definition at line 3577 of file stm32f10x.h.

#define DMA_CCR5_PL_1 ((uint16_t)0x2000)

Bit 1

Definition at line 3578 of file stm32f10x.h.

#define DMA_CCR5_PSIZE ((uint16_t)0x0300)

PSIZE[1:0] bits (Peripheral size)

Definition at line 3568 of file stm32f10x.h.

#define DMA_CCR5_PSIZE_0 ((uint16_t)0x0100)

Bit 0

Definition at line 3569 of file stm32f10x.h.

#define DMA_CCR5_PSIZE_1 ((uint16_t)0x0200)

Bit 1

Definition at line 3570 of file stm32f10x.h.

#define DMA_CCR5_TCIE ((uint16_t)0x0002)

Transfer complete interrupt enable

Definition at line 3560 of file stm32f10x.h.

#define DMA_CCR5_TEIE ((uint16_t)0x0008)

Transfer error interrupt enable

Definition at line 3562 of file stm32f10x.h.

#define DMA_CCR6_CIRC ((uint16_t)0x0020)

Circular mode

Definition at line 3588 of file stm32f10x.h.

#define DMA_CCR6_DIR ((uint16_t)0x0010)

Data transfer direction

Definition at line 3587 of file stm32f10x.h.

#define DMA_CCR6_EN ((uint16_t)0x0001)

Channel enable

Definition at line 3583 of file stm32f10x.h.

#define DMA_CCR6_HTIE ((uint16_t)0x0004)

Half Transfer interrupt enable

Definition at line 3585 of file stm32f10x.h.

#define DMA_CCR6_MEM2MEM ((uint16_t)0x4000)

Memory to memory mode

Definition at line 3604 of file stm32f10x.h.

#define DMA_CCR6_MINC ((uint16_t)0x0080)

Memory increment mode

Definition at line 3590 of file stm32f10x.h.

#define DMA_CCR6_MSIZE ((uint16_t)0x0C00)

MSIZE[1:0] bits (Memory size)

Definition at line 3596 of file stm32f10x.h.

#define DMA_CCR6_MSIZE_0 ((uint16_t)0x0400)

Bit 0

Definition at line 3597 of file stm32f10x.h.

#define DMA_CCR6_MSIZE_1 ((uint16_t)0x0800)

Bit 1

Definition at line 3598 of file stm32f10x.h.

#define DMA_CCR6_PINC ((uint16_t)0x0040)

Peripheral increment mode

Definition at line 3589 of file stm32f10x.h.

#define DMA_CCR6_PL ((uint16_t)0x3000)

PL[1:0] bits (Channel Priority level)

Definition at line 3600 of file stm32f10x.h.

#define DMA_CCR6_PL_0 ((uint16_t)0x1000)

Bit 0

Definition at line 3601 of file stm32f10x.h.

#define DMA_CCR6_PL_1 ((uint16_t)0x2000)

Bit 1

Definition at line 3602 of file stm32f10x.h.

#define DMA_CCR6_PSIZE ((uint16_t)0x0300)

PSIZE[1:0] bits (Peripheral size)

Definition at line 3592 of file stm32f10x.h.

#define DMA_CCR6_PSIZE_0 ((uint16_t)0x0100)

Bit 0

Definition at line 3593 of file stm32f10x.h.

#define DMA_CCR6_PSIZE_1 ((uint16_t)0x0200)

Bit 1

Definition at line 3594 of file stm32f10x.h.

#define DMA_CCR6_TCIE ((uint16_t)0x0002)

Transfer complete interrupt enable

Definition at line 3584 of file stm32f10x.h.

#define DMA_CCR6_TEIE ((uint16_t)0x0008)

Transfer error interrupt enable

Definition at line 3586 of file stm32f10x.h.

#define DMA_CCR7_CIRC ((uint16_t)0x0020)

Circular mode

Definition at line 3612 of file stm32f10x.h.

#define DMA_CCR7_DIR ((uint16_t)0x0010)

Data transfer direction

Definition at line 3611 of file stm32f10x.h.

#define DMA_CCR7_EN ((uint16_t)0x0001)

Channel enable

Definition at line 3607 of file stm32f10x.h.

#define DMA_CCR7_HTIE ((uint16_t)0x0004)

Half Transfer interrupt enable

Definition at line 3609 of file stm32f10x.h.

#define DMA_CCR7_MEM2MEM ((uint16_t)0x4000)

Memory to memory mode enable

Definition at line 3628 of file stm32f10x.h.

#define DMA_CCR7_MINC ((uint16_t)0x0080)

Memory increment mode

Definition at line 3614 of file stm32f10x.h.

#define DMA_CCR7_MSIZE ((uint16_t)0x0C00)

MSIZE[1:0] bits (Memory size)

Definition at line 3620 of file stm32f10x.h.

#define DMA_CCR7_MSIZE_0 ((uint16_t)0x0400)

Bit 0

Definition at line 3621 of file stm32f10x.h.

#define DMA_CCR7_MSIZE_1 ((uint16_t)0x0800)

Bit 1

Definition at line 3622 of file stm32f10x.h.

#define DMA_CCR7_PINC ((uint16_t)0x0040)

Peripheral increment mode

Definition at line 3613 of file stm32f10x.h.

#define DMA_CCR7_PL ((uint16_t)0x3000)

PL[1:0] bits (Channel Priority level)

Definition at line 3624 of file stm32f10x.h.

#define DMA_CCR7_PL_0 ((uint16_t)0x1000)

Bit 0

Definition at line 3625 of file stm32f10x.h.

#define DMA_CCR7_PL_1 ((uint16_t)0x2000)

Bit 1

Definition at line 3626 of file stm32f10x.h.

#define DMA_CCR7_PSIZE , ((uint16_t)0x0300)

PSIZE[1:0] bits (Peripheral size)

Definition at line 3616 of file stm32f10x.h.

#define DMA_CCR7_PSIZE_0 ((uint16_t)0x0100)

Bit 0

Definition at line 3617 of file stm32f10x.h.

#define DMA_CCR7_PSIZE_1 ((uint16_t)0x0200)

Bit 1

Definition at line 3618 of file stm32f10x.h.

#define DMA_CCR7_TCIE ((uint16_t)0x0002)

Transfer complete interrupt enable

Definition at line 3608 of file stm32f10x.h.

#define DMA_CCR7_TEIE ((uint16_t)0x0008)

Transfer error interrupt enable

Definition at line 3610 of file stm32f10x.h.

#define DMA_CMAR1_MA ((uint32_t)0xFFFFFFFF)

Memory Address

Definition at line 3675 of file stm32f10x.h.

#define DMA_CMAR2_MA ((uint32_t)0xFFFFFFFF)

Memory Address

Definition at line 3678 of file stm32f10x.h.

#define DMA_CMAR3_MA ((uint32_t)0xFFFFFFFF)

Memory Address

Definition at line 3681 of file stm32f10x.h.

#define DMA_CMAR4_MA ((uint32_t)0xFFFFFFFF)

Memory Address

Definition at line 3685 of file stm32f10x.h.

#define DMA_CMAR5_MA ((uint32_t)0xFFFFFFFF)

Memory Address

Definition at line 3688 of file stm32f10x.h.

#define DMA_CMAR6_MA ((uint32_t)0xFFFFFFFF)

Memory Address

Definition at line 3691 of file stm32f10x.h.

#define DMA_CMAR7_MA ((uint32_t)0xFFFFFFFF)

Memory Address

Definition at line 3694 of file stm32f10x.h.

#define DMA_CNDTR1_NDT ((uint16_t)0xFFFF)

Number of data to Transfer

Definition at line 3631 of file stm32f10x.h.

#define DMA_CNDTR2_NDT ((uint16_t)0xFFFF)

Number of data to Transfer

Definition at line 3634 of file stm32f10x.h.

#define DMA_CNDTR3_NDT ((uint16_t)0xFFFF)

Number of data to Transfer

Definition at line 3637 of file stm32f10x.h.

#define DMA_CNDTR4_NDT ((uint16_t)0xFFFF)

Number of data to Transfer

Definition at line 3640 of file stm32f10x.h.

#define DMA_CNDTR5_NDT ((uint16_t)0xFFFF)

Number of data to Transfer

Definition at line 3643 of file stm32f10x.h.

#define DMA_CNDTR6_NDT ((uint16_t)0xFFFF)

Number of data to Transfer

Definition at line 3646 of file stm32f10x.h.

#define DMA_CNDTR7_NDT ((uint16_t)0xFFFF)

Number of data to Transfer

Definition at line 3649 of file stm32f10x.h.

#define DMA_CPAR1_PA ((uint32_t)0xFFFFFFFF)

Peripheral Address

Definition at line 3652 of file stm32f10x.h.

#define DMA_CPAR2_PA ((uint32_t)0xFFFFFFFF)

Peripheral Address

Definition at line 3655 of file stm32f10x.h.

#define DMA_CPAR3_PA ((uint32_t)0xFFFFFFFF)

Peripheral Address

Definition at line 3658 of file stm32f10x.h.

#define DMA_CPAR4_PA ((uint32_t)0xFFFFFFFF)

Peripheral Address

Definition at line 3662 of file stm32f10x.h.

#define DMA_CPAR5_PA ((uint32_t)0xFFFFFFFF)

Peripheral Address

Definition at line 3665 of file stm32f10x.h.

#define DMA_CPAR6_PA ((uint32_t)0xFFFFFFFF)

Peripheral Address

Definition at line 3668 of file stm32f10x.h.

#define DMA_CPAR7_PA ((uint32_t)0xFFFFFFFF)

Peripheral Address

Definition at line 3672 of file stm32f10x.h.

#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001)

Channel 1 Global interrupt clear

Definition at line 3433 of file stm32f10x.h.

#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010)

Channel 2 Global interrupt clear

Definition at line 3437 of file stm32f10x.h.

#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100)

Channel 3 Global interrupt clear

Definition at line 3441 of file stm32f10x.h.

#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000)

Channel 4 Global interrupt clear

Definition at line 3445 of file stm32f10x.h.

#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000)

Channel 5 Global interrupt clear

Definition at line 3449 of file stm32f10x.h.

#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000)

Channel 6 Global interrupt clear

Definition at line 3453 of file stm32f10x.h.

#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000)

Channel 7 Global interrupt clear

Definition at line 3457 of file stm32f10x.h.

#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004)

Channel 1 Half Transfer clear

Definition at line 3435 of file stm32f10x.h.

#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040)

Channel 2 Half Transfer clear

Definition at line 3439 of file stm32f10x.h.

#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400)

Channel 3 Half Transfer clear

Definition at line 3443 of file stm32f10x.h.

#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000)

Channel 4 Half Transfer clear

Definition at line 3447 of file stm32f10x.h.

#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000)

Channel 5 Half Transfer clear

Definition at line 3451 of file stm32f10x.h.

#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000)

Channel 6 Half Transfer clear

Definition at line 3455 of file stm32f10x.h.

#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000)

Channel 7 Half Transfer clear

Definition at line 3459 of file stm32f10x.h.

#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002)

Channel 1 Transfer Complete clear

Definition at line 3434 of file stm32f10x.h.

#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020)

Channel 2 Transfer Complete clear

Definition at line 3438 of file stm32f10x.h.

#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200)

Channel 3 Transfer Complete clear

Definition at line 3442 of file stm32f10x.h.

#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000)

Channel 4 Transfer Complete clear

Definition at line 3446 of file stm32f10x.h.

#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000)

Channel 5 Transfer Complete clear

Definition at line 3450 of file stm32f10x.h.

#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000)

Channel 6 Transfer Complete clear

Definition at line 3454 of file stm32f10x.h.

#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000)

Channel 7 Transfer Complete clear

Definition at line 3458 of file stm32f10x.h.

#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008)

Channel 1 Transfer Error clear

Definition at line 3436 of file stm32f10x.h.

#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080)

Channel 2 Transfer Error clear

Definition at line 3440 of file stm32f10x.h.

#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800)

Channel 3 Transfer Error clear

Definition at line 3444 of file stm32f10x.h.

#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000)

Channel 4 Transfer Error clear

Definition at line 3448 of file stm32f10x.h.

#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000)

Channel 5 Transfer Error clear

Definition at line 3452 of file stm32f10x.h.

#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000)

Channel 6 Transfer Error clear

Definition at line 3456 of file stm32f10x.h.

#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000)

Channel 7 Transfer Error clear

Definition at line 3460 of file stm32f10x.h.

#define DMA_ISR_GIF1 ((uint32_t)0x00000001)

Channel 1 Global interrupt flag

Definition at line 3403 of file stm32f10x.h.

#define DMA_ISR_GIF2 ((uint32_t)0x00000010)

Channel 2 Global interrupt flag

Definition at line 3407 of file stm32f10x.h.

#define DMA_ISR_GIF3 ((uint32_t)0x00000100)

Channel 3 Global interrupt flag

Definition at line 3411 of file stm32f10x.h.

#define DMA_ISR_GIF4 ((uint32_t)0x00001000)

Channel 4 Global interrupt flag

Definition at line 3415 of file stm32f10x.h.

#define DMA_ISR_GIF5 ((uint32_t)0x00010000)

Channel 5 Global interrupt flag

Definition at line 3419 of file stm32f10x.h.

#define DMA_ISR_GIF6 ((uint32_t)0x00100000)

Channel 6 Global interrupt flag

Definition at line 3423 of file stm32f10x.h.

#define DMA_ISR_GIF7 ((uint32_t)0x01000000)

Channel 7 Global interrupt flag

Definition at line 3427 of file stm32f10x.h.

#define DMA_ISR_HTIF1 ((uint32_t)0x00000004)

Channel 1 Half Transfer flag

Definition at line 3405 of file stm32f10x.h.

#define DMA_ISR_HTIF2 ((uint32_t)0x00000040)

Channel 2 Half Transfer flag

Definition at line 3409 of file stm32f10x.h.

#define DMA_ISR_HTIF3 ((uint32_t)0x00000400)

Channel 3 Half Transfer flag

Definition at line 3413 of file stm32f10x.h.

#define DMA_ISR_HTIF4 ((uint32_t)0x00004000)

Channel 4 Half Transfer flag

Definition at line 3417 of file stm32f10x.h.

#define DMA_ISR_HTIF5 ((uint32_t)0x00040000)

Channel 5 Half Transfer flag

Definition at line 3421 of file stm32f10x.h.

#define DMA_ISR_HTIF6 ((uint32_t)0x00400000)

Channel 6 Half Transfer flag

Definition at line 3425 of file stm32f10x.h.

#define DMA_ISR_HTIF7 ((uint32_t)0x04000000)

Channel 7 Half Transfer flag

Definition at line 3429 of file stm32f10x.h.

#define DMA_ISR_TCIF1 ((uint32_t)0x00000002)

Channel 1 Transfer Complete flag

Definition at line 3404 of file stm32f10x.h.

#define DMA_ISR_TCIF2 ((uint32_t)0x00000020)

Channel 2 Transfer Complete flag

Definition at line 3408 of file stm32f10x.h.

#define DMA_ISR_TCIF3 ((uint32_t)0x00000200)

Channel 3 Transfer Complete flag

Definition at line 3412 of file stm32f10x.h.

#define DMA_ISR_TCIF4 ((uint32_t)0x00002000)

Channel 4 Transfer Complete flag

Definition at line 3416 of file stm32f10x.h.

#define DMA_ISR_TCIF5 ((uint32_t)0x00020000)

Channel 5 Transfer Complete flag

Definition at line 3420 of file stm32f10x.h.

#define DMA_ISR_TCIF6 ((uint32_t)0x00200000)

Channel 6 Transfer Complete flag

Definition at line 3424 of file stm32f10x.h.

#define DMA_ISR_TCIF7 ((uint32_t)0x02000000)

Channel 7 Transfer Complete flag

Definition at line 3428 of file stm32f10x.h.

#define DMA_ISR_TEIF1 ((uint32_t)0x00000008)

Channel 1 Transfer Error flag

Definition at line 3406 of file stm32f10x.h.

#define DMA_ISR_TEIF2 ((uint32_t)0x00000080)

Channel 2 Transfer Error flag

Definition at line 3410 of file stm32f10x.h.

#define DMA_ISR_TEIF3 ((uint32_t)0x00000800)

Channel 3 Transfer Error flag

Definition at line 3414 of file stm32f10x.h.

#define DMA_ISR_TEIF4 ((uint32_t)0x00008000)

Channel 4 Transfer Error flag

Definition at line 3418 of file stm32f10x.h.

#define DMA_ISR_TEIF5 ((uint32_t)0x00080000)

Channel 5 Transfer Error flag

Definition at line 3422 of file stm32f10x.h.

#define DMA_ISR_TEIF6 ((uint32_t)0x00800000)

Channel 6 Transfer Error flag

Definition at line 3426 of file stm32f10x.h.

#define DMA_ISR_TEIF7 ((uint32_t)0x08000000)

Channel 7 Transfer Error flag

Definition at line 3430 of file stm32f10x.h.

#define EXTI_EMR_MR0 ((uint32_t)0x00000001)

Event Mask on line 0

Definition at line 3287 of file stm32f10x.h.

#define EXTI_EMR_MR1 ((uint32_t)0x00000002)

Event Mask on line 1

Definition at line 3288 of file stm32f10x.h.

#define EXTI_EMR_MR10 ((uint32_t)0x00000400)

Event Mask on line 10

Definition at line 3297 of file stm32f10x.h.

#define EXTI_EMR_MR11 ((uint32_t)0x00000800)

Event Mask on line 11

Definition at line 3298 of file stm32f10x.h.

#define EXTI_EMR_MR12 ((uint32_t)0x00001000)

Event Mask on line 12

Definition at line 3299 of file stm32f10x.h.

#define EXTI_EMR_MR13 ((uint32_t)0x00002000)

Event Mask on line 13

Definition at line 3300 of file stm32f10x.h.

#define EXTI_EMR_MR14 ((uint32_t)0x00004000)

Event Mask on line 14

Definition at line 3301 of file stm32f10x.h.

#define EXTI_EMR_MR15 ((uint32_t)0x00008000)

Event Mask on line 15

Definition at line 3302 of file stm32f10x.h.

#define EXTI_EMR_MR16 ((uint32_t)0x00010000)

Event Mask on line 16

Definition at line 3303 of file stm32f10x.h.

#define EXTI_EMR_MR17 ((uint32_t)0x00020000)

Event Mask on line 17

Definition at line 3304 of file stm32f10x.h.

#define EXTI_EMR_MR18 ((uint32_t)0x00040000)

Event Mask on line 18

Definition at line 3305 of file stm32f10x.h.

#define EXTI_EMR_MR19 ((uint32_t)0x00080000)

Event Mask on line 19

Definition at line 3306 of file stm32f10x.h.

#define EXTI_EMR_MR2 ((uint32_t)0x00000004)

Event Mask on line 2

Definition at line 3289 of file stm32f10x.h.

#define EXTI_EMR_MR3 ((uint32_t)0x00000008)

Event Mask on line 3

Definition at line 3290 of file stm32f10x.h.

#define EXTI_EMR_MR4 ((uint32_t)0x00000010)

Event Mask on line 4

Definition at line 3291 of file stm32f10x.h.

#define EXTI_EMR_MR5 ((uint32_t)0x00000020)

Event Mask on line 5

Definition at line 3292 of file stm32f10x.h.

#define EXTI_EMR_MR6 ((uint32_t)0x00000040)

Event Mask on line 6

Definition at line 3293 of file stm32f10x.h.

#define EXTI_EMR_MR7 ((uint32_t)0x00000080)

Event Mask on line 7

Definition at line 3294 of file stm32f10x.h.

#define EXTI_EMR_MR8 ((uint32_t)0x00000100)

Event Mask on line 8

Definition at line 3295 of file stm32f10x.h.

#define EXTI_EMR_MR9 ((uint32_t)0x00000200)

Event Mask on line 9

Definition at line 3296 of file stm32f10x.h.

#define EXTI_FTSR_TR0 ((uint32_t)0x00000001)

Falling trigger event configuration bit of line 0

Definition at line 3331 of file stm32f10x.h.

#define EXTI_FTSR_TR1 ((uint32_t)0x00000002)

Falling trigger event configuration bit of line 1

Definition at line 3332 of file stm32f10x.h.

#define EXTI_FTSR_TR10 ((uint32_t)0x00000400)

Falling trigger event configuration bit of line 10

Definition at line 3341 of file stm32f10x.h.

#define EXTI_FTSR_TR11 ((uint32_t)0x00000800)

Falling trigger event configuration bit of line 11

Definition at line 3342 of file stm32f10x.h.

#define EXTI_FTSR_TR12 ((uint32_t)0x00001000)

Falling trigger event configuration bit of line 12

Definition at line 3343 of file stm32f10x.h.

#define EXTI_FTSR_TR13 ((uint32_t)0x00002000)

Falling trigger event configuration bit of line 13

Definition at line 3344 of file stm32f10x.h.

#define EXTI_FTSR_TR14 ((uint32_t)0x00004000)

Falling trigger event configuration bit of line 14

Definition at line 3345 of file stm32f10x.h.

#define EXTI_FTSR_TR15 ((uint32_t)0x00008000)

Falling trigger event configuration bit of line 15

Definition at line 3346 of file stm32f10x.h.

#define EXTI_FTSR_TR16 ((uint32_t)0x00010000)

Falling trigger event configuration bit of line 16

Definition at line 3347 of file stm32f10x.h.

#define EXTI_FTSR_TR17 ((uint32_t)0x00020000)

Falling trigger event configuration bit of line 17

Definition at line 3348 of file stm32f10x.h.

#define EXTI_FTSR_TR18 ((uint32_t)0x00040000)

Falling trigger event configuration bit of line 18

Definition at line 3349 of file stm32f10x.h.

#define EXTI_FTSR_TR19 ((uint32_t)0x00080000)

Falling trigger event configuration bit of line 19

Definition at line 3350 of file stm32f10x.h.

#define EXTI_FTSR_TR2 ((uint32_t)0x00000004)

Falling trigger event configuration bit of line 2

Definition at line 3333 of file stm32f10x.h.

#define EXTI_FTSR_TR3 ((uint32_t)0x00000008)

Falling trigger event configuration bit of line 3

Definition at line 3334 of file stm32f10x.h.

#define EXTI_FTSR_TR4 ((uint32_t)0x00000010)

Falling trigger event configuration bit of line 4

Definition at line 3335 of file stm32f10x.h.

#define EXTI_FTSR_TR5 ((uint32_t)0x00000020)

Falling trigger event configuration bit of line 5

Definition at line 3336 of file stm32f10x.h.

#define EXTI_FTSR_TR6 ((uint32_t)0x00000040)

Falling trigger event configuration bit of line 6

Definition at line 3337 of file stm32f10x.h.

#define EXTI_FTSR_TR7 ((uint32_t)0x00000080)

Falling trigger event configuration bit of line 7

Definition at line 3338 of file stm32f10x.h.

#define EXTI_FTSR_TR8 ((uint32_t)0x00000100)

Falling trigger event configuration bit of line 8

Definition at line 3339 of file stm32f10x.h.

#define EXTI_FTSR_TR9 ((uint32_t)0x00000200)

Falling trigger event configuration bit of line 9

Definition at line 3340 of file stm32f10x.h.

#define EXTI_IMR_MR0 ((uint32_t)0x00000001)

Interrupt Mask on line 0

Definition at line 3265 of file stm32f10x.h.

#define EXTI_IMR_MR1 ((uint32_t)0x00000002)

Interrupt Mask on line 1

Definition at line 3266 of file stm32f10x.h.

#define EXTI_IMR_MR10 ((uint32_t)0x00000400)

Interrupt Mask on line 10

Definition at line 3275 of file stm32f10x.h.

#define EXTI_IMR_MR11 ((uint32_t)0x00000800)

Interrupt Mask on line 11

Definition at line 3276 of file stm32f10x.h.

#define EXTI_IMR_MR12 ((uint32_t)0x00001000)

Interrupt Mask on line 12

Definition at line 3277 of file stm32f10x.h.

#define EXTI_IMR_MR13 ((uint32_t)0x00002000)

Interrupt Mask on line 13

Definition at line 3278 of file stm32f10x.h.

#define EXTI_IMR_MR14 ((uint32_t)0x00004000)

Interrupt Mask on line 14

Definition at line 3279 of file stm32f10x.h.

#define EXTI_IMR_MR15 ((uint32_t)0x00008000)

Interrupt Mask on line 15

Definition at line 3280 of file stm32f10x.h.

#define EXTI_IMR_MR16 ((uint32_t)0x00010000)

Interrupt Mask on line 16

Definition at line 3281 of file stm32f10x.h.

#define EXTI_IMR_MR17 ((uint32_t)0x00020000)

Interrupt Mask on line 17

Definition at line 3282 of file stm32f10x.h.

#define EXTI_IMR_MR18 ((uint32_t)0x00040000)

Interrupt Mask on line 18

Definition at line 3283 of file stm32f10x.h.

#define EXTI_IMR_MR19 ((uint32_t)0x00080000)

Interrupt Mask on line 19

Definition at line 3284 of file stm32f10x.h.

#define EXTI_IMR_MR2 ((uint32_t)0x00000004)

Interrupt Mask on line 2

Definition at line 3267 of file stm32f10x.h.

#define EXTI_IMR_MR3 ((uint32_t)0x00000008)

Interrupt Mask on line 3

Definition at line 3268 of file stm32f10x.h.

#define EXTI_IMR_MR4 ((uint32_t)0x00000010)

Interrupt Mask on line 4

Definition at line 3269 of file stm32f10x.h.

#define EXTI_IMR_MR5 ((uint32_t)0x00000020)

Interrupt Mask on line 5

Definition at line 3270 of file stm32f10x.h.

#define EXTI_IMR_MR6 ((uint32_t)0x00000040)

Interrupt Mask on line 6

Definition at line 3271 of file stm32f10x.h.

#define EXTI_IMR_MR7 ((uint32_t)0x00000080)

Interrupt Mask on line 7

Definition at line 3272 of file stm32f10x.h.

#define EXTI_IMR_MR8 ((uint32_t)0x00000100)

Interrupt Mask on line 8

Definition at line 3273 of file stm32f10x.h.

#define EXTI_IMR_MR9 ((uint32_t)0x00000200)

Interrupt Mask on line 9

Definition at line 3274 of file stm32f10x.h.

#define EXTI_PR_PR0 ((uint32_t)0x00000001)

Pending bit for line 0

Definition at line 3375 of file stm32f10x.h.

#define EXTI_PR_PR1 ((uint32_t)0x00000002)

Pending bit for line 1

Definition at line 3376 of file stm32f10x.h.

#define EXTI_PR_PR10 ((uint32_t)0x00000400)

Pending bit for line 10

Definition at line 3385 of file stm32f10x.h.

#define EXTI_PR_PR11 ((uint32_t)0x00000800)

Pending bit for line 11

Definition at line 3386 of file stm32f10x.h.

#define EXTI_PR_PR12 ((uint32_t)0x00001000)

Pending bit for line 12

Definition at line 3387 of file stm32f10x.h.

#define EXTI_PR_PR13 ((uint32_t)0x00002000)

Pending bit for line 13

Definition at line 3388 of file stm32f10x.h.

#define EXTI_PR_PR14 ((uint32_t)0x00004000)

Pending bit for line 14

Definition at line 3389 of file stm32f10x.h.

#define EXTI_PR_PR15 ((uint32_t)0x00008000)

Pending bit for line 15

Definition at line 3390 of file stm32f10x.h.

#define EXTI_PR_PR16 ((uint32_t)0x00010000)

Pending bit for line 16

Definition at line 3391 of file stm32f10x.h.

#define EXTI_PR_PR17 ((uint32_t)0x00020000)

Pending bit for line 17

Definition at line 3392 of file stm32f10x.h.

#define EXTI_PR_PR18 ((uint32_t)0x00040000)

Pending bit for line 18

Definition at line 3393 of file stm32f10x.h.

#define EXTI_PR_PR19 ((uint32_t)0x00080000)

Pending bit for line 19

Definition at line 3394 of file stm32f10x.h.

#define EXTI_PR_PR2 ((uint32_t)0x00000004)

Pending bit for line 2

Definition at line 3377 of file stm32f10x.h.

#define EXTI_PR_PR3 ((uint32_t)0x00000008)

Pending bit for line 3

Definition at line 3378 of file stm32f10x.h.

#define EXTI_PR_PR4 ((uint32_t)0x00000010)

Pending bit for line 4

Definition at line 3379 of file stm32f10x.h.

#define EXTI_PR_PR5 ((uint32_t)0x00000020)

Pending bit for line 5

Definition at line 3380 of file stm32f10x.h.

#define EXTI_PR_PR6 ((uint32_t)0x00000040)

Pending bit for line 6

Definition at line 3381 of file stm32f10x.h.

#define EXTI_PR_PR7 ((uint32_t)0x00000080)

Pending bit for line 7

Definition at line 3382 of file stm32f10x.h.

#define EXTI_PR_PR8 ((uint32_t)0x00000100)

Pending bit for line 8

Definition at line 3383 of file stm32f10x.h.

#define EXTI_PR_PR9 ((uint32_t)0x00000200)

Pending bit for line 9

Definition at line 3384 of file stm32f10x.h.

#define EXTI_RTSR_TR0 ((uint32_t)0x00000001)

Rising trigger event configuration bit of line 0

Definition at line 3309 of file stm32f10x.h.

#define EXTI_RTSR_TR1 ((uint32_t)0x00000002)

Rising trigger event configuration bit of line 1

Definition at line 3310 of file stm32f10x.h.

#define EXTI_RTSR_TR10 ((uint32_t)0x00000400)

Rising trigger event configuration bit of line 10

Definition at line 3319 of file stm32f10x.h.

#define EXTI_RTSR_TR11 ((uint32_t)0x00000800)

Rising trigger event configuration bit of line 11

Definition at line 3320 of file stm32f10x.h.

#define EXTI_RTSR_TR12 ((uint32_t)0x00001000)

Rising trigger event configuration bit of line 12

Definition at line 3321 of file stm32f10x.h.

#define EXTI_RTSR_TR13 ((uint32_t)0x00002000)

Rising trigger event configuration bit of line 13

Definition at line 3322 of file stm32f10x.h.

#define EXTI_RTSR_TR14 ((uint32_t)0x00004000)

Rising trigger event configuration bit of line 14

Definition at line 3323 of file stm32f10x.h.

#define EXTI_RTSR_TR15 ((uint32_t)0x00008000)

Rising trigger event configuration bit of line 15

Definition at line 3324 of file stm32f10x.h.

#define EXTI_RTSR_TR16 ((uint32_t)0x00010000)

Rising trigger event configuration bit of line 16

Definition at line 3325 of file stm32f10x.h.

#define EXTI_RTSR_TR17 ((uint32_t)0x00020000)

Rising trigger event configuration bit of line 17

Definition at line 3326 of file stm32f10x.h.

#define EXTI_RTSR_TR18 ((uint32_t)0x00040000)

Rising trigger event configuration bit of line 18

Definition at line 3327 of file stm32f10x.h.

#define EXTI_RTSR_TR19 ((uint32_t)0x00080000)

Rising trigger event configuration bit of line 19

Definition at line 3328 of file stm32f10x.h.

#define EXTI_RTSR_TR2 ((uint32_t)0x00000004)

Rising trigger event configuration bit of line 2

Definition at line 3311 of file stm32f10x.h.

#define EXTI_RTSR_TR3 ((uint32_t)0x00000008)

Rising trigger event configuration bit of line 3

Definition at line 3312 of file stm32f10x.h.

#define EXTI_RTSR_TR4 ((uint32_t)0x00000010)

Rising trigger event configuration bit of line 4

Definition at line 3313 of file stm32f10x.h.

#define EXTI_RTSR_TR5 ((uint32_t)0x00000020)

Rising trigger event configuration bit of line 5

Definition at line 3314 of file stm32f10x.h.

#define EXTI_RTSR_TR6 ((uint32_t)0x00000040)

Rising trigger event configuration bit of line 6

Definition at line 3315 of file stm32f10x.h.

#define EXTI_RTSR_TR7 ((uint32_t)0x00000080)

Rising trigger event configuration bit of line 7

Definition at line 3316 of file stm32f10x.h.

#define EXTI_RTSR_TR8 ((uint32_t)0x00000100)

Rising trigger event configuration bit of line 8

Definition at line 3317 of file stm32f10x.h.

#define EXTI_RTSR_TR9 ((uint32_t)0x00000200)

Rising trigger event configuration bit of line 9

Definition at line 3318 of file stm32f10x.h.

#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001)

Software Interrupt on line 0

Definition at line 3353 of file stm32f10x.h.

#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002)

Software Interrupt on line 1

Definition at line 3354 of file stm32f10x.h.

#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400)

Software Interrupt on line 10

Definition at line 3363 of file stm32f10x.h.

#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800)

Software Interrupt on line 11

Definition at line 3364 of file stm32f10x.h.

#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000)

Software Interrupt on line 12

Definition at line 3365 of file stm32f10x.h.

#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000)

Software Interrupt on line 13

Definition at line 3366 of file stm32f10x.h.

#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000)

Software Interrupt on line 14

Definition at line 3367 of file stm32f10x.h.

#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000)

Software Interrupt on line 15

Definition at line 3368 of file stm32f10x.h.

#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000)

Software Interrupt on line 16

Definition at line 3369 of file stm32f10x.h.

#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000)

Software Interrupt on line 17

Definition at line 3370 of file stm32f10x.h.

#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000)

Software Interrupt on line 18

Definition at line 3371 of file stm32f10x.h.

#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000)

Software Interrupt on line 19

Definition at line 3372 of file stm32f10x.h.

#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004)

Software Interrupt on line 2

Definition at line 3355 of file stm32f10x.h.

#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008)

Software Interrupt on line 3

Definition at line 3356 of file stm32f10x.h.

#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010)

Software Interrupt on line 4

Definition at line 3357 of file stm32f10x.h.

#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020)

Software Interrupt on line 5

Definition at line 3358 of file stm32f10x.h.

#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040)

Software Interrupt on line 6

Definition at line 3359 of file stm32f10x.h.

#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080)

Software Interrupt on line 7

Definition at line 3360 of file stm32f10x.h.

#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100)

Software Interrupt on line 8

Definition at line 3361 of file stm32f10x.h.

#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200)

Software Interrupt on line 9

Definition at line 3362 of file stm32f10x.h.

#define FLASH_ACR_HLFCYA ((uint8_t)0x08)

Flash Half Cycle Access Enable

Definition at line 7796 of file stm32f10x.h.

#define FLASH_ACR_LATENCY ((uint8_t)0x03)

LATENCY[2:0] bits (Latency)

Definition at line 7791 of file stm32f10x.h.

Referenced by SetSysClockTo56(), and SetSysClockTo72().

#define FLASH_ACR_LATENCY_0 ((uint8_t)0x00)

Bit 0

Definition at line 7792 of file stm32f10x.h.

#define FLASH_ACR_LATENCY_1 ((uint8_t)0x01)

Bit 0

Definition at line 7793 of file stm32f10x.h.

#define FLASH_ACR_LATENCY_2 ((uint8_t)0x02)

Bit 1

Definition at line 7794 of file stm32f10x.h.

Referenced by SetSysClockTo56(), and SetSysClockTo72().

#define FLASH_ACR_PRFTBE ((uint8_t)0x10)

Prefetch Buffer Enable

Definition at line 7797 of file stm32f10x.h.

Referenced by SetSysClockTo56(), and SetSysClockTo72().

#define FLASH_ACR_PRFTBS ((uint8_t)0x20)

Prefetch Buffer Status

Definition at line 7798 of file stm32f10x.h.

#define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF)

Flash Address

Definition at line 7825 of file stm32f10x.h.

#define FLASH_CR_EOPIE ((uint16_t)0x1000)

End of operation interrupt enable

Definition at line 7822 of file stm32f10x.h.

#define FLASH_CR_ERRIE ((uint16_t)0x0400)

Error Interrupt Enable

Definition at line 7821 of file stm32f10x.h.

#define FLASH_CR_LOCK ((uint16_t)0x0080)

Lock

Definition at line 7819 of file stm32f10x.h.

#define FLASH_CR_MER ((uint16_t)0x0004)

Mass Erase

Definition at line 7815 of file stm32f10x.h.

#define FLASH_CR_OPTER ((uint16_t)0x0020)

Option Byte Erase

Definition at line 7817 of file stm32f10x.h.

#define FLASH_CR_OPTPG ((uint16_t)0x0010)

Option Byte Programming

Definition at line 7816 of file stm32f10x.h.

#define FLASH_CR_OPTWRE ((uint16_t)0x0200)

Option Bytes Write Enable

Definition at line 7820 of file stm32f10x.h.

#define FLASH_CR_PER ((uint16_t)0x0002)

Page Erase

Definition at line 7814 of file stm32f10x.h.

#define FLASH_CR_PG ((uint16_t)0x0001)

Programming

Definition at line 7813 of file stm32f10x.h.

#define FLASH_CR_STRT ((uint16_t)0x0040)

Start

Definition at line 7818 of file stm32f10x.h.

#define FLASH_Data0_Data0 ((uint32_t)0x000000FF)

User data storage option byte

Definition at line 7851 of file stm32f10x.h.

#define FLASH_Data0_nData0 ((uint32_t)0x0000FF00)

User data storage complemented option byte

Definition at line 7852 of file stm32f10x.h.

#define FLASH_Data1_Data1 ((uint32_t)0x00FF0000)

User data storage option byte

Definition at line 7855 of file stm32f10x.h.

#define FLASH_Data1_nData1 ((uint32_t)0xFF000000)

User data storage complemented option byte

Definition at line 7856 of file stm32f10x.h.

#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF)

FPEC Key

Definition at line 7801 of file stm32f10x.h.

#define FLASH_OBR_BFB2 ((uint16_t)0x0020)

BFB2

Definition at line 7835 of file stm32f10x.h.

#define FLASH_OBR_nRST_STDBY ((uint16_t)0x0010)

nRST_STDBY

Definition at line 7834 of file stm32f10x.h.

#define FLASH_OBR_nRST_STOP ((uint16_t)0x0008)

nRST_STOP

Definition at line 7833 of file stm32f10x.h.

#define FLASH_OBR_OPTERR ((uint16_t)0x0001)

Option Byte Error

Definition at line 7828 of file stm32f10x.h.

#define FLASH_OBR_RDPRT ((uint16_t)0x0002)

Read protection

Definition at line 7829 of file stm32f10x.h.

#define FLASH_OBR_USER ((uint16_t)0x03FC)

User Option Bytes

Definition at line 7831 of file stm32f10x.h.

#define FLASH_OBR_WDG_SW ((uint16_t)0x0004)

WDG_SW

Definition at line 7832 of file stm32f10x.h.

#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF)

Option Byte Key

Definition at line 7804 of file stm32f10x.h.

#define FLASH_RDP_nRDP ((uint32_t)0x0000FF00)

Read protection complemented option byte

Definition at line 7844 of file stm32f10x.h.

#define FLASH_RDP_RDP ((uint32_t)0x000000FF)

Read protection option byte

Definition at line 7843 of file stm32f10x.h.

#define FLASH_SR_BSY ((uint8_t)0x01)

Busy

Definition at line 7807 of file stm32f10x.h.

#define FLASH_SR_EOP ((uint8_t)0x20)

End of operation

Definition at line 7810 of file stm32f10x.h.

#define FLASH_SR_PGERR ((uint8_t)0x04)

Programming Error

Definition at line 7808 of file stm32f10x.h.

#define FLASH_SR_WRPRTERR ((uint8_t)0x10)

Write Protection Error

Definition at line 7809 of file stm32f10x.h.

#define FLASH_USER_nUSER ((uint32_t)0xFF000000)

User complemented option byte

Definition at line 7848 of file stm32f10x.h.

#define FLASH_USER_USER ((uint32_t)0x00FF0000)

User option byte

Definition at line 7847 of file stm32f10x.h.

#define FLASH_WRP0_nWRP0 ((uint32_t)0x0000FF00)

Flash memory write protection complemented option bytes

Definition at line 7860 of file stm32f10x.h.

#define FLASH_WRP0_WRP0 ((uint32_t)0x000000FF)

Flash memory write protection option bytes

Definition at line 7859 of file stm32f10x.h.

#define FLASH_WRP1_nWRP1 ((uint32_t)0xFF000000)

Flash memory write protection complemented option bytes

Definition at line 7864 of file stm32f10x.h.

#define FLASH_WRP1_WRP1 ((uint32_t)0x00FF0000)

Flash memory write protection option bytes

Definition at line 7863 of file stm32f10x.h.

#define FLASH_WRP2_nWRP2 ((uint32_t)0x0000FF00)

Flash memory write protection complemented option bytes

Definition at line 7868 of file stm32f10x.h.

#define FLASH_WRP2_WRP2 ((uint32_t)0x000000FF)

Flash memory write protection option bytes

Definition at line 7867 of file stm32f10x.h.

#define FLASH_WRP3_nWRP3 ((uint32_t)0xFF000000)

Flash memory write protection complemented option bytes

Definition at line 7872 of file stm32f10x.h.

#define FLASH_WRP3_WRP3 ((uint32_t)0x00FF0000)

Flash memory write protection option bytes

Definition at line 7871 of file stm32f10x.h.

#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF)

Write Protect

Definition at line 7838 of file stm32f10x.h.

#define FSMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000)

Asynchronous wait

Definition at line 4604 of file stm32f10x.h.

#define FSMC_BCR1_BURSTEN ((uint32_t)0x00000100)

Burst enable bit

Definition at line 4597 of file stm32f10x.h.

#define FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000)

Write burst enable

Definition at line 4605 of file stm32f10x.h.

#define FSMC_BCR1_EXTMOD ((uint32_t)0x00004000)

Extended mode enable

Definition at line 4603 of file stm32f10x.h.

#define FSMC_BCR1_FACCEN ((uint32_t)0x00000040)

Flash access enable

Definition at line 4596 of file stm32f10x.h.

#define FSMC_BCR1_MBKEN ((uint32_t)0x00000001)

Memory bank enable bit

Definition at line 4585 of file stm32f10x.h.

#define FSMC_BCR1_MTYP ((uint32_t)0x0000000C)

MTYP[1:0] bits (Memory type)

Definition at line 4588 of file stm32f10x.h.

#define FSMC_BCR1_MTYP_0 ((uint32_t)0x00000004)

Bit 0

Definition at line 4589 of file stm32f10x.h.

#define FSMC_BCR1_MTYP_1 ((uint32_t)0x00000008)

Bit 1

Definition at line 4590 of file stm32f10x.h.

#define FSMC_BCR1_MUXEN ((uint32_t)0x00000002)

Address/data multiplexing enable bit

Definition at line 4586 of file stm32f10x.h.

#define FSMC_BCR1_MWID ((uint32_t)0x00000030)

MWID[1:0] bits (Memory data bus width)

Definition at line 4592 of file stm32f10x.h.

#define FSMC_BCR1_MWID_0 ((uint32_t)0x00000010)

Bit 0

Definition at line 4593 of file stm32f10x.h.

#define FSMC_BCR1_MWID_1 ((uint32_t)0x00000020)

Bit 1

Definition at line 4594 of file stm32f10x.h.

#define FSMC_BCR1_WAITCFG ((uint32_t)0x00000800)

Wait timing configuration

Definition at line 4600 of file stm32f10x.h.

#define FSMC_BCR1_WAITEN ((uint32_t)0x00002000)

Wait enable bit

Definition at line 4602 of file stm32f10x.h.

#define FSMC_BCR1_WAITPOL ((uint32_t)0x00000200)

Wait signal polarity bit

Definition at line 4598 of file stm32f10x.h.

#define FSMC_BCR1_WRAPMOD ((uint32_t)0x00000400)

Wrapped burst mode support

Definition at line 4599 of file stm32f10x.h.

#define FSMC_BCR1_WREN ((uint32_t)0x00001000)

Write enable bit

Definition at line 4601 of file stm32f10x.h.

#define FSMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000)

Asynchronous wait

Definition at line 4627 of file stm32f10x.h.

#define FSMC_BCR2_BURSTEN ((uint32_t)0x00000100)

Burst enable bit

Definition at line 4620 of file stm32f10x.h.

#define FSMC_BCR2_CBURSTRW ((uint32_t)0x00080000)

Write burst enable

Definition at line 4628 of file stm32f10x.h.

#define FSMC_BCR2_EXTMOD ((uint32_t)0x00004000)

Extended mode enable

Definition at line 4626 of file stm32f10x.h.

#define FSMC_BCR2_FACCEN ((uint32_t)0x00000040)

Flash access enable

Definition at line 4619 of file stm32f10x.h.

#define FSMC_BCR2_MBKEN ((uint32_t)0x00000001)

Memory bank enable bit

Definition at line 4608 of file stm32f10x.h.

#define FSMC_BCR2_MTYP ((uint32_t)0x0000000C)

MTYP[1:0] bits (Memory type)

Definition at line 4611 of file stm32f10x.h.

#define FSMC_BCR2_MTYP_0 ((uint32_t)0x00000004)

Bit 0

Definition at line 4612 of file stm32f10x.h.

#define FSMC_BCR2_MTYP_1 ((uint32_t)0x00000008)

Bit 1

Definition at line 4613 of file stm32f10x.h.

#define FSMC_BCR2_MUXEN ((uint32_t)0x00000002)

Address/data multiplexing enable bit

Definition at line 4609 of file stm32f10x.h.

#define FSMC_BCR2_MWID ((uint32_t)0x00000030)

MWID[1:0] bits (Memory data bus width)

Definition at line 4615 of file stm32f10x.h.

#define FSMC_BCR2_MWID_0 ((uint32_t)0x00000010)

Bit 0

Definition at line 4616 of file stm32f10x.h.

#define FSMC_BCR2_MWID_1 ((uint32_t)0x00000020)

Bit 1

Definition at line 4617 of file stm32f10x.h.

#define FSMC_BCR2_WAITCFG ((uint32_t)0x00000800)

Wait timing configuration

Definition at line 4623 of file stm32f10x.h.

#define FSMC_BCR2_WAITEN ((uint32_t)0x00002000)

Wait enable bit

Definition at line 4625 of file stm32f10x.h.

#define FSMC_BCR2_WAITPOL ((uint32_t)0x00000200)

Wait signal polarity bit

Definition at line 4621 of file stm32f10x.h.

#define FSMC_BCR2_WRAPMOD ((uint32_t)0x00000400)

Wrapped burst mode support

Definition at line 4622 of file stm32f10x.h.

#define FSMC_BCR2_WREN ((uint32_t)0x00001000)

Write enable bit

Definition at line 4624 of file stm32f10x.h.

#define FSMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000)

Asynchronous wait

Definition at line 4650 of file stm32f10x.h.

#define FSMC_BCR3_BURSTEN ((uint32_t)0x00000100)

Burst enable bit

Definition at line 4643 of file stm32f10x.h.

#define FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000)

Write burst enable

Definition at line 4651 of file stm32f10x.h.

#define FSMC_BCR3_EXTMOD ((uint32_t)0x00004000)

Extended mode enable

Definition at line 4649 of file stm32f10x.h.

#define FSMC_BCR3_FACCEN ((uint32_t)0x00000040)

Flash access enable

Definition at line 4642 of file stm32f10x.h.

#define FSMC_BCR3_MBKEN ((uint32_t)0x00000001)

Memory bank enable bit

Definition at line 4631 of file stm32f10x.h.

#define FSMC_BCR3_MTYP ((uint32_t)0x0000000C)

MTYP[1:0] bits (Memory type)

Definition at line 4634 of file stm32f10x.h.

#define FSMC_BCR3_MTYP_0 ((uint32_t)0x00000004)

Bit 0

Definition at line 4635 of file stm32f10x.h.

#define FSMC_BCR3_MTYP_1 ((uint32_t)0x00000008)

Bit 1

Definition at line 4636 of file stm32f10x.h.

#define FSMC_BCR3_MUXEN ((uint32_t)0x00000002)

Address/data multiplexing enable bit

Definition at line 4632 of file stm32f10x.h.

#define FSMC_BCR3_MWID ((uint32_t)0x00000030)

MWID[1:0] bits (Memory data bus width)

Definition at line 4638 of file stm32f10x.h.

#define FSMC_BCR3_MWID_0 ((uint32_t)0x00000010)

Bit 0

Definition at line 4639 of file stm32f10x.h.

#define FSMC_BCR3_MWID_1 ((uint32_t)0x00000020)

Bit 1

Definition at line 4640 of file stm32f10x.h.

#define FSMC_BCR3_WAITCFG ((uint32_t)0x00000800)

Wait timing configuration

Definition at line 4646 of file stm32f10x.h.

#define FSMC_BCR3_WAITEN ((uint32_t)0x00002000)

Wait enable bit

Definition at line 4648 of file stm32f10x.h.

#define FSMC_BCR3_WAITPOL ((uint32_t)0x00000200)

Wait signal polarity bit.

Definition at line 4644 of file stm32f10x.h.

#define FSMC_BCR3_WRAPMOD ((uint32_t)0x00000400)

Wrapped burst mode support

Definition at line 4645 of file stm32f10x.h.

#define FSMC_BCR3_WREN ((uint32_t)0x00001000)

Write enable bit

Definition at line 4647 of file stm32f10x.h.

#define FSMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000)

Asynchronous wait

Definition at line 4673 of file stm32f10x.h.

#define FSMC_BCR4_BURSTEN ((uint32_t)0x00000100)

Burst enable bit

Definition at line 4666 of file stm32f10x.h.

#define FSMC_BCR4_CBURSTRW ((uint32_t)0x00080000)

Write burst enable

Definition at line 4674 of file stm32f10x.h.

#define FSMC_BCR4_EXTMOD ((uint32_t)0x00004000)

Extended mode enable

Definition at line 4672 of file stm32f10x.h.

#define FSMC_BCR4_FACCEN ((uint32_t)0x00000040)

Flash access enable

Definition at line 4665 of file stm32f10x.h.

#define FSMC_BCR4_MBKEN ((uint32_t)0x00000001)

Memory bank enable bit

Definition at line 4654 of file stm32f10x.h.

#define FSMC_BCR4_MTYP ((uint32_t)0x0000000C)

MTYP[1:0] bits (Memory type)

Definition at line 4657 of file stm32f10x.h.

#define FSMC_BCR4_MTYP_0 ((uint32_t)0x00000004)

Bit 0

Definition at line 4658 of file stm32f10x.h.

#define FSMC_BCR4_MTYP_1 ((uint32_t)0x00000008)

Bit 1

Definition at line 4659 of file stm32f10x.h.

#define FSMC_BCR4_MUXEN ((uint32_t)0x00000002)

Address/data multiplexing enable bit

Definition at line 4655 of file stm32f10x.h.

#define FSMC_BCR4_MWID ((uint32_t)0x00000030)

MWID[1:0] bits (Memory data bus width)

Definition at line 4661 of file stm32f10x.h.

#define FSMC_BCR4_MWID_0 ((uint32_t)0x00000010)

Bit 0

Definition at line 4662 of file stm32f10x.h.

#define FSMC_BCR4_MWID_1 ((uint32_t)0x00000020)

Bit 1

Definition at line 4663 of file stm32f10x.h.

#define FSMC_BCR4_WAITCFG ((uint32_t)0x00000800)

Wait timing configuration

Definition at line 4669 of file stm32f10x.h.

#define FSMC_BCR4_WAITEN ((uint32_t)0x00002000)

Wait enable bit

Definition at line 4671 of file stm32f10x.h.

#define FSMC_BCR4_WAITPOL ((uint32_t)0x00000200)

Wait signal polarity bit

Definition at line 4667 of file stm32f10x.h.

#define FSMC_BCR4_WRAPMOD ((uint32_t)0x00000400)

Wrapped burst mode support

Definition at line 4668 of file stm32f10x.h.

#define FSMC_BCR4_WREN ((uint32_t)0x00001000)

Write enable bit

Definition at line 4670 of file stm32f10x.h.

#define FSMC_BTR1_ACCMOD ((uint32_t)0x30000000)

ACCMOD[1:0] bits (Access mode)

Definition at line 4713 of file stm32f10x.h.

#define FSMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000)

Bit 0

Definition at line 4714 of file stm32f10x.h.

#define FSMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000)

Bit 1

Definition at line 4715 of file stm32f10x.h.

#define FSMC_BTR1_ADDHLD ((uint32_t)0x000000F0)

ADDHLD[3:0] bits (Address-hold phase duration)

Definition at line 4683 of file stm32f10x.h.

#define FSMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010)

Bit 0

Definition at line 4684 of file stm32f10x.h.

#define FSMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020)

Bit 1

Definition at line 4685 of file stm32f10x.h.

#define FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040)

Bit 2

Definition at line 4686 of file stm32f10x.h.

#define FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080)

Bit 3

Definition at line 4687 of file stm32f10x.h.

#define FSMC_BTR1_ADDSET ((uint32_t)0x0000000F)

ADDSET[3:0] bits (Address setup phase duration)

Definition at line 4677 of file stm32f10x.h.

#define FSMC_BTR1_ADDSET_0 ((uint32_t)0x00000001)

Bit 0

Definition at line 4678 of file stm32f10x.h.

#define FSMC_BTR1_ADDSET_1 ((uint32_t)0x00000002)

Bit 1

Definition at line 4679 of file stm32f10x.h.

#define FSMC_BTR1_ADDSET_2 ((uint32_t)0x00000004)

Bit 2

Definition at line 4680 of file stm32f10x.h.

#define FSMC_BTR1_ADDSET_3 ((uint32_t)0x00000008)

Bit 3

Definition at line 4681 of file stm32f10x.h.

#define FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000)

BUSTURN[3:0] bits (Bus turnaround phase duration)

Definition at line 4695 of file stm32f10x.h.

#define FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000)

Bit 0

Definition at line 4696 of file stm32f10x.h.

#define FSMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000)

Bit 1

Definition at line 4697 of file stm32f10x.h.

#define FSMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000)

Bit 2

Definition at line 4698 of file stm32f10x.h.

#define FSMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000)

Bit 3

Definition at line 4699 of file stm32f10x.h.

#define FSMC_BTR1_CLKDIV ((uint32_t)0x00F00000)

CLKDIV[3:0] bits (Clock divide ratio)

Definition at line 4701 of file stm32f10x.h.

#define FSMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000)

Bit 0

Definition at line 4702 of file stm32f10x.h.

#define FSMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000)

Bit 1

Definition at line 4703 of file stm32f10x.h.

#define FSMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000)

Bit 2

Definition at line 4704 of file stm32f10x.h.

#define FSMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000)

Bit 3

Definition at line 4705 of file stm32f10x.h.

#define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00)

DATAST [3:0] bits (Data-phase duration)

Definition at line 4689 of file stm32f10x.h.

#define FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100)

Bit 0

Definition at line 4690 of file stm32f10x.h.

#define FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200)

Bit 1

Definition at line 4691 of file stm32f10x.h.

#define FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400)

Bit 2

Definition at line 4692 of file stm32f10x.h.

#define FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800)

Bit 3

Definition at line 4693 of file stm32f10x.h.

#define FSMC_BTR1_DATLAT ((uint32_t)0x0F000000)

DATLA[3:0] bits (Data latency)

Definition at line 4707 of file stm32f10x.h.

#define FSMC_BTR1_DATLAT_0 ((uint32_t)0x01000000)

Bit 0

Definition at line 4708 of file stm32f10x.h.

#define FSMC_BTR1_DATLAT_1 ((uint32_t)0x02000000)

Bit 1

Definition at line 4709 of file stm32f10x.h.

#define FSMC_BTR1_DATLAT_2 ((uint32_t)0x04000000)

Bit 2

Definition at line 4710 of file stm32f10x.h.

#define FSMC_BTR1_DATLAT_3 ((uint32_t)0x08000000)

Bit 3

Definition at line 4711 of file stm32f10x.h.

#define FSMC_BTR2_ACCMOD ((uint32_t)0x30000000)

ACCMOD[1:0] bits (Access mode)

Definition at line 4754 of file stm32f10x.h.

#define FSMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000)

Bit 0

Definition at line 4755 of file stm32f10x.h.

#define FSMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000)

Bit 1

Definition at line 4756 of file stm32f10x.h.

#define FSMC_BTR2_ADDHLD ((uint32_t)0x000000F0)

ADDHLD[3:0] bits (Address-hold phase duration)

Definition at line 4724 of file stm32f10x.h.

#define FSMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010)

Bit 0

Definition at line 4725 of file stm32f10x.h.

#define FSMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020)

Bit 1

Definition at line 4726 of file stm32f10x.h.

#define FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040)

Bit 2

Definition at line 4727 of file stm32f10x.h.

#define FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080)

Bit 3

Definition at line 4728 of file stm32f10x.h.

#define FSMC_BTR2_ADDSET ((uint32_t)0x0000000F)

ADDSET[3:0] bits (Address setup phase duration)

Definition at line 4718 of file stm32f10x.h.

#define FSMC_BTR2_ADDSET_0 ((uint32_t)0x00000001)

Bit 0

Definition at line 4719 of file stm32f10x.h.

#define FSMC_BTR2_ADDSET_1 ((uint32_t)0x00000002)

Bit 1

Definition at line 4720 of file stm32f10x.h.

#define FSMC_BTR2_ADDSET_2 ((uint32_t)0x00000004)

Bit 2

Definition at line 4721 of file stm32f10x.h.

#define FSMC_BTR2_ADDSET_3 ((uint32_t)0x00000008)

Bit 3

Definition at line 4722 of file stm32f10x.h.

#define FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000)

BUSTURN[3:0] bits (Bus turnaround phase duration)

Definition at line 4736 of file stm32f10x.h.

#define FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000)

Bit 0

Definition at line 4737 of file stm32f10x.h.

#define FSMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000)

Bit 1

Definition at line 4738 of file stm32f10x.h.

#define FSMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000)

Bit 2

Definition at line 4739 of file stm32f10x.h.

#define FSMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000)

Bit 3

Definition at line 4740 of file stm32f10x.h.

#define FSMC_BTR2_CLKDIV ((uint32_t)0x00F00000)

CLKDIV[3:0] bits (Clock divide ratio)

Definition at line 4742 of file stm32f10x.h.

#define FSMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000)

Bit 0

Definition at line 4743 of file stm32f10x.h.

#define FSMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000)

Bit 1

Definition at line 4744 of file stm32f10x.h.

#define FSMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000)

Bit 2

Definition at line 4745 of file stm32f10x.h.

#define FSMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000)

Bit 3

Definition at line 4746 of file stm32f10x.h.

#define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00)

DATAST [3:0] bits (Data-phase duration)

Definition at line 4730 of file stm32f10x.h.

#define FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100)

Bit 0

Definition at line 4731 of file stm32f10x.h.

#define FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200)

Bit 1

Definition at line 4732 of file stm32f10x.h.

#define FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400)

Bit 2

Definition at line 4733 of file stm32f10x.h.

#define FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800)

Bit 3

Definition at line 4734 of file stm32f10x.h.

#define FSMC_BTR2_DATLAT ((uint32_t)0x0F000000)

DATLA[3:0] bits (Data latency)

Definition at line 4748 of file stm32f10x.h.

#define FSMC_BTR2_DATLAT_0 ((uint32_t)0x01000000)

Bit 0

Definition at line 4749 of file stm32f10x.h.

#define FSMC_BTR2_DATLAT_1 ((uint32_t)0x02000000)

Bit 1

Definition at line 4750 of file stm32f10x.h.

#define FSMC_BTR2_DATLAT_2 ((uint32_t)0x04000000)

Bit 2

Definition at line 4751 of file stm32f10x.h.

#define FSMC_BTR2_DATLAT_3 ((uint32_t)0x08000000)

Bit 3

Definition at line 4752 of file stm32f10x.h.

#define FSMC_BTR3_ACCMOD ((uint32_t)0x30000000)

ACCMOD[1:0] bits (Access mode)

Definition at line 4795 of file stm32f10x.h.

#define FSMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000)

Bit 0

Definition at line 4796 of file stm32f10x.h.

#define FSMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000)

Bit 1

Definition at line 4797 of file stm32f10x.h.

#define FSMC_BTR3_ADDHLD ((uint32_t)0x000000F0)

ADDHLD[3:0] bits (Address-hold phase duration)

Definition at line 4765 of file stm32f10x.h.

#define FSMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010)

Bit 0

Definition at line 4766 of file stm32f10x.h.

#define FSMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020)

Bit 1

Definition at line 4767 of file stm32f10x.h.

#define FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040)

Bit 2

Definition at line 4768 of file stm32f10x.h.

#define FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080)

Bit 3

Definition at line 4769 of file stm32f10x.h.

#define FSMC_BTR3_ADDSET ((uint32_t)0x0000000F)

ADDSET[3:0] bits (Address setup phase duration)

Definition at line 4759 of file stm32f10x.h.

#define FSMC_BTR3_ADDSET_0 ((uint32_t)0x00000001)

Bit 0

Definition at line 4760 of file stm32f10x.h.

#define FSMC_BTR3_ADDSET_1 ((uint32_t)0x00000002)

Bit 1

Definition at line 4761 of file stm32f10x.h.

#define FSMC_BTR3_ADDSET_2 ((uint32_t)0x00000004)

Bit 2

Definition at line 4762 of file stm32f10x.h.

#define FSMC_BTR3_ADDSET_3 ((uint32_t)0x00000008)

Bit 3

Definition at line 4763 of file stm32f10x.h.

#define FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000)

BUSTURN[3:0] bits (Bus turnaround phase duration)

Definition at line 4777 of file stm32f10x.h.

#define FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000)

Bit 0

Definition at line 4778 of file stm32f10x.h.

#define FSMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000)

Bit 1

Definition at line 4779 of file stm32f10x.h.

#define FSMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000)

Bit 2

Definition at line 4780 of file stm32f10x.h.

#define FSMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000)

Bit 3

Definition at line 4781 of file stm32f10x.h.

#define FSMC_BTR3_CLKDIV ((uint32_t)0x00F00000)

CLKDIV[3:0] bits (Clock divide ratio)

Definition at line 4783 of file stm32f10x.h.

#define FSMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000)

Bit 0

Definition at line 4784 of file stm32f10x.h.

#define FSMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000)

Bit 1

Definition at line 4785 of file stm32f10x.h.

#define FSMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000)

Bit 2

Definition at line 4786 of file stm32f10x.h.

#define FSMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000)

Bit 3

Definition at line 4787 of file stm32f10x.h.

#define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00)

DATAST [3:0] bits (Data-phase duration)

Definition at line 4771 of file stm32f10x.h.

#define FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100)

Bit 0

Definition at line 4772 of file stm32f10x.h.

#define FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200)

Bit 1

Definition at line 4773 of file stm32f10x.h.

#define FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400)

Bit 2

Definition at line 4774 of file stm32f10x.h.

#define FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800)

Bit 3

Definition at line 4775 of file stm32f10x.h.

#define FSMC_BTR3_DATLAT ((uint32_t)0x0F000000)

DATLA[3:0] bits (Data latency)

Definition at line 4789 of file stm32f10x.h.

#define FSMC_BTR3_DATLAT_0 ((uint32_t)0x01000000)

Bit 0

Definition at line 4790 of file stm32f10x.h.

#define FSMC_BTR3_DATLAT_1 ((uint32_t)0x02000000)

Bit 1

Definition at line 4791 of file stm32f10x.h.

#define FSMC_BTR3_DATLAT_2 ((uint32_t)0x04000000)

Bit 2

Definition at line 4792 of file stm32f10x.h.

#define FSMC_BTR3_DATLAT_3 ((uint32_t)0x08000000)

Bit 3

Definition at line 4793 of file stm32f10x.h.

#define FSMC_BTR4_ACCMOD ((uint32_t)0x30000000)

ACCMOD[1:0] bits (Access mode)

Definition at line 4836 of file stm32f10x.h.

#define FSMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000)

Bit 0

Definition at line 4837 of file stm32f10x.h.

#define FSMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000)

Bit 1

Definition at line 4838 of file stm32f10x.h.

#define FSMC_BTR4_ADDHLD ((uint32_t)0x000000F0)

ADDHLD[3:0] bits (Address-hold phase duration)

Definition at line 4806 of file stm32f10x.h.

#define FSMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010)

Bit 0

Definition at line 4807 of file stm32f10x.h.

#define FSMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020)

Bit 1

Definition at line 4808 of file stm32f10x.h.

#define FSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040)

Bit 2

Definition at line 4809 of file stm32f10x.h.

#define FSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080)

Bit 3

Definition at line 4810 of file stm32f10x.h.

#define FSMC_BTR4_ADDSET ((uint32_t)0x0000000F)

ADDSET[3:0] bits (Address setup phase duration)

Definition at line 4800 of file stm32f10x.h.

#define FSMC_BTR4_ADDSET_0 ((uint32_t)0x00000001)

Bit 0

Definition at line 4801 of file stm32f10x.h.

#define FSMC_BTR4_ADDSET_1 ((uint32_t)0x00000002)

Bit 1

Definition at line 4802 of file stm32f10x.h.

#define FSMC_BTR4_ADDSET_2 ((uint32_t)0x00000004)

Bit 2

Definition at line 4803 of file stm32f10x.h.

#define FSMC_BTR4_ADDSET_3 ((uint32_t)0x00000008)

Bit 3

Definition at line 4804 of file stm32f10x.h.

#define FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000)

BUSTURN[3:0] bits (Bus turnaround phase duration)

Definition at line 4818 of file stm32f10x.h.

#define FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000)

Bit 0

Definition at line 4819 of file stm32f10x.h.

#define FSMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000)

Bit 1

Definition at line 4820 of file stm32f10x.h.

#define FSMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000)

Bit 2

Definition at line 4821 of file stm32f10x.h.

#define FSMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000)

Bit 3

Definition at line 4822 of file stm32f10x.h.

#define FSMC_BTR4_CLKDIV ((uint32_t)0x00F00000)

CLKDIV[3:0] bits (Clock divide ratio)

Definition at line 4824 of file stm32f10x.h.

#define FSMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000)

Bit 0

Definition at line 4825 of file stm32f10x.h.

#define FSMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000)

Bit 1

Definition at line 4826 of file stm32f10x.h.

#define FSMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000)

Bit 2

Definition at line 4827 of file stm32f10x.h.

#define FSMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000)

Bit 3

Definition at line 4828 of file stm32f10x.h.

#define FSMC_BTR4_DATAST ((uint32_t)0x0000FF00)

DATAST [3:0] bits (Data-phase duration)

Definition at line 4812 of file stm32f10x.h.

#define FSMC_BTR4_DATAST_0 ((uint32_t)0x00000100)

Bit 0

Definition at line 4813 of file stm32f10x.h.

#define FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200)

Bit 1

Definition at line 4814 of file stm32f10x.h.

#define FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400)

Bit 2

Definition at line 4815 of file stm32f10x.h.

#define FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800)

Bit 3

Definition at line 4816 of file stm32f10x.h.

#define FSMC_BTR4_DATLAT ((uint32_t)0x0F000000)

DATLA[3:0] bits (Data latency)

Definition at line 4830 of file stm32f10x.h.

#define FSMC_BTR4_DATLAT_0 ((uint32_t)0x01000000)

Bit 0

Definition at line 4831 of file stm32f10x.h.

#define FSMC_BTR4_DATLAT_1 ((uint32_t)0x02000000)

Bit 1

Definition at line 4832 of file stm32f10x.h.

#define FSMC_BTR4_DATLAT_2 ((uint32_t)0x04000000)

Bit 2

Definition at line 4833 of file stm32f10x.h.

#define FSMC_BTR4_DATLAT_3 ((uint32_t)0x08000000)

Bit 3

Definition at line 4834 of file stm32f10x.h.

#define FSMC_BWTR1_ACCMOD ((uint32_t)0x30000000)

ACCMOD[1:0] bits (Access mode)

Definition at line 4871 of file stm32f10x.h.

#define FSMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000)

Bit 0

Definition at line 4872 of file stm32f10x.h.

#define FSMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000)

Bit 1

Definition at line 4873 of file stm32f10x.h.

#define FSMC_BWTR1_ADDHLD ((uint32_t)0x000000F0)

ADDHLD[3:0] bits (Address-hold phase duration)

Definition at line 4847 of file stm32f10x.h.

#define FSMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010)

Bit 0

Definition at line 4848 of file stm32f10x.h.

#define FSMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020)

Bit 1

Definition at line 4849 of file stm32f10x.h.

#define FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040)

Bit 2

Definition at line 4850 of file stm32f10x.h.

#define FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080)

Bit 3

Definition at line 4851 of file stm32f10x.h.

#define FSMC_BWTR1_ADDSET ((uint32_t)0x0000000F)

ADDSET[3:0] bits (Address setup phase duration)

Definition at line 4841 of file stm32f10x.h.

#define FSMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001)

Bit 0

Definition at line 4842 of file stm32f10x.h.

#define FSMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002)

Bit 1

Definition at line 4843 of file stm32f10x.h.

#define FSMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004)

Bit 2

Definition at line 4844 of file stm32f10x.h.

#define FSMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008)

Bit 3

Definition at line 4845 of file stm32f10x.h.

#define FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000)

CLKDIV[3:0] bits (Clock divide ratio)

Definition at line 4859 of file stm32f10x.h.

#define FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000)

Bit 0

Definition at line 4860 of file stm32f10x.h.

#define FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000)

Bit 1

Definition at line 4861 of file stm32f10x.h.

#define FSMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000)

Bit 2

Definition at line 4862 of file stm32f10x.h.

#define FSMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000)

Bit 3

Definition at line 4863 of file stm32f10x.h.

#define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00)

DATAST [3:0] bits (Data-phase duration)

Definition at line 4853 of file stm32f10x.h.

#define FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100)

Bit 0

Definition at line 4854 of file stm32f10x.h.

#define FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200)

Bit 1

Definition at line 4855 of file stm32f10x.h.

#define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400)

Bit 2

Definition at line 4856 of file stm32f10x.h.

#define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800)

Bit 3

Definition at line 4857 of file stm32f10x.h.

#define FSMC_BWTR1_DATLAT ((uint32_t)0x0F000000)

DATLA[3:0] bits (Data latency)

Definition at line 4865 of file stm32f10x.h.

#define FSMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000)

Bit 0

Definition at line 4866 of file stm32f10x.h.

#define FSMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000)

Bit 1

Definition at line 4867 of file stm32f10x.h.

#define FSMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000)

Bit 2

Definition at line 4868 of file stm32f10x.h.

#define FSMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000)

Bit 3

Definition at line 4869 of file stm32f10x.h.

#define FSMC_BWTR2_ACCMOD ((uint32_t)0x30000000)

ACCMOD[1:0] bits (Access mode)

Definition at line 4906 of file stm32f10x.h.

#define FSMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000)

Bit 0

Definition at line 4907 of file stm32f10x.h.

#define FSMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000)

Bit 1

Definition at line 4908 of file stm32f10x.h.

#define FSMC_BWTR2_ADDHLD ((uint32_t)0x000000F0)

ADDHLD[3:0] bits (Address-hold phase duration)

Definition at line 4882 of file stm32f10x.h.

#define FSMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010)

Bit 0

Definition at line 4883 of file stm32f10x.h.

#define FSMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020)

Bit 1

Definition at line 4884 of file stm32f10x.h.

#define FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040)

Bit 2

Definition at line 4885 of file stm32f10x.h.

#define FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080)

Bit 3

Definition at line 4886 of file stm32f10x.h.

#define FSMC_BWTR2_ADDSET ((uint32_t)0x0000000F)

ADDSET[3:0] bits (Address setup phase duration)

Definition at line 4876 of file stm32f10x.h.

#define FSMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001)

Bit 0

Definition at line 4877 of file stm32f10x.h.

#define FSMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002)

Bit 1

Definition at line 4878 of file stm32f10x.h.

#define FSMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004)

Bit 2

Definition at line 4879 of file stm32f10x.h.

#define FSMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008)

Bit 3

Definition at line 4880 of file stm32f10x.h.

#define FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000)

CLKDIV[3:0] bits (Clock divide ratio)

Definition at line 4894 of file stm32f10x.h.

#define FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000)

Bit 0

Definition at line 4895 of file stm32f10x.h.

#define FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000)

Bit 1

Definition at line 4896 of file stm32f10x.h.

#define FSMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000)

Bit 2

Definition at line 4897 of file stm32f10x.h.

#define FSMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000)

Bit 3

Definition at line 4898 of file stm32f10x.h.

#define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00)

DATAST [3:0] bits (Data-phase duration)

Definition at line 4888 of file stm32f10x.h.

#define FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100)

Bit 0

Definition at line 4889 of file stm32f10x.h.

#define FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200)

Bit 1

Definition at line 4890 of file stm32f10x.h.

#define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400)

Bit 2

Definition at line 4891 of file stm32f10x.h.

#define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800)

Bit 3

Definition at line 4892 of file stm32f10x.h.

#define FSMC_BWTR2_DATLAT ((uint32_t)0x0F000000)

DATLA[3:0] bits (Data latency)

Definition at line 4900 of file stm32f10x.h.

#define FSMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000)

Bit 0

Definition at line 4901 of file stm32f10x.h.

#define FSMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000)

Bit 1

Definition at line 4902 of file stm32f10x.h.

#define FSMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000)

Bit 2

Definition at line 4903 of file stm32f10x.h.

#define FSMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000)

Bit 3

Definition at line 4904 of file stm32f10x.h.

#define FSMC_BWTR3_ACCMOD ((uint32_t)0x30000000)

ACCMOD[1:0] bits (Access mode)

Definition at line 4941 of file stm32f10x.h.

#define FSMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000)

Bit 0

Definition at line 4942 of file stm32f10x.h.

#define FSMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000)

Bit 1

Definition at line 4943 of file stm32f10x.h.

#define FSMC_BWTR3_ADDHLD ((uint32_t)0x000000F0)

ADDHLD[3:0] bits (Address-hold phase duration)

Definition at line 4917 of file stm32f10x.h.

#define FSMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010)

Bit 0

Definition at line 4918 of file stm32f10x.h.

#define FSMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020)

Bit 1

Definition at line 4919 of file stm32f10x.h.

#define FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040)

Bit 2

Definition at line 4920 of file stm32f10x.h.

#define FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080)

Bit 3

Definition at line 4921 of file stm32f10x.h.

#define FSMC_BWTR3_ADDSET ((uint32_t)0x0000000F)

ADDSET[3:0] bits (Address setup phase duration)

Definition at line 4911 of file stm32f10x.h.

#define FSMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001)

Bit 0

Definition at line 4912 of file stm32f10x.h.

#define FSMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002)

Bit 1

Definition at line 4913 of file stm32f10x.h.

#define FSMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004)

Bit 2

Definition at line 4914 of file stm32f10x.h.

#define FSMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008)

Bit 3

Definition at line 4915 of file stm32f10x.h.

#define FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000)

CLKDIV[3:0] bits (Clock divide ratio)

Definition at line 4929 of file stm32f10x.h.

#define FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000)

Bit 0

Definition at line 4930 of file stm32f10x.h.

#define FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000)

Bit 1

Definition at line 4931 of file stm32f10x.h.

#define FSMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000)

Bit 2

Definition at line 4932 of file stm32f10x.h.

#define FSMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000)

Bit 3

Definition at line 4933 of file stm32f10x.h.

#define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00)

DATAST [3:0] bits (Data-phase duration)

Definition at line 4923 of file stm32f10x.h.

#define FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100)

Bit 0

Definition at line 4924 of file stm32f10x.h.

#define FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200)

Bit 1

Definition at line 4925 of file stm32f10x.h.

#define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400)

Bit 2

Definition at line 4926 of file stm32f10x.h.

#define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800)

Bit 3

Definition at line 4927 of file stm32f10x.h.

#define FSMC_BWTR3_DATLAT ((uint32_t)0x0F000000)

DATLA[3:0] bits (Data latency)

Definition at line 4935 of file stm32f10x.h.

#define FSMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000)

Bit 0

Definition at line 4936 of file stm32f10x.h.

#define FSMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000)

Bit 1

Definition at line 4937 of file stm32f10x.h.

#define FSMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000)

Bit 2

Definition at line 4938 of file stm32f10x.h.

#define FSMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000)

Bit 3

Definition at line 4939 of file stm32f10x.h.

#define FSMC_BWTR4_ACCMOD ((uint32_t)0x30000000)

ACCMOD[1:0] bits (Access mode)

Definition at line 4976 of file stm32f10x.h.

#define FSMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000)

Bit 0

Definition at line 4977 of file stm32f10x.h.

#define FSMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000)

Bit 1

Definition at line 4978 of file stm32f10x.h.

#define FSMC_BWTR4_ADDHLD ((uint32_t)0x000000F0)

ADDHLD[3:0] bits (Address-hold phase duration)

Definition at line 4952 of file stm32f10x.h.

#define FSMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010)

Bit 0

Definition at line 4953 of file stm32f10x.h.

#define FSMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020)

Bit 1

Definition at line 4954 of file stm32f10x.h.

#define FSMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040)

Bit 2

Definition at line 4955 of file stm32f10x.h.

#define FSMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080)

Bit 3

Definition at line 4956 of file stm32f10x.h.

#define FSMC_BWTR4_ADDSET ((uint32_t)0x0000000F)

ADDSET[3:0] bits (Address setup phase duration)

Definition at line 4946 of file stm32f10x.h.

#define FSMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001)

Bit 0

Definition at line 4947 of file stm32f10x.h.

#define FSMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002)

Bit 1

Definition at line 4948 of file stm32f10x.h.

#define FSMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004)

Bit 2

Definition at line 4949 of file stm32f10x.h.

#define FSMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008)

Bit 3

Definition at line 4950 of file stm32f10x.h.

#define FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000)

CLKDIV[3:0] bits (Clock divide ratio)

Definition at line 4964 of file stm32f10x.h.

#define FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000)

Bit 0

Definition at line 4965 of file stm32f10x.h.

#define FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000)

Bit 1

Definition at line 4966 of file stm32f10x.h.

#define FSMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000)

Bit 2

Definition at line 4967 of file stm32f10x.h.

#define FSMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000)

Bit 3

Definition at line 4968 of file stm32f10x.h.

#define FSMC_BWTR4_DATAST ((uint32_t)0x0000FF00)

DATAST [3:0] bits (Data-phase duration)

Definition at line 4958 of file stm32f10x.h.

#define FSMC_BWTR4_DATAST_0 ((uint32_t)0x00000100)

Bit 0

Definition at line 4959 of file stm32f10x.h.

#define FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200)

Bit 1

Definition at line 4960 of file stm32f10x.h.

#define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400)

Bit 2

Definition at line 4961 of file stm32f10x.h.

#define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800)

Bit 3

Definition at line 4962 of file stm32f10x.h.

#define FSMC_BWTR4_DATLAT ((uint32_t)0x0F000000)

DATLA[3:0] bits (Data latency)

Definition at line 4970 of file stm32f10x.h.

#define FSMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000)

Bit 0

Definition at line 4971 of file stm32f10x.h.

#define FSMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000)

Bit 1

Definition at line 4972 of file stm32f10x.h.

#define FSMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000)

Bit 2

Definition at line 4973 of file stm32f10x.h.

#define FSMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000)

Bit 3

Definition at line 4974 of file stm32f10x.h.

#define FSMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF)

ECC result

Definition at line 5379 of file stm32f10x.h.

#define FSMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF)

ECC result

Definition at line 5382 of file stm32f10x.h.

#define FSMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000)

ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time)

Definition at line 5245 of file stm32f10x.h.

#define FSMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000)

Bit 0

Definition at line 5246 of file stm32f10x.h.

#define FSMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000)

Bit 1

Definition at line 5247 of file stm32f10x.h.

#define FSMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000)

Bit 2

Definition at line 5248 of file stm32f10x.h.

#define FSMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000)

Bit 3

Definition at line 5249 of file stm32f10x.h.

#define FSMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000)

Bit 4

Definition at line 5250 of file stm32f10x.h.

#define FSMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000)

Bit 5

Definition at line 5251 of file stm32f10x.h.

#define FSMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000)

Bit 6

Definition at line 5252 of file stm32f10x.h.

#define FSMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000)

Bit 7

Definition at line 5253 of file stm32f10x.h.

#define FSMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000)

ATTHOLD2[7:0] bits (Attribute memory 2 hold time)

Definition at line 5235 of file stm32f10x.h.

#define FSMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000)

Bit 0

Definition at line 5236 of file stm32f10x.h.

#define FSMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000)

Bit 1

Definition at line 5237 of file stm32f10x.h.

#define FSMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000)

Bit 2

Definition at line 5238 of file stm32f10x.h.

#define FSMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000)

Bit 3

Definition at line 5239 of file stm32f10x.h.

#define FSMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000)

Bit 4

Definition at line 5240 of file stm32f10x.h.

#define FSMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000)

Bit 5

Definition at line 5241 of file stm32f10x.h.

#define FSMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000)

Bit 6

Definition at line 5242 of file stm32f10x.h.

#define FSMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000)

Bit 7

Definition at line 5243 of file stm32f10x.h.

#define FSMC_PATT2_ATTSET2 ((uint32_t)0x000000FF)

ATTSET2[7:0] bits (Attribute memory 2 setup time)

Definition at line 5215 of file stm32f10x.h.

#define FSMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001)

Bit 0

Definition at line 5216 of file stm32f10x.h.

#define FSMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002)

Bit 1

Definition at line 5217 of file stm32f10x.h.

#define FSMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004)

Bit 2

Definition at line 5218 of file stm32f10x.h.

#define FSMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008)

Bit 3

Definition at line 5219 of file stm32f10x.h.

#define FSMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010)

Bit 4

Definition at line 5220 of file stm32f10x.h.

#define FSMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020)

Bit 5

Definition at line 5221 of file stm32f10x.h.

#define FSMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040)

Bit 6

Definition at line 5222 of file stm32f10x.h.

#define FSMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080)

Bit 7

Definition at line 5223 of file stm32f10x.h.

#define FSMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00)

ATTWAIT2[7:0] bits (Attribute memory 2 wait time)

Definition at line 5225 of file stm32f10x.h.

#define FSMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100)

Bit 0

Definition at line 5226 of file stm32f10x.h.

#define FSMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200)

Bit 1

Definition at line 5227 of file stm32f10x.h.

#define FSMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400)

Bit 2

Definition at line 5228 of file stm32f10x.h.

#define FSMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800)

Bit 3

Definition at line 5229 of file stm32f10x.h.

#define FSMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000)

Bit 4

Definition at line 5230 of file stm32f10x.h.

#define FSMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000)

Bit 5

Definition at line 5231 of file stm32f10x.h.

#define FSMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000)

Bit 6

Definition at line 5232 of file stm32f10x.h.

#define FSMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000)

Bit 7

Definition at line 5233 of file stm32f10x.h.

#define FSMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000)

ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time)

Definition at line 5286 of file stm32f10x.h.

#define FSMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000)

Bit 0

Definition at line 5287 of file stm32f10x.h.

#define FSMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000)

Bit 1

Definition at line 5288 of file stm32f10x.h.

#define FSMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000)

Bit 2

Definition at line 5289 of file stm32f10x.h.

#define FSMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000)

Bit 3

Definition at line 5290 of file stm32f10x.h.

#define FSMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000)

Bit 4

Definition at line 5291 of file stm32f10x.h.

#define FSMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000)

Bit 5

Definition at line 5292 of file stm32f10x.h.

#define FSMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000)

Bit 6

Definition at line 5293 of file stm32f10x.h.

#define FSMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000)

Bit 7

Definition at line 5294 of file stm32f10x.h.

#define FSMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000)

ATTHOLD3[7:0] bits (Attribute memory 3 hold time)

Definition at line 5276 of file stm32f10x.h.

#define FSMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000)

Bit 0

Definition at line 5277 of file stm32f10x.h.

#define FSMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000)

Bit 1

Definition at line 5278 of file stm32f10x.h.

#define FSMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000)

Bit 2

Definition at line 5279 of file stm32f10x.h.

#define FSMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000)

Bit 3

Definition at line 5280 of file stm32f10x.h.

#define FSMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000)

Bit 4

Definition at line 5281 of file stm32f10x.h.

#define FSMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000)

Bit 5

Definition at line 5282 of file stm32f10x.h.

#define FSMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000)

Bit 6

Definition at line 5283 of file stm32f10x.h.

#define FSMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000)

Bit 7

Definition at line 5284 of file stm32f10x.h.

#define FSMC_PATT3_ATTSET3 ((uint32_t)0x000000FF)

ATTSET3[7:0] bits (Attribute memory 3 setup time)

Definition at line 5256 of file stm32f10x.h.

#define FSMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001)

Bit 0

Definition at line 5257 of file stm32f10x.h.

#define FSMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002)

Bit 1

Definition at line 5258 of file stm32f10x.h.

#define FSMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004)

Bit 2

Definition at line 5259 of file stm32f10x.h.

#define FSMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008)

Bit 3

Definition at line 5260 of file stm32f10x.h.

#define FSMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010)

Bit 4

Definition at line 5261 of file stm32f10x.h.

#define FSMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020)

Bit 5

Definition at line 5262 of file stm32f10x.h.

#define FSMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040)

Bit 6

Definition at line 5263 of file stm32f10x.h.

#define FSMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080)

Bit 7

Definition at line 5264 of file stm32f10x.h.

#define FSMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00)

ATTWAIT3[7:0] bits (Attribute memory 3 wait time)

Definition at line 5266 of file stm32f10x.h.

#define FSMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100)

Bit 0

Definition at line 5267 of file stm32f10x.h.

#define FSMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200)

Bit 1

Definition at line 5268 of file stm32f10x.h.

#define FSMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400)

Bit 2

Definition at line 5269 of file stm32f10x.h.

#define FSMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800)

Bit 3

Definition at line 5270 of file stm32f10x.h.

#define FSMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000)

Bit 4

Definition at line 5271 of file stm32f10x.h.

#define FSMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000)

Bit 5

Definition at line 5272 of file stm32f10x.h.

#define FSMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000)

Bit 6

Definition at line 5273 of file stm32f10x.h.

#define FSMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000)

Bit 7

Definition at line 5274 of file stm32f10x.h.

#define FSMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000)

ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time)

Definition at line 5327 of file stm32f10x.h.

#define FSMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000)

Bit 0

Definition at line 5328 of file stm32f10x.h.

#define FSMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000)

Bit 1

Definition at line 5329 of file stm32f10x.h.

#define FSMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000)

Bit 2

Definition at line 5330 of file stm32f10x.h.

#define FSMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000)

Bit 3

Definition at line 5331 of file stm32f10x.h.

#define FSMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000)

Bit 4

Definition at line 5332 of file stm32f10x.h.

#define FSMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000)

Bit 5

Definition at line 5333 of file stm32f10x.h.

#define FSMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000)

Bit 6

Definition at line 5334 of file stm32f10x.h.

#define FSMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000)

Bit 7

Definition at line 5335 of file stm32f10x.h.

#define FSMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000)

ATTHOLD4[7:0] bits (Attribute memory 4 hold time)

Definition at line 5317 of file stm32f10x.h.

#define FSMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000)

Bit 0

Definition at line 5318 of file stm32f10x.h.

#define FSMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000)

Bit 1

Definition at line 5319 of file stm32f10x.h.

#define FSMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000)

Bit 2

Definition at line 5320 of file stm32f10x.h.

#define FSMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000)

Bit 3

Definition at line 5321 of file stm32f10x.h.

#define FSMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000)

Bit 4

Definition at line 5322 of file stm32f10x.h.

#define FSMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000)

Bit 5

Definition at line 5323 of file stm32f10x.h.

#define FSMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000)

Bit 6

Definition at line 5324 of file stm32f10x.h.

#define FSMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000)

Bit 7

Definition at line 5325 of file stm32f10x.h.

#define FSMC_PATT4_ATTSET4 ((uint32_t)0x000000FF)

ATTSET4[7:0] bits (Attribute memory 4 setup time)

Definition at line 5297 of file stm32f10x.h.

#define FSMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001)

Bit 0

Definition at line 5298 of file stm32f10x.h.

#define FSMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002)

Bit 1

Definition at line 5299 of file stm32f10x.h.

#define FSMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004)

Bit 2

Definition at line 5300 of file stm32f10x.h.

#define FSMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008)

Bit 3

Definition at line 5301 of file stm32f10x.h.

#define FSMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010)

Bit 4

Definition at line 5302 of file stm32f10x.h.

#define FSMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020)

Bit 5

Definition at line 5303 of file stm32f10x.h.

#define FSMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040)

Bit 6

Definition at line 5304 of file stm32f10x.h.

#define FSMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080)

Bit 7

Definition at line 5305 of file stm32f10x.h.

#define FSMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00)

ATTWAIT4[7:0] bits (Attribute memory 4 wait time)

Definition at line 5307 of file stm32f10x.h.

#define FSMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100)

Bit 0

Definition at line 5308 of file stm32f10x.h.

#define FSMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200)

Bit 1

Definition at line 5309 of file stm32f10x.h.

#define FSMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400)

Bit 2

Definition at line 5310 of file stm32f10x.h.

#define FSMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800)

Bit 3

Definition at line 5311 of file stm32f10x.h.

#define FSMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000)

Bit 4

Definition at line 5312 of file stm32f10x.h.

#define FSMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000)

Bit 5

Definition at line 5313 of file stm32f10x.h.

#define FSMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000)

Bit 6

Definition at line 5314 of file stm32f10x.h.

#define FSMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000)

Bit 7

Definition at line 5315 of file stm32f10x.h.

#define FSMC_PCR2_ECCEN ((uint32_t)0x00000040)

ECC computation logic enable bit

Definition at line 4989 of file stm32f10x.h.

#define FSMC_PCR2_ECCPS ((uint32_t)0x000E0000)

ECCPS[1:0] bits (ECC page size)

Definition at line 5003 of file stm32f10x.h.

#define FSMC_PCR2_ECCPS_0 ((uint32_t)0x00020000)

Bit 0

Definition at line 5004 of file stm32f10x.h.

#define FSMC_PCR2_ECCPS_1 ((uint32_t)0x00040000)

Bit 1

Definition at line 5005 of file stm32f10x.h.

#define FSMC_PCR2_ECCPS_2 ((uint32_t)0x00080000)

Bit 2

Definition at line 5006 of file stm32f10x.h.

#define FSMC_PCR2_PBKEN ((uint32_t)0x00000004)

PC Card/NAND Flash memory bank enable bit

Definition at line 4982 of file stm32f10x.h.

#define FSMC_PCR2_PTYP ((uint32_t)0x00000008)

Memory type

Definition at line 4983 of file stm32f10x.h.

#define FSMC_PCR2_PWAITEN ((uint32_t)0x00000002)

Wait feature enable bit

Definition at line 4981 of file stm32f10x.h.

#define FSMC_PCR2_PWID ((uint32_t)0x00000030)

PWID[1:0] bits (NAND Flash databus width)

Definition at line 4985 of file stm32f10x.h.

#define FSMC_PCR2_PWID_0 ((uint32_t)0x00000010)

Bit 0

Definition at line 4986 of file stm32f10x.h.

#define FSMC_PCR2_PWID_1 ((uint32_t)0x00000020)

Bit 1

Definition at line 4987 of file stm32f10x.h.

#define FSMC_PCR2_TAR ((uint32_t)0x0001E000)

TAR[3:0] bits (ALE to RE delay)

Definition at line 4997 of file stm32f10x.h.

#define FSMC_PCR2_TAR_0 ((uint32_t)0x00002000)

Bit 0

Definition at line 4998 of file stm32f10x.h.

#define FSMC_PCR2_TAR_1 ((uint32_t)0x00004000)

Bit 1

Definition at line 4999 of file stm32f10x.h.

#define FSMC_PCR2_TAR_2 ((uint32_t)0x00008000)

Bit 2

Definition at line 5000 of file stm32f10x.h.

#define FSMC_PCR2_TAR_3 ((uint32_t)0x00010000)

Bit 3

Definition at line 5001 of file stm32f10x.h.

#define FSMC_PCR2_TCLR ((uint32_t)0x00001E00)

TCLR[3:0] bits (CLE to RE delay)

Definition at line 4991 of file stm32f10x.h.

#define FSMC_PCR2_TCLR_0 ((uint32_t)0x00000200)

Bit 0

Definition at line 4992 of file stm32f10x.h.

#define FSMC_PCR2_TCLR_1 ((uint32_t)0x00000400)

Bit 1

Definition at line 4993 of file stm32f10x.h.

#define FSMC_PCR2_TCLR_2 ((uint32_t)0x00000800)

Bit 2

Definition at line 4994 of file stm32f10x.h.

#define FSMC_PCR2_TCLR_3 ((uint32_t)0x00001000)

Bit 3

Definition at line 4995 of file stm32f10x.h.

#define FSMC_PCR3_ECCEN ((uint32_t)0x00000040)

ECC computation logic enable bit

Definition at line 5017 of file stm32f10x.h.

#define FSMC_PCR3_ECCPS ((uint32_t)0x000E0000)

ECCPS[2:0] bits (ECC page size)

Definition at line 5031 of file stm32f10x.h.

#define FSMC_PCR3_ECCPS_0 ((uint32_t)0x00020000)

Bit 0

Definition at line 5032 of file stm32f10x.h.

#define FSMC_PCR3_ECCPS_1 ((uint32_t)0x00040000)

Bit 1

Definition at line 5033 of file stm32f10x.h.

#define FSMC_PCR3_ECCPS_2 ((uint32_t)0x00080000)

Bit 2

Definition at line 5034 of file stm32f10x.h.

#define FSMC_PCR3_PBKEN ((uint32_t)0x00000004)

PC Card/NAND Flash memory bank enable bit

Definition at line 5010 of file stm32f10x.h.

#define FSMC_PCR3_PTYP ((uint32_t)0x00000008)

Memory type

Definition at line 5011 of file stm32f10x.h.

#define FSMC_PCR3_PWAITEN ((uint32_t)0x00000002)

Wait feature enable bit

Definition at line 5009 of file stm32f10x.h.

#define FSMC_PCR3_PWID ((uint32_t)0x00000030)

PWID[1:0] bits (NAND Flash databus width)

Definition at line 5013 of file stm32f10x.h.

#define FSMC_PCR3_PWID_0 ((uint32_t)0x00000010)

Bit 0

Definition at line 5014 of file stm32f10x.h.

#define FSMC_PCR3_PWID_1 ((uint32_t)0x00000020)

Bit 1

Definition at line 5015 of file stm32f10x.h.

#define FSMC_PCR3_TAR ((uint32_t)0x0001E000)

TAR[3:0] bits (ALE to RE delay)

Definition at line 5025 of file stm32f10x.h.

#define FSMC_PCR3_TAR_0 ((uint32_t)0x00002000)

Bit 0

Definition at line 5026 of file stm32f10x.h.

#define FSMC_PCR3_TAR_1 ((uint32_t)0x00004000)

Bit 1

Definition at line 5027 of file stm32f10x.h.

#define FSMC_PCR3_TAR_2 ((uint32_t)0x00008000)

Bit 2

Definition at line 5028 of file stm32f10x.h.

#define FSMC_PCR3_TAR_3 ((uint32_t)0x00010000)

Bit 3

Definition at line 5029 of file stm32f10x.h.

#define FSMC_PCR3_TCLR ((uint32_t)0x00001E00)

TCLR[3:0] bits (CLE to RE delay)

Definition at line 5019 of file stm32f10x.h.

#define FSMC_PCR3_TCLR_0 ((uint32_t)0x00000200)

Bit 0

Definition at line 5020 of file stm32f10x.h.

#define FSMC_PCR3_TCLR_1 ((uint32_t)0x00000400)

Bit 1

Definition at line 5021 of file stm32f10x.h.

#define FSMC_PCR3_TCLR_2 ((uint32_t)0x00000800)

Bit 2

Definition at line 5022 of file stm32f10x.h.

#define FSMC_PCR3_TCLR_3 ((uint32_t)0x00001000)

Bit 3

Definition at line 5023 of file stm32f10x.h.

#define FSMC_PCR4_ECCEN ((uint32_t)0x00000040)

ECC computation logic enable bit

Definition at line 5045 of file stm32f10x.h.

#define FSMC_PCR4_ECCPS ((uint32_t)0x000E0000)

ECCPS[2:0] bits (ECC page size)

Definition at line 5059 of file stm32f10x.h.

#define FSMC_PCR4_ECCPS_0 ((uint32_t)0x00020000)

Bit 0

Definition at line 5060 of file stm32f10x.h.

#define FSMC_PCR4_ECCPS_1 ((uint32_t)0x00040000)

Bit 1

Definition at line 5061 of file stm32f10x.h.

#define FSMC_PCR4_ECCPS_2 ((uint32_t)0x00080000)

Bit 2

Definition at line 5062 of file stm32f10x.h.

#define FSMC_PCR4_PBKEN ((uint32_t)0x00000004)

PC Card/NAND Flash memory bank enable bit

Definition at line 5038 of file stm32f10x.h.

#define FSMC_PCR4_PTYP ((uint32_t)0x00000008)

Memory type

Definition at line 5039 of file stm32f10x.h.

#define FSMC_PCR4_PWAITEN ((uint32_t)0x00000002)

Wait feature enable bit

Definition at line 5037 of file stm32f10x.h.

#define FSMC_PCR4_PWID ((uint32_t)0x00000030)

PWID[1:0] bits (NAND Flash databus width)

Definition at line 5041 of file stm32f10x.h.

#define FSMC_PCR4_PWID_0 ((uint32_t)0x00000010)

Bit 0

Definition at line 5042 of file stm32f10x.h.

#define FSMC_PCR4_PWID_1 ((uint32_t)0x00000020)

Bit 1

Definition at line 5043 of file stm32f10x.h.

#define FSMC_PCR4_TAR ((uint32_t)0x0001E000)

TAR[3:0] bits (ALE to RE delay)

Definition at line 5053 of file stm32f10x.h.

#define FSMC_PCR4_TAR_0 ((uint32_t)0x00002000)

Bit 0

Definition at line 5054 of file stm32f10x.h.

#define FSMC_PCR4_TAR_1 ((uint32_t)0x00004000)

Bit 1

Definition at line 5055 of file stm32f10x.h.

#define FSMC_PCR4_TAR_2 ((uint32_t)0x00008000)

Bit 2

Definition at line 5056 of file stm32f10x.h.

#define FSMC_PCR4_TAR_3 ((uint32_t)0x00010000)

Bit 3

Definition at line 5057 of file stm32f10x.h.

#define FSMC_PCR4_TCLR ((uint32_t)0x00001E00)

TCLR[3:0] bits (CLE to RE delay)

Definition at line 5047 of file stm32f10x.h.

#define FSMC_PCR4_TCLR_0 ((uint32_t)0x00000200)

Bit 0

Definition at line 5048 of file stm32f10x.h.

#define FSMC_PCR4_TCLR_1 ((uint32_t)0x00000400)

Bit 1

Definition at line 5049 of file stm32f10x.h.

#define FSMC_PCR4_TCLR_2 ((uint32_t)0x00000800)

Bit 2

Definition at line 5050 of file stm32f10x.h.

#define FSMC_PCR4_TCLR_3 ((uint32_t)0x00001000)

Bit 3

Definition at line 5051 of file stm32f10x.h.

#define FSMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000)

IOHIZ4[7:0] bits (I/O 4 databus HiZ time)

Definition at line 5368 of file stm32f10x.h.

#define FSMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000)

Bit 0

Definition at line 5369 of file stm32f10x.h.

#define FSMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000)

Bit 1

Definition at line 5370 of file stm32f10x.h.

#define FSMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000)

Bit 2

Definition at line 5371 of file stm32f10x.h.

#define FSMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000)

Bit 3

Definition at line 5372 of file stm32f10x.h.

#define FSMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000)

Bit 4

Definition at line 5373 of file stm32f10x.h.

#define FSMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000)

Bit 5

Definition at line 5374 of file stm32f10x.h.

#define FSMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000)

Bit 6

Definition at line 5375 of file stm32f10x.h.

#define FSMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000)

Bit 7

Definition at line 5376 of file stm32f10x.h.

#define FSMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000)

IOHOLD4[7:0] bits (I/O 4 hold time)

Definition at line 5358 of file stm32f10x.h.

#define FSMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000)

Bit 0

Definition at line 5359 of file stm32f10x.h.

#define FSMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000)

Bit 1

Definition at line 5360 of file stm32f10x.h.

#define FSMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000)

Bit 2

Definition at line 5361 of file stm32f10x.h.

#define FSMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000)

Bit 3

Definition at line 5362 of file stm32f10x.h.

#define FSMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000)

Bit 4

Definition at line 5363 of file stm32f10x.h.

#define FSMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000)

Bit 5

Definition at line 5364 of file stm32f10x.h.

#define FSMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000)

Bit 6

Definition at line 5365 of file stm32f10x.h.

#define FSMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000)

Bit 7

Definition at line 5366 of file stm32f10x.h.

#define FSMC_PIO4_IOSET4 ((uint32_t)0x000000FF)

IOSET4[7:0] bits (I/O 4 setup time)

Definition at line 5338 of file stm32f10x.h.

#define FSMC_PIO4_IOSET4_0 ((uint32_t)0x00000001)

Bit 0

Definition at line 5339 of file stm32f10x.h.

#define FSMC_PIO4_IOSET4_1 ((uint32_t)0x00000002)

Bit 1

Definition at line 5340 of file stm32f10x.h.

#define FSMC_PIO4_IOSET4_2 ((uint32_t)0x00000004)

Bit 2

Definition at line 5341 of file stm32f10x.h.

#define FSMC_PIO4_IOSET4_3 ((uint32_t)0x00000008)

Bit 3

Definition at line 5342 of file stm32f10x.h.

#define FSMC_PIO4_IOSET4_4 ((uint32_t)0x00000010)

Bit 4

Definition at line 5343 of file stm32f10x.h.

#define FSMC_PIO4_IOSET4_5 ((uint32_t)0x00000020)

Bit 5

Definition at line 5344 of file stm32f10x.h.

#define FSMC_PIO4_IOSET4_6 ((uint32_t)0x00000040)

Bit 6

Definition at line 5345 of file stm32f10x.h.

#define FSMC_PIO4_IOSET4_7 ((uint32_t)0x00000080)

Bit 7

Definition at line 5346 of file stm32f10x.h.

#define FSMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00)

IOWAIT4[7:0] bits (I/O 4 wait time)

Definition at line 5348 of file stm32f10x.h.

#define FSMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100)

Bit 0

Definition at line 5349 of file stm32f10x.h.

#define FSMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200)

Bit 1

Definition at line 5350 of file stm32f10x.h.

#define FSMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400)

Bit 2

Definition at line 5351 of file stm32f10x.h.

#define FSMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800)

Bit 3

Definition at line 5352 of file stm32f10x.h.

#define FSMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000)

Bit 4

Definition at line 5353 of file stm32f10x.h.

#define FSMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000)

Bit 5

Definition at line 5354 of file stm32f10x.h.

#define FSMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000)

Bit 6

Definition at line 5355 of file stm32f10x.h.

#define FSMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000)

Bit 7

Definition at line 5356 of file stm32f10x.h.

#define FSMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000)

MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time)

Definition at line 5122 of file stm32f10x.h.

#define FSMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000)

Bit 0

Definition at line 5123 of file stm32f10x.h.

#define FSMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000)

Bit 1

Definition at line 5124 of file stm32f10x.h.

#define FSMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000)

Bit 2

Definition at line 5125 of file stm32f10x.h.

#define FSMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000)

Bit 3

Definition at line 5126 of file stm32f10x.h.

#define FSMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000)

Bit 4

Definition at line 5127 of file stm32f10x.h.

#define FSMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000)

Bit 5

Definition at line 5128 of file stm32f10x.h.

#define FSMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000)

Bit 6

Definition at line 5129 of file stm32f10x.h.

#define FSMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000)

Bit 7

Definition at line 5130 of file stm32f10x.h.

#define FSMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000)

MEMHOLD2[7:0] bits (Common memory 2 hold time)

Definition at line 5112 of file stm32f10x.h.

#define FSMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000)

Bit 0

Definition at line 5113 of file stm32f10x.h.

#define FSMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000)

Bit 1

Definition at line 5114 of file stm32f10x.h.

#define FSMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000)

Bit 2

Definition at line 5115 of file stm32f10x.h.

#define FSMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000)

Bit 3

Definition at line 5116 of file stm32f10x.h.

#define FSMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000)

Bit 4

Definition at line 5117 of file stm32f10x.h.

#define FSMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000)

Bit 5

Definition at line 5118 of file stm32f10x.h.

#define FSMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000)

Bit 6

Definition at line 5119 of file stm32f10x.h.

#define FSMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000)

Bit 7

Definition at line 5120 of file stm32f10x.h.

#define FSMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF)

MEMSET2[7:0] bits (Common memory 2 setup time)

Definition at line 5092 of file stm32f10x.h.

#define FSMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001)

Bit 0

Definition at line 5093 of file stm32f10x.h.

#define FSMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002)

Bit 1

Definition at line 5094 of file stm32f10x.h.

#define FSMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004)

Bit 2

Definition at line 5095 of file stm32f10x.h.

#define FSMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008)

Bit 3

Definition at line 5096 of file stm32f10x.h.

#define FSMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010)

Bit 4

Definition at line 5097 of file stm32f10x.h.

#define FSMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020)

Bit 5

Definition at line 5098 of file stm32f10x.h.

#define FSMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040)

Bit 6

Definition at line 5099 of file stm32f10x.h.

#define FSMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080)

Bit 7

Definition at line 5100 of file stm32f10x.h.

#define FSMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00)

MEMWAIT2[7:0] bits (Common memory 2 wait time)

Definition at line 5102 of file stm32f10x.h.

#define FSMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100)

Bit 0

Definition at line 5103 of file stm32f10x.h.

#define FSMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200)

Bit 1

Definition at line 5104 of file stm32f10x.h.

#define FSMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400)

Bit 2

Definition at line 5105 of file stm32f10x.h.

#define FSMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800)

Bit 3

Definition at line 5106 of file stm32f10x.h.

#define FSMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000)

Bit 4

Definition at line 5107 of file stm32f10x.h.

#define FSMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000)

Bit 5

Definition at line 5108 of file stm32f10x.h.

#define FSMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000)

Bit 6

Definition at line 5109 of file stm32f10x.h.

#define FSMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000)

Bit 7

Definition at line 5110 of file stm32f10x.h.

#define FSMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000)

MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time)

Definition at line 5163 of file stm32f10x.h.

#define FSMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000)

Bit 0

Definition at line 5164 of file stm32f10x.h.

#define FSMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000)

Bit 1

Definition at line 5165 of file stm32f10x.h.

#define FSMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000)

Bit 2

Definition at line 5166 of file stm32f10x.h.

#define FSMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000)

Bit 3

Definition at line 5167 of file stm32f10x.h.

#define FSMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000)

Bit 4

Definition at line 5168 of file stm32f10x.h.

#define FSMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000)

Bit 5

Definition at line 5169 of file stm32f10x.h.

#define FSMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000)

Bit 6

Definition at line 5170 of file stm32f10x.h.

#define FSMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000)

Bit 7

Definition at line 5171 of file stm32f10x.h.

#define FSMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000)

MEMHOLD3[7:0] bits (Common memory 3 hold time)

Definition at line 5153 of file stm32f10x.h.

#define FSMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000)

Bit 0

Definition at line 5154 of file stm32f10x.h.

#define FSMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000)

Bit 1

Definition at line 5155 of file stm32f10x.h.

#define FSMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000)

Bit 2

Definition at line 5156 of file stm32f10x.h.

#define FSMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000)

Bit 3

Definition at line 5157 of file stm32f10x.h.

#define FSMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000)

Bit 4

Definition at line 5158 of file stm32f10x.h.

#define FSMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000)

Bit 5

Definition at line 5159 of file stm32f10x.h.

#define FSMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000)

Bit 6

Definition at line 5160 of file stm32f10x.h.

#define FSMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000)

Bit 7

Definition at line 5161 of file stm32f10x.h.

#define FSMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF)

MEMSET3[7:0] bits (Common memory 3 setup time)

Definition at line 5133 of file stm32f10x.h.

#define FSMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001)

Bit 0

Definition at line 5134 of file stm32f10x.h.

#define FSMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002)

Bit 1

Definition at line 5135 of file stm32f10x.h.

#define FSMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004)

Bit 2

Definition at line 5136 of file stm32f10x.h.

#define FSMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008)

Bit 3

Definition at line 5137 of file stm32f10x.h.

#define FSMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010)

Bit 4

Definition at line 5138 of file stm32f10x.h.

#define FSMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020)

Bit 5

Definition at line 5139 of file stm32f10x.h.

#define FSMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040)

Bit 6

Definition at line 5140 of file stm32f10x.h.

#define FSMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080)

Bit 7

Definition at line 5141 of file stm32f10x.h.

#define FSMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00)

MEMWAIT3[7:0] bits (Common memory 3 wait time)

Definition at line 5143 of file stm32f10x.h.

#define FSMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100)

Bit 0

Definition at line 5144 of file stm32f10x.h.

#define FSMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200)

Bit 1

Definition at line 5145 of file stm32f10x.h.

#define FSMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400)

Bit 2

Definition at line 5146 of file stm32f10x.h.

#define FSMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800)

Bit 3

Definition at line 5147 of file stm32f10x.h.

#define FSMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000)

Bit 4

Definition at line 5148 of file stm32f10x.h.

#define FSMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000)

Bit 5

Definition at line 5149 of file stm32f10x.h.

#define FSMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000)

Bit 6

Definition at line 5150 of file stm32f10x.h.

#define FSMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000)

Bit 7

Definition at line 5151 of file stm32f10x.h.

#define FSMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000)

MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time)

Definition at line 5204 of file stm32f10x.h.

#define FSMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000)

Bit 0

Definition at line 5205 of file stm32f10x.h.

#define FSMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000)

Bit 1

Definition at line 5206 of file stm32f10x.h.

#define FSMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000)

Bit 2

Definition at line 5207 of file stm32f10x.h.

#define FSMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000)

Bit 3

Definition at line 5208 of file stm32f10x.h.

#define FSMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000)

Bit 4

Definition at line 5209 of file stm32f10x.h.

#define FSMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000)

Bit 5

Definition at line 5210 of file stm32f10x.h.

#define FSMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000)

Bit 6

Definition at line 5211 of file stm32f10x.h.

#define FSMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000)

Bit 7

Definition at line 5212 of file stm32f10x.h.

#define FSMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000)

MEMHOLD4[7:0] bits (Common memory 4 hold time)

Definition at line 5194 of file stm32f10x.h.

#define FSMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000)

Bit 0

Definition at line 5195 of file stm32f10x.h.

#define FSMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000)

Bit 1

Definition at line 5196 of file stm32f10x.h.

#define FSMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000)

Bit 2

Definition at line 5197 of file stm32f10x.h.

#define FSMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000)

Bit 3

Definition at line 5198 of file stm32f10x.h.

#define FSMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000)

Bit 4

Definition at line 5199 of file stm32f10x.h.

#define FSMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000)

Bit 5

Definition at line 5200 of file stm32f10x.h.

#define FSMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000)

Bit 6

Definition at line 5201 of file stm32f10x.h.

#define FSMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000)

Bit 7

Definition at line 5202 of file stm32f10x.h.

#define FSMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF)

MEMSET4[7:0] bits (Common memory 4 setup time)

Definition at line 5174 of file stm32f10x.h.

#define FSMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001)

Bit 0

Definition at line 5175 of file stm32f10x.h.

#define FSMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002)

Bit 1

Definition at line 5176 of file stm32f10x.h.

#define FSMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004)

Bit 2

Definition at line 5177 of file stm32f10x.h.

#define FSMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008)

Bit 3

Definition at line 5178 of file stm32f10x.h.

#define FSMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010)

Bit 4

Definition at line 5179 of file stm32f10x.h.

#define FSMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020)

Bit 5

Definition at line 5180 of file stm32f10x.h.

#define FSMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040)

Bit 6

Definition at line 5181 of file stm32f10x.h.

#define FSMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080)

Bit 7

Definition at line 5182 of file stm32f10x.h.

#define FSMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00)

MEMWAIT4[7:0] bits (Common memory 4 wait time)

Definition at line 5184 of file stm32f10x.h.

#define FSMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100)

Bit 0

Definition at line 5185 of file stm32f10x.h.

#define FSMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200)

Bit 1

Definition at line 5186 of file stm32f10x.h.

#define FSMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400)

Bit 2

Definition at line 5187 of file stm32f10x.h.

#define FSMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800)

Bit 3

Definition at line 5188 of file stm32f10x.h.

#define FSMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000)

Bit 4

Definition at line 5189 of file stm32f10x.h.

#define FSMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000)

Bit 5

Definition at line 5190 of file stm32f10x.h.

#define FSMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000)

Bit 6

Definition at line 5191 of file stm32f10x.h.

#define FSMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000)

Bit 7

Definition at line 5192 of file stm32f10x.h.

#define FSMC_SR2_FEMPT ((uint8_t)0x40)

FIFO empty

Definition at line 5071 of file stm32f10x.h.

#define FSMC_SR2_IFEN ((uint8_t)0x20)

Interrupt Falling Edge detection Enable bit

Definition at line 5070 of file stm32f10x.h.

#define FSMC_SR2_IFS ((uint8_t)0x04)

Interrupt Falling Edge status

Definition at line 5067 of file stm32f10x.h.

#define FSMC_SR2_ILEN ((uint8_t)0x10)

Interrupt Level detection Enable bit

Definition at line 5069 of file stm32f10x.h.

#define FSMC_SR2_ILS ((uint8_t)0x02)

Interrupt Level status

Definition at line 5066 of file stm32f10x.h.

#define FSMC_SR2_IREN ((uint8_t)0x08)

Interrupt Rising Edge detection Enable bit

Definition at line 5068 of file stm32f10x.h.

#define FSMC_SR2_IRS ((uint8_t)0x01)

Interrupt Rising Edge status

Definition at line 5065 of file stm32f10x.h.

#define FSMC_SR3_FEMPT ((uint8_t)0x40)

FIFO empty

Definition at line 5080 of file stm32f10x.h.

#define FSMC_SR3_IFEN ((uint8_t)0x20)

Interrupt Falling Edge detection Enable bit

Definition at line 5079 of file stm32f10x.h.

#define FSMC_SR3_IFS ((uint8_t)0x04)

Interrupt Falling Edge status

Definition at line 5076 of file stm32f10x.h.

#define FSMC_SR3_ILEN ((uint8_t)0x10)

Interrupt Level detection Enable bit

Definition at line 5078 of file stm32f10x.h.

#define FSMC_SR3_ILS ((uint8_t)0x02)

Interrupt Level status

Definition at line 5075 of file stm32f10x.h.

#define FSMC_SR3_IREN ((uint8_t)0x08)

Interrupt Rising Edge detection Enable bit

Definition at line 5077 of file stm32f10x.h.

#define FSMC_SR3_IRS ((uint8_t)0x01)

Interrupt Rising Edge status

Definition at line 5074 of file stm32f10x.h.

#define FSMC_SR4_FEMPT ((uint8_t)0x40)

FIFO empty

Definition at line 5089 of file stm32f10x.h.

#define FSMC_SR4_IFEN ((uint8_t)0x20)

Interrupt Falling Edge detection Enable bit

Definition at line 5088 of file stm32f10x.h.

#define FSMC_SR4_IFS ((uint8_t)0x04)

Interrupt Falling Edge status

Definition at line 5085 of file stm32f10x.h.

#define FSMC_SR4_ILEN ((uint8_t)0x10)

Interrupt Level detection Enable bit

Definition at line 5087 of file stm32f10x.h.

#define FSMC_SR4_ILS ((uint8_t)0x02)

Interrupt Level status

Definition at line 5084 of file stm32f10x.h.

#define FSMC_SR4_IREN ((uint8_t)0x08)

Interrupt Rising Edge detection Enable bit

Definition at line 5086 of file stm32f10x.h.

#define FSMC_SR4_IRS ((uint8_t)0x01)

Interrupt Rising Edge status

Definition at line 5083 of file stm32f10x.h.

#define GPIO_BRR_BR0 ((uint16_t)0x0001)

Port x Reset bit 0

Definition at line 2517 of file stm32f10x.h.

#define GPIO_BRR_BR1 ((uint16_t)0x0002)

Port x Reset bit 1

Definition at line 2518 of file stm32f10x.h.

#define GPIO_BRR_BR10 ((uint16_t)0x0400)

Port x Reset bit 10

Definition at line 2527 of file stm32f10x.h.

#define GPIO_BRR_BR11 ((uint16_t)0x0800)

Port x Reset bit 11

Definition at line 2528 of file stm32f10x.h.

#define GPIO_BRR_BR12 ((uint16_t)0x1000)

Port x Reset bit 12

Definition at line 2529 of file stm32f10x.h.

#define GPIO_BRR_BR13 ((uint16_t)0x2000)

Port x Reset bit 13

Definition at line 2530 of file stm32f10x.h.

#define GPIO_BRR_BR14 ((uint16_t)0x4000)

Port x Reset bit 14

Definition at line 2531 of file stm32f10x.h.

#define GPIO_BRR_BR15 ((uint16_t)0x8000)

Port x Reset bit 15

Definition at line 2532 of file stm32f10x.h.

#define GPIO_BRR_BR2 ((uint16_t)0x0004)

Port x Reset bit 2

Definition at line 2519 of file stm32f10x.h.

#define GPIO_BRR_BR3 ((uint16_t)0x0008)

Port x Reset bit 3

Definition at line 2520 of file stm32f10x.h.

#define GPIO_BRR_BR4 ((uint16_t)0x0010)

Port x Reset bit 4

Definition at line 2521 of file stm32f10x.h.

#define GPIO_BRR_BR5 ((uint16_t)0x0020)

Port x Reset bit 5

Definition at line 2522 of file stm32f10x.h.

#define GPIO_BRR_BR6 ((uint16_t)0x0040)

Port x Reset bit 6

Definition at line 2523 of file stm32f10x.h.

#define GPIO_BRR_BR7 ((uint16_t)0x0080)

Port x Reset bit 7

Definition at line 2524 of file stm32f10x.h.

#define GPIO_BRR_BR8 ((uint16_t)0x0100)

Port x Reset bit 8

Definition at line 2525 of file stm32f10x.h.

#define GPIO_BRR_BR9 ((uint16_t)0x0200)

Port x Reset bit 9

Definition at line 2526 of file stm32f10x.h.

#define GPIO_BSRR_BR0 ((uint32_t)0x00010000)

Port x Reset bit 0

Definition at line 2499 of file stm32f10x.h.

#define GPIO_BSRR_BR1 ((uint32_t)0x00020000)

Port x Reset bit 1

Definition at line 2500 of file stm32f10x.h.

#define GPIO_BSRR_BR10 ((uint32_t)0x04000000)

Port x Reset bit 10

Definition at line 2509 of file stm32f10x.h.

#define GPIO_BSRR_BR11 ((uint32_t)0x08000000)

Port x Reset bit 11

Definition at line 2510 of file stm32f10x.h.

#define GPIO_BSRR_BR12 ((uint32_t)0x10000000)

Port x Reset bit 12

Definition at line 2511 of file stm32f10x.h.

#define GPIO_BSRR_BR13 ((uint32_t)0x20000000)

Port x Reset bit 13

Definition at line 2512 of file stm32f10x.h.

#define GPIO_BSRR_BR14 ((uint32_t)0x40000000)

Port x Reset bit 14

Definition at line 2513 of file stm32f10x.h.

#define GPIO_BSRR_BR15 ((uint32_t)0x80000000)

Port x Reset bit 15

Definition at line 2514 of file stm32f10x.h.

#define GPIO_BSRR_BR2 ((uint32_t)0x00040000)

Port x Reset bit 2

Definition at line 2501 of file stm32f10x.h.

#define GPIO_BSRR_BR3 ((uint32_t)0x00080000)

Port x Reset bit 3

Definition at line 2502 of file stm32f10x.h.

#define GPIO_BSRR_BR4 ((uint32_t)0x00100000)

Port x Reset bit 4

Definition at line 2503 of file stm32f10x.h.

#define GPIO_BSRR_BR5 ((uint32_t)0x00200000)

Port x Reset bit 5

Definition at line 2504 of file stm32f10x.h.

#define GPIO_BSRR_BR6 ((uint32_t)0x00400000)

Port x Reset bit 6

Definition at line 2505 of file stm32f10x.h.

#define GPIO_BSRR_BR7 ((uint32_t)0x00800000)

Port x Reset bit 7

Definition at line 2506 of file stm32f10x.h.

#define GPIO_BSRR_BR8 ((uint32_t)0x01000000)

Port x Reset bit 8

Definition at line 2507 of file stm32f10x.h.

#define GPIO_BSRR_BR9 ((uint32_t)0x02000000)

Port x Reset bit 9

Definition at line 2508 of file stm32f10x.h.

#define GPIO_BSRR_BS0 ((uint32_t)0x00000001)

Port x Set bit 0

Definition at line 2482 of file stm32f10x.h.

#define GPIO_BSRR_BS1 ((uint32_t)0x00000002)

Port x Set bit 1

Definition at line 2483 of file stm32f10x.h.

#define GPIO_BSRR_BS10 ((uint32_t)0x00000400)

Port x Set bit 10

Definition at line 2492 of file stm32f10x.h.

#define GPIO_BSRR_BS11 ((uint32_t)0x00000800)

Port x Set bit 11

Definition at line 2493 of file stm32f10x.h.

#define GPIO_BSRR_BS12 ((uint32_t)0x00001000)

Port x Set bit 12

Definition at line 2494 of file stm32f10x.h.

#define GPIO_BSRR_BS13 ((uint32_t)0x00002000)

Port x Set bit 13

Definition at line 2495 of file stm32f10x.h.

#define GPIO_BSRR_BS14 ((uint32_t)0x00004000)

Port x Set bit 14

Definition at line 2496 of file stm32f10x.h.

#define GPIO_BSRR_BS15 ((uint32_t)0x00008000)

Port x Set bit 15

Definition at line 2497 of file stm32f10x.h.

#define GPIO_BSRR_BS2 ((uint32_t)0x00000004)

Port x Set bit 2

Definition at line 2484 of file stm32f10x.h.

#define GPIO_BSRR_BS3 ((uint32_t)0x00000008)

Port x Set bit 3

Definition at line 2485 of file stm32f10x.h.

#define GPIO_BSRR_BS4 ((uint32_t)0x00000010)

Port x Set bit 4

Definition at line 2486 of file stm32f10x.h.

#define GPIO_BSRR_BS5 ((uint32_t)0x00000020)

Port x Set bit 5

Definition at line 2487 of file stm32f10x.h.

#define GPIO_BSRR_BS6 ((uint32_t)0x00000040)

Port x Set bit 6

Definition at line 2488 of file stm32f10x.h.

#define GPIO_BSRR_BS7 ((uint32_t)0x00000080)

Port x Set bit 7

Definition at line 2489 of file stm32f10x.h.

#define GPIO_BSRR_BS8 ((uint32_t)0x00000100)

Port x Set bit 8

Definition at line 2490 of file stm32f10x.h.

#define GPIO_BSRR_BS9 ((uint32_t)0x00000200)

Port x Set bit 9

Definition at line 2491 of file stm32f10x.h.

#define GPIO_CRH_CNF ((uint32_t)0xCCCCCCCC)

Port x configuration bits

Definition at line 2411 of file stm32f10x.h.

#define GPIO_CRH_CNF10 ((uint32_t)0x00000C00)

CNF10[1:0] bits (Port x configuration bits, pin 10)

Definition at line 2421 of file stm32f10x.h.

#define GPIO_CRH_CNF10_0 ((uint32_t)0x00000400)

Bit 0

Definition at line 2422 of file stm32f10x.h.

#define GPIO_CRH_CNF10_1 ((uint32_t)0x00000800)

Bit 1

Definition at line 2423 of file stm32f10x.h.

#define GPIO_CRH_CNF11 ((uint32_t)0x0000C000)

CNF11[1:0] bits (Port x configuration bits, pin 11)

Definition at line 2425 of file stm32f10x.h.

#define GPIO_CRH_CNF11_0 ((uint32_t)0x00004000)

Bit 0

Definition at line 2426 of file stm32f10x.h.

#define GPIO_CRH_CNF11_1 ((uint32_t)0x00008000)

Bit 1

Definition at line 2427 of file stm32f10x.h.

#define GPIO_CRH_CNF12 ((uint32_t)0x000C0000)

CNF12[1:0] bits (Port x configuration bits, pin 12)

Definition at line 2429 of file stm32f10x.h.

#define GPIO_CRH_CNF12_0 ((uint32_t)0x00040000)

Bit 0

Definition at line 2430 of file stm32f10x.h.

#define GPIO_CRH_CNF12_1 ((uint32_t)0x00080000)

Bit 1

Definition at line 2431 of file stm32f10x.h.

#define GPIO_CRH_CNF13 ((uint32_t)0x00C00000)

CNF13[1:0] bits (Port x configuration bits, pin 13)

Definition at line 2433 of file stm32f10x.h.

#define GPIO_CRH_CNF13_0 ((uint32_t)0x00400000)

Bit 0

Definition at line 2434 of file stm32f10x.h.

#define GPIO_CRH_CNF13_1 ((uint32_t)0x00800000)

Bit 1

Definition at line 2435 of file stm32f10x.h.

#define GPIO_CRH_CNF14 ((uint32_t)0x0C000000)

CNF14[1:0] bits (Port x configuration bits, pin 14)

Definition at line 2437 of file stm32f10x.h.

#define GPIO_CRH_CNF14_0 ((uint32_t)0x04000000)

Bit 0

Definition at line 2438 of file stm32f10x.h.

#define GPIO_CRH_CNF14_1 ((uint32_t)0x08000000)

Bit 1

Definition at line 2439 of file stm32f10x.h.

#define GPIO_CRH_CNF15 ((uint32_t)0xC0000000)

CNF15[1:0] bits (Port x configuration bits, pin 15)

Definition at line 2441 of file stm32f10x.h.

#define GPIO_CRH_CNF15_0 ((uint32_t)0x40000000)

Bit 0

Definition at line 2442 of file stm32f10x.h.

#define GPIO_CRH_CNF15_1 ((uint32_t)0x80000000)

Bit 1 ****************** Bit definition for GPIO_IDR register

Definition at line 2443 of file stm32f10x.h.

#define GPIO_CRH_CNF8 ((uint32_t)0x0000000C)

CNF8[1:0] bits (Port x configuration bits, pin 8)

Definition at line 2413 of file stm32f10x.h.

#define GPIO_CRH_CNF8_0 ((uint32_t)0x00000004)

Bit 0

Definition at line 2414 of file stm32f10x.h.

#define GPIO_CRH_CNF8_1 ((uint32_t)0x00000008)

Bit 1

Definition at line 2415 of file stm32f10x.h.

#define GPIO_CRH_CNF9 ((uint32_t)0x000000C0)

CNF9[1:0] bits (Port x configuration bits, pin 9)

Definition at line 2417 of file stm32f10x.h.

#define GPIO_CRH_CNF9_0 ((uint32_t)0x00000040)

Bit 0

Definition at line 2418 of file stm32f10x.h.

#define GPIO_CRH_CNF9_1 ((uint32_t)0x00000080)

Bit 1

Definition at line 2419 of file stm32f10x.h.

#define GPIO_CRH_MODE ((uint32_t)0x33333333)

Port x mode bits

Definition at line 2377 of file stm32f10x.h.

#define GPIO_CRH_MODE10 ((uint32_t)0x00000300)

MODE10[1:0] bits (Port x mode bits, pin 10)

Definition at line 2387 of file stm32f10x.h.

#define GPIO_CRH_MODE10_0 ((uint32_t)0x00000100)

Bit 0

Definition at line 2388 of file stm32f10x.h.

#define GPIO_CRH_MODE10_1 ((uint32_t)0x00000200)

Bit 1

Definition at line 2389 of file stm32f10x.h.

#define GPIO_CRH_MODE11 ((uint32_t)0x00003000)

MODE11[1:0] bits (Port x mode bits, pin 11)

Definition at line 2391 of file stm32f10x.h.

#define GPIO_CRH_MODE11_0 ((uint32_t)0x00001000)

Bit 0

Definition at line 2392 of file stm32f10x.h.

#define GPIO_CRH_MODE11_1 ((uint32_t)0x00002000)

Bit 1

Definition at line 2393 of file stm32f10x.h.

#define GPIO_CRH_MODE12 ((uint32_t)0x00030000)

MODE12[1:0] bits (Port x mode bits, pin 12)

Definition at line 2395 of file stm32f10x.h.

#define GPIO_CRH_MODE12_0 ((uint32_t)0x00010000)

Bit 0

Definition at line 2396 of file stm32f10x.h.

#define GPIO_CRH_MODE12_1 ((uint32_t)0x00020000)

Bit 1

Definition at line 2397 of file stm32f10x.h.

#define GPIO_CRH_MODE13 ((uint32_t)0x00300000)

MODE13[1:0] bits (Port x mode bits, pin 13)

Definition at line 2399 of file stm32f10x.h.

#define GPIO_CRH_MODE13_0 ((uint32_t)0x00100000)

Bit 0

Definition at line 2400 of file stm32f10x.h.

#define GPIO_CRH_MODE13_1 ((uint32_t)0x00200000)

Bit 1

Definition at line 2401 of file stm32f10x.h.

#define GPIO_CRH_MODE14 ((uint32_t)0x03000000)

MODE14[1:0] bits (Port x mode bits, pin 14)

Definition at line 2403 of file stm32f10x.h.

#define GPIO_CRH_MODE14_0 ((uint32_t)0x01000000)

Bit 0

Definition at line 2404 of file stm32f10x.h.

#define GPIO_CRH_MODE14_1 ((uint32_t)0x02000000)

Bit 1

Definition at line 2405 of file stm32f10x.h.

#define GPIO_CRH_MODE15 ((uint32_t)0x30000000)

MODE15[1:0] bits (Port x mode bits, pin 15)

Definition at line 2407 of file stm32f10x.h.

#define GPIO_CRH_MODE15_0 ((uint32_t)0x10000000)

Bit 0

Definition at line 2408 of file stm32f10x.h.

#define GPIO_CRH_MODE15_1 ((uint32_t)0x20000000)

Bit 1

Definition at line 2409 of file stm32f10x.h.

#define GPIO_CRH_MODE8 ((uint32_t)0x00000003)

MODE8[1:0] bits (Port x mode bits, pin 8)

Definition at line 2379 of file stm32f10x.h.

#define GPIO_CRH_MODE8_0 ((uint32_t)0x00000001)

Bit 0

Definition at line 2380 of file stm32f10x.h.

#define GPIO_CRH_MODE8_1 ((uint32_t)0x00000002)

Bit 1

Definition at line 2381 of file stm32f10x.h.

#define GPIO_CRH_MODE9 ((uint32_t)0x00000030)

MODE9[1:0] bits (Port x mode bits, pin 9)

Definition at line 2383 of file stm32f10x.h.

#define GPIO_CRH_MODE9_0 ((uint32_t)0x00000010)

Bit 0

Definition at line 2384 of file stm32f10x.h.

#define GPIO_CRH_MODE9_1 ((uint32_t)0x00000020)

Bit 1

Definition at line 2385 of file stm32f10x.h.

#define GPIO_CRL_CNF ((uint32_t)0xCCCCCCCC)

Port x configuration bits

Definition at line 2342 of file stm32f10x.h.

#define GPIO_CRL_CNF0 ((uint32_t)0x0000000C)

CNF0[1:0] bits (Port x configuration bits, pin 0)

Definition at line 2344 of file stm32f10x.h.

#define GPIO_CRL_CNF0_0 ((uint32_t)0x00000004)

Bit 0

Definition at line 2345 of file stm32f10x.h.

#define GPIO_CRL_CNF0_1 ((uint32_t)0x00000008)

Bit 1

Definition at line 2346 of file stm32f10x.h.

#define GPIO_CRL_CNF1 ((uint32_t)0x000000C0)

CNF1[1:0] bits (Port x configuration bits, pin 1)

Definition at line 2348 of file stm32f10x.h.

#define GPIO_CRL_CNF1_0 ((uint32_t)0x00000040)

Bit 0

Definition at line 2349 of file stm32f10x.h.

#define GPIO_CRL_CNF1_1 ((uint32_t)0x00000080)

Bit 1

Definition at line 2350 of file stm32f10x.h.

#define GPIO_CRL_CNF2 ((uint32_t)0x00000C00)

CNF2[1:0] bits (Port x configuration bits, pin 2)

Definition at line 2352 of file stm32f10x.h.

#define GPIO_CRL_CNF2_0 ((uint32_t)0x00000400)

Bit 0

Definition at line 2353 of file stm32f10x.h.

#define GPIO_CRL_CNF2_1 ((uint32_t)0x00000800)

Bit 1

Definition at line 2354 of file stm32f10x.h.

#define GPIO_CRL_CNF3 ((uint32_t)0x0000C000)

CNF3[1:0] bits (Port x configuration bits, pin 3)

Definition at line 2356 of file stm32f10x.h.

#define GPIO_CRL_CNF3_0 ((uint32_t)0x00004000)

Bit 0

Definition at line 2357 of file stm32f10x.h.

#define GPIO_CRL_CNF3_1 ((uint32_t)0x00008000)

Bit 1

Definition at line 2358 of file stm32f10x.h.

#define GPIO_CRL_CNF4 ((uint32_t)0x000C0000)

CNF4[1:0] bits (Port x configuration bits, pin 4)

Definition at line 2360 of file stm32f10x.h.

#define GPIO_CRL_CNF4_0 ((uint32_t)0x00040000)

Bit 0

Definition at line 2361 of file stm32f10x.h.

#define GPIO_CRL_CNF4_1 ((uint32_t)0x00080000)

Bit 1

Definition at line 2362 of file stm32f10x.h.

#define GPIO_CRL_CNF5 ((uint32_t)0x00C00000)

CNF5[1:0] bits (Port x configuration bits, pin 5)

Definition at line 2364 of file stm32f10x.h.

#define GPIO_CRL_CNF5_0 ((uint32_t)0x00400000)

Bit 0

Definition at line 2365 of file stm32f10x.h.

#define GPIO_CRL_CNF5_1 ((uint32_t)0x00800000)

Bit 1

Definition at line 2366 of file stm32f10x.h.

#define GPIO_CRL_CNF6 ((uint32_t)0x0C000000)

CNF6[1:0] bits (Port x configuration bits, pin 6)

Definition at line 2368 of file stm32f10x.h.

#define GPIO_CRL_CNF6_0 ((uint32_t)0x04000000)

Bit 0

Definition at line 2369 of file stm32f10x.h.

#define GPIO_CRL_CNF6_1 ((uint32_t)0x08000000)

Bit 1

Definition at line 2370 of file stm32f10x.h.

#define GPIO_CRL_CNF7 ((uint32_t)0xC0000000)

CNF7[1:0] bits (Port x configuration bits, pin 7)

Definition at line 2372 of file stm32f10x.h.

#define GPIO_CRL_CNF7_0 ((uint32_t)0x40000000)

Bit 0

Definition at line 2373 of file stm32f10x.h.

#define GPIO_CRL_CNF7_1 ((uint32_t)0x80000000)

Bit 1

Definition at line 2374 of file stm32f10x.h.

#define GPIO_CRL_MODE ((uint32_t)0x33333333)

Port x mode bits

Definition at line 2308 of file stm32f10x.h.

#define GPIO_CRL_MODE0 ((uint32_t)0x00000003)

MODE0[1:0] bits (Port x mode bits, pin 0)

Definition at line 2310 of file stm32f10x.h.

#define GPIO_CRL_MODE0_0 ((uint32_t)0x00000001)

Bit 0

Definition at line 2311 of file stm32f10x.h.

#define GPIO_CRL_MODE0_1 ((uint32_t)0x00000002)

Bit 1

Definition at line 2312 of file stm32f10x.h.

#define GPIO_CRL_MODE1 ((uint32_t)0x00000030)

MODE1[1:0] bits (Port x mode bits, pin 1)

Definition at line 2314 of file stm32f10x.h.

#define GPIO_CRL_MODE1_0 ((uint32_t)0x00000010)

Bit 0

Definition at line 2315 of file stm32f10x.h.

#define GPIO_CRL_MODE1_1 ((uint32_t)0x00000020)

Bit 1

Definition at line 2316 of file stm32f10x.h.

#define GPIO_CRL_MODE2 ((uint32_t)0x00000300)

MODE2[1:0] bits (Port x mode bits, pin 2)

Definition at line 2318 of file stm32f10x.h.

#define GPIO_CRL_MODE2_0 ((uint32_t)0x00000100)

Bit 0

Definition at line 2319 of file stm32f10x.h.

#define GPIO_CRL_MODE2_1 ((uint32_t)0x00000200)

Bit 1

Definition at line 2320 of file stm32f10x.h.

#define GPIO_CRL_MODE3 ((uint32_t)0x00003000)

MODE3[1:0] bits (Port x mode bits, pin 3)

Definition at line 2322 of file stm32f10x.h.

#define GPIO_CRL_MODE3_0 ((uint32_t)0x00001000)

Bit 0

Definition at line 2323 of file stm32f10x.h.

#define GPIO_CRL_MODE3_1 ((uint32_t)0x00002000)

Bit 1

Definition at line 2324 of file stm32f10x.h.

#define GPIO_CRL_MODE4 ((uint32_t)0x00030000)

MODE4[1:0] bits (Port x mode bits, pin 4)

Definition at line 2326 of file stm32f10x.h.

#define GPIO_CRL_MODE4_0 ((uint32_t)0x00010000)

Bit 0

Definition at line 2327 of file stm32f10x.h.

#define GPIO_CRL_MODE4_1 ((uint32_t)0x00020000)

Bit 1

Definition at line 2328 of file stm32f10x.h.

#define GPIO_CRL_MODE5 ((uint32_t)0x00300000)

MODE5[1:0] bits (Port x mode bits, pin 5)

Definition at line 2330 of file stm32f10x.h.

#define GPIO_CRL_MODE5_0 ((uint32_t)0x00100000)

Bit 0

Definition at line 2331 of file stm32f10x.h.

#define GPIO_CRL_MODE5_1 ((uint32_t)0x00200000)

Bit 1

Definition at line 2332 of file stm32f10x.h.

#define GPIO_CRL_MODE6 ((uint32_t)0x03000000)

MODE6[1:0] bits (Port x mode bits, pin 6)

Definition at line 2334 of file stm32f10x.h.

#define GPIO_CRL_MODE6_0 ((uint32_t)0x01000000)

Bit 0

Definition at line 2335 of file stm32f10x.h.

#define GPIO_CRL_MODE6_1 ((uint32_t)0x02000000)

Bit 1

Definition at line 2336 of file stm32f10x.h.

#define GPIO_CRL_MODE7 ((uint32_t)0x30000000)

MODE7[1:0] bits (Port x mode bits, pin 7)

Definition at line 2338 of file stm32f10x.h.

#define GPIO_CRL_MODE7_0 ((uint32_t)0x10000000)

Bit 0

Definition at line 2339 of file stm32f10x.h.

#define GPIO_CRL_MODE7_1 ((uint32_t)0x20000000)

Bit 1

Definition at line 2340 of file stm32f10x.h.

#define GPIO_IDR_IDR0 ((uint16_t)0x0001)

Port input data, bit 0

Definition at line 2446 of file stm32f10x.h.

#define GPIO_IDR_IDR1 ((uint16_t)0x0002)

Port input data, bit 1

Definition at line 2447 of file stm32f10x.h.

#define GPIO_IDR_IDR10 ((uint16_t)0x0400)

Port input data, bit 10

Definition at line 2456 of file stm32f10x.h.

#define GPIO_IDR_IDR11 ((uint16_t)0x0800)

Port input data, bit 11

Definition at line 2457 of file stm32f10x.h.

#define GPIO_IDR_IDR12 ((uint16_t)0x1000)

Port input data, bit 12

Definition at line 2458 of file stm32f10x.h.

#define GPIO_IDR_IDR13 ((uint16_t)0x2000)

Port input data, bit 13

Definition at line 2459 of file stm32f10x.h.

#define GPIO_IDR_IDR14 ((uint16_t)0x4000)

Port input data, bit 14

Definition at line 2460 of file stm32f10x.h.

#define GPIO_IDR_IDR15 ((uint16_t)0x8000)

Port input data, bit 15

Definition at line 2461 of file stm32f10x.h.

#define GPIO_IDR_IDR2 ((uint16_t)0x0004)

Port input data, bit 2

Definition at line 2448 of file stm32f10x.h.

#define GPIO_IDR_IDR3 ((uint16_t)0x0008)

Port input data, bit 3

Definition at line 2449 of file stm32f10x.h.

#define GPIO_IDR_IDR4 ((uint16_t)0x0010)

Port input data, bit 4

Definition at line 2450 of file stm32f10x.h.

#define GPIO_IDR_IDR5 ((uint16_t)0x0020)

Port input data, bit 5

Definition at line 2451 of file stm32f10x.h.

#define GPIO_IDR_IDR6 ((uint16_t)0x0040)

Port input data, bit 6

Definition at line 2452 of file stm32f10x.h.

#define GPIO_IDR_IDR7 ((uint16_t)0x0080)

Port input data, bit 7

Definition at line 2453 of file stm32f10x.h.

#define GPIO_IDR_IDR8 ((uint16_t)0x0100)

Port input data, bit 8

Definition at line 2454 of file stm32f10x.h.

#define GPIO_IDR_IDR9 ((uint16_t)0x0200)

Port input data, bit 9

Definition at line 2455 of file stm32f10x.h.

#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)

Port x Lock bit 0

Definition at line 2535 of file stm32f10x.h.

#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)

Port x Lock bit 1

Definition at line 2536 of file stm32f10x.h.

#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)

Port x Lock bit 10

Definition at line 2545 of file stm32f10x.h.

#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)

Port x Lock bit 11

Definition at line 2546 of file stm32f10x.h.

#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)

Port x Lock bit 12

Definition at line 2547 of file stm32f10x.h.

#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)

Port x Lock bit 13

Definition at line 2548 of file stm32f10x.h.

#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)

Port x Lock bit 14

Definition at line 2549 of file stm32f10x.h.

#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)

Port x Lock bit 15

Definition at line 2550 of file stm32f10x.h.

#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)

Port x Lock bit 2

Definition at line 2537 of file stm32f10x.h.

#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)

Port x Lock bit 3

Definition at line 2538 of file stm32f10x.h.

#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)

Port x Lock bit 4

Definition at line 2539 of file stm32f10x.h.

#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)

Port x Lock bit 5

Definition at line 2540 of file stm32f10x.h.

#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)

Port x Lock bit 6

Definition at line 2541 of file stm32f10x.h.

#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)

Port x Lock bit 7

Definition at line 2542 of file stm32f10x.h.

#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)

Port x Lock bit 8

Definition at line 2543 of file stm32f10x.h.

#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)

Port x Lock bit 9

Definition at line 2544 of file stm32f10x.h.

#define GPIO_LCKR_LCKK ((uint32_t)0x00010000)

Lock key

Definition at line 2551 of file stm32f10x.h.

#define GPIO_ODR_ODR0 ((uint16_t)0x0001)

Port output data, bit 0

Definition at line 2464 of file stm32f10x.h.

#define GPIO_ODR_ODR1 ((uint16_t)0x0002)

Port output data, bit 1

Definition at line 2465 of file stm32f10x.h.

#define GPIO_ODR_ODR10 ((uint16_t)0x0400)

Port output data, bit 10

Definition at line 2474 of file stm32f10x.h.

#define GPIO_ODR_ODR11 ((uint16_t)0x0800)

Port output data, bit 11

Definition at line 2475 of file stm32f10x.h.

#define GPIO_ODR_ODR12 ((uint16_t)0x1000)

Port output data, bit 12

Definition at line 2476 of file stm32f10x.h.

#define GPIO_ODR_ODR13 ((uint16_t)0x2000)

Port output data, bit 13

Definition at line 2477 of file stm32f10x.h.

#define GPIO_ODR_ODR14 ((uint16_t)0x4000)

Port output data, bit 14

Definition at line 2478 of file stm32f10x.h.

#define GPIO_ODR_ODR15 ((uint16_t)0x8000)

Port output data, bit 15

Definition at line 2479 of file stm32f10x.h.

#define GPIO_ODR_ODR2 ((uint16_t)0x0004)

Port output data, bit 2

Definition at line 2466 of file stm32f10x.h.

#define GPIO_ODR_ODR3 ((uint16_t)0x0008)

Port output data, bit 3

Definition at line 2467 of file stm32f10x.h.

#define GPIO_ODR_ODR4 ((uint16_t)0x0010)

Port output data, bit 4

Definition at line 2468 of file stm32f10x.h.

#define GPIO_ODR_ODR5 ((uint16_t)0x0020)

Port output data, bit 5

Definition at line 2469 of file stm32f10x.h.

#define GPIO_ODR_ODR6 ((uint16_t)0x0040)

Port output data, bit 6

Definition at line 2470 of file stm32f10x.h.

#define GPIO_ODR_ODR7 ((uint16_t)0x0080)

Port output data, bit 7

Definition at line 2471 of file stm32f10x.h.

#define GPIO_ODR_ODR8 ((uint16_t)0x0100)

Port output data, bit 8

Definition at line 2472 of file stm32f10x.h.

#define GPIO_ODR_ODR9 ((uint16_t)0x0200)

Port output data, bit 9

Definition at line 2473 of file stm32f10x.h.

#define I2C_CCR_CCR ((uint16_t)0x0FFF)

Clock Control Register in Fast/Standard mode (Master mode)

Definition at line 7632 of file stm32f10x.h.

#define I2C_CCR_DUTY ((uint16_t)0x4000)

Fast Mode Duty Cycle

Definition at line 7633 of file stm32f10x.h.

#define I2C_CCR_FS ((uint16_t)0x8000)

I2C Master Mode Selection

Definition at line 7634 of file stm32f10x.h.

#define I2C_CR1_ACK ((uint16_t)0x0400)

Acknowledge Enable

Definition at line 7560 of file stm32f10x.h.

#define I2C_CR1_ALERT ((uint16_t)0x2000)

SMBus Alert

Definition at line 7563 of file stm32f10x.h.

#define I2C_CR1_ENARP ((uint16_t)0x0010)

ARP Enable

Definition at line 7554 of file stm32f10x.h.

#define I2C_CR1_ENGC ((uint16_t)0x0040)

General Call Enable

Definition at line 7556 of file stm32f10x.h.

#define I2C_CR1_ENPEC ((uint16_t)0x0020)

PEC Enable

Definition at line 7555 of file stm32f10x.h.

#define I2C_CR1_NOSTRETCH ((uint16_t)0x0080)

Clock Stretching Disable (Slave mode)

Definition at line 7557 of file stm32f10x.h.

#define I2C_CR1_PE ((uint16_t)0x0001)

Peripheral Enable

Definition at line 7551 of file stm32f10x.h.

#define I2C_CR1_PEC ((uint16_t)0x1000)

Packet Error Checking

Definition at line 7562 of file stm32f10x.h.

#define I2C_CR1_POS ((uint16_t)0x0800)

Acknowledge/PEC Position (for data reception)

Definition at line 7561 of file stm32f10x.h.

#define I2C_CR1_SMBTYPE ((uint16_t)0x0008)

SMBus Type

Definition at line 7553 of file stm32f10x.h.

#define I2C_CR1_SMBUS ((uint16_t)0x0002)

SMBus Mode

Definition at line 7552 of file stm32f10x.h.

#define I2C_CR1_START ((uint16_t)0x0100)

Start Generation

Definition at line 7558 of file stm32f10x.h.

#define I2C_CR1_STOP ((uint16_t)0x0200)

Stop Generation

Definition at line 7559 of file stm32f10x.h.

Referenced by sEE_ReadBuffer().

#define I2C_CR1_SWRST ((uint16_t)0x8000)

Software Reset

Definition at line 7564 of file stm32f10x.h.

#define I2C_CR2_DMAEN ((uint16_t)0x0800)

DMA Requests Enable

Definition at line 7578 of file stm32f10x.h.

#define I2C_CR2_FREQ ((uint16_t)0x003F)

FREQ[5:0] bits (Peripheral Clock Frequency)

Definition at line 7567 of file stm32f10x.h.

#define I2C_CR2_FREQ_0 ((uint16_t)0x0001)

Bit 0

Definition at line 7568 of file stm32f10x.h.

#define I2C_CR2_FREQ_1 ((uint16_t)0x0002)

Bit 1

Definition at line 7569 of file stm32f10x.h.

#define I2C_CR2_FREQ_2 ((uint16_t)0x0004)

Bit 2

Definition at line 7570 of file stm32f10x.h.

#define I2C_CR2_FREQ_3 ((uint16_t)0x0008)

Bit 3

Definition at line 7571 of file stm32f10x.h.

#define I2C_CR2_FREQ_4 ((uint16_t)0x0010)

Bit 4

Definition at line 7572 of file stm32f10x.h.

#define I2C_CR2_FREQ_5 ((uint16_t)0x0020)

Bit 5

Definition at line 7573 of file stm32f10x.h.

#define I2C_CR2_ITBUFEN ((uint16_t)0x0400)

Buffer Interrupt Enable

Definition at line 7577 of file stm32f10x.h.

#define I2C_CR2_ITERREN ((uint16_t)0x0100)

Error Interrupt Enable

Definition at line 7575 of file stm32f10x.h.

#define I2C_CR2_ITEVTEN ((uint16_t)0x0200)

Event Interrupt Enable

Definition at line 7576 of file stm32f10x.h.

#define I2C_CR2_LAST ((uint16_t)0x1000)

DMA Last Transfer

Definition at line 7579 of file stm32f10x.h.

#define I2C_DR_DR ((uint8_t)0xFF)

8-bit Data Register

Definition at line 7603 of file stm32f10x.h.

#define I2C_OAR1_ADD0 ((uint16_t)0x0001)

Bit 0

Definition at line 7585 of file stm32f10x.h.

#define I2C_OAR1_ADD1 ((uint16_t)0x0002)

Bit 1

Definition at line 7586 of file stm32f10x.h.

#define I2C_OAR1_ADD1_7 ((uint16_t)0x00FE)

Interface Address

Definition at line 7582 of file stm32f10x.h.

#define I2C_OAR1_ADD2 ((uint16_t)0x0004)

Bit 2

Definition at line 7587 of file stm32f10x.h.

#define I2C_OAR1_ADD3 ((uint16_t)0x0008)

Bit 3

Definition at line 7588 of file stm32f10x.h.

#define I2C_OAR1_ADD4 ((uint16_t)0x0010)

Bit 4

Definition at line 7589 of file stm32f10x.h.

#define I2C_OAR1_ADD5 ((uint16_t)0x0020)

Bit 5

Definition at line 7590 of file stm32f10x.h.

#define I2C_OAR1_ADD6 ((uint16_t)0x0040)

Bit 6

Definition at line 7591 of file stm32f10x.h.

#define I2C_OAR1_ADD7 ((uint16_t)0x0080)

Bit 7

Definition at line 7592 of file stm32f10x.h.

#define I2C_OAR1_ADD8 ((uint16_t)0x0100)

Bit 8

Definition at line 7593 of file stm32f10x.h.

#define I2C_OAR1_ADD8_9 ((uint16_t)0x0300)

Interface Address

Definition at line 7583 of file stm32f10x.h.

#define I2C_OAR1_ADD9 ((uint16_t)0x0200)

Bit 9

Definition at line 7594 of file stm32f10x.h.

#define I2C_OAR1_ADDMODE ((uint16_t)0x8000)

Addressing Mode (Slave mode)

Definition at line 7596 of file stm32f10x.h.

#define I2C_OAR2_ADD2 ((uint8_t)0xFE)

Interface address

Definition at line 7600 of file stm32f10x.h.

#define I2C_OAR2_ENDUAL ((uint8_t)0x01)

Dual addressing mode enable

Definition at line 7599 of file stm32f10x.h.

#define I2C_SR1_ADD10 ((uint16_t)0x0008)

10-bit header sent (Master mode)

Definition at line 7609 of file stm32f10x.h.

#define I2C_SR1_ADDR ((uint16_t)0x0002)

Address sent (master mode)/matched (slave mode)

Definition at line 7607 of file stm32f10x.h.

Referenced by sEE_WaitEepromStandbyState().

#define I2C_SR1_AF ((uint16_t)0x0400)

Acknowledge Failure

Definition at line 7615 of file stm32f10x.h.

Referenced by sEE_WaitEepromStandbyState().

#define I2C_SR1_ARLO ((uint16_t)0x0200)

Arbitration Lost (master mode)

Definition at line 7614 of file stm32f10x.h.

#define I2C_SR1_BERR ((uint16_t)0x0100)

Bus Error

Definition at line 7613 of file stm32f10x.h.

#define I2C_SR1_BTF ((uint16_t)0x0004)

Byte Transfer Finished

Definition at line 7608 of file stm32f10x.h.

#define I2C_SR1_OVR ((uint16_t)0x0800)

Overrun/Underrun

Definition at line 7616 of file stm32f10x.h.

#define I2C_SR1_PECERR ((uint16_t)0x1000)

PEC Error in reception

Definition at line 7617 of file stm32f10x.h.

#define I2C_SR1_RXNE ((uint16_t)0x0040)

Data Register not Empty (receivers)

Definition at line 7611 of file stm32f10x.h.

#define I2C_SR1_SB ((uint16_t)0x0001)

Start Bit (Master mode)

Definition at line 7606 of file stm32f10x.h.

#define I2C_SR1_SMBALERT ((uint16_t)0x8000)

SMBus Alert

Definition at line 7619 of file stm32f10x.h.

#define I2C_SR1_STOPF ((uint16_t)0x0010)

Stop detection (Slave mode)

Definition at line 7610 of file stm32f10x.h.

#define I2C_SR1_TIMEOUT ((uint16_t)0x4000)

Timeout or Tlow Error

Definition at line 7618 of file stm32f10x.h.

#define I2C_SR1_TXE ((uint16_t)0x0080)

Data Register Empty (transmitters)

Definition at line 7612 of file stm32f10x.h.

#define I2C_SR2_BUSY ((uint16_t)0x0002)

Bus Busy

Definition at line 7623 of file stm32f10x.h.

#define I2C_SR2_DUALF ((uint16_t)0x0080)

Dual Flag (Slave mode)

Definition at line 7628 of file stm32f10x.h.

#define I2C_SR2_GENCALL ((uint16_t)0x0010)

General Call Address (Slave mode)

Definition at line 7625 of file stm32f10x.h.

#define I2C_SR2_MSL ((uint16_t)0x0001)

Master/Slave

Definition at line 7622 of file stm32f10x.h.

#define I2C_SR2_PEC ((uint16_t)0xFF00)

Packet Error Checking Register

Definition at line 7629 of file stm32f10x.h.

#define I2C_SR2_SMBDEFAULT ((uint16_t)0x0020)

SMBus Device Default Address (Slave mode)

Definition at line 7626 of file stm32f10x.h.

#define I2C_SR2_SMBHOST ((uint16_t)0x0040)

SMBus Host Header (Slave mode)

Definition at line 7627 of file stm32f10x.h.

#define I2C_SR2_TRA ((uint16_t)0x0004)

Transmitter/Receiver

Definition at line 7624 of file stm32f10x.h.

#define I2C_TRISE_TRISE ((uint8_t)0x3F)

Maximum Rise Time in Fast/Standard mode (Master mode)

Definition at line 7637 of file stm32f10x.h.

#define IWDG_KR_KEY ((uint16_t)0xFFFF)

Key value (write only, read 0000h)

Definition at line 4526 of file stm32f10x.h.

#define IWDG_PR_PR ((uint8_t)0x07)

PR[2:0] (Prescaler divider)

Definition at line 4529 of file stm32f10x.h.

#define IWDG_PR_PR_0 ((uint8_t)0x01)

Bit 0

Definition at line 4530 of file stm32f10x.h.

#define IWDG_PR_PR_1 ((uint8_t)0x02)

Bit 1

Definition at line 4531 of file stm32f10x.h.

#define IWDG_PR_PR_2 ((uint8_t)0x04)

Bit 2

Definition at line 4532 of file stm32f10x.h.

#define IWDG_RLR_RL ((uint16_t)0x0FFF)

Watchdog counter reload value

Definition at line 4535 of file stm32f10x.h.

#define IWDG_SR_PVU ((uint8_t)0x01)

Watchdog prescaler value update

Definition at line 4538 of file stm32f10x.h.

#define IWDG_SR_RVU ((uint8_t)0x02)

Watchdog counter reload value update

Definition at line 4539 of file stm32f10x.h.

#define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF)

Interrupt active flags

Definition at line 3052 of file stm32f10x.h.

#define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001)

bit 0

Definition at line 3053 of file stm32f10x.h.

#define NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002)

bit 1

Definition at line 3054 of file stm32f10x.h.

#define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400)

bit 10

Definition at line 3063 of file stm32f10x.h.

#define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800)

bit 11

Definition at line 3064 of file stm32f10x.h.

#define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000)

bit 12

Definition at line 3065 of file stm32f10x.h.

#define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000)

bit 13

Definition at line 3066 of file stm32f10x.h.

#define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000)

bit 14

Definition at line 3067 of file stm32f10x.h.

#define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000)

bit 15

Definition at line 3068 of file stm32f10x.h.

#define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000)

bit 16

Definition at line 3069 of file stm32f10x.h.

#define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000)

bit 17

Definition at line 3070 of file stm32f10x.h.

#define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000)

bit 18

Definition at line 3071 of file stm32f10x.h.

#define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000)

bit 19

Definition at line 3072 of file stm32f10x.h.

#define NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004)

bit 2

Definition at line 3055 of file stm32f10x.h.

#define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000)

bit 20

Definition at line 3073 of file stm32f10x.h.

#define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000)

bit 21

Definition at line 3074 of file stm32f10x.h.

#define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000)

bit 22

Definition at line 3075 of file stm32f10x.h.

#define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000)

bit 23

Definition at line 3076 of file stm32f10x.h.

#define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000)

bit 24

Definition at line 3077 of file stm32f10x.h.

#define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000)

bit 25

Definition at line 3078 of file stm32f10x.h.

#define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000)

bit 26

Definition at line 3079 of file stm32f10x.h.

#define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000)

bit 27

Definition at line 3080 of file stm32f10x.h.

#define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000)

bit 28

Definition at line 3081 of file stm32f10x.h.

#define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000)

bit 29

Definition at line 3082 of file stm32f10x.h.

#define NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008)

bit 3

Definition at line 3056 of file stm32f10x.h.

#define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000)

bit 30

Definition at line 3083 of file stm32f10x.h.

#define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000)

bit 31

Definition at line 3084 of file stm32f10x.h.

#define NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010)

bit 4

Definition at line 3057 of file stm32f10x.h.

#define NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020)

bit 5

Definition at line 3058 of file stm32f10x.h.

#define NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040)

bit 6

Definition at line 3059 of file stm32f10x.h.

#define NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080)

bit 7

Definition at line 3060 of file stm32f10x.h.

#define NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100)

bit 8

Definition at line 3061 of file stm32f10x.h.

#define NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200)

bit 9

Definition at line 3062 of file stm32f10x.h.

#define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF)

Interrupt clear-enable bits

Definition at line 2947 of file stm32f10x.h.

#define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001)

bit 0

Definition at line 2948 of file stm32f10x.h.

#define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002)

bit 1

Definition at line 2949 of file stm32f10x.h.

#define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400)

bit 10

Definition at line 2958 of file stm32f10x.h.

#define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800)

bit 11

Definition at line 2959 of file stm32f10x.h.

#define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000)

bit 12

Definition at line 2960 of file stm32f10x.h.

#define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000)

bit 13

Definition at line 2961 of file stm32f10x.h.

#define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000)

bit 14

Definition at line 2962 of file stm32f10x.h.

#define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000)

bit 15

Definition at line 2963 of file stm32f10x.h.

#define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000)

bit 16

Definition at line 2964 of file stm32f10x.h.

#define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000)

bit 17

Definition at line 2965 of file stm32f10x.h.

#define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000)

bit 18

Definition at line 2966 of file stm32f10x.h.

#define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000)

bit 19

Definition at line 2967 of file stm32f10x.h.

#define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004)

bit 2

Definition at line 2950 of file stm32f10x.h.

#define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000)

bit 20

Definition at line 2968 of file stm32f10x.h.

#define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000)

bit 21

Definition at line 2969 of file stm32f10x.h.

#define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000)

bit 22

Definition at line 2970 of file stm32f10x.h.

#define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000)

bit 23

Definition at line 2971 of file stm32f10x.h.

#define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000)

bit 24

Definition at line 2972 of file stm32f10x.h.

#define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000)

bit 25

Definition at line 2973 of file stm32f10x.h.

#define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000)

bit 26

Definition at line 2974 of file stm32f10x.h.

#define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000)

bit 27

Definition at line 2975 of file stm32f10x.h.

#define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000)

bit 28

Definition at line 2976 of file stm32f10x.h.

#define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000)

bit 29

Definition at line 2977 of file stm32f10x.h.

#define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008)

bit 3

Definition at line 2951 of file stm32f10x.h.

#define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000)

bit 30

Definition at line 2978 of file stm32f10x.h.

#define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000)

bit 31

Definition at line 2979 of file stm32f10x.h.

#define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010)

bit 4

Definition at line 2952 of file stm32f10x.h.

#define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020)

bit 5

Definition at line 2953 of file stm32f10x.h.

#define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040)

bit 6

Definition at line 2954 of file stm32f10x.h.

#define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080)

bit 7

Definition at line 2955 of file stm32f10x.h.

#define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100)

bit 8

Definition at line 2956 of file stm32f10x.h.

#define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200)

bit 9

Definition at line 2957 of file stm32f10x.h.

#define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF)

Interrupt clear-pending bits

Definition at line 3017 of file stm32f10x.h.

#define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001)

bit 0

Definition at line 3018 of file stm32f10x.h.

#define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002)

bit 1

Definition at line 3019 of file stm32f10x.h.

#define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400)

bit 10

Definition at line 3028 of file stm32f10x.h.

#define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800)

bit 11

Definition at line 3029 of file stm32f10x.h.

#define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000)

bit 12

Definition at line 3030 of file stm32f10x.h.

#define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000)

bit 13

Definition at line 3031 of file stm32f10x.h.

#define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000)

bit 14

Definition at line 3032 of file stm32f10x.h.

#define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000)

bit 15

Definition at line 3033 of file stm32f10x.h.

#define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000)

bit 16

Definition at line 3034 of file stm32f10x.h.

#define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000)

bit 17

Definition at line 3035 of file stm32f10x.h.

#define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000)

bit 18

Definition at line 3036 of file stm32f10x.h.

#define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000)

bit 19

Definition at line 3037 of file stm32f10x.h.

#define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004)

bit 2

Definition at line 3020 of file stm32f10x.h.

#define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000)

bit 20

Definition at line 3038 of file stm32f10x.h.

#define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000)

bit 21

Definition at line 3039 of file stm32f10x.h.

#define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000)

bit 22

Definition at line 3040 of file stm32f10x.h.

#define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000)

bit 23

Definition at line 3041 of file stm32f10x.h.

#define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000)

bit 24

Definition at line 3042 of file stm32f10x.h.

#define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000)

bit 25

Definition at line 3043 of file stm32f10x.h.

#define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000)

bit 26

Definition at line 3044 of file stm32f10x.h.

#define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000)

bit 27

Definition at line 3045 of file stm32f10x.h.

#define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000)

bit 28

Definition at line 3046 of file stm32f10x.h.

#define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000)

bit 29

Definition at line 3047 of file stm32f10x.h.

#define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008)

bit 3

Definition at line 3021 of file stm32f10x.h.

#define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000)

bit 30

Definition at line 3048 of file stm32f10x.h.

#define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000)

bit 31

Definition at line 3049 of file stm32f10x.h.

#define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010)

bit 4

Definition at line 3022 of file stm32f10x.h.

#define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020)

bit 5

Definition at line 3023 of file stm32f10x.h.

#define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040)

bit 6

Definition at line 3024 of file stm32f10x.h.

#define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080)

bit 7

Definition at line 3025 of file stm32f10x.h.

#define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100)

bit 8

Definition at line 3026 of file stm32f10x.h.

#define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200)

bit 9

Definition at line 3027 of file stm32f10x.h.

#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF)

Priority of interrupt 0

Definition at line 3087 of file stm32f10x.h.

#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00)

Priority of interrupt 1

Definition at line 3088 of file stm32f10x.h.

#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000)

Priority of interrupt 2

Definition at line 3089 of file stm32f10x.h.

#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000)

Priority of interrupt 3

Definition at line 3090 of file stm32f10x.h.

#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF)

Priority of interrupt 4

Definition at line 3093 of file stm32f10x.h.

#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00)

Priority of interrupt 5

Definition at line 3094 of file stm32f10x.h.

#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000)

Priority of interrupt 6

Definition at line 3095 of file stm32f10x.h.

#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000)

Priority of interrupt 7

Definition at line 3096 of file stm32f10x.h.

#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000)

Priority of interrupt 10

Definition at line 3101 of file stm32f10x.h.

#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000)

Priority of interrupt 11

Definition at line 3102 of file stm32f10x.h.

#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF)

Priority of interrupt 8

Definition at line 3099 of file stm32f10x.h.

#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00)

Priority of interrupt 9

Definition at line 3100 of file stm32f10x.h.

#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF)

Priority of interrupt 12

Definition at line 3105 of file stm32f10x.h.

#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00)

Priority of interrupt 13

Definition at line 3106 of file stm32f10x.h.

#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000)

Priority of interrupt 14

Definition at line 3107 of file stm32f10x.h.

#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000)

Priority of interrupt 15

Definition at line 3108 of file stm32f10x.h.

#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF)

Priority of interrupt 16

Definition at line 3111 of file stm32f10x.h.

#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00)

Priority of interrupt 17

Definition at line 3112 of file stm32f10x.h.

#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000)

Priority of interrupt 18

Definition at line 3113 of file stm32f10x.h.

#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000)

Priority of interrupt 19

Definition at line 3114 of file stm32f10x.h.

#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF)

Priority of interrupt 20

Definition at line 3117 of file stm32f10x.h.

#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00)

Priority of interrupt 21

Definition at line 3118 of file stm32f10x.h.

#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000)

Priority of interrupt 22

Definition at line 3119 of file stm32f10x.h.

#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000)

Priority of interrupt 23

Definition at line 3120 of file stm32f10x.h.

#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF)

Priority of interrupt 24

Definition at line 3123 of file stm32f10x.h.

#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00)

Priority of interrupt 25

Definition at line 3124 of file stm32f10x.h.

#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000)

Priority of interrupt 26

Definition at line 3125 of file stm32f10x.h.

#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000)

Priority of interrupt 27

Definition at line 3126 of file stm32f10x.h.

#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF)

Priority of interrupt 28

Definition at line 3129 of file stm32f10x.h.

#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00)

Priority of interrupt 29

Definition at line 3130 of file stm32f10x.h.

#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000)

Priority of interrupt 30

Definition at line 3131 of file stm32f10x.h.

#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000)

Priority of interrupt 31

Definition at line 3132 of file stm32f10x.h.

#define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF)

Interrupt set enable bits

Definition at line 2912 of file stm32f10x.h.

#define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001)

bit 0

Definition at line 2913 of file stm32f10x.h.

#define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002)

bit 1

Definition at line 2914 of file stm32f10x.h.

#define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400)

bit 10

Definition at line 2923 of file stm32f10x.h.

#define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800)

bit 11

Definition at line 2924 of file stm32f10x.h.

#define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000)

bit 12

Definition at line 2925 of file stm32f10x.h.

#define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000)

bit 13

Definition at line 2926 of file stm32f10x.h.

#define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000)

bit 14

Definition at line 2927 of file stm32f10x.h.

#define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000)

bit 15

Definition at line 2928 of file stm32f10x.h.

#define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000)

bit 16

Definition at line 2929 of file stm32f10x.h.

#define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000)

bit 17

Definition at line 2930 of file stm32f10x.h.

#define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000)

bit 18

Definition at line 2931 of file stm32f10x.h.

#define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000)

bit 19

Definition at line 2932 of file stm32f10x.h.

#define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004)

bit 2

Definition at line 2915 of file stm32f10x.h.

#define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000)

bit 20

Definition at line 2933 of file stm32f10x.h.

#define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000)

bit 21

Definition at line 2934 of file stm32f10x.h.

#define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000)

bit 22

Definition at line 2935 of file stm32f10x.h.

#define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000)

bit 23

Definition at line 2936 of file stm32f10x.h.

#define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000)

bit 24

Definition at line 2937 of file stm32f10x.h.

#define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000)

bit 25

Definition at line 2938 of file stm32f10x.h.

#define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000)

bit 26

Definition at line 2939 of file stm32f10x.h.

#define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000)

bit 27

Definition at line 2940 of file stm32f10x.h.

#define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000)

bit 28

Definition at line 2941 of file stm32f10x.h.

#define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000)

bit 29

Definition at line 2942 of file stm32f10x.h.

#define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008)

bit 3

Definition at line 2916 of file stm32f10x.h.

#define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000)

bit 30

Definition at line 2943 of file stm32f10x.h.

#define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000)

bit 31

Definition at line 2944 of file stm32f10x.h.

#define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010)

bit 4

Definition at line 2917 of file stm32f10x.h.

#define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020)

bit 5

Definition at line 2918 of file stm32f10x.h.

#define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040)

bit 6

Definition at line 2919 of file stm32f10x.h.

#define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080)

bit 7

Definition at line 2920 of file stm32f10x.h.

#define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100)

bit 8

Definition at line 2921 of file stm32f10x.h.

#define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200)

bit 9

Definition at line 2922 of file stm32f10x.h.

#define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF)

Interrupt set-pending bits

Definition at line 2982 of file stm32f10x.h.

#define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001)

bit 0

Definition at line 2983 of file stm32f10x.h.

#define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002)

bit 1

Definition at line 2984 of file stm32f10x.h.

#define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400)

bit 10

Definition at line 2993 of file stm32f10x.h.

#define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800)

bit 11

Definition at line 2994 of file stm32f10x.h.

#define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000)

bit 12

Definition at line 2995 of file stm32f10x.h.

#define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000)

bit 13

Definition at line 2996 of file stm32f10x.h.

#define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000)

bit 14

Definition at line 2997 of file stm32f10x.h.

#define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000)

bit 15

Definition at line 2998 of file stm32f10x.h.

#define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000)

bit 16

Definition at line 2999 of file stm32f10x.h.

#define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000)

bit 17

Definition at line 3000 of file stm32f10x.h.

#define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000)

bit 18

Definition at line 3001 of file stm32f10x.h.

#define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000)

bit 19

Definition at line 3002 of file stm32f10x.h.

#define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004)

bit 2

Definition at line 2985 of file stm32f10x.h.

#define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000)

bit 20

Definition at line 3003 of file stm32f10x.h.

#define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000)

bit 21

Definition at line 3004 of file stm32f10x.h.

#define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000)

bit 22

Definition at line 3005 of file stm32f10x.h.

#define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000)

bit 23

Definition at line 3006 of file stm32f10x.h.

#define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000)

bit 24

Definition at line 3007 of file stm32f10x.h.

#define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000)

bit 25

Definition at line 3008 of file stm32f10x.h.

#define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000)

bit 26

Definition at line 3009 of file stm32f10x.h.

#define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000)

bit 27

Definition at line 3010 of file stm32f10x.h.

#define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000)

bit 28

Definition at line 3011 of file stm32f10x.h.

#define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000)

bit 29

Definition at line 3012 of file stm32f10x.h.

#define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008)

bit 3

Definition at line 2986 of file stm32f10x.h.

#define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000)

bit 30

Definition at line 3013 of file stm32f10x.h.

#define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000)

bit 31

Definition at line 3014 of file stm32f10x.h.

#define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010)

bit 4

Definition at line 2987 of file stm32f10x.h.

#define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020)

bit 5

Definition at line 2988 of file stm32f10x.h.

#define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040)

bit 6

Definition at line 2989 of file stm32f10x.h.

#define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080)

bit 7

Definition at line 2990 of file stm32f10x.h.

#define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100)

bit 8

Definition at line 2991 of file stm32f10x.h.

#define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200)

bit 9

Definition at line 2992 of file stm32f10x.h.

#define PWR_CR_CSBF ((uint16_t)0x0008)

Clear Standby Flag

Definition at line 1498 of file stm32f10x.h.

#define PWR_CR_CWUF ((uint16_t)0x0004)

Clear Wakeup Flag

Definition at line 1497 of file stm32f10x.h.

Referenced by PWR_EnterSTANDBYMode().

#define PWR_CR_DBP ((uint16_t)0x0100)

Disable Backup Domain write protection

Definition at line 1516 of file stm32f10x.h.

#define PWR_CR_LPDS ((uint16_t)0x0001)

Low-Power Deepsleep

Definition at line 1495 of file stm32f10x.h.

#define PWR_CR_PDDS ((uint16_t)0x0002)

Power Down Deepsleep

Definition at line 1496 of file stm32f10x.h.

Referenced by PWR_EnterSTANDBYMode().

#define PWR_CR_PLS ((uint16_t)0x00E0)

PLS[2:0] bits (PVD Level Selection)

Definition at line 1501 of file stm32f10x.h.

#define PWR_CR_PLS_0 ((uint16_t)0x0020)

Bit 0

Definition at line 1502 of file stm32f10x.h.

#define PWR_CR_PLS_1 ((uint16_t)0x0040)

Bit 1

Definition at line 1503 of file stm32f10x.h.

#define PWR_CR_PLS_2 ((uint16_t)0x0080)

Bit 2 PVD level configuration

Definition at line 1504 of file stm32f10x.h.

#define PWR_CR_PLS_2V2 ((uint16_t)0x0000)

PVD level 2.2V

Definition at line 1507 of file stm32f10x.h.

#define PWR_CR_PLS_2V3 ((uint16_t)0x0020)

PVD level 2.3V

Definition at line 1508 of file stm32f10x.h.

#define PWR_CR_PLS_2V4 ((uint16_t)0x0040)

PVD level 2.4V

Definition at line 1509 of file stm32f10x.h.

#define PWR_CR_PLS_2V5 ((uint16_t)0x0060)

PVD level 2.5V

Definition at line 1510 of file stm32f10x.h.

#define PWR_CR_PLS_2V6 ((uint16_t)0x0080)

PVD level 2.6V

Definition at line 1511 of file stm32f10x.h.

#define PWR_CR_PLS_2V7 ((uint16_t)0x00A0)

PVD level 2.7V

Definition at line 1512 of file stm32f10x.h.

#define PWR_CR_PLS_2V8 ((uint16_t)0x00C0)

PVD level 2.8V

Definition at line 1513 of file stm32f10x.h.

#define PWR_CR_PLS_2V9 ((uint16_t)0x00E0)

PVD level 2.9V

Definition at line 1514 of file stm32f10x.h.

#define PWR_CR_PVDE ((uint16_t)0x0010)

Power Voltage Detector Enable

Definition at line 1499 of file stm32f10x.h.

#define PWR_CSR_EWUP ((uint16_t)0x0100)

Enable WKUP pin

Definition at line 1523 of file stm32f10x.h.

#define PWR_CSR_PVDO ((uint16_t)0x0004)

PVD Output

Definition at line 1522 of file stm32f10x.h.

#define PWR_CSR_SBF ((uint16_t)0x0002)

Standby Flag

Definition at line 1521 of file stm32f10x.h.

#define PWR_CSR_WUF ((uint16_t)0x0001)

Wakeup Flag

Definition at line 1520 of file stm32f10x.h.

#define RCC_AHBENR_CRCEN ((uint16_t)0x0040)

CRC clock enable

Definition at line 2022 of file stm32f10x.h.

#define RCC_AHBENR_DMA1EN ((uint16_t)0x0001)

DMA1 clock enable

Definition at line 2019 of file stm32f10x.h.

#define RCC_AHBENR_FLITFEN ((uint16_t)0x0010)

FLITF clock enable

Definition at line 2021 of file stm32f10x.h.

#define RCC_AHBENR_SRAMEN ((uint16_t)0x0004)

SRAM interface clock enable

Definition at line 2020 of file stm32f10x.h.

#define RCC_APB1ENR_BKPEN ((uint32_t)0x08000000)

Backup interface clock enable

Definition at line 2099 of file stm32f10x.h.

#define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000)

CAN1 clock enable

Definition at line 2096 of file stm32f10x.h.

#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000)

I2C 1 clock enable

Definition at line 2093 of file stm32f10x.h.

#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000)

I2C 2 clock enable

Definition at line 2106 of file stm32f10x.h.

#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000)

Power interface clock enable

Definition at line 2100 of file stm32f10x.h.

#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000)

SPI 2 clock enable

Definition at line 2104 of file stm32f10x.h.

#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001)

Timer 2 clock enabled

Definition at line 2089 of file stm32f10x.h.

#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002)

Timer 3 clock enable

Definition at line 2090 of file stm32f10x.h.

#define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004)

Timer 4 clock enable

Definition at line 2103 of file stm32f10x.h.

#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000)

USART 2 clock enable

Definition at line 2092 of file stm32f10x.h.

#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000)

USART 3 clock enable

Definition at line 2105 of file stm32f10x.h.

#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800)

Window Watchdog clock enable

Definition at line 2091 of file stm32f10x.h.

#define RCC_APB1RSTR_BKPRST ((uint32_t)0x08000000)

Backup interface reset

Definition at line 1967 of file stm32f10x.h.

#define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000)

CAN1 reset

Definition at line 1964 of file stm32f10x.h.

#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000)

I2C 1 reset

Definition at line 1961 of file stm32f10x.h.

#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000)

I2C 2 reset

Definition at line 1974 of file stm32f10x.h.

#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000)

Power interface reset

Definition at line 1968 of file stm32f10x.h.

#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000)

SPI 2 reset

Definition at line 1972 of file stm32f10x.h.

#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001)

Timer 2 reset

Definition at line 1957 of file stm32f10x.h.

#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002)

Timer 3 reset

Definition at line 1958 of file stm32f10x.h.

#define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004)

Timer 4 reset

Definition at line 1971 of file stm32f10x.h.

#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000)

USART 2 reset

Definition at line 1960 of file stm32f10x.h.

#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000)

USART 3 reset

Definition at line 1973 of file stm32f10x.h.

#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800)

Window Watchdog reset

Definition at line 1959 of file stm32f10x.h.

#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200)

ADC 1 interface clock enable

Definition at line 2050 of file stm32f10x.h.

#define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000400)

ADC 2 interface clock enable

Definition at line 2053 of file stm32f10x.h.

#define RCC_APB2ENR_AFIOEN ((uint32_t)0x00000001)

Alternate Function I/O clock enable

Definition at line 2045 of file stm32f10x.h.

#define RCC_APB2ENR_IOPAEN ((uint32_t)0x00000004)

I/O port A clock enable

Definition at line 2046 of file stm32f10x.h.

#define RCC_APB2ENR_IOPBEN ((uint32_t)0x00000008)

I/O port B clock enable

Definition at line 2047 of file stm32f10x.h.

#define RCC_APB2ENR_IOPCEN ((uint32_t)0x00000010)

I/O port C clock enable

Definition at line 2048 of file stm32f10x.h.

#define RCC_APB2ENR_IOPDEN ((uint32_t)0x00000020)

I/O port D clock enable

Definition at line 2049 of file stm32f10x.h.

#define RCC_APB2ENR_IOPEEN ((uint32_t)0x00000040)

I/O port E clock enable

Definition at line 2067 of file stm32f10x.h.

#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000)

SPI 1 clock enable

Definition at line 2057 of file stm32f10x.h.

#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800)

TIM1 Timer clock enable

Definition at line 2056 of file stm32f10x.h.

#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000)

USART1 clock enable

Definition at line 2058 of file stm32f10x.h.

#define RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200)

ADC 1 interface reset

Definition at line 1918 of file stm32f10x.h.

#define RCC_APB2RSTR_ADC2RST ((uint32_t)0x00000400)

ADC 2 interface reset

Definition at line 1921 of file stm32f10x.h.

#define RCC_APB2RSTR_AFIORST ((uint32_t)0x00000001)

Alternate Function I/O reset

Definition at line 1913 of file stm32f10x.h.

#define RCC_APB2RSTR_IOPARST ((uint32_t)0x00000004)

I/O port A reset

Definition at line 1914 of file stm32f10x.h.

#define RCC_APB2RSTR_IOPBRST ((uint32_t)0x00000008)

I/O port B reset

Definition at line 1915 of file stm32f10x.h.

#define RCC_APB2RSTR_IOPCRST ((uint32_t)0x00000010)

I/O port C reset

Definition at line 1916 of file stm32f10x.h.

#define RCC_APB2RSTR_IOPDRST ((uint32_t)0x00000020)

I/O port D reset

Definition at line 1917 of file stm32f10x.h.

#define RCC_APB2RSTR_IOPERST ((uint32_t)0x00000040)

I/O port E reset

Definition at line 1935 of file stm32f10x.h.

#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000)

SPI 1 reset

Definition at line 1925 of file stm32f10x.h.

#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800)

TIM1 Timer reset

Definition at line 1924 of file stm32f10x.h.

#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000)

USART1 reset

Definition at line 1926 of file stm32f10x.h.

#define RCC_BDCR_BDRST ((uint32_t)0x00010000)

Backup domain software reset

Definition at line 2166 of file stm32f10x.h.

#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004)

External Low Speed oscillator Bypass

Definition at line 2153 of file stm32f10x.h.

#define RCC_BDCR_LSEON ((uint32_t)0x00000001)

External Low Speed oscillator enable

Definition at line 2151 of file stm32f10x.h.

#define RCC_BDCR_LSERDY ((uint32_t)0x00000002)

External Low Speed oscillator Ready

Definition at line 2152 of file stm32f10x.h.

#define RCC_BDCR_RTCEN ((uint32_t)0x00008000)

RTC clock enable

Definition at line 2165 of file stm32f10x.h.

#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300)

RTCSEL[1:0] bits (RTC clock source selection)

Definition at line 2155 of file stm32f10x.h.

#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100)

Bit 0

Definition at line 2156 of file stm32f10x.h.

#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200)

Bit 1 RTC congiguration

Definition at line 2157 of file stm32f10x.h.

#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300)

HSE oscillator clock divided by 128 used as RTC clock

Definition at line 2163 of file stm32f10x.h.

#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100)

LSE oscillator clock used as RTC clock

Definition at line 2161 of file stm32f10x.h.

#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200)

LSI oscillator clock used as RTC clock

Definition at line 2162 of file stm32f10x.h.

#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000)

No clock

Definition at line 2160 of file stm32f10x.h.

#define RCC_CFGR_ADCPRE ((uint32_t)0x0000C000)

ADCPRE[1:0] bits (ADC prescaler)

Definition at line 1760 of file stm32f10x.h.

#define RCC_CFGR_ADCPRE_0 ((uint32_t)0x00004000)

Bit 0

Definition at line 1761 of file stm32f10x.h.

#define RCC_CFGR_ADCPRE_1 ((uint32_t)0x00008000)

Bit 1

Definition at line 1762 of file stm32f10x.h.

#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000)

PCLK2 divided by 2

Definition at line 1764 of file stm32f10x.h.

#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000)

PCLK2 divided by 4

Definition at line 1765 of file stm32f10x.h.

#define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000)

PCLK2 divided by 6

Definition at line 1766 of file stm32f10x.h.

#define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000)

PCLK2 divided by 8

Definition at line 1767 of file stm32f10x.h.

#define RCC_CFGR_HPRE ((uint32_t)0x000000F0)

HPRE[3:0] bits (AHB prescaler)

Definition at line 1719 of file stm32f10x.h.

Referenced by SystemCoreClockUpdate().

#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010)

Bit 0

Definition at line 1720 of file stm32f10x.h.

#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020)

Bit 1

Definition at line 1721 of file stm32f10x.h.

#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040)

Bit 2

Definition at line 1722 of file stm32f10x.h.

#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080)

Bit 3

Definition at line 1723 of file stm32f10x.h.

#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000)

SYSCLK not divided

Definition at line 1725 of file stm32f10x.h.

Referenced by SetSysClockTo56(), and SetSysClockTo72().

#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0)

SYSCLK divided by 128

Definition at line 1731 of file stm32f10x.h.

#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0)

SYSCLK divided by 16

Definition at line 1729 of file stm32f10x.h.

#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080)

SYSCLK divided by 2

Definition at line 1726 of file stm32f10x.h.

#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0)

SYSCLK divided by 256

Definition at line 1732 of file stm32f10x.h.

#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090)

SYSCLK divided by 4

Definition at line 1727 of file stm32f10x.h.

#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0)

SYSCLK divided by 512 PPRE1 configuration

Definition at line 1733 of file stm32f10x.h.

#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0)

SYSCLK divided by 64

Definition at line 1730 of file stm32f10x.h.

#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0)

SYSCLK divided by 8

Definition at line 1728 of file stm32f10x.h.

#define RCC_CFGR_MCO ((uint32_t)0x07000000)

MCO[2:0] bits (Microcontroller Clock Output)

Definition at line 1872 of file stm32f10x.h.

#define RCC_CFGR_MCO_0 ((uint32_t)0x01000000)

Bit 0

Definition at line 1873 of file stm32f10x.h.

#define RCC_CFGR_MCO_1 ((uint32_t)0x02000000)

Bit 1

Definition at line 1874 of file stm32f10x.h.

#define RCC_CFGR_MCO_2 ((uint32_t)0x04000000)

Bit 2

Definition at line 1875 of file stm32f10x.h.

#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000)

HSE clock selected as MCO source

Definition at line 1880 of file stm32f10x.h.

#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000)

HSI clock selected as MCO source

Definition at line 1879 of file stm32f10x.h.

#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000)

No clock

Definition at line 1877 of file stm32f10x.h.

#define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000)

PLL clock divided by 2 selected as MCO source

Definition at line 1881 of file stm32f10x.h.

#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000)

System clock selected as MCO source

Definition at line 1878 of file stm32f10x.h.

#define RCC_CFGR_PLLMULL ((uint32_t)0x003C0000)

PLLMUL[3:0] bits (PLL multiplication factor)

Definition at line 1774 of file stm32f10x.h.

Referenced by SetSysClockTo56(), SetSysClockTo72(), and SystemCoreClockUpdate().

#define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000)

PLL input clock10

Definition at line 1862 of file stm32f10x.h.

#define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000)

PLL input clock*11

Definition at line 1863 of file stm32f10x.h.

#define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000)

PLL input clock*12

Definition at line 1864 of file stm32f10x.h.

#define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000)

PLL input clock*13

Definition at line 1865 of file stm32f10x.h.

#define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000)

PLL input clock*14

Definition at line 1866 of file stm32f10x.h.

#define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000)

PLL input clock*15

Definition at line 1867 of file stm32f10x.h.

#define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000)

PLL input clock*16

Definition at line 1868 of file stm32f10x.h.

#define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000)

PLL input clock*2

Definition at line 1854 of file stm32f10x.h.

#define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000)

PLL input clock*3

Definition at line 1855 of file stm32f10x.h.

#define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000)

PLL input clock*4

Definition at line 1856 of file stm32f10x.h.

#define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000)

PLL input clock*5

Definition at line 1857 of file stm32f10x.h.

#define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000)

PLL input clock*6

Definition at line 1858 of file stm32f10x.h.

#define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000)

PLL input clock*7

Definition at line 1859 of file stm32f10x.h.

Referenced by SetSysClockTo56().

#define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000)

PLL input clock*8

Definition at line 1860 of file stm32f10x.h.

#define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000)

PLL input clock*9

Definition at line 1861 of file stm32f10x.h.

Referenced by SetSysClockTo72().

#define RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000)

Bit 0

Definition at line 1775 of file stm32f10x.h.

#define RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000)

Bit 1

Definition at line 1776 of file stm32f10x.h.

#define RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000)

Bit 2

Definition at line 1777 of file stm32f10x.h.

#define RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000)

Bit 3

Definition at line 1778 of file stm32f10x.h.

#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000)

PLL entry clock source

Definition at line 1769 of file stm32f10x.h.

Referenced by SetSysClockTo56(), SetSysClockTo72(), and SystemCoreClockUpdate().

#define RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000)

HSE clock selected as PLL entry clock source

Definition at line 1849 of file stm32f10x.h.

Referenced by SetSysClockTo56(), and SetSysClockTo72().

#define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000)

HSI clock divided by 2 selected as PLL entry clock source

Definition at line 1848 of file stm32f10x.h.

#define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000)

HSE divider for PLL entry PLLMUL configuration

Definition at line 1771 of file stm32f10x.h.

Referenced by SetSysClockTo56(), SetSysClockTo72(), and SystemCoreClockUpdate().

#define RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000)

HSE clock not divided for PLL entry

Definition at line 1851 of file stm32f10x.h.

#define RCC_CFGR_PLLXTPRE_HSE_Div2 ((uint32_t)0x00020000)

HSE clock divided by 2 for PLL entry

Definition at line 1852 of file stm32f10x.h.

#define RCC_CFGR_PPRE1 ((uint32_t)0x00000700)

PRE1[2:0] bits (APB1 prescaler)

Definition at line 1736 of file stm32f10x.h.

#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100)

Bit 0

Definition at line 1737 of file stm32f10x.h.

#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200)

Bit 1

Definition at line 1738 of file stm32f10x.h.

#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400)

Bit 2

Definition at line 1739 of file stm32f10x.h.

#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000)

HCLK not divided

Definition at line 1741 of file stm32f10x.h.

#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700)

HCLK divided by 16 PPRE2 configuration

Definition at line 1745 of file stm32f10x.h.

#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400)

HCLK divided by 2

Definition at line 1742 of file stm32f10x.h.

Referenced by SetSysClockTo56(), and SetSysClockTo72().

#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500)

HCLK divided by 4

Definition at line 1743 of file stm32f10x.h.

#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600)

HCLK divided by 8

Definition at line 1744 of file stm32f10x.h.

#define RCC_CFGR_PPRE2 ((uint32_t)0x00003800)

PRE2[2:0] bits (APB2 prescaler)

Definition at line 1748 of file stm32f10x.h.

#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800)

Bit 0

Definition at line 1749 of file stm32f10x.h.

#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000)

Bit 1

Definition at line 1750 of file stm32f10x.h.

#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000)

Bit 2

Definition at line 1751 of file stm32f10x.h.

#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000)

HCLK not divided

Definition at line 1753 of file stm32f10x.h.

Referenced by SetSysClockTo56(), and SetSysClockTo72().

#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800)

HCLK divided by 16 ADCPPRE configuration

Definition at line 1757 of file stm32f10x.h.

#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000)

HCLK divided by 2

Definition at line 1754 of file stm32f10x.h.

#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800)

HCLK divided by 4

Definition at line 1755 of file stm32f10x.h.

#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000)

HCLK divided by 8

Definition at line 1756 of file stm32f10x.h.

#define RCC_CFGR_SW ((uint32_t)0x00000003)

< SW configuration SW[1:0] bits (System clock Switch)

Definition at line 1701 of file stm32f10x.h.

Referenced by SetSysClockTo56(), and SetSysClockTo72().

#define RCC_CFGR_SW_0 ((uint32_t)0x00000001)

Bit 0

Definition at line 1702 of file stm32f10x.h.

#define RCC_CFGR_SW_1 ((uint32_t)0x00000002)

Bit 1

Definition at line 1703 of file stm32f10x.h.

#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001)

HSE selected as system clock

Definition at line 1706 of file stm32f10x.h.

#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000)

HSI selected as system clock

Definition at line 1705 of file stm32f10x.h.

#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002)

PLL selected as system clock SWS configuration

Definition at line 1707 of file stm32f10x.h.

Referenced by SetSysClockTo56(), and SetSysClockTo72().

#define RCC_CFGR_SWS ((uint32_t)0x0000000C)

SWS[1:0] bits (System Clock Switch Status)

Definition at line 1710 of file stm32f10x.h.

Referenced by SetSysClockTo56(), SetSysClockTo72(), and SystemCoreClockUpdate().

#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004)

Bit 0

Definition at line 1711 of file stm32f10x.h.

#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008)

Bit 1

Definition at line 1712 of file stm32f10x.h.

#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004)

HSE oscillator used as system clock

Definition at line 1715 of file stm32f10x.h.

#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000)

HSI oscillator used as system clock

Definition at line 1714 of file stm32f10x.h.

#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008)

PLL used as system clock HPRE configuration

Definition at line 1716 of file stm32f10x.h.

#define RCC_CFGR_USBPRE ((uint32_t)0x00400000)

USB Device prescaler MCO configuration

Definition at line 1869 of file stm32f10x.h.

#define RCC_CIR_CSSC ((uint32_t)0x00800000)

Clock Security System Interrupt Clear

Definition at line 1901 of file stm32f10x.h.

#define RCC_CIR_CSSF ((uint32_t)0x00000080)

Clock Security System Interrupt flag

Definition at line 1890 of file stm32f10x.h.

#define RCC_CIR_HSERDYC ((uint32_t)0x00080000)

HSE Ready Interrupt Clear

Definition at line 1899 of file stm32f10x.h.

#define RCC_CIR_HSERDYF ((uint32_t)0x00000008)

HSE Ready Interrupt flag

Definition at line 1888 of file stm32f10x.h.

#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800)

HSE Ready Interrupt Enable

Definition at line 1894 of file stm32f10x.h.

#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000)

HSI Ready Interrupt Clear

Definition at line 1898 of file stm32f10x.h.

#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004)

HSI Ready Interrupt flag

Definition at line 1887 of file stm32f10x.h.

#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400)

HSI Ready Interrupt Enable

Definition at line 1893 of file stm32f10x.h.

#define RCC_CIR_LSERDYC ((uint32_t)0x00020000)

LSE Ready Interrupt Clear

Definition at line 1897 of file stm32f10x.h.

#define RCC_CIR_LSERDYF ((uint32_t)0x00000002)

LSE Ready Interrupt flag

Definition at line 1886 of file stm32f10x.h.

#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200)

LSE Ready Interrupt Enable

Definition at line 1892 of file stm32f10x.h.

#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000)

LSI Ready Interrupt Clear

Definition at line 1896 of file stm32f10x.h.

#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001)

<****************** Bit definition for RCC_CIR register LSI Ready Interrupt flag

Definition at line 1885 of file stm32f10x.h.

#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100)

LSI Ready Interrupt Enable

Definition at line 1891 of file stm32f10x.h.

#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000)

PLL Ready Interrupt Clear

Definition at line 1900 of file stm32f10x.h.

#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010)

PLL Ready Interrupt flag

Definition at line 1889 of file stm32f10x.h.

#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000)

PLL Ready Interrupt Enable

Definition at line 1895 of file stm32f10x.h.

#define RCC_CR_CSSON ((uint32_t)0x00080000)

Clock Security System enable

Definition at line 1688 of file stm32f10x.h.

#define RCC_CR_HSEBYP ((uint32_t)0x00040000)

External High Speed clock Bypass

Definition at line 1687 of file stm32f10x.h.

#define RCC_CR_HSEON ((uint32_t)0x00010000)

External High Speed clock enable

Definition at line 1685 of file stm32f10x.h.

Referenced by SetSysClockTo56(), and SetSysClockTo72().

#define RCC_CR_HSERDY ((uint32_t)0x00020000)

External High Speed clock ready flag

Definition at line 1686 of file stm32f10x.h.

Referenced by SetSysClockTo56(), and SetSysClockTo72().

#define RCC_CR_HSICAL ((uint32_t)0x0000FF00)

Internal High Speed clock Calibration

Definition at line 1684 of file stm32f10x.h.

#define RCC_CR_HSION ((uint32_t)0x00000001)

Internal High Speed clock enable

Definition at line 1681 of file stm32f10x.h.

#define RCC_CR_HSIRDY ((uint32_t)0x00000002)

Internal High Speed clock ready flag

Definition at line 1682 of file stm32f10x.h.

#define RCC_CR_HSITRIM ((uint32_t)0x000000F8)

Internal High Speed clock trimming

Definition at line 1683 of file stm32f10x.h.

#define RCC_CR_PLLON ((uint32_t)0x01000000)

PLL enable

Definition at line 1689 of file stm32f10x.h.

Referenced by SetSysClockTo56(), and SetSysClockTo72().

#define RCC_CR_PLLRDY ((uint32_t)0x02000000)

PLL clock ready flag

Definition at line 1690 of file stm32f10x.h.

Referenced by SetSysClockTo56(), and SetSysClockTo72().

#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000)

Independent Watchdog reset flag

Definition at line 2175 of file stm32f10x.h.

#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000)

Low-Power reset flag

Definition at line 2177 of file stm32f10x.h.

#define RCC_CSR_LSION ((uint32_t)0x00000001)

Internal Low Speed oscillator enable

Definition at line 2169 of file stm32f10x.h.

#define RCC_CSR_LSIRDY ((uint32_t)0x00000002)

Internal Low Speed oscillator Ready

Definition at line 2170 of file stm32f10x.h.

#define RCC_CSR_PINRSTF ((uint32_t)0x04000000)

PIN reset flag

Definition at line 2172 of file stm32f10x.h.

#define RCC_CSR_PORRSTF ((uint32_t)0x08000000)

POR/PDR reset flag

Definition at line 2173 of file stm32f10x.h.

#define RCC_CSR_RMVF ((uint32_t)0x01000000)

Remove reset flag

Definition at line 2171 of file stm32f10x.h.

#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000)

Software Reset flag

Definition at line 2174 of file stm32f10x.h.

#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000)

Window watchdog reset flag

Definition at line 2176 of file stm32f10x.h.

#define RTC_ALRH_RTC_ALR ((uint16_t)0xFFFF)

RTC Alarm High

Definition at line 4514 of file stm32f10x.h.

#define RTC_ALRL_RTC_ALR ((uint16_t)0xFFFF)

RTC Alarm Low

Definition at line 4517 of file stm32f10x.h.

#define RTC_CNTH_RTC_CNT ((uint16_t)0xFFFF)

RTC Counter High

Definition at line 4508 of file stm32f10x.h.

#define RTC_CNTL_RTC_CNT ((uint16_t)0xFFFF)

RTC Counter Low

Definition at line 4511 of file stm32f10x.h.

#define RTC_CRH_ALRIE ((uint8_t)0x02)

Alarm Interrupt Enable

Definition at line 4484 of file stm32f10x.h.

#define RTC_CRH_OWIE ((uint8_t)0x04)

OverfloW Interrupt Enable

Definition at line 4485 of file stm32f10x.h.

#define RTC_CRH_SECIE ((uint8_t)0x01)

Second Interrupt Enable

Definition at line 4483 of file stm32f10x.h.

#define RTC_CRL_ALRF ((uint8_t)0x02)

Alarm Flag

Definition at line 4489 of file stm32f10x.h.

#define RTC_CRL_CNF ((uint8_t)0x10)

Configuration Flag

Definition at line 4492 of file stm32f10x.h.

Referenced by RTC_EnterConfigMode(), and RTC_ExitConfigMode().

#define RTC_CRL_OWF ((uint8_t)0x04)

OverfloW Flag

Definition at line 4490 of file stm32f10x.h.

#define RTC_CRL_RSF ((uint8_t)0x08)

Registers Synchronized Flag

Definition at line 4491 of file stm32f10x.h.

#define RTC_CRL_RTOFF ((uint8_t)0x20)

RTC operation OFF

Definition at line 4493 of file stm32f10x.h.

#define RTC_CRL_SECF ((uint8_t)0x01)

Second Flag

Definition at line 4488 of file stm32f10x.h.

#define RTC_DIVH_RTC_DIV ((uint16_t)0x000F)

RTC Clock Divider High

Definition at line 4502 of file stm32f10x.h.

#define RTC_DIVL_RTC_DIV ((uint16_t)0xFFFF)

RTC Clock Divider Low

Definition at line 4505 of file stm32f10x.h.

#define RTC_PRLH_PRL ((uint16_t)0x000F)

RTC Prescaler Reload Value High

Definition at line 4496 of file stm32f10x.h.

#define RTC_PRLL_PRL ((uint16_t)0xFFFF)

RTC Prescaler Reload Value Low

Definition at line 4499 of file stm32f10x.h.

#define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF)

Implementation defined

Definition at line 3256 of file stm32f10x.h.

#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000)

Data endianness bit

Definition at line 3177 of file stm32f10x.h.

#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700)

PRIGROUP[2:0] bits (Priority group)

Definition at line 3162 of file stm32f10x.h.

#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000)

Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority)

Definition at line 3168 of file stm32f10x.h.

#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100)

Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority)

Definition at line 3169 of file stm32f10x.h.

#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200)

Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority)

Definition at line 3170 of file stm32f10x.h.

#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300)

Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority)

Definition at line 3171 of file stm32f10x.h.

#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400)

Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority)

Definition at line 3172 of file stm32f10x.h.

#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500)

Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority)

Definition at line 3173 of file stm32f10x.h.

#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600)

Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority)

Definition at line 3174 of file stm32f10x.h.

#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700)

Priority group=7 (no pre-emption priority, 8 bits of subpriority)

Definition at line 3175 of file stm32f10x.h.

#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100)

Bit 0

Definition at line 3163 of file stm32f10x.h.

#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200)

Bit 1

Definition at line 3164 of file stm32f10x.h.

#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400)

Bit 2

Definition at line 3165 of file stm32f10x.h.

#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004)

Requests chip control logic to generate a reset

Definition at line 3160 of file stm32f10x.h.

#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002)

Clear active vector bit

Definition at line 3159 of file stm32f10x.h.

#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000)

Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT)

Definition at line 3178 of file stm32f10x.h.

#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001)

System Reset bit

Definition at line 3158 of file stm32f10x.h.

#define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF)

Bus fault address field

Definition at line 3253 of file stm32f10x.h.

#define SCB_CCR_BFHFNMIGN ((uint16_t)0x0100)

Handlers running at priority -1 and -2

Definition at line 3190 of file stm32f10x.h.

#define SCB_CCR_DIV_0_TRP ((uint16_t)0x0010)

Trap on Divide by 0

Definition at line 3189 of file stm32f10x.h.

#define SCB_CCR_NONBASETHRDENA ((uint16_t)0x0001)

Thread mode can be entered from any level in Handler mode by controlled return value

Definition at line 3186 of file stm32f10x.h.

#define SCB_CCR_STKALIGN ((uint16_t)0x0200)

On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned

Definition at line 3191 of file stm32f10x.h.

#define SCB_CCR_UNALIGN_TRP ((uint16_t)0x0008)

Trap for unaligned access

Definition at line 3188 of file stm32f10x.h.

#define SCB_CCR_USERSETMPEND ((uint16_t)0x0002)

Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception

Definition at line 3187 of file stm32f10x.h.

#define SCB_CFSR_BFARVALID ((uint32_t)0x00008000)

Bus Fault Address Register address valid flag UFSR

Definition at line 3228 of file stm32f10x.h.

#define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002)

Data access violation

Definition at line 3218 of file stm32f10x.h.

#define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000)

Fault occurs when SDIV or DIV instruction is used with a divisor of 0

Definition at line 3235 of file stm32f10x.h.

#define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001)

< MFSR Instruction access violation

Definition at line 3217 of file stm32f10x.h.

#define SCB_CFSR_IBUSERR ((uint32_t)0x00000100)

Instruction bus error flag

Definition at line 3223 of file stm32f10x.h.

#define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400)

Imprecise data bus error

Definition at line 3225 of file stm32f10x.h.

#define SCB_CFSR_INVPC ((uint32_t)0x00040000)

Attempt to load EXC_RETURN into pc illegally

Definition at line 3232 of file stm32f10x.h.

#define SCB_CFSR_INVSTATE ((uint32_t)0x00020000)

Invalid combination of EPSR and instruction

Definition at line 3231 of file stm32f10x.h.

#define SCB_CFSR_MMARVALID ((uint32_t)0x00000080)

Memory Manage Address Register address valid flag BFSR

Definition at line 3221 of file stm32f10x.h.

#define SCB_CFSR_MSTKERR ((uint32_t)0x00000010)

Stacking error

Definition at line 3220 of file stm32f10x.h.

#define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008)

Unstacking error

Definition at line 3219 of file stm32f10x.h.

#define SCB_CFSR_NOCP ((uint32_t)0x00080000)

Attempt to use a coprocessor instruction

Definition at line 3233 of file stm32f10x.h.

#define SCB_CFSR_PRECISERR ((uint32_t)0x00000200)

Precise data bus error

Definition at line 3224 of file stm32f10x.h.

#define SCB_CFSR_STKERR ((uint32_t)0x00001000)

Stacking error

Definition at line 3227 of file stm32f10x.h.

#define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000)

Fault occurs when there is an attempt to make an unaligned memory access

Definition at line 3234 of file stm32f10x.h.

#define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000)

The processor attempt to execute an undefined instruction

Definition at line 3230 of file stm32f10x.h.

#define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800)

Unstacking error

Definition at line 3226 of file stm32f10x.h.

#define SCB_CPUID_Constant ((uint32_t)0x000F0000)

Reads as 0x0F

Definition at line 3137 of file stm32f10x.h.

#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000)

Implementer code. ARM is 0x41

Definition at line 3139 of file stm32f10x.h.

#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0)

Number of processor within family

Definition at line 3136 of file stm32f10x.h.

#define SCB_CPUID_REVISION ((uint32_t)0x0000000F)

Implementation defined revision number

Definition at line 3135 of file stm32f10x.h.

#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000)

Implementation defined variant number

Definition at line 3138 of file stm32f10x.h.

#define SCB_DFSR_BKPT ((uint8_t)0x02)

BKPT flag

Definition at line 3244 of file stm32f10x.h.

#define SCB_DFSR_DWTTRAP ((uint8_t)0x04)

Data Watchpoint and Trace (DWT) flag

Definition at line 3245 of file stm32f10x.h.

#define SCB_DFSR_EXTERNAL ((uint8_t)0x10)

External debug request flag

Definition at line 3247 of file stm32f10x.h.

#define SCB_DFSR_HALTED ((uint8_t)0x01)

Halt request flag

Definition at line 3243 of file stm32f10x.h.

#define SCB_DFSR_VCATCH ((uint8_t)0x08)

Vector catch flag

Definition at line 3246 of file stm32f10x.h.

#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000)

Fault related to debug

Definition at line 3240 of file stm32f10x.h.

#define SCB_HFSR_FORCED ((uint32_t)0x40000000)

Hard Fault activated when a configurable Fault was received and cannot activate

Definition at line 3239 of file stm32f10x.h.

#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002)

Fault occurs because of vector table read on exception processing

Definition at line 3238 of file stm32f10x.h.

#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000)

Interrupt pending flag

Definition at line 3145 of file stm32f10x.h.

#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000)

It indicates that a pending interrupt becomes active in the next running cycle

Definition at line 3146 of file stm32f10x.h.

#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000)

Set pending NMI bit

Definition at line 3151 of file stm32f10x.h.

#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000)

Clear pending SysTick bit

Definition at line 3147 of file stm32f10x.h.

#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000)

Set pending SysTick bit

Definition at line 3148 of file stm32f10x.h.

#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000)

Clear pending pendSV bit

Definition at line 3149 of file stm32f10x.h.

#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000)

Set pending pendSV bit

Definition at line 3150 of file stm32f10x.h.

#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800)

All active exceptions minus the IPSR_current_exception yields the empty set

Definition at line 3143 of file stm32f10x.h.

#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF)

Active ISR number field

Definition at line 3142 of file stm32f10x.h.

#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000)

Pending ISR number field

Definition at line 3144 of file stm32f10x.h.

#define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF)

Mem Manage fault address field

Definition at line 3250 of file stm32f10x.h.

#define SCB_SCR_SEVONPEND ((uint8_t)0x10)

Wake up from WFE

Definition at line 3183 of file stm32f10x.h.

#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04)

Sleep deep bit

Definition at line 3182 of file stm32f10x.h.

Referenced by PWR_EnterSTANDBYMode(), and PWR_EnterSTOPMode().

#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02)

Sleep on exit bit

Definition at line 3181 of file stm32f10x.h.

#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002)

BusFault is active

Definition at line 3201 of file stm32f10x.h.

#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000)

Bus Fault enable

Definition at line 3212 of file stm32f10x.h.

#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000)

Bus Fault is pended

Definition at line 3209 of file stm32f10x.h.

#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001)

MemManage is active

Definition at line 3200 of file stm32f10x.h.

#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000)

MemManage enable

Definition at line 3211 of file stm32f10x.h.

#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000)

MemManage is pended

Definition at line 3208 of file stm32f10x.h.

#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100)

Monitor is active

Definition at line 3204 of file stm32f10x.h.

#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400)

PendSV is active

Definition at line 3205 of file stm32f10x.h.

#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080)

SVCall is active

Definition at line 3203 of file stm32f10x.h.

#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000)

SVCall is pended

Definition at line 3210 of file stm32f10x.h.

#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800)

SysTick is active

Definition at line 3206 of file stm32f10x.h.

#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008)

UsageFault is active

Definition at line 3202 of file stm32f10x.h.

#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000)

UsageFault enable

Definition at line 3213 of file stm32f10x.h.

#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000)

Usage Fault is pended

Definition at line 3207 of file stm32f10x.h.

#define SCB_SHPR_PRI_N ((uint32_t)0x000000FF)

Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor

Definition at line 3194 of file stm32f10x.h.

#define SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00)

Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved

Definition at line 3195 of file stm32f10x.h.

#define SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000)

Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV

Definition at line 3196 of file stm32f10x.h.

#define SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000)

Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick

Definition at line 3197 of file stm32f10x.h.

#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000)

Table base in code(0) or RAM(1) ***************** Bit definition for SCB_AIRCR register

Definition at line 3155 of file stm32f10x.h.

#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80)

Vector table base offset field

Definition at line 3154 of file stm32f10x.h.

#define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF)

Command argument

Definition at line 5409 of file stm32f10x.h.

#define SDIO_CLKCR_BYPASS ((uint16_t)0x0400)

Clock divider bypass enable bit

Definition at line 5399 of file stm32f10x.h.

#define SDIO_CLKCR_CLKDIV ((uint16_t)0x00FF)

Clock divide factor

Definition at line 5396 of file stm32f10x.h.

#define SDIO_CLKCR_CLKEN ((uint16_t)0x0100)

Clock enable bit

Definition at line 5397 of file stm32f10x.h.

#define SDIO_CLKCR_HWFC_EN ((uint16_t)0x4000)

HW Flow Control enable

Definition at line 5406 of file stm32f10x.h.

#define SDIO_CLKCR_NEGEDGE ((uint16_t)0x2000)

SDIO_CK dephasing selection bit

Definition at line 5405 of file stm32f10x.h.

#define SDIO_CLKCR_PWRSAV ((uint16_t)0x0200)

Power saving configuration bit

Definition at line 5398 of file stm32f10x.h.

#define SDIO_CLKCR_WIDBUS ((uint16_t)0x1800)

WIDBUS[1:0] bits (Wide bus mode enable bit)

Definition at line 5401 of file stm32f10x.h.

#define SDIO_CLKCR_WIDBUS_0 ((uint16_t)0x0800)

Bit 0

Definition at line 5402 of file stm32f10x.h.

#define SDIO_CLKCR_WIDBUS_1 ((uint16_t)0x1000)

Bit 1

Definition at line 5403 of file stm32f10x.h.

#define SDIO_CMD_CEATACMD ((uint16_t)0x4000)

CE-ATA command

Definition at line 5424 of file stm32f10x.h.

#define SDIO_CMD_CMDINDEX ((uint16_t)0x003F)

Command Index

Definition at line 5412 of file stm32f10x.h.

#define SDIO_CMD_CPSMEN ((uint16_t)0x0400)

Command path state machine (CPSM) Enable bit

Definition at line 5420 of file stm32f10x.h.

#define SDIO_CMD_ENCMDCOMPL ((uint16_t)0x1000)

Enable CMD completion

Definition at line 5422 of file stm32f10x.h.

#define SDIO_CMD_NIEN ((uint16_t)0x2000)

Not Interrupt Enable

Definition at line 5423 of file stm32f10x.h.

#define SDIO_CMD_SDIOSUSPEND ((uint16_t)0x0800)

SD I/O suspend command

Definition at line 5421 of file stm32f10x.h.

#define SDIO_CMD_WAITINT ((uint16_t)0x0100)

CPSM Waits for Interrupt Request

Definition at line 5418 of file stm32f10x.h.

#define SDIO_CMD_WAITPEND ((uint16_t)0x0200)

CPSM Waits for ends of data transfer (CmdPend internal signal)

Definition at line 5419 of file stm32f10x.h.

#define SDIO_CMD_WAITRESP ((uint16_t)0x00C0)

WAITRESP[1:0] bits (Wait for response bits)

Definition at line 5414 of file stm32f10x.h.

#define SDIO_CMD_WAITRESP_0 ((uint16_t)0x0040)

Bit 0

Definition at line 5415 of file stm32f10x.h.

#define SDIO_CMD_WAITRESP_1 ((uint16_t)0x0080)

Bit 1

Definition at line 5416 of file stm32f10x.h.

#define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF)

Data count value

Definition at line 5468 of file stm32f10x.h.

#define SDIO_DCTRL_DBLOCKSIZE ((uint16_t)0x00F0)

DBLOCKSIZE[3:0] bits (Data block size)

Definition at line 5456 of file stm32f10x.h.

#define SDIO_DCTRL_DBLOCKSIZE_0 ((uint16_t)0x0010)

Bit 0

Definition at line 5457 of file stm32f10x.h.

#define SDIO_DCTRL_DBLOCKSIZE_1 ((uint16_t)0x0020)

Bit 1

Definition at line 5458 of file stm32f10x.h.

#define SDIO_DCTRL_DBLOCKSIZE_2 ((uint16_t)0x0040)

Bit 2

Definition at line 5459 of file stm32f10x.h.

#define SDIO_DCTRL_DBLOCKSIZE_3 ((uint16_t)0x0080)

Bit 3

Definition at line 5460 of file stm32f10x.h.

#define SDIO_DCTRL_DMAEN ((uint16_t)0x0008)

DMA enabled bit

Definition at line 5454 of file stm32f10x.h.

#define SDIO_DCTRL_DTDIR ((uint16_t)0x0002)

Data transfer direction selection

Definition at line 5452 of file stm32f10x.h.

#define SDIO_DCTRL_DTEN ((uint16_t)0x0001)

Data transfer enabled bit

Definition at line 5451 of file stm32f10x.h.

#define SDIO_DCTRL_DTMODE ((uint16_t)0x0004)

Data transfer mode selection

Definition at line 5453 of file stm32f10x.h.

#define SDIO_DCTRL_RWMOD ((uint16_t)0x0400)

Read wait mode

Definition at line 5464 of file stm32f10x.h.

#define SDIO_DCTRL_RWSTART ((uint16_t)0x0100)

Read wait start

Definition at line 5462 of file stm32f10x.h.

#define SDIO_DCTRL_RWSTOP ((uint16_t)0x0200)

Read wait stop

Definition at line 5463 of file stm32f10x.h.

#define SDIO_DCTRL_SDIOEN ((uint16_t)0x0800)

SD I/O enable functions

Definition at line 5465 of file stm32f10x.h.

#define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF)

Data length value

Definition at line 5448 of file stm32f10x.h.

#define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF)

Data timeout period.

Definition at line 5445 of file stm32f10x.h.

#define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF)

Receive and transmit FIFO data

Definition at line 5541 of file stm32f10x.h.

#define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF)

Remaining number of words to be written to or read from the FIFO

Definition at line 5538 of file stm32f10x.h.

#define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001)

CCRCFAIL flag clear bit

Definition at line 5497 of file stm32f10x.h.

#define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000)

CEATAEND flag clear bit

Definition at line 5509 of file stm32f10x.h.

#define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040)

CMDREND flag clear bit

Definition at line 5503 of file stm32f10x.h.

#define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080)

CMDSENT flag clear bit

Definition at line 5504 of file stm32f10x.h.

#define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004)

CTIMEOUT flag clear bit

Definition at line 5499 of file stm32f10x.h.

#define SDIO_ICR_DATAENDC ((uint32_t)0x00000100)

DATAEND flag clear bit

Definition at line 5505 of file stm32f10x.h.

#define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400)

DBCKEND flag clear bit

Definition at line 5507 of file stm32f10x.h.

#define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002)

DCRCFAIL flag clear bit

Definition at line 5498 of file stm32f10x.h.

#define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008)

DTIMEOUT flag clear bit

Definition at line 5500 of file stm32f10x.h.

#define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020)

RXOVERR flag clear bit

Definition at line 5502 of file stm32f10x.h.

#define SDIO_ICR_SDIOITC ((uint32_t)0x00400000)

SDIOIT flag clear bit

Definition at line 5508 of file stm32f10x.h.

#define SDIO_ICR_STBITERRC ((uint32_t)0x00000200)

STBITERR flag clear bit

Definition at line 5506 of file stm32f10x.h.

#define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010)

TXUNDERR flag clear bit

Definition at line 5501 of file stm32f10x.h.

#define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001)

Command CRC Fail Interrupt Enable

Definition at line 5512 of file stm32f10x.h.

#define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000)

CE-ATA command completion signal received Interrupt Enable

Definition at line 5535 of file stm32f10x.h.

#define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800)

Command Acting Interrupt Enable

Definition at line 5523 of file stm32f10x.h.

#define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040)

Command Response Received Interrupt Enable

Definition at line 5518 of file stm32f10x.h.

#define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080)

Command Sent Interrupt Enable

Definition at line 5519 of file stm32f10x.h.

#define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004)

Command TimeOut Interrupt Enable

Definition at line 5514 of file stm32f10x.h.

#define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100)

Data End Interrupt Enable

Definition at line 5520 of file stm32f10x.h.

#define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400)

Data Block End Interrupt Enable

Definition at line 5522 of file stm32f10x.h.

#define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002)

Data CRC Fail Interrupt Enable

Definition at line 5513 of file stm32f10x.h.

#define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008)

Data TimeOut Interrupt Enable

Definition at line 5515 of file stm32f10x.h.

#define SDIO_MASK_RXACTIE ((uint32_t)0x00002000)

Data receive acting interrupt enabled

Definition at line 5525 of file stm32f10x.h.

#define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000)

Data available in Rx FIFO interrupt Enable

Definition at line 5533 of file stm32f10x.h.

#define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000)

Rx FIFO Empty interrupt Enable

Definition at line 5531 of file stm32f10x.h.

#define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000)

Rx FIFO Full interrupt Enable

Definition at line 5529 of file stm32f10x.h.

#define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000)

Rx FIFO Half Full interrupt Enable

Definition at line 5527 of file stm32f10x.h.

#define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020)

Rx FIFO OverRun Error Interrupt Enable

Definition at line 5517 of file stm32f10x.h.

#define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000)

SDIO Mode Interrupt Received interrupt Enable

Definition at line 5534 of file stm32f10x.h.

#define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200)

Start Bit Error Interrupt Enable

Definition at line 5521 of file stm32f10x.h.

#define SDIO_MASK_TXACTIE ((uint32_t)0x00001000)

Data Transmit Acting Interrupt Enable

Definition at line 5524 of file stm32f10x.h.

#define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000)

Data available in Tx FIFO interrupt Enable

Definition at line 5532 of file stm32f10x.h.

#define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000)

Tx FIFO Empty interrupt Enable

Definition at line 5530 of file stm32f10x.h.

#define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000)

Tx FIFO Full interrupt Enable

Definition at line 5528 of file stm32f10x.h.

#define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000)

Tx FIFO Half Empty interrupt Enable

Definition at line 5526 of file stm32f10x.h.

#define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010)

Tx FIFO UnderRun Error Interrupt Enable

Definition at line 5516 of file stm32f10x.h.

#define SDIO_POWER_PWRCTRL ((uint8_t)0x03)

PWRCTRL[1:0] bits (Power supply control bits)

Definition at line 5391 of file stm32f10x.h.

#define SDIO_POWER_PWRCTRL_0 ((uint8_t)0x01)

Bit 0

Definition at line 5392 of file stm32f10x.h.

#define SDIO_POWER_PWRCTRL_1 ((uint8_t)0x02)

Bit 1

Definition at line 5393 of file stm32f10x.h.

#define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF)

Card Status

Definition at line 5430 of file stm32f10x.h.

#define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF)

Card Status

Definition at line 5433 of file stm32f10x.h.

#define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF)

Card Status

Definition at line 5436 of file stm32f10x.h.

#define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF)

Card Status

Definition at line 5439 of file stm32f10x.h.

#define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF)

Card Status

Definition at line 5442 of file stm32f10x.h.

#define SDIO_RESPCMD_RESPCMD ((uint8_t)0x3F)

Response command index

Definition at line 5427 of file stm32f10x.h.

#define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001)

Command response received (CRC check failed)

Definition at line 5471 of file stm32f10x.h.

#define SDIO_STA_CEATAEND ((uint32_t)0x00800000)

CE-ATA command completion signal received for CMD61

Definition at line 5494 of file stm32f10x.h.

#define SDIO_STA_CMDACT ((uint32_t)0x00000800)

Command transfer in progress

Definition at line 5482 of file stm32f10x.h.

#define SDIO_STA_CMDREND ((uint32_t)0x00000040)

Command response received (CRC check passed)

Definition at line 5477 of file stm32f10x.h.

#define SDIO_STA_CMDSENT ((uint32_t)0x00000080)

Command sent (no response required)

Definition at line 5478 of file stm32f10x.h.

#define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004)

Command response timeout

Definition at line 5473 of file stm32f10x.h.

#define SDIO_STA_DATAEND ((uint32_t)0x00000100)

Data end (data counter, SDIDCOUNT, is zero)

Definition at line 5479 of file stm32f10x.h.

#define SDIO_STA_DBCKEND ((uint32_t)0x00000400)

Data block sent/received (CRC check passed)

Definition at line 5481 of file stm32f10x.h.

#define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002)

Data block sent/received (CRC check failed)

Definition at line 5472 of file stm32f10x.h.

#define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008)

Data timeout

Definition at line 5474 of file stm32f10x.h.

#define SDIO_STA_RXACT ((uint32_t)0x00002000)

Data receive in progress

Definition at line 5484 of file stm32f10x.h.

#define SDIO_STA_RXDAVL ((uint32_t)0x00200000)

Data available in receive FIFO

Definition at line 5492 of file stm32f10x.h.

#define SDIO_STA_RXFIFOE ((uint32_t)0x00080000)

Receive FIFO empty

Definition at line 5490 of file stm32f10x.h.

#define SDIO_STA_RXFIFOF ((uint32_t)0x00020000)

Receive FIFO full

Definition at line 5488 of file stm32f10x.h.

#define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000)

Receive FIFO Half Full: there are at least 8 words in the FIFO

Definition at line 5486 of file stm32f10x.h.

#define SDIO_STA_RXOVERR ((uint32_t)0x00000020)

Received FIFO overrun error

Definition at line 5476 of file stm32f10x.h.

#define SDIO_STA_SDIOIT ((uint32_t)0x00400000)

SDIO interrupt received

Definition at line 5493 of file stm32f10x.h.

#define SDIO_STA_STBITERR ((uint32_t)0x00000200)

Start bit not detected on all data signals in wide bus mode

Definition at line 5480 of file stm32f10x.h.

#define SDIO_STA_TXACT ((uint32_t)0x00001000)

Data transmit in progress

Definition at line 5483 of file stm32f10x.h.

#define SDIO_STA_TXDAVL ((uint32_t)0x00100000)

Data available in transmit FIFO

Definition at line 5491 of file stm32f10x.h.

#define SDIO_STA_TXFIFOE ((uint32_t)0x00040000)

Transmit FIFO empty

Definition at line 5489 of file stm32f10x.h.

#define SDIO_STA_TXFIFOF ((uint32_t)0x00010000)

Transmit FIFO full

Definition at line 5487 of file stm32f10x.h.

#define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000)

Transmit FIFO Half Empty: at least 8 words can be written into the FIFO

Definition at line 5485 of file stm32f10x.h.

#define SDIO_STA_TXUNDERR ((uint32_t)0x00000010)

Transmit FIFO underrun error

Definition at line 5475 of file stm32f10x.h.

#define SPI_CR1_BIDIMODE ((uint16_t)0x8000)

Bidirectional data mode enable

Definition at line 7485 of file stm32f10x.h.

#define SPI_CR1_BIDIOE ((uint16_t)0x4000)

Output enable in bidirectional mode

Definition at line 7484 of file stm32f10x.h.

#define SPI_CR1_BR ((uint16_t)0x0038)

BR[2:0] bits (Baud Rate Control)

Definition at line 7471 of file stm32f10x.h.

#define SPI_CR1_BR_0 ((uint16_t)0x0008)

Bit 0

Definition at line 7472 of file stm32f10x.h.

#define SPI_CR1_BR_1 ((uint16_t)0x0010)

Bit 1

Definition at line 7473 of file stm32f10x.h.

#define SPI_CR1_BR_2 ((uint16_t)0x0020)

Bit 2

Definition at line 7474 of file stm32f10x.h.

#define SPI_CR1_CPHA ((uint16_t)0x0001)

Clock Phase

Definition at line 7467 of file stm32f10x.h.

#define SPI_CR1_CPOL ((uint16_t)0x0002)

Clock Polarity

Definition at line 7468 of file stm32f10x.h.

#define SPI_CR1_CRCEN ((uint16_t)0x2000)

Hardware CRC calculation enable

Definition at line 7483 of file stm32f10x.h.

#define SPI_CR1_CRCNEXT ((uint16_t)0x1000)

Transmit CRC next

Definition at line 7482 of file stm32f10x.h.

#define SPI_CR1_DFF ((uint16_t)0x0800)

Data Frame Format

Definition at line 7481 of file stm32f10x.h.

#define SPI_CR1_LSBFIRST ((uint16_t)0x0080)

Frame Format

Definition at line 7477 of file stm32f10x.h.

#define SPI_CR1_MSTR ((uint16_t)0x0004)

Master Selection

Definition at line 7469 of file stm32f10x.h.

#define SPI_CR1_RXONLY ((uint16_t)0x0400)

Receive only

Definition at line 7480 of file stm32f10x.h.

#define SPI_CR1_SPE ((uint16_t)0x0040)

SPI Enable

Definition at line 7476 of file stm32f10x.h.

#define SPI_CR1_SSI ((uint16_t)0x0100)

Internal slave select

Definition at line 7478 of file stm32f10x.h.

#define SPI_CR1_SSM ((uint16_t)0x0200)

Software slave management

Definition at line 7479 of file stm32f10x.h.

#define SPI_CR2_ERRIE ((uint8_t)0x20)

Error Interrupt Enable

Definition at line 7491 of file stm32f10x.h.

#define SPI_CR2_RXDMAEN ((uint8_t)0x01)

Rx Buffer DMA Enable

Definition at line 7488 of file stm32f10x.h.

#define SPI_CR2_RXNEIE ((uint8_t)0x40)

RX buffer Not Empty Interrupt Enable

Definition at line 7492 of file stm32f10x.h.

#define SPI_CR2_SSOE ((uint8_t)0x04)

SS Output Enable

Definition at line 7490 of file stm32f10x.h.

#define SPI_CR2_TXDMAEN ((uint8_t)0x02)

Tx Buffer DMA Enable

Definition at line 7489 of file stm32f10x.h.

#define SPI_CR2_TXEIE ((uint8_t)0x80)

Tx buffer Empty Interrupt Enable

Definition at line 7493 of file stm32f10x.h.

#define SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF)

CRC polynomial register

Definition at line 7509 of file stm32f10x.h.

#define SPI_DR_DR ((uint16_t)0xFFFF)

Data Register

Definition at line 7506 of file stm32f10x.h.

#define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001)

Channel length (number of bits per audio channel)

Definition at line 7518 of file stm32f10x.h.

#define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008)

steady state clock polarity

Definition at line 7524 of file stm32f10x.h.

#define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006)

DATLEN[1:0] bits (Data length to be transferred)

Definition at line 7520 of file stm32f10x.h.

#define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002)

Bit 0

Definition at line 7521 of file stm32f10x.h.

#define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004)

Bit 1

Definition at line 7522 of file stm32f10x.h.

#define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300)

I2SCFG[1:0] bits (I2S configuration mode)

Definition at line 7532 of file stm32f10x.h.

#define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100)

Bit 0

Definition at line 7533 of file stm32f10x.h.

#define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200)

Bit 1

Definition at line 7534 of file stm32f10x.h.

#define SPI_I2SCFGR_I2SE ((uint16_t)0x0400)

I2S Enable

Definition at line 7536 of file stm32f10x.h.

#define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800)

I2S mode selection

Definition at line 7537 of file stm32f10x.h.

#define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030)

I2SSTD[1:0] bits (I2S standard selection)

Definition at line 7526 of file stm32f10x.h.

#define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010)

Bit 0

Definition at line 7527 of file stm32f10x.h.

#define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020)

Bit 1

Definition at line 7528 of file stm32f10x.h.

#define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080)

PCM frame synchronization

Definition at line 7530 of file stm32f10x.h.

#define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF)

I2S Linear prescaler

Definition at line 7540 of file stm32f10x.h.

#define SPI_I2SPR_MCKOE ((uint16_t)0x0200)

Master Clock Output Enable

Definition at line 7542 of file stm32f10x.h.

#define SPI_I2SPR_ODD ((uint16_t)0x0100)

Odd factor for the prescaler

Definition at line 7541 of file stm32f10x.h.

#define SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF)

Rx CRC Register

Definition at line 7512 of file stm32f10x.h.

#define SPI_SR_BSY ((uint8_t)0x80)

Busy flag

Definition at line 7503 of file stm32f10x.h.

#define SPI_SR_CHSIDE ((uint8_t)0x04)

Channel side

Definition at line 7498 of file stm32f10x.h.

#define SPI_SR_CRCERR ((uint8_t)0x10)

CRC Error flag

Definition at line 7500 of file stm32f10x.h.

#define SPI_SR_MODF ((uint8_t)0x20)

Mode fault

Definition at line 7501 of file stm32f10x.h.

#define SPI_SR_OVR ((uint8_t)0x40)

Overrun flag

Definition at line 7502 of file stm32f10x.h.

#define SPI_SR_RXNE ((uint8_t)0x01)

Receive buffer Not Empty

Definition at line 7496 of file stm32f10x.h.

#define SPI_SR_TXE ((uint8_t)0x02)

Transmit buffer Empty

Definition at line 7497 of file stm32f10x.h.

#define SPI_SR_UDR ((uint8_t)0x08)

Underrun flag

Definition at line 7499 of file stm32f10x.h.

#define SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF)

Tx CRC Register

Definition at line 7515 of file stm32f10x.h.

#define SysTick_CALIB_NOREF ((uint32_t)0x80000000)

The reference clock is not provided

Definition at line 2903 of file stm32f10x.h.

#define SysTick_CALIB_SKEW ((uint32_t)0x40000000)

Calibration value is not exactly 10 ms

Definition at line 2902 of file stm32f10x.h.

#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF)

Reload value to use for 10ms timing

Definition at line 2901 of file stm32f10x.h.

#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004)

Clock source

Definition at line 2891 of file stm32f10x.h.

#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000)

Count Flag

Definition at line 2892 of file stm32f10x.h.

#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001)

Counter enable

Definition at line 2889 of file stm32f10x.h.

#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002)

Counting down to 0 pends the SysTick handler

Definition at line 2890 of file stm32f10x.h.

#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF)

Value to load into the SysTick Current Value Register when the counter reaches 0

Definition at line 2895 of file stm32f10x.h.

#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF)

Current value at the time the register is accessed

Definition at line 2898 of file stm32f10x.h.

#define TIM_ARR_ARR ((uint16_t)0xFFFF)

actual auto-reload Value

Definition at line 4419 of file stm32f10x.h.

#define TIM_BDTR_AOE ((uint16_t)0x4000)

Automatic Output enable

Definition at line 4455 of file stm32f10x.h.

#define TIM_BDTR_BKE ((uint16_t)0x1000)

Break enable

Definition at line 4453 of file stm32f10x.h.

#define TIM_BDTR_BKP ((uint16_t)0x2000)

Break Polarity

Definition at line 4454 of file stm32f10x.h.

#define TIM_BDTR_DTG ((uint16_t)0x00FF)

DTG[0:7] bits (Dead-Time Generator set-up)

Definition at line 4437 of file stm32f10x.h.

#define TIM_BDTR_DTG_0 ((uint16_t)0x0001)

Bit 0

Definition at line 4438 of file stm32f10x.h.

#define TIM_BDTR_DTG_1 ((uint16_t)0x0002)

Bit 1

Definition at line 4439 of file stm32f10x.h.

#define TIM_BDTR_DTG_2 ((uint16_t)0x0004)

Bit 2

Definition at line 4440 of file stm32f10x.h.

#define TIM_BDTR_DTG_3 ((uint16_t)0x0008)

Bit 3

Definition at line 4441 of file stm32f10x.h.

#define TIM_BDTR_DTG_4 ((uint16_t)0x0010)

Bit 4

Definition at line 4442 of file stm32f10x.h.

#define TIM_BDTR_DTG_5 ((uint16_t)0x0020)

Bit 5

Definition at line 4443 of file stm32f10x.h.

#define TIM_BDTR_DTG_6 ((uint16_t)0x0040)

Bit 6

Definition at line 4444 of file stm32f10x.h.

#define TIM_BDTR_DTG_7 ((uint16_t)0x0080)

Bit 7

Definition at line 4445 of file stm32f10x.h.

#define TIM_BDTR_LOCK ((uint16_t)0x0300)

LOCK[1:0] bits (Lock Configuration)

Definition at line 4447 of file stm32f10x.h.

#define TIM_BDTR_LOCK_0 ((uint16_t)0x0100)

Bit 0

Definition at line 4448 of file stm32f10x.h.

#define TIM_BDTR_LOCK_1 ((uint16_t)0x0200)

Bit 1

Definition at line 4449 of file stm32f10x.h.

#define TIM_BDTR_MOE ((uint16_t)0x8000)

Main Output enable

Definition at line 4456 of file stm32f10x.h.

Referenced by TIM_CtrlPWMOutputs().

#define TIM_BDTR_OSSI ((uint16_t)0x0400)

Off-State Selection for Idle mode

Definition at line 4451 of file stm32f10x.h.

#define TIM_BDTR_OSSR ((uint16_t)0x0800)

Off-State Selection for Run mode

Definition at line 4452 of file stm32f10x.h.

#define TIM_CCER_CC1E ((uint16_t)0x0001)

Capture/Compare 1 output enable

Definition at line 4396 of file stm32f10x.h.

Referenced by TI1_Config(), and TIM_OC1Init().

#define TIM_CCER_CC1NE ((uint16_t)0x0004)

Capture/Compare 1 Complementary output enable

Definition at line 4398 of file stm32f10x.h.

Referenced by TIM_OC1Init().

#define TIM_CCER_CC1NP ((uint16_t)0x0008)

Capture/Compare 1 Complementary output Polarity

Definition at line 4399 of file stm32f10x.h.

Referenced by TI1_Config(), TIM_OC1Init(), and TIM_OC1NPolarityConfig().

#define TIM_CCER_CC1P ((uint16_t)0x0002)

Capture/Compare 1 output Polarity

Definition at line 4397 of file stm32f10x.h.

Referenced by TI1_Config(), TIM_EncoderInterfaceConfig(), TIM_OC1Init(), and TIM_OC1PolarityConfig().

#define TIM_CCER_CC2E ((uint16_t)0x0010)

Capture/Compare 2 output enable

Definition at line 4400 of file stm32f10x.h.

Referenced by TI2_Config(), and TIM_OC2Init().

#define TIM_CCER_CC2NE ((uint16_t)0x0040)

Capture/Compare 2 Complementary output enable

Definition at line 4402 of file stm32f10x.h.

Referenced by TIM_OC2Init().

#define TIM_CCER_CC2NP ((uint16_t)0x0080)

Capture/Compare 2 Complementary output Polarity

Definition at line 4403 of file stm32f10x.h.

Referenced by TI2_Config(), TIM_OC2Init(), and TIM_OC2NPolarityConfig().

#define TIM_CCER_CC2P ((uint16_t)0x0020)

Capture/Compare 2 output Polarity

Definition at line 4401 of file stm32f10x.h.

Referenced by TI2_Config(), TIM_EncoderInterfaceConfig(), TIM_OC2Init(), and TIM_OC2PolarityConfig().

#define TIM_CCER_CC3E ((uint16_t)0x0100)

Capture/Compare 3 output enable

Definition at line 4404 of file stm32f10x.h.

Referenced by TI3_Config(), and TIM_OC3Init().

#define TIM_CCER_CC3NE ((uint16_t)0x0400)

Capture/Compare 3 Complementary output enable

Definition at line 4406 of file stm32f10x.h.

Referenced by TIM_OC3Init().

#define TIM_CCER_CC3NP ((uint16_t)0x0800)

Capture/Compare 3 Complementary output Polarity

Definition at line 4407 of file stm32f10x.h.

Referenced by TI3_Config(), TIM_OC3Init(), and TIM_OC3NPolarityConfig().

#define TIM_CCER_CC3P ((uint16_t)0x0200)

Capture/Compare 3 output Polarity

Definition at line 4405 of file stm32f10x.h.

Referenced by TI3_Config(), TI4_Config(), TIM_OC3Init(), and TIM_OC3PolarityConfig().

#define TIM_CCER_CC4E ((uint16_t)0x1000)

Capture/Compare 4 output enable

Definition at line 4408 of file stm32f10x.h.

Referenced by TI4_Config(), and TIM_OC4Init().

#define TIM_CCER_CC4NP ((uint16_t)0x8000)

Capture/Compare 4 Complementary output Polarity

Definition at line 4410 of file stm32f10x.h.

Referenced by TI4_Config().

#define TIM_CCER_CC4P ((uint16_t)0x2000)

Capture/Compare 4 output Polarity

Definition at line 4409 of file stm32f10x.h.

Referenced by TI4_Config(), TIM_OC4Init(), and TIM_OC4PolarityConfig().

#define TIM_CCMR1_CC1S ((uint16_t)0x0003)

CC1S[1:0] bits (Capture/Compare 1 Selection)

Definition at line 4294 of file stm32f10x.h.

Referenced by TI1_Config(), TIM_EncoderInterfaceConfig(), and TIM_OC1Init().

#define TIM_CCMR1_CC1S_0 ((uint16_t)0x0001)

Bit 0

Definition at line 4295 of file stm32f10x.h.

Referenced by TIM_EncoderInterfaceConfig().

#define TIM_CCMR1_CC1S_1 ((uint16_t)0x0002)

Bit 1

Definition at line 4296 of file stm32f10x.h.

#define TIM_CCMR1_CC2S ((uint16_t)0x0300)

CC2S[1:0] bits (Capture/Compare 2 Selection)

Definition at line 4308 of file stm32f10x.h.

Referenced by TI2_Config(), TIM_EncoderInterfaceConfig(), and TIM_OC2Init().

#define TIM_CCMR1_CC2S_0 ((uint16_t)0x0100)

Bit 0

Definition at line 4309 of file stm32f10x.h.

Referenced by TIM_EncoderInterfaceConfig().

#define TIM_CCMR1_CC2S_1 ((uint16_t)0x0200)

Bit 1

Definition at line 4310 of file stm32f10x.h.

#define TIM_CCMR1_IC1F ((uint16_t)0x00F0)

IC1F[3:0] bits (Input Capture 1 Filter)

Definition at line 4328 of file stm32f10x.h.

Referenced by TI1_Config().

#define TIM_CCMR1_IC1F_0 ((uint16_t)0x0010)

Bit 0

Definition at line 4329 of file stm32f10x.h.

#define TIM_CCMR1_IC1F_1 ((uint16_t)0x0020)

Bit 1

Definition at line 4330 of file stm32f10x.h.

#define TIM_CCMR1_IC1F_2 ((uint16_t)0x0040)

Bit 2

Definition at line 4331 of file stm32f10x.h.

#define TIM_CCMR1_IC1F_3 ((uint16_t)0x0080)

Bit 3

Definition at line 4332 of file stm32f10x.h.

#define TIM_CCMR1_IC1PSC ((uint16_t)0x000C)

IC1PSC[1:0] bits (Input Capture 1 Prescaler)

Definition at line 4324 of file stm32f10x.h.

Referenced by TIM_SetIC1Prescaler().

#define TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004)

Bit 0

Definition at line 4325 of file stm32f10x.h.

#define TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008)

Bit 1

Definition at line 4326 of file stm32f10x.h.

#define TIM_CCMR1_IC2F ((uint16_t)0xF000)

IC2F[3:0] bits (Input Capture 2 Filter)

Definition at line 4338 of file stm32f10x.h.

Referenced by TI2_Config().

#define TIM_CCMR1_IC2F_0 ((uint16_t)0x1000)

Bit 0

Definition at line 4339 of file stm32f10x.h.

#define TIM_CCMR1_IC2F_1 ((uint16_t)0x2000)

Bit 1

Definition at line 4340 of file stm32f10x.h.

#define TIM_CCMR1_IC2F_2 ((uint16_t)0x4000)

Bit 2

Definition at line 4341 of file stm32f10x.h.

#define TIM_CCMR1_IC2F_3 ((uint16_t)0x8000)

Bit 3

Definition at line 4342 of file stm32f10x.h.

#define TIM_CCMR1_IC2PSC ((uint16_t)0x0C00)

IC2PSC[1:0] bits (Input Capture 2 Prescaler)

Definition at line 4334 of file stm32f10x.h.

Referenced by TIM_SetIC2Prescaler().

#define TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400)

Bit 0

Definition at line 4335 of file stm32f10x.h.

#define TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800)

Bit 1

Definition at line 4336 of file stm32f10x.h.

#define TIM_CCMR1_OC1CE ((uint16_t)0x0080)

Output Compare 1Clear Enable

Definition at line 4306 of file stm32f10x.h.

Referenced by TIM_ClearOC1Ref().

#define TIM_CCMR1_OC1FE ((uint16_t)0x0004)

Output Compare 1 Fast enable

Definition at line 4298 of file stm32f10x.h.

Referenced by TIM_OC1FastConfig().

#define TIM_CCMR1_OC1M ((uint16_t)0x0070)

OC1M[2:0] bits (Output Compare 1 Mode)

Definition at line 4301 of file stm32f10x.h.

Referenced by TIM_ForcedOC1Config(), TIM_OC1Init(), and TIM_SelectOCxM().

#define TIM_CCMR1_OC1M_0 ((uint16_t)0x0010)

Bit 0

Definition at line 4302 of file stm32f10x.h.

#define TIM_CCMR1_OC1M_1 ((uint16_t)0x0020)

Bit 1

Definition at line 4303 of file stm32f10x.h.

#define TIM_CCMR1_OC1M_2 ((uint16_t)0x0040)

Bit 2

Definition at line 4304 of file stm32f10x.h.

#define TIM_CCMR1_OC1PE ((uint16_t)0x0008)

Output Compare 1 Preload enable

Definition at line 4299 of file stm32f10x.h.

Referenced by TIM_OC1PreloadConfig().

#define TIM_CCMR1_OC2CE ((uint16_t)0x8000)

Output Compare 2 Clear Enable

Definition at line 4320 of file stm32f10x.h.

Referenced by TIM_ClearOC2Ref().

#define TIM_CCMR1_OC2FE ((uint16_t)0x0400)

Output Compare 2 Fast enable

Definition at line 4312 of file stm32f10x.h.

Referenced by TIM_OC2FastConfig().

#define TIM_CCMR1_OC2M ((uint16_t)0x7000)

OC2M[2:0] bits (Output Compare 2 Mode)

Definition at line 4315 of file stm32f10x.h.

Referenced by TIM_ForcedOC2Config(), TIM_OC2Init(), and TIM_SelectOCxM().

#define TIM_CCMR1_OC2M_0 ((uint16_t)0x1000)

Bit 0

Definition at line 4316 of file stm32f10x.h.

#define TIM_CCMR1_OC2M_1 ((uint16_t)0x2000)

Bit 1

Definition at line 4317 of file stm32f10x.h.

#define TIM_CCMR1_OC2M_2 ((uint16_t)0x4000)

Bit 2

Definition at line 4318 of file stm32f10x.h.

#define TIM_CCMR1_OC2PE ((uint16_t)0x0800)

Output Compare 2 Preload enable

Definition at line 4313 of file stm32f10x.h.

Referenced by TIM_OC2PreloadConfig().

#define TIM_CCMR2_CC3S ((uint16_t)0x0003)

CC3S[1:0] bits (Capture/Compare 3 Selection)

Definition at line 4345 of file stm32f10x.h.

Referenced by TI3_Config(), and TIM_OC3Init().

#define TIM_CCMR2_CC3S_0 ((uint16_t)0x0001)

Bit 0

Definition at line 4346 of file stm32f10x.h.

#define TIM_CCMR2_CC3S_1 ((uint16_t)0x0002)

Bit 1

Definition at line 4347 of file stm32f10x.h.

#define TIM_CCMR2_CC4S ((uint16_t)0x0300)

CC4S[1:0] bits (Capture/Compare 4 Selection)

Definition at line 4359 of file stm32f10x.h.

Referenced by TI4_Config(), and TIM_OC4Init().

#define TIM_CCMR2_CC4S_0 ((uint16_t)0x0100)

Bit 0

Definition at line 4360 of file stm32f10x.h.

#define TIM_CCMR2_CC4S_1 ((uint16_t)0x0200)

Bit 1

Definition at line 4361 of file stm32f10x.h.

#define TIM_CCMR2_IC3F ((uint16_t)0x00F0)

IC3F[3:0] bits (Input Capture 3 Filter)

Definition at line 4379 of file stm32f10x.h.

Referenced by TI3_Config().

#define TIM_CCMR2_IC3F_0 ((uint16_t)0x0010)

Bit 0

Definition at line 4380 of file stm32f10x.h.

#define TIM_CCMR2_IC3F_1 ((uint16_t)0x0020)

Bit 1

Definition at line 4381 of file stm32f10x.h.

#define TIM_CCMR2_IC3F_2 ((uint16_t)0x0040)

Bit 2

Definition at line 4382 of file stm32f10x.h.

#define TIM_CCMR2_IC3F_3 ((uint16_t)0x0080)

Bit 3

Definition at line 4383 of file stm32f10x.h.

#define TIM_CCMR2_IC3PSC ((uint16_t)0x000C)

IC3PSC[1:0] bits (Input Capture 3 Prescaler)

Definition at line 4375 of file stm32f10x.h.

Referenced by TIM_SetIC3Prescaler().

#define TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004)

Bit 0

Definition at line 4376 of file stm32f10x.h.

#define TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008)

Bit 1

Definition at line 4377 of file stm32f10x.h.

#define TIM_CCMR2_IC4F ((uint16_t)0xF000)

IC4F[3:0] bits (Input Capture 4 Filter)

Definition at line 4389 of file stm32f10x.h.

Referenced by TI4_Config().

#define TIM_CCMR2_IC4F_0 ((uint16_t)0x1000)

Bit 0

Definition at line 4390 of file stm32f10x.h.

#define TIM_CCMR2_IC4F_1 ((uint16_t)0x2000)

Bit 1

Definition at line 4391 of file stm32f10x.h.

#define TIM_CCMR2_IC4F_2 ((uint16_t)0x4000)

Bit 2

Definition at line 4392 of file stm32f10x.h.

#define TIM_CCMR2_IC4F_3 ((uint16_t)0x8000)

Bit 3

Definition at line 4393 of file stm32f10x.h.

#define TIM_CCMR2_IC4PSC ((uint16_t)0x0C00)

IC4PSC[1:0] bits (Input Capture 4 Prescaler)

Definition at line 4385 of file stm32f10x.h.

Referenced by TIM_SetIC4Prescaler().

#define TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400)

Bit 0

Definition at line 4386 of file stm32f10x.h.

#define TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800)

Bit 1

Definition at line 4387 of file stm32f10x.h.

#define TIM_CCMR2_OC3CE ((uint16_t)0x0080)

Output Compare 3 Clear Enable

Definition at line 4357 of file stm32f10x.h.

Referenced by TIM_ClearOC3Ref().

#define TIM_CCMR2_OC3FE ((uint16_t)0x0004)

Output Compare 3 Fast enable

Definition at line 4349 of file stm32f10x.h.

Referenced by TIM_OC3FastConfig().

#define TIM_CCMR2_OC3M ((uint16_t)0x0070)

OC3M[2:0] bits (Output Compare 3 Mode)

Definition at line 4352 of file stm32f10x.h.

Referenced by TIM_ForcedOC3Config(), and TIM_OC3Init().

#define TIM_CCMR2_OC3M_0 ((uint16_t)0x0010)

Bit 0

Definition at line 4353 of file stm32f10x.h.

#define TIM_CCMR2_OC3M_1 ((uint16_t)0x0020)

Bit 1

Definition at line 4354 of file stm32f10x.h.

#define TIM_CCMR2_OC3M_2 ((uint16_t)0x0040)

Bit 2

Definition at line 4355 of file stm32f10x.h.

#define TIM_CCMR2_OC3PE ((uint16_t)0x0008)

Output Compare 3 Preload enable

Definition at line 4350 of file stm32f10x.h.

Referenced by TIM_OC3PreloadConfig().

#define TIM_CCMR2_OC4CE ((uint16_t)0x8000)

Output Compare 4 Clear Enable

Definition at line 4371 of file stm32f10x.h.

Referenced by TIM_ClearOC4Ref().

#define TIM_CCMR2_OC4FE ((uint16_t)0x0400)

Output Compare 4 Fast enable

Definition at line 4363 of file stm32f10x.h.

Referenced by TIM_OC4FastConfig().

#define TIM_CCMR2_OC4M ((uint16_t)0x7000)

OC4M[2:0] bits (Output Compare 4 Mode)

Definition at line 4366 of file stm32f10x.h.

Referenced by TIM_ForcedOC4Config(), and TIM_OC4Init().

#define TIM_CCMR2_OC4M_0 ((uint16_t)0x1000)

Bit 0

Definition at line 4367 of file stm32f10x.h.

#define TIM_CCMR2_OC4M_1 ((uint16_t)0x2000)

Bit 1

Definition at line 4368 of file stm32f10x.h.

#define TIM_CCMR2_OC4M_2 ((uint16_t)0x4000)

Bit 2

Definition at line 4369 of file stm32f10x.h.

#define TIM_CCMR2_OC4PE ((uint16_t)0x0800)

Output Compare 4 Preload enable

Definition at line 4364 of file stm32f10x.h.

Referenced by TIM_OC4PreloadConfig().

#define TIM_CCR1_CCR1 ((uint16_t)0xFFFF)

Capture/Compare 1 Value

Definition at line 4425 of file stm32f10x.h.

#define TIM_CCR2_CCR2 ((uint16_t)0xFFFF)

Capture/Compare 2 Value

Definition at line 4428 of file stm32f10x.h.

#define TIM_CCR3_CCR3 ((uint16_t)0xFFFF)

Capture/Compare 3 Value

Definition at line 4431 of file stm32f10x.h.

#define TIM_CCR4_CCR4 ((uint16_t)0xFFFF)

Capture/Compare 4 Value

Definition at line 4434 of file stm32f10x.h.

#define TIM_CNT_CNT ((uint16_t)0xFFFF)

Counter Value

Definition at line 4413 of file stm32f10x.h.

#define TIM_CR1_ARPE ((uint16_t)0x0080)

Auto-reload preload enable

Definition at line 4201 of file stm32f10x.h.

Referenced by TIM_ARRPreloadConfig().

#define TIM_CR1_CEN ((uint16_t)0x0001)

Counter enable

Definition at line 4191 of file stm32f10x.h.

Referenced by TIM_Cmd().

#define TIM_CR1_CKD ((uint16_t)0x0300)

CKD[1:0] bits (clock division)

Definition at line 4203 of file stm32f10x.h.

Referenced by TIM_SetClockDivision(), and TIM_TimeBaseInit().

#define TIM_CR1_CKD_0 ((uint16_t)0x0100)

Bit 0

Definition at line 4204 of file stm32f10x.h.

#define TIM_CR1_CKD_1 ((uint16_t)0x0200)

Bit 1

Definition at line 4205 of file stm32f10x.h.

#define TIM_CR1_CMS ((uint16_t)0x0060)

CMS[1:0] bits (Center-aligned mode selection)

Definition at line 4197 of file stm32f10x.h.

Referenced by TIM_CounterModeConfig(), and TIM_TimeBaseInit().

#define TIM_CR1_CMS_0 ((uint16_t)0x0020)

Bit 0

Definition at line 4198 of file stm32f10x.h.

#define TIM_CR1_CMS_1 ((uint16_t)0x0040)

Bit 1

Definition at line 4199 of file stm32f10x.h.

#define TIM_CR1_DIR ((uint16_t)0x0010)

Direction

Definition at line 4195 of file stm32f10x.h.

Referenced by TIM_CounterModeConfig(), and TIM_TimeBaseInit().

#define TIM_CR1_OPM ((uint16_t)0x0008)

One pulse mode

Definition at line 4194 of file stm32f10x.h.

Referenced by TIM_SelectOnePulseMode().

#define TIM_CR1_UDIS ((uint16_t)0x0002)

Update disable

Definition at line 4192 of file stm32f10x.h.

Referenced by TIM_UpdateDisableConfig().

#define TIM_CR1_URS ((uint16_t)0x0004)

Update request source

Definition at line 4193 of file stm32f10x.h.

Referenced by TIM_UpdateRequestConfig().

#define TIM_CR2_CCDS ((uint16_t)0x0008)

Capture/Compare DMA Selection

Definition at line 4210 of file stm32f10x.h.

Referenced by TIM_SelectCCDMA().

#define TIM_CR2_CCPC ((uint16_t)0x0001)

Capture/Compare Preloaded Control

Definition at line 4208 of file stm32f10x.h.

Referenced by TIM_CCPreloadControl().

#define TIM_CR2_CCUS ((uint16_t)0x0004)

Capture/Compare Control Update Selection

Definition at line 4209 of file stm32f10x.h.

Referenced by TIM_SelectCOM().

#define TIM_CR2_MMS ((uint16_t)0x0070)

MMS[2:0] bits (Master Mode Selection)

Definition at line 4212 of file stm32f10x.h.

Referenced by TIM_SelectOutputTrigger().

#define TIM_CR2_MMS_0 ((uint16_t)0x0010)

Bit 0

Definition at line 4213 of file stm32f10x.h.

#define TIM_CR2_MMS_1 ((uint16_t)0x0020)

Bit 1

Definition at line 4214 of file stm32f10x.h.

#define TIM_CR2_MMS_2 ((uint16_t)0x0040)

Bit 2

Definition at line 4215 of file stm32f10x.h.

#define TIM_CR2_OIS1 ((uint16_t)0x0100)

Output Idle state 1 (OC1 output)

Definition at line 4218 of file stm32f10x.h.

Referenced by TIM_OC1Init().

#define TIM_CR2_OIS1N ((uint16_t)0x0200)

Output Idle state 1 (OC1N output)

Definition at line 4219 of file stm32f10x.h.

Referenced by TIM_OC1Init().

#define TIM_CR2_OIS2 ((uint16_t)0x0400)

Output Idle state 2 (OC2 output)

Definition at line 4220 of file stm32f10x.h.

Referenced by TIM_OC2Init().

#define TIM_CR2_OIS2N ((uint16_t)0x0800)

Output Idle state 2 (OC2N output)

Definition at line 4221 of file stm32f10x.h.

Referenced by TIM_OC2Init().

#define TIM_CR2_OIS3 ((uint16_t)0x1000)

Output Idle state 3 (OC3 output)

Definition at line 4222 of file stm32f10x.h.

Referenced by TIM_OC3Init().

#define TIM_CR2_OIS3N ((uint16_t)0x2000)

Output Idle state 3 (OC3N output)

Definition at line 4223 of file stm32f10x.h.

Referenced by TIM_OC3Init().

#define TIM_CR2_OIS4 ((uint16_t)0x4000)

Output Idle state 4 (OC4 output)

Definition at line 4224 of file stm32f10x.h.

Referenced by TIM_OC4Init().

#define TIM_CR2_TI1S ((uint16_t)0x0080)

TI1 Selection

Definition at line 4217 of file stm32f10x.h.

Referenced by TIM_SelectHallSensor().

#define TIM_DCR_DBA ((uint16_t)0x001F)

DBA[4:0] bits (DMA Base Address)

Definition at line 4459 of file stm32f10x.h.

#define TIM_DCR_DBA_0 ((uint16_t)0x0001)

Bit 0

Definition at line 4460 of file stm32f10x.h.

#define TIM_DCR_DBA_1 ((uint16_t)0x0002)

Bit 1

Definition at line 4461 of file stm32f10x.h.

#define TIM_DCR_DBA_2 ((uint16_t)0x0004)

Bit 2

Definition at line 4462 of file stm32f10x.h.

#define TIM_DCR_DBA_3 ((uint16_t)0x0008)

Bit 3

Definition at line 4463 of file stm32f10x.h.

#define TIM_DCR_DBA_4 ((uint16_t)0x0010)

Bit 4

Definition at line 4464 of file stm32f10x.h.

#define TIM_DCR_DBL ((uint16_t)0x1F00)

DBL[4:0] bits (DMA Burst Length)

Definition at line 4466 of file stm32f10x.h.

#define TIM_DCR_DBL_0 ((uint16_t)0x0100)

Bit 0

Definition at line 4467 of file stm32f10x.h.

#define TIM_DCR_DBL_1 ((uint16_t)0x0200)

Bit 1

Definition at line 4468 of file stm32f10x.h.

#define TIM_DCR_DBL_2 ((uint16_t)0x0400)

Bit 2

Definition at line 4469 of file stm32f10x.h.

#define TIM_DCR_DBL_3 ((uint16_t)0x0800)

Bit 3

Definition at line 4470 of file stm32f10x.h.

#define TIM_DCR_DBL_4 ((uint16_t)0x1000)

Bit 4

Definition at line 4471 of file stm32f10x.h.

#define TIM_DIER_BIE ((uint16_t)0x0080)

Break interrupt enable

Definition at line 4260 of file stm32f10x.h.

#define TIM_DIER_CC1DE ((uint16_t)0x0200)

Capture/Compare 1 DMA request enable

Definition at line 4262 of file stm32f10x.h.

#define TIM_DIER_CC1IE ((uint16_t)0x0002)

Capture/Compare 1 interrupt enable

Definition at line 4254 of file stm32f10x.h.

#define TIM_DIER_CC2DE ((uint16_t)0x0400)

Capture/Compare 2 DMA request enable

Definition at line 4263 of file stm32f10x.h.

#define TIM_DIER_CC2IE ((uint16_t)0x0004)

Capture/Compare 2 interrupt enable

Definition at line 4255 of file stm32f10x.h.

#define TIM_DIER_CC3DE ((uint16_t)0x0800)

Capture/Compare 3 DMA request enable

Definition at line 4264 of file stm32f10x.h.

#define TIM_DIER_CC3IE ((uint16_t)0x0008)

Capture/Compare 3 interrupt enable

Definition at line 4256 of file stm32f10x.h.

#define TIM_DIER_CC4DE ((uint16_t)0x1000)

Capture/Compare 4 DMA request enable

Definition at line 4265 of file stm32f10x.h.

#define TIM_DIER_CC4IE ((uint16_t)0x0010)

Capture/Compare 4 interrupt enable

Definition at line 4257 of file stm32f10x.h.

#define TIM_DIER_COMDE ((uint16_t)0x2000)

COM DMA request enable

Definition at line 4266 of file stm32f10x.h.

#define TIM_DIER_COMIE ((uint16_t)0x0020)

COM interrupt enable

Definition at line 4258 of file stm32f10x.h.

#define TIM_DIER_TDE ((uint16_t)0x4000)

Trigger DMA request enable

Definition at line 4267 of file stm32f10x.h.

#define TIM_DIER_TIE ((uint16_t)0x0040)

Trigger interrupt enable

Definition at line 4259 of file stm32f10x.h.

#define TIM_DIER_UDE ((uint16_t)0x0100)

Update DMA request enable

Definition at line 4261 of file stm32f10x.h.

#define TIM_DIER_UIE ((uint16_t)0x0001)

Update interrupt enable

Definition at line 4253 of file stm32f10x.h.

#define TIM_DMAR_DMAB ((uint16_t)0xFFFF)

DMA register for burst accesses

Definition at line 4474 of file stm32f10x.h.

#define TIM_EGR_BG ((uint8_t)0x80)

Break Generation

Definition at line 4291 of file stm32f10x.h.

#define TIM_EGR_CC1G ((uint8_t)0x02)

Capture/Compare 1 Generation

Definition at line 4285 of file stm32f10x.h.

#define TIM_EGR_CC2G ((uint8_t)0x04)

Capture/Compare 2 Generation

Definition at line 4286 of file stm32f10x.h.

#define TIM_EGR_CC3G ((uint8_t)0x08)

Capture/Compare 3 Generation

Definition at line 4287 of file stm32f10x.h.

#define TIM_EGR_CC4G ((uint8_t)0x10)

Capture/Compare 4 Generation

Definition at line 4288 of file stm32f10x.h.

#define TIM_EGR_COMG ((uint8_t)0x20)

Capture/Compare Control Update Generation

Definition at line 4289 of file stm32f10x.h.

#define TIM_EGR_TG ((uint8_t)0x40)

Trigger Generation

Definition at line 4290 of file stm32f10x.h.

#define TIM_EGR_UG ((uint8_t)0x01)

Update Generation

Definition at line 4284 of file stm32f10x.h.

#define TIM_PSC_PSC ((uint16_t)0xFFFF)

Prescaler Value

Definition at line 4416 of file stm32f10x.h.

#define TIM_RCR_REP ((uint8_t)0xFF)

Repetition Counter Value

Definition at line 4422 of file stm32f10x.h.

#define TIM_SMCR_ECE ((uint16_t)0x4000)

External clock enable

Definition at line 4249 of file stm32f10x.h.

Referenced by TIM_ETRClockMode2Config().

#define TIM_SMCR_ETF ((uint16_t)0x0F00)

ETF[3:0] bits (External trigger filter)

Definition at line 4239 of file stm32f10x.h.

#define TIM_SMCR_ETF_0 ((uint16_t)0x0100)

Bit 0

Definition at line 4240 of file stm32f10x.h.

#define TIM_SMCR_ETF_1 ((uint16_t)0x0200)

Bit 1

Definition at line 4241 of file stm32f10x.h.

#define TIM_SMCR_ETF_2 ((uint16_t)0x0400)

Bit 2

Definition at line 4242 of file stm32f10x.h.

#define TIM_SMCR_ETF_3 ((uint16_t)0x0800)

Bit 3

Definition at line 4243 of file stm32f10x.h.

#define TIM_SMCR_ETP ((uint16_t)0x8000)

External trigger polarity

Definition at line 4250 of file stm32f10x.h.

#define TIM_SMCR_ETPS ((uint16_t)0x3000)

ETPS[1:0] bits (External trigger prescaler)

Definition at line 4245 of file stm32f10x.h.

#define TIM_SMCR_ETPS_0 ((uint16_t)0x1000)

Bit 0

Definition at line 4246 of file stm32f10x.h.

#define TIM_SMCR_ETPS_1 ((uint16_t)0x2000)

Bit 1

Definition at line 4247 of file stm32f10x.h.

#define TIM_SMCR_MSM ((uint16_t)0x0080)

Master/slave mode

Definition at line 4237 of file stm32f10x.h.

Referenced by TIM_SelectMasterSlaveMode().

#define TIM_SMCR_SMS ((uint16_t)0x0007)

SMS[2:0] bits (Slave mode selection)

Definition at line 4227 of file stm32f10x.h.

Referenced by TIM_EncoderInterfaceConfig(), TIM_ETRClockMode1Config(), TIM_InternalClockConfig(), and TIM_SelectSlaveMode().

#define TIM_SMCR_SMS_0 ((uint16_t)0x0001)

Bit 0

Definition at line 4228 of file stm32f10x.h.

#define TIM_SMCR_SMS_1 ((uint16_t)0x0002)

Bit 1

Definition at line 4229 of file stm32f10x.h.

#define TIM_SMCR_SMS_2 ((uint16_t)0x0004)

Bit 2

Definition at line 4230 of file stm32f10x.h.

#define TIM_SMCR_TS ((uint16_t)0x0070)

TS[2:0] bits (Trigger selection)

Definition at line 4232 of file stm32f10x.h.

Referenced by TIM_ETRClockMode1Config(), and TIM_SelectInputTrigger().

#define TIM_SMCR_TS_0 ((uint16_t)0x0010)

Bit 0

Definition at line 4233 of file stm32f10x.h.

#define TIM_SMCR_TS_1 ((uint16_t)0x0020)

Bit 1

Definition at line 4234 of file stm32f10x.h.

#define TIM_SMCR_TS_2 ((uint16_t)0x0040)

Bit 2

Definition at line 4235 of file stm32f10x.h.

#define TIM_SR_BIF ((uint16_t)0x0080)

Break interrupt Flag

Definition at line 4277 of file stm32f10x.h.

#define TIM_SR_CC1IF ((uint16_t)0x0002)

Capture/Compare 1 interrupt Flag

Definition at line 4271 of file stm32f10x.h.

#define TIM_SR_CC1OF ((uint16_t)0x0200)

Capture/Compare 1 Overcapture Flag

Definition at line 4278 of file stm32f10x.h.

#define TIM_SR_CC2IF ((uint16_t)0x0004)

Capture/Compare 2 interrupt Flag

Definition at line 4272 of file stm32f10x.h.

#define TIM_SR_CC2OF ((uint16_t)0x0400)

Capture/Compare 2 Overcapture Flag

Definition at line 4279 of file stm32f10x.h.

#define TIM_SR_CC3IF ((uint16_t)0x0008)

Capture/Compare 3 interrupt Flag

Definition at line 4273 of file stm32f10x.h.

#define TIM_SR_CC3OF ((uint16_t)0x0800)

Capture/Compare 3 Overcapture Flag

Definition at line 4280 of file stm32f10x.h.

#define TIM_SR_CC4IF ((uint16_t)0x0010)

Capture/Compare 4 interrupt Flag

Definition at line 4274 of file stm32f10x.h.

#define TIM_SR_CC4OF ((uint16_t)0x1000)

Capture/Compare 4 Overcapture Flag

Definition at line 4281 of file stm32f10x.h.

#define TIM_SR_COMIF ((uint16_t)0x0020)

COM interrupt Flag

Definition at line 4275 of file stm32f10x.h.

#define TIM_SR_TIF ((uint16_t)0x0040)

Trigger interrupt Flag

Definition at line 4276 of file stm32f10x.h.

#define TIM_SR_UIF ((uint16_t)0x0001)

Update interrupt Flag

Definition at line 4270 of file stm32f10x.h.

#define USART_BRR_DIV_Fraction ((uint16_t)0x000F)

Fraction of USARTDIV

Definition at line 7661 of file stm32f10x.h.

#define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0)

Mantissa of USARTDIV

Definition at line 7662 of file stm32f10x.h.

#define USART_CR1_IDLEIE ((uint16_t)0x0010)

IDLE Interrupt Enable

Definition at line 7669 of file stm32f10x.h.

#define USART_CR1_M ((uint16_t)0x1000)

Word length

Definition at line 7677 of file stm32f10x.h.

#define USART_CR1_OVER8 ((uint16_t)0x8000)

USART Oversmapling 8-bits

Definition at line 7679 of file stm32f10x.h.

#define USART_CR1_PCE ((uint16_t)0x0400)

Parity Control Enable

Definition at line 7675 of file stm32f10x.h.

#define USART_CR1_PEIE ((uint16_t)0x0100)

PE Interrupt Enable

Definition at line 7673 of file stm32f10x.h.

#define USART_CR1_PS ((uint16_t)0x0200)

Parity Selection

Definition at line 7674 of file stm32f10x.h.

#define USART_CR1_RE ((uint16_t)0x0004)

Receiver Enable

Definition at line 7667 of file stm32f10x.h.

#define USART_CR1_RWU ((uint16_t)0x0002)

Receiver wakeup

Definition at line 7666 of file stm32f10x.h.

#define USART_CR1_RXNEIE ((uint16_t)0x0020)

RXNE Interrupt Enable

Definition at line 7670 of file stm32f10x.h.

#define USART_CR1_SBK ((uint16_t)0x0001)

Send Break

Definition at line 7665 of file stm32f10x.h.

#define USART_CR1_TCIE ((uint16_t)0x0040)

Transmission Complete Interrupt Enable

Definition at line 7671 of file stm32f10x.h.

#define USART_CR1_TE ((uint16_t)0x0008)

Transmitter Enable

Definition at line 7668 of file stm32f10x.h.

#define USART_CR1_TXEIE ((uint16_t)0x0080)

PE Interrupt Enable

Definition at line 7672 of file stm32f10x.h.

#define USART_CR1_UE ((uint16_t)0x2000)

USART Enable

Definition at line 7678 of file stm32f10x.h.

#define USART_CR1_WAKE ((uint16_t)0x0800)

Wakeup method

Definition at line 7676 of file stm32f10x.h.

#define USART_CR2_ADD ((uint16_t)0x000F)

Address of the USART node

Definition at line 7682 of file stm32f10x.h.

#define USART_CR2_CLKEN ((uint16_t)0x0800)

Clock Enable

Definition at line 7688 of file stm32f10x.h.

#define USART_CR2_CPHA ((uint16_t)0x0200)

Clock Phase

Definition at line 7686 of file stm32f10x.h.

#define USART_CR2_CPOL ((uint16_t)0x0400)

Clock Polarity

Definition at line 7687 of file stm32f10x.h.

#define USART_CR2_LBCL ((uint16_t)0x0100)

Last Bit Clock pulse

Definition at line 7685 of file stm32f10x.h.

#define USART_CR2_LBDIE ((uint16_t)0x0040)

LIN Break Detection Interrupt Enable

Definition at line 7684 of file stm32f10x.h.

#define USART_CR2_LBDL ((uint16_t)0x0020)

LIN Break Detection Length

Definition at line 7683 of file stm32f10x.h.

#define USART_CR2_LINEN ((uint16_t)0x4000)

LIN mode enable

Definition at line 7694 of file stm32f10x.h.

#define USART_CR2_STOP ((uint16_t)0x3000)

STOP[1:0] bits (STOP bits)

Definition at line 7690 of file stm32f10x.h.

#define USART_CR2_STOP_0 ((uint16_t)0x1000)

Bit 0

Definition at line 7691 of file stm32f10x.h.

#define USART_CR2_STOP_1 ((uint16_t)0x2000)

Bit 1

Definition at line 7692 of file stm32f10x.h.

#define USART_CR3_CTSE ((uint16_t)0x0200)

CTS Enable

Definition at line 7706 of file stm32f10x.h.

#define USART_CR3_CTSIE ((uint16_t)0x0400)

CTS Interrupt Enable

Definition at line 7707 of file stm32f10x.h.

#define USART_CR3_DMAR ((uint16_t)0x0040)

DMA Enable Receiver

Definition at line 7703 of file stm32f10x.h.

#define USART_CR3_DMAT ((uint16_t)0x0080)

DMA Enable Transmitter

Definition at line 7704 of file stm32f10x.h.

#define USART_CR3_EIE ((uint16_t)0x0001)

Error Interrupt Enable

Definition at line 7697 of file stm32f10x.h.

#define USART_CR3_HDSEL ((uint16_t)0x0008)

Half-Duplex Selection

Definition at line 7700 of file stm32f10x.h.

#define USART_CR3_IREN ((uint16_t)0x0002)

IrDA mode Enable

Definition at line 7698 of file stm32f10x.h.

#define USART_CR3_IRLP ((uint16_t)0x0004)

IrDA Low-Power

Definition at line 7699 of file stm32f10x.h.

#define USART_CR3_NACK ((uint16_t)0x0010)

Smartcard NACK enable

Definition at line 7701 of file stm32f10x.h.

#define USART_CR3_ONEBIT ((uint16_t)0x0800)

One Bit method

Definition at line 7708 of file stm32f10x.h.

#define USART_CR3_RTSE ((uint16_t)0x0100)

RTS Enable

Definition at line 7705 of file stm32f10x.h.

#define USART_CR3_SCEN ((uint16_t)0x0020)

Smartcard mode enable

Definition at line 7702 of file stm32f10x.h.

#define USART_DR_DR ((uint16_t)0x01FF)

Data value

Definition at line 7658 of file stm32f10x.h.

#define USART_GTPR_GT ((uint16_t)0xFF00)

Guard time value

Definition at line 7721 of file stm32f10x.h.

#define USART_GTPR_PSC ((uint16_t)0x00FF)

PSC[7:0] bits (Prescaler value)

Definition at line 7711 of file stm32f10x.h.

#define USART_GTPR_PSC_0 ((uint16_t)0x0001)

Bit 0

Definition at line 7712 of file stm32f10x.h.

#define USART_GTPR_PSC_1 ((uint16_t)0x0002)

Bit 1

Definition at line 7713 of file stm32f10x.h.

#define USART_GTPR_PSC_2 ((uint16_t)0x0004)

Bit 2

Definition at line 7714 of file stm32f10x.h.

#define USART_GTPR_PSC_3 ((uint16_t)0x0008)

Bit 3

Definition at line 7715 of file stm32f10x.h.

#define USART_GTPR_PSC_4 ((uint16_t)0x0010)

Bit 4

Definition at line 7716 of file stm32f10x.h.

#define USART_GTPR_PSC_5 ((uint16_t)0x0020)

Bit 5

Definition at line 7717 of file stm32f10x.h.

#define USART_GTPR_PSC_6 ((uint16_t)0x0040)

Bit 6

Definition at line 7718 of file stm32f10x.h.

#define USART_GTPR_PSC_7 ((uint16_t)0x0080)

Bit 7

Definition at line 7719 of file stm32f10x.h.

#define USART_SR_CTS ((uint16_t)0x0200)

CTS Flag

Definition at line 7655 of file stm32f10x.h.

#define USART_SR_FE ((uint16_t)0x0002)

Framing Error

Definition at line 7647 of file stm32f10x.h.

#define USART_SR_IDLE ((uint16_t)0x0010)

IDLE line detected

Definition at line 7650 of file stm32f10x.h.

#define USART_SR_LBD ((uint16_t)0x0100)

LIN Break Detection Flag

Definition at line 7654 of file stm32f10x.h.

#define USART_SR_NE ((uint16_t)0x0004)

Noise Error Flag

Definition at line 7648 of file stm32f10x.h.

#define USART_SR_ORE ((uint16_t)0x0008)

OverRun Error

Definition at line 7649 of file stm32f10x.h.

#define USART_SR_PE ((uint16_t)0x0001)

Parity Error

Definition at line 7646 of file stm32f10x.h.

#define USART_SR_RXNE ((uint16_t)0x0020)

Read Data Register Not Empty

Definition at line 7651 of file stm32f10x.h.

#define USART_SR_TC ((uint16_t)0x0040)

Transmission Complete

Definition at line 7652 of file stm32f10x.h.

#define USART_SR_TXE ((uint16_t)0x0080)

Transmit Data Register Empty

Definition at line 7653 of file stm32f10x.h.

#define USB_ADDR0_RX_ADDR0_RX ((uint16_t)0xFFFE)

Reception Buffer Address 0

Definition at line 5896 of file stm32f10x.h.

#define USB_ADDR0_TX_ADDR0_TX ((uint16_t)0xFFFE)

Transmission Buffer Address 0

Definition at line 5794 of file stm32f10x.h.

#define USB_ADDR1_RX_ADDR1_RX ((uint16_t)0xFFFE)

Reception Buffer Address 1

Definition at line 5899 of file stm32f10x.h.

#define USB_ADDR1_TX_ADDR1_TX ((uint16_t)0xFFFE)

Transmission Buffer Address 1

Definition at line 5797 of file stm32f10x.h.

#define USB_ADDR2_RX_ADDR2_RX ((uint16_t)0xFFFE)

Reception Buffer Address 2

Definition at line 5902 of file stm32f10x.h.

#define USB_ADDR2_TX_ADDR2_TX ((uint16_t)0xFFFE)

Transmission Buffer Address 2

Definition at line 5800 of file stm32f10x.h.

#define USB_ADDR3_RX_ADDR3_RX ((uint16_t)0xFFFE)

Reception Buffer Address 3

Definition at line 5905 of file stm32f10x.h.

#define USB_ADDR3_TX_ADDR3_TX ((uint16_t)0xFFFE)

Transmission Buffer Address 3

Definition at line 5803 of file stm32f10x.h.

#define USB_ADDR4_RX_ADDR4_RX ((uint16_t)0xFFFE)

Reception Buffer Address 4

Definition at line 5908 of file stm32f10x.h.

#define USB_ADDR4_TX_ADDR4_TX ((uint16_t)0xFFFE)

Transmission Buffer Address 4

Definition at line 5806 of file stm32f10x.h.

#define USB_ADDR5_RX_ADDR5_RX ((uint16_t)0xFFFE)

Reception Buffer Address 5

Definition at line 5911 of file stm32f10x.h.

#define USB_ADDR5_TX_ADDR5_TX ((uint16_t)0xFFFE)

Transmission Buffer Address 5

Definition at line 5809 of file stm32f10x.h.

#define USB_ADDR6_RX_ADDR6_RX ((uint16_t)0xFFFE)

Reception Buffer Address 6

Definition at line 5914 of file stm32f10x.h.

#define USB_ADDR6_TX_ADDR6_TX ((uint16_t)0xFFFE)

Transmission Buffer Address 6

Definition at line 5812 of file stm32f10x.h.

#define USB_ADDR7_RX_ADDR7_RX ((uint16_t)0xFFFE)

Reception Buffer Address 7

Definition at line 5917 of file stm32f10x.h.

#define USB_ADDR7_TX_ADDR7_TX ((uint16_t)0xFFFE)

Transmission Buffer Address 7

Definition at line 5815 of file stm32f10x.h.

#define USB_BTABLE_BTABLE ((uint16_t)0xFFF8)

Buffer Table Buffer descriptor table

Definition at line 5790 of file stm32f10x.h.

#define USB_CNTR_CTRM ((uint16_t)0x8000)

Correct Transfer Interrupt Mask

Definition at line 5756 of file stm32f10x.h.

#define USB_CNTR_ERRM ((uint16_t)0x2000)

Error Interrupt Mask

Definition at line 5754 of file stm32f10x.h.

#define USB_CNTR_ESOFM ((uint16_t)0x0100)

Expected Start Of Frame Interrupt Mask

Definition at line 5749 of file stm32f10x.h.

#define USB_CNTR_FRES ((uint16_t)0x0001)

Force USB Reset

Definition at line 5744 of file stm32f10x.h.

#define USB_CNTR_FSUSP ((uint16_t)0x0008)

Force suspend

Definition at line 5747 of file stm32f10x.h.

#define USB_CNTR_LP_MODE ((uint16_t)0x0004)

Low-power mode

Definition at line 5746 of file stm32f10x.h.

#define USB_CNTR_PDWN ((uint16_t)0x0002)

Power down

Definition at line 5745 of file stm32f10x.h.

#define USB_CNTR_PMAOVRM ((uint16_t)0x4000)

Packet Memory Area Over / Underrun Interrupt Mask

Definition at line 5755 of file stm32f10x.h.

#define USB_CNTR_RESETM ((uint16_t)0x0400)

RESET Interrupt Mask

Definition at line 5751 of file stm32f10x.h.

#define USB_CNTR_RESUME ((uint16_t)0x0010)

Resume request

Definition at line 5748 of file stm32f10x.h.

#define USB_CNTR_SOFM ((uint16_t)0x0200)

Start Of Frame Interrupt Mask

Definition at line 5750 of file stm32f10x.h.

#define USB_CNTR_SUSPM ((uint16_t)0x0800)

Suspend mode Interrupt Mask

Definition at line 5752 of file stm32f10x.h.

#define USB_CNTR_WKUPM ((uint16_t)0x1000)

Wakeup Interrupt Mask

Definition at line 5753 of file stm32f10x.h.

#define USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000)

BLock SIZE (low)

Definition at line 6029 of file stm32f10x.h.

#define USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF)

Reception Byte Count (low)

Definition at line 6020 of file stm32f10x.h.

#define USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00)

NUM_BLOCK_0[4:0] bits (Number of blocks) (low)

Definition at line 6022 of file stm32f10x.h.

#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400)

Bit 0

Definition at line 6023 of file stm32f10x.h.

#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800)

Bit 1

Definition at line 6024 of file stm32f10x.h.

#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000)

Bit 2

Definition at line 6025 of file stm32f10x.h.

#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000)

Bit 3

Definition at line 6026 of file stm32f10x.h.

#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000)

Bit 4

Definition at line 6027 of file stm32f10x.h.

#define USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000)

BLock SIZE (high)

Definition at line 6041 of file stm32f10x.h.

#define USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000)

Reception Byte Count (high)

Definition at line 6032 of file stm32f10x.h.

#define USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000)

NUM_BLOCK_1[4:0] bits (Number of blocks) (high)

Definition at line 6034 of file stm32f10x.h.

#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000)

Bit 1

Definition at line 6035 of file stm32f10x.h.

#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000)

Bit 1

Definition at line 6036 of file stm32f10x.h.

#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000)

Bit 2

Definition at line 6037 of file stm32f10x.h.

#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000)

Bit 3

Definition at line 6038 of file stm32f10x.h.

#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000)

Bit 4

Definition at line 6039 of file stm32f10x.h.

#define USB_COUNT0_RX_BLSIZE ((uint16_t)0x8000)

BLock SIZE

Definition at line 5931 of file stm32f10x.h.

#define USB_COUNT0_RX_COUNT0_RX ((uint16_t)0x03FF)

Reception Byte Count

Definition at line 5922 of file stm32f10x.h.

#define USB_COUNT0_RX_NUM_BLOCK ((uint16_t)0x7C00)

NUM_BLOCK[4:0] bits (Number of blocks)

Definition at line 5924 of file stm32f10x.h.

#define USB_COUNT0_RX_NUM_BLOCK_0 ((uint16_t)0x0400)

Bit 0

Definition at line 5925 of file stm32f10x.h.

#define USB_COUNT0_RX_NUM_BLOCK_1 ((uint16_t)0x0800)

Bit 1

Definition at line 5926 of file stm32f10x.h.

#define USB_COUNT0_RX_NUM_BLOCK_2 ((uint16_t)0x1000)

Bit 2

Definition at line 5927 of file stm32f10x.h.

#define USB_COUNT0_RX_NUM_BLOCK_3 ((uint16_t)0x2000)

Bit 3

Definition at line 5928 of file stm32f10x.h.

#define USB_COUNT0_RX_NUM_BLOCK_4 ((uint16_t)0x4000)

Bit 4

Definition at line 5929 of file stm32f10x.h.

#define USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF)

Transmission Byte Count 0 (low)

Definition at line 5846 of file stm32f10x.h.

#define USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000)

Transmission Byte Count 0 (high)

Definition at line 5849 of file stm32f10x.h.

#define USB_COUNT0_TX_COUNT0_TX ((uint16_t)0x03FF)

Transmission Byte Count 0

Definition at line 5820 of file stm32f10x.h.

#define USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000)

BLock SIZE (low)

Definition at line 6053 of file stm32f10x.h.

#define USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF)

Reception Byte Count (low)

Definition at line 6044 of file stm32f10x.h.

#define USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00)

NUM_BLOCK_0[4:0] bits (Number of blocks) (low)

Definition at line 6046 of file stm32f10x.h.

#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400)

Bit 0

Definition at line 6047 of file stm32f10x.h.

#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800)

Bit 1

Definition at line 6048 of file stm32f10x.h.

#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000)

Bit 2

Definition at line 6049 of file stm32f10x.h.

#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000)

Bit 3

Definition at line 6050 of file stm32f10x.h.

#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000)

Bit 4

Definition at line 6051 of file stm32f10x.h.

#define USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000)

BLock SIZE (high)

Definition at line 6065 of file stm32f10x.h.

#define USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000)

Reception Byte Count (high)

Definition at line 6056 of file stm32f10x.h.

#define USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000)

NUM_BLOCK_1[4:0] bits (Number of blocks) (high)

Definition at line 6058 of file stm32f10x.h.

#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000)

Bit 0

Definition at line 6059 of file stm32f10x.h.

#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000)

Bit 1

Definition at line 6060 of file stm32f10x.h.

#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000)

Bit 2

Definition at line 6061 of file stm32f10x.h.

#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000)

Bit 3

Definition at line 6062 of file stm32f10x.h.

#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000)

Bit 4

Definition at line 6063 of file stm32f10x.h.

#define USB_COUNT1_RX_BLSIZE ((uint16_t)0x8000)

BLock SIZE

Definition at line 5943 of file stm32f10x.h.

#define USB_COUNT1_RX_COUNT1_RX ((uint16_t)0x03FF)

Reception Byte Count

Definition at line 5934 of file stm32f10x.h.

#define USB_COUNT1_RX_NUM_BLOCK ((uint16_t)0x7C00)

NUM_BLOCK[4:0] bits (Number of blocks)

Definition at line 5936 of file stm32f10x.h.

#define USB_COUNT1_RX_NUM_BLOCK_0 ((uint16_t)0x0400)

Bit 0

Definition at line 5937 of file stm32f10x.h.

#define USB_COUNT1_RX_NUM_BLOCK_1 ((uint16_t)0x0800)

Bit 1

Definition at line 5938 of file stm32f10x.h.

#define USB_COUNT1_RX_NUM_BLOCK_2 ((uint16_t)0x1000)

Bit 2

Definition at line 5939 of file stm32f10x.h.

#define USB_COUNT1_RX_NUM_BLOCK_3 ((uint16_t)0x2000)

Bit 3

Definition at line 5940 of file stm32f10x.h.

#define USB_COUNT1_RX_NUM_BLOCK_4 ((uint16_t)0x4000)

Bit 4

Definition at line 5941 of file stm32f10x.h.

#define USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF)

Transmission Byte Count 1 (low)

Definition at line 5852 of file stm32f10x.h.

#define USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000)

Transmission Byte Count 1 (high)

Definition at line 5855 of file stm32f10x.h.

#define USB_COUNT1_TX_COUNT1_TX ((uint16_t)0x03FF)

Transmission Byte Count 1

Definition at line 5823 of file stm32f10x.h.

#define USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000)

BLock SIZE (low)

Definition at line 6077 of file stm32f10x.h.

#define USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF)

Reception Byte Count (low)

Definition at line 6068 of file stm32f10x.h.

#define USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00)

NUM_BLOCK_0[4:0] bits (Number of blocks) (low)

Definition at line 6070 of file stm32f10x.h.

#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400)

Bit 0

Definition at line 6071 of file stm32f10x.h.

#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800)

Bit 1

Definition at line 6072 of file stm32f10x.h.

#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000)

Bit 2

Definition at line 6073 of file stm32f10x.h.

#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000)

Bit 3

Definition at line 6074 of file stm32f10x.h.

#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000)

Bit 4

Definition at line 6075 of file stm32f10x.h.

#define USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000)

BLock SIZE (high)

Definition at line 6089 of file stm32f10x.h.

#define USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000)

Reception Byte Count (high)

Definition at line 6080 of file stm32f10x.h.

#define USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000)

NUM_BLOCK_1[4:0] bits (Number of blocks) (high)

Definition at line 6082 of file stm32f10x.h.

#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000)

Bit 0

Definition at line 6083 of file stm32f10x.h.

#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000)

Bit 1

Definition at line 6084 of file stm32f10x.h.

#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000)

Bit 2

Definition at line 6085 of file stm32f10x.h.

#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000)

Bit 3

Definition at line 6086 of file stm32f10x.h.

#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000)

Bit 4

Definition at line 6087 of file stm32f10x.h.

#define USB_COUNT2_RX_BLSIZE ((uint16_t)0x8000)

BLock SIZE

Definition at line 5955 of file stm32f10x.h.

#define USB_COUNT2_RX_COUNT2_RX ((uint16_t)0x03FF)

Reception Byte Count

Definition at line 5946 of file stm32f10x.h.

#define USB_COUNT2_RX_NUM_BLOCK ((uint16_t)0x7C00)

NUM_BLOCK[4:0] bits (Number of blocks)

Definition at line 5948 of file stm32f10x.h.

#define USB_COUNT2_RX_NUM_BLOCK_0 ((uint16_t)0x0400)

Bit 0

Definition at line 5949 of file stm32f10x.h.

#define USB_COUNT2_RX_NUM_BLOCK_1 ((uint16_t)0x0800)

Bit 1

Definition at line 5950 of file stm32f10x.h.

#define USB_COUNT2_RX_NUM_BLOCK_2 ((uint16_t)0x1000)

Bit 2

Definition at line 5951 of file stm32f10x.h.

#define USB_COUNT2_RX_NUM_BLOCK_3 ((uint16_t)0x2000)

Bit 3

Definition at line 5952 of file stm32f10x.h.

#define USB_COUNT2_RX_NUM_BLOCK_4 ((uint16_t)0x4000)

Bit 4

Definition at line 5953 of file stm32f10x.h.

#define USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF)

Transmission Byte Count 2 (low)

Definition at line 5858 of file stm32f10x.h.

#define USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000)

Transmission Byte Count 2 (high)

Definition at line 5861 of file stm32f10x.h.

#define USB_COUNT2_TX_COUNT2_TX ((uint16_t)0x03FF)

Transmission Byte Count 2

Definition at line 5826 of file stm32f10x.h.

#define USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000)

BLock SIZE (low)

Definition at line 6101 of file stm32f10x.h.

#define USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF)

Reception Byte Count (low)

Definition at line 6092 of file stm32f10x.h.

#define USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00)

NUM_BLOCK_0[4:0] bits (Number of blocks) (low)

Definition at line 6094 of file stm32f10x.h.

#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400)

Bit 0

Definition at line 6095 of file stm32f10x.h.

#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800)

Bit 1

Definition at line 6096 of file stm32f10x.h.

#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000)

Bit 2

Definition at line 6097 of file stm32f10x.h.

#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000)

Bit 3

Definition at line 6098 of file stm32f10x.h.

#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000)

Bit 4

Definition at line 6099 of file stm32f10x.h.

#define USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000)

BLock SIZE (high)

Definition at line 6113 of file stm32f10x.h.

#define USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000)

Reception Byte Count (high)

Definition at line 6104 of file stm32f10x.h.

#define USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000)

NUM_BLOCK_1[4:0] bits (Number of blocks) (high)

Definition at line 6106 of file stm32f10x.h.

#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000)

Bit 0

Definition at line 6107 of file stm32f10x.h.

#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000)

Bit 1

Definition at line 6108 of file stm32f10x.h.

#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000)

Bit 2

Definition at line 6109 of file stm32f10x.h.

#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000)

Bit 3

Definition at line 6110 of file stm32f10x.h.

#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000)

Bit 4

Definition at line 6111 of file stm32f10x.h.

#define USB_COUNT3_RX_BLSIZE ((uint16_t)0x8000)

BLock SIZE

Definition at line 5967 of file stm32f10x.h.

#define USB_COUNT3_RX_COUNT3_RX ((uint16_t)0x03FF)

Reception Byte Count

Definition at line 5958 of file stm32f10x.h.

#define USB_COUNT3_RX_NUM_BLOCK ((uint16_t)0x7C00)

NUM_BLOCK[4:0] bits (Number of blocks)

Definition at line 5960 of file stm32f10x.h.

#define USB_COUNT3_RX_NUM_BLOCK_0 ((uint16_t)0x0400)

Bit 0

Definition at line 5961 of file stm32f10x.h.

#define USB_COUNT3_RX_NUM_BLOCK_1 ((uint16_t)0x0800)

Bit 1

Definition at line 5962 of file stm32f10x.h.

#define USB_COUNT3_RX_NUM_BLOCK_2 ((uint16_t)0x1000)

Bit 2

Definition at line 5963 of file stm32f10x.h.

#define USB_COUNT3_RX_NUM_BLOCK_3 ((uint16_t)0x2000)

Bit 3

Definition at line 5964 of file stm32f10x.h.

#define USB_COUNT3_RX_NUM_BLOCK_4 ((uint16_t)0x4000)

Bit 4

Definition at line 5965 of file stm32f10x.h.

#define USB_COUNT3_TX_0_COUNT3_TX_0 ((uint16_t)0x000003FF)

Transmission Byte Count 3 (low)

Definition at line 5864 of file stm32f10x.h.

#define USB_COUNT3_TX_1_COUNT3_TX_1 ((uint16_t)0x03FF0000)

Transmission Byte Count 3 (high)

Definition at line 5867 of file stm32f10x.h.

#define USB_COUNT3_TX_COUNT3_TX ((uint16_t)0x03FF)

Transmission Byte Count 3

Definition at line 5829 of file stm32f10x.h.

#define USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000)

BLock SIZE (low)

Definition at line 6125 of file stm32f10x.h.

#define USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF)

Reception Byte Count (low)

Definition at line 6116 of file stm32f10x.h.

#define USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00)

NUM_BLOCK_0[4:0] bits (Number of blocks) (low)

Definition at line 6118 of file stm32f10x.h.

#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400)

Bit 0

Definition at line 6119 of file stm32f10x.h.

#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800)

Bit 1

Definition at line 6120 of file stm32f10x.h.

#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000)

Bit 2

Definition at line 6121 of file stm32f10x.h.

#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000)

Bit 3

Definition at line 6122 of file stm32f10x.h.

#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000)

Bit 4

Definition at line 6123 of file stm32f10x.h.

#define USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000)

BLock SIZE (high)

Definition at line 6137 of file stm32f10x.h.

#define USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000)

Reception Byte Count (high)

Definition at line 6128 of file stm32f10x.h.

#define USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000)

NUM_BLOCK_1[4:0] bits (Number of blocks) (high)

Definition at line 6130 of file stm32f10x.h.

#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000)

Bit 0

Definition at line 6131 of file stm32f10x.h.

#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000)

Bit 1

Definition at line 6132 of file stm32f10x.h.

#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000)

Bit 2

Definition at line 6133 of file stm32f10x.h.

#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000)

Bit 3

Definition at line 6134 of file stm32f10x.h.

#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000)

Bit 4

Definition at line 6135 of file stm32f10x.h.

#define USB_COUNT4_RX_BLSIZE ((uint16_t)0x8000)

BLock SIZE

Definition at line 5979 of file stm32f10x.h.

#define USB_COUNT4_RX_COUNT4_RX ((uint16_t)0x03FF)

Reception Byte Count

Definition at line 5970 of file stm32f10x.h.

#define USB_COUNT4_RX_NUM_BLOCK ((uint16_t)0x7C00)

NUM_BLOCK[4:0] bits (Number of blocks)

Definition at line 5972 of file stm32f10x.h.

#define USB_COUNT4_RX_NUM_BLOCK_0 ((uint16_t)0x0400)

Bit 0

Definition at line 5973 of file stm32f10x.h.

#define USB_COUNT4_RX_NUM_BLOCK_1 ((uint16_t)0x0800)

Bit 1

Definition at line 5974 of file stm32f10x.h.

#define USB_COUNT4_RX_NUM_BLOCK_2 ((uint16_t)0x1000)

Bit 2

Definition at line 5975 of file stm32f10x.h.

#define USB_COUNT4_RX_NUM_BLOCK_3 ((uint16_t)0x2000)

Bit 3

Definition at line 5976 of file stm32f10x.h.

#define USB_COUNT4_RX_NUM_BLOCK_4 ((uint16_t)0x4000)

Bit 4

Definition at line 5977 of file stm32f10x.h.

#define USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF)

Transmission Byte Count 4 (low)

Definition at line 5870 of file stm32f10x.h.

#define USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000)

Transmission Byte Count 4 (high)

Definition at line 5873 of file stm32f10x.h.

#define USB_COUNT4_TX_COUNT4_TX ((uint16_t)0x03FF)

Transmission Byte Count 4

Definition at line 5832 of file stm32f10x.h.

#define USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000)

BLock SIZE (low)

Definition at line 6149 of file stm32f10x.h.

#define USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF)

Reception Byte Count (low)

Definition at line 6140 of file stm32f10x.h.

#define USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00)

NUM_BLOCK_0[4:0] bits (Number of blocks) (low)

Definition at line 6142 of file stm32f10x.h.

#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400)

Bit 0

Definition at line 6143 of file stm32f10x.h.

#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800)

Bit 1

Definition at line 6144 of file stm32f10x.h.

#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000)

Bit 2

Definition at line 6145 of file stm32f10x.h.

#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000)

Bit 3

Definition at line 6146 of file stm32f10x.h.

#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000)

Bit 4

Definition at line 6147 of file stm32f10x.h.

#define USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000)

BLock SIZE (high)

Definition at line 6161 of file stm32f10x.h.

#define USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000)

Reception Byte Count (high)

Definition at line 6152 of file stm32f10x.h.

#define USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000)

NUM_BLOCK_1[4:0] bits (Number of blocks) (high)

Definition at line 6154 of file stm32f10x.h.

#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000)

Bit 0

Definition at line 6155 of file stm32f10x.h.

#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000)

Bit 1

Definition at line 6156 of file stm32f10x.h.

#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000)

Bit 2

Definition at line 6157 of file stm32f10x.h.

#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000)

Bit 3

Definition at line 6158 of file stm32f10x.h.

#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000)

Bit 4

Definition at line 6159 of file stm32f10x.h.

#define USB_COUNT5_RX_BLSIZE ((uint16_t)0x8000)

BLock SIZE

Definition at line 5991 of file stm32f10x.h.

#define USB_COUNT5_RX_COUNT5_RX ((uint16_t)0x03FF)

Reception Byte Count

Definition at line 5982 of file stm32f10x.h.

#define USB_COUNT5_RX_NUM_BLOCK ((uint16_t)0x7C00)

NUM_BLOCK[4:0] bits (Number of blocks)

Definition at line 5984 of file stm32f10x.h.

#define USB_COUNT5_RX_NUM_BLOCK_0 ((uint16_t)0x0400)

Bit 0

Definition at line 5985 of file stm32f10x.h.

#define USB_COUNT5_RX_NUM_BLOCK_1 ((uint16_t)0x0800)

Bit 1

Definition at line 5986 of file stm32f10x.h.

#define USB_COUNT5_RX_NUM_BLOCK_2 ((uint16_t)0x1000)

Bit 2

Definition at line 5987 of file stm32f10x.h.

#define USB_COUNT5_RX_NUM_BLOCK_3 ((uint16_t)0x2000)

Bit 3

Definition at line 5988 of file stm32f10x.h.

#define USB_COUNT5_RX_NUM_BLOCK_4 ((uint16_t)0x4000)

Bit 4

Definition at line 5989 of file stm32f10x.h.

#define USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF)

Transmission Byte Count 5 (low)

Definition at line 5876 of file stm32f10x.h.

#define USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000)

Transmission Byte Count 5 (high)

Definition at line 5879 of file stm32f10x.h.

#define USB_COUNT5_TX_COUNT5_TX ((uint16_t)0x03FF)

Transmission Byte Count 5

Definition at line 5835 of file stm32f10x.h.

#define USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000)

BLock SIZE (low)

Definition at line 6173 of file stm32f10x.h.

#define USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF)

Reception Byte Count (low)

Definition at line 6164 of file stm32f10x.h.

#define USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00)

NUM_BLOCK_0[4:0] bits (Number of blocks) (low)

Definition at line 6166 of file stm32f10x.h.

#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400)

Bit 0

Definition at line 6167 of file stm32f10x.h.

#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800)

Bit 1

Definition at line 6168 of file stm32f10x.h.

#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000)

Bit 2

Definition at line 6169 of file stm32f10x.h.

#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000)

Bit 3

Definition at line 6170 of file stm32f10x.h.

#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000)

Bit 4

Definition at line 6171 of file stm32f10x.h.

#define USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000)

BLock SIZE (high)

Definition at line 6185 of file stm32f10x.h.

#define USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000)

Reception Byte Count (high)

Definition at line 6176 of file stm32f10x.h.

#define USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000)

NUM_BLOCK_1[4:0] bits (Number of blocks) (high)

Definition at line 6178 of file stm32f10x.h.

#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000)

Bit 0

Definition at line 6179 of file stm32f10x.h.

#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000)

Bit 1

Definition at line 6180 of file stm32f10x.h.

#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000)

Bit 2

Definition at line 6181 of file stm32f10x.h.

#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000)

Bit 3

Definition at line 6182 of file stm32f10x.h.

#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000)

Bit 4

Definition at line 6183 of file stm32f10x.h.

#define USB_COUNT6_RX_BLSIZE ((uint16_t)0x8000)

BLock SIZE

Definition at line 6003 of file stm32f10x.h.

#define USB_COUNT6_RX_COUNT6_RX ((uint16_t)0x03FF)

Reception Byte Count

Definition at line 5994 of file stm32f10x.h.

#define USB_COUNT6_RX_NUM_BLOCK ((uint16_t)0x7C00)

NUM_BLOCK[4:0] bits (Number of blocks)

Definition at line 5996 of file stm32f10x.h.

#define USB_COUNT6_RX_NUM_BLOCK_0 ((uint16_t)0x0400)

Bit 0

Definition at line 5997 of file stm32f10x.h.

#define USB_COUNT6_RX_NUM_BLOCK_1 ((uint16_t)0x0800)

Bit 1

Definition at line 5998 of file stm32f10x.h.

#define USB_COUNT6_RX_NUM_BLOCK_2 ((uint16_t)0x1000)

Bit 2

Definition at line 5999 of file stm32f10x.h.

#define USB_COUNT6_RX_NUM_BLOCK_3 ((uint16_t)0x2000)

Bit 3

Definition at line 6000 of file stm32f10x.h.

#define USB_COUNT6_RX_NUM_BLOCK_4 ((uint16_t)0x4000)

Bit 4

Definition at line 6001 of file stm32f10x.h.

#define USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF)

Transmission Byte Count 6 (low)

Definition at line 5882 of file stm32f10x.h.

#define USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000)

Transmission Byte Count 6 (high)

Definition at line 5885 of file stm32f10x.h.

#define USB_COUNT6_TX_COUNT6_TX ((uint16_t)0x03FF)

Transmission Byte Count 6

Definition at line 5838 of file stm32f10x.h.

#define USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000)

BLock SIZE (low)

Definition at line 6197 of file stm32f10x.h.

#define USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF)

Reception Byte Count (low)

Definition at line 6188 of file stm32f10x.h.

#define USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00)

NUM_BLOCK_0[4:0] bits (Number of blocks) (low)

Definition at line 6190 of file stm32f10x.h.

#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400)

Bit 0

Definition at line 6191 of file stm32f10x.h.

#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800)

Bit 1

Definition at line 6192 of file stm32f10x.h.

#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000)

Bit 2

Definition at line 6193 of file stm32f10x.h.

#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000)

Bit 3

Definition at line 6194 of file stm32f10x.h.

#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000)

Bit 4

Definition at line 6195 of file stm32f10x.h.

#define USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000)

BLock SIZE (high)

Definition at line 6209 of file stm32f10x.h.

#define USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000)

Reception Byte Count (high)

Definition at line 6200 of file stm32f10x.h.

#define USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000)

NUM_BLOCK_1[4:0] bits (Number of blocks) (high)

Definition at line 6202 of file stm32f10x.h.

#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000)

Bit 0

Definition at line 6203 of file stm32f10x.h.

#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000)

Bit 1

Definition at line 6204 of file stm32f10x.h.

#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000)

Bit 2

Definition at line 6205 of file stm32f10x.h.

#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000)

Bit 3

Definition at line 6206 of file stm32f10x.h.

#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000)

Bit 4

Definition at line 6207 of file stm32f10x.h.

#define USB_COUNT7_RX_BLSIZE ((uint16_t)0x8000)

BLock SIZE

Definition at line 6015 of file stm32f10x.h.

#define USB_COUNT7_RX_COUNT7_RX ((uint16_t)0x03FF)

Reception Byte Count

Definition at line 6006 of file stm32f10x.h.

#define USB_COUNT7_RX_NUM_BLOCK ((uint16_t)0x7C00)

NUM_BLOCK[4:0] bits (Number of blocks)

Definition at line 6008 of file stm32f10x.h.

#define USB_COUNT7_RX_NUM_BLOCK_0 ((uint16_t)0x0400)

Bit 0

Definition at line 6009 of file stm32f10x.h.

#define USB_COUNT7_RX_NUM_BLOCK_1 ((uint16_t)0x0800)

Bit 1

Definition at line 6010 of file stm32f10x.h.

#define USB_COUNT7_RX_NUM_BLOCK_2 ((uint16_t)0x1000)

Bit 2

Definition at line 6011 of file stm32f10x.h.

#define USB_COUNT7_RX_NUM_BLOCK_3 ((uint16_t)0x2000)

Bit 3

Definition at line 6012 of file stm32f10x.h.

#define USB_COUNT7_RX_NUM_BLOCK_4 ((uint16_t)0x4000)

Bit 4

Definition at line 6013 of file stm32f10x.h.

#define USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF)

Transmission Byte Count 7 (low)

Definition at line 5888 of file stm32f10x.h.

#define USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000)

Transmission Byte Count 7 (high)

Definition at line 5891 of file stm32f10x.h.

#define USB_COUNT7_TX_COUNT7_TX ((uint16_t)0x03FF)

Transmission Byte Count 7

Definition at line 5841 of file stm32f10x.h.

#define USB_DADDR_ADD ((uint8_t)0x7F)

ADD[6:0] bits (Device Address)

Definition at line 5778 of file stm32f10x.h.

#define USB_DADDR_ADD0 ((uint8_t)0x01)

Bit 0

Definition at line 5779 of file stm32f10x.h.

#define USB_DADDR_ADD1 ((uint8_t)0x02)

Bit 1

Definition at line 5780 of file stm32f10x.h.

#define USB_DADDR_ADD2 ((uint8_t)0x04)

Bit 2

Definition at line 5781 of file stm32f10x.h.

#define USB_DADDR_ADD3 ((uint8_t)0x08)

Bit 3

Definition at line 5782 of file stm32f10x.h.

#define USB_DADDR_ADD4 ((uint8_t)0x10)

Bit 4

Definition at line 5783 of file stm32f10x.h.

#define USB_DADDR_ADD5 ((uint8_t)0x20)

Bit 5

Definition at line 5784 of file stm32f10x.h.

#define USB_DADDR_ADD6 ((uint8_t)0x40)

Bit 6

Definition at line 5785 of file stm32f10x.h.

#define USB_DADDR_EF ((uint8_t)0x80)

Enable Function

Definition at line 5787 of file stm32f10x.h.

#define USB_EP0R_CTR_RX ((uint16_t)0x8000)

Correct Transfer for reception

Definition at line 5572 of file stm32f10x.h.

#define USB_EP0R_CTR_TX ((uint16_t)0x0080)

Correct Transfer for transmission

Definition at line 5558 of file stm32f10x.h.

#define USB_EP0R_DTOG_RX ((uint16_t)0x4000)

Data Toggle, for reception transfers

Definition at line 5571 of file stm32f10x.h.

#define USB_EP0R_DTOG_TX ((uint16_t)0x0040)

Data Toggle, for transmission transfers

Definition at line 5557 of file stm32f10x.h.

#define USB_EP0R_EA ((uint16_t)0x000F)

< Endpoint-specific registers Endpoint Address

Definition at line 5551 of file stm32f10x.h.

#define USB_EP0R_EP_KIND ((uint16_t)0x0100)

Endpoint Kind

Definition at line 5559 of file stm32f10x.h.

#define USB_EP0R_EP_TYPE ((uint16_t)0x0600)

EP_TYPE[1:0] bits (Endpoint type)

Definition at line 5561 of file stm32f10x.h.

#define USB_EP0R_EP_TYPE_0 ((uint16_t)0x0200)

Bit 0

Definition at line 5562 of file stm32f10x.h.

#define USB_EP0R_EP_TYPE_1 ((uint16_t)0x0400)

Bit 1

Definition at line 5563 of file stm32f10x.h.

#define USB_EP0R_SETUP ((uint16_t)0x0800)

Setup transaction completed

Definition at line 5565 of file stm32f10x.h.

#define USB_EP0R_STAT_RX ((uint16_t)0x3000)

STAT_RX[1:0] bits (Status bits, for reception transfers)

Definition at line 5567 of file stm32f10x.h.

#define USB_EP0R_STAT_RX_0 ((uint16_t)0x1000)

Bit 0

Definition at line 5568 of file stm32f10x.h.

#define USB_EP0R_STAT_RX_1 ((uint16_t)0x2000)

Bit 1

Definition at line 5569 of file stm32f10x.h.

#define USB_EP0R_STAT_TX ((uint16_t)0x0030)

STAT_TX[1:0] bits (Status bits, for transmission transfers)

Definition at line 5553 of file stm32f10x.h.

#define USB_EP0R_STAT_TX_0 ((uint16_t)0x0010)

Bit 0

Definition at line 5554 of file stm32f10x.h.

#define USB_EP0R_STAT_TX_1 ((uint16_t)0x0020)

Bit 1

Definition at line 5555 of file stm32f10x.h.

#define USB_EP1R_CTR_RX ((uint16_t)0x8000)

Correct Transfer for reception

Definition at line 5596 of file stm32f10x.h.

#define USB_EP1R_CTR_TX ((uint16_t)0x0080)

Correct Transfer for transmission

Definition at line 5582 of file stm32f10x.h.

#define USB_EP1R_DTOG_RX ((uint16_t)0x4000)

Data Toggle, for reception transfers

Definition at line 5595 of file stm32f10x.h.

#define USB_EP1R_DTOG_TX ((uint16_t)0x0040)

Data Toggle, for transmission transfers

Definition at line 5581 of file stm32f10x.h.

#define USB_EP1R_EA ((uint16_t)0x000F)

Endpoint Address

Definition at line 5575 of file stm32f10x.h.

#define USB_EP1R_EP_KIND ((uint16_t)0x0100)

Endpoint Kind

Definition at line 5583 of file stm32f10x.h.

#define USB_EP1R_EP_TYPE ((uint16_t)0x0600)

EP_TYPE[1:0] bits (Endpoint type)

Definition at line 5585 of file stm32f10x.h.

#define USB_EP1R_EP_TYPE_0 ((uint16_t)0x0200)

Bit 0

Definition at line 5586 of file stm32f10x.h.

#define USB_EP1R_EP_TYPE_1 ((uint16_t)0x0400)

Bit 1

Definition at line 5587 of file stm32f10x.h.

#define USB_EP1R_SETUP ((uint16_t)0x0800)

Setup transaction completed

Definition at line 5589 of file stm32f10x.h.

#define USB_EP1R_STAT_RX ((uint16_t)0x3000)

STAT_RX[1:0] bits (Status bits, for reception transfers)

Definition at line 5591 of file stm32f10x.h.

#define USB_EP1R_STAT_RX_0 ((uint16_t)0x1000)

Bit 0

Definition at line 5592 of file stm32f10x.h.

#define USB_EP1R_STAT_RX_1 ((uint16_t)0x2000)

Bit 1

Definition at line 5593 of file stm32f10x.h.

#define USB_EP1R_STAT_TX ((uint16_t)0x0030)

STAT_TX[1:0] bits (Status bits, for transmission transfers)

Definition at line 5577 of file stm32f10x.h.

#define USB_EP1R_STAT_TX_0 ((uint16_t)0x0010)

Bit 0

Definition at line 5578 of file stm32f10x.h.

#define USB_EP1R_STAT_TX_1 ((uint16_t)0x0020)

Bit 1

Definition at line 5579 of file stm32f10x.h.

#define USB_EP2R_CTR_RX ((uint16_t)0x8000)

Correct Transfer for reception

Definition at line 5620 of file stm32f10x.h.

#define USB_EP2R_CTR_TX ((uint16_t)0x0080)

Correct Transfer for transmission

Definition at line 5606 of file stm32f10x.h.

#define USB_EP2R_DTOG_RX ((uint16_t)0x4000)

Data Toggle, for reception transfers

Definition at line 5619 of file stm32f10x.h.

#define USB_EP2R_DTOG_TX ((uint16_t)0x0040)

Data Toggle, for transmission transfers

Definition at line 5605 of file stm32f10x.h.

#define USB_EP2R_EA ((uint16_t)0x000F)

Endpoint Address

Definition at line 5599 of file stm32f10x.h.

#define USB_EP2R_EP_KIND ((uint16_t)0x0100)

Endpoint Kind

Definition at line 5607 of file stm32f10x.h.

#define USB_EP2R_EP_TYPE ((uint16_t)0x0600)

EP_TYPE[1:0] bits (Endpoint type)

Definition at line 5609 of file stm32f10x.h.

#define USB_EP2R_EP_TYPE_0 ((uint16_t)0x0200)

Bit 0

Definition at line 5610 of file stm32f10x.h.

#define USB_EP2R_EP_TYPE_1 ((uint16_t)0x0400)

Bit 1

Definition at line 5611 of file stm32f10x.h.

#define USB_EP2R_SETUP ((uint16_t)0x0800)

Setup transaction completed

Definition at line 5613 of file stm32f10x.h.

#define USB_EP2R_STAT_RX ((uint16_t)0x3000)

STAT_RX[1:0] bits (Status bits, for reception transfers)

Definition at line 5615 of file stm32f10x.h.

#define USB_EP2R_STAT_RX_0 ((uint16_t)0x1000)

Bit 0

Definition at line 5616 of file stm32f10x.h.

#define USB_EP2R_STAT_RX_1 ((uint16_t)0x2000)

Bit 1

Definition at line 5617 of file stm32f10x.h.

#define USB_EP2R_STAT_TX ((uint16_t)0x0030)

STAT_TX[1:0] bits (Status bits, for transmission transfers)

Definition at line 5601 of file stm32f10x.h.

#define USB_EP2R_STAT_TX_0 ((uint16_t)0x0010)

Bit 0

Definition at line 5602 of file stm32f10x.h.

#define USB_EP2R_STAT_TX_1 ((uint16_t)0x0020)

Bit 1

Definition at line 5603 of file stm32f10x.h.

#define USB_EP3R_CTR_RX ((uint16_t)0x8000)

Correct Transfer for reception

Definition at line 5644 of file stm32f10x.h.

#define USB_EP3R_CTR_TX ((uint16_t)0x0080)

Correct Transfer for transmission

Definition at line 5630 of file stm32f10x.h.

#define USB_EP3R_DTOG_RX ((uint16_t)0x4000)

Data Toggle, for reception transfers

Definition at line 5643 of file stm32f10x.h.

#define USB_EP3R_DTOG_TX ((uint16_t)0x0040)

Data Toggle, for transmission transfers

Definition at line 5629 of file stm32f10x.h.

#define USB_EP3R_EA ((uint16_t)0x000F)

Endpoint Address

Definition at line 5623 of file stm32f10x.h.

#define USB_EP3R_EP_KIND ((uint16_t)0x0100)

Endpoint Kind

Definition at line 5631 of file stm32f10x.h.

#define USB_EP3R_EP_TYPE ((uint16_t)0x0600)

EP_TYPE[1:0] bits (Endpoint type)

Definition at line 5633 of file stm32f10x.h.

#define USB_EP3R_EP_TYPE_0 ((uint16_t)0x0200)

Bit 0

Definition at line 5634 of file stm32f10x.h.

#define USB_EP3R_EP_TYPE_1 ((uint16_t)0x0400)

Bit 1

Definition at line 5635 of file stm32f10x.h.

#define USB_EP3R_SETUP ((uint16_t)0x0800)

Setup transaction completed

Definition at line 5637 of file stm32f10x.h.

#define USB_EP3R_STAT_RX ((uint16_t)0x3000)

STAT_RX[1:0] bits (Status bits, for reception transfers)

Definition at line 5639 of file stm32f10x.h.

#define USB_EP3R_STAT_RX_0 ((uint16_t)0x1000)

Bit 0

Definition at line 5640 of file stm32f10x.h.

#define USB_EP3R_STAT_RX_1 ((uint16_t)0x2000)

Bit 1

Definition at line 5641 of file stm32f10x.h.

#define USB_EP3R_STAT_TX ((uint16_t)0x0030)

STAT_TX[1:0] bits (Status bits, for transmission transfers)

Definition at line 5625 of file stm32f10x.h.

#define USB_EP3R_STAT_TX_0 ((uint16_t)0x0010)

Bit 0

Definition at line 5626 of file stm32f10x.h.

#define USB_EP3R_STAT_TX_1 ((uint16_t)0x0020)

Bit 1

Definition at line 5627 of file stm32f10x.h.

#define USB_EP4R_CTR_RX ((uint16_t)0x8000)

Correct Transfer for reception

Definition at line 5668 of file stm32f10x.h.

#define USB_EP4R_CTR_TX ((uint16_t)0x0080)

Correct Transfer for transmission

Definition at line 5654 of file stm32f10x.h.

#define USB_EP4R_DTOG_RX ((uint16_t)0x4000)

Data Toggle, for reception transfers

Definition at line 5667 of file stm32f10x.h.

#define USB_EP4R_DTOG_TX ((uint16_t)0x0040)

Data Toggle, for transmission transfers

Definition at line 5653 of file stm32f10x.h.

#define USB_EP4R_EA ((uint16_t)0x000F)

Endpoint Address

Definition at line 5647 of file stm32f10x.h.

#define USB_EP4R_EP_KIND ((uint16_t)0x0100)

Endpoint Kind

Definition at line 5655 of file stm32f10x.h.

#define USB_EP4R_EP_TYPE ((uint16_t)0x0600)

EP_TYPE[1:0] bits (Endpoint type)

Definition at line 5657 of file stm32f10x.h.

#define USB_EP4R_EP_TYPE_0 ((uint16_t)0x0200)

Bit 0

Definition at line 5658 of file stm32f10x.h.

#define USB_EP4R_EP_TYPE_1 ((uint16_t)0x0400)

Bit 1

Definition at line 5659 of file stm32f10x.h.

#define USB_EP4R_SETUP ((uint16_t)0x0800)

Setup transaction completed

Definition at line 5661 of file stm32f10x.h.

#define USB_EP4R_STAT_RX ((uint16_t)0x3000)

STAT_RX[1:0] bits (Status bits, for reception transfers)

Definition at line 5663 of file stm32f10x.h.

#define USB_EP4R_STAT_RX_0 ((uint16_t)0x1000)

Bit 0

Definition at line 5664 of file stm32f10x.h.

#define USB_EP4R_STAT_RX_1 ((uint16_t)0x2000)

Bit 1

Definition at line 5665 of file stm32f10x.h.

#define USB_EP4R_STAT_TX ((uint16_t)0x0030)

STAT_TX[1:0] bits (Status bits, for transmission transfers)

Definition at line 5649 of file stm32f10x.h.

#define USB_EP4R_STAT_TX_0 ((uint16_t)0x0010)

Bit 0

Definition at line 5650 of file stm32f10x.h.

#define USB_EP4R_STAT_TX_1 ((uint16_t)0x0020)

Bit 1

Definition at line 5651 of file stm32f10x.h.

#define USB_EP5R_CTR_RX ((uint16_t)0x8000)

Correct Transfer for reception

Definition at line 5692 of file stm32f10x.h.

#define USB_EP5R_CTR_TX ((uint16_t)0x0080)

Correct Transfer for transmission

Definition at line 5678 of file stm32f10x.h.

#define USB_EP5R_DTOG_RX ((uint16_t)0x4000)

Data Toggle, for reception transfers

Definition at line 5691 of file stm32f10x.h.

#define USB_EP5R_DTOG_TX ((uint16_t)0x0040)

Data Toggle, for transmission transfers

Definition at line 5677 of file stm32f10x.h.

#define USB_EP5R_EA ((uint16_t)0x000F)

Endpoint Address

Definition at line 5671 of file stm32f10x.h.

#define USB_EP5R_EP_KIND ((uint16_t)0x0100)

Endpoint Kind

Definition at line 5679 of file stm32f10x.h.

#define USB_EP5R_EP_TYPE ((uint16_t)0x0600)

EP_TYPE[1:0] bits (Endpoint type)

Definition at line 5681 of file stm32f10x.h.

#define USB_EP5R_EP_TYPE_0 ((uint16_t)0x0200)

Bit 0

Definition at line 5682 of file stm32f10x.h.

#define USB_EP5R_EP_TYPE_1 ((uint16_t)0x0400)

Bit 1

Definition at line 5683 of file stm32f10x.h.

#define USB_EP5R_SETUP ((uint16_t)0x0800)

Setup transaction completed

Definition at line 5685 of file stm32f10x.h.

#define USB_EP5R_STAT_RX ((uint16_t)0x3000)

STAT_RX[1:0] bits (Status bits, for reception transfers)

Definition at line 5687 of file stm32f10x.h.

#define USB_EP5R_STAT_RX_0 ((uint16_t)0x1000)

Bit 0

Definition at line 5688 of file stm32f10x.h.

#define USB_EP5R_STAT_RX_1 ((uint16_t)0x2000)

Bit 1

Definition at line 5689 of file stm32f10x.h.

#define USB_EP5R_STAT_TX ((uint16_t)0x0030)

STAT_TX[1:0] bits (Status bits, for transmission transfers)

Definition at line 5673 of file stm32f10x.h.

#define USB_EP5R_STAT_TX_0 ((uint16_t)0x0010)

Bit 0

Definition at line 5674 of file stm32f10x.h.

#define USB_EP5R_STAT_TX_1 ((uint16_t)0x0020)

Bit 1

Definition at line 5675 of file stm32f10x.h.

#define USB_EP6R_CTR_RX ((uint16_t)0x8000)

Correct Transfer for reception

Definition at line 5716 of file stm32f10x.h.

#define USB_EP6R_CTR_TX ((uint16_t)0x0080)

Correct Transfer for transmission

Definition at line 5702 of file stm32f10x.h.

#define USB_EP6R_DTOG_RX ((uint16_t)0x4000)

Data Toggle, for reception transfers

Definition at line 5715 of file stm32f10x.h.

#define USB_EP6R_DTOG_TX ((uint16_t)0x0040)

Data Toggle, for transmission transfers

Definition at line 5701 of file stm32f10x.h.

#define USB_EP6R_EA ((uint16_t)0x000F)

Endpoint Address

Definition at line 5695 of file stm32f10x.h.

#define USB_EP6R_EP_KIND ((uint16_t)0x0100)

Endpoint Kind

Definition at line 5703 of file stm32f10x.h.

#define USB_EP6R_EP_TYPE ((uint16_t)0x0600)

EP_TYPE[1:0] bits (Endpoint type)

Definition at line 5705 of file stm32f10x.h.

#define USB_EP6R_EP_TYPE_0 ((uint16_t)0x0200)

Bit 0

Definition at line 5706 of file stm32f10x.h.

#define USB_EP6R_EP_TYPE_1 ((uint16_t)0x0400)

Bit 1

Definition at line 5707 of file stm32f10x.h.

#define USB_EP6R_SETUP ((uint16_t)0x0800)

Setup transaction completed

Definition at line 5709 of file stm32f10x.h.

#define USB_EP6R_STAT_RX ((uint16_t)0x3000)

STAT_RX[1:0] bits (Status bits, for reception transfers)

Definition at line 5711 of file stm32f10x.h.

#define USB_EP6R_STAT_RX_0 ((uint16_t)0x1000)

Bit 0

Definition at line 5712 of file stm32f10x.h.

#define USB_EP6R_STAT_RX_1 ((uint16_t)0x2000)

Bit 1

Definition at line 5713 of file stm32f10x.h.

#define USB_EP6R_STAT_TX ((uint16_t)0x0030)

STAT_TX[1:0] bits (Status bits, for transmission transfers)

Definition at line 5697 of file stm32f10x.h.

#define USB_EP6R_STAT_TX_0 ((uint16_t)0x0010)

Bit 0

Definition at line 5698 of file stm32f10x.h.

#define USB_EP6R_STAT_TX_1 ((uint16_t)0x0020)

Bit 1

Definition at line 5699 of file stm32f10x.h.

#define USB_EP7R_CTR_RX ((uint16_t)0x8000)

Correct Transfer for reception Common registers

Definition at line 5740 of file stm32f10x.h.

#define USB_EP7R_CTR_TX ((uint16_t)0x0080)

Correct Transfer for transmission

Definition at line 5726 of file stm32f10x.h.

#define USB_EP7R_DTOG_RX ((uint16_t)0x4000)

Data Toggle, for reception transfers

Definition at line 5739 of file stm32f10x.h.

#define USB_EP7R_DTOG_TX ((uint16_t)0x0040)

Data Toggle, for transmission transfers

Definition at line 5725 of file stm32f10x.h.

#define USB_EP7R_EA ((uint16_t)0x000F)

Endpoint Address

Definition at line 5719 of file stm32f10x.h.

#define USB_EP7R_EP_KIND ((uint16_t)0x0100)

Endpoint Kind

Definition at line 5727 of file stm32f10x.h.

#define USB_EP7R_EP_TYPE ((uint16_t)0x0600)

EP_TYPE[1:0] bits (Endpoint type)

Definition at line 5729 of file stm32f10x.h.

#define USB_EP7R_EP_TYPE_0 ((uint16_t)0x0200)

Bit 0

Definition at line 5730 of file stm32f10x.h.

#define USB_EP7R_EP_TYPE_1 ((uint16_t)0x0400)

Bit 1

Definition at line 5731 of file stm32f10x.h.

#define USB_EP7R_SETUP ((uint16_t)0x0800)

Setup transaction completed

Definition at line 5733 of file stm32f10x.h.

#define USB_EP7R_STAT_RX ((uint16_t)0x3000)

STAT_RX[1:0] bits (Status bits, for reception transfers)

Definition at line 5735 of file stm32f10x.h.

#define USB_EP7R_STAT_RX_0 ((uint16_t)0x1000)

Bit 0

Definition at line 5736 of file stm32f10x.h.

#define USB_EP7R_STAT_RX_1 ((uint16_t)0x2000)

Bit 1

Definition at line 5737 of file stm32f10x.h.

#define USB_EP7R_STAT_TX ((uint16_t)0x0030)

STAT_TX[1:0] bits (Status bits, for transmission transfers)

Definition at line 5721 of file stm32f10x.h.

#define USB_EP7R_STAT_TX_0 ((uint16_t)0x0010)

Bit 0

Definition at line 5722 of file stm32f10x.h.

#define USB_EP7R_STAT_TX_1 ((uint16_t)0x0020)

Bit 1

Definition at line 5723 of file stm32f10x.h.

#define USB_FNR_FN ((uint16_t)0x07FF)

Frame Number

Definition at line 5771 of file stm32f10x.h.

#define USB_FNR_LCK ((uint16_t)0x2000)

Locked

Definition at line 5773 of file stm32f10x.h.

#define USB_FNR_LSOF ((uint16_t)0x1800)

Lost SOF

Definition at line 5772 of file stm32f10x.h.

#define USB_FNR_RXDM ((uint16_t)0x4000)

Receive Data - Line Status

Definition at line 5774 of file stm32f10x.h.

#define USB_FNR_RXDP ((uint16_t)0x8000)

Receive Data + Line Status

Definition at line 5775 of file stm32f10x.h.

#define USB_ISTR_CTR ((uint16_t)0x8000)

Correct Transfer

Definition at line 5768 of file stm32f10x.h.

#define USB_ISTR_DIR ((uint16_t)0x0010)

Direction of transaction

Definition at line 5760 of file stm32f10x.h.

#define USB_ISTR_EP_ID ((uint16_t)0x000F)

Endpoint Identifier

Definition at line 5759 of file stm32f10x.h.

#define USB_ISTR_ERR ((uint16_t)0x2000)

Error

Definition at line 5766 of file stm32f10x.h.

#define USB_ISTR_ESOF ((uint16_t)0x0100)

Expected Start Of Frame

Definition at line 5761 of file stm32f10x.h.

#define USB_ISTR_PMAOVR ((uint16_t)0x4000)

Packet Memory Area Over / Underrun

Definition at line 5767 of file stm32f10x.h.

#define USB_ISTR_RESET ((uint16_t)0x0400)

USB RESET request

Definition at line 5763 of file stm32f10x.h.

#define USB_ISTR_SOF ((uint16_t)0x0200)

Start Of Frame

Definition at line 5762 of file stm32f10x.h.

#define USB_ISTR_SUSP ((uint16_t)0x0800)

Suspend mode request

Definition at line 5764 of file stm32f10x.h.

#define USB_ISTR_WKUP ((uint16_t)0x1000)

Wake up

Definition at line 5765 of file stm32f10x.h.

#define WWDG_CFR_EWI ((uint16_t)0x0200)

Early Wakeup Interrupt

Definition at line 4573 of file stm32f10x.h.

#define WWDG_CFR_W ((uint16_t)0x007F)

W[6:0] bits (7-bit window value)

Definition at line 4560 of file stm32f10x.h.

#define WWDG_CFR_W0 ((uint16_t)0x0001)

Bit 0

Definition at line 4561 of file stm32f10x.h.

#define WWDG_CFR_W1 ((uint16_t)0x0002)

Bit 1

Definition at line 4562 of file stm32f10x.h.

#define WWDG_CFR_W2 ((uint16_t)0x0004)

Bit 2

Definition at line 4563 of file stm32f10x.h.

#define WWDG_CFR_W3 ((uint16_t)0x0008)

Bit 3

Definition at line 4564 of file stm32f10x.h.

#define WWDG_CFR_W4 ((uint16_t)0x0010)

Bit 4

Definition at line 4565 of file stm32f10x.h.

#define WWDG_CFR_W5 ((uint16_t)0x0020)

Bit 5

Definition at line 4566 of file stm32f10x.h.

#define WWDG_CFR_W6 ((uint16_t)0x0040)

Bit 6

Definition at line 4567 of file stm32f10x.h.

#define WWDG_CFR_WDGTB ((uint16_t)0x0180)

WDGTB[1:0] bits (Timer Base)

Definition at line 4569 of file stm32f10x.h.

#define WWDG_CFR_WDGTB0 ((uint16_t)0x0080)

Bit 0

Definition at line 4570 of file stm32f10x.h.

#define WWDG_CFR_WDGTB1 ((uint16_t)0x0100)

Bit 1

Definition at line 4571 of file stm32f10x.h.

#define WWDG_CR_T ((uint8_t)0x7F)

T[6:0] bits (7-Bit counter (MSB to LSB))

Definition at line 4548 of file stm32f10x.h.

#define WWDG_CR_T0 ((uint8_t)0x01)

Bit 0

Definition at line 4549 of file stm32f10x.h.

#define WWDG_CR_T1 ((uint8_t)0x02)

Bit 1

Definition at line 4550 of file stm32f10x.h.

#define WWDG_CR_T2 ((uint8_t)0x04)

Bit 2

Definition at line 4551 of file stm32f10x.h.

#define WWDG_CR_T3 ((uint8_t)0x08)

Bit 3

Definition at line 4552 of file stm32f10x.h.

#define WWDG_CR_T4 ((uint8_t)0x10)

Bit 4

Definition at line 4553 of file stm32f10x.h.

#define WWDG_CR_T5 ((uint8_t)0x20)

Bit 5

Definition at line 4554 of file stm32f10x.h.

#define WWDG_CR_T6 ((uint8_t)0x40)

Bit 6

Definition at line 4555 of file stm32f10x.h.

#define WWDG_CR_WDGA ((uint8_t)0x80)

Activation bit

Definition at line 4557 of file stm32f10x.h.

#define WWDG_SR_EWIF ((uint8_t)0x01)

Early Wakeup Interrupt Flag

Definition at line 4576 of file stm32f10x.h.


STM32F10x Standard Peripherals Firmware Library: Exported_macro

Defines

Exported_macro

Stm32f10x

Defines

#define | CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
#define | CLEAR_REG(REG) ((REG) = (0x0))
#define | MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
#define | READ_BIT(REG, BIT) ((REG) & (BIT))
#define | READ_REG(REG) ((REG))
#define | SET_BIT(REG, BIT) ((REG) |= (BIT))
#define | WRITE_REG(REG, VAL) ((REG) = (VAL))

Define Documentation

#define CLEAR_BIT | ( | REG,
 |  | BIT
 | ) | ((REG) &= ~(BIT))

Definition at line 8306 of file stm32f10x.h.

#define CLEAR_REG ( REG ) ((REG) = (0x0))

Definition at line 8310 of file stm32f10x.h.

#define MODIFY_REG | ( | REG,
 |  | CLEARMASK,
 |  | SETMASK
 | ) | WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))

Definition at line 8316 of file stm32f10x.h.

#define READ_BIT | ( | REG,
 |  | BIT
 | ) | ((REG) & (BIT))

Definition at line 8308 of file stm32f10x.h.

#define READ_REG ( REG ) ((REG))

Definition at line 8314 of file stm32f10x.h.

#define SET_BIT | ( | REG,
 |  | BIT
 | ) | ((REG) |= (BIT))

Definition at line 8304 of file stm32f10x.h.

#define WRITE_REG | ( | REG,
 |  | VAL
 | ) | ((REG) = (VAL))

Definition at line 8312 of file stm32f10x.h.


STM32F10x Standard Peripherals Firmware Library: STM32F10x_System_Private_Includes

STM32F10x_System_Private_Includes

Stm32f10x_system


STM32F10x Standard Peripherals Firmware Library: STM32F10x_System_Private_TypesDefinitions

STM32F10x_System_Private_TypesDefinitions

Stm32f10x_system


STM32F10x Standard Peripherals Firmware Library: STM32F10x_System_Private_Defines

Defines

STM32F10x_System_Private_Defines

Stm32f10x_system

Defines

#define | SYSCLK_FREQ_56MHz 56000000
#define | SYSCLK_FREQ_56MHz 56000000
#define | SYSCLK_FREQ_56MHz 56000000
#define | SYSCLK_FREQ_56MHz 56000000
#define | SYSCLK_FREQ_56MHz 56000000
#define | SYSCLK_FREQ_56MHz 56000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x0
#define | VECT_TAB_OFFSET 0x3000
#define | VECT_TAB_OFFSET 0x0

Define Documentation

#define SYSCLK_FREQ_56MHz 56000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly.

Definition at line 114 of file Project/STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/system_stm32f10x.c.

#define SYSCLK_FREQ_56MHz 56000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly.

Definition at line 114 of file Project/STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/system_stm32f10x.c.

#define SYSCLK_FREQ_56MHz 56000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly.

Definition at line 114 of file Project/STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/system_stm32f10x.c.

#define SYSCLK_FREQ_56MHz 56000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly.

Definition at line 114 of file Project/STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/system_stm32f10x.c.

#define SYSCLK_FREQ_56MHz 56000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly.

Definition at line 114 of file Project/STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/system_stm32f10x.c.

#define SYSCLK_FREQ_56MHz 56000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly.

Definition at line 114 of file Project/STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/BKP/Tamper/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/TIM/DMA/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/FSMC/OneNAND/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/TIM/DMABurst/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/TIM/InputCapture/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/TIM/OCActive/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/CAN/DualCAN/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/TIM/OCInactive/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/TIM/OCToggle/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/GPIO/IOToggle/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/TIM/OnePulse/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Input/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Output/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/I2C/EEPROM/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/CAN/LoopBack/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/I2C/IOExpander/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/TIM/TimeBase/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/I2S/Interrupt/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/USART/DMA_Polling/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/USART/HalfDuplex/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/CAN/Networking/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/USART/Interrupt/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/USART/MultiProcessor/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/DMA/FSMC/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/USART/Polling/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/USART/Printf/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/USART/Smartcard/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/USART/Synchronous/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/TIM/6Steps/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Template/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/PWR/PVD/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/PWR/STANDBY/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/CortexM3/BitBand/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/PWR/STOP/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/RTC/Calendar/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/FLASH/Program/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/SDIO/uSDCard/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/SPI/CRC/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/SPI/DMA/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/BKP/Backup_Data/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/FSMC/NAND/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/CortexM3/MPU/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/SysTick/TimeBase/system_stm32f10x.c.

#define SYSCLK_FREQ_72MHz 72000000

< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source)

IMPORTANT NOTE: ============== 1. After each device reset the HSI is used as System clock source.

2. Please make sure that the selected System clock doesn't exceed your device's maximum frequency.

3. If none of the define below is enabled, the HSI is used as System clock source.

4. The System clock configuration functions provided within this file assume that:

  • For Low, Medium and High density Value line devices an external 8MHz crystal is used to drive the System clock.
  • For Low, Medium and High density devices an external 8MHz crystal is used to drive the System clock.
  • For Connectivity line devices an external 25MHz crystal is used to drive the System clock. If you are using different crystal you have to adapt those functions accordingly. Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory Uncomment the following line if you need to relocate your vector Table in Internal SRAM.

Definition at line 115 of file Project/STM32F10x_StdPeriph_Examples/FSMC/NOR/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/CAN/Networking/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/USART/Synchronous/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/TIM/DMABurst/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/FSMC/OneNAND/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/TIM/OCActive/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/TIM/OCToggle/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/GPIO/IOToggle/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Output/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

< Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory

< Uncomment the following line if you need to relocate your vector Table in Internal SRAM. Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/DMA/FSMC/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/CAN/DualCAN/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/USART/DMA_Polling/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

< Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory

< Uncomment the following line if you need to relocate your vector Table in Internal SRAM. Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/USART/Interrupt/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/CAN/LoopBack/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/USART/Polling/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/USART/Smartcard/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Template/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/PWR/STANDBY/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

< Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory

< Uncomment the following line if you need to relocate your vector Table in Internal SRAM. Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/SDIO/uSDCard/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/CortexM3/BitBand/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

< Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory

< Uncomment the following line if you need to relocate your vector Table in Internal SRAM. Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/SysTick/TimeBase/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/TIM/6Steps/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/CortexM3/MPU/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/TIM/DMA/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

< Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory

< Uncomment the following line if you need to relocate your vector Table in Internal SRAM. Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/TIM/OCInactive/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/BKP/Tamper/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Input/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/I2C/EEPROM/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/TIM/TimeBase/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/I2C/IOExpander/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/I2S/Interrupt/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/USART/MultiProcessor/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/USART/Printf/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.c.

Referenced by SystemInit().

#define VECT_TAB_OFFSET 0x0

< Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density and XL-density devices) or on STM32100E-EVAL board (STM32 High-density value line devices) as data memory

< Uncomment the following line if you need to relocate your vector Table in Internal SRAM. Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/PWR/STOP/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/RTC/Calendar/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/SPI/DMA/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/FSMC/NAND/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/FSMC/NOR/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/BKP/Backup_Data/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/TIM/InputCapture/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/TIM/OnePulse/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/USART/HalfDuplex/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/PWR/PVD/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/FLASH/Program/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/SPI/CRC/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x3000

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/system_stm32f10x.c.

#define VECT_TAB_OFFSET 0x0

Vector Table base offset field. This value must be a multiple of 0x200.

Definition at line 128 of file Project/STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: STM32F10x_System_Private_Macros

STM32F10x_System_Private_Macros

Stm32f10x_system


STM32F10x Standard Peripherals Firmware Library: STM32F10x_System_Private_Variables

Variables

STM32F10x_System_Private_Variables

Stm32f10x_system

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = SYSCLK_FREQ_56MHz
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = SYSCLK_FREQ_72MHz
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE
uint32_t | SystemCoreClock = HSI_VALUE

Variable Documentation

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.c.

Referenced by SystemCoreClockUpdate().

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/BKP/Backup_Data/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/CortexM3/MPU/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/FSMC/NOR/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/TIM/6Steps/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/TIM/DMA/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/TIM/DMABurst/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/FSMC/OneNAND/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/TIM/InputCapture/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/BKP/Tamper/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/TIM/OCActive/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/TIM/OCInactive/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/TIM/OCToggle/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/TIM/OnePulse/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/GPIO/IOToggle/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Input/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Output/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/CAN/DualCAN/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/I2C/EEPROM/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/TIM/TimeBase/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/I2C/IOExpander/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/USART/DMA_Polling/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/I2S/Interrupt/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/USART/HalfDuplex/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/CAN/LoopBack/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/USART/Interrupt/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/USART/MultiProcessor/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/USART/Polling/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/USART/Printf/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/USART/Smartcard/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/CAN/Networking/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/DMA/FSMC/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/USART/Synchronous/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Template/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/PWR/PVD/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/PWR/STANDBY/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/PWR/STOP/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/RTC/Calendar/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/CortexM3/BitBand/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/SDIO/uSDCard/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/FLASH/Program/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/SPI/CRC/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/SPI/DMA/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/FSMC/NAND/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/system_stm32f10x.c.

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}

Definition at line 167 of file Project/STM32F10x_StdPeriph_Examples/SysTick/TimeBase/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/TIM/OCActive/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/TIM/OCToggle/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/TIM/OnePulse/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/GPIO/IOToggle/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Output/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/I2C/EEPROM/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/TIM/TimeBase/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/I2S/Interrupt/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/USART/HalfDuplex/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/USART/Interrupt/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/USART/Polling/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/DMA/FSMC/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/USART/Smartcard/system_stm32f10x.c.

uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz

System Clock Frequency (Core Clock)

Definition at line 160 of file Project/STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Template/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/PWR/STOP/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/CortexM3/BitBand/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/FLASH/Program/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/SPI/CRC/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/BKP/Backup_Data/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/FSMC/NAND/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/FSMC/NOR/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/TIM/6Steps/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/FSMC/OneNAND/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/TIM/InputCapture/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/TIM/OCInactive/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Input/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/USART/DMA_Polling/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/CAN/Networking/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/USART/Printf/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/USART/Synchronous/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/PWR/STANDBY/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/SDIO/uSDCard/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/SysTick/TimeBase/system_stm32f10x.c.

uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz

System Clock Frequency (Core Clock)

Definition at line 162 of file Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.c.

Referenced by main(), SystemCoreClockUpdate(), SysTick_Configuration(), TIM3_IRQHandler(), TIM5_IRQHandler(), and TIM_Config().

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/TIM/DMABurst/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/CAN/DualCAN/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/CAN/LoopBack/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/USART/MultiProcessor/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/RTC/Calendar/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/SPI/DMA/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/CortexM3/MPU/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/BKP/Tamper/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/PWR/PVD/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/TIM/DMA/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/I2C/IOExpander/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/system_stm32f10x.c.

uint32_t SystemCoreClock = HSI_VALUE

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 164 of file Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: STM32F10x_System_Private_FunctionPrototypes

STM32F10x_System_Private_FunctionPrototypes

Stm32f10x_system


STM32F10x Standard Peripherals Firmware Library: STM32F10x_System_Private_Functions

Functions

STM32F10x_System_Private_Functions

Stm32f10x_system

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClockTo56 (void)
Setup the external memory controller.
static void | SetSysClockTo72 (void)
Setup the external memory controller.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Function Documentation

static void SetSysClock ( void ) [static]

Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.

Parameters:
None
Return values:
None

Definition at line 419 of file Project/STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/system_stm32f10x.c.

References SetSysClockTo24(), SetSysClockTo36(), SetSysClockTo48(), SetSysClockTo56(), SetSysClockTo72(), and SetSysClockToHSE().

static void SetSysClockTo56 ( void ) [static]

Setup the external memory controller.

Called in startup_stm32f10x.s before jump to __main

Parameters:
None
Return values:
None Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
Note:
This function should be used only after reset.
Parameters:
None
Return values:
None

Definition at line 885 of file Project/STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/system_stm32f10x.c.

References FLASH, FLASH_ACR_LATENCY, FLASH_ACR_LATENCY_2, FLASH_ACR_PRFTBE, HSE_STARTUP_TIMEOUT, RCC, RCC_CFGR_HPRE_DIV1, RCC_CFGR_PLLMULL, RCC_CFGR_PLLMULL7, RCC_CFGR_PLLSRC, RCC_CFGR_PLLSRC_HSE, RCC_CFGR_PLLXTPRE, RCC_CFGR_PPRE1_DIV2, RCC_CFGR_PPRE2_DIV1, RCC_CFGR_SW, RCC_CFGR_SW_PLL, RCC_CFGR_SWS, RCC_CR_HSEON, RCC_CR_HSERDY, RCC_CR_PLLON, RCC_CR_PLLRDY, and RESET.

Referenced by SetSysClock().

static void SetSysClockTo72 ( void ) [static]

Setup the external memory controller.

Called in startup_stm32f10x.s before jump to __main

Parameters:
None
Return values:
None Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
Note:
This function should be used only after reset.
Parameters:
None
Return values:
None

Definition at line 987 of file Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.c.

References FLASH, FLASH_ACR_LATENCY, FLASH_ACR_LATENCY_2, FLASH_ACR_PRFTBE, HSE_STARTUP_TIMEOUT, RCC, RCC_CFGR_HPRE_DIV1, RCC_CFGR_PLLMULL, RCC_CFGR_PLLMULL9, RCC_CFGR_PLLSRC, RCC_CFGR_PLLSRC_HSE, RCC_CFGR_PLLXTPRE, RCC_CFGR_PPRE1_DIV2, RCC_CFGR_PPRE2_DIV1, RCC_CFGR_SW, RCC_CFGR_SW_PLL, RCC_CFGR_SWS, RCC_CR_HSEON, RCC_CR_HSERDY, RCC_CR_PLLON, RCC_CR_PLLRDY, and RESET.

Referenced by SetSysClock().

void SystemCoreClockUpdate ( void )

Update SystemCoreClock variable according to Clock Register Values.

The SystemCoreClock variable contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.

Note:
Each time the core clock (HCLK) changes, this function must be called to update SystemCoreClock variable value. Otherwise, any configuration based on this variable will be incorrect.
- The system frequency computed by this function is not the real frequency in the chip. It is calculated based on the predefined constant and the selected clock source:
  • If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
  • If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
  • If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) or HSI_VALUE(*) multiplied by the PLL factors.

(*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value 8 MHz) but the real value may vary depending on the variations in voltage and temperature.

(**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value 8 MHz or 25 MHz, depedning on the product used), user has to ensure that HSE_VALUE is same as the real frequency of the crystal used. Otherwise, this function may have wrong result.

  • The result of this function could be not correct when using fractional value for HSE crystal.
    Parameters:
    None
    Return values:
    None

Definition at line 306 of file Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.c.

References AHBPrescTable, HSE_VALUE, HSI_VALUE, RCC, RCC_CFGR_HPRE, RCC_CFGR_PLLMULL, RCC_CFGR_PLLSRC, RCC_CFGR_PLLXTPRE, RCC_CFGR_SWS, RESET, and SystemCoreClock.

void SystemInit ( void )

Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Note:
This function should be used only after reset.
Parameters:
None
Return values:
None

Definition at line 212 of file Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.c.

References FLASH_BASE, RCC, SetSysClock(), SRAM_BASE, and VECT_TAB_OFFSET.


STM32F10x Standard Peripherals Firmware Library: STM32F10x_System_Includes

STM32F10x_System_Includes

Stm32f10x_system

Define to prevent recursive inclusion. More...

Define to prevent recursive inclusion.


STM32F10x Standard Peripherals Firmware Library: STM32F10x_System_Exported_types

Variables

STM32F10x_System_Exported_types

Stm32f10x_system

Variables

uint32_t SystemCoreClock

Variable Documentation

uint32_t SystemCoreClock

System Clock Frequency (Core Clock)

< HSI Selected as System Clock source System Clock Frequency (Core Clock)

Definition at line 162 of file Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.c.

Referenced by main(), SystemCoreClockUpdate(), SysTick_Configuration(), TIM3_IRQHandler(), TIM5_IRQHandler(), and TIM_Config().


STM32F10x Standard Peripherals Firmware Library: STM32F10x_System_Exported_Constants

STM32F10x_System_Exported_Constants

Stm32f10x_system


STM32F10x Standard Peripherals Firmware Library: STM32F10x_System_Exported_Macros

STM32F10x_System_Exported_Macros

Stm32f10x_system


STM32F10x Standard Peripherals Firmware Library: STM32F10x_System_Exported_Functions

Functions

STM32F10x_System_Exported_Functions

Stm32f10x_system

Functions

void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Function Documentation

void SystemCoreClockUpdate ( void )

Update SystemCoreClock variable according to Clock Register Values.

The SystemCoreClock variable contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.

Note:
Each time the core clock (HCLK) changes, this function must be called to update SystemCoreClock variable value. Otherwise, any configuration based on this variable will be incorrect.
- The system frequency computed by this function is not the real frequency in the chip. It is calculated based on the predefined constant and the selected clock source:
  • If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
  • If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
  • If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) or HSI_VALUE(*) multiplied by the PLL factors.

(*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value 8 MHz) but the real value may vary depending on the variations in voltage and temperature.

(**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value 8 MHz or 25 MHz, depedning on the product used), user has to ensure that HSE_VALUE is same as the real frequency of the crystal used. Otherwise, this function may have wrong result.

  • The result of this function could be not correct when using fractional value for HSE crystal.
    Parameters:
    None
    Return values:
    None

Definition at line 306 of file Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.c.

References AHBPrescTable, HSE_VALUE, HSI_VALUE, RCC, RCC_CFGR_HPRE, RCC_CFGR_PLLMULL, RCC_CFGR_PLLSRC, RCC_CFGR_PLLXTPRE, RCC_CFGR_SWS, RESET, and SystemCoreClock.

void SystemInit ( void )

Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Note:
This function should be used only after reset.
Parameters:
None
Return values:
None

Definition at line 212 of file Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.c.

References FLASH_BASE, RCC, SetSysClock(), SRAM_BASE, and VECT_TAB_OFFSET.


STM32F10x Standard Peripherals Firmware Library: NVIC_InitTypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

NVIC_InitTypeDef Struct Reference
MISC_Exported_Types

NVIC Init Structure definition. More...

#include <misc.h>

Data Fields

uint8_t | NVIC_IRQChannel
FunctionalState NVIC_IRQChannelCmd
uint8_t | NVIC_IRQChannelPreemptionPriority
uint8_t | NVIC_IRQChannelSubPriority

Detailed Description

NVIC Init Structure definition.

Definition at line 50 of file misc.h.

Field Documentation

uint8_t NVIC_InitTypeDef::NVIC_IRQChannel

Specifies the IRQ channel to be enabled or disabled. This parameter can be a value of IRQn_Type (For the complete STM32 Devices IRQ Channels list, please refer to stm32f10x.h file)

Definition at line 52 of file misc.h.

Referenced by EXTI0_Config(), EXTI9_5_Config(), EXTI9_5_IRQHandler(), IOE_EXTI_Config(), main(), NVIC_Config(), NVIC_Configuration(), NVIC_Init(), sEE_LowLevel_DeInit(), sEE_LowLevel_Init(), STM_EVAL_PBInit(), TIM5_ConfigForLSI(), and TIM_Config().

FunctionalState NVIC_InitTypeDef::NVIC_IRQChannelCmd

Specifies whether the IRQ channel defined in NVIC_IRQChannel will be enabled or disabled. This parameter can be set either to ENABLE or DISABLE

Definition at line 65 of file misc.h.

Referenced by EXTI0_Config(), EXTI9_5_Config(), EXTI9_5_IRQHandler(), IOE_EXTI_Config(), main(), NVIC_Config(), NVIC_Configuration(), NVIC_Init(), sEE_LowLevel_DeInit(), sEE_LowLevel_Init(), STM_EVAL_PBInit(), TIM5_ConfigForLSI(), and TIM_Config().

uint8_t NVIC_InitTypeDef::NVIC_IRQChannelPreemptionPriority

Specifies the pre-emption priority for the IRQ channel specified in NVIC_IRQChannel. This parameter can be a value between 0 and 15 as described in the table NVIC_Priority_Table

Definition at line 57 of file misc.h.

Referenced by EXTI0_Config(), EXTI9_5_Config(), EXTI9_5_IRQHandler(), IOE_EXTI_Config(), main(), NVIC_Config(), NVIC_Configuration(), NVIC_Init(), sEE_LowLevel_DeInit(), sEE_LowLevel_Init(), STM_EVAL_PBInit(), TIM5_ConfigForLSI(), and TIM_Config().

uint8_t NVIC_InitTypeDef::NVIC_IRQChannelSubPriority

Specifies the subpriority level for the IRQ channel specified in NVIC_IRQChannel. This parameter can be a value between 0 and 15 as described in the table NVIC_Priority_Table

Definition at line 61 of file misc.h.

Referenced by EXTI0_Config(), EXTI9_5_Config(), EXTI9_5_IRQHandler(), IOE_EXTI_Config(), main(), NVIC_Config(), NVIC_Configuration(), NVIC_Init(), sEE_LowLevel_DeInit(), sEE_LowLevel_Init(), STM_EVAL_PBInit(), TIM5_ConfigForLSI(), and TIM_Config().

The documentation for this struct was generated from the following file:
  • misc.h


STM32F10x Standard Peripherals Firmware Library: NVIC_Priority_Table

NVIC_Priority_Table

MISC


STM32F10x Standard Peripherals Firmware Library: Vector_Table_Base

Defines

Vector_Table_Base

MISC_Exported_Constants

Defines

#define | IS_NVIC_VECTTAB(VECTTAB)
#define | NVIC_VectTab_FLASH ((uint32_t)0x08000000)
#define | NVIC_VectTab_RAM ((uint32_t)0x20000000)

Define Documentation

#define IS_NVIC_VECTTAB ( VECTTAB )
Value:
(((VECTTAB) == NVIC_VectTab_RAM) || \
                                  ((VECTTAB) == NVIC_VectTab_FLASH))

Definition at line 117 of file misc.h.

Referenced by NVIC_SetVectorTable().

#define NVIC_VectTab_FLASH ((uint32_t)0x08000000)

Definition at line 116 of file misc.h.

Referenced by main().

#define NVIC_VectTab_RAM ((uint32_t)0x20000000)

Definition at line 115 of file misc.h.


STM32F10x Standard Peripherals Firmware Library: System_Low_Power

Defines

System_Low_Power

MISC_Exported_Constants

Defines

#define | IS_NVIC_LP(LP)
#define | NVIC_LP_SEVONPEND ((uint8_t)0x10)
#define | NVIC_LP_SLEEPDEEP ((uint8_t)0x04)
#define | NVIC_LP_SLEEPONEXIT ((uint8_t)0x02)

Define Documentation

#define IS_NVIC_LP ( LP )
Value:
(((LP) == NVIC_LP_SEVONPEND) || \
                        ((LP) == NVIC_LP_SLEEPDEEP) || \
                        ((LP) == NVIC_LP_SLEEPONEXIT))

Definition at line 130 of file misc.h.

Referenced by NVIC_SystemLPConfig().

#define NVIC_LP_SEVONPEND ((uint8_t)0x10)

Definition at line 127 of file misc.h.

#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04)

Definition at line 128 of file misc.h.

#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02)

Definition at line 129 of file misc.h.


STM32F10x Standard Peripherals Firmware Library: Preemption_Priority_Group

Defines

Preemption_Priority_Group

MISC_Exported_Constants

Defines

#define | IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF)
#define | IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
#define | IS_NVIC_PRIORITY_GROUP(GROUP)
#define | IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
#define | NVIC_PriorityGroup_0 ((uint32_t)0x700)
#define | NVIC_PriorityGroup_1 ((uint32_t)0x600)
#define | NVIC_PriorityGroup_2 ((uint32_t)0x500)
#define | NVIC_PriorityGroup_3 ((uint32_t)0x400)
#define | NVIC_PriorityGroup_4 ((uint32_t)0x300)

Define Documentation

#define IS_NVIC_OFFSET ( OFFSET ) ((OFFSET) < 0x000FFFFF)

Definition at line 162 of file misc.h.

Referenced by NVIC_SetVectorTable().

#define IS_NVIC_PREEMPTION_PRIORITY ( PRIORITY ) ((PRIORITY) < 0x10)

Definition at line 158 of file misc.h.

Referenced by NVIC_Init().

#define IS_NVIC_PRIORITY_GROUP ( GROUP )
Value:
(((GROUP) == NVIC_PriorityGroup_0) || \
                                       ((GROUP) == NVIC_PriorityGroup_1) || \
                                       ((GROUP) == NVIC_PriorityGroup_2) || \
                                       ((GROUP) == NVIC_PriorityGroup_3) || \
                                       ((GROUP) == NVIC_PriorityGroup_4))

Definition at line 152 of file misc.h.

Referenced by NVIC_PriorityGroupConfig().

#define IS_NVIC_SUB_PRIORITY ( PRIORITY ) ((PRIORITY) < 0x10)

Definition at line 160 of file misc.h.

Referenced by NVIC_Init().

#define NVIC_PriorityGroup_0 ((uint32_t)0x700)

0 bits for pre-emption priority 4 bits for subpriority

Definition at line 141 of file misc.h.

#define NVIC_PriorityGroup_1 ((uint32_t)0x600)

1 bits for pre-emption priority 3 bits for subpriority

Definition at line 143 of file misc.h.

Referenced by main(), and NVIC_Config().

#define NVIC_PriorityGroup_2 ((uint32_t)0x500)

2 bits for pre-emption priority 2 bits for subpriority

Definition at line 145 of file misc.h.

Referenced by TIM_Config().

#define NVIC_PriorityGroup_3 ((uint32_t)0x400)

3 bits for pre-emption priority 1 bits for subpriority

Definition at line 147 of file misc.h.

#define NVIC_PriorityGroup_4 ((uint32_t)0x300)

4 bits for pre-emption priority 0 bits for subpriority

Definition at line 149 of file misc.h.


STM32F10x Standard Peripherals Firmware Library: SysTick_clock_source

Defines

SysTick_clock_source

MISC_Exported_Constants

Defines

#define | IS_SYSTICK_CLK_SOURCE(SOURCE)
#define | SysTick_CLKSource_HCLK ((uint32_t)0x00000004)
#define | SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)

Define Documentation

#define IS_SYSTICK_CLK_SOURCE ( SOURCE )
Value:
(((SOURCE) == SysTick_CLKSource_HCLK) || \
                                       ((SOURCE) == SysTick_CLKSource_HCLK_Div8))

Definition at line 174 of file misc.h.

Referenced by SysTick_CLKSourceConfig().

#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004)

Definition at line 173 of file misc.h.

Referenced by SysTick_CLKSourceConfig().

#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)

Definition at line 172 of file misc.h.

Referenced by SysTick_CLKSourceConfig(), and SysTick_Configuration().


STM32F10x Standard Peripherals Firmware Library: MISC_Exported_Macros

MISC_Exported_Macros

MISC


STM32F10x Standard Peripherals Firmware Library: MISC_Exported_Functions

Functions

MISC_Exported_Functions

MISC

Functions

void | NVIC_Init (NVIC_InitTypeDef *NVIC_InitStruct)
Initializes the NVIC peripheral according to the specified parameters in the NVIC_InitStruct.
void | NVIC_PriorityGroupConfig (uint32_t NVIC_PriorityGroup)
Configures the priority grouping: pre-emption priority and subpriority.
void | NVIC_SetVectorTable (uint32_t NVIC_VectTab, uint32_t Offset)
Sets the vector table location and Offset.
void | NVIC_SystemLPConfig (uint8_t LowPowerMode, FunctionalState NewState)
Selects the condition for the system to enter low power mode.
void | SysTick_CLKSourceConfig (uint32_t SysTick_CLKSource)
Configures the SysTick clock source.

Function Documentation

void NVIC_Init ( NVIC_InitTypeDef * NVIC_InitStruct )

Initializes the NVIC peripheral according to the specified parameters in the NVIC_InitStruct.

Parameters:
NVIC_InitStruct,: pointer to a NVIC_InitTypeDef structure that contains the configuration information for the specified NVIC peripheral.
Return values:
None

Definition at line 112 of file misc.c.

References assert_param, DISABLE, IS_FUNCTIONAL_STATE, IS_NVIC_PREEMPTION_PRIORITY, IS_NVIC_SUB_PRIORITY, NVIC_InitTypeDef::NVIC_IRQChannel, NVIC_InitTypeDef::NVIC_IRQChannelCmd, NVIC_InitTypeDef::NVIC_IRQChannelPreemptionPriority, and NVIC_InitTypeDef::NVIC_IRQChannelSubPriority.

Referenced by EXTI0_Config(), EXTI9_5_Config(), EXTI9_5_IRQHandler(), IOE_EXTI_Config(), main(), NVIC_Config(), NVIC_Configuration(), sEE_LowLevel_DeInit(), sEE_LowLevel_Init(), STM_EVAL_PBInit(), TIM5_ConfigForLSI(), and TIM_Config().

void NVIC_PriorityGroupConfig ( uint32_t NVIC_PriorityGroup )

Configures the priority grouping: pre-emption priority and subpriority.

Parameters:
NVIC_PriorityGroup,: specifies the priority grouping bits length. This parameter can be one of the following values:

  • NVIC_PriorityGroup_0: 0 bits for pre-emption priority 4 bits for subpriority
  • NVIC_PriorityGroup_1: 1 bits for pre-emption priority 3 bits for subpriority
  • NVIC_PriorityGroup_2: 2 bits for pre-emption priority 2 bits for subpriority
  • NVIC_PriorityGroup_3: 3 bits for pre-emption priority 1 bits for subpriority
  • NVIC_PriorityGroup_4: 4 bits for pre-emption priority 0 bits for subpriority
Return values:
None

Definition at line 96 of file misc.c.

References AIRCR_VECTKEY_MASK, assert_param, and IS_NVIC_PRIORITY_GROUP.

Referenced by main(), NVIC_Config(), and TIM_Config().

void NVIC_SetVectorTable | ( | uint32_t | NVIC_VectTab,
 |  | uint32_t | Offset
 | ) |  |

Sets the vector table location and Offset.

Parameters:
NVIC_VectTab,: specifies if the vector table is in RAM or FLASH memory. This parameter can be one of the following values:

  • NVIC_VectTab_RAM
  • NVIC_VectTab_FLASH
Offset,: Vector Table base offset field. This value must be a multiple of 0x200.
Return values:
None

Definition at line 156 of file misc.c.

References assert_param, IS_NVIC_OFFSET, and IS_NVIC_VECTTAB.

Referenced by main().

void NVIC_SystemLPConfig | ( | uint8_t | LowPowerMode,
 |  | FunctionalState | NewState
 | ) |  |

Selects the condition for the system to enter low power mode.

Parameters:
LowPowerMode,: Specifies the new mode for the system to enter low power mode. This parameter can be one of the following values:

  • NVIC_LP_SEVONPEND
  • NVIC_LP_SLEEPDEEP
  • NVIC_LP_SLEEPONEXIT
NewState,: new state of LP condition. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 175 of file misc.c.

References assert_param, DISABLE, IS_FUNCTIONAL_STATE, IS_NVIC_LP, and LowPowerMode.

void SysTick_CLKSourceConfig ( uint32_t SysTick_CLKSource )

Configures the SysTick clock source.

Parameters:
SysTick_CLKSource,: specifies the SysTick clock source. This parameter can be one of the following values:

  • SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source.
  • SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source.
Return values:
None

Definition at line 199 of file misc.c.

References assert_param, IS_SYSTICK_CLK_SOURCE, SysTick_CLKSource_HCLK, and SysTick_CLKSource_HCLK_Div8.

Referenced by SysTick_Configuration().


STM32F10x Standard Peripherals Firmware Library: MISC_Private_TypesDefinitions

MISC_Private_TypesDefinitions

MISC


STM32F10x Standard Peripherals Firmware Library: MISC_Private_Defines

Defines

MISC_Private_Defines

MISC

Defines

#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)

Define Documentation

#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)

Definition at line 47 of file misc.c.

Referenced by NVIC_PriorityGroupConfig().


STM32F10x Standard Peripherals Firmware Library: MISC_Private_Macros

MISC_Private_Macros

MISC


STM32F10x Standard Peripherals Firmware Library: MISC_Private_Variables

MISC_Private_Variables

MISC


STM32F10x Standard Peripherals Firmware Library: MISC_Private_FunctionPrototypes

MISC_Private_FunctionPrototypes

MISC


STM32F10x Standard Peripherals Firmware Library: MISC_Private_Functions

Functions

MISC_Private_Functions

MISC

Functions

void | NVIC_Init (NVIC_InitTypeDef *NVIC_InitStruct)
Initializes the NVIC peripheral according to the specified parameters in the NVIC_InitStruct.
void | NVIC_PriorityGroupConfig (uint32_t NVIC_PriorityGroup)
Configures the priority grouping: pre-emption priority and subpriority.
void | NVIC_SetVectorTable (uint32_t NVIC_VectTab, uint32_t Offset)
Sets the vector table location and Offset.
void | NVIC_SystemLPConfig (uint8_t LowPowerMode, FunctionalState NewState)
Selects the condition for the system to enter low power mode.
void | SysTick_CLKSourceConfig (uint32_t SysTick_CLKSource)
Configures the SysTick clock source.

Function Documentation

void NVIC_Init ( NVIC_InitTypeDef * NVIC_InitStruct )

Initializes the NVIC peripheral according to the specified parameters in the NVIC_InitStruct.

Parameters:
NVIC_InitStruct,: pointer to a NVIC_InitTypeDef structure that contains the configuration information for the specified NVIC peripheral.
Return values:
None

Definition at line 112 of file misc.c.

References assert_param, DISABLE, IS_FUNCTIONAL_STATE, IS_NVIC_PREEMPTION_PRIORITY, IS_NVIC_SUB_PRIORITY, NVIC_InitTypeDef::NVIC_IRQChannel, NVIC_InitTypeDef::NVIC_IRQChannelCmd, NVIC_InitTypeDef::NVIC_IRQChannelPreemptionPriority, and NVIC_InitTypeDef::NVIC_IRQChannelSubPriority.

Referenced by EXTI0_Config(), EXTI9_5_Config(), EXTI9_5_IRQHandler(), IOE_EXTI_Config(), main(), NVIC_Config(), NVIC_Configuration(), sEE_LowLevel_DeInit(), sEE_LowLevel_Init(), STM_EVAL_PBInit(), TIM5_ConfigForLSI(), and TIM_Config().

void NVIC_PriorityGroupConfig ( uint32_t NVIC_PriorityGroup )

Configures the priority grouping: pre-emption priority and subpriority.

Parameters:
NVIC_PriorityGroup,: specifies the priority grouping bits length. This parameter can be one of the following values:

  • NVIC_PriorityGroup_0: 0 bits for pre-emption priority 4 bits for subpriority
  • NVIC_PriorityGroup_1: 1 bits for pre-emption priority 3 bits for subpriority
  • NVIC_PriorityGroup_2: 2 bits for pre-emption priority 2 bits for subpriority
  • NVIC_PriorityGroup_3: 3 bits for pre-emption priority 1 bits for subpriority
  • NVIC_PriorityGroup_4: 4 bits for pre-emption priority 0 bits for subpriority
Return values:
None

Definition at line 96 of file misc.c.

References AIRCR_VECTKEY_MASK, assert_param, and IS_NVIC_PRIORITY_GROUP.

Referenced by main(), NVIC_Config(), and TIM_Config().

void NVIC_SetVectorTable | ( | uint32_t | NVIC_VectTab,
 |  | uint32_t | Offset
 | ) |  |

Sets the vector table location and Offset.

Parameters:
NVIC_VectTab,: specifies if the vector table is in RAM or FLASH memory. This parameter can be one of the following values:

  • NVIC_VectTab_RAM
  • NVIC_VectTab_FLASH
Offset,: Vector Table base offset field. This value must be a multiple of 0x200.
Return values:
None

Definition at line 156 of file misc.c.

References assert_param, IS_NVIC_OFFSET, and IS_NVIC_VECTTAB.

Referenced by main().

void NVIC_SystemLPConfig | ( | uint8_t | LowPowerMode,
 |  | FunctionalState | NewState
 | ) |  |

Selects the condition for the system to enter low power mode.

Parameters:
LowPowerMode,: Specifies the new mode for the system to enter low power mode. This parameter can be one of the following values:

  • NVIC_LP_SEVONPEND
  • NVIC_LP_SLEEPDEEP
  • NVIC_LP_SLEEPONEXIT
NewState,: new state of LP condition. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 175 of file misc.c.

References assert_param, DISABLE, IS_FUNCTIONAL_STATE, IS_NVIC_LP, and LowPowerMode.

void SysTick_CLKSourceConfig ( uint32_t SysTick_CLKSource )

Configures the SysTick clock source.

Parameters:
SysTick_CLKSource,: specifies the SysTick clock source. This parameter can be one of the following values:

  • SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source.
  • SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source.
Return values:
None

Definition at line 199 of file misc.c.

References assert_param, IS_SYSTICK_CLK_SOURCE, SysTick_CLKSource_HCLK, and SysTick_CLKSource_HCLK_Div8.

Referenced by SysTick_Configuration().


STM32F10x Standard Peripherals Firmware Library: ADC_InitTypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

ADC_InitTypeDef Struct Reference
ADC_Exported_Types

ADC Init structure definition. More...

#include <stm32f10x_adc.h>

Data Fields

FunctionalState ADC_ContinuousConvMode
uint32_t | ADC_DataAlign
uint32_t | ADC_ExternalTrigConv
uint32_t | ADC_Mode
uint8_t | ADC_NbrOfChannel
FunctionalState ADC_ScanConvMode

Detailed Description

ADC Init structure definition.

Definition at line 50 of file stm32f10x_adc.h.

Field Documentation

FunctionalState ADC_InitTypeDef::ADC_ContinuousConvMode

Specifies whether the conversion is performed in Continuous or Single mode. This parameter can be set to ENABLE or DISABLE.

Definition at line 60 of file stm32f10x_adc.h.

Referenced by ADC_Init(), ADC_StructInit(), and main().

uint32_t ADC_InitTypeDef::ADC_DataAlign

Specifies whether the ADC data alignment is left or right. This parameter can be a value of ADC_data_align

Definition at line 68 of file stm32f10x_adc.h.

Referenced by ADC_Init(), ADC_StructInit(), and main().

uint32_t ADC_InitTypeDef::ADC_ExternalTrigConv

Defines the external trigger used to start the analog to digital conversion of regular channels. This parameter can be a value of ADC_external_trigger_sources_for_regular_channels_conversion

Definition at line 64 of file stm32f10x_adc.h.

Referenced by ADC_Init(), ADC_StructInit(), and main().

uint32_t ADC_InitTypeDef::ADC_Mode

Configures the ADC to operate in independent or dual mode. This parameter can be a value of ADC_mode

Definition at line 52 of file stm32f10x_adc.h.

Referenced by ADC_Init(), ADC_StructInit(), and main().

uint8_t ADC_InitTypeDef::ADC_NbrOfChannel

Specifies the number of ADC channels that will be converted using the sequencer for regular channel group. This parameter must range from 1 to 16.

Definition at line 71 of file stm32f10x_adc.h.

Referenced by ADC_Init(), ADC_StructInit(), and main().

FunctionalState ADC_InitTypeDef::ADC_ScanConvMode

Specifies whether the conversion is performed in Scan (multichannels) or Single (one channel) mode. This parameter can be set to ENABLE or DISABLE

Definition at line 56 of file stm32f10x_adc.h.

Referenced by ADC_Init(), ADC_StructInit(), and main().

The documentation for this struct was generated from the following file:
  • stm32f10x_adc.h


STM32F10x Standard Peripherals Firmware Library: ADC_mode

Defines

ADC_mode

ADC_Exported_Constants

Defines

#define | ADC_Mode_AlterTrig ((uint32_t)0x00090000)
#define | ADC_Mode_FastInterl ((uint32_t)0x00070000)
#define | ADC_Mode_Independent ((uint32_t)0x00000000)
#define | ADC_Mode_InjecSimult ((uint32_t)0x00050000)
#define | ADC_Mode_InjecSimult_FastInterl ((uint32_t)0x00030000)
#define | ADC_Mode_InjecSimult_SlowInterl ((uint32_t)0x00040000)
#define | ADC_Mode_RegInjecSimult ((uint32_t)0x00010000)
#define | ADC_Mode_RegSimult ((uint32_t)0x00060000)
#define | ADC_Mode_RegSimult_AlterTrig ((uint32_t)0x00020000)
#define | ADC_Mode_SlowInterl ((uint32_t)0x00080000)
#define | IS_ADC_MODE(MODE)

Define Documentation

#define ADC_Mode_AlterTrig ((uint32_t)0x00090000)

Definition at line 103 of file stm32f10x_adc.h.

#define ADC_Mode_FastInterl ((uint32_t)0x00070000)

Definition at line 101 of file stm32f10x_adc.h.

#define ADC_Mode_Independent ((uint32_t)0x00000000)

Definition at line 94 of file stm32f10x_adc.h.

Referenced by ADC_StructInit(), and main().

#define ADC_Mode_InjecSimult ((uint32_t)0x00050000)

Definition at line 99 of file stm32f10x_adc.h.

#define ADC_Mode_InjecSimult_FastInterl ((uint32_t)0x00030000)

Definition at line 97 of file stm32f10x_adc.h.

#define ADC_Mode_InjecSimult_SlowInterl ((uint32_t)0x00040000)

Definition at line 98 of file stm32f10x_adc.h.

#define ADC_Mode_RegInjecSimult ((uint32_t)0x00010000)

Definition at line 95 of file stm32f10x_adc.h.

#define ADC_Mode_RegSimult ((uint32_t)0x00060000)

Definition at line 100 of file stm32f10x_adc.h.

Referenced by main().

#define ADC_Mode_RegSimult_AlterTrig ((uint32_t)0x00020000)

Definition at line 96 of file stm32f10x_adc.h.

#define ADC_Mode_SlowInterl ((uint32_t)0x00080000)

Definition at line 102 of file stm32f10x_adc.h.

#define IS_ADC_MODE ( MODE )
Value:
(((MODE) == ADC_Mode_Independent) || \
                           ((MODE) == ADC_Mode_RegInjecSimult) || \
                           ((MODE) == ADC_Mode_RegSimult_AlterTrig) || \
                           ((MODE) == ADC_Mode_InjecSimult_FastInterl) || \
                           ((MODE) == ADC_Mode_InjecSimult_SlowInterl) || \
                           ((MODE) == ADC_Mode_InjecSimult) || \
                           ((MODE) == ADC_Mode_RegSimult) || \
                           ((MODE) == ADC_Mode_FastInterl) || \
                           ((MODE) == ADC_Mode_SlowInterl) || \
                           ((MODE) == ADC_Mode_AlterTrig))

Definition at line 105 of file stm32f10x_adc.h.

Referenced by ADC_Init().


STM32F10x Standard Peripherals Firmware Library: ADC_external_trigger_sources_for_regular_channels_conversion

Defines

ADC_external_trigger_sources_for_regular_channels_conversion

ADC_Exported_Constants

Defines

#define | ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO ((uint32_t)0x000C0000)
#define | ADC_ExternalTrigConv_None ((uint32_t)0x000E0000)
#define | ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000)
#define | ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00020000)
#define | ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x00040000)
#define | ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x00060000)
#define | ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x00020000)
#define | ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x00000000)
#define | ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x00080000)
#define | ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x000A0000)
#define | ADC_ExternalTrigConv_T5_CC1 ((uint32_t)0x000A0000)
#define | ADC_ExternalTrigConv_T5_CC3 ((uint32_t)0x000C0000)
#define | ADC_ExternalTrigConv_T8_CC1 ((uint32_t)0x00060000)
#define | ADC_ExternalTrigConv_T8_TRGO ((uint32_t)0x00080000)
#define | IS_ADC_EXT_TRIG(REGTRIG)

Define Documentation

#define ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO ((uint32_t)0x000C0000)

For ADC1 and ADC2

Definition at line 128 of file stm32f10x_adc.h.

Referenced by main().

#define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000)

For ADC1, ADC2 and ADC3

Definition at line 131 of file stm32f10x_adc.h.

Referenced by main().

#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000)

For ADC1 and ADC2

Definition at line 123 of file stm32f10x_adc.h.

Referenced by ADC_StructInit(), and main().

#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00020000)

For ADC1 and ADC2

Definition at line 124 of file stm32f10x_adc.h.

#define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x00040000)

For ADC1, ADC2 and ADC3

Definition at line 130 of file stm32f10x_adc.h.

#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x00060000)

For ADC1 and ADC2

Definition at line 125 of file stm32f10x_adc.h.

#define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x00020000)

For ADC3 only

Definition at line 134 of file stm32f10x_adc.h.

#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x00000000)

For ADC3 only

Definition at line 133 of file stm32f10x_adc.h.

#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x00080000)

For ADC1 and ADC2

Definition at line 126 of file stm32f10x_adc.h.

#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x000A0000)

For ADC1 and ADC2

Definition at line 127 of file stm32f10x_adc.h.

#define ADC_ExternalTrigConv_T5_CC1 ((uint32_t)0x000A0000)

For ADC3 only

Definition at line 137 of file stm32f10x_adc.h.

#define ADC_ExternalTrigConv_T5_CC3 ((uint32_t)0x000C0000)

For ADC3 only

Definition at line 138 of file stm32f10x_adc.h.

#define ADC_ExternalTrigConv_T8_CC1 ((uint32_t)0x00060000)

For ADC3 only

Definition at line 135 of file stm32f10x_adc.h.

#define ADC_ExternalTrigConv_T8_TRGO ((uint32_t)0x00080000)

For ADC3 only

Definition at line 136 of file stm32f10x_adc.h.

#define IS_ADC_EXT_TRIG ( REGTRIG )
Value:
(((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \
                                  ((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \
                                  ((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || \
                                  ((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \
                                  ((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \
                                  ((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \
                                  ((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO) || \
                                  ((REGTRIG) == ADC_ExternalTrigConv_None) || \
                                  ((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \
                                  ((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \
                                  ((REGTRIG) == ADC_ExternalTrigConv_T8_CC1) || \
                                  ((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO) || \
                                  ((REGTRIG) == ADC_ExternalTrigConv_T5_CC1) || \
                                  ((REGTRIG) == ADC_ExternalTrigConv_T5_CC3))

Definition at line 140 of file stm32f10x_adc.h.

Referenced by ADC_Init().


STM32F10x Standard Peripherals Firmware Library: ADC_data_align

Defines

ADC_data_align

ADC_Exported_Constants

Defines

#define | ADC_DataAlign_Left ((uint32_t)0x00000800)
#define | ADC_DataAlign_Right ((uint32_t)0x00000000)
#define | IS_ADC_DATA_ALIGN(ALIGN)

Define Documentation

#define ADC_DataAlign_Left ((uint32_t)0x00000800)

Definition at line 163 of file stm32f10x_adc.h.

#define ADC_DataAlign_Right ((uint32_t)0x00000000)

Definition at line 162 of file stm32f10x_adc.h.

Referenced by ADC_StructInit(), and main().

#define IS_ADC_DATA_ALIGN ( ALIGN )
Value:
(((ALIGN) == ADC_DataAlign_Right) || \
                                  ((ALIGN) == ADC_DataAlign_Left))

Definition at line 164 of file stm32f10x_adc.h.

Referenced by ADC_Init().


STM32F10x Standard Peripherals Firmware Library: ADC_channels

Defines

ADC_channels

ADC_Exported_Constants

Defines

#define | ADC_Channel_0 ((uint8_t)0x00)
#define | ADC_Channel_1 ((uint8_t)0x01)
#define | ADC_Channel_10 ((uint8_t)0x0A)
#define | ADC_Channel_11 ((uint8_t)0x0B)
#define | ADC_Channel_12 ((uint8_t)0x0C)
#define | ADC_Channel_13 ((uint8_t)0x0D)
#define | ADC_Channel_14 ((uint8_t)0x0E)
#define | ADC_Channel_15 ((uint8_t)0x0F)
#define | ADC_Channel_16 ((uint8_t)0x10)
#define | ADC_Channel_17 ((uint8_t)0x11)
#define | ADC_Channel_2 ((uint8_t)0x02)
#define | ADC_Channel_3 ((uint8_t)0x03)
#define | ADC_Channel_4 ((uint8_t)0x04)
#define | ADC_Channel_5 ((uint8_t)0x05)
#define | ADC_Channel_6 ((uint8_t)0x06)
#define | ADC_Channel_7 ((uint8_t)0x07)
#define | ADC_Channel_8 ((uint8_t)0x08)
#define | ADC_Channel_9 ((uint8_t)0x09)
#define | ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16)
#define | ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17)
#define | IS_ADC_CHANNEL(CHANNEL)

Define Documentation

#define ADC_Channel_0 ((uint8_t)0x00)

Definition at line 174 of file stm32f10x_adc.h.

#define ADC_Channel_1 ((uint8_t)0x01)

Definition at line 175 of file stm32f10x_adc.h.

#define ADC_Channel_10 ((uint8_t)0x0A)

Definition at line 184 of file stm32f10x_adc.h.

#define ADC_Channel_11 ((uint8_t)0x0B)

Definition at line 185 of file stm32f10x_adc.h.

Referenced by main().

#define ADC_Channel_12 ((uint8_t)0x0C)

Definition at line 186 of file stm32f10x_adc.h.

Referenced by main().

#define ADC_Channel_13 ((uint8_t)0x0D)

Definition at line 187 of file stm32f10x_adc.h.

Referenced by main().

#define ADC_Channel_14 ((uint8_t)0x0E)

Definition at line 188 of file stm32f10x_adc.h.

Referenced by main().

#define ADC_Channel_15 ((uint8_t)0x0F)

Definition at line 189 of file stm32f10x_adc.h.

#define ADC_Channel_16 ((uint8_t)0x10)

Definition at line 190 of file stm32f10x_adc.h.

#define ADC_Channel_17 ((uint8_t)0x11)

Definition at line 191 of file stm32f10x_adc.h.

Referenced by main().

#define ADC_Channel_2 ((uint8_t)0x02)

Definition at line 176 of file stm32f10x_adc.h.

#define ADC_Channel_3 ((uint8_t)0x03)

Definition at line 177 of file stm32f10x_adc.h.

#define ADC_Channel_4 ((uint8_t)0x04)

Definition at line 178 of file stm32f10x_adc.h.

Referenced by main().

#define ADC_Channel_5 ((uint8_t)0x05)

Definition at line 179 of file stm32f10x_adc.h.

#define ADC_Channel_6 ((uint8_t)0x06)

Definition at line 180 of file stm32f10x_adc.h.

#define ADC_Channel_7 ((uint8_t)0x07)

Definition at line 181 of file stm32f10x_adc.h.

#define ADC_Channel_8 ((uint8_t)0x08)

Definition at line 182 of file stm32f10x_adc.h.

#define ADC_Channel_9 ((uint8_t)0x09)

Definition at line 183 of file stm32f10x_adc.h.

Referenced by ADC_InjectedChannelConfig(), and ADC_RegularChannelConfig().

#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16)

Definition at line 193 of file stm32f10x_adc.h.

#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17)

Definition at line 194 of file stm32f10x_adc.h.

#define IS_ADC_CHANNEL ( CHANNEL )
Value:
(((CHANNEL) == ADC_Channel_0) || ((CHANNEL) == ADC_Channel_1) || \
                                 ((CHANNEL) == ADC_Channel_2) || ((CHANNEL) == ADC_Channel_3) || \
                                 ((CHANNEL) == ADC_Channel_4) || ((CHANNEL) == ADC_Channel_5) || \
                                 ((CHANNEL) == ADC_Channel_6) || ((CHANNEL) == ADC_Channel_7) || \
                                 ((CHANNEL) == ADC_Channel_8) || ((CHANNEL) == ADC_Channel_9) || \
                                 ((CHANNEL) == ADC_Channel_10) || ((CHANNEL) == ADC_Channel_11) || \
                                 ((CHANNEL) == ADC_Channel_12) || ((CHANNEL) == ADC_Channel_13) || \
                                 ((CHANNEL) == ADC_Channel_14) || ((CHANNEL) == ADC_Channel_15) || \
                                 ((CHANNEL) == ADC_Channel_16) || ((CHANNEL) == ADC_Channel_17))

Definition at line 196 of file stm32f10x_adc.h.

Referenced by ADC_AnalogWatchdogSingleChannelConfig(), ADC_InjectedChannelConfig(), and ADC_RegularChannelConfig().


STM32F10x Standard Peripherals Firmware Library: ADC_sampling_time

Defines

ADC_sampling_time

ADC_Exported_Constants

Defines

#define | ADC_SampleTime_13Cycles5 ((uint8_t)0x02)
#define | ADC_SampleTime_1Cycles5 ((uint8_t)0x00)
#define | ADC_SampleTime_239Cycles5 ((uint8_t)0x07)
#define | ADC_SampleTime_28Cycles5 ((uint8_t)0x03)
#define | ADC_SampleTime_41Cycles5 ((uint8_t)0x04)
#define | ADC_SampleTime_55Cycles5 ((uint8_t)0x05)
#define | ADC_SampleTime_71Cycles5 ((uint8_t)0x06)
#define | ADC_SampleTime_7Cycles5 ((uint8_t)0x01)
#define | IS_ADC_SAMPLE_TIME(TIME)

Define Documentation

#define ADC_SampleTime_13Cycles5 ((uint8_t)0x02)

Definition at line 215 of file stm32f10x_adc.h.

Referenced by main().

#define ADC_SampleTime_1Cycles5 ((uint8_t)0x00)

Definition at line 213 of file stm32f10x_adc.h.

#define ADC_SampleTime_239Cycles5 ((uint8_t)0x07)

Definition at line 220 of file stm32f10x_adc.h.

Referenced by main().

#define ADC_SampleTime_28Cycles5 ((uint8_t)0x03)

Definition at line 216 of file stm32f10x_adc.h.

Referenced by main().

#define ADC_SampleTime_41Cycles5 ((uint8_t)0x04)

Definition at line 217 of file stm32f10x_adc.h.

#define ADC_SampleTime_55Cycles5 ((uint8_t)0x05)

Definition at line 218 of file stm32f10x_adc.h.

Referenced by main().

#define ADC_SampleTime_71Cycles5 ((uint8_t)0x06)

Definition at line 219 of file stm32f10x_adc.h.

Referenced by main().

#define ADC_SampleTime_7Cycles5 ((uint8_t)0x01)

Definition at line 214 of file stm32f10x_adc.h.

#define IS_ADC_SAMPLE_TIME ( TIME )
Value:
(((TIME) == ADC_SampleTime_1Cycles5) || \
                                  ((TIME) == ADC_SampleTime_7Cycles5) || \
                                  ((TIME) == ADC_SampleTime_13Cycles5) || \
                                  ((TIME) == ADC_SampleTime_28Cycles5) || \
                                  ((TIME) == ADC_SampleTime_41Cycles5) || \
                                  ((TIME) == ADC_SampleTime_55Cycles5) || \
                                  ((TIME) == ADC_SampleTime_71Cycles5) || \
                                  ((TIME) == ADC_SampleTime_239Cycles5))

Definition at line 221 of file stm32f10x_adc.h.

Referenced by ADC_InjectedChannelConfig(), and ADC_RegularChannelConfig().


STM32F10x Standard Peripherals Firmware Library: ADC_external_trigger_sources_for_injected_channels_conversion

Defines

ADC_external_trigger_sources_for_injected_channels_conversion

ADC_Exported_Constants

Defines

#define | ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 ((uint32_t)0x00006000)
#define | ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000)
#define | ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00001000)
#define | ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00000000)
#define | ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00003000)
#define | ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00002000)
#define | ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00004000)
#define | ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00002000)
#define | ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00005000)
#define | ADC_ExternalTrigInjecConv_T5_CC4 ((uint32_t)0x00006000)
#define | ADC_ExternalTrigInjecConv_T5_TRGO ((uint32_t)0x00005000)
#define | ADC_ExternalTrigInjecConv_T8_CC2 ((uint32_t)0x00003000)
#define | ADC_ExternalTrigInjecConv_T8_CC4 ((uint32_t)0x00004000)
#define | IS_ADC_EXT_INJEC_TRIG(INJTRIG)

Define Documentation

#define ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 ((uint32_t)0x00006000)

For ADC1 and ADC2

Definition at line 241 of file stm32f10x_adc.h.

Referenced by main().

#define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000)

For ADC1, ADC2 and ADC3

Definition at line 245 of file stm32f10x_adc.h.

Referenced by main().

#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00001000)

For ADC1, ADC2 and ADC3

Definition at line 244 of file stm32f10x_adc.h.

#define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00000000)

For ADC1, ADC2 and ADC3

Definition at line 243 of file stm32f10x_adc.h.

#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00003000)

For ADC1 and ADC2

Definition at line 238 of file stm32f10x_adc.h.

#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00002000)

For ADC1 and ADC2

Definition at line 237 of file stm32f10x_adc.h.

#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00004000)

For ADC1 and ADC2

Definition at line 239 of file stm32f10x_adc.h.

#define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00002000)

For ADC3 only

Definition at line 247 of file stm32f10x_adc.h.

#define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00005000)

For ADC1 and ADC2

Definition at line 240 of file stm32f10x_adc.h.

#define ADC_ExternalTrigInjecConv_T5_CC4 ((uint32_t)0x00006000)

For ADC3 only

Definition at line 251 of file stm32f10x_adc.h.

#define ADC_ExternalTrigInjecConv_T5_TRGO ((uint32_t)0x00005000)

For ADC3 only

Definition at line 250 of file stm32f10x_adc.h.

#define ADC_ExternalTrigInjecConv_T8_CC2 ((uint32_t)0x00003000)

For ADC3 only

Definition at line 248 of file stm32f10x_adc.h.

#define ADC_ExternalTrigInjecConv_T8_CC4 ((uint32_t)0x00004000)

For ADC3 only

Definition at line 249 of file stm32f10x_adc.h.

#define IS_ADC_EXT_INJEC_TRIG ( INJTRIG )
Value:
(((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO) || \
                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T1_CC4) || \
                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \
                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \
                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \
                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \
                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4) || \
                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_None) || \
                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \
                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC2) || \
                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC4) || \
                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO) || \
                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_CC4))

Definition at line 253 of file stm32f10x_adc.h.

Referenced by ADC_ExternalTrigInjectedConvConfig().


STM32F10x Standard Peripherals Firmware Library: ADC_injected_channel_selection

Defines

ADC_injected_channel_selection

ADC_Exported_Constants

Defines

#define | ADC_InjectedChannel_1 ((uint8_t)0x14)
#define | ADC_InjectedChannel_2 ((uint8_t)0x18)
#define | ADC_InjectedChannel_3 ((uint8_t)0x1C)
#define | ADC_InjectedChannel_4 ((uint8_t)0x20)
#define | IS_ADC_INJECTED_CHANNEL(CHANNEL)

Define Documentation

#define ADC_InjectedChannel_1 ((uint8_t)0x14)

Definition at line 274 of file stm32f10x_adc.h.

Referenced by ADC1_2_IRQHandler().

#define ADC_InjectedChannel_2 ((uint8_t)0x18)

Definition at line 275 of file stm32f10x_adc.h.

Referenced by ADC1_2_IRQHandler().

#define ADC_InjectedChannel_3 ((uint8_t)0x1C)

Definition at line 276 of file stm32f10x_adc.h.

#define ADC_InjectedChannel_4 ((uint8_t)0x20)

Definition at line 277 of file stm32f10x_adc.h.

#define IS_ADC_INJECTED_CHANNEL ( CHANNEL )
Value:
(((CHANNEL) == ADC_InjectedChannel_1) || \
                                          ((CHANNEL) == ADC_InjectedChannel_2) || \
                                          ((CHANNEL) == ADC_InjectedChannel_3) || \
                                          ((CHANNEL) == ADC_InjectedChannel_4))

Definition at line 278 of file stm32f10x_adc.h.

Referenced by ADC_GetInjectedConversionValue(), and ADC_SetInjectedOffset().


STM32F10x Standard Peripherals Firmware Library: ADC_analog_watchdog_selection

Defines

ADC_analog_watchdog_selection

ADC_Exported_Constants

Defines

#define | ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000)
#define | ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000)
#define | ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000)
#define | ADC_AnalogWatchdog_None ((uint32_t)0x00000000)
#define | ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200)
#define | ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200)
#define | ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200)
#define | IS_ADC_ANALOG_WATCHDOG(WATCHDOG)

Define Documentation

#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000)

Definition at line 294 of file stm32f10x_adc.h.

#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000)

Definition at line 295 of file stm32f10x_adc.h.

#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000)

Definition at line 293 of file stm32f10x_adc.h.

#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000)

Definition at line 296 of file stm32f10x_adc.h.

#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200)

Definition at line 291 of file stm32f10x_adc.h.

#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200)

Definition at line 290 of file stm32f10x_adc.h.

Referenced by main().

#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200)

Definition at line 292 of file stm32f10x_adc.h.

#define IS_ADC_ANALOG_WATCHDOG ( WATCHDOG )
Value:
(((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \
                                          ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \
                                          ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \
                                          ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \
                                          ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \
                                          ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \
                                          ((WATCHDOG) == ADC_AnalogWatchdog_None))

Definition at line 298 of file stm32f10x_adc.h.

Referenced by ADC_AnalogWatchdogCmd().


STM32F10x Standard Peripherals Firmware Library: ADC_interrupts_definition

Defines

ADC_interrupts_definition

ADC_Exported_Constants

Defines

#define | ADC_IT_AWD ((uint16_t)0x0140)
#define | ADC_IT_EOC ((uint16_t)0x0220)
#define | ADC_IT_JEOC ((uint16_t)0x0480)
#define | IS_ADC_GET_IT(IT)
#define | IS_ADC_IT(IT) ((((IT) & (uint16_t)0xF81F) == 0x00) && ((IT) != 0x00))

Define Documentation

#define ADC_IT_AWD ((uint16_t)0x0140)

Definition at line 314 of file stm32f10x_adc.h.

Referenced by ADC1_2_IRQHandler(), and main().

#define ADC_IT_EOC ((uint16_t)0x0220)

Definition at line 313 of file stm32f10x_adc.h.

Referenced by main().

#define ADC_IT_JEOC ((uint16_t)0x0480)

Definition at line 315 of file stm32f10x_adc.h.

Referenced by ADC1_2_IRQHandler(), and main().

#define IS_ADC_GET_IT ( IT )
Value:
(((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \
                           ((IT) == ADC_IT_JEOC))

Definition at line 319 of file stm32f10x_adc.h.

Referenced by ADC_GetITStatus().

#define IS_ADC_IT ( IT ) ((((IT) & (uint16_t)0xF81F) == 0x00) && ((IT) != 0x00))

Definition at line 317 of file stm32f10x_adc.h.

Referenced by ADC_ClearITPendingBit(), and ADC_ITConfig().


STM32F10x Standard Peripherals Firmware Library: ADC_flags_definition

Defines

ADC_flags_definition

ADC_Exported_Constants

Defines

#define | ADC_FLAG_AWD ((uint8_t)0x01)
#define | ADC_FLAG_EOC ((uint8_t)0x02)
#define | ADC_FLAG_JEOC ((uint8_t)0x04)
#define | ADC_FLAG_JSTRT ((uint8_t)0x08)
#define | ADC_FLAG_STRT ((uint8_t)0x10)
#define | IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint8_t)0xE0) == 0x00) && ((FLAG) != 0x00))
#define | IS_ADC_GET_FLAG(FLAG)

Define Documentation

#define ADC_FLAG_AWD ((uint8_t)0x01)

Definition at line 329 of file stm32f10x_adc.h.

#define ADC_FLAG_EOC ((uint8_t)0x02)

Definition at line 330 of file stm32f10x_adc.h.

#define ADC_FLAG_JEOC ((uint8_t)0x04)

Definition at line 331 of file stm32f10x_adc.h.

#define ADC_FLAG_JSTRT ((uint8_t)0x08)

Definition at line 332 of file stm32f10x_adc.h.

#define ADC_FLAG_STRT ((uint8_t)0x10)

Definition at line 333 of file stm32f10x_adc.h.

#define IS_ADC_CLEAR_FLAG ( FLAG ) ((((FLAG) & (uint8_t)0xE0) == 0x00) && ((FLAG) != 0x00))

Definition at line 334 of file stm32f10x_adc.h.

Referenced by ADC_ClearFlag().

#define IS_ADC_GET_FLAG ( FLAG )
Value:
(((FLAG) == ADC_FLAG_AWD) || ((FLAG) == ADC_FLAG_EOC) || \
                               ((FLAG) == ADC_FLAG_JEOC) || ((FLAG)== ADC_FLAG_JSTRT) || \
                               ((FLAG) == ADC_FLAG_STRT))

Definition at line 335 of file stm32f10x_adc.h.

Referenced by ADC_GetFlagStatus().


STM32F10x Standard Peripherals Firmware Library: ADC_thresholds

Defines

ADC_thresholds

ADC_Exported_Constants

Defines

#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF)

Define Documentation

#define IS_ADC_THRESHOLD ( THRESHOLD ) ((THRESHOLD) <= 0xFFF)

Definition at line 346 of file stm32f10x_adc.h.

Referenced by ADC_AnalogWatchdogThresholdsConfig().


STM32F10x Standard Peripherals Firmware Library: ADC_injected_offset

Defines

ADC_injected_offset

ADC_Exported_Constants

Defines

#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF)

Define Documentation

#define IS_ADC_OFFSET ( OFFSET ) ((OFFSET) <= 0xFFF)

Definition at line 356 of file stm32f10x_adc.h.

Referenced by ADC_SetInjectedOffset().


STM32F10x Standard Peripherals Firmware Library: ADC_injected_length

Defines

ADC_injected_length

ADC_Exported_Constants

Defines

#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4))

Define Documentation

#define IS_ADC_INJECTED_LENGTH ( LENGTH ) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4))

Definition at line 366 of file stm32f10x_adc.h.

Referenced by ADC_InjectedSequencerLengthConfig().


STM32F10x Standard Peripherals Firmware Library: ADC_injected_rank

Defines

ADC_injected_rank

ADC_Exported_Constants

Defines

#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4))

Define Documentation

#define IS_ADC_INJECTED_RANK ( RANK ) (((RANK) >= 0x1) && ((RANK) <= 0x4))

Definition at line 376 of file stm32f10x_adc.h.

Referenced by ADC_InjectedChannelConfig().


STM32F10x Standard Peripherals Firmware Library: ADC_regular_length

Defines

ADC_regular_length

ADC_Exported_Constants

Defines

#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10))

Define Documentation

#define IS_ADC_REGULAR_LENGTH ( LENGTH ) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10))

Definition at line 387 of file stm32f10x_adc.h.

Referenced by ADC_Init().


STM32F10x Standard Peripherals Firmware Library: ADC_regular_rank

Defines

ADC_regular_rank

ADC_Exported_Constants

Defines

#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10))

Define Documentation

#define IS_ADC_REGULAR_RANK ( RANK ) (((RANK) >= 0x1) && ((RANK) <= 0x10))

Definition at line 396 of file stm32f10x_adc.h.

Referenced by ADC_RegularChannelConfig().


STM32F10x Standard Peripherals Firmware Library: ADC_regular_discontinuous_mode_number

Defines

ADC_regular_discontinuous_mode_number

ADC_Exported_Constants

Defines

#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))

Define Documentation

#define IS_ADC_REGULAR_DISC_NUMBER ( NUMBER ) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))

Definition at line 406 of file stm32f10x_adc.h.

Referenced by ADC_DiscModeChannelCountConfig().


STM32F10x Standard Peripherals Firmware Library: ADC_Exported_Constants

Modules | Defines

ADC_Exported_Constants

ADC

Modules

ADC_mode
ADC_external_trigger_sources_for_regular_channels_conversion
ADC_data_align
ADC_channels
ADC_sampling_time
ADC_external_trigger_sources_for_injected_channels_conversion
ADC_injected_channel_selection
ADC_analog_watchdog_selection
ADC_interrupts_definition
ADC_flags_definition
ADC_thresholds
ADC_injected_offset
ADC_injected_length
ADC_injected_rank
ADC_regular_length
ADC_regular_rank
ADC_regular_discontinuous_mode_number

Defines

#define | IS_ADC_ALL_PERIPH(PERIPH)
#define | IS_ADC_DMA_PERIPH(PERIPH)

Define Documentation

#define IS_ADC_ALL_PERIPH ( PERIPH )
Value:
(((PERIPH) == ADC1) || \
                                   ((PERIPH) == ADC2) || \
                                   ((PERIPH) == ADC3))

Definition at line 83 of file stm32f10x_adc.h.

Referenced by ADC_AnalogWatchdogCmd(), ADC_AnalogWatchdogSingleChannelConfig(), ADC_AnalogWatchdogThresholdsConfig(), ADC_AutoInjectedConvCmd(), ADC_ClearFlag(), ADC_ClearITPendingBit(), ADC_Cmd(), ADC_DeInit(), ADC_DiscModeChannelCountConfig(), ADC_DiscModeCmd(), ADC_ExternalTrigConvCmd(), ADC_ExternalTrigInjectedConvCmd(), ADC_ExternalTrigInjectedConvConfig(), ADC_GetCalibrationStatus(), ADC_GetConversionValue(), ADC_GetFlagStatus(), ADC_GetInjectedConversionValue(), ADC_GetITStatus(), ADC_GetResetCalibrationStatus(), ADC_GetSoftwareStartConvStatus(), ADC_GetSoftwareStartInjectedConvCmdStatus(), ADC_Init(), ADC_InjectedChannelConfig(), ADC_InjectedDiscModeCmd(), ADC_InjectedSequencerLengthConfig(), ADC_ITConfig(), ADC_RegularChannelConfig(), ADC_ResetCalibration(), ADC_SetInjectedOffset(), ADC_SoftwareStartConvCmd(), ADC_SoftwareStartInjectedConvCmd(), and ADC_StartCalibration().

#define IS_ADC_DMA_PERIPH ( PERIPH )
Value:
(((PERIPH) == ADC1) || \
                                   ((PERIPH) == ADC3))

Definition at line 87 of file stm32f10x_adc.h.

Referenced by ADC_DMACmd().


STM32F10x Standard Peripherals Firmware Library: ADC_Exported_Macros

ADC_Exported_Macros

ADC


STM32F10x Standard Peripherals Firmware Library: ADC_Exported_Functions

Functions

ADC_Exported_Functions

ADC

Functions

void | ADC_AnalogWatchdogCmd (ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog)
Enables or disables the analog watchdog on single/all regular or injected channels.
void | ADC_AnalogWatchdogSingleChannelConfig (ADC_TypeDef *ADCx, uint8_t ADC_Channel)
Configures the analog watchdog guarded single channel.
void | ADC_AnalogWatchdogThresholdsConfig (ADC_TypeDef *ADCx, uint16_t HighThreshold, uint16_t LowThreshold)
Configures the high and low thresholds of the analog watchdog.
void | ADC_AutoInjectedConvCmd (ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the selected ADC automatic injected group conversion after regular one.
void | ADC_ClearFlag (ADC_TypeDef *ADCx, uint8_t ADC_FLAG)
Clears the ADCx's pending flags.
void | ADC_ClearITPendingBit (ADC_TypeDef *ADCx, uint16_t ADC_IT)
Clears the ADCx's interrupt pending bits.
void | ADC_Cmd (ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the specified ADC peripheral.
void | ADC_DeInit (ADC_TypeDef *ADCx)
Deinitializes the ADCx peripheral registers to their default reset values.
void | ADC_DiscModeChannelCountConfig (ADC_TypeDef *ADCx, uint8_t Number)
Configures the discontinuous mode for the selected ADC regular group channel.
void | ADC_DiscModeCmd (ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the discontinuous mode on regular group channel for the specified ADC.
void | ADC_DMACmd (ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the specified ADC DMA request.
void | ADC_ExternalTrigConvCmd (ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the ADCx conversion through external trigger.
void | ADC_ExternalTrigInjectedConvCmd (ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the ADCx injected channels conversion through external trigger.
void | ADC_ExternalTrigInjectedConvConfig (ADC_TypeDef *ADCx, uint32_t ADC_ExternalTrigInjecConv)
Configures the ADCx external trigger for injected channels conversion.
FlagStatus | ADC_GetCalibrationStatus (ADC_TypeDef *ADCx)
Gets the selected ADC calibration status.
uint16_t | ADC_GetConversionValue (ADC_TypeDef *ADCx)
Returns the last ADCx conversion result data for regular channel.
uint32_t | ADC_GetDualModeConversionValue (void)
Returns the last ADC1 and ADC2 conversion result data in dual mode.
FlagStatus | ADC_GetFlagStatus (ADC_TypeDef *ADCx, uint8_t ADC_FLAG)
Checks whether the specified ADC flag is set or not.
uint16_t | ADC_GetInjectedConversionValue (ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel)
Returns the ADC injected channel conversion result.
ITStatus | ADC_GetITStatus (ADC_TypeDef *ADCx, uint16_t ADC_IT)
Checks whether the specified ADC interrupt has occurred or not.
FlagStatus | ADC_GetResetCalibrationStatus (ADC_TypeDef *ADCx)
Gets the selected ADC reset calibration registers status.
FlagStatus | ADC_GetSoftwareStartConvStatus (ADC_TypeDef *ADCx)
Gets the selected ADC Software start conversion Status.
FlagStatus | ADC_GetSoftwareStartInjectedConvCmdStatus (ADC_TypeDef *ADCx)
Gets the selected ADC Software start injected conversion Status.
void | ADC_Init (ADC_TypeDef *ADCx, ADC_InitTypeDef *ADC_InitStruct)
Initializes the ADCx peripheral according to the specified parameters in the ADC_InitStruct.
void | ADC_InjectedChannelConfig (ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
Configures for the selected ADC injected channel its corresponding rank in the sequencer and its sample time.
void | ADC_InjectedDiscModeCmd (ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the discontinuous mode for injected group channel for the specified ADC.
void | ADC_InjectedSequencerLengthConfig (ADC_TypeDef *ADCx, uint8_t Length)
Configures the sequencer length for injected channels.
void | ADC_ITConfig (ADC_TypeDef *ADCx, uint16_t ADC_IT, FunctionalState NewState)
Enables or disables the specified ADC interrupts.
void | ADC_RegularChannelConfig (ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
Configures for the selected ADC regular channel its corresponding rank in the sequencer and its sample time.
void | ADC_ResetCalibration (ADC_TypeDef *ADCx)
Resets the selected ADC calibration registers.
void | ADC_SetInjectedOffset (ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset)
Set the injected channels conversion value offset.
void | ADC_SoftwareStartConvCmd (ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the selected ADC software start conversion .
void | ADC_SoftwareStartInjectedConvCmd (ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the selected ADC start of the injected channels conversion.
void | ADC_StartCalibration (ADC_TypeDef *ADCx)
Starts the selected ADC calibration process.
void | ADC_StructInit (ADC_InitTypeDef *ADC_InitStruct)
Fills each ADC_InitStruct member with its default value.
void | ADC_TempSensorVrefintCmd (FunctionalState NewState)
Enables or disables the temperature sensor and Vrefint channel.

Function Documentation

void ADC_AnalogWatchdogCmd | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | ADC_AnalogWatchdog
 | ) |  |

Enables or disables the analog watchdog on single/all regular or injected channels.

Parameters:
ADCx,: where x can be 1, 2 or 3 to select the ADC peripheral.
ADC_AnalogWatchdog,: the ADC analog watchdog configuration. This parameter can be one of the following values:

  • ADC_AnalogWatchdog_SingleRegEnable: Analog watchdog on a single regular channel
  • ADC_AnalogWatchdog_SingleInjecEnable: Analog watchdog on a single injected channel
  • ADC_AnalogWatchdog_SingleRegOrInjecEnable: Analog watchdog on a single regular or injected channel
  • ADC_AnalogWatchdog_AllRegEnable: Analog watchdog on all regular channel
  • ADC_AnalogWatchdog_AllInjecEnable: Analog watchdog on all injected channel
  • ADC_AnalogWatchdog_AllRegAllInjecEnable: Analog watchdog on all regular and injected channels
  • ADC_AnalogWatchdog_None: No channel guarded by the analog watchdog
Return values:
None

Definition at line 1082 of file stm32f10x_adc.c.

References assert_param, ADC_TypeDef::CR1, CR1_AWDMode_Reset, IS_ADC_ALL_PERIPH, and IS_ADC_ANALOG_WATCHDOG.

Referenced by main().

void ADC_AnalogWatchdogSingleChannelConfig | ( | ADC_TypeDef * | ADCx,
 |  | uint8_t | ADC_Channel
 | ) |  |

Configures the analog watchdog guarded single channel.

Parameters:
ADCx,: where x can be 1, 2 or 3 to select the ADC peripheral.
ADC_Channel,: the ADC channel to configure for the analog watchdog. This parameter can be one of the following values:

  • ADC_Channel_0: ADC Channel0 selected
  • ADC_Channel_1: ADC Channel1 selected
  • ADC_Channel_2: ADC Channel2 selected
  • ADC_Channel_3: ADC Channel3 selected
  • ADC_Channel_4: ADC Channel4 selected
  • ADC_Channel_5: ADC Channel5 selected
  • ADC_Channel_6: ADC Channel6 selected
  • ADC_Channel_7: ADC Channel7 selected
  • ADC_Channel_8: ADC Channel8 selected
  • ADC_Channel_9: ADC Channel9 selected
  • ADC_Channel_10: ADC Channel10 selected
  • ADC_Channel_11: ADC Channel11 selected
  • ADC_Channel_12: ADC Channel12 selected
  • ADC_Channel_13: ADC Channel13 selected
  • ADC_Channel_14: ADC Channel14 selected
  • ADC_Channel_15: ADC Channel15 selected
  • ADC_Channel_16: ADC Channel16 selected
  • ADC_Channel_17: ADC Channel17 selected
Return values:
None

Definition at line 1145 of file stm32f10x_adc.c.

References assert_param, ADC_TypeDef::CR1, CR1_AWDCH_Reset, IS_ADC_ALL_PERIPH, and IS_ADC_CHANNEL.

Referenced by main().

void ADC_AnalogWatchdogThresholdsConfig | ( | ADC_TypeDef * | ADCx,
 |  | uint16_t | HighThreshold,
 |  | uint16_t | LowThreshold
 | ) |  |

Configures the high and low thresholds of the analog watchdog.

Parameters:
ADCx,: where x can be 1, 2 or 3 to select the ADC peripheral.
HighThreshold,: the ADC analog watchdog High threshold value. This parameter must be a 12bit value.
LowThreshold,: the ADC analog watchdog Low threshold value. This parameter must be a 12bit value.
Return values:
None

Definition at line 1107 of file stm32f10x_adc.c.

References assert_param, ADC_TypeDef::HTR, IS_ADC_ALL_PERIPH, IS_ADC_THRESHOLD, and ADC_TypeDef::LTR.

Referenced by main().

void ADC_AutoInjectedConvCmd | ( | ADC_TypeDef * | ADCx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the selected ADC automatic injected group conversion after regular one.

Parameters:
ADCx,: where x can be 1, 2 or 3 to select the ADC peripheral.
NewState,: new state of the selected ADC auto injected conversion This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 734 of file stm32f10x_adc.c.

References assert_param, ADC_TypeDef::CR1, CR1_JAUTO_Reset, CR1_JAUTO_Set, DISABLE, IS_ADC_ALL_PERIPH, and IS_FUNCTIONAL_STATE.

Referenced by main().

void ADC_ClearFlag | ( | ADC_TypeDef * | ADCx,
 |  | uint8_t | ADC_FLAG
 | ) |  |

Clears the ADCx's pending flags.

Parameters:
ADCx,: where x can be 1, 2 or 3 to select the ADC peripheral.
ADC_FLAG,: specifies the flag to clear. This parameter can be any combination of the following values:

  • ADC_FLAG_AWD: Analog watchdog flag
  • ADC_FLAG_EOC: End of conversion flag
  • ADC_FLAG_JEOC: End of injected group conversion flag
  • ADC_FLAG_JSTRT: Start of injected group conversion flag
  • ADC_FLAG_STRT: Start of regular group conversion flag
Return values:
None

Definition at line 1228 of file stm32f10x_adc.c.

References assert_param, IS_ADC_ALL_PERIPH, IS_ADC_CLEAR_FLAG, and ADC_TypeDef::SR.

void ADC_ClearITPendingBit | ( | ADC_TypeDef * | ADCx,
 |  | uint16_t | ADC_IT
 | ) |  |

Clears the ADCx's interrupt pending bits.

Parameters:
ADCx,: where x can be 1, 2 or 3 to select the ADC peripheral.
ADC_IT,: specifies the ADC interrupt pending bit to clear. This parameter can be any combination of the following values:

  • ADC_IT_EOC: End of conversion interrupt mask
  • ADC_IT_AWD: Analog watchdog interrupt mask
  • ADC_IT_JEOC: End of injected conversion interrupt mask
Return values:
None

Definition at line 1283 of file stm32f10x_adc.c.

References assert_param, IS_ADC_ALL_PERIPH, IS_ADC_IT, and ADC_TypeDef::SR.

Referenced by ADC1_2_IRQHandler().

void ADC_Cmd | ( | ADC_TypeDef * | ADCx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified ADC peripheral.

Parameters:
ADCx,: where x can be 1, 2 or 3 to select the ADC peripheral.
NewState,: new state of the ADCx peripheral. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 299 of file stm32f10x_adc.c.

References assert_param, ADC_TypeDef::CR2, CR2_ADON_Reset, CR2_ADON_Set, DISABLE, IS_ADC_ALL_PERIPH, and IS_FUNCTIONAL_STATE.

Referenced by main().

void ADC_DeInit ( ADC_TypeDef * ADCx )

Deinitializes the ADCx peripheral registers to their default reset values.

Parameters:
ADCx,: where x can be 1, 2 or 3 to select the ADC peripheral.
Return values:
None

Definition at line 179 of file stm32f10x_adc.c.

References ADC1, ADC2, ADC3, assert_param, DISABLE, ENABLE, IS_ADC_ALL_PERIPH, RCC_APB2Periph_ADC1, RCC_APB2Periph_ADC2, RCC_APB2Periph_ADC3, and RCC_APB2PeriphResetCmd().

void ADC_DiscModeChannelCountConfig | ( | ADC_TypeDef * | ADCx,
 |  | uint8_t | Number
 | ) |  |

Configures the discontinuous mode for the selected ADC regular group channel.

Parameters:
ADCx,: where x can be 1, 2 or 3 to select the ADC peripheral.
Number,: specifies the discontinuous mode regular channel count value. This number must be between 1 and 8.
Return values:
None

Definition at line 509 of file stm32f10x_adc.c.

References assert_param, ADC_TypeDef::CR1, CR1_DISCNUM_Reset, IS_ADC_ALL_PERIPH, and IS_ADC_REGULAR_DISC_NUMBER.

Referenced by main().

void ADC_DiscModeCmd | ( | ADC_TypeDef * | ADCx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the discontinuous mode on regular group channel for the specified ADC.

Parameters:
ADCx,: where x can be 1, 2 or 3 to select the ADC peripheral.
NewState,: new state of the selected ADC discontinuous mode on regular group channel. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 536 of file stm32f10x_adc.c.

References assert_param, ADC_TypeDef::CR1, CR1_DISCEN_Reset, CR1_DISCEN_Set, DISABLE, IS_ADC_ALL_PERIPH, and IS_FUNCTIONAL_STATE.

Referenced by main().

void ADC_DMACmd | ( | ADC_TypeDef * | ADCx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified ADC DMA request.

Parameters:
ADCx,: where x can be 1 or 3 to select the ADC peripheral. Note: ADC2 hasn't a DMA capability.
NewState,: new state of the selected ADC DMA transfer. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 324 of file stm32f10x_adc.c.

References assert_param, ADC_TypeDef::CR2, CR2_DMA_Reset, CR2_DMA_Set, DISABLE, IS_ADC_DMA_PERIPH, and IS_FUNCTIONAL_STATE.

Referenced by main().

void ADC_ExternalTrigConvCmd | ( | ADC_TypeDef * | ADCx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the ADCx conversion through external trigger.

Parameters:
ADCx,: where x can be 1, 2 or 3 to select the ADC peripheral.
NewState,: new state of the selected ADC external trigger start of conversion. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 686 of file stm32f10x_adc.c.

References assert_param, ADC_TypeDef::CR2, CR2_EXTTRIG_Reset, CR2_EXTTRIG_Set, DISABLE, IS_ADC_ALL_PERIPH, and IS_FUNCTIONAL_STATE.

Referenced by main().

void ADC_ExternalTrigInjectedConvCmd | ( | ADC_TypeDef * | ADCx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the ADCx injected channels conversion through external trigger.

Parameters:
ADCx,: where x can be 1, 2 or 3 to select the ADC peripheral.
NewState,: new state of the selected ADC external trigger start of injected conversion. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 824 of file stm32f10x_adc.c.

References assert_param, ADC_TypeDef::CR2, CR2_JEXTTRIG_Reset, CR2_JEXTTRIG_Set, DISABLE, IS_ADC_ALL_PERIPH, and IS_FUNCTIONAL_STATE.

Referenced by main().

void ADC_ExternalTrigInjectedConvConfig | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | ADC_ExternalTrigInjecConv
 | ) |  |

Configures the ADCx external trigger for injected channels conversion.

Parameters:
ADCx,: where x can be 1, 2 or 3 to select the ADC peripheral.
ADC_ExternalTrigInjecConv,: specifies the ADC trigger to start injected conversion. This parameter can be one of the following values:

  • ADC_ExternalTrigInjecConv_T1_TRGO: Timer1 TRGO event selected (for ADC1, ADC2 and ADC3)
  • ADC_ExternalTrigInjecConv_T1_CC4: Timer1 capture compare4 selected (for ADC1, ADC2 and ADC3)
  • ADC_ExternalTrigInjecConv_T2_TRGO: Timer2 TRGO event selected (for ADC1 and ADC2)
  • ADC_ExternalTrigInjecConv_T2_CC1: Timer2 capture compare1 selected (for ADC1 and ADC2)
  • ADC_ExternalTrigInjecConv_T3_CC4: Timer3 capture compare4 selected (for ADC1 and ADC2)
  • ADC_ExternalTrigInjecConv_T4_TRGO: Timer4 TRGO event selected (for ADC1 and ADC2)
  • ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4: External interrupt line 15 or Timer8 capture compare4 event selected (for ADC1 and ADC2)
  • ADC_ExternalTrigInjecConv_T4_CC3: Timer4 capture compare3 selected (for ADC3 only)
  • ADC_ExternalTrigInjecConv_T8_CC2: Timer8 capture compare2 selected (for ADC3 only)
  • ADC_ExternalTrigInjecConv_T8_CC4: Timer8 capture compare4 selected (for ADC3 only)
  • ADC_ExternalTrigInjecConv_T5_TRGO: Timer5 TRGO event selected (for ADC3 only)
  • ADC_ExternalTrigInjecConv_T5_CC4: Timer5 capture compare4 selected (for ADC3 only)
  • ADC_ExternalTrigInjecConv_None: Injected conversion started by software and not by external trigger (for ADC1, ADC2 and ADC3)
Return values:
None

Definition at line 799 of file stm32f10x_adc.c.

References assert_param, ADC_TypeDef::CR2, CR2_JEXTSEL_Reset, IS_ADC_ALL_PERIPH, and IS_ADC_EXT_INJEC_TRIG.

Referenced by main().

FlagStatus ADC_GetCalibrationStatus ( ADC_TypeDef * ADCx )

Gets the selected ADC calibration status.

Parameters:
ADCx,: where x can be 1, 2 or 3 to select the ADC peripheral.
Return values:
The new state of ADC calibration (SET or RESET).

Definition at line 430 of file stm32f10x_adc.c.

References assert_param, ADC_TypeDef::CR2, CR2_CAL_Set, IS_ADC_ALL_PERIPH, RESET, and SET.

Referenced by main().

uint16_t ADC_GetConversionValue ( ADC_TypeDef * ADCx )

Returns the last ADCx conversion result data for regular channel.

Parameters:
ADCx,: where x can be 1, 2 or 3 to select the ADC peripheral.
Return values:
The Data conversion value.

Definition at line 708 of file stm32f10x_adc.c.

References assert_param, ADC_TypeDef::DR, and IS_ADC_ALL_PERIPH.

Referenced by ADC1_2_IRQHandler().

uint32_t ADC_GetDualModeConversionValue ( void )

Returns the last ADC1 and ADC2 conversion result data in dual mode.

Return values:
The Data conversion value.

Definition at line 720 of file stm32f10x_adc.c.

References DR_ADDRESS.

FlagStatus ADC_GetFlagStatus | ( | ADC_TypeDef * | ADCx,
 |  | uint8_t | ADC_FLAG
 | ) |  |

Checks whether the specified ADC flag is set or not.

Parameters:
ADCx,: where x can be 1, 2 or 3 to select the ADC peripheral.
ADC_FLAG,: specifies the flag to check. This parameter can be one of the following values:

  • ADC_FLAG_AWD: Analog watchdog flag
  • ADC_FLAG_EOC: End of conversion flag
  • ADC_FLAG_JEOC: End of injected group conversion flag
  • ADC_FLAG_JSTRT: Start of injected group conversion flag
  • ADC_FLAG_STRT: Start of regular group conversion flag
Return values:
The new state of ADC_FLAG (SET or RESET).

Definition at line 1195 of file stm32f10x_adc.c.

References assert_param, IS_ADC_ALL_PERIPH, IS_ADC_GET_FLAG, RESET, SET, and ADC_TypeDef::SR.

uint16_t ADC_GetInjectedConversionValue | ( | ADC_TypeDef * | ADCx,
 |  | uint8_t | ADC_InjectedChannel
 | ) |  |

Returns the ADC injected channel conversion result.

Parameters:
ADCx,: where x can be 1, 2 or 3 to select the ADC peripheral.
ADC_InjectedChannel,: the converted ADC injected channel. This parameter can be one of the following values:

  • ADC_InjectedChannel_1: Injected Channel1 selected
  • ADC_InjectedChannel_2: Injected Channel2 selected
  • ADC_InjectedChannel_3: Injected Channel3 selected
  • ADC_InjectedChannel_4: Injected Channel4 selected
Return values:
The Data conversion value.

Definition at line 1052 of file stm32f10x_adc.c.

References assert_param, IS_ADC_ALL_PERIPH, IS_ADC_INJECTED_CHANNEL, and JDR_Offset.

Referenced by ADC1_2_IRQHandler().

ITStatus ADC_GetITStatus | ( | ADC_TypeDef * | ADCx,
 |  | uint16_t | ADC_IT
 | ) |  |

Checks whether the specified ADC interrupt has occurred or not.

Parameters:
ADCx,: where x can be 1, 2 or 3 to select the ADC peripheral.
ADC_IT,: specifies the ADC interrupt source to check. This parameter can be one of the following values:

  • ADC_IT_EOC: End of conversion interrupt mask
  • ADC_IT_AWD: Analog watchdog interrupt mask
  • ADC_IT_JEOC: End of injected conversion interrupt mask
Return values:
The new state of ADC_IT (SET or RESET).

Definition at line 1247 of file stm32f10x_adc.c.

References assert_param, ADC_TypeDef::CR1, IS_ADC_ALL_PERIPH, IS_ADC_GET_IT, RESET, SET, and ADC_TypeDef::SR.

FlagStatus ADC_GetResetCalibrationStatus ( ADC_TypeDef * ADCx )

Gets the selected ADC reset calibration registers status.

Parameters:
ADCx,: where x can be 1, 2 or 3 to select the ADC peripheral.
Return values:
The new state of ADC reset calibration registers (SET or RESET).

Definition at line 392 of file stm32f10x_adc.c.

References assert_param, ADC_TypeDef::CR2, CR2_RSTCAL_Set, IS_ADC_ALL_PERIPH, RESET, and SET.

Referenced by main().

FlagStatus ADC_GetSoftwareStartConvStatus ( ADC_TypeDef * ADCx )

Gets the selected ADC Software start conversion Status.

Parameters:
ADCx,: where x can be 1, 2 or 3 to select the ADC peripheral.
Return values:
The new state of ADC software start conversion (SET or RESET).

Definition at line 481 of file stm32f10x_adc.c.

References assert_param, ADC_TypeDef::CR2, CR2_SWSTART_Set, IS_ADC_ALL_PERIPH, RESET, and SET.

FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus ( ADC_TypeDef * ADCx )

Gets the selected ADC Software start injected conversion Status.

Parameters:
ADCx,: where x can be 1, 2 or 3 to select the ADC peripheral.
Return values:
The new state of ADC software start injected conversion (SET or RESET).

Definition at line 873 of file stm32f10x_adc.c.

References assert_param, ADC_TypeDef::CR2, CR2_JSWSTART_Set, IS_ADC_ALL_PERIPH, RESET, and SET.

void ADC_Init | ( | ADC_TypeDef * | ADCx,
 |  | ADC_InitTypeDef * | ADC_InitStruct
 | ) |  |

Initializes the ADCx peripheral according to the specified parameters in the ADC_InitStruct.

Parameters:
ADCx,: where x can be 1, 2 or 3 to select the ADC peripheral.
ADC_InitStruct,: pointer to an ADC_InitTypeDef structure that contains the configuration information for the specified ADC peripheral.
Return values:
None

Definition at line 218 of file stm32f10x_adc.c.

References ADC_InitTypeDef::ADC_ContinuousConvMode, ADC_InitTypeDef::ADC_DataAlign, ADC_InitTypeDef::ADC_ExternalTrigConv, ADC_InitTypeDef::ADC_Mode, ADC_InitTypeDef::ADC_NbrOfChannel, ADC_InitTypeDef::ADC_ScanConvMode, assert_param, ADC_TypeDef::CR1, CR1_CLEAR_Mask, ADC_TypeDef::CR2, CR2_CLEAR_Mask, IS_ADC_ALL_PERIPH, IS_ADC_DATA_ALIGN, IS_ADC_EXT_TRIG, IS_ADC_MODE, IS_ADC_REGULAR_LENGTH, IS_FUNCTIONAL_STATE, ADC_TypeDef::SQR1, and SQR1_CLEAR_Mask.

Referenced by main().

void ADC_InjectedChannelConfig | ( | ADC_TypeDef * | ADCx,
 |  | uint8_t | ADC_Channel,
 |  | uint8_t | Rank,
 |  | uint8_t | ADC_SampleTime
 | ) |  |

Configures for the selected ADC injected channel its corresponding rank in the sequencer and its sample time.

Parameters:
ADCx,: where x can be 1, 2 or 3 to select the ADC peripheral.
ADC_Channel,: the ADC channel to configure. This parameter can be one of the following values:

  • ADC_Channel_0: ADC Channel0 selected
  • ADC_Channel_1: ADC Channel1 selected
  • ADC_Channel_2: ADC Channel2 selected
  • ADC_Channel_3: ADC Channel3 selected
  • ADC_Channel_4: ADC Channel4 selected
  • ADC_Channel_5: ADC Channel5 selected
  • ADC_Channel_6: ADC Channel6 selected
  • ADC_Channel_7: ADC Channel7 selected
  • ADC_Channel_8: ADC Channel8 selected
  • ADC_Channel_9: ADC Channel9 selected
  • ADC_Channel_10: ADC Channel10 selected
  • ADC_Channel_11: ADC Channel11 selected
  • ADC_Channel_12: ADC Channel12 selected
  • ADC_Channel_13: ADC Channel13 selected
  • ADC_Channel_14: ADC Channel14 selected
  • ADC_Channel_15: ADC Channel15 selected
  • ADC_Channel_16: ADC Channel16 selected
  • ADC_Channel_17: ADC Channel17 selected
Rank,: The rank in the injected group sequencer. This parameter must be between 1 and 4.
ADC_SampleTime,: The sample time value to be set for the selected channel. This parameter can be one of the following values:

  • ADC_SampleTime_1Cycles5: Sample time equal to 1.5 cycles
  • ADC_SampleTime_7Cycles5: Sample time equal to 7.5 cycles
  • ADC_SampleTime_13Cycles5: Sample time equal to 13.5 cycles
  • ADC_SampleTime_28Cycles5: Sample time equal to 28.5 cycles
  • ADC_SampleTime_41Cycles5: Sample time equal to 41.5 cycles
  • ADC_SampleTime_55Cycles5: Sample time equal to 55.5 cycles
  • ADC_SampleTime_71Cycles5: Sample time equal to 71.5 cycles
  • ADC_SampleTime_239Cycles5: Sample time equal to 239.5 cycles
Return values:
None

Definition at line 930 of file stm32f10x_adc.c.

References ADC_Channel_9, assert_param, IS_ADC_ALL_PERIPH, IS_ADC_CHANNEL, IS_ADC_INJECTED_RANK, IS_ADC_SAMPLE_TIME, ADC_TypeDef::JSQR, JSQR_JL_Set, JSQR_JSQ_Set, ADC_TypeDef::SMPR1, SMPR1_SMP_Set, ADC_TypeDef::SMPR2, and SMPR2_SMP_Set.

Referenced by main().

void ADC_InjectedDiscModeCmd | ( | ADC_TypeDef * | ADCx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the discontinuous mode for injected group channel for the specified ADC.

Parameters:
ADCx,: where x can be 1, 2 or 3 to select the ADC peripheral.
NewState,: new state of the selected ADC discontinuous mode on injected group channel. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 760 of file stm32f10x_adc.c.

References assert_param, ADC_TypeDef::CR1, CR1_JDISCEN_Reset, CR1_JDISCEN_Set, DISABLE, IS_ADC_ALL_PERIPH, and IS_FUNCTIONAL_STATE.

void ADC_InjectedSequencerLengthConfig | ( | ADC_TypeDef * | ADCx,
 |  | uint8_t | Length
 | ) |  |

Configures the sequencer length for injected channels.

Parameters:
ADCx,: where x can be 1, 2 or 3 to select the ADC peripheral.
Length,: The sequencer length. This parameter must be a number between 1 to 4.
Return values:
None

Definition at line 993 of file stm32f10x_adc.c.

References assert_param, IS_ADC_ALL_PERIPH, IS_ADC_INJECTED_LENGTH, ADC_TypeDef::JSQR, and JSQR_JL_Reset.

Referenced by main().

void ADC_ITConfig | ( | ADC_TypeDef * | ADCx,
 |  | uint16_t | ADC_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified ADC interrupts.

Parameters:
ADCx,: where x can be 1, 2 or 3 to select the ADC peripheral.
ADC_IT,: specifies the ADC interrupt sources to be enabled or disabled. This parameter can be any combination of the following values:

  • ADC_IT_EOC: End of conversion interrupt mask
  • ADC_IT_AWD: Analog watchdog interrupt mask
  • ADC_IT_JEOC: End of injected conversion interrupt mask
NewState,: new state of the specified ADC interrupts. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 353 of file stm32f10x_adc.c.

References assert_param, ADC_TypeDef::CR1, DISABLE, IS_ADC_ALL_PERIPH, IS_ADC_IT, and IS_FUNCTIONAL_STATE.

Referenced by main().

void ADC_RegularChannelConfig | ( | ADC_TypeDef * | ADCx,
 |  | uint8_t | ADC_Channel,
 |  | uint8_t | Rank,
 |  | uint8_t | ADC_SampleTime
 | ) |  |

Configures for the selected ADC regular channel its corresponding rank in the sequencer and its sample time.

Parameters:
ADCx,: where x can be 1, 2 or 3 to select the ADC peripheral.
ADC_Channel,: the ADC channel to configure. This parameter can be one of the following values:

  • ADC_Channel_0: ADC Channel0 selected
  • ADC_Channel_1: ADC Channel1 selected
  • ADC_Channel_2: ADC Channel2 selected
  • ADC_Channel_3: ADC Channel3 selected
  • ADC_Channel_4: ADC Channel4 selected
  • ADC_Channel_5: ADC Channel5 selected
  • ADC_Channel_6: ADC Channel6 selected
  • ADC_Channel_7: ADC Channel7 selected
  • ADC_Channel_8: ADC Channel8 selected
  • ADC_Channel_9: ADC Channel9 selected
  • ADC_Channel_10: ADC Channel10 selected
  • ADC_Channel_11: ADC Channel11 selected
  • ADC_Channel_12: ADC Channel12 selected
  • ADC_Channel_13: ADC Channel13 selected
  • ADC_Channel_14: ADC Channel14 selected
  • ADC_Channel_15: ADC Channel15 selected
  • ADC_Channel_16: ADC Channel16 selected
  • ADC_Channel_17: ADC Channel17 selected
Rank,: The rank in the regular group sequencer. This parameter must be between 1 to 16.
ADC_SampleTime,: The sample time value to be set for the selected channel. This parameter can be one of the following values:

  • ADC_SampleTime_1Cycles5: Sample time equal to 1.5 cycles
  • ADC_SampleTime_7Cycles5: Sample time equal to 7.5 cycles
  • ADC_SampleTime_13Cycles5: Sample time equal to 13.5 cycles
  • ADC_SampleTime_28Cycles5: Sample time equal to 28.5 cycles
  • ADC_SampleTime_41Cycles5: Sample time equal to 41.5 cycles
  • ADC_SampleTime_55Cycles5: Sample time equal to 55.5 cycles
  • ADC_SampleTime_71Cycles5: Sample time equal to 71.5 cycles
  • ADC_SampleTime_239Cycles5: Sample time equal to 239.5 cycles
Return values:
None

Definition at line 590 of file stm32f10x_adc.c.

References ADC_Channel_9, assert_param, IS_ADC_ALL_PERIPH, IS_ADC_CHANNEL, IS_ADC_REGULAR_RANK, IS_ADC_SAMPLE_TIME, ADC_TypeDef::SMPR1, SMPR1_SMP_Set, ADC_TypeDef::SMPR2, SMPR2_SMP_Set, ADC_TypeDef::SQR1, SQR1_SQ_Set, ADC_TypeDef::SQR2, SQR2_SQ_Set, ADC_TypeDef::SQR3, and SQR3_SQ_Set.

Referenced by main().

void ADC_ResetCalibration ( ADC_TypeDef * ADCx )

Resets the selected ADC calibration registers.

Parameters:
ADCx,: where x can be 1, 2 or 3 to select the ADC peripheral.
Return values:
None

Definition at line 379 of file stm32f10x_adc.c.

References assert_param, ADC_TypeDef::CR2, CR2_RSTCAL_Set, and IS_ADC_ALL_PERIPH.

Referenced by main().

void ADC_SetInjectedOffset | ( | ADC_TypeDef * | ADCx,
 |  | uint8_t | ADC_InjectedChannel,
 |  | uint16_t | Offset
 | ) |  |

Set the injected channels conversion value offset.

Parameters:
ADCx,: where x can be 1, 2 or 3 to select the ADC peripheral.
ADC_InjectedChannel,: the ADC injected channel to set its offset. This parameter can be one of the following values:

  • ADC_InjectedChannel_1: Injected Channel1 selected
  • ADC_InjectedChannel_2: Injected Channel2 selected
  • ADC_InjectedChannel_3: Injected Channel3 selected
  • ADC_InjectedChannel_4: Injected Channel4 selected
Offset,: the offset value for the selected ADC injected channel This parameter must be a 12bit value.
Return values:
None

Definition at line 1025 of file stm32f10x_adc.c.

References assert_param, IS_ADC_ALL_PERIPH, IS_ADC_INJECTED_CHANNEL, and IS_ADC_OFFSET.

void ADC_SoftwareStartConvCmd | ( | ADC_TypeDef * | ADCx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the selected ADC software start conversion .

Parameters:
ADCx,: where x can be 1, 2 or 3 to select the ADC peripheral.
NewState,: new state of the selected ADC software start conversion. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 457 of file stm32f10x_adc.c.

References assert_param, ADC_TypeDef::CR2, CR2_EXTTRIG_SWSTART_Reset, CR2_EXTTRIG_SWSTART_Set, DISABLE, IS_ADC_ALL_PERIPH, and IS_FUNCTIONAL_STATE.

Referenced by main().

void ADC_SoftwareStartInjectedConvCmd | ( | ADC_TypeDef * | ADCx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the selected ADC start of the injected channels conversion.

Parameters:
ADCx,: where x can be 1, 2 or 3 to select the ADC peripheral.
NewState,: new state of the selected ADC software start injected conversion. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 849 of file stm32f10x_adc.c.

References assert_param, ADC_TypeDef::CR2, CR2_JEXTTRIG_JSWSTART_Reset, CR2_JEXTTRIG_JSWSTART_Set, DISABLE, IS_ADC_ALL_PERIPH, and IS_FUNCTIONAL_STATE.

void ADC_StartCalibration ( ADC_TypeDef * ADCx )

Starts the selected ADC calibration process.

Parameters:
ADCx,: where x can be 1, 2 or 3 to select the ADC peripheral.
Return values:
None

Definition at line 417 of file stm32f10x_adc.c.

References assert_param, ADC_TypeDef::CR2, CR2_CAL_Set, and IS_ADC_ALL_PERIPH.

Referenced by main().

void ADC_StructInit ( ADC_InitTypeDef * ADC_InitStruct )

Fills each ADC_InitStruct member with its default value.

Parameters:
ADC_InitStruct : pointer to an ADC_InitTypeDef structure which will be initialized.
Return values:
None

Definition at line 275 of file stm32f10x_adc.c.

References ADC_InitTypeDef::ADC_ContinuousConvMode, ADC_InitTypeDef::ADC_DataAlign, ADC_DataAlign_Right, ADC_InitTypeDef::ADC_ExternalTrigConv, ADC_ExternalTrigConv_T1_CC1, ADC_InitTypeDef::ADC_Mode, ADC_Mode_Independent, ADC_InitTypeDef::ADC_NbrOfChannel, ADC_InitTypeDef::ADC_ScanConvMode, and DISABLE.

void ADC_TempSensorVrefintCmd ( FunctionalState NewState )

Enables or disables the temperature sensor and Vrefint channel.

Parameters:
NewState,: new state of the temperature sensor. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1167 of file stm32f10x_adc.c.

References ADC1, assert_param, CR2_TSVREFE_Reset, CR2_TSVREFE_Set, DISABLE, and IS_FUNCTIONAL_STATE.

Referenced by main().


STM32F10x Standard Peripherals Firmware Library: ADC_Private_TypesDefinitions

ADC_Private_TypesDefinitions

ADC


STM32F10x Standard Peripherals Firmware Library: ADC_Private_Defines

Defines

ADC_Private_Defines

ADC

Defines

#define | CR1_AWDCH_Reset ((uint32_t)0xFFFFFFE0)
#define | CR1_AWDMode_Reset ((uint32_t)0xFF3FFDFF)
#define | CR1_CLEAR_Mask ((uint32_t)0xFFF0FEFF)
#define | CR1_DISCEN_Reset ((uint32_t)0xFFFFF7FF)
#define | CR1_DISCEN_Set ((uint32_t)0x00000800)
#define | CR1_DISCNUM_Reset ((uint32_t)0xFFFF1FFF)
#define | CR1_JAUTO_Reset ((uint32_t)0xFFFFFBFF)
#define | CR1_JAUTO_Set ((uint32_t)0x00000400)
#define | CR1_JDISCEN_Reset ((uint32_t)0xFFFFEFFF)
#define | CR1_JDISCEN_Set ((uint32_t)0x00001000)
#define | CR2_ADON_Reset ((uint32_t)0xFFFFFFFE)
#define | CR2_ADON_Set ((uint32_t)0x00000001)
#define | CR2_CAL_Set ((uint32_t)0x00000004)
#define | CR2_CLEAR_Mask ((uint32_t)0xFFF1F7FD)
#define | CR2_DMA_Reset ((uint32_t)0xFFFFFEFF)
#define | CR2_DMA_Set ((uint32_t)0x00000100)
#define | CR2_EXTTRIG_Reset ((uint32_t)0xFFEFFFFF)
#define | CR2_EXTTRIG_Set ((uint32_t)0x00100000)
#define | CR2_EXTTRIG_SWSTART_Reset ((uint32_t)0xFFAFFFFF)
#define | CR2_EXTTRIG_SWSTART_Set ((uint32_t)0x00500000)
#define | CR2_JEXTSEL_Reset ((uint32_t)0xFFFF8FFF)
#define | CR2_JEXTTRIG_JSWSTART_Reset ((uint32_t)0xFFDF7FFF)
#define | CR2_JEXTTRIG_JSWSTART_Set ((uint32_t)0x00208000)
#define | CR2_JEXTTRIG_Reset ((uint32_t)0xFFFF7FFF)
#define | CR2_JEXTTRIG_Set ((uint32_t)0x00008000)
#define | CR2_JSWSTART_Set ((uint32_t)0x00200000)
#define | CR2_RSTCAL_Set ((uint32_t)0x00000008)
#define | CR2_SWSTART_Set ((uint32_t)0x00400000)
#define | CR2_TSVREFE_Reset ((uint32_t)0xFF7FFFFF)
#define | CR2_TSVREFE_Set ((uint32_t)0x00800000)
#define | DR_ADDRESS ((uint32_t)0x4001244C)
#define | JDR_Offset ((uint8_t)0x28)
#define | JSQR_JL_Reset ((uint32_t)0xFFCFFFFF)
#define | JSQR_JL_Set ((uint32_t)0x00300000)
#define | JSQR_JSQ_Set ((uint32_t)0x0000001F)
#define | SMPR1_SMP_Set ((uint32_t)0x00000007)
#define | SMPR2_SMP_Set ((uint32_t)0x00000007)
#define | SQR1_CLEAR_Mask ((uint32_t)0xFF0FFFFF)
#define | SQR1_SQ_Set ((uint32_t)0x0000001F)
#define | SQR2_SQ_Set ((uint32_t)0x0000001F)
#define | SQR3_SQ_Set ((uint32_t)0x0000001F)

Define Documentation

#define CR1_AWDCH_Reset ((uint32_t)0xFFFFFFE0)

Definition at line 63 of file stm32f10x_adc.c.

Referenced by ADC_AnalogWatchdogSingleChannelConfig().

#define CR1_AWDMode_Reset ((uint32_t)0xFF3FFDFF)

Definition at line 66 of file stm32f10x_adc.c.

Referenced by ADC_AnalogWatchdogCmd().

#define CR1_CLEAR_Mask ((uint32_t)0xFFF0FEFF)

Definition at line 69 of file stm32f10x_adc.c.

Referenced by ADC_Init().

#define CR1_DISCEN_Reset ((uint32_t)0xFFFFF7FF)

Definition at line 52 of file stm32f10x_adc.c.

Referenced by ADC_DiscModeCmd().

#define CR1_DISCEN_Set ((uint32_t)0x00000800)

Definition at line 51 of file stm32f10x_adc.c.

Referenced by ADC_DiscModeCmd().

#define CR1_DISCNUM_Reset ((uint32_t)0xFFFF1FFF)

Definition at line 48 of file stm32f10x_adc.c.

Referenced by ADC_DiscModeChannelCountConfig().

#define CR1_JAUTO_Reset ((uint32_t)0xFFFFFBFF)

Definition at line 56 of file stm32f10x_adc.c.

Referenced by ADC_AutoInjectedConvCmd().

#define CR1_JAUTO_Set ((uint32_t)0x00000400)

Definition at line 55 of file stm32f10x_adc.c.

Referenced by ADC_AutoInjectedConvCmd().

#define CR1_JDISCEN_Reset ((uint32_t)0xFFFFEFFF)

Definition at line 60 of file stm32f10x_adc.c.

Referenced by ADC_InjectedDiscModeCmd().

#define CR1_JDISCEN_Set ((uint32_t)0x00001000)

Definition at line 59 of file stm32f10x_adc.c.

Referenced by ADC_InjectedDiscModeCmd().

#define CR2_ADON_Reset ((uint32_t)0xFFFFFFFE)

Definition at line 73 of file stm32f10x_adc.c.

Referenced by ADC_Cmd().

#define CR2_ADON_Set ((uint32_t)0x00000001)

Definition at line 72 of file stm32f10x_adc.c.

Referenced by ADC_Cmd().

#define CR2_CAL_Set ((uint32_t)0x00000004)

Definition at line 83 of file stm32f10x_adc.c.

Referenced by ADC_GetCalibrationStatus(), and ADC_StartCalibration().

#define CR2_CLEAR_Mask ((uint32_t)0xFFF1F7FD)

Definition at line 115 of file stm32f10x_adc.c.

Referenced by ADC_Init().

#define CR2_DMA_Reset ((uint32_t)0xFFFFFEFF)

Definition at line 77 of file stm32f10x_adc.c.

Referenced by ADC_DMACmd().

#define CR2_DMA_Set ((uint32_t)0x00000100)

Definition at line 76 of file stm32f10x_adc.c.

Referenced by ADC_DMACmd().

#define CR2_EXTTRIG_Reset ((uint32_t)0xFFEFFFFF)

Definition at line 90 of file stm32f10x_adc.c.

Referenced by ADC_ExternalTrigConvCmd().

#define CR2_EXTTRIG_Set ((uint32_t)0x00100000)

Definition at line 89 of file stm32f10x_adc.c.

Referenced by ADC_ExternalTrigConvCmd().

#define CR2_EXTTRIG_SWSTART_Reset ((uint32_t)0xFFAFFFFF)

Definition at line 94 of file stm32f10x_adc.c.

Referenced by ADC_SoftwareStartConvCmd().

#define CR2_EXTTRIG_SWSTART_Set ((uint32_t)0x00500000)

Definition at line 93 of file stm32f10x_adc.c.

Referenced by ADC_SoftwareStartConvCmd().

#define CR2_JEXTSEL_Reset ((uint32_t)0xFFFF8FFF)

Definition at line 97 of file stm32f10x_adc.c.

Referenced by ADC_ExternalTrigInjectedConvConfig().

#define CR2_JEXTTRIG_JSWSTART_Reset ((uint32_t)0xFFDF7FFF)

Definition at line 108 of file stm32f10x_adc.c.

Referenced by ADC_SoftwareStartInjectedConvCmd().

#define CR2_JEXTTRIG_JSWSTART_Set ((uint32_t)0x00208000)

Definition at line 107 of file stm32f10x_adc.c.

Referenced by ADC_SoftwareStartInjectedConvCmd().

#define CR2_JEXTTRIG_Reset ((uint32_t)0xFFFF7FFF)

Definition at line 101 of file stm32f10x_adc.c.

Referenced by ADC_ExternalTrigInjectedConvCmd().

#define CR2_JEXTTRIG_Set ((uint32_t)0x00008000)

Definition at line 100 of file stm32f10x_adc.c.

Referenced by ADC_ExternalTrigInjectedConvCmd().

#define CR2_JSWSTART_Set ((uint32_t)0x00200000)

Definition at line 104 of file stm32f10x_adc.c.

Referenced by ADC_GetSoftwareStartInjectedConvCmdStatus().

#define CR2_RSTCAL_Set ((uint32_t)0x00000008)

Definition at line 80 of file stm32f10x_adc.c.

Referenced by ADC_GetResetCalibrationStatus(), and ADC_ResetCalibration().

#define CR2_SWSTART_Set ((uint32_t)0x00400000)

Definition at line 86 of file stm32f10x_adc.c.

Referenced by ADC_GetSoftwareStartConvStatus().

#define CR2_TSVREFE_Reset ((uint32_t)0xFF7FFFFF)

Definition at line 112 of file stm32f10x_adc.c.

Referenced by ADC_TempSensorVrefintCmd().

#define CR2_TSVREFE_Set ((uint32_t)0x00800000)

Definition at line 111 of file stm32f10x_adc.c.

Referenced by ADC_TempSensorVrefintCmd().

#define DR_ADDRESS ((uint32_t)0x4001244C)

Definition at line 140 of file stm32f10x_adc.c.

Referenced by ADC_GetDualModeConversionValue().

#define JDR_Offset ((uint8_t)0x28)

Definition at line 137 of file stm32f10x_adc.c.

Referenced by ADC_GetInjectedConversionValue().

#define JSQR_JL_Reset ((uint32_t)0xFFCFFFFF)

Definition at line 130 of file stm32f10x_adc.c.

Referenced by ADC_InjectedSequencerLengthConfig().

#define JSQR_JL_Set ((uint32_t)0x00300000)

Definition at line 129 of file stm32f10x_adc.c.

Referenced by ADC_InjectedChannelConfig().

#define JSQR_JSQ_Set ((uint32_t)0x0000001F)

Definition at line 126 of file stm32f10x_adc.c.

Referenced by ADC_InjectedChannelConfig().

#define SMPR1_SMP_Set ((uint32_t)0x00000007)

Definition at line 133 of file stm32f10x_adc.c.

Referenced by ADC_InjectedChannelConfig(), and ADC_RegularChannelConfig().

#define SMPR2_SMP_Set ((uint32_t)0x00000007)

Definition at line 134 of file stm32f10x_adc.c.

Referenced by ADC_InjectedChannelConfig(), and ADC_RegularChannelConfig().

#define SQR1_CLEAR_Mask ((uint32_t)0xFF0FFFFF)

Definition at line 123 of file stm32f10x_adc.c.

Referenced by ADC_Init().

#define SQR1_SQ_Set ((uint32_t)0x0000001F)

Definition at line 120 of file stm32f10x_adc.c.

Referenced by ADC_RegularChannelConfig().

#define SQR2_SQ_Set ((uint32_t)0x0000001F)

Definition at line 119 of file stm32f10x_adc.c.

Referenced by ADC_RegularChannelConfig().

#define SQR3_SQ_Set ((uint32_t)0x0000001F)

Definition at line 118 of file stm32f10x_adc.c.

Referenced by ADC_RegularChannelConfig().


STM32F10x Standard Peripherals Firmware Library: ADC_Private_Macros

ADC_Private_Macros

ADC


STM32F10x Standard Peripherals Firmware Library: ADC_Private_Variables

ADC_Private_Variables

ADC


STM32F10x Standard Peripherals Firmware Library: ADC_Private_FunctionPrototypes

ADC_Private_FunctionPrototypes

ADC


STM32F10x Standard Peripherals Firmware Library: ADC_Private_Functions

Functions

ADC_Private_Functions

ADC

Functions

void | ADC_AnalogWatchdogCmd (ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog)
Enables or disables the analog watchdog on single/all regular or injected channels.
void | ADC_AnalogWatchdogSingleChannelConfig (ADC_TypeDef *ADCx, uint8_t ADC_Channel)
Configures the analog watchdog guarded single channel.
void | ADC_AnalogWatchdogThresholdsConfig (ADC_TypeDef *ADCx, uint16_t HighThreshold, uint16_t LowThreshold)
Configures the high and low thresholds of the analog watchdog.
void | ADC_AutoInjectedConvCmd (ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the selected ADC automatic injected group conversion after regular one.
void | ADC_ClearFlag (ADC_TypeDef *ADCx, uint8_t ADC_FLAG)
Clears the ADCx's pending flags.
void | ADC_ClearITPendingBit (ADC_TypeDef *ADCx, uint16_t ADC_IT)
Clears the ADCx's interrupt pending bits.
void | ADC_Cmd (ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the specified ADC peripheral.
void | ADC_DeInit (ADC_TypeDef *ADCx)
Deinitializes the ADCx peripheral registers to their default reset values.
void | ADC_DiscModeChannelCountConfig (ADC_TypeDef *ADCx, uint8_t Number)
Configures the discontinuous mode for the selected ADC regular group channel.
void | ADC_DiscModeCmd (ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the discontinuous mode on regular group channel for the specified ADC.
void | ADC_DMACmd (ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the specified ADC DMA request.
void | ADC_ExternalTrigConvCmd (ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the ADCx conversion through external trigger.
void | ADC_ExternalTrigInjectedConvCmd (ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the ADCx injected channels conversion through external trigger.
void | ADC_ExternalTrigInjectedConvConfig (ADC_TypeDef *ADCx, uint32_t ADC_ExternalTrigInjecConv)
Configures the ADCx external trigger for injected channels conversion.
FlagStatus | ADC_GetCalibrationStatus (ADC_TypeDef *ADCx)
Gets the selected ADC calibration status.
uint16_t | ADC_GetConversionValue (ADC_TypeDef *ADCx)
Returns the last ADCx conversion result data for regular channel.
uint32_t | ADC_GetDualModeConversionValue (void)
Returns the last ADC1 and ADC2 conversion result data in dual mode.
FlagStatus | ADC_GetFlagStatus (ADC_TypeDef *ADCx, uint8_t ADC_FLAG)
Checks whether the specified ADC flag is set or not.
uint16_t | ADC_GetInjectedConversionValue (ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel)
Returns the ADC injected channel conversion result.
ITStatus | ADC_GetITStatus (ADC_TypeDef *ADCx, uint16_t ADC_IT)
Checks whether the specified ADC interrupt has occurred or not.
FlagStatus | ADC_GetResetCalibrationStatus (ADC_TypeDef *ADCx)
Gets the selected ADC reset calibration registers status.
FlagStatus | ADC_GetSoftwareStartConvStatus (ADC_TypeDef *ADCx)
Gets the selected ADC Software start conversion Status.
FlagStatus | ADC_GetSoftwareStartInjectedConvCmdStatus (ADC_TypeDef *ADCx)
Gets the selected ADC Software start injected conversion Status.
void | ADC_Init (ADC_TypeDef *ADCx, ADC_InitTypeDef *ADC_InitStruct)
Initializes the ADCx peripheral according to the specified parameters in the ADC_InitStruct.
void | ADC_InjectedChannelConfig (ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
Configures for the selected ADC injected channel its corresponding rank in the sequencer and its sample time.
void | ADC_InjectedDiscModeCmd (ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the discontinuous mode for injected group channel for the specified ADC.
void | ADC_InjectedSequencerLengthConfig (ADC_TypeDef *ADCx, uint8_t Length)
Configures the sequencer length for injected channels.
void | ADC_ITConfig (ADC_TypeDef *ADCx, uint16_t ADC_IT, FunctionalState NewState)
Enables or disables the specified ADC interrupts.
void | ADC_RegularChannelConfig (ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
Configures for the selected ADC regular channel its corresponding rank in the sequencer and its sample time.
void | ADC_ResetCalibration (ADC_TypeDef *ADCx)
Resets the selected ADC calibration registers.
void | ADC_SetInjectedOffset (ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset)
Set the injected channels conversion value offset.
void | ADC_SoftwareStartConvCmd (ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the selected ADC software start conversion .
void | ADC_SoftwareStartInjectedConvCmd (ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the selected ADC start of the injected channels conversion.
void | ADC_StartCalibration (ADC_TypeDef *ADCx)
Starts the selected ADC calibration process.
void | ADC_StructInit (ADC_InitTypeDef *ADC_InitStruct)
Fills each ADC_InitStruct member with its default value.
void | ADC_TempSensorVrefintCmd (FunctionalState NewState)
Enables or disables the temperature sensor and Vrefint channel.

Function Documentation

void ADC_AnalogWatchdogCmd | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | ADC_AnalogWatchdog
 | ) |  |

Enables or disables the analog watchdog on single/all regular or injected channels.

Parameters:
ADCx,: where x can be 1, 2 or 3 to select the ADC peripheral.
ADC_AnalogWatchdog,: the ADC analog watchdog configuration. This parameter can be one of the following values:

  • ADC_AnalogWatchdog_SingleRegEnable: Analog watchdog on a single regular channel
  • ADC_AnalogWatchdog_SingleInjecEnable: Analog watchdog on a single injected channel
  • ADC_AnalogWatchdog_SingleRegOrInjecEnable: Analog watchdog on a single regular or injected channel
  • ADC_AnalogWatchdog_AllRegEnable: Analog watchdog on all regular channel
  • ADC_AnalogWatchdog_AllInjecEnable: Analog watchdog on all injected channel
  • ADC_AnalogWatchdog_AllRegAllInjecEnable: Analog watchdog on all regular and injected channels
  • ADC_AnalogWatchdog_None: No channel guarded by the analog watchdog
Return values:
None

Definition at line 1082 of file stm32f10x_adc.c.

References assert_param, ADC_TypeDef::CR1, CR1_AWDMode_Reset, IS_ADC_ALL_PERIPH, and IS_ADC_ANALOG_WATCHDOG.

Referenced by main().

void ADC_AnalogWatchdogSingleChannelConfig | ( | ADC_TypeDef * | ADCx,
 |  | uint8_t | ADC_Channel
 | ) |  |

Configures the analog watchdog guarded single channel.

Parameters:
ADCx,: where x can be 1, 2 or 3 to select the ADC peripheral.
ADC_Channel,: the ADC channel to configure for the analog watchdog. This parameter can be one of the following values:

  • ADC_Channel_0: ADC Channel0 selected
  • ADC_Channel_1: ADC Channel1 selected
  • ADC_Channel_2: ADC Channel2 selected
  • ADC_Channel_3: ADC Channel3 selected
  • ADC_Channel_4: ADC Channel4 selected
  • ADC_Channel_5: ADC Channel5 selected
  • ADC_Channel_6: ADC Channel6 selected
  • ADC_Channel_7: ADC Channel7 selected
  • ADC_Channel_8: ADC Channel8 selected
  • ADC_Channel_9: ADC Channel9 selected
  • ADC_Channel_10: ADC Channel10 selected
  • ADC_Channel_11: ADC Channel11 selected
  • ADC_Channel_12: ADC Channel12 selected
  • ADC_Channel_13: ADC Channel13 selected
  • ADC_Channel_14: ADC Channel14 selected
  • ADC_Channel_15: ADC Channel15 selected
  • ADC_Channel_16: ADC Channel16 selected
  • ADC_Channel_17: ADC Channel17 selected
Return values:
None

Definition at line 1145 of file stm32f10x_adc.c.

References assert_param, ADC_TypeDef::CR1, CR1_AWDCH_Reset, IS_ADC_ALL_PERIPH, and IS_ADC_CHANNEL.

Referenced by main().

void ADC_AnalogWatchdogThresholdsConfig | ( | ADC_TypeDef * | ADCx,
 |  | uint16_t | HighThreshold,
 |  | uint16_t | LowThreshold
 | ) |  |

Configures the high and low thresholds of the analog watchdog.

Parameters:
ADCx,: where x can be 1, 2 or 3 to select the ADC peripheral.
HighThreshold,: the ADC analog watchdog High threshold value. This parameter must be a 12bit value.
LowThreshold,: the ADC analog watchdog Low threshold value. This parameter must be a 12bit value.
Return values:
None

Definition at line 1107 of file stm32f10x_adc.c.

References assert_param, ADC_TypeDef::HTR, IS_ADC_ALL_PERIPH, IS_ADC_THRESHOLD, and ADC_TypeDef::LTR.

Referenced by main().

void ADC_AutoInjectedConvCmd | ( | ADC_TypeDef * | ADCx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the selected ADC automatic injected group conversion after regular one.

Parameters:
ADCx,: where x can be 1, 2 or 3 to select the ADC peripheral.
NewState,: new state of the selected ADC auto injected conversion This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 734 of file stm32f10x_adc.c.

References assert_param, ADC_TypeDef::CR1, CR1_JAUTO_Reset, CR1_JAUTO_Set, DISABLE, IS_ADC_ALL_PERIPH, and IS_FUNCTIONAL_STATE.

Referenced by main().

void ADC_ClearFlag | ( | ADC_TypeDef * | ADCx,
 |  | uint8_t | ADC_FLAG
 | ) |  |

Clears the ADCx's pending flags.

Parameters:
ADCx,: where x can be 1, 2 or 3 to select the ADC peripheral.
ADC_FLAG,: specifies the flag to clear. This parameter can be any combination of the following values:

  • ADC_FLAG_AWD: Analog watchdog flag
  • ADC_FLAG_EOC: End of conversion flag
  • ADC_FLAG_JEOC: End of injected group conversion flag
  • ADC_FLAG_JSTRT: Start of injected group conversion flag
  • ADC_FLAG_STRT: Start of regular group conversion flag
Return values:
None

Definition at line 1228 of file stm32f10x_adc.c.

References assert_param, IS_ADC_ALL_PERIPH, IS_ADC_CLEAR_FLAG, and ADC_TypeDef::SR.

void ADC_ClearITPendingBit | ( | ADC_TypeDef * | ADCx,
 |  | uint16_t | ADC_IT
 | ) |  |

Clears the ADCx's interrupt pending bits.

Parameters:
ADCx,: where x can be 1, 2 or 3 to select the ADC peripheral.
ADC_IT,: specifies the ADC interrupt pending bit to clear. This parameter can be any combination of the following values:

  • ADC_IT_EOC: End of conversion interrupt mask
  • ADC_IT_AWD: Analog watchdog interrupt mask
  • ADC_IT_JEOC: End of injected conversion interrupt mask
Return values:
None

Definition at line 1283 of file stm32f10x_adc.c.

References assert_param, IS_ADC_ALL_PERIPH, IS_ADC_IT, and ADC_TypeDef::SR.

Referenced by ADC1_2_IRQHandler().

void ADC_Cmd | ( | ADC_TypeDef * | ADCx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified ADC peripheral.

Parameters:
ADCx,: where x can be 1, 2 or 3 to select the ADC peripheral.
NewState,: new state of the ADCx peripheral. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 299 of file stm32f10x_adc.c.

References assert_param, ADC_TypeDef::CR2, CR2_ADON_Reset, CR2_ADON_Set, DISABLE, IS_ADC_ALL_PERIPH, and IS_FUNCTIONAL_STATE.

Referenced by main().

void ADC_DeInit ( ADC_TypeDef * ADCx )

Deinitializes the ADCx peripheral registers to their default reset values.

Parameters:
ADCx,: where x can be 1, 2 or 3 to select the ADC peripheral.
Return values:
None

Definition at line 179 of file stm32f10x_adc.c.

References ADC1, ADC2, ADC3, assert_param, DISABLE, ENABLE, IS_ADC_ALL_PERIPH, RCC_APB2Periph_ADC1, RCC_APB2Periph_ADC2, RCC_APB2Periph_ADC3, and RCC_APB2PeriphResetCmd().

void ADC_DiscModeChannelCountConfig | ( | ADC_TypeDef * | ADCx,
 |  | uint8_t | Number
 | ) |  |

Configures the discontinuous mode for the selected ADC regular group channel.

Parameters:
ADCx,: where x can be 1, 2 or 3 to select the ADC peripheral.
Number,: specifies the discontinuous mode regular channel count value. This number must be between 1 and 8.
Return values:
None

Definition at line 509 of file stm32f10x_adc.c.

References assert_param, ADC_TypeDef::CR1, CR1_DISCNUM_Reset, IS_ADC_ALL_PERIPH, and IS_ADC_REGULAR_DISC_NUMBER.

Referenced by main().

void ADC_DiscModeCmd | ( | ADC_TypeDef * | ADCx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the discontinuous mode on regular group channel for the specified ADC.

Parameters:
ADCx,: where x can be 1, 2 or 3 to select the ADC peripheral.
NewState,: new state of the selected ADC discontinuous mode on regular group channel. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 536 of file stm32f10x_adc.c.

References assert_param, ADC_TypeDef::CR1, CR1_DISCEN_Reset, CR1_DISCEN_Set, DISABLE, IS_ADC_ALL_PERIPH, and IS_FUNCTIONAL_STATE.

Referenced by main().

void ADC_DMACmd | ( | ADC_TypeDef * | ADCx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified ADC DMA request.

Parameters:
ADCx,: where x can be 1 or 3 to select the ADC peripheral. Note: ADC2 hasn't a DMA capability.
NewState,: new state of the selected ADC DMA transfer. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 324 of file stm32f10x_adc.c.

References assert_param, ADC_TypeDef::CR2, CR2_DMA_Reset, CR2_DMA_Set, DISABLE, IS_ADC_DMA_PERIPH, and IS_FUNCTIONAL_STATE.

Referenced by main().

void ADC_ExternalTrigConvCmd | ( | ADC_TypeDef * | ADCx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the ADCx conversion through external trigger.

Parameters:
ADCx,: where x can be 1, 2 or 3 to select the ADC peripheral.
NewState,: new state of the selected ADC external trigger start of conversion. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 686 of file stm32f10x_adc.c.

References assert_param, ADC_TypeDef::CR2, CR2_EXTTRIG_Reset, CR2_EXTTRIG_Set, DISABLE, IS_ADC_ALL_PERIPH, and IS_FUNCTIONAL_STATE.

Referenced by main().

void ADC_ExternalTrigInjectedConvCmd | ( | ADC_TypeDef * | ADCx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the ADCx injected channels conversion through external trigger.

Parameters:
ADCx,: where x can be 1, 2 or 3 to select the ADC peripheral.
NewState,: new state of the selected ADC external trigger start of injected conversion. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 824 of file stm32f10x_adc.c.

References assert_param, ADC_TypeDef::CR2, CR2_JEXTTRIG_Reset, CR2_JEXTTRIG_Set, DISABLE, IS_ADC_ALL_PERIPH, and IS_FUNCTIONAL_STATE.

Referenced by main().

void ADC_ExternalTrigInjectedConvConfig | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | ADC_ExternalTrigInjecConv
 | ) |  |

Configures the ADCx external trigger for injected channels conversion.

Parameters:
ADCx,: where x can be 1, 2 or 3 to select the ADC peripheral.
ADC_ExternalTrigInjecConv,: specifies the ADC trigger to start injected conversion. This parameter can be one of the following values:

  • ADC_ExternalTrigInjecConv_T1_TRGO: Timer1 TRGO event selected (for ADC1, ADC2 and ADC3)
  • ADC_ExternalTrigInjecConv_T1_CC4: Timer1 capture compare4 selected (for ADC1, ADC2 and ADC3)
  • ADC_ExternalTrigInjecConv_T2_TRGO: Timer2 TRGO event selected (for ADC1 and ADC2)
  • ADC_ExternalTrigInjecConv_T2_CC1: Timer2 capture compare1 selected (for ADC1 and ADC2)
  • ADC_ExternalTrigInjecConv_T3_CC4: Timer3 capture compare4 selected (for ADC1 and ADC2)
  • ADC_ExternalTrigInjecConv_T4_TRGO: Timer4 TRGO event selected (for ADC1 and ADC2)
  • ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4: External interrupt line 15 or Timer8 capture compare4 event selected (for ADC1 and ADC2)
  • ADC_ExternalTrigInjecConv_T4_CC3: Timer4 capture compare3 selected (for ADC3 only)
  • ADC_ExternalTrigInjecConv_T8_CC2: Timer8 capture compare2 selected (for ADC3 only)
  • ADC_ExternalTrigInjecConv_T8_CC4: Timer8 capture compare4 selected (for ADC3 only)
  • ADC_ExternalTrigInjecConv_T5_TRGO: Timer5 TRGO event selected (for ADC3 only)
  • ADC_ExternalTrigInjecConv_T5_CC4: Timer5 capture compare4 selected (for ADC3 only)
  • ADC_ExternalTrigInjecConv_None: Injected conversion started by software and not by external trigger (for ADC1, ADC2 and ADC3)
Return values:
None

Definition at line 799 of file stm32f10x_adc.c.

References assert_param, ADC_TypeDef::CR2, CR2_JEXTSEL_Reset, IS_ADC_ALL_PERIPH, and IS_ADC_EXT_INJEC_TRIG.

Referenced by main().

FlagStatus ADC_GetCalibrationStatus ( ADC_TypeDef * ADCx )

Gets the selected ADC calibration status.

Parameters:
ADCx,: where x can be 1, 2 or 3 to select the ADC peripheral.
Return values:
The new state of ADC calibration (SET or RESET).

Definition at line 430 of file stm32f10x_adc.c.

References assert_param, ADC_TypeDef::CR2, CR2_CAL_Set, IS_ADC_ALL_PERIPH, RESET, and SET.

Referenced by main().

uint16_t ADC_GetConversionValue ( ADC_TypeDef * ADCx )

Returns the last ADCx conversion result data for regular channel.

Parameters:
ADCx,: where x can be 1, 2 or 3 to select the ADC peripheral.
Return values:
The Data conversion value.

Definition at line 708 of file stm32f10x_adc.c.

References assert_param, ADC_TypeDef::DR, and IS_ADC_ALL_PERIPH.

Referenced by ADC1_2_IRQHandler().

uint32_t ADC_GetDualModeConversionValue ( void )

Returns the last ADC1 and ADC2 conversion result data in dual mode.

Return values:
The Data conversion value.

Definition at line 720 of file stm32f10x_adc.c.

References DR_ADDRESS.

FlagStatus ADC_GetFlagStatus | ( | ADC_TypeDef * | ADCx,
 |  | uint8_t | ADC_FLAG
 | ) |  |

Checks whether the specified ADC flag is set or not.

Parameters:
ADCx,: where x can be 1, 2 or 3 to select the ADC peripheral.
ADC_FLAG,: specifies the flag to check. This parameter can be one of the following values:

  • ADC_FLAG_AWD: Analog watchdog flag
  • ADC_FLAG_EOC: End of conversion flag
  • ADC_FLAG_JEOC: End of injected group conversion flag
  • ADC_FLAG_JSTRT: Start of injected group conversion flag
  • ADC_FLAG_STRT: Start of regular group conversion flag
Return values:
The new state of ADC_FLAG (SET or RESET).

Definition at line 1195 of file stm32f10x_adc.c.

References assert_param, IS_ADC_ALL_PERIPH, IS_ADC_GET_FLAG, RESET, SET, and ADC_TypeDef::SR.

uint16_t ADC_GetInjectedConversionValue | ( | ADC_TypeDef * | ADCx,
 |  | uint8_t | ADC_InjectedChannel
 | ) |  |

Returns the ADC injected channel conversion result.

Parameters:
ADCx,: where x can be 1, 2 or 3 to select the ADC peripheral.
ADC_InjectedChannel,: the converted ADC injected channel. This parameter can be one of the following values:

  • ADC_InjectedChannel_1: Injected Channel1 selected
  • ADC_InjectedChannel_2: Injected Channel2 selected
  • ADC_InjectedChannel_3: Injected Channel3 selected
  • ADC_InjectedChannel_4: Injected Channel4 selected
Return values:
The Data conversion value.

Definition at line 1052 of file stm32f10x_adc.c.

References assert_param, IS_ADC_ALL_PERIPH, IS_ADC_INJECTED_CHANNEL, and JDR_Offset.

Referenced by ADC1_2_IRQHandler().

ITStatus ADC_GetITStatus | ( | ADC_TypeDef * | ADCx,
 |  | uint16_t | ADC_IT
 | ) |  |

Checks whether the specified ADC interrupt has occurred or not.

Parameters:
ADCx,: where x can be 1, 2 or 3 to select the ADC peripheral.
ADC_IT,: specifies the ADC interrupt source to check. This parameter can be one of the following values:

  • ADC_IT_EOC: End of conversion interrupt mask
  • ADC_IT_AWD: Analog watchdog interrupt mask
  • ADC_IT_JEOC: End of injected conversion interrupt mask
Return values:
The new state of ADC_IT (SET or RESET).

Definition at line 1247 of file stm32f10x_adc.c.

References assert_param, ADC_TypeDef::CR1, IS_ADC_ALL_PERIPH, IS_ADC_GET_IT, RESET, SET, and ADC_TypeDef::SR.

FlagStatus ADC_GetResetCalibrationStatus ( ADC_TypeDef * ADCx )

Gets the selected ADC reset calibration registers status.

Parameters:
ADCx,: where x can be 1, 2 or 3 to select the ADC peripheral.
Return values:
The new state of ADC reset calibration registers (SET or RESET).

Definition at line 392 of file stm32f10x_adc.c.

References assert_param, ADC_TypeDef::CR2, CR2_RSTCAL_Set, IS_ADC_ALL_PERIPH, RESET, and SET.

Referenced by main().

FlagStatus ADC_GetSoftwareStartConvStatus ( ADC_TypeDef * ADCx )

Gets the selected ADC Software start conversion Status.

Parameters:
ADCx,: where x can be 1, 2 or 3 to select the ADC peripheral.
Return values:
The new state of ADC software start conversion (SET or RESET).

Definition at line 481 of file stm32f10x_adc.c.

References assert_param, ADC_TypeDef::CR2, CR2_SWSTART_Set, IS_ADC_ALL_PERIPH, RESET, and SET.

FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus ( ADC_TypeDef * ADCx )

Gets the selected ADC Software start injected conversion Status.

Parameters:
ADCx,: where x can be 1, 2 or 3 to select the ADC peripheral.
Return values:
The new state of ADC software start injected conversion (SET or RESET).

Definition at line 873 of file stm32f10x_adc.c.

References assert_param, ADC_TypeDef::CR2, CR2_JSWSTART_Set, IS_ADC_ALL_PERIPH, RESET, and SET.

void ADC_Init | ( | ADC_TypeDef * | ADCx,
 |  | ADC_InitTypeDef * | ADC_InitStruct
 | ) |  |

Initializes the ADCx peripheral according to the specified parameters in the ADC_InitStruct.

Parameters:
ADCx,: where x can be 1, 2 or 3 to select the ADC peripheral.
ADC_InitStruct,: pointer to an ADC_InitTypeDef structure that contains the configuration information for the specified ADC peripheral.
Return values:
None

Definition at line 218 of file stm32f10x_adc.c.

References ADC_InitTypeDef::ADC_ContinuousConvMode, ADC_InitTypeDef::ADC_DataAlign, ADC_InitTypeDef::ADC_ExternalTrigConv, ADC_InitTypeDef::ADC_Mode, ADC_InitTypeDef::ADC_NbrOfChannel, ADC_InitTypeDef::ADC_ScanConvMode, assert_param, ADC_TypeDef::CR1, CR1_CLEAR_Mask, ADC_TypeDef::CR2, CR2_CLEAR_Mask, IS_ADC_ALL_PERIPH, IS_ADC_DATA_ALIGN, IS_ADC_EXT_TRIG, IS_ADC_MODE, IS_ADC_REGULAR_LENGTH, IS_FUNCTIONAL_STATE, ADC_TypeDef::SQR1, and SQR1_CLEAR_Mask.

Referenced by main().

void ADC_InjectedChannelConfig | ( | ADC_TypeDef * | ADCx,
 |  | uint8_t | ADC_Channel,
 |  | uint8_t | Rank,
 |  | uint8_t | ADC_SampleTime
 | ) |  |

Configures for the selected ADC injected channel its corresponding rank in the sequencer and its sample time.

Parameters:
ADCx,: where x can be 1, 2 or 3 to select the ADC peripheral.
ADC_Channel,: the ADC channel to configure. This parameter can be one of the following values:

  • ADC_Channel_0: ADC Channel0 selected
  • ADC_Channel_1: ADC Channel1 selected
  • ADC_Channel_2: ADC Channel2 selected
  • ADC_Channel_3: ADC Channel3 selected
  • ADC_Channel_4: ADC Channel4 selected
  • ADC_Channel_5: ADC Channel5 selected
  • ADC_Channel_6: ADC Channel6 selected
  • ADC_Channel_7: ADC Channel7 selected
  • ADC_Channel_8: ADC Channel8 selected
  • ADC_Channel_9: ADC Channel9 selected
  • ADC_Channel_10: ADC Channel10 selected
  • ADC_Channel_11: ADC Channel11 selected
  • ADC_Channel_12: ADC Channel12 selected
  • ADC_Channel_13: ADC Channel13 selected
  • ADC_Channel_14: ADC Channel14 selected
  • ADC_Channel_15: ADC Channel15 selected
  • ADC_Channel_16: ADC Channel16 selected
  • ADC_Channel_17: ADC Channel17 selected
Rank,: The rank in the injected group sequencer. This parameter must be between 1 and 4.
ADC_SampleTime,: The sample time value to be set for the selected channel. This parameter can be one of the following values:

  • ADC_SampleTime_1Cycles5: Sample time equal to 1.5 cycles
  • ADC_SampleTime_7Cycles5: Sample time equal to 7.5 cycles
  • ADC_SampleTime_13Cycles5: Sample time equal to 13.5 cycles
  • ADC_SampleTime_28Cycles5: Sample time equal to 28.5 cycles
  • ADC_SampleTime_41Cycles5: Sample time equal to 41.5 cycles
  • ADC_SampleTime_55Cycles5: Sample time equal to 55.5 cycles
  • ADC_SampleTime_71Cycles5: Sample time equal to 71.5 cycles
  • ADC_SampleTime_239Cycles5: Sample time equal to 239.5 cycles
Return values:
None

Definition at line 930 of file stm32f10x_adc.c.

References ADC_Channel_9, assert_param, IS_ADC_ALL_PERIPH, IS_ADC_CHANNEL, IS_ADC_INJECTED_RANK, IS_ADC_SAMPLE_TIME, ADC_TypeDef::JSQR, JSQR_JL_Set, JSQR_JSQ_Set, ADC_TypeDef::SMPR1, SMPR1_SMP_Set, ADC_TypeDef::SMPR2, and SMPR2_SMP_Set.

Referenced by main().

void ADC_InjectedDiscModeCmd | ( | ADC_TypeDef * | ADCx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the discontinuous mode for injected group channel for the specified ADC.

Parameters:
ADCx,: where x can be 1, 2 or 3 to select the ADC peripheral.
NewState,: new state of the selected ADC discontinuous mode on injected group channel. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 760 of file stm32f10x_adc.c.

References assert_param, ADC_TypeDef::CR1, CR1_JDISCEN_Reset, CR1_JDISCEN_Set, DISABLE, IS_ADC_ALL_PERIPH, and IS_FUNCTIONAL_STATE.

void ADC_InjectedSequencerLengthConfig | ( | ADC_TypeDef * | ADCx,
 |  | uint8_t | Length
 | ) |  |

Configures the sequencer length for injected channels.

Parameters:
ADCx,: where x can be 1, 2 or 3 to select the ADC peripheral.
Length,: The sequencer length. This parameter must be a number between 1 to 4.
Return values:
None

Definition at line 993 of file stm32f10x_adc.c.

References assert_param, IS_ADC_ALL_PERIPH, IS_ADC_INJECTED_LENGTH, ADC_TypeDef::JSQR, and JSQR_JL_Reset.

Referenced by main().

void ADC_ITConfig | ( | ADC_TypeDef * | ADCx,
 |  | uint16_t | ADC_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified ADC interrupts.

Parameters:
ADCx,: where x can be 1, 2 or 3 to select the ADC peripheral.
ADC_IT,: specifies the ADC interrupt sources to be enabled or disabled. This parameter can be any combination of the following values:

  • ADC_IT_EOC: End of conversion interrupt mask
  • ADC_IT_AWD: Analog watchdog interrupt mask
  • ADC_IT_JEOC: End of injected conversion interrupt mask
NewState,: new state of the specified ADC interrupts. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 353 of file stm32f10x_adc.c.

References assert_param, ADC_TypeDef::CR1, DISABLE, IS_ADC_ALL_PERIPH, IS_ADC_IT, and IS_FUNCTIONAL_STATE.

Referenced by main().

void ADC_RegularChannelConfig | ( | ADC_TypeDef * | ADCx,
 |  | uint8_t | ADC_Channel,
 |  | uint8_t | Rank,
 |  | uint8_t | ADC_SampleTime
 | ) |  |

Configures for the selected ADC regular channel its corresponding rank in the sequencer and its sample time.

Parameters:
ADCx,: where x can be 1, 2 or 3 to select the ADC peripheral.
ADC_Channel,: the ADC channel to configure. This parameter can be one of the following values:

  • ADC_Channel_0: ADC Channel0 selected
  • ADC_Channel_1: ADC Channel1 selected
  • ADC_Channel_2: ADC Channel2 selected
  • ADC_Channel_3: ADC Channel3 selected
  • ADC_Channel_4: ADC Channel4 selected
  • ADC_Channel_5: ADC Channel5 selected
  • ADC_Channel_6: ADC Channel6 selected
  • ADC_Channel_7: ADC Channel7 selected
  • ADC_Channel_8: ADC Channel8 selected
  • ADC_Channel_9: ADC Channel9 selected
  • ADC_Channel_10: ADC Channel10 selected
  • ADC_Channel_11: ADC Channel11 selected
  • ADC_Channel_12: ADC Channel12 selected
  • ADC_Channel_13: ADC Channel13 selected
  • ADC_Channel_14: ADC Channel14 selected
  • ADC_Channel_15: ADC Channel15 selected
  • ADC_Channel_16: ADC Channel16 selected
  • ADC_Channel_17: ADC Channel17 selected
Rank,: The rank in the regular group sequencer. This parameter must be between 1 to 16.
ADC_SampleTime,: The sample time value to be set for the selected channel. This parameter can be one of the following values:

  • ADC_SampleTime_1Cycles5: Sample time equal to 1.5 cycles
  • ADC_SampleTime_7Cycles5: Sample time equal to 7.5 cycles
  • ADC_SampleTime_13Cycles5: Sample time equal to 13.5 cycles
  • ADC_SampleTime_28Cycles5: Sample time equal to 28.5 cycles
  • ADC_SampleTime_41Cycles5: Sample time equal to 41.5 cycles
  • ADC_SampleTime_55Cycles5: Sample time equal to 55.5 cycles
  • ADC_SampleTime_71Cycles5: Sample time equal to 71.5 cycles
  • ADC_SampleTime_239Cycles5: Sample time equal to 239.5 cycles
Return values:
None

Definition at line 590 of file stm32f10x_adc.c.

References ADC_Channel_9, assert_param, IS_ADC_ALL_PERIPH, IS_ADC_CHANNEL, IS_ADC_REGULAR_RANK, IS_ADC_SAMPLE_TIME, ADC_TypeDef::SMPR1, SMPR1_SMP_Set, ADC_TypeDef::SMPR2, SMPR2_SMP_Set, ADC_TypeDef::SQR1, SQR1_SQ_Set, ADC_TypeDef::SQR2, SQR2_SQ_Set, ADC_TypeDef::SQR3, and SQR3_SQ_Set.

Referenced by main().

void ADC_ResetCalibration ( ADC_TypeDef * ADCx )

Resets the selected ADC calibration registers.

Parameters:
ADCx,: where x can be 1, 2 or 3 to select the ADC peripheral.
Return values:
None

Definition at line 379 of file stm32f10x_adc.c.

References assert_param, ADC_TypeDef::CR2, CR2_RSTCAL_Set, and IS_ADC_ALL_PERIPH.

Referenced by main().

void ADC_SetInjectedOffset | ( | ADC_TypeDef * | ADCx,
 |  | uint8_t | ADC_InjectedChannel,
 |  | uint16_t | Offset
 | ) |  |

Set the injected channels conversion value offset.

Parameters:
ADCx,: where x can be 1, 2 or 3 to select the ADC peripheral.
ADC_InjectedChannel,: the ADC injected channel to set its offset. This parameter can be one of the following values:

  • ADC_InjectedChannel_1: Injected Channel1 selected
  • ADC_InjectedChannel_2: Injected Channel2 selected
  • ADC_InjectedChannel_3: Injected Channel3 selected
  • ADC_InjectedChannel_4: Injected Channel4 selected
Offset,: the offset value for the selected ADC injected channel This parameter must be a 12bit value.
Return values:
None

Definition at line 1025 of file stm32f10x_adc.c.

References assert_param, IS_ADC_ALL_PERIPH, IS_ADC_INJECTED_CHANNEL, and IS_ADC_OFFSET.

void ADC_SoftwareStartConvCmd | ( | ADC_TypeDef * | ADCx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the selected ADC software start conversion .

Parameters:
ADCx,: where x can be 1, 2 or 3 to select the ADC peripheral.
NewState,: new state of the selected ADC software start conversion. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 457 of file stm32f10x_adc.c.

References assert_param, ADC_TypeDef::CR2, CR2_EXTTRIG_SWSTART_Reset, CR2_EXTTRIG_SWSTART_Set, DISABLE, IS_ADC_ALL_PERIPH, and IS_FUNCTIONAL_STATE.

Referenced by main().

void ADC_SoftwareStartInjectedConvCmd | ( | ADC_TypeDef * | ADCx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the selected ADC start of the injected channels conversion.

Parameters:
ADCx,: where x can be 1, 2 or 3 to select the ADC peripheral.
NewState,: new state of the selected ADC software start injected conversion. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 849 of file stm32f10x_adc.c.

References assert_param, ADC_TypeDef::CR2, CR2_JEXTTRIG_JSWSTART_Reset, CR2_JEXTTRIG_JSWSTART_Set, DISABLE, IS_ADC_ALL_PERIPH, and IS_FUNCTIONAL_STATE.

void ADC_StartCalibration ( ADC_TypeDef * ADCx )

Starts the selected ADC calibration process.

Parameters:
ADCx,: where x can be 1, 2 or 3 to select the ADC peripheral.
Return values:
None

Definition at line 417 of file stm32f10x_adc.c.

References assert_param, ADC_TypeDef::CR2, CR2_CAL_Set, and IS_ADC_ALL_PERIPH.

Referenced by main().

void ADC_StructInit ( ADC_InitTypeDef * ADC_InitStruct )

Fills each ADC_InitStruct member with its default value.

Parameters:
ADC_InitStruct : pointer to an ADC_InitTypeDef structure which will be initialized.
Return values:
None

Definition at line 275 of file stm32f10x_adc.c.

References ADC_InitTypeDef::ADC_ContinuousConvMode, ADC_InitTypeDef::ADC_DataAlign, ADC_DataAlign_Right, ADC_InitTypeDef::ADC_ExternalTrigConv, ADC_ExternalTrigConv_T1_CC1, ADC_InitTypeDef::ADC_Mode, ADC_Mode_Independent, ADC_InitTypeDef::ADC_NbrOfChannel, ADC_InitTypeDef::ADC_ScanConvMode, and DISABLE.

void ADC_TempSensorVrefintCmd ( FunctionalState NewState )

Enables or disables the temperature sensor and Vrefint channel.

Parameters:
NewState,: new state of the temperature sensor. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1167 of file stm32f10x_adc.c.

References ADC1, assert_param, CR2_TSVREFE_Reset, CR2_TSVREFE_Set, DISABLE, and IS_FUNCTIONAL_STATE.

Referenced by main().


STM32F10x Standard Peripherals Firmware Library: BKP_Exported_Types

BKP_Exported_Types

BKP


STM32F10x Standard Peripherals Firmware Library: Tamper_Pin_active_level

Defines

Tamper_Pin_active_level

BKP_Exported_Constants

Defines

#define | BKP_TamperPinLevel_High ((uint16_t)0x0000)
#define | BKP_TamperPinLevel_Low ((uint16_t)0x0001)
#define | IS_BKP_TAMPER_PIN_LEVEL(LEVEL)

Define Documentation

#define BKP_TamperPinLevel_High ((uint16_t)0x0000)

Definition at line 58 of file stm32f10x_bkp.h.

#define BKP_TamperPinLevel_Low ((uint16_t)0x0001)

Definition at line 59 of file stm32f10x_bkp.h.

Referenced by main().

#define IS_BKP_TAMPER_PIN_LEVEL ( LEVEL )
Value:
(((LEVEL) == BKP_TamperPinLevel_High) || \
                                        ((LEVEL) == BKP_TamperPinLevel_Low))

Definition at line 60 of file stm32f10x_bkp.h.

Referenced by BKP_TamperPinLevelConfig().


STM32F10x Standard Peripherals Firmware Library: RTC_output_source_to_output_on_the_Tamper_pin

Defines

RTC_output_source_to_output_on_the_Tamper_pin

BKP_Exported_Constants

Defines

#define | BKP_RTCOutputSource_Alarm ((uint16_t)0x0100)
#define | BKP_RTCOutputSource_CalibClock ((uint16_t)0x0080)
#define | BKP_RTCOutputSource_None ((uint16_t)0x0000)
#define | BKP_RTCOutputSource_Second ((uint16_t)0x0300)
#define | IS_BKP_RTC_OUTPUT_SOURCE(SOURCE)

Define Documentation

#define BKP_RTCOutputSource_Alarm ((uint16_t)0x0100)

Definition at line 72 of file stm32f10x_bkp.h.

#define BKP_RTCOutputSource_CalibClock ((uint16_t)0x0080)

Definition at line 71 of file stm32f10x_bkp.h.

Referenced by main().

#define BKP_RTCOutputSource_None ((uint16_t)0x0000)

Definition at line 70 of file stm32f10x_bkp.h.

#define BKP_RTCOutputSource_Second ((uint16_t)0x0300)

Definition at line 73 of file stm32f10x_bkp.h.

#define IS_BKP_RTC_OUTPUT_SOURCE ( SOURCE )
Value:
(((SOURCE) == BKP_RTCOutputSource_None) || \
                                          ((SOURCE) == BKP_RTCOutputSource_CalibClock) || \
                                          ((SOURCE) == BKP_RTCOutputSource_Alarm) || \
                                          ((SOURCE) == BKP_RTCOutputSource_Second))

Definition at line 74 of file stm32f10x_bkp.h.

Referenced by BKP_RTCOutputConfig().


STM32F10x Standard Peripherals Firmware Library: Data_Backup_Register

Defines

Data_Backup_Register

BKP_Exported_Constants

Defines

#define | BKP_DR1 ((uint16_t)0x0004)
#define | BKP_DR10 ((uint16_t)0x0028)
#define | BKP_DR11 ((uint16_t)0x0040)
#define | BKP_DR12 ((uint16_t)0x0044)
#define | BKP_DR13 ((uint16_t)0x0048)
#define | BKP_DR14 ((uint16_t)0x004C)
#define | BKP_DR15 ((uint16_t)0x0050)
#define | BKP_DR16 ((uint16_t)0x0054)
#define | BKP_DR17 ((uint16_t)0x0058)
#define | BKP_DR18 ((uint16_t)0x005C)
#define | BKP_DR19 ((uint16_t)0x0060)
#define | BKP_DR2 ((uint16_t)0x0008)
#define | BKP_DR20 ((uint16_t)0x0064)
#define | BKP_DR21 ((uint16_t)0x0068)
#define | BKP_DR22 ((uint16_t)0x006C)
#define | BKP_DR23 ((uint16_t)0x0070)
#define | BKP_DR24 ((uint16_t)0x0074)
#define | BKP_DR25 ((uint16_t)0x0078)
#define | BKP_DR26 ((uint16_t)0x007C)
#define | BKP_DR27 ((uint16_t)0x0080)
#define | BKP_DR28 ((uint16_t)0x0084)
#define | BKP_DR29 ((uint16_t)0x0088)
#define | BKP_DR3 ((uint16_t)0x000C)
#define | BKP_DR30 ((uint16_t)0x008C)
#define | BKP_DR31 ((uint16_t)0x0090)
#define | BKP_DR32 ((uint16_t)0x0094)
#define | BKP_DR33 ((uint16_t)0x0098)
#define | BKP_DR34 ((uint16_t)0x009C)
#define | BKP_DR35 ((uint16_t)0x00A0)
#define | BKP_DR36 ((uint16_t)0x00A4)
#define | BKP_DR37 ((uint16_t)0x00A8)
#define | BKP_DR38 ((uint16_t)0x00AC)
#define | BKP_DR39 ((uint16_t)0x00B0)
#define | BKP_DR4 ((uint16_t)0x0010)
#define | BKP_DR40 ((uint16_t)0x00B4)
#define | BKP_DR41 ((uint16_t)0x00B8)
#define | BKP_DR42 ((uint16_t)0x00BC)
#define | BKP_DR5 ((uint16_t)0x0014)
#define | BKP_DR6 ((uint16_t)0x0018)
#define | BKP_DR7 ((uint16_t)0x001C)
#define | BKP_DR8 ((uint16_t)0x0020)
#define | BKP_DR9 ((uint16_t)0x0024)
#define | IS_BKP_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x7F)
#define | IS_BKP_DR(DR)

Define Documentation

#define BKP_DR1 ((uint16_t)0x0004)

Definition at line 86 of file stm32f10x_bkp.h.

Referenced by main().

#define BKP_DR10 ((uint16_t)0x0028)

Definition at line 95 of file stm32f10x_bkp.h.

#define BKP_DR11 ((uint16_t)0x0040)

Definition at line 96 of file stm32f10x_bkp.h.

#define BKP_DR12 ((uint16_t)0x0044)

Definition at line 97 of file stm32f10x_bkp.h.

#define BKP_DR13 ((uint16_t)0x0048)

Definition at line 98 of file stm32f10x_bkp.h.

#define BKP_DR14 ((uint16_t)0x004C)

Definition at line 99 of file stm32f10x_bkp.h.

#define BKP_DR15 ((uint16_t)0x0050)

Definition at line 100 of file stm32f10x_bkp.h.

#define BKP_DR16 ((uint16_t)0x0054)

Definition at line 101 of file stm32f10x_bkp.h.

#define BKP_DR17 ((uint16_t)0x0058)

Definition at line 102 of file stm32f10x_bkp.h.

#define BKP_DR18 ((uint16_t)0x005C)

Definition at line 103 of file stm32f10x_bkp.h.

#define BKP_DR19 ((uint16_t)0x0060)

Definition at line 104 of file stm32f10x_bkp.h.

#define BKP_DR2 ((uint16_t)0x0008)

Definition at line 87 of file stm32f10x_bkp.h.

#define BKP_DR20 ((uint16_t)0x0064)

Definition at line 105 of file stm32f10x_bkp.h.

#define BKP_DR21 ((uint16_t)0x0068)

Definition at line 106 of file stm32f10x_bkp.h.

#define BKP_DR22 ((uint16_t)0x006C)

Definition at line 107 of file stm32f10x_bkp.h.

#define BKP_DR23 ((uint16_t)0x0070)

Definition at line 108 of file stm32f10x_bkp.h.

#define BKP_DR24 ((uint16_t)0x0074)

Definition at line 109 of file stm32f10x_bkp.h.

#define BKP_DR25 ((uint16_t)0x0078)

Definition at line 110 of file stm32f10x_bkp.h.

#define BKP_DR26 ((uint16_t)0x007C)

Definition at line 111 of file stm32f10x_bkp.h.

#define BKP_DR27 ((uint16_t)0x0080)

Definition at line 112 of file stm32f10x_bkp.h.

#define BKP_DR28 ((uint16_t)0x0084)

Definition at line 113 of file stm32f10x_bkp.h.

#define BKP_DR29 ((uint16_t)0x0088)

Definition at line 114 of file stm32f10x_bkp.h.

#define BKP_DR3 ((uint16_t)0x000C)

Definition at line 88 of file stm32f10x_bkp.h.

#define BKP_DR30 ((uint16_t)0x008C)

Definition at line 115 of file stm32f10x_bkp.h.

#define BKP_DR31 ((uint16_t)0x0090)

Definition at line 116 of file stm32f10x_bkp.h.

#define BKP_DR32 ((uint16_t)0x0094)

Definition at line 117 of file stm32f10x_bkp.h.

#define BKP_DR33 ((uint16_t)0x0098)

Definition at line 118 of file stm32f10x_bkp.h.

#define BKP_DR34 ((uint16_t)0x009C)

Definition at line 119 of file stm32f10x_bkp.h.

#define BKP_DR35 ((uint16_t)0x00A0)

Definition at line 120 of file stm32f10x_bkp.h.

#define BKP_DR36 ((uint16_t)0x00A4)

Definition at line 121 of file stm32f10x_bkp.h.

#define BKP_DR37 ((uint16_t)0x00A8)

Definition at line 122 of file stm32f10x_bkp.h.

#define BKP_DR38 ((uint16_t)0x00AC)

Definition at line 123 of file stm32f10x_bkp.h.

#define BKP_DR39 ((uint16_t)0x00B0)

Definition at line 124 of file stm32f10x_bkp.h.

#define BKP_DR4 ((uint16_t)0x0010)

Definition at line 89 of file stm32f10x_bkp.h.

#define BKP_DR40 ((uint16_t)0x00B4)

Definition at line 125 of file stm32f10x_bkp.h.

#define BKP_DR41 ((uint16_t)0x00B8)

Definition at line 126 of file stm32f10x_bkp.h.

#define BKP_DR42 ((uint16_t)0x00BC)

Definition at line 127 of file stm32f10x_bkp.h.

#define BKP_DR5 ((uint16_t)0x0014)

Definition at line 90 of file stm32f10x_bkp.h.

#define BKP_DR6 ((uint16_t)0x0018)

Definition at line 91 of file stm32f10x_bkp.h.

#define BKP_DR7 ((uint16_t)0x001C)

Definition at line 92 of file stm32f10x_bkp.h.

#define BKP_DR8 ((uint16_t)0x0020)

Definition at line 93 of file stm32f10x_bkp.h.

#define BKP_DR9 ((uint16_t)0x0024)

Definition at line 94 of file stm32f10x_bkp.h.

#define IS_BKP_CALIBRATION_VALUE ( VALUE ) ((VALUE) <= 0x7F)

Definition at line 144 of file stm32f10x_bkp.h.

Referenced by BKP_SetRTCCalibrationValue().

#define IS_BKP_DR ( DR )
Value:
(((DR) == BKP_DR1)  || ((DR) == BKP_DR2)  || ((DR) == BKP_DR3)  || \
                       ((DR) == BKP_DR4)  || ((DR) == BKP_DR5)  || ((DR) == BKP_DR6)  || \
                       ((DR) == BKP_DR7)  || ((DR) == BKP_DR8)  || ((DR) == BKP_DR9)  || \
                       ((DR) == BKP_DR10) || ((DR) == BKP_DR11) || ((DR) == BKP_DR12) || \
                       ((DR) == BKP_DR13) || ((DR) == BKP_DR14) || ((DR) == BKP_DR15) || \
                       ((DR) == BKP_DR16) || ((DR) == BKP_DR17) || ((DR) == BKP_DR18) || \
                       ((DR) == BKP_DR19) || ((DR) == BKP_DR20) || ((DR) == BKP_DR21) || \
                       ((DR) == BKP_DR22) || ((DR) == BKP_DR23) || ((DR) == BKP_DR24) || \
                       ((DR) == BKP_DR25) || ((DR) == BKP_DR26) || ((DR) == BKP_DR27) || \
                       ((DR) == BKP_DR28) || ((DR) == BKP_DR29) || ((DR) == BKP_DR30) || \
                       ((DR) == BKP_DR31) || ((DR) == BKP_DR32) || ((DR) == BKP_DR33) || \
                       ((DR) == BKP_DR34) || ((DR) == BKP_DR35) || ((DR) == BKP_DR36) || \
                       ((DR) == BKP_DR37) || ((DR) == BKP_DR38) || ((DR) == BKP_DR39) || \
                       ((DR) == BKP_DR40) || ((DR) == BKP_DR41) || ((DR) == BKP_DR42))

Definition at line 129 of file stm32f10x_bkp.h.

Referenced by BKP_ReadBackupRegister(), and BKP_WriteBackupRegister().


STM32F10x Standard Peripherals Firmware Library: BKP_Exported_Macros

BKP_Exported_Macros

BKP


STM32F10x Standard Peripherals Firmware Library: BKP_Exported_Functions

Functions

BKP_Exported_Functions

BKP

Functions

void | BKP_ClearFlag (void)
Clears Tamper Pin Event pending flag.
void | BKP_ClearITPendingBit (void)
Clears Tamper Pin Interrupt pending bit.
void | BKP_DeInit (void)
Deinitializes the BKP peripheral registers to their default reset values.
FlagStatus | BKP_GetFlagStatus (void)
Checks whether the Tamper Pin Event flag is set or not.
ITStatus | BKP_GetITStatus (void)
Checks whether the Tamper Pin Interrupt has occurred or not.
void | BKP_ITConfig (FunctionalState NewState)
Enables or disables the Tamper Pin Interrupt.
uint16_t | BKP_ReadBackupRegister (uint16_t BKP_DR)
Reads data from the specified Data Backup Register.
void | BKP_RTCOutputConfig (uint16_t BKP_RTCOutputSource)
Select the RTC output source to output on the Tamper pin.
void | BKP_SetRTCCalibrationValue (uint8_t CalibrationValue)
Sets RTC Clock Calibration value.
void | BKP_TamperPinCmd (FunctionalState NewState)
Enables or disables the Tamper Pin activation.
void | BKP_TamperPinLevelConfig (uint16_t BKP_TamperPinLevel)
Configures the Tamper Pin active level.
void | BKP_WriteBackupRegister (uint16_t BKP_DR, uint16_t Data)
Writes user data to the specified Data Backup Register.

Function Documentation

void BKP_ClearFlag ( void )

Clears Tamper Pin Event pending flag.

Parameters:
None
Return values:
None

Definition at line 269 of file stm32f10x_bkp.c.

References BKP, and BKP_CSR_CTE.

Referenced by main(), and TAMPER_IRQHandler().

void BKP_ClearITPendingBit ( void )

Clears Tamper Pin Interrupt pending bit.

Parameters:
None
Return values:
None

Definition at line 290 of file stm32f10x_bkp.c.

References BKP, and BKP_CSR_CTI.

Referenced by TAMPER_IRQHandler().

void BKP_DeInit ( void )

Deinitializes the BKP peripheral registers to their default reset values.

Parameters:
None
Return values:
None

Definition at line 120 of file stm32f10x_bkp.c.

References DISABLE, ENABLE, and RCC_BackupResetCmd().

Referenced by RTC_Configuration().

FlagStatus BKP_GetFlagStatus ( void )

Checks whether the Tamper Pin Event flag is set or not.

Parameters:
None
Return values:
The new state of the Tamper Pin Event flag (SET or RESET).

Definition at line 259 of file stm32f10x_bkp.c.

References CSR_TEF_BB.

ITStatus BKP_GetITStatus ( void )

Checks whether the Tamper Pin Interrupt has occurred or not.

Parameters:
None
Return values:
The new state of the Tamper Pin Interrupt (SET or RESET).

Definition at line 280 of file stm32f10x_bkp.c.

References CSR_TIF_BB.

Referenced by TAMPER_IRQHandler().

void BKP_ITConfig ( FunctionalState NewState )

Enables or disables the Tamper Pin Interrupt.

Parameters:
NewState,: new state of the Tamper Pin Interrupt. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 160 of file stm32f10x_bkp.c.

References assert_param, CSR_TPIE_BB, and IS_FUNCTIONAL_STATE.

Referenced by main().

uint16_t BKP_ReadBackupRegister ( uint16_t BKP_DR )

Reads data from the specified Data Backup Register.

Parameters:
BKP_DR,: specifies the Data Backup Register. This parameter can be BKP_DRx where x:[1, 42]
Return values:
The content of the specified Data Backup Register

Definition at line 241 of file stm32f10x_bkp.c.

References assert_param, BKP_BASE, and IS_BKP_DR.

Referenced by CheckBackupReg(), IsBackupRegReset(), and main().

void BKP_RTCOutputConfig ( uint16_t BKP_RTCOutputSource )

Select the RTC output source to output on the Tamper pin.

Parameters:
BKP_RTCOutputSource,: specifies the RTC output source. This parameter can be one of the following values:

  • BKP_RTCOutputSource_None: no RTC output on the Tamper pin.
  • BKP_RTCOutputSource_CalibClock: output the RTC clock with frequency divided by 64 on the Tamper pin.
  • BKP_RTCOutputSource_Alarm: output the RTC Alarm pulse signal on the Tamper pin.
  • BKP_RTCOutputSource_Second: output the RTC Second pulse signal on the Tamper pin.
Return values:
None

Definition at line 180 of file stm32f10x_bkp.c.

References assert_param, BKP, IS_BKP_RTC_OUTPUT_SOURCE, and RTCCR_MASK.

Referenced by main().

void BKP_SetRTCCalibrationValue ( uint8_t CalibrationValue )

Sets RTC Clock Calibration value.

Parameters:
CalibrationValue,: specifies the RTC Clock Calibration value. This parameter must be a number between 0 and 0x7F.
Return values:
None

Definition at line 201 of file stm32f10x_bkp.c.

References assert_param, BKP, IS_BKP_CALIBRATION_VALUE, and RTCCR_CAL_MASK.

void BKP_TamperPinCmd ( FunctionalState NewState )

Enables or disables the Tamper Pin activation.

Parameters:
NewState,: new state of the Tamper Pin activation. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 147 of file stm32f10x_bkp.c.

References assert_param, CR_TPE_BB, and IS_FUNCTIONAL_STATE.

Referenced by main(), and TAMPER_IRQHandler().

void BKP_TamperPinLevelConfig ( uint16_t BKP_TamperPinLevel )

Configures the Tamper Pin active level.

Parameters:
BKP_TamperPinLevel,: specifies the Tamper Pin active level. This parameter can be one of the following values:

  • BKP_TamperPinLevel_High: Tamper pin active on high level
  • BKP_TamperPinLevel_Low: Tamper pin active on low level
Return values:
None

Definition at line 134 of file stm32f10x_bkp.c.

References assert_param, CR_TPAL_BB, and IS_BKP_TAMPER_PIN_LEVEL.

Referenced by main().

void BKP_WriteBackupRegister | ( | uint16_t | BKP_DR,
 |  | uint16_t | Data
 | ) |  |

Writes user data to the specified Data Backup Register.

Parameters:
BKP_DR,: specifies the Data Backup Register. This parameter can be BKP_DRx where x:[1, 42]
Data,: data to write
Return values:
None

Definition at line 222 of file stm32f10x_bkp.c.

References assert_param, BKP_BASE, and IS_BKP_DR.

Referenced by main(), and WriteToBackupReg().


STM32F10x Standard Peripherals Firmware Library: BKP_Private_TypesDefinitions

BKP_Private_TypesDefinitions

BKP


STM32F10x Standard Peripherals Firmware Library: BKP_Private_Defines

Defines

BKP_Private_Defines

BKP

Defines

#define | BKP_OFFSET (BKP_BASE - PERIPH_BASE)
#define | CR_OFFSET (BKP_OFFSET + 0x30)
#define | CR_TPAL_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPAL_BitNumber * 4))
#define | CR_TPE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPE_BitNumber * 4))
#define | CSR_OFFSET (BKP_OFFSET + 0x34)
#define | CSR_TEF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEF_BitNumber * 4))
#define | CSR_TIF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TIF_BitNumber * 4))
#define | CSR_TPIE_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TPIE_BitNumber * 4))
#define | RTCCR_CAL_MASK ((uint16_t)0xFF80)
#define | RTCCR_MASK ((uint16_t)0xFC7F)
#define | TEF_BitNumber 0x08
#define | TIF_BitNumber 0x09
#define | TPAL_BitNumber 0x01
#define | TPE_BitNumber 0x00
#define | TPIE_BitNumber 0x02

Define Documentation

#define BKP_OFFSET (BKP_BASE - PERIPH_BASE)

Definition at line 48 of file stm32f10x_bkp.c.

#define CR_OFFSET (BKP_OFFSET + 0x30)

Definition at line 53 of file stm32f10x_bkp.c.

#define CR_TPAL_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPAL_BitNumber * 4))

Definition at line 55 of file stm32f10x_bkp.c.

Referenced by BKP_TamperPinLevelConfig().

#define CR_TPE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPE_BitNumber * 4))

Definition at line 59 of file stm32f10x_bkp.c.

Referenced by BKP_TamperPinCmd().

#define CSR_OFFSET (BKP_OFFSET + 0x34)

Definition at line 64 of file stm32f10x_bkp.c.

#define CSR_TEF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEF_BitNumber * 4))

Definition at line 74 of file stm32f10x_bkp.c.

Referenced by BKP_GetFlagStatus().

#define CSR_TIF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TIF_BitNumber * 4))

Definition at line 70 of file stm32f10x_bkp.c.

Referenced by BKP_GetITStatus().

#define CSR_TPIE_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TPIE_BitNumber * 4))

Definition at line 66 of file stm32f10x_bkp.c.

Referenced by BKP_ITConfig().

#define RTCCR_CAL_MASK ((uint16_t)0xFF80)

Definition at line 79 of file stm32f10x_bkp.c.

Referenced by BKP_SetRTCCalibrationValue().

#define RTCCR_MASK ((uint16_t)0xFC7F)

Definition at line 80 of file stm32f10x_bkp.c.

Referenced by BKP_RTCOutputConfig().

#define TEF_BitNumber 0x08

Definition at line 73 of file stm32f10x_bkp.c.

#define TIF_BitNumber 0x09

Definition at line 69 of file stm32f10x_bkp.c.

#define TPAL_BitNumber 0x01

Definition at line 54 of file stm32f10x_bkp.c.

#define TPE_BitNumber 0x00

Definition at line 58 of file stm32f10x_bkp.c.

#define TPIE_BitNumber 0x02

Definition at line 65 of file stm32f10x_bkp.c.


STM32F10x Standard Peripherals Firmware Library: BKP_Private_Macros

BKP_Private_Macros

BKP


STM32F10x Standard Peripherals Firmware Library: BKP_Private_Variables

BKP_Private_Variables

BKP


STM32F10x Standard Peripherals Firmware Library: BKP_Private_FunctionPrototypes

BKP_Private_FunctionPrototypes

BKP


STM32F10x Standard Peripherals Firmware Library: BKP_Private_Functions

Functions

BKP_Private_Functions

BKP

Functions

void | BKP_ClearFlag (void)
Clears Tamper Pin Event pending flag.
void | BKP_ClearITPendingBit (void)
Clears Tamper Pin Interrupt pending bit.
void | BKP_DeInit (void)
Deinitializes the BKP peripheral registers to their default reset values.
FlagStatus | BKP_GetFlagStatus (void)
Checks whether the Tamper Pin Event flag is set or not.
ITStatus | BKP_GetITStatus (void)
Checks whether the Tamper Pin Interrupt has occurred or not.
void | BKP_ITConfig (FunctionalState NewState)
Enables or disables the Tamper Pin Interrupt.
uint16_t | BKP_ReadBackupRegister (uint16_t BKP_DR)
Reads data from the specified Data Backup Register.
void | BKP_RTCOutputConfig (uint16_t BKP_RTCOutputSource)
Select the RTC output source to output on the Tamper pin.
void | BKP_SetRTCCalibrationValue (uint8_t CalibrationValue)
Sets RTC Clock Calibration value.
void | BKP_TamperPinCmd (FunctionalState NewState)
Enables or disables the Tamper Pin activation.
void | BKP_TamperPinLevelConfig (uint16_t BKP_TamperPinLevel)
Configures the Tamper Pin active level.
void | BKP_WriteBackupRegister (uint16_t BKP_DR, uint16_t Data)
Writes user data to the specified Data Backup Register.

Function Documentation

void BKP_ClearFlag ( void )

Clears Tamper Pin Event pending flag.

Parameters:
None
Return values:
None

Definition at line 269 of file stm32f10x_bkp.c.

References BKP, and BKP_CSR_CTE.

Referenced by main(), and TAMPER_IRQHandler().

void BKP_ClearITPendingBit ( void )

Clears Tamper Pin Interrupt pending bit.

Parameters:
None
Return values:
None

Definition at line 290 of file stm32f10x_bkp.c.

References BKP, and BKP_CSR_CTI.

Referenced by TAMPER_IRQHandler().

void BKP_DeInit ( void )

Deinitializes the BKP peripheral registers to their default reset values.

Parameters:
None
Return values:
None

Definition at line 120 of file stm32f10x_bkp.c.

References DISABLE, ENABLE, and RCC_BackupResetCmd().

Referenced by RTC_Configuration().

FlagStatus BKP_GetFlagStatus ( void )

Checks whether the Tamper Pin Event flag is set or not.

Parameters:
None
Return values:
The new state of the Tamper Pin Event flag (SET or RESET).

Definition at line 259 of file stm32f10x_bkp.c.

References CSR_TEF_BB.

ITStatus BKP_GetITStatus ( void )

Checks whether the Tamper Pin Interrupt has occurred or not.

Parameters:
None
Return values:
The new state of the Tamper Pin Interrupt (SET or RESET).

Definition at line 280 of file stm32f10x_bkp.c.

References CSR_TIF_BB.

Referenced by TAMPER_IRQHandler().

void BKP_ITConfig ( FunctionalState NewState )

Enables or disables the Tamper Pin Interrupt.

Parameters:
NewState,: new state of the Tamper Pin Interrupt. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 160 of file stm32f10x_bkp.c.

References assert_param, CSR_TPIE_BB, and IS_FUNCTIONAL_STATE.

Referenced by main().

uint16_t BKP_ReadBackupRegister ( uint16_t BKP_DR )

Reads data from the specified Data Backup Register.

Parameters:
BKP_DR,: specifies the Data Backup Register. This parameter can be BKP_DRx where x:[1, 42]
Return values:
The content of the specified Data Backup Register

Definition at line 241 of file stm32f10x_bkp.c.

References assert_param, BKP_BASE, and IS_BKP_DR.

Referenced by CheckBackupReg(), IsBackupRegReset(), and main().

void BKP_RTCOutputConfig ( uint16_t BKP_RTCOutputSource )

Select the RTC output source to output on the Tamper pin.

Parameters:
BKP_RTCOutputSource,: specifies the RTC output source. This parameter can be one of the following values:

  • BKP_RTCOutputSource_None: no RTC output on the Tamper pin.
  • BKP_RTCOutputSource_CalibClock: output the RTC clock with frequency divided by 64 on the Tamper pin.
  • BKP_RTCOutputSource_Alarm: output the RTC Alarm pulse signal on the Tamper pin.
  • BKP_RTCOutputSource_Second: output the RTC Second pulse signal on the Tamper pin.
Return values:
None

Definition at line 180 of file stm32f10x_bkp.c.

References assert_param, BKP, IS_BKP_RTC_OUTPUT_SOURCE, and RTCCR_MASK.

Referenced by main().

void BKP_SetRTCCalibrationValue ( uint8_t CalibrationValue )

Sets RTC Clock Calibration value.

Parameters:
CalibrationValue,: specifies the RTC Clock Calibration value. This parameter must be a number between 0 and 0x7F.
Return values:
None

Definition at line 201 of file stm32f10x_bkp.c.

References assert_param, BKP, IS_BKP_CALIBRATION_VALUE, and RTCCR_CAL_MASK.

void BKP_TamperPinCmd ( FunctionalState NewState )

Enables or disables the Tamper Pin activation.

Parameters:
NewState,: new state of the Tamper Pin activation. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 147 of file stm32f10x_bkp.c.

References assert_param, CR_TPE_BB, and IS_FUNCTIONAL_STATE.

Referenced by main(), and TAMPER_IRQHandler().

void BKP_TamperPinLevelConfig ( uint16_t BKP_TamperPinLevel )

Configures the Tamper Pin active level.

Parameters:
BKP_TamperPinLevel,: specifies the Tamper Pin active level. This parameter can be one of the following values:

  • BKP_TamperPinLevel_High: Tamper pin active on high level
  • BKP_TamperPinLevel_Low: Tamper pin active on low level
Return values:
None

Definition at line 134 of file stm32f10x_bkp.c.

References assert_param, CR_TPAL_BB, and IS_BKP_TAMPER_PIN_LEVEL.

Referenced by main().

void BKP_WriteBackupRegister | ( | uint16_t | BKP_DR,
 |  | uint16_t | Data
 | ) |  |

Writes user data to the specified Data Backup Register.

Parameters:
BKP_DR,: specifies the Data Backup Register. This parameter can be BKP_DRx where x:[1, 42]
Data,: data to write
Return values:
None

Definition at line 222 of file stm32f10x_bkp.c.

References assert_param, BKP_BASE, and IS_BKP_DR.

Referenced by main(), and WriteToBackupReg().


STM32F10x Standard Peripherals Firmware Library: CAN_Exported_Types

Data Structures | Defines

CAN_Exported_Types

CAN

Data Structures

struct | CAN_FilterInitTypeDef
CAN filter init structure definition. More...
struct | CAN_InitTypeDef
CAN init structure definition. More...
struct | CanRxMsg
CAN Rx message structure definition. More...
struct | CanTxMsg
CAN Tx message structure definition. More...

Defines

#define | IS_CAN_ALL_PERIPH(PERIPH)

Define Documentation

#define IS_CAN_ALL_PERIPH ( PERIPH )
Value:
(((PERIPH) == CAN1) || \
                                   ((PERIPH) == CAN2))

Definition at line 46 of file stm32f10x_can.h.

Referenced by CAN_CancelTransmit(), CAN_ClearFlag(), CAN_ClearITPendingBit(), CAN_DBGFreeze(), CAN_DeInit(), CAN_FIFORelease(), CAN_GetFlagStatus(), CAN_GetITStatus(), CAN_GetLastErrorCode(), CAN_GetLSBTransmitErrorCounter(), CAN_GetReceiveErrorCounter(), CAN_Init(), CAN_ITConfig(), CAN_MessagePending(), CAN_OperatingModeRequest(), CAN_Receive(), CAN_Sleep(), CAN_Transmit(), CAN_TransmitStatus(), CAN_TTComModeCmd(), and CAN_WakeUp().


STM32F10x Standard Peripherals Firmware Library: CAN_FilterInitTypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

CAN_FilterInitTypeDef Struct Reference
CAN_Exported_Types

CAN filter init structure definition. More...

#include <stm32f10x_can.h>

Data Fields

FunctionalState CAN_FilterActivation
uint16_t | CAN_FilterFIFOAssignment
uint16_t | CAN_FilterIdHigh
uint16_t | CAN_FilterIdLow
uint16_t | CAN_FilterMaskIdHigh
uint16_t | CAN_FilterMaskIdLow
uint8_t | CAN_FilterMode
uint8_t | CAN_FilterNumber
uint8_t | CAN_FilterScale

Detailed Description

CAN filter init structure definition.

Definition at line 106 of file stm32f10x_can.h.

Field Documentation

FunctionalState CAN_FilterInitTypeDef::CAN_FilterActivation

Enable or disable the filter. This parameter can be set either to ENABLE or DISABLE.

Definition at line 137 of file stm32f10x_can.h.

Referenced by CAN_Config(), CAN_FilterInit(), CAN_Interrupt(), and CAN_Polling().

uint16_t CAN_FilterInitTypeDef::CAN_FilterFIFOAssignment

Specifies the FIFO (0 or 1) which will be assigned to the filter. This parameter can be a value of CAN_filter_FIFO

Definition at line 126 of file stm32f10x_can.h.

Referenced by CAN_Config(), CAN_FilterInit(), CAN_Interrupt(), and CAN_Polling().

uint16_t CAN_FilterInitTypeDef::CAN_FilterIdHigh

Specifies the filter identification number (MSBs for a 32-bit configuration, first one for a 16-bit configuration). This parameter can be a value between 0x0000 and 0xFFFF

Definition at line 108 of file stm32f10x_can.h.

Referenced by CAN_Config(), CAN_FilterInit(), CAN_Interrupt(), and CAN_Polling().

uint16_t CAN_FilterInitTypeDef::CAN_FilterIdLow

Specifies the filter identification number (LSBs for a 32-bit configuration, second one for a 16-bit configuration). This parameter can be a value between 0x0000 and 0xFFFF

Definition at line 112 of file stm32f10x_can.h.

Referenced by CAN_Config(), CAN_FilterInit(), CAN_Interrupt(), and CAN_Polling().

uint16_t CAN_FilterInitTypeDef::CAN_FilterMaskIdHigh

Specifies the filter mask number or identification number, according to the mode (MSBs for a 32-bit configuration, first one for a 16-bit configuration). This parameter can be a value between 0x0000 and 0xFFFF

Definition at line 116 of file stm32f10x_can.h.

Referenced by CAN_Config(), CAN_FilterInit(), CAN_Interrupt(), and CAN_Polling().

uint16_t CAN_FilterInitTypeDef::CAN_FilterMaskIdLow

Specifies the filter mask number or identification number, according to the mode (LSBs for a 32-bit configuration, second one for a 16-bit configuration). This parameter can be a value between 0x0000 and 0xFFFF

Definition at line 121 of file stm32f10x_can.h.

Referenced by CAN_Config(), CAN_FilterInit(), CAN_Interrupt(), and CAN_Polling().

uint8_t CAN_FilterInitTypeDef::CAN_FilterMode

Specifies the filter mode to be initialized. This parameter can be a value of CAN_filter_mode

Definition at line 131 of file stm32f10x_can.h.

Referenced by CAN_Config(), CAN_FilterInit(), CAN_Interrupt(), and CAN_Polling().

uint8_t CAN_FilterInitTypeDef::CAN_FilterNumber

Specifies the filter which will be initialized. It ranges from 0 to 13.

Definition at line 129 of file stm32f10x_can.h.

Referenced by CAN_Config(), CAN_FilterInit(), CAN_Interrupt(), and CAN_Polling().

uint8_t CAN_FilterInitTypeDef::CAN_FilterScale

Specifies the filter scale. This parameter can be a value of CAN_filter_scale

Definition at line 134 of file stm32f10x_can.h.

Referenced by CAN_Config(), CAN_FilterInit(), CAN_Interrupt(), and CAN_Polling().

The documentation for this struct was generated from the following file:
  • stm32f10x_can.h


STM32F10x Standard Peripherals Firmware Library: CAN_InitTypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

CAN_InitTypeDef Struct Reference
CAN_Exported_Types

CAN init structure definition. More...

#include <stm32f10x_can.h>

Data Fields

FunctionalState CAN_ABOM
FunctionalState CAN_AWUM
uint8_t | CAN_BS1
uint8_t | CAN_BS2
uint8_t | CAN_Mode
FunctionalState CAN_NART
uint16_t | CAN_Prescaler
FunctionalState CAN_RFLM
uint8_t | CAN_SJW
FunctionalState CAN_TTCM
FunctionalState CAN_TXFP

Detailed Description

CAN init structure definition.

Definition at line 53 of file stm32f10x_can.h.

Field Documentation

FunctionalState CAN_InitTypeDef::CAN_ABOM

Enable or disable the automatic bus-off management. This parameter can be set either to ENABLE or DISABLE.

Definition at line 81 of file stm32f10x_can.h.

Referenced by CAN_Config(), CAN_Init(), CAN_Interrupt(), CAN_Polling(), and CAN_StructInit().

FunctionalState CAN_InitTypeDef::CAN_AWUM

Enable or disable the automatic wake-up mode. This parameter can be set either to ENABLE or DISABLE.

Definition at line 85 of file stm32f10x_can.h.

Referenced by CAN_Config(), CAN_Init(), CAN_Interrupt(), CAN_Polling(), and CAN_StructInit().

uint8_t CAN_InitTypeDef::CAN_BS1

Specifies the number of time quanta in Bit Segment 1. This parameter can be a value of CAN_time_quantum_in_bit_segment_1

Definition at line 68 of file stm32f10x_can.h.

Referenced by CAN_Config(), CAN_Init(), CAN_Interrupt(), CAN_Polling(), and CAN_StructInit().

uint8_t CAN_InitTypeDef::CAN_BS2

Specifies the number of time quanta in Bit Segment 2. This parameter can be a value of CAN_time_quantum_in_bit_segment_2

Definition at line 72 of file stm32f10x_can.h.

Referenced by CAN_Config(), CAN_Init(), CAN_Interrupt(), CAN_Polling(), and CAN_StructInit().

uint8_t CAN_InitTypeDef::CAN_Mode

Specifies the CAN operating mode. This parameter can be a value of CAN_operating_mode

Definition at line 58 of file stm32f10x_can.h.

Referenced by CAN_Config(), CAN_Init(), CAN_Interrupt(), CAN_Polling(), and CAN_StructInit().

FunctionalState CAN_InitTypeDef::CAN_NART

Enable or disable the no-automatic retransmission mode. This parameter can be set either to ENABLE or DISABLE.

Definition at line 89 of file stm32f10x_can.h.

Referenced by CAN_Config(), CAN_Init(), CAN_Interrupt(), CAN_Polling(), and CAN_StructInit().

uint16_t CAN_InitTypeDef::CAN_Prescaler

Specifies the length of a time quantum. It ranges from 1 to 1024.

Definition at line 55 of file stm32f10x_can.h.

Referenced by CAN_Config(), CAN_Init(), CAN_Interrupt(), CAN_Polling(), and CAN_StructInit().

FunctionalState CAN_InitTypeDef::CAN_RFLM

Enable or disable the Receive FIFO Locked mode. This parameter can be set either to ENABLE or DISABLE.

Definition at line 93 of file stm32f10x_can.h.

Referenced by CAN_Config(), CAN_Init(), CAN_Interrupt(), CAN_Polling(), and CAN_StructInit().

uint8_t CAN_InitTypeDef::CAN_SJW

Specifies the maximum number of time quanta the CAN hardware is allowed to lengthen or shorten a bit to perform resynchronization. This parameter can be a value of CAN_synchronisation_jump_width

Definition at line 62 of file stm32f10x_can.h.

Referenced by CAN_Config(), CAN_Init(), CAN_Interrupt(), CAN_Polling(), and CAN_StructInit().

FunctionalState CAN_InitTypeDef::CAN_TTCM

Enable or disable the time triggered communication mode. This parameter can be set either to ENABLE or DISABLE.

Definition at line 77 of file stm32f10x_can.h.

Referenced by CAN_Config(), CAN_Init(), CAN_Interrupt(), CAN_Polling(), and CAN_StructInit().

FunctionalState CAN_InitTypeDef::CAN_TXFP

Enable or disable the transmit FIFO priority. This parameter can be set either to ENABLE or DISABLE.

Definition at line 97 of file stm32f10x_can.h.

Referenced by CAN_Config(), CAN_Init(), CAN_Interrupt(), CAN_Polling(), and CAN_StructInit().

The documentation for this struct was generated from the following file:
  • stm32f10x_can.h


STM32F10x Standard Peripherals Firmware Library: CanRxMsg Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

CanRxMsg Struct Reference
CAN_Exported_Types

CAN Rx message structure definition. More...

#include <stm32f10x_can.h>

Data Fields

uint8_t | Data [8]
uint8_t | DLC
uint32_t | ExtId
uint8_t | FMI
uint8_t | IDE
uint8_t | RTR
uint32_t | StdId

Detailed Description

CAN Rx message structure definition.

Definition at line 173 of file stm32f10x_can.h.

Field Documentation

uint8_t CanRxMsg::Data[8]

Contains the data to be received. It ranges from 0 to 0xFF.

Definition at line 192 of file stm32f10x_can.h.

Referenced by CAN1_RX0_IRQHandler(), CAN2_RX0_IRQHandler(), CAN_Polling(), CAN_Receive(), Init_RxMes(), and USB_LP_CAN1_RX0_IRQHandler().

uint8_t CanRxMsg::DLC

Specifies the length of the frame that will be received. This parameter can be a value between 0 to 8

Definition at line 189 of file stm32f10x_can.h.

Referenced by CAN1_RX0_IRQHandler(), CAN2_RX0_IRQHandler(), CAN_Polling(), CAN_Receive(), Init_RxMes(), and USB_LP_CAN1_RX0_IRQHandler().

uint32_t CanRxMsg::ExtId

Specifies the extended identifier. This parameter can be a value between 0 to 0x1FFFFFFF.

Definition at line 178 of file stm32f10x_can.h.

Referenced by CAN_Receive(), Init_RxMes(), and USB_LP_CAN1_RX0_IRQHandler().

uint8_t CanRxMsg::FMI

Specifies the index of the filter the message stored in the mailbox passes through. This parameter can be a value between 0 to 0xFF

Definition at line 195 of file stm32f10x_can.h.

Referenced by CAN_Receive(), Init_RxMes(), and USB_LP_CAN1_RX0_IRQHandler().

uint8_t CanRxMsg::IDE

Specifies the type of identifier for the message that will be received. This parameter can be a value of CAN_identifier_type

Definition at line 181 of file stm32f10x_can.h.

Referenced by CAN1_RX0_IRQHandler(), CAN2_RX0_IRQHandler(), CAN_Polling(), CAN_Receive(), Init_RxMes(), and USB_LP_CAN1_RX0_IRQHandler().

uint8_t CanRxMsg::RTR

Specifies the type of frame for the received message. This parameter can be a value of CAN_remote_transmission_request

Definition at line 185 of file stm32f10x_can.h.

Referenced by CAN_Receive().

uint32_t CanRxMsg::StdId

Specifies the standard identifier. This parameter can be a value between 0 to 0x7FF.

Definition at line 175 of file stm32f10x_can.h.

Referenced by CAN1_RX0_IRQHandler(), CAN2_RX0_IRQHandler(), CAN_Polling(), CAN_Receive(), Init_RxMes(), and USB_LP_CAN1_RX0_IRQHandler().

The documentation for this struct was generated from the following file:
  • stm32f10x_can.h


STM32F10x Standard Peripherals Firmware Library: CanTxMsg Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

CanTxMsg Struct Reference
CAN_Exported_Types

CAN Tx message structure definition. More...

#include <stm32f10x_can.h>

Data Fields

uint8_t | Data [8]
uint8_t | DLC
uint32_t | ExtId
uint8_t | IDE
uint8_t | RTR
uint32_t | StdId

Detailed Description

CAN Tx message structure definition.

Definition at line 145 of file stm32f10x_can.h.

Field Documentation

uint8_t CanTxMsg::Data[8]

Contains the data to be transmitted. It ranges from 0 to 0xFF.

Definition at line 165 of file stm32f10x_can.h.

Referenced by CAN_Interrupt(), CAN_Polling(), CAN_Transmit(), and main().

uint8_t CanTxMsg::DLC

Specifies the length of the frame that will be transmitted. This parameter can be a value between 0 to 8

Definition at line 161 of file stm32f10x_can.h.

Referenced by CAN_Config(), CAN_Interrupt(), CAN_Polling(), and CAN_Transmit().

uint32_t CanTxMsg::ExtId

Specifies the extended identifier. This parameter can be a value between 0 to 0x1FFFFFFF.

Definition at line 150 of file stm32f10x_can.h.

Referenced by CAN_Config(), CAN_Interrupt(), and CAN_Transmit().

uint8_t CanTxMsg::IDE

Specifies the type of identifier for the message that will be transmitted. This parameter can be a value of CAN_identifier_type

Definition at line 153 of file stm32f10x_can.h.

Referenced by CAN_Config(), CAN_Interrupt(), CAN_Polling(), and CAN_Transmit().

uint8_t CanTxMsg::RTR

Specifies the type of frame for the message that will be transmitted. This parameter can be a value of CAN_remote_transmission_request

Definition at line 157 of file stm32f10x_can.h.

Referenced by CAN_Config(), CAN_Interrupt(), CAN_Polling(), and CAN_Transmit().

uint32_t CanTxMsg::StdId

Specifies the standard identifier. This parameter can be a value between 0 to 0x7FF.

Definition at line 147 of file stm32f10x_can.h.

Referenced by CAN_Config(), CAN_Interrupt(), CAN_Polling(), and CAN_Transmit().

The documentation for this struct was generated from the following file:
  • stm32f10x_can.h


STM32F10x Standard Peripherals Firmware Library: CAN_sleep_constants

Defines

CAN_sleep_constants

CAN_Exported_Constants

Defines

#define | CAN_InitStatus_Failed ((uint8_t)0x00)
#define | CAN_InitStatus_Success ((uint8_t)0x01)
#define | CAN_Sleep_Failed ((uint8_t)0x00)
#define | CAN_Sleep_Ok ((uint8_t)0x01)

Define Documentation

#define CAN_InitStatus_Failed ((uint8_t)0x00)

CAN initialization failed

Definition at line 212 of file stm32f10x_can.h.

Referenced by CAN_Init().

#define CAN_InitStatus_Success ((uint8_t)0x01)

CAN initialization OK

Definition at line 213 of file stm32f10x_can.h.

Referenced by CAN_Init().

#define CAN_Sleep_Failed ((uint8_t)0x00)

CAN did not enter the sleep mode

Definition at line 462 of file stm32f10x_can.h.

Referenced by CAN_Sleep().

#define CAN_Sleep_Ok ((uint8_t)0x01)

CAN entered the sleep mode

Definition at line 463 of file stm32f10x_can.h.

Referenced by CAN_Sleep().


STM32F10x Standard Peripherals Firmware Library: CAN_Mode

Defines

CAN_Mode

CAN_Exported_Constants

Defines

#define | CAN_Mode_LoopBack ((uint8_t)0x01)
#define | CAN_Mode_Normal ((uint8_t)0x00)
#define | CAN_Mode_Silent ((uint8_t)0x02)
#define | CAN_Mode_Silent_LoopBack ((uint8_t)0x03)
#define | IS_CAN_MODE(MODE)

Define Documentation

#define CAN_Mode_LoopBack ((uint8_t)0x01)

loopback mode

Definition at line 224 of file stm32f10x_can.h.

Referenced by CAN_Interrupt(), and CAN_Polling().

#define CAN_Mode_Normal ((uint8_t)0x00)

normal mode

Definition at line 223 of file stm32f10x_can.h.

Referenced by CAN_Config(), and CAN_StructInit().

#define CAN_Mode_Silent ((uint8_t)0x02)

silent mode

Definition at line 225 of file stm32f10x_can.h.

#define CAN_Mode_Silent_LoopBack ((uint8_t)0x03)

loopback combined with silent mode

Definition at line 226 of file stm32f10x_can.h.

#define IS_CAN_MODE ( MODE )
Value:
(((MODE) == CAN_Mode_Normal) || \
                           ((MODE) == CAN_Mode_LoopBack)|| \
                           ((MODE) == CAN_Mode_Silent) || \
                           ((MODE) == CAN_Mode_Silent_LoopBack))

Definition at line 228 of file stm32f10x_can.h.

Referenced by CAN_Init().


STM32F10x Standard Peripherals Firmware Library: CAN_Operating_Mode

Defines

CAN_Operating_Mode

CAN_Exported_Constants

Defines

#define | CAN_OperatingMode_Initialization ((uint8_t)0x00)
#define | CAN_OperatingMode_Normal ((uint8_t)0x01)
#define | CAN_OperatingMode_Sleep ((uint8_t)0x02)
#define | IS_CAN_OPERATING_MODE(MODE)

Define Documentation

#define CAN_OperatingMode_Initialization ((uint8_t)0x00)

Initialization mode

Definition at line 241 of file stm32f10x_can.h.

Referenced by CAN_OperatingModeRequest().

#define CAN_OperatingMode_Normal ((uint8_t)0x01)

Normal mode

Definition at line 242 of file stm32f10x_can.h.

Referenced by CAN_OperatingModeRequest().

#define CAN_OperatingMode_Sleep ((uint8_t)0x02)

sleep mode

Definition at line 243 of file stm32f10x_can.h.

Referenced by CAN_OperatingModeRequest().

#define IS_CAN_OPERATING_MODE ( MODE )
Value:
(((MODE) == CAN_OperatingMode_Initialization) ||\
                                    ((MODE) == CAN_OperatingMode_Normal)|| \
                                                                                ((MODE) == CAN_OperatingMode_Sleep))

Definition at line 246 of file stm32f10x_can.h.

Referenced by CAN_OperatingModeRequest().


STM32F10x Standard Peripherals Firmware Library: CAN_Mode_Status

Defines

CAN_Mode_Status

CAN_Exported_Constants

Defines

#define | CAN_ModeStatus_Failed ((uint8_t)0x00)
#define | CAN_ModeStatus_Success ((uint8_t)!CAN_ModeStatus_Failed)

Define Documentation

#define CAN_ModeStatus_Failed ((uint8_t)0x00)

CAN entering the specific mode failed

Definition at line 258 of file stm32f10x_can.h.

Referenced by CAN_OperatingModeRequest().

#define CAN_ModeStatus_Success ((uint8_t)!CAN_ModeStatus_Failed)

CAN entering the specific mode Succeed

Definition at line 259 of file stm32f10x_can.h.

Referenced by CAN_OperatingModeRequest().


STM32F10x Standard Peripherals Firmware Library: CAN_synchronisation_jump_width

Defines

CAN_synchronisation_jump_width

CAN_Exported_Constants

Defines

#define | CAN_SJW_1tq ((uint8_t)0x00)
#define | CAN_SJW_2tq ((uint8_t)0x01)
#define | CAN_SJW_3tq ((uint8_t)0x02)
#define | CAN_SJW_4tq ((uint8_t)0x03)
#define | IS_CAN_SJW(SJW)

Define Documentation

#define CAN_SJW_1tq ((uint8_t)0x00)

1 time quantum

Definition at line 270 of file stm32f10x_can.h.

Referenced by CAN_Config(), CAN_Interrupt(), CAN_Polling(), and CAN_StructInit().

#define CAN_SJW_2tq ((uint8_t)0x01)

2 time quantum

Definition at line 271 of file stm32f10x_can.h.

#define CAN_SJW_3tq ((uint8_t)0x02)

3 time quantum

Definition at line 272 of file stm32f10x_can.h.

#define CAN_SJW_4tq ((uint8_t)0x03)

4 time quantum

Definition at line 273 of file stm32f10x_can.h.

#define IS_CAN_SJW ( SJW )
Value:
(((SJW) == CAN_SJW_1tq) || ((SJW) == CAN_SJW_2tq)|| \
                         ((SJW) == CAN_SJW_3tq) || ((SJW) == CAN_SJW_4tq))

Definition at line 275 of file stm32f10x_can.h.

Referenced by CAN_Init().


STM32F10x Standard Peripherals Firmware Library: CAN_time_quantum_in_bit_segment_1

Defines

CAN_time_quantum_in_bit_segment_1

CAN_Exported_Constants

Defines

#define | CAN_BS1_10tq ((uint8_t)0x09)
#define | CAN_BS1_11tq ((uint8_t)0x0A)
#define | CAN_BS1_12tq ((uint8_t)0x0B)
#define | CAN_BS1_13tq ((uint8_t)0x0C)
#define | CAN_BS1_14tq ((uint8_t)0x0D)
#define | CAN_BS1_15tq ((uint8_t)0x0E)
#define | CAN_BS1_16tq ((uint8_t)0x0F)
#define | CAN_BS1_1tq ((uint8_t)0x00)
#define | CAN_BS1_2tq ((uint8_t)0x01)
#define | CAN_BS1_3tq ((uint8_t)0x02)
#define | CAN_BS1_4tq ((uint8_t)0x03)
#define | CAN_BS1_5tq ((uint8_t)0x04)
#define | CAN_BS1_6tq ((uint8_t)0x05)
#define | CAN_BS1_7tq ((uint8_t)0x06)
#define | CAN_BS1_8tq ((uint8_t)0x07)
#define | CAN_BS1_9tq ((uint8_t)0x08)
#define | IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16tq)

Define Documentation

#define CAN_BS1_10tq ((uint8_t)0x09)

10 time quantum

Definition at line 294 of file stm32f10x_can.h.

#define CAN_BS1_11tq ((uint8_t)0x0A)

11 time quantum

Definition at line 295 of file stm32f10x_can.h.

#define CAN_BS1_12tq ((uint8_t)0x0B)

12 time quantum

Definition at line 296 of file stm32f10x_can.h.

#define CAN_BS1_13tq ((uint8_t)0x0C)

13 time quantum

Definition at line 297 of file stm32f10x_can.h.

#define CAN_BS1_14tq ((uint8_t)0x0D)

14 time quantum

Definition at line 298 of file stm32f10x_can.h.

#define CAN_BS1_15tq ((uint8_t)0x0E)

15 time quantum

Definition at line 299 of file stm32f10x_can.h.

#define CAN_BS1_16tq ((uint8_t)0x0F)

16 time quantum

Definition at line 300 of file stm32f10x_can.h.

#define CAN_BS1_1tq ((uint8_t)0x00)

1 time quantum

Definition at line 285 of file stm32f10x_can.h.

#define CAN_BS1_2tq ((uint8_t)0x01)

2 time quantum

Definition at line 286 of file stm32f10x_can.h.

Referenced by CAN_Interrupt(), and CAN_Polling().

#define CAN_BS1_3tq ((uint8_t)0x02)

3 time quantum

Definition at line 287 of file stm32f10x_can.h.

Referenced by CAN_Config().

#define CAN_BS1_4tq ((uint8_t)0x03)

4 time quantum

Definition at line 288 of file stm32f10x_can.h.

Referenced by CAN_StructInit().

#define CAN_BS1_5tq ((uint8_t)0x04)

5 time quantum

Definition at line 289 of file stm32f10x_can.h.

#define CAN_BS1_6tq ((uint8_t)0x05)

6 time quantum

Definition at line 290 of file stm32f10x_can.h.

#define CAN_BS1_7tq ((uint8_t)0x06)

7 time quantum

Definition at line 291 of file stm32f10x_can.h.

#define CAN_BS1_8tq ((uint8_t)0x07)

8 time quantum

Definition at line 292 of file stm32f10x_can.h.

#define CAN_BS1_9tq ((uint8_t)0x08)

9 time quantum

Definition at line 293 of file stm32f10x_can.h.

#define IS_CAN_BS1 ( BS1 ) ((BS1) <= CAN_BS1_16tq)

Definition at line 302 of file stm32f10x_can.h.

Referenced by CAN_Init().


STM32F10x Standard Peripherals Firmware Library: CAN_time_quantum_in_bit_segment_2

Defines

CAN_time_quantum_in_bit_segment_2

CAN_Exported_Constants

Defines

#define | CAN_BS2_1tq ((uint8_t)0x00)
#define | CAN_BS2_2tq ((uint8_t)0x01)
#define | CAN_BS2_3tq ((uint8_t)0x02)
#define | CAN_BS2_4tq ((uint8_t)0x03)
#define | CAN_BS2_5tq ((uint8_t)0x04)
#define | CAN_BS2_6tq ((uint8_t)0x05)
#define | CAN_BS2_7tq ((uint8_t)0x06)
#define | CAN_BS2_8tq ((uint8_t)0x07)
#define | IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8tq)

Define Documentation

#define CAN_BS2_1tq ((uint8_t)0x00)

1 time quantum

Definition at line 311 of file stm32f10x_can.h.

#define CAN_BS2_2tq ((uint8_t)0x01)

2 time quantum

Definition at line 312 of file stm32f10x_can.h.

Referenced by CAN_Config().

#define CAN_BS2_3tq ((uint8_t)0x02)

3 time quantum

Definition at line 313 of file stm32f10x_can.h.

Referenced by CAN_Interrupt(), CAN_Polling(), and CAN_StructInit().

#define CAN_BS2_4tq ((uint8_t)0x03)

4 time quantum

Definition at line 314 of file stm32f10x_can.h.

#define CAN_BS2_5tq ((uint8_t)0x04)

5 time quantum

Definition at line 315 of file stm32f10x_can.h.

#define CAN_BS2_6tq ((uint8_t)0x05)

6 time quantum

Definition at line 316 of file stm32f10x_can.h.

#define CAN_BS2_7tq ((uint8_t)0x06)

7 time quantum

Definition at line 317 of file stm32f10x_can.h.

#define CAN_BS2_8tq ((uint8_t)0x07)

8 time quantum

Definition at line 318 of file stm32f10x_can.h.

#define IS_CAN_BS2 ( BS2 ) ((BS2) <= CAN_BS2_8tq)

Definition at line 320 of file stm32f10x_can.h.

Referenced by CAN_Init().


STM32F10x Standard Peripherals Firmware Library: CAN_clock_prescaler

Defines

CAN_clock_prescaler

CAN_Exported_Constants

Defines

#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))

Define Documentation

#define IS_CAN_PRESCALER ( PRESCALER ) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))

Definition at line 330 of file stm32f10x_can.h.

Referenced by CAN_Init().


STM32F10x Standard Peripherals Firmware Library: CAN_filter_number

Defines

CAN_filter_number

CAN_Exported_Constants

Defines

#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 13)

Define Documentation

#define IS_CAN_FILTER_NUMBER ( NUMBER ) ((NUMBER) <= 13)

Definition at line 340 of file stm32f10x_can.h.

Referenced by CAN_FilterInit().


STM32F10x Standard Peripherals Firmware Library: CAN_filter_mode

Defines

CAN_filter_mode

CAN_Exported_Constants

Defines

#define | CAN_FilterMode_IdList ((uint8_t)0x01)
#define | CAN_FilterMode_IdMask ((uint8_t)0x00)
#define | IS_CAN_FILTER_MODE(MODE)

Define Documentation

#define CAN_FilterMode_IdList ((uint8_t)0x01)

identifier list mode

Definition at line 353 of file stm32f10x_can.h.

#define CAN_FilterMode_IdMask ((uint8_t)0x00)

identifier/mask mode

Definition at line 352 of file stm32f10x_can.h.

Referenced by CAN_Config(), CAN_FilterInit(), CAN_Interrupt(), and CAN_Polling().

#define IS_CAN_FILTER_MODE ( MODE )
Value:
(((MODE) == CAN_FilterMode_IdMask) || \
                                  ((MODE) == CAN_FilterMode_IdList))

Definition at line 355 of file stm32f10x_can.h.

Referenced by CAN_FilterInit().


STM32F10x Standard Peripherals Firmware Library: CAN_filter_scale

Defines

CAN_filter_scale

CAN_Exported_Constants

Defines

#define | CAN_FilterScale_16bit ((uint8_t)0x00)
#define | CAN_FilterScale_32bit ((uint8_t)0x01)
#define | IS_CAN_FILTER_SCALE(SCALE)

Define Documentation

#define CAN_FilterScale_16bit ((uint8_t)0x00)

Two 16-bit filters

Definition at line 365 of file stm32f10x_can.h.

Referenced by CAN_FilterInit().

#define CAN_FilterScale_32bit ((uint8_t)0x01)

One 32-bit filter

Definition at line 366 of file stm32f10x_can.h.

Referenced by CAN_Config(), CAN_FilterInit(), CAN_Interrupt(), and CAN_Polling().

#define IS_CAN_FILTER_SCALE ( SCALE )
Value:
(((SCALE) == CAN_FilterScale_16bit) || \
                                    ((SCALE) == CAN_FilterScale_32bit))

Definition at line 368 of file stm32f10x_can.h.

Referenced by CAN_FilterInit().


STM32F10x Standard Peripherals Firmware Library: CAN_filter_FIFO

Defines

CAN_filter_FIFO

CAN_Exported_Constants

Defines

#define | CAN_Filter_FIFO0 ((uint8_t)0x00)
#define | CAN_Filter_FIFO1 ((uint8_t)0x01)
#define | IS_CAN_FILTER_FIFO(FIFO)

Define Documentation

#define CAN_Filter_FIFO0 ((uint8_t)0x00)

Filter FIFO 0 assignment for filter x

Definition at line 379 of file stm32f10x_can.h.

Referenced by CAN_FilterInit().

#define CAN_Filter_FIFO1 ((uint8_t)0x01)

Filter FIFO 1 assignment for filter x

Definition at line 380 of file stm32f10x_can.h.

Referenced by CAN_FilterInit().

#define IS_CAN_FILTER_FIFO ( FIFO )
Value:
(((FIFO) == CAN_FilterFIFO0) || \
                                  ((FIFO) == CAN_FilterFIFO1))

Definition at line 381 of file stm32f10x_can.h.

Referenced by CAN_FilterInit().


STM32F10x Standard Peripherals Firmware Library: Start_bank_filter_for_slave_CAN

Defines

Start_bank_filter_for_slave_CAN

CAN_Exported_Constants

Defines

#define IS_CAN_BANKNUMBER(BANKNUMBER) (((BANKNUMBER) >= 1) && ((BANKNUMBER) <= 27))

Define Documentation

#define IS_CAN_BANKNUMBER ( BANKNUMBER ) (((BANKNUMBER) >= 1) && ((BANKNUMBER) <= 27))

Definition at line 390 of file stm32f10x_can.h.

Referenced by CAN_SlaveStartBank().


STM32F10x Standard Peripherals Firmware Library: CAN_Tx

Defines

CAN_Tx

CAN_Exported_Constants

Defines

#define | IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08))
#define | IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF))
#define | IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF))
#define | IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))

Define Documentation

#define IS_CAN_DLC ( DLC ) ((DLC) <= ((uint8_t)0x08))

Definition at line 402 of file stm32f10x_can.h.

Referenced by CAN_Transmit().

#define IS_CAN_EXTID ( EXTID ) ((EXTID) <= ((uint32_t)0x1FFFFFFF))

Definition at line 401 of file stm32f10x_can.h.

Referenced by CAN_Transmit().

#define IS_CAN_STDID ( STDID ) ((STDID) <= ((uint32_t)0x7FF))

Definition at line 400 of file stm32f10x_can.h.

Referenced by CAN_Transmit().

#define IS_CAN_TRANSMITMAILBOX ( TRANSMITMAILBOX ) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))

Definition at line 399 of file stm32f10x_can.h.

Referenced by CAN_CancelTransmit(), and CAN_TransmitStatus().


STM32F10x Standard Peripherals Firmware Library: CAN_identifier_type

Defines

CAN_identifier_type

CAN_Exported_Constants

Defines

#define | CAN_Id_Extended ((uint32_t)0x00000004)
#define | CAN_Id_Standard ((uint32_t)0x00000000)
#define | IS_CAN_IDTYPE(IDTYPE)

Define Documentation

#define CAN_Id_Extended ((uint32_t)0x00000004)

Extended Id

Definition at line 413 of file stm32f10x_can.h.

#define CAN_Id_Standard ((uint32_t)0x00000000)

Standard Id

Definition at line 412 of file stm32f10x_can.h.

Referenced by CAN_Receive(), and CAN_Transmit().

#define IS_CAN_IDTYPE ( IDTYPE )
Value:
(((IDTYPE) == CAN_Id_Standard) || \
                               ((IDTYPE) == CAN_Id_Extended))

Definition at line 414 of file stm32f10x_can.h.

Referenced by CAN_Transmit().


STM32F10x Standard Peripherals Firmware Library: CAN_remote_transmission_request

Defines

CAN_remote_transmission_request

CAN_Exported_Constants

Defines

#define | CAN_RTR_Data ((uint32_t)0x00000000)
#define | CAN_RTR_Remote ((uint32_t)0x00000002)
#define | IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_Data) || ((RTR) == CAN_RTR_Remote))

Define Documentation

#define CAN_RTR_Data ((uint32_t)0x00000000)

Data frame

Definition at line 424 of file stm32f10x_can.h.

#define CAN_RTR_Remote ((uint32_t)0x00000002)

Remote frame

Definition at line 425 of file stm32f10x_can.h.

#define IS_CAN_RTR ( RTR ) (((RTR) == CAN_RTR_Data) || ((RTR) == CAN_RTR_Remote))

Definition at line 426 of file stm32f10x_can.h.

Referenced by CAN_Transmit().


STM32F10x Standard Peripherals Firmware Library: CAN_transmit_constants

Defines

CAN_transmit_constants

CAN_Exported_Constants

Defines

#define | CAN_TxStatus_Failed ((uint8_t)0x00)
#define | CAN_TxStatus_NoMailBox ((uint8_t)0x04)
#define | CAN_TxStatus_Ok ((uint8_t)0x01)
#define | CAN_TxStatus_Pending ((uint8_t)0x02)

Define Documentation

#define CAN_TxStatus_Failed ((uint8_t)0x00)

CAN transmission failed

Definition at line 436 of file stm32f10x_can.h.

Referenced by CAN_TransmitStatus().

#define CAN_TxStatus_NoMailBox ((uint8_t)0x04)

CAN cell did not provide an empty mailbox

Definition at line 439 of file stm32f10x_can.h.

Referenced by CAN_Transmit().

#define CAN_TxStatus_Ok ((uint8_t)0x01)

CAN transmission succeeded

Definition at line 437 of file stm32f10x_can.h.

Referenced by CAN_TransmitStatus().

#define CAN_TxStatus_Pending ((uint8_t)0x02)

CAN transmission pending

Definition at line 438 of file stm32f10x_can.h.

Referenced by CAN_TransmitStatus().


STM32F10x Standard Peripherals Firmware Library: CAN_receive_FIFO_number_constants

Defines

CAN_receive_FIFO_number_constants

CAN_Exported_Constants

Defines

#define | CAN_FIFO0 ((uint8_t)0x00)
#define | CAN_FIFO1 ((uint8_t)0x01)
#define | IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))

Define Documentation

#define CAN_FIFO0 ((uint8_t)0x00)

CAN FIFO 0 used to receive

Definition at line 449 of file stm32f10x_can.h.

Referenced by CAN1_RX0_IRQHandler(), CAN2_RX0_IRQHandler(), CAN_FIFORelease(), CAN_Interrupt(), CAN_MessagePending(), CAN_Polling(), CAN_Receive(), and USB_LP_CAN1_RX0_IRQHandler().

#define CAN_FIFO1 ((uint8_t)0x01)

CAN FIFO 1 used to receive

Definition at line 450 of file stm32f10x_can.h.

Referenced by CAN_MessagePending().

#define IS_CAN_FIFO ( FIFO ) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))

Definition at line 452 of file stm32f10x_can.h.

Referenced by CAN_FIFORelease(), CAN_MessagePending(), and CAN_Receive().


STM32F10x Standard Peripherals Firmware Library: CAN_wake_up_constants

Defines

CAN_wake_up_constants

CAN_Exported_Constants

Defines

#define | CAN_WakeUp_Failed ((uint8_t)0x00)
#define | CAN_WakeUp_Ok ((uint8_t)0x01)

Define Documentation

#define CAN_WakeUp_Failed ((uint8_t)0x00)

CAN did not leave the sleep mode

Definition at line 473 of file stm32f10x_can.h.

Referenced by CAN_WakeUp().

#define CAN_WakeUp_Ok ((uint8_t)0x01)

CAN leaved the sleep mode

Definition at line 474 of file stm32f10x_can.h.

Referenced by CAN_WakeUp().


STM32F10x Standard Peripherals Firmware Library: CAN_Error_Code_constants

Defines

CAN_Error_Code_constants

CAN_Exported_Constants

Defines

#define | CAN_ErrorCode_ACKErr ((uint8_t)0x30)
#define | CAN_ErrorCode_BitDominantErr ((uint8_t)0x50)
#define | CAN_ErrorCode_BitRecessiveErr ((uint8_t)0x40)
#define | CAN_ErrorCode_CRCErr ((uint8_t)0x60)
#define | CAN_ErrorCode_FormErr ((uint8_t)0x20)
#define | CAN_ErrorCode_NoErr ((uint8_t)0x00)
#define | CAN_ErrorCode_SoftwareSetErr ((uint8_t)0x70)
#define | CAN_ErrorCode_StuffErr ((uint8_t)0x10)

Define Documentation

#define CAN_ErrorCode_ACKErr ((uint8_t)0x30)

Acknowledgment Error

Definition at line 488 of file stm32f10x_can.h.

#define CAN_ErrorCode_BitDominantErr ((uint8_t)0x50)

Bit Dominant Error

Definition at line 490 of file stm32f10x_can.h.

#define CAN_ErrorCode_BitRecessiveErr ((uint8_t)0x40)

Bit Recessive Error

Definition at line 489 of file stm32f10x_can.h.

#define CAN_ErrorCode_CRCErr ((uint8_t)0x60)

CRC Error

Definition at line 491 of file stm32f10x_can.h.

#define CAN_ErrorCode_FormErr ((uint8_t)0x20)

Form Error

Definition at line 487 of file stm32f10x_can.h.

#define CAN_ErrorCode_NoErr ((uint8_t)0x00)

No Error

Definition at line 485 of file stm32f10x_can.h.

#define CAN_ErrorCode_SoftwareSetErr ((uint8_t)0x70)

Software Set Error

Definition at line 492 of file stm32f10x_can.h.

#define CAN_ErrorCode_StuffErr ((uint8_t)0x10)

Stuff Error

Definition at line 486 of file stm32f10x_can.h.


STM32F10x Standard Peripherals Firmware Library: CAN_flags

Defines

CAN_flags

CAN_Exported_Constants

Defines

#define | CAN_FLAG_BOF ((uint32_t)0x10F00004)
#define | CAN_FLAG_EPV ((uint32_t)0x10F00002)
#define | CAN_FLAG_EWG ((uint32_t)0x10F00001)
#define | CAN_FLAG_FF0 ((uint32_t)0x32000008)
#define | CAN_FLAG_FF1 ((uint32_t)0x34000008)
#define | CAN_FLAG_FMP0 ((uint32_t)0x12000003)
#define | CAN_FLAG_FMP1 ((uint32_t)0x14000003)
#define | CAN_FLAG_FOV0 ((uint32_t)0x32000010)
#define | CAN_FLAG_FOV1 ((uint32_t)0x34000010)
#define | CAN_FLAG_LEC ((uint32_t)0x30F00070)
#define | CAN_FLAG_RQCP0 ((uint32_t)0x38000001)
#define | CAN_FLAG_RQCP1 ((uint32_t)0x38000100)
#define | CAN_FLAG_RQCP2 ((uint32_t)0x38010000)
#define | CAN_FLAG_SLAK ((uint32_t)0x31000012)
#define | CAN_FLAG_WKU ((uint32_t)0x31000008)
#define | IS_CAN_CLEAR_FLAG(FLAG)
#define | IS_CAN_GET_FLAG(FLAG)

Define Documentation

#define CAN_FLAG_BOF ((uint32_t)0x10F00004)

Bus-Off Flag

Definition at line 528 of file stm32f10x_can.h.

#define CAN_FLAG_EPV ((uint32_t)0x10F00002)

Error Passive Flag

Definition at line 527 of file stm32f10x_can.h.

#define CAN_FLAG_EWG ((uint32_t)0x10F00001)

Error Warning Flag

Definition at line 526 of file stm32f10x_can.h.

#define CAN_FLAG_FF0 ((uint32_t)0x32000008)

FIFO 0 Full Flag

Definition at line 513 of file stm32f10x_can.h.

#define CAN_FLAG_FF1 ((uint32_t)0x34000008)

FIFO 1 Full Flag

Definition at line 516 of file stm32f10x_can.h.

#define CAN_FLAG_FMP0 ((uint32_t)0x12000003)

FIFO 0 Message Pending Flag

Definition at line 512 of file stm32f10x_can.h.

#define CAN_FLAG_FMP1 ((uint32_t)0x14000003)

FIFO 1 Message Pending Flag

Definition at line 515 of file stm32f10x_can.h.

#define CAN_FLAG_FOV0 ((uint32_t)0x32000010)

FIFO 0 Overrun Flag

Definition at line 514 of file stm32f10x_can.h.

#define CAN_FLAG_FOV1 ((uint32_t)0x34000010)

FIFO 1 Overrun Flag

Definition at line 517 of file stm32f10x_can.h.

#define CAN_FLAG_LEC ((uint32_t)0x30F00070)

Last error code Flag

Definition at line 529 of file stm32f10x_can.h.

Referenced by CAN_ClearFlag().

#define CAN_FLAG_RQCP0 ((uint32_t)0x38000001)

Request MailBox0 Flag

Definition at line 507 of file stm32f10x_can.h.

#define CAN_FLAG_RQCP1 ((uint32_t)0x38000100)

Request MailBox1 Flag

Definition at line 508 of file stm32f10x_can.h.

#define CAN_FLAG_RQCP2 ((uint32_t)0x38010000)

Request MailBox2 Flag

Definition at line 509 of file stm32f10x_can.h.

#define CAN_FLAG_SLAK ((uint32_t)0x31000012)

Sleep acknowledge Flag

Definition at line 521 of file stm32f10x_can.h.

#define CAN_FLAG_WKU ((uint32_t)0x31000008)

Wake up Flag

Definition at line 520 of file stm32f10x_can.h.

#define IS_CAN_CLEAR_FLAG ( FLAG )
Value:
(((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_RQCP2) || \
                                ((FLAG) == CAN_FLAG_RQCP1)  || ((FLAG) == CAN_FLAG_RQCP0) || \
                                ((FLAG) == CAN_FLAG_FF0)  || ((FLAG) == CAN_FLAG_FOV0) ||\
                                ((FLAG) == CAN_FLAG_FF1) || ((FLAG) == CAN_FLAG_FOV1) || \
                                ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_SLAK))

Definition at line 540 of file stm32f10x_can.h.

Referenced by CAN_ClearFlag().

#define IS_CAN_GET_FLAG ( FLAG )
Value:
(((FLAG) == CAN_FLAG_LEC)  || ((FLAG) == CAN_FLAG_BOF)   || \
                               ((FLAG) == CAN_FLAG_EPV)  || ((FLAG) == CAN_FLAG_EWG)   || \
                               ((FLAG) == CAN_FLAG_WKU)  || ((FLAG) == CAN_FLAG_FOV0)  || \
                               ((FLAG) == CAN_FLAG_FF0)  || ((FLAG) == CAN_FLAG_FMP0)  || \
                               ((FLAG) == CAN_FLAG_FOV1) || ((FLAG) == CAN_FLAG_FF1)   || \
                               ((FLAG) == CAN_FLAG_FMP1) || ((FLAG) == CAN_FLAG_RQCP2) || \
                               ((FLAG) == CAN_FLAG_RQCP1)|| ((FLAG) == CAN_FLAG_RQCP0) || \
                               ((FLAG) == CAN_FLAG_SLAK ))

Definition at line 531 of file stm32f10x_can.h.

Referenced by CAN_GetFlagStatus().


STM32F10x Standard Peripherals Firmware Library: CAN_interrupts

Defines

CAN_interrupts

CAN_Exported_Constants

Defines

#define | CAN_IT_BOF ((uint32_t)0x00000400)
#define | CAN_IT_EPV ((uint32_t)0x00000200)
#define | CAN_IT_ERR ((uint32_t)0x00008000)
#define | CAN_IT_EWG ((uint32_t)0x00000100)
#define | CAN_IT_FF0 ((uint32_t)0x00000004)
#define | CAN_IT_FF1 ((uint32_t)0x00000020)
#define | CAN_IT_FMP0 ((uint32_t)0x00000002)
#define | CAN_IT_FMP1 ((uint32_t)0x00000010)
#define | CAN_IT_FOV0 ((uint32_t)0x00000008)
#define | CAN_IT_FOV1 ((uint32_t)0x00000040)
#define | CAN_IT_LEC ((uint32_t)0x00000800)
#define | CAN_IT_RQCP0 CAN_IT_TME
#define | CAN_IT_RQCP1 CAN_IT_TME
#define | CAN_IT_RQCP2 CAN_IT_TME
#define | CAN_IT_SLK ((uint32_t)0x00020000)
#define | CAN_IT_TME ((uint32_t)0x00000001)
#define | CAN_IT_WKU ((uint32_t)0x00010000)
#define | IS_CAN_CLEAR_IT(IT)
#define | IS_CAN_IT(IT)

Define Documentation

#define CAN_IT_BOF ((uint32_t)0x00000400)

Bus-off Interrupt

Definition at line 573 of file stm32f10x_can.h.

Referenced by CAN_ClearITPendingBit(), and CAN_GetITStatus().

#define CAN_IT_EPV ((uint32_t)0x00000200)

Error passive Interrupt

Definition at line 572 of file stm32f10x_can.h.

Referenced by CAN_ClearITPendingBit(), and CAN_GetITStatus().

#define CAN_IT_ERR ((uint32_t)0x00008000)

Error Interrupt

Definition at line 575 of file stm32f10x_can.h.

Referenced by CAN_ClearITPendingBit(), and CAN_GetITStatus().

#define CAN_IT_EWG ((uint32_t)0x00000100)

Error warning Interrupt

Definition at line 571 of file stm32f10x_can.h.

Referenced by CAN_ClearITPendingBit(), and CAN_GetITStatus().

#define CAN_IT_FF0 ((uint32_t)0x00000004)

FIFO 0 full Interrupt

Definition at line 560 of file stm32f10x_can.h.

Referenced by CAN_ClearITPendingBit(), and CAN_GetITStatus().

#define CAN_IT_FF1 ((uint32_t)0x00000020)

FIFO 1 full Interrupt

Definition at line 563 of file stm32f10x_can.h.

Referenced by CAN_ClearITPendingBit(), and CAN_GetITStatus().

#define CAN_IT_FMP0 ((uint32_t)0x00000002)

FIFO 0 message pending Interrupt

Definition at line 559 of file stm32f10x_can.h.

Referenced by CAN_GetITStatus(), CAN_Interrupt(), and main().

#define CAN_IT_FMP1 ((uint32_t)0x00000010)

FIFO 1 message pending Interrupt

Definition at line 562 of file stm32f10x_can.h.

Referenced by CAN_GetITStatus().

#define CAN_IT_FOV0 ((uint32_t)0x00000008)

FIFO 0 overrun Interrupt

Definition at line 561 of file stm32f10x_can.h.

Referenced by CAN_ClearITPendingBit(), and CAN_GetITStatus().

#define CAN_IT_FOV1 ((uint32_t)0x00000040)

FIFO 1 overrun Interrupt

Definition at line 564 of file stm32f10x_can.h.

Referenced by CAN_ClearITPendingBit(), and CAN_GetITStatus().

#define CAN_IT_LEC ((uint32_t)0x00000800)

Last error code Interrupt

Definition at line 574 of file stm32f10x_can.h.

Referenced by CAN_ClearITPendingBit(), and CAN_GetITStatus().

#define CAN_IT_RQCP0 CAN_IT_TME

Definition at line 578 of file stm32f10x_can.h.

#define CAN_IT_RQCP1 CAN_IT_TME

Definition at line 579 of file stm32f10x_can.h.

#define CAN_IT_RQCP2 CAN_IT_TME

Definition at line 580 of file stm32f10x_can.h.

#define CAN_IT_SLK ((uint32_t)0x00020000)

Sleep acknowledge Interrupt

Definition at line 568 of file stm32f10x_can.h.

Referenced by CAN_ClearITPendingBit(), and CAN_GetITStatus().

#define CAN_IT_TME ((uint32_t)0x00000001)

Transmit mailbox empty Interrupt

Definition at line 556 of file stm32f10x_can.h.

Referenced by CAN_ClearITPendingBit(), and CAN_GetITStatus().

#define CAN_IT_WKU ((uint32_t)0x00010000)

Wake-up Interrupt

Definition at line 567 of file stm32f10x_can.h.

Referenced by CAN_ClearITPendingBit(), and CAN_GetITStatus().

#define IS_CAN_CLEAR_IT ( IT )
Value:
(((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0)    ||\
                             ((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1)    ||\
                             ((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG)    ||\
                             ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF)    ||\
                             ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR)    ||\
                             ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))

Definition at line 591 of file stm32f10x_can.h.

Referenced by CAN_ClearITPendingBit().

#define IS_CAN_IT ( IT )
Value:
(((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0)  ||\
                             ((IT) == CAN_IT_FF0)  || ((IT) == CAN_IT_FOV0)  ||\
                             ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1)   ||\
                             ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG)   ||\
                             ((IT) == CAN_IT_EPV)  || ((IT) == CAN_IT_BOF)   ||\
                             ((IT) == CAN_IT_LEC)  || ((IT) == CAN_IT_ERR)   ||\
                             ((IT) == CAN_IT_WKU)  || ((IT) == CAN_IT_SLK))

Definition at line 583 of file stm32f10x_can.h.

Referenced by CAN_GetITStatus(), and CAN_ITConfig().


STM32F10x Standard Peripherals Firmware Library: CAN_Legacy

Defines

CAN_Legacy

CAN_Exported_Constants

Defines

#define | CAN_FilterFIFO0 CAN_Filter_FIFO0
#define | CAN_FilterFIFO1 CAN_Filter_FIFO1
#define | CAN_ID_EXT CAN_Id_Extended
#define | CAN_ID_STD CAN_Id_Standard
#define | CAN_NO_MB CAN_TxStatus_NoMailBox
#define | CAN_RTR_DATA CAN_RTR_Data
#define | CAN_RTR_REMOTE CAN_RTR_Remote
#define | CANINITFAILED CAN_InitStatus_Failed
#define | CANINITOK CAN_InitStatus_Success
#define | CANSLEEPFAILED CAN_Sleep_Failed
#define | CANSLEEPOK CAN_Sleep_Ok
#define | CANTXFAILE CAN_TxStatus_Failed
#define | CANTXOK CAN_TxStatus_Ok
#define | CANTXPENDING CAN_TxStatus_Pending
#define | CANWAKEUPFAILED CAN_WakeUp_Failed
#define | CANWAKEUPOK CAN_WakeUp_Ok

Define Documentation

#define CAN_FilterFIFO0 CAN_Filter_FIFO0

Definition at line 607 of file stm32f10x_can.h.

#define CAN_FilterFIFO1 CAN_Filter_FIFO1

Definition at line 608 of file stm32f10x_can.h.

#define CAN_ID_EXT CAN_Id_Extended

Definition at line 610 of file stm32f10x_can.h.

Referenced by CAN_Interrupt(), and USB_LP_CAN1_RX0_IRQHandler().

#define CAN_ID_STD CAN_Id_Standard

Definition at line 609 of file stm32f10x_can.h.

Referenced by CAN1_RX0_IRQHandler(), CAN2_RX0_IRQHandler(), CAN_Config(), CAN_Polling(), Init_RxMes(), and USB_LP_CAN1_RX0_IRQHandler().

#define CAN_NO_MB CAN_TxStatus_NoMailBox

Definition at line 616 of file stm32f10x_can.h.

#define CAN_RTR_DATA CAN_RTR_Data

Definition at line 611 of file stm32f10x_can.h.

Referenced by CAN_Config(), CAN_Interrupt(), and CAN_Polling().

#define CAN_RTR_REMOTE CAN_RTR_Remote

Definition at line 612 of file stm32f10x_can.h.

#define CANINITFAILED CAN_InitStatus_Failed

Definition at line 605 of file stm32f10x_can.h.

#define CANINITOK CAN_InitStatus_Success

Definition at line 606 of file stm32f10x_can.h.

#define CANSLEEPFAILED CAN_Sleep_Failed

Definition at line 617 of file stm32f10x_can.h.

#define CANSLEEPOK CAN_Sleep_Ok

Definition at line 618 of file stm32f10x_can.h.

#define CANTXFAILE CAN_TxStatus_Failed

Definition at line 613 of file stm32f10x_can.h.

#define CANTXOK CAN_TxStatus_Ok

Definition at line 614 of file stm32f10x_can.h.

Referenced by CAN_Polling().

#define CANTXPENDING CAN_TxStatus_Pending

Definition at line 615 of file stm32f10x_can.h.

#define CANWAKEUPFAILED CAN_WakeUp_Failed

Definition at line 619 of file stm32f10x_can.h.

#define CANWAKEUPOK CAN_WakeUp_Ok

Definition at line 620 of file stm32f10x_can.h.


STM32F10x Standard Peripherals Firmware Library: CAN_Exported_Macros

CAN_Exported_Macros

CAN


STM32F10x Standard Peripherals Firmware Library: CAN_Exported_Functions

Functions

CAN_Exported_Functions

CAN

Functions

void | CAN_CancelTransmit (CAN_TypeDef *CANx, uint8_t Mailbox)
Cancels a transmit request.
void | CAN_ClearFlag (CAN_TypeDef *CANx, uint32_t CAN_FLAG)
Clears the CAN's pending flags.
void | CAN_ClearITPendingBit (CAN_TypeDef *CANx, uint32_t CAN_IT)
Clears the CANx's interrupt pending bits.
void | CAN_DBGFreeze (CAN_TypeDef *CANx, FunctionalState NewState)
Enables or disables the DBG Freeze for CAN.
void | CAN_DeInit (CAN_TypeDef *CANx)
Deinitializes the CAN peripheral registers to their default reset values.
void | CAN_FIFORelease (CAN_TypeDef *CANx, uint8_t FIFONumber)
Releases the specified FIFO.
void | CAN_FilterInit (CAN_FilterInitTypeDef *CAN_FilterInitStruct)
Initializes the CAN peripheral according to the specified parameters in the CAN_FilterInitStruct.
FlagStatus | CAN_GetFlagStatus (CAN_TypeDef *CANx, uint32_t CAN_FLAG)
Checks whether the specified CAN flag is set or not.
ITStatus | CAN_GetITStatus (CAN_TypeDef *CANx, uint32_t CAN_IT)
Checks whether the specified CANx interrupt has occurred or not.
uint8_t | CAN_GetLastErrorCode (CAN_TypeDef *CANx)
Returns the CANx's last error code (LEC).
uint8_t | CAN_GetLSBTransmitErrorCounter (CAN_TypeDef *CANx)
Returns the LSB of the 9-bit CANx Transmit Error Counter(TEC).
uint8_t | CAN_GetReceiveErrorCounter (CAN_TypeDef *CANx)
Returns the CANx Receive Error Counter (REC).
uint8_t | CAN_Init (CAN_TypeDef *CANx, CAN_InitTypeDef *CAN_InitStruct)
Initializes the CAN peripheral according to the specified parameters in the CAN_InitStruct.
void | CAN_ITConfig (CAN_TypeDef *CANx, uint32_t CAN_IT, FunctionalState NewState)
Enables or disables the specified CANx interrupts.
uint8_t | CAN_MessagePending (CAN_TypeDef *CANx, uint8_t FIFONumber)
Returns the number of pending messages.
uint8_t | CAN_OperatingModeRequest (CAN_TypeDef *CANx, uint8_t CAN_OperatingMode)
Select the CAN Operation mode.
void | CAN_Receive (CAN_TypeDef *CANx, uint8_t FIFONumber, CanRxMsg *RxMessage)
Receives a message.
void | CAN_SlaveStartBank (uint8_t CAN_BankNumber)
Select the start bank filter for slave CAN.
uint8_t | CAN_Sleep (CAN_TypeDef *CANx)
Enters the low power mode.
void | CAN_StructInit (CAN_InitTypeDef *CAN_InitStruct)
Fills each CAN_InitStruct member with its default value.
uint8_t | CAN_Transmit (CAN_TypeDef *CANx, CanTxMsg *TxMessage)
Initiates the transmission of a message.
uint8_t | CAN_TransmitStatus (CAN_TypeDef *CANx, uint8_t TransmitMailbox)
Checks the transmission of a message.
void | CAN_TTComModeCmd (CAN_TypeDef *CANx, FunctionalState NewState)
Enables or disabes the CAN Time TriggerOperation communication mode.
uint8_t | CAN_WakeUp (CAN_TypeDef *CANx)
Wakes the CAN up.

Function Documentation

void CAN_CancelTransmit | ( | CAN_TypeDef * | CANx,
 |  | uint8_t | Mailbox
 | ) |  |

Cancels a transmit request.

Parameters:
CANx,: where x can be 1 or 2 to to select the CAN peripheral.
Mailbox,: Mailbox number.
Return values:
None.

Definition at line 643 of file stm32f10x_can.c.

References assert_param, CAN_TSR_ABRQ0, CAN_TSR_ABRQ1, CAN_TSR_ABRQ2, CAN_TXMAILBOX_0, CAN_TXMAILBOX_1, CAN_TXMAILBOX_2, IS_CAN_ALL_PERIPH, IS_CAN_TRANSMITMAILBOX, and CAN_TypeDef::TSR.

void CAN_ClearFlag | ( | CAN_TypeDef * | CANx,
 |  | uint32_t | CAN_FLAG
 | ) |  |

Clears the CAN's pending flags.

Parameters:
CANx,: where x can be 1 or 2 to to select the CAN peripheral.
CAN_FLAG,: specifies the flag to clear. This parameter can be one of the following flags:

  • CAN_FLAG_RQCP0
  • CAN_FLAG_RQCP1
  • CAN_FLAG_RQCP2
  • CAN_FLAG_FF1
  • CAN_FLAG_FOV1
  • CAN_FLAG_FF0
  • CAN_FLAG_FOV0
  • CAN_FLAG_WKU
  • CAN_FLAG_SLAK
  • CAN_FLAG_LEC
Return values:
None.

Definition at line 1143 of file stm32f10x_can.c.

References assert_param, CAN_FLAG_LEC, CAN_FLAGS_RF0R, CAN_FLAGS_RF1R, CAN_FLAGS_TSR, CAN_TypeDef::ESR, IS_CAN_ALL_PERIPH, IS_CAN_CLEAR_FLAG, CAN_TypeDef::MSR, RESET, CAN_TypeDef::RF0R, CAN_TypeDef::RF1R, and CAN_TypeDef::TSR.

void CAN_ClearITPendingBit | ( | CAN_TypeDef * | CANx,
 |  | uint32_t | CAN_IT
 | ) |  |

Clears the CANx's interrupt pending bits.

Parameters:
CANx,: where x can be 1 or 2 to to select the CAN peripheral.
CAN_IT,: specifies the interrupt pending bit to clear.

  • CAN_IT_TME
  • CAN_IT_FF0
  • CAN_IT_FOV0
  • CAN_IT_FF1
  • CAN_IT_FOV1
  • CAN_IT_WKU
  • CAN_IT_SLK
  • CAN_IT_EWG
  • CAN_IT_EPV
  • CAN_IT_BOF
  • CAN_IT_LEC
  • CAN_IT_ERR
Return values:
None.

Definition at line 1306 of file stm32f10x_can.c.

References assert_param, CAN_IT_BOF, CAN_IT_EPV, CAN_IT_ERR, CAN_IT_EWG, CAN_IT_FF0, CAN_IT_FF1, CAN_IT_FOV0, CAN_IT_FOV1, CAN_IT_LEC, CAN_IT_SLK, CAN_IT_TME, CAN_IT_WKU, CAN_MSR_ERRI, CAN_MSR_SLAKI, CAN_MSR_WKUI, CAN_RF0R_FOVR0, CAN_RF0R_FULL0, CAN_RF1R_FOVR1, CAN_RF1R_FULL1, CAN_TSR_RQCP0, CAN_TSR_RQCP1, CAN_TSR_RQCP2, CAN_TypeDef::ESR, IS_CAN_ALL_PERIPH, IS_CAN_CLEAR_IT, CAN_TypeDef::MSR, RESET, CAN_TypeDef::RF0R, CAN_TypeDef::RF1R, and CAN_TypeDef::TSR.

void CAN_DBGFreeze | ( | CAN_TypeDef * | CANx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the DBG Freeze for CAN.

Parameters:
CANx,: where x can be 1 or 2 to to select the CAN peripheral.
NewState,: new state of the CAN peripheral. This parameter can be: ENABLE or DISABLE.
Return values:
None.

Definition at line 451 of file stm32f10x_can.c.

References assert_param, DISABLE, IS_CAN_ALL_PERIPH, IS_FUNCTIONAL_STATE, CAN_TypeDef::MCR, and MCR_DBF.

void CAN_DeInit ( CAN_TypeDef * CANx )

Deinitializes the CAN peripheral registers to their default reset values.

Parameters:
CANx,: where x can be 1 or 2 to select the CAN peripheral.
Return values:
None.

Definition at line 122 of file stm32f10x_can.c.

References assert_param, CAN1, DISABLE, ENABLE, IS_CAN_ALL_PERIPH, RCC_APB1Periph_CAN1, RCC_APB1Periph_CAN2, and RCC_APB1PeriphResetCmd().

Referenced by CAN_Config(), CAN_Interrupt(), and CAN_Polling().

void CAN_FIFORelease | ( | CAN_TypeDef * | CANx,
 |  | uint8_t | FIFONumber
 | ) |  |

Releases the specified FIFO.

Parameters:
CANx,: where x can be 1 or 2 to to select the CAN peripheral.
FIFONumber,: FIFO to release, CAN_FIFO0 or CAN_FIFO1.
Return values:
None.

Definition at line 720 of file stm32f10x_can.c.

References assert_param, CAN_FIFO0, CAN_RF0R_RFOM0, CAN_RF1R_RFOM1, IS_CAN_ALL_PERIPH, IS_CAN_FIFO, CAN_TypeDef::RF0R, and CAN_TypeDef::RF1R.

void CAN_FilterInit ( CAN_FilterInitTypeDef * CAN_FilterInitStruct )

Initializes the CAN peripheral according to the specified parameters in the CAN_FilterInitStruct.

Parameters:
CAN_FilterInitStruct,: pointer to a CAN_FilterInitTypeDef structure that contains the configuration information.
Return values:
None.

Definition at line 292 of file stm32f10x_can.c.

References assert_param, CAN1, CAN_Filter_FIFO0, CAN_Filter_FIFO1, CAN_FilterInitTypeDef::CAN_FilterActivation, CAN_FilterInitTypeDef::CAN_FilterFIFOAssignment, CAN_FilterInitTypeDef::CAN_FilterIdHigh, CAN_FilterInitTypeDef::CAN_FilterIdLow, CAN_FilterInitTypeDef::CAN_FilterMaskIdHigh, CAN_FilterInitTypeDef::CAN_FilterMaskIdLow, CAN_FilterInitTypeDef::CAN_FilterMode, CAN_FilterMode_IdMask, CAN_FilterInitTypeDef::CAN_FilterNumber, CAN_FilterInitTypeDef::CAN_FilterScale, CAN_FilterScale_16bit, CAN_FilterScale_32bit, ENABLE, FMR_FINIT, IS_CAN_FILTER_FIFO, IS_CAN_FILTER_MODE, IS_CAN_FILTER_NUMBER, IS_CAN_FILTER_SCALE, and IS_FUNCTIONAL_STATE.

Referenced by CAN_Config(), CAN_Interrupt(), and CAN_Polling().

FlagStatus CAN_GetFlagStatus | ( | CAN_TypeDef * | CANx,
 |  | uint32_t | CAN_FLAG
 | ) |  |

Checks whether the specified CAN flag is set or not.

Parameters:
CANx,: where x can be 1 or 2 to to select the CAN peripheral.
CAN_FLAG,: specifies the flag to check. This parameter can be one of the following flags:

  • CAN_FLAG_EWG
  • CAN_FLAG_EPV
  • CAN_FLAG_BOF
  • CAN_FLAG_RQCP0
  • CAN_FLAG_RQCP1
  • CAN_FLAG_RQCP2
  • CAN_FLAG_FMP1
  • CAN_FLAG_FF1
  • CAN_FLAG_FOV1
  • CAN_FLAG_FMP0
  • CAN_FLAG_FF0
  • CAN_FLAG_FOV0
  • CAN_FLAG_WKU
  • CAN_FLAG_SLAK
  • CAN_FLAG_LEC
Return values:
The new state of CAN_FLAG (SET or RESET).

Definition at line 1043 of file stm32f10x_can.c.

References assert_param, CAN_FLAGS_ESR, CAN_FLAGS_MSR, CAN_FLAGS_RF0R, CAN_FLAGS_TSR, CAN_TypeDef::ESR, IS_CAN_ALL_PERIPH, IS_CAN_GET_FLAG, CAN_TypeDef::MSR, RESET, CAN_TypeDef::RF0R, CAN_TypeDef::RF1R, SET, and CAN_TypeDef::TSR.

ITStatus CAN_GetITStatus | ( | CAN_TypeDef * | CANx,
 |  | uint32_t | CAN_IT
 | ) |  |

Checks whether the specified CANx interrupt has occurred or not.

Parameters:
CANx,: where x can be 1 or 2 to to select the CAN peripheral.
CAN_IT,: specifies the CAN interrupt source to check. This parameter can be one of the following flags:

  • CAN_IT_TME
  • CAN_IT_FMP0
  • CAN_IT_FF0
  • CAN_IT_FOV0
  • CAN_IT_FMP1
  • CAN_IT_FF1
  • CAN_IT_FOV1
  • CAN_IT_WKU
  • CAN_IT_SLK
  • CAN_IT_EWG
  • CAN_IT_EPV
  • CAN_IT_BOF
  • CAN_IT_LEC
  • CAN_IT_ERR
Return values:
The current state of CAN_IT (SET or RESET).

Definition at line 1203 of file stm32f10x_can.c.

References assert_param, CAN_ESR_BOFF, CAN_ESR_EPVF, CAN_ESR_EWGF, CAN_ESR_LEC, CAN_IT_BOF, CAN_IT_EPV, CAN_IT_ERR, CAN_IT_EWG, CAN_IT_FF0, CAN_IT_FF1, CAN_IT_FMP0, CAN_IT_FMP1, CAN_IT_FOV0, CAN_IT_FOV1, CAN_IT_LEC, CAN_IT_SLK, CAN_IT_TME, CAN_IT_WKU, CAN_MSR_ERRI, CAN_MSR_SLAKI, CAN_MSR_WKUI, CAN_RF0R_FMP0, CAN_RF0R_FOVR0, CAN_RF0R_FULL0, CAN_RF1R_FMP1, CAN_RF1R_FOVR1, CAN_RF1R_FULL1, CAN_TSR_RQCP0, CAN_TSR_RQCP1, CAN_TSR_RQCP2, CheckITStatus(), CAN_TypeDef::ESR, CAN_TypeDef::IER, IS_CAN_ALL_PERIPH, IS_CAN_IT, CAN_TypeDef::MSR, RESET, CAN_TypeDef::RF0R, CAN_TypeDef::RF1R, and CAN_TypeDef::TSR.

uint8_t CAN_GetLastErrorCode ( CAN_TypeDef * CANx )

Returns the CANx's last error code (LEC).

Parameters:
CANx,: where x can be 1 or 2 to to select the CAN peripheral.
Return values:
CAN_ErrorCode,: specifies the Error code :

  • CAN_ERRORCODE_NoErr No Error
  • CAN_ERRORCODE_StuffErr Stuff Error
  • CAN_ERRORCODE_FormErr Form Error
  • CAN_ERRORCODE_ACKErr Acknowledgment Error
  • CAN_ERRORCODE_BitRecessiveErr Bit Recessive Error
  • CAN_ERRORCODE_BitDominantErr Bit Dominant Error
  • CAN_ERRORCODE_CRCErr CRC Error
  • CAN_ERRORCODE_SoftwareSetErr Software Set Error

Definition at line 922 of file stm32f10x_can.c.

References assert_param, CAN_ESR_LEC, CAN_TypeDef::ESR, and IS_CAN_ALL_PERIPH.

uint8_t CAN_GetLSBTransmitErrorCounter ( CAN_TypeDef * CANx )

Returns the LSB of the 9-bit CANx Transmit Error Counter(TEC).

Parameters:
CANx,: where x can be 1 or 2 to to select the CAN peripheral.
Return values:
LSB of the 9-bit CAN Transmit Error Counter.

Definition at line 966 of file stm32f10x_can.c.

References assert_param, CAN_ESR_TEC, CAN_TypeDef::ESR, and IS_CAN_ALL_PERIPH.

uint8_t CAN_GetReceiveErrorCounter ( CAN_TypeDef * CANx )

Returns the CANx Receive Error Counter (REC).

Note:
In case of an error during reception, this counter is incremented by 1 or by 8 depending on the error condition as defined by the CAN standard. After every successful reception, the counter is decremented by 1 or reset to 120 if its value was higher than 128. When the counter value exceeds 127, the CAN controller enters the error passive state.
Parameters:
CANx,: where x can be 1 or 2 to to select the CAN peripheral.
Return values:
CAN Receive Error Counter.

Definition at line 946 of file stm32f10x_can.c.

References assert_param, CAN_ESR_REC, CAN_TypeDef::ESR, and IS_CAN_ALL_PERIPH.

uint8_t CAN_Init | ( | CAN_TypeDef * | CANx,
 |  | CAN_InitTypeDef * | CAN_InitStruct
 | ) |  |

Initializes the CAN peripheral according to the specified parameters in the CAN_InitStruct.

Parameters:
CANx,: where x can be 1 or 2 to to select the CAN peripheral.
CAN_InitStruct,: pointer to a CAN_InitTypeDef structure that contains the configuration information for the CAN peripheral.
Return values:
Constant indicates initialization succeed which will be CAN_InitStatus_Failed or CAN_InitStatus_Success.

Definition at line 154 of file stm32f10x_can.c.

References assert_param, CAN_TypeDef::BTR, CAN_InitTypeDef::CAN_ABOM, CAN_InitTypeDef::CAN_AWUM, CAN_InitTypeDef::CAN_BS1, CAN_InitTypeDef::CAN_BS2, CAN_InitStatus_Failed, CAN_InitStatus_Success, CAN_MCR_ABOM, CAN_MCR_AWUM, CAN_MCR_INRQ, CAN_MCR_NART, CAN_MCR_RFLM, CAN_MCR_SLEEP, CAN_MCR_TTCM, CAN_MCR_TXFP, CAN_InitTypeDef::CAN_Mode, CAN_MSR_INAK, CAN_InitTypeDef::CAN_NART, CAN_InitTypeDef::CAN_Prescaler, CAN_InitTypeDef::CAN_RFLM, CAN_InitTypeDef::CAN_SJW, CAN_InitTypeDef::CAN_TTCM, CAN_InitTypeDef::CAN_TXFP, ENABLE, INAK_TIMEOUT, IS_CAN_ALL_PERIPH, IS_CAN_BS1, IS_CAN_BS2, IS_CAN_MODE, IS_CAN_PRESCALER, IS_CAN_SJW, IS_FUNCTIONAL_STATE, CAN_TypeDef::MCR, and CAN_TypeDef::MSR.

Referenced by CAN_Config(), CAN_Interrupt(), and CAN_Polling().

void CAN_ITConfig | ( | CAN_TypeDef * | CANx,
 |  | uint32_t | CAN_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified CANx interrupts.

Parameters:
CANx,: where x can be 1 or 2 to to select the CAN peripheral.
CAN_IT,: specifies the CAN interrupt sources to be enabled or disabled. This parameter can be:

  • CAN_IT_TME,
  • CAN_IT_FMP0,
  • CAN_IT_FF0,
  • CAN_IT_FOV0,
  • CAN_IT_FMP1,
  • CAN_IT_FF1,
  • CAN_IT_FOV1,
  • CAN_IT_EWG,
  • CAN_IT_EPV,
  • CAN_IT_LEC,
  • CAN_IT_ERR,
  • CAN_IT_WKU or
  • CAN_IT_SLK.
NewState,: new state of the CAN interrupts. This parameter can be: ENABLE or DISABLE.
Return values:
None.

Definition at line 1003 of file stm32f10x_can.c.

References assert_param, DISABLE, CAN_TypeDef::IER, IS_CAN_ALL_PERIPH, IS_CAN_IT, and IS_FUNCTIONAL_STATE.

Referenced by CAN_Interrupt(), and main().

uint8_t CAN_MessagePending | ( | CAN_TypeDef * | CANx,
 |  | uint8_t | FIFONumber
 | ) |  |

Returns the number of pending messages.

Parameters:
CANx,: where x can be 1 or 2 to to select the CAN peripheral.
FIFONumber,: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
Return values:
NbMessage : which is the number of pending message.

Definition at line 743 of file stm32f10x_can.c.

References assert_param, CAN_FIFO0, CAN_FIFO1, IS_CAN_ALL_PERIPH, IS_CAN_FIFO, CAN_TypeDef::RF0R, and CAN_TypeDef::RF1R.

Referenced by CAN_Polling().

uint8_t CAN_OperatingModeRequest | ( | CAN_TypeDef * | CANx,
 |  | uint8_t | CAN_OperatingMode
 | ) |  |

Select the CAN Operation mode.

Parameters:
CAN_OperatingMode : CAN Operating Mode. This parameter can be one of CAN_OperatingMode_TypeDef enumeration.
Return values:
status of the requested mode which can be

  • CAN_ModeStatus_Failed CAN failed entering the specific mode
  • CAN_ModeStatus_Success CAN Succeed entering the specific mode

Definition at line 774 of file stm32f10x_can.c.

References assert_param, CAN_MCR_INRQ, CAN_MCR_SLEEP, CAN_MODE_MASK, CAN_ModeStatus_Failed, CAN_ModeStatus_Success, CAN_MSR_INAK, CAN_MSR_SLAK, CAN_OperatingMode_Initialization, CAN_OperatingMode_Normal, CAN_OperatingMode_Sleep, INAK_TIMEOUT, IS_CAN_ALL_PERIPH, IS_CAN_OPERATING_MODE, CAN_TypeDef::MCR, CAN_TypeDef::MSR, and status.

void CAN_Receive | ( | CAN_TypeDef * | CANx,
 |  | uint8_t | FIFONumber,
 |  | CanRxMsg * | RxMessage
 | ) |  |

Receives a message.

Parameters:
CANx,: where x can be 1 or 2 to to select the CAN peripheral.
FIFONumber,: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
RxMessage,: pointer to a structure receive message which contains CAN Id, CAN DLC, CAN datas and FMI number.
Return values:
None.

Definition at line 671 of file stm32f10x_can.c.

References assert_param, CAN_FIFO0, CAN_Id_Standard, CAN_RF0R_RFOM0, CAN_RF1R_RFOM1, CanRxMsg::Data, CanRxMsg::DLC, CanRxMsg::ExtId, CanRxMsg::FMI, CanRxMsg::IDE, IS_CAN_ALL_PERIPH, IS_CAN_FIFO, CAN_FIFOMailBox_TypeDef::RDHR, CAN_FIFOMailBox_TypeDef::RDLR, CAN_FIFOMailBox_TypeDef::RDTR, CAN_TypeDef::RF0R, CAN_TypeDef::RF1R, CAN_FIFOMailBox_TypeDef::RIR, CanRxMsg::RTR, CAN_TypeDef::sFIFOMailBox, and CanRxMsg::StdId.

Referenced by CAN1_RX0_IRQHandler(), CAN2_RX0_IRQHandler(), CAN_Polling(), and USB_LP_CAN1_RX0_IRQHandler().

void CAN_SlaveStartBank ( uint8_t CAN_BankNumber )

Select the start bank filter for slave CAN.

Note:
This function applies only to STM32 Connectivity line devices.
Parameters:
CAN_BankNumber,: Select the start slave bank filter from 1..27.
Return values:
None.

Definition at line 428 of file stm32f10x_can.c.

References assert_param, CAN1, FMR_FINIT, and IS_CAN_BANKNUMBER.

uint8_t CAN_Sleep ( CAN_TypeDef * CANx )

Enters the low power mode.

Parameters:
CANx,: where x can be 1 or 2 to to select the CAN peripheral.
Return values:
status,: CAN_Sleep_Ok if sleep entered, CAN_Sleep_Failed in an other case.

Definition at line 856 of file stm32f10x_can.c.

References assert_param, CAN_MCR_INRQ, CAN_MCR_SLEEP, CAN_MSR_INAK, CAN_MSR_SLAK, CAN_Sleep_Failed, CAN_Sleep_Ok, IS_CAN_ALL_PERIPH, CAN_TypeDef::MCR, and CAN_TypeDef::MSR.

void CAN_StructInit ( CAN_InitTypeDef * CAN_InitStruct )

Fills each CAN_InitStruct member with its default value.

Parameters:
CAN_InitStruct,: pointer to a CAN_InitTypeDef structure which will be initialized.
Return values:
None.

Definition at line 384 of file stm32f10x_can.c.

References CAN_InitTypeDef::CAN_ABOM, CAN_InitTypeDef::CAN_AWUM, CAN_InitTypeDef::CAN_BS1, CAN_BS1_4tq, CAN_InitTypeDef::CAN_BS2, CAN_BS2_3tq, CAN_InitTypeDef::CAN_Mode, CAN_Mode_Normal, CAN_InitTypeDef::CAN_NART, CAN_InitTypeDef::CAN_Prescaler, CAN_InitTypeDef::CAN_RFLM, CAN_InitTypeDef::CAN_SJW, CAN_SJW_1tq, CAN_InitTypeDef::CAN_TTCM, CAN_InitTypeDef::CAN_TXFP, and DISABLE.

Referenced by CAN_Config(), CAN_Interrupt(), and CAN_Polling().

uint8_t CAN_Transmit | ( | CAN_TypeDef * | CANx,
 |  | CanTxMsg * | TxMessage
 | ) |  |

Initiates the transmission of a message.

Parameters:
CANx,: where x can be 1 or 2 to to select the CAN peripheral.
TxMessage,: pointer to a structure which contains CAN Id, CAN DLC and CAN data.
Return values:
The number of the mailbox that is used for transmission or CAN_TxStatus_NoMailBox if there is no empty mailbox.

Definition at line 515 of file stm32f10x_can.c.

References assert_param, CAN_Id_Standard, CAN_TSR_TME0, CAN_TSR_TME1, CAN_TSR_TME2, CAN_TxStatus_NoMailBox, CanTxMsg::Data, CanTxMsg::DLC, CanTxMsg::ExtId, CanTxMsg::IDE, IS_CAN_ALL_PERIPH, IS_CAN_DLC, IS_CAN_EXTID, IS_CAN_IDTYPE, IS_CAN_RTR, IS_CAN_STDID, CanTxMsg::RTR, CanTxMsg::StdId, CAN_TypeDef::sTxMailBox, CAN_TxMailBox_TypeDef::TDHR, CAN_TxMailBox_TypeDef::TDLR, CAN_TxMailBox_TypeDef::TDTR, CAN_TxMailBox_TypeDef::TIR, TMIDxR_TXRQ, and CAN_TypeDef::TSR.

Referenced by CAN_Interrupt(), CAN_Polling(), and main().

uint8_t CAN_TransmitStatus | ( | CAN_TypeDef * | CANx,
 |  | uint8_t | TransmitMailbox
 | ) |  |

Checks the transmission of a message.

Parameters:
CANx,: where x can be 1 or 2 to to select the CAN peripheral.
TransmitMailbox,: the number of the mailbox that is used for transmission.
Return values:
CAN_TxStatus_Ok if the CAN driver transmits the message, CAN_TxStatus_Failed in an other case.

Definition at line 589 of file stm32f10x_can.c.

References assert_param, CAN_TSR_RQCP0, CAN_TSR_RQCP1, CAN_TSR_RQCP2, CAN_TSR_TME0, CAN_TSR_TME1, CAN_TSR_TME2, CAN_TSR_TXOK0, CAN_TSR_TXOK1, CAN_TSR_TXOK2, CAN_TXMAILBOX_0, CAN_TXMAILBOX_1, CAN_TXMAILBOX_2, CAN_TxStatus_Failed, CAN_TxStatus_Ok, CAN_TxStatus_Pending, IS_CAN_ALL_PERIPH, IS_CAN_TRANSMITMAILBOX, and CAN_TypeDef::TSR.

Referenced by CAN_Polling().

void CAN_TTComModeCmd | ( | CAN_TypeDef * | CANx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disabes the CAN Time TriggerOperation communication mode.

Parameters:
CANx,: where x can be 1 or 2 to to select the CAN peripheral.
NewState : Mode new state , can be one of FunctionalState.
Note:
when enabled, Time stamp (TIME[15:0]) value is sent in the last two data bytes of the 8-byte message: TIME[7:0] in data byte 6 and TIME[15:8] in data byte 7
DLC must be programmed as 8 in order Time Stamp (2 bytes) to be sent over the CAN bus.
Return values:
None

Definition at line 481 of file stm32f10x_can.c.

References assert_param, CAN_MCR_TTCM, CAN_TDT0R_TGT, CAN_TDT1R_TGT, CAN_TDT2R_TGT, DISABLE, IS_CAN_ALL_PERIPH, IS_FUNCTIONAL_STATE, CAN_TypeDef::MCR, CAN_TypeDef::sTxMailBox, and CAN_TxMailBox_TypeDef::TDTR.

uint8_t CAN_WakeUp ( CAN_TypeDef * CANx )

Wakes the CAN up.

Parameters:
CANx,: where x can be 1 or 2 to to select the CAN peripheral.
Return values:
status,: CAN_WakeUp_Ok if sleep mode left, CAN_WakeUp_Failed in an other case.

Definition at line 882 of file stm32f10x_can.c.

References assert_param, CAN_MCR_SLEEP, CAN_MSR_SLAK, CAN_WakeUp_Failed, CAN_WakeUp_Ok, IS_CAN_ALL_PERIPH, CAN_TypeDef::MCR, CAN_TypeDef::MSR, and SLAK_TIMEOUT.


STM32F10x Standard Peripherals Firmware Library: CAN_Private_TypesDefinitions

CAN_Private_TypesDefinitions

CAN


STM32F10x Standard Peripherals Firmware Library: CAN_Private_Defines

Defines

CAN_Private_Defines

CAN

Defines

#define | CAN_FLAGS_ESR ((uint32_t)0x00F00000)
#define | CAN_FLAGS_MSR ((uint32_t)0x01000000)
#define | CAN_FLAGS_RF0R ((uint32_t)0x02000000)
#define | CAN_FLAGS_RF1R ((uint32_t)0x04000000)
#define | CAN_FLAGS_TSR ((uint32_t)0x08000000)
#define | CAN_MODE_MASK ((uint32_t) 0x00000003)
#define | CAN_TXMAILBOX_0 ((uint8_t)0x00)
#define | CAN_TXMAILBOX_1 ((uint8_t)0x01)
#define | CAN_TXMAILBOX_2 ((uint8_t)0x02)
#define | FMR_FINIT ((uint32_t)0x00000001)
#define | INAK_TIMEOUT ((uint32_t)0x0000FFFF)
#define | MCR_DBF ((uint32_t)0x00010000)
#define | SLAK_TIMEOUT ((uint32_t)0x0000FFFF)
#define | TMIDxR_TXRQ ((uint32_t)0x00000001)

Define Documentation

#define CAN_FLAGS_ESR ((uint32_t)0x00F00000)

Definition at line 73 of file stm32f10x_can.c.

Referenced by CAN_GetFlagStatus().

#define CAN_FLAGS_MSR ((uint32_t)0x01000000)

Definition at line 71 of file stm32f10x_can.c.

Referenced by CAN_GetFlagStatus().

#define CAN_FLAGS_RF0R ((uint32_t)0x02000000)

Definition at line 69 of file stm32f10x_can.c.

Referenced by CAN_ClearFlag(), and CAN_GetFlagStatus().

#define CAN_FLAGS_RF1R ((uint32_t)0x04000000)

Definition at line 67 of file stm32f10x_can.c.

Referenced by CAN_ClearFlag().

#define CAN_FLAGS_TSR ((uint32_t)0x08000000)

Definition at line 65 of file stm32f10x_can.c.

Referenced by CAN_ClearFlag(), and CAN_GetFlagStatus().

#define CAN_MODE_MASK ((uint32_t) 0x00000003)

Definition at line 82 of file stm32f10x_can.c.

Referenced by CAN_OperatingModeRequest().

#define CAN_TXMAILBOX_0 ((uint8_t)0x00)

Definition at line 76 of file stm32f10x_can.c.

Referenced by CAN_CancelTransmit(), and CAN_TransmitStatus().

#define CAN_TXMAILBOX_1 ((uint8_t)0x01)

Definition at line 77 of file stm32f10x_can.c.

Referenced by CAN_CancelTransmit(), and CAN_TransmitStatus().

#define CAN_TXMAILBOX_2 ((uint8_t)0x02)

Definition at line 78 of file stm32f10x_can.c.

Referenced by CAN_CancelTransmit(), and CAN_TransmitStatus().

#define FMR_FINIT ((uint32_t)0x00000001)

Definition at line 55 of file stm32f10x_can.c.

Referenced by CAN_FilterInit(), and CAN_SlaveStartBank().

#define INAK_TIMEOUT ((uint32_t)0x0000FFFF)

Definition at line 58 of file stm32f10x_can.c.

Referenced by CAN_Init(), and CAN_OperatingModeRequest().

#define MCR_DBF ((uint32_t)0x00010000)

Definition at line 49 of file stm32f10x_can.c.

Referenced by CAN_DBGFreeze().

#define SLAK_TIMEOUT ((uint32_t)0x0000FFFF)

Definition at line 60 of file stm32f10x_can.c.

Referenced by CAN_WakeUp().

#define TMIDxR_TXRQ ((uint32_t)0x00000001)

Definition at line 52 of file stm32f10x_can.c.

Referenced by CAN_Transmit().


STM32F10x Standard Peripherals Firmware Library: CAN_Private_Macros

CAN_Private_Macros

CAN


STM32F10x Standard Peripherals Firmware Library: CAN_Private_Variables

CAN_Private_Variables

CAN


STM32F10x Standard Peripherals Firmware Library: CAN_Private_FunctionPrototypes

CAN_Private_FunctionPrototypes

CAN


STM32F10x Standard Peripherals Firmware Library: CAN_Private_Functions

Functions

CAN_Private_Functions

CAN

Functions

void | CAN_CancelTransmit (CAN_TypeDef *CANx, uint8_t Mailbox)
Cancels a transmit request.
void | CAN_ClearFlag (CAN_TypeDef *CANx, uint32_t CAN_FLAG)
Clears the CAN's pending flags.
void | CAN_ClearITPendingBit (CAN_TypeDef *CANx, uint32_t CAN_IT)
Clears the CANx's interrupt pending bits.
void | CAN_DBGFreeze (CAN_TypeDef *CANx, FunctionalState NewState)
Enables or disables the DBG Freeze for CAN.
void | CAN_DeInit (CAN_TypeDef *CANx)
Deinitializes the CAN peripheral registers to their default reset values.
void | CAN_FIFORelease (CAN_TypeDef *CANx, uint8_t FIFONumber)
Releases the specified FIFO.
void | CAN_FilterInit (CAN_FilterInitTypeDef *CAN_FilterInitStruct)
Initializes the CAN peripheral according to the specified parameters in the CAN_FilterInitStruct.
FlagStatus | CAN_GetFlagStatus (CAN_TypeDef *CANx, uint32_t CAN_FLAG)
Checks whether the specified CAN flag is set or not.
ITStatus | CAN_GetITStatus (CAN_TypeDef *CANx, uint32_t CAN_IT)
Checks whether the specified CANx interrupt has occurred or not.
uint8_t | CAN_GetLastErrorCode (CAN_TypeDef *CANx)
Returns the CANx's last error code (LEC).
uint8_t | CAN_GetLSBTransmitErrorCounter (CAN_TypeDef *CANx)
Returns the LSB of the 9-bit CANx Transmit Error Counter(TEC).
uint8_t | CAN_GetReceiveErrorCounter (CAN_TypeDef *CANx)
Returns the CANx Receive Error Counter (REC).
uint8_t | CAN_Init (CAN_TypeDef *CANx, CAN_InitTypeDef *CAN_InitStruct)
Initializes the CAN peripheral according to the specified parameters in the CAN_InitStruct.
void | CAN_ITConfig (CAN_TypeDef *CANx, uint32_t CAN_IT, FunctionalState NewState)
Enables or disables the specified CANx interrupts.
uint8_t | CAN_MessagePending (CAN_TypeDef *CANx, uint8_t FIFONumber)
Returns the number of pending messages.
uint8_t | CAN_OperatingModeRequest (CAN_TypeDef *CANx, uint8_t CAN_OperatingMode)
Select the CAN Operation mode.
void | CAN_Receive (CAN_TypeDef *CANx, uint8_t FIFONumber, CanRxMsg *RxMessage)
Receives a message.
void | CAN_SlaveStartBank (uint8_t CAN_BankNumber)
Select the start bank filter for slave CAN.
uint8_t | CAN_Sleep (CAN_TypeDef *CANx)
Enters the low power mode.
void | CAN_StructInit (CAN_InitTypeDef *CAN_InitStruct)
Fills each CAN_InitStruct member with its default value.
uint8_t | CAN_Transmit (CAN_TypeDef *CANx, CanTxMsg *TxMessage)
Initiates the transmission of a message.
uint8_t | CAN_TransmitStatus (CAN_TypeDef *CANx, uint8_t TransmitMailbox)
Checks the transmission of a message.
void | CAN_TTComModeCmd (CAN_TypeDef *CANx, FunctionalState NewState)
Enables or disabes the CAN Time TriggerOperation communication mode.
uint8_t | CAN_WakeUp (CAN_TypeDef *CANx)
Wakes the CAN up.
static ITStatus | CheckITStatus (uint32_t CAN_Reg, uint32_t It_Bit)
Checks whether the CAN interrupt has occurred or not.

Function Documentation

void CAN_CancelTransmit | ( | CAN_TypeDef * | CANx,
 |  | uint8_t | Mailbox
 | ) |  |

Cancels a transmit request.

Parameters:
CANx,: where x can be 1 or 2 to to select the CAN peripheral.
Mailbox,: Mailbox number.
Return values:
None.

Definition at line 643 of file stm32f10x_can.c.

References assert_param, CAN_TSR_ABRQ0, CAN_TSR_ABRQ1, CAN_TSR_ABRQ2, CAN_TXMAILBOX_0, CAN_TXMAILBOX_1, CAN_TXMAILBOX_2, IS_CAN_ALL_PERIPH, IS_CAN_TRANSMITMAILBOX, and CAN_TypeDef::TSR.

void CAN_ClearFlag | ( | CAN_TypeDef * | CANx,
 |  | uint32_t | CAN_FLAG
 | ) |  |

Clears the CAN's pending flags.

Parameters:
CANx,: where x can be 1 or 2 to to select the CAN peripheral.
CAN_FLAG,: specifies the flag to clear. This parameter can be one of the following flags:

  • CAN_FLAG_RQCP0
  • CAN_FLAG_RQCP1
  • CAN_FLAG_RQCP2
  • CAN_FLAG_FF1
  • CAN_FLAG_FOV1
  • CAN_FLAG_FF0
  • CAN_FLAG_FOV0
  • CAN_FLAG_WKU
  • CAN_FLAG_SLAK
  • CAN_FLAG_LEC
Return values:
None.

Definition at line 1143 of file stm32f10x_can.c.

References assert_param, CAN_FLAG_LEC, CAN_FLAGS_RF0R, CAN_FLAGS_RF1R, CAN_FLAGS_TSR, CAN_TypeDef::ESR, IS_CAN_ALL_PERIPH, IS_CAN_CLEAR_FLAG, CAN_TypeDef::MSR, RESET, CAN_TypeDef::RF0R, CAN_TypeDef::RF1R, and CAN_TypeDef::TSR.

void CAN_ClearITPendingBit | ( | CAN_TypeDef * | CANx,
 |  | uint32_t | CAN_IT
 | ) |  |

Clears the CANx's interrupt pending bits.

Parameters:
CANx,: where x can be 1 or 2 to to select the CAN peripheral.
CAN_IT,: specifies the interrupt pending bit to clear.

  • CAN_IT_TME
  • CAN_IT_FF0
  • CAN_IT_FOV0
  • CAN_IT_FF1
  • CAN_IT_FOV1
  • CAN_IT_WKU
  • CAN_IT_SLK
  • CAN_IT_EWG
  • CAN_IT_EPV
  • CAN_IT_BOF
  • CAN_IT_LEC
  • CAN_IT_ERR
Return values:
None.

Definition at line 1306 of file stm32f10x_can.c.

References assert_param, CAN_IT_BOF, CAN_IT_EPV, CAN_IT_ERR, CAN_IT_EWG, CAN_IT_FF0, CAN_IT_FF1, CAN_IT_FOV0, CAN_IT_FOV1, CAN_IT_LEC, CAN_IT_SLK, CAN_IT_TME, CAN_IT_WKU, CAN_MSR_ERRI, CAN_MSR_SLAKI, CAN_MSR_WKUI, CAN_RF0R_FOVR0, CAN_RF0R_FULL0, CAN_RF1R_FOVR1, CAN_RF1R_FULL1, CAN_TSR_RQCP0, CAN_TSR_RQCP1, CAN_TSR_RQCP2, CAN_TypeDef::ESR, IS_CAN_ALL_PERIPH, IS_CAN_CLEAR_IT, CAN_TypeDef::MSR, RESET, CAN_TypeDef::RF0R, CAN_TypeDef::RF1R, and CAN_TypeDef::TSR.

void CAN_DBGFreeze | ( | CAN_TypeDef * | CANx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the DBG Freeze for CAN.

Parameters:
CANx,: where x can be 1 or 2 to to select the CAN peripheral.
NewState,: new state of the CAN peripheral. This parameter can be: ENABLE or DISABLE.
Return values:
None.

Definition at line 451 of file stm32f10x_can.c.

References assert_param, DISABLE, IS_CAN_ALL_PERIPH, IS_FUNCTIONAL_STATE, CAN_TypeDef::MCR, and MCR_DBF.

void CAN_DeInit ( CAN_TypeDef * CANx )

Deinitializes the CAN peripheral registers to their default reset values.

Parameters:
CANx,: where x can be 1 or 2 to select the CAN peripheral.
Return values:
None.

Definition at line 122 of file stm32f10x_can.c.

References assert_param, CAN1, DISABLE, ENABLE, IS_CAN_ALL_PERIPH, RCC_APB1Periph_CAN1, RCC_APB1Periph_CAN2, and RCC_APB1PeriphResetCmd().

Referenced by CAN_Config(), CAN_Interrupt(), and CAN_Polling().

void CAN_FIFORelease | ( | CAN_TypeDef * | CANx,
 |  | uint8_t | FIFONumber
 | ) |  |

Releases the specified FIFO.

Parameters:
CANx,: where x can be 1 or 2 to to select the CAN peripheral.
FIFONumber,: FIFO to release, CAN_FIFO0 or CAN_FIFO1.
Return values:
None.

Definition at line 720 of file stm32f10x_can.c.

References assert_param, CAN_FIFO0, CAN_RF0R_RFOM0, CAN_RF1R_RFOM1, IS_CAN_ALL_PERIPH, IS_CAN_FIFO, CAN_TypeDef::RF0R, and CAN_TypeDef::RF1R.

void CAN_FilterInit ( CAN_FilterInitTypeDef * CAN_FilterInitStruct )

Initializes the CAN peripheral according to the specified parameters in the CAN_FilterInitStruct.

Parameters:
CAN_FilterInitStruct,: pointer to a CAN_FilterInitTypeDef structure that contains the configuration information.
Return values:
None.

Definition at line 292 of file stm32f10x_can.c.

References assert_param, CAN1, CAN_Filter_FIFO0, CAN_Filter_FIFO1, CAN_FilterInitTypeDef::CAN_FilterActivation, CAN_FilterInitTypeDef::CAN_FilterFIFOAssignment, CAN_FilterInitTypeDef::CAN_FilterIdHigh, CAN_FilterInitTypeDef::CAN_FilterIdLow, CAN_FilterInitTypeDef::CAN_FilterMaskIdHigh, CAN_FilterInitTypeDef::CAN_FilterMaskIdLow, CAN_FilterInitTypeDef::CAN_FilterMode, CAN_FilterMode_IdMask, CAN_FilterInitTypeDef::CAN_FilterNumber, CAN_FilterInitTypeDef::CAN_FilterScale, CAN_FilterScale_16bit, CAN_FilterScale_32bit, ENABLE, FMR_FINIT, IS_CAN_FILTER_FIFO, IS_CAN_FILTER_MODE, IS_CAN_FILTER_NUMBER, IS_CAN_FILTER_SCALE, and IS_FUNCTIONAL_STATE.

Referenced by CAN_Config(), CAN_Interrupt(), and CAN_Polling().

FlagStatus CAN_GetFlagStatus | ( | CAN_TypeDef * | CANx,
 |  | uint32_t | CAN_FLAG
 | ) |  |

Checks whether the specified CAN flag is set or not.

Parameters:
CANx,: where x can be 1 or 2 to to select the CAN peripheral.
CAN_FLAG,: specifies the flag to check. This parameter can be one of the following flags:

  • CAN_FLAG_EWG
  • CAN_FLAG_EPV
  • CAN_FLAG_BOF
  • CAN_FLAG_RQCP0
  • CAN_FLAG_RQCP1
  • CAN_FLAG_RQCP2
  • CAN_FLAG_FMP1
  • CAN_FLAG_FF1
  • CAN_FLAG_FOV1
  • CAN_FLAG_FMP0
  • CAN_FLAG_FF0
  • CAN_FLAG_FOV0
  • CAN_FLAG_WKU
  • CAN_FLAG_SLAK
  • CAN_FLAG_LEC
Return values:
The new state of CAN_FLAG (SET or RESET).

Definition at line 1043 of file stm32f10x_can.c.

References assert_param, CAN_FLAGS_ESR, CAN_FLAGS_MSR, CAN_FLAGS_RF0R, CAN_FLAGS_TSR, CAN_TypeDef::ESR, IS_CAN_ALL_PERIPH, IS_CAN_GET_FLAG, CAN_TypeDef::MSR, RESET, CAN_TypeDef::RF0R, CAN_TypeDef::RF1R, SET, and CAN_TypeDef::TSR.

ITStatus CAN_GetITStatus | ( | CAN_TypeDef * | CANx,
 |  | uint32_t | CAN_IT
 | ) |  |

Checks whether the specified CANx interrupt has occurred or not.

Parameters:
CANx,: where x can be 1 or 2 to to select the CAN peripheral.
CAN_IT,: specifies the CAN interrupt source to check. This parameter can be one of the following flags:

  • CAN_IT_TME
  • CAN_IT_FMP0
  • CAN_IT_FF0
  • CAN_IT_FOV0
  • CAN_IT_FMP1
  • CAN_IT_FF1
  • CAN_IT_FOV1
  • CAN_IT_WKU
  • CAN_IT_SLK
  • CAN_IT_EWG
  • CAN_IT_EPV
  • CAN_IT_BOF
  • CAN_IT_LEC
  • CAN_IT_ERR
Return values:
The current state of CAN_IT (SET or RESET).

Definition at line 1203 of file stm32f10x_can.c.

References assert_param, CAN_ESR_BOFF, CAN_ESR_EPVF, CAN_ESR_EWGF, CAN_ESR_LEC, CAN_IT_BOF, CAN_IT_EPV, CAN_IT_ERR, CAN_IT_EWG, CAN_IT_FF0, CAN_IT_FF1, CAN_IT_FMP0, CAN_IT_FMP1, CAN_IT_FOV0, CAN_IT_FOV1, CAN_IT_LEC, CAN_IT_SLK, CAN_IT_TME, CAN_IT_WKU, CAN_MSR_ERRI, CAN_MSR_SLAKI, CAN_MSR_WKUI, CAN_RF0R_FMP0, CAN_RF0R_FOVR0, CAN_RF0R_FULL0, CAN_RF1R_FMP1, CAN_RF1R_FOVR1, CAN_RF1R_FULL1, CAN_TSR_RQCP0, CAN_TSR_RQCP1, CAN_TSR_RQCP2, CheckITStatus(), CAN_TypeDef::ESR, CAN_TypeDef::IER, IS_CAN_ALL_PERIPH, IS_CAN_IT, CAN_TypeDef::MSR, RESET, CAN_TypeDef::RF0R, CAN_TypeDef::RF1R, and CAN_TypeDef::TSR.

uint8_t CAN_GetLastErrorCode ( CAN_TypeDef * CANx )

Returns the CANx's last error code (LEC).

Parameters:
CANx,: where x can be 1 or 2 to to select the CAN peripheral.
Return values:
CAN_ErrorCode,: specifies the Error code :

  • CAN_ERRORCODE_NoErr No Error
  • CAN_ERRORCODE_StuffErr Stuff Error
  • CAN_ERRORCODE_FormErr Form Error
  • CAN_ERRORCODE_ACKErr Acknowledgment Error
  • CAN_ERRORCODE_BitRecessiveErr Bit Recessive Error
  • CAN_ERRORCODE_BitDominantErr Bit Dominant Error
  • CAN_ERRORCODE_CRCErr CRC Error
  • CAN_ERRORCODE_SoftwareSetErr Software Set Error

Definition at line 922 of file stm32f10x_can.c.

References assert_param, CAN_ESR_LEC, CAN_TypeDef::ESR, and IS_CAN_ALL_PERIPH.

uint8_t CAN_GetLSBTransmitErrorCounter ( CAN_TypeDef * CANx )

Returns the LSB of the 9-bit CANx Transmit Error Counter(TEC).

Parameters:
CANx,: where x can be 1 or 2 to to select the CAN peripheral.
Return values:
LSB of the 9-bit CAN Transmit Error Counter.

Definition at line 966 of file stm32f10x_can.c.

References assert_param, CAN_ESR_TEC, CAN_TypeDef::ESR, and IS_CAN_ALL_PERIPH.

uint8_t CAN_GetReceiveErrorCounter ( CAN_TypeDef * CANx )

Returns the CANx Receive Error Counter (REC).

Note:
In case of an error during reception, this counter is incremented by 1 or by 8 depending on the error condition as defined by the CAN standard. After every successful reception, the counter is decremented by 1 or reset to 120 if its value was higher than 128. When the counter value exceeds 127, the CAN controller enters the error passive state.
Parameters:
CANx,: where x can be 1 or 2 to to select the CAN peripheral.
Return values:
CAN Receive Error Counter.

Definition at line 946 of file stm32f10x_can.c.

References assert_param, CAN_ESR_REC, CAN_TypeDef::ESR, and IS_CAN_ALL_PERIPH.

uint8_t CAN_Init | ( | CAN_TypeDef * | CANx,
 |  | CAN_InitTypeDef * | CAN_InitStruct
 | ) |  |

Initializes the CAN peripheral according to the specified parameters in the CAN_InitStruct.

Parameters:
CANx,: where x can be 1 or 2 to to select the CAN peripheral.
CAN_InitStruct,: pointer to a CAN_InitTypeDef structure that contains the configuration information for the CAN peripheral.
Return values:
Constant indicates initialization succeed which will be CAN_InitStatus_Failed or CAN_InitStatus_Success.

Definition at line 154 of file stm32f10x_can.c.

References assert_param, CAN_TypeDef::BTR, CAN_InitTypeDef::CAN_ABOM, CAN_InitTypeDef::CAN_AWUM, CAN_InitTypeDef::CAN_BS1, CAN_InitTypeDef::CAN_BS2, CAN_InitStatus_Failed, CAN_InitStatus_Success, CAN_MCR_ABOM, CAN_MCR_AWUM, CAN_MCR_INRQ, CAN_MCR_NART, CAN_MCR_RFLM, CAN_MCR_SLEEP, CAN_MCR_TTCM, CAN_MCR_TXFP, CAN_InitTypeDef::CAN_Mode, CAN_MSR_INAK, CAN_InitTypeDef::CAN_NART, CAN_InitTypeDef::CAN_Prescaler, CAN_InitTypeDef::CAN_RFLM, CAN_InitTypeDef::CAN_SJW, CAN_InitTypeDef::CAN_TTCM, CAN_InitTypeDef::CAN_TXFP, ENABLE, INAK_TIMEOUT, IS_CAN_ALL_PERIPH, IS_CAN_BS1, IS_CAN_BS2, IS_CAN_MODE, IS_CAN_PRESCALER, IS_CAN_SJW, IS_FUNCTIONAL_STATE, CAN_TypeDef::MCR, and CAN_TypeDef::MSR.

Referenced by CAN_Config(), CAN_Interrupt(), and CAN_Polling().

void CAN_ITConfig | ( | CAN_TypeDef * | CANx,
 |  | uint32_t | CAN_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified CANx interrupts.

Parameters:
CANx,: where x can be 1 or 2 to to select the CAN peripheral.
CAN_IT,: specifies the CAN interrupt sources to be enabled or disabled. This parameter can be:

  • CAN_IT_TME,
  • CAN_IT_FMP0,
  • CAN_IT_FF0,
  • CAN_IT_FOV0,
  • CAN_IT_FMP1,
  • CAN_IT_FF1,
  • CAN_IT_FOV1,
  • CAN_IT_EWG,
  • CAN_IT_EPV,
  • CAN_IT_LEC,
  • CAN_IT_ERR,
  • CAN_IT_WKU or
  • CAN_IT_SLK.
NewState,: new state of the CAN interrupts. This parameter can be: ENABLE or DISABLE.
Return values:
None.

Definition at line 1003 of file stm32f10x_can.c.

References assert_param, DISABLE, CAN_TypeDef::IER, IS_CAN_ALL_PERIPH, IS_CAN_IT, and IS_FUNCTIONAL_STATE.

Referenced by CAN_Interrupt(), and main().

uint8_t CAN_MessagePending | ( | CAN_TypeDef * | CANx,
 |  | uint8_t | FIFONumber
 | ) |  |

Returns the number of pending messages.

Parameters:
CANx,: where x can be 1 or 2 to to select the CAN peripheral.
FIFONumber,: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
Return values:
NbMessage : which is the number of pending message.

Definition at line 743 of file stm32f10x_can.c.

References assert_param, CAN_FIFO0, CAN_FIFO1, IS_CAN_ALL_PERIPH, IS_CAN_FIFO, CAN_TypeDef::RF0R, and CAN_TypeDef::RF1R.

Referenced by CAN_Polling().

uint8_t CAN_OperatingModeRequest | ( | CAN_TypeDef * | CANx,
 |  | uint8_t | CAN_OperatingMode
 | ) |  |

Select the CAN Operation mode.

Parameters:
CAN_OperatingMode : CAN Operating Mode. This parameter can be one of CAN_OperatingMode_TypeDef enumeration.
Return values:
status of the requested mode which can be

  • CAN_ModeStatus_Failed CAN failed entering the specific mode
  • CAN_ModeStatus_Success CAN Succeed entering the specific mode

Definition at line 774 of file stm32f10x_can.c.

References assert_param, CAN_MCR_INRQ, CAN_MCR_SLEEP, CAN_MODE_MASK, CAN_ModeStatus_Failed, CAN_ModeStatus_Success, CAN_MSR_INAK, CAN_MSR_SLAK, CAN_OperatingMode_Initialization, CAN_OperatingMode_Normal, CAN_OperatingMode_Sleep, INAK_TIMEOUT, IS_CAN_ALL_PERIPH, IS_CAN_OPERATING_MODE, CAN_TypeDef::MCR, CAN_TypeDef::MSR, and status.

void CAN_Receive | ( | CAN_TypeDef * | CANx,
 |  | uint8_t | FIFONumber,
 |  | CanRxMsg * | RxMessage
 | ) |  |

Receives a message.

Parameters:
CANx,: where x can be 1 or 2 to to select the CAN peripheral.
FIFONumber,: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
RxMessage,: pointer to a structure receive message which contains CAN Id, CAN DLC, CAN datas and FMI number.
Return values:
None.

Definition at line 671 of file stm32f10x_can.c.

References assert_param, CAN_FIFO0, CAN_Id_Standard, CAN_RF0R_RFOM0, CAN_RF1R_RFOM1, CanRxMsg::Data, CanRxMsg::DLC, CanRxMsg::ExtId, CanRxMsg::FMI, CanRxMsg::IDE, IS_CAN_ALL_PERIPH, IS_CAN_FIFO, CAN_FIFOMailBox_TypeDef::RDHR, CAN_FIFOMailBox_TypeDef::RDLR, CAN_FIFOMailBox_TypeDef::RDTR, CAN_TypeDef::RF0R, CAN_TypeDef::RF1R, CAN_FIFOMailBox_TypeDef::RIR, CanRxMsg::RTR, CAN_TypeDef::sFIFOMailBox, and CanRxMsg::StdId.

Referenced by CAN1_RX0_IRQHandler(), CAN2_RX0_IRQHandler(), CAN_Polling(), and USB_LP_CAN1_RX0_IRQHandler().

void CAN_SlaveStartBank ( uint8_t CAN_BankNumber )

Select the start bank filter for slave CAN.

Note:
This function applies only to STM32 Connectivity line devices.
Parameters:
CAN_BankNumber,: Select the start slave bank filter from 1..27.
Return values:
None.

Definition at line 428 of file stm32f10x_can.c.

References assert_param, CAN1, FMR_FINIT, and IS_CAN_BANKNUMBER.

uint8_t CAN_Sleep ( CAN_TypeDef * CANx )

Enters the low power mode.

Parameters:
CANx,: where x can be 1 or 2 to to select the CAN peripheral.
Return values:
status,: CAN_Sleep_Ok if sleep entered, CAN_Sleep_Failed in an other case.

Definition at line 856 of file stm32f10x_can.c.

References assert_param, CAN_MCR_INRQ, CAN_MCR_SLEEP, CAN_MSR_INAK, CAN_MSR_SLAK, CAN_Sleep_Failed, CAN_Sleep_Ok, IS_CAN_ALL_PERIPH, CAN_TypeDef::MCR, and CAN_TypeDef::MSR.

void CAN_StructInit ( CAN_InitTypeDef * CAN_InitStruct )

Fills each CAN_InitStruct member with its default value.

Parameters:
CAN_InitStruct,: pointer to a CAN_InitTypeDef structure which will be initialized.
Return values:
None.

Definition at line 384 of file stm32f10x_can.c.

References CAN_InitTypeDef::CAN_ABOM, CAN_InitTypeDef::CAN_AWUM, CAN_InitTypeDef::CAN_BS1, CAN_BS1_4tq, CAN_InitTypeDef::CAN_BS2, CAN_BS2_3tq, CAN_InitTypeDef::CAN_Mode, CAN_Mode_Normal, CAN_InitTypeDef::CAN_NART, CAN_InitTypeDef::CAN_Prescaler, CAN_InitTypeDef::CAN_RFLM, CAN_InitTypeDef::CAN_SJW, CAN_SJW_1tq, CAN_InitTypeDef::CAN_TTCM, CAN_InitTypeDef::CAN_TXFP, and DISABLE.

Referenced by CAN_Config(), CAN_Interrupt(), and CAN_Polling().

uint8_t CAN_Transmit | ( | CAN_TypeDef * | CANx,
 |  | CanTxMsg * | TxMessage
 | ) |  |

Initiates the transmission of a message.

Parameters:
CANx,: where x can be 1 or 2 to to select the CAN peripheral.
TxMessage,: pointer to a structure which contains CAN Id, CAN DLC and CAN data.
Return values:
The number of the mailbox that is used for transmission or CAN_TxStatus_NoMailBox if there is no empty mailbox.

Definition at line 515 of file stm32f10x_can.c.

References assert_param, CAN_Id_Standard, CAN_TSR_TME0, CAN_TSR_TME1, CAN_TSR_TME2, CAN_TxStatus_NoMailBox, CanTxMsg::Data, CanTxMsg::DLC, CanTxMsg::ExtId, CanTxMsg::IDE, IS_CAN_ALL_PERIPH, IS_CAN_DLC, IS_CAN_EXTID, IS_CAN_IDTYPE, IS_CAN_RTR, IS_CAN_STDID, CanTxMsg::RTR, CanTxMsg::StdId, CAN_TypeDef::sTxMailBox, CAN_TxMailBox_TypeDef::TDHR, CAN_TxMailBox_TypeDef::TDLR, CAN_TxMailBox_TypeDef::TDTR, CAN_TxMailBox_TypeDef::TIR, TMIDxR_TXRQ, and CAN_TypeDef::TSR.

Referenced by CAN_Interrupt(), CAN_Polling(), and main().

uint8_t CAN_TransmitStatus | ( | CAN_TypeDef * | CANx,
 |  | uint8_t | TransmitMailbox
 | ) |  |

Checks the transmission of a message.

Parameters:
CANx,: where x can be 1 or 2 to to select the CAN peripheral.
TransmitMailbox,: the number of the mailbox that is used for transmission.
Return values:
CAN_TxStatus_Ok if the CAN driver transmits the message, CAN_TxStatus_Failed in an other case.

Definition at line 589 of file stm32f10x_can.c.

References assert_param, CAN_TSR_RQCP0, CAN_TSR_RQCP1, CAN_TSR_RQCP2, CAN_TSR_TME0, CAN_TSR_TME1, CAN_TSR_TME2, CAN_TSR_TXOK0, CAN_TSR_TXOK1, CAN_TSR_TXOK2, CAN_TXMAILBOX_0, CAN_TXMAILBOX_1, CAN_TXMAILBOX_2, CAN_TxStatus_Failed, CAN_TxStatus_Ok, CAN_TxStatus_Pending, IS_CAN_ALL_PERIPH, IS_CAN_TRANSMITMAILBOX, and CAN_TypeDef::TSR.

Referenced by CAN_Polling().

void CAN_TTComModeCmd | ( | CAN_TypeDef * | CANx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disabes the CAN Time TriggerOperation communication mode.

Parameters:
CANx,: where x can be 1 or 2 to to select the CAN peripheral.
NewState : Mode new state , can be one of FunctionalState.
Note:
when enabled, Time stamp (TIME[15:0]) value is sent in the last two data bytes of the 8-byte message: TIME[7:0] in data byte 6 and TIME[15:8] in data byte 7
DLC must be programmed as 8 in order Time Stamp (2 bytes) to be sent over the CAN bus.
Return values:
None

Definition at line 481 of file stm32f10x_can.c.

References assert_param, CAN_MCR_TTCM, CAN_TDT0R_TGT, CAN_TDT1R_TGT, CAN_TDT2R_TGT, DISABLE, IS_CAN_ALL_PERIPH, IS_FUNCTIONAL_STATE, CAN_TypeDef::MCR, CAN_TypeDef::sTxMailBox, and CAN_TxMailBox_TypeDef::TDTR.

uint8_t CAN_WakeUp ( CAN_TypeDef * CANx )

Wakes the CAN up.

Parameters:
CANx,: where x can be 1 or 2 to to select the CAN peripheral.
Return values:
status,: CAN_WakeUp_Ok if sleep mode left, CAN_WakeUp_Failed in an other case.

Definition at line 882 of file stm32f10x_can.c.

References assert_param, CAN_MCR_SLEEP, CAN_MSR_SLAK, CAN_WakeUp_Failed, CAN_WakeUp_Ok, IS_CAN_ALL_PERIPH, CAN_TypeDef::MCR, CAN_TypeDef::MSR, and SLAK_TIMEOUT.

static ITStatus CheckITStatus | ( | uint32_t | CAN_Reg,
 |  | uint32_t | It_Bit
 | ) |  | [static]

Checks whether the CAN interrupt has occurred or not.

Parameters:
CAN_Reg,: specifies the CAN interrupt register to check.
It_Bit,: specifies the interrupt source bit to check.
Return values:
The new state of the CAN Interrupt (SET or RESET).

Definition at line 1385 of file stm32f10x_can.c.

References RESET, and SET.

Referenced by CAN_GetITStatus().


STM32F10x Standard Peripherals Firmware Library: CEC_InitTypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

CEC_InitTypeDef Struct Reference
CEC_Exported_Types

CEC Init structure definition. More...

#include <stm32f10x_cec.h>

Data Fields

uint16_t | CEC_BitPeriodMode
uint16_t | CEC_BitTimingMode

Detailed Description

CEC Init structure definition.

Definition at line 50 of file stm32f10x_cec.h.

Field Documentation

uint16_t CEC_InitTypeDef::CEC_BitPeriodMode

Configures the CEC Bit Period Error Mode. This parameter can be a value of CEC_BitPeriod_Mode

Definition at line 54 of file stm32f10x_cec.h.

Referenced by CEC_Init(), HDMI_CEC_Init(), and main().

uint16_t CEC_InitTypeDef::CEC_BitTimingMode

Configures the CEC Bit Timing Error Mode. This parameter can be a value of CEC_BitTiming_Mode

Definition at line 52 of file stm32f10x_cec.h.

Referenced by CEC_Init(), HDMI_CEC_Init(), and main().

The documentation for this struct was generated from the following file:
  • stm32f10x_cec.h


STM32F10x Standard Peripherals Firmware Library: CEC_BitTiming_Mode

Defines

CEC_BitTiming_Mode

CEC_Exported_Constants

Defines

#define | CEC_BitTimingErrFreeMode CEC_CFGR_BTEM
#define | CEC_BitTimingStdMode ((uint16_t)0x00)
#define | IS_CEC_BIT_TIMING_ERROR_MODE(MODE)

Define Documentation

#define CEC_BitTimingErrFreeMode CEC_CFGR_BTEM

Bit timing error Free Mode

Definition at line 70 of file stm32f10x_cec.h.

#define CEC_BitTimingStdMode ((uint16_t)0x00)

Bit timing error Standard Mode

Definition at line 69 of file stm32f10x_cec.h.

Referenced by HDMI_CEC_Init(), and main().

#define IS_CEC_BIT_TIMING_ERROR_MODE ( MODE )
Value:
(((MODE) == CEC_BitTimingStdMode) || \
                                            ((MODE) == CEC_BitTimingErrFreeMode))

Definition at line 72 of file stm32f10x_cec.h.

Referenced by CEC_Init().


STM32F10x Standard Peripherals Firmware Library: CEC_BitPeriod_Mode

Defines

CEC_BitPeriod_Mode

CEC_Exported_Constants

Defines

#define | CEC_BitPeriodFlexibleMode CEC_CFGR_BPEM
#define | CEC_BitPeriodStdMode ((uint16_t)0x00)
#define | IS_CEC_BIT_PERIOD_ERROR_MODE(MODE)

Define Documentation

#define CEC_BitPeriodFlexibleMode CEC_CFGR_BPEM

Bit period error Flexible Mode

Definition at line 82 of file stm32f10x_cec.h.

#define CEC_BitPeriodStdMode ((uint16_t)0x00)

Bit period error Standard Mode

Definition at line 81 of file stm32f10x_cec.h.

Referenced by HDMI_CEC_Init(), and main().

#define IS_CEC_BIT_PERIOD_ERROR_MODE ( MODE )
Value:
(((MODE) == CEC_BitPeriodStdMode) || \
                                            ((MODE) == CEC_BitPeriodFlexibleMode))

Definition at line 84 of file stm32f10x_cec.h.

Referenced by CEC_Init().


STM32F10x Standard Peripherals Firmware Library: CEC_interrupts_definition

Defines

CEC_interrupts_definition

CEC_Exported_Constants

Defines

#define | CEC_IT_RBTF CEC_CSR_RBTF
#define | CEC_IT_RERR CEC_CSR_RERR
#define | CEC_IT_TBTRF CEC_CSR_TBTRF
#define | CEC_IT_TERR CEC_CSR_TERR
#define | IS_CEC_GET_IT(IT)

Define Documentation

#define CEC_IT_RBTF CEC_CSR_RBTF

Definition at line 97 of file stm32f10x_cec.h.

#define CEC_IT_RERR CEC_CSR_RERR

Definition at line 96 of file stm32f10x_cec.h.

#define CEC_IT_TBTRF CEC_CSR_TBTRF

Definition at line 95 of file stm32f10x_cec.h.

#define CEC_IT_TERR CEC_CSR_TERR

Definition at line 94 of file stm32f10x_cec.h.

#define IS_CEC_GET_IT ( IT )
Value:
(((IT) == CEC_IT_TERR) || ((IT) == CEC_IT_TBTRF) || \
                           ((IT) == CEC_IT_RERR) || ((IT) == CEC_IT_RBTF))

Definition at line 98 of file stm32f10x_cec.h.

Referenced by CEC_ClearITPendingBit(), and CEC_GetITStatus().


STM32F10x Standard Peripherals Firmware Library: CEC_Own_Address

Defines

CEC_Own_Address

CEC_Exported_Constants

Defines

#define IS_CEC_ADDRESS(ADDRESS) ((ADDRESS) < 0x10)

Define Documentation

#define IS_CEC_ADDRESS ( ADDRESS ) ((ADDRESS) < 0x10)

Definition at line 108 of file stm32f10x_cec.h.

Referenced by CEC_OwnAddressConfig().


STM32F10x Standard Peripherals Firmware Library: CEC_Prescaler

Defines

CEC_Prescaler

CEC_Exported_Constants

Defines

#define IS_CEC_PRESCALER(PRESCALER) ((PRESCALER) <= 0x3FFF)

Define Documentation

#define IS_CEC_PRESCALER ( PRESCALER ) ((PRESCALER) <= 0x3FFF)

Definition at line 116 of file stm32f10x_cec.h.

Referenced by CEC_SetPrescaler().


STM32F10x Standard Peripherals Firmware Library: CEC_flags_definition

Defines

CEC_flags_definition

CEC_Exported_Constants

Defines

#define | CEC_FLAG_ACKE ((uint32_t)0x10100000)
#define | CEC_FLAG_BPE ((uint32_t)0x10020000)
#define | CEC_FLAG_BTE ((uint32_t)0x10010000)
ESR register flags.
#define | CEC_FLAG_LINE ((uint32_t)0x10200000)
#define | CEC_FLAG_RBTF ((uint32_t)0x00000080)
#define | CEC_FLAG_RBTFE ((uint32_t)0x10040000)
#define | CEC_FLAG_REOM ((uint32_t)0x00000020)
#define | CEC_FLAG_RERR ((uint32_t)0x00000040)
#define | CEC_FLAG_RSOM ((uint32_t)0x00000010)
#define | CEC_FLAG_SBE ((uint32_t)0x10080000)
#define | CEC_FLAG_TBTFE ((uint32_t)0x10400000)
#define | CEC_FLAG_TBTRF ((uint32_t)0x00000008)
#define | CEC_FLAG_TEOM ((uint32_t)0x00000002)
CSR register flags.
#define | CEC_FLAG_TERR ((uint32_t)0x00000004)
#define | IS_CEC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFF03) == 0x00) && ((FLAG) != 0x00))
#define | IS_CEC_GET_FLAG(FLAG)

Define Documentation

#define CEC_FLAG_ACKE ((uint32_t)0x10100000)

Definition at line 133 of file stm32f10x_cec.h.

Referenced by HDMI_CEC_GetErrorStatus().

#define CEC_FLAG_BPE ((uint32_t)0x10020000)

Definition at line 130 of file stm32f10x_cec.h.

Referenced by HDMI_CEC_GetErrorStatus().

#define CEC_FLAG_BTE ((uint32_t)0x10010000)

ESR register flags.

Definition at line 129 of file stm32f10x_cec.h.

Referenced by HDMI_CEC_GetErrorStatus().

#define CEC_FLAG_LINE ((uint32_t)0x10200000)

Definition at line 134 of file stm32f10x_cec.h.

Referenced by HDMI_CEC_GetErrorStatus().

#define CEC_FLAG_RBTF ((uint32_t)0x00000080)

Definition at line 146 of file stm32f10x_cec.h.

Referenced by CEC_IRQHandler(), and HDMI_CEC_ProcessIRQSrc().

#define CEC_FLAG_RBTFE ((uint32_t)0x10040000)

Definition at line 131 of file stm32f10x_cec.h.

Referenced by HDMI_CEC_GetErrorStatus().

#define CEC_FLAG_REOM ((uint32_t)0x00000020)

Definition at line 144 of file stm32f10x_cec.h.

Referenced by CEC_IRQHandler(), and HDMI_CEC_ProcessIRQSrc().

#define CEC_FLAG_RERR ((uint32_t)0x00000040)

Definition at line 145 of file stm32f10x_cec.h.

Referenced by CEC_IRQHandler(), HDMI_CEC_GetErrorStatus(), and HDMI_CEC_ProcessIRQSrc().

#define CEC_FLAG_RSOM ((uint32_t)0x00000010)

Definition at line 143 of file stm32f10x_cec.h.

Referenced by CEC_IRQHandler(), and HDMI_CEC_ProcessIRQSrc().

#define CEC_FLAG_SBE ((uint32_t)0x10080000)

Definition at line 132 of file stm32f10x_cec.h.

Referenced by HDMI_CEC_GetErrorStatus().

#define CEC_FLAG_TBTFE ((uint32_t)0x10400000)

Definition at line 135 of file stm32f10x_cec.h.

Referenced by HDMI_CEC_GetErrorStatus().

#define CEC_FLAG_TBTRF ((uint32_t)0x00000008)

Definition at line 142 of file stm32f10x_cec.h.

Referenced by CEC_IRQHandler(), HDMI_CEC_CheckConnectedDevices(), HDMI_CEC_ProcessIRQSrc(), HDMI_CEC_TransmitMessage(), and LogicalAddressAllocation().

#define CEC_FLAG_TEOM ((uint32_t)0x00000002)

CSR register flags.

Definition at line 140 of file stm32f10x_cec.h.

Referenced by CEC_IRQHandler(), and HDMI_CEC_ProcessIRQSrc().

#define CEC_FLAG_TERR ((uint32_t)0x00000004)

Definition at line 141 of file stm32f10x_cec.h.

Referenced by CEC_IRQHandler(), HDMI_CEC_CheckConnectedDevices(), HDMI_CEC_GetErrorStatus(), HDMI_CEC_ProcessIRQSrc(), HDMI_CEC_TransmitMessage(), and LogicalAddressAllocation().

#define IS_CEC_CLEAR_FLAG ( FLAG ) ((((FLAG) & (uint32_t)0xFFFFFF03) == 0x00) && ((FLAG) != 0x00))

Definition at line 148 of file stm32f10x_cec.h.

Referenced by CEC_ClearFlag().

#define IS_CEC_GET_FLAG ( FLAG )
Value:
(((FLAG) == CEC_FLAG_BTE) || ((FLAG) == CEC_FLAG_BPE) || \
                               ((FLAG) == CEC_FLAG_RBTFE) || ((FLAG)== CEC_FLAG_SBE) || \
                               ((FLAG) == CEC_FLAG_ACKE) || ((FLAG) == CEC_FLAG_LINE) || \
                               ((FLAG) == CEC_FLAG_TBTFE) || ((FLAG) == CEC_FLAG_TEOM) || \
                               ((FLAG) == CEC_FLAG_TERR) || ((FLAG) == CEC_FLAG_TBTRF) || \
                               ((FLAG) == CEC_FLAG_RSOM) || ((FLAG) == CEC_FLAG_REOM) || \
                               ((FLAG) == CEC_FLAG_RERR) || ((FLAG) == CEC_FLAG_RBTF))

Definition at line 150 of file stm32f10x_cec.h.

Referenced by CEC_GetFlagStatus().


STM32F10x Standard Peripherals Firmware Library: CEC_Exported_Macros

CEC_Exported_Macros

CEC


STM32F10x Standard Peripherals Firmware Library: CEC_Exported_Functions

Functions

CEC_Exported_Functions

CEC

Functions

void | CEC_ClearFlag (uint32_t CEC_FLAG)
Clears the CEC's pending flags.
void | CEC_ClearITPendingBit (uint16_t CEC_IT)
Clears the CEC's interrupt pending bits.
void | CEC_Cmd (FunctionalState NewState)
Enables or disables the specified CEC peripheral.
void | CEC_DeInit (void)
Deinitializes the CEC peripheral registers to their default reset values.
void | CEC_EndOfMessageCmd (FunctionalState NewState)
Transmits message with or without an EOM bit.
FlagStatus | CEC_GetFlagStatus (uint32_t CEC_FLAG)
Gets the CEC flag status.
ITStatus | CEC_GetITStatus (uint8_t CEC_IT)
Checks whether the specified CEC interrupt has occurred or not.
void | CEC_Init (CEC_InitTypeDef *CEC_InitStruct)
Initializes the CEC peripheral according to the specified parameters in the CEC_InitStruct.
void | CEC_ITConfig (FunctionalState NewState)
Enables or disables the CEC interrupt.
void | CEC_OwnAddressConfig (uint8_t CEC_OwnAddress)
Defines the Own Address of the CEC device.
uint8_t | CEC_ReceiveDataByte (void)
Returns the most recent received data by the CEC peripheral.
void | CEC_SendDataByte (uint8_t Data)
Transmits single data through the CEC peripheral.
void | CEC_SetPrescaler (uint16_t CEC_Prescaler)
Sets the CEC prescaler value.
void | CEC_StartOfMessage (void)
Starts a new message.

Function Documentation

void CEC_ClearFlag ( uint32_t CEC_FLAG )

Clears the CEC's pending flags.

Parameters:
CEC_FLAG,: specifies the flag to clear. This parameter can be any combination of the following values:

  • CEC_FLAG_TERR: Tx Error
  • CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished
  • CEC_FLAG_RSOM: Rx Start Of Message
  • CEC_FLAG_REOM: Rx End Of Message
  • CEC_FLAG_RERR: Rx Error
  • CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished
Return values:
None

Definition at line 349 of file stm32f10x_cec.c.

References assert_param, CEC, and IS_CEC_CLEAR_FLAG.

Referenced by CEC_IRQHandler(), HDMI_CEC_CheckConnectedDevices(), HDMI_CEC_GetErrorStatus(), HDMI_CEC_ProcessIRQSrc(), HDMI_CEC_TransmitMessage(), and LogicalAddressAllocation().

void CEC_ClearITPendingBit ( uint16_t CEC_IT )

Clears the CEC's interrupt pending bits.

Parameters:
CEC_IT,: specifies the CEC interrupt pending bit to clear. This parameter can be any combination of the following values:

  • CEC_IT_TERR: Tx Error
  • CEC_IT_TBTF: Tx Block Transfer Finished
  • CEC_IT_RERR: Rx Error
  • CEC_IT_RBTF: Rx Block Transfer Finished
Return values:
None

Definition at line 408 of file stm32f10x_cec.c.

References assert_param, CEC, and IS_CEC_GET_IT.

void CEC_Cmd ( FunctionalState NewState )

Enables or disables the specified CEC peripheral.

Parameters:
NewState,: new state of the CEC peripheral. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 164 of file stm32f10x_cec.c.

References assert_param, CEC, CEC_CFGR_PE, CFGR_PE_BB, DISABLE, IS_FUNCTIONAL_STATE, and RESET.

Referenced by HDMI_CEC_Init(), and main().

void CEC_DeInit ( void )

Deinitializes the CEC peripheral registers to their default reset values.

Parameters:
None
Return values:
None

Definition at line 118 of file stm32f10x_cec.c.

References DISABLE, ENABLE, RCC_APB1Periph_CEC, and RCC_APB1PeriphResetCmd().

Referenced by HDMI_CEC_Init().

void CEC_EndOfMessageCmd ( FunctionalState NewState )

Transmits message with or without an EOM bit.

Parameters:
NewState,: new state of the CEC Tx End Of Message. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 262 of file stm32f10x_cec.c.

References assert_param, CSR_TEOM_BB, and IS_FUNCTIONAL_STATE.

Referenced by CEC_IRQHandler(), HDMI_CEC_CheckConnectedDevices(), HDMI_CEC_ProcessIRQSrc(), and LogicalAddressAllocation().

FlagStatus CEC_GetFlagStatus ( uint32_t CEC_FLAG )

Gets the CEC flag status.

Parameters:
CEC_FLAG,: specifies the CEC flag to check. This parameter can be one of the following values:

  • CEC_FLAG_BTE: Bit Timing Error
  • CEC_FLAG_BPE: Bit Period Error
  • CEC_FLAG_RBTFE: Rx Block Transfer Finished Error
  • CEC_FLAG_SBE: Start Bit Error
  • CEC_FLAG_ACKE: Block Acknowledge Error
  • CEC_FLAG_LINE: Line Error
  • CEC_FLAG_TBTFE: Tx Block Transfer Finished Error
  • CEC_FLAG_TEOM: Tx End Of Message
  • CEC_FLAG_TERR: Tx Error
  • CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished
  • CEC_FLAG_RSOM: Rx Start Of Message
  • CEC_FLAG_REOM: Rx End Of Message
  • CEC_FLAG_RERR: Rx Error
  • CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished
Return values:
The new state of CEC_FLAG (SET or RESET)

Definition at line 291 of file stm32f10x_cec.c.

References assert_param, CEC_BASE, FLAG_Mask, IS_CEC_GET_FLAG, RESET, and SET.

Referenced by CEC_IRQHandler(), HDMI_CEC_CheckConnectedDevices(), HDMI_CEC_GetErrorStatus(), HDMI_CEC_ProcessIRQSrc(), and LogicalAddressAllocation().

ITStatus CEC_GetITStatus ( uint8_t CEC_IT )

Checks whether the specified CEC interrupt has occurred or not.

Parameters:
CEC_IT,: specifies the CEC interrupt source to check. This parameter can be one of the following values:

  • CEC_IT_TERR: Tx Error
  • CEC_IT_TBTF: Tx Block Transfer Finished
  • CEC_IT_RERR: Rx Error
  • CEC_IT_RBTF: Rx Block Transfer Finished
Return values:
The new state of CEC_IT (SET or RESET).

Definition at line 372 of file stm32f10x_cec.c.

References assert_param, CEC, CEC_CFGR_IE, IS_CEC_GET_IT, RESET, and SET.

void CEC_Init ( CEC_InitTypeDef * CEC_InitStruct )

Initializes the CEC peripheral according to the specified parameters in the CEC_InitStruct.

Parameters:
CEC_InitStruct,: pointer to an CEC_InitTypeDef structure that contains the configuration information for the specified CEC peripheral.
Return values:
None

Definition at line 135 of file stm32f10x_cec.c.

References assert_param, CEC, CEC_InitTypeDef::CEC_BitPeriodMode, CEC_InitTypeDef::CEC_BitTimingMode, CFGR_CLEAR_Mask, IS_CEC_BIT_PERIOD_ERROR_MODE, and IS_CEC_BIT_TIMING_ERROR_MODE.

Referenced by HDMI_CEC_Init(), and main().

void CEC_ITConfig ( FunctionalState NewState )

Enables or disables the CEC interrupt.

Parameters:
NewState,: new state of the CEC interrupt. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 186 of file stm32f10x_cec.c.

References assert_param, CFGR_IE_BB, and IS_FUNCTIONAL_STATE.

Referenced by HDMI_CEC_Init(), and main().

void CEC_OwnAddressConfig ( uint8_t CEC_OwnAddress )

Defines the Own Address of the CEC device.

Parameters:
CEC_OwnAddress,: The CEC own address
Return values:
None

Definition at line 199 of file stm32f10x_cec.c.

References assert_param, CEC, and IS_CEC_ADDRESS.

Referenced by HDMI_CEC_CheckConnectedDevices(), HDMI_CEC_Init(), LogicalAddressAllocation(), and main().

uint8_t CEC_ReceiveDataByte ( void )

Returns the most recent received data by the CEC peripheral.

Parameters:
None
Return values:
The received data.

Definition at line 239 of file stm32f10x_cec.c.

References CEC.

Referenced by CEC_IRQHandler(), and HDMI_CEC_ProcessIRQSrc().

void CEC_SendDataByte ( uint8_t Data )

Transmits single data through the CEC peripheral.

Parameters:
Data,: the data to transmit.
Return values:
None

Definition at line 227 of file stm32f10x_cec.c.

References CEC, and Data.

Referenced by CEC_IRQHandler(), EXTI9_5_IRQHandler(), HDMI_CEC_CheckConnectedDevices(), HDMI_CEC_ProcessIRQSrc(), HDMI_CEC_TransmitMessage(), and LogicalAddressAllocation().

void CEC_SetPrescaler ( uint16_t CEC_Prescaler )

Sets the CEC prescaler value.

Parameters:
CEC_Prescaler,: CEC prescaler new value
Return values:
None

Definition at line 213 of file stm32f10x_cec.c.

References assert_param, CEC, and IS_CEC_PRESCALER.

Referenced by HDMI_CEC_Init(), and main().

void CEC_StartOfMessage ( void )

Starts a new message.

Parameters:
None
Return values:
None

Definition at line 250 of file stm32f10x_cec.c.

References CSR_TSOM_BB.

Referenced by EXTI9_5_IRQHandler(), HDMI_CEC_CheckConnectedDevices(), HDMI_CEC_TransmitMessage(), and LogicalAddressAllocation().


STM32F10x Standard Peripherals Firmware Library: CEC_Private_TypesDefinitions

CEC_Private_TypesDefinitions

CEC


STM32F10x Standard Peripherals Firmware Library: CEC_Private_Defines

Defines

CEC_Private_Defines

CEC

Defines

#define | CEC_OFFSET (CEC_BASE - PERIPH_BASE)
#define | CFGR_CLEAR_Mask (uint8_t)(0xF3)
#define | CFGR_IE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (IE_BitNumber * 4))
#define | CFGR_OFFSET (CEC_OFFSET + 0x00)
#define | CFGR_PE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (PE_BitNumber * 4))
#define | CSR_OFFSET (CEC_OFFSET + 0x10)
#define | CSR_TEOM_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEOM_BitNumber * 4))
#define | CSR_TSOM_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TSOM_BitNumber * 4))
#define | FLAG_Mask ((uint32_t)0x00FFFFFF)
#define | IE_BitNumber 0x01
#define | PE_BitNumber 0x00
#define | TEOM_BitNumber 0x01
#define | TSOM_BitNumber 0x00

Define Documentation

#define CEC_OFFSET (CEC_BASE - PERIPH_BASE)

Definition at line 49 of file stm32f10x_cec.c.

#define CFGR_CLEAR_Mask (uint8_t)(0xF3)

Definition at line 73 of file stm32f10x_cec.c.

Referenced by CEC_Init().

#define CFGR_IE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (IE_BitNumber * 4))

Definition at line 60 of file stm32f10x_cec.c.

Referenced by CEC_ITConfig().

#define CFGR_OFFSET (CEC_OFFSET + 0x00)

Definition at line 54 of file stm32f10x_cec.c.

#define CFGR_PE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (PE_BitNumber * 4))

Definition at line 56 of file stm32f10x_cec.c.

Referenced by CEC_Cmd().

#define CSR_OFFSET (CEC_OFFSET + 0x10)

Definition at line 65 of file stm32f10x_cec.c.

#define CSR_TEOM_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEOM_BitNumber * 4))

Definition at line 71 of file stm32f10x_cec.c.

Referenced by CEC_EndOfMessageCmd().

#define CSR_TSOM_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TSOM_BitNumber * 4))

Definition at line 67 of file stm32f10x_cec.c.

Referenced by CEC_StartOfMessage().

#define FLAG_Mask ((uint32_t)0x00FFFFFF)

Definition at line 74 of file stm32f10x_cec.c.

Referenced by CEC_GetFlagStatus().

#define IE_BitNumber 0x01

Definition at line 59 of file stm32f10x_cec.c.

#define PE_BitNumber 0x00

Definition at line 55 of file stm32f10x_cec.c.

#define TEOM_BitNumber 0x01

Definition at line 70 of file stm32f10x_cec.c.

#define TSOM_BitNumber 0x00

Definition at line 66 of file stm32f10x_cec.c.


STM32F10x Standard Peripherals Firmware Library: CEC_Private_Macros

CEC_Private_Macros

CEC


STM32F10x Standard Peripherals Firmware Library: CEC_Private_Variables

CEC_Private_Variables

CEC


STM32F10x Standard Peripherals Firmware Library: CEC_Private_FunctionPrototypes

CEC_Private_FunctionPrototypes

CEC


STM32F10x Standard Peripherals Firmware Library: CEC_Private_Functions

Functions

CEC_Private_Functions

CEC

Functions

void | CEC_ClearFlag (uint32_t CEC_FLAG)
Clears the CEC's pending flags.
void | CEC_ClearITPendingBit (uint16_t CEC_IT)
Clears the CEC's interrupt pending bits.
void | CEC_Cmd (FunctionalState NewState)
Enables or disables the specified CEC peripheral.
void | CEC_DeInit (void)
Deinitializes the CEC peripheral registers to their default reset values.
void | CEC_EndOfMessageCmd (FunctionalState NewState)
Transmits message with or without an EOM bit.
FlagStatus | CEC_GetFlagStatus (uint32_t CEC_FLAG)
Gets the CEC flag status.
ITStatus | CEC_GetITStatus (uint8_t CEC_IT)
Checks whether the specified CEC interrupt has occurred or not.
void | CEC_Init (CEC_InitTypeDef *CEC_InitStruct)
Initializes the CEC peripheral according to the specified parameters in the CEC_InitStruct.
void | CEC_ITConfig (FunctionalState NewState)
Enables or disables the CEC interrupt.
void | CEC_OwnAddressConfig (uint8_t CEC_OwnAddress)
Defines the Own Address of the CEC device.
uint8_t | CEC_ReceiveDataByte (void)
Returns the most recent received data by the CEC peripheral.
void | CEC_SendDataByte (uint8_t Data)
Transmits single data through the CEC peripheral.
void | CEC_SetPrescaler (uint16_t CEC_Prescaler)
Sets the CEC prescaler value.
void | CEC_StartOfMessage (void)
Starts a new message.

Function Documentation

void CEC_ClearFlag ( uint32_t CEC_FLAG )

Clears the CEC's pending flags.

Parameters:
CEC_FLAG,: specifies the flag to clear. This parameter can be any combination of the following values:

  • CEC_FLAG_TERR: Tx Error
  • CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished
  • CEC_FLAG_RSOM: Rx Start Of Message
  • CEC_FLAG_REOM: Rx End Of Message
  • CEC_FLAG_RERR: Rx Error
  • CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished
Return values:
None

Definition at line 349 of file stm32f10x_cec.c.

References assert_param, CEC, and IS_CEC_CLEAR_FLAG.

Referenced by CEC_IRQHandler(), HDMI_CEC_CheckConnectedDevices(), HDMI_CEC_GetErrorStatus(), HDMI_CEC_ProcessIRQSrc(), HDMI_CEC_TransmitMessage(), and LogicalAddressAllocation().

void CEC_ClearITPendingBit ( uint16_t CEC_IT )

Clears the CEC's interrupt pending bits.

Parameters:
CEC_IT,: specifies the CEC interrupt pending bit to clear. This parameter can be any combination of the following values:

  • CEC_IT_TERR: Tx Error
  • CEC_IT_TBTF: Tx Block Transfer Finished
  • CEC_IT_RERR: Rx Error
  • CEC_IT_RBTF: Rx Block Transfer Finished
Return values:
None

Definition at line 408 of file stm32f10x_cec.c.

References assert_param, CEC, and IS_CEC_GET_IT.

void CEC_Cmd ( FunctionalState NewState )

Enables or disables the specified CEC peripheral.

Parameters:
NewState,: new state of the CEC peripheral. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 164 of file stm32f10x_cec.c.

References assert_param, CEC, CEC_CFGR_PE, CFGR_PE_BB, DISABLE, IS_FUNCTIONAL_STATE, and RESET.

Referenced by HDMI_CEC_Init(), and main().

void CEC_DeInit ( void )

Deinitializes the CEC peripheral registers to their default reset values.

Parameters:
None
Return values:
None

Definition at line 118 of file stm32f10x_cec.c.

References DISABLE, ENABLE, RCC_APB1Periph_CEC, and RCC_APB1PeriphResetCmd().

Referenced by HDMI_CEC_Init().

void CEC_EndOfMessageCmd ( FunctionalState NewState )

Transmits message with or without an EOM bit.

Parameters:
NewState,: new state of the CEC Tx End Of Message. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 262 of file stm32f10x_cec.c.

References assert_param, CSR_TEOM_BB, and IS_FUNCTIONAL_STATE.

Referenced by CEC_IRQHandler(), HDMI_CEC_CheckConnectedDevices(), HDMI_CEC_ProcessIRQSrc(), and LogicalAddressAllocation().

FlagStatus CEC_GetFlagStatus ( uint32_t CEC_FLAG )

Gets the CEC flag status.

Parameters:
CEC_FLAG,: specifies the CEC flag to check. This parameter can be one of the following values:

  • CEC_FLAG_BTE: Bit Timing Error
  • CEC_FLAG_BPE: Bit Period Error
  • CEC_FLAG_RBTFE: Rx Block Transfer Finished Error
  • CEC_FLAG_SBE: Start Bit Error
  • CEC_FLAG_ACKE: Block Acknowledge Error
  • CEC_FLAG_LINE: Line Error
  • CEC_FLAG_TBTFE: Tx Block Transfer Finished Error
  • CEC_FLAG_TEOM: Tx End Of Message
  • CEC_FLAG_TERR: Tx Error
  • CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished
  • CEC_FLAG_RSOM: Rx Start Of Message
  • CEC_FLAG_REOM: Rx End Of Message
  • CEC_FLAG_RERR: Rx Error
  • CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished
Return values:
The new state of CEC_FLAG (SET or RESET)

Definition at line 291 of file stm32f10x_cec.c.

References assert_param, CEC_BASE, FLAG_Mask, IS_CEC_GET_FLAG, RESET, and SET.

Referenced by CEC_IRQHandler(), HDMI_CEC_CheckConnectedDevices(), HDMI_CEC_GetErrorStatus(), HDMI_CEC_ProcessIRQSrc(), and LogicalAddressAllocation().

ITStatus CEC_GetITStatus ( uint8_t CEC_IT )

Checks whether the specified CEC interrupt has occurred or not.

Parameters:
CEC_IT,: specifies the CEC interrupt source to check. This parameter can be one of the following values:

  • CEC_IT_TERR: Tx Error
  • CEC_IT_TBTF: Tx Block Transfer Finished
  • CEC_IT_RERR: Rx Error
  • CEC_IT_RBTF: Rx Block Transfer Finished
Return values:
The new state of CEC_IT (SET or RESET).

Definition at line 372 of file stm32f10x_cec.c.

References assert_param, CEC, CEC_CFGR_IE, IS_CEC_GET_IT, RESET, and SET.

void CEC_Init ( CEC_InitTypeDef * CEC_InitStruct )

Initializes the CEC peripheral according to the specified parameters in the CEC_InitStruct.

Parameters:
CEC_InitStruct,: pointer to an CEC_InitTypeDef structure that contains the configuration information for the specified CEC peripheral.
Return values:
None

Definition at line 135 of file stm32f10x_cec.c.

References assert_param, CEC, CEC_InitTypeDef::CEC_BitPeriodMode, CEC_InitTypeDef::CEC_BitTimingMode, CFGR_CLEAR_Mask, IS_CEC_BIT_PERIOD_ERROR_MODE, and IS_CEC_BIT_TIMING_ERROR_MODE.

Referenced by HDMI_CEC_Init(), and main().

void CEC_ITConfig ( FunctionalState NewState )

Enables or disables the CEC interrupt.

Parameters:
NewState,: new state of the CEC interrupt. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 186 of file stm32f10x_cec.c.

References assert_param, CFGR_IE_BB, and IS_FUNCTIONAL_STATE.

Referenced by HDMI_CEC_Init(), and main().

void CEC_OwnAddressConfig ( uint8_t CEC_OwnAddress )

Defines the Own Address of the CEC device.

Parameters:
CEC_OwnAddress,: The CEC own address
Return values:
None

Definition at line 199 of file stm32f10x_cec.c.

References assert_param, CEC, and IS_CEC_ADDRESS.

Referenced by HDMI_CEC_CheckConnectedDevices(), HDMI_CEC_Init(), LogicalAddressAllocation(), and main().

uint8_t CEC_ReceiveDataByte ( void )

Returns the most recent received data by the CEC peripheral.

Parameters:
None
Return values:
The received data.

Definition at line 239 of file stm32f10x_cec.c.

References CEC.

Referenced by CEC_IRQHandler(), and HDMI_CEC_ProcessIRQSrc().

void CEC_SendDataByte ( uint8_t Data )

Transmits single data through the CEC peripheral.

Parameters:
Data,: the data to transmit.
Return values:
None

Definition at line 227 of file stm32f10x_cec.c.

References CEC, and Data.

Referenced by CEC_IRQHandler(), EXTI9_5_IRQHandler(), HDMI_CEC_CheckConnectedDevices(), HDMI_CEC_ProcessIRQSrc(), HDMI_CEC_TransmitMessage(), and LogicalAddressAllocation().

void CEC_SetPrescaler ( uint16_t CEC_Prescaler )

Sets the CEC prescaler value.

Parameters:
CEC_Prescaler,: CEC prescaler new value
Return values:
None

Definition at line 213 of file stm32f10x_cec.c.

References assert_param, CEC, and IS_CEC_PRESCALER.

Referenced by HDMI_CEC_Init(), and main().

void CEC_StartOfMessage ( void )

Starts a new message.

Parameters:
None
Return values:
None

Definition at line 250 of file stm32f10x_cec.c.

References CSR_TSOM_BB.

Referenced by EXTI9_5_IRQHandler(), HDMI_CEC_CheckConnectedDevices(), HDMI_CEC_TransmitMessage(), and LogicalAddressAllocation().


STM32F10x Standard Peripherals Firmware Library: CRC_Exported_Types

CRC_Exported_Types

CRC


STM32F10x Standard Peripherals Firmware Library: CRC_Exported_Constants

CRC_Exported_Constants

CRC


STM32F10x Standard Peripherals Firmware Library: CRC_Exported_Macros

CRC_Exported_Macros

CRC


STM32F10x Standard Peripherals Firmware Library: CRC_Exported_Functions

Functions

CRC_Exported_Functions

CRC

Functions

uint32_t | CRC_CalcBlockCRC (uint32_t pBuffer[], uint32_t BufferLength)
Computes the 32-bit CRC of a given buffer of data word(32-bit).
uint32_t | CRC_CalcCRC (uint32_t Data)
Computes the 32-bit CRC of a given data word(32-bit).
uint32_t | CRC_GetCRC (void)
Returns the current CRC value.
uint8_t | CRC_GetIDRegister (void)
Returns the 8-bit data stored in the Independent Data(ID) register.
void | CRC_ResetDR (void)
Resets the CRC Data register (DR).
void | CRC_SetIDRegister (uint8_t IDValue)
Stores a 8-bit data in the Independent Data(ID) register.

Function Documentation

uint32_t CRC_CalcBlockCRC | ( | uint32_t | pBuffer[],
 |  | uint32_t | BufferLength
 | ) |  |

Computes the 32-bit CRC of a given buffer of data word(32-bit).

Parameters:
pBuffer,: pointer to the buffer containing the data to be computed
BufferLength,: length of the buffer to be computed
Return values:
32-bit CRC

Definition at line 107 of file stm32f10x_crc.c.

References CRC, and index.

Referenced by main().

uint32_t CRC_CalcCRC ( uint32_t Data )

Computes the 32-bit CRC of a given data word(32-bit).

Parameters:
Data,: data word(32-bit) to compute its CRC
Return values:
32-bit CRC

Definition at line 94 of file stm32f10x_crc.c.

References CRC, and Data.

uint32_t CRC_GetCRC ( void )

Returns the current CRC value.

Parameters:
None
Return values:
32-bit CRC

Definition at line 123 of file stm32f10x_crc.c.

References CRC.

uint8_t CRC_GetIDRegister ( void )

Returns the 8-bit data stored in the Independent Data(ID) register.

Parameters:
None
Return values:
8-bit value of the ID register

Definition at line 143 of file stm32f10x_crc.c.

References CRC.

void CRC_ResetDR ( void )

Resets the CRC Data register (DR).

Parameters:
None
Return values:
None

Definition at line 83 of file stm32f10x_crc.c.

References CRC, and CRC_CR_RESET.

void CRC_SetIDRegister ( uint8_t IDValue )

Stores a 8-bit data in the Independent Data(ID) register.

Parameters:
IDValue,: 8-bit value to be stored in the ID register
Return values:
None

Definition at line 133 of file stm32f10x_crc.c.

References CRC.


STM32F10x Standard Peripherals Firmware Library: CRC_Private_TypesDefinitions

CRC_Private_TypesDefinitions

CRC


STM32F10x Standard Peripherals Firmware Library: CRC_Private_Defines

CRC_Private_Defines

CRC


STM32F10x Standard Peripherals Firmware Library: CRC_Private_Macros

CRC_Private_Macros

CRC


STM32F10x Standard Peripherals Firmware Library: CRC_Private_Variables

CRC_Private_Variables

CRC


STM32F10x Standard Peripherals Firmware Library: CRC_Private_FunctionPrototypes

CRC_Private_FunctionPrototypes

CRC


STM32F10x Standard Peripherals Firmware Library: CRC_Private_Functions

Functions

CRC_Private_Functions

CRC

Functions

uint32_t | CRC_CalcBlockCRC (uint32_t pBuffer[], uint32_t BufferLength)
Computes the 32-bit CRC of a given buffer of data word(32-bit).
uint32_t | CRC_CalcCRC (uint32_t Data)
Computes the 32-bit CRC of a given data word(32-bit).
uint32_t | CRC_GetCRC (void)
Returns the current CRC value.
uint8_t | CRC_GetIDRegister (void)
Returns the 8-bit data stored in the Independent Data(ID) register.
void | CRC_ResetDR (void)
Resets the CRC Data register (DR).
void | CRC_SetIDRegister (uint8_t IDValue)
Stores a 8-bit data in the Independent Data(ID) register.

Function Documentation

uint32_t CRC_CalcBlockCRC | ( | uint32_t | pBuffer[],
 |  | uint32_t | BufferLength
 | ) |  |

Computes the 32-bit CRC of a given buffer of data word(32-bit).

Parameters:
pBuffer,: pointer to the buffer containing the data to be computed
BufferLength,: length of the buffer to be computed
Return values:
32-bit CRC

Definition at line 107 of file stm32f10x_crc.c.

References CRC, and index.

Referenced by main().

uint32_t CRC_CalcCRC ( uint32_t Data )

Computes the 32-bit CRC of a given data word(32-bit).

Parameters:
Data,: data word(32-bit) to compute its CRC
Return values:
32-bit CRC

Definition at line 94 of file stm32f10x_crc.c.

References CRC, and Data.

uint32_t CRC_GetCRC ( void )

Returns the current CRC value.

Parameters:
None
Return values:
32-bit CRC

Definition at line 123 of file stm32f10x_crc.c.

References CRC.

uint8_t CRC_GetIDRegister ( void )

Returns the 8-bit data stored in the Independent Data(ID) register.

Parameters:
None
Return values:
8-bit value of the ID register

Definition at line 143 of file stm32f10x_crc.c.

References CRC.

void CRC_ResetDR ( void )

Resets the CRC Data register (DR).

Parameters:
None
Return values:
None

Definition at line 83 of file stm32f10x_crc.c.

References CRC, and CRC_CR_RESET.

void CRC_SetIDRegister ( uint8_t IDValue )

Stores a 8-bit data in the Independent Data(ID) register.

Parameters:
IDValue,: 8-bit value to be stored in the ID register
Return values:
None

Definition at line 133 of file stm32f10x_crc.c.

References CRC.


STM32F10x Standard Peripherals Firmware Library: DAC_InitTypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

DAC_InitTypeDef Struct Reference
DAC_Exported_Types

DAC Init structure definition. More...

#include <stm32f10x_dac.h>

Data Fields

uint32_t | DAC_LFSRUnmask_TriangleAmplitude
uint32_t | DAC_OutputBuffer
uint32_t | DAC_Trigger
uint32_t | DAC_WaveGeneration

Detailed Description

DAC Init structure definition.

Definition at line 50 of file stm32f10x_dac.h.

Field Documentation

uint32_t DAC_InitTypeDef::DAC_LFSRUnmask_TriangleAmplitude

Specifies the LFSR mask for noise wave generation or the maximum amplitude triangle generation for the DAC channel. This parameter can be a value of DAC_lfsrunmask_triangleamplitude

Definition at line 59 of file stm32f10x_dac.h.

Referenced by DAC_Init(), DAC_StructInit(), and main().

uint32_t DAC_InitTypeDef::DAC_OutputBuffer

Specifies whether the DAC channel output buffer is enabled or disabled. This parameter can be a value of DAC_output_buffer

Definition at line 63 of file stm32f10x_dac.h.

Referenced by DAC_Init(), DAC_StructInit(), and main().

uint32_t DAC_InitTypeDef::DAC_Trigger

Specifies the external trigger for the selected DAC channel. This parameter can be a value of DAC_trigger_selection

Definition at line 52 of file stm32f10x_dac.h.

Referenced by DAC_Init(), DAC_StructInit(), and main().

uint32_t DAC_InitTypeDef::DAC_WaveGeneration

Specifies whether DAC channel noise waves or triangle waves are generated, or whether no wave is generated. This parameter can be a value of DAC_wave_generation

Definition at line 55 of file stm32f10x_dac.h.

Referenced by DAC_Init(), DAC_StructInit(), and main().

The documentation for this struct was generated from the following file:
  • stm32f10x_dac.h


STM32F10x Standard Peripherals Firmware Library: DAC_trigger_selection

Defines

DAC_trigger_selection

DAC_Exported_Constants

Defines

#define | DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034)
#define | DAC_Trigger_None ((uint32_t)0x00000000)
#define | DAC_Trigger_Software ((uint32_t)0x0000003C)
#define | DAC_Trigger_T15_TRGO ((uint32_t)0x0000001C)
#define | DAC_Trigger_T2_TRGO ((uint32_t)0x00000024)
#define | DAC_Trigger_T3_TRGO ((uint32_t)0x0000000C)
#define | DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C)
#define | DAC_Trigger_T5_TRGO ((uint32_t)0x0000001C)
#define | DAC_Trigger_T6_TRGO ((uint32_t)0x00000004)
#define | DAC_Trigger_T7_TRGO ((uint32_t)0x00000014)
#define | DAC_Trigger_T8_TRGO ((uint32_t)0x0000000C)
#define | IS_DAC_TRIGGER(TRIGGER)

Define Documentation

#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034)

EXTI Line9 event selected as external conversion trigger for DAC channel

Definition at line 92 of file stm32f10x_dac.h.

#define DAC_Trigger_None ((uint32_t)0x00000000)

Conversion is automatic once the DAC1_DHRxxxx register has been loaded, and not by external trigger

Definition at line 79 of file stm32f10x_dac.h.

Referenced by DAC_StructInit().

#define DAC_Trigger_Software ((uint32_t)0x0000003C)

Conversion started by software trigger for DAC channel

Definition at line 93 of file stm32f10x_dac.h.

Referenced by main().

#define DAC_Trigger_T15_TRGO ((uint32_t)0x0000001C)

TIM15 TRGO selected as external conversion trigger for DAC channel only in Medium-density and Low-density Value Line devices

Definition at line 88 of file stm32f10x_dac.h.

#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024)

TIM2 TRGO selected as external conversion trigger for DAC channel

Definition at line 90 of file stm32f10x_dac.h.

Referenced by main().

#define DAC_Trigger_T3_TRGO ((uint32_t)0x0000000C)

TIM8 TRGO selected as external conversion trigger for DAC channel only in Connectivity line, Medium-density and Low-density Value Line devices

Definition at line 84 of file stm32f10x_dac.h.

#define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C)

TIM4 TRGO selected as external conversion trigger for DAC channel

Definition at line 91 of file stm32f10x_dac.h.

#define DAC_Trigger_T5_TRGO ((uint32_t)0x0000001C)

TIM5 TRGO selected as external conversion trigger for DAC channel

Definition at line 87 of file stm32f10x_dac.h.

#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004)

TIM6 TRGO selected as external conversion trigger for DAC channel

Definition at line 81 of file stm32f10x_dac.h.

Referenced by main().

#define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014)

TIM7 TRGO selected as external conversion trigger for DAC channel

Definition at line 86 of file stm32f10x_dac.h.

#define DAC_Trigger_T8_TRGO ((uint32_t)0x0000000C)

TIM8 TRGO selected as external conversion trigger for DAC channel only in High-density devices

Definition at line 82 of file stm32f10x_dac.h.

#define IS_DAC_TRIGGER ( TRIGGER )
Value:
(((TRIGGER) == DAC_Trigger_None) || \
                                 ((TRIGGER) == DAC_Trigger_T6_TRGO) || \
                                 ((TRIGGER) == DAC_Trigger_T8_TRGO) || \
                                 ((TRIGGER) == DAC_Trigger_T7_TRGO) || \
                                 ((TRIGGER) == DAC_Trigger_T5_TRGO) || \
                                 ((TRIGGER) == DAC_Trigger_T2_TRGO) || \
                                 ((TRIGGER) == DAC_Trigger_T4_TRGO) || \
                                 ((TRIGGER) == DAC_Trigger_Ext_IT9) || \
                                 ((TRIGGER) == DAC_Trigger_Software))

Definition at line 95 of file stm32f10x_dac.h.

Referenced by DAC_Init().


STM32F10x Standard Peripherals Firmware Library: DAC_wave_generation

Defines

DAC_wave_generation

DAC_Exported_Constants

Defines

#define | DAC_Wave_Noise ((uint32_t)0x00000040)
#define | DAC_Wave_Triangle ((uint32_t)0x00000080)
#define | DAC_WaveGeneration_Noise ((uint32_t)0x00000040)
#define | DAC_WaveGeneration_None ((uint32_t)0x00000000)
#define | DAC_WaveGeneration_Triangle ((uint32_t)0x00000080)
#define | IS_DAC_GENERATE_WAVE(WAVE)
#define | IS_DAC_WAVE(WAVE)

Define Documentation

#define DAC_Wave_Noise ((uint32_t)0x00000040)

Definition at line 222 of file stm32f10x_dac.h.

#define DAC_Wave_Triangle ((uint32_t)0x00000080)

Definition at line 223 of file stm32f10x_dac.h.

#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040)

Definition at line 114 of file stm32f10x_dac.h.

Referenced by main().

#define DAC_WaveGeneration_None ((uint32_t)0x00000000)

Definition at line 113 of file stm32f10x_dac.h.

Referenced by DAC_StructInit(), and main().

#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080)

Definition at line 115 of file stm32f10x_dac.h.

Referenced by main().

#define IS_DAC_GENERATE_WAVE ( WAVE )
Value:
(((WAVE) == DAC_WaveGeneration_None) || \
                                    ((WAVE) == DAC_WaveGeneration_Noise) || \
                                    ((WAVE) == DAC_WaveGeneration_Triangle))

Definition at line 116 of file stm32f10x_dac.h.

Referenced by DAC_Init().

#define IS_DAC_WAVE ( WAVE )
Value:
(((WAVE) == DAC_Wave_Noise) || \
                           ((WAVE) == DAC_Wave_Triangle))

Definition at line 224 of file stm32f10x_dac.h.

Referenced by DAC_WaveGenerationCmd().


STM32F10x Standard Peripherals Firmware Library: DAC_lfsrunmask_triangleamplitude

Defines

DAC_lfsrunmask_triangleamplitude

DAC_Exported_Constants

Defines

#define | DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000)
#define | DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00)
#define | DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00)
#define | DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100)
#define | DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200)
#define | DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300)
#define | DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400)
#define | DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500)
#define | DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600)
#define | DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700)
#define | DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800)
#define | DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900)
#define | DAC_TriangleAmplitude_1 ((uint32_t)0x00000000)
#define | DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900)
#define | DAC_TriangleAmplitude_127 ((uint32_t)0x00000600)
#define | DAC_TriangleAmplitude_15 ((uint32_t)0x00000300)
#define | DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00)
#define | DAC_TriangleAmplitude_255 ((uint32_t)0x00000700)
#define | DAC_TriangleAmplitude_3 ((uint32_t)0x00000100)
#define | DAC_TriangleAmplitude_31 ((uint32_t)0x00000400)
#define | DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00)
#define | DAC_TriangleAmplitude_511 ((uint32_t)0x00000800)
#define | DAC_TriangleAmplitude_63 ((uint32_t)0x00000500)
#define | DAC_TriangleAmplitude_7 ((uint32_t)0x00000200)
#define | IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE)

Define Documentation

#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000)

Unmask DAC channel LFSR bit0 for noise wave generation

Definition at line 127 of file stm32f10x_dac.h.

Referenced by DAC_StructInit().

#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00)

Unmask DAC channel LFSR bit[10:0] for noise wave generation

Definition at line 137 of file stm32f10x_dac.h.

#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00)

Unmask DAC channel LFSR bit[11:0] for noise wave generation

Definition at line 138 of file stm32f10x_dac.h.

#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100)

Unmask DAC channel LFSR bit[1:0] for noise wave generation

Definition at line 128 of file stm32f10x_dac.h.

#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200)

Unmask DAC channel LFSR bit[2:0] for noise wave generation

Definition at line 129 of file stm32f10x_dac.h.

#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300)

Unmask DAC channel LFSR bit[3:0] for noise wave generation

Definition at line 130 of file stm32f10x_dac.h.

#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400)

Unmask DAC channel LFSR bit[4:0] for noise wave generation

Definition at line 131 of file stm32f10x_dac.h.

#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500)

Unmask DAC channel LFSR bit[5:0] for noise wave generation

Definition at line 132 of file stm32f10x_dac.h.

#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600)

Unmask DAC channel LFSR bit[6:0] for noise wave generation

Definition at line 133 of file stm32f10x_dac.h.

#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700)

Unmask DAC channel LFSR bit[7:0] for noise wave generation

Definition at line 134 of file stm32f10x_dac.h.

#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800)

Unmask DAC channel LFSR bit[8:0] for noise wave generation

Definition at line 135 of file stm32f10x_dac.h.

Referenced by main().

#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900)

Unmask DAC channel LFSR bit[9:0] for noise wave generation

Definition at line 136 of file stm32f10x_dac.h.

#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000)

Select max triangle amplitude of 1

Definition at line 139 of file stm32f10x_dac.h.

#define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900)

Select max triangle amplitude of 1023

Definition at line 148 of file stm32f10x_dac.h.

Referenced by main().

#define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600)

Select max triangle amplitude of 127

Definition at line 145 of file stm32f10x_dac.h.

#define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300)

Select max triangle amplitude of 15

Definition at line 142 of file stm32f10x_dac.h.

#define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00)

Select max triangle amplitude of 2047

Definition at line 149 of file stm32f10x_dac.h.

Referenced by main().

#define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700)

Select max triangle amplitude of 255

Definition at line 146 of file stm32f10x_dac.h.

#define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100)

Select max triangle amplitude of 3

Definition at line 140 of file stm32f10x_dac.h.

#define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400)

Select max triangle amplitude of 31

Definition at line 143 of file stm32f10x_dac.h.

#define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00)

Select max triangle amplitude of 4095

Definition at line 150 of file stm32f10x_dac.h.

#define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800)

Select max triangle amplitude of 511

Definition at line 147 of file stm32f10x_dac.h.

#define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500)

Select max triangle amplitude of 63

Definition at line 144 of file stm32f10x_dac.h.

#define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200)

Select max triangle amplitude of 7

Definition at line 141 of file stm32f10x_dac.h.

#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE ( VALUE )
Value:
(((VALUE) == DAC_LFSRUnmask_Bit0) || \
                                                      ((VALUE) == DAC_LFSRUnmask_Bits1_0) || \
                                                      ((VALUE) == DAC_LFSRUnmask_Bits2_0) || \
                                                      ((VALUE) == DAC_LFSRUnmask_Bits3_0) || \
                                                      ((VALUE) == DAC_LFSRUnmask_Bits4_0) || \
                                                      ((VALUE) == DAC_LFSRUnmask_Bits5_0) || \
                                                      ((VALUE) == DAC_LFSRUnmask_Bits6_0) || \
                                                      ((VALUE) == DAC_LFSRUnmask_Bits7_0) || \
                                                      ((VALUE) == DAC_LFSRUnmask_Bits8_0) || \
                                                      ((VALUE) == DAC_LFSRUnmask_Bits9_0) || \
                                                      ((VALUE) == DAC_LFSRUnmask_Bits10_0) || \
                                                      ((VALUE) == DAC_LFSRUnmask_Bits11_0) || \
                                                      ((VALUE) == DAC_TriangleAmplitude_1) || \
                                                      ((VALUE) == DAC_TriangleAmplitude_3) || \
                                                      ((VALUE) == DAC_TriangleAmplitude_7) || \
                                                      ((VALUE) == DAC_TriangleAmplitude_15) || \
                                                      ((VALUE) == DAC_TriangleAmplitude_31) || \
                                                      ((VALUE) == DAC_TriangleAmplitude_63) || \
                                                      ((VALUE) == DAC_TriangleAmplitude_127) || \
                                                      ((VALUE) == DAC_TriangleAmplitude_255) || \
                                                      ((VALUE) == DAC_TriangleAmplitude_511) || \
                                                      ((VALUE) == DAC_TriangleAmplitude_1023) || \
                                                      ((VALUE) == DAC_TriangleAmplitude_2047) || \
                                                      ((VALUE) == DAC_TriangleAmplitude_4095))

Definition at line 152 of file stm32f10x_dac.h.

Referenced by DAC_Init().


STM32F10x Standard Peripherals Firmware Library: DAC_output_buffer

Defines

DAC_output_buffer

DAC_Exported_Constants

Defines

#define | DAC_OutputBuffer_Disable ((uint32_t)0x00000002)
#define | DAC_OutputBuffer_Enable ((uint32_t)0x00000000)
#define | IS_DAC_OUTPUT_BUFFER_STATE(STATE)

Define Documentation

#define DAC_OutputBuffer_Disable ((uint32_t)0x00000002)

Definition at line 185 of file stm32f10x_dac.h.

Referenced by main().

#define DAC_OutputBuffer_Enable ((uint32_t)0x00000000)

Definition at line 184 of file stm32f10x_dac.h.

Referenced by DAC_StructInit(), and main().

#define IS_DAC_OUTPUT_BUFFER_STATE ( STATE )
Value:
(((STATE) == DAC_OutputBuffer_Enable) || \
                                           ((STATE) == DAC_OutputBuffer_Disable))

Definition at line 186 of file stm32f10x_dac.h.

Referenced by DAC_Init().


STM32F10x Standard Peripherals Firmware Library: DAC_Channel_selection

Defines

DAC_Channel_selection

DAC_Exported_Constants

Defines

#define | DAC_Channel_1 ((uint32_t)0x00000000)
#define | DAC_Channel_2 ((uint32_t)0x00000010)
#define | IS_DAC_CHANNEL(CHANNEL)

Define Documentation

#define DAC_Channel_1 ((uint32_t)0x00000000)

Definition at line 196 of file stm32f10x_dac.h.

Referenced by main().

#define DAC_Channel_2 ((uint32_t)0x00000010)

Definition at line 197 of file stm32f10x_dac.h.

Referenced by main().

#define IS_DAC_CHANNEL ( CHANNEL )
Value:
(((CHANNEL) == DAC_Channel_1) || \
                                 ((CHANNEL) == DAC_Channel_2))

Definition at line 198 of file stm32f10x_dac.h.

Referenced by DAC_Cmd(), DAC_DMACmd(), DAC_GetDataOutputValue(), DAC_SoftwareTriggerCmd(), and DAC_WaveGenerationCmd().


STM32F10x Standard Peripherals Firmware Library: DAC_data_alignment

Defines

DAC_data_alignment

DAC_Exported_Constants

Defines

#define | DAC_Align_12b_L ((uint32_t)0x00000004)
#define | DAC_Align_12b_R ((uint32_t)0x00000000)
#define | DAC_Align_8b_R ((uint32_t)0x00000008)
#define | IS_DAC_ALIGN(ALIGN)

Define Documentation

#define DAC_Align_12b_L ((uint32_t)0x00000004)

Definition at line 209 of file stm32f10x_dac.h.

Referenced by main().

#define DAC_Align_12b_R ((uint32_t)0x00000000)

Definition at line 208 of file stm32f10x_dac.h.

Referenced by main().

#define DAC_Align_8b_R ((uint32_t)0x00000008)

Definition at line 210 of file stm32f10x_dac.h.

Referenced by DAC_SetDualChannelData().

#define IS_DAC_ALIGN ( ALIGN )
Value:
(((ALIGN) == DAC_Align_12b_R) || \
                             ((ALIGN) == DAC_Align_12b_L) || \
                             ((ALIGN) == DAC_Align_8b_R))

Definition at line 211 of file stm32f10x_dac.h.

Referenced by DAC_SetChannel1Data(), DAC_SetChannel2Data(), and DAC_SetDualChannelData().


STM32F10x Standard Peripherals Firmware Library: DAC_data

Defines

DAC_data

DAC_Exported_Constants

Defines

#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)

Define Documentation

#define IS_DAC_DATA ( DATA ) ((DATA) <= 0xFFF0)

Definition at line 234 of file stm32f10x_dac.h.

Referenced by DAC_SetChannel1Data(), DAC_SetChannel2Data(), and DAC_SetDualChannelData().


STM32F10x Standard Peripherals Firmware Library: DAC_Exported_Macros

DAC_Exported_Macros

DAC


STM32F10x Standard Peripherals Firmware Library: DAC_Exported_Functions

Functions

DAC_Exported_Functions

DAC

Functions

void | DAC_Cmd (uint32_t DAC_Channel, FunctionalState NewState)
Enables or disables the specified DAC channel.
void | DAC_DeInit (void)
Deinitializes the DAC peripheral registers to their default reset values.
void | DAC_DMACmd (uint32_t DAC_Channel, FunctionalState NewState)
Enables or disables the specified DAC channel DMA request.
void | DAC_DualSoftwareTriggerCmd (FunctionalState NewState)
Enables or disables simultaneously the two DAC channels software triggers.
uint16_t | DAC_GetDataOutputValue (uint32_t DAC_Channel)
Returns the last data output value of the selected DAC channel.
void | DAC_Init (uint32_t DAC_Channel, DAC_InitTypeDef *DAC_InitStruct)
Initializes the DAC peripheral according to the specified parameters in the DAC_InitStruct.
void | DAC_SetChannel1Data (uint32_t DAC_Align, uint16_t Data)
Set the specified data holding register value for DAC channel1.
void | DAC_SetChannel2Data (uint32_t DAC_Align, uint16_t Data)
Set the specified data holding register value for DAC channel2.
void | DAC_SetDualChannelData (uint32_t DAC_Align, uint16_t Data2, uint16_t Data1)
Set the specified data holding register value for dual channel DAC.
void | DAC_SoftwareTriggerCmd (uint32_t DAC_Channel, FunctionalState NewState)
Enables or disables the selected DAC channel software trigger.
void | DAC_StructInit (DAC_InitTypeDef *DAC_InitStruct)
Fills each DAC_InitStruct member with its default value.
void | DAC_WaveGenerationCmd (uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState)
Enables or disables the selected DAC channel wave generation.

Function Documentation

void DAC_Cmd | ( | uint32_t | DAC_Channel,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified DAC channel.

Parameters:
DAC_Channel,: the selected DAC channel. This parameter can be one of the following values:

  • DAC_Channel_1: DAC Channel1 selected
  • DAC_Channel_2: DAC Channel2 selected
NewState,: new state of the DAC channel. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 173 of file stm32f10x_dac.c.

References assert_param, DAC, DAC_CR_EN1, DISABLE, IS_DAC_CHANNEL, and IS_FUNCTIONAL_STATE.

Referenced by main().

void DAC_DeInit ( void )

Deinitializes the DAC peripheral registers to their default reset values.

Parameters:
None
Return values:
None

Definition at line 98 of file stm32f10x_dac.c.

References DISABLE, ENABLE, RCC_APB1Periph_DAC, and RCC_APB1PeriphResetCmd().

void DAC_DMACmd | ( | uint32_t | DAC_Channel,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified DAC channel DMA request.

Parameters:
DAC_Channel,: the selected DAC channel. This parameter can be one of the following values:

  • DAC_Channel_1: DAC Channel1 selected
  • DAC_Channel_2: DAC Channel2 selected
NewState,: new state of the selected DAC channel DMA request. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 233 of file stm32f10x_dac.c.

References assert_param, DAC, DAC_CR_DMAEN1, DISABLE, IS_DAC_CHANNEL, and IS_FUNCTIONAL_STATE.

Referenced by main().

void DAC_DualSoftwareTriggerCmd ( FunctionalState NewState )

Enables or disables simultaneously the two DAC channels software triggers.

Parameters:
NewState,: new state of the DAC channels software triggers. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 284 of file stm32f10x_dac.c.

References assert_param, DAC, DISABLE, DUAL_SWTRIG_RESET, DUAL_SWTRIG_SET, and IS_FUNCTIONAL_STATE.

uint16_t DAC_GetDataOutputValue ( uint32_t DAC_Channel )

Returns the last data output value of the selected DAC channel.

Parameters:
DAC_Channel,: the selected DAC channel. This parameter can be one of the following values:

  • DAC_Channel_1: DAC Channel1 selected
  • DAC_Channel_2: DAC Channel2 selected
Return values:
The selected DAC channel data output value.

Definition at line 430 of file stm32f10x_dac.c.

References assert_param, DAC_BASE, DOR_OFFSET, and IS_DAC_CHANNEL.

void DAC_Init | ( | uint32_t | DAC_Channel,
 |  | DAC_InitTypeDef * | DAC_InitStruct
 | ) |  |

Initializes the DAC peripheral according to the specified parameters in the DAC_InitStruct.

Parameters:
DAC_Channel,: the selected DAC channel. This parameter can be one of the following values:

  • DAC_Channel_1: DAC Channel1 selected
  • DAC_Channel_2: DAC Channel2 selected
DAC_InitStruct,: pointer to a DAC_InitTypeDef structure that contains the configuration information for the specified DAC channel.
Return values:
None

Definition at line 117 of file stm32f10x_dac.c.

References assert_param, CR_CLEAR_MASK, DAC, DAC_InitTypeDef::DAC_LFSRUnmask_TriangleAmplitude, DAC_InitTypeDef::DAC_OutputBuffer, DAC_InitTypeDef::DAC_Trigger, DAC_InitTypeDef::DAC_WaveGeneration, IS_DAC_GENERATE_WAVE, IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE, IS_DAC_OUTPUT_BUFFER_STATE, and IS_DAC_TRIGGER.

Referenced by main().

void DAC_SetChannel1Data | ( | uint32_t | DAC_Align,
 |  | uint16_t | Data
 | ) |  |

Set the specified data holding register value for DAC channel1.

Parameters:
DAC_Align,: Specifies the data alignment for DAC channel1. This parameter can be one of the following values:

  • DAC_Align_8b_R: 8bit right data alignment selected
  • DAC_Align_12b_L: 12bit left data alignment selected
  • DAC_Align_12b_R: 12bit right data alignment selected
Data : Data to be loaded in the selected data holding register.
Return values:
None

Definition at line 342 of file stm32f10x_dac.c.

References assert_param, DAC_BASE, DHR12R1_OFFSET, IS_DAC_ALIGN, and IS_DAC_DATA.

Referenced by main().

void DAC_SetChannel2Data | ( | uint32_t | DAC_Align,
 |  | uint16_t | Data
 | ) |  |

Set the specified data holding register value for DAC channel2.

Parameters:
DAC_Align,: Specifies the data alignment for DAC channel2. This parameter can be one of the following values:

  • DAC_Align_8b_R: 8bit right data alignment selected
  • DAC_Align_12b_L: 12bit left data alignment selected
  • DAC_Align_12b_R: 12bit right data alignment selected
Data : Data to be loaded in the selected data holding register.
Return values:
None

Definition at line 367 of file stm32f10x_dac.c.

References assert_param, DAC_BASE, DHR12R2_OFFSET, IS_DAC_ALIGN, and IS_DAC_DATA.

void DAC_SetDualChannelData | ( | uint32_t | DAC_Align,
 |  | uint16_t | Data2,
 |  | uint16_t | Data1
 | ) |  |

Set the specified data holding register value for dual channel DAC.

Parameters:
DAC_Align,: Specifies the data alignment for dual channel DAC. This parameter can be one of the following values:

  • DAC_Align_8b_R: 8bit right data alignment selected
  • DAC_Align_12b_L: 12bit left data alignment selected
  • DAC_Align_12b_R: 12bit right data alignment selected
Data2,: Data for DAC Channel2 to be loaded in the selected data holding register.
Data1,: Data for DAC Channel1 to be loaded in the selected data holding register.
Return values:
None

Definition at line 396 of file stm32f10x_dac.c.

References assert_param, DAC_Align_8b_R, DAC_BASE, DHR12RD_OFFSET, IS_DAC_ALIGN, and IS_DAC_DATA.

Referenced by main().

void DAC_SoftwareTriggerCmd | ( | uint32_t | DAC_Channel,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the selected DAC channel software trigger.

Parameters:
DAC_Channel,: the selected DAC channel. This parameter can be one of the following values:

  • DAC_Channel_1: DAC Channel1 selected
  • DAC_Channel_2: DAC Channel2 selected
NewState,: new state of the selected DAC channel software trigger. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 260 of file stm32f10x_dac.c.

References assert_param, DAC, DAC_SWTRIGR_SWTRIG1, DISABLE, IS_DAC_CHANNEL, and IS_FUNCTIONAL_STATE.

Referenced by main().

void DAC_StructInit ( DAC_InitTypeDef * DAC_InitStruct )

Fills each DAC_InitStruct member with its default value.

Parameters:
DAC_InitStruct : pointer to a DAC_InitTypeDef structure which will be initialized.
Return values:
None

Definition at line 150 of file stm32f10x_dac.c.

References DAC_LFSRUnmask_Bit0, DAC_InitTypeDef::DAC_LFSRUnmask_TriangleAmplitude, DAC_InitTypeDef::DAC_OutputBuffer, DAC_OutputBuffer_Enable, DAC_InitTypeDef::DAC_Trigger, DAC_Trigger_None, DAC_InitTypeDef::DAC_WaveGeneration, and DAC_WaveGeneration_None.

void DAC_WaveGenerationCmd | ( | uint32_t | DAC_Channel,
 |  | uint32_t | DAC_Wave,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the selected DAC channel wave generation.

Parameters:
DAC_Channel,: the selected DAC channel. This parameter can be one of the following values:

  • DAC_Channel_1: DAC Channel1 selected
  • DAC_Channel_2: DAC Channel2 selected
DAC_Wave,: Specifies the wave type to enable or disable. This parameter can be one of the following values:

  • DAC_Wave_Noise: noise wave generation
  • DAC_Wave_Triangle: triangle wave generation
NewState,: new state of the selected DAC channel wave generation. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 314 of file stm32f10x_dac.c.

References assert_param, DAC, DISABLE, IS_DAC_CHANNEL, IS_DAC_WAVE, and IS_FUNCTIONAL_STATE.


STM32F10x Standard Peripherals Firmware Library: DAC_Private_TypesDefinitions

DAC_Private_TypesDefinitions

DAC


STM32F10x Standard Peripherals Firmware Library: DAC_Private_Defines

Defines

DAC_Private_Defines

DAC

Defines

#define | CR_CLEAR_MASK ((uint32_t)0x00000FFE)
#define | DHR12R1_OFFSET ((uint32_t)0x00000008)
#define | DHR12R2_OFFSET ((uint32_t)0x00000014)
#define | DHR12RD_OFFSET ((uint32_t)0x00000020)
#define | DOR_OFFSET ((uint32_t)0x0000002C)
#define | DUAL_SWTRIG_RESET ((uint32_t)0xFFFFFFFC)
#define | DUAL_SWTRIG_SET ((uint32_t)0x00000003)

Define Documentation

#define CR_CLEAR_MASK ((uint32_t)0x00000FFE)

Definition at line 48 of file stm32f10x_dac.c.

Referenced by DAC_Init().

#define DHR12R1_OFFSET ((uint32_t)0x00000008)

Definition at line 55 of file stm32f10x_dac.c.

Referenced by DAC_SetChannel1Data().

#define DHR12R2_OFFSET ((uint32_t)0x00000014)

Definition at line 56 of file stm32f10x_dac.c.

Referenced by DAC_SetChannel2Data().

#define DHR12RD_OFFSET ((uint32_t)0x00000020)

Definition at line 57 of file stm32f10x_dac.c.

Referenced by DAC_SetDualChannelData().

#define DOR_OFFSET ((uint32_t)0x0000002C)

Definition at line 60 of file stm32f10x_dac.c.

Referenced by DAC_GetDataOutputValue().

#define DUAL_SWTRIG_RESET ((uint32_t)0xFFFFFFFC)

Definition at line 52 of file stm32f10x_dac.c.

Referenced by DAC_DualSoftwareTriggerCmd().

#define DUAL_SWTRIG_SET ((uint32_t)0x00000003)

Definition at line 51 of file stm32f10x_dac.c.

Referenced by DAC_DualSoftwareTriggerCmd().


STM32F10x Standard Peripherals Firmware Library: DAC_Private_Macros

DAC_Private_Macros

DAC


STM32F10x Standard Peripherals Firmware Library: DAC_Private_Variables

DAC_Private_Variables

DAC


STM32F10x Standard Peripherals Firmware Library: DAC_Private_FunctionPrototypes

DAC_Private_FunctionPrototypes

DAC


STM32F10x Standard Peripherals Firmware Library: DAC_Private_Functions

Functions

DAC_Private_Functions

DAC

Functions

void | DAC_Cmd (uint32_t DAC_Channel, FunctionalState NewState)
Enables or disables the specified DAC channel.
void | DAC_DeInit (void)
Deinitializes the DAC peripheral registers to their default reset values.
void | DAC_DMACmd (uint32_t DAC_Channel, FunctionalState NewState)
Enables or disables the specified DAC channel DMA request.
void | DAC_DualSoftwareTriggerCmd (FunctionalState NewState)
Enables or disables simultaneously the two DAC channels software triggers.
uint16_t | DAC_GetDataOutputValue (uint32_t DAC_Channel)
Returns the last data output value of the selected DAC channel.
void | DAC_Init (uint32_t DAC_Channel, DAC_InitTypeDef *DAC_InitStruct)
Initializes the DAC peripheral according to the specified parameters in the DAC_InitStruct.
void | DAC_SetChannel1Data (uint32_t DAC_Align, uint16_t Data)
Set the specified data holding register value for DAC channel1.
void | DAC_SetChannel2Data (uint32_t DAC_Align, uint16_t Data)
Set the specified data holding register value for DAC channel2.
void | DAC_SetDualChannelData (uint32_t DAC_Align, uint16_t Data2, uint16_t Data1)
Set the specified data holding register value for dual channel DAC.
void | DAC_SoftwareTriggerCmd (uint32_t DAC_Channel, FunctionalState NewState)
Enables or disables the selected DAC channel software trigger.
void | DAC_StructInit (DAC_InitTypeDef *DAC_InitStruct)
Fills each DAC_InitStruct member with its default value.
void | DAC_WaveGenerationCmd (uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState)
Enables or disables the selected DAC channel wave generation.

Function Documentation

void DAC_Cmd | ( | uint32_t | DAC_Channel,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified DAC channel.

Parameters:
DAC_Channel,: the selected DAC channel. This parameter can be one of the following values:

  • DAC_Channel_1: DAC Channel1 selected
  • DAC_Channel_2: DAC Channel2 selected
NewState,: new state of the DAC channel. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 173 of file stm32f10x_dac.c.

References assert_param, DAC, DAC_CR_EN1, DISABLE, IS_DAC_CHANNEL, and IS_FUNCTIONAL_STATE.

Referenced by main().

void DAC_DeInit ( void )

Deinitializes the DAC peripheral registers to their default reset values.

Parameters:
None
Return values:
None

Definition at line 98 of file stm32f10x_dac.c.

References DISABLE, ENABLE, RCC_APB1Periph_DAC, and RCC_APB1PeriphResetCmd().

void DAC_DMACmd | ( | uint32_t | DAC_Channel,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified DAC channel DMA request.

Parameters:
DAC_Channel,: the selected DAC channel. This parameter can be one of the following values:

  • DAC_Channel_1: DAC Channel1 selected
  • DAC_Channel_2: DAC Channel2 selected
NewState,: new state of the selected DAC channel DMA request. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 233 of file stm32f10x_dac.c.

References assert_param, DAC, DAC_CR_DMAEN1, DISABLE, IS_DAC_CHANNEL, and IS_FUNCTIONAL_STATE.

Referenced by main().

void DAC_DualSoftwareTriggerCmd ( FunctionalState NewState )

Enables or disables simultaneously the two DAC channels software triggers.

Parameters:
NewState,: new state of the DAC channels software triggers. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 284 of file stm32f10x_dac.c.

References assert_param, DAC, DISABLE, DUAL_SWTRIG_RESET, DUAL_SWTRIG_SET, and IS_FUNCTIONAL_STATE.

uint16_t DAC_GetDataOutputValue ( uint32_t DAC_Channel )

Returns the last data output value of the selected DAC channel.

Parameters:
DAC_Channel,: the selected DAC channel. This parameter can be one of the following values:

  • DAC_Channel_1: DAC Channel1 selected
  • DAC_Channel_2: DAC Channel2 selected
Return values:
The selected DAC channel data output value.

Definition at line 430 of file stm32f10x_dac.c.

References assert_param, DAC_BASE, DOR_OFFSET, and IS_DAC_CHANNEL.

void DAC_Init | ( | uint32_t | DAC_Channel,
 |  | DAC_InitTypeDef * | DAC_InitStruct
 | ) |  |

Initializes the DAC peripheral according to the specified parameters in the DAC_InitStruct.

Parameters:
DAC_Channel,: the selected DAC channel. This parameter can be one of the following values:

  • DAC_Channel_1: DAC Channel1 selected
  • DAC_Channel_2: DAC Channel2 selected
DAC_InitStruct,: pointer to a DAC_InitTypeDef structure that contains the configuration information for the specified DAC channel.
Return values:
None

Definition at line 117 of file stm32f10x_dac.c.

References assert_param, CR_CLEAR_MASK, DAC, DAC_InitTypeDef::DAC_LFSRUnmask_TriangleAmplitude, DAC_InitTypeDef::DAC_OutputBuffer, DAC_InitTypeDef::DAC_Trigger, DAC_InitTypeDef::DAC_WaveGeneration, IS_DAC_GENERATE_WAVE, IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE, IS_DAC_OUTPUT_BUFFER_STATE, and IS_DAC_TRIGGER.

Referenced by main().

void DAC_SetChannel1Data | ( | uint32_t | DAC_Align,
 |  | uint16_t | Data
 | ) |  |

Set the specified data holding register value for DAC channel1.

Parameters:
DAC_Align,: Specifies the data alignment for DAC channel1. This parameter can be one of the following values:

  • DAC_Align_8b_R: 8bit right data alignment selected
  • DAC_Align_12b_L: 12bit left data alignment selected
  • DAC_Align_12b_R: 12bit right data alignment selected
Data : Data to be loaded in the selected data holding register.
Return values:
None

Definition at line 342 of file stm32f10x_dac.c.

References assert_param, DAC_BASE, DHR12R1_OFFSET, IS_DAC_ALIGN, and IS_DAC_DATA.

Referenced by main().

void DAC_SetChannel2Data | ( | uint32_t | DAC_Align,
 |  | uint16_t | Data
 | ) |  |

Set the specified data holding register value for DAC channel2.

Parameters:
DAC_Align,: Specifies the data alignment for DAC channel2. This parameter can be one of the following values:

  • DAC_Align_8b_R: 8bit right data alignment selected
  • DAC_Align_12b_L: 12bit left data alignment selected
  • DAC_Align_12b_R: 12bit right data alignment selected
Data : Data to be loaded in the selected data holding register.
Return values:
None

Definition at line 367 of file stm32f10x_dac.c.

References assert_param, DAC_BASE, DHR12R2_OFFSET, IS_DAC_ALIGN, and IS_DAC_DATA.

void DAC_SetDualChannelData | ( | uint32_t | DAC_Align,
 |  | uint16_t | Data2,
 |  | uint16_t | Data1
 | ) |  |

Set the specified data holding register value for dual channel DAC.

Parameters:
DAC_Align,: Specifies the data alignment for dual channel DAC. This parameter can be one of the following values:

  • DAC_Align_8b_R: 8bit right data alignment selected
  • DAC_Align_12b_L: 12bit left data alignment selected
  • DAC_Align_12b_R: 12bit right data alignment selected
Data2,: Data for DAC Channel2 to be loaded in the selected data holding register.
Data1,: Data for DAC Channel1 to be loaded in the selected data holding register.
Return values:
None

Definition at line 396 of file stm32f10x_dac.c.

References assert_param, DAC_Align_8b_R, DAC_BASE, DHR12RD_OFFSET, IS_DAC_ALIGN, and IS_DAC_DATA.

Referenced by main().

void DAC_SoftwareTriggerCmd | ( | uint32_t | DAC_Channel,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the selected DAC channel software trigger.

Parameters:
DAC_Channel,: the selected DAC channel. This parameter can be one of the following values:

  • DAC_Channel_1: DAC Channel1 selected
  • DAC_Channel_2: DAC Channel2 selected
NewState,: new state of the selected DAC channel software trigger. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 260 of file stm32f10x_dac.c.

References assert_param, DAC, DAC_SWTRIGR_SWTRIG1, DISABLE, IS_DAC_CHANNEL, and IS_FUNCTIONAL_STATE.

Referenced by main().

void DAC_StructInit ( DAC_InitTypeDef * DAC_InitStruct )

Fills each DAC_InitStruct member with its default value.

Parameters:
DAC_InitStruct : pointer to a DAC_InitTypeDef structure which will be initialized.
Return values:
None

Definition at line 150 of file stm32f10x_dac.c.

References DAC_LFSRUnmask_Bit0, DAC_InitTypeDef::DAC_LFSRUnmask_TriangleAmplitude, DAC_InitTypeDef::DAC_OutputBuffer, DAC_OutputBuffer_Enable, DAC_InitTypeDef::DAC_Trigger, DAC_Trigger_None, DAC_InitTypeDef::DAC_WaveGeneration, and DAC_WaveGeneration_None.

void DAC_WaveGenerationCmd | ( | uint32_t | DAC_Channel,
 |  | uint32_t | DAC_Wave,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the selected DAC channel wave generation.

Parameters:
DAC_Channel,: the selected DAC channel. This parameter can be one of the following values:

  • DAC_Channel_1: DAC Channel1 selected
  • DAC_Channel_2: DAC Channel2 selected
DAC_Wave,: Specifies the wave type to enable or disable. This parameter can be one of the following values:

  • DAC_Wave_Noise: noise wave generation
  • DAC_Wave_Triangle: triangle wave generation
NewState,: new state of the selected DAC channel wave generation. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 314 of file stm32f10x_dac.c.

References assert_param, DAC, DISABLE, IS_DAC_CHANNEL, IS_DAC_WAVE, and IS_FUNCTIONAL_STATE.


STM32F10x Standard Peripherals Firmware Library: DBGMCU_Exported_Types

DBGMCU_Exported_Types

DBGMCU


STM32F10x Standard Peripherals Firmware Library: DBGMCU_Exported_Constants

Defines

DBGMCU_Exported_Constants

DBGMCU

Defines

#define | DBGMCU_CAN1_STOP ((uint32_t)0x00004000)
#define | DBGMCU_CAN2_STOP ((uint32_t)0x00200000)
#define | DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000)
#define | DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000)
#define | DBGMCU_IWDG_STOP ((uint32_t)0x00000100)
#define | DBGMCU_SLEEP ((uint32_t)0x00000001)
#define | DBGMCU_STANDBY ((uint32_t)0x00000004)
#define | DBGMCU_STOP ((uint32_t)0x00000002)
#define | DBGMCU_TIM10_STOP ((uint32_t)0x20000000)
#define | DBGMCU_TIM11_STOP ((uint32_t)0x40000000)
#define | DBGMCU_TIM12_STOP ((uint32_t)0x02000000)
#define | DBGMCU_TIM13_STOP ((uint32_t)0x04000000)
#define | DBGMCU_TIM14_STOP ((uint32_t)0x08000000)
#define | DBGMCU_TIM15_STOP ((uint32_t)0x00400000)
#define | DBGMCU_TIM16_STOP ((uint32_t)0x00800000)
#define | DBGMCU_TIM17_STOP ((uint32_t)0x01000000)
#define | DBGMCU_TIM1_STOP ((uint32_t)0x00000400)
#define | DBGMCU_TIM2_STOP ((uint32_t)0x00000800)
#define | DBGMCU_TIM3_STOP ((uint32_t)0x00001000)
#define | DBGMCU_TIM4_STOP ((uint32_t)0x00002000)
#define | DBGMCU_TIM5_STOP ((uint32_t)0x00040000)
#define | DBGMCU_TIM6_STOP ((uint32_t)0x00080000)
#define | DBGMCU_TIM7_STOP ((uint32_t)0x00100000)
#define | DBGMCU_TIM8_STOP ((uint32_t)0x00020000)
#define | DBGMCU_TIM9_STOP ((uint32_t)0x10000000)
#define | DBGMCU_WWDG_STOP ((uint32_t)0x00000200)
#define | IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0x800000F8) == 0x00) && ((PERIPH) != 0x00))

Define Documentation

#define DBGMCU_CAN1_STOP ((uint32_t)0x00004000)

Definition at line 63 of file stm32f10x_dbgmcu.h.

#define DBGMCU_CAN2_STOP ((uint32_t)0x00200000)

Definition at line 70 of file stm32f10x_dbgmcu.h.

#define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000)

Definition at line 64 of file stm32f10x_dbgmcu.h.

#define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000)

Definition at line 65 of file stm32f10x_dbgmcu.h.

#define DBGMCU_IWDG_STOP ((uint32_t)0x00000100)

Definition at line 57 of file stm32f10x_dbgmcu.h.

#define DBGMCU_SLEEP ((uint32_t)0x00000001)

Definition at line 54 of file stm32f10x_dbgmcu.h.

#define DBGMCU_STANDBY ((uint32_t)0x00000004)

Definition at line 56 of file stm32f10x_dbgmcu.h.

#define DBGMCU_STOP ((uint32_t)0x00000002)

Definition at line 55 of file stm32f10x_dbgmcu.h.

#define DBGMCU_TIM10_STOP ((uint32_t)0x20000000)

Definition at line 78 of file stm32f10x_dbgmcu.h.

#define DBGMCU_TIM11_STOP ((uint32_t)0x40000000)

Definition at line 79 of file stm32f10x_dbgmcu.h.

#define DBGMCU_TIM12_STOP ((uint32_t)0x02000000)

Definition at line 74 of file stm32f10x_dbgmcu.h.

#define DBGMCU_TIM13_STOP ((uint32_t)0x04000000)

Definition at line 75 of file stm32f10x_dbgmcu.h.

#define DBGMCU_TIM14_STOP ((uint32_t)0x08000000)

Definition at line 76 of file stm32f10x_dbgmcu.h.

#define DBGMCU_TIM15_STOP ((uint32_t)0x00400000)

Definition at line 71 of file stm32f10x_dbgmcu.h.

#define DBGMCU_TIM16_STOP ((uint32_t)0x00800000)

Definition at line 72 of file stm32f10x_dbgmcu.h.

#define DBGMCU_TIM17_STOP ((uint32_t)0x01000000)

Definition at line 73 of file stm32f10x_dbgmcu.h.

#define DBGMCU_TIM1_STOP ((uint32_t)0x00000400)

Definition at line 59 of file stm32f10x_dbgmcu.h.

#define DBGMCU_TIM2_STOP ((uint32_t)0x00000800)

Definition at line 60 of file stm32f10x_dbgmcu.h.

#define DBGMCU_TIM3_STOP ((uint32_t)0x00001000)

Definition at line 61 of file stm32f10x_dbgmcu.h.

#define DBGMCU_TIM4_STOP ((uint32_t)0x00002000)

Definition at line 62 of file stm32f10x_dbgmcu.h.

#define DBGMCU_TIM5_STOP ((uint32_t)0x00040000)

Definition at line 67 of file stm32f10x_dbgmcu.h.

#define DBGMCU_TIM6_STOP ((uint32_t)0x00080000)

Definition at line 68 of file stm32f10x_dbgmcu.h.

#define DBGMCU_TIM7_STOP ((uint32_t)0x00100000)

Definition at line 69 of file stm32f10x_dbgmcu.h.

#define DBGMCU_TIM8_STOP ((uint32_t)0x00020000)

Definition at line 66 of file stm32f10x_dbgmcu.h.

#define DBGMCU_TIM9_STOP ((uint32_t)0x10000000)

Definition at line 77 of file stm32f10x_dbgmcu.h.

#define DBGMCU_WWDG_STOP ((uint32_t)0x00000200)

Definition at line 58 of file stm32f10x_dbgmcu.h.

#define IS_DBGMCU_PERIPH ( PERIPH ) ((((PERIPH) & 0x800000F8) == 0x00) && ((PERIPH) != 0x00))

Definition at line 81 of file stm32f10x_dbgmcu.h.

Referenced by DBGMCU_Config().


STM32F10x Standard Peripherals Firmware Library: DBGMCU_Exported_Macros

DBGMCU_Exported_Macros

DBGMCU


STM32F10x Standard Peripherals Firmware Library: DBGMCU_Exported_Functions

Functions

DBGMCU_Exported_Functions

DBGMCU

Functions

void | DBGMCU_Config (uint32_t DBGMCU_Periph, FunctionalState NewState)
Configures the specified peripheral and low power mode behavior when the MCU under Debug mode.
uint32_t | DBGMCU_GetDEVID (void)
Returns the device identifier.
uint32_t | DBGMCU_GetREVID (void)
Returns the device revision identifier.

Function Documentation

void DBGMCU_Config | ( | uint32_t | DBGMCU_Periph,
 |  | FunctionalState | NewState
 | ) |  |

Configures the specified peripheral and low power mode behavior when the MCU under Debug mode.

Parameters:
DBGMCU_Periph,: specifies the peripheral and low power mode. This parameter can be any combination of the following values:

  • DBGMCU_SLEEP: Keep debugger connection during SLEEP mode
  • DBGMCU_STOP: Keep debugger connection during STOP mode
  • DBGMCU_STANDBY: Keep debugger connection during STANDBY mode
  • DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted
  • DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted
  • DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted
  • DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted
  • DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted
  • DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted
  • DBGMCU_CAN1_STOP: Debug CAN2 stopped when Core is halted
  • DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is halted
  • DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is halted
  • DBGMCU_TIM5_STOP: TIM5 counter stopped when Core is halted
  • DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted
  • DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted
  • DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted
  • DBGMCU_CAN2_STOP: Debug CAN2 stopped when Core is halted
  • DBGMCU_TIM15_STOP: TIM15 counter stopped when Core is halted
  • DBGMCU_TIM16_STOP: TIM16 counter stopped when Core is halted
  • DBGMCU_TIM17_STOP: TIM17 counter stopped when Core is halted
  • DBGMCU_TIM9_STOP: TIM9 counter stopped when Core is halted
  • DBGMCU_TIM10_STOP: TIM10 counter stopped when Core is halted
  • DBGMCU_TIM11_STOP: TIM11 counter stopped when Core is halted
  • DBGMCU_TIM12_STOP: TIM12 counter stopped when Core is halted
  • DBGMCU_TIM13_STOP: TIM13 counter stopped when Core is halted
  • DBGMCU_TIM14_STOP: TIM14 counter stopped when Core is halted
NewState,: new state of the specified peripheral in Debug mode. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 134 of file stm32f10x_dbgmcu.c.

References assert_param, DBGMCU, DISABLE, IS_DBGMCU_PERIPH, and IS_FUNCTIONAL_STATE.

uint32_t DBGMCU_GetDEVID ( void )

Returns the device identifier.

Parameters:
None
Return values:
Device identifier

Definition at line 94 of file stm32f10x_dbgmcu.c.

References DBGMCU, and IDCODE_DEVID_MASK.

uint32_t DBGMCU_GetREVID ( void )

Returns the device revision identifier.

Parameters:
None
Return values:
Device revision identifier

Definition at line 84 of file stm32f10x_dbgmcu.c.

References DBGMCU.


STM32F10x Standard Peripherals Firmware Library: DBGMCU_Private_TypesDefinitions

DBGMCU_Private_TypesDefinitions

DBGMCU


STM32F10x Standard Peripherals Firmware Library: DBGMCU_Private_Defines

Defines

DBGMCU_Private_Defines

DBGMCU

Defines

#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)

Define Documentation

#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)

Definition at line 46 of file stm32f10x_dbgmcu.c.

Referenced by DBGMCU_GetDEVID().


STM32F10x Standard Peripherals Firmware Library: DBGMCU_Private_Macros

DBGMCU_Private_Macros

DBGMCU


STM32F10x Standard Peripherals Firmware Library: DBGMCU_Private_Variables

DBGMCU_Private_Variables

DBGMCU


STM32F10x Standard Peripherals Firmware Library: DBGMCU_Private_FunctionPrototypes

DBGMCU_Private_FunctionPrototypes

DBGMCU


STM32F10x Standard Peripherals Firmware Library: DBGMCU_Private_Functions

Functions

DBGMCU_Private_Functions

DBGMCU

Functions

void | DBGMCU_Config (uint32_t DBGMCU_Periph, FunctionalState NewState)
Configures the specified peripheral and low power mode behavior when the MCU under Debug mode.
uint32_t | DBGMCU_GetDEVID (void)
Returns the device identifier.
uint32_t | DBGMCU_GetREVID (void)
Returns the device revision identifier.

Function Documentation

void DBGMCU_Config | ( | uint32_t | DBGMCU_Periph,
 |  | FunctionalState | NewState
 | ) |  |

Configures the specified peripheral and low power mode behavior when the MCU under Debug mode.

Parameters:
DBGMCU_Periph,: specifies the peripheral and low power mode. This parameter can be any combination of the following values:

  • DBGMCU_SLEEP: Keep debugger connection during SLEEP mode
  • DBGMCU_STOP: Keep debugger connection during STOP mode
  • DBGMCU_STANDBY: Keep debugger connection during STANDBY mode
  • DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted
  • DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted
  • DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted
  • DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted
  • DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted
  • DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted
  • DBGMCU_CAN1_STOP: Debug CAN2 stopped when Core is halted
  • DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is halted
  • DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is halted
  • DBGMCU_TIM5_STOP: TIM5 counter stopped when Core is halted
  • DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted
  • DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted
  • DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted
  • DBGMCU_CAN2_STOP: Debug CAN2 stopped when Core is halted
  • DBGMCU_TIM15_STOP: TIM15 counter stopped when Core is halted
  • DBGMCU_TIM16_STOP: TIM16 counter stopped when Core is halted
  • DBGMCU_TIM17_STOP: TIM17 counter stopped when Core is halted
  • DBGMCU_TIM9_STOP: TIM9 counter stopped when Core is halted
  • DBGMCU_TIM10_STOP: TIM10 counter stopped when Core is halted
  • DBGMCU_TIM11_STOP: TIM11 counter stopped when Core is halted
  • DBGMCU_TIM12_STOP: TIM12 counter stopped when Core is halted
  • DBGMCU_TIM13_STOP: TIM13 counter stopped when Core is halted
  • DBGMCU_TIM14_STOP: TIM14 counter stopped when Core is halted
NewState,: new state of the specified peripheral in Debug mode. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 134 of file stm32f10x_dbgmcu.c.

References assert_param, DBGMCU, DISABLE, IS_DBGMCU_PERIPH, and IS_FUNCTIONAL_STATE.

uint32_t DBGMCU_GetDEVID ( void )

Returns the device identifier.

Parameters:
None
Return values:
Device identifier

Definition at line 94 of file stm32f10x_dbgmcu.c.

References DBGMCU, and IDCODE_DEVID_MASK.

uint32_t DBGMCU_GetREVID ( void )

Returns the device revision identifier.

Parameters:
None
Return values:
Device revision identifier

Definition at line 84 of file stm32f10x_dbgmcu.c.

References DBGMCU.


STM32F10x Standard Peripherals Firmware Library: DMA_InitTypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

DMA_InitTypeDef Struct Reference
DMA_Exported_Types

DMA Init structure definition. More...

#include <stm32f10x_dma.h>

Data Fields

uint32_t | DMA_BufferSize
uint32_t | DMA_DIR
uint32_t | DMA_M2M
uint32_t | DMA_MemoryBaseAddr
uint32_t | DMA_MemoryDataSize
uint32_t | DMA_MemoryInc
uint32_t | DMA_Mode
uint32_t | DMA_PeripheralBaseAddr
uint32_t | DMA_PeripheralDataSize
uint32_t | DMA_PeripheralInc
uint32_t | DMA_Priority

Detailed Description

DMA Init structure definition.

Definition at line 50 of file stm32f10x_dma.h.

Field Documentation

uint32_t DMA_InitTypeDef::DMA_BufferSize

Specifies the buffer size, in data unit, of the specified Channel. The data unit is equal to the configuration set in DMA_PeripheralDataSize or DMA_MemoryDataSize members depending in the transfer direction.

Definition at line 59 of file stm32f10x_dma.h.

Referenced by DMA_Configuration(), DMA_Init(), DMA_StructInit(), IOE_DMA_Config(), LM75_DMA_Config(), main(), SD_LowLevel_DMA_RxConfig(), SD_LowLevel_DMA_TxConfig(), sEE_LowLevel_DMAConfig(), and sEE_LowLevel_Init().

uint32_t DMA_InitTypeDef::DMA_DIR

Specifies if the peripheral is the source or destination. This parameter can be a value of DMA_data_transfer_direction

Definition at line 56 of file stm32f10x_dma.h.

Referenced by DMA_Configuration(), DMA_Init(), DMA_StructInit(), IOE_DMA_Config(), LM75_DMA_Config(), main(), SD_LowLevel_DMA_RxConfig(), SD_LowLevel_DMA_TxConfig(), sEE_LowLevel_DMAConfig(), and sEE_LowLevel_Init().

uint32_t DMA_InitTypeDef::DMA_M2M

Specifies if the DMAy Channelx will be used in memory-to-memory transfer. This parameter can be a value of DMA_memory_to_memory

Definition at line 83 of file stm32f10x_dma.h.

Referenced by DMA_Configuration(), DMA_Init(), DMA_StructInit(), IOE_DMA_Config(), LM75_DMA_Config(), main(), SD_LowLevel_DMA_RxConfig(), SD_LowLevel_DMA_TxConfig(), and sEE_LowLevel_Init().

uint32_t DMA_InitTypeDef::DMA_MemoryBaseAddr

Specifies the memory base address for DMAy Channelx.

Definition at line 54 of file stm32f10x_dma.h.

Referenced by DMA_Configuration(), DMA_Init(), DMA_StructInit(), IOE_DMA_Config(), LM75_DMA_Config(), main(), SD_LowLevel_DMA_RxConfig(), SD_LowLevel_DMA_TxConfig(), sEE_LowLevel_DMAConfig(), and sEE_LowLevel_Init().

uint32_t DMA_InitTypeDef::DMA_MemoryDataSize

Specifies the Memory data width. This parameter can be a value of DMA_memory_data_size

Definition at line 72 of file stm32f10x_dma.h.

Referenced by DMA_Configuration(), DMA_Init(), DMA_StructInit(), IOE_DMA_Config(), LM75_DMA_Config(), main(), SD_LowLevel_DMA_RxConfig(), SD_LowLevel_DMA_TxConfig(), and sEE_LowLevel_Init().

uint32_t DMA_InitTypeDef::DMA_MemoryInc

Specifies whether the memory address register is incremented or not. This parameter can be a value of DMA_memory_incremented_mode

Definition at line 66 of file stm32f10x_dma.h.

Referenced by DMA_Configuration(), DMA_Init(), DMA_StructInit(), IOE_DMA_Config(), LM75_DMA_Config(), main(), SD_LowLevel_DMA_RxConfig(), SD_LowLevel_DMA_TxConfig(), and sEE_LowLevel_Init().

uint32_t DMA_InitTypeDef::DMA_Mode

Specifies the operation mode of the DMAy Channelx. This parameter can be a value of DMA_circular_normal_mode.

Note:
: The circular buffer mode cannot be used if the memory-to-memory data transfer is configured on the selected Channel

Definition at line 75 of file stm32f10x_dma.h.

Referenced by DMA_Configuration(), DMA_Init(), DMA_StructInit(), IOE_DMA_Config(), LM75_DMA_Config(), main(), SD_LowLevel_DMA_RxConfig(), SD_LowLevel_DMA_TxConfig(), and sEE_LowLevel_Init().

uint32_t DMA_InitTypeDef::DMA_PeripheralBaseAddr

Specifies the peripheral base address for DMAy Channelx.

Definition at line 52 of file stm32f10x_dma.h.

Referenced by DMA_Configuration(), DMA_Init(), DMA_StructInit(), IOE_DMA_Config(), LM75_DMA_Config(), main(), SD_LowLevel_DMA_RxConfig(), SD_LowLevel_DMA_TxConfig(), and sEE_LowLevel_Init().

uint32_t DMA_InitTypeDef::DMA_PeripheralDataSize

Specifies the Peripheral data width. This parameter can be a value of DMA_peripheral_data_size

Definition at line 69 of file stm32f10x_dma.h.

Referenced by DMA_Configuration(), DMA_Init(), DMA_StructInit(), IOE_DMA_Config(), LM75_DMA_Config(), main(), SD_LowLevel_DMA_RxConfig(), SD_LowLevel_DMA_TxConfig(), and sEE_LowLevel_Init().

uint32_t DMA_InitTypeDef::DMA_PeripheralInc

Specifies whether the Peripheral address register is incremented or not. This parameter can be a value of DMA_peripheral_incremented_mode

Definition at line 63 of file stm32f10x_dma.h.

Referenced by DMA_Configuration(), DMA_Init(), DMA_StructInit(), IOE_DMA_Config(), LM75_DMA_Config(), main(), SD_LowLevel_DMA_RxConfig(), SD_LowLevel_DMA_TxConfig(), and sEE_LowLevel_Init().

uint32_t DMA_InitTypeDef::DMA_Priority

Specifies the software priority for the DMAy Channelx. This parameter can be a value of DMA_priority_level

Definition at line 80 of file stm32f10x_dma.h.

Referenced by DMA_Configuration(), DMA_Init(), DMA_StructInit(), IOE_DMA_Config(), LM75_DMA_Config(), main(), SD_LowLevel_DMA_RxConfig(), SD_LowLevel_DMA_TxConfig(), and sEE_LowLevel_Init().

The documentation for this struct was generated from the following file:
  • stm32f10x_dma.h


STM32F10x Standard Peripherals Firmware Library: DMA_data_transfer_direction

Defines

DMA_data_transfer_direction

DMA_Exported_Constants

Defines

#define | DMA_DIR_PeripheralDST ((uint32_t)0x00000010)
#define | DMA_DIR_PeripheralSRC ((uint32_t)0x00000000)
#define | IS_DMA_DIR(DIR)

Define Documentation

#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010)

Definition at line 112 of file stm32f10x_dma.h.

Referenced by IOE_DMA_Config(), LM75_DMA_Config(), main(), SD_LowLevel_DMA_TxConfig(), sEE_LowLevel_DMAConfig(), and sEE_LowLevel_Init().

#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000)

Definition at line 113 of file stm32f10x_dma.h.

Referenced by DMA_Configuration(), DMA_StructInit(), IOE_DMA_Config(), LM75_DMA_Config(), main(), SD_LowLevel_DMA_RxConfig(), and sEE_LowLevel_DMAConfig().

#define IS_DMA_DIR ( DIR )
Value:
(((DIR) == DMA_DIR_PeripheralDST) || \
                         ((DIR) == DMA_DIR_PeripheralSRC))

Definition at line 114 of file stm32f10x_dma.h.

Referenced by DMA_Init().


STM32F10x Standard Peripherals Firmware Library: DMA_peripheral_incremented_mode

Defines

DMA_peripheral_incremented_mode

DMA_Exported_Constants

Defines

#define | DMA_PeripheralInc_Disable ((uint32_t)0x00000000)
#define | DMA_PeripheralInc_Enable ((uint32_t)0x00000040)
#define | IS_DMA_PERIPHERAL_INC_STATE(STATE)

Define Documentation

#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000)

Definition at line 125 of file stm32f10x_dma.h.

Referenced by DMA_Configuration(), DMA_StructInit(), IOE_DMA_Config(), LM75_DMA_Config(), main(), SD_LowLevel_DMA_RxConfig(), SD_LowLevel_DMA_TxConfig(), and sEE_LowLevel_Init().

#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040)

Definition at line 124 of file stm32f10x_dma.h.

Referenced by main().

#define IS_DMA_PERIPHERAL_INC_STATE ( STATE )
Value:
(((STATE) == DMA_PeripheralInc_Enable) || \
                                            ((STATE) == DMA_PeripheralInc_Disable))

Definition at line 126 of file stm32f10x_dma.h.

Referenced by DMA_Init().


STM32F10x Standard Peripherals Firmware Library: DMA_memory_incremented_mode

Defines

DMA_memory_incremented_mode

DMA_Exported_Constants

Defines

#define | DMA_MemoryInc_Disable ((uint32_t)0x00000000)
#define | DMA_MemoryInc_Enable ((uint32_t)0x00000080)
#define | IS_DMA_MEMORY_INC_STATE(STATE)

Define Documentation

#define DMA_MemoryInc_Disable ((uint32_t)0x00000000)

Definition at line 137 of file stm32f10x_dma.h.

Referenced by DMA_StructInit(), and main().

#define DMA_MemoryInc_Enable ((uint32_t)0x00000080)

Definition at line 136 of file stm32f10x_dma.h.

Referenced by DMA_Configuration(), IOE_DMA_Config(), LM75_DMA_Config(), main(), SD_LowLevel_DMA_RxConfig(), SD_LowLevel_DMA_TxConfig(), and sEE_LowLevel_Init().

#define IS_DMA_MEMORY_INC_STATE ( STATE )
Value:
(((STATE) == DMA_MemoryInc_Enable) || \
                                        ((STATE) == DMA_MemoryInc_Disable))

Definition at line 138 of file stm32f10x_dma.h.

Referenced by DMA_Init().


STM32F10x Standard Peripherals Firmware Library: DMA_peripheral_data_size

Defines

DMA_peripheral_data_size

DMA_Exported_Constants

Defines

#define | DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000)
#define | DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100)
#define | DMA_PeripheralDataSize_Word ((uint32_t)0x00000200)
#define | IS_DMA_PERIPHERAL_DATA_SIZE(SIZE)

Define Documentation

#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000)

Definition at line 148 of file stm32f10x_dma.h.

Referenced by DMA_StructInit(), IOE_DMA_Config(), LM75_DMA_Config(), and main().

#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100)

Definition at line 149 of file stm32f10x_dma.h.

Referenced by DMA_Configuration(), and main().

#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200)

Definition at line 150 of file stm32f10x_dma.h.

Referenced by main(), SD_LowLevel_DMA_RxConfig(), and SD_LowLevel_DMA_TxConfig().

#define IS_DMA_PERIPHERAL_DATA_SIZE ( SIZE )
Value:
(((SIZE) == DMA_PeripheralDataSize_Byte) || \
                                           ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \
                                           ((SIZE) == DMA_PeripheralDataSize_Word))

Definition at line 151 of file stm32f10x_dma.h.

Referenced by DMA_Init().


STM32F10x Standard Peripherals Firmware Library: DMA_memory_data_size

Defines

DMA_memory_data_size

DMA_Exported_Constants

Defines

#define | DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)
#define | DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400)
#define | DMA_MemoryDataSize_Word ((uint32_t)0x00000800)
#define | IS_DMA_MEMORY_DATA_SIZE(SIZE)

Define Documentation

#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)

Definition at line 162 of file stm32f10x_dma.h.

Referenced by DMA_StructInit(), IOE_DMA_Config(), LM75_DMA_Config(), main(), and sEE_LowLevel_Init().

#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400)

Definition at line 163 of file stm32f10x_dma.h.

Referenced by DMA_Configuration(), and main().

#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800)

Definition at line 164 of file stm32f10x_dma.h.

Referenced by main(), SD_LowLevel_DMA_RxConfig(), and SD_LowLevel_DMA_TxConfig().

#define IS_DMA_MEMORY_DATA_SIZE ( SIZE )
Value:
(((SIZE) == DMA_MemoryDataSize_Byte) || \
                                       ((SIZE) == DMA_MemoryDataSize_HalfWord) || \
                                       ((SIZE) == DMA_MemoryDataSize_Word))

Definition at line 165 of file stm32f10x_dma.h.

Referenced by DMA_Init().


STM32F10x Standard Peripherals Firmware Library: DMA_circular_normal_mode

Defines

DMA_circular_normal_mode

DMA_Exported_Constants

Defines

#define | DMA_Mode_Circular ((uint32_t)0x00000020)
#define | DMA_Mode_Normal ((uint32_t)0x00000000)
#define | IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Circular) || ((MODE) == DMA_Mode_Normal))

Define Documentation

#define DMA_Mode_Circular ((uint32_t)0x00000020)

Definition at line 176 of file stm32f10x_dma.h.

Referenced by DMA_Configuration(), and main().

#define DMA_Mode_Normal ((uint32_t)0x00000000)

Definition at line 177 of file stm32f10x_dma.h.

Referenced by DMA_StructInit(), IOE_DMA_Config(), LM75_DMA_Config(), main(), SD_LowLevel_DMA_RxConfig(), SD_LowLevel_DMA_TxConfig(), and sEE_LowLevel_Init().

#define IS_DMA_MODE ( MODE ) (((MODE) == DMA_Mode_Circular) || ((MODE) == DMA_Mode_Normal))

Definition at line 178 of file stm32f10x_dma.h.

Referenced by DMA_Init().


STM32F10x Standard Peripherals Firmware Library: DMA_priority_level

Defines

DMA_priority_level

DMA_Exported_Constants

Defines

#define | DMA_Priority_High ((uint32_t)0x00002000)
#define | DMA_Priority_Low ((uint32_t)0x00000000)
#define | DMA_Priority_Medium ((uint32_t)0x00001000)
#define | DMA_Priority_VeryHigh ((uint32_t)0x00003000)
#define | IS_DMA_PRIORITY(PRIORITY)

Define Documentation

#define DMA_Priority_High ((uint32_t)0x00002000)

Definition at line 188 of file stm32f10x_dma.h.

Referenced by DMA_Configuration(), main(), SD_LowLevel_DMA_RxConfig(), and SD_LowLevel_DMA_TxConfig().

#define DMA_Priority_Low ((uint32_t)0x00000000)

Definition at line 190 of file stm32f10x_dma.h.

Referenced by DMA_StructInit(), and main().

#define DMA_Priority_Medium ((uint32_t)0x00001000)

Definition at line 189 of file stm32f10x_dma.h.

Referenced by main().

#define DMA_Priority_VeryHigh ((uint32_t)0x00003000)

Definition at line 187 of file stm32f10x_dma.h.

Referenced by IOE_DMA_Config(), LM75_DMA_Config(), main(), and sEE_LowLevel_Init().

#define IS_DMA_PRIORITY ( PRIORITY )
Value:
(((PRIORITY) == DMA_Priority_VeryHigh) || \
                                   ((PRIORITY) == DMA_Priority_High) || \
                                   ((PRIORITY) == DMA_Priority_Medium) || \
                                   ((PRIORITY) == DMA_Priority_Low))

Definition at line 191 of file stm32f10x_dma.h.

Referenced by DMA_Init().


STM32F10x Standard Peripherals Firmware Library: DMA_memory_to_memory

Defines

DMA_memory_to_memory

DMA_Exported_Constants

Defines

#define | DMA_M2M_Disable ((uint32_t)0x00000000)
#define | DMA_M2M_Enable ((uint32_t)0x00004000)
#define | IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Enable) || ((STATE) == DMA_M2M_Disable))

Define Documentation

#define DMA_M2M_Disable ((uint32_t)0x00000000)

Definition at line 204 of file stm32f10x_dma.h.

Referenced by DMA_Configuration(), DMA_StructInit(), IOE_DMA_Config(), LM75_DMA_Config(), main(), SD_LowLevel_DMA_RxConfig(), SD_LowLevel_DMA_TxConfig(), and sEE_LowLevel_Init().

#define DMA_M2M_Enable ((uint32_t)0x00004000)

Definition at line 203 of file stm32f10x_dma.h.

Referenced by main().

#define IS_DMA_M2M_STATE ( STATE ) (((STATE) == DMA_M2M_Enable) || ((STATE) == DMA_M2M_Disable))

Definition at line 205 of file stm32f10x_dma.h.

Referenced by DMA_Init().


STM32F10x Standard Peripherals Firmware Library: DMA_interrupts_definition

Defines

DMA_interrupts_definition

DMA_Exported_Constants

Defines

#define | DMA1_IT_GL1 ((uint32_t)0x00000001)
#define | DMA1_IT_GL2 ((uint32_t)0x00000010)
#define | DMA1_IT_GL3 ((uint32_t)0x00000100)
#define | DMA1_IT_GL4 ((uint32_t)0x00001000)
#define | DMA1_IT_GL5 ((uint32_t)0x00010000)
#define | DMA1_IT_GL6 ((uint32_t)0x00100000)
#define | DMA1_IT_GL7 ((uint32_t)0x01000000)
#define | DMA1_IT_HT1 ((uint32_t)0x00000004)
#define | DMA1_IT_HT2 ((uint32_t)0x00000040)
#define | DMA1_IT_HT3 ((uint32_t)0x00000400)
#define | DMA1_IT_HT4 ((uint32_t)0x00004000)
#define | DMA1_IT_HT5 ((uint32_t)0x00040000)
#define | DMA1_IT_HT6 ((uint32_t)0x00400000)
#define | DMA1_IT_HT7 ((uint32_t)0x04000000)
#define | DMA1_IT_TC1 ((uint32_t)0x00000002)
#define | DMA1_IT_TC2 ((uint32_t)0x00000020)
#define | DMA1_IT_TC3 ((uint32_t)0x00000200)
#define | DMA1_IT_TC4 ((uint32_t)0x00002000)
#define | DMA1_IT_TC5 ((uint32_t)0x00020000)
#define | DMA1_IT_TC6 ((uint32_t)0x00200000)
#define | DMA1_IT_TC7 ((uint32_t)0x02000000)
#define | DMA1_IT_TE1 ((uint32_t)0x00000008)
#define | DMA1_IT_TE2 ((uint32_t)0x00000080)
#define | DMA1_IT_TE3 ((uint32_t)0x00000800)
#define | DMA1_IT_TE4 ((uint32_t)0x00008000)
#define | DMA1_IT_TE5 ((uint32_t)0x00080000)
#define | DMA1_IT_TE6 ((uint32_t)0x00800000)
#define | DMA1_IT_TE7 ((uint32_t)0x08000000)
#define | DMA2_IT_GL1 ((uint32_t)0x10000001)
#define | DMA2_IT_GL2 ((uint32_t)0x10000010)
#define | DMA2_IT_GL3 ((uint32_t)0x10000100)
#define | DMA2_IT_GL4 ((uint32_t)0x10001000)
#define | DMA2_IT_GL5 ((uint32_t)0x10010000)
#define | DMA2_IT_HT1 ((uint32_t)0x10000004)
#define | DMA2_IT_HT2 ((uint32_t)0x10000040)
#define | DMA2_IT_HT3 ((uint32_t)0x10000400)
#define | DMA2_IT_HT4 ((uint32_t)0x10004000)
#define | DMA2_IT_HT5 ((uint32_t)0x10040000)
#define | DMA2_IT_TC1 ((uint32_t)0x10000002)
#define | DMA2_IT_TC2 ((uint32_t)0x10000020)
#define | DMA2_IT_TC3 ((uint32_t)0x10000200)
#define | DMA2_IT_TC4 ((uint32_t)0x10002000)
#define | DMA2_IT_TC5 ((uint32_t)0x10020000)
#define | DMA2_IT_TE1 ((uint32_t)0x10000008)
#define | DMA2_IT_TE2 ((uint32_t)0x10000080)
#define | DMA2_IT_TE3 ((uint32_t)0x10000800)
#define | DMA2_IT_TE4 ((uint32_t)0x10008000)
#define | DMA2_IT_TE5 ((uint32_t)0x10080000)
#define | DMA_IT_HT ((uint32_t)0x00000004)
#define | DMA_IT_TC ((uint32_t)0x00000002)
#define | DMA_IT_TE ((uint32_t)0x00000008)
#define | IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00))
#define | IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00))
#define | IS_DMA_GET_IT(IT)

Define Documentation

#define DMA1_IT_GL1 ((uint32_t)0x00000001)

Definition at line 220 of file stm32f10x_dma.h.

#define DMA1_IT_GL2 ((uint32_t)0x00000010)

Definition at line 224 of file stm32f10x_dma.h.

#define DMA1_IT_GL3 ((uint32_t)0x00000100)

Definition at line 228 of file stm32f10x_dma.h.

#define DMA1_IT_GL4 ((uint32_t)0x00001000)

Definition at line 232 of file stm32f10x_dma.h.

#define DMA1_IT_GL5 ((uint32_t)0x00010000)

Definition at line 236 of file stm32f10x_dma.h.

Referenced by DMA1_Channel5_IRQHandler().

#define DMA1_IT_GL6 ((uint32_t)0x00100000)

Definition at line 240 of file stm32f10x_dma.h.

Referenced by DMA1_Channel6_IRQHandler().

#define DMA1_IT_GL7 ((uint32_t)0x01000000)

Definition at line 244 of file stm32f10x_dma.h.

#define DMA1_IT_HT1 ((uint32_t)0x00000004)

Definition at line 222 of file stm32f10x_dma.h.

#define DMA1_IT_HT2 ((uint32_t)0x00000040)

Definition at line 226 of file stm32f10x_dma.h.

#define DMA1_IT_HT3 ((uint32_t)0x00000400)

Definition at line 230 of file stm32f10x_dma.h.

#define DMA1_IT_HT4 ((uint32_t)0x00004000)

Definition at line 234 of file stm32f10x_dma.h.

#define DMA1_IT_HT5 ((uint32_t)0x00040000)

Definition at line 238 of file stm32f10x_dma.h.

#define DMA1_IT_HT6 ((uint32_t)0x00400000)

Definition at line 242 of file stm32f10x_dma.h.

#define DMA1_IT_HT7 ((uint32_t)0x04000000)

Definition at line 246 of file stm32f10x_dma.h.

#define DMA1_IT_TC1 ((uint32_t)0x00000002)

Definition at line 221 of file stm32f10x_dma.h.

#define DMA1_IT_TC2 ((uint32_t)0x00000020)

Definition at line 225 of file stm32f10x_dma.h.

#define DMA1_IT_TC3 ((uint32_t)0x00000200)

Definition at line 229 of file stm32f10x_dma.h.

#define DMA1_IT_TC4 ((uint32_t)0x00002000)

Definition at line 233 of file stm32f10x_dma.h.

#define DMA1_IT_TC5 ((uint32_t)0x00020000)

Definition at line 237 of file stm32f10x_dma.h.

Referenced by DMA1_Channel5_IRQHandler().

#define DMA1_IT_TC6 ((uint32_t)0x00200000)

Definition at line 241 of file stm32f10x_dma.h.

Referenced by DMA1_Channel6_IRQHandler().

#define DMA1_IT_TC7 ((uint32_t)0x02000000)

Definition at line 245 of file stm32f10x_dma.h.

#define DMA1_IT_TE1 ((uint32_t)0x00000008)

Definition at line 223 of file stm32f10x_dma.h.

#define DMA1_IT_TE2 ((uint32_t)0x00000080)

Definition at line 227 of file stm32f10x_dma.h.

#define DMA1_IT_TE3 ((uint32_t)0x00000800)

Definition at line 231 of file stm32f10x_dma.h.

#define DMA1_IT_TE4 ((uint32_t)0x00008000)

Definition at line 235 of file stm32f10x_dma.h.

#define DMA1_IT_TE5 ((uint32_t)0x00080000)

Definition at line 239 of file stm32f10x_dma.h.

#define DMA1_IT_TE6 ((uint32_t)0x00800000)

Definition at line 243 of file stm32f10x_dma.h.

#define DMA1_IT_TE7 ((uint32_t)0x08000000)

Definition at line 247 of file stm32f10x_dma.h.

#define DMA2_IT_GL1 ((uint32_t)0x10000001)

Definition at line 249 of file stm32f10x_dma.h.

#define DMA2_IT_GL2 ((uint32_t)0x10000010)

Definition at line 253 of file stm32f10x_dma.h.

#define DMA2_IT_GL3 ((uint32_t)0x10000100)

Definition at line 257 of file stm32f10x_dma.h.

#define DMA2_IT_GL4 ((uint32_t)0x10001000)

Definition at line 261 of file stm32f10x_dma.h.

#define DMA2_IT_GL5 ((uint32_t)0x10010000)

Definition at line 265 of file stm32f10x_dma.h.

#define DMA2_IT_HT1 ((uint32_t)0x10000004)

Definition at line 251 of file stm32f10x_dma.h.

#define DMA2_IT_HT2 ((uint32_t)0x10000040)

Definition at line 255 of file stm32f10x_dma.h.

#define DMA2_IT_HT3 ((uint32_t)0x10000400)

Definition at line 259 of file stm32f10x_dma.h.

#define DMA2_IT_HT4 ((uint32_t)0x10004000)

Definition at line 263 of file stm32f10x_dma.h.

#define DMA2_IT_HT5 ((uint32_t)0x10040000)

Definition at line 267 of file stm32f10x_dma.h.

#define DMA2_IT_TC1 ((uint32_t)0x10000002)

Definition at line 250 of file stm32f10x_dma.h.

#define DMA2_IT_TC2 ((uint32_t)0x10000020)

Definition at line 254 of file stm32f10x_dma.h.

#define DMA2_IT_TC3 ((uint32_t)0x10000200)

Definition at line 258 of file stm32f10x_dma.h.

#define DMA2_IT_TC4 ((uint32_t)0x10002000)

Definition at line 262 of file stm32f10x_dma.h.

#define DMA2_IT_TC5 ((uint32_t)0x10020000)

Definition at line 266 of file stm32f10x_dma.h.

#define DMA2_IT_TE1 ((uint32_t)0x10000008)

Definition at line 252 of file stm32f10x_dma.h.

#define DMA2_IT_TE2 ((uint32_t)0x10000080)

Definition at line 256 of file stm32f10x_dma.h.

#define DMA2_IT_TE3 ((uint32_t)0x10000800)

Definition at line 260 of file stm32f10x_dma.h.

#define DMA2_IT_TE4 ((uint32_t)0x10008000)

Definition at line 264 of file stm32f10x_dma.h.

#define DMA2_IT_TE5 ((uint32_t)0x10080000)

Definition at line 268 of file stm32f10x_dma.h.

#define DMA_IT_HT ((uint32_t)0x00000004)

Definition at line 216 of file stm32f10x_dma.h.

#define DMA_IT_TC ((uint32_t)0x00000002)

Definition at line 215 of file stm32f10x_dma.h.

Referenced by DMA_Configuration(), main(), and sEE_LowLevel_Init().

#define DMA_IT_TE ((uint32_t)0x00000008)

Definition at line 217 of file stm32f10x_dma.h.

#define IS_DMA_CLEAR_IT ( IT ) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00))

Definition at line 270 of file stm32f10x_dma.h.

Referenced by DMA_ClearITPendingBit().

#define IS_DMA_CONFIG_IT ( IT ) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00))

Definition at line 218 of file stm32f10x_dma.h.

Referenced by DMA_ITConfig().

#define IS_DMA_GET_IT ( IT )
Value:
(((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \
                           ((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \
                           ((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \
                           ((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \
                           ((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \
                           ((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \
                           ((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \
                           ((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \
                           ((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \
                           ((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \
                           ((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \
                           ((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \
                           ((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \
                           ((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7) || \
                           ((IT) == DMA2_IT_GL1) || ((IT) == DMA2_IT_TC1) || \
                           ((IT) == DMA2_IT_HT1) || ((IT) == DMA2_IT_TE1) || \
                           ((IT) == DMA2_IT_GL2) || ((IT) == DMA2_IT_TC2) || \
                           ((IT) == DMA2_IT_HT2) || ((IT) == DMA2_IT_TE2) || \
                           ((IT) == DMA2_IT_GL3) || ((IT) == DMA2_IT_TC3) || \
                           ((IT) == DMA2_IT_HT3) || ((IT) == DMA2_IT_TE3) || \
                           ((IT) == DMA2_IT_GL4) || ((IT) == DMA2_IT_TC4) || \
                           ((IT) == DMA2_IT_HT4) || ((IT) == DMA2_IT_TE4) || \
                           ((IT) == DMA2_IT_GL5) || ((IT) == DMA2_IT_TC5) || \
                           ((IT) == DMA2_IT_HT5) || ((IT) == DMA2_IT_TE5))

Definition at line 272 of file stm32f10x_dma.h.

Referenced by DMA_GetITStatus().


STM32F10x Standard Peripherals Firmware Library: DMA_flags_definition

Defines

DMA_flags_definition

DMA_Exported_Constants

Defines

#define | DMA1_FLAG_GL1 ((uint32_t)0x00000001)
#define | DMA1_FLAG_GL2 ((uint32_t)0x00000010)
#define | DMA1_FLAG_GL3 ((uint32_t)0x00000100)
#define | DMA1_FLAG_GL4 ((uint32_t)0x00001000)
#define | DMA1_FLAG_GL5 ((uint32_t)0x00010000)
#define | DMA1_FLAG_GL6 ((uint32_t)0x00100000)
#define | DMA1_FLAG_GL7 ((uint32_t)0x01000000)
#define | DMA1_FLAG_HT1 ((uint32_t)0x00000004)
#define | DMA1_FLAG_HT2 ((uint32_t)0x00000040)
#define | DMA1_FLAG_HT3 ((uint32_t)0x00000400)
#define | DMA1_FLAG_HT4 ((uint32_t)0x00004000)
#define | DMA1_FLAG_HT5 ((uint32_t)0x00040000)
#define | DMA1_FLAG_HT6 ((uint32_t)0x00400000)
#define | DMA1_FLAG_HT7 ((uint32_t)0x04000000)
#define | DMA1_FLAG_TC1 ((uint32_t)0x00000002)
#define | DMA1_FLAG_TC2 ((uint32_t)0x00000020)
#define | DMA1_FLAG_TC3 ((uint32_t)0x00000200)
#define | DMA1_FLAG_TC4 ((uint32_t)0x00002000)
#define | DMA1_FLAG_TC5 ((uint32_t)0x00020000)
#define | DMA1_FLAG_TC6 ((uint32_t)0x00200000)
#define | DMA1_FLAG_TC7 ((uint32_t)0x02000000)
#define | DMA1_FLAG_TE1 ((uint32_t)0x00000008)
#define | DMA1_FLAG_TE2 ((uint32_t)0x00000080)
#define | DMA1_FLAG_TE3 ((uint32_t)0x00000800)
#define | DMA1_FLAG_TE4 ((uint32_t)0x00008000)
#define | DMA1_FLAG_TE5 ((uint32_t)0x00080000)
#define | DMA1_FLAG_TE6 ((uint32_t)0x00800000)
#define | DMA1_FLAG_TE7 ((uint32_t)0x08000000)
#define | DMA2_FLAG_GL1 ((uint32_t)0x10000001)
#define | DMA2_FLAG_GL2 ((uint32_t)0x10000010)
#define | DMA2_FLAG_GL3 ((uint32_t)0x10000100)
#define | DMA2_FLAG_GL4 ((uint32_t)0x10001000)
#define | DMA2_FLAG_GL5 ((uint32_t)0x10010000)
#define | DMA2_FLAG_HT1 ((uint32_t)0x10000004)
#define | DMA2_FLAG_HT2 ((uint32_t)0x10000040)
#define | DMA2_FLAG_HT3 ((uint32_t)0x10000400)
#define | DMA2_FLAG_HT4 ((uint32_t)0x10004000)
#define | DMA2_FLAG_HT5 ((uint32_t)0x10040000)
#define | DMA2_FLAG_TC1 ((uint32_t)0x10000002)
#define | DMA2_FLAG_TC2 ((uint32_t)0x10000020)
#define | DMA2_FLAG_TC3 ((uint32_t)0x10000200)
#define | DMA2_FLAG_TC4 ((uint32_t)0x10002000)
#define | DMA2_FLAG_TC5 ((uint32_t)0x10020000)
#define | DMA2_FLAG_TE1 ((uint32_t)0x10000008)
#define | DMA2_FLAG_TE2 ((uint32_t)0x10000080)
#define | DMA2_FLAG_TE3 ((uint32_t)0x10000800)
#define | DMA2_FLAG_TE4 ((uint32_t)0x10008000)
#define | DMA2_FLAG_TE5 ((uint32_t)0x10080000)
#define | IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00))
#define | IS_DMA_GET_FLAG(FLAG)

Define Documentation

#define DMA1_FLAG_GL1 ((uint32_t)0x00000001)

Definition at line 304 of file stm32f10x_dma.h.

#define DMA1_FLAG_GL2 ((uint32_t)0x00000010)

Definition at line 308 of file stm32f10x_dma.h.

#define DMA1_FLAG_GL3 ((uint32_t)0x00000100)

Definition at line 312 of file stm32f10x_dma.h.

#define DMA1_FLAG_GL4 ((uint32_t)0x00001000)

Definition at line 316 of file stm32f10x_dma.h.

#define DMA1_FLAG_GL5 ((uint32_t)0x00010000)

Definition at line 320 of file stm32f10x_dma.h.

#define DMA1_FLAG_GL6 ((uint32_t)0x00100000)

Definition at line 324 of file stm32f10x_dma.h.

#define DMA1_FLAG_GL7 ((uint32_t)0x01000000)

Definition at line 328 of file stm32f10x_dma.h.

#define DMA1_FLAG_HT1 ((uint32_t)0x00000004)

Definition at line 306 of file stm32f10x_dma.h.

#define DMA1_FLAG_HT2 ((uint32_t)0x00000040)

Definition at line 310 of file stm32f10x_dma.h.

#define DMA1_FLAG_HT3 ((uint32_t)0x00000400)

Definition at line 314 of file stm32f10x_dma.h.

#define DMA1_FLAG_HT4 ((uint32_t)0x00004000)

Definition at line 318 of file stm32f10x_dma.h.

#define DMA1_FLAG_HT5 ((uint32_t)0x00040000)

Definition at line 322 of file stm32f10x_dma.h.

#define DMA1_FLAG_HT6 ((uint32_t)0x00400000)

Definition at line 326 of file stm32f10x_dma.h.

#define DMA1_FLAG_HT7 ((uint32_t)0x04000000)

Definition at line 330 of file stm32f10x_dma.h.

#define DMA1_FLAG_TC1 ((uint32_t)0x00000002)

Definition at line 305 of file stm32f10x_dma.h.

Referenced by main().

#define DMA1_FLAG_TC2 ((uint32_t)0x00000020)

Definition at line 309 of file stm32f10x_dma.h.

#define DMA1_FLAG_TC3 ((uint32_t)0x00000200)

Definition at line 313 of file stm32f10x_dma.h.

Referenced by main().

#define DMA1_FLAG_TC4 ((uint32_t)0x00002000)

Definition at line 317 of file stm32f10x_dma.h.

#define DMA1_FLAG_TC5 ((uint32_t)0x00020000)

Definition at line 321 of file stm32f10x_dma.h.

Referenced by main().

#define DMA1_FLAG_TC6 ((uint32_t)0x00200000)

Definition at line 325 of file stm32f10x_dma.h.

Referenced by main().

#define DMA1_FLAG_TC7 ((uint32_t)0x02000000)

Definition at line 329 of file stm32f10x_dma.h.

#define DMA1_FLAG_TE1 ((uint32_t)0x00000008)

Definition at line 307 of file stm32f10x_dma.h.

#define DMA1_FLAG_TE2 ((uint32_t)0x00000080)

Definition at line 311 of file stm32f10x_dma.h.

#define DMA1_FLAG_TE3 ((uint32_t)0x00000800)

Definition at line 315 of file stm32f10x_dma.h.

#define DMA1_FLAG_TE4 ((uint32_t)0x00008000)

Definition at line 319 of file stm32f10x_dma.h.

#define DMA1_FLAG_TE5 ((uint32_t)0x00080000)

Definition at line 323 of file stm32f10x_dma.h.

#define DMA1_FLAG_TE6 ((uint32_t)0x00800000)

Definition at line 327 of file stm32f10x_dma.h.

#define DMA1_FLAG_TE7 ((uint32_t)0x08000000)

Definition at line 331 of file stm32f10x_dma.h.

#define DMA2_FLAG_GL1 ((uint32_t)0x10000001)

Definition at line 333 of file stm32f10x_dma.h.

#define DMA2_FLAG_GL2 ((uint32_t)0x10000010)

Definition at line 337 of file stm32f10x_dma.h.

#define DMA2_FLAG_GL3 ((uint32_t)0x10000100)

Definition at line 341 of file stm32f10x_dma.h.

#define DMA2_FLAG_GL4 ((uint32_t)0x10001000)

Definition at line 345 of file stm32f10x_dma.h.

Referenced by SD_LowLevel_DMA_RxConfig(), and SD_LowLevel_DMA_TxConfig().

#define DMA2_FLAG_GL5 ((uint32_t)0x10010000)

Definition at line 349 of file stm32f10x_dma.h.

#define DMA2_FLAG_HT1 ((uint32_t)0x10000004)

Definition at line 335 of file stm32f10x_dma.h.

#define DMA2_FLAG_HT2 ((uint32_t)0x10000040)

Definition at line 339 of file stm32f10x_dma.h.

#define DMA2_FLAG_HT3 ((uint32_t)0x10000400)

Definition at line 343 of file stm32f10x_dma.h.

#define DMA2_FLAG_HT4 ((uint32_t)0x10004000)

Definition at line 347 of file stm32f10x_dma.h.

Referenced by SD_LowLevel_DMA_RxConfig(), and SD_LowLevel_DMA_TxConfig().

#define DMA2_FLAG_HT5 ((uint32_t)0x10040000)

Definition at line 351 of file stm32f10x_dma.h.

#define DMA2_FLAG_TC1 ((uint32_t)0x10000002)

Definition at line 334 of file stm32f10x_dma.h.

#define DMA2_FLAG_TC2 ((uint32_t)0x10000020)

Definition at line 338 of file stm32f10x_dma.h.

#define DMA2_FLAG_TC3 ((uint32_t)0x10000200)

Definition at line 342 of file stm32f10x_dma.h.

#define DMA2_FLAG_TC4 ((uint32_t)0x10002000)

Definition at line 346 of file stm32f10x_dma.h.

Referenced by SD_DMAEndOfTransferStatus(), SD_LowLevel_DMA_RxConfig(), and SD_LowLevel_DMA_TxConfig().

#define DMA2_FLAG_TC5 ((uint32_t)0x10020000)

Definition at line 350 of file stm32f10x_dma.h.

Referenced by main().

#define DMA2_FLAG_TE1 ((uint32_t)0x10000008)

Definition at line 336 of file stm32f10x_dma.h.

#define DMA2_FLAG_TE2 ((uint32_t)0x10000080)

Definition at line 340 of file stm32f10x_dma.h.

#define DMA2_FLAG_TE3 ((uint32_t)0x10000800)

Definition at line 344 of file stm32f10x_dma.h.

#define DMA2_FLAG_TE4 ((uint32_t)0x10008000)

Definition at line 348 of file stm32f10x_dma.h.

Referenced by SD_LowLevel_DMA_RxConfig(), and SD_LowLevel_DMA_TxConfig().

#define DMA2_FLAG_TE5 ((uint32_t)0x10080000)

Definition at line 352 of file stm32f10x_dma.h.

#define IS_DMA_CLEAR_FLAG ( FLAG ) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00))

Definition at line 354 of file stm32f10x_dma.h.

Referenced by DMA_ClearFlag().

#define IS_DMA_GET_FLAG ( FLAG )
Value:
(((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \
                               ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \
                               ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \
                               ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \
                               ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \
                               ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \
                               ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \
                               ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \
                               ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \
                               ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \
                               ((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \
                               ((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \
                               ((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \
                               ((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7) || \
                               ((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) || \
                               ((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_TE1) || \
                               ((FLAG) == DMA2_FLAG_GL2) || ((FLAG) == DMA2_FLAG_TC2) || \
                               ((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_TE2) || \
                               ((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || \
                               ((FLAG) == DMA2_FLAG_HT3) || ((FLAG) == DMA2_FLAG_TE3) || \
                               ((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) || \
                               ((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || \
                               ((FLAG) == DMA2_FLAG_GL5) || ((FLAG) == DMA2_FLAG_TC5) || \
                               ((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5))

Definition at line 356 of file stm32f10x_dma.h.

Referenced by DMA_GetFlagStatus().


STM32F10x Standard Peripherals Firmware Library: DMA_Buffer_Size

Defines

DMA_Buffer_Size

DMA_Exported_Constants

Defines

#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))

Define Documentation

#define IS_DMA_BUFFER_SIZE ( SIZE ) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))

Definition at line 388 of file stm32f10x_dma.h.

Referenced by DMA_Init().


STM32F10x Standard Peripherals Firmware Library: DMA_Exported_Constants

Modules | Defines

DMA_Exported_Constants

DMA

Modules

DMA_data_transfer_direction
DMA_peripheral_incremented_mode
DMA_memory_incremented_mode
DMA_peripheral_data_size
DMA_memory_data_size
DMA_circular_normal_mode
DMA_priority_level
DMA_memory_to_memory
DMA_interrupts_definition
DMA_flags_definition
DMA_Buffer_Size

Defines

#define IS_DMA_ALL_PERIPH(PERIPH)

Define Documentation

#define IS_DMA_ALL_PERIPH ( PERIPH )
Value:
(((PERIPH) == DMA1_Channel1) || \
                                   ((PERIPH) == DMA1_Channel2) || \
                                   ((PERIPH) == DMA1_Channel3) || \
                                   ((PERIPH) == DMA1_Channel4) || \
                                   ((PERIPH) == DMA1_Channel5) || \
                                   ((PERIPH) == DMA1_Channel6) || \
                                   ((PERIPH) == DMA1_Channel7) || \
                                   ((PERIPH) == DMA2_Channel1) || \
                                   ((PERIPH) == DMA2_Channel2) || \
                                   ((PERIPH) == DMA2_Channel3) || \
                                   ((PERIPH) == DMA2_Channel4) || \
                                   ((PERIPH) == DMA2_Channel5))

Definition at line 95 of file stm32f10x_dma.h.

Referenced by DMA_Cmd(), DMA_DeInit(), DMA_GetCurrDataCounter(), DMA_Init(), DMA_ITConfig(), and DMA_SetCurrDataCounter().


STM32F10x Standard Peripherals Firmware Library: DMA_Exported_Macros

DMA_Exported_Macros

DMA


STM32F10x Standard Peripherals Firmware Library: DMA_Exported_Functions

Functions

DMA_Exported_Functions

DMA

Functions

void | DMA_ClearFlag (uint32_t DMAy_FLAG)
Clears the DMAy Channelx's pending flags.
void | DMA_ClearITPendingBit (uint32_t DMAy_IT)
Clears the DMAy Channelx's interrupt pending bits.
void | DMA_Cmd (DMA_Channel_TypeDef *DMAy_Channelx, FunctionalState NewState)
Enables or disables the specified DMAy Channelx.
void | DMA_DeInit (DMA_Channel_TypeDef *DMAy_Channelx)
Deinitializes the DMAy Channelx registers to their default reset values.
uint16_t | DMA_GetCurrDataCounter (DMA_Channel_TypeDef *DMAy_Channelx)
Returns the number of remaining data units in the current DMAy Channelx transfer.
FlagStatus | DMA_GetFlagStatus (uint32_t DMAy_FLAG)
Checks whether the specified DMAy Channelx flag is set or not.
ITStatus | DMA_GetITStatus (uint32_t DMAy_IT)
Checks whether the specified DMAy Channelx interrupt has occurred or not.
void | DMA_Init (DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitTypeDef *DMA_InitStruct)
Initializes the DMAy Channelx according to the specified parameters in the DMA_InitStruct.
void | DMA_ITConfig (DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)
Enables or disables the specified DMAy Channelx interrupts.
void | DMA_SetCurrDataCounter (DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber)
Sets the number of data units in the current DMAy Channelx transfer.
void | DMA_StructInit (DMA_InitTypeDef *DMA_InitStruct)
Fills each DMA_InitStruct member with its default value.

Function Documentation

void DMA_ClearFlag ( uint32_t DMAy_FLAG )

Clears the DMAy Channelx's pending flags.

Parameters:
DMAy_FLAG,: specifies the flag to clear. This parameter can be any combination (for the same DMA) of the following values:

  • DMA1_FLAG_GL1: DMA1 Channel1 global flag.
  • DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
  • DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
  • DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
  • DMA1_FLAG_GL2: DMA1 Channel2 global flag.
  • DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
  • DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
  • DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
  • DMA1_FLAG_GL3: DMA1 Channel3 global flag.
  • DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
  • DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
  • DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
  • DMA1_FLAG_GL4: DMA1 Channel4 global flag.
  • DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
  • DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
  • DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
  • DMA1_FLAG_GL5: DMA1 Channel5 global flag.
  • DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
  • DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
  • DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
  • DMA1_FLAG_GL6: DMA1 Channel6 global flag.
  • DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
  • DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
  • DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
  • DMA1_FLAG_GL7: DMA1 Channel7 global flag.
  • DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
  • DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
  • DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
  • DMA2_FLAG_GL1: DMA2 Channel1 global flag.
  • DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
  • DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
  • DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
  • DMA2_FLAG_GL2: DMA2 Channel2 global flag.
  • DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
  • DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
  • DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
  • DMA2_FLAG_GL3: DMA2 Channel3 global flag.
  • DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
  • DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
  • DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
  • DMA2_FLAG_GL4: DMA2 Channel4 global flag.
  • DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
  • DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
  • DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
  • DMA2_FLAG_GL5: DMA2 Channel5 global flag.
  • DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
  • DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
  • DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
Return values:
None

Definition at line 523 of file stm32f10x_dma.c.

References assert_param, DMA1, DMA2, FLAG_Mask, IS_DMA_CLEAR_FLAG, and RESET.

Referenced by I2C_ReadDataBuffer(), I2C_ReadDeviceRegister(), I2C_WriteDeviceRegister(), LM75_ReadConfReg(), LM75_ReadReg(), LM75_ReadTemp(), LM75_ShutDown(), LM75_WriteConfReg(), LM75_WriteReg(), main(), SD_LowLevel_DMA_RxConfig(), SD_LowLevel_DMA_TxConfig(), sEE_I2C_DMA_RX_IRQHandler(), and sEE_I2C_DMA_TX_IRQHandler().

void DMA_ClearITPendingBit ( uint32_t DMAy_IT )

Clears the DMAy Channelx's interrupt pending bits.

Parameters:
DMAy_IT,: specifies the DMAy interrupt pending bit to clear. This parameter can be any combination (for the same DMA) of the following values:

  • DMA1_IT_GL1: DMA1 Channel1 global interrupt.
  • DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
  • DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
  • DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
  • DMA1_IT_GL2: DMA1 Channel2 global interrupt.
  • DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
  • DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
  • DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
  • DMA1_IT_GL3: DMA1 Channel3 global interrupt.
  • DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
  • DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
  • DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
  • DMA1_IT_GL4: DMA1 Channel4 global interrupt.
  • DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
  • DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
  • DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
  • DMA1_IT_GL5: DMA1 Channel5 global interrupt.
  • DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
  • DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
  • DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
  • DMA1_IT_GL6: DMA1 Channel6 global interrupt.
  • DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
  • DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
  • DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
  • DMA1_IT_GL7: DMA1 Channel7 global interrupt.
  • DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
  • DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
  • DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
  • DMA2_IT_GL1: DMA2 Channel1 global interrupt.
  • DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.
  • DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.
  • DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.
  • DMA2_IT_GL2: DMA2 Channel2 global interrupt.
  • DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.
  • DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.
  • DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.
  • DMA2_IT_GL3: DMA2 Channel3 global interrupt.
  • DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.
  • DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.
  • DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.
  • DMA2_IT_GL4: DMA2 Channel4 global interrupt.
  • DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.
  • DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.
  • DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.
  • DMA2_IT_GL5: DMA2 Channel5 global interrupt.
  • DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.
  • DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.
  • DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
Return values:
None

Definition at line 684 of file stm32f10x_dma.c.

References assert_param, DMA1, DMA2, FLAG_Mask, IS_DMA_CLEAR_IT, and RESET.

Referenced by DMA1_Channel5_IRQHandler(), and DMA1_Channel6_IRQHandler().

void DMA_Cmd | ( | DMA_Channel_TypeDef * | DMAy_Channelx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified DMAy Channelx.

Parameters:
DMAy_Channelx,: where y can be 1 or 2 to select the DMA and x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
NewState,: new state of the DMAy Channelx. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 294 of file stm32f10x_dma.c.

References assert_param, DMA_Channel_TypeDef::CCR, DISABLE, DMA_CCR1_EN, IS_DMA_ALL_PERIPH, and IS_FUNCTIONAL_STATE.

Referenced by DMA_Configuration(), I2C_ReadDataBuffer(), I2C_ReadDeviceRegister(), I2C_WriteDeviceRegister(), LM75_ReadConfReg(), LM75_ReadReg(), LM75_ReadTemp(), LM75_ShutDown(), LM75_WriteConfReg(), LM75_WriteReg(), main(), SD_LowLevel_DMA_RxConfig(), SD_LowLevel_DMA_TxConfig(), sEE_I2C_DMA_RX_IRQHandler(), sEE_I2C_DMA_TX_IRQHandler(), sEE_LowLevel_DeInit(), sEE_ReadBuffer(), and sEE_WritePage().

void DMA_DeInit ( DMA_Channel_TypeDef * DMAy_Channelx )

Deinitializes the DMAy Channelx registers to their default reset values.

Parameters:
DMAy_Channelx,: where y can be 1 or 2 to select the DMA and x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
Return values:
None

Definition at line 108 of file stm32f10x_dma.c.

References assert_param, DMA_Channel_TypeDef::CCR, DMA_Channel_TypeDef::CMAR, DMA_Channel_TypeDef::CNDTR, DMA_Channel_TypeDef::CPAR, DMA1, DMA1_Channel1, DMA1_Channel1_IT_Mask, DMA1_Channel2, DMA1_Channel2_IT_Mask, DMA1_Channel3, DMA1_Channel3_IT_Mask, DMA1_Channel4, DMA1_Channel4_IT_Mask, DMA1_Channel5, DMA1_Channel5_IT_Mask, DMA1_Channel6, DMA1_Channel6_IT_Mask, DMA1_Channel7, DMA1_Channel7_IT_Mask, DMA2, DMA2_Channel1, DMA2_Channel1_IT_Mask, DMA2_Channel2, DMA2_Channel2_IT_Mask, DMA2_Channel3, DMA2_Channel3_IT_Mask, DMA2_Channel4, DMA2_Channel4_IT_Mask, DMA2_Channel5, DMA2_Channel5_IT_Mask, DMA_CCR1_EN, and IS_DMA_ALL_PERIPH.

Referenced by DMA_Configuration(), IOE_DMA_Config(), LM75_DMA_Config(), main(), sEE_LowLevel_DeInit(), and sEE_LowLevel_Init().

uint16_t DMA_GetCurrDataCounter ( DMA_Channel_TypeDef * DMAy_Channelx )

Returns the number of remaining data units in the current DMAy Channelx transfer.

Parameters:
DMAy_Channelx,: where y can be 1 or 2 to select the DMA and x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
Return values:
The number of remaining data units in the current DMAy Channelx transfer.

Definition at line 371 of file stm32f10x_dma.c.

References assert_param, DMA_Channel_TypeDef::CNDTR, and IS_DMA_ALL_PERIPH.

Referenced by DMA1_Channel6_IRQHandler(), and main().

FlagStatus DMA_GetFlagStatus ( uint32_t DMAy_FLAG )

Checks whether the specified DMAy Channelx flag is set or not.

Parameters:
DMAy_FLAG,: specifies the flag to check. This parameter can be one of the following values:

  • DMA1_FLAG_GL1: DMA1 Channel1 global flag.
  • DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
  • DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
  • DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
  • DMA1_FLAG_GL2: DMA1 Channel2 global flag.
  • DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
  • DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
  • DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
  • DMA1_FLAG_GL3: DMA1 Channel3 global flag.
  • DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
  • DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
  • DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
  • DMA1_FLAG_GL4: DMA1 Channel4 global flag.
  • DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
  • DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
  • DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
  • DMA1_FLAG_GL5: DMA1 Channel5 global flag.
  • DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
  • DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
  • DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
  • DMA1_FLAG_GL6: DMA1 Channel6 global flag.
  • DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
  • DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
  • DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
  • DMA1_FLAG_GL7: DMA1 Channel7 global flag.
  • DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
  • DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
  • DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
  • DMA2_FLAG_GL1: DMA2 Channel1 global flag.
  • DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
  • DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
  • DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
  • DMA2_FLAG_GL2: DMA2 Channel2 global flag.
  • DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
  • DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
  • DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
  • DMA2_FLAG_GL3: DMA2 Channel3 global flag.
  • DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
  • DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
  • DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
  • DMA2_FLAG_GL4: DMA2 Channel4 global flag.
  • DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
  • DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
  • DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
  • DMA2_FLAG_GL5: DMA2 Channel5 global flag.
  • DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
  • DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
  • DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
Return values:
The new state of DMAy_FLAG (SET or RESET).

Definition at line 433 of file stm32f10x_dma.c.

References assert_param, DMA1, DMA2, FLAG_Mask, IS_DMA_GET_FLAG, RESET, and SET.

Referenced by I2C_ReadDataBuffer(), I2C_ReadDeviceRegister(), I2C_WriteDeviceRegister(), LM75_ReadConfReg(), LM75_ReadReg(), LM75_ReadTemp(), LM75_ShutDown(), LM75_WriteConfReg(), LM75_WriteReg(), main(), SD_DMAEndOfTransferStatus(), sEE_I2C_DMA_RX_IRQHandler(), and sEE_I2C_DMA_TX_IRQHandler().

ITStatus DMA_GetITStatus ( uint32_t DMAy_IT )

Checks whether the specified DMAy Channelx interrupt has occurred or not.

Parameters:
DMAy_IT,: specifies the DMAy interrupt source to check. This parameter can be one of the following values:

  • DMA1_IT_GL1: DMA1 Channel1 global interrupt.
  • DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
  • DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
  • DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
  • DMA1_IT_GL2: DMA1 Channel2 global interrupt.
  • DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
  • DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
  • DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
  • DMA1_IT_GL3: DMA1 Channel3 global interrupt.
  • DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
  • DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
  • DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
  • DMA1_IT_GL4: DMA1 Channel4 global interrupt.
  • DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
  • DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
  • DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
  • DMA1_IT_GL5: DMA1 Channel5 global interrupt.
  • DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
  • DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
  • DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
  • DMA1_IT_GL6: DMA1 Channel6 global interrupt.
  • DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
  • DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
  • DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
  • DMA1_IT_GL7: DMA1 Channel7 global interrupt.
  • DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
  • DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
  • DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
  • DMA2_IT_GL1: DMA2 Channel1 global interrupt.
  • DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.
  • DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.
  • DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.
  • DMA2_IT_GL2: DMA2 Channel2 global interrupt.
  • DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.
  • DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.
  • DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.
  • DMA2_IT_GL3: DMA2 Channel3 global interrupt.
  • DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.
  • DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.
  • DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.
  • DMA2_IT_GL4: DMA2 Channel4 global interrupt.
  • DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.
  • DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.
  • DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.
  • DMA2_IT_GL5: DMA2 Channel5 global interrupt.
  • DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.
  • DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.
  • DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
Return values:
The new state of DMAy_IT (SET or RESET).

Definition at line 595 of file stm32f10x_dma.c.

References assert_param, DMA1, DMA2, FLAG_Mask, IS_DMA_GET_IT, RESET, and SET.

Referenced by DMA1_Channel5_IRQHandler(), and DMA1_Channel6_IRQHandler().

void DMA_Init | ( | DMA_Channel_TypeDef * | DMAy_Channelx,
 |  | DMA_InitTypeDef * | DMA_InitStruct
 | ) |  |

Initializes the DMAy Channelx according to the specified parameters in the DMA_InitStruct.

Parameters:
DMAy_Channelx,: where y can be 1 or 2 to select the DMA and x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
DMA_InitStruct,: pointer to a DMA_InitTypeDef structure that contains the configuration information for the specified DMA Channel.
Return values:
None

Definition at line 202 of file stm32f10x_dma.c.

References assert_param, DMA_Channel_TypeDef::CCR, CCR_CLEAR_Mask, DMA_Channel_TypeDef::CMAR, DMA_Channel_TypeDef::CNDTR, DMA_Channel_TypeDef::CPAR, DMA_InitTypeDef::DMA_BufferSize, DMA_InitTypeDef::DMA_DIR, DMA_InitTypeDef::DMA_M2M, DMA_InitTypeDef::DMA_MemoryBaseAddr, DMA_InitTypeDef::DMA_MemoryDataSize, DMA_InitTypeDef::DMA_MemoryInc, DMA_InitTypeDef::DMA_Mode, DMA_InitTypeDef::DMA_PeripheralBaseAddr, DMA_InitTypeDef::DMA_PeripheralDataSize, DMA_InitTypeDef::DMA_PeripheralInc, DMA_InitTypeDef::DMA_Priority, IS_DMA_ALL_PERIPH, IS_DMA_BUFFER_SIZE, IS_DMA_DIR, IS_DMA_M2M_STATE, IS_DMA_MEMORY_DATA_SIZE, IS_DMA_MEMORY_INC_STATE, IS_DMA_MODE, IS_DMA_PERIPHERAL_DATA_SIZE, IS_DMA_PERIPHERAL_INC_STATE, and IS_DMA_PRIORITY.

Referenced by DMA_Configuration(), IOE_DMA_Config(), LM75_DMA_Config(), main(), SD_LowLevel_DMA_RxConfig(), SD_LowLevel_DMA_TxConfig(), sEE_LowLevel_DMAConfig(), and sEE_LowLevel_Init().

void DMA_ITConfig | ( | DMA_Channel_TypeDef * | DMAy_Channelx,
 |  | uint32_t | DMA_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified DMAy Channelx interrupts.

Parameters:
DMAy_Channelx,: where y can be 1 or 2 to select the DMA and x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
DMA_IT,: specifies the DMA interrupts sources to be enabled or disabled. This parameter can be any combination of the following values:

  • DMA_IT_TC: Transfer complete interrupt mask
  • DMA_IT_HT: Half transfer interrupt mask
  • DMA_IT_TE: Transfer error interrupt mask
NewState,: new state of the specified DMA interrupts. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 326 of file stm32f10x_dma.c.

References assert_param, DMA_Channel_TypeDef::CCR, DISABLE, IS_DMA_ALL_PERIPH, IS_DMA_CONFIG_IT, and IS_FUNCTIONAL_STATE.

Referenced by DMA_Configuration(), main(), and sEE_LowLevel_Init().

void DMA_SetCurrDataCounter | ( | DMA_Channel_TypeDef * | DMAy_Channelx,
 |  | uint16_t | DataNumber
 | ) |  |

Sets the number of data units in the current DMAy Channelx transfer.

Parameters:
DMAy_Channelx,: where y can be 1 or 2 to select the DMA and x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
DataNumber,: The number of data units in the current DMAy Channelx transfer.
Note:
This function can only be used when the DMAy_Channelx is disabled.
Return values:
None.

Definition at line 353 of file stm32f10x_dma.c.

References assert_param, DMA_Channel_TypeDef::CNDTR, and IS_DMA_ALL_PERIPH.

void DMA_StructInit ( DMA_InitTypeDef * DMA_InitStruct )

Fills each DMA_InitStruct member with its default value.

Parameters:
DMA_InitStruct : pointer to a DMA_InitTypeDef structure which will be initialized.
Return values:
None

Definition at line 259 of file stm32f10x_dma.c.

References DMA_InitTypeDef::DMA_BufferSize, DMA_InitTypeDef::DMA_DIR, DMA_DIR_PeripheralSRC, DMA_InitTypeDef::DMA_M2M, DMA_M2M_Disable, DMA_InitTypeDef::DMA_MemoryBaseAddr, DMA_InitTypeDef::DMA_MemoryDataSize, DMA_MemoryDataSize_Byte, DMA_InitTypeDef::DMA_MemoryInc, DMA_MemoryInc_Disable, DMA_InitTypeDef::DMA_Mode, DMA_Mode_Normal, DMA_InitTypeDef::DMA_PeripheralBaseAddr, DMA_InitTypeDef::DMA_PeripheralDataSize, DMA_PeripheralDataSize_Byte, DMA_InitTypeDef::DMA_PeripheralInc, DMA_PeripheralInc_Disable, DMA_InitTypeDef::DMA_Priority, and DMA_Priority_Low.


STM32F10x Standard Peripherals Firmware Library: DMA_Private_TypesDefinitions

DMA_Private_TypesDefinitions

DMA


STM32F10x Standard Peripherals Firmware Library: DMA_Private_Defines

Defines

DMA_Private_Defines

DMA

Defines

#define | CCR_CLEAR_Mask ((uint32_t)0xFFFF800F)
#define | DMA1_Channel1_IT_Mask ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))
#define | DMA1_Channel2_IT_Mask ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))
#define | DMA1_Channel3_IT_Mask ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))
#define | DMA1_Channel4_IT_Mask ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))
#define | DMA1_Channel5_IT_Mask ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))
#define | DMA1_Channel6_IT_Mask ((uint32_t)(DMA_ISR_GIF6 | DMA_ISR_TCIF6 | DMA_ISR_HTIF6 | DMA_ISR_TEIF6))
#define | DMA1_Channel7_IT_Mask ((uint32_t)(DMA_ISR_GIF7 | DMA_ISR_TCIF7 | DMA_ISR_HTIF7 | DMA_ISR_TEIF7))
#define | DMA2_Channel1_IT_Mask ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))
#define | DMA2_Channel2_IT_Mask ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))
#define | DMA2_Channel3_IT_Mask ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))
#define | DMA2_Channel4_IT_Mask ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))
#define | DMA2_Channel5_IT_Mask ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))
#define | FLAG_Mask ((uint32_t)0x10000000)

Define Documentation

#define CCR_CLEAR_Mask ((uint32_t)0xFFFF800F)

Definition at line 67 of file stm32f10x_dma.c.

Referenced by DMA_Init().

#define DMA1_Channel1_IT_Mask ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))

Definition at line 48 of file stm32f10x_dma.c.

Referenced by DMA_DeInit().

#define DMA1_Channel2_IT_Mask ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))

Definition at line 49 of file stm32f10x_dma.c.

Referenced by DMA_DeInit().

#define DMA1_Channel3_IT_Mask ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))

Definition at line 50 of file stm32f10x_dma.c.

Referenced by DMA_DeInit().

#define DMA1_Channel4_IT_Mask ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))

Definition at line 51 of file stm32f10x_dma.c.

Referenced by DMA_DeInit().

#define DMA1_Channel5_IT_Mask ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))

Definition at line 52 of file stm32f10x_dma.c.

Referenced by DMA_DeInit().

#define DMA1_Channel6_IT_Mask ((uint32_t)(DMA_ISR_GIF6 | DMA_ISR_TCIF6 | DMA_ISR_HTIF6 | DMA_ISR_TEIF6))

Definition at line 53 of file stm32f10x_dma.c.

Referenced by DMA_DeInit().

#define DMA1_Channel7_IT_Mask ((uint32_t)(DMA_ISR_GIF7 | DMA_ISR_TCIF7 | DMA_ISR_HTIF7 | DMA_ISR_TEIF7))

Definition at line 54 of file stm32f10x_dma.c.

Referenced by DMA_DeInit().

#define DMA2_Channel1_IT_Mask ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))

Definition at line 57 of file stm32f10x_dma.c.

Referenced by DMA_DeInit().

#define DMA2_Channel2_IT_Mask ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))

Definition at line 58 of file stm32f10x_dma.c.

Referenced by DMA_DeInit().

#define DMA2_Channel3_IT_Mask ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))

Definition at line 59 of file stm32f10x_dma.c.

Referenced by DMA_DeInit().

#define DMA2_Channel4_IT_Mask ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))

Definition at line 60 of file stm32f10x_dma.c.

Referenced by DMA_DeInit().

#define DMA2_Channel5_IT_Mask ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))

Definition at line 61 of file stm32f10x_dma.c.

Referenced by DMA_DeInit().

#define FLAG_Mask ((uint32_t)0x10000000)

Definition at line 64 of file stm32f10x_dma.c.

Referenced by DMA_ClearFlag(), DMA_ClearITPendingBit(), DMA_GetFlagStatus(), and DMA_GetITStatus().


STM32F10x Standard Peripherals Firmware Library: DMA_Private_Macros

DMA_Private_Macros

DMA


STM32F10x Standard Peripherals Firmware Library: DMA_Private_Variables

DMA_Private_Variables

DMA


STM32F10x Standard Peripherals Firmware Library: DMA_Private_FunctionPrototypes

DMA_Private_FunctionPrototypes

DMA


STM32F10x Standard Peripherals Firmware Library: DMA_Private_Functions

Functions

DMA_Private_Functions

DMA

Functions

void | DMA_ClearFlag (uint32_t DMAy_FLAG)
Clears the DMAy Channelx's pending flags.
void | DMA_ClearITPendingBit (uint32_t DMAy_IT)
Clears the DMAy Channelx's interrupt pending bits.
void | DMA_Cmd (DMA_Channel_TypeDef *DMAy_Channelx, FunctionalState NewState)
Enables or disables the specified DMAy Channelx.
void | DMA_DeInit (DMA_Channel_TypeDef *DMAy_Channelx)
Deinitializes the DMAy Channelx registers to their default reset values.
uint16_t | DMA_GetCurrDataCounter (DMA_Channel_TypeDef *DMAy_Channelx)
Returns the number of remaining data units in the current DMAy Channelx transfer.
FlagStatus | DMA_GetFlagStatus (uint32_t DMAy_FLAG)
Checks whether the specified DMAy Channelx flag is set or not.
ITStatus | DMA_GetITStatus (uint32_t DMAy_IT)
Checks whether the specified DMAy Channelx interrupt has occurred or not.
void | DMA_Init (DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitTypeDef *DMA_InitStruct)
Initializes the DMAy Channelx according to the specified parameters in the DMA_InitStruct.
void | DMA_ITConfig (DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)
Enables or disables the specified DMAy Channelx interrupts.
void | DMA_SetCurrDataCounter (DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber)
Sets the number of data units in the current DMAy Channelx transfer.
void | DMA_StructInit (DMA_InitTypeDef *DMA_InitStruct)
Fills each DMA_InitStruct member with its default value.

Function Documentation

void DMA_ClearFlag ( uint32_t DMAy_FLAG )

Clears the DMAy Channelx's pending flags.

Parameters:
DMAy_FLAG,: specifies the flag to clear. This parameter can be any combination (for the same DMA) of the following values:

  • DMA1_FLAG_GL1: DMA1 Channel1 global flag.
  • DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
  • DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
  • DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
  • DMA1_FLAG_GL2: DMA1 Channel2 global flag.
  • DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
  • DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
  • DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
  • DMA1_FLAG_GL3: DMA1 Channel3 global flag.
  • DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
  • DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
  • DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
  • DMA1_FLAG_GL4: DMA1 Channel4 global flag.
  • DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
  • DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
  • DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
  • DMA1_FLAG_GL5: DMA1 Channel5 global flag.
  • DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
  • DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
  • DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
  • DMA1_FLAG_GL6: DMA1 Channel6 global flag.
  • DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
  • DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
  • DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
  • DMA1_FLAG_GL7: DMA1 Channel7 global flag.
  • DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
  • DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
  • DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
  • DMA2_FLAG_GL1: DMA2 Channel1 global flag.
  • DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
  • DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
  • DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
  • DMA2_FLAG_GL2: DMA2 Channel2 global flag.
  • DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
  • DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
  • DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
  • DMA2_FLAG_GL3: DMA2 Channel3 global flag.
  • DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
  • DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
  • DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
  • DMA2_FLAG_GL4: DMA2 Channel4 global flag.
  • DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
  • DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
  • DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
  • DMA2_FLAG_GL5: DMA2 Channel5 global flag.
  • DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
  • DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
  • DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
Return values:
None

Definition at line 523 of file stm32f10x_dma.c.

References assert_param, DMA1, DMA2, FLAG_Mask, IS_DMA_CLEAR_FLAG, and RESET.

Referenced by I2C_ReadDataBuffer(), I2C_ReadDeviceRegister(), I2C_WriteDeviceRegister(), LM75_ReadConfReg(), LM75_ReadReg(), LM75_ReadTemp(), LM75_ShutDown(), LM75_WriteConfReg(), LM75_WriteReg(), main(), SD_LowLevel_DMA_RxConfig(), SD_LowLevel_DMA_TxConfig(), sEE_I2C_DMA_RX_IRQHandler(), and sEE_I2C_DMA_TX_IRQHandler().

void DMA_ClearITPendingBit ( uint32_t DMAy_IT )

Clears the DMAy Channelx's interrupt pending bits.

Parameters:
DMAy_IT,: specifies the DMAy interrupt pending bit to clear. This parameter can be any combination (for the same DMA) of the following values:

  • DMA1_IT_GL1: DMA1 Channel1 global interrupt.
  • DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
  • DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
  • DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
  • DMA1_IT_GL2: DMA1 Channel2 global interrupt.
  • DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
  • DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
  • DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
  • DMA1_IT_GL3: DMA1 Channel3 global interrupt.
  • DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
  • DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
  • DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
  • DMA1_IT_GL4: DMA1 Channel4 global interrupt.
  • DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
  • DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
  • DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
  • DMA1_IT_GL5: DMA1 Channel5 global interrupt.
  • DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
  • DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
  • DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
  • DMA1_IT_GL6: DMA1 Channel6 global interrupt.
  • DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
  • DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
  • DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
  • DMA1_IT_GL7: DMA1 Channel7 global interrupt.
  • DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
  • DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
  • DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
  • DMA2_IT_GL1: DMA2 Channel1 global interrupt.
  • DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.
  • DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.
  • DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.
  • DMA2_IT_GL2: DMA2 Channel2 global interrupt.
  • DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.
  • DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.
  • DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.
  • DMA2_IT_GL3: DMA2 Channel3 global interrupt.
  • DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.
  • DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.
  • DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.
  • DMA2_IT_GL4: DMA2 Channel4 global interrupt.
  • DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.
  • DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.
  • DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.
  • DMA2_IT_GL5: DMA2 Channel5 global interrupt.
  • DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.
  • DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.
  • DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
Return values:
None

Definition at line 684 of file stm32f10x_dma.c.

References assert_param, DMA1, DMA2, FLAG_Mask, IS_DMA_CLEAR_IT, and RESET.

Referenced by DMA1_Channel5_IRQHandler(), and DMA1_Channel6_IRQHandler().

void DMA_Cmd | ( | DMA_Channel_TypeDef * | DMAy_Channelx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified DMAy Channelx.

Parameters:
DMAy_Channelx,: where y can be 1 or 2 to select the DMA and x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
NewState,: new state of the DMAy Channelx. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 294 of file stm32f10x_dma.c.

References assert_param, DMA_Channel_TypeDef::CCR, DISABLE, DMA_CCR1_EN, IS_DMA_ALL_PERIPH, and IS_FUNCTIONAL_STATE.

Referenced by DMA_Configuration(), I2C_ReadDataBuffer(), I2C_ReadDeviceRegister(), I2C_WriteDeviceRegister(), LM75_ReadConfReg(), LM75_ReadReg(), LM75_ReadTemp(), LM75_ShutDown(), LM75_WriteConfReg(), LM75_WriteReg(), main(), SD_LowLevel_DMA_RxConfig(), SD_LowLevel_DMA_TxConfig(), sEE_I2C_DMA_RX_IRQHandler(), sEE_I2C_DMA_TX_IRQHandler(), sEE_LowLevel_DeInit(), sEE_ReadBuffer(), and sEE_WritePage().

void DMA_DeInit ( DMA_Channel_TypeDef * DMAy_Channelx )

Deinitializes the DMAy Channelx registers to their default reset values.

Parameters:
DMAy_Channelx,: where y can be 1 or 2 to select the DMA and x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
Return values:
None

Definition at line 108 of file stm32f10x_dma.c.

References assert_param, DMA_Channel_TypeDef::CCR, DMA_Channel_TypeDef::CMAR, DMA_Channel_TypeDef::CNDTR, DMA_Channel_TypeDef::CPAR, DMA1, DMA1_Channel1, DMA1_Channel1_IT_Mask, DMA1_Channel2, DMA1_Channel2_IT_Mask, DMA1_Channel3, DMA1_Channel3_IT_Mask, DMA1_Channel4, DMA1_Channel4_IT_Mask, DMA1_Channel5, DMA1_Channel5_IT_Mask, DMA1_Channel6, DMA1_Channel6_IT_Mask, DMA1_Channel7, DMA1_Channel7_IT_Mask, DMA2, DMA2_Channel1, DMA2_Channel1_IT_Mask, DMA2_Channel2, DMA2_Channel2_IT_Mask, DMA2_Channel3, DMA2_Channel3_IT_Mask, DMA2_Channel4, DMA2_Channel4_IT_Mask, DMA2_Channel5, DMA2_Channel5_IT_Mask, DMA_CCR1_EN, and IS_DMA_ALL_PERIPH.

Referenced by DMA_Configuration(), IOE_DMA_Config(), LM75_DMA_Config(), main(), sEE_LowLevel_DeInit(), and sEE_LowLevel_Init().

uint16_t DMA_GetCurrDataCounter ( DMA_Channel_TypeDef * DMAy_Channelx )

Returns the number of remaining data units in the current DMAy Channelx transfer.

Parameters:
DMAy_Channelx,: where y can be 1 or 2 to select the DMA and x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
Return values:
The number of remaining data units in the current DMAy Channelx transfer.

Definition at line 371 of file stm32f10x_dma.c.

References assert_param, DMA_Channel_TypeDef::CNDTR, and IS_DMA_ALL_PERIPH.

Referenced by DMA1_Channel6_IRQHandler(), and main().

FlagStatus DMA_GetFlagStatus ( uint32_t DMAy_FLAG )

Checks whether the specified DMAy Channelx flag is set or not.

Parameters:
DMAy_FLAG,: specifies the flag to check. This parameter can be one of the following values:

  • DMA1_FLAG_GL1: DMA1 Channel1 global flag.
  • DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
  • DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
  • DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
  • DMA1_FLAG_GL2: DMA1 Channel2 global flag.
  • DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
  • DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
  • DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
  • DMA1_FLAG_GL3: DMA1 Channel3 global flag.
  • DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
  • DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
  • DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
  • DMA1_FLAG_GL4: DMA1 Channel4 global flag.
  • DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
  • DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
  • DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
  • DMA1_FLAG_GL5: DMA1 Channel5 global flag.
  • DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
  • DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
  • DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
  • DMA1_FLAG_GL6: DMA1 Channel6 global flag.
  • DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
  • DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
  • DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
  • DMA1_FLAG_GL7: DMA1 Channel7 global flag.
  • DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
  • DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
  • DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
  • DMA2_FLAG_GL1: DMA2 Channel1 global flag.
  • DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
  • DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
  • DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
  • DMA2_FLAG_GL2: DMA2 Channel2 global flag.
  • DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
  • DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
  • DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
  • DMA2_FLAG_GL3: DMA2 Channel3 global flag.
  • DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
  • DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
  • DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
  • DMA2_FLAG_GL4: DMA2 Channel4 global flag.
  • DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
  • DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
  • DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
  • DMA2_FLAG_GL5: DMA2 Channel5 global flag.
  • DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
  • DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
  • DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
Return values:
The new state of DMAy_FLAG (SET or RESET).

Definition at line 433 of file stm32f10x_dma.c.

References assert_param, DMA1, DMA2, FLAG_Mask, IS_DMA_GET_FLAG, RESET, and SET.

Referenced by I2C_ReadDataBuffer(), I2C_ReadDeviceRegister(), I2C_WriteDeviceRegister(), LM75_ReadConfReg(), LM75_ReadReg(), LM75_ReadTemp(), LM75_ShutDown(), LM75_WriteConfReg(), LM75_WriteReg(), main(), SD_DMAEndOfTransferStatus(), sEE_I2C_DMA_RX_IRQHandler(), and sEE_I2C_DMA_TX_IRQHandler().

ITStatus DMA_GetITStatus ( uint32_t DMAy_IT )

Checks whether the specified DMAy Channelx interrupt has occurred or not.

Parameters:
DMAy_IT,: specifies the DMAy interrupt source to check. This parameter can be one of the following values:

  • DMA1_IT_GL1: DMA1 Channel1 global interrupt.
  • DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
  • DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
  • DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
  • DMA1_IT_GL2: DMA1 Channel2 global interrupt.
  • DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
  • DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
  • DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
  • DMA1_IT_GL3: DMA1 Channel3 global interrupt.
  • DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
  • DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
  • DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
  • DMA1_IT_GL4: DMA1 Channel4 global interrupt.
  • DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
  • DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
  • DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
  • DMA1_IT_GL5: DMA1 Channel5 global interrupt.
  • DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
  • DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
  • DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
  • DMA1_IT_GL6: DMA1 Channel6 global interrupt.
  • DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
  • DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
  • DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
  • DMA1_IT_GL7: DMA1 Channel7 global interrupt.
  • DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
  • DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
  • DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
  • DMA2_IT_GL1: DMA2 Channel1 global interrupt.
  • DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.
  • DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.
  • DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.
  • DMA2_IT_GL2: DMA2 Channel2 global interrupt.
  • DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.
  • DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.
  • DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.
  • DMA2_IT_GL3: DMA2 Channel3 global interrupt.
  • DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.
  • DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.
  • DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.
  • DMA2_IT_GL4: DMA2 Channel4 global interrupt.
  • DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.
  • DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.
  • DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.
  • DMA2_IT_GL5: DMA2 Channel5 global interrupt.
  • DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.
  • DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.
  • DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
Return values:
The new state of DMAy_IT (SET or RESET).

Definition at line 595 of file stm32f10x_dma.c.

References assert_param, DMA1, DMA2, FLAG_Mask, IS_DMA_GET_IT, RESET, and SET.

Referenced by DMA1_Channel5_IRQHandler(), and DMA1_Channel6_IRQHandler().

void DMA_Init | ( | DMA_Channel_TypeDef * | DMAy_Channelx,
 |  | DMA_InitTypeDef * | DMA_InitStruct
 | ) |  |

Initializes the DMAy Channelx according to the specified parameters in the DMA_InitStruct.

Parameters:
DMAy_Channelx,: where y can be 1 or 2 to select the DMA and x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
DMA_InitStruct,: pointer to a DMA_InitTypeDef structure that contains the configuration information for the specified DMA Channel.
Return values:
None

Definition at line 202 of file stm32f10x_dma.c.

References assert_param, DMA_Channel_TypeDef::CCR, CCR_CLEAR_Mask, DMA_Channel_TypeDef::CMAR, DMA_Channel_TypeDef::CNDTR, DMA_Channel_TypeDef::CPAR, DMA_InitTypeDef::DMA_BufferSize, DMA_InitTypeDef::DMA_DIR, DMA_InitTypeDef::DMA_M2M, DMA_InitTypeDef::DMA_MemoryBaseAddr, DMA_InitTypeDef::DMA_MemoryDataSize, DMA_InitTypeDef::DMA_MemoryInc, DMA_InitTypeDef::DMA_Mode, DMA_InitTypeDef::DMA_PeripheralBaseAddr, DMA_InitTypeDef::DMA_PeripheralDataSize, DMA_InitTypeDef::DMA_PeripheralInc, DMA_InitTypeDef::DMA_Priority, IS_DMA_ALL_PERIPH, IS_DMA_BUFFER_SIZE, IS_DMA_DIR, IS_DMA_M2M_STATE, IS_DMA_MEMORY_DATA_SIZE, IS_DMA_MEMORY_INC_STATE, IS_DMA_MODE, IS_DMA_PERIPHERAL_DATA_SIZE, IS_DMA_PERIPHERAL_INC_STATE, and IS_DMA_PRIORITY.

Referenced by DMA_Configuration(), IOE_DMA_Config(), LM75_DMA_Config(), main(), SD_LowLevel_DMA_RxConfig(), SD_LowLevel_DMA_TxConfig(), sEE_LowLevel_DMAConfig(), and sEE_LowLevel_Init().

void DMA_ITConfig | ( | DMA_Channel_TypeDef * | DMAy_Channelx,
 |  | uint32_t | DMA_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified DMAy Channelx interrupts.

Parameters:
DMAy_Channelx,: where y can be 1 or 2 to select the DMA and x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
DMA_IT,: specifies the DMA interrupts sources to be enabled or disabled. This parameter can be any combination of the following values:

  • DMA_IT_TC: Transfer complete interrupt mask
  • DMA_IT_HT: Half transfer interrupt mask
  • DMA_IT_TE: Transfer error interrupt mask
NewState,: new state of the specified DMA interrupts. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 326 of file stm32f10x_dma.c.

References assert_param, DMA_Channel_TypeDef::CCR, DISABLE, IS_DMA_ALL_PERIPH, IS_DMA_CONFIG_IT, and IS_FUNCTIONAL_STATE.

Referenced by DMA_Configuration(), main(), and sEE_LowLevel_Init().

void DMA_SetCurrDataCounter | ( | DMA_Channel_TypeDef * | DMAy_Channelx,
 |  | uint16_t | DataNumber
 | ) |  |

Sets the number of data units in the current DMAy Channelx transfer.

Parameters:
DMAy_Channelx,: where y can be 1 or 2 to select the DMA and x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
DataNumber,: The number of data units in the current DMAy Channelx transfer.
Note:
This function can only be used when the DMAy_Channelx is disabled.
Return values:
None.

Definition at line 353 of file stm32f10x_dma.c.

References assert_param, DMA_Channel_TypeDef::CNDTR, and IS_DMA_ALL_PERIPH.

void DMA_StructInit ( DMA_InitTypeDef * DMA_InitStruct )

Fills each DMA_InitStruct member with its default value.

Parameters:
DMA_InitStruct : pointer to a DMA_InitTypeDef structure which will be initialized.
Return values:
None

Definition at line 259 of file stm32f10x_dma.c.

References DMA_InitTypeDef::DMA_BufferSize, DMA_InitTypeDef::DMA_DIR, DMA_DIR_PeripheralSRC, DMA_InitTypeDef::DMA_M2M, DMA_M2M_Disable, DMA_InitTypeDef::DMA_MemoryBaseAddr, DMA_InitTypeDef::DMA_MemoryDataSize, DMA_MemoryDataSize_Byte, DMA_InitTypeDef::DMA_MemoryInc, DMA_MemoryInc_Disable, DMA_InitTypeDef::DMA_Mode, DMA_Mode_Normal, DMA_InitTypeDef::DMA_PeripheralBaseAddr, DMA_InitTypeDef::DMA_PeripheralDataSize, DMA_PeripheralDataSize_Byte, DMA_InitTypeDef::DMA_PeripheralInc, DMA_PeripheralInc_Disable, DMA_InitTypeDef::DMA_Priority, and DMA_Priority_Low.


STM32F10x Standard Peripherals Firmware Library: EXTI_Exported_Types

Data Structures | Defines | Enumerations

EXTI_Exported_Types

EXTI

Data Structures

struct | EXTI_InitTypeDef
EXTI Init Structure definition. More...

Defines

#define | IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))
#define | IS_EXTI_TRIGGER(TRIGGER)

Enumerations

enum | EXTIMode_TypeDef { EXTI_Mode_Interrupt = 0x00, EXTI_Mode_Event = 0x04 }

EXTI mode enumeration.

More...
enum | EXTITrigger_TypeDef { EXTI_Trigger_Rising = 0x08, EXTI_Trigger_Falling = 0x0C, EXTI_Trigger_Rising_Falling = 0x10 }

EXTI Trigger enumeration.

More...

Define Documentation

#define IS_EXTI_MODE ( MODE ) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))

Definition at line 56 of file stm32f10x_exti.h.

Referenced by EXTI_Init().

#define IS_EXTI_TRIGGER ( TRIGGER )
Value:
(((TRIGGER) == EXTI_Trigger_Rising) || \
                                  ((TRIGGER) == EXTI_Trigger_Falling) || \
                                  ((TRIGGER) == EXTI_Trigger_Rising_Falling))

Definition at line 69 of file stm32f10x_exti.h.

Referenced by EXTI_Init().

Enumeration Type Documentation

enum EXTIMode_TypeDef

EXTI mode enumeration.

Enumerator:
EXTI_Mode_Interrupt
EXTI_Mode_Event

Definition at line 50 of file stm32f10x_exti.h.

enum EXTITrigger_TypeDef

EXTI Trigger enumeration.

Enumerator:
EXTI_Trigger_Rising
EXTI_Trigger_Falling
EXTI_Trigger_Rising_Falling

Definition at line 62 of file stm32f10x_exti.h.


STM32F10x Standard Peripherals Firmware Library: EXTI_InitTypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

EXTI_InitTypeDef Struct Reference
EXTI_Exported_Types

EXTI Init Structure definition. More...

#include <stm32f10x_exti.h>

Data Fields

uint32_t EXTI_Line
FunctionalState EXTI_LineCmd
EXTIMode_TypeDef EXTI_Mode
EXTITrigger_TypeDef EXTI_Trigger

Detailed Description

EXTI Init Structure definition.

Definition at line 76 of file stm32f10x_exti.h.

Field Documentation

uint32_t EXTI_InitTypeDef::EXTI_Line

Specifies the EXTI lines to be enabled or disabled. This parameter can be any combination of EXTI_Lines

Definition at line 78 of file stm32f10x_exti.h.

Referenced by EXTI0_Config(), EXTI9_5_Config(), EXTI_Configuration(), EXTI_Init(), EXTI_StructInit(), HDMI_CEC_CommandCallBack(), IOE_EXTI_Config(), and STM_EVAL_PBInit().

FunctionalState EXTI_InitTypeDef::EXTI_LineCmd

Specifies the new state of the selected EXTI lines. This parameter can be set either to ENABLE or DISABLE

Definition at line 87 of file stm32f10x_exti.h.

Referenced by EXTI0_Config(), EXTI9_5_Config(), EXTI_Configuration(), EXTI_Init(), EXTI_StructInit(), HDMI_CEC_CommandCallBack(), IOE_EXTI_Config(), and STM_EVAL_PBInit().

EXTIMode_TypeDef EXTI_InitTypeDef::EXTI_Mode

Specifies the mode for the EXTI lines. This parameter can be a value of EXTIMode_TypeDef

Definition at line 81 of file stm32f10x_exti.h.

Referenced by EXTI0_Config(), EXTI9_5_Config(), EXTI_Configuration(), EXTI_Init(), EXTI_StructInit(), HDMI_CEC_CommandCallBack(), IOE_EXTI_Config(), and STM_EVAL_PBInit().

EXTITrigger_TypeDef EXTI_InitTypeDef::EXTI_Trigger

Specifies the trigger signal active edge for the EXTI lines. This parameter can be a value of EXTIMode_TypeDef

Definition at line 84 of file stm32f10x_exti.h.

Referenced by EXTI0_Config(), EXTI9_5_Config(), EXTI_Configuration(), EXTI_Init(), EXTI_StructInit(), HDMI_CEC_CommandCallBack(), IOE_EXTI_Config(), and STM_EVAL_PBInit().

The documentation for this struct was generated from the following file:
  • stm32f10x_exti.h


STM32F10x Standard Peripherals Firmware Library: EXTI_Lines

Defines

EXTI_Lines

EXTI_Exported_Constants

Defines

#define | EXTI_Line0 ((uint32_t)0x00001)
#define | EXTI_Line1 ((uint32_t)0x00002)
#define | EXTI_Line10 ((uint32_t)0x00400)
#define | EXTI_Line11 ((uint32_t)0x00800)
#define | EXTI_Line12 ((uint32_t)0x01000)
#define | EXTI_Line13 ((uint32_t)0x02000)
#define | EXTI_Line14 ((uint32_t)0x04000)
#define | EXTI_Line15 ((uint32_t)0x08000)
#define | EXTI_Line16 ((uint32_t)0x10000)
#define | EXTI_Line17 ((uint32_t)0x20000)
#define | EXTI_Line18 ((uint32_t)0x40000)
#define | EXTI_Line19 ((uint32_t)0x80000)
#define | EXTI_Line2 ((uint32_t)0x00004)
#define | EXTI_Line3 ((uint32_t)0x00008)
#define | EXTI_Line4 ((uint32_t)0x00010)
#define | EXTI_Line5 ((uint32_t)0x00020)
#define | EXTI_Line6 ((uint32_t)0x00040)
#define | EXTI_Line7 ((uint32_t)0x00080)
#define | EXTI_Line8 ((uint32_t)0x00100)
#define | EXTI_Line9 ((uint32_t)0x00200)
#define | IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFFF00000) == 0x00) && ((LINE) != (uint16_t)0x00))
#define | IS_GET_EXTI_LINE(LINE)

Define Documentation

#define EXTI_Line0 ((uint32_t)0x00001)

External interrupt line 0

Definition at line 103 of file stm32f10x_exti.h.

Referenced by EXTI0_Config(), EXTI0_IRQHandler(), and main().

#define EXTI_Line1 ((uint32_t)0x00002)

External interrupt line 1

Definition at line 104 of file stm32f10x_exti.h.

#define EXTI_Line10 ((uint32_t)0x00400)

External interrupt line 10

Definition at line 113 of file stm32f10x_exti.h.

#define EXTI_Line11 ((uint32_t)0x00800)

External interrupt line 11

Definition at line 114 of file stm32f10x_exti.h.

Referenced by EXTI_Configuration().

#define EXTI_Line12 ((uint32_t)0x01000)

External interrupt line 12

Definition at line 115 of file stm32f10x_exti.h.

#define EXTI_Line13 ((uint32_t)0x02000)

External interrupt line 13

Definition at line 116 of file stm32f10x_exti.h.

#define EXTI_Line14 ((uint32_t)0x04000)

External interrupt line 14

Definition at line 117 of file stm32f10x_exti.h.

#define EXTI_Line15 ((uint32_t)0x08000)

External interrupt line 15

Definition at line 118 of file stm32f10x_exti.h.

Referenced by EXTI_Configuration().

#define EXTI_Line16 ((uint32_t)0x10000)

External interrupt line 16 Connected to the PVD Output

Definition at line 119 of file stm32f10x_exti.h.

Referenced by PVD_IRQHandler().

#define EXTI_Line17 ((uint32_t)0x20000)

External interrupt line 17 Connected to the RTC Alarm event

Definition at line 120 of file stm32f10x_exti.h.

Referenced by RTCAlarm_IRQHandler().

#define EXTI_Line18 ((uint32_t)0x40000)

External interrupt line 18 Connected to the USB Device/USB OTG FS Wakeup from suspend event

Definition at line 121 of file stm32f10x_exti.h.

#define EXTI_Line19 ((uint32_t)0x80000)

External interrupt line 19 Connected to the Ethernet Wakeup event

Definition at line 123 of file stm32f10x_exti.h.

#define EXTI_Line2 ((uint32_t)0x00004)

External interrupt line 2

Definition at line 105 of file stm32f10x_exti.h.

#define EXTI_Line3 ((uint32_t)0x00008)

External interrupt line 3

Definition at line 106 of file stm32f10x_exti.h.

#define EXTI_Line4 ((uint32_t)0x00010)

External interrupt line 4

Definition at line 107 of file stm32f10x_exti.h.

#define EXTI_Line5 ((uint32_t)0x00020)

External interrupt line 5

Definition at line 108 of file stm32f10x_exti.h.

#define EXTI_Line6 ((uint32_t)0x00040)

External interrupt line 6

Definition at line 109 of file stm32f10x_exti.h.

#define EXTI_Line7 ((uint32_t)0x00080)

External interrupt line 7

Definition at line 110 of file stm32f10x_exti.h.

#define EXTI_Line8 ((uint32_t)0x00100)

External interrupt line 8

Definition at line 111 of file stm32f10x_exti.h.

Referenced by EXTI9_5_Config(), EXTI9_5_IRQHandler(), and HDMI_CEC_CommandCallBack().

#define EXTI_Line9 ((uint32_t)0x00200)

External interrupt line 9

Definition at line 112 of file stm32f10x_exti.h.

Referenced by EXTI9_5_Config(), and EXTI9_5_IRQHandler().

#define IS_EXTI_LINE ( LINE ) ((((LINE) & (uint32_t)0xFFF00000) == 0x00) && ((LINE) != (uint16_t)0x00))

Definition at line 125 of file stm32f10x_exti.h.

Referenced by EXTI_ClearFlag(), EXTI_ClearITPendingBit(), EXTI_GenerateSWInterrupt(), and EXTI_Init().

#define IS_GET_EXTI_LINE ( LINE )
Value:
(((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \
                            ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \
                            ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \
                            ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \
                            ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \
                            ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \
                            ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \
                            ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \
                            ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \
                            ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19))

Definition at line 126 of file stm32f10x_exti.h.

Referenced by EXTI_GetFlagStatus(), and EXTI_GetITStatus().


STM32F10x Standard Peripherals Firmware Library: EXTI_Exported_Macros

EXTI_Exported_Macros

EXTI


STM32F10x Standard Peripherals Firmware Library: EXTI_Exported_Functions

Functions

EXTI_Exported_Functions

EXTI

Functions

void | EXTI_ClearFlag (uint32_t EXTI_Line)
Clears the EXTI's line pending flags.
void | EXTI_ClearITPendingBit (uint32_t EXTI_Line)
Clears the EXTI's line pending bits.
void | EXTI_DeInit (void)
Deinitializes the EXTI peripheral registers to their default reset values.
void | EXTI_GenerateSWInterrupt (uint32_t EXTI_Line)
Generates a Software interrupt.
FlagStatus | EXTI_GetFlagStatus (uint32_t EXTI_Line)
Checks whether the specified EXTI line flag is set or not.
ITStatus | EXTI_GetITStatus (uint32_t EXTI_Line)
Checks whether the specified EXTI line is asserted or not.
void | EXTI_Init (EXTI_InitTypeDef *EXTI_InitStruct)
Initializes the EXTI peripheral according to the specified parameters in the EXTI_InitStruct.
void | EXTI_StructInit (EXTI_InitTypeDef *EXTI_InitStruct)
Fills each EXTI_InitStruct member with its reset value.

Function Documentation

void EXTI_ClearFlag ( uint32_t EXTI_Line )

Clears the EXTI's line pending flags.

Parameters:
EXTI_Line,: specifies the EXTI lines flags to clear. This parameter can be any combination of EXTI_Linex where x can be (0..19).
Return values:
None

Definition at line 209 of file stm32f10x_exti.c.

References assert_param, EXTI, and IS_EXTI_LINE.

void EXTI_ClearITPendingBit ( uint32_t EXTI_Line )

Clears the EXTI's line pending bits.

Parameters:
EXTI_Line,: specifies the EXTI lines to clear. This parameter can be any combination of EXTI_Linex where x can be (0..19).
Return values:
None

Definition at line 249 of file stm32f10x_exti.c.

References assert_param, EXTI, and IS_EXTI_LINE.

Referenced by EXTI0_IRQHandler(), EXTI15_10_IRQHandler(), EXTI9_5_IRQHandler(), HDMI_CEC_CommandCallBack(), PVD_IRQHandler(), and RTCAlarm_IRQHandler().

void EXTI_DeInit ( void )

Deinitializes the EXTI peripheral registers to their default reset values.

Parameters:
None
Return values:
None

Definition at line 85 of file stm32f10x_exti.c.

References EXTI.

void EXTI_GenerateSWInterrupt ( uint32_t EXTI_Line )

Generates a Software interrupt.

Parameters:
EXTI_Line,: specifies the EXTI lines to be enabled or disabled. This parameter can be any combination of EXTI_Linex where x can be (0..19).
Return values:
None

Definition at line 171 of file stm32f10x_exti.c.

References assert_param, EXTI, and IS_EXTI_LINE.

Referenced by main().

FlagStatus EXTI_GetFlagStatus ( uint32_t EXTI_Line )

Checks whether the specified EXTI line flag is set or not.

Parameters:
EXTI_Line,: specifies the EXTI line flag to check. This parameter can be:

  • EXTI_Linex: External interrupt line x where x(0..19)
Return values:
The new state of EXTI_Line (SET or RESET).

Definition at line 186 of file stm32f10x_exti.c.

References assert_param, EXTI, IS_GET_EXTI_LINE, RESET, and SET.

ITStatus EXTI_GetITStatus ( uint32_t EXTI_Line )

Checks whether the specified EXTI line is asserted or not.

Parameters:
EXTI_Line,: specifies the EXTI line to check. This parameter can be:

  • EXTI_Linex: External interrupt line x where x(0..19)
Return values:
The new state of EXTI_Line (SET or RESET).

Definition at line 224 of file stm32f10x_exti.c.

References assert_param, EXTI, IS_GET_EXTI_LINE, RESET, and SET.

Referenced by EXTI0_IRQHandler(), EXTI15_10_IRQHandler(), EXTI9_5_IRQHandler(), and PVD_IRQHandler().

void EXTI_Init ( EXTI_InitTypeDef * EXTI_InitStruct )

Initializes the EXTI peripheral according to the specified parameters in the EXTI_InitStruct.

Parameters:
EXTI_InitStruct,: pointer to a EXTI_InitTypeDef structure that contains the configuration information for the EXTI peripheral.
Return values:
None

Definition at line 101 of file stm32f10x_exti.c.

References assert_param, DISABLE, EXTI, EXTI_BASE, EXTI_InitTypeDef::EXTI_Line, EXTI_InitTypeDef::EXTI_LineCmd, EXTI_InitTypeDef::EXTI_Mode, EXTI_InitTypeDef::EXTI_Trigger, EXTI_Trigger_Rising_Falling, IS_EXTI_LINE, IS_EXTI_MODE, IS_EXTI_TRIGGER, and IS_FUNCTIONAL_STATE.

Referenced by EXTI0_Config(), EXTI9_5_Config(), EXTI_Configuration(), HDMI_CEC_CommandCallBack(), IOE_EXTI_Config(), and STM_EVAL_PBInit().

void EXTI_StructInit ( EXTI_InitTypeDef * EXTI_InitStruct )

Fills each EXTI_InitStruct member with its reset value.

Parameters:
EXTI_InitStruct,: pointer to a EXTI_InitTypeDef structure which will be initialized.
Return values:
None

Definition at line 157 of file stm32f10x_exti.c.

References DISABLE, EXTI_InitTypeDef::EXTI_Line, EXTI_InitTypeDef::EXTI_LineCmd, EXTI_LINENONE, EXTI_InitTypeDef::EXTI_Mode, EXTI_Mode_Interrupt, EXTI_InitTypeDef::EXTI_Trigger, and EXTI_Trigger_Falling.


STM32F10x Standard Peripherals Firmware Library: EXTI_Private_TypesDefinitions

EXTI_Private_TypesDefinitions

EXTI


STM32F10x Standard Peripherals Firmware Library: EXTI_Private_Defines

Defines

EXTI_Private_Defines

EXTI

Defines

#define EXTI_LINENONE ((uint32_t)0x00000)

Define Documentation

#define EXTI_LINENONE ((uint32_t)0x00000)

Definition at line 46 of file stm32f10x_exti.c.

Referenced by EXTI_StructInit().


STM32F10x Standard Peripherals Firmware Library: EXTI_Private_Macros

EXTI_Private_Macros

EXTI


STM32F10x Standard Peripherals Firmware Library: EXTI_Private_Variables

EXTI_Private_Variables

EXTI


STM32F10x Standard Peripherals Firmware Library: EXTI_Private_FunctionPrototypes

EXTI_Private_FunctionPrototypes

EXTI


STM32F10x Standard Peripherals Firmware Library: EXTI_Private_Functions

Functions

EXTI_Private_Functions

EXTI

Functions

void | EXTI_ClearFlag (uint32_t EXTI_Line)
Clears the EXTI's line pending flags.
void | EXTI_ClearITPendingBit (uint32_t EXTI_Line)
Clears the EXTI's line pending bits.
void | EXTI_DeInit (void)
Deinitializes the EXTI peripheral registers to their default reset values.
void | EXTI_GenerateSWInterrupt (uint32_t EXTI_Line)
Generates a Software interrupt.
FlagStatus | EXTI_GetFlagStatus (uint32_t EXTI_Line)
Checks whether the specified EXTI line flag is set or not.
ITStatus | EXTI_GetITStatus (uint32_t EXTI_Line)
Checks whether the specified EXTI line is asserted or not.
void | EXTI_Init (EXTI_InitTypeDef *EXTI_InitStruct)
Initializes the EXTI peripheral according to the specified parameters in the EXTI_InitStruct.
void | EXTI_StructInit (EXTI_InitTypeDef *EXTI_InitStruct)
Fills each EXTI_InitStruct member with its reset value.

Function Documentation

void EXTI_ClearFlag ( uint32_t EXTI_Line )

Clears the EXTI's line pending flags.

Parameters:
EXTI_Line,: specifies the EXTI lines flags to clear. This parameter can be any combination of EXTI_Linex where x can be (0..19).
Return values:
None

Definition at line 209 of file stm32f10x_exti.c.

References assert_param, EXTI, and IS_EXTI_LINE.

void EXTI_ClearITPendingBit ( uint32_t EXTI_Line )

Clears the EXTI's line pending bits.

Parameters:
EXTI_Line,: specifies the EXTI lines to clear. This parameter can be any combination of EXTI_Linex where x can be (0..19).
Return values:
None

Definition at line 249 of file stm32f10x_exti.c.

References assert_param, EXTI, and IS_EXTI_LINE.

Referenced by EXTI0_IRQHandler(), EXTI15_10_IRQHandler(), EXTI9_5_IRQHandler(), HDMI_CEC_CommandCallBack(), PVD_IRQHandler(), and RTCAlarm_IRQHandler().

void EXTI_DeInit ( void )

Deinitializes the EXTI peripheral registers to their default reset values.

Parameters:
None
Return values:
None

Definition at line 85 of file stm32f10x_exti.c.

References EXTI.

void EXTI_GenerateSWInterrupt ( uint32_t EXTI_Line )

Generates a Software interrupt.

Parameters:
EXTI_Line,: specifies the EXTI lines to be enabled or disabled. This parameter can be any combination of EXTI_Linex where x can be (0..19).
Return values:
None

Definition at line 171 of file stm32f10x_exti.c.

References assert_param, EXTI, and IS_EXTI_LINE.

Referenced by main().

FlagStatus EXTI_GetFlagStatus ( uint32_t EXTI_Line )

Checks whether the specified EXTI line flag is set or not.

Parameters:
EXTI_Line,: specifies the EXTI line flag to check. This parameter can be:

  • EXTI_Linex: External interrupt line x where x(0..19)
Return values:
The new state of EXTI_Line (SET or RESET).

Definition at line 186 of file stm32f10x_exti.c.

References assert_param, EXTI, IS_GET_EXTI_LINE, RESET, and SET.

ITStatus EXTI_GetITStatus ( uint32_t EXTI_Line )

Checks whether the specified EXTI line is asserted or not.

Parameters:
EXTI_Line,: specifies the EXTI line to check. This parameter can be:

  • EXTI_Linex: External interrupt line x where x(0..19)
Return values:
The new state of EXTI_Line (SET or RESET).

Definition at line 224 of file stm32f10x_exti.c.

References assert_param, EXTI, IS_GET_EXTI_LINE, RESET, and SET.

Referenced by EXTI0_IRQHandler(), EXTI15_10_IRQHandler(), EXTI9_5_IRQHandler(), and PVD_IRQHandler().

void EXTI_Init ( EXTI_InitTypeDef * EXTI_InitStruct )

Initializes the EXTI peripheral according to the specified parameters in the EXTI_InitStruct.

Parameters:
EXTI_InitStruct,: pointer to a EXTI_InitTypeDef structure that contains the configuration information for the EXTI peripheral.
Return values:
None

Definition at line 101 of file stm32f10x_exti.c.

References assert_param, DISABLE, EXTI, EXTI_BASE, EXTI_InitTypeDef::EXTI_Line, EXTI_InitTypeDef::EXTI_LineCmd, EXTI_InitTypeDef::EXTI_Mode, EXTI_InitTypeDef::EXTI_Trigger, EXTI_Trigger_Rising_Falling, IS_EXTI_LINE, IS_EXTI_MODE, IS_EXTI_TRIGGER, and IS_FUNCTIONAL_STATE.

Referenced by EXTI0_Config(), EXTI9_5_Config(), EXTI_Configuration(), HDMI_CEC_CommandCallBack(), IOE_EXTI_Config(), and STM_EVAL_PBInit().

void EXTI_StructInit ( EXTI_InitTypeDef * EXTI_InitStruct )

Fills each EXTI_InitStruct member with its reset value.

Parameters:
EXTI_InitStruct,: pointer to a EXTI_InitTypeDef structure which will be initialized.
Return values:
None

Definition at line 157 of file stm32f10x_exti.c.

References DISABLE, EXTI_InitTypeDef::EXTI_Line, EXTI_InitTypeDef::EXTI_LineCmd, EXTI_LINENONE, EXTI_InitTypeDef::EXTI_Mode, EXTI_Mode_Interrupt, EXTI_InitTypeDef::EXTI_Trigger, and EXTI_Trigger_Falling.


STM32F10x Standard Peripherals Firmware Library: FLASH_Exported_Types

Enumerations

FLASH_Exported_Types

FLASH

Enumerations

enum FLASH_Status {
FLASH_BUSY = 1, FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE,
FLASH_TIMEOUT
}

FLASH Status.

More...

Enumeration Type Documentation

enum FLASH_Status

FLASH Status.

Enumerator:
FLASH_BUSY
FLASH_ERROR_PG
FLASH_ERROR_WRP
FLASH_COMPLETE
FLASH_TIMEOUT

Definition at line 50 of file stm32f10x_flash.h.


STM32F10x Standard Peripherals Firmware Library: Flash_Latency

Defines

Flash_Latency

FLASH_Exported_Constants

Defines

#define | FLASH_Latency_0 ((uint32_t)0x00000000)
#define | FLASH_Latency_1 ((uint32_t)0x00000001)
#define | FLASH_Latency_2 ((uint32_t)0x00000002)
#define | IS_FLASH_LATENCY(LATENCY)

Define Documentation

#define FLASH_Latency_0 ((uint32_t)0x00000000)

FLASH Zero Latency cycle

Definition at line 71 of file stm32f10x_flash.h.

Referenced by SetSysClockTo24(), and SetSysClockToHSE().

#define FLASH_Latency_1 ((uint32_t)0x00000001)

FLASH One Latency cycle

Definition at line 72 of file stm32f10x_flash.h.

Referenced by SetSysClockTo36(), SetSysClockTo48(), and SetSysClockToHSE().

#define FLASH_Latency_2 ((uint32_t)0x00000002)

FLASH Two Latency cycles

Definition at line 73 of file stm32f10x_flash.h.

Referenced by SetSysClockTo56(), and SetSysClockTo72().

#define IS_FLASH_LATENCY ( LATENCY )
Value:
(((LATENCY) == FLASH_Latency_0) || \
                                   ((LATENCY) == FLASH_Latency_1) || \
                                   ((LATENCY) == FLASH_Latency_2))

Definition at line 74 of file stm32f10x_flash.h.

Referenced by FLASH_SetLatency().


STM32F10x Standard Peripherals Firmware Library: Half_Cycle_Enable_Disable

Defines

Half_Cycle_Enable_Disable

FLASH_Exported_Constants

Defines

#define | FLASH_HalfCycleAccess_Disable ((uint32_t)0x00000000)
#define | FLASH_HalfCycleAccess_Enable ((uint32_t)0x00000008)
#define | IS_FLASH_HALFCYCLEACCESS_STATE(STATE)

Define Documentation

#define FLASH_HalfCycleAccess_Disable ((uint32_t)0x00000000)

FLASH Half Cycle Disable

Definition at line 86 of file stm32f10x_flash.h.

#define FLASH_HalfCycleAccess_Enable ((uint32_t)0x00000008)

FLASH Half Cycle Enable

Definition at line 85 of file stm32f10x_flash.h.

#define IS_FLASH_HALFCYCLEACCESS_STATE ( STATE )
Value:
(((STATE) == FLASH_HalfCycleAccess_Enable) || \
                                               ((STATE) == FLASH_HalfCycleAccess_Disable))

Definition at line 87 of file stm32f10x_flash.h.

Referenced by FLASH_HalfCycleAccessCmd().


STM32F10x Standard Peripherals Firmware Library: Prefetch_Buffer_Enable_Disable

Defines

Prefetch_Buffer_Enable_Disable

FLASH_Exported_Constants

Defines

#define | FLASH_PrefetchBuffer_Disable ((uint32_t)0x00000000)
#define | FLASH_PrefetchBuffer_Enable ((uint32_t)0x00000010)
#define | IS_FLASH_PREFETCHBUFFER_STATE(STATE)

Define Documentation

#define FLASH_PrefetchBuffer_Disable ((uint32_t)0x00000000)

FLASH Prefetch Buffer Disable

Definition at line 98 of file stm32f10x_flash.h.

#define FLASH_PrefetchBuffer_Enable ((uint32_t)0x00000010)

FLASH Prefetch Buffer Enable

Definition at line 97 of file stm32f10x_flash.h.

Referenced by SetSysClockTo24(), SetSysClockTo36(), SetSysClockTo48(), SetSysClockTo56(), SetSysClockTo72(), and SetSysClockToHSE().

#define IS_FLASH_PREFETCHBUFFER_STATE ( STATE )
Value:
(((STATE) == FLASH_PrefetchBuffer_Enable) || \
                                              ((STATE) == FLASH_PrefetchBuffer_Disable))

Definition at line 99 of file stm32f10x_flash.h.

Referenced by FLASH_PrefetchBufferCmd().


STM32F10x Standard Peripherals Firmware Library: Option_Bytes_Write_Protection

Defines

Option_Bytes_Write_Protection

FLASH_Exported_Constants

Defines

#define | FLASH_WRProt_AllPages ((uint32_t)0xFFFFFFFF)
#define | FLASH_WRProt_Pages0to1 ((uint32_t)0x00000001)
#define | FLASH_WRProt_Pages0to3 ((uint32_t)0x00000001)
#define | FLASH_WRProt_Pages100to103 ((uint32_t)0x02000000)
#define | FLASH_WRProt_Pages104to107 ((uint32_t)0x04000000)
#define | FLASH_WRProt_Pages108to111 ((uint32_t)0x08000000)
#define | FLASH_WRProt_Pages10to11 ((uint32_t)0x00000020)
#define | FLASH_WRProt_Pages112to115 ((uint32_t)0x10000000)
#define | FLASH_WRProt_Pages116to119 ((uint32_t)0x20000000)
#define | FLASH_WRProt_Pages120to123 ((uint32_t)0x40000000)
#define | FLASH_WRProt_Pages124to127 ((uint32_t)0x80000000)
#define | FLASH_WRProt_Pages12to13 ((uint32_t)0x00000040)
#define | FLASH_WRProt_Pages12to15 ((uint32_t)0x00000008)
#define | FLASH_WRProt_Pages14to15 ((uint32_t)0x00000080)
#define | FLASH_WRProt_Pages16to17 ((uint32_t)0x00000100)
#define | FLASH_WRProt_Pages16to19 ((uint32_t)0x00000010)
#define | FLASH_WRProt_Pages18to19 ((uint32_t)0x00000200)
#define | FLASH_WRProt_Pages20to21 ((uint32_t)0x00000400)
#define | FLASH_WRProt_Pages20to23 ((uint32_t)0x00000020)
#define | FLASH_WRProt_Pages22to23 ((uint32_t)0x00000800)
#define | FLASH_WRProt_Pages24to25 ((uint32_t)0x00001000)
#define | FLASH_WRProt_Pages24to27 ((uint32_t)0x00000040)
#define | FLASH_WRProt_Pages26to27 ((uint32_t)0x00002000)
#define | FLASH_WRProt_Pages28to29 ((uint32_t)0x00004000)
#define | FLASH_WRProt_Pages28to31 ((uint32_t)0x00000080)
#define | FLASH_WRProt_Pages2to3 ((uint32_t)0x00000002)
#define | FLASH_WRProt_Pages30to31 ((uint32_t)0x00008000)
#define | FLASH_WRProt_Pages32to33 ((uint32_t)0x00010000)
#define | FLASH_WRProt_Pages32to35 ((uint32_t)0x00000100)
#define | FLASH_WRProt_Pages34to35 ((uint32_t)0x00020000)
#define | FLASH_WRProt_Pages36to37 ((uint32_t)0x00040000)
#define | FLASH_WRProt_Pages36to39 ((uint32_t)0x00000200)
#define | FLASH_WRProt_Pages38to39 ((uint32_t)0x00080000)
#define | FLASH_WRProt_Pages40to41 ((uint32_t)0x00100000)
#define | FLASH_WRProt_Pages40to43 ((uint32_t)0x00000400)
#define | FLASH_WRProt_Pages42to43 ((uint32_t)0x00200000)
#define | FLASH_WRProt_Pages44to45 ((uint32_t)0x00400000)
#define | FLASH_WRProt_Pages44to47 ((uint32_t)0x00000800)
#define | FLASH_WRProt_Pages46to47 ((uint32_t)0x00800000)
#define | FLASH_WRProt_Pages48to49 ((uint32_t)0x01000000)
#define | FLASH_WRProt_Pages48to51 ((uint32_t)0x00001000)
#define | FLASH_WRProt_Pages4to5 ((uint32_t)0x00000004)
#define | FLASH_WRProt_Pages4to7 ((uint32_t)0x00000002)
#define | FLASH_WRProt_Pages50to51 ((uint32_t)0x02000000)
#define | FLASH_WRProt_Pages52to53 ((uint32_t)0x04000000)
#define | FLASH_WRProt_Pages52to55 ((uint32_t)0x00002000)
#define | FLASH_WRProt_Pages54to55 ((uint32_t)0x08000000)
#define | FLASH_WRProt_Pages56to57 ((uint32_t)0x10000000)
#define | FLASH_WRProt_Pages56to59 ((uint32_t)0x00004000)
#define | FLASH_WRProt_Pages58to59 ((uint32_t)0x20000000)
#define | FLASH_WRProt_Pages60to61 ((uint32_t)0x40000000)
#define | FLASH_WRProt_Pages60to63 ((uint32_t)0x00008000)
#define | FLASH_WRProt_Pages62to127 ((uint32_t)0x80000000)
#define | FLASH_WRProt_Pages62to255 ((uint32_t)0x80000000)
#define | FLASH_WRProt_Pages62to511 ((uint32_t)0x80000000)
#define | FLASH_WRProt_Pages64to67 ((uint32_t)0x00010000)
#define | FLASH_WRProt_Pages68to71 ((uint32_t)0x00020000)
#define | FLASH_WRProt_Pages6to7 ((uint32_t)0x00000008)
#define | FLASH_WRProt_Pages72to75 ((uint32_t)0x00040000)
#define | FLASH_WRProt_Pages76to79 ((uint32_t)0x00080000)
#define | FLASH_WRProt_Pages80to83 ((uint32_t)0x00100000)
#define | FLASH_WRProt_Pages84to87 ((uint32_t)0x00200000)
#define | FLASH_WRProt_Pages88to91 ((uint32_t)0x00400000)
#define | FLASH_WRProt_Pages8to11 ((uint32_t)0x00000004)
#define | FLASH_WRProt_Pages8to9 ((uint32_t)0x00000010)
#define | FLASH_WRProt_Pages92to95 ((uint32_t)0x00800000)
#define | FLASH_WRProt_Pages96to99 ((uint32_t)0x01000000)
#define | IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x080FFFFF))
#define | IS_FLASH_WRPROT_PAGE(PAGE) (((PAGE) != 0x00000000))
#define | IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == 0x1FFFF804) || ((ADDRESS) == 0x1FFFF806))

Define Documentation

#define FLASH_WRProt_AllPages ((uint32_t)0xFFFFFFFF)

Write protection of all Pages

Definition at line 212 of file stm32f10x_flash.h.

#define FLASH_WRProt_Pages0to1 ((uint32_t)0x00000001)

STM32 High-density, XL-density and Connectivity line devices: Write protection of page 0 to 1

Definition at line 146 of file stm32f10x_flash.h.

#define FLASH_WRProt_Pages0to3 ((uint32_t)0x00000001)

STM32 Low and Medium density devices: Write protection of page 0 to 3

Definition at line 110 of file stm32f10x_flash.h.

#define FLASH_WRProt_Pages100to103 ((uint32_t)0x02000000)

STM32 Medium-density devices: Write protection of page 100 to 103

Definition at line 137 of file stm32f10x_flash.h.

#define FLASH_WRProt_Pages104to107 ((uint32_t)0x04000000)

STM32 Medium-density devices: Write protection of page 104 to 107

Definition at line 138 of file stm32f10x_flash.h.

#define FLASH_WRProt_Pages108to111 ((uint32_t)0x08000000)

STM32 Medium-density devices: Write protection of page 108 to 111

Definition at line 139 of file stm32f10x_flash.h.

#define FLASH_WRProt_Pages10to11 ((uint32_t)0x00000020)

STM32 High-density, XL-density and Connectivity line devices: Write protection of page 10 to 11

Definition at line 156 of file stm32f10x_flash.h.

#define FLASH_WRProt_Pages112to115 ((uint32_t)0x10000000)

STM32 Medium-density devices: Write protection of page 112 to 115

Definition at line 140 of file stm32f10x_flash.h.

#define FLASH_WRProt_Pages116to119 ((uint32_t)0x20000000)

STM32 Medium-density devices: Write protection of page 115 to 119

Definition at line 141 of file stm32f10x_flash.h.

#define FLASH_WRProt_Pages120to123 ((uint32_t)0x40000000)

STM32 Medium-density devices: Write protection of page 120 to 123

Definition at line 142 of file stm32f10x_flash.h.

#define FLASH_WRProt_Pages124to127 ((uint32_t)0x80000000)

STM32 Medium-density devices: Write protection of page 124 to 127

Definition at line 143 of file stm32f10x_flash.h.

#define FLASH_WRProt_Pages12to13 ((uint32_t)0x00000040)

STM32 High-density, XL-density and Connectivity line devices: Write protection of page 12 to 13

Definition at line 158 of file stm32f10x_flash.h.

#define FLASH_WRProt_Pages12to15 ((uint32_t)0x00000008)

STM32 Low and Medium density devices: Write protection of page 12 to 15

Definition at line 113 of file stm32f10x_flash.h.

#define FLASH_WRProt_Pages14to15 ((uint32_t)0x00000080)

STM32 High-density, XL-density and Connectivity line devices: Write protection of page 14 to 15

Definition at line 160 of file stm32f10x_flash.h.

#define FLASH_WRProt_Pages16to17 ((uint32_t)0x00000100)

STM32 High-density, XL-density and Connectivity line devices: Write protection of page 16 to 17

Definition at line 162 of file stm32f10x_flash.h.

#define FLASH_WRProt_Pages16to19 ((uint32_t)0x00000010)

STM32 Low and Medium density devices: Write protection of page 16 to 19

Definition at line 114 of file stm32f10x_flash.h.

#define FLASH_WRProt_Pages18to19 ((uint32_t)0x00000200)

STM32 High-density, XL-density and Connectivity line devices: Write protection of page 18 to 19

Definition at line 164 of file stm32f10x_flash.h.

#define FLASH_WRProt_Pages20to21 ((uint32_t)0x00000400)

STM32 High-density, XL-density and Connectivity line devices: Write protection of page 20 to 21

Definition at line 166 of file stm32f10x_flash.h.

#define FLASH_WRProt_Pages20to23 ((uint32_t)0x00000020)

STM32 Low and Medium density devices: Write protection of page 20 to 23

Definition at line 115 of file stm32f10x_flash.h.

#define FLASH_WRProt_Pages22to23 ((uint32_t)0x00000800)

STM32 High-density, XL-density and Connectivity line devices: Write protection of page 22 to 23

Definition at line 168 of file stm32f10x_flash.h.

#define FLASH_WRProt_Pages24to25 ((uint32_t)0x00001000)

STM32 High-density, XL-density and Connectivity line devices: Write protection of page 24 to 25

Definition at line 170 of file stm32f10x_flash.h.

#define FLASH_WRProt_Pages24to27 ((uint32_t)0x00000040)

STM32 Low and Medium density devices: Write protection of page 24 to 27

Definition at line 116 of file stm32f10x_flash.h.

#define FLASH_WRProt_Pages26to27 ((uint32_t)0x00002000)

STM32 High-density, XL-density and Connectivity line devices: Write protection of page 26 to 27

Definition at line 172 of file stm32f10x_flash.h.

#define FLASH_WRProt_Pages28to29 ((uint32_t)0x00004000)

STM32 High-density, XL-density and Connectivity line devices: Write protection of page 28 to 29

Definition at line 174 of file stm32f10x_flash.h.

#define FLASH_WRProt_Pages28to31 ((uint32_t)0x00000080)

STM32 Low and Medium density devices: Write protection of page 28 to 31

Definition at line 117 of file stm32f10x_flash.h.

#define FLASH_WRProt_Pages2to3 ((uint32_t)0x00000002)

STM32 High-density, XL-density and Connectivity line devices: Write protection of page 2 to 3

Definition at line 148 of file stm32f10x_flash.h.

#define FLASH_WRProt_Pages30to31 ((uint32_t)0x00008000)

STM32 High-density, XL-density and Connectivity line devices: Write protection of page 30 to 31

Definition at line 176 of file stm32f10x_flash.h.

#define FLASH_WRProt_Pages32to33 ((uint32_t)0x00010000)

STM32 High-density, XL-density and Connectivity line devices: Write protection of page 32 to 33

Definition at line 178 of file stm32f10x_flash.h.

#define FLASH_WRProt_Pages32to35 ((uint32_t)0x00000100)

STM32 Medium-density devices: Write protection of page 32 to 35

Definition at line 120 of file stm32f10x_flash.h.

#define FLASH_WRProt_Pages34to35 ((uint32_t)0x00020000)

STM32 High-density, XL-density and Connectivity line devices: Write protection of page 34 to 35

Definition at line 180 of file stm32f10x_flash.h.

#define FLASH_WRProt_Pages36to37 ((uint32_t)0x00040000)

STM32 High-density, XL-density and Connectivity line devices: Write protection of page 36 to 37

Definition at line 182 of file stm32f10x_flash.h.

#define FLASH_WRProt_Pages36to39 ((uint32_t)0x00000200)

STM32 Medium-density devices: Write protection of page 36 to 39

Definition at line 121 of file stm32f10x_flash.h.

#define FLASH_WRProt_Pages38to39 ((uint32_t)0x00080000)

STM32 High-density, XL-density and Connectivity line devices: Write protection of page 38 to 39

Definition at line 184 of file stm32f10x_flash.h.

#define FLASH_WRProt_Pages40to41 ((uint32_t)0x00100000)

STM32 High-density, XL-density and Connectivity line devices: Write protection of page 40 to 41

Definition at line 186 of file stm32f10x_flash.h.

#define FLASH_WRProt_Pages40to43 ((uint32_t)0x00000400)

STM32 Medium-density devices: Write protection of page 40 to 43

Definition at line 122 of file stm32f10x_flash.h.

#define FLASH_WRProt_Pages42to43 ((uint32_t)0x00200000)

STM32 High-density, XL-density and Connectivity line devices: Write protection of page 42 to 43

Definition at line 188 of file stm32f10x_flash.h.

#define FLASH_WRProt_Pages44to45 ((uint32_t)0x00400000)

STM32 High-density, XL-density and Connectivity line devices: Write protection of page 44 to 45

Definition at line 190 of file stm32f10x_flash.h.

#define FLASH_WRProt_Pages44to47 ((uint32_t)0x00000800)

STM32 Medium-density devices: Write protection of page 44 to 47

Definition at line 123 of file stm32f10x_flash.h.

#define FLASH_WRProt_Pages46to47 ((uint32_t)0x00800000)

STM32 High-density, XL-density and Connectivity line devices: Write protection of page 46 to 47

Definition at line 192 of file stm32f10x_flash.h.

#define FLASH_WRProt_Pages48to49 ((uint32_t)0x01000000)

STM32 High-density, XL-density and Connectivity line devices: Write protection of page 48 to 49

Definition at line 194 of file stm32f10x_flash.h.

#define FLASH_WRProt_Pages48to51 ((uint32_t)0x00001000)

STM32 Medium-density devices: Write protection of page 48 to 51

Definition at line 124 of file stm32f10x_flash.h.

#define FLASH_WRProt_Pages4to5 ((uint32_t)0x00000004)

STM32 High-density, XL-density and Connectivity line devices: Write protection of page 4 to 5

Definition at line 150 of file stm32f10x_flash.h.

#define FLASH_WRProt_Pages4to7 ((uint32_t)0x00000002)

STM32 Low and Medium density devices: Write protection of page 4 to 7

Definition at line 111 of file stm32f10x_flash.h.

#define FLASH_WRProt_Pages50to51 ((uint32_t)0x02000000)

STM32 High-density, XL-density and Connectivity line devices: Write protection of page 50 to 51

Definition at line 196 of file stm32f10x_flash.h.

#define FLASH_WRProt_Pages52to53 ((uint32_t)0x04000000)

STM32 High-density, XL-density and Connectivity line devices: Write protection of page 52 to 53

Definition at line 198 of file stm32f10x_flash.h.

#define FLASH_WRProt_Pages52to55 ((uint32_t)0x00002000)

STM32 Medium-density devices: Write protection of page 52 to 55

Definition at line 125 of file stm32f10x_flash.h.

#define FLASH_WRProt_Pages54to55 ((uint32_t)0x08000000)

STM32 High-density, XL-density and Connectivity line devices: Write protection of page 54 to 55

Definition at line 200 of file stm32f10x_flash.h.

#define FLASH_WRProt_Pages56to57 ((uint32_t)0x10000000)

STM32 High-density, XL-density and Connectivity line devices: Write protection of page 56 to 57

Definition at line 202 of file stm32f10x_flash.h.

#define FLASH_WRProt_Pages56to59 ((uint32_t)0x00004000)

STM32 Medium-density devices: Write protection of page 56 to 59

Definition at line 126 of file stm32f10x_flash.h.

#define FLASH_WRProt_Pages58to59 ((uint32_t)0x20000000)

STM32 High-density, XL-density and Connectivity line devices: Write protection of page 58 to 59

Definition at line 204 of file stm32f10x_flash.h.

#define FLASH_WRProt_Pages60to61 ((uint32_t)0x40000000)

STM32 High-density, XL-density and Connectivity line devices: Write protection of page 60 to 61

Definition at line 206 of file stm32f10x_flash.h.

#define FLASH_WRProt_Pages60to63 ((uint32_t)0x00008000)

STM32 Medium-density devices: Write protection of page 60 to 63

Definition at line 127 of file stm32f10x_flash.h.

#define FLASH_WRProt_Pages62to127 ((uint32_t)0x80000000)

STM32 Connectivity line devices: Write protection of page 62 to 127

Definition at line 208 of file stm32f10x_flash.h.

#define FLASH_WRProt_Pages62to255 ((uint32_t)0x80000000)

STM32 Medium-density devices: Write protection of page 62 to 255

Definition at line 209 of file stm32f10x_flash.h.

#define FLASH_WRProt_Pages62to511 ((uint32_t)0x80000000)

STM32 XL-density devices: Write protection of page 62 to 511

Definition at line 210 of file stm32f10x_flash.h.

#define FLASH_WRProt_Pages64to67 ((uint32_t)0x00010000)

STM32 Medium-density devices: Write protection of page 64 to 67

Definition at line 128 of file stm32f10x_flash.h.

#define FLASH_WRProt_Pages68to71 ((uint32_t)0x00020000)

STM32 Medium-density devices: Write protection of page 68 to 71

Definition at line 129 of file stm32f10x_flash.h.

#define FLASH_WRProt_Pages6to7 ((uint32_t)0x00000008)

STM32 High-density, XL-density and Connectivity line devices: Write protection of page 6 to 7

Definition at line 152 of file stm32f10x_flash.h.

#define FLASH_WRProt_Pages72to75 ((uint32_t)0x00040000)

STM32 Medium-density devices: Write protection of page 72 to 75

Definition at line 130 of file stm32f10x_flash.h.

#define FLASH_WRProt_Pages76to79 ((uint32_t)0x00080000)

STM32 Medium-density devices: Write protection of page 76 to 79

Definition at line 131 of file stm32f10x_flash.h.

#define FLASH_WRProt_Pages80to83 ((uint32_t)0x00100000)

STM32 Medium-density devices: Write protection of page 80 to 83

Definition at line 132 of file stm32f10x_flash.h.

#define FLASH_WRProt_Pages84to87 ((uint32_t)0x00200000)

STM32 Medium-density devices: Write protection of page 84 to 87

Definition at line 133 of file stm32f10x_flash.h.

#define FLASH_WRProt_Pages88to91 ((uint32_t)0x00400000)

STM32 Medium-density devices: Write protection of page 88 to 91

Definition at line 134 of file stm32f10x_flash.h.

#define FLASH_WRProt_Pages8to11 ((uint32_t)0x00000004)

STM32 Low and Medium density devices: Write protection of page 8 to 11

Definition at line 112 of file stm32f10x_flash.h.

#define FLASH_WRProt_Pages8to9 ((uint32_t)0x00000010)

STM32 High-density, XL-density and Connectivity line devices: Write protection of page 8 to 9

Definition at line 154 of file stm32f10x_flash.h.

#define FLASH_WRProt_Pages92to95 ((uint32_t)0x00800000)

STM32 Medium-density devices: Write protection of page 92 to 95

Definition at line 135 of file stm32f10x_flash.h.

#define FLASH_WRProt_Pages96to99 ((uint32_t)0x01000000)

STM32 Medium-density devices: Write protection of page 96 to 99

Definition at line 136 of file stm32f10x_flash.h.

#define IS_FLASH_ADDRESS ( ADDRESS ) (((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x080FFFFF))

Definition at line 216 of file stm32f10x_flash.h.

Referenced by FLASH_ErasePage(), FLASH_ProgramHalfWord(), and FLASH_ProgramWord().

#define IS_FLASH_WRPROT_PAGE ( PAGE ) (((PAGE) != 0x00000000))

Definition at line 214 of file stm32f10x_flash.h.

Referenced by FLASH_EnableWriteProtection().

#define IS_OB_DATA_ADDRESS ( ADDRESS ) (((ADDRESS) == 0x1FFFF804) || ((ADDRESS) == 0x1FFFF806))

Definition at line 218 of file stm32f10x_flash.h.

Referenced by FLASH_ProgramOptionByteData().


STM32F10x Standard Peripherals Firmware Library: Option_Bytes_IWatchdog

Defines

Option_Bytes_IWatchdog

FLASH_Exported_Constants

Defines

#define | IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
#define | OB_IWDG_HW ((uint16_t)0x0000)
#define | OB_IWDG_SW ((uint16_t)0x0001)

Define Documentation

#define IS_OB_IWDG_SOURCE ( SOURCE ) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))

Definition at line 230 of file stm32f10x_flash.h.

Referenced by FLASH_UserOptionByteConfig().

#define OB_IWDG_HW ((uint16_t)0x0000)

Hardware IWDG selected

Definition at line 229 of file stm32f10x_flash.h.

#define OB_IWDG_SW ((uint16_t)0x0001)

Software IWDG selected

Definition at line 228 of file stm32f10x_flash.h.


STM32F10x Standard Peripherals Firmware Library: Option_Bytes_nRST_STOP

Defines

Option_Bytes_nRST_STOP

FLASH_Exported_Constants

Defines

#define | IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST))
#define | OB_STOP_NoRST ((uint16_t)0x0002)
#define | OB_STOP_RST ((uint16_t)0x0000)

Define Documentation

#define IS_OB_STOP_SOURCE ( SOURCE ) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST))

Definition at line 242 of file stm32f10x_flash.h.

Referenced by FLASH_UserOptionByteConfig().

#define OB_STOP_NoRST ((uint16_t)0x0002)

No reset generated when entering in STOP

Definition at line 240 of file stm32f10x_flash.h.

#define OB_STOP_RST ((uint16_t)0x0000)

Reset generated when entering in STOP

Definition at line 241 of file stm32f10x_flash.h.


STM32F10x Standard Peripherals Firmware Library: Option_Bytes_nRST_STDBY

Defines

Option_Bytes_nRST_STDBY

FLASH_Exported_Constants

Defines

#define | IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST))
#define | OB_STDBY_NoRST ((uint16_t)0x0004)
#define | OB_STDBY_RST ((uint16_t)0x0000)

Define Documentation

#define IS_OB_STDBY_SOURCE ( SOURCE ) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST))

Definition at line 254 of file stm32f10x_flash.h.

Referenced by FLASH_UserOptionByteConfig().

#define OB_STDBY_NoRST ((uint16_t)0x0004)

No reset generated when entering in STANDBY

Definition at line 252 of file stm32f10x_flash.h.

#define OB_STDBY_RST ((uint16_t)0x0000)

Reset generated when entering in STANDBY

Definition at line 253 of file stm32f10x_flash.h.


STM32F10x Standard Peripherals Firmware Library: FLASH_Interrupts

Defines

FLASH_Interrupts

FLASH_Exported_Constants

Defines

#define | FLASH_IT_BANK1_EOP FLASH_IT_EOP
#define | FLASH_IT_BANK1_ERROR FLASH_IT_ERROR
#define | FLASH_IT_EOP ((uint32_t)0x00001000)
#define | FLASH_IT_ERROR ((uint32_t)0x00000400)
#define | IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFFEBFF) == 0x00000000) && (((IT) != 0x00000000)))

Define Documentation

#define FLASH_IT_BANK1_EOP FLASH_IT_EOP

End of FLASH BANK1 Operation Interrupt source

Definition at line 290 of file stm32f10x_flash.h.

#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR

FPEC BANK1 error interrupt source

Definition at line 289 of file stm32f10x_flash.h.

#define FLASH_IT_EOP ((uint32_t)0x00001000)

End of FLASH Operation Interrupt source

Definition at line 288 of file stm32f10x_flash.h.

#define FLASH_IT_ERROR ((uint32_t)0x00000400)

FPEC error interrupt source

Definition at line 287 of file stm32f10x_flash.h.

#define IS_FLASH_IT ( IT ) ((((IT) & (uint32_t)0xFFFFEBFF) == 0x00000000) && (((IT) != 0x00000000)))

Definition at line 292 of file stm32f10x_flash.h.

Referenced by FLASH_ITConfig().


STM32F10x Standard Peripherals Firmware Library: FLASH_Flags

Defines

FLASH_Flags

FLASH_Exported_Constants

Defines

#define | FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY
#define | FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP
#define | FLASH_FLAG_BANK1_PGERR FLASH_FLAG_PGERR
#define | FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR
#define | FLASH_FLAG_BSY ((uint32_t)0x00000001)
#define | FLASH_FLAG_EOP ((uint32_t)0x00000020)
#define | FLASH_FLAG_OPTERR ((uint32_t)0x00000001)
#define | FLASH_FLAG_PGERR ((uint32_t)0x00000004)
#define | FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010)
#define | IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000))
#define | IS_FLASH_GET_FLAG(FLAG)

Define Documentation

#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY

FLASH BANK1 Busy flag

Definition at line 334 of file stm32f10x_flash.h.

Referenced by FLASH_GetBank1Status(), and FLASH_WaitForLastBank1Operation().

#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP

FLASH BANK1 End of Operation flag

Definition at line 335 of file stm32f10x_flash.h.

#define FLASH_FLAG_BANK1_PGERR FLASH_FLAG_PGERR

FLASH BANK1 Program error flag

Definition at line 336 of file stm32f10x_flash.h.

Referenced by FLASH_GetBank1Status().

#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR

FLASH BANK1 Write protected error flag

Definition at line 337 of file stm32f10x_flash.h.

Referenced by FLASH_GetBank1Status().

#define FLASH_FLAG_BSY ((uint32_t)0x00000001)

FLASH Busy flag

Definition at line 328 of file stm32f10x_flash.h.

Referenced by FLASH_GetBank1Status(), FLASH_GetStatus(), and main().

#define FLASH_FLAG_EOP ((uint32_t)0x00000020)

FLASH End of Operation flag

Definition at line 329 of file stm32f10x_flash.h.

Referenced by main().

#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001)

FLASH Option Byte error flag

Definition at line 332 of file stm32f10x_flash.h.

Referenced by FLASH_GetFlagStatus().

#define FLASH_FLAG_PGERR ((uint32_t)0x00000004)

FLASH Program error flag

Definition at line 330 of file stm32f10x_flash.h.

Referenced by FLASH_GetStatus(), and main().

#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010)

FLASH Write protected error flag

Definition at line 331 of file stm32f10x_flash.h.

Referenced by FLASH_GetStatus(), and main().

#define IS_FLASH_CLEAR_FLAG ( FLAG ) ((((FLAG) & (uint32_t)0xFFFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000))

Definition at line 339 of file stm32f10x_flash.h.

Referenced by FLASH_ClearFlag().

#define IS_FLASH_GET_FLAG ( FLAG )
Value:
(((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \
                                  ((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || \
                                                                  ((FLAG) == FLASH_FLAG_BANK1_BSY) || ((FLAG) == FLASH_FLAG_BANK1_EOP) || \
                                  ((FLAG) == FLASH_FLAG_BANK1_PGERR) || ((FLAG) == FLASH_FLAG_BANK1_WRPRTERR) || \
                                  ((FLAG) == FLASH_FLAG_OPTERR))

Definition at line 340 of file stm32f10x_flash.h.

Referenced by FLASH_GetFlagStatus().


STM32F10x Standard Peripherals Firmware Library: FLASH_Exported_Macros

FLASH_Exported_Macros

FLASH


STM32F10x Standard Peripherals Firmware Library: FLASH_Exported_Functions

Functions

FLASH_Exported_Functions

FLASH

Functions

void | FLASH_ClearFlag (uint32_t FLASH_FLAG)
Clears the FLASH's pending flags.
FLASH_Status | FLASH_EnableWriteProtection (uint32_t FLASH_Pages)
Write protects the desired pages.
FLASH_Status | FLASH_EraseAllBank1Pages (void)
Erases all Bank1 FLASH pages.
FLASH_Status | FLASH_EraseAllPages (void)
Erases all FLASH pages.
FLASH_Status | FLASH_EraseOptionBytes (void)
Erases the FLASH option bytes.
FLASH_Status | FLASH_ErasePage (uint32_t Page_Address)
Erases a specified FLASH page.
FLASH_Status | FLASH_GetBank1Status (void)
Returns the FLASH Bank1 Status.
FlagStatus | FLASH_GetFlagStatus (uint32_t FLASH_FLAG)
Checks whether the specified FLASH flag is set or not.
FlagStatus | FLASH_GetPrefetchBufferStatus (void)
Checks whether the FLASH Prefetch Buffer status is set or not.
FlagStatus | FLASH_GetReadOutProtectionStatus (void)
Checks whether the FLASH Read Out Protection Status is set or not.
FLASH_Status | FLASH_GetStatus (void)
Returns the FLASH Status.
uint32_t | FLASH_GetUserOptionByte (void)
Returns the FLASH User Option Bytes values.
uint32_t | FLASH_GetWriteProtectionOptionByte (void)
Returns the FLASH Write Protection Option Bytes Register value.
void | FLASH_HalfCycleAccessCmd (uint32_t FLASH_HalfCycleAccess)
Enables or disables the Half cycle flash access.
void | FLASH_ITConfig (uint32_t FLASH_IT, FunctionalState NewState)
Enables or disables the specified FLASH interrupts.
void | FLASH_Lock (void)
Locks the FLASH Program Erase Controller.
void | FLASH_LockBank1 (void)
Locks the FLASH Bank1 Program Erase Controller.
void | FLASH_PrefetchBufferCmd (uint32_t FLASH_PrefetchBuffer)
Enables or disables the Prefetch Buffer.
FLASH_Status | FLASH_ProgramHalfWord (uint32_t Address, uint16_t Data)
Programs a half word at a specified address.
FLASH_Status | FLASH_ProgramOptionByteData (uint32_t Address, uint8_t Data)
Programs a half word at a specified Option Byte Data address.
FLASH_Status | FLASH_ProgramWord (uint32_t Address, uint32_t Data)
Programs a word at a specified address.
FLASH_Status | FLASH_ReadOutProtection (FunctionalState NewState)
Enables or disables the read out protection.
void | FLASH_SetLatency (uint32_t FLASH_Latency)
Sets the code latency value.
void | FLASH_Unlock (void)
Unlocks the FLASH Program Erase Controller.
void | FLASH_UnlockBank1 (void)
Unlocks the FLASH Bank1 Program Erase Controller.
FLASH_Status | FLASH_UserOptionByteConfig (uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY)
Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
FLASH_Status | FLASH_WaitForLastBank1Operation (uint32_t Timeout)
Waits for a Flash operation on Bank1 to complete or a TIMEOUT to occur.
FLASH_Status | FLASH_WaitForLastOperation (uint32_t Timeout)
Waits for a Flash operation to complete or a TIMEOUT to occur.

Function Documentation

void FLASH_ClearFlag ( uint32_t FLASH_FLAG )

Clears the FLASH's pending flags.

Note:
This function can be used for all STM32F10x devices.
  • For STM32F10X_XL devices, this function clears Bank1 or Bank2’s pending flags
  • For other devices, it clears Bank1’s pending flags.
Parameters:
FLASH_FLAG,: specifies the FLASH flags to clear. This parameter can be any combination of the following values:

  • FLASH_FLAG_PGERR: FLASH Program error flag
  • FLASH_FLAG_WRPRTERR: FLASH Write protected error flag
  • FLASH_FLAG_EOP: FLASH End of Operation flag
Return values:
None

Definition at line 1443 of file stm32f10x_flash.c.

References assert_param, FLASH, and IS_FLASH_CLEAR_FLAG.

Referenced by main().

FLASH_Status FLASH_EnableWriteProtection ( uint32_t FLASH_Pages )

Write protects the desired pages.

Note:
This function can be used for all STM32F10x devices.
Parameters:
FLASH_Pages,: specifies the address of the pages to be write protected. This parameter can be:

  • For STM32_Low-density_devices: value between FLASH_WRProt_Pages0to3 and FLASH_WRProt_Pages28to31
  • For STM32_Medium-density_devices: value between FLASH_WRProt_Pages0to3 and FLASH_WRProt_Pages124to127
  • For STM32_High-density_devices: value between FLASH_WRProt_Pages0to1 and FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to255
  • For STM32_Connectivity_line_devices: value between FLASH_WRProt_Pages0to1 and FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to127
  • For STM32_XL-density_devices: value between FLASH_WRProt_Pages0to1 and FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to511
  • FLASH_WRProt_AllPages
Return values:
FLASH Status: The returned value can be: FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.

Definition at line 975 of file stm32f10x_flash.c.

References assert_param, CR_OPTPG_Reset, CR_OPTPG_Set, FLASH, FLASH_COMPLETE, FLASH_KEY1, FLASH_KEY2, FLASH_TIMEOUT, FLASH_WaitForLastOperation(), IS_FLASH_WRPROT_PAGE, OB, ProgramTimeout, status, WRP0_Mask, WRP1_Mask, WRP2_Mask, and WRP3_Mask.

Referenced by main().

FLASH_Status FLASH_EraseAllBank1Pages ( void )

Erases all Bank1 FLASH pages.

Note:
This function can be used for all STM32F10x devices.
  • For STM32F10X_XL devices this function erases all Bank1 pages.
  • For all other devices it erases all Bank1 pages and it is equivalent to FLASH_EraseAllPages function.
Parameters:
None
Return values:
FLASH Status: The returned value can be: FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.

Definition at line 555 of file stm32f10x_flash.c.

References CR_MER_Reset, CR_MER_Set, CR_STRT_Set, EraseTimeout, FLASH, FLASH_COMPLETE, FLASH_WaitForLastBank1Operation(), and status.

FLASH_Status FLASH_EraseAllPages ( void )

Erases all FLASH pages.

Note:
This function can be used for all STM32F10x devices.
Parameters:
None
Return values:
FLASH Status: The returned value can be: FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.

Definition at line 492 of file stm32f10x_flash.c.

References CR_MER_Reset, CR_MER_Set, CR_STRT_Set, EraseTimeout, FLASH, FLASH_COMPLETE, FLASH_WaitForLastBank1Operation(), FLASH_WaitForLastOperation(), and status.

FLASH_Status FLASH_EraseOptionBytes ( void )

Erases the FLASH option bytes.

Note:
This functions erases all option bytes except the Read protection (RDP).
This function can be used for all STM32F10x devices.
Parameters:
None
Return values:
FLASH Status: The returned value can be: FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.

Definition at line 616 of file stm32f10x_flash.c.

References CR_OPTER_Reset, CR_OPTER_Set, CR_OPTPG_Reset, CR_OPTPG_Set, CR_STRT_Set, EraseTimeout, FLASH, FLASH_COMPLETE, FLASH_GetReadOutProtectionStatus(), FLASH_KEY1, FLASH_KEY2, FLASH_TIMEOUT, FLASH_WaitForLastOperation(), OB, ProgramTimeout, RDP_Key, RESET, and status.

Referenced by main().

FLASH_Status FLASH_ErasePage ( uint32_t Page_Address )

Erases a specified FLASH page.

Note:
This function can be used for all STM32F10x devices.
Parameters:
Page_Address,: The page address to be erased.
Return values:
FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.

Definition at line 419 of file stm32f10x_flash.c.

References assert_param, CR_PER_Reset, CR_PER_Set, CR_STRT_Set, EraseTimeout, FLASH, FLASH_BANK1_END_ADDRESS, FLASH_COMPLETE, FLASH_WaitForLastBank1Operation(), FLASH_WaitForLastOperation(), IS_FLASH_ADDRESS, and status.

Referenced by main().

FLASH_Status FLASH_GetBank1Status ( void )

Returns the FLASH Bank1 Status.

Note:
This function can be used for all STM32F10x devices, it is equivalent to FLASH_GetStatus function.
Parameters:
None
Return values:
FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, FLASH_ERROR_WRP or FLASH_COMPLETE

Definition at line 1515 of file stm32f10x_flash.c.

References FLASH, FLASH_BUSY, FLASH_COMPLETE, FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_FLAG_BANK1_BSY, FLASH_FLAG_BANK1_PGERR, FLASH_FLAG_BANK1_WRPRTERR, and FLASH_FLAG_BSY.

Referenced by FLASH_WaitForLastBank1Operation(), and FLASH_WaitForLastOperation().

FlagStatus FLASH_GetFlagStatus ( uint32_t FLASH_FLAG )

Checks whether the specified FLASH flag is set or not.

Note:
This function can be used for all STM32F10x devices.
  • For STM32F10X_XL devices, this function checks whether the specified Bank1 or Bank2 flag is set or not.
  • For other devices, it checks whether the specified Bank1 flag is set or not.
Parameters:
FLASH_FLAG,: specifies the FLASH flag to check. This parameter can be one of the following values:

  • FLASH_FLAG_BSY: FLASH Busy flag
  • FLASH_FLAG_PGERR: FLASH Program error flag
  • FLASH_FLAG_WRPRTERR: FLASH Write protected error flag
  • FLASH_FLAG_EOP: FLASH End of Operation flag
  • FLASH_FLAG_OPTERR: FLASH Option Byte error flag
Return values:
The new state of FLASH_FLAG (SET or RESET).

Definition at line 1357 of file stm32f10x_flash.c.

References assert_param, FLASH, FLASH_FLAG_OPTERR, IS_FLASH_GET_FLAG, RESET, and SET.

FlagStatus FLASH_GetPrefetchBufferStatus ( void )

Checks whether the FLASH Prefetch Buffer status is set or not.

Note:
This function can be used for all STM32F10x devices.
Parameters:
None
Return values:
FLASH Prefetch Buffer Status (SET or RESET).

Definition at line 1260 of file stm32f10x_flash.c.

References ACR_PRFTBS_Mask, FLASH, RESET, and SET.

FlagStatus FLASH_GetReadOutProtectionStatus ( void )

Checks whether the FLASH Read Out Protection Status is set or not.

Note:
This function can be used for all STM32F10x devices.
Parameters:
None
Return values:
FLASH ReadOut Protection Status(SET or RESET)

Definition at line 1240 of file stm32f10x_flash.c.

References FLASH, RDPRT_Mask, RESET, and SET.

Referenced by FLASH_EraseOptionBytes().

FLASH_Status FLASH_GetStatus ( void )

Returns the FLASH Status.

Note:
This function can be used for all STM32F10x devices, it is equivalent to FLASH_GetBank1Status function.
Parameters:
None
Return values:
FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, FLASH_ERROR_WRP or FLASH_COMPLETE

Definition at line 1477 of file stm32f10x_flash.c.

References FLASH, FLASH_BUSY, FLASH_COMPLETE, FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_FLAG_BSY, FLASH_FLAG_PGERR, and FLASH_FLAG_WRPRTERR.

uint32_t FLASH_GetUserOptionByte ( void )

Returns the FLASH User Option Bytes values.

Note:
This function can be used for all STM32F10x devices.
Parameters:
None
Return values:
The FLASH User Option Bytes values:IWDG_SW(Bit0), RST_STOP(Bit1) and RST_STDBY(Bit2).

Definition at line 1216 of file stm32f10x_flash.c.

References FLASH.

uint32_t FLASH_GetWriteProtectionOptionByte ( void )

Returns the FLASH Write Protection Option Bytes Register value.

Note:
This function can be used for all STM32F10x devices.
Parameters:
None
Return values:
The FLASH Write Protection Option Bytes Register value

Definition at line 1228 of file stm32f10x_flash.c.

References FLASH.

Referenced by main().

void FLASH_HalfCycleAccessCmd ( uint32_t FLASH_HalfCycleAccess )

Enables or disables the Half cycle flash access.

Note:
This function can be used for all STM32F10x devices.
Parameters:
FLASH_HalfCycleAccess,: specifies the FLASH Half cycle Access mode. This parameter can be one of the following values:

  • FLASH_HalfCycleAccess_Enable: FLASH Half Cycle Enable
  • FLASH_HalfCycleAccess_Disable: FLASH Half Cycle Disable
Return values:
None

Definition at line 281 of file stm32f10x_flash.c.

References ACR_HLFCYA_Mask, assert_param, FLASH, and IS_FLASH_HALFCYCLEACCESS_STATE.

void FLASH_ITConfig | ( | uint32_t | FLASH_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified FLASH interrupts.

Note:
This function can be used for all STM32F10x devices.
  • For STM32F10X_XL devices, enables or disables the specified FLASH interrupts for Bank1 and Bank2.
  • For other devices it enables or disables the specified FLASH interrupts for Bank1.
Parameters:
FLASH_IT,: specifies the FLASH interrupt sources to be enabled or disabled. This parameter can be any combination of the following values:

  • FLASH_IT_ERROR: FLASH Error Interrupt
  • FLASH_IT_EOP: FLASH end of operation Interrupt
NewState,: new state of the specified Flash interrupts. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1290 of file stm32f10x_flash.c.

References assert_param, DISABLE, FLASH, IS_FLASH_IT, and IS_FUNCTIONAL_STATE.

void FLASH_Lock ( void )

Locks the FLASH Program Erase Controller.

Note:
This function can be used for all STM32F10x devices.
  • For STM32F10X_XL devices this function Locks Bank1 and Bank2.
  • For all other devices it Locks Bank1 and it is equivalent to FLASH_LockBank1 function.
Parameters:
None
Return values:
None

Definition at line 372 of file stm32f10x_flash.c.

References CR_LOCK_Set, and FLASH.

Referenced by main().

void FLASH_LockBank1 ( void )

Locks the FLASH Bank1 Program Erase Controller.

Note:
this function can be used for all STM32F10x devices.
  • For STM32F10X_XL devices this function Locks Bank1.
  • For all other devices it Locks Bank1 and it is equivalent to FLASH_Lock function.
Parameters:
None
Return values:
None

Definition at line 392 of file stm32f10x_flash.c.

References CR_LOCK_Set, and FLASH.

Referenced by main().

void FLASH_PrefetchBufferCmd ( uint32_t FLASH_PrefetchBuffer )

Enables or disables the Prefetch Buffer.

Note:
This function can be used for all STM32F10x devices.
Parameters:
FLASH_PrefetchBuffer,: specifies the Prefetch buffer status. This parameter can be one of the following values:

  • FLASH_PrefetchBuffer_Enable: FLASH Prefetch Buffer Enable
  • FLASH_PrefetchBuffer_Disable: FLASH Prefetch Buffer Disable
Return values:
None

Definition at line 300 of file stm32f10x_flash.c.

References ACR_PRFTBE_Mask, assert_param, FLASH, and IS_FLASH_PREFETCHBUFFER_STATE.

Referenced by SetSysClockTo24(), SetSysClockTo36(), SetSysClockTo48(), SetSysClockTo56(), SetSysClockTo72(), and SetSysClockToHSE().

FLASH_Status FLASH_ProgramHalfWord | ( | uint32_t | Address,
 |  | uint16_t | Data
 | ) |  |

Programs a half word at a specified address.

Note:
This function can be used for all STM32F10x devices.
Parameters:
Address,: specifies the address to be programmed.
Data,: specifies the data to be programmed.
Return values:
FLASH Status: The returned value can be: FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.

Definition at line 858 of file stm32f10x_flash.c.

References assert_param, CR_PG_Reset, CR_PG_Set, FLASH, FLASH_BANK1_END_ADDRESS, FLASH_COMPLETE, FLASH_WaitForLastBank1Operation(), FLASH_WaitForLastOperation(), IS_FLASH_ADDRESS, ProgramTimeout, and status.

Referenced by main().

FLASH_Status FLASH_ProgramOptionByteData | ( | uint32_t | Address,
 |  | uint8_t | Data
 | ) |  |

Programs a half word at a specified Option Byte Data address.

Note:
This function can be used for all STM32F10x devices.
Parameters:
Address,: specifies the address to be programmed. This parameter can be 0x1FFFF804 or 0x1FFFF806.
Data,: specifies the data to be programmed.
Return values:
FLASH Status: The returned value can be: FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.

Definition at line 929 of file stm32f10x_flash.c.

References assert_param, CR_OPTPG_Reset, CR_OPTPG_Set, FLASH, FLASH_COMPLETE, FLASH_KEY1, FLASH_KEY2, FLASH_TIMEOUT, FLASH_WaitForLastOperation(), IS_OB_DATA_ADDRESS, ProgramTimeout, and status.

FLASH_Status FLASH_ProgramWord | ( | uint32_t | Address,
 |  | uint32_t | Data
 | ) |  |

Programs a word at a specified address.

Note:
This function can be used for all STM32F10x devices.
Parameters:
Address,: specifies the address to be programmed.
Data,: specifies the data to be programmed.
Return values:
FLASH Status: The returned value can be: FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.

Definition at line 681 of file stm32f10x_flash.c.

References assert_param, CR_PG_Reset, CR_PG_Set, Data, FLASH, FLASH_BANK1_END_ADDRESS, FLASH_COMPLETE, FLASH_WaitForLastBank1Operation(), FLASH_WaitForLastOperation(), IS_FLASH_ADDRESS, ProgramTimeout, and status.

Referenced by main().

FLASH_Status FLASH_ReadOutProtection ( FunctionalState NewState )

Enables or disables the read out protection.

Note:
If the user has already programmed the other option bytes before calling this function, he must re-program them since this function erases all option bytes.
This function can be used for all STM32F10x devices.
Parameters:
Newstate,: new state of the ReadOut Protection. This parameter can be: ENABLE or DISABLE.
Return values:
FLASH Status: The returned value can be: FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.

Definition at line 1049 of file stm32f10x_flash.c.

References assert_param, CR_OPTER_Reset, CR_OPTER_Set, CR_OPTPG_Reset, CR_OPTPG_Set, CR_STRT_Set, DISABLE, EraseTimeout, FLASH, FLASH_COMPLETE, FLASH_KEY1, FLASH_KEY2, FLASH_TIMEOUT, FLASH_WaitForLastOperation(), IS_FUNCTIONAL_STATE, OB, RDP_Key, and status.

void FLASH_SetLatency ( uint32_t FLASH_Latency )

Sets the code latency value.

 This driver provides functions to configure and program the Flash memory of all STM32F10x devices,
 including the latest STM32F10x_XL density devices.

 STM32F10x_XL devices feature up to 1 Mbyte with dual bank architecture for read-while-write (RWW) capability:
    - bank1: fixed size of 512 Kbytes (256 pages of 2Kbytes each)
    - bank2: up to 512 Kbytes (up to 256 pages of 2Kbytes each)
 While other STM32F10x devices features only one bank with memory up to 512 Kbytes.

 In version V3.3.0, some functions were updated and new ones were added to support
 STM32F10x_XL devices. Thus some functions manages all devices, while other are
 dedicated for XL devices only.

 The table below presents the list of available functions depending on the used STM32F10x devices.

 Legacy functions used for all STM32F10x devices *

   +----------------------------------------------------------------------------------------------------------------------------------+
   |       Functions prototypes         |STM32F10x_XL|Other STM32F10x|    Comments                                                    |
   |                                    |   devices  |  devices      |                                                                |
   |----------------------------------------------------------------------------------------------------------------------------------|
   |FLASH_SetLatency                    |    Yes     |      Yes      | No change                                                      |
   |----------------------------------------------------------------------------------------------------------------------------------|
   |FLASH_HalfCycleAccessCmd            |    Yes     |      Yes      | No change                                                      |
   |----------------------------------------------------------------------------------------------------------------------------------|
   |FLASH_PrefetchBufferCmd             |    Yes     |      Yes      | No change                                                      |
   |----------------------------------------------------------------------------------------------------------------------------------|
   |FLASH_Unlock                        |    Yes     |      Yes      | - For STM32F10X_XL devices: unlock Bank1 and Bank2.            |
   |                                    |            |               | - For other devices: unlock Bank1 and it is equivalent         |
   |                                    |            |               |   to FLASH_UnlockBank1 function.                               |
   |----------------------------------------------------------------------------------------------------------------------------------|
   |FLASH_Lock                          |    Yes     |      Yes      | - For STM32F10X_XL devices: lock Bank1 and Bank2.              |
   |                                    |            |               | - For other devices: lock Bank1 and it is equivalent           |
   |                                    |            |               |   to FLASH_LockBank1 function.                                 |
   |----------------------------------------------------------------------------------------------------------------------------------|
   |FLASH_ErasePage                     |    Yes     |      Yes      | - For STM32F10x_XL devices: erase a page in Bank1 and Bank2    |
   |                                    |            |               | - For other devices: erase a page in Bank1                     |
   |----------------------------------------------------------------------------------------------------------------------------------|
   |FLASH_EraseAllPages                 |    Yes     |      Yes      | - For STM32F10x_XL devices: erase all pages in Bank1 and Bank2 |
   |                                    |            |               | - For other devices: erase all pages in Bank1                  |
   |----------------------------------------------------------------------------------------------------------------------------------|
   |FLASH_EraseOptionBytes              |    Yes     |      Yes      | No change                                                      |
   |----------------------------------------------------------------------------------------------------------------------------------|
   |FLASH_ProgramWord                   |    Yes     |      Yes      | Updated to program up to 1MByte (depending on the used device) |
   |----------------------------------------------------------------------------------------------------------------------------------|
   |FLASH_ProgramHalfWord               |    Yes     |      Yes      | Updated to program up to 1MByte (depending on the used device) |
   |----------------------------------------------------------------------------------------------------------------------------------|
   |FLASH_ProgramOptionByteData         |    Yes     |      Yes      | No change                                                      |
   |----------------------------------------------------------------------------------------------------------------------------------|
   |FLASH_EnableWriteProtection         |    Yes     |      Yes      | No change                                                      |
   |----------------------------------------------------------------------------------------------------------------------------------|
   |FLASH_ReadOutProtection             |    Yes     |      Yes      | No change                                                      |
   |----------------------------------------------------------------------------------------------------------------------------------|
   |FLASH_UserOptionByteConfig          |    Yes     |      Yes      | No change                                                      |
   |----------------------------------------------------------------------------------------------------------------------------------|
   |FLASH_GetUserOptionByte             |    Yes     |      Yes      | No change                                                      |
   |----------------------------------------------------------------------------------------------------------------------------------|
   |FLASH_GetWriteProtectionOptionByte  |    Yes     |      Yes      | No change                                                      |
   |----------------------------------------------------------------------------------------------------------------------------------|
   |FLASH_GetReadOutProtectionStatus    |    Yes     |      Yes      | No change                                                      |
   |----------------------------------------------------------------------------------------------------------------------------------|
   |FLASH_GetPrefetchBufferStatus       |    Yes     |      Yes      | No change                                                      |
   |----------------------------------------------------------------------------------------------------------------------------------|
   |FLASH_ITConfig                      |    Yes     |      Yes      | - For STM32F10x_XL devices: enable Bank1 and Bank2's interrupts|
   |                                    |            |               | - For other devices: enable Bank1's interrupts                 |
   |----------------------------------------------------------------------------------------------------------------------------------|
   |FLASH_GetFlagStatus                 |    Yes     |      Yes      | - For STM32F10x_XL devices: return Bank1 and Bank2's flag status|
   |                                    |            |               | - For other devices: return Bank1's flag status                |
   |----------------------------------------------------------------------------------------------------------------------------------|
   |FLASH_ClearFlag                     |    Yes     |      Yes      | - For STM32F10x_XL devices: clear Bank1 and Bank2's flag       |
   |                                    |            |               | - For other devices: clear Bank1's flag                        |
   |----------------------------------------------------------------------------------------------------------------------------------|
   |FLASH_GetStatus                     |    Yes     |      Yes      | - Return the status of Bank1 (for all devices)                 |
   |                                    |            |               |   equivalent to FLASH_GetBank1Status function                  |
   |----------------------------------------------------------------------------------------------------------------------------------|
   |FLASH_WaitForLastOperation          |    Yes     |      Yes      | - Wait for Bank1 last operation (for all devices)              |
   |                                    |            |               |   equivalent to: FLASH_WaitForLastBank1Operation function      |
   +----------------------------------------------------------------------------------------------------------------------------------+

 New functions used for all STM32F10x devices to manage Bank1:                                                        *
   - These functions are mainly useful for STM32F10x_XL density devices, to have separate control for Bank1 and bank2 *
   - For other devices, these functions are optional (covered by functions listed above)                              *

   +----------------------------------------------------------------------------------------------------------------------------------+
   |       Functions prototypes         |STM32F10x_XL|Other STM32F10x|    Comments                                                    |
   |                                    |   devices  |  devices      |                                                                |
   |----------------------------------------------------------------------------------------------------------------------------------|
   | FLASH_UnlockBank1                  |    Yes     |      Yes      | - Unlock Bank1                                                 |
   |----------------------------------------------------------------------------------------------------------------------------------|
   |FLASH_LockBank1                     |    Yes     |      Yes      | - Lock Bank1                                                   |
   |----------------------------------------------------------------------------------------------------------------------------------|
   | FLASH_EraseAllBank1Pages           |    Yes     |      Yes      | - Erase all pages in Bank1                                     |
   |----------------------------------------------------------------------------------------------------------------------------------|
   | FLASH_GetBank1Status               |    Yes     |      Yes      | - Return the status of Bank1                                   |
   |----------------------------------------------------------------------------------------------------------------------------------|
   | FLASH_WaitForLastBank1Operation    |    Yes     |      Yes      | - Wait for Bank1 last operation                                |
   +----------------------------------------------------------------------------------------------------------------------------------+

 New Functions used only with STM32F10x_XL density devices to manage Bank2 *

   +----------------------------------------------------------------------------------------------------------------------------------+
   |       Functions prototypes         |STM32F10x_XL|Other STM32F10x|    Comments                                                    |
   |                                    |   devices  |  devices      |                                                                |
   |----------------------------------------------------------------------------------------------------------------------------------|
   | FLASH_UnlockBank2                  |    Yes     |      No       | - Unlock Bank2                                                 |
   |----------------------------------------------------------------------------------------------------------------------------------|
   |FLASH_LockBank2                     |    Yes     |      No       | - Lock Bank2                                                   |
   |----------------------------------------------------------------------------------------------------------------------------------|
   | FLASH_EraseAllBank2Pages           |    Yes     |      No       | - Erase all pages in Bank2                                     |
   |----------------------------------------------------------------------------------------------------------------------------------|
   | FLASH_GetBank2Status               |    Yes     |      No       | - Return the status of Bank2                                   |
   |----------------------------------------------------------------------------------------------------------------------------------|
   | FLASH_WaitForLastBank2Operation    |    Yes     |      No       | - Wait for Bank2 last operation                                |
   |----------------------------------------------------------------------------------------------------------------------------------|
   | FLASH_BootConfig                   |    Yes     |      No       | - Configure to boot from Bank1 or Bank2                        |
   +----------------------------------------------------------------------------------------------------------------------------------+
Note:
This function can be used for all STM32F10x devices.
Parameters:
FLASH_Latency,: specifies the FLASH Latency value. This parameter can be one of the following values:

  • FLASH_Latency_0: FLASH Zero Latency cycle
  • FLASH_Latency_1: FLASH One Latency cycle
  • FLASH_Latency_2: FLASH Two Latency cycles
Return values:
None

Definition at line 254 of file stm32f10x_flash.c.

References ACR_LATENCY_Mask, assert_param, FLASH, and IS_FLASH_LATENCY.

Referenced by SetSysClockTo24(), SetSysClockTo36(), SetSysClockTo48(), SetSysClockTo56(), SetSysClockTo72(), and SetSysClockToHSE().

void FLASH_Unlock ( void )

Unlocks the FLASH Program Erase Controller.

Note:
This function can be used for all STM32F10x devices.
  • For STM32F10X_XL devices this function unlocks Bank1 and Bank2.
  • For all other devices it unlocks Bank1 and it is equivalent to FLASH_UnlockBank1 function..
Parameters:
None
Return values:
None

Definition at line 319 of file stm32f10x_flash.c.

References FLASH, FLASH_KEY1, and FLASH_KEY2.

Referenced by main().

void FLASH_UnlockBank1 ( void )

Unlocks the FLASH Bank1 Program Erase Controller.

Note:
This function can be used for all STM32F10x devices.
  • For STM32F10X_XL devices this function unlocks Bank1.
  • For all other devices it unlocks Bank1 and it is equivalent to FLASH_Unlock function.
Parameters:
None
Return values:
None

Definition at line 340 of file stm32f10x_flash.c.

References FLASH, FLASH_KEY1, and FLASH_KEY2.

Referenced by main().

FLASH_Status FLASH_UserOptionByteConfig | ( | uint16_t | OB_IWDG,
 |  | uint16_t | OB_STOP,
 |  | uint16_t | OB_STDBY
 | ) |  |

Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.

Note:
This function can be used for all STM32F10x devices.
Parameters:
OB_IWDG,: Selects the IWDG mode This parameter can be one of the following values:

  • OB_IWDG_SW: Software IWDG selected
  • OB_IWDG_HW: Hardware IWDG selected
OB_STOP,: Reset event when entering STOP mode. This parameter can be one of the following values:

  • OB_STOP_NoRST: No reset generated when entering in STOP
  • OB_STOP_RST: Reset generated when entering in STOP
OB_STDBY,: Reset event when entering Standby mode. This parameter can be one of the following values:

  • OB_STDBY_NoRST: No reset generated when entering in STANDBY
  • OB_STDBY_RST: Reset generated when entering in STANDBY
Return values:
FLASH Status: The returned value can be: FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.

Definition at line 1118 of file stm32f10x_flash.c.

References assert_param, CR_OPTPG_Reset, CR_OPTPG_Set, FLASH, FLASH_COMPLETE, FLASH_KEY1, FLASH_KEY2, FLASH_TIMEOUT, FLASH_WaitForLastOperation(), IS_OB_IWDG_SOURCE, IS_OB_STDBY_SOURCE, IS_OB_STOP_SOURCE, OB, ProgramTimeout, and status.

FLASH_Status FLASH_WaitForLastBank1Operation ( uint32_t Timeout )

Waits for a Flash operation on Bank1 to complete or a TIMEOUT to occur.

Note:
This function can be used for all STM32F10x devices, it is equivalent to FLASH_WaitForLastOperation.
Parameters:
Timeout,: FLASH programming Timeout
Return values:
FLASH Status: The returned value can be: FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.

Definition at line 1623 of file stm32f10x_flash.c.

References FLASH_COMPLETE, FLASH_FLAG_BANK1_BSY, FLASH_GetBank1Status(), FLASH_TIMEOUT, and status.

Referenced by FLASH_EraseAllBank1Pages(), FLASH_EraseAllPages(), FLASH_ErasePage(), FLASH_ProgramHalfWord(), and FLASH_ProgramWord().

FLASH_Status FLASH_WaitForLastOperation ( uint32_t Timeout )

Waits for a Flash operation to complete or a TIMEOUT to occur.

Note:
This function can be used for all STM32F10x devices, it is equivalent to FLASH_WaitForLastBank1Operation.
  • For STM32F10X_XL devices this function waits for a Bank1 Flash operation to complete or a TIMEOUT to occur.
  • For all other devices it waits for a Flash operation to complete or a TIMEOUT to occur.
Parameters:
Timeout,: FLASH programming Timeout
Return values:
FLASH Status: The returned value can be: FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.

Definition at line 1595 of file stm32f10x_flash.c.

References FLASH_BUSY, FLASH_COMPLETE, FLASH_GetBank1Status(), FLASH_TIMEOUT, and status.

Referenced by FLASH_EnableWriteProtection(), FLASH_EraseAllPages(), FLASH_EraseOptionBytes(), FLASH_ErasePage(), FLASH_ProgramHalfWord(), FLASH_ProgramOptionByteData(), FLASH_ProgramWord(), FLASH_ReadOutProtection(), and FLASH_UserOptionByteConfig().


STM32F10x Standard Peripherals Firmware Library: FLASH_Private_TypesDefinitions

FLASH_Private_TypesDefinitions

FLASH


STM32F10x Standard Peripherals Firmware Library: FLASH_Private_Defines

Defines

FLASH_Private_Defines

FLASH

Defines

#define | ACR_HLFCYA_Mask ((uint32_t)0xFFFFFFF7)
#define | ACR_LATENCY_Mask ((uint32_t)0x00000038)
#define | ACR_PRFTBE_Mask ((uint32_t)0xFFFFFFEF)
#define | ACR_PRFTBS_Mask ((uint32_t)0x00000020)
#define | CR_LOCK_Set ((uint32_t)0x00000080)
#define | CR_MER_Reset ((uint32_t)0x00001FFB)
#define | CR_MER_Set ((uint32_t)0x00000004)
#define | CR_OPTER_Reset ((uint32_t)0x00001FDF)
#define | CR_OPTER_Set ((uint32_t)0x00000020)
#define | CR_OPTPG_Reset ((uint32_t)0x00001FEF)
#define | CR_OPTPG_Set ((uint32_t)0x00000010)
#define | CR_PER_Reset ((uint32_t)0x00001FFD)
#define | CR_PER_Set ((uint32_t)0x00000002)
#define | CR_PG_Reset ((uint32_t)0x00001FFE)
#define | CR_PG_Set ((uint32_t)0x00000001)
#define | CR_STRT_Set ((uint32_t)0x00000040)
#define | EraseTimeout ((uint32_t)0x000B0000)
#define | FLASH_BANK1_END_ADDRESS ((uint32_t)0x807FFFF)
#define | FLASH_KEY1 ((uint32_t)0x45670123)
#define | FLASH_KEY2 ((uint32_t)0xCDEF89AB)
#define | OB_USER_BFB2 ((uint16_t)0x0008)
#define | ProgramTimeout ((uint32_t)0x00002000)
#define | RDP_Key ((uint16_t)0x00A5)
#define | RDPRT_Mask ((uint32_t)0x00000002)
#define | WRP0_Mask ((uint32_t)0x000000FF)
#define | WRP1_Mask ((uint32_t)0x0000FF00)
#define | WRP2_Mask ((uint32_t)0x00FF0000)
#define | WRP3_Mask ((uint32_t)0xFF000000)

Define Documentation

#define ACR_HLFCYA_Mask ((uint32_t)0xFFFFFFF7)

Definition at line 48 of file stm32f10x_flash.c.

Referenced by FLASH_HalfCycleAccessCmd().

#define ACR_LATENCY_Mask ((uint32_t)0x00000038)

Definition at line 47 of file stm32f10x_flash.c.

Referenced by FLASH_SetLatency().

#define ACR_PRFTBE_Mask ((uint32_t)0xFFFFFFEF)

Definition at line 49 of file stm32f10x_flash.c.

Referenced by FLASH_PrefetchBufferCmd().

#define ACR_PRFTBS_Mask ((uint32_t)0x00000020)

Definition at line 52 of file stm32f10x_flash.c.

Referenced by FLASH_GetPrefetchBufferStatus().

#define CR_LOCK_Set ((uint32_t)0x00000080)

Definition at line 66 of file stm32f10x_flash.c.

Referenced by FLASH_Lock(), and FLASH_LockBank1().

#define CR_MER_Reset ((uint32_t)0x00001FFB)

Definition at line 60 of file stm32f10x_flash.c.

Referenced by FLASH_EraseAllBank1Pages(), and FLASH_EraseAllPages().

#define CR_MER_Set ((uint32_t)0x00000004)

Definition at line 59 of file stm32f10x_flash.c.

Referenced by FLASH_EraseAllBank1Pages(), and FLASH_EraseAllPages().

#define CR_OPTER_Reset ((uint32_t)0x00001FDF)

Definition at line 64 of file stm32f10x_flash.c.

Referenced by FLASH_EraseOptionBytes(), and FLASH_ReadOutProtection().

#define CR_OPTER_Set ((uint32_t)0x00000020)

Definition at line 63 of file stm32f10x_flash.c.

Referenced by FLASH_EraseOptionBytes(), and FLASH_ReadOutProtection().

#define CR_OPTPG_Reset ((uint32_t)0x00001FEF)

Definition at line 62 of file stm32f10x_flash.c.

Referenced by FLASH_EnableWriteProtection(), FLASH_EraseOptionBytes(), FLASH_ProgramOptionByteData(), FLASH_ReadOutProtection(), and FLASH_UserOptionByteConfig().

#define CR_OPTPG_Set ((uint32_t)0x00000010)

Definition at line 61 of file stm32f10x_flash.c.

Referenced by FLASH_EnableWriteProtection(), FLASH_EraseOptionBytes(), FLASH_ProgramOptionByteData(), FLASH_ReadOutProtection(), and FLASH_UserOptionByteConfig().

#define CR_PER_Reset ((uint32_t)0x00001FFD)

Definition at line 58 of file stm32f10x_flash.c.

Referenced by FLASH_ErasePage().

#define CR_PER_Set ((uint32_t)0x00000002)

Definition at line 57 of file stm32f10x_flash.c.

Referenced by FLASH_ErasePage().

#define CR_PG_Reset ((uint32_t)0x00001FFE)

Definition at line 56 of file stm32f10x_flash.c.

Referenced by FLASH_ProgramHalfWord(), and FLASH_ProgramWord().

#define CR_PG_Set ((uint32_t)0x00000001)

Definition at line 55 of file stm32f10x_flash.c.

Referenced by FLASH_ProgramHalfWord(), and FLASH_ProgramWord().

#define CR_STRT_Set ((uint32_t)0x00000040)

Definition at line 65 of file stm32f10x_flash.c.

Referenced by FLASH_EraseAllBank1Pages(), FLASH_EraseAllPages(), FLASH_EraseOptionBytes(), FLASH_ErasePage(), and FLASH_ReadOutProtection().

#define EraseTimeout ((uint32_t)0x000B0000)

Definition at line 85 of file stm32f10x_flash.c.

Referenced by FLASH_EraseAllBank1Pages(), FLASH_EraseAllPages(), FLASH_EraseOptionBytes(), FLASH_ErasePage(), and FLASH_ReadOutProtection().

#define FLASH_BANK1_END_ADDRESS ((uint32_t)0x807FFFF)

Definition at line 82 of file stm32f10x_flash.c.

Referenced by FLASH_ErasePage(), FLASH_ProgramHalfWord(), and FLASH_ProgramWord().

#define FLASH_KEY1 ((uint32_t)0x45670123)

Definition at line 78 of file stm32f10x_flash.c.

Referenced by FLASH_EnableWriteProtection(), FLASH_EraseOptionBytes(), FLASH_ProgramOptionByteData(), FLASH_ReadOutProtection(), FLASH_Unlock(), FLASH_UnlockBank1(), and FLASH_UserOptionByteConfig().

#define FLASH_KEY2 ((uint32_t)0xCDEF89AB)

Definition at line 79 of file stm32f10x_flash.c.

Referenced by FLASH_EnableWriteProtection(), FLASH_EraseOptionBytes(), FLASH_ProgramOptionByteData(), FLASH_ReadOutProtection(), FLASH_Unlock(), FLASH_UnlockBank1(), and FLASH_UserOptionByteConfig().

#define OB_USER_BFB2 ((uint16_t)0x0008)

Definition at line 74 of file stm32f10x_flash.c.

#define ProgramTimeout ((uint32_t)0x00002000)

Definition at line 86 of file stm32f10x_flash.c.

Referenced by FLASH_EnableWriteProtection(), FLASH_EraseOptionBytes(), FLASH_ProgramHalfWord(), FLASH_ProgramOptionByteData(), FLASH_ProgramWord(), and FLASH_UserOptionByteConfig().

#define RDP_Key ((uint16_t)0x00A5)

Definition at line 77 of file stm32f10x_flash.c.

Referenced by FLASH_EraseOptionBytes(), and FLASH_ReadOutProtection().

#define RDPRT_Mask ((uint32_t)0x00000002)

Definition at line 69 of file stm32f10x_flash.c.

Referenced by FLASH_GetReadOutProtectionStatus().

#define WRP0_Mask ((uint32_t)0x000000FF)

Definition at line 70 of file stm32f10x_flash.c.

Referenced by FLASH_EnableWriteProtection().

#define WRP1_Mask ((uint32_t)0x0000FF00)

Definition at line 71 of file stm32f10x_flash.c.

Referenced by FLASH_EnableWriteProtection().

#define WRP2_Mask ((uint32_t)0x00FF0000)

Definition at line 72 of file stm32f10x_flash.c.

Referenced by FLASH_EnableWriteProtection().

#define WRP3_Mask ((uint32_t)0xFF000000)

Definition at line 73 of file stm32f10x_flash.c.

Referenced by FLASH_EnableWriteProtection().


STM32F10x Standard Peripherals Firmware Library: FLASH_Private_Macros

FLASH_Private_Macros

FLASH


STM32F10x Standard Peripherals Firmware Library: FLASH_Private_Variables

FLASH_Private_Variables

FLASH


STM32F10x Standard Peripherals Firmware Library: FLASH_Private_FunctionPrototypes

FLASH_Private_FunctionPrototypes

FLASH


STM32F10x Standard Peripherals Firmware Library: FLASH_Private_Functions

Functions

FLASH_Private_Functions

FLASH

Functions

void | FLASH_ClearFlag (uint32_t FLASH_FLAG)
Clears the FLASH's pending flags.
FLASH_Status | FLASH_EnableWriteProtection (uint32_t FLASH_Pages)
Write protects the desired pages.
FLASH_Status | FLASH_EraseAllBank1Pages (void)
Erases all Bank1 FLASH pages.
FLASH_Status | FLASH_EraseAllPages (void)
Erases all FLASH pages.
FLASH_Status | FLASH_EraseOptionBytes (void)
Erases the FLASH option bytes.
FLASH_Status | FLASH_ErasePage (uint32_t Page_Address)
Erases a specified FLASH page.
FLASH_Status | FLASH_GetBank1Status (void)
Returns the FLASH Bank1 Status.
FlagStatus | FLASH_GetFlagStatus (uint32_t FLASH_FLAG)
Checks whether the specified FLASH flag is set or not.
FlagStatus | FLASH_GetPrefetchBufferStatus (void)
Checks whether the FLASH Prefetch Buffer status is set or not.
FlagStatus | FLASH_GetReadOutProtectionStatus (void)
Checks whether the FLASH Read Out Protection Status is set or not.
FLASH_Status | FLASH_GetStatus (void)
Returns the FLASH Status.
uint32_t | FLASH_GetUserOptionByte (void)
Returns the FLASH User Option Bytes values.
uint32_t | FLASH_GetWriteProtectionOptionByte (void)
Returns the FLASH Write Protection Option Bytes Register value.
void | FLASH_HalfCycleAccessCmd (uint32_t FLASH_HalfCycleAccess)
Enables or disables the Half cycle flash access.
void | FLASH_ITConfig (uint32_t FLASH_IT, FunctionalState NewState)
Enables or disables the specified FLASH interrupts.
void | FLASH_Lock (void)
Locks the FLASH Program Erase Controller.
void | FLASH_LockBank1 (void)
Locks the FLASH Bank1 Program Erase Controller.
void | FLASH_PrefetchBufferCmd (uint32_t FLASH_PrefetchBuffer)
Enables or disables the Prefetch Buffer.
FLASH_Status | FLASH_ProgramHalfWord (uint32_t Address, uint16_t Data)
Programs a half word at a specified address.
FLASH_Status | FLASH_ProgramOptionByteData (uint32_t Address, uint8_t Data)
Programs a half word at a specified Option Byte Data address.
FLASH_Status | FLASH_ProgramWord (uint32_t Address, uint32_t Data)
Programs a word at a specified address.
FLASH_Status | FLASH_ReadOutProtection (FunctionalState NewState)
Enables or disables the read out protection.
void | FLASH_SetLatency (uint32_t FLASH_Latency)
Sets the code latency value.
void | FLASH_Unlock (void)
Unlocks the FLASH Program Erase Controller.
void | FLASH_UnlockBank1 (void)
Unlocks the FLASH Bank1 Program Erase Controller.
FLASH_Status | FLASH_UserOptionByteConfig (uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY)
Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
FLASH_Status | FLASH_WaitForLastBank1Operation (uint32_t Timeout)
Waits for a Flash operation on Bank1 to complete or a TIMEOUT to occur.
FLASH_Status | FLASH_WaitForLastOperation (uint32_t Timeout)
Waits for a Flash operation to complete or a TIMEOUT to occur.

Function Documentation

void FLASH_ClearFlag ( uint32_t FLASH_FLAG )

Clears the FLASH's pending flags.

Note:
This function can be used for all STM32F10x devices.
  • For STM32F10X_XL devices, this function clears Bank1 or Bank2’s pending flags
  • For other devices, it clears Bank1’s pending flags.
Parameters:
FLASH_FLAG,: specifies the FLASH flags to clear. This parameter can be any combination of the following values:

  • FLASH_FLAG_PGERR: FLASH Program error flag
  • FLASH_FLAG_WRPRTERR: FLASH Write protected error flag
  • FLASH_FLAG_EOP: FLASH End of Operation flag
Return values:
None

Definition at line 1443 of file stm32f10x_flash.c.

References assert_param, FLASH, and IS_FLASH_CLEAR_FLAG.

Referenced by main().

FLASH_Status FLASH_EnableWriteProtection ( uint32_t FLASH_Pages )

Write protects the desired pages.

Note:
This function can be used for all STM32F10x devices.
Parameters:
FLASH_Pages,: specifies the address of the pages to be write protected. This parameter can be:

  • For STM32_Low-density_devices: value between FLASH_WRProt_Pages0to3 and FLASH_WRProt_Pages28to31
  • For STM32_Medium-density_devices: value between FLASH_WRProt_Pages0to3 and FLASH_WRProt_Pages124to127
  • For STM32_High-density_devices: value between FLASH_WRProt_Pages0to1 and FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to255
  • For STM32_Connectivity_line_devices: value between FLASH_WRProt_Pages0to1 and FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to127
  • For STM32_XL-density_devices: value between FLASH_WRProt_Pages0to1 and FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to511
  • FLASH_WRProt_AllPages
Return values:
FLASH Status: The returned value can be: FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.

Definition at line 975 of file stm32f10x_flash.c.

References assert_param, CR_OPTPG_Reset, CR_OPTPG_Set, FLASH, FLASH_COMPLETE, FLASH_KEY1, FLASH_KEY2, FLASH_TIMEOUT, FLASH_WaitForLastOperation(), IS_FLASH_WRPROT_PAGE, OB, ProgramTimeout, status, WRP0_Mask, WRP1_Mask, WRP2_Mask, and WRP3_Mask.

Referenced by main().

FLASH_Status FLASH_EraseAllBank1Pages ( void )

Erases all Bank1 FLASH pages.

Note:
This function can be used for all STM32F10x devices.
  • For STM32F10X_XL devices this function erases all Bank1 pages.
  • For all other devices it erases all Bank1 pages and it is equivalent to FLASH_EraseAllPages function.
Parameters:
None
Return values:
FLASH Status: The returned value can be: FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.

Definition at line 555 of file stm32f10x_flash.c.

References CR_MER_Reset, CR_MER_Set, CR_STRT_Set, EraseTimeout, FLASH, FLASH_COMPLETE, FLASH_WaitForLastBank1Operation(), and status.

FLASH_Status FLASH_EraseAllPages ( void )

Erases all FLASH pages.

Note:
This function can be used for all STM32F10x devices.
Parameters:
None
Return values:
FLASH Status: The returned value can be: FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.

Definition at line 492 of file stm32f10x_flash.c.

References CR_MER_Reset, CR_MER_Set, CR_STRT_Set, EraseTimeout, FLASH, FLASH_COMPLETE, FLASH_WaitForLastBank1Operation(), FLASH_WaitForLastOperation(), and status.

FLASH_Status FLASH_EraseOptionBytes ( void )

Erases the FLASH option bytes.

Note:
This functions erases all option bytes except the Read protection (RDP).
This function can be used for all STM32F10x devices.
Parameters:
None
Return values:
FLASH Status: The returned value can be: FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.

Definition at line 616 of file stm32f10x_flash.c.

References CR_OPTER_Reset, CR_OPTER_Set, CR_OPTPG_Reset, CR_OPTPG_Set, CR_STRT_Set, EraseTimeout, FLASH, FLASH_COMPLETE, FLASH_GetReadOutProtectionStatus(), FLASH_KEY1, FLASH_KEY2, FLASH_TIMEOUT, FLASH_WaitForLastOperation(), OB, ProgramTimeout, RDP_Key, RESET, and status.

Referenced by main().

FLASH_Status FLASH_ErasePage ( uint32_t Page_Address )

Erases a specified FLASH page.

Note:
This function can be used for all STM32F10x devices.
Parameters:
Page_Address,: The page address to be erased.
Return values:
FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.

Definition at line 419 of file stm32f10x_flash.c.

References assert_param, CR_PER_Reset, CR_PER_Set, CR_STRT_Set, EraseTimeout, FLASH, FLASH_BANK1_END_ADDRESS, FLASH_COMPLETE, FLASH_WaitForLastBank1Operation(), FLASH_WaitForLastOperation(), IS_FLASH_ADDRESS, and status.

Referenced by main().

FLASH_Status FLASH_GetBank1Status ( void )

Returns the FLASH Bank1 Status.

Note:
This function can be used for all STM32F10x devices, it is equivalent to FLASH_GetStatus function.
Parameters:
None
Return values:
FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, FLASH_ERROR_WRP or FLASH_COMPLETE

Definition at line 1515 of file stm32f10x_flash.c.

References FLASH, FLASH_BUSY, FLASH_COMPLETE, FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_FLAG_BANK1_BSY, FLASH_FLAG_BANK1_PGERR, FLASH_FLAG_BANK1_WRPRTERR, and FLASH_FLAG_BSY.

Referenced by FLASH_WaitForLastBank1Operation(), and FLASH_WaitForLastOperation().

FlagStatus FLASH_GetFlagStatus ( uint32_t FLASH_FLAG )

Checks whether the specified FLASH flag is set or not.

Note:
This function can be used for all STM32F10x devices.
  • For STM32F10X_XL devices, this function checks whether the specified Bank1 or Bank2 flag is set or not.
  • For other devices, it checks whether the specified Bank1 flag is set or not.
Parameters:
FLASH_FLAG,: specifies the FLASH flag to check. This parameter can be one of the following values:

  • FLASH_FLAG_BSY: FLASH Busy flag
  • FLASH_FLAG_PGERR: FLASH Program error flag
  • FLASH_FLAG_WRPRTERR: FLASH Write protected error flag
  • FLASH_FLAG_EOP: FLASH End of Operation flag
  • FLASH_FLAG_OPTERR: FLASH Option Byte error flag
Return values:
The new state of FLASH_FLAG (SET or RESET).

Definition at line 1357 of file stm32f10x_flash.c.

References assert_param, FLASH, FLASH_FLAG_OPTERR, IS_FLASH_GET_FLAG, RESET, and SET.

FlagStatus FLASH_GetPrefetchBufferStatus ( void )

Checks whether the FLASH Prefetch Buffer status is set or not.

Note:
This function can be used for all STM32F10x devices.
Parameters:
None
Return values:
FLASH Prefetch Buffer Status (SET or RESET).

Definition at line 1260 of file stm32f10x_flash.c.

References ACR_PRFTBS_Mask, FLASH, RESET, and SET.

FlagStatus FLASH_GetReadOutProtectionStatus ( void )

Checks whether the FLASH Read Out Protection Status is set or not.

Note:
This function can be used for all STM32F10x devices.
Parameters:
None
Return values:
FLASH ReadOut Protection Status(SET or RESET)

Definition at line 1240 of file stm32f10x_flash.c.

References FLASH, RDPRT_Mask, RESET, and SET.

Referenced by FLASH_EraseOptionBytes().

FLASH_Status FLASH_GetStatus ( void )

Returns the FLASH Status.

Note:
This function can be used for all STM32F10x devices, it is equivalent to FLASH_GetBank1Status function.
Parameters:
None
Return values:
FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, FLASH_ERROR_WRP or FLASH_COMPLETE

Definition at line 1477 of file stm32f10x_flash.c.

References FLASH, FLASH_BUSY, FLASH_COMPLETE, FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_FLAG_BSY, FLASH_FLAG_PGERR, and FLASH_FLAG_WRPRTERR.

uint32_t FLASH_GetUserOptionByte ( void )

Returns the FLASH User Option Bytes values.

Note:
This function can be used for all STM32F10x devices.
Parameters:
None
Return values:
The FLASH User Option Bytes values:IWDG_SW(Bit0), RST_STOP(Bit1) and RST_STDBY(Bit2).

Definition at line 1216 of file stm32f10x_flash.c.

References FLASH.

uint32_t FLASH_GetWriteProtectionOptionByte ( void )

Returns the FLASH Write Protection Option Bytes Register value.

Note:
This function can be used for all STM32F10x devices.
Parameters:
None
Return values:
The FLASH Write Protection Option Bytes Register value

Definition at line 1228 of file stm32f10x_flash.c.

References FLASH.

Referenced by main().

void FLASH_HalfCycleAccessCmd ( uint32_t FLASH_HalfCycleAccess )

Enables or disables the Half cycle flash access.

Note:
This function can be used for all STM32F10x devices.
Parameters:
FLASH_HalfCycleAccess,: specifies the FLASH Half cycle Access mode. This parameter can be one of the following values:

  • FLASH_HalfCycleAccess_Enable: FLASH Half Cycle Enable
  • FLASH_HalfCycleAccess_Disable: FLASH Half Cycle Disable
Return values:
None

Definition at line 281 of file stm32f10x_flash.c.

References ACR_HLFCYA_Mask, assert_param, FLASH, and IS_FLASH_HALFCYCLEACCESS_STATE.

void FLASH_ITConfig | ( | uint32_t | FLASH_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified FLASH interrupts.

Note:
This function can be used for all STM32F10x devices.
  • For STM32F10X_XL devices, enables or disables the specified FLASH interrupts for Bank1 and Bank2.
  • For other devices it enables or disables the specified FLASH interrupts for Bank1.
Parameters:
FLASH_IT,: specifies the FLASH interrupt sources to be enabled or disabled. This parameter can be any combination of the following values:

  • FLASH_IT_ERROR: FLASH Error Interrupt
  • FLASH_IT_EOP: FLASH end of operation Interrupt
NewState,: new state of the specified Flash interrupts. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1290 of file stm32f10x_flash.c.

References assert_param, DISABLE, FLASH, IS_FLASH_IT, and IS_FUNCTIONAL_STATE.

void FLASH_Lock ( void )

Locks the FLASH Program Erase Controller.

Note:
This function can be used for all STM32F10x devices.
  • For STM32F10X_XL devices this function Locks Bank1 and Bank2.
  • For all other devices it Locks Bank1 and it is equivalent to FLASH_LockBank1 function.
Parameters:
None
Return values:
None

Definition at line 372 of file stm32f10x_flash.c.

References CR_LOCK_Set, and FLASH.

Referenced by main().

void FLASH_LockBank1 ( void )

Locks the FLASH Bank1 Program Erase Controller.

Note:
this function can be used for all STM32F10x devices.
  • For STM32F10X_XL devices this function Locks Bank1.
  • For all other devices it Locks Bank1 and it is equivalent to FLASH_Lock function.
Parameters:
None
Return values:
None

Definition at line 392 of file stm32f10x_flash.c.

References CR_LOCK_Set, and FLASH.

Referenced by main().

void FLASH_PrefetchBufferCmd ( uint32_t FLASH_PrefetchBuffer )

Enables or disables the Prefetch Buffer.

Note:
This function can be used for all STM32F10x devices.
Parameters:
FLASH_PrefetchBuffer,: specifies the Prefetch buffer status. This parameter can be one of the following values:

  • FLASH_PrefetchBuffer_Enable: FLASH Prefetch Buffer Enable
  • FLASH_PrefetchBuffer_Disable: FLASH Prefetch Buffer Disable
Return values:
None

Definition at line 300 of file stm32f10x_flash.c.

References ACR_PRFTBE_Mask, assert_param, FLASH, and IS_FLASH_PREFETCHBUFFER_STATE.

Referenced by SetSysClockTo24(), SetSysClockTo36(), SetSysClockTo48(), SetSysClockTo56(), SetSysClockTo72(), and SetSysClockToHSE().

FLASH_Status FLASH_ProgramHalfWord | ( | uint32_t | Address,
 |  | uint16_t | Data
 | ) |  |

Programs a half word at a specified address.

Note:
This function can be used for all STM32F10x devices.
Parameters:
Address,: specifies the address to be programmed.
Data,: specifies the data to be programmed.
Return values:
FLASH Status: The returned value can be: FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.

Definition at line 858 of file stm32f10x_flash.c.

References assert_param, CR_PG_Reset, CR_PG_Set, FLASH, FLASH_BANK1_END_ADDRESS, FLASH_COMPLETE, FLASH_WaitForLastBank1Operation(), FLASH_WaitForLastOperation(), IS_FLASH_ADDRESS, ProgramTimeout, and status.

Referenced by main().

FLASH_Status FLASH_ProgramOptionByteData | ( | uint32_t | Address,
 |  | uint8_t | Data
 | ) |  |

Programs a half word at a specified Option Byte Data address.

Note:
This function can be used for all STM32F10x devices.
Parameters:
Address,: specifies the address to be programmed. This parameter can be 0x1FFFF804 or 0x1FFFF806.
Data,: specifies the data to be programmed.
Return values:
FLASH Status: The returned value can be: FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.

Definition at line 929 of file stm32f10x_flash.c.

References assert_param, CR_OPTPG_Reset, CR_OPTPG_Set, FLASH, FLASH_COMPLETE, FLASH_KEY1, FLASH_KEY2, FLASH_TIMEOUT, FLASH_WaitForLastOperation(), IS_OB_DATA_ADDRESS, ProgramTimeout, and status.

FLASH_Status FLASH_ProgramWord | ( | uint32_t | Address,
 |  | uint32_t | Data
 | ) |  |

Programs a word at a specified address.

Note:
This function can be used for all STM32F10x devices.
Parameters:
Address,: specifies the address to be programmed.
Data,: specifies the data to be programmed.
Return values:
FLASH Status: The returned value can be: FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.

Definition at line 681 of file stm32f10x_flash.c.

References assert_param, CR_PG_Reset, CR_PG_Set, Data, FLASH, FLASH_BANK1_END_ADDRESS, FLASH_COMPLETE, FLASH_WaitForLastBank1Operation(), FLASH_WaitForLastOperation(), IS_FLASH_ADDRESS, ProgramTimeout, and status.

Referenced by main().

FLASH_Status FLASH_ReadOutProtection ( FunctionalState NewState )

Enables or disables the read out protection.

Note:
If the user has already programmed the other option bytes before calling this function, he must re-program them since this function erases all option bytes.
This function can be used for all STM32F10x devices.
Parameters:
Newstate,: new state of the ReadOut Protection. This parameter can be: ENABLE or DISABLE.
Return values:
FLASH Status: The returned value can be: FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.

Definition at line 1049 of file stm32f10x_flash.c.

References assert_param, CR_OPTER_Reset, CR_OPTER_Set, CR_OPTPG_Reset, CR_OPTPG_Set, CR_STRT_Set, DISABLE, EraseTimeout, FLASH, FLASH_COMPLETE, FLASH_KEY1, FLASH_KEY2, FLASH_TIMEOUT, FLASH_WaitForLastOperation(), IS_FUNCTIONAL_STATE, OB, RDP_Key, and status.

void FLASH_SetLatency ( uint32_t FLASH_Latency )

Sets the code latency value.

 This driver provides functions to configure and program the Flash memory of all STM32F10x devices,
 including the latest STM32F10x_XL density devices.

 STM32F10x_XL devices feature up to 1 Mbyte with dual bank architecture for read-while-write (RWW) capability:
    - bank1: fixed size of 512 Kbytes (256 pages of 2Kbytes each)
    - bank2: up to 512 Kbytes (up to 256 pages of 2Kbytes each)
 While other STM32F10x devices features only one bank with memory up to 512 Kbytes.

 In version V3.3.0, some functions were updated and new ones were added to support
 STM32F10x_XL devices. Thus some functions manages all devices, while other are
 dedicated for XL devices only.

 The table below presents the list of available functions depending on the used STM32F10x devices.

 Legacy functions used for all STM32F10x devices *

   +----------------------------------------------------------------------------------------------------------------------------------+
   |       Functions prototypes         |STM32F10x_XL|Other STM32F10x|    Comments                                                    |
   |                                    |   devices  |  devices      |                                                                |
   |----------------------------------------------------------------------------------------------------------------------------------|
   |FLASH_SetLatency                    |    Yes     |      Yes      | No change                                                      |
   |----------------------------------------------------------------------------------------------------------------------------------|
   |FLASH_HalfCycleAccessCmd            |    Yes     |      Yes      | No change                                                      |
   |----------------------------------------------------------------------------------------------------------------------------------|
   |FLASH_PrefetchBufferCmd             |    Yes     |      Yes      | No change                                                      |
   |----------------------------------------------------------------------------------------------------------------------------------|
   |FLASH_Unlock                        |    Yes     |      Yes      | - For STM32F10X_XL devices: unlock Bank1 and Bank2.            |
   |                                    |            |               | - For other devices: unlock Bank1 and it is equivalent         |
   |                                    |            |               |   to FLASH_UnlockBank1 function.                               |
   |----------------------------------------------------------------------------------------------------------------------------------|
   |FLASH_Lock                          |    Yes     |      Yes      | - For STM32F10X_XL devices: lock Bank1 and Bank2.              |
   |                                    |            |               | - For other devices: lock Bank1 and it is equivalent           |
   |                                    |            |               |   to FLASH_LockBank1 function.                                 |
   |----------------------------------------------------------------------------------------------------------------------------------|
   |FLASH_ErasePage                     |    Yes     |      Yes      | - For STM32F10x_XL devices: erase a page in Bank1 and Bank2    |
   |                                    |            |               | - For other devices: erase a page in Bank1                     |
   |----------------------------------------------------------------------------------------------------------------------------------|
   |FLASH_EraseAllPages                 |    Yes     |      Yes      | - For STM32F10x_XL devices: erase all pages in Bank1 and Bank2 |
   |                                    |            |               | - For other devices: erase all pages in Bank1                  |
   |----------------------------------------------------------------------------------------------------------------------------------|
   |FLASH_EraseOptionBytes              |    Yes     |      Yes      | No change                                                      |
   |----------------------------------------------------------------------------------------------------------------------------------|
   |FLASH_ProgramWord                   |    Yes     |      Yes      | Updated to program up to 1MByte (depending on the used device) |
   |----------------------------------------------------------------------------------------------------------------------------------|
   |FLASH_ProgramHalfWord               |    Yes     |      Yes      | Updated to program up to 1MByte (depending on the used device) |
   |----------------------------------------------------------------------------------------------------------------------------------|
   |FLASH_ProgramOptionByteData         |    Yes     |      Yes      | No change                                                      |
   |----------------------------------------------------------------------------------------------------------------------------------|
   |FLASH_EnableWriteProtection         |    Yes     |      Yes      | No change                                                      |
   |----------------------------------------------------------------------------------------------------------------------------------|
   |FLASH_ReadOutProtection             |    Yes     |      Yes      | No change                                                      |
   |----------------------------------------------------------------------------------------------------------------------------------|
   |FLASH_UserOptionByteConfig          |    Yes     |      Yes      | No change                                                      |
   |----------------------------------------------------------------------------------------------------------------------------------|
   |FLASH_GetUserOptionByte             |    Yes     |      Yes      | No change                                                      |
   |----------------------------------------------------------------------------------------------------------------------------------|
   |FLASH_GetWriteProtectionOptionByte  |    Yes     |      Yes      | No change                                                      |
   |----------------------------------------------------------------------------------------------------------------------------------|
   |FLASH_GetReadOutProtectionStatus    |    Yes     |      Yes      | No change                                                      |
   |----------------------------------------------------------------------------------------------------------------------------------|
   |FLASH_GetPrefetchBufferStatus       |    Yes     |      Yes      | No change                                                      |
   |----------------------------------------------------------------------------------------------------------------------------------|
   |FLASH_ITConfig                      |    Yes     |      Yes      | - For STM32F10x_XL devices: enable Bank1 and Bank2's interrupts|
   |                                    |            |               | - For other devices: enable Bank1's interrupts                 |
   |----------------------------------------------------------------------------------------------------------------------------------|
   |FLASH_GetFlagStatus                 |    Yes     |      Yes      | - For STM32F10x_XL devices: return Bank1 and Bank2's flag status|
   |                                    |            |               | - For other devices: return Bank1's flag status                |
   |----------------------------------------------------------------------------------------------------------------------------------|
   |FLASH_ClearFlag                     |    Yes     |      Yes      | - For STM32F10x_XL devices: clear Bank1 and Bank2's flag       |
   |                                    |            |               | - For other devices: clear Bank1's flag                        |
   |----------------------------------------------------------------------------------------------------------------------------------|
   |FLASH_GetStatus                     |    Yes     |      Yes      | - Return the status of Bank1 (for all devices)                 |
   |                                    |            |               |   equivalent to FLASH_GetBank1Status function                  |
   |----------------------------------------------------------------------------------------------------------------------------------|
   |FLASH_WaitForLastOperation          |    Yes     |      Yes      | - Wait for Bank1 last operation (for all devices)              |
   |                                    |            |               |   equivalent to: FLASH_WaitForLastBank1Operation function      |
   +----------------------------------------------------------------------------------------------------------------------------------+

 New functions used for all STM32F10x devices to manage Bank1:                                                        *
   - These functions are mainly useful for STM32F10x_XL density devices, to have separate control for Bank1 and bank2 *
   - For other devices, these functions are optional (covered by functions listed above)                              *

   +----------------------------------------------------------------------------------------------------------------------------------+
   |       Functions prototypes         |STM32F10x_XL|Other STM32F10x|    Comments                                                    |
   |                                    |   devices  |  devices      |                                                                |
   |----------------------------------------------------------------------------------------------------------------------------------|
   | FLASH_UnlockBank1                  |    Yes     |      Yes      | - Unlock Bank1                                                 |
   |----------------------------------------------------------------------------------------------------------------------------------|
   |FLASH_LockBank1                     |    Yes     |      Yes      | - Lock Bank1                                                   |
   |----------------------------------------------------------------------------------------------------------------------------------|
   | FLASH_EraseAllBank1Pages           |    Yes     |      Yes      | - Erase all pages in Bank1                                     |
   |----------------------------------------------------------------------------------------------------------------------------------|
   | FLASH_GetBank1Status               |    Yes     |      Yes      | - Return the status of Bank1                                   |
   |----------------------------------------------------------------------------------------------------------------------------------|
   | FLASH_WaitForLastBank1Operation    |    Yes     |      Yes      | - Wait for Bank1 last operation                                |
   +----------------------------------------------------------------------------------------------------------------------------------+

 New Functions used only with STM32F10x_XL density devices to manage Bank2 *

   +----------------------------------------------------------------------------------------------------------------------------------+
   |       Functions prototypes         |STM32F10x_XL|Other STM32F10x|    Comments                                                    |
   |                                    |   devices  |  devices      |                                                                |
   |----------------------------------------------------------------------------------------------------------------------------------|
   | FLASH_UnlockBank2                  |    Yes     |      No       | - Unlock Bank2                                                 |
   |----------------------------------------------------------------------------------------------------------------------------------|
   |FLASH_LockBank2                     |    Yes     |      No       | - Lock Bank2                                                   |
   |----------------------------------------------------------------------------------------------------------------------------------|
   | FLASH_EraseAllBank2Pages           |    Yes     |      No       | - Erase all pages in Bank2                                     |
   |----------------------------------------------------------------------------------------------------------------------------------|
   | FLASH_GetBank2Status               |    Yes     |      No       | - Return the status of Bank2                                   |
   |----------------------------------------------------------------------------------------------------------------------------------|
   | FLASH_WaitForLastBank2Operation    |    Yes     |      No       | - Wait for Bank2 last operation                                |
   |----------------------------------------------------------------------------------------------------------------------------------|
   | FLASH_BootConfig                   |    Yes     |      No       | - Configure to boot from Bank1 or Bank2                        |
   +----------------------------------------------------------------------------------------------------------------------------------+
Note:
This function can be used for all STM32F10x devices.
Parameters:
FLASH_Latency,: specifies the FLASH Latency value. This parameter can be one of the following values:

  • FLASH_Latency_0: FLASH Zero Latency cycle
  • FLASH_Latency_1: FLASH One Latency cycle
  • FLASH_Latency_2: FLASH Two Latency cycles
Return values:
None

Definition at line 254 of file stm32f10x_flash.c.

References ACR_LATENCY_Mask, assert_param, FLASH, and IS_FLASH_LATENCY.

Referenced by SetSysClockTo24(), SetSysClockTo36(), SetSysClockTo48(), SetSysClockTo56(), SetSysClockTo72(), and SetSysClockToHSE().

void FLASH_Unlock ( void )

Unlocks the FLASH Program Erase Controller.

Note:
This function can be used for all STM32F10x devices.
  • For STM32F10X_XL devices this function unlocks Bank1 and Bank2.
  • For all other devices it unlocks Bank1 and it is equivalent to FLASH_UnlockBank1 function..
Parameters:
None
Return values:
None

Definition at line 319 of file stm32f10x_flash.c.

References FLASH, FLASH_KEY1, and FLASH_KEY2.

Referenced by main().

void FLASH_UnlockBank1 ( void )

Unlocks the FLASH Bank1 Program Erase Controller.

Note:
This function can be used for all STM32F10x devices.
  • For STM32F10X_XL devices this function unlocks Bank1.
  • For all other devices it unlocks Bank1 and it is equivalent to FLASH_Unlock function.
Parameters:
None
Return values:
None

Definition at line 340 of file stm32f10x_flash.c.

References FLASH, FLASH_KEY1, and FLASH_KEY2.

Referenced by main().

FLASH_Status FLASH_UserOptionByteConfig | ( | uint16_t | OB_IWDG,
 |  | uint16_t | OB_STOP,
 |  | uint16_t | OB_STDBY
 | ) |  |

Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.

Note:
This function can be used for all STM32F10x devices.
Parameters:
OB_IWDG,: Selects the IWDG mode This parameter can be one of the following values:

  • OB_IWDG_SW: Software IWDG selected
  • OB_IWDG_HW: Hardware IWDG selected
OB_STOP,: Reset event when entering STOP mode. This parameter can be one of the following values:

  • OB_STOP_NoRST: No reset generated when entering in STOP
  • OB_STOP_RST: Reset generated when entering in STOP
OB_STDBY,: Reset event when entering Standby mode. This parameter can be one of the following values:

  • OB_STDBY_NoRST: No reset generated when entering in STANDBY
  • OB_STDBY_RST: Reset generated when entering in STANDBY
Return values:
FLASH Status: The returned value can be: FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.

Definition at line 1118 of file stm32f10x_flash.c.

References assert_param, CR_OPTPG_Reset, CR_OPTPG_Set, FLASH, FLASH_COMPLETE, FLASH_KEY1, FLASH_KEY2, FLASH_TIMEOUT, FLASH_WaitForLastOperation(), IS_OB_IWDG_SOURCE, IS_OB_STDBY_SOURCE, IS_OB_STOP_SOURCE, OB, ProgramTimeout, and status.

FLASH_Status FLASH_WaitForLastBank1Operation ( uint32_t Timeout )

Waits for a Flash operation on Bank1 to complete or a TIMEOUT to occur.

Note:
This function can be used for all STM32F10x devices, it is equivalent to FLASH_WaitForLastOperation.
Parameters:
Timeout,: FLASH programming Timeout
Return values:
FLASH Status: The returned value can be: FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.

Definition at line 1623 of file stm32f10x_flash.c.

References FLASH_COMPLETE, FLASH_FLAG_BANK1_BSY, FLASH_GetBank1Status(), FLASH_TIMEOUT, and status.

Referenced by FLASH_EraseAllBank1Pages(), FLASH_EraseAllPages(), FLASH_ErasePage(), FLASH_ProgramHalfWord(), and FLASH_ProgramWord().

FLASH_Status FLASH_WaitForLastOperation ( uint32_t Timeout )

Waits for a Flash operation to complete or a TIMEOUT to occur.

Note:
This function can be used for all STM32F10x devices, it is equivalent to FLASH_WaitForLastBank1Operation.
  • For STM32F10X_XL devices this function waits for a Bank1 Flash operation to complete or a TIMEOUT to occur.
  • For all other devices it waits for a Flash operation to complete or a TIMEOUT to occur.
Parameters:
Timeout,: FLASH programming Timeout
Return values:
FLASH Status: The returned value can be: FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.

Definition at line 1595 of file stm32f10x_flash.c.

References FLASH_BUSY, FLASH_COMPLETE, FLASH_GetBank1Status(), FLASH_TIMEOUT, and status.

Referenced by FLASH_EnableWriteProtection(), FLASH_EraseAllPages(), FLASH_EraseOptionBytes(), FLASH_ErasePage(), FLASH_ProgramHalfWord(), FLASH_ProgramOptionByteData(), FLASH_ProgramWord(), FLASH_ReadOutProtection(), and FLASH_UserOptionByteConfig().


STM32F10x Standard Peripherals Firmware Library: FSMC_NAND_PCCARDTimingInitTypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

FSMC_NAND_PCCARDTimingInitTypeDef Struct Reference
FSMC_Exported_Types

Timing parameters For FSMC NAND and PCCARD Banks. More...

#include <stm32f10x_fsmc.h>

Data Fields

uint32_t | FSMC_HiZSetupTime
uint32_t | FSMC_HoldSetupTime
uint32_t | FSMC_SetupTime
uint32_t | FSMC_WaitSetupTime

Detailed Description

Timing parameters For FSMC NAND and PCCARD Banks.

Definition at line 151 of file stm32f10x_fsmc.h.

Field Documentation

uint32_t FSMC_NAND_PCCARDTimingInitTypeDef::FSMC_HiZSetupTime

Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the start of a NAND-Flash write access to common/Attribute or I/O memory space (depending on the memory space timing to be configured). This parameter can be a number between 0x00 and 0xFF

Definition at line 172 of file stm32f10x_fsmc.h.

Referenced by FSMC_NANDInit(), FSMC_NANDStructInit(), FSMC_PCCARDInit(), FSMC_PCCARDStructInit(), and NAND_Init().

uint32_t FSMC_NAND_PCCARDTimingInitTypeDef::FSMC_HoldSetupTime

Defines the number of HCLK clock cycles to hold address (and data for write access) after the command deassertion for NAND-Flash read or write access to common/Attribute or I/O memory space (depending on the memory space timing to be configured). This parameter can be a number between 0x00 and 0xFF

Definition at line 165 of file stm32f10x_fsmc.h.

Referenced by FSMC_NANDInit(), FSMC_NANDStructInit(), FSMC_PCCARDInit(), FSMC_PCCARDStructInit(), and NAND_Init().

uint32_t FSMC_NAND_PCCARDTimingInitTypeDef::FSMC_SetupTime

Defines the number of HCLK cycles to setup address before the command assertion for NAND-Flash read or write access to common/Attribute or I/O memory space (depending on the memory space timing to be configured). This parameter can be a value between 0 and 0xFF.

Definition at line 153 of file stm32f10x_fsmc.h.

Referenced by FSMC_NANDInit(), FSMC_NANDStructInit(), FSMC_PCCARDInit(), FSMC_PCCARDStructInit(), and NAND_Init().

uint32_t FSMC_NAND_PCCARDTimingInitTypeDef::FSMC_WaitSetupTime

Defines the minimum number of HCLK cycles to assert the command for NAND-Flash read or write access to common/Attribute or I/O memory space (depending on the memory space timing to be configured). This parameter can be a number between 0x00 and 0xFF

Definition at line 159 of file stm32f10x_fsmc.h.

Referenced by FSMC_NANDInit(), FSMC_NANDStructInit(), FSMC_PCCARDInit(), FSMC_PCCARDStructInit(), and NAND_Init().

The documentation for this struct was generated from the following file:
  • stm32f10x_fsmc.h


STM32F10x Standard Peripherals Firmware Library: FSMC_NANDInitTypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

FSMC_NANDInitTypeDef Struct Reference
FSMC_Exported_Types

FSMC NAND Init structure definition. More...

#include <stm32f10x_fsmc.h>

Data Fields

FSMC_NAND_PCCARDTimingInitTypeDef * FSMC_AttributeSpaceTimingStruct
uint32_t | FSMC_Bank
FSMC_NAND_PCCARDTimingInitTypeDef * FSMC_CommonSpaceTimingStruct
uint32_t | FSMC_ECC
uint32_t | FSMC_ECCPageSize
uint32_t | FSMC_MemoryDataWidth
uint32_t | FSMC_TARSetupTime
uint32_t | FSMC_TCLRSetupTime
uint32_t | FSMC_Waitfeature

Detailed Description

FSMC NAND Init structure definition.

Definition at line 183 of file stm32f10x_fsmc.h.

Field Documentation

FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_NANDInitTypeDef::FSMC_AttributeSpaceTimingStruct

FSMC Attribute Space Timing

Definition at line 210 of file stm32f10x_fsmc.h.

Referenced by FSMC_NANDInit(), FSMC_NANDStructInit(), and NAND_Init().

uint32_t FSMC_NANDInitTypeDef::FSMC_Bank

Specifies the NAND memory bank that will be used. This parameter can be a value of FSMC_NAND_Bank

Definition at line 185 of file stm32f10x_fsmc.h.

Referenced by FSMC_NANDInit(), FSMC_NANDStructInit(), and NAND_Init().

FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_NANDInitTypeDef::FSMC_CommonSpaceTimingStruct

FSMC Common Space Timing

Definition at line 208 of file stm32f10x_fsmc.h.

Referenced by FSMC_NANDInit(), FSMC_NANDStructInit(), and NAND_Init().

uint32_t FSMC_NANDInitTypeDef::FSMC_ECC

Enables or disables the ECC computation. This parameter can be any value of FSMC_ECC

Definition at line 194 of file stm32f10x_fsmc.h.

Referenced by FSMC_NANDInit(), FSMC_NANDStructInit(), and NAND_Init().

uint32_t FSMC_NANDInitTypeDef::FSMC_ECCPageSize

Defines the page size for the extended ECC. This parameter can be any value of FSMC_ECC_Page_Size

Definition at line 197 of file stm32f10x_fsmc.h.

Referenced by FSMC_NANDInit(), FSMC_NANDStructInit(), and NAND_Init().

uint32_t FSMC_NANDInitTypeDef::FSMC_MemoryDataWidth

Specifies the external memory device width. This parameter can be any value of FSMC_Data_Width

Definition at line 191 of file stm32f10x_fsmc.h.

Referenced by FSMC_NANDInit(), FSMC_NANDStructInit(), and NAND_Init().

uint32_t FSMC_NANDInitTypeDef::FSMC_TARSetupTime

Defines the number of HCLK cycles to configure the delay between ALE low and RE low. This parameter can be a number between 0x0 and 0xFF

Definition at line 204 of file stm32f10x_fsmc.h.

Referenced by FSMC_NANDInit(), FSMC_NANDStructInit(), and NAND_Init().

uint32_t FSMC_NANDInitTypeDef::FSMC_TCLRSetupTime

Defines the number of HCLK cycles to configure the delay between CLE low and RE low. This parameter can be a value between 0 and 0xFF.

Definition at line 200 of file stm32f10x_fsmc.h.

Referenced by FSMC_NANDInit(), FSMC_NANDStructInit(), and NAND_Init().

uint32_t FSMC_NANDInitTypeDef::FSMC_Waitfeature

Enables or disables the Wait feature for the NAND Memory Bank. This parameter can be any value of FSMC_Wait_feature

Definition at line 188 of file stm32f10x_fsmc.h.

Referenced by FSMC_NANDInit(), FSMC_NANDStructInit(), and NAND_Init().

The documentation for this struct was generated from the following file:
  • stm32f10x_fsmc.h


STM32F10x Standard Peripherals Firmware Library: FSMC_NORSRAMInitTypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

FSMC_NORSRAMInitTypeDef Struct Reference
FSMC_Exported_Types

FSMC NOR/SRAM Init structure definition. More...

#include <stm32f10x_fsmc.h>

Data Fields

uint32_t | FSMC_AsynchronousWait
uint32_t | FSMC_Bank
uint32_t | FSMC_BurstAccessMode
uint32_t | FSMC_DataAddressMux
uint32_t | FSMC_ExtendedMode
uint32_t | FSMC_MemoryDataWidth
uint32_t | FSMC_MemoryType
FSMC_NORSRAMTimingInitTypeDef * FSMC_ReadWriteTimingStruct
uint32_t | FSMC_WaitSignal
uint32_t | FSMC_WaitSignalActive
uint32_t | FSMC_WaitSignalPolarity
uint32_t | FSMC_WrapMode
uint32_t | FSMC_WriteBurst
uint32_t | FSMC_WriteOperation
FSMC_NORSRAMTimingInitTypeDef * FSMC_WriteTimingStruct

Detailed Description

FSMC NOR/SRAM Init structure definition.

Definition at line 92 of file stm32f10x_fsmc.h.

Field Documentation

uint32_t FSMC_NORSRAMInitTypeDef::FSMC_AsynchronousWait

Enables or disables wait signal during asynchronous transfers, valid only with asynchronous Flash memories. This parameter can be a value of FSMC_AsynchronousWait

Definition at line 112 of file stm32f10x_fsmc.h.

Referenced by FSMC_NORSRAMInit(), FSMC_NORSRAMStructInit(), LCD_FSMCConfig(), NOR_Init(), OneNAND_Init(), and SRAM_Init().

uint32_t FSMC_NORSRAMInitTypeDef::FSMC_Bank

Specifies the NOR/SRAM memory bank that will be used. This parameter can be a value of FSMC_NORSRAM_Bank

Definition at line 94 of file stm32f10x_fsmc.h.

Referenced by FSMC_NORSRAMInit(), FSMC_NORSRAMStructInit(), LCD_FSMCConfig(), NOR_Init(), OneNAND_Init(), and SRAM_Init().

uint32_t FSMC_NORSRAMInitTypeDef::FSMC_BurstAccessMode

Enables or disables the burst access mode for Flash memory, valid only with synchronous burst Flash memories. This parameter can be a value of FSMC_Burst_Access_Mode

Definition at line 108 of file stm32f10x_fsmc.h.

Referenced by FSMC_NORSRAMInit(), FSMC_NORSRAMStructInit(), LCD_FSMCConfig(), NOR_Init(), OneNAND_Init(), and SRAM_Init().

uint32_t FSMC_NORSRAMInitTypeDef::FSMC_DataAddressMux

Specifies whether the address and data values are multiplexed on the databus or not. This parameter can be a value of FSMC_Data_Address_Bus_Multiplexing

Definition at line 97 of file stm32f10x_fsmc.h.

Referenced by FSMC_NORSRAMInit(), FSMC_NORSRAMStructInit(), LCD_FSMCConfig(), NOR_Init(), OneNAND_Init(), and SRAM_Init().

uint32_t FSMC_NORSRAMInitTypeDef::FSMC_ExtendedMode

Enables or disables the extended mode. This parameter can be a value of FSMC_Extended_Mode

Definition at line 136 of file stm32f10x_fsmc.h.

Referenced by FSMC_NORSRAMInit(), FSMC_NORSRAMStructInit(), LCD_FSMCConfig(), NOR_Init(), OneNAND_Init(), and SRAM_Init().

uint32_t FSMC_NORSRAMInitTypeDef::FSMC_MemoryDataWidth

Specifies the external memory device width. This parameter can be a value of FSMC_Data_Width

Definition at line 105 of file stm32f10x_fsmc.h.

Referenced by FSMC_NORSRAMInit(), FSMC_NORSRAMStructInit(), LCD_FSMCConfig(), NOR_Init(), OneNAND_Init(), and SRAM_Init().

uint32_t FSMC_NORSRAMInitTypeDef::FSMC_MemoryType

Specifies the type of external memory attached to the corresponding memory bank. This parameter can be a value of FSMC_Memory_Type

Definition at line 101 of file stm32f10x_fsmc.h.

Referenced by FSMC_NORSRAMInit(), FSMC_NORSRAMStructInit(), LCD_FSMCConfig(), NOR_Init(), OneNAND_Init(), and SRAM_Init().

FSMC_NORSRAMTimingInitTypeDef* FSMC_NORSRAMInitTypeDef::FSMC_ReadWriteTimingStruct

Timing Parameters for write and read access if the ExtendedMode is not used

Definition at line 142 of file stm32f10x_fsmc.h.

Referenced by FSMC_NORSRAMInit(), FSMC_NORSRAMStructInit(), LCD_FSMCConfig(), NOR_Init(), OneNAND_Init(), and SRAM_Init().

uint32_t FSMC_NORSRAMInitTypeDef::FSMC_WaitSignal

Enables or disables the wait-state insertion via wait signal, valid for Flash memory access in burst mode. This parameter can be a value of FSMC_Wait_Signal

Definition at line 132 of file stm32f10x_fsmc.h.

Referenced by FSMC_NORSRAMInit(), FSMC_NORSRAMStructInit(), LCD_FSMCConfig(), NOR_Init(), OneNAND_Init(), and SRAM_Init().

uint32_t FSMC_NORSRAMInitTypeDef::FSMC_WaitSignalActive

Specifies if the wait signal is asserted by the memory one clock cycle before the wait state or during the wait state, valid only when accessing memories in burst mode. This parameter can be a value of FSMC_Wait_Timing

Definition at line 124 of file stm32f10x_fsmc.h.

Referenced by FSMC_NORSRAMInit(), FSMC_NORSRAMStructInit(), LCD_FSMCConfig(), NOR_Init(), OneNAND_Init(), and SRAM_Init().

uint32_t FSMC_NORSRAMInitTypeDef::FSMC_WaitSignalPolarity

Specifies the wait signal polarity, valid only when accessing the Flash memory in burst mode. This parameter can be a value of FSMC_Wait_Signal_Polarity

Definition at line 116 of file stm32f10x_fsmc.h.

Referenced by FSMC_NORSRAMInit(), FSMC_NORSRAMStructInit(), LCD_FSMCConfig(), NOR_Init(), OneNAND_Init(), and SRAM_Init().

uint32_t FSMC_NORSRAMInitTypeDef::FSMC_WrapMode

Enables or disables the Wrapped burst access mode for Flash memory, valid only when accessing Flash memories in burst mode. This parameter can be a value of FSMC_Wrap_Mode

Definition at line 120 of file stm32f10x_fsmc.h.

Referenced by FSMC_NORSRAMInit(), FSMC_NORSRAMStructInit(), LCD_FSMCConfig(), NOR_Init(), OneNAND_Init(), and SRAM_Init().

uint32_t FSMC_NORSRAMInitTypeDef::FSMC_WriteBurst

Enables or disables the write burst operation. This parameter can be a value of FSMC_Write_Burst

Definition at line 139 of file stm32f10x_fsmc.h.

Referenced by FSMC_NORSRAMInit(), FSMC_NORSRAMStructInit(), LCD_FSMCConfig(), NOR_Init(), OneNAND_Init(), and SRAM_Init().

uint32_t FSMC_NORSRAMInitTypeDef::FSMC_WriteOperation

Enables or disables the write operation in the selected bank by the FSMC. This parameter can be a value of FSMC_Write_Operation

Definition at line 129 of file stm32f10x_fsmc.h.

Referenced by FSMC_NORSRAMInit(), FSMC_NORSRAMStructInit(), LCD_FSMCConfig(), NOR_Init(), OneNAND_Init(), and SRAM_Init().

FSMC_NORSRAMTimingInitTypeDef* FSMC_NORSRAMInitTypeDef::FSMC_WriteTimingStruct

Timing Parameters for write access if the ExtendedMode is used

Definition at line 144 of file stm32f10x_fsmc.h.

Referenced by FSMC_NORSRAMInit(), FSMC_NORSRAMStructInit(), LCD_FSMCConfig(), NOR_Init(), OneNAND_Init(), and SRAM_Init().

The documentation for this struct was generated from the following file:
  • stm32f10x_fsmc.h


STM32F10x Standard Peripherals Firmware Library: FSMC_NORSRAMTimingInitTypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

FSMC_NORSRAMTimingInitTypeDef Struct Reference
FSMC_Exported_Types

Timing parameters For NOR/SRAM Banks. More...

#include <stm32f10x_fsmc.h>

Data Fields

uint32_t | FSMC_AccessMode
uint32_t | FSMC_AddressHoldTime
uint32_t | FSMC_AddressSetupTime
uint32_t | FSMC_BusTurnAroundDuration
uint32_t | FSMC_CLKDivision
uint32_t | FSMC_DataLatency
uint32_t | FSMC_DataSetupTime

Detailed Description

Timing parameters For NOR/SRAM Banks.

Definition at line 50 of file stm32f10x_fsmc.h.

Field Documentation

uint32_t FSMC_NORSRAMTimingInitTypeDef::FSMC_AccessMode

Specifies the asynchronous access mode. This parameter can be a value of FSMC_Access_Mode

Definition at line 84 of file stm32f10x_fsmc.h.

Referenced by FSMC_NORSRAMInit(), FSMC_NORSRAMStructInit(), LCD_FSMCConfig(), NOR_Init(), OneNAND_Init(), and SRAM_Init().

uint32_t FSMC_NORSRAMTimingInitTypeDef::FSMC_AddressHoldTime

Defines the number of HCLK cycles to configure the duration of the address hold time. This parameter can be a value between 0 and 0xF.

Note:
: It is not used with synchronous NOR Flash memories.

Definition at line 57 of file stm32f10x_fsmc.h.

Referenced by FSMC_NORSRAMInit(), FSMC_NORSRAMStructInit(), LCD_FSMCConfig(), NOR_Init(), OneNAND_Init(), and SRAM_Init().

uint32_t FSMC_NORSRAMTimingInitTypeDef::FSMC_AddressSetupTime

Defines the number of HCLK cycles to configure the duration of the address setup time. This parameter can be a value between 0 and 0xF.

Note:
: It is not used with synchronous NOR Flash memories.

Definition at line 52 of file stm32f10x_fsmc.h.

Referenced by FSMC_NORSRAMInit(), FSMC_NORSRAMStructInit(), LCD_FSMCConfig(), NOR_Init(), OneNAND_Init(), and SRAM_Init().

uint32_t FSMC_NORSRAMTimingInitTypeDef::FSMC_BusTurnAroundDuration

Defines the number of HCLK cycles to configure the duration of the bus turnaround. This parameter can be a value between 0 and 0xF.

Note:
: It is only used for multiplexed NOR Flash memories.

Definition at line 67 of file stm32f10x_fsmc.h.

Referenced by FSMC_NORSRAMInit(), FSMC_NORSRAMStructInit(), LCD_FSMCConfig(), NOR_Init(), OneNAND_Init(), and SRAM_Init().

uint32_t FSMC_NORSRAMTimingInitTypeDef::FSMC_CLKDivision

Defines the period of CLK clock output signal, expressed in number of HCLK cycles. This parameter can be a value between 1 and 0xF.

Note:
: This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses.

Definition at line 72 of file stm32f10x_fsmc.h.

Referenced by FSMC_NORSRAMInit(), FSMC_NORSRAMStructInit(), LCD_FSMCConfig(), NOR_Init(), OneNAND_Init(), and SRAM_Init().

uint32_t FSMC_NORSRAMTimingInitTypeDef::FSMC_DataLatency

Defines the number of memory clock cycles to issue to the memory before getting the first data. The value of this parameter depends on the memory type as shown below:

  • It must be set to 0 in case of a CRAM
  • It is don't care in asynchronous NOR, SRAM or ROM accesses
  • It may assume a value between 0 and 0xF in NOR Flash memories with synchronous burst mode enable

Definition at line 76 of file stm32f10x_fsmc.h.

Referenced by FSMC_NORSRAMInit(), FSMC_NORSRAMStructInit(), LCD_FSMCConfig(), NOR_Init(), OneNAND_Init(), and SRAM_Init().

uint32_t FSMC_NORSRAMTimingInitTypeDef::FSMC_DataSetupTime

Defines the number of HCLK cycles to configure the duration of the data setup time. This parameter can be a value between 0 and 0xFF.

Note:
: It is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories.

Definition at line 62 of file stm32f10x_fsmc.h.

Referenced by FSMC_NORSRAMInit(), FSMC_NORSRAMStructInit(), LCD_FSMCConfig(), NOR_Init(), OneNAND_Init(), and SRAM_Init().

The documentation for this struct was generated from the following file:
  • stm32f10x_fsmc.h


STM32F10x Standard Peripherals Firmware Library: FSMC_PCCARDInitTypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

FSMC_PCCARDInitTypeDef Struct Reference
FSMC_Exported_Types

FSMC PCCARD Init structure definition. More...

#include <stm32f10x_fsmc.h>

Data Fields

FSMC_NAND_PCCARDTimingInitTypeDef * FSMC_AttributeSpaceTimingStruct
FSMC_NAND_PCCARDTimingInitTypeDef * FSMC_CommonSpaceTimingStruct
FSMC_NAND_PCCARDTimingInitTypeDef * FSMC_IOSpaceTimingStruct
uint32_t | FSMC_TARSetupTime
uint32_t | FSMC_TCLRSetupTime
uint32_t | FSMC_Waitfeature

Detailed Description

FSMC PCCARD Init structure definition.

Definition at line 217 of file stm32f10x_fsmc.h.

Field Documentation

FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_PCCARDInitTypeDef::FSMC_AttributeSpaceTimingStruct

FSMC Attribute Space Timing

Definition at line 233 of file stm32f10x_fsmc.h.

Referenced by FSMC_PCCARDInit(), and FSMC_PCCARDStructInit().

FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_PCCARDInitTypeDef::FSMC_CommonSpaceTimingStruct

FSMC Common Space Timing

Definition at line 231 of file stm32f10x_fsmc.h.

Referenced by FSMC_PCCARDInit(), and FSMC_PCCARDStructInit().

FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_PCCARDInitTypeDef::FSMC_IOSpaceTimingStruct

FSMC IO Space Timing

Definition at line 235 of file stm32f10x_fsmc.h.

Referenced by FSMC_PCCARDInit(), and FSMC_PCCARDStructInit().

uint32_t FSMC_PCCARDInitTypeDef::FSMC_TARSetupTime

Defines the number of HCLK cycles to configure the delay between ALE low and RE low. This parameter can be a number between 0x0 and 0xFF

Definition at line 226 of file stm32f10x_fsmc.h.

Referenced by FSMC_PCCARDInit(), and FSMC_PCCARDStructInit().

uint32_t FSMC_PCCARDInitTypeDef::FSMC_TCLRSetupTime

Defines the number of HCLK cycles to configure the delay between CLE low and RE low. This parameter can be a value between 0 and 0xFF.

Definition at line 222 of file stm32f10x_fsmc.h.

Referenced by FSMC_PCCARDInit(), and FSMC_PCCARDStructInit().

uint32_t FSMC_PCCARDInitTypeDef::FSMC_Waitfeature

Enables or disables the Wait feature for the Memory Bank. This parameter can be any value of FSMC_Wait_feature

Definition at line 219 of file stm32f10x_fsmc.h.

Referenced by FSMC_PCCARDInit(), and FSMC_PCCARDStructInit().

The documentation for this struct was generated from the following file:
  • stm32f10x_fsmc.h


STM32F10x Standard Peripherals Firmware Library: FSMC_NORSRAM_Bank

Defines

FSMC_NORSRAM_Bank

FSMC_Exported_Constants

Defines

#define | FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000)
#define | FSMC_Bank1_NORSRAM2 ((uint32_t)0x00000002)
#define | FSMC_Bank1_NORSRAM3 ((uint32_t)0x00000004)
#define | FSMC_Bank1_NORSRAM4 ((uint32_t)0x00000006)

Define Documentation

#define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000)

Definition at line 249 of file stm32f10x_fsmc.h.

Referenced by FSMC_NORSRAMDeInit(), FSMC_NORSRAMStructInit(), and OneNAND_Init().

#define FSMC_Bank1_NORSRAM2 ((uint32_t)0x00000002)

Definition at line 250 of file stm32f10x_fsmc.h.

Referenced by NOR_Init().

#define FSMC_Bank1_NORSRAM3 ((uint32_t)0x00000004)

Definition at line 251 of file stm32f10x_fsmc.h.

Referenced by SRAM_Init().

#define FSMC_Bank1_NORSRAM4 ((uint32_t)0x00000006)

Definition at line 252 of file stm32f10x_fsmc.h.

Referenced by LCD_DeInit(), and LCD_FSMCConfig().


STM32F10x Standard Peripherals Firmware Library: FSMC_NAND_Bank

Defines

FSMC_NAND_Bank

FSMC_Exported_Constants

Defines

#define | FSMC_Bank2_NAND ((uint32_t)0x00000010)
#define | FSMC_Bank3_NAND ((uint32_t)0x00000100)

Define Documentation

#define FSMC_Bank2_NAND ((uint32_t)0x00000010)

Definition at line 260 of file stm32f10x_fsmc.h.

Referenced by FSMC_ClearFlag(), FSMC_ClearITPendingBit(), FSMC_GetECC(), FSMC_GetFlagStatus(), FSMC_GetITStatus(), FSMC_ITConfig(), FSMC_NANDCmd(), FSMC_NANDDeInit(), FSMC_NANDECCCmd(), FSMC_NANDInit(), FSMC_NANDStructInit(), and NAND_Init().

#define FSMC_Bank3_NAND ((uint32_t)0x00000100)

Definition at line 261 of file stm32f10x_fsmc.h.

Referenced by FSMC_ClearFlag(), FSMC_ClearITPendingBit(), FSMC_GetFlagStatus(), FSMC_GetITStatus(), and FSMC_ITConfig().


STM32F10x Standard Peripherals Firmware Library: FSMC_PCCARD_Bank

Defines

FSMC_PCCARD_Bank

FSMC_Exported_Constants

Defines

#define FSMC_Bank4_PCCARD ((uint32_t)0x00001000)

Define Documentation

#define FSMC_Bank4_PCCARD ((uint32_t)0x00001000)

Definition at line 269 of file stm32f10x_fsmc.h.


STM32F10x Standard Peripherals Firmware Library: FSMC_Data_Address_Bus_Multiplexing

Defines

FSMC_Data_Address_Bus_Multiplexing

NOR_SRAM_Controller

Defines

#define | FSMC_DataAddressMux_Disable ((uint32_t)0x00000000)
#define | FSMC_DataAddressMux_Enable ((uint32_t)0x00000002)
#define | IS_FSMC_MUX(MUX)

Define Documentation

#define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000)

Definition at line 298 of file stm32f10x_fsmc.h.

Referenced by LCD_FSMCConfig(), NOR_Init(), OneNAND_Init(), and SRAM_Init().

#define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002)

Definition at line 299 of file stm32f10x_fsmc.h.

Referenced by FSMC_NORSRAMStructInit().

#define IS_FSMC_MUX ( MUX )
Value:
(((MUX) == FSMC_DataAddressMux_Disable) || \
                          ((MUX) == FSMC_DataAddressMux_Enable))

Definition at line 300 of file stm32f10x_fsmc.h.

Referenced by FSMC_NORSRAMInit().


STM32F10x Standard Peripherals Firmware Library: FSMC_Memory_Type

Defines

FSMC_Memory_Type

NOR_SRAM_Controller

Defines

#define | FSMC_MemoryType_NOR ((uint32_t)0x00000008)
#define | FSMC_MemoryType_PSRAM ((uint32_t)0x00000004)
#define | FSMC_MemoryType_SRAM ((uint32_t)0x00000000)
#define | IS_FSMC_MEMORY(MEMORY)

Define Documentation

#define FSMC_MemoryType_NOR ((uint32_t)0x00000008)

Definition at line 313 of file stm32f10x_fsmc.h.

Referenced by FSMC_NORSRAMInit(), NOR_Init(), and OneNAND_Init().

#define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004)

Definition at line 312 of file stm32f10x_fsmc.h.

#define FSMC_MemoryType_SRAM ((uint32_t)0x00000000)

Definition at line 311 of file stm32f10x_fsmc.h.

Referenced by FSMC_NORSRAMStructInit(), LCD_FSMCConfig(), and SRAM_Init().

#define IS_FSMC_MEMORY ( MEMORY )
Value:
(((MEMORY) == FSMC_MemoryType_SRAM) || \
                                ((MEMORY) == FSMC_MemoryType_PSRAM)|| \
                                ((MEMORY) == FSMC_MemoryType_NOR))

Definition at line 314 of file stm32f10x_fsmc.h.

Referenced by FSMC_NORSRAMInit().


STM32F10x Standard Peripherals Firmware Library: FSMC_Data_Width

Defines

FSMC_Data_Width

NOR_SRAM_Controller

Defines

#define | FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010)
#define | FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000)
#define | IS_FSMC_MEMORY_WIDTH(WIDTH)

Define Documentation

#define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010)

Definition at line 327 of file stm32f10x_fsmc.h.

Referenced by FSMC_PCCARDInit(), LCD_FSMCConfig(), NOR_Init(), OneNAND_Init(), and SRAM_Init().

#define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000)

Definition at line 326 of file stm32f10x_fsmc.h.

Referenced by FSMC_NANDStructInit(), FSMC_NORSRAMStructInit(), and NAND_Init().

#define IS_FSMC_MEMORY_WIDTH ( WIDTH )
Value:
(((WIDTH) == FSMC_MemoryDataWidth_8b) || \
                                     ((WIDTH) == FSMC_MemoryDataWidth_16b))

Definition at line 328 of file stm32f10x_fsmc.h.

Referenced by FSMC_NANDInit(), and FSMC_NORSRAMInit().


STM32F10x Standard Peripherals Firmware Library: FSMC_Burst_Access_Mode

Defines

FSMC_Burst_Access_Mode

NOR_SRAM_Controller

Defines

#define | FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000)
#define | FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100)
#define | IS_FSMC_BURSTMODE(STATE)

Define Documentation

#define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000)

Definition at line 339 of file stm32f10x_fsmc.h.

Referenced by FSMC_NORSRAMStructInit(), LCD_FSMCConfig(), NOR_Init(), and SRAM_Init().

#define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100)

Definition at line 340 of file stm32f10x_fsmc.h.

Referenced by OneNAND_Init().

#define IS_FSMC_BURSTMODE ( STATE )
Value:
(((STATE) == FSMC_BurstAccessMode_Disable) || \
                                  ((STATE) == FSMC_BurstAccessMode_Enable))

Definition at line 341 of file stm32f10x_fsmc.h.

Referenced by FSMC_NORSRAMInit().


STM32F10x Standard Peripherals Firmware Library: FSMC_AsynchronousWait

Defines

FSMC_AsynchronousWait

NOR_SRAM_Controller

Defines

#define | FSMC_AsynchronousWait_Disable ((uint32_t)0x00000000)
#define | FSMC_AsynchronousWait_Enable ((uint32_t)0x00008000)
#define | IS_FSMC_ASYNWAIT(STATE)

Define Documentation

#define FSMC_AsynchronousWait_Disable ((uint32_t)0x00000000)

Definition at line 350 of file stm32f10x_fsmc.h.

Referenced by FSMC_NORSRAMStructInit(), LCD_FSMCConfig(), NOR_Init(), OneNAND_Init(), and SRAM_Init().

#define FSMC_AsynchronousWait_Enable ((uint32_t)0x00008000)

Definition at line 351 of file stm32f10x_fsmc.h.

#define IS_FSMC_ASYNWAIT ( STATE )
Value:
(((STATE) == FSMC_AsynchronousWait_Disable) || \
                                 ((STATE) == FSMC_AsynchronousWait_Enable))

Definition at line 352 of file stm32f10x_fsmc.h.

Referenced by FSMC_NORSRAMInit().


STM32F10x Standard Peripherals Firmware Library: FSMC_Wait_Signal_Polarity

Defines

FSMC_Wait_Signal_Polarity

NOR_SRAM_Controller

Defines

#define | FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200)
#define | FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000)
#define | IS_FSMC_WAIT_POLARITY(POLARITY)

Define Documentation

#define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200)

Definition at line 364 of file stm32f10x_fsmc.h.

#define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000)

Definition at line 363 of file stm32f10x_fsmc.h.

Referenced by FSMC_NORSRAMStructInit(), LCD_FSMCConfig(), NOR_Init(), OneNAND_Init(), and SRAM_Init().

#define IS_FSMC_WAIT_POLARITY ( POLARITY )
Value:
(((POLARITY) == FSMC_WaitSignalPolarity_Low) || \
                                         ((POLARITY) == FSMC_WaitSignalPolarity_High))

Definition at line 365 of file stm32f10x_fsmc.h.

Referenced by FSMC_NORSRAMInit().


STM32F10x Standard Peripherals Firmware Library: FSMC_Wrap_Mode

Defines

FSMC_Wrap_Mode

NOR_SRAM_Controller

Defines

#define | FSMC_WrapMode_Disable ((uint32_t)0x00000000)
#define | FSMC_WrapMode_Enable ((uint32_t)0x00000400)
#define | IS_FSMC_WRAP_MODE(MODE)

Define Documentation

#define FSMC_WrapMode_Disable ((uint32_t)0x00000000)

Definition at line 376 of file stm32f10x_fsmc.h.

Referenced by FSMC_NORSRAMStructInit(), LCD_FSMCConfig(), NOR_Init(), OneNAND_Init(), and SRAM_Init().

#define FSMC_WrapMode_Enable ((uint32_t)0x00000400)

Definition at line 377 of file stm32f10x_fsmc.h.

#define IS_FSMC_WRAP_MODE ( MODE )
Value:
(((MODE) == FSMC_WrapMode_Disable) || \
                                 ((MODE) == FSMC_WrapMode_Enable))

Definition at line 378 of file stm32f10x_fsmc.h.

Referenced by FSMC_NORSRAMInit().


STM32F10x Standard Peripherals Firmware Library: FSMC_Wait_Timing

Defines

FSMC_Wait_Timing

NOR_SRAM_Controller

Defines

#define | FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000)
#define | FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800)
#define | IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE)

Define Documentation

#define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000)

Definition at line 389 of file stm32f10x_fsmc.h.

Referenced by FSMC_NORSRAMStructInit(), LCD_FSMCConfig(), NOR_Init(), OneNAND_Init(), and SRAM_Init().

#define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800)

Definition at line 390 of file stm32f10x_fsmc.h.

#define IS_FSMC_WAIT_SIGNAL_ACTIVE ( ACTIVE )
Value:
(((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \
                                            ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState))

Definition at line 391 of file stm32f10x_fsmc.h.

Referenced by FSMC_NORSRAMInit().


STM32F10x Standard Peripherals Firmware Library: FSMC_Write_Operation

Defines

FSMC_Write_Operation

NOR_SRAM_Controller

Defines

#define | FSMC_WriteOperation_Disable ((uint32_t)0x00000000)
#define | FSMC_WriteOperation_Enable ((uint32_t)0x00001000)
#define | IS_FSMC_WRITE_OPERATION(OPERATION)

Define Documentation

#define FSMC_WriteOperation_Disable ((uint32_t)0x00000000)

Definition at line 402 of file stm32f10x_fsmc.h.

#define FSMC_WriteOperation_Enable ((uint32_t)0x00001000)

Definition at line 403 of file stm32f10x_fsmc.h.

Referenced by FSMC_NORSRAMStructInit(), LCD_FSMCConfig(), NOR_Init(), OneNAND_Init(), and SRAM_Init().

#define IS_FSMC_WRITE_OPERATION ( OPERATION )
Value:
(((OPERATION) == FSMC_WriteOperation_Disable) || \
                                            ((OPERATION) == FSMC_WriteOperation_Enable))

Definition at line 404 of file stm32f10x_fsmc.h.

Referenced by FSMC_NORSRAMInit().


STM32F10x Standard Peripherals Firmware Library: FSMC_Wait_Signal

Defines

FSMC_Wait_Signal

NOR_SRAM_Controller

Defines

#define | FSMC_WaitSignal_Disable ((uint32_t)0x00000000)
#define | FSMC_WaitSignal_Enable ((uint32_t)0x00002000)
#define | IS_FSMC_WAITE_SIGNAL(SIGNAL)

Define Documentation

#define FSMC_WaitSignal_Disable ((uint32_t)0x00000000)

Definition at line 415 of file stm32f10x_fsmc.h.

Referenced by LCD_FSMCConfig(), NOR_Init(), and SRAM_Init().

#define FSMC_WaitSignal_Enable ((uint32_t)0x00002000)

Definition at line 416 of file stm32f10x_fsmc.h.

Referenced by FSMC_NORSRAMStructInit(), and OneNAND_Init().

#define IS_FSMC_WAITE_SIGNAL ( SIGNAL )
Value:
(((SIGNAL) == FSMC_WaitSignal_Disable) || \
                                      ((SIGNAL) == FSMC_WaitSignal_Enable))

Definition at line 417 of file stm32f10x_fsmc.h.

Referenced by FSMC_NORSRAMInit().


STM32F10x Standard Peripherals Firmware Library: FSMC_Extended_Mode

Defines

FSMC_Extended_Mode

NOR_SRAM_Controller

Defines

#define | FSMC_ExtendedMode_Disable ((uint32_t)0x00000000)
#define | FSMC_ExtendedMode_Enable ((uint32_t)0x00004000)
#define | IS_FSMC_EXTENDED_MODE(MODE)

Define Documentation

#define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000)

Definition at line 427 of file stm32f10x_fsmc.h.

Referenced by FSMC_NORSRAMStructInit(), LCD_FSMCConfig(), NOR_Init(), OneNAND_Init(), and SRAM_Init().

#define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000)

Definition at line 428 of file stm32f10x_fsmc.h.

Referenced by FSMC_NORSRAMInit().

#define IS_FSMC_EXTENDED_MODE ( MODE )
Value:
(((MODE) == FSMC_ExtendedMode_Disable) || \
                                     ((MODE) == FSMC_ExtendedMode_Enable))

Definition at line 430 of file stm32f10x_fsmc.h.

Referenced by FSMC_NORSRAMInit().


STM32F10x Standard Peripherals Firmware Library: FSMC_Write_Burst

Defines

FSMC_Write_Burst

NOR_SRAM_Controller

Defines

#define | FSMC_WriteBurst_Disable ((uint32_t)0x00000000)
#define | FSMC_WriteBurst_Enable ((uint32_t)0x00080000)
#define | IS_FSMC_WRITE_BURST(BURST)

Define Documentation

#define FSMC_WriteBurst_Disable ((uint32_t)0x00000000)

Definition at line 441 of file stm32f10x_fsmc.h.

Referenced by FSMC_NORSRAMStructInit(), LCD_FSMCConfig(), NOR_Init(), OneNAND_Init(), and SRAM_Init().

#define FSMC_WriteBurst_Enable ((uint32_t)0x00080000)

Definition at line 442 of file stm32f10x_fsmc.h.

#define IS_FSMC_WRITE_BURST ( BURST )
Value:
(((BURST) == FSMC_WriteBurst_Disable) || \
                                    ((BURST) == FSMC_WriteBurst_Enable))

Definition at line 443 of file stm32f10x_fsmc.h.

Referenced by FSMC_NORSRAMInit().


STM32F10x Standard Peripherals Firmware Library: FSMC_Address_Setup_Time

Defines

FSMC_Address_Setup_Time

NOR_SRAM_Controller

Defines

#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF)

Define Documentation

#define IS_FSMC_ADDRESS_SETUP_TIME ( TIME ) ((TIME) <= 0xF)

Definition at line 453 of file stm32f10x_fsmc.h.

Referenced by FSMC_NORSRAMInit().


STM32F10x Standard Peripherals Firmware Library: FSMC_Address_Hold_Time

Defines

FSMC_Address_Hold_Time

NOR_SRAM_Controller

Defines

#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF)

Define Documentation

#define IS_FSMC_ADDRESS_HOLD_TIME ( TIME ) ((TIME) <= 0xF)

Definition at line 463 of file stm32f10x_fsmc.h.

Referenced by FSMC_NORSRAMInit().


STM32F10x Standard Peripherals Firmware Library: FSMC_Data_Setup_Time

Defines

FSMC_Data_Setup_Time

NOR_SRAM_Controller

Defines

#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF))

Define Documentation

#define IS_FSMC_DATASETUP_TIME ( TIME ) (((TIME) > 0) && ((TIME) <= 0xFF))

Definition at line 473 of file stm32f10x_fsmc.h.

Referenced by FSMC_NORSRAMInit().


STM32F10x Standard Peripherals Firmware Library: FSMC_Bus_Turn_around_Duration

Defines

FSMC_Bus_Turn_around_Duration

NOR_SRAM_Controller

Defines

#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF)

Define Documentation

#define IS_FSMC_TURNAROUND_TIME ( TIME ) ((TIME) <= 0xF)

Definition at line 483 of file stm32f10x_fsmc.h.

Referenced by FSMC_NORSRAMInit().


STM32F10x Standard Peripherals Firmware Library: FSMC_CLK_Division

Defines

FSMC_CLK_Division

NOR_SRAM_Controller

Defines

#define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF)

Define Documentation

#define IS_FSMC_CLK_DIV ( DIV ) ((DIV) <= 0xF)

Definition at line 493 of file stm32f10x_fsmc.h.

Referenced by FSMC_NORSRAMInit().


STM32F10x Standard Peripherals Firmware Library: FSMC_Data_Latency

Defines

FSMC_Data_Latency

NOR_SRAM_Controller

Defines

#define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF)

Define Documentation

#define IS_FSMC_DATA_LATENCY ( LATENCY ) ((LATENCY) <= 0xF)

Definition at line 503 of file stm32f10x_fsmc.h.

Referenced by FSMC_NORSRAMInit().


STM32F10x Standard Peripherals Firmware Library: FSMC_Access_Mode

Defines

FSMC_Access_Mode

NOR_SRAM_Controller

Defines

#define | FSMC_AccessMode_A ((uint32_t)0x00000000)
#define | FSMC_AccessMode_B ((uint32_t)0x10000000)
#define | FSMC_AccessMode_C ((uint32_t)0x20000000)
#define | FSMC_AccessMode_D ((uint32_t)0x30000000)
#define | IS_FSMC_ACCESS_MODE(MODE)

Define Documentation

#define FSMC_AccessMode_A ((uint32_t)0x00000000)

Definition at line 513 of file stm32f10x_fsmc.h.

Referenced by FSMC_NORSRAMStructInit(), LCD_FSMCConfig(), and SRAM_Init().

#define FSMC_AccessMode_B ((uint32_t)0x10000000)

Definition at line 514 of file stm32f10x_fsmc.h.

Referenced by NOR_Init(), and OneNAND_Init().

#define FSMC_AccessMode_C ((uint32_t)0x20000000)

Definition at line 515 of file stm32f10x_fsmc.h.

#define FSMC_AccessMode_D ((uint32_t)0x30000000)

Definition at line 516 of file stm32f10x_fsmc.h.

#define IS_FSMC_ACCESS_MODE ( MODE )
Value:
(((MODE) == FSMC_AccessMode_A) || \
                                   ((MODE) == FSMC_AccessMode_B) || \
                                   ((MODE) == FSMC_AccessMode_C) || \
                                   ((MODE) == FSMC_AccessMode_D))

Definition at line 517 of file stm32f10x_fsmc.h.

Referenced by FSMC_NORSRAMInit().


STM32F10x Standard Peripherals Firmware Library: FSMC_Wait_feature

Defines

FSMC_Wait_feature

NAND_PCCARD_Controller

Defines

#define | FSMC_Waitfeature_Disable ((uint32_t)0x00000000)
#define | FSMC_Waitfeature_Enable ((uint32_t)0x00000002)
#define | IS_FSMC_WAIT_FEATURE(FEATURE)

Define Documentation

#define FSMC_Waitfeature_Disable ((uint32_t)0x00000000)

Definition at line 538 of file stm32f10x_fsmc.h.

Referenced by FSMC_NANDStructInit(), and FSMC_PCCARDStructInit().

#define FSMC_Waitfeature_Enable ((uint32_t)0x00000002)

Definition at line 539 of file stm32f10x_fsmc.h.

Referenced by NAND_Init().

#define IS_FSMC_WAIT_FEATURE ( FEATURE )
Value:
(((FEATURE) == FSMC_Waitfeature_Disable) || \
                                       ((FEATURE) == FSMC_Waitfeature_Enable))

Definition at line 540 of file stm32f10x_fsmc.h.

Referenced by FSMC_NANDInit(), and FSMC_PCCARDInit().


STM32F10x Standard Peripherals Firmware Library: FSMC_ECC

Defines

FSMC_ECC

NAND_PCCARD_Controller

Defines

#define | FSMC_ECC_Disable ((uint32_t)0x00000000)
#define | FSMC_ECC_Enable ((uint32_t)0x00000040)
#define | IS_FSMC_ECC_STATE(STATE)

Define Documentation

#define FSMC_ECC_Disable ((uint32_t)0x00000000)

Definition at line 552 of file stm32f10x_fsmc.h.

Referenced by FSMC_NANDStructInit().

#define FSMC_ECC_Enable ((uint32_t)0x00000040)

Definition at line 553 of file stm32f10x_fsmc.h.

Referenced by NAND_Init().

#define IS_FSMC_ECC_STATE ( STATE )
Value:
(((STATE) == FSMC_ECC_Disable) || \
                                  ((STATE) == FSMC_ECC_Enable))

Definition at line 554 of file stm32f10x_fsmc.h.

Referenced by FSMC_NANDInit().


STM32F10x Standard Peripherals Firmware Library: FSMC_ECC_Page_Size

Defines

FSMC_ECC_Page_Size

NAND_PCCARD_Controller

Defines

#define | FSMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000)
#define | FSMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000)
#define | FSMC_ECCPageSize_256Bytes ((uint32_t)0x00000000)
#define | FSMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000)
#define | FSMC_ECCPageSize_512Bytes ((uint32_t)0x00020000)
#define | FSMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000)
#define | IS_FSMC_ECCPAGE_SIZE(SIZE)

Define Documentation

#define FSMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000)

Definition at line 567 of file stm32f10x_fsmc.h.

#define FSMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000)

Definition at line 568 of file stm32f10x_fsmc.h.

#define FSMC_ECCPageSize_256Bytes ((uint32_t)0x00000000)

Definition at line 565 of file stm32f10x_fsmc.h.

Referenced by FSMC_NANDStructInit().

#define FSMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000)

Definition at line 569 of file stm32f10x_fsmc.h.

#define FSMC_ECCPageSize_512Bytes ((uint32_t)0x00020000)

Definition at line 566 of file stm32f10x_fsmc.h.

Referenced by NAND_Init().

#define FSMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000)

Definition at line 570 of file stm32f10x_fsmc.h.

#define IS_FSMC_ECCPAGE_SIZE ( SIZE )
Value:
(((SIZE) == FSMC_ECCPageSize_256Bytes) || \
                                    ((SIZE) == FSMC_ECCPageSize_512Bytes) || \
                                    ((SIZE) == FSMC_ECCPageSize_1024Bytes) || \
                                    ((SIZE) == FSMC_ECCPageSize_2048Bytes) || \
                                    ((SIZE) == FSMC_ECCPageSize_4096Bytes) || \
                                    ((SIZE) == FSMC_ECCPageSize_8192Bytes))

Definition at line 571 of file stm32f10x_fsmc.h.

Referenced by FSMC_NANDInit().


STM32F10x Standard Peripherals Firmware Library: FSMC_TCLR_Setup_Time

Defines

FSMC_TCLR_Setup_Time

NAND_PCCARD_Controller

Defines

#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF)

Define Documentation

#define IS_FSMC_TCLR_TIME ( TIME ) ((TIME) <= 0xFF)

Definition at line 586 of file stm32f10x_fsmc.h.

Referenced by FSMC_NANDInit(), and FSMC_PCCARDInit().


STM32F10x Standard Peripherals Firmware Library: FSMC_TAR_Setup_Time

Defines

FSMC_TAR_Setup_Time

NAND_PCCARD_Controller

Defines

#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF)

Define Documentation

#define IS_FSMC_TAR_TIME ( TIME ) ((TIME) <= 0xFF)

Definition at line 596 of file stm32f10x_fsmc.h.

Referenced by FSMC_NANDInit(), and FSMC_PCCARDInit().


STM32F10x Standard Peripherals Firmware Library: FSMC_Setup_Time

Defines

FSMC_Setup_Time

NAND_PCCARD_Controller

Defines

#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF)

Define Documentation

#define IS_FSMC_SETUP_TIME ( TIME ) ((TIME) <= 0xFF)

Definition at line 606 of file stm32f10x_fsmc.h.

Referenced by FSMC_NANDInit(), and FSMC_PCCARDInit().


STM32F10x Standard Peripherals Firmware Library: FSMC_Wait_Setup_Time

Defines

FSMC_Wait_Setup_Time

NAND_PCCARD_Controller

Defines

#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF)

Define Documentation

#define IS_FSMC_WAIT_TIME ( TIME ) ((TIME) <= 0xFF)

Definition at line 616 of file stm32f10x_fsmc.h.

Referenced by FSMC_NANDInit(), and FSMC_PCCARDInit().


STM32F10x Standard Peripherals Firmware Library: FSMC_Hold_Setup_Time

Defines

FSMC_Hold_Setup_Time

NAND_PCCARD_Controller

Defines

#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF)

Define Documentation

#define IS_FSMC_HOLD_TIME ( TIME ) ((TIME) <= 0xFF)

Definition at line 626 of file stm32f10x_fsmc.h.

Referenced by FSMC_NANDInit(), and FSMC_PCCARDInit().


STM32F10x Standard Peripherals Firmware Library: FSMC_HiZ_Setup_Time

Defines

FSMC_HiZ_Setup_Time

NAND_PCCARD_Controller

Defines

#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF)

Define Documentation

#define IS_FSMC_HIZ_TIME ( TIME ) ((TIME) <= 0xFF)

Definition at line 636 of file stm32f10x_fsmc.h.

Referenced by FSMC_NANDInit(), and FSMC_PCCARDInit().


STM32F10x Standard Peripherals Firmware Library: FSMC_Interrupt_sources

Defines

FSMC_Interrupt_sources

NAND_PCCARD_Controller

Defines

#define | FSMC_IT_FallingEdge ((uint32_t)0x00000020)
#define | FSMC_IT_Level ((uint32_t)0x00000010)
#define | FSMC_IT_RisingEdge ((uint32_t)0x00000008)
#define | IS_FSMC_GET_IT(IT)
#define | IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000))

Define Documentation

#define FSMC_IT_FallingEdge ((uint32_t)0x00000020)

Definition at line 648 of file stm32f10x_fsmc.h.

#define FSMC_IT_Level ((uint32_t)0x00000010)

Definition at line 647 of file stm32f10x_fsmc.h.

#define FSMC_IT_RisingEdge ((uint32_t)0x00000008)

Definition at line 646 of file stm32f10x_fsmc.h.

#define IS_FSMC_GET_IT ( IT )
Value:
(((IT) == FSMC_IT_RisingEdge) || \
                            ((IT) == FSMC_IT_Level) || \
                            ((IT) == FSMC_IT_FallingEdge))

Definition at line 650 of file stm32f10x_fsmc.h.

Referenced by FSMC_GetITStatus().

#define IS_FSMC_IT ( IT ) ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000))

Definition at line 649 of file stm32f10x_fsmc.h.

Referenced by FSMC_ClearITPendingBit(), and FSMC_ITConfig().


STM32F10x Standard Peripherals Firmware Library: FSMC_Flags

Defines

FSMC_Flags

NAND_PCCARD_Controller

Defines

#define | FSMC_FLAG_FallingEdge ((uint32_t)0x00000004)
#define | FSMC_FLAG_FEMPT ((uint32_t)0x00000040)
#define | FSMC_FLAG_Level ((uint32_t)0x00000002)
#define | FSMC_FLAG_RisingEdge ((uint32_t)0x00000001)
#define | IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
#define | IS_FSMC_GET_FLAG(FLAG)

Define Documentation

#define FSMC_FLAG_FallingEdge ((uint32_t)0x00000004)

Definition at line 663 of file stm32f10x_fsmc.h.

#define FSMC_FLAG_FEMPT ((uint32_t)0x00000040)

Definition at line 664 of file stm32f10x_fsmc.h.

#define FSMC_FLAG_Level ((uint32_t)0x00000002)

Definition at line 662 of file stm32f10x_fsmc.h.

#define FSMC_FLAG_RisingEdge ((uint32_t)0x00000001)

Definition at line 661 of file stm32f10x_fsmc.h.

#define IS_FSMC_CLEAR_FLAG ( FLAG ) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))

Definition at line 670 of file stm32f10x_fsmc.h.

Referenced by FSMC_ClearFlag().

#define IS_FSMC_GET_FLAG ( FLAG )
Value:
(((FLAG) == FSMC_FLAG_RisingEdge) || \
                                ((FLAG) == FSMC_FLAG_Level) || \
                                ((FLAG) == FSMC_FLAG_FallingEdge) || \
                                ((FLAG) == FSMC_FLAG_FEMPT))

Definition at line 665 of file stm32f10x_fsmc.h.

Referenced by FSMC_GetFlagStatus().


STM32F10x Standard Peripherals Firmware Library: FSMC_Exported_Constants

Modules | Defines

FSMC_Exported_Constants

FSMC

Modules

FSMC_NORSRAM_Bank
FSMC_NAND_Bank
FSMC_PCCARD_Bank
NOR_SRAM_Controller
NAND_PCCARD_Controller

Defines

#define | IS_FSMC_GETFLAG_BANK(BANK)
#define | IS_FSMC_IT_BANK(BANK)
#define | IS_FSMC_NAND_BANK(BANK)
#define | IS_FSMC_NORSRAM_BANK(BANK)

Define Documentation

#define IS_FSMC_GETFLAG_BANK ( BANK )
Value:
(((BANK) == FSMC_Bank2_NAND) || \
                                    ((BANK) == FSMC_Bank3_NAND) || \
                                    ((BANK) == FSMC_Bank4_PCCARD))

Definition at line 282 of file stm32f10x_fsmc.h.

Referenced by FSMC_ClearFlag(), and FSMC_GetFlagStatus().

#define IS_FSMC_IT_BANK ( BANK )
Value:
(((BANK) == FSMC_Bank2_NAND) || \
                               ((BANK) == FSMC_Bank3_NAND) || \
                               ((BANK) == FSMC_Bank4_PCCARD))

Definition at line 286 of file stm32f10x_fsmc.h.

Referenced by FSMC_ClearITPendingBit(), FSMC_GetITStatus(), and FSMC_ITConfig().

#define IS_FSMC_NAND_BANK ( BANK )
Value:
(((BANK) == FSMC_Bank2_NAND) || \
                                 ((BANK) == FSMC_Bank3_NAND))

Definition at line 279 of file stm32f10x_fsmc.h.

Referenced by FSMC_NANDCmd(), FSMC_NANDDeInit(), FSMC_NANDECCCmd(), and FSMC_NANDInit().

#define IS_FSMC_NORSRAM_BANK ( BANK )
Value:
(((BANK) == FSMC_Bank1_NORSRAM1) || \
                                    ((BANK) == FSMC_Bank1_NORSRAM2) || \
                                    ((BANK) == FSMC_Bank1_NORSRAM3) || \
                                    ((BANK) == FSMC_Bank1_NORSRAM4))

Definition at line 274 of file stm32f10x_fsmc.h.

Referenced by FSMC_NORSRAMCmd(), FSMC_NORSRAMDeInit(), and FSMC_NORSRAMInit().


STM32F10x Standard Peripherals Firmware Library: FSMC_Exported_Macros

FSMC_Exported_Macros

FSMC


STM32F10x Standard Peripherals Firmware Library: FSMC_Exported_Functions

Functions

FSMC_Exported_Functions

FSMC

Functions

void | FSMC_ClearFlag (uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
Clears the FSMC's pending flags.
void | FSMC_ClearITPendingBit (uint32_t FSMC_Bank, uint32_t FSMC_IT)
Clears the FSMC's interrupt pending bits.
uint32_t | FSMC_GetECC (uint32_t FSMC_Bank)
Returns the error correction code register value.
FlagStatus | FSMC_GetFlagStatus (uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
Checks whether the specified FSMC flag is set or not.
ITStatus | FSMC_GetITStatus (uint32_t FSMC_Bank, uint32_t FSMC_IT)
Checks whether the specified FSMC interrupt has occurred or not.
void | FSMC_ITConfig (uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState)
Enables or disables the specified FSMC interrupts.
void | FSMC_NANDCmd (uint32_t FSMC_Bank, FunctionalState NewState)
Enables or disables the specified NAND Memory Bank.
void | FSMC_NANDDeInit (uint32_t FSMC_Bank)
Deinitializes the FSMC NAND Banks registers to their default reset values.
void | FSMC_NANDECCCmd (uint32_t FSMC_Bank, FunctionalState NewState)
Enables or disables the FSMC NAND ECC feature.
void | FSMC_NANDInit (FSMC_NANDInitTypeDef *FSMC_NANDInitStruct)
Initializes the FSMC NAND Banks according to the specified parameters in the FSMC_NANDInitStruct.
void | FSMC_NANDStructInit (FSMC_NANDInitTypeDef *FSMC_NANDInitStruct)
Fills each FSMC_NANDInitStruct member with its default value.
void | FSMC_NORSRAMCmd (uint32_t FSMC_Bank, FunctionalState NewState)
Enables or disables the specified NOR/SRAM Memory Bank.
void | FSMC_NORSRAMDeInit (uint32_t FSMC_Bank)
Deinitializes the FSMC NOR/SRAM Banks registers to their default reset values.
void | FSMC_NORSRAMInit (FSMC_NORSRAMInitTypeDef *FSMC_NORSRAMInitStruct)
Initializes the FSMC NOR/SRAM Banks according to the specified parameters in the FSMC_NORSRAMInitStruct.
void | FSMC_NORSRAMStructInit (FSMC_NORSRAMInitTypeDef *FSMC_NORSRAMInitStruct)
Fills each FSMC_NORSRAMInitStruct member with its default value.
void | FSMC_PCCARDCmd (FunctionalState NewState)
Enables or disables the PCCARD Memory Bank.
void | FSMC_PCCARDDeInit (void)
Deinitializes the FSMC PCCARD Bank registers to their default reset values.
void | FSMC_PCCARDInit (FSMC_PCCARDInitTypeDef *FSMC_PCCARDInitStruct)
Initializes the FSMC PCCARD Bank according to the specified parameters in the FSMC_PCCARDInitStruct.
void | FSMC_PCCARDStructInit (FSMC_PCCARDInitTypeDef *FSMC_PCCARDInitStruct)
Fills each FSMC_PCCARDInitStruct member with its default value.

Function Documentation

void FSMC_ClearFlag | ( | uint32_t | FSMC_Bank,
 |  | uint32_t | FSMC_FLAG
 | ) |  |

Clears the FSMC's pending flags.

Parameters:
FSMC_Bank,: specifies the FSMC Bank to be used This parameter can be one of the following values:

  • FSMC_Bank2_NAND: FSMC Bank2 NAND
  • FSMC_Bank3_NAND: FSMC Bank3 NAND
  • FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
FSMC_FLAG,: specifies the flag to clear. This parameter can be any combination of the following values:

  • FSMC_FLAG_RisingEdge: Rising egde detection Flag.
  • FSMC_FLAG_Level: Level detection Flag.
  • FSMC_FLAG_FallingEdge: Falling egde detection Flag.
Return values:
None

Definition at line 747 of file stm32f10x_fsmc.c.

References assert_param, FSMC_Bank2, FSMC_Bank2_NAND, FSMC_Bank3, FSMC_Bank3_NAND, FSMC_Bank4, IS_FSMC_CLEAR_FLAG, and IS_FSMC_GETFLAG_BANK.

void FSMC_ClearITPendingBit | ( | uint32_t | FSMC_Bank,
 |  | uint32_t | FSMC_IT
 | ) |  |

Clears the FSMC's interrupt pending bits.

Parameters:
FSMC_Bank,: specifies the FSMC Bank to be used This parameter can be one of the following values:

  • FSMC_Bank2_NAND: FSMC Bank2 NAND
  • FSMC_Bank3_NAND: FSMC Bank3 NAND
  • FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
FSMC_IT,: specifies the interrupt pending bit to clear. This parameter can be any combination of the following values:

  • FSMC_IT_RisingEdge: Rising edge detection interrupt.
  • FSMC_IT_Level: Level edge detection interrupt.
  • FSMC_IT_FallingEdge: Falling edge detection interrupt.
Return values:
None

Definition at line 833 of file stm32f10x_fsmc.c.

References assert_param, FSMC_Bank2, FSMC_Bank2_NAND, FSMC_Bank3, FSMC_Bank3_NAND, FSMC_Bank4, IS_FSMC_IT, and IS_FSMC_IT_BANK.

uint32_t FSMC_GetECC ( uint32_t FSMC_Bank )

Returns the error correction code register value.

Parameters:
FSMC_Bank,: specifies the FSMC Bank to be used This parameter can be one of the following values:

  • FSMC_Bank2_NAND: FSMC Bank2 NAND
  • FSMC_Bank3_NAND: FSMC Bank3 NAND
Return values:
The Error Correction Code (ECC) value.

Definition at line 603 of file stm32f10x_fsmc.c.

References FSMC_Bank2, FSMC_Bank2_NAND, and FSMC_Bank3.

FlagStatus FSMC_GetFlagStatus | ( | uint32_t | FSMC_Bank,
 |  | uint32_t | FSMC_FLAG
 | ) |  |

Checks whether the specified FSMC flag is set or not.

Parameters:
FSMC_Bank,: specifies the FSMC Bank to be used This parameter can be one of the following values:

  • FSMC_Bank2_NAND: FSMC Bank2 NAND
  • FSMC_Bank3_NAND: FSMC Bank3 NAND
  • FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
FSMC_FLAG,: specifies the flag to check. This parameter can be one of the following values:

  • FSMC_FLAG_RisingEdge: Rising egde detection Flag.
  • FSMC_FLAG_Level: Level detection Flag.
  • FSMC_FLAG_FallingEdge: Falling egde detection Flag.
  • FSMC_FLAG_FEMPT: Fifo empty Flag.
Return values:
The new state of FSMC_FLAG (SET or RESET).

Definition at line 697 of file stm32f10x_fsmc.c.

References assert_param, FSMC_Bank2, FSMC_Bank2_NAND, FSMC_Bank3, FSMC_Bank3_NAND, FSMC_Bank4, IS_FSMC_GET_FLAG, IS_FSMC_GETFLAG_BANK, RESET, and SET.

ITStatus FSMC_GetITStatus | ( | uint32_t | FSMC_Bank,
 |  | uint32_t | FSMC_IT
 | ) |  |

Checks whether the specified FSMC interrupt has occurred or not.

Parameters:
FSMC_Bank,: specifies the FSMC Bank to be used This parameter can be one of the following values:

  • FSMC_Bank2_NAND: FSMC Bank2 NAND
  • FSMC_Bank3_NAND: FSMC Bank3 NAND
  • FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
FSMC_IT,: specifies the FSMC interrupt source to check. This parameter can be one of the following values:

  • FSMC_IT_RisingEdge: Rising edge detection interrupt.
  • FSMC_IT_Level: Level edge detection interrupt.
  • FSMC_IT_FallingEdge: Falling edge detection interrupt.
Return values:
The new state of FSMC_IT (SET or RESET).

Definition at line 782 of file stm32f10x_fsmc.c.

References assert_param, FSMC_Bank2, FSMC_Bank2_NAND, FSMC_Bank3, FSMC_Bank3_NAND, FSMC_Bank4, IS_FSMC_GET_IT, IS_FSMC_IT_BANK, RESET, and SET.

void FSMC_ITConfig | ( | uint32_t | FSMC_Bank,
 |  | uint32_t | FSMC_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified FSMC interrupts.

Parameters:
FSMC_Bank,: specifies the FSMC Bank to be used This parameter can be one of the following values:

  • FSMC_Bank2_NAND: FSMC Bank2 NAND
  • FSMC_Bank3_NAND: FSMC Bank3 NAND
  • FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
FSMC_IT,: specifies the FSMC interrupt sources to be enabled or disabled. This parameter can be any combination of the following values:

  • FSMC_IT_RisingEdge: Rising edge detection interrupt.
  • FSMC_IT_Level: Level edge detection interrupt.
  • FSMC_IT_FallingEdge: Falling edge detection interrupt.
NewState,: new state of the specified FSMC interrupts. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 637 of file stm32f10x_fsmc.c.

References assert_param, DISABLE, FSMC_Bank2, FSMC_Bank2_NAND, FSMC_Bank3, FSMC_Bank3_NAND, FSMC_Bank4, IS_FSMC_IT, IS_FSMC_IT_BANK, and IS_FUNCTIONAL_STATE.

void FSMC_NANDCmd | ( | uint32_t | FSMC_Bank,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified NAND Memory Bank.

Parameters:
FSMC_Bank,: specifies the FSMC Bank to be used This parameter can be one of the following values:

  • FSMC_Bank2_NAND: FSMC Bank2 NAND
  • FSMC_Bank3_NAND: FSMC Bank3 NAND
NewState,: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 501 of file stm32f10x_fsmc.c.

References assert_param, DISABLE, FSMC_Bank2, FSMC_Bank2_NAND, FSMC_Bank3, IS_FSMC_NAND_BANK, IS_FUNCTIONAL_STATE, PCR_PBKEN_Reset, and PCR_PBKEN_Set.

Referenced by NAND_Init().

void FSMC_NANDDeInit ( uint32_t FSMC_Bank )

Deinitializes the FSMC NAND Banks registers to their default reset values.

Parameters:
FSMC_Bank,: specifies the FSMC Bank to be used This parameter can be one of the following values:

  • FSMC_Bank2_NAND: FSMC Bank2 NAND
  • FSMC_Bank3_NAND: FSMC Bank3 NAND
Return values:
None

Definition at line 129 of file stm32f10x_fsmc.c.

References assert_param, FSMC_Bank2, FSMC_Bank2_NAND, FSMC_Bank3, and IS_FSMC_NAND_BANK.

void FSMC_NANDECCCmd | ( | uint32_t | FSMC_Bank,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the FSMC NAND ECC feature.

Parameters:
FSMC_Bank,: specifies the FSMC Bank to be used This parameter can be one of the following values:

  • FSMC_Bank2_NAND: FSMC Bank2 NAND
  • FSMC_Bank3_NAND: FSMC Bank3 NAND
NewState,: new state of the FSMC NAND ECC feature. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 564 of file stm32f10x_fsmc.c.

References assert_param, DISABLE, FSMC_Bank2, FSMC_Bank2_NAND, FSMC_Bank3, IS_FSMC_NAND_BANK, IS_FUNCTIONAL_STATE, PCR_ECCEN_Reset, and PCR_ECCEN_Set.

void FSMC_NANDInit ( FSMC_NANDInitTypeDef * FSMC_NANDInitStruct )

Initializes the FSMC NAND Banks according to the specified parameters in the FSMC_NANDInitStruct.

Parameters:
FSMC_NANDInitStruct : pointer to a FSMC_NANDInitTypeDef structure that contains the configuration information for the FSMC NAND specified Banks.
Return values:
None

Definition at line 262 of file stm32f10x_fsmc.c.

References assert_param, FSMC_NANDInitTypeDef::FSMC_AttributeSpaceTimingStruct, FSMC_NANDInitTypeDef::FSMC_Bank, FSMC_Bank2, FSMC_Bank2_NAND, FSMC_Bank3, FSMC_NANDInitTypeDef::FSMC_CommonSpaceTimingStruct, FSMC_NANDInitTypeDef::FSMC_ECC, FSMC_NANDInitTypeDef::FSMC_ECCPageSize, FSMC_NAND_PCCARDTimingInitTypeDef::FSMC_HiZSetupTime, FSMC_NAND_PCCARDTimingInitTypeDef::FSMC_HoldSetupTime, FSMC_NANDInitTypeDef::FSMC_MemoryDataWidth, FSMC_NAND_PCCARDTimingInitTypeDef::FSMC_SetupTime, FSMC_NANDInitTypeDef::FSMC_TARSetupTime, FSMC_NANDInitTypeDef::FSMC_TCLRSetupTime, FSMC_NANDInitTypeDef::FSMC_Waitfeature, FSMC_NAND_PCCARDTimingInitTypeDef::FSMC_WaitSetupTime, IS_FSMC_ECC_STATE, IS_FSMC_ECCPAGE_SIZE, IS_FSMC_HIZ_TIME, IS_FSMC_HOLD_TIME, IS_FSMC_MEMORY_WIDTH, IS_FSMC_NAND_BANK, IS_FSMC_SETUP_TIME, IS_FSMC_TAR_TIME, IS_FSMC_TCLR_TIME, IS_FSMC_WAIT_FEATURE, IS_FSMC_WAIT_TIME, and PCR_MemoryType_NAND.

Referenced by NAND_Init().

void FSMC_NANDStructInit ( FSMC_NANDInitTypeDef * FSMC_NANDInitStruct )

Fills each FSMC_NANDInitStruct member with its default value.

Parameters:
FSMC_NANDInitStruct,: pointer to a FSMC_NANDInitTypeDef structure which will be initialized.
Return values:
None

Definition at line 418 of file stm32f10x_fsmc.c.

References FSMC_NANDInitTypeDef::FSMC_AttributeSpaceTimingStruct, FSMC_NANDInitTypeDef::FSMC_Bank, FSMC_Bank2_NAND, FSMC_NANDInitTypeDef::FSMC_CommonSpaceTimingStruct, FSMC_NANDInitTypeDef::FSMC_ECC, FSMC_ECC_Disable, FSMC_NANDInitTypeDef::FSMC_ECCPageSize, FSMC_ECCPageSize_256Bytes, FSMC_NAND_PCCARDTimingInitTypeDef::FSMC_HiZSetupTime, FSMC_NAND_PCCARDTimingInitTypeDef::FSMC_HoldSetupTime, FSMC_NANDInitTypeDef::FSMC_MemoryDataWidth, FSMC_MemoryDataWidth_8b, FSMC_NAND_PCCARDTimingInitTypeDef::FSMC_SetupTime, FSMC_NANDInitTypeDef::FSMC_TARSetupTime, FSMC_NANDInitTypeDef::FSMC_TCLRSetupTime, FSMC_NANDInitTypeDef::FSMC_Waitfeature, FSMC_Waitfeature_Disable, and FSMC_NAND_PCCARDTimingInitTypeDef::FSMC_WaitSetupTime.

void FSMC_NORSRAMCmd | ( | uint32_t | FSMC_Bank,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified NOR/SRAM Memory Bank.

Parameters:
FSMC_Bank,: specifies the FSMC Bank to be used This parameter can be one of the following values:

  • FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1
  • FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2
  • FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3
  • FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4
NewState,: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 475 of file stm32f10x_fsmc.c.

References assert_param, BCR_MBKEN_Reset, BCR_MBKEN_Set, DISABLE, FSMC_Bank1, IS_FSMC_NORSRAM_BANK, and IS_FUNCTIONAL_STATE.

Referenced by LCD_DeInit(), LCD_FSMCConfig(), NOR_Init(), OneNAND_Init(), and SRAM_Init().

void FSMC_NORSRAMDeInit ( uint32_t FSMC_Bank )

Deinitializes the FSMC NOR/SRAM Banks registers to their default reset values.

Parameters:
FSMC_Bank,: specifies the FSMC Bank to be used This parameter can be one of the following values:

  • FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1
  • FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2
  • FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3
  • FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4
Return values:
None

Definition at line 102 of file stm32f10x_fsmc.c.

References assert_param, FSMC_Bank1, FSMC_Bank1_NORSRAM1, FSMC_Bank1E, and IS_FSMC_NORSRAM_BANK.

Referenced by LCD_DeInit().

void FSMC_NORSRAMInit ( FSMC_NORSRAMInitTypeDef * FSMC_NORSRAMInitStruct )

Initializes the FSMC NOR/SRAM Banks according to the specified parameters in the FSMC_NORSRAMInitStruct.

Parameters:
FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef structure that contains the configuration information for the FSMC NOR/SRAM specified Banks.
Return values:
None

Definition at line 176 of file stm32f10x_fsmc.c.

References assert_param, BCR_FACCEN_Set, FSMC_NORSRAMTimingInitTypeDef::FSMC_AccessMode, FSMC_NORSRAMTimingInitTypeDef::FSMC_AddressHoldTime, FSMC_NORSRAMTimingInitTypeDef::FSMC_AddressSetupTime, FSMC_NORSRAMInitTypeDef::FSMC_AsynchronousWait, FSMC_NORSRAMInitTypeDef::FSMC_Bank, FSMC_Bank1, FSMC_Bank1E, FSMC_NORSRAMInitTypeDef::FSMC_BurstAccessMode, FSMC_NORSRAMTimingInitTypeDef::FSMC_BusTurnAroundDuration, FSMC_NORSRAMTimingInitTypeDef::FSMC_CLKDivision, FSMC_NORSRAMInitTypeDef::FSMC_DataAddressMux, FSMC_NORSRAMTimingInitTypeDef::FSMC_DataLatency, FSMC_NORSRAMTimingInitTypeDef::FSMC_DataSetupTime, FSMC_NORSRAMInitTypeDef::FSMC_ExtendedMode, FSMC_ExtendedMode_Enable, FSMC_NORSRAMInitTypeDef::FSMC_MemoryDataWidth, FSMC_NORSRAMInitTypeDef::FSMC_MemoryType, FSMC_MemoryType_NOR, FSMC_NORSRAMInitTypeDef::FSMC_ReadWriteTimingStruct, FSMC_NORSRAMInitTypeDef::FSMC_WaitSignal, FSMC_NORSRAMInitTypeDef::FSMC_WaitSignalActive, FSMC_NORSRAMInitTypeDef::FSMC_WaitSignalPolarity, FSMC_NORSRAMInitTypeDef::FSMC_WrapMode, FSMC_NORSRAMInitTypeDef::FSMC_WriteBurst, FSMC_NORSRAMInitTypeDef::FSMC_WriteOperation, FSMC_NORSRAMInitTypeDef::FSMC_WriteTimingStruct, IS_FSMC_ACCESS_MODE, IS_FSMC_ADDRESS_HOLD_TIME, IS_FSMC_ADDRESS_SETUP_TIME, IS_FSMC_ASYNWAIT, IS_FSMC_BURSTMODE, IS_FSMC_CLK_DIV, IS_FSMC_DATA_LATENCY, IS_FSMC_DATASETUP_TIME, IS_FSMC_EXTENDED_MODE, IS_FSMC_MEMORY, IS_FSMC_MEMORY_WIDTH, IS_FSMC_MUX, IS_FSMC_NORSRAM_BANK, IS_FSMC_TURNAROUND_TIME, IS_FSMC_WAIT_POLARITY, IS_FSMC_WAIT_SIGNAL_ACTIVE, IS_FSMC_WAITE_SIGNAL, IS_FSMC_WRAP_MODE, IS_FSMC_WRITE_BURST, and IS_FSMC_WRITE_OPERATION.

Referenced by LCD_FSMCConfig(), NOR_Init(), OneNAND_Init(), and SRAM_Init().

void FSMC_NORSRAMStructInit ( FSMC_NORSRAMInitTypeDef * FSMC_NORSRAMInitStruct )

Fills each FSMC_NORSRAMInitStruct member with its default value.

Parameters:
FSMC_NORSRAMInitStruct,: pointer to a FSMC_NORSRAMInitTypeDef structure which will be initialized.
Return values:
None

Definition at line 380 of file stm32f10x_fsmc.c.

References FSMC_NORSRAMTimingInitTypeDef::FSMC_AccessMode, FSMC_AccessMode_A, FSMC_NORSRAMTimingInitTypeDef::FSMC_AddressHoldTime, FSMC_NORSRAMTimingInitTypeDef::FSMC_AddressSetupTime, FSMC_NORSRAMInitTypeDef::FSMC_AsynchronousWait, FSMC_AsynchronousWait_Disable, FSMC_NORSRAMInitTypeDef::FSMC_Bank, FSMC_Bank1_NORSRAM1, FSMC_NORSRAMInitTypeDef::FSMC_BurstAccessMode, FSMC_BurstAccessMode_Disable, FSMC_NORSRAMTimingInitTypeDef::FSMC_BusTurnAroundDuration, FSMC_NORSRAMTimingInitTypeDef::FSMC_CLKDivision, FSMC_NORSRAMInitTypeDef::FSMC_DataAddressMux, FSMC_DataAddressMux_Enable, FSMC_NORSRAMTimingInitTypeDef::FSMC_DataLatency, FSMC_NORSRAMTimingInitTypeDef::FSMC_DataSetupTime, FSMC_NORSRAMInitTypeDef::FSMC_ExtendedMode, FSMC_ExtendedMode_Disable, FSMC_NORSRAMInitTypeDef::FSMC_MemoryDataWidth, FSMC_MemoryDataWidth_8b, FSMC_NORSRAMInitTypeDef::FSMC_MemoryType, FSMC_MemoryType_SRAM, FSMC_NORSRAMInitTypeDef::FSMC_ReadWriteTimingStruct, FSMC_NORSRAMInitTypeDef::FSMC_WaitSignal, FSMC_WaitSignal_Enable, FSMC_NORSRAMInitTypeDef::FSMC_WaitSignalActive, FSMC_WaitSignalActive_BeforeWaitState, FSMC_NORSRAMInitTypeDef::FSMC_WaitSignalPolarity, FSMC_WaitSignalPolarity_Low, FSMC_NORSRAMInitTypeDef::FSMC_WrapMode, FSMC_WrapMode_Disable, FSMC_NORSRAMInitTypeDef::FSMC_WriteBurst, FSMC_WriteBurst_Disable, FSMC_NORSRAMInitTypeDef::FSMC_WriteOperation, FSMC_WriteOperation_Enable, and FSMC_NORSRAMInitTypeDef::FSMC_WriteTimingStruct.

void FSMC_PCCARDCmd ( FunctionalState NewState )

Enables or disables the PCCARD Memory Bank.

Parameters:
NewState,: new state of the PCCARD Memory Bank. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 538 of file stm32f10x_fsmc.c.

References assert_param, DISABLE, FSMC_Bank4, IS_FUNCTIONAL_STATE, PCR_PBKEN_Reset, and PCR_PBKEN_Set.

void FSMC_PCCARDDeInit ( void )

Deinitializes the FSMC PCCARD Bank registers to their default reset values.

Parameters:
None
Return values:
None

Definition at line 158 of file stm32f10x_fsmc.c.

References FSMC_Bank4.

void FSMC_PCCARDInit ( FSMC_PCCARDInitTypeDef * FSMC_PCCARDInitStruct )

Initializes the FSMC PCCARD Bank according to the specified parameters in the FSMC_PCCARDInitStruct.

Parameters:
FSMC_PCCARDInitStruct : pointer to a FSMC_PCCARDInitTypeDef structure that contains the configuration information for the FSMC PCCARD Bank.
Return values:
None

Definition at line 328 of file stm32f10x_fsmc.c.

References assert_param, FSMC_PCCARDInitTypeDef::FSMC_AttributeSpaceTimingStruct, FSMC_Bank4, FSMC_PCCARDInitTypeDef::FSMC_CommonSpaceTimingStruct, FSMC_NAND_PCCARDTimingInitTypeDef::FSMC_HiZSetupTime, FSMC_NAND_PCCARDTimingInitTypeDef::FSMC_HoldSetupTime, FSMC_PCCARDInitTypeDef::FSMC_IOSpaceTimingStruct, FSMC_MemoryDataWidth_16b, FSMC_NAND_PCCARDTimingInitTypeDef::FSMC_SetupTime, FSMC_PCCARDInitTypeDef::FSMC_TARSetupTime, FSMC_PCCARDInitTypeDef::FSMC_TCLRSetupTime, FSMC_PCCARDInitTypeDef::FSMC_Waitfeature, FSMC_NAND_PCCARDTimingInitTypeDef::FSMC_WaitSetupTime, IS_FSMC_HIZ_TIME, IS_FSMC_HOLD_TIME, IS_FSMC_SETUP_TIME, IS_FSMC_TAR_TIME, IS_FSMC_TCLR_TIME, IS_FSMC_WAIT_FEATURE, and IS_FSMC_WAIT_TIME.

void FSMC_PCCARDStructInit ( FSMC_PCCARDInitTypeDef * FSMC_PCCARDInitStruct )

Fills each FSMC_PCCARDInitStruct member with its default value.

Parameters:
FSMC_PCCARDInitStruct,: pointer to a FSMC_PCCARDInitTypeDef structure which will be initialized.
Return values:
None

Definition at line 444 of file stm32f10x_fsmc.c.

References FSMC_PCCARDInitTypeDef::FSMC_AttributeSpaceTimingStruct, FSMC_PCCARDInitTypeDef::FSMC_CommonSpaceTimingStruct, FSMC_NAND_PCCARDTimingInitTypeDef::FSMC_HiZSetupTime, FSMC_NAND_PCCARDTimingInitTypeDef::FSMC_HoldSetupTime, FSMC_PCCARDInitTypeDef::FSMC_IOSpaceTimingStruct, FSMC_NAND_PCCARDTimingInitTypeDef::FSMC_SetupTime, FSMC_PCCARDInitTypeDef::FSMC_TARSetupTime, FSMC_PCCARDInitTypeDef::FSMC_TCLRSetupTime, FSMC_PCCARDInitTypeDef::FSMC_Waitfeature, FSMC_Waitfeature_Disable, and FSMC_NAND_PCCARDTimingInitTypeDef::FSMC_WaitSetupTime.


STM32F10x Standard Peripherals Firmware Library: FSMC_Private_TypesDefinitions

FSMC_Private_TypesDefinitions

FSMC


STM32F10x Standard Peripherals Firmware Library: FSMC_Private_Defines

Defines

FSMC_Private_Defines

FSMC

Defines

#define | BCR_FACCEN_Set ((uint32_t)0x00000040)
#define | BCR_MBKEN_Reset ((uint32_t)0x000FFFFE)
#define | BCR_MBKEN_Set ((uint32_t)0x00000001)
#define | PCR_ECCEN_Reset ((uint32_t)0x000FFFBF)
#define | PCR_ECCEN_Set ((uint32_t)0x00000040)
#define | PCR_MemoryType_NAND ((uint32_t)0x00000008)
#define | PCR_PBKEN_Reset ((uint32_t)0x000FFFFB)
#define | PCR_PBKEN_Set ((uint32_t)0x00000004)

Define Documentation

#define BCR_FACCEN_Set ((uint32_t)0x00000040)

Definition at line 51 of file stm32f10x_fsmc.c.

Referenced by FSMC_NORSRAMInit().

#define BCR_MBKEN_Reset ((uint32_t)0x000FFFFE)

Definition at line 50 of file stm32f10x_fsmc.c.

Referenced by FSMC_NORSRAMCmd().

#define BCR_MBKEN_Set ((uint32_t)0x00000001)

Definition at line 49 of file stm32f10x_fsmc.c.

Referenced by FSMC_NORSRAMCmd().

#define PCR_ECCEN_Reset ((uint32_t)0x000FFFBF)

Definition at line 57 of file stm32f10x_fsmc.c.

Referenced by FSMC_NANDECCCmd().

#define PCR_ECCEN_Set ((uint32_t)0x00000040)

Definition at line 56 of file stm32f10x_fsmc.c.

Referenced by FSMC_NANDECCCmd().

#define PCR_MemoryType_NAND ((uint32_t)0x00000008)

Definition at line 58 of file stm32f10x_fsmc.c.

Referenced by FSMC_NANDInit().

#define PCR_PBKEN_Reset ((uint32_t)0x000FFFFB)

Definition at line 55 of file stm32f10x_fsmc.c.

Referenced by FSMC_NANDCmd(), and FSMC_PCCARDCmd().

#define PCR_PBKEN_Set ((uint32_t)0x00000004)

Definition at line 54 of file stm32f10x_fsmc.c.

Referenced by FSMC_NANDCmd(), and FSMC_PCCARDCmd().


STM32F10x Standard Peripherals Firmware Library: FSMC_Private_Macros

FSMC_Private_Macros

FSMC


STM32F10x Standard Peripherals Firmware Library: FSMC_Private_Variables

FSMC_Private_Variables

FSMC


STM32F10x Standard Peripherals Firmware Library: FSMC_Private_FunctionPrototypes

FSMC_Private_FunctionPrototypes

FSMC


STM32F10x Standard Peripherals Firmware Library: FSMC_Private_Functions

Functions

FSMC_Private_Functions

FSMC

Functions

void | FSMC_ClearFlag (uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
Clears the FSMC's pending flags.
void | FSMC_ClearITPendingBit (uint32_t FSMC_Bank, uint32_t FSMC_IT)
Clears the FSMC's interrupt pending bits.
uint32_t | FSMC_GetECC (uint32_t FSMC_Bank)
Returns the error correction code register value.
FlagStatus | FSMC_GetFlagStatus (uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
Checks whether the specified FSMC flag is set or not.
ITStatus | FSMC_GetITStatus (uint32_t FSMC_Bank, uint32_t FSMC_IT)
Checks whether the specified FSMC interrupt has occurred or not.
void | FSMC_ITConfig (uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState)
Enables or disables the specified FSMC interrupts.
void | FSMC_NANDCmd (uint32_t FSMC_Bank, FunctionalState NewState)
Enables or disables the specified NAND Memory Bank.
void | FSMC_NANDDeInit (uint32_t FSMC_Bank)
Deinitializes the FSMC NAND Banks registers to their default reset values.
void | FSMC_NANDECCCmd (uint32_t FSMC_Bank, FunctionalState NewState)
Enables or disables the FSMC NAND ECC feature.
void | FSMC_NANDInit (FSMC_NANDInitTypeDef *FSMC_NANDInitStruct)
Initializes the FSMC NAND Banks according to the specified parameters in the FSMC_NANDInitStruct.
void | FSMC_NANDStructInit (FSMC_NANDInitTypeDef *FSMC_NANDInitStruct)
Fills each FSMC_NANDInitStruct member with its default value.
void | FSMC_NORSRAMCmd (uint32_t FSMC_Bank, FunctionalState NewState)
Enables or disables the specified NOR/SRAM Memory Bank.
void | FSMC_NORSRAMDeInit (uint32_t FSMC_Bank)
Deinitializes the FSMC NOR/SRAM Banks registers to their default reset values.
void | FSMC_NORSRAMInit (FSMC_NORSRAMInitTypeDef *FSMC_NORSRAMInitStruct)
Initializes the FSMC NOR/SRAM Banks according to the specified parameters in the FSMC_NORSRAMInitStruct.
void | FSMC_NORSRAMStructInit (FSMC_NORSRAMInitTypeDef *FSMC_NORSRAMInitStruct)
Fills each FSMC_NORSRAMInitStruct member with its default value.
void | FSMC_PCCARDCmd (FunctionalState NewState)
Enables or disables the PCCARD Memory Bank.
void | FSMC_PCCARDDeInit (void)
Deinitializes the FSMC PCCARD Bank registers to their default reset values.
void | FSMC_PCCARDInit (FSMC_PCCARDInitTypeDef *FSMC_PCCARDInitStruct)
Initializes the FSMC PCCARD Bank according to the specified parameters in the FSMC_PCCARDInitStruct.
void | FSMC_PCCARDStructInit (FSMC_PCCARDInitTypeDef *FSMC_PCCARDInitStruct)
Fills each FSMC_PCCARDInitStruct member with its default value.

Function Documentation

void FSMC_ClearFlag | ( | uint32_t | FSMC_Bank,
 |  | uint32_t | FSMC_FLAG
 | ) |  |

Clears the FSMC's pending flags.

Parameters:
FSMC_Bank,: specifies the FSMC Bank to be used This parameter can be one of the following values:

  • FSMC_Bank2_NAND: FSMC Bank2 NAND
  • FSMC_Bank3_NAND: FSMC Bank3 NAND
  • FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
FSMC_FLAG,: specifies the flag to clear. This parameter can be any combination of the following values:

  • FSMC_FLAG_RisingEdge: Rising egde detection Flag.
  • FSMC_FLAG_Level: Level detection Flag.
  • FSMC_FLAG_FallingEdge: Falling egde detection Flag.
Return values:
None

Definition at line 747 of file stm32f10x_fsmc.c.

References assert_param, FSMC_Bank2, FSMC_Bank2_NAND, FSMC_Bank3, FSMC_Bank3_NAND, FSMC_Bank4, IS_FSMC_CLEAR_FLAG, and IS_FSMC_GETFLAG_BANK.

void FSMC_ClearITPendingBit | ( | uint32_t | FSMC_Bank,
 |  | uint32_t | FSMC_IT
 | ) |  |

Clears the FSMC's interrupt pending bits.

Parameters:
FSMC_Bank,: specifies the FSMC Bank to be used This parameter can be one of the following values:

  • FSMC_Bank2_NAND: FSMC Bank2 NAND
  • FSMC_Bank3_NAND: FSMC Bank3 NAND
  • FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
FSMC_IT,: specifies the interrupt pending bit to clear. This parameter can be any combination of the following values:

  • FSMC_IT_RisingEdge: Rising edge detection interrupt.
  • FSMC_IT_Level: Level edge detection interrupt.
  • FSMC_IT_FallingEdge: Falling edge detection interrupt.
Return values:
None

Definition at line 833 of file stm32f10x_fsmc.c.

References assert_param, FSMC_Bank2, FSMC_Bank2_NAND, FSMC_Bank3, FSMC_Bank3_NAND, FSMC_Bank4, IS_FSMC_IT, and IS_FSMC_IT_BANK.

uint32_t FSMC_GetECC ( uint32_t FSMC_Bank )

Returns the error correction code register value.

Parameters:
FSMC_Bank,: specifies the FSMC Bank to be used This parameter can be one of the following values:

  • FSMC_Bank2_NAND: FSMC Bank2 NAND
  • FSMC_Bank3_NAND: FSMC Bank3 NAND
Return values:
The Error Correction Code (ECC) value.

Definition at line 603 of file stm32f10x_fsmc.c.

References FSMC_Bank2, FSMC_Bank2_NAND, and FSMC_Bank3.

FlagStatus FSMC_GetFlagStatus | ( | uint32_t | FSMC_Bank,
 |  | uint32_t | FSMC_FLAG
 | ) |  |

Checks whether the specified FSMC flag is set or not.

Parameters:
FSMC_Bank,: specifies the FSMC Bank to be used This parameter can be one of the following values:

  • FSMC_Bank2_NAND: FSMC Bank2 NAND
  • FSMC_Bank3_NAND: FSMC Bank3 NAND
  • FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
FSMC_FLAG,: specifies the flag to check. This parameter can be one of the following values:

  • FSMC_FLAG_RisingEdge: Rising egde detection Flag.
  • FSMC_FLAG_Level: Level detection Flag.
  • FSMC_FLAG_FallingEdge: Falling egde detection Flag.
  • FSMC_FLAG_FEMPT: Fifo empty Flag.
Return values:
The new state of FSMC_FLAG (SET or RESET).

Definition at line 697 of file stm32f10x_fsmc.c.

References assert_param, FSMC_Bank2, FSMC_Bank2_NAND, FSMC_Bank3, FSMC_Bank3_NAND, FSMC_Bank4, IS_FSMC_GET_FLAG, IS_FSMC_GETFLAG_BANK, RESET, and SET.

ITStatus FSMC_GetITStatus | ( | uint32_t | FSMC_Bank,
 |  | uint32_t | FSMC_IT
 | ) |  |

Checks whether the specified FSMC interrupt has occurred or not.

Parameters:
FSMC_Bank,: specifies the FSMC Bank to be used This parameter can be one of the following values:

  • FSMC_Bank2_NAND: FSMC Bank2 NAND
  • FSMC_Bank3_NAND: FSMC Bank3 NAND
  • FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
FSMC_IT,: specifies the FSMC interrupt source to check. This parameter can be one of the following values:

  • FSMC_IT_RisingEdge: Rising edge detection interrupt.
  • FSMC_IT_Level: Level edge detection interrupt.
  • FSMC_IT_FallingEdge: Falling edge detection interrupt.
Return values:
The new state of FSMC_IT (SET or RESET).

Definition at line 782 of file stm32f10x_fsmc.c.

References assert_param, FSMC_Bank2, FSMC_Bank2_NAND, FSMC_Bank3, FSMC_Bank3_NAND, FSMC_Bank4, IS_FSMC_GET_IT, IS_FSMC_IT_BANK, RESET, and SET.

void FSMC_ITConfig | ( | uint32_t | FSMC_Bank,
 |  | uint32_t | FSMC_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified FSMC interrupts.

Parameters:
FSMC_Bank,: specifies the FSMC Bank to be used This parameter can be one of the following values:

  • FSMC_Bank2_NAND: FSMC Bank2 NAND
  • FSMC_Bank3_NAND: FSMC Bank3 NAND
  • FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
FSMC_IT,: specifies the FSMC interrupt sources to be enabled or disabled. This parameter can be any combination of the following values:

  • FSMC_IT_RisingEdge: Rising edge detection interrupt.
  • FSMC_IT_Level: Level edge detection interrupt.
  • FSMC_IT_FallingEdge: Falling edge detection interrupt.
NewState,: new state of the specified FSMC interrupts. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 637 of file stm32f10x_fsmc.c.

References assert_param, DISABLE, FSMC_Bank2, FSMC_Bank2_NAND, FSMC_Bank3, FSMC_Bank3_NAND, FSMC_Bank4, IS_FSMC_IT, IS_FSMC_IT_BANK, and IS_FUNCTIONAL_STATE.

void FSMC_NANDCmd | ( | uint32_t | FSMC_Bank,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified NAND Memory Bank.

Parameters:
FSMC_Bank,: specifies the FSMC Bank to be used This parameter can be one of the following values:

  • FSMC_Bank2_NAND: FSMC Bank2 NAND
  • FSMC_Bank3_NAND: FSMC Bank3 NAND
NewState,: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 501 of file stm32f10x_fsmc.c.

References assert_param, DISABLE, FSMC_Bank2, FSMC_Bank2_NAND, FSMC_Bank3, IS_FSMC_NAND_BANK, IS_FUNCTIONAL_STATE, PCR_PBKEN_Reset, and PCR_PBKEN_Set.

Referenced by NAND_Init().

void FSMC_NANDDeInit ( uint32_t FSMC_Bank )

Deinitializes the FSMC NAND Banks registers to their default reset values.

Parameters:
FSMC_Bank,: specifies the FSMC Bank to be used This parameter can be one of the following values:

  • FSMC_Bank2_NAND: FSMC Bank2 NAND
  • FSMC_Bank3_NAND: FSMC Bank3 NAND
Return values:
None

Definition at line 129 of file stm32f10x_fsmc.c.

References assert_param, FSMC_Bank2, FSMC_Bank2_NAND, FSMC_Bank3, and IS_FSMC_NAND_BANK.

void FSMC_NANDECCCmd | ( | uint32_t | FSMC_Bank,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the FSMC NAND ECC feature.

Parameters:
FSMC_Bank,: specifies the FSMC Bank to be used This parameter can be one of the following values:

  • FSMC_Bank2_NAND: FSMC Bank2 NAND
  • FSMC_Bank3_NAND: FSMC Bank3 NAND
NewState,: new state of the FSMC NAND ECC feature. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 564 of file stm32f10x_fsmc.c.

References assert_param, DISABLE, FSMC_Bank2, FSMC_Bank2_NAND, FSMC_Bank3, IS_FSMC_NAND_BANK, IS_FUNCTIONAL_STATE, PCR_ECCEN_Reset, and PCR_ECCEN_Set.

void FSMC_NANDInit ( FSMC_NANDInitTypeDef * FSMC_NANDInitStruct )

Initializes the FSMC NAND Banks according to the specified parameters in the FSMC_NANDInitStruct.

Parameters:
FSMC_NANDInitStruct : pointer to a FSMC_NANDInitTypeDef structure that contains the configuration information for the FSMC NAND specified Banks.
Return values:
None

Definition at line 262 of file stm32f10x_fsmc.c.

References assert_param, FSMC_NANDInitTypeDef::FSMC_AttributeSpaceTimingStruct, FSMC_NANDInitTypeDef::FSMC_Bank, FSMC_Bank2, FSMC_Bank2_NAND, FSMC_Bank3, FSMC_NANDInitTypeDef::FSMC_CommonSpaceTimingStruct, FSMC_NANDInitTypeDef::FSMC_ECC, FSMC_NANDInitTypeDef::FSMC_ECCPageSize, FSMC_NAND_PCCARDTimingInitTypeDef::FSMC_HiZSetupTime, FSMC_NAND_PCCARDTimingInitTypeDef::FSMC_HoldSetupTime, FSMC_NANDInitTypeDef::FSMC_MemoryDataWidth, FSMC_NAND_PCCARDTimingInitTypeDef::FSMC_SetupTime, FSMC_NANDInitTypeDef::FSMC_TARSetupTime, FSMC_NANDInitTypeDef::FSMC_TCLRSetupTime, FSMC_NANDInitTypeDef::FSMC_Waitfeature, FSMC_NAND_PCCARDTimingInitTypeDef::FSMC_WaitSetupTime, IS_FSMC_ECC_STATE, IS_FSMC_ECCPAGE_SIZE, IS_FSMC_HIZ_TIME, IS_FSMC_HOLD_TIME, IS_FSMC_MEMORY_WIDTH, IS_FSMC_NAND_BANK, IS_FSMC_SETUP_TIME, IS_FSMC_TAR_TIME, IS_FSMC_TCLR_TIME, IS_FSMC_WAIT_FEATURE, IS_FSMC_WAIT_TIME, and PCR_MemoryType_NAND.

Referenced by NAND_Init().

void FSMC_NANDStructInit ( FSMC_NANDInitTypeDef * FSMC_NANDInitStruct )

Fills each FSMC_NANDInitStruct member with its default value.

Parameters:
FSMC_NANDInitStruct,: pointer to a FSMC_NANDInitTypeDef structure which will be initialized.
Return values:
None

Definition at line 418 of file stm32f10x_fsmc.c.

References FSMC_NANDInitTypeDef::FSMC_AttributeSpaceTimingStruct, FSMC_NANDInitTypeDef::FSMC_Bank, FSMC_Bank2_NAND, FSMC_NANDInitTypeDef::FSMC_CommonSpaceTimingStruct, FSMC_NANDInitTypeDef::FSMC_ECC, FSMC_ECC_Disable, FSMC_NANDInitTypeDef::FSMC_ECCPageSize, FSMC_ECCPageSize_256Bytes, FSMC_NAND_PCCARDTimingInitTypeDef::FSMC_HiZSetupTime, FSMC_NAND_PCCARDTimingInitTypeDef::FSMC_HoldSetupTime, FSMC_NANDInitTypeDef::FSMC_MemoryDataWidth, FSMC_MemoryDataWidth_8b, FSMC_NAND_PCCARDTimingInitTypeDef::FSMC_SetupTime, FSMC_NANDInitTypeDef::FSMC_TARSetupTime, FSMC_NANDInitTypeDef::FSMC_TCLRSetupTime, FSMC_NANDInitTypeDef::FSMC_Waitfeature, FSMC_Waitfeature_Disable, and FSMC_NAND_PCCARDTimingInitTypeDef::FSMC_WaitSetupTime.

void FSMC_NORSRAMCmd | ( | uint32_t | FSMC_Bank,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified NOR/SRAM Memory Bank.

Parameters:
FSMC_Bank,: specifies the FSMC Bank to be used This parameter can be one of the following values:

  • FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1
  • FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2
  • FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3
  • FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4
NewState,: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 475 of file stm32f10x_fsmc.c.

References assert_param, BCR_MBKEN_Reset, BCR_MBKEN_Set, DISABLE, FSMC_Bank1, IS_FSMC_NORSRAM_BANK, and IS_FUNCTIONAL_STATE.

Referenced by LCD_DeInit(), LCD_FSMCConfig(), NOR_Init(), OneNAND_Init(), and SRAM_Init().

void FSMC_NORSRAMDeInit ( uint32_t FSMC_Bank )

Deinitializes the FSMC NOR/SRAM Banks registers to their default reset values.

Parameters:
FSMC_Bank,: specifies the FSMC Bank to be used This parameter can be one of the following values:

  • FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1
  • FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2
  • FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3
  • FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4
Return values:
None

Definition at line 102 of file stm32f10x_fsmc.c.

References assert_param, FSMC_Bank1, FSMC_Bank1_NORSRAM1, FSMC_Bank1E, and IS_FSMC_NORSRAM_BANK.

Referenced by LCD_DeInit().

void FSMC_NORSRAMInit ( FSMC_NORSRAMInitTypeDef * FSMC_NORSRAMInitStruct )

Initializes the FSMC NOR/SRAM Banks according to the specified parameters in the FSMC_NORSRAMInitStruct.

Parameters:
FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef structure that contains the configuration information for the FSMC NOR/SRAM specified Banks.
Return values:
None

Definition at line 176 of file stm32f10x_fsmc.c.

References assert_param, BCR_FACCEN_Set, FSMC_NORSRAMTimingInitTypeDef::FSMC_AccessMode, FSMC_NORSRAMTimingInitTypeDef::FSMC_AddressHoldTime, FSMC_NORSRAMTimingInitTypeDef::FSMC_AddressSetupTime, FSMC_NORSRAMInitTypeDef::FSMC_AsynchronousWait, FSMC_NORSRAMInitTypeDef::FSMC_Bank, FSMC_Bank1, FSMC_Bank1E, FSMC_NORSRAMInitTypeDef::FSMC_BurstAccessMode, FSMC_NORSRAMTimingInitTypeDef::FSMC_BusTurnAroundDuration, FSMC_NORSRAMTimingInitTypeDef::FSMC_CLKDivision, FSMC_NORSRAMInitTypeDef::FSMC_DataAddressMux, FSMC_NORSRAMTimingInitTypeDef::FSMC_DataLatency, FSMC_NORSRAMTimingInitTypeDef::FSMC_DataSetupTime, FSMC_NORSRAMInitTypeDef::FSMC_ExtendedMode, FSMC_ExtendedMode_Enable, FSMC_NORSRAMInitTypeDef::FSMC_MemoryDataWidth, FSMC_NORSRAMInitTypeDef::FSMC_MemoryType, FSMC_MemoryType_NOR, FSMC_NORSRAMInitTypeDef::FSMC_ReadWriteTimingStruct, FSMC_NORSRAMInitTypeDef::FSMC_WaitSignal, FSMC_NORSRAMInitTypeDef::FSMC_WaitSignalActive, FSMC_NORSRAMInitTypeDef::FSMC_WaitSignalPolarity, FSMC_NORSRAMInitTypeDef::FSMC_WrapMode, FSMC_NORSRAMInitTypeDef::FSMC_WriteBurst, FSMC_NORSRAMInitTypeDef::FSMC_WriteOperation, FSMC_NORSRAMInitTypeDef::FSMC_WriteTimingStruct, IS_FSMC_ACCESS_MODE, IS_FSMC_ADDRESS_HOLD_TIME, IS_FSMC_ADDRESS_SETUP_TIME, IS_FSMC_ASYNWAIT, IS_FSMC_BURSTMODE, IS_FSMC_CLK_DIV, IS_FSMC_DATA_LATENCY, IS_FSMC_DATASETUP_TIME, IS_FSMC_EXTENDED_MODE, IS_FSMC_MEMORY, IS_FSMC_MEMORY_WIDTH, IS_FSMC_MUX, IS_FSMC_NORSRAM_BANK, IS_FSMC_TURNAROUND_TIME, IS_FSMC_WAIT_POLARITY, IS_FSMC_WAIT_SIGNAL_ACTIVE, IS_FSMC_WAITE_SIGNAL, IS_FSMC_WRAP_MODE, IS_FSMC_WRITE_BURST, and IS_FSMC_WRITE_OPERATION.

Referenced by LCD_FSMCConfig(), NOR_Init(), OneNAND_Init(), and SRAM_Init().

void FSMC_NORSRAMStructInit ( FSMC_NORSRAMInitTypeDef * FSMC_NORSRAMInitStruct )

Fills each FSMC_NORSRAMInitStruct member with its default value.

Parameters:
FSMC_NORSRAMInitStruct,: pointer to a FSMC_NORSRAMInitTypeDef structure which will be initialized.
Return values:
None

Definition at line 380 of file stm32f10x_fsmc.c.

References FSMC_NORSRAMTimingInitTypeDef::FSMC_AccessMode, FSMC_AccessMode_A, FSMC_NORSRAMTimingInitTypeDef::FSMC_AddressHoldTime, FSMC_NORSRAMTimingInitTypeDef::FSMC_AddressSetupTime, FSMC_NORSRAMInitTypeDef::FSMC_AsynchronousWait, FSMC_AsynchronousWait_Disable, FSMC_NORSRAMInitTypeDef::FSMC_Bank, FSMC_Bank1_NORSRAM1, FSMC_NORSRAMInitTypeDef::FSMC_BurstAccessMode, FSMC_BurstAccessMode_Disable, FSMC_NORSRAMTimingInitTypeDef::FSMC_BusTurnAroundDuration, FSMC_NORSRAMTimingInitTypeDef::FSMC_CLKDivision, FSMC_NORSRAMInitTypeDef::FSMC_DataAddressMux, FSMC_DataAddressMux_Enable, FSMC_NORSRAMTimingInitTypeDef::FSMC_DataLatency, FSMC_NORSRAMTimingInitTypeDef::FSMC_DataSetupTime, FSMC_NORSRAMInitTypeDef::FSMC_ExtendedMode, FSMC_ExtendedMode_Disable, FSMC_NORSRAMInitTypeDef::FSMC_MemoryDataWidth, FSMC_MemoryDataWidth_8b, FSMC_NORSRAMInitTypeDef::FSMC_MemoryType, FSMC_MemoryType_SRAM, FSMC_NORSRAMInitTypeDef::FSMC_ReadWriteTimingStruct, FSMC_NORSRAMInitTypeDef::FSMC_WaitSignal, FSMC_WaitSignal_Enable, FSMC_NORSRAMInitTypeDef::FSMC_WaitSignalActive, FSMC_WaitSignalActive_BeforeWaitState, FSMC_NORSRAMInitTypeDef::FSMC_WaitSignalPolarity, FSMC_WaitSignalPolarity_Low, FSMC_NORSRAMInitTypeDef::FSMC_WrapMode, FSMC_WrapMode_Disable, FSMC_NORSRAMInitTypeDef::FSMC_WriteBurst, FSMC_WriteBurst_Disable, FSMC_NORSRAMInitTypeDef::FSMC_WriteOperation, FSMC_WriteOperation_Enable, and FSMC_NORSRAMInitTypeDef::FSMC_WriteTimingStruct.

void FSMC_PCCARDCmd ( FunctionalState NewState )

Enables or disables the PCCARD Memory Bank.

Parameters:
NewState,: new state of the PCCARD Memory Bank. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 538 of file stm32f10x_fsmc.c.

References assert_param, DISABLE, FSMC_Bank4, IS_FUNCTIONAL_STATE, PCR_PBKEN_Reset, and PCR_PBKEN_Set.

void FSMC_PCCARDDeInit ( void )

Deinitializes the FSMC PCCARD Bank registers to their default reset values.

Parameters:
None
Return values:
None

Definition at line 158 of file stm32f10x_fsmc.c.

References FSMC_Bank4.

void FSMC_PCCARDInit ( FSMC_PCCARDInitTypeDef * FSMC_PCCARDInitStruct )

Initializes the FSMC PCCARD Bank according to the specified parameters in the FSMC_PCCARDInitStruct.

Parameters:
FSMC_PCCARDInitStruct : pointer to a FSMC_PCCARDInitTypeDef structure that contains the configuration information for the FSMC PCCARD Bank.
Return values:
None

Definition at line 328 of file stm32f10x_fsmc.c.

References assert_param, FSMC_PCCARDInitTypeDef::FSMC_AttributeSpaceTimingStruct, FSMC_Bank4, FSMC_PCCARDInitTypeDef::FSMC_CommonSpaceTimingStruct, FSMC_NAND_PCCARDTimingInitTypeDef::FSMC_HiZSetupTime, FSMC_NAND_PCCARDTimingInitTypeDef::FSMC_HoldSetupTime, FSMC_PCCARDInitTypeDef::FSMC_IOSpaceTimingStruct, FSMC_MemoryDataWidth_16b, FSMC_NAND_PCCARDTimingInitTypeDef::FSMC_SetupTime, FSMC_PCCARDInitTypeDef::FSMC_TARSetupTime, FSMC_PCCARDInitTypeDef::FSMC_TCLRSetupTime, FSMC_PCCARDInitTypeDef::FSMC_Waitfeature, FSMC_NAND_PCCARDTimingInitTypeDef::FSMC_WaitSetupTime, IS_FSMC_HIZ_TIME, IS_FSMC_HOLD_TIME, IS_FSMC_SETUP_TIME, IS_FSMC_TAR_TIME, IS_FSMC_TCLR_TIME, IS_FSMC_WAIT_FEATURE, and IS_FSMC_WAIT_TIME.

void FSMC_PCCARDStructInit ( FSMC_PCCARDInitTypeDef * FSMC_PCCARDInitStruct )

Fills each FSMC_PCCARDInitStruct member with its default value.

Parameters:
FSMC_PCCARDInitStruct,: pointer to a FSMC_PCCARDInitTypeDef structure which will be initialized.
Return values:
None

Definition at line 444 of file stm32f10x_fsmc.c.

References FSMC_PCCARDInitTypeDef::FSMC_AttributeSpaceTimingStruct, FSMC_PCCARDInitTypeDef::FSMC_CommonSpaceTimingStruct, FSMC_NAND_PCCARDTimingInitTypeDef::FSMC_HiZSetupTime, FSMC_NAND_PCCARDTimingInitTypeDef::FSMC_HoldSetupTime, FSMC_PCCARDInitTypeDef::FSMC_IOSpaceTimingStruct, FSMC_NAND_PCCARDTimingInitTypeDef::FSMC_SetupTime, FSMC_PCCARDInitTypeDef::FSMC_TARSetupTime, FSMC_PCCARDInitTypeDef::FSMC_TCLRSetupTime, FSMC_PCCARDInitTypeDef::FSMC_Waitfeature, FSMC_Waitfeature_Disable, and FSMC_NAND_PCCARDTimingInitTypeDef::FSMC_WaitSetupTime.


STM32F10x Standard Peripherals Firmware Library: GPIO_Exported_Types

Data Structures | Defines | Enumerations

GPIO_Exported_Types

GPIO

Data Structures

struct | GPIO_InitTypeDef
GPIO Init structure definition. More...

Defines

#define | IS_GPIO_ALL_PERIPH(PERIPH)
#define | IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))
#define | IS_GPIO_MODE(MODE)
#define | IS_GPIO_SPEED(SPEED)

Enumerations

enum | BitAction { Bit_RESET = 0, Bit_SET }

Bit_SET and Bit_RESET enumeration.

More...
enum GPIOMode_TypeDef {
GPIO_Mode_AIN = 0x0, GPIO_Mode_IN_FLOATING = 0x04, GPIO_Mode_IPD = 0x28, GPIO_Mode_IPU = 0x48,
GPIO_Mode_Out_OD = 0x14, GPIO_Mode_Out_PP = 0x10, GPIO_Mode_AF_OD = 0x1C, GPIO_Mode_AF_PP = 0x18
}

Configuration Mode enumeration.

More...
enum | GPIOSpeed_TypeDef { GPIO_Speed_10MHz = 1, GPIO_Speed_2MHz, GPIO_Speed_50MHz }

Output Maximum frequency selection.

More...

Define Documentation

#define IS_GPIO_ALL_PERIPH ( PERIPH )
Value:
(((PERIPH) == GPIOA) || \
                                    ((PERIPH) == GPIOB) || \
                                    ((PERIPH) == GPIOC) || \
                                    ((PERIPH) == GPIOD) || \
                                    ((PERIPH) == GPIOE) || \
                                    ((PERIPH) == GPIOF) || \
                                    ((PERIPH) == GPIOG))

Definition at line 46 of file stm32f10x_gpio.h.

Referenced by GPIO_DeInit(), GPIO_Init(), GPIO_PinLockConfig(), GPIO_ReadInputData(), GPIO_ReadInputDataBit(), GPIO_ReadOutputData(), GPIO_ReadOutputDataBit(), GPIO_ResetBits(), GPIO_SetBits(), GPIO_Write(), and GPIO_WriteBit().

#define IS_GPIO_BIT_ACTION ( ACTION ) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))

Definition at line 113 of file stm32f10x_gpio.h.

Referenced by GPIO_WriteBit().

#define IS_GPIO_MODE ( MODE )
Value:
(((MODE) == GPIO_Mode_AIN) || ((MODE) == GPIO_Mode_IN_FLOATING) || \
                            ((MODE) == GPIO_Mode_IPD) || ((MODE) == GPIO_Mode_IPU) || \
                            ((MODE) == GPIO_Mode_Out_OD) || ((MODE) == GPIO_Mode_Out_PP) || \
                            ((MODE) == GPIO_Mode_AF_OD) || ((MODE) == GPIO_Mode_AF_PP))

Definition at line 82 of file stm32f10x_gpio.h.

Referenced by GPIO_Init().

#define IS_GPIO_SPEED ( SPEED )
Value:
(((SPEED) == GPIO_Speed_10MHz) || ((SPEED) == GPIO_Speed_2MHz) || \
                              ((SPEED) == GPIO_Speed_50MHz))

Definition at line 64 of file stm32f10x_gpio.h.

Referenced by GPIO_Init().

Enumeration Type Documentation

enum BitAction

Bit_SET and Bit_RESET enumeration.

Enumerator:
Bit_RESET
Bit_SET

Definition at line 108 of file stm32f10x_gpio.h.

enum GPIOMode_TypeDef

Configuration Mode enumeration.

Enumerator:
GPIO_Mode_AIN
GPIO_Mode_IN_FLOATING
GPIO_Mode_IPD
GPIO_Mode_IPU
GPIO_Mode_Out_OD
GPIO_Mode_Out_PP
GPIO_Mode_AF_OD
GPIO_Mode_AF_PP

Definition at line 71 of file stm32f10x_gpio.h.

enum GPIOSpeed_TypeDef

Output Maximum frequency selection.

Enumerator:
GPIO_Speed_10MHz
GPIO_Speed_2MHz
GPIO_Speed_50MHz

Definition at line 58 of file stm32f10x_gpio.h.


STM32F10x Standard Peripherals Firmware Library: GPIO_InitTypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

GPIO_InitTypeDef Struct Reference
GPIO_Exported_Types

GPIO Init structure definition. More...

#include <stm32f10x_gpio.h>

Data Fields

GPIOMode_TypeDef GPIO_Mode
uint16_t GPIO_Pin
GPIOSpeed_TypeDef GPIO_Speed

Detailed Description

GPIO Init structure definition.

Definition at line 91 of file stm32f10x_gpio.h.

Field Documentation

GPIOMode_TypeDef GPIO_InitTypeDef::GPIO_Mode

Specifies the operating mode for the selected pins. This parameter can be a value of GPIOMode_TypeDef

Definition at line 99 of file stm32f10x_gpio.h.

Referenced by CAN_Config(), EXTI0_Config(), EXTI9_5_Config(), GPIO_Configuration(), GPIO_Init(), GPIO_StructInit(), HDMI_CEC_Init(), IOE_EXTI_Config(), IOE_GPIO_Config(), LCD_CtrlLinesConfig(), LCD_DeInit(), LCD_GPIOConfig(), LCD_SPIConfig(), LM75_LowLevel_DeInit(), LM75_LowLevel_Init(), main(), NAND_Init(), NOR_Init(), OneNAND_Init(), SD_LowLevel_DeInit(), SD_LowLevel_Init(), sEE_LowLevel_DeInit(), sEE_LowLevel_Init(), sFLASH_LowLevel_DeInit(), sFLASH_LowLevel_Init(), SRAM_Init(), STM32L152_LCD_DeInit(), STM_EVAL_COMInit(), STM_EVAL_LEDInit(), and STM_EVAL_PBInit().

uint16_t GPIO_InitTypeDef::GPIO_Pin

Specifies the GPIO pins to be configured. This parameter can be any value of GPIO_pins_define

Definition at line 93 of file stm32f10x_gpio.h.

Referenced by CAN_Config(), EXTI0_Config(), EXTI9_5_Config(), GPIO_Configuration(), GPIO_Init(), GPIO_StructInit(), HDMI_CEC_Init(), IOE_EXTI_Config(), IOE_GPIO_Config(), LCD_CtrlLinesConfig(), LCD_DeInit(), LCD_GPIOConfig(), LCD_SPIConfig(), LM75_LowLevel_DeInit(), LM75_LowLevel_Init(), main(), NAND_Init(), NOR_Init(), OneNAND_Init(), SD_LowLevel_DeInit(), SD_LowLevel_Init(), sEE_LowLevel_DeInit(), sEE_LowLevel_Init(), sFLASH_LowLevel_DeInit(), sFLASH_LowLevel_Init(), SRAM_Init(), STM32L152_LCD_DeInit(), STM_EVAL_COMInit(), STM_EVAL_LEDInit(), and STM_EVAL_PBInit().

GPIOSpeed_TypeDef GPIO_InitTypeDef::GPIO_Speed

Specifies the speed for the selected pins. This parameter can be a value of GPIOSpeed_TypeDef

Definition at line 96 of file stm32f10x_gpio.h.

Referenced by CAN_Config(), GPIO_Configuration(), GPIO_Init(), GPIO_StructInit(), HDMI_CEC_Init(), IOE_GPIO_Config(), LCD_CtrlLinesConfig(), LCD_GPIOConfig(), LCD_SPIConfig(), LM75_LowLevel_Init(), main(), NAND_Init(), NOR_Init(), OneNAND_Init(), SD_LowLevel_Init(), sEE_LowLevel_Init(), sFLASH_LowLevel_Init(), SRAM_Init(), STM_EVAL_COMInit(), and STM_EVAL_LEDInit().

The documentation for this struct was generated from the following file:
  • stm32f10x_gpio.h


STM32F10x Standard Peripherals Firmware Library: GPIO_pins_define

Defines

GPIO_pins_define

GPIO_Exported_Constants

Defines

#define | GPIO_Pin_0 ((uint16_t)0x0001)
#define | GPIO_Pin_1 ((uint16_t)0x0002)
#define | GPIO_Pin_10 ((uint16_t)0x0400)
#define | GPIO_Pin_11 ((uint16_t)0x0800)
#define | GPIO_Pin_12 ((uint16_t)0x1000)
#define | GPIO_Pin_13 ((uint16_t)0x2000)
#define | GPIO_Pin_14 ((uint16_t)0x4000)
#define | GPIO_Pin_15 ((uint16_t)0x8000)
#define | GPIO_Pin_2 ((uint16_t)0x0004)
#define | GPIO_Pin_3 ((uint16_t)0x0008)
#define | GPIO_Pin_4 ((uint16_t)0x0010)
#define | GPIO_Pin_5 ((uint16_t)0x0020)
#define | GPIO_Pin_6 ((uint16_t)0x0040)
#define | GPIO_Pin_7 ((uint16_t)0x0080)
#define | GPIO_Pin_8 ((uint16_t)0x0100)
#define | GPIO_Pin_9 ((uint16_t)0x0200)
#define | GPIO_Pin_All ((uint16_t)0xFFFF)
#define | IS_GET_GPIO_PIN(PIN)
#define | IS_GPIO_PIN(PIN) ((((PIN) & (uint16_t)0x00) == 0x00) && ((PIN) != (uint16_t)0x00))

Define Documentation

#define GPIO_Pin_0 ((uint16_t)0x0001)

Pin 0 selected

Definition at line 127 of file stm32f10x_gpio.h.

Referenced by CAN_Config(), EXTI0_Config(), LCD_CtrlLinesConfig(), LCD_DeInit(), LCD_GPIOConfig(), main(), NAND_Init(), NOR_Init(), OneNAND_Init(), and SRAM_Init().

#define GPIO_Pin_1 ((uint16_t)0x0002)

Pin 1 selected

Definition at line 128 of file stm32f10x_gpio.h.

Referenced by CAN_Config(), LCD_CtrlLinesConfig(), LCD_DeInit(), LCD_GPIOConfig(), NAND_Init(), NOR_Init(), OneNAND_Init(), and SRAM_Init().

#define GPIO_Pin_10 ((uint16_t)0x0400)

Pin 10 selected

Definition at line 137 of file stm32f10x_gpio.h.

Referenced by LCD_CtrlLinesConfig(), LCD_DeInit(), LCD_GPIOConfig(), NAND_Init(), NOR_Init(), OneNAND_Init(), SD_LowLevel_DeInit(), SD_LowLevel_Init(), and SRAM_Init().

#define GPIO_Pin_11 ((uint16_t)0x0800)

Pin 11 selected

Definition at line 138 of file stm32f10x_gpio.h.

Referenced by LCD_CtrlLinesConfig(), LCD_DeInit(), LCD_GPIOConfig(), NAND_Init(), NOR_Init(), OneNAND_Init(), SD_LowLevel_DeInit(), SD_LowLevel_Init(), and SRAM_Init().

#define GPIO_Pin_12 ((uint16_t)0x1000)

Pin 12 selected

Definition at line 139 of file stm32f10x_gpio.h.

Referenced by LCD_CtrlLinesConfig(), LCD_DeInit(), LCD_GPIOConfig(), NAND_Init(), NOR_Init(), OneNAND_Init(), SD_LowLevel_DeInit(), SD_LowLevel_Init(), and SRAM_Init().

#define GPIO_Pin_13 ((uint16_t)0x2000)

Pin 13 selected

Definition at line 140 of file stm32f10x_gpio.h.

Referenced by LCD_CtrlLinesConfig(), LCD_DeInit(), LCD_GPIOConfig(), main(), NOR_Init(), OneNAND_Init(), and SRAM_Init().

#define GPIO_Pin_14 ((uint16_t)0x4000)

Pin 14 selected

Definition at line 141 of file stm32f10x_gpio.h.

Referenced by LCD_CtrlLinesConfig(), LCD_DeInit(), LCD_GPIOConfig(), main(), NAND_Init(), NOR_Init(), OneNAND_Init(), and SRAM_Init().

#define GPIO_Pin_15 ((uint16_t)0x8000)

Pin 15 selected

Definition at line 142 of file stm32f10x_gpio.h.

Referenced by LCD_CtrlLinesConfig(), LCD_DeInit(), LCD_GPIOConfig(), main(), NAND_Init(), NOR_Init(), OneNAND_Init(), and SRAM_Init().

#define GPIO_Pin_2 ((uint16_t)0x0004)

Pin 2 selected

Definition at line 129 of file stm32f10x_gpio.h.

Referenced by GPIO_Configuration(), LCD_GPIOConfig(), main(), NOR_Init(), OneNAND_Init(), SD_LowLevel_DeInit(), SD_LowLevel_Init(), and SRAM_Init().

#define GPIO_Pin_3 ((uint16_t)0x0008)

Pin 3 selected

Definition at line 130 of file stm32f10x_gpio.h.

Referenced by GPIO_Configuration(), LCD_GPIOConfig(), main(), NOR_Init(), OneNAND_Init(), and SRAM_Init().

#define GPIO_Pin_4 ((uint16_t)0x0010)

Pin 4 selected

Definition at line 131 of file stm32f10x_gpio.h.

Referenced by GPIO_Configuration(), LCD_CtrlLinesConfig(), LCD_DeInit(), LCD_GPIOConfig(), main(), NAND_Init(), NOR_Init(), OneNAND_Init(), and SRAM_Init().

#define GPIO_Pin_5 ((uint16_t)0x0020)

Pin 5 selected

Definition at line 132 of file stm32f10x_gpio.h.

Referenced by CAN_Config(), LCD_CtrlLinesConfig(), LCD_DeInit(), LCD_GPIOConfig(), NAND_Init(), NOR_Init(), OneNAND_Init(), and SRAM_Init().

#define GPIO_Pin_6 ((uint16_t)0x0040)

Pin 6 selected

Definition at line 133 of file stm32f10x_gpio.h.

Referenced by ADC1_2_IRQHandler(), CAN_Config(), LCD_GPIOConfig(), main(), NAND_Init(), NOR_GetStatus(), NOR_Init(), OneNAND_Init(), and TIM2_IRQHandler().

#define GPIO_Pin_7 ((uint16_t)0x0080)

Pin 7 selected

Definition at line 134 of file stm32f10x_gpio.h.

Referenced by LCD_CtrlLinesConfig(), LCD_DeInit(), LCD_GPIOConfig(), main(), NAND_Init(), NOR_Init(), OneNAND_Init(), SRAM_Init(), and TIM2_IRQHandler().

#define GPIO_Pin_8 ((uint16_t)0x0100)

Pin 8 selected

Definition at line 135 of file stm32f10x_gpio.h.

Referenced by EXTI9_5_Config(), LCD_CtrlLinesConfig(), LCD_DeInit(), LCD_GPIOConfig(), main(), NAND_Init(), NOR_Init(), OneNAND_Init(), SD_LowLevel_DeInit(), SD_LowLevel_Init(), SRAM_Init(), and TIM2_IRQHandler().

#define GPIO_Pin_9 ((uint16_t)0x0200)

Pin 9 selected

Definition at line 136 of file stm32f10x_gpio.h.

Referenced by EXTI9_5_Config(), LCD_CtrlLinesConfig(), LCD_DeInit(), LCD_GPIOConfig(), main(), NAND_Init(), NOR_Init(), OneNAND_Init(), SD_LowLevel_DeInit(), SD_LowLevel_Init(), SRAM_Init(), and TIM2_IRQHandler().

#define GPIO_Pin_All ((uint16_t)0xFFFF)

All pins selected

Definition at line 143 of file stm32f10x_gpio.h.

Referenced by GPIO_StructInit().

#define IS_GET_GPIO_PIN ( PIN )
Value:
(((PIN) == GPIO_Pin_0) || \
                              ((PIN) == GPIO_Pin_1) || \
                              ((PIN) == GPIO_Pin_2) || \
                              ((PIN) == GPIO_Pin_3) || \
                              ((PIN) == GPIO_Pin_4) || \
                              ((PIN) == GPIO_Pin_5) || \
                              ((PIN) == GPIO_Pin_6) || \
                              ((PIN) == GPIO_Pin_7) || \
                              ((PIN) == GPIO_Pin_8) || \
                              ((PIN) == GPIO_Pin_9) || \
                              ((PIN) == GPIO_Pin_10) || \
                              ((PIN) == GPIO_Pin_11) || \
                              ((PIN) == GPIO_Pin_12) || \
                              ((PIN) == GPIO_Pin_13) || \
                              ((PIN) == GPIO_Pin_14) || \
                              ((PIN) == GPIO_Pin_15))

Definition at line 147 of file stm32f10x_gpio.h.

Referenced by GPIO_ReadInputDataBit(), GPIO_ReadOutputDataBit(), and GPIO_WriteBit().

#define IS_GPIO_PIN ( PIN ) ((((PIN) & (uint16_t)0x00) == 0x00) && ((PIN) != (uint16_t)0x00))

Definition at line 145 of file stm32f10x_gpio.h.

Referenced by GPIO_Init(), GPIO_PinLockConfig(), GPIO_ResetBits(), and GPIO_SetBits().


STM32F10x Standard Peripherals Firmware Library: GPIO_Remap_define

Defines

GPIO_Remap_define

GPIO_Exported_Constants

Defines

#define | GPIO_FullRemap_TIM1 ((uint32_t)0x001600C0)
#define | GPIO_FullRemap_TIM2 ((uint32_t)0x00180300)
#define | GPIO_FullRemap_TIM3 ((uint32_t)0x001A0C00)
#define | GPIO_FullRemap_USART3 ((uint32_t)0x00140030)
#define | GPIO_PartialRemap1_TIM2 ((uint32_t)0x00180100)
#define | GPIO_PartialRemap2_TIM2 ((uint32_t)0x00180200)
#define | GPIO_PartialRemap_TIM1 ((uint32_t)0x00160040)
#define | GPIO_PartialRemap_TIM3 ((uint32_t)0x001A0800)
#define | GPIO_PartialRemap_USART3 ((uint32_t)0x00140010)
#define | GPIO_Remap1_CAN1 ((uint32_t)0x001D4000)
#define | GPIO_Remap2_CAN1 ((uint32_t)0x001D6000)
#define | GPIO_Remap_ADC1_ETRGINJ ((uint32_t)0x00200002)
#define | GPIO_Remap_ADC1_ETRGREG ((uint32_t)0x00200004)
#define | GPIO_Remap_ADC2_ETRGINJ ((uint32_t)0x00200008)
#define | GPIO_Remap_ADC2_ETRGREG ((uint32_t)0x00200010)
#define | GPIO_Remap_CAN2 ((uint32_t)0x00200040)
#define | GPIO_Remap_CEC ((uint32_t)0x80000008)
#define | GPIO_Remap_ETH ((uint32_t)0x00200020)
#define | GPIO_Remap_FSMC_NADV ((uint32_t)0x80000400)
#define | GPIO_Remap_I2C1 ((uint32_t)0x00000002)
#define | GPIO_Remap_MISC ((uint32_t)0x80002000)
#define | GPIO_Remap_PD01 ((uint32_t)0x00008000)
#define | GPIO_Remap_PTP_PPS ((uint32_t)0x00204000)
#define | GPIO_Remap_SPI1 ((uint32_t)0x00000001)
#define | GPIO_Remap_SPI3 ((uint32_t)0x00201100)
#define | GPIO_Remap_SWJ_Disable ((uint32_t)0x00300400)
#define | GPIO_Remap_SWJ_JTAGDisable ((uint32_t)0x00300200)
#define | GPIO_Remap_SWJ_NoJTRST ((uint32_t)0x00300100)
#define | GPIO_Remap_TIM10 ((uint32_t)0x80000040)
#define | GPIO_Remap_TIM11 ((uint32_t)0x80000080)
#define | GPIO_Remap_TIM12 ((uint32_t)0x80001000)
#define | GPIO_Remap_TIM13 ((uint32_t)0x80000100)
#define | GPIO_Remap_TIM14 ((uint32_t)0x80000200)
#define | GPIO_Remap_TIM15 ((uint32_t)0x80000001)
#define | GPIO_Remap_TIM16 ((uint32_t)0x80000002)
#define | GPIO_Remap_TIM17 ((uint32_t)0x80000004)
#define | GPIO_Remap_TIM1_DMA ((uint32_t)0x80000010)
#define | GPIO_Remap_TIM2ITR1_PTP_SOF ((uint32_t)0x00202000)
#define | GPIO_Remap_TIM4 ((uint32_t)0x00001000)
#define | GPIO_Remap_TIM5CH4_LSI ((uint32_t)0x00200001)
#define | GPIO_Remap_TIM67_DAC_DMA ((uint32_t)0x80000800)
#define | GPIO_Remap_TIM9 ((uint32_t)0x80000020)
#define | GPIO_Remap_USART1 ((uint32_t)0x00000004)
#define | GPIO_Remap_USART2 ((uint32_t)0x00000008)
#define | IS_GPIO_REMAP(REMAP)

Define Documentation

#define GPIO_FullRemap_TIM1 ((uint32_t)0x001600C0)

TIM1 Full Alternate Function mapping

Definition at line 179 of file stm32f10x_gpio.h.

#define GPIO_FullRemap_TIM2 ((uint32_t)0x00180300)

TIM2 Full Alternate Function mapping

Definition at line 182 of file stm32f10x_gpio.h.

#define GPIO_FullRemap_TIM3 ((uint32_t)0x001A0C00)

TIM3 Full Alternate Function mapping

Definition at line 184 of file stm32f10x_gpio.h.

#define GPIO_FullRemap_USART3 ((uint32_t)0x00140030)

USART3 Full Alternate Function mapping

Definition at line 177 of file stm32f10x_gpio.h.

#define GPIO_PartialRemap1_TIM2 ((uint32_t)0x00180100)

TIM2 Partial1 Alternate Function mapping

Definition at line 180 of file stm32f10x_gpio.h.

#define GPIO_PartialRemap2_TIM2 ((uint32_t)0x00180200)

TIM2 Partial2 Alternate Function mapping

Definition at line 181 of file stm32f10x_gpio.h.

#define GPIO_PartialRemap_TIM1 ((uint32_t)0x00160040)

TIM1 Partial Alternate Function mapping

Definition at line 178 of file stm32f10x_gpio.h.

#define GPIO_PartialRemap_TIM3 ((uint32_t)0x001A0800)

TIM3 Partial Alternate Function mapping

Definition at line 183 of file stm32f10x_gpio.h.

#define GPIO_PartialRemap_USART3 ((uint32_t)0x00140010)

USART3 Partial Alternate Function mapping

Definition at line 176 of file stm32f10x_gpio.h.

#define GPIO_Remap1_CAN1 ((uint32_t)0x001D4000)

CAN1 Alternate Function mapping

Definition at line 186 of file stm32f10x_gpio.h.

#define GPIO_Remap2_CAN1 ((uint32_t)0x001D6000)

CAN1 Alternate Function mapping

Definition at line 187 of file stm32f10x_gpio.h.

Referenced by CAN_Config().

#define GPIO_Remap_ADC1_ETRGINJ ((uint32_t)0x00200002)

ADC1 External Trigger Injected Conversion remapping

Definition at line 190 of file stm32f10x_gpio.h.

#define GPIO_Remap_ADC1_ETRGREG ((uint32_t)0x00200004)

ADC1 External Trigger Regular Conversion remapping

Definition at line 191 of file stm32f10x_gpio.h.

#define GPIO_Remap_ADC2_ETRGINJ ((uint32_t)0x00200008)

ADC2 External Trigger Injected Conversion remapping

Definition at line 192 of file stm32f10x_gpio.h.

#define GPIO_Remap_ADC2_ETRGREG ((uint32_t)0x00200010)

ADC2 External Trigger Regular Conversion remapping

Definition at line 193 of file stm32f10x_gpio.h.

#define GPIO_Remap_CAN2 ((uint32_t)0x00200040)

CAN2 remapping (only for Connectivity line devices)

Definition at line 195 of file stm32f10x_gpio.h.

Referenced by CAN_Config().

#define GPIO_Remap_CEC ((uint32_t)0x80000008)

CEC Alternate Function mapping (only for Value line devices)

Definition at line 208 of file stm32f10x_gpio.h.

#define GPIO_Remap_ETH ((uint32_t)0x00200020)

Ethernet remapping (only for Connectivity line devices)

Definition at line 194 of file stm32f10x_gpio.h.

#define GPIO_Remap_FSMC_NADV ((uint32_t)0x80000400)

FSMC_NADV Alternate Function mapping (only for High density Value line and XL-density devices)

Definition at line 216 of file stm32f10x_gpio.h.

Referenced by OneNAND_Init().

#define GPIO_Remap_I2C1 ((uint32_t)0x00000002)

I2C1 Alternate Function mapping

Definition at line 173 of file stm32f10x_gpio.h.

#define GPIO_Remap_MISC ((uint32_t)0x80002000)

Miscellaneous Remap (DMA2 Channel5 Position and DAC Trigger remapping, only for High density Value line devices)

Definition at line 220 of file stm32f10x_gpio.h.

#define GPIO_Remap_PD01 ((uint32_t)0x00008000)

PD01 Alternate Function mapping

Definition at line 188 of file stm32f10x_gpio.h.

#define GPIO_Remap_PTP_PPS ((uint32_t)0x00204000)

Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices)

Definition at line 203 of file stm32f10x_gpio.h.

#define GPIO_Remap_SPI1 ((uint32_t)0x00000001)

SPI1 Alternate Function mapping

Definition at line 172 of file stm32f10x_gpio.h.

#define GPIO_Remap_SPI3 ((uint32_t)0x00201100)

SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices)

Definition at line 199 of file stm32f10x_gpio.h.

Referenced by GPIO_Configuration(), LCD_DeInit(), LCD_SPIConfig(), SD_LowLevel_DeInit(), and SD_LowLevel_Init().

#define GPIO_Remap_SWJ_Disable ((uint32_t)0x00300400)

Full SWJ Disabled (JTAG-DP + SW-DP)

Definition at line 198 of file stm32f10x_gpio.h.

Referenced by main().

#define GPIO_Remap_SWJ_JTAGDisable ((uint32_t)0x00300200)

JTAG-DP Disabled and SW-DP Enabled

Definition at line 197 of file stm32f10x_gpio.h.

#define GPIO_Remap_SWJ_NoJTRST ((uint32_t)0x00300100)

Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST

Definition at line 196 of file stm32f10x_gpio.h.

#define GPIO_Remap_TIM10 ((uint32_t)0x80000040)

TIM10 Alternate Function mapping (only for XL-density devices)

Definition at line 212 of file stm32f10x_gpio.h.

#define GPIO_Remap_TIM11 ((uint32_t)0x80000080)

TIM11 Alternate Function mapping (only for XL-density devices)

Definition at line 213 of file stm32f10x_gpio.h.

#define GPIO_Remap_TIM12 ((uint32_t)0x80001000)

TIM12 Alternate Function mapping (only for High density Value line devices)

Definition at line 219 of file stm32f10x_gpio.h.

#define GPIO_Remap_TIM13 ((uint32_t)0x80000100)

TIM13 Alternate Function mapping (only for High density Value line and XL-density devices)

Definition at line 214 of file stm32f10x_gpio.h.

#define GPIO_Remap_TIM14 ((uint32_t)0x80000200)

TIM14 Alternate Function mapping (only for High density Value line and XL-density devices)

Definition at line 215 of file stm32f10x_gpio.h.

#define GPIO_Remap_TIM15 ((uint32_t)0x80000001)

TIM15 Alternate Function mapping (only for Value line devices)

Definition at line 205 of file stm32f10x_gpio.h.

#define GPIO_Remap_TIM16 ((uint32_t)0x80000002)

TIM16 Alternate Function mapping (only for Value line devices)

Definition at line 206 of file stm32f10x_gpio.h.

#define GPIO_Remap_TIM17 ((uint32_t)0x80000004)

TIM17 Alternate Function mapping (only for Value line devices)

Definition at line 207 of file stm32f10x_gpio.h.

#define GPIO_Remap_TIM1_DMA ((uint32_t)0x80000010)

TIM1 DMA requests mapping (only for Value line devices)

Definition at line 209 of file stm32f10x_gpio.h.

#define GPIO_Remap_TIM2ITR1_PTP_SOF ((uint32_t)0x00202000)

Ethernet PTP output or USB OTG SOF (Start of Frame) connected to TIM2 Internal Trigger 1 for calibration (only for Connectivity line devices)

Definition at line 200 of file stm32f10x_gpio.h.

#define GPIO_Remap_TIM4 ((uint32_t)0x00001000)

TIM4 Alternate Function mapping

Definition at line 185 of file stm32f10x_gpio.h.

#define GPIO_Remap_TIM5CH4_LSI ((uint32_t)0x00200001)

LSI connected to TIM5 Channel4 input capture for calibration

Definition at line 189 of file stm32f10x_gpio.h.

Referenced by main(), and TIM5_ConfigForLSI().

#define GPIO_Remap_TIM67_DAC_DMA ((uint32_t)0x80000800)

TIM6/TIM7 and DAC DMA requests remapping (only for High density Value line devices)

Definition at line 218 of file stm32f10x_gpio.h.

#define GPIO_Remap_TIM9 ((uint32_t)0x80000020)

TIM9 Alternate Function mapping (only for XL-density devices)

Definition at line 211 of file stm32f10x_gpio.h.

#define GPIO_Remap_USART1 ((uint32_t)0x00000004)

USART1 Alternate Function mapping

Definition at line 174 of file stm32f10x_gpio.h.

#define GPIO_Remap_USART2 ((uint32_t)0x00000008)

USART2 Alternate Function mapping

Definition at line 175 of file stm32f10x_gpio.h.

Referenced by STM_EVAL_COMInit().

#define IS_GPIO_REMAP ( REMAP )
Value:
(((REMAP) == GPIO_Remap_SPI1) || ((REMAP) == GPIO_Remap_I2C1) || \
                              ((REMAP) == GPIO_Remap_USART1) || ((REMAP) == GPIO_Remap_USART2) || \
                              ((REMAP) == GPIO_PartialRemap_USART3) || ((REMAP) == GPIO_FullRemap_USART3) || \
                              ((REMAP) == GPIO_PartialRemap_TIM1) || ((REMAP) == GPIO_FullRemap_TIM1) || \
                              ((REMAP) == GPIO_PartialRemap1_TIM2) || ((REMAP) == GPIO_PartialRemap2_TIM2) || \
                              ((REMAP) == GPIO_FullRemap_TIM2) || ((REMAP) == GPIO_PartialRemap_TIM3) || \
                              ((REMAP) == GPIO_FullRemap_TIM3) || ((REMAP) == GPIO_Remap_TIM4) || \
                              ((REMAP) == GPIO_Remap1_CAN1) || ((REMAP) == GPIO_Remap2_CAN1) || \
                              ((REMAP) == GPIO_Remap_PD01) || ((REMAP) == GPIO_Remap_TIM5CH4_LSI) || \
                              ((REMAP) == GPIO_Remap_ADC1_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC1_ETRGREG) || \
                              ((REMAP) == GPIO_Remap_ADC2_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC2_ETRGREG) || \
                              ((REMAP) == GPIO_Remap_ETH) ||((REMAP) == GPIO_Remap_CAN2) || \
                              ((REMAP) == GPIO_Remap_SWJ_NoJTRST) || ((REMAP) == GPIO_Remap_SWJ_JTAGDisable) || \
                              ((REMAP) == GPIO_Remap_SWJ_Disable)|| ((REMAP) == GPIO_Remap_SPI3) || \
                              ((REMAP) == GPIO_Remap_TIM2ITR1_PTP_SOF) || ((REMAP) == GPIO_Remap_PTP_PPS) || \
                              ((REMAP) == GPIO_Remap_TIM15) || ((REMAP) == GPIO_Remap_TIM16) || \
                              ((REMAP) == GPIO_Remap_TIM17) || ((REMAP) == GPIO_Remap_CEC) || \
                              ((REMAP) == GPIO_Remap_TIM1_DMA) || ((REMAP) == GPIO_Remap_TIM9) || \
                              ((REMAP) == GPIO_Remap_TIM10) || ((REMAP) == GPIO_Remap_TIM11) || \
                              ((REMAP) == GPIO_Remap_TIM13) || ((REMAP) == GPIO_Remap_TIM14) || \
                              ((REMAP) == GPIO_Remap_FSMC_NADV) || ((REMAP) == GPIO_Remap_TIM67_DAC_DMA) || \
                              ((REMAP) == GPIO_Remap_TIM12) || ((REMAP) == GPIO_Remap_MISC))

Definition at line 223 of file stm32f10x_gpio.h.

Referenced by GPIO_PinRemapConfig().


STM32F10x Standard Peripherals Firmware Library: GPIO_Port_Sources

Defines

GPIO_Port_Sources

GPIO_Exported_Constants

Defines

#define | GPIO_PortSourceGPIOA ((uint8_t)0x00)
#define | GPIO_PortSourceGPIOB ((uint8_t)0x01)
#define | GPIO_PortSourceGPIOC ((uint8_t)0x02)
#define | GPIO_PortSourceGPIOD ((uint8_t)0x03)
#define | GPIO_PortSourceGPIOE ((uint8_t)0x04)
#define | GPIO_PortSourceGPIOF ((uint8_t)0x05)
#define | GPIO_PortSourceGPIOG ((uint8_t)0x06)
#define | IS_GPIO_EVENTOUT_PORT_SOURCE(PORTSOURCE)
#define | IS_GPIO_EXTI_PORT_SOURCE(PORTSOURCE)

Define Documentation

#define GPIO_PortSourceGPIOA ((uint8_t)0x00)

Definition at line 254 of file stm32f10x_gpio.h.

Referenced by EXTI0_Config().

#define GPIO_PortSourceGPIOB ((uint8_t)0x01)

Definition at line 255 of file stm32f10x_gpio.h.

Referenced by EXTI9_5_Config(), and HDMI_CEC_CommandCallBack().

#define GPIO_PortSourceGPIOC ((uint8_t)0x02)

Definition at line 256 of file stm32f10x_gpio.h.

#define GPIO_PortSourceGPIOD ((uint8_t)0x03)

Definition at line 257 of file stm32f10x_gpio.h.

#define GPIO_PortSourceGPIOE ((uint8_t)0x04)

Definition at line 258 of file stm32f10x_gpio.h.

Referenced by EXTI_Configuration().

#define GPIO_PortSourceGPIOF ((uint8_t)0x05)

Definition at line 259 of file stm32f10x_gpio.h.

Referenced by EXTI_Configuration().

#define GPIO_PortSourceGPIOG ((uint8_t)0x06)

Definition at line 260 of file stm32f10x_gpio.h.

Referenced by EXTI9_5_Config().

#define IS_GPIO_EVENTOUT_PORT_SOURCE ( PORTSOURCE )
Value:
(((PORTSOURCE) == GPIO_PortSourceGPIOA) || \
                                                  ((PORTSOURCE) == GPIO_PortSourceGPIOB) || \
                                                  ((PORTSOURCE) == GPIO_PortSourceGPIOC) || \
                                                  ((PORTSOURCE) == GPIO_PortSourceGPIOD) || \
                                                  ((PORTSOURCE) == GPIO_PortSourceGPIOE))

Definition at line 261 of file stm32f10x_gpio.h.

Referenced by GPIO_EventOutputConfig().

#define IS_GPIO_EXTI_PORT_SOURCE ( PORTSOURCE )
Value:
(((PORTSOURCE) == GPIO_PortSourceGPIOA) || \
                                              ((PORTSOURCE) == GPIO_PortSourceGPIOB) || \
                                              ((PORTSOURCE) == GPIO_PortSourceGPIOC) || \
                                              ((PORTSOURCE) == GPIO_PortSourceGPIOD) || \
                                              ((PORTSOURCE) == GPIO_PortSourceGPIOE) || \
                                              ((PORTSOURCE) == GPIO_PortSourceGPIOF) || \
                                              ((PORTSOURCE) == GPIO_PortSourceGPIOG))

Definition at line 267 of file stm32f10x_gpio.h.

Referenced by GPIO_EXTILineConfig().


STM32F10x Standard Peripherals Firmware Library: GPIO_Pin_sources

Defines

GPIO_Pin_sources

GPIO_Exported_Constants

Defines

#define | GPIO_PinSource0 ((uint8_t)0x00)
#define | GPIO_PinSource1 ((uint8_t)0x01)
#define | GPIO_PinSource10 ((uint8_t)0x0A)
#define | GPIO_PinSource11 ((uint8_t)0x0B)
#define | GPIO_PinSource12 ((uint8_t)0x0C)
#define | GPIO_PinSource13 ((uint8_t)0x0D)
#define | GPIO_PinSource14 ((uint8_t)0x0E)
#define | GPIO_PinSource15 ((uint8_t)0x0F)
#define | GPIO_PinSource2 ((uint8_t)0x02)
#define | GPIO_PinSource3 ((uint8_t)0x03)
#define | GPIO_PinSource4 ((uint8_t)0x04)
#define | GPIO_PinSource5 ((uint8_t)0x05)
#define | GPIO_PinSource6 ((uint8_t)0x06)
#define | GPIO_PinSource7 ((uint8_t)0x07)
#define | GPIO_PinSource8 ((uint8_t)0x08)
#define | GPIO_PinSource9 ((uint8_t)0x09)
#define | IS_GPIO_PIN_SOURCE(PINSOURCE)

Define Documentation

#define GPIO_PinSource0 ((uint8_t)0x00)

Definition at line 283 of file stm32f10x_gpio.h.

Referenced by EXTI0_Config(), and LCD_GPIOConfig().

#define GPIO_PinSource1 ((uint8_t)0x01)

Definition at line 284 of file stm32f10x_gpio.h.

Referenced by LCD_GPIOConfig().

#define GPIO_PinSource10 ((uint8_t)0x0A)

Definition at line 293 of file stm32f10x_gpio.h.

Referenced by LCD_GPIOConfig().

#define GPIO_PinSource11 ((uint8_t)0x0B)

Definition at line 294 of file stm32f10x_gpio.h.

Referenced by EXTI_Configuration(), and LCD_GPIOConfig().

#define GPIO_PinSource12 ((uint8_t)0x0C)

Definition at line 295 of file stm32f10x_gpio.h.

Referenced by LCD_GPIOConfig().

#define GPIO_PinSource13 ((uint8_t)0x0D)

Definition at line 296 of file stm32f10x_gpio.h.

Referenced by LCD_GPIOConfig().

#define GPIO_PinSource14 ((uint8_t)0x0E)

Definition at line 297 of file stm32f10x_gpio.h.

Referenced by LCD_GPIOConfig().

#define GPIO_PinSource15 ((uint8_t)0x0F)

Definition at line 298 of file stm32f10x_gpio.h.

Referenced by EXTI_Configuration(), and LCD_GPIOConfig().

#define GPIO_PinSource2 ((uint8_t)0x02)

Definition at line 285 of file stm32f10x_gpio.h.

Referenced by LCD_GPIOConfig().

#define GPIO_PinSource3 ((uint8_t)0x03)

Definition at line 286 of file stm32f10x_gpio.h.

Referenced by LCD_GPIOConfig().

#define GPIO_PinSource4 ((uint8_t)0x04)

Definition at line 287 of file stm32f10x_gpio.h.

Referenced by LCD_GPIOConfig().

#define GPIO_PinSource5 ((uint8_t)0x05)

Definition at line 288 of file stm32f10x_gpio.h.

Referenced by LCD_GPIOConfig().

#define GPIO_PinSource6 ((uint8_t)0x06)

Definition at line 289 of file stm32f10x_gpio.h.

Referenced by LCD_GPIOConfig().

#define GPIO_PinSource7 ((uint8_t)0x07)

Definition at line 290 of file stm32f10x_gpio.h.

Referenced by LCD_GPIOConfig().

#define GPIO_PinSource8 ((uint8_t)0x08)

Definition at line 291 of file stm32f10x_gpio.h.

Referenced by EXTI9_5_Config(), HDMI_CEC_CommandCallBack(), and LCD_GPIOConfig().

#define GPIO_PinSource9 ((uint8_t)0x09)

Definition at line 292 of file stm32f10x_gpio.h.

Referenced by EXTI9_5_Config(), and LCD_GPIOConfig().

#define IS_GPIO_PIN_SOURCE ( PINSOURCE )
Value:
(((PINSOURCE) == GPIO_PinSource0) || \
                                       ((PINSOURCE) == GPIO_PinSource1) || \
                                       ((PINSOURCE) == GPIO_PinSource2) || \
                                       ((PINSOURCE) == GPIO_PinSource3) || \
                                       ((PINSOURCE) == GPIO_PinSource4) || \
                                       ((PINSOURCE) == GPIO_PinSource5) || \
                                       ((PINSOURCE) == GPIO_PinSource6) || \
                                       ((PINSOURCE) == GPIO_PinSource7) || \
                                       ((PINSOURCE) == GPIO_PinSource8) || \
                                       ((PINSOURCE) == GPIO_PinSource9) || \
                                       ((PINSOURCE) == GPIO_PinSource10) || \
                                       ((PINSOURCE) == GPIO_PinSource11) || \
                                       ((PINSOURCE) == GPIO_PinSource12) || \
                                       ((PINSOURCE) == GPIO_PinSource13) || \
                                       ((PINSOURCE) == GPIO_PinSource14) || \
                                       ((PINSOURCE) == GPIO_PinSource15))

Definition at line 300 of file stm32f10x_gpio.h.

Referenced by GPIO_EventOutputConfig(), and GPIO_EXTILineConfig().


STM32F10x Standard Peripherals Firmware Library: Ethernet_Media_Interface

Defines

Ethernet_Media_Interface

GPIO_Exported_Constants

Defines

#define | GPIO_ETH_MediaInterface_MII ((u32)0x00000000)
#define | GPIO_ETH_MediaInterface_RMII ((u32)0x00000001)
#define | IS_GPIO_ETH_MEDIA_INTERFACE(INTERFACE)

Define Documentation

#define GPIO_ETH_MediaInterface_MII ((u32)0x00000000)

Definition at line 324 of file stm32f10x_gpio.h.

#define GPIO_ETH_MediaInterface_RMII ((u32)0x00000001)

Definition at line 325 of file stm32f10x_gpio.h.

#define IS_GPIO_ETH_MEDIA_INTERFACE ( INTERFACE )
Value:
(((INTERFACE) == GPIO_ETH_MediaInterface_MII) || \
                                                ((INTERFACE) == GPIO_ETH_MediaInterface_RMII))

Definition at line 327 of file stm32f10x_gpio.h.

Referenced by GPIO_ETH_MediaInterfaceConfig().


STM32F10x Standard Peripherals Firmware Library: GPIO_Exported_Macros

GPIO_Exported_Macros

GPIO


STM32F10x Standard Peripherals Firmware Library: GPIO_Exported_Functions

Functions

GPIO_Exported_Functions

GPIO

Functions

void | GPIO_AFIODeInit (void)
Deinitializes the Alternate Functions (remap, event control and EXTI configuration) registers to their default reset values.
void | GPIO_DeInit (GPIO_TypeDef *GPIOx)
Deinitializes the GPIOx peripheral registers to their default reset values.
void | GPIO_ETH_MediaInterfaceConfig (uint32_t GPIO_ETH_MediaInterface)
Selects the Ethernet media interface.
void | GPIO_EventOutputCmd (FunctionalState NewState)
Enables or disables the Event Output.
void | GPIO_EventOutputConfig (uint8_t GPIO_PortSource, uint8_t GPIO_PinSource)
Selects the GPIO pin used as Event output.
void | GPIO_EXTILineConfig (uint8_t GPIO_PortSource, uint8_t GPIO_PinSource)
Selects the GPIO pin used as EXTI Line.
void | GPIO_Init (GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct)
Initializes the GPIOx peripheral according to the specified parameters in the GPIO_InitStruct.
void | GPIO_PinLockConfig (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Locks GPIO Pins configuration registers.
void | GPIO_PinRemapConfig (uint32_t GPIO_Remap, FunctionalState NewState)
Changes the mapping of the specified pin.
uint16_t | GPIO_ReadInputData (GPIO_TypeDef *GPIOx)
Reads the specified GPIO input data port.
uint8_t | GPIO_ReadInputDataBit (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Reads the specified input port pin.
uint16_t | GPIO_ReadOutputData (GPIO_TypeDef *GPIOx)
Reads the specified GPIO output data port.
uint8_t | GPIO_ReadOutputDataBit (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Reads the specified output data port bit.
void | GPIO_ResetBits (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Clears the selected data port bits.
void | GPIO_SetBits (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Sets the selected data port bits.
void | GPIO_StructInit (GPIO_InitTypeDef *GPIO_InitStruct)
Fills each GPIO_InitStruct member with its default value.
void | GPIO_Write (GPIO_TypeDef *GPIOx, uint16_t PortVal)
Writes data to the specified GPIO data port.
void | GPIO_WriteBit (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
Sets or clears the selected data port bit.

Function Documentation

void GPIO_AFIODeInit ( void )

Deinitializes the Alternate Functions (remap, event control and EXTI configuration) registers to their default reset values.

Parameters:
None
Return values:
None

Definition at line 159 of file stm32f10x_gpio.c.

References DISABLE, ENABLE, RCC_APB2Periph_AFIO, and RCC_APB2PeriphResetCmd().

void GPIO_DeInit ( GPIO_TypeDef * GPIOx )

Deinitializes the GPIOx peripheral registers to their default reset values.

Parameters:
GPIOx,: where x can be (A..G) to select the GPIO peripheral.
Return values:
None

Definition at line 108 of file stm32f10x_gpio.c.

References assert_param, DISABLE, ENABLE, GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, IS_GPIO_ALL_PERIPH, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB, RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE, RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, and RCC_APB2PeriphResetCmd().

void GPIO_ETH_MediaInterfaceConfig ( uint32_t GPIO_ETH_MediaInterface )

Selects the Ethernet media interface.

Note:
This function applies only to STM32 Connectivity line devices.
Parameters:
GPIO_ETH_MediaInterface,: specifies the Media Interface mode. This parameter can be one of the following values:

  • GPIO_ETH_MediaInterface_MII: MII mode
  • GPIO_ETH_MediaInterface_RMII: RMII mode
Return values:
None

Definition at line 630 of file stm32f10x_gpio.c.

References assert_param, IS_GPIO_ETH_MEDIA_INTERFACE, and MAPR_MII_RMII_SEL_BB.

void GPIO_EventOutputCmd ( FunctionalState NewState )

Enables or disables the Event Output.

Parameters:
NewState,: new state of the Event output. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 483 of file stm32f10x_gpio.c.

References assert_param, EVCR_EVOE_BB, and IS_FUNCTIONAL_STATE.

void GPIO_EventOutputConfig | ( | uint8_t | GPIO_PortSource,
 |  | uint8_t | GPIO_PinSource
 | ) |  |

Selects the GPIO pin used as Event output.

Parameters:
GPIO_PortSource,: selects the GPIO port to be used as source for Event output. This parameter can be GPIO_PortSourceGPIOx where x can be (A..E).
GPIO_PinSource,: specifies the pin for the Event output. This parameter can be GPIO_PinSourcex where x can be (0..15).
Return values:
None

Definition at line 462 of file stm32f10x_gpio.c.

References AFIO, assert_param, EVCR_PORTPINCONFIG_MASK, IS_GPIO_EVENTOUT_PORT_SOURCE, and IS_GPIO_PIN_SOURCE.

void GPIO_EXTILineConfig | ( | uint8_t | GPIO_PortSource,
 |  | uint8_t | GPIO_PinSource
 | ) |  |

Selects the GPIO pin used as EXTI Line.

Parameters:
GPIO_PortSource,: selects the GPIO port to be used as source for EXTI lines. This parameter can be GPIO_PortSourceGPIOx where x can be (A..G).
GPIO_PinSource,: specifies the EXTI line to be configured. This parameter can be GPIO_PinSourcex where x can be (0..15).
Return values:
None

Definition at line 609 of file stm32f10x_gpio.c.

References AFIO, assert_param, IS_GPIO_EXTI_PORT_SOURCE, and IS_GPIO_PIN_SOURCE.

Referenced by EXTI0_Config(), EXTI9_5_Config(), EXTI_Configuration(), HDMI_CEC_CommandCallBack(), IOE_EXTI_Config(), IOE_GPIO_Config(), and STM_EVAL_PBInit().

void GPIO_Init | ( | GPIO_TypeDef * | GPIOx,
 |  | GPIO_InitTypeDef * | GPIO_InitStruct
 | ) |  |

Initializes the GPIOx peripheral according to the specified parameters in the GPIO_InitStruct.

Parameters:
GPIOx,: where x can be (A..G) to select the GPIO peripheral.
GPIO_InitStruct,: pointer to a GPIO_InitTypeDef structure that contains the configuration information for the specified GPIO peripheral.
Return values:
None

Definition at line 173 of file stm32f10x_gpio.c.

References assert_param, GPIO_TypeDef::BRR, GPIO_TypeDef::BSRR, GPIO_TypeDef::CRH, GPIO_TypeDef::CRL, GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_IPD, GPIO_Mode_IPU, GPIO_InitTypeDef::GPIO_Pin, GPIO_InitTypeDef::GPIO_Speed, IS_GPIO_ALL_PERIPH, IS_GPIO_MODE, IS_GPIO_PIN, and IS_GPIO_SPEED.

Referenced by CAN_Config(), EXTI0_Config(), EXTI9_5_Config(), GPIO_Configuration(), HDMI_CEC_Init(), IOE_EXTI_Config(), IOE_GPIO_Config(), LCD_CtrlLinesConfig(), LCD_DeInit(), LCD_GPIOConfig(), LCD_SPIConfig(), LM75_LowLevel_DeInit(), LM75_LowLevel_Init(), main(), NAND_Init(), NOR_Init(), OneNAND_Init(), SD_LowLevel_DeInit(), SD_LowLevel_Init(), sEE_LowLevel_DeInit(), sEE_LowLevel_Init(), sFLASH_LowLevel_DeInit(), sFLASH_LowLevel_Init(), SRAM_Init(), STM32L152_LCD_DeInit(), STM_EVAL_COMInit(), STM_EVAL_LEDInit(), and STM_EVAL_PBInit().

void GPIO_PinLockConfig | ( | GPIO_TypeDef * | GPIOx,
 |  | uint16_t | GPIO_Pin
 | ) |  |

Locks GPIO Pins configuration registers.

Parameters:
GPIOx,: where x can be (A..G) to select the GPIO peripheral.
GPIO_Pin,: specifies the port bit to be written. This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
Return values:
None

Definition at line 432 of file stm32f10x_gpio.c.

References assert_param, IS_GPIO_ALL_PERIPH, IS_GPIO_PIN, and GPIO_TypeDef::LCKR.

void GPIO_PinRemapConfig | ( | uint32_t | GPIO_Remap,
 |  | FunctionalState | NewState
 | ) |  |

Changes the mapping of the specified pin.

Parameters:
GPIO_Remap,: selects the pin to remap. This parameter can be one of the following values:

  • GPIO_Remap_SPI1 : SPI1 Alternate Function mapping
  • GPIO_Remap_I2C1 : I2C1 Alternate Function mapping
  • GPIO_Remap_USART1 : USART1 Alternate Function mapping
  • GPIO_Remap_USART2 : USART2 Alternate Function mapping
  • GPIO_PartialRemap_USART3 : USART3 Partial Alternate Function mapping
  • GPIO_FullRemap_USART3 : USART3 Full Alternate Function mapping
  • GPIO_PartialRemap_TIM1 : TIM1 Partial Alternate Function mapping
  • GPIO_FullRemap_TIM1 : TIM1 Full Alternate Function mapping
  • GPIO_PartialRemap1_TIM2 : TIM2 Partial1 Alternate Function mapping
  • GPIO_PartialRemap2_TIM2 : TIM2 Partial2 Alternate Function mapping
  • GPIO_FullRemap_TIM2 : TIM2 Full Alternate Function mapping
  • GPIO_PartialRemap_TIM3 : TIM3 Partial Alternate Function mapping
  • GPIO_FullRemap_TIM3 : TIM3 Full Alternate Function mapping
  • GPIO_Remap_TIM4 : TIM4 Alternate Function mapping
  • GPIO_Remap1_CAN1 : CAN1 Alternate Function mapping
  • GPIO_Remap2_CAN1 : CAN1 Alternate Function mapping
  • GPIO_Remap_PD01 : PD01 Alternate Function mapping
  • GPIO_Remap_TIM5CH4_LSI : LSI connected to TIM5 Channel4 input capture for calibration
  • GPIO_Remap_ADC1_ETRGINJ : ADC1 External Trigger Injected Conversion remapping
  • GPIO_Remap_ADC1_ETRGREG : ADC1 External Trigger Regular Conversion remapping
  • GPIO_Remap_ADC2_ETRGINJ : ADC2 External Trigger Injected Conversion remapping
  • GPIO_Remap_ADC2_ETRGREG : ADC2 External Trigger Regular Conversion remapping
  • GPIO_Remap_ETH : Ethernet remapping (only for Connectivity line devices)
  • GPIO_Remap_CAN2 : CAN2 remapping (only for Connectivity line devices)
  • GPIO_Remap_SWJ_NoJTRST : Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST
  • GPIO_Remap_SWJ_JTAGDisable : JTAG-DP Disabled and SW-DP Enabled
  • GPIO_Remap_SWJ_Disable : Full SWJ Disabled (JTAG-DP + SW-DP)
  • GPIO_Remap_SPI3 : SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices) When the SPI3/I2S3 is remapped using this function, the SWJ is configured to Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST.
  • GPIO_Remap_TIM2ITR1_PTP_SOF : Ethernet PTP output or USB OTG SOF (Start of Frame) connected to TIM2 Internal Trigger 1 for calibration (only for Connectivity line devices) If the GPIO_Remap_TIM2ITR1_PTP_SOF is enabled the TIM2 ITR1 is connected to Ethernet PTP output. When Reset TIM2 ITR1 is connected to USB OTG SOF output.
  • GPIO_Remap_PTP_PPS : Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices)
  • GPIO_Remap_TIM15 : TIM15 Alternate Function mapping (only for Value line devices)
  • GPIO_Remap_TIM16 : TIM16 Alternate Function mapping (only for Value line devices)
  • GPIO_Remap_TIM17 : TIM17 Alternate Function mapping (only for Value line devices)
  • GPIO_Remap_CEC : CEC Alternate Function mapping (only for Value line devices)
  • GPIO_Remap_TIM1_DMA : TIM1 DMA requests mapping (only for Value line devices)
  • GPIO_Remap_TIM9 : TIM9 Alternate Function mapping (only for XL-density devices)
  • GPIO_Remap_TIM10 : TIM10 Alternate Function mapping (only for XL-density devices)
  • GPIO_Remap_TIM11 : TIM11 Alternate Function mapping (only for XL-density devices)
  • GPIO_Remap_TIM13 : TIM13 Alternate Function mapping (only for High density Value line and XL-density devices)
  • GPIO_Remap_TIM14 : TIM14 Alternate Function mapping (only for High density Value line and XL-density devices)
  • GPIO_Remap_FSMC_NADV : FSMC_NADV Alternate Function mapping (only for High density Value line and XL-density devices)
  • GPIO_Remap_TIM67_DAC_DMA : TIM6/TIM7 and DAC DMA requests remapping (only for High density Value line devices)
  • GPIO_Remap_TIM12 : TIM12 Alternate Function mapping (only for High density Value line devices)
  • GPIO_Remap_MISC : Miscellaneous Remap (DMA2 Channel5 Position and DAC Trigger remapping, only for High density Value line devices)
NewState,: new state of the port pin remapping. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 549 of file stm32f10x_gpio.c.

References AFIO, assert_param, DBGAFR_LOCATION_MASK, DBGAFR_NUMBITS_MASK, DBGAFR_POSITION_MASK, DBGAFR_SWJCFG_MASK, DISABLE, IS_FUNCTIONAL_STATE, IS_GPIO_REMAP, and LSB_MASK.

Referenced by CAN_Config(), GPIO_Configuration(), LCD_DeInit(), LCD_SPIConfig(), main(), OneNAND_Init(), SD_LowLevel_DeInit(), SD_LowLevel_Init(), STM_EVAL_COMInit(), and TIM5_ConfigForLSI().

uint16_t GPIO_ReadInputData ( GPIO_TypeDef * GPIOx )

Reads the specified GPIO input data port.

Parameters:
GPIOx,: where x can be (A..G) to select the GPIO peripheral.
Return values:
GPIO input data port value.

Definition at line 305 of file stm32f10x_gpio.c.

References assert_param, GPIO_TypeDef::IDR, and IS_GPIO_ALL_PERIPH.

Referenced by SD_Detect().

uint8_t GPIO_ReadInputDataBit | ( | GPIO_TypeDef * | GPIOx,
 |  | uint16_t | GPIO_Pin
 | ) |  |

Reads the specified input port pin.

Parameters:
GPIOx,: where x can be (A..G) to select the GPIO peripheral.
GPIO_Pin,: specifies the port bit to read. This parameter can be GPIO_Pin_x where x can be (0..15).
Return values:
The input port pin value.

Definition at line 281 of file stm32f10x_gpio.c.

References assert_param, Bit_RESET, Bit_SET, GPIO_TypeDef::IDR, IS_GET_GPIO_PIN, and IS_GPIO_ALL_PERIPH.

Referenced by NOR_GetStatus(), PhysicalAddressDiscovery(), SD_Detect(), and STM_EVAL_PBGetState().

uint16_t GPIO_ReadOutputData ( GPIO_TypeDef * GPIOx )

Reads the specified GPIO output data port.

Parameters:
GPIOx,: where x can be (A..G) to select the GPIO peripheral.
Return values:
GPIO output data port value.

Definition at line 343 of file stm32f10x_gpio.c.

References assert_param, IS_GPIO_ALL_PERIPH, and GPIO_TypeDef::ODR.

uint8_t GPIO_ReadOutputDataBit | ( | GPIO_TypeDef * | GPIOx,
 |  | uint16_t | GPIO_Pin
 | ) |  |

Reads the specified output data port bit.

Parameters:
GPIOx,: where x can be (A..G) to select the GPIO peripheral.
GPIO_Pin,: specifies the port bit to read. This parameter can be GPIO_Pin_x where x can be (0..15).
Return values:
The output port pin value.

Definition at line 320 of file stm32f10x_gpio.c.

References assert_param, Bit_RESET, Bit_SET, IS_GET_GPIO_PIN, IS_GPIO_ALL_PERIPH, and GPIO_TypeDef::ODR.

Referenced by main(), and TIM2_IRQHandler().

void GPIO_ResetBits | ( | GPIO_TypeDef * | GPIOx,
 |  | uint16_t | GPIO_Pin
 | ) |  |

Clears the selected data port bits.

Parameters:
GPIOx,: where x can be (A..G) to select the GPIO peripheral.
GPIO_Pin,: specifies the port bits to be written. This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
Return values:
None

Definition at line 374 of file stm32f10x_gpio.c.

References assert_param, GPIO_TypeDef::BRR, IS_GPIO_ALL_PERIPH, and IS_GPIO_PIN.

Referenced by EXTI15_10_IRQHandler(), EXTI9_5_IRQHandler(), and TIM2_IRQHandler().

void GPIO_SetBits | ( | GPIO_TypeDef * | GPIOx,
 |  | uint16_t | GPIO_Pin
 | ) |  |

Sets the selected data port bits.

Parameters:
GPIOx,: where x can be (A..G) to select the GPIO peripheral.
GPIO_Pin,: specifies the port bits to be written. This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
Return values:
None

Definition at line 358 of file stm32f10x_gpio.c.

References assert_param, GPIO_TypeDef::BSRR, IS_GPIO_ALL_PERIPH, and IS_GPIO_PIN.

Referenced by EXTI15_10_IRQHandler(), EXTI9_5_IRQHandler(), and main().

void GPIO_StructInit ( GPIO_InitTypeDef * GPIO_InitStruct )

Fills each GPIO_InitStruct member with its default value.

Parameters:
GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will be initialized.
Return values:
None

Definition at line 266 of file stm32f10x_gpio.c.

References GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_IN_FLOATING, GPIO_InitTypeDef::GPIO_Pin, GPIO_Pin_All, GPIO_InitTypeDef::GPIO_Speed, and GPIO_Speed_2MHz.

void GPIO_Write | ( | GPIO_TypeDef * | GPIOx,
 |  | uint16_t | PortVal
 | ) |  |

Writes data to the specified GPIO data port.

Parameters:
GPIOx,: where x can be (A..G) to select the GPIO peripheral.
PortVal,: specifies the value to be written to the port output data register.
Return values:
None

Definition at line 417 of file stm32f10x_gpio.c.

References assert_param, IS_GPIO_ALL_PERIPH, and GPIO_TypeDef::ODR.

void GPIO_WriteBit | ( | GPIO_TypeDef * | GPIOx,
 |  | uint16_t | GPIO_Pin,
 |  | BitAction | BitVal
 | ) |  |

Sets or clears the selected data port bit.

Parameters:
GPIOx,: where x can be (A..G) to select the GPIO peripheral.
GPIO_Pin,: specifies the port bit to be written. This parameter can be one of GPIO_Pin_x where x can be (0..15).
BitVal,: specifies the value to be written to the selected bit. This parameter can be one of the BitAction enum values:

  • Bit_RESET: to clear the port pin
  • Bit_SET: to set the port pin
Return values:
None

Definition at line 394 of file stm32f10x_gpio.c.

References assert_param, Bit_RESET, GPIO_TypeDef::BRR, GPIO_TypeDef::BSRR, IS_GET_GPIO_PIN, IS_GPIO_ALL_PERIPH, and IS_GPIO_BIT_ACTION.

Referenced by ADC1_2_IRQHandler(), LCD_CtrlLinesWrite(), main(), and TIM2_IRQHandler().


STM32F10x Standard Peripherals Firmware Library: GPIO_Private_TypesDefinitions

GPIO_Private_TypesDefinitions

GPIO


STM32F10x Standard Peripherals Firmware Library: GPIO_Private_Defines

Defines

GPIO_Private_Defines

GPIO

Defines

#define | AFIO_OFFSET (AFIO_BASE - PERIPH_BASE)
#define | DBGAFR_LOCATION_MASK ((uint32_t)0x00200000)
#define | DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000)
#define | DBGAFR_POSITION_MASK ((uint32_t)0x000F0000)
#define | DBGAFR_SWJCFG_MASK ((uint32_t)0xF0FFFFFF)
#define | EVCR_EVOE_BB (PERIPH_BB_BASE + (EVCR_OFFSET * 32) + (EVOE_BitNumber * 4))
#define | EVCR_OFFSET (AFIO_OFFSET + 0x00)
#define | EVCR_PORTPINCONFIG_MASK ((uint16_t)0xFF80)
#define | EVOE_BitNumber ((uint8_t)0x07)
#define | LSB_MASK ((uint16_t)0xFFFF)
#define | MAPR_MII_RMII_SEL_BB (PERIPH_BB_BASE + (MAPR_OFFSET * 32) + (MII_RMII_SEL_BitNumber * 4))
#define | MAPR_OFFSET (AFIO_OFFSET + 0x04)
#define | MII_RMII_SEL_BitNumber ((u8)0x17)

Define Documentation

#define AFIO_OFFSET (AFIO_BASE - PERIPH_BASE)

Definition at line 48 of file stm32f10x_gpio.c.

#define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000)

Definition at line 69 of file stm32f10x_gpio.c.

Referenced by GPIO_PinRemapConfig().

#define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000)

Definition at line 70 of file stm32f10x_gpio.c.

Referenced by GPIO_PinRemapConfig().

#define DBGAFR_POSITION_MASK ((uint32_t)0x000F0000)

Definition at line 67 of file stm32f10x_gpio.c.

Referenced by GPIO_PinRemapConfig().

#define DBGAFR_SWJCFG_MASK ((uint32_t)0xF0FFFFFF)

Definition at line 68 of file stm32f10x_gpio.c.

Referenced by GPIO_PinRemapConfig().

#define EVCR_EVOE_BB (PERIPH_BB_BASE + (EVCR_OFFSET * 32) + (EVOE_BitNumber * 4))

Definition at line 55 of file stm32f10x_gpio.c.

Referenced by GPIO_EventOutputCmd().

#define EVCR_OFFSET (AFIO_OFFSET + 0x00)

Definition at line 53 of file stm32f10x_gpio.c.

#define EVCR_PORTPINCONFIG_MASK ((uint16_t)0xFF80)

Definition at line 65 of file stm32f10x_gpio.c.

Referenced by GPIO_EventOutputConfig().

#define EVOE_BitNumber ((uint8_t)0x07)

Definition at line 54 of file stm32f10x_gpio.c.

#define LSB_MASK ((uint16_t)0xFFFF)

Definition at line 66 of file stm32f10x_gpio.c.

Referenced by GPIO_PinRemapConfig().

#define MAPR_MII_RMII_SEL_BB (PERIPH_BB_BASE + (MAPR_OFFSET * 32) + (MII_RMII_SEL_BitNumber * 4))

Definition at line 62 of file stm32f10x_gpio.c.

Referenced by GPIO_ETH_MediaInterfaceConfig().

#define MAPR_OFFSET (AFIO_OFFSET + 0x04)

Definition at line 60 of file stm32f10x_gpio.c.

#define MII_RMII_SEL_BitNumber ((u8)0x17)

Definition at line 61 of file stm32f10x_gpio.c.


STM32F10x Standard Peripherals Firmware Library: GPIO_Private_Macros

GPIO_Private_Macros

GPIO


STM32F10x Standard Peripherals Firmware Library: GPIO_Private_Variables

GPIO_Private_Variables

GPIO


STM32F10x Standard Peripherals Firmware Library: GPIO_Private_FunctionPrototypes

GPIO_Private_FunctionPrototypes

GPIO


STM32F10x Standard Peripherals Firmware Library: GPIO_Private_Functions

Functions

GPIO_Private_Functions

GPIO

Functions

void | GPIO_AFIODeInit (void)
Deinitializes the Alternate Functions (remap, event control and EXTI configuration) registers to their default reset values.
void | GPIO_DeInit (GPIO_TypeDef *GPIOx)
Deinitializes the GPIOx peripheral registers to their default reset values.
void | GPIO_ETH_MediaInterfaceConfig (uint32_t GPIO_ETH_MediaInterface)
Selects the Ethernet media interface.
void | GPIO_EventOutputCmd (FunctionalState NewState)
Enables or disables the Event Output.
void | GPIO_EventOutputConfig (uint8_t GPIO_PortSource, uint8_t GPIO_PinSource)
Selects the GPIO pin used as Event output.
void | GPIO_EXTILineConfig (uint8_t GPIO_PortSource, uint8_t GPIO_PinSource)
Selects the GPIO pin used as EXTI Line.
void | GPIO_Init (GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct)
Initializes the GPIOx peripheral according to the specified parameters in the GPIO_InitStruct.
void | GPIO_PinLockConfig (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Locks GPIO Pins configuration registers.
void | GPIO_PinRemapConfig (uint32_t GPIO_Remap, FunctionalState NewState)
Changes the mapping of the specified pin.
uint16_t | GPIO_ReadInputData (GPIO_TypeDef *GPIOx)
Reads the specified GPIO input data port.
uint8_t | GPIO_ReadInputDataBit (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Reads the specified input port pin.
uint16_t | GPIO_ReadOutputData (GPIO_TypeDef *GPIOx)
Reads the specified GPIO output data port.
uint8_t | GPIO_ReadOutputDataBit (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Reads the specified output data port bit.
void | GPIO_ResetBits (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Clears the selected data port bits.
void | GPIO_SetBits (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Sets the selected data port bits.
void | GPIO_StructInit (GPIO_InitTypeDef *GPIO_InitStruct)
Fills each GPIO_InitStruct member with its default value.
void | GPIO_Write (GPIO_TypeDef *GPIOx, uint16_t PortVal)
Writes data to the specified GPIO data port.
void | GPIO_WriteBit (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
Sets or clears the selected data port bit.

Function Documentation

void GPIO_AFIODeInit ( void )

Deinitializes the Alternate Functions (remap, event control and EXTI configuration) registers to their default reset values.

Parameters:
None
Return values:
None

Definition at line 159 of file stm32f10x_gpio.c.

References DISABLE, ENABLE, RCC_APB2Periph_AFIO, and RCC_APB2PeriphResetCmd().

void GPIO_DeInit ( GPIO_TypeDef * GPIOx )

Deinitializes the GPIOx peripheral registers to their default reset values.

Parameters:
GPIOx,: where x can be (A..G) to select the GPIO peripheral.
Return values:
None

Definition at line 108 of file stm32f10x_gpio.c.

References assert_param, DISABLE, ENABLE, GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, IS_GPIO_ALL_PERIPH, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB, RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE, RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, and RCC_APB2PeriphResetCmd().

void GPIO_ETH_MediaInterfaceConfig ( uint32_t GPIO_ETH_MediaInterface )

Selects the Ethernet media interface.

Note:
This function applies only to STM32 Connectivity line devices.
Parameters:
GPIO_ETH_MediaInterface,: specifies the Media Interface mode. This parameter can be one of the following values:

  • GPIO_ETH_MediaInterface_MII: MII mode
  • GPIO_ETH_MediaInterface_RMII: RMII mode
Return values:
None

Definition at line 630 of file stm32f10x_gpio.c.

References assert_param, IS_GPIO_ETH_MEDIA_INTERFACE, and MAPR_MII_RMII_SEL_BB.

void GPIO_EventOutputCmd ( FunctionalState NewState )

Enables or disables the Event Output.

Parameters:
NewState,: new state of the Event output. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 483 of file stm32f10x_gpio.c.

References assert_param, EVCR_EVOE_BB, and IS_FUNCTIONAL_STATE.

void GPIO_EventOutputConfig | ( | uint8_t | GPIO_PortSource,
 |  | uint8_t | GPIO_PinSource
 | ) |  |

Selects the GPIO pin used as Event output.

Parameters:
GPIO_PortSource,: selects the GPIO port to be used as source for Event output. This parameter can be GPIO_PortSourceGPIOx where x can be (A..E).
GPIO_PinSource,: specifies the pin for the Event output. This parameter can be GPIO_PinSourcex where x can be (0..15).
Return values:
None

Definition at line 462 of file stm32f10x_gpio.c.

References AFIO, assert_param, EVCR_PORTPINCONFIG_MASK, IS_GPIO_EVENTOUT_PORT_SOURCE, and IS_GPIO_PIN_SOURCE.

void GPIO_EXTILineConfig | ( | uint8_t | GPIO_PortSource,
 |  | uint8_t | GPIO_PinSource
 | ) |  |

Selects the GPIO pin used as EXTI Line.

Parameters:
GPIO_PortSource,: selects the GPIO port to be used as source for EXTI lines. This parameter can be GPIO_PortSourceGPIOx where x can be (A..G).
GPIO_PinSource,: specifies the EXTI line to be configured. This parameter can be GPIO_PinSourcex where x can be (0..15).
Return values:
None

Definition at line 609 of file stm32f10x_gpio.c.

References AFIO, assert_param, IS_GPIO_EXTI_PORT_SOURCE, and IS_GPIO_PIN_SOURCE.

Referenced by EXTI0_Config(), EXTI9_5_Config(), EXTI_Configuration(), HDMI_CEC_CommandCallBack(), IOE_EXTI_Config(), IOE_GPIO_Config(), and STM_EVAL_PBInit().

void GPIO_Init | ( | GPIO_TypeDef * | GPIOx,
 |  | GPIO_InitTypeDef * | GPIO_InitStruct
 | ) |  |

Initializes the GPIOx peripheral according to the specified parameters in the GPIO_InitStruct.

Parameters:
GPIOx,: where x can be (A..G) to select the GPIO peripheral.
GPIO_InitStruct,: pointer to a GPIO_InitTypeDef structure that contains the configuration information for the specified GPIO peripheral.
Return values:
None

Definition at line 173 of file stm32f10x_gpio.c.

References assert_param, GPIO_TypeDef::BRR, GPIO_TypeDef::BSRR, GPIO_TypeDef::CRH, GPIO_TypeDef::CRL, GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_IPD, GPIO_Mode_IPU, GPIO_InitTypeDef::GPIO_Pin, GPIO_InitTypeDef::GPIO_Speed, IS_GPIO_ALL_PERIPH, IS_GPIO_MODE, IS_GPIO_PIN, and IS_GPIO_SPEED.

Referenced by CAN_Config(), EXTI0_Config(), EXTI9_5_Config(), GPIO_Configuration(), HDMI_CEC_Init(), IOE_EXTI_Config(), IOE_GPIO_Config(), LCD_CtrlLinesConfig(), LCD_DeInit(), LCD_GPIOConfig(), LCD_SPIConfig(), LM75_LowLevel_DeInit(), LM75_LowLevel_Init(), main(), NAND_Init(), NOR_Init(), OneNAND_Init(), SD_LowLevel_DeInit(), SD_LowLevel_Init(), sEE_LowLevel_DeInit(), sEE_LowLevel_Init(), sFLASH_LowLevel_DeInit(), sFLASH_LowLevel_Init(), SRAM_Init(), STM32L152_LCD_DeInit(), STM_EVAL_COMInit(), STM_EVAL_LEDInit(), and STM_EVAL_PBInit().

void GPIO_PinLockConfig | ( | GPIO_TypeDef * | GPIOx,
 |  | uint16_t | GPIO_Pin
 | ) |  |

Locks GPIO Pins configuration registers.

Parameters:
GPIOx,: where x can be (A..G) to select the GPIO peripheral.
GPIO_Pin,: specifies the port bit to be written. This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
Return values:
None

Definition at line 432 of file stm32f10x_gpio.c.

References assert_param, IS_GPIO_ALL_PERIPH, IS_GPIO_PIN, and GPIO_TypeDef::LCKR.

void GPIO_PinRemapConfig | ( | uint32_t | GPIO_Remap,
 |  | FunctionalState | NewState
 | ) |  |

Changes the mapping of the specified pin.

Parameters:
GPIO_Remap,: selects the pin to remap. This parameter can be one of the following values:

  • GPIO_Remap_SPI1 : SPI1 Alternate Function mapping
  • GPIO_Remap_I2C1 : I2C1 Alternate Function mapping
  • GPIO_Remap_USART1 : USART1 Alternate Function mapping
  • GPIO_Remap_USART2 : USART2 Alternate Function mapping
  • GPIO_PartialRemap_USART3 : USART3 Partial Alternate Function mapping
  • GPIO_FullRemap_USART3 : USART3 Full Alternate Function mapping
  • GPIO_PartialRemap_TIM1 : TIM1 Partial Alternate Function mapping
  • GPIO_FullRemap_TIM1 : TIM1 Full Alternate Function mapping
  • GPIO_PartialRemap1_TIM2 : TIM2 Partial1 Alternate Function mapping
  • GPIO_PartialRemap2_TIM2 : TIM2 Partial2 Alternate Function mapping
  • GPIO_FullRemap_TIM2 : TIM2 Full Alternate Function mapping
  • GPIO_PartialRemap_TIM3 : TIM3 Partial Alternate Function mapping
  • GPIO_FullRemap_TIM3 : TIM3 Full Alternate Function mapping
  • GPIO_Remap_TIM4 : TIM4 Alternate Function mapping
  • GPIO_Remap1_CAN1 : CAN1 Alternate Function mapping
  • GPIO_Remap2_CAN1 : CAN1 Alternate Function mapping
  • GPIO_Remap_PD01 : PD01 Alternate Function mapping
  • GPIO_Remap_TIM5CH4_LSI : LSI connected to TIM5 Channel4 input capture for calibration
  • GPIO_Remap_ADC1_ETRGINJ : ADC1 External Trigger Injected Conversion remapping
  • GPIO_Remap_ADC1_ETRGREG : ADC1 External Trigger Regular Conversion remapping
  • GPIO_Remap_ADC2_ETRGINJ : ADC2 External Trigger Injected Conversion remapping
  • GPIO_Remap_ADC2_ETRGREG : ADC2 External Trigger Regular Conversion remapping
  • GPIO_Remap_ETH : Ethernet remapping (only for Connectivity line devices)
  • GPIO_Remap_CAN2 : CAN2 remapping (only for Connectivity line devices)
  • GPIO_Remap_SWJ_NoJTRST : Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST
  • GPIO_Remap_SWJ_JTAGDisable : JTAG-DP Disabled and SW-DP Enabled
  • GPIO_Remap_SWJ_Disable : Full SWJ Disabled (JTAG-DP + SW-DP)
  • GPIO_Remap_SPI3 : SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices) When the SPI3/I2S3 is remapped using this function, the SWJ is configured to Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST.
  • GPIO_Remap_TIM2ITR1_PTP_SOF : Ethernet PTP output or USB OTG SOF (Start of Frame) connected to TIM2 Internal Trigger 1 for calibration (only for Connectivity line devices) If the GPIO_Remap_TIM2ITR1_PTP_SOF is enabled the TIM2 ITR1 is connected to Ethernet PTP output. When Reset TIM2 ITR1 is connected to USB OTG SOF output.
  • GPIO_Remap_PTP_PPS : Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices)
  • GPIO_Remap_TIM15 : TIM15 Alternate Function mapping (only for Value line devices)
  • GPIO_Remap_TIM16 : TIM16 Alternate Function mapping (only for Value line devices)
  • GPIO_Remap_TIM17 : TIM17 Alternate Function mapping (only for Value line devices)
  • GPIO_Remap_CEC : CEC Alternate Function mapping (only for Value line devices)
  • GPIO_Remap_TIM1_DMA : TIM1 DMA requests mapping (only for Value line devices)
  • GPIO_Remap_TIM9 : TIM9 Alternate Function mapping (only for XL-density devices)
  • GPIO_Remap_TIM10 : TIM10 Alternate Function mapping (only for XL-density devices)
  • GPIO_Remap_TIM11 : TIM11 Alternate Function mapping (only for XL-density devices)
  • GPIO_Remap_TIM13 : TIM13 Alternate Function mapping (only for High density Value line and XL-density devices)
  • GPIO_Remap_TIM14 : TIM14 Alternate Function mapping (only for High density Value line and XL-density devices)
  • GPIO_Remap_FSMC_NADV : FSMC_NADV Alternate Function mapping (only for High density Value line and XL-density devices)
  • GPIO_Remap_TIM67_DAC_DMA : TIM6/TIM7 and DAC DMA requests remapping (only for High density Value line devices)
  • GPIO_Remap_TIM12 : TIM12 Alternate Function mapping (only for High density Value line devices)
  • GPIO_Remap_MISC : Miscellaneous Remap (DMA2 Channel5 Position and DAC Trigger remapping, only for High density Value line devices)
NewState,: new state of the port pin remapping. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 549 of file stm32f10x_gpio.c.

References AFIO, assert_param, DBGAFR_LOCATION_MASK, DBGAFR_NUMBITS_MASK, DBGAFR_POSITION_MASK, DBGAFR_SWJCFG_MASK, DISABLE, IS_FUNCTIONAL_STATE, IS_GPIO_REMAP, and LSB_MASK.

Referenced by CAN_Config(), GPIO_Configuration(), LCD_DeInit(), LCD_SPIConfig(), main(), OneNAND_Init(), SD_LowLevel_DeInit(), SD_LowLevel_Init(), STM_EVAL_COMInit(), and TIM5_ConfigForLSI().

uint16_t GPIO_ReadInputData ( GPIO_TypeDef * GPIOx )

Reads the specified GPIO input data port.

Parameters:
GPIOx,: where x can be (A..G) to select the GPIO peripheral.
Return values:
GPIO input data port value.

Definition at line 305 of file stm32f10x_gpio.c.

References assert_param, GPIO_TypeDef::IDR, and IS_GPIO_ALL_PERIPH.

Referenced by SD_Detect().

uint8_t GPIO_ReadInputDataBit | ( | GPIO_TypeDef * | GPIOx,
 |  | uint16_t | GPIO_Pin
 | ) |  |

Reads the specified input port pin.

Parameters:
GPIOx,: where x can be (A..G) to select the GPIO peripheral.
GPIO_Pin,: specifies the port bit to read. This parameter can be GPIO_Pin_x where x can be (0..15).
Return values:
The input port pin value.

Definition at line 281 of file stm32f10x_gpio.c.

References assert_param, Bit_RESET, Bit_SET, GPIO_TypeDef::IDR, IS_GET_GPIO_PIN, and IS_GPIO_ALL_PERIPH.

Referenced by NOR_GetStatus(), PhysicalAddressDiscovery(), SD_Detect(), and STM_EVAL_PBGetState().

uint16_t GPIO_ReadOutputData ( GPIO_TypeDef * GPIOx )

Reads the specified GPIO output data port.

Parameters:
GPIOx,: where x can be (A..G) to select the GPIO peripheral.
Return values:
GPIO output data port value.

Definition at line 343 of file stm32f10x_gpio.c.

References assert_param, IS_GPIO_ALL_PERIPH, and GPIO_TypeDef::ODR.

uint8_t GPIO_ReadOutputDataBit | ( | GPIO_TypeDef * | GPIOx,
 |  | uint16_t | GPIO_Pin
 | ) |  |

Reads the specified output data port bit.

Parameters:
GPIOx,: where x can be (A..G) to select the GPIO peripheral.
GPIO_Pin,: specifies the port bit to read. This parameter can be GPIO_Pin_x where x can be (0..15).
Return values:
The output port pin value.

Definition at line 320 of file stm32f10x_gpio.c.

References assert_param, Bit_RESET, Bit_SET, IS_GET_GPIO_PIN, IS_GPIO_ALL_PERIPH, and GPIO_TypeDef::ODR.

Referenced by main(), and TIM2_IRQHandler().

void GPIO_ResetBits | ( | GPIO_TypeDef * | GPIOx,
 |  | uint16_t | GPIO_Pin
 | ) |  |

Clears the selected data port bits.

Parameters:
GPIOx,: where x can be (A..G) to select the GPIO peripheral.
GPIO_Pin,: specifies the port bits to be written. This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
Return values:
None

Definition at line 374 of file stm32f10x_gpio.c.

References assert_param, GPIO_TypeDef::BRR, IS_GPIO_ALL_PERIPH, and IS_GPIO_PIN.

Referenced by EXTI15_10_IRQHandler(), EXTI9_5_IRQHandler(), and TIM2_IRQHandler().

void GPIO_SetBits | ( | GPIO_TypeDef * | GPIOx,
 |  | uint16_t | GPIO_Pin
 | ) |  |

Sets the selected data port bits.

Parameters:
GPIOx,: where x can be (A..G) to select the GPIO peripheral.
GPIO_Pin,: specifies the port bits to be written. This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
Return values:
None

Definition at line 358 of file stm32f10x_gpio.c.

References assert_param, GPIO_TypeDef::BSRR, IS_GPIO_ALL_PERIPH, and IS_GPIO_PIN.

Referenced by EXTI15_10_IRQHandler(), EXTI9_5_IRQHandler(), and main().

void GPIO_StructInit ( GPIO_InitTypeDef * GPIO_InitStruct )

Fills each GPIO_InitStruct member with its default value.

Parameters:
GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will be initialized.
Return values:
None

Definition at line 266 of file stm32f10x_gpio.c.

References GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_IN_FLOATING, GPIO_InitTypeDef::GPIO_Pin, GPIO_Pin_All, GPIO_InitTypeDef::GPIO_Speed, and GPIO_Speed_2MHz.

void GPIO_Write | ( | GPIO_TypeDef * | GPIOx,
 |  | uint16_t | PortVal
 | ) |  |

Writes data to the specified GPIO data port.

Parameters:
GPIOx,: where x can be (A..G) to select the GPIO peripheral.
PortVal,: specifies the value to be written to the port output data register.
Return values:
None

Definition at line 417 of file stm32f10x_gpio.c.

References assert_param, IS_GPIO_ALL_PERIPH, and GPIO_TypeDef::ODR.

void GPIO_WriteBit | ( | GPIO_TypeDef * | GPIOx,
 |  | uint16_t | GPIO_Pin,
 |  | BitAction | BitVal
 | ) |  |

Sets or clears the selected data port bit.

Parameters:
GPIOx,: where x can be (A..G) to select the GPIO peripheral.
GPIO_Pin,: specifies the port bit to be written. This parameter can be one of GPIO_Pin_x where x can be (0..15).
BitVal,: specifies the value to be written to the selected bit. This parameter can be one of the BitAction enum values:

  • Bit_RESET: to clear the port pin
  • Bit_SET: to set the port pin
Return values:
None

Definition at line 394 of file stm32f10x_gpio.c.

References assert_param, Bit_RESET, GPIO_TypeDef::BRR, GPIO_TypeDef::BSRR, IS_GET_GPIO_PIN, IS_GPIO_ALL_PERIPH, and IS_GPIO_BIT_ACTION.

Referenced by ADC1_2_IRQHandler(), LCD_CtrlLinesWrite(), main(), and TIM2_IRQHandler().


STM32F10x Standard Peripherals Firmware Library: I2C_InitTypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

I2C_InitTypeDef Struct Reference
I2C_Exported_Types

I2C Init structure definition. More...

#include <stm32f10x_i2c.h>

Data Fields

uint16_t | I2C_Ack
uint16_t | I2C_AcknowledgedAddress
uint32_t | I2C_ClockSpeed
uint16_t | I2C_DutyCycle
uint16_t | I2C_Mode
uint16_t | I2C_OwnAddress1

Detailed Description

I2C Init structure definition.

Definition at line 50 of file stm32f10x_i2c.h.

Field Documentation

uint16_t I2C_InitTypeDef::I2C_Ack

Enables or disables the acknowledgement. This parameter can be a value of I2C_acknowledgement

Definition at line 64 of file stm32f10x_i2c.h.

Referenced by HDMI_CEC_Init(), I2C_Init(), I2C_StructInit(), IOE_I2C_Config(), LM75_Init(), main(), and sEE_Init().

uint16_t I2C_InitTypeDef::I2C_AcknowledgedAddress

Specifies if 7-bit or 10-bit address is acknowledged. This parameter can be a value of I2C_acknowledged_address

Definition at line 67 of file stm32f10x_i2c.h.

Referenced by HDMI_CEC_Init(), I2C_Init(), I2C_StructInit(), IOE_I2C_Config(), LM75_Init(), main(), and sEE_Init().

uint32_t I2C_InitTypeDef::I2C_ClockSpeed

Specifies the clock frequency. This parameter must be set to a value lower than 400kHz

Definition at line 52 of file stm32f10x_i2c.h.

Referenced by HDMI_CEC_Init(), I2C_Init(), I2C_StructInit(), IOE_I2C_Config(), LM75_Init(), main(), and sEE_Init().

uint16_t I2C_InitTypeDef::I2C_DutyCycle

Specifies the I2C fast mode duty cycle. This parameter can be a value of I2C_duty_cycle_in_fast_mode

Definition at line 58 of file stm32f10x_i2c.h.

Referenced by HDMI_CEC_Init(), I2C_Init(), I2C_StructInit(), IOE_I2C_Config(), LM75_Init(), main(), and sEE_Init().

uint16_t I2C_InitTypeDef::I2C_Mode

Specifies the I2C mode. This parameter can be a value of I2C_mode

Definition at line 55 of file stm32f10x_i2c.h.

Referenced by HDMI_CEC_Init(), I2C_Init(), I2C_StructInit(), IOE_I2C_Config(), LM75_Init(), main(), and sEE_Init().

uint16_t I2C_InitTypeDef::I2C_OwnAddress1

Specifies the first device own address. This parameter can be a 7-bit or 10-bit address.

Definition at line 61 of file stm32f10x_i2c.h.

Referenced by HDMI_CEC_Init(), I2C_Init(), I2C_StructInit(), IOE_I2C_Config(), LM75_Init(), main(), and sEE_Init().

The documentation for this struct was generated from the following file:
  • stm32f10x_i2c.h


STM32F10x Standard Peripherals Firmware Library: I2C_mode

Defines

I2C_mode

I2C_Exported_Constants

Defines

#define | I2C_Mode_I2C ((uint16_t)0x0000)
#define | I2C_Mode_SMBusDevice ((uint16_t)0x0002)
#define | I2C_Mode_SMBusHost ((uint16_t)0x000A)
#define | IS_I2C_MODE(MODE)

Define Documentation

#define I2C_Mode_I2C ((uint16_t)0x0000)

Definition at line 86 of file stm32f10x_i2c.h.

Referenced by HDMI_CEC_Init(), I2C_StructInit(), IOE_I2C_Config(), main(), and sEE_Init().

#define I2C_Mode_SMBusDevice ((uint16_t)0x0002)

Definition at line 87 of file stm32f10x_i2c.h.

#define I2C_Mode_SMBusHost ((uint16_t)0x000A)

Definition at line 88 of file stm32f10x_i2c.h.

Referenced by LM75_Init().

#define IS_I2C_MODE ( MODE )
Value:
(((MODE) == I2C_Mode_I2C) || \
                           ((MODE) == I2C_Mode_SMBusDevice) || \
                           ((MODE) == I2C_Mode_SMBusHost))

Definition at line 89 of file stm32f10x_i2c.h.

Referenced by I2C_Init().


STM32F10x Standard Peripherals Firmware Library: I2C_duty_cycle_in_fast_mode

Defines

I2C_duty_cycle_in_fast_mode

I2C_Exported_Constants

Defines

#define | I2C_DutyCycle_16_9 ((uint16_t)0x4000)
#define | I2C_DutyCycle_2 ((uint16_t)0xBFFF)
#define | IS_I2C_DUTY_CYCLE(CYCLE)

Define Documentation

#define I2C_DutyCycle_16_9 ((uint16_t)0x4000)

I2C fast mode Tlow/Thigh = 16/9

Definition at line 100 of file stm32f10x_i2c.h.

Referenced by I2C_FastModeDutyCycleConfig(), and I2C_Init().

#define I2C_DutyCycle_2 ((uint16_t)0xBFFF)

I2C fast mode Tlow/Thigh = 2

Definition at line 101 of file stm32f10x_i2c.h.

Referenced by HDMI_CEC_Init(), I2C_FastModeDutyCycleConfig(), I2C_Init(), I2C_StructInit(), IOE_I2C_Config(), LM75_Init(), main(), and sEE_Init().

#define IS_I2C_DUTY_CYCLE ( CYCLE )
Value:
(((CYCLE) == I2C_DutyCycle_16_9) || \
                                  ((CYCLE) == I2C_DutyCycle_2))

Definition at line 102 of file stm32f10x_i2c.h.

Referenced by I2C_FastModeDutyCycleConfig(), and I2C_Init().


STM32F10x Standard Peripherals Firmware Library: I2C_acknowledgement

Defines

I2C_acknowledgement

I2C_Exported_Constants

Defines

#define | I2C_Ack_Disable ((uint16_t)0x0000)
#define | I2C_Ack_Enable ((uint16_t)0x0400)
#define | IS_I2C_ACK_STATE(STATE)

Define Documentation

#define I2C_Ack_Disable ((uint16_t)0x0000)

Definition at line 113 of file stm32f10x_i2c.h.

Referenced by I2C_StructInit().

#define I2C_Ack_Enable ((uint16_t)0x0400)

Definition at line 112 of file stm32f10x_i2c.h.

Referenced by HDMI_CEC_Init(), IOE_I2C_Config(), LM75_Init(), main(), and sEE_Init().

#define IS_I2C_ACK_STATE ( STATE )
Value:
(((STATE) == I2C_Ack_Enable) || \
                                 ((STATE) == I2C_Ack_Disable))

Definition at line 114 of file stm32f10x_i2c.h.

Referenced by I2C_Init().


STM32F10x Standard Peripherals Firmware Library: I2C_transfer_direction

Defines

I2C_transfer_direction

I2C_Exported_Constants

Defines

#define | I2C_Direction_Receiver ((uint8_t)0x01)
#define | I2C_Direction_Transmitter ((uint8_t)0x00)
#define | IS_I2C_DIRECTION(DIRECTION)

Define Documentation

#define I2C_Direction_Receiver ((uint8_t)0x01)

Definition at line 125 of file stm32f10x_i2c.h.

Referenced by I2C_ReadDataBuffer(), I2C_ReadDeviceRegister(), LM75_ReadConfReg(), LM75_ReadReg(), LM75_ReadTemp(), LM75_ShutDown(), PhysicalAddressDiscovery(), and sEE_ReadBuffer().

#define I2C_Direction_Transmitter ((uint8_t)0x00)

Definition at line 124 of file stm32f10x_i2c.h.

Referenced by I2C_ReadDataBuffer(), I2C_ReadDeviceRegister(), I2C_Send7bitAddress(), I2C_WriteDeviceRegister(), LM75_GetStatus(), LM75_ReadConfReg(), LM75_ReadReg(), LM75_ReadTemp(), LM75_ShutDown(), LM75_WriteConfReg(), LM75_WriteReg(), main(), PhysicalAddressDiscovery(), sEE_ReadBuffer(), sEE_WaitEepromStandbyState(), and sEE_WritePage().

#define IS_I2C_DIRECTION ( DIRECTION )
Value:
(((DIRECTION) == I2C_Direction_Transmitter) || \
                                     ((DIRECTION) == I2C_Direction_Receiver))

Definition at line 126 of file stm32f10x_i2c.h.

Referenced by I2C_Send7bitAddress().


STM32F10x Standard Peripherals Firmware Library: I2C_acknowledged_address

Defines

I2C_acknowledged_address

I2C_Exported_Constants

Defines

#define | I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000)
#define | I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000)
#define | IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS)

Define Documentation

#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000)

Definition at line 137 of file stm32f10x_i2c.h.

#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000)

Definition at line 136 of file stm32f10x_i2c.h.

Referenced by HDMI_CEC_Init(), I2C_StructInit(), IOE_I2C_Config(), LM75_Init(), main(), and sEE_Init().

#define IS_I2C_ACKNOWLEDGE_ADDRESS ( ADDRESS )
Value:
(((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \
                                             ((ADDRESS) == I2C_AcknowledgedAddress_10bit))

Definition at line 138 of file stm32f10x_i2c.h.

Referenced by I2C_Init().


STM32F10x Standard Peripherals Firmware Library: I2C_registers

Defines

I2C_registers

I2C_Exported_Constants

Defines

#define | I2C_Register_CCR ((uint8_t)0x1C)
#define | I2C_Register_CR1 ((uint8_t)0x00)
#define | I2C_Register_CR2 ((uint8_t)0x04)
#define | I2C_Register_DR ((uint8_t)0x10)
#define | I2C_Register_OAR1 ((uint8_t)0x08)
#define | I2C_Register_OAR2 ((uint8_t)0x0C)
#define | I2C_Register_SR1 ((uint8_t)0x14)
#define | I2C_Register_SR2 ((uint8_t)0x18)
#define | I2C_Register_TRISE ((uint8_t)0x20)
#define | IS_I2C_REGISTER(REGISTER)

Define Documentation

#define I2C_Register_CCR ((uint8_t)0x1C)

Definition at line 155 of file stm32f10x_i2c.h.

#define I2C_Register_CR1 ((uint8_t)0x00)

Definition at line 148 of file stm32f10x_i2c.h.

#define I2C_Register_CR2 ((uint8_t)0x04)

Definition at line 149 of file stm32f10x_i2c.h.

#define I2C_Register_DR ((uint8_t)0x10)

Definition at line 152 of file stm32f10x_i2c.h.

#define I2C_Register_OAR1 ((uint8_t)0x08)

Definition at line 150 of file stm32f10x_i2c.h.

#define I2C_Register_OAR2 ((uint8_t)0x0C)

Definition at line 151 of file stm32f10x_i2c.h.

#define I2C_Register_SR1 ((uint8_t)0x14)

Definition at line 153 of file stm32f10x_i2c.h.

#define I2C_Register_SR2 ((uint8_t)0x18)

Definition at line 154 of file stm32f10x_i2c.h.

#define I2C_Register_TRISE ((uint8_t)0x20)

Definition at line 156 of file stm32f10x_i2c.h.

#define IS_I2C_REGISTER ( REGISTER )
Value:
(((REGISTER) == I2C_Register_CR1) || \
                                   ((REGISTER) == I2C_Register_CR2) || \
                                   ((REGISTER) == I2C_Register_OAR1) || \
                                   ((REGISTER) == I2C_Register_OAR2) || \
                                   ((REGISTER) == I2C_Register_DR) || \
                                   ((REGISTER) == I2C_Register_SR1) || \
                                   ((REGISTER) == I2C_Register_SR2) || \
                                   ((REGISTER) == I2C_Register_CCR) || \
                                   ((REGISTER) == I2C_Register_TRISE))

Definition at line 157 of file stm32f10x_i2c.h.

Referenced by I2C_ReadRegister().


STM32F10x Standard Peripherals Firmware Library: I2C_SMBus_alert_pin_level

Defines

I2C_SMBus_alert_pin_level

I2C_Exported_Constants

Defines

#define | I2C_SMBusAlert_High ((uint16_t)0xDFFF)
#define | I2C_SMBusAlert_Low ((uint16_t)0x2000)
#define | IS_I2C_SMBUS_ALERT(ALERT)

Define Documentation

#define I2C_SMBusAlert_High ((uint16_t)0xDFFF)

Definition at line 175 of file stm32f10x_i2c.h.

Referenced by I2C_SMBusAlertConfig().

#define I2C_SMBusAlert_Low ((uint16_t)0x2000)

Definition at line 174 of file stm32f10x_i2c.h.

Referenced by I2C_SMBusAlertConfig().

#define IS_I2C_SMBUS_ALERT ( ALERT )
Value:
(((ALERT) == I2C_SMBusAlert_Low) || \
                                   ((ALERT) == I2C_SMBusAlert_High))

Definition at line 176 of file stm32f10x_i2c.h.

Referenced by I2C_SMBusAlertConfig().


STM32F10x Standard Peripherals Firmware Library: I2C_PEC_position

Defines

I2C_PEC_position

I2C_Exported_Constants

Defines

#define | I2C_PECPosition_Current ((uint16_t)0xF7FF)
#define | I2C_PECPosition_Next ((uint16_t)0x0800)
#define | IS_I2C_PEC_POSITION(POSITION)

Define Documentation

#define I2C_PECPosition_Current ((uint16_t)0xF7FF)

Definition at line 187 of file stm32f10x_i2c.h.

Referenced by I2C_PECPositionConfig().

#define I2C_PECPosition_Next ((uint16_t)0x0800)

Definition at line 186 of file stm32f10x_i2c.h.

Referenced by I2C_PECPositionConfig().

#define IS_I2C_PEC_POSITION ( POSITION )
Value:
(((POSITION) == I2C_PECPosition_Next) || \
                                       ((POSITION) == I2C_PECPosition_Current))

Definition at line 188 of file stm32f10x_i2c.h.

Referenced by I2C_PECPositionConfig().


STM32F10x Standard Peripherals Firmware Library: I2C_NCAK_position

Defines

I2C_NCAK_position

I2C_Exported_Constants

Defines

#define | I2C_NACKPosition_Current ((uint16_t)0xF7FF)
#define | I2C_NACKPosition_Next ((uint16_t)0x0800)
#define | IS_I2C_NACK_POSITION(POSITION)

Define Documentation

#define I2C_NACKPosition_Current ((uint16_t)0xF7FF)

Definition at line 199 of file stm32f10x_i2c.h.

Referenced by I2C_NACKPositionConfig().

#define I2C_NACKPosition_Next ((uint16_t)0x0800)

Definition at line 198 of file stm32f10x_i2c.h.

Referenced by I2C_NACKPositionConfig().

#define IS_I2C_NACK_POSITION ( POSITION )
Value:
(((POSITION) == I2C_NACKPosition_Next) || \
                                         ((POSITION) == I2C_NACKPosition_Current))

Definition at line 200 of file stm32f10x_i2c.h.

Referenced by I2C_NACKPositionConfig().


STM32F10x Standard Peripherals Firmware Library: I2C_interrupts_definition

Defines

I2C_interrupts_definition

I2C_Exported_Constants

Defines

#define | I2C_IT_ADD10 ((uint32_t)0x02000008)
#define | I2C_IT_ADDR ((uint32_t)0x02000002)
#define | I2C_IT_AF ((uint32_t)0x01000400)
#define | I2C_IT_ARLO ((uint32_t)0x01000200)
#define | I2C_IT_BERR ((uint32_t)0x01000100)
#define | I2C_IT_BTF ((uint32_t)0x02000004)
#define | I2C_IT_BUF ((uint16_t)0x0400)
#define | I2C_IT_ERR ((uint16_t)0x0100)
#define | I2C_IT_EVT ((uint16_t)0x0200)
#define | I2C_IT_OVR ((uint32_t)0x01000800)
#define | I2C_IT_PECERR ((uint32_t)0x01001000)
#define | I2C_IT_RXNE ((uint32_t)0x06000040)
#define | I2C_IT_SB ((uint32_t)0x02000001)
#define | I2C_IT_SMBALERT ((uint32_t)0x01008000)
#define | I2C_IT_STOPF ((uint32_t)0x02000010)
#define | I2C_IT_TIMEOUT ((uint32_t)0x01004000)
#define | I2C_IT_TXE ((uint32_t)0x06000080)
#define | IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00))
#define | IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00))
#define | IS_I2C_GET_IT(IT)

Define Documentation

#define I2C_IT_ADD10 ((uint32_t)0x02000008)

Definition at line 232 of file stm32f10x_i2c.h.

#define I2C_IT_ADDR ((uint32_t)0x02000002)

Definition at line 234 of file stm32f10x_i2c.h.

#define I2C_IT_AF ((uint32_t)0x01000400)

Definition at line 226 of file stm32f10x_i2c.h.

Referenced by I2C1_ER_IRQHandler().

#define I2C_IT_ARLO ((uint32_t)0x01000200)

Definition at line 227 of file stm32f10x_i2c.h.

Referenced by I2C1_ER_IRQHandler().

#define I2C_IT_BERR ((uint32_t)0x01000100)

Definition at line 228 of file stm32f10x_i2c.h.

Referenced by I2C1_ER_IRQHandler().

#define I2C_IT_BTF ((uint32_t)0x02000004)

Definition at line 233 of file stm32f10x_i2c.h.

#define I2C_IT_BUF ((uint16_t)0x0400)

Definition at line 210 of file stm32f10x_i2c.h.

#define I2C_IT_ERR ((uint16_t)0x0100)

Definition at line 212 of file stm32f10x_i2c.h.

Referenced by LM75_Init().

#define I2C_IT_EVT ((uint16_t)0x0200)

Definition at line 211 of file stm32f10x_i2c.h.

#define I2C_IT_OVR ((uint32_t)0x01000800)

Definition at line 225 of file stm32f10x_i2c.h.

Referenced by I2C1_ER_IRQHandler().

#define I2C_IT_PECERR ((uint32_t)0x01001000)

Definition at line 224 of file stm32f10x_i2c.h.

Referenced by I2C1_ER_IRQHandler().

#define I2C_IT_RXNE ((uint32_t)0x06000040)

Definition at line 230 of file stm32f10x_i2c.h.

#define I2C_IT_SB ((uint32_t)0x02000001)

Definition at line 235 of file stm32f10x_i2c.h.

#define I2C_IT_SMBALERT ((uint32_t)0x01008000)

Definition at line 222 of file stm32f10x_i2c.h.

Referenced by I2C1_ER_IRQHandler(), and main().

#define I2C_IT_STOPF ((uint32_t)0x02000010)

Definition at line 231 of file stm32f10x_i2c.h.

#define I2C_IT_TIMEOUT ((uint32_t)0x01004000)

Definition at line 223 of file stm32f10x_i2c.h.

Referenced by I2C1_ER_IRQHandler().

#define I2C_IT_TXE ((uint32_t)0x06000080)

Definition at line 229 of file stm32f10x_i2c.h.

#define IS_I2C_CLEAR_IT ( IT ) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00))

Definition at line 237 of file stm32f10x_i2c.h.

Referenced by I2C_ClearITPendingBit().

#define IS_I2C_CONFIG_IT ( IT ) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00))

Definition at line 213 of file stm32f10x_i2c.h.

Referenced by I2C_ITConfig().

#define IS_I2C_GET_IT ( IT )
Value:
(((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \
                           ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \
                           ((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \
                           ((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \
                           ((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \
                           ((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \
                           ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB))

Definition at line 239 of file stm32f10x_i2c.h.

Referenced by I2C_GetITStatus().


STM32F10x Standard Peripherals Firmware Library: I2C_flags_definition

Defines

I2C_flags_definition

I2C_Exported_Constants

Defines

#define | I2C_FLAG_ADD10 ((uint32_t)0x10000008)
#define | I2C_FLAG_ADDR ((uint32_t)0x10000002)
#define | I2C_FLAG_AF ((uint32_t)0x10000400)
#define | I2C_FLAG_ARLO ((uint32_t)0x10000200)
#define | I2C_FLAG_BERR ((uint32_t)0x10000100)
#define | I2C_FLAG_BTF ((uint32_t)0x10000004)
#define | I2C_FLAG_BUSY ((uint32_t)0x00020000)
#define | I2C_FLAG_DUALF ((uint32_t)0x00800000)
SR2 register flags.
#define | I2C_FLAG_GENCALL ((uint32_t)0x00100000)
#define | I2C_FLAG_MSL ((uint32_t)0x00010000)
#define | I2C_FLAG_OVR ((uint32_t)0x10000800)
#define | I2C_FLAG_PECERR ((uint32_t)0x10001000)
#define | I2C_FLAG_RXNE ((uint32_t)0x10000040)
#define | I2C_FLAG_SB ((uint32_t)0x10000001)
#define | I2C_FLAG_SMBALERT ((uint32_t)0x10008000)
SR1 register flags.
#define | I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000)
#define | I2C_FLAG_SMBHOST ((uint32_t)0x00400000)
#define | I2C_FLAG_STOPF ((uint32_t)0x10000010)
#define | I2C_FLAG_TIMEOUT ((uint32_t)0x10004000)
#define | I2C_FLAG_TRA ((uint32_t)0x00040000)
#define | I2C_FLAG_TXE ((uint32_t)0x10000080)
#define | IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00))
#define | IS_I2C_GET_FLAG(FLAG)

Define Documentation

#define I2C_FLAG_ADD10 ((uint32_t)0x10000008)

Definition at line 280 of file stm32f10x_i2c.h.

#define I2C_FLAG_ADDR ((uint32_t)0x10000002)

Definition at line 282 of file stm32f10x_i2c.h.

Referenced by sEE_ReadBuffer().

#define I2C_FLAG_AF ((uint32_t)0x10000400)

Definition at line 274 of file stm32f10x_i2c.h.

Referenced by LM75_GetStatus(), and sEE_WaitEepromStandbyState().

#define I2C_FLAG_ARLO ((uint32_t)0x10000200)

Definition at line 275 of file stm32f10x_i2c.h.

#define I2C_FLAG_BERR ((uint32_t)0x10000100)

Definition at line 276 of file stm32f10x_i2c.h.

#define I2C_FLAG_BTF ((uint32_t)0x10000004)

Definition at line 281 of file stm32f10x_i2c.h.

Referenced by I2C_ReadDataBuffer(), I2C_ReadDeviceRegister(), I2C_WriteDeviceRegister(), LM75_ReadConfReg(), LM75_ReadReg(), LM75_ReadTemp(), LM75_ShutDown(), LM75_WriteConfReg(), LM75_WriteReg(), sEE_I2C_DMA_TX_IRQHandler(), and sEE_ReadBuffer().

#define I2C_FLAG_BUSY ((uint32_t)0x00020000)

Definition at line 263 of file stm32f10x_i2c.h.

Referenced by LM75_ReadConfReg(), LM75_ReadReg(), LM75_ReadTemp(), LM75_ShutDown(), LM75_WriteConfReg(), LM75_WriteReg(), PhysicalAddressDiscovery(), sEE_ReadBuffer(), sEE_WaitEepromStandbyState(), and sEE_WritePage().

#define I2C_FLAG_DUALF ((uint32_t)0x00800000)

SR2 register flags.

Definition at line 258 of file stm32f10x_i2c.h.

#define I2C_FLAG_GENCALL ((uint32_t)0x00100000)

Definition at line 261 of file stm32f10x_i2c.h.

#define I2C_FLAG_MSL ((uint32_t)0x00010000)

Definition at line 264 of file stm32f10x_i2c.h.

#define I2C_FLAG_OVR ((uint32_t)0x10000800)

Definition at line 273 of file stm32f10x_i2c.h.

#define I2C_FLAG_PECERR ((uint32_t)0x10001000)

Definition at line 272 of file stm32f10x_i2c.h.

#define I2C_FLAG_RXNE ((uint32_t)0x10000040)

Definition at line 278 of file stm32f10x_i2c.h.

Referenced by sEE_ReadBuffer().

#define I2C_FLAG_SB ((uint32_t)0x10000001)

Definition at line 283 of file stm32f10x_i2c.h.

Referenced by I2C_ReadDataBuffer(), I2C_ReadDeviceRegister(), I2C_WriteDeviceRegister(), LM75_GetStatus(), LM75_ReadConfReg(), LM75_ReadReg(), LM75_ReadTemp(), LM75_ShutDown(), LM75_WriteConfReg(), and LM75_WriteReg().

#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000)

SR1 register flags.

Definition at line 270 of file stm32f10x_i2c.h.

#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000)

Definition at line 260 of file stm32f10x_i2c.h.

#define I2C_FLAG_SMBHOST ((uint32_t)0x00400000)

Definition at line 259 of file stm32f10x_i2c.h.

#define I2C_FLAG_STOPF ((uint32_t)0x10000010)

Definition at line 279 of file stm32f10x_i2c.h.

Referenced by main().

#define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000)

Definition at line 271 of file stm32f10x_i2c.h.

#define I2C_FLAG_TRA ((uint32_t)0x00040000)

Definition at line 262 of file stm32f10x_i2c.h.

#define I2C_FLAG_TXE ((uint32_t)0x10000080)

Definition at line 277 of file stm32f10x_i2c.h.

Referenced by I2C_ReadDataBuffer(), I2C_ReadDeviceRegister(), I2C_WriteDeviceRegister(), LM75_ReadConfReg(), LM75_ReadReg(), LM75_ReadTemp(), LM75_ShutDown(), LM75_WriteConfReg(), and LM75_WriteReg().

#define IS_I2C_CLEAR_FLAG ( FLAG ) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00))

Definition at line 285 of file stm32f10x_i2c.h.

Referenced by I2C_ClearFlag().

#define IS_I2C_GET_FLAG ( FLAG )
Value:
(((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \
                               ((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \
                               ((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \
                               ((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \
                               ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \
                               ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \
                               ((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \
                               ((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \
                               ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \
                               ((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \
                               ((FLAG) == I2C_FLAG_SB))

Definition at line 287 of file stm32f10x_i2c.h.

Referenced by I2C_GetFlagStatus().


STM32F10x Standard Peripherals Firmware Library: I2C_Events

Defines

I2C_Events

I2C_Exported_Constants

Defines

#define | I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040)
Communication events.
#define | I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084)
#define | I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080)
#define | I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008)
#define | I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001)
Communication start.
#define | I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002)
#define | I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082)
Address Acknowledge.
#define | I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400)
#define | I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040)
Communication events.
#define | I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084)
#define | I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080)
#define | I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000)
#define | I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002)
Communication start events.
#define | I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000)
#define | I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010)
#define | I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082)
#define | I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080)
#define | IS_I2C_EVENT(EVENT)

Define Documentation

#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040)

Communication events.

If a communication is established (START condition generated and slave address acknowledged) then the master has to check on one of the following events for communication procedures:

1) Master Receiver mode: The master has to wait on the event EV7 then to read the data received from the slave (I2C_ReceiveData() function).

2) Master Transmitter mode: The master has to send data (I2C_SendData() function) then to wait on event EV8 or EV8_2. These two events are similar:

  • EV8 means that the data has been written in the data register and is being shifted out.
  • EV8_2 means that the data has been physically shifted out and output on the bus. In most cases, using EV8 is sufficient for the application. Using EV8_2 leads to a slower communication but ensure more reliable test. EV8_2 is also more suitable than EV8 for testing on the last data transmission (before Stop condition generation).
Note:
In case the user software does not guarantee that this event EV7 is managed before the current byte end of transfer, then user may check on EV7 and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)). In this case the communication may be slower.

Definition at line 383 of file stm32f10x_i2c.h.

Referenced by PhysicalAddressDiscovery().

#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084)

Definition at line 389 of file stm32f10x_i2c.h.

Referenced by PhysicalAddressDiscovery(), sEE_ReadBuffer(), and sEE_WritePage().

#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080)

Definition at line 387 of file stm32f10x_i2c.h.

Referenced by sEE_ReadBuffer(), and sEE_WritePage().

#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008)

Definition at line 350 of file stm32f10x_i2c.h.

#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001)

Communication start.

After sending the START condition (I2C_GenerateSTART() function) the master has to wait for this event. It means that the Start condition has been correctly released on the I2C bus (the bus is free, no other devices is communicating).

Definition at line 319 of file stm32f10x_i2c.h.

Referenced by main(), PhysicalAddressDiscovery(), sEE_ReadBuffer(), sEE_WaitEepromStandbyState(), and sEE_WritePage().

#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002)

Definition at line 348 of file stm32f10x_i2c.h.

Referenced by I2C_ReadDataBuffer(), I2C_ReadDeviceRegister(), LM75_ReadConfReg(), LM75_ReadReg(), LM75_ReadTemp(), LM75_ShutDown(), PhysicalAddressDiscovery(), and sEE_ReadBuffer().

#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082)

Address Acknowledge.

After checking on EV5 (start condition correctly released on the bus), the master sends the address of the slave(s) with which it will communicate (I2C_Send7bitAddress() function, it also determines the direction of the communication: Master transmitter or Receiver). Then the master has to wait that a slave acknowledges his address. If an acknowledge is sent on the bus, one of the following events will be set:

1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED event is set.

2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED is set

3) In case of 10-Bit addressing mode, the master (just after generating the START and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData() function). Then master should wait on EV9. It means that the 10-bit addressing header has been correctly sent on the bus. Then master should send the second part of the 10-bit address (LSB) using the function I2C_Send7bitAddress(). Then master should wait for event EV6.

Definition at line 347 of file stm32f10x_i2c.h.

Referenced by I2C_ReadDataBuffer(), I2C_ReadDeviceRegister(), I2C_WriteDeviceRegister(), LM75_GetStatus(), LM75_ReadConfReg(), LM75_ReadReg(), LM75_ReadTemp(), LM75_ShutDown(), LM75_WriteConfReg(), LM75_WriteReg(), main(), PhysicalAddressDiscovery(), sEE_ReadBuffer(), and sEE_WritePage().

#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400)

Definition at line 472 of file stm32f10x_i2c.h.

#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040)

Communication events.

Wait on one of these events when EV1 has already been checked and:

  • Slave RECEIVER mode:
    • EV2: When the application is expecting a data byte to be received.
    • EV4: When the application is expecting the end of the communication: master sends a stop condition and data transmission is stopped.
  • Slave Transmitter mode:
    • EV3: When a byte has been transmitted by the slave and the application is expecting the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. The second one can optionally be used when the user software doesn't guarantee the EV3 is managed before the current byte end of transfer.
    • EV3_2: When the master sends a NACK in order to tell slave that data transmission shall end (before sending the STOP condition). In this case slave has to stop sending data bytes and expect a Stop condition on the bus.
Note:
In case the user software does not guarantee that the event EV2 is managed before the current byte end of transfer, then user may check on EV2 and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)). In this case the communication may be slower.

Definition at line 463 of file stm32f10x_i2c.h.

#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084)

Definition at line 469 of file stm32f10x_i2c.h.

#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080)

Definition at line 470 of file stm32f10x_i2c.h.

#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000)

Definition at line 432 of file stm32f10x_i2c.h.

#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002)

Communication start events.

Wait on one of these events at the start of the communication. It means that the I2C peripheral detected a Start condition on the bus (generated by master device) followed by the peripheral address. The peripheral generates an ACK condition on the bus (if the acknowledge feature is enabled through function I2C_AcknowledgeConfig()) and the events listed above are set :

1) In normal case (only one address managed by the slave), when the address sent by the master matches the own address of the peripheral (configured by I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set (where XXX could be TRANSMITTER or RECEIVER).

2) In case the address sent by the master matches the second address of the peripheral (configured by the function I2C_OwnAddress2Config() and enabled by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED (where XXX could be TRANSMITTER or RECEIVER) are set.

3) In case the address sent by the master is General Call (address 0x00) and if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd()) the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED.

Definition at line 424 of file stm32f10x_i2c.h.

Referenced by main().

#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000)

Definition at line 428 of file stm32f10x_i2c.h.

#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010)

Definition at line 465 of file stm32f10x_i2c.h.

Referenced by main().

#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082)

Definition at line 425 of file stm32f10x_i2c.h.

#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080)

Definition at line 429 of file stm32f10x_i2c.h.

#define IS_I2C_EVENT ( EVENT )
Value:
(((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \
                             ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \
                             ((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \
                             ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \
                             ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \
                             ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \
                             ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \
                             ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \
                             ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \
                             ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \
                             ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \
                             ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \
                             ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \
                             ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \
                             ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \
                             ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \
                             ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \
                             ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \
                             ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \
                             ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE))

Definition at line 476 of file stm32f10x_i2c.h.

Referenced by I2C_CheckEvent().


STM32F10x Standard Peripherals Firmware Library: I2C_own_address1

Defines

I2C_own_address1

I2C_Exported_Constants

Defines

#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF)

Define Documentation

#define IS_I2C_OWN_ADDRESS1 ( ADDRESS1 ) ((ADDRESS1) <= 0x3FF)

Definition at line 504 of file stm32f10x_i2c.h.

Referenced by I2C_Init().


STM32F10x Standard Peripherals Firmware Library: I2C_clock_speed

Defines

I2C_clock_speed

I2C_Exported_Constants

Defines

#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000))

Define Documentation

#define IS_I2C_CLOCK_SPEED ( SPEED ) (((SPEED) >= 0x1) && ((SPEED) <= 400000))

Definition at line 513 of file stm32f10x_i2c.h.

Referenced by I2C_Init().


STM32F10x Standard Peripherals Firmware Library: I2C_Exported_Constants

Modules | Defines

I2C_Exported_Constants

I2C

Modules

I2C_mode
I2C_duty_cycle_in_fast_mode
I2C_acknowledgement
I2C_transfer_direction
I2C_acknowledged_address
I2C_registers
I2C_SMBus_alert_pin_level
I2C_PEC_position
I2C_NCAK_position
I2C_interrupts_definition
I2C_flags_definition
I2C_Events
I2C_own_address1
I2C_clock_speed

Defines

#define IS_I2C_ALL_PERIPH(PERIPH)

Define Documentation

#define IS_I2C_ALL_PERIPH ( PERIPH )
Value:
(((PERIPH) == I2C1) || \
                                   ((PERIPH) == I2C2))

Definition at line 80 of file stm32f10x_i2c.h.

Referenced by I2C_AcknowledgeConfig(), I2C_ARPCmd(), I2C_CalculatePEC(), I2C_CheckEvent(), I2C_ClearFlag(), I2C_ClearITPendingBit(), I2C_Cmd(), I2C_DeInit(), I2C_DMACmd(), I2C_DMALastTransferCmd(), I2C_DualAddressCmd(), I2C_FastModeDutyCycleConfig(), I2C_GeneralCallCmd(), I2C_GenerateSTART(), I2C_GenerateSTOP(), I2C_GetFlagStatus(), I2C_GetITStatus(), I2C_GetLastEvent(), I2C_GetPEC(), I2C_Init(), I2C_ITConfig(), I2C_NACKPositionConfig(), I2C_OwnAddress2Config(), I2C_PECPositionConfig(), I2C_ReadRegister(), I2C_ReceiveData(), I2C_Send7bitAddress(), I2C_SendData(), I2C_SMBusAlertConfig(), I2C_SoftwareResetCmd(), I2C_StretchClockCmd(), and I2C_TransmitPEC().


STM32F10x Standard Peripherals Firmware Library: I2C_Exported_Macros

I2C_Exported_Macros

I2C


STM32F10x Standard Peripherals Firmware Library: I2C_Exported_Functions

Functions

I2C_Exported_Functions

I2C

Functions

void | I2C_AcknowledgeConfig (I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C acknowledge feature.
void | I2C_ARPCmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C ARP.
void | I2C_CalculatePEC (I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the PEC value calculation of the transferred bytes.
ErrorStatus | I2C_CheckEvent (I2C_TypeDef *I2Cx, uint32_t I2C_EVENT)
I2C State Monitoring Functions.
void | I2C_ClearFlag (I2C_TypeDef *I2Cx, uint32_t I2C_FLAG)
Clears the I2Cx's pending flags.
void | I2C_ClearITPendingBit (I2C_TypeDef *I2Cx, uint32_t I2C_IT)
Clears the I2Cx’s interrupt pending bits.
void | I2C_Cmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C peripheral.
void | I2C_DeInit (I2C_TypeDef *I2Cx)
Deinitializes the I2Cx peripheral registers to their default reset values.
void | I2C_DMACmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C DMA requests.
void | I2C_DMALastTransferCmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
Specifies if the next DMA transfer will be the last one.
void | I2C_DualAddressCmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C dual addressing mode.
void | I2C_FastModeDutyCycleConfig (I2C_TypeDef *I2Cx, uint16_t I2C_DutyCycle)
Selects the specified I2C fast mode duty cycle.
void | I2C_GeneralCallCmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C general call feature.
void | I2C_GenerateSTART (I2C_TypeDef *I2Cx, FunctionalState NewState)
Generates I2Cx communication START condition.
void | I2C_GenerateSTOP (I2C_TypeDef *I2Cx, FunctionalState NewState)
Generates I2Cx communication STOP condition.
FlagStatus | I2C_GetFlagStatus (I2C_TypeDef *I2Cx, uint32_t I2C_FLAG)
3) Flag-based state monitoring
ITStatus | I2C_GetITStatus (I2C_TypeDef *I2Cx, uint32_t I2C_IT)
Checks whether the specified I2C interrupt has occurred or not.
uint32_t | I2C_GetLastEvent (I2C_TypeDef *I2Cx)
2) Advanced state monitoring
uint8_t | I2C_GetPEC (I2C_TypeDef *I2Cx)
Returns the PEC value for the specified I2C.
void | I2C_Init (I2C_TypeDef *I2Cx, I2C_InitTypeDef *I2C_InitStruct)
Initializes the I2Cx peripheral according to the specified parameters in the I2C_InitStruct.
void | I2C_ITConfig (I2C_TypeDef *I2Cx, uint16_t I2C_IT, FunctionalState NewState)
Enables or disables the specified I2C interrupts.
void | I2C_NACKPositionConfig (I2C_TypeDef *I2Cx, uint16_t I2C_NACKPosition)
Selects the specified I2C NACK position in master receiver mode.
void | I2C_OwnAddress2Config (I2C_TypeDef *I2Cx, uint8_t Address)
Configures the specified I2C own address2.
void | I2C_PECPositionConfig (I2C_TypeDef *I2Cx, uint16_t I2C_PECPosition)
Selects the specified I2C PEC position.
uint16_t | I2C_ReadRegister (I2C_TypeDef *I2Cx, uint8_t I2C_Register)
Reads the specified I2C register and returns its value.
uint8_t | I2C_ReceiveData (I2C_TypeDef *I2Cx)
Returns the most recent received data by the I2Cx peripheral.
void | I2C_Send7bitAddress (I2C_TypeDef *I2Cx, uint8_t Address, uint8_t I2C_Direction)
Transmits the address byte to select the slave device.
void | I2C_SendData (I2C_TypeDef *I2Cx, uint8_t Data)
Sends a data byte through the I2Cx peripheral.
void | I2C_SMBusAlertConfig (I2C_TypeDef *I2Cx, uint16_t I2C_SMBusAlert)
Drives the SMBusAlert pin high or low for the specified I2C.
void | I2C_SoftwareResetCmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C software reset.
void | I2C_StretchClockCmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C Clock stretching.
void | I2C_StructInit (I2C_InitTypeDef *I2C_InitStruct)
Fills each I2C_InitStruct member with its default value.
void | I2C_TransmitPEC (I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C PEC transfer.

Function Documentation

void I2C_AcknowledgeConfig | ( | I2C_TypeDef * | I2Cx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified I2C acknowledge feature.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
NewState,: new state of the I2C Acknowledgement. This parameter can be: ENABLE or DISABLE.
Return values:
None.

Definition at line 442 of file stm32f10x_i2c.c.

References assert_param, I2C_TypeDef::CR1, CR1_ACK_Reset, CR1_ACK_Set, DISABLE, IS_FUNCTIONAL_STATE, and IS_I2C_ALL_PERIPH.

Referenced by LM75_GetStatus(), PhysicalAddressDiscovery(), and sEE_ReadBuffer().

void I2C_ARPCmd | ( | I2C_TypeDef * | I2Cx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified I2C ARP.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
NewState,: new state of the I2Cx ARP. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 840 of file stm32f10x_i2c.c.

References assert_param, I2C_TypeDef::CR1, CR1_ENARP_Reset, CR1_ENARP_Set, DISABLE, IS_FUNCTIONAL_STATE, and IS_I2C_ALL_PERIPH.

void I2C_CalculatePEC | ( | I2C_TypeDef * | I2Cx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the PEC value calculation of the transferred bytes.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
NewState,: new state of the I2Cx PEC value calculation. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 803 of file stm32f10x_i2c.c.

References assert_param, I2C_TypeDef::CR1, CR1_ENPEC_Reset, CR1_ENPEC_Set, DISABLE, IS_FUNCTIONAL_STATE, and IS_I2C_ALL_PERIPH.

ErrorStatus I2C_CheckEvent | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | I2C_EVENT
 | ) |  |

I2C State Monitoring Functions.

This I2C driver provides three different ways for I2C state monitoring depending on the application requirements and constraints:

1) Basic state monitoring: Using I2C_CheckEvent() function: It compares the status registers (SR1 and SR2) content to a given event (can be the combination of one or more flags). It returns SUCCESS if the current status includes the given flags and returns ERROR if one or more flags are missing in the current status.

  • When to use:
    • This function is suitable for most applications as well as for startup activity since the events are fully described in the product reference manual (RM0008).
    • It is also suitable for users who need to define their own events.
  • Limitations:
    • If an error occurs (ie. error flags are set besides to the monitored flags), the I2C_CheckEvent() function may return SUCCESS despite the communication hold or corrupted real state. In this case, it is advised to use error interrupts to monitor the error events and handle them in the interrupt IRQ handler.
Note:
For error management, it is advised to use the following functions:
  • I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).
  • I2Cx_ER_IRQHandler() which is called when the error interrupt occurs. Where x is the peripheral instance (I2C1, I2C2 ...)
  • I2C_GetFlagStatus() or I2C_GetITStatus() to be called into I2Cx_ER_IRQHandler() in order to determine which error occurred.
  • I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd() and/or I2C_GenerateStop() in order to clear the error flag and source, and return to correct communication status.

2) Advanced state monitoring: Using the function I2C_GetLastEvent() which returns the image of both status registers in a single word (uint32_t) (Status Register 2 value is shifted left by 16 bits and concatenated to Status Register 1).

  • When to use:
    • This function is suitable for the same applications above but it allows to overcome the limitations of I2C_GetFlagStatus() function (see below). The returned value could be compared to events already defined in the library (stm32f10x_i2c.h) or to custom values defined by user.
    • This function is suitable when multiple flags are monitored at the same time.
    • At the opposite of I2C_CheckEvent() function, this function allows user to choose when an event is accepted (when all events flags are set and no other flags are set or just when the needed flags are set like I2C_CheckEvent() function).
  • Limitations:
    • User may need to define his own events.
    • Same remark concerning the error management is applicable for this function if user decides to check only regular communication flags (and ignores error flags).

3) Flag-based state monitoring: Using the function I2C_GetFlagStatus() which simply returns the status of one single flag (ie. I2C_FLAG_RXNE ...).

  • When to use:
    • This function could be used for specific applications or in debug phase.
    • It is suitable when only one flag checking is needed (most I2C events are monitored through multiple flags).
  • Limitations:
    • When calling this function, the Status register is accessed. Some flags are cleared when the status register is accessed. So checking the status of one Flag, may clear other ones.
    • Function may need to be called twice or more in order to monitor one single event.

1) Basic state monitoring

This I2C driver provides three different ways for I2C state monitoring depending on the application requirements and constraints:

1) Basic state monitoring: Using I2C_CheckEvent() function: It compares the status registers (SR1 and SR2) content to a given event (can be the combination of one or more flags). It returns SUCCESS if the current status includes the given flags and returns ERROR if one or more flags are missing in the current status.

  • When to use:
    • This function is suitable for most applications as well as for startup activity since the events are fully described in the product reference manual (RM0008).
    • It is also suitable for users who need to define their own events.
  • Limitations:
    • If an error occurs (ie. error flags are set besides to the monitored flags), the I2C_CheckEvent() function may return SUCCESS despite the communication hold or corrupted real state. In this case, it is advised to use error interrupts to monitor the error events and handle them in the interrupt IRQ handler.
Note:
For error management, it is advised to use the following functions:
  • I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).
  • I2Cx_ER_IRQHandler() which is called when the error interrupt occurs. Where x is the peripheral instance (I2C1, I2C2 ...)
  • I2C_GetFlagStatus() or I2C_GetITStatus() to be called into I2Cx_ER_IRQHandler() in order to determine which error occured.
  • I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd() and/or I2C_GenerateStop() in order to clear the error flag and source, and return to correct communication status.

2) Advanced state monitoring: Using the function I2C_GetLastEvent() which returns the image of both status registers in a single word (uint32_t) (Status Register 2 value is shifted left by 16 bits and concatenated to Status Register 1).

  • When to use:
    • This function is suitable for the same applications above but it allows to overcome the mentioned limitation of I2C_GetFlagStatus() function. The returned value could be compared to events already defined in the library (stm32f10x_i2c.h) or to custom values defined by user.
    • This function is suitable when multiple flags are monitored at the same time.
    • At the opposite of I2C_CheckEvent() function, this function allows user to choose when an event is accepted (when all events flags are set and no other flags are set or just when the needed flags are set like I2C_CheckEvent() function).
  • Limitations:
    • User may need to define his own events.
    • Same remark concerning the error management is applicable for this function if user decides to check only regular communication flags (and ignores error flags).

3) Flag-based state monitoring: Using the function I2C_GetFlagStatus() which simply returns the status of one single flag (ie. I2C_FLAG_RXNE ...).

  • When to use:
    • This function could be used for specific applications or in debug phase.
    • It is suitable when only one flag checking is needed (most I2C events are monitored through multiple flags).
  • Limitations:
    • When calling this function, the Status register is accessed. Some flags are cleared when the status register is accessed. So checking the status of one Flag, may clear other ones.
    • Function may need to be called twice or more in order to monitor one single event.

For detailed description of Events, please refer to section I2C_Events in stm32f10x_i2c.h file.

1) Basic state monitoring Checks whether the last I2Cx Event is equal to the one passed as parameter.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
I2C_EVENT,: specifies the event to be checked. This parameter can be one of the following values:

  • I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED : EV1
  • I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED : EV1
  • I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED : EV1
  • I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED : EV1
  • I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED : EV1
  • I2C_EVENT_SLAVE_BYTE_RECEIVED : EV2
  • (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF) : EV2
  • (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL) : EV2
  • I2C_EVENT_SLAVE_BYTE_TRANSMITTED : EV3
  • (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF) : EV3
  • (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL) : EV3
  • I2C_EVENT_SLAVE_ACK_FAILURE : EV3_2
  • I2C_EVENT_SLAVE_STOP_DETECTED : EV4
  • I2C_EVENT_MASTER_MODE_SELECT : EV5
  • I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED : EV6
  • I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED : EV6
  • I2C_EVENT_MASTER_BYTE_RECEIVED : EV7
  • I2C_EVENT_MASTER_BYTE_TRANSMITTING : EV8
  • I2C_EVENT_MASTER_BYTE_TRANSMITTED : EV8_2
  • I2C_EVENT_MASTER_MODE_ADDRESS10 : EV9
Note:
: For detailed description of Events, please refer to section I2C_Events in stm32f10x_i2c.h file.
Return values:
An ErrorStatus enumeration value:

  • SUCCESS: Last event is equal to the I2C_EVENT
  • ERROR: Last event is different from the I2C_EVENT

Definition at line 1030 of file stm32f10x_i2c.c.

References assert_param, ERROR, FLAG_Mask, IS_I2C_ALL_PERIPH, IS_I2C_EVENT, I2C_TypeDef::SR1, I2C_TypeDef::SR2, status, and SUCCESS.

Referenced by I2C_ReadDataBuffer(), I2C_ReadDeviceRegister(), I2C_WriteDeviceRegister(), LM75_GetStatus(), LM75_ReadConfReg(), LM75_ReadReg(), LM75_ReadTemp(), LM75_ShutDown(), LM75_WriteConfReg(), LM75_WriteReg(), main(), PhysicalAddressDiscovery(), sEE_ReadBuffer(), sEE_WaitEepromStandbyState(), and sEE_WritePage().

void I2C_ClearFlag | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | I2C_FLAG
 | ) |  |

Clears the I2Cx's pending flags.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
I2C_FLAG,: specifies the flag to clear. This parameter can be any combination of the following values:

  • I2C_FLAG_SMBALERT: SMBus Alert flag
  • I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
  • I2C_FLAG_PECERR: PEC error in reception flag
  • I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
  • I2C_FLAG_AF: Acknowledge failure flag
  • I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
  • I2C_FLAG_BERR: Bus error flag
Note:
  • STOPF (STOP detection) is cleared by software sequence: a read operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a write operation to I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral).
  • ADD10 (10-bit header sent) is cleared by software sequence: a read operation to I2C_SR1 (I2C_GetFlagStatus()) followed by writing the second byte of the address in DR register.
  • BTF (Byte Transfer Finished) is cleared by software sequence: a read operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a read/write to I2C_DR register (I2C_SendData()).
  • ADDR (Address sent) is cleared by software sequence: a read operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a read operation to I2C_SR2 register ((void)(I2Cx->SR2)).
  • SB (Start Bit) is cleared software sequence: a read operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a write operation to I2C_DR register (I2C_SendData()).
Return values:
None

Definition at line 1212 of file stm32f10x_i2c.c.

References assert_param, FLAG_Mask, IS_I2C_ALL_PERIPH, IS_I2C_CLEAR_FLAG, and I2C_TypeDef::SR1.

Referenced by LM75_GetStatus(), and sEE_WaitEepromStandbyState().

void I2C_ClearITPendingBit | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | I2C_IT
 | ) |  |

Clears the I2Cx’s interrupt pending bits.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
I2C_IT,: specifies the interrupt pending bit to clear. This parameter can be any combination of the following values:

  • I2C_IT_SMBALERT: SMBus Alert interrupt
  • I2C_IT_TIMEOUT: Timeout or Tlow error interrupt
  • I2C_IT_PECERR: PEC error in reception interrupt
  • I2C_IT_OVR: Overrun/Underrun interrupt (Slave mode)
  • I2C_IT_AF: Acknowledge failure interrupt
  • I2C_IT_ARLO: Arbitration lost interrupt (Master mode)
  • I2C_IT_BERR: Bus error interrupt
Note:
  • STOPF (STOP detection) is cleared by software sequence: a read operation to I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral).
  • ADD10 (10-bit header sent) is cleared by software sequence: a read operation to I2C_SR1 (I2C_GetITStatus()) followed by writing the second byte of the address in I2C_DR register.
  • BTF (Byte Transfer Finished) is cleared by software sequence: a read operation to I2C_SR1 register (I2C_GetITStatus()) followed by a read/write to I2C_DR register (I2C_SendData()).
  • ADDR (Address sent) is cleared by software sequence: a read operation to I2C_SR1 register (I2C_GetITStatus()) followed by a read operation to I2C_SR2 register ((void)(I2Cx->SR2)).
  • SB (Start Bit) is cleared by software sequence: a read operation to I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to I2C_DR register (I2C_SendData()).
Return values:
None

Definition at line 1307 of file stm32f10x_i2c.c.

References assert_param, FLAG_Mask, IS_I2C_ALL_PERIPH, IS_I2C_CLEAR_IT, and I2C_TypeDef::SR1.

Referenced by I2C1_ER_IRQHandler(), and main().

void I2C_Cmd | ( | I2C_TypeDef * | I2Cx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified I2C peripheral.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
NewState,: new state of the I2Cx peripheral. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 322 of file stm32f10x_i2c.c.

References assert_param, I2C_TypeDef::CR1, CR1_PE_Reset, CR1_PE_Set, DISABLE, IS_FUNCTIONAL_STATE, and IS_I2C_ALL_PERIPH.

Referenced by HDMI_CEC_Init(), LM75_Init(), LM75_LowLevel_DeInit(), main(), sEE_Init(), and sEE_LowLevel_DeInit().

void I2C_DeInit ( I2C_TypeDef * I2Cx )

Deinitializes the I2Cx peripheral registers to their default reset values.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
Return values:
None

Definition at line 162 of file stm32f10x_i2c.c.

References assert_param, DISABLE, ENABLE, I2C1, IS_I2C_ALL_PERIPH, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2, and RCC_APB1PeriphResetCmd().

Referenced by LM75_Init(), LM75_LowLevel_DeInit(), and sEE_LowLevel_DeInit().

void I2C_DMACmd | ( | I2C_TypeDef * | I2Cx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified I2C DMA requests.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
NewState,: new state of the I2C DMA transfer. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 346 of file stm32f10x_i2c.c.

References assert_param, I2C_TypeDef::CR2, CR2_DMAEN_Reset, CR2_DMAEN_Set, DISABLE, IS_FUNCTIONAL_STATE, and IS_I2C_ALL_PERIPH.

Referenced by I2C_ReadDataBuffer(), I2C_ReadDeviceRegister(), I2C_WriteDeviceRegister(), LM75_ReadConfReg(), LM75_ReadReg(), LM75_ReadTemp(), LM75_ShutDown(), LM75_WriteConfReg(), LM75_WriteReg(), main(), and sEE_Init().

void I2C_DMALastTransferCmd | ( | I2C_TypeDef * | I2Cx,
 |  | FunctionalState | NewState
 | ) |  |

Specifies if the next DMA transfer will be the last one.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
NewState,: new state of the I2C DMA last transfer. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 370 of file stm32f10x_i2c.c.

References assert_param, I2C_TypeDef::CR2, CR2_LAST_Reset, CR2_LAST_Set, DISABLE, IS_FUNCTIONAL_STATE, and IS_I2C_ALL_PERIPH.

Referenced by I2C_ReadDataBuffer(), I2C_ReadDeviceRegister(), LM75_ReadConfReg(), LM75_ReadReg(), LM75_ReadTemp(), LM75_ShutDown(), and sEE_ReadBuffer().

void I2C_DualAddressCmd | ( | I2C_TypeDef * | I2Cx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified I2C dual addressing mode.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
NewState,: new state of the I2C dual addressing mode. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 492 of file stm32f10x_i2c.c.

References assert_param, DISABLE, IS_FUNCTIONAL_STATE, IS_I2C_ALL_PERIPH, I2C_TypeDef::OAR2, OAR2_ENDUAL_Reset, and OAR2_ENDUAL_Set.

void I2C_FastModeDutyCycleConfig | ( | I2C_TypeDef * | I2Cx,
 |  | uint16_t | I2C_DutyCycle
 | ) |  |

Selects the specified I2C fast mode duty cycle.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
I2C_DutyCycle,: specifies the fast mode duty cycle. This parameter can be one of the following values:

  • I2C_DutyCycle_2: I2C fast mode Tlow/Thigh = 2
  • I2C_DutyCycle_16_9: I2C fast mode Tlow/Thigh = 16/9
Return values:
None

Definition at line 890 of file stm32f10x_i2c.c.

References assert_param, I2C_TypeDef::CCR, I2C_DutyCycle_16_9, I2C_DutyCycle_2, IS_I2C_ALL_PERIPH, and IS_I2C_DUTY_CYCLE.

void I2C_GeneralCallCmd | ( | I2C_TypeDef * | I2Cx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified I2C general call feature.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
NewState,: new state of the I2C General call. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 516 of file stm32f10x_i2c.c.

References assert_param, I2C_TypeDef::CR1, CR1_ENGC_Reset, CR1_ENGC_Set, DISABLE, IS_FUNCTIONAL_STATE, and IS_I2C_ALL_PERIPH.

void I2C_GenerateSTART | ( | I2C_TypeDef * | I2Cx,
 |  | FunctionalState | NewState
 | ) |  |

Generates I2Cx communication START condition.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
NewState,: new state of the I2C START condition generation. This parameter can be: ENABLE or DISABLE.
Return values:
None.

Definition at line 394 of file stm32f10x_i2c.c.

References assert_param, I2C_TypeDef::CR1, CR1_START_Reset, CR1_START_Set, DISABLE, IS_FUNCTIONAL_STATE, and IS_I2C_ALL_PERIPH.

Referenced by I2C_ReadDataBuffer(), I2C_ReadDeviceRegister(), I2C_WriteDeviceRegister(), LM75_GetStatus(), LM75_ReadConfReg(), LM75_ReadReg(), LM75_ReadTemp(), LM75_ShutDown(), LM75_WriteConfReg(), LM75_WriteReg(), main(), PhysicalAddressDiscovery(), sEE_ReadBuffer(), sEE_WaitEepromStandbyState(), and sEE_WritePage().

void I2C_GenerateSTOP | ( | I2C_TypeDef * | I2Cx,
 |  | FunctionalState | NewState
 | ) |  |

Generates I2Cx communication STOP condition.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
NewState,: new state of the I2C STOP condition generation. This parameter can be: ENABLE or DISABLE.
Return values:
None.

Definition at line 418 of file stm32f10x_i2c.c.

References assert_param, I2C_TypeDef::CR1, CR1_STOP_Reset, CR1_STOP_Set, DISABLE, IS_FUNCTIONAL_STATE, and IS_I2C_ALL_PERIPH.

Referenced by I2C_ReadDataBuffer(), I2C_ReadDeviceRegister(), I2C_WriteDeviceRegister(), LM75_ReadConfReg(), LM75_ReadReg(), LM75_ReadTemp(), LM75_ShutDown(), LM75_WriteConfReg(), LM75_WriteReg(), main(), PhysicalAddressDiscovery(), sEE_I2C_DMA_RX_IRQHandler(), sEE_I2C_DMA_TX_IRQHandler(), sEE_ReadBuffer(), and sEE_WaitEepromStandbyState().

FlagStatus I2C_GetFlagStatus | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | I2C_FLAG
 | ) |  |

3) Flag-based state monitoring

Checks whether the specified I2C flag is set or not.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
I2C_FLAG,: specifies the flag to check. This parameter can be one of the following values:

  • I2C_FLAG_DUALF: Dual flag (Slave mode)
  • I2C_FLAG_SMBHOST: SMBus host header (Slave mode)
  • I2C_FLAG_SMBDEFAULT: SMBus default header (Slave mode)
  • I2C_FLAG_GENCALL: General call header flag (Slave mode)
  • I2C_FLAG_TRA: Transmitter/Receiver flag
  • I2C_FLAG_BUSY: Bus busy flag
  • I2C_FLAG_MSL: Master/Slave flag
  • I2C_FLAG_SMBALERT: SMBus Alert flag
  • I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
  • I2C_FLAG_PECERR: PEC error in reception flag
  • I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
  • I2C_FLAG_AF: Acknowledge failure flag
  • I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
  • I2C_FLAG_BERR: Bus error flag
  • I2C_FLAG_TXE: Data register empty flag (Transmitter)
  • I2C_FLAG_RXNE: Data register not empty (Receiver) flag
  • I2C_FLAG_STOPF: Stop detection flag (Slave mode)
  • I2C_FLAG_ADD10: 10-bit header sent flag (Master mode)
  • I2C_FLAG_BTF: Byte transfer finished flag
  • I2C_FLAG_ADDR: Address sent flag (Master mode) "ADSL" Address matched flag (Slave mode)"ENDA"
  • I2C_FLAG_SB: Start bit flag (Master mode)
Return values:
The new state of I2C_FLAG (SET or RESET).

Definition at line 1133 of file stm32f10x_i2c.c.

References assert_param, FLAG_Mask, IS_I2C_ALL_PERIPH, IS_I2C_GET_FLAG, RESET, and SET.

Referenced by I2C_ReadDataBuffer(), I2C_ReadDeviceRegister(), I2C_WriteDeviceRegister(), LM75_GetStatus(), LM75_ReadConfReg(), LM75_ReadReg(), LM75_ReadTemp(), LM75_ShutDown(), LM75_WriteConfReg(), LM75_WriteReg(), main(), PhysicalAddressDiscovery(), sEE_I2C_DMA_TX_IRQHandler(), sEE_ReadBuffer(), sEE_WaitEepromStandbyState(), and sEE_WritePage().

ITStatus I2C_GetITStatus | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | I2C_IT
 | ) |  |

Checks whether the specified I2C interrupt has occurred or not.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
I2C_IT,: specifies the interrupt source to check. This parameter can be one of the following values:

  • I2C_IT_SMBALERT: SMBus Alert flag
  • I2C_IT_TIMEOUT: Timeout or Tlow error flag
  • I2C_IT_PECERR: PEC error in reception flag
  • I2C_IT_OVR: Overrun/Underrun flag (Slave mode)
  • I2C_IT_AF: Acknowledge failure flag
  • I2C_IT_ARLO: Arbitration lost flag (Master mode)
  • I2C_IT_BERR: Bus error flag
  • I2C_IT_TXE: Data register empty flag (Transmitter)
  • I2C_IT_RXNE: Data register not empty (Receiver) flag
  • I2C_IT_STOPF: Stop detection flag (Slave mode)
  • I2C_IT_ADD10: 10-bit header sent flag (Master mode)
  • I2C_IT_BTF: Byte transfer finished flag
  • I2C_IT_ADDR: Address sent flag (Master mode) "ADSL" Address matched flag (Slave mode)"ENDAD"
  • I2C_IT_SB: Start bit flag (Master mode)
Return values:
The new state of I2C_IT (SET or RESET).

Definition at line 1246 of file stm32f10x_i2c.c.

References assert_param, I2C_TypeDef::CR2, FLAG_Mask, IS_I2C_ALL_PERIPH, IS_I2C_GET_IT, ITEN_Mask, RESET, SET, and I2C_TypeDef::SR1.

Referenced by I2C1_ER_IRQHandler().

uint32_t I2C_GetLastEvent ( I2C_TypeDef * I2Cx )

2) Advanced state monitoring

Returns the last I2Cx Event.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
Note:
: For detailed description of Events, please refer to section I2C_Events in stm32f10x_i2c.h file.
Return values:
The last event

Definition at line 1078 of file stm32f10x_i2c.c.

References assert_param, FLAG_Mask, IS_I2C_ALL_PERIPH, I2C_TypeDef::SR1, and I2C_TypeDef::SR2.

uint8_t I2C_GetPEC ( I2C_TypeDef * I2Cx )

Returns the PEC value for the specified I2C.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
Return values:
The PEC value.

Definition at line 825 of file stm32f10x_i2c.c.

References assert_param, IS_I2C_ALL_PERIPH, and I2C_TypeDef::SR2.

void I2C_Init | ( | I2C_TypeDef * | I2Cx,
 |  | I2C_InitTypeDef * | I2C_InitStruct
 | ) |  |

Initializes the I2Cx peripheral according to the specified parameters in the I2C_InitStruct.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
I2C_InitStruct,: pointer to a I2C_InitTypeDef structure that contains the configuration information for the specified I2C peripheral.
Return values:
None

Definition at line 191 of file stm32f10x_i2c.c.

References assert_param, I2C_TypeDef::CCR, CCR_CCR_Set, CCR_FS_Set, I2C_TypeDef::CR1, CR1_CLEAR_Mask, CR1_PE_Reset, CR1_PE_Set, I2C_TypeDef::CR2, CR2_FREQ_Reset, I2C_InitTypeDef::I2C_Ack, I2C_InitTypeDef::I2C_AcknowledgedAddress, I2C_InitTypeDef::I2C_ClockSpeed, I2C_InitTypeDef::I2C_DutyCycle, I2C_DutyCycle_16_9, I2C_DutyCycle_2, I2C_InitTypeDef::I2C_Mode, I2C_InitTypeDef::I2C_OwnAddress1, IS_I2C_ACK_STATE, IS_I2C_ACKNOWLEDGE_ADDRESS, IS_I2C_ALL_PERIPH, IS_I2C_CLOCK_SPEED, IS_I2C_DUTY_CYCLE, IS_I2C_MODE, IS_I2C_OWN_ADDRESS1, I2C_TypeDef::OAR1, RCC_ClocksTypeDef::PCLK1_Frequency, RCC_GetClocksFreq(), and I2C_TypeDef::TRISE.

Referenced by HDMI_CEC_Init(), IOE_I2C_Config(), LM75_Init(), main(), and sEE_Init().

void I2C_ITConfig | ( | I2C_TypeDef * | I2Cx,
 |  | uint16_t | I2C_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified I2C interrupts.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
I2C_IT,: specifies the I2C interrupts sources to be enabled or disabled. This parameter can be any combination of the following values:

  • I2C_IT_BUF: Buffer interrupt mask
  • I2C_IT_EVT: Event interrupt mask
  • I2C_IT_ERR: Error interrupt mask
NewState,: new state of the specified I2C interrupts. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 545 of file stm32f10x_i2c.c.

References assert_param, I2C_TypeDef::CR2, DISABLE, IS_FUNCTIONAL_STATE, IS_I2C_ALL_PERIPH, and IS_I2C_CONFIG_IT.

Referenced by LM75_Init().

void I2C_NACKPositionConfig | ( | I2C_TypeDef * | I2Cx,
 |  | uint16_t | I2C_NACKPosition
 | ) |  |

Selects the specified I2C NACK position in master receiver mode.

This function is useful in I2C Master Receiver mode when the number of data to be received is equal to 2. In this case, this function should be called (with parameter I2C_NACKPosition_Next) before data reception starts,as described in the 2-byte reception procedure recommended in Reference Manual in Section: Master receiver.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
I2C_NACKPosition,: specifies the NACK position. This parameter can be one of the following values:

  • I2C_NACKPosition_Next: indicates that the next byte will be the last received byte.
  • I2C_NACKPosition_Current: indicates that current byte is the last received byte.
Note:
This function configures the same bit (POS) as I2C_PECPositionConfig() but is intended to be used in I2C mode while I2C_PECPositionConfig() is intended to used in SMBUS mode.
Return values:
None

Definition at line 696 of file stm32f10x_i2c.c.

References assert_param, I2C_TypeDef::CR1, I2C_NACKPosition_Current, I2C_NACKPosition_Next, IS_I2C_ALL_PERIPH, and IS_I2C_NACK_POSITION.

void I2C_OwnAddress2Config | ( | I2C_TypeDef * | I2Cx,
 |  | uint8_t | Address
 | ) |  |

Configures the specified I2C own address2.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
Address,: specifies the 7bit I2C own address2.
Return values:
None.

Definition at line 465 of file stm32f10x_i2c.c.

References assert_param, IS_I2C_ALL_PERIPH, I2C_TypeDef::OAR2, and OAR2_ADD2_Reset.

void I2C_PECPositionConfig | ( | I2C_TypeDef * | I2Cx,
 |  | uint16_t | I2C_PECPosition
 | ) |  |

Selects the specified I2C PEC position.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
I2C_PECPosition,: specifies the PEC position. This parameter can be one of the following values:

  • I2C_PECPosition_Next: indicates that the next byte is PEC
  • I2C_PECPosition_Current: indicates that current byte is PEC
Note:
This function configures the same bit (POS) as I2C_NACKPositionConfig() but is intended to be used in SMBUS mode while I2C_NACKPositionConfig() is intended to used in I2C mode.
Return values:
None

Definition at line 779 of file stm32f10x_i2c.c.

References assert_param, I2C_TypeDef::CR1, I2C_PECPosition_Current, I2C_PECPosition_Next, IS_I2C_ALL_PERIPH, and IS_I2C_PEC_POSITION.

uint16_t I2C_ReadRegister | ( | I2C_TypeDef * | I2Cx,
 |  | uint8_t | I2C_Register
 | ) |  |

Reads the specified I2C register and returns its value.

Parameters:
I2C_Register,: specifies the register to read. This parameter can be one of the following values:

  • I2C_Register_CR1: CR1 register.
  • I2C_Register_CR2: CR2 register.
  • I2C_Register_OAR1: OAR1 register.
  • I2C_Register_OAR2: OAR2 register.
  • I2C_Register_DR: DR register.
  • I2C_Register_SR1: SR1 register.
  • I2C_Register_SR2: SR2 register.
  • I2C_Register_CCR: CCR register.
  • I2C_Register_TRISE: TRISE register.
Return values:
The value of the read register.

Definition at line 636 of file stm32f10x_i2c.c.

References assert_param, IS_I2C_ALL_PERIPH, and IS_I2C_REGISTER.

uint8_t I2C_ReceiveData ( I2C_TypeDef * I2Cx )

Returns the most recent received data by the I2Cx peripheral.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
Return values:
The value of the received data.

Definition at line 583 of file stm32f10x_i2c.c.

References assert_param, I2C_TypeDef::DR, and IS_I2C_ALL_PERIPH.

Referenced by PhysicalAddressDiscovery(), and sEE_ReadBuffer().

void I2C_Send7bitAddress | ( | I2C_TypeDef * | I2Cx,
 |  | uint8_t | Address,
 |  | uint8_t | I2C_Direction
 | ) |  |

Transmits the address byte to select the slave device.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
Address,: specifies the slave address which will be transmitted
I2C_Direction,: specifies whether the I2C device will be a Transmitter or a Receiver. This parameter can be one of the following values

  • I2C_Direction_Transmitter: Transmitter mode
  • I2C_Direction_Receiver: Receiver mode
Return values:
None.

Definition at line 601 of file stm32f10x_i2c.c.

References Address, assert_param, I2C_TypeDef::DR, I2C_Direction_Transmitter, IS_I2C_ALL_PERIPH, IS_I2C_DIRECTION, OAR1_ADD0_Reset, and OAR1_ADD0_Set.

Referenced by I2C_ReadDataBuffer(), I2C_ReadDeviceRegister(), I2C_WriteDeviceRegister(), LM75_GetStatus(), LM75_ReadConfReg(), LM75_ReadReg(), LM75_ReadTemp(), LM75_ShutDown(), LM75_WriteConfReg(), LM75_WriteReg(), main(), PhysicalAddressDiscovery(), sEE_ReadBuffer(), sEE_WaitEepromStandbyState(), and sEE_WritePage().

void I2C_SendData | ( | I2C_TypeDef * | I2Cx,
 |  | uint8_t | Data
 | ) |  |

Sends a data byte through the I2Cx peripheral.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
Data,: Byte to be transmitted..
Return values:
None

Definition at line 570 of file stm32f10x_i2c.c.

References assert_param, Data, I2C_TypeDef::DR, and IS_I2C_ALL_PERIPH.

Referenced by I2C_ReadDataBuffer(), I2C_ReadDeviceRegister(), I2C_WriteDeviceRegister(), LM75_ReadConfReg(), LM75_ReadReg(), LM75_ReadTemp(), LM75_ShutDown(), LM75_WriteConfReg(), LM75_WriteReg(), PhysicalAddressDiscovery(), sEE_ReadBuffer(), and sEE_WritePage().

void I2C_SMBusAlertConfig | ( | I2C_TypeDef * | I2Cx,
 |  | uint16_t | I2C_SMBusAlert
 | ) |  |

Drives the SMBusAlert pin high or low for the specified I2C.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
I2C_SMBusAlert,: specifies SMBAlert pin level. This parameter can be one of the following values:

  • I2C_SMBusAlert_Low: SMBAlert pin driven low
  • I2C_SMBusAlert_High: SMBAlert pin driven high
Return values:
None

Definition at line 724 of file stm32f10x_i2c.c.

References assert_param, I2C_TypeDef::CR1, I2C_SMBusAlert_High, I2C_SMBusAlert_Low, IS_I2C_ALL_PERIPH, and IS_I2C_SMBUS_ALERT.

void I2C_SoftwareResetCmd | ( | I2C_TypeDef * | I2Cx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified I2C software reset.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
NewState,: new state of the I2C software reset. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 658 of file stm32f10x_i2c.c.

References assert_param, I2C_TypeDef::CR1, CR1_SWRST_Reset, CR1_SWRST_Set, DISABLE, IS_FUNCTIONAL_STATE, and IS_I2C_ALL_PERIPH.

void I2C_StretchClockCmd | ( | I2C_TypeDef * | I2Cx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified I2C Clock stretching.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
NewState,: new state of the I2Cx Clock stretching. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 864 of file stm32f10x_i2c.c.

References assert_param, I2C_TypeDef::CR1, CR1_NOSTRETCH_Reset, CR1_NOSTRETCH_Set, DISABLE, IS_FUNCTIONAL_STATE, and IS_I2C_ALL_PERIPH.

void I2C_StructInit ( I2C_InitTypeDef * I2C_InitStruct )

Fills each I2C_InitStruct member with its default value.

Parameters:
I2C_InitStruct,: pointer to an I2C_InitTypeDef structure which will be initialized.
Return values:
None

Definition at line 298 of file stm32f10x_i2c.c.

References I2C_InitTypeDef::I2C_Ack, I2C_Ack_Disable, I2C_InitTypeDef::I2C_AcknowledgedAddress, I2C_AcknowledgedAddress_7bit, I2C_InitTypeDef::I2C_ClockSpeed, I2C_InitTypeDef::I2C_DutyCycle, I2C_DutyCycle_2, I2C_InitTypeDef::I2C_Mode, I2C_Mode_I2C, and I2C_InitTypeDef::I2C_OwnAddress1.

void I2C_TransmitPEC | ( | I2C_TypeDef * | I2Cx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified I2C PEC transfer.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
NewState,: new state of the I2C PEC transmission. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 748 of file stm32f10x_i2c.c.

References assert_param, I2C_TypeDef::CR1, CR1_PEC_Reset, CR1_PEC_Set, DISABLE, IS_FUNCTIONAL_STATE, and IS_I2C_ALL_PERIPH.


STM32F10x Standard Peripherals Firmware Library: I2C_Private_TypesDefinitions

I2C_Private_TypesDefinitions

I2C


STM32F10x Standard Peripherals Firmware Library: I2C_Private_Defines

Defines

I2C_Private_Defines

I2C

Defines

#define | CCR_CCR_Set ((uint16_t)0x0FFF)
#define | CCR_FS_Set ((uint16_t)0x8000)
#define | CR1_ACK_Reset ((uint16_t)0xFBFF)
#define | CR1_ACK_Set ((uint16_t)0x0400)
#define | CR1_CLEAR_Mask ((uint16_t)0xFBF5)
#define | CR1_ENARP_Reset ((uint16_t)0xFFEF)
#define | CR1_ENARP_Set ((uint16_t)0x0010)
#define | CR1_ENGC_Reset ((uint16_t)0xFFBF)
#define | CR1_ENGC_Set ((uint16_t)0x0040)
#define | CR1_ENPEC_Reset ((uint16_t)0xFFDF)
#define | CR1_ENPEC_Set ((uint16_t)0x0020)
#define | CR1_NOSTRETCH_Reset ((uint16_t)0xFF7F)
#define | CR1_NOSTRETCH_Set ((uint16_t)0x0080)
#define | CR1_PE_Reset ((uint16_t)0xFFFE)
#define | CR1_PE_Set ((uint16_t)0x0001)
#define | CR1_PEC_Reset ((uint16_t)0xEFFF)
#define | CR1_PEC_Set ((uint16_t)0x1000)
#define | CR1_START_Reset ((uint16_t)0xFEFF)
#define | CR1_START_Set ((uint16_t)0x0100)
#define | CR1_STOP_Reset ((uint16_t)0xFDFF)
#define | CR1_STOP_Set ((uint16_t)0x0200)
#define | CR1_SWRST_Reset ((uint16_t)0x7FFF)
#define | CR1_SWRST_Set ((uint16_t)0x8000)
#define | CR2_DMAEN_Reset ((uint16_t)0xF7FF)
#define | CR2_DMAEN_Set ((uint16_t)0x0800)
#define | CR2_FREQ_Reset ((uint16_t)0xFFC0)
#define | CR2_LAST_Reset ((uint16_t)0xEFFF)
#define | CR2_LAST_Set ((uint16_t)0x1000)
#define | FLAG_Mask ((uint32_t)0x00FFFFFF)
#define | ITEN_Mask ((uint32_t)0x07000000)
#define | OAR1_ADD0_Reset ((uint16_t)0xFFFE)
#define | OAR1_ADD0_Set ((uint16_t)0x0001)
#define | OAR2_ADD2_Reset ((uint16_t)0xFF01)
#define | OAR2_ENDUAL_Reset ((uint16_t)0xFFFE)
#define | OAR2_ENDUAL_Set ((uint16_t)0x0001)

Define Documentation

#define CCR_CCR_Set ((uint16_t)0x0FFF)

Definition at line 117 of file stm32f10x_i2c.c.

Referenced by I2C_Init().

#define CCR_FS_Set ((uint16_t)0x8000)

Definition at line 114 of file stm32f10x_i2c.c.

Referenced by I2C_Init().

#define CR1_ACK_Reset ((uint16_t)0xFBFF)

Definition at line 62 of file stm32f10x_i2c.c.

Referenced by I2C_AcknowledgeConfig().

#define CR1_ACK_Set ((uint16_t)0x0400)

Definition at line 61 of file stm32f10x_i2c.c.

Referenced by I2C_AcknowledgeConfig().

#define CR1_CLEAR_Mask ((uint16_t)0xFBF5)

Definition at line 89 of file stm32f10x_i2c.c.

Referenced by I2C_Init().

#define CR1_ENARP_Reset ((uint16_t)0xFFEF)

Definition at line 82 of file stm32f10x_i2c.c.

Referenced by I2C_ARPCmd().

#define CR1_ENARP_Set ((uint16_t)0x0010)

Definition at line 81 of file stm32f10x_i2c.c.

Referenced by I2C_ARPCmd().

#define CR1_ENGC_Reset ((uint16_t)0xFFBF)

Definition at line 66 of file stm32f10x_i2c.c.

Referenced by I2C_GeneralCallCmd().

#define CR1_ENGC_Set ((uint16_t)0x0040)

Definition at line 65 of file stm32f10x_i2c.c.

Referenced by I2C_GeneralCallCmd().

#define CR1_ENPEC_Reset ((uint16_t)0xFFDF)

Definition at line 78 of file stm32f10x_i2c.c.

Referenced by I2C_CalculatePEC().

#define CR1_ENPEC_Set ((uint16_t)0x0020)

Definition at line 77 of file stm32f10x_i2c.c.

Referenced by I2C_CalculatePEC().

#define CR1_NOSTRETCH_Reset ((uint16_t)0xFF7F)

Definition at line 86 of file stm32f10x_i2c.c.

Referenced by I2C_StretchClockCmd().

#define CR1_NOSTRETCH_Set ((uint16_t)0x0080)

Definition at line 85 of file stm32f10x_i2c.c.

Referenced by I2C_StretchClockCmd().

#define CR1_PE_Reset ((uint16_t)0xFFFE)

Definition at line 50 of file stm32f10x_i2c.c.

Referenced by I2C_Cmd(), and I2C_Init().

#define CR1_PE_Set ((uint16_t)0x0001)

Definition at line 49 of file stm32f10x_i2c.c.

Referenced by I2C_Cmd(), and I2C_Init().

#define CR1_PEC_Reset ((uint16_t)0xEFFF)

Definition at line 74 of file stm32f10x_i2c.c.

Referenced by I2C_TransmitPEC().

#define CR1_PEC_Set ((uint16_t)0x1000)

Definition at line 73 of file stm32f10x_i2c.c.

Referenced by I2C_TransmitPEC().

#define CR1_START_Reset ((uint16_t)0xFEFF)

Definition at line 54 of file stm32f10x_i2c.c.

Referenced by I2C_GenerateSTART().

#define CR1_START_Set ((uint16_t)0x0100)

Definition at line 53 of file stm32f10x_i2c.c.

Referenced by I2C_GenerateSTART().

#define CR1_STOP_Reset ((uint16_t)0xFDFF)

Definition at line 58 of file stm32f10x_i2c.c.

Referenced by I2C_GenerateSTOP().

#define CR1_STOP_Set ((uint16_t)0x0200)

Definition at line 57 of file stm32f10x_i2c.c.

Referenced by I2C_GenerateSTOP().

#define CR1_SWRST_Reset ((uint16_t)0x7FFF)

Definition at line 70 of file stm32f10x_i2c.c.

Referenced by I2C_SoftwareResetCmd().

#define CR1_SWRST_Set ((uint16_t)0x8000)

Definition at line 69 of file stm32f10x_i2c.c.

Referenced by I2C_SoftwareResetCmd().

#define CR2_DMAEN_Reset ((uint16_t)0xF7FF)

Definition at line 93 of file stm32f10x_i2c.c.

Referenced by I2C_DMACmd().

#define CR2_DMAEN_Set ((uint16_t)0x0800)

Definition at line 92 of file stm32f10x_i2c.c.

Referenced by I2C_DMACmd().

#define CR2_FREQ_Reset ((uint16_t)0xFFC0)

Definition at line 100 of file stm32f10x_i2c.c.

Referenced by I2C_Init().

#define CR2_LAST_Reset ((uint16_t)0xEFFF)

Definition at line 97 of file stm32f10x_i2c.c.

Referenced by I2C_DMALastTransferCmd().

#define CR2_LAST_Set ((uint16_t)0x1000)

Definition at line 96 of file stm32f10x_i2c.c.

Referenced by I2C_DMALastTransferCmd().

#define FLAG_Mask ((uint32_t)0x00FFFFFF)

Definition at line 120 of file stm32f10x_i2c.c.

Referenced by I2C_CheckEvent(), I2C_ClearFlag(), I2C_ClearITPendingBit(), I2C_GetFlagStatus(), I2C_GetITStatus(), and I2C_GetLastEvent().

#define ITEN_Mask ((uint32_t)0x07000000)

Definition at line 123 of file stm32f10x_i2c.c.

Referenced by I2C_GetITStatus().

#define OAR1_ADD0_Reset ((uint16_t)0xFFFE)

Definition at line 104 of file stm32f10x_i2c.c.

Referenced by I2C_Send7bitAddress().

#define OAR1_ADD0_Set ((uint16_t)0x0001)

Definition at line 103 of file stm32f10x_i2c.c.

Referenced by I2C_Send7bitAddress().

#define OAR2_ADD2_Reset ((uint16_t)0xFF01)

Definition at line 111 of file stm32f10x_i2c.c.

Referenced by I2C_OwnAddress2Config().

#define OAR2_ENDUAL_Reset ((uint16_t)0xFFFE)

Definition at line 108 of file stm32f10x_i2c.c.

Referenced by I2C_DualAddressCmd().

#define OAR2_ENDUAL_Set ((uint16_t)0x0001)

Definition at line 107 of file stm32f10x_i2c.c.

Referenced by I2C_DualAddressCmd().


STM32F10x Standard Peripherals Firmware Library: I2C_Private_Macros

I2C_Private_Macros

I2C


STM32F10x Standard Peripherals Firmware Library: I2C_Private_Variables

I2C_Private_Variables

I2C


STM32F10x Standard Peripherals Firmware Library: I2C_Private_FunctionPrototypes

I2C_Private_FunctionPrototypes

I2C


STM32F10x Standard Peripherals Firmware Library: I2C_Private_Functions

Functions

I2C_Private_Functions

I2C

Functions

void | I2C_AcknowledgeConfig (I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C acknowledge feature.
void | I2C_ARPCmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C ARP.
void | I2C_CalculatePEC (I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the PEC value calculation of the transferred bytes.
ErrorStatus | I2C_CheckEvent (I2C_TypeDef *I2Cx, uint32_t I2C_EVENT)
I2C State Monitoring Functions.
void | I2C_ClearFlag (I2C_TypeDef *I2Cx, uint32_t I2C_FLAG)
Clears the I2Cx's pending flags.
void | I2C_ClearITPendingBit (I2C_TypeDef *I2Cx, uint32_t I2C_IT)
Clears the I2Cx’s interrupt pending bits.
void | I2C_Cmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C peripheral.
void | I2C_DeInit (I2C_TypeDef *I2Cx)
Deinitializes the I2Cx peripheral registers to their default reset values.
void | I2C_DMACmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C DMA requests.
void | I2C_DMALastTransferCmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
Specifies if the next DMA transfer will be the last one.
void | I2C_DualAddressCmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C dual addressing mode.
void | I2C_FastModeDutyCycleConfig (I2C_TypeDef *I2Cx, uint16_t I2C_DutyCycle)
Selects the specified I2C fast mode duty cycle.
void | I2C_GeneralCallCmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C general call feature.
void | I2C_GenerateSTART (I2C_TypeDef *I2Cx, FunctionalState NewState)
Generates I2Cx communication START condition.
void | I2C_GenerateSTOP (I2C_TypeDef *I2Cx, FunctionalState NewState)
Generates I2Cx communication STOP condition.
FlagStatus | I2C_GetFlagStatus (I2C_TypeDef *I2Cx, uint32_t I2C_FLAG)
3) Flag-based state monitoring
ITStatus | I2C_GetITStatus (I2C_TypeDef *I2Cx, uint32_t I2C_IT)
Checks whether the specified I2C interrupt has occurred or not.
uint32_t | I2C_GetLastEvent (I2C_TypeDef *I2Cx)
2) Advanced state monitoring
uint8_t | I2C_GetPEC (I2C_TypeDef *I2Cx)
Returns the PEC value for the specified I2C.
void | I2C_Init (I2C_TypeDef *I2Cx, I2C_InitTypeDef *I2C_InitStruct)
Initializes the I2Cx peripheral according to the specified parameters in the I2C_InitStruct.
void | I2C_ITConfig (I2C_TypeDef *I2Cx, uint16_t I2C_IT, FunctionalState NewState)
Enables or disables the specified I2C interrupts.
void | I2C_NACKPositionConfig (I2C_TypeDef *I2Cx, uint16_t I2C_NACKPosition)
Selects the specified I2C NACK position in master receiver mode.
void | I2C_OwnAddress2Config (I2C_TypeDef *I2Cx, uint8_t Address)
Configures the specified I2C own address2.
void | I2C_PECPositionConfig (I2C_TypeDef *I2Cx, uint16_t I2C_PECPosition)
Selects the specified I2C PEC position.
uint16_t | I2C_ReadRegister (I2C_TypeDef *I2Cx, uint8_t I2C_Register)
Reads the specified I2C register and returns its value.
uint8_t | I2C_ReceiveData (I2C_TypeDef *I2Cx)
Returns the most recent received data by the I2Cx peripheral.
void | I2C_Send7bitAddress (I2C_TypeDef *I2Cx, uint8_t Address, uint8_t I2C_Direction)
Transmits the address byte to select the slave device.
void | I2C_SendData (I2C_TypeDef *I2Cx, uint8_t Data)
Sends a data byte through the I2Cx peripheral.
void | I2C_SMBusAlertConfig (I2C_TypeDef *I2Cx, uint16_t I2C_SMBusAlert)
Drives the SMBusAlert pin high or low for the specified I2C.
void | I2C_SoftwareResetCmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C software reset.
void | I2C_StretchClockCmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C Clock stretching.
void | I2C_StructInit (I2C_InitTypeDef *I2C_InitStruct)
Fills each I2C_InitStruct member with its default value.
void | I2C_TransmitPEC (I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C PEC transfer.

Function Documentation

void I2C_AcknowledgeConfig | ( | I2C_TypeDef * | I2Cx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified I2C acknowledge feature.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
NewState,: new state of the I2C Acknowledgement. This parameter can be: ENABLE or DISABLE.
Return values:
None.

Definition at line 442 of file stm32f10x_i2c.c.

References assert_param, I2C_TypeDef::CR1, CR1_ACK_Reset, CR1_ACK_Set, DISABLE, IS_FUNCTIONAL_STATE, and IS_I2C_ALL_PERIPH.

Referenced by LM75_GetStatus(), PhysicalAddressDiscovery(), and sEE_ReadBuffer().

void I2C_ARPCmd | ( | I2C_TypeDef * | I2Cx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified I2C ARP.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
NewState,: new state of the I2Cx ARP. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 840 of file stm32f10x_i2c.c.

References assert_param, I2C_TypeDef::CR1, CR1_ENARP_Reset, CR1_ENARP_Set, DISABLE, IS_FUNCTIONAL_STATE, and IS_I2C_ALL_PERIPH.

void I2C_CalculatePEC | ( | I2C_TypeDef * | I2Cx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the PEC value calculation of the transferred bytes.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
NewState,: new state of the I2Cx PEC value calculation. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 803 of file stm32f10x_i2c.c.

References assert_param, I2C_TypeDef::CR1, CR1_ENPEC_Reset, CR1_ENPEC_Set, DISABLE, IS_FUNCTIONAL_STATE, and IS_I2C_ALL_PERIPH.

ErrorStatus I2C_CheckEvent | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | I2C_EVENT
 | ) |  |

I2C State Monitoring Functions.

This I2C driver provides three different ways for I2C state monitoring depending on the application requirements and constraints:

1) Basic state monitoring: Using I2C_CheckEvent() function: It compares the status registers (SR1 and SR2) content to a given event (can be the combination of one or more flags). It returns SUCCESS if the current status includes the given flags and returns ERROR if one or more flags are missing in the current status.

  • When to use:
    • This function is suitable for most applications as well as for startup activity since the events are fully described in the product reference manual (RM0008).
    • It is also suitable for users who need to define their own events.
  • Limitations:
    • If an error occurs (ie. error flags are set besides to the monitored flags), the I2C_CheckEvent() function may return SUCCESS despite the communication hold or corrupted real state. In this case, it is advised to use error interrupts to monitor the error events and handle them in the interrupt IRQ handler.
Note:
For error management, it is advised to use the following functions:
  • I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).
  • I2Cx_ER_IRQHandler() which is called when the error interrupt occurs. Where x is the peripheral instance (I2C1, I2C2 ...)
  • I2C_GetFlagStatus() or I2C_GetITStatus() to be called into I2Cx_ER_IRQHandler() in order to determine which error occured.
  • I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd() and/or I2C_GenerateStop() in order to clear the error flag and source, and return to correct communication status.

2) Advanced state monitoring: Using the function I2C_GetLastEvent() which returns the image of both status registers in a single word (uint32_t) (Status Register 2 value is shifted left by 16 bits and concatenated to Status Register 1).

  • When to use:
    • This function is suitable for the same applications above but it allows to overcome the mentioned limitation of I2C_GetFlagStatus() function. The returned value could be compared to events already defined in the library (stm32f10x_i2c.h) or to custom values defined by user.
    • This function is suitable when multiple flags are monitored at the same time.
    • At the opposite of I2C_CheckEvent() function, this function allows user to choose when an event is accepted (when all events flags are set and no other flags are set or just when the needed flags are set like I2C_CheckEvent() function).
  • Limitations:
    • User may need to define his own events.
    • Same remark concerning the error management is applicable for this function if user decides to check only regular communication flags (and ignores error flags).

3) Flag-based state monitoring: Using the function I2C_GetFlagStatus() which simply returns the status of one single flag (ie. I2C_FLAG_RXNE ...).

  • When to use:
    • This function could be used for specific applications or in debug phase.
    • It is suitable when only one flag checking is needed (most I2C events are monitored through multiple flags).
  • Limitations:
    • When calling this function, the Status register is accessed. Some flags are cleared when the status register is accessed. So checking the status of one Flag, may clear other ones.
    • Function may need to be called twice or more in order to monitor one single event.

For detailed description of Events, please refer to section I2C_Events in stm32f10x_i2c.h file.

1) Basic state monitoring Checks whether the last I2Cx Event is equal to the one passed as parameter.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
I2C_EVENT,: specifies the event to be checked. This parameter can be one of the following values:

  • I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED : EV1
  • I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED : EV1
  • I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED : EV1
  • I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED : EV1
  • I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED : EV1
  • I2C_EVENT_SLAVE_BYTE_RECEIVED : EV2
  • (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF) : EV2
  • (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL) : EV2
  • I2C_EVENT_SLAVE_BYTE_TRANSMITTED : EV3
  • (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF) : EV3
  • (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL) : EV3
  • I2C_EVENT_SLAVE_ACK_FAILURE : EV3_2
  • I2C_EVENT_SLAVE_STOP_DETECTED : EV4
  • I2C_EVENT_MASTER_MODE_SELECT : EV5
  • I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED : EV6
  • I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED : EV6
  • I2C_EVENT_MASTER_BYTE_RECEIVED : EV7
  • I2C_EVENT_MASTER_BYTE_TRANSMITTING : EV8
  • I2C_EVENT_MASTER_BYTE_TRANSMITTED : EV8_2
  • I2C_EVENT_MASTER_MODE_ADDRESS10 : EV9
Note:
: For detailed description of Events, please refer to section I2C_Events in stm32f10x_i2c.h file.
Return values:
An ErrorStatus enumeration value:

  • SUCCESS: Last event is equal to the I2C_EVENT
  • ERROR: Last event is different from the I2C_EVENT

Definition at line 1030 of file stm32f10x_i2c.c.

References assert_param, ERROR, FLAG_Mask, IS_I2C_ALL_PERIPH, IS_I2C_EVENT, I2C_TypeDef::SR1, I2C_TypeDef::SR2, status, and SUCCESS.

Referenced by I2C_ReadDataBuffer(), I2C_ReadDeviceRegister(), I2C_WriteDeviceRegister(), LM75_GetStatus(), LM75_ReadConfReg(), LM75_ReadReg(), LM75_ReadTemp(), LM75_ShutDown(), LM75_WriteConfReg(), LM75_WriteReg(), main(), PhysicalAddressDiscovery(), sEE_ReadBuffer(), sEE_WaitEepromStandbyState(), and sEE_WritePage().

void I2C_ClearFlag | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | I2C_FLAG
 | ) |  |

Clears the I2Cx's pending flags.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
I2C_FLAG,: specifies the flag to clear. This parameter can be any combination of the following values:

  • I2C_FLAG_SMBALERT: SMBus Alert flag
  • I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
  • I2C_FLAG_PECERR: PEC error in reception flag
  • I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
  • I2C_FLAG_AF: Acknowledge failure flag
  • I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
  • I2C_FLAG_BERR: Bus error flag
Note:
  • STOPF (STOP detection) is cleared by software sequence: a read operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a write operation to I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral).
  • ADD10 (10-bit header sent) is cleared by software sequence: a read operation to I2C_SR1 (I2C_GetFlagStatus()) followed by writing the second byte of the address in DR register.
  • BTF (Byte Transfer Finished) is cleared by software sequence: a read operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a read/write to I2C_DR register (I2C_SendData()).
  • ADDR (Address sent) is cleared by software sequence: a read operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a read operation to I2C_SR2 register ((void)(I2Cx->SR2)).
  • SB (Start Bit) is cleared software sequence: a read operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a write operation to I2C_DR register (I2C_SendData()).
Return values:
None

Definition at line 1212 of file stm32f10x_i2c.c.

References assert_param, FLAG_Mask, IS_I2C_ALL_PERIPH, IS_I2C_CLEAR_FLAG, and I2C_TypeDef::SR1.

Referenced by LM75_GetStatus(), and sEE_WaitEepromStandbyState().

void I2C_ClearITPendingBit | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | I2C_IT
 | ) |  |

Clears the I2Cx’s interrupt pending bits.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
I2C_IT,: specifies the interrupt pending bit to clear. This parameter can be any combination of the following values:

  • I2C_IT_SMBALERT: SMBus Alert interrupt
  • I2C_IT_TIMEOUT: Timeout or Tlow error interrupt
  • I2C_IT_PECERR: PEC error in reception interrupt
  • I2C_IT_OVR: Overrun/Underrun interrupt (Slave mode)
  • I2C_IT_AF: Acknowledge failure interrupt
  • I2C_IT_ARLO: Arbitration lost interrupt (Master mode)
  • I2C_IT_BERR: Bus error interrupt
Note:
  • STOPF (STOP detection) is cleared by software sequence: a read operation to I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral).
  • ADD10 (10-bit header sent) is cleared by software sequence: a read operation to I2C_SR1 (I2C_GetITStatus()) followed by writing the second byte of the address in I2C_DR register.
  • BTF (Byte Transfer Finished) is cleared by software sequence: a read operation to I2C_SR1 register (I2C_GetITStatus()) followed by a read/write to I2C_DR register (I2C_SendData()).
  • ADDR (Address sent) is cleared by software sequence: a read operation to I2C_SR1 register (I2C_GetITStatus()) followed by a read operation to I2C_SR2 register ((void)(I2Cx->SR2)).
  • SB (Start Bit) is cleared by software sequence: a read operation to I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to I2C_DR register (I2C_SendData()).
Return values:
None

Definition at line 1307 of file stm32f10x_i2c.c.

References assert_param, FLAG_Mask, IS_I2C_ALL_PERIPH, IS_I2C_CLEAR_IT, and I2C_TypeDef::SR1.

Referenced by I2C1_ER_IRQHandler(), and main().

void I2C_Cmd | ( | I2C_TypeDef * | I2Cx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified I2C peripheral.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
NewState,: new state of the I2Cx peripheral. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 322 of file stm32f10x_i2c.c.

References assert_param, I2C_TypeDef::CR1, CR1_PE_Reset, CR1_PE_Set, DISABLE, IS_FUNCTIONAL_STATE, and IS_I2C_ALL_PERIPH.

Referenced by HDMI_CEC_Init(), LM75_Init(), LM75_LowLevel_DeInit(), main(), sEE_Init(), and sEE_LowLevel_DeInit().

void I2C_DeInit ( I2C_TypeDef * I2Cx )

Deinitializes the I2Cx peripheral registers to their default reset values.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
Return values:
None

Definition at line 162 of file stm32f10x_i2c.c.

References assert_param, DISABLE, ENABLE, I2C1, IS_I2C_ALL_PERIPH, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2, and RCC_APB1PeriphResetCmd().

Referenced by LM75_Init(), LM75_LowLevel_DeInit(), and sEE_LowLevel_DeInit().

void I2C_DMACmd | ( | I2C_TypeDef * | I2Cx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified I2C DMA requests.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
NewState,: new state of the I2C DMA transfer. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 346 of file stm32f10x_i2c.c.

References assert_param, I2C_TypeDef::CR2, CR2_DMAEN_Reset, CR2_DMAEN_Set, DISABLE, IS_FUNCTIONAL_STATE, and IS_I2C_ALL_PERIPH.

Referenced by I2C_ReadDataBuffer(), I2C_ReadDeviceRegister(), I2C_WriteDeviceRegister(), LM75_ReadConfReg(), LM75_ReadReg(), LM75_ReadTemp(), LM75_ShutDown(), LM75_WriteConfReg(), LM75_WriteReg(), main(), and sEE_Init().

void I2C_DMALastTransferCmd | ( | I2C_TypeDef * | I2Cx,
 |  | FunctionalState | NewState
 | ) |  |

Specifies if the next DMA transfer will be the last one.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
NewState,: new state of the I2C DMA last transfer. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 370 of file stm32f10x_i2c.c.

References assert_param, I2C_TypeDef::CR2, CR2_LAST_Reset, CR2_LAST_Set, DISABLE, IS_FUNCTIONAL_STATE, and IS_I2C_ALL_PERIPH.

Referenced by I2C_ReadDataBuffer(), I2C_ReadDeviceRegister(), LM75_ReadConfReg(), LM75_ReadReg(), LM75_ReadTemp(), LM75_ShutDown(), and sEE_ReadBuffer().

void I2C_DualAddressCmd | ( | I2C_TypeDef * | I2Cx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified I2C dual addressing mode.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
NewState,: new state of the I2C dual addressing mode. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 492 of file stm32f10x_i2c.c.

References assert_param, DISABLE, IS_FUNCTIONAL_STATE, IS_I2C_ALL_PERIPH, I2C_TypeDef::OAR2, OAR2_ENDUAL_Reset, and OAR2_ENDUAL_Set.

void I2C_FastModeDutyCycleConfig | ( | I2C_TypeDef * | I2Cx,
 |  | uint16_t | I2C_DutyCycle
 | ) |  |

Selects the specified I2C fast mode duty cycle.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
I2C_DutyCycle,: specifies the fast mode duty cycle. This parameter can be one of the following values:

  • I2C_DutyCycle_2: I2C fast mode Tlow/Thigh = 2
  • I2C_DutyCycle_16_9: I2C fast mode Tlow/Thigh = 16/9
Return values:
None

Definition at line 890 of file stm32f10x_i2c.c.

References assert_param, I2C_TypeDef::CCR, I2C_DutyCycle_16_9, I2C_DutyCycle_2, IS_I2C_ALL_PERIPH, and IS_I2C_DUTY_CYCLE.

void I2C_GeneralCallCmd | ( | I2C_TypeDef * | I2Cx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified I2C general call feature.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
NewState,: new state of the I2C General call. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 516 of file stm32f10x_i2c.c.

References assert_param, I2C_TypeDef::CR1, CR1_ENGC_Reset, CR1_ENGC_Set, DISABLE, IS_FUNCTIONAL_STATE, and IS_I2C_ALL_PERIPH.

void I2C_GenerateSTART | ( | I2C_TypeDef * | I2Cx,
 |  | FunctionalState | NewState
 | ) |  |

Generates I2Cx communication START condition.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
NewState,: new state of the I2C START condition generation. This parameter can be: ENABLE or DISABLE.
Return values:
None.

Definition at line 394 of file stm32f10x_i2c.c.

References assert_param, I2C_TypeDef::CR1, CR1_START_Reset, CR1_START_Set, DISABLE, IS_FUNCTIONAL_STATE, and IS_I2C_ALL_PERIPH.

Referenced by I2C_ReadDataBuffer(), I2C_ReadDeviceRegister(), I2C_WriteDeviceRegister(), LM75_GetStatus(), LM75_ReadConfReg(), LM75_ReadReg(), LM75_ReadTemp(), LM75_ShutDown(), LM75_WriteConfReg(), LM75_WriteReg(), main(), PhysicalAddressDiscovery(), sEE_ReadBuffer(), sEE_WaitEepromStandbyState(), and sEE_WritePage().

void I2C_GenerateSTOP | ( | I2C_TypeDef * | I2Cx,
 |  | FunctionalState | NewState
 | ) |  |

Generates I2Cx communication STOP condition.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
NewState,: new state of the I2C STOP condition generation. This parameter can be: ENABLE or DISABLE.
Return values:
None.

Definition at line 418 of file stm32f10x_i2c.c.

References assert_param, I2C_TypeDef::CR1, CR1_STOP_Reset, CR1_STOP_Set, DISABLE, IS_FUNCTIONAL_STATE, and IS_I2C_ALL_PERIPH.

Referenced by I2C_ReadDataBuffer(), I2C_ReadDeviceRegister(), I2C_WriteDeviceRegister(), LM75_ReadConfReg(), LM75_ReadReg(), LM75_ReadTemp(), LM75_ShutDown(), LM75_WriteConfReg(), LM75_WriteReg(), main(), PhysicalAddressDiscovery(), sEE_I2C_DMA_RX_IRQHandler(), sEE_I2C_DMA_TX_IRQHandler(), sEE_ReadBuffer(), and sEE_WaitEepromStandbyState().

FlagStatus I2C_GetFlagStatus | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | I2C_FLAG
 | ) |  |

3) Flag-based state monitoring

Checks whether the specified I2C flag is set or not.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
I2C_FLAG,: specifies the flag to check. This parameter can be one of the following values:

  • I2C_FLAG_DUALF: Dual flag (Slave mode)
  • I2C_FLAG_SMBHOST: SMBus host header (Slave mode)
  • I2C_FLAG_SMBDEFAULT: SMBus default header (Slave mode)
  • I2C_FLAG_GENCALL: General call header flag (Slave mode)
  • I2C_FLAG_TRA: Transmitter/Receiver flag
  • I2C_FLAG_BUSY: Bus busy flag
  • I2C_FLAG_MSL: Master/Slave flag
  • I2C_FLAG_SMBALERT: SMBus Alert flag
  • I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
  • I2C_FLAG_PECERR: PEC error in reception flag
  • I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
  • I2C_FLAG_AF: Acknowledge failure flag
  • I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
  • I2C_FLAG_BERR: Bus error flag
  • I2C_FLAG_TXE: Data register empty flag (Transmitter)
  • I2C_FLAG_RXNE: Data register not empty (Receiver) flag
  • I2C_FLAG_STOPF: Stop detection flag (Slave mode)
  • I2C_FLAG_ADD10: 10-bit header sent flag (Master mode)
  • I2C_FLAG_BTF: Byte transfer finished flag
  • I2C_FLAG_ADDR: Address sent flag (Master mode) "ADSL" Address matched flag (Slave mode)"ENDA"
  • I2C_FLAG_SB: Start bit flag (Master mode)
Return values:
The new state of I2C_FLAG (SET or RESET).

Definition at line 1133 of file stm32f10x_i2c.c.

References assert_param, FLAG_Mask, IS_I2C_ALL_PERIPH, IS_I2C_GET_FLAG, RESET, and SET.

Referenced by I2C_ReadDataBuffer(), I2C_ReadDeviceRegister(), I2C_WriteDeviceRegister(), LM75_GetStatus(), LM75_ReadConfReg(), LM75_ReadReg(), LM75_ReadTemp(), LM75_ShutDown(), LM75_WriteConfReg(), LM75_WriteReg(), main(), PhysicalAddressDiscovery(), sEE_I2C_DMA_TX_IRQHandler(), sEE_ReadBuffer(), sEE_WaitEepromStandbyState(), and sEE_WritePage().

ITStatus I2C_GetITStatus | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | I2C_IT
 | ) |  |

Checks whether the specified I2C interrupt has occurred or not.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
I2C_IT,: specifies the interrupt source to check. This parameter can be one of the following values:

  • I2C_IT_SMBALERT: SMBus Alert flag
  • I2C_IT_TIMEOUT: Timeout or Tlow error flag
  • I2C_IT_PECERR: PEC error in reception flag
  • I2C_IT_OVR: Overrun/Underrun flag (Slave mode)
  • I2C_IT_AF: Acknowledge failure flag
  • I2C_IT_ARLO: Arbitration lost flag (Master mode)
  • I2C_IT_BERR: Bus error flag
  • I2C_IT_TXE: Data register empty flag (Transmitter)
  • I2C_IT_RXNE: Data register not empty (Receiver) flag
  • I2C_IT_STOPF: Stop detection flag (Slave mode)
  • I2C_IT_ADD10: 10-bit header sent flag (Master mode)
  • I2C_IT_BTF: Byte transfer finished flag
  • I2C_IT_ADDR: Address sent flag (Master mode) "ADSL" Address matched flag (Slave mode)"ENDAD"
  • I2C_IT_SB: Start bit flag (Master mode)
Return values:
The new state of I2C_IT (SET or RESET).

Definition at line 1246 of file stm32f10x_i2c.c.

References assert_param, I2C_TypeDef::CR2, FLAG_Mask, IS_I2C_ALL_PERIPH, IS_I2C_GET_IT, ITEN_Mask, RESET, SET, and I2C_TypeDef::SR1.

Referenced by I2C1_ER_IRQHandler().

uint32_t I2C_GetLastEvent ( I2C_TypeDef * I2Cx )

2) Advanced state monitoring

Returns the last I2Cx Event.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
Note:
: For detailed description of Events, please refer to section I2C_Events in stm32f10x_i2c.h file.
Return values:
The last event

Definition at line 1078 of file stm32f10x_i2c.c.

References assert_param, FLAG_Mask, IS_I2C_ALL_PERIPH, I2C_TypeDef::SR1, and I2C_TypeDef::SR2.

uint8_t I2C_GetPEC ( I2C_TypeDef * I2Cx )

Returns the PEC value for the specified I2C.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
Return values:
The PEC value.

Definition at line 825 of file stm32f10x_i2c.c.

References assert_param, IS_I2C_ALL_PERIPH, and I2C_TypeDef::SR2.

void I2C_Init | ( | I2C_TypeDef * | I2Cx,
 |  | I2C_InitTypeDef * | I2C_InitStruct
 | ) |  |

Initializes the I2Cx peripheral according to the specified parameters in the I2C_InitStruct.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
I2C_InitStruct,: pointer to a I2C_InitTypeDef structure that contains the configuration information for the specified I2C peripheral.
Return values:
None

Definition at line 191 of file stm32f10x_i2c.c.

References assert_param, I2C_TypeDef::CCR, CCR_CCR_Set, CCR_FS_Set, I2C_TypeDef::CR1, CR1_CLEAR_Mask, CR1_PE_Reset, CR1_PE_Set, I2C_TypeDef::CR2, CR2_FREQ_Reset, I2C_InitTypeDef::I2C_Ack, I2C_InitTypeDef::I2C_AcknowledgedAddress, I2C_InitTypeDef::I2C_ClockSpeed, I2C_InitTypeDef::I2C_DutyCycle, I2C_DutyCycle_16_9, I2C_DutyCycle_2, I2C_InitTypeDef::I2C_Mode, I2C_InitTypeDef::I2C_OwnAddress1, IS_I2C_ACK_STATE, IS_I2C_ACKNOWLEDGE_ADDRESS, IS_I2C_ALL_PERIPH, IS_I2C_CLOCK_SPEED, IS_I2C_DUTY_CYCLE, IS_I2C_MODE, IS_I2C_OWN_ADDRESS1, I2C_TypeDef::OAR1, RCC_ClocksTypeDef::PCLK1_Frequency, RCC_GetClocksFreq(), and I2C_TypeDef::TRISE.

Referenced by HDMI_CEC_Init(), IOE_I2C_Config(), LM75_Init(), main(), and sEE_Init().

void I2C_ITConfig | ( | I2C_TypeDef * | I2Cx,
 |  | uint16_t | I2C_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified I2C interrupts.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
I2C_IT,: specifies the I2C interrupts sources to be enabled or disabled. This parameter can be any combination of the following values:

  • I2C_IT_BUF: Buffer interrupt mask
  • I2C_IT_EVT: Event interrupt mask
  • I2C_IT_ERR: Error interrupt mask
NewState,: new state of the specified I2C interrupts. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 545 of file stm32f10x_i2c.c.

References assert_param, I2C_TypeDef::CR2, DISABLE, IS_FUNCTIONAL_STATE, IS_I2C_ALL_PERIPH, and IS_I2C_CONFIG_IT.

Referenced by LM75_Init().

void I2C_NACKPositionConfig | ( | I2C_TypeDef * | I2Cx,
 |  | uint16_t | I2C_NACKPosition
 | ) |  |

Selects the specified I2C NACK position in master receiver mode.

This function is useful in I2C Master Receiver mode when the number of data to be received is equal to 2. In this case, this function should be called (with parameter I2C_NACKPosition_Next) before data reception starts,as described in the 2-byte reception procedure recommended in Reference Manual in Section: Master receiver.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
I2C_NACKPosition,: specifies the NACK position. This parameter can be one of the following values:

  • I2C_NACKPosition_Next: indicates that the next byte will be the last received byte.
  • I2C_NACKPosition_Current: indicates that current byte is the last received byte.
Note:
This function configures the same bit (POS) as I2C_PECPositionConfig() but is intended to be used in I2C mode while I2C_PECPositionConfig() is intended to used in SMBUS mode.
Return values:
None

Definition at line 696 of file stm32f10x_i2c.c.

References assert_param, I2C_TypeDef::CR1, I2C_NACKPosition_Current, I2C_NACKPosition_Next, IS_I2C_ALL_PERIPH, and IS_I2C_NACK_POSITION.

void I2C_OwnAddress2Config | ( | I2C_TypeDef * | I2Cx,
 |  | uint8_t | Address
 | ) |  |

Configures the specified I2C own address2.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
Address,: specifies the 7bit I2C own address2.
Return values:
None.

Definition at line 465 of file stm32f10x_i2c.c.

References assert_param, IS_I2C_ALL_PERIPH, I2C_TypeDef::OAR2, and OAR2_ADD2_Reset.

void I2C_PECPositionConfig | ( | I2C_TypeDef * | I2Cx,
 |  | uint16_t | I2C_PECPosition
 | ) |  |

Selects the specified I2C PEC position.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
I2C_PECPosition,: specifies the PEC position. This parameter can be one of the following values:

  • I2C_PECPosition_Next: indicates that the next byte is PEC
  • I2C_PECPosition_Current: indicates that current byte is PEC
Note:
This function configures the same bit (POS) as I2C_NACKPositionConfig() but is intended to be used in SMBUS mode while I2C_NACKPositionConfig() is intended to used in I2C mode.
Return values:
None

Definition at line 779 of file stm32f10x_i2c.c.

References assert_param, I2C_TypeDef::CR1, I2C_PECPosition_Current, I2C_PECPosition_Next, IS_I2C_ALL_PERIPH, and IS_I2C_PEC_POSITION.

uint16_t I2C_ReadRegister | ( | I2C_TypeDef * | I2Cx,
 |  | uint8_t | I2C_Register
 | ) |  |

Reads the specified I2C register and returns its value.

Parameters:
I2C_Register,: specifies the register to read. This parameter can be one of the following values:

  • I2C_Register_CR1: CR1 register.
  • I2C_Register_CR2: CR2 register.
  • I2C_Register_OAR1: OAR1 register.
  • I2C_Register_OAR2: OAR2 register.
  • I2C_Register_DR: DR register.
  • I2C_Register_SR1: SR1 register.
  • I2C_Register_SR2: SR2 register.
  • I2C_Register_CCR: CCR register.
  • I2C_Register_TRISE: TRISE register.
Return values:
The value of the read register.

Definition at line 636 of file stm32f10x_i2c.c.

References assert_param, IS_I2C_ALL_PERIPH, and IS_I2C_REGISTER.

uint8_t I2C_ReceiveData ( I2C_TypeDef * I2Cx )

Returns the most recent received data by the I2Cx peripheral.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
Return values:
The value of the received data.

Definition at line 583 of file stm32f10x_i2c.c.

References assert_param, I2C_TypeDef::DR, and IS_I2C_ALL_PERIPH.

Referenced by PhysicalAddressDiscovery(), and sEE_ReadBuffer().

void I2C_Send7bitAddress | ( | I2C_TypeDef * | I2Cx,
 |  | uint8_t | Address,
 |  | uint8_t | I2C_Direction
 | ) |  |

Transmits the address byte to select the slave device.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
Address,: specifies the slave address which will be transmitted
I2C_Direction,: specifies whether the I2C device will be a Transmitter or a Receiver. This parameter can be one of the following values

  • I2C_Direction_Transmitter: Transmitter mode
  • I2C_Direction_Receiver: Receiver mode
Return values:
None.

Definition at line 601 of file stm32f10x_i2c.c.

References Address, assert_param, I2C_TypeDef::DR, I2C_Direction_Transmitter, IS_I2C_ALL_PERIPH, IS_I2C_DIRECTION, OAR1_ADD0_Reset, and OAR1_ADD0_Set.

Referenced by I2C_ReadDataBuffer(), I2C_ReadDeviceRegister(), I2C_WriteDeviceRegister(), LM75_GetStatus(), LM75_ReadConfReg(), LM75_ReadReg(), LM75_ReadTemp(), LM75_ShutDown(), LM75_WriteConfReg(), LM75_WriteReg(), main(), PhysicalAddressDiscovery(), sEE_ReadBuffer(), sEE_WaitEepromStandbyState(), and sEE_WritePage().

void I2C_SendData | ( | I2C_TypeDef * | I2Cx,
 |  | uint8_t | Data
 | ) |  |

Sends a data byte through the I2Cx peripheral.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
Data,: Byte to be transmitted..
Return values:
None

Definition at line 570 of file stm32f10x_i2c.c.

References assert_param, Data, I2C_TypeDef::DR, and IS_I2C_ALL_PERIPH.

Referenced by I2C_ReadDataBuffer(), I2C_ReadDeviceRegister(), I2C_WriteDeviceRegister(), LM75_ReadConfReg(), LM75_ReadReg(), LM75_ReadTemp(), LM75_ShutDown(), LM75_WriteConfReg(), LM75_WriteReg(), PhysicalAddressDiscovery(), sEE_ReadBuffer(), and sEE_WritePage().

void I2C_SMBusAlertConfig | ( | I2C_TypeDef * | I2Cx,
 |  | uint16_t | I2C_SMBusAlert
 | ) |  |

Drives the SMBusAlert pin high or low for the specified I2C.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
I2C_SMBusAlert,: specifies SMBAlert pin level. This parameter can be one of the following values:

  • I2C_SMBusAlert_Low: SMBAlert pin driven low
  • I2C_SMBusAlert_High: SMBAlert pin driven high
Return values:
None

Definition at line 724 of file stm32f10x_i2c.c.

References assert_param, I2C_TypeDef::CR1, I2C_SMBusAlert_High, I2C_SMBusAlert_Low, IS_I2C_ALL_PERIPH, and IS_I2C_SMBUS_ALERT.

void I2C_SoftwareResetCmd | ( | I2C_TypeDef * | I2Cx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified I2C software reset.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
NewState,: new state of the I2C software reset. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 658 of file stm32f10x_i2c.c.

References assert_param, I2C_TypeDef::CR1, CR1_SWRST_Reset, CR1_SWRST_Set, DISABLE, IS_FUNCTIONAL_STATE, and IS_I2C_ALL_PERIPH.

void I2C_StretchClockCmd | ( | I2C_TypeDef * | I2Cx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified I2C Clock stretching.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
NewState,: new state of the I2Cx Clock stretching. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 864 of file stm32f10x_i2c.c.

References assert_param, I2C_TypeDef::CR1, CR1_NOSTRETCH_Reset, CR1_NOSTRETCH_Set, DISABLE, IS_FUNCTIONAL_STATE, and IS_I2C_ALL_PERIPH.

void I2C_StructInit ( I2C_InitTypeDef * I2C_InitStruct )

Fills each I2C_InitStruct member with its default value.

Parameters:
I2C_InitStruct,: pointer to an I2C_InitTypeDef structure which will be initialized.
Return values:
None

Definition at line 298 of file stm32f10x_i2c.c.

References I2C_InitTypeDef::I2C_Ack, I2C_Ack_Disable, I2C_InitTypeDef::I2C_AcknowledgedAddress, I2C_AcknowledgedAddress_7bit, I2C_InitTypeDef::I2C_ClockSpeed, I2C_InitTypeDef::I2C_DutyCycle, I2C_DutyCycle_2, I2C_InitTypeDef::I2C_Mode, I2C_Mode_I2C, and I2C_InitTypeDef::I2C_OwnAddress1.

void I2C_TransmitPEC | ( | I2C_TypeDef * | I2Cx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified I2C PEC transfer.

Parameters:
I2Cx,: where x can be 1 or 2 to select the I2C peripheral.
NewState,: new state of the I2C PEC transmission. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 748 of file stm32f10x_i2c.c.

References assert_param, I2C_TypeDef::CR1, CR1_PEC_Reset, CR1_PEC_Set, DISABLE, IS_FUNCTIONAL_STATE, and IS_I2C_ALL_PERIPH.


STM32F10x Standard Peripherals Firmware Library: IWDG_Exported_Types

IWDG_Exported_Types

IWDG


STM32F10x Standard Peripherals Firmware Library: IWDG_WriteAccess

Defines

IWDG_WriteAccess

IWDG_Exported_Constants

Defines

#define | IS_IWDG_WRITE_ACCESS(ACCESS)
#define | IWDG_WriteAccess_Disable ((uint16_t)0x0000)
#define | IWDG_WriteAccess_Enable ((uint16_t)0x5555)

Define Documentation

#define IS_IWDG_WRITE_ACCESS ( ACCESS )
Value:
(((ACCESS) == IWDG_WriteAccess_Enable) || \
                                      ((ACCESS) == IWDG_WriteAccess_Disable))

Definition at line 60 of file stm32f10x_iwdg.h.

Referenced by IWDG_WriteAccessCmd().

#define IWDG_WriteAccess_Disable ((uint16_t)0x0000)

Definition at line 59 of file stm32f10x_iwdg.h.

#define IWDG_WriteAccess_Enable ((uint16_t)0x5555)

Definition at line 58 of file stm32f10x_iwdg.h.

Referenced by main().


STM32F10x Standard Peripherals Firmware Library: IWDG_prescaler

Defines

IWDG_prescaler

IWDG_Exported_Constants

Defines

#define | IS_IWDG_PRESCALER(PRESCALER)
#define | IWDG_Prescaler_128 ((uint8_t)0x05)
#define | IWDG_Prescaler_16 ((uint8_t)0x02)
#define | IWDG_Prescaler_256 ((uint8_t)0x06)
#define | IWDG_Prescaler_32 ((uint8_t)0x03)
#define | IWDG_Prescaler_4 ((uint8_t)0x00)
#define | IWDG_Prescaler_64 ((uint8_t)0x04)
#define | IWDG_Prescaler_8 ((uint8_t)0x01)

Define Documentation

#define IS_IWDG_PRESCALER ( PRESCALER )
Value:
(((PRESCALER) == IWDG_Prescaler_4)  || \
                                      ((PRESCALER) == IWDG_Prescaler_8)  || \
                                      ((PRESCALER) == IWDG_Prescaler_16) || \
                                      ((PRESCALER) == IWDG_Prescaler_32) || \
                                      ((PRESCALER) == IWDG_Prescaler_64) || \
                                      ((PRESCALER) == IWDG_Prescaler_128)|| \
                                      ((PRESCALER) == IWDG_Prescaler_256))

Definition at line 77 of file stm32f10x_iwdg.h.

Referenced by IWDG_SetPrescaler().

#define IWDG_Prescaler_128 ((uint8_t)0x05)

Definition at line 75 of file stm32f10x_iwdg.h.

#define IWDG_Prescaler_16 ((uint8_t)0x02)

Definition at line 72 of file stm32f10x_iwdg.h.

#define IWDG_Prescaler_256 ((uint8_t)0x06)

Definition at line 76 of file stm32f10x_iwdg.h.

#define IWDG_Prescaler_32 ((uint8_t)0x03)

Definition at line 73 of file stm32f10x_iwdg.h.

Referenced by main().

#define IWDG_Prescaler_4 ((uint8_t)0x00)

Definition at line 70 of file stm32f10x_iwdg.h.

#define IWDG_Prescaler_64 ((uint8_t)0x04)

Definition at line 74 of file stm32f10x_iwdg.h.

#define IWDG_Prescaler_8 ((uint8_t)0x01)

Definition at line 71 of file stm32f10x_iwdg.h.


STM32F10x Standard Peripherals Firmware Library: IWDG_Flag

Defines

IWDG_Flag

IWDG_Exported_Constants

Defines

#define | IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU))
#define | IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)
#define | IWDG_FLAG_PVU ((uint16_t)0x0001)
#define | IWDG_FLAG_RVU ((uint16_t)0x0002)

Define Documentation

#define IS_IWDG_FLAG ( FLAG ) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU))

Definition at line 94 of file stm32f10x_iwdg.h.

Referenced by IWDG_GetFlagStatus().

#define IS_IWDG_RELOAD ( RELOAD ) ((RELOAD) <= 0xFFF)

Definition at line 95 of file stm32f10x_iwdg.h.

Referenced by IWDG_SetReload().

#define IWDG_FLAG_PVU ((uint16_t)0x0001)

Definition at line 92 of file stm32f10x_iwdg.h.

#define IWDG_FLAG_RVU ((uint16_t)0x0002)

Definition at line 93 of file stm32f10x_iwdg.h.


STM32F10x Standard Peripherals Firmware Library: IWDG_Exported_Macros

IWDG_Exported_Macros

IWDG


STM32F10x Standard Peripherals Firmware Library: IWDG_Exported_Functions

Functions

IWDG_Exported_Functions

IWDG

Functions

void | IWDG_Enable (void)
Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled).
FlagStatus | IWDG_GetFlagStatus (uint16_t IWDG_FLAG)
Checks whether the specified IWDG flag is set or not.
void | IWDG_ReloadCounter (void)
Reloads IWDG counter with value defined in the reload register (write access to IWDG_PR and IWDG_RLR registers disabled).
void | IWDG_SetPrescaler (uint8_t IWDG_Prescaler)
Sets IWDG Prescaler value.
void | IWDG_SetReload (uint16_t Reload)
Sets IWDG Reload value.
void | IWDG_WriteAccessCmd (uint16_t IWDG_WriteAccess)
Enables or disables write access to IWDG_PR and IWDG_RLR registers.

Function Documentation

void IWDG_Enable ( void )

Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled).

Parameters:
None
Return values:
None

Definition at line 148 of file stm32f10x_iwdg.c.

References IWDG, and KR_KEY_Enable.

Referenced by main().

FlagStatus IWDG_GetFlagStatus ( uint16_t IWDG_FLAG )

Checks whether the specified IWDG flag is set or not.

Parameters:
IWDG_FLAG,: specifies the flag to check. This parameter can be one of the following values:

  • IWDG_FLAG_PVU: Prescaler Value Update on going
  • IWDG_FLAG_RVU: Reload Value Update on going
Return values:
The new state of IWDG_FLAG (SET or RESET).

Definition at line 161 of file stm32f10x_iwdg.c.

References assert_param, IS_IWDG_FLAG, IWDG, RESET, and SET.

void IWDG_ReloadCounter ( void )

Reloads IWDG counter with value defined in the reload register (write access to IWDG_PR and IWDG_RLR registers disabled).

Parameters:
None
Return values:
None

Definition at line 138 of file stm32f10x_iwdg.c.

References IWDG, and KR_KEY_Reload.

Referenced by main().

void IWDG_SetPrescaler ( uint8_t IWDG_Prescaler )

Sets IWDG Prescaler value.

Parameters:
IWDG_Prescaler,: specifies the IWDG Prescaler value. This parameter can be one of the following values:

  • IWDG_Prescaler_4: IWDG prescaler set to 4
  • IWDG_Prescaler_8: IWDG prescaler set to 8
  • IWDG_Prescaler_16: IWDG prescaler set to 16
  • IWDG_Prescaler_32: IWDG prescaler set to 32
  • IWDG_Prescaler_64: IWDG prescaler set to 64
  • IWDG_Prescaler_128: IWDG prescaler set to 128
  • IWDG_Prescaler_256: IWDG prescaler set to 256
Return values:
None

Definition at line 112 of file stm32f10x_iwdg.c.

References assert_param, IS_IWDG_PRESCALER, and IWDG.

Referenced by main().

void IWDG_SetReload ( uint16_t Reload )

Sets IWDG Reload value.

Parameters:
Reload,: specifies the IWDG Reload value. This parameter must be a number between 0 and 0x0FFF.
Return values:
None

Definition at line 125 of file stm32f10x_iwdg.c.

References assert_param, IS_IWDG_RELOAD, and IWDG.

Referenced by main().

void IWDG_WriteAccessCmd ( uint16_t IWDG_WriteAccess )

Enables or disables write access to IWDG_PR and IWDG_RLR registers.

Parameters:
IWDG_WriteAccess,: new state of write access to IWDG_PR and IWDG_RLR registers. This parameter can be one of the following values:

  • IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers
  • IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers
Return values:
None

Definition at line 92 of file stm32f10x_iwdg.c.

References assert_param, IS_IWDG_WRITE_ACCESS, and IWDG.

Referenced by main().


STM32F10x Standard Peripherals Firmware Library: IWDG_Private_TypesDefinitions

IWDG_Private_TypesDefinitions

IWDG


STM32F10x Standard Peripherals Firmware Library: IWDG_Private_Defines

Defines

IWDG_Private_Defines

IWDG

Defines

#define | KR_KEY_Enable ((uint16_t)0xCCCC)
#define | KR_KEY_Reload ((uint16_t)0xAAAA)

Define Documentation

#define KR_KEY_Enable ((uint16_t)0xCCCC)

Definition at line 50 of file stm32f10x_iwdg.c.

Referenced by IWDG_Enable().

#define KR_KEY_Reload ((uint16_t)0xAAAA)

Definition at line 49 of file stm32f10x_iwdg.c.

Referenced by IWDG_ReloadCounter().


STM32F10x Standard Peripherals Firmware Library: IWDG_Private_Macros

IWDG_Private_Macros

IWDG


STM32F10x Standard Peripherals Firmware Library: IWDG_Private_Variables

IWDG_Private_Variables

IWDG


STM32F10x Standard Peripherals Firmware Library: IWDG_Private_FunctionPrototypes

IWDG_Private_FunctionPrototypes

IWDG


STM32F10x Standard Peripherals Firmware Library: IWDG_Private_Functions

Functions

IWDG_Private_Functions

IWDG

Functions

void | IWDG_Enable (void)
Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled).
FlagStatus | IWDG_GetFlagStatus (uint16_t IWDG_FLAG)
Checks whether the specified IWDG flag is set or not.
void | IWDG_ReloadCounter (void)
Reloads IWDG counter with value defined in the reload register (write access to IWDG_PR and IWDG_RLR registers disabled).
void | IWDG_SetPrescaler (uint8_t IWDG_Prescaler)
Sets IWDG Prescaler value.
void | IWDG_SetReload (uint16_t Reload)
Sets IWDG Reload value.
void | IWDG_WriteAccessCmd (uint16_t IWDG_WriteAccess)
Enables or disables write access to IWDG_PR and IWDG_RLR registers.

Function Documentation

void IWDG_Enable ( void )

Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled).

Parameters:
None
Return values:
None

Definition at line 148 of file stm32f10x_iwdg.c.

References IWDG, and KR_KEY_Enable.

Referenced by main().

FlagStatus IWDG_GetFlagStatus ( uint16_t IWDG_FLAG )

Checks whether the specified IWDG flag is set or not.

Parameters:
IWDG_FLAG,: specifies the flag to check. This parameter can be one of the following values:

  • IWDG_FLAG_PVU: Prescaler Value Update on going
  • IWDG_FLAG_RVU: Reload Value Update on going
Return values:
The new state of IWDG_FLAG (SET or RESET).

Definition at line 161 of file stm32f10x_iwdg.c.

References assert_param, IS_IWDG_FLAG, IWDG, RESET, and SET.

void IWDG_ReloadCounter ( void )

Reloads IWDG counter with value defined in the reload register (write access to IWDG_PR and IWDG_RLR registers disabled).

Parameters:
None
Return values:
None

Definition at line 138 of file stm32f10x_iwdg.c.

References IWDG, and KR_KEY_Reload.

Referenced by main().

void IWDG_SetPrescaler ( uint8_t IWDG_Prescaler )

Sets IWDG Prescaler value.

Parameters:
IWDG_Prescaler,: specifies the IWDG Prescaler value. This parameter can be one of the following values:

  • IWDG_Prescaler_4: IWDG prescaler set to 4
  • IWDG_Prescaler_8: IWDG prescaler set to 8
  • IWDG_Prescaler_16: IWDG prescaler set to 16
  • IWDG_Prescaler_32: IWDG prescaler set to 32
  • IWDG_Prescaler_64: IWDG prescaler set to 64
  • IWDG_Prescaler_128: IWDG prescaler set to 128
  • IWDG_Prescaler_256: IWDG prescaler set to 256
Return values:
None

Definition at line 112 of file stm32f10x_iwdg.c.

References assert_param, IS_IWDG_PRESCALER, and IWDG.

Referenced by main().

void IWDG_SetReload ( uint16_t Reload )

Sets IWDG Reload value.

Parameters:
Reload,: specifies the IWDG Reload value. This parameter must be a number between 0 and 0x0FFF.
Return values:
None

Definition at line 125 of file stm32f10x_iwdg.c.

References assert_param, IS_IWDG_RELOAD, and IWDG.

Referenced by main().

void IWDG_WriteAccessCmd ( uint16_t IWDG_WriteAccess )

Enables or disables write access to IWDG_PR and IWDG_RLR registers.

Parameters:
IWDG_WriteAccess,: new state of write access to IWDG_PR and IWDG_RLR registers. This parameter can be one of the following values:

  • IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers
  • IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers
Return values:
None

Definition at line 92 of file stm32f10x_iwdg.c.

References assert_param, IS_IWDG_WRITE_ACCESS, and IWDG.

Referenced by main().


STM32F10x Standard Peripherals Firmware Library: PWR_Exported_Types

PWR_Exported_Types

PWR


STM32F10x Standard Peripherals Firmware Library: PVD_detection_level

Defines

PVD_detection_level

PWR_Exported_Constants

Defines

#define | IS_PWR_PVD_LEVEL(LEVEL)
#define | PWR_PVDLevel_2V2 ((uint32_t)0x00000000)
#define | PWR_PVDLevel_2V3 ((uint32_t)0x00000020)
#define | PWR_PVDLevel_2V4 ((uint32_t)0x00000040)
#define | PWR_PVDLevel_2V5 ((uint32_t)0x00000060)
#define | PWR_PVDLevel_2V6 ((uint32_t)0x00000080)
#define | PWR_PVDLevel_2V7 ((uint32_t)0x000000A0)
#define | PWR_PVDLevel_2V8 ((uint32_t)0x000000C0)
#define | PWR_PVDLevel_2V9 ((uint32_t)0x000000E0)

Define Documentation

#define IS_PWR_PVD_LEVEL ( LEVEL )
Value:
(((LEVEL) == PWR_PVDLevel_2V2) || ((LEVEL) == PWR_PVDLevel_2V3)|| \
                                 ((LEVEL) == PWR_PVDLevel_2V4) || ((LEVEL) == PWR_PVDLevel_2V5)|| \
                                 ((LEVEL) == PWR_PVDLevel_2V6) || ((LEVEL) == PWR_PVDLevel_2V7)|| \
                                 ((LEVEL) == PWR_PVDLevel_2V8) || ((LEVEL) == PWR_PVDLevel_2V9))

Definition at line 66 of file stm32f10x_pwr.h.

Referenced by PWR_PVDLevelConfig().

#define PWR_PVDLevel_2V2 ((uint32_t)0x00000000)

Definition at line 58 of file stm32f10x_pwr.h.

#define PWR_PVDLevel_2V3 ((uint32_t)0x00000020)

Definition at line 59 of file stm32f10x_pwr.h.

#define PWR_PVDLevel_2V4 ((uint32_t)0x00000040)

Definition at line 60 of file stm32f10x_pwr.h.

#define PWR_PVDLevel_2V5 ((uint32_t)0x00000060)

Definition at line 61 of file stm32f10x_pwr.h.

#define PWR_PVDLevel_2V6 ((uint32_t)0x00000080)

Definition at line 62 of file stm32f10x_pwr.h.

#define PWR_PVDLevel_2V7 ((uint32_t)0x000000A0)

Definition at line 63 of file stm32f10x_pwr.h.

#define PWR_PVDLevel_2V8 ((uint32_t)0x000000C0)

Definition at line 64 of file stm32f10x_pwr.h.

#define PWR_PVDLevel_2V9 ((uint32_t)0x000000E0)

Definition at line 65 of file stm32f10x_pwr.h.

Referenced by main().


STM32F10x Standard Peripherals Firmware Library: Regulator_state_is_STOP_mode

Defines

Regulator_state_is_STOP_mode

PWR_Exported_Constants

Defines

#define | IS_PWR_REGULATOR(REGULATOR)
#define | PWR_Regulator_LowPower ((uint32_t)0x00000001)
#define | PWR_Regulator_ON ((uint32_t)0x00000000)

Define Documentation

#define IS_PWR_REGULATOR ( REGULATOR )
Value:
(((REGULATOR) == PWR_Regulator_ON) || \
                                     ((REGULATOR) == PWR_Regulator_LowPower))

Definition at line 80 of file stm32f10x_pwr.h.

Referenced by PWR_EnterSTOPMode().

#define PWR_Regulator_LowPower ((uint32_t)0x00000001)

Definition at line 79 of file stm32f10x_pwr.h.

Referenced by main().

#define PWR_Regulator_ON ((uint32_t)0x00000000)

Definition at line 78 of file stm32f10x_pwr.h.

Referenced by HDMI_CEC_CommandCallBack().


STM32F10x Standard Peripherals Firmware Library: STOP_mode_entry

Defines

STOP_mode_entry

PWR_Exported_Constants

Defines

#define | IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE))
#define | PWR_STOPEntry_WFE ((uint8_t)0x02)
#define | PWR_STOPEntry_WFI ((uint8_t)0x01)

Define Documentation

#define IS_PWR_STOP_ENTRY ( ENTRY ) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE))

Definition at line 92 of file stm32f10x_pwr.h.

Referenced by PWR_EnterSTOPMode().

#define PWR_STOPEntry_WFE ((uint8_t)0x02)

Definition at line 91 of file stm32f10x_pwr.h.

#define PWR_STOPEntry_WFI ((uint8_t)0x01)

Definition at line 90 of file stm32f10x_pwr.h.

Referenced by HDMI_CEC_CommandCallBack(), main(), and PWR_EnterSTOPMode().


STM32F10x Standard Peripherals Firmware Library: PWR_Flag

Defines

PWR_Flag

PWR_Exported_Constants

Defines

#define | IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB))
#define | IS_PWR_GET_FLAG(FLAG)
#define | PWR_FLAG_PVDO ((uint32_t)0x00000004)
#define | PWR_FLAG_SB ((uint32_t)0x00000002)
#define | PWR_FLAG_WU ((uint32_t)0x00000001)

Define Documentation

#define IS_PWR_CLEAR_FLAG ( FLAG ) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB))

Definition at line 108 of file stm32f10x_pwr.h.

Referenced by PWR_ClearFlag().

#define IS_PWR_GET_FLAG ( FLAG )
Value:
(((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \
                               ((FLAG) == PWR_FLAG_PVDO))

Definition at line 105 of file stm32f10x_pwr.h.

Referenced by PWR_GetFlagStatus().

#define PWR_FLAG_PVDO ((uint32_t)0x00000004)

Definition at line 104 of file stm32f10x_pwr.h.

#define PWR_FLAG_SB ((uint32_t)0x00000002)

Definition at line 103 of file stm32f10x_pwr.h.

Referenced by RTC_Configuration().

#define PWR_FLAG_WU ((uint32_t)0x00000001)

Definition at line 102 of file stm32f10x_pwr.h.

Referenced by RTCAlarm_IRQHandler().


STM32F10x Standard Peripherals Firmware Library: PWR_Exported_Macros

PWR_Exported_Macros

PWR


STM32F10x Standard Peripherals Firmware Library: PWR_Exported_Functions

Functions

PWR_Exported_Functions

PWR

Functions

void | PWR_BackupAccessCmd (FunctionalState NewState)
Enables or disables access to the RTC and backup registers.
void | PWR_ClearFlag (uint32_t PWR_FLAG)
Clears the PWR's pending flags.
void | PWR_DeInit (void)
Deinitializes the PWR peripheral registers to their default reset values.
void | PWR_EnterSTANDBYMode (void)
Enters STANDBY mode.
void | PWR_EnterSTOPMode (uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
Enters STOP mode.
FlagStatus | PWR_GetFlagStatus (uint32_t PWR_FLAG)
Checks whether the specified PWR flag is set or not.
void | PWR_PVDCmd (FunctionalState NewState)
Enables or disables the Power Voltage Detector(PVD).
void | PWR_PVDLevelConfig (uint32_t PWR_PVDLevel)
Configures the voltage threshold detected by the Power Voltage Detector(PVD).
void | PWR_WakeUpPinCmd (FunctionalState NewState)
Enables or disables the WakeUp Pin functionality.

Function Documentation

void PWR_BackupAccessCmd ( FunctionalState NewState )

Enables or disables access to the RTC and backup registers.

Parameters:
NewState,: new state of the access to the RTC and backup registers. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 124 of file stm32f10x_pwr.c.

References assert_param, CR_DBP_BB, and IS_FUNCTIONAL_STATE.

Referenced by main().

void PWR_ClearFlag ( uint32_t PWR_FLAG )

Clears the PWR's pending flags.

Parameters:
PWR_FLAG,: specifies the flag to clear. This parameter can be one of the following values:

  • PWR_FLAG_WU: Wake Up flag
  • PWR_FLAG_SB: StandBy flag
Return values:
None

Definition at line 287 of file stm32f10x_pwr.c.

References assert_param, IS_PWR_CLEAR_FLAG, and PWR.

Referenced by RTC_Configuration(), and RTCAlarm_IRQHandler().

void PWR_DeInit ( void )

Deinitializes the PWR peripheral registers to their default reset values.

Parameters:
None
Return values:
None

Definition at line 112 of file stm32f10x_pwr.c.

References DISABLE, ENABLE, RCC_APB1Periph_PWR, and RCC_APB1PeriphResetCmd().

void PWR_EnterSTANDBYMode ( void )

Enters STANDBY mode.

Parameters:
None
Return values:
None

Definition at line 236 of file stm32f10x_pwr.c.

References PWR, PWR_CR_CWUF, PWR_CR_PDDS, and SCB_SCR_SLEEPDEEP.

Referenced by EXTI9_5_IRQHandler().

void PWR_EnterSTOPMode | ( | uint32_t | PWR_Regulator,
 |  | uint8_t | PWR_STOPEntry
 | ) |  |

Enters STOP mode.

Parameters:
PWR_Regulator,: specifies the regulator state in STOP mode. This parameter can be one of the following values:

  • PWR_Regulator_ON: STOP mode with regulator ON
  • PWR_Regulator_LowPower: STOP mode with regulator in low power mode
PWR_STOPEntry,: specifies if STOP mode in entered with WFI or WFE instruction. This parameter can be one of the following values:

  • PWR_STOPEntry_WFI: enter STOP mode with WFI instruction
  • PWR_STOPEntry_WFE: enter STOP mode with WFE instruction
Return values:
None

Definition at line 197 of file stm32f10x_pwr.c.

References assert_param, CR_DS_MASK, IS_PWR_REGULATOR, IS_PWR_STOP_ENTRY, PWR, PWR_STOPEntry_WFI, and SCB_SCR_SLEEPDEEP.

Referenced by HDMI_CEC_CommandCallBack(), and main().

FlagStatus PWR_GetFlagStatus ( uint32_t PWR_FLAG )

Checks whether the specified PWR flag is set or not.

Parameters:
PWR_FLAG,: specifies the flag to check. This parameter can be one of the following values:

  • PWR_FLAG_WU: Wake Up flag
  • PWR_FLAG_SB: StandBy flag
  • PWR_FLAG_PVDO: PVD Output
Return values:
The new state of PWR_FLAG (SET or RESET).

Definition at line 261 of file stm32f10x_pwr.c.

References assert_param, IS_PWR_GET_FLAG, PWR, RESET, and SET.

Referenced by RTC_Configuration(), and RTCAlarm_IRQHandler().

void PWR_PVDCmd ( FunctionalState NewState )

Enables or disables the Power Voltage Detector(PVD).

Parameters:
NewState,: new state of the PVD. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 137 of file stm32f10x_pwr.c.

References assert_param, CR_PVDE_BB, and IS_FUNCTIONAL_STATE.

Referenced by main().

void PWR_PVDLevelConfig ( uint32_t PWR_PVDLevel )

Configures the voltage threshold detected by the Power Voltage Detector(PVD).

Parameters:
PWR_PVDLevel,: specifies the PVD detection level This parameter can be one of the following values:

  • PWR_PVDLevel_2V2: PVD detection level set to 2.2V
  • PWR_PVDLevel_2V3: PVD detection level set to 2.3V
  • PWR_PVDLevel_2V4: PVD detection level set to 2.4V
  • PWR_PVDLevel_2V5: PVD detection level set to 2.5V
  • PWR_PVDLevel_2V6: PVD detection level set to 2.6V
  • PWR_PVDLevel_2V7: PVD detection level set to 2.7V
  • PWR_PVDLevel_2V8: PVD detection level set to 2.8V
  • PWR_PVDLevel_2V9: PVD detection level set to 2.9V
Return values:
None

Definition at line 158 of file stm32f10x_pwr.c.

References assert_param, CR_PLS_MASK, IS_PWR_PVD_LEVEL, and PWR.

Referenced by main().

void PWR_WakeUpPinCmd ( FunctionalState NewState )

Enables or disables the WakeUp Pin functionality.

Parameters:
NewState,: new state of the WakeUp Pin functionality. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 178 of file stm32f10x_pwr.c.

References assert_param, CSR_EWUP_BB, and IS_FUNCTIONAL_STATE.

Referenced by main().


STM32F10x Standard Peripherals Firmware Library: PWR_Private_TypesDefinitions

PWR_Private_TypesDefinitions

PWR


STM32F10x Standard Peripherals Firmware Library: PWR_Private_Defines

Defines

PWR_Private_Defines

PWR

Defines

#define | CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))
#define | CR_DS_MASK ((uint32_t)0xFFFFFFFC)
#define | CR_OFFSET (PWR_OFFSET + 0x00)
#define | CR_PLS_MASK ((uint32_t)0xFFFFFF1F)
#define | CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))
#define | CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))
#define | CSR_OFFSET (PWR_OFFSET + 0x04)
#define | DBP_BitNumber 0x08
#define | EWUP_BitNumber 0x08
#define | PVDE_BitNumber 0x04
#define | PWR_OFFSET (PWR_BASE - PERIPH_BASE)

Define Documentation

#define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))

Definition at line 55 of file stm32f10x_pwr.c.

Referenced by PWR_BackupAccessCmd().

#define CR_DS_MASK ((uint32_t)0xFFFFFFFC)

Definition at line 71 of file stm32f10x_pwr.c.

Referenced by PWR_EnterSTOPMode().

#define CR_OFFSET (PWR_OFFSET + 0x00)

Definition at line 53 of file stm32f10x_pwr.c.

#define CR_PLS_MASK ((uint32_t)0xFFFFFF1F)

Definition at line 72 of file stm32f10x_pwr.c.

Referenced by PWR_PVDLevelConfig().

#define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))

Definition at line 59 of file stm32f10x_pwr.c.

Referenced by PWR_PVDCmd().

#define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))

Definition at line 66 of file stm32f10x_pwr.c.

Referenced by PWR_WakeUpPinCmd().

#define CSR_OFFSET (PWR_OFFSET + 0x04)

Definition at line 64 of file stm32f10x_pwr.c.

#define DBP_BitNumber 0x08

Definition at line 54 of file stm32f10x_pwr.c.

#define EWUP_BitNumber 0x08

Definition at line 65 of file stm32f10x_pwr.c.

#define PVDE_BitNumber 0x04

Definition at line 58 of file stm32f10x_pwr.c.

#define PWR_OFFSET (PWR_BASE - PERIPH_BASE)

Definition at line 48 of file stm32f10x_pwr.c.


STM32F10x Standard Peripherals Firmware Library: PWR_Private_Macros

PWR_Private_Macros

PWR


STM32F10x Standard Peripherals Firmware Library: PWR_Private_Variables

PWR_Private_Variables

PWR


STM32F10x Standard Peripherals Firmware Library: PWR_Private_FunctionPrototypes

PWR_Private_FunctionPrototypes

PWR


STM32F10x Standard Peripherals Firmware Library: PWR_Private_Functions

Functions

PWR_Private_Functions

PWR

Functions

void | PWR_BackupAccessCmd (FunctionalState NewState)
Enables or disables access to the RTC and backup registers.
void | PWR_ClearFlag (uint32_t PWR_FLAG)
Clears the PWR's pending flags.
void | PWR_DeInit (void)
Deinitializes the PWR peripheral registers to their default reset values.
void | PWR_EnterSTANDBYMode (void)
Enters STANDBY mode.
void | PWR_EnterSTOPMode (uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
Enters STOP mode.
FlagStatus | PWR_GetFlagStatus (uint32_t PWR_FLAG)
Checks whether the specified PWR flag is set or not.
void | PWR_PVDCmd (FunctionalState NewState)
Enables or disables the Power Voltage Detector(PVD).
void | PWR_PVDLevelConfig (uint32_t PWR_PVDLevel)
Configures the voltage threshold detected by the Power Voltage Detector(PVD).
void | PWR_WakeUpPinCmd (FunctionalState NewState)
Enables or disables the WakeUp Pin functionality.

Function Documentation

void PWR_BackupAccessCmd ( FunctionalState NewState )

Enables or disables access to the RTC and backup registers.

Parameters:
NewState,: new state of the access to the RTC and backup registers. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 124 of file stm32f10x_pwr.c.

References assert_param, CR_DBP_BB, and IS_FUNCTIONAL_STATE.

Referenced by main().

void PWR_ClearFlag ( uint32_t PWR_FLAG )

Clears the PWR's pending flags.

Parameters:
PWR_FLAG,: specifies the flag to clear. This parameter can be one of the following values:

  • PWR_FLAG_WU: Wake Up flag
  • PWR_FLAG_SB: StandBy flag
Return values:
None

Definition at line 287 of file stm32f10x_pwr.c.

References assert_param, IS_PWR_CLEAR_FLAG, and PWR.

Referenced by RTC_Configuration(), and RTCAlarm_IRQHandler().

void PWR_DeInit ( void )

Deinitializes the PWR peripheral registers to their default reset values.

Parameters:
None
Return values:
None

Definition at line 112 of file stm32f10x_pwr.c.

References DISABLE, ENABLE, RCC_APB1Periph_PWR, and RCC_APB1PeriphResetCmd().

void PWR_EnterSTANDBYMode ( void )

Enters STANDBY mode.

Parameters:
None
Return values:
None

Definition at line 236 of file stm32f10x_pwr.c.

References PWR, PWR_CR_CWUF, PWR_CR_PDDS, and SCB_SCR_SLEEPDEEP.

Referenced by EXTI9_5_IRQHandler().

void PWR_EnterSTOPMode | ( | uint32_t | PWR_Regulator,
 |  | uint8_t | PWR_STOPEntry
 | ) |  |

Enters STOP mode.

Parameters:
PWR_Regulator,: specifies the regulator state in STOP mode. This parameter can be one of the following values:

  • PWR_Regulator_ON: STOP mode with regulator ON
  • PWR_Regulator_LowPower: STOP mode with regulator in low power mode
PWR_STOPEntry,: specifies if STOP mode in entered with WFI or WFE instruction. This parameter can be one of the following values:

  • PWR_STOPEntry_WFI: enter STOP mode with WFI instruction
  • PWR_STOPEntry_WFE: enter STOP mode with WFE instruction
Return values:
None

Definition at line 197 of file stm32f10x_pwr.c.

References assert_param, CR_DS_MASK, IS_PWR_REGULATOR, IS_PWR_STOP_ENTRY, PWR, PWR_STOPEntry_WFI, and SCB_SCR_SLEEPDEEP.

Referenced by HDMI_CEC_CommandCallBack(), and main().

FlagStatus PWR_GetFlagStatus ( uint32_t PWR_FLAG )

Checks whether the specified PWR flag is set or not.

Parameters:
PWR_FLAG,: specifies the flag to check. This parameter can be one of the following values:

  • PWR_FLAG_WU: Wake Up flag
  • PWR_FLAG_SB: StandBy flag
  • PWR_FLAG_PVDO: PVD Output
Return values:
The new state of PWR_FLAG (SET or RESET).

Definition at line 261 of file stm32f10x_pwr.c.

References assert_param, IS_PWR_GET_FLAG, PWR, RESET, and SET.

Referenced by RTC_Configuration(), and RTCAlarm_IRQHandler().

void PWR_PVDCmd ( FunctionalState NewState )

Enables or disables the Power Voltage Detector(PVD).

Parameters:
NewState,: new state of the PVD. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 137 of file stm32f10x_pwr.c.

References assert_param, CR_PVDE_BB, and IS_FUNCTIONAL_STATE.

Referenced by main().

void PWR_PVDLevelConfig ( uint32_t PWR_PVDLevel )

Configures the voltage threshold detected by the Power Voltage Detector(PVD).

Parameters:
PWR_PVDLevel,: specifies the PVD detection level This parameter can be one of the following values:

  • PWR_PVDLevel_2V2: PVD detection level set to 2.2V
  • PWR_PVDLevel_2V3: PVD detection level set to 2.3V
  • PWR_PVDLevel_2V4: PVD detection level set to 2.4V
  • PWR_PVDLevel_2V5: PVD detection level set to 2.5V
  • PWR_PVDLevel_2V6: PVD detection level set to 2.6V
  • PWR_PVDLevel_2V7: PVD detection level set to 2.7V
  • PWR_PVDLevel_2V8: PVD detection level set to 2.8V
  • PWR_PVDLevel_2V9: PVD detection level set to 2.9V
Return values:
None

Definition at line 158 of file stm32f10x_pwr.c.

References assert_param, CR_PLS_MASK, IS_PWR_PVD_LEVEL, and PWR.

Referenced by main().

void PWR_WakeUpPinCmd ( FunctionalState NewState )

Enables or disables the WakeUp Pin functionality.

Parameters:
NewState,: new state of the WakeUp Pin functionality. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 178 of file stm32f10x_pwr.c.

References assert_param, CSR_EWUP_BB, and IS_FUNCTIONAL_STATE.

Referenced by main().


STM32F10x Standard Peripherals Firmware Library: RCC_ClocksTypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

RCC_ClocksTypeDef Struct Reference
RCC_Exported_Types

#include <stm32f10x_rcc.h>

Data Fields

uint32_t | ADCCLK_Frequency
uint32_t | HCLK_Frequency
uint32_t | PCLK1_Frequency
uint32_t | PCLK2_Frequency
uint32_t | SYSCLK_Frequency

Detailed Description

Definition at line 46 of file stm32f10x_rcc.h.

Field Documentation

uint32_t RCC_ClocksTypeDef::ADCCLK_Frequency

returns ADCCLK clock frequency expressed in Hz

Definition at line 52 of file stm32f10x_rcc.h.

Referenced by RCC_GetClocksFreq().

uint32_t RCC_ClocksTypeDef::HCLK_Frequency

returns HCLK clock frequency expressed in Hz

Definition at line 49 of file stm32f10x_rcc.h.

Referenced by main(), and RCC_GetClocksFreq().

uint32_t RCC_ClocksTypeDef::PCLK1_Frequency

returns PCLK1 clock frequency expressed in Hz

Definition at line 50 of file stm32f10x_rcc.h.

Referenced by I2C_Init(), main(), RCC_GetClocksFreq(), and USART_Init().

uint32_t RCC_ClocksTypeDef::PCLK2_Frequency

returns PCLK2 clock frequency expressed in Hz

Definition at line 51 of file stm32f10x_rcc.h.

Referenced by RCC_GetClocksFreq(), and USART_Init().

uint32_t RCC_ClocksTypeDef::SYSCLK_Frequency

returns SYSCLK clock frequency expressed in Hz

Definition at line 48 of file stm32f10x_rcc.h.

Referenced by I2S_Init(), and RCC_GetClocksFreq().

The documentation for this struct was generated from the following file:
  • stm32f10x_rcc.h


STM32F10x Standard Peripherals Firmware Library: HSE_configuration

Defines

HSE_configuration

RCC_Exported_Constants

Defines

#define | IS_RCC_HSE(HSE)
#define | RCC_HSE_Bypass ((uint32_t)0x00040000)
#define | RCC_HSE_OFF ((uint32_t)0x00000000)
#define | RCC_HSE_ON ((uint32_t)0x00010000)

Define Documentation

#define IS_RCC_HSE ( HSE )
Value:
(((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
                         ((HSE) == RCC_HSE_Bypass))

Definition at line 70 of file stm32f10x_rcc.h.

Referenced by RCC_HSEConfig().

#define RCC_HSE_Bypass ((uint32_t)0x00040000)

Definition at line 69 of file stm32f10x_rcc.h.

Referenced by RCC_HSEConfig().

#define RCC_HSE_OFF ((uint32_t)0x00000000)

Definition at line 67 of file stm32f10x_rcc.h.

#define RCC_HSE_ON ((uint32_t)0x00010000)

Definition at line 68 of file stm32f10x_rcc.h.

Referenced by NMI_Handler(), RCC_HSEConfig(), SetSysClockTo24(), SetSysClockTo36(), SetSysClockTo48(), SetSysClockTo56(), SetSysClockTo72(), SetSysClockToHSE(), and SYSCLKConfig_STOP().


STM32F10x Standard Peripherals Firmware Library: PLL_entry_clock_source

Defines

PLL_entry_clock_source

RCC_Exported_Constants

Defines

#define | IS_RCC_PLL_SOURCE(SOURCE)
#define | RCC_PLLSource_HSE_Div1 ((uint32_t)0x00010000)
#define | RCC_PLLSource_HSE_Div2 ((uint32_t)0x00030000)
#define | RCC_PLLSource_HSI_Div2 ((uint32_t)0x00000000)

Define Documentation

#define IS_RCC_PLL_SOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_PLLSource_HSI_Div2) || \
                                   ((SOURCE) == RCC_PLLSource_HSE_Div1) || \
                                   ((SOURCE) == RCC_PLLSource_HSE_Div2))

Definition at line 86 of file stm32f10x_rcc.h.

Referenced by RCC_PLLConfig().

#define RCC_PLLSource_HSE_Div1 ((uint32_t)0x00010000)

Definition at line 84 of file stm32f10x_rcc.h.

Referenced by SetSysClockTo24(), SetSysClockTo48(), SetSysClockTo56(), and SetSysClockTo72().

#define RCC_PLLSource_HSE_Div2 ((uint32_t)0x00030000)

Definition at line 85 of file stm32f10x_rcc.h.

Referenced by SetSysClockTo36().

#define RCC_PLLSource_HSI_Div2 ((uint32_t)0x00000000)

Definition at line 81 of file stm32f10x_rcc.h.

Referenced by HDMI_CEC_CommandCallBack().


STM32F10x Standard Peripherals Firmware Library: PLL_multiplication_factor

Defines

PLL_multiplication_factor

RCC_Exported_Constants

Defines

#define | IS_RCC_PLL_MUL(MUL)
#define | RCC_PLLMul_10 ((uint32_t)0x00200000)
#define | RCC_PLLMul_11 ((uint32_t)0x00240000)
#define | RCC_PLLMul_12 ((uint32_t)0x00280000)
#define | RCC_PLLMul_13 ((uint32_t)0x002C0000)
#define | RCC_PLLMul_14 ((uint32_t)0x00300000)
#define | RCC_PLLMul_15 ((uint32_t)0x00340000)
#define | RCC_PLLMul_16 ((uint32_t)0x00380000)
#define | RCC_PLLMul_2 ((uint32_t)0x00000000)
#define | RCC_PLLMul_3 ((uint32_t)0x00040000)
#define | RCC_PLLMul_4 ((uint32_t)0x00080000)
#define | RCC_PLLMul_5 ((uint32_t)0x000C0000)
#define | RCC_PLLMul_6 ((uint32_t)0x00100000)
#define | RCC_PLLMul_7 ((uint32_t)0x00140000)
#define | RCC_PLLMul_8 ((uint32_t)0x00180000)
#define | RCC_PLLMul_9 ((uint32_t)0x001C0000)

Define Documentation

#define IS_RCC_PLL_MUL ( MUL )
Value:
(((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3)   || \
                              ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5)   || \
                              ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7)   || \
                              ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9)   || \
                              ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \
                              ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \
                              ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \
                              ((MUL) == RCC_PLLMul_16))

Definition at line 118 of file stm32f10x_rcc.h.

Referenced by RCC_PLLConfig().

#define RCC_PLLMul_10 ((uint32_t)0x00200000)

Definition at line 111 of file stm32f10x_rcc.h.

#define RCC_PLLMul_11 ((uint32_t)0x00240000)

Definition at line 112 of file stm32f10x_rcc.h.

#define RCC_PLLMul_12 ((uint32_t)0x00280000)

Definition at line 113 of file stm32f10x_rcc.h.

#define RCC_PLLMul_13 ((uint32_t)0x002C0000)

Definition at line 114 of file stm32f10x_rcc.h.

#define RCC_PLLMul_14 ((uint32_t)0x00300000)

Definition at line 115 of file stm32f10x_rcc.h.

#define RCC_PLLMul_15 ((uint32_t)0x00340000)

Definition at line 116 of file stm32f10x_rcc.h.

#define RCC_PLLMul_16 ((uint32_t)0x00380000)

Definition at line 117 of file stm32f10x_rcc.h.

#define RCC_PLLMul_2 ((uint32_t)0x00000000)

Definition at line 103 of file stm32f10x_rcc.h.

#define RCC_PLLMul_3 ((uint32_t)0x00040000)

Definition at line 104 of file stm32f10x_rcc.h.

Referenced by SetSysClockTo24().

#define RCC_PLLMul_4 ((uint32_t)0x00080000)

Definition at line 105 of file stm32f10x_rcc.h.

#define RCC_PLLMul_5 ((uint32_t)0x000C0000)

Definition at line 106 of file stm32f10x_rcc.h.

#define RCC_PLLMul_6 ((uint32_t)0x00100000)

Definition at line 107 of file stm32f10x_rcc.h.

Referenced by HDMI_CEC_CommandCallBack(), SetSysClockTo24(), and SetSysClockTo48().

#define RCC_PLLMul_7 ((uint32_t)0x00140000)

Definition at line 108 of file stm32f10x_rcc.h.

Referenced by SetSysClockTo56().

#define RCC_PLLMul_8 ((uint32_t)0x00180000)

Definition at line 109 of file stm32f10x_rcc.h.

#define RCC_PLLMul_9 ((uint32_t)0x001C0000)

Definition at line 110 of file stm32f10x_rcc.h.

Referenced by SetSysClockTo36(), and SetSysClockTo72().


STM32F10x Standard Peripherals Firmware Library: PREDIV1_division_factor

PREDIV1_division_factor

RCC_Exported_Constants


STM32F10x Standard Peripherals Firmware Library: PREDIV1_clock_source

PREDIV1_clock_source

RCC_Exported_Constants


STM32F10x Standard Peripherals Firmware Library: System_clock_source

Defines

System_clock_source

RCC_Exported_Constants

Defines

#define | IS_RCC_SYSCLK_SOURCE(SOURCE)
#define | RCC_SYSCLKSource_HSE ((uint32_t)0x00000001)
#define | RCC_SYSCLKSource_HSI ((uint32_t)0x00000000)
#define | RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002)

Define Documentation

#define IS_RCC_SYSCLK_SOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_SYSCLKSource_HSI) || \
                                      ((SOURCE) == RCC_SYSCLKSource_HSE) || \
                                      ((SOURCE) == RCC_SYSCLKSource_PLLCLK))

Definition at line 292 of file stm32f10x_rcc.h.

Referenced by RCC_SYSCLKConfig().

#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001)

Definition at line 290 of file stm32f10x_rcc.h.

Referenced by RCC_IRQHandler(), and SetSysClockToHSE().

#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000)

Definition at line 289 of file stm32f10x_rcc.h.

#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002)

Definition at line 291 of file stm32f10x_rcc.h.

Referenced by HDMI_CEC_CommandCallBack(), RCC_IRQHandler(), SetSysClockTo24(), SetSysClockTo36(), SetSysClockTo48(), SetSysClockTo56(), SetSysClockTo72(), and SYSCLKConfig_STOP().


STM32F10x Standard Peripherals Firmware Library: AHB_clock_source

Defines

AHB_clock_source

RCC_Exported_Constants

Defines

#define | IS_RCC_HCLK(HCLK)
#define | RCC_SYSCLK_Div1 ((uint32_t)0x00000000)
#define | RCC_SYSCLK_Div128 ((uint32_t)0x000000D0)
#define | RCC_SYSCLK_Div16 ((uint32_t)0x000000B0)
#define | RCC_SYSCLK_Div2 ((uint32_t)0x00000080)
#define | RCC_SYSCLK_Div256 ((uint32_t)0x000000E0)
#define | RCC_SYSCLK_Div4 ((uint32_t)0x00000090)
#define | RCC_SYSCLK_Div512 ((uint32_t)0x000000F0)
#define | RCC_SYSCLK_Div64 ((uint32_t)0x000000C0)
#define | RCC_SYSCLK_Div8 ((uint32_t)0x000000A0)

Define Documentation

#define IS_RCC_HCLK ( HCLK )
Value:
(((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
                           ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \
                           ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \
                           ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \
                           ((HCLK) == RCC_SYSCLK_Div512))

Definition at line 312 of file stm32f10x_rcc.h.

Referenced by RCC_HCLKConfig().

#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000)

Definition at line 303 of file stm32f10x_rcc.h.

Referenced by SetSysClockTo24(), SetSysClockTo36(), SetSysClockTo48(), SetSysClockTo56(), SetSysClockTo72(), and SetSysClockToHSE().

#define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0)

Definition at line 309 of file stm32f10x_rcc.h.

#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0)

Definition at line 307 of file stm32f10x_rcc.h.

#define RCC_SYSCLK_Div2 ((uint32_t)0x00000080)

Definition at line 304 of file stm32f10x_rcc.h.

#define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0)

Definition at line 310 of file stm32f10x_rcc.h.

#define RCC_SYSCLK_Div4 ((uint32_t)0x00000090)

Definition at line 305 of file stm32f10x_rcc.h.

#define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0)

Definition at line 311 of file stm32f10x_rcc.h.

#define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0)

Definition at line 308 of file stm32f10x_rcc.h.

#define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0)

Definition at line 306 of file stm32f10x_rcc.h.


STM32F10x Standard Peripherals Firmware Library: APB1_APB2_clock_source

Defines

APB1_APB2_clock_source

RCC_Exported_Constants

Defines

#define | IS_RCC_PCLK(PCLK)
#define | RCC_HCLK_Div1 ((uint32_t)0x00000000)
#define | RCC_HCLK_Div16 ((uint32_t)0x00000700)
#define | RCC_HCLK_Div2 ((uint32_t)0x00000400)
#define | RCC_HCLK_Div4 ((uint32_t)0x00000500)
#define | RCC_HCLK_Div8 ((uint32_t)0x00000600)

Define Documentation

#define IS_RCC_PCLK ( PCLK )
Value:
(((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
                           ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \
                           ((PCLK) == RCC_HCLK_Div16))

Definition at line 330 of file stm32f10x_rcc.h.

Referenced by RCC_PCLK1Config(), and RCC_PCLK2Config().

#define RCC_HCLK_Div1 ((uint32_t)0x00000000)

Definition at line 325 of file stm32f10x_rcc.h.

Referenced by SetSysClockTo24(), SetSysClockTo36(), SetSysClockTo48(), SetSysClockTo56(), SetSysClockTo72(), and SetSysClockToHSE().

#define RCC_HCLK_Div16 ((uint32_t)0x00000700)

Definition at line 329 of file stm32f10x_rcc.h.

#define RCC_HCLK_Div2 ((uint32_t)0x00000400)

Definition at line 326 of file stm32f10x_rcc.h.

Referenced by SetSysClockTo48(), SetSysClockTo56(), and SetSysClockTo72().

#define RCC_HCLK_Div4 ((uint32_t)0x00000500)

Definition at line 327 of file stm32f10x_rcc.h.

#define RCC_HCLK_Div8 ((uint32_t)0x00000600)

Definition at line 328 of file stm32f10x_rcc.h.


STM32F10x Standard Peripherals Firmware Library: RCC_Interrupt_source

Defines

RCC_Interrupt_source

RCC_Exported_Constants

Defines

#define | IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x60) == 0x00) && ((IT) != 0x00))
#define | IS_RCC_GET_IT(IT)
#define | IS_RCC_IT(IT) ((((IT) & (uint8_t)0xE0) == 0x00) && ((IT) != 0x00))
#define | RCC_IT_CSS ((uint8_t)0x80)
#define | RCC_IT_HSERDY ((uint8_t)0x08)
#define | RCC_IT_HSIRDY ((uint8_t)0x04)
#define | RCC_IT_LSERDY ((uint8_t)0x02)
#define | RCC_IT_LSIRDY ((uint8_t)0x01)
#define | RCC_IT_PLLRDY ((uint8_t)0x10)

Define Documentation

#define IS_RCC_CLEAR_IT ( IT ) ((((IT) & (uint8_t)0x60) == 0x00) && ((IT) != 0x00))

Definition at line 353 of file stm32f10x_rcc.h.

Referenced by RCC_ClearITPendingBit().

#define IS_RCC_GET_IT ( IT )
Value:
(((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
                            ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
                            ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS))

Definition at line 350 of file stm32f10x_rcc.h.

Referenced by RCC_GetITStatus().

#define IS_RCC_IT ( IT ) ((((IT) & (uint8_t)0xE0) == 0x00) && ((IT) != 0x00))

Definition at line 349 of file stm32f10x_rcc.h.

Referenced by RCC_ITConfig().

#define RCC_IT_CSS ((uint8_t)0x80)

Definition at line 346 of file stm32f10x_rcc.h.

Referenced by NMI_Handler().

#define RCC_IT_HSERDY ((uint8_t)0x08)

Definition at line 344 of file stm32f10x_rcc.h.

Referenced by NMI_Handler(), and RCC_IRQHandler().

#define RCC_IT_HSIRDY ((uint8_t)0x04)

Definition at line 343 of file stm32f10x_rcc.h.

#define RCC_IT_LSERDY ((uint8_t)0x02)

Definition at line 342 of file stm32f10x_rcc.h.

#define RCC_IT_LSIRDY ((uint8_t)0x01)

Definition at line 341 of file stm32f10x_rcc.h.

#define RCC_IT_PLLRDY ((uint8_t)0x10)

Definition at line 345 of file stm32f10x_rcc.h.

Referenced by NMI_Handler(), and RCC_IRQHandler().


STM32F10x Standard Peripherals Firmware Library: USB_Device_clock_source

Defines

USB_Device_clock_source

RCC_Exported_Constants

Defines

#define | IS_RCC_USBCLK_SOURCE(SOURCE)
#define | RCC_USBCLKSource_PLLCLK_1Div5 ((uint8_t)0x00)
#define | RCC_USBCLKSource_PLLCLK_Div1 ((uint8_t)0x01)

Define Documentation

#define IS_RCC_USBCLK_SOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_USBCLKSource_PLLCLK_1Div5) || \
                                      ((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1))

Definition at line 378 of file stm32f10x_rcc.h.

Referenced by RCC_USBCLKConfig().

#define RCC_USBCLKSource_PLLCLK_1Div5 ((uint8_t)0x00)

Definition at line 375 of file stm32f10x_rcc.h.

#define RCC_USBCLKSource_PLLCLK_Div1 ((uint8_t)0x01)

Definition at line 376 of file stm32f10x_rcc.h.


STM32F10x Standard Peripherals Firmware Library: ADC_clock_source

Defines

ADC_clock_source

RCC_Exported_Constants

Defines

#define | IS_RCC_ADCCLK(ADCCLK)
#define | RCC_PCLK2_Div2 ((uint32_t)0x00000000)
#define | RCC_PCLK2_Div4 ((uint32_t)0x00004000)
#define | RCC_PCLK2_Div6 ((uint32_t)0x00008000)
#define | RCC_PCLK2_Div8 ((uint32_t)0x0000C000)

Define Documentation

#define IS_RCC_ADCCLK ( ADCCLK )
Value:
(((ADCCLK) == RCC_PCLK2_Div2) || ((ADCCLK) == RCC_PCLK2_Div4) || \
                               ((ADCCLK) == RCC_PCLK2_Div6) || ((ADCCLK) == RCC_PCLK2_Div8))

Definition at line 433 of file stm32f10x_rcc.h.

Referenced by RCC_ADCCLKConfig().

#define RCC_PCLK2_Div2 ((uint32_t)0x00000000)

Definition at line 429 of file stm32f10x_rcc.h.

#define RCC_PCLK2_Div4 ((uint32_t)0x00004000)

Definition at line 430 of file stm32f10x_rcc.h.

Referenced by RCC_Configuration().

#define RCC_PCLK2_Div6 ((uint32_t)0x00008000)

Definition at line 431 of file stm32f10x_rcc.h.

#define RCC_PCLK2_Div8 ((uint32_t)0x0000C000)

Definition at line 432 of file stm32f10x_rcc.h.


STM32F10x Standard Peripherals Firmware Library: LSE_configuration

Defines

LSE_configuration

RCC_Exported_Constants

Defines

#define | IS_RCC_LSE(LSE)
#define | RCC_LSE_Bypass ((uint8_t)0x04)
#define | RCC_LSE_OFF ((uint8_t)0x00)
#define | RCC_LSE_ON ((uint8_t)0x01)

Define Documentation

#define IS_RCC_LSE ( LSE )
Value:
(((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
                         ((LSE) == RCC_LSE_Bypass))

Definition at line 446 of file stm32f10x_rcc.h.

Referenced by RCC_LSEConfig().

#define RCC_LSE_Bypass ((uint8_t)0x04)

Definition at line 445 of file stm32f10x_rcc.h.

Referenced by RCC_LSEConfig().

#define RCC_LSE_OFF ((uint8_t)0x00)

Definition at line 443 of file stm32f10x_rcc.h.

Referenced by RCC_LSEConfig().

#define RCC_LSE_ON ((uint8_t)0x01)

Definition at line 444 of file stm32f10x_rcc.h.

Referenced by RCC_LSEConfig(), and RTC_Configuration().


STM32F10x Standard Peripherals Firmware Library: RTC_clock_source

Defines

RTC_clock_source

RCC_Exported_Constants

Defines

#define | IS_RCC_RTCCLK_SOURCE(SOURCE)
#define | RCC_RTCCLKSource_HSE_Div128 ((uint32_t)0x00000300)
#define | RCC_RTCCLKSource_LSE ((uint32_t)0x00000100)
#define | RCC_RTCCLKSource_LSI ((uint32_t)0x00000200)

Define Documentation

#define IS_RCC_RTCCLK_SOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_RTCCLKSource_LSE) || \
                                      ((SOURCE) == RCC_RTCCLKSource_LSI) || \
                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div128))

Definition at line 459 of file stm32f10x_rcc.h.

Referenced by RCC_RTCCLKConfig().

#define RCC_RTCCLKSource_HSE_Div128 ((uint32_t)0x00000300)

Definition at line 458 of file stm32f10x_rcc.h.

#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100)

Definition at line 456 of file stm32f10x_rcc.h.

Referenced by RTC_Configuration().

#define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200)

Definition at line 457 of file stm32f10x_rcc.h.


STM32F10x Standard Peripherals Firmware Library: AHB_peripheral

Defines

AHB_peripheral

RCC_Exported_Constants

Defines

#define | IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFAA8) == 0x00) && ((PERIPH) != 0x00))
#define | RCC_AHBPeriph_CRC ((uint32_t)0x00000040)
#define | RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001)
#define | RCC_AHBPeriph_DMA2 ((uint32_t)0x00000002)
#define | RCC_AHBPeriph_FLITF ((uint32_t)0x00000010)
#define | RCC_AHBPeriph_FSMC ((uint32_t)0x00000100)
#define | RCC_AHBPeriph_SDIO ((uint32_t)0x00000400)
#define | RCC_AHBPeriph_SRAM ((uint32_t)0x00000004)

Define Documentation

#define IS_RCC_AHB_PERIPH ( PERIPH ) ((((PERIPH) & 0xFFFFFAA8) == 0x00) && ((PERIPH) != 0x00))

Definition at line 479 of file stm32f10x_rcc.h.

Referenced by RCC_AHBPeriphClockCmd().

#define RCC_AHBPeriph_CRC ((uint32_t)0x00000040)

Definition at line 474 of file stm32f10x_rcc.h.

Referenced by main().

#define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001)

Definition at line 470 of file stm32f10x_rcc.h.

Referenced by main(), and RCC_Configuration().

#define RCC_AHBPeriph_DMA2 ((uint32_t)0x00000002)

Definition at line 471 of file stm32f10x_rcc.h.

Referenced by RCC_Configuration(), and SD_LowLevel_Init().

#define RCC_AHBPeriph_FLITF ((uint32_t)0x00000010)

Definition at line 473 of file stm32f10x_rcc.h.

#define RCC_AHBPeriph_FSMC ((uint32_t)0x00000100)

Definition at line 477 of file stm32f10x_rcc.h.

Referenced by LCD_CtrlLinesConfig(), main(), and OneNAND_Init().

#define RCC_AHBPeriph_SDIO ((uint32_t)0x00000400)

Definition at line 478 of file stm32f10x_rcc.h.

Referenced by SD_LowLevel_DeInit(), and SD_LowLevel_Init().

#define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004)

Definition at line 472 of file stm32f10x_rcc.h.


STM32F10x Standard Peripherals Firmware Library: APB2_peripheral

Defines

APB2_peripheral

RCC_Exported_Constants

Defines

#define | IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFC00002) == 0x00) && ((PERIPH) != 0x00))
#define | RCC_APB2Periph_ADC1 ((uint32_t)0x00000200)
#define | RCC_APB2Periph_ADC2 ((uint32_t)0x00000400)
#define | RCC_APB2Periph_ADC3 ((uint32_t)0x00008000)
#define | RCC_APB2Periph_AFIO ((uint32_t)0x00000001)
#define | RCC_APB2Periph_GPIOA ((uint32_t)0x00000004)
#define | RCC_APB2Periph_GPIOB ((uint32_t)0x00000008)
#define | RCC_APB2Periph_GPIOC ((uint32_t)0x00000010)
#define | RCC_APB2Periph_GPIOD ((uint32_t)0x00000020)
#define | RCC_APB2Periph_GPIOE ((uint32_t)0x00000040)
#define | RCC_APB2Periph_GPIOF ((uint32_t)0x00000080)
#define | RCC_APB2Periph_GPIOG ((uint32_t)0x00000100)
#define | RCC_APB2Periph_SPI1 ((uint32_t)0x00001000)
#define | RCC_APB2Periph_TIM1 ((uint32_t)0x00000800)
#define | RCC_APB2Periph_TIM10 ((uint32_t)0x00100000)
#define | RCC_APB2Periph_TIM11 ((uint32_t)0x00200000)
#define | RCC_APB2Periph_TIM15 ((uint32_t)0x00010000)
#define | RCC_APB2Periph_TIM16 ((uint32_t)0x00020000)
#define | RCC_APB2Periph_TIM17 ((uint32_t)0x00040000)
#define | RCC_APB2Periph_TIM8 ((uint32_t)0x00002000)
#define | RCC_APB2Periph_TIM9 ((uint32_t)0x00080000)
#define | RCC_APB2Periph_USART1 ((uint32_t)0x00004000)

Define Documentation

#define IS_RCC_APB2_PERIPH ( PERIPH ) ((((PERIPH) & 0xFFC00002) == 0x00) && ((PERIPH) != 0x00))

Definition at line 519 of file stm32f10x_rcc.h.

Referenced by RCC_APB2PeriphClockCmd(), and RCC_APB2PeriphResetCmd().

#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200)

Definition at line 505 of file stm32f10x_rcc.h.

Referenced by ADC_DeInit(), and RCC_Configuration().

#define RCC_APB2Periph_ADC2 ((uint32_t)0x00000400)

Definition at line 506 of file stm32f10x_rcc.h.

Referenced by ADC_DeInit(), and RCC_Configuration().

#define RCC_APB2Periph_ADC3 ((uint32_t)0x00008000)

Definition at line 511 of file stm32f10x_rcc.h.

Referenced by ADC_DeInit(), and RCC_Configuration().

#define RCC_APB2Periph_AFIO ((uint32_t)0x00000001)

Definition at line 497 of file stm32f10x_rcc.h.

Referenced by CAN_Config(), EXTI0_Config(), EXTI9_5_Config(), GPIO_AFIODeInit(), IOE_EXTI_Config(), IOE_GPIO_Config(), LCD_CtrlLinesConfig(), LCD_SPIConfig(), OneNAND_Init(), SD_LowLevel_Init(), STM_EVAL_COMInit(), and STM_EVAL_PBInit().

#define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004)

Definition at line 498 of file stm32f10x_rcc.h.

Referenced by EXTI0_Config(), GPIO_DeInit(), and main().

#define RCC_APB2Periph_GPIOB ((uint32_t)0x00000008)

Definition at line 499 of file stm32f10x_rcc.h.

Referenced by CAN_Config(), EXTI9_5_Config(), GPIO_DeInit(), and OneNAND_Init().

#define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010)

Definition at line 500 of file stm32f10x_rcc.h.

Referenced by GPIO_DeInit(), RCC_Configuration(), and SD_LowLevel_Init().

#define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020)

Definition at line 501 of file stm32f10x_rcc.h.

Referenced by CAN_Config(), GPIO_DeInit(), LCD_CtrlLinesConfig(), main(), NAND_Init(), NOR_Init(), OneNAND_Init(), SD_LowLevel_Init(), and SRAM_Init().

#define RCC_APB2Periph_GPIOE ((uint32_t)0x00000040)

Definition at line 502 of file stm32f10x_rcc.h.

Referenced by GPIO_DeInit(), LCD_CtrlLinesConfig(), NAND_Init(), NOR_Init(), OneNAND_Init(), and SRAM_Init().

#define RCC_APB2Periph_GPIOF ((uint32_t)0x00000080)

Definition at line 503 of file stm32f10x_rcc.h.

Referenced by GPIO_DeInit(), LCD_CtrlLinesConfig(), NAND_Init(), NOR_Init(), OneNAND_Init(), and SRAM_Init().

#define RCC_APB2Periph_GPIOG ((uint32_t)0x00000100)

Definition at line 504 of file stm32f10x_rcc.h.

Referenced by EXTI9_5_Config(), GPIO_DeInit(), LCD_CtrlLinesConfig(), NAND_Init(), NOR_Init(), OneNAND_Init(), and SRAM_Init().

#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000)

Definition at line 508 of file stm32f10x_rcc.h.

Referenced by main(), and SPI_I2S_DeInit().

#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800)

Definition at line 507 of file stm32f10x_rcc.h.

Referenced by main(), and TIM_DeInit().

#define RCC_APB2Periph_TIM10 ((uint32_t)0x00100000)

Definition at line 516 of file stm32f10x_rcc.h.

Referenced by TIM_DeInit().

#define RCC_APB2Periph_TIM11 ((uint32_t)0x00200000)

Definition at line 517 of file stm32f10x_rcc.h.

Referenced by TIM_DeInit().

#define RCC_APB2Periph_TIM15 ((uint32_t)0x00010000)

Definition at line 512 of file stm32f10x_rcc.h.

Referenced by TIM_DeInit().

#define RCC_APB2Periph_TIM16 ((uint32_t)0x00020000)

Definition at line 513 of file stm32f10x_rcc.h.

Referenced by TIM_DeInit().

#define RCC_APB2Periph_TIM17 ((uint32_t)0x00040000)

Definition at line 514 of file stm32f10x_rcc.h.

Referenced by TIM_DeInit().

#define RCC_APB2Periph_TIM8 ((uint32_t)0x00002000)

Definition at line 509 of file stm32f10x_rcc.h.

Referenced by TIM_DeInit().

#define RCC_APB2Periph_TIM9 ((uint32_t)0x00080000)

Definition at line 515 of file stm32f10x_rcc.h.

Referenced by TIM_DeInit().

#define RCC_APB2Periph_USART1 ((uint32_t)0x00004000)

Definition at line 510 of file stm32f10x_rcc.h.

Referenced by USART_DeInit().


STM32F10x Standard Peripherals Firmware Library: APB1_peripheral

Defines

APB1_peripheral

RCC_Exported_Constants

Defines

#define | IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x81013600) == 0x00) && ((PERIPH) != 0x00))
#define | RCC_APB1Periph_BKP ((uint32_t)0x08000000)
#define | RCC_APB1Periph_CAN1 ((uint32_t)0x02000000)
#define | RCC_APB1Periph_CAN2 ((uint32_t)0x04000000)
#define | RCC_APB1Periph_CEC ((uint32_t)0x40000000)
#define | RCC_APB1Periph_DAC ((uint32_t)0x20000000)
#define | RCC_APB1Periph_I2C1 ((uint32_t)0x00200000)
#define | RCC_APB1Periph_I2C2 ((uint32_t)0x00400000)
#define | RCC_APB1Periph_PWR ((uint32_t)0x10000000)
#define | RCC_APB1Periph_SPI2 ((uint32_t)0x00004000)
#define | RCC_APB1Periph_SPI3 ((uint32_t)0x00008000)
#define | RCC_APB1Periph_TIM12 ((uint32_t)0x00000040)
#define | RCC_APB1Periph_TIM13 ((uint32_t)0x00000080)
#define | RCC_APB1Periph_TIM14 ((uint32_t)0x00000100)
#define | RCC_APB1Periph_TIM2 ((uint32_t)0x00000001)
#define | RCC_APB1Periph_TIM3 ((uint32_t)0x00000002)
#define | RCC_APB1Periph_TIM4 ((uint32_t)0x00000004)
#define | RCC_APB1Periph_TIM5 ((uint32_t)0x00000008)
#define | RCC_APB1Periph_TIM6 ((uint32_t)0x00000010)
#define | RCC_APB1Periph_TIM7 ((uint32_t)0x00000020)
#define | RCC_APB1Periph_UART4 ((uint32_t)0x00080000)
#define | RCC_APB1Periph_UART5 ((uint32_t)0x00100000)
#define | RCC_APB1Periph_USART2 ((uint32_t)0x00020000)
#define | RCC_APB1Periph_USART3 ((uint32_t)0x00040000)
#define | RCC_APB1Periph_USB ((uint32_t)0x00800000)
#define | RCC_APB1Periph_WWDG ((uint32_t)0x00000800)

Define Documentation

#define IS_RCC_APB1_PERIPH ( PERIPH ) ((((PERIPH) & 0x81013600) == 0x00) && ((PERIPH) != 0x00))

Definition at line 554 of file stm32f10x_rcc.h.

Referenced by RCC_APB1PeriphClockCmd(), and RCC_APB1PeriphResetCmd().

#define RCC_APB1Periph_BKP ((uint32_t)0x08000000)

Definition at line 549 of file stm32f10x_rcc.h.

Referenced by main().

#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000)

Definition at line 547 of file stm32f10x_rcc.h.

Referenced by CAN_Config(), CAN_DeInit(), and main().

#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000)

Definition at line 548 of file stm32f10x_rcc.h.

Referenced by CAN_Config(), CAN_DeInit(), and main().

#define RCC_APB1Periph_CEC ((uint32_t)0x40000000)

Definition at line 552 of file stm32f10x_rcc.h.

Referenced by CEC_DeInit(), and HDMI_CEC_Init().

#define RCC_APB1Periph_DAC ((uint32_t)0x20000000)

Definition at line 551 of file stm32f10x_rcc.h.

Referenced by DAC_DeInit().

#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000)

Definition at line 544 of file stm32f10x_rcc.h.

Referenced by I2C_DeInit().

#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000)

Definition at line 545 of file stm32f10x_rcc.h.

Referenced by I2C_DeInit().

#define RCC_APB1Periph_PWR ((uint32_t)0x10000000)

Definition at line 550 of file stm32f10x_rcc.h.

Referenced by main(), and PWR_DeInit().

#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000)

Definition at line 538 of file stm32f10x_rcc.h.

Referenced by SPI_I2S_DeInit().

#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000)

Definition at line 539 of file stm32f10x_rcc.h.

Referenced by SPI_I2S_DeInit().

#define RCC_APB1Periph_TIM12 ((uint32_t)0x00000040)

Definition at line 534 of file stm32f10x_rcc.h.

Referenced by TIM_DeInit().

#define RCC_APB1Periph_TIM13 ((uint32_t)0x00000080)

Definition at line 535 of file stm32f10x_rcc.h.

Referenced by TIM_DeInit().

#define RCC_APB1Periph_TIM14 ((uint32_t)0x00000100)

Definition at line 536 of file stm32f10x_rcc.h.

Referenced by TIM_DeInit().

#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001)

Definition at line 528 of file stm32f10x_rcc.h.

Referenced by TIM_Config(), and TIM_DeInit().

#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002)

Definition at line 529 of file stm32f10x_rcc.h.

Referenced by TIM_Config(), and TIM_DeInit().

#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004)

Definition at line 530 of file stm32f10x_rcc.h.

Referenced by TIM_Config(), and TIM_DeInit().

#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008)

Definition at line 531 of file stm32f10x_rcc.h.

Referenced by main(), TIM5_ConfigForLSI(), and TIM_DeInit().

#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010)

Definition at line 532 of file stm32f10x_rcc.h.

Referenced by TIM_DeInit().

#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020)

Definition at line 533 of file stm32f10x_rcc.h.

Referenced by TIM_DeInit().

#define RCC_APB1Periph_UART4 ((uint32_t)0x00080000)

Definition at line 542 of file stm32f10x_rcc.h.

Referenced by USART_DeInit().

#define RCC_APB1Periph_UART5 ((uint32_t)0x00100000)

Definition at line 543 of file stm32f10x_rcc.h.

Referenced by USART_DeInit().

#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000)

Definition at line 540 of file stm32f10x_rcc.h.

Referenced by USART_DeInit().

#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000)

Definition at line 541 of file stm32f10x_rcc.h.

Referenced by USART_DeInit().

#define RCC_APB1Periph_USB ((uint32_t)0x00800000)

Definition at line 546 of file stm32f10x_rcc.h.

#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800)

Definition at line 537 of file stm32f10x_rcc.h.

Referenced by main(), and WWDG_DeInit().


STM32F10x Standard Peripherals Firmware Library: Clock_source_to_output_on_MCO_pin

Defines

Clock_source_to_output_on_MCO_pin

RCC_Exported_Constants

Defines

#define | IS_RCC_MCO(MCO)
#define | RCC_MCO_HSE ((uint8_t)0x06)
#define | RCC_MCO_HSI ((uint8_t)0x05)
#define | RCC_MCO_NoClock ((uint8_t)0x00)
#define | RCC_MCO_PLLCLK_Div2 ((uint8_t)0x07)
#define | RCC_MCO_SYSCLK ((uint8_t)0x04)

Define Documentation

#define IS_RCC_MCO ( MCO )
Value:
(((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \
                          ((MCO) == RCC_MCO_SYSCLK)  || ((MCO) == RCC_MCO_HSE) || \
                          ((MCO) == RCC_MCO_PLLCLK_Div2))

Definition at line 571 of file stm32f10x_rcc.h.

Referenced by RCC_MCOConfig().

#define RCC_MCO_HSE ((uint8_t)0x06)

Definition at line 567 of file stm32f10x_rcc.h.

Referenced by main().

#define RCC_MCO_HSI ((uint8_t)0x05)

Definition at line 566 of file stm32f10x_rcc.h.

#define RCC_MCO_NoClock ((uint8_t)0x00)

Definition at line 564 of file stm32f10x_rcc.h.

#define RCC_MCO_PLLCLK_Div2 ((uint8_t)0x07)

Definition at line 568 of file stm32f10x_rcc.h.

#define RCC_MCO_SYSCLK ((uint8_t)0x04)

Definition at line 565 of file stm32f10x_rcc.h.


STM32F10x Standard Peripherals Firmware Library: RCC_Flag

Defines

RCC_Flag

RCC_Exported_Constants

Defines

#define | IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
#define | IS_RCC_FLAG(FLAG)
#define | RCC_FLAG_HSERDY ((uint8_t)0x31)
#define | RCC_FLAG_HSIRDY ((uint8_t)0x21)
#define | RCC_FLAG_IWDGRST ((uint8_t)0x7D)
#define | RCC_FLAG_LPWRRST ((uint8_t)0x7F)
#define | RCC_FLAG_LSERDY ((uint8_t)0x41)
#define | RCC_FLAG_LSIRDY ((uint8_t)0x61)
#define | RCC_FLAG_PINRST ((uint8_t)0x7A)
#define | RCC_FLAG_PLLRDY ((uint8_t)0x39)
#define | RCC_FLAG_PORRST ((uint8_t)0x7B)
#define | RCC_FLAG_SFTRST ((uint8_t)0x7C)
#define | RCC_FLAG_WWDGRST ((uint8_t)0x7E)

Define Documentation

#define IS_RCC_CALIBRATION_VALUE ( VALUE ) ((VALUE) <= 0x1F)

Definition at line 626 of file stm32f10x_rcc.h.

Referenced by RCC_AdjustHSICalibrationValue().

#define IS_RCC_FLAG ( FLAG )
Value:
(((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
                            ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
                            ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \
                            ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \
                            ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \
                            ((FLAG) == RCC_FLAG_LPWRRST))

Definition at line 608 of file stm32f10x_rcc.h.

Referenced by RCC_GetFlagStatus().

#define RCC_FLAG_HSERDY ((uint8_t)0x31)

Definition at line 596 of file stm32f10x_rcc.h.

Referenced by RCC_IRQHandler(), and RCC_WaitForHSEStartUp().

#define RCC_FLAG_HSIRDY ((uint8_t)0x21)

Definition at line 595 of file stm32f10x_rcc.h.

#define RCC_FLAG_IWDGRST ((uint8_t)0x7D)

Definition at line 603 of file stm32f10x_rcc.h.

Referenced by main().

#define RCC_FLAG_LPWRRST ((uint8_t)0x7F)

Definition at line 605 of file stm32f10x_rcc.h.

#define RCC_FLAG_LSERDY ((uint8_t)0x41)

Definition at line 598 of file stm32f10x_rcc.h.

Referenced by RTC_Configuration().

#define RCC_FLAG_LSIRDY ((uint8_t)0x61)

Definition at line 599 of file stm32f10x_rcc.h.

Referenced by main().

#define RCC_FLAG_PINRST ((uint8_t)0x7A)

Definition at line 600 of file stm32f10x_rcc.h.

Referenced by main().

#define RCC_FLAG_PLLRDY ((uint8_t)0x39)

Definition at line 597 of file stm32f10x_rcc.h.

Referenced by HDMI_CEC_CommandCallBack(), RCC_IRQHandler(), SetSysClockTo24(), SetSysClockTo36(), SetSysClockTo48(), SetSysClockTo56(), SetSysClockTo72(), and SYSCLKConfig_STOP().

#define RCC_FLAG_PORRST ((uint8_t)0x7B)

Definition at line 601 of file stm32f10x_rcc.h.

Referenced by main().

#define RCC_FLAG_SFTRST ((uint8_t)0x7C)

Definition at line 602 of file stm32f10x_rcc.h.

#define RCC_FLAG_WWDGRST ((uint8_t)0x7E)

Definition at line 604 of file stm32f10x_rcc.h.

Referenced by main().


STM32F10x Standard Peripherals Firmware Library: RCC_Exported_Macros

RCC_Exported_Macros

RCC


STM32F10x Standard Peripherals Firmware Library: RCC_Exported_Functions

Functions

RCC_Exported_Functions

RCC

Functions

void | RCC_ADCCLKConfig (uint32_t RCC_PCLK2)
Configures the ADC clock (ADCCLK).
void | RCC_AdjustHSICalibrationValue (uint8_t HSICalibrationValue)
Adjusts the Internal High Speed oscillator (HSI) calibration value.
void | RCC_AHBPeriphClockCmd (uint32_t RCC_AHBPeriph, FunctionalState NewState)
Enables or disables the AHB peripheral clock.
void | RCC_APB1PeriphClockCmd (uint32_t RCC_APB1Periph, FunctionalState NewState)
Enables or disables the Low Speed APB (APB1) peripheral clock.
void | RCC_APB1PeriphResetCmd (uint32_t RCC_APB1Periph, FunctionalState NewState)
Forces or releases Low Speed APB (APB1) peripheral reset.
void | RCC_APB2PeriphClockCmd (uint32_t RCC_APB2Periph, FunctionalState NewState)
Enables or disables the High Speed APB (APB2) peripheral clock.
void | RCC_APB2PeriphResetCmd (uint32_t RCC_APB2Periph, FunctionalState NewState)
Forces or releases High Speed APB (APB2) peripheral reset.
void | RCC_BackupResetCmd (FunctionalState NewState)
Forces or releases the Backup domain reset.
void | RCC_ClearFlag (void)
Clears the RCC reset flags.
void | RCC_ClearITPendingBit (uint8_t RCC_IT)
Clears the RCC's interrupt pending bits.
void | RCC_ClockSecuritySystemCmd (FunctionalState NewState)
Enables or disables the Clock Security System.
void | RCC_DeInit (void)
Resets the RCC clock configuration to the default reset state.
void | RCC_GetClocksFreq (RCC_ClocksTypeDef *RCC_Clocks)
Returns the frequencies of different on chip clocks.
FlagStatus | RCC_GetFlagStatus (uint8_t RCC_FLAG)
Checks whether the specified RCC flag is set or not.
ITStatus | RCC_GetITStatus (uint8_t RCC_IT)
Checks whether the specified RCC interrupt has occurred or not.
uint8_t | RCC_GetSYSCLKSource (void)
Returns the clock source used as system clock.
void | RCC_HCLKConfig (uint32_t RCC_SYSCLK)
Configures the AHB clock (HCLK).
void | RCC_HSEConfig (uint32_t RCC_HSE)
Configures the External High Speed oscillator (HSE).
void | RCC_HSICmd (FunctionalState NewState)
Enables or disables the Internal High Speed oscillator (HSI).
void | RCC_ITConfig (uint8_t RCC_IT, FunctionalState NewState)
Enables or disables the specified RCC interrupts.
void | RCC_LSEConfig (uint8_t RCC_LSE)
Configures the External Low Speed oscillator (LSE).
void | RCC_LSICmd (FunctionalState NewState)
Enables or disables the Internal Low Speed oscillator (LSI).
void | RCC_MCOConfig (uint8_t RCC_MCO)
Selects the clock source to output on MCO pin.
void | RCC_PCLK1Config (uint32_t RCC_HCLK)
Configures the Low Speed APB clock (PCLK1).
void | RCC_PCLK2Config (uint32_t RCC_HCLK)
Configures the High Speed APB clock (PCLK2).
void | RCC_PLLCmd (FunctionalState NewState)
Enables or disables the PLL.
void | RCC_PLLConfig (uint32_t RCC_PLLSource, uint32_t RCC_PLLMul)
Configures the PLL clock source and multiplication factor.
void | RCC_RTCCLKCmd (FunctionalState NewState)
Enables or disables the RTC clock.
void | RCC_RTCCLKConfig (uint32_t RCC_RTCCLKSource)
Configures the RTC clock (RTCCLK).
void | RCC_SYSCLKConfig (uint32_t RCC_SYSCLKSource)
Configures the system clock (SYSCLK).
void | RCC_USBCLKConfig (uint32_t RCC_USBCLKSource)
Configures the USB clock (USBCLK).
ErrorStatus | RCC_WaitForHSEStartUp (void)
Waits for HSE start-up.

Function Documentation

void RCC_ADCCLKConfig ( uint32_t RCC_PCLK2 )

Configures the ADC clock (ADCCLK).

Parameters:
RCC_PCLK2,: defines the ADC clock divider. This clock is derived from the APB2 clock (PCLK2). This parameter can be one of the following values:

  • RCC_PCLK2_Div2: ADC clock = PCLK2/2
  • RCC_PCLK2_Div4: ADC clock = PCLK2/4
  • RCC_PCLK2_Div6: ADC clock = PCLK2/6
  • RCC_PCLK2_Div8: ADC clock = PCLK2/8
Return values:
None

Definition at line 766 of file stm32f10x_rcc.c.

References assert_param, CFGR_ADCPRE_Reset_Mask, IS_RCC_ADCCLK, and RCC.

Referenced by RCC_Configuration().

void RCC_AdjustHSICalibrationValue ( uint8_t HSICalibrationValue )

Adjusts the Internal High Speed oscillator (HSI) calibration value.

Parameters:
HSICalibrationValue,: specifies the calibration trimming value. This parameter must be a number between 0 and 0x1F.
Return values:
None

Definition at line 334 of file stm32f10x_rcc.c.

References assert_param, CR_HSITRIM_Mask, IS_RCC_CALIBRATION_VALUE, and RCC.

void RCC_AHBPeriphClockCmd | ( | uint32_t | RCC_AHBPeriph,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the AHB peripheral clock.

Parameters:
RCC_AHBPeriph,: specifies the AHB peripheral to gates its clock.

For STM32_Connectivity_line_devices, this parameter can be any combination of the following values:

  • RCC_AHBPeriph_DMA1
  • RCC_AHBPeriph_DMA2
  • RCC_AHBPeriph_SRAM
  • RCC_AHBPeriph_FLITF
  • RCC_AHBPeriph_CRC
  • RCC_AHBPeriph_OTG_FS
  • RCC_AHBPeriph_ETH_MAC
  • RCC_AHBPeriph_ETH_MAC_Tx
  • RCC_AHBPeriph_ETH_MAC_Rx

For other_STM32_devices, this parameter can be any combination of the following values:

  • RCC_AHBPeriph_DMA1
  • RCC_AHBPeriph_DMA2
  • RCC_AHBPeriph_SRAM
  • RCC_AHBPeriph_FLITF
  • RCC_AHBPeriph_CRC
  • RCC_AHBPeriph_FSMC
  • RCC_AHBPeriph_SDIO
Note:
SRAM and FLITF clock can be disabled only during sleep mode.
Parameters:
NewState,: new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1064 of file stm32f10x_rcc.c.

References assert_param, DISABLE, IS_FUNCTIONAL_STATE, IS_RCC_AHB_PERIPH, and RCC.

Referenced by IOE_DMA_Config(), LCD_CtrlLinesConfig(), LCD_GPIOConfig(), LCD_SPIConfig(), LM75_DMA_Config(), LM75_LowLevel_Init(), main(), OneNAND_Init(), RCC_Configuration(), SD_LowLevel_DeInit(), SD_LowLevel_Init(), sEE_LowLevel_Init(), STM_EVAL_COMInit(), STM_EVAL_LEDInit(), and STM_EVAL_PBInit().

void RCC_APB1PeriphClockCmd | ( | uint32_t | RCC_APB1Periph,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the Low Speed APB (APB1) peripheral clock.

Parameters:
RCC_APB1Periph,: specifies the APB1 peripheral to gates its clock. This parameter can be any combination of the following values:

  • RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4, RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7, RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3, RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4, RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2, RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP, RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_CEC, RCC_APB1Periph_TIM12, RCC_APB1Periph_TIM13, RCC_APB1Periph_TIM14
NewState,: new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1126 of file stm32f10x_rcc.c.

References assert_param, DISABLE, IS_FUNCTIONAL_STATE, IS_RCC_APB1_PERIPH, and RCC.

Referenced by CAN_Config(), HDMI_CEC_Init(), IOE_GPIO_Config(), LCD_DeInit(), LCD_GLASS_Init(), LCD_SPIConfig(), LM75_LowLevel_DeInit(), LM75_LowLevel_Init(), main(), SD_LowLevel_DeInit(), SD_LowLevel_Init(), sEE_LowLevel_DeInit(), sEE_LowLevel_Init(), STM32L152_LCD_DeInit(), STM_EVAL_COMInit(), TIM5_ConfigForLSI(), and TIM_Config().

void RCC_APB1PeriphResetCmd | ( | uint32_t | RCC_APB1Periph,
 |  | FunctionalState | NewState
 | ) |  |

Forces or releases Low Speed APB (APB1) peripheral reset.

Parameters:
RCC_APB1Periph,: specifies the APB1 peripheral to reset. This parameter can be any combination of the following values:

  • RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4, RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7, RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3, RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4, RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2, RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP, RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_CEC, RCC_APB1Periph_TIM12, RCC_APB1Periph_TIM13, RCC_APB1Periph_TIM14
NewState,: new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1216 of file stm32f10x_rcc.c.

References assert_param, DISABLE, IS_FUNCTIONAL_STATE, IS_RCC_APB1_PERIPH, and RCC.

Referenced by CAN_DeInit(), CEC_DeInit(), DAC_DeInit(), I2C_DeInit(), IOE_GPIO_Config(), PWR_DeInit(), sEE_LowLevel_Init(), SPI_I2S_DeInit(), TIM_DeInit(), USART_DeInit(), and WWDG_DeInit().

void RCC_APB2PeriphClockCmd | ( | uint32_t | RCC_APB2Periph,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the High Speed APB (APB2) peripheral clock.

Parameters:
RCC_APB2Periph,: specifies the APB2 peripheral to gates its clock. This parameter can be any combination of the following values:

  • RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB, RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE, RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1, RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1, RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3, RCC_APB2Periph_TIM15, RCC_APB2Periph_TIM16, RCC_APB2Periph_TIM17, RCC_APB2Periph_TIM9, RCC_APB2Periph_TIM10, RCC_APB2Periph_TIM11
NewState,: new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1095 of file stm32f10x_rcc.c.

References assert_param, DISABLE, IS_FUNCTIONAL_STATE, IS_RCC_APB2_PERIPH, and RCC.

Referenced by CAN_Config(), EXTI0_Config(), EXTI9_5_Config(), HDMI_CEC_Init(), IOE_EXTI_Config(), IOE_GPIO_Config(), LCD_CtrlLinesConfig(), LCD_SPIConfig(), LM75_LowLevel_Init(), main(), NAND_Init(), NOR_Init(), OneNAND_Init(), RCC_Configuration(), SD_LowLevel_DeInit(), SD_LowLevel_Init(), sEE_LowLevel_Init(), sFLASH_LowLevel_DeInit(), sFLASH_LowLevel_Init(), SRAM_Init(), STM_EVAL_COMInit(), STM_EVAL_LEDInit(), and STM_EVAL_PBInit().

void RCC_APB2PeriphResetCmd | ( | uint32_t | RCC_APB2Periph,
 |  | FunctionalState | NewState
 | ) |  |

Forces or releases High Speed APB (APB2) peripheral reset.

Parameters:
RCC_APB2Periph,: specifies the APB2 peripheral to reset. This parameter can be any combination of the following values:

  • RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB, RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE, RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1, RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1, RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3, RCC_APB2Periph_TIM15, RCC_APB2Periph_TIM16, RCC_APB2Periph_TIM17, RCC_APB2Periph_TIM9, RCC_APB2Periph_TIM10, RCC_APB2Periph_TIM11
NewState,: new state of the specified peripheral reset. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1185 of file stm32f10x_rcc.c.

References assert_param, DISABLE, IS_FUNCTIONAL_STATE, IS_RCC_APB2_PERIPH, and RCC.

Referenced by ADC_DeInit(), GPIO_AFIODeInit(), GPIO_DeInit(), SPI_I2S_DeInit(), TIM_DeInit(), and USART_DeInit().

void RCC_BackupResetCmd ( FunctionalState NewState )

Forces or releases the Backup domain reset.

Parameters:
NewState,: new state of the Backup domain reset. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1237 of file stm32f10x_rcc.c.

References assert_param, BDCR_BDRST_BB, and IS_FUNCTIONAL_STATE.

Referenced by BKP_DeInit().

void RCC_ClearFlag ( void )

Clears the RCC reset flags.

Note:
The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
Parameters:
None
Return values:
None

Definition at line 1371 of file stm32f10x_rcc.c.

References CSR_RMVF_Set, and RCC.

Referenced by main().

void RCC_ClearITPendingBit ( uint8_t RCC_IT )

Clears the RCC's interrupt pending bits.

Parameters:
RCC_IT,: specifies the interrupt pending bit to clear.

For STM32_Connectivity_line_devices, this parameter can be any combination of the following values:

  • RCC_IT_LSIRDY: LSI ready interrupt
  • RCC_IT_LSERDY: LSE ready interrupt
  • RCC_IT_HSIRDY: HSI ready interrupt
  • RCC_IT_HSERDY: HSE ready interrupt
  • RCC_IT_PLLRDY: PLL ready interrupt
  • RCC_IT_PLL2RDY: PLL2 ready interrupt
  • RCC_IT_PLL3RDY: PLL3 ready interrupt
  • RCC_IT_CSS: Clock Security System interrupt

For other_STM32_devices, this parameter can be any combination of the following values:

  • RCC_IT_LSIRDY: LSI ready interrupt
  • RCC_IT_LSERDY: LSE ready interrupt
  • RCC_IT_HSIRDY: HSI ready interrupt
  • RCC_IT_HSERDY: HSE ready interrupt
  • RCC_IT_PLLRDY: PLL ready interrupt
  • RCC_IT_CSS: Clock Security System interrupt
    Return values:
    None

Definition at line 1448 of file stm32f10x_rcc.c.

References assert_param, CIR_BYTE3_ADDRESS, and IS_RCC_CLEAR_IT.

Referenced by NMI_Handler(), and RCC_IRQHandler().

void RCC_ClockSecuritySystemCmd ( FunctionalState NewState )

Enables or disables the Clock Security System.

Parameters:
NewState,: new state of the Clock Security System.. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1250 of file stm32f10x_rcc.c.

References assert_param, CR_CSSON_BB, and IS_FUNCTIONAL_STATE.

Referenced by main().

void RCC_DeInit ( void )

Resets the RCC clock configuration to the default reset state.

Parameters:
None
Return values:
None

Definition at line 217 of file stm32f10x_rcc.c.

References RCC.

Referenced by SetSysClockTo24(), SetSysClockTo36(), SetSysClockTo48(), SetSysClockTo56(), SetSysClockTo72(), and SetSysClockToHSE().

void RCC_GetClocksFreq ( RCC_ClocksTypeDef * RCC_Clocks )

Returns the frequencies of different on chip clocks.

Parameters:
RCC_Clocks,: pointer to a RCC_ClocksTypeDef structure which will hold the clocks frequencies.
Note:
The result of this function could be not correct when using fractional value for HSE crystal.
Return values:
None

Definition at line 908 of file stm32f10x_rcc.c.

References RCC_ClocksTypeDef::ADCCLK_Frequency, ADCPrescTable, APBAHBPrescTable, CFGR_ADCPRE_Set_Mask, CFGR_HPRE_Set_Mask, CFGR_PLLMull_Mask, CFGR_PLLSRC_Mask, CFGR_PLLXTPRE_Mask, CFGR_PPRE1_Set_Mask, CFGR_PPRE2_Set_Mask, CFGR_SWS_Mask, RCC_ClocksTypeDef::HCLK_Frequency, HSE_VALUE, HSI_VALUE, RCC_ClocksTypeDef::PCLK1_Frequency, RCC_ClocksTypeDef::PCLK2_Frequency, RCC, RESET, and RCC_ClocksTypeDef::SYSCLK_Frequency.

Referenced by I2C_Init(), I2S_Init(), main(), and USART_Init().

FlagStatus RCC_GetFlagStatus ( uint8_t RCC_FLAG )

Checks whether the specified RCC flag is set or not.

Parameters:
RCC_FLAG,: specifies the flag to check.

For STM32_Connectivity_line_devices, this parameter can be one of the following values:

  • RCC_FLAG_HSIRDY: HSI oscillator clock ready
  • RCC_FLAG_HSERDY: HSE oscillator clock ready
  • RCC_FLAG_PLLRDY: PLL clock ready
  • RCC_FLAG_PLL2RDY: PLL2 clock ready
  • RCC_FLAG_PLL3RDY: PLL3 clock ready
  • RCC_FLAG_LSERDY: LSE oscillator clock ready
  • RCC_FLAG_LSIRDY: LSI oscillator clock ready
  • RCC_FLAG_PINRST: Pin reset
  • RCC_FLAG_PORRST: POR/PDR reset
  • RCC_FLAG_SFTRST: Software reset
  • RCC_FLAG_IWDGRST: Independent Watchdog reset
  • RCC_FLAG_WWDGRST: Window Watchdog reset
  • RCC_FLAG_LPWRRST: Low Power reset

For other_STM32_devices, this parameter can be one of the following values:

  • RCC_FLAG_HSIRDY: HSI oscillator clock ready
  • RCC_FLAG_HSERDY: HSE oscillator clock ready
  • RCC_FLAG_PLLRDY: PLL clock ready
  • RCC_FLAG_LSERDY: LSE oscillator clock ready
  • RCC_FLAG_LSIRDY: LSI oscillator clock ready
  • RCC_FLAG_PINRST: Pin reset
  • RCC_FLAG_PORRST: POR/PDR reset
  • RCC_FLAG_SFTRST: Software reset
  • RCC_FLAG_IWDGRST: Independent Watchdog reset
  • RCC_FLAG_WWDGRST: Window Watchdog reset
  • RCC_FLAG_LPWRRST: Low Power reset
Return values:
The new state of RCC_FLAG (SET or RESET).

Definition at line 1326 of file stm32f10x_rcc.c.

References assert_param, FLAG_Mask, IS_RCC_FLAG, RCC, RESET, and SET.

Referenced by HDMI_CEC_CommandCallBack(), main(), RCC_IRQHandler(), RCC_WaitForHSEStartUp(), RTC_Configuration(), SetSysClockTo24(), SetSysClockTo36(), SetSysClockTo48(), SetSysClockTo56(), SetSysClockTo72(), and SYSCLKConfig_STOP().

ITStatus RCC_GetITStatus ( uint8_t RCC_IT )

Checks whether the specified RCC interrupt has occurred or not.

Parameters:
RCC_IT,: specifies the RCC interrupt source to check.

For STM32_Connectivity_line_devices, this parameter can be one of the following values:

  • RCC_IT_LSIRDY: LSI ready interrupt
  • RCC_IT_LSERDY: LSE ready interrupt
  • RCC_IT_HSIRDY: HSI ready interrupt
  • RCC_IT_HSERDY: HSE ready interrupt
  • RCC_IT_PLLRDY: PLL ready interrupt
  • RCC_IT_PLL2RDY: PLL2 ready interrupt
  • RCC_IT_PLL3RDY: PLL3 ready interrupt
  • RCC_IT_CSS: Clock Security System interrupt

For other_STM32_devices, this parameter can be one of the following values:

  • RCC_IT_LSIRDY: LSI ready interrupt
  • RCC_IT_LSERDY: LSE ready interrupt
  • RCC_IT_HSIRDY: HSI ready interrupt
  • RCC_IT_HSERDY: HSE ready interrupt
  • RCC_IT_PLLRDY: PLL ready interrupt
  • RCC_IT_CSS: Clock Security System interrupt
Return values:
The new state of RCC_IT (SET or RESET).

Definition at line 1402 of file stm32f10x_rcc.c.

References assert_param, IS_RCC_GET_IT, RCC, RESET, and SET.

Referenced by NMI_Handler(), and RCC_IRQHandler().

uint8_t RCC_GetSYSCLKSource ( void )

Returns the clock source used as system clock.

Parameters:
None
Return values:
The clock source used as system clock. The returned value can be one of the following:

  • 0x00: HSI used as system clock
  • 0x04: HSE used as system clock
  • 0x08: PLL used as system clock

Definition at line 587 of file stm32f10x_rcc.c.

References CFGR_SWS_Mask, and RCC.

Referenced by HDMI_CEC_CommandCallBack(), SetSysClockTo24(), SetSysClockTo36(), SetSysClockTo48(), SetSysClockTo56(), SetSysClockTo72(), SetSysClockToHSE(), and SYSCLKConfig_STOP().

void RCC_HCLKConfig ( uint32_t RCC_SYSCLK )

Configures the AHB clock (HCLK).

Parameters:
RCC_SYSCLK,: defines the AHB clock divider. This clock is derived from the system clock (SYSCLK). This parameter can be one of the following values:

  • RCC_SYSCLK_Div1: AHB clock = SYSCLK
  • RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
  • RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
  • RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
  • RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
  • RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
  • RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
  • RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
  • RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
Return values:
None

Definition at line 608 of file stm32f10x_rcc.c.

References assert_param, CFGR_HPRE_Reset_Mask, IS_RCC_HCLK, and RCC.

Referenced by SetSysClockTo24(), SetSysClockTo36(), SetSysClockTo48(), SetSysClockTo56(), SetSysClockTo72(), and SetSysClockToHSE().

void RCC_HSEConfig ( uint32_t RCC_HSE )

Configures the External High Speed oscillator (HSE).

Note:
HSE can not be stopped if it is used directly or through the PLL as system clock.
Parameters:
RCC_HSE,: specifies the new state of the HSE. This parameter can be one of the following values:

  • RCC_HSE_OFF: HSE oscillator OFF
  • RCC_HSE_ON: HSE oscillator ON
  • RCC_HSE_Bypass: HSE oscillator bypassed with external clock
Return values:
None

Definition at line 270 of file stm32f10x_rcc.c.

References assert_param, CR_HSEBYP_Reset, CR_HSEBYP_Set, CR_HSEON_Reset, CR_HSEON_Set, IS_RCC_HSE, RCC, RCC_HSE_Bypass, and RCC_HSE_ON.

Referenced by NMI_Handler(), SetSysClockTo24(), SetSysClockTo36(), SetSysClockTo48(), SetSysClockTo56(), SetSysClockTo72(), SetSysClockToHSE(), and SYSCLKConfig_STOP().

void RCC_HSICmd ( FunctionalState NewState )

Enables or disables the Internal High Speed oscillator (HSI).

Note:
HSI can not be stopped if it is used directly or through the PLL as system clock.
Parameters:
NewState,: new state of the HSI. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 354 of file stm32f10x_rcc.c.

References assert_param, CR_HSION_BB, and IS_FUNCTIONAL_STATE.

void RCC_ITConfig | ( | uint8_t | RCC_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified RCC interrupts.

Parameters:
RCC_IT,: specifies the RCC interrupt sources to be enabled or disabled.

For STM32_Connectivity_line_devices, this parameter can be any combination of the following values

  • RCC_IT_LSIRDY: LSI ready interrupt
  • RCC_IT_LSERDY: LSE ready interrupt
  • RCC_IT_HSIRDY: HSI ready interrupt
  • RCC_IT_HSERDY: HSE ready interrupt
  • RCC_IT_PLLRDY: PLL ready interrupt
  • RCC_IT_PLL2RDY: PLL2 ready interrupt
  • RCC_IT_PLL3RDY: PLL3 ready interrupt

For other_STM32_devices, this parameter can be any combination of the following values

  • RCC_IT_LSIRDY: LSI ready interrupt
  • RCC_IT_LSERDY: LSE ready interrupt
  • RCC_IT_HSIRDY: HSI ready interrupt
  • RCC_IT_HSERDY: HSE ready interrupt
  • RCC_IT_PLLRDY: PLL ready interrupt
Parameters:
NewState,: new state of the specified RCC interrupts. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 700 of file stm32f10x_rcc.c.

References assert_param, CIR_BYTE2_ADDRESS, DISABLE, IS_FUNCTIONAL_STATE, and IS_RCC_IT.

Referenced by NMI_Handler().

void RCC_LSEConfig ( uint8_t RCC_LSE )

Configures the External Low Speed oscillator (LSE).

Parameters:
RCC_LSE,: specifies the new state of the LSE. This parameter can be one of the following values:

  • RCC_LSE_OFF: LSE oscillator OFF
  • RCC_LSE_ON: LSE oscillator ON
  • RCC_LSE_Bypass: LSE oscillator bypassed with external clock
Return values:
None

Definition at line 829 of file stm32f10x_rcc.c.

References assert_param, BDCR_ADDRESS, IS_RCC_LSE, RCC_LSE_Bypass, RCC_LSE_OFF, and RCC_LSE_ON.

Referenced by RTC_Configuration().

void RCC_LSICmd ( FunctionalState NewState )

Enables or disables the Internal Low Speed oscillator (LSI).

Note:
LSI can not be disabled if the IWDG is running.
Parameters:
NewState,: new state of the LSI. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 862 of file stm32f10x_rcc.c.

References assert_param, CSR_LSION_BB, and IS_FUNCTIONAL_STATE.

Referenced by main().

void RCC_MCOConfig ( uint8_t RCC_MCO )

Selects the clock source to output on MCO pin.

Parameters:
RCC_MCO,: specifies the clock source to output.

For STM32_Connectivity_line_devices, this parameter can be one of the following values:

  • RCC_MCO_NoClock: No clock selected
  • RCC_MCO_SYSCLK: System clock selected
  • RCC_MCO_HSI: HSI oscillator clock selected
  • RCC_MCO_HSE: HSE oscillator clock selected
  • RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected
  • RCC_MCO_PLL2CLK: PLL2 clock selected
  • RCC_MCO_PLL3CLK_Div2: PLL3 clock divided by 2 selected
  • RCC_MCO_XT1: External 3-25 MHz oscillator clock selected
  • RCC_MCO_PLL3CLK: PLL3 clock selected

For other_STM32_devices, this parameter can be one of the following values:

  • RCC_MCO_NoClock: No clock selected
  • RCC_MCO_SYSCLK: System clock selected
  • RCC_MCO_HSI: HSI oscillator clock selected
  • RCC_MCO_HSE: HSE oscillator clock selected
  • RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected
Return values:
None

Definition at line 1282 of file stm32f10x_rcc.c.

References assert_param, CFGR_BYTE4_ADDRESS, and IS_RCC_MCO.

Referenced by main().

void RCC_PCLK1Config ( uint32_t RCC_HCLK )

Configures the Low Speed APB clock (PCLK1).

Parameters:
RCC_HCLK,: defines the APB1 clock divider. This clock is derived from the AHB clock (HCLK). This parameter can be one of the following values:

  • RCC_HCLK_Div1: APB1 clock = HCLK
  • RCC_HCLK_Div2: APB1 clock = HCLK/2
  • RCC_HCLK_Div4: APB1 clock = HCLK/4
  • RCC_HCLK_Div8: APB1 clock = HCLK/8
  • RCC_HCLK_Div16: APB1 clock = HCLK/16
Return values:
None

Definition at line 634 of file stm32f10x_rcc.c.

References assert_param, CFGR_PPRE1_Reset_Mask, IS_RCC_PCLK, and RCC.

Referenced by SetSysClockTo24(), SetSysClockTo36(), SetSysClockTo48(), SetSysClockTo56(), SetSysClockTo72(), and SetSysClockToHSE().

void RCC_PCLK2Config ( uint32_t RCC_HCLK )

Configures the High Speed APB clock (PCLK2).

Parameters:
RCC_HCLK,: defines the APB2 clock divider. This clock is derived from the AHB clock (HCLK). This parameter can be one of the following values:

  • RCC_HCLK_Div1: APB2 clock = HCLK
  • RCC_HCLK_Div2: APB2 clock = HCLK/2
  • RCC_HCLK_Div4: APB2 clock = HCLK/4
  • RCC_HCLK_Div8: APB2 clock = HCLK/8
  • RCC_HCLK_Div16: APB2 clock = HCLK/16
Return values:
None

Definition at line 660 of file stm32f10x_rcc.c.

References assert_param, CFGR_PPRE2_Reset_Mask, IS_RCC_PCLK, and RCC.

Referenced by SetSysClockTo24(), SetSysClockTo36(), SetSysClockTo48(), SetSysClockTo56(), SetSysClockTo72(), and SetSysClockToHSE().

void RCC_PLLCmd ( FunctionalState NewState )

Enables or disables the PLL.

Note:
The PLL can not be disabled if it is used as system clock.
Parameters:
NewState,: new state of the PLL. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 401 of file stm32f10x_rcc.c.

References assert_param, CR_PLLON_BB, and IS_FUNCTIONAL_STATE.

Referenced by HDMI_CEC_CommandCallBack(), RCC_IRQHandler(), SetSysClockTo24(), SetSysClockTo36(), SetSysClockTo48(), SetSysClockTo56(), SetSysClockTo72(), and SYSCLKConfig_STOP().

void RCC_PLLConfig | ( | uint32_t | RCC_PLLSource,
 |  | uint32_t | RCC_PLLMul
 | ) |  |

Configures the PLL clock source and multiplication factor.

Note:
This function must be used only when the PLL is disabled.
Parameters:
RCC_PLLSource,: specifies the PLL entry clock source. For STM32_Connectivity_line_devices or STM32_Value_line_devices, this parameter can be one of the following values:

  • RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as PLL clock entry
  • RCC_PLLSource_PREDIV1: PREDIV1 clock selected as PLL clock entry For other_STM32_devices, this parameter can be one of the following values:
  • RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as PLL clock entry
  • RCC_PLLSource_HSE_Div1: HSE oscillator clock selected as PLL clock entry
  • RCC_PLLSource_HSE_Div2: HSE oscillator clock divided by 2 selected as PLL clock entry
RCC_PLLMul,: specifies the PLL multiplication factor. For STM32_Connectivity_line_devices, this parameter can be RCC_PLLMul_x where x:{[4,9], 6_5} For other_STM32_devices, this parameter can be RCC_PLLMul_x where x:[2,16]
Return values:
None

Definition at line 378 of file stm32f10x_rcc.c.

References assert_param, CFGR_PLL_Mask, IS_RCC_PLL_MUL, IS_RCC_PLL_SOURCE, and RCC.

Referenced by HDMI_CEC_CommandCallBack(), SetSysClockTo24(), SetSysClockTo36(), SetSysClockTo48(), SetSysClockTo56(), and SetSysClockTo72().

void RCC_RTCCLKCmd ( FunctionalState NewState )

Enables or disables the RTC clock.

Note:
This function must be used only after the RTC clock was selected using the RCC_RTCCLKConfig function.
Parameters:
NewState,: new state of the RTC clock. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 893 of file stm32f10x_rcc.c.

References assert_param, BDCR_RTCEN_BB, and IS_FUNCTIONAL_STATE.

Referenced by RTC_Configuration().

void RCC_RTCCLKConfig ( uint32_t RCC_RTCCLKSource )

Configures the RTC clock (RTCCLK).

Note:
Once the RTC clock is selected it can't be changed unless the Backup domain is reset.
Parameters:
RCC_RTCCLKSource,: specifies the RTC clock source. This parameter can be one of the following values:

  • RCC_RTCCLKSource_LSE: LSE selected as RTC clock
  • RCC_RTCCLKSource_LSI: LSI selected as RTC clock
  • RCC_RTCCLKSource_HSE_Div128: HSE clock divided by 128 selected as RTC clock
Return values:
None

Definition at line 879 of file stm32f10x_rcc.c.

References assert_param, IS_RCC_RTCCLK_SOURCE, and RCC.

Referenced by RTC_Configuration().

void RCC_SYSCLKConfig ( uint32_t RCC_SYSCLKSource )

Configures the system clock (SYSCLK).

Parameters:
RCC_SYSCLKSource,: specifies the clock source used as system clock. This parameter can be one of the following values:

  • RCC_SYSCLKSource_HSI: HSI selected as system clock
  • RCC_SYSCLKSource_HSE: HSE selected as system clock
  • RCC_SYSCLKSource_PLLCLK: PLL selected as system clock
Return values:
None

Definition at line 564 of file stm32f10x_rcc.c.

References assert_param, CFGR_SW_Mask, IS_RCC_SYSCLK_SOURCE, and RCC.

Referenced by HDMI_CEC_CommandCallBack(), RCC_IRQHandler(), SetSysClockTo24(), SetSysClockTo36(), SetSysClockTo48(), SetSysClockTo56(), SetSysClockTo72(), SetSysClockToHSE(), and SYSCLKConfig_STOP().

void RCC_USBCLKConfig ( uint32_t RCC_USBCLKSource )

Configures the USB clock (USBCLK).

Parameters:
RCC_USBCLKSource,: specifies the USB clock source. This clock is derived from the PLL output. This parameter can be one of the following values:

  • RCC_USBCLKSource_PLLCLK_1Div5: PLL clock divided by 1,5 selected as USB clock source
  • RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB clock source
Return values:
None

Definition at line 728 of file stm32f10x_rcc.c.

References assert_param, CFGR_USBPRE_BB, and IS_RCC_USBCLK_SOURCE.

ErrorStatus RCC_WaitForHSEStartUp ( void )

Waits for HSE start-up.

Parameters:
None
Return values:
An ErrorStatus enumuration value:

  • SUCCESS: HSE oscillator is stable and ready to use
  • ERROR: HSE oscillator not yet ready

Definition at line 304 of file stm32f10x_rcc.c.

References ERROR, HSE_STARTUP_TIMEOUT, RCC_FLAG_HSERDY, RCC_GetFlagStatus(), RESET, status, and SUCCESS.

Referenced by SetSysClockTo24(), SetSysClockTo36(), SetSysClockTo48(), SetSysClockTo56(), SetSysClockTo72(), SetSysClockToHSE(), and SYSCLKConfig_STOP().


STM32F10x Standard Peripherals Firmware Library: RCC_Private_TypesDefinitions

RCC_Private_TypesDefinitions

RCC


STM32F10x Standard Peripherals Firmware Library: RCC_Private_Defines

Defines

RCC_Private_Defines

RCC

Defines

#define | BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET)
#define | BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))
#define | BDCR_OFFSET (RCC_OFFSET + 0x20)
#define | BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))
#define | BDRST_BitNumber 0x10
#define | CFGR_ADCPRE_Reset_Mask ((uint32_t)0xFFFF3FFF)
#define | CFGR_ADCPRE_Set_Mask ((uint32_t)0x0000C000)
#define | CFGR_BYTE4_ADDRESS ((uint32_t)0x40021007)
#define | CFGR_HPRE_Reset_Mask ((uint32_t)0xFFFFFF0F)
#define | CFGR_HPRE_Set_Mask ((uint32_t)0x000000F0)
#define | CFGR_OFFSET (RCC_OFFSET + 0x04)
#define | CFGR_PLL_Mask ((uint32_t)0xFFC0FFFF)
#define | CFGR_PLLMull_Mask ((uint32_t)0x003C0000)
#define | CFGR_PLLSRC_Mask ((uint32_t)0x00010000)
#define | CFGR_PLLXTPRE_Mask ((uint32_t)0x00020000)
#define | CFGR_PPRE1_Reset_Mask ((uint32_t)0xFFFFF8FF)
#define | CFGR_PPRE1_Set_Mask ((uint32_t)0x00000700)
#define | CFGR_PPRE2_Reset_Mask ((uint32_t)0xFFFFC7FF)
#define | CFGR_PPRE2_Set_Mask ((uint32_t)0x00003800)
#define | CFGR_SW_Mask ((uint32_t)0xFFFFFFFC)
#define | CFGR_SWS_Mask ((uint32_t)0x0000000C)
#define | CFGR_USBPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (USBPRE_BitNumber * 4))
#define | CIR_BYTE2_ADDRESS ((uint32_t)0x40021009)
#define | CIR_BYTE3_ADDRESS ((uint32_t)0x4002100A)
#define | CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))
#define | CR_HSEBYP_Reset ((uint32_t)0xFFFBFFFF)
#define | CR_HSEBYP_Set ((uint32_t)0x00040000)
#define | CR_HSEON_Reset ((uint32_t)0xFFFEFFFF)
#define | CR_HSEON_Set ((uint32_t)0x00010000)
#define | CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))
#define | CR_HSITRIM_Mask ((uint32_t)0xFFFFFF07)
#define | CR_OFFSET (RCC_OFFSET + 0x00)
#define | CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))
#define | CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))
#define | CSR_OFFSET (RCC_OFFSET + 0x24)
#define | CSR_RMVF_Set ((uint32_t)0x01000000)
#define | CSSON_BitNumber 0x13
#define | FLAG_Mask ((uint8_t)0x1F)
#define | HSION_BitNumber 0x00
#define | LSION_BitNumber 0x00
#define | PLLON_BitNumber 0x18
#define | RCC_OFFSET (RCC_BASE - PERIPH_BASE)
#define | RTCEN_BitNumber 0x0F
#define | USBPRE_BitNumber 0x16

Define Documentation

#define BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET)

Definition at line 175 of file stm32f10x_rcc.c.

Referenced by RCC_LSEConfig().

#define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))

Definition at line 96 of file stm32f10x_rcc.c.

Referenced by RCC_BackupResetCmd().

#define BDCR_OFFSET (RCC_OFFSET + 0x20)

Definition at line 90 of file stm32f10x_rcc.c.

#define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))

Definition at line 92 of file stm32f10x_rcc.c.

Referenced by RCC_RTCCLKCmd().

#define BDRST_BitNumber 0x10

Definition at line 95 of file stm32f10x_rcc.c.

#define CFGR_ADCPRE_Reset_Mask ((uint32_t)0xFFFF3FFF)

Definition at line 145 of file stm32f10x_rcc.c.

Referenced by RCC_ADCCLKConfig().

#define CFGR_ADCPRE_Set_Mask ((uint32_t)0x0000C000)

Definition at line 146 of file stm32f10x_rcc.c.

Referenced by RCC_GetClocksFreq().

#define CFGR_BYTE4_ADDRESS ((uint32_t)0x40021007)

Definition at line 172 of file stm32f10x_rcc.c.

Referenced by RCC_MCOConfig().

#define CFGR_HPRE_Reset_Mask ((uint32_t)0xFFFFFF0F)

Definition at line 139 of file stm32f10x_rcc.c.

Referenced by RCC_HCLKConfig().

#define CFGR_HPRE_Set_Mask ((uint32_t)0x000000F0)

Definition at line 140 of file stm32f10x_rcc.c.

Referenced by RCC_GetClocksFreq().

#define CFGR_OFFSET (RCC_OFFSET + 0x04)

Definition at line 77 of file stm32f10x_rcc.c.

#define CFGR_PLL_Mask ((uint32_t)0xFFC0FFFF)

Definition at line 131 of file stm32f10x_rcc.c.

Referenced by RCC_PLLConfig().

#define CFGR_PLLMull_Mask ((uint32_t)0x003C0000)

Definition at line 134 of file stm32f10x_rcc.c.

Referenced by RCC_GetClocksFreq().

#define CFGR_PLLSRC_Mask ((uint32_t)0x00010000)

Definition at line 135 of file stm32f10x_rcc.c.

Referenced by RCC_GetClocksFreq().

#define CFGR_PLLXTPRE_Mask ((uint32_t)0x00020000)

Definition at line 136 of file stm32f10x_rcc.c.

Referenced by RCC_GetClocksFreq().

#define CFGR_PPRE1_Reset_Mask ((uint32_t)0xFFFFF8FF)

Definition at line 141 of file stm32f10x_rcc.c.

Referenced by RCC_PCLK1Config().

#define CFGR_PPRE1_Set_Mask ((uint32_t)0x00000700)

Definition at line 142 of file stm32f10x_rcc.c.

Referenced by RCC_GetClocksFreq().

#define CFGR_PPRE2_Reset_Mask ((uint32_t)0xFFFFC7FF)

Definition at line 143 of file stm32f10x_rcc.c.

Referenced by RCC_PCLK2Config().

#define CFGR_PPRE2_Set_Mask ((uint32_t)0x00003800)

Definition at line 144 of file stm32f10x_rcc.c.

Referenced by RCC_GetClocksFreq().

#define CFGR_SW_Mask ((uint32_t)0xFFFFFFFC)

Definition at line 138 of file stm32f10x_rcc.c.

Referenced by RCC_SYSCLKConfig().

#define CFGR_SWS_Mask ((uint32_t)0x0000000C)

Definition at line 137 of file stm32f10x_rcc.c.

Referenced by RCC_GetClocksFreq(), and RCC_GetSYSCLKSource().

#define CFGR_USBPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (USBPRE_BitNumber * 4))

Definition at line 81 of file stm32f10x_rcc.c.

Referenced by RCC_USBCLKConfig().

#define CIR_BYTE2_ADDRESS ((uint32_t)0x40021009)

Definition at line 166 of file stm32f10x_rcc.c.

Referenced by RCC_ITConfig().

#define CIR_BYTE3_ADDRESS ((uint32_t)0x4002100A)

Definition at line 169 of file stm32f10x_rcc.c.

Referenced by RCC_ClearITPendingBit().

#define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))

Definition at line 72 of file stm32f10x_rcc.c.

Referenced by RCC_ClockSecuritySystemCmd().

#define CR_HSEBYP_Reset ((uint32_t)0xFFFBFFFF)

Definition at line 121 of file stm32f10x_rcc.c.

Referenced by RCC_HSEConfig().

#define CR_HSEBYP_Set ((uint32_t)0x00040000)

Definition at line 122 of file stm32f10x_rcc.c.

Referenced by RCC_HSEConfig().

#define CR_HSEON_Reset ((uint32_t)0xFFFEFFFF)

Definition at line 123 of file stm32f10x_rcc.c.

Referenced by RCC_HSEConfig().

#define CR_HSEON_Set ((uint32_t)0x00010000)

Definition at line 124 of file stm32f10x_rcc.c.

Referenced by RCC_HSEConfig().

#define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))

Definition at line 54 of file stm32f10x_rcc.c.

Referenced by RCC_HSICmd().

#define CR_HSITRIM_Mask ((uint32_t)0xFFFFFF07)

Definition at line 125 of file stm32f10x_rcc.c.

Referenced by RCC_AdjustHSICalibrationValue().

#define CR_OFFSET (RCC_OFFSET + 0x00)

Definition at line 52 of file stm32f10x_rcc.c.

#define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))

Definition at line 58 of file stm32f10x_rcc.c.

Referenced by RCC_PLLCmd().

#define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))

Definition at line 103 of file stm32f10x_rcc.c.

Referenced by RCC_LSICmd().

#define CSR_OFFSET (RCC_OFFSET + 0x24)

Definition at line 101 of file stm32f10x_rcc.c.

#define CSR_RMVF_Set ((uint32_t)0x01000000)

Definition at line 149 of file stm32f10x_rcc.c.

Referenced by RCC_ClearFlag().

#define CSSON_BitNumber 0x13

Definition at line 71 of file stm32f10x_rcc.c.

#define FLAG_Mask ((uint8_t)0x1F)

Definition at line 163 of file stm32f10x_rcc.c.

Referenced by RCC_GetFlagStatus().

#define HSION_BitNumber 0x00

Definition at line 53 of file stm32f10x_rcc.c.

#define LSION_BitNumber 0x00

Definition at line 102 of file stm32f10x_rcc.c.

#define PLLON_BitNumber 0x18

Definition at line 57 of file stm32f10x_rcc.c.

#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)

Definition at line 47 of file stm32f10x_rcc.c.

#define RTCEN_BitNumber 0x0F

Definition at line 91 of file stm32f10x_rcc.c.

#define USBPRE_BitNumber 0x16

Definition at line 80 of file stm32f10x_rcc.c.


STM32F10x Standard Peripherals Firmware Library: RCC_Private_Macros

RCC_Private_Macros

RCC


STM32F10x Standard Peripherals Firmware Library: RCC_Private_Variables

Variables

RCC_Private_Variables

RCC

Variables

static __I uint8_t | ADCPrescTable [4] = {2, 4, 6, 8}
static __I uint8_t | APBAHBPrescTable [16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}

Variable Documentation

__I uint8_t ADCPrescTable[4] = {2, 4, 6, 8} [static]

Definition at line 194 of file stm32f10x_rcc.c.

Referenced by RCC_GetClocksFreq().

__I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9} [static]

Definition at line 193 of file stm32f10x_rcc.c.

Referenced by RCC_GetClocksFreq().


STM32F10x Standard Peripherals Firmware Library: RCC_Private_FunctionPrototypes

RCC_Private_FunctionPrototypes

RCC


STM32F10x Standard Peripherals Firmware Library: RCC_Private_Functions

Functions

RCC_Private_Functions

RCC

Functions

void | RCC_ADCCLKConfig (uint32_t RCC_PCLK2)
Configures the ADC clock (ADCCLK).
void | RCC_AdjustHSICalibrationValue (uint8_t HSICalibrationValue)
Adjusts the Internal High Speed oscillator (HSI) calibration value.
void | RCC_AHBPeriphClockCmd (uint32_t RCC_AHBPeriph, FunctionalState NewState)
Enables or disables the AHB peripheral clock.
void | RCC_APB1PeriphClockCmd (uint32_t RCC_APB1Periph, FunctionalState NewState)
Enables or disables the Low Speed APB (APB1) peripheral clock.
void | RCC_APB1PeriphResetCmd (uint32_t RCC_APB1Periph, FunctionalState NewState)
Forces or releases Low Speed APB (APB1) peripheral reset.
void | RCC_APB2PeriphClockCmd (uint32_t RCC_APB2Periph, FunctionalState NewState)
Enables or disables the High Speed APB (APB2) peripheral clock.
void | RCC_APB2PeriphResetCmd (uint32_t RCC_APB2Periph, FunctionalState NewState)
Forces or releases High Speed APB (APB2) peripheral reset.
void | RCC_BackupResetCmd (FunctionalState NewState)
Forces or releases the Backup domain reset.
void | RCC_ClearFlag (void)
Clears the RCC reset flags.
void | RCC_ClearITPendingBit (uint8_t RCC_IT)
Clears the RCC's interrupt pending bits.
void | RCC_ClockSecuritySystemCmd (FunctionalState NewState)
Enables or disables the Clock Security System.
void | RCC_DeInit (void)
Resets the RCC clock configuration to the default reset state.
void | RCC_GetClocksFreq (RCC_ClocksTypeDef *RCC_Clocks)
Returns the frequencies of different on chip clocks.
FlagStatus | RCC_GetFlagStatus (uint8_t RCC_FLAG)
Checks whether the specified RCC flag is set or not.
ITStatus | RCC_GetITStatus (uint8_t RCC_IT)
Checks whether the specified RCC interrupt has occurred or not.
uint8_t | RCC_GetSYSCLKSource (void)
Returns the clock source used as system clock.
void | RCC_HCLKConfig (uint32_t RCC_SYSCLK)
Configures the AHB clock (HCLK).
void | RCC_HSEConfig (uint32_t RCC_HSE)
Configures the External High Speed oscillator (HSE).
void | RCC_HSICmd (FunctionalState NewState)
Enables or disables the Internal High Speed oscillator (HSI).
void | RCC_ITConfig (uint8_t RCC_IT, FunctionalState NewState)
Enables or disables the specified RCC interrupts.
void | RCC_LSEConfig (uint8_t RCC_LSE)
Configures the External Low Speed oscillator (LSE).
void | RCC_LSICmd (FunctionalState NewState)
Enables or disables the Internal Low Speed oscillator (LSI).
void | RCC_MCOConfig (uint8_t RCC_MCO)
Selects the clock source to output on MCO pin.
void | RCC_PCLK1Config (uint32_t RCC_HCLK)
Configures the Low Speed APB clock (PCLK1).
void | RCC_PCLK2Config (uint32_t RCC_HCLK)
Configures the High Speed APB clock (PCLK2).
void | RCC_PLLCmd (FunctionalState NewState)
Enables or disables the PLL.
void | RCC_PLLConfig (uint32_t RCC_PLLSource, uint32_t RCC_PLLMul)
Configures the PLL clock source and multiplication factor.
void | RCC_RTCCLKCmd (FunctionalState NewState)
Enables or disables the RTC clock.
void | RCC_RTCCLKConfig (uint32_t RCC_RTCCLKSource)
Configures the RTC clock (RTCCLK).
void | RCC_SYSCLKConfig (uint32_t RCC_SYSCLKSource)
Configures the system clock (SYSCLK).
void | RCC_USBCLKConfig (uint32_t RCC_USBCLKSource)
Configures the USB clock (USBCLK).
ErrorStatus | RCC_WaitForHSEStartUp (void)
Waits for HSE start-up.

Function Documentation

void RCC_ADCCLKConfig ( uint32_t RCC_PCLK2 )

Configures the ADC clock (ADCCLK).

Parameters:
RCC_PCLK2,: defines the ADC clock divider. This clock is derived from the APB2 clock (PCLK2). This parameter can be one of the following values:

  • RCC_PCLK2_Div2: ADC clock = PCLK2/2
  • RCC_PCLK2_Div4: ADC clock = PCLK2/4
  • RCC_PCLK2_Div6: ADC clock = PCLK2/6
  • RCC_PCLK2_Div8: ADC clock = PCLK2/8
Return values:
None

Definition at line 766 of file stm32f10x_rcc.c.

References assert_param, CFGR_ADCPRE_Reset_Mask, IS_RCC_ADCCLK, and RCC.

Referenced by RCC_Configuration().

void RCC_AdjustHSICalibrationValue ( uint8_t HSICalibrationValue )

Adjusts the Internal High Speed oscillator (HSI) calibration value.

Parameters:
HSICalibrationValue,: specifies the calibration trimming value. This parameter must be a number between 0 and 0x1F.
Return values:
None

Definition at line 334 of file stm32f10x_rcc.c.

References assert_param, CR_HSITRIM_Mask, IS_RCC_CALIBRATION_VALUE, and RCC.

void RCC_AHBPeriphClockCmd | ( | uint32_t | RCC_AHBPeriph,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the AHB peripheral clock.

Parameters:
RCC_AHBPeriph,: specifies the AHB peripheral to gates its clock.

For STM32_Connectivity_line_devices, this parameter can be any combination of the following values:

  • RCC_AHBPeriph_DMA1
  • RCC_AHBPeriph_DMA2
  • RCC_AHBPeriph_SRAM
  • RCC_AHBPeriph_FLITF
  • RCC_AHBPeriph_CRC
  • RCC_AHBPeriph_OTG_FS
  • RCC_AHBPeriph_ETH_MAC
  • RCC_AHBPeriph_ETH_MAC_Tx
  • RCC_AHBPeriph_ETH_MAC_Rx

For other_STM32_devices, this parameter can be any combination of the following values:

  • RCC_AHBPeriph_DMA1
  • RCC_AHBPeriph_DMA2
  • RCC_AHBPeriph_SRAM
  • RCC_AHBPeriph_FLITF
  • RCC_AHBPeriph_CRC
  • RCC_AHBPeriph_FSMC
  • RCC_AHBPeriph_SDIO
Note:
SRAM and FLITF clock can be disabled only during sleep mode.
Parameters:
NewState,: new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1064 of file stm32f10x_rcc.c.

References assert_param, DISABLE, IS_FUNCTIONAL_STATE, IS_RCC_AHB_PERIPH, and RCC.

Referenced by IOE_DMA_Config(), LCD_CtrlLinesConfig(), LCD_GPIOConfig(), LCD_SPIConfig(), LM75_DMA_Config(), LM75_LowLevel_Init(), main(), OneNAND_Init(), RCC_Configuration(), SD_LowLevel_DeInit(), SD_LowLevel_Init(), sEE_LowLevel_Init(), STM_EVAL_COMInit(), STM_EVAL_LEDInit(), and STM_EVAL_PBInit().

void RCC_APB1PeriphClockCmd | ( | uint32_t | RCC_APB1Periph,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the Low Speed APB (APB1) peripheral clock.

Parameters:
RCC_APB1Periph,: specifies the APB1 peripheral to gates its clock. This parameter can be any combination of the following values:

  • RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4, RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7, RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3, RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4, RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2, RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP, RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_CEC, RCC_APB1Periph_TIM12, RCC_APB1Periph_TIM13, RCC_APB1Periph_TIM14
NewState,: new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1126 of file stm32f10x_rcc.c.

References assert_param, DISABLE, IS_FUNCTIONAL_STATE, IS_RCC_APB1_PERIPH, and RCC.

Referenced by CAN_Config(), HDMI_CEC_Init(), IOE_GPIO_Config(), LCD_DeInit(), LCD_GLASS_Init(), LCD_SPIConfig(), LM75_LowLevel_DeInit(), LM75_LowLevel_Init(), main(), SD_LowLevel_DeInit(), SD_LowLevel_Init(), sEE_LowLevel_DeInit(), sEE_LowLevel_Init(), STM32L152_LCD_DeInit(), STM_EVAL_COMInit(), TIM5_ConfigForLSI(), and TIM_Config().

void RCC_APB1PeriphResetCmd | ( | uint32_t | RCC_APB1Periph,
 |  | FunctionalState | NewState
 | ) |  |

Forces or releases Low Speed APB (APB1) peripheral reset.

Parameters:
RCC_APB1Periph,: specifies the APB1 peripheral to reset. This parameter can be any combination of the following values:

  • RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4, RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7, RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3, RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4, RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2, RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP, RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_CEC, RCC_APB1Periph_TIM12, RCC_APB1Periph_TIM13, RCC_APB1Periph_TIM14
NewState,: new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1216 of file stm32f10x_rcc.c.

References assert_param, DISABLE, IS_FUNCTIONAL_STATE, IS_RCC_APB1_PERIPH, and RCC.

Referenced by CAN_DeInit(), CEC_DeInit(), DAC_DeInit(), I2C_DeInit(), IOE_GPIO_Config(), PWR_DeInit(), sEE_LowLevel_Init(), SPI_I2S_DeInit(), TIM_DeInit(), USART_DeInit(), and WWDG_DeInit().

void RCC_APB2PeriphClockCmd | ( | uint32_t | RCC_APB2Periph,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the High Speed APB (APB2) peripheral clock.

Parameters:
RCC_APB2Periph,: specifies the APB2 peripheral to gates its clock. This parameter can be any combination of the following values:

  • RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB, RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE, RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1, RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1, RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3, RCC_APB2Periph_TIM15, RCC_APB2Periph_TIM16, RCC_APB2Periph_TIM17, RCC_APB2Periph_TIM9, RCC_APB2Periph_TIM10, RCC_APB2Periph_TIM11
NewState,: new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1095 of file stm32f10x_rcc.c.

References assert_param, DISABLE, IS_FUNCTIONAL_STATE, IS_RCC_APB2_PERIPH, and RCC.

Referenced by CAN_Config(), EXTI0_Config(), EXTI9_5_Config(), HDMI_CEC_Init(), IOE_EXTI_Config(), IOE_GPIO_Config(), LCD_CtrlLinesConfig(), LCD_SPIConfig(), LM75_LowLevel_Init(), main(), NAND_Init(), NOR_Init(), OneNAND_Init(), RCC_Configuration(), SD_LowLevel_DeInit(), SD_LowLevel_Init(), sEE_LowLevel_Init(), sFLASH_LowLevel_DeInit(), sFLASH_LowLevel_Init(), SRAM_Init(), STM_EVAL_COMInit(), STM_EVAL_LEDInit(), and STM_EVAL_PBInit().

void RCC_APB2PeriphResetCmd | ( | uint32_t | RCC_APB2Periph,
 |  | FunctionalState | NewState
 | ) |  |

Forces or releases High Speed APB (APB2) peripheral reset.

Parameters:
RCC_APB2Periph,: specifies the APB2 peripheral to reset. This parameter can be any combination of the following values:

  • RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB, RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE, RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1, RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1, RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3, RCC_APB2Periph_TIM15, RCC_APB2Periph_TIM16, RCC_APB2Periph_TIM17, RCC_APB2Periph_TIM9, RCC_APB2Periph_TIM10, RCC_APB2Periph_TIM11
NewState,: new state of the specified peripheral reset. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1185 of file stm32f10x_rcc.c.

References assert_param, DISABLE, IS_FUNCTIONAL_STATE, IS_RCC_APB2_PERIPH, and RCC.

Referenced by ADC_DeInit(), GPIO_AFIODeInit(), GPIO_DeInit(), SPI_I2S_DeInit(), TIM_DeInit(), and USART_DeInit().

void RCC_BackupResetCmd ( FunctionalState NewState )

Forces or releases the Backup domain reset.

Parameters:
NewState,: new state of the Backup domain reset. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1237 of file stm32f10x_rcc.c.

References assert_param, BDCR_BDRST_BB, and IS_FUNCTIONAL_STATE.

Referenced by BKP_DeInit().

void RCC_ClearFlag ( void )

Clears the RCC reset flags.

Note:
The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
Parameters:
None
Return values:
None

Definition at line 1371 of file stm32f10x_rcc.c.

References CSR_RMVF_Set, and RCC.

Referenced by main().

void RCC_ClearITPendingBit ( uint8_t RCC_IT )

Clears the RCC's interrupt pending bits.

Parameters:
RCC_IT,: specifies the interrupt pending bit to clear.

For STM32_Connectivity_line_devices, this parameter can be any combination of the following values:

  • RCC_IT_LSIRDY: LSI ready interrupt
  • RCC_IT_LSERDY: LSE ready interrupt
  • RCC_IT_HSIRDY: HSI ready interrupt
  • RCC_IT_HSERDY: HSE ready interrupt
  • RCC_IT_PLLRDY: PLL ready interrupt
  • RCC_IT_PLL2RDY: PLL2 ready interrupt
  • RCC_IT_PLL3RDY: PLL3 ready interrupt
  • RCC_IT_CSS: Clock Security System interrupt

For other_STM32_devices, this parameter can be any combination of the following values:

  • RCC_IT_LSIRDY: LSI ready interrupt
  • RCC_IT_LSERDY: LSE ready interrupt
  • RCC_IT_HSIRDY: HSI ready interrupt
  • RCC_IT_HSERDY: HSE ready interrupt
  • RCC_IT_PLLRDY: PLL ready interrupt
  • RCC_IT_CSS: Clock Security System interrupt
    Return values:
    None

Definition at line 1448 of file stm32f10x_rcc.c.

References assert_param, CIR_BYTE3_ADDRESS, and IS_RCC_CLEAR_IT.

Referenced by NMI_Handler(), and RCC_IRQHandler().

void RCC_ClockSecuritySystemCmd ( FunctionalState NewState )

Enables or disables the Clock Security System.

Parameters:
NewState,: new state of the Clock Security System.. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1250 of file stm32f10x_rcc.c.

References assert_param, CR_CSSON_BB, and IS_FUNCTIONAL_STATE.

Referenced by main().

void RCC_DeInit ( void )

Resets the RCC clock configuration to the default reset state.

Parameters:
None
Return values:
None

Definition at line 217 of file stm32f10x_rcc.c.

References RCC.

Referenced by SetSysClockTo24(), SetSysClockTo36(), SetSysClockTo48(), SetSysClockTo56(), SetSysClockTo72(), and SetSysClockToHSE().

void RCC_GetClocksFreq ( RCC_ClocksTypeDef * RCC_Clocks )

Returns the frequencies of different on chip clocks.

Parameters:
RCC_Clocks,: pointer to a RCC_ClocksTypeDef structure which will hold the clocks frequencies.
Note:
The result of this function could be not correct when using fractional value for HSE crystal.
Return values:
None

Definition at line 908 of file stm32f10x_rcc.c.

References RCC_ClocksTypeDef::ADCCLK_Frequency, ADCPrescTable, APBAHBPrescTable, CFGR_ADCPRE_Set_Mask, CFGR_HPRE_Set_Mask, CFGR_PLLMull_Mask, CFGR_PLLSRC_Mask, CFGR_PLLXTPRE_Mask, CFGR_PPRE1_Set_Mask, CFGR_PPRE2_Set_Mask, CFGR_SWS_Mask, RCC_ClocksTypeDef::HCLK_Frequency, HSE_VALUE, HSI_VALUE, RCC_ClocksTypeDef::PCLK1_Frequency, RCC_ClocksTypeDef::PCLK2_Frequency, RCC, RESET, and RCC_ClocksTypeDef::SYSCLK_Frequency.

Referenced by I2C_Init(), I2S_Init(), main(), and USART_Init().

FlagStatus RCC_GetFlagStatus ( uint8_t RCC_FLAG )

Checks whether the specified RCC flag is set or not.

Parameters:
RCC_FLAG,: specifies the flag to check.

For STM32_Connectivity_line_devices, this parameter can be one of the following values:

  • RCC_FLAG_HSIRDY: HSI oscillator clock ready
  • RCC_FLAG_HSERDY: HSE oscillator clock ready
  • RCC_FLAG_PLLRDY: PLL clock ready
  • RCC_FLAG_PLL2RDY: PLL2 clock ready
  • RCC_FLAG_PLL3RDY: PLL3 clock ready
  • RCC_FLAG_LSERDY: LSE oscillator clock ready
  • RCC_FLAG_LSIRDY: LSI oscillator clock ready
  • RCC_FLAG_PINRST: Pin reset
  • RCC_FLAG_PORRST: POR/PDR reset
  • RCC_FLAG_SFTRST: Software reset
  • RCC_FLAG_IWDGRST: Independent Watchdog reset
  • RCC_FLAG_WWDGRST: Window Watchdog reset
  • RCC_FLAG_LPWRRST: Low Power reset

For other_STM32_devices, this parameter can be one of the following values:

  • RCC_FLAG_HSIRDY: HSI oscillator clock ready
  • RCC_FLAG_HSERDY: HSE oscillator clock ready
  • RCC_FLAG_PLLRDY: PLL clock ready
  • RCC_FLAG_LSERDY: LSE oscillator clock ready
  • RCC_FLAG_LSIRDY: LSI oscillator clock ready
  • RCC_FLAG_PINRST: Pin reset
  • RCC_FLAG_PORRST: POR/PDR reset
  • RCC_FLAG_SFTRST: Software reset
  • RCC_FLAG_IWDGRST: Independent Watchdog reset
  • RCC_FLAG_WWDGRST: Window Watchdog reset
  • RCC_FLAG_LPWRRST: Low Power reset
Return values:
The new state of RCC_FLAG (SET or RESET).

Definition at line 1326 of file stm32f10x_rcc.c.

References assert_param, FLAG_Mask, IS_RCC_FLAG, RCC, RESET, and SET.

Referenced by HDMI_CEC_CommandCallBack(), main(), RCC_IRQHandler(), RCC_WaitForHSEStartUp(), RTC_Configuration(), SetSysClockTo24(), SetSysClockTo36(), SetSysClockTo48(), SetSysClockTo56(), SetSysClockTo72(), and SYSCLKConfig_STOP().

ITStatus RCC_GetITStatus ( uint8_t RCC_IT )

Checks whether the specified RCC interrupt has occurred or not.

Parameters:
RCC_IT,: specifies the RCC interrupt source to check.

For STM32_Connectivity_line_devices, this parameter can be one of the following values:

  • RCC_IT_LSIRDY: LSI ready interrupt
  • RCC_IT_LSERDY: LSE ready interrupt
  • RCC_IT_HSIRDY: HSI ready interrupt
  • RCC_IT_HSERDY: HSE ready interrupt
  • RCC_IT_PLLRDY: PLL ready interrupt
  • RCC_IT_PLL2RDY: PLL2 ready interrupt
  • RCC_IT_PLL3RDY: PLL3 ready interrupt
  • RCC_IT_CSS: Clock Security System interrupt

For other_STM32_devices, this parameter can be one of the following values:

  • RCC_IT_LSIRDY: LSI ready interrupt
  • RCC_IT_LSERDY: LSE ready interrupt
  • RCC_IT_HSIRDY: HSI ready interrupt
  • RCC_IT_HSERDY: HSE ready interrupt
  • RCC_IT_PLLRDY: PLL ready interrupt
  • RCC_IT_CSS: Clock Security System interrupt
Return values:
The new state of RCC_IT (SET or RESET).

Definition at line 1402 of file stm32f10x_rcc.c.

References assert_param, IS_RCC_GET_IT, RCC, RESET, and SET.

Referenced by NMI_Handler(), and RCC_IRQHandler().

uint8_t RCC_GetSYSCLKSource ( void )

Returns the clock source used as system clock.

Parameters:
None
Return values:
The clock source used as system clock. The returned value can be one of the following:

  • 0x00: HSI used as system clock
  • 0x04: HSE used as system clock
  • 0x08: PLL used as system clock

Definition at line 587 of file stm32f10x_rcc.c.

References CFGR_SWS_Mask, and RCC.

Referenced by HDMI_CEC_CommandCallBack(), SetSysClockTo24(), SetSysClockTo36(), SetSysClockTo48(), SetSysClockTo56(), SetSysClockTo72(), SetSysClockToHSE(), and SYSCLKConfig_STOP().

void RCC_HCLKConfig ( uint32_t RCC_SYSCLK )

Configures the AHB clock (HCLK).

Parameters:
RCC_SYSCLK,: defines the AHB clock divider. This clock is derived from the system clock (SYSCLK). This parameter can be one of the following values:

  • RCC_SYSCLK_Div1: AHB clock = SYSCLK
  • RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
  • RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
  • RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
  • RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
  • RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
  • RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
  • RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
  • RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
Return values:
None

Definition at line 608 of file stm32f10x_rcc.c.

References assert_param, CFGR_HPRE_Reset_Mask, IS_RCC_HCLK, and RCC.

Referenced by SetSysClockTo24(), SetSysClockTo36(), SetSysClockTo48(), SetSysClockTo56(), SetSysClockTo72(), and SetSysClockToHSE().

void RCC_HSEConfig ( uint32_t RCC_HSE )

Configures the External High Speed oscillator (HSE).

Note:
HSE can not be stopped if it is used directly or through the PLL as system clock.
Parameters:
RCC_HSE,: specifies the new state of the HSE. This parameter can be one of the following values:

  • RCC_HSE_OFF: HSE oscillator OFF
  • RCC_HSE_ON: HSE oscillator ON
  • RCC_HSE_Bypass: HSE oscillator bypassed with external clock
Return values:
None

Definition at line 270 of file stm32f10x_rcc.c.

References assert_param, CR_HSEBYP_Reset, CR_HSEBYP_Set, CR_HSEON_Reset, CR_HSEON_Set, IS_RCC_HSE, RCC, RCC_HSE_Bypass, and RCC_HSE_ON.

Referenced by NMI_Handler(), SetSysClockTo24(), SetSysClockTo36(), SetSysClockTo48(), SetSysClockTo56(), SetSysClockTo72(), SetSysClockToHSE(), and SYSCLKConfig_STOP().

void RCC_HSICmd ( FunctionalState NewState )

Enables or disables the Internal High Speed oscillator (HSI).

Note:
HSI can not be stopped if it is used directly or through the PLL as system clock.
Parameters:
NewState,: new state of the HSI. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 354 of file stm32f10x_rcc.c.

References assert_param, CR_HSION_BB, and IS_FUNCTIONAL_STATE.

void RCC_ITConfig | ( | uint8_t | RCC_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified RCC interrupts.

Parameters:
RCC_IT,: specifies the RCC interrupt sources to be enabled or disabled.

For STM32_Connectivity_line_devices, this parameter can be any combination of the following values

  • RCC_IT_LSIRDY: LSI ready interrupt
  • RCC_IT_LSERDY: LSE ready interrupt
  • RCC_IT_HSIRDY: HSI ready interrupt
  • RCC_IT_HSERDY: HSE ready interrupt
  • RCC_IT_PLLRDY: PLL ready interrupt
  • RCC_IT_PLL2RDY: PLL2 ready interrupt
  • RCC_IT_PLL3RDY: PLL3 ready interrupt

For other_STM32_devices, this parameter can be any combination of the following values

  • RCC_IT_LSIRDY: LSI ready interrupt
  • RCC_IT_LSERDY: LSE ready interrupt
  • RCC_IT_HSIRDY: HSI ready interrupt
  • RCC_IT_HSERDY: HSE ready interrupt
  • RCC_IT_PLLRDY: PLL ready interrupt
Parameters:
NewState,: new state of the specified RCC interrupts. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 700 of file stm32f10x_rcc.c.

References assert_param, CIR_BYTE2_ADDRESS, DISABLE, IS_FUNCTIONAL_STATE, and IS_RCC_IT.

Referenced by NMI_Handler().

void RCC_LSEConfig ( uint8_t RCC_LSE )

Configures the External Low Speed oscillator (LSE).

Parameters:
RCC_LSE,: specifies the new state of the LSE. This parameter can be one of the following values:

  • RCC_LSE_OFF: LSE oscillator OFF
  • RCC_LSE_ON: LSE oscillator ON
  • RCC_LSE_Bypass: LSE oscillator bypassed with external clock
Return values:
None

Definition at line 829 of file stm32f10x_rcc.c.

References assert_param, BDCR_ADDRESS, IS_RCC_LSE, RCC_LSE_Bypass, RCC_LSE_OFF, and RCC_LSE_ON.

Referenced by RTC_Configuration().

void RCC_LSICmd ( FunctionalState NewState )

Enables or disables the Internal Low Speed oscillator (LSI).

Note:
LSI can not be disabled if the IWDG is running.
Parameters:
NewState,: new state of the LSI. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 862 of file stm32f10x_rcc.c.

References assert_param, CSR_LSION_BB, and IS_FUNCTIONAL_STATE.

Referenced by main().

void RCC_MCOConfig ( uint8_t RCC_MCO )

Selects the clock source to output on MCO pin.

Parameters:
RCC_MCO,: specifies the clock source to output.

For STM32_Connectivity_line_devices, this parameter can be one of the following values:

  • RCC_MCO_NoClock: No clock selected
  • RCC_MCO_SYSCLK: System clock selected
  • RCC_MCO_HSI: HSI oscillator clock selected
  • RCC_MCO_HSE: HSE oscillator clock selected
  • RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected
  • RCC_MCO_PLL2CLK: PLL2 clock selected
  • RCC_MCO_PLL3CLK_Div2: PLL3 clock divided by 2 selected
  • RCC_MCO_XT1: External 3-25 MHz oscillator clock selected
  • RCC_MCO_PLL3CLK: PLL3 clock selected

For other_STM32_devices, this parameter can be one of the following values:

  • RCC_MCO_NoClock: No clock selected
  • RCC_MCO_SYSCLK: System clock selected
  • RCC_MCO_HSI: HSI oscillator clock selected
  • RCC_MCO_HSE: HSE oscillator clock selected
  • RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected
Return values:
None

Definition at line 1282 of file stm32f10x_rcc.c.

References assert_param, CFGR_BYTE4_ADDRESS, and IS_RCC_MCO.

Referenced by main().

void RCC_PCLK1Config ( uint32_t RCC_HCLK )

Configures the Low Speed APB clock (PCLK1).

Parameters:
RCC_HCLK,: defines the APB1 clock divider. This clock is derived from the AHB clock (HCLK). This parameter can be one of the following values:

  • RCC_HCLK_Div1: APB1 clock = HCLK
  • RCC_HCLK_Div2: APB1 clock = HCLK/2
  • RCC_HCLK_Div4: APB1 clock = HCLK/4
  • RCC_HCLK_Div8: APB1 clock = HCLK/8
  • RCC_HCLK_Div16: APB1 clock = HCLK/16
Return values:
None

Definition at line 634 of file stm32f10x_rcc.c.

References assert_param, CFGR_PPRE1_Reset_Mask, IS_RCC_PCLK, and RCC.

Referenced by SetSysClockTo24(), SetSysClockTo36(), SetSysClockTo48(), SetSysClockTo56(), SetSysClockTo72(), and SetSysClockToHSE().

void RCC_PCLK2Config ( uint32_t RCC_HCLK )

Configures the High Speed APB clock (PCLK2).

Parameters:
RCC_HCLK,: defines the APB2 clock divider. This clock is derived from the AHB clock (HCLK). This parameter can be one of the following values:

  • RCC_HCLK_Div1: APB2 clock = HCLK
  • RCC_HCLK_Div2: APB2 clock = HCLK/2
  • RCC_HCLK_Div4: APB2 clock = HCLK/4
  • RCC_HCLK_Div8: APB2 clock = HCLK/8
  • RCC_HCLK_Div16: APB2 clock = HCLK/16
Return values:
None

Definition at line 660 of file stm32f10x_rcc.c.

References assert_param, CFGR_PPRE2_Reset_Mask, IS_RCC_PCLK, and RCC.

Referenced by SetSysClockTo24(), SetSysClockTo36(), SetSysClockTo48(), SetSysClockTo56(), SetSysClockTo72(), and SetSysClockToHSE().

void RCC_PLLCmd ( FunctionalState NewState )

Enables or disables the PLL.

Note:
The PLL can not be disabled if it is used as system clock.
Parameters:
NewState,: new state of the PLL. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 401 of file stm32f10x_rcc.c.

References assert_param, CR_PLLON_BB, and IS_FUNCTIONAL_STATE.

Referenced by HDMI_CEC_CommandCallBack(), RCC_IRQHandler(), SetSysClockTo24(), SetSysClockTo36(), SetSysClockTo48(), SetSysClockTo56(), SetSysClockTo72(), and SYSCLKConfig_STOP().

void RCC_PLLConfig | ( | uint32_t | RCC_PLLSource,
 |  | uint32_t | RCC_PLLMul
 | ) |  |

Configures the PLL clock source and multiplication factor.

Note:
This function must be used only when the PLL is disabled.
Parameters:
RCC_PLLSource,: specifies the PLL entry clock source. For STM32_Connectivity_line_devices or STM32_Value_line_devices, this parameter can be one of the following values:

  • RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as PLL clock entry
  • RCC_PLLSource_PREDIV1: PREDIV1 clock selected as PLL clock entry For other_STM32_devices, this parameter can be one of the following values:
  • RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as PLL clock entry
  • RCC_PLLSource_HSE_Div1: HSE oscillator clock selected as PLL clock entry
  • RCC_PLLSource_HSE_Div2: HSE oscillator clock divided by 2 selected as PLL clock entry
RCC_PLLMul,: specifies the PLL multiplication factor. For STM32_Connectivity_line_devices, this parameter can be RCC_PLLMul_x where x:{[4,9], 6_5} For other_STM32_devices, this parameter can be RCC_PLLMul_x where x:[2,16]
Return values:
None

Definition at line 378 of file stm32f10x_rcc.c.

References assert_param, CFGR_PLL_Mask, IS_RCC_PLL_MUL, IS_RCC_PLL_SOURCE, and RCC.

Referenced by HDMI_CEC_CommandCallBack(), SetSysClockTo24(), SetSysClockTo36(), SetSysClockTo48(), SetSysClockTo56(), and SetSysClockTo72().

void RCC_RTCCLKCmd ( FunctionalState NewState )

Enables or disables the RTC clock.

Note:
This function must be used only after the RTC clock was selected using the RCC_RTCCLKConfig function.
Parameters:
NewState,: new state of the RTC clock. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 893 of file stm32f10x_rcc.c.

References assert_param, BDCR_RTCEN_BB, and IS_FUNCTIONAL_STATE.

Referenced by RTC_Configuration().

void RCC_RTCCLKConfig ( uint32_t RCC_RTCCLKSource )

Configures the RTC clock (RTCCLK).

Note:
Once the RTC clock is selected it can't be changed unless the Backup domain is reset.
Parameters:
RCC_RTCCLKSource,: specifies the RTC clock source. This parameter can be one of the following values:

  • RCC_RTCCLKSource_LSE: LSE selected as RTC clock
  • RCC_RTCCLKSource_LSI: LSI selected as RTC clock
  • RCC_RTCCLKSource_HSE_Div128: HSE clock divided by 128 selected as RTC clock
Return values:
None

Definition at line 879 of file stm32f10x_rcc.c.

References assert_param, IS_RCC_RTCCLK_SOURCE, and RCC.

Referenced by RTC_Configuration().

void RCC_SYSCLKConfig ( uint32_t RCC_SYSCLKSource )

Configures the system clock (SYSCLK).

Parameters:
RCC_SYSCLKSource,: specifies the clock source used as system clock. This parameter can be one of the following values:

  • RCC_SYSCLKSource_HSI: HSI selected as system clock
  • RCC_SYSCLKSource_HSE: HSE selected as system clock
  • RCC_SYSCLKSource_PLLCLK: PLL selected as system clock
Return values:
None

Definition at line 564 of file stm32f10x_rcc.c.

References assert_param, CFGR_SW_Mask, IS_RCC_SYSCLK_SOURCE, and RCC.

Referenced by HDMI_CEC_CommandCallBack(), RCC_IRQHandler(), SetSysClockTo24(), SetSysClockTo36(), SetSysClockTo48(), SetSysClockTo56(), SetSysClockTo72(), SetSysClockToHSE(), and SYSCLKConfig_STOP().

void RCC_USBCLKConfig ( uint32_t RCC_USBCLKSource )

Configures the USB clock (USBCLK).

Parameters:
RCC_USBCLKSource,: specifies the USB clock source. This clock is derived from the PLL output. This parameter can be one of the following values:

  • RCC_USBCLKSource_PLLCLK_1Div5: PLL clock divided by 1,5 selected as USB clock source
  • RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB clock source
Return values:
None

Definition at line 728 of file stm32f10x_rcc.c.

References assert_param, CFGR_USBPRE_BB, and IS_RCC_USBCLK_SOURCE.

ErrorStatus RCC_WaitForHSEStartUp ( void )

Waits for HSE start-up.

Parameters:
None
Return values:
An ErrorStatus enumuration value:

  • SUCCESS: HSE oscillator is stable and ready to use
  • ERROR: HSE oscillator not yet ready

Definition at line 304 of file stm32f10x_rcc.c.

References ERROR, HSE_STARTUP_TIMEOUT, RCC_FLAG_HSERDY, RCC_GetFlagStatus(), RESET, status, and SUCCESS.

Referenced by SetSysClockTo24(), SetSysClockTo36(), SetSysClockTo48(), SetSysClockTo56(), SetSysClockTo72(), SetSysClockToHSE(), and SYSCLKConfig_STOP().


STM32F10x Standard Peripherals Firmware Library: RTC_Exported_Types

RTC_Exported_Types

RTC


STM32F10x Standard Peripherals Firmware Library: RTC_interrupts_define

Defines

RTC_interrupts_define

RTC_Exported_Constants

Defines

#define | IS_RTC_GET_IT(IT)
#define | IS_RTC_IT(IT) ((((IT) & (uint16_t)0xFFF8) == 0x00) && ((IT) != 0x00))
#define | RTC_IT_ALR ((uint16_t)0x0002)
#define | RTC_IT_OW ((uint16_t)0x0004)
#define | RTC_IT_SEC ((uint16_t)0x0001)

Define Documentation

#define IS_RTC_GET_IT ( IT )
Value:
(((IT) == RTC_IT_OW) || ((IT) == RTC_IT_ALR) || \
                           ((IT) == RTC_IT_SEC))

Definition at line 62 of file stm32f10x_rtc.h.

Referenced by RTC_GetITStatus().

#define IS_RTC_IT ( IT ) ((((IT) & (uint16_t)0xFFF8) == 0x00) && ((IT) != 0x00))

Definition at line 61 of file stm32f10x_rtc.h.

Referenced by RTC_ClearITPendingBit(), and RTC_ITConfig().

#define RTC_IT_ALR ((uint16_t)0x0002)

Alarm interrupt

Definition at line 59 of file stm32f10x_rtc.h.

Referenced by RTCAlarm_IRQHandler().

#define RTC_IT_OW ((uint16_t)0x0004)

Overflow interrupt

Definition at line 58 of file stm32f10x_rtc.h.

#define RTC_IT_SEC ((uint16_t)0x0001)

Second interrupt

Definition at line 60 of file stm32f10x_rtc.h.

Referenced by main(), and RTC_IRQHandler().


STM32F10x Standard Peripherals Firmware Library: RTC_interrupts_flags

Defines

RTC_interrupts_flags

RTC_Exported_Constants

Defines

#define | IS_RTC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFFF0) == 0x00) && ((FLAG) != 0x00))
#define | IS_RTC_GET_FLAG(FLAG)
#define | IS_RTC_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFFFF)
#define | RTC_FLAG_ALR ((uint16_t)0x0002)
#define | RTC_FLAG_OW ((uint16_t)0x0004)
#define | RTC_FLAG_RSF ((uint16_t)0x0008)
#define | RTC_FLAG_RTOFF ((uint16_t)0x0020)
#define | RTC_FLAG_SEC ((uint16_t)0x0001)

Define Documentation

#define IS_RTC_CLEAR_FLAG ( FLAG ) ((((FLAG) & (uint16_t)0xFFF0) == 0x00) && ((FLAG) != 0x00))

Definition at line 77 of file stm32f10x_rtc.h.

Referenced by RTC_ClearFlag().

#define IS_RTC_GET_FLAG ( FLAG )
Value:
(((FLAG) == RTC_FLAG_RTOFF) || ((FLAG) == RTC_FLAG_RSF) || \
                               ((FLAG) == RTC_FLAG_OW) || ((FLAG) == RTC_FLAG_ALR) || \
                               ((FLAG) == RTC_FLAG_SEC))

Definition at line 78 of file stm32f10x_rtc.h.

Referenced by RTC_GetFlagStatus().

#define IS_RTC_PRESCALER ( PRESCALER ) ((PRESCALER) <= 0xFFFFF)

Definition at line 81 of file stm32f10x_rtc.h.

Referenced by RTC_SetPrescaler().

#define RTC_FLAG_ALR ((uint16_t)0x0002)

Alarm flag

Definition at line 75 of file stm32f10x_rtc.h.

#define RTC_FLAG_OW ((uint16_t)0x0004)

Overflow flag

Definition at line 74 of file stm32f10x_rtc.h.

#define RTC_FLAG_RSF ((uint16_t)0x0008)

Registers Synchronized flag

Definition at line 73 of file stm32f10x_rtc.h.

Referenced by RTC_WaitForSynchro().

#define RTC_FLAG_RTOFF ((uint16_t)0x0020)

RTC Operation OFF flag

Definition at line 72 of file stm32f10x_rtc.h.

Referenced by RTC_WaitForLastTask().

#define RTC_FLAG_SEC ((uint16_t)0x0001)

Second flag

Definition at line 76 of file stm32f10x_rtc.h.

Referenced by EXTI9_5_IRQHandler(), main(), and RTC_IRQHandler().


STM32F10x Standard Peripherals Firmware Library: RTC_Exported_Macros

RTC_Exported_Macros

RTC


STM32F10x Standard Peripherals Firmware Library: RTC_Exported_Functions

Functions

RTC_Exported_Functions

RTC

Functions

void | RTC_ClearFlag (uint16_t RTC_FLAG)
Clears the RTC's pending flags.
void | RTC_ClearITPendingBit (uint16_t RTC_IT)
Clears the RTC's interrupt pending bits.
void | RTC_EnterConfigMode (void)
Enters the RTC configuration mode.
void | RTC_ExitConfigMode (void)
Exits from the RTC configuration mode.
uint32_t | RTC_GetCounter (void)
Gets the RTC counter value.
uint32_t | RTC_GetDivider (void)
Gets the RTC divider value.
FlagStatus | RTC_GetFlagStatus (uint16_t RTC_FLAG)
Checks whether the specified RTC flag is set or not.
ITStatus | RTC_GetITStatus (uint16_t RTC_IT)
Checks whether the specified RTC interrupt has occurred or not.
void | RTC_ITConfig (uint16_t RTC_IT, FunctionalState NewState)
Enables or disables the specified RTC interrupts.
void | RTC_SetAlarm (uint32_t AlarmValue)
Sets the RTC alarm value.
void | RTC_SetCounter (uint32_t CounterValue)
Sets the RTC counter value.
void | RTC_SetPrescaler (uint32_t PrescalerValue)
Sets the RTC prescaler value.
void | RTC_WaitForLastTask (void)
Waits until last write operation on RTC registers has finished.
void | RTC_WaitForSynchro (void)
Waits until the RTC registers (RTC_CNT, RTC_ALR and RTC_PRL) are synchronized with RTC APB clock.

Function Documentation

void RTC_ClearFlag ( uint16_t RTC_FLAG )

Clears the RTC's pending flags.

Parameters:
RTC_FLAG,: specifies the flag to clear. This parameter can be any combination of the following values:

  • RTC_FLAG_RSF: Registers Synchronized flag. This flag is cleared only after an APB reset or an APB Clock stop.
  • RTC_FLAG_OW: Overflow flag
  • RTC_FLAG_ALR: Alarm flag
  • RTC_FLAG_SEC: Second flag
Return values:
None

Definition at line 273 of file stm32f10x_rtc.c.

References assert_param, IS_RTC_CLEAR_FLAG, and RTC.

Referenced by EXTI9_5_IRQHandler(), and main().

void RTC_ClearITPendingBit ( uint16_t RTC_IT )

Clears the RTC's interrupt pending bits.

Parameters:
RTC_IT,: specifies the interrupt pending bit to clear. This parameter can be any combination of the following values:

  • RTC_IT_OW: Overflow interrupt
  • RTC_IT_ALR: Alarm interrupt
  • RTC_IT_SEC: Second interrupt
Return values:
None

Definition at line 318 of file stm32f10x_rtc.c.

References assert_param, IS_RTC_IT, and RTC.

Referenced by RTC_IRQHandler(), and RTCAlarm_IRQHandler().

void RTC_EnterConfigMode ( void )

Enters the RTC configuration mode.

Parameters:
None
Return values:
None

Definition at line 111 of file stm32f10x_rtc.c.

References RTC, and RTC_CRL_CNF.

Referenced by RTC_SetAlarm(), RTC_SetCounter(), and RTC_SetPrescaler().

void RTC_ExitConfigMode ( void )

Exits from the RTC configuration mode.

Parameters:
None
Return values:
None

Definition at line 122 of file stm32f10x_rtc.c.

References RTC, and RTC_CRL_CNF.

Referenced by RTC_SetAlarm(), RTC_SetCounter(), and RTC_SetPrescaler().

uint32_t RTC_GetCounter ( void )

Gets the RTC counter value.

Parameters:
None
Return values:
RTC counter value.

Definition at line 133 of file stm32f10x_rtc.c.

References RTC.

Referenced by EXTI9_5_IRQHandler(), main(), Time_Display(), and Time_Show().

uint32_t RTC_GetDivider ( void )

Gets the RTC divider value.

Parameters:
None
Return values:
RTC Divider value.

Definition at line 193 of file stm32f10x_rtc.c.

References RTC.

FlagStatus RTC_GetFlagStatus ( uint16_t RTC_FLAG )

Checks whether the specified RTC flag is set or not.

Parameters:
RTC_FLAG,: specifies the flag to check. This parameter can be one the following values:

  • RTC_FLAG_RTOFF: RTC Operation OFF flag
  • RTC_FLAG_RSF: Registers Synchronized flag
  • RTC_FLAG_OW: Overflow flag
  • RTC_FLAG_ALR: Alarm flag
  • RTC_FLAG_SEC: Second flag
Return values:
The new state of RTC_FLAG (SET or RESET).

Definition at line 244 of file stm32f10x_rtc.c.

References assert_param, IS_RTC_GET_FLAG, RESET, RTC, and SET.

Referenced by EXTI9_5_IRQHandler(), and main().

ITStatus RTC_GetITStatus ( uint16_t RTC_IT )

Checks whether the specified RTC interrupt has occurred or not.

Parameters:
RTC_IT,: specifies the RTC interrupts sources to check. This parameter can be one of the following values:

  • RTC_IT_OW: Overflow interrupt
  • RTC_IT_ALR: Alarm interrupt
  • RTC_IT_SEC: Second interrupt
Return values:
The new state of the RTC_IT (SET or RESET).

Definition at line 291 of file stm32f10x_rtc.c.

References assert_param, IS_RTC_GET_IT, RESET, RTC, and SET.

Referenced by RTC_IRQHandler(), and RTCAlarm_IRQHandler().

void RTC_ITConfig | ( | uint16_t | RTC_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified RTC interrupts.

Parameters:
RTC_IT,: specifies the RTC interrupts sources to be enabled or disabled. This parameter can be any combination of the following values:

  • RTC_IT_OW: Overflow interrupt
  • RTC_IT_ALR: Alarm interrupt
  • RTC_IT_SEC: Second interrupt
NewState,: new state of the specified RTC interrupts. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 90 of file stm32f10x_rtc.c.

References assert_param, DISABLE, IS_FUNCTIONAL_STATE, IS_RTC_IT, and RTC.

Referenced by main().

void RTC_SetAlarm ( uint32_t AlarmValue )

Sets the RTC alarm value.

Parameters:
AlarmValue,: RTC alarm new value.
Return values:
None

Definition at line 178 of file stm32f10x_rtc.c.

References RTC, RTC_EnterConfigMode(), RTC_ExitConfigMode(), and RTC_LSB_MASK.

Referenced by EXTI9_5_IRQHandler(), and main().

void RTC_SetCounter ( uint32_t CounterValue )

Sets the RTC counter value.

Parameters:
CounterValue,: RTC counter new value.
Return values:
None

Definition at line 145 of file stm32f10x_rtc.c.

References RTC, RTC_EnterConfigMode(), RTC_ExitConfigMode(), and RTC_LSB_MASK.

Referenced by Time_Adjust(), and Time_Display().

void RTC_SetPrescaler ( uint32_t PrescalerValue )

Sets the RTC prescaler value.

Parameters:
PrescalerValue,: RTC prescaler new value.
Return values:
None

Definition at line 160 of file stm32f10x_rtc.c.

References assert_param, IS_RTC_PRESCALER, PRLH_MSB_MASK, RTC, RTC_EnterConfigMode(), RTC_ExitConfigMode(), and RTC_LSB_MASK.

Referenced by main(), and RTC_Configuration().

void RTC_WaitForLastTask ( void )

Waits until last write operation on RTC registers has finished.

Note:
This function must be called before any write to RTC registers.
Parameters:
None
Return values:
None

Definition at line 207 of file stm32f10x_rtc.c.

References RESET, RTC, and RTC_FLAG_RTOFF.

Referenced by EXTI9_5_IRQHandler(), main(), RTC_Configuration(), RTC_IRQHandler(), RTCAlarm_IRQHandler(), Time_Adjust(), and Time_Display().

void RTC_WaitForSynchro ( void )

Waits until the RTC registers (RTC_CNT, RTC_ALR and RTC_PRL) are synchronized with RTC APB clock.

Note:
This function must be called before any read operation after an APB reset or an APB clock stop.
Parameters:
None
Return values:
None

Definition at line 223 of file stm32f10x_rtc.c.

References RESET, RTC, and RTC_FLAG_RSF.

Referenced by main(), and RTC_Configuration().


STM32F10x Standard Peripherals Firmware Library: RTC_Private_TypesDefinitions

RTC_Private_TypesDefinitions

RTC


STM32F10x Standard Peripherals Firmware Library: RTC_Private_Defines

Defines

RTC_Private_Defines

RTC

Defines

#define | PRLH_MSB_MASK ((uint32_t)0x000F0000)
#define | RTC_LSB_MASK ((uint32_t)0x0000FFFF)

Define Documentation

#define PRLH_MSB_MASK ((uint32_t)0x000F0000)

RTC Prescaler MSB Mask

Definition at line 45 of file stm32f10x_rtc.c.

Referenced by RTC_SetPrescaler().

#define RTC_LSB_MASK ((uint32_t)0x0000FFFF)

RTC LSB Mask

Definition at line 44 of file stm32f10x_rtc.c.

Referenced by RTC_SetAlarm(), RTC_SetCounter(), and RTC_SetPrescaler().


STM32F10x Standard Peripherals Firmware Library: RTC_Private_Macros

RTC_Private_Macros

RTC


STM32F10x Standard Peripherals Firmware Library: RTC_Private_Variables

RTC_Private_Variables

RTC


STM32F10x Standard Peripherals Firmware Library: RTC_Private_FunctionPrototypes

RTC_Private_FunctionPrototypes

RTC


STM32F10x Standard Peripherals Firmware Library: RTC_Private_Functions

Functions

RTC_Private_Functions

RTC

Functions

void | RTC_ClearFlag (uint16_t RTC_FLAG)
Clears the RTC's pending flags.
void | RTC_ClearITPendingBit (uint16_t RTC_IT)
Clears the RTC's interrupt pending bits.
void | RTC_EnterConfigMode (void)
Enters the RTC configuration mode.
void | RTC_ExitConfigMode (void)
Exits from the RTC configuration mode.
uint32_t | RTC_GetCounter (void)
Gets the RTC counter value.
uint32_t | RTC_GetDivider (void)
Gets the RTC divider value.
FlagStatus | RTC_GetFlagStatus (uint16_t RTC_FLAG)
Checks whether the specified RTC flag is set or not.
ITStatus | RTC_GetITStatus (uint16_t RTC_IT)
Checks whether the specified RTC interrupt has occurred or not.
void | RTC_ITConfig (uint16_t RTC_IT, FunctionalState NewState)
Enables or disables the specified RTC interrupts.
void | RTC_SetAlarm (uint32_t AlarmValue)
Sets the RTC alarm value.
void | RTC_SetCounter (uint32_t CounterValue)
Sets the RTC counter value.
void | RTC_SetPrescaler (uint32_t PrescalerValue)
Sets the RTC prescaler value.
void | RTC_WaitForLastTask (void)
Waits until last write operation on RTC registers has finished.
void | RTC_WaitForSynchro (void)
Waits until the RTC registers (RTC_CNT, RTC_ALR and RTC_PRL) are synchronized with RTC APB clock.

Function Documentation

void RTC_ClearFlag ( uint16_t RTC_FLAG )

Clears the RTC's pending flags.

Parameters:
RTC_FLAG,: specifies the flag to clear. This parameter can be any combination of the following values:

  • RTC_FLAG_RSF: Registers Synchronized flag. This flag is cleared only after an APB reset or an APB Clock stop.
  • RTC_FLAG_OW: Overflow flag
  • RTC_FLAG_ALR: Alarm flag
  • RTC_FLAG_SEC: Second flag
Return values:
None

Definition at line 273 of file stm32f10x_rtc.c.

References assert_param, IS_RTC_CLEAR_FLAG, and RTC.

Referenced by EXTI9_5_IRQHandler(), and main().

void RTC_ClearITPendingBit ( uint16_t RTC_IT )

Clears the RTC's interrupt pending bits.

Parameters:
RTC_IT,: specifies the interrupt pending bit to clear. This parameter can be any combination of the following values:

  • RTC_IT_OW: Overflow interrupt
  • RTC_IT_ALR: Alarm interrupt
  • RTC_IT_SEC: Second interrupt
Return values:
None

Definition at line 318 of file stm32f10x_rtc.c.

References assert_param, IS_RTC_IT, and RTC.

Referenced by RTC_IRQHandler(), and RTCAlarm_IRQHandler().

void RTC_EnterConfigMode ( void )

Enters the RTC configuration mode.

Parameters:
None
Return values:
None

Definition at line 111 of file stm32f10x_rtc.c.

References RTC, and RTC_CRL_CNF.

Referenced by RTC_SetAlarm(), RTC_SetCounter(), and RTC_SetPrescaler().

void RTC_ExitConfigMode ( void )

Exits from the RTC configuration mode.

Parameters:
None
Return values:
None

Definition at line 122 of file stm32f10x_rtc.c.

References RTC, and RTC_CRL_CNF.

Referenced by RTC_SetAlarm(), RTC_SetCounter(), and RTC_SetPrescaler().

uint32_t RTC_GetCounter ( void )

Gets the RTC counter value.

Parameters:
None
Return values:
RTC counter value.

Definition at line 133 of file stm32f10x_rtc.c.

References RTC.

Referenced by EXTI9_5_IRQHandler(), main(), Time_Display(), and Time_Show().

uint32_t RTC_GetDivider ( void )

Gets the RTC divider value.

Parameters:
None
Return values:
RTC Divider value.

Definition at line 193 of file stm32f10x_rtc.c.

References RTC.

FlagStatus RTC_GetFlagStatus ( uint16_t RTC_FLAG )

Checks whether the specified RTC flag is set or not.

Parameters:
RTC_FLAG,: specifies the flag to check. This parameter can be one the following values:

  • RTC_FLAG_RTOFF: RTC Operation OFF flag
  • RTC_FLAG_RSF: Registers Synchronized flag
  • RTC_FLAG_OW: Overflow flag
  • RTC_FLAG_ALR: Alarm flag
  • RTC_FLAG_SEC: Second flag
Return values:
The new state of RTC_FLAG (SET or RESET).

Definition at line 244 of file stm32f10x_rtc.c.

References assert_param, IS_RTC_GET_FLAG, RESET, RTC, and SET.

Referenced by EXTI9_5_IRQHandler(), and main().

ITStatus RTC_GetITStatus ( uint16_t RTC_IT )

Checks whether the specified RTC interrupt has occurred or not.

Parameters:
RTC_IT,: specifies the RTC interrupts sources to check. This parameter can be one of the following values:

  • RTC_IT_OW: Overflow interrupt
  • RTC_IT_ALR: Alarm interrupt
  • RTC_IT_SEC: Second interrupt
Return values:
The new state of the RTC_IT (SET or RESET).

Definition at line 291 of file stm32f10x_rtc.c.

References assert_param, IS_RTC_GET_IT, RESET, RTC, and SET.

Referenced by RTC_IRQHandler(), and RTCAlarm_IRQHandler().

void RTC_ITConfig | ( | uint16_t | RTC_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified RTC interrupts.

Parameters:
RTC_IT,: specifies the RTC interrupts sources to be enabled or disabled. This parameter can be any combination of the following values:

  • RTC_IT_OW: Overflow interrupt
  • RTC_IT_ALR: Alarm interrupt
  • RTC_IT_SEC: Second interrupt
NewState,: new state of the specified RTC interrupts. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 90 of file stm32f10x_rtc.c.

References assert_param, DISABLE, IS_FUNCTIONAL_STATE, IS_RTC_IT, and RTC.

Referenced by main().

void RTC_SetAlarm ( uint32_t AlarmValue )

Sets the RTC alarm value.

Parameters:
AlarmValue,: RTC alarm new value.
Return values:
None

Definition at line 178 of file stm32f10x_rtc.c.

References RTC, RTC_EnterConfigMode(), RTC_ExitConfigMode(), and RTC_LSB_MASK.

Referenced by EXTI9_5_IRQHandler(), and main().

void RTC_SetCounter ( uint32_t CounterValue )

Sets the RTC counter value.

Parameters:
CounterValue,: RTC counter new value.
Return values:
None

Definition at line 145 of file stm32f10x_rtc.c.

References RTC, RTC_EnterConfigMode(), RTC_ExitConfigMode(), and RTC_LSB_MASK.

Referenced by Time_Adjust(), and Time_Display().

void RTC_SetPrescaler ( uint32_t PrescalerValue )

Sets the RTC prescaler value.

Parameters:
PrescalerValue,: RTC prescaler new value.
Return values:
None

Definition at line 160 of file stm32f10x_rtc.c.

References assert_param, IS_RTC_PRESCALER, PRLH_MSB_MASK, RTC, RTC_EnterConfigMode(), RTC_ExitConfigMode(), and RTC_LSB_MASK.

Referenced by main(), and RTC_Configuration().

void RTC_WaitForLastTask ( void )

Waits until last write operation on RTC registers has finished.

Note:
This function must be called before any write to RTC registers.
Parameters:
None
Return values:
None

Definition at line 207 of file stm32f10x_rtc.c.

References RESET, RTC, and RTC_FLAG_RTOFF.

Referenced by EXTI9_5_IRQHandler(), main(), RTC_Configuration(), RTC_IRQHandler(), RTCAlarm_IRQHandler(), Time_Adjust(), and Time_Display().

void RTC_WaitForSynchro ( void )

Waits until the RTC registers (RTC_CNT, RTC_ALR and RTC_PRL) are synchronized with RTC APB clock.

Note:
This function must be called before any read operation after an APB reset or an APB clock stop.
Parameters:
None
Return values:
None

Definition at line 223 of file stm32f10x_rtc.c.

References RESET, RTC, and RTC_FLAG_RSF.

Referenced by main(), and RTC_Configuration().


STM32F10x Standard Peripherals Firmware Library: SDIO_CmdInitTypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

SDIO_CmdInitTypeDef Struct Reference
SDIO_Exported_Types

#include <stm32f10x_sdio.h>

Data Fields

uint32_t | SDIO_Argument
uint32_t | SDIO_CmdIndex
uint32_t | SDIO_CPSM
uint32_t | SDIO_Response
uint32_t | SDIO_Wait

Detailed Description

Definition at line 70 of file stm32f10x_sdio.h.

Field Documentation

uint32_t SDIO_CmdInitTypeDef::SDIO_Argument

Specifies the SDIO command argument which is sent to a card as part of a command message. If a command contains an argument, it must be loaded into this register before writing the command to the command register

Definition at line 72 of file stm32f10x_sdio.h.

Referenced by FindSCR(), IsCardProgramming(), SD_Erase(), SD_InitializeCards(), SD_PowerON(), SD_ReadBlock(), SD_ReadMultiBlocks(), SD_SelectDeselect(), SD_SendSDStatus(), SD_WriteBlock(), SD_WriteMultiBlocks(), SDEnWideBus(), SDIO_CmdStructInit(), and SDIO_SendCommand().

uint32_t SDIO_CmdInitTypeDef::SDIO_CmdIndex

Specifies the SDIO command index. It must be lower than 0x40.

Definition at line 77 of file stm32f10x_sdio.h.

Referenced by FindSCR(), IsCardProgramming(), SD_Erase(), SD_InitializeCards(), SD_PowerON(), SD_ReadBlock(), SD_ReadMultiBlocks(), SD_SelectDeselect(), SD_SendSDStatus(), SD_WriteBlock(), SD_WriteMultiBlocks(), SDEnWideBus(), SDIO_CmdStructInit(), and SDIO_SendCommand().

uint32_t SDIO_CmdInitTypeDef::SDIO_CPSM

Specifies whether SDIO Command path state machine (CPSM) is enabled or disabled. This parameter can be a value of SDIO_CPSM_State

Definition at line 85 of file stm32f10x_sdio.h.

Referenced by FindSCR(), IsCardProgramming(), SD_Erase(), SD_InitializeCards(), SD_PowerON(), SD_ReadBlock(), SD_ReadMultiBlocks(), SD_SelectDeselect(), SD_SendSDStatus(), SD_WriteBlock(), SD_WriteMultiBlocks(), SDEnWideBus(), SDIO_CmdStructInit(), and SDIO_SendCommand().

uint32_t SDIO_CmdInitTypeDef::SDIO_Response

Specifies the SDIO response type. This parameter can be a value of SDIO_Response_Type

Definition at line 79 of file stm32f10x_sdio.h.

Referenced by FindSCR(), IsCardProgramming(), SD_Erase(), SD_InitializeCards(), SD_PowerON(), SD_ReadBlock(), SD_ReadMultiBlocks(), SD_SelectDeselect(), SD_SendSDStatus(), SD_WriteBlock(), SD_WriteMultiBlocks(), SDEnWideBus(), SDIO_CmdStructInit(), and SDIO_SendCommand().

uint32_t SDIO_CmdInitTypeDef::SDIO_Wait

Specifies whether SDIO wait-for-interrupt request is enabled or disabled. This parameter can be a value of SDIO_Wait_Interrupt_State

Definition at line 82 of file stm32f10x_sdio.h.

Referenced by FindSCR(), IsCardProgramming(), SD_Erase(), SD_InitializeCards(), SD_PowerON(), SD_ReadBlock(), SD_ReadMultiBlocks(), SD_SelectDeselect(), SD_SendSDStatus(), SD_WriteBlock(), SD_WriteMultiBlocks(), SDEnWideBus(), SDIO_CmdStructInit(), and SDIO_SendCommand().

The documentation for this struct was generated from the following file:
  • stm32f10x_sdio.h


STM32F10x Standard Peripherals Firmware Library: SDIO_DataInitTypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

SDIO_DataInitTypeDef Struct Reference
SDIO_Exported_Types

#include <stm32f10x_sdio.h>

Data Fields

uint32_t | SDIO_DataBlockSize
uint32_t | SDIO_DataLength
uint32_t | SDIO_DataTimeOut
uint32_t | SDIO_DPSM
uint32_t | SDIO_TransferDir
uint32_t | SDIO_TransferMode

Detailed Description

Definition at line 90 of file stm32f10x_sdio.h.

Field Documentation

uint32_t SDIO_DataInitTypeDef::SDIO_DataBlockSize

Specifies the data block size for block transfer. This parameter can be a value of SDIO_Data_Block_Size

Definition at line 96 of file stm32f10x_sdio.h.

Referenced by FindSCR(), SD_ReadBlock(), SD_ReadMultiBlocks(), SD_SendSDStatus(), SD_WriteBlock(), SD_WriteMultiBlocks(), SDIO_DataConfig(), and SDIO_DataStructInit().

uint32_t SDIO_DataInitTypeDef::SDIO_DataLength

Specifies the number of data bytes to be transferred.

Definition at line 94 of file stm32f10x_sdio.h.

Referenced by FindSCR(), SD_ReadBlock(), SD_ReadMultiBlocks(), SD_SendSDStatus(), SD_WriteBlock(), SD_WriteMultiBlocks(), SDIO_DataConfig(), and SDIO_DataStructInit().

uint32_t SDIO_DataInitTypeDef::SDIO_DataTimeOut

Specifies the data timeout period in card bus clock periods.

Definition at line 92 of file stm32f10x_sdio.h.

Referenced by FindSCR(), SD_ReadBlock(), SD_ReadMultiBlocks(), SD_SendSDStatus(), SD_WriteBlock(), SD_WriteMultiBlocks(), SDIO_DataConfig(), and SDIO_DataStructInit().

uint32_t SDIO_DataInitTypeDef::SDIO_DPSM

Specifies whether SDIO Data path state machine (DPSM) is enabled or disabled. This parameter can be a value of SDIO_DPSM_State

Definition at line 106 of file stm32f10x_sdio.h.

Referenced by FindSCR(), SD_ReadBlock(), SD_ReadMultiBlocks(), SD_SendSDStatus(), SD_WriteBlock(), SD_WriteMultiBlocks(), SDIO_DataConfig(), and SDIO_DataStructInit().

uint32_t SDIO_DataInitTypeDef::SDIO_TransferDir

Specifies the data transfer direction, whether the transfer is a read or write. This parameter can be a value of SDIO_Transfer_Direction

Definition at line 99 of file stm32f10x_sdio.h.

Referenced by FindSCR(), SD_ReadBlock(), SD_ReadMultiBlocks(), SD_SendSDStatus(), SD_WriteBlock(), SD_WriteMultiBlocks(), SDIO_DataConfig(), and SDIO_DataStructInit().

uint32_t SDIO_DataInitTypeDef::SDIO_TransferMode

Specifies whether data transfer is in stream or block mode. This parameter can be a value of SDIO_Transfer_Type

Definition at line 103 of file stm32f10x_sdio.h.

Referenced by FindSCR(), SD_ReadBlock(), SD_ReadMultiBlocks(), SD_SendSDStatus(), SD_WriteBlock(), SD_WriteMultiBlocks(), SDIO_DataConfig(), and SDIO_DataStructInit().

The documentation for this struct was generated from the following file:
  • stm32f10x_sdio.h


STM32F10x Standard Peripherals Firmware Library: SDIO_InitTypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

SDIO_InitTypeDef Struct Reference
SDIO_Exported_Types

#include <stm32f10x_sdio.h>

Data Fields

uint32_t | SDIO_BusWide
uint32_t | SDIO_ClockBypass
uint8_t | SDIO_ClockDiv
uint32_t | SDIO_ClockEdge
uint32_t | SDIO_ClockPowerSave
uint32_t | SDIO_HardwareFlowControl

Detailed Description

Definition at line 46 of file stm32f10x_sdio.h.

Field Documentation

uint32_t SDIO_InitTypeDef::SDIO_BusWide

Specifies the SDIO bus width. This parameter can be a value of SDIO_Bus_Wide

Definition at line 59 of file stm32f10x_sdio.h.

Referenced by SD_EnableWideBusOperation(), SD_Init(), SD_PowerON(), SDIO_Init(), and SDIO_StructInit().

uint32_t SDIO_InitTypeDef::SDIO_ClockBypass

Specifies whether the SDIO Clock divider bypass is enabled or disabled. This parameter can be a value of SDIO_Clock_Bypass

Definition at line 51 of file stm32f10x_sdio.h.

Referenced by SD_EnableWideBusOperation(), SD_Init(), SD_PowerON(), SDIO_Init(), and SDIO_StructInit().

uint8_t SDIO_InitTypeDef::SDIO_ClockDiv

Specifies the clock frequency of the SDIO controller. This parameter can be a value between 0x00 and 0xFF.

Definition at line 65 of file stm32f10x_sdio.h.

Referenced by SD_EnableWideBusOperation(), SD_Init(), SD_PowerON(), SDIO_Init(), and SDIO_StructInit().

uint32_t SDIO_InitTypeDef::SDIO_ClockEdge

Specifies the clock transition on which the bit capture is made. This parameter can be a value of SDIO_Clock_Edge

Definition at line 48 of file stm32f10x_sdio.h.

Referenced by SD_EnableWideBusOperation(), SD_Init(), SD_PowerON(), SDIO_Init(), and SDIO_StructInit().

uint32_t SDIO_InitTypeDef::SDIO_ClockPowerSave

Specifies whether SDIO Clock output is enabled or disabled when the bus is idle. This parameter can be a value of SDIO_Clock_Power_Save

Definition at line 55 of file stm32f10x_sdio.h.

Referenced by SD_EnableWideBusOperation(), SD_Init(), SD_PowerON(), SDIO_Init(), and SDIO_StructInit().

uint32_t SDIO_InitTypeDef::SDIO_HardwareFlowControl

Specifies whether the SDIO hardware flow control is enabled or disabled. This parameter can be a value of SDIO_Hardware_Flow_Control

Definition at line 62 of file stm32f10x_sdio.h.

Referenced by SD_EnableWideBusOperation(), SD_Init(), SD_PowerON(), SDIO_Init(), and SDIO_StructInit().

The documentation for this struct was generated from the following file:
  • stm32f10x_sdio.h


STM32F10x Standard Peripherals Firmware Library: SDIO_Clock_Edge

Defines

SDIO_Clock_Edge

SDIO_Exported_Constants

Defines

#define | IS_SDIO_CLOCK_EDGE(EDGE)
#define | SDIO_ClockEdge_Falling ((uint32_t)0x00002000)
#define | SDIO_ClockEdge_Rising ((uint32_t)0x00000000)

Define Documentation

#define IS_SDIO_CLOCK_EDGE ( EDGE )
Value:
(((EDGE) == SDIO_ClockEdge_Rising) || \
                                  ((EDGE) == SDIO_ClockEdge_Falling))

Definition at line 125 of file stm32f10x_sdio.h.

Referenced by SDIO_Init().

#define SDIO_ClockEdge_Falling ((uint32_t)0x00002000)

Definition at line 124 of file stm32f10x_sdio.h.

#define SDIO_ClockEdge_Rising ((uint32_t)0x00000000)

Definition at line 123 of file stm32f10x_sdio.h.

Referenced by SD_EnableWideBusOperation(), SD_Init(), SD_PowerON(), and SDIO_StructInit().


STM32F10x Standard Peripherals Firmware Library: SDIO_Clock_Bypass

Defines

SDIO_Clock_Bypass

SDIO_Exported_Constants

Defines

#define | IS_SDIO_CLOCK_BYPASS(BYPASS)
#define | SDIO_ClockBypass_Disable ((uint32_t)0x00000000)
#define | SDIO_ClockBypass_Enable ((uint32_t)0x00000400)

Define Documentation

#define IS_SDIO_CLOCK_BYPASS ( BYPASS )
Value:
(((BYPASS) == SDIO_ClockBypass_Disable) || \
                                     ((BYPASS) == SDIO_ClockBypass_Enable))

Definition at line 137 of file stm32f10x_sdio.h.

Referenced by SDIO_Init().

#define SDIO_ClockBypass_Disable ((uint32_t)0x00000000)

Definition at line 135 of file stm32f10x_sdio.h.

Referenced by SD_EnableWideBusOperation(), SD_Init(), SD_PowerON(), and SDIO_StructInit().

#define SDIO_ClockBypass_Enable ((uint32_t)0x00000400)

Definition at line 136 of file stm32f10x_sdio.h.


STM32F10x Standard Peripherals Firmware Library: SDIO_Clock_Power_Save

Defines

SDIO_Clock_Power_Save

SDIO_Exported_Constants

Defines

#define | IS_SDIO_CLOCK_POWER_SAVE(SAVE)
#define | SDIO_ClockPowerSave_Disable ((uint32_t)0x00000000)
#define | SDIO_ClockPowerSave_Enable ((uint32_t)0x00000200)

Define Documentation

#define IS_SDIO_CLOCK_POWER_SAVE ( SAVE )
Value:
(((SAVE) == SDIO_ClockPowerSave_Disable) || \
                                        ((SAVE) == SDIO_ClockPowerSave_Enable))

Definition at line 149 of file stm32f10x_sdio.h.

Referenced by SDIO_Init().

#define SDIO_ClockPowerSave_Disable ((uint32_t)0x00000000)

Definition at line 147 of file stm32f10x_sdio.h.

Referenced by SD_EnableWideBusOperation(), SD_Init(), SD_PowerON(), and SDIO_StructInit().

#define SDIO_ClockPowerSave_Enable ((uint32_t)0x00000200)

Definition at line 148 of file stm32f10x_sdio.h.


STM32F10x Standard Peripherals Firmware Library: SDIO_Bus_Wide

Defines

SDIO_Bus_Wide

SDIO_Exported_Constants

Defines

#define | IS_SDIO_BUS_WIDE(WIDE)
#define | SDIO_BusWide_1b ((uint32_t)0x00000000)
#define | SDIO_BusWide_4b ((uint32_t)0x00000800)
#define | SDIO_BusWide_8b ((uint32_t)0x00001000)

Define Documentation

#define IS_SDIO_BUS_WIDE ( WIDE )
Value:
(((WIDE) == SDIO_BusWide_1b) || ((WIDE) == SDIO_BusWide_4b) || \
                                ((WIDE) == SDIO_BusWide_8b))

Definition at line 162 of file stm32f10x_sdio.h.

Referenced by SDIO_Init().

#define SDIO_BusWide_1b ((uint32_t)0x00000000)

Definition at line 159 of file stm32f10x_sdio.h.

Referenced by SD_EnableWideBusOperation(), SD_Init(), SD_PowerON(), and SDIO_StructInit().

#define SDIO_BusWide_4b ((uint32_t)0x00000800)

Definition at line 160 of file stm32f10x_sdio.h.

Referenced by SD_EnableWideBusOperation(), and SD_Init().

#define SDIO_BusWide_8b ((uint32_t)0x00001000)

Definition at line 161 of file stm32f10x_sdio.h.

Referenced by SD_EnableWideBusOperation().


STM32F10x Standard Peripherals Firmware Library: SDIO_Hardware_Flow_Control

Defines

SDIO_Hardware_Flow_Control

SDIO_Exported_Constants

Defines

#define | IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL)
#define | SDIO_HardwareFlowControl_Disable ((uint32_t)0x00000000)
#define | SDIO_HardwareFlowControl_Enable ((uint32_t)0x00004000)

Define Documentation

#define IS_SDIO_HARDWARE_FLOW_CONTROL ( CONTROL )
Value:
(((CONTROL) == SDIO_HardwareFlowControl_Disable) || \
                                                ((CONTROL) == SDIO_HardwareFlowControl_Enable))

Definition at line 175 of file stm32f10x_sdio.h.

Referenced by SDIO_Init().

#define SDIO_HardwareFlowControl_Disable ((uint32_t)0x00000000)

Definition at line 173 of file stm32f10x_sdio.h.

Referenced by SD_EnableWideBusOperation(), SD_Init(), SD_PowerON(), and SDIO_StructInit().

#define SDIO_HardwareFlowControl_Enable ((uint32_t)0x00004000)

Definition at line 174 of file stm32f10x_sdio.h.


STM32F10x Standard Peripherals Firmware Library: SDIO_Power_State

Defines

SDIO_Power_State

SDIO_Exported_Constants

Defines

#define | IS_SDIO_POWER_STATE(STATE) (((STATE) == SDIO_PowerState_OFF) || ((STATE) == SDIO_PowerState_ON))
#define | SDIO_PowerState_OFF ((uint32_t)0x00000000)
#define | SDIO_PowerState_ON ((uint32_t)0x00000003)

Define Documentation

#define IS_SDIO_POWER_STATE ( STATE ) (((STATE) == SDIO_PowerState_OFF) || ((STATE) == SDIO_PowerState_ON))

Definition at line 187 of file stm32f10x_sdio.h.

Referenced by SDIO_SetPowerState().

#define SDIO_PowerState_OFF ((uint32_t)0x00000000)

Definition at line 185 of file stm32f10x_sdio.h.

Referenced by SD_InitializeCards(), SD_LowLevel_DeInit(), and SD_PowerOFF().

#define SDIO_PowerState_ON ((uint32_t)0x00000003)

Definition at line 186 of file stm32f10x_sdio.h.

Referenced by SD_PowerON().


STM32F10x Standard Peripherals Firmware Library: SDIO_Interrupt_sources

Defines

SDIO_Interrupt_sources

SDIO_Exported_Constants

Defines

#define | IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00))
#define | SDIO_IT_CCRCFAIL ((uint32_t)0x00000001)
#define | SDIO_IT_CEATAEND ((uint32_t)0x00800000)
#define | SDIO_IT_CMDACT ((uint32_t)0x00000800)
#define | SDIO_IT_CMDREND ((uint32_t)0x00000040)
#define | SDIO_IT_CMDSENT ((uint32_t)0x00000080)
#define | SDIO_IT_CTIMEOUT ((uint32_t)0x00000004)
#define | SDIO_IT_DATAEND ((uint32_t)0x00000100)
#define | SDIO_IT_DBCKEND ((uint32_t)0x00000400)
#define | SDIO_IT_DCRCFAIL ((uint32_t)0x00000002)
#define | SDIO_IT_DTIMEOUT ((uint32_t)0x00000008)
#define | SDIO_IT_RXACT ((uint32_t)0x00002000)
#define | SDIO_IT_RXDAVL ((uint32_t)0x00200000)
#define | SDIO_IT_RXFIFOE ((uint32_t)0x00080000)
#define | SDIO_IT_RXFIFOF ((uint32_t)0x00020000)
#define | SDIO_IT_RXFIFOHF ((uint32_t)0x00008000)
#define | SDIO_IT_RXOVERR ((uint32_t)0x00000020)
#define | SDIO_IT_SDIOIT ((uint32_t)0x00400000)
#define | SDIO_IT_STBITERR ((uint32_t)0x00000200)
#define | SDIO_IT_TXACT ((uint32_t)0x00001000)
#define | SDIO_IT_TXDAVL ((uint32_t)0x00100000)
#define | SDIO_IT_TXFIFOE ((uint32_t)0x00040000)
#define | SDIO_IT_TXFIFOF ((uint32_t)0x00010000)
#define | SDIO_IT_TXFIFOHE ((uint32_t)0x00004000)
#define | SDIO_IT_TXUNDERR ((uint32_t)0x00000010)

Define Documentation

#define IS_SDIO_IT ( IT ) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00))

Definition at line 221 of file stm32f10x_sdio.h.

Referenced by SDIO_ITConfig().

#define SDIO_IT_CCRCFAIL ((uint32_t)0x00000001)

Definition at line 197 of file stm32f10x_sdio.h.

#define SDIO_IT_CEATAEND ((uint32_t)0x00800000)

Definition at line 220 of file stm32f10x_sdio.h.

#define SDIO_IT_CMDACT ((uint32_t)0x00000800)

Definition at line 208 of file stm32f10x_sdio.h.

#define SDIO_IT_CMDREND ((uint32_t)0x00000040)

Definition at line 203 of file stm32f10x_sdio.h.

#define SDIO_IT_CMDSENT ((uint32_t)0x00000080)

Definition at line 204 of file stm32f10x_sdio.h.

#define SDIO_IT_CTIMEOUT ((uint32_t)0x00000004)

Definition at line 199 of file stm32f10x_sdio.h.

#define SDIO_IT_DATAEND ((uint32_t)0x00000100)

Definition at line 205 of file stm32f10x_sdio.h.

Referenced by SD_ProcessIRQSrc(), SD_ReadBlock(), SD_ReadMultiBlocks(), SD_WriteBlock(), and SD_WriteMultiBlocks().

#define SDIO_IT_DBCKEND ((uint32_t)0x00000400)

Definition at line 207 of file stm32f10x_sdio.h.

#define SDIO_IT_DCRCFAIL ((uint32_t)0x00000002)

Definition at line 198 of file stm32f10x_sdio.h.

#define SDIO_IT_DTIMEOUT ((uint32_t)0x00000008)

Definition at line 200 of file stm32f10x_sdio.h.

#define SDIO_IT_RXACT ((uint32_t)0x00002000)

Definition at line 210 of file stm32f10x_sdio.h.

#define SDIO_IT_RXDAVL ((uint32_t)0x00200000)

Definition at line 218 of file stm32f10x_sdio.h.

#define SDIO_IT_RXFIFOE ((uint32_t)0x00080000)

Definition at line 216 of file stm32f10x_sdio.h.

#define SDIO_IT_RXFIFOF ((uint32_t)0x00020000)

Definition at line 214 of file stm32f10x_sdio.h.

#define SDIO_IT_RXFIFOHF ((uint32_t)0x00008000)

Definition at line 212 of file stm32f10x_sdio.h.

#define SDIO_IT_RXOVERR ((uint32_t)0x00000020)

Definition at line 202 of file stm32f10x_sdio.h.

#define SDIO_IT_SDIOIT ((uint32_t)0x00400000)

Definition at line 219 of file stm32f10x_sdio.h.

#define SDIO_IT_STBITERR ((uint32_t)0x00000200)

Definition at line 206 of file stm32f10x_sdio.h.

#define SDIO_IT_TXACT ((uint32_t)0x00001000)

Definition at line 209 of file stm32f10x_sdio.h.

#define SDIO_IT_TXDAVL ((uint32_t)0x00100000)

Definition at line 217 of file stm32f10x_sdio.h.

#define SDIO_IT_TXFIFOE ((uint32_t)0x00040000)

Definition at line 215 of file stm32f10x_sdio.h.

#define SDIO_IT_TXFIFOF ((uint32_t)0x00010000)

Definition at line 213 of file stm32f10x_sdio.h.

#define SDIO_IT_TXFIFOHE ((uint32_t)0x00004000)

Definition at line 211 of file stm32f10x_sdio.h.

#define SDIO_IT_TXUNDERR ((uint32_t)0x00000010)

Definition at line 201 of file stm32f10x_sdio.h.


STM32F10x Standard Peripherals Firmware Library: SDIO_Command_Index

Defines

SDIO_Command_Index

SDIO_Exported_Constants

Defines

#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40)

Define Documentation

#define IS_SDIO_CMD_INDEX ( INDEX ) ((INDEX) < 0x40)

Definition at line 230 of file stm32f10x_sdio.h.

Referenced by SDIO_SendCommand().


STM32F10x Standard Peripherals Firmware Library: SDIO_Response_Type

Defines

SDIO_Response_Type

SDIO_Exported_Constants

Defines

#define | IS_SDIO_RESPONSE(RESPONSE)
#define | SDIO_Response_Long ((uint32_t)0x000000C0)
#define | SDIO_Response_No ((uint32_t)0x00000000)
#define | SDIO_Response_Short ((uint32_t)0x00000040)

Define Documentation

#define IS_SDIO_RESPONSE ( RESPONSE )
Value:
(((RESPONSE) == SDIO_Response_No) || \
                                    ((RESPONSE) == SDIO_Response_Short) || \
                                    ((RESPONSE) == SDIO_Response_Long))

Definition at line 242 of file stm32f10x_sdio.h.

Referenced by SDIO_SendCommand().

#define SDIO_Response_Long ((uint32_t)0x000000C0)

Definition at line 241 of file stm32f10x_sdio.h.

Referenced by SD_InitializeCards().

#define SDIO_Response_No ((uint32_t)0x00000000)

Definition at line 239 of file stm32f10x_sdio.h.

Referenced by SD_PowerON(), and SDIO_CmdStructInit().

#define SDIO_Response_Short ((uint32_t)0x00000040)

Definition at line 240 of file stm32f10x_sdio.h.

Referenced by FindSCR(), IsCardProgramming(), SD_Erase(), SD_InitializeCards(), SD_PowerON(), SD_ReadBlock(), SD_ReadMultiBlocks(), SD_SelectDeselect(), SD_SendSDStatus(), SD_WriteBlock(), SD_WriteMultiBlocks(), and SDEnWideBus().


STM32F10x Standard Peripherals Firmware Library: SDIO_Wait_Interrupt_State

Defines

SDIO_Wait_Interrupt_State

SDIO_Exported_Constants

Defines

#define | IS_SDIO_WAIT(WAIT)
#define | SDIO_Wait_IT ((uint32_t)0x00000100)
#define | SDIO_Wait_No ((uint32_t)0x00000000)
#define | SDIO_Wait_Pend ((uint32_t)0x00000200)

Define Documentation

#define IS_SDIO_WAIT ( WAIT )
Value:
(((WAIT) == SDIO_Wait_No) || ((WAIT) == SDIO_Wait_IT) || \
                            ((WAIT) == SDIO_Wait_Pend))

Definition at line 256 of file stm32f10x_sdio.h.

Referenced by SDIO_SendCommand().

#define SDIO_Wait_IT ((uint32_t)0x00000100)

SDIO Wait Interrupt Request

Definition at line 254 of file stm32f10x_sdio.h.

#define SDIO_Wait_No ((uint32_t)0x00000000)

SDIO No Wait, TimeOut is enabled

Definition at line 253 of file stm32f10x_sdio.h.

Referenced by FindSCR(), IsCardProgramming(), SD_Erase(), SD_InitializeCards(), SD_PowerON(), SD_ReadBlock(), SD_ReadMultiBlocks(), SD_SelectDeselect(), SD_SendSDStatus(), SD_WriteBlock(), SD_WriteMultiBlocks(), SDEnWideBus(), and SDIO_CmdStructInit().

#define SDIO_Wait_Pend ((uint32_t)0x00000200)

SDIO Wait End of transfer

Definition at line 255 of file stm32f10x_sdio.h.


STM32F10x Standard Peripherals Firmware Library: SDIO_CPSM_State

Defines

SDIO_CPSM_State

SDIO_Exported_Constants

Defines

#define | IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_Enable) || ((CPSM) == SDIO_CPSM_Disable))
#define | SDIO_CPSM_Disable ((uint32_t)0x00000000)
#define | SDIO_CPSM_Enable ((uint32_t)0x00000400)

Define Documentation

#define IS_SDIO_CPSM ( CPSM ) (((CPSM) == SDIO_CPSM_Enable) || ((CPSM) == SDIO_CPSM_Disable))

Definition at line 268 of file stm32f10x_sdio.h.

Referenced by SDIO_SendCommand().

#define SDIO_CPSM_Disable ((uint32_t)0x00000000)

Definition at line 266 of file stm32f10x_sdio.h.

Referenced by SDIO_CmdStructInit().

#define SDIO_CPSM_Enable ((uint32_t)0x00000400)

Definition at line 267 of file stm32f10x_sdio.h.

Referenced by FindSCR(), IsCardProgramming(), SD_Erase(), SD_InitializeCards(), SD_PowerON(), SD_ReadBlock(), SD_ReadMultiBlocks(), SD_SelectDeselect(), SD_SendSDStatus(), SD_WriteBlock(), SD_WriteMultiBlocks(), and SDEnWideBus().


STM32F10x Standard Peripherals Firmware Library: SDIO_Response_Registers

Defines

SDIO_Response_Registers

SDIO_Exported_Constants

Defines

#define | IS_SDIO_RESP(RESP)
#define | SDIO_RESP1 ((uint32_t)0x00000000)
#define | SDIO_RESP2 ((uint32_t)0x00000004)
#define | SDIO_RESP3 ((uint32_t)0x00000008)
#define | SDIO_RESP4 ((uint32_t)0x0000000C)

Define Documentation

#define IS_SDIO_RESP ( RESP )
Value:
(((RESP) == SDIO_RESP1) || ((RESP) == SDIO_RESP2) || \
                            ((RESP) == SDIO_RESP3) || ((RESP) == SDIO_RESP4))

Definition at line 281 of file stm32f10x_sdio.h.

Referenced by SDIO_GetResponse().

#define SDIO_RESP1 ((uint32_t)0x00000000)

Definition at line 277 of file stm32f10x_sdio.h.

Referenced by CmdResp6Error(), IsCardProgramming(), SD_Erase(), SD_InitializeCards(), SD_PowerON(), SD_SendSDStatus(), and SDEnWideBus().

#define SDIO_RESP2 ((uint32_t)0x00000004)

Definition at line 278 of file stm32f10x_sdio.h.

Referenced by SD_InitializeCards().

#define SDIO_RESP3 ((uint32_t)0x00000008)

Definition at line 279 of file stm32f10x_sdio.h.

Referenced by SD_InitializeCards().

#define SDIO_RESP4 ((uint32_t)0x0000000C)

Definition at line 280 of file stm32f10x_sdio.h.

Referenced by SD_InitializeCards().


STM32F10x Standard Peripherals Firmware Library: SDIO_Data_Length

Defines

SDIO_Data_Length

SDIO_Exported_Constants

Defines

#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)

Define Documentation

#define IS_SDIO_DATA_LENGTH ( LENGTH ) ((LENGTH) <= 0x01FFFFFF)

Definition at line 291 of file stm32f10x_sdio.h.

Referenced by SDIO_DataConfig().


STM32F10x Standard Peripherals Firmware Library: SDIO_Data_Block_Size

Defines

SDIO_Data_Block_Size

SDIO_Exported_Constants

Defines

#define | IS_SDIO_BLOCK_SIZE(SIZE)
#define | SDIO_DataBlockSize_1024b ((uint32_t)0x000000A0)
#define | SDIO_DataBlockSize_128b ((uint32_t)0x00000070)
#define | SDIO_DataBlockSize_16384b ((uint32_t)0x000000E0)
#define | SDIO_DataBlockSize_16b ((uint32_t)0x00000040)
#define | SDIO_DataBlockSize_1b ((uint32_t)0x00000000)
#define | SDIO_DataBlockSize_2048b ((uint32_t)0x000000B0)
#define | SDIO_DataBlockSize_256b ((uint32_t)0x00000080)
#define | SDIO_DataBlockSize_2b ((uint32_t)0x00000010)
#define | SDIO_DataBlockSize_32b ((uint32_t)0x00000050)
#define | SDIO_DataBlockSize_4096b ((uint32_t)0x000000C0)
#define | SDIO_DataBlockSize_4b ((uint32_t)0x00000020)
#define | SDIO_DataBlockSize_512b ((uint32_t)0x00000090)
#define | SDIO_DataBlockSize_64b ((uint32_t)0x00000060)
#define | SDIO_DataBlockSize_8192b ((uint32_t)0x000000D0)
#define | SDIO_DataBlockSize_8b ((uint32_t)0x00000030)

Define Documentation

#define IS_SDIO_BLOCK_SIZE ( SIZE )
Value:
(((SIZE) == SDIO_DataBlockSize_1b) || \
                                  ((SIZE) == SDIO_DataBlockSize_2b) || \
                                  ((SIZE) == SDIO_DataBlockSize_4b) || \
                                  ((SIZE) == SDIO_DataBlockSize_8b) || \
                                  ((SIZE) == SDIO_DataBlockSize_16b) || \
                                  ((SIZE) == SDIO_DataBlockSize_32b) || \
                                  ((SIZE) == SDIO_DataBlockSize_64b) || \
                                  ((SIZE) == SDIO_DataBlockSize_128b) || \
                                  ((SIZE) == SDIO_DataBlockSize_256b) || \
                                  ((SIZE) == SDIO_DataBlockSize_512b) || \
                                  ((SIZE) == SDIO_DataBlockSize_1024b) || \
                                  ((SIZE) == SDIO_DataBlockSize_2048b) || \
                                  ((SIZE) == SDIO_DataBlockSize_4096b) || \
                                  ((SIZE) == SDIO_DataBlockSize_8192b) || \
                                  ((SIZE) == SDIO_DataBlockSize_16384b))

Definition at line 315 of file stm32f10x_sdio.h.

Referenced by SDIO_DataConfig().

#define SDIO_DataBlockSize_1024b ((uint32_t)0x000000A0)

Definition at line 310 of file stm32f10x_sdio.h.

#define SDIO_DataBlockSize_128b ((uint32_t)0x00000070)

Definition at line 307 of file stm32f10x_sdio.h.

#define SDIO_DataBlockSize_16384b ((uint32_t)0x000000E0)

Definition at line 314 of file stm32f10x_sdio.h.

#define SDIO_DataBlockSize_16b ((uint32_t)0x00000040)

Definition at line 304 of file stm32f10x_sdio.h.

#define SDIO_DataBlockSize_1b ((uint32_t)0x00000000)

Definition at line 300 of file stm32f10x_sdio.h.

Referenced by SDIO_DataStructInit().

#define SDIO_DataBlockSize_2048b ((uint32_t)0x000000B0)

Definition at line 311 of file stm32f10x_sdio.h.

#define SDIO_DataBlockSize_256b ((uint32_t)0x00000080)

Definition at line 308 of file stm32f10x_sdio.h.

#define SDIO_DataBlockSize_2b ((uint32_t)0x00000010)

Definition at line 301 of file stm32f10x_sdio.h.

#define SDIO_DataBlockSize_32b ((uint32_t)0x00000050)

Definition at line 305 of file stm32f10x_sdio.h.

#define SDIO_DataBlockSize_4096b ((uint32_t)0x000000C0)

Definition at line 312 of file stm32f10x_sdio.h.

#define SDIO_DataBlockSize_4b ((uint32_t)0x00000020)

Definition at line 302 of file stm32f10x_sdio.h.

#define SDIO_DataBlockSize_512b ((uint32_t)0x00000090)

Definition at line 309 of file stm32f10x_sdio.h.

#define SDIO_DataBlockSize_64b ((uint32_t)0x00000060)

Definition at line 306 of file stm32f10x_sdio.h.

Referenced by SD_SendSDStatus().

#define SDIO_DataBlockSize_8192b ((uint32_t)0x000000D0)

Definition at line 313 of file stm32f10x_sdio.h.

#define SDIO_DataBlockSize_8b ((uint32_t)0x00000030)

Definition at line 303 of file stm32f10x_sdio.h.

Referenced by FindSCR().


STM32F10x Standard Peripherals Firmware Library: SDIO_Transfer_Direction

Defines

SDIO_Transfer_Direction

SDIO_Exported_Constants

Defines

#define | IS_SDIO_TRANSFER_DIR(DIR)
#define | SDIO_TransferDir_ToCard ((uint32_t)0x00000000)
#define | SDIO_TransferDir_ToSDIO ((uint32_t)0x00000002)

Define Documentation

#define IS_SDIO_TRANSFER_DIR ( DIR )
Value:
(((DIR) == SDIO_TransferDir_ToCard) || \
                                   ((DIR) == SDIO_TransferDir_ToSDIO))

Definition at line 340 of file stm32f10x_sdio.h.

Referenced by SDIO_DataConfig().

#define SDIO_TransferDir_ToCard ((uint32_t)0x00000000)

Definition at line 338 of file stm32f10x_sdio.h.

Referenced by SD_WriteBlock(), SD_WriteMultiBlocks(), and SDIO_DataStructInit().

#define SDIO_TransferDir_ToSDIO ((uint32_t)0x00000002)

Definition at line 339 of file stm32f10x_sdio.h.

Referenced by FindSCR(), SD_ReadBlock(), SD_ReadMultiBlocks(), and SD_SendSDStatus().


STM32F10x Standard Peripherals Firmware Library: SDIO_Transfer_Type

Defines

SDIO_Transfer_Type

SDIO_Exported_Constants

Defines

#define | IS_SDIO_TRANSFER_MODE(MODE)
#define | SDIO_TransferMode_Block ((uint32_t)0x00000000)
#define | SDIO_TransferMode_Stream ((uint32_t)0x00000004)

Define Documentation

#define IS_SDIO_TRANSFER_MODE ( MODE )
Value:
(((MODE) == SDIO_TransferMode_Stream) || \
                                     ((MODE) == SDIO_TransferMode_Block))

Definition at line 352 of file stm32f10x_sdio.h.

Referenced by SDIO_DataConfig().

#define SDIO_TransferMode_Block ((uint32_t)0x00000000)

Definition at line 350 of file stm32f10x_sdio.h.

Referenced by FindSCR(), SD_ReadBlock(), SD_ReadMultiBlocks(), SD_SendSDStatus(), SD_WriteBlock(), SD_WriteMultiBlocks(), and SDIO_DataStructInit().

#define SDIO_TransferMode_Stream ((uint32_t)0x00000004)

Definition at line 351 of file stm32f10x_sdio.h.


STM32F10x Standard Peripherals Firmware Library: SDIO_DPSM_State

Defines

SDIO_DPSM_State

SDIO_Exported_Constants

Defines

#define | IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_Enable) || ((DPSM) == SDIO_DPSM_Disable))
#define | SDIO_DPSM_Disable ((uint32_t)0x00000000)
#define | SDIO_DPSM_Enable ((uint32_t)0x00000001)

Define Documentation

#define IS_SDIO_DPSM ( DPSM ) (((DPSM) == SDIO_DPSM_Enable) || ((DPSM) == SDIO_DPSM_Disable))

Definition at line 364 of file stm32f10x_sdio.h.

Referenced by SDIO_DataConfig().

#define SDIO_DPSM_Disable ((uint32_t)0x00000000)

Definition at line 362 of file stm32f10x_sdio.h.

Referenced by SDIO_DataStructInit().

#define SDIO_DPSM_Enable ((uint32_t)0x00000001)

Definition at line 363 of file stm32f10x_sdio.h.

Referenced by FindSCR(), SD_ReadBlock(), SD_ReadMultiBlocks(), SD_SendSDStatus(), SD_WriteBlock(), and SD_WriteMultiBlocks().


STM32F10x Standard Peripherals Firmware Library: SDIO_Flags

Defines

SDIO_Flags

SDIO_Exported_Constants

Defines

#define | IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00))
#define | IS_SDIO_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00))
#define | IS_SDIO_FLAG(FLAG)
#define | IS_SDIO_GET_IT(IT)
#define | SDIO_FLAG_CCRCFAIL ((uint32_t)0x00000001)
#define | SDIO_FLAG_CEATAEND ((uint32_t)0x00800000)
#define | SDIO_FLAG_CMDACT ((uint32_t)0x00000800)
#define | SDIO_FLAG_CMDREND ((uint32_t)0x00000040)
#define | SDIO_FLAG_CMDSENT ((uint32_t)0x00000080)
#define | SDIO_FLAG_CTIMEOUT ((uint32_t)0x00000004)
#define | SDIO_FLAG_DATAEND ((uint32_t)0x00000100)
#define | SDIO_FLAG_DBCKEND ((uint32_t)0x00000400)
#define | SDIO_FLAG_DCRCFAIL ((uint32_t)0x00000002)
#define | SDIO_FLAG_DTIMEOUT ((uint32_t)0x00000008)
#define | SDIO_FLAG_RXACT ((uint32_t)0x00002000)
#define | SDIO_FLAG_RXDAVL ((uint32_t)0x00200000)
#define | SDIO_FLAG_RXFIFOE ((uint32_t)0x00080000)
#define | SDIO_FLAG_RXFIFOF ((uint32_t)0x00020000)
#define | SDIO_FLAG_RXFIFOHF ((uint32_t)0x00008000)
#define | SDIO_FLAG_RXOVERR ((uint32_t)0x00000020)
#define | SDIO_FLAG_SDIOIT ((uint32_t)0x00400000)
#define | SDIO_FLAG_STBITERR ((uint32_t)0x00000200)
#define | SDIO_FLAG_TXACT ((uint32_t)0x00001000)
#define | SDIO_FLAG_TXDAVL ((uint32_t)0x00100000)
#define | SDIO_FLAG_TXFIFOE ((uint32_t)0x00040000)
#define | SDIO_FLAG_TXFIFOF ((uint32_t)0x00010000)
#define | SDIO_FLAG_TXFIFOHE ((uint32_t)0x00004000)
#define | SDIO_FLAG_TXUNDERR ((uint32_t)0x00000010)

Define Documentation

#define IS_SDIO_CLEAR_FLAG ( FLAG ) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00))

Definition at line 422 of file stm32f10x_sdio.h.

Referenced by SDIO_ClearFlag().

#define IS_SDIO_CLEAR_IT ( IT ) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00))

Definition at line 449 of file stm32f10x_sdio.h.

Referenced by SDIO_ClearITPendingBit().

#define IS_SDIO_FLAG ( FLAG )
Value:
(((FLAG)  == SDIO_FLAG_CCRCFAIL) || \
                            ((FLAG)  == SDIO_FLAG_DCRCFAIL) || \
                            ((FLAG)  == SDIO_FLAG_CTIMEOUT) || \
                            ((FLAG)  == SDIO_FLAG_DTIMEOUT) || \
                            ((FLAG)  == SDIO_FLAG_TXUNDERR) || \
                            ((FLAG)  == SDIO_FLAG_RXOVERR) || \
                            ((FLAG)  == SDIO_FLAG_CMDREND) || \
                            ((FLAG)  == SDIO_FLAG_CMDSENT) || \
                            ((FLAG)  == SDIO_FLAG_DATAEND) || \
                            ((FLAG)  == SDIO_FLAG_STBITERR) || \
                            ((FLAG)  == SDIO_FLAG_DBCKEND) || \
                            ((FLAG)  == SDIO_FLAG_CMDACT) || \
                            ((FLAG)  == SDIO_FLAG_TXACT) || \
                            ((FLAG)  == SDIO_FLAG_RXACT) || \
                            ((FLAG)  == SDIO_FLAG_TXFIFOHE) || \
                            ((FLAG)  == SDIO_FLAG_RXFIFOHF) || \
                            ((FLAG)  == SDIO_FLAG_TXFIFOF) || \
                            ((FLAG)  == SDIO_FLAG_RXFIFOF) || \
                            ((FLAG)  == SDIO_FLAG_TXFIFOE) || \
                            ((FLAG)  == SDIO_FLAG_RXFIFOE) || \
                            ((FLAG)  == SDIO_FLAG_TXDAVL) || \
                            ((FLAG)  == SDIO_FLAG_RXDAVL) || \
                            ((FLAG)  == SDIO_FLAG_SDIOIT) || \
                            ((FLAG)  == SDIO_FLAG_CEATAEND))

Definition at line 397 of file stm32f10x_sdio.h.

Referenced by SDIO_GetFlagStatus().

#define IS_SDIO_GET_IT ( IT )
Value:
(((IT)  == SDIO_IT_CCRCFAIL) || \
                            ((IT)  == SDIO_IT_DCRCFAIL) || \
                            ((IT)  == SDIO_IT_CTIMEOUT) || \
                            ((IT)  == SDIO_IT_DTIMEOUT) || \
                            ((IT)  == SDIO_IT_TXUNDERR) || \
                            ((IT)  == SDIO_IT_RXOVERR) || \
                            ((IT)  == SDIO_IT_CMDREND) || \
                            ((IT)  == SDIO_IT_CMDSENT) || \
                            ((IT)  == SDIO_IT_DATAEND) || \
                            ((IT)  == SDIO_IT_STBITERR) || \
                            ((IT)  == SDIO_IT_DBCKEND) || \
                            ((IT)  == SDIO_IT_CMDACT) || \
                            ((IT)  == SDIO_IT_TXACT) || \
                            ((IT)  == SDIO_IT_RXACT) || \
                            ((IT)  == SDIO_IT_TXFIFOHE) || \
                            ((IT)  == SDIO_IT_RXFIFOHF) || \
                            ((IT)  == SDIO_IT_TXFIFOF) || \
                            ((IT)  == SDIO_IT_RXFIFOF) || \
                            ((IT)  == SDIO_IT_TXFIFOE) || \
                            ((IT)  == SDIO_IT_RXFIFOE) || \
                            ((IT)  == SDIO_IT_TXDAVL) || \
                            ((IT)  == SDIO_IT_RXDAVL) || \
                            ((IT)  == SDIO_IT_SDIOIT) || \
                            ((IT)  == SDIO_IT_CEATAEND))

Definition at line 424 of file stm32f10x_sdio.h.

Referenced by SDIO_GetITStatus().

#define SDIO_FLAG_CCRCFAIL ((uint32_t)0x00000001)

Definition at line 373 of file stm32f10x_sdio.h.

Referenced by CmdResp1Error(), CmdResp2Error(), CmdResp3Error(), CmdResp6Error(), CmdResp7Error(), and IsCardProgramming().

#define SDIO_FLAG_CEATAEND ((uint32_t)0x00800000)

Definition at line 396 of file stm32f10x_sdio.h.

#define SDIO_FLAG_CMDACT ((uint32_t)0x00000800)

Definition at line 384 of file stm32f10x_sdio.h.

#define SDIO_FLAG_CMDREND ((uint32_t)0x00000040)

Definition at line 379 of file stm32f10x_sdio.h.

Referenced by CmdResp1Error(), CmdResp2Error(), CmdResp3Error(), CmdResp6Error(), CmdResp7Error(), and IsCardProgramming().

#define SDIO_FLAG_CMDSENT ((uint32_t)0x00000080)

Definition at line 380 of file stm32f10x_sdio.h.

Referenced by CmdError().

#define SDIO_FLAG_CTIMEOUT ((uint32_t)0x00000004)

Definition at line 375 of file stm32f10x_sdio.h.

Referenced by CmdResp1Error(), CmdResp2Error(), CmdResp3Error(), CmdResp6Error(), CmdResp7Error(), and IsCardProgramming().

#define SDIO_FLAG_DATAEND ((uint32_t)0x00000100)

Definition at line 381 of file stm32f10x_sdio.h.

#define SDIO_FLAG_DBCKEND ((uint32_t)0x00000400)

Definition at line 383 of file stm32f10x_sdio.h.

Referenced by FindSCR(), SD_ReadBlock(), SD_SendSDStatus(), and SD_WriteBlock().

#define SDIO_FLAG_DCRCFAIL ((uint32_t)0x00000002)

Definition at line 374 of file stm32f10x_sdio.h.

Referenced by FindSCR(), SD_ReadBlock(), SD_SendSDStatus(), and SD_WriteBlock().

#define SDIO_FLAG_DTIMEOUT ((uint32_t)0x00000008)

Definition at line 376 of file stm32f10x_sdio.h.

Referenced by FindSCR(), SD_ReadBlock(), SD_SendSDStatus(), and SD_WriteBlock().

#define SDIO_FLAG_RXACT ((uint32_t)0x00002000)

Definition at line 386 of file stm32f10x_sdio.h.

Referenced by SD_GetTransferState().

#define SDIO_FLAG_RXDAVL ((uint32_t)0x00200000)

Definition at line 394 of file stm32f10x_sdio.h.

Referenced by FindSCR(), SD_ReadBlock(), and SD_SendSDStatus().

#define SDIO_FLAG_RXFIFOE ((uint32_t)0x00080000)

Definition at line 392 of file stm32f10x_sdio.h.

#define SDIO_FLAG_RXFIFOF ((uint32_t)0x00020000)

Definition at line 390 of file stm32f10x_sdio.h.

#define SDIO_FLAG_RXFIFOHF ((uint32_t)0x00008000)

Definition at line 388 of file stm32f10x_sdio.h.

Referenced by SD_ReadBlock(), and SD_SendSDStatus().

#define SDIO_FLAG_RXOVERR ((uint32_t)0x00000020)

Definition at line 378 of file stm32f10x_sdio.h.

Referenced by FindSCR(), SD_ReadBlock(), and SD_SendSDStatus().

#define SDIO_FLAG_SDIOIT ((uint32_t)0x00400000)

Definition at line 395 of file stm32f10x_sdio.h.

#define SDIO_FLAG_STBITERR ((uint32_t)0x00000200)

Definition at line 382 of file stm32f10x_sdio.h.

Referenced by FindSCR(), SD_ReadBlock(), SD_SendSDStatus(), and SD_WriteBlock().

#define SDIO_FLAG_TXACT ((uint32_t)0x00001000)

Definition at line 385 of file stm32f10x_sdio.h.

Referenced by SD_GetTransferState().

#define SDIO_FLAG_TXDAVL ((uint32_t)0x00100000)

Definition at line 393 of file stm32f10x_sdio.h.

#define SDIO_FLAG_TXFIFOE ((uint32_t)0x00040000)

Definition at line 391 of file stm32f10x_sdio.h.

#define SDIO_FLAG_TXFIFOF ((uint32_t)0x00010000)

Definition at line 389 of file stm32f10x_sdio.h.

#define SDIO_FLAG_TXFIFOHE ((uint32_t)0x00004000)

Definition at line 387 of file stm32f10x_sdio.h.

Referenced by SD_WriteBlock().

#define SDIO_FLAG_TXUNDERR ((uint32_t)0x00000010)

Definition at line 377 of file stm32f10x_sdio.h.

Referenced by SD_WriteBlock().


STM32F10x Standard Peripherals Firmware Library: SDIO_Read_Wait_Mode

Defines

SDIO_Read_Wait_Mode

SDIO_Exported_Constants

Defines

#define | IS_SDIO_READWAIT_MODE(MODE)
#define | SDIO_ReadWaitMode_CLK ((uint32_t)0x00000001)
#define | SDIO_ReadWaitMode_DATA2 ((uint32_t)0x00000000)

Define Documentation

#define IS_SDIO_READWAIT_MODE ( MODE )
Value:
(((MODE) == SDIO_ReadWaitMode_CLK) || \
                                     ((MODE) == SDIO_ReadWaitMode_DATA2))

Definition at line 461 of file stm32f10x_sdio.h.

Referenced by SDIO_SetSDIOReadWaitMode().

#define SDIO_ReadWaitMode_CLK ((uint32_t)0x00000001)

Definition at line 459 of file stm32f10x_sdio.h.

#define SDIO_ReadWaitMode_DATA2 ((uint32_t)0x00000000)

Definition at line 460 of file stm32f10x_sdio.h.


STM32F10x Standard Peripherals Firmware Library: SDIO_Exported_Macros

SDIO_Exported_Macros

SDIO


STM32F10x Standard Peripherals Firmware Library: SDIO_Exported_Functions

Functions

SDIO_Exported_Functions

SDIO

Functions

void | SDIO_CEATAITCmd (FunctionalState NewState)
Enables or disables the CE-ATA interrupt.
void | SDIO_ClearFlag (uint32_t SDIO_FLAG)
Clears the SDIO's pending flags.
void | SDIO_ClearITPendingBit (uint32_t SDIO_IT)
Clears the SDIO's interrupt pending bits.
void | SDIO_ClockCmd (FunctionalState NewState)
Enables or disables the SDIO Clock.
void | SDIO_CmdStructInit (SDIO_CmdInitTypeDef *SDIO_CmdInitStruct)
Fills each SDIO_CmdInitStruct member with its default value.
void | SDIO_CommandCompletionCmd (FunctionalState NewState)
Enables or disables the command completion signal.
void | SDIO_DataConfig (SDIO_DataInitTypeDef *SDIO_DataInitStruct)
Initializes the SDIO data path according to the specified parameters in the SDIO_DataInitStruct.
void | SDIO_DataStructInit (SDIO_DataInitTypeDef *SDIO_DataInitStruct)
Fills each SDIO_DataInitStruct member with its default value.
void | SDIO_DeInit (void)
Deinitializes the SDIO peripheral registers to their default reset values.
void | SDIO_DMACmd (FunctionalState NewState)
Enables or disables the SDIO DMA request.
uint8_t | SDIO_GetCommandResponse (void)
Returns command index of last command for which response received.
uint32_t | SDIO_GetDataCounter (void)
Returns number of remaining data bytes to be transferred.
uint32_t | SDIO_GetFIFOCount (void)
Returns the number of words left to be written to or read from FIFO.
FlagStatus | SDIO_GetFlagStatus (uint32_t SDIO_FLAG)
Checks whether the specified SDIO flag is set or not.
ITStatus | SDIO_GetITStatus (uint32_t SDIO_IT)
Checks whether the specified SDIO interrupt has occurred or not.
uint32_t | SDIO_GetPowerState (void)
Gets the power status of the controller.
uint32_t | SDIO_GetResponse (uint32_t SDIO_RESP)
Returns response received from the card for the last command.
void | SDIO_Init (SDIO_InitTypeDef *SDIO_InitStruct)
Initializes the SDIO peripheral according to the specified parameters in the SDIO_InitStruct.
void | SDIO_ITConfig (uint32_t SDIO_IT, FunctionalState NewState)
Enables or disables the SDIO interrupts.
uint32_t | SDIO_ReadData (void)
Read one data word from Rx FIFO.
void | SDIO_SendCEATACmd (FunctionalState NewState)
Sends CE-ATA command (CMD61).
void | SDIO_SendCommand (SDIO_CmdInitTypeDef *SDIO_CmdInitStruct)
Initializes the SDIO Command according to the specified parameters in the SDIO_CmdInitStruct and send the command.
void | SDIO_SendSDIOSuspendCmd (FunctionalState NewState)
Enables or disables the SD I/O Mode suspend command sending.
void | SDIO_SetPowerState (uint32_t SDIO_PowerState)
Sets the power status of the controller.
void | SDIO_SetSDIOOperation (FunctionalState NewState)
Enables or disables the SD I/O Mode Operation.
void | SDIO_SetSDIOReadWaitMode (uint32_t SDIO_ReadWaitMode)
Sets one of the two options of inserting read wait interval.
void | SDIO_StartSDIOReadWait (FunctionalState NewState)
Starts the SD I/O Read Wait operation.
void | SDIO_StopSDIOReadWait (FunctionalState NewState)
Stops the SD I/O Read Wait operation.
void | SDIO_StructInit (SDIO_InitTypeDef *SDIO_InitStruct)
Fills each SDIO_InitStruct member with its default value.
void | SDIO_WriteData (uint32_t Data)
Write one data word to Tx FIFO.

Function Documentation

void SDIO_CEATAITCmd ( FunctionalState NewState )

Enables or disables the CE-ATA interrupt.

Parameters:
NewState,: new state of CE-ATA interrupt. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 614 of file stm32f10x_sdio.c.

References assert_param, CMD_NIEN_BB, and IS_FUNCTIONAL_STATE.

void SDIO_ClearFlag ( uint32_t SDIO_FLAG )

Clears the SDIO's pending flags.

Parameters:
SDIO_FLAG,: specifies the flag to clear. This parameter can be one or a combination of the following values:

  • SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
  • SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
  • SDIO_FLAG_CTIMEOUT: Command response timeout
  • SDIO_FLAG_DTIMEOUT: Data timeout
  • SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
  • SDIO_FLAG_RXOVERR: Received FIFO overrun error
  • SDIO_FLAG_CMDREND: Command response received (CRC check passed)
  • SDIO_FLAG_CMDSENT: Command sent (no response required)
  • SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
  • SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode
  • SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
  • SDIO_FLAG_SDIOIT: SD I/O interrupt received
  • SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
Return values:
None

Definition at line 704 of file stm32f10x_sdio.c.

References assert_param, IS_SDIO_CLEAR_FLAG, and SDIO.

Referenced by CmdError(), CmdResp2Error(), CmdResp3Error(), CmdResp6Error(), CmdResp7Error(), FindSCR(), IsCardProgramming(), SD_ReadBlock(), SD_SendSDStatus(), SD_WaitWriteOperation(), and SD_WriteBlock().

void SDIO_ClearITPendingBit ( uint32_t SDIO_IT )

Clears the SDIO's interrupt pending bits.

Parameters:
SDIO_IT,: specifies the interrupt pending bit to clear. This parameter can be one or a combination of the following values:

  • SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
  • SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
  • SDIO_IT_CTIMEOUT: Command response timeout interrupt
  • SDIO_IT_DTIMEOUT: Data timeout interrupt
  • SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
  • SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
  • SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
  • SDIO_IT_CMDSENT: Command sent (no response required) interrupt
  • SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
  • SDIO_IT_STBITERR: Start bit not detected on all data signals in wide bus mode interrupt
  • SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
  • SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61
Return values:
None

Definition at line 779 of file stm32f10x_sdio.c.

References assert_param, IS_SDIO_CLEAR_IT, and SDIO.

Referenced by SD_ProcessIRQSrc().

void SDIO_ClockCmd ( FunctionalState NewState )

Enables or disables the SDIO Clock.

Parameters:
NewState,: new state of the SDIO Clock. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 235 of file stm32f10x_sdio.c.

References assert_param, CLKCR_CLKEN_BB, and IS_FUNCTIONAL_STATE.

Referenced by SD_LowLevel_DeInit(), and SD_PowerON().

void SDIO_CmdStructInit ( SDIO_CmdInitTypeDef * SDIO_CmdInitStruct )

Fills each SDIO_CmdInitStruct member with its default value.

Parameters:
SDIO_CmdInitStruct,: pointer to an SDIO_CmdInitTypeDef structure which will be initialized.
Return values:
None

Definition at line 382 of file stm32f10x_sdio.c.

References SDIO_CmdInitTypeDef::SDIO_Argument, SDIO_CmdInitTypeDef::SDIO_CmdIndex, SDIO_CmdInitTypeDef::SDIO_CPSM, SDIO_CPSM_Disable, SDIO_CmdInitTypeDef::SDIO_Response, SDIO_Response_No, SDIO_CmdInitTypeDef::SDIO_Wait, and SDIO_Wait_No.

void SDIO_CommandCompletionCmd ( FunctionalState NewState )

Enables or disables the command completion signal.

Parameters:
NewState,: new state of command completion signal. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 601 of file stm32f10x_sdio.c.

References assert_param, CMD_ENCMDCOMPL_BB, and IS_FUNCTIONAL_STATE.

void SDIO_DataConfig ( SDIO_DataInitTypeDef * SDIO_DataInitStruct )

Initializes the SDIO data path according to the specified parameters in the SDIO_DataInitStruct.

Parameters:
SDIO_DataInitStruct : pointer to a SDIO_DataInitTypeDef structure that contains the configuration information for the SDIO command.
Return values:
None

Definition at line 431 of file stm32f10x_sdio.c.

References assert_param, DCTRL_CLEAR_MASK, IS_SDIO_BLOCK_SIZE, IS_SDIO_DATA_LENGTH, IS_SDIO_DPSM, IS_SDIO_TRANSFER_DIR, IS_SDIO_TRANSFER_MODE, SDIO, SDIO_DataInitTypeDef::SDIO_DataBlockSize, SDIO_DataInitTypeDef::SDIO_DataLength, SDIO_DataInitTypeDef::SDIO_DataTimeOut, SDIO_DataInitTypeDef::SDIO_DPSM, SDIO_DataInitTypeDef::SDIO_TransferDir, and SDIO_DataInitTypeDef::SDIO_TransferMode.

Referenced by FindSCR(), SD_ReadBlock(), SD_ReadMultiBlocks(), SD_SendSDStatus(), SD_WriteBlock(), and SD_WriteMultiBlocks().

void SDIO_DataStructInit ( SDIO_DataInitTypeDef * SDIO_DataInitStruct )

Fills each SDIO_DataInitStruct member with its default value.

Parameters:
SDIO_DataInitStruct,: pointer to an SDIO_DataInitTypeDef structure which will be initialized.
Return values:
None

Definition at line 472 of file stm32f10x_sdio.c.

References SDIO_DataInitTypeDef::SDIO_DataBlockSize, SDIO_DataBlockSize_1b, SDIO_DataInitTypeDef::SDIO_DataLength, SDIO_DataInitTypeDef::SDIO_DataTimeOut, SDIO_DataInitTypeDef::SDIO_DPSM, SDIO_DPSM_Disable, SDIO_DataInitTypeDef::SDIO_TransferDir, SDIO_TransferDir_ToCard, SDIO_DataInitTypeDef::SDIO_TransferMode, and SDIO_TransferMode_Block.

void SDIO_DeInit ( void )

Deinitializes the SDIO peripheral registers to their default reset values.

Parameters:
None
Return values:
None

Definition at line 161 of file stm32f10x_sdio.c.

References SDIO.

Referenced by SD_Init(), and SD_LowLevel_DeInit().

void SDIO_DMACmd ( FunctionalState NewState )

Enables or disables the SDIO DMA request.

Parameters:
NewState,: new state of the selected SDIO DMA request. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 331 of file stm32f10x_sdio.c.

References assert_param, DCTRL_DMAEN_BB, and IS_FUNCTIONAL_STATE.

Referenced by SD_ReadBlock(), SD_ReadMultiBlocks(), SD_WriteBlock(), and SD_WriteMultiBlocks().

uint8_t SDIO_GetCommandResponse ( void )

Returns command index of last command for which response received.

Parameters:
None
Return values:
Returns the command index of the last command response received.

Definition at line 397 of file stm32f10x_sdio.c.

References SDIO.

Referenced by CmdResp6Error(), and IsCardProgramming().

uint32_t SDIO_GetDataCounter ( void )

Returns number of remaining data bytes to be transferred.

Parameters:
None
Return values:
Number of remaining data bytes to be transferred

Definition at line 488 of file stm32f10x_sdio.c.

References SDIO.

uint32_t SDIO_GetFIFOCount ( void )

Returns the number of words left to be written to or read from FIFO.

Parameters:
None
Return values:
Remaining number of words.

Definition at line 518 of file stm32f10x_sdio.c.

References SDIO.

FlagStatus SDIO_GetFlagStatus ( uint32_t SDIO_FLAG )

Checks whether the specified SDIO flag is set or not.

Parameters:
SDIO_FLAG,: specifies the flag to check. This parameter can be one of the following values:

  • SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
  • SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
  • SDIO_FLAG_CTIMEOUT: Command response timeout
  • SDIO_FLAG_DTIMEOUT: Data timeout
  • SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
  • SDIO_FLAG_RXOVERR: Received FIFO overrun error
  • SDIO_FLAG_CMDREND: Command response received (CRC check passed)
  • SDIO_FLAG_CMDSENT: Command sent (no response required)
  • SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
  • SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode.
  • SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
  • SDIO_FLAG_CMDACT: Command transfer in progress
  • SDIO_FLAG_TXACT: Data transmit in progress
  • SDIO_FLAG_RXACT: Data receive in progress
  • SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
  • SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
  • SDIO_FLAG_TXFIFOF: Transmit FIFO full
  • SDIO_FLAG_RXFIFOF: Receive FIFO full
  • SDIO_FLAG_TXFIFOE: Transmit FIFO empty
  • SDIO_FLAG_RXFIFOE: Receive FIFO empty
  • SDIO_FLAG_TXDAVL: Data available in transmit FIFO
  • SDIO_FLAG_RXDAVL: Data available in receive FIFO
  • SDIO_FLAG_SDIOIT: SD I/O interrupt received
  • SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
Return values:
The new state of SDIO_FLAG (SET or RESET).

Definition at line 666 of file stm32f10x_sdio.c.

References assert_param, IS_SDIO_FLAG, RESET, SDIO, and SET.

Referenced by CmdError(), FindSCR(), SD_ReadBlock(), SD_SendSDStatus(), and SD_WriteBlock().

ITStatus SDIO_GetITStatus ( uint32_t SDIO_IT )

Checks whether the specified SDIO interrupt has occurred or not.

Parameters:
SDIO_IT,: specifies the SDIO interrupt source to check. This parameter can be one of the following values:

  • SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
  • SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
  • SDIO_IT_CTIMEOUT: Command response timeout interrupt
  • SDIO_IT_DTIMEOUT: Data timeout interrupt
  • SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
  • SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
  • SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
  • SDIO_IT_CMDSENT: Command sent (no response required) interrupt
  • SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
  • SDIO_IT_STBITERR: Start bit not detected on all data signals in wide bus mode interrupt
  • SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
  • SDIO_IT_CMDACT: Command transfer in progress interrupt
  • SDIO_IT_TXACT: Data transmit in progress interrupt
  • SDIO_IT_RXACT: Data receive in progress interrupt
  • SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
  • SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
  • SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
  • SDIO_IT_RXFIFOF: Receive FIFO full interrupt
  • SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
  • SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
  • SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
  • SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
  • SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
  • SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
Return values:
The new state of SDIO_IT (SET or RESET).

Definition at line 743 of file stm32f10x_sdio.c.

References assert_param, IS_SDIO_GET_IT, RESET, SDIO, and SET.

uint32_t SDIO_GetPowerState ( void )

Gets the power status of the controller.

Parameters:
None
Return values:
Power status of the controller. The returned value can be one of the following:

  • 0x00: Power OFF
  • 0x02: Power UP
  • 0x03: Power ON

Definition at line 269 of file stm32f10x_sdio.c.

References PWR_PWRCTRL_MASK, and SDIO.

Referenced by SD_InitializeCards().

uint32_t SDIO_GetResponse ( uint32_t SDIO_RESP )

Returns response received from the card for the last command.

Parameters:
SDIO_RESP,: Specifies the SDIO response register. This parameter can be one of the following values:

  • SDIO_RESP1: Response Register 1
  • SDIO_RESP2: Response Register 2
  • SDIO_RESP3: Response Register 3
  • SDIO_RESP4: Response Register 4
Return values:
The Corresponding response register value.

Definition at line 412 of file stm32f10x_sdio.c.

References assert_param, IS_SDIO_RESP, and SDIO_RESP_ADDR.

Referenced by CmdResp6Error(), IsCardProgramming(), SD_Erase(), SD_InitializeCards(), SD_PowerON(), SD_SendSDStatus(), and SDEnWideBus().

void SDIO_Init ( SDIO_InitTypeDef * SDIO_InitStruct )

Initializes the SDIO peripheral according to the specified parameters in the SDIO_InitStruct.

Parameters:
SDIO_InitStruct : pointer to a SDIO_InitTypeDef structure that contains the configuration information for the SDIO peripheral.
Return values:
None

Definition at line 181 of file stm32f10x_sdio.c.

References assert_param, CLKCR_CLEAR_MASK, IS_SDIO_BUS_WIDE, IS_SDIO_CLOCK_BYPASS, IS_SDIO_CLOCK_EDGE, IS_SDIO_CLOCK_POWER_SAVE, IS_SDIO_HARDWARE_FLOW_CONTROL, SDIO, SDIO_InitTypeDef::SDIO_BusWide, SDIO_InitTypeDef::SDIO_ClockBypass, SDIO_InitTypeDef::SDIO_ClockDiv, SDIO_InitTypeDef::SDIO_ClockEdge, SDIO_InitTypeDef::SDIO_ClockPowerSave, and SDIO_InitTypeDef::SDIO_HardwareFlowControl.

Referenced by SD_EnableWideBusOperation(), SD_Init(), and SD_PowerON().

void SDIO_ITConfig | ( | uint32_t | SDIO_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the SDIO interrupts.

Parameters:
SDIO_IT,: specifies the SDIO interrupt sources to be enabled or disabled. This parameter can be one or a combination of the following values:

  • SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
  • SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
  • SDIO_IT_CTIMEOUT: Command response timeout interrupt
  • SDIO_IT_DTIMEOUT: Data timeout interrupt
  • SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
  • SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
  • SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
  • SDIO_IT_CMDSENT: Command sent (no response required) interrupt
  • SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
  • SDIO_IT_STBITERR: Start bit not detected on all data signals in wide bus mode interrupt
  • SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
  • SDIO_IT_CMDACT: Command transfer in progress interrupt
  • SDIO_IT_TXACT: Data transmit in progress interrupt
  • SDIO_IT_RXACT: Data receive in progress interrupt
  • SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
  • SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
  • SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
  • SDIO_IT_RXFIFOF: Receive FIFO full interrupt
  • SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
  • SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
  • SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
  • SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
  • SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
  • SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
NewState,: new state of the specified SDIO interrupts. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 307 of file stm32f10x_sdio.c.

References assert_param, DISABLE, IS_FUNCTIONAL_STATE, IS_SDIO_IT, and SDIO.

Referenced by SD_ProcessIRQSrc(), SD_ReadBlock(), SD_ReadMultiBlocks(), SD_WriteBlock(), and SD_WriteMultiBlocks().

uint32_t SDIO_ReadData ( void )

Read one data word from Rx FIFO.

Parameters:
None
Return values:
Data received

Definition at line 498 of file stm32f10x_sdio.c.

References SDIO.

Referenced by FindSCR(), SD_ReadBlock(), and SD_SendSDStatus().

void SDIO_SendCEATACmd ( FunctionalState NewState )

Sends CE-ATA command (CMD61).

Parameters:
NewState,: new state of CE-ATA command. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 627 of file stm32f10x_sdio.c.

References assert_param, CMD_ATACMD_BB, and IS_FUNCTIONAL_STATE.

void SDIO_SendCommand ( SDIO_CmdInitTypeDef * SDIO_CmdInitStruct )

Initializes the SDIO Command according to the specified parameters in the SDIO_CmdInitStruct and send the command.

Parameters:
SDIO_CmdInitStruct : pointer to a SDIO_CmdInitTypeDef structure that contains the configuration information for the SDIO command.
Return values:
None

Definition at line 346 of file stm32f10x_sdio.c.

References assert_param, CMD_CLEAR_MASK, IS_SDIO_CMD_INDEX, IS_SDIO_CPSM, IS_SDIO_RESPONSE, IS_SDIO_WAIT, SDIO, SDIO_CmdInitTypeDef::SDIO_Argument, SDIO_CmdInitTypeDef::SDIO_CmdIndex, SDIO_CmdInitTypeDef::SDIO_CPSM, SDIO_CmdInitTypeDef::SDIO_Response, and SDIO_CmdInitTypeDef::SDIO_Wait.

Referenced by FindSCR(), IsCardProgramming(), SD_Erase(), SD_InitializeCards(), SD_PowerON(), SD_ReadBlock(), SD_ReadMultiBlocks(), SD_SelectDeselect(), SD_SendSDStatus(), SD_WriteBlock(), SD_WriteMultiBlocks(), and SDEnWideBus().

void SDIO_SendSDIOSuspendCmd ( FunctionalState NewState )

Enables or disables the SD I/O Mode suspend command sending.

Parameters:
NewState,: new state of the SD I/O Mode suspend command. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 587 of file stm32f10x_sdio.c.

References assert_param, CMD_SDIOSUSPEND_BB, and IS_FUNCTIONAL_STATE.

void SDIO_SetPowerState ( uint32_t SDIO_PowerState )

Sets the power status of the controller.

Parameters:
SDIO_PowerState,: new state of the Power state. This parameter can be one of the following values:

  • SDIO_PowerState_OFF
  • SDIO_PowerState_ON
Return values:
None

Definition at line 251 of file stm32f10x_sdio.c.

References assert_param, IS_SDIO_POWER_STATE, PWR_PWRCTRL_MASK, and SDIO.

Referenced by SD_LowLevel_DeInit(), SD_PowerOFF(), and SD_PowerON().

void SDIO_SetSDIOOperation ( FunctionalState NewState )

Enables or disables the SD I/O Mode Operation.

Parameters:
NewState,: new state of SDIO specific operation. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 573 of file stm32f10x_sdio.c.

References assert_param, DCTRL_SDIOEN_BB, and IS_FUNCTIONAL_STATE.

void SDIO_SetSDIOReadWaitMode ( uint32_t SDIO_ReadWaitMode )

Sets one of the two options of inserting read wait interval.

Parameters:
SDIO_ReadWaitMode,: SD I/O Read Wait operation mode. This parameter can be:

  • SDIO_ReadWaitMode_CLK: Read Wait control by stopping SDIOCLK
  • SDIO_ReadWaitMode_DATA2: Read Wait control using SDIO_DATA2
Return values:
None

Definition at line 559 of file stm32f10x_sdio.c.

References assert_param, DCTRL_RWMOD_BB, and IS_SDIO_READWAIT_MODE.

void SDIO_StartSDIOReadWait ( FunctionalState NewState )

Starts the SD I/O Read Wait operation.

Parameters:
NewState,: new state of the Start SDIO Read Wait operation. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 529 of file stm32f10x_sdio.c.

References assert_param, DCTRL_RWSTART_BB, and IS_FUNCTIONAL_STATE.

void SDIO_StopSDIOReadWait ( FunctionalState NewState )

Stops the SD I/O Read Wait operation.

Parameters:
NewState,: new state of the Stop SDIO Read Wait operation. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 543 of file stm32f10x_sdio.c.

References assert_param, DCTRL_RWSTOP_BB, and IS_FUNCTIONAL_STATE.

void SDIO_StructInit ( SDIO_InitTypeDef * SDIO_InitStruct )

Fills each SDIO_InitStruct member with its default value.

Parameters:
SDIO_InitStruct,: pointer to an SDIO_InitTypeDef structure which will be initialized.
Return values:
None

Definition at line 219 of file stm32f10x_sdio.c.

References SDIO_InitTypeDef::SDIO_BusWide, SDIO_BusWide_1b, SDIO_InitTypeDef::SDIO_ClockBypass, SDIO_ClockBypass_Disable, SDIO_InitTypeDef::SDIO_ClockDiv, SDIO_InitTypeDef::SDIO_ClockEdge, SDIO_ClockEdge_Rising, SDIO_InitTypeDef::SDIO_ClockPowerSave, SDIO_ClockPowerSave_Disable, SDIO_InitTypeDef::SDIO_HardwareFlowControl, and SDIO_HardwareFlowControl_Disable.

void SDIO_WriteData ( uint32_t Data )

Write one data word to Tx FIFO.

Parameters:
Data,: 32-bit data word to write.
Return values:
None

Definition at line 508 of file stm32f10x_sdio.c.

References Data, and SDIO.

Referenced by SD_WriteBlock().


STM32F10x Standard Peripherals Firmware Library: SDIO_Private_TypesDefinitions

Defines

SDIO_Private_TypesDefinitions

SDIO

Defines

#define | ATACMD_BitNumber 0x0E
#define | CLKCR_CLEAR_MASK ((uint32_t)0xFFFF8100)
#define | CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4))
#define | CLKCR_OFFSET (SDIO_OFFSET + 0x04)
#define | CLKEN_BitNumber 0x08
#define | CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4))
#define | CMD_CLEAR_MASK ((uint32_t)0xFFFFF800)
#define | CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4))
#define | CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4))
#define | CMD_OFFSET (SDIO_OFFSET + 0x0C)
#define | CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4))
#define | DCTRL_CLEAR_MASK ((uint32_t)0xFFFFFF08)
#define | DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4))
#define | DCTRL_OFFSET (SDIO_OFFSET + 0x2C)
#define | DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4))
#define | DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4))
#define | DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4))
#define | DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4))
#define | DMAEN_BitNumber 0x03
#define | ENCMDCOMPL_BitNumber 0x0C
#define | NIEN_BitNumber 0x0D
#define | PWR_PWRCTRL_MASK ((uint32_t)0xFFFFFFFC)
#define | RWMOD_BitNumber 0x0A
#define | RWSTART_BitNumber 0x08
#define | RWSTOP_BitNumber 0x09
#define | SDIO_OFFSET (SDIO_BASE - PERIPH_BASE)
#define | SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14))
#define | SDIOEN_BitNumber 0x0B
#define | SDIOSUSPEND_BitNumber 0x0B

Define Documentation

#define ATACMD_BitNumber 0x0E

Definition at line 65 of file stm32f10x_sdio.c.

#define CLKCR_CLEAR_MASK ((uint32_t)0xFFFF8100)

Definition at line 96 of file stm32f10x_sdio.c.

Referenced by SDIO_Init().

#define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4))

Definition at line 47 of file stm32f10x_sdio.c.

Referenced by SDIO_ClockCmd().

#define CLKCR_OFFSET (SDIO_OFFSET + 0x04)

Definition at line 45 of file stm32f10x_sdio.c.

#define CLKEN_BitNumber 0x08

Definition at line 46 of file stm32f10x_sdio.c.

#define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4))

Definition at line 66 of file stm32f10x_sdio.c.

Referenced by SDIO_SendCEATACmd().

#define CMD_CLEAR_MASK ((uint32_t)0xFFFFF800)

Definition at line 111 of file stm32f10x_sdio.c.

Referenced by SDIO_SendCommand().

#define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4))

Definition at line 58 of file stm32f10x_sdio.c.

Referenced by SDIO_CommandCompletionCmd().

#define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4))

Definition at line 62 of file stm32f10x_sdio.c.

Referenced by SDIO_CEATAITCmd().

#define CMD_OFFSET (SDIO_OFFSET + 0x0C)

Definition at line 52 of file stm32f10x_sdio.c.

#define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4))

Definition at line 54 of file stm32f10x_sdio.c.

Referenced by SDIO_SendSDIOSuspendCmd().

#define DCTRL_CLEAR_MASK ((uint32_t)0xFFFFFF08)

Definition at line 106 of file stm32f10x_sdio.c.

Referenced by SDIO_DataConfig().

#define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4))

Definition at line 73 of file stm32f10x_sdio.c.

Referenced by SDIO_DMACmd().

#define DCTRL_OFFSET (SDIO_OFFSET + 0x2C)

Definition at line 71 of file stm32f10x_sdio.c.

#define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4))

Definition at line 85 of file stm32f10x_sdio.c.

Referenced by SDIO_SetSDIOReadWaitMode().

#define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4))

Definition at line 77 of file stm32f10x_sdio.c.

Referenced by SDIO_StartSDIOReadWait().

#define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4))

Definition at line 81 of file stm32f10x_sdio.c.

Referenced by SDIO_StopSDIOReadWait().

#define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4))

Definition at line 89 of file stm32f10x_sdio.c.

Referenced by SDIO_SetSDIOOperation().

#define DMAEN_BitNumber 0x03

Definition at line 72 of file stm32f10x_sdio.c.

#define ENCMDCOMPL_BitNumber 0x0C

Definition at line 57 of file stm32f10x_sdio.c.

#define NIEN_BitNumber 0x0D

Definition at line 61 of file stm32f10x_sdio.c.

#define PWR_PWRCTRL_MASK ((uint32_t)0xFFFFFFFC)

Definition at line 101 of file stm32f10x_sdio.c.

Referenced by SDIO_GetPowerState(), and SDIO_SetPowerState().

#define RWMOD_BitNumber 0x0A

Definition at line 84 of file stm32f10x_sdio.c.

#define RWSTART_BitNumber 0x08

Definition at line 76 of file stm32f10x_sdio.c.

#define RWSTOP_BitNumber 0x09

Definition at line 80 of file stm32f10x_sdio.c.

#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE)

Definition at line 40 of file stm32f10x_sdio.c.

#define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14))

Definition at line 114 of file stm32f10x_sdio.c.

Referenced by SDIO_GetResponse().

#define SDIOEN_BitNumber 0x0B

Definition at line 88 of file stm32f10x_sdio.c.

#define SDIOSUSPEND_BitNumber 0x0B

Definition at line 53 of file stm32f10x_sdio.c.


STM32F10x Standard Peripherals Firmware Library: SDIO_Private_Defines

SDIO_Private_Defines

SDIO


STM32F10x Standard Peripherals Firmware Library: SDIO_Private_Macros

SDIO_Private_Macros

SDIO


STM32F10x Standard Peripherals Firmware Library: SDIO_Private_Variables

SDIO_Private_Variables

SDIO


STM32F10x Standard Peripherals Firmware Library: SDIO_Private_FunctionPrototypes

SDIO_Private_FunctionPrototypes

SDIO


STM32F10x Standard Peripherals Firmware Library: SDIO_Private_Functions

Functions

SDIO_Private_Functions

SDIO

Functions

void | SDIO_CEATAITCmd (FunctionalState NewState)
Enables or disables the CE-ATA interrupt.
void | SDIO_ClearFlag (uint32_t SDIO_FLAG)
Clears the SDIO's pending flags.
void | SDIO_ClearITPendingBit (uint32_t SDIO_IT)
Clears the SDIO's interrupt pending bits.
void | SDIO_ClockCmd (FunctionalState NewState)
Enables or disables the SDIO Clock.
void | SDIO_CmdStructInit (SDIO_CmdInitTypeDef *SDIO_CmdInitStruct)
Fills each SDIO_CmdInitStruct member with its default value.
void | SDIO_CommandCompletionCmd (FunctionalState NewState)
Enables or disables the command completion signal.
void | SDIO_DataConfig (SDIO_DataInitTypeDef *SDIO_DataInitStruct)
Initializes the SDIO data path according to the specified parameters in the SDIO_DataInitStruct.
void | SDIO_DataStructInit (SDIO_DataInitTypeDef *SDIO_DataInitStruct)
Fills each SDIO_DataInitStruct member with its default value.
void | SDIO_DeInit (void)
Deinitializes the SDIO peripheral registers to their default reset values.
void | SDIO_DMACmd (FunctionalState NewState)
Enables or disables the SDIO DMA request.
uint8_t | SDIO_GetCommandResponse (void)
Returns command index of last command for which response received.
uint32_t | SDIO_GetDataCounter (void)
Returns number of remaining data bytes to be transferred.
uint32_t | SDIO_GetFIFOCount (void)
Returns the number of words left to be written to or read from FIFO.
FlagStatus | SDIO_GetFlagStatus (uint32_t SDIO_FLAG)
Checks whether the specified SDIO flag is set or not.
ITStatus | SDIO_GetITStatus (uint32_t SDIO_IT)
Checks whether the specified SDIO interrupt has occurred or not.
uint32_t | SDIO_GetPowerState (void)
Gets the power status of the controller.
uint32_t | SDIO_GetResponse (uint32_t SDIO_RESP)
Returns response received from the card for the last command.
void | SDIO_Init (SDIO_InitTypeDef *SDIO_InitStruct)
Initializes the SDIO peripheral according to the specified parameters in the SDIO_InitStruct.
void | SDIO_ITConfig (uint32_t SDIO_IT, FunctionalState NewState)
Enables or disables the SDIO interrupts.
uint32_t | SDIO_ReadData (void)
Read one data word from Rx FIFO.
void | SDIO_SendCEATACmd (FunctionalState NewState)
Sends CE-ATA command (CMD61).
void | SDIO_SendCommand (SDIO_CmdInitTypeDef *SDIO_CmdInitStruct)
Initializes the SDIO Command according to the specified parameters in the SDIO_CmdInitStruct and send the command.
void | SDIO_SendSDIOSuspendCmd (FunctionalState NewState)
Enables or disables the SD I/O Mode suspend command sending.
void | SDIO_SetPowerState (uint32_t SDIO_PowerState)
Sets the power status of the controller.
void | SDIO_SetSDIOOperation (FunctionalState NewState)
Enables or disables the SD I/O Mode Operation.
void | SDIO_SetSDIOReadWaitMode (uint32_t SDIO_ReadWaitMode)
Sets one of the two options of inserting read wait interval.
void | SDIO_StartSDIOReadWait (FunctionalState NewState)
Starts the SD I/O Read Wait operation.
void | SDIO_StopSDIOReadWait (FunctionalState NewState)
Stops the SD I/O Read Wait operation.
void | SDIO_StructInit (SDIO_InitTypeDef *SDIO_InitStruct)
Fills each SDIO_InitStruct member with its default value.
void | SDIO_WriteData (uint32_t Data)
Write one data word to Tx FIFO.

Function Documentation

void SDIO_CEATAITCmd ( FunctionalState NewState )

Enables or disables the CE-ATA interrupt.

Parameters:
NewState,: new state of CE-ATA interrupt. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 614 of file stm32f10x_sdio.c.

References assert_param, CMD_NIEN_BB, and IS_FUNCTIONAL_STATE.

void SDIO_ClearFlag ( uint32_t SDIO_FLAG )

Clears the SDIO's pending flags.

Parameters:
SDIO_FLAG,: specifies the flag to clear. This parameter can be one or a combination of the following values:

  • SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
  • SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
  • SDIO_FLAG_CTIMEOUT: Command response timeout
  • SDIO_FLAG_DTIMEOUT: Data timeout
  • SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
  • SDIO_FLAG_RXOVERR: Received FIFO overrun error
  • SDIO_FLAG_CMDREND: Command response received (CRC check passed)
  • SDIO_FLAG_CMDSENT: Command sent (no response required)
  • SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
  • SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode
  • SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
  • SDIO_FLAG_SDIOIT: SD I/O interrupt received
  • SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
Return values:
None

Definition at line 704 of file stm32f10x_sdio.c.

References assert_param, IS_SDIO_CLEAR_FLAG, and SDIO.

Referenced by CmdError(), CmdResp2Error(), CmdResp3Error(), CmdResp6Error(), CmdResp7Error(), FindSCR(), IsCardProgramming(), SD_ReadBlock(), SD_SendSDStatus(), SD_WaitWriteOperation(), and SD_WriteBlock().

void SDIO_ClearITPendingBit ( uint32_t SDIO_IT )

Clears the SDIO's interrupt pending bits.

Parameters:
SDIO_IT,: specifies the interrupt pending bit to clear. This parameter can be one or a combination of the following values:

  • SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
  • SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
  • SDIO_IT_CTIMEOUT: Command response timeout interrupt
  • SDIO_IT_DTIMEOUT: Data timeout interrupt
  • SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
  • SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
  • SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
  • SDIO_IT_CMDSENT: Command sent (no response required) interrupt
  • SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
  • SDIO_IT_STBITERR: Start bit not detected on all data signals in wide bus mode interrupt
  • SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
  • SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61
Return values:
None

Definition at line 779 of file stm32f10x_sdio.c.

References assert_param, IS_SDIO_CLEAR_IT, and SDIO.

Referenced by SD_ProcessIRQSrc().

void SDIO_ClockCmd ( FunctionalState NewState )

Enables or disables the SDIO Clock.

Parameters:
NewState,: new state of the SDIO Clock. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 235 of file stm32f10x_sdio.c.

References assert_param, CLKCR_CLKEN_BB, and IS_FUNCTIONAL_STATE.

Referenced by SD_LowLevel_DeInit(), and SD_PowerON().

void SDIO_CmdStructInit ( SDIO_CmdInitTypeDef * SDIO_CmdInitStruct )

Fills each SDIO_CmdInitStruct member with its default value.

Parameters:
SDIO_CmdInitStruct,: pointer to an SDIO_CmdInitTypeDef structure which will be initialized.
Return values:
None

Definition at line 382 of file stm32f10x_sdio.c.

References SDIO_CmdInitTypeDef::SDIO_Argument, SDIO_CmdInitTypeDef::SDIO_CmdIndex, SDIO_CmdInitTypeDef::SDIO_CPSM, SDIO_CPSM_Disable, SDIO_CmdInitTypeDef::SDIO_Response, SDIO_Response_No, SDIO_CmdInitTypeDef::SDIO_Wait, and SDIO_Wait_No.

void SDIO_CommandCompletionCmd ( FunctionalState NewState )

Enables or disables the command completion signal.

Parameters:
NewState,: new state of command completion signal. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 601 of file stm32f10x_sdio.c.

References assert_param, CMD_ENCMDCOMPL_BB, and IS_FUNCTIONAL_STATE.

void SDIO_DataConfig ( SDIO_DataInitTypeDef * SDIO_DataInitStruct )

Initializes the SDIO data path according to the specified parameters in the SDIO_DataInitStruct.

Parameters:
SDIO_DataInitStruct : pointer to a SDIO_DataInitTypeDef structure that contains the configuration information for the SDIO command.
Return values:
None

Definition at line 431 of file stm32f10x_sdio.c.

References assert_param, DCTRL_CLEAR_MASK, IS_SDIO_BLOCK_SIZE, IS_SDIO_DATA_LENGTH, IS_SDIO_DPSM, IS_SDIO_TRANSFER_DIR, IS_SDIO_TRANSFER_MODE, SDIO, SDIO_DataInitTypeDef::SDIO_DataBlockSize, SDIO_DataInitTypeDef::SDIO_DataLength, SDIO_DataInitTypeDef::SDIO_DataTimeOut, SDIO_DataInitTypeDef::SDIO_DPSM, SDIO_DataInitTypeDef::SDIO_TransferDir, and SDIO_DataInitTypeDef::SDIO_TransferMode.

Referenced by FindSCR(), SD_ReadBlock(), SD_ReadMultiBlocks(), SD_SendSDStatus(), SD_WriteBlock(), and SD_WriteMultiBlocks().

void SDIO_DataStructInit ( SDIO_DataInitTypeDef * SDIO_DataInitStruct )

Fills each SDIO_DataInitStruct member with its default value.

Parameters:
SDIO_DataInitStruct,: pointer to an SDIO_DataInitTypeDef structure which will be initialized.
Return values:
None

Definition at line 472 of file stm32f10x_sdio.c.

References SDIO_DataInitTypeDef::SDIO_DataBlockSize, SDIO_DataBlockSize_1b, SDIO_DataInitTypeDef::SDIO_DataLength, SDIO_DataInitTypeDef::SDIO_DataTimeOut, SDIO_DataInitTypeDef::SDIO_DPSM, SDIO_DPSM_Disable, SDIO_DataInitTypeDef::SDIO_TransferDir, SDIO_TransferDir_ToCard, SDIO_DataInitTypeDef::SDIO_TransferMode, and SDIO_TransferMode_Block.

void SDIO_DeInit ( void )

Deinitializes the SDIO peripheral registers to their default reset values.

Parameters:
None
Return values:
None

Definition at line 161 of file stm32f10x_sdio.c.

References SDIO.

Referenced by SD_Init(), and SD_LowLevel_DeInit().

void SDIO_DMACmd ( FunctionalState NewState )

Enables or disables the SDIO DMA request.

Parameters:
NewState,: new state of the selected SDIO DMA request. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 331 of file stm32f10x_sdio.c.

References assert_param, DCTRL_DMAEN_BB, and IS_FUNCTIONAL_STATE.

Referenced by SD_ReadBlock(), SD_ReadMultiBlocks(), SD_WriteBlock(), and SD_WriteMultiBlocks().

uint8_t SDIO_GetCommandResponse ( void )

Returns command index of last command for which response received.

Parameters:
None
Return values:
Returns the command index of the last command response received.

Definition at line 397 of file stm32f10x_sdio.c.

References SDIO.

Referenced by CmdResp6Error(), and IsCardProgramming().

uint32_t SDIO_GetDataCounter ( void )

Returns number of remaining data bytes to be transferred.

Parameters:
None
Return values:
Number of remaining data bytes to be transferred

Definition at line 488 of file stm32f10x_sdio.c.

References SDIO.

uint32_t SDIO_GetFIFOCount ( void )

Returns the number of words left to be written to or read from FIFO.

Parameters:
None
Return values:
Remaining number of words.

Definition at line 518 of file stm32f10x_sdio.c.

References SDIO.

FlagStatus SDIO_GetFlagStatus ( uint32_t SDIO_FLAG )

Checks whether the specified SDIO flag is set or not.

Parameters:
SDIO_FLAG,: specifies the flag to check. This parameter can be one of the following values:

  • SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
  • SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
  • SDIO_FLAG_CTIMEOUT: Command response timeout
  • SDIO_FLAG_DTIMEOUT: Data timeout
  • SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
  • SDIO_FLAG_RXOVERR: Received FIFO overrun error
  • SDIO_FLAG_CMDREND: Command response received (CRC check passed)
  • SDIO_FLAG_CMDSENT: Command sent (no response required)
  • SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
  • SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode.
  • SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
  • SDIO_FLAG_CMDACT: Command transfer in progress
  • SDIO_FLAG_TXACT: Data transmit in progress
  • SDIO_FLAG_RXACT: Data receive in progress
  • SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
  • SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
  • SDIO_FLAG_TXFIFOF: Transmit FIFO full
  • SDIO_FLAG_RXFIFOF: Receive FIFO full
  • SDIO_FLAG_TXFIFOE: Transmit FIFO empty
  • SDIO_FLAG_RXFIFOE: Receive FIFO empty
  • SDIO_FLAG_TXDAVL: Data available in transmit FIFO
  • SDIO_FLAG_RXDAVL: Data available in receive FIFO
  • SDIO_FLAG_SDIOIT: SD I/O interrupt received
  • SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
Return values:
The new state of SDIO_FLAG (SET or RESET).

Definition at line 666 of file stm32f10x_sdio.c.

References assert_param, IS_SDIO_FLAG, RESET, SDIO, and SET.

Referenced by CmdError(), FindSCR(), SD_ReadBlock(), SD_SendSDStatus(), and SD_WriteBlock().

ITStatus SDIO_GetITStatus ( uint32_t SDIO_IT )

Checks whether the specified SDIO interrupt has occurred or not.

Parameters:
SDIO_IT,: specifies the SDIO interrupt source to check. This parameter can be one of the following values:

  • SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
  • SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
  • SDIO_IT_CTIMEOUT: Command response timeout interrupt
  • SDIO_IT_DTIMEOUT: Data timeout interrupt
  • SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
  • SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
  • SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
  • SDIO_IT_CMDSENT: Command sent (no response required) interrupt
  • SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
  • SDIO_IT_STBITERR: Start bit not detected on all data signals in wide bus mode interrupt
  • SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
  • SDIO_IT_CMDACT: Command transfer in progress interrupt
  • SDIO_IT_TXACT: Data transmit in progress interrupt
  • SDIO_IT_RXACT: Data receive in progress interrupt
  • SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
  • SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
  • SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
  • SDIO_IT_RXFIFOF: Receive FIFO full interrupt
  • SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
  • SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
  • SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
  • SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
  • SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
  • SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
Return values:
The new state of SDIO_IT (SET or RESET).

Definition at line 743 of file stm32f10x_sdio.c.

References assert_param, IS_SDIO_GET_IT, RESET, SDIO, and SET.

uint32_t SDIO_GetPowerState ( void )

Gets the power status of the controller.

Parameters:
None
Return values:
Power status of the controller. The returned value can be one of the following:

  • 0x00: Power OFF
  • 0x02: Power UP
  • 0x03: Power ON

Definition at line 269 of file stm32f10x_sdio.c.

References PWR_PWRCTRL_MASK, and SDIO.

Referenced by SD_InitializeCards().

uint32_t SDIO_GetResponse ( uint32_t SDIO_RESP )

Returns response received from the card for the last command.

Parameters:
SDIO_RESP,: Specifies the SDIO response register. This parameter can be one of the following values:

  • SDIO_RESP1: Response Register 1
  • SDIO_RESP2: Response Register 2
  • SDIO_RESP3: Response Register 3
  • SDIO_RESP4: Response Register 4
Return values:
The Corresponding response register value.

Definition at line 412 of file stm32f10x_sdio.c.

References assert_param, IS_SDIO_RESP, and SDIO_RESP_ADDR.

Referenced by CmdResp6Error(), IsCardProgramming(), SD_Erase(), SD_InitializeCards(), SD_PowerON(), SD_SendSDStatus(), and SDEnWideBus().

void SDIO_Init ( SDIO_InitTypeDef * SDIO_InitStruct )

Initializes the SDIO peripheral according to the specified parameters in the SDIO_InitStruct.

Parameters:
SDIO_InitStruct : pointer to a SDIO_InitTypeDef structure that contains the configuration information for the SDIO peripheral.
Return values:
None

Definition at line 181 of file stm32f10x_sdio.c.

References assert_param, CLKCR_CLEAR_MASK, IS_SDIO_BUS_WIDE, IS_SDIO_CLOCK_BYPASS, IS_SDIO_CLOCK_EDGE, IS_SDIO_CLOCK_POWER_SAVE, IS_SDIO_HARDWARE_FLOW_CONTROL, SDIO, SDIO_InitTypeDef::SDIO_BusWide, SDIO_InitTypeDef::SDIO_ClockBypass, SDIO_InitTypeDef::SDIO_ClockDiv, SDIO_InitTypeDef::SDIO_ClockEdge, SDIO_InitTypeDef::SDIO_ClockPowerSave, and SDIO_InitTypeDef::SDIO_HardwareFlowControl.

Referenced by SD_EnableWideBusOperation(), SD_Init(), and SD_PowerON().

void SDIO_ITConfig | ( | uint32_t | SDIO_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the SDIO interrupts.

Parameters:
SDIO_IT,: specifies the SDIO interrupt sources to be enabled or disabled. This parameter can be one or a combination of the following values:

  • SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
  • SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
  • SDIO_IT_CTIMEOUT: Command response timeout interrupt
  • SDIO_IT_DTIMEOUT: Data timeout interrupt
  • SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
  • SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
  • SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
  • SDIO_IT_CMDSENT: Command sent (no response required) interrupt
  • SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
  • SDIO_IT_STBITERR: Start bit not detected on all data signals in wide bus mode interrupt
  • SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
  • SDIO_IT_CMDACT: Command transfer in progress interrupt
  • SDIO_IT_TXACT: Data transmit in progress interrupt
  • SDIO_IT_RXACT: Data receive in progress interrupt
  • SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
  • SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
  • SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
  • SDIO_IT_RXFIFOF: Receive FIFO full interrupt
  • SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
  • SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
  • SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
  • SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
  • SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
  • SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
NewState,: new state of the specified SDIO interrupts. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 307 of file stm32f10x_sdio.c.

References assert_param, DISABLE, IS_FUNCTIONAL_STATE, IS_SDIO_IT, and SDIO.

Referenced by SD_ProcessIRQSrc(), SD_ReadBlock(), SD_ReadMultiBlocks(), SD_WriteBlock(), and SD_WriteMultiBlocks().

uint32_t SDIO_ReadData ( void )

Read one data word from Rx FIFO.

Parameters:
None
Return values:
Data received

Definition at line 498 of file stm32f10x_sdio.c.

References SDIO.

Referenced by FindSCR(), SD_ReadBlock(), and SD_SendSDStatus().

void SDIO_SendCEATACmd ( FunctionalState NewState )

Sends CE-ATA command (CMD61).

Parameters:
NewState,: new state of CE-ATA command. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 627 of file stm32f10x_sdio.c.

References assert_param, CMD_ATACMD_BB, and IS_FUNCTIONAL_STATE.

void SDIO_SendCommand ( SDIO_CmdInitTypeDef * SDIO_CmdInitStruct )

Initializes the SDIO Command according to the specified parameters in the SDIO_CmdInitStruct and send the command.

Parameters:
SDIO_CmdInitStruct : pointer to a SDIO_CmdInitTypeDef structure that contains the configuration information for the SDIO command.
Return values:
None

Definition at line 346 of file stm32f10x_sdio.c.

References assert_param, CMD_CLEAR_MASK, IS_SDIO_CMD_INDEX, IS_SDIO_CPSM, IS_SDIO_RESPONSE, IS_SDIO_WAIT, SDIO, SDIO_CmdInitTypeDef::SDIO_Argument, SDIO_CmdInitTypeDef::SDIO_CmdIndex, SDIO_CmdInitTypeDef::SDIO_CPSM, SDIO_CmdInitTypeDef::SDIO_Response, and SDIO_CmdInitTypeDef::SDIO_Wait.

Referenced by FindSCR(), IsCardProgramming(), SD_Erase(), SD_InitializeCards(), SD_PowerON(), SD_ReadBlock(), SD_ReadMultiBlocks(), SD_SelectDeselect(), SD_SendSDStatus(), SD_WriteBlock(), SD_WriteMultiBlocks(), and SDEnWideBus().

void SDIO_SendSDIOSuspendCmd ( FunctionalState NewState )

Enables or disables the SD I/O Mode suspend command sending.

Parameters:
NewState,: new state of the SD I/O Mode suspend command. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 587 of file stm32f10x_sdio.c.

References assert_param, CMD_SDIOSUSPEND_BB, and IS_FUNCTIONAL_STATE.

void SDIO_SetPowerState ( uint32_t SDIO_PowerState )

Sets the power status of the controller.

Parameters:
SDIO_PowerState,: new state of the Power state. This parameter can be one of the following values:

  • SDIO_PowerState_OFF
  • SDIO_PowerState_ON
Return values:
None

Definition at line 251 of file stm32f10x_sdio.c.

References assert_param, IS_SDIO_POWER_STATE, PWR_PWRCTRL_MASK, and SDIO.

Referenced by SD_LowLevel_DeInit(), SD_PowerOFF(), and SD_PowerON().

void SDIO_SetSDIOOperation ( FunctionalState NewState )

Enables or disables the SD I/O Mode Operation.

Parameters:
NewState,: new state of SDIO specific operation. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 573 of file stm32f10x_sdio.c.

References assert_param, DCTRL_SDIOEN_BB, and IS_FUNCTIONAL_STATE.

void SDIO_SetSDIOReadWaitMode ( uint32_t SDIO_ReadWaitMode )

Sets one of the two options of inserting read wait interval.

Parameters:
SDIO_ReadWaitMode,: SD I/O Read Wait operation mode. This parameter can be:

  • SDIO_ReadWaitMode_CLK: Read Wait control by stopping SDIOCLK
  • SDIO_ReadWaitMode_DATA2: Read Wait control using SDIO_DATA2
Return values:
None

Definition at line 559 of file stm32f10x_sdio.c.

References assert_param, DCTRL_RWMOD_BB, and IS_SDIO_READWAIT_MODE.

void SDIO_StartSDIOReadWait ( FunctionalState NewState )

Starts the SD I/O Read Wait operation.

Parameters:
NewState,: new state of the Start SDIO Read Wait operation. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 529 of file stm32f10x_sdio.c.

References assert_param, DCTRL_RWSTART_BB, and IS_FUNCTIONAL_STATE.

void SDIO_StopSDIOReadWait ( FunctionalState NewState )

Stops the SD I/O Read Wait operation.

Parameters:
NewState,: new state of the Stop SDIO Read Wait operation. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 543 of file stm32f10x_sdio.c.

References assert_param, DCTRL_RWSTOP_BB, and IS_FUNCTIONAL_STATE.

void SDIO_StructInit ( SDIO_InitTypeDef * SDIO_InitStruct )

Fills each SDIO_InitStruct member with its default value.

Parameters:
SDIO_InitStruct,: pointer to an SDIO_InitTypeDef structure which will be initialized.
Return values:
None

Definition at line 219 of file stm32f10x_sdio.c.

References SDIO_InitTypeDef::SDIO_BusWide, SDIO_BusWide_1b, SDIO_InitTypeDef::SDIO_ClockBypass, SDIO_ClockBypass_Disable, SDIO_InitTypeDef::SDIO_ClockDiv, SDIO_InitTypeDef::SDIO_ClockEdge, SDIO_ClockEdge_Rising, SDIO_InitTypeDef::SDIO_ClockPowerSave, SDIO_ClockPowerSave_Disable, SDIO_InitTypeDef::SDIO_HardwareFlowControl, and SDIO_HardwareFlowControl_Disable.

void SDIO_WriteData ( uint32_t Data )

Write one data word to Tx FIFO.

Parameters:
Data,: 32-bit data word to write.
Return values:
None

Definition at line 508 of file stm32f10x_sdio.c.

References Data, and SDIO.

Referenced by SD_WriteBlock().


STM32F10x Standard Peripherals Firmware Library: I2S_InitTypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

I2S_InitTypeDef Struct Reference
SPI_Exported_Types

I2S Init structure definition. More...

#include <stm32f10x_spi.h>

Data Fields

uint32_t | I2S_AudioFreq
uint16_t | I2S_CPOL
uint16_t | I2S_DataFormat
uint16_t | I2S_MCLKOutput
uint16_t | I2S_Mode
uint16_t | I2S_Standard

Detailed Description

I2S Init structure definition.

Definition at line 87 of file stm32f10x_spi.h.

Field Documentation

uint32_t I2S_InitTypeDef::I2S_AudioFreq

Specifies the frequency selected for the I2S communication. This parameter can be a value of I2S_Audio_Frequency

Definition at line 102 of file stm32f10x_spi.h.

Referenced by I2S_Init(), I2S_StructInit(), and main().

uint16_t I2S_InitTypeDef::I2S_CPOL

Specifies the idle state of the I2S clock. This parameter can be a value of I2S_Clock_Polarity

Definition at line 105 of file stm32f10x_spi.h.

Referenced by I2S_Init(), I2S_StructInit(), and main().

uint16_t I2S_InitTypeDef::I2S_DataFormat

Specifies the data format for the I2S communication. This parameter can be a value of I2S_Data_Format

Definition at line 96 of file stm32f10x_spi.h.

Referenced by I2S_Init(), I2S_StructInit(), and main().

uint16_t I2S_InitTypeDef::I2S_MCLKOutput

Specifies whether the I2S MCLK output is enabled or not. This parameter can be a value of I2S_MCLK_Output

Definition at line 99 of file stm32f10x_spi.h.

Referenced by I2S_Init(), I2S_StructInit(), and main().

uint16_t I2S_InitTypeDef::I2S_Mode

Specifies the I2S operating mode. This parameter can be a value of I2S_Mode

Definition at line 90 of file stm32f10x_spi.h.

Referenced by I2S_Init(), I2S_StructInit(), and main().

uint16_t I2S_InitTypeDef::I2S_Standard

Specifies the standard used for the I2S communication. This parameter can be a value of I2S_Standard

Definition at line 93 of file stm32f10x_spi.h.

Referenced by I2S_Init(), I2S_StructInit(), and main().

The documentation for this struct was generated from the following file:
  • stm32f10x_spi.h


STM32F10x Standard Peripherals Firmware Library: SPI_InitTypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

SPI_InitTypeDef Struct Reference
SPI_Exported_Types

SPI Init structure definition. More...

#include <stm32f10x_spi.h>

Data Fields

uint16_t | SPI_BaudRatePrescaler
uint16_t | SPI_CPHA
uint16_t | SPI_CPOL
uint16_t | SPI_CRCPolynomial
uint16_t | SPI_DataSize
uint16_t | SPI_Direction
uint16_t | SPI_FirstBit
uint16_t | SPI_Mode
uint16_t | SPI_NSS

Detailed Description

SPI Init structure definition.

Definition at line 50 of file stm32f10x_spi.h.

Field Documentation

uint16_t SPI_InitTypeDef::SPI_BaudRatePrescaler

Specifies the Baud Rate prescaler value which will be used to configure the transmit and receive SCK clock. This parameter can be a value of SPI_BaudRate_Prescaler.

Note:
The communication clock is derived from the master clock. The slave clock does not need to be set.

Definition at line 71 of file stm32f10x_spi.h.

Referenced by LCD_SPIConfig(), main(), SD_LowLevel_Init(), sFLASH_Init(), SPI_Init(), and SPI_StructInit().

uint16_t SPI_InitTypeDef::SPI_CPHA

Specifies the clock active edge for the bit capture. This parameter can be a value of SPI_Clock_Phase

Definition at line 64 of file stm32f10x_spi.h.

Referenced by LCD_SPIConfig(), main(), SD_LowLevel_Init(), sFLASH_Init(), SPI_Configuration(), SPI_Init(), and SPI_StructInit().

uint16_t SPI_InitTypeDef::SPI_CPOL

Specifies the serial clock steady state. This parameter can be a value of SPI_Clock_Polarity

Definition at line 61 of file stm32f10x_spi.h.

Referenced by LCD_SPIConfig(), main(), SD_LowLevel_Init(), sFLASH_Init(), SPI_Configuration(), SPI_Init(), and SPI_StructInit().

uint16_t SPI_InitTypeDef::SPI_CRCPolynomial

Specifies the polynomial used for the CRC calculation.

Definition at line 80 of file stm32f10x_spi.h.

Referenced by LCD_SPIConfig(), main(), SD_LowLevel_Init(), sFLASH_Init(), SPI_Init(), and SPI_StructInit().

uint16_t SPI_InitTypeDef::SPI_DataSize

Specifies the SPI data size. This parameter can be a value of SPI_data_size

Definition at line 58 of file stm32f10x_spi.h.

Referenced by LCD_SPIConfig(), main(), SD_LowLevel_Init(), sFLASH_Init(), SPI_Configuration(), SPI_Init(), and SPI_StructInit().

uint16_t SPI_InitTypeDef::SPI_Direction

Specifies the SPI unidirectional or bidirectional data mode. This parameter can be a value of SPI_data_direction

Definition at line 52 of file stm32f10x_spi.h.

Referenced by LCD_SPIConfig(), main(), SD_LowLevel_Init(), sFLASH_Init(), SPI_Configuration(), SPI_Init(), and SPI_StructInit().

uint16_t SPI_InitTypeDef::SPI_FirstBit

Specifies whether data transfers start from MSB or LSB bit. This parameter can be a value of SPI_MSB_LSB_transmission

Definition at line 77 of file stm32f10x_spi.h.

Referenced by LCD_SPIConfig(), main(), SD_LowLevel_Init(), sFLASH_Init(), SPI_Configuration(), SPI_Init(), and SPI_StructInit().

uint16_t SPI_InitTypeDef::SPI_Mode

Specifies the SPI operating mode. This parameter can be a value of SPI_mode

Definition at line 55 of file stm32f10x_spi.h.

Referenced by LCD_SPIConfig(), main(), SD_LowLevel_Init(), sFLASH_Init(), SPI_Configuration(), SPI_Init(), and SPI_StructInit().

uint16_t SPI_InitTypeDef::SPI_NSS

Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit. This parameter can be a value of SPI_Slave_Select_management

Definition at line 67 of file stm32f10x_spi.h.

Referenced by LCD_SPIConfig(), main(), SD_LowLevel_Init(), sFLASH_Init(), SPI_Configuration(), SPI_Init(), and SPI_StructInit().

The documentation for this struct was generated from the following file:
  • stm32f10x_spi.h


STM32F10x Standard Peripherals Firmware Library: SPI_data_direction

Defines

SPI_data_direction

SPI_Exported_Constants

Defines

#define | IS_SPI_DIRECTION_MODE(MODE)
#define | SPI_Direction_1Line_Rx ((uint16_t)0x8000)
#define | SPI_Direction_1Line_Tx ((uint16_t)0xC000)
#define | SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)
#define | SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400)

Define Documentation

#define IS_SPI_DIRECTION_MODE ( MODE )
Value:
(((MODE) == SPI_Direction_2Lines_FullDuplex) || \
                                     ((MODE) == SPI_Direction_2Lines_RxOnly) || \
                                     ((MODE) == SPI_Direction_1Line_Rx) || \
                                     ((MODE) == SPI_Direction_1Line_Tx))

Definition at line 132 of file stm32f10x_spi.h.

Referenced by SPI_Init().

#define SPI_Direction_1Line_Rx ((uint16_t)0x8000)

Definition at line 130 of file stm32f10x_spi.h.

Referenced by main().

#define SPI_Direction_1Line_Tx ((uint16_t)0xC000)

Definition at line 131 of file stm32f10x_spi.h.

Referenced by main().

#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)

Definition at line 128 of file stm32f10x_spi.h.

Referenced by LCD_SPIConfig(), main(), SD_LowLevel_Init(), sFLASH_Init(), SPI_Configuration(), and SPI_StructInit().

#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400)

Definition at line 129 of file stm32f10x_spi.h.

Referenced by main().


STM32F10x Standard Peripherals Firmware Library: SPI_mode

Defines

SPI_mode

SPI_Exported_Constants

Defines

#define | IS_SPI_MODE(MODE)
#define | SPI_Mode_Master ((uint16_t)0x0104)
#define | SPI_Mode_Slave ((uint16_t)0x0000)

Define Documentation

#define IS_SPI_MODE ( MODE )
Value:
(((MODE) == SPI_Mode_Master) || \
                           ((MODE) == SPI_Mode_Slave))

Definition at line 146 of file stm32f10x_spi.h.

Referenced by SPI_Init().

#define SPI_Mode_Master ((uint16_t)0x0104)

Definition at line 144 of file stm32f10x_spi.h.

Referenced by GPIO_Configuration(), LCD_SPIConfig(), main(), SD_LowLevel_Init(), and sFLASH_Init().

#define SPI_Mode_Slave ((uint16_t)0x0000)

Definition at line 145 of file stm32f10x_spi.h.

Referenced by GPIO_Configuration(), main(), SPI_Configuration(), and SPI_StructInit().


STM32F10x Standard Peripherals Firmware Library: SPI_data_size

Defines

SPI_data_size

SPI_Exported_Constants

Defines

#define | IS_SPI_DATASIZE(DATASIZE)
#define | SPI_DataSize_16b ((uint16_t)0x0800)
#define | SPI_DataSize_8b ((uint16_t)0x0000)

Define Documentation

#define IS_SPI_DATASIZE ( DATASIZE )
Value:
(((DATASIZE) == SPI_DataSize_16b) || \
                                   ((DATASIZE) == SPI_DataSize_8b))

Definition at line 158 of file stm32f10x_spi.h.

Referenced by SPI_DataSizeConfig(), and SPI_Init().

#define SPI_DataSize_16b ((uint16_t)0x0800)

Definition at line 156 of file stm32f10x_spi.h.

Referenced by LCD_SPIConfig(), main(), and SPI_DataSizeConfig().

#define SPI_DataSize_8b ((uint16_t)0x0000)

Definition at line 157 of file stm32f10x_spi.h.

Referenced by LCD_SPIConfig(), main(), SD_LowLevel_Init(), sFLASH_Init(), SPI_Configuration(), and SPI_StructInit().


STM32F10x Standard Peripherals Firmware Library: SPI_Clock_Polarity

Defines

SPI_Clock_Polarity

SPI_Exported_Constants

Defines

#define | IS_SPI_CPOL(CPOL)
#define | SPI_CPOL_High ((uint16_t)0x0002)
#define | SPI_CPOL_Low ((uint16_t)0x0000)

Define Documentation

#define IS_SPI_CPOL ( CPOL )
Value:
(((CPOL) == SPI_CPOL_Low) || \
                           ((CPOL) == SPI_CPOL_High))

Definition at line 170 of file stm32f10x_spi.h.

Referenced by SPI_Init().

#define SPI_CPOL_High ((uint16_t)0x0002)

Definition at line 169 of file stm32f10x_spi.h.

Referenced by LCD_SPIConfig(), main(), SD_LowLevel_Init(), sFLASH_Init(), and SPI_Configuration().

#define SPI_CPOL_Low ((uint16_t)0x0000)

Definition at line 168 of file stm32f10x_spi.h.

Referenced by LCD_SPIConfig(), main(), and SPI_StructInit().


STM32F10x Standard Peripherals Firmware Library: SPI_Clock_Phase

Defines

SPI_Clock_Phase

SPI_Exported_Constants

Defines

#define | IS_SPI_CPHA(CPHA)
#define | SPI_CPHA_1Edge ((uint16_t)0x0000)
#define | SPI_CPHA_2Edge ((uint16_t)0x0001)

Define Documentation

#define IS_SPI_CPHA ( CPHA )
Value:
(((CPHA) == SPI_CPHA_1Edge) || \
                           ((CPHA) == SPI_CPHA_2Edge))

Definition at line 182 of file stm32f10x_spi.h.

Referenced by SPI_Init().

#define SPI_CPHA_1Edge ((uint16_t)0x0000)

Definition at line 180 of file stm32f10x_spi.h.

Referenced by LCD_SPIConfig(), main(), and SPI_StructInit().

#define SPI_CPHA_2Edge ((uint16_t)0x0001)

Definition at line 181 of file stm32f10x_spi.h.

Referenced by LCD_SPIConfig(), main(), SD_LowLevel_Init(), sFLASH_Init(), and SPI_Configuration().


STM32F10x Standard Peripherals Firmware Library: SPI_Slave_Select_management

Defines

SPI_Slave_Select_management

SPI_Exported_Constants

Defines

#define | IS_SPI_NSS(NSS)
#define | SPI_NSS_Hard ((uint16_t)0x0000)
#define | SPI_NSS_Soft ((uint16_t)0x0200)

Define Documentation

#define IS_SPI_NSS ( NSS )
Value:
(((NSS) == SPI_NSS_Soft) || \
                         ((NSS) == SPI_NSS_Hard))

Definition at line 194 of file stm32f10x_spi.h.

Referenced by SPI_Init().

#define SPI_NSS_Hard ((uint16_t)0x0000)

Definition at line 193 of file stm32f10x_spi.h.

Referenced by main(), and SPI_StructInit().

#define SPI_NSS_Soft ((uint16_t)0x0200)

Definition at line 192 of file stm32f10x_spi.h.

Referenced by LCD_SPIConfig(), main(), SD_LowLevel_Init(), sFLASH_Init(), and SPI_Configuration().


STM32F10x Standard Peripherals Firmware Library: SPI_BaudRate_Prescaler

Defines

SPI_BaudRate_Prescaler

SPI_Exported_Constants

Defines

#define | IS_SPI_BAUDRATE_PRESCALER(PRESCALER)
#define | SPI_BaudRatePrescaler_128 ((uint16_t)0x0030)
#define | SPI_BaudRatePrescaler_16 ((uint16_t)0x0018)
#define | SPI_BaudRatePrescaler_2 ((uint16_t)0x0000)
#define | SPI_BaudRatePrescaler_256 ((uint16_t)0x0038)
#define | SPI_BaudRatePrescaler_32 ((uint16_t)0x0020)
#define | SPI_BaudRatePrescaler_4 ((uint16_t)0x0008)
#define | SPI_BaudRatePrescaler_64 ((uint16_t)0x0028)
#define | SPI_BaudRatePrescaler_8 ((uint16_t)0x0010)

Define Documentation

#define IS_SPI_BAUDRATE_PRESCALER ( PRESCALER )
Value:
(((PRESCALER) == SPI_BaudRatePrescaler_2) || \
                                              ((PRESCALER) == SPI_BaudRatePrescaler_4) || \
                                              ((PRESCALER) == SPI_BaudRatePrescaler_8) || \
                                              ((PRESCALER) == SPI_BaudRatePrescaler_16) || \
                                              ((PRESCALER) == SPI_BaudRatePrescaler_32) || \
                                              ((PRESCALER) == SPI_BaudRatePrescaler_64) || \
                                              ((PRESCALER) == SPI_BaudRatePrescaler_128) || \
                                              ((PRESCALER) == SPI_BaudRatePrescaler_256))

Definition at line 212 of file stm32f10x_spi.h.

Referenced by SPI_Init().

#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030)

Definition at line 210 of file stm32f10x_spi.h.

#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018)

Definition at line 207 of file stm32f10x_spi.h.

#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000)

Definition at line 204 of file stm32f10x_spi.h.

Referenced by LCD_SPIConfig(), SD_LowLevel_Init(), sFLASH_Init(), and SPI_StructInit().

#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038)

Definition at line 211 of file stm32f10x_spi.h.

#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020)

Definition at line 208 of file stm32f10x_spi.h.

#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008)

Definition at line 205 of file stm32f10x_spi.h.

Referenced by main(), SD_LowLevel_Init(), and sFLASH_Init().

#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028)

Definition at line 209 of file stm32f10x_spi.h.

#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010)

Definition at line 206 of file stm32f10x_spi.h.

Referenced by main().


STM32F10x Standard Peripherals Firmware Library: SPI_MSB_LSB_transmission

Defines

SPI_MSB_LSB_transmission

SPI_Exported_Constants

Defines

#define | IS_SPI_FIRST_BIT(BIT)
#define | SPI_FirstBit_LSB ((uint16_t)0x0080)
#define | SPI_FirstBit_MSB ((uint16_t)0x0000)

Define Documentation

#define IS_SPI_FIRST_BIT ( BIT )
Value:
(((BIT) == SPI_FirstBit_MSB) || \
                               ((BIT) == SPI_FirstBit_LSB))

Definition at line 230 of file stm32f10x_spi.h.

Referenced by SPI_Init().

#define SPI_FirstBit_LSB ((uint16_t)0x0080)

Definition at line 229 of file stm32f10x_spi.h.

Referenced by main(), and SPI_Configuration().

#define SPI_FirstBit_MSB ((uint16_t)0x0000)

Definition at line 228 of file stm32f10x_spi.h.

Referenced by LCD_SPIConfig(), main(), SD_LowLevel_Init(), sFLASH_Init(), and SPI_StructInit().


STM32F10x Standard Peripherals Firmware Library: I2S_Mode

Defines

I2S_Mode

SPI_Exported_Constants

Defines

#define | I2S_Mode_MasterRx ((uint16_t)0x0300)
#define | I2S_Mode_MasterTx ((uint16_t)0x0200)
#define | I2S_Mode_SlaveRx ((uint16_t)0x0100)
#define | I2S_Mode_SlaveTx ((uint16_t)0x0000)
#define | IS_I2S_MODE(MODE)

Define Documentation

#define I2S_Mode_MasterRx ((uint16_t)0x0300)

Definition at line 243 of file stm32f10x_spi.h.

Referenced by main().

#define I2S_Mode_MasterTx ((uint16_t)0x0200)

Definition at line 242 of file stm32f10x_spi.h.

Referenced by main().

#define I2S_Mode_SlaveRx ((uint16_t)0x0100)

Definition at line 241 of file stm32f10x_spi.h.

Referenced by main().

#define I2S_Mode_SlaveTx ((uint16_t)0x0000)

Definition at line 240 of file stm32f10x_spi.h.

Referenced by I2S_StructInit(), and main().

#define IS_I2S_MODE ( MODE )
Value:
(((MODE) == I2S_Mode_SlaveTx) || \
                           ((MODE) == I2S_Mode_SlaveRx) || \
                           ((MODE) == I2S_Mode_MasterTx) || \
                           ((MODE) == I2S_Mode_MasterRx) )

Definition at line 244 of file stm32f10x_spi.h.

Referenced by I2S_Init().


STM32F10x Standard Peripherals Firmware Library: I2S_Standard

Defines

I2S_Standard

SPI_Exported_Constants

Defines

#define | I2S_Standard_LSB ((uint16_t)0x0020)
#define | I2S_Standard_MSB ((uint16_t)0x0010)
#define | I2S_Standard_PCMLong ((uint16_t)0x00B0)
#define | I2S_Standard_PCMShort ((uint16_t)0x0030)
#define | I2S_Standard_Phillips ((uint16_t)0x0000)
#define | IS_I2S_STANDARD(STANDARD)

Define Documentation

#define I2S_Standard_LSB ((uint16_t)0x0020)

Definition at line 258 of file stm32f10x_spi.h.

#define I2S_Standard_MSB ((uint16_t)0x0010)

Definition at line 257 of file stm32f10x_spi.h.

#define I2S_Standard_PCMLong ((uint16_t)0x00B0)

Definition at line 260 of file stm32f10x_spi.h.

#define I2S_Standard_PCMShort ((uint16_t)0x0030)

Definition at line 259 of file stm32f10x_spi.h.

#define I2S_Standard_Phillips ((uint16_t)0x0000)

Definition at line 256 of file stm32f10x_spi.h.

Referenced by I2S_StructInit(), and main().

#define IS_I2S_STANDARD ( STANDARD )
Value:
(((STANDARD) == I2S_Standard_Phillips) || \
                                   ((STANDARD) == I2S_Standard_MSB) || \
                                   ((STANDARD) == I2S_Standard_LSB) || \
                                   ((STANDARD) == I2S_Standard_PCMShort) || \
                                   ((STANDARD) == I2S_Standard_PCMLong))

Definition at line 261 of file stm32f10x_spi.h.

Referenced by I2S_Init().


STM32F10x Standard Peripherals Firmware Library: I2S_Data_Format

Defines

I2S_Data_Format

SPI_Exported_Constants

Defines

#define | I2S_DataFormat_16b ((uint16_t)0x0000)
#define | I2S_DataFormat_16bextended ((uint16_t)0x0001)
#define | I2S_DataFormat_24b ((uint16_t)0x0003)
#define | I2S_DataFormat_32b ((uint16_t)0x0005)
#define | IS_I2S_DATA_FORMAT(FORMAT)

Define Documentation

#define I2S_DataFormat_16b ((uint16_t)0x0000)

Definition at line 274 of file stm32f10x_spi.h.

Referenced by I2S_Init(), and I2S_StructInit().

#define I2S_DataFormat_16bextended ((uint16_t)0x0001)

Definition at line 275 of file stm32f10x_spi.h.

Referenced by main().

#define I2S_DataFormat_24b ((uint16_t)0x0003)

Definition at line 276 of file stm32f10x_spi.h.

Referenced by main().

#define I2S_DataFormat_32b ((uint16_t)0x0005)

Definition at line 277 of file stm32f10x_spi.h.

#define IS_I2S_DATA_FORMAT ( FORMAT )
Value:
(((FORMAT) == I2S_DataFormat_16b) || \
                                    ((FORMAT) == I2S_DataFormat_16bextended) || \
                                    ((FORMAT) == I2S_DataFormat_24b) || \
                                    ((FORMAT) == I2S_DataFormat_32b))

Definition at line 278 of file stm32f10x_spi.h.

Referenced by I2S_Init().


STM32F10x Standard Peripherals Firmware Library: I2S_MCLK_Output

Defines

I2S_MCLK_Output

SPI_Exported_Constants

Defines

#define | I2S_MCLKOutput_Disable ((uint16_t)0x0000)
#define | I2S_MCLKOutput_Enable ((uint16_t)0x0200)
#define | IS_I2S_MCLK_OUTPUT(OUTPUT)

Define Documentation

#define I2S_MCLKOutput_Disable ((uint16_t)0x0000)

Definition at line 291 of file stm32f10x_spi.h.

Referenced by I2S_StructInit(), and main().

#define I2S_MCLKOutput_Enable ((uint16_t)0x0200)

Definition at line 290 of file stm32f10x_spi.h.

Referenced by I2S_Init().

#define IS_I2S_MCLK_OUTPUT ( OUTPUT )
Value:
(((OUTPUT) == I2S_MCLKOutput_Enable) || \
                                    ((OUTPUT) == I2S_MCLKOutput_Disable))

Definition at line 292 of file stm32f10x_spi.h.

Referenced by I2S_Init().


STM32F10x Standard Peripherals Firmware Library: I2S_Audio_Frequency

Defines

I2S_Audio_Frequency

SPI_Exported_Constants

Defines

#define | I2S_AudioFreq_11k ((uint32_t)11025)
#define | I2S_AudioFreq_16k ((uint32_t)16000)
#define | I2S_AudioFreq_192k ((uint32_t)192000)
#define | I2S_AudioFreq_22k ((uint32_t)22050)
#define | I2S_AudioFreq_32k ((uint32_t)32000)
#define | I2S_AudioFreq_44k ((uint32_t)44100)
#define | I2S_AudioFreq_48k ((uint32_t)48000)
#define | I2S_AudioFreq_8k ((uint32_t)8000)
#define | I2S_AudioFreq_96k ((uint32_t)96000)
#define | I2S_AudioFreq_Default ((uint32_t)2)
#define | IS_I2S_AUDIO_FREQ(FREQ)

Define Documentation

#define I2S_AudioFreq_11k ((uint32_t)11025)

Definition at line 309 of file stm32f10x_spi.h.

#define I2S_AudioFreq_16k ((uint32_t)16000)

Definition at line 308 of file stm32f10x_spi.h.

Referenced by main().

#define I2S_AudioFreq_192k ((uint32_t)192000)

Definition at line 302 of file stm32f10x_spi.h.

#define I2S_AudioFreq_22k ((uint32_t)22050)

Definition at line 307 of file stm32f10x_spi.h.

#define I2S_AudioFreq_32k ((uint32_t)32000)

Definition at line 306 of file stm32f10x_spi.h.

#define I2S_AudioFreq_44k ((uint32_t)44100)

Definition at line 305 of file stm32f10x_spi.h.

#define I2S_AudioFreq_48k ((uint32_t)48000)

Definition at line 304 of file stm32f10x_spi.h.

Referenced by main().

#define I2S_AudioFreq_8k ((uint32_t)8000)

Definition at line 310 of file stm32f10x_spi.h.

#define I2S_AudioFreq_96k ((uint32_t)96000)

Definition at line 303 of file stm32f10x_spi.h.

#define I2S_AudioFreq_Default ((uint32_t)2)

Definition at line 311 of file stm32f10x_spi.h.

Referenced by I2S_Init(), and I2S_StructInit().

#define IS_I2S_AUDIO_FREQ ( FREQ )
Value:
((((FREQ) >= I2S_AudioFreq_8k) && \
                                  ((FREQ) <= I2S_AudioFreq_192k)) || \
                                 ((FREQ) == I2S_AudioFreq_Default))

Definition at line 313 of file stm32f10x_spi.h.

Referenced by I2S_Init().


STM32F10x Standard Peripherals Firmware Library: I2S_Clock_Polarity

Defines

I2S_Clock_Polarity

SPI_Exported_Constants

Defines

#define | I2S_CPOL_High ((uint16_t)0x0008)
#define | I2S_CPOL_Low ((uint16_t)0x0000)
#define | IS_I2S_CPOL(CPOL)

Define Documentation

#define I2S_CPOL_High ((uint16_t)0x0008)

Definition at line 325 of file stm32f10x_spi.h.

#define I2S_CPOL_Low ((uint16_t)0x0000)

Definition at line 324 of file stm32f10x_spi.h.

Referenced by I2S_StructInit(), and main().

#define IS_I2S_CPOL ( CPOL )
Value:
(((CPOL) == I2S_CPOL_Low) || \
                           ((CPOL) == I2S_CPOL_High))

Definition at line 326 of file stm32f10x_spi.h.

Referenced by I2S_Init().


STM32F10x Standard Peripherals Firmware Library: SPI_I2S_DMA_transfer_requests

Defines

SPI_I2S_DMA_transfer_requests

SPI_Exported_Constants

Defines

#define | IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00))
#define | SPI_I2S_DMAReq_Rx ((uint16_t)0x0001)
#define | SPI_I2S_DMAReq_Tx ((uint16_t)0x0002)

Define Documentation

#define IS_SPI_I2S_DMAREQ ( DMAREQ ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00))

Definition at line 338 of file stm32f10x_spi.h.

Referenced by SPI_I2S_DMACmd().

#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001)

Definition at line 337 of file stm32f10x_spi.h.

Referenced by main().

#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002)

Definition at line 336 of file stm32f10x_spi.h.

Referenced by main().


STM32F10x Standard Peripherals Firmware Library: SPI_NSS_internal_software_management

Defines

SPI_NSS_internal_software_management

SPI_Exported_Constants

Defines

#define | IS_SPI_NSS_INTERNAL(INTERNAL)
#define | SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF)
#define | SPI_NSSInternalSoft_Set ((uint16_t)0x0100)

Define Documentation

#define IS_SPI_NSS_INTERNAL ( INTERNAL )
Value:
(((INTERNAL) == SPI_NSSInternalSoft_Set) || \
                                       ((INTERNAL) == SPI_NSSInternalSoft_Reset))

Definition at line 349 of file stm32f10x_spi.h.

Referenced by SPI_NSSInternalSoftwareConfig().

#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF)

Definition at line 348 of file stm32f10x_spi.h.

Referenced by SPI_NSSInternalSoftwareConfig().

#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100)

Definition at line 347 of file stm32f10x_spi.h.

Referenced by SPI_NSSInternalSoftwareConfig().


STM32F10x Standard Peripherals Firmware Library: SPI_CRC_Transmit_Receive

Defines

SPI_CRC_Transmit_Receive

SPI_Exported_Constants

Defines

#define | IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx))
#define | SPI_CRC_Rx ((uint8_t)0x01)
#define | SPI_CRC_Tx ((uint8_t)0x00)

Define Documentation

#define IS_SPI_CRC ( CRC ) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx))

Definition at line 361 of file stm32f10x_spi.h.

Referenced by SPI_GetCRC().

#define SPI_CRC_Rx ((uint8_t)0x01)

Definition at line 360 of file stm32f10x_spi.h.

Referenced by SPI_GetCRC().

#define SPI_CRC_Tx ((uint8_t)0x00)

Definition at line 359 of file stm32f10x_spi.h.


STM32F10x Standard Peripherals Firmware Library: SPI_direction_transmit_receive

Defines

SPI_direction_transmit_receive

SPI_Exported_Constants

Defines

#define | IS_SPI_DIRECTION(DIRECTION)
#define | SPI_Direction_Rx ((uint16_t)0xBFFF)
#define | SPI_Direction_Tx ((uint16_t)0x4000)

Define Documentation

#define IS_SPI_DIRECTION ( DIRECTION )
Value:
(((DIRECTION) == SPI_Direction_Rx) || \
                                     ((DIRECTION) == SPI_Direction_Tx))

Definition at line 372 of file stm32f10x_spi.h.

Referenced by SPI_BiDirectionalLineConfig().

#define SPI_Direction_Rx ((uint16_t)0xBFFF)

Definition at line 370 of file stm32f10x_spi.h.

Referenced by SPI_BiDirectionalLineConfig().

#define SPI_Direction_Tx ((uint16_t)0x4000)

Definition at line 371 of file stm32f10x_spi.h.

Referenced by SPI_BiDirectionalLineConfig().


STM32F10x Standard Peripherals Firmware Library: SPI_I2S_interrupts_definition

Defines

SPI_I2S_interrupts_definition

SPI_Exported_Constants

Defines

#define | I2S_IT_UDR ((uint8_t)0x53)
#define | IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR))
#define | IS_SPI_I2S_CONFIG_IT(IT)
#define | IS_SPI_I2S_GET_IT(IT)
#define | SPI_I2S_IT_ERR ((uint8_t)0x50)
#define | SPI_I2S_IT_OVR ((uint8_t)0x56)
#define | SPI_I2S_IT_RXNE ((uint8_t)0x60)
#define | SPI_I2S_IT_TXE ((uint8_t)0x71)
#define | SPI_IT_CRCERR ((uint8_t)0x54)
#define | SPI_IT_MODF ((uint8_t)0x55)

Define Documentation

#define I2S_IT_UDR ((uint8_t)0x53)

Definition at line 391 of file stm32f10x_spi.h.

#define IS_SPI_I2S_CLEAR_IT ( IT ) (((IT) == SPI_IT_CRCERR))

Definition at line 392 of file stm32f10x_spi.h.

Referenced by SPI_I2S_ClearITPendingBit().

#define IS_SPI_I2S_CONFIG_IT ( IT )
Value:
(((IT) == SPI_I2S_IT_TXE) || \
                                 ((IT) == SPI_I2S_IT_RXNE) || \
                                 ((IT) == SPI_I2S_IT_ERR))

Definition at line 385 of file stm32f10x_spi.h.

Referenced by SPI_I2S_ITConfig().

#define IS_SPI_I2S_GET_IT ( IT )
Value:
(((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \
                               ((IT) == I2S_IT_UDR) || ((IT) == SPI_IT_CRCERR) || \
                               ((IT) == SPI_IT_MODF) || ((IT) == SPI_I2S_IT_OVR))

Definition at line 393 of file stm32f10x_spi.h.

Referenced by SPI_I2S_GetITStatus().

#define SPI_I2S_IT_ERR ((uint8_t)0x50)

Definition at line 384 of file stm32f10x_spi.h.

#define SPI_I2S_IT_OVR ((uint8_t)0x56)

Definition at line 388 of file stm32f10x_spi.h.

#define SPI_I2S_IT_RXNE ((uint8_t)0x60)

Definition at line 383 of file stm32f10x_spi.h.

Referenced by main(), and SPI2_IRQHandler().

#define SPI_I2S_IT_TXE ((uint8_t)0x71)

Definition at line 382 of file stm32f10x_spi.h.

Referenced by main(), SPI1_IRQHandler(), and SPI3_IRQHandler().

#define SPI_IT_CRCERR ((uint8_t)0x54)

Definition at line 390 of file stm32f10x_spi.h.

#define SPI_IT_MODF ((uint8_t)0x55)

Definition at line 389 of file stm32f10x_spi.h.


STM32F10x Standard Peripherals Firmware Library: SPI_I2S_flags_definition

Defines

SPI_I2S_flags_definition

SPI_Exported_Constants

Defines

#define | I2S_FLAG_CHSIDE ((uint16_t)0x0004)
#define | I2S_FLAG_UDR ((uint16_t)0x0008)
#define | IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR))
#define | IS_SPI_I2S_GET_FLAG(FLAG)
#define | SPI_FLAG_CRCERR ((uint16_t)0x0010)
#define | SPI_FLAG_MODF ((uint16_t)0x0020)
#define | SPI_I2S_FLAG_BSY ((uint16_t)0x0080)
#define | SPI_I2S_FLAG_OVR ((uint16_t)0x0040)
#define | SPI_I2S_FLAG_RXNE ((uint16_t)0x0001)
#define | SPI_I2S_FLAG_TXE ((uint16_t)0x0002)

Define Documentation

#define I2S_FLAG_CHSIDE ((uint16_t)0x0004)

Definition at line 406 of file stm32f10x_spi.h.

#define I2S_FLAG_UDR ((uint16_t)0x0008)

Definition at line 407 of file stm32f10x_spi.h.

#define IS_SPI_I2S_CLEAR_FLAG ( FLAG ) (((FLAG) == SPI_FLAG_CRCERR))

Definition at line 412 of file stm32f10x_spi.h.

Referenced by SPI_I2S_ClearFlag().

#define IS_SPI_I2S_GET_FLAG ( FLAG )
Value:
(((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \
                                   ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \
                                   ((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) || \
                                   ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE))

Definition at line 413 of file stm32f10x_spi.h.

Referenced by SPI_I2S_GetFlagStatus().

#define SPI_FLAG_CRCERR ((uint16_t)0x0010)

Definition at line 408 of file stm32f10x_spi.h.

Referenced by main().

#define SPI_FLAG_MODF ((uint16_t)0x0020)

Definition at line 409 of file stm32f10x_spi.h.

#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080)

Definition at line 411 of file stm32f10x_spi.h.

Referenced by LCD_nCS_StartByte(), LCD_ReadReg(), LCD_WriteRAM(), LCD_WriteReg(), LCD_WriteRegHX8312(), LCD_WriteRegILI9320(), and LCD_WriteRegIndex().

#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040)

Definition at line 410 of file stm32f10x_spi.h.

#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001)

Definition at line 404 of file stm32f10x_spi.h.

Referenced by LCD_ReadReg(), main(), SD_ReadByte(), SD_WriteByte(), sFLASH_SendByte(), and sFLASH_SendHalfWord().

#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002)

Definition at line 405 of file stm32f10x_spi.h.

Referenced by main(), SD_ReadByte(), SD_WriteByte(), sFLASH_SendByte(), and sFLASH_SendHalfWord().


STM32F10x Standard Peripherals Firmware Library: SPI_CRC_polynomial

Defines

SPI_CRC_polynomial

SPI_Exported_Constants

Defines

#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1)

Define Documentation

#define IS_SPI_CRC_POLYNOMIAL ( POLYNOMIAL ) ((POLYNOMIAL) >= 0x1)

Definition at line 425 of file stm32f10x_spi.h.

Referenced by SPI_Init().


STM32F10x Standard Peripherals Firmware Library: SPI_Exported_Constants

Modules | Defines

SPI_Exported_Constants

SPI

Modules

SPI_data_direction
SPI_mode
SPI_data_size
SPI_Clock_Polarity
SPI_Clock_Phase
SPI_Slave_Select_management
SPI_BaudRate_Prescaler
SPI_MSB_LSB_transmission
I2S_Mode
I2S_Standard
I2S_Data_Format
I2S_MCLK_Output
I2S_Audio_Frequency
I2S_Clock_Polarity
SPI_I2S_DMA_transfer_requests
SPI_NSS_internal_software_management
SPI_CRC_Transmit_Receive
SPI_direction_transmit_receive
SPI_I2S_interrupts_definition
SPI_I2S_flags_definition
SPI_CRC_polynomial

Defines

#define | IS_SPI_23_PERIPH(PERIPH)
#define | IS_SPI_ALL_PERIPH(PERIPH)

Define Documentation

#define IS_SPI_23_PERIPH ( PERIPH )
Value:
(((PERIPH) == SPI2) || \
                                  ((PERIPH) == SPI3))

Definition at line 121 of file stm32f10x_spi.h.

Referenced by I2S_Cmd(), and I2S_Init().

#define IS_SPI_ALL_PERIPH ( PERIPH )
Value:
(((PERIPH) == SPI1) || \
                                   ((PERIPH) == SPI2) || \
                                   ((PERIPH) == SPI3))

Definition at line 117 of file stm32f10x_spi.h.

Referenced by SPI_BiDirectionalLineConfig(), SPI_CalculateCRC(), SPI_Cmd(), SPI_DataSizeConfig(), SPI_GetCRC(), SPI_GetCRCPolynomial(), SPI_I2S_ClearFlag(), SPI_I2S_ClearITPendingBit(), SPI_I2S_DeInit(), SPI_I2S_DMACmd(), SPI_I2S_GetFlagStatus(), SPI_I2S_GetITStatus(), SPI_I2S_ITConfig(), SPI_I2S_ReceiveData(), SPI_I2S_SendData(), SPI_Init(), SPI_NSSInternalSoftwareConfig(), SPI_SSOutputCmd(), and SPI_TransmitCRC().


STM32F10x Standard Peripherals Firmware Library: SPI_Exported_Macros

SPI_Exported_Macros

SPI


STM32F10x Standard Peripherals Firmware Library: SPI_Exported_Functions

Functions

SPI_Exported_Functions

SPI

Functions

void | I2S_Cmd (SPI_TypeDef *SPIx, FunctionalState NewState)
Enables or disables the specified SPI peripheral (in I2S mode).
void | I2S_Init (SPI_TypeDef *SPIx, I2S_InitTypeDef *I2S_InitStruct)
Initializes the SPIx peripheral according to the specified parameters in the I2S_InitStruct.
void | I2S_StructInit (I2S_InitTypeDef *I2S_InitStruct)
Fills each I2S_InitStruct member with its default value.
void | SPI_BiDirectionalLineConfig (SPI_TypeDef *SPIx, uint16_t SPI_Direction)
Selects the data transfer direction in bi-directional mode for the specified SPI.
void | SPI_CalculateCRC (SPI_TypeDef *SPIx, FunctionalState NewState)
Enables or disables the CRC value calculation of the transferred bytes.
void | SPI_Cmd (SPI_TypeDef *SPIx, FunctionalState NewState)
Enables or disables the specified SPI peripheral.
void | SPI_DataSizeConfig (SPI_TypeDef *SPIx, uint16_t SPI_DataSize)
Configures the data size for the selected SPI.
uint16_t | SPI_GetCRC (SPI_TypeDef *SPIx, uint8_t SPI_CRC)
Returns the transmit or the receive CRC register value for the specified SPI.
uint16_t | SPI_GetCRCPolynomial (SPI_TypeDef *SPIx)
Returns the CRC Polynomial register value for the specified SPI.
void | SPI_I2S_ClearFlag (SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG)
Clears the SPIx CRC Error (CRCERR) flag.
void | SPI_I2S_ClearITPendingBit (SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT)
Clears the SPIx CRC Error (CRCERR) interrupt pending bit.
void | SPI_I2S_DeInit (SPI_TypeDef *SPIx)
Deinitializes the SPIx peripheral registers to their default reset values (Affects also the I2Ss).
void | SPI_I2S_DMACmd (SPI_TypeDef *SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState)
Enables or disables the SPIx/I2Sx DMA interface.
FlagStatus | SPI_I2S_GetFlagStatus (SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG)
Checks whether the specified SPI/I2S flag is set or not.
ITStatus | SPI_I2S_GetITStatus (SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT)
Checks whether the specified SPI/I2S interrupt has occurred or not.
void | SPI_I2S_ITConfig (SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState)
Enables or disables the specified SPI/I2S interrupts.
uint16_t | SPI_I2S_ReceiveData (SPI_TypeDef *SPIx)
Returns the most recent received data by the SPIx/I2Sx peripheral.
void | SPI_I2S_SendData (SPI_TypeDef *SPIx, uint16_t Data)
Transmits a Data through the SPIx/I2Sx peripheral.
void | SPI_Init (SPI_TypeDef *SPIx, SPI_InitTypeDef *SPI_InitStruct)
Initializes the SPIx peripheral according to the specified parameters in the SPI_InitStruct.
void | SPI_NSSInternalSoftwareConfig (SPI_TypeDef *SPIx, uint16_t SPI_NSSInternalSoft)
Configures internally by software the NSS pin for the selected SPI.
void | SPI_SSOutputCmd (SPI_TypeDef *SPIx, FunctionalState NewState)
Enables or disables the SS output for the selected SPI.
void | SPI_StructInit (SPI_InitTypeDef *SPI_InitStruct)
Fills each SPI_InitStruct member with its default value.
void | SPI_TransmitCRC (SPI_TypeDef *SPIx)
Transmit the SPIx CRC value.

Function Documentation

void I2S_Cmd | ( | SPI_TypeDef * | SPIx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified SPI peripheral (in I2S mode).

Parameters:
SPIx,: where x can be 2 or 3 to select the SPI peripheral.
NewState,: new state of the SPIx peripheral. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 451 of file stm32f10x_spi.c.

References assert_param, DISABLE, SPI_TypeDef::I2SCFGR, I2SCFGR_I2SE_Reset, I2SCFGR_I2SE_Set, IS_FUNCTIONAL_STATE, and IS_SPI_23_PERIPH.

Referenced by main().

void I2S_Init | ( | SPI_TypeDef * | SPIx,
 |  | I2S_InitTypeDef * | I2S_InitStruct
 | ) |  |

Initializes the SPIx peripheral according to the specified parameters in the I2S_InitStruct.

Parameters:
SPIx,: where x can be 2 or 3 to select the SPI peripheral (configured in I2S mode).
I2S_InitStruct,: pointer to an I2S_InitTypeDef structure that contains the configuration information for the specified SPI peripheral configured in I2S mode.
Note:
The function calculates the optimal prescaler needed to obtain the most accurate audio frequency (depending on the I2S clock source, the PLL values and the product configuration). But in case the prescaler value is greater than 511, the default value (0x02) will be configured instead. *
Return values:
None

Definition at line 219 of file stm32f10x_spi.c.

References assert_param, HSE_Value, I2S2_CLOCK_SRC, I2S3_CLOCK_SRC, I2S_InitTypeDef::I2S_AudioFreq, I2S_AudioFreq_Default, I2S_InitTypeDef::I2S_CPOL, I2S_InitTypeDef::I2S_DataFormat, I2S_DataFormat_16b, I2S_DIV_MASK, I2S_InitTypeDef::I2S_MCLKOutput, I2S_MCLKOutput_Enable, I2S_InitTypeDef::I2S_Mode, I2S_Mode_Select, I2S_MUL_MASK, I2S_InitTypeDef::I2S_Standard, SPI_TypeDef::I2SCFGR, I2SCFGR_CLEAR_Mask, SPI_TypeDef::I2SPR, IS_I2S_AUDIO_FREQ, IS_I2S_CPOL, IS_I2S_DATA_FORMAT, IS_I2S_MCLK_OUTPUT, IS_I2S_MODE, IS_I2S_STANDARD, IS_SPI_23_PERIPH, RCC, RCC_Clocks, RCC_GetClocksFreq(), SPI2_BASE, and RCC_ClocksTypeDef::SYSCLK_Frequency.

Referenced by main().

void I2S_StructInit ( I2S_InitTypeDef * I2S_InitStruct )

Fills each I2S_InitStruct member with its default value.

Parameters:
I2S_InitStruct : pointer to a I2S_InitTypeDef structure which will be initialized.
Return values:
None

Definition at line 398 of file stm32f10x_spi.c.

References I2S_InitTypeDef::I2S_AudioFreq, I2S_AudioFreq_Default, I2S_InitTypeDef::I2S_CPOL, I2S_CPOL_Low, I2S_InitTypeDef::I2S_DataFormat, I2S_DataFormat_16b, I2S_InitTypeDef::I2S_MCLKOutput, I2S_MCLKOutput_Disable, I2S_InitTypeDef::I2S_Mode, I2S_Mode_SlaveTx, I2S_InitTypeDef::I2S_Standard, and I2S_Standard_Phillips.

void SPI_BiDirectionalLineConfig | ( | SPI_TypeDef * | SPIx,
 |  | uint16_t | SPI_Direction
 | ) |  |

Selects the data transfer direction in bi-directional mode for the specified SPI.

Parameters:
SPIx,: where x can be 1, 2 or 3 to select the SPI peripheral.
SPI_Direction,: specifies the data transfer direction in bi-directional mode. This parameter can be one of the following values:

  • SPI_Direction_Tx: Selects Tx transmission direction
  • SPI_Direction_Rx: Selects Rx receive direction
Return values:
None

Definition at line 732 of file stm32f10x_spi.c.

References assert_param, SPI_TypeDef::CR1, IS_SPI_ALL_PERIPH, IS_SPI_DIRECTION, SPI_Direction_Rx, and SPI_Direction_Tx.

void SPI_CalculateCRC | ( | SPI_TypeDef * | SPIx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the CRC value calculation of the transferred bytes.

Parameters:
SPIx,: where x can be 1, 2 or 3 to select the SPI peripheral.
NewState,: new state of the SPIx CRC value calculation. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 663 of file stm32f10x_spi.c.

References assert_param, SPI_TypeDef::CR1, CR1_CRCEN_Reset, CR1_CRCEN_Set, DISABLE, IS_FUNCTIONAL_STATE, and IS_SPI_ALL_PERIPH.

Referenced by main().

void SPI_Cmd | ( | SPI_TypeDef * | SPIx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified SPI peripheral.

Parameters:
SPIx,: where x can be 1, 2 or 3 to select the SPI peripheral.
NewState,: new state of the SPIx peripheral. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 427 of file stm32f10x_spi.c.

References assert_param, SPI_TypeDef::CR1, CR1_SPE_Reset, CR1_SPE_Set, DISABLE, IS_FUNCTIONAL_STATE, and IS_SPI_ALL_PERIPH.

Referenced by LCD_DeInit(), LCD_SPIConfig(), main(), SD_LowLevel_DeInit(), SD_LowLevel_Init(), sFLASH_Init(), sFLASH_LowLevel_DeInit(), SPI_Configuration(), and STM32L152_LCD_DeInit().

void SPI_DataSizeConfig | ( | SPI_TypeDef * | SPIx,
 |  | uint16_t | SPI_DataSize
 | ) |  |

Configures the data size for the selected SPI.

Parameters:
SPIx,: where x can be 1, 2 or 3 to select the SPI peripheral.
SPI_DataSize,: specifies the SPI data size. This parameter can be one of the following values:

  • SPI_DataSize_16b: Set data frame format to 16bit
  • SPI_DataSize_8b: Set data frame format to 8bit
Return values:
None

Definition at line 631 of file stm32f10x_spi.c.

References assert_param, SPI_TypeDef::CR1, IS_SPI_ALL_PERIPH, IS_SPI_DATASIZE, and SPI_DataSize_16b.

uint16_t SPI_GetCRC | ( | SPI_TypeDef * | SPIx,
 |  | uint8_t | SPI_CRC
 | ) |  |

Returns the transmit or the receive CRC register value for the specified SPI.

Parameters:
SPIx,: where x can be 1, 2 or 3 to select the SPI peripheral.
SPI_CRC,: specifies the CRC register to be read. This parameter can be one of the following values:

  • SPI_CRC_Tx: Selects Tx CRC register
  • SPI_CRC_Rx: Selects Rx CRC register
Return values:
The selected CRC register value..

Definition at line 689 of file stm32f10x_spi.c.

References assert_param, IS_SPI_ALL_PERIPH, IS_SPI_CRC, SPI_TypeDef::RXCRCR, SPI_CRC_Rx, and SPI_TypeDef::TXCRCR.

uint16_t SPI_GetCRCPolynomial ( SPI_TypeDef * SPIx )

Returns the CRC Polynomial register value for the specified SPI.

Parameters:
SPIx,: where x can be 1, 2 or 3 to select the SPI peripheral.
Return values:
The CRC Polynomial register value.

Definition at line 714 of file stm32f10x_spi.c.

References assert_param, SPI_TypeDef::CRCPR, and IS_SPI_ALL_PERIPH.

void SPI_I2S_ClearFlag | ( | SPI_TypeDef * | SPIx,
 |  | uint16_t | SPI_I2S_FLAG
 | ) |  |

Clears the SPIx CRC Error (CRCERR) flag.

Parameters:
SPIx,: where x can be

  • 1, 2 or 3 in SPI mode
SPI_I2S_FLAG,: specifies the SPI flag to clear. This function clears only CRCERR flag.
Note:
  • OVR (OverRun error) flag is cleared by software sequence: a read operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by a read operation to SPI_SR register (SPI_I2S_GetFlagStatus()).
  • UDR (UnderRun error) flag is cleared by a read operation to SPI_SR register (SPI_I2S_GetFlagStatus()).
  • MODF (Mode Fault) flag is cleared by software sequence: a read/write operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by a write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI).
Return values:
None

Definition at line 804 of file stm32f10x_spi.c.

References assert_param, IS_SPI_ALL_PERIPH, IS_SPI_I2S_CLEAR_FLAG, and SPI_TypeDef::SR.

void SPI_I2S_ClearITPendingBit | ( | SPI_TypeDef * | SPIx,
 |  | uint8_t | SPI_I2S_IT
 | ) |  |

Clears the SPIx CRC Error (CRCERR) interrupt pending bit.

Parameters:
SPIx,: where x can be

  • 1, 2 or 3 in SPI mode
SPI_I2S_IT,: specifies the SPI interrupt pending bit to clear. This function clears only CRCERR interrupt pending bit.
Note:
  • OVR (OverRun Error) interrupt pending bit is cleared by software sequence: a read operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by a read operation to SPI_SR register (SPI_I2S_GetITStatus()).
  • UDR (UnderRun Error) interrupt pending bit is cleared by a read operation to SPI_SR register (SPI_I2S_GetITStatus()).
  • MODF (Mode Fault) interrupt pending bit is cleared by software sequence: a read/write operation to SPI_SR register (SPI_I2S_GetITStatus()) followed by a write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI).
Return values:
None

Definition at line 883 of file stm32f10x_spi.c.

References assert_param, IS_SPI_ALL_PERIPH, IS_SPI_I2S_CLEAR_IT, and SPI_TypeDef::SR.

void SPI_I2S_DeInit ( SPI_TypeDef * SPIx )

Deinitializes the SPIx peripheral registers to their default reset values (Affects also the I2Ss).

Parameters:
SPIx,: where x can be 1, 2 or 3 to select the SPI peripheral.
Return values:
None

Definition at line 119 of file stm32f10x_spi.c.

References assert_param, DISABLE, ENABLE, IS_SPI_ALL_PERIPH, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3, RCC_APB1PeriphResetCmd(), RCC_APB2Periph_SPI1, RCC_APB2PeriphResetCmd(), SPI1, SPI2, and SPI3.

Referenced by LCD_DeInit(), LCD_SPIConfig(), main(), SD_LowLevel_DeInit(), sFLASH_LowLevel_DeInit(), and SPI_Configuration().

void SPI_I2S_DMACmd | ( | SPI_TypeDef * | SPIx,
 |  | uint16_t | SPI_I2S_DMAReq,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the SPIx/I2Sx DMA interface.

Parameters:
SPIx,: where x can be

  • 1, 2 or 3 in SPI mode
  • 2 or 3 in I2S mode
SPI_I2S_DMAReq,: specifies the SPI/I2S DMA transfer request to be enabled or disabled. This parameter can be any combination of the following values:

  • SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request
  • SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request
NewState,: new state of the selected SPI/I2S DMA transfer request. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 521 of file stm32f10x_spi.c.

References assert_param, SPI_TypeDef::CR2, DISABLE, IS_FUNCTIONAL_STATE, IS_SPI_ALL_PERIPH, and IS_SPI_I2S_DMAREQ.

Referenced by main().

FlagStatus SPI_I2S_GetFlagStatus | ( | SPI_TypeDef * | SPIx,
 |  | uint16_t | SPI_I2S_FLAG
 | ) |  |

Checks whether the specified SPI/I2S flag is set or not.

Parameters:
SPIx,: where x can be

  • 1, 2 or 3 in SPI mode
  • 2 or 3 in I2S mode
SPI_I2S_FLAG,: specifies the SPI/I2S flag to check. This parameter can be one of the following values:

  • SPI_I2S_FLAG_TXE: Transmit buffer empty flag.
  • SPI_I2S_FLAG_RXNE: Receive buffer not empty flag.
  • SPI_I2S_FLAG_BSY: Busy flag.
  • SPI_I2S_FLAG_OVR: Overrun flag.
  • SPI_FLAG_MODF: Mode Fault flag.
  • SPI_FLAG_CRCERR: CRC Error flag.
  • I2S_FLAG_UDR: Underrun Error flag.
  • I2S_FLAG_CHSIDE: Channel Side flag.
Return values:
The new state of SPI_I2S_FLAG (SET or RESET).

Definition at line 766 of file stm32f10x_spi.c.

References assert_param, IS_SPI_ALL_PERIPH, IS_SPI_I2S_GET_FLAG, RESET, SET, and SPI_TypeDef::SR.

Referenced by LCD_nCS_StartByte(), LCD_ReadReg(), LCD_WriteRAM(), LCD_WriteReg(), LCD_WriteRegHX8312(), LCD_WriteRegILI9320(), LCD_WriteRegIndex(), main(), SD_ReadByte(), SD_WriteByte(), sFLASH_SendByte(), and sFLASH_SendHalfWord().

ITStatus SPI_I2S_GetITStatus | ( | SPI_TypeDef * | SPIx,
 |  | uint8_t | SPI_I2S_IT
 | ) |  |

Checks whether the specified SPI/I2S interrupt has occurred or not.

Parameters:
SPIx,: where x can be

  • 1, 2 or 3 in SPI mode
  • 2 or 3 in I2S mode
SPI_I2S_IT,: specifies the SPI/I2S interrupt source to check. This parameter can be one of the following values:

  • SPI_I2S_IT_TXE: Transmit buffer empty interrupt.
  • SPI_I2S_IT_RXNE: Receive buffer not empty interrupt.
  • SPI_I2S_IT_OVR: Overrun interrupt.
  • SPI_IT_MODF: Mode Fault interrupt.
  • SPI_IT_CRCERR: CRC Error interrupt.
  • I2S_IT_UDR: Underrun Error interrupt.
Return values:
The new state of SPI_I2S_IT (SET or RESET).

Definition at line 829 of file stm32f10x_spi.c.

References assert_param, SPI_TypeDef::CR2, IS_SPI_ALL_PERIPH, IS_SPI_I2S_GET_IT, RESET, SET, and SPI_TypeDef::SR.

Referenced by SPI1_IRQHandler(), SPI2_IRQHandler(), and SPI3_IRQHandler().

void SPI_I2S_ITConfig | ( | SPI_TypeDef * | SPIx,
 |  | uint8_t | SPI_I2S_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified SPI/I2S interrupts.

Parameters:
SPIx,: where x can be

  • 1, 2 or 3 in SPI mode
  • 2 or 3 in I2S mode
SPI_I2S_IT,: specifies the SPI/I2S interrupt source to be enabled or disabled. This parameter can be one of the following values:

  • SPI_I2S_IT_TXE: Tx buffer empty interrupt mask
  • SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask
  • SPI_I2S_IT_ERR: Error interrupt mask
NewState,: new state of the specified SPI/I2S interrupt. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 482 of file stm32f10x_spi.c.

References assert_param, SPI_TypeDef::CR2, DISABLE, IS_FUNCTIONAL_STATE, IS_SPI_ALL_PERIPH, and IS_SPI_I2S_CONFIG_IT.

Referenced by main(), SPI1_IRQHandler(), and SPI3_IRQHandler().

uint16_t SPI_I2S_ReceiveData ( SPI_TypeDef * SPIx )

Returns the most recent received data by the SPIx/I2Sx peripheral.

Parameters:
SPIx,: where x can be

  • 1, 2 or 3 in SPI mode
  • 2 or 3 in I2S mode
Return values:
The value of the received data.

Definition at line 563 of file stm32f10x_spi.c.

References assert_param, SPI_TypeDef::DR, and IS_SPI_ALL_PERIPH.

Referenced by LCD_ReadReg(), main(), SD_ReadByte(), SD_WriteByte(), sFLASH_SendByte(), sFLASH_SendHalfWord(), and SPI2_IRQHandler().

void SPI_I2S_SendData | ( | SPI_TypeDef * | SPIx,
 |  | uint16_t | Data
 | ) |  |

Transmits a Data through the SPIx/I2Sx peripheral.

Parameters:
SPIx,: where x can be

  • 1, 2 or 3 in SPI mode
  • 2 or 3 in I2S mode
Data : Data to be transmitted.
Return values:
None

Definition at line 547 of file stm32f10x_spi.c.

References assert_param, Data, SPI_TypeDef::DR, and IS_SPI_ALL_PERIPH.

Referenced by LCD_nCS_StartByte(), LCD_ReadReg(), LCD_WriteRAM(), LCD_WriteReg(), LCD_WriteRegHX8312(), LCD_WriteRegILI9320(), LCD_WriteRegIndex(), main(), SD_ReadByte(), SD_WriteByte(), sFLASH_SendByte(), sFLASH_SendHalfWord(), SPI1_IRQHandler(), and SPI3_IRQHandler().

void SPI_Init | ( | SPI_TypeDef * | SPIx,
 |  | SPI_InitTypeDef * | SPI_InitStruct
 | ) |  |

Initializes the SPIx peripheral according to the specified parameters in the SPI_InitStruct.

Parameters:
SPIx,: where x can be 1, 2 or 3 to select the SPI peripheral.
SPI_InitStruct,: pointer to a SPI_InitTypeDef structure that contains the configuration information for the specified SPI peripheral.
Return values:
None

Definition at line 158 of file stm32f10x_spi.c.

References assert_param, SPI_TypeDef::CR1, CR1_CLEAR_Mask, SPI_TypeDef::CRCPR, SPI_TypeDef::I2SCFGR, IS_SPI_ALL_PERIPH, IS_SPI_BAUDRATE_PRESCALER, IS_SPI_CPHA, IS_SPI_CPOL, IS_SPI_CRC_POLYNOMIAL, IS_SPI_DATASIZE, IS_SPI_DIRECTION_MODE, IS_SPI_FIRST_BIT, IS_SPI_MODE, IS_SPI_NSS, SPI_InitTypeDef::SPI_BaudRatePrescaler, SPI_InitTypeDef::SPI_CPHA, SPI_InitTypeDef::SPI_CPOL, SPI_InitTypeDef::SPI_CRCPolynomial, SPI_InitTypeDef::SPI_DataSize, SPI_InitTypeDef::SPI_Direction, SPI_InitTypeDef::SPI_FirstBit, SPI_InitTypeDef::SPI_Mode, SPI_Mode_Select, and SPI_InitTypeDef::SPI_NSS.

Referenced by LCD_SPIConfig(), main(), SD_LowLevel_Init(), sFLASH_Init(), and SPI_Configuration().

void SPI_NSSInternalSoftwareConfig | ( | SPI_TypeDef * | SPIx,
 |  | uint16_t | SPI_NSSInternalSoft
 | ) |  |

Configures internally by software the NSS pin for the selected SPI.

Parameters:
SPIx,: where x can be 1, 2 or 3 to select the SPI peripheral.
SPI_NSSInternalSoft,: specifies the SPI NSS internal state. This parameter can be one of the following values:

  • SPI_NSSInternalSoft_Set: Set NSS pin internally
  • SPI_NSSInternalSoft_Reset: Reset NSS pin internally
Return values:
None

Definition at line 581 of file stm32f10x_spi.c.

References assert_param, SPI_TypeDef::CR1, IS_SPI_ALL_PERIPH, IS_SPI_NSS_INTERNAL, SPI_NSSInternalSoft_Reset, and SPI_NSSInternalSoft_Set.

void SPI_SSOutputCmd | ( | SPI_TypeDef * | SPIx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the SS output for the selected SPI.

Parameters:
SPIx,: where x can be 1, 2 or 3 to select the SPI peripheral.
NewState,: new state of the SPIx SS output. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 605 of file stm32f10x_spi.c.

References assert_param, SPI_TypeDef::CR2, CR2_SSOE_Reset, CR2_SSOE_Set, DISABLE, IS_FUNCTIONAL_STATE, and IS_SPI_ALL_PERIPH.

Referenced by main().

void SPI_StructInit ( SPI_InitTypeDef * SPI_InitStruct )

Fills each SPI_InitStruct member with its default value.

Parameters:
SPI_InitStruct : pointer to a SPI_InitTypeDef structure which will be initialized.
Return values:
None

Definition at line 370 of file stm32f10x_spi.c.

References SPI_InitTypeDef::SPI_BaudRatePrescaler, SPI_BaudRatePrescaler_2, SPI_InitTypeDef::SPI_CPHA, SPI_CPHA_1Edge, SPI_InitTypeDef::SPI_CPOL, SPI_CPOL_Low, SPI_InitTypeDef::SPI_CRCPolynomial, SPI_InitTypeDef::SPI_DataSize, SPI_DataSize_8b, SPI_InitTypeDef::SPI_Direction, SPI_Direction_2Lines_FullDuplex, SPI_InitTypeDef::SPI_FirstBit, SPI_FirstBit_MSB, SPI_InitTypeDef::SPI_Mode, SPI_Mode_Slave, SPI_InitTypeDef::SPI_NSS, and SPI_NSS_Hard.

Referenced by SPI_Configuration().

void SPI_TransmitCRC ( SPI_TypeDef * SPIx )

Transmit the SPIx CRC value.

Parameters:
SPIx,: where x can be 1, 2 or 3 to select the SPI peripheral.
Return values:
None

Definition at line 647 of file stm32f10x_spi.c.

References assert_param, SPI_TypeDef::CR1, CR1_CRCNext_Set, and IS_SPI_ALL_PERIPH.

Referenced by main().


STM32F10x Standard Peripherals Firmware Library: SPI_Private_TypesDefinitions

SPI_Private_TypesDefinitions

SPI


STM32F10x Standard Peripherals Firmware Library: SPI_Private_Defines

Defines

SPI_Private_Defines

SPI

Defines

#define | CR1_CLEAR_Mask ((uint16_t)0x3040)
#define | CR1_CRCEN_Reset ((uint16_t)0xDFFF)
#define | CR1_CRCEN_Set ((uint16_t)0x2000)
#define | CR1_CRCNext_Set ((uint16_t)0x1000)
#define | CR1_SPE_Reset ((uint16_t)0xFFBF)
#define | CR1_SPE_Set ((uint16_t)0x0040)
#define | CR2_SSOE_Reset ((uint16_t)0xFFFB)
#define | CR2_SSOE_Set ((uint16_t)0x0004)
#define | I2S2_CLOCK_SRC ((uint32_t)(0x00020000))
#define | I2S3_CLOCK_SRC ((uint32_t)(0x00040000))
#define | I2S_DIV_MASK ((uint32_t)(0x000000F0))
#define | I2S_Mode_Select ((uint16_t)0x0800)
#define | I2S_MUL_MASK ((uint32_t)(0x0000F000))
#define | I2SCFGR_CLEAR_Mask ((uint16_t)0xF040)
#define | I2SCFGR_I2SE_Reset ((uint16_t)0xFBFF)
#define | I2SCFGR_I2SE_Set ((uint16_t)0x0400)
#define | SPI_Mode_Select ((uint16_t)0xF7FF)

Define Documentation

#define CR1_CLEAR_Mask ((uint16_t)0x3040)

Definition at line 68 of file stm32f10x_spi.c.

Referenced by SPI_Init().

#define CR1_CRCEN_Reset ((uint16_t)0xDFFF)

Definition at line 61 of file stm32f10x_spi.c.

Referenced by SPI_CalculateCRC().

#define CR1_CRCEN_Set ((uint16_t)0x2000)

Definition at line 60 of file stm32f10x_spi.c.

Referenced by SPI_CalculateCRC().

#define CR1_CRCNext_Set ((uint16_t)0x1000)

Definition at line 57 of file stm32f10x_spi.c.

Referenced by SPI_TransmitCRC().

#define CR1_SPE_Reset ((uint16_t)0xFFBF)

Definition at line 50 of file stm32f10x_spi.c.

Referenced by SPI_Cmd().

#define CR1_SPE_Set ((uint16_t)0x0040)

Definition at line 49 of file stm32f10x_spi.c.

Referenced by SPI_Cmd().

#define CR2_SSOE_Reset ((uint16_t)0xFFFB)

Definition at line 65 of file stm32f10x_spi.c.

Referenced by SPI_SSOutputCmd().

#define CR2_SSOE_Set ((uint16_t)0x0004)

Definition at line 64 of file stm32f10x_spi.c.

Referenced by SPI_SSOutputCmd().

#define I2S2_CLOCK_SRC ((uint32_t)(0x00020000))

Definition at line 76 of file stm32f10x_spi.c.

Referenced by I2S_Init().

#define I2S3_CLOCK_SRC ((uint32_t)(0x00040000))

Definition at line 77 of file stm32f10x_spi.c.

Referenced by I2S_Init().

#define I2S_DIV_MASK ((uint32_t)(0x000000F0))

Definition at line 79 of file stm32f10x_spi.c.

Referenced by I2S_Init().

#define I2S_Mode_Select ((uint16_t)0x0800)

Definition at line 73 of file stm32f10x_spi.c.

Referenced by I2S_Init().

#define I2S_MUL_MASK ((uint32_t)(0x0000F000))

Definition at line 78 of file stm32f10x_spi.c.

Referenced by I2S_Init().

#define I2SCFGR_CLEAR_Mask ((uint16_t)0xF040)

Definition at line 69 of file stm32f10x_spi.c.

Referenced by I2S_Init().

#define I2SCFGR_I2SE_Reset ((uint16_t)0xFBFF)

Definition at line 54 of file stm32f10x_spi.c.

Referenced by I2S_Cmd().

#define I2SCFGR_I2SE_Set ((uint16_t)0x0400)

Definition at line 53 of file stm32f10x_spi.c.

Referenced by I2S_Cmd().

#define SPI_Mode_Select ((uint16_t)0xF7FF)

Definition at line 72 of file stm32f10x_spi.c.

Referenced by SPI_Init().


STM32F10x Standard Peripherals Firmware Library: SPI_Private_Macros

SPI_Private_Macros

SPI


STM32F10x Standard Peripherals Firmware Library: SPI_Private_Variables

SPI_Private_Variables

SPI


STM32F10x Standard Peripherals Firmware Library: SPI_Private_FunctionPrototypes

SPI_Private_FunctionPrototypes

SPI


STM32F10x Standard Peripherals Firmware Library: SPI_Private_Functions

Functions

SPI_Private_Functions

SPI

Functions

void | I2S_Cmd (SPI_TypeDef *SPIx, FunctionalState NewState)
Enables or disables the specified SPI peripheral (in I2S mode).
void | I2S_Init (SPI_TypeDef *SPIx, I2S_InitTypeDef *I2S_InitStruct)
Initializes the SPIx peripheral according to the specified parameters in the I2S_InitStruct.
void | I2S_StructInit (I2S_InitTypeDef *I2S_InitStruct)
Fills each I2S_InitStruct member with its default value.
void | SPI_BiDirectionalLineConfig (SPI_TypeDef *SPIx, uint16_t SPI_Direction)
Selects the data transfer direction in bi-directional mode for the specified SPI.
void | SPI_CalculateCRC (SPI_TypeDef *SPIx, FunctionalState NewState)
Enables or disables the CRC value calculation of the transferred bytes.
void | SPI_Cmd (SPI_TypeDef *SPIx, FunctionalState NewState)
Enables or disables the specified SPI peripheral.
void | SPI_DataSizeConfig (SPI_TypeDef *SPIx, uint16_t SPI_DataSize)
Configures the data size for the selected SPI.
uint16_t | SPI_GetCRC (SPI_TypeDef *SPIx, uint8_t SPI_CRC)
Returns the transmit or the receive CRC register value for the specified SPI.
uint16_t | SPI_GetCRCPolynomial (SPI_TypeDef *SPIx)
Returns the CRC Polynomial register value for the specified SPI.
void | SPI_I2S_ClearFlag (SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG)
Clears the SPIx CRC Error (CRCERR) flag.
void | SPI_I2S_ClearITPendingBit (SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT)
Clears the SPIx CRC Error (CRCERR) interrupt pending bit.
void | SPI_I2S_DeInit (SPI_TypeDef *SPIx)
Deinitializes the SPIx peripheral registers to their default reset values (Affects also the I2Ss).
void | SPI_I2S_DMACmd (SPI_TypeDef *SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState)
Enables or disables the SPIx/I2Sx DMA interface.
FlagStatus | SPI_I2S_GetFlagStatus (SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG)
Checks whether the specified SPI/I2S flag is set or not.
ITStatus | SPI_I2S_GetITStatus (SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT)
Checks whether the specified SPI/I2S interrupt has occurred or not.
void | SPI_I2S_ITConfig (SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState)
Enables or disables the specified SPI/I2S interrupts.
uint16_t | SPI_I2S_ReceiveData (SPI_TypeDef *SPIx)
Returns the most recent received data by the SPIx/I2Sx peripheral.
void | SPI_I2S_SendData (SPI_TypeDef *SPIx, uint16_t Data)
Transmits a Data through the SPIx/I2Sx peripheral.
void | SPI_Init (SPI_TypeDef *SPIx, SPI_InitTypeDef *SPI_InitStruct)
Initializes the SPIx peripheral according to the specified parameters in the SPI_InitStruct.
void | SPI_NSSInternalSoftwareConfig (SPI_TypeDef *SPIx, uint16_t SPI_NSSInternalSoft)
Configures internally by software the NSS pin for the selected SPI.
void | SPI_SSOutputCmd (SPI_TypeDef *SPIx, FunctionalState NewState)
Enables or disables the SS output for the selected SPI.
void | SPI_StructInit (SPI_InitTypeDef *SPI_InitStruct)
Fills each SPI_InitStruct member with its default value.
void | SPI_TransmitCRC (SPI_TypeDef *SPIx)
Transmit the SPIx CRC value.

Function Documentation

void I2S_Cmd | ( | SPI_TypeDef * | SPIx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified SPI peripheral (in I2S mode).

Parameters:
SPIx,: where x can be 2 or 3 to select the SPI peripheral.
NewState,: new state of the SPIx peripheral. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 451 of file stm32f10x_spi.c.

References assert_param, DISABLE, SPI_TypeDef::I2SCFGR, I2SCFGR_I2SE_Reset, I2SCFGR_I2SE_Set, IS_FUNCTIONAL_STATE, and IS_SPI_23_PERIPH.

Referenced by main().

void I2S_Init | ( | SPI_TypeDef * | SPIx,
 |  | I2S_InitTypeDef * | I2S_InitStruct
 | ) |  |

Initializes the SPIx peripheral according to the specified parameters in the I2S_InitStruct.

Parameters:
SPIx,: where x can be 2 or 3 to select the SPI peripheral (configured in I2S mode).
I2S_InitStruct,: pointer to an I2S_InitTypeDef structure that contains the configuration information for the specified SPI peripheral configured in I2S mode.
Note:
The function calculates the optimal prescaler needed to obtain the most accurate audio frequency (depending on the I2S clock source, the PLL values and the product configuration). But in case the prescaler value is greater than 511, the default value (0x02) will be configured instead. *
Return values:
None

Definition at line 219 of file stm32f10x_spi.c.

References assert_param, HSE_Value, I2S2_CLOCK_SRC, I2S3_CLOCK_SRC, I2S_InitTypeDef::I2S_AudioFreq, I2S_AudioFreq_Default, I2S_InitTypeDef::I2S_CPOL, I2S_InitTypeDef::I2S_DataFormat, I2S_DataFormat_16b, I2S_DIV_MASK, I2S_InitTypeDef::I2S_MCLKOutput, I2S_MCLKOutput_Enable, I2S_InitTypeDef::I2S_Mode, I2S_Mode_Select, I2S_MUL_MASK, I2S_InitTypeDef::I2S_Standard, SPI_TypeDef::I2SCFGR, I2SCFGR_CLEAR_Mask, SPI_TypeDef::I2SPR, IS_I2S_AUDIO_FREQ, IS_I2S_CPOL, IS_I2S_DATA_FORMAT, IS_I2S_MCLK_OUTPUT, IS_I2S_MODE, IS_I2S_STANDARD, IS_SPI_23_PERIPH, RCC, RCC_Clocks, RCC_GetClocksFreq(), SPI2_BASE, and RCC_ClocksTypeDef::SYSCLK_Frequency.

Referenced by main().

void I2S_StructInit ( I2S_InitTypeDef * I2S_InitStruct )

Fills each I2S_InitStruct member with its default value.

Parameters:
I2S_InitStruct : pointer to a I2S_InitTypeDef structure which will be initialized.
Return values:
None

Definition at line 398 of file stm32f10x_spi.c.

References I2S_InitTypeDef::I2S_AudioFreq, I2S_AudioFreq_Default, I2S_InitTypeDef::I2S_CPOL, I2S_CPOL_Low, I2S_InitTypeDef::I2S_DataFormat, I2S_DataFormat_16b, I2S_InitTypeDef::I2S_MCLKOutput, I2S_MCLKOutput_Disable, I2S_InitTypeDef::I2S_Mode, I2S_Mode_SlaveTx, I2S_InitTypeDef::I2S_Standard, and I2S_Standard_Phillips.

void SPI_BiDirectionalLineConfig | ( | SPI_TypeDef * | SPIx,
 |  | uint16_t | SPI_Direction
 | ) |  |

Selects the data transfer direction in bi-directional mode for the specified SPI.

Parameters:
SPIx,: where x can be 1, 2 or 3 to select the SPI peripheral.
SPI_Direction,: specifies the data transfer direction in bi-directional mode. This parameter can be one of the following values:

  • SPI_Direction_Tx: Selects Tx transmission direction
  • SPI_Direction_Rx: Selects Rx receive direction
Return values:
None

Definition at line 732 of file stm32f10x_spi.c.

References assert_param, SPI_TypeDef::CR1, IS_SPI_ALL_PERIPH, IS_SPI_DIRECTION, SPI_Direction_Rx, and SPI_Direction_Tx.

void SPI_CalculateCRC | ( | SPI_TypeDef * | SPIx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the CRC value calculation of the transferred bytes.

Parameters:
SPIx,: where x can be 1, 2 or 3 to select the SPI peripheral.
NewState,: new state of the SPIx CRC value calculation. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 663 of file stm32f10x_spi.c.

References assert_param, SPI_TypeDef::CR1, CR1_CRCEN_Reset, CR1_CRCEN_Set, DISABLE, IS_FUNCTIONAL_STATE, and IS_SPI_ALL_PERIPH.

Referenced by main().

void SPI_Cmd | ( | SPI_TypeDef * | SPIx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified SPI peripheral.

Parameters:
SPIx,: where x can be 1, 2 or 3 to select the SPI peripheral.
NewState,: new state of the SPIx peripheral. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 427 of file stm32f10x_spi.c.

References assert_param, SPI_TypeDef::CR1, CR1_SPE_Reset, CR1_SPE_Set, DISABLE, IS_FUNCTIONAL_STATE, and IS_SPI_ALL_PERIPH.

Referenced by LCD_DeInit(), LCD_SPIConfig(), main(), SD_LowLevel_DeInit(), SD_LowLevel_Init(), sFLASH_Init(), sFLASH_LowLevel_DeInit(), SPI_Configuration(), and STM32L152_LCD_DeInit().

void SPI_DataSizeConfig | ( | SPI_TypeDef * | SPIx,
 |  | uint16_t | SPI_DataSize
 | ) |  |

Configures the data size for the selected SPI.

Parameters:
SPIx,: where x can be 1, 2 or 3 to select the SPI peripheral.
SPI_DataSize,: specifies the SPI data size. This parameter can be one of the following values:

  • SPI_DataSize_16b: Set data frame format to 16bit
  • SPI_DataSize_8b: Set data frame format to 8bit
Return values:
None

Definition at line 631 of file stm32f10x_spi.c.

References assert_param, SPI_TypeDef::CR1, IS_SPI_ALL_PERIPH, IS_SPI_DATASIZE, and SPI_DataSize_16b.

uint16_t SPI_GetCRC | ( | SPI_TypeDef * | SPIx,
 |  | uint8_t | SPI_CRC
 | ) |  |

Returns the transmit or the receive CRC register value for the specified SPI.

Parameters:
SPIx,: where x can be 1, 2 or 3 to select the SPI peripheral.
SPI_CRC,: specifies the CRC register to be read. This parameter can be one of the following values:

  • SPI_CRC_Tx: Selects Tx CRC register
  • SPI_CRC_Rx: Selects Rx CRC register
Return values:
The selected CRC register value..

Definition at line 689 of file stm32f10x_spi.c.

References assert_param, IS_SPI_ALL_PERIPH, IS_SPI_CRC, SPI_TypeDef::RXCRCR, SPI_CRC_Rx, and SPI_TypeDef::TXCRCR.

uint16_t SPI_GetCRCPolynomial ( SPI_TypeDef * SPIx )

Returns the CRC Polynomial register value for the specified SPI.

Parameters:
SPIx,: where x can be 1, 2 or 3 to select the SPI peripheral.
Return values:
The CRC Polynomial register value.

Definition at line 714 of file stm32f10x_spi.c.

References assert_param, SPI_TypeDef::CRCPR, and IS_SPI_ALL_PERIPH.

void SPI_I2S_ClearFlag | ( | SPI_TypeDef * | SPIx,
 |  | uint16_t | SPI_I2S_FLAG
 | ) |  |

Clears the SPIx CRC Error (CRCERR) flag.

Parameters:
SPIx,: where x can be

  • 1, 2 or 3 in SPI mode
SPI_I2S_FLAG,: specifies the SPI flag to clear. This function clears only CRCERR flag.
Note:
  • OVR (OverRun error) flag is cleared by software sequence: a read operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by a read operation to SPI_SR register (SPI_I2S_GetFlagStatus()).
  • UDR (UnderRun error) flag is cleared by a read operation to SPI_SR register (SPI_I2S_GetFlagStatus()).
  • MODF (Mode Fault) flag is cleared by software sequence: a read/write operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by a write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI).
Return values:
None

Definition at line 804 of file stm32f10x_spi.c.

References assert_param, IS_SPI_ALL_PERIPH, IS_SPI_I2S_CLEAR_FLAG, and SPI_TypeDef::SR.

void SPI_I2S_ClearITPendingBit | ( | SPI_TypeDef * | SPIx,
 |  | uint8_t | SPI_I2S_IT
 | ) |  |

Clears the SPIx CRC Error (CRCERR) interrupt pending bit.

Parameters:
SPIx,: where x can be

  • 1, 2 or 3 in SPI mode
SPI_I2S_IT,: specifies the SPI interrupt pending bit to clear. This function clears only CRCERR interrupt pending bit.
Note:
  • OVR (OverRun Error) interrupt pending bit is cleared by software sequence: a read operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by a read operation to SPI_SR register (SPI_I2S_GetITStatus()).
  • UDR (UnderRun Error) interrupt pending bit is cleared by a read operation to SPI_SR register (SPI_I2S_GetITStatus()).
  • MODF (Mode Fault) interrupt pending bit is cleared by software sequence: a read/write operation to SPI_SR register (SPI_I2S_GetITStatus()) followed by a write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI).
Return values:
None

Definition at line 883 of file stm32f10x_spi.c.

References assert_param, IS_SPI_ALL_PERIPH, IS_SPI_I2S_CLEAR_IT, and SPI_TypeDef::SR.

void SPI_I2S_DeInit ( SPI_TypeDef * SPIx )

Deinitializes the SPIx peripheral registers to their default reset values (Affects also the I2Ss).

Parameters:
SPIx,: where x can be 1, 2 or 3 to select the SPI peripheral.
Return values:
None

Definition at line 119 of file stm32f10x_spi.c.

References assert_param, DISABLE, ENABLE, IS_SPI_ALL_PERIPH, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3, RCC_APB1PeriphResetCmd(), RCC_APB2Periph_SPI1, RCC_APB2PeriphResetCmd(), SPI1, SPI2, and SPI3.

Referenced by LCD_DeInit(), LCD_SPIConfig(), main(), SD_LowLevel_DeInit(), sFLASH_LowLevel_DeInit(), and SPI_Configuration().

void SPI_I2S_DMACmd | ( | SPI_TypeDef * | SPIx,
 |  | uint16_t | SPI_I2S_DMAReq,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the SPIx/I2Sx DMA interface.

Parameters:
SPIx,: where x can be

  • 1, 2 or 3 in SPI mode
  • 2 or 3 in I2S mode
SPI_I2S_DMAReq,: specifies the SPI/I2S DMA transfer request to be enabled or disabled. This parameter can be any combination of the following values:

  • SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request
  • SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request
NewState,: new state of the selected SPI/I2S DMA transfer request. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 521 of file stm32f10x_spi.c.

References assert_param, SPI_TypeDef::CR2, DISABLE, IS_FUNCTIONAL_STATE, IS_SPI_ALL_PERIPH, and IS_SPI_I2S_DMAREQ.

Referenced by main().

FlagStatus SPI_I2S_GetFlagStatus | ( | SPI_TypeDef * | SPIx,
 |  | uint16_t | SPI_I2S_FLAG
 | ) |  |

Checks whether the specified SPI/I2S flag is set or not.

Parameters:
SPIx,: where x can be

  • 1, 2 or 3 in SPI mode
  • 2 or 3 in I2S mode
SPI_I2S_FLAG,: specifies the SPI/I2S flag to check. This parameter can be one of the following values:

  • SPI_I2S_FLAG_TXE: Transmit buffer empty flag.
  • SPI_I2S_FLAG_RXNE: Receive buffer not empty flag.
  • SPI_I2S_FLAG_BSY: Busy flag.
  • SPI_I2S_FLAG_OVR: Overrun flag.
  • SPI_FLAG_MODF: Mode Fault flag.
  • SPI_FLAG_CRCERR: CRC Error flag.
  • I2S_FLAG_UDR: Underrun Error flag.
  • I2S_FLAG_CHSIDE: Channel Side flag.
Return values:
The new state of SPI_I2S_FLAG (SET or RESET).

Definition at line 766 of file stm32f10x_spi.c.

References assert_param, IS_SPI_ALL_PERIPH, IS_SPI_I2S_GET_FLAG, RESET, SET, and SPI_TypeDef::SR.

Referenced by LCD_nCS_StartByte(), LCD_ReadReg(), LCD_WriteRAM(), LCD_WriteReg(), LCD_WriteRegHX8312(), LCD_WriteRegILI9320(), LCD_WriteRegIndex(), main(), SD_ReadByte(), SD_WriteByte(), sFLASH_SendByte(), and sFLASH_SendHalfWord().

ITStatus SPI_I2S_GetITStatus | ( | SPI_TypeDef * | SPIx,
 |  | uint8_t | SPI_I2S_IT
 | ) |  |

Checks whether the specified SPI/I2S interrupt has occurred or not.

Parameters:
SPIx,: where x can be

  • 1, 2 or 3 in SPI mode
  • 2 or 3 in I2S mode
SPI_I2S_IT,: specifies the SPI/I2S interrupt source to check. This parameter can be one of the following values:

  • SPI_I2S_IT_TXE: Transmit buffer empty interrupt.
  • SPI_I2S_IT_RXNE: Receive buffer not empty interrupt.
  • SPI_I2S_IT_OVR: Overrun interrupt.
  • SPI_IT_MODF: Mode Fault interrupt.
  • SPI_IT_CRCERR: CRC Error interrupt.
  • I2S_IT_UDR: Underrun Error interrupt.
Return values:
The new state of SPI_I2S_IT (SET or RESET).

Definition at line 829 of file stm32f10x_spi.c.

References assert_param, SPI_TypeDef::CR2, IS_SPI_ALL_PERIPH, IS_SPI_I2S_GET_IT, RESET, SET, and SPI_TypeDef::SR.

Referenced by SPI1_IRQHandler(), SPI2_IRQHandler(), and SPI3_IRQHandler().

void SPI_I2S_ITConfig | ( | SPI_TypeDef * | SPIx,
 |  | uint8_t | SPI_I2S_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified SPI/I2S interrupts.

Parameters:
SPIx,: where x can be

  • 1, 2 or 3 in SPI mode
  • 2 or 3 in I2S mode
SPI_I2S_IT,: specifies the SPI/I2S interrupt source to be enabled or disabled. This parameter can be one of the following values:

  • SPI_I2S_IT_TXE: Tx buffer empty interrupt mask
  • SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask
  • SPI_I2S_IT_ERR: Error interrupt mask
NewState,: new state of the specified SPI/I2S interrupt. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 482 of file stm32f10x_spi.c.

References assert_param, SPI_TypeDef::CR2, DISABLE, IS_FUNCTIONAL_STATE, IS_SPI_ALL_PERIPH, and IS_SPI_I2S_CONFIG_IT.

Referenced by main(), SPI1_IRQHandler(), and SPI3_IRQHandler().

uint16_t SPI_I2S_ReceiveData ( SPI_TypeDef * SPIx )

Returns the most recent received data by the SPIx/I2Sx peripheral.

Parameters:
SPIx,: where x can be

  • 1, 2 or 3 in SPI mode
  • 2 or 3 in I2S mode
Return values:
The value of the received data.

Definition at line 563 of file stm32f10x_spi.c.

References assert_param, SPI_TypeDef::DR, and IS_SPI_ALL_PERIPH.

Referenced by LCD_ReadReg(), main(), SD_ReadByte(), SD_WriteByte(), sFLASH_SendByte(), sFLASH_SendHalfWord(), and SPI2_IRQHandler().

void SPI_I2S_SendData | ( | SPI_TypeDef * | SPIx,
 |  | uint16_t | Data
 | ) |  |

Transmits a Data through the SPIx/I2Sx peripheral.

Parameters:
SPIx,: where x can be

  • 1, 2 or 3 in SPI mode
  • 2 or 3 in I2S mode
Data : Data to be transmitted.
Return values:
None

Definition at line 547 of file stm32f10x_spi.c.

References assert_param, Data, SPI_TypeDef::DR, and IS_SPI_ALL_PERIPH.

Referenced by LCD_nCS_StartByte(), LCD_ReadReg(), LCD_WriteRAM(), LCD_WriteReg(), LCD_WriteRegHX8312(), LCD_WriteRegILI9320(), LCD_WriteRegIndex(), main(), SD_ReadByte(), SD_WriteByte(), sFLASH_SendByte(), sFLASH_SendHalfWord(), SPI1_IRQHandler(), and SPI3_IRQHandler().

void SPI_Init | ( | SPI_TypeDef * | SPIx,
 |  | SPI_InitTypeDef * | SPI_InitStruct
 | ) |  |

Initializes the SPIx peripheral according to the specified parameters in the SPI_InitStruct.

Parameters:
SPIx,: where x can be 1, 2 or 3 to select the SPI peripheral.
SPI_InitStruct,: pointer to a SPI_InitTypeDef structure that contains the configuration information for the specified SPI peripheral.
Return values:
None

Definition at line 158 of file stm32f10x_spi.c.

References assert_param, SPI_TypeDef::CR1, CR1_CLEAR_Mask, SPI_TypeDef::CRCPR, SPI_TypeDef::I2SCFGR, IS_SPI_ALL_PERIPH, IS_SPI_BAUDRATE_PRESCALER, IS_SPI_CPHA, IS_SPI_CPOL, IS_SPI_CRC_POLYNOMIAL, IS_SPI_DATASIZE, IS_SPI_DIRECTION_MODE, IS_SPI_FIRST_BIT, IS_SPI_MODE, IS_SPI_NSS, SPI_InitTypeDef::SPI_BaudRatePrescaler, SPI_InitTypeDef::SPI_CPHA, SPI_InitTypeDef::SPI_CPOL, SPI_InitTypeDef::SPI_CRCPolynomial, SPI_InitTypeDef::SPI_DataSize, SPI_InitTypeDef::SPI_Direction, SPI_InitTypeDef::SPI_FirstBit, SPI_InitTypeDef::SPI_Mode, SPI_Mode_Select, and SPI_InitTypeDef::SPI_NSS.

Referenced by LCD_SPIConfig(), main(), SD_LowLevel_Init(), sFLASH_Init(), and SPI_Configuration().

void SPI_NSSInternalSoftwareConfig | ( | SPI_TypeDef * | SPIx,
 |  | uint16_t | SPI_NSSInternalSoft
 | ) |  |

Configures internally by software the NSS pin for the selected SPI.

Parameters:
SPIx,: where x can be 1, 2 or 3 to select the SPI peripheral.
SPI_NSSInternalSoft,: specifies the SPI NSS internal state. This parameter can be one of the following values:

  • SPI_NSSInternalSoft_Set: Set NSS pin internally
  • SPI_NSSInternalSoft_Reset: Reset NSS pin internally
Return values:
None

Definition at line 581 of file stm32f10x_spi.c.

References assert_param, SPI_TypeDef::CR1, IS_SPI_ALL_PERIPH, IS_SPI_NSS_INTERNAL, SPI_NSSInternalSoft_Reset, and SPI_NSSInternalSoft_Set.

void SPI_SSOutputCmd | ( | SPI_TypeDef * | SPIx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the SS output for the selected SPI.

Parameters:
SPIx,: where x can be 1, 2 or 3 to select the SPI peripheral.
NewState,: new state of the SPIx SS output. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 605 of file stm32f10x_spi.c.

References assert_param, SPI_TypeDef::CR2, CR2_SSOE_Reset, CR2_SSOE_Set, DISABLE, IS_FUNCTIONAL_STATE, and IS_SPI_ALL_PERIPH.

Referenced by main().

void SPI_StructInit ( SPI_InitTypeDef * SPI_InitStruct )

Fills each SPI_InitStruct member with its default value.

Parameters:
SPI_InitStruct : pointer to a SPI_InitTypeDef structure which will be initialized.
Return values:
None

Definition at line 370 of file stm32f10x_spi.c.

References SPI_InitTypeDef::SPI_BaudRatePrescaler, SPI_BaudRatePrescaler_2, SPI_InitTypeDef::SPI_CPHA, SPI_CPHA_1Edge, SPI_InitTypeDef::SPI_CPOL, SPI_CPOL_Low, SPI_InitTypeDef::SPI_CRCPolynomial, SPI_InitTypeDef::SPI_DataSize, SPI_DataSize_8b, SPI_InitTypeDef::SPI_Direction, SPI_Direction_2Lines_FullDuplex, SPI_InitTypeDef::SPI_FirstBit, SPI_FirstBit_MSB, SPI_InitTypeDef::SPI_Mode, SPI_Mode_Slave, SPI_InitTypeDef::SPI_NSS, and SPI_NSS_Hard.

Referenced by SPI_Configuration().

void SPI_TransmitCRC ( SPI_TypeDef * SPIx )

Transmit the SPIx CRC value.

Parameters:
SPIx,: where x can be 1, 2 or 3 to select the SPI peripheral.
Return values:
None

Definition at line 647 of file stm32f10x_spi.c.

References assert_param, SPI_TypeDef::CR1, CR1_CRCNext_Set, and IS_SPI_ALL_PERIPH.

Referenced by main().


STM32F10x Standard Peripherals Firmware Library: TIM_Exported_constants

Defines

TIM_Exported_constants

TIM_Exported_Types

Defines

#define | IS_TIM_ALL_PERIPH(PERIPH)
#define | IS_TIM_LIST1_PERIPH(PERIPH)
#define | IS_TIM_LIST2_PERIPH(PERIPH)
#define | IS_TIM_LIST3_PERIPH(PERIPH)
#define | IS_TIM_LIST4_PERIPH(PERIPH)
#define | IS_TIM_LIST5_PERIPH(PERIPH)
#define | IS_TIM_LIST6_PERIPH(PERIPH)
#define | IS_TIM_LIST7_PERIPH(PERIPH)
#define | IS_TIM_LIST8_PERIPH(PERIPH)
#define | IS_TIM_LIST9_PERIPH(PERIPH)

Define Documentation

#define IS_TIM_ALL_PERIPH ( PERIPH )
Value:
(((PERIPH) == TIM1) || \
                                   ((PERIPH) == TIM2) || \
                                   ((PERIPH) == TIM3) || \
                                   ((PERIPH) == TIM4) || \
                                   ((PERIPH) == TIM5) || \
                                   ((PERIPH) == TIM6) || \
                                   ((PERIPH) == TIM7) || \
                                   ((PERIPH) == TIM8) || \
                                   ((PERIPH) == TIM9) || \
                                   ((PERIPH) == TIM10)|| \
                                   ((PERIPH) == TIM11)|| \
                                   ((PERIPH) == TIM12)|| \
                                   ((PERIPH) == TIM13)|| \
                                   ((PERIPH) == TIM14)|| \
                                   ((PERIPH) == TIM15)|| \
                                   ((PERIPH) == TIM16)|| \
                                   ((PERIPH) == TIM17))

Definition at line 169 of file stm32f10x_tim.h.

Referenced by TIM_ARRPreloadConfig(), TIM_ClearFlag(), TIM_ClearITPendingBit(), TIM_Cmd(), TIM_DeInit(), TIM_GenerateEvent(), TIM_GetCounter(), TIM_GetFlagStatus(), TIM_GetITStatus(), TIM_GetPrescaler(), TIM_ITConfig(), TIM_PrescalerConfig(), TIM_SelectOnePulseMode(), TIM_SetAutoreload(), TIM_SetCounter(), TIM_TimeBaseInit(), TIM_UpdateDisableConfig(), and TIM_UpdateRequestConfig().

#define IS_TIM_LIST1_PERIPH ( PERIPH )
Value:
(((PERIPH) == TIM1) || \
                                      ((PERIPH) == TIM8))

Definition at line 188 of file stm32f10x_tim.h.

Referenced by TIM_OC2NPolarityConfig(), and TIM_OC3NPolarityConfig().

#define IS_TIM_LIST2_PERIPH ( PERIPH )
Value:
(((PERIPH) == TIM1) || \
                                     ((PERIPH) == TIM8) || \
                                     ((PERIPH) == TIM15)|| \
                                     ((PERIPH) == TIM16)|| \
                                     ((PERIPH) == TIM17))

Definition at line 192 of file stm32f10x_tim.h.

Referenced by TIM_BDTRConfig(), TIM_CCxNCmd(), TIM_CtrlPWMOutputs(), TIM_OC1NPolarityConfig(), and TIM_SelectCOM().

#define IS_TIM_LIST3_PERIPH ( PERIPH )
Value:
(((PERIPH) == TIM1) || \
                                     ((PERIPH) == TIM2) || \
                                     ((PERIPH) == TIM3) || \
                                     ((PERIPH) == TIM4) || \
                                     ((PERIPH) == TIM5) || \
                                     ((PERIPH) == TIM8))

Definition at line 199 of file stm32f10x_tim.h.

Referenced by TIM_ClearOC1Ref(), TIM_ClearOC2Ref(), TIM_ClearOC3Ref(), TIM_ClearOC4Ref(), TIM_CounterModeConfig(), TIM_ETRClockMode1Config(), TIM_ETRClockMode2Config(), TIM_ETRConfig(), TIM_ForcedOC3Config(), TIM_ForcedOC4Config(), TIM_GetCapture3(), TIM_GetCapture4(), TIM_ICInit(), TIM_OC3FastConfig(), TIM_OC3Init(), TIM_OC3PolarityConfig(), TIM_OC3PreloadConfig(), TIM_OC4FastConfig(), TIM_OC4Init(), TIM_OC4PolarityConfig(), TIM_OC4PreloadConfig(), TIM_SetCompare3(), TIM_SetCompare4(), TIM_SetIC3Prescaler(), and TIM_SetIC4Prescaler().

#define IS_TIM_LIST4_PERIPH ( PERIPH )
Value:
(((PERIPH) == TIM1) || \
                                     ((PERIPH) == TIM2) || \
                                     ((PERIPH) == TIM3) || \
                                     ((PERIPH) == TIM4) || \
                                     ((PERIPH) == TIM5) || \
                                     ((PERIPH) == TIM8) || \
                                     ((PERIPH) == TIM15)|| \
                                     ((PERIPH) == TIM16)|| \
                                     ((PERIPH) == TIM17))

Definition at line 207 of file stm32f10x_tim.h.

Referenced by TIM_DMAConfig(), and TIM_SelectCCDMA().

#define IS_TIM_LIST5_PERIPH ( PERIPH )
Value:
(((PERIPH) == TIM1) || \
                                     ((PERIPH) == TIM2) || \
                                     ((PERIPH) == TIM3) || \
                                     ((PERIPH) == TIM4) || \
                                     ((PERIPH) == TIM5) || \
                                     ((PERIPH) == TIM8) || \
                                     ((PERIPH) == TIM15))

Definition at line 218 of file stm32f10x_tim.h.

Referenced by TIM_CCPreloadControl(), and TIM_EncoderInterfaceConfig().

#define IS_TIM_LIST6_PERIPH ( PERIPH )
Value:
(((PERIPH) == TIM1) || \
                                      ((PERIPH) == TIM2) || \
                                      ((PERIPH) == TIM3) || \
                                      ((PERIPH) == TIM4) || \
                                      ((PERIPH) == TIM5) || \
                                      ((PERIPH) == TIM8) || \
                                      ((PERIPH) == TIM9) || \
                                                                          ((PERIPH) == TIM12)|| \
                                      ((PERIPH) == TIM15))

Definition at line 227 of file stm32f10x_tim.h.

Referenced by TIM_ForcedOC2Config(), TIM_GetCapture2(), TIM_ICInit(), TIM_InternalClockConfig(), TIM_ITRxExternalClockConfig(), TIM_OC2FastConfig(), TIM_OC2Init(), TIM_OC2PolarityConfig(), TIM_OC2PreloadConfig(), TIM_PWMIConfig(), TIM_SelectHallSensor(), TIM_SelectInputTrigger(), TIM_SelectMasterSlaveMode(), TIM_SelectSlaveMode(), TIM_SetCompare2(), TIM_SetIC2Prescaler(), and TIM_TIxExternalClockConfig().

#define IS_TIM_LIST7_PERIPH ( PERIPH )
Value:
(((PERIPH) == TIM1) || \
                                      ((PERIPH) == TIM2) || \
                                      ((PERIPH) == TIM3) || \
                                      ((PERIPH) == TIM4) || \
                                      ((PERIPH) == TIM5) || \
                                      ((PERIPH) == TIM6) || \
                                      ((PERIPH) == TIM7) || \
                                      ((PERIPH) == TIM8) || \
                                      ((PERIPH) == TIM9) || \
                                      ((PERIPH) == TIM12)|| \
                                      ((PERIPH) == TIM15))

Definition at line 238 of file stm32f10x_tim.h.

Referenced by TIM_SelectOutputTrigger().

#define IS_TIM_LIST8_PERIPH ( PERIPH )
Value:
(((PERIPH) == TIM1) || \
                                      ((PERIPH) == TIM2) || \
                                      ((PERIPH) == TIM3) || \
                                      ((PERIPH) == TIM4) || \
                                      ((PERIPH) == TIM5) || \
                                      ((PERIPH) == TIM8) || \
                                      ((PERIPH) == TIM9) || \
                                      ((PERIPH) == TIM10)|| \
                                      ((PERIPH) == TIM11)|| \
                                      ((PERIPH) == TIM12)|| \
                                      ((PERIPH) == TIM13)|| \
                                      ((PERIPH) == TIM14)|| \
                                      ((PERIPH) == TIM15)|| \
                                      ((PERIPH) == TIM16)|| \
                                      ((PERIPH) == TIM17))

Definition at line 251 of file stm32f10x_tim.h.

Referenced by TIM_CCxCmd(), TIM_ForcedOC1Config(), TIM_GetCapture1(), TIM_ICInit(), TIM_OC1FastConfig(), TIM_OC1Init(), TIM_OC1PolarityConfig(), TIM_OC1PreloadConfig(), TIM_SelectOCxM(), TIM_SetClockDivision(), TIM_SetCompare1(), and TIM_SetIC1Prescaler().

#define IS_TIM_LIST9_PERIPH ( PERIPH )
Value:
(((PERIPH) == TIM1) || \
                                      ((PERIPH) == TIM2) || \
                                      ((PERIPH) == TIM3) || \
                                      ((PERIPH) == TIM4) || \
                                      ((PERIPH) == TIM5) || \
                                      ((PERIPH) == TIM6) || \
                                      ((PERIPH) == TIM7) || \
                                      ((PERIPH) == TIM8) || \
                                      ((PERIPH) == TIM15)|| \
                                      ((PERIPH) == TIM16)|| \
                                      ((PERIPH) == TIM17))

Definition at line 268 of file stm32f10x_tim.h.

Referenced by TIM_DMACmd().


STM32F10x Standard Peripherals Firmware Library: TIM_Output_Compare_and_PWM_modes

Defines

TIM_Output_Compare_and_PWM_modes

TIM_Exported_Types

Defines

#define | IS_TIM_OC_MODE(MODE)
#define | IS_TIM_OCM(MODE)
#define | TIM_OCMode_Active ((uint16_t)0x0010)
#define | TIM_OCMode_Inactive ((uint16_t)0x0020)
#define | TIM_OCMode_PWM1 ((uint16_t)0x0060)
#define | TIM_OCMode_PWM2 ((uint16_t)0x0070)
#define | TIM_OCMode_Timing ((uint16_t)0x0000)
#define | TIM_OCMode_Toggle ((uint16_t)0x0030)

Define Documentation

#define IS_TIM_OC_MODE ( MODE )
Value:
(((MODE) == TIM_OCMode_Timing) || \
                              ((MODE) == TIM_OCMode_Active) || \
                              ((MODE) == TIM_OCMode_Inactive) || \
                              ((MODE) == TIM_OCMode_Toggle)|| \
                              ((MODE) == TIM_OCMode_PWM1) || \
                              ((MODE) == TIM_OCMode_PWM2))

Definition at line 294 of file stm32f10x_tim.h.

Referenced by TIM_OC1Init(), TIM_OC2Init(), TIM_OC3Init(), and TIM_OC4Init().

#define IS_TIM_OCM ( MODE )
Value:
(((MODE) == TIM_OCMode_Timing) || \
                          ((MODE) == TIM_OCMode_Active) || \
                          ((MODE) == TIM_OCMode_Inactive) || \
                          ((MODE) == TIM_OCMode_Toggle)|| \
                          ((MODE) == TIM_OCMode_PWM1) || \
                          ((MODE) == TIM_OCMode_PWM2) ||        \
                          ((MODE) == TIM_ForcedAction_Active) || \
                          ((MODE) == TIM_ForcedAction_InActive))

Definition at line 300 of file stm32f10x_tim.h.

Referenced by TIM_SelectOCxM().

#define TIM_OCMode_Active ((uint16_t)0x0010)

Definition at line 289 of file stm32f10x_tim.h.

Referenced by main().

#define TIM_OCMode_Inactive ((uint16_t)0x0020)

Definition at line 290 of file stm32f10x_tim.h.

Referenced by main().

#define TIM_OCMode_PWM1 ((uint16_t)0x0060)

Definition at line 292 of file stm32f10x_tim.h.

Referenced by main(), and TIM1_TRG_COM_IRQHandler().

#define TIM_OCMode_PWM2 ((uint16_t)0x0070)

Definition at line 293 of file stm32f10x_tim.h.

Referenced by main().

#define TIM_OCMode_Timing ((uint16_t)0x0000)

Definition at line 288 of file stm32f10x_tim.h.

Referenced by main(), TIM_Config(), and TIM_OCStructInit().

#define TIM_OCMode_Toggle ((uint16_t)0x0030)

Definition at line 291 of file stm32f10x_tim.h.

Referenced by main().


STM32F10x Standard Peripherals Firmware Library: TIM_One_Pulse_Mode

Defines

TIM_One_Pulse_Mode

TIM_Exported_Types

Defines

#define | IS_TIM_OPM_MODE(MODE)
#define | TIM_OPMode_Repetitive ((uint16_t)0x0000)
#define | TIM_OPMode_Single ((uint16_t)0x0008)

Define Documentation

#define IS_TIM_OPM_MODE ( MODE )
Value:
(((MODE) == TIM_OPMode_Single) || \
                               ((MODE) == TIM_OPMode_Repetitive))

Definition at line 318 of file stm32f10x_tim.h.

Referenced by TIM_SelectOnePulseMode().

#define TIM_OPMode_Repetitive ((uint16_t)0x0000)

Definition at line 317 of file stm32f10x_tim.h.

#define TIM_OPMode_Single ((uint16_t)0x0008)

Definition at line 316 of file stm32f10x_tim.h.

Referenced by main().


STM32F10x Standard Peripherals Firmware Library: TIM_Channel

Defines

TIM_Channel

TIM_Exported_Types

Defines

#define | IS_TIM_CHANNEL(CHANNEL)
#define | IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL)
#define | IS_TIM_PWMI_CHANNEL(CHANNEL)
#define | TIM_Channel_1 ((uint16_t)0x0000)
#define | TIM_Channel_2 ((uint16_t)0x0004)
#define | TIM_Channel_3 ((uint16_t)0x0008)
#define | TIM_Channel_4 ((uint16_t)0x000C)

Define Documentation

#define IS_TIM_CHANNEL ( CHANNEL )
Value:
(((CHANNEL) == TIM_Channel_1) || \
                                 ((CHANNEL) == TIM_Channel_2) || \
                                 ((CHANNEL) == TIM_Channel_3) || \
                                 ((CHANNEL) == TIM_Channel_4))

Definition at line 332 of file stm32f10x_tim.h.

Referenced by TIM_CCxCmd(), TIM_ICInit(), and TIM_SelectOCxM().

#define IS_TIM_COMPLEMENTARY_CHANNEL ( CHANNEL )
Value:
(((CHANNEL) == TIM_Channel_1) || \
                                               ((CHANNEL) == TIM_Channel_2) || \
                                               ((CHANNEL) == TIM_Channel_3))

Definition at line 338 of file stm32f10x_tim.h.

Referenced by TIM_CCxNCmd().

#define IS_TIM_PWMI_CHANNEL ( CHANNEL )
Value:
(((CHANNEL) == TIM_Channel_1) || \
                                      ((CHANNEL) == TIM_Channel_2))

Definition at line 336 of file stm32f10x_tim.h.

#define TIM_Channel_1 ((uint16_t)0x0000)

Definition at line 328 of file stm32f10x_tim.h.

Referenced by TIM1_TRG_COM_IRQHandler(), TIM_ICInit(), TIM_ICStructInit(), TIM_PWMIConfig(), and TIM_SelectOCxM().

#define TIM_Channel_2 ((uint16_t)0x0004)

Definition at line 329 of file stm32f10x_tim.h.

Referenced by main(), TIM1_TRG_COM_IRQHandler(), and TIM_ICInit().

#define TIM_Channel_3 ((uint16_t)0x0008)

Definition at line 330 of file stm32f10x_tim.h.

Referenced by TIM1_TRG_COM_IRQHandler(), TIM_ICInit(), and TIM_SelectOCxM().

#define TIM_Channel_4 ((uint16_t)0x000C)

Definition at line 331 of file stm32f10x_tim.h.

Referenced by main(), and TIM5_ConfigForLSI().


STM32F10x Standard Peripherals Firmware Library: TIM_Clock_Division_CKD

Defines

TIM_Clock_Division_CKD

TIM_Exported_Types

Defines

#define | IS_TIM_CKD_DIV(DIV)
#define | TIM_CKD_DIV1 ((uint16_t)0x0000)
#define | TIM_CKD_DIV2 ((uint16_t)0x0100)
#define | TIM_CKD_DIV4 ((uint16_t)0x0200)

Define Documentation

#define IS_TIM_CKD_DIV ( DIV )
Value:
(((DIV) == TIM_CKD_DIV1) || \
                             ((DIV) == TIM_CKD_DIV2) || \
                             ((DIV) == TIM_CKD_DIV4))

Definition at line 352 of file stm32f10x_tim.h.

Referenced by TIM_SetClockDivision(), and TIM_TimeBaseInit().

#define TIM_CKD_DIV1 ((uint16_t)0x0000)

Definition at line 349 of file stm32f10x_tim.h.

Referenced by main(), and TIM_TimeBaseStructInit().

#define TIM_CKD_DIV2 ((uint16_t)0x0100)

Definition at line 350 of file stm32f10x_tim.h.

#define TIM_CKD_DIV4 ((uint16_t)0x0200)

Definition at line 351 of file stm32f10x_tim.h.


STM32F10x Standard Peripherals Firmware Library: TIM_Counter_Mode

Defines

TIM_Counter_Mode

TIM_Exported_Types

Defines

#define | IS_TIM_COUNTER_MODE(MODE)
#define | TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020)
#define | TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040)
#define | TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060)
#define | TIM_CounterMode_Down ((uint16_t)0x0010)
#define | TIM_CounterMode_Up ((uint16_t)0x0000)

Define Documentation

#define IS_TIM_COUNTER_MODE ( MODE )
Value:
(((MODE) == TIM_CounterMode_Up) ||  \
                                   ((MODE) == TIM_CounterMode_Down) || \
                                   ((MODE) == TIM_CounterMode_CenterAligned1) || \
                                   ((MODE) == TIM_CounterMode_CenterAligned2) || \
                                   ((MODE) == TIM_CounterMode_CenterAligned3))

Definition at line 368 of file stm32f10x_tim.h.

Referenced by TIM_CounterModeConfig(), and TIM_TimeBaseInit().

#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020)

Definition at line 365 of file stm32f10x_tim.h.

#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040)

Definition at line 366 of file stm32f10x_tim.h.

#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060)

Definition at line 367 of file stm32f10x_tim.h.

#define TIM_CounterMode_Down ((uint16_t)0x0010)

Definition at line 364 of file stm32f10x_tim.h.

#define TIM_CounterMode_Up ((uint16_t)0x0000)

Definition at line 363 of file stm32f10x_tim.h.

Referenced by main(), TIM_Config(), and TIM_TimeBaseStructInit().


STM32F10x Standard Peripherals Firmware Library: TIM_Output_Compare_Polarity

Defines

TIM_Output_Compare_Polarity

TIM_Exported_Types

Defines

#define | IS_TIM_OC_POLARITY(POLARITY)
#define | TIM_OCPolarity_High ((uint16_t)0x0000)
#define | TIM_OCPolarity_Low ((uint16_t)0x0002)

Define Documentation

#define IS_TIM_OC_POLARITY ( POLARITY )
Value:
(((POLARITY) == TIM_OCPolarity_High) || \
                                      ((POLARITY) == TIM_OCPolarity_Low))

Definition at line 383 of file stm32f10x_tim.h.

Referenced by TIM_OC1Init(), TIM_OC1PolarityConfig(), TIM_OC2Init(), TIM_OC2PolarityConfig(), TIM_OC3Init(), TIM_OC3PolarityConfig(), TIM_OC4Init(), and TIM_OC4PolarityConfig().

#define TIM_OCPolarity_High ((uint16_t)0x0000)

Definition at line 381 of file stm32f10x_tim.h.

Referenced by main(), and TIM_OCStructInit().

#define TIM_OCPolarity_Low ((uint16_t)0x0002)

Definition at line 382 of file stm32f10x_tim.h.

Referenced by main().


STM32F10x Standard Peripherals Firmware Library: TIM_Output_Compare_N_Polarity

Defines

TIM_Output_Compare_N_Polarity

TIM_Exported_Types

Defines

#define | IS_TIM_OCN_POLARITY(POLARITY)
#define | TIM_OCNPolarity_High ((uint16_t)0x0000)
#define | TIM_OCNPolarity_Low ((uint16_t)0x0008)

Define Documentation

#define IS_TIM_OCN_POLARITY ( POLARITY )
Value:
(((POLARITY) == TIM_OCNPolarity_High) || \
                                       ((POLARITY) == TIM_OCNPolarity_Low))

Definition at line 395 of file stm32f10x_tim.h.

Referenced by TIM_OC1Init(), TIM_OC1NPolarityConfig(), TIM_OC2Init(), TIM_OC2NPolarityConfig(), TIM_OC3Init(), and TIM_OC3NPolarityConfig().

#define TIM_OCNPolarity_High ((uint16_t)0x0000)

Definition at line 393 of file stm32f10x_tim.h.

Referenced by main().

#define TIM_OCNPolarity_Low ((uint16_t)0x0008)

Definition at line 394 of file stm32f10x_tim.h.

Referenced by main().


STM32F10x Standard Peripherals Firmware Library: TIM_Output_Compare_state

Defines

TIM_Output_Compare_state

TIM_Exported_Types

Defines

#define | IS_TIM_OUTPUT_STATE(STATE)
#define | TIM_OutputState_Disable ((uint16_t)0x0000)
#define | TIM_OutputState_Enable ((uint16_t)0x0001)

Define Documentation

#define IS_TIM_OUTPUT_STATE ( STATE )
Value:
(((STATE) == TIM_OutputState_Disable) || \
                                    ((STATE) == TIM_OutputState_Enable))

Definition at line 407 of file stm32f10x_tim.h.

Referenced by TIM_OC1Init(), TIM_OC2Init(), TIM_OC3Init(), and TIM_OC4Init().

#define TIM_OutputState_Disable ((uint16_t)0x0000)

Definition at line 405 of file stm32f10x_tim.h.

Referenced by TIM_OCStructInit().

#define TIM_OutputState_Enable ((uint16_t)0x0001)

Definition at line 406 of file stm32f10x_tim.h.

Referenced by main().


STM32F10x Standard Peripherals Firmware Library: TIM_Output_Compare_N_state

Defines

TIM_Output_Compare_N_state

TIM_Exported_Types

Defines

#define | IS_TIM_OUTPUTN_STATE(STATE)
#define | TIM_OutputNState_Disable ((uint16_t)0x0000)
#define | TIM_OutputNState_Enable ((uint16_t)0x0004)

Define Documentation

#define IS_TIM_OUTPUTN_STATE ( STATE )
Value:
(((STATE) == TIM_OutputNState_Disable) || \
                                     ((STATE) == TIM_OutputNState_Enable))

Definition at line 419 of file stm32f10x_tim.h.

Referenced by TIM_OC1Init(), TIM_OC2Init(), and TIM_OC3Init().

#define TIM_OutputNState_Disable ((uint16_t)0x0000)

Definition at line 417 of file stm32f10x_tim.h.

Referenced by TIM_OCStructInit().

#define TIM_OutputNState_Enable ((uint16_t)0x0004)

Definition at line 418 of file stm32f10x_tim.h.

Referenced by main().


STM32F10x Standard Peripherals Firmware Library: TIM_Capture_Compare_state

Defines

TIM_Capture_Compare_state

TIM_Exported_Types

Defines

#define | IS_TIM_CCX(CCX)
#define | TIM_CCx_Disable ((uint16_t)0x0000)
#define | TIM_CCx_Enable ((uint16_t)0x0001)

Define Documentation

#define IS_TIM_CCX ( CCX )
Value:
(((CCX) == TIM_CCx_Enable) || \
                         ((CCX) == TIM_CCx_Disable))

Definition at line 431 of file stm32f10x_tim.h.

Referenced by TIM_CCxCmd().

#define TIM_CCx_Disable ((uint16_t)0x0000)

Definition at line 430 of file stm32f10x_tim.h.

Referenced by TIM1_TRG_COM_IRQHandler().

#define TIM_CCx_Enable ((uint16_t)0x0001)

Definition at line 429 of file stm32f10x_tim.h.

Referenced by TIM1_TRG_COM_IRQHandler().


STM32F10x Standard Peripherals Firmware Library: TIM_Capture_Compare_N_state

Defines

TIM_Capture_Compare_N_state

TIM_Exported_Types

Defines

#define | IS_TIM_CCXN(CCXN)
#define | TIM_CCxN_Disable ((uint16_t)0x0000)
#define | TIM_CCxN_Enable ((uint16_t)0x0004)

Define Documentation

#define IS_TIM_CCXN ( CCXN )
Value:
(((CCXN) == TIM_CCxN_Enable) || \
                           ((CCXN) == TIM_CCxN_Disable))

Definition at line 443 of file stm32f10x_tim.h.

Referenced by TIM_CCxNCmd().

#define TIM_CCxN_Disable ((uint16_t)0x0000)

Definition at line 442 of file stm32f10x_tim.h.

Referenced by TIM1_TRG_COM_IRQHandler().

#define TIM_CCxN_Enable ((uint16_t)0x0004)

Definition at line 441 of file stm32f10x_tim.h.

Referenced by TIM1_TRG_COM_IRQHandler().


STM32F10x Standard Peripherals Firmware Library: Break_Input_enable_disable

Defines

Break_Input_enable_disable

TIM_Exported_Types

Defines

#define | IS_TIM_BREAK_STATE(STATE)
#define | TIM_Break_Disable ((uint16_t)0x0000)
#define | TIM_Break_Enable ((uint16_t)0x1000)

Define Documentation

#define IS_TIM_BREAK_STATE ( STATE )
Value:
(((STATE) == TIM_Break_Enable) || \
                                   ((STATE) == TIM_Break_Disable))

Definition at line 455 of file stm32f10x_tim.h.

Referenced by TIM_BDTRConfig().

#define TIM_Break_Disable ((uint16_t)0x0000)

Definition at line 454 of file stm32f10x_tim.h.

Referenced by main(), and TIM_BDTRStructInit().

#define TIM_Break_Enable ((uint16_t)0x1000)

Definition at line 453 of file stm32f10x_tim.h.

Referenced by main().


STM32F10x Standard Peripherals Firmware Library: Break_Polarity

Defines

Break_Polarity

TIM_Exported_Types

Defines

#define | IS_TIM_BREAK_POLARITY(POLARITY)
#define | TIM_BreakPolarity_High ((uint16_t)0x2000)
#define | TIM_BreakPolarity_Low ((uint16_t)0x0000)

Define Documentation

#define IS_TIM_BREAK_POLARITY ( POLARITY )
Value:
(((POLARITY) == TIM_BreakPolarity_Low) || \
                                         ((POLARITY) == TIM_BreakPolarity_High))

Definition at line 467 of file stm32f10x_tim.h.

Referenced by TIM_BDTRConfig().

#define TIM_BreakPolarity_High ((uint16_t)0x2000)

Definition at line 466 of file stm32f10x_tim.h.

Referenced by main().

#define TIM_BreakPolarity_Low ((uint16_t)0x0000)

Definition at line 465 of file stm32f10x_tim.h.

Referenced by TIM_BDTRStructInit().


STM32F10x Standard Peripherals Firmware Library: TIM_AOE_Bit_Set_Reset

Defines

TIM_AOE_Bit_Set_Reset

TIM_Exported_Types

Defines

#define | IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE)
#define | TIM_AutomaticOutput_Disable ((uint16_t)0x0000)
#define | TIM_AutomaticOutput_Enable ((uint16_t)0x4000)

Define Documentation

#define IS_TIM_AUTOMATIC_OUTPUT_STATE ( STATE )
Value:
(((STATE) == TIM_AutomaticOutput_Enable) || \
                                              ((STATE) == TIM_AutomaticOutput_Disable))

Definition at line 479 of file stm32f10x_tim.h.

Referenced by TIM_BDTRConfig().

#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000)

Definition at line 478 of file stm32f10x_tim.h.

Referenced by main(), and TIM_BDTRStructInit().

#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000)

Definition at line 477 of file stm32f10x_tim.h.

Referenced by main().


STM32F10x Standard Peripherals Firmware Library: Lock_level

Defines

Lock_level

TIM_Exported_Types

Defines

#define | IS_TIM_LOCK_LEVEL(LEVEL)
#define | TIM_LOCKLevel_1 ((uint16_t)0x0100)
#define | TIM_LOCKLevel_2 ((uint16_t)0x0200)
#define | TIM_LOCKLevel_3 ((uint16_t)0x0300)
#define | TIM_LOCKLevel_OFF ((uint16_t)0x0000)

Define Documentation

#define IS_TIM_LOCK_LEVEL ( LEVEL )
Value:
(((LEVEL) == TIM_LOCKLevel_OFF) || \
                                  ((LEVEL) == TIM_LOCKLevel_1) || \
                                  ((LEVEL) == TIM_LOCKLevel_2) || \
                                  ((LEVEL) == TIM_LOCKLevel_3))

Definition at line 493 of file stm32f10x_tim.h.

Referenced by TIM_BDTRConfig().

#define TIM_LOCKLevel_1 ((uint16_t)0x0100)

Definition at line 490 of file stm32f10x_tim.h.

Referenced by main().

#define TIM_LOCKLevel_2 ((uint16_t)0x0200)

Definition at line 491 of file stm32f10x_tim.h.

#define TIM_LOCKLevel_3 ((uint16_t)0x0300)

Definition at line 492 of file stm32f10x_tim.h.

#define TIM_LOCKLevel_OFF ((uint16_t)0x0000)

Definition at line 489 of file stm32f10x_tim.h.

Referenced by main(), and TIM_BDTRStructInit().


STM32F10x Standard Peripherals Firmware Library: OSSI_Off_State_Selection_for_Idle_mode_state

Defines

OSSI_Off_State_Selection_for_Idle_mode_state

TIM_Exported_Types

Defines

#define | IS_TIM_OSSI_STATE(STATE)
#define | TIM_OSSIState_Disable ((uint16_t)0x0000)
#define | TIM_OSSIState_Enable ((uint16_t)0x0400)

Define Documentation

#define IS_TIM_OSSI_STATE ( STATE )
Value:
(((STATE) == TIM_OSSIState_Enable) || \
                                  ((STATE) == TIM_OSSIState_Disable))

Definition at line 507 of file stm32f10x_tim.h.

Referenced by TIM_BDTRConfig().

#define TIM_OSSIState_Disable ((uint16_t)0x0000)

Definition at line 506 of file stm32f10x_tim.h.

Referenced by TIM_BDTRStructInit().

#define TIM_OSSIState_Enable ((uint16_t)0x0400)

Definition at line 505 of file stm32f10x_tim.h.

Referenced by main().


STM32F10x Standard Peripherals Firmware Library: OSSR_Off_State_Selection_for_Run_mode_state

Defines

OSSR_Off_State_Selection_for_Run_mode_state

TIM_Exported_Types

Defines

#define | IS_TIM_OSSR_STATE(STATE)
#define | TIM_OSSRState_Disable ((uint16_t)0x0000)
#define | TIM_OSSRState_Enable ((uint16_t)0x0800)

Define Documentation

#define IS_TIM_OSSR_STATE ( STATE )
Value:
(((STATE) == TIM_OSSRState_Enable) || \
                                  ((STATE) == TIM_OSSRState_Disable))

Definition at line 519 of file stm32f10x_tim.h.

Referenced by TIM_BDTRConfig().

#define TIM_OSSRState_Disable ((uint16_t)0x0000)

Definition at line 518 of file stm32f10x_tim.h.

Referenced by TIM_BDTRStructInit().

#define TIM_OSSRState_Enable ((uint16_t)0x0800)

Definition at line 517 of file stm32f10x_tim.h.

Referenced by main().


STM32F10x Standard Peripherals Firmware Library: TIM_Output_Compare_Idle_State

Defines

TIM_Output_Compare_Idle_State

TIM_Exported_Types

Defines

#define | IS_TIM_OCIDLE_STATE(STATE)
#define | TIM_OCIdleState_Reset ((uint16_t)0x0000)
#define | TIM_OCIdleState_Set ((uint16_t)0x0100)

Define Documentation

#define IS_TIM_OCIDLE_STATE ( STATE )
Value:
(((STATE) == TIM_OCIdleState_Set) || \
                                    ((STATE) == TIM_OCIdleState_Reset))

Definition at line 531 of file stm32f10x_tim.h.

Referenced by TIM_OC1Init(), TIM_OC2Init(), TIM_OC3Init(), and TIM_OC4Init().

#define TIM_OCIdleState_Reset ((uint16_t)0x0000)

Definition at line 530 of file stm32f10x_tim.h.

Referenced by main(), and TIM_OCStructInit().

#define TIM_OCIdleState_Set ((uint16_t)0x0100)

Definition at line 529 of file stm32f10x_tim.h.

Referenced by main().


STM32F10x Standard Peripherals Firmware Library: TIM_Output_Compare_N_Idle_State

Defines

TIM_Output_Compare_N_Idle_State

TIM_Exported_Types

Defines

#define | IS_TIM_OCNIDLE_STATE(STATE)
#define | TIM_OCNIdleState_Reset ((uint16_t)0x0000)
#define | TIM_OCNIdleState_Set ((uint16_t)0x0200)

Define Documentation

#define IS_TIM_OCNIDLE_STATE ( STATE )
Value:
(((STATE) == TIM_OCNIdleState_Set) || \
                                     ((STATE) == TIM_OCNIdleState_Reset))

Definition at line 543 of file stm32f10x_tim.h.

Referenced by TIM_OC1Init(), TIM_OC2Init(), and TIM_OC3Init().

#define TIM_OCNIdleState_Reset ((uint16_t)0x0000)

Definition at line 542 of file stm32f10x_tim.h.

Referenced by TIM_OCStructInit().

#define TIM_OCNIdleState_Set ((uint16_t)0x0200)

Definition at line 541 of file stm32f10x_tim.h.

Referenced by main().


STM32F10x Standard Peripherals Firmware Library: TIM_Input_Capture_Polarity

Defines

TIM_Input_Capture_Polarity

TIM_Exported_Types

Defines

#define | IS_TIM_IC_POLARITY(POLARITY)
#define | IS_TIM_IC_POLARITY_LITE(POLARITY)
#define | TIM_ICPolarity_BothEdge ((uint16_t)0x000A)
#define | TIM_ICPolarity_Falling ((uint16_t)0x0002)
#define | TIM_ICPolarity_Rising ((uint16_t)0x0000)

Define Documentation

#define IS_TIM_IC_POLARITY ( POLARITY )
Value:
(((POLARITY) == TIM_ICPolarity_Rising) || \
                                      ((POLARITY) == TIM_ICPolarity_Falling))

Definition at line 556 of file stm32f10x_tim.h.

Referenced by TIM_EncoderInterfaceConfig(), TIM_ICInit(), and TIM_TIxExternalClockConfig().

#define IS_TIM_IC_POLARITY_LITE ( POLARITY )
Value:
(((POLARITY) == TIM_ICPolarity_Rising) || \
                                           ((POLARITY) == TIM_ICPolarity_Falling)|| \
                                           ((POLARITY) == TIM_ICPolarity_BothEdge))

Definition at line 558 of file stm32f10x_tim.h.

Referenced by TIM_ICInit().

#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A)

Definition at line 555 of file stm32f10x_tim.h.

#define TIM_ICPolarity_Falling ((uint16_t)0x0002)

Definition at line 554 of file stm32f10x_tim.h.

Referenced by TIM_PWMIConfig().

#define TIM_ICPolarity_Rising ((uint16_t)0x0000)

Definition at line 553 of file stm32f10x_tim.h.

Referenced by main(), TIM5_ConfigForLSI(), TIM_ICStructInit(), and TIM_PWMIConfig().


STM32F10x Standard Peripherals Firmware Library: TIM_Input_Capture_Selection

Defines

TIM_Input_Capture_Selection

TIM_Exported_Types

Defines

#define | IS_TIM_IC_SELECTION(SELECTION)
#define | TIM_ICSelection_DirectTI ((uint16_t)0x0001)
#define | TIM_ICSelection_IndirectTI ((uint16_t)0x0002)
#define | TIM_ICSelection_TRC ((uint16_t)0x0003)

Define Documentation

#define IS_TIM_IC_SELECTION ( SELECTION )
Value:
(((SELECTION) == TIM_ICSelection_DirectTI) || \
                                        ((SELECTION) == TIM_ICSelection_IndirectTI) || \
                                        ((SELECTION) == TIM_ICSelection_TRC))

Definition at line 574 of file stm32f10x_tim.h.

Referenced by TIM_ICInit().

#define TIM_ICSelection_DirectTI ((uint16_t)0x0001)

TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively

Definition at line 569 of file stm32f10x_tim.h.

Referenced by main(), TIM5_ConfigForLSI(), TIM_ICStructInit(), TIM_PWMIConfig(), and TIM_TIxExternalClockConfig().

#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002)

TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively.

Definition at line 571 of file stm32f10x_tim.h.

Referenced by TIM_PWMIConfig().

#define TIM_ICSelection_TRC ((uint16_t)0x0003)

TIM Input 1, 2, 3 or 4 is selected to be connected to TRC.

Definition at line 573 of file stm32f10x_tim.h.


STM32F10x Standard Peripherals Firmware Library: TIM_Input_Capture_Prescaler

Defines

TIM_Input_Capture_Prescaler

TIM_Exported_Types

Defines

#define | IS_TIM_IC_PRESCALER(PRESCALER)
#define | TIM_ICPSC_DIV1 ((uint16_t)0x0000)
#define | TIM_ICPSC_DIV2 ((uint16_t)0x0004)
#define | TIM_ICPSC_DIV4 ((uint16_t)0x0008)
#define | TIM_ICPSC_DIV8 ((uint16_t)0x000C)

Define Documentation

#define IS_TIM_IC_PRESCALER ( PRESCALER )
Value:
(((PRESCALER) == TIM_ICPSC_DIV1) || \
                                        ((PRESCALER) == TIM_ICPSC_DIV2) || \
                                        ((PRESCALER) == TIM_ICPSC_DIV4) || \
                                        ((PRESCALER) == TIM_ICPSC_DIV8))

Definition at line 589 of file stm32f10x_tim.h.

Referenced by TIM_ICInit(), TIM_SetIC1Prescaler(), TIM_SetIC2Prescaler(), TIM_SetIC3Prescaler(), and TIM_SetIC4Prescaler().

#define TIM_ICPSC_DIV1 ((uint16_t)0x0000)

Capture performed each time an edge is detected on the capture input.

Definition at line 585 of file stm32f10x_tim.h.

Referenced by main(), and TIM_ICStructInit().

#define TIM_ICPSC_DIV2 ((uint16_t)0x0004)

Capture performed once every 2 events.

Definition at line 586 of file stm32f10x_tim.h.

#define TIM_ICPSC_DIV4 ((uint16_t)0x0008)

Capture performed once every 4 events.

Definition at line 587 of file stm32f10x_tim.h.

#define TIM_ICPSC_DIV8 ((uint16_t)0x000C)

Capture performed once every 8 events.

Definition at line 588 of file stm32f10x_tim.h.

Referenced by TIM5_ConfigForLSI().


STM32F10x Standard Peripherals Firmware Library: TIM_interrupt_sources

Defines

TIM_interrupt_sources

TIM_Exported_Types

Defines

#define | IS_TIM_GET_IT(IT)
#define | IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000))
#define | TIM_IT_Break ((uint16_t)0x0080)
#define | TIM_IT_CC1 ((uint16_t)0x0002)
#define | TIM_IT_CC2 ((uint16_t)0x0004)
#define | TIM_IT_CC3 ((uint16_t)0x0008)
#define | TIM_IT_CC4 ((uint16_t)0x0010)
#define | TIM_IT_COM ((uint16_t)0x0020)
#define | TIM_IT_Trigger ((uint16_t)0x0040)
#define | TIM_IT_Update ((uint16_t)0x0001)

Define Documentation

#define IS_TIM_GET_IT ( IT )
Value:
(((IT) == TIM_IT_Update) || \
                           ((IT) == TIM_IT_CC1) || \
                           ((IT) == TIM_IT_CC2) || \
                           ((IT) == TIM_IT_CC3) || \
                           ((IT) == TIM_IT_CC4) || \
                           ((IT) == TIM_IT_COM) || \
                           ((IT) == TIM_IT_Trigger) || \
                           ((IT) == TIM_IT_Break))

Definition at line 611 of file stm32f10x_tim.h.

Referenced by TIM_GetITStatus().

#define IS_TIM_IT ( IT ) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000))

Definition at line 609 of file stm32f10x_tim.h.

Referenced by TIM_ClearITPendingBit(), and TIM_ITConfig().

#define TIM_IT_Break ((uint16_t)0x0080)

Definition at line 608 of file stm32f10x_tim.h.

#define TIM_IT_CC1 ((uint16_t)0x0002)

Definition at line 602 of file stm32f10x_tim.h.

Referenced by main(), TIM1_BRK_TIM9_IRQHandler(), TIM2_IRQHandler(), and TIM3_IRQHandler().

#define TIM_IT_CC2 ((uint16_t)0x0004)

Definition at line 603 of file stm32f10x_tim.h.

Referenced by main(), TIM1_BRK_TIM9_IRQHandler(), TIM2_IRQHandler(), and TIM3_IRQHandler().

#define TIM_IT_CC3 ((uint16_t)0x0008)

Definition at line 604 of file stm32f10x_tim.h.

Referenced by main(), TIM2_IRQHandler(), and TIM3_IRQHandler().

#define TIM_IT_CC4 ((uint16_t)0x0010)

Definition at line 605 of file stm32f10x_tim.h.

Referenced by main(), TIM2_IRQHandler(), TIM3_IRQHandler(), TIM5_ConfigForLSI(), and TIM5_IRQHandler().

#define TIM_IT_COM ((uint16_t)0x0020)

Definition at line 606 of file stm32f10x_tim.h.

Referenced by main(), and TIM1_TRG_COM_IRQHandler().

#define TIM_IT_Trigger ((uint16_t)0x0040)

Definition at line 607 of file stm32f10x_tim.h.

#define TIM_IT_Update ((uint16_t)0x0001)

Definition at line 601 of file stm32f10x_tim.h.

Referenced by TIM2_IRQHandler(), TIM3_IRQHandler(), TIM4_IRQHandler(), and TIM_Config().


STM32F10x Standard Peripherals Firmware Library: TIM_DMA_Base_address

Defines

TIM_DMA_Base_address

TIM_Exported_Types

Defines

#define | IS_TIM_DMA_BASE(BASE)
#define | TIM_DMABase_ARR ((uint16_t)0x000B)
#define | TIM_DMABase_BDTR ((uint16_t)0x0011)
#define | TIM_DMABase_CCER ((uint16_t)0x0008)
#define | TIM_DMABase_CCMR1 ((uint16_t)0x0006)
#define | TIM_DMABase_CCMR2 ((uint16_t)0x0007)
#define | TIM_DMABase_CCR1 ((uint16_t)0x000D)
#define | TIM_DMABase_CCR2 ((uint16_t)0x000E)
#define | TIM_DMABase_CCR3 ((uint16_t)0x000F)
#define | TIM_DMABase_CCR4 ((uint16_t)0x0010)
#define | TIM_DMABase_CNT ((uint16_t)0x0009)
#define | TIM_DMABase_CR1 ((uint16_t)0x0000)
#define | TIM_DMABase_CR2 ((uint16_t)0x0001)
#define | TIM_DMABase_DCR ((uint16_t)0x0012)
#define | TIM_DMABase_DIER ((uint16_t)0x0003)
#define | TIM_DMABase_EGR ((uint16_t)0x0005)
#define | TIM_DMABase_PSC ((uint16_t)0x000A)
#define | TIM_DMABase_RCR ((uint16_t)0x000C)
#define | TIM_DMABase_SMCR ((uint16_t)0x0002)
#define | TIM_DMABase_SR ((uint16_t)0x0004)

Define Documentation

#define IS_TIM_DMA_BASE ( BASE )
Value:
(((BASE) == TIM_DMABase_CR1) || \
                               ((BASE) == TIM_DMABase_CR2) || \
                               ((BASE) == TIM_DMABase_SMCR) || \
                               ((BASE) == TIM_DMABase_DIER) || \
                               ((BASE) == TIM_DMABase_SR) || \
                               ((BASE) == TIM_DMABase_EGR) || \
                               ((BASE) == TIM_DMABase_CCMR1) || \
                               ((BASE) == TIM_DMABase_CCMR2) || \
                               ((BASE) == TIM_DMABase_CCER) || \
                               ((BASE) == TIM_DMABase_CNT) || \
                               ((BASE) == TIM_DMABase_PSC) || \
                               ((BASE) == TIM_DMABase_ARR) || \
                               ((BASE) == TIM_DMABase_RCR) || \
                               ((BASE) == TIM_DMABase_CCR1) || \
                               ((BASE) == TIM_DMABase_CCR2) || \
                               ((BASE) == TIM_DMABase_CCR3) || \
                               ((BASE) == TIM_DMABase_CCR4) || \
                               ((BASE) == TIM_DMABase_BDTR) || \
                               ((BASE) == TIM_DMABase_DCR))

Definition at line 646 of file stm32f10x_tim.h.

Referenced by TIM_DMAConfig().

#define TIM_DMABase_ARR ((uint16_t)0x000B)

Definition at line 638 of file stm32f10x_tim.h.

Referenced by main().

#define TIM_DMABase_BDTR ((uint16_t)0x0011)

Definition at line 644 of file stm32f10x_tim.h.

#define TIM_DMABase_CCER ((uint16_t)0x0008)

Definition at line 635 of file stm32f10x_tim.h.

#define TIM_DMABase_CCMR1 ((uint16_t)0x0006)

Definition at line 633 of file stm32f10x_tim.h.

#define TIM_DMABase_CCMR2 ((uint16_t)0x0007)

Definition at line 634 of file stm32f10x_tim.h.

#define TIM_DMABase_CCR1 ((uint16_t)0x000D)

Definition at line 640 of file stm32f10x_tim.h.

#define TIM_DMABase_CCR2 ((uint16_t)0x000E)

Definition at line 641 of file stm32f10x_tim.h.

#define TIM_DMABase_CCR3 ((uint16_t)0x000F)

Definition at line 642 of file stm32f10x_tim.h.

#define TIM_DMABase_CCR4 ((uint16_t)0x0010)

Definition at line 643 of file stm32f10x_tim.h.

#define TIM_DMABase_CNT ((uint16_t)0x0009)

Definition at line 636 of file stm32f10x_tim.h.

#define TIM_DMABase_CR1 ((uint16_t)0x0000)

Definition at line 627 of file stm32f10x_tim.h.

#define TIM_DMABase_CR2 ((uint16_t)0x0001)

Definition at line 628 of file stm32f10x_tim.h.

#define TIM_DMABase_DCR ((uint16_t)0x0012)

Definition at line 645 of file stm32f10x_tim.h.

#define TIM_DMABase_DIER ((uint16_t)0x0003)

Definition at line 630 of file stm32f10x_tim.h.

#define TIM_DMABase_EGR ((uint16_t)0x0005)

Definition at line 632 of file stm32f10x_tim.h.

#define TIM_DMABase_PSC ((uint16_t)0x000A)

Definition at line 637 of file stm32f10x_tim.h.

#define TIM_DMABase_RCR ((uint16_t)0x000C)

Definition at line 639 of file stm32f10x_tim.h.

#define TIM_DMABase_SMCR ((uint16_t)0x0002)

Definition at line 629 of file stm32f10x_tim.h.

#define TIM_DMABase_SR ((uint16_t)0x0004)

Definition at line 631 of file stm32f10x_tim.h.


STM32F10x Standard Peripherals Firmware Library: TIM_DMA_Burst_Length

Defines

TIM_DMA_Burst_Length

TIM_Exported_Types

Defines

#define | IS_TIM_DMA_LENGTH(LENGTH)
#define | TIM_DMABurstLength_10Transfers ((uint16_t)0x0900)
#define | TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00)
#define | TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00)
#define | TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00)
#define | TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00)
#define | TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00)
#define | TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00)
#define | TIM_DMABurstLength_17Transfers ((uint16_t)0x1000)
#define | TIM_DMABurstLength_18Transfers ((uint16_t)0x1100)
#define | TIM_DMABurstLength_1Transfer ((uint16_t)0x0000)
#define | TIM_DMABurstLength_2Transfers ((uint16_t)0x0100)
#define | TIM_DMABurstLength_3Transfers ((uint16_t)0x0200)
#define | TIM_DMABurstLength_4Transfers ((uint16_t)0x0300)
#define | TIM_DMABurstLength_5Transfers ((uint16_t)0x0400)
#define | TIM_DMABurstLength_6Transfers ((uint16_t)0x0500)
#define | TIM_DMABurstLength_7Transfers ((uint16_t)0x0600)
#define | TIM_DMABurstLength_8Transfers ((uint16_t)0x0700)
#define | TIM_DMABurstLength_9Transfers ((uint16_t)0x0800)

Define Documentation

#define IS_TIM_DMA_LENGTH ( LENGTH )
Value:
(((LENGTH) == TIM_DMABurstLength_1Transfer) || \
                                   ((LENGTH) == TIM_DMABurstLength_2Transfers) || \
                                   ((LENGTH) == TIM_DMABurstLength_3Transfers) || \
                                   ((LENGTH) == TIM_DMABurstLength_4Transfers) || \
                                   ((LENGTH) == TIM_DMABurstLength_5Transfers) || \
                                   ((LENGTH) == TIM_DMABurstLength_6Transfers) || \
                                   ((LENGTH) == TIM_DMABurstLength_7Transfers) || \
                                   ((LENGTH) == TIM_DMABurstLength_8Transfers) || \
                                   ((LENGTH) == TIM_DMABurstLength_9Transfers) || \
                                   ((LENGTH) == TIM_DMABurstLength_10Transfers) || \
                                   ((LENGTH) == TIM_DMABurstLength_11Transfers) || \
                                   ((LENGTH) == TIM_DMABurstLength_12Transfers) || \
                                   ((LENGTH) == TIM_DMABurstLength_13Transfers) || \
                                   ((LENGTH) == TIM_DMABurstLength_14Transfers) || \
                                   ((LENGTH) == TIM_DMABurstLength_15Transfers) || \
                                   ((LENGTH) == TIM_DMABurstLength_16Transfers) || \
                                   ((LENGTH) == TIM_DMABurstLength_17Transfers) || \
                                   ((LENGTH) == TIM_DMABurstLength_18Transfers))

Definition at line 691 of file stm32f10x_tim.h.

Referenced by TIM_DMAConfig().

#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900)

Definition at line 682 of file stm32f10x_tim.h.

#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00)

Definition at line 683 of file stm32f10x_tim.h.

#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00)

Definition at line 684 of file stm32f10x_tim.h.

#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00)

Definition at line 685 of file stm32f10x_tim.h.

#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00)

Definition at line 686 of file stm32f10x_tim.h.

#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00)

Definition at line 687 of file stm32f10x_tim.h.

#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00)

Definition at line 688 of file stm32f10x_tim.h.

#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000)

Definition at line 689 of file stm32f10x_tim.h.

#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100)

Definition at line 690 of file stm32f10x_tim.h.

#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000)

Definition at line 673 of file stm32f10x_tim.h.

#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100)

Definition at line 674 of file stm32f10x_tim.h.

#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200)

Definition at line 675 of file stm32f10x_tim.h.

Referenced by main().

#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300)

Definition at line 676 of file stm32f10x_tim.h.

#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400)

Definition at line 677 of file stm32f10x_tim.h.

#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500)

Definition at line 678 of file stm32f10x_tim.h.

#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600)

Definition at line 679 of file stm32f10x_tim.h.

#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700)

Definition at line 680 of file stm32f10x_tim.h.

#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800)

Definition at line 681 of file stm32f10x_tim.h.


STM32F10x Standard Peripherals Firmware Library: TIM_DMA_sources

Defines

TIM_DMA_sources

TIM_Exported_Types

Defines

#define | IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000))
#define | TIM_DMA_CC1 ((uint16_t)0x0200)
#define | TIM_DMA_CC2 ((uint16_t)0x0400)
#define | TIM_DMA_CC3 ((uint16_t)0x0800)
#define | TIM_DMA_CC4 ((uint16_t)0x1000)
#define | TIM_DMA_COM ((uint16_t)0x2000)
#define | TIM_DMA_Trigger ((uint16_t)0x4000)
#define | TIM_DMA_Update ((uint16_t)0x0100)

Define Documentation

#define IS_TIM_DMA_SOURCE ( SOURCE ) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000))

Definition at line 724 of file stm32f10x_tim.h.

Referenced by TIM_DMACmd().

#define TIM_DMA_CC1 ((uint16_t)0x0200)

Definition at line 718 of file stm32f10x_tim.h.

#define TIM_DMA_CC2 ((uint16_t)0x0400)

Definition at line 719 of file stm32f10x_tim.h.

#define TIM_DMA_CC3 ((uint16_t)0x0800)

Definition at line 720 of file stm32f10x_tim.h.

#define TIM_DMA_CC4 ((uint16_t)0x1000)

Definition at line 721 of file stm32f10x_tim.h.

#define TIM_DMA_COM ((uint16_t)0x2000)

Definition at line 722 of file stm32f10x_tim.h.

#define TIM_DMA_Trigger ((uint16_t)0x4000)

Definition at line 723 of file stm32f10x_tim.h.

#define TIM_DMA_Update ((uint16_t)0x0100)

Definition at line 717 of file stm32f10x_tim.h.

Referenced by main().


STM32F10x Standard Peripherals Firmware Library: TIM_External_Trigger_Prescaler

Defines

TIM_External_Trigger_Prescaler

TIM_Exported_Types

Defines

#define | IS_TIM_EXT_PRESCALER(PRESCALER)
#define | TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000)
#define | TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000)
#define | TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000)
#define | TIM_ExtTRGPSC_OFF ((uint16_t)0x0000)

Define Documentation

#define IS_TIM_EXT_PRESCALER ( PRESCALER )
Value:
(((PRESCALER) == TIM_ExtTRGPSC_OFF) || \
                                         ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \
                                         ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \
                                         ((PRESCALER) == TIM_ExtTRGPSC_DIV8))

Definition at line 738 of file stm32f10x_tim.h.

Referenced by TIM_ETRClockMode1Config(), TIM_ETRClockMode2Config(), and TIM_ETRConfig().

#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000)

Definition at line 735 of file stm32f10x_tim.h.

#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000)

Definition at line 736 of file stm32f10x_tim.h.

#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000)

Definition at line 737 of file stm32f10x_tim.h.

#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000)

Definition at line 734 of file stm32f10x_tim.h.


STM32F10x Standard Peripherals Firmware Library: TIM_Internal_Trigger_Selection

Defines

TIM_Internal_Trigger_Selection

TIM_Exported_Types

Defines

#define | IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION)
#define | IS_TIM_TRIGGER_SELECTION(SELECTION)
#define | TIM_TS_ETRF ((uint16_t)0x0070)
#define | TIM_TS_ITR0 ((uint16_t)0x0000)
#define | TIM_TS_ITR1 ((uint16_t)0x0010)
#define | TIM_TS_ITR2 ((uint16_t)0x0020)
#define | TIM_TS_ITR3 ((uint16_t)0x0030)
#define | TIM_TS_TI1F_ED ((uint16_t)0x0040)
#define | TIM_TS_TI1FP1 ((uint16_t)0x0050)
#define | TIM_TS_TI2FP2 ((uint16_t)0x0060)

Define Documentation

#define IS_TIM_INTERNAL_TRIGGER_SELECTION ( SELECTION )
Value:
(((SELECTION) == TIM_TS_ITR0) || \
                                                      ((SELECTION) == TIM_TS_ITR1) || \
                                                      ((SELECTION) == TIM_TS_ITR2) || \
                                                      ((SELECTION) == TIM_TS_ITR3))

Definition at line 766 of file stm32f10x_tim.h.

Referenced by TIM_ITRxExternalClockConfig().

#define IS_TIM_TRIGGER_SELECTION ( SELECTION )
Value:
(((SELECTION) == TIM_TS_ITR0) || \
                                             ((SELECTION) == TIM_TS_ITR1) || \
                                             ((SELECTION) == TIM_TS_ITR2) || \
                                             ((SELECTION) == TIM_TS_ITR3) || \
                                             ((SELECTION) == TIM_TS_TI1F_ED) || \
                                             ((SELECTION) == TIM_TS_TI1FP1) || \
                                             ((SELECTION) == TIM_TS_TI2FP2) || \
                                             ((SELECTION) == TIM_TS_ETRF))

Definition at line 758 of file stm32f10x_tim.h.

Referenced by TIM_SelectInputTrigger().

#define TIM_TS_ETRF ((uint16_t)0x0070)

Definition at line 757 of file stm32f10x_tim.h.

Referenced by TIM_ETRClockMode1Config().

#define TIM_TS_ITR0 ((uint16_t)0x0000)

Definition at line 750 of file stm32f10x_tim.h.

Referenced by main().

#define TIM_TS_ITR1 ((uint16_t)0x0010)

Definition at line 751 of file stm32f10x_tim.h.

Referenced by main().

#define TIM_TS_ITR2 ((uint16_t)0x0020)

Definition at line 752 of file stm32f10x_tim.h.

Referenced by main().

#define TIM_TS_ITR3 ((uint16_t)0x0030)

Definition at line 753 of file stm32f10x_tim.h.

#define TIM_TS_TI1F_ED ((uint16_t)0x0040)

Definition at line 754 of file stm32f10x_tim.h.

#define TIM_TS_TI1FP1 ((uint16_t)0x0050)

Definition at line 755 of file stm32f10x_tim.h.

#define TIM_TS_TI2FP2 ((uint16_t)0x0060)

Definition at line 756 of file stm32f10x_tim.h.

Referenced by main().


STM32F10x Standard Peripherals Firmware Library: TIM_TIx_External_Clock_Source

Defines

TIM_TIx_External_Clock_Source

TIM_Exported_Types

Defines

#define | IS_TIM_TIXCLK_SOURCE(SOURCE)
#define | TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050)
#define | TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040)
#define | TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060)

Define Documentation

#define IS_TIM_TIXCLK_SOURCE ( SOURCE )
Value:
(((SOURCE) == TIM_TIxExternalCLK1Source_TI1) || \
                                      ((SOURCE) == TIM_TIxExternalCLK1Source_TI2) || \
                                      ((SOURCE) == TIM_TIxExternalCLK1Source_TI1ED))

Definition at line 781 of file stm32f10x_tim.h.

Referenced by TIM_TIxExternalClockConfig().

#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050)

Definition at line 778 of file stm32f10x_tim.h.

#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040)

Definition at line 780 of file stm32f10x_tim.h.

#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060)

Definition at line 779 of file stm32f10x_tim.h.

Referenced by TIM_TIxExternalClockConfig().


STM32F10x Standard Peripherals Firmware Library: TIM_External_Trigger_Polarity

Defines

TIM_External_Trigger_Polarity

TIM_Exported_Types

Defines

#define | IS_TIM_EXT_POLARITY(POLARITY)
#define | TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000)
#define | TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000)

Define Documentation

#define IS_TIM_EXT_POLARITY ( POLARITY )
Value:
(((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \
                                       ((POLARITY) == TIM_ExtTRGPolarity_NonInverted))

Definition at line 793 of file stm32f10x_tim.h.

Referenced by TIM_ETRClockMode1Config(), TIM_ETRClockMode2Config(), and TIM_ETRConfig().

#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000)

Definition at line 791 of file stm32f10x_tim.h.

#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000)

Definition at line 792 of file stm32f10x_tim.h.


STM32F10x Standard Peripherals Firmware Library: TIM_Prescaler_Reload_Mode

Defines

TIM_Prescaler_Reload_Mode

TIM_Exported_Types

Defines

#define | IS_TIM_PRESCALER_RELOAD(RELOAD)
#define | TIM_PSCReloadMode_Immediate ((uint16_t)0x0001)
#define | TIM_PSCReloadMode_Update ((uint16_t)0x0000)

Define Documentation

#define IS_TIM_PRESCALER_RELOAD ( RELOAD )
Value:
(((RELOAD) == TIM_PSCReloadMode_Update) || \
                                         ((RELOAD) == TIM_PSCReloadMode_Immediate))

Definition at line 805 of file stm32f10x_tim.h.

Referenced by TIM_PrescalerConfig().

#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001)

Definition at line 804 of file stm32f10x_tim.h.

Referenced by main(), TIM5_ConfigForLSI(), TIM_Config(), and TIM_TimeBaseInit().

#define TIM_PSCReloadMode_Update ((uint16_t)0x0000)

Definition at line 803 of file stm32f10x_tim.h.

Referenced by main().


STM32F10x Standard Peripherals Firmware Library: TIM_Forced_Action

Defines

TIM_Forced_Action

TIM_Exported_Types

Defines

#define | IS_TIM_FORCED_ACTION(ACTION)
#define | TIM_ForcedAction_Active ((uint16_t)0x0050)
#define | TIM_ForcedAction_InActive ((uint16_t)0x0040)

Define Documentation

#define IS_TIM_FORCED_ACTION ( ACTION )
Value:
(((ACTION) == TIM_ForcedAction_Active) || \
                                      ((ACTION) == TIM_ForcedAction_InActive))

Definition at line 817 of file stm32f10x_tim.h.

Referenced by TIM_ForcedOC1Config(), TIM_ForcedOC2Config(), TIM_ForcedOC3Config(), and TIM_ForcedOC4Config().

#define TIM_ForcedAction_Active ((uint16_t)0x0050)

Definition at line 815 of file stm32f10x_tim.h.

#define TIM_ForcedAction_InActive ((uint16_t)0x0040)

Definition at line 816 of file stm32f10x_tim.h.


STM32F10x Standard Peripherals Firmware Library: TIM_Encoder_Mode

Defines

TIM_Encoder_Mode

TIM_Exported_Types

Defines

#define | IS_TIM_ENCODER_MODE(MODE)
#define | TIM_EncoderMode_TI1 ((uint16_t)0x0001)
#define | TIM_EncoderMode_TI12 ((uint16_t)0x0003)
#define | TIM_EncoderMode_TI2 ((uint16_t)0x0002)

Define Documentation

#define IS_TIM_ENCODER_MODE ( MODE )
Value:
(((MODE) == TIM_EncoderMode_TI1) || \
                                   ((MODE) == TIM_EncoderMode_TI2) || \
                                   ((MODE) == TIM_EncoderMode_TI12))

Definition at line 830 of file stm32f10x_tim.h.

Referenced by TIM_EncoderInterfaceConfig().

#define TIM_EncoderMode_TI1 ((uint16_t)0x0001)

Definition at line 827 of file stm32f10x_tim.h.

#define TIM_EncoderMode_TI12 ((uint16_t)0x0003)

Definition at line 829 of file stm32f10x_tim.h.

#define TIM_EncoderMode_TI2 ((uint16_t)0x0002)

Definition at line 828 of file stm32f10x_tim.h.


STM32F10x Standard Peripherals Firmware Library: TIM_Event_Source

Defines

TIM_Event_Source

TIM_Exported_Types

Defines

#define | IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000))
#define | TIM_EventSource_Break ((uint16_t)0x0080)
#define | TIM_EventSource_CC1 ((uint16_t)0x0002)
#define | TIM_EventSource_CC2 ((uint16_t)0x0004)
#define | TIM_EventSource_CC3 ((uint16_t)0x0008)
#define | TIM_EventSource_CC4 ((uint16_t)0x0010)
#define | TIM_EventSource_COM ((uint16_t)0x0020)
#define | TIM_EventSource_Trigger ((uint16_t)0x0040)
#define | TIM_EventSource_Update ((uint16_t)0x0001)

Define Documentation

#define IS_TIM_EVENT_SOURCE ( SOURCE ) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000))

Definition at line 850 of file stm32f10x_tim.h.

Referenced by TIM_GenerateEvent().

#define TIM_EventSource_Break ((uint16_t)0x0080)

Definition at line 849 of file stm32f10x_tim.h.

#define TIM_EventSource_CC1 ((uint16_t)0x0002)

Definition at line 843 of file stm32f10x_tim.h.

#define TIM_EventSource_CC2 ((uint16_t)0x0004)

Definition at line 844 of file stm32f10x_tim.h.

#define TIM_EventSource_CC3 ((uint16_t)0x0008)

Definition at line 845 of file stm32f10x_tim.h.

#define TIM_EventSource_CC4 ((uint16_t)0x0010)

Definition at line 846 of file stm32f10x_tim.h.

#define TIM_EventSource_COM ((uint16_t)0x0020)

Definition at line 847 of file stm32f10x_tim.h.

Referenced by SysTick_Handler().

#define TIM_EventSource_Trigger ((uint16_t)0x0040)

Definition at line 848 of file stm32f10x_tim.h.

#define TIM_EventSource_Update ((uint16_t)0x0001)

Definition at line 842 of file stm32f10x_tim.h.


STM32F10x Standard Peripherals Firmware Library: TIM_Update_Source

Defines

TIM_Update_Source

TIM_Exported_Types

Defines

#define | IS_TIM_UPDATE_SOURCE(SOURCE)
#define | TIM_UpdateSource_Global ((uint16_t)0x0000)
#define | TIM_UpdateSource_Regular ((uint16_t)0x0001)

Define Documentation

#define IS_TIM_UPDATE_SOURCE ( SOURCE )
Value:
(((SOURCE) == TIM_UpdateSource_Global) || \
                                      ((SOURCE) == TIM_UpdateSource_Regular))

Definition at line 864 of file stm32f10x_tim.h.

Referenced by TIM_UpdateRequestConfig().

#define TIM_UpdateSource_Global ((uint16_t)0x0000)

Source of update is the counter overflow/underflow or the setting of UG bit, or an update generation through the slave mode controller.

Definition at line 860 of file stm32f10x_tim.h.

Referenced by TIM_UpdateRequestConfig().

#define TIM_UpdateSource_Regular ((uint16_t)0x0001)

Source of update is counter overflow/underflow.

Definition at line 863 of file stm32f10x_tim.h.


STM32F10x Standard Peripherals Firmware Library: TIM_Output_Compare_Preload_State

Defines

TIM_Output_Compare_Preload_State

TIM_Exported_Types

Defines

#define | IS_TIM_OCPRELOAD_STATE(STATE)
#define | TIM_OCPreload_Disable ((uint16_t)0x0000)
#define | TIM_OCPreload_Enable ((uint16_t)0x0008)

Define Documentation

#define IS_TIM_OCPRELOAD_STATE ( STATE )
Value:
(((STATE) == TIM_OCPreload_Enable) || \
                                       ((STATE) == TIM_OCPreload_Disable))

Definition at line 876 of file stm32f10x_tim.h.

Referenced by TIM_OC1PreloadConfig(), TIM_OC2PreloadConfig(), TIM_OC3PreloadConfig(), and TIM_OC4PreloadConfig().

#define TIM_OCPreload_Disable ((uint16_t)0x0000)

Definition at line 875 of file stm32f10x_tim.h.

Referenced by main().

#define TIM_OCPreload_Enable ((uint16_t)0x0008)

Definition at line 874 of file stm32f10x_tim.h.

Referenced by main().


STM32F10x Standard Peripherals Firmware Library: TIM_Output_Compare_Fast_State

Defines

TIM_Output_Compare_Fast_State

TIM_Exported_Types

Defines

#define | IS_TIM_OCFAST_STATE(STATE)
#define | TIM_OCFast_Disable ((uint16_t)0x0000)
#define | TIM_OCFast_Enable ((uint16_t)0x0004)

Define Documentation

#define IS_TIM_OCFAST_STATE ( STATE )
Value:
(((STATE) == TIM_OCFast_Enable) || \
                                    ((STATE) == TIM_OCFast_Disable))

Definition at line 888 of file stm32f10x_tim.h.

Referenced by TIM_OC1FastConfig(), TIM_OC2FastConfig(), TIM_OC3FastConfig(), and TIM_OC4FastConfig().

#define TIM_OCFast_Disable ((uint16_t)0x0000)

Definition at line 887 of file stm32f10x_tim.h.

#define TIM_OCFast_Enable ((uint16_t)0x0004)

Definition at line 886 of file stm32f10x_tim.h.


STM32F10x Standard Peripherals Firmware Library: TIM_Output_Compare_Clear_State

Defines

TIM_Output_Compare_Clear_State

TIM_Exported_Types

Defines

#define | IS_TIM_OCCLEAR_STATE(STATE)
#define | TIM_OCClear_Disable ((uint16_t)0x0000)
#define | TIM_OCClear_Enable ((uint16_t)0x0080)

Define Documentation

#define IS_TIM_OCCLEAR_STATE ( STATE )
Value:
(((STATE) == TIM_OCClear_Enable) || \
                                     ((STATE) == TIM_OCClear_Disable))

Definition at line 901 of file stm32f10x_tim.h.

Referenced by TIM_ClearOC1Ref(), TIM_ClearOC2Ref(), TIM_ClearOC3Ref(), and TIM_ClearOC4Ref().

#define TIM_OCClear_Disable ((uint16_t)0x0000)

Definition at line 900 of file stm32f10x_tim.h.

#define TIM_OCClear_Enable ((uint16_t)0x0080)

Definition at line 899 of file stm32f10x_tim.h.


STM32F10x Standard Peripherals Firmware Library: TIM_Trigger_Output_Source

Defines

TIM_Trigger_Output_Source

TIM_Exported_Types

Defines

#define | IS_TIM_TRGO_SOURCE(SOURCE)
#define | TIM_TRGOSource_Enable ((uint16_t)0x0010)
#define | TIM_TRGOSource_OC1 ((uint16_t)0x0030)
#define | TIM_TRGOSource_OC1Ref ((uint16_t)0x0040)
#define | TIM_TRGOSource_OC2Ref ((uint16_t)0x0050)
#define | TIM_TRGOSource_OC3Ref ((uint16_t)0x0060)
#define | TIM_TRGOSource_OC4Ref ((uint16_t)0x0070)
#define | TIM_TRGOSource_Reset ((uint16_t)0x0000)
#define | TIM_TRGOSource_Update ((uint16_t)0x0020)

Define Documentation

#define IS_TIM_TRGO_SOURCE ( SOURCE )
Value:
(((SOURCE) == TIM_TRGOSource_Reset) || \
                                    ((SOURCE) == TIM_TRGOSource_Enable) || \
                                    ((SOURCE) == TIM_TRGOSource_Update) || \
                                    ((SOURCE) == TIM_TRGOSource_OC1) || \
                                    ((SOURCE) == TIM_TRGOSource_OC1Ref) || \
                                    ((SOURCE) == TIM_TRGOSource_OC2Ref) || \
                                    ((SOURCE) == TIM_TRGOSource_OC3Ref) || \
                                    ((SOURCE) == TIM_TRGOSource_OC4Ref))

Definition at line 919 of file stm32f10x_tim.h.

Referenced by TIM_SelectOutputTrigger().

#define TIM_TRGOSource_Enable ((uint16_t)0x0010)

Definition at line 912 of file stm32f10x_tim.h.

Referenced by main().

#define TIM_TRGOSource_OC1 ((uint16_t)0x0030)

Definition at line 914 of file stm32f10x_tim.h.

#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040)

Definition at line 915 of file stm32f10x_tim.h.

#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050)

Definition at line 916 of file stm32f10x_tim.h.

#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060)

Definition at line 917 of file stm32f10x_tim.h.

#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070)

Definition at line 918 of file stm32f10x_tim.h.

#define TIM_TRGOSource_Reset ((uint16_t)0x0000)

Definition at line 911 of file stm32f10x_tim.h.

#define TIM_TRGOSource_Update ((uint16_t)0x0020)

Definition at line 913 of file stm32f10x_tim.h.

Referenced by main().


STM32F10x Standard Peripherals Firmware Library: TIM_Slave_Mode

Defines

TIM_Slave_Mode

TIM_Exported_Types

Defines

#define | IS_TIM_SLAVE_MODE(MODE)
#define | TIM_SlaveMode_External1 ((uint16_t)0x0007)
#define | TIM_SlaveMode_Gated ((uint16_t)0x0005)
#define | TIM_SlaveMode_Reset ((uint16_t)0x0004)
#define | TIM_SlaveMode_Trigger ((uint16_t)0x0006)

Define Documentation

#define IS_TIM_SLAVE_MODE ( MODE )
Value:
(((MODE) == TIM_SlaveMode_Reset) || \
                                 ((MODE) == TIM_SlaveMode_Gated) || \
                                 ((MODE) == TIM_SlaveMode_Trigger) || \
                                 ((MODE) == TIM_SlaveMode_External1))

Definition at line 939 of file stm32f10x_tim.h.

Referenced by TIM_SelectSlaveMode().

#define TIM_SlaveMode_External1 ((uint16_t)0x0007)

Definition at line 938 of file stm32f10x_tim.h.

Referenced by TIM_ETRClockMode1Config(), TIM_ITRxExternalClockConfig(), and TIM_TIxExternalClockConfig().

#define TIM_SlaveMode_Gated ((uint16_t)0x0005)

Definition at line 936 of file stm32f10x_tim.h.

Referenced by main().

#define TIM_SlaveMode_Reset ((uint16_t)0x0004)

Definition at line 935 of file stm32f10x_tim.h.

Referenced by main().

#define TIM_SlaveMode_Trigger ((uint16_t)0x0006)

Definition at line 937 of file stm32f10x_tim.h.

Referenced by main().


STM32F10x Standard Peripherals Firmware Library: TIM_Master_Slave_Mode

Defines

TIM_Master_Slave_Mode

TIM_Exported_Types

Defines

#define | IS_TIM_MSM_STATE(STATE)
#define | TIM_MasterSlaveMode_Disable ((uint16_t)0x0000)
#define | TIM_MasterSlaveMode_Enable ((uint16_t)0x0080)

Define Documentation

#define IS_TIM_MSM_STATE ( STATE )
Value:
(((STATE) == TIM_MasterSlaveMode_Enable) || \
                                 ((STATE) == TIM_MasterSlaveMode_Disable))

Definition at line 953 of file stm32f10x_tim.h.

Referenced by TIM_SelectMasterSlaveMode().

#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000)

Definition at line 952 of file stm32f10x_tim.h.

#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080)

Definition at line 951 of file stm32f10x_tim.h.

Referenced by main().


STM32F10x Standard Peripherals Firmware Library: TIM_Flags

Defines

TIM_Flags

TIM_Exported_Types

Defines

#define | IS_TIM_CLEAR_FLAG(TIM_FLAG) ((((TIM_FLAG) & (uint16_t)0xE100) == 0x0000) && ((TIM_FLAG) != 0x0000))
#define | IS_TIM_GET_FLAG(FLAG)
#define | TIM_FLAG_Break ((uint16_t)0x0080)
#define | TIM_FLAG_CC1 ((uint16_t)0x0002)
#define | TIM_FLAG_CC1OF ((uint16_t)0x0200)
#define | TIM_FLAG_CC2 ((uint16_t)0x0004)
#define | TIM_FLAG_CC2OF ((uint16_t)0x0400)
#define | TIM_FLAG_CC3 ((uint16_t)0x0008)
#define | TIM_FLAG_CC3OF ((uint16_t)0x0800)
#define | TIM_FLAG_CC4 ((uint16_t)0x0010)
#define | TIM_FLAG_CC4OF ((uint16_t)0x1000)
#define | TIM_FLAG_COM ((uint16_t)0x0020)
#define | TIM_FLAG_Trigger ((uint16_t)0x0040)
#define | TIM_FLAG_Update ((uint16_t)0x0001)

Define Documentation

#define IS_TIM_CLEAR_FLAG ( TIM_FLAG ) ((((TIM_FLAG) & (uint16_t)0xE100) == 0x0000) && ((TIM_FLAG) != 0x0000))

Definition at line 989 of file stm32f10x_tim.h.

Referenced by TIM_ClearFlag().

#define IS_TIM_GET_FLAG ( FLAG )
Value:
(((FLAG) == TIM_FLAG_Update) || \
                               ((FLAG) == TIM_FLAG_CC1) || \
                               ((FLAG) == TIM_FLAG_CC2) || \
                               ((FLAG) == TIM_FLAG_CC3) || \
                               ((FLAG) == TIM_FLAG_CC4) || \
                               ((FLAG) == TIM_FLAG_COM) || \
                               ((FLAG) == TIM_FLAG_Trigger) || \
                               ((FLAG) == TIM_FLAG_Break) || \
                               ((FLAG) == TIM_FLAG_CC1OF) || \
                               ((FLAG) == TIM_FLAG_CC2OF) || \
                               ((FLAG) == TIM_FLAG_CC3OF) || \
                               ((FLAG) == TIM_FLAG_CC4OF))

Definition at line 975 of file stm32f10x_tim.h.

Referenced by TIM_GetFlagStatus().

#define TIM_FLAG_Break ((uint16_t)0x0080)

Definition at line 970 of file stm32f10x_tim.h.

#define TIM_FLAG_CC1 ((uint16_t)0x0002)

Definition at line 964 of file stm32f10x_tim.h.

#define TIM_FLAG_CC1OF ((uint16_t)0x0200)

Definition at line 971 of file stm32f10x_tim.h.

#define TIM_FLAG_CC2 ((uint16_t)0x0004)

Definition at line 965 of file stm32f10x_tim.h.

#define TIM_FLAG_CC2OF ((uint16_t)0x0400)

Definition at line 972 of file stm32f10x_tim.h.

#define TIM_FLAG_CC3 ((uint16_t)0x0008)

Definition at line 966 of file stm32f10x_tim.h.

#define TIM_FLAG_CC3OF ((uint16_t)0x0800)

Definition at line 973 of file stm32f10x_tim.h.

#define TIM_FLAG_CC4 ((uint16_t)0x0010)

Definition at line 967 of file stm32f10x_tim.h.

#define TIM_FLAG_CC4OF ((uint16_t)0x1000)

Definition at line 974 of file stm32f10x_tim.h.

#define TIM_FLAG_COM ((uint16_t)0x0020)

Definition at line 968 of file stm32f10x_tim.h.

#define TIM_FLAG_Trigger ((uint16_t)0x0040)

Definition at line 969 of file stm32f10x_tim.h.

#define TIM_FLAG_Update ((uint16_t)0x0001)

Definition at line 963 of file stm32f10x_tim.h.

Referenced by TIM_Config().


STM32F10x Standard Peripherals Firmware Library: TIM_Input_Capture_Filer_Value

Defines

TIM_Input_Capture_Filer_Value

TIM_Exported_Types

Defines

#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)

Define Documentation

#define IS_TIM_IC_FILTER ( ICFILTER ) ((ICFILTER) <= 0xF)

Definition at line 998 of file stm32f10x_tim.h.

Referenced by TIM_ICInit(), and TIM_TIxExternalClockConfig().


STM32F10x Standard Peripherals Firmware Library: TIM_External_Trigger_Filter

Defines

TIM_External_Trigger_Filter

TIM_Exported_Types

Defines

#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF)

Define Documentation

#define IS_TIM_EXT_FILTER ( EXTFILTER ) ((EXTFILTER) <= 0xF)

Definition at line 1007 of file stm32f10x_tim.h.

Referenced by TIM_ETRClockMode1Config(), TIM_ETRClockMode2Config(), and TIM_ETRConfig().


STM32F10x Standard Peripherals Firmware Library: TIM_Legacy

Defines

TIM_Legacy

TIM_Exported_Types

Defines

#define | TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers
#define | TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers
#define | TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers
#define | TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers
#define | TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers
#define | TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers
#define | TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers
#define | TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers
#define | TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers
#define | TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer
#define | TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers
#define | TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers
#define | TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers
#define | TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers
#define | TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers
#define | TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers
#define | TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers
#define | TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers

Define Documentation

#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers

Definition at line 1025 of file stm32f10x_tim.h.

#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers

Definition at line 1026 of file stm32f10x_tim.h.

#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers

Definition at line 1027 of file stm32f10x_tim.h.

#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers

Definition at line 1028 of file stm32f10x_tim.h.

#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers

Definition at line 1029 of file stm32f10x_tim.h.

#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers

Definition at line 1030 of file stm32f10x_tim.h.

#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers

Definition at line 1031 of file stm32f10x_tim.h.

#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers

Definition at line 1032 of file stm32f10x_tim.h.

#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers

Definition at line 1033 of file stm32f10x_tim.h.

#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer

Definition at line 1016 of file stm32f10x_tim.h.

#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers

Definition at line 1017 of file stm32f10x_tim.h.

#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers

Definition at line 1018 of file stm32f10x_tim.h.

#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers

Definition at line 1019 of file stm32f10x_tim.h.

#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers

Definition at line 1020 of file stm32f10x_tim.h.

#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers

Definition at line 1021 of file stm32f10x_tim.h.

#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers

Definition at line 1022 of file stm32f10x_tim.h.

#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers

Definition at line 1023 of file stm32f10x_tim.h.

#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers

Definition at line 1024 of file stm32f10x_tim.h.


STM32F10x Standard Peripherals Firmware Library: TIM_BDTRInitTypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

TIM_BDTRInitTypeDef Struct Reference
TIM_Exported_Types

BDTR structure definition. More...

#include <stm32f10x_tim.h>

Data Fields

uint16_t | TIM_AutomaticOutput
uint16_t | TIM_Break
uint16_t | TIM_BreakPolarity
uint16_t | TIM_DeadTime
uint16_t | TIM_LOCKLevel
uint16_t | TIM_OSSIState
uint16_t | TIM_OSSRState

Detailed Description

BDTR structure definition.

Note:
This structure is used only with TIM1 and TIM8.

Definition at line 139 of file stm32f10x_tim.h.

Field Documentation

uint16_t TIM_BDTRInitTypeDef::TIM_AutomaticOutput

Specifies whether the TIM Automatic Output feature is enabled or not. This parameter can be a value of TIM_AOE_Bit_Set_Reset

Definition at line 161 of file stm32f10x_tim.h.

Referenced by main(), TIM_BDTRConfig(), and TIM_BDTRStructInit().

uint16_t TIM_BDTRInitTypeDef::TIM_Break

Specifies whether the TIM Break input is enabled or not. This parameter can be a value of Break_Input_enable_disable

Definition at line 155 of file stm32f10x_tim.h.

Referenced by main(), TIM_BDTRConfig(), and TIM_BDTRStructInit().

uint16_t TIM_BDTRInitTypeDef::TIM_BreakPolarity

Specifies the TIM Break Input pin polarity. This parameter can be a value of Break_Polarity

Definition at line 158 of file stm32f10x_tim.h.

Referenced by main(), TIM_BDTRConfig(), and TIM_BDTRStructInit().

uint16_t TIM_BDTRInitTypeDef::TIM_DeadTime

Specifies the delay time between the switching-off and the switching-on of the outputs. This parameter can be a number between 0x00 and 0xFF

Definition at line 151 of file stm32f10x_tim.h.

Referenced by main(), TIM_BDTRConfig(), and TIM_BDTRStructInit().

uint16_t TIM_BDTRInitTypeDef::TIM_LOCKLevel

Specifies the LOCK level parameters. This parameter can be a value of Lock_level

Definition at line 148 of file stm32f10x_tim.h.

Referenced by main(), TIM_BDTRConfig(), and TIM_BDTRStructInit().

uint16_t TIM_BDTRInitTypeDef::TIM_OSSIState

Specifies the Off-State used in Idle state. This parameter can be a value of OSSI_Off_State_Selection_for_Idle_mode_state

Definition at line 145 of file stm32f10x_tim.h.

Referenced by main(), TIM_BDTRConfig(), and TIM_BDTRStructInit().

uint16_t TIM_BDTRInitTypeDef::TIM_OSSRState

Specifies the Off-State selection used in Run mode. This parameter can be a value of OSSR_Off_State_Selection_for_Run_mode_state

Definition at line 142 of file stm32f10x_tim.h.

Referenced by main(), TIM_BDTRConfig(), and TIM_BDTRStructInit().

The documentation for this struct was generated from the following file:
  • stm32f10x_tim.h


STM32F10x Standard Peripherals Firmware Library: TIM_ICInitTypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

TIM_ICInitTypeDef Struct Reference
TIM_Exported_Types

TIM Input Capture Init structure definition. More...

#include <stm32f10x_tim.h>

Data Fields

uint16_t | TIM_Channel
uint16_t | TIM_ICFilter
uint16_t | TIM_ICPolarity
uint16_t | TIM_ICPrescaler
uint16_t | TIM_ICSelection

Detailed Description

TIM Input Capture Init structure definition.

Definition at line 115 of file stm32f10x_tim.h.

Field Documentation

uint16_t TIM_ICInitTypeDef::TIM_Channel

Specifies the TIM channel. This parameter can be a value of TIM_Channel

Definition at line 118 of file stm32f10x_tim.h.

Referenced by main(), TIM5_ConfigForLSI(), TIM_ICInit(), TIM_ICStructInit(), and TIM_PWMIConfig().

uint16_t TIM_ICInitTypeDef::TIM_ICFilter

Specifies the input capture filter. This parameter can be a number between 0x0 and 0xF

Definition at line 130 of file stm32f10x_tim.h.

Referenced by main(), TIM5_ConfigForLSI(), TIM_ICInit(), TIM_ICStructInit(), and TIM_PWMIConfig().

uint16_t TIM_ICInitTypeDef::TIM_ICPolarity

Specifies the active edge of the input signal. This parameter can be a value of TIM_Input_Capture_Polarity

Definition at line 121 of file stm32f10x_tim.h.

Referenced by main(), TIM5_ConfigForLSI(), TIM_ICInit(), TIM_ICStructInit(), and TIM_PWMIConfig().

uint16_t TIM_ICInitTypeDef::TIM_ICPrescaler

Specifies the Input Capture Prescaler. This parameter can be a value of TIM_Input_Capture_Prescaler

Definition at line 127 of file stm32f10x_tim.h.

Referenced by main(), TIM5_ConfigForLSI(), TIM_ICInit(), TIM_ICStructInit(), and TIM_PWMIConfig().

uint16_t TIM_ICInitTypeDef::TIM_ICSelection

Specifies the input. This parameter can be a value of TIM_Input_Capture_Selection

Definition at line 124 of file stm32f10x_tim.h.

Referenced by main(), TIM5_ConfigForLSI(), TIM_ICInit(), TIM_ICStructInit(), and TIM_PWMIConfig().

The documentation for this struct was generated from the following file:
  • stm32f10x_tim.h


STM32F10x Standard Peripherals Firmware Library: TIM_OCInitTypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

TIM_OCInitTypeDef Struct Reference
TIM_Exported_Types

TIM Output Compare Init structure definition. More...

#include <stm32f10x_tim.h>

Data Fields

uint16_t | TIM_OCIdleState
uint16_t | TIM_OCMode
uint16_t | TIM_OCNIdleState
uint16_t | TIM_OCNPolarity
uint16_t | TIM_OCPolarity
uint16_t | TIM_OutputNState
uint16_t | TIM_OutputState
uint16_t | TIM_Pulse

Detailed Description

TIM Output Compare Init structure definition.

Definition at line 80 of file stm32f10x_tim.h.

Field Documentation

uint16_t TIM_OCInitTypeDef::TIM_OCIdleState

Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of TIM_Output_Compare_Idle_State

Note:
This parameter is valid only for TIM1 and TIM8.

Definition at line 102 of file stm32f10x_tim.h.

Referenced by main(), TIM_OC1Init(), TIM_OC2Init(), TIM_OC3Init(), TIM_OC4Init(), and TIM_OCStructInit().

uint16_t TIM_OCInitTypeDef::TIM_OCMode

Specifies the TIM mode. This parameter can be a value of TIM_Output_Compare_and_PWM_modes

Definition at line 82 of file stm32f10x_tim.h.

Referenced by main(), TIM_Config(), TIM_OC1Init(), TIM_OC2Init(), TIM_OC3Init(), TIM_OC4Init(), and TIM_OCStructInit().

uint16_t TIM_OCInitTypeDef::TIM_OCNIdleState

Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of TIM_Output_Compare_N_Idle_State

Note:
This parameter is valid only for TIM1 and TIM8.

Definition at line 106 of file stm32f10x_tim.h.

Referenced by main(), TIM_OC1Init(), TIM_OC2Init(), TIM_OC3Init(), and TIM_OCStructInit().

uint16_t TIM_OCInitTypeDef::TIM_OCNPolarity

Specifies the complementary output polarity. This parameter can be a value of TIM_Output_Compare_N_Polarity

Note:
This parameter is valid only for TIM1 and TIM8.

Definition at line 98 of file stm32f10x_tim.h.

Referenced by main(), TIM_OC1Init(), TIM_OC2Init(), TIM_OC3Init(), and TIM_OCStructInit().

uint16_t TIM_OCInitTypeDef::TIM_OCPolarity

Specifies the output polarity. This parameter can be a value of TIM_Output_Compare_Polarity

Definition at line 95 of file stm32f10x_tim.h.

Referenced by main(), TIM_OC1Init(), TIM_OC2Init(), TIM_OC3Init(), TIM_OC4Init(), and TIM_OCStructInit().

uint16_t TIM_OCInitTypeDef::TIM_OutputNState

Specifies the TIM complementary Output Compare state. This parameter can be a value of TIM_Output_Compare_N_state

Note:
This parameter is valid only for TIM1 and TIM8.

Definition at line 88 of file stm32f10x_tim.h.

Referenced by main(), TIM_OC1Init(), TIM_OC2Init(), TIM_OC3Init(), and TIM_OCStructInit().

uint16_t TIM_OCInitTypeDef::TIM_OutputState

Specifies the TIM Output Compare state. This parameter can be a value of TIM_Output_Compare_state

Definition at line 85 of file stm32f10x_tim.h.

Referenced by main(), TIM_OC1Init(), TIM_OC2Init(), TIM_OC3Init(), TIM_OC4Init(), and TIM_OCStructInit().

uint16_t TIM_OCInitTypeDef::TIM_Pulse

Specifies the pulse value to be loaded into the Capture Compare Register. This parameter can be a number between 0x0000 and 0xFFFF

Definition at line 92 of file stm32f10x_tim.h.

Referenced by main(), TIM_Config(), TIM_OC1Init(), TIM_OC2Init(), TIM_OC3Init(), TIM_OC4Init(), and TIM_OCStructInit().

The documentation for this struct was generated from the following file:
  • stm32f10x_tim.h


STM32F10x Standard Peripherals Firmware Library: TIM_TimeBaseInitTypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

TIM_TimeBaseInitTypeDef Struct Reference
TIM_Exported_Types

TIM Time Base Init structure definition. More...

#include <stm32f10x_tim.h>

Data Fields

uint16_t | TIM_ClockDivision
uint16_t | TIM_CounterMode
uint16_t | TIM_Period
uint16_t | TIM_Prescaler
uint8_t | TIM_RepetitionCounter

Detailed Description

TIM Time Base Init structure definition.

Note:
This structure is used with all TIMx except for TIM6 and TIM7.

Definition at line 51 of file stm32f10x_tim.h.

Field Documentation

uint16_t TIM_TimeBaseInitTypeDef::TIM_ClockDivision

Specifies the clock division. This parameter can be a value of TIM_Clock_Division_CKD

Definition at line 63 of file stm32f10x_tim.h.

Referenced by main(), TIM_Config(), TIM_TimeBaseInit(), and TIM_TimeBaseStructInit().

uint16_t TIM_TimeBaseInitTypeDef::TIM_CounterMode

Specifies the counter mode. This parameter can be a value of TIM_Counter_Mode

Definition at line 56 of file stm32f10x_tim.h.

Referenced by main(), TIM_Config(), TIM_TimeBaseInit(), and TIM_TimeBaseStructInit().

uint16_t TIM_TimeBaseInitTypeDef::TIM_Period

Specifies the period value to be loaded into the active Auto-Reload Register at the next update event. This parameter must be a number between 0x0000 and 0xFFFF.

Definition at line 59 of file stm32f10x_tim.h.

Referenced by main(), TIM_Config(), TIM_TimeBaseInit(), and TIM_TimeBaseStructInit().

uint16_t TIM_TimeBaseInitTypeDef::TIM_Prescaler

Specifies the prescaler value used to divide the TIM clock. This parameter can be a number between 0x0000 and 0xFFFF

Definition at line 53 of file stm32f10x_tim.h.

Referenced by main(), TIM_Config(), TIM_TimeBaseInit(), and TIM_TimeBaseStructInit().

uint8_t TIM_TimeBaseInitTypeDef::TIM_RepetitionCounter

Specifies the repetition counter value. Each time the RCR downcounter reaches zero, an update event is generated and counting restarts from the RCR value (N). This means in PWM mode that (N+1) corresponds to:

  • the number of PWM periods in edge-aligned mode
  • the number of half PWM period in center-aligned mode This parameter must be a number between 0x00 and 0xFF.
    Note:
    This parameter is valid only for TIM1 and TIM8.

Definition at line 66 of file stm32f10x_tim.h.

Referenced by main(), TIM_TimeBaseInit(), and TIM_TimeBaseStructInit().

The documentation for this struct was generated from the following file:
  • stm32f10x_tim.h


STM32F10x Standard Peripherals Firmware Library: TIM_Exported_Macros

TIM_Exported_Macros

TIM


STM32F10x Standard Peripherals Firmware Library: TIM_Exported_Functions

Functions

TIM_Exported_Functions

TIM

Functions

void | TIM_ARRPreloadConfig (TIM_TypeDef *TIMx, FunctionalState NewState)
Enables or disables TIMx peripheral Preload register on ARR.
void | TIM_BDTRConfig (TIM_TypeDef *TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)
Configures the: Break feature, dead time, Lock level, the OSSI, the OSSR State and the AOE(automatic output enable).
void | TIM_BDTRStructInit (TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)
Fills each TIM_BDTRInitStruct member with its default value.
void | TIM_CCPreloadControl (TIM_TypeDef *TIMx, FunctionalState NewState)
Sets or Resets the TIM peripheral Capture Compare Preload Control bit.
void | TIM_CCxCmd (TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx)
Enables or disables the TIM Capture Compare Channel x.
void | TIM_CCxNCmd (TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN)
Enables or disables the TIM Capture Compare Channel xN.
void | TIM_ClearFlag (TIM_TypeDef *TIMx, uint16_t TIM_FLAG)
Clears the TIMx's pending flags.
void | TIM_ClearITPendingBit (TIM_TypeDef *TIMx, uint16_t TIM_IT)
Clears the TIMx's interrupt pending bits.
void | TIM_ClearOC1Ref (TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
Clears or safeguards the OCREF1 signal on an external event.
void | TIM_ClearOC2Ref (TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
Clears or safeguards the OCREF2 signal on an external event.
void | TIM_ClearOC3Ref (TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
Clears or safeguards the OCREF3 signal on an external event.
void | TIM_ClearOC4Ref (TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
Clears or safeguards the OCREF4 signal on an external event.
void | TIM_Cmd (TIM_TypeDef *TIMx, FunctionalState NewState)
Enables or disables the specified TIM peripheral.
void | TIM_CounterModeConfig (TIM_TypeDef *TIMx, uint16_t TIM_CounterMode)
Specifies the TIMx Counter Mode to be used.
void | TIM_CtrlPWMOutputs (TIM_TypeDef *TIMx, FunctionalState NewState)
Enables or disables the TIM peripheral Main Outputs.
void | TIM_DeInit (TIM_TypeDef *TIMx)
Deinitializes the TIMx peripheral registers to their default reset values.
void | TIM_DMACmd (TIM_TypeDef *TIMx, uint16_t TIM_DMASource, FunctionalState NewState)
Enables or disables the TIMx's DMA Requests.
void | TIM_DMAConfig (TIM_TypeDef *TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)
Configures the TIMx's DMA interface.
void | TIM_EncoderInterfaceConfig (TIM_TypeDef *TIMx, uint16_t TIM_EncoderMode, uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity)
Configures the TIMx Encoder Interface.
void | TIM_ETRClockMode1Config (TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
Configures the External clock Mode1.
void | TIM_ETRClockMode2Config (TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
Configures the External clock Mode2.
void | TIM_ETRConfig (TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
Configures the TIMx External Trigger (ETR).
void | TIM_ForcedOC1Config (TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
Forces the TIMx output 1 waveform to active or inactive level.
void | TIM_ForcedOC2Config (TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
Forces the TIMx output 2 waveform to active or inactive level.
void | TIM_ForcedOC3Config (TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
Forces the TIMx output 3 waveform to active or inactive level.
void | TIM_ForcedOC4Config (TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
Forces the TIMx output 4 waveform to active or inactive level.
void | TIM_GenerateEvent (TIM_TypeDef *TIMx, uint16_t TIM_EventSource)
Configures the TIMx event to be generate by software.
uint16_t | TIM_GetCapture1 (TIM_TypeDef *TIMx)
Gets the TIMx Input Capture 1 value.
uint16_t | TIM_GetCapture2 (TIM_TypeDef *TIMx)
Gets the TIMx Input Capture 2 value.
uint16_t | TIM_GetCapture3 (TIM_TypeDef *TIMx)
Gets the TIMx Input Capture 3 value.
uint16_t | TIM_GetCapture4 (TIM_TypeDef *TIMx)
Gets the TIMx Input Capture 4 value.
uint16_t | TIM_GetCounter (TIM_TypeDef *TIMx)
Gets the TIMx Counter value.
FlagStatus | TIM_GetFlagStatus (TIM_TypeDef *TIMx, uint16_t TIM_FLAG)
Checks whether the specified TIM flag is set or not.
ITStatus | TIM_GetITStatus (TIM_TypeDef *TIMx, uint16_t TIM_IT)
Checks whether the TIM interrupt has occurred or not.
uint16_t | TIM_GetPrescaler (TIM_TypeDef *TIMx)
Gets the TIMx Prescaler value.
void | TIM_ICInit (TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct)
Initializes the TIM peripheral according to the specified parameters in the TIM_ICInitStruct.
void | TIM_ICStructInit (TIM_ICInitTypeDef *TIM_ICInitStruct)
Fills each TIM_ICInitStruct member with its default value.
void | TIM_InternalClockConfig (TIM_TypeDef *TIMx)
Configures the TIMx internal Clock.
void | TIM_ITConfig (TIM_TypeDef *TIMx, uint16_t TIM_IT, FunctionalState NewState)
Enables or disables the specified TIM interrupts.
void | TIM_ITRxExternalClockConfig (TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource)
Configures the TIMx Internal Trigger as External Clock.
void | TIM_OC1FastConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
Configures the TIMx Output Compare 1 Fast feature.
void | TIM_OC1Init (TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
Initializes the TIMx Channel1 according to the specified parameters in the TIM_OCInitStruct.
void | TIM_OC1NPolarityConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity)
Configures the TIMx Channel 1N polarity.
void | TIM_OC1PolarityConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
Configures the TIMx channel 1 polarity.
void | TIM_OC1PreloadConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
Enables or disables the TIMx peripheral Preload register on CCR1.
void | TIM_OC2FastConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
Configures the TIMx Output Compare 2 Fast feature.
void | TIM_OC2Init (TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
Initializes the TIMx Channel2 according to the specified parameters in the TIM_OCInitStruct.
void | TIM_OC2NPolarityConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity)
Configures the TIMx Channel 2N polarity.
void | TIM_OC2PolarityConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
Configures the TIMx channel 2 polarity.
void | TIM_OC2PreloadConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
Enables or disables the TIMx peripheral Preload register on CCR2.
void | TIM_OC3FastConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
Configures the TIMx Output Compare 3 Fast feature.
void | TIM_OC3Init (TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
Initializes the TIMx Channel3 according to the specified parameters in the TIM_OCInitStruct.
void | TIM_OC3NPolarityConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity)
Configures the TIMx Channel 3N polarity.
void | TIM_OC3PolarityConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
Configures the TIMx channel 3 polarity.
void | TIM_OC3PreloadConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
Enables or disables the TIMx peripheral Preload register on CCR3.
void | TIM_OC4FastConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
Configures the TIMx Output Compare 4 Fast feature.
void | TIM_OC4Init (TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
Initializes the TIMx Channel4 according to the specified parameters in the TIM_OCInitStruct.
void | TIM_OC4PolarityConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
Configures the TIMx channel 4 polarity.
void | TIM_OC4PreloadConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
Enables or disables the TIMx peripheral Preload register on CCR4.
void | TIM_OCStructInit (TIM_OCInitTypeDef *TIM_OCInitStruct)
Fills each TIM_OCInitStruct member with its default value.
void | TIM_PrescalerConfig (TIM_TypeDef *TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)
Configures the TIMx Prescaler.
void | TIM_PWMIConfig (TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct)
Configures the TIM peripheral according to the specified parameters in the TIM_ICInitStruct to measure an external PWM signal.
void | TIM_SelectCCDMA (TIM_TypeDef *TIMx, FunctionalState NewState)
Selects the TIMx peripheral Capture Compare DMA source.
void | TIM_SelectCOM (TIM_TypeDef *TIMx, FunctionalState NewState)
Selects the TIM peripheral Commutation event.
void | TIM_SelectHallSensor (TIM_TypeDef *TIMx, FunctionalState NewState)
Enables or disables the TIMx's Hall sensor interface.
void | TIM_SelectInputTrigger (TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource)
Selects the Input Trigger source.
void | TIM_SelectMasterSlaveMode (TIM_TypeDef *TIMx, uint16_t TIM_MasterSlaveMode)
Sets or Resets the TIMx Master/Slave Mode.
void | TIM_SelectOCxM (TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode)
Selects the TIM Output Compare Mode.
void | TIM_SelectOnePulseMode (TIM_TypeDef *TIMx, uint16_t TIM_OPMode)
Selects the TIMx's One Pulse Mode.
void | TIM_SelectOutputTrigger (TIM_TypeDef *TIMx, uint16_t TIM_TRGOSource)
Selects the TIMx Trigger Output Mode.
void | TIM_SelectSlaveMode (TIM_TypeDef *TIMx, uint16_t TIM_SlaveMode)
Selects the TIMx Slave Mode.
void | TIM_SetAutoreload (TIM_TypeDef *TIMx, uint16_t Autoreload)
Sets the TIMx Autoreload Register value.
void | TIM_SetClockDivision (TIM_TypeDef *TIMx, uint16_t TIM_CKD)
Sets the TIMx Clock Division value.
void | TIM_SetCompare1 (TIM_TypeDef *TIMx, uint16_t Compare1)
Sets the TIMx Capture Compare1 Register value.
void | TIM_SetCompare2 (TIM_TypeDef *TIMx, uint16_t Compare2)
Sets the TIMx Capture Compare2 Register value.
void | TIM_SetCompare3 (TIM_TypeDef *TIMx, uint16_t Compare3)
Sets the TIMx Capture Compare3 Register value.
void | TIM_SetCompare4 (TIM_TypeDef *TIMx, uint16_t Compare4)
Sets the TIMx Capture Compare4 Register value.
void | TIM_SetCounter (TIM_TypeDef *TIMx, uint16_t Counter)
Sets the TIMx Counter Register value.
void | TIM_SetIC1Prescaler (TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
Sets the TIMx Input Capture 1 prescaler.
void | TIM_SetIC2Prescaler (TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
Sets the TIMx Input Capture 2 prescaler.
void | TIM_SetIC3Prescaler (TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
Sets the TIMx Input Capture 3 prescaler.
void | TIM_SetIC4Prescaler (TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
Sets the TIMx Input Capture 4 prescaler.
void | TIM_TimeBaseInit (TIM_TypeDef *TIMx, TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct)
Initializes the TIMx Time Base Unit peripheral according to the specified parameters in the TIM_TimeBaseInitStruct.
void | TIM_TimeBaseStructInit (TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct)
Fills each TIM_TimeBaseInitStruct member with its default value.
void | TIM_TIxExternalClockConfig (TIM_TypeDef *TIMx, uint16_t TIM_TIxExternalCLKSource, uint16_t TIM_ICPolarity, uint16_t ICFilter)
Configures the TIMx Trigger as External Clock.
void | TIM_UpdateDisableConfig (TIM_TypeDef *TIMx, FunctionalState NewState)
Enables or Disables the TIMx Update event.
void | TIM_UpdateRequestConfig (TIM_TypeDef *TIMx, uint16_t TIM_UpdateSource)
Configures the TIMx Update Request Interrupt source.

Function Documentation

void TIM_ARRPreloadConfig | ( | TIM_TypeDef * | TIMx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables TIMx peripheral Preload register on ARR.

Parameters:
TIMx,: where x can be 1 to 17 to select the TIM peripheral.
NewState,: new state of the TIMx peripheral Preload register This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1409 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CR1, DISABLE, IS_FUNCTIONAL_STATE, IS_TIM_ALL_PERIPH, and TIM_CR1_ARPE.

Referenced by main().

void TIM_BDTRConfig | ( | TIM_TypeDef * | TIMx,
 |  | TIM_BDTRInitTypeDef * | TIM_BDTRInitStruct
 | ) |  |

Configures the: Break feature, dead time, Lock level, the OSSI, the OSSR State and the AOE(automatic output enable).

Parameters:
TIMx,: where x can be 1 or 8 to select the TIM
TIM_BDTRInitStruct,: pointer to a TIM_BDTRInitTypeDef structure that contains the BDTR Register configuration information for the TIM peripheral.
Return values:
None

Definition at line 712 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::BDTR, IS_TIM_AUTOMATIC_OUTPUT_STATE, IS_TIM_BREAK_POLARITY, IS_TIM_BREAK_STATE, IS_TIM_LIST2_PERIPH, IS_TIM_LOCK_LEVEL, IS_TIM_OSSI_STATE, IS_TIM_OSSR_STATE, TIM_BDTRInitTypeDef::TIM_AutomaticOutput, TIM_BDTRInitTypeDef::TIM_Break, TIM_BDTRInitTypeDef::TIM_BreakPolarity, TIM_BDTRInitTypeDef::TIM_DeadTime, TIM_BDTRInitTypeDef::TIM_LOCKLevel, TIM_BDTRInitTypeDef::TIM_OSSIState, and TIM_BDTRInitTypeDef::TIM_OSSRState.

Referenced by main().

void TIM_BDTRStructInit ( TIM_BDTRInitTypeDef * TIM_BDTRInitStruct )

Fills each TIM_BDTRInitStruct member with its default value.

Parameters:
TIM_BDTRInitStruct,: pointer to a TIM_BDTRInitTypeDef structure which will be initialized.
Return values:
None

Definition at line 787 of file stm32f10x_tim.c.

References TIM_BDTRInitTypeDef::TIM_AutomaticOutput, TIM_AutomaticOutput_Disable, TIM_BDTRInitTypeDef::TIM_Break, TIM_Break_Disable, TIM_BDTRInitTypeDef::TIM_BreakPolarity, TIM_BreakPolarity_Low, TIM_BDTRInitTypeDef::TIM_DeadTime, TIM_BDTRInitTypeDef::TIM_LOCKLevel, TIM_LOCKLevel_OFF, TIM_BDTRInitTypeDef::TIM_OSSIState, TIM_OSSIState_Disable, TIM_BDTRInitTypeDef::TIM_OSSRState, and TIM_OSSRState_Disable.

void TIM_CCPreloadControl | ( | TIM_TypeDef * | TIMx,
 |  | FunctionalState | NewState
 | ) |  |

Sets or Resets the TIM peripheral Capture Compare Preload Control bit.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5, 8 or 15 to select the TIMx peripheral
NewState,: new state of the Capture Compare Preload Control bit This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1483 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CR2, DISABLE, IS_FUNCTIONAL_STATE, IS_TIM_LIST5_PERIPH, and TIM_CR2_CCPC.

Referenced by main().

void TIM_CCxCmd | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_Channel,
 |  | uint16_t | TIM_CCx
 | ) |  |

Enables or disables the TIM Capture Compare Channel x.

Parameters:
TIMx,: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
TIM_Channel,: specifies the TIM Channel This parameter can be one of the following values:

  • TIM_Channel_1: TIM Channel 1
  • TIM_Channel_2: TIM Channel 2
  • TIM_Channel_3: TIM Channel 3
  • TIM_Channel_4: TIM Channel 4
TIM_CCx,: specifies the TIM Channel CCxE bit new state. This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable.
Return values:
None

Definition at line 1974 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CCER, CCER_CCE_Set, IS_TIM_CCX, IS_TIM_CHANNEL, and IS_TIM_LIST8_PERIPH.

Referenced by TIM1_TRG_COM_IRQHandler().

void TIM_CCxNCmd | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_Channel,
 |  | uint16_t | TIM_CCxN
 | ) |  |

Enables or disables the TIM Capture Compare Channel xN.

Parameters:
TIMx,: where x can be 1, 8, 15, 16 or 17 to select the TIM peripheral.
TIM_Channel,: specifies the TIM Channel This parameter can be one of the following values:

  • TIM_Channel_1: TIM Channel 1
  • TIM_Channel_2: TIM Channel 2
  • TIM_Channel_3: TIM Channel 3
TIM_CCxN,: specifies the TIM Channel CCxNE bit new state. This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable.
Return values:
None

Definition at line 2004 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CCER, CCER_CCNE_Set, IS_TIM_CCXN, IS_TIM_COMPLEMENTARY_CHANNEL, and IS_TIM_LIST2_PERIPH.

Referenced by TIM1_TRG_COM_IRQHandler().

void TIM_ClearFlag | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_FLAG
 | ) |  |

Clears the TIMx's pending flags.

Parameters:
TIMx,: where x can be 1 to 17 to select the TIM peripheral.
TIM_FLAG,: specifies the flag bit to clear. This parameter can be any combination of the following values:

  • TIM_FLAG_Update: TIM update Flag
  • TIM_FLAG_CC1: TIM Capture Compare 1 Flag
  • TIM_FLAG_CC2: TIM Capture Compare 2 Flag
  • TIM_FLAG_CC3: TIM Capture Compare 3 Flag
  • TIM_FLAG_CC4: TIM Capture Compare 4 Flag
  • TIM_FLAG_COM: TIM Commutation Flag
  • TIM_FLAG_Trigger: TIM Trigger Flag
  • TIM_FLAG_Break: TIM Break Flag
  • TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag
  • TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag
  • TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag
  • TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag
Note:
  • TIM6 and TIM7 can have only one update flag.
  • TIM9, TIM12 and TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1, TIM_FLAG_CC2 or TIM_FLAG_Trigger.
  • TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1.
  • TIM_FLAG_Break is used only with TIM1, TIM8 and TIM15.
  • TIM_FLAG_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17.
Return values:
None

Definition at line 2600 of file stm32f10x_tim.c.

References assert_param, IS_TIM_ALL_PERIPH, IS_TIM_CLEAR_FLAG, and TIM_TypeDef::SR.

Referenced by TIM_Config().

void TIM_ClearITPendingBit | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_IT
 | ) |  |

Clears the TIMx's interrupt pending bits.

Parameters:
TIMx,: where x can be 1 to 17 to select the TIM peripheral.
TIM_IT,: specifies the pending bit to clear. This parameter can be any combination of the following values:

  • TIM_IT_Update: TIM1 update Interrupt source
  • TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
  • TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
  • TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
  • TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
  • TIM_IT_COM: TIM Commutation Interrupt source
  • TIM_IT_Trigger: TIM Trigger Interrupt source
  • TIM_IT_Break: TIM Break Interrupt source
Note:
  • TIM6 and TIM7 can generate only an update interrupt.
  • TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1, TIM_IT_CC2 or TIM_IT_Trigger.
  • TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1.
  • TIM_IT_Break is used only with TIM1, TIM8 and TIM15.
  • TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17.
Return values:
None

Definition at line 2676 of file stm32f10x_tim.c.

References assert_param, IS_TIM_ALL_PERIPH, IS_TIM_IT, and TIM_TypeDef::SR.

Referenced by TIM1_BRK_TIM9_IRQHandler(), TIM1_TRG_COM_IRQHandler(), TIM2_IRQHandler(), TIM3_IRQHandler(), TIM4_IRQHandler(), and TIM5_IRQHandler().

void TIM_ClearOC1Ref | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_OCClear
 | ) |  |

Clears or safeguards the OCREF1 signal on an external event.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
TIM_OCClear,: new state of the Output Compare Clear Enable Bit. This parameter can be one of the following values:

  • TIM_OCClear_Enable: TIM Output clear enable
  • TIM_OCClear_Disable: TIM Output clear disable
Return values:
None

Definition at line 1707 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CCMR1, IS_TIM_LIST3_PERIPH, IS_TIM_OCCLEAR_STATE, and TIM_CCMR1_OC1CE.

void TIM_ClearOC2Ref | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_OCClear
 | ) |  |

Clears or safeguards the OCREF2 signal on an external event.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
TIM_OCClear,: new state of the Output Compare Clear Enable Bit. This parameter can be one of the following values:

  • TIM_OCClear_Enable: TIM Output clear enable
  • TIM_OCClear_Disable: TIM Output clear disable
Return values:
None

Definition at line 1733 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CCMR1, IS_TIM_LIST3_PERIPH, IS_TIM_OCCLEAR_STATE, and TIM_CCMR1_OC2CE.

void TIM_ClearOC3Ref | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_OCClear
 | ) |  |

Clears or safeguards the OCREF3 signal on an external event.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
TIM_OCClear,: new state of the Output Compare Clear Enable Bit. This parameter can be one of the following values:

  • TIM_OCClear_Enable: TIM Output clear enable
  • TIM_OCClear_Disable: TIM Output clear disable
Return values:
None

Definition at line 1757 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CCMR2, IS_TIM_LIST3_PERIPH, IS_TIM_OCCLEAR_STATE, and TIM_CCMR2_OC3CE.

void TIM_ClearOC4Ref | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_OCClear
 | ) |  |

Clears or safeguards the OCREF4 signal on an external event.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
TIM_OCClear,: new state of the Output Compare Clear Enable Bit. This parameter can be one of the following values:

  • TIM_OCClear_Enable: TIM Output clear enable
  • TIM_OCClear_Disable: TIM Output clear disable
Return values:
None

Definition at line 1781 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CCMR2, IS_TIM_LIST3_PERIPH, IS_TIM_OCCLEAR_STATE, and TIM_CCMR2_OC4CE.

void TIM_Cmd | ( | TIM_TypeDef * | TIMx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified TIM peripheral.

Parameters:
TIMx,: where x can be 1 to 17 to select the TIMx peripheral.
NewState,: new state of the TIMx peripheral. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 806 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CR1, DISABLE, IS_FUNCTIONAL_STATE, IS_TIM_ALL_PERIPH, and TIM_CR1_CEN.

Referenced by main(), TIM5_ConfigForLSI(), TIM5_IRQHandler(), and TIM_Config().

void TIM_CounterModeConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_CounterMode
 | ) |  |

Specifies the TIMx Counter Mode to be used.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
TIM_CounterMode,: specifies the Counter Mode to be used This parameter can be one of the following values:

  • TIM_CounterMode_Up: TIM Up Counting Mode
  • TIM_CounterMode_Down: TIM Down Counting Mode
  • TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1
  • TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2
  • TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3
Return values:
None

Definition at line 1199 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CR1, IS_TIM_COUNTER_MODE, IS_TIM_LIST3_PERIPH, TIM_CR1_CMS, and TIM_CR1_DIR.

void TIM_CtrlPWMOutputs | ( | TIM_TypeDef * | TIMx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the TIM peripheral Main Outputs.

Parameters:
TIMx,: where x can be 1, 8, 15, 16 or 17 to select the TIMx peripheral.
NewState,: new state of the TIM peripheral Main Outputs. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 831 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::BDTR, DISABLE, IS_FUNCTIONAL_STATE, IS_TIM_LIST2_PERIPH, and TIM_BDTR_MOE.

Referenced by main().

void TIM_DeInit ( TIM_TypeDef * TIMx )

Deinitializes the TIMx peripheral registers to their default reset values.

Parameters:
TIMx,: where x can be 1 to 17 to select the TIM peripheral.
Return values:
None

Definition at line 122 of file stm32f10x_tim.c.

References assert_param, DISABLE, ENABLE, IS_TIM_ALL_PERIPH, RCC_APB1Periph_TIM12, RCC_APB1Periph_TIM13, RCC_APB1Periph_TIM14, RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4, RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7, RCC_APB1PeriphResetCmd(), RCC_APB2Periph_TIM1, RCC_APB2Periph_TIM10, RCC_APB2Periph_TIM11, RCC_APB2Periph_TIM15, RCC_APB2Periph_TIM16, RCC_APB2Periph_TIM17, RCC_APB2Periph_TIM8, RCC_APB2Periph_TIM9, RCC_APB2PeriphResetCmd(), TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, and TIM9.

Referenced by main().

void TIM_DMACmd | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_DMASource,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the TIMx's DMA Requests.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5, 6, 7, 8, 15, 16 or 17 to select the TIM peripheral.
TIM_DMASource,: specifies the DMA Request sources. This parameter can be any combination of the following values:

  • TIM_DMA_Update: TIM update Interrupt source
  • TIM_DMA_CC1: TIM Capture Compare 1 DMA source
  • TIM_DMA_CC2: TIM Capture Compare 2 DMA source
  • TIM_DMA_CC3: TIM Capture Compare 3 DMA source
  • TIM_DMA_CC4: TIM Capture Compare 4 DMA source
  • TIM_DMA_COM: TIM Commutation DMA source
  • TIM_DMA_Trigger: TIM Trigger DMA source
NewState,: new state of the DMA Request sources. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 964 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::DIER, DISABLE, IS_FUNCTIONAL_STATE, IS_TIM_DMA_SOURCE, and IS_TIM_LIST9_PERIPH.

Referenced by main().

void TIM_DMAConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_DMABase,
 |  | uint16_t | TIM_DMABurstLength
 | ) |  |

Configures the TIMx's DMA interface.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5, 8, 15, 16 or 17 to select the TIM peripheral.
TIM_DMABase,: DMA Base address. This parameter can be one of the following values:

  • TIM_DMABase_CR, TIM_DMABase_CR2, TIM_DMABase_SMCR, TIM_DMABase_DIER, TIM1_DMABase_SR, TIM_DMABase_EGR, TIM_DMABase_CCMR1, TIM_DMABase_CCMR2, TIM_DMABase_CCER, TIM_DMABase_CNT, TIM_DMABase_PSC, TIM_DMABase_ARR, TIM_DMABase_RCR, TIM_DMABase_CCR1, TIM_DMABase_CCR2, TIM_DMABase_CCR3, TIM_DMABase_CCR4, TIM_DMABase_BDTR, TIM_DMABase_DCR.
TIM_DMABurstLength,: DMA Burst length. This parameter can be one value between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
Return values:
None

Definition at line 937 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::DCR, IS_TIM_DMA_BASE, IS_TIM_DMA_LENGTH, and IS_TIM_LIST4_PERIPH.

Referenced by main().

void TIM_EncoderInterfaceConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_EncoderMode,
 |  | uint16_t | TIM_IC1Polarity,
 |  | uint16_t | TIM_IC2Polarity
 | ) |  |

Configures the TIMx Encoder Interface.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
TIM_EncoderMode,: specifies the TIMx Encoder Mode. This parameter can be one of the following values:

  • TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level.
  • TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level.
  • TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
TIM_IC1Polarity,: specifies the IC1 Polarity This parameter can be one of the following values:

  • TIM_ICPolarity_Falling: IC Falling edge.
  • TIM_ICPolarity_Rising: IC Rising edge.
TIM_IC2Polarity,: specifies the IC2 Polarity This parameter can be one of the following values:

  • TIM_ICPolarity_Falling: IC Falling edge.
  • TIM_ICPolarity_Rising: IC Rising edge.
Return values:
None

Definition at line 1264 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CCER, TIM_TypeDef::CCMR1, IS_TIM_ENCODER_MODE, IS_TIM_IC_POLARITY, IS_TIM_LIST5_PERIPH, TIM_TypeDef::SMCR, TIM_CCER_CC1P, TIM_CCER_CC2P, TIM_CCMR1_CC1S, TIM_CCMR1_CC1S_0, TIM_CCMR1_CC2S, TIM_CCMR1_CC2S_0, and TIM_SMCR_SMS.

void TIM_ETRClockMode1Config | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_ExtTRGPrescaler,
 |  | uint16_t | TIM_ExtTRGPolarity,
 |  | uint16_t | ExtTRGFilter
 | ) |  |

Configures the External clock Mode1.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
TIM_ExtTRGPrescaler,: The external Trigger Prescaler. This parameter can be one of the following values:

  • TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
  • TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
  • TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
  • TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
TIM_ExtTRGPolarity,: The external Trigger Polarity. This parameter can be one of the following values:

  • TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
  • TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
ExtTRGFilter,: External Trigger Filter. This parameter must be a value between 0x00 and 0x0F
Return values:
None

Definition at line 1075 of file stm32f10x_tim.c.

References assert_param, IS_TIM_EXT_FILTER, IS_TIM_EXT_POLARITY, IS_TIM_EXT_PRESCALER, IS_TIM_LIST3_PERIPH, TIM_TypeDef::SMCR, TIM_ETRConfig(), TIM_SlaveMode_External1, TIM_SMCR_SMS, TIM_SMCR_TS, and TIM_TS_ETRF.

void TIM_ETRClockMode2Config | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_ExtTRGPrescaler,
 |  | uint16_t | TIM_ExtTRGPolarity,
 |  | uint16_t | ExtTRGFilter
 | ) |  |

Configures the External clock Mode2.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
TIM_ExtTRGPrescaler,: The external Trigger Prescaler. This parameter can be one of the following values:

  • TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
  • TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
  • TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
  • TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
TIM_ExtTRGPolarity,: The external Trigger Polarity. This parameter can be one of the following values:

  • TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
  • TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
ExtTRGFilter,: External Trigger Filter. This parameter must be a value between 0x00 and 0x0F
Return values:
None

Definition at line 1117 of file stm32f10x_tim.c.

References assert_param, IS_TIM_EXT_FILTER, IS_TIM_EXT_POLARITY, IS_TIM_EXT_PRESCALER, IS_TIM_LIST3_PERIPH, TIM_TypeDef::SMCR, TIM_ETRConfig(), and TIM_SMCR_ECE.

void TIM_ETRConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_ExtTRGPrescaler,
 |  | uint16_t | TIM_ExtTRGPolarity,
 |  | uint16_t | ExtTRGFilter
 | ) |  |

Configures the TIMx External Trigger (ETR).

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
TIM_ExtTRGPrescaler,: The external Trigger Prescaler. This parameter can be one of the following values:

  • TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
  • TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
  • TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
  • TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
TIM_ExtTRGPolarity,: The external Trigger Polarity. This parameter can be one of the following values:

  • TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
  • TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
ExtTRGFilter,: External Trigger Filter. This parameter must be a value between 0x00 and 0x0F
Return values:
None

Definition at line 1148 of file stm32f10x_tim.c.

References assert_param, IS_TIM_EXT_FILTER, IS_TIM_EXT_POLARITY, IS_TIM_EXT_PRESCALER, IS_TIM_LIST3_PERIPH, TIM_TypeDef::SMCR, and SMCR_ETR_Mask.

Referenced by TIM_ETRClockMode1Config(), and TIM_ETRClockMode2Config().

void TIM_ForcedOC1Config | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_ForcedAction
 | ) |  |

Forces the TIMx output 1 waveform to active or inactive level.

Parameters:
TIMx,: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
TIM_ForcedAction,: specifies the forced Action to be set to the output waveform. This parameter can be one of the following values:

  • TIM_ForcedAction_Active: Force active level on OC1REF
  • TIM_ForcedAction_InActive: Force inactive level on OC1REF.
Return values:
None

Definition at line 1315 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CCMR1, IS_TIM_FORCED_ACTION, IS_TIM_LIST8_PERIPH, and TIM_CCMR1_OC1M.

void TIM_ForcedOC2Config | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_ForcedAction
 | ) |  |

Forces the TIMx output 2 waveform to active or inactive level.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
TIM_ForcedAction,: specifies the forced Action to be set to the output waveform. This parameter can be one of the following values:

  • TIM_ForcedAction_Active: Force active level on OC2REF
  • TIM_ForcedAction_InActive: Force inactive level on OC2REF.
Return values:
None

Definition at line 1339 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CCMR1, IS_TIM_FORCED_ACTION, IS_TIM_LIST6_PERIPH, and TIM_CCMR1_OC2M.

void TIM_ForcedOC3Config | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_ForcedAction
 | ) |  |

Forces the TIMx output 3 waveform to active or inactive level.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
TIM_ForcedAction,: specifies the forced Action to be set to the output waveform. This parameter can be one of the following values:

  • TIM_ForcedAction_Active: Force active level on OC3REF
  • TIM_ForcedAction_InActive: Force inactive level on OC3REF.
Return values:
None

Definition at line 1363 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CCMR2, IS_TIM_FORCED_ACTION, IS_TIM_LIST3_PERIPH, and TIM_CCMR2_OC3M.

void TIM_ForcedOC4Config | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_ForcedAction
 | ) |  |

Forces the TIMx output 4 waveform to active or inactive level.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
TIM_ForcedAction,: specifies the forced Action to be set to the output waveform. This parameter can be one of the following values:

  • TIM_ForcedAction_Active: Force active level on OC4REF
  • TIM_ForcedAction_InActive: Force inactive level on OC4REF.
Return values:
None

Definition at line 1387 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CCMR2, IS_TIM_FORCED_ACTION, IS_TIM_LIST3_PERIPH, and TIM_CCMR2_OC4M.

void TIM_GenerateEvent | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_EventSource
 | ) |  |

Configures the TIMx event to be generate by software.

Parameters:
TIMx,: where x can be 1 to 17 to select the TIM peripheral.
TIM_EventSource,: specifies the event source. This parameter can be one or more of the following values:

  • TIM_EventSource_Update: Timer update Event source
  • TIM_EventSource_CC1: Timer Capture Compare 1 Event source
  • TIM_EventSource_CC2: Timer Capture Compare 2 Event source
  • TIM_EventSource_CC3: Timer Capture Compare 3 Event source
  • TIM_EventSource_CC4: Timer Capture Compare 4 Event source
  • TIM_EventSource_COM: Timer COM event source
  • TIM_EventSource_Trigger: Timer Trigger Event source
  • TIM_EventSource_Break: Timer Break event source
Note:
  • TIM6 and TIM7 can only generate an update event.
  • TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1 and TIM8.
Return values:
None

Definition at line 909 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::EGR, IS_TIM_ALL_PERIPH, and IS_TIM_EVENT_SOURCE.

Referenced by SysTick_Handler().

uint16_t TIM_GetCapture1 ( TIM_TypeDef * TIMx )

Gets the TIMx Input Capture 1 value.

Parameters:
TIMx,: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
Return values:
Capture Compare 1 Register value.

Definition at line 2457 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CCR1, and IS_TIM_LIST8_PERIPH.

Referenced by TIM1_BRK_TIM9_IRQHandler(), TIM2_IRQHandler(), and TIM3_IRQHandler().

uint16_t TIM_GetCapture2 ( TIM_TypeDef * TIMx )

Gets the TIMx Input Capture 2 value.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
Return values:
Capture Compare 2 Register value.

Definition at line 2470 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CCR2, and IS_TIM_LIST6_PERIPH.

Referenced by TIM1_BRK_TIM9_IRQHandler(), TIM2_IRQHandler(), and TIM3_IRQHandler().

uint16_t TIM_GetCapture3 ( TIM_TypeDef * TIMx )

Gets the TIMx Input Capture 3 value.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
Return values:
Capture Compare 3 Register value.

Definition at line 2483 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CCR3, and IS_TIM_LIST3_PERIPH.

Referenced by TIM2_IRQHandler(), and TIM3_IRQHandler().

uint16_t TIM_GetCapture4 ( TIM_TypeDef * TIMx )

Gets the TIMx Input Capture 4 value.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
Return values:
Capture Compare 4 Register value.

Definition at line 2496 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CCR4, and IS_TIM_LIST3_PERIPH.

Referenced by TIM2_IRQHandler(), TIM3_IRQHandler(), and TIM5_IRQHandler().

uint16_t TIM_GetCounter ( TIM_TypeDef * TIMx )

Gets the TIMx Counter value.

Parameters:
TIMx,: where x can be 1 to 17 to select the TIM peripheral.
Return values:
Counter Register value.

Definition at line 2509 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CNT, and IS_TIM_ALL_PERIPH.

FlagStatus TIM_GetFlagStatus | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_FLAG
 | ) |  |

Checks whether the specified TIM flag is set or not.

Parameters:
TIMx,: where x can be 1 to 17 to select the TIM peripheral.
TIM_FLAG,: specifies the flag to check. This parameter can be one of the following values:

  • TIM_FLAG_Update: TIM update Flag
  • TIM_FLAG_CC1: TIM Capture Compare 1 Flag
  • TIM_FLAG_CC2: TIM Capture Compare 2 Flag
  • TIM_FLAG_CC3: TIM Capture Compare 3 Flag
  • TIM_FLAG_CC4: TIM Capture Compare 4 Flag
  • TIM_FLAG_COM: TIM Commutation Flag
  • TIM_FLAG_Trigger: TIM Trigger Flag
  • TIM_FLAG_Break: TIM Break Flag
  • TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag
  • TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag
  • TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag
  • TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag
Note:
  • TIM6 and TIM7 can have only one update flag.
  • TIM9, TIM12 and TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1, TIM_FLAG_CC2 or TIM_FLAG_Trigger.
  • TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1.
  • TIM_FLAG_Break is used only with TIM1, TIM8 and TIM15.
  • TIM_FLAG_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17.
Return values:
The new state of TIM_FLAG (SET or RESET).

Definition at line 2556 of file stm32f10x_tim.c.

References assert_param, IS_TIM_ALL_PERIPH, IS_TIM_GET_FLAG, RESET, SET, and TIM_TypeDef::SR.

ITStatus TIM_GetITStatus | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_IT
 | ) |  |

Checks whether the TIM interrupt has occurred or not.

Parameters:
TIMx,: where x can be 1 to 17 to select the TIM peripheral.
TIM_IT,: specifies the TIM interrupt source to check. This parameter can be one of the following values:

  • TIM_IT_Update: TIM update Interrupt source
  • TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
  • TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
  • TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
  • TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
  • TIM_IT_COM: TIM Commutation Interrupt source
  • TIM_IT_Trigger: TIM Trigger Interrupt source
  • TIM_IT_Break: TIM Break Interrupt source
Note:
  • TIM6 and TIM7 can generate only an update interrupt.
  • TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1, TIM_IT_CC2 or TIM_IT_Trigger.
  • TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1.
  • TIM_IT_Break is used only with TIM1, TIM8 and TIM15.
  • TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17.
Return values:
The new state of the TIM_IT(SET or RESET).

Definition at line 2632 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::DIER, IS_TIM_ALL_PERIPH, IS_TIM_GET_IT, RESET, SET, and TIM_TypeDef::SR.

Referenced by TIM1_BRK_TIM9_IRQHandler(), TIM2_IRQHandler(), TIM3_IRQHandler(), and TIM5_IRQHandler().

uint16_t TIM_GetPrescaler ( TIM_TypeDef * TIMx )

Gets the TIMx Prescaler value.

Parameters:
TIMx,: where x can be 1 to 17 to select the TIM peripheral.
Return values:
Prescaler Register value.

Definition at line 2522 of file stm32f10x_tim.c.

References assert_param, IS_TIM_ALL_PERIPH, and TIM_TypeDef::PSC.

void TIM_ICInit | ( | TIM_TypeDef * | TIMx,
 |  | TIM_ICInitTypeDef * | TIM_ICInitStruct
 | ) |  |

Initializes the TIM peripheral according to the specified parameters in the TIM_ICInitStruct.

Parameters:
TIMx,: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
TIM_ICInitStruct,: pointer to a TIM_ICInitTypeDef structure that contains the configuration information for the specified TIM peripheral.
Return values:
None

Definition at line 587 of file stm32f10x_tim.c.

References assert_param, IS_TIM_CHANNEL, IS_TIM_IC_FILTER, IS_TIM_IC_POLARITY, IS_TIM_IC_POLARITY_LITE, IS_TIM_IC_PRESCALER, IS_TIM_IC_SELECTION, IS_TIM_LIST3_PERIPH, IS_TIM_LIST6_PERIPH, IS_TIM_LIST8_PERIPH, TI1_Config(), TI2_Config(), TI3_Config(), TI4_Config(), TIM1, TIM2, TIM3, TIM4, TIM5, TIM8, TIM_ICInitTypeDef::TIM_Channel, TIM_Channel_1, TIM_Channel_2, TIM_Channel_3, TIM_ICInitTypeDef::TIM_ICFilter, TIM_ICInitTypeDef::TIM_ICPolarity, TIM_ICInitTypeDef::TIM_ICPrescaler, TIM_ICInitTypeDef::TIM_ICSelection, TIM_SetIC1Prescaler(), TIM_SetIC2Prescaler(), TIM_SetIC3Prescaler(), and TIM_SetIC4Prescaler().

Referenced by main(), and TIM5_ConfigForLSI().

void TIM_ICStructInit ( TIM_ICInitTypeDef * TIM_ICInitStruct )

Fills each TIM_ICInitStruct member with its default value.

Parameters:
TIM_ICInitStruct,: pointer to a TIM_ICInitTypeDef structure which will be initialized.
Return values:
None

Definition at line 771 of file stm32f10x_tim.c.

References TIM_ICInitTypeDef::TIM_Channel, TIM_Channel_1, TIM_ICInitTypeDef::TIM_ICFilter, TIM_ICInitTypeDef::TIM_ICPolarity, TIM_ICPolarity_Rising, TIM_ICInitTypeDef::TIM_ICPrescaler, TIM_ICPSC_DIV1, TIM_ICInitTypeDef::TIM_ICSelection, and TIM_ICSelection_DirectTI.

Referenced by main().

void TIM_InternalClockConfig ( TIM_TypeDef * TIMx )

Configures the TIMx internal Clock.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
Return values:
None

Definition at line 989 of file stm32f10x_tim.c.

References assert_param, IS_TIM_LIST6_PERIPH, TIM_TypeDef::SMCR, and TIM_SMCR_SMS.

void TIM_ITConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified TIM interrupts.

Parameters:
TIMx,: where x can be 1 to 17 to select the TIMx peripheral.
TIM_IT,: specifies the TIM interrupts sources to be enabled or disabled. This parameter can be any combination of the following values:

  • TIM_IT_Update: TIM update Interrupt source
  • TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
  • TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
  • TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
  • TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
  • TIM_IT_COM: TIM Commutation Interrupt source
  • TIM_IT_Trigger: TIM Trigger Interrupt source
  • TIM_IT_Break: TIM Break Interrupt source
Note:
  • TIM6 and TIM7 can only generate an update interrupt.
  • TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1, TIM_IT_CC2 or TIM_IT_Trigger.
  • TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1.
  • TIM_IT_Break is used only with TIM1, TIM8 and TIM15.
  • TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17.
Parameters:
NewState,: new state of the TIM interrupts. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 872 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::DIER, DISABLE, IS_FUNCTIONAL_STATE, IS_TIM_ALL_PERIPH, and IS_TIM_IT.

Referenced by main(), TIM5_ConfigForLSI(), TIM5_IRQHandler(), and TIM_Config().

void TIM_ITRxExternalClockConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_InputTriggerSource
 | ) |  |

Configures the TIMx Internal Trigger as External Clock.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5, 9, 12 or 15 to select the TIM peripheral.
TIM_ITRSource,: Trigger source. This parameter can be one of the following values:
TIM_TS_ITR0,: Internal Trigger 0
TIM_TS_ITR1,: Internal Trigger 1
TIM_TS_ITR2,: Internal Trigger 2
TIM_TS_ITR3,: Internal Trigger 3
Return values:
None

Definition at line 1008 of file stm32f10x_tim.c.

References assert_param, IS_TIM_INTERNAL_TRIGGER_SELECTION, IS_TIM_LIST6_PERIPH, TIM_TypeDef::SMCR, TIM_SelectInputTrigger(), and TIM_SlaveMode_External1.

void TIM_OC1FastConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_OCFast
 | ) |  |

Configures the TIMx Output Compare 1 Fast feature.

Parameters:
TIMx,: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
TIM_OCFast,: new state of the Output Compare Fast Enable Bit. This parameter can be one of the following values:

  • TIM_OCFast_Enable: TIM output compare fast enable
  • TIM_OCFast_Disable: TIM output compare fast disable
Return values:
None

Definition at line 1606 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CCMR1, IS_TIM_LIST8_PERIPH, IS_TIM_OCFAST_STATE, and TIM_CCMR1_OC1FE.

void TIM_OC1Init | ( | TIM_TypeDef * | TIMx,
 |  | TIM_OCInitTypeDef * | TIM_OCInitStruct
 | ) |  |

Initializes the TIMx Channel1 according to the specified parameters in the TIM_OCInitStruct.

Parameters:
TIMx,: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
TIM_OCInitStruct,: pointer to a TIM_OCInitTypeDef structure that contains the configuration information for the specified TIM peripheral.
Return values:
None

Definition at line 279 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CCER, TIM_TypeDef::CCMR1, TIM_TypeDef::CCR1, TIM_TypeDef::CR2, IS_TIM_LIST8_PERIPH, IS_TIM_OC_MODE, IS_TIM_OC_POLARITY, IS_TIM_OCIDLE_STATE, IS_TIM_OCN_POLARITY, IS_TIM_OCNIDLE_STATE, IS_TIM_OUTPUT_STATE, IS_TIM_OUTPUTN_STATE, TIM1, TIM15, TIM16, TIM17, TIM8, TIM_CCER_CC1E, TIM_CCER_CC1NE, TIM_CCER_CC1NP, TIM_CCER_CC1P, TIM_CCMR1_CC1S, TIM_CCMR1_OC1M, TIM_CR2_OIS1, TIM_CR2_OIS1N, TIM_OCInitTypeDef::TIM_OCIdleState, TIM_OCInitTypeDef::TIM_OCMode, TIM_OCInitTypeDef::TIM_OCNIdleState, TIM_OCInitTypeDef::TIM_OCNPolarity, TIM_OCInitTypeDef::TIM_OCPolarity, TIM_OCInitTypeDef::TIM_OutputNState, TIM_OCInitTypeDef::TIM_OutputState, and TIM_OCInitTypeDef::TIM_Pulse.

Referenced by main(), and TIM_Config().

void TIM_OC1NPolarityConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_OCNPolarity
 | ) |  |

Configures the TIMx Channel 1N polarity.

Parameters:
TIMx,: where x can be 1, 8, 15, 16 or 17 to select the TIM peripheral.
TIM_OCNPolarity,: specifies the OC1N Polarity This parameter can be one of the following values:

  • TIM_OCNPolarity_High: Output Compare active high
  • TIM_OCNPolarity_Low: Output Compare active low
Return values:
None

Definition at line 1828 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CCER, IS_TIM_LIST2_PERIPH, IS_TIM_OCN_POLARITY, and TIM_CCER_CC1NP.

void TIM_OC1PolarityConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_OCPolarity
 | ) |  |

Configures the TIMx channel 1 polarity.

Parameters:
TIMx,: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
TIM_OCPolarity,: specifies the OC1 Polarity This parameter can be one of the following values:

  • TIM_OCPolarity_High: Output Compare active high
  • TIM_OCPolarity_Low: Output Compare active low
Return values:
None

Definition at line 1805 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CCER, IS_TIM_LIST8_PERIPH, IS_TIM_OC_POLARITY, and TIM_CCER_CC1P.

void TIM_OC1PreloadConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_OCPreload
 | ) |  |

Enables or disables the TIMx peripheral Preload register on CCR1.

Parameters:
TIMx,: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
TIM_OCPreload,: new state of the TIMx peripheral Preload register This parameter can be one of the following values:

  • TIM_OCPreload_Enable
  • TIM_OCPreload_Disable
Return values:
None

Definition at line 1509 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CCMR1, IS_TIM_LIST8_PERIPH, IS_TIM_OCPRELOAD_STATE, and TIM_CCMR1_OC1PE.

Referenced by main().

void TIM_OC2FastConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_OCFast
 | ) |  |

Configures the TIMx Output Compare 2 Fast feature.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
TIM_OCFast,: new state of the Output Compare Fast Enable Bit. This parameter can be one of the following values:

  • TIM_OCFast_Enable: TIM output compare fast enable
  • TIM_OCFast_Disable: TIM output compare fast disable
Return values:
None

Definition at line 1632 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CCMR1, IS_TIM_LIST6_PERIPH, IS_TIM_OCFAST_STATE, and TIM_CCMR1_OC2FE.

void TIM_OC2Init | ( | TIM_TypeDef * | TIMx,
 |  | TIM_OCInitTypeDef * | TIM_OCInitStruct
 | ) |  |

Initializes the TIMx Channel2 according to the specified parameters in the TIM_OCInitStruct.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
TIM_OCInitStruct,: pointer to a TIM_OCInitTypeDef structure that contains the configuration information for the specified TIM peripheral.
Return values:
None

Definition at line 362 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CCER, TIM_TypeDef::CCMR1, TIM_TypeDef::CCR2, TIM_TypeDef::CR2, IS_TIM_LIST6_PERIPH, IS_TIM_OC_MODE, IS_TIM_OC_POLARITY, IS_TIM_OCIDLE_STATE, IS_TIM_OCN_POLARITY, IS_TIM_OCNIDLE_STATE, IS_TIM_OUTPUT_STATE, IS_TIM_OUTPUTN_STATE, TIM1, TIM8, TIM_CCER_CC2E, TIM_CCER_CC2NE, TIM_CCER_CC2NP, TIM_CCER_CC2P, TIM_CCMR1_CC2S, TIM_CCMR1_OC2M, TIM_CR2_OIS2, TIM_CR2_OIS2N, TIM_OCInitTypeDef::TIM_OCIdleState, TIM_OCInitTypeDef::TIM_OCMode, TIM_OCInitTypeDef::TIM_OCNIdleState, TIM_OCInitTypeDef::TIM_OCNPolarity, TIM_OCInitTypeDef::TIM_OCPolarity, TIM_OCInitTypeDef::TIM_OutputNState, TIM_OCInitTypeDef::TIM_OutputState, and TIM_OCInitTypeDef::TIM_Pulse.

Referenced by main().

void TIM_OC2NPolarityConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_OCNPolarity
 | ) |  |

Configures the TIMx Channel 2N polarity.

Parameters:
TIMx,: where x can be 1 or 8 to select the TIM peripheral.
TIM_OCNPolarity,: specifies the OC2N Polarity This parameter can be one of the following values:

  • TIM_OCNPolarity_High: Output Compare active high
  • TIM_OCNPolarity_Low: Output Compare active low
Return values:
None

Definition at line 1875 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CCER, IS_TIM_LIST1_PERIPH, IS_TIM_OCN_POLARITY, and TIM_CCER_CC2NP.

void TIM_OC2PolarityConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_OCPolarity
 | ) |  |

Configures the TIMx channel 2 polarity.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
TIM_OCPolarity,: specifies the OC2 Polarity This parameter can be one of the following values:

  • TIM_OCPolarity_High: Output Compare active high
  • TIM_OCPolarity_Low: Output Compare active low
Return values:
None

Definition at line 1852 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CCER, IS_TIM_LIST6_PERIPH, IS_TIM_OC_POLARITY, and TIM_CCER_CC2P.

void TIM_OC2PreloadConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_OCPreload
 | ) |  |

Enables or disables the TIMx peripheral Preload register on CCR2.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
TIM_OCPreload,: new state of the TIMx peripheral Preload register This parameter can be one of the following values:

  • TIM_OCPreload_Enable
  • TIM_OCPreload_Disable
Return values:
None

Definition at line 1534 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CCMR1, IS_TIM_LIST6_PERIPH, IS_TIM_OCPRELOAD_STATE, and TIM_CCMR1_OC2PE.

Referenced by main().

void TIM_OC3FastConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_OCFast
 | ) |  |

Configures the TIMx Output Compare 3 Fast feature.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
TIM_OCFast,: new state of the Output Compare Fast Enable Bit. This parameter can be one of the following values:

  • TIM_OCFast_Enable: TIM output compare fast enable
  • TIM_OCFast_Disable: TIM output compare fast disable
Return values:
None

Definition at line 1657 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CCMR2, IS_TIM_LIST3_PERIPH, IS_TIM_OCFAST_STATE, and TIM_CCMR2_OC3FE.

void TIM_OC3Init | ( | TIM_TypeDef * | TIMx,
 |  | TIM_OCInitTypeDef * | TIM_OCInitStruct
 | ) |  |

Initializes the TIMx Channel3 according to the specified parameters in the TIM_OCInitStruct.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
TIM_OCInitStruct,: pointer to a TIM_OCInitTypeDef structure that contains the configuration information for the specified TIM peripheral.
Return values:
None

Definition at line 444 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CCER, TIM_TypeDef::CCMR2, TIM_TypeDef::CCR3, TIM_TypeDef::CR2, IS_TIM_LIST3_PERIPH, IS_TIM_OC_MODE, IS_TIM_OC_POLARITY, IS_TIM_OCIDLE_STATE, IS_TIM_OCN_POLARITY, IS_TIM_OCNIDLE_STATE, IS_TIM_OUTPUT_STATE, IS_TIM_OUTPUTN_STATE, TIM1, TIM8, TIM_CCER_CC3E, TIM_CCER_CC3NE, TIM_CCER_CC3NP, TIM_CCER_CC3P, TIM_CCMR2_CC3S, TIM_CCMR2_OC3M, TIM_CR2_OIS3, TIM_CR2_OIS3N, TIM_OCInitTypeDef::TIM_OCIdleState, TIM_OCInitTypeDef::TIM_OCMode, TIM_OCInitTypeDef::TIM_OCNIdleState, TIM_OCInitTypeDef::TIM_OCNPolarity, TIM_OCInitTypeDef::TIM_OCPolarity, TIM_OCInitTypeDef::TIM_OutputNState, TIM_OCInitTypeDef::TIM_OutputState, and TIM_OCInitTypeDef::TIM_Pulse.

Referenced by main().

void TIM_OC3NPolarityConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_OCNPolarity
 | ) |  |

Configures the TIMx Channel 3N polarity.

Parameters:
TIMx,: where x can be 1 or 8 to select the TIM peripheral.
TIM_OCNPolarity,: specifies the OC3N Polarity This parameter can be one of the following values:

  • TIM_OCNPolarity_High: Output Compare active high
  • TIM_OCNPolarity_Low: Output Compare active low
Return values:
None

Definition at line 1922 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CCER, IS_TIM_LIST1_PERIPH, IS_TIM_OCN_POLARITY, and TIM_CCER_CC3NP.

void TIM_OC3PolarityConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_OCPolarity
 | ) |  |

Configures the TIMx channel 3 polarity.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
TIM_OCPolarity,: specifies the OC3 Polarity This parameter can be one of the following values:

  • TIM_OCPolarity_High: Output Compare active high
  • TIM_OCPolarity_Low: Output Compare active low
Return values:
None

Definition at line 1899 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CCER, IS_TIM_LIST3_PERIPH, IS_TIM_OC_POLARITY, and TIM_CCER_CC3P.

void TIM_OC3PreloadConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_OCPreload
 | ) |  |

Enables or disables the TIMx peripheral Preload register on CCR3.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
TIM_OCPreload,: new state of the TIMx peripheral Preload register This parameter can be one of the following values:

  • TIM_OCPreload_Enable
  • TIM_OCPreload_Disable
Return values:
None

Definition at line 1558 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CCMR2, IS_TIM_LIST3_PERIPH, IS_TIM_OCPRELOAD_STATE, and TIM_CCMR2_OC3PE.

Referenced by main().

void TIM_OC4FastConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_OCFast
 | ) |  |

Configures the TIMx Output Compare 4 Fast feature.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
TIM_OCFast,: new state of the Output Compare Fast Enable Bit. This parameter can be one of the following values:

  • TIM_OCFast_Enable: TIM output compare fast enable
  • TIM_OCFast_Disable: TIM output compare fast disable
Return values:
None

Definition at line 1682 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CCMR2, IS_TIM_LIST3_PERIPH, IS_TIM_OCFAST_STATE, and TIM_CCMR2_OC4FE.

void TIM_OC4Init | ( | TIM_TypeDef * | TIMx,
 |  | TIM_OCInitTypeDef * | TIM_OCInitStruct
 | ) |  |

Initializes the TIMx Channel4 according to the specified parameters in the TIM_OCInitStruct.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
TIM_OCInitStruct,: pointer to a TIM_OCInitTypeDef structure that contains the configuration information for the specified TIM peripheral.
Return values:
None

Definition at line 523 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CCER, TIM_TypeDef::CCMR2, TIM_TypeDef::CCR4, TIM_TypeDef::CR2, IS_TIM_LIST3_PERIPH, IS_TIM_OC_MODE, IS_TIM_OC_POLARITY, IS_TIM_OCIDLE_STATE, IS_TIM_OUTPUT_STATE, TIM1, TIM8, TIM_CCER_CC4E, TIM_CCER_CC4P, TIM_CCMR2_CC4S, TIM_CCMR2_OC4M, TIM_CR2_OIS4, TIM_OCInitTypeDef::TIM_OCIdleState, TIM_OCInitTypeDef::TIM_OCMode, TIM_OCInitTypeDef::TIM_OCPolarity, TIM_OCInitTypeDef::TIM_OutputState, and TIM_OCInitTypeDef::TIM_Pulse.

Referenced by main().

void TIM_OC4PolarityConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_OCPolarity
 | ) |  |

Configures the TIMx channel 4 polarity.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
TIM_OCPolarity,: specifies the OC4 Polarity This parameter can be one of the following values:

  • TIM_OCPolarity_High: Output Compare active high
  • TIM_OCPolarity_Low: Output Compare active low
Return values:
None

Definition at line 1947 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CCER, IS_TIM_LIST3_PERIPH, IS_TIM_OC_POLARITY, and TIM_CCER_CC4P.

void TIM_OC4PreloadConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_OCPreload
 | ) |  |

Enables or disables the TIMx peripheral Preload register on CCR4.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
TIM_OCPreload,: new state of the TIMx peripheral Preload register This parameter can be one of the following values:

  • TIM_OCPreload_Enable
  • TIM_OCPreload_Disable
Return values:
None

Definition at line 1582 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CCMR2, IS_TIM_LIST3_PERIPH, IS_TIM_OCPRELOAD_STATE, and TIM_CCMR2_OC4PE.

Referenced by main().

void TIM_OCStructInit ( TIM_OCInitTypeDef * TIM_OCInitStruct )

Fills each TIM_OCInitStruct member with its default value.

Parameters:
TIM_OCInitStruct : pointer to a TIM_OCInitTypeDef structure which will be initialized.
Return values:
None

Definition at line 752 of file stm32f10x_tim.c.

References TIM_OCInitTypeDef::TIM_OCIdleState, TIM_OCIdleState_Reset, TIM_OCInitTypeDef::TIM_OCMode, TIM_OCMode_Timing, TIM_OCInitTypeDef::TIM_OCNIdleState, TIM_OCNIdleState_Reset, TIM_OCInitTypeDef::TIM_OCNPolarity, TIM_OCInitTypeDef::TIM_OCPolarity, TIM_OCPolarity_High, TIM_OCInitTypeDef::TIM_OutputNState, TIM_OutputNState_Disable, TIM_OCInitTypeDef::TIM_OutputState, TIM_OutputState_Disable, and TIM_OCInitTypeDef::TIM_Pulse.

Referenced by TIM_Config().

void TIM_PrescalerConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | Prescaler,
 |  | uint16_t | TIM_PSCReloadMode
 | ) |  |

Configures the TIMx Prescaler.

Parameters:
TIMx,: where x can be 1 to 17 to select the TIM peripheral.
Prescaler,: specifies the Prescaler Register value
TIM_PSCReloadMode,: specifies the TIM Prescaler Reload mode This parameter can be one of the following values:

  • TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event.
  • TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediately.
Return values:
None

Definition at line 1176 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::EGR, IS_TIM_ALL_PERIPH, IS_TIM_PRESCALER_RELOAD, and TIM_TypeDef::PSC.

Referenced by main(), TIM5_ConfigForLSI(), and TIM_Config().

void TIM_PWMIConfig | ( | TIM_TypeDef * | TIMx,
 |  | TIM_ICInitTypeDef * | TIM_ICInitStruct
 | ) |  |

Configures the TIM peripheral according to the specified parameters in the TIM_ICInitStruct to measure an external PWM signal.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
TIM_ICInitStruct,: pointer to a TIM_ICInitTypeDef structure that contains the configuration information for the specified TIM peripheral.
Return values:
None

Definition at line 654 of file stm32f10x_tim.c.

References assert_param, IS_TIM_LIST6_PERIPH, TI1_Config(), TI2_Config(), TIM_ICInitTypeDef::TIM_Channel, TIM_Channel_1, TIM_ICInitTypeDef::TIM_ICFilter, TIM_ICInitTypeDef::TIM_ICPolarity, TIM_ICPolarity_Falling, TIM_ICPolarity_Rising, TIM_ICInitTypeDef::TIM_ICPrescaler, TIM_ICInitTypeDef::TIM_ICSelection, TIM_ICSelection_DirectTI, TIM_ICSelection_IndirectTI, TIM_SetIC1Prescaler(), and TIM_SetIC2Prescaler().

Referenced by main().

void TIM_SelectCCDMA | ( | TIM_TypeDef * | TIMx,
 |  | FunctionalState | NewState
 | ) |  |

Selects the TIMx peripheral Capture Compare DMA source.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5, 8, 15, 16 or 17 to select the TIM peripheral.
NewState,: new state of the Capture Compare DMA source This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1458 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CR2, DISABLE, IS_FUNCTIONAL_STATE, IS_TIM_LIST4_PERIPH, and TIM_CR2_CCDS.

void TIM_SelectCOM | ( | TIM_TypeDef * | TIMx,
 |  | FunctionalState | NewState
 | ) |  |

Selects the TIM peripheral Commutation event.

Parameters:
TIMx,: where x can be 1, 8, 15, 16 or 17 to select the TIMx peripheral
NewState,: new state of the Commutation event. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1433 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CR2, DISABLE, IS_FUNCTIONAL_STATE, IS_TIM_LIST2_PERIPH, and TIM_CR2_CCUS.

void TIM_SelectHallSensor | ( | TIM_TypeDef * | TIMx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the TIMx's Hall sensor interface.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
NewState,: new state of the TIMx Hall sensor interface. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 2144 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CR2, DISABLE, IS_FUNCTIONAL_STATE, IS_TIM_LIST6_PERIPH, and TIM_CR2_TI1S.

void TIM_SelectInputTrigger | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_InputTriggerSource
 | ) |  |

Selects the Input Trigger source.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
TIM_InputTriggerSource,: The Input Trigger source. This parameter can be one of the following values:

  • TIM_TS_ITR0: Internal Trigger 0
  • TIM_TS_ITR1: Internal Trigger 1
  • TIM_TS_ITR2: Internal Trigger 2
  • TIM_TS_ITR3: Internal Trigger 3
  • TIM_TS_TI1F_ED: TI1 Edge Detector
  • TIM_TS_TI1FP1: Filtered Timer Input 1
  • TIM_TS_TI2FP2: Filtered Timer Input 2
  • TIM_TS_ETRF: External Trigger input
Return values:
None

Definition at line 1229 of file stm32f10x_tim.c.

References assert_param, IS_TIM_LIST6_PERIPH, IS_TIM_TRIGGER_SELECTION, TIM_TypeDef::SMCR, and TIM_SMCR_TS.

Referenced by main(), TIM_ITRxExternalClockConfig(), and TIM_TIxExternalClockConfig().

void TIM_SelectMasterSlaveMode | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_MasterSlaveMode
 | ) |  |

Sets or Resets the TIMx Master/Slave Mode.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
TIM_MasterSlaveMode,: specifies the Timer Master Slave Mode. This parameter can be one of the following values:

  • TIM_MasterSlaveMode_Enable: synchronization between the current timer and its slaves (through TRGO).
  • TIM_MasterSlaveMode_Disable: No action
Return values:
None

Definition at line 2246 of file stm32f10x_tim.c.

References assert_param, IS_TIM_LIST6_PERIPH, IS_TIM_MSM_STATE, TIM_TypeDef::SMCR, and TIM_SMCR_MSM.

Referenced by main().

void TIM_SelectOCxM | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_Channel,
 |  | uint16_t | TIM_OCMode
 | ) |  |

Selects the TIM Output Compare Mode.

Note:
This function disables the selected channel before changing the Output Compare Mode. User has to enable this channel using TIM_CCxCmd and TIM_CCxNCmd functions.
Parameters:
TIMx,: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
TIM_Channel,: specifies the TIM Channel This parameter can be one of the following values:

  • TIM_Channel_1: TIM Channel 1
  • TIM_Channel_2: TIM Channel 2
  • TIM_Channel_3: TIM Channel 3
  • TIM_Channel_4: TIM Channel 4
TIM_OCMode,: specifies the TIM Output Compare Mode. This parameter can be one of the following values:

  • TIM_OCMode_Timing
  • TIM_OCMode_Active
  • TIM_OCMode_Toggle
  • TIM_OCMode_PWM1
  • TIM_OCMode_PWM2
  • TIM_ForcedAction_Active
  • TIM_ForcedAction_InActive
Return values:
None

Definition at line 2045 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CCER, CCER_CCE_Set, CCMR_Offset, IS_TIM_CHANNEL, IS_TIM_LIST8_PERIPH, IS_TIM_OCM, TIM_CCMR1_OC1M, TIM_CCMR1_OC2M, TIM_Channel_1, and TIM_Channel_3.

Referenced by TIM1_TRG_COM_IRQHandler().

void TIM_SelectOnePulseMode | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_OPMode
 | ) |  |

Selects the TIMx's One Pulse Mode.

Parameters:
TIMx,: where x can be 1 to 17 to select the TIM peripheral.
TIM_OPMode,: specifies the OPM Mode to be used. This parameter can be one of the following values:

  • TIM_OPMode_Single
  • TIM_OPMode_Repetitive
Return values:
None

Definition at line 2170 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CR1, IS_TIM_ALL_PERIPH, IS_TIM_OPM_MODE, and TIM_CR1_OPM.

Referenced by main().

void TIM_SelectOutputTrigger | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_TRGOSource
 | ) |  |

Selects the TIMx Trigger Output Mode.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5, 6, 7, 8, 9, 12 or 15 to select the TIM peripheral.
TIM_TRGOSource,: specifies the Trigger Output source. This paramter can be one of the following values:
  • For all TIMx
    • TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output (TRGO).
    • TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output (TRGO).
    • TIM_TRGOSource_Update: The update event is selected as the trigger output (TRGO).
  • For all TIMx except TIM6 and TIM7
    • TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag is to be set, as soon as a capture or compare match occurs (TRGO).
    • TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output (TRGO).
    • TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output (TRGO).
    • TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output (TRGO).
    • TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output (TRGO).
    Return values:
    None

Definition at line 2202 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CR2, IS_TIM_LIST7_PERIPH, IS_TIM_TRGO_SOURCE, and TIM_CR2_MMS.

Referenced by main().

void TIM_SelectSlaveMode | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_SlaveMode
 | ) |  |

Selects the TIMx Slave Mode.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
TIM_SlaveMode,: specifies the Timer Slave Mode. This parameter can be one of the following values:

  • TIM_SlaveMode_Reset: Rising edge of the selected trigger signal (TRGI) re-initializes the counter and triggers an update of the registers.
  • TIM_SlaveMode_Gated: The counter clock is enabled when the trigger signal (TRGI) is high.
  • TIM_SlaveMode_Trigger: The counter starts at a rising edge of the trigger TRGI.
  • TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter.
Return values:
None

Definition at line 2225 of file stm32f10x_tim.c.

References assert_param, IS_TIM_LIST6_PERIPH, IS_TIM_SLAVE_MODE, TIM_TypeDef::SMCR, and TIM_SMCR_SMS.

Referenced by main().

void TIM_SetAutoreload | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | Autoreload
 | ) |  |

Sets the TIMx Autoreload Register value.

Parameters:
TIMx,: where x can be 1 to 17 to select the TIM peripheral.
Autoreload,: specifies the Autoreload register new value.
Return values:
None

Definition at line 2278 of file stm32f10x_tim.c.

References TIM_TypeDef::ARR, assert_param, and IS_TIM_ALL_PERIPH.

Referenced by main().

void TIM_SetClockDivision | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_CKD
 | ) |  |

Sets the TIMx Clock Division value.

Parameters:
TIMx,: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
TIM_CKD,: specifies the clock division value. This parameter can be one of the following value:

  • TIM_CKD_DIV1: TDTS = Tck_tim
  • TIM_CKD_DIV2: TDTS = 2*Tck_tim
  • TIM_CKD_DIV4: TDTS = 4*Tck_tim
Return values:
None

Definition at line 2441 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CR1, IS_TIM_CKD_DIV, IS_TIM_LIST8_PERIPH, and TIM_CR1_CKD.

void TIM_SetCompare1 | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | Compare1
 | ) |  |

Sets the TIMx Capture Compare1 Register value.

Parameters:
TIMx,: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
Compare1,: specifies the Capture Compare1 register new value.
Return values:
None

Definition at line 2292 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CCR1, and IS_TIM_LIST8_PERIPH.

Referenced by TIM1_BRK_TIM9_IRQHandler(), TIM2_IRQHandler(), and TIM3_IRQHandler().

void TIM_SetCompare2 | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | Compare2
 | ) |  |

Sets the TIMx Capture Compare2 Register value.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
Compare2,: specifies the Capture Compare2 register new value.
Return values:
None

Definition at line 2306 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CCR2, and IS_TIM_LIST6_PERIPH.

Referenced by TIM1_BRK_TIM9_IRQHandler(), TIM2_IRQHandler(), and TIM3_IRQHandler().

void TIM_SetCompare3 | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | Compare3
 | ) |  |

Sets the TIMx Capture Compare3 Register value.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
Compare3,: specifies the Capture Compare3 register new value.
Return values:
None

Definition at line 2320 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CCR3, and IS_TIM_LIST3_PERIPH.

Referenced by TIM2_IRQHandler(), and TIM3_IRQHandler().

void TIM_SetCompare4 | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | Compare4
 | ) |  |

Sets the TIMx Capture Compare4 Register value.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
Compare4,: specifies the Capture Compare4 register new value.
Return values:
None

Definition at line 2334 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CCR4, and IS_TIM_LIST3_PERIPH.

Referenced by TIM2_IRQHandler(), and TIM3_IRQHandler().

void TIM_SetCounter | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | Counter
 | ) |  |

Sets the TIMx Counter Register value.

Parameters:
TIMx,: where x can be 1 to 17 to select the TIM peripheral.
Counter,: specifies the Counter register new value.
Return values:
None

Definition at line 2264 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CNT, Counter, and IS_TIM_ALL_PERIPH.

void TIM_SetIC1Prescaler | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_ICPSC
 | ) |  |

Sets the TIMx Input Capture 1 prescaler.

Parameters:
TIMx,: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
TIM_ICPSC,: specifies the Input Capture1 prescaler new value. This parameter can be one of the following values:

  • TIM_ICPSC_DIV1: no prescaler
  • TIM_ICPSC_DIV2: capture is done once every 2 events
  • TIM_ICPSC_DIV4: capture is done once every 4 events
  • TIM_ICPSC_DIV8: capture is done once every 8 events
Return values:
None

Definition at line 2353 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CCMR1, IS_TIM_IC_PRESCALER, IS_TIM_LIST8_PERIPH, and TIM_CCMR1_IC1PSC.

Referenced by TIM_ICInit(), and TIM_PWMIConfig().

void TIM_SetIC2Prescaler | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_ICPSC
 | ) |  |

Sets the TIMx Input Capture 2 prescaler.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
TIM_ICPSC,: specifies the Input Capture2 prescaler new value. This parameter can be one of the following values:

  • TIM_ICPSC_DIV1: no prescaler
  • TIM_ICPSC_DIV2: capture is done once every 2 events
  • TIM_ICPSC_DIV4: capture is done once every 4 events
  • TIM_ICPSC_DIV8: capture is done once every 8 events
Return values:
None

Definition at line 2375 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CCMR1, IS_TIM_IC_PRESCALER, IS_TIM_LIST6_PERIPH, and TIM_CCMR1_IC2PSC.

Referenced by TIM_ICInit(), and TIM_PWMIConfig().

void TIM_SetIC3Prescaler | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_ICPSC
 | ) |  |

Sets the TIMx Input Capture 3 prescaler.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
TIM_ICPSC,: specifies the Input Capture3 prescaler new value. This parameter can be one of the following values:

  • TIM_ICPSC_DIV1: no prescaler
  • TIM_ICPSC_DIV2: capture is done once every 2 events
  • TIM_ICPSC_DIV4: capture is done once every 4 events
  • TIM_ICPSC_DIV8: capture is done once every 8 events
Return values:
None

Definition at line 2397 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CCMR2, IS_TIM_IC_PRESCALER, IS_TIM_LIST3_PERIPH, and TIM_CCMR2_IC3PSC.

Referenced by TIM_ICInit().

void TIM_SetIC4Prescaler | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_ICPSC
 | ) |  |

Sets the TIMx Input Capture 4 prescaler.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
TIM_ICPSC,: specifies the Input Capture4 prescaler new value. This parameter can be one of the following values:

  • TIM_ICPSC_DIV1: no prescaler
  • TIM_ICPSC_DIV2: capture is done once every 2 events
  • TIM_ICPSC_DIV4: capture is done once every 4 events
  • TIM_ICPSC_DIV8: capture is done once every 8 events
Return values:
None

Definition at line 2419 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CCMR2, IS_TIM_IC_PRESCALER, IS_TIM_LIST3_PERIPH, and TIM_CCMR2_IC4PSC.

Referenced by TIM_ICInit().

void TIM_TimeBaseInit | ( | TIM_TypeDef * | TIMx,
 |  | TIM_TimeBaseInitTypeDef * | TIM_TimeBaseInitStruct
 | ) |  |

Initializes the TIMx Time Base Unit peripheral according to the specified parameters in the TIM_TimeBaseInitStruct.

Parameters:
TIMx,: where x can be 1 to 17 to select the TIM peripheral.
TIM_TimeBaseInitStruct,: pointer to a TIM_TimeBaseInitTypeDef structure that contains the configuration information for the specified TIM peripheral.
Return values:
None

Definition at line 226 of file stm32f10x_tim.c.

References TIM_TypeDef::ARR, assert_param, TIM_TypeDef::CR1, TIM_TypeDef::EGR, IS_TIM_ALL_PERIPH, IS_TIM_CKD_DIV, IS_TIM_COUNTER_MODE, TIM_TypeDef::PSC, TIM_TypeDef::RCR, TIM1, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM_TimeBaseInitTypeDef::TIM_ClockDivision, TIM_TimeBaseInitTypeDef::TIM_CounterMode, TIM_CR1_CKD, TIM_CR1_CMS, TIM_CR1_DIR, TIM_TimeBaseInitTypeDef::TIM_Period, TIM_TimeBaseInitTypeDef::TIM_Prescaler, TIM_PSCReloadMode_Immediate, and TIM_TimeBaseInitTypeDef::TIM_RepetitionCounter.

Referenced by main(), and TIM_Config().

void TIM_TimeBaseStructInit ( TIM_TimeBaseInitTypeDef * TIM_TimeBaseInitStruct )

Fills each TIM_TimeBaseInitStruct member with its default value.

Parameters:
TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef structure which will be initialized.
Return values:
None

Definition at line 736 of file stm32f10x_tim.c.

References TIM_CKD_DIV1, TIM_TimeBaseInitTypeDef::TIM_ClockDivision, TIM_TimeBaseInitTypeDef::TIM_CounterMode, TIM_CounterMode_Up, TIM_TimeBaseInitTypeDef::TIM_Period, TIM_TimeBaseInitTypeDef::TIM_Prescaler, and TIM_TimeBaseInitTypeDef::TIM_RepetitionCounter.

Referenced by main().

void TIM_TIxExternalClockConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_TIxExternalCLKSource,
 |  | uint16_t | TIM_ICPolarity,
 |  | uint16_t | ICFilter
 | ) |  |

Configures the TIMx Trigger as External Clock.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5, 9, 12 or 15 to select the TIM peripheral.
TIM_TIxExternalCLKSource,: Trigger source. This parameter can be one of the following values:

  • TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector
  • TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1
  • TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2
TIM_ICPolarity,: specifies the TIx Polarity. This parameter can be one of the following values:

  • TIM_ICPolarity_Rising
  • TIM_ICPolarity_Falling
ICFilter : specifies the filter value. This parameter must be a value between 0x0 and 0xF.
Return values:
None

Definition at line 1035 of file stm32f10x_tim.c.

References assert_param, IS_TIM_IC_FILTER, IS_TIM_IC_POLARITY, IS_TIM_LIST6_PERIPH, IS_TIM_TIXCLK_SOURCE, TIM_TypeDef::SMCR, TI1_Config(), TI2_Config(), TIM_ICSelection_DirectTI, TIM_SelectInputTrigger(), TIM_SlaveMode_External1, and TIM_TIxExternalCLK1Source_TI2.

void TIM_UpdateDisableConfig | ( | TIM_TypeDef * | TIMx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or Disables the TIMx Update event.

Parameters:
TIMx,: where x can be 1 to 17 to select the TIM peripheral.
NewState,: new state of the TIMx UDIS bit This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 2092 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CR1, DISABLE, IS_FUNCTIONAL_STATE, IS_TIM_ALL_PERIPH, and TIM_CR1_UDIS.

void TIM_UpdateRequestConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_UpdateSource
 | ) |  |

Configures the TIMx Update Request Interrupt source.

Parameters:
TIMx,: where x can be 1 to 17 to select the TIM peripheral.
TIM_UpdateSource,: specifies the Update source. This parameter can be one of the following values:

  • TIM_UpdateSource_Regular: Source of update is the counter overflow/underflow or the setting of UG bit, or an update generation through the slave mode controller.
  • TIM_UpdateSource_Global: Source of update is counter overflow/underflow.
Return values:
None

Definition at line 2120 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CR1, IS_TIM_ALL_PERIPH, IS_TIM_UPDATE_SOURCE, TIM_CR1_URS, and TIM_UpdateSource_Global.


STM32F10x Standard Peripherals Firmware Library: TIM_Private_TypesDefinitions

TIM_Private_TypesDefinitions

TIM


STM32F10x Standard Peripherals Firmware Library: TIM_Private_Defines

Defines

TIM_Private_Defines

TIM

Defines

#define | CCER_CCE_Set ((uint16_t)0x0001)
#define | CCER_CCNE_Set ((uint16_t)0x0004)
#define | CCMR_Offset ((uint16_t)0x0018)
#define | SMCR_ETR_Mask ((uint16_t)0x00FF)

Define Documentation

#define CCER_CCE_Set ((uint16_t)0x0001)

Definition at line 50 of file stm32f10x_tim.c.

Referenced by TIM_CCxCmd(), and TIM_SelectOCxM().

#define CCER_CCNE_Set ((uint16_t)0x0004)

Definition at line 51 of file stm32f10x_tim.c.

Referenced by TIM_CCxNCmd().

#define CCMR_Offset ((uint16_t)0x0018)

Definition at line 49 of file stm32f10x_tim.c.

Referenced by TIM_SelectOCxM().

#define SMCR_ETR_Mask ((uint16_t)0x00FF)

Definition at line 48 of file stm32f10x_tim.c.

Referenced by TIM_ETRConfig().


STM32F10x Standard Peripherals Firmware Library: TIM_Private_Macros

TIM_Private_Macros

TIM


STM32F10x Standard Peripherals Firmware Library: TIM_Private_Variables

TIM_Private_Variables

TIM


STM32F10x Standard Peripherals Firmware Library: TIM_Private_FunctionPrototypes

TIM_Private_FunctionPrototypes

TIM


STM32F10x Standard Peripherals Firmware Library: TIM_Private_Functions

Functions

TIM_Private_Functions

TIM

Functions

static void | TI1_Config (TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, uint16_t TIM_ICFilter)
Configure the TI1 as Input.
static void | TI2_Config (TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, uint16_t TIM_ICFilter)
Configure the TI2 as Input.
static void | TI3_Config (TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, uint16_t TIM_ICFilter)
Configure the TI3 as Input.
static void | TI4_Config (TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, uint16_t TIM_ICFilter)
Configure the TI4 as Input.
void | TIM_ARRPreloadConfig (TIM_TypeDef *TIMx, FunctionalState NewState)
Enables or disables TIMx peripheral Preload register on ARR.
void | TIM_BDTRConfig (TIM_TypeDef *TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)
Configures the: Break feature, dead time, Lock level, the OSSI, the OSSR State and the AOE(automatic output enable).
void | TIM_BDTRStructInit (TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)
Fills each TIM_BDTRInitStruct member with its default value.
void | TIM_CCPreloadControl (TIM_TypeDef *TIMx, FunctionalState NewState)
Sets or Resets the TIM peripheral Capture Compare Preload Control bit.
void | TIM_CCxCmd (TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx)
Enables or disables the TIM Capture Compare Channel x.
void | TIM_CCxNCmd (TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN)
Enables or disables the TIM Capture Compare Channel xN.
void | TIM_ClearFlag (TIM_TypeDef *TIMx, uint16_t TIM_FLAG)
Clears the TIMx's pending flags.
void | TIM_ClearITPendingBit (TIM_TypeDef *TIMx, uint16_t TIM_IT)
Clears the TIMx's interrupt pending bits.
void | TIM_ClearOC1Ref (TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
Clears or safeguards the OCREF1 signal on an external event.
void | TIM_ClearOC2Ref (TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
Clears or safeguards the OCREF2 signal on an external event.
void | TIM_ClearOC3Ref (TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
Clears or safeguards the OCREF3 signal on an external event.
void | TIM_ClearOC4Ref (TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
Clears or safeguards the OCREF4 signal on an external event.
void | TIM_Cmd (TIM_TypeDef *TIMx, FunctionalState NewState)
Enables or disables the specified TIM peripheral.
void | TIM_CounterModeConfig (TIM_TypeDef *TIMx, uint16_t TIM_CounterMode)
Specifies the TIMx Counter Mode to be used.
void | TIM_CtrlPWMOutputs (TIM_TypeDef *TIMx, FunctionalState NewState)
Enables or disables the TIM peripheral Main Outputs.
void | TIM_DeInit (TIM_TypeDef *TIMx)
Deinitializes the TIMx peripheral registers to their default reset values.
void | TIM_DMACmd (TIM_TypeDef *TIMx, uint16_t TIM_DMASource, FunctionalState NewState)
Enables or disables the TIMx's DMA Requests.
void | TIM_DMAConfig (TIM_TypeDef *TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)
Configures the TIMx's DMA interface.
void | TIM_EncoderInterfaceConfig (TIM_TypeDef *TIMx, uint16_t TIM_EncoderMode, uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity)
Configures the TIMx Encoder Interface.
void | TIM_ETRClockMode1Config (TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
Configures the External clock Mode1.
void | TIM_ETRClockMode2Config (TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
Configures the External clock Mode2.
void | TIM_ETRConfig (TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
Configures the TIMx External Trigger (ETR).
void | TIM_ForcedOC1Config (TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
Forces the TIMx output 1 waveform to active or inactive level.
void | TIM_ForcedOC2Config (TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
Forces the TIMx output 2 waveform to active or inactive level.
void | TIM_ForcedOC3Config (TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
Forces the TIMx output 3 waveform to active or inactive level.
void | TIM_ForcedOC4Config (TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
Forces the TIMx output 4 waveform to active or inactive level.
void | TIM_GenerateEvent (TIM_TypeDef *TIMx, uint16_t TIM_EventSource)
Configures the TIMx event to be generate by software.
uint16_t | TIM_GetCapture1 (TIM_TypeDef *TIMx)
Gets the TIMx Input Capture 1 value.
uint16_t | TIM_GetCapture2 (TIM_TypeDef *TIMx)
Gets the TIMx Input Capture 2 value.
uint16_t | TIM_GetCapture3 (TIM_TypeDef *TIMx)
Gets the TIMx Input Capture 3 value.
uint16_t | TIM_GetCapture4 (TIM_TypeDef *TIMx)
Gets the TIMx Input Capture 4 value.
uint16_t | TIM_GetCounter (TIM_TypeDef *TIMx)
Gets the TIMx Counter value.
FlagStatus | TIM_GetFlagStatus (TIM_TypeDef *TIMx, uint16_t TIM_FLAG)
Checks whether the specified TIM flag is set or not.
ITStatus | TIM_GetITStatus (TIM_TypeDef *TIMx, uint16_t TIM_IT)
Checks whether the TIM interrupt has occurred or not.
uint16_t | TIM_GetPrescaler (TIM_TypeDef *TIMx)
Gets the TIMx Prescaler value.
void | TIM_ICInit (TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct)
Initializes the TIM peripheral according to the specified parameters in the TIM_ICInitStruct.
void | TIM_ICStructInit (TIM_ICInitTypeDef *TIM_ICInitStruct)
Fills each TIM_ICInitStruct member with its default value.
void | TIM_InternalClockConfig (TIM_TypeDef *TIMx)
Configures the TIMx internal Clock.
void | TIM_ITConfig (TIM_TypeDef *TIMx, uint16_t TIM_IT, FunctionalState NewState)
Enables or disables the specified TIM interrupts.
void | TIM_ITRxExternalClockConfig (TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource)
Configures the TIMx Internal Trigger as External Clock.
void | TIM_OC1FastConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
Configures the TIMx Output Compare 1 Fast feature.
void | TIM_OC1Init (TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
Initializes the TIMx Channel1 according to the specified parameters in the TIM_OCInitStruct.
void | TIM_OC1NPolarityConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity)
Configures the TIMx Channel 1N polarity.
void | TIM_OC1PolarityConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
Configures the TIMx channel 1 polarity.
void | TIM_OC1PreloadConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
Enables or disables the TIMx peripheral Preload register on CCR1.
void | TIM_OC2FastConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
Configures the TIMx Output Compare 2 Fast feature.
void | TIM_OC2Init (TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
Initializes the TIMx Channel2 according to the specified parameters in the TIM_OCInitStruct.
void | TIM_OC2NPolarityConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity)
Configures the TIMx Channel 2N polarity.
void | TIM_OC2PolarityConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
Configures the TIMx channel 2 polarity.
void | TIM_OC2PreloadConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
Enables or disables the TIMx peripheral Preload register on CCR2.
void | TIM_OC3FastConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
Configures the TIMx Output Compare 3 Fast feature.
void | TIM_OC3Init (TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
Initializes the TIMx Channel3 according to the specified parameters in the TIM_OCInitStruct.
void | TIM_OC3NPolarityConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity)
Configures the TIMx Channel 3N polarity.
void | TIM_OC3PolarityConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
Configures the TIMx channel 3 polarity.
void | TIM_OC3PreloadConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
Enables or disables the TIMx peripheral Preload register on CCR3.
void | TIM_OC4FastConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
Configures the TIMx Output Compare 4 Fast feature.
void | TIM_OC4Init (TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
Initializes the TIMx Channel4 according to the specified parameters in the TIM_OCInitStruct.
void | TIM_OC4PolarityConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
Configures the TIMx channel 4 polarity.
void | TIM_OC4PreloadConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
Enables or disables the TIMx peripheral Preload register on CCR4.
void | TIM_OCStructInit (TIM_OCInitTypeDef *TIM_OCInitStruct)
Fills each TIM_OCInitStruct member with its default value.
void | TIM_PrescalerConfig (TIM_TypeDef *TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)
Configures the TIMx Prescaler.
void | TIM_PWMIConfig (TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct)
Configures the TIM peripheral according to the specified parameters in the TIM_ICInitStruct to measure an external PWM signal.
void | TIM_SelectCCDMA (TIM_TypeDef *TIMx, FunctionalState NewState)
Selects the TIMx peripheral Capture Compare DMA source.
void | TIM_SelectCOM (TIM_TypeDef *TIMx, FunctionalState NewState)
Selects the TIM peripheral Commutation event.
void | TIM_SelectHallSensor (TIM_TypeDef *TIMx, FunctionalState NewState)
Enables or disables the TIMx's Hall sensor interface.
void | TIM_SelectInputTrigger (TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource)
Selects the Input Trigger source.
void | TIM_SelectMasterSlaveMode (TIM_TypeDef *TIMx, uint16_t TIM_MasterSlaveMode)
Sets or Resets the TIMx Master/Slave Mode.
void | TIM_SelectOCxM (TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode)
Selects the TIM Output Compare Mode.
void | TIM_SelectOnePulseMode (TIM_TypeDef *TIMx, uint16_t TIM_OPMode)
Selects the TIMx's One Pulse Mode.
void | TIM_SelectOutputTrigger (TIM_TypeDef *TIMx, uint16_t TIM_TRGOSource)
Selects the TIMx Trigger Output Mode.
void | TIM_SelectSlaveMode (TIM_TypeDef *TIMx, uint16_t TIM_SlaveMode)
Selects the TIMx Slave Mode.
void | TIM_SetAutoreload (TIM_TypeDef *TIMx, uint16_t Autoreload)
Sets the TIMx Autoreload Register value.
void | TIM_SetClockDivision (TIM_TypeDef *TIMx, uint16_t TIM_CKD)
Sets the TIMx Clock Division value.
void | TIM_SetCompare1 (TIM_TypeDef *TIMx, uint16_t Compare1)
Sets the TIMx Capture Compare1 Register value.
void | TIM_SetCompare2 (TIM_TypeDef *TIMx, uint16_t Compare2)
Sets the TIMx Capture Compare2 Register value.
void | TIM_SetCompare3 (TIM_TypeDef *TIMx, uint16_t Compare3)
Sets the TIMx Capture Compare3 Register value.
void | TIM_SetCompare4 (TIM_TypeDef *TIMx, uint16_t Compare4)
Sets the TIMx Capture Compare4 Register value.
void | TIM_SetCounter (TIM_TypeDef *TIMx, uint16_t Counter)
Sets the TIMx Counter Register value.
void | TIM_SetIC1Prescaler (TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
Sets the TIMx Input Capture 1 prescaler.
void | TIM_SetIC2Prescaler (TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
Sets the TIMx Input Capture 2 prescaler.
void | TIM_SetIC3Prescaler (TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
Sets the TIMx Input Capture 3 prescaler.
void | TIM_SetIC4Prescaler (TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
Sets the TIMx Input Capture 4 prescaler.
void | TIM_TimeBaseInit (TIM_TypeDef *TIMx, TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct)
Initializes the TIMx Time Base Unit peripheral according to the specified parameters in the TIM_TimeBaseInitStruct.
void | TIM_TimeBaseStructInit (TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct)
Fills each TIM_TimeBaseInitStruct member with its default value.
void | TIM_TIxExternalClockConfig (TIM_TypeDef *TIMx, uint16_t TIM_TIxExternalCLKSource, uint16_t TIM_ICPolarity, uint16_t ICFilter)
Configures the TIMx Trigger as External Clock.
void | TIM_UpdateDisableConfig (TIM_TypeDef *TIMx, FunctionalState NewState)
Enables or Disables the TIMx Update event.
void | TIM_UpdateRequestConfig (TIM_TypeDef *TIMx, uint16_t TIM_UpdateSource)
Configures the TIMx Update Request Interrupt source.

Function Documentation

static void TI1_Config | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_ICPolarity,
 |  | uint16_t | TIM_ICSelection,
 |  | uint16_t | TIM_ICFilter
 | ) |  | [static]

Configure the TI1 as Input.

Parameters:
TIMx,: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
TIM_ICPolarity : The Input Polarity. This parameter can be one of the following values:

  • TIM_ICPolarity_Rising
  • TIM_ICPolarity_Falling
TIM_ICSelection,: specifies the input to be used. This parameter can be one of the following values:

  • TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
  • TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
  • TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
TIM_ICFilter,: Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values:
None

Definition at line 2701 of file stm32f10x_tim.c.

References TIM_TypeDef::CCER, TIM_TypeDef::CCMR1, TIM1, TIM2, TIM3, TIM4, TIM5, TIM8, TIM_CCER_CC1E, TIM_CCER_CC1NP, TIM_CCER_CC1P, TIM_CCMR1_CC1S, and TIM_CCMR1_IC1F.

Referenced by TIM_ICInit(), TIM_PWMIConfig(), and TIM_TIxExternalClockConfig().

static void TI2_Config | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_ICPolarity,
 |  | uint16_t | TIM_ICSelection,
 |  | uint16_t | TIM_ICFilter
 | ) |  | [static]

Configure the TI2 as Input.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
TIM_ICPolarity : The Input Polarity. This parameter can be one of the following values:

  • TIM_ICPolarity_Rising
  • TIM_ICPolarity_Falling
TIM_ICSelection,: specifies the input to be used. This parameter can be one of the following values:

  • TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
  • TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
  • TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
TIM_ICFilter,: Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values:
None

Definition at line 2748 of file stm32f10x_tim.c.

References TIM_TypeDef::CCER, TIM_TypeDef::CCMR1, TIM1, TIM2, TIM3, TIM4, TIM5, TIM8, TIM_CCER_CC2E, TIM_CCER_CC2NP, TIM_CCER_CC2P, TIM_CCMR1_CC2S, and TIM_CCMR1_IC2F.

Referenced by TIM_ICInit(), TIM_PWMIConfig(), and TIM_TIxExternalClockConfig().

static void TI3_Config | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_ICPolarity,
 |  | uint16_t | TIM_ICSelection,
 |  | uint16_t | TIM_ICFilter
 | ) |  | [static]

Configure the TI3 as Input.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
TIM_ICPolarity : The Input Polarity. This parameter can be one of the following values:

  • TIM_ICPolarity_Rising
  • TIM_ICPolarity_Falling
TIM_ICSelection,: specifies the input to be used. This parameter can be one of the following values:

  • TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
  • TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
  • TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
TIM_ICFilter,: Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values:
None

Definition at line 2797 of file stm32f10x_tim.c.

References TIM_TypeDef::CCER, TIM_TypeDef::CCMR2, TIM1, TIM2, TIM3, TIM4, TIM5, TIM8, TIM_CCER_CC3E, TIM_CCER_CC3NP, TIM_CCER_CC3P, TIM_CCMR2_CC3S, and TIM_CCMR2_IC3F.

Referenced by TIM_ICInit().

static void TI4_Config | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_ICPolarity,
 |  | uint16_t | TIM_ICSelection,
 |  | uint16_t | TIM_ICFilter
 | ) |  | [static]

Configure the TI4 as Input.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
TIM_ICPolarity : The Input Polarity. This parameter can be one of the following values:

  • TIM_ICPolarity_Rising
  • TIM_ICPolarity_Falling
TIM_ICSelection,: specifies the input to be used. This parameter can be one of the following values:

  • TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
  • TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
  • TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
TIM_ICFilter,: Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values:
None

Definition at line 2845 of file stm32f10x_tim.c.

References TIM_TypeDef::CCER, TIM_TypeDef::CCMR2, TIM1, TIM2, TIM3, TIM4, TIM5, TIM8, TIM_CCER_CC3P, TIM_CCER_CC4E, TIM_CCER_CC4NP, TIM_CCER_CC4P, TIM_CCMR2_CC4S, and TIM_CCMR2_IC4F.

Referenced by TIM_ICInit().

void TIM_ARRPreloadConfig | ( | TIM_TypeDef * | TIMx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables TIMx peripheral Preload register on ARR.

Parameters:
TIMx,: where x can be 1 to 17 to select the TIM peripheral.
NewState,: new state of the TIMx peripheral Preload register This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1409 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CR1, DISABLE, IS_FUNCTIONAL_STATE, IS_TIM_ALL_PERIPH, and TIM_CR1_ARPE.

Referenced by main().

void TIM_BDTRConfig | ( | TIM_TypeDef * | TIMx,
 |  | TIM_BDTRInitTypeDef * | TIM_BDTRInitStruct
 | ) |  |

Configures the: Break feature, dead time, Lock level, the OSSI, the OSSR State and the AOE(automatic output enable).

Parameters:
TIMx,: where x can be 1 or 8 to select the TIM
TIM_BDTRInitStruct,: pointer to a TIM_BDTRInitTypeDef structure that contains the BDTR Register configuration information for the TIM peripheral.
Return values:
None

Definition at line 712 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::BDTR, IS_TIM_AUTOMATIC_OUTPUT_STATE, IS_TIM_BREAK_POLARITY, IS_TIM_BREAK_STATE, IS_TIM_LIST2_PERIPH, IS_TIM_LOCK_LEVEL, IS_TIM_OSSI_STATE, IS_TIM_OSSR_STATE, TIM_BDTRInitTypeDef::TIM_AutomaticOutput, TIM_BDTRInitTypeDef::TIM_Break, TIM_BDTRInitTypeDef::TIM_BreakPolarity, TIM_BDTRInitTypeDef::TIM_DeadTime, TIM_BDTRInitTypeDef::TIM_LOCKLevel, TIM_BDTRInitTypeDef::TIM_OSSIState, and TIM_BDTRInitTypeDef::TIM_OSSRState.

Referenced by main().

void TIM_BDTRStructInit ( TIM_BDTRInitTypeDef * TIM_BDTRInitStruct )

Fills each TIM_BDTRInitStruct member with its default value.

Parameters:
TIM_BDTRInitStruct,: pointer to a TIM_BDTRInitTypeDef structure which will be initialized.
Return values:
None

Definition at line 787 of file stm32f10x_tim.c.

References TIM_BDTRInitTypeDef::TIM_AutomaticOutput, TIM_AutomaticOutput_Disable, TIM_BDTRInitTypeDef::TIM_Break, TIM_Break_Disable, TIM_BDTRInitTypeDef::TIM_BreakPolarity, TIM_BreakPolarity_Low, TIM_BDTRInitTypeDef::TIM_DeadTime, TIM_BDTRInitTypeDef::TIM_LOCKLevel, TIM_LOCKLevel_OFF, TIM_BDTRInitTypeDef::TIM_OSSIState, TIM_OSSIState_Disable, TIM_BDTRInitTypeDef::TIM_OSSRState, and TIM_OSSRState_Disable.

void TIM_CCPreloadControl | ( | TIM_TypeDef * | TIMx,
 |  | FunctionalState | NewState
 | ) |  |

Sets or Resets the TIM peripheral Capture Compare Preload Control bit.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5, 8 or 15 to select the TIMx peripheral
NewState,: new state of the Capture Compare Preload Control bit This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1483 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CR2, DISABLE, IS_FUNCTIONAL_STATE, IS_TIM_LIST5_PERIPH, and TIM_CR2_CCPC.

Referenced by main().

void TIM_CCxCmd | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_Channel,
 |  | uint16_t | TIM_CCx
 | ) |  |

Enables or disables the TIM Capture Compare Channel x.

Parameters:
TIMx,: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
TIM_Channel,: specifies the TIM Channel This parameter can be one of the following values:

  • TIM_Channel_1: TIM Channel 1
  • TIM_Channel_2: TIM Channel 2
  • TIM_Channel_3: TIM Channel 3
  • TIM_Channel_4: TIM Channel 4
TIM_CCx,: specifies the TIM Channel CCxE bit new state. This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable.
Return values:
None

Definition at line 1974 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CCER, CCER_CCE_Set, IS_TIM_CCX, IS_TIM_CHANNEL, and IS_TIM_LIST8_PERIPH.

Referenced by TIM1_TRG_COM_IRQHandler().

void TIM_CCxNCmd | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_Channel,
 |  | uint16_t | TIM_CCxN
 | ) |  |

Enables or disables the TIM Capture Compare Channel xN.

Parameters:
TIMx,: where x can be 1, 8, 15, 16 or 17 to select the TIM peripheral.
TIM_Channel,: specifies the TIM Channel This parameter can be one of the following values:

  • TIM_Channel_1: TIM Channel 1
  • TIM_Channel_2: TIM Channel 2
  • TIM_Channel_3: TIM Channel 3
TIM_CCxN,: specifies the TIM Channel CCxNE bit new state. This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable.
Return values:
None

Definition at line 2004 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CCER, CCER_CCNE_Set, IS_TIM_CCXN, IS_TIM_COMPLEMENTARY_CHANNEL, and IS_TIM_LIST2_PERIPH.

Referenced by TIM1_TRG_COM_IRQHandler().

void TIM_ClearFlag | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_FLAG
 | ) |  |

Clears the TIMx's pending flags.

Parameters:
TIMx,: where x can be 1 to 17 to select the TIM peripheral.
TIM_FLAG,: specifies the flag bit to clear. This parameter can be any combination of the following values:

  • TIM_FLAG_Update: TIM update Flag
  • TIM_FLAG_CC1: TIM Capture Compare 1 Flag
  • TIM_FLAG_CC2: TIM Capture Compare 2 Flag
  • TIM_FLAG_CC3: TIM Capture Compare 3 Flag
  • TIM_FLAG_CC4: TIM Capture Compare 4 Flag
  • TIM_FLAG_COM: TIM Commutation Flag
  • TIM_FLAG_Trigger: TIM Trigger Flag
  • TIM_FLAG_Break: TIM Break Flag
  • TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag
  • TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag
  • TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag
  • TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag
Note:
  • TIM6 and TIM7 can have only one update flag.
  • TIM9, TIM12 and TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1, TIM_FLAG_CC2 or TIM_FLAG_Trigger.
  • TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1.
  • TIM_FLAG_Break is used only with TIM1, TIM8 and TIM15.
  • TIM_FLAG_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17.
Return values:
None

Definition at line 2600 of file stm32f10x_tim.c.

References assert_param, IS_TIM_ALL_PERIPH, IS_TIM_CLEAR_FLAG, and TIM_TypeDef::SR.

Referenced by TIM_Config().

void TIM_ClearITPendingBit | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_IT
 | ) |  |

Clears the TIMx's interrupt pending bits.

Parameters:
TIMx,: where x can be 1 to 17 to select the TIM peripheral.
TIM_IT,: specifies the pending bit to clear. This parameter can be any combination of the following values:

  • TIM_IT_Update: TIM1 update Interrupt source
  • TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
  • TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
  • TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
  • TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
  • TIM_IT_COM: TIM Commutation Interrupt source
  • TIM_IT_Trigger: TIM Trigger Interrupt source
  • TIM_IT_Break: TIM Break Interrupt source
Note:
  • TIM6 and TIM7 can generate only an update interrupt.
  • TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1, TIM_IT_CC2 or TIM_IT_Trigger.
  • TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1.
  • TIM_IT_Break is used only with TIM1, TIM8 and TIM15.
  • TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17.
Return values:
None

Definition at line 2676 of file stm32f10x_tim.c.

References assert_param, IS_TIM_ALL_PERIPH, IS_TIM_IT, and TIM_TypeDef::SR.

Referenced by TIM1_BRK_TIM9_IRQHandler(), TIM1_TRG_COM_IRQHandler(), TIM2_IRQHandler(), TIM3_IRQHandler(), TIM4_IRQHandler(), and TIM5_IRQHandler().

void TIM_ClearOC1Ref | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_OCClear
 | ) |  |

Clears or safeguards the OCREF1 signal on an external event.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
TIM_OCClear,: new state of the Output Compare Clear Enable Bit. This parameter can be one of the following values:

  • TIM_OCClear_Enable: TIM Output clear enable
  • TIM_OCClear_Disable: TIM Output clear disable
Return values:
None

Definition at line 1707 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CCMR1, IS_TIM_LIST3_PERIPH, IS_TIM_OCCLEAR_STATE, and TIM_CCMR1_OC1CE.

void TIM_ClearOC2Ref | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_OCClear
 | ) |  |

Clears or safeguards the OCREF2 signal on an external event.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
TIM_OCClear,: new state of the Output Compare Clear Enable Bit. This parameter can be one of the following values:

  • TIM_OCClear_Enable: TIM Output clear enable
  • TIM_OCClear_Disable: TIM Output clear disable
Return values:
None

Definition at line 1733 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CCMR1, IS_TIM_LIST3_PERIPH, IS_TIM_OCCLEAR_STATE, and TIM_CCMR1_OC2CE.

void TIM_ClearOC3Ref | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_OCClear
 | ) |  |

Clears or safeguards the OCREF3 signal on an external event.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
TIM_OCClear,: new state of the Output Compare Clear Enable Bit. This parameter can be one of the following values:

  • TIM_OCClear_Enable: TIM Output clear enable
  • TIM_OCClear_Disable: TIM Output clear disable
Return values:
None

Definition at line 1757 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CCMR2, IS_TIM_LIST3_PERIPH, IS_TIM_OCCLEAR_STATE, and TIM_CCMR2_OC3CE.

void TIM_ClearOC4Ref | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_OCClear
 | ) |  |

Clears or safeguards the OCREF4 signal on an external event.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
TIM_OCClear,: new state of the Output Compare Clear Enable Bit. This parameter can be one of the following values:

  • TIM_OCClear_Enable: TIM Output clear enable
  • TIM_OCClear_Disable: TIM Output clear disable
Return values:
None

Definition at line 1781 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CCMR2, IS_TIM_LIST3_PERIPH, IS_TIM_OCCLEAR_STATE, and TIM_CCMR2_OC4CE.

void TIM_Cmd | ( | TIM_TypeDef * | TIMx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified TIM peripheral.

Parameters:
TIMx,: where x can be 1 to 17 to select the TIMx peripheral.
NewState,: new state of the TIMx peripheral. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 806 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CR1, DISABLE, IS_FUNCTIONAL_STATE, IS_TIM_ALL_PERIPH, and TIM_CR1_CEN.

Referenced by main(), TIM5_ConfigForLSI(), TIM5_IRQHandler(), and TIM_Config().

void TIM_CounterModeConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_CounterMode
 | ) |  |

Specifies the TIMx Counter Mode to be used.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
TIM_CounterMode,: specifies the Counter Mode to be used This parameter can be one of the following values:

  • TIM_CounterMode_Up: TIM Up Counting Mode
  • TIM_CounterMode_Down: TIM Down Counting Mode
  • TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1
  • TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2
  • TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3
Return values:
None

Definition at line 1199 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CR1, IS_TIM_COUNTER_MODE, IS_TIM_LIST3_PERIPH, TIM_CR1_CMS, and TIM_CR1_DIR.

void TIM_CtrlPWMOutputs | ( | TIM_TypeDef * | TIMx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the TIM peripheral Main Outputs.

Parameters:
TIMx,: where x can be 1, 8, 15, 16 or 17 to select the TIMx peripheral.
NewState,: new state of the TIM peripheral Main Outputs. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 831 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::BDTR, DISABLE, IS_FUNCTIONAL_STATE, IS_TIM_LIST2_PERIPH, and TIM_BDTR_MOE.

Referenced by main().

void TIM_DeInit ( TIM_TypeDef * TIMx )

Deinitializes the TIMx peripheral registers to their default reset values.

Parameters:
TIMx,: where x can be 1 to 17 to select the TIM peripheral.
Return values:
None

Definition at line 122 of file stm32f10x_tim.c.

References assert_param, DISABLE, ENABLE, IS_TIM_ALL_PERIPH, RCC_APB1Periph_TIM12, RCC_APB1Periph_TIM13, RCC_APB1Periph_TIM14, RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4, RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7, RCC_APB1PeriphResetCmd(), RCC_APB2Periph_TIM1, RCC_APB2Periph_TIM10, RCC_APB2Periph_TIM11, RCC_APB2Periph_TIM15, RCC_APB2Periph_TIM16, RCC_APB2Periph_TIM17, RCC_APB2Periph_TIM8, RCC_APB2Periph_TIM9, RCC_APB2PeriphResetCmd(), TIM1, TIM10, TIM11, TIM12, TIM13, TIM14, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, and TIM9.

Referenced by main().

void TIM_DMACmd | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_DMASource,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the TIMx's DMA Requests.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5, 6, 7, 8, 15, 16 or 17 to select the TIM peripheral.
TIM_DMASource,: specifies the DMA Request sources. This parameter can be any combination of the following values:

  • TIM_DMA_Update: TIM update Interrupt source
  • TIM_DMA_CC1: TIM Capture Compare 1 DMA source
  • TIM_DMA_CC2: TIM Capture Compare 2 DMA source
  • TIM_DMA_CC3: TIM Capture Compare 3 DMA source
  • TIM_DMA_CC4: TIM Capture Compare 4 DMA source
  • TIM_DMA_COM: TIM Commutation DMA source
  • TIM_DMA_Trigger: TIM Trigger DMA source
NewState,: new state of the DMA Request sources. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 964 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::DIER, DISABLE, IS_FUNCTIONAL_STATE, IS_TIM_DMA_SOURCE, and IS_TIM_LIST9_PERIPH.

Referenced by main().

void TIM_DMAConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_DMABase,
 |  | uint16_t | TIM_DMABurstLength
 | ) |  |

Configures the TIMx's DMA interface.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5, 8, 15, 16 or 17 to select the TIM peripheral.
TIM_DMABase,: DMA Base address. This parameter can be one of the following values:

  • TIM_DMABase_CR, TIM_DMABase_CR2, TIM_DMABase_SMCR, TIM_DMABase_DIER, TIM1_DMABase_SR, TIM_DMABase_EGR, TIM_DMABase_CCMR1, TIM_DMABase_CCMR2, TIM_DMABase_CCER, TIM_DMABase_CNT, TIM_DMABase_PSC, TIM_DMABase_ARR, TIM_DMABase_RCR, TIM_DMABase_CCR1, TIM_DMABase_CCR2, TIM_DMABase_CCR3, TIM_DMABase_CCR4, TIM_DMABase_BDTR, TIM_DMABase_DCR.
TIM_DMABurstLength,: DMA Burst length. This parameter can be one value between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
Return values:
None

Definition at line 937 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::DCR, IS_TIM_DMA_BASE, IS_TIM_DMA_LENGTH, and IS_TIM_LIST4_PERIPH.

Referenced by main().

void TIM_EncoderInterfaceConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_EncoderMode,
 |  | uint16_t | TIM_IC1Polarity,
 |  | uint16_t | TIM_IC2Polarity
 | ) |  |

Configures the TIMx Encoder Interface.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
TIM_EncoderMode,: specifies the TIMx Encoder Mode. This parameter can be one of the following values:

  • TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level.
  • TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level.
  • TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
TIM_IC1Polarity,: specifies the IC1 Polarity This parameter can be one of the following values:

  • TIM_ICPolarity_Falling: IC Falling edge.
  • TIM_ICPolarity_Rising: IC Rising edge.
TIM_IC2Polarity,: specifies the IC2 Polarity This parameter can be one of the following values:

  • TIM_ICPolarity_Falling: IC Falling edge.
  • TIM_ICPolarity_Rising: IC Rising edge.
Return values:
None

Definition at line 1264 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CCER, TIM_TypeDef::CCMR1, IS_TIM_ENCODER_MODE, IS_TIM_IC_POLARITY, IS_TIM_LIST5_PERIPH, TIM_TypeDef::SMCR, TIM_CCER_CC1P, TIM_CCER_CC2P, TIM_CCMR1_CC1S, TIM_CCMR1_CC1S_0, TIM_CCMR1_CC2S, TIM_CCMR1_CC2S_0, and TIM_SMCR_SMS.

void TIM_ETRClockMode1Config | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_ExtTRGPrescaler,
 |  | uint16_t | TIM_ExtTRGPolarity,
 |  | uint16_t | ExtTRGFilter
 | ) |  |

Configures the External clock Mode1.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
TIM_ExtTRGPrescaler,: The external Trigger Prescaler. This parameter can be one of the following values:

  • TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
  • TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
  • TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
  • TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
TIM_ExtTRGPolarity,: The external Trigger Polarity. This parameter can be one of the following values:

  • TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
  • TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
ExtTRGFilter,: External Trigger Filter. This parameter must be a value between 0x00 and 0x0F
Return values:
None

Definition at line 1075 of file stm32f10x_tim.c.

References assert_param, IS_TIM_EXT_FILTER, IS_TIM_EXT_POLARITY, IS_TIM_EXT_PRESCALER, IS_TIM_LIST3_PERIPH, TIM_TypeDef::SMCR, TIM_ETRConfig(), TIM_SlaveMode_External1, TIM_SMCR_SMS, TIM_SMCR_TS, and TIM_TS_ETRF.

void TIM_ETRClockMode2Config | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_ExtTRGPrescaler,
 |  | uint16_t | TIM_ExtTRGPolarity,
 |  | uint16_t | ExtTRGFilter
 | ) |  |

Configures the External clock Mode2.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
TIM_ExtTRGPrescaler,: The external Trigger Prescaler. This parameter can be one of the following values:

  • TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
  • TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
  • TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
  • TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
TIM_ExtTRGPolarity,: The external Trigger Polarity. This parameter can be one of the following values:

  • TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
  • TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
ExtTRGFilter,: External Trigger Filter. This parameter must be a value between 0x00 and 0x0F
Return values:
None

Definition at line 1117 of file stm32f10x_tim.c.

References assert_param, IS_TIM_EXT_FILTER, IS_TIM_EXT_POLARITY, IS_TIM_EXT_PRESCALER, IS_TIM_LIST3_PERIPH, TIM_TypeDef::SMCR, TIM_ETRConfig(), and TIM_SMCR_ECE.

void TIM_ETRConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_ExtTRGPrescaler,
 |  | uint16_t | TIM_ExtTRGPolarity,
 |  | uint16_t | ExtTRGFilter
 | ) |  |

Configures the TIMx External Trigger (ETR).

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
TIM_ExtTRGPrescaler,: The external Trigger Prescaler. This parameter can be one of the following values:

  • TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
  • TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
  • TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
  • TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
TIM_ExtTRGPolarity,: The external Trigger Polarity. This parameter can be one of the following values:

  • TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
  • TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
ExtTRGFilter,: External Trigger Filter. This parameter must be a value between 0x00 and 0x0F
Return values:
None

Definition at line 1148 of file stm32f10x_tim.c.

References assert_param, IS_TIM_EXT_FILTER, IS_TIM_EXT_POLARITY, IS_TIM_EXT_PRESCALER, IS_TIM_LIST3_PERIPH, TIM_TypeDef::SMCR, and SMCR_ETR_Mask.

Referenced by TIM_ETRClockMode1Config(), and TIM_ETRClockMode2Config().

void TIM_ForcedOC1Config | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_ForcedAction
 | ) |  |

Forces the TIMx output 1 waveform to active or inactive level.

Parameters:
TIMx,: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
TIM_ForcedAction,: specifies the forced Action to be set to the output waveform. This parameter can be one of the following values:

  • TIM_ForcedAction_Active: Force active level on OC1REF
  • TIM_ForcedAction_InActive: Force inactive level on OC1REF.
Return values:
None

Definition at line 1315 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CCMR1, IS_TIM_FORCED_ACTION, IS_TIM_LIST8_PERIPH, and TIM_CCMR1_OC1M.

void TIM_ForcedOC2Config | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_ForcedAction
 | ) |  |

Forces the TIMx output 2 waveform to active or inactive level.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
TIM_ForcedAction,: specifies the forced Action to be set to the output waveform. This parameter can be one of the following values:

  • TIM_ForcedAction_Active: Force active level on OC2REF
  • TIM_ForcedAction_InActive: Force inactive level on OC2REF.
Return values:
None

Definition at line 1339 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CCMR1, IS_TIM_FORCED_ACTION, IS_TIM_LIST6_PERIPH, and TIM_CCMR1_OC2M.

void TIM_ForcedOC3Config | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_ForcedAction
 | ) |  |

Forces the TIMx output 3 waveform to active or inactive level.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
TIM_ForcedAction,: specifies the forced Action to be set to the output waveform. This parameter can be one of the following values:

  • TIM_ForcedAction_Active: Force active level on OC3REF
  • TIM_ForcedAction_InActive: Force inactive level on OC3REF.
Return values:
None

Definition at line 1363 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CCMR2, IS_TIM_FORCED_ACTION, IS_TIM_LIST3_PERIPH, and TIM_CCMR2_OC3M.

void TIM_ForcedOC4Config | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_ForcedAction
 | ) |  |

Forces the TIMx output 4 waveform to active or inactive level.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
TIM_ForcedAction,: specifies the forced Action to be set to the output waveform. This parameter can be one of the following values:

  • TIM_ForcedAction_Active: Force active level on OC4REF
  • TIM_ForcedAction_InActive: Force inactive level on OC4REF.
Return values:
None

Definition at line 1387 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CCMR2, IS_TIM_FORCED_ACTION, IS_TIM_LIST3_PERIPH, and TIM_CCMR2_OC4M.

void TIM_GenerateEvent | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_EventSource
 | ) |  |

Configures the TIMx event to be generate by software.

Parameters:
TIMx,: where x can be 1 to 17 to select the TIM peripheral.
TIM_EventSource,: specifies the event source. This parameter can be one or more of the following values:

  • TIM_EventSource_Update: Timer update Event source
  • TIM_EventSource_CC1: Timer Capture Compare 1 Event source
  • TIM_EventSource_CC2: Timer Capture Compare 2 Event source
  • TIM_EventSource_CC3: Timer Capture Compare 3 Event source
  • TIM_EventSource_CC4: Timer Capture Compare 4 Event source
  • TIM_EventSource_COM: Timer COM event source
  • TIM_EventSource_Trigger: Timer Trigger Event source
  • TIM_EventSource_Break: Timer Break event source
Note:
  • TIM6 and TIM7 can only generate an update event.
  • TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1 and TIM8.
Return values:
None

Definition at line 909 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::EGR, IS_TIM_ALL_PERIPH, and IS_TIM_EVENT_SOURCE.

Referenced by SysTick_Handler().

uint16_t TIM_GetCapture1 ( TIM_TypeDef * TIMx )

Gets the TIMx Input Capture 1 value.

Parameters:
TIMx,: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
Return values:
Capture Compare 1 Register value.

Definition at line 2457 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CCR1, and IS_TIM_LIST8_PERIPH.

Referenced by TIM1_BRK_TIM9_IRQHandler(), TIM2_IRQHandler(), and TIM3_IRQHandler().

uint16_t TIM_GetCapture2 ( TIM_TypeDef * TIMx )

Gets the TIMx Input Capture 2 value.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
Return values:
Capture Compare 2 Register value.

Definition at line 2470 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CCR2, and IS_TIM_LIST6_PERIPH.

Referenced by TIM1_BRK_TIM9_IRQHandler(), TIM2_IRQHandler(), and TIM3_IRQHandler().

uint16_t TIM_GetCapture3 ( TIM_TypeDef * TIMx )

Gets the TIMx Input Capture 3 value.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
Return values:
Capture Compare 3 Register value.

Definition at line 2483 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CCR3, and IS_TIM_LIST3_PERIPH.

Referenced by TIM2_IRQHandler(), and TIM3_IRQHandler().

uint16_t TIM_GetCapture4 ( TIM_TypeDef * TIMx )

Gets the TIMx Input Capture 4 value.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
Return values:
Capture Compare 4 Register value.

Definition at line 2496 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CCR4, and IS_TIM_LIST3_PERIPH.

Referenced by TIM2_IRQHandler(), TIM3_IRQHandler(), and TIM5_IRQHandler().

uint16_t TIM_GetCounter ( TIM_TypeDef * TIMx )

Gets the TIMx Counter value.

Parameters:
TIMx,: where x can be 1 to 17 to select the TIM peripheral.
Return values:
Counter Register value.

Definition at line 2509 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CNT, and IS_TIM_ALL_PERIPH.

FlagStatus TIM_GetFlagStatus | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_FLAG
 | ) |  |

Checks whether the specified TIM flag is set or not.

Parameters:
TIMx,: where x can be 1 to 17 to select the TIM peripheral.
TIM_FLAG,: specifies the flag to check. This parameter can be one of the following values:

  • TIM_FLAG_Update: TIM update Flag
  • TIM_FLAG_CC1: TIM Capture Compare 1 Flag
  • TIM_FLAG_CC2: TIM Capture Compare 2 Flag
  • TIM_FLAG_CC3: TIM Capture Compare 3 Flag
  • TIM_FLAG_CC4: TIM Capture Compare 4 Flag
  • TIM_FLAG_COM: TIM Commutation Flag
  • TIM_FLAG_Trigger: TIM Trigger Flag
  • TIM_FLAG_Break: TIM Break Flag
  • TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag
  • TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag
  • TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag
  • TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag
Note:
  • TIM6 and TIM7 can have only one update flag.
  • TIM9, TIM12 and TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1, TIM_FLAG_CC2 or TIM_FLAG_Trigger.
  • TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1.
  • TIM_FLAG_Break is used only with TIM1, TIM8 and TIM15.
  • TIM_FLAG_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17.
Return values:
The new state of TIM_FLAG (SET or RESET).

Definition at line 2556 of file stm32f10x_tim.c.

References assert_param, IS_TIM_ALL_PERIPH, IS_TIM_GET_FLAG, RESET, SET, and TIM_TypeDef::SR.

ITStatus TIM_GetITStatus | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_IT
 | ) |  |

Checks whether the TIM interrupt has occurred or not.

Parameters:
TIMx,: where x can be 1 to 17 to select the TIM peripheral.
TIM_IT,: specifies the TIM interrupt source to check. This parameter can be one of the following values:

  • TIM_IT_Update: TIM update Interrupt source
  • TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
  • TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
  • TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
  • TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
  • TIM_IT_COM: TIM Commutation Interrupt source
  • TIM_IT_Trigger: TIM Trigger Interrupt source
  • TIM_IT_Break: TIM Break Interrupt source
Note:
  • TIM6 and TIM7 can generate only an update interrupt.
  • TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1, TIM_IT_CC2 or TIM_IT_Trigger.
  • TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1.
  • TIM_IT_Break is used only with TIM1, TIM8 and TIM15.
  • TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17.
Return values:
The new state of the TIM_IT(SET or RESET).

Definition at line 2632 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::DIER, IS_TIM_ALL_PERIPH, IS_TIM_GET_IT, RESET, SET, and TIM_TypeDef::SR.

Referenced by TIM1_BRK_TIM9_IRQHandler(), TIM2_IRQHandler(), TIM3_IRQHandler(), and TIM5_IRQHandler().

uint16_t TIM_GetPrescaler ( TIM_TypeDef * TIMx )

Gets the TIMx Prescaler value.

Parameters:
TIMx,: where x can be 1 to 17 to select the TIM peripheral.
Return values:
Prescaler Register value.

Definition at line 2522 of file stm32f10x_tim.c.

References assert_param, IS_TIM_ALL_PERIPH, and TIM_TypeDef::PSC.

void TIM_ICInit | ( | TIM_TypeDef * | TIMx,
 |  | TIM_ICInitTypeDef * | TIM_ICInitStruct
 | ) |  |

Initializes the TIM peripheral according to the specified parameters in the TIM_ICInitStruct.

Parameters:
TIMx,: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
TIM_ICInitStruct,: pointer to a TIM_ICInitTypeDef structure that contains the configuration information for the specified TIM peripheral.
Return values:
None

Definition at line 587 of file stm32f10x_tim.c.

References assert_param, IS_TIM_CHANNEL, IS_TIM_IC_FILTER, IS_TIM_IC_POLARITY, IS_TIM_IC_POLARITY_LITE, IS_TIM_IC_PRESCALER, IS_TIM_IC_SELECTION, IS_TIM_LIST3_PERIPH, IS_TIM_LIST6_PERIPH, IS_TIM_LIST8_PERIPH, TI1_Config(), TI2_Config(), TI3_Config(), TI4_Config(), TIM1, TIM2, TIM3, TIM4, TIM5, TIM8, TIM_ICInitTypeDef::TIM_Channel, TIM_Channel_1, TIM_Channel_2, TIM_Channel_3, TIM_ICInitTypeDef::TIM_ICFilter, TIM_ICInitTypeDef::TIM_ICPolarity, TIM_ICInitTypeDef::TIM_ICPrescaler, TIM_ICInitTypeDef::TIM_ICSelection, TIM_SetIC1Prescaler(), TIM_SetIC2Prescaler(), TIM_SetIC3Prescaler(), and TIM_SetIC4Prescaler().

Referenced by main(), and TIM5_ConfigForLSI().

void TIM_ICStructInit ( TIM_ICInitTypeDef * TIM_ICInitStruct )

Fills each TIM_ICInitStruct member with its default value.

Parameters:
TIM_ICInitStruct,: pointer to a TIM_ICInitTypeDef structure which will be initialized.
Return values:
None

Definition at line 771 of file stm32f10x_tim.c.

References TIM_ICInitTypeDef::TIM_Channel, TIM_Channel_1, TIM_ICInitTypeDef::TIM_ICFilter, TIM_ICInitTypeDef::TIM_ICPolarity, TIM_ICPolarity_Rising, TIM_ICInitTypeDef::TIM_ICPrescaler, TIM_ICPSC_DIV1, TIM_ICInitTypeDef::TIM_ICSelection, and TIM_ICSelection_DirectTI.

Referenced by main().

void TIM_InternalClockConfig ( TIM_TypeDef * TIMx )

Configures the TIMx internal Clock.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
Return values:
None

Definition at line 989 of file stm32f10x_tim.c.

References assert_param, IS_TIM_LIST6_PERIPH, TIM_TypeDef::SMCR, and TIM_SMCR_SMS.

void TIM_ITConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified TIM interrupts.

Parameters:
TIMx,: where x can be 1 to 17 to select the TIMx peripheral.
TIM_IT,: specifies the TIM interrupts sources to be enabled or disabled. This parameter can be any combination of the following values:

  • TIM_IT_Update: TIM update Interrupt source
  • TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
  • TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
  • TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
  • TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
  • TIM_IT_COM: TIM Commutation Interrupt source
  • TIM_IT_Trigger: TIM Trigger Interrupt source
  • TIM_IT_Break: TIM Break Interrupt source
Note:
  • TIM6 and TIM7 can only generate an update interrupt.
  • TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1, TIM_IT_CC2 or TIM_IT_Trigger.
  • TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1.
  • TIM_IT_Break is used only with TIM1, TIM8 and TIM15.
  • TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17.
Parameters:
NewState,: new state of the TIM interrupts. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 872 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::DIER, DISABLE, IS_FUNCTIONAL_STATE, IS_TIM_ALL_PERIPH, and IS_TIM_IT.

Referenced by main(), TIM5_ConfigForLSI(), TIM5_IRQHandler(), and TIM_Config().

void TIM_ITRxExternalClockConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_InputTriggerSource
 | ) |  |

Configures the TIMx Internal Trigger as External Clock.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5, 9, 12 or 15 to select the TIM peripheral.
TIM_ITRSource,: Trigger source. This parameter can be one of the following values:
TIM_TS_ITR0,: Internal Trigger 0
TIM_TS_ITR1,: Internal Trigger 1
TIM_TS_ITR2,: Internal Trigger 2
TIM_TS_ITR3,: Internal Trigger 3
Return values:
None

Definition at line 1008 of file stm32f10x_tim.c.

References assert_param, IS_TIM_INTERNAL_TRIGGER_SELECTION, IS_TIM_LIST6_PERIPH, TIM_TypeDef::SMCR, TIM_SelectInputTrigger(), and TIM_SlaveMode_External1.

void TIM_OC1FastConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_OCFast
 | ) |  |

Configures the TIMx Output Compare 1 Fast feature.

Parameters:
TIMx,: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
TIM_OCFast,: new state of the Output Compare Fast Enable Bit. This parameter can be one of the following values:

  • TIM_OCFast_Enable: TIM output compare fast enable
  • TIM_OCFast_Disable: TIM output compare fast disable
Return values:
None

Definition at line 1606 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CCMR1, IS_TIM_LIST8_PERIPH, IS_TIM_OCFAST_STATE, and TIM_CCMR1_OC1FE.

void TIM_OC1Init | ( | TIM_TypeDef * | TIMx,
 |  | TIM_OCInitTypeDef * | TIM_OCInitStruct
 | ) |  |

Initializes the TIMx Channel1 according to the specified parameters in the TIM_OCInitStruct.

Parameters:
TIMx,: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
TIM_OCInitStruct,: pointer to a TIM_OCInitTypeDef structure that contains the configuration information for the specified TIM peripheral.
Return values:
None

Definition at line 279 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CCER, TIM_TypeDef::CCMR1, TIM_TypeDef::CCR1, TIM_TypeDef::CR2, IS_TIM_LIST8_PERIPH, IS_TIM_OC_MODE, IS_TIM_OC_POLARITY, IS_TIM_OCIDLE_STATE, IS_TIM_OCN_POLARITY, IS_TIM_OCNIDLE_STATE, IS_TIM_OUTPUT_STATE, IS_TIM_OUTPUTN_STATE, TIM1, TIM15, TIM16, TIM17, TIM8, TIM_CCER_CC1E, TIM_CCER_CC1NE, TIM_CCER_CC1NP, TIM_CCER_CC1P, TIM_CCMR1_CC1S, TIM_CCMR1_OC1M, TIM_CR2_OIS1, TIM_CR2_OIS1N, TIM_OCInitTypeDef::TIM_OCIdleState, TIM_OCInitTypeDef::TIM_OCMode, TIM_OCInitTypeDef::TIM_OCNIdleState, TIM_OCInitTypeDef::TIM_OCNPolarity, TIM_OCInitTypeDef::TIM_OCPolarity, TIM_OCInitTypeDef::TIM_OutputNState, TIM_OCInitTypeDef::TIM_OutputState, and TIM_OCInitTypeDef::TIM_Pulse.

Referenced by main(), and TIM_Config().

void TIM_OC1NPolarityConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_OCNPolarity
 | ) |  |

Configures the TIMx Channel 1N polarity.

Parameters:
TIMx,: where x can be 1, 8, 15, 16 or 17 to select the TIM peripheral.
TIM_OCNPolarity,: specifies the OC1N Polarity This parameter can be one of the following values:

  • TIM_OCNPolarity_High: Output Compare active high
  • TIM_OCNPolarity_Low: Output Compare active low
Return values:
None

Definition at line 1828 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CCER, IS_TIM_LIST2_PERIPH, IS_TIM_OCN_POLARITY, and TIM_CCER_CC1NP.

void TIM_OC1PolarityConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_OCPolarity
 | ) |  |

Configures the TIMx channel 1 polarity.

Parameters:
TIMx,: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
TIM_OCPolarity,: specifies the OC1 Polarity This parameter can be one of the following values:

  • TIM_OCPolarity_High: Output Compare active high
  • TIM_OCPolarity_Low: Output Compare active low
Return values:
None

Definition at line 1805 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CCER, IS_TIM_LIST8_PERIPH, IS_TIM_OC_POLARITY, and TIM_CCER_CC1P.

void TIM_OC1PreloadConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_OCPreload
 | ) |  |

Enables or disables the TIMx peripheral Preload register on CCR1.

Parameters:
TIMx,: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
TIM_OCPreload,: new state of the TIMx peripheral Preload register This parameter can be one of the following values:

  • TIM_OCPreload_Enable
  • TIM_OCPreload_Disable
Return values:
None

Definition at line 1509 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CCMR1, IS_TIM_LIST8_PERIPH, IS_TIM_OCPRELOAD_STATE, and TIM_CCMR1_OC1PE.

Referenced by main().

void TIM_OC2FastConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_OCFast
 | ) |  |

Configures the TIMx Output Compare 2 Fast feature.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
TIM_OCFast,: new state of the Output Compare Fast Enable Bit. This parameter can be one of the following values:

  • TIM_OCFast_Enable: TIM output compare fast enable
  • TIM_OCFast_Disable: TIM output compare fast disable
Return values:
None

Definition at line 1632 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CCMR1, IS_TIM_LIST6_PERIPH, IS_TIM_OCFAST_STATE, and TIM_CCMR1_OC2FE.

void TIM_OC2Init | ( | TIM_TypeDef * | TIMx,
 |  | TIM_OCInitTypeDef * | TIM_OCInitStruct
 | ) |  |

Initializes the TIMx Channel2 according to the specified parameters in the TIM_OCInitStruct.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
TIM_OCInitStruct,: pointer to a TIM_OCInitTypeDef structure that contains the configuration information for the specified TIM peripheral.
Return values:
None

Definition at line 362 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CCER, TIM_TypeDef::CCMR1, TIM_TypeDef::CCR2, TIM_TypeDef::CR2, IS_TIM_LIST6_PERIPH, IS_TIM_OC_MODE, IS_TIM_OC_POLARITY, IS_TIM_OCIDLE_STATE, IS_TIM_OCN_POLARITY, IS_TIM_OCNIDLE_STATE, IS_TIM_OUTPUT_STATE, IS_TIM_OUTPUTN_STATE, TIM1, TIM8, TIM_CCER_CC2E, TIM_CCER_CC2NE, TIM_CCER_CC2NP, TIM_CCER_CC2P, TIM_CCMR1_CC2S, TIM_CCMR1_OC2M, TIM_CR2_OIS2, TIM_CR2_OIS2N, TIM_OCInitTypeDef::TIM_OCIdleState, TIM_OCInitTypeDef::TIM_OCMode, TIM_OCInitTypeDef::TIM_OCNIdleState, TIM_OCInitTypeDef::TIM_OCNPolarity, TIM_OCInitTypeDef::TIM_OCPolarity, TIM_OCInitTypeDef::TIM_OutputNState, TIM_OCInitTypeDef::TIM_OutputState, and TIM_OCInitTypeDef::TIM_Pulse.

Referenced by main().

void TIM_OC2NPolarityConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_OCNPolarity
 | ) |  |

Configures the TIMx Channel 2N polarity.

Parameters:
TIMx,: where x can be 1 or 8 to select the TIM peripheral.
TIM_OCNPolarity,: specifies the OC2N Polarity This parameter can be one of the following values:

  • TIM_OCNPolarity_High: Output Compare active high
  • TIM_OCNPolarity_Low: Output Compare active low
Return values:
None

Definition at line 1875 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CCER, IS_TIM_LIST1_PERIPH, IS_TIM_OCN_POLARITY, and TIM_CCER_CC2NP.

void TIM_OC2PolarityConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_OCPolarity
 | ) |  |

Configures the TIMx channel 2 polarity.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
TIM_OCPolarity,: specifies the OC2 Polarity This parameter can be one of the following values:

  • TIM_OCPolarity_High: Output Compare active high
  • TIM_OCPolarity_Low: Output Compare active low
Return values:
None

Definition at line 1852 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CCER, IS_TIM_LIST6_PERIPH, IS_TIM_OC_POLARITY, and TIM_CCER_CC2P.

void TIM_OC2PreloadConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_OCPreload
 | ) |  |

Enables or disables the TIMx peripheral Preload register on CCR2.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
TIM_OCPreload,: new state of the TIMx peripheral Preload register This parameter can be one of the following values:

  • TIM_OCPreload_Enable
  • TIM_OCPreload_Disable
Return values:
None

Definition at line 1534 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CCMR1, IS_TIM_LIST6_PERIPH, IS_TIM_OCPRELOAD_STATE, and TIM_CCMR1_OC2PE.

Referenced by main().

void TIM_OC3FastConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_OCFast
 | ) |  |

Configures the TIMx Output Compare 3 Fast feature.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
TIM_OCFast,: new state of the Output Compare Fast Enable Bit. This parameter can be one of the following values:

  • TIM_OCFast_Enable: TIM output compare fast enable
  • TIM_OCFast_Disable: TIM output compare fast disable
Return values:
None

Definition at line 1657 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CCMR2, IS_TIM_LIST3_PERIPH, IS_TIM_OCFAST_STATE, and TIM_CCMR2_OC3FE.

void TIM_OC3Init | ( | TIM_TypeDef * | TIMx,
 |  | TIM_OCInitTypeDef * | TIM_OCInitStruct
 | ) |  |

Initializes the TIMx Channel3 according to the specified parameters in the TIM_OCInitStruct.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
TIM_OCInitStruct,: pointer to a TIM_OCInitTypeDef structure that contains the configuration information for the specified TIM peripheral.
Return values:
None

Definition at line 444 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CCER, TIM_TypeDef::CCMR2, TIM_TypeDef::CCR3, TIM_TypeDef::CR2, IS_TIM_LIST3_PERIPH, IS_TIM_OC_MODE, IS_TIM_OC_POLARITY, IS_TIM_OCIDLE_STATE, IS_TIM_OCN_POLARITY, IS_TIM_OCNIDLE_STATE, IS_TIM_OUTPUT_STATE, IS_TIM_OUTPUTN_STATE, TIM1, TIM8, TIM_CCER_CC3E, TIM_CCER_CC3NE, TIM_CCER_CC3NP, TIM_CCER_CC3P, TIM_CCMR2_CC3S, TIM_CCMR2_OC3M, TIM_CR2_OIS3, TIM_CR2_OIS3N, TIM_OCInitTypeDef::TIM_OCIdleState, TIM_OCInitTypeDef::TIM_OCMode, TIM_OCInitTypeDef::TIM_OCNIdleState, TIM_OCInitTypeDef::TIM_OCNPolarity, TIM_OCInitTypeDef::TIM_OCPolarity, TIM_OCInitTypeDef::TIM_OutputNState, TIM_OCInitTypeDef::TIM_OutputState, and TIM_OCInitTypeDef::TIM_Pulse.

Referenced by main().

void TIM_OC3NPolarityConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_OCNPolarity
 | ) |  |

Configures the TIMx Channel 3N polarity.

Parameters:
TIMx,: where x can be 1 or 8 to select the TIM peripheral.
TIM_OCNPolarity,: specifies the OC3N Polarity This parameter can be one of the following values:

  • TIM_OCNPolarity_High: Output Compare active high
  • TIM_OCNPolarity_Low: Output Compare active low
Return values:
None

Definition at line 1922 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CCER, IS_TIM_LIST1_PERIPH, IS_TIM_OCN_POLARITY, and TIM_CCER_CC3NP.

void TIM_OC3PolarityConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_OCPolarity
 | ) |  |

Configures the TIMx channel 3 polarity.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
TIM_OCPolarity,: specifies the OC3 Polarity This parameter can be one of the following values:

  • TIM_OCPolarity_High: Output Compare active high
  • TIM_OCPolarity_Low: Output Compare active low
Return values:
None

Definition at line 1899 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CCER, IS_TIM_LIST3_PERIPH, IS_TIM_OC_POLARITY, and TIM_CCER_CC3P.

void TIM_OC3PreloadConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_OCPreload
 | ) |  |

Enables or disables the TIMx peripheral Preload register on CCR3.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
TIM_OCPreload,: new state of the TIMx peripheral Preload register This parameter can be one of the following values:

  • TIM_OCPreload_Enable
  • TIM_OCPreload_Disable
Return values:
None

Definition at line 1558 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CCMR2, IS_TIM_LIST3_PERIPH, IS_TIM_OCPRELOAD_STATE, and TIM_CCMR2_OC3PE.

Referenced by main().

void TIM_OC4FastConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_OCFast
 | ) |  |

Configures the TIMx Output Compare 4 Fast feature.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
TIM_OCFast,: new state of the Output Compare Fast Enable Bit. This parameter can be one of the following values:

  • TIM_OCFast_Enable: TIM output compare fast enable
  • TIM_OCFast_Disable: TIM output compare fast disable
Return values:
None

Definition at line 1682 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CCMR2, IS_TIM_LIST3_PERIPH, IS_TIM_OCFAST_STATE, and TIM_CCMR2_OC4FE.

void TIM_OC4Init | ( | TIM_TypeDef * | TIMx,
 |  | TIM_OCInitTypeDef * | TIM_OCInitStruct
 | ) |  |

Initializes the TIMx Channel4 according to the specified parameters in the TIM_OCInitStruct.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
TIM_OCInitStruct,: pointer to a TIM_OCInitTypeDef structure that contains the configuration information for the specified TIM peripheral.
Return values:
None

Definition at line 523 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CCER, TIM_TypeDef::CCMR2, TIM_TypeDef::CCR4, TIM_TypeDef::CR2, IS_TIM_LIST3_PERIPH, IS_TIM_OC_MODE, IS_TIM_OC_POLARITY, IS_TIM_OCIDLE_STATE, IS_TIM_OUTPUT_STATE, TIM1, TIM8, TIM_CCER_CC4E, TIM_CCER_CC4P, TIM_CCMR2_CC4S, TIM_CCMR2_OC4M, TIM_CR2_OIS4, TIM_OCInitTypeDef::TIM_OCIdleState, TIM_OCInitTypeDef::TIM_OCMode, TIM_OCInitTypeDef::TIM_OCPolarity, TIM_OCInitTypeDef::TIM_OutputState, and TIM_OCInitTypeDef::TIM_Pulse.

Referenced by main().

void TIM_OC4PolarityConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_OCPolarity
 | ) |  |

Configures the TIMx channel 4 polarity.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
TIM_OCPolarity,: specifies the OC4 Polarity This parameter can be one of the following values:

  • TIM_OCPolarity_High: Output Compare active high
  • TIM_OCPolarity_Low: Output Compare active low
Return values:
None

Definition at line 1947 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CCER, IS_TIM_LIST3_PERIPH, IS_TIM_OC_POLARITY, and TIM_CCER_CC4P.

void TIM_OC4PreloadConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_OCPreload
 | ) |  |

Enables or disables the TIMx peripheral Preload register on CCR4.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
TIM_OCPreload,: new state of the TIMx peripheral Preload register This parameter can be one of the following values:

  • TIM_OCPreload_Enable
  • TIM_OCPreload_Disable
Return values:
None

Definition at line 1582 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CCMR2, IS_TIM_LIST3_PERIPH, IS_TIM_OCPRELOAD_STATE, and TIM_CCMR2_OC4PE.

Referenced by main().

void TIM_OCStructInit ( TIM_OCInitTypeDef * TIM_OCInitStruct )

Fills each TIM_OCInitStruct member with its default value.

Parameters:
TIM_OCInitStruct : pointer to a TIM_OCInitTypeDef structure which will be initialized.
Return values:
None

Definition at line 752 of file stm32f10x_tim.c.

References TIM_OCInitTypeDef::TIM_OCIdleState, TIM_OCIdleState_Reset, TIM_OCInitTypeDef::TIM_OCMode, TIM_OCMode_Timing, TIM_OCInitTypeDef::TIM_OCNIdleState, TIM_OCNIdleState_Reset, TIM_OCInitTypeDef::TIM_OCNPolarity, TIM_OCInitTypeDef::TIM_OCPolarity, TIM_OCPolarity_High, TIM_OCInitTypeDef::TIM_OutputNState, TIM_OutputNState_Disable, TIM_OCInitTypeDef::TIM_OutputState, TIM_OutputState_Disable, and TIM_OCInitTypeDef::TIM_Pulse.

Referenced by TIM_Config().

void TIM_PrescalerConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | Prescaler,
 |  | uint16_t | TIM_PSCReloadMode
 | ) |  |

Configures the TIMx Prescaler.

Parameters:
TIMx,: where x can be 1 to 17 to select the TIM peripheral.
Prescaler,: specifies the Prescaler Register value
TIM_PSCReloadMode,: specifies the TIM Prescaler Reload mode This parameter can be one of the following values:

  • TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event.
  • TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediately.
Return values:
None

Definition at line 1176 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::EGR, IS_TIM_ALL_PERIPH, IS_TIM_PRESCALER_RELOAD, and TIM_TypeDef::PSC.

Referenced by main(), TIM5_ConfigForLSI(), and TIM_Config().

void TIM_PWMIConfig | ( | TIM_TypeDef * | TIMx,
 |  | TIM_ICInitTypeDef * | TIM_ICInitStruct
 | ) |  |

Configures the TIM peripheral according to the specified parameters in the TIM_ICInitStruct to measure an external PWM signal.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
TIM_ICInitStruct,: pointer to a TIM_ICInitTypeDef structure that contains the configuration information for the specified TIM peripheral.
Return values:
None

Definition at line 654 of file stm32f10x_tim.c.

References assert_param, IS_TIM_LIST6_PERIPH, TI1_Config(), TI2_Config(), TIM_ICInitTypeDef::TIM_Channel, TIM_Channel_1, TIM_ICInitTypeDef::TIM_ICFilter, TIM_ICInitTypeDef::TIM_ICPolarity, TIM_ICPolarity_Falling, TIM_ICPolarity_Rising, TIM_ICInitTypeDef::TIM_ICPrescaler, TIM_ICInitTypeDef::TIM_ICSelection, TIM_ICSelection_DirectTI, TIM_ICSelection_IndirectTI, TIM_SetIC1Prescaler(), and TIM_SetIC2Prescaler().

Referenced by main().

void TIM_SelectCCDMA | ( | TIM_TypeDef * | TIMx,
 |  | FunctionalState | NewState
 | ) |  |

Selects the TIMx peripheral Capture Compare DMA source.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5, 8, 15, 16 or 17 to select the TIM peripheral.
NewState,: new state of the Capture Compare DMA source This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1458 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CR2, DISABLE, IS_FUNCTIONAL_STATE, IS_TIM_LIST4_PERIPH, and TIM_CR2_CCDS.

void TIM_SelectCOM | ( | TIM_TypeDef * | TIMx,
 |  | FunctionalState | NewState
 | ) |  |

Selects the TIM peripheral Commutation event.

Parameters:
TIMx,: where x can be 1, 8, 15, 16 or 17 to select the TIMx peripheral
NewState,: new state of the Commutation event. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1433 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CR2, DISABLE, IS_FUNCTIONAL_STATE, IS_TIM_LIST2_PERIPH, and TIM_CR2_CCUS.

void TIM_SelectHallSensor | ( | TIM_TypeDef * | TIMx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the TIMx's Hall sensor interface.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
NewState,: new state of the TIMx Hall sensor interface. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 2144 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CR2, DISABLE, IS_FUNCTIONAL_STATE, IS_TIM_LIST6_PERIPH, and TIM_CR2_TI1S.

void TIM_SelectInputTrigger | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_InputTriggerSource
 | ) |  |

Selects the Input Trigger source.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
TIM_InputTriggerSource,: The Input Trigger source. This parameter can be one of the following values:

  • TIM_TS_ITR0: Internal Trigger 0
  • TIM_TS_ITR1: Internal Trigger 1
  • TIM_TS_ITR2: Internal Trigger 2
  • TIM_TS_ITR3: Internal Trigger 3
  • TIM_TS_TI1F_ED: TI1 Edge Detector
  • TIM_TS_TI1FP1: Filtered Timer Input 1
  • TIM_TS_TI2FP2: Filtered Timer Input 2
  • TIM_TS_ETRF: External Trigger input
Return values:
None

Definition at line 1229 of file stm32f10x_tim.c.

References assert_param, IS_TIM_LIST6_PERIPH, IS_TIM_TRIGGER_SELECTION, TIM_TypeDef::SMCR, and TIM_SMCR_TS.

Referenced by main(), TIM_ITRxExternalClockConfig(), and TIM_TIxExternalClockConfig().

void TIM_SelectMasterSlaveMode | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_MasterSlaveMode
 | ) |  |

Sets or Resets the TIMx Master/Slave Mode.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
TIM_MasterSlaveMode,: specifies the Timer Master Slave Mode. This parameter can be one of the following values:

  • TIM_MasterSlaveMode_Enable: synchronization between the current timer and its slaves (through TRGO).
  • TIM_MasterSlaveMode_Disable: No action
Return values:
None

Definition at line 2246 of file stm32f10x_tim.c.

References assert_param, IS_TIM_LIST6_PERIPH, IS_TIM_MSM_STATE, TIM_TypeDef::SMCR, and TIM_SMCR_MSM.

Referenced by main().

void TIM_SelectOCxM | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_Channel,
 |  | uint16_t | TIM_OCMode
 | ) |  |

Selects the TIM Output Compare Mode.

Note:
This function disables the selected channel before changing the Output Compare Mode. User has to enable this channel using TIM_CCxCmd and TIM_CCxNCmd functions.
Parameters:
TIMx,: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
TIM_Channel,: specifies the TIM Channel This parameter can be one of the following values:

  • TIM_Channel_1: TIM Channel 1
  • TIM_Channel_2: TIM Channel 2
  • TIM_Channel_3: TIM Channel 3
  • TIM_Channel_4: TIM Channel 4
TIM_OCMode,: specifies the TIM Output Compare Mode. This parameter can be one of the following values:

  • TIM_OCMode_Timing
  • TIM_OCMode_Active
  • TIM_OCMode_Toggle
  • TIM_OCMode_PWM1
  • TIM_OCMode_PWM2
  • TIM_ForcedAction_Active
  • TIM_ForcedAction_InActive
Return values:
None

Definition at line 2045 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CCER, CCER_CCE_Set, CCMR_Offset, IS_TIM_CHANNEL, IS_TIM_LIST8_PERIPH, IS_TIM_OCM, TIM_CCMR1_OC1M, TIM_CCMR1_OC2M, TIM_Channel_1, and TIM_Channel_3.

Referenced by TIM1_TRG_COM_IRQHandler().

void TIM_SelectOnePulseMode | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_OPMode
 | ) |  |

Selects the TIMx's One Pulse Mode.

Parameters:
TIMx,: where x can be 1 to 17 to select the TIM peripheral.
TIM_OPMode,: specifies the OPM Mode to be used. This parameter can be one of the following values:

  • TIM_OPMode_Single
  • TIM_OPMode_Repetitive
Return values:
None

Definition at line 2170 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CR1, IS_TIM_ALL_PERIPH, IS_TIM_OPM_MODE, and TIM_CR1_OPM.

Referenced by main().

void TIM_SelectOutputTrigger | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_TRGOSource
 | ) |  |

Selects the TIMx Trigger Output Mode.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5, 6, 7, 8, 9, 12 or 15 to select the TIM peripheral.
TIM_TRGOSource,: specifies the Trigger Output source. This paramter can be one of the following values:
  • For all TIMx
    • TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output (TRGO).
    • TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output (TRGO).
    • TIM_TRGOSource_Update: The update event is selected as the trigger output (TRGO).
  • For all TIMx except TIM6 and TIM7
    • TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag is to be set, as soon as a capture or compare match occurs (TRGO).
    • TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output (TRGO).
    • TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output (TRGO).
    • TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output (TRGO).
    • TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output (TRGO).
    Return values:
    None

Definition at line 2202 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CR2, IS_TIM_LIST7_PERIPH, IS_TIM_TRGO_SOURCE, and TIM_CR2_MMS.

Referenced by main().

void TIM_SelectSlaveMode | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_SlaveMode
 | ) |  |

Selects the TIMx Slave Mode.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
TIM_SlaveMode,: specifies the Timer Slave Mode. This parameter can be one of the following values:

  • TIM_SlaveMode_Reset: Rising edge of the selected trigger signal (TRGI) re-initializes the counter and triggers an update of the registers.
  • TIM_SlaveMode_Gated: The counter clock is enabled when the trigger signal (TRGI) is high.
  • TIM_SlaveMode_Trigger: The counter starts at a rising edge of the trigger TRGI.
  • TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter.
Return values:
None

Definition at line 2225 of file stm32f10x_tim.c.

References assert_param, IS_TIM_LIST6_PERIPH, IS_TIM_SLAVE_MODE, TIM_TypeDef::SMCR, and TIM_SMCR_SMS.

Referenced by main().

void TIM_SetAutoreload | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | Autoreload
 | ) |  |

Sets the TIMx Autoreload Register value.

Parameters:
TIMx,: where x can be 1 to 17 to select the TIM peripheral.
Autoreload,: specifies the Autoreload register new value.
Return values:
None

Definition at line 2278 of file stm32f10x_tim.c.

References TIM_TypeDef::ARR, assert_param, and IS_TIM_ALL_PERIPH.

Referenced by main().

void TIM_SetClockDivision | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_CKD
 | ) |  |

Sets the TIMx Clock Division value.

Parameters:
TIMx,: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
TIM_CKD,: specifies the clock division value. This parameter can be one of the following value:

  • TIM_CKD_DIV1: TDTS = Tck_tim
  • TIM_CKD_DIV2: TDTS = 2*Tck_tim
  • TIM_CKD_DIV4: TDTS = 4*Tck_tim
Return values:
None

Definition at line 2441 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CR1, IS_TIM_CKD_DIV, IS_TIM_LIST8_PERIPH, and TIM_CR1_CKD.

void TIM_SetCompare1 | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | Compare1
 | ) |  |

Sets the TIMx Capture Compare1 Register value.

Parameters:
TIMx,: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
Compare1,: specifies the Capture Compare1 register new value.
Return values:
None

Definition at line 2292 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CCR1, and IS_TIM_LIST8_PERIPH.

Referenced by TIM1_BRK_TIM9_IRQHandler(), TIM2_IRQHandler(), and TIM3_IRQHandler().

void TIM_SetCompare2 | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | Compare2
 | ) |  |

Sets the TIMx Capture Compare2 Register value.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
Compare2,: specifies the Capture Compare2 register new value.
Return values:
None

Definition at line 2306 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CCR2, and IS_TIM_LIST6_PERIPH.

Referenced by TIM1_BRK_TIM9_IRQHandler(), TIM2_IRQHandler(), and TIM3_IRQHandler().

void TIM_SetCompare3 | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | Compare3
 | ) |  |

Sets the TIMx Capture Compare3 Register value.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
Compare3,: specifies the Capture Compare3 register new value.
Return values:
None

Definition at line 2320 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CCR3, and IS_TIM_LIST3_PERIPH.

Referenced by TIM2_IRQHandler(), and TIM3_IRQHandler().

void TIM_SetCompare4 | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | Compare4
 | ) |  |

Sets the TIMx Capture Compare4 Register value.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
Compare4,: specifies the Capture Compare4 register new value.
Return values:
None

Definition at line 2334 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CCR4, and IS_TIM_LIST3_PERIPH.

Referenced by TIM2_IRQHandler(), and TIM3_IRQHandler().

void TIM_SetCounter | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | Counter
 | ) |  |

Sets the TIMx Counter Register value.

Parameters:
TIMx,: where x can be 1 to 17 to select the TIM peripheral.
Counter,: specifies the Counter register new value.
Return values:
None

Definition at line 2264 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CNT, Counter, and IS_TIM_ALL_PERIPH.

void TIM_SetIC1Prescaler | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_ICPSC
 | ) |  |

Sets the TIMx Input Capture 1 prescaler.

Parameters:
TIMx,: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
TIM_ICPSC,: specifies the Input Capture1 prescaler new value. This parameter can be one of the following values:

  • TIM_ICPSC_DIV1: no prescaler
  • TIM_ICPSC_DIV2: capture is done once every 2 events
  • TIM_ICPSC_DIV4: capture is done once every 4 events
  • TIM_ICPSC_DIV8: capture is done once every 8 events
Return values:
None

Definition at line 2353 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CCMR1, IS_TIM_IC_PRESCALER, IS_TIM_LIST8_PERIPH, and TIM_CCMR1_IC1PSC.

Referenced by TIM_ICInit(), and TIM_PWMIConfig().

void TIM_SetIC2Prescaler | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_ICPSC
 | ) |  |

Sets the TIMx Input Capture 2 prescaler.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
TIM_ICPSC,: specifies the Input Capture2 prescaler new value. This parameter can be one of the following values:

  • TIM_ICPSC_DIV1: no prescaler
  • TIM_ICPSC_DIV2: capture is done once every 2 events
  • TIM_ICPSC_DIV4: capture is done once every 4 events
  • TIM_ICPSC_DIV8: capture is done once every 8 events
Return values:
None

Definition at line 2375 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CCMR1, IS_TIM_IC_PRESCALER, IS_TIM_LIST6_PERIPH, and TIM_CCMR1_IC2PSC.

Referenced by TIM_ICInit(), and TIM_PWMIConfig().

void TIM_SetIC3Prescaler | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_ICPSC
 | ) |  |

Sets the TIMx Input Capture 3 prescaler.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
TIM_ICPSC,: specifies the Input Capture3 prescaler new value. This parameter can be one of the following values:

  • TIM_ICPSC_DIV1: no prescaler
  • TIM_ICPSC_DIV2: capture is done once every 2 events
  • TIM_ICPSC_DIV4: capture is done once every 4 events
  • TIM_ICPSC_DIV8: capture is done once every 8 events
Return values:
None

Definition at line 2397 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CCMR2, IS_TIM_IC_PRESCALER, IS_TIM_LIST3_PERIPH, and TIM_CCMR2_IC3PSC.

Referenced by TIM_ICInit().

void TIM_SetIC4Prescaler | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_ICPSC
 | ) |  |

Sets the TIMx Input Capture 4 prescaler.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
TIM_ICPSC,: specifies the Input Capture4 prescaler new value. This parameter can be one of the following values:

  • TIM_ICPSC_DIV1: no prescaler
  • TIM_ICPSC_DIV2: capture is done once every 2 events
  • TIM_ICPSC_DIV4: capture is done once every 4 events
  • TIM_ICPSC_DIV8: capture is done once every 8 events
Return values:
None

Definition at line 2419 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CCMR2, IS_TIM_IC_PRESCALER, IS_TIM_LIST3_PERIPH, and TIM_CCMR2_IC4PSC.

Referenced by TIM_ICInit().

void TIM_TimeBaseInit | ( | TIM_TypeDef * | TIMx,
 |  | TIM_TimeBaseInitTypeDef * | TIM_TimeBaseInitStruct
 | ) |  |

Initializes the TIMx Time Base Unit peripheral according to the specified parameters in the TIM_TimeBaseInitStruct.

Parameters:
TIMx,: where x can be 1 to 17 to select the TIM peripheral.
TIM_TimeBaseInitStruct,: pointer to a TIM_TimeBaseInitTypeDef structure that contains the configuration information for the specified TIM peripheral.
Return values:
None

Definition at line 226 of file stm32f10x_tim.c.

References TIM_TypeDef::ARR, assert_param, TIM_TypeDef::CR1, TIM_TypeDef::EGR, IS_TIM_ALL_PERIPH, IS_TIM_CKD_DIV, IS_TIM_COUNTER_MODE, TIM_TypeDef::PSC, TIM_TypeDef::RCR, TIM1, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TIM_TimeBaseInitTypeDef::TIM_ClockDivision, TIM_TimeBaseInitTypeDef::TIM_CounterMode, TIM_CR1_CKD, TIM_CR1_CMS, TIM_CR1_DIR, TIM_TimeBaseInitTypeDef::TIM_Period, TIM_TimeBaseInitTypeDef::TIM_Prescaler, TIM_PSCReloadMode_Immediate, and TIM_TimeBaseInitTypeDef::TIM_RepetitionCounter.

Referenced by main(), and TIM_Config().

void TIM_TimeBaseStructInit ( TIM_TimeBaseInitTypeDef * TIM_TimeBaseInitStruct )

Fills each TIM_TimeBaseInitStruct member with its default value.

Parameters:
TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef structure which will be initialized.
Return values:
None

Definition at line 736 of file stm32f10x_tim.c.

References TIM_CKD_DIV1, TIM_TimeBaseInitTypeDef::TIM_ClockDivision, TIM_TimeBaseInitTypeDef::TIM_CounterMode, TIM_CounterMode_Up, TIM_TimeBaseInitTypeDef::TIM_Period, TIM_TimeBaseInitTypeDef::TIM_Prescaler, and TIM_TimeBaseInitTypeDef::TIM_RepetitionCounter.

Referenced by main().

void TIM_TIxExternalClockConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_TIxExternalCLKSource,
 |  | uint16_t | TIM_ICPolarity,
 |  | uint16_t | ICFilter
 | ) |  |

Configures the TIMx Trigger as External Clock.

Parameters:
TIMx,: where x can be 1, 2, 3, 4, 5, 9, 12 or 15 to select the TIM peripheral.
TIM_TIxExternalCLKSource,: Trigger source. This parameter can be one of the following values:

  • TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector
  • TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1
  • TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2
TIM_ICPolarity,: specifies the TIx Polarity. This parameter can be one of the following values:

  • TIM_ICPolarity_Rising
  • TIM_ICPolarity_Falling
ICFilter : specifies the filter value. This parameter must be a value between 0x0 and 0xF.
Return values:
None

Definition at line 1035 of file stm32f10x_tim.c.

References assert_param, IS_TIM_IC_FILTER, IS_TIM_IC_POLARITY, IS_TIM_LIST6_PERIPH, IS_TIM_TIXCLK_SOURCE, TIM_TypeDef::SMCR, TI1_Config(), TI2_Config(), TIM_ICSelection_DirectTI, TIM_SelectInputTrigger(), TIM_SlaveMode_External1, and TIM_TIxExternalCLK1Source_TI2.

void TIM_UpdateDisableConfig | ( | TIM_TypeDef * | TIMx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or Disables the TIMx Update event.

Parameters:
TIMx,: where x can be 1 to 17 to select the TIM peripheral.
NewState,: new state of the TIMx UDIS bit This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 2092 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CR1, DISABLE, IS_FUNCTIONAL_STATE, IS_TIM_ALL_PERIPH, and TIM_CR1_UDIS.

void TIM_UpdateRequestConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_UpdateSource
 | ) |  |

Configures the TIMx Update Request Interrupt source.

Parameters:
TIMx,: where x can be 1 to 17 to select the TIM peripheral.
TIM_UpdateSource,: specifies the Update source. This parameter can be one of the following values:

  • TIM_UpdateSource_Regular: Source of update is the counter overflow/underflow or the setting of UG bit, or an update generation through the slave mode controller.
  • TIM_UpdateSource_Global: Source of update is counter overflow/underflow.
Return values:
None

Definition at line 2120 of file stm32f10x_tim.c.

References assert_param, TIM_TypeDef::CR1, IS_TIM_ALL_PERIPH, IS_TIM_UPDATE_SOURCE, TIM_CR1_URS, and TIM_UpdateSource_Global.


STM32F10x Standard Peripherals Firmware Library: USART_ClockInitTypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

USART_ClockInitTypeDef Struct Reference
USART_Exported_Types

USART Clock Init Structure definition. More...

#include <stm32f10x_usart.h>

Data Fields

uint16_t | USART_Clock
uint16_t | USART_CPHA
uint16_t | USART_CPOL
uint16_t | USART_LastBit

Detailed Description

USART Clock Init Structure definition.

Definition at line 82 of file stm32f10x_usart.h.

Field Documentation

uint16_t USART_ClockInitTypeDef::USART_Clock

Specifies whether the USART clock is enabled or disabled. This parameter can be a value of USART_Clock

Definition at line 85 of file stm32f10x_usart.h.

Referenced by main(), USART_ClockInit(), and USART_ClockStructInit().

uint16_t USART_ClockInitTypeDef::USART_CPHA

Specifies the clock transition on which the bit capture is made. This parameter can be a value of USART_Clock_Phase

Definition at line 91 of file stm32f10x_usart.h.

Referenced by main(), USART_ClockInit(), and USART_ClockStructInit().

uint16_t USART_ClockInitTypeDef::USART_CPOL

Specifies the steady state value of the serial clock. This parameter can be a value of USART_Clock_Polarity

Definition at line 88 of file stm32f10x_usart.h.

Referenced by main(), USART_ClockInit(), and USART_ClockStructInit().

uint16_t USART_ClockInitTypeDef::USART_LastBit

Specifies whether the clock pulse corresponding to the last transmitted data bit (MSB) has to be output on the SCLK pin in synchronous mode. This parameter can be a value of USART_Last_Bit

Definition at line 94 of file stm32f10x_usart.h.

Referenced by main(), USART_ClockInit(), and USART_ClockStructInit().

The documentation for this struct was generated from the following file:
  • stm32f10x_usart.h


STM32F10x Standard Peripherals Firmware Library: USART_InitTypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

USART_InitTypeDef Struct Reference
USART_Exported_Types

USART Init Structure definition. More...

#include <stm32f10x_usart.h>

Data Fields

uint32_t | USART_BaudRate
uint16_t | USART_HardwareFlowControl
uint16_t | USART_Mode
uint16_t | USART_Parity
uint16_t | USART_StopBits
uint16_t | USART_WordLength

Detailed Description

USART Init Structure definition.

Definition at line 50 of file stm32f10x_usart.h.

Field Documentation

uint32_t USART_InitTypeDef::USART_BaudRate

This member configures the USART communication baud rate. The baud rate is computed using the following formula:

  • IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate)))
  • FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5

Definition at line 52 of file stm32f10x_usart.h.

Referenced by main(), USART_Init(), and USART_StructInit().

uint16_t USART_InitTypeDef::USART_HardwareFlowControl

Specifies wether the hardware flow control mode is enabled or disabled. This parameter can be a value of USART_Hardware_Flow_Control

Definition at line 73 of file stm32f10x_usart.h.

Referenced by main(), USART_Init(), and USART_StructInit().

uint16_t USART_InitTypeDef::USART_Mode

Specifies wether the Receive or Transmit mode is enabled or disabled. This parameter can be a value of USART_Mode

Definition at line 70 of file stm32f10x_usart.h.

Referenced by main(), USART_Init(), and USART_StructInit().

uint16_t USART_InitTypeDef::USART_Parity

Specifies the parity mode. This parameter can be a value of USART_Parity

Note:
When parity is enabled, the computed parity is inserted at the MSB position of the transmitted data (9th bit when the word length is set to 9 data bits; 8th bit when the word length is set to 8 data bits).

Definition at line 63 of file stm32f10x_usart.h.

Referenced by main(), USART_Init(), and USART_StructInit().

uint16_t USART_InitTypeDef::USART_StopBits

Specifies the number of stop bits transmitted. This parameter can be a value of USART_Stop_Bits

Definition at line 60 of file stm32f10x_usart.h.

Referenced by main(), USART_Init(), and USART_StructInit().

uint16_t USART_InitTypeDef::USART_WordLength

Specifies the number of data bits transmitted or received in a frame. This parameter can be a value of USART_Word_Length

Definition at line 57 of file stm32f10x_usart.h.

Referenced by main(), USART_Init(), and USART_StructInit().

The documentation for this struct was generated from the following file:
  • stm32f10x_usart.h


STM32F10x Standard Peripherals Firmware Library: USART_Word_Length

Defines

USART_Word_Length

USART_Exported_Constants

Defines

#define | IS_USART_WORD_LENGTH(LENGTH)
#define | USART_WordLength_8b ((uint16_t)0x0000)
#define | USART_WordLength_9b ((uint16_t)0x1000)

Define Documentation

#define IS_USART_WORD_LENGTH ( LENGTH )
Value:
(((LENGTH) == USART_WordLength_8b) || \
                                      ((LENGTH) == USART_WordLength_9b))

Definition at line 128 of file stm32f10x_usart.h.

Referenced by USART_Init().

#define USART_WordLength_8b ((uint16_t)0x0000)

Definition at line 125 of file stm32f10x_usart.h.

Referenced by main(), and USART_StructInit().

#define USART_WordLength_9b ((uint16_t)0x1000)

Definition at line 126 of file stm32f10x_usart.h.

Referenced by main().


STM32F10x Standard Peripherals Firmware Library: USART_Stop_Bits

Defines

USART_Stop_Bits

USART_Exported_Constants

Defines

#define | IS_USART_STOPBITS(STOPBITS)
#define | USART_StopBits_0_5 ((uint16_t)0x1000)
#define | USART_StopBits_1 ((uint16_t)0x0000)
#define | USART_StopBits_1_5 ((uint16_t)0x3000)
#define | USART_StopBits_2 ((uint16_t)0x2000)

Define Documentation

#define IS_USART_STOPBITS ( STOPBITS )
Value:
(((STOPBITS) == USART_StopBits_1) || \
                                     ((STOPBITS) == USART_StopBits_0_5) || \
                                     ((STOPBITS) == USART_StopBits_2) || \
                                     ((STOPBITS) == USART_StopBits_1_5))

Definition at line 142 of file stm32f10x_usart.h.

Referenced by USART_Init().

#define USART_StopBits_0_5 ((uint16_t)0x1000)

Definition at line 139 of file stm32f10x_usart.h.

#define USART_StopBits_1 ((uint16_t)0x0000)

Definition at line 138 of file stm32f10x_usart.h.

Referenced by main(), and USART_StructInit().

#define USART_StopBits_1_5 ((uint16_t)0x3000)

Definition at line 141 of file stm32f10x_usart.h.

Referenced by main().

#define USART_StopBits_2 ((uint16_t)0x2000)

Definition at line 140 of file stm32f10x_usart.h.

Referenced by main().


STM32F10x Standard Peripherals Firmware Library: USART_Parity

Defines

USART_Parity

USART_Exported_Constants

Defines

#define | IS_USART_PARITY(PARITY)
#define | USART_Parity_Even ((uint16_t)0x0400)
#define | USART_Parity_No ((uint16_t)0x0000)
#define | USART_Parity_Odd ((uint16_t)0x0600)

Define Documentation

#define IS_USART_PARITY ( PARITY )
Value:
(((PARITY) == USART_Parity_No) || \
                                 ((PARITY) == USART_Parity_Even) || \
                                 ((PARITY) == USART_Parity_Odd))

Definition at line 157 of file stm32f10x_usart.h.

Referenced by USART_Init().

#define USART_Parity_Even ((uint16_t)0x0400)

Definition at line 155 of file stm32f10x_usart.h.

Referenced by main().

#define USART_Parity_No ((uint16_t)0x0000)

Definition at line 154 of file stm32f10x_usart.h.

Referenced by main(), and USART_StructInit().

#define USART_Parity_Odd ((uint16_t)0x0600)

Definition at line 156 of file stm32f10x_usart.h.

Referenced by main().


STM32F10x Standard Peripherals Firmware Library: USART_Mode

Defines

USART_Mode

USART_Exported_Constants

Defines

#define | IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00))
#define | USART_Mode_Rx ((uint16_t)0x0004)
#define | USART_Mode_Tx ((uint16_t)0x0008)

Define Documentation

#define IS_USART_MODE ( MODE ) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00))

Definition at line 170 of file stm32f10x_usart.h.

Referenced by USART_Init().

#define USART_Mode_Rx ((uint16_t)0x0004)

Definition at line 168 of file stm32f10x_usart.h.

Referenced by main(), and USART_StructInit().

#define USART_Mode_Tx ((uint16_t)0x0008)

Definition at line 169 of file stm32f10x_usart.h.

Referenced by main(), and USART_StructInit().


STM32F10x Standard Peripherals Firmware Library: USART_Hardware_Flow_Control

Defines

USART_Hardware_Flow_Control

USART_Exported_Constants

Defines

#define | IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)
#define | USART_HardwareFlowControl_CTS ((uint16_t)0x0200)
#define | USART_HardwareFlowControl_None ((uint16_t)0x0000)
#define | USART_HardwareFlowControl_RTS ((uint16_t)0x0100)
#define | USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300)

Define Documentation

#define IS_USART_HARDWARE_FLOW_CONTROL ( CONTROL )
Value:
(((CONTROL) == USART_HardwareFlowControl_None) || \
                               ((CONTROL) == USART_HardwareFlowControl_RTS) || \
                               ((CONTROL) == USART_HardwareFlowControl_CTS) || \
                               ((CONTROL) == USART_HardwareFlowControl_RTS_CTS))

Definition at line 182 of file stm32f10x_usart.h.

Referenced by USART_Init().

#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200)

Definition at line 180 of file stm32f10x_usart.h.

#define USART_HardwareFlowControl_None ((uint16_t)0x0000)

Definition at line 178 of file stm32f10x_usart.h.

Referenced by main(), USART_Init(), and USART_StructInit().

#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100)

Definition at line 179 of file stm32f10x_usart.h.

#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300)

Definition at line 181 of file stm32f10x_usart.h.

Referenced by main().


STM32F10x Standard Peripherals Firmware Library: USART_Clock

Defines

USART_Clock

USART_Exported_Constants

Defines

#define | IS_USART_CLOCK(CLOCK)
#define | USART_Clock_Disable ((uint16_t)0x0000)
#define | USART_Clock_Enable ((uint16_t)0x0800)

Define Documentation

#define IS_USART_CLOCK ( CLOCK )
Value:
(((CLOCK) == USART_Clock_Disable) || \
                               ((CLOCK) == USART_Clock_Enable))

Definition at line 196 of file stm32f10x_usart.h.

Referenced by USART_ClockInit().

#define USART_Clock_Disable ((uint16_t)0x0000)

Definition at line 194 of file stm32f10x_usart.h.

Referenced by USART_ClockStructInit().

#define USART_Clock_Enable ((uint16_t)0x0800)

Definition at line 195 of file stm32f10x_usart.h.

Referenced by main().


STM32F10x Standard Peripherals Firmware Library: USART_Clock_Polarity

Defines

USART_Clock_Polarity

USART_Exported_Constants

Defines

#define | IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High))
#define | USART_CPOL_High ((uint16_t)0x0400)
#define | USART_CPOL_Low ((uint16_t)0x0000)

Define Documentation

#define IS_USART_CPOL ( CPOL ) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High))

Definition at line 208 of file stm32f10x_usart.h.

Referenced by USART_ClockInit().

#define USART_CPOL_High ((uint16_t)0x0400)

Definition at line 207 of file stm32f10x_usart.h.

Referenced by main().

#define USART_CPOL_Low ((uint16_t)0x0000)

Definition at line 206 of file stm32f10x_usart.h.

Referenced by main(), and USART_ClockStructInit().


STM32F10x Standard Peripherals Firmware Library: USART_Clock_Phase

Defines

USART_Clock_Phase

USART_Exported_Constants

Defines

#define | IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge))
#define | USART_CPHA_1Edge ((uint16_t)0x0000)
#define | USART_CPHA_2Edge ((uint16_t)0x0200)

Define Documentation

#define IS_USART_CPHA ( CPHA ) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge))

Definition at line 220 of file stm32f10x_usart.h.

Referenced by USART_ClockInit().

#define USART_CPHA_1Edge ((uint16_t)0x0000)

Definition at line 218 of file stm32f10x_usart.h.

Referenced by main(), and USART_ClockStructInit().

#define USART_CPHA_2Edge ((uint16_t)0x0200)

Definition at line 219 of file stm32f10x_usart.h.

Referenced by main().


STM32F10x Standard Peripherals Firmware Library: USART_Last_Bit

Defines

USART_Last_Bit

USART_Exported_Constants

Defines

#define | IS_USART_LASTBIT(LASTBIT)
#define | USART_LastBit_Disable ((uint16_t)0x0000)
#define | USART_LastBit_Enable ((uint16_t)0x0100)

Define Documentation

#define IS_USART_LASTBIT ( LASTBIT )
Value:
(((LASTBIT) == USART_LastBit_Disable) || \
                                   ((LASTBIT) == USART_LastBit_Enable))

Definition at line 232 of file stm32f10x_usart.h.

Referenced by USART_ClockInit().

#define USART_LastBit_Disable ((uint16_t)0x0000)

Definition at line 230 of file stm32f10x_usart.h.

Referenced by USART_ClockStructInit().

#define USART_LastBit_Enable ((uint16_t)0x0100)

Definition at line 231 of file stm32f10x_usart.h.

Referenced by main().


STM32F10x Standard Peripherals Firmware Library: USART_Interrupt_definition

Defines

USART_Interrupt_definition

USART_Exported_Constants

Defines

#define | IS_USART_CLEAR_IT(IT)
#define | IS_USART_CONFIG_IT(IT)
#define | IS_USART_GET_IT(IT)
#define | USART_IT_CTS ((uint16_t)0x096A)
#define | USART_IT_ERR ((uint16_t)0x0060)
#define | USART_IT_FE ((uint16_t)0x0160)
#define | USART_IT_IDLE ((uint16_t)0x0424)
#define | USART_IT_LBD ((uint16_t)0x0846)
#define | USART_IT_NE ((uint16_t)0x0260)
#define | USART_IT_ORE ((uint16_t)0x0360)
#define | USART_IT_PE ((uint16_t)0x0028)
#define | USART_IT_RXNE ((uint16_t)0x0525)
#define | USART_IT_TC ((uint16_t)0x0626)
#define | USART_IT_TXE ((uint16_t)0x0727)

Define Documentation

#define IS_USART_CLEAR_IT ( IT )
Value:
(((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
                               ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS))

Definition at line 262 of file stm32f10x_usart.h.

Referenced by USART_ClearITPendingBit().

#define IS_USART_CONFIG_IT ( IT )
Value:
(((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
                               ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
                               ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
                               ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR))

Definition at line 253 of file stm32f10x_usart.h.

Referenced by USART_ITConfig().

#define IS_USART_GET_IT ( IT )
Value:
(((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
                            ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
                            ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
                            ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \
                            ((IT) == USART_IT_NE) || ((IT) == USART_IT_FE))

Definition at line 257 of file stm32f10x_usart.h.

Referenced by USART_GetITStatus().

#define USART_IT_CTS ((uint16_t)0x096A)

Definition at line 248 of file stm32f10x_usart.h.

Referenced by USART_ClearITPendingBit(), USART_GetITStatus(), and USART_ITConfig().

#define USART_IT_ERR ((uint16_t)0x0060)

Definition at line 249 of file stm32f10x_usart.h.

#define USART_IT_FE ((uint16_t)0x0160)

Definition at line 252 of file stm32f10x_usart.h.

#define USART_IT_IDLE ((uint16_t)0x0424)

Definition at line 246 of file stm32f10x_usart.h.

#define USART_IT_LBD ((uint16_t)0x0846)

Definition at line 247 of file stm32f10x_usart.h.

#define USART_IT_NE ((uint16_t)0x0260)

Definition at line 251 of file stm32f10x_usart.h.

#define USART_IT_ORE ((uint16_t)0x0360)

Definition at line 250 of file stm32f10x_usart.h.

#define USART_IT_PE ((uint16_t)0x0028)

Definition at line 242 of file stm32f10x_usart.h.

Referenced by main(), and SC_USART_IRQHandler().

#define USART_IT_RXNE ((uint16_t)0x0525)

Definition at line 245 of file stm32f10x_usart.h.

Referenced by main(), SC_USART_IRQHandler(), USART2_IRQHandler(), USART3_IRQHandler(), USARTx_IRQHandler(), USARTy_IRQHandler(), and USARTz_IRQHandler().

#define USART_IT_TC ((uint16_t)0x0626)

Definition at line 244 of file stm32f10x_usart.h.

#define USART_IT_TXE ((uint16_t)0x0727)

Definition at line 243 of file stm32f10x_usart.h.

Referenced by main(), USARTx_IRQHandler(), USARTy_IRQHandler(), and USARTz_IRQHandler().


STM32F10x Standard Peripherals Firmware Library: USART_DMA_Requests

Defines

USART_DMA_Requests

USART_Exported_Constants

Defines

#define | IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00))
#define | USART_DMAReq_Rx ((uint16_t)0x0040)
#define | USART_DMAReq_Tx ((uint16_t)0x0080)

Define Documentation

#define IS_USART_DMAREQ ( DMAREQ ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00))

Definition at line 274 of file stm32f10x_usart.h.

Referenced by USART_DMACmd().

#define USART_DMAReq_Rx ((uint16_t)0x0040)

Definition at line 273 of file stm32f10x_usart.h.

Referenced by main().

#define USART_DMAReq_Tx ((uint16_t)0x0080)

Definition at line 272 of file stm32f10x_usart.h.

Referenced by main().


STM32F10x Standard Peripherals Firmware Library: USART_WakeUp_methods

Defines

USART_WakeUp_methods

USART_Exported_Constants

Defines

#define | IS_USART_WAKEUP(WAKEUP)
#define | USART_WakeUp_AddressMark ((uint16_t)0x0800)
#define | USART_WakeUp_IdleLine ((uint16_t)0x0000)

Define Documentation

#define IS_USART_WAKEUP ( WAKEUP )
Value:
(((WAKEUP) == USART_WakeUp_IdleLine) || \
                                 ((WAKEUP) == USART_WakeUp_AddressMark))

Definition at line 286 of file stm32f10x_usart.h.

Referenced by USART_WakeUpConfig().

#define USART_WakeUp_AddressMark ((uint16_t)0x0800)

Definition at line 285 of file stm32f10x_usart.h.

Referenced by main().

#define USART_WakeUp_IdleLine ((uint16_t)0x0000)

Definition at line 284 of file stm32f10x_usart.h.


STM32F10x Standard Peripherals Firmware Library: USART_LIN_Break_Detection_Length

Defines

USART_LIN_Break_Detection_Length

USART_Exported_Constants

Defines

#define | IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH)
#define | USART_LINBreakDetectLength_10b ((uint16_t)0x0000)
#define | USART_LINBreakDetectLength_11b ((uint16_t)0x0020)

Define Documentation

#define IS_USART_LIN_BREAK_DETECT_LENGTH ( LENGTH )
Value:
(((LENGTH) == USART_LINBreakDetectLength_10b) || \
                                ((LENGTH) == USART_LINBreakDetectLength_11b))

Definition at line 298 of file stm32f10x_usart.h.

Referenced by USART_LINBreakDetectLengthConfig().

#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000)

Definition at line 296 of file stm32f10x_usart.h.

#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020)

Definition at line 297 of file stm32f10x_usart.h.


STM32F10x Standard Peripherals Firmware Library: USART_IrDA_Low_Power

Defines

USART_IrDA_Low_Power

USART_Exported_Constants

Defines

#define | IS_USART_IRDA_MODE(MODE)
#define | USART_IrDAMode_LowPower ((uint16_t)0x0004)
#define | USART_IrDAMode_Normal ((uint16_t)0x0000)

Define Documentation

#define IS_USART_IRDA_MODE ( MODE )
Value:
(((MODE) == USART_IrDAMode_LowPower) || \
                                  ((MODE) == USART_IrDAMode_Normal))

Definition at line 311 of file stm32f10x_usart.h.

Referenced by USART_IrDAConfig().

#define USART_IrDAMode_LowPower ((uint16_t)0x0004)

Definition at line 309 of file stm32f10x_usart.h.

#define USART_IrDAMode_Normal ((uint16_t)0x0000)

Definition at line 310 of file stm32f10x_usart.h.

Referenced by main().


STM32F10x Standard Peripherals Firmware Library: USART_Flags

Defines

USART_Flags

USART_Exported_Constants

Defines

#define | IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF)
#define | IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x0044AA21))
#define | IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00))
#define | IS_USART_DATA(DATA) ((DATA) <= 0x1FF)
#define | IS_USART_FLAG(FLAG)
#define | IS_USART_PERIPH_FLAG(PERIPH, USART_FLAG)
#define | USART_FLAG_CTS ((uint16_t)0x0200)
#define | USART_FLAG_FE ((uint16_t)0x0002)
#define | USART_FLAG_IDLE ((uint16_t)0x0010)
#define | USART_FLAG_LBD ((uint16_t)0x0100)
#define | USART_FLAG_NE ((uint16_t)0x0004)
#define | USART_FLAG_ORE ((uint16_t)0x0008)
#define | USART_FLAG_PE ((uint16_t)0x0001)
#define | USART_FLAG_RXNE ((uint16_t)0x0020)
#define | USART_FLAG_TC ((uint16_t)0x0040)
#define | USART_FLAG_TXE ((uint16_t)0x0080)

Define Documentation

#define IS_USART_ADDRESS ( ADDRESS ) ((ADDRESS) <= 0xF)

Definition at line 342 of file stm32f10x_usart.h.

Referenced by USART_SetAddress().

#define IS_USART_BAUDRATE ( BAUDRATE ) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x0044AA21))

Definition at line 341 of file stm32f10x_usart.h.

Referenced by USART_Init().

#define IS_USART_CLEAR_FLAG ( FLAG ) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00))

Definition at line 337 of file stm32f10x_usart.h.

Referenced by USART_ClearFlag().

#define IS_USART_DATA ( DATA ) ((DATA) <= 0x1FF)

Definition at line 343 of file stm32f10x_usart.h.

Referenced by USART_SendData().

#define IS_USART_FLAG ( FLAG )
Value:
(((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \
                             ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \
                             ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \
                             ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \
                             ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE))

Definition at line 331 of file stm32f10x_usart.h.

Referenced by USART_GetFlagStatus().

#define IS_USART_PERIPH_FLAG | ( | PERIPH,
 |  | USART_FLAG
 | ) |
Value:
((((*(uint32_t*)&(PERIPH)) != UART4_BASE) &&\
                                                  ((*(uint32_t*)&(PERIPH)) != UART5_BASE)) \
                                                  || ((USART_FLAG) != USART_FLAG_CTS))

Definition at line 338 of file stm32f10x_usart.h.

#define USART_FLAG_CTS ((uint16_t)0x0200)

Definition at line 321 of file stm32f10x_usart.h.

Referenced by USART_ClearFlag(), and USART_GetFlagStatus().

#define USART_FLAG_FE ((uint16_t)0x0002)

Definition at line 329 of file stm32f10x_usart.h.

#define USART_FLAG_IDLE ((uint16_t)0x0010)

Definition at line 326 of file stm32f10x_usart.h.

#define USART_FLAG_LBD ((uint16_t)0x0100)

Definition at line 322 of file stm32f10x_usart.h.

#define USART_FLAG_NE ((uint16_t)0x0004)

Definition at line 328 of file stm32f10x_usart.h.

#define USART_FLAG_ORE ((uint16_t)0x0008)

Definition at line 327 of file stm32f10x_usart.h.

#define USART_FLAG_PE ((uint16_t)0x0001)

Definition at line 330 of file stm32f10x_usart.h.

#define USART_FLAG_RXNE ((uint16_t)0x0020)

Definition at line 325 of file stm32f10x_usart.h.

Referenced by main().

#define USART_FLAG_TC ((uint16_t)0x0040)

Definition at line 324 of file stm32f10x_usart.h.

Referenced by main().

#define USART_FLAG_TXE ((uint16_t)0x0080)

Definition at line 323 of file stm32f10x_usart.h.

Referenced by EXTI0_IRQHandler(), and main().


STM32F10x Standard Peripherals Firmware Library: USART_Exported_Constants

Modules | Defines

USART_Exported_Constants

USART

Modules

USART_Word_Length
USART_Stop_Bits
USART_Parity
USART_Mode
USART_Hardware_Flow_Control
USART_Clock
USART_Clock_Polarity
USART_Clock_Phase
USART_Last_Bit
USART_Interrupt_definition
USART_DMA_Requests
USART_WakeUp_methods
USART_LIN_Break_Detection_Length
USART_IrDA_Low_Power
USART_Flags

Defines

#define | IS_USART_1234_PERIPH(PERIPH)
#define | IS_USART_123_PERIPH(PERIPH)
#define | IS_USART_ALL_PERIPH(PERIPH)

Define Documentation

#define IS_USART_1234_PERIPH ( PERIPH )
Value:
(((PERIPH) == USART1) || \
                                      ((PERIPH) == USART2) || \
                                      ((PERIPH) == USART3) || \
                                      ((PERIPH) == UART4))

Definition at line 117 of file stm32f10x_usart.h.

#define IS_USART_123_PERIPH ( PERIPH )
Value:
(((PERIPH) == USART1) || \
                                     ((PERIPH) == USART2) || \
                                     ((PERIPH) == USART3))

Definition at line 113 of file stm32f10x_usart.h.

Referenced by USART_ClearFlag(), USART_ClearITPendingBit(), USART_ClockInit(), USART_GetFlagStatus(), USART_GetITStatus(), USART_Init(), USART_ITConfig(), USART_SetGuardTime(), USART_SmartCardCmd(), and USART_SmartCardNACKCmd().

#define IS_USART_ALL_PERIPH ( PERIPH )
Value:
(((PERIPH) == USART1) || \
                                     ((PERIPH) == USART2) || \
                                     ((PERIPH) == USART3) || \
                                     ((PERIPH) == UART4) || \
                                     ((PERIPH) == UART5))

Definition at line 107 of file stm32f10x_usart.h.

Referenced by USART_ClearFlag(), USART_ClearITPendingBit(), USART_Cmd(), USART_DeInit(), USART_DMACmd(), USART_GetFlagStatus(), USART_GetITStatus(), USART_HalfDuplexCmd(), USART_Init(), USART_IrDACmd(), USART_IrDAConfig(), USART_ITConfig(), USART_LINBreakDetectLengthConfig(), USART_LINCmd(), USART_OneBitMethodCmd(), USART_OverSampling8Cmd(), USART_ReceiveData(), USART_ReceiverWakeUpCmd(), USART_SendBreak(), USART_SendData(), USART_SetAddress(), USART_SetPrescaler(), and USART_WakeUpConfig().


STM32F10x Standard Peripherals Firmware Library: USART_Exported_Macros

USART_Exported_Macros

USART


STM32F10x Standard Peripherals Firmware Library: USART_Exported_Functions

Functions

USART_Exported_Functions

USART

Functions

void | USART_ClearFlag (USART_TypeDef *USARTx, uint16_t USART_FLAG)
Clears the USARTx's pending flags.
void | USART_ClearITPendingBit (USART_TypeDef *USARTx, uint16_t USART_IT)
Clears the USARTx's interrupt pending bits.
void | USART_ClockInit (USART_TypeDef *USARTx, USART_ClockInitTypeDef *USART_ClockInitStruct)
Initializes the USARTx peripheral Clock according to the specified parameters in the USART_ClockInitStruct .
void | USART_ClockStructInit (USART_ClockInitTypeDef *USART_ClockInitStruct)
Fills each USART_ClockInitStruct member with its default value.
void | USART_Cmd (USART_TypeDef *USARTx, FunctionalState NewState)
Enables or disables the specified USART peripheral.
void | USART_DeInit (USART_TypeDef *USARTx)
Deinitializes the USARTx peripheral registers to their default reset values.
void | USART_DMACmd (USART_TypeDef *USARTx, uint16_t USART_DMAReq, FunctionalState NewState)
Enables or disables the USART’s DMA interface.
FlagStatus | USART_GetFlagStatus (USART_TypeDef *USARTx, uint16_t USART_FLAG)
Checks whether the specified USART flag is set or not.
ITStatus | USART_GetITStatus (USART_TypeDef *USARTx, uint16_t USART_IT)
Checks whether the specified USART interrupt has occurred or not.
void | USART_HalfDuplexCmd (USART_TypeDef *USARTx, FunctionalState NewState)
Enables or disables the USART’s Half Duplex communication.
void | USART_Init (USART_TypeDef *USARTx, USART_InitTypeDef *USART_InitStruct)
Initializes the USARTx peripheral according to the specified parameters in the USART_InitStruct .
void | USART_IrDACmd (USART_TypeDef *USARTx, FunctionalState NewState)
Enables or disables the USART's IrDA interface.
void | USART_IrDAConfig (USART_TypeDef *USARTx, uint16_t USART_IrDAMode)
Configures the USART's IrDA interface.
void | USART_ITConfig (USART_TypeDef *USARTx, uint16_t USART_IT, FunctionalState NewState)
Enables or disables the specified USART interrupts.
void | USART_LINBreakDetectLengthConfig (USART_TypeDef *USARTx, uint16_t USART_LINBreakDetectLength)
Sets the USART LIN Break detection length.
void | USART_LINCmd (USART_TypeDef *USARTx, FunctionalState NewState)
Enables or disables the USART’s LIN mode.
void | USART_OneBitMethodCmd (USART_TypeDef *USARTx, FunctionalState NewState)
Enables or disables the USART's one bit sampling method.
void | USART_OverSampling8Cmd (USART_TypeDef *USARTx, FunctionalState NewState)
Enables or disables the USART's 8x oversampling mode.
uint16_t | USART_ReceiveData (USART_TypeDef *USARTx)
Returns the most recent received data by the USARTx peripheral.
void | USART_ReceiverWakeUpCmd (USART_TypeDef *USARTx, FunctionalState NewState)
Determines if the USART is in mute mode or not.
void | USART_SendBreak (USART_TypeDef *USARTx)
Transmits break characters.
void | USART_SendData (USART_TypeDef *USARTx, uint16_t Data)
Transmits single data through the USARTx peripheral.
void | USART_SetAddress (USART_TypeDef *USARTx, uint8_t USART_Address)
Sets the address of the USART node.
void | USART_SetGuardTime (USART_TypeDef *USARTx, uint8_t USART_GuardTime)
Sets the specified USART guard time.
void | USART_SetPrescaler (USART_TypeDef *USARTx, uint8_t USART_Prescaler)
Sets the system clock prescaler.
void | USART_SmartCardCmd (USART_TypeDef *USARTx, FunctionalState NewState)
Enables or disables the USART’s Smart Card mode.
void | USART_SmartCardNACKCmd (USART_TypeDef *USARTx, FunctionalState NewState)
Enables or disables NACK transmission.
void | USART_StructInit (USART_InitTypeDef *USART_InitStruct)
Fills each USART_InitStruct member with its default value.
void | USART_WakeUpConfig (USART_TypeDef *USARTx, uint16_t USART_WakeUp)
Selects the USART WakeUp method.

Function Documentation

void USART_ClearFlag | ( | USART_TypeDef * | USARTx,
 |  | uint16_t | USART_FLAG
 | ) |  |

Clears the USARTx's pending flags.

Parameters:
USARTx,: Select the USART or the UART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
USART_FLAG,: specifies the flag to clear. This parameter can be any combination of the following values:

  • USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5).
  • USART_FLAG_LBD: LIN Break detection flag.
  • USART_FLAG_TC: Transmission Complete flag.
  • USART_FLAG_RXNE: Receive data register not empty flag.
Note:
  • PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun error) and IDLE (Idle line detected) flags are cleared by software sequence: a read operation to USART_SR register (USART_GetFlagStatus()) followed by a read operation to USART_DR register (USART_ReceiveData()).
  • RXNE flag can be also cleared by a read to the USART_DR register (USART_ReceiveData()).
  • TC flag can be also cleared by software sequence: a read operation to USART_SR register (USART_GetFlagStatus()) followed by a write operation to USART_DR register (USART_SendData()).
  • TXE flag is cleared only by a write to the USART_DR register (USART_SendData()).
Return values:
None

Definition at line 923 of file stm32f10x_usart.c.

References assert_param, IS_USART_123_PERIPH, IS_USART_ALL_PERIPH, IS_USART_CLEAR_FLAG, USART_TypeDef::SR, and USART_FLAG_CTS.

void USART_ClearITPendingBit | ( | USART_TypeDef * | USARTx,
 |  | uint16_t | USART_IT
 | ) |  |

Clears the USARTx's interrupt pending bits.

Parameters:
USARTx,: Select the USART or the UART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
USART_IT,: specifies the interrupt pending bit to clear. This parameter can be one of the following values:

  • USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
  • USART_IT_LBD: LIN Break detection interrupt
  • USART_IT_TC: Transmission complete interrupt.
  • USART_IT_RXNE: Receive Data register not empty interrupt.
Note:
  • PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun error) and IDLE (Idle line detected) pending bits are cleared by software sequence: a read operation to USART_SR register (USART_GetITStatus()) followed by a read operation to USART_DR register (USART_ReceiveData()).
  • RXNE pending bit can be also cleared by a read to the USART_DR register (USART_ReceiveData()).
  • TC pending bit can be also cleared by software sequence: a read operation to USART_SR register (USART_GetITStatus()) followed by a write operation to USART_DR register (USART_SendData()).
  • TXE pending bit is cleared only by a write to the USART_DR register (USART_SendData()).
Return values:
None

Definition at line 1030 of file stm32f10x_usart.c.

References assert_param, IS_USART_123_PERIPH, IS_USART_ALL_PERIPH, IS_USART_CLEAR_IT, USART_TypeDef::SR, and USART_IT_CTS.

void USART_ClockInit | ( | USART_TypeDef * | USARTx,
 |  | USART_ClockInitTypeDef * | USART_ClockInitStruct
 | ) |  |

Initializes the USARTx peripheral Clock according to the specified parameters in the USART_ClockInitStruct .

Parameters:
USARTx,: where x can be 1, 2, 3 to select the USART peripheral.
USART_ClockInitStruct,: pointer to a USART_ClockInitTypeDef structure that contains the configuration information for the specified USART peripheral.
Note:
The Smart Card and Synchronous modes are not available for UART4 and UART5.
Return values:
None

Definition at line 302 of file stm32f10x_usart.c.

References assert_param, USART_TypeDef::CR2, CR2_CLOCK_CLEAR_Mask, IS_USART_123_PERIPH, IS_USART_CLOCK, IS_USART_CPHA, IS_USART_CPOL, IS_USART_LASTBIT, USART_ClockInitTypeDef::USART_Clock, USART_ClockInitTypeDef::USART_CPHA, USART_ClockInitTypeDef::USART_CPOL, and USART_ClockInitTypeDef::USART_LastBit.

Referenced by main().

void USART_ClockStructInit ( USART_ClockInitTypeDef * USART_ClockInitStruct )

Fills each USART_ClockInitStruct member with its default value.

Parameters:
USART_ClockInitStruct,: pointer to a USART_ClockInitTypeDef structure which will be initialized.
Return values:
None

Definition at line 333 of file stm32f10x_usart.c.

References USART_ClockInitTypeDef::USART_Clock, USART_Clock_Disable, USART_ClockInitTypeDef::USART_CPHA, USART_CPHA_1Edge, USART_ClockInitTypeDef::USART_CPOL, USART_CPOL_Low, USART_ClockInitTypeDef::USART_LastBit, and USART_LastBit_Disable.

void USART_Cmd | ( | USART_TypeDef * | USARTx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified USART peripheral.

Parameters:
USARTx,: Select the USART or the UART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
NewState,: new state of the USARTx peripheral. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 351 of file stm32f10x_usart.c.

References assert_param, USART_TypeDef::CR1, CR1_UE_Reset, CR1_UE_Set, DISABLE, IS_FUNCTIONAL_STATE, and IS_USART_ALL_PERIPH.

Referenced by main(), and STM_EVAL_COMInit().

void USART_DeInit ( USART_TypeDef * USARTx )

Deinitializes the USARTx peripheral registers to their default reset values.

Parameters:
USARTx,: Select the USART or the UART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
Return values:
None

Definition at line 130 of file stm32f10x_usart.c.

References assert_param, DISABLE, ENABLE, IS_USART_ALL_PERIPH, RCC_APB1Periph_UART4, RCC_APB1Periph_UART5, RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1PeriphResetCmd(), RCC_APB2Periph_USART1, RCC_APB2PeriphResetCmd(), UART4, UART5, USART1, USART2, and USART3.

void USART_DMACmd | ( | USART_TypeDef * | USARTx,
 |  | uint16_t | USART_DMAReq,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the USART’s DMA interface.

Parameters:
USARTx,: Select the USART or the UART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
USART_DMAReq,: specifies the DMA request. This parameter can be any combination of the following values:

  • USART_DMAReq_Tx: USART DMA transmit request
  • USART_DMAReq_Rx: USART DMA receive request
NewState,: new state of the DMA Request sources. This parameter can be: ENABLE or DISABLE.
Note:
The DMA mode is not available for UART5 except in the STM32 High density value line devices(STM32F10X_HD_VL).
Return values:
None

Definition at line 448 of file stm32f10x_usart.c.

References assert_param, USART_TypeDef::CR3, DISABLE, IS_FUNCTIONAL_STATE, IS_USART_ALL_PERIPH, and IS_USART_DMAREQ.

Referenced by main().

FlagStatus USART_GetFlagStatus | ( | USART_TypeDef * | USARTx,
 |  | uint16_t | USART_FLAG
 | ) |  |

Checks whether the specified USART flag is set or not.

Parameters:
USARTx,: Select the USART or the UART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
USART_FLAG,: specifies the flag to check. This parameter can be one of the following values:

  • USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5)
  • USART_FLAG_LBD: LIN Break detection flag
  • USART_FLAG_TXE: Transmit data register empty flag
  • USART_FLAG_TC: Transmission Complete flag
  • USART_FLAG_RXNE: Receive data register not empty flag
  • USART_FLAG_IDLE: Idle Line detection flag
  • USART_FLAG_ORE: OverRun Error flag
  • USART_FLAG_NE: Noise Error flag
  • USART_FLAG_FE: Framing Error flag
  • USART_FLAG_PE: Parity Error flag
Return values:
The new state of USART_FLAG (SET or RESET).

Definition at line 874 of file stm32f10x_usart.c.

References assert_param, IS_USART_123_PERIPH, IS_USART_ALL_PERIPH, IS_USART_FLAG, RESET, SET, USART_TypeDef::SR, and USART_FLAG_CTS.

Referenced by EXTI0_IRQHandler(), and main().

ITStatus USART_GetITStatus | ( | USART_TypeDef * | USARTx,
 |  | uint16_t | USART_IT
 | ) |  |

Checks whether the specified USART interrupt has occurred or not.

Parameters:
USARTx,: Select the USART or the UART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
USART_IT,: specifies the USART interrupt source to check. This parameter can be one of the following values:

  • USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
  • USART_IT_LBD: LIN Break detection interrupt
  • USART_IT_TXE: Tansmit Data Register empty interrupt
  • USART_IT_TC: Transmission complete interrupt
  • USART_IT_RXNE: Receive Data register not empty interrupt
  • USART_IT_IDLE: Idle line detection interrupt
  • USART_IT_ORE: OverRun Error interrupt
  • USART_IT_NE: Noise Error interrupt
  • USART_IT_FE: Framing Error interrupt
  • USART_IT_PE: Parity Error interrupt
Return values:
The new state of USART_IT (SET or RESET).

Definition at line 956 of file stm32f10x_usart.c.

References assert_param, USART_TypeDef::CR1, USART_TypeDef::CR2, USART_TypeDef::CR3, IS_USART_123_PERIPH, IS_USART_ALL_PERIPH, IS_USART_GET_IT, IT_Mask, RESET, SET, USART_TypeDef::SR, and USART_IT_CTS.

Referenced by SC_USART_IRQHandler(), USART2_IRQHandler(), USART3_IRQHandler(), USARTx_IRQHandler(), USARTy_IRQHandler(), and USARTz_IRQHandler().

void USART_HalfDuplexCmd | ( | USART_TypeDef * | USARTx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the USART’s Half Duplex communication.

Parameters:
USARTx,: Select the USART or the UART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
NewState,: new state of the USART Communication. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 731 of file stm32f10x_usart.c.

References assert_param, USART_TypeDef::CR3, CR3_HDSEL_Reset, CR3_HDSEL_Set, DISABLE, IS_FUNCTIONAL_STATE, and IS_USART_ALL_PERIPH.

Referenced by main().

void USART_Init | ( | USART_TypeDef * | USARTx,
 |  | USART_InitTypeDef * | USART_InitStruct
 | ) |  |

Initializes the USARTx peripheral according to the specified parameters in the USART_InitStruct .

Parameters:
USARTx,: Select the USART or the UART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
USART_InitStruct,: pointer to a USART_InitTypeDef structure that contains the configuration information for the specified USART peripheral.
Return values:
None

Definition at line 176 of file stm32f10x_usart.c.

References assert_param, USART_TypeDef::BRR, USART_TypeDef::CR1, CR1_CLEAR_Mask, CR1_OVER8_Set, USART_TypeDef::CR2, CR2_STOP_CLEAR_Mask, USART_TypeDef::CR3, CR3_CLEAR_Mask, IS_USART_123_PERIPH, IS_USART_ALL_PERIPH, IS_USART_BAUDRATE, IS_USART_HARDWARE_FLOW_CONTROL, IS_USART_MODE, IS_USART_PARITY, IS_USART_STOPBITS, IS_USART_WORD_LENGTH, RCC_ClocksTypeDef::PCLK1_Frequency, RCC_ClocksTypeDef::PCLK2_Frequency, RCC_GetClocksFreq(), USART1_BASE, USART_InitTypeDef::USART_BaudRate, USART_InitTypeDef::USART_HardwareFlowControl, USART_HardwareFlowControl_None, USART_InitTypeDef::USART_Mode, USART_InitTypeDef::USART_Parity, USART_InitTypeDef::USART_StopBits, and USART_InitTypeDef::USART_WordLength.

Referenced by main(), and STM_EVAL_COMInit().

void USART_IrDACmd | ( | USART_TypeDef * | USARTx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the USART's IrDA interface.

Parameters:
USARTx,: Select the USART or the UART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
NewState,: new state of the IrDA mode. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 837 of file stm32f10x_usart.c.

References assert_param, USART_TypeDef::CR3, CR3_IREN_Reset, CR3_IREN_Set, DISABLE, IS_FUNCTIONAL_STATE, and IS_USART_ALL_PERIPH.

Referenced by main().

void USART_IrDAConfig | ( | USART_TypeDef * | USARTx,
 |  | uint16_t | USART_IrDAMode
 | ) |  |

Configures the USART's IrDA interface.

Parameters:
USARTx,: Select the USART or the UART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
USART_IrDAMode,: specifies the IrDA mode. This parameter can be one of the following values:

  • USART_IrDAMode_LowPower
  • USART_IrDAMode_Normal
Return values:
None

Definition at line 818 of file stm32f10x_usart.c.

References assert_param, USART_TypeDef::CR3, CR3_IRLP_Mask, IS_USART_ALL_PERIPH, and IS_USART_IRDA_MODE.

Referenced by main().

void USART_ITConfig | ( | USART_TypeDef * | USARTx,
 |  | uint16_t | USART_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified USART interrupts.

Parameters:
USARTx,: Select the USART or the UART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
USART_IT,: specifies the USART interrupt sources to be enabled or disabled. This parameter can be one of the following values:

  • USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
  • USART_IT_LBD: LIN Break detection interrupt
  • USART_IT_TXE: Transmit Data Register empty interrupt
  • USART_IT_TC: Transmission complete interrupt
  • USART_IT_RXNE: Receive Data register not empty interrupt
  • USART_IT_IDLE: Idle line detection interrupt
  • USART_IT_PE: Parity Error interrupt
  • USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
NewState,: new state of the specified USARTx interrupts. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 388 of file stm32f10x_usart.c.

References assert_param, DISABLE, IS_FUNCTIONAL_STATE, IS_USART_123_PERIPH, IS_USART_ALL_PERIPH, IS_USART_CONFIG_IT, IT_Mask, and USART_IT_CTS.

Referenced by main(), SC_USART_IRQHandler(), USART2_IRQHandler(), USART3_IRQHandler(), USARTx_IRQHandler(), USARTy_IRQHandler(), and USARTz_IRQHandler().

void USART_LINBreakDetectLengthConfig | ( | USART_TypeDef * | USARTx,
 |  | uint16_t | USART_LINBreakDetectLength
 | ) |  |

Sets the USART LIN Break detection length.

Parameters:
USARTx,: Select the USART or the UART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
USART_LINBreakDetectLength,: specifies the LIN break detection length. This parameter can be one of the following values:

  • USART_LINBreakDetectLength_10b: 10-bit break detection
  • USART_LINBreakDetectLength_11b: 11-bit break detection
Return values:
None

Definition at line 547 of file stm32f10x_usart.c.

References assert_param, USART_TypeDef::CR2, CR2_LBDL_Mask, IS_USART_ALL_PERIPH, and IS_USART_LIN_BREAK_DETECT_LENGTH.

void USART_LINCmd | ( | USART_TypeDef * | USARTx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the USART’s LIN mode.

Parameters:
USARTx,: Select the USART or the UART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
NewState,: new state of the USART LIN mode. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 566 of file stm32f10x_usart.c.

References assert_param, USART_TypeDef::CR2, CR2_LINEN_Reset, CR2_LINEN_Set, DISABLE, IS_FUNCTIONAL_STATE, and IS_USART_ALL_PERIPH.

void USART_OneBitMethodCmd | ( | USART_TypeDef * | USARTx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the USART's one bit sampling method.

Parameters:
USARTx,: Select the USART or the UART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
NewState,: new state of the USART one bit sampling method. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 789 of file stm32f10x_usart.c.

References assert_param, USART_TypeDef::CR3, CR3_ONEBITE_Reset, CR3_ONEBITE_Set, DISABLE, IS_FUNCTIONAL_STATE, and IS_USART_ALL_PERIPH.

void USART_OverSampling8Cmd | ( | USART_TypeDef * | USARTx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the USART's 8x oversampling mode.

Parameters:
USARTx,: Select the USART or the UART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
NewState,: new state of the USART one bit sampling method. This parameter can be: ENABLE or DISABLE.
Note:
This function has to be called before calling USART_Init() function in order to have correct baudrate Divider value.
Return values:
None

Definition at line 762 of file stm32f10x_usart.c.

References assert_param, USART_TypeDef::CR1, CR1_OVER8_Reset, CR1_OVER8_Set, DISABLE, IS_FUNCTIONAL_STATE, and IS_USART_ALL_PERIPH.

uint16_t USART_ReceiveData ( USART_TypeDef * USARTx )

Returns the most recent received data by the USARTx peripheral.

Parameters:
USARTx,: Select the USART or the UART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
Return values:
The received data.

Definition at line 609 of file stm32f10x_usart.c.

References assert_param, USART_TypeDef::DR, and IS_USART_ALL_PERIPH.

Referenced by EXTI9_5_IRQHandler(), main(), SC_USART_IRQHandler(), USART2_IRQHandler(), USART3_IRQHandler(), USARTx_IRQHandler(), USARTy_IRQHandler(), and USARTz_IRQHandler().

void USART_ReceiverWakeUpCmd | ( | USART_TypeDef * | USARTx,
 |  | FunctionalState | NewState
 | ) |  |

Determines if the USART is in mute mode or not.

Parameters:
USARTx,: Select the USART or the UART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
NewState,: new state of the USART mute mode. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 518 of file stm32f10x_usart.c.

References assert_param, USART_TypeDef::CR1, CR1_RWU_Reset, CR1_RWU_Set, DISABLE, IS_FUNCTIONAL_STATE, and IS_USART_ALL_PERIPH.

Referenced by EXTI9_5_IRQHandler().

void USART_SendBreak ( USART_TypeDef * USARTx )

Transmits break characters.

Parameters:
USARTx,: Select the USART or the UART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
Return values:
None

Definition at line 625 of file stm32f10x_usart.c.

References assert_param, USART_TypeDef::CR1, CR1_SBK_Set, and IS_USART_ALL_PERIPH.

void USART_SendData | ( | USART_TypeDef * | USARTx,
 |  | uint16_t | Data
 | ) |  |

Transmits single data through the USARTx peripheral.

Parameters:
USARTx,: Select the USART or the UART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
Data,: the data to transmit.
Return values:
None

Definition at line 592 of file stm32f10x_usart.c.

References assert_param, USART_TypeDef::DR, IS_USART_ALL_PERIPH, and IS_USART_DATA.

Referenced by EXTI0_IRQHandler(), main(), USARTx_IRQHandler(), USARTy_IRQHandler(), and USARTz_IRQHandler().

void USART_SetAddress | ( | USART_TypeDef * | USARTx,
 |  | uint8_t | USART_Address
 | ) |  |

Sets the address of the USART node.

Parameters:
USARTx,: Select the USART or the UART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
USART_Address,: Indicates the address of the USART node.
Return values:
None

Definition at line 476 of file stm32f10x_usart.c.

References assert_param, USART_TypeDef::CR2, CR2_Address_Mask, IS_USART_ADDRESS, and IS_USART_ALL_PERIPH.

Referenced by main().

void USART_SetGuardTime | ( | USART_TypeDef * | USARTx,
 |  | uint8_t | USART_GuardTime
 | ) |  |

Sets the specified USART guard time.

Parameters:
USARTx,: where x can be 1, 2 or 3 to select the USART peripheral.
USART_GuardTime,: specifies the guard time.
Note:
The guard time bits are not available for UART4 and UART5.
Return values:
None

Definition at line 641 of file stm32f10x_usart.c.

References assert_param, USART_TypeDef::GTPR, GTPR_LSB_Mask, and IS_USART_123_PERIPH.

Referenced by main().

void USART_SetPrescaler | ( | USART_TypeDef * | USARTx,
 |  | uint8_t | USART_Prescaler
 | ) |  |

Sets the system clock prescaler.

Parameters:
USARTx,: Select the USART or the UART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
USART_Prescaler,: specifies the prescaler clock.
Note:
The function is used for IrDA mode with UART4 and UART5.
Return values:
None

Definition at line 661 of file stm32f10x_usart.c.

References assert_param, USART_TypeDef::GTPR, GTPR_MSB_Mask, and IS_USART_ALL_PERIPH.

Referenced by main().

void USART_SmartCardCmd | ( | USART_TypeDef * | USARTx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the USART’s Smart Card mode.

Parameters:
USARTx,: where x can be 1, 2 or 3 to select the USART peripheral.
NewState,: new state of the Smart Card mode. This parameter can be: ENABLE or DISABLE.
Note:
The Smart Card mode is not available for UART4 and UART5.
Return values:
None

Definition at line 680 of file stm32f10x_usart.c.

References assert_param, USART_TypeDef::CR3, CR3_SCEN_Reset, CR3_SCEN_Set, DISABLE, IS_FUNCTIONAL_STATE, and IS_USART_123_PERIPH.

Referenced by main().

void USART_SmartCardNACKCmd | ( | USART_TypeDef * | USARTx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables NACK transmission.

Parameters:
USARTx,: where x can be 1, 2 or 3 to select the USART peripheral.
NewState,: new state of the NACK transmission. This parameter can be: ENABLE or DISABLE.
Note:
The Smart Card mode is not available for UART4 and UART5.
Return values:
None

Definition at line 705 of file stm32f10x_usart.c.

References assert_param, USART_TypeDef::CR3, CR3_NACK_Reset, CR3_NACK_Set, DISABLE, IS_FUNCTIONAL_STATE, and IS_USART_123_PERIPH.

Referenced by main().

void USART_StructInit ( USART_InitTypeDef * USART_InitStruct )

Fills each USART_InitStruct member with its default value.

Parameters:
USART_InitStruct,: pointer to a USART_InitTypeDef structure which will be initialized.
Return values:
None

Definition at line 281 of file stm32f10x_usart.c.

References USART_InitTypeDef::USART_BaudRate, USART_InitTypeDef::USART_HardwareFlowControl, USART_HardwareFlowControl_None, USART_InitTypeDef::USART_Mode, USART_Mode_Rx, USART_Mode_Tx, USART_InitTypeDef::USART_Parity, USART_Parity_No, USART_InitTypeDef::USART_StopBits, USART_StopBits_1, USART_InitTypeDef::USART_WordLength, and USART_WordLength_8b.

void USART_WakeUpConfig | ( | USART_TypeDef * | USARTx,
 |  | uint16_t | USART_WakeUp
 | ) |  |

Selects the USART WakeUp method.

Parameters:
USARTx,: Select the USART or the UART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
USART_WakeUp,: specifies the USART wakeup method. This parameter can be one of the following values:

  • USART_WakeUp_IdleLine: WakeUp by an idle line detection
  • USART_WakeUp_AddressMark: WakeUp by an address mark
Return values:
None

Definition at line 499 of file stm32f10x_usart.c.

References assert_param, USART_TypeDef::CR1, CR1_WAKE_Mask, IS_USART_ALL_PERIPH, and IS_USART_WAKEUP.

Referenced by main().


STM32F10x Standard Peripherals Firmware Library: USART_Private_TypesDefinitions

USART_Private_TypesDefinitions

USART


STM32F10x Standard Peripherals Firmware Library: USART_Private_Defines

Defines

USART_Private_Defines

USART

Defines

#define | CR1_CLEAR_Mask ((uint16_t)0xE9F3)
#define | CR1_OVER8_Reset ((u16)0x7FFF)
#define | CR1_OVER8_Set ((u16)0x8000)
#define | CR1_RWU_Reset ((uint16_t)0xFFFD)
#define | CR1_RWU_Set ((uint16_t)0x0002)
#define | CR1_SBK_Set ((uint16_t)0x0001)
#define | CR1_UE_Reset ((uint16_t)0xDFFF)
#define | CR1_UE_Set ((uint16_t)0x2000)
#define | CR1_WAKE_Mask ((uint16_t)0xF7FF)
#define | CR2_Address_Mask ((uint16_t)0xFFF0)
#define | CR2_CLOCK_CLEAR_Mask ((uint16_t)0xF0FF)
#define | CR2_LBDL_Mask ((uint16_t)0xFFDF)
#define | CR2_LINEN_Reset ((uint16_t)0xBFFF)
#define | CR2_LINEN_Set ((uint16_t)0x4000)
#define | CR2_STOP_CLEAR_Mask ((uint16_t)0xCFFF)
#define | CR3_CLEAR_Mask ((uint16_t)0xFCFF)
#define | CR3_HDSEL_Reset ((uint16_t)0xFFF7)
#define | CR3_HDSEL_Set ((uint16_t)0x0008)
#define | CR3_IREN_Reset ((uint16_t)0xFFFD)
#define | CR3_IREN_Set ((uint16_t)0x0002)
#define | CR3_IRLP_Mask ((uint16_t)0xFFFB)
#define | CR3_NACK_Reset ((uint16_t)0xFFEF)
#define | CR3_NACK_Set ((uint16_t)0x0010)
#define | CR3_ONEBITE_Reset ((u16)0xF7FF)
#define | CR3_ONEBITE_Set ((u16)0x0800)
#define | CR3_SCEN_Reset ((uint16_t)0xFFDF)
#define | CR3_SCEN_Set ((uint16_t)0x0020)
#define | GTPR_LSB_Mask ((uint16_t)0x00FF)
#define | GTPR_MSB_Mask ((uint16_t)0xFF00)
#define | IT_Mask ((uint16_t)0x001F)

Define Documentation

#define CR1_CLEAR_Mask ((uint16_t)0xE9F3)

USART CR1 Mask

Definition at line 55 of file stm32f10x_usart.c.

Referenced by USART_Init().

#define CR1_OVER8_Reset ((u16)0x7FFF)

Definition at line 85 of file stm32f10x_usart.c.

Referenced by USART_OverSampling8Cmd().

#define CR1_OVER8_Set ((u16)0x8000)

Definition at line 84 of file stm32f10x_usart.c.

Referenced by USART_Init(), and USART_OverSampling8Cmd().

#define CR1_RWU_Reset ((uint16_t)0xFFFD)

USART mute mode Enable Mask

Definition at line 53 of file stm32f10x_usart.c.

Referenced by USART_ReceiverWakeUpCmd().

#define CR1_RWU_Set ((uint16_t)0x0002)

USART mute mode Enable Mask

Definition at line 52 of file stm32f10x_usart.c.

Referenced by USART_ReceiverWakeUpCmd().

#define CR1_SBK_Set ((uint16_t)0x0001)

USART Break Character send Mask

Definition at line 54 of file stm32f10x_usart.c.

Referenced by USART_SendBreak().

#define CR1_UE_Reset ((uint16_t)0xDFFF)

USART Disable Mask

Definition at line 48 of file stm32f10x_usart.c.

Referenced by USART_Cmd().

#define CR1_UE_Set ((uint16_t)0x2000)

USART Enable Mask

Definition at line 47 of file stm32f10x_usart.c.

Referenced by USART_Cmd().

#define CR1_WAKE_Mask ((uint16_t)0xF7FF)

USART WakeUp Method Mask

Definition at line 50 of file stm32f10x_usart.c.

Referenced by USART_WakeUpConfig().

#define CR2_Address_Mask ((uint16_t)0xFFF0)

USART address Mask

Definition at line 56 of file stm32f10x_usart.c.

Referenced by USART_SetAddress().

#define CR2_CLOCK_CLEAR_Mask ((uint16_t)0xF0FF)

USART CR2 Clock Mask

Definition at line 63 of file stm32f10x_usart.c.

Referenced by USART_ClockInit().

#define CR2_LBDL_Mask ((uint16_t)0xFFDF)

USART LIN Break detection Mask

Definition at line 61 of file stm32f10x_usart.c.

Referenced by USART_LINBreakDetectLengthConfig().

#define CR2_LINEN_Reset ((uint16_t)0xBFFF)

USART LIN Disable Mask

Definition at line 59 of file stm32f10x_usart.c.

Referenced by USART_LINCmd().

#define CR2_LINEN_Set ((uint16_t)0x4000)

USART LIN Enable Mask

Definition at line 58 of file stm32f10x_usart.c.

Referenced by USART_LINCmd().

#define CR2_STOP_CLEAR_Mask ((uint16_t)0xCFFF)

USART CR2 STOP Bits Mask

Definition at line 62 of file stm32f10x_usart.c.

Referenced by USART_Init().

#define CR3_CLEAR_Mask ((uint16_t)0xFCFF)

USART CR3 Mask

Definition at line 75 of file stm32f10x_usart.c.

Referenced by USART_Init().

#define CR3_HDSEL_Reset ((uint16_t)0xFFF7)

USART Half-Duplex Disable Mask

Definition at line 72 of file stm32f10x_usart.c.

Referenced by USART_HalfDuplexCmd().

#define CR3_HDSEL_Set ((uint16_t)0x0008)

USART Half-Duplex Enable Mask

Definition at line 71 of file stm32f10x_usart.c.

Referenced by USART_HalfDuplexCmd().

#define CR3_IREN_Reset ((uint16_t)0xFFFD)

USART IrDA Disable Mask

Definition at line 78 of file stm32f10x_usart.c.

Referenced by USART_IrDACmd().

#define CR3_IREN_Set ((uint16_t)0x0002)

USART IrDA Enable Mask

Definition at line 77 of file stm32f10x_usart.c.

Referenced by USART_IrDACmd().

#define CR3_IRLP_Mask ((uint16_t)0xFFFB)

USART IrDA LowPower mode Mask

Definition at line 74 of file stm32f10x_usart.c.

Referenced by USART_IrDAConfig().

#define CR3_NACK_Reset ((uint16_t)0xFFEF)

USART SC NACK Disable Mask

Definition at line 69 of file stm32f10x_usart.c.

Referenced by USART_SmartCardNACKCmd().

#define CR3_NACK_Set ((uint16_t)0x0010)

USART SC NACK Enable Mask

Definition at line 68 of file stm32f10x_usart.c.

Referenced by USART_SmartCardNACKCmd().

#define CR3_ONEBITE_Reset ((u16)0xF7FF)

Definition at line 89 of file stm32f10x_usart.c.

Referenced by USART_OneBitMethodCmd().

#define CR3_ONEBITE_Set ((u16)0x0800)

Definition at line 88 of file stm32f10x_usart.c.

Referenced by USART_OneBitMethodCmd().

#define CR3_SCEN_Reset ((uint16_t)0xFFDF)

USART SC Disable Mask

Definition at line 66 of file stm32f10x_usart.c.

Referenced by USART_SmartCardCmd().

#define CR3_SCEN_Set ((uint16_t)0x0020)

USART SC Enable Mask

Definition at line 65 of file stm32f10x_usart.c.

Referenced by USART_SmartCardCmd().

#define GTPR_LSB_Mask ((uint16_t)0x00FF)

Guard Time Register LSB Mask

Definition at line 79 of file stm32f10x_usart.c.

Referenced by USART_SetGuardTime().

#define GTPR_MSB_Mask ((uint16_t)0xFF00)

Guard Time Register MSB Mask

Definition at line 80 of file stm32f10x_usart.c.

Referenced by USART_SetPrescaler().

#define IT_Mask ((uint16_t)0x001F)

USART Interrupt Mask

Definition at line 81 of file stm32f10x_usart.c.

Referenced by USART_GetITStatus(), and USART_ITConfig().


STM32F10x Standard Peripherals Firmware Library: USART_Private_Macros

USART_Private_Macros

USART


STM32F10x Standard Peripherals Firmware Library: USART_Private_Variables

USART_Private_Variables

USART


STM32F10x Standard Peripherals Firmware Library: USART_Private_FunctionPrototypes

USART_Private_FunctionPrototypes

USART


STM32F10x Standard Peripherals Firmware Library: USART_Private_Functions

Functions

USART_Private_Functions

USART

Functions

void | USART_ClearFlag (USART_TypeDef *USARTx, uint16_t USART_FLAG)
Clears the USARTx's pending flags.
void | USART_ClearITPendingBit (USART_TypeDef *USARTx, uint16_t USART_IT)
Clears the USARTx's interrupt pending bits.
void | USART_ClockInit (USART_TypeDef *USARTx, USART_ClockInitTypeDef *USART_ClockInitStruct)
Initializes the USARTx peripheral Clock according to the specified parameters in the USART_ClockInitStruct .
void | USART_ClockStructInit (USART_ClockInitTypeDef *USART_ClockInitStruct)
Fills each USART_ClockInitStruct member with its default value.
void | USART_Cmd (USART_TypeDef *USARTx, FunctionalState NewState)
Enables or disables the specified USART peripheral.
void | USART_DeInit (USART_TypeDef *USARTx)
Deinitializes the USARTx peripheral registers to their default reset values.
void | USART_DMACmd (USART_TypeDef *USARTx, uint16_t USART_DMAReq, FunctionalState NewState)
Enables or disables the USART’s DMA interface.
FlagStatus | USART_GetFlagStatus (USART_TypeDef *USARTx, uint16_t USART_FLAG)
Checks whether the specified USART flag is set or not.
ITStatus | USART_GetITStatus (USART_TypeDef *USARTx, uint16_t USART_IT)
Checks whether the specified USART interrupt has occurred or not.
void | USART_HalfDuplexCmd (USART_TypeDef *USARTx, FunctionalState NewState)
Enables or disables the USART’s Half Duplex communication.
void | USART_Init (USART_TypeDef *USARTx, USART_InitTypeDef *USART_InitStruct)
Initializes the USARTx peripheral according to the specified parameters in the USART_InitStruct .
void | USART_IrDACmd (USART_TypeDef *USARTx, FunctionalState NewState)
Enables or disables the USART's IrDA interface.
void | USART_IrDAConfig (USART_TypeDef *USARTx, uint16_t USART_IrDAMode)
Configures the USART's IrDA interface.
void | USART_ITConfig (USART_TypeDef *USARTx, uint16_t USART_IT, FunctionalState NewState)
Enables or disables the specified USART interrupts.
void | USART_LINBreakDetectLengthConfig (USART_TypeDef *USARTx, uint16_t USART_LINBreakDetectLength)
Sets the USART LIN Break detection length.
void | USART_LINCmd (USART_TypeDef *USARTx, FunctionalState NewState)
Enables or disables the USART’s LIN mode.
void | USART_OneBitMethodCmd (USART_TypeDef *USARTx, FunctionalState NewState)
Enables or disables the USART's one bit sampling method.
void | USART_OverSampling8Cmd (USART_TypeDef *USARTx, FunctionalState NewState)
Enables or disables the USART's 8x oversampling mode.
uint16_t | USART_ReceiveData (USART_TypeDef *USARTx)
Returns the most recent received data by the USARTx peripheral.
void | USART_ReceiverWakeUpCmd (USART_TypeDef *USARTx, FunctionalState NewState)
Determines if the USART is in mute mode or not.
void | USART_SendBreak (USART_TypeDef *USARTx)
Transmits break characters.
void | USART_SendData (USART_TypeDef *USARTx, uint16_t Data)
Transmits single data through the USARTx peripheral.
void | USART_SetAddress (USART_TypeDef *USARTx, uint8_t USART_Address)
Sets the address of the USART node.
void | USART_SetGuardTime (USART_TypeDef *USARTx, uint8_t USART_GuardTime)
Sets the specified USART guard time.
void | USART_SetPrescaler (USART_TypeDef *USARTx, uint8_t USART_Prescaler)
Sets the system clock prescaler.
void | USART_SmartCardCmd (USART_TypeDef *USARTx, FunctionalState NewState)
Enables or disables the USART’s Smart Card mode.
void | USART_SmartCardNACKCmd (USART_TypeDef *USARTx, FunctionalState NewState)
Enables or disables NACK transmission.
void | USART_StructInit (USART_InitTypeDef *USART_InitStruct)
Fills each USART_InitStruct member with its default value.
void | USART_WakeUpConfig (USART_TypeDef *USARTx, uint16_t USART_WakeUp)
Selects the USART WakeUp method.

Function Documentation

void USART_ClearFlag | ( | USART_TypeDef * | USARTx,
 |  | uint16_t | USART_FLAG
 | ) |  |

Clears the USARTx's pending flags.

Parameters:
USARTx,: Select the USART or the UART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
USART_FLAG,: specifies the flag to clear. This parameter can be any combination of the following values:

  • USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5).
  • USART_FLAG_LBD: LIN Break detection flag.
  • USART_FLAG_TC: Transmission Complete flag.
  • USART_FLAG_RXNE: Receive data register not empty flag.
Note:
  • PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun error) and IDLE (Idle line detected) flags are cleared by software sequence: a read operation to USART_SR register (USART_GetFlagStatus()) followed by a read operation to USART_DR register (USART_ReceiveData()).
  • RXNE flag can be also cleared by a read to the USART_DR register (USART_ReceiveData()).
  • TC flag can be also cleared by software sequence: a read operation to USART_SR register (USART_GetFlagStatus()) followed by a write operation to USART_DR register (USART_SendData()).
  • TXE flag is cleared only by a write to the USART_DR register (USART_SendData()).
Return values:
None

Definition at line 923 of file stm32f10x_usart.c.

References assert_param, IS_USART_123_PERIPH, IS_USART_ALL_PERIPH, IS_USART_CLEAR_FLAG, USART_TypeDef::SR, and USART_FLAG_CTS.

void USART_ClearITPendingBit | ( | USART_TypeDef * | USARTx,
 |  | uint16_t | USART_IT
 | ) |  |

Clears the USARTx's interrupt pending bits.

Parameters:
USARTx,: Select the USART or the UART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
USART_IT,: specifies the interrupt pending bit to clear. This parameter can be one of the following values:

  • USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
  • USART_IT_LBD: LIN Break detection interrupt
  • USART_IT_TC: Transmission complete interrupt.
  • USART_IT_RXNE: Receive Data register not empty interrupt.
Note:
  • PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun error) and IDLE (Idle line detected) pending bits are cleared by software sequence: a read operation to USART_SR register (USART_GetITStatus()) followed by a read operation to USART_DR register (USART_ReceiveData()).
  • RXNE pending bit can be also cleared by a read to the USART_DR register (USART_ReceiveData()).
  • TC pending bit can be also cleared by software sequence: a read operation to USART_SR register (USART_GetITStatus()) followed by a write operation to USART_DR register (USART_SendData()).
  • TXE pending bit is cleared only by a write to the USART_DR register (USART_SendData()).
Return values:
None

Definition at line 1030 of file stm32f10x_usart.c.

References assert_param, IS_USART_123_PERIPH, IS_USART_ALL_PERIPH, IS_USART_CLEAR_IT, USART_TypeDef::SR, and USART_IT_CTS.

void USART_ClockInit | ( | USART_TypeDef * | USARTx,
 |  | USART_ClockInitTypeDef * | USART_ClockInitStruct
 | ) |  |

Initializes the USARTx peripheral Clock according to the specified parameters in the USART_ClockInitStruct .

Parameters:
USARTx,: where x can be 1, 2, 3 to select the USART peripheral.
USART_ClockInitStruct,: pointer to a USART_ClockInitTypeDef structure that contains the configuration information for the specified USART peripheral.
Note:
The Smart Card and Synchronous modes are not available for UART4 and UART5.
Return values:
None

Definition at line 302 of file stm32f10x_usart.c.

References assert_param, USART_TypeDef::CR2, CR2_CLOCK_CLEAR_Mask, IS_USART_123_PERIPH, IS_USART_CLOCK, IS_USART_CPHA, IS_USART_CPOL, IS_USART_LASTBIT, USART_ClockInitTypeDef::USART_Clock, USART_ClockInitTypeDef::USART_CPHA, USART_ClockInitTypeDef::USART_CPOL, and USART_ClockInitTypeDef::USART_LastBit.

Referenced by main().

void USART_ClockStructInit ( USART_ClockInitTypeDef * USART_ClockInitStruct )

Fills each USART_ClockInitStruct member with its default value.

Parameters:
USART_ClockInitStruct,: pointer to a USART_ClockInitTypeDef structure which will be initialized.
Return values:
None

Definition at line 333 of file stm32f10x_usart.c.

References USART_ClockInitTypeDef::USART_Clock, USART_Clock_Disable, USART_ClockInitTypeDef::USART_CPHA, USART_CPHA_1Edge, USART_ClockInitTypeDef::USART_CPOL, USART_CPOL_Low, USART_ClockInitTypeDef::USART_LastBit, and USART_LastBit_Disable.

void USART_Cmd | ( | USART_TypeDef * | USARTx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified USART peripheral.

Parameters:
USARTx,: Select the USART or the UART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
NewState,: new state of the USARTx peripheral. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 351 of file stm32f10x_usart.c.

References assert_param, USART_TypeDef::CR1, CR1_UE_Reset, CR1_UE_Set, DISABLE, IS_FUNCTIONAL_STATE, and IS_USART_ALL_PERIPH.

Referenced by main(), and STM_EVAL_COMInit().

void USART_DeInit ( USART_TypeDef * USARTx )

Deinitializes the USARTx peripheral registers to their default reset values.

Parameters:
USARTx,: Select the USART or the UART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
Return values:
None

Definition at line 130 of file stm32f10x_usart.c.

References assert_param, DISABLE, ENABLE, IS_USART_ALL_PERIPH, RCC_APB1Periph_UART4, RCC_APB1Periph_UART5, RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1PeriphResetCmd(), RCC_APB2Periph_USART1, RCC_APB2PeriphResetCmd(), UART4, UART5, USART1, USART2, and USART3.

void USART_DMACmd | ( | USART_TypeDef * | USARTx,
 |  | uint16_t | USART_DMAReq,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the USART’s DMA interface.

Parameters:
USARTx,: Select the USART or the UART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
USART_DMAReq,: specifies the DMA request. This parameter can be any combination of the following values:

  • USART_DMAReq_Tx: USART DMA transmit request
  • USART_DMAReq_Rx: USART DMA receive request
NewState,: new state of the DMA Request sources. This parameter can be: ENABLE or DISABLE.
Note:
The DMA mode is not available for UART5 except in the STM32 High density value line devices(STM32F10X_HD_VL).
Return values:
None

Definition at line 448 of file stm32f10x_usart.c.

References assert_param, USART_TypeDef::CR3, DISABLE, IS_FUNCTIONAL_STATE, IS_USART_ALL_PERIPH, and IS_USART_DMAREQ.

Referenced by main().

FlagStatus USART_GetFlagStatus | ( | USART_TypeDef * | USARTx,
 |  | uint16_t | USART_FLAG
 | ) |  |

Checks whether the specified USART flag is set or not.

Parameters:
USARTx,: Select the USART or the UART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
USART_FLAG,: specifies the flag to check. This parameter can be one of the following values:

  • USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5)
  • USART_FLAG_LBD: LIN Break detection flag
  • USART_FLAG_TXE: Transmit data register empty flag
  • USART_FLAG_TC: Transmission Complete flag
  • USART_FLAG_RXNE: Receive data register not empty flag
  • USART_FLAG_IDLE: Idle Line detection flag
  • USART_FLAG_ORE: OverRun Error flag
  • USART_FLAG_NE: Noise Error flag
  • USART_FLAG_FE: Framing Error flag
  • USART_FLAG_PE: Parity Error flag
Return values:
The new state of USART_FLAG (SET or RESET).

Definition at line 874 of file stm32f10x_usart.c.

References assert_param, IS_USART_123_PERIPH, IS_USART_ALL_PERIPH, IS_USART_FLAG, RESET, SET, USART_TypeDef::SR, and USART_FLAG_CTS.

Referenced by EXTI0_IRQHandler(), and main().

ITStatus USART_GetITStatus | ( | USART_TypeDef * | USARTx,
 |  | uint16_t | USART_IT
 | ) |  |

Checks whether the specified USART interrupt has occurred or not.

Parameters:
USARTx,: Select the USART or the UART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
USART_IT,: specifies the USART interrupt source to check. This parameter can be one of the following values:

  • USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
  • USART_IT_LBD: LIN Break detection interrupt
  • USART_IT_TXE: Tansmit Data Register empty interrupt
  • USART_IT_TC: Transmission complete interrupt
  • USART_IT_RXNE: Receive Data register not empty interrupt
  • USART_IT_IDLE: Idle line detection interrupt
  • USART_IT_ORE: OverRun Error interrupt
  • USART_IT_NE: Noise Error interrupt
  • USART_IT_FE: Framing Error interrupt
  • USART_IT_PE: Parity Error interrupt
Return values:
The new state of USART_IT (SET or RESET).

Definition at line 956 of file stm32f10x_usart.c.

References assert_param, USART_TypeDef::CR1, USART_TypeDef::CR2, USART_TypeDef::CR3, IS_USART_123_PERIPH, IS_USART_ALL_PERIPH, IS_USART_GET_IT, IT_Mask, RESET, SET, USART_TypeDef::SR, and USART_IT_CTS.

Referenced by SC_USART_IRQHandler(), USART2_IRQHandler(), USART3_IRQHandler(), USARTx_IRQHandler(), USARTy_IRQHandler(), and USARTz_IRQHandler().

void USART_HalfDuplexCmd | ( | USART_TypeDef * | USARTx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the USART’s Half Duplex communication.

Parameters:
USARTx,: Select the USART or the UART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
NewState,: new state of the USART Communication. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 731 of file stm32f10x_usart.c.

References assert_param, USART_TypeDef::CR3, CR3_HDSEL_Reset, CR3_HDSEL_Set, DISABLE, IS_FUNCTIONAL_STATE, and IS_USART_ALL_PERIPH.

Referenced by main().

void USART_Init | ( | USART_TypeDef * | USARTx,
 |  | USART_InitTypeDef * | USART_InitStruct
 | ) |  |

Initializes the USARTx peripheral according to the specified parameters in the USART_InitStruct .

Parameters:
USARTx,: Select the USART or the UART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
USART_InitStruct,: pointer to a USART_InitTypeDef structure that contains the configuration information for the specified USART peripheral.
Return values:
None

Definition at line 176 of file stm32f10x_usart.c.

References assert_param, USART_TypeDef::BRR, USART_TypeDef::CR1, CR1_CLEAR_Mask, CR1_OVER8_Set, USART_TypeDef::CR2, CR2_STOP_CLEAR_Mask, USART_TypeDef::CR3, CR3_CLEAR_Mask, IS_USART_123_PERIPH, IS_USART_ALL_PERIPH, IS_USART_BAUDRATE, IS_USART_HARDWARE_FLOW_CONTROL, IS_USART_MODE, IS_USART_PARITY, IS_USART_STOPBITS, IS_USART_WORD_LENGTH, RCC_ClocksTypeDef::PCLK1_Frequency, RCC_ClocksTypeDef::PCLK2_Frequency, RCC_GetClocksFreq(), USART1_BASE, USART_InitTypeDef::USART_BaudRate, USART_InitTypeDef::USART_HardwareFlowControl, USART_HardwareFlowControl_None, USART_InitTypeDef::USART_Mode, USART_InitTypeDef::USART_Parity, USART_InitTypeDef::USART_StopBits, and USART_InitTypeDef::USART_WordLength.

Referenced by main(), and STM_EVAL_COMInit().

void USART_IrDACmd | ( | USART_TypeDef * | USARTx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the USART's IrDA interface.

Parameters:
USARTx,: Select the USART or the UART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
NewState,: new state of the IrDA mode. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 837 of file stm32f10x_usart.c.

References assert_param, USART_TypeDef::CR3, CR3_IREN_Reset, CR3_IREN_Set, DISABLE, IS_FUNCTIONAL_STATE, and IS_USART_ALL_PERIPH.

Referenced by main().

void USART_IrDAConfig | ( | USART_TypeDef * | USARTx,
 |  | uint16_t | USART_IrDAMode
 | ) |  |

Configures the USART's IrDA interface.

Parameters:
USARTx,: Select the USART or the UART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
USART_IrDAMode,: specifies the IrDA mode. This parameter can be one of the following values:

  • USART_IrDAMode_LowPower
  • USART_IrDAMode_Normal
Return values:
None

Definition at line 818 of file stm32f10x_usart.c.

References assert_param, USART_TypeDef::CR3, CR3_IRLP_Mask, IS_USART_ALL_PERIPH, and IS_USART_IRDA_MODE.

Referenced by main().

void USART_ITConfig | ( | USART_TypeDef * | USARTx,
 |  | uint16_t | USART_IT,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the specified USART interrupts.

Parameters:
USARTx,: Select the USART or the UART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
USART_IT,: specifies the USART interrupt sources to be enabled or disabled. This parameter can be one of the following values:

  • USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
  • USART_IT_LBD: LIN Break detection interrupt
  • USART_IT_TXE: Transmit Data Register empty interrupt
  • USART_IT_TC: Transmission complete interrupt
  • USART_IT_RXNE: Receive Data register not empty interrupt
  • USART_IT_IDLE: Idle line detection interrupt
  • USART_IT_PE: Parity Error interrupt
  • USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
NewState,: new state of the specified USARTx interrupts. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 388 of file stm32f10x_usart.c.

References assert_param, DISABLE, IS_FUNCTIONAL_STATE, IS_USART_123_PERIPH, IS_USART_ALL_PERIPH, IS_USART_CONFIG_IT, IT_Mask, and USART_IT_CTS.

Referenced by main(), SC_USART_IRQHandler(), USART2_IRQHandler(), USART3_IRQHandler(), USARTx_IRQHandler(), USARTy_IRQHandler(), and USARTz_IRQHandler().

void USART_LINBreakDetectLengthConfig | ( | USART_TypeDef * | USARTx,
 |  | uint16_t | USART_LINBreakDetectLength
 | ) |  |

Sets the USART LIN Break detection length.

Parameters:
USARTx,: Select the USART or the UART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
USART_LINBreakDetectLength,: specifies the LIN break detection length. This parameter can be one of the following values:

  • USART_LINBreakDetectLength_10b: 10-bit break detection
  • USART_LINBreakDetectLength_11b: 11-bit break detection
Return values:
None

Definition at line 547 of file stm32f10x_usart.c.

References assert_param, USART_TypeDef::CR2, CR2_LBDL_Mask, IS_USART_ALL_PERIPH, and IS_USART_LIN_BREAK_DETECT_LENGTH.

void USART_LINCmd | ( | USART_TypeDef * | USARTx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the USART’s LIN mode.

Parameters:
USARTx,: Select the USART or the UART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
NewState,: new state of the USART LIN mode. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 566 of file stm32f10x_usart.c.

References assert_param, USART_TypeDef::CR2, CR2_LINEN_Reset, CR2_LINEN_Set, DISABLE, IS_FUNCTIONAL_STATE, and IS_USART_ALL_PERIPH.

void USART_OneBitMethodCmd | ( | USART_TypeDef * | USARTx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the USART's one bit sampling method.

Parameters:
USARTx,: Select the USART or the UART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
NewState,: new state of the USART one bit sampling method. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 789 of file stm32f10x_usart.c.

References assert_param, USART_TypeDef::CR3, CR3_ONEBITE_Reset, CR3_ONEBITE_Set, DISABLE, IS_FUNCTIONAL_STATE, and IS_USART_ALL_PERIPH.

void USART_OverSampling8Cmd | ( | USART_TypeDef * | USARTx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the USART's 8x oversampling mode.

Parameters:
USARTx,: Select the USART or the UART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
NewState,: new state of the USART one bit sampling method. This parameter can be: ENABLE or DISABLE.
Note:
This function has to be called before calling USART_Init() function in order to have correct baudrate Divider value.
Return values:
None

Definition at line 762 of file stm32f10x_usart.c.

References assert_param, USART_TypeDef::CR1, CR1_OVER8_Reset, CR1_OVER8_Set, DISABLE, IS_FUNCTIONAL_STATE, and IS_USART_ALL_PERIPH.

uint16_t USART_ReceiveData ( USART_TypeDef * USARTx )

Returns the most recent received data by the USARTx peripheral.

Parameters:
USARTx,: Select the USART or the UART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
Return values:
The received data.

Definition at line 609 of file stm32f10x_usart.c.

References assert_param, USART_TypeDef::DR, and IS_USART_ALL_PERIPH.

Referenced by EXTI9_5_IRQHandler(), main(), SC_USART_IRQHandler(), USART2_IRQHandler(), USART3_IRQHandler(), USARTx_IRQHandler(), USARTy_IRQHandler(), and USARTz_IRQHandler().

void USART_ReceiverWakeUpCmd | ( | USART_TypeDef * | USARTx,
 |  | FunctionalState | NewState
 | ) |  |

Determines if the USART is in mute mode or not.

Parameters:
USARTx,: Select the USART or the UART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
NewState,: new state of the USART mute mode. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 518 of file stm32f10x_usart.c.

References assert_param, USART_TypeDef::CR1, CR1_RWU_Reset, CR1_RWU_Set, DISABLE, IS_FUNCTIONAL_STATE, and IS_USART_ALL_PERIPH.

Referenced by EXTI9_5_IRQHandler().

void USART_SendBreak ( USART_TypeDef * USARTx )

Transmits break characters.

Parameters:
USARTx,: Select the USART or the UART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
Return values:
None

Definition at line 625 of file stm32f10x_usart.c.

References assert_param, USART_TypeDef::CR1, CR1_SBK_Set, and IS_USART_ALL_PERIPH.

void USART_SendData | ( | USART_TypeDef * | USARTx,
 |  | uint16_t | Data
 | ) |  |

Transmits single data through the USARTx peripheral.

Parameters:
USARTx,: Select the USART or the UART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
Data,: the data to transmit.
Return values:
None

Definition at line 592 of file stm32f10x_usart.c.

References assert_param, USART_TypeDef::DR, IS_USART_ALL_PERIPH, and IS_USART_DATA.

Referenced by EXTI0_IRQHandler(), main(), USARTx_IRQHandler(), USARTy_IRQHandler(), and USARTz_IRQHandler().

void USART_SetAddress | ( | USART_TypeDef * | USARTx,
 |  | uint8_t | USART_Address
 | ) |  |

Sets the address of the USART node.

Parameters:
USARTx,: Select the USART or the UART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
USART_Address,: Indicates the address of the USART node.
Return values:
None

Definition at line 476 of file stm32f10x_usart.c.

References assert_param, USART_TypeDef::CR2, CR2_Address_Mask, IS_USART_ADDRESS, and IS_USART_ALL_PERIPH.

Referenced by main().

void USART_SetGuardTime | ( | USART_TypeDef * | USARTx,
 |  | uint8_t | USART_GuardTime
 | ) |  |

Sets the specified USART guard time.

Parameters:
USARTx,: where x can be 1, 2 or 3 to select the USART peripheral.
USART_GuardTime,: specifies the guard time.
Note:
The guard time bits are not available for UART4 and UART5.
Return values:
None

Definition at line 641 of file stm32f10x_usart.c.

References assert_param, USART_TypeDef::GTPR, GTPR_LSB_Mask, and IS_USART_123_PERIPH.

Referenced by main().

void USART_SetPrescaler | ( | USART_TypeDef * | USARTx,
 |  | uint8_t | USART_Prescaler
 | ) |  |

Sets the system clock prescaler.

Parameters:
USARTx,: Select the USART or the UART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
USART_Prescaler,: specifies the prescaler clock.
Note:
The function is used for IrDA mode with UART4 and UART5.
Return values:
None

Definition at line 661 of file stm32f10x_usart.c.

References assert_param, USART_TypeDef::GTPR, GTPR_MSB_Mask, and IS_USART_ALL_PERIPH.

Referenced by main().

void USART_SmartCardCmd | ( | USART_TypeDef * | USARTx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the USART’s Smart Card mode.

Parameters:
USARTx,: where x can be 1, 2 or 3 to select the USART peripheral.
NewState,: new state of the Smart Card mode. This parameter can be: ENABLE or DISABLE.
Note:
The Smart Card mode is not available for UART4 and UART5.
Return values:
None

Definition at line 680 of file stm32f10x_usart.c.

References assert_param, USART_TypeDef::CR3, CR3_SCEN_Reset, CR3_SCEN_Set, DISABLE, IS_FUNCTIONAL_STATE, and IS_USART_123_PERIPH.

Referenced by main().

void USART_SmartCardNACKCmd | ( | USART_TypeDef * | USARTx,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables NACK transmission.

Parameters:
USARTx,: where x can be 1, 2 or 3 to select the USART peripheral.
NewState,: new state of the NACK transmission. This parameter can be: ENABLE or DISABLE.
Note:
The Smart Card mode is not available for UART4 and UART5.
Return values:
None

Definition at line 705 of file stm32f10x_usart.c.

References assert_param, USART_TypeDef::CR3, CR3_NACK_Reset, CR3_NACK_Set, DISABLE, IS_FUNCTIONAL_STATE, and IS_USART_123_PERIPH.

Referenced by main().

void USART_StructInit ( USART_InitTypeDef * USART_InitStruct )

Fills each USART_InitStruct member with its default value.

Parameters:
USART_InitStruct,: pointer to a USART_InitTypeDef structure which will be initialized.
Return values:
None

Definition at line 281 of file stm32f10x_usart.c.

References USART_InitTypeDef::USART_BaudRate, USART_InitTypeDef::USART_HardwareFlowControl, USART_HardwareFlowControl_None, USART_InitTypeDef::USART_Mode, USART_Mode_Rx, USART_Mode_Tx, USART_InitTypeDef::USART_Parity, USART_Parity_No, USART_InitTypeDef::USART_StopBits, USART_StopBits_1, USART_InitTypeDef::USART_WordLength, and USART_WordLength_8b.

void USART_WakeUpConfig | ( | USART_TypeDef * | USARTx,
 |  | uint16_t | USART_WakeUp
 | ) |  |

Selects the USART WakeUp method.

Parameters:
USARTx,: Select the USART or the UART peripheral. This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
USART_WakeUp,: specifies the USART wakeup method. This parameter can be one of the following values:

  • USART_WakeUp_IdleLine: WakeUp by an idle line detection
  • USART_WakeUp_AddressMark: WakeUp by an address mark
Return values:
None

Definition at line 499 of file stm32f10x_usart.c.

References assert_param, USART_TypeDef::CR1, CR1_WAKE_Mask, IS_USART_ALL_PERIPH, and IS_USART_WAKEUP.

Referenced by main().


STM32F10x Standard Peripherals Firmware Library: WWDG_Exported_Types

WWDG_Exported_Types

WWDG


STM32F10x Standard Peripherals Firmware Library: WWDG_Prescaler

Defines

WWDG_Prescaler

WWDG_Exported_Constants

Defines

#define | IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F))
#define | IS_WWDG_PRESCALER(PRESCALER)
#define | IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F)
#define | WWDG_Prescaler_1 ((uint32_t)0x00000000)
#define | WWDG_Prescaler_2 ((uint32_t)0x00000080)
#define | WWDG_Prescaler_4 ((uint32_t)0x00000100)
#define | WWDG_Prescaler_8 ((uint32_t)0x00000180)

Define Documentation

#define IS_WWDG_COUNTER ( COUNTER ) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F))

Definition at line 67 of file stm32f10x_wwdg.h.

Referenced by WWDG_Enable(), and WWDG_SetCounter().

#define IS_WWDG_PRESCALER ( PRESCALER )
Value:
(((PRESCALER) == WWDG_Prescaler_1) || \
                                      ((PRESCALER) == WWDG_Prescaler_2) || \
                                      ((PRESCALER) == WWDG_Prescaler_4) || \
                                      ((PRESCALER) == WWDG_Prescaler_8))

Definition at line 62 of file stm32f10x_wwdg.h.

Referenced by WWDG_SetPrescaler().

#define IS_WWDG_WINDOW_VALUE ( VALUE ) ((VALUE) <= 0x7F)

Definition at line 66 of file stm32f10x_wwdg.h.

Referenced by WWDG_SetWindowValue().

#define WWDG_Prescaler_1 ((uint32_t)0x00000000)

Definition at line 58 of file stm32f10x_wwdg.h.

#define WWDG_Prescaler_2 ((uint32_t)0x00000080)

Definition at line 59 of file stm32f10x_wwdg.h.

#define WWDG_Prescaler_4 ((uint32_t)0x00000100)

Definition at line 60 of file stm32f10x_wwdg.h.

#define WWDG_Prescaler_8 ((uint32_t)0x00000180)

Definition at line 61 of file stm32f10x_wwdg.h.

Referenced by main().


STM32F10x Standard Peripherals Firmware Library: WWDG_Exported_Macros

WWDG_Exported_Macros

WWDG


STM32F10x Standard Peripherals Firmware Library: WWDG_Exported_Functions

Functions

WWDG_Exported_Functions

WWDG

Functions

void | WWDG_ClearFlag (void)
Clears Early Wakeup interrupt flag.
void | WWDG_DeInit (void)
Deinitializes the WWDG peripheral registers to their default reset values.
void | WWDG_Enable (uint8_t Counter)
Enables WWDG and load the counter value.
void | WWDG_EnableIT (void)
Enables the WWDG Early Wakeup interrupt(EWI).
FlagStatus | WWDG_GetFlagStatus (void)
Checks whether the Early Wakeup interrupt flag is set or not.
void | WWDG_SetCounter (uint8_t Counter)
Sets the WWDG counter value.
void | WWDG_SetPrescaler (uint32_t WWDG_Prescaler)
Sets the WWDG Prescaler.
void | WWDG_SetWindowValue (uint8_t WindowValue)
Sets the WWDG window value.

Function Documentation

void WWDG_ClearFlag ( void )

Clears Early Wakeup interrupt flag.

Parameters:
None
Return values:
None

Definition at line 207 of file stm32f10x_wwdg.c.

References RESET, and WWDG.

void WWDG_DeInit ( void )

Deinitializes the WWDG peripheral registers to their default reset values.

Parameters:
None
Return values:
None

Definition at line 102 of file stm32f10x_wwdg.c.

References DISABLE, ENABLE, RCC_APB1Periph_WWDG, and RCC_APB1PeriphResetCmd().

void WWDG_Enable ( uint8_t Counter )

Enables WWDG and load the counter value.

Parameters:
Counter,: specifies the watchdog counter value. This parameter must be a number between 0x40 and 0x7F.
Return values:
None

Definition at line 185 of file stm32f10x_wwdg.c.

References assert_param, Counter, CR_WDGA_Set, IS_WWDG_COUNTER, and WWDG.

Referenced by main().

void WWDG_EnableIT ( void )

Enables the WWDG Early Wakeup interrupt(EWI).

Parameters:
None
Return values:
None

Definition at line 159 of file stm32f10x_wwdg.c.

References CFR_EWI_BB, and ENABLE.

FlagStatus WWDG_GetFlagStatus ( void )

Checks whether the Early Wakeup interrupt flag is set or not.

Parameters:
None
Return values:
The new state of the Early Wakeup interrupt flag (SET or RESET)

Definition at line 197 of file stm32f10x_wwdg.c.

References WWDG.

void WWDG_SetCounter ( uint8_t Counter )

Sets the WWDG counter value.

Parameters:
Counter,: specifies the watchdog counter value. This parameter must be a number between 0x40 and 0x7F.
Return values:
None

Definition at line 170 of file stm32f10x_wwdg.c.

References assert_param, BIT_Mask, IS_WWDG_COUNTER, and WWDG.

Referenced by main().

void WWDG_SetPrescaler ( uint32_t WWDG_Prescaler )

Sets the WWDG Prescaler.

Parameters:
WWDG_Prescaler,: specifies the WWDG Prescaler. This parameter can be one of the following values:

  • WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1
  • WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2
  • WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4
  • WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8
Return values:
None

Definition at line 118 of file stm32f10x_wwdg.c.

References assert_param, CFR_WDGTB_Mask, IS_WWDG_PRESCALER, and WWDG.

Referenced by main().

void WWDG_SetWindowValue ( uint8_t WindowValue )

Sets the WWDG window value.

Parameters:
WindowValue,: specifies the window value to be compared to the downcounter. This parameter value must be lower than 0x80.
Return values:
None

Definition at line 137 of file stm32f10x_wwdg.c.

References assert_param, BIT_Mask, CFR_W_Mask, IS_WWDG_WINDOW_VALUE, and WWDG.

Referenced by main().


STM32F10x Standard Peripherals Firmware Library: WWDG_Private_TypesDefinitions

WWDG_Private_TypesDefinitions

WWDG


STM32F10x Standard Peripherals Firmware Library: WWDG_Private_Defines

Defines

WWDG_Private_Defines

WWDG

Defines

#define | BIT_Mask ((uint8_t)0x7F)
#define | CFR_EWI_BB (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4))
#define | CFR_OFFSET (WWDG_OFFSET + 0x04)
#define | CFR_W_Mask ((uint32_t)0xFFFFFF80)
#define | CFR_WDGTB_Mask ((uint32_t)0xFFFFFE7F)
#define | CR_WDGA_Set ((uint32_t)0x00000080)
#define | EWI_BitNumber 0x09
#define | WWDG_OFFSET (WWDG_BASE - PERIPH_BASE)

Define Documentation

#define BIT_Mask ((uint8_t)0x7F)

Definition at line 63 of file stm32f10x_wwdg.c.

Referenced by WWDG_SetCounter(), and WWDG_SetWindowValue().

#define CFR_EWI_BB (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4))

Definition at line 53 of file stm32f10x_wwdg.c.

Referenced by WWDG_EnableIT().

#define CFR_OFFSET (WWDG_OFFSET + 0x04)

Definition at line 51 of file stm32f10x_wwdg.c.

#define CFR_W_Mask ((uint32_t)0xFFFFFF80)

Definition at line 62 of file stm32f10x_wwdg.c.

Referenced by WWDG_SetWindowValue().

#define CFR_WDGTB_Mask ((uint32_t)0xFFFFFE7F)

Definition at line 61 of file stm32f10x_wwdg.c.

Referenced by WWDG_SetPrescaler().

#define CR_WDGA_Set ((uint32_t)0x00000080)

Definition at line 58 of file stm32f10x_wwdg.c.

Referenced by WWDG_Enable().

#define EWI_BitNumber 0x09

Definition at line 52 of file stm32f10x_wwdg.c.

#define WWDG_OFFSET (WWDG_BASE - PERIPH_BASE)

Definition at line 48 of file stm32f10x_wwdg.c.


STM32F10x Standard Peripherals Firmware Library: WWDG_Private_Macros

WWDG_Private_Macros

WWDG


STM32F10x Standard Peripherals Firmware Library: WWDG_Private_Variables

WWDG_Private_Variables

WWDG


STM32F10x Standard Peripherals Firmware Library: WWDG_Private_FunctionPrototypes

WWDG_Private_FunctionPrototypes

WWDG


STM32F10x Standard Peripherals Firmware Library: WWDG_Private_Functions

Functions

WWDG_Private_Functions

WWDG

Functions

void | WWDG_ClearFlag (void)
Clears Early Wakeup interrupt flag.
void | WWDG_DeInit (void)
Deinitializes the WWDG peripheral registers to their default reset values.
void | WWDG_Enable (uint8_t Counter)
Enables WWDG and load the counter value.
void | WWDG_EnableIT (void)
Enables the WWDG Early Wakeup interrupt(EWI).
FlagStatus | WWDG_GetFlagStatus (void)
Checks whether the Early Wakeup interrupt flag is set or not.
void | WWDG_SetCounter (uint8_t Counter)
Sets the WWDG counter value.
void | WWDG_SetPrescaler (uint32_t WWDG_Prescaler)
Sets the WWDG Prescaler.
void | WWDG_SetWindowValue (uint8_t WindowValue)
Sets the WWDG window value.

Function Documentation

void WWDG_ClearFlag ( void )

Clears Early Wakeup interrupt flag.

Parameters:
None
Return values:
None

Definition at line 207 of file stm32f10x_wwdg.c.

References RESET, and WWDG.

void WWDG_DeInit ( void )

Deinitializes the WWDG peripheral registers to their default reset values.

Parameters:
None
Return values:
None

Definition at line 102 of file stm32f10x_wwdg.c.

References DISABLE, ENABLE, RCC_APB1Periph_WWDG, and RCC_APB1PeriphResetCmd().

void WWDG_Enable ( uint8_t Counter )

Enables WWDG and load the counter value.

Parameters:
Counter,: specifies the watchdog counter value. This parameter must be a number between 0x40 and 0x7F.
Return values:
None

Definition at line 185 of file stm32f10x_wwdg.c.

References assert_param, Counter, CR_WDGA_Set, IS_WWDG_COUNTER, and WWDG.

Referenced by main().

void WWDG_EnableIT ( void )

Enables the WWDG Early Wakeup interrupt(EWI).

Parameters:
None
Return values:
None

Definition at line 159 of file stm32f10x_wwdg.c.

References CFR_EWI_BB, and ENABLE.

FlagStatus WWDG_GetFlagStatus ( void )

Checks whether the Early Wakeup interrupt flag is set or not.

Parameters:
None
Return values:
The new state of the Early Wakeup interrupt flag (SET or RESET)

Definition at line 197 of file stm32f10x_wwdg.c.

References WWDG.

void WWDG_SetCounter ( uint8_t Counter )

Sets the WWDG counter value.

Parameters:
Counter,: specifies the watchdog counter value. This parameter must be a number between 0x40 and 0x7F.
Return values:
None

Definition at line 170 of file stm32f10x_wwdg.c.

References assert_param, BIT_Mask, IS_WWDG_COUNTER, and WWDG.

Referenced by main().

void WWDG_SetPrescaler ( uint32_t WWDG_Prescaler )

Sets the WWDG Prescaler.

Parameters:
WWDG_Prescaler,: specifies the WWDG Prescaler. This parameter can be one of the following values:

  • WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1
  • WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2
  • WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4
  • WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8
Return values:
None

Definition at line 118 of file stm32f10x_wwdg.c.

References assert_param, CFR_WDGTB_Mask, IS_WWDG_PRESCALER, and WWDG.

Referenced by main().

void WWDG_SetWindowValue ( uint8_t WindowValue )

Sets the WWDG window value.

Parameters:
WindowValue,: specifies the window value to be compared to the downcounter. This parameter value must be lower than 0x80.
Return values:
None

Definition at line 137 of file stm32f10x_wwdg.c.

References assert_param, BIT_Mask, CFR_W_Mask, IS_WWDG_WINDOW_VALUE, and WWDG.

Referenced by main().


STM32F10x Standard Peripherals Firmware Library: ADC_3ADCs_DMA

Defines | Functions | Variables

ADC_3ADCs_DMA

STM32F10x_StdPeriph_Examples

Defines

#define | ADC1_DR_Address ((uint32_t)0x4001244C)
#define | ADC3_DR_Address ((uint32_t)0x40013C4C)

Functions

void | ADC1_2_IRQHandler (void)
This function handles ADC1 and ADC2 global interrupts requests.
void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

__IO uint16_t | ADC1ConvertedValue = 0
__IO uint16_t | ADC2ConvertedValue
__IO uint16_t | ADC3ConvertedValue = 0
ADC_InitTypeDef ADC_InitStructure
DMA_InitTypeDef DMA_InitStructure

Define Documentation

#define ADC1_DR_Address ((uint32_t)0x4001244C)

Definition at line 35 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

Referenced by main().

#define ADC3_DR_Address ((uint32_t)0x40013C4C)

Definition at line 36 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

Referenced by main().

Function Documentation

void ADC1_2_IRQHandler ( void )

This function handles ADC1 and ADC2 global interrupts requests.

Parameters:
None
Return values:
None

Definition at line 154 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_it.c.

void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 88 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 123 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_it.c.

void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 62 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 56 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

References ADC1, ADC1_DR_Address, ADC1ConvertedValue, ADC2, ADC3, ADC3_DR_Address, ADC3ConvertedValue, ADC_Channel_12, ADC_Channel_13, ADC_Channel_14, ADC_Cmd(), ADC_InitTypeDef::ADC_ContinuousConvMode, ADC_InitTypeDef::ADC_DataAlign, ADC_DataAlign_Right, ADC_DMACmd(), ADC_InitTypeDef::ADC_ExternalTrigConv, ADC_ExternalTrigConv_None, ADC_GetCalibrationStatus(), ADC_GetResetCalibrationStatus(), ADC_Init(), ADC_IT_EOC, ADC_ITConfig(), ADC_InitTypeDef::ADC_Mode, ADC_Mode_Independent, ADC_InitTypeDef::ADC_NbrOfChannel, ADC_RegularChannelConfig(), ADC_ResetCalibration(), ADC_SampleTime_28Cycles5, ADC_InitTypeDef::ADC_ScanConvMode, ADC_SoftwareStartConvCmd(), ADC_StartCalibration(), DISABLE, DMA1_Channel1, DMA2_Channel5, DMA_InitTypeDef::DMA_BufferSize, DMA_Cmd(), DMA_DeInit(), DMA_InitTypeDef::DMA_DIR, DMA_DIR_PeripheralSRC, DMA_Init(), DMA_InitTypeDef::DMA_M2M, DMA_M2M_Disable, DMA_InitTypeDef::DMA_MemoryBaseAddr, DMA_InitTypeDef::DMA_MemoryDataSize, DMA_MemoryDataSize_HalfWord, DMA_InitTypeDef::DMA_MemoryInc, DMA_MemoryInc_Disable, DMA_InitTypeDef::DMA_Mode, DMA_Mode_Circular, DMA_InitTypeDef::DMA_PeripheralBaseAddr, DMA_InitTypeDef::DMA_PeripheralDataSize, DMA_PeripheralDataSize_HalfWord, DMA_InitTypeDef::DMA_PeripheralInc, DMA_PeripheralInc_Disable, DMA_InitTypeDef::DMA_Priority, DMA_Priority_High, ENABLE, GPIO_Configuration(), NVIC_Configuration(), and RCC_Configuration().

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 75 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 53 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_it.c.

void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 132 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_it.c.

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 114 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 141 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_it.c.

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 101 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_it.c.

Variable Documentation

__IO uint16_t ADC1ConvertedValue = 0

Definition at line 42 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

Referenced by main().

__IO uint16_t ADC2ConvertedValue

Definition at line 39 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_it.c.

Referenced by ADC1_2_IRQHandler().

__IO uint16_t ADC3ConvertedValue = 0

Definition at line 42 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

Referenced by main().

ADC_InitTypeDef ADC_InitStructure

Definition at line 40 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

DMA_InitTypeDef DMA_InitStructure

Definition at line 41 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

Referenced by DMA_Configuration(), IOE_DMA_Config(), LM75_DMA_Config(), SD_LowLevel_DMA_RxConfig(), and SD_LowLevel_DMA_TxConfig().


STM32F10x Standard Peripherals Firmware Library: ADC_ADC1_DMA

Defines | Functions | Variables

ADC_ADC1_DMA

STM32F10x_StdPeriph_Examples

Defines

#define | ADC1_DR_Address ((uint32_t)0x4001244C)

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | GPIO_Configuration (void)
Configures the different GPIO ports.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | RCC_Configuration (void)
Configures the different system clocks.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

ADC_InitTypeDef ADC_InitStructure
__IO uint16_t | ADCConvertedValue
DMA_InitTypeDef DMA_InitStructure

Define Documentation

#define ADC1_DR_Address ((uint32_t)0x4001244C)

Definition at line 36 of file STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/main.c.

Referenced by main().

Function Documentation

void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 86 of file STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 121 of file STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/stm32f10x_it.c.

void GPIO_Configuration ( void )

Configures the different GPIO ports.

Parameters:
None
Return values:
None

Definition at line 222 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 60 of file STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 55 of file STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/main.c.

References ADC1, ADC1_DR_Address, ADC_Channel_14, ADC_Cmd(), ADC_InitTypeDef::ADC_ContinuousConvMode, ADC_InitTypeDef::ADC_DataAlign, ADC_DataAlign_Right, ADC_DMACmd(), ADC_InitTypeDef::ADC_ExternalTrigConv, ADC_ExternalTrigConv_None, ADC_GetCalibrationStatus(), ADC_GetResetCalibrationStatus(), ADC_Init(), ADC_InitTypeDef::ADC_Mode, ADC_Mode_Independent, ADC_InitTypeDef::ADC_NbrOfChannel, ADC_RegularChannelConfig(), ADC_ResetCalibration(), ADC_SampleTime_55Cycles5, ADC_InitTypeDef::ADC_ScanConvMode, ADC_SoftwareStartConvCmd(), ADC_StartCalibration(), ADCConvertedValue, DMA1_Channel1, DMA_InitTypeDef::DMA_BufferSize, DMA_Cmd(), DMA_DeInit(), DMA_InitTypeDef::DMA_DIR, DMA_DIR_PeripheralSRC, DMA_Init(), DMA_InitTypeDef::DMA_M2M, DMA_M2M_Disable, DMA_InitTypeDef::DMA_MemoryBaseAddr, DMA_InitTypeDef::DMA_MemoryDataSize, DMA_MemoryDataSize_HalfWord, DMA_InitTypeDef::DMA_MemoryInc, DMA_MemoryInc_Disable, DMA_InitTypeDef::DMA_Mode, DMA_Mode_Circular, DMA_InitTypeDef::DMA_PeripheralBaseAddr, DMA_InitTypeDef::DMA_PeripheralDataSize, DMA_PeripheralDataSize_HalfWord, DMA_InitTypeDef::DMA_PeripheralInc, DMA_PeripheralInc_Disable, DMA_InitTypeDef::DMA_Priority, DMA_Priority_High, ENABLE, GPIO_Configuration(), and RCC_Configuration().

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 73 of file STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 51 of file STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/stm32f10x_it.c.

void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 130 of file STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/stm32f10x_it.c.

void RCC_Configuration ( void )

Configures the different system clocks.

Parameters:
None
Return values:
None

Definition at line 203 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 112 of file STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 139 of file STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/stm32f10x_it.c.

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 99 of file STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/stm32f10x_it.c.

Variable Documentation

ADC_InitTypeDef ADC_InitStructure

Definition at line 40 of file STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/main.c.

__IO uint16_t ADCConvertedValue

Definition at line 42 of file STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/main.c.

Referenced by main().

DMA_InitTypeDef DMA_InitStructure

Definition at line 41 of file STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/main.c.


STM32F10x Standard Peripherals Firmware Library: ADC_AnalogWatchdog

Functions | Variables

ADC_AnalogWatchdog

STM32F10x_StdPeriph_Examples

Functions

void | ADC1_2_IRQHandler (void)
This function handles ADC1 and ADC2 global interrupts requests.
void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | GPIO_Configuration (void)
Configures the different GPIO ports.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | NVIC_Configuration (void)
Configures NVIC and Vector Table base location.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | RCC_Configuration (void)
Configures the different system clocks.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

ADC_InitTypeDef ADC_InitStructure

Function Documentation

void ADC1_2_IRQHandler ( void )

This function handles ADC1 and ADC2 global interrupts requests.

Parameters:
None
Return values:
None

Definition at line 156 of file STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/stm32f10x_it.c.

References ADC1, ADC_ClearITPendingBit(), ADC_IT_AWD, LED1, STM_EVAL_LEDOff(), and STM_EVAL_LEDOn().

void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 87 of file STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 122 of file STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/stm32f10x_it.c.

void GPIO_Configuration ( void )

Configures the different GPIO ports.

Parameters:
None
Return values:
None

Definition at line 222 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 61 of file STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 52 of file STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/main.c.

References ADC1, ADC_AnalogWatchdog_SingleRegEnable, ADC_AnalogWatchdogCmd(), ADC_AnalogWatchdogSingleChannelConfig(), ADC_AnalogWatchdogThresholdsConfig(), ADC_Channel_14, ADC_Cmd(), ADC_InitTypeDef::ADC_ContinuousConvMode, ADC_InitTypeDef::ADC_DataAlign, ADC_DataAlign_Right, ADC_InitTypeDef::ADC_ExternalTrigConv, ADC_ExternalTrigConv_None, ADC_GetCalibrationStatus(), ADC_GetResetCalibrationStatus(), ADC_Init(), ADC_IT_AWD, ADC_ITConfig(), ADC_InitTypeDef::ADC_Mode, ADC_Mode_Independent, ADC_InitTypeDef::ADC_NbrOfChannel, ADC_RegularChannelConfig(), ADC_ResetCalibration(), ADC_SampleTime_13Cycles5, ADC_InitTypeDef::ADC_ScanConvMode, ADC_SoftwareStartConvCmd(), ADC_StartCalibration(), DISABLE, ENABLE, GPIO_Configuration(), LED1, NVIC_Configuration(), RCC_Configuration(), and STM_EVAL_LEDInit().

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 74 of file STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 52 of file STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/stm32f10x_it.c.

void NVIC_Configuration ( void )

Configures NVIC and Vector Table base location.

Parameters:
None
Return values:
None
void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 131 of file STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/stm32f10x_it.c.

void RCC_Configuration ( void )

Configures the different system clocks.

Parameters:
None
Return values:
None

Definition at line 203 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 113 of file STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 140 of file STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/stm32f10x_it.c.

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 100 of file STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/stm32f10x_it.c.

Variable Documentation

ADC_InitTypeDef ADC_InitStructure

Definition at line 38 of file STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/main.c.


STM32F10x Standard Peripherals Firmware Library: ADC_ExtLinesTrigger

Defines | Functions | Variables

ADC_ExtLinesTrigger

STM32F10x_StdPeriph_Examples

Defines

#define | ADC1_DR_Address ((uint32_t)0x4001244C)

Functions

void | ADC1_2_IRQHandler (void)
This function handles ADC1 and ADC2 global interrupts requests.
void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | GPIO_Configuration (void)
Configures the different GPIO ports.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | NVIC_Configuration (void)
Configures NVIC and Vector Table base location.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | RCC_Configuration (void)
Configures the different system clocks.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

ADC_InitTypeDef ADC_InitStructure
__IO uint16_t | ADC_InjectedConvertedValueTab [32]
__IO uint16_t | ADC_InjectedConvertedValueTab [32]
__IO uint16_t | ADC_RegularConvertedValueTab [64]
DMA_InitTypeDef DMA_InitStructure
uint32_t | Index = 0

Define Documentation

#define ADC1_DR_Address ((uint32_t)0x4001244C)

Definition at line 35 of file STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/main.c.

Referenced by main().

Function Documentation

void ADC1_2_IRQHandler ( void )

This function handles ADC1 and ADC2 global interrupts requests.

Parameters:
None
Return values:
None

Definition at line 158 of file STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_it.c.

References ADC1, ADC_ClearITPendingBit(), ADC_GetInjectedConversionValue(), ADC_InjectedChannel_1, ADC_InjectedChannel_2, ADC_InjectedConvertedValueTab, ADC_IT_JEOC, and Index.

void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 89 of file STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 124 of file STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_it.c.

void GPIO_Configuration ( void )

Configures the different GPIO ports.

Parameters:
None
Return values:
None

Definition at line 222 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 63 of file STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 56 of file STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/main.c.

References ADC1, ADC1_DR_Address, ADC_Channel_11, ADC_Channel_12, ADC_Channel_14, ADC_Channel_4, ADC_Cmd(), ADC_InitTypeDef::ADC_ContinuousConvMode, ADC_InitTypeDef::ADC_DataAlign, ADC_DataAlign_Right, ADC_DiscModeChannelCountConfig(), ADC_DiscModeCmd(), ADC_DMACmd(), ADC_InitTypeDef::ADC_ExternalTrigConv, ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO, ADC_ExternalTrigConvCmd(), ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4, ADC_ExternalTrigInjectedConvCmd(), ADC_ExternalTrigInjectedConvConfig(), ADC_GetCalibrationStatus(), ADC_GetResetCalibrationStatus(), ADC_Init(), ADC_InjectedChannelConfig(), ADC_InjectedSequencerLengthConfig(), ADC_IT_JEOC, ADC_ITConfig(), ADC_InitTypeDef::ADC_Mode, ADC_Mode_Independent, ADC_InitTypeDef::ADC_NbrOfChannel, ADC_RegularChannelConfig(), ADC_RegularConvertedValueTab, ADC_ResetCalibration(), ADC_SampleTime_28Cycles5, ADC_InitTypeDef::ADC_ScanConvMode, ADC_StartCalibration(), DISABLE, DMA1_Channel1, DMA_InitTypeDef::DMA_BufferSize, DMA_Cmd(), DMA_DeInit(), DMA_InitTypeDef::DMA_DIR, DMA_DIR_PeripheralSRC, DMA_Init(), DMA_InitTypeDef::DMA_M2M, DMA_M2M_Disable, DMA_InitTypeDef::DMA_MemoryBaseAddr, DMA_InitTypeDef::DMA_MemoryDataSize, DMA_MemoryDataSize_HalfWord, DMA_InitTypeDef::DMA_MemoryInc, DMA_MemoryInc_Enable, DMA_InitTypeDef::DMA_Mode, DMA_Mode_Circular, DMA_InitTypeDef::DMA_PeripheralBaseAddr, DMA_InitTypeDef::DMA_PeripheralDataSize, DMA_PeripheralDataSize_HalfWord, DMA_InitTypeDef::DMA_PeripheralInc, DMA_PeripheralInc_Disable, DMA_InitTypeDef::DMA_Priority, DMA_Priority_High, ENABLE, EXTI_Configuration(), GPIO_Configuration(), NVIC_Configuration(), and RCC_Configuration().

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 76 of file STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 54 of file STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_it.c.

void NVIC_Configuration ( void )

Configures NVIC and Vector Table base location.

Parameters:
None
Return values:
None
void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 133 of file STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_it.c.

void RCC_Configuration ( void )

Configures the different system clocks.

Parameters:
None
Return values:
None

Definition at line 203 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 115 of file STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 142 of file STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_it.c.

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 102 of file STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_it.c.

Variable Documentation

ADC_InitTypeDef ADC_InitStructure

Definition at line 39 of file STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/main.c.

__IO uint16_t ADC_InjectedConvertedValueTab[32]

Definition at line 41 of file STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/main.c.

Referenced by ADC1_2_IRQHandler().

__IO uint16_t ADC_InjectedConvertedValueTab[32]

Definition at line 41 of file STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/main.c.

__IO uint16_t ADC_RegularConvertedValueTab[64]

Definition at line 41 of file STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/main.c.

Referenced by main().

DMA_InitTypeDef DMA_InitStructure

Definition at line 40 of file STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/main.c.

uint32_t Index = 0

Definition at line 40 of file STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_it.c.

Referenced by ADC1_2_IRQHandler(), and main().


STM32F10x Standard Peripherals Firmware Library: ADC_RegSimul_DualMode

Defines | Functions | Variables

ADC_RegSimul_DualMode

STM32F10x_StdPeriph_Examples

Defines

#define | ADC1_DR_Address ((uint32_t)0x4001244C)

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | GPIO_Configuration (void)
Configures the different GPIO ports.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | RCC_Configuration (void)
Configures the different system clocks.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

__IO uint32_t | ADC_DualConvertedValueTab [16]
ADC_InitTypeDef ADC_InitStructure
DMA_InitTypeDef DMA_InitStructure

Define Documentation

#define ADC1_DR_Address ((uint32_t)0x4001244C)

Definition at line 35 of file STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/main.c.

Referenced by main().

Function Documentation

void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 86 of file STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 121 of file STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/stm32f10x_it.c.

void GPIO_Configuration ( void )

Configures the different GPIO ports.

Parameters:
None
Return values:
None

Definition at line 222 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 60 of file STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 54 of file STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/main.c.

References ADC1, ADC1_DR_Address, ADC2, ADC_Channel_11, ADC_Channel_12, ADC_Channel_14, ADC_Channel_17, ADC_Cmd(), ADC_InitTypeDef::ADC_ContinuousConvMode, ADC_InitTypeDef::ADC_DataAlign, ADC_DataAlign_Right, ADC_DMACmd(), ADC_DualConvertedValueTab, ADC_InitTypeDef::ADC_ExternalTrigConv, ADC_ExternalTrigConv_None, ADC_ExternalTrigConvCmd(), ADC_GetCalibrationStatus(), ADC_GetResetCalibrationStatus(), ADC_Init(), ADC_InitTypeDef::ADC_Mode, ADC_Mode_RegSimult, ADC_InitTypeDef::ADC_NbrOfChannel, ADC_RegularChannelConfig(), ADC_ResetCalibration(), ADC_SampleTime_239Cycles5, ADC_InitTypeDef::ADC_ScanConvMode, ADC_SoftwareStartConvCmd(), ADC_StartCalibration(), ADC_TempSensorVrefintCmd(), DMA1_Channel1, DMA1_FLAG_TC1, DMA_InitTypeDef::DMA_BufferSize, DMA_ClearFlag(), DMA_Cmd(), DMA_DeInit(), DMA_InitTypeDef::DMA_DIR, DMA_DIR_PeripheralSRC, DMA_GetFlagStatus(), DMA_Init(), DMA_InitTypeDef::DMA_M2M, DMA_M2M_Disable, DMA_InitTypeDef::DMA_MemoryBaseAddr, DMA_InitTypeDef::DMA_MemoryDataSize, DMA_MemoryDataSize_Word, DMA_InitTypeDef::DMA_MemoryInc, DMA_MemoryInc_Enable, DMA_InitTypeDef::DMA_Mode, DMA_Mode_Normal, DMA_InitTypeDef::DMA_PeripheralBaseAddr, DMA_InitTypeDef::DMA_PeripheralDataSize, DMA_PeripheralDataSize_Word, DMA_InitTypeDef::DMA_PeripheralInc, DMA_PeripheralInc_Disable, DMA_InitTypeDef::DMA_Priority, DMA_Priority_High, ENABLE, GPIO_Configuration(), and RCC_Configuration().

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 73 of file STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 51 of file STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/stm32f10x_it.c.

void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 130 of file STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/stm32f10x_it.c.

void RCC_Configuration ( void )

Configures the different system clocks.

Parameters:
None
Return values:
None

Definition at line 203 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 112 of file STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 139 of file STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/stm32f10x_it.c.

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 99 of file STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/stm32f10x_it.c.

Variable Documentation

__IO uint32_t ADC_DualConvertedValueTab[16]

Definition at line 41 of file STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/main.c.

Referenced by main().

ADC_InitTypeDef ADC_InitStructure

Definition at line 39 of file STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/main.c.

DMA_InitTypeDef DMA_InitStructure

Definition at line 40 of file STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/main.c.


STM32F10x Standard Peripherals Firmware Library: ADC_TIMTrigger_AutoInjection

Defines | Functions | Variables

ADC_TIMTrigger_AutoInjection

STM32F10x_StdPeriph_Examples

Defines

#define | ADC1_DR_Address ((uint32_t)0x4001244C)

Functions

void | ADC1_2_IRQHandler (void)
This function handles ADC1 and ADC2 global interrupts requests.
void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | GPIO_Configuration (void)
Configures the different GPIO ports.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | NVIC_Configuration (void)
Configures NVIC and Vector Table base location.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | RCC_Configuration (void)
Configures the different system clocks.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

ADC_InitTypeDef ADC_InitStructure
__IO uint16_t | ADC_InjectedConvertedValueTab [32]
__IO uint16_t | ADC_InjectedConvertedValueTab [32]
__IO uint16_t | ADC_RegularConvertedValueTab [32]
DMA_InitTypeDef DMA_InitStructure
__IO uint32_t | Index
TIM_OCInitTypeDef TIM_OCInitStructure
TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure

Define Documentation

#define ADC1_DR_Address ((uint32_t)0x4001244C)

Definition at line 35 of file STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/main.c.

Referenced by main().

Function Documentation

void ADC1_2_IRQHandler ( void )

This function handles ADC1 and ADC2 global interrupts requests.

Parameters:
None
Return values:
None

Definition at line 158 of file STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_it.c.

References ADC1, ADC2, ADC2ConvertedValue, ADC_ClearITPendingBit(), ADC_GetConversionValue(), ADC_GetInjectedConversionValue(), ADC_InjectedChannel_1, ADC_InjectedConvertedValueTab, ADC_IT_JEOC, Bit_RESET, Bit_SET, GPIO_Pin_6, GPIO_WriteBit(), GPIOC, and Index.

void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 89 of file STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 124 of file STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_it.c.

void GPIO_Configuration ( void )

Configures the different GPIO ports.

Parameters:
None
Return values:
None

Definition at line 222 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 63 of file STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 57 of file STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/main.c.

References ADC1, ADC1_DR_Address, ADC_AutoInjectedConvCmd(), ADC_Channel_11, ADC_Channel_14, ADC_Cmd(), ADC_InitTypeDef::ADC_ContinuousConvMode, ADC_InitTypeDef::ADC_DataAlign, ADC_DataAlign_Right, ADC_DMACmd(), ADC_InitTypeDef::ADC_ExternalTrigConv, ADC_ExternalTrigConv_T1_CC1, ADC_ExternalTrigConvCmd(), ADC_ExternalTrigInjecConv_None, ADC_ExternalTrigInjectedConvConfig(), ADC_GetCalibrationStatus(), ADC_GetResetCalibrationStatus(), ADC_Init(), ADC_InjectedChannelConfig(), ADC_InjectedSequencerLengthConfig(), ADC_IT_JEOC, ADC_ITConfig(), ADC_InitTypeDef::ADC_Mode, ADC_Mode_Independent, ADC_InitTypeDef::ADC_NbrOfChannel, ADC_RegularChannelConfig(), ADC_RegularConvertedValueTab, ADC_ResetCalibration(), ADC_SampleTime_13Cycles5, ADC_SampleTime_71Cycles5, ADC_InitTypeDef::ADC_ScanConvMode, ADC_StartCalibration(), DISABLE, DMA1_Channel1, DMA1_FLAG_TC1, DMA_InitTypeDef::DMA_BufferSize, DMA_ClearFlag(), DMA_Cmd(), DMA_DeInit(), DMA_InitTypeDef::DMA_DIR, DMA_DIR_PeripheralSRC, DMA_GetFlagStatus(), DMA_Init(), DMA_InitTypeDef::DMA_M2M, DMA_M2M_Disable, DMA_InitTypeDef::DMA_MemoryBaseAddr, DMA_InitTypeDef::DMA_MemoryDataSize, DMA_MemoryDataSize_HalfWord, DMA_InitTypeDef::DMA_MemoryInc, DMA_MemoryInc_Enable, DMA_InitTypeDef::DMA_Mode, DMA_Mode_Normal, DMA_InitTypeDef::DMA_PeripheralBaseAddr, DMA_InitTypeDef::DMA_PeripheralDataSize, DMA_PeripheralDataSize_HalfWord, DMA_InitTypeDef::DMA_PeripheralInc, DMA_PeripheralInc_Disable, DMA_InitTypeDef::DMA_Priority, DMA_Priority_High, ENABLE, GPIO_Configuration(), NVIC_Configuration(), RCC_Configuration(), TIM1, TIM_TimeBaseInitTypeDef::TIM_ClockDivision, TIM_Cmd(), TIM_TimeBaseInitTypeDef::TIM_CounterMode, TIM_CounterMode_Up, TIM_CtrlPWMOutputs(), TIM_OC1Init(), TIM_OCInitTypeDef::TIM_OCMode, TIM_OCMode_PWM1, TIM_OCInitTypeDef::TIM_OCPolarity, TIM_OCPolarity_Low, TIM_OCInitTypeDef::TIM_OutputState, TIM_OutputState_Enable, TIM_TimeBaseInitTypeDef::TIM_Period, TIM_TimeBaseInitTypeDef::TIM_Prescaler, TIM_OCInitTypeDef::TIM_Pulse, TIM_TimeBaseInit(), and TIM_TimeBaseStructInit().

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 76 of file STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 54 of file STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_it.c.

void NVIC_Configuration ( void )

Configures NVIC and Vector Table base location.

Parameters:
None
Return values:
None
void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 133 of file STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_it.c.

void RCC_Configuration ( void )

Configures the different system clocks.

Parameters:
None
Return values:
None

Definition at line 203 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 115 of file STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 142 of file STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_it.c.

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 102 of file STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_it.c.

Variable Documentation

ADC_InitTypeDef ADC_InitStructure

Definition at line 39 of file STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/main.c.

__IO uint16_t ADC_InjectedConvertedValueTab[32]

Definition at line 43 of file STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/main.c.

__IO uint16_t ADC_InjectedConvertedValueTab[32]

Definition at line 41 of file STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/main.c.

Referenced by ADC1_2_IRQHandler().

__IO uint16_t ADC_RegularConvertedValueTab[32]

Definition at line 43 of file STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/main.c.

DMA_InitTypeDef DMA_InitStructure

Definition at line 40 of file STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/main.c.

__IO uint32_t Index

Definition at line 40 of file STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_it.c.

TIM_OCInitTypeDef TIM_OCInitStructure

Definition at line 42 of file STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/main.c.

Referenced by TIM_Config().

TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure

Definition at line 41 of file STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/main.c.

Referenced by TIM_Config().


STM32F10x Standard Peripherals Firmware Library: BKP_Backup_Data

Defines | Functions | Variables

BKP_Backup_Data

STM32F10x_StdPeriph_Examples

Defines

#define | BKP_DR_NUMBER 42

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

uint16_t | BKPDataReg [BKP_DR_NUMBER]

Define Documentation

#define BKP_DR_NUMBER 42

Definition at line 39 of file STM32F10x_StdPeriph_Examples/BKP/Backup_Data/main.c.

Referenced by CheckBackupReg(), and WriteToBackupReg().

Function Documentation

void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 86 of file STM32F10x_StdPeriph_Examples/BKP/Backup_Data/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 121 of file STM32F10x_StdPeriph_Examples/BKP/Backup_Data/stm32f10x_it.c.

void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 60 of file STM32F10x_StdPeriph_Examples/BKP/Backup_Data/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 73 of file STM32F10x_StdPeriph_Examples/BKP/Backup_Data/main.c.

References BKP_ClearFlag(), CheckBackupReg(), ENABLE, LED1, LED2, LED3, LED4, PWR_BackupAccessCmd(), RCC_APB1Periph_BKP, RCC_APB1Periph_PWR, RCC_APB1PeriphClockCmd(), RCC_ClearFlag(), RCC_FLAG_PORRST, RCC_GetFlagStatus(), RESET, STM_EVAL_LEDInit(), STM_EVAL_LEDOn(), and WriteToBackupReg().

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 73 of file STM32F10x_StdPeriph_Examples/BKP/Backup_Data/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 51 of file STM32F10x_StdPeriph_Examples/BKP/Backup_Data/stm32f10x_it.c.

void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 130 of file STM32F10x_StdPeriph_Examples/BKP/Backup_Data/stm32f10x_it.c.

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 112 of file STM32F10x_StdPeriph_Examples/BKP/Backup_Data/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 139 of file STM32F10x_StdPeriph_Examples/BKP/Backup_Data/stm32f10x_it.c.

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 99 of file STM32F10x_StdPeriph_Examples/BKP/Backup_Data/stm32f10x_it.c.

Variable Documentation

uint16_t BKPDataReg[BKP_DR_NUMBER]
Initial value:
  {
    BKP_DR1, BKP_DR2, BKP_DR3, BKP_DR4, BKP_DR5, BKP_DR6, BKP_DR7, BKP_DR8,
    BKP_DR9, BKP_DR10, BKP_DR11, BKP_DR12, BKP_DR13, BKP_DR14, BKP_DR15, BKP_DR16,
    BKP_DR17, BKP_DR18, BKP_DR19, BKP_DR20, BKP_DR21, BKP_DR22, BKP_DR23, BKP_DR24,
    BKP_DR25, BKP_DR26, BKP_DR27, BKP_DR28, BKP_DR29, BKP_DR30, BKP_DR31, BKP_DR32,
    BKP_DR33, BKP_DR34, BKP_DR35, BKP_DR36, BKP_DR37, BKP_DR38, BKP_DR39, BKP_DR40,
    BKP_DR41, BKP_DR42
  }

Definition at line 51 of file STM32F10x_StdPeriph_Examples/BKP/Backup_Data/main.c.

Referenced by CheckBackupReg(), IsBackupRegReset(), and WriteToBackupReg().


STM32F10x Standard Peripherals Firmware Library: BKP_Tamper

Defines | Functions | Variables

BKP_Tamper

STM32F10x_StdPeriph_Examples

Defines

#define | BKP_DR_NUMBER 42

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
uint32_t | CheckBackupReg (uint16_t FirstBackupData)
Checks if the Backup DRx registers values are correct or not.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | GPIO_Configuration (void)
Configures the different GPIO ports.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
uint32_t | IsBackupRegReset (void)
Checks if the Backup DRx registers are reset or not.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | NVIC_Configuration (void)
Configures NVIC and Vector Table base location.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | TAMPER_IRQHandler (void)
This function handles Tamper interrupt request.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.
void | WriteToBackupReg (uint16_t FirstBackupData)
Writes data Backup DRx registers.

Variables

uint16_t | BKPDataReg [BKP_DR_NUMBER]

Define Documentation

#define BKP_DR_NUMBER 42

Definition at line 38 of file STM32F10x_StdPeriph_Examples/BKP/Tamper/main.c.

Referenced by IsBackupRegReset().

Function Documentation

void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 87 of file STM32F10x_StdPeriph_Examples/BKP/Tamper/stm32f10x_it.c.

uint32_t CheckBackupReg ( uint16_t FirstBackupData )

Checks if the Backup DRx registers values are correct or not.

Parameters:
FirstBackupData,: data to be compared with Backup data registers.
Return values:
0,: All Backup DRx registers values are correct

  • Value different from 0: Number of the first Backup register which value is not correct
void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 122 of file STM32F10x_StdPeriph_Examples/BKP/Tamper/stm32f10x_it.c.

void GPIO_Configuration ( void )

Configures the different GPIO ports.

Configure TIM9 pins.

Configures TIM1, TIM3 and TIM4 Pins.

Configure TIM10 pin.

Configure the TIM3 Ouput Channels.

Configure the TIM3 Pins.

Configure the TIM3 and the GPIOE Pins.

Configure the GPIO Pins.

Configure the GPIOD Pins.

Configure the TIM1 Pins.

Parameters:
None
Return values:
None
Parameters:
None
Return values:
None Configures the different GPIO ports.
Parameters:
None
Return values:
None

Definition at line 222 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

References GPIO_Init(), GPIO_InitStructure, GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_AIN, GPIO_InitTypeDef::GPIO_Pin, GPIO_Pin_2, GPIO_Pin_3, GPIO_Pin_4, and GPIOC.

Referenced by main().

void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 61 of file STM32F10x_StdPeriph_Examples/BKP/Tamper/stm32f10x_it.c.

uint32_t IsBackupRegReset ( void )

Checks if the Backup DRx registers are reset or not.

Parameters:
None
Return values:
0,: All Backup DRx registers are reset

  • Value different from 0: Number of the first Backup register not reset

Definition at line 199 of file STM32F10x_StdPeriph_Examples/BKP/Tamper/main.c.

References BKP_DR_NUMBER, BKP_ReadBackupRegister(), and BKPDataReg.

Referenced by TAMPER_IRQHandler().

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 74 of file STM32F10x_StdPeriph_Examples/BKP/Tamper/main.c.

References BKP_ClearFlag(), BKP_ITConfig(), BKP_TamperPinCmd(), BKP_TamperPinLevel_Low, BKP_TamperPinLevelConfig(), CheckBackupReg(), DISABLE, ENABLE, LED1, LED2, LED3, LED4, NVIC_Configuration(), PWR_BackupAccessCmd(), RCC_APB1Periph_BKP, RCC_APB1Periph_PWR, RCC_APB1PeriphClockCmd(), STM_EVAL_LEDInit(), STM_EVAL_LEDOn(), and WriteToBackupReg().

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 74 of file STM32F10x_StdPeriph_Examples/BKP/Tamper/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 52 of file STM32F10x_StdPeriph_Examples/BKP/Tamper/stm32f10x_it.c.

void NVIC_Configuration ( void )

Configures NVIC and Vector Table base location.

Parameters:
None
Return values:
None
void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 131 of file STM32F10x_StdPeriph_Examples/BKP/Tamper/stm32f10x_it.c.

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 113 of file STM32F10x_StdPeriph_Examples/BKP/Tamper/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 140 of file STM32F10x_StdPeriph_Examples/BKP/Tamper/stm32f10x_it.c.

void TAMPER_IRQHandler ( void )

This function handles Tamper interrupt request.

Parameters:
None
Return values:
None

Definition at line 153 of file STM32F10x_StdPeriph_Examples/BKP/Tamper/stm32f10x_it.c.

References BKP_ClearFlag(), BKP_ClearITPendingBit(), BKP_GetITStatus(), BKP_TamperPinCmd(), DISABLE, ENABLE, IsBackupRegReset(), LED3, LED4, RESET, and STM_EVAL_LEDOn().

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 100 of file STM32F10x_StdPeriph_Examples/BKP/Tamper/stm32f10x_it.c.

void WriteToBackupReg ( uint16_t FirstBackupData )

Writes data Backup DRx registers.

Parameters:
FirstBackupData,: data to be written to Backup data registers.
Return values:
None

Variable Documentation

uint16_t BKPDataReg[BKP_DR_NUMBER]
Initial value:
  {
    BKP_DR1, BKP_DR2, BKP_DR3, BKP_DR4, BKP_DR5, BKP_DR6, BKP_DR7, BKP_DR8,
    BKP_DR9, BKP_DR10, BKP_DR11, BKP_DR12, BKP_DR13, BKP_DR14, BKP_DR15, BKP_DR16,
    BKP_DR17, BKP_DR18, BKP_DR19, BKP_DR20, BKP_DR21, BKP_DR22, BKP_DR23, BKP_DR24,
    BKP_DR25, BKP_DR26, BKP_DR27, BKP_DR28, BKP_DR29, BKP_DR30, BKP_DR31, BKP_DR32,
    BKP_DR33, BKP_DR34, BKP_DR35, BKP_DR36, BKP_DR37, BKP_DR38, BKP_DR39, BKP_DR40,
    BKP_DR41, BKP_DR42
  }

Definition at line 50 of file STM32F10x_StdPeriph_Examples/BKP/Tamper/main.c.


STM32F10x Standard Peripherals Firmware Library: CAN_DualCAN

Defines | Functions | Variables

CAN_DualCAN

STM32F10x_StdPeriph_Examples

Defines

#define | CAN_BAUDRATE 1000

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | CAN1_RX0_IRQHandler (void)
This function handles CAN1 RX0 Handler.
void | CAN2_RX0_IRQHandler (void)
This function handles CAN2 RX0 Handler.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSVC exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

CAN_FilterInitTypeDef CAN_FilterInitStructure
CAN_InitTypeDef CAN_InitStructure
CanRxMsg RxMessage
CanTxMsg TxMessage

Define Documentation

#define CAN_BAUDRATE 1000

Definition at line 37 of file STM32F10x_StdPeriph_Examples/CAN/DualCAN/main.c.

Function Documentation

void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 89 of file STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_it.c.

void CAN1_RX0_IRQHandler ( void )

This function handles CAN1 RX0 Handler.

Parameters:
None
Return values:
None

Definition at line 156 of file STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_it.c.

References CAN1, CAN_FIFO0, CAN_ID_STD, CAN_Receive(), CanRxMsg::Data, CanRxMsg::DLC, CanRxMsg::IDE, LED_Display(), and CanRxMsg::StdId.

void CAN2_RX0_IRQHandler ( void )

This function handles CAN2 RX0 Handler.

Parameters:
None
Return values:
None

Definition at line 178 of file STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_it.c.

References CAN2, CAN_FIFO0, CAN_ID_STD, CAN_Receive(), CanRxMsg::Data, CanRxMsg::DLC, CanRxMsg::IDE, LED_Display(), and CanRxMsg::StdId.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 124 of file STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_it.c.

void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 63 of file STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 65 of file STM32F10x_StdPeriph_Examples/CAN/DualCAN/main.c.

References BUTTON_KEY, BUTTON_MODE_GPIO, BUTTON_TAMPER, CAN1, CAN2, CAN_Config(), CAN_IT_FMP0, CAN_ITConfig(), CAN_Transmit(), CanTxMsg::Data, ENABLE, LCD_Clear(), LCD_COLOR_BLUE, LCD_COLOR_GREEN, LCD_COLOR_RED, LCD_COLOR_WHITE, LCD_DisplayStringLine(), LCD_LINE_0, LCD_LINE_1, LCD_LINE_2, LCD_LINE_3, LCD_LINE_4, LCD_SetBackColor(), LCD_SetTextColor(), LED1, LED2, LED3, LED4, LED_Display(), NVIC_Config(), RESET, STM3210C_LCD_Init(), STM_EVAL_LEDInit(), STM_EVAL_LEDOff(), STM_EVAL_PBGetState(), and STM_EVAL_PBInit().

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 76 of file STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 54 of file STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_it.c.

void PendSV_Handler ( void )

This function handles PendSVC exception.

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 133 of file STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_it.c.

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 115 of file STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 142 of file STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_it.c.

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 102 of file STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_it.c.

Variable Documentation

CAN_FilterInitTypeDef CAN_FilterInitStructure

Definition at line 48 of file STM32F10x_StdPeriph_Examples/CAN/DualCAN/main.c.

Referenced by CAN_Interrupt(), and CAN_Polling().

CAN_InitTypeDef CAN_InitStructure

Definition at line 47 of file STM32F10x_StdPeriph_Examples/CAN/DualCAN/main.c.

Referenced by CAN_Interrupt(), and CAN_Polling().

CanRxMsg RxMessage

Definition at line 39 of file STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_it.c.

Referenced by CAN_Polling(), and USB_LP_CAN1_RX0_IRQHandler().

CanTxMsg TxMessage

Definition at line 49 of file STM32F10x_StdPeriph_Examples/CAN/DualCAN/main.c.

Referenced by CAN_Interrupt(), and CAN_Polling().


STM32F10x Standard Peripherals Firmware Library: CAN_LoopBack

Defines | Enumerations | Functions | Variables

CAN_LoopBack

STM32F10x_StdPeriph_Examples

Defines

#define | __CAN1_USED__
#define | CANx CAN1

Enumerations

enum TestStatus {
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED
}

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
TestStatus | CAN_Interrupt (void)
Configures the CAN, transmit and receive using interrupt.
TestStatus | CAN_Polling (void)
Configures the CAN, transmit and receive by polling.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | NVIC_Configuration (void)
Configures the NVIC and Vector Table base address.
void | PendSV_Handler (void)
This function handles PendSVC exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.
void | USB_LP_CAN1_RX0_IRQHandler (void)
This function handles CAN1 Handler.

Variables

__IO uint32_t | ret = 0
__IO uint32_t | ret
volatile TestStatus | TestRx

Define Documentation

#define __CAN1_USED__

Definition at line 37 of file STM32F10x_StdPeriph_Examples/CAN/LoopBack/main.c.

#define CANx CAN1

Definition at line 42 of file STM32F10x_StdPeriph_Examples/CAN/LoopBack/main.c.

Referenced by CAN_Interrupt(), and CAN_Polling().

Enumeration Type Documentation

enum TestStatus
Enumerator:
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED

Definition at line 48 of file STM32F10x_StdPeriph_Examples/CAN/LoopBack/main.c.

Function Documentation

void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 88 of file STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_it.c.

TestStatus CAN_Interrupt ( void )

Configures the CAN, transmit and receive using interrupt.

Parameters:
None
Return values:
PASSED if the reception is well done, FAILED in other case

Definition at line 245 of file STM32F10x_StdPeriph_Examples/CAN/LoopBack/main.c.

References CAN_InitTypeDef::CAN_ABOM, CAN_InitTypeDef::CAN_AWUM, CAN_InitTypeDef::CAN_BS1, CAN_BS1_2tq, CAN_InitTypeDef::CAN_BS2, CAN_BS2_3tq, CAN_DeInit(), CAN_FIFO0, CAN_FilterInitTypeDef::CAN_FilterActivation, CAN_FilterInitTypeDef::CAN_FilterFIFOAssignment, CAN_FilterInitTypeDef::CAN_FilterIdHigh, CAN_FilterInitTypeDef::CAN_FilterIdLow, CAN_FilterInit(), CAN_FilterInitStructure, CAN_FilterInitTypeDef::CAN_FilterMaskIdHigh, CAN_FilterInitTypeDef::CAN_FilterMaskIdLow, CAN_FilterInitTypeDef::CAN_FilterMode, CAN_FilterMode_IdMask, CAN_FilterInitTypeDef::CAN_FilterNumber, CAN_FilterInitTypeDef::CAN_FilterScale, CAN_FilterScale_32bit, CAN_ID_EXT, CAN_Init(), CAN_InitStructure, CAN_IT_FMP0, CAN_ITConfig(), CAN_InitTypeDef::CAN_Mode, CAN_Mode_LoopBack, CAN_InitTypeDef::CAN_NART, CAN_InitTypeDef::CAN_Prescaler, CAN_InitTypeDef::CAN_RFLM, CAN_RTR_DATA, CAN_InitTypeDef::CAN_SJW, CAN_SJW_1tq, CAN_StructInit(), CAN_Transmit(), CAN_InitTypeDef::CAN_TTCM, CAN_InitTypeDef::CAN_TXFP, CANx, CanTxMsg::Data, DISABLE, CanTxMsg::DLC, ENABLE, CanTxMsg::ExtId, CanTxMsg::IDE, ret, CanTxMsg::RTR, CanTxMsg::StdId, and TxMessage.

Referenced by main().

TestStatus CAN_Polling ( void )

Configures the CAN, transmit and receive by polling.

Parameters:
None
Return values:
PASSED if the reception is well done, FAILED in other case

Definition at line 140 of file STM32F10x_StdPeriph_Examples/CAN/LoopBack/main.c.

References CAN_InitTypeDef::CAN_ABOM, CAN_InitTypeDef::CAN_AWUM, CAN_InitTypeDef::CAN_BS1, CAN_BS1_2tq, CAN_InitTypeDef::CAN_BS2, CAN_BS2_3tq, CAN_DeInit(), CAN_FIFO0, CAN_FilterInitTypeDef::CAN_FilterActivation, CAN_FilterInitTypeDef::CAN_FilterFIFOAssignment, CAN_FilterInitTypeDef::CAN_FilterIdHigh, CAN_FilterInitTypeDef::CAN_FilterIdLow, CAN_FilterInit(), CAN_FilterInitStructure, CAN_FilterInitTypeDef::CAN_FilterMaskIdHigh, CAN_FilterInitTypeDef::CAN_FilterMaskIdLow, CAN_FilterInitTypeDef::CAN_FilterMode, CAN_FilterMode_IdMask, CAN_FilterInitTypeDef::CAN_FilterNumber, CAN_FilterInitTypeDef::CAN_FilterScale, CAN_FilterScale_32bit, CAN_ID_STD, CAN_Init(), CAN_InitStructure, CAN_MessagePending(), CAN_InitTypeDef::CAN_Mode, CAN_Mode_LoopBack, CAN_InitTypeDef::CAN_NART, CAN_InitTypeDef::CAN_Prescaler, CAN_Receive(), CAN_InitTypeDef::CAN_RFLM, CAN_RTR_DATA, CAN_InitTypeDef::CAN_SJW, CAN_SJW_1tq, CAN_StructInit(), CAN_Transmit(), CAN_TransmitStatus(), CAN_InitTypeDef::CAN_TTCM, CAN_InitTypeDef::CAN_TXFP, CANTXOK, CANx, CanRxMsg::Data, CanTxMsg::Data, DISABLE, CanRxMsg::DLC, CanTxMsg::DLC, ENABLE, FAILED, CanRxMsg::IDE, CanTxMsg::IDE, PASSED, CanTxMsg::RTR, RxMessage, CanRxMsg::StdId, CanTxMsg::StdId, and TxMessage.

Referenced by main().

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 123 of file STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_it.c.

void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 62 of file STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 66 of file STM32F10x_StdPeriph_Examples/CAN/LoopBack/main.c.

References CAN_Interrupt(), CAN_Polling(), ENABLE, FAILED, LED1, LED2, LED3, LED4, NVIC_Configuration(), RCC_APB1Periph_CAN1, RCC_APB1Periph_CAN2, RCC_APB1PeriphClockCmd(), STM_EVAL_LEDInit(), STM_EVAL_LEDOff(), STM_EVAL_LEDOn(), and TestRx.

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 75 of file STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 53 of file STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_it.c.

void NVIC_Configuration ( void )

Configures the NVIC and Vector Table base address.

Parameters:
None
Return values:
None
void PendSV_Handler ( void )

This function handles PendSVC exception.

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 132 of file STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_it.c.

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 114 of file STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 141 of file STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_it.c.

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 101 of file STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_it.c.

void USB_LP_CAN1_RX0_IRQHandler ( void )

This function handles CAN1 Handler.

Parameters:
None
Return values:
None

Definition at line 155 of file STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_it.c.

Variable Documentation

__IO uint32_t ret = 0

Definition at line 51 of file STM32F10x_StdPeriph_Examples/CAN/LoopBack/main.c.

Referenced by CAN_Interrupt(), and USB_LP_CAN1_RX0_IRQHandler().

__IO uint32_t ret

Definition at line 51 of file STM32F10x_StdPeriph_Examples/CAN/LoopBack/main.c.

Referenced by CAN_Interrupt(), and USB_LP_CAN1_RX0_IRQHandler().

volatile TestStatus TestRx

Definition at line 52 of file STM32F10x_StdPeriph_Examples/CAN/LoopBack/main.c.

Referenced by main().


STM32F10x Standard Peripherals Firmware Library: CAN_Networking

Defines | Functions | Variables

CAN_Networking

STM32F10x_StdPeriph_Examples

Defines

#define | __CAN1_USED__
#define | CANx CAN2
#define | GPIO_CAN GPIO_CAN2
#define | GPIO_CAN GPIO_CAN2
#define | GPIO_Pin_CAN_RX GPIO_Pin_CAN2_RX
#define | GPIO_Pin_CAN_TX GPIO_Pin_CAN2_TX
#define | GPIO_Remapping_CAN GPIO_Remap_CAN2
#define | KEY_NOT_PRESSED 0x00
#define | KEY_PRESSED 0x01

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | CAN_Config (void)
Configures the CAN.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | Delay (void)
Delay.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | Init_RxMes (CanRxMsg *RxMessage)
Initializes a Rx Message.
void | LED_Display (uint8_t Ledstatus)
Turn ON/OFF the dedicate led.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | NVIC_Config (void)
Configures the NVIC for CAN.
void | PendSV_Handler (void)
This function handles PendSVC exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.
void | USB_LP_CAN1_RX0_IRQHandler (void)
This function handles CAN1 Handler.

Variables

CAN_FilterInitTypeDef CAN_FilterInitStructure
CAN_InitTypeDef CAN_InitStructure
uint8_t | KeyNumber = 0x0
uint8_t | KeyNumber
CanRxMsg RxMessage
CanTxMsg TxMessage

Define Documentation

#define __CAN1_USED__

Definition at line 37 of file STM32F10x_StdPeriph_Examples/CAN/Networking/main.c.

#define CANx CAN2

Definition at line 48 of file STM32F10x_StdPeriph_Examples/CAN/Networking/main.c.

Referenced by main().

#define GPIO_CAN GPIO_CAN2

Definition at line 51 of file STM32F10x_StdPeriph_Examples/CAN/Networking/main.c.

#define GPIO_CAN GPIO_CAN2

Definition at line 51 of file STM32F10x_StdPeriph_Examples/CAN/Networking/main.c.

#define GPIO_Pin_CAN_RX GPIO_Pin_CAN2_RX

Definition at line 52 of file STM32F10x_StdPeriph_Examples/CAN/Networking/main.c.

#define GPIO_Pin_CAN_TX GPIO_Pin_CAN2_TX

Definition at line 53 of file STM32F10x_StdPeriph_Examples/CAN/Networking/main.c.

#define GPIO_Remapping_CAN GPIO_Remap_CAN2

Definition at line 50 of file STM32F10x_StdPeriph_Examples/CAN/Networking/main.c.

#define KEY_NOT_PRESSED 0x00

Definition at line 57 of file STM32F10x_StdPeriph_Examples/CAN/Networking/main.c.

Referenced by main().

#define KEY_PRESSED 0x01

Definition at line 56 of file STM32F10x_StdPeriph_Examples/CAN/Networking/main.c.

Referenced by main().

Function Documentation

void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 90 of file STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_it.c.

void CAN_Config ( void )

Configures the CAN.

Parameters:
None
Return values:
None
void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 125 of file STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_it.c.

void Delay ( void )

Delay.

Parameters:
None
Return values:
None
void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 64 of file STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_it.c.

void Init_RxMes ( CanRxMsg * RxMessage )

Initializes a Rx Message.

Parameters:
CanRxMsg *RxMessage
Return values:
None
void LED_Display ( uint8_t Ledstatus )

Turn ON/OFF the dedicate led.

Parameters:
Ledstatus,: Led number from 0 to 3.
Return values:
None
int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 80 of file STM32F10x_StdPeriph_Examples/CAN/Networking/main.c.

References BUTTON_KEY, BUTTON_MODE_GPIO, CAN_Config(), CAN_IT_FMP0, CAN_ITConfig(), CAN_Transmit(), CANx, CanTxMsg::Data, Delay(), ENABLE, KEY_NOT_PRESSED, KEY_PRESSED, KeyNumber, LED1, LED2, LED3, LED4, LED_Display(), NVIC_Config(), STM_EVAL_LEDInit(), STM_EVAL_LEDOff(), STM_EVAL_PBGetState(), and STM_EVAL_PBInit().

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 77 of file STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 55 of file STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_it.c.

void NVIC_Config ( void )

Configures the NVIC for CAN.

Parameters:
None
Return values:
None
void PendSV_Handler ( void )

This function handles PendSVC exception.

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 134 of file STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_it.c.

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 116 of file STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 143 of file STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_it.c.

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 103 of file STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_it.c.

void USB_LP_CAN1_RX0_IRQHandler ( void )

This function handles CAN1 Handler.

Parameters:
None
Return values:
None

Definition at line 157 of file STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_it.c.

References CAN1, CAN_FIFO0, CAN_ID_EXT, CAN_ID_STD, CAN_Receive(), CanRxMsg::Data, CanRxMsg::DLC, CanRxMsg::ExtId, CanRxMsg::FMI, CanRxMsg::IDE, KeyNumber, LED_Display(), ret, RxMessage, and CanRxMsg::StdId.

Variable Documentation

CAN_FilterInitTypeDef CAN_FilterInitStructure

Definition at line 62 of file STM32F10x_StdPeriph_Examples/CAN/Networking/main.c.

CAN_InitTypeDef CAN_InitStructure

Definition at line 61 of file STM32F10x_StdPeriph_Examples/CAN/Networking/main.c.

uint8_t KeyNumber = 0x0

Definition at line 64 of file STM32F10x_StdPeriph_Examples/CAN/Networking/main.c.

Referenced by main(), and USB_LP_CAN1_RX0_IRQHandler().

uint8_t KeyNumber

Definition at line 64 of file STM32F10x_StdPeriph_Examples/CAN/Networking/main.c.

Referenced by main(), and USB_LP_CAN1_RX0_IRQHandler().

CanRxMsg RxMessage

Definition at line 39 of file STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_it.c.

CanTxMsg TxMessage

Definition at line 63 of file STM32F10x_StdPeriph_Examples/CAN/Networking/main.c.


STM32F10x Standard Peripherals Firmware Library: CEC_DataExchangeInterrupt

Enumerations | Functions | Variables

CEC_DataExchangeInterrupt

STM32F10x_StdPeriph_Examples

Enumerations

enum TestStatus {
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED
}

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | CEC_IRQHandler (void)
This function handles CEC global interrupt request.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | EXTI9_5_IRQHandler (void)
This function handles EXTI Lines 9 to 5 interrupts requests.
void | GPIO_Configuration (void)
Configures the different GPIO ports.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | NVIC_Configuration (void)
Configures the different NVIC interrupts.
void | PendSV_Handler (void)
This function handles PendSVC exception.
void | RCC_Configuration (void)
Configures the different system clocks.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

uint8_t | ByteNumber = 10
uint8_t | ByteNumber
CEC_InitTypeDef CEC_InitStructure
uint8_t | HeaderBlockValueToSend = 0
uint8_t | InitiatorAddress = 0
uint8_t | rcv_inc = 0
uint8_t | ReceiveBuffer [10]
uint8_t | ReceiveBuffer [10]
__IO uint8_t | ReceivedFrame = 0
__IO uint8_t | ReceivedFrame
uint8_t | RecepErrorCode = 0
uint8_t | send_inc = 0
uint8_t | TransErrorCode = 0
volatile TestStatus | TransferStatus = FAILED
uint8_t | TransmitBuffer [10]
uint8_t | TransmitBuffer [10]

Enumeration Type Documentation

enum TestStatus
Enumerator:
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED

Definition at line 36 of file STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/main.c.

Function Documentation

void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 100 of file STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.c.

void CEC_IRQHandler ( void )

This function handles CEC global interrupt request.

Parameters:
None
Return values:
None

Definition at line 190 of file STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.c.

References ByteNumber, CEC, CEC_ClearFlag(), CEC_EndOfMessageCmd(), CEC_FLAG_RBTF, CEC_FLAG_REOM, CEC_FLAG_RERR, CEC_FLAG_RSOM, CEC_FLAG_TBTRF, CEC_FLAG_TEOM, CEC_FLAG_TERR, CEC_GetFlagStatus(), CEC_ReceiveDataByte(), CEC_SendDataByte(), DISABLE, ENABLE, InitiatorAddress, LED4, rcv_inc, ReceiveBuffer, ReceivedFrame, RecepErrorCode, send_inc, STM_EVAL_LEDOn(), TransErrorCode, and TransmitBuffer.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 135 of file STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.c.

void EXTI9_5_IRQHandler ( void )

This function handles EXTI Lines 9 to 5 interrupts requests.

Parameters:
None
Return values:
None

Definition at line 162 of file STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.c.

void GPIO_Configuration ( void )

Configures the different GPIO ports.

Parameters:
None
Return values:
None

Definition at line 222 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 74 of file STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 62 of file STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/main.c.

References Buffercmp(), ByteNumber, CEC_InitTypeDef::CEC_BitPeriodMode, CEC_BitPeriodStdMode, CEC_InitTypeDef::CEC_BitTimingMode, CEC_BitTimingStdMode, CEC_Cmd(), CEC_Init(), CEC_ITConfig(), CEC_OwnAddressConfig(), CEC_SetPrescaler(), ENABLE, GPIO_Configuration(), LED1, LED2, MY_DEVICE_ADDRESS, NVIC_Configuration(), PASSED, RCC_Configuration(), ReceiveBuffer, ReceivedFrame, STM_EVAL_LEDOn(), TransferStatus, and TransmitBuffer.

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 87 of file STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 65 of file STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.c.

void NVIC_Configuration ( void )

Configures the different NVIC interrupts.

Parameters:
None
Return values:
None
void PendSV_Handler ( void )

This function handles PendSVC exception.

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 144 of file STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.c.

void RCC_Configuration ( void )

Configures the different system clocks.

Parameters:
None
Return values:
None

Definition at line 203 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 126 of file STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 153 of file STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.c.

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 113 of file STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.c.

Variable Documentation

uint8_t ByteNumber = 10

Definition at line 43 of file STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/main.c.

Referenced by CEC_IRQHandler(), and main().

uint8_t ByteNumber

Definition at line 43 of file STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/main.c.

Referenced by CEC_IRQHandler(), and main().

CEC_InitTypeDef CEC_InitStructure

Definition at line 41 of file STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/main.c.

Referenced by HDMI_CEC_Init().

uint8_t HeaderBlockValueToSend = 0

Definition at line 47 of file STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.c.

Referenced by EXTI9_5_IRQHandler().

uint8_t InitiatorAddress = 0

Definition at line 48 of file STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.c.

Referenced by CEC_IRQHandler().

uint8_t rcv_inc = 0

Definition at line 46 of file STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.c.

Referenced by CEC_IRQHandler().

uint8_t ReceiveBuffer[10]

Definition at line 41 of file STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.c.

Referenced by CEC_IRQHandler(), and main().

uint8_t ReceiveBuffer[10]

Definition at line 41 of file STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.c.

Referenced by CEC_IRQHandler(), and main().

__IO uint8_t ReceivedFrame = 0

Definition at line 45 of file STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.c.

__IO uint8_t ReceivedFrame

Definition at line 45 of file STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.c.

Referenced by CEC_IRQHandler(), HDMI_CEC_ProcessIRQSrc(), and main().

uint8_t RecepErrorCode = 0

Definition at line 50 of file STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.c.

Referenced by CEC_IRQHandler(), and HDMI_CEC_ProcessIRQSrc().

uint8_t send_inc = 0

Definition at line 46 of file STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.c.

Referenced by CEC_IRQHandler().

uint8_t TransErrorCode = 0

Definition at line 49 of file STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.c.

Referenced by CEC_IRQHandler(), HDMI_CEC_ProcessIRQSrc(), and HDMI_CEC_TransmitMessage().

volatile TestStatus TransferStatus = FAILED

Definition at line 44 of file STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/main.c.

Referenced by main().

uint8_t TransmitBuffer[10]

Definition at line 43 of file STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.c.

Referenced by CEC_IRQHandler(), and main().

uint8_t TransmitBuffer[10]
Initial value:
 {0xDF, 0x12, 0xD3, 0x56, 0x97,
                              0xA1, 0xEC, 0x7B, 0x4F, 0x22}

Definition at line 43 of file STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.c.

Referenced by CEC_IRQHandler(), and main().


STM32F10x Standard Peripherals Firmware Library: CortexM3_BitBand

Defines | Functions | Variables

CortexM3_BitBand

STM32F10x_StdPeriph_Examples

Defines

#define | RAM_BASE 0x20000000
#define | RAM_BB_BASE 0x22000000
#define | Var_GetBit_BB(VarAddr, BitNumber) (*(__IO uint32_t *) (RAM_BB_BASE | ((VarAddr - RAM_BASE) << 5) | ((BitNumber) << 2)))
#define | Var_ResetBit_BB(VarAddr, BitNumber) (*(__IO uint32_t *) (RAM_BB_BASE | ((VarAddr - RAM_BASE) << 5) | ((BitNumber) << 2)) = 0)
#define | Var_SetBit_BB(VarAddr, BitNumber) (*(__IO uint32_t *) (RAM_BB_BASE | ((VarAddr - RAM_BASE) << 5) | ((BitNumber) << 2)) = 1)

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

__IO uint32_t | Var
__IO uint32_t | VarAddr = 0
__IO uint32_t | VarBitValue = 0

Define Documentation

#define RAM_BASE 0x20000000

Definition at line 35 of file STM32F10x_StdPeriph_Examples/CortexM3/BitBand/main.c.

#define RAM_BB_BASE 0x22000000

Definition at line 36 of file STM32F10x_StdPeriph_Examples/CortexM3/BitBand/main.c.

#define Var_GetBit_BB | ( | VarAddr,
 |  | BitNumber
 | ) | (*(__IO uint32_t *) (RAM_BB_BASE | ((VarAddr - RAM_BASE) << 5) | ((BitNumber) << 2)))

Definition at line 45 of file STM32F10x_StdPeriph_Examples/CortexM3/BitBand/main.c.

Referenced by main().

#define Var_ResetBit_BB | ( | VarAddr,
 |  | BitNumber
 | ) | (*(__IO uint32_t *) (RAM_BB_BASE | ((VarAddr - RAM_BASE) << 5) | ((BitNumber) << 2)) = 0)

Definition at line 39 of file STM32F10x_StdPeriph_Examples/CortexM3/BitBand/main.c.

Referenced by main().

#define Var_SetBit_BB | ( | VarAddr,
 |  | BitNumber
 | ) | (*(__IO uint32_t *) (RAM_BB_BASE | ((VarAddr - RAM_BASE) << 5) | ((BitNumber) << 2)) = 1)

Definition at line 42 of file STM32F10x_StdPeriph_Examples/CortexM3/BitBand/main.c.

Referenced by main().

Function Documentation

void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 86 of file STM32F10x_StdPeriph_Examples/CortexM3/BitBand/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 121 of file STM32F10x_StdPeriph_Examples/CortexM3/BitBand/stm32f10x_it.c.

void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 60 of file STM32F10x_StdPeriph_Examples/CortexM3/BitBand/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 60 of file STM32F10x_StdPeriph_Examples/CortexM3/BitBand/main.c.

References Var, Var_GetBit_BB, Var_ResetBit_BB, Var_SetBit_BB, VarAddr, and VarBitValue.

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 73 of file STM32F10x_StdPeriph_Examples/CortexM3/BitBand/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 51 of file STM32F10x_StdPeriph_Examples/CortexM3/BitBand/stm32f10x_it.c.

void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 130 of file STM32F10x_StdPeriph_Examples/CortexM3/BitBand/stm32f10x_it.c.

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 112 of file STM32F10x_StdPeriph_Examples/CortexM3/BitBand/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 139 of file STM32F10x_StdPeriph_Examples/CortexM3/BitBand/stm32f10x_it.c.

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 99 of file STM32F10x_StdPeriph_Examples/CortexM3/BitBand/stm32f10x_it.c.

Variable Documentation

__IO uint32_t Var

Definition at line 50 of file STM32F10x_StdPeriph_Examples/CortexM3/BitBand/main.c.

Referenced by main().

__IO uint32_t VarAddr = 0

Definition at line 50 of file STM32F10x_StdPeriph_Examples/CortexM3/BitBand/main.c.

Referenced by main().

__IO uint32_t VarBitValue = 0

Definition at line 50 of file STM32F10x_StdPeriph_Examples/CortexM3/BitBand/main.c.

Referenced by main().


STM32F10x Standard Peripherals Firmware Library: CortexM3_Mode_Privilege

Defines | Functions | Variables

CortexM3_Mode_Privilege

STM32F10x_StdPeriph_Examples

Defines

#define | SP_MAIN 0x00
#define | SP_PROCESS 0x02
#define | SP_PROCESS_SIZE 0x200
#define | THREAD_MODE_PRIVILEGED 0x00
#define | THREAD_MODE_UNPRIVILEGED 0x01

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

__IO uint32_t | CurrentStack = 0
__IO uint32_t | Index = 0
__IO uint8_t | PSPMemAlloc [SP_PROCESS_SIZE]
__IO uint32_t | PSPValue = 0
__IO uint32_t | ThreadMode = 0

Define Documentation

#define SP_MAIN 0x00

Definition at line 37 of file STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/main.c.

Referenced by main().

#define SP_PROCESS 0x02

Definition at line 36 of file STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/main.c.

Referenced by main().

#define SP_PROCESS_SIZE 0x200

Definition at line 35 of file STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/main.c.

Referenced by main().

#define THREAD_MODE_PRIVILEGED 0x00

Definition at line 38 of file STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/main.c.

Referenced by main().

#define THREAD_MODE_UNPRIVILEGED 0x01

Definition at line 39 of file STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/main.c.

Referenced by main().

Function Documentation

void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 86 of file STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 112 of file STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f10x_it.c.

void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 60 of file STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 67 of file STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/main.c.

References CurrentStack, Index, PSPMemAlloc, PSPValue, SP_MAIN, SP_PROCESS, SP_PROCESS_SIZE, THREAD_MODE_PRIVILEGED, THREAD_MODE_UNPRIVILEGED, and ThreadMode.

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 73 of file STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 51 of file STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f10x_it.c.

void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 132 of file STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f10x_it.c.

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 121 of file STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 141 of file STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f10x_it.c.

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 99 of file STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f10x_it.c.

Variable Documentation

__IO uint32_t CurrentStack = 0

Definition at line 57 of file STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/main.c.

Referenced by main().

__IO uint32_t Index = 0

Definition at line 57 of file STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/main.c.

__IO uint8_t PSPMemAlloc[SP_PROCESS_SIZE]

Definition at line 56 of file STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/main.c.

Referenced by main().

__IO uint32_t PSPValue = 0

Definition at line 57 of file STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/main.c.

Referenced by main().

__IO uint32_t ThreadMode = 0

Definition at line 57 of file STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/main.c.

Referenced by main().


STM32F10x Standard Peripherals Firmware Library: CortexM3_MPU

Defines | Functions

CortexM3_MPU

STM32F10x_StdPeriph_Examples

Defines

#define | ACCESS_PERMISSION
#define | ARRAY_ADDRESS_START (0x20002000UL)
#define | ARRAY_REGION_NUMBER (0x03UL << MPU_RNR_REGION_Pos)
#define | ARRAY_SIZE (0x09UL << 0UL)

Functions

void | accesspermission (void)
This function configure the access right using Cortex-M3 MPU regions.
void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | MPU_SETUP (void)
Configures the main MPU regions.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Define Documentation

#define ACCESS_PERMISSION

Definition at line 37 of file STM32F10x_StdPeriph_Examples/CortexM3/MPU/main.c.

#define ARRAY_ADDRESS_START (0x20002000UL)

Definition at line 36 of file accesspermission.c.

Referenced by accesspermission().

#define ARRAY_REGION_NUMBER (0x03UL << MPU_RNR_REGION_Pos)

Definition at line 38 of file accesspermission.c.

Referenced by accesspermission().

#define ARRAY_SIZE (0x09UL << 0UL)

Definition at line 37 of file accesspermission.c.

Referenced by accesspermission().

Function Documentation

void accesspermission ( void )

This function configure the access right using Cortex-M3 MPU regions.

Parameters:
None
Return values:
None

Definition at line 63 of file accesspermission.c.

References ARRAY_ADDRESS_START, ARRAY_REGION_NUMBER, ARRAY_SIZE, and portMPU_REGION_PRIVILEGED_READ_ONLY.

Referenced by main().

void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 88 of file STM32F10x_StdPeriph_Examples/CortexM3/MPU/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 114 of file STM32F10x_StdPeriph_Examples/CortexM3/MPU/stm32f10x_it.c.

void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 61 of file STM32F10x_StdPeriph_Examples/CortexM3/MPU/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 50 of file STM32F10x_StdPeriph_Examples/CortexM3/MPU/main.c.

References accesspermission(), LED1, LED2, MPU_SETUP(), STM_EVAL_LEDInit(), and STM_EVAL_LEDOn().

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 74 of file STM32F10x_StdPeriph_Examples/CortexM3/MPU/stm32f10x_it.c.

References LED2, and STM_EVAL_LEDOn().

void MPU_SETUP ( void )

Configures the main MPU regions.

Parameters:
None
Return values:
None

Definition at line 84 of file STM32F10x_StdPeriph_Examples/CortexM3/MPU/main.c.

References FLASH_ADDRESS_START, FLASH_REGION_NUMBER, FLASH_SIZE, PERIPH_ADDRESS_START, PERIPH_REGION_NUMBER, PERIPH_SIZE, portMPU_REGION_READ_WRITE, RAM_ADDRESS_START, RAM_REGION_NUMBER, and RAM_SIZE.

Referenced by main().

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 52 of file STM32F10x_StdPeriph_Examples/CortexM3/MPU/stm32f10x_it.c.

void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 132 of file STM32F10x_StdPeriph_Examples/CortexM3/MPU/stm32f10x_it.c.

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 123 of file STM32F10x_StdPeriph_Examples/CortexM3/MPU/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 141 of file STM32F10x_StdPeriph_Examples/CortexM3/MPU/stm32f10x_it.c.

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 101 of file STM32F10x_StdPeriph_Examples/CortexM3/MPU/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: CRC_Calculation

Defines | Functions | Variables

CRC_Calculation

STM32F10x_StdPeriph_Examples

Defines

#define | BUFFER_SIZE 114

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

__IO uint32_t | CRCValue = 0
static const uint32_t | DataBuffer [BUFFER_SIZE]

Define Documentation

#define BUFFER_SIZE 114

Definition at line 35 of file STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/main.c.

Referenced by main().

Function Documentation

void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 86 of file STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 121 of file STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/stm32f10x_it.c.

void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 60 of file STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 74 of file STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/main.c.

References BUFFER_SIZE, CRC_CalcBlockCRC(), CRCValue, DataBuffer, ENABLE, RCC_AHBPeriph_CRC, and RCC_AHBPeriphClockCmd().

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 73 of file STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 51 of file STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/stm32f10x_it.c.

void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 130 of file STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/stm32f10x_it.c.

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 112 of file STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 139 of file STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/stm32f10x_it.c.

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 99 of file STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/stm32f10x_it.c.

Variable Documentation

__IO uint32_t CRCValue = 0

Definition at line 62 of file STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/main.c.

Referenced by main().

const uint32_t DataBuffer[BUFFER_SIZE] [static]
Initial value:
  {
    0x00001021, 0x20423063, 0x408450a5, 0x60c670e7, 0x9129a14a, 0xb16bc18c,
    0xd1ade1ce, 0xf1ef1231, 0x32732252, 0x52b54294, 0x72f762d6, 0x93398318,
    0xa35ad3bd, 0xc39cf3ff, 0xe3de2462, 0x34430420, 0x64e674c7, 0x44a45485,
    0xa56ab54b, 0x85289509, 0xf5cfc5ac, 0xd58d3653, 0x26721611, 0x063076d7,
    0x569546b4, 0xb75ba77a, 0x97198738, 0xf7dfe7fe, 0xc7bc48c4, 0x58e56886,
    0x78a70840, 0x18612802, 0xc9ccd9ed, 0xe98ef9af, 0x89489969, 0xa90ab92b,
    0x4ad47ab7, 0x6a961a71, 0x0a503a33, 0x2a12dbfd, 0xfbbfeb9e, 0x9b798b58,
    0xbb3bab1a, 0x6ca67c87, 0x5cc52c22, 0x3c030c60, 0x1c41edae, 0xfd8fcdec,
    0xad2abd0b, 0x8d689d49, 0x7e976eb6, 0x5ed54ef4, 0x2e321e51, 0x0e70ff9f,
    0xefbedfdd, 0xcffcbf1b, 0x9f598f78, 0x918881a9, 0xb1caa1eb, 0xd10cc12d,
    0xe16f1080, 0x00a130c2, 0x20e35004, 0x40257046, 0x83b99398, 0xa3fbb3da,
    0xc33dd31c, 0xe37ff35e, 0x129022f3, 0x32d24235, 0x52146277, 0x7256b5ea,
    0x95a88589, 0xf56ee54f, 0xd52cc50d, 0x34e224c3, 0x04817466, 0x64475424,
    0x4405a7db, 0xb7fa8799, 0xe75ff77e, 0xc71dd73c, 0x26d336f2, 0x069116b0,
    0x76764615, 0x5634d94c, 0xc96df90e, 0xe92f99c8, 0xb98aa9ab, 0x58444865,
    0x78066827, 0x18c008e1, 0x28a3cb7d, 0xdb5ceb3f, 0xfb1e8bf9, 0x9bd8abbb,
    0x4a755a54, 0x6a377a16, 0x0af11ad0, 0x2ab33a92, 0xed0fdd6c, 0xcd4dbdaa,
    0xad8b9de8, 0x8dc97c26, 0x5c644c45, 0x3ca22c83, 0x1ce00cc1, 0xef1fff3e,
    0xdf7caf9b, 0xbfba8fd9, 0x9ff86e17, 0x7e364e55, 0x2e933eb2, 0x0ed11ef0
  }

Definition at line 39 of file STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/main.c.

Referenced by main().


STM32F10x Standard Peripherals Firmware Library: DAC_DualModeDMA_SineWave

Defines | Functions | Variables

DAC_DualModeDMA_SineWave

STM32F10x_StdPeriph_Examples

Defines

#define | DAC_DHR12RD_Address 0x40007420

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | Delay (__IO uint32_t nCount)
Inserts a delay time.
void | GPIO_Configuration (void)
Configures the different GPIO ports.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | RCC_Configuration (void)
Configures the different system clocks.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

DAC_InitTypeDef DAC_InitStructure
DMA_InitTypeDef DMA_InitStructure
uint32_t | DualSine12bit [32]
uint32_t | Idx = 0
const uint16_t | Sine12bit [32]
TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure

Define Documentation

#define DAC_DHR12RD_Address 0x40007420

Definition at line 35 of file STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/main.c.

Referenced by main().

Function Documentation

void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 86 of file STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 121 of file STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/stm32f10x_it.c.

void Delay ( __IO uint32_t nCount )

Inserts a delay time.

Parameters:
nCount,: specifies the delay time length.
Return values:
None
void GPIO_Configuration ( void )

Configures the different GPIO ports.

Parameters:
None
Return values:
None

Definition at line 222 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 60 of file STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 64 of file STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/main.c.

References DAC_Channel_1, DAC_Channel_2, DAC_Cmd(), DAC_DHR12RD_Address, DAC_DMACmd(), DAC_Init(), DAC_InitTypeDef::DAC_OutputBuffer, DAC_OutputBuffer_Disable, DAC_InitTypeDef::DAC_Trigger, DAC_Trigger_T2_TRGO, DAC_InitTypeDef::DAC_WaveGeneration, DAC_WaveGeneration_None, DMA1_Channel4, DMA2_Channel4, DMA_InitTypeDef::DMA_BufferSize, DMA_Cmd(), DMA_DeInit(), DMA_InitTypeDef::DMA_DIR, DMA_DIR_PeripheralDST, DMA_Init(), DMA_InitTypeDef::DMA_M2M, DMA_M2M_Disable, DMA_InitTypeDef::DMA_MemoryBaseAddr, DMA_InitTypeDef::DMA_MemoryDataSize, DMA_MemoryDataSize_Word, DMA_InitTypeDef::DMA_MemoryInc, DMA_MemoryInc_Enable, DMA_InitTypeDef::DMA_Mode, DMA_Mode_Circular, DMA_InitTypeDef::DMA_PeripheralBaseAddr, DMA_InitTypeDef::DMA_PeripheralDataSize, DMA_PeripheralDataSize_Word, DMA_InitTypeDef::DMA_PeripheralInc, DMA_PeripheralInc_Disable, DMA_InitTypeDef::DMA_Priority, DMA_Priority_High, DualSine12bit, ENABLE, GPIO_Configuration(), Idx, RCC_Configuration(), Sine12bit, TIM2, TIM_TimeBaseInitTypeDef::TIM_ClockDivision, TIM_Cmd(), TIM_TimeBaseInitTypeDef::TIM_CounterMode, TIM_CounterMode_Up, TIM_TimeBaseInitTypeDef::TIM_Period, TIM_TimeBaseInitTypeDef::TIM_Prescaler, TIM_SelectOutputTrigger(), TIM_TimeBaseInit(), TIM_TimeBaseStructInit(), and TIM_TRGOSource_Update.

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 73 of file STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 51 of file STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/stm32f10x_it.c.

void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 130 of file STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/stm32f10x_it.c.

void RCC_Configuration ( void )

Configures the different system clocks.

Parameters:
None
Return values:
None

Definition at line 203 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 112 of file STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 139 of file STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/stm32f10x_it.c.

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 99 of file STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/stm32f10x_it.c.

Variable Documentation

DAC_InitTypeDef DAC_InitStructure

Definition at line 38 of file STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/main.c.

DMA_InitTypeDef DMA_InitStructure

Definition at line 39 of file STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/main.c.

uint32_t DualSine12bit[32]

Definition at line 50 of file STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/main.c.

Referenced by main().

uint32_t Idx = 0

Definition at line 41 of file STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/main.c.

Referenced by main().

const uint16_t Sine12bit[32]
Initial value:
 {
                      2047, 2447, 2831, 3185, 3498, 3750, 3939, 4056, 4095, 4056,
                      3939, 3750, 3495, 3185, 2831, 2447, 2047, 1647, 1263, 909,
                      599, 344, 155, 38, 0, 38, 155, 344, 599, 909, 1263, 1647}

Definition at line 45 of file STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/main.c.

Referenced by main().

TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure

Definition at line 40 of file STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/main.c.


STM32F10x Standard Peripherals Firmware Library: DAC_OneChannel_NoiseWave

Functions | Variables

DAC_OneChannel_NoiseWave

STM32F10x_StdPeriph_Examples

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | Delay (__IO uint32_t nCount)
Inserts a delay time.
void | GPIO_Configuration (void)
Configures the different GPIO ports.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | RCC_Configuration (void)
Configures the different system clocks.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

DAC_InitTypeDef DAC_InitStructure

Function Documentation

void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 86 of file STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 121 of file STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/stm32f10x_it.c.

void Delay ( __IO uint32_t nCount )

Inserts a delay time.

Parameters:
nCount,: specifies the delay time length.
Return values:
None
void GPIO_Configuration ( void )

Configures the different GPIO ports.

Parameters:
None
Return values:
None

Definition at line 222 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 60 of file STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 52 of file STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/main.c.

References DAC_Align_12b_L, DAC_Channel_1, DAC_Cmd(), DAC_Init(), DAC_LFSRUnmask_Bits8_0, DAC_InitTypeDef::DAC_LFSRUnmask_TriangleAmplitude, DAC_InitTypeDef::DAC_OutputBuffer, DAC_OutputBuffer_Enable, DAC_SetChannel1Data(), DAC_SoftwareTriggerCmd(), DAC_InitTypeDef::DAC_Trigger, DAC_Trigger_Software, DAC_InitTypeDef::DAC_WaveGeneration, DAC_WaveGeneration_Noise, ENABLE, GPIO_Configuration(), and RCC_Configuration().

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 73 of file STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 51 of file STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/stm32f10x_it.c.

void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 130 of file STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/stm32f10x_it.c.

void RCC_Configuration ( void )

Configures the different system clocks.

Parameters:
None
Return values:
None

Definition at line 203 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 112 of file STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 139 of file STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/stm32f10x_it.c.

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 99 of file STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/stm32f10x_it.c.

Variable Documentation

DAC_InitTypeDef DAC_InitStructure

Definition at line 36 of file STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/main.c.


STM32F10x Standard Peripherals Firmware Library: DAC_OneChannelDMA_Escalator

Defines | Functions | Variables

DAC_OneChannelDMA_Escalator

STM32F10x_StdPeriph_Examples

Defines

#define | DAC_DHR8R1_Address 0x40007410

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | Delay (__IO uint32_t nCount)
Inserts a delay time.
void | GPIO_Configuration (void)
Configures the different GPIO ports.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | RCC_Configuration (void)
Configures the different system clocks.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

DAC_InitTypeDef DAC_InitStructure
DMA_InitTypeDef DMA_InitStructure
const uint8_t | Escalator8bit [6] = {0x0, 0x33, 0x66, 0x99, 0xCC, 0xFF}

Define Documentation

#define DAC_DHR8R1_Address 0x40007410

Definition at line 35 of file STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/main.c.

Referenced by main().

Function Documentation

void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 86 of file STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 121 of file STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/stm32f10x_it.c.

void Delay ( __IO uint32_t nCount )

Inserts a delay time.

Parameters:
nCount,: specifies the delay time length.
Return values:
None
void GPIO_Configuration ( void )

Configures the different GPIO ports.

Parameters:
None
Return values:
None

Definition at line 222 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 60 of file STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 57 of file STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/main.c.

References DAC_Channel_1, DAC_Cmd(), DAC_DHR8R1_Address, DAC_DMACmd(), DAC_Init(), DAC_InitTypeDef::DAC_OutputBuffer, DAC_OutputBuffer_Disable, DAC_InitTypeDef::DAC_Trigger, DAC_Trigger_T6_TRGO, DAC_InitTypeDef::DAC_WaveGeneration, DAC_WaveGeneration_None, DMA1_Channel3, DMA2_Channel3, DMA_InitTypeDef::DMA_BufferSize, DMA_Cmd(), DMA_DeInit(), DMA_InitTypeDef::DMA_DIR, DMA_DIR_PeripheralDST, DMA_Init(), DMA_InitTypeDef::DMA_M2M, DMA_M2M_Disable, DMA_InitTypeDef::DMA_MemoryBaseAddr, DMA_InitTypeDef::DMA_MemoryDataSize, DMA_MemoryDataSize_Byte, DMA_InitTypeDef::DMA_MemoryInc, DMA_MemoryInc_Enable, DMA_InitTypeDef::DMA_Mode, DMA_Mode_Circular, DMA_InitTypeDef::DMA_PeripheralBaseAddr, DMA_InitTypeDef::DMA_PeripheralDataSize, DMA_PeripheralDataSize_Byte, DMA_InitTypeDef::DMA_PeripheralInc, DMA_PeripheralInc_Disable, DMA_InitTypeDef::DMA_Priority, DMA_Priority_High, ENABLE, Escalator8bit, GPIO_Configuration(), RCC_Configuration(), TIM6, TIM_Cmd(), TIM_PrescalerConfig(), TIM_PSCReloadMode_Update, TIM_SelectOutputTrigger(), TIM_SetAutoreload(), and TIM_TRGOSource_Update.

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 73 of file STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 51 of file STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/stm32f10x_it.c.

void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 130 of file STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/stm32f10x_it.c.

void RCC_Configuration ( void )

Configures the different system clocks.

Parameters:
None
Return values:
None

Definition at line 203 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 112 of file STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 139 of file STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/stm32f10x_it.c.

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 99 of file STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/stm32f10x_it.c.

Variable Documentation

DAC_InitTypeDef DAC_InitStructure

Definition at line 38 of file STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/main.c.

DMA_InitTypeDef DMA_InitStructure

Definition at line 39 of file STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/main.c.

const uint8_t Escalator8bit[6] = {0x0, 0x33, 0x66, 0x99, 0xCC, 0xFF}

Definition at line 43 of file STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/main.c.

Referenced by main().


STM32F10x Standard Peripherals Firmware Library: DAC_TwoChannels_TriangleWave

Functions | Variables

DAC_TwoChannels_TriangleWave

STM32F10x_StdPeriph_Examples

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | Delay (__IO uint32_t nCount)
Inserts a delay time.
void | GPIO_Configuration (void)
Configures the different GPIO ports.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | RCC_Configuration (void)
Configures the different system clocks.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

DAC_InitTypeDef DAC_InitStructure
TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure

Function Documentation

void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 87 of file STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 122 of file STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/stm32f10x_it.c.

void Delay ( __IO uint32_t nCount )

Inserts a delay time.

Parameters:
nCount,: specifies the delay time length.
Return values:
None
void GPIO_Configuration ( void )

Configures the different GPIO ports.

Parameters:
None
Return values:
None

Definition at line 222 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 61 of file STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 53 of file STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/main.c.

References DAC_Align_12b_R, DAC_Channel_1, DAC_Channel_2, DAC_Cmd(), DAC_Init(), DAC_InitTypeDef::DAC_LFSRUnmask_TriangleAmplitude, DAC_InitTypeDef::DAC_OutputBuffer, DAC_OutputBuffer_Disable, DAC_SetDualChannelData(), DAC_TriangleAmplitude_1023, DAC_TriangleAmplitude_2047, DAC_InitTypeDef::DAC_Trigger, DAC_Trigger_T2_TRGO, DAC_InitTypeDef::DAC_WaveGeneration, DAC_WaveGeneration_Triangle, ENABLE, GPIO_Configuration(), RCC_Configuration(), TIM2, TIM_TimeBaseInitTypeDef::TIM_ClockDivision, TIM_Cmd(), TIM_TimeBaseInitTypeDef::TIM_CounterMode, TIM_CounterMode_Up, TIM_TimeBaseInitTypeDef::TIM_Period, TIM_TimeBaseInitTypeDef::TIM_Prescaler, TIM_SelectOutputTrigger(), TIM_TimeBaseInit(), TIM_TimeBaseStructInit(), and TIM_TRGOSource_Update.

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 74 of file STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 52 of file STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/stm32f10x_it.c.

void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 131 of file STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/stm32f10x_it.c.

void RCC_Configuration ( void )

Configures the different system clocks.

Parameters:
None
Return values:
None

Definition at line 203 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 113 of file STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 140 of file STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/stm32f10x_it.c.

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 100 of file STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/stm32f10x_it.c.

Variable Documentation

DAC_InitTypeDef DAC_InitStructure

Definition at line 36 of file STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/main.c.

TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure

Definition at line 37 of file STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/main.c.


STM32F10x Standard Peripherals Firmware Library: DMA_ADC_TIM1

Defines | Functions | Variables

DMA_ADC_TIM1

STM32F10x_StdPeriph_Examples

Defines

#define | ADC1_DR_Address 0x4001244C
#define | TIM1_CCR1_Address 0x40012C34

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | GPIO_Configuration (void)
Configures the different GPIO ports.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | RCC_Configuration (void)
Configures the different system clocks.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

ADC_InitTypeDef ADC_InitStructure
DMA_InitTypeDef DMA_InitStructure
TIM_OCInitTypeDef TIM_OCInitStructure
TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure

Define Documentation

#define ADC1_DR_Address 0x4001244C

Definition at line 35 of file STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/main.c.

Referenced by main().

#define TIM1_CCR1_Address 0x40012C34

Definition at line 36 of file STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/main.c.

Referenced by main().

Function Documentation

void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 88 of file STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 123 of file STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/stm32f10x_it.c.

void GPIO_Configuration ( void )

Configures the different GPIO ports.

Parameters:
None
Return values:
None

Definition at line 222 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 62 of file STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 56 of file STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/main.c.

References ADC1, ADC1_DR_Address, ADC_Channel_14, ADC_Cmd(), ADC_InitTypeDef::ADC_ContinuousConvMode, ADC_InitTypeDef::ADC_DataAlign, ADC_DataAlign_Right, ADC_InitTypeDef::ADC_ExternalTrigConv, ADC_ExternalTrigConv_None, ADC_GetCalibrationStatus(), ADC_GetResetCalibrationStatus(), ADC_Init(), ADC_InitTypeDef::ADC_Mode, ADC_Mode_Independent, ADC_InitTypeDef::ADC_NbrOfChannel, ADC_RegularChannelConfig(), ADC_ResetCalibration(), ADC_SampleTime_55Cycles5, ADC_InitTypeDef::ADC_ScanConvMode, ADC_SoftwareStartConvCmd(), ADC_StartCalibration(), DISABLE, DMA1_Channel5, DMA_InitTypeDef::DMA_BufferSize, DMA_Cmd(), DMA_DeInit(), DMA_InitTypeDef::DMA_DIR, DMA_DIR_PeripheralDST, DMA_Init(), DMA_InitTypeDef::DMA_M2M, DMA_M2M_Disable, DMA_InitTypeDef::DMA_MemoryBaseAddr, DMA_InitTypeDef::DMA_MemoryDataSize, DMA_MemoryDataSize_HalfWord, DMA_InitTypeDef::DMA_MemoryInc, DMA_MemoryInc_Disable, DMA_InitTypeDef::DMA_Mode, DMA_Mode_Circular, DMA_InitTypeDef::DMA_PeripheralBaseAddr, DMA_InitTypeDef::DMA_PeripheralDataSize, DMA_PeripheralDataSize_HalfWord, DMA_InitTypeDef::DMA_PeripheralInc, DMA_PeripheralInc_Disable, DMA_InitTypeDef::DMA_Priority, DMA_Priority_High, ENABLE, GPIO_Configuration(), RCC_Configuration(), TIM1, TIM1_CCR1_Address, TIM_TimeBaseInitTypeDef::TIM_ClockDivision, TIM_Cmd(), TIM_TimeBaseInitTypeDef::TIM_CounterMode, TIM_CounterMode_Up, TIM_CtrlPWMOutputs(), TIM_DMA_Update, TIM_DMACmd(), TIM_OC1Init(), TIM_OCInitTypeDef::TIM_OCMode, TIM_OCMode_PWM1, TIM_OCInitTypeDef::TIM_OCPolarity, TIM_OCPolarity_High, TIM_OCInitTypeDef::TIM_OutputState, TIM_OutputState_Enable, TIM_TimeBaseInitTypeDef::TIM_Period, TIM_TimeBaseInitTypeDef::TIM_Prescaler, TIM_TimeBaseInit(), and TIM_TimeBaseStructInit().

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 75 of file STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 51 of file STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/stm32f10x_it.c.

void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 132 of file STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/stm32f10x_it.c.

void RCC_Configuration ( void )

Configures the different system clocks.

Parameters:
None
Return values:
None

Definition at line 203 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 114 of file STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 141 of file STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/stm32f10x_it.c.

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 101 of file STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/stm32f10x_it.c.

Variable Documentation

ADC_InitTypeDef ADC_InitStructure

Definition at line 40 of file STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/main.c.

DMA_InitTypeDef DMA_InitStructure

Definition at line 43 of file STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/main.c.

TIM_OCInitTypeDef TIM_OCInitStructure

Definition at line 42 of file STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/main.c.

TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure

Definition at line 41 of file STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/main.c.


STM32F10x Standard Peripherals Firmware Library: DMA_FLASH_RAM

Defines | Enumerations | Functions | Variables

DMA_FLASH_RAM

STM32F10x_StdPeriph_Examples

Defines

#define | BufferSize 32

Enumerations

enum TestStatus {
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED
}

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | DMA1_Channel6_IRQHandler (void)
This function handles DMA1 Channel 6 interrupt request.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | NVIC_Configuration (void)
Configure the nested vectored interrupt controller.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | RCC_Configuration (void)
Configures the different system clocks.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

__IO uint32_t | CurrDataCounterBegin = 0
__IO uint16_t | CurrDataCounterEnd
__IO uint32_t | CurrDataCounterEnd = 0x01
DMA_InitTypeDef DMA_InitStructure
uint32_t | DST_Buffer [BufferSize]
const uint32_t | SRC_Const_Buffer [BufferSize]
TestStatus | TransferStatus = FAILED

Define Documentation

#define BufferSize 32

Definition at line 37 of file STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/main.c.

Referenced by main().

Enumeration Type Documentation

enum TestStatus
Enumerator:
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED

Definition at line 34 of file STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/main.c.

Function Documentation

void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 88 of file STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 123 of file STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/stm32f10x_it.c.

void DMA1_Channel6_IRQHandler ( void )

This function handles DMA1 Channel 6 interrupt request.

Parameters:
None
Return values:
None

Definition at line 154 of file STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/stm32f10x_it.c.

void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 62 of file STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 69 of file STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/main.c.

References Buffercmp(), BufferSize, CurrDataCounterBegin, CurrDataCounterEnd, DMA1_Channel6, DMA_InitTypeDef::DMA_BufferSize, DMA_Cmd(), DMA_DeInit(), DMA_InitTypeDef::DMA_DIR, DMA_DIR_PeripheralSRC, DMA_GetCurrDataCounter(), DMA_Init(), DMA_IT_TC, DMA_ITConfig(), DMA_InitTypeDef::DMA_M2M, DMA_M2M_Enable, DMA_InitTypeDef::DMA_MemoryBaseAddr, DMA_InitTypeDef::DMA_MemoryDataSize, DMA_MemoryDataSize_Word, DMA_InitTypeDef::DMA_MemoryInc, DMA_MemoryInc_Enable, DMA_InitTypeDef::DMA_Mode, DMA_Mode_Normal, DMA_InitTypeDef::DMA_PeripheralBaseAddr, DMA_InitTypeDef::DMA_PeripheralDataSize, DMA_PeripheralDataSize_Word, DMA_InitTypeDef::DMA_PeripheralInc, DMA_PeripheralInc_Enable, DMA_InitTypeDef::DMA_Priority, DMA_Priority_High, DST_Buffer, ENABLE, NVIC_Configuration(), RCC_Configuration(), SRC_Const_Buffer, and TransferStatus.

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 75 of file STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 53 of file STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/stm32f10x_it.c.

void NVIC_Configuration ( void )

Configure the nested vectored interrupt controller.

Parameters:
None
Return values:
None
void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 132 of file STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/stm32f10x_it.c.

void RCC_Configuration ( void )

Configures the different system clocks.

Parameters:
None
Return values:
None

Definition at line 203 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 114 of file STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 141 of file STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/stm32f10x_it.c.

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 101 of file STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/stm32f10x_it.c.

Variable Documentation

__IO uint32_t CurrDataCounterBegin = 0

Definition at line 42 of file STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/main.c.

Referenced by main().

__IO uint16_t CurrDataCounterEnd

Definition at line 43 of file STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/main.c.

Referenced by DMA1_Channel6_IRQHandler(), and main().

__IO uint32_t CurrDataCounterEnd = 0x01

Definition at line 43 of file STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/main.c.

Referenced by DMA1_Channel6_IRQHandler(), and main().

DMA_InitTypeDef DMA_InitStructure

Definition at line 41 of file STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/main.c.

uint32_t DST_Buffer[BufferSize]

Definition at line 55 of file STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/main.c.

Referenced by DMA1_Channel5_IRQHandler(), DMA1_Channel6_IRQHandler(), DMA_Configuration(), and main().

const uint32_t SRC_Const_Buffer[BufferSize]
Initial value:
 {
                                    0x01020304,0x05060708,0x090A0B0C,0x0D0E0F10,
                                    0x11121314,0x15161718,0x191A1B1C,0x1D1E1F20,
                                    0x21222324,0x25262728,0x292A2B2C,0x2D2E2F30,
                                    0x31323334,0x35363738,0x393A3B3C,0x3D3E3F40,
                                    0x41424344,0x45464748,0x494A4B4C,0x4D4E4F50,
                                    0x51525354,0x55565758,0x595A5B5C,0x5D5E5F60,
                                    0x61626364,0x65666768,0x696A6B6C,0x6D6E6F70,
                                    0x71727374,0x75767778,0x797A7B7C,0x7D7E7F80}

Definition at line 46 of file STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/main.c.

Referenced by main().

TestStatus TransferStatus = FAILED

Definition at line 45 of file STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/main.c.


STM32F10x Standard Peripherals Firmware Library: DMA_FSMC

Defines | Enumerations | Functions | Variables

DMA_FSMC

STM32F10x_StdPeriph_Examples

Defines

#define | Bank1_SRAM3_ADDR ((uint32_t)0x68000000)
#define | BufferSize 32

Enumerations

enum TestStatus {
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED
}

Functions

TestStatus | Buffercmp (const uint32_t *pBuffer, uint32_t *pBuffer1, uint16_t BufferLength)
Compares two buffers.
void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | RCC_Configuration (void)
Configures the different system clocks.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

DMA_InitTypeDef DMA_InitStructure
uint8_t | DST_Buffer [4 *BufferSize]
uint32_t | Idx = 0
const uint32_t | SRC_Const_Buffer [BufferSize]
volatile TestStatus | TransferStatus

Define Documentation

#define Bank1_SRAM3_ADDR ((uint32_t)0x68000000)

Definition at line 42 of file STM32F10x_StdPeriph_Examples/DMA/FSMC/main.c.

Referenced by main().

#define BufferSize 32

Definition at line 41 of file STM32F10x_StdPeriph_Examples/DMA/FSMC/main.c.

Referenced by main().

Enumeration Type Documentation

enum TestStatus
Enumerator:
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED

Definition at line 38 of file STM32F10x_StdPeriph_Examples/DMA/FSMC/main.c.

Function Documentation

TestStatus Buffercmp | ( | const uint32_t * | pBuffer,
 |  | uint32_t * | pBuffer1,
 |  | uint16_t | BufferLength
 | ) |  |

Compares two buffers.

Parameters:
pBuffer,pBuffer1,: buffers to be compared.
BufferLength,: buffer's length
Return values:
PASSED,: pBuffer identical to pBuffer1 FAILED: pBuffer differs from pBuffer1
void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 86 of file STM32F10x_StdPeriph_Examples/DMA/FSMC/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 121 of file STM32F10x_StdPeriph_Examples/DMA/FSMC/stm32f10x_it.c.

void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 60 of file STM32F10x_StdPeriph_Examples/DMA/FSMC/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 71 of file STM32F10x_StdPeriph_Examples/DMA/FSMC/main.c.

References Bank1_SRAM3_ADDR, Buffercmp(), BufferSize, DMA1_Channel3, DMA1_FLAG_TC3, DMA2_Channel5, DMA2_FLAG_TC5, DMA_InitTypeDef::DMA_BufferSize, DMA_ClearFlag(), DMA_Cmd(), DMA_DeInit(), DMA_InitTypeDef::DMA_DIR, DMA_DIR_PeripheralSRC, DMA_GetFlagStatus(), DMA_Init(), DMA_InitTypeDef::DMA_M2M, DMA_M2M_Enable, DMA_InitTypeDef::DMA_MemoryBaseAddr, DMA_InitTypeDef::DMA_MemoryDataSize, DMA_MemoryDataSize_Byte, DMA_MemoryDataSize_Word, DMA_InitTypeDef::DMA_MemoryInc, DMA_MemoryInc_Enable, DMA_InitTypeDef::DMA_Mode, DMA_Mode_Normal, DMA_InitTypeDef::DMA_PeripheralBaseAddr, DMA_InitTypeDef::DMA_PeripheralDataSize, DMA_PeripheralDataSize_Byte, DMA_PeripheralDataSize_Word, DMA_InitTypeDef::DMA_PeripheralInc, DMA_PeripheralInc_Enable, DMA_InitTypeDef::DMA_Priority, DMA_Priority_High, DST_Buffer, ENABLE, Idx, RCC_Configuration(), SRAM_Init(), SRC_Const_Buffer, and TransferStatus.

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 73 of file STM32F10x_StdPeriph_Examples/DMA/FSMC/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 51 of file STM32F10x_StdPeriph_Examples/DMA/FSMC/stm32f10x_it.c.

void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 130 of file STM32F10x_StdPeriph_Examples/DMA/FSMC/stm32f10x_it.c.

void RCC_Configuration ( void )

Configures the different system clocks.

Parameters:
None
Return values:
None

Definition at line 203 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 112 of file STM32F10x_StdPeriph_Examples/DMA/FSMC/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 139 of file STM32F10x_StdPeriph_Examples/DMA/FSMC/stm32f10x_it.c.

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 99 of file STM32F10x_StdPeriph_Examples/DMA/FSMC/stm32f10x_it.c.

Variable Documentation

DMA_InitTypeDef DMA_InitStructure

Definition at line 46 of file STM32F10x_StdPeriph_Examples/DMA/FSMC/main.c.

uint8_t DST_Buffer[4 *BufferSize]

Definition at line 57 of file STM32F10x_StdPeriph_Examples/DMA/FSMC/main.c.

uint32_t Idx = 0

Definition at line 58 of file STM32F10x_StdPeriph_Examples/DMA/FSMC/main.c.

const uint32_t SRC_Const_Buffer[BufferSize]
Initial value:
 {
                            0x01020304,0x05060708,0x090A0B0C,0x0D0E0F10,
                            0x11121314,0x15161718,0x191A1B1C,0x1D1E1F20,
                            0x21222324,0x25262728,0x292A2B2C,0x2D2E2F30,
                            0x31323334,0x35363738,0x393A3B3C,0x3D3E3F40,
                            0x41424344,0x45464748,0x494A4B4C,0x4D4E4F50,
                            0x51525354,0x55565758,0x595A5B5C,0x5D5E5F60,
                            0x61626364,0x65666768,0x696A6B6C,0x6D6E6F70,
                            0x71727374,0x75767778,0x797A7B7C,0x7D7E7F80}

Definition at line 48 of file STM32F10x_StdPeriph_Examples/DMA/FSMC/main.c.

volatile TestStatus TransferStatus

Definition at line 47 of file STM32F10x_StdPeriph_Examples/DMA/FSMC/main.c.


STM32F10x Standard Peripherals Firmware Library: DMA_I2C_RAM

Defines | Enumerations | Functions | Variables

DMA_I2C_RAM

STM32F10x_StdPeriph_Examples

Defines

#define | BufferSize 8
#define | ClockSpeed 100000
#define | I2C1_DR_Address 0x40005410
#define | I2C1_SLAVE_ADDRESS7 0x30
#define | I2C2_DR_Address 0x40005810
#define | I2C2_SLAVE_ADDRESS7 0x30

Enumerations

enum TestStatus {
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED
}

Functions

TestStatus | Buffercmp (uint8_t *pBuffer, uint8_t *pBuffer1, uint16_t BufferLength)
Compares two buffers.
void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | GPIO_Configuration (void)
Configures the different GPIO ports.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | RCC_Configuration (void)
Configures the different system clocks.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

DMA_InitTypeDef DMA_InitStructure
uint8_t | I2C1_Buffer_Tx [BufferSize] = {1, 2, 3, 4, 5, 6, 7, 8}
uint8_t | I2C2_Buffer_Rx [BufferSize]
I2C_InitTypeDef I2C_InitStructure
uint8_t | Rx_Idx = 0
volatile TestStatus | TransferStatus
uint8_t | Tx_Idx = 0

Define Documentation

#define BufferSize 8

Definition at line 41 of file STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/main.c.

Referenced by main().

#define ClockSpeed 100000

Definition at line 42 of file STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/main.c.

Referenced by main().

#define I2C1_DR_Address 0x40005410

Definition at line 37 of file STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/main.c.

Referenced by main().

#define I2C1_SLAVE_ADDRESS7 0x30

Definition at line 39 of file STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/main.c.

Referenced by main().

#define I2C2_DR_Address 0x40005810

Definition at line 38 of file STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/main.c.

Referenced by main().

#define I2C2_SLAVE_ADDRESS7 0x30

Definition at line 40 of file STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/main.c.

Referenced by main().

Enumeration Type Documentation

enum TestStatus
Enumerator:
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED

Definition at line 34 of file STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/main.c.

Function Documentation

TestStatus Buffercmp | ( | uint8_t * | pBuffer,
 |  | uint8_t * | pBuffer1,
 |  | uint16_t | BufferLength
 | ) |  |

Compares two buffers.

Parameters:
pBuffer,pBuffer1,: buffers to be compared.
BufferLength,: buffer's length
Return values:
PASSED,: pBuffer identical to pBuffer1 FAILED: pBuffer differs from pBuffer1
void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 86 of file STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 121 of file STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/stm32f10x_it.c.

void GPIO_Configuration ( void )

Configures the different GPIO ports.

Parameters:
None
Return values:
None

Definition at line 222 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 60 of file STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 65 of file STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/main.c.

References Buffercmp(), BufferSize, ClockSpeed, DMA1_Channel5, DMA1_Channel6, DMA1_FLAG_TC5, DMA1_FLAG_TC6, DMA_InitTypeDef::DMA_BufferSize, DMA_Cmd(), DMA_DeInit(), DMA_InitTypeDef::DMA_DIR, DMA_DIR_PeripheralDST, DMA_DIR_PeripheralSRC, DMA_GetFlagStatus(), DMA_Init(), DMA_InitTypeDef::DMA_M2M, DMA_M2M_Disable, DMA_InitTypeDef::DMA_MemoryBaseAddr, DMA_InitTypeDef::DMA_MemoryDataSize, DMA_MemoryDataSize_Byte, DMA_InitTypeDef::DMA_MemoryInc, DMA_MemoryInc_Enable, DMA_InitTypeDef::DMA_Mode, DMA_Mode_Normal, DMA_InitTypeDef::DMA_PeripheralBaseAddr, DMA_InitTypeDef::DMA_PeripheralDataSize, DMA_InitTypeDef::DMA_PeripheralInc, DMA_PeripheralInc_Disable, DMA_InitTypeDef::DMA_Priority, DMA_Priority_High, DMA_Priority_VeryHigh, ENABLE, GPIO_Configuration(), I2C1, I2C1_Buffer_Tx, I2C1_DR_Address, I2C1_SLAVE_ADDRESS7, I2C2, I2C2_Buffer_Rx, I2C2_DR_Address, I2C2_SLAVE_ADDRESS7, I2C_InitTypeDef::I2C_Ack, I2C_Ack_Enable, I2C_InitTypeDef::I2C_AcknowledgedAddress, I2C_AcknowledgedAddress_7bit, I2C_CheckEvent(), I2C_InitTypeDef::I2C_ClockSpeed, I2C_Cmd(), I2C_Direction_Transmitter, I2C_DMACmd(), I2C_InitTypeDef::I2C_DutyCycle, I2C_DutyCycle_2, I2C_EVENT_MASTER_MODE_SELECT, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED, I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED, I2C_EVENT_SLAVE_STOP_DETECTED, I2C_FLAG_STOPF, I2C_GenerateSTART(), I2C_GenerateSTOP(), I2C_GetFlagStatus(), I2C_Init(), I2C_InitTypeDef::I2C_Mode, I2C_Mode_I2C, I2C_InitTypeDef::I2C_OwnAddress1, I2C_Send7bitAddress(), RCC_Configuration(), and TransferStatus.

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 73 of file STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 51 of file STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/stm32f10x_it.c.

void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 130 of file STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/stm32f10x_it.c.

void RCC_Configuration ( void )

Configures the different system clocks.

Parameters:
None
Return values:
None

Definition at line 203 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 112 of file STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 139 of file STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/stm32f10x_it.c.

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 99 of file STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/stm32f10x_it.c.

Variable Documentation

DMA_InitTypeDef DMA_InitStructure

Definition at line 47 of file STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/main.c.

uint8_t I2C1_Buffer_Tx[BufferSize] = {1, 2, 3, 4, 5, 6, 7, 8}

Definition at line 48 of file STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/main.c.

Referenced by main().

uint8_t I2C2_Buffer_Rx[BufferSize]

Definition at line 49 of file STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/main.c.

Referenced by main().

I2C_InitTypeDef I2C_InitStructure

Definition at line 46 of file STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/main.c.

Referenced by HDMI_CEC_Init(), IOE_I2C_Config(), LM75_Init(), and sEE_Init().

uint8_t Rx_Idx = 0

Definition at line 50 of file STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/main.c.

volatile TestStatus TransferStatus

Definition at line 51 of file STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/main.c.

uint8_t Tx_Idx = 0

Definition at line 50 of file STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/main.c.


STM32F10x Standard Peripherals Firmware Library: DMA_SPI_RAM

Defines | Enumerations | Functions | Variables

DMA_SPI_RAM

STM32F10x_StdPeriph_Examples

Defines

#define | BufferSize 32
#define | CRCPolynomial 7

Enumerations

enum TestStatus {
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED
}

Functions

TestStatus | Buffercmp (uint8_t *pBuffer, uint8_t *pBuffer1, uint16_t BufferLength)
Compares two buffers.
void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | GPIO_Configuration (void)
Configures the different GPIO ports.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | RCC_Configuration (void)
Configures the different system clocks.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

DMA_InitTypeDef DMA_InitStructure
SPI_InitTypeDef SPI_InitStructure
uint8_t | SPI_MASTER_Buffer_Rx [BufferSize]
uint8_t | SPI_MASTER_Buffer_Tx [BufferSize]
volatile uint8_t | SPI_MASTERCRCValue = 0
uint8_t | SPI_SLAVE_Buffer_Rx [BufferSize]
uint8_t | SPI_SLAVE_Buffer_Tx [BufferSize]
volatile uint8_t | SPI_SLAVECRCValue = 0
volatile TestStatus | TransferStatus1 = FAILED
volatile TestStatus | TransferStatus2 = FAILED

Define Documentation

#define BufferSize 32

Definition at line 39 of file STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/main.c.

Referenced by main().

#define CRCPolynomial 7

Definition at line 40 of file STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/main.c.

Referenced by main().

Enumeration Type Documentation

enum TestStatus
Enumerator:
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED

Definition at line 36 of file STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/main.c.

Function Documentation

TestStatus Buffercmp | ( | uint8_t * | pBuffer,
 |  | uint8_t * | pBuffer1,
 |  | uint16_t | BufferLength
 | ) |  |

Compares two buffers.

Parameters:
pBuffer,pBuffer1,: buffers to be compared.
BufferLength,: buffer's length
Return values:
PASSED,: pBuffer identical to pBuffer1 FAILED: pBuffer differs from pBuffer1
void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 86 of file STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 121 of file STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/stm32f10x_it.c.

void GPIO_Configuration ( void )

Configures the different GPIO ports.

Parameters:
None
Return values:
None

Definition at line 222 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 60 of file STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 72 of file STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/main.c.

References Buffercmp(), BufferSize, CRCPolynomial, DMA_InitTypeDef::DMA_BufferSize, DMA_Cmd(), DMA_DeInit(), DMA_InitTypeDef::DMA_DIR, DMA_DIR_PeripheralDST, DMA_DIR_PeripheralSRC, DMA_GetFlagStatus(), DMA_Init(), DMA_InitTypeDef::DMA_M2M, DMA_M2M_Disable, DMA_InitTypeDef::DMA_MemoryBaseAddr, DMA_InitTypeDef::DMA_MemoryDataSize, DMA_MemoryDataSize_Byte, DMA_InitTypeDef::DMA_MemoryInc, DMA_MemoryInc_Enable, DMA_InitTypeDef::DMA_Mode, DMA_Mode_Normal, DMA_InitTypeDef::DMA_PeripheralBaseAddr, DMA_InitTypeDef::DMA_PeripheralDataSize, DMA_PeripheralDataSize_Byte, DMA_InitTypeDef::DMA_PeripheralInc, DMA_PeripheralInc_Disable, DMA_InitTypeDef::DMA_Priority, DMA_Priority_High, DMA_Priority_Low, DMA_Priority_Medium, DMA_Priority_VeryHigh, ENABLE, FAILED, GPIO_Configuration(), LED1, LED2, RCC_Configuration(), RESET, SPI_InitTypeDef::SPI_BaudRatePrescaler, SPI_BaudRatePrescaler_8, SPI_CalculateCRC(), SPI_Cmd(), SPI_InitTypeDef::SPI_CPHA, SPI_CPHA_2Edge, SPI_InitTypeDef::SPI_CPOL, SPI_CPOL_Low, SPI_InitTypeDef::SPI_CRCPolynomial, SPI_InitTypeDef::SPI_DataSize, SPI_DataSize_8b, SPI_InitTypeDef::SPI_Direction, SPI_Direction_2Lines_FullDuplex, SPI_InitTypeDef::SPI_FirstBit, SPI_FirstBit_MSB, SPI_FLAG_CRCERR, SPI_I2S_DMACmd(), SPI_I2S_DMAReq_Rx, SPI_I2S_DMAReq_Tx, SPI_I2S_FLAG_RXNE, SPI_I2S_GetFlagStatus(), SPI_I2S_ReceiveData(), SPI_Init(), SPI_MASTER_Buffer_Rx, SPI_MASTER_Buffer_Tx, SPI_MASTERCRCValue, SPI_InitTypeDef::SPI_Mode, SPI_Mode_Master, SPI_Mode_Slave, SPI_InitTypeDef::SPI_NSS, SPI_NSS_Soft, SPI_SLAVE_Buffer_Rx, SPI_SLAVE_Buffer_Tx, SPI_SLAVECRCValue, STM_EVAL_LEDInit(), STM_EVAL_LEDOff(), STM_EVAL_LEDOn(), TransferStatus1, and TransferStatus2.

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 73 of file STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 51 of file STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/stm32f10x_it.c.

void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 130 of file STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/stm32f10x_it.c.

void RCC_Configuration ( void )

Configures the different system clocks.

Parameters:
None
Return values:
None

Definition at line 203 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 112 of file STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 139 of file STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/stm32f10x_it.c.

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 99 of file STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/stm32f10x_it.c.

Variable Documentation

DMA_InitTypeDef DMA_InitStructure

Definition at line 45 of file STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/main.c.

SPI_InitTypeDef SPI_InitStructure

Definition at line 44 of file STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/main.c.

Referenced by LCD_SPIConfig(), SD_LowLevel_Init(), sFLASH_Init(), and SPI_Configuration().

uint8_t SPI_MASTER_Buffer_Rx[BufferSize]

Definition at line 46 of file STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/main.c.

Referenced by main().

uint8_t SPI_MASTER_Buffer_Tx[BufferSize]
Initial value:
 {0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,
                                            0x09,0x0A,0x0B,0x0C,0x0D,0x0E,0x0F,0x10,
                                            0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x18,
                                            0x19,0x1A,0x1B,0x1C,0x1D,0x1E,0x1F,0x20}

Definition at line 50 of file STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/main.c.

Referenced by main(), and SPI1_IRQHandler().

volatile uint8_t SPI_MASTERCRCValue = 0

Definition at line 47 of file STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/main.c.

Referenced by main().

uint8_t SPI_SLAVE_Buffer_Rx[BufferSize]

Definition at line 46 of file STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/main.c.

Referenced by main(), and SPI2_IRQHandler().

uint8_t SPI_SLAVE_Buffer_Tx[BufferSize]
Initial value:
 {0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,
                                           0x59,0x5A,0x5B,0x5C,0x5D,0x5E,0x5F,0x60,
                                           0x61,0x62,0x63,0x64,0x65,0x66,0x67,0x68,
                                           0x69,0x6A,0x6B,0x6C,0x6D,0x6E,0x6F,0x70}

Definition at line 55 of file STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/main.c.

Referenced by main().

volatile uint8_t SPI_SLAVECRCValue = 0

Definition at line 47 of file STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/main.c.

Referenced by main().

volatile TestStatus TransferStatus1 = FAILED

Definition at line 48 of file STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/main.c.

Referenced by main(), and SD_SingleBlockTest().

volatile TestStatus TransferStatus2 = FAILED

Definition at line 48 of file STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/main.c.

Referenced by main(), and SD_MultiBlockTest().


STM32F10x Standard Peripherals Firmware Library: EXTI_Config

Functions | Variables

EXTI_Config

STM32F10x_StdPeriph_Examples

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | EXTI0_Config (void)
Configure PA.00 in interrupt mode.
void | EXTI0_IRQHandler (void)
This function handles External line 0 interrupt request.
void | EXTI9_5_Config (void)
Configure PB.09 or PG.08 in interrupt mode.
void | EXTI9_5_IRQHandler (void)
This function handles External lines 9 to 5 interrupt request.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

EXTI_InitTypeDef EXTI_InitStructure
GPIO_InitTypeDef GPIO_InitStructure
NVIC_InitTypeDef NVIC_InitStructure

Function Documentation

void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 87 of file STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 122 of file STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/stm32f10x_it.c.

void EXTI0_Config ( void )

Configure PA.00 in interrupt mode.

Parameters:
None
Return values:
None

Definition at line 85 of file STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/main.c.

References ENABLE, EXTI0_IRQn, EXTI_Init(), EXTI_InitTypeDef::EXTI_Line, EXTI_Line0, EXTI_InitTypeDef::EXTI_LineCmd, EXTI_InitTypeDef::EXTI_Mode, EXTI_Mode_Interrupt, EXTI_InitTypeDef::EXTI_Trigger, EXTI_Trigger_Rising, GPIO_EXTILineConfig(), GPIO_Init(), GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_IN_FLOATING, GPIO_InitTypeDef::GPIO_Pin, GPIO_Pin_0, GPIO_PinSource0, GPIO_PortSourceGPIOA, GPIOA, NVIC_Init(), NVIC_InitTypeDef::NVIC_IRQChannel, NVIC_InitTypeDef::NVIC_IRQChannelCmd, NVIC_InitTypeDef::NVIC_IRQChannelPreemptionPriority, NVIC_InitTypeDef::NVIC_IRQChannelSubPriority, RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, and RCC_APB2PeriphClockCmd().

Referenced by main().

void EXTI0_IRQHandler ( void )

This function handles External line 0 interrupt request.

Parameters:
None
Return values:
None

Definition at line 153 of file STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/stm32f10x_it.c.

void EXTI9_5_Config ( void )

Configure PB.09 or PG.08 in interrupt mode.

Parameters:
None
Return values:
None

Definition at line 121 of file STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/main.c.

References ENABLE, EXTI_Init(), EXTI_InitTypeDef::EXTI_Line, EXTI_Line8, EXTI_Line9, EXTI_InitTypeDef::EXTI_LineCmd, EXTI_InitTypeDef::EXTI_Mode, EXTI_Mode_Interrupt, EXTI_InitTypeDef::EXTI_Trigger, EXTI_Trigger_Falling, GPIO_EXTILineConfig(), GPIO_Init(), GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_IN_FLOATING, GPIO_InitTypeDef::GPIO_Pin, GPIO_Pin_8, GPIO_Pin_9, GPIO_PinSource8, GPIO_PinSource9, GPIO_PortSourceGPIOB, GPIO_PortSourceGPIOG, GPIOB, GPIOG, NVIC_Init(), NVIC_InitTypeDef::NVIC_IRQChannel, NVIC_InitTypeDef::NVIC_IRQChannelCmd, NVIC_InitTypeDef::NVIC_IRQChannelPreemptionPriority, NVIC_InitTypeDef::NVIC_IRQChannelSubPriority, RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOB, RCC_APB2Periph_GPIOG, and RCC_APB2PeriphClockCmd().

Referenced by main().

void EXTI9_5_IRQHandler ( void )

This function handles External lines 9 to 5 interrupt request.

This function handles EXTI Lines 9 to 5 interrupts requests.

Parameters:
None
Return values:
None

Definition at line 170 of file STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/stm32f10x_it.c.

References EXTI_ClearITPendingBit(), EXTI_GetITStatus(), EXTI_Line8, EXTI_Line9, LED2, RESET, and STM_EVAL_LEDToggle().

void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 61 of file STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 53 of file STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/main.c.

References EXTI0_Config(), EXTI9_5_Config(), EXTI_GenerateSWInterrupt(), EXTI_Line0, LED1, LED2, and STM_EVAL_LEDInit().

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 74 of file STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 52 of file STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/stm32f10x_it.c.

void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 131 of file STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/stm32f10x_it.c.

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 113 of file STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 140 of file STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/stm32f10x_it.c.

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 100 of file STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/stm32f10x_it.c.

Variable Documentation

EXTI_InitTypeDef EXTI_InitStructure

Definition at line 38 of file STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/main.c.

Referenced by EXTI_Configuration(), HDMI_CEC_CommandCallBack(), IOE_EXTI_Config(), and STM_EVAL_PBInit().

GPIO_InitTypeDef GPIO_InitStructure

Definition at line 39 of file STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/main.c.

Referenced by CAN_Config(), GPIO_Configuration(), HDMI_CEC_Init(), IOE_EXTI_Config(), IOE_GPIO_Config(), LCD_CtrlLinesConfig(), LCD_DeInit(), LCD_GPIOConfig(), LCD_SPIConfig(), LM75_LowLevel_DeInit(), LM75_LowLevel_Init(), NAND_Init(), NOR_Init(), OneNAND_Init(), SD_LowLevel_DeInit(), SD_LowLevel_Init(), sEE_LowLevel_DeInit(), sEE_LowLevel_Init(), sFLASH_LowLevel_DeInit(), sFLASH_LowLevel_Init(), SRAM_Init(), STM32L152_LCD_DeInit(), STM_EVAL_COMInit(), STM_EVAL_LEDInit(), and STM_EVAL_PBInit().

NVIC_InitTypeDef NVIC_InitStructure

Definition at line 40 of file STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/main.c.

Referenced by EXTI9_5_IRQHandler(), IOE_EXTI_Config(), NVIC_Config(), NVIC_Configuration(), sEE_LowLevel_DeInit(), sEE_LowLevel_Init(), STM_EVAL_PBInit(), TIM5_ConfigForLSI(), and TIM_Config().


STM32F10x Standard Peripherals Firmware Library: Dual_Boot

Defines | Enumerations | Functions | Variables

Dual_Boot

STM32F10x_StdPeriph_Examples

Defines

#define | BANK1_START_ADDRESS 0x08000000
#define | BANK2_START_ADDRESS 0x08080000
#define | MESSAGE1 " STM32 XL Density "
#define | MESSAGE10 " 0x0 the base @ of Bank1/2"
#define | MESSAGE11 " Operation Failed !"
#define | MESSAGE12 "Bank 1/2 base @ -> 0"
#define | MESSAGE2 " Device running on "
#define | MESSAGE3 " STM3210E-EVAL "
#define | MESSAGE5 " Joystick-DOWN: reset BFB2"
#define | MESSAGE6 " bit to Boot from Bank2 "
#define | MESSAGE7 " Joystick-UP: set BFB2 "
#define | MESSAGE8 " bit to Boot from Bank1 "
#define | MESSAGE9 " Joystick-SEL: program to "

Enumerations

enum TestStatus {
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED
}

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | Delay (__IO uint32_t nTime)
Inserts a delay time.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | TimingDelay_Decrement (void)
Decrements the TimingDelay variable.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

RCC_ClocksTypeDef RCC_Clocks
static __IO uint32_t | TimingDelay
USART_InitTypeDef USART_InitStructure

Define Documentation

#define BANK1_START_ADDRESS 0x08000000

Definition at line 67 of file STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/main.c.

Referenced by main().

#define BANK2_START_ADDRESS 0x08080000

Definition at line 68 of file STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/main.c.

Referenced by main().

#define MESSAGE1 " STM32 XL Density "

Definition at line 52 of file STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/main.c.

Referenced by main().

#define MESSAGE10 " 0x0 the base @ of Bank1/2"

Definition at line 62 of file STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/main.c.

Referenced by main().

#define MESSAGE11 " Operation Failed !"

Definition at line 64 of file STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/main.c.

Referenced by main().

#define MESSAGE12 "Bank 1/2 base @ -> 0"

Definition at line 65 of file STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/main.c.

Referenced by main().

#define MESSAGE2 " Device running on "

Definition at line 53 of file STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/main.c.

Referenced by main().

#define MESSAGE3 " STM3210E-EVAL "

Definition at line 54 of file STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/main.c.

Referenced by main().

#define MESSAGE5 " Joystick-DOWN: reset BFB2"

Definition at line 56 of file STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/main.c.

Referenced by main().

#define MESSAGE6 " bit to Boot from Bank2 "

Definition at line 57 of file STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/main.c.

Referenced by main().

#define MESSAGE7 " Joystick-UP: set BFB2 "

Definition at line 58 of file STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/main.c.

Referenced by main().

#define MESSAGE8 " bit to Boot from Bank1 "

Definition at line 59 of file STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/main.c.

Referenced by main().

#define MESSAGE9 " Joystick-SEL: program to "

Definition at line 61 of file STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/main.c.

Referenced by main().

Enumeration Type Documentation

enum TestStatus
Enumerator:
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED

Definition at line 35 of file STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/main.c.

Function Documentation

void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 87 of file STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 122 of file STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/stm32f10x_it.c.

void Delay ( __IO uint32_t nTime )

Inserts a delay time.

Parameters:
nTime,: specifies the delay time length, in 10 ms.
Return values:
None
void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 61 of file STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 87 of file STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/main.c.

References BANK1_START_ADDRESS, BANK2_START_ADDRESS, BUTTON_DOWN, BUTTON_MODE_GPIO, BUTTON_SEL, BUTTON_UP, Delay(), FLASH_COMPLETE, FLASH_EraseOptionBytes(), FLASH_Lock(), FLASH_ProgramWord(), FLASH_Unlock(), Font12x12, Font16x24, RCC_ClocksTypeDef::HCLK_Frequency, LCD_Clear(), LCD_ClearLine(), LCD_COLOR_BLUE, LCD_COLOR_RED, LCD_COLOR_WHITE, LCD_DisplayStringLine(), LCD_LINE_0, LCD_LINE_1, LCD_LINE_12, LCD_LINE_13, LCD_LINE_15, LCD_LINE_16, LCD_LINE_18, LCD_LINE_19, LCD_LINE_2, LCD_LINE_4, LCD_LINE_6, LCD_LINE_7, LCD_LINE_8, LCD_LINE_9, LCD_SetBackColor(), LCD_SetFont(), LCD_SetTextColor(), LED1, LED2, LED3, LED4, MESSAGE1, MESSAGE10, MESSAGE11, MESSAGE12, MESSAGE2, MESSAGE3, MESSAGE5, MESSAGE6, MESSAGE7, MESSAGE8, MESSAGE9, NVIC_SetVectorTable(), NVIC_VectTab_FLASH, RCC_GetClocksFreq(), STM3210E_LCD_Init(), STM_EVAL_LEDInit(), STM_EVAL_LEDOn(), STM_EVAL_LEDToggle(), STM_EVAL_PBGetState(), and STM_EVAL_PBInit().

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 74 of file STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 52 of file STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/stm32f10x_it.c.

void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 131 of file STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/stm32f10x_it.c.

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 113 of file STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 140 of file STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/stm32f10x_it.c.

References TimingDelay_Decrement().

void TimingDelay_Decrement ( void )

Decrements the TimingDelay variable.

Parameters:
None
Return values:
None

Definition at line 264 of file STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/main.c.

Referenced by SysTick_Handler().

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 100 of file STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/stm32f10x_it.c.

Variable Documentation

RCC_ClocksTypeDef RCC_Clocks

Definition at line 75 of file STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/main.c.

Referenced by I2S_Init().

__IO uint32_t TimingDelay [static]

Definition at line 74 of file STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/main.c.

Referenced by SysTick_Handler(), and TimingDelay_Decrement().

USART_InitTypeDef USART_InitStructure

Definition at line 72 of file STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/main.c.


STM32F10x Standard Peripherals Firmware Library: FLASH_Program

Defines | Enumerations | Functions | Variables

FLASH_Program

STM32F10x_StdPeriph_Examples

Defines

#define | BANK1_WRITE_END_ADDR ((uint32_t)0x0800C000)
#define | BANK1_WRITE_START_ADDR ((uint32_t)0x08008000)
#define | FLASH_PAGE_SIZE ((uint16_t)0x400)

Enumerations

enum TestStatus {
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED
}

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

uint32_t | Address = 0x00
uint32_t | Data = 0x3210ABCD
uint32_t | EraseCounter = 0x00
volatile FLASH_Status | FLASHStatus = FLASH_COMPLETE
volatile TestStatus | MemoryProgramStatus = PASSED
uint32_t | NbrOfPage = 0x00

Define Documentation

#define BANK1_WRITE_END_ADDR ((uint32_t)0x0800C000)

Definition at line 46 of file STM32F10x_StdPeriph_Examples/FLASH/Program/main.c.

Referenced by main().

#define BANK1_WRITE_START_ADDR ((uint32_t)0x08008000)

Definition at line 45 of file STM32F10x_StdPeriph_Examples/FLASH/Program/main.c.

Referenced by main().

#define FLASH_PAGE_SIZE ((uint16_t)0x400)

Definition at line 42 of file STM32F10x_StdPeriph_Examples/FLASH/Program/main.c.

Referenced by main().

Enumeration Type Documentation

enum TestStatus
Enumerator:
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED

Definition at line 35 of file STM32F10x_StdPeriph_Examples/FLASH/Program/main.c.

Function Documentation

void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 86 of file STM32F10x_StdPeriph_Examples/FLASH/Program/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 121 of file STM32F10x_StdPeriph_Examples/FLASH/Program/stm32f10x_it.c.

void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 60 of file STM32F10x_StdPeriph_Examples/FLASH/Program/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 73 of file STM32F10x_StdPeriph_Examples/FLASH/Program/main.c.

References Address, BANK1_WRITE_END_ADDR, BANK1_WRITE_START_ADDR, Data, EraseCounter, FAILED, FLASH_ClearFlag(), FLASH_COMPLETE, FLASH_ErasePage(), FLASH_FLAG_EOP, FLASH_FLAG_PGERR, FLASH_FLAG_WRPRTERR, FLASH_LockBank1(), FLASH_PAGE_SIZE, FLASH_ProgramWord(), FLASH_UnlockBank1(), FLASHStatus, MemoryProgramStatus, and NbrOfPage.

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 73 of file STM32F10x_StdPeriph_Examples/FLASH/Program/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 51 of file STM32F10x_StdPeriph_Examples/FLASH/Program/stm32f10x_it.c.

void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 130 of file STM32F10x_StdPeriph_Examples/FLASH/Program/stm32f10x_it.c.

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 112 of file STM32F10x_StdPeriph_Examples/FLASH/Program/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 139 of file STM32F10x_StdPeriph_Examples/FLASH/Program/stm32f10x_it.c.

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 99 of file STM32F10x_StdPeriph_Examples/FLASH/Program/stm32f10x_it.c.

Variable Documentation

uint32_t Address = 0x00

Definition at line 55 of file STM32F10x_StdPeriph_Examples/FLASH/Program/main.c.

Referenced by I2C_Send7bitAddress(), and main().

uint32_t Data = 0x3210ABCD

Definition at line 56 of file STM32F10x_StdPeriph_Examples/FLASH/Program/main.c.

Referenced by CEC_SendDataByte(), CRC_CalcCRC(), FLASH_ProgramWord(), I2C_SendData(), main(), SD_ReadByte(), SDIO_WriteData(), and SPI_I2S_SendData().

uint32_t EraseCounter = 0x00

Definition at line 55 of file STM32F10x_StdPeriph_Examples/FLASH/Program/main.c.

Referenced by main().

volatile FLASH_Status FLASHStatus = FLASH_COMPLETE

Definition at line 58 of file STM32F10x_StdPeriph_Examples/FLASH/Program/main.c.

Referenced by main().

volatile TestStatus MemoryProgramStatus = PASSED

Definition at line 59 of file STM32F10x_StdPeriph_Examples/FLASH/Program/main.c.

Referenced by main().

uint32_t NbrOfPage = 0x00

Definition at line 57 of file STM32F10x_StdPeriph_Examples/FLASH/Program/main.c.

Referenced by main().


STM32F10x Standard Peripherals Firmware Library: FLASH_Write_Protection

Defines | Enumerations | Functions | Variables

FLASH_Write_Protection

STM32F10x_StdPeriph_Examples

Defines

#define | BANK1_WRITE_END_ADDR ((uint32_t)0x08008000)
#define | BANK1_WRITE_START_ADDR ((uint32_t)0x08006000)
#define | FLASH_PAGE_SIZE ((uint16_t)0x400)
#define | FLASH_PAGES_TO_BE_PROTECTED (FLASH_WRProt_Pages24to27 | FLASH_WRProt_Pages28to31)
#define | WRITE_PROTECTION_DISABLE

Enumerations

enum TestStatus {
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED
}

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

uint32_t | Address = 0x0
uint16_t | Data = 0x1753
uint32_t | EraseCounter = 0x0
volatile FLASH_Status | FLASHStatus = FLASH_COMPLETE
volatile TestStatus | MemoryProgramStatus = PASSED
uint32_t | NbrOfPage
uint32_t | ProtectedPages = 0x0
uint32_t | WRPR_Value = 0xFFFFFFFF

Define Documentation

#define BANK1_WRITE_END_ADDR ((uint32_t)0x08008000)

Definition at line 47 of file STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/main.c.

Referenced by main().

#define BANK1_WRITE_START_ADDR ((uint32_t)0x08006000)

Definition at line 46 of file STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/main.c.

Referenced by main().

#define FLASH_PAGE_SIZE ((uint16_t)0x400)

Definition at line 42 of file STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/main.c.

Referenced by main().

#define FLASH_PAGES_TO_BE_PROTECTED (FLASH_WRProt_Pages24to27 | FLASH_WRProt_Pages28to31)

Definition at line 43 of file STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/main.c.

Referenced by main().

#define WRITE_PROTECTION_DISABLE

Definition at line 54 of file STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/main.c.

Enumeration Type Documentation

enum TestStatus
Enumerator:
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED

Definition at line 34 of file STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/main.c.

Function Documentation

void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 86 of file STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 121 of file STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/stm32f10x_it.c.

void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 60 of file STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 73 of file STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/main.c.

References Address, BANK1_WRITE_END_ADDR, BANK1_WRITE_START_ADDR, Data, EraseCounter, FAILED, FLASH_ClearFlag(), FLASH_COMPLETE, FLASH_EnableWriteProtection(), FLASH_EraseOptionBytes(), FLASH_ErasePage(), FLASH_FLAG_BSY, FLASH_FLAG_EOP, FLASH_FLAG_PGERR, FLASH_FLAG_WRPRTERR, FLASH_GetWriteProtectionOptionByte(), FLASH_PAGE_SIZE, FLASH_PAGES_TO_BE_PROTECTED, FLASH_ProgramHalfWord(), FLASH_Unlock(), FLASHStatus, MemoryProgramStatus, NbrOfPage, ProtectedPages, and WRPR_Value.

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 73 of file STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 51 of file STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/stm32f10x_it.c.

void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 130 of file STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/stm32f10x_it.c.

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 112 of file STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 139 of file STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/stm32f10x_it.c.

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 99 of file STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/stm32f10x_it.c.

Variable Documentation

uint32_t Address = 0x0

Definition at line 58 of file STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/main.c.

uint16_t Data = 0x1753

Definition at line 59 of file STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/main.c.

uint32_t EraseCounter = 0x0

Definition at line 58 of file STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/main.c.

volatile FLASH_Status FLASHStatus = FLASH_COMPLETE

Definition at line 62 of file STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/main.c.

volatile TestStatus MemoryProgramStatus = PASSED

Definition at line 63 of file STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/main.c.

uint32_t NbrOfPage

Definition at line 61 of file STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/main.c.

uint32_t ProtectedPages = 0x0

Definition at line 60 of file STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/main.c.

Referenced by main().

uint32_t WRPR_Value = 0xFFFFFFFF

Definition at line 60 of file STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/main.c.

Referenced by main().


STM32F10x Standard Peripherals Firmware Library: FSMC_NAND

Defines | Functions | Variables

FSMC_NAND

STM32F10x_StdPeriph_Examples

Defines

#define | BUFFER_SIZE 0x400
#define | NAND_ST_DeviceID 0x76
#define | NAND_ST_MakerID 0x20

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | Fill_Buffer (uint8_t *pBuffer, uint16_t BufferLenght, uint32_t Offset)
Fill the buffer.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

uint32_t | j = 0
NAND_IDTypeDef NAND_ID
uint32_t | PageNumber = 2
uint8_t | RxBuffer [BUFFER_SIZE]
uint32_t | status = 0
uint8_t | TxBuffer [BUFFER_SIZE]
NAND_ADDRESS WriteReadAddr
uint32_t | WriteReadStatus = 0

Define Documentation

#define BUFFER_SIZE 0x400

Definition at line 36 of file STM32F10x_StdPeriph_Examples/FSMC/NAND/main.c.

Referenced by main().

#define NAND_ST_DeviceID 0x76

Definition at line 38 of file STM32F10x_StdPeriph_Examples/FSMC/NAND/main.c.

Referenced by main().

#define NAND_ST_MakerID 0x20

Definition at line 37 of file STM32F10x_StdPeriph_Examples/FSMC/NAND/main.c.

Referenced by main().

Function Documentation

void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 86 of file STM32F10x_StdPeriph_Examples/FSMC/NAND/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 121 of file STM32F10x_StdPeriph_Examples/FSMC/NAND/stm32f10x_it.c.

void Fill_Buffer | ( | uint8_t * | pBuffer,
 |  | uint16_t | BufferLenght,
 |  | uint32_t | Offset
 | ) |  |

Fill the buffer.

Parameters:
pBuffer,: pointer on the Buffer to fill
BufferSize,: size of the buffer to fill
Offset,: first value to fill on the Buffer

Definition at line 141 of file STM32F10x_StdPeriph_Examples/FSMC/NAND/main.c.

Referenced by main(), SD_MultiBlockTest(), and SD_SingleBlockTest().

void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 60 of file STM32F10x_StdPeriph_Examples/FSMC/NAND/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 58 of file STM32F10x_StdPeriph_Examples/FSMC/NAND/main.c.

References NAND_ADDRESS::Block, BUFFER_SIZE, NAND_IDTypeDef::Device_ID, ENABLE, Fill_Buffer(), j, LED1, LED2, LED3, NAND_IDTypeDef::Maker_ID, NAND_EraseBlock(), NAND_Init(), NAND_ReadID(), NAND_ReadSmallPage(), NAND_ST_DeviceID, NAND_ST_MakerID, NAND_WriteSmallPage(), NAND_ADDRESS::Page, PageNumber, RCC_AHBPeriph_FSMC, RCC_AHBPeriphClockCmd(), RxBuffer, status, STM_EVAL_LEDInit(), STM_EVAL_LEDOn(), TxBuffer, WriteReadStatus, and NAND_ADDRESS::Zone.

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 73 of file STM32F10x_StdPeriph_Examples/FSMC/NAND/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 51 of file STM32F10x_StdPeriph_Examples/FSMC/NAND/stm32f10x_it.c.

void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 130 of file STM32F10x_StdPeriph_Examples/FSMC/NAND/stm32f10x_it.c.

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 112 of file STM32F10x_StdPeriph_Examples/FSMC/NAND/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 139 of file STM32F10x_StdPeriph_Examples/FSMC/NAND/stm32f10x_it.c.

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 99 of file STM32F10x_StdPeriph_Examples/FSMC/NAND/stm32f10x_it.c.

Variable Documentation

uint32_t j = 0

Definition at line 46 of file STM32F10x_StdPeriph_Examples/FSMC/NAND/main.c.

Referenced by HDMI_CEC_TransmitMessage(), LCD_FillPolyLine(), and main().

NAND_IDTypeDef NAND_ID

Definition at line 42 of file STM32F10x_StdPeriph_Examples/FSMC/NAND/main.c.

uint32_t PageNumber = 2

Definition at line 45 of file STM32F10x_StdPeriph_Examples/FSMC/NAND/main.c.

Referenced by main().

uint8_t RxBuffer[BUFFER_SIZE]

Definition at line 44 of file STM32F10x_StdPeriph_Examples/FSMC/NAND/main.c.

Referenced by main(), and USARTx_IRQHandler().

uint32_t status = 0

Definition at line 45 of file STM32F10x_StdPeriph_Examples/FSMC/NAND/main.c.

Referenced by CAN_OperatingModeRequest(), CmdResp2Error(), CmdResp3Error(), CmdResp6Error(), CmdResp7Error(), FLASH_EnableWriteProtection(), FLASH_EraseAllBank1Pages(), FLASH_EraseAllPages(), FLASH_EraseOptionBytes(), FLASH_ErasePage(), FLASH_ProgramHalfWord(), FLASH_ProgramOptionByteData(), FLASH_ProgramWord(), FLASH_ReadOutProtection(), FLASH_UserOptionByteConfig(), FLASH_WaitForLastBank1Operation(), FLASH_WaitForLastOperation(), I2C_CheckEvent(), IsCardProgramming(), main(), NAND_AddressIncrement(), NAND_GetStatus(), NAND_ReadSmallPage(), NAND_ReadSpareArea(), NAND_ReadStatus(), NAND_WriteSmallPage(), NAND_WriteSpareArea(), NOR_GetStatus(), NOR_WriteBuffer(), OneNAND_AsynchronousRead(), OneNAND_EraseBlock(), OneNAND_ReadControllerStatus(), OneNAND_ReadID(), OneNAND_ReadStatus(), OneNAND_SynchronousRead(), OneNAND_UnlockBlock(), OneNAND_WriteBuffer(), RCC_WaitForHSEStartUp(), SD_Detect(), and SD_GetCardInfo().

uint8_t TxBuffer[BUFFER_SIZE]

Definition at line 44 of file STM32F10x_StdPeriph_Examples/FSMC/NAND/main.c.

Referenced by main(), and USARTx_IRQHandler().

NAND_ADDRESS WriteReadAddr

Definition at line 43 of file STM32F10x_StdPeriph_Examples/FSMC/NAND/main.c.

uint32_t WriteReadStatus = 0

Definition at line 45 of file STM32F10x_StdPeriph_Examples/FSMC/NAND/main.c.

Referenced by main().


STM32F10x Standard Peripherals Firmware Library: FSMC_NOR

Defines | Functions | Variables

FSMC_NOR

STM32F10x_StdPeriph_Examples

Defines

#define | BUFFER_SIZE 0x400
#define | WRITE_READ_ADDR 0x8000

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | RCC_Configuration (void)
Configures the different system clocks.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

uint32_t | Index = 0
NOR_IDTypeDef NOR_ID
uint16_t | RxBuffer [BUFFER_SIZE]
uint16_t | TxBuffer [BUFFER_SIZE]
uint32_t | WriteReadStatus = 0

Define Documentation

#define BUFFER_SIZE 0x400

Definition at line 36 of file STM32F10x_StdPeriph_Examples/FSMC/NOR/main.c.

Referenced by main().

#define WRITE_READ_ADDR 0x8000

Definition at line 37 of file STM32F10x_StdPeriph_Examples/FSMC/NOR/main.c.

Referenced by main().

Function Documentation

void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 86 of file STM32F10x_StdPeriph_Examples/FSMC/NOR/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 121 of file STM32F10x_StdPeriph_Examples/FSMC/NOR/stm32f10x_it.c.

void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 60 of file STM32F10x_StdPeriph_Examples/FSMC/NOR/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 57 of file STM32F10x_StdPeriph_Examples/FSMC/NOR/main.c.

References BUFFER_SIZE, ENABLE, Fill_Buffer(), Index, LED1, LED2, NOR_EraseBlock(), NOR_Init(), NOR_ReadBuffer(), NOR_ReadID(), NOR_ReturnToReadMode(), NOR_WriteBuffer(), RCC_AHBPeriph_FSMC, RCC_AHBPeriphClockCmd(), RxBuffer, STM_EVAL_LEDInit(), STM_EVAL_LEDOn(), TxBuffer, WRITE_READ_ADDR, and WriteReadStatus.

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 73 of file STM32F10x_StdPeriph_Examples/FSMC/NOR/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 51 of file STM32F10x_StdPeriph_Examples/FSMC/NOR/stm32f10x_it.c.

void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 130 of file STM32F10x_StdPeriph_Examples/FSMC/NOR/stm32f10x_it.c.

void RCC_Configuration ( void )

Configures the different system clocks.

Parameters:
None
Return values:
None

Definition at line 203 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 112 of file STM32F10x_StdPeriph_Examples/FSMC/NOR/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 139 of file STM32F10x_StdPeriph_Examples/FSMC/NOR/stm32f10x_it.c.

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 99 of file STM32F10x_StdPeriph_Examples/FSMC/NOR/stm32f10x_it.c.

Variable Documentation

uint32_t Index = 0

Definition at line 43 of file STM32F10x_StdPeriph_Examples/FSMC/NOR/main.c.

NOR_IDTypeDef NOR_ID

Definition at line 44 of file STM32F10x_StdPeriph_Examples/FSMC/NOR/main.c.

uint16_t RxBuffer[BUFFER_SIZE]

Definition at line 42 of file STM32F10x_StdPeriph_Examples/FSMC/NOR/main.c.

uint16_t TxBuffer[BUFFER_SIZE]

Definition at line 41 of file STM32F10x_StdPeriph_Examples/FSMC/NOR/main.c.

uint32_t WriteReadStatus = 0

Definition at line 43 of file STM32F10x_StdPeriph_Examples/FSMC/NOR/main.c.


STM32F10x Standard Peripherals Firmware Library: FSMC_NOR_CodeExecute_binary

Functions

FSMC_NOR_CodeExecute_binary

STM32F10x_StdPeriph_Examples

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | Delay (__IO uint32_t nCount)
Inserts a delay time.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Function Documentation

void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 86 of file STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 121 of file STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/stm32f10x_it.c.

void Delay ( __IO uint32_t nCount )

Inserts a delay time.

Parameters:
nCount,: specifies the delay time length.
Return values:
None
void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 60 of file STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 48 of file STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/main.c.

References Delay(), LED1, LED2, LED3, LED4, STM_EVAL_LEDInit(), STM_EVAL_LEDOff(), and STM_EVAL_LEDOn().

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 73 of file STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 51 of file STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/stm32f10x_it.c.

void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 130 of file STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/stm32f10x_it.c.

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 112 of file STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 139 of file STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/stm32f10x_it.c.

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 99 of file STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: FSMC_NOR_CodeExecute

Defines | Typedefs | Functions | Variables

FSMC_NOR_CodeExecute

STM32F10x_StdPeriph_Examples

Defines

#define | ApplicationAddress ((uint32_t)0x64000000)

Typedefs

typedef void(* | pFunction )(void)

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

pFunction Jump_To_Application
__IO uint32_t | JumpAddress

Define Documentation

#define ApplicationAddress ((uint32_t)0x64000000)

Definition at line 37 of file STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/main.c.

Referenced by main().

Typedef Documentation

typedef void(* pFunction)(void)

Definition at line 34 of file STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/main.c.

Function Documentation

void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 86 of file STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 121 of file STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/stm32f10x_it.c.

void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 60 of file STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 52 of file STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/main.c.

References ApplicationAddress, ENABLE, Jump_To_Application, JumpAddress, NOR_Init(), RCC_AHBPeriph_FSMC, and RCC_AHBPeriphClockCmd().

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 73 of file STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 51 of file STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/stm32f10x_it.c.

void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 130 of file STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/stm32f10x_it.c.

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 112 of file STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 139 of file STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/stm32f10x_it.c.

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 99 of file STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/stm32f10x_it.c.

Variable Documentation

pFunction Jump_To_Application

Definition at line 41 of file STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/main.c.

Referenced by main().

__IO uint32_t JumpAddress

Definition at line 42 of file STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/main.c.

Referenced by main().


STM32F10x Standard Peripherals Firmware Library: FSMC_OneNAND

Defines | Functions | Variables

FSMC_OneNAND

STM32F10x_StdPeriph_Examples

Defines

#define | OneNAND_BUFFER_SIZE 0x0400
#define | OneNAND_NUMBER_OF_PAGE_PER_BLOCK 0x0040
#define | OneNAND_SAMSUNG_DEVICE_ID 0x0025
#define | OneNAND_SAMSUNG_MANUFACTURER_ID 0x00EC
#define | OneNAND_WRITE_BLOCK_NUMBER 0x0000
#define | OneNAND_WRITE_PAGE_NUMBER 0x0000

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | Fill_hBuffer (uint16_t *pBuffer, uint16_t BufferLenght, uint32_t Offset)
Fills a global 16-bit buffer.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

OneNAND_ADDRESS Address
uint32_t | j = 0
OneNAND_IDTypeDef OneNAND_ID
uint32_t | PageIndex = 0
uint16_t | RxBuffer_A [OneNAND_BUFFER_SIZE]
uint16_t | RxBuffer_S [OneNAND_BUFFER_SIZE]
uint32_t | Status = 0
uint16_t | TxBuffer [OneNAND_BUFFER_SIZE]

Define Documentation

#define OneNAND_BUFFER_SIZE 0x0400

Definition at line 39 of file STM32F10x_StdPeriph_Examples/FSMC/OneNAND/main.c.

Referenced by main().

#define OneNAND_NUMBER_OF_PAGE_PER_BLOCK 0x0040

Definition at line 42 of file STM32F10x_StdPeriph_Examples/FSMC/OneNAND/main.c.

Referenced by main().

#define OneNAND_SAMSUNG_DEVICE_ID 0x0025

Definition at line 37 of file STM32F10x_StdPeriph_Examples/FSMC/OneNAND/main.c.

Referenced by main().

#define OneNAND_SAMSUNG_MANUFACTURER_ID 0x00EC

Definition at line 36 of file STM32F10x_StdPeriph_Examples/FSMC/OneNAND/main.c.

Referenced by main().

#define OneNAND_WRITE_BLOCK_NUMBER 0x0000

Definition at line 40 of file STM32F10x_StdPeriph_Examples/FSMC/OneNAND/main.c.

Referenced by main().

#define OneNAND_WRITE_PAGE_NUMBER 0x0000

Definition at line 41 of file STM32F10x_StdPeriph_Examples/FSMC/OneNAND/main.c.

Referenced by main().

Function Documentation

void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 86 of file STM32F10x_StdPeriph_Examples/FSMC/OneNAND/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 121 of file STM32F10x_StdPeriph_Examples/FSMC/OneNAND/stm32f10x_it.c.

void Fill_hBuffer | ( | uint16_t * | pBuffer,
 |  | uint16_t | BufferLenght,
 |  | uint32_t | Offset
 | ) |  |

Fills a global 16-bit buffer.

Parameters:
pBuffer,: pointer on the Buffer to fill
BufferSize,: size of the buffer to fill
Offset,: first value to fill on the Buffer
Return values:
None

Definition at line 214 of file STM32F10x_StdPeriph_Examples/FSMC/OneNAND/main.c.

Referenced by main().

void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 60 of file STM32F10x_StdPeriph_Examples/FSMC/OneNAND/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 60 of file STM32F10x_StdPeriph_Examples/FSMC/OneNAND/main.c.

References OneNAND_ADDRESS::Block, OneNAND_IDTypeDef::Device_ID, Fill_hBuffer(), j, LED1, LED2, LED3, LED4, OneNAND_IDTypeDef::Manufacturer_ID, OneNAND_AsynchronousRead(), OneNAND_BUFFER_SIZE, OneNAND_EraseBlock(), OneNAND_Init(), OneNAND_NUMBER_OF_PAGE_PER_BLOCK, OneNAND_ReadID(), OneNAND_SAMSUNG_DEVICE_ID, OneNAND_SAMSUNG_MANUFACTURER_ID, OneNAND_SynchronousRead(), OneNAND_UnlockBlock(), OneNAND_WRITE_BLOCK_NUMBER, OneNAND_WRITE_PAGE_NUMBER, OneNAND_WriteBuffer(), OneNAND_ADDRESS::Page, PageIndex, RxBuffer_A, RxBuffer_S, Status, STM_EVAL_LEDInit(), STM_EVAL_LEDOn(), and TxBuffer.

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 73 of file STM32F10x_StdPeriph_Examples/FSMC/OneNAND/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 51 of file STM32F10x_StdPeriph_Examples/FSMC/OneNAND/stm32f10x_it.c.

void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 130 of file STM32F10x_StdPeriph_Examples/FSMC/OneNAND/stm32f10x_it.c.

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 112 of file STM32F10x_StdPeriph_Examples/FSMC/OneNAND/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 139 of file STM32F10x_StdPeriph_Examples/FSMC/OneNAND/stm32f10x_it.c.

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 99 of file STM32F10x_StdPeriph_Examples/FSMC/OneNAND/stm32f10x_it.c.

Variable Documentation

OneNAND_ADDRESS Address

Definition at line 47 of file STM32F10x_StdPeriph_Examples/FSMC/OneNAND/main.c.

uint32_t j = 0

Definition at line 49 of file STM32F10x_StdPeriph_Examples/FSMC/OneNAND/main.c.

OneNAND_IDTypeDef OneNAND_ID

Definition at line 46 of file STM32F10x_StdPeriph_Examples/FSMC/OneNAND/main.c.

uint32_t PageIndex = 0

Definition at line 49 of file STM32F10x_StdPeriph_Examples/FSMC/OneNAND/main.c.

Referenced by main().

uint16_t RxBuffer_A[OneNAND_BUFFER_SIZE]

Definition at line 48 of file STM32F10x_StdPeriph_Examples/FSMC/OneNAND/main.c.

Referenced by main().

uint16_t RxBuffer_S[OneNAND_BUFFER_SIZE]

Definition at line 48 of file STM32F10x_StdPeriph_Examples/FSMC/OneNAND/main.c.

Referenced by main().

uint32_t Status = 0

Definition at line 49 of file STM32F10x_StdPeriph_Examples/FSMC/OneNAND/main.c.

Referenced by main(), SD_EraseTest(), SD_GetStatus(), SD_MultiBlockTest(), and SD_SingleBlockTest().

uint16_t TxBuffer[OneNAND_BUFFER_SIZE]

Definition at line 48 of file STM32F10x_StdPeriph_Examples/FSMC/OneNAND/main.c.


STM32F10x Standard Peripherals Firmware Library: FSMC_SRAM

Defines | Functions | Variables

FSMC_SRAM

STM32F10x_StdPeriph_Examples

Defines

#define | BUFFER_SIZE 0x400
#define | WRITE_READ_ADDR 0x8000

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | Fill_Buffer (uint16_t *pBuffer, uint16_t BufferLenght, uint32_t Offset)
Fill the global buffer.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

uint32_t | Index = 0
uint16_t | RxBuffer [BUFFER_SIZE]
uint16_t | TxBuffer [BUFFER_SIZE]
uint32_t | WriteReadStatus = 0

Define Documentation

#define BUFFER_SIZE 0x400

Definition at line 41 of file STM32F10x_StdPeriph_Examples/FSMC/SRAM/main.c.

Referenced by main().

#define WRITE_READ_ADDR 0x8000

Definition at line 42 of file STM32F10x_StdPeriph_Examples/FSMC/SRAM/main.c.

Referenced by main().

Function Documentation

void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 86 of file STM32F10x_StdPeriph_Examples/FSMC/SRAM/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 121 of file STM32F10x_StdPeriph_Examples/FSMC/SRAM/stm32f10x_it.c.

void Fill_Buffer | ( | uint16_t * | pBuffer,
 |  | uint16_t | BufferLenght,
 |  | uint32_t | Offset
 | ) |  |

Fill the global buffer.

Parameters:
pBuffer,: pointer on the Buffer to fill
BufferSize,: size of the buffer to fill
Offset,: first value to fill on the Buffer
void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 60 of file STM32F10x_StdPeriph_Examples/FSMC/SRAM/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 60 of file STM32F10x_StdPeriph_Examples/FSMC/SRAM/main.c.

References BUFFER_SIZE, ENABLE, Fill_Buffer(), Index, LED1, LED2, RCC_AHBPeriph_FSMC, RCC_AHBPeriphClockCmd(), RxBuffer, SRAM_Init(), SRAM_ReadBuffer(), SRAM_WriteBuffer(), STM_EVAL_LEDInit(), STM_EVAL_LEDOn(), TxBuffer, WRITE_READ_ADDR, and WriteReadStatus.

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 73 of file STM32F10x_StdPeriph_Examples/FSMC/SRAM/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 51 of file STM32F10x_StdPeriph_Examples/FSMC/SRAM/stm32f10x_it.c.

void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 130 of file STM32F10x_StdPeriph_Examples/FSMC/SRAM/stm32f10x_it.c.

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 112 of file STM32F10x_StdPeriph_Examples/FSMC/SRAM/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 139 of file STM32F10x_StdPeriph_Examples/FSMC/SRAM/stm32f10x_it.c.

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 99 of file STM32F10x_StdPeriph_Examples/FSMC/SRAM/stm32f10x_it.c.

Variable Documentation

uint32_t Index = 0

Definition at line 48 of file STM32F10x_StdPeriph_Examples/FSMC/SRAM/main.c.

uint16_t RxBuffer[BUFFER_SIZE]

Definition at line 47 of file STM32F10x_StdPeriph_Examples/FSMC/SRAM/main.c.

uint16_t TxBuffer[BUFFER_SIZE]

Definition at line 46 of file STM32F10x_StdPeriph_Examples/FSMC/SRAM/main.c.

uint32_t WriteReadStatus = 0

Definition at line 48 of file STM32F10x_StdPeriph_Examples/FSMC/SRAM/main.c.


STM32F10x Standard Peripherals Firmware Library: FSMC_SRAM_DataMemory

Functions | Variables

FSMC_SRAM_DataMemory

STM32F10x_StdPeriph_Examples

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

uint32_t | Index
__IO uint32_t | MSPValue = 0
uint32_t | Tab [1024]
__IO uint32_t | TabAddr

Function Documentation

void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 86 of file STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 121 of file STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/stm32f10x_it.c.

void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 60 of file STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 48 of file STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/main.c.

References Index, MSPValue, Tab, and TabAddr.

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 73 of file STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 51 of file STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/stm32f10x_it.c.

void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 130 of file STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/stm32f10x_it.c.

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 112 of file STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 139 of file STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/stm32f10x_it.c.

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 99 of file STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/stm32f10x_it.c.

Variable Documentation

uint32_t Index

Definition at line 37 of file STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/main.c.

__IO uint32_t MSPValue = 0

Definition at line 38 of file STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/main.c.

Referenced by main().

uint32_t Tab[1024]

Definition at line 37 of file STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/main.c.

Referenced by main().

__IO uint32_t TabAddr

Definition at line 38 of file STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/main.c.

Referenced by main().


STM32F10x Standard Peripherals Firmware Library: GPIO_IOToggle

Functions | Variables

GPIO_IOToggle

STM32F10x_StdPeriph_Examples

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

GPIO_InitTypeDef GPIO_InitStructure

Function Documentation

void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 86 of file STM32F10x_StdPeriph_Examples/GPIO/IOToggle/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 121 of file STM32F10x_StdPeriph_Examples/GPIO/IOToggle/stm32f10x_it.c.

void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 60 of file STM32F10x_StdPeriph_Examples/GPIO/IOToggle/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 48 of file STM32F10x_StdPeriph_Examples/GPIO/IOToggle/main.c.

References ENABLE, GPIO_Init(), GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_Out_PP, GPIO_InitTypeDef::GPIO_Pin, GPIO_Pin_0, GPIO_Pin_2, GPIO_InitTypeDef::GPIO_Speed, GPIO_Speed_50MHz, GPIOD, RCC_APB2Periph_GPIOD, and RCC_APB2PeriphClockCmd().

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 73 of file STM32F10x_StdPeriph_Examples/GPIO/IOToggle/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 51 of file STM32F10x_StdPeriph_Examples/GPIO/IOToggle/stm32f10x_it.c.

void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 130 of file STM32F10x_StdPeriph_Examples/GPIO/IOToggle/stm32f10x_it.c.

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 112 of file STM32F10x_StdPeriph_Examples/GPIO/IOToggle/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 139 of file STM32F10x_StdPeriph_Examples/GPIO/IOToggle/stm32f10x_it.c.

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 99 of file STM32F10x_StdPeriph_Examples/GPIO/IOToggle/stm32f10x_it.c.

Variable Documentation

GPIO_InitTypeDef GPIO_InitStructure

Definition at line 38 of file STM32F10x_StdPeriph_Examples/GPIO/IOToggle/main.c.


STM32F10x Standard Peripherals Firmware Library: GPIO_JTAG_Remap

Functions | Variables

GPIO_JTAG_Remap

STM32F10x_StdPeriph_Examples

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | Delay (__IO uint32_t nCount)
Inserts a delay time.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | RCC_Configuration (void)
Configures the different system clocks.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

GPIO_InitTypeDef GPIO_InitStructure

Function Documentation

void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 86 of file STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 121 of file STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/stm32f10x_it.c.

void Delay ( __IO uint32_t nCount )

Inserts a delay time.

Parameters:
nCount,: specifies the delay time length.
Return values:
None
void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 60 of file STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 51 of file STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/main.c.

References BUTTON_KEY, BUTTON_MODE_GPIO, Delay(), ENABLE, GPIO_Init(), GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_Out_PP, GPIO_InitTypeDef::GPIO_Pin, GPIO_Pin_13, GPIO_Pin_14, GPIO_Pin_15, GPIO_Pin_3, GPIO_Pin_4, GPIO_PinRemapConfig(), GPIO_ReadOutputDataBit(), GPIO_Remap_SWJ_Disable, GPIO_InitTypeDef::GPIO_Speed, GPIO_Speed_50MHz, GPIO_WriteBit(), GPIOA, GPIOB, LED1, LED2, RCC_Configuration(), STM_EVAL_LEDInit(), STM_EVAL_LEDOn(), STM_EVAL_PBGetState(), and STM_EVAL_PBInit().

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 73 of file STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 51 of file STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/stm32f10x_it.c.

void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 130 of file STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/stm32f10x_it.c.

void RCC_Configuration ( void )

Configures the different system clocks.

Parameters:
None
Return values:
None

Definition at line 203 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 112 of file STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 139 of file STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/stm32f10x_it.c.

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 99 of file STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/stm32f10x_it.c.

Variable Documentation

GPIO_InitTypeDef GPIO_InitStructure

Definition at line 38 of file STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/main.c.


STM32F10x Standard Peripherals Firmware Library: I2C_EEPROM

Defines | Enumerations | Functions | Variables

I2C_EEPROM

STM32F10x_StdPeriph_Examples

Defines

#define | BUFFER_SIZE1 (countof(Tx1_Buffer)-1)
#define | BUFFER_SIZE2 (countof(Tx2_Buffer)-1)
#define | countof(a) (sizeof(a) / sizeof(*(a)))
#define | ENABLE_LCD_MSG_DISPLAY
#define | sEE_READ_ADDRESS1 0x50
#define | sEE_READ_ADDRESS2 (sEE_READ_ADDRESS1 + BUFFER_SIZE1)
#define | sEE_WRITE_ADDRESS1 0x50
#define | sEE_WRITE_ADDRESS2 (sEE_WRITE_ADDRESS1 + BUFFER_SIZE1)

Enumerations

enum TestStatus {
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED
}

Functions

TestStatus | Buffercmp (uint8_t *pBuffer1, uint8_t *pBuffer2, uint16_t BufferLength)
Compares two buffers.
void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
uint32_t | sEE_TIMEOUT_UserCallback (void)
Example of timeout situation management.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

volatile uint16_t | NumDataRead = 0
uint8_t | Rx1_Buffer [BUFFER_SIZE1]
uint8_t | Rx2_Buffer [BUFFER_SIZE2]
volatile TestStatus | TransferStatus1 = FAILED
volatile TestStatus | TransferStatus2 = FAILED
uint8_t | Tx1_Buffer []
uint8_t | Tx2_Buffer []

Define Documentation

#define BUFFER_SIZE1 (countof(Tx1_Buffer)-1)

Definition at line 55 of file STM32F10x_StdPeriph_Examples/I2C/EEPROM/main.c.

Referenced by main().

#define BUFFER_SIZE2 (countof(Tx2_Buffer)-1)

Definition at line 56 of file STM32F10x_StdPeriph_Examples/I2C/EEPROM/main.c.

Referenced by main().

#define countof ( a ) (sizeof(a) / sizeof(*(a)))

Definition at line 61 of file STM32F10x_StdPeriph_Examples/I2C/EEPROM/main.c.

#define ENABLE_LCD_MSG_DISPLAY

Definition at line 51 of file STM32F10x_StdPeriph_Examples/I2C/EEPROM/main.c.

#define sEE_READ_ADDRESS1 0x50

Definition at line 54 of file STM32F10x_StdPeriph_Examples/I2C/EEPROM/main.c.

Referenced by main().

#define sEE_READ_ADDRESS2 (sEE_READ_ADDRESS1 + BUFFER_SIZE1)

Definition at line 58 of file STM32F10x_StdPeriph_Examples/I2C/EEPROM/main.c.

Referenced by main().

#define sEE_WRITE_ADDRESS1 0x50

Definition at line 53 of file STM32F10x_StdPeriph_Examples/I2C/EEPROM/main.c.

Referenced by main().

#define sEE_WRITE_ADDRESS2 (sEE_WRITE_ADDRESS1 + BUFFER_SIZE1)

Definition at line 57 of file STM32F10x_StdPeriph_Examples/I2C/EEPROM/main.c.

Referenced by main().

Enumeration Type Documentation

enum TestStatus
Enumerator:
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED

Definition at line 47 of file STM32F10x_StdPeriph_Examples/I2C/EEPROM/main.c.

Function Documentation

TestStatus Buffercmp | ( | uint8_t * | pBuffer1,
 |  | uint8_t * | pBuffer2,
 |  | uint16_t | BufferLength
 | ) |  |

Compares two buffers.

Parameters:
pBuffer1,pBuffer2,: buffers to be compared.
BufferLength,: buffer's length
Return values:
PASSED,: pBuffer1 identical to pBuffer2 FAILED: pBuffer1 differs from pBuffer2
void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 86 of file STM32F10x_StdPeriph_Examples/I2C/EEPROM/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 121 of file STM32F10x_StdPeriph_Examples/I2C/EEPROM/stm32f10x_it.c.

void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 60 of file STM32F10x_StdPeriph_Examples/I2C/EEPROM/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 116 of file STM32F10x_StdPeriph_Examples/I2C/EEPROM/main.c.

References BUFFER_SIZE1, BUFFER_SIZE2, Buffercmp(), LCD_Clear(), LCD_COLOR_BLUE, LCD_COLOR_WHITE, LCD_DisplayStringLine(), LCD_LINE_0, LCD_LINE_1, LCD_LINE_3, LCD_LINE_5, LCD_LINE_7, LCD_SetBackColor(), LCD_SetTextColor(), NumDataRead, PASSED, Rx1_Buffer, Rx2_Buffer, sEE_DeInit(), sEE_Init(), sEE_READ_ADDRESS1, sEE_READ_ADDRESS2, sEE_ReadBuffer(), sEE_WRITE_ADDRESS1, sEE_WRITE_ADDRESS2, sEE_WriteBuffer(), STM32100B_LCD_Init(), STM32100E_LCD_Init(), STM3210B_LCD_Init(), STM3210C_LCD_Init(), STM3210E_LCD_Init(), TransferStatus1, TransferStatus2, Tx1_Buffer, and Tx2_Buffer.

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 73 of file STM32F10x_StdPeriph_Examples/I2C/EEPROM/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 51 of file STM32F10x_StdPeriph_Examples/I2C/EEPROM/stm32f10x_it.c.

void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 130 of file STM32F10x_StdPeriph_Examples/I2C/EEPROM/stm32f10x_it.c.

uint32_t sEE_TIMEOUT_UserCallback ( void )

Example of timeout situation management.

Parameters:
None.
Return values:
None.

Definition at line 267 of file STM32F10x_StdPeriph_Examples/I2C/EEPROM/main.c.

References LCD_Clear(), LCD_COLOR_RED, LCD_DisplayStringLine(), LCD_LINE_4, LCD_LINE_5, and LCD_LINE_6.

Referenced by sEE_I2C_DMA_TX_IRQHandler(), sEE_ReadBuffer(), sEE_WaitEepromStandbyState(), sEE_WriteBuffer(), and sEE_WritePage().

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 112 of file STM32F10x_StdPeriph_Examples/I2C/EEPROM/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 139 of file STM32F10x_StdPeriph_Examples/I2C/EEPROM/stm32f10x_it.c.

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 99 of file STM32F10x_StdPeriph_Examples/I2C/EEPROM/stm32f10x_it.c.

Variable Documentation

volatile uint16_t NumDataRead = 0

Definition at line 106 of file STM32F10x_StdPeriph_Examples/I2C/EEPROM/main.c.

Referenced by main().

uint8_t Rx1_Buffer[BUFFER_SIZE1]

Definition at line 104 of file STM32F10x_StdPeriph_Examples/I2C/EEPROM/main.c.

Referenced by main().

uint8_t Rx2_Buffer[BUFFER_SIZE2]

Definition at line 104 of file STM32F10x_StdPeriph_Examples/I2C/EEPROM/main.c.

Referenced by main().

volatile TestStatus TransferStatus1 = FAILED

Definition at line 105 of file STM32F10x_StdPeriph_Examples/I2C/EEPROM/main.c.

volatile TestStatus TransferStatus2 = FAILED

Definition at line 105 of file STM32F10x_StdPeriph_Examples/I2C/EEPROM/main.c.

uint8_t Tx1_Buffer[]

Definition at line 64 of file STM32F10x_StdPeriph_Examples/I2C/EEPROM/main.c.

Referenced by main().

uint8_t Tx2_Buffer[]
Initial value:
"/* STM32F10xx I2C Firmware Library EEPROM driver example: \
                        buffer 2 transfer into address sEE_WRITE_ADDRESS2 */"

Definition at line 102 of file STM32F10x_StdPeriph_Examples/I2C/EEPROM/main.c.

Referenced by main().


STM32F10x Standard Peripherals Firmware Library: I2C_TSENSOR

Defines | Enumerations | Functions | Variables

I2C_TSENSOR

STM32F10x_StdPeriph_Examples

Defines

#define | TEMPERATURE_THYS 31
#define | TEMPERATURE_TOS 32

Enumerations

enum TestStatus {
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED
}

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | I2C1_ER_IRQHandler (void)
This function handles I2C2 Error interrupt request.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | NVIC_Configuration (void)
Configures the different interrupt.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

uint32_t | index = 0
__IO uint8_t | SMbusAlertOccurred
__IO uint8_t | SMbusAlertOccurred = 0
static uint8_t | TempCelsiusDisplay [] = " +abc.d C "
static uint8_t | TempFahrenheitDisplay [] = " +abc.d F "
static int32_t | TempValue = 0
static int32_t | TempValueCelsius = 0
static int32_t | TempValueFahrenheit = 0

Define Documentation

#define TEMPERATURE_THYS 31

Definition at line 50 of file STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/main.c.

Referenced by main().

#define TEMPERATURE_TOS 32

Definition at line 51 of file STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/main.c.

Referenced by main().

Enumeration Type Documentation

enum TestStatus
Enumerator:
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED

Definition at line 47 of file STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/main.c.

Function Documentation

void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 89 of file STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 124 of file STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/stm32f10x_it.c.

void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 63 of file STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/stm32f10x_it.c.

void I2C1_ER_IRQHandler ( void )

This function handles I2C2 Error interrupt request.

Parameters:
None
Return values:
None

Definition at line 157 of file STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/stm32f10x_it.c.

References I2C_ClearITPendingBit(), I2C_GetITStatus(), I2C_IT_AF, I2C_IT_ARLO, I2C_IT_BERR, I2C_IT_OVR, I2C_IT_PECERR, I2C_IT_SMBALERT, I2C_IT_TIMEOUT, LM75_I2C, and SMbusAlertOccurred.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 69 of file STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/main.c.

References DISABLE, ENABLE, I2C_ClearITPendingBit(), I2C_IT_SMBALERT, index, LCD_Clear(), LCD_ClearLine(), LCD_COLOR_BLUE, LCD_COLOR_GREEN, LCD_COLOR_RED, LCD_COLOR_WHITE, LCD_DisplayChar(), LCD_DisplayStringLine(), LCD_LINE_0, LCD_LINE_2, LCD_LINE_3, LCD_LINE_4, LCD_LINE_5, LCD_LINE_6, LCD_LINE_7, LCD_SetBackColor(), LCD_SetTextColor(), LM75_GetStatus(), LM75_I2C, LM75_Init(), LM75_ReadTemp(), LM75_REG_THYS, LM75_REG_TOS, LM75_WriteConfReg(), LM75_WriteReg(), NVIC_Configuration(), RCC_AHBPeriph_FSMC, RCC_AHBPeriphClockCmd(), SMbusAlertOccurred, STM32100B_LCD_Init(), STM32100E_LCD_Init(), STM3210B_LCD_Init(), STM3210E_LCD_Init(), SUCCESS, TempCelsiusDisplay, TEMPERATURE_THYS, TEMPERATURE_TOS, TempFahrenheitDisplay, TempValue, TempValueCelsius, and TempValueFahrenheit.

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 76 of file STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 54 of file STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/stm32f10x_it.c.

void NVIC_Configuration ( void )

Configures the different interrupt.

Parameters:
None
Return values:
None
void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 133 of file STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/stm32f10x_it.c.

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 115 of file STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 142 of file STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/stm32f10x_it.c.

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 102 of file STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/stm32f10x_it.c.

Variable Documentation

uint32_t index = 0

Definition at line 59 of file STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/main.c.

Referenced by CheckBackupReg(), CRC_CalcBlockCRC(), delay(), EXTI0_IRQHandler(), Fill_Buffer(), FindSCR(), LCD_Clear(), LCD_DrawChar(), LCD_DrawMonoPict(), LCD_WriteBMP(), main(), NAND_ReadSmallPage(), NAND_ReadSpareArea(), NAND_WriteSmallPage(), NAND_WriteSpareArea(), OneNAND_AsynchronousRead(), OneNAND_SynchronousRead(), PhysicalAddressDiscovery(), and WriteToBackupReg().

__IO uint8_t SMbusAlertOccurred

Definition at line 58 of file STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/main.c.

Referenced by I2C1_ER_IRQHandler(), and main().

__IO uint8_t SMbusAlertOccurred = 0

Definition at line 58 of file STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/main.c.

Referenced by I2C1_ER_IRQHandler(), and main().

uint8_t TempCelsiusDisplay[] = " +abc.d C " [static]

Definition at line 55 of file STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/main.c.

Referenced by main().

uint8_t TempFahrenheitDisplay[] = " +abc.d F " [static]

Definition at line 56 of file STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/main.c.

Referenced by main().

int32_t TempValue = 0 [static]

Definition at line 57 of file STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/main.c.

Referenced by main().

int32_t TempValueCelsius = 0

Definition at line 57 of file STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/main.c.

Referenced by main().

int32_t TempValueFahrenheit = 0

Definition at line 57 of file STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/main.c.

Referenced by main().


STM32F10x Standard Peripherals Firmware Library: I2C_IOExpander

Defines | Functions

I2C_IOExpander

STM32F10x_StdPeriph_Examples

Defines

#define | MESSAGE2 " Example on how to "
#define | MESSAGE3 " use the IO Expander"

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | EXTI15_10_IRQHandler (void)
This function handles External lines 15 to 10 interrupt request.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSVC exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Define Documentation

#define MESSAGE2 " Example on how to "

Definition at line 41 of file STM32F10x_StdPeriph_Examples/I2C/IOExpander/main.c.

Referenced by main().

#define MESSAGE3 " use the IO Expander"

Definition at line 42 of file STM32F10x_StdPeriph_Examples/I2C/IOExpander/main.c.

Referenced by main().

Function Documentation

void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 87 of file STM32F10x_StdPeriph_Examples/I2C/IOExpander/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 122 of file STM32F10x_StdPeriph_Examples/I2C/IOExpander/stm32f10x_it.c.

void EXTI15_10_IRQHandler ( void )

This function handles External lines 15 to 10 interrupt request.

Parameters:
None
Return values:
None

Definition at line 148 of file STM32F10x_StdPeriph_Examples/I2C/IOExpander/stm32f10x_it.c.

void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 61 of file STM32F10x_StdPeriph_Examples/I2C/IOExpander/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

Definition at line 54 of file STM32F10x_StdPeriph_Examples/I2C/IOExpander/main.c.

References Black, Blue, IOE_Config(), IOE_ITConfig(), IOE_ITSRC_JOYSTICK, IOE_ITSRC_TSC, IOE_JoyStickGetState(), IOE_OK, IOE_TS_GetState(), JOY_CENTER, JOY_DOWN, JOY_LEFT, JOY_NONE, JOY_RIGHT, JOY_State_TypeDef, JOY_UP, LCD_Clear(), LCD_DisplayStringLine(), LCD_DrawRect(), LCD_SetBackColor(), LCD_SetTextColor(), LED1, LED2, LED3, LED4, Line0, Line1, Line2, Line4, Line5, Line6, Line7, MESSAGE1, MESSAGE2, MESSAGE3, Red, STM32100E_LCD_Init(), STM3210C_LCD_Init(), STM_EVAL_LEDInit(), STM_EVAL_LEDOff(), STM_EVAL_LEDOn(), TS_STATE::TouchDetected, TS_State, White, TS_STATE::X, TS_STATE::Y, and Yellow.

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 74 of file STM32F10x_StdPeriph_Examples/I2C/IOExpander/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 52 of file STM32F10x_StdPeriph_Examples/I2C/IOExpander/stm32f10x_it.c.

void PendSV_Handler ( void )

This function handles PendSVC exception.

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 131 of file STM32F10x_StdPeriph_Examples/I2C/IOExpander/stm32f10x_it.c.

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 113 of file STM32F10x_StdPeriph_Examples/I2C/IOExpander/stm32f10x_it.c.

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 100 of file STM32F10x_StdPeriph_Examples/I2C/IOExpander/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: I2S_Interrupt

Enumerations | Functions | Variables

I2S_Interrupt

STM32F10x_StdPeriph_Examples

Enumerations

enum TestStatus {
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED
}

Functions

TestStatus | Buffercmp24bits (uint16_t *pBuffer1, uint16_t *pBuffer2, uint16_t BufferLength)
Compares two buffers in 24 bits data format.
void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | GPIO_Configuration (void)
Configures the different GPIO ports.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | NVIC_Configuration (void)
Configure the nested vectored interrupt controller.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | RCC_Configuration (void)
Configures the different system clocks.
void | SPI2_IRQHandler (void)
This function handles SPI2 global interrupt request.
void | SPI3_IRQHandler (void)
This function handles SPI3 global interrupt request.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

ErrorStatus HSEStartUpStatus
uint16_t | I2S2_Buffer_Rx [32]
uint16_t | I2S2_Buffer_Rx [32]
const uint16_t | I2S3_Buffer_Tx [32]
const uint16_t | I2S3_Buffer_Tx [32]
I2S_InitTypeDef I2S_InitStructure
__IO uint32_t | RxIdx = 0
__IO uint32_t | RxIdx
TestStatus | TransferStatus1 = FAILED
TestStatus | TransferStatus2 = FAILED
__IO uint32_t | TxIdx
__IO uint32_t | TxIdx = 0

Enumeration Type Documentation

enum TestStatus
Enumerator:
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED

Definition at line 34 of file STM32F10x_StdPeriph_Examples/I2S/Interrupt/main.c.

Function Documentation

TestStatus Buffercmp24bits | ( | uint16_t * | pBuffer1,
 |  | uint16_t * | pBuffer2,
 |  | uint16_t | BufferLength
 | ) |  |

Compares two buffers in 24 bits data format.

Parameters:
pBuffer1,pBuffer2,: buffers to be compared.
BufferLength,: buffer's length
Return values:
PASSED,: pBuffer1 identical to pBuffer2 FAILED: pBuffer1 differs from pBuffer2

Definition at line 387 of file STM32F10x_StdPeriph_Examples/I2S/Interrupt/main.c.

References FAILED, and PASSED.

Referenced by main().

void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 88 of file STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 112 of file STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_it.c.

void GPIO_Configuration ( void )

Configures the different GPIO ports.

Parameters:
None
Return values:
None

Definition at line 222 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 64 of file STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 66 of file STM32F10x_StdPeriph_Examples/I2S/Interrupt/main.c.

References Buffercmp(), Buffercmp24bits(), ENABLE, GPIO_Configuration(), I2S2_Buffer_Rx, I2S3_Buffer_Tx, I2S_InitTypeDef::I2S_AudioFreq, I2S_AudioFreq_16k, I2S_AudioFreq_48k, I2S_Cmd(), I2S_InitTypeDef::I2S_CPOL, I2S_CPOL_Low, I2S_InitTypeDef::I2S_DataFormat, I2S_DataFormat_16bextended, I2S_DataFormat_24b, I2S_Init(), I2S_InitTypeDef::I2S_MCLKOutput, I2S_MCLKOutput_Disable, I2S_InitTypeDef::I2S_Mode, I2S_Mode_MasterTx, I2S_Mode_SlaveRx, I2S_InitTypeDef::I2S_Standard, I2S_Standard_Phillips, NVIC_Configuration(), RCC_Configuration(), RxIdx, SPI2, SPI3, SPI_I2S_DeInit(), SPI_I2S_IT_RXNE, SPI_I2S_IT_TXE, SPI_I2S_ITConfig(), TransferStatus1, TransferStatus2, and TxIdx.

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 76 of file STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 55 of file STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_it.c.

void NVIC_Configuration ( void )

Configure the nested vectored interrupt controller.

Parameters:
None
Return values:
None
void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 130 of file STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_it.c.

void RCC_Configuration ( void )

Configures the different system clocks.

Parameters:
None
Return values:
None

Definition at line 203 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void SPI2_IRQHandler ( void )

This function handles SPI2 global interrupt request.

Parameters:
None
Return values:
None

Definition at line 174 of file STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_it.c.

void SPI3_IRQHandler ( void )

This function handles SPI3 global interrupt request.

Parameters:
None
Return values:
None

Definition at line 152 of file STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_it.c.

References DISABLE, I2S3_Buffer_Tx, RxIdx, SET, SPI3, SPI_I2S_GetITStatus(), SPI_I2S_IT_TXE, SPI_I2S_ITConfig(), SPI_I2S_SendData(), and TxIdx.

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 121 of file STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 139 of file STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_it.c.

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 100 of file STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_it.c.

Variable Documentation

ErrorStatus HSEStartUpStatus

Definition at line 50 of file STM32F10x_StdPeriph_Examples/I2S/Interrupt/main.c.

Referenced by SetSysClockTo24(), SetSysClockTo36(), SetSysClockTo48(), SetSysClockTo56(), SetSysClockTo72(), SetSysClockToHSE(), and SYSCLKConfig_STOP().

uint16_t I2S2_Buffer_Rx[32]

Definition at line 47 of file STM32F10x_StdPeriph_Examples/I2S/Interrupt/main.c.

Referenced by main(), and SPI2_IRQHandler().

uint16_t I2S2_Buffer_Rx[32]

Definition at line 47 of file STM32F10x_StdPeriph_Examples/I2S/Interrupt/main.c.

Referenced by main(), and SPI2_IRQHandler().

const uint16_t I2S3_Buffer_Tx[32]

Definition at line 40 of file STM32F10x_StdPeriph_Examples/I2S/Interrupt/main.c.

Referenced by main(), and SPI3_IRQHandler().

const uint16_t I2S3_Buffer_Tx[32]
Initial value:
 {0x0102, 0x0304, 0x0506, 0x0708, 0x090A, 0x0B0C,
                                     0x0D0E, 0x0F10, 0x1112, 0x1314, 0x1516, 0x1718,
                                     0x191A, 0x1B1C, 0x1D1E, 0x1F20, 0x2122, 0x2324,
                                     0x2526, 0x2728, 0x292A, 0x2B2C, 0x2D2E, 0x2F30,
                                     0x3132, 0x3334, 0x3536, 0x3738, 0x393A, 0x3B3C,
                                     0x3D3E, 0x3F40}

Definition at line 40 of file STM32F10x_StdPeriph_Examples/I2S/Interrupt/main.c.

Referenced by main(), and SPI3_IRQHandler().

I2S_InitTypeDef I2S_InitStructure

Definition at line 39 of file STM32F10x_StdPeriph_Examples/I2S/Interrupt/main.c.

__IO uint32_t RxIdx = 0

Definition at line 48 of file STM32F10x_StdPeriph_Examples/I2S/Interrupt/main.c.

Referenced by main(), SPI2_IRQHandler(), and SPI3_IRQHandler().

__IO uint32_t RxIdx

Definition at line 48 of file STM32F10x_StdPeriph_Examples/I2S/Interrupt/main.c.

TestStatus TransferStatus1 = FAILED

Definition at line 49 of file STM32F10x_StdPeriph_Examples/I2S/Interrupt/main.c.

TestStatus TransferStatus2 = FAILED

Definition at line 49 of file STM32F10x_StdPeriph_Examples/I2S/Interrupt/main.c.

__IO uint32_t TxIdx

Definition at line 48 of file STM32F10x_StdPeriph_Examples/I2S/Interrupt/main.c.

__IO uint32_t TxIdx = 0

Definition at line 48 of file STM32F10x_StdPeriph_Examples/I2S/Interrupt/main.c.

Referenced by main(), SPI1_IRQHandler(), and SPI3_IRQHandler().


STM32F10x Standard Peripherals Firmware Library: I2S_SPI_I2S_Switch

Defines | Enumerations | Functions | Variables

I2S_SPI_I2S_Switch

STM32F10x_StdPeriph_Examples

Defines

#define | BufferSize 32

Enumerations

enum TestStatus {
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED
}

Functions

TestStatus | Buffercmp (uint16_t *pBuffer1, uint16_t *pBuffer2, uint16_t BufferLength)
Compares two buffers.
void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | GPIO_Configuration (void)
Configures the different GPIO ports.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | RCC_Configuration (void)
Configures the different system clocks.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

ErrorStatus HSEStartUpStatus
__IO uint16_t | I2S2_Buffer_Rx [BufferSize]
uint16_t | I2S3_Buffer_Tx [BufferSize]
I2S_InitTypeDef I2S_InitStructure
__IO uint8_t | RxIdx = 0
__IO uint16_t | SPI2_Buffer_Rx [BufferSize]
uint16_t | SPI3_Buffer_Tx [BufferSize]
SPI_InitTypeDef SPI_InitStructure
volatile TestStatus | TransferStatus1 = FAILED
volatile TestStatus | TransferStatus2 = FAILED
volatile TestStatus | TransferStatus3 = FAILED
__IO uint8_t | TxIdx = 0

Define Documentation

#define BufferSize 32

Definition at line 39 of file STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/main.c.

Referenced by main().

Enumeration Type Documentation

enum TestStatus
Enumerator:
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED

Definition at line 36 of file STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/main.c.

Function Documentation

TestStatus Buffercmp | ( | uint16_t * | pBuffer1,
 |  | uint16_t * | pBuffer2,
 |  | uint16_t | BufferLength
 | ) |  |

Compares two buffers.

Parameters:
pBuffer1,pBuffer2,: buffers to be compared.
BufferLength,: buffer's length
Return values:
PASSED,: pBuffer1 identical to pBuffer2 FAILED: pBuffer1 differs from pBuffer2
void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 84 of file STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 108 of file STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/stm32f10x_it.c.

void GPIO_Configuration ( void )

Configures the different GPIO ports.

Parameters:
None
Return values:
None

Definition at line 222 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 60 of file STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 76 of file STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/main.c.

References Buffercmp(), BufferSize, ENABLE, GPIO_Configuration(), I2S2_Buffer_Rx, I2S3_Buffer_Tx, I2S_InitTypeDef::I2S_AudioFreq, I2S_AudioFreq_48k, I2S_Cmd(), I2S_InitTypeDef::I2S_CPOL, I2S_CPOL_Low, I2S_InitTypeDef::I2S_DataFormat, I2S_DataFormat_16bextended, I2S_Init(), I2S_InitTypeDef::I2S_MCLKOutput, I2S_MCLKOutput_Disable, I2S_InitTypeDef::I2S_Mode, I2S_Mode_MasterRx, I2S_Mode_MasterTx, I2S_Mode_SlaveRx, I2S_Mode_SlaveTx, I2S_InitTypeDef::I2S_Standard, I2S_Standard_Phillips, RCC_Configuration(), RESET, RxIdx, SPI2, SPI2_Buffer_Rx, SPI3, SPI3_Buffer_Tx, SPI_InitTypeDef::SPI_BaudRatePrescaler, SPI_BaudRatePrescaler_4, SPI_Cmd(), SPI_InitTypeDef::SPI_CPHA, SPI_CPHA_2Edge, SPI_InitTypeDef::SPI_CPOL, SPI_CPOL_Low, SPI_InitTypeDef::SPI_CRCPolynomial, SPI_InitTypeDef::SPI_DataSize, SPI_DataSize_16b, SPI_InitTypeDef::SPI_Direction, SPI_Direction_1Line_Tx, SPI_Direction_2Lines_RxOnly, SPI_InitTypeDef::SPI_FirstBit, SPI_FirstBit_MSB, SPI_I2S_DeInit(), SPI_I2S_FLAG_RXNE, SPI_I2S_FLAG_TXE, SPI_I2S_GetFlagStatus(), SPI_I2S_ReceiveData(), SPI_I2S_SendData(), SPI_Init(), SPI_InitTypeDef::SPI_Mode, SPI_Mode_Master, SPI_Mode_Slave, SPI_InitTypeDef::SPI_NSS, SPI_NSS_Soft, TransferStatus1, TransferStatus2, TransferStatus3, and TxIdx.

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 72 of file STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 51 of file STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/stm32f10x_it.c.

void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 126 of file STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/stm32f10x_it.c.

void RCC_Configuration ( void )

Configures the different system clocks.

Parameters:
None
Return values:
None

Definition at line 203 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 117 of file STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 135 of file STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/stm32f10x_it.c.

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 96 of file STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/stm32f10x_it.c.

Variable Documentation

ErrorStatus HSEStartUpStatus

Definition at line 64 of file STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/main.c.

__IO uint16_t I2S2_Buffer_Rx[BufferSize]

Definition at line 59 of file STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/main.c.

uint16_t I2S3_Buffer_Tx[BufferSize]
Initial value:
 {0x0102, 0x0304, 0x0506, 0x0708, 0x090A, 0x0B0C,
                                  0x0D0E, 0x0F10, 0x1112, 0x1314, 0x1516, 0x1718,
                                  0x191A, 0x1B1C, 0x1D1E, 0x1F20, 0x2122, 0x2324,
                                  0x2526, 0x2728, 0x292A, 0x2B2C, 0x2D2E, 0x2F30,
                                  0x3132, 0x3334, 0x3536, 0x3738, 0x393A, 0x3B3C,
                                  0x3D3E, 0x3F40}

Definition at line 45 of file STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/main.c.

I2S_InitTypeDef I2S_InitStructure

Definition at line 43 of file STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/main.c.

__IO uint8_t RxIdx = 0

Definition at line 61 of file STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/main.c.

__IO uint16_t SPI2_Buffer_Rx[BufferSize]

Definition at line 60 of file STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/main.c.

Referenced by main().

uint16_t SPI3_Buffer_Tx[BufferSize]
Initial value:
 {0x5152, 0x5354, 0x5556, 0x5758, 0x595A, 0x5B5C,
                                  0x5D5E, 0x5F60, 0x6162, 0x6364, 0x6566, 0x6768,
                                  0x696A, 0x6B6C, 0x6D6E, 0x6F70, 0x7172, 0x7374,
                                  0x7576, 0x7778, 0x797A, 0x7B7C, 0x7D7E, 0x7F80,
                                  0x8182, 0x8384, 0x8586, 0x8788, 0x898A, 0x8B8C,
                                  0x8D8E, 0x8F90}

Definition at line 52 of file STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/main.c.

Referenced by main().

SPI_InitTypeDef SPI_InitStructure

Definition at line 44 of file STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/main.c.

volatile TestStatus TransferStatus1 = FAILED

Definition at line 62 of file STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/main.c.

volatile TestStatus TransferStatus2 = FAILED

Definition at line 62 of file STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/main.c.

volatile TestStatus TransferStatus3 = FAILED

Definition at line 63 of file STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/main.c.

Referenced by main().

__IO uint8_t TxIdx = 0

Definition at line 61 of file STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/main.c.


STM32F10x Standard Peripherals Firmware Library: IWDG_Reset

Defines | Functions | Variables

IWDG_Reset

STM32F10x_StdPeriph_Examples

Defines

#define | LSI_TIM_MEASURE

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | Delay (__IO uint32_t nTime)
Inserts a delay time.
void | EXTI9_5_IRQHandler (void)
This function handles External lines 9 to 5 interrupt request.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | TIM5_ConfigForLSI (void)
Configures TIM5 to measure the LSI oscillator frequency.
void | TIM5_IRQHandler (void)
This function handles TIM5 global interrupt request.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

__IO uint32_t | Capture = 0
__IO uint16_t | CaptureNumber
__IO uint16_t | CaptureNumber = 0
__IO uint16_t | IC1ReadValue1 = 0
__IO uint16_t | IC1ReadValue2 = 0
uint32_t | LsiFreq
__IO uint32_t | LsiFreq = 40000
__IO uint32_t | TimingDelay
__IO uint32_t | TimingDelay = 0

Define Documentation

#define LSI_TIM_MEASURE

Definition at line 39 of file STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/main.c.

Function Documentation

void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 91 of file STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 115 of file STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_it.c.

void Delay ( __IO uint32_t nTime )

Inserts a delay time.

Parameters:
nTime,: specifies the delay time length, in milliseconds.
Return values:
None
void EXTI9_5_IRQHandler ( void )

This function handles External lines 9 to 5 interrupt request.

This function handles EXTI Lines 9 to 5 interrupts requests.

Parameters:
None
Return values:
None

Definition at line 156 of file STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_it.c.

References EXTI_ClearITPendingBit(), EXTI_GetITStatus(), KEY_BUTTON_EXTI_LINE, and RESET.

void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 67 of file STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 58 of file STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/main.c.

References BUTTON_KEY, BUTTON_MODE_EXTI, CaptureNumber, Delay(), DISABLE, ENABLE, IWDG_Enable(), IWDG_Prescaler_32, IWDG_ReloadCounter(), IWDG_SetPrescaler(), IWDG_SetReload(), IWDG_WriteAccess_Enable, IWDG_WriteAccessCmd(), LED1, LED2, LsiFreq, RCC_ClearFlag(), RCC_FLAG_IWDGRST, RCC_FLAG_LSIRDY, RCC_GetFlagStatus(), RCC_LSICmd(), RESET, STM_EVAL_LEDInit(), STM_EVAL_LEDOff(), STM_EVAL_LEDOn(), STM_EVAL_LEDToggle(), STM_EVAL_PBInit(), SystemCoreClock, TIM5, TIM5_ConfigForLSI(), TIM_IT_CC4, and TIM_ITConfig().

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 79 of file STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 58 of file STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_it.c.

void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 133 of file STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_it.c.

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 124 of file STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 142 of file STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_it.c.

References TimingDelay.

void TIM5_ConfigForLSI ( void )

Configures TIM5 to measure the LSI oscillator frequency.

Parameters:
None
Return values:
None

Definition at line 171 of file STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/main.c.

References ENABLE, GPIO_PinRemapConfig(), GPIO_Remap_TIM5CH4_LSI, NVIC_Init(), NVIC_InitStructure, NVIC_InitTypeDef::NVIC_IRQChannel, NVIC_InitTypeDef::NVIC_IRQChannelCmd, NVIC_InitTypeDef::NVIC_IRQChannelPreemptionPriority, NVIC_InitTypeDef::NVIC_IRQChannelSubPriority, RCC_APB1Periph_TIM5, RCC_APB1PeriphClockCmd(), TIM5, TIM_ICInitTypeDef::TIM_Channel, TIM_Channel_4, TIM_Cmd(), TIM_ICInitTypeDef::TIM_ICFilter, TIM_ICInit(), TIM_ICInitStructure, TIM_ICInitTypeDef::TIM_ICPolarity, TIM_ICPolarity_Rising, TIM_ICInitTypeDef::TIM_ICPrescaler, TIM_ICPSC_DIV8, TIM_ICInitTypeDef::TIM_ICSelection, TIM_ICSelection_DirectTI, TIM_IT_CC4, TIM_ITConfig(), TIM_PrescalerConfig(), and TIM_PSCReloadMode_Immediate.

Referenced by main().

void TIM5_IRQHandler ( void )

This function handles TIM5 global interrupt request.

Parameters:
None
Return values:
None

Definition at line 175 of file STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_it.c.

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 103 of file STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_it.c.

Variable Documentation

__IO uint32_t Capture = 0

Definition at line 43 of file STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_it.c.

Referenced by TIM3_IRQHandler(), and TIM5_IRQHandler().

__IO uint16_t CaptureNumber

Definition at line 42 of file STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_it.c.

Referenced by main(), TIM3_IRQHandler(), and TIM5_IRQHandler().

__IO uint16_t CaptureNumber = 0

Definition at line 42 of file STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_it.c.

__IO uint16_t IC1ReadValue1 = 0

Definition at line 41 of file STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_it.c.

Referenced by TIM5_IRQHandler().

__IO uint16_t IC1ReadValue2 = 0

Definition at line 41 of file STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_it.c.

Referenced by TIM5_IRQHandler().

uint32_t LsiFreq

Definition at line 44 of file STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/main.c.

Referenced by main(), and TIM5_IRQHandler().

__IO uint32_t LsiFreq = 40000

Definition at line 44 of file STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/main.c.

Referenced by main(), and TIM5_IRQHandler().

__IO uint32_t TimingDelay

Definition at line 43 of file STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/main.c.

__IO uint32_t TimingDelay = 0

Definition at line 43 of file STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/main.c.


STM32F10x Standard Peripherals Firmware Library: Lib_DEBUG_RunTime_Check

Defines | Functions | Variables

Lib_DEBUG_RunTime_Check

STM32F10x_StdPeriph_Examples

Defines

#define | PUTCHAR_PROTOTYPE int fputc(int ch, FILE *f)

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | debug (void)
This function initialize peripherals pointers.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

ADC_TypeDef * ADC1_DBG
ADC_TypeDef * ADC2_DBG
ADC_TypeDef * ADC3_DBG
AFIO_TypeDef * AFIO_DBG
BKP_TypeDef * BKP_DBG
CAN_TypeDef * CAN1_DBG
CEC_TypeDef * CEC_DBG
CRC_TypeDef * CRC_DBG
DAC_TypeDef * DAC_DBG
DBGMCU_TypeDef * DBGMCU_DBG
DMA_Channel_TypeDef * DMA1_Channel1_DBG
DMA_Channel_TypeDef * DMA1_Channel2_DBG
DMA_Channel_TypeDef * DMA1_Channel3_DBG
DMA_Channel_TypeDef * DMA1_Channel4_DBG
DMA_Channel_TypeDef * DMA1_Channel5_DBG
DMA_Channel_TypeDef * DMA1_Channel6_DBG
DMA_Channel_TypeDef * DMA1_Channel7_DBG
DMA_TypeDef * DMA1_DBG
DMA_Channel_TypeDef * DMA2_Channel1_DBG
DMA_Channel_TypeDef * DMA2_Channel2_DBG
DMA_Channel_TypeDef * DMA2_Channel3_DBG
DMA_Channel_TypeDef * DMA2_Channel4_DBG
DMA_Channel_TypeDef * DMA2_Channel5_DBG
DMA_TypeDef * DMA2_DBG
EXTI_TypeDef * EXTI_DBG
FLASH_TypeDef * FLASH_DBG
FSMC_Bank1_TypeDef * FSMC_Bank1_DBG
FSMC_Bank1E_TypeDef * FSMC_Bank1E_DBG
FSMC_Bank2_TypeDef * FSMC_Bank2_DBG
FSMC_Bank3_TypeDef * FSMC_Bank3_DBG
FSMC_Bank4_TypeDef * FSMC_Bank4_DBG
GPIO_TypeDef * GPIOA_DBG
GPIO_TypeDef * GPIOB_DBG
GPIO_TypeDef * GPIOC_DBG
GPIO_TypeDef * GPIOD_DBG
GPIO_TypeDef * GPIOE_DBG
GPIO_TypeDef * GPIOF_DBG
GPIO_TypeDef * GPIOG_DBG
I2C_TypeDef * I2C1_DBG
I2C_TypeDef * I2C2_DBG
IWDG_TypeDef * IWDG_DBG
NVIC_Type * | NVIC_DBG
OB_TypeDef * OB_DBG
PWR_TypeDef * PWR_DBG
RCC_TypeDef * RCC_DBG
RTC_TypeDef * RTC_DBG
SCB_Type * | SCB_DBG
SDIO_TypeDef * SDIO_DBG
SPI_TypeDef * SPI1_DBG
SPI_TypeDef * SPI2_DBG
SPI_TypeDef * SPI3_DBG
SysTick_Type * | SysTick_DBG
TIM_TypeDef * TIM15_DBG
TIM_TypeDef * TIM16_DBG
TIM_TypeDef * TIM17_DBG
TIM_TypeDef * TIM1_DBG
TIM_TypeDef * TIM2_DBG
TIM_TypeDef * TIM3_DBG
TIM_TypeDef * TIM4_DBG
TIM_TypeDef * TIM5_DBG
TIM_TypeDef * TIM6_DBG
TIM_TypeDef * TIM7_DBG
TIM_TypeDef * TIM8_DBG
USART_TypeDef * UART4_DBG
USART_TypeDef * UART5_DBG
USART_TypeDef * USART1_DBG
USART_TypeDef * USART2_DBG
USART_TypeDef * USART3_DBG
USART_InitTypeDef USART_InitStructure
WWDG_TypeDef * WWDG_DBG

Define Documentation

#define PUTCHAR_PROTOTYPE int fputc(int ch, FILE *f)

Definition at line 48 of file STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/main.c.

Function Documentation

void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 86 of file STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/stm32f10x_it.c.

void debug ( void )

This function initialize peripherals pointers.

Parameters:
None
Return values:
None

Definition at line 115 of file stm32f10x_ip_dbg.c.

References ADC1_BASE, ADC2_BASE, ADC3_BASE, AFIO_BASE, BKP_BASE, CAN1_BASE, CEC_BASE, CRC_BASE, DAC_BASE, DBGMCU_BASE, DMA1_BASE, DMA1_Channel1_BASE, DMA1_Channel2_BASE, DMA1_Channel3_BASE, DMA1_Channel4_BASE, DMA1_Channel5_BASE, DMA1_Channel6_BASE, DMA1_Channel7_BASE, DMA2_BASE, DMA2_Channel1_BASE, DMA2_Channel2_BASE, DMA2_Channel3_BASE, DMA2_Channel4_BASE, DMA2_Channel5_BASE, EXTI_BASE, FLASH_R_BASE, FSMC_Bank1_R_BASE, FSMC_Bank1E_R_BASE, FSMC_Bank2_R_BASE, FSMC_Bank3_R_BASE, FSMC_Bank4_R_BASE, GPIOA_BASE, GPIOB_BASE, GPIOC_BASE, GPIOD_BASE, GPIOE_BASE, GPIOF_BASE, GPIOG_BASE, I2C1_BASE, I2C2_BASE, IWDG_BASE, NVIC_DBG, OB_BASE, PWR_BASE, RCC_BASE, RTC_BASE, SCB_DBG, SDIO_BASE, SPI1_BASE, SPI2_BASE, SPI3_BASE, SysTick_DBG, TIM15_BASE, TIM16_BASE, TIM17_BASE, TIM1_BASE, TIM2_BASE, TIM3_BASE, TIM4_BASE, TIM5_BASE, TIM6_BASE, TIM7_BASE, TIM8_BASE, UART4_BASE, UART5_BASE, USART1_BASE, USART2_BASE, USART3_BASE, and WWDG_BASE.

Referenced by main().

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 121 of file STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/stm32f10x_it.c.

void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 60 of file STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 58 of file STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/main.c.

References COM1, debug(), ENABLE, GPIO_Init(), GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_Out_PP, GPIO_InitTypeDef::GPIO_Pin, GPIO_Pin_6, GPIOA, RCC_APB1PeriphClockCmd(), RCC_APB2Periph_SPI1, STM_EVAL_COMInit(), USART_InitTypeDef::USART_BaudRate, USART_InitTypeDef::USART_HardwareFlowControl, USART_HardwareFlowControl_None, USART_InitTypeDef::USART_Mode, USART_Mode_Rx, USART_Mode_Tx, USART_InitTypeDef::USART_Parity, USART_Parity_No, USART_InitTypeDef::USART_StopBits, USART_StopBits_1, USART_InitTypeDef::USART_WordLength, and USART_WordLength_8b.

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 73 of file STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 51 of file STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/stm32f10x_it.c.

void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 130 of file STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/stm32f10x_it.c.

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 112 of file STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 139 of file STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/stm32f10x_it.c.

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 99 of file STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/stm32f10x_it.c.

Variable Documentation

ADC_TypeDef* ADC1_DBG

Definition at line 68 of file stm32f10x_ip_dbg.c.

ADC_TypeDef* ADC2_DBG

Definition at line 69 of file stm32f10x_ip_dbg.c.

ADC_TypeDef* ADC3_DBG

Definition at line 74 of file stm32f10x_ip_dbg.c.

AFIO_TypeDef* AFIO_DBG

Definition at line 59 of file stm32f10x_ip_dbg.c.

BKP_TypeDef* BKP_DBG

Definition at line 55 of file stm32f10x_ip_dbg.c.

CAN_TypeDef* CAN1_DBG

Definition at line 54 of file stm32f10x_ip_dbg.c.

CEC_TypeDef* CEC_DBG

Definition at line 58 of file stm32f10x_ip_dbg.c.

CRC_TypeDef* CRC_DBG

Definition at line 94 of file stm32f10x_ip_dbg.c.

DAC_TypeDef* DAC_DBG

Definition at line 57 of file stm32f10x_ip_dbg.c.

DBGMCU_TypeDef* DBGMCU_DBG

Definition at line 102 of file stm32f10x_ip_dbg.c.

DMA_Channel_TypeDef* DMA1_Channel1_DBG

Definition at line 81 of file stm32f10x_ip_dbg.c.

DMA_Channel_TypeDef* DMA1_Channel2_DBG

Definition at line 82 of file stm32f10x_ip_dbg.c.

DMA_Channel_TypeDef* DMA1_Channel3_DBG

Definition at line 83 of file stm32f10x_ip_dbg.c.

DMA_Channel_TypeDef* DMA1_Channel4_DBG

Definition at line 84 of file stm32f10x_ip_dbg.c.

DMA_Channel_TypeDef* DMA1_Channel5_DBG

Definition at line 85 of file stm32f10x_ip_dbg.c.

DMA_Channel_TypeDef* DMA1_Channel6_DBG

Definition at line 86 of file stm32f10x_ip_dbg.c.

DMA_Channel_TypeDef* DMA1_Channel7_DBG

Definition at line 87 of file stm32f10x_ip_dbg.c.

DMA_TypeDef* DMA1_DBG

Definition at line 79 of file stm32f10x_ip_dbg.c.

DMA_Channel_TypeDef* DMA2_Channel1_DBG

Definition at line 88 of file stm32f10x_ip_dbg.c.

DMA_Channel_TypeDef* DMA2_Channel2_DBG

Definition at line 89 of file stm32f10x_ip_dbg.c.

DMA_Channel_TypeDef* DMA2_Channel3_DBG

Definition at line 90 of file stm32f10x_ip_dbg.c.

DMA_Channel_TypeDef* DMA2_Channel4_DBG

Definition at line 91 of file stm32f10x_ip_dbg.c.

DMA_Channel_TypeDef* DMA2_Channel5_DBG

Definition at line 92 of file stm32f10x_ip_dbg.c.

DMA_TypeDef* DMA2_DBG

Definition at line 80 of file stm32f10x_ip_dbg.c.

EXTI_TypeDef* EXTI_DBG

Definition at line 60 of file stm32f10x_ip_dbg.c.

FLASH_TypeDef* FLASH_DBG

Definition at line 95 of file stm32f10x_ip_dbg.c.

FSMC_Bank1_TypeDef* FSMC_Bank1_DBG

Definition at line 97 of file stm32f10x_ip_dbg.c.

FSMC_Bank1E_TypeDef* FSMC_Bank1E_DBG

Definition at line 98 of file stm32f10x_ip_dbg.c.

FSMC_Bank2_TypeDef* FSMC_Bank2_DBG

Definition at line 99 of file stm32f10x_ip_dbg.c.

FSMC_Bank3_TypeDef* FSMC_Bank3_DBG

Definition at line 100 of file stm32f10x_ip_dbg.c.

FSMC_Bank4_TypeDef* FSMC_Bank4_DBG

Definition at line 101 of file stm32f10x_ip_dbg.c.

GPIO_TypeDef* GPIOA_DBG

Definition at line 61 of file stm32f10x_ip_dbg.c.

GPIO_TypeDef* GPIOB_DBG

Definition at line 62 of file stm32f10x_ip_dbg.c.

GPIO_TypeDef* GPIOC_DBG

Definition at line 63 of file stm32f10x_ip_dbg.c.

GPIO_TypeDef* GPIOD_DBG

Definition at line 64 of file stm32f10x_ip_dbg.c.

GPIO_TypeDef* GPIOE_DBG

Definition at line 65 of file stm32f10x_ip_dbg.c.

GPIO_TypeDef* GPIOF_DBG

Definition at line 66 of file stm32f10x_ip_dbg.c.

GPIO_TypeDef* GPIOG_DBG

Definition at line 67 of file stm32f10x_ip_dbg.c.

I2C_TypeDef* I2C1_DBG

Definition at line 52 of file stm32f10x_ip_dbg.c.

I2C_TypeDef* I2C2_DBG

Definition at line 53 of file stm32f10x_ip_dbg.c.

IWDG_TypeDef* IWDG_DBG

Definition at line 45 of file stm32f10x_ip_dbg.c.

NVIC_Type* NVIC_DBG

Definition at line 104 of file stm32f10x_ip_dbg.c.

Referenced by debug().

OB_TypeDef* OB_DBG

Definition at line 96 of file stm32f10x_ip_dbg.c.

PWR_TypeDef* PWR_DBG

Definition at line 56 of file stm32f10x_ip_dbg.c.

RCC_TypeDef* RCC_DBG

Definition at line 93 of file stm32f10x_ip_dbg.c.

RTC_TypeDef* RTC_DBG

Definition at line 43 of file stm32f10x_ip_dbg.c.

SCB_Type* SCB_DBG

Definition at line 105 of file stm32f10x_ip_dbg.c.

Referenced by debug().

SDIO_TypeDef* SDIO_DBG

Definition at line 78 of file stm32f10x_ip_dbg.c.

SPI_TypeDef* SPI1_DBG

Definition at line 71 of file stm32f10x_ip_dbg.c.

SPI_TypeDef* SPI2_DBG

Definition at line 46 of file stm32f10x_ip_dbg.c.

SPI_TypeDef* SPI3_DBG

Definition at line 47 of file stm32f10x_ip_dbg.c.

SysTick_Type* SysTick_DBG

Definition at line 103 of file stm32f10x_ip_dbg.c.

Referenced by debug().

TIM_TypeDef* TIM15_DBG

Definition at line 75 of file stm32f10x_ip_dbg.c.

TIM_TypeDef* TIM16_DBG

Definition at line 76 of file stm32f10x_ip_dbg.c.

TIM_TypeDef* TIM17_DBG

Definition at line 77 of file stm32f10x_ip_dbg.c.

TIM_TypeDef* TIM1_DBG

Definition at line 70 of file stm32f10x_ip_dbg.c.

TIM_TypeDef* TIM2_DBG

Definition at line 37 of file stm32f10x_ip_dbg.c.

TIM_TypeDef* TIM3_DBG

Definition at line 38 of file stm32f10x_ip_dbg.c.

TIM_TypeDef* TIM4_DBG

Definition at line 39 of file stm32f10x_ip_dbg.c.

TIM_TypeDef* TIM5_DBG

Definition at line 40 of file stm32f10x_ip_dbg.c.

TIM_TypeDef* TIM6_DBG

Definition at line 41 of file stm32f10x_ip_dbg.c.

TIM_TypeDef* TIM7_DBG

Definition at line 42 of file stm32f10x_ip_dbg.c.

TIM_TypeDef* TIM8_DBG

Definition at line 72 of file stm32f10x_ip_dbg.c.

USART_TypeDef* UART4_DBG

Definition at line 50 of file stm32f10x_ip_dbg.c.

USART_TypeDef* UART5_DBG

Definition at line 51 of file stm32f10x_ip_dbg.c.

USART_TypeDef* USART1_DBG

Definition at line 73 of file stm32f10x_ip_dbg.c.

USART_TypeDef* USART2_DBG

Definition at line 48 of file stm32f10x_ip_dbg.c.

USART_TypeDef* USART3_DBG

Definition at line 49 of file stm32f10x_ip_dbg.c.

USART_InitTypeDef USART_InitStructure

Definition at line 40 of file STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/main.c.

WWDG_TypeDef* WWDG_DBG

Definition at line 44 of file stm32f10x_ip_dbg.c.


STM32F10x Standard Peripherals Firmware Library: NVIC_DMA_WFIMode

Defines | Functions | Variables

NVIC_DMA_WFIMode

STM32F10x_StdPeriph_Examples

Defines

#define | USARTy_DMA1_Channel DMA1_Channel5
#define | USARTy_DMA1_IRQn DMA1_Channel5_IRQn
#define | USARTy_DR_Address 0x40013804

Functions

uint8_t | Buffercmp16 (uint16_t *pBuffer1, uint16_t *pBuffer2, uint16_t BufferLength)
Compares two buffers.
void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | Delay (__IO uint32_t nCount)
Inserts a delay time.
void | DMA1_Channel5_IRQHandler (void)
This function handles DMA1 Channel 5 interrupt request.
void | DMA1_Channel6_IRQHandler (void)
This function handles DMA1 Channel 6 interrupt request.
void | EXTI9_5_IRQHandler (void)
This function handles External lines 9 to 5 interrupt request.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | RCC_Configuration (void)
Configures the different system clocks.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

DMA_InitTypeDef DMA_InitStructure
uint16_t | DST_Buffer [10] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
uint16_t | DST_Buffer [10]
__IO uint32_t | LowPowerMode
__IO uint32_t | LowPowerMode = 0
NVIC_InitTypeDef NVIC_InitStructure
uint16_t | SRC_Buffer [10] = {0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39}
uint8_t | TestStatus = 0
USART_InitTypeDef USART_InitStructure

Define Documentation

#define USARTy_DMA1_Channel DMA1_Channel5

Definition at line 42 of file STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/main.c.

Referenced by DMA_Configuration().

#define USARTy_DMA1_IRQn DMA1_Channel5_IRQn

Definition at line 43 of file STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/main.c.

Referenced by main().

#define USARTy_DR_Address 0x40013804

Definition at line 41 of file STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/main.c.

Referenced by DMA_Configuration().

Function Documentation

uint8_t Buffercmp16 | ( | uint16_t * | pBuffer1,
 |  | uint16_t * | pBuffer2,
 |  | uint16_t | BufferLength
 | ) |  |

Compares two buffers.

Parameters:
pBuffer1,pBuffer2,: buffers to be compared.
BufferLength,: buffer's length
Return values:
0,: pBuffer1 identical to pBuffer2 1: pBuffer1 differs from pBuffer2

Definition at line 189 of file STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/main.c.

Referenced by DMA1_Channel5_IRQHandler(), and DMA1_Channel6_IRQHandler().

void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 94 of file STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 129 of file STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_it.c.

void Delay ( __IO uint32_t nCount )

Inserts a delay time.

Parameters:
nCount,: specifies the delay time length.
Return values:
None
void DMA1_Channel5_IRQHandler ( void )

This function handles DMA1 Channel 5 interrupt request.

Parameters:
None
Return values:
None

Definition at line 160 of file STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_it.c.

References Buffercmp16(), DMA1_IT_GL5, DMA1_IT_TC5, DMA_ClearITPendingBit(), DMA_GetITStatus(), DST_Buffer, LED2, LED3, SRC_Buffer, and STM_EVAL_LEDToggle().

void DMA1_Channel6_IRQHandler ( void )

This function handles DMA1 Channel 6 interrupt request.

Parameters:
None
Return values:
None

Definition at line 185 of file STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_it.c.

References Buffercmp16(), CurrDataCounterEnd, DMA1_Channel6, DMA1_IT_GL6, DMA1_IT_TC6, DMA_ClearITPendingBit(), DMA_GetCurrDataCounter(), DMA_GetITStatus(), DST_Buffer, LED2, LED3, SRC_Buffer, and STM_EVAL_LEDToggle().

void EXTI9_5_IRQHandler ( void )

This function handles External lines 9 to 5 interrupt request.

This function handles EXTI Lines 9 to 5 interrupts requests.

Parameters:
None
Return values:
None

Definition at line 210 of file STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_it.c.

References EXTI_ClearITPendingBit(), EXTI_GetITStatus(), KEY_BUTTON_EXTI_LINE, LowPowerMode, and RESET.

void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 68 of file STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 67 of file STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/main.c.

References BUTTON_KEY, BUTTON_MODE_EXTI, COM1, Delay(), DMA_Configuration(), ENABLE, EVAL_COM1, LED1, LED2, LED3, LED4, LowPowerMode, NVIC_Init(), NVIC_InitTypeDef::NVIC_IRQChannel, NVIC_InitTypeDef::NVIC_IRQChannelCmd, NVIC_InitTypeDef::NVIC_IRQChannelPreemptionPriority, NVIC_InitTypeDef::NVIC_IRQChannelSubPriority, NVIC_PriorityGroup_1, NVIC_PriorityGroupConfig(), RCC_Configuration(), STM_EVAL_COMInit(), STM_EVAL_LEDInit(), STM_EVAL_LEDOff(), STM_EVAL_LEDToggle(), STM_EVAL_PBInit(), USART_InitTypeDef::USART_BaudRate, USART_DMACmd(), USART_DMAReq_Rx, USART_InitTypeDef::USART_HardwareFlowControl, USART_HardwareFlowControl_None, USART_InitTypeDef::USART_Mode, USART_Mode_Rx, USART_Mode_Tx, USART_InitTypeDef::USART_Parity, USART_Parity_No, USART_InitTypeDef::USART_StopBits, USART_StopBits_1, USART_InitTypeDef::USART_WordLength, USART_WordLength_8b, and USARTy_DMA1_IRQn.

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 81 of file STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 59 of file STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_it.c.

void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 138 of file STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_it.c.

void RCC_Configuration ( void )

Configures the different system clocks.

Parameters:
None
Return values:
None

Definition at line 203 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 120 of file STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 147 of file STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_it.c.

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 107 of file STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_it.c.

Variable Documentation

DMA_InitTypeDef DMA_InitStructure

Definition at line 50 of file STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/main.c.

uint16_t DST_Buffer[10] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0}

Definition at line 52 of file STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/main.c.

uint16_t DST_Buffer[10]

Definition at line 55 of file STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/main.c.

Referenced by DMA1_Channel5_IRQHandler(), DMA1_Channel6_IRQHandler(), DMA_Configuration(), and main().

__IO uint32_t LowPowerMode

Definition at line 51 of file STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/main.c.

Referenced by EXTI9_5_IRQHandler(), main(), and NVIC_SystemLPConfig().

__IO uint32_t LowPowerMode = 0

Definition at line 51 of file STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/main.c.

Referenced by EXTI9_5_IRQHandler(), main(), and NVIC_SystemLPConfig().

NVIC_InitTypeDef NVIC_InitStructure

Definition at line 48 of file STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/main.c.

uint16_t SRC_Buffer[10] = {0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39}

Definition at line 41 of file STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_it.c.

Referenced by DMA1_Channel5_IRQHandler(), DMA1_Channel6_IRQHandler(), and main().

uint8_t TestStatus = 0

Definition at line 40 of file STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_it.c.

USART_InitTypeDef USART_InitStructure

Definition at line 49 of file STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/main.c.


STM32F10x Standard Peripherals Firmware Library: IRQ_Mask

Functions | Variables

IRQ_Mask

STM32F10x_StdPeriph_Examples

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | EXTI0_IRQHandler (void)
This function handles EXTI Lines 0 interrupt request.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | TIM2_IRQHandler (void)
This function handles TIM2 global interrupt request.
void | TIM3_IRQHandler (void)
This function handles TIM3 global interrupt request.
void | TIM4_IRQHandler (void)
This function handles TIM4 global interrupt request.
void | TIM_Config (void)
Configures the used Timers.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

__IO uint32_t | index = 0

Function Documentation

void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 89 of file STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 124 of file STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_it.c.

void EXTI0_IRQHandler ( void )

This function handles EXTI Lines 0 interrupt request.

This function handles External line 0 interrupt request.

Parameters:
None
Return values:
None

Definition at line 155 of file STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_it.c.

References EXTI_ClearITPendingBit(), EXTI_GetITStatus(), index, RESET, and WAKEUP_BUTTON_EXTI_LINE.

void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 63 of file STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 48 of file STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/main.c.

References BUTTON_KEY, BUTTON_MODE_EXTI, BUTTON_MODE_GPIO, BUTTON_WAKEUP, LED1, LED2, LED3, LED4, RESET, STM_EVAL_LEDInit(), STM_EVAL_LEDOff(), STM_EVAL_LEDOn(), STM_EVAL_PBGetState(), STM_EVAL_PBInit(), and TIM_Config().

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 76 of file STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 54 of file STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_it.c.

void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 133 of file STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_it.c.

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 115 of file STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 142 of file STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_it.c.

void TIM2_IRQHandler ( void )

This function handles TIM2 global interrupt request.

Parameters:
None
Return values:
None

Definition at line 186 of file STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_it.c.

void TIM3_IRQHandler ( void )

This function handles TIM3 global interrupt request.

Parameters:
None
Return values:
None

Definition at line 200 of file STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_it.c.

void TIM4_IRQHandler ( void )

This function handles TIM4 global interrupt request.

Parameters:
None
Return values:
None

Definition at line 214 of file STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_it.c.

References LED3, STM_EVAL_LEDToggle(), TIM4, TIM_ClearITPendingBit(), and TIM_IT_Update.

void TIM_Config ( void )

Configures the used Timers.

Parameters:
None
Return values:
None

Definition at line 110 of file STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/main.c.

References ENABLE, NVIC_Init(), NVIC_InitStructure, NVIC_InitTypeDef::NVIC_IRQChannel, NVIC_InitTypeDef::NVIC_IRQChannelCmd, NVIC_InitTypeDef::NVIC_IRQChannelPreemptionPriority, NVIC_InitTypeDef::NVIC_IRQChannelSubPriority, NVIC_PriorityGroup_2, NVIC_PriorityGroupConfig(), RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4, RCC_APB1PeriphClockCmd(), SystemCoreClock, TIM2, TIM3, TIM4, TIM_ClearFlag(), TIM_TimeBaseInitTypeDef::TIM_ClockDivision, TIM_Cmd(), TIM_TimeBaseInitTypeDef::TIM_CounterMode, TIM_CounterMode_Up, TIM_FLAG_Update, TIM_IT_Update, TIM_ITConfig(), TIM_OC1Init(), TIM_OCInitStructure, TIM_OCInitTypeDef::TIM_OCMode, TIM_OCMode_Timing, TIM_OCStructInit(), TIM_TimeBaseInitTypeDef::TIM_Period, TIM_TimeBaseInitTypeDef::TIM_Prescaler, TIM_PrescalerConfig(), TIM_PSCReloadMode_Immediate, TIM_OCInitTypeDef::TIM_Pulse, TIM_TimeBaseInit(), and TIM_TimeBaseStructure.

Referenced by main().

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 102 of file STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_it.c.

Variable Documentation

__IO uint32_t index = 0

Definition at line 40 of file STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: IRQ_Priority

Functions | Variables

IRQ_Priority

STM32F10x_StdPeriph_Examples

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | Delay (__IO uint32_t nCount)
Inserts a delay time.
void | EXTI0_IRQHandler (void)
This function handles External interrupt Line 0 request.
void | EXTI9_5_IRQHandler (void)
This function handles External lines 9 to 5 interrupt request.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | NVIC_Config (void)
Configures the NVIC interrupts.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

__IO uint8_t | PreemptionOccured = 0
uint8_t | PreemptionOccured
uint8_t | PreemptionPriorityValue
__IO uint8_t | PreemptionPriorityValue = 0

Function Documentation

void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 90 of file STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 125 of file STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_it.c.

void Delay ( __IO uint32_t nCount )

Inserts a delay time.

Parameters:
nCount,: specifies the delay time length.
Return values:
None
void EXTI0_IRQHandler ( void )

This function handles External interrupt Line 0 request.

This function handles External line 0 interrupt request.

Parameters:
None
Return values:
None

Definition at line 161 of file STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_it.c.

References EXTI_ClearITPendingBit(), and WAKEUP_BUTTON_EXTI_LINE.

void EXTI9_5_IRQHandler ( void )

This function handles External lines 9 to 5 interrupt request.

This function handles EXTI Lines 9 to 5 interrupts requests.

Parameters:
None
Return values:
None

Definition at line 175 of file STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_it.c.

References ENABLE, EXTI_ClearITPendingBit(), EXTI_GetITStatus(), KEY_BUTTON_EXTI_LINE, NVIC_Init(), NVIC_InitStructure, NVIC_InitTypeDef::NVIC_IRQChannel, NVIC_InitTypeDef::NVIC_IRQChannelCmd, NVIC_InitTypeDef::NVIC_IRQChannelPreemptionPriority, NVIC_InitTypeDef::NVIC_IRQChannelSubPriority, PreemptionOccured, PreemptionPriorityValue, RESET, SysTick_IRQn, and WAKEUP_BUTTON_EXTI_IRQn.

void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 64 of file STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 52 of file STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/main.c.

References BUTTON_KEY, BUTTON_MODE_EXTI, BUTTON_WAKEUP, Delay(), LED1, LED2, LED3, LED4, NVIC_Config(), PreemptionOccured, PreemptionPriorityValue, STM_EVAL_LEDInit(), STM_EVAL_LEDToggle(), STM_EVAL_PBInit(), and SysTick_IRQn.

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 77 of file STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 55 of file STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_it.c.

void NVIC_Config ( void )

Configures the NVIC interrupts.

Parameters:
None
Return values:
None
void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 134 of file STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_it.c.

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 116 of file STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 143 of file STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_it.c.

References PreemptionOccured, and WAKEUP_BUTTON_EXTI_IRQn.

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 103 of file STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_it.c.

Variable Documentation

__IO uint8_t PreemptionOccured = 0

Definition at line 38 of file STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/main.c.

Referenced by EXTI9_5_IRQHandler(), main(), and SysTick_Handler().

uint8_t PreemptionOccured

Definition at line 38 of file STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/main.c.

Referenced by EXTI9_5_IRQHandler(), main(), and SysTick_Handler().

uint8_t PreemptionPriorityValue

Definition at line 39 of file STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/main.c.

Referenced by EXTI9_5_IRQHandler(), and main().

__IO uint8_t PreemptionPriorityValue = 0

Definition at line 39 of file STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/main.c.

Referenced by EXTI9_5_IRQHandler(), and main().


STM32F10x Standard Peripherals Firmware Library: NVIC_VectorTable_Relocation

Functions | Variables

NVIC_VectorTable_Relocation

STM32F10x_StdPeriph_Examples

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | Delay (__IO uint32_t nTime)
Inserts a delay time.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | TimingDelay_Decrement (void)
Decrements the TimingDelay variable.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

static __IO uint32_t | TimingDelay

Function Documentation

void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 87 of file STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 122 of file STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f10x_it.c.

void Delay ( __IO uint32_t nTime )

Inserts a delay time.

Parameters:
nTime,: specifies the delay time length, in milliseconds.
Return values:
None
void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 61 of file STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 49 of file STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/main.c.

References Delay(), LED1, LED2, LED3, LED4, STM_EVAL_LEDInit(), STM_EVAL_LEDOn(), STM_EVAL_LEDToggle(), and SystemCoreClock.

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 74 of file STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 52 of file STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f10x_it.c.

void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 131 of file STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f10x_it.c.

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 113 of file STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 140 of file STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f10x_it.c.

References TimingDelay_Decrement().

void TimingDelay_Decrement ( void )

Decrements the TimingDelay variable.

Parameters:
None
Return values:
None

Definition at line 116 of file STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/main.c.

References TimingDelay.

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 100 of file STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f10x_it.c.

Variable Documentation

__IO uint32_t TimingDelay [static]

Definition at line 37 of file STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/main.c.


STM32F10x Standard Peripherals Firmware Library: PWR_PVD

Functions

PWR_PVD

STM32F10x_StdPeriph_Examples

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | EXTI_Configuration (void)
Configures EXTI Lines.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | NVIC_Configuration (void)
Configures NVIC and Vector Table base location.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | PVD_IRQHandler (void)
This function handles the PVD Output interrupt request.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Function Documentation

void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 87 of file STM32F10x_StdPeriph_Examples/PWR/PVD/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 122 of file STM32F10x_StdPeriph_Examples/PWR/PVD/stm32f10x_it.c.

void EXTI_Configuration ( void )

Configures EXTI Lines.

Parameters:
None
Return values:
None
void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 61 of file STM32F10x_StdPeriph_Examples/PWR/PVD/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 49 of file STM32F10x_StdPeriph_Examples/PWR/PVD/main.c.

References ENABLE, EXTI_Configuration(), LED1, NVIC_Configuration(), PWR_PVDCmd(), PWR_PVDLevel_2V9, PWR_PVDLevelConfig(), RCC_APB1Periph_BKP, RCC_APB1Periph_PWR, RCC_APB1PeriphClockCmd(), and STM_EVAL_LEDInit().

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 74 of file STM32F10x_StdPeriph_Examples/PWR/PVD/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 52 of file STM32F10x_StdPeriph_Examples/PWR/PVD/stm32f10x_it.c.

void NVIC_Configuration ( void )

Configures NVIC and Vector Table base location.

Parameters:
None
Return values:
None
void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 131 of file STM32F10x_StdPeriph_Examples/PWR/PVD/stm32f10x_it.c.

void PVD_IRQHandler ( void )

This function handles the PVD Output interrupt request.

Parameters:
None
Return values:
None

Definition at line 153 of file STM32F10x_StdPeriph_Examples/PWR/PVD/stm32f10x_it.c.

References EXTI_ClearITPendingBit(), EXTI_GetITStatus(), EXTI_Line16, LED1, RESET, and STM_EVAL_LEDToggle().

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 113 of file STM32F10x_StdPeriph_Examples/PWR/PVD/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 140 of file STM32F10x_StdPeriph_Examples/PWR/PVD/stm32f10x_it.c.

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 100 of file STM32F10x_StdPeriph_Examples/PWR/PVD/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: PWR_STANDBY

Functions

PWR_STANDBY

STM32F10x_StdPeriph_Examples

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | EXTI9_5_IRQHandler (void)
This function handles External lines 9 to 5 interrupt request.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Function Documentation

void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 87 of file STM32F10x_StdPeriph_Examples/PWR/STANDBY/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 122 of file STM32F10x_StdPeriph_Examples/PWR/STANDBY/stm32f10x_it.c.

void EXTI9_5_IRQHandler ( void )

This function handles External lines 9 to 5 interrupt request.

This function handles EXTI Lines 9 to 5 interrupts requests.

Parameters:
None
Return values:
None

Definition at line 155 of file STM32F10x_StdPeriph_Examples/PWR/STANDBY/stm32f10x_it.c.

References EXTI_ClearITPendingBit(), EXTI_GetITStatus(), KEY_BUTTON_EXTI_LINE, LED1, PWR_EnterSTANDBYMode(), RESET, RTC_ClearFlag(), RTC_FLAG_SEC, RTC_GetCounter(), RTC_GetFlagStatus(), RTC_SetAlarm(), RTC_WaitForLastTask(), and STM_EVAL_LEDOn().

void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 61 of file STM32F10x_StdPeriph_Examples/PWR/STANDBY/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 50 of file STM32F10x_StdPeriph_Examples/PWR/STANDBY/main.c.

References BUTTON_KEY, BUTTON_MODE_EXTI, ENABLE, LED1, LED2, PWR_BackupAccessCmd(), PWR_WakeUpPinCmd(), RCC_APB1Periph_BKP, RCC_APB1Periph_PWR, RCC_APB1PeriphClockCmd(), RTC_Configuration(), STM_EVAL_LEDInit(), STM_EVAL_LEDOn(), STM_EVAL_PBInit(), and SysTick_Configuration().

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 74 of file STM32F10x_StdPeriph_Examples/PWR/STANDBY/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 52 of file STM32F10x_StdPeriph_Examples/PWR/STANDBY/stm32f10x_it.c.

void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 131 of file STM32F10x_StdPeriph_Examples/PWR/STANDBY/stm32f10x_it.c.

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 113 of file STM32F10x_StdPeriph_Examples/PWR/STANDBY/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 140 of file STM32F10x_StdPeriph_Examples/PWR/STANDBY/stm32f10x_it.c.

References LED1, and STM_EVAL_LEDToggle().

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 100 of file STM32F10x_StdPeriph_Examples/PWR/STANDBY/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: PWR_STOP

Functions | Variables

PWR_STOP

STM32F10x_StdPeriph_Examples

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | Delay (__IO uint32_t nTime)
Inserts a delay time.
void | EXTI9_5_IRQHandler (void)
This function handles External lines 9 to 5 interrupt request.
void | EXTI_Configuration (void)
Configures EXTI Lines.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | NVIC_Configuration (void)
Configures NVIC and Vector Table base location.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | RTC_Configuration (void)
Configures RTC clock source and prescaler.
void | RTCAlarm_IRQHandler (void)
This function handles RTC Alarm interrupt request.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SYSCLKConfig_STOP (void)
Configures system clock after wake-up from STOP: enable HSE, PLL and select PLL as system clock source.
void | SysTick_Configuration (void)
Configures the SysTick to generate an interrupt each 1 millisecond.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

ErrorStatus HSEStartUpStatus
__IO uint32_t | TimingDelay = 0
__IO uint32_t | TimingDelay

Function Documentation

void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 89 of file STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 124 of file STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_it.c.

void Delay ( __IO uint32_t nTime )

Inserts a delay time.

Parameters:
nTime,: specifies the delay time length, in milliseconds.
Return values:
None
void EXTI9_5_IRQHandler ( void )

This function handles External lines 9 to 5 interrupt request.

This function handles EXTI Lines 9 to 5 interrupts requests.

Parameters:
None
Return values:
None

Definition at line 156 of file STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_it.c.

References EXTI_ClearITPendingBit(), EXTI_GetITStatus(), KEY_BUTTON_EXTI_LINE, LED2, RESET, and STM_EVAL_LEDToggle().

void EXTI_Configuration ( void )

Configures EXTI Lines.

Parameters:
None
Return values:
None
void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 63 of file STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 56 of file STM32F10x_StdPeriph_Examples/PWR/STOP/main.c.

References BUTTON_KEY, BUTTON_MODE_EXTI, Delay(), ENABLE, EXTI_Configuration(), LED1, LED2, LED3, NVIC_Configuration(), PWR_EnterSTOPMode(), PWR_Regulator_LowPower, PWR_STOPEntry_WFI, RCC_APB1Periph_BKP, RCC_APB1Periph_PWR, RCC_APB1PeriphClockCmd(), RESET, RTC_ClearFlag(), RTC_Configuration(), RTC_FLAG_SEC, RTC_GetCounter(), RTC_GetFlagStatus(), RTC_SetAlarm(), RTC_WaitForLastTask(), STM_EVAL_LEDInit(), STM_EVAL_LEDOff(), STM_EVAL_LEDOn(), STM_EVAL_PBInit(), SYSCLKConfig_STOP(), and SysTick_Configuration().

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 76 of file STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 54 of file STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_it.c.

void NVIC_Configuration ( void )

Configures NVIC and Vector Table base location.

Parameters:
None
Return values:
None
void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 133 of file STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_it.c.

void RTC_Configuration ( void )

Configures RTC clock source and prescaler.

Parameters:
None
Return values:
None
void RTCAlarm_IRQHandler ( void )

This function handles RTC Alarm interrupt request.

Parameters:
None
Return values:
None

Definition at line 173 of file STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_it.c.

References EXTI_ClearITPendingBit(), EXTI_Line17, LED3, PWR_ClearFlag(), PWR_FLAG_WU, PWR_GetFlagStatus(), RESET, RTC_ClearITPendingBit(), RTC_GetITStatus(), RTC_IT_ALR, RTC_WaitForLastTask(), and STM_EVAL_LEDToggle().

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 115 of file STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_it.c.

void SYSCLKConfig_STOP ( void )

Configures system clock after wake-up from STOP: enable HSE, PLL and select PLL as system clock source.

Parameters:
None
Return values:
None

Definition at line 125 of file STM32F10x_StdPeriph_Examples/PWR/STOP/main.c.

References ENABLE, HSEStartUpStatus, RCC_FLAG_PLLRDY, RCC_GetFlagStatus(), RCC_GetSYSCLKSource(), RCC_HSE_ON, RCC_HSEConfig(), RCC_PLLCmd(), RCC_SYSCLKConfig(), RCC_SYSCLKSource_PLLCLK, RCC_WaitForHSEStartUp(), RESET, and SUCCESS.

Referenced by main().

void SysTick_Configuration ( void )

Configures the SysTick to generate an interrupt each 1 millisecond.

Parameters:
None
Return values:
None
void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 142 of file STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_it.c.

References TimingDelay.

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 102 of file STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_it.c.

Variable Documentation

ErrorStatus HSEStartUpStatus

Definition at line 39 of file STM32F10x_StdPeriph_Examples/PWR/STOP/main.c.

__IO uint32_t TimingDelay = 0

Definition at line 40 of file STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_it.c.

__IO uint32_t TimingDelay

Definition at line 43 of file STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/main.c.


STM32F10x Standard Peripherals Firmware Library: RCC_ClockConfig

Defines | Functions | Variables

RCC_ClockConfig

STM32F10x_StdPeriph_Examples

Defines

#define | DELAY_COUNT 0x3FFFF

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | Delay (__IO uint32_t nCount)
Inserts a delay time.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | NVIC_Configuration (void)
Configures Vector Table base location.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | RCC_IRQHandler (void)
This function handles RCC interrupt request.
void | SetSysClockTo24 (void)
Sets System clock frequency to 24MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
void | SetSysClockTo36 (void)
Sets System clock frequency to 36MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
void | SetSysClockTo48 (void)
Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
void | SetSysClockTo56 (void)
Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
void | SetSysClockTo72 (void)
Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
void | SetSysClockToHSE (void)
Selects HSE as System clock source and configure HCLK, PCLK2 and PCLK1 prescalers.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

GPIO_InitTypeDef GPIO_InitStructure
ErrorStatus HSEStartUpStatus
RCC_ClocksTypeDef RCC_ClockFreq

Define Documentation

#define DELAY_COUNT 0x3FFFF

Definition at line 36 of file STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/main.c.

Referenced by main().

Function Documentation

void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 116 of file STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 151 of file STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/stm32f10x_it.c.

void Delay ( __IO uint32_t nCount )

Inserts a delay time.

Parameters:
nCount,: specifies the delay time length.
Return values:
None
void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 90 of file STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 70 of file STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/main.c.

References Delay(), DELAY_COUNT, ENABLE, GPIO_Init(), GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_AF_PP, GPIO_InitTypeDef::GPIO_Pin, GPIO_Pin_8, GPIO_InitTypeDef::GPIO_Speed, GPIO_Speed_50MHz, GPIOA, LED1, LED2, LED3, LED4, NVIC_Configuration(), RCC_APB2Periph_GPIOA, RCC_APB2PeriphClockCmd(), RCC_ClockSecuritySystemCmd(), RCC_GetClocksFreq(), RCC_MCO_HSE, RCC_MCOConfig(), SetSysClock(), STM_EVAL_LEDInit(), and STM_EVAL_LEDToggle().

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 103 of file STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 52 of file STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/stm32f10x_it.c.

References ENABLE, RCC_ClearITPendingBit(), RCC_GetITStatus(), RCC_HSE_ON, RCC_HSEConfig(), RCC_IT_CSS, RCC_IT_HSERDY, RCC_IT_PLLRDY, RCC_ITConfig(), and RESET.

void NVIC_Configuration ( void )

Configures Vector Table base location.

Parameters:
None
Return values:
None
void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 160 of file STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/stm32f10x_it.c.

void RCC_IRQHandler ( void )

This function handles RCC interrupt request.

Parameters:
None
Return values:
None

Definition at line 182 of file STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/stm32f10x_it.c.

References ENABLE, RCC_ClearITPendingBit(), RCC_FLAG_HSERDY, RCC_FLAG_PLLRDY, RCC_GetFlagStatus(), RCC_GetITStatus(), RCC_IT_HSERDY, RCC_IT_PLLRDY, RCC_PLLCmd(), RCC_SYSCLKConfig(), RCC_SYSCLKSource_HSE, RCC_SYSCLKSource_PLLCLK, and RESET.

void SetSysClockTo24 ( void )

Sets System clock frequency to 24MHz and configure HCLK, PCLK2 and PCLK1 prescalers.

Parameters:
None
Return values:
None

Definition at line 241 of file STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/main.c.

References ENABLE, FLASH_Latency_0, FLASH_PrefetchBuffer_Enable, FLASH_PrefetchBufferCmd(), FLASH_SetLatency(), HSEStartUpStatus, RCC_DeInit(), RCC_FLAG_PLLRDY, RCC_GetFlagStatus(), RCC_GetSYSCLKSource(), RCC_HCLK_Div1, RCC_HCLKConfig(), RCC_HSE_ON, RCC_HSEConfig(), RCC_PCLK1Config(), RCC_PCLK2Config(), RCC_PLLCmd(), RCC_PLLConfig(), RCC_PLLMul_3, RCC_PLLMul_6, RCC_PLLSource_HSE_Div1, RCC_SYSCLK_Div1, RCC_SYSCLKConfig(), RCC_SYSCLKSource_PLLCLK, RCC_WaitForHSEStartUp(), RESET, and SUCCESS.

Referenced by SetSysClock().

void SetSysClockTo36 ( void )

Sets System clock frequency to 36MHz and configure HCLK, PCLK2 and PCLK1 prescalers.

Parameters:
None
Return values:
None

Definition at line 330 of file STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/main.c.

References ENABLE, FLASH_Latency_1, FLASH_PrefetchBuffer_Enable, FLASH_PrefetchBufferCmd(), FLASH_SetLatency(), HSEStartUpStatus, RCC_DeInit(), RCC_FLAG_PLLRDY, RCC_GetFlagStatus(), RCC_GetSYSCLKSource(), RCC_HCLK_Div1, RCC_HCLKConfig(), RCC_HSE_ON, RCC_HSEConfig(), RCC_PCLK1Config(), RCC_PCLK2Config(), RCC_PLLCmd(), RCC_PLLConfig(), RCC_PLLMul_9, RCC_PLLSource_HSE_Div2, RCC_SYSCLK_Div1, RCC_SYSCLKConfig(), RCC_SYSCLKSource_PLLCLK, RCC_WaitForHSEStartUp(), RESET, and SUCCESS.

Referenced by SetSysClock().

void SetSysClockTo48 ( void )

Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers.

Parameters:
None
Return values:
None

Definition at line 413 of file STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/main.c.

References ENABLE, FLASH_Latency_1, FLASH_PrefetchBuffer_Enable, FLASH_PrefetchBufferCmd(), FLASH_SetLatency(), HSEStartUpStatus, RCC_DeInit(), RCC_FLAG_PLLRDY, RCC_GetFlagStatus(), RCC_GetSYSCLKSource(), RCC_HCLK_Div1, RCC_HCLK_Div2, RCC_HCLKConfig(), RCC_HSE_ON, RCC_HSEConfig(), RCC_PCLK1Config(), RCC_PCLK2Config(), RCC_PLLCmd(), RCC_PLLConfig(), RCC_PLLMul_6, RCC_PLLSource_HSE_Div1, RCC_SYSCLK_Div1, RCC_SYSCLKConfig(), RCC_SYSCLKSource_PLLCLK, RCC_WaitForHSEStartUp(), RESET, and SUCCESS.

Referenced by SetSysClock().

void SetSysClockTo56 ( void )

Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers.

Parameters:
None
Return values:
None

Definition at line 496 of file STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/main.c.

References ENABLE, FLASH_Latency_2, FLASH_PrefetchBuffer_Enable, FLASH_PrefetchBufferCmd(), FLASH_SetLatency(), HSEStartUpStatus, RCC_DeInit(), RCC_FLAG_PLLRDY, RCC_GetFlagStatus(), RCC_GetSYSCLKSource(), RCC_HCLK_Div1, RCC_HCLK_Div2, RCC_HCLKConfig(), RCC_HSE_ON, RCC_HSEConfig(), RCC_PCLK1Config(), RCC_PCLK2Config(), RCC_PLLCmd(), RCC_PLLConfig(), RCC_PLLMul_7, RCC_PLLSource_HSE_Div1, RCC_SYSCLK_Div1, RCC_SYSCLKConfig(), RCC_SYSCLKSource_PLLCLK, RCC_WaitForHSEStartUp(), RESET, and SUCCESS.

Referenced by SetSysClock().

void SetSysClockTo72 ( void )

Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers.

Parameters:
None
Return values:
None

Definition at line 579 of file STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/main.c.

References ENABLE, FLASH_Latency_2, FLASH_PrefetchBuffer_Enable, FLASH_PrefetchBufferCmd(), FLASH_SetLatency(), HSEStartUpStatus, RCC_DeInit(), RCC_FLAG_PLLRDY, RCC_GetFlagStatus(), RCC_GetSYSCLKSource(), RCC_HCLK_Div1, RCC_HCLK_Div2, RCC_HCLKConfig(), RCC_HSE_ON, RCC_HSEConfig(), RCC_PCLK1Config(), RCC_PCLK2Config(), RCC_PLLCmd(), RCC_PLLConfig(), RCC_PLLMul_9, RCC_PLLSource_HSE_Div1, RCC_SYSCLK_Div1, RCC_SYSCLKConfig(), RCC_SYSCLKSource_PLLCLK, RCC_WaitForHSEStartUp(), RESET, and SUCCESS.

Referenced by SetSysClock().

void SetSysClockToHSE ( void )

Selects HSE as System clock source and configure HCLK, PCLK2 and PCLK1 prescalers.

Parameters:
None
Return values:
None

Definition at line 171 of file STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/main.c.

References FLASH_Latency_0, FLASH_Latency_1, FLASH_PrefetchBuffer_Enable, FLASH_PrefetchBufferCmd(), FLASH_SetLatency(), HSE_Value, HSEStartUpStatus, RCC_DeInit(), RCC_GetSYSCLKSource(), RCC_HCLK_Div1, RCC_HCLKConfig(), RCC_HSE_ON, RCC_HSEConfig(), RCC_PCLK1Config(), RCC_PCLK2Config(), RCC_SYSCLK_Div1, RCC_SYSCLKConfig(), RCC_SYSCLKSource_HSE, RCC_WaitForHSEStartUp(), and SUCCESS.

Referenced by SetSysClock().

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 142 of file STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 169 of file STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/stm32f10x_it.c.

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 129 of file STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/stm32f10x_it.c.

Variable Documentation

GPIO_InitTypeDef GPIO_InitStructure

Definition at line 40 of file STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/main.c.

ErrorStatus HSEStartUpStatus

Definition at line 42 of file STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/main.c.

RCC_ClocksTypeDef RCC_ClockFreq

Definition at line 41 of file STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/main.c.


STM32F10x Standard Peripherals Firmware Library: RTC_Calendar

Defines | Functions | Variables

RTC_Calendar

STM32F10x_StdPeriph_Examples

Defines

#define | PUTCHAR_PROTOTYPE int fputc(int ch, FILE *f)
#define | RTCClockOutput_Enable

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | NVIC_Configuration (void)
Configures the nested vectored interrupt controller.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | RTC_Configuration (void)
Configures the RTC.
void | RTC_IRQHandler (void)
This function handles RTC global interrupt request.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | Time_Adjust (void)
Adjusts time.
void | Time_Display (uint32_t TimeVar)
Displays the current time.
uint32_t | Time_Regulate (void)
Returns the time entered by user, using Hyperterminal.
void | Time_Show (void)
Shows the current time (HH:MM:SS) on the Hyperterminal.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.
uint8_t | USART_Scanf (uint32_t value)

Variables

__IO uint32_t | TimeDisplay = 0
__IO uint32_t | TimeDisplay
USART_InitTypeDef USART_InitStructure

Define Documentation

#define PUTCHAR_PROTOTYPE int fputc(int ch, FILE *f)

Definition at line 58 of file STM32F10x_StdPeriph_Examples/RTC/Calendar/main.c.

#define RTCClockOutput_Enable

Definition at line 37 of file STM32F10x_StdPeriph_Examples/RTC/Calendar/main.c.

Function Documentation

void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 87 of file STM32F10x_StdPeriph_Examples/RTC/Calendar/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 111 of file STM32F10x_StdPeriph_Examples/RTC/Calendar/stm32f10x_it.c.

void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 63 of file STM32F10x_StdPeriph_Examples/RTC/Calendar/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 68 of file STM32F10x_StdPeriph_Examples/RTC/Calendar/main.c.

References BKP_DR1, BKP_ReadBackupRegister(), BKP_RTCOutputConfig(), BKP_RTCOutputSource_CalibClock, BKP_TamperPinCmd(), BKP_WriteBackupRegister(), COM1, DISABLE, ENABLE, LED1, NVIC_Configuration(), PWR_BackupAccessCmd(), RCC_APB1Periph_BKP, RCC_APB1Periph_PWR, RCC_APB1PeriphClockCmd(), RCC_ClearFlag(), RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_GetFlagStatus(), RESET, RTC_Configuration(), RTC_IT_SEC, RTC_ITConfig(), RTC_WaitForLastTask(), RTC_WaitForSynchro(), STM_EVAL_COMInit(), STM_EVAL_LEDInit(), Time_Adjust(), Time_Show(), USART_InitTypeDef::USART_BaudRate, USART_InitTypeDef::USART_HardwareFlowControl, USART_HardwareFlowControl_None, USART_InitTypeDef::USART_Mode, USART_Mode_Rx, USART_Mode_Tx, USART_InitTypeDef::USART_Parity, USART_Parity_No, USART_InitTypeDef::USART_StopBits, USART_StopBits_1, USART_InitTypeDef::USART_WordLength, and USART_WordLength_8b.

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 75 of file STM32F10x_StdPeriph_Examples/RTC/Calendar/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 54 of file STM32F10x_StdPeriph_Examples/RTC/Calendar/stm32f10x_it.c.

void NVIC_Configuration ( void )

Configures the nested vectored interrupt controller.

Parameters:
None
Return values:
None
void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 129 of file STM32F10x_StdPeriph_Examples/RTC/Calendar/stm32f10x_it.c.

void RTC_Configuration ( void )

Configures the RTC.

Parameters:
None
Return values:
None
void RTC_IRQHandler ( void )

This function handles RTC global interrupt request.

Parameters:
None
Return values:
None

Definition at line 151 of file STM32F10x_StdPeriph_Examples/RTC/Calendar/stm32f10x_it.c.

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 120 of file STM32F10x_StdPeriph_Examples/RTC/Calendar/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 138 of file STM32F10x_StdPeriph_Examples/RTC/Calendar/stm32f10x_it.c.

void Time_Adjust ( void )

Adjusts time.

Parameters:
None
Return values:
None

Definition at line 270 of file STM32F10x_StdPeriph_Examples/RTC/Calendar/main.c.

References RTC_SetCounter(), RTC_WaitForLastTask(), and Time_Regulate().

Referenced by main().

void Time_Display ( uint32_t TimeVar )

Displays the current time.

Parameters:
TimeVar,: RTC counter value.
Return values:
None

Definition at line 285 of file STM32F10x_StdPeriph_Examples/RTC/Calendar/main.c.

References RTC_GetCounter(), RTC_SetCounter(), and RTC_WaitForLastTask().

Referenced by Time_Show().

uint32_t Time_Regulate ( void )

Returns the time entered by user, using Hyperterminal.

Parameters:
None
Return values:
Current time RTC counter value

Definition at line 236 of file STM32F10x_StdPeriph_Examples/RTC/Calendar/main.c.

References USART_Scanf().

Referenced by Time_Adjust().

void Time_Show ( void )

Shows the current time (HH:MM:SS) on the Hyperterminal.

Parameters:
None
Return values:
None

Definition at line 312 of file STM32F10x_StdPeriph_Examples/RTC/Calendar/main.c.

References RTC_GetCounter(), Time_Display(), and TimeDisplay.

Referenced by main().

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 99 of file STM32F10x_StdPeriph_Examples/RTC/Calendar/stm32f10x_it.c.

uint8_t USART_Scanf ( uint32_t value )

Referenced by Time_Regulate().

Variable Documentation

__IO uint32_t TimeDisplay = 0

Definition at line 41 of file STM32F10x_StdPeriph_Examples/RTC/Calendar/main.c.

Referenced by RTC_IRQHandler(), and Time_Show().

__IO uint32_t TimeDisplay

Definition at line 41 of file STM32F10x_StdPeriph_Examples/RTC/Calendar/main.c.

Referenced by RTC_IRQHandler(), and Time_Show().

USART_InitTypeDef USART_InitStructure

Definition at line 42 of file STM32F10x_StdPeriph_Examples/RTC/Calendar/main.c.


STM32F10x Standard Peripherals Firmware Library: RTC_LSI_Calib

Defines | Functions | Variables

RTC_LSI_Calib

STM32F10x_StdPeriph_Examples

Defines

#define | RTCClockOutput_Enable

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
uint32_t | GetVar_OperationComplete (void)
Returns OperationComplete value.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
uint32_t | IncrementVar_OperationComplete (void)
Increments OperationComplete variable and return its value before increment operation.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | NVIC_Configuration (void)
Configures the nested vectored interrupt controller.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | RTC_Configuration (void)
Configures the RTC.
void | RTC_IRQHandler (void)
This function handles RTC global interrupt request.
void | SetVar_PeriodValue (uint32_t Value)
Sets the PeriodValue variable with input parameter.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | TIM5_IRQHandler (void)
This function handles TIM5 global interrupt request.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

__IO uint32_t | LsiFreq = 0
__IO uint32_t | OperationComplete = 0
__IO uint32_t | PeriodValue = 0
RCC_ClocksTypeDef RCC_Clocks
TIM_ICInitTypeDef TIM_ICInitStructure
TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure
uint16_t | tmpCC4 [2] = {0, 0}

Define Documentation

#define RTCClockOutput_Enable

Definition at line 36 of file STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/main.c.

Function Documentation

void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 87 of file STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 111 of file STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_it.c.

uint32_t GetVar_OperationComplete ( void )

Returns OperationComplete value.

Parameters:
None
Return values:
OperationComplete value

Definition at line 244 of file STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/main.c.

References OperationComplete.

Referenced by TIM5_IRQHandler().

void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 63 of file STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_it.c.

uint32_t IncrementVar_OperationComplete ( void )

Increments OperationComplete variable and return its value before increment operation.

Parameters:
None
Return values:
OperationComplete value before increment

Definition at line 232 of file STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/main.c.

References OperationComplete.

Referenced by TIM5_IRQHandler().

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 58 of file STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/main.c.

References BUTTON_KEY, BUTTON_MODE_GPIO, ENABLE, GPIO_PinRemapConfig(), GPIO_Remap_TIM5CH4_LSI, LED1, LED2, LsiFreq, NVIC_Configuration(), OperationComplete, RCC_ClocksTypeDef::PCLK1_Frequency, PeriodValue, RCC_APB1Periph_TIM5, RCC_APB1PeriphClockCmd(), RCC_GetClocksFreq(), RTC_Configuration(), RTC_SetPrescaler(), RTC_WaitForLastTask(), STM_EVAL_LEDInit(), STM_EVAL_LEDOn(), STM_EVAL_PBGetState(), STM_EVAL_PBInit(), TIM5, TIM_ICInitTypeDef::TIM_Channel, TIM_Channel_4, TIM_CKD_DIV1, TIM_TimeBaseInitTypeDef::TIM_ClockDivision, TIM_Cmd(), TIM_TimeBaseInitTypeDef::TIM_CounterMode, TIM_CounterMode_Up, TIM_ICInitTypeDef::TIM_ICFilter, TIM_ICInit(), TIM_ICInitTypeDef::TIM_ICPolarity, TIM_ICPolarity_Rising, TIM_ICInitTypeDef::TIM_ICPrescaler, TIM_ICPSC_DIV1, TIM_ICInitTypeDef::TIM_ICSelection, TIM_ICSelection_DirectTI, TIM_IT_CC4, TIM_ITConfig(), TIM_TimeBaseInitTypeDef::TIM_Period, TIM_TimeBaseInitTypeDef::TIM_Prescaler, and TIM_TimeBaseInit().

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 75 of file STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 54 of file STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_it.c.

void NVIC_Configuration ( void )

Configures the nested vectored interrupt controller.

Parameters:
None
Return values:
None
void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 129 of file STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_it.c.

void RTC_Configuration ( void )

Configures the RTC.

Parameters:
None
Return values:
None
void RTC_IRQHandler ( void )

This function handles RTC global interrupt request.

Parameters:
None
Return values:
None

Definition at line 151 of file STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_it.c.

References LED1, RESET, RTC_ClearITPendingBit(), RTC_FLAG_SEC, RTC_GetITStatus(), RTC_IT_SEC, RTC_WaitForLastTask(), STM_EVAL_LEDToggle(), and TimeDisplay.

void SetVar_PeriodValue ( uint32_t Value )

Sets the PeriodValue variable with input parameter.

Parameters:
Value,: Value of PeriodValue to be set.
Return values:
None

Definition at line 254 of file STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/main.c.

References PeriodValue.

Referenced by TIM5_IRQHandler().

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 120 of file STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 138 of file STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_it.c.

void TIM5_IRQHandler ( void )

This function handles TIM5 global interrupt request.

Parameters:
None
Return values:
None

Definition at line 168 of file STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_it.c.

References Capture, CaptureNumber, DISABLE, GetVar_OperationComplete(), IC1ReadValue1, IC1ReadValue2, IncrementVar_OperationComplete(), LsiFreq, RESET, SET, SetVar_PeriodValue(), SystemCoreClock, TIM5, TIM_ClearITPendingBit(), TIM_Cmd(), TIM_GetCapture4(), TIM_GetITStatus(), TIM_IT_CC4, TIM_ITConfig(), and tmpCC4.

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 99 of file STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_it.c.

Variable Documentation

__IO uint32_t LsiFreq = 0

Definition at line 44 of file STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/main.c.

__IO uint32_t OperationComplete = 0

Definition at line 45 of file STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/main.c.

Referenced by GetVar_OperationComplete(), IncrementVar_OperationComplete(), and main().

__IO uint32_t PeriodValue = 0

Definition at line 44 of file STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/main.c.

Referenced by main(), and SetVar_PeriodValue().

RCC_ClocksTypeDef RCC_Clocks

Definition at line 43 of file STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/main.c.

TIM_ICInitTypeDef TIM_ICInitStructure

Definition at line 42 of file STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/main.c.

Referenced by TIM5_ConfigForLSI().

TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure

Definition at line 41 of file STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/main.c.

uint16_t tmpCC4[2] = {0, 0}

Definition at line 40 of file STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_it.c.

Referenced by TIM5_IRQHandler().


STM32F10x Standard Peripherals Firmware Library: SDIO_uSDCard

Defines | Enumerations | Functions | Variables

SDIO_uSDCard

STM32F10x_StdPeriph_Examples

Defines

#define | BLOCK_SIZE 512
#define | MULTI_BUFFER_SIZE (BLOCK_SIZE * NUMBER_OF_BLOCKS)
#define | NUMBER_OF_BLOCKS 32
#define | SD_OPERATION_BLOCK 1
#define | SD_OPERATION_END 3
#define | SD_OPERATION_ERASE 0
#define | SD_OPERATION_MULTI_BLOCK 2

Enumerations

enum TestStatus {
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED
}

Functions

TestStatus | Buffercmp (uint8_t *pBuffer1, uint8_t *pBuffer2, uint32_t BufferLength)
Compares two buffers.
void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
TestStatus | eBuffercmp (uint8_t *pBuffer, uint32_t BufferLength)
Checks if a buffer has all its values are equal to zero.
void | Fill_Buffer (uint8_t *pBuffer, uint32_t BufferLength, uint32_t Offset)
Fills buffer with user predefined data.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | NVIC_Configuration (void)
Configures SDIO IRQ channel.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SD_EraseTest (void)
Tests the SD card erase operation.
void | SD_MultiBlockTest (void)
Tests the SD card Multiple Blocks operations.
void | SD_SingleBlockTest (void)
Tests the SD card Single Blocks operations.
void | SDIO_IRQHandler (void)
This function handles SDIO global interrupt request.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

uint8_t | Buffer_Block_Rx [BLOCK_SIZE]
uint8_t | Buffer_Block_Tx [BLOCK_SIZE]
uint8_t | Buffer_MultiBlock_Rx [MULTI_BUFFER_SIZE]
uint8_t | Buffer_MultiBlock_Tx [MULTI_BUFFER_SIZE]
volatile TestStatus | EraseStatus = FAILED
__IO uint32_t | SDCardOperation = SD_OPERATION_ERASE
SD_Error | Status = SD_OK
volatile TestStatus | TransferStatus1 = FAILED
volatile TestStatus | TransferStatus2 = FAILED

Define Documentation

#define BLOCK_SIZE 512

Definition at line 38 of file STM32F10x_StdPeriph_Examples/SDIO/uSDCard/main.c.

Referenced by SD_EraseTest(), SD_MultiBlockTest(), and SD_SingleBlockTest().

#define MULTI_BUFFER_SIZE (BLOCK_SIZE * NUMBER_OF_BLOCKS)

Definition at line 41 of file STM32F10x_StdPeriph_Examples/SDIO/uSDCard/main.c.

Referenced by SD_EraseTest(), and SD_MultiBlockTest().

#define NUMBER_OF_BLOCKS 32

Definition at line 40 of file STM32F10x_StdPeriph_Examples/SDIO/uSDCard/main.c.

Referenced by SD_EraseTest(), and SD_MultiBlockTest().

#define SD_OPERATION_BLOCK 1

Definition at line 44 of file STM32F10x_StdPeriph_Examples/SDIO/uSDCard/main.c.

Referenced by main().

#define SD_OPERATION_END 3

Definition at line 46 of file STM32F10x_StdPeriph_Examples/SDIO/uSDCard/main.c.

Referenced by main().

#define SD_OPERATION_ERASE 0

Definition at line 43 of file STM32F10x_StdPeriph_Examples/SDIO/uSDCard/main.c.

Referenced by main().

#define SD_OPERATION_MULTI_BLOCK 2

Definition at line 45 of file STM32F10x_StdPeriph_Examples/SDIO/uSDCard/main.c.

Referenced by main().

Enumeration Type Documentation

enum TestStatus
Enumerator:
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED

Definition at line 35 of file STM32F10x_StdPeriph_Examples/SDIO/uSDCard/main.c.

Function Documentation

TestStatus Buffercmp | ( | uint8_t * | pBuffer1,
 |  | uint8_t * | pBuffer2,
 |  | uint32_t | BufferLength
 | ) |  |

Compares two buffers.

Parameters:
pBuffer1,pBuffer2,: buffers to be compared.
BufferLength,: buffer's length
Return values:
PASSED,: pBuffer1 identical to pBuffer2 FAILED: pBuffer1 differs from pBuffer2

Definition at line 289 of file STM32F10x_StdPeriph_Examples/SDIO/uSDCard/main.c.

References FAILED, and PASSED.

void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 85 of file STM32F10x_StdPeriph_Examples/SDIO/uSDCard/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 109 of file STM32F10x_StdPeriph_Examples/SDIO/uSDCard/stm32f10x_it.c.

TestStatus eBuffercmp | ( | uint8_t * | pBuffer,
 |  | uint32_t | BufferLength
 | ) |  |

Checks if a buffer has all its values are equal to zero.

Parameters:
pBuffer,: buffer to be compared.
BufferLength,: buffer's length
Return values:
PASSED,: pBuffer values are zero FAILED: At least one value from pBuffer buffer is different from zero.

Definition at line 330 of file STM32F10x_StdPeriph_Examples/SDIO/uSDCard/main.c.

References FAILED, and PASSED.

Referenced by SD_EraseTest().

void Fill_Buffer | ( | uint8_t * | pBuffer,
 |  | uint32_t | BufferLength,
 |  | uint32_t | Offset
 | ) |  |

Fills buffer with user predefined data.

Parameters:
pBuffer,: pointer on the Buffer to fill
BufferLength,: size of the buffer to fill
Offset,: first value to fill on the Buffer
Return values:
None

Definition at line 312 of file STM32F10x_StdPeriph_Examples/SDIO/uSDCard/main.c.

References index.

void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 61 of file STM32F10x_StdPeriph_Examples/SDIO/uSDCard/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 72 of file STM32F10x_StdPeriph_Examples/SDIO/uSDCard/main.c.

References LED1, LED2, LED3, LED4, NVIC_Configuration(), SD_Detect(), SD_EraseTest(), SD_Init(), SD_MultiBlockTest(), SD_OK, SD_OPERATION_BLOCK, SD_OPERATION_END, SD_OPERATION_ERASE, SD_OPERATION_MULTI_BLOCK, SD_PRESENT, SD_SingleBlockTest(), SDCardOperation, Status, STM_EVAL_LEDInit(), and STM_EVAL_LEDOn().

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 73 of file STM32F10x_StdPeriph_Examples/SDIO/uSDCard/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 52 of file STM32F10x_StdPeriph_Examples/SDIO/uSDCard/stm32f10x_it.c.

void NVIC_Configuration ( void )

Configures SDIO IRQ channel.

Parameters:
None
Return values:
None
void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 127 of file STM32F10x_StdPeriph_Examples/SDIO/uSDCard/stm32f10x_it.c.

void SD_EraseTest ( void )

Tests the SD card erase operation.

Parameters:
None
Return values:
None

Definition at line 153 of file STM32F10x_StdPeriph_Examples/SDIO/uSDCard/main.c.

References BLOCK_SIZE, Buffer_MultiBlock_Rx, eBuffercmp(), EraseStatus, LED1, LED4, MULTI_BUFFER_SIZE, NUMBER_OF_BLOCKS, PASSED, SD_Erase(), SD_GetStatus(), SD_OK, SD_ReadMultiBlocks(), SD_TRANSFER_OK, SD_WaitReadOperation(), Status, STM_EVAL_LEDOff(), and STM_EVAL_LEDOn().

Referenced by main().

void SD_MultiBlockTest ( void )

Tests the SD card Multiple Blocks operations.

Parameters:
None
Return values:
None

Definition at line 241 of file STM32F10x_StdPeriph_Examples/SDIO/uSDCard/main.c.

References BLOCK_SIZE, Buffer_MultiBlock_Rx, Buffer_MultiBlock_Tx, Buffercmp(), Fill_Buffer(), LED3, LED4, MULTI_BUFFER_SIZE, NUMBER_OF_BLOCKS, PASSED, SD_GetStatus(), SD_OK, SD_ReadMultiBlocks(), SD_TRANSFER_OK, SD_WaitReadOperation(), SD_WaitWriteOperation(), SD_WriteMultiBlocks(), Status, STM_EVAL_LEDOff(), STM_EVAL_LEDOn(), and TransferStatus2.

Referenced by main().

void SD_SingleBlockTest ( void )

Tests the SD card Single Blocks operations.

Parameters:
None
Return values:
None

Definition at line 195 of file STM32F10x_StdPeriph_Examples/SDIO/uSDCard/main.c.

References BLOCK_SIZE, Buffer_Block_Rx, Buffer_Block_Tx, Buffercmp(), Fill_Buffer(), LED2, LED4, PASSED, SD_GetStatus(), SD_OK, SD_ReadBlock(), SD_TRANSFER_OK, SD_WaitReadOperation(), SD_WaitWriteOperation(), SD_WriteBlock(), Status, STM_EVAL_LEDOff(), STM_EVAL_LEDOn(), and TransferStatus1.

Referenced by main().

void SDIO_IRQHandler ( void )

This function handles SDIO global interrupt request.

Parameters:
None
Return values:
None

Definition at line 149 of file STM32F10x_StdPeriph_Examples/SDIO/uSDCard/stm32f10x_it.c.

References SD_ProcessIRQSrc().

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 118 of file STM32F10x_StdPeriph_Examples/SDIO/uSDCard/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 136 of file STM32F10x_StdPeriph_Examples/SDIO/uSDCard/stm32f10x_it.c.

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 97 of file STM32F10x_StdPeriph_Examples/SDIO/uSDCard/stm32f10x_it.c.

Variable Documentation

uint8_t Buffer_Block_Rx[BLOCK_SIZE]

Definition at line 50 of file STM32F10x_StdPeriph_Examples/SDIO/uSDCard/main.c.

Referenced by SD_SingleBlockTest().

uint8_t Buffer_Block_Tx[BLOCK_SIZE]

Definition at line 50 of file STM32F10x_StdPeriph_Examples/SDIO/uSDCard/main.c.

Referenced by SD_SingleBlockTest().

uint8_t Buffer_MultiBlock_Rx[MULTI_BUFFER_SIZE]

Definition at line 51 of file STM32F10x_StdPeriph_Examples/SDIO/uSDCard/main.c.

Referenced by SD_EraseTest(), and SD_MultiBlockTest().

uint8_t Buffer_MultiBlock_Tx[MULTI_BUFFER_SIZE]

Definition at line 51 of file STM32F10x_StdPeriph_Examples/SDIO/uSDCard/main.c.

Referenced by SD_MultiBlockTest().

volatile TestStatus EraseStatus = FAILED

Definition at line 52 of file STM32F10x_StdPeriph_Examples/SDIO/uSDCard/main.c.

Referenced by SD_EraseTest().

__IO uint32_t SDCardOperation = SD_OPERATION_ERASE

Definition at line 54 of file STM32F10x_StdPeriph_Examples/SDIO/uSDCard/main.c.

Referenced by main().

SD_Error Status = SD_OK

Definition at line 53 of file STM32F10x_StdPeriph_Examples/SDIO/uSDCard/main.c.

volatile TestStatus TransferStatus1 = FAILED

Definition at line 52 of file STM32F10x_StdPeriph_Examples/SDIO/uSDCard/main.c.

volatile TestStatus TransferStatus2 = FAILED

Definition at line 52 of file STM32F10x_StdPeriph_Examples/SDIO/uSDCard/main.c.


STM32F10x Standard Peripherals Firmware Library: SPI_CRC

Defines | Enumerations | Functions | Variables

SPI_CRC

STM32F10x_StdPeriph_Examples

Defines

#define | BufferSize 32

Enumerations

enum TestStatus {
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED
}

Functions

TestStatus | Buffercmp (uint16_t *pBuffer1, uint16_t *pBuffer2, uint16_t BufferLength)
Compares two buffers.
void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | GPIO_Configuration (void)
Configures the different GPIO ports.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | RCC_Configuration (void)
Configures the different system clocks.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

__IO uint16_t | CRC1Value = 0
__IO uint16_t | CRC2Value = 0
uint32_t | RxIdx = 0
uint16_t | SPI1_Buffer_Rx [BufferSize]
uint16_t | SPI1_Buffer_Tx [BufferSize]
uint16_t | SPI2_Buffer_Rx [BufferSize]
uint16_t | SPI2_Buffer_Tx [BufferSize]
SPI_InitTypeDef SPI_InitStructure
volatile TestStatus | TransferStatus1 = FAILED
volatile TestStatus | TransferStatus2 = FAILED
uint32_t | TxIdx = 0

Define Documentation

#define BufferSize 32

Definition at line 37 of file STM32F10x_StdPeriph_Examples/SPI/CRC/main.c.

Referenced by main().

Enumeration Type Documentation

enum TestStatus
Enumerator:
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED

Definition at line 34 of file STM32F10x_StdPeriph_Examples/SPI/CRC/main.c.

Function Documentation

TestStatus Buffercmp | ( | uint16_t * | pBuffer1,
 |  | uint16_t * | pBuffer2,
 |  | uint16_t | BufferLength
 | ) |  |

Compares two buffers.

Parameters:
pBuffer1,pBuffer2,: buffers to be compared.
BufferLength,: buffer's length
Return values:
PASSED,: pBuffer1 identical to pBuffer2 FAILED: pBuffer1 differs from pBuffer2
void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 84 of file STM32F10x_StdPeriph_Examples/SPI/CRC/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 108 of file STM32F10x_StdPeriph_Examples/SPI/CRC/stm32f10x_it.c.

void GPIO_Configuration ( void )

Configures the different GPIO ports.

Parameters:
None
Return values:
None

Definition at line 222 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 60 of file STM32F10x_StdPeriph_Examples/SPI/CRC/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 69 of file STM32F10x_StdPeriph_Examples/SPI/CRC/main.c.

References Buffercmp(), BufferSize, CRC1Value, CRC2Value, ENABLE, FAILED, GPIO_Configuration(), RCC_Configuration(), RESET, RxIdx, SET, SPI1, SPI1_Buffer_Rx, SPI1_Buffer_Tx, SPI2, SPI2_Buffer_Rx, SPI2_Buffer_Tx, SPI_InitTypeDef::SPI_BaudRatePrescaler, SPI_BaudRatePrescaler_8, SPI_CalculateCRC(), SPI_Cmd(), SPI_InitTypeDef::SPI_CPHA, SPI_CPHA_2Edge, SPI_InitTypeDef::SPI_CPOL, SPI_CPOL_Low, SPI_InitTypeDef::SPI_CRCPolynomial, SPI_InitTypeDef::SPI_DataSize, SPI_DataSize_16b, SPI_InitTypeDef::SPI_Direction, SPI_Direction_2Lines_FullDuplex, SPI_InitTypeDef::SPI_FirstBit, SPI_FirstBit_MSB, SPI_FLAG_CRCERR, SPI_I2S_FLAG_RXNE, SPI_I2S_FLAG_TXE, SPI_I2S_GetFlagStatus(), SPI_I2S_ReceiveData(), SPI_I2S_SendData(), SPI_Init(), SPI_InitTypeDef::SPI_Mode, SPI_Mode_Master, SPI_Mode_Slave, SPI_InitTypeDef::SPI_NSS, SPI_NSS_Soft, SPI_TransmitCRC(), TransferStatus1, TransferStatus2, and TxIdx.

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 72 of file STM32F10x_StdPeriph_Examples/SPI/CRC/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 51 of file STM32F10x_StdPeriph_Examples/SPI/CRC/stm32f10x_it.c.

void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 124 of file STM32F10x_StdPeriph_Examples/SPI/CRC/stm32f10x_it.c.

void RCC_Configuration ( void )

Configures the different system clocks.

Parameters:
None
Return values:
None

Definition at line 203 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 116 of file STM32F10x_StdPeriph_Examples/SPI/CRC/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 132 of file STM32F10x_StdPeriph_Examples/SPI/CRC/stm32f10x_it.c.

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 96 of file STM32F10x_StdPeriph_Examples/SPI/CRC/stm32f10x_it.c.

Variable Documentation

__IO uint16_t CRC1Value = 0

Definition at line 56 of file STM32F10x_StdPeriph_Examples/SPI/CRC/main.c.

Referenced by main().

__IO uint16_t CRC2Value = 0

Definition at line 56 of file STM32F10x_StdPeriph_Examples/SPI/CRC/main.c.

Referenced by main().

uint32_t RxIdx = 0

Definition at line 55 of file STM32F10x_StdPeriph_Examples/SPI/CRC/main.c.

uint16_t SPI1_Buffer_Rx[BufferSize]

Definition at line 54 of file STM32F10x_StdPeriph_Examples/SPI/CRC/main.c.

Referenced by main().

uint16_t SPI1_Buffer_Tx[BufferSize]
Initial value:
 {0x0102, 0x0304, 0x0506, 0x0708, 0x090A, 0x0B0C,
                                  0x0D0E, 0x0F10, 0x1112, 0x1314, 0x1516, 0x1718,
                                  0x191A, 0x1B1C, 0x1D1E, 0x1F20, 0x2122, 0x2324,
                                  0x2526, 0x2728, 0x292A, 0x2B2C, 0x2D2E, 0x2F30,
                                  0x3132, 0x3334, 0x3536, 0x3738, 0x393A, 0x3B3C,
                                  0x3D3E, 0x3F40}

Definition at line 42 of file STM32F10x_StdPeriph_Examples/SPI/CRC/main.c.

Referenced by main().

uint16_t SPI2_Buffer_Rx[BufferSize]

Definition at line 54 of file STM32F10x_StdPeriph_Examples/SPI/CRC/main.c.

uint16_t SPI2_Buffer_Tx[BufferSize]
Initial value:
 {0x5152, 0x5354, 0x5556, 0x5758, 0x595A, 0x5B5C,
                                  0x5D5E, 0x5F60, 0x6162, 0x6364, 0x6566, 0x6768,
                                  0x696A, 0x6B6C, 0x6D6E, 0x6F70, 0x7172, 0x7374,
                                  0x7576, 0x7778, 0x797A, 0x7B7C, 0x7D7E, 0x7F80,
                                  0x8182, 0x8384, 0x8586, 0x8788, 0x898A, 0x8B8C,
                                  0x8D8E, 0x8F90}

Definition at line 48 of file STM32F10x_StdPeriph_Examples/SPI/CRC/main.c.

Referenced by main().

SPI_InitTypeDef SPI_InitStructure

Definition at line 41 of file STM32F10x_StdPeriph_Examples/SPI/CRC/main.c.

volatile TestStatus TransferStatus1 = FAILED

Definition at line 57 of file STM32F10x_StdPeriph_Examples/SPI/CRC/main.c.

volatile TestStatus TransferStatus2 = FAILED

Definition at line 57 of file STM32F10x_StdPeriph_Examples/SPI/CRC/main.c.

uint32_t TxIdx = 0

Definition at line 55 of file STM32F10x_StdPeriph_Examples/SPI/CRC/main.c.


STM32F10x Standard Peripherals Firmware Library: SPI_DMA

Defines | Enumerations | Functions | Variables

SPI_DMA

STM32F10x_StdPeriph_Examples

Defines

#define | BufferSize 32

Enumerations

enum TestStatus {
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED
}

Functions

TestStatus | Buffercmp (uint8_t *pBuffer1, uint8_t *pBuffer2, uint16_t BufferLength)
Compares two buffers.
void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | GPIO_Configuration (void)
Configures the different GPIO ports.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | RCC_Configuration (void)
Configures the different system clocks.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

DMA_InitTypeDef DMA_InitStructure
GPIO_InitTypeDef GPIO_InitStructure
SPI_InitTypeDef SPI_InitStructure
uint8_t | SPI_MASTER_Buffer_Tx [BufferSize]
uint8_t | SPI_SLAVE_Buffer_Rx [BufferSize]
volatile TestStatus | TransferStatus = FAILED
__IO uint8_t | TxIdx = 0

Define Documentation

#define BufferSize 32

Definition at line 39 of file STM32F10x_StdPeriph_Examples/SPI/DMA/main.c.

Referenced by main().

Enumeration Type Documentation

enum TestStatus
Enumerator:
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED

Definition at line 36 of file STM32F10x_StdPeriph_Examples/SPI/DMA/main.c.

Function Documentation

TestStatus Buffercmp | ( | uint8_t * | pBuffer1,
 |  | uint8_t * | pBuffer2,
 |  | uint16_t | BufferLength
 | ) |  |

Compares two buffers.

Parameters:
pBuffer1,pBuffer2,: buffers to be compared.
BufferLength,: buffer's length
Return values:
PASSED,: pBuffer1 identical to pBuffer2 FAILED: pBuffer1 differs from pBuffer2
void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 84 of file STM32F10x_StdPeriph_Examples/SPI/DMA/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 108 of file STM32F10x_StdPeriph_Examples/SPI/DMA/stm32f10x_it.c.

void GPIO_Configuration ( void )

Configures the different GPIO ports.

Parameters:
None
Return values:
None

Definition at line 222 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 60 of file STM32F10x_StdPeriph_Examples/SPI/DMA/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 70 of file STM32F10x_StdPeriph_Examples/SPI/DMA/main.c.

References Buffercmp(), BufferSize, DMA_InitTypeDef::DMA_BufferSize, DMA_Cmd(), DMA_DeInit(), DMA_InitTypeDef::DMA_DIR, DMA_DIR_PeripheralSRC, DMA_GetFlagStatus(), DMA_Init(), DMA_InitTypeDef::DMA_M2M, DMA_M2M_Disable, DMA_InitTypeDef::DMA_MemoryBaseAddr, DMA_InitTypeDef::DMA_MemoryDataSize, DMA_MemoryDataSize_Byte, DMA_InitTypeDef::DMA_MemoryInc, DMA_MemoryInc_Enable, DMA_InitTypeDef::DMA_Mode, DMA_Mode_Normal, DMA_InitTypeDef::DMA_PeripheralBaseAddr, DMA_InitTypeDef::DMA_PeripheralDataSize, DMA_PeripheralDataSize_Byte, DMA_InitTypeDef::DMA_PeripheralInc, DMA_PeripheralInc_Disable, DMA_InitTypeDef::DMA_Priority, DMA_Priority_VeryHigh, ENABLE, GPIO_Configuration(), RCC_Configuration(), RESET, SPI_InitTypeDef::SPI_BaudRatePrescaler, SPI_BaudRatePrescaler_4, SPI_Cmd(), SPI_InitTypeDef::SPI_CPHA, SPI_CPHA_1Edge, SPI_InitTypeDef::SPI_CPOL, SPI_CPOL_High, SPI_InitTypeDef::SPI_CRCPolynomial, SPI_InitTypeDef::SPI_DataSize, SPI_DataSize_8b, SPI_InitTypeDef::SPI_Direction, SPI_Direction_1Line_Rx, SPI_Direction_1Line_Tx, SPI_InitTypeDef::SPI_FirstBit, SPI_FirstBit_MSB, SPI_I2S_DMACmd(), SPI_I2S_DMAReq_Rx, SPI_I2S_FLAG_TXE, SPI_I2S_GetFlagStatus(), SPI_I2S_SendData(), SPI_Init(), SPI_MASTER_Buffer_Tx, SPI_InitTypeDef::SPI_Mode, SPI_Mode_Master, SPI_Mode_Slave, SPI_InitTypeDef::SPI_NSS, SPI_NSS_Hard, SPI_SLAVE_Buffer_Rx, SPI_SSOutputCmd(), TransferStatus, and TxIdx.

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 72 of file STM32F10x_StdPeriph_Examples/SPI/DMA/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 51 of file STM32F10x_StdPeriph_Examples/SPI/DMA/stm32f10x_it.c.

void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 124 of file STM32F10x_StdPeriph_Examples/SPI/DMA/stm32f10x_it.c.

void RCC_Configuration ( void )

Configures the different system clocks.

Parameters:
None
Return values:
None

Definition at line 203 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 116 of file STM32F10x_StdPeriph_Examples/SPI/DMA/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 132 of file STM32F10x_StdPeriph_Examples/SPI/DMA/stm32f10x_it.c.

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 96 of file STM32F10x_StdPeriph_Examples/SPI/DMA/stm32f10x_it.c.

Variable Documentation

DMA_InitTypeDef DMA_InitStructure

Definition at line 44 of file STM32F10x_StdPeriph_Examples/SPI/DMA/main.c.

GPIO_InitTypeDef GPIO_InitStructure

Definition at line 45 of file STM32F10x_StdPeriph_Examples/SPI/DMA/main.c.

SPI_InitTypeDef SPI_InitStructure

Definition at line 43 of file STM32F10x_StdPeriph_Examples/SPI/DMA/main.c.

uint8_t SPI_MASTER_Buffer_Tx[BufferSize]
Initial value:
 {0x01, 0x02, 0x03, 0x04, 0x05, 0x06,
                                            0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C,
                                            0x0D, 0x0E, 0x0F, 0x10, 0x11, 0x12,
                                            0x13, 0x14, 0x15, 0x16, 0x17, 0x18,
                                            0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E,
                                            0x1F, 0x20}

Definition at line 47 of file STM32F10x_StdPeriph_Examples/SPI/DMA/main.c.

uint8_t SPI_SLAVE_Buffer_Rx[BufferSize]

Definition at line 53 of file STM32F10x_StdPeriph_Examples/SPI/DMA/main.c.

volatile TestStatus TransferStatus = FAILED

Definition at line 55 of file STM32F10x_StdPeriph_Examples/SPI/DMA/main.c.

__IO uint8_t TxIdx = 0

Definition at line 54 of file STM32F10x_StdPeriph_Examples/SPI/DMA/main.c.


STM32F10x Standard Peripherals Firmware Library: SPI_FullDuplex_SoftNSS

Defines | Enumerations | Functions | Variables

SPI_FullDuplex_SoftNSS

STM32F10x_StdPeriph_Examples

Defines

#define | BufferSize 32

Enumerations

enum TestStatus {
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED
}

Functions

TestStatus | Buffercmp (uint8_t *pBuffer1, uint8_t *pBuffer2, uint16_t BufferLength)
Compares two buffers.
void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | GPIO_Configuration (uint16_t SPIy_Mode, uint16_t SPIz_Mode)
Configures the different SPIy and SPIz GPIO ports.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | RCC_Configuration (void)
Configures the different system clocks.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

__IO uint8_t | k = 0
__IO uint8_t | RxIdx = 0
SPI_InitTypeDef SPI_InitStructure
uint8_t | SPIy_Buffer_Rx [BufferSize]
uint8_t | SPIy_Buffer_Tx [BufferSize]
uint8_t | SPIz_Buffer_Rx [BufferSize]
uint8_t | SPIz_Buffer_Tx [BufferSize]
volatile TestStatus | TransferStatus1 = FAILED
volatile TestStatus | TransferStatus2 = FAILED
volatile TestStatus | TransferStatus3 = FAILED
volatile TestStatus | TransferStatus4 = FAILED
__IO uint8_t | TxIdx = 0

Define Documentation

#define BufferSize 32

Definition at line 38 of file STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/main.c.

Referenced by main().

Enumeration Type Documentation

enum TestStatus
Enumerator:
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED

Definition at line 35 of file STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/main.c.

Function Documentation

TestStatus Buffercmp | ( | uint8_t * | pBuffer1,
 |  | uint8_t * | pBuffer2,
 |  | uint16_t | BufferLength
 | ) |  |

Compares two buffers.

Parameters:
pBuffer1,pBuffer2,: buffers to be compared.
BufferLength,: buffer's length
Return values:
PASSED,: pBuffer1 identical to pBuffer2 FAILED: pBuffer1 differs from pBuffer2
void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 84 of file STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 108 of file STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/stm32f10x_it.c.

void GPIO_Configuration | ( | uint16_t | SPIy_Mode,
 |  | uint16_t | SPIz_Mode
 | ) |  |

Configures the different SPIy and SPIz GPIO ports.

Parameters:
SPIy_Mode,: Specifies the SPIy operating mode. This parameter can be:

  • SPIy_Mode_Master
  • SPIy_Mode_Slave
SPIz_Mode,: Specifies the SPIz operating mode. This parameter can be:

  • SPIz_Mode_Master
  • SPIz_Mode_Slave
Return values:
None

Definition at line 219 of file STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/main.c.

References ENABLE, GPIO_Init(), GPIO_InitStructure, GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_AF_PP, GPIO_Mode_IN_FLOATING, GPIO_InitTypeDef::GPIO_Pin, GPIO_PinRemapConfig(), GPIO_Remap_SPI3, GPIO_InitTypeDef::GPIO_Speed, GPIO_Speed_50MHz, SPI_Mode_Master, and SPI_Mode_Slave.

void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 60 of file STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 68 of file STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/main.c.

References Buffercmp(), BufferSize, ENABLE, GPIO_Configuration(), k, RCC_Configuration(), RESET, RxIdx, SPI_InitTypeDef::SPI_BaudRatePrescaler, SPI_BaudRatePrescaler_4, SPI_Cmd(), SPI_InitTypeDef::SPI_CPHA, SPI_CPHA_2Edge, SPI_InitTypeDef::SPI_CPOL, SPI_CPOL_Low, SPI_InitTypeDef::SPI_CRCPolynomial, SPI_InitTypeDef::SPI_DataSize, SPI_DataSize_8b, SPI_InitTypeDef::SPI_Direction, SPI_Direction_2Lines_FullDuplex, SPI_InitTypeDef::SPI_FirstBit, SPI_FirstBit_LSB, SPI_I2S_FLAG_RXNE, SPI_I2S_FLAG_TXE, SPI_I2S_GetFlagStatus(), SPI_I2S_ReceiveData(), SPI_I2S_SendData(), SPI_Init(), SPI_InitTypeDef::SPI_Mode, SPI_Mode_Master, SPI_Mode_Slave, SPI_InitTypeDef::SPI_NSS, SPI_NSS_Soft, SPIy_Buffer_Rx, SPIy_Buffer_Tx, SPIz_Buffer_Rx, SPIz_Buffer_Tx, TransferStatus1, TransferStatus2, TransferStatus3, TransferStatus4, and TxIdx.

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 72 of file STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 51 of file STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/stm32f10x_it.c.

void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 124 of file STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/stm32f10x_it.c.

void RCC_Configuration ( void )

Configures the different system clocks.

Parameters:
None
Return values:
None

Definition at line 203 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 116 of file STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 132 of file STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/stm32f10x_it.c.

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 96 of file STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/stm32f10x_it.c.

Variable Documentation

__IO uint8_t k = 0

Definition at line 54 of file STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/main.c.

Referenced by main().

__IO uint8_t RxIdx = 0

Definition at line 54 of file STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/main.c.

SPI_InitTypeDef SPI_InitStructure

Definition at line 42 of file STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/main.c.

uint8_t SPIy_Buffer_Rx[BufferSize]

Definition at line 53 of file STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/main.c.

Referenced by main().

uint8_t SPIy_Buffer_Tx[BufferSize]
Initial value:
 {0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
                                      0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E,
                                      0x0F, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15,
                                      0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C,
                                      0x1D, 0x1E, 0x1F, 0x20}

Definition at line 43 of file STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/main.c.

Referenced by main().

uint8_t SPIz_Buffer_Rx[BufferSize]

Definition at line 53 of file STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/main.c.

Referenced by main().

uint8_t SPIz_Buffer_Tx[BufferSize]
Initial value:
 {0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
                                      0x58, 0x59, 0x5A, 0x5B, 0x5C, 0x5D, 0x5E,
                                      0x5F, 0x60, 0x61, 0x62, 0x63, 0x64, 0x65,
                                      0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C,
                                      0x6D, 0x6E, 0x6F, 0x70}

Definition at line 48 of file STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/main.c.

Referenced by main().

volatile TestStatus TransferStatus1 = FAILED

Definition at line 55 of file STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/main.c.

volatile TestStatus TransferStatus2 = FAILED

Definition at line 55 of file STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/main.c.

volatile TestStatus TransferStatus3 = FAILED

Definition at line 56 of file STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/main.c.

volatile TestStatus TransferStatus4 = FAILED

Definition at line 56 of file STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/main.c.

Referenced by main().

__IO uint8_t TxIdx = 0

Definition at line 54 of file STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/main.c.


STM32F10x Standard Peripherals Firmware Library: SPI_Simplex_Interrupt

Defines | Enumerations | Functions | Variables

SPI_Simplex_Interrupt

STM32F10x_StdPeriph_Examples

Defines

#define | BufferSize 32
#define | BufferSize 32

Enumerations

enum TestStatus {
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED
}

Functions

TestStatus | Buffercmp (uint8_t *pBuffer1, uint8_t *pBuffer2, uint16_t BufferLength)
Compares two buffers.
void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | GPIO_Configuration (void)
Configures the different GPIO ports.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | NVIC_Configuration (void)
Configure the nested vectored interrupt controller.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | RCC_Configuration (void)
Configures the different system clocks.
void | SPI1_IRQHandler (void)
This function handles SPI1 or SPI3 global interrupt request.
void | SPI2_IRQHandler (void)
This function handles SPI2 global interrupt request.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

__IO uint8_t | RxIdx = 0
__IO uint8_t | RxIdx
SPI_InitTypeDef SPI_InitStructure
uint8_t | SPI_MASTER_Buffer_Tx [BufferSize]
uint8_t | SPI_MASTER_Buffer_Tx [BufferSize]
uint8_t | SPI_SLAVE_Buffer_Rx [BufferSize]
uint8_t | SPI_SLAVE_Buffer_Rx [BufferSize]
volatile TestStatus | TransferStatus = FAILED
__IO uint8_t | TxIdx = 0
__IO uint8_t | TxIdx

Define Documentation

#define BufferSize 32

Definition at line 38 of file STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/main.c.

Referenced by main().

#define BufferSize 32

Definition at line 38 of file STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.c.

Referenced by SPI1_IRQHandler().

Enumeration Type Documentation

enum TestStatus
Enumerator:
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED

Definition at line 35 of file STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/main.c.

Function Documentation

TestStatus Buffercmp | ( | uint8_t * | pBuffer1,
 |  | uint8_t * | pBuffer2,
 |  | uint16_t | BufferLength
 | ) |  |

Compares two buffers.

Parameters:
pBuffer1,pBuffer2,: buffers to be compared.
BufferLength,: buffer's length
Return values:
PASSED,: pBuffer1 identical to pBuffer2 FAILED: pBuffer1 differs from pBuffer2
void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 91 of file STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 115 of file STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.c.

void GPIO_Configuration ( void )

Configures the different GPIO ports.

Parameters:
None
Return values:
None

Definition at line 222 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 67 of file STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 64 of file STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/main.c.

References Buffercmp(), BufferSize, ENABLE, GPIO_Configuration(), NVIC_Configuration(), RCC_Configuration(), RxIdx, SPI_InitTypeDef::SPI_BaudRatePrescaler, SPI_BaudRatePrescaler_4, SPI_Cmd(), SPI_InitTypeDef::SPI_CPHA, SPI_CPHA_2Edge, SPI_InitTypeDef::SPI_CPOL, SPI_CPOL_Low, SPI_InitTypeDef::SPI_CRCPolynomial, SPI_InitTypeDef::SPI_DataSize, SPI_DataSize_8b, SPI_InitTypeDef::SPI_Direction, SPI_Direction_1Line_Rx, SPI_Direction_1Line_Tx, SPI_InitTypeDef::SPI_FirstBit, SPI_FirstBit_MSB, SPI_I2S_IT_RXNE, SPI_I2S_IT_TXE, SPI_I2S_ITConfig(), SPI_Init(), SPI_MASTER_Buffer_Tx, SPI_InitTypeDef::SPI_Mode, SPI_Mode_Master, SPI_Mode_Slave, SPI_InitTypeDef::SPI_NSS, SPI_NSS_Soft, SPI_SLAVE_Buffer_Rx, and TransferStatus.

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 79 of file STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 58 of file STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.c.

void NVIC_Configuration ( void )

Configure the nested vectored interrupt controller.

Parameters:
None
Return values:
None
void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 131 of file STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.c.

void RCC_Configuration ( void )

Configures the different system clocks.

Parameters:
None
Return values:
None

Definition at line 203 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void SPI1_IRQHandler ( void )

This function handles SPI1 or SPI3 global interrupt request.

Parameters:
None
Return values:
None

Definition at line 152 of file STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.c.

References BufferSize, DISABLE, RESET, SPI_I2S_GetITStatus(), SPI_I2S_IT_TXE, SPI_I2S_ITConfig(), SPI_I2S_SendData(), SPI_MASTER_Buffer_Tx, and TxIdx.

void SPI2_IRQHandler ( void )

This function handles SPI2 global interrupt request.

Parameters:
None
Return values:
None

Definition at line 175 of file STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.c.

References I2S2_Buffer_Rx, RxIdx, SET, SPI2, SPI_I2S_GetITStatus(), SPI_I2S_IT_RXNE, SPI_I2S_ReceiveData(), and SPI_SLAVE_Buffer_Rx.

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 123 of file STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 139 of file STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.c.

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 103 of file STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.c.

Variable Documentation

__IO uint8_t RxIdx = 0

Definition at line 50 of file STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/main.c.

__IO uint8_t RxIdx

Definition at line 48 of file STM32F10x_StdPeriph_Examples/I2S/Interrupt/main.c.

Referenced by main(), SPI2_IRQHandler(), and SPI3_IRQHandler().

SPI_InitTypeDef SPI_InitStructure

Definition at line 42 of file STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/main.c.

uint8_t SPI_MASTER_Buffer_Tx[BufferSize]

Definition at line 50 of file STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/main.c.

Referenced by main(), and SPI1_IRQHandler().

uint8_t SPI_MASTER_Buffer_Tx[BufferSize]
Initial value:
 {0x01, 0x02, 0x03, 0x04, 0x05, 0x06,
                                            0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C,
                                            0x0D, 0x0E, 0x0F, 0x10, 0x11, 0x12,
                                            0x13, 0x14, 0x15, 0x16, 0x17, 0x18,
                                            0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E,
                                            0x1F, 0x20}

Definition at line 43 of file STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/main.c.

uint8_t SPI_SLAVE_Buffer_Rx[BufferSize]

Definition at line 46 of file STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/main.c.

Referenced by main(), and SPI2_IRQHandler().

uint8_t SPI_SLAVE_Buffer_Rx[BufferSize]

Definition at line 49 of file STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/main.c.

volatile TestStatus TransferStatus = FAILED

Definition at line 51 of file STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/main.c.

__IO uint8_t TxIdx = 0

Definition at line 50 of file STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/main.c.

__IO uint8_t TxIdx

Definition at line 48 of file STM32F10x_StdPeriph_Examples/I2S/Interrupt/main.c.

Referenced by main(), SPI1_IRQHandler(), and SPI3_IRQHandler().


STM32F10x Standard Peripherals Firmware Library: SPI_FLASH

Defines | Enumerations | Functions | Variables

SPI_FLASH

STM32F10x_StdPeriph_Examples

Defines

#define | BufferSize (countof(Tx_Buffer)-1)
#define | countof(a) (sizeof(a) / sizeof(*(a)))
#define | FLASH_ReadAddress FLASH_WriteAddress
#define | FLASH_SectorToErase FLASH_WriteAddress
#define | FLASH_WriteAddress 0x700000
#define | sFLASH_ID sFLASH_M25P64_ID

Enumerations

enum TestStatus {
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED
}

Functions

TestStatus | Buffercmp (uint8_t *pBuffer1, uint8_t *pBuffer2, uint16_t BufferLength)
Compares two buffers.
void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

__IO uint32_t | FlashID = 0
__IO uint8_t | Index = 0x0
uint8_t | Rx_Buffer [BufferSize]
volatile TestStatus | TransferStatus1 = FAILED
volatile TestStatus | TransferStatus2 = PASSED
uint8_t | Tx_Buffer [] = "STM32F10x SPI Firmware Library Example: communication with an M25P SPI FLASH"

Define Documentation

#define BufferSize (countof(Tx_Buffer)-1)

Definition at line 48 of file STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/main.c.

Referenced by main().

#define countof ( a ) (sizeof(a) / sizeof(*(a)))

Definition at line 51 of file STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/main.c.

#define FLASH_ReadAddress FLASH_WriteAddress

Definition at line 39 of file STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/main.c.

Referenced by main().

#define FLASH_SectorToErase FLASH_WriteAddress

Definition at line 40 of file STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/main.c.

Referenced by main().

#define FLASH_WriteAddress 0x700000

Definition at line 38 of file STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/main.c.

Referenced by main().

#define sFLASH_ID sFLASH_M25P64_ID

Definition at line 45 of file STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/main.c.

Referenced by main().

Enumeration Type Documentation

enum TestStatus
Enumerator:
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED

Definition at line 35 of file STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/main.c.

Function Documentation

TestStatus Buffercmp | ( | uint8_t * | pBuffer1,
 |  | uint8_t * | pBuffer2,
 |  | uint16_t | BufferLength
 | ) |  |

Compares two buffers.

Parameters:
pBuffer1,pBuffer2,: buffers to be compared.
BufferLength,: buffer's length
Return values:
PASSED,: pBuffer1 identical to pBuffer2 FAILED: pBuffer1 differs from pBuffer2
void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 84 of file STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 108 of file STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/stm32f10x_it.c.

void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 60 of file STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 68 of file STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/main.c.

References Buffercmp(), BufferSize, FAILED, FLASH_ReadAddress, FLASH_SectorToErase, FLASH_WriteAddress, FlashID, Index, LED1, LED2, Rx_Buffer, sFLASH_EraseSector(), sFLASH_ID, sFLASH_Init(), sFLASH_ReadBuffer(), sFLASH_ReadID(), sFLASH_WriteBuffer(), STM_EVAL_LEDInit(), STM_EVAL_LEDOn(), TransferStatus1, TransferStatus2, and Tx_Buffer.

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 72 of file STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 51 of file STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/stm32f10x_it.c.

void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 124 of file STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/stm32f10x_it.c.

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 116 of file STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 132 of file STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/stm32f10x_it.c.

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 96 of file STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/stm32f10x_it.c.

Variable Documentation

__IO uint32_t FlashID = 0

Definition at line 58 of file STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/main.c.

Referenced by main().

__IO uint8_t Index = 0x0

Definition at line 56 of file STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/main.c.

uint8_t Rx_Buffer[BufferSize]

Definition at line 55 of file STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/main.c.

Referenced by main().

volatile TestStatus TransferStatus1 = FAILED

Definition at line 57 of file STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/main.c.

volatile TestStatus TransferStatus2 = PASSED

Definition at line 57 of file STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/main.c.

uint8_t Tx_Buffer[] = "STM32F10x SPI Firmware Library Example: communication with an M25P SPI FLASH"

Definition at line 54 of file STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/main.c.

Referenced by main().


STM32F10x Standard Peripherals Firmware Library: SysTick_TimeBase

Functions | Variables

SysTick_TimeBase

STM32F10x_StdPeriph_Examples

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | Delay (__IO uint32_t nTime)
Inserts a delay time.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | TimingDelay_Decrement (void)
Decrements the TimingDelay variable.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

static __IO uint32_t | TimingDelay

Function Documentation

void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 87 of file STM32F10x_StdPeriph_Examples/SysTick/TimeBase/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 122 of file STM32F10x_StdPeriph_Examples/SysTick/TimeBase/stm32f10x_it.c.

void Delay ( __IO uint32_t nTime )

Inserts a delay time.

Parameters:
nTime,: specifies the delay time length, in milliseconds.
Return values:
None
void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 61 of file STM32F10x_StdPeriph_Examples/SysTick/TimeBase/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 49 of file STM32F10x_StdPeriph_Examples/SysTick/TimeBase/main.c.

References Delay(), LED1, LED2, LED3, LED4, STM_EVAL_LEDInit(), STM_EVAL_LEDOn(), STM_EVAL_LEDToggle(), and SystemCoreClock.

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 74 of file STM32F10x_StdPeriph_Examples/SysTick/TimeBase/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 52 of file STM32F10x_StdPeriph_Examples/SysTick/TimeBase/stm32f10x_it.c.

void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 131 of file STM32F10x_StdPeriph_Examples/SysTick/TimeBase/stm32f10x_it.c.

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 113 of file STM32F10x_StdPeriph_Examples/SysTick/TimeBase/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 140 of file STM32F10x_StdPeriph_Examples/SysTick/TimeBase/stm32f10x_it.c.

References TimingDelay_Decrement().

void TimingDelay_Decrement ( void )

Decrements the TimingDelay variable.

Parameters:
None
Return values:
None

Definition at line 135 of file STM32F10x_StdPeriph_Examples/SysTick/TimeBase/main.c.

References TimingDelay.

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 100 of file STM32F10x_StdPeriph_Examples/SysTick/TimeBase/stm32f10x_it.c.

Variable Documentation

__IO uint32_t TimingDelay [static]

Definition at line 37 of file STM32F10x_StdPeriph_Examples/SysTick/TimeBase/main.c.


STM32F10x Standard Peripherals Firmware Library: TIM_6Steps

Functions | Variables

TIM_6Steps

STM32F10x_StdPeriph_Examples

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | GPIO_Configuration (void)
Configure the TIM1 Pins.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | NVIC_Configuration (void)
Configures the nested vectored interrupt controller.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | RCC_Configuration (void)
Configures the different system clocks.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Configuration (void)
Configures the SysTick.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | TIM1_TRG_COM_IRQHandler (void)
This function handles TIM1 Trigger and commutation interrupts requests.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

uint16_t | CCR1_Val = 32767
uint16_t | CCR2_Val = 24575
uint16_t | CCR3_Val = 16383
uint16_t | CCR4_Val = 8191
__IO uint32_t | step = 1
TIM_BDTRInitTypeDef TIM_BDTRInitStructure
TIM_OCInitTypeDef TIM_OCInitStructure
TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure

Function Documentation

void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 86 of file STM32F10x_StdPeriph_Examples/TIM/6Steps/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 110 of file STM32F10x_StdPeriph_Examples/TIM/6Steps/stm32f10x_it.c.

void GPIO_Configuration ( void )

Configure the TIM1 Pins.

Configures the different GPIO ports.

Parameters:
None
Return values:
None

Definition at line 222 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 62 of file STM32F10x_StdPeriph_Examples/TIM/6Steps/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 58 of file STM32F10x_StdPeriph_Examples/TIM/6Steps/main.c.

References ENABLE, GPIO_Configuration(), NVIC_Configuration(), RCC_Configuration(), SysTick_Configuration(), TIM1, TIM_BDTRInitTypeDef::TIM_AutomaticOutput, TIM_AutomaticOutput_Enable, TIM_BDTRConfig(), TIM_BDTRInitTypeDef::TIM_Break, TIM_Break_Enable, TIM_BDTRInitTypeDef::TIM_BreakPolarity, TIM_BreakPolarity_High, TIM_CCPreloadControl(), TIM_TimeBaseInitTypeDef::TIM_ClockDivision, TIM_Cmd(), TIM_TimeBaseInitTypeDef::TIM_CounterMode, TIM_CounterMode_Up, TIM_CtrlPWMOutputs(), TIM_BDTRInitTypeDef::TIM_DeadTime, TIM_IT_COM, TIM_ITConfig(), TIM_BDTRInitTypeDef::TIM_LOCKLevel, TIM_LOCKLevel_OFF, TIM_OC1Init(), TIM_OC2Init(), TIM_OC3Init(), TIM_OCInitTypeDef::TIM_OCIdleState, TIM_OCIdleState_Set, TIM_OCInitTypeDef::TIM_OCMode, TIM_OCMode_Timing, TIM_OCInitTypeDef::TIM_OCNIdleState, TIM_OCNIdleState_Set, TIM_OCInitTypeDef::TIM_OCNPolarity, TIM_OCNPolarity_High, TIM_OCInitTypeDef::TIM_OCPolarity, TIM_OCPolarity_High, TIM_BDTRInitTypeDef::TIM_OSSIState, TIM_OSSIState_Enable, TIM_BDTRInitTypeDef::TIM_OSSRState, TIM_OSSRState_Enable, TIM_OCInitTypeDef::TIM_OutputNState, TIM_OutputNState_Enable, TIM_OCInitTypeDef::TIM_OutputState, TIM_OutputState_Enable, TIM_TimeBaseInitTypeDef::TIM_Period, TIM_TimeBaseInitTypeDef::TIM_Prescaler, TIM_OCInitTypeDef::TIM_Pulse, TIM_TimeBaseInitTypeDef::TIM_RepetitionCounter, and TIM_TimeBaseInit().

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 74 of file STM32F10x_StdPeriph_Examples/TIM/6Steps/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 53 of file STM32F10x_StdPeriph_Examples/TIM/6Steps/stm32f10x_it.c.

void NVIC_Configuration ( void )

Configures the nested vectored interrupt controller.

Parameters:
None
Return values:
None
void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 126 of file STM32F10x_StdPeriph_Examples/TIM/6Steps/stm32f10x_it.c.

void RCC_Configuration ( void )

Configures the different system clocks.

Parameters:
None
Return values:
None

Definition at line 203 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 118 of file STM32F10x_StdPeriph_Examples/TIM/6Steps/stm32f10x_it.c.

void SysTick_Configuration ( void )

Configures the SysTick.

Parameters:
None
Return values:
None
void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 134 of file STM32F10x_StdPeriph_Examples/TIM/6Steps/stm32f10x_it.c.

References TIM1, TIM_EventSource_COM, and TIM_GenerateEvent().

void TIM1_TRG_COM_IRQHandler ( void )

This function handles TIM1 Trigger and commutation interrupts requests.

Parameters:
None
Return values:
None

Definition at line 153 of file STM32F10x_StdPeriph_Examples/TIM/6Steps/stm32f10x_it.c.

References step, TIM1, TIM_CCx_Disable, TIM_CCx_Enable, TIM_CCxCmd(), TIM_CCxN_Disable, TIM_CCxN_Enable, TIM_CCxNCmd(), TIM_Channel_1, TIM_Channel_2, TIM_Channel_3, TIM_ClearITPendingBit(), TIM_IT_COM, TIM_OCMode_PWM1, and TIM_SelectOCxM().

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 98 of file STM32F10x_StdPeriph_Examples/TIM/6Steps/stm32f10x_it.c.

Variable Documentation

uint16_t CCR1_Val = 32767

Definition at line 40 of file STM32F10x_StdPeriph_Examples/TIM/6Steps/main.c.

Referenced by main(), TIM2_IRQHandler(), and TIM3_IRQHandler().

uint16_t CCR2_Val = 24575

Definition at line 41 of file STM32F10x_StdPeriph_Examples/TIM/6Steps/main.c.

Referenced by main(), TIM2_IRQHandler(), and TIM3_IRQHandler().

uint16_t CCR3_Val = 16383

Definition at line 42 of file STM32F10x_StdPeriph_Examples/TIM/6Steps/main.c.

Referenced by main(), TIM2_IRQHandler(), and TIM3_IRQHandler().

uint16_t CCR4_Val = 8191

Definition at line 43 of file STM32F10x_StdPeriph_Examples/TIM/6Steps/main.c.

Referenced by main(), TIM2_IRQHandler(), and TIM3_IRQHandler().

__IO uint32_t step = 1

Definition at line 39 of file STM32F10x_StdPeriph_Examples/TIM/6Steps/stm32f10x_it.c.

Referenced by TIM1_TRG_COM_IRQHandler().

TIM_BDTRInitTypeDef TIM_BDTRInitStructure

Definition at line 39 of file STM32F10x_StdPeriph_Examples/TIM/6Steps/main.c.

TIM_OCInitTypeDef TIM_OCInitStructure

Definition at line 38 of file STM32F10x_StdPeriph_Examples/TIM/6Steps/main.c.

TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure

Definition at line 37 of file STM32F10x_StdPeriph_Examples/TIM/6Steps/main.c.


STM32F10x Standard Peripherals Firmware Library: TIM_7PWM_Output

Functions | Variables

TIM_7PWM_Output

STM32F10x_StdPeriph_Examples

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | GPIO_Configuration (void)
Configure the TIM1 Pins.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | RCC_Configuration (void)
Configures the different system clocks.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

uint16_t | Channel1Pulse = 0
uint16_t | Channel2Pulse = 0
uint16_t | Channel3Pulse = 0
uint16_t | Channel4Pulse = 0
TIM_OCInitTypeDef TIM_OCInitStructure
TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure
uint16_t | TimerPeriod = 0

Function Documentation

void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 83 of file STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 107 of file STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/stm32f10x_it.c.

void GPIO_Configuration ( void )

Configure the TIM1 Pins.

Configures the different GPIO ports.

Parameters:
None
Return values:
None

Definition at line 222 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 59 of file STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 53 of file STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/main.c.

References Channel1Pulse, Channel2Pulse, Channel3Pulse, Channel4Pulse, ENABLE, GPIO_Configuration(), RCC_Configuration(), SystemCoreClock, TIM1, TIM_TimeBaseInitTypeDef::TIM_ClockDivision, TIM_Cmd(), TIM_TimeBaseInitTypeDef::TIM_CounterMode, TIM_CounterMode_Up, TIM_CtrlPWMOutputs(), TIM_OC1Init(), TIM_OC2Init(), TIM_OC3Init(), TIM_OC4Init(), TIM_OCInitTypeDef::TIM_OCIdleState, TIM_OCIdleState_Reset, TIM_OCIdleState_Set, TIM_OCInitTypeDef::TIM_OCMode, TIM_OCMode_PWM2, TIM_OCInitTypeDef::TIM_OCNIdleState, TIM_OCInitTypeDef::TIM_OCNPolarity, TIM_OCNPolarity_High, TIM_OCInitTypeDef::TIM_OCPolarity, TIM_OCPolarity_Low, TIM_OCInitTypeDef::TIM_OutputNState, TIM_OutputNState_Enable, TIM_OCInitTypeDef::TIM_OutputState, TIM_OutputState_Enable, TIM_TimeBaseInitTypeDef::TIM_Period, TIM_TimeBaseInitTypeDef::TIM_Prescaler, TIM_OCInitTypeDef::TIM_Pulse, TIM_TimeBaseInitTypeDef::TIM_RepetitionCounter, TIM_TimeBaseInit(), and TimerPeriod.

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 71 of file STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 51 of file STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/stm32f10x_it.c.

void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 123 of file STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/stm32f10x_it.c.

void RCC_Configuration ( void )

Configures the different system clocks.

Parameters:
None
Return values:
None

Definition at line 203 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 115 of file STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 131 of file STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/stm32f10x_it.c.

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 95 of file STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/stm32f10x_it.c.

Variable Documentation

uint16_t Channel1Pulse = 0

Definition at line 40 of file STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/main.c.

Referenced by main().

uint16_t Channel2Pulse = 0

Definition at line 40 of file STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/main.c.

Referenced by main().

uint16_t Channel3Pulse = 0

Definition at line 40 of file STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/main.c.

Referenced by main().

uint16_t Channel4Pulse = 0

Definition at line 40 of file STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/main.c.

Referenced by main().

TIM_OCInitTypeDef TIM_OCInitStructure

Definition at line 38 of file STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/main.c.

TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure

Definition at line 37 of file STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/main.c.

uint16_t TimerPeriod = 0

Definition at line 39 of file STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/main.c.

Referenced by main().


STM32F10x Standard Peripherals Firmware Library: TIM_Cascade_Synchro

Functions | Variables

TIM_Cascade_Synchro

STM32F10x_StdPeriph_Examples

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | GPIO_Configuration (void)
Configure the GPIOD Pins.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | RCC_Configuration (void)
Configures the different system clocks.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

TIM_OCInitTypeDef TIM_OCInitStructure
TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure

Function Documentation

void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 83 of file STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 107 of file STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f10x_it.c.

void GPIO_Configuration ( void )

Configure the GPIOD Pins.

Configures the different GPIO ports.

Parameters:
None
Return values:
None

Definition at line 222 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 59 of file STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 51 of file STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/main.c.

References ENABLE, GPIO_Configuration(), RCC_Configuration(), TIM2, TIM3, TIM4, TIM_TimeBaseInitTypeDef::TIM_ClockDivision, TIM_Cmd(), TIM_TimeBaseInitTypeDef::TIM_CounterMode, TIM_CounterMode_Up, TIM_MasterSlaveMode_Enable, TIM_OC1Init(), TIM_OCInitTypeDef::TIM_OCMode, TIM_OCMode_PWM1, TIM_OCInitTypeDef::TIM_OCPolarity, TIM_OCPolarity_High, TIM_OCInitTypeDef::TIM_OutputState, TIM_OutputState_Enable, TIM_TimeBaseInitTypeDef::TIM_Period, TIM_TimeBaseInitTypeDef::TIM_Prescaler, TIM_OCInitTypeDef::TIM_Pulse, TIM_SelectInputTrigger(), TIM_SelectMasterSlaveMode(), TIM_SelectOutputTrigger(), TIM_SelectSlaveMode(), TIM_SlaveMode_Gated, TIM_TimeBaseInit(), TIM_TRGOSource_Update, TIM_TS_ITR1, and TIM_TS_ITR2.

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 71 of file STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 51 of file STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f10x_it.c.

void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 123 of file STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f10x_it.c.

void RCC_Configuration ( void )

Configures the different system clocks.

Parameters:
None
Return values:
None

Definition at line 203 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 115 of file STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 131 of file STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f10x_it.c.

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 95 of file STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f10x_it.c.

Variable Documentation

TIM_OCInitTypeDef TIM_OCInitStructure

Definition at line 38 of file STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/main.c.

TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure

Definition at line 37 of file STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/main.c.


STM32F10x Standard Peripherals Firmware Library: TIM_ComplementarySignals

Functions | Variables

TIM_ComplementarySignals

STM32F10x_StdPeriph_Examples

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | GPIO_Configuration (void)
Configure the TIM1 Pins.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | RCC_Configuration (void)
Configures the different system clocks.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

uint16_t | Channel1Pulse = 0
uint16_t | Channel2Pulse = 0
uint16_t | Channel3Pulse = 0
TIM_BDTRInitTypeDef TIM_BDTRInitStructure
TIM_OCInitTypeDef TIM_OCInitStructure
TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure
uint16_t | TimerPeriod = 0

Function Documentation

void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 83 of file STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 107 of file STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/stm32f10x_it.c.

void GPIO_Configuration ( void )

Configure the TIM1 Pins.

Configures the different GPIO ports.

Parameters:
None
Return values:
None

Definition at line 222 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 59 of file STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 54 of file STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/main.c.

References Channel1Pulse, Channel2Pulse, Channel3Pulse, ENABLE, GPIO_Configuration(), RCC_Configuration(), SystemCoreClock, TIM1, TIM_BDTRInitTypeDef::TIM_AutomaticOutput, TIM_AutomaticOutput_Enable, TIM_BDTRConfig(), TIM_BDTRInitTypeDef::TIM_Break, TIM_Break_Enable, TIM_BDTRInitTypeDef::TIM_BreakPolarity, TIM_BreakPolarity_High, TIM_TimeBaseInitTypeDef::TIM_ClockDivision, TIM_Cmd(), TIM_TimeBaseInitTypeDef::TIM_CounterMode, TIM_CounterMode_Up, TIM_CtrlPWMOutputs(), TIM_BDTRInitTypeDef::TIM_DeadTime, TIM_BDTRInitTypeDef::TIM_LOCKLevel, TIM_LOCKLevel_1, TIM_OC1Init(), TIM_OC2Init(), TIM_OC3Init(), TIM_OCInitTypeDef::TIM_OCIdleState, TIM_OCIdleState_Reset, TIM_OCIdleState_Set, TIM_OCInitTypeDef::TIM_OCMode, TIM_OCMode_PWM2, TIM_OCInitTypeDef::TIM_OCNIdleState, TIM_OCInitTypeDef::TIM_OCNPolarity, TIM_OCNPolarity_Low, TIM_OCInitTypeDef::TIM_OCPolarity, TIM_OCPolarity_Low, TIM_BDTRInitTypeDef::TIM_OSSIState, TIM_OSSIState_Enable, TIM_BDTRInitTypeDef::TIM_OSSRState, TIM_OSSRState_Enable, TIM_OCInitTypeDef::TIM_OutputNState, TIM_OutputNState_Enable, TIM_OCInitTypeDef::TIM_OutputState, TIM_OutputState_Enable, TIM_TimeBaseInitTypeDef::TIM_Period, TIM_TimeBaseInitTypeDef::TIM_Prescaler, TIM_OCInitTypeDef::TIM_Pulse, TIM_TimeBaseInitTypeDef::TIM_RepetitionCounter, TIM_TimeBaseInit(), and TimerPeriod.

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 71 of file STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 51 of file STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/stm32f10x_it.c.

void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 123 of file STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/stm32f10x_it.c.

void RCC_Configuration ( void )

Configures the different system clocks.

Parameters:
None
Return values:
None

Definition at line 203 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 115 of file STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 131 of file STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/stm32f10x_it.c.

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 95 of file STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/stm32f10x_it.c.

Variable Documentation

uint16_t Channel1Pulse = 0

Definition at line 41 of file STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/main.c.

uint16_t Channel2Pulse = 0

Definition at line 41 of file STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/main.c.

uint16_t Channel3Pulse = 0

Definition at line 41 of file STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/main.c.

TIM_BDTRInitTypeDef TIM_BDTRInitStructure

Definition at line 39 of file STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/main.c.

TIM_OCInitTypeDef TIM_OCInitStructure

Definition at line 38 of file STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/main.c.

TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure

Definition at line 37 of file STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/main.c.

uint16_t TimerPeriod = 0

Definition at line 40 of file STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/main.c.


STM32F10x Standard Peripherals Firmware Library: TIM_DMA

Defines | Functions | Variables

TIM_DMA

STM32F10x_StdPeriph_Examples

Defines

#define | TIM1_CCR3_Address 0x40012C3C

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | DMA_Configuration (void)
Configures the DMA.
void | GPIO_Configuration (void)
Configure the TIM1 Pins.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | RCC_Configuration (void)
Configures the different system clocks.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

uint16_t | SRC_Buffer [3] = {0, 0, 0}
TIM_OCInitTypeDef TIM_OCInitStructure
TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure
uint16_t | TimerPeriod = 0

Define Documentation

#define TIM1_CCR3_Address 0x40012C3C

Definition at line 35 of file STM32F10x_StdPeriph_Examples/TIM/DMA/main.c.

Function Documentation

void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 84 of file STM32F10x_StdPeriph_Examples/TIM/DMA/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 108 of file STM32F10x_StdPeriph_Examples/TIM/DMA/stm32f10x_it.c.

void DMA_Configuration ( void )

Configures the DMA.

Parameters:
None
Return values:
None
void GPIO_Configuration ( void )

Configure the TIM1 Pins.

Configures the different GPIO ports.

Parameters:
None
Return values:
None

Definition at line 222 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 60 of file STM32F10x_StdPeriph_Examples/TIM/DMA/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 56 of file STM32F10x_StdPeriph_Examples/TIM/DMA/main.c.

References DMA_Configuration(), ENABLE, GPIO_Configuration(), RCC_Configuration(), SRC_Buffer, SystemCoreClock, TIM1, TIM_TimeBaseInitTypeDef::TIM_ClockDivision, TIM_Cmd(), TIM_TimeBaseInitTypeDef::TIM_CounterMode, TIM_CounterMode_Up, TIM_CtrlPWMOutputs(), TIM_DMA_Update, TIM_DMACmd(), TIM_OC3Init(), TIM_OCInitTypeDef::TIM_OCIdleState, TIM_OCIdleState_Reset, TIM_OCIdleState_Set, TIM_OCInitTypeDef::TIM_OCMode, TIM_OCMode_PWM2, TIM_OCInitTypeDef::TIM_OCNIdleState, TIM_OCInitTypeDef::TIM_OCNPolarity, TIM_OCNPolarity_Low, TIM_OCInitTypeDef::TIM_OCPolarity, TIM_OCPolarity_Low, TIM_OCInitTypeDef::TIM_OutputNState, TIM_OutputNState_Enable, TIM_OCInitTypeDef::TIM_OutputState, TIM_OutputState_Enable, TIM_TimeBaseInitTypeDef::TIM_Period, TIM_TimeBaseInitTypeDef::TIM_Prescaler, TIM_OCInitTypeDef::TIM_Pulse, TIM_TimeBaseInitTypeDef::TIM_RepetitionCounter, TIM_TimeBaseInit(), and TimerPeriod.

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 72 of file STM32F10x_StdPeriph_Examples/TIM/DMA/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 51 of file STM32F10x_StdPeriph_Examples/TIM/DMA/stm32f10x_it.c.

void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 124 of file STM32F10x_StdPeriph_Examples/TIM/DMA/stm32f10x_it.c.

void RCC_Configuration ( void )

Configures the different system clocks.

Parameters:
None
Return values:
None

Definition at line 203 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 116 of file STM32F10x_StdPeriph_Examples/TIM/DMA/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 132 of file STM32F10x_StdPeriph_Examples/TIM/DMA/stm32f10x_it.c.

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 96 of file STM32F10x_StdPeriph_Examples/TIM/DMA/stm32f10x_it.c.

Variable Documentation

uint16_t SRC_Buffer[3] = {0, 0, 0}

Definition at line 41 of file STM32F10x_StdPeriph_Examples/TIM/DMA/main.c.

TIM_OCInitTypeDef TIM_OCInitStructure

Definition at line 40 of file STM32F10x_StdPeriph_Examples/TIM/DMA/main.c.

TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure

Definition at line 39 of file STM32F10x_StdPeriph_Examples/TIM/DMA/main.c.

uint16_t TimerPeriod = 0

Definition at line 42 of file STM32F10x_StdPeriph_Examples/TIM/DMA/main.c.


STM32F10x Standard Peripherals Firmware Library: TIM_DMABurst

Defines | Functions | Variables

TIM_DMABurst

STM32F10x_StdPeriph_Examples

Defines

#define | TIM1_DMAR_ADDRESS ((uint32_t)0x40012C4C)

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

DMA_InitTypeDef DMA_InitStructure
GPIO_InitTypeDef GPIO_InitStructure
uint16_t | SRC_Buffer [6] = {0x0FFF, 0x0000, 0x0555}
TIM_OCInitTypeDef TIM_OCInitStructure
TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure

Define Documentation

#define TIM1_DMAR_ADDRESS ((uint32_t)0x40012C4C)

Definition at line 35 of file STM32F10x_StdPeriph_Examples/TIM/DMABurst/main.c.

Referenced by main().

Function Documentation

void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 86 of file STM32F10x_StdPeriph_Examples/TIM/DMABurst/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 121 of file STM32F10x_StdPeriph_Examples/TIM/DMABurst/stm32f10x_it.c.

void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 60 of file STM32F10x_StdPeriph_Examples/TIM/DMABurst/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 53 of file STM32F10x_StdPeriph_Examples/TIM/DMABurst/main.c.

References DMA1_Channel5, DMA1_FLAG_TC5, DMA_InitTypeDef::DMA_BufferSize, DMA_Cmd(), DMA_DeInit(), DMA_InitTypeDef::DMA_DIR, DMA_DIR_PeripheralDST, DMA_GetFlagStatus(), DMA_Init(), DMA_InitTypeDef::DMA_M2M, DMA_M2M_Disable, DMA_InitTypeDef::DMA_MemoryBaseAddr, DMA_InitTypeDef::DMA_MemoryDataSize, DMA_MemoryDataSize_HalfWord, DMA_InitTypeDef::DMA_MemoryInc, DMA_MemoryInc_Enable, DMA_InitTypeDef::DMA_Mode, DMA_Mode_Normal, DMA_InitTypeDef::DMA_PeripheralBaseAddr, DMA_InitTypeDef::DMA_PeripheralDataSize, DMA_PeripheralDataSize_HalfWord, DMA_InitTypeDef::DMA_PeripheralInc, DMA_PeripheralInc_Disable, DMA_InitTypeDef::DMA_Priority, DMA_Priority_High, ENABLE, GPIO_Init(), GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_AF_PP, GPIO_InitTypeDef::GPIO_Pin, GPIO_Pin_8, GPIO_InitTypeDef::GPIO_Speed, GPIO_Speed_50MHz, GPIOA, RCC_AHBPeriph_DMA1, RCC_AHBPeriphClockCmd(), RCC_APB2Periph_GPIOA, RCC_APB2Periph_TIM1, RCC_APB2PeriphClockCmd(), SRC_Buffer, SystemCoreClock, TIM1, TIM1_DMAR_ADDRESS, TIM_TimeBaseInitTypeDef::TIM_ClockDivision, TIM_Cmd(), TIM_TimeBaseInitTypeDef::TIM_CounterMode, TIM_CounterMode_Up, TIM_CtrlPWMOutputs(), TIM_DeInit(), TIM_DMA_Update, TIM_DMABase_ARR, TIM_DMABurstLength_3Transfers, TIM_DMACmd(), TIM_DMAConfig(), TIM_OC1Init(), TIM_OCInitTypeDef::TIM_OCMode, TIM_OCMode_PWM1, TIM_OCInitTypeDef::TIM_OutputState, TIM_OutputState_Enable, TIM_TimeBaseInitTypeDef::TIM_Period, TIM_TimeBaseInitTypeDef::TIM_Prescaler, TIM_OCInitTypeDef::TIM_Pulse, and TIM_TimeBaseInit().

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 73 of file STM32F10x_StdPeriph_Examples/TIM/DMABurst/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 51 of file STM32F10x_StdPeriph_Examples/TIM/DMABurst/stm32f10x_it.c.

void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 130 of file STM32F10x_StdPeriph_Examples/TIM/DMABurst/stm32f10x_it.c.

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 112 of file STM32F10x_StdPeriph_Examples/TIM/DMABurst/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 139 of file STM32F10x_StdPeriph_Examples/TIM/DMABurst/stm32f10x_it.c.

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 99 of file STM32F10x_StdPeriph_Examples/TIM/DMABurst/stm32f10x_it.c.

Variable Documentation

DMA_InitTypeDef DMA_InitStructure

Definition at line 40 of file STM32F10x_StdPeriph_Examples/TIM/DMABurst/main.c.

GPIO_InitTypeDef GPIO_InitStructure

Definition at line 39 of file STM32F10x_StdPeriph_Examples/TIM/DMABurst/main.c.

uint16_t SRC_Buffer[6] = {0x0FFF, 0x0000, 0x0555}

Definition at line 43 of file STM32F10x_StdPeriph_Examples/TIM/DMABurst/main.c.

TIM_OCInitTypeDef TIM_OCInitStructure

Definition at line 42 of file STM32F10x_StdPeriph_Examples/TIM/DMABurst/main.c.

TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure

Definition at line 41 of file STM32F10x_StdPeriph_Examples/TIM/DMABurst/main.c.


STM32F10x Standard Peripherals Firmware Library: TIM_ExtTrigger_Synchro

Functions | Variables

TIM_ExtTrigger_Synchro

STM32F10x_StdPeriph_Examples

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | GPIO_Configuration (void)
Configure the GPIO Pins.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | RCC_Configuration (void)
Configures the different system clocks.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

TIM_ICInitTypeDef TIM_ICInitStructure
TIM_OCInitTypeDef TIM_OCInitStructure
TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure

Function Documentation

void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 84 of file STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 108 of file STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/stm32f10x_it.c.

void GPIO_Configuration ( void )

Configure the GPIO Pins.

Configures the different GPIO ports.

Parameters:
None
Return values:
None

Definition at line 222 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 60 of file STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 52 of file STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/main.c.

References ENABLE, GPIO_Configuration(), RCC_Configuration(), TIM1, TIM3, TIM4, TIM_ICInitTypeDef::TIM_Channel, TIM_Channel_2, TIM_TimeBaseInitTypeDef::TIM_ClockDivision, TIM_Cmd(), TIM_TimeBaseInitTypeDef::TIM_CounterMode, TIM_CounterMode_Up, TIM_CtrlPWMOutputs(), TIM_ICInitTypeDef::TIM_ICFilter, TIM_ICInit(), TIM_ICInitTypeDef::TIM_ICPolarity, TIM_ICPolarity_Rising, TIM_ICInitTypeDef::TIM_ICPrescaler, TIM_ICPSC_DIV1, TIM_ICInitTypeDef::TIM_ICSelection, TIM_ICSelection_DirectTI, TIM_MasterSlaveMode_Enable, TIM_OC1Init(), TIM_OCInitTypeDef::TIM_OCMode, TIM_OCMode_Toggle, TIM_OCInitTypeDef::TIM_OCPolarity, TIM_OCPolarity_High, TIM_OCInitTypeDef::TIM_OutputState, TIM_OutputState_Enable, TIM_TimeBaseInitTypeDef::TIM_Period, TIM_TimeBaseInitTypeDef::TIM_Prescaler, TIM_OCInitTypeDef::TIM_Pulse, TIM_SelectInputTrigger(), TIM_SelectMasterSlaveMode(), TIM_SelectOutputTrigger(), TIM_SelectSlaveMode(), TIM_SlaveMode_Gated, TIM_TimeBaseInit(), TIM_TRGOSource_Enable, TIM_TS_ITR0, TIM_TS_ITR2, and TIM_TS_TI2FP2.

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 72 of file STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 51 of file STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/stm32f10x_it.c.

void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 124 of file STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/stm32f10x_it.c.

void RCC_Configuration ( void )

Configures the different system clocks.

Parameters:
None
Return values:
None

Definition at line 203 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 116 of file STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 132 of file STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/stm32f10x_it.c.

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 96 of file STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/stm32f10x_it.c.

Variable Documentation

TIM_ICInitTypeDef TIM_ICInitStructure

Definition at line 38 of file STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/main.c.

TIM_OCInitTypeDef TIM_OCInitStructure

Definition at line 39 of file STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/main.c.

TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure

Definition at line 37 of file STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/main.c.


STM32F10x Standard Peripherals Firmware Library: TIM_Input_Capture

Functions | Variables

TIM_Input_Capture

STM32F10x_StdPeriph_Examples

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | GPIO_Configuration (void)
Configure the GPIOD Pins.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | NVIC_Configuration (void)
Configure the nested vectored interrupt controller.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | RCC_Configuration (void)
Configures the different system clocks.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | TIM3_IRQHandler (void)
This function handles TIM3 global interrupt request.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

__IO uint32_t | Capture = 0
__IO uint16_t | CaptureNumber = 0
__IO uint16_t | IC3ReadValue1 = 0
__IO uint16_t | IC3ReadValue2 = 0
__IO uint32_t | TIM3Freq = 0
TIM_ICInitTypeDef TIM_ICInitStructure

Function Documentation

void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 89 of file STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 113 of file STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_it.c.

void GPIO_Configuration ( void )

Configure the GPIOD Pins.

Configures the different GPIO ports.

Parameters:
None
Return values:
None

Definition at line 222 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 65 of file STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 51 of file STM32F10x_StdPeriph_Examples/TIM/InputCapture/main.c.

References ENABLE, GPIO_Configuration(), NVIC_Configuration(), RCC_Configuration(), TIM3, TIM_ICInitTypeDef::TIM_Channel, TIM_Channel_2, TIM_Cmd(), TIM_ICInitTypeDef::TIM_ICFilter, TIM_ICInit(), TIM_ICInitTypeDef::TIM_ICPolarity, TIM_ICPolarity_Rising, TIM_ICInitTypeDef::TIM_ICPrescaler, TIM_ICPSC_DIV1, TIM_ICInitTypeDef::TIM_ICSelection, TIM_ICSelection_DirectTI, TIM_IT_CC2, and TIM_ITConfig().

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 77 of file STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 56 of file STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_it.c.

void NVIC_Configuration ( void )

Configure the nested vectored interrupt controller.

Parameters:
None
Return values:
None
void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 129 of file STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_it.c.

void RCC_Configuration ( void )

Configures the different system clocks.

Parameters:
None
Return values:
None

Definition at line 203 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 121 of file STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 137 of file STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_it.c.

void TIM3_IRQHandler ( void )

This function handles TIM3 global interrupt request.

Parameters:
None
Return values:
None

Definition at line 148 of file STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_it.c.

References Capture, CaptureNumber, IC3ReadValue1, IC3ReadValue2, SET, SystemCoreClock, TIM3, TIM3Freq, TIM_ClearITPendingBit(), TIM_GetCapture2(), TIM_GetITStatus(), and TIM_IT_CC2.

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 101 of file STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_it.c.

Variable Documentation

__IO uint32_t Capture = 0

Definition at line 41 of file STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_it.c.

__IO uint16_t CaptureNumber = 0

Definition at line 40 of file STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_it.c.

Referenced by main(), TIM3_IRQHandler(), and TIM5_IRQHandler().

__IO uint16_t IC3ReadValue1 = 0

Definition at line 39 of file STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_it.c.

Referenced by TIM3_IRQHandler().

__IO uint16_t IC3ReadValue2 = 0

Definition at line 39 of file STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_it.c.

Referenced by TIM3_IRQHandler().

__IO uint32_t TIM3Freq = 0

Definition at line 42 of file STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_it.c.

Referenced by TIM3_IRQHandler().

TIM_ICInitTypeDef TIM_ICInitStructure

Definition at line 37 of file STM32F10x_StdPeriph_Examples/TIM/InputCapture/main.c.


STM32F10x Standard Peripherals Firmware Library: TIM_OCActive

Functions | Variables

TIM_OCActive

STM32F10x_StdPeriph_Examples

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | GPIO_Configuration (void)
Configure the TIM3 and the GPIOE Pins.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | RCC_Configuration (void)
Configures the different system clocks.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

uint16_t | CCR1_Val = 1000
uint16_t | CCR2_Val = 500
uint16_t | CCR3_Val = 250
uint16_t | CCR4_Val = 125
uint16_t | PrescalerValue = 0
TIM_OCInitTypeDef TIM_OCInitStructure
TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure

Function Documentation

void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 84 of file STM32F10x_StdPeriph_Examples/TIM/OCActive/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 108 of file STM32F10x_StdPeriph_Examples/TIM/OCActive/stm32f10x_it.c.

void GPIO_Configuration ( void )

Configure the TIM3 and the GPIOE Pins.

Configures the different GPIO ports.

Parameters:
None
Return values:
None

Definition at line 222 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 60 of file STM32F10x_StdPeriph_Examples/TIM/OCActive/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 56 of file STM32F10x_StdPeriph_Examples/TIM/OCActive/main.c.

References CCR1_Val, CCR2_Val, CCR3_Val, CCR4_Val, ENABLE, GPIO_Configuration(), GPIO_Pin_6, GPIO_Pin_7, GPIO_SetBits(), GPIOC, GPIOD, PrescalerValue, RCC_Configuration(), SystemCoreClock, TIM3, TIM_ARRPreloadConfig(), TIM_TimeBaseInitTypeDef::TIM_ClockDivision, TIM_Cmd(), TIM_TimeBaseInitTypeDef::TIM_CounterMode, TIM_CounterMode_Up, TIM_OC1Init(), TIM_OC1PreloadConfig(), TIM_OC2Init(), TIM_OC2PreloadConfig(), TIM_OC3Init(), TIM_OC3PreloadConfig(), TIM_OC4Init(), TIM_OC4PreloadConfig(), TIM_OCInitTypeDef::TIM_OCMode, TIM_OCMode_Active, TIM_OCInitTypeDef::TIM_OCPolarity, TIM_OCPolarity_High, TIM_OCPreload_Disable, TIM_OCInitTypeDef::TIM_OutputState, TIM_OutputState_Enable, TIM_TimeBaseInitTypeDef::TIM_Period, TIM_TimeBaseInitTypeDef::TIM_Prescaler, TIM_OCInitTypeDef::TIM_Pulse, and TIM_TimeBaseInit().

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 72 of file STM32F10x_StdPeriph_Examples/TIM/OCActive/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 51 of file STM32F10x_StdPeriph_Examples/TIM/OCActive/stm32f10x_it.c.

void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 124 of file STM32F10x_StdPeriph_Examples/TIM/OCActive/stm32f10x_it.c.

void RCC_Configuration ( void )

Configures the different system clocks.

Parameters:
None
Return values:
None

Definition at line 203 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 116 of file STM32F10x_StdPeriph_Examples/TIM/OCActive/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 132 of file STM32F10x_StdPeriph_Examples/TIM/OCActive/stm32f10x_it.c.

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 96 of file STM32F10x_StdPeriph_Examples/TIM/OCActive/stm32f10x_it.c.

Variable Documentation

uint16_t CCR1_Val = 1000

Definition at line 39 of file STM32F10x_StdPeriph_Examples/TIM/OCActive/main.c.

uint16_t CCR2_Val = 500

Definition at line 40 of file STM32F10x_StdPeriph_Examples/TIM/OCActive/main.c.

uint16_t CCR3_Val = 250

Definition at line 41 of file STM32F10x_StdPeriph_Examples/TIM/OCActive/main.c.

uint16_t CCR4_Val = 125

Definition at line 42 of file STM32F10x_StdPeriph_Examples/TIM/OCActive/main.c.

uint16_t PrescalerValue = 0

Definition at line 43 of file STM32F10x_StdPeriph_Examples/TIM/OCActive/main.c.

Referenced by main().

TIM_OCInitTypeDef TIM_OCInitStructure

Definition at line 38 of file STM32F10x_StdPeriph_Examples/TIM/OCActive/main.c.

TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure

Definition at line 37 of file STM32F10x_StdPeriph_Examples/TIM/OCActive/main.c.


STM32F10x Standard Peripherals Firmware Library: TIM_OCInactive

Functions | Variables

TIM_OCInactive

STM32F10x_StdPeriph_Examples

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | GPIO_Configuration (void)
Configure the GPIOD Pins.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | NVIC_Configuration (void)
Configure the nested vectored interrupt controller.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | RCC_Configuration (void)
Configures the different system clocks.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | TIM2_IRQHandler (void)
This function handles TIM2 global interrupt request.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

uint16_t | CCR1_Val = 1000
uint16_t | CCR2_Val = 500
uint16_t | CCR3_Val = 250
uint16_t | CCR4_Val = 125
uint16_t | PrescalerValue = 0
TIM_OCInitTypeDef TIM_OCInitStructure
TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure

Function Documentation

void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 84 of file STM32F10x_StdPeriph_Examples/TIM/OCInactive/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 108 of file STM32F10x_StdPeriph_Examples/TIM/OCInactive/stm32f10x_it.c.

void GPIO_Configuration ( void )

Configure the GPIOD Pins.

Configures the different GPIO ports.

Parameters:
None
Return values:
None

Definition at line 222 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 60 of file STM32F10x_StdPeriph_Examples/TIM/OCInactive/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 57 of file STM32F10x_StdPeriph_Examples/TIM/OCInactive/main.c.

References CCR1_Val, CCR2_Val, CCR3_Val, CCR4_Val, ENABLE, GPIO_Configuration(), GPIO_Pin_6, GPIO_Pin_7, GPIO_Pin_8, GPIO_Pin_9, GPIO_SetBits(), GPIOC, NVIC_Configuration(), PrescalerValue, RCC_Configuration(), SystemCoreClock, TIM2, TIM_ARRPreloadConfig(), TIM_TimeBaseInitTypeDef::TIM_ClockDivision, TIM_Cmd(), TIM_TimeBaseInitTypeDef::TIM_CounterMode, TIM_CounterMode_Up, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, TIM_IT_CC4, TIM_ITConfig(), TIM_OC1Init(), TIM_OC1PreloadConfig(), TIM_OC2Init(), TIM_OC2PreloadConfig(), TIM_OC3Init(), TIM_OC3PreloadConfig(), TIM_OC4Init(), TIM_OC4PreloadConfig(), TIM_OCInitTypeDef::TIM_OCMode, TIM_OCMode_Inactive, TIM_OCInitTypeDef::TIM_OCPolarity, TIM_OCPolarity_High, TIM_OCPreload_Disable, TIM_OCInitTypeDef::TIM_OutputState, TIM_OutputState_Enable, TIM_TimeBaseInitTypeDef::TIM_Period, TIM_TimeBaseInitTypeDef::TIM_Prescaler, TIM_OCInitTypeDef::TIM_Pulse, and TIM_TimeBaseInit().

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 72 of file STM32F10x_StdPeriph_Examples/TIM/OCInactive/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 51 of file STM32F10x_StdPeriph_Examples/TIM/OCInactive/stm32f10x_it.c.

void NVIC_Configuration ( void )

Configure the nested vectored interrupt controller.

Parameters:
None
Return values:
None
void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 124 of file STM32F10x_StdPeriph_Examples/TIM/OCInactive/stm32f10x_it.c.

void RCC_Configuration ( void )

Configures the different system clocks.

Parameters:
None
Return values:
None

Definition at line 203 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 116 of file STM32F10x_StdPeriph_Examples/TIM/OCInactive/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 132 of file STM32F10x_StdPeriph_Examples/TIM/OCInactive/stm32f10x_it.c.

void TIM2_IRQHandler ( void )

This function handles TIM2 global interrupt request.

Parameters:
None
Return values:
None

Definition at line 144 of file STM32F10x_StdPeriph_Examples/TIM/OCInactive/stm32f10x_it.c.

References GPIO_Pin_6, GPIO_Pin_7, GPIO_Pin_8, GPIO_Pin_9, GPIO_ResetBits(), GPIOC, RESET, TIM2, TIM_ClearITPendingBit(), TIM_GetITStatus(), TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, and TIM_IT_CC4.

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 96 of file STM32F10x_StdPeriph_Examples/TIM/OCInactive/stm32f10x_it.c.

Variable Documentation

uint16_t CCR1_Val = 1000

Definition at line 39 of file STM32F10x_StdPeriph_Examples/TIM/OCInactive/main.c.

uint16_t CCR2_Val = 500

Definition at line 40 of file STM32F10x_StdPeriph_Examples/TIM/OCInactive/main.c.

uint16_t CCR3_Val = 250

Definition at line 41 of file STM32F10x_StdPeriph_Examples/TIM/OCInactive/main.c.

uint16_t CCR4_Val = 125

Definition at line 42 of file STM32F10x_StdPeriph_Examples/TIM/OCInactive/main.c.

uint16_t PrescalerValue = 0

Definition at line 43 of file STM32F10x_StdPeriph_Examples/TIM/OCInactive/main.c.

TIM_OCInitTypeDef TIM_OCInitStructure

Definition at line 38 of file STM32F10x_StdPeriph_Examples/TIM/OCInactive/main.c.

TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure

Definition at line 37 of file STM32F10x_StdPeriph_Examples/TIM/OCInactive/main.c.


STM32F10x Standard Peripherals Firmware Library: TIM_OCToggle

Functions | Variables

TIM_OCToggle

STM32F10x_StdPeriph_Examples

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | GPIO_Configuration (void)
Configure the TIM3 Pins.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | NVIC_Configuration (void)
Configure the nested vectored interrupt controller.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | RCC_Configuration (void)
Configures the different system clocks.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | TIM3_IRQHandler (void)
This function handles TIM3 global interrupt request.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

uint16_t | capture = 0
__IO uint16_t | CCR1_Val = 32768
__IO uint16_t | CCR1_Val
__IO uint16_t | CCR2_Val = 16384
__IO uint16_t | CCR2_Val
__IO uint16_t | CCR3_Val
__IO uint16_t | CCR3_Val = 8192
__IO uint16_t | CCR4_Val
__IO uint16_t | CCR4_Val = 4096
uint16_t | PrescalerValue = 0
TIM_OCInitTypeDef TIM_OCInitStructure
TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure

Function Documentation

void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 90 of file STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 114 of file STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_it.c.

void GPIO_Configuration ( void )

Configure the TIM3 Pins.

Configures the different GPIO ports.

Parameters:
None
Return values:
None

Definition at line 222 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 66 of file STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 57 of file STM32F10x_StdPeriph_Examples/TIM/OCToggle/main.c.

References CCR1_Val, CCR2_Val, CCR3_Val, CCR4_Val, ENABLE, GPIO_Configuration(), NVIC_Configuration(), PrescalerValue, RCC_Configuration(), SystemCoreClock, TIM3, TIM_TimeBaseInitTypeDef::TIM_ClockDivision, TIM_Cmd(), TIM_TimeBaseInitTypeDef::TIM_CounterMode, TIM_CounterMode_Up, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, TIM_IT_CC4, TIM_ITConfig(), TIM_OC1Init(), TIM_OC1PreloadConfig(), TIM_OC2Init(), TIM_OC2PreloadConfig(), TIM_OC3Init(), TIM_OC3PreloadConfig(), TIM_OC4Init(), TIM_OC4PreloadConfig(), TIM_OCInitTypeDef::TIM_OCMode, TIM_OCMode_Toggle, TIM_OCInitTypeDef::TIM_OCPolarity, TIM_OCPolarity_Low, TIM_OCPreload_Disable, TIM_OCInitTypeDef::TIM_OutputState, TIM_OutputState_Enable, TIM_TimeBaseInitTypeDef::TIM_Period, TIM_TimeBaseInitTypeDef::TIM_Prescaler, TIM_OCInitTypeDef::TIM_Pulse, and TIM_TimeBaseInit().

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 78 of file STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 57 of file STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_it.c.

void NVIC_Configuration ( void )

Configure the nested vectored interrupt controller.

Parameters:
None
Return values:
None
void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 130 of file STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_it.c.

void RCC_Configuration ( void )

Configures the different system clocks.

Parameters:
None
Return values:
None

Definition at line 203 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 122 of file STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 138 of file STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_it.c.

void TIM3_IRQHandler ( void )

This function handles TIM3 global interrupt request.

Parameters:
None
Return values:
None

Definition at line 150 of file STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_it.c.

References capture, CCR1_Val, CCR2_Val, CCR3_Val, CCR4_Val, RESET, TIM3, TIM_ClearITPendingBit(), TIM_GetCapture1(), TIM_GetCapture2(), TIM_GetCapture3(), TIM_GetCapture4(), TIM_GetITStatus(), TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, TIM_IT_CC4, TIM_SetCompare1(), TIM_SetCompare2(), TIM_SetCompare3(), and TIM_SetCompare4().

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 102 of file STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_it.c.

Variable Documentation

uint16_t capture = 0

Definition at line 39 of file STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_it.c.

Referenced by TIM1_BRK_TIM9_IRQHandler(), TIM2_IRQHandler(), and TIM3_IRQHandler().

__IO uint16_t CCR1_Val = 32768

Definition at line 39 of file STM32F10x_StdPeriph_Examples/TIM/OCToggle/main.c.

__IO uint16_t CCR1_Val

Definition at line 40 of file STM32F10x_StdPeriph_Examples/TIM/6Steps/main.c.

__IO uint16_t CCR2_Val = 16384

Definition at line 40 of file STM32F10x_StdPeriph_Examples/TIM/OCToggle/main.c.

__IO uint16_t CCR2_Val

Definition at line 41 of file STM32F10x_StdPeriph_Examples/TIM/6Steps/main.c.

__IO uint16_t CCR3_Val

Definition at line 42 of file STM32F10x_StdPeriph_Examples/TIM/6Steps/main.c.

__IO uint16_t CCR3_Val = 8192

Definition at line 41 of file STM32F10x_StdPeriph_Examples/TIM/OCToggle/main.c.

__IO uint16_t CCR4_Val

Definition at line 43 of file STM32F10x_StdPeriph_Examples/TIM/6Steps/main.c.

__IO uint16_t CCR4_Val = 4096

Definition at line 42 of file STM32F10x_StdPeriph_Examples/TIM/OCToggle/main.c.

uint16_t PrescalerValue = 0

Definition at line 43 of file STM32F10x_StdPeriph_Examples/TIM/OCToggle/main.c.

TIM_OCInitTypeDef TIM_OCInitStructure

Definition at line 38 of file STM32F10x_StdPeriph_Examples/TIM/OCToggle/main.c.

TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure

Definition at line 37 of file STM32F10x_StdPeriph_Examples/TIM/OCToggle/main.c.


STM32F10x Standard Peripherals Firmware Library: TIM_OnePulse

Functions | Variables

TIM_OnePulse

STM32F10x_StdPeriph_Examples

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | GPIO_Configuration (void)
Configure the GPIOD Pins.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | RCC_Configuration (void)
Configures the different system clocks.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

uint16_t | PrescalerValue = 0
TIM_ICInitTypeDef TIM_ICInitStructure
TIM_OCInitTypeDef TIM_OCInitStructure
TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure

Function Documentation

void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 83 of file STM32F10x_StdPeriph_Examples/TIM/OnePulse/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 107 of file STM32F10x_StdPeriph_Examples/TIM/OnePulse/stm32f10x_it.c.

void GPIO_Configuration ( void )

Configure the GPIOD Pins.

Configures the different GPIO ports.

Parameters:
None
Return values:
None

Definition at line 222 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 59 of file STM32F10x_StdPeriph_Examples/TIM/OnePulse/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 53 of file STM32F10x_StdPeriph_Examples/TIM/OnePulse/main.c.

References GPIO_Configuration(), PrescalerValue, RCC_Configuration(), SystemCoreClock, TIM4, TIM_ICInitTypeDef::TIM_Channel, TIM_Channel_2, TIM_TimeBaseInitTypeDef::TIM_ClockDivision, TIM_TimeBaseInitTypeDef::TIM_CounterMode, TIM_CounterMode_Up, TIM_ICInitTypeDef::TIM_ICFilter, TIM_ICInit(), TIM_ICInitTypeDef::TIM_ICPolarity, TIM_ICPolarity_Rising, TIM_ICInitTypeDef::TIM_ICPrescaler, TIM_ICPSC_DIV1, TIM_ICInitTypeDef::TIM_ICSelection, TIM_ICSelection_DirectTI, TIM_ICStructInit(), TIM_OC1Init(), TIM_OCInitTypeDef::TIM_OCMode, TIM_OCMode_PWM2, TIM_OCInitTypeDef::TIM_OCPolarity, TIM_OCPolarity_High, TIM_OPMode_Single, TIM_OCInitTypeDef::TIM_OutputState, TIM_OutputState_Enable, TIM_TimeBaseInitTypeDef::TIM_Period, TIM_TimeBaseInitTypeDef::TIM_Prescaler, TIM_OCInitTypeDef::TIM_Pulse, TIM_SelectInputTrigger(), TIM_SelectOnePulseMode(), TIM_SelectSlaveMode(), TIM_SlaveMode_Trigger, TIM_TimeBaseInit(), and TIM_TS_TI2FP2.

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 71 of file STM32F10x_StdPeriph_Examples/TIM/OnePulse/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 51 of file STM32F10x_StdPeriph_Examples/TIM/OnePulse/stm32f10x_it.c.

void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 123 of file STM32F10x_StdPeriph_Examples/TIM/OnePulse/stm32f10x_it.c.

void RCC_Configuration ( void )

Configures the different system clocks.

Parameters:
None
Return values:
None

Definition at line 203 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 115 of file STM32F10x_StdPeriph_Examples/TIM/OnePulse/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 131 of file STM32F10x_StdPeriph_Examples/TIM/OnePulse/stm32f10x_it.c.

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 95 of file STM32F10x_StdPeriph_Examples/TIM/OnePulse/stm32f10x_it.c.

Variable Documentation

uint16_t PrescalerValue = 0

Definition at line 40 of file STM32F10x_StdPeriph_Examples/TIM/OnePulse/main.c.

TIM_ICInitTypeDef TIM_ICInitStructure

Definition at line 38 of file STM32F10x_StdPeriph_Examples/TIM/OnePulse/main.c.

TIM_OCInitTypeDef TIM_OCInitStructure

Definition at line 39 of file STM32F10x_StdPeriph_Examples/TIM/OnePulse/main.c.

TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure

Definition at line 37 of file STM32F10x_StdPeriph_Examples/TIM/OnePulse/main.c.


STM32F10x Standard Peripherals Firmware Library: TIM_Parallel_Synchro

Functions | Variables

TIM_Parallel_Synchro

STM32F10x_StdPeriph_Examples

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | GPIO_Configuration (void)
Configure the GPIO Pins.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | RCC_Configuration (void)
Configures the different system clocks.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

TIM_OCInitTypeDef TIM_OCInitStructure
TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure

Function Documentation

void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 84 of file STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 108 of file STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/stm32f10x_it.c.

void GPIO_Configuration ( void )

Configure the GPIO Pins.

Configures the different GPIO ports.

Parameters:
None
Return values:
None

Definition at line 222 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 60 of file STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 51 of file STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/main.c.

References ENABLE, GPIO_Configuration(), RCC_Configuration(), TIM2, TIM3, TIM4, TIM_TimeBaseInitTypeDef::TIM_ClockDivision, TIM_Cmd(), TIM_TimeBaseInitTypeDef::TIM_CounterMode, TIM_CounterMode_Up, TIM_MasterSlaveMode_Enable, TIM_OC1Init(), TIM_OCInitTypeDef::TIM_OCMode, TIM_OCMode_PWM1, TIM_OCInitTypeDef::TIM_OCPolarity, TIM_OCPolarity_High, TIM_OCInitTypeDef::TIM_OutputState, TIM_OutputState_Enable, TIM_TimeBaseInitTypeDef::TIM_Period, TIM_TimeBaseInitTypeDef::TIM_Prescaler, TIM_OCInitTypeDef::TIM_Pulse, TIM_SelectInputTrigger(), TIM_SelectMasterSlaveMode(), TIM_SelectOutputTrigger(), TIM_SelectSlaveMode(), TIM_SlaveMode_Gated, TIM_TimeBaseInit(), TIM_TRGOSource_Update, and TIM_TS_ITR1.

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 72 of file STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 51 of file STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/stm32f10x_it.c.

void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 124 of file STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/stm32f10x_it.c.

void RCC_Configuration ( void )

Configures the different system clocks.

Parameters:
None
Return values:
None

Definition at line 203 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 116 of file STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 132 of file STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/stm32f10x_it.c.

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 96 of file STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/stm32f10x_it.c.

Variable Documentation

TIM_OCInitTypeDef TIM_OCInitStructure

Definition at line 38 of file STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/main.c.

TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure

Definition at line 37 of file STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/main.c.


STM32F10x Standard Peripherals Firmware Library: TIM_PWM_Input

Functions | Variables

TIM_PWM_Input

STM32F10x_StdPeriph_Examples

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | GPIO_Configuration (void)
Configure the GPIO Pins.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | NVIC_Configuration (void)
Configure the nested vectored interrupt controller.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | RCC_Configuration (void)
Configures the different system clocks.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | TIM3_IRQHandler (void)
This function handles TIM3 global interrupt request.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

__IO uint16_t | DutyCycle = 0
__IO uint32_t | Frequency = 0
__IO uint16_t | IC2Value = 0
TIM_ICInitTypeDef TIM_ICInitStructure

Function Documentation

void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 88 of file STM32F10x_StdPeriph_Examples/TIM/PWM_Input/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 112 of file STM32F10x_StdPeriph_Examples/TIM/PWM_Input/stm32f10x_it.c.

void GPIO_Configuration ( void )

Configure the GPIO Pins.

Configures the different GPIO ports.

Parameters:
None
Return values:
None

Definition at line 222 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 64 of file STM32F10x_StdPeriph_Examples/TIM/PWM_Input/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 51 of file STM32F10x_StdPeriph_Examples/TIM/PWM_Input/main.c.

References ENABLE, GPIO_Configuration(), NVIC_Configuration(), RCC_Configuration(), TIM3, TIM_ICInitTypeDef::TIM_Channel, TIM_Channel_2, TIM_Cmd(), TIM_ICInitTypeDef::TIM_ICFilter, TIM_ICInitTypeDef::TIM_ICPolarity, TIM_ICPolarity_Rising, TIM_ICInitTypeDef::TIM_ICPrescaler, TIM_ICPSC_DIV1, TIM_ICInitTypeDef::TIM_ICSelection, TIM_ICSelection_DirectTI, TIM_IT_CC2, TIM_ITConfig(), TIM_MasterSlaveMode_Enable, TIM_PWMIConfig(), TIM_SelectInputTrigger(), TIM_SelectMasterSlaveMode(), TIM_SelectSlaveMode(), TIM_SlaveMode_Reset, and TIM_TS_TI2FP2.

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 76 of file STM32F10x_StdPeriph_Examples/TIM/PWM_Input/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 55 of file STM32F10x_StdPeriph_Examples/TIM/PWM_Input/stm32f10x_it.c.

void NVIC_Configuration ( void )

Configure the nested vectored interrupt controller.

Parameters:
None
Return values:
None
void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 128 of file STM32F10x_StdPeriph_Examples/TIM/PWM_Input/stm32f10x_it.c.

void RCC_Configuration ( void )

Configures the different system clocks.

Parameters:
None
Return values:
None

Definition at line 203 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 120 of file STM32F10x_StdPeriph_Examples/TIM/PWM_Input/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 136 of file STM32F10x_StdPeriph_Examples/TIM/PWM_Input/stm32f10x_it.c.

void TIM3_IRQHandler ( void )

This function handles TIM3 global interrupt request.

Parameters:
None
Return values:
None

Definition at line 148 of file STM32F10x_StdPeriph_Examples/TIM/PWM_Input/stm32f10x_it.c.

References DutyCycle, Frequency, IC2Value, LED2, STM_EVAL_LEDToggle(), SystemCoreClock, TIM3, TIM_ClearITPendingBit(), TIM_GetCapture1(), TIM_GetCapture2(), TIM_IT_CC2, and TIM_IT_Update.

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 100 of file STM32F10x_StdPeriph_Examples/TIM/PWM_Input/stm32f10x_it.c.

Variable Documentation

__IO uint16_t DutyCycle = 0

Definition at line 40 of file STM32F10x_StdPeriph_Examples/TIM/PWM_Input/stm32f10x_it.c.

Referenced by TIM3_IRQHandler().

__IO uint32_t Frequency = 0

Definition at line 41 of file STM32F10x_StdPeriph_Examples/TIM/PWM_Input/stm32f10x_it.c.

Referenced by TIM3_IRQHandler().

__IO uint16_t IC2Value = 0

Definition at line 39 of file STM32F10x_StdPeriph_Examples/TIM/PWM_Input/stm32f10x_it.c.

Referenced by TIM3_IRQHandler().

TIM_ICInitTypeDef TIM_ICInitStructure

Definition at line 37 of file STM32F10x_StdPeriph_Examples/TIM/PWM_Input/main.c.


STM32F10x Standard Peripherals Firmware Library: TIM_PWM_Output

Functions | Variables

TIM_PWM_Output

STM32F10x_StdPeriph_Examples

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | GPIO_Configuration (void)
Configure the TIM3 Ouput Channels.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | RCC_Configuration (void)
Configures the different system clocks.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

uint16_t | CCR1_Val = 333
uint16_t | CCR2_Val = 249
uint16_t | CCR3_Val = 166
uint16_t | CCR4_Val = 83
uint16_t | PrescalerValue = 0
TIM_OCInitTypeDef TIM_OCInitStructure
TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure

Function Documentation

void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 84 of file STM32F10x_StdPeriph_Examples/TIM/PWM_Output/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 108 of file STM32F10x_StdPeriph_Examples/TIM/PWM_Output/stm32f10x_it.c.

void GPIO_Configuration ( void )

Configure the TIM3 Ouput Channels.

Configures the different GPIO ports.

Parameters:
None
Return values:
None

Definition at line 222 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 60 of file STM32F10x_StdPeriph_Examples/TIM/PWM_Output/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 56 of file STM32F10x_StdPeriph_Examples/TIM/PWM_Output/main.c.

References CCR1_Val, CCR2_Val, CCR3_Val, CCR4_Val, ENABLE, GPIO_Configuration(), PrescalerValue, RCC_Configuration(), SystemCoreClock, TIM3, TIM_ARRPreloadConfig(), TIM_TimeBaseInitTypeDef::TIM_ClockDivision, TIM_Cmd(), TIM_TimeBaseInitTypeDef::TIM_CounterMode, TIM_CounterMode_Up, TIM_OC1Init(), TIM_OC1PreloadConfig(), TIM_OC2Init(), TIM_OC2PreloadConfig(), TIM_OC3Init(), TIM_OC3PreloadConfig(), TIM_OC4Init(), TIM_OC4PreloadConfig(), TIM_OCInitTypeDef::TIM_OCMode, TIM_OCMode_PWM1, TIM_OCInitTypeDef::TIM_OCPolarity, TIM_OCPolarity_High, TIM_OCPreload_Enable, TIM_OCInitTypeDef::TIM_OutputState, TIM_OutputState_Enable, TIM_TimeBaseInitTypeDef::TIM_Period, TIM_TimeBaseInitTypeDef::TIM_Prescaler, TIM_OCInitTypeDef::TIM_Pulse, and TIM_TimeBaseInit().

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 72 of file STM32F10x_StdPeriph_Examples/TIM/PWM_Output/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 51 of file STM32F10x_StdPeriph_Examples/TIM/PWM_Output/stm32f10x_it.c.

void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 124 of file STM32F10x_StdPeriph_Examples/TIM/PWM_Output/stm32f10x_it.c.

void RCC_Configuration ( void )

Configures the different system clocks.

Parameters:
None
Return values:
None

Definition at line 203 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 116 of file STM32F10x_StdPeriph_Examples/TIM/PWM_Output/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 132 of file STM32F10x_StdPeriph_Examples/TIM/PWM_Output/stm32f10x_it.c.

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 96 of file STM32F10x_StdPeriph_Examples/TIM/PWM_Output/stm32f10x_it.c.

Variable Documentation

uint16_t CCR1_Val = 333

Definition at line 39 of file STM32F10x_StdPeriph_Examples/TIM/PWM_Output/main.c.

uint16_t CCR2_Val = 249

Definition at line 40 of file STM32F10x_StdPeriph_Examples/TIM/PWM_Output/main.c.

uint16_t CCR3_Val = 166

Definition at line 41 of file STM32F10x_StdPeriph_Examples/TIM/PWM_Output/main.c.

uint16_t CCR4_Val = 83

Definition at line 42 of file STM32F10x_StdPeriph_Examples/TIM/PWM_Output/main.c.

uint16_t PrescalerValue = 0

Definition at line 43 of file STM32F10x_StdPeriph_Examples/TIM/PWM_Output/main.c.

TIM_OCInitTypeDef TIM_OCInitStructure

Definition at line 38 of file STM32F10x_StdPeriph_Examples/TIM/PWM_Output/main.c.

TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure

Definition at line 37 of file STM32F10x_StdPeriph_Examples/TIM/PWM_Output/main.c.


STM32F10x Standard Peripherals Firmware Library: TIM10_PWMOutput

Functions | Variables

TIM10_PWMOutput

STM32F10x_StdPeriph_Examples

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | GPIO_Configuration (void)
Configure TIM10 pin.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | RCC_Configuration (void)
Configures the different system clocks.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

uint16_t | CCR1Val = 249
uint16_t | PrescalerValue = 0
TIM_OCInitTypeDef TIM_OCInitStructure
TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure

Function Documentation

void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 84 of file STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 108 of file STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/stm32f10x_it.c.

void GPIO_Configuration ( void )

Configure TIM10 pin.

Configures the different GPIO ports.

Parameters:
None
Return values:
None

Definition at line 222 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 60 of file STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 53 of file STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/main.c.

References CCR1Val, ENABLE, GPIO_Configuration(), PrescalerValue, SystemCoreClock, TIM10, TIM_ARRPreloadConfig(), TIM_TimeBaseInitTypeDef::TIM_ClockDivision, TIM_Cmd(), TIM_TimeBaseInitTypeDef::TIM_CounterMode, TIM_CounterMode_Up, TIM_OC1Init(), TIM_OC1PreloadConfig(), TIM_OCInitTypeDef::TIM_OCMode, TIM_OCMode_PWM1, TIM_OCInitTypeDef::TIM_OCPolarity, TIM_OCPolarity_High, TIM_OCPreload_Enable, TIM_OCInitTypeDef::TIM_OutputState, TIM_OutputState_Enable, TIM_TimeBaseInitTypeDef::TIM_Period, TIM_TimeBaseInitTypeDef::TIM_Prescaler, TIM_OCInitTypeDef::TIM_Pulse, and TIM_TimeBaseInit().

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 72 of file STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 51 of file STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/stm32f10x_it.c.

void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 124 of file STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/stm32f10x_it.c.

void RCC_Configuration ( void )

Configures the different system clocks.

Parameters:
None
Return values:
None

Definition at line 203 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

References ENABLE, RCC_ADCCLKConfig(), RCC_AHBPeriph_DMA1, RCC_AHBPeriph_DMA2, RCC_AHBPeriphClockCmd(), RCC_APB2Periph_ADC1, RCC_APB2Periph_ADC2, RCC_APB2Periph_ADC3, RCC_APB2Periph_GPIOC, RCC_APB2PeriphClockCmd(), and RCC_PCLK2_Div4.

Referenced by main().

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 116 of file STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 132 of file STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/stm32f10x_it.c.

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 96 of file STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/stm32f10x_it.c.

Variable Documentation

uint16_t CCR1Val = 249

Definition at line 39 of file STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/main.c.

Referenced by main(), and TIM1_BRK_TIM9_IRQHandler().

uint16_t PrescalerValue = 0

Definition at line 40 of file STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/main.c.

TIM_OCInitTypeDef TIM_OCInitStructure

Definition at line 38 of file STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/main.c.

TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure

Definition at line 37 of file STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/main.c.


STM32F10x Standard Peripherals Firmware Library: TIM15_ComplementarySignals

Functions | Variables

TIM15_ComplementarySignals

STM32F10x_StdPeriph_Examples

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | GPIO_Configuration (void)
Configure the TIM1 Pins.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | RCC_Configuration (void)
Configures the different system clocks.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

uint16_t | CCR1_Val = 32767
TIM_BDTRInitTypeDef TIM_BDTRInitStructure
TIM_OCInitTypeDef TIM_OCInitStructure
TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure

Function Documentation

void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 83 of file STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 107 of file STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/stm32f10x_it.c.

void GPIO_Configuration ( void )

Configure the TIM1 Pins.

Configures the different GPIO ports.

Parameters:
None
Return values:
None

Definition at line 222 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 59 of file STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 53 of file STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/main.c.

References CCR1_Val, ENABLE, GPIO_Configuration(), RCC_Configuration(), TIM15, TIM_BDTRInitTypeDef::TIM_AutomaticOutput, TIM_AutomaticOutput_Enable, TIM_BDTRConfig(), TIM_BDTRInitTypeDef::TIM_Break, TIM_Break_Enable, TIM_BDTRInitTypeDef::TIM_BreakPolarity, TIM_BreakPolarity_High, TIM_TimeBaseInitTypeDef::TIM_ClockDivision, TIM_Cmd(), TIM_TimeBaseInitTypeDef::TIM_CounterMode, TIM_CounterMode_Up, TIM_CtrlPWMOutputs(), TIM_BDTRInitTypeDef::TIM_DeadTime, TIM_BDTRInitTypeDef::TIM_LOCKLevel, TIM_LOCKLevel_1, TIM_OC1Init(), TIM_OCInitTypeDef::TIM_OCIdleState, TIM_OCIdleState_Reset, TIM_OCIdleState_Set, TIM_OCInitTypeDef::TIM_OCMode, TIM_OCMode_PWM2, TIM_OCInitTypeDef::TIM_OCNIdleState, TIM_OCInitTypeDef::TIM_OCNPolarity, TIM_OCNPolarity_Low, TIM_OCInitTypeDef::TIM_OCPolarity, TIM_OCPolarity_Low, TIM_BDTRInitTypeDef::TIM_OSSIState, TIM_OSSIState_Enable, TIM_BDTRInitTypeDef::TIM_OSSRState, TIM_OSSRState_Enable, TIM_OCInitTypeDef::TIM_OutputNState, TIM_OutputNState_Enable, TIM_OCInitTypeDef::TIM_OutputState, TIM_OutputState_Enable, TIM_TimeBaseInitTypeDef::TIM_Period, TIM_TimeBaseInitTypeDef::TIM_Prescaler, TIM_OCInitTypeDef::TIM_Pulse, TIM_TimeBaseInitTypeDef::TIM_RepetitionCounter, and TIM_TimeBaseInit().

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 71 of file STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 51 of file STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/stm32f10x_it.c.

void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 123 of file STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/stm32f10x_it.c.

void RCC_Configuration ( void )

Configures the different system clocks.

Parameters:
None
Return values:
None

Definition at line 203 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 115 of file STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 131 of file STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/stm32f10x_it.c.

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 95 of file STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/stm32f10x_it.c.

Variable Documentation

uint16_t CCR1_Val = 32767

Definition at line 40 of file STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/main.c.

TIM_BDTRInitTypeDef TIM_BDTRInitStructure

Definition at line 39 of file STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/main.c.

TIM_OCInitTypeDef TIM_OCInitStructure

Definition at line 38 of file STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/main.c.

TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure

Definition at line 37 of file STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/main.c.


STM32F10x Standard Peripherals Firmware Library: TIM_TIM1_Synchro

Functions | Variables

TIM_TIM1_Synchro

STM32F10x_StdPeriph_Examples

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | GPIO_Configuration (void)
Configures TIM1, TIM3 and TIM4 Pins.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | RCC_Configuration (void)
Configures the different system clocks.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

TIM_BDTRInitTypeDef TIM_BDTRInitStructure
TIM_OCInitTypeDef TIM_OCInitStructure
TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure

Function Documentation

void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 84 of file STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 108 of file STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f10x_it.c.

void GPIO_Configuration ( void )

Configures TIM1, TIM3 and TIM4 Pins.

Configures the different GPIO ports.

Parameters:
None
Return values:
None

Definition at line 222 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 60 of file STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 52 of file STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/main.c.

References ENABLE, GPIO_Configuration(), RCC_Configuration(), TIM1, TIM3, TIM4, TIM_BDTRInitTypeDef::TIM_AutomaticOutput, TIM_AutomaticOutput_Disable, TIM_BDTRConfig(), TIM_BDTRInitTypeDef::TIM_Break, TIM_Break_Disable, TIM_BDTRInitTypeDef::TIM_BreakPolarity, TIM_BreakPolarity_High, TIM_TimeBaseInitTypeDef::TIM_ClockDivision, TIM_Cmd(), TIM_TimeBaseInitTypeDef::TIM_CounterMode, TIM_CounterMode_Up, TIM_CtrlPWMOutputs(), TIM_BDTRInitTypeDef::TIM_DeadTime, TIM_BDTRInitTypeDef::TIM_LOCKLevel, TIM_LOCKLevel_1, TIM_MasterSlaveMode_Enable, TIM_OC1Init(), TIM_OCInitTypeDef::TIM_OCIdleState, TIM_OCIdleState_Reset, TIM_OCIdleState_Set, TIM_OCInitTypeDef::TIM_OCMode, TIM_OCMode_PWM1, TIM_OCMode_PWM2, TIM_OCInitTypeDef::TIM_OCNIdleState, TIM_OCInitTypeDef::TIM_OCNPolarity, TIM_OCNPolarity_Low, TIM_OCInitTypeDef::TIM_OCPolarity, TIM_OCPolarity_Low, TIM_BDTRInitTypeDef::TIM_OSSIState, TIM_OSSIState_Enable, TIM_BDTRInitTypeDef::TIM_OSSRState, TIM_OSSRState_Enable, TIM_OCInitTypeDef::TIM_OutputNState, TIM_OutputNState_Enable, TIM_OCInitTypeDef::TIM_OutputState, TIM_OutputState_Enable, TIM_TimeBaseInitTypeDef::TIM_Period, TIM_TimeBaseInitTypeDef::TIM_Prescaler, TIM_OCInitTypeDef::TIM_Pulse, TIM_TimeBaseInitTypeDef::TIM_RepetitionCounter, TIM_SelectInputTrigger(), TIM_SelectMasterSlaveMode(), TIM_SelectOutputTrigger(), TIM_SelectSlaveMode(), TIM_SlaveMode_Gated, TIM_TimeBaseInit(), TIM_TRGOSource_Update, and TIM_TS_ITR0.

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 72 of file STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 51 of file STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f10x_it.c.

void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 124 of file STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f10x_it.c.

void RCC_Configuration ( void )

Configures the different system clocks.

Parameters:
None
Return values:
None

Definition at line 203 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 116 of file STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 132 of file STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f10x_it.c.

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 96 of file STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f10x_it.c.

Variable Documentation

TIM_BDTRInitTypeDef TIM_BDTRInitStructure

Definition at line 39 of file STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/main.c.

TIM_OCInitTypeDef TIM_OCInitStructure

Definition at line 38 of file STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/main.c.

TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure

Definition at line 37 of file STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/main.c.


STM32F10x Standard Peripherals Firmware Library: TIM9_OCToggle

Functions | Variables

TIM9_OCToggle

STM32F10x_StdPeriph_Examples

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | GPIO_Configuration (void)
Configure TIM9 pins.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | NVIC_Configuration (void)
Configure the nested vectored interrupt controller.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | TIM1_BRK_TIM9_IRQHandler (void)
This function handles TIM1 Break and TIM9 interrupts request.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

uint16_t | capture = 0
__IO uint16_t | CCR1Val = 32768
__IO uint16_t | CCR1Val
__IO uint16_t | CCR2Val = 16384
__IO uint16_t | CCR2Val
uint16_t | PrescalerValue = 0
TIM_OCInitTypeDef TIM_OCInitStructure
TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure

Function Documentation

void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 88 of file STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 112 of file STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_it.c.

void GPIO_Configuration ( void )

Configure TIM9 pins.

Configures the different GPIO ports.

Parameters:
None
Return values:
None

Definition at line 222 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 64 of file STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 54 of file STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/main.c.

References CCR1Val, CCR2Val, ENABLE, GPIO_Configuration(), NVIC_Configuration(), PrescalerValue, SystemCoreClock, TIM9, TIM_TimeBaseInitTypeDef::TIM_ClockDivision, TIM_Cmd(), TIM_TimeBaseInitTypeDef::TIM_CounterMode, TIM_CounterMode_Up, TIM_IT_CC1, TIM_IT_CC2, TIM_ITConfig(), TIM_OC1Init(), TIM_OC1PreloadConfig(), TIM_OC2Init(), TIM_OC2PreloadConfig(), TIM_OCInitTypeDef::TIM_OCMode, TIM_OCMode_Toggle, TIM_OCInitTypeDef::TIM_OCPolarity, TIM_OCPolarity_Low, TIM_OCPreload_Disable, TIM_OCInitTypeDef::TIM_OutputState, TIM_OutputState_Enable, TIM_TimeBaseInitTypeDef::TIM_Period, TIM_TimeBaseInitTypeDef::TIM_Prescaler, TIM_OCInitTypeDef::TIM_Pulse, and TIM_TimeBaseInit().

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 76 of file STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 55 of file STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_it.c.

void NVIC_Configuration ( void )

Configure the nested vectored interrupt controller.

Parameters:
None
Return values:
None
void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 128 of file STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_it.c.

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 120 of file STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 136 of file STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_it.c.

void TIM1_BRK_TIM9_IRQHandler ( void )

This function handles TIM1 Break and TIM9 interrupts request.

Parameters:
None
Return values:
None

Definition at line 148 of file STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_it.c.

References capture, CCR1Val, CCR2Val, RESET, TIM9, TIM_ClearITPendingBit(), TIM_GetCapture1(), TIM_GetCapture2(), TIM_GetITStatus(), TIM_IT_CC1, TIM_IT_CC2, TIM_SetCompare1(), and TIM_SetCompare2().

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 100 of file STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_it.c.

Variable Documentation

uint16_t capture = 0

Definition at line 39 of file STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_it.c.

__IO uint16_t CCR1Val = 32768

Definition at line 39 of file STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/main.c.

__IO uint16_t CCR1Val

Definition at line 39 of file STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/main.c.

Referenced by main(), and TIM1_BRK_TIM9_IRQHandler().

__IO uint16_t CCR2Val = 16384

Definition at line 40 of file STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/main.c.

Referenced by main(), and TIM1_BRK_TIM9_IRQHandler().

__IO uint16_t CCR2Val

Definition at line 40 of file STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/main.c.

Referenced by main(), and TIM1_BRK_TIM9_IRQHandler().

uint16_t PrescalerValue = 0

Definition at line 41 of file STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/main.c.

TIM_OCInitTypeDef TIM_OCInitStructure

Definition at line 38 of file STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/main.c.

TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure

Definition at line 37 of file STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/main.c.


STM32F10x Standard Peripherals Firmware Library: TIM_TimeBase

Functions | Variables

TIM_TimeBase

STM32F10x_StdPeriph_Examples

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | GPIO_Configuration (void)
Configure the GPIO Pins.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | NVIC_Configuration (void)
Configure the nested vectored interrupt controller.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | RCC_Configuration (void)
Configures the different system clocks.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | TIM2_IRQHandler (void)
This function handles TIM2 global interrupt request.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

uint16_t | capture = 0
__IO uint16_t | CCR1_Val = 40961
__IO uint16_t | CCR1_Val
__IO uint16_t | CCR2_Val = 27309
__IO uint16_t | CCR2_Val
__IO uint16_t | CCR3_Val
__IO uint16_t | CCR3_Val = 13654
__IO uint16_t | CCR4_Val
__IO uint16_t | CCR4_Val = 6826
uint16_t | PrescalerValue = 0
TIM_OCInitTypeDef TIM_OCInitStructure
TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure

Function Documentation

void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 90 of file STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 114 of file STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_it.c.

void GPIO_Configuration ( void )

Configure the GPIO Pins.

Configures the different GPIO ports.

Parameters:
None
Return values:
None

Definition at line 222 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 66 of file STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 57 of file STM32F10x_StdPeriph_Examples/TIM/TimeBase/main.c.

References CCR1_Val, CCR2_Val, CCR3_Val, CCR4_Val, ENABLE, GPIO_Configuration(), NVIC_Configuration(), PrescalerValue, RCC_Configuration(), SystemCoreClock, TIM2, TIM_TimeBaseInitTypeDef::TIM_ClockDivision, TIM_Cmd(), TIM_TimeBaseInitTypeDef::TIM_CounterMode, TIM_CounterMode_Up, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, TIM_IT_CC4, TIM_ITConfig(), TIM_OC1Init(), TIM_OC1PreloadConfig(), TIM_OC2Init(), TIM_OC2PreloadConfig(), TIM_OC3Init(), TIM_OC3PreloadConfig(), TIM_OC4Init(), TIM_OC4PreloadConfig(), TIM_OCInitTypeDef::TIM_OCMode, TIM_OCMode_Timing, TIM_OCInitTypeDef::TIM_OCPolarity, TIM_OCPolarity_High, TIM_OCPreload_Disable, TIM_OCInitTypeDef::TIM_OutputState, TIM_OutputState_Enable, TIM_TimeBaseInitTypeDef::TIM_Period, TIM_TimeBaseInitTypeDef::TIM_Prescaler, TIM_PrescalerConfig(), TIM_PSCReloadMode_Immediate, TIM_OCInitTypeDef::TIM_Pulse, and TIM_TimeBaseInit().

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 78 of file STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 57 of file STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_it.c.

void NVIC_Configuration ( void )

Configure the nested vectored interrupt controller.

Parameters:
None
Return values:
None
void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 130 of file STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_it.c.

void RCC_Configuration ( void )

Configures the different system clocks.

Parameters:
None
Return values:
None

Definition at line 203 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 122 of file STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 138 of file STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_it.c.

void TIM2_IRQHandler ( void )

This function handles TIM2 global interrupt request.

Parameters:
None
Return values:
None

Definition at line 150 of file STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_it.c.

References capture, CCR1_Val, CCR2_Val, CCR3_Val, CCR4_Val, GPIO_Pin_6, GPIO_Pin_7, GPIO_Pin_8, GPIO_Pin_9, GPIO_ReadOutputDataBit(), GPIO_WriteBit(), GPIOC, LED1, RESET, STM_EVAL_LEDToggle(), TIM2, TIM_ClearITPendingBit(), TIM_GetCapture1(), TIM_GetCapture2(), TIM_GetCapture3(), TIM_GetCapture4(), TIM_GetITStatus(), TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, TIM_IT_CC4, TIM_IT_Update, TIM_SetCompare1(), TIM_SetCompare2(), TIM_SetCompare3(), and TIM_SetCompare4().

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 102 of file STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_it.c.

Variable Documentation

uint16_t capture = 0

Definition at line 39 of file STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_it.c.

__IO uint16_t CCR1_Val = 40961

Definition at line 39 of file STM32F10x_StdPeriph_Examples/TIM/TimeBase/main.c.

__IO uint16_t CCR1_Val

Definition at line 40 of file STM32F10x_StdPeriph_Examples/TIM/6Steps/main.c.

Referenced by main(), TIM2_IRQHandler(), and TIM3_IRQHandler().

__IO uint16_t CCR2_Val = 27309

Definition at line 40 of file STM32F10x_StdPeriph_Examples/TIM/TimeBase/main.c.

__IO uint16_t CCR2_Val

Definition at line 41 of file STM32F10x_StdPeriph_Examples/TIM/6Steps/main.c.

Referenced by main(), TIM2_IRQHandler(), and TIM3_IRQHandler().

__IO uint16_t CCR3_Val

Definition at line 42 of file STM32F10x_StdPeriph_Examples/TIM/6Steps/main.c.

Referenced by main(), TIM2_IRQHandler(), and TIM3_IRQHandler().

__IO uint16_t CCR3_Val = 13654

Definition at line 41 of file STM32F10x_StdPeriph_Examples/TIM/TimeBase/main.c.

__IO uint16_t CCR4_Val

Definition at line 43 of file STM32F10x_StdPeriph_Examples/TIM/6Steps/main.c.

Referenced by main(), TIM2_IRQHandler(), and TIM3_IRQHandler().

__IO uint16_t CCR4_Val = 6826

Definition at line 42 of file STM32F10x_StdPeriph_Examples/TIM/TimeBase/main.c.

uint16_t PrescalerValue = 0

Definition at line 43 of file STM32F10x_StdPeriph_Examples/TIM/TimeBase/main.c.

TIM_OCInitTypeDef TIM_OCInitStructure

Definition at line 38 of file STM32F10x_StdPeriph_Examples/TIM/TimeBase/main.c.

TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure

Definition at line 37 of file STM32F10x_StdPeriph_Examples/TIM/TimeBase/main.c.


STM32F10x Standard Peripherals Firmware Library: USART_DMA_Interrupt

Defines | Enumerations | Functions | Variables

USART_DMA_Interrupt

STM32F10x_StdPeriph_Examples

Defines

#define | countof(a) (sizeof(a) / sizeof(*(a)))
#define | TxBufferSize1 (countof(TxBuffer1) - 1)
#define | TxBufferSize2 (countof(TxBuffer2) - 1)

Enumerations

enum TestStatus {
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED
}

Functions

TestStatus | Buffercmp (uint8_t *pBuffer1, uint8_t *pBuffer2, uint16_t BufferLength)
Compares two buffers.
void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | DMA_Configuration (void)
Configures the DMA.
void | GPIO_Configuration (void)
Configures the different GPIO ports.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | NVIC_Configuration (void)
Configures the nested vectored interrupt controller.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | RCC_Configuration (void)
Configures the different system clocks.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.
void | USART2_IRQHandler (void)
This function handles USART2 global interrupt request.
void | USART3_IRQHandler (void)
This function handles USART3 global interrupt request.

Variables

uint32_t | index = 0
uint8_t | NbrOfDataToRead = TxBufferSize1
uint8_t | NbrOfDataToRead
uint8_t | RxBuffer1 [TxBufferSize2]
uint8_t | RxBuffer2 [TxBufferSize1]
uint8_t | RxBuffer2 []
uint8_t | RxCounter = 0
volatile TestStatus | TransferStatus1 = FAILED
volatile TestStatus | TransferStatus2 = FAILED
uint8_t | TxBuffer1 [] = "USART DMA Interrupt: USARTy -> USARTz using DMA Tx and Rx Flag"
uint8_t | TxBuffer2 [] = "USART DMA Interrupt: USARTz -> USARTy using DMA Tx and Rx Interrupt"
USART_InitTypeDef USART_InitStructure

Define Documentation

#define countof ( a ) (sizeof(a) / sizeof(*(a)))

Definition at line 42 of file STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/main.c.

#define TxBufferSize1 (countof(TxBuffer1) - 1)

Definition at line 38 of file STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/main.c.

Referenced by main().

#define TxBufferSize2 (countof(TxBuffer2) - 1)

Definition at line 39 of file STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/main.c.

Referenced by main().

Enumeration Type Documentation

enum TestStatus
Enumerator:
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED

Definition at line 35 of file STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/main.c.

Function Documentation

TestStatus Buffercmp | ( | uint8_t * | pBuffer1,
 |  | uint8_t * | pBuffer2,
 |  | uint16_t | BufferLength
 | ) |  |

Compares two buffers.

Parameters:
pBuffer1,pBuffer2,: buffers to be compared.
BufferLength,: buffer's length
Return values:
PASSED,: pBuffer1 identical to pBuffer2 FAILED: pBuffer1 differs from pBuffer2
void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 90 of file STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 125 of file STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_it.c.

void DMA_Configuration ( void )

Configures the DMA.

Parameters:
None
Return values:
None
void GPIO_Configuration ( void )

Configures the different GPIO ports.

Parameters:
None
Return values:
None

Definition at line 222 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 64 of file STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 68 of file STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/main.c.

References Buffercmp(), DMA_Cmd(), DMA_Configuration(), DMA_GetFlagStatus(), ENABLE, GPIO_Configuration(), index, NVIC_Configuration(), RCC_Configuration(), RESET, RxBuffer1, RxBuffer2, TransferStatus1, TransferStatus2, TxBuffer1, TxBuffer2, TxBufferSize1, TxBufferSize2, USART_InitTypeDef::USART_BaudRate, USART_Cmd(), USART_DMACmd(), USART_DMAReq_Tx, USART_FLAG_RXNE, USART_GetFlagStatus(), USART_InitTypeDef::USART_HardwareFlowControl, USART_HardwareFlowControl_None, USART_Init(), USART_IT_RXNE, USART_ITConfig(), USART_InitTypeDef::USART_Mode, USART_Mode_Rx, USART_Mode_Tx, USART_InitTypeDef::USART_Parity, USART_Parity_No, USART_ReceiveData(), USART_InitTypeDef::USART_StopBits, USART_StopBits_1, USART_InitTypeDef::USART_WordLength, USART_WordLength_8b, USARTy, and USARTz.

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 77 of file STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 55 of file STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_it.c.

void NVIC_Configuration ( void )

Configures the nested vectored interrupt controller.

Parameters:
None
Return values:
None
void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 134 of file STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_it.c.

void RCC_Configuration ( void )

Configures the different system clocks.

Parameters:
None
Return values:
None

Definition at line 203 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 116 of file STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 143 of file STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_it.c.

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 103 of file STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_it.c.

void USART2_IRQHandler ( void )

This function handles USART2 global interrupt request.

Parameters:
None
Return values:
None

Definition at line 156 of file STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_it.c.

References DISABLE, NbrOfDataToRead, RESET, RxBuffer2, RxCounter, USART2, USART_GetITStatus(), USART_IT_RXNE, USART_ITConfig(), and USART_ReceiveData().

void USART3_IRQHandler ( void )

This function handles USART3 global interrupt request.

Parameters:
None
Return values:
None

Definition at line 176 of file STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_it.c.

References DISABLE, NbrOfDataToRead, RESET, RxBuffer2, RxCounter, USART3, USART_GetITStatus(), USART_IT_RXNE, USART_ITConfig(), and USART_ReceiveData().

Variable Documentation

uint32_t index = 0

Definition at line 51 of file STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/main.c.

uint8_t NbrOfDataToRead = TxBufferSize1

Definition at line 50 of file STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/main.c.

Referenced by USART2_IRQHandler(), USART3_IRQHandler(), and USARTx_IRQHandler().

uint8_t NbrOfDataToRead

Definition at line 50 of file STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/main.c.

Referenced by USART2_IRQHandler(), USART3_IRQHandler(), and USARTx_IRQHandler().

uint8_t RxBuffer1[TxBufferSize2]

Definition at line 48 of file STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/main.c.

Referenced by main(), and USARTy_IRQHandler().

uint8_t RxBuffer2[TxBufferSize1]

Definition at line 49 of file STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/main.c.

Referenced by main(), USART2_IRQHandler(), USART3_IRQHandler(), and USARTz_IRQHandler().

uint8_t RxBuffer2[]

Definition at line 49 of file STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/main.c.

uint8_t RxCounter = 0

Definition at line 39 of file STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_it.c.

Referenced by HDMI_CEC_ProcessIRQSrc(), main(), USART2_IRQHandler(), USART3_IRQHandler(), and USARTx_IRQHandler().

volatile TestStatus TransferStatus1 = FAILED

Definition at line 52 of file STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/main.c.

volatile TestStatus TransferStatus2 = FAILED

Definition at line 52 of file STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/main.c.

uint8_t TxBuffer1[] = "USART DMA Interrupt: USARTy -> USARTz using DMA Tx and Rx Flag"

Definition at line 46 of file STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/main.c.

Referenced by main(), and USARTy_IRQHandler().

uint8_t TxBuffer2[] = "USART DMA Interrupt: USARTz -> USARTy using DMA Tx and Rx Interrupt"

Definition at line 47 of file STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/main.c.

Referenced by main(), and USARTz_IRQHandler().

USART_InitTypeDef USART_InitStructure

Definition at line 45 of file STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/main.c.


STM32F10x Standard Peripherals Firmware Library: USART_DMA_Polling

Defines | Enumerations | Functions | Variables

USART_DMA_Polling

STM32F10x_StdPeriph_Examples

Defines

#define | countof(a) (sizeof(a) / sizeof(*(a)))
#define | TxBufferSize1 (countof(TxBuffer1) - 1)
#define | TxBufferSize2 (countof(TxBuffer2) - 1)

Enumerations

enum TestStatus {
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED
}

Functions

TestStatus | Buffercmp (uint8_t *pBuffer1, uint8_t *pBuffer2, uint16_t BufferLength)
Compares two buffers.
void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | DMA_Configuration (void)
Configures the DMA.
void | GPIO_Configuration (void)
Configures the different GPIO ports.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | RCC_Configuration (void)
Configures the different system clocks.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

uint8_t | RxBuffer1 [TxBufferSize2]
uint8_t | RxBuffer2 [TxBufferSize1]
volatile TestStatus | TransferStatus1 = FAILED
volatile TestStatus | TransferStatus2 = FAILED
uint8_t | TxBuffer1 [] = "USART DMA Polling: USARTy -> USARTz using DMA"
uint8_t | TxBuffer2 [] = "USART DMA Polling: USARTz -> USARTy using DMA"
USART_InitTypeDef USART_InitStructure

Define Documentation

#define countof ( a ) (sizeof(a) / sizeof(*(a)))

Definition at line 42 of file STM32F10x_StdPeriph_Examples/USART/DMA_Polling/main.c.

#define TxBufferSize1 (countof(TxBuffer1) - 1)

Definition at line 38 of file STM32F10x_StdPeriph_Examples/USART/DMA_Polling/main.c.

Referenced by main().

#define TxBufferSize2 (countof(TxBuffer2) - 1)

Definition at line 39 of file STM32F10x_StdPeriph_Examples/USART/DMA_Polling/main.c.

Referenced by main().

Enumeration Type Documentation

enum TestStatus
Enumerator:
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED

Definition at line 35 of file STM32F10x_StdPeriph_Examples/USART/DMA_Polling/main.c.

Function Documentation

TestStatus Buffercmp | ( | uint8_t * | pBuffer1,
 |  | uint8_t * | pBuffer2,
 |  | uint16_t | BufferLength
 | ) |  |

Compares two buffers.

Parameters:
pBuffer1,pBuffer2,: buffers to be compared.
BufferLength,: buffer's length
Return values:
PASSED,: pBuffer1 identical to pBuffer2 FAILED: pBuffer1 differs from pBuffer2
void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 86 of file STM32F10x_StdPeriph_Examples/USART/DMA_Polling/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 121 of file STM32F10x_StdPeriph_Examples/USART/DMA_Polling/stm32f10x_it.c.

void DMA_Configuration ( void )

Configures the DMA.

Parameters:
None
Return values:
None
void GPIO_Configuration ( void )

Configures the different GPIO ports.

Parameters:
None
Return values:
None

Definition at line 222 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 60 of file STM32F10x_StdPeriph_Examples/USART/DMA_Polling/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 66 of file STM32F10x_StdPeriph_Examples/USART/DMA_Polling/main.c.

References Buffercmp(), DMA_Cmd(), DMA_Configuration(), DMA_GetFlagStatus(), ENABLE, GPIO_Configuration(), RCC_Configuration(), RESET, RxBuffer1, RxBuffer2, TransferStatus1, TransferStatus2, TxBuffer1, TxBuffer2, TxBufferSize1, TxBufferSize2, USART_InitTypeDef::USART_BaudRate, USART_Cmd(), USART_DMACmd(), USART_DMAReq_Rx, USART_DMAReq_Tx, USART_InitTypeDef::USART_HardwareFlowControl, USART_HardwareFlowControl_None, USART_Init(), USART_InitTypeDef::USART_Mode, USART_Mode_Rx, USART_Mode_Tx, USART_InitTypeDef::USART_Parity, USART_Parity_No, USART_InitTypeDef::USART_StopBits, USART_StopBits_1, USART_InitTypeDef::USART_WordLength, USART_WordLength_8b, USARTy, and USARTz.

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 73 of file STM32F10x_StdPeriph_Examples/USART/DMA_Polling/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 51 of file STM32F10x_StdPeriph_Examples/USART/DMA_Polling/stm32f10x_it.c.

void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 130 of file STM32F10x_StdPeriph_Examples/USART/DMA_Polling/stm32f10x_it.c.

void RCC_Configuration ( void )

Configures the different system clocks.

Parameters:
None
Return values:
None

Definition at line 203 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 112 of file STM32F10x_StdPeriph_Examples/USART/DMA_Polling/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 139 of file STM32F10x_StdPeriph_Examples/USART/DMA_Polling/stm32f10x_it.c.

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 99 of file STM32F10x_StdPeriph_Examples/USART/DMA_Polling/stm32f10x_it.c.

Variable Documentation

uint8_t RxBuffer1[TxBufferSize2]

Definition at line 48 of file STM32F10x_StdPeriph_Examples/USART/DMA_Polling/main.c.

uint8_t RxBuffer2[TxBufferSize1]

Definition at line 49 of file STM32F10x_StdPeriph_Examples/USART/DMA_Polling/main.c.

volatile TestStatus TransferStatus1 = FAILED

Definition at line 50 of file STM32F10x_StdPeriph_Examples/USART/DMA_Polling/main.c.

volatile TestStatus TransferStatus2 = FAILED

Definition at line 51 of file STM32F10x_StdPeriph_Examples/USART/DMA_Polling/main.c.

uint8_t TxBuffer1[] = "USART DMA Polling: USARTy -> USARTz using DMA"

Definition at line 46 of file STM32F10x_StdPeriph_Examples/USART/DMA_Polling/main.c.

uint8_t TxBuffer2[] = "USART DMA Polling: USARTz -> USARTy using DMA"

Definition at line 47 of file STM32F10x_StdPeriph_Examples/USART/DMA_Polling/main.c.

USART_InitTypeDef USART_InitStructure

Definition at line 45 of file STM32F10x_StdPeriph_Examples/USART/DMA_Polling/main.c.


STM32F10x Standard Peripherals Firmware Library: USART_HalfDuplex

Defines | Enumerations | Functions | Variables

USART_HalfDuplex

STM32F10x_StdPeriph_Examples

Defines

#define | countof(a) (sizeof(a) / sizeof(*(a)))
#define | TxBufferSize1 (countof(TxBuffer1) - 1)
#define | TxBufferSize2 (countof(TxBuffer2) - 1)

Enumerations

enum TestStatus {
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED
}

Functions

TestStatus | Buffercmp (uint8_t *pBuffer1, uint8_t *pBuffer2, uint16_t BufferLength)
Compares two buffers.
void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | GPIO_Configuration (void)
Configures the different GPIO ports.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | RCC_Configuration (void)
Configures the different system clocks.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

uint32_t | NbrOfDataToRead1 = TxBufferSize2
uint32_t | NbrOfDataToRead2 = TxBufferSize1
uint8_t | RxBuffer1 [TxBufferSize2]
uint8_t | RxBuffer2 [TxBufferSize1]
uint8_t | RxCounter1 = 0
uint8_t | RxCounter2 = 0
volatile TestStatus | TransferStatus1 = FAILED
volatile TestStatus | TransferStatus2 = FAILED
uint8_t | TxBuffer1 [] = "USART Half Duplex: USARTy -> USARTz using HalfDuplex mode"
uint8_t | TxBuffer2 [] = "USART Half Duplex: USARTz -> USARTy using HalfDuplex mode"
uint8_t | TxCounter1 = 0
uint8_t | TxCounter2 = 0
USART_InitTypeDef USART_InitStructure

Define Documentation

#define countof ( a ) (sizeof(a) / sizeof(*(a)))

Definition at line 42 of file STM32F10x_StdPeriph_Examples/USART/HalfDuplex/main.c.

#define TxBufferSize1 (countof(TxBuffer1) - 1)

Definition at line 38 of file STM32F10x_StdPeriph_Examples/USART/HalfDuplex/main.c.

Referenced by main().

#define TxBufferSize2 (countof(TxBuffer2) - 1)

Definition at line 39 of file STM32F10x_StdPeriph_Examples/USART/HalfDuplex/main.c.

Referenced by main().

Enumeration Type Documentation

enum TestStatus
Enumerator:
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED

Definition at line 35 of file STM32F10x_StdPeriph_Examples/USART/HalfDuplex/main.c.

Function Documentation

TestStatus Buffercmp | ( | uint8_t * | pBuffer1,
 |  | uint8_t * | pBuffer2,
 |  | uint16_t | BufferLength
 | ) |  |

Compares two buffers.

Parameters:
pBuffer1,pBuffer2,: buffers to be compared.
BufferLength,: buffer's length
Return values:
PASSED,: pBuffer1 identical to pBuffer2 FAILED: pBuffer1 differs from pBuffer2
void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 86 of file STM32F10x_StdPeriph_Examples/USART/HalfDuplex/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 121 of file STM32F10x_StdPeriph_Examples/USART/HalfDuplex/stm32f10x_it.c.

void GPIO_Configuration ( void )

Configures the different GPIO ports.

Parameters:
None
Return values:
None

Definition at line 222 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 60 of file STM32F10x_StdPeriph_Examples/USART/HalfDuplex/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 68 of file STM32F10x_StdPeriph_Examples/USART/HalfDuplex/main.c.

References Buffercmp(), ENABLE, GPIO_Configuration(), NbrOfDataToRead1, NbrOfDataToRead2, RCC_Configuration(), RESET, RxBuffer1, RxBuffer2, RxCounter1, RxCounter2, TransferStatus1, TransferStatus2, TxBuffer1, TxBuffer2, TxBufferSize1, TxBufferSize2, TxCounter1, TxCounter2, USART_InitTypeDef::USART_BaudRate, USART_Cmd(), USART_FLAG_RXNE, USART_FLAG_TXE, USART_GetFlagStatus(), USART_HalfDuplexCmd(), USART_InitTypeDef::USART_HardwareFlowControl, USART_HardwareFlowControl_None, USART_Init(), USART_InitTypeDef::USART_Mode, USART_Mode_Rx, USART_Mode_Tx, USART_InitTypeDef::USART_Parity, USART_Parity_No, USART_ReceiveData(), USART_SendData(), USART_InitTypeDef::USART_StopBits, USART_StopBits_1, USART_InitTypeDef::USART_WordLength, USART_WordLength_8b, USARTy, and USARTz.

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 73 of file STM32F10x_StdPeriph_Examples/USART/HalfDuplex/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 51 of file STM32F10x_StdPeriph_Examples/USART/HalfDuplex/stm32f10x_it.c.

void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 130 of file STM32F10x_StdPeriph_Examples/USART/HalfDuplex/stm32f10x_it.c.

void RCC_Configuration ( void )

Configures the different system clocks.

Parameters:
None
Return values:
None

Definition at line 203 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 112 of file STM32F10x_StdPeriph_Examples/USART/HalfDuplex/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 139 of file STM32F10x_StdPeriph_Examples/USART/HalfDuplex/stm32f10x_it.c.

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 99 of file STM32F10x_StdPeriph_Examples/USART/HalfDuplex/stm32f10x_it.c.

Variable Documentation

uint32_t NbrOfDataToRead1 = TxBufferSize2

Definition at line 50 of file STM32F10x_StdPeriph_Examples/USART/HalfDuplex/main.c.

Referenced by main(), USARTy_IRQHandler(), and USARTz_IRQHandler().

uint32_t NbrOfDataToRead2 = TxBufferSize1

Definition at line 51 of file STM32F10x_StdPeriph_Examples/USART/HalfDuplex/main.c.

Referenced by main().

uint8_t RxBuffer1[TxBufferSize2]

Definition at line 48 of file STM32F10x_StdPeriph_Examples/USART/HalfDuplex/main.c.

uint8_t RxBuffer2[TxBufferSize1]

Definition at line 49 of file STM32F10x_StdPeriph_Examples/USART/HalfDuplex/main.c.

uint8_t RxCounter1 = 0

Definition at line 52 of file STM32F10x_StdPeriph_Examples/USART/HalfDuplex/main.c.

Referenced by main(), and USARTy_IRQHandler().

uint8_t RxCounter2 = 0

Definition at line 53 of file STM32F10x_StdPeriph_Examples/USART/HalfDuplex/main.c.

Referenced by main(), and USARTz_IRQHandler().

volatile TestStatus TransferStatus1 = FAILED

Definition at line 54 of file STM32F10x_StdPeriph_Examples/USART/HalfDuplex/main.c.

volatile TestStatus TransferStatus2 = FAILED

Definition at line 54 of file STM32F10x_StdPeriph_Examples/USART/HalfDuplex/main.c.

uint8_t TxBuffer1[] = "USART Half Duplex: USARTy -> USARTz using HalfDuplex mode"

Definition at line 46 of file STM32F10x_StdPeriph_Examples/USART/HalfDuplex/main.c.

uint8_t TxBuffer2[] = "USART Half Duplex: USARTz -> USARTy using HalfDuplex mode"

Definition at line 47 of file STM32F10x_StdPeriph_Examples/USART/HalfDuplex/main.c.

uint8_t TxCounter1 = 0

Definition at line 52 of file STM32F10x_StdPeriph_Examples/USART/HalfDuplex/main.c.

Referenced by main(), and USARTy_IRQHandler().

uint8_t TxCounter2 = 0

Definition at line 53 of file STM32F10x_StdPeriph_Examples/USART/HalfDuplex/main.c.

Referenced by main(), and USARTz_IRQHandler().

USART_InitTypeDef USART_InitStructure

Definition at line 45 of file STM32F10x_StdPeriph_Examples/USART/HalfDuplex/main.c.


STM32F10x Standard Peripherals Firmware Library: USART_HyperTerminal_HwFlowControl

Defines | Functions | Variables

USART_HyperTerminal_HwFlowControl

STM32F10x_StdPeriph_Examples

Defines

#define | countof(a) (sizeof(a) / sizeof(*(a)))
#define | RxBufferSize 0xFF
#define | TxBufferSize (countof(TxBuffer) - 1)

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | GPIO_Configuration (void)
Configures the different GPIO ports.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | RCC_Configuration (void)
Configures the different system clocks.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

uint8_t | NbrOfDataToTransfer = TxBufferSize
uint8_t | RxBuffer [RxBufferSize]
uint8_t | RxCounter = 0
uint8_t | TxBuffer []
uint8_t | TxCounter = 0
USART_InitTypeDef USART_InitStructure

Define Documentation

#define countof ( a ) (sizeof(a) / sizeof(*(a)))

Definition at line 40 of file STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/main.c.

#define RxBufferSize 0xFF

Definition at line 37 of file STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/main.c.

Referenced by main().

#define TxBufferSize (countof(TxBuffer) - 1)

Definition at line 36 of file STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/main.c.

Function Documentation

void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 86 of file STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 121 of file STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/stm32f10x_it.c.

void GPIO_Configuration ( void )

Configures the different GPIO ports.

Parameters:
None
Return values:
None

Definition at line 222 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 60 of file STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 62 of file STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/main.c.

References ENABLE, GPIO_Configuration(), NbrOfDataToTransfer, RCC_Configuration(), RESET, RxBuffer, RxBufferSize, RxCounter, TxBuffer, TxCounter, USART2, USART_InitTypeDef::USART_BaudRate, USART_Cmd(), USART_FLAG_RXNE, USART_FLAG_TXE, USART_GetFlagStatus(), USART_InitTypeDef::USART_HardwareFlowControl, USART_HardwareFlowControl_RTS_CTS, USART_Init(), USART_InitTypeDef::USART_Mode, USART_Mode_Rx, USART_Mode_Tx, USART_InitTypeDef::USART_Parity, USART_Parity_No, USART_ReceiveData(), USART_SendData(), USART_InitTypeDef::USART_StopBits, USART_StopBits_1, USART_InitTypeDef::USART_WordLength, and USART_WordLength_8b.

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 73 of file STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 51 of file STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/stm32f10x_it.c.

void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 130 of file STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/stm32f10x_it.c.

void RCC_Configuration ( void )

Configures the different system clocks.

Parameters:
None
Return values:
None

Definition at line 203 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 112 of file STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 139 of file STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/stm32f10x_it.c.

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 99 of file STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/stm32f10x_it.c.

Variable Documentation

uint8_t NbrOfDataToTransfer = TxBufferSize

Definition at line 47 of file STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/main.c.

Referenced by main(), and USARTx_IRQHandler().

uint8_t RxBuffer[RxBufferSize]

Definition at line 46 of file STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/main.c.

uint8_t RxCounter = 0

Definition at line 49 of file STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/main.c.

uint8_t TxBuffer[]
Initial value:
"\n\rUSART Hyperterminal Hardware Flow Control Example: USART - \
Hyperterminal communication using hardware flow control\n\r"

Definition at line 44 of file STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/main.c.

uint8_t TxCounter = 0

Definition at line 48 of file STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/main.c.

Referenced by HDMI_CEC_ProcessIRQSrc(), HDMI_CEC_TransmitMessage(), main(), and USARTx_IRQHandler().

USART_InitTypeDef USART_InitStructure

Definition at line 43 of file STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/main.c.


STM32F10x Standard Peripherals Firmware Library: USART_HyperTerminal_Interrupt

Defines | Functions | Variables

USART_HyperTerminal_Interrupt

STM32F10x_StdPeriph_Examples

Defines

#define | countof(a) (sizeof(a) / sizeof(*(a)))
#define | RxBufferSize 0x20
#define | TxBufferSize (countof(TxBuffer) - 1)
#define | USARTx_IRQHandler USART1_IRQHandler
#define | USARTx_IRQn USART1_IRQn

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | NVIC_Configuration (void)
Configures the nested vectored interrupt controller.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.
void | USARTx_IRQHandler (void)
This function handles USARTx global interrupt request.

Variables

uint8_t | NbrOfDataToRead = RxBufferSize
uint8_t | NbrOfDataToTransfer = TxBufferSize
uint8_t | RxBuffer [RxBufferSize]
uint16_t | RxCounter = 0
uint8_t | TxBuffer []
uint8_t | TxCounter = 0
USART_InitTypeDef USART_InitStructure

Define Documentation

#define countof ( a ) (sizeof(a) / sizeof(*(a)))

Definition at line 48 of file STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.c.

#define RxBufferSize 0x20

Definition at line 45 of file STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.c.

#define TxBufferSize (countof(TxBuffer) - 1)

Definition at line 44 of file STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.c.

#define USARTx_IRQHandler USART1_IRQHandler

Definition at line 41 of file STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.c.

#define USARTx_IRQn USART1_IRQn

Definition at line 39 of file STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/main.c.

Function Documentation

void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 106 of file STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 141 of file STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.c.

void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 80 of file STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 56 of file STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/main.c.

References COM1, ENABLE, EVAL_COM1, NVIC_Configuration(), STM_EVAL_COMInit(), USART_InitTypeDef::USART_BaudRate, USART_InitTypeDef::USART_HardwareFlowControl, USART_HardwareFlowControl_None, USART_IT_RXNE, USART_IT_TXE, USART_ITConfig(), USART_InitTypeDef::USART_Mode, USART_Mode_Rx, USART_Mode_Tx, USART_InitTypeDef::USART_Parity, USART_Parity_Odd, USART_InitTypeDef::USART_StopBits, USART_StopBits_2, USART_InitTypeDef::USART_WordLength, and USART_WordLength_8b.

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 93 of file STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 71 of file STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.c.

void NVIC_Configuration ( void )

Configures the nested vectored interrupt controller.

Parameters:
None
Return values:
None
void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 150 of file STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.c.

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 132 of file STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 159 of file STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.c.

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 119 of file STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.c.

void USARTx_IRQHandler ( void )

This function handles USARTx global interrupt request.

Parameters:
None
Return values:
None

Definition at line 172 of file STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.c.

References DISABLE, EVAL_COM1, NbrOfDataToRead, NbrOfDataToTransfer, RESET, RxBuffer, RxCounter, TxBuffer, TxCounter, USART_GetITStatus(), USART_IT_RXNE, USART_IT_TXE, USART_ITConfig(), USART_ReceiveData(), and USART_SendData().

Variable Documentation

uint8_t NbrOfDataToRead = RxBufferSize

Definition at line 55 of file STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.c.

uint8_t NbrOfDataToTransfer = TxBufferSize

Definition at line 54 of file STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.c.

uint8_t RxBuffer[RxBufferSize]

Definition at line 53 of file STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.c.

uint16_t RxCounter = 0

Definition at line 57 of file STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.c.

uint8_t TxBuffer[]
Initial value:
"\n\rUSART Hyperterminal Interrupts Example: USART-Hyperterminal\
 communication using Interrupt\n\r"

Definition at line 51 of file STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.c.

uint8_t TxCounter = 0

Definition at line 56 of file STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.c.

USART_InitTypeDef USART_InitStructure

Definition at line 44 of file STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/main.c.


STM32F10x Standard Peripherals Firmware Library: USART_Interrupt

Defines | Enumerations | Functions | Variables

USART_Interrupt

STM32F10x_StdPeriph_Examples

Defines

#define | countof(a) (sizeof(a) / sizeof(*(a)))
#define | RxBufferSize1 TxBufferSize2
#define | RxBufferSize2 TxBufferSize1
#define | TxBufferSize1 (countof(TxBuffer1) - 1)
#define | TxBufferSize2 (countof(TxBuffer2) - 1)

Enumerations

enum TestStatus {
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED
}

Functions

TestStatus | Buffercmp (uint8_t *pBuffer1, uint8_t *pBuffer2, uint16_t BufferLength)
Compares two buffers.
void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | GPIO_Configuration (void)
Configures the different GPIO ports.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | NVIC_Configuration (void)
Configures the nested vectored interrupt controller.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | RCC_Configuration (void)
Configures the different system clocks.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.
void | USARTy_IRQHandler (void)
This function handles USARTy global interrupt request.
void | USARTz_IRQHandler (void)
This function handles USARTz global interrupt request.

Variables

uint8_t | NbrOfDataToRead1 = RxBufferSize1
uint8_t | NbrOfDataToRead1
uint8_t | NbrOfDataToRead2 = RxBufferSize2
uint8_t | NbrOfDataToRead2
uint8_t | NbrOfDataToTransfer1
uint8_t | NbrOfDataToTransfer1 = TxBufferSize1
uint8_t | NbrOfDataToTransfer2 = TxBufferSize2
uint8_t | NbrOfDataToTransfer2
uint8_t | RxBuffer1 []
uint8_t | RxBuffer1 [RxBufferSize1]
uint8_t | RxBuffer2 []
uint8_t | RxBuffer2 [RxBufferSize2]
__IO uint8_t | RxCounter1 = 0x00
__IO uint8_t | RxCounter1
__IO uint8_t | RxCounter2 = 0x00
__IO uint8_t | RxCounter2
__IO TestStatus | TransferStatus1 = FAILED
__IO TestStatus | TransferStatus2 = FAILED
uint8_t | TxBuffer1 []
uint8_t | TxBuffer1 [] = "USART Interrupt Example: USARTy -> USARTz using Interrupt"
uint8_t | TxBuffer2 []
uint8_t | TxBuffer2 [] = "USART Interrupt Example: USARTz -> USARTy using Interrupt"
__IO uint8_t | TxCounter1
__IO uint8_t | TxCounter1 = 0x00
__IO uint8_t | TxCounter2
__IO uint8_t | TxCounter2 = 0x00
USART_InitTypeDef USART_InitStructure

Define Documentation

#define countof ( a ) (sizeof(a) / sizeof(*(a)))

Definition at line 44 of file STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c.

#define RxBufferSize1 TxBufferSize2

Definition at line 40 of file STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c.

Referenced by main().

#define RxBufferSize2 TxBufferSize1

Definition at line 41 of file STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c.

Referenced by main().

#define TxBufferSize1 (countof(TxBuffer1) - 1)

Definition at line 38 of file STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c.

#define TxBufferSize2 (countof(TxBuffer2) - 1)

Definition at line 39 of file STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c.

Enumeration Type Documentation

enum TestStatus
Enumerator:
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED

Definition at line 35 of file STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c.

Function Documentation

TestStatus Buffercmp | ( | uint8_t * | pBuffer1,
 |  | uint8_t * | pBuffer2,
 |  | uint16_t | BufferLength
 | ) |  |

Compares two buffers.

Parameters:
pBuffer1,pBuffer2,: buffers to be compared.
BufferLength,: buffer's length
Return values:
PASSED,: pBuffer1 identical to pBuffer2 FAILED: pBuffer1 differs from pBuffer2
void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 100 of file STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 135 of file STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.c.

void GPIO_Configuration ( void )

Configures the different GPIO ports.

Parameters:
None
Return values:
None

Definition at line 222 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 74 of file STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 76 of file STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c.

References Buffercmp(), ENABLE, GPIO_Configuration(), NVIC_Configuration(), RCC_Configuration(), RxBuffer1, RxBuffer2, RxBufferSize1, RxBufferSize2, RxCounter1, RxCounter2, TransferStatus1, TransferStatus2, TxBuffer1, TxBuffer2, USART_InitTypeDef::USART_BaudRate, USART_Cmd(), USART_InitTypeDef::USART_HardwareFlowControl, USART_HardwareFlowControl_None, USART_Init(), USART_IT_RXNE, USART_IT_TXE, USART_ITConfig(), USART_InitTypeDef::USART_Mode, USART_Mode_Rx, USART_Mode_Tx, USART_InitTypeDef::USART_Parity, USART_Parity_No, USART_InitTypeDef::USART_StopBits, USART_StopBits_1, USART_InitTypeDef::USART_WordLength, USART_WordLength_8b, USARTy, and USARTz.

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 87 of file STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 65 of file STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.c.

void NVIC_Configuration ( void )

Configures the nested vectored interrupt controller.

Parameters:
None
Return values:
None
void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 144 of file STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.c.

void RCC_Configuration ( void )

Configures the different system clocks.

Parameters:
None
Return values:
None

Definition at line 203 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 126 of file STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 153 of file STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.c.

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 113 of file STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.c.

void USARTy_IRQHandler ( void )

This function handles USARTy global interrupt request.

Parameters:
None
Return values:
None

Definition at line 166 of file STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.c.

References DISABLE, NbrOfDataToRead1, NbrOfDataToTransfer1, RESET, RxBuffer1, RxCounter1, TxBuffer1, TxCounter1, USART_GetITStatus(), USART_IT_RXNE, USART_IT_TXE, USART_ITConfig(), USART_ReceiveData(), USART_SendData(), and USARTy.

void USARTz_IRQHandler ( void )

This function handles USARTz global interrupt request.

Parameters:
None
Return values:
None

Definition at line 198 of file STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.c.

References DISABLE, NbrOfDataToRead1, NbrOfDataToTransfer2, RESET, RxBuffer2, RxCounter2, TxBuffer2, TxCounter2, USART_GetITStatus(), USART_IT_RXNE, USART_IT_TXE, USART_ITConfig(), USART_ReceiveData(), USART_SendData(), and USARTz.

Variable Documentation

uint8_t NbrOfDataToRead1 = RxBufferSize1

Definition at line 58 of file STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c.

uint8_t NbrOfDataToRead1

Definition at line 50 of file STM32F10x_StdPeriph_Examples/USART/HalfDuplex/main.c.

Referenced by main(), USARTy_IRQHandler(), and USARTz_IRQHandler().

uint8_t NbrOfDataToRead2 = RxBufferSize2

Definition at line 59 of file STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c.

uint8_t NbrOfDataToRead2

Definition at line 51 of file STM32F10x_StdPeriph_Examples/USART/HalfDuplex/main.c.

Referenced by main().

uint8_t NbrOfDataToTransfer1

Definition at line 56 of file STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c.

Referenced by USARTy_IRQHandler().

uint8_t NbrOfDataToTransfer1 = TxBufferSize1

Definition at line 56 of file STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c.

Referenced by USARTy_IRQHandler().

uint8_t NbrOfDataToTransfer2 = TxBufferSize2

Definition at line 57 of file STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c.

Referenced by USARTz_IRQHandler().

uint8_t NbrOfDataToTransfer2

Definition at line 57 of file STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c.

Referenced by USARTz_IRQHandler().

uint8_t RxBuffer1[]

Definition at line 48 of file STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/main.c.

Referenced by main(), and USARTy_IRQHandler().

uint8_t RxBuffer1[RxBufferSize1]

Definition at line 50 of file STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c.

uint8_t RxBuffer2[]

Definition at line 49 of file STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/main.c.

Referenced by main(), USART2_IRQHandler(), USART3_IRQHandler(), and USARTz_IRQHandler().

uint8_t RxBuffer2[RxBufferSize2]

Definition at line 51 of file STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c.

__IO uint8_t RxCounter1 = 0x00

Definition at line 54 of file STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c.

__IO uint8_t RxCounter1

Definition at line 52 of file STM32F10x_StdPeriph_Examples/USART/HalfDuplex/main.c.

Referenced by main(), and USARTy_IRQHandler().

__IO uint8_t RxCounter2 = 0x00

Definition at line 55 of file STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c.

__IO uint8_t RxCounter2

Definition at line 53 of file STM32F10x_StdPeriph_Examples/USART/HalfDuplex/main.c.

Referenced by main(), and USARTz_IRQHandler().

__IO TestStatus TransferStatus1 = FAILED

Definition at line 60 of file STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c.

__IO TestStatus TransferStatus2 = FAILED

Definition at line 61 of file STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c.

uint8_t TxBuffer1[]

Definition at line 46 of file STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/main.c.

Referenced by main(), and USARTy_IRQHandler().

uint8_t TxBuffer1[] = "USART Interrupt Example: USARTy -> USARTz using Interrupt"

Definition at line 48 of file STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c.

uint8_t TxBuffer2[]

Definition at line 47 of file STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/main.c.

Referenced by main(), and USARTz_IRQHandler().

uint8_t TxBuffer2[] = "USART Interrupt Example: USARTz -> USARTy using Interrupt"

Definition at line 49 of file STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c.

__IO uint8_t TxCounter1

Definition at line 52 of file STM32F10x_StdPeriph_Examples/USART/HalfDuplex/main.c.

Referenced by main(), and USARTy_IRQHandler().

__IO uint8_t TxCounter1 = 0x00

Definition at line 52 of file STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c.

__IO uint8_t TxCounter2

Definition at line 53 of file STM32F10x_StdPeriph_Examples/USART/HalfDuplex/main.c.

Referenced by main(), and USARTz_IRQHandler().

__IO uint8_t TxCounter2 = 0x00

Definition at line 53 of file STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c.

USART_InitTypeDef USART_InitStructure

Definition at line 47 of file STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c.


STM32F10x Standard Peripherals Firmware Library: USART_IrDA_Receive

Functions | Variables

USART_IrDA_Receive

STM32F10x_StdPeriph_Examples

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | GPIO_Configuration (void)
Configures the different GPIO ports.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | RCC_Configuration (void)
Configures the different system clocks.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

JOYState_TypeDef | ReceivedData = JOY_NONE
USART_InitTypeDef USART_InitStructure

Function Documentation

void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 86 of file STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 121 of file STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/stm32f10x_it.c.

void GPIO_Configuration ( void )

Configures the different GPIO ports.

Parameters:
None
Return values:
None

Definition at line 222 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 60 of file STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 52 of file STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/main.c.

References ENABLE, GPIO_Configuration(), JOY_DOWN, JOY_LEFT, JOY_NONE, JOY_RIGHT, JOY_SEL, JOY_UP, LED1, LED2, LED3, LED4, RCC_Configuration(), ReceivedData, RESET, STM_EVAL_LEDInit(), STM_EVAL_LEDOff(), STM_EVAL_LEDOn(), USART_InitTypeDef::USART_BaudRate, USART_Cmd(), USART_FLAG_RXNE, USART_GetFlagStatus(), USART_InitTypeDef::USART_HardwareFlowControl, USART_HardwareFlowControl_None, USART_Init(), USART_IrDACmd(), USART_IrDAConfig(), USART_IrDAMode_Normal, USART_InitTypeDef::USART_Mode, USART_Mode_Rx, USART_Mode_Tx, USART_InitTypeDef::USART_Parity, USART_Parity_No, USART_ReceiveData(), USART_SetPrescaler(), USART_InitTypeDef::USART_StopBits, USART_StopBits_1, USART_InitTypeDef::USART_WordLength, USART_WordLength_8b, and USARTy.

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 73 of file STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 51 of file STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/stm32f10x_it.c.

void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 130 of file STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/stm32f10x_it.c.

void RCC_Configuration ( void )

Configures the different system clocks.

Parameters:
None
Return values:
None

Definition at line 203 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 112 of file STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 139 of file STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/stm32f10x_it.c.

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 99 of file STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/stm32f10x_it.c.

Variable Documentation

JOYState_TypeDef ReceivedData = JOY_NONE

Definition at line 39 of file STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/main.c.

Referenced by main().

USART_InitTypeDef USART_InitStructure

Definition at line 38 of file STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/main.c.


STM32F10x Standard Peripherals Firmware Library: USART_IrDA_Transmit

Functions | Variables

USART_IrDA_Transmit

STM32F10x_StdPeriph_Examples

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | GPIO_Configuration (void)
Configures the different GPIO ports.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | RCC_Configuration (void)
Configures the different system clocks.
JOYState_TypeDef | ReadKey (void)
Reads key from board.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

JOYState_TypeDef | MyKey = JOY_NONE
USART_InitTypeDef USART_InitStructure

Function Documentation

void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 86 of file STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 121 of file STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/stm32f10x_it.c.

void GPIO_Configuration ( void )

Configures the different GPIO ports.

Parameters:
None
Return values:
None

Definition at line 222 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 60 of file STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 53 of file STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/main.c.

References BUTTON_DOWN, BUTTON_LEFT, BUTTON_MODE_GPIO, BUTTON_RIGHT, BUTTON_SEL, BUTTON_UP, ENABLE, GPIO_Configuration(), IOE_Config(), JOY_DOWN, JOY_LEFT, JOY_NONE, JOY_RIGHT, JOY_SEL, JOY_UP, MyKey, RCC_Configuration(), ReadKey(), RESET, STM_EVAL_PBInit(), USART_InitTypeDef::USART_BaudRate, USART_Cmd(), USART_FLAG_TXE, USART_GetFlagStatus(), USART_InitTypeDef::USART_HardwareFlowControl, USART_HardwareFlowControl_None, USART_Init(), USART_IrDACmd(), USART_IrDAConfig(), USART_IrDAMode_Normal, USART_InitTypeDef::USART_Mode, USART_Mode_Rx, USART_Mode_Tx, USART_InitTypeDef::USART_Parity, USART_Parity_No, USART_SendData(), USART_SetPrescaler(), USART_InitTypeDef::USART_StopBits, USART_StopBits_1, USART_InitTypeDef::USART_WordLength, USART_WordLength_8b, and USARTy.

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 73 of file STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 51 of file STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/stm32f10x_it.c.

void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 130 of file STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/stm32f10x_it.c.

void RCC_Configuration ( void )

Configures the different system clocks.

Parameters:
None
Return values:
None

Definition at line 203 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

JOYState_TypeDef ReadKey ( void )

Reads key from board.

Parameters:
None
Return values:
Return JOY_RIGHT, JOY_LEFT, JOY_SEL, JOY_UP, JOY_DOWN or JOY_NONE

Definition at line 211 of file STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/main.c.

References Bit_RESET, BUTTON_DOWN, BUTTON_LEFT, BUTTON_RIGHT, BUTTON_SEL, BUTTON_UP, IOE_JoyStickGetState(), JOY_DOWN, JOY_LEFT, JOY_NONE, JOY_RIGHT, JOY_SEL, JOY_UP, and STM_EVAL_PBGetState().

Referenced by main().

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 112 of file STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 139 of file STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/stm32f10x_it.c.

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 99 of file STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/stm32f10x_it.c.

Variable Documentation

JOYState_TypeDef MyKey = JOY_NONE

Definition at line 39 of file STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/main.c.

Referenced by main().

USART_InitTypeDef USART_InitStructure

Definition at line 38 of file STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/main.c.


STM32F10x Standard Peripherals Firmware Library: USART_MultiProcessor

Functions | Variables

USART_MultiProcessor

STM32F10x_StdPeriph_Examples

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | Delay (__IO uint32_t nCount)
Inserts a delay time.
void | EXTI0_IRQHandler (void)
This function handles External interrupt Line 0 request.
void | EXTI9_5_IRQHandler (void)
This function handles External lines 9 to 5 interrupt request.
void | GPIO_Configuration (void)
Configures the different GPIO ports.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | RCC_Configuration (void)
Configures the different system clocks.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

USART_InitTypeDef USART_InitStructure

Function Documentation

void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 87 of file STM32F10x_StdPeriph_Examples/USART/MultiProcessor/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 122 of file STM32F10x_StdPeriph_Examples/USART/MultiProcessor/stm32f10x_it.c.

void Delay ( __IO uint32_t nCount )

Inserts a delay time.

Parameters:
nCount,: specifies the delay time length.
Return values:
None
void EXTI0_IRQHandler ( void )

This function handles External interrupt Line 0 request.

This function handles External line 0 interrupt request.

Parameters:
None
Return values:
None

Definition at line 153 of file STM32F10x_StdPeriph_Examples/USART/MultiProcessor/stm32f10x_it.c.

References EXTI_ClearITPendingBit(), EXTI_GetITStatus(), EXTI_Line0, LED1, RESET, STM_EVAL_LEDToggle(), USART_FLAG_TXE, USART_GetFlagStatus(), USART_SendData(), and USARTy.

void EXTI9_5_IRQHandler ( void )

This function handles External lines 9 to 5 interrupt request.

This function handles EXTI Lines 9 to 5 interrupts requests.

Parameters:
None
Return values:
None

Definition at line 172 of file STM32F10x_StdPeriph_Examples/USART/MultiProcessor/stm32f10x_it.c.

References ENABLE, EXTI_ClearITPendingBit(), EXTI_GetITStatus(), KEY_BUTTON_EXTI_LINE, RESET, USART_ReceiveData(), USART_ReceiverWakeUpCmd(), and USARTz.

void GPIO_Configuration ( void )

Configures the different GPIO ports.

Parameters:
None
Return values:
None

Definition at line 222 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 61 of file STM32F10x_StdPeriph_Examples/USART/MultiProcessor/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 51 of file STM32F10x_StdPeriph_Examples/USART/MultiProcessor/main.c.

References BUTTON_KEY, BUTTON_MODE_EXTI, BUTTON_WAKEUP, Delay(), ENABLE, GPIO_Configuration(), LED1, LED2, LED3, LED4, RCC_Configuration(), RESET, STM_EVAL_LEDInit(), STM_EVAL_LEDToggle(), STM_EVAL_PBInit(), USART_InitTypeDef::USART_BaudRate, USART_Cmd(), USART_FLAG_RXNE, USART_FLAG_TXE, USART_GetFlagStatus(), USART_InitTypeDef::USART_HardwareFlowControl, USART_HardwareFlowControl_None, USART_Init(), USART_InitTypeDef::USART_Mode, USART_Mode_Rx, USART_Mode_Tx, USART_InitTypeDef::USART_Parity, USART_Parity_No, USART_ReceiveData(), USART_SendData(), USART_SetAddress(), USART_InitTypeDef::USART_StopBits, USART_StopBits_1, USART_WakeUp_AddressMark, USART_WakeUpConfig(), USART_InitTypeDef::USART_WordLength, USART_WordLength_9b, USARTy, and USARTz.

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 74 of file STM32F10x_StdPeriph_Examples/USART/MultiProcessor/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 52 of file STM32F10x_StdPeriph_Examples/USART/MultiProcessor/stm32f10x_it.c.

void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 131 of file STM32F10x_StdPeriph_Examples/USART/MultiProcessor/stm32f10x_it.c.

void RCC_Configuration ( void )

Configures the different system clocks.

Parameters:
None
Return values:
None

Definition at line 203 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 113 of file STM32F10x_StdPeriph_Examples/USART/MultiProcessor/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 140 of file STM32F10x_StdPeriph_Examples/USART/MultiProcessor/stm32f10x_it.c.

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 100 of file STM32F10x_StdPeriph_Examples/USART/MultiProcessor/stm32f10x_it.c.

Variable Documentation

USART_InitTypeDef USART_InitStructure

Definition at line 38 of file STM32F10x_StdPeriph_Examples/USART/MultiProcessor/main.c.


STM32F10x Standard Peripherals Firmware Library: USART_Polling

Defines | Enumerations | Functions | Variables

USART_Polling

STM32F10x_StdPeriph_Examples

Defines

#define | countof(a) (sizeof(a) / sizeof(*(a)))
#define | TxBufferSize (countof(TxBuffer))

Enumerations

enum TestStatus {
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED
}

Functions

TestStatus | Buffercmp (uint8_t *pBuffer1, uint8_t *pBuffer2, uint16_t BufferLength)
Compares two buffers.
void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | GPIO_Configuration (void)
Configures the different GPIO ports.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | RCC_Configuration (void)
Configures the different system clocks.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

__IO uint8_t | index = 0
uint8_t | RxBuffer [TxBufferSize]
__IO uint8_t | RxCounter = 0
volatile TestStatus | TransferStatus = FAILED
uint8_t | TxBuffer [] = "Buffer Send from USARTy to USARTz using Flags"
__IO uint8_t | TxCounter = 0
USART_InitTypeDef USART_InitStructure

Define Documentation

#define countof ( a ) (sizeof(a) / sizeof(*(a)))

Definition at line 41 of file STM32F10x_StdPeriph_Examples/USART/Polling/main.c.

#define TxBufferSize (countof(TxBuffer))

Definition at line 38 of file STM32F10x_StdPeriph_Examples/USART/Polling/main.c.

Referenced by main().

Enumeration Type Documentation

enum TestStatus
Enumerator:
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED

Definition at line 35 of file STM32F10x_StdPeriph_Examples/USART/Polling/main.c.

Function Documentation

TestStatus Buffercmp | ( | uint8_t * | pBuffer1,
 |  | uint8_t * | pBuffer2,
 |  | uint16_t | BufferLength
 | ) |  |

Compares two buffers.

Parameters:
pBuffer1,pBuffer2,: buffers to be compared.
BufferLength,: buffer's length
Return values:
PASSED,: pBuffer1 identical to pBuffer2 FAILED: pBuffer1 differs from pBuffer2
void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 86 of file STM32F10x_StdPeriph_Examples/USART/Polling/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 121 of file STM32F10x_StdPeriph_Examples/USART/Polling/stm32f10x_it.c.

void GPIO_Configuration ( void )

Configures the different GPIO ports.

Parameters:
None
Return values:
None

Definition at line 222 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 60 of file STM32F10x_StdPeriph_Examples/USART/Polling/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 63 of file STM32F10x_StdPeriph_Examples/USART/Polling/main.c.

References Buffercmp(), ENABLE, GPIO_Configuration(), RCC_Configuration(), RESET, RxBuffer, RxCounter, TransferStatus, TxBuffer, TxBufferSize, TxCounter, USART_InitTypeDef::USART_BaudRate, USART_Cmd(), USART_FLAG_RXNE, USART_FLAG_TXE, USART_GetFlagStatus(), USART_InitTypeDef::USART_HardwareFlowControl, USART_HardwareFlowControl_None, USART_Init(), USART_InitTypeDef::USART_Mode, USART_Mode_Rx, USART_Mode_Tx, USART_InitTypeDef::USART_Parity, USART_Parity_Even, USART_ReceiveData(), USART_SendData(), USART_InitTypeDef::USART_StopBits, USART_StopBits_1, USART_InitTypeDef::USART_WordLength, USART_WordLength_8b, USARTy, and USARTz.

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 73 of file STM32F10x_StdPeriph_Examples/USART/Polling/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 51 of file STM32F10x_StdPeriph_Examples/USART/Polling/stm32f10x_it.c.

void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 130 of file STM32F10x_StdPeriph_Examples/USART/Polling/stm32f10x_it.c.

void RCC_Configuration ( void )

Configures the different system clocks.

Parameters:
None
Return values:
None

Definition at line 203 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 112 of file STM32F10x_StdPeriph_Examples/USART/Polling/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 139 of file STM32F10x_StdPeriph_Examples/USART/Polling/stm32f10x_it.c.

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 99 of file STM32F10x_StdPeriph_Examples/USART/Polling/stm32f10x_it.c.

Variable Documentation

__IO uint8_t index = 0

Definition at line 54 of file STM32F10x_StdPeriph_Examples/USART/Polling/main.c.

uint8_t RxBuffer[TxBufferSize]

Definition at line 46 of file STM32F10x_StdPeriph_Examples/USART/Polling/main.c.

__IO uint8_t RxCounter = 0

Definition at line 47 of file STM32F10x_StdPeriph_Examples/USART/Polling/main.c.

volatile TestStatus TransferStatus = FAILED

Definition at line 48 of file STM32F10x_StdPeriph_Examples/USART/Polling/main.c.

uint8_t TxBuffer[] = "Buffer Send from USARTy to USARTz using Flags"

Definition at line 45 of file STM32F10x_StdPeriph_Examples/USART/Polling/main.c.

__IO uint8_t TxCounter = 0

Definition at line 47 of file STM32F10x_StdPeriph_Examples/USART/Polling/main.c.

USART_InitTypeDef USART_InitStructure

Definition at line 44 of file STM32F10x_StdPeriph_Examples/USART/Polling/main.c.


STM32F10x Standard Peripherals Firmware Library: USART_Printf

Defines | Functions | Variables

USART_Printf

STM32F10x_StdPeriph_Examples

Defines

#define | PUTCHAR_PROTOTYPE int fputc(int ch, FILE *f)

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

USART_InitTypeDef USART_InitStructure

Define Documentation

#define PUTCHAR_PROTOTYPE int fputc(int ch, FILE *f)

Definition at line 48 of file STM32F10x_StdPeriph_Examples/USART/Printf/main.c.

Function Documentation

void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 86 of file STM32F10x_StdPeriph_Examples/USART/Printf/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 121 of file STM32F10x_StdPeriph_Examples/USART/Printf/stm32f10x_it.c.

void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 60 of file STM32F10x_StdPeriph_Examples/USART/Printf/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 58 of file STM32F10x_StdPeriph_Examples/USART/Printf/main.c.

References COM1, STM_EVAL_COMInit(), USART_InitTypeDef::USART_BaudRate, USART_InitTypeDef::USART_HardwareFlowControl, USART_HardwareFlowControl_None, USART_InitTypeDef::USART_Mode, USART_Mode_Rx, USART_Mode_Tx, USART_InitTypeDef::USART_Parity, USART_Parity_No, USART_InitTypeDef::USART_StopBits, USART_StopBits_1, USART_InitTypeDef::USART_WordLength, and USART_WordLength_8b.

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 73 of file STM32F10x_StdPeriph_Examples/USART/Printf/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 51 of file STM32F10x_StdPeriph_Examples/USART/Printf/stm32f10x_it.c.

void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 130 of file STM32F10x_StdPeriph_Examples/USART/Printf/stm32f10x_it.c.

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 112 of file STM32F10x_StdPeriph_Examples/USART/Printf/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 139 of file STM32F10x_StdPeriph_Examples/USART/Printf/stm32f10x_it.c.

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 99 of file STM32F10x_StdPeriph_Examples/USART/Printf/stm32f10x_it.c.

Variable Documentation

USART_InitTypeDef USART_InitStructure

Definition at line 39 of file STM32F10x_StdPeriph_Examples/USART/Printf/main.c.


STM32F10x Standard Peripherals Firmware Library: USART_Smartcard

Data Structures | Enumerations | Functions | Variables

USART_Smartcard

STM32F10x_StdPeriph_Examples

Data Structures

struct | SC_ATR

Enumerations

enum TestStatus {
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED
}

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | EXTI15_10_IRQHandler (void)
This function handles External lines 15 to 10 interrupt request.
void | EXTI9_5_IRQHandler (void)
This function handles External lines 9 to 5 interrupt request.
void | EXTI_Configuration (void)
Configures the External Interrupts controller.
void | GPIO_Configuration (void)
Configures the different GPIO ports.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | NVIC_Configuration (void)
Configures the nested vectored interrupt controller.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | RCC_Configuration (void)
Configures the different system clocks.
uint8_t | SC_decode_Answer2reset (__IO uint8_t *card)
Decode the Card ATR Response.
void | SC_USART_IRQHandler (void)
This function handles SC_USART global interrupt request.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

volatile TestStatus | ATRDecodeStatus = FAILED
__IO uint32_t | CardInserted
__IO uint32_t | CardInserted = 0
__IO uint32_t | CardProtocol = 1
__IO uint32_t | Counter = 0
__IO uint8_t | DST_Buffer [50]
__IO uint32_t | index = 0
SC_ATR SC_A2R
USART_ClockInitTypeDef USART_ClockInitStructure
USART_InitTypeDef USART_InitStructure

Enumeration Type Documentation

enum TestStatus
Enumerator:
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED

Definition at line 52 of file STM32F10x_StdPeriph_Examples/USART/Smartcard/main.c.

Function Documentation

void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 89 of file STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 124 of file STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_it.c.

void EXTI15_10_IRQHandler ( void )

This function handles External lines 15 to 10 interrupt request.

Parameters:
None
Return values:
None

Definition at line 202 of file STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_it.c.

References ALL_IT, CardInserted, EXTI_ClearITPendingBit(), EXTI_GetITStatus(), GPIO_ResetBits(), GPIO_SetBits(), IOE_1_ADDR, IOE_2_ADDR, IOE_ClearGITPending(), IOE_ClearIOITPending(), IOE_GetGITStatus(), IOE_GIT_GPIO, IOE_IT_EXTI_LINE, IOE_JOY_IT, IOE_JoyStickGetState(), IOE_TS_GetState(), IOE_TS_IT, JOY_CENTER, JOY_DOWN, JOY_LEFT, JOY_NONE, JOY_RIGHT, JOY_State_TypeDef, JOY_UP, LCD_DisplayStringLine(), LED1, LED2, LED3, LED4, Line5, Line6, RESET, STM_EVAL_LEDOff(), STM_EVAL_LEDOn(), TS_STATE::TouchDetected, TS_State, TS_STATE::X, and TS_STATE::Y.

void EXTI9_5_IRQHandler ( void )

This function handles External lines 9 to 5 interrupt request.

This function handles EXTI Lines 9 to 5 interrupts requests.

Parameters:
None
Return values:
None

Definition at line 155 of file STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_it.c.

References CardInserted, EXTI_ClearITPendingBit(), GPIO_ResetBits(), and GPIO_SetBits().

void EXTI_Configuration ( void )

Configures the External Interrupts controller.

Parameters:
None
Return values:
None
void GPIO_Configuration ( void )

Configures the different GPIO ports.

Parameters:
None
Return values:
None

Definition at line 222 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 63 of file STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 81 of file STM32F10x_StdPeriph_Examples/USART/Smartcard/main.c.

References ATRDecodeStatus, CardInserted, CardProtocol, Counter, DST_Buffer, ENABLE, EXTI_Configuration(), FAILED, GPIO_Configuration(), index, NVIC_Configuration(), PASSED, RCC_Configuration(), RESET, SC_decode_Answer2reset(), SC_Receive_Timeout, USART_InitTypeDef::USART_BaudRate, USART_ClockInitTypeDef::USART_Clock, USART_Clock_Enable, USART_ClockInit(), USART_Cmd(), USART_ClockInitTypeDef::USART_CPHA, USART_CPHA_1Edge, USART_ClockInitTypeDef::USART_CPOL, USART_CPOL_Low, USART_FLAG_RXNE, USART_GetFlagStatus(), USART_InitTypeDef::USART_HardwareFlowControl, USART_HardwareFlowControl_None, USART_Init(), USART_IT_PE, USART_ITConfig(), USART_ClockInitTypeDef::USART_LastBit, USART_LastBit_Enable, USART_InitTypeDef::USART_Mode, USART_Mode_Rx, USART_Mode_Tx, USART_InitTypeDef::USART_Parity, USART_Parity_Even, USART_ReceiveData(), USART_SetGuardTime(), USART_SetPrescaler(), USART_SmartCardCmd(), USART_SmartCardNACKCmd(), USART_InitTypeDef::USART_StopBits, USART_StopBits_1_5, USART_InitTypeDef::USART_WordLength, and USART_WordLength_9b.

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 76 of file STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 54 of file STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_it.c.

void NVIC_Configuration ( void )

Configures the nested vectored interrupt controller.

Parameters:
None
Return values:
None
void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 133 of file STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_it.c.

void RCC_Configuration ( void )

Configures the different system clocks.

Parameters:
None
Return values:
None

Definition at line 203 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

uint8_t SC_decode_Answer2reset ( __IO uint8_t * card )

Decode the Card ATR Response.

Parameters:
card,: pointer to the buffer containing the Card ATR.
Return values:
Card protocol

Definition at line 310 of file STM32F10x_StdPeriph_Examples/USART/Smartcard/main.c.

References SC_ATR::H, HIST_LENGHT, SC_ATR::Hlenght, SETUP_LENGHT, SC_ATR::T, SC_ATR::T0, SC_ATR::Tlenght, and SC_ATR::TS.

Referenced by main().

void SC_USART_IRQHandler ( void )

This function handles SC_USART global interrupt request.

Parameters:
None
Return values:
None

Definition at line 178 of file STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_it.c.

References DISABLE, ENABLE, RESET, USART_GetITStatus(), USART_IT_PE, USART_IT_RXNE, USART_ITConfig(), and USART_ReceiveData().

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 115 of file STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 142 of file STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_it.c.

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 102 of file STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_it.c.

Variable Documentation

volatile TestStatus ATRDecodeStatus = FAILED

Definition at line 60 of file STM32F10x_StdPeriph_Examples/USART/Smartcard/main.c.

Referenced by main().

__IO uint32_t CardInserted

Definition at line 61 of file STM32F10x_StdPeriph_Examples/USART/Smartcard/main.c.

Referenced by EXTI15_10_IRQHandler(), EXTI9_5_IRQHandler(), and main().

__IO uint32_t CardInserted = 0

Definition at line 61 of file STM32F10x_StdPeriph_Examples/USART/Smartcard/main.c.

Referenced by EXTI15_10_IRQHandler(), EXTI9_5_IRQHandler(), and main().

__IO uint32_t CardProtocol = 1

Definition at line 61 of file STM32F10x_StdPeriph_Examples/USART/Smartcard/main.c.

Referenced by main().

__IO uint32_t Counter = 0

Definition at line 59 of file STM32F10x_StdPeriph_Examples/USART/Smartcard/main.c.

Referenced by main(), TIM_SetCounter(), and WWDG_Enable().

__IO uint8_t DST_Buffer[50]
Initial value:
 {
                     0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
                     0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
                     0, 0, 0, 0, 0, 0, 0, 0, 0, 0}

Definition at line 63 of file STM32F10x_StdPeriph_Examples/USART/Smartcard/main.c.

__IO uint32_t index = 0

Definition at line 59 of file STM32F10x_StdPeriph_Examples/USART/Smartcard/main.c.

SC_ATR SC_A2R

Definition at line 58 of file STM32F10x_StdPeriph_Examples/USART/Smartcard/main.c.

USART_ClockInitTypeDef USART_ClockInitStructure

Definition at line 57 of file STM32F10x_StdPeriph_Examples/USART/Smartcard/main.c.

USART_InitTypeDef USART_InitStructure

Definition at line 56 of file STM32F10x_StdPeriph_Examples/USART/Smartcard/main.c.


STM32F10x Standard Peripherals Firmware Library: SC_ATR Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

SC_ATR Struct Reference
USART_Smartcard

Data Fields

uint8_t | H [HIST_LENGHT]
uint8_t | Hlenght
uint8_t | T [SETUP_LENGHT]
uint8_t | T0
uint8_t | Tlenght
uint8_t | TS

Detailed Description

Definition at line 42 of file STM32F10x_StdPeriph_Examples/USART/Smartcard/main.c.

Field Documentation

uint8_t SC_ATR::H[HIST_LENGHT]

Definition at line 47 of file STM32F10x_StdPeriph_Examples/USART/Smartcard/main.c.

Referenced by SC_decode_Answer2reset().

uint8_t SC_ATR::Hlenght

Definition at line 49 of file STM32F10x_StdPeriph_Examples/USART/Smartcard/main.c.

Referenced by SC_decode_Answer2reset().

uint8_t SC_ATR::T[SETUP_LENGHT]

Definition at line 46 of file STM32F10x_StdPeriph_Examples/USART/Smartcard/main.c.

Referenced by SC_decode_Answer2reset().

uint8_t SC_ATR::T0

Definition at line 45 of file STM32F10x_StdPeriph_Examples/USART/Smartcard/main.c.

Referenced by SC_decode_Answer2reset().

uint8_t SC_ATR::Tlenght

Definition at line 48 of file STM32F10x_StdPeriph_Examples/USART/Smartcard/main.c.

Referenced by SC_decode_Answer2reset().

uint8_t SC_ATR::TS

Definition at line 44 of file STM32F10x_StdPeriph_Examples/USART/Smartcard/main.c.

Referenced by SC_decode_Answer2reset().

The documentation for this struct was generated from the following file:
  • STM32F10x_StdPeriph_Examples/USART/Smartcard/main.c


STM32F10x Standard Peripherals Firmware Library: USART_Synchronous

Defines | Enumerations | Functions | Variables

USART_Synchronous

STM32F10x_StdPeriph_Examples

Defines

#define | countof(a) (sizeof(a) / sizeof(*(a)))
#define | DYMMY_BYTE 0x00
#define | TxBufferSize1 (countof(TxBuffer1) - 1)
#define | TxBufferSize2 (countof(TxBuffer2) - 1)

Enumerations

enum TestStatus {
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED
}

Functions

TestStatus | Buffercmp (uint8_t *pBuffer1, uint8_t *pBuffer2, uint16_t BufferLength)
Compares two buffers.
void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | GPIO_Configuration (void)
Configures the different GPIO ports.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | RCC_Configuration (void)
Configures the different system clocks.
void | SPI_Configuration (void)
Configures the SPI.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

__IO uint8_t | NbrOfDataToRead1 = TxBufferSize2
__IO uint8_t | NbrOfDataToRead2 = TxBufferSize1
uint8_t | RxBuffer1 [TxBufferSize2]
uint8_t | RxBuffer2 [TxBufferSize1]
__IO uint8_t | RxCounter1 = 0
__IO uint8_t | RxCounter2 = 0
volatile TestStatus | TransferStatus1 = FAILED
volatile TestStatus | TransferStatus2 = FAILED
uint8_t | TxBuffer1 [] = "USART Synchronous Example: USARTy -> SPIy using TXE and RXNE Flags"
uint8_t | TxBuffer2 [] = "USART Synchronous Example: SPIy -> USARTy using TXE and RXNE Flags"
__IO uint8_t | TxCounter1 = 0
__IO uint8_t | TxCounter2 = 0
USART_ClockInitTypeDef USART_ClockInitStructure
USART_InitTypeDef USART_InitStructure

Define Documentation

#define countof ( a ) (sizeof(a) / sizeof(*(a)))

Definition at line 43 of file STM32F10x_StdPeriph_Examples/USART/Synchronous/main.c.

#define DYMMY_BYTE 0x00

Definition at line 40 of file STM32F10x_StdPeriph_Examples/USART/Synchronous/main.c.

Referenced by main().

#define TxBufferSize1 (countof(TxBuffer1) - 1)

Definition at line 38 of file STM32F10x_StdPeriph_Examples/USART/Synchronous/main.c.

Referenced by main().

#define TxBufferSize2 (countof(TxBuffer2) - 1)

Definition at line 39 of file STM32F10x_StdPeriph_Examples/USART/Synchronous/main.c.

Referenced by main().

Enumeration Type Documentation

enum TestStatus
Enumerator:
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED
FAILED
PASSED

Definition at line 35 of file STM32F10x_StdPeriph_Examples/USART/Synchronous/main.c.

Function Documentation

TestStatus Buffercmp | ( | uint8_t * | pBuffer1,
 |  | uint8_t * | pBuffer2,
 |  | uint16_t | BufferLength
 | ) |  |

Compares two buffers.

Parameters:
pBuffer1,pBuffer2,: buffers to be compared.
BufferLength,: buffer's length
Return values:
PASSED,: pBuffer1 identical to pBuffer2 FAILED: pBuffer1 differs from pBuffer2
void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 86 of file STM32F10x_StdPeriph_Examples/USART/Synchronous/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 121 of file STM32F10x_StdPeriph_Examples/USART/Synchronous/stm32f10x_it.c.

void GPIO_Configuration ( void )

Configures the different GPIO ports.

Parameters:
None
Return values:
None

Definition at line 222 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

References GPIO_Init(), GPIO_InitStructure, GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_AIN, GPIO_InitTypeDef::GPIO_Pin, GPIO_Pin_2, GPIO_Pin_3, GPIO_Pin_4, and GPIOC.

void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 60 of file STM32F10x_StdPeriph_Examples/USART/Synchronous/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 72 of file STM32F10x_StdPeriph_Examples/USART/Synchronous/main.c.

References Buffercmp(), DYMMY_BYTE, ENABLE, GPIO_Configuration(), NbrOfDataToRead1, NbrOfDataToRead2, RCC_Configuration(), RESET, RxBuffer1, RxBuffer2, RxCounter1, RxCounter2, SPI_Configuration(), SPI_I2S_FLAG_RXNE, SPI_I2S_FLAG_TXE, SPI_I2S_GetFlagStatus(), SPI_I2S_ReceiveData(), SPI_I2S_SendData(), TransferStatus1, TransferStatus2, TxBuffer1, TxBuffer2, TxBufferSize1, TxBufferSize2, TxCounter1, TxCounter2, USART_InitTypeDef::USART_BaudRate, USART_ClockInitTypeDef::USART_Clock, USART_Clock_Enable, USART_ClockInit(), USART_Cmd(), USART_ClockInitTypeDef::USART_CPHA, USART_CPHA_2Edge, USART_ClockInitTypeDef::USART_CPOL, USART_CPOL_High, USART_FLAG_RXNE, USART_FLAG_TC, USART_GetFlagStatus(), USART_InitTypeDef::USART_HardwareFlowControl, USART_HardwareFlowControl_None, USART_Init(), USART_ClockInitTypeDef::USART_LastBit, USART_LastBit_Enable, USART_InitTypeDef::USART_Mode, USART_Mode_Rx, USART_Mode_Tx, USART_InitTypeDef::USART_Parity, USART_Parity_No, USART_ReceiveData(), USART_SendData(), USART_InitTypeDef::USART_StopBits, USART_StopBits_1, USART_InitTypeDef::USART_WordLength, USART_WordLength_8b, and USARTy.

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 73 of file STM32F10x_StdPeriph_Examples/USART/Synchronous/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 51 of file STM32F10x_StdPeriph_Examples/USART/Synchronous/stm32f10x_it.c.

void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 130 of file STM32F10x_StdPeriph_Examples/USART/Synchronous/stm32f10x_it.c.

void RCC_Configuration ( void )

Configures the different system clocks.

Parameters:
None
Return values:
None

Definition at line 203 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.

References ENABLE, RCC_ADCCLKConfig(), RCC_AHBPeriph_DMA1, RCC_AHBPeriph_DMA2, RCC_AHBPeriphClockCmd(), RCC_APB2Periph_ADC1, RCC_APB2Periph_ADC2, RCC_APB2Periph_ADC3, RCC_APB2Periph_GPIOC, RCC_APB2PeriphClockCmd(), and RCC_PCLK2_Div4.

void SPI_Configuration ( void )

Configures the SPI.

Parameters:
None
Return values:
None

Definition at line 229 of file STM32F10x_StdPeriph_Examples/USART/Synchronous/main.c.

References ENABLE, SPI_Cmd(), SPI_InitTypeDef::SPI_CPHA, SPI_CPHA_2Edge, SPI_InitTypeDef::SPI_CPOL, SPI_CPOL_High, SPI_InitTypeDef::SPI_DataSize, SPI_DataSize_8b, SPI_InitTypeDef::SPI_Direction, SPI_Direction_2Lines_FullDuplex, SPI_InitTypeDef::SPI_FirstBit, SPI_FirstBit_LSB, SPI_I2S_DeInit(), SPI_Init(), SPI_InitStructure, SPI_InitTypeDef::SPI_Mode, SPI_Mode_Slave, SPI_InitTypeDef::SPI_NSS, SPI_NSS_Soft, and SPI_StructInit().

Referenced by main().

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 112 of file STM32F10x_StdPeriph_Examples/USART/Synchronous/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 139 of file STM32F10x_StdPeriph_Examples/USART/Synchronous/stm32f10x_it.c.

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 99 of file STM32F10x_StdPeriph_Examples/USART/Synchronous/stm32f10x_it.c.

Variable Documentation

__IO uint8_t NbrOfDataToRead1 = TxBufferSize2

Definition at line 53 of file STM32F10x_StdPeriph_Examples/USART/Synchronous/main.c.

__IO uint8_t NbrOfDataToRead2 = TxBufferSize1

Definition at line 54 of file STM32F10x_StdPeriph_Examples/USART/Synchronous/main.c.

uint8_t RxBuffer1[TxBufferSize2]

Definition at line 51 of file STM32F10x_StdPeriph_Examples/USART/Synchronous/main.c.

uint8_t RxBuffer2[TxBufferSize1]

Definition at line 52 of file STM32F10x_StdPeriph_Examples/USART/Synchronous/main.c.

__IO uint8_t RxCounter1 = 0

Definition at line 55 of file STM32F10x_StdPeriph_Examples/USART/Synchronous/main.c.

__IO uint8_t RxCounter2 = 0

Definition at line 56 of file STM32F10x_StdPeriph_Examples/USART/Synchronous/main.c.

volatile TestStatus TransferStatus1 = FAILED

Definition at line 57 of file STM32F10x_StdPeriph_Examples/USART/Synchronous/main.c.

volatile TestStatus TransferStatus2 = FAILED

Definition at line 57 of file STM32F10x_StdPeriph_Examples/USART/Synchronous/main.c.

uint8_t TxBuffer1[] = "USART Synchronous Example: USARTy -> SPIy using TXE and RXNE Flags"

Definition at line 49 of file STM32F10x_StdPeriph_Examples/USART/Synchronous/main.c.

uint8_t TxBuffer2[] = "USART Synchronous Example: SPIy -> USARTy using TXE and RXNE Flags"

Definition at line 50 of file STM32F10x_StdPeriph_Examples/USART/Synchronous/main.c.

__IO uint8_t TxCounter1 = 0

Definition at line 55 of file STM32F10x_StdPeriph_Examples/USART/Synchronous/main.c.

__IO uint8_t TxCounter2 = 0

Definition at line 56 of file STM32F10x_StdPeriph_Examples/USART/Synchronous/main.c.

USART_ClockInitTypeDef USART_ClockInitStructure

Definition at line 47 of file STM32F10x_StdPeriph_Examples/USART/Synchronous/main.c.

USART_InitTypeDef USART_InitStructure

Definition at line 46 of file STM32F10x_StdPeriph_Examples/USART/Synchronous/main.c.


STM32F10x Standard Peripherals Firmware Library: WWDG_Reset

Functions | Variables

WWDG_Reset

STM32F10x_StdPeriph_Examples

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | Delay (__IO uint32_t nTime)
Inserts a delay time.
void | EXTI9_5_IRQHandler (void)
This function handles External lines 9 to 5 interrupt request.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

__IO uint32_t | TimingDelay = 0
__IO uint32_t | TimingDelay

Function Documentation

void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 87 of file STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 111 of file STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_it.c.

void Delay ( __IO uint32_t nTime )

Inserts a delay time.

Parameters:
nTime,: specifies the delay time length, in milliseconds.
Return values:
None
void EXTI9_5_IRQHandler ( void )

This function handles External lines 9 to 5 interrupt request.

This function handles EXTI Lines 9 to 5 interrupts requests.

Parameters:
None
Return values:
None

Definition at line 152 of file STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_it.c.

References CEC_SendDataByte(), CEC_StartOfMessage(), EXTI_ClearITPendingBit(), EXTI_GetITStatus(), FOLLOWER, HeaderBlockValueToSend, KEY_BUTTON_EXTI_LINE, LED3, MY_DEVICE_ADDRESS, RESET, and STM_EVAL_LEDOn().

void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 63 of file STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 51 of file STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/main.c.

References BUTTON_KEY, BUTTON_MODE_EXTI, Delay(), ENABLE, LED1, LED2, RCC_APB1Periph_WWDG, RCC_APB1PeriphClockCmd(), RCC_ClearFlag(), RCC_FLAG_WWDGRST, RCC_GetFlagStatus(), RESET, STM_EVAL_LEDInit(), STM_EVAL_LEDOff(), STM_EVAL_LEDOn(), STM_EVAL_LEDToggle(), STM_EVAL_PBInit(), SystemCoreClock, WWDG_Enable(), WWDG_Prescaler_8, WWDG_SetCounter(), WWDG_SetPrescaler(), and WWDG_SetWindowValue().

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 75 of file STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 54 of file STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_it.c.

void PendSV_Handler ( void )

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 129 of file STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_it.c.

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 120 of file STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 138 of file STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_it.c.

References TimingDelay.

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 99 of file STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_it.c.

Variable Documentation

__IO uint32_t TimingDelay = 0

Definition at line 39 of file STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/main.c.

__IO uint32_t TimingDelay

Definition at line 43 of file STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/main.c.


STM32F10x Standard Peripherals Firmware Library: STM32F10x_StdPeriph_Template

Defines | Functions | Variables

STM32F10x_StdPeriph_Template

Defines

#define | PUTCHAR_PROTOTYPE int fputc(int ch, FILE *f)

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
int | main (void)
Main program.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSVC exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

USART_InitTypeDef USART_InitStructure

Define Documentation

#define PUTCHAR_PROTOTYPE int fputc(int ch, FILE *f)

Definition at line 81 of file STM32F10x_StdPeriph_Template/main.c.

Function Documentation

void BusFault_Handler ( void )

This function handles Bus Fault exception.

Parameters:
None
Return values:
None

Definition at line 82 of file STM32F10x_StdPeriph_Template/stm32f10x_it.c.

void DebugMon_Handler ( void )

This function handles Debug Monitor exception.

Parameters:
None
Return values:
None

Definition at line 117 of file STM32F10x_StdPeriph_Template/stm32f10x_it.c.

void HardFault_Handler ( void )

This function handles Hard Fault exception.

Parameters:
None
Return values:
None

Definition at line 56 of file STM32F10x_StdPeriph_Template/stm32f10x_it.c.

int main ( void )

Main program.

Parameters:
None
Return values:
None

< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file

Definition at line 91 of file STM32F10x_StdPeriph_Template/main.c.

References COM1, LCD_Clear(), LCD_COLOR_BLUE, LCD_COLOR_WHITE, LCD_DisplayStringLine(), LCD_LINE_0, LCD_LINE_1, LCD_LINE_2, LCD_SetBackColor(), LCD_SetTextColor(), LED1, LED2, LED3, LED4, MESSAGE1, MESSAGE2, MESSAGE3, STM32100B_LCD_Init(), STM32100E_LCD_Init(), STM3210B_LCD_Init(), STM3210C_LCD_Init(), STM3210E_LCD_Init(), STM_EVAL_COMInit(), STM_EVAL_LEDInit(), STM_EVAL_LEDOn(), USART_InitTypeDef::USART_BaudRate, USART_InitTypeDef::USART_HardwareFlowControl, USART_HardwareFlowControl_None, USART_InitTypeDef::USART_Mode, USART_Mode_Rx, USART_Mode_Tx, USART_InitTypeDef::USART_Parity, USART_Parity_No, USART_InitTypeDef::USART_StopBits, USART_StopBits_1, USART_InitTypeDef::USART_WordLength, and USART_WordLength_8b.

void MemManage_Handler ( void )

This function handles Memory Manage exception.

Parameters:
None
Return values:
None

Definition at line 69 of file STM32F10x_StdPeriph_Template/stm32f10x_it.c.

void NMI_Handler ( void )

This function handles NMI exception.

Parameters:
None
Return values:
None

Definition at line 47 of file STM32F10x_StdPeriph_Template/stm32f10x_it.c.

void PendSV_Handler ( void )

This function handles PendSVC exception.

This function handles PendSV_Handler exception.

Parameters:
None
Return values:
None

Definition at line 126 of file STM32F10x_StdPeriph_Template/stm32f10x_it.c.

void SVC_Handler ( void )

This function handles SVCall exception.

Parameters:
None
Return values:
None

Definition at line 108 of file STM32F10x_StdPeriph_Template/stm32f10x_it.c.

void SysTick_Handler ( void )

This function handles SysTick Handler.

Parameters:
None
Return values:
None

Definition at line 135 of file STM32F10x_StdPeriph_Template/stm32f10x_it.c.

void UsageFault_Handler ( void )

This function handles Usage Fault exception.

Parameters:
None
Return values:
None

Definition at line 95 of file STM32F10x_StdPeriph_Template/stm32f10x_it.c.

Variable Documentation

USART_InitTypeDef USART_InitStructure

Definition at line 73 of file STM32F10x_StdPeriph_Template/main.c.


STM32F10x Standard Peripherals Firmware Library: STM32_EVAL_Private_TypesDefinitions

STM32_EVAL_Private_TypesDefinitions

STM32_EVAL_Abstraction_Layer


STM32F10x Standard Peripherals Firmware Library: STM32_EVAL_Private_Defines

STM32_EVAL_Private_Defines

STM32_EVAL_Abstraction_Layer


STM32F10x Standard Peripherals Firmware Library: STM32_EVAL_Private_Macros

STM32_EVAL_Private_Macros

STM32_EVAL_Abstraction_Layer


STM32F10x Standard Peripherals Firmware Library: STM32_EVAL_Private_Variables

STM32_EVAL_Private_Variables

STM32_EVAL_Abstraction_Layer


STM32F10x Standard Peripherals Firmware Library: STM32_EVAL_Private_FunctionPrototypes

STM32_EVAL_Private_FunctionPrototypes

STM32_EVAL_Abstraction_Layer


STM32F10x Standard Peripherals Firmware Library: STM32_EVAL_Private_Functions

STM32_EVAL_Private_Functions

STM32_EVAL_Abstraction_Layer


STM32F10x Standard Peripherals Firmware Library: STM32_EVAL_HARDWARE_RESOURCES

STM32_EVAL_HARDWARE_RESOURCES

STM32_EVAL_Abstraction_Layer


STM32F10x Standard Peripherals Firmware Library: STM32_EVAL_Exported_Types

Enumerations

STM32_EVAL_Exported_Types

STM32_EVAL_Abstraction_Layer

Enumerations

enum Button_TypeDef {
BUTTON_WAKEUP = 0, BUTTON_TAMPER = 1, BUTTON_KEY = 2, BUTTON_RIGHT = 3,
BUTTON_LEFT = 4, BUTTON_UP = 5, BUTTON_DOWN = 6, BUTTON_SEL = 7
}
enum | ButtonMode_TypeDef { BUTTON_MODE_GPIO = 0, BUTTON_MODE_EXTI = 1 }
enum | COM_TypeDef { COM1 = 0, COM2 = 1 }
enum JOYState_TypeDef {
JOY_NONE = 0, JOY_SEL = 1, JOY_DOWN = 2, JOY_LEFT = 3,
JOY_RIGHT = 4, JOY_UP = 5, JOY_NONE = 0, JOY_SEL = 1,
JOY_DOWN = 2, JOY_LEFT = 3, JOY_RIGHT = 4, JOY_UP = 5
}
enum | Led_TypeDef { LED1 = 0, LED2 = 1, LED3 = 2, LED4 = 3 }

Enumeration Type Documentation

enum Button_TypeDef
Enumerator:
BUTTON_WAKEUP
BUTTON_TAMPER
BUTTON_KEY
BUTTON_RIGHT
BUTTON_LEFT
BUTTON_UP
BUTTON_DOWN
BUTTON_SEL

Definition at line 91 of file stm32_eval.h.

enum ButtonMode_TypeDef
Enumerator:
BUTTON_MODE_GPIO
BUTTON_MODE_EXTI

Definition at line 103 of file stm32_eval.h.

enum COM_TypeDef
Enumerator:
COM1
COM2

Definition at line 120 of file stm32_eval.h.

enum JOYState_TypeDef
Enumerator:
JOY_NONE
JOY_SEL
JOY_DOWN
JOY_LEFT
JOY_RIGHT
JOY_UP
JOY_NONE
JOY_SEL
JOY_DOWN
JOY_LEFT
JOY_RIGHT
JOY_UP

Definition at line 109 of file stm32_eval.h.

enum Led_TypeDef
Enumerator:
LED1
LED2
LED3
LED4

Definition at line 83 of file stm32_eval.h.


STM32F10x Standard Peripherals Firmware Library: STM32_EVAL_Exported_Constants

Defines

STM32_EVAL_Exported_Constants

STM32_EVAL_Abstraction_Layer

Defines

#define | Black LCD_COLOR_BLACK
#define | Blue LCD_COLOR_BLUE
#define | Blue2 LCD_COLOR_BLUE2
#define | Button_DOWN BUTTON_DOWN
#define | Button_KEY BUTTON_KEY
#define | Button_LEFT BUTTON_LEFT
#define | Button_Mode_TypeDef ButtonMode_TypeDef
#define | Button_RIGHT BUTTON_RIGHT
#define | Button_SEL BUTTON_SEL
#define | Button_TAMPER BUTTON_TAMPER
#define | Button_UP BUTTON_UP
#define | Button_WAKEUP BUTTON_WAKEUP
Uncomment the line corresponding to the STMicroelectronics evaluation board used in your application.
#define | Cyan LCD_COLOR_CYAN
#define | Green LCD_COLOR_GREEN
#define | Grey LCD_COLOR_GREY
#define | Horizontal LCD_DIR_HORIZONTAL
#define | JOY_CENTER JOY_SEL
#define | JOY_State_TypeDef JOYState_TypeDef
#define | LCD_RSNWR_GPIO_CLK LCD_NWR_GPIO_CLK
LCD Defines Legacy.
#define | LCD_SPI_GPIO_CLK LCD_SPI_SCK_GPIO_CLK
#define | LCD_SPI_GPIO_PORT LCD_SPI_SCK_GPIO_PORT
#define | Line0 LCD_LINE_0
#define | Line1 LCD_LINE_1
#define | Line2 LCD_LINE_2
#define | Line3 LCD_LINE_3
#define | Line4 LCD_LINE_4
#define | Line5 LCD_LINE_5
#define | Line6 LCD_LINE_6
#define | Line7 LCD_LINE_7
#define | Line8 LCD_LINE_8
#define | Line9 LCD_LINE_9
#define | Magenta LCD_COLOR_MAGENTA
#define | Mode_EXTI BUTTON_MODE_EXTI
#define | Mode_GPIO BUTTON_MODE_GPIO
#define | R0 LCD_REG_0
#define | R1 LCD_REG_1
#define | R10 LCD_REG_10
#define | R106 LCD_REG_106
#define | R118 LCD_REG_118
#define | R12 LCD_REG_12
#define | R128 LCD_REG_128
#define | R129 LCD_REG_129
#define | R13 LCD_REG_13
#define | R130 LCD_REG_130
#define | R131 LCD_REG_131
#define | R132 LCD_REG_132
#define | R133 LCD_REG_133
#define | R134 LCD_REG_134
#define | R135 LCD_REG_135
#define | R136 LCD_REG_136
#define | R137 LCD_REG_137
#define | R139 LCD_REG_139
#define | R14 LCD_REG_14
#define | R140 LCD_REG_140
#define | R141 LCD_REG_141
#define | R143 LCD_REG_143
#define | R144 LCD_REG_144
#define | R145 LCD_REG_145
#define | R146 LCD_REG_146
#define | R147 LCD_REG_147
#define | R148 LCD_REG_148
#define | R149 LCD_REG_149
#define | R15 LCD_REG_15
#define | R150 LCD_REG_150
#define | R151 LCD_REG_151
#define | R152 LCD_REG_152
#define | R153 LCD_REG_153
#define | R154 LCD_REG_154
#define | R157 LCD_REG_157
#define | R16 LCD_REG_16
#define | R17 LCD_REG_17
#define | R18 LCD_REG_18
#define | R19 LCD_REG_19
#define | R192 LCD_REG_192
#define | R193 LCD_REG_193
#define | R2 LCD_REG_2
#define | R20 LCD_REG_20
#define | R21 LCD_REG_21
#define | R22 LCD_REG_22
#define | R227 LCD_REG_227
#define | R229 LCD_REG_229
#define | R23 LCD_REG_23
#define | R231 LCD_REG_231
#define | R239 LCD_REG_239
#define | R24 LCD_REG_24
#define | R25 LCD_REG_25
#define | R26 LCD_REG_26
#define | R27 LCD_REG_27
#define | R28 LCD_REG_28
#define | R29 LCD_REG_29
#define | R3 LCD_REG_3
#define | R30 LCD_REG_30
#define | R31 LCD_REG_31
#define | R32 LCD_REG_32
#define | R33 LCD_REG_33
#define | R34 LCD_REG_34
#define | R36 LCD_REG_36
#define | R37 LCD_REG_37
#define | R4 LCD_REG_4
#define | R40 LCD_REG_40
#define | R41 LCD_REG_41
#define | R43 LCD_REG_43
#define | R45 LCD_REG_45
#define | R48 LCD_REG_48
#define | R49 LCD_REG_49
#define | R5 LCD_REG_5
#define | R50 LCD_REG_50
#define | R51 LCD_REG_51
#define | R52 LCD_REG_52
#define | R53 LCD_REG_53
#define | R54 LCD_REG_54
#define | R55 LCD_REG_55
#define | R56 LCD_REG_56
#define | R57 LCD_REG_57
#define | R59 LCD_REG_59
#define | R6 LCD_REG_6
#define | R60 LCD_REG_60
#define | R61 LCD_REG_61
#define | R62 LCD_REG_62
#define | R63 LCD_REG_63
#define | R64 LCD_REG_64
#define | R65 LCD_REG_65
#define | R66 LCD_REG_66
#define | R67 LCD_REG_67
#define | R68 LCD_REG_68
#define | R69 LCD_REG_69
#define | R7 LCD_REG_7
#define | R70 LCD_REG_70
#define | R71 LCD_REG_71
#define | R72 LCD_REG_72
#define | R73 LCD_REG_73
#define | R74 LCD_REG_74
#define | R75 LCD_REG_75
#define | R76 LCD_REG_76
#define | R77 LCD_REG_77
#define | R78 LCD_REG_78
#define | R79 LCD_REG_79
#define | R8 LCD_REG_8
#define | R80 LCD_REG_80
#define | R81 LCD_REG_81
#define | R82 LCD_REG_82
#define | R83 LCD_REG_83
#define | R9 LCD_REG_9
#define | R96 LCD_REG_96
#define | R97 LCD_REG_97
#define | Red LCD_COLOR_RED
#define | Vertical LCD_DIR_VERTICAL
#define | White LCD_COLOR_WHITE
#define | Yellow LCD_COLOR_YELLOW

Define Documentation

#define Black LCD_COLOR_BLACK

Definition at line 308 of file stm32_eval.h.

Referenced by main().

#define Blue LCD_COLOR_BLUE

Definition at line 310 of file stm32_eval.h.

Referenced by main().

#define Blue2 LCD_COLOR_BLUE2

Definition at line 311 of file stm32_eval.h.

#define Button_DOWN BUTTON_DOWN

Definition at line 182 of file stm32_eval.h.

#define Button_KEY BUTTON_KEY

Definition at line 178 of file stm32_eval.h.

#define Button_LEFT BUTTON_LEFT

Definition at line 180 of file stm32_eval.h.

#define Button_Mode_TypeDef ButtonMode_TypeDef

Definition at line 186 of file stm32_eval.h.

#define Button_RIGHT BUTTON_RIGHT

Definition at line 179 of file stm32_eval.h.

#define Button_SEL BUTTON_SEL

Definition at line 183 of file stm32_eval.h.

#define Button_TAMPER BUTTON_TAMPER

Definition at line 177 of file stm32_eval.h.

#define Button_UP BUTTON_UP

Definition at line 181 of file stm32_eval.h.

#define Button_WAKEUP BUTTON_WAKEUP

Uncomment the line corresponding to the STMicroelectronics evaluation board used in your application.

Tip: To avoid modifying this file each time you need to switch between these boards, you can define the board in your toolchain compiler preprocessor. STM32 Button Defines Legacy

Definition at line 176 of file stm32_eval.h.

#define Cyan LCD_COLOR_CYAN

Definition at line 315 of file stm32_eval.h.

#define Green LCD_COLOR_GREEN

Definition at line 314 of file stm32_eval.h.

#define Grey LCD_COLOR_GREY

Definition at line 309 of file stm32_eval.h.

#define Horizontal LCD_DIR_HORIZONTAL

Definition at line 327 of file stm32_eval.h.

#define JOY_CENTER JOY_SEL

Definition at line 187 of file stm32_eval.h.

Referenced by EXTI15_10_IRQHandler(), and main().

#define JOY_State_TypeDef JOYState_TypeDef

Definition at line 188 of file stm32_eval.h.

Referenced by EXTI15_10_IRQHandler(), and main().

#define LCD_RSNWR_GPIO_CLK LCD_NWR_GPIO_CLK

LCD Defines Legacy.

Definition at line 193 of file stm32_eval.h.

#define LCD_SPI_GPIO_CLK LCD_SPI_SCK_GPIO_CLK

Definition at line 195 of file stm32_eval.h.

#define LCD_SPI_GPIO_PORT LCD_SPI_SCK_GPIO_PORT

Definition at line 194 of file stm32_eval.h.

#define Line0 LCD_LINE_0

Definition at line 317 of file stm32_eval.h.

Referenced by main().

#define Line1 LCD_LINE_1

Definition at line 318 of file stm32_eval.h.

Referenced by main().

#define Line2 LCD_LINE_2

Definition at line 319 of file stm32_eval.h.

Referenced by main().

#define Line3 LCD_LINE_3

Definition at line 320 of file stm32_eval.h.

#define Line4 LCD_LINE_4

Definition at line 321 of file stm32_eval.h.

Referenced by main().

#define Line5 LCD_LINE_5

Definition at line 322 of file stm32_eval.h.

Referenced by EXTI15_10_IRQHandler(), and main().

#define Line6 LCD_LINE_6

Definition at line 323 of file stm32_eval.h.

Referenced by EXTI15_10_IRQHandler(), and main().

#define Line7 LCD_LINE_7

Definition at line 324 of file stm32_eval.h.

Referenced by main().

#define Line8 LCD_LINE_8

Definition at line 325 of file stm32_eval.h.

#define Line9 LCD_LINE_9

Definition at line 326 of file stm32_eval.h.

#define Magenta LCD_COLOR_MAGENTA

Definition at line 313 of file stm32_eval.h.

#define Mode_EXTI BUTTON_MODE_EXTI

Definition at line 185 of file stm32_eval.h.

#define Mode_GPIO BUTTON_MODE_GPIO

Definition at line 184 of file stm32_eval.h.

#define R0 LCD_REG_0

Definition at line 196 of file stm32_eval.h.

#define R1 LCD_REG_1

Definition at line 197 of file stm32_eval.h.

#define R10 LCD_REG_10

Definition at line 206 of file stm32_eval.h.

#define R106 LCD_REG_106

Definition at line 273 of file stm32_eval.h.

#define R118 LCD_REG_118

Definition at line 274 of file stm32_eval.h.

#define R12 LCD_REG_12

Definition at line 207 of file stm32_eval.h.

#define R128 LCD_REG_128

Definition at line 275 of file stm32_eval.h.

#define R129 LCD_REG_129

Definition at line 276 of file stm32_eval.h.

#define R13 LCD_REG_13

Definition at line 208 of file stm32_eval.h.

#define R130 LCD_REG_130

Definition at line 277 of file stm32_eval.h.

#define R131 LCD_REG_131

Definition at line 278 of file stm32_eval.h.

#define R132 LCD_REG_132

Definition at line 279 of file stm32_eval.h.

#define R133 LCD_REG_133

Definition at line 280 of file stm32_eval.h.

#define R134 LCD_REG_134

Definition at line 281 of file stm32_eval.h.

#define R135 LCD_REG_135

Definition at line 282 of file stm32_eval.h.

#define R136 LCD_REG_136

Definition at line 283 of file stm32_eval.h.

#define R137 LCD_REG_137

Definition at line 284 of file stm32_eval.h.

#define R139 LCD_REG_139

Definition at line 285 of file stm32_eval.h.

#define R14 LCD_REG_14

Definition at line 209 of file stm32_eval.h.

#define R140 LCD_REG_140

Definition at line 286 of file stm32_eval.h.

#define R141 LCD_REG_141

Definition at line 287 of file stm32_eval.h.

#define R143 LCD_REG_143

Definition at line 288 of file stm32_eval.h.

#define R144 LCD_REG_144

Definition at line 289 of file stm32_eval.h.

#define R145 LCD_REG_145

Definition at line 290 of file stm32_eval.h.

#define R146 LCD_REG_146

Definition at line 291 of file stm32_eval.h.

#define R147 LCD_REG_147

Definition at line 292 of file stm32_eval.h.

#define R148 LCD_REG_148

Definition at line 293 of file stm32_eval.h.

#define R149 LCD_REG_149

Definition at line 294 of file stm32_eval.h.

#define R15 LCD_REG_15

Definition at line 210 of file stm32_eval.h.

#define R150 LCD_REG_150

Definition at line 295 of file stm32_eval.h.

#define R151 LCD_REG_151

Definition at line 296 of file stm32_eval.h.

#define R152 LCD_REG_152

Definition at line 297 of file stm32_eval.h.

#define R153 LCD_REG_153

Definition at line 298 of file stm32_eval.h.

#define R154 LCD_REG_154

Definition at line 299 of file stm32_eval.h.

#define R157 LCD_REG_157

Definition at line 300 of file stm32_eval.h.

#define R16 LCD_REG_16

Definition at line 211 of file stm32_eval.h.

#define R17 LCD_REG_17

Definition at line 212 of file stm32_eval.h.

#define R18 LCD_REG_18

Definition at line 213 of file stm32_eval.h.

#define R19 LCD_REG_19

Definition at line 214 of file stm32_eval.h.

#define R192 LCD_REG_192

Definition at line 301 of file stm32_eval.h.

#define R193 LCD_REG_193

Definition at line 302 of file stm32_eval.h.

#define R2 LCD_REG_2

Definition at line 198 of file stm32_eval.h.

#define R20 LCD_REG_20

Definition at line 215 of file stm32_eval.h.

#define R21 LCD_REG_21

Definition at line 216 of file stm32_eval.h.

#define R22 LCD_REG_22

Definition at line 217 of file stm32_eval.h.

#define R227 LCD_REG_227

Definition at line 303 of file stm32_eval.h.

#define R229 LCD_REG_229

Definition at line 304 of file stm32_eval.h.

#define R23 LCD_REG_23

Definition at line 218 of file stm32_eval.h.

#define R231 LCD_REG_231

Definition at line 305 of file stm32_eval.h.

#define R239 LCD_REG_239

Definition at line 306 of file stm32_eval.h.

#define R24 LCD_REG_24

Definition at line 219 of file stm32_eval.h.

#define R25 LCD_REG_25

Definition at line 220 of file stm32_eval.h.

#define R26 LCD_REG_26

Definition at line 221 of file stm32_eval.h.

#define R27 LCD_REG_27

Definition at line 222 of file stm32_eval.h.

#define R28 LCD_REG_28

Definition at line 223 of file stm32_eval.h.

#define R29 LCD_REG_29

Definition at line 224 of file stm32_eval.h.

#define R3 LCD_REG_3

Definition at line 199 of file stm32_eval.h.

#define R30 LCD_REG_30

Definition at line 225 of file stm32_eval.h.

#define R31 LCD_REG_31

Definition at line 226 of file stm32_eval.h.

#define R32 LCD_REG_32

Definition at line 227 of file stm32_eval.h.

#define R33 LCD_REG_33

Definition at line 228 of file stm32_eval.h.

#define R34 LCD_REG_34

Definition at line 229 of file stm32_eval.h.

#define R36 LCD_REG_36

Definition at line 230 of file stm32_eval.h.

#define R37 LCD_REG_37

Definition at line 231 of file stm32_eval.h.

#define R4 LCD_REG_4

Definition at line 200 of file stm32_eval.h.

#define R40 LCD_REG_40

Definition at line 232 of file stm32_eval.h.

#define R41 LCD_REG_41

Definition at line 233 of file stm32_eval.h.

#define R43 LCD_REG_43

Definition at line 234 of file stm32_eval.h.

#define R45 LCD_REG_45

Definition at line 235 of file stm32_eval.h.

#define R48 LCD_REG_48

Definition at line 236 of file stm32_eval.h.

#define R49 LCD_REG_49

Definition at line 237 of file stm32_eval.h.

#define R5 LCD_REG_5

Definition at line 201 of file stm32_eval.h.

#define R50 LCD_REG_50

Definition at line 238 of file stm32_eval.h.

#define R51 LCD_REG_51

Definition at line 239 of file stm32_eval.h.

#define R52 LCD_REG_52

Definition at line 240 of file stm32_eval.h.

#define R53 LCD_REG_53

Definition at line 241 of file stm32_eval.h.

#define R54 LCD_REG_54

Definition at line 242 of file stm32_eval.h.

#define R55 LCD_REG_55

Definition at line 243 of file stm32_eval.h.

#define R56 LCD_REG_56

Definition at line 244 of file stm32_eval.h.

#define R57 LCD_REG_57

Definition at line 245 of file stm32_eval.h.

#define R59 LCD_REG_59

Definition at line 246 of file stm32_eval.h.

#define R6 LCD_REG_6

Definition at line 202 of file stm32_eval.h.

#define R60 LCD_REG_60

Definition at line 247 of file stm32_eval.h.

#define R61 LCD_REG_61

Definition at line 248 of file stm32_eval.h.

#define R62 LCD_REG_62

Definition at line 249 of file stm32_eval.h.

#define R63 LCD_REG_63

Definition at line 250 of file stm32_eval.h.

#define R64 LCD_REG_64

Definition at line 251 of file stm32_eval.h.

#define R65 LCD_REG_65

Definition at line 252 of file stm32_eval.h.

#define R66 LCD_REG_66

Definition at line 253 of file stm32_eval.h.

#define R67 LCD_REG_67

Definition at line 254 of file stm32_eval.h.

#define R68 LCD_REG_68

Definition at line 255 of file stm32_eval.h.

#define R69 LCD_REG_69

Definition at line 256 of file stm32_eval.h.

#define R7 LCD_REG_7

Definition at line 203 of file stm32_eval.h.

#define R70 LCD_REG_70

Definition at line 257 of file stm32_eval.h.

#define R71 LCD_REG_71

Definition at line 258 of file stm32_eval.h.

#define R72 LCD_REG_72

Definition at line 259 of file stm32_eval.h.

#define R73 LCD_REG_73

Definition at line 260 of file stm32_eval.h.

#define R74 LCD_REG_74

Definition at line 261 of file stm32_eval.h.

#define R75 LCD_REG_75

Definition at line 262 of file stm32_eval.h.

#define R76 LCD_REG_76

Definition at line 263 of file stm32_eval.h.

#define R77 LCD_REG_77

Definition at line 264 of file stm32_eval.h.

#define R78 LCD_REG_78

Definition at line 265 of file stm32_eval.h.

#define R79 LCD_REG_79

Definition at line 266 of file stm32_eval.h.

#define R8 LCD_REG_8

Definition at line 204 of file stm32_eval.h.

#define R80 LCD_REG_80

Definition at line 267 of file stm32_eval.h.

#define R81 LCD_REG_81

Definition at line 268 of file stm32_eval.h.

#define R82 LCD_REG_82

Definition at line 269 of file stm32_eval.h.

#define R83 LCD_REG_83

Definition at line 270 of file stm32_eval.h.

#define R9 LCD_REG_9

Definition at line 205 of file stm32_eval.h.

#define R96 LCD_REG_96

Definition at line 271 of file stm32_eval.h.

#define R97 LCD_REG_97

Definition at line 272 of file stm32_eval.h.

#define Red LCD_COLOR_RED

Definition at line 312 of file stm32_eval.h.

Referenced by main().

#define Vertical LCD_DIR_VERTICAL

Definition at line 328 of file stm32_eval.h.

#define White LCD_COLOR_WHITE

Definition at line 307 of file stm32_eval.h.

Referenced by main().

#define Yellow LCD_COLOR_YELLOW

Definition at line 316 of file stm32_eval.h.

Referenced by main().


STM32F10x Standard Peripherals Firmware Library: STM32_EVAL_Exported_Macros

STM32_EVAL_Exported_Macros

STM32_EVAL_Abstraction_Layer


STM32F10x Standard Peripherals Firmware Library: STM32_EVAL_Exported_Functions

STM32_EVAL_Exported_Functions

STM32_EVAL_Abstraction_Layer


STM32F10x Standard Peripherals Firmware Library: FONTS_Private_Types

FONTS_Private_Types

FONTS


STM32F10x Standard Peripherals Firmware Library: FONTS_Private_Defines

FONTS_Private_Defines

FONTS


STM32F10x Standard Peripherals Firmware Library: FONTS_Private_Macros

FONTS_Private_Macros

FONTS


STM32F10x Standard Peripherals Firmware Library: FONTS_Private_Variables

Variables

FONTS_Private_Variables

FONTS

Variables

const uint16_t | ASCII12x12_Table []
const uint16_t | ASCII16x24_Table []
const uint16_t | ASCII8x12_Table []
const uint16_t | ASCII8x8_Table []
sFONT Font12x12
sFONT Font16x24
sFONT Font8x12
sFONT Font8x8

Variable Documentation

const uint16_t ASCII12x12_Table[]

Definition at line 641 of file fonts.c.

const uint16_t ASCII16x24_Table[]

Definition at line 69 of file fonts.c.

const uint16_t ASCII8x12_Table[]

Definition at line 739 of file fonts.c.

const uint16_t ASCII8x8_Table[]

Definition at line 837 of file fonts.c.

sFONT Font12x12
Initial value:
 {
  ASCII12x12_Table,
  12,
  12,
}

Definition at line 942 of file fonts.c.

Referenced by main().

sFONT Font16x24
Initial value:
 {
  ASCII16x24_Table,
  16,
  24,
}

Definition at line 936 of file fonts.c.

Referenced by main().

sFONT Font8x12
Initial value:
 {
  ASCII8x12_Table,
  8,
  12,
}

Definition at line 948 of file fonts.c.

sFONT Font8x8
Initial value:
 {
  ASCII8x8_Table,
  8,
  8,
}

Definition at line 955 of file fonts.c.


STM32F10x Standard Peripherals Firmware Library: FONTS_Private_Function_Prototypes

FONTS_Private_Function_Prototypes

FONTS


STM32F10x Standard Peripherals Firmware Library: FONTS_Private_Functions

FONTS_Private_Functions

FONTS


STM32F10x Standard Peripherals Firmware Library: FONTS_Exported_Types

Data Structures | Typedefs | Variables

FONTS_Exported_Types

FONTS

Data Structures

struct | _tFont

Typedefs

typedef struct _tFont | sFONT

Variables

sFONT Font12x12
sFONT Font16x24
sFONT Font8x12
sFONT Font8x8

Typedef Documentation

typedef struct _tFont sFONT

Variable Documentation

sFONT Font12x12

Definition at line 942 of file fonts.c.

Referenced by main().

sFONT Font16x24

Definition at line 936 of file fonts.c.

Referenced by main().

sFONT Font8x12

Definition at line 948 of file fonts.c.

sFONT Font8x8

Definition at line 955 of file fonts.c.


STM32F10x Standard Peripherals Firmware Library: _tFont Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

_tFont Struct Reference
FONTS_Exported_Types

#include <fonts.h>

Data Fields

uint16_t | Height
const uint16_t * | table
uint16_t | Width

Detailed Description

Definition at line 52 of file fonts.h.

Field Documentation

uint16_t _tFont::Height

Definition at line 56 of file fonts.h.

Referenced by LCD_DisplayChar(), and LCD_DrawChar().

const uint16_t* _tFont::table

Definition at line 54 of file fonts.h.

Referenced by LCD_DisplayChar().

uint16_t _tFont::Width

Definition at line 55 of file fonts.h.

Referenced by LCD_ClearLine(), LCD_DisplayStringLine(), and LCD_DrawChar().

The documentation for this struct was generated from the following file:
  • fonts.h


STM32F10x Standard Peripherals Firmware Library: FONTS_Exported_Constants

Defines

FONTS_Exported_Constants

FONTS

Defines

#define LINE(x) ((x) * (((sFONT *)LCD_GetFont())->Height))

Define Documentation

#define LINE ( x ) ((x) * (((sFONT *)LCD_GetFont())->Height))

Definition at line 72 of file fonts.h.


STM32F10x Standard Peripherals Firmware Library: FONTS_Exported_Macros

FONTS_Exported_Macros

FONTS


STM32F10x Standard Peripherals Firmware Library: FONTS_Exported_Functions

FONTS_Exported_Functions

FONTS


STM32F10x Standard Peripherals Firmware Library: STM32_EVAL_I2C_EE_Private_Types

STM32_EVAL_I2C_EE_Private_Types

STM32_EVAL_I2C_EE


STM32F10x Standard Peripherals Firmware Library: STM32_EVAL_I2C_EE_Private_Defines

STM32_EVAL_I2C_EE_Private_Defines

STM32_EVAL_I2C_EE


STM32F10x Standard Peripherals Firmware Library: STM32_EVAL_I2C_EE_Private_Macros

STM32_EVAL_I2C_EE_Private_Macros

STM32_EVAL_I2C_EE


STM32F10x Standard Peripherals Firmware Library: STM32_EVAL_I2C_EE_Private_Variables

Variables

STM32_EVAL_I2C_EE_Private_Variables

STM32_EVAL_I2C_EE

Variables

__IO uint16_t | sEEAddress = 0
__IO uint8_t | sEEDataNum
__IO uint16_t * | sEEDataReadPointer
__IO uint8_t * | sEEDataWritePointer
__IO uint32_t | sEETimeout = sEE_LONG_TIMEOUT

Variable Documentation

__IO uint16_t sEEAddress = 0

Definition at line 110 of file stm32_eval_i2c_ee.c.

Referenced by sEE_Init(), sEE_ReadBuffer(), sEE_WaitEepromStandbyState(), and sEE_WritePage().

__IO uint8_t sEEDataNum

Definition at line 114 of file stm32_eval_i2c_ee.c.

Referenced by sEE_WriteBuffer().

__IO uint16_t* sEEDataReadPointer

Definition at line 112 of file stm32_eval_i2c_ee.c.

Referenced by sEE_I2C_DMA_RX_IRQHandler(), and sEE_ReadBuffer().

__IO uint8_t* sEEDataWritePointer

Definition at line 113 of file stm32_eval_i2c_ee.c.

Referenced by sEE_I2C_DMA_TX_IRQHandler(), and sEE_WritePage().

__IO uint32_t sEETimeout = sEE_LONG_TIMEOUT

Definition at line 111 of file stm32_eval_i2c_ee.c.

Referenced by sEE_I2C_DMA_TX_IRQHandler(), sEE_ReadBuffer(), sEE_WaitEepromStandbyState(), sEE_WriteBuffer(), and sEE_WritePage().


STM32F10x Standard Peripherals Firmware Library: STM32_EVAL_I2C_EE_Private_Function_Prototypes

STM32_EVAL_I2C_EE_Private_Function_Prototypes

STM32_EVAL_I2C_EE


STM32F10x Standard Peripherals Firmware Library: STM32_EVAL_I2C_EE_Private_Functions

Functions

STM32_EVAL_I2C_EE_Private_Functions

STM32_EVAL_I2C_EE

Functions

void | sEE_DeInit (void)
DeInitializes peripherals used by the I2C EEPROM driver.
void | sEE_EnterCriticalSection_UserCallback (void)
Start critical section: these callbacks should be typically used to disable interrupts when entering a critical section of I2C communication You may use default callbacks provided into this driver by uncommenting the define USE_DEFAULT_CRITICAL_CALLBACK.
void | sEE_ExitCriticalSection_UserCallback (void)
Start and End of critical section: these callbacks should be typically used to re-enable interrupts when exiting a critical section of I2C communication You may use default callbacks provided into this driver by uncommenting the define USE_DEFAULT_CRITICAL_CALLBACK.
void | sEE_I2C_DMA_RX_IRQHandler (void)
This function handles the DMA Rx Channel interrupt Handler.
void | sEE_I2C_DMA_TX_IRQHandler (void)
This function handles the DMA Tx Channel interrupt Handler.
void | sEE_Init (void)
Initializes peripherals used by the I2C EEPROM driver.
uint32_t | sEE_ReadBuffer (uint8_t *pBuffer, uint16_t ReadAddr, uint16_t *NumByteToRead)
Reads a block of data from the EEPROM.
uint32_t | sEE_WaitEepromStandbyState (void)
Wait for EEPROM Standby state.
void | sEE_WriteBuffer (uint8_t *pBuffer, uint16_t WriteAddr, uint16_t NumByteToWrite)
Writes buffer of data to the I2C EEPROM.
uint32_t | sEE_WritePage (uint8_t *pBuffer, uint16_t WriteAddr, uint8_t *NumByteToWrite)
Writes more than one byte to the EEPROM with a single WRITE cycle.

Function Documentation

void sEE_DeInit ( void )

DeInitializes peripherals used by the I2C EEPROM driver.

Parameters:
None
Return values:
None

Definition at line 137 of file stm32_eval_i2c_ee.c.

Referenced by main().

void sEE_EnterCriticalSection_UserCallback ( void )

Start critical section: these callbacks should be typically used to disable interrupts when entering a critical section of I2C communication You may use default callbacks provided into this driver by uncommenting the define USE_DEFAULT_CRITICAL_CALLBACK.

Or you can comment that line and implement these callbacks into your application.

Parameters:
None.
Return values:
None.

Definition at line 813 of file stm32_eval_i2c_ee.c.

Referenced by sEE_ReadBuffer().

void sEE_ExitCriticalSection_UserCallback ( void )

Start and End of critical section: these callbacks should be typically used to re-enable interrupts when exiting a critical section of I2C communication You may use default callbacks provided into this driver by uncommenting the define USE_DEFAULT_CRITICAL_CALLBACK.

Or you can comment that line and implement these callbacks into your application.

Parameters:
None.
Return values:
None.

Definition at line 828 of file stm32_eval_i2c_ee.c.

Referenced by sEE_ReadBuffer().

void sEE_I2C_DMA_RX_IRQHandler ( void )

This function handles the DMA Rx Channel interrupt Handler.

Parameters:
None
Return values:
None

< Send STOP Condition

Definition at line 770 of file stm32_eval_i2c_ee.c.

References DISABLE, DMA_ClearFlag(), DMA_Cmd(), DMA_GetFlagStatus(), ENABLE, I2C_GenerateSTOP(), RESET, sEE_I2C, sEE_I2C_DMA_CHANNEL_RX, sEE_I2C_DMA_FLAG_RX_GL, sEE_I2C_DMA_FLAG_RX_TC, and sEEDataReadPointer.

void sEE_I2C_DMA_TX_IRQHandler ( void )

This function handles the DMA Tx Channel interrupt Handler.

Parameters:
None
Return values:
None

< Wait till all data have been physically transferred on the bus

Definition at line 737 of file stm32_eval_i2c_ee.c.

References DISABLE, DMA_ClearFlag(), DMA_Cmd(), DMA_GetFlagStatus(), ENABLE, I2C_FLAG_BTF, I2C_GenerateSTOP(), I2C_GetFlagStatus(), RESET, sEE_I2C, sEE_I2C_DMA_CHANNEL_TX, sEE_I2C_DMA_FLAG_TX_GL, sEE_I2C_DMA_FLAG_TX_TC, sEE_LONG_TIMEOUT, sEE_TIMEOUT_UserCallback(), sEEDataWritePointer, and sEETimeout.

void sEE_Init ( void )

Initializes peripherals used by the I2C EEPROM driver.

Parameters:
None
Return values:
None

< I2C configuration

< Select the EEPROM address according to the state of E0, E1, E2 pins

< sEE_M24C64_32

Definition at line 147 of file stm32_eval_i2c_ee.c.

Referenced by main().

uint32_t sEE_ReadBuffer | ( | uint8_t * | pBuffer,
 |  | uint16_t | ReadAddr,
 |  | uint16_t * | NumByteToRead
 | ) |  |

Reads a block of data from the EEPROM.

Parameters:
pBuffer | : pointer to the buffer that receives the data read from the EEPROM.
ReadAddr | : EEPROM's internal address to start reading from.
NumByteToRead | : pointer to the variable holding number of bytes to be read from the EEPROM.
Note:
The variable pointed by NumByteToRead is reset to 0 when all the data are read from the EEPROM. Application should monitor this variable in order know when the transfer is complete.
When number of data to be read is higher than 1, this function just configures the communication and enable the DMA channel to transfer data. Meanwhile, the user application may perform other tasks. When number of data to be read is 1, then the DMA is not used. The byte is read in polling mode.
Return values:
sEE_OK (0) if operation is correctly performed, else return value different from sEE_OK (0) or the timeout user callback.

< While the bus is busy

< Test on EV5 and clear it (cleared by reading SR1 then writing to DR)

< Test on EV6 and clear it

< Test on EV8 and clear it

< sEE_M24C08

< Test on EV8 and clear it

< Test on EV5 and clear it (cleared by reading SR1 then writing to DR)

< Send STOP Condition

< Decrement the read bytes counter

< Test on EV6 and clear it

Definition at line 218 of file stm32_eval_i2c_ee.c.

Referenced by main().

uint32_t sEE_WaitEepromStandbyState ( void )

Wait for EEPROM Standby state.

Note:
This function allows to wait and check that EEPROM has finished the last Write operation. It is mostly used after Write operation: after receiving the buffer to be written, the EEPROM may need additional time to actually perform the write operation. During this time, it doesn't answer to I2C packets addressed to it. Once the write operation is complete the EEPROM responds to its address.
It is not necessary to call this function after sEE_WriteBuffer() function (sEE_WriteBuffer() already calls this function after each write page operation).
Parameters:
None
Return values:
sEE_OK (0) if operation is correctly performed, else return value different from sEE_OK (0) or the timeout user callback.

< While the bus is busy

< Send START condition

< Test on EV5 and clear it

< STOP condition

< Clear AF flag

Definition at line 660 of file stm32_eval_i2c_ee.c.

Referenced by sEE_WriteBuffer().

void sEE_WriteBuffer | ( | uint8_t * | pBuffer,
 |  | uint16_t | WriteAddr,
 |  | uint16_t | NumByteToWrite
 | ) |  |

Writes buffer of data to the I2C EEPROM.

Parameters:
pBuffer | : pointer to the buffer containing the data to be written to the EEPROM.
WriteAddr | : EEPROM's internal address to write to.
NumByteToWrite | : number of bytes to write to the EEPROM.
Return values:
None

< If WriteAddr is sEE_PAGESIZE aligned

< If NumByteToWrite < sEE_PAGESIZE

< If NumByteToWrite < sEE_PAGESIZE

< If the number of data to be written is more than the remaining space in the current page:

< Write the data conained in same page

< Write the remaining data in the following page

Definition at line 477 of file stm32_eval_i2c_ee.c.

Referenced by main().

uint32_t sEE_WritePage | ( | uint8_t * | pBuffer,
 |  | uint16_t | WriteAddr,
 |  | uint8_t * | NumByteToWrite
 | ) |  |

Writes more than one byte to the EEPROM with a single WRITE cycle.

Note:
The number of bytes (combined to write start address) must not cross the EEPROM page boundary. This function can only write into the boundaries of an EEPROM page. This function doesn't check on boundaries condition (in this driver the function sEE_WriteBuffer() which calls sEE_WritePage() is responsible of checking on Page boundaries).
Parameters:
pBuffer | : pointer to the buffer containing the data to be written to the EEPROM.
WriteAddr | : EEPROM's internal address to write to.
NumByteToWrite | : pointer to the variable holding number of bytes to be written into the EEPROM.
Note:
The variable pointed by NumByteToWrite is reset to 0 when all the data are written to the EEPROM. Application should monitor this variable in order know when the transfer is complete.
This function just configure the communication and enable the DMA channel to transfer data. Meanwhile, the user application may perform other tasks in parallel.
Return values:
sEE_OK (0) if operation is correctly performed, else return value different from sEE_OK (0) or the timeout user callback.

< While the bus is busy

< Test on EV5 and clear it

< Test on EV6 and clear it

< Test on EV8 and clear it

< sEE_M24C08

< Test on EV8 and clear it

Definition at line 394 of file stm32_eval_i2c_ee.c.

Referenced by sEE_WriteBuffer().


STM32F10x Standard Peripherals Firmware Library: STM32_EVAL_I2C_EE_Exported_Types

STM32_EVAL_I2C_EE_Exported_Types

STM32_EVAL_I2C_EE


STM32F10x Standard Peripherals Firmware Library: STM32_EVAL_I2C_EE_Exported_Constants

Defines

STM32_EVAL_I2C_EE_Exported_Constants

STM32_EVAL_I2C_EE

Defines

#define | I2C_SLAVE_ADDRESS7 0xA0
#define | I2C_SPEED 300000
#define | sEE_FAIL 1
#define | sEE_FLAG_TIMEOUT ((uint32_t)0x1000)
#define | sEE_HW_ADDRESS 0xA0
#define | sEE_LONG_TIMEOUT ((uint32_t)(10 * sEE_FLAG_TIMEOUT))
#define | sEE_M24C64_32
#define | sEE_MAX_TRIALS_NUMBER 150
#define | sEE_OK 0
#define | sEE_PAGESIZE 32
#define | sEE_STATE_BUSY 1
#define | sEE_STATE_ERROR 2
#define | sEE_STATE_READY 0
#define | USE_DEFAULT_CRITICAL_CALLBACK

Define Documentation

#define I2C_SLAVE_ADDRESS7 0xA0

Definition at line 105 of file stm32_eval_i2c_ee.h.

Referenced by sEE_Init().

#define I2C_SPEED 300000

Definition at line 104 of file stm32_eval_i2c_ee.h.

Referenced by sEE_Init().

#define sEE_FAIL 1

Definition at line 130 of file stm32_eval_i2c_ee.h.

#define sEE_FLAG_TIMEOUT ((uint32_t)0x1000)

Definition at line 118 of file stm32_eval_i2c_ee.h.

Referenced by sEE_ReadBuffer(), sEE_WaitEepromStandbyState(), and sEE_WritePage().

#define sEE_HW_ADDRESS 0xA0

Definition at line 92 of file stm32_eval_i2c_ee.h.

Referenced by sEE_Init().

#define sEE_LONG_TIMEOUT ((uint32_t)(10 * sEE_FLAG_TIMEOUT))

Definition at line 119 of file stm32_eval_i2c_ee.h.

Referenced by sEE_I2C_DMA_TX_IRQHandler(), sEE_ReadBuffer(), sEE_WaitEepromStandbyState(), sEE_WriteBuffer(), and sEE_WritePage().

#define sEE_M24C64_32

Definition at line 84 of file stm32_eval_i2c_ee.h.

#define sEE_MAX_TRIALS_NUMBER 150

Definition at line 122 of file stm32_eval_i2c_ee.h.

Referenced by sEE_WaitEepromStandbyState().

#define sEE_OK 0

Definition at line 129 of file stm32_eval_i2c_ee.h.

Referenced by sEE_ReadBuffer(), sEE_WaitEepromStandbyState(), and sEE_WritePage().

#define sEE_PAGESIZE 32

Definition at line 110 of file stm32_eval_i2c_ee.h.

Referenced by sEE_WriteBuffer().

#define sEE_STATE_BUSY 1

Definition at line 126 of file stm32_eval_i2c_ee.h.

#define sEE_STATE_ERROR 2

Definition at line 127 of file stm32_eval_i2c_ee.h.

#define sEE_STATE_READY 0

Definition at line 125 of file stm32_eval_i2c_ee.h.

#define USE_DEFAULT_CRITICAL_CALLBACK

Definition at line 64 of file stm32_eval_i2c_ee.h.


STM32F10x Standard Peripherals Firmware Library: STM32_EVAL_I2C_EE_Exported_Macros

STM32_EVAL_I2C_EE_Exported_Macros

STM32_EVAL_I2C_EE


STM32F10x Standard Peripherals Firmware Library: STM32_EVAL_I2C_EE_Exported_Functions

Functions

STM32_EVAL_I2C_EE_Exported_Functions

STM32_EVAL_I2C_EE

Functions

void | sEE_DeInit (void)
DeInitializes peripherals used by the I2C EEPROM driver.
void | sEE_EnterCriticalSection_UserCallback (void)
Start critical section: these callbacks should be typically used to disable interrupts when entering a critical section of I2C communication You may use default callbacks provided into this driver by uncommenting the define USE_DEFAULT_CRITICAL_CALLBACK.
void | sEE_ExitCriticalSection_UserCallback (void)
Start and End of critical section: these callbacks should be typically used to re-enable interrupts when exiting a critical section of I2C communication You may use default callbacks provided into this driver by uncommenting the define USE_DEFAULT_CRITICAL_CALLBACK.
void | sEE_Init (void)
Initializes peripherals used by the I2C EEPROM driver.
uint32_t | sEE_ReadBuffer (uint8_t *pBuffer, uint16_t ReadAddr, uint16_t *NumByteToRead)
Reads a block of data from the EEPROM.
uint32_t | sEE_TIMEOUT_UserCallback (void)
Example of timeout situation management.
uint32_t | sEE_WaitEepromStandbyState (void)
Wait for EEPROM Standby state.
void | sEE_WriteBuffer (uint8_t *pBuffer, uint16_t WriteAddr, uint16_t NumByteToWrite)
Writes buffer of data to the I2C EEPROM.
uint32_t | sEE_WritePage (uint8_t *pBuffer, uint16_t WriteAddr, uint8_t *NumByteToWrite)
Writes more than one byte to the EEPROM with a single WRITE cycle.

Function Documentation

void sEE_DeInit ( void )

DeInitializes peripherals used by the I2C EEPROM driver.

Parameters:
None
Return values:
None

Definition at line 137 of file stm32_eval_i2c_ee.c.

void sEE_EnterCriticalSection_UserCallback ( void )

Start critical section: these callbacks should be typically used to disable interrupts when entering a critical section of I2C communication You may use default callbacks provided into this driver by uncommenting the define USE_DEFAULT_CRITICAL_CALLBACK.

Or you can comment that line and implement these callbacks into your application.

Parameters:
None.
Return values:
None.

Definition at line 813 of file stm32_eval_i2c_ee.c.

Referenced by sEE_ReadBuffer().

void sEE_ExitCriticalSection_UserCallback ( void )

Start and End of critical section: these callbacks should be typically used to re-enable interrupts when exiting a critical section of I2C communication You may use default callbacks provided into this driver by uncommenting the define USE_DEFAULT_CRITICAL_CALLBACK.

Or you can comment that line and implement these callbacks into your application.

Parameters:
None.
Return values:
None.

Definition at line 828 of file stm32_eval_i2c_ee.c.

Referenced by sEE_ReadBuffer().

void sEE_Init ( void )

Initializes peripherals used by the I2C EEPROM driver.

Parameters:
None
Return values:
None

< I2C configuration

< Select the EEPROM address according to the state of E0, E1, E2 pins

< sEE_M24C64_32

< I2C configuration

< sEE_M24C64_32

Definition at line 147 of file stm32_eval_i2c_ee.c.

uint32_t sEE_ReadBuffer | ( | uint8_t * | pBuffer,
 |  | uint16_t | ReadAddr,
 |  | uint16_t * | NumByteToRead
 | ) |  |

Reads a block of data from the EEPROM.

Parameters:
pBuffer | : pointer to the buffer that receives the data read from the EEPROM.
ReadAddr | : EEPROM's internal address to start reading from.
NumByteToRead | : pointer to the variable holding number of bytes to be read from the EEPROM.
Note:
The variable pointed by NumByteToRead is reset to 0 when all the data are read from the EEPROM. Application should monitor this variable in order know when the transfer is complete.
When number of data to be read is higher than 1, this function just configures the communication and enable the DMA channel to transfer data. Meanwhile, the user application may perform other tasks. When number of data to be read is 1, then the DMA is not used. The byte is read in polling mode.
Return values:
sEE_OK (0) if operation is correctly performed, else return value different from sEE_OK (0) or the timeout user callback.

< While the bus is busy

< Test on EV5 and clear it (cleared by reading SR1 then writing to DR)

< Test on EV6 and clear it

< Test on EV8 and clear it

< sEE_M24C08

< Test on EV8 and clear it

< Test on EV5 and clear it (cleared by reading SR1 then writing to DR)

< Send STOP Condition

< Decrement the read bytes counter

< Test on EV6 and clear it

< While the bus is busy

< Test on EV5 and clear it (cleared by reading SR1 then writing to DR)

< Test on EV6 and clear it

< Test on EV8 and clear it

< Test on EV5 and clear it (cleared by reading SR1 then writing to DR)

< Send STOP Condition

< Decrement the read bytes counter

< Test on EV6 and clear it

Definition at line 218 of file stm32_eval_i2c_ee.c.

uint32_t sEE_TIMEOUT_UserCallback ( void )

Example of timeout situation management.

Parameters:
None.
Return values:
None.

Definition at line 267 of file STM32F10x_StdPeriph_Examples/I2C/EEPROM/main.c.

uint32_t sEE_WaitEepromStandbyState ( void )

Wait for EEPROM Standby state.

Note:
This function allows to wait and check that EEPROM has finished the last Write operation. It is mostly used after Write operation: after receiving the buffer to be written, the EEPROM may need additional time to actually perform the write operation. During this time, it doesn't answer to I2C packets addressed to it. Once the write operation is complete the EEPROM responds to its address.
It is not necessary to call this function after sEE_WriteBuffer() function (sEE_WriteBuffer() already calls this function after each write page operation).
Parameters:
None
Return values:
sEE_OK (0) if operation is correctly performed, else return value different from sEE_OK (0) or the timeout user callback.
Note:
This function allows to wait and check that EEPROM has finished the last operation. It is mostly used after Write operation: after receiving the buffer to be written, the EEPROM may need additional time to actually perform the write operation. During this time, it doesn't answer to I2C packets addressed to it. Once the write operation is complete the EEPROM responds to its address.
Parameters:
None
Return values:
sEE_OK (0) if operation is correctly performed, else return value different from sEE_OK (0) or the timeout user callback.

< While the bus is busy

< Send START condition

< Test on EV5 and clear it

< STOP condition

< Clear AF flag

< While the bus is busy

< Send START condition

< Test on EV5 and clear it

< STOP condition

< Clear AF flag

Definition at line 660 of file stm32_eval_i2c_ee.c.

void sEE_WriteBuffer | ( | uint8_t * | pBuffer,
 |  | uint16_t | WriteAddr,
 |  | uint16_t | NumByteToWrite
 | ) |  |

Writes buffer of data to the I2C EEPROM.

Parameters:
pBuffer | : pointer to the buffer containing the data to be written to the EEPROM.
WriteAddr | : EEPROM's internal address to write to.
NumByteToWrite | : number of bytes to write to the EEPROM.
Return values:
None

< If WriteAddr is sEE_PAGESIZE aligned

< If NumByteToWrite < sEE_PAGESIZE

< If NumByteToWrite < sEE_PAGESIZE

< If the number of data to be written is more than the remaining space in the current page:

< Write the data conained in same page

< Write the remaining data in the following page

< If WriteAddr is sEE_PAGESIZE aligned

< If NumByteToWrite < sEE_PAGESIZE

< If NumByteToWrite < sEE_PAGESIZE

< If the number of data to be written is more than the remaining space in the current page:

< Write the data conained in same page

< Write the remaining data in the following page

Definition at line 477 of file stm32_eval_i2c_ee.c.

uint32_t sEE_WritePage | ( | uint8_t * | pBuffer,
 |  | uint16_t | WriteAddr,
 |  | uint8_t * | NumByteToWrite
 | ) |  |

Writes more than one byte to the EEPROM with a single WRITE cycle.

Note:
The number of bytes (combined to write start address) must not cross the EEPROM page boundary. This function can only write into the boundaries of an EEPROM page. This function doesn't check on boundaries condition (in this driver the function sEE_WriteBuffer() which calls sEE_WritePage() is responsible of checking on Page boundaries).
Parameters:
pBuffer | : pointer to the buffer containing the data to be written to the EEPROM.
WriteAddr | : EEPROM's internal address to write to.
NumByteToWrite | : pointer to the variable holding number of bytes to be written into the EEPROM.
Note:
The variable pointed by NumByteToWrite is reset to 0 when all the data are written to the EEPROM. Application should monitor this variable in order know when the transfer is complete.
This function just configure the communication and enable the DMA channel to transfer data. Meanwhile, the user application may perform other tasks in parallel.
Return values:
sEE_OK (0) if operation is correctly performed, else return value different from sEE_OK (0) or the timeout user callback.

< While the bus is busy

< Test on EV5 and clear it

< Test on EV6 and clear it

< Test on EV8 and clear it

< sEE_M24C08

< Test on EV8 and clear it

< While the bus is busy

< Test on EV5 and clear it

< Test on EV6 and clear it

< Test on EV8 and clear it

Definition at line 394 of file stm32_eval_i2c_ee.c.


STM32F10x Standard Peripherals Firmware Library: STM32_EVAL_I2C_TSENSOR_Private_Types

STM32_EVAL_I2C_TSENSOR_Private_Types

STM32_EVAL_I2C_TSENSOR


STM32F10x Standard Peripherals Firmware Library: STM32_EVAL_I2C_TSENSOR_Private_Defines

Defines

STM32_EVAL_I2C_TSENSOR_Private_Defines

STM32_EVAL_I2C_TSENSOR

Defines

#define | LM75_SD_RESET 0xFE
#define | LM75_SD_SET 0x01

Define Documentation

#define LM75_SD_RESET 0xFE

Reset SD bit in the configuration register

Definition at line 85 of file stm32_eval_i2c_tsensor.c.

Referenced by LM75_ShutDown().

#define LM75_SD_SET 0x01

Set SD bit in the configuration register

Definition at line 84 of file stm32_eval_i2c_tsensor.c.

Referenced by LM75_ShutDown().


STM32F10x Standard Peripherals Firmware Library: STM32_EVAL_I2C_TSENSOR_Private_Macros

STM32_EVAL_I2C_TSENSOR_Private_Macros

STM32_EVAL_I2C_TSENSOR


STM32F10x Standard Peripherals Firmware Library: STM32_EVAL_I2C_TSENSOR_Private_Variables

Variables

STM32_EVAL_I2C_TSENSOR_Private_Variables

STM32_EVAL_I2C_TSENSOR

Variables

__IO uint32_t LM75_Timeout = LM75_LONG_TIMEOUT

Variable Documentation

__IO uint32_t LM75_Timeout = LM75_LONG_TIMEOUT

Definition at line 101 of file stm32_eval_i2c_tsensor.c.

Referenced by LM75_ReadConfReg(), LM75_ReadReg(), LM75_ReadTemp(), LM75_ShutDown(), LM75_WriteConfReg(), and LM75_WriteReg().


STM32F10x Standard Peripherals Firmware Library: STM32_EVAL_I2C_TSENSOR_Private_Function_Prototypes

STM32_EVAL_I2C_TSENSOR_Private_Function_Prototypes

STM32_EVAL_I2C_TSENSOR


STM32F10x Standard Peripherals Firmware Library: STM32_EVAL_I2C_TSENSOR_Private_Functions

Functions

STM32_EVAL_I2C_TSENSOR_Private_Functions

STM32_EVAL_I2C_TSENSOR

Functions

void | LM75_DeInit (void)
DeInitializes the LM75_I2C.
static void | LM75_DMA_Config (LM75_DMADirection_TypeDef Direction, uint8_t *buffer, uint8_t NumData)
Configure the DMA Peripheral used to handle communication via I2C.
ErrorStatus | LM75_GetStatus (void)
Checks the LM75 status.
void | LM75_Init (void)
Initializes the LM75_I2C.
uint8_t | LM75_ReadConfReg (void)
Read the configuration register from the LM75.
uint16_t | LM75_ReadReg (uint8_t RegName)
Read the specified register from the LM75.
uint16_t | LM75_ReadTemp (void)
Read Temperature register of LM75: double temperature value.
uint8_t | LM75_ShutDown (FunctionalState NewState)
Enables or disables the LM75.
uint8_t | LM75_WriteConfReg (uint8_t RegValue)
Write to the configuration register of the LM75.
uint8_t | LM75_WriteReg (uint8_t RegName, uint16_t RegValue)
Write to the specified register of the LM75.

Function Documentation

void LM75_DeInit ( void )

DeInitializes the LM75_I2C.

Parameters:
None
Return values:
None

Definition at line 125 of file stm32_eval_i2c_tsensor.c.

References LM75_LowLevel_DeInit().

static void LM75_DMA_Config | ( | LM75_DMADirection_TypeDef | Direction,
 |  | uint8_t * | buffer,
 |  | uint8_t | NumData
 | ) |  | [static]

Configure the DMA Peripheral used to handle communication via I2C.

Parameters:
None
Return values:
None

Definition at line 166 of file stm32_eval_i2c_tsensor.c.

References DMA_InitTypeDef::DMA_BufferSize, DMA_DeInit(), DMA_InitTypeDef::DMA_DIR, DMA_DIR_PeripheralDST, DMA_DIR_PeripheralSRC, DMA_Init(), DMA_InitStructure, DMA_InitTypeDef::DMA_M2M, DMA_M2M_Disable, DMA_InitTypeDef::DMA_MemoryBaseAddr, DMA_InitTypeDef::DMA_MemoryDataSize, DMA_MemoryDataSize_Byte, DMA_InitTypeDef::DMA_MemoryInc, DMA_MemoryInc_Enable, DMA_InitTypeDef::DMA_Mode, DMA_Mode_Normal, DMA_InitTypeDef::DMA_PeripheralBaseAddr, DMA_InitTypeDef::DMA_PeripheralDataSize, DMA_PeripheralDataSize_Byte, DMA_InitTypeDef::DMA_PeripheralInc, DMA_PeripheralInc_Disable, DMA_InitTypeDef::DMA_Priority, DMA_Priority_VeryHigh, ENABLE, LM75_DMA_CLK, LM75_DMA_RX, LM75_DMA_RX_CHANNEL, LM75_DMA_TX, LM75_DMA_TX_CHANNEL, LM75_I2C_DR, and RCC_AHBPeriphClockCmd().

Referenced by LM75_ReadConfReg(), LM75_ReadReg(), LM75_ReadTemp(), LM75_ShutDown(), LM75_WriteConfReg(), and LM75_WriteReg().

ErrorStatus LM75_GetStatus ( void )

Checks the LM75 status.

Parameters:
None
Return values:
ErrorStatus,: LM75 Status (ERROR or SUCCESS).

< Clear the LM75_I2C AF flag

< Enable LM75_I2C acknowledgement if it is already disabled by other function

< Send LM75_I2C START condition

< Test on LM75_I2C EV5 and clear it

< EV5

< Send STLM75 slave address for write

Definition at line 225 of file stm32_eval_i2c_tsensor.c.

References ENABLE, ERROR, I2C_AcknowledgeConfig(), I2C_CheckEvent(), I2C_ClearFlag(), I2C_Direction_Transmitter, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED, I2C_FLAG_AF, I2C_FLAG_SB, I2C_GenerateSTART(), I2C_GetFlagStatus(), I2C_Send7bitAddress(), I2C_TIMEOUT, LM75_ADDR, LM75_I2C, and SUCCESS.

Referenced by main().

void LM75_Init ( void )

Initializes the LM75_I2C.

Parameters:
None
Return values:
None

< LM75_I2C Init

< Enable SMBus Alert interrupt

< LM75_I2C Init

Definition at line 135 of file stm32_eval_i2c_tsensor.c.

References ENABLE, I2C_InitTypeDef::I2C_Ack, I2C_Ack_Enable, I2C_InitTypeDef::I2C_AcknowledgedAddress, I2C_AcknowledgedAddress_7bit, I2C_InitTypeDef::I2C_ClockSpeed, I2C_Cmd(), I2C_DeInit(), I2C_InitTypeDef::I2C_DutyCycle, I2C_DutyCycle_2, I2C_Init(), I2C_InitStructure, I2C_IT_ERR, I2C_ITConfig(), I2C_InitTypeDef::I2C_Mode, I2C_Mode_SMBusHost, I2C_InitTypeDef::I2C_OwnAddress1, LM75_I2C, LM75_I2C_SPEED, and LM75_LowLevel_Init().

Referenced by main().

uint8_t LM75_ReadConfReg ( void )

Read the configuration register from the LM75.

Parameters:
None
Return values:
LM75 configuration register value.

< Return Temperature value

Definition at line 580 of file stm32_eval_i2c_tsensor.c.

References DISABLE, DMA_ClearFlag(), DMA_Cmd(), DMA_GetFlagStatus(), ENABLE, I2C_CheckEvent(), I2C_Direction_Receiver, I2C_Direction_Transmitter, I2C_DMACmd(), I2C_DMALastTransferCmd(), I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED, I2C_FLAG_BTF, I2C_FLAG_BUSY, I2C_FLAG_SB, I2C_FLAG_TXE, I2C_GenerateSTART(), I2C_GenerateSTOP(), I2C_GetFlagStatus(), I2C_Send7bitAddress(), I2C_SendData(), LM75_ADDR, LM75_DMA_Config(), LM75_DMA_RX, LM75_DMA_RX_CHANNEL, LM75_DMA_RX_TCFLAG, LM75_FLAG_TIMEOUT, LM75_I2C, LM75_LONG_TIMEOUT, LM75_REG_CONF, LM75_Timeout, and LM75_TIMEOUT_UserCallback.

uint16_t LM75_ReadReg ( uint8_t RegName )

Read the specified register from the LM75.

Parameters:
RegName,: specifies the LM75 register to be read. This member can be one of the following values:

  • LM75_REG_TEMP: temperature register
  • LM75_REG_TOS: Over-limit temperature register
  • LM75_REG_THYS: Hysteresis temperature register
Return values:
LM75 register value.

< Store LM75_I2C received data

Definition at line 278 of file stm32_eval_i2c_tsensor.c.

References DISABLE, DMA_ClearFlag(), DMA_Cmd(), DMA_GetFlagStatus(), ENABLE, I2C_CheckEvent(), I2C_Direction_Receiver, I2C_Direction_Transmitter, I2C_DMACmd(), I2C_DMALastTransferCmd(), I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED, I2C_FLAG_BTF, I2C_FLAG_BUSY, I2C_FLAG_SB, I2C_FLAG_TXE, I2C_GenerateSTART(), I2C_GenerateSTOP(), I2C_GetFlagStatus(), I2C_Send7bitAddress(), I2C_SendData(), LM75_ADDR, LM75_DMA_Config(), LM75_DMA_RX, LM75_DMA_RX_CHANNEL, LM75_DMA_RX_TCFLAG, LM75_FLAG_TIMEOUT, LM75_I2C, LM75_LONG_TIMEOUT, LM75_Timeout, and LM75_TIMEOUT_UserCallback.

uint16_t LM75_ReadTemp ( void )

Read Temperature register of LM75: double temperature value.

Parameters:
None
Return values:
LM75 measured temperature value.

< Store LM75_I2C received data

< Return Temperature value

Definition at line 474 of file stm32_eval_i2c_tsensor.c.

References DISABLE, DMA_ClearFlag(), DMA_Cmd(), DMA_GetFlagStatus(), ENABLE, I2C_CheckEvent(), I2C_Direction_Receiver, I2C_Direction_Transmitter, I2C_DMACmd(), I2C_DMALastTransferCmd(), I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED, I2C_FLAG_BTF, I2C_FLAG_BUSY, I2C_FLAG_SB, I2C_FLAG_TXE, I2C_GenerateSTART(), I2C_GenerateSTOP(), I2C_GetFlagStatus(), I2C_Send7bitAddress(), I2C_SendData(), LM75_ADDR, LM75_DMA_Config(), LM75_DMA_RX, LM75_DMA_RX_CHANNEL, LM75_DMA_RX_TCFLAG, LM75_FLAG_TIMEOUT, LM75_I2C, LM75_LONG_TIMEOUT, LM75_REG_TEMP, LM75_Timeout, and LM75_TIMEOUT_UserCallback.

Referenced by main().

uint8_t LM75_ShutDown ( FunctionalState NewState )

Enables or disables the LM75.

Parameters:
NewState,: specifies the LM75 new status. This parameter can be ENABLE or DISABLE.
Return values:
None

< Get received data

< Enable or disable SD bit

< Enable LM75

< Disable LM75

Definition at line 769 of file stm32_eval_i2c_tsensor.c.

References DISABLE, DMA_ClearFlag(), DMA_Cmd(), DMA_GetFlagStatus(), ENABLE, I2C_CheckEvent(), I2C_Direction_Receiver, I2C_Direction_Transmitter, I2C_DMACmd(), I2C_DMALastTransferCmd(), I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED, I2C_FLAG_BTF, I2C_FLAG_BUSY, I2C_FLAG_SB, I2C_FLAG_TXE, I2C_GenerateSTART(), I2C_GenerateSTOP(), I2C_GetFlagStatus(), I2C_Send7bitAddress(), I2C_SendData(), LM75_ADDR, LM75_DMA_Config(), LM75_DMA_RX, LM75_DMA_RX_CHANNEL, LM75_DMA_RX_TCFLAG, LM75_DMA_TX, LM75_DMA_TX_CHANNEL, LM75_DMA_TX_TCFLAG, LM75_FLAG_TIMEOUT, LM75_I2C, LM75_LONG_TIMEOUT, LM75_OK, LM75_REG_CONF, LM75_SD_RESET, LM75_SD_SET, LM75_Timeout, LM75_TIMEOUT_UserCallback, and RESET.

uint8_t LM75_WriteConfReg ( uint8_t RegValue )

Write to the configuration register of the LM75.

Parameters:
RegValue,: sepecifies the value to be written to LM75 configuration register.
Return values:
None

Definition at line 682 of file stm32_eval_i2c_tsensor.c.

References DISABLE, DMA_ClearFlag(), DMA_Cmd(), DMA_GetFlagStatus(), ENABLE, I2C_CheckEvent(), I2C_Direction_Transmitter, I2C_DMACmd(), I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED, I2C_FLAG_BTF, I2C_FLAG_BUSY, I2C_FLAG_SB, I2C_FLAG_TXE, I2C_GenerateSTART(), I2C_GenerateSTOP(), I2C_GetFlagStatus(), I2C_Send7bitAddress(), I2C_SendData(), LM75_ADDR, LM75_DMA_Config(), LM75_DMA_TX, LM75_DMA_TX_CHANNEL, LM75_DMA_TX_TCFLAG, LM75_FLAG_TIMEOUT, LM75_I2C, LM75_LONG_TIMEOUT, LM75_OK, LM75_REG_CONF, LM75_Timeout, LM75_TIMEOUT_UserCallback, and RESET.

Referenced by main().

uint8_t LM75_WriteReg | ( | uint8_t | RegName,
 |  | uint16_t | RegValue
 | ) |  |

Write to the specified register of the LM75.

Parameters:
RegName,: specifies the LM75 register to be written. This member can be one of the following values:

  • LM75_REG_TOS: Over-limit temperature register
  • LM75_REG_THYS: Hysteresis temperature register
RegValue,: value to be written to LM75 register.
Return values:
None

Definition at line 388 of file stm32_eval_i2c_tsensor.c.

References DISABLE, DMA_ClearFlag(), DMA_Cmd(), DMA_GetFlagStatus(), ENABLE, I2C_CheckEvent(), I2C_Direction_Transmitter, I2C_DMACmd(), I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED, I2C_FLAG_BTF, I2C_FLAG_BUSY, I2C_FLAG_SB, I2C_FLAG_TXE, I2C_GenerateSTART(), I2C_GenerateSTOP(), I2C_GetFlagStatus(), I2C_Send7bitAddress(), I2C_SendData(), LM75_ADDR, LM75_DMA_Config(), LM75_DMA_TX, LM75_DMA_TX_CHANNEL, LM75_DMA_TX_TCFLAG, LM75_FLAG_TIMEOUT, LM75_I2C, LM75_LONG_TIMEOUT, LM75_OK, LM75_Timeout, LM75_TIMEOUT_UserCallback, and RESET.

Referenced by main().


STM32F10x Standard Peripherals Firmware Library: STM32_EVAL_I2C_TSENSOR_Exported_Types

Enumerations

STM32_EVAL_I2C_TSENSOR_Exported_Types

STM32_EVAL_I2C_TSENSOR

Enumerations

enum | LM75_DMADirection_TypeDef { LM75_DMA_TX = 0, LM75_DMA_RX = 1 }

IOE DMA Direction.

More...
enum | LM75_Status_TypDef { LM75_OK = 0, LM75_FAIL }

TSENSOR Status.

More...

Enumeration Type Documentation

enum LM75_DMADirection_TypeDef

IOE DMA Direction.

Enumerator:
LM75_DMA_TX
LM75_DMA_RX

Definition at line 57 of file stm32_eval_i2c_tsensor.h.

enum LM75_Status_TypDef

TSENSOR Status.

Enumerator:
LM75_OK
LM75_FAIL

Definition at line 66 of file stm32_eval_i2c_tsensor.h.


STM32F10x Standard Peripherals Firmware Library: STM32_EVAL_I2C_TSENSOR_Exported_Constants

Defines

STM32_EVAL_I2C_TSENSOR_Exported_Constants

STM32_EVAL_I2C_TSENSOR

Defines

#define | I2C_TIMEOUT ((uint32_t)0x3FFFF)
#define | LM75_ADDR 0x90
#define | LM75_FLAG_TIMEOUT ((uint32_t)0x1000)
#define | LM75_I2C_SPEED 100000
#define | LM75_LONG_TIMEOUT ((uint32_t)(10 * LM75_FLAG_TIMEOUT))
#define | LM75_REG_CONF 0x01
#define | LM75_REG_TEMP 0x00
Block Size.
#define | LM75_REG_THYS 0x02
#define | LM75_REG_TOS 0x03

Define Documentation

#define I2C_TIMEOUT ((uint32_t)0x3FFFF)

I2C Time out

Definition at line 103 of file stm32_eval_i2c_tsensor.h.

Referenced by LM75_GetStatus().

#define LM75_ADDR 0x90

LM75 address

Definition at line 104 of file stm32_eval_i2c_tsensor.h.

Referenced by LM75_GetStatus(), LM75_ReadConfReg(), LM75_ReadReg(), LM75_ReadTemp(), LM75_ShutDown(), LM75_WriteConfReg(), and LM75_WriteReg().

#define LM75_FLAG_TIMEOUT ((uint32_t)0x1000)

Definition at line 92 of file stm32_eval_i2c_tsensor.h.

Referenced by LM75_ReadConfReg(), LM75_ReadReg(), LM75_ReadTemp(), LM75_ShutDown(), LM75_WriteConfReg(), and LM75_WriteReg().

#define LM75_I2C_SPEED 100000

I2C Speed

Definition at line 105 of file stm32_eval_i2c_tsensor.h.

Referenced by LM75_Init().

#define LM75_LONG_TIMEOUT ((uint32_t)(10 * LM75_FLAG_TIMEOUT))

Definition at line 93 of file stm32_eval_i2c_tsensor.h.

Referenced by LM75_ReadConfReg(), LM75_ReadReg(), LM75_ReadTemp(), LM75_ShutDown(), LM75_WriteConfReg(), and LM75_WriteReg().

#define LM75_REG_CONF 0x01

Configuration Register of LM75

Definition at line 100 of file stm32_eval_i2c_tsensor.h.

Referenced by LM75_ReadConfReg(), LM75_ShutDown(), and LM75_WriteConfReg().

#define LM75_REG_TEMP 0x00

Block Size.

Temperature Register of LM75

Definition at line 99 of file stm32_eval_i2c_tsensor.h.

Referenced by LM75_ReadTemp().

#define LM75_REG_THYS 0x02

Temperature Register of LM75

Definition at line 101 of file stm32_eval_i2c_tsensor.h.

Referenced by main().

#define LM75_REG_TOS 0x03

Over-temp Shutdown threshold Register of LM75

Definition at line 102 of file stm32_eval_i2c_tsensor.h.

Referenced by main().


STM32F10x Standard Peripherals Firmware Library: STM32_EVAL_I2C_TSENSOR_Exported_Macros

STM32_EVAL_I2C_TSENSOR_Exported_Macros

STM32_EVAL_I2C_TSENSOR


STM32F10x Standard Peripherals Firmware Library: STM32_EVAL_I2C_TSENSOR_Exported_Functions

Defines | Functions

STM32_EVAL_I2C_TSENSOR_Exported_Functions

STM32_EVAL_I2C_TSENSOR

Defines

#define | LM75_TIMEOUT_UserCallback() LM75_FAIL
Timeout user callback function.

Functions

void | LM75_DeInit (void)
DeInitializes the LM75_I2C.
ErrorStatus | LM75_GetStatus (void)
Checks the LM75 status.
void | LM75_Init (void)
Initializes the LM75_I2C.
uint8_t | LM75_ReadConfReg (void)
Read the configuration register from the LM75.
uint16_t | LM75_ReadReg (uint8_t RegName)
Read the specified register from the LM75.
uint16_t | LM75_ReadTemp (void)
Read Temperature register of LM75: double temperature value.
uint8_t | LM75_ShutDown (FunctionalState NewState)
Enables or disables the LM75.
uint8_t | LM75_WriteConfReg (uint8_t RegValue)
Write to the configuration register of the LM75.
uint8_t | LM75_WriteReg (uint8_t RegName, uint16_t RegValue)
Write to the specified register of the LM75.

Define Documentation

#define LM75_TIMEOUT_UserCallback ( ) LM75_FAIL

Timeout user callback function.

This function is called when a timeout condition occurs during communication with IO Expander. Only protoype of this function is decalred in IO Expander driver. Its implementation may be done into user application. This function may typically stop current operations and reset the I2C peripheral and IO Expander. To enable this function use uncomment the define USE_TIMEOUT_USER_CALLBACK at the top of this file.

Definition at line 145 of file stm32_eval_i2c_tsensor.h.

Referenced by LM75_ReadConfReg(), LM75_ReadReg(), LM75_ReadTemp(), LM75_ShutDown(), LM75_WriteConfReg(), and LM75_WriteReg().

Function Documentation

void LM75_DeInit ( void )

DeInitializes the LM75_I2C.

Parameters:
None
Return values:
None

Definition at line 125 of file stm32_eval_i2c_tsensor.c.

References LM75_LowLevel_DeInit().

ErrorStatus LM75_GetStatus ( void )

Checks the LM75 status.

Parameters:
None
Return values:
ErrorStatus,: LM75 Status (ERROR or SUCCESS).

< Clear the LM75_I2C AF flag

< Enable LM75_I2C acknowledgement if it is already disabled by other function

< Send LM75_I2C START condition

< Test on LM75_I2C EV5 and clear it

< EV5

< Send STLM75 slave address for write

Definition at line 225 of file stm32_eval_i2c_tsensor.c.

References ENABLE, ERROR, I2C_AcknowledgeConfig(), I2C_CheckEvent(), I2C_ClearFlag(), I2C_Direction_Transmitter, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED, I2C_FLAG_AF, I2C_FLAG_SB, I2C_GenerateSTART(), I2C_GetFlagStatus(), I2C_Send7bitAddress(), I2C_TIMEOUT, LM75_ADDR, LM75_I2C, and SUCCESS.

Referenced by main().

void LM75_Init ( void )

Initializes the LM75_I2C.

Parameters:
None
Return values:
None

< LM75_I2C Init

< Enable SMBus Alert interrupt

< LM75_I2C Init

Definition at line 135 of file stm32_eval_i2c_tsensor.c.

References ENABLE, I2C_InitTypeDef::I2C_Ack, I2C_Ack_Enable, I2C_InitTypeDef::I2C_AcknowledgedAddress, I2C_AcknowledgedAddress_7bit, I2C_InitTypeDef::I2C_ClockSpeed, I2C_Cmd(), I2C_DeInit(), I2C_InitTypeDef::I2C_DutyCycle, I2C_DutyCycle_2, I2C_Init(), I2C_InitStructure, I2C_IT_ERR, I2C_ITConfig(), I2C_InitTypeDef::I2C_Mode, I2C_Mode_SMBusHost, I2C_InitTypeDef::I2C_OwnAddress1, LM75_I2C, LM75_I2C_SPEED, and LM75_LowLevel_Init().

Referenced by main().

uint8_t LM75_ReadConfReg ( void )

Read the configuration register from the LM75.

Parameters:
None
Return values:
LM75 configuration register value.

< Return Temperature value

Definition at line 580 of file stm32_eval_i2c_tsensor.c.

References DISABLE, DMA_ClearFlag(), DMA_Cmd(), DMA_GetFlagStatus(), ENABLE, I2C_CheckEvent(), I2C_Direction_Receiver, I2C_Direction_Transmitter, I2C_DMACmd(), I2C_DMALastTransferCmd(), I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED, I2C_FLAG_BTF, I2C_FLAG_BUSY, I2C_FLAG_SB, I2C_FLAG_TXE, I2C_GenerateSTART(), I2C_GenerateSTOP(), I2C_GetFlagStatus(), I2C_Send7bitAddress(), I2C_SendData(), LM75_ADDR, LM75_DMA_Config(), LM75_DMA_RX, LM75_DMA_RX_CHANNEL, LM75_DMA_RX_TCFLAG, LM75_FLAG_TIMEOUT, LM75_I2C, LM75_LONG_TIMEOUT, LM75_REG_CONF, LM75_Timeout, and LM75_TIMEOUT_UserCallback.

uint16_t LM75_ReadReg ( uint8_t RegName )

Read the specified register from the LM75.

Parameters:
RegName,: specifies the LM75 register to be read. This member can be one of the following values:

  • LM75_REG_TEMP: temperature register
  • LM75_REG_TOS: Over-limit temperature register
  • LM75_REG_THYS: Hysteresis temperature register
Return values:
LM75 register value.

< Store LM75_I2C received data

Definition at line 278 of file stm32_eval_i2c_tsensor.c.

References DISABLE, DMA_ClearFlag(), DMA_Cmd(), DMA_GetFlagStatus(), ENABLE, I2C_CheckEvent(), I2C_Direction_Receiver, I2C_Direction_Transmitter, I2C_DMACmd(), I2C_DMALastTransferCmd(), I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED, I2C_FLAG_BTF, I2C_FLAG_BUSY, I2C_FLAG_SB, I2C_FLAG_TXE, I2C_GenerateSTART(), I2C_GenerateSTOP(), I2C_GetFlagStatus(), I2C_Send7bitAddress(), I2C_SendData(), LM75_ADDR, LM75_DMA_Config(), LM75_DMA_RX, LM75_DMA_RX_CHANNEL, LM75_DMA_RX_TCFLAG, LM75_FLAG_TIMEOUT, LM75_I2C, LM75_LONG_TIMEOUT, LM75_Timeout, and LM75_TIMEOUT_UserCallback.

uint16_t LM75_ReadTemp ( void )

Read Temperature register of LM75: double temperature value.

Parameters:
None
Return values:
LM75 measured temperature value.

< Store LM75_I2C received data

< Return Temperature value

Definition at line 474 of file stm32_eval_i2c_tsensor.c.

References DISABLE, DMA_ClearFlag(), DMA_Cmd(), DMA_GetFlagStatus(), ENABLE, I2C_CheckEvent(), I2C_Direction_Receiver, I2C_Direction_Transmitter, I2C_DMACmd(), I2C_DMALastTransferCmd(), I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED, I2C_FLAG_BTF, I2C_FLAG_BUSY, I2C_FLAG_SB, I2C_FLAG_TXE, I2C_GenerateSTART(), I2C_GenerateSTOP(), I2C_GetFlagStatus(), I2C_Send7bitAddress(), I2C_SendData(), LM75_ADDR, LM75_DMA_Config(), LM75_DMA_RX, LM75_DMA_RX_CHANNEL, LM75_DMA_RX_TCFLAG, LM75_FLAG_TIMEOUT, LM75_I2C, LM75_LONG_TIMEOUT, LM75_REG_TEMP, LM75_Timeout, and LM75_TIMEOUT_UserCallback.

Referenced by main().

uint8_t LM75_ShutDown ( FunctionalState NewState )

Enables or disables the LM75.

Parameters:
NewState,: specifies the LM75 new status. This parameter can be ENABLE or DISABLE.
Return values:
None

< Get received data

< Enable or disable SD bit

< Enable LM75

< Disable LM75

Definition at line 769 of file stm32_eval_i2c_tsensor.c.

References DISABLE, DMA_ClearFlag(), DMA_Cmd(), DMA_GetFlagStatus(), ENABLE, I2C_CheckEvent(), I2C_Direction_Receiver, I2C_Direction_Transmitter, I2C_DMACmd(), I2C_DMALastTransferCmd(), I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED, I2C_FLAG_BTF, I2C_FLAG_BUSY, I2C_FLAG_SB, I2C_FLAG_TXE, I2C_GenerateSTART(), I2C_GenerateSTOP(), I2C_GetFlagStatus(), I2C_Send7bitAddress(), I2C_SendData(), LM75_ADDR, LM75_DMA_Config(), LM75_DMA_RX, LM75_DMA_RX_CHANNEL, LM75_DMA_RX_TCFLAG, LM75_DMA_TX, LM75_DMA_TX_CHANNEL, LM75_DMA_TX_TCFLAG, LM75_FLAG_TIMEOUT, LM75_I2C, LM75_LONG_TIMEOUT, LM75_OK, LM75_REG_CONF, LM75_SD_RESET, LM75_SD_SET, LM75_Timeout, LM75_TIMEOUT_UserCallback, and RESET.

uint8_t LM75_WriteConfReg ( uint8_t RegValue )

Write to the configuration register of the LM75.

Parameters:
RegValue,: sepecifies the value to be written to LM75 configuration register.
Return values:
None

Definition at line 682 of file stm32_eval_i2c_tsensor.c.

References DISABLE, DMA_ClearFlag(), DMA_Cmd(), DMA_GetFlagStatus(), ENABLE, I2C_CheckEvent(), I2C_Direction_Transmitter, I2C_DMACmd(), I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED, I2C_FLAG_BTF, I2C_FLAG_BUSY, I2C_FLAG_SB, I2C_FLAG_TXE, I2C_GenerateSTART(), I2C_GenerateSTOP(), I2C_GetFlagStatus(), I2C_Send7bitAddress(), I2C_SendData(), LM75_ADDR, LM75_DMA_Config(), LM75_DMA_TX, LM75_DMA_TX_CHANNEL, LM75_DMA_TX_TCFLAG, LM75_FLAG_TIMEOUT, LM75_I2C, LM75_LONG_TIMEOUT, LM75_OK, LM75_REG_CONF, LM75_Timeout, LM75_TIMEOUT_UserCallback, and RESET.

Referenced by main().

uint8_t LM75_WriteReg | ( | uint8_t | RegName,
 |  | uint16_t | RegValue
 | ) |  |

Write to the specified register of the LM75.

Parameters:
RegName,: specifies the LM75 register to be written. This member can be one of the following values:

  • LM75_REG_TOS: Over-limit temperature register
  • LM75_REG_THYS: Hysteresis temperature register
RegValue,: value to be written to LM75 register.
Return values:
None

Definition at line 388 of file stm32_eval_i2c_tsensor.c.

References DISABLE, DMA_ClearFlag(), DMA_Cmd(), DMA_GetFlagStatus(), ENABLE, I2C_CheckEvent(), I2C_Direction_Transmitter, I2C_DMACmd(), I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED, I2C_FLAG_BTF, I2C_FLAG_BUSY, I2C_FLAG_SB, I2C_FLAG_TXE, I2C_GenerateSTART(), I2C_GenerateSTOP(), I2C_GetFlagStatus(), I2C_Send7bitAddress(), I2C_SendData(), LM75_ADDR, LM75_DMA_Config(), LM75_DMA_TX, LM75_DMA_TX_CHANNEL, LM75_DMA_TX_TCFLAG, LM75_FLAG_TIMEOUT, LM75_I2C, LM75_LONG_TIMEOUT, LM75_OK, LM75_Timeout, LM75_TIMEOUT_UserCallback, and RESET.

Referenced by main().


STM32F10x Standard Peripherals Firmware Library: STM32_EVAL_SDIO_SD_Private_Types

STM32_EVAL_SDIO_SD_Private_Types

STM32_EVAL_SDIO_SD


STM32F10x Standard Peripherals Firmware Library: STM32_EVAL_SDIO_SD_Private_Defines

Defines

STM32_EVAL_SDIO_SD_Private_Defines

STM32_EVAL_SDIO_SD

Defines

#define | NULL 0
SDIO Static flags, TimeOut, FIFO Address.
#define | SD_0TO7BITS ((uint32_t)0x000000FF)
#define | SD_16TO23BITS ((uint32_t)0x00FF0000)
#define | SD_24TO31BITS ((uint32_t)0xFF000000)
#define | SD_8TO15BITS ((uint32_t)0x0000FF00)
#define | SD_ALLZERO ((uint32_t)0x00000000)
#define | SD_CARD_LOCKED ((uint32_t)0x02000000)
#define | SD_CCCC_ERASE ((uint32_t)0x00000020)
#define | SD_CCCC_LOCK_UNLOCK ((uint32_t)0x00000080)
Command Class Supported.
#define | SD_CCCC_WRITE_PROT ((uint32_t)0x00000040)
#define | SD_CHECK_PATTERN ((uint32_t)0x000001AA)
#define | SD_DATATIMEOUT ((uint32_t)0xFFFFFFFF)
#define | SD_HALFFIFO ((uint32_t)0x00000008)
#define | SD_HALFFIFOBYTES ((uint32_t)0x00000020)
#define | SD_HIGH_CAPACITY ((uint32_t)0x40000000)
#define | SD_MAX_DATA_LENGTH ((uint32_t)0x01FFFFFF)
#define | SD_MAX_VOLT_TRIAL ((uint32_t)0x0000FFFF)
#define | SD_OCR_ADDR_MISALIGNED ((uint32_t)0x40000000)
#define | SD_OCR_ADDR_OUT_OF_RANGE ((uint32_t)0x80000000)
Mask for errors Card Status R1 (OCR Register)
#define | SD_OCR_AKE_SEQ_ERROR ((uint32_t)0x00000008)
#define | SD_OCR_BAD_ERASE_PARAM ((uint32_t)0x08000000)
#define | SD_OCR_BLOCK_LEN_ERR ((uint32_t)0x20000000)
#define | SD_OCR_CARD_ECC_DISABLED ((uint32_t)0x00004000)
#define | SD_OCR_CARD_ECC_FAILED ((uint32_t)0x00200000)
#define | SD_OCR_CC_ERROR ((uint32_t)0x00100000)
#define | SD_OCR_CID_CSD_OVERWRIETE ((uint32_t)0x00010000)
#define | SD_OCR_COM_CRC_FAILED ((uint32_t)0x00800000)
#define | SD_OCR_ERASE_RESET ((uint32_t)0x00002000)
#define | SD_OCR_ERASE_SEQ_ERR ((uint32_t)0x10000000)
#define | SD_OCR_ERRORBITS ((uint32_t)0xFDFFE008)
#define | SD_OCR_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00080000)
#define | SD_OCR_ILLEGAL_CMD ((uint32_t)0x00400000)
#define | SD_OCR_LOCK_UNLOCK_FAILED ((uint32_t)0x01000000)
#define | SD_OCR_STREAM_READ_UNDERRUN ((uint32_t)0x00040000)
#define | SD_OCR_STREAM_WRITE_OVERRUN ((uint32_t)0x00020000)
#define | SD_OCR_WP_ERASE_SKIP ((uint32_t)0x00008000)
#define | SD_OCR_WRITE_PROT_VIOLATION ((uint32_t)0x04000000)
#define | SD_R6_COM_CRC_FAILED ((uint32_t)0x00008000)
#define | SD_R6_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00002000)
Masks for R6 Response.
#define | SD_R6_ILLEGAL_CMD ((uint32_t)0x00004000)
#define | SD_SINGLE_BUS_SUPPORT ((uint32_t)0x00010000)
#define | SD_STD_CAPACITY ((uint32_t)0x00000000)
#define | SD_VOLTAGE_WINDOW_SD ((uint32_t)0x80100000)
#define | SD_WIDE_BUS_SUPPORT ((uint32_t)0x00040000)
#define | SDIO_CMD0TIMEOUT ((uint32_t)0x00010000)
#define | SDIO_SEND_IF_COND ((uint32_t)0x00000008)
Following commands are SD Card Specific commands.
#define | SDIO_STATIC_FLAGS ((uint32_t)0x000005FF)

Define Documentation

#define NULL 0

SDIO Static flags, TimeOut, FIFO Address.

Definition at line 226 of file stm32_eval_sdio_sd.c.

#define SD_0TO7BITS ((uint32_t)0x000000FF)

Definition at line 274 of file stm32_eval_sdio_sd.c.

Referenced by FindSCR().

#define SD_16TO23BITS ((uint32_t)0x00FF0000)

Definition at line 276 of file stm32_eval_sdio_sd.c.

Referenced by FindSCR().

#define SD_24TO31BITS ((uint32_t)0xFF000000)

Definition at line 277 of file stm32_eval_sdio_sd.c.

Referenced by FindSCR().

#define SD_8TO15BITS ((uint32_t)0x0000FF00)

Definition at line 275 of file stm32_eval_sdio_sd.c.

Referenced by FindSCR().

#define SD_ALLZERO ((uint32_t)0x00000000)

Definition at line 267 of file stm32_eval_sdio_sd.c.

Referenced by CmdResp6Error(), IsCardProgramming(), and SDEnWideBus().

#define SD_CARD_LOCKED ((uint32_t)0x02000000)

Definition at line 271 of file stm32_eval_sdio_sd.c.

Referenced by SD_Erase(), SD_SendSDStatus(), and SDEnWideBus().

#define SD_CCCC_ERASE ((uint32_t)0x00000020)

Definition at line 288 of file stm32_eval_sdio_sd.c.

Referenced by SD_Erase().

#define SD_CCCC_LOCK_UNLOCK ((uint32_t)0x00000080)

Command Class Supported.

Definition at line 286 of file stm32_eval_sdio_sd.c.

#define SD_CCCC_WRITE_PROT ((uint32_t)0x00000040)

Definition at line 287 of file stm32_eval_sdio_sd.c.

#define SD_CHECK_PATTERN ((uint32_t)0x000001AA)

Definition at line 264 of file stm32_eval_sdio_sd.c.

Referenced by SD_PowerON().

#define SD_DATATIMEOUT ((uint32_t)0xFFFFFFFF)

Definition at line 273 of file stm32_eval_sdio_sd.c.

Referenced by FindSCR(), SD_ReadBlock(), SD_ReadMultiBlocks(), SD_SendSDStatus(), SD_WriteBlock(), and SD_WriteMultiBlocks().

#define SD_HALFFIFO ((uint32_t)0x00000008)

Definition at line 280 of file stm32_eval_sdio_sd.c.

#define SD_HALFFIFOBYTES ((uint32_t)0x00000020)

Definition at line 281 of file stm32_eval_sdio_sd.c.

#define SD_HIGH_CAPACITY ((uint32_t)0x40000000)

Definition at line 262 of file stm32_eval_sdio_sd.c.

Referenced by SD_PowerON().

#define SD_MAX_DATA_LENGTH ((uint32_t)0x01FFFFFF)

Definition at line 278 of file stm32_eval_sdio_sd.c.

#define SD_MAX_VOLT_TRIAL ((uint32_t)0x0000FFFF)

Definition at line 266 of file stm32_eval_sdio_sd.c.

Referenced by SD_PowerON().

#define SD_OCR_ADDR_MISALIGNED ((uint32_t)0x40000000)

Definition at line 234 of file stm32_eval_sdio_sd.c.

Referenced by IsCardProgramming().

#define SD_OCR_ADDR_OUT_OF_RANGE ((uint32_t)0x80000000)

Mask for errors Card Status R1 (OCR Register)

Definition at line 233 of file stm32_eval_sdio_sd.c.

Referenced by IsCardProgramming().

#define SD_OCR_AKE_SEQ_ERROR ((uint32_t)0x00000008)

Definition at line 251 of file stm32_eval_sdio_sd.c.

Referenced by IsCardProgramming().

#define SD_OCR_BAD_ERASE_PARAM ((uint32_t)0x08000000)

Definition at line 237 of file stm32_eval_sdio_sd.c.

Referenced by IsCardProgramming().

#define SD_OCR_BLOCK_LEN_ERR ((uint32_t)0x20000000)

Definition at line 235 of file stm32_eval_sdio_sd.c.

Referenced by IsCardProgramming().

#define SD_OCR_CARD_ECC_DISABLED ((uint32_t)0x00004000)

Definition at line 249 of file stm32_eval_sdio_sd.c.

Referenced by IsCardProgramming().

#define SD_OCR_CARD_ECC_FAILED ((uint32_t)0x00200000)

Definition at line 242 of file stm32_eval_sdio_sd.c.

Referenced by IsCardProgramming().

#define SD_OCR_CC_ERROR ((uint32_t)0x00100000)

Definition at line 243 of file stm32_eval_sdio_sd.c.

Referenced by IsCardProgramming().

#define SD_OCR_CID_CSD_OVERWRIETE ((uint32_t)0x00010000)

Definition at line 247 of file stm32_eval_sdio_sd.c.

Referenced by IsCardProgramming().

#define SD_OCR_COM_CRC_FAILED ((uint32_t)0x00800000)

Definition at line 240 of file stm32_eval_sdio_sd.c.

Referenced by IsCardProgramming().

#define SD_OCR_ERASE_RESET ((uint32_t)0x00002000)

Definition at line 250 of file stm32_eval_sdio_sd.c.

Referenced by IsCardProgramming().

#define SD_OCR_ERASE_SEQ_ERR ((uint32_t)0x10000000)

Definition at line 236 of file stm32_eval_sdio_sd.c.

Referenced by IsCardProgramming().

#define SD_OCR_ERRORBITS ((uint32_t)0xFDFFE008)

Definition at line 252 of file stm32_eval_sdio_sd.c.

Referenced by CmdResp1Error(), and IsCardProgramming().

#define SD_OCR_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00080000)

Definition at line 244 of file stm32_eval_sdio_sd.c.

Referenced by IsCardProgramming().

#define SD_OCR_ILLEGAL_CMD ((uint32_t)0x00400000)

Definition at line 241 of file stm32_eval_sdio_sd.c.

Referenced by IsCardProgramming().

#define SD_OCR_LOCK_UNLOCK_FAILED ((uint32_t)0x01000000)

Definition at line 239 of file stm32_eval_sdio_sd.c.

Referenced by IsCardProgramming().

#define SD_OCR_STREAM_READ_UNDERRUN ((uint32_t)0x00040000)

Definition at line 245 of file stm32_eval_sdio_sd.c.

Referenced by IsCardProgramming().

#define SD_OCR_STREAM_WRITE_OVERRUN ((uint32_t)0x00020000)

Definition at line 246 of file stm32_eval_sdio_sd.c.

Referenced by IsCardProgramming().

#define SD_OCR_WP_ERASE_SKIP ((uint32_t)0x00008000)

Definition at line 248 of file stm32_eval_sdio_sd.c.

Referenced by IsCardProgramming().

#define SD_OCR_WRITE_PROT_VIOLATION ((uint32_t)0x04000000)

Definition at line 238 of file stm32_eval_sdio_sd.c.

Referenced by IsCardProgramming().

#define SD_R6_COM_CRC_FAILED ((uint32_t)0x00008000)

Definition at line 259 of file stm32_eval_sdio_sd.c.

Referenced by CmdResp6Error().

#define SD_R6_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00002000)

Masks for R6 Response.

Definition at line 257 of file stm32_eval_sdio_sd.c.

Referenced by CmdResp6Error().

#define SD_R6_ILLEGAL_CMD ((uint32_t)0x00004000)

Definition at line 258 of file stm32_eval_sdio_sd.c.

Referenced by CmdResp6Error().

#define SD_SINGLE_BUS_SUPPORT ((uint32_t)0x00010000)

Definition at line 270 of file stm32_eval_sdio_sd.c.

Referenced by SDEnWideBus().

#define SD_STD_CAPACITY ((uint32_t)0x00000000)

Definition at line 263 of file stm32_eval_sdio_sd.c.

Referenced by SD_PowerON().

#define SD_VOLTAGE_WINDOW_SD ((uint32_t)0x80100000)

Definition at line 261 of file stm32_eval_sdio_sd.c.

Referenced by SD_PowerON().

#define SD_WIDE_BUS_SUPPORT ((uint32_t)0x00040000)

Definition at line 269 of file stm32_eval_sdio_sd.c.

Referenced by SDEnWideBus().

#define SDIO_CMD0TIMEOUT ((uint32_t)0x00010000)

Definition at line 228 of file stm32_eval_sdio_sd.c.

Referenced by CmdError(), and CmdResp7Error().

#define SDIO_SEND_IF_COND ((uint32_t)0x00000008)

Following commands are SD Card Specific commands.

SDIO_APP_CMD should be sent before sending these commands.

Definition at line 294 of file stm32_eval_sdio_sd.c.

Referenced by SD_PowerON().

#define SDIO_STATIC_FLAGS ((uint32_t)0x000005FF)

Definition at line 227 of file stm32_eval_sdio_sd.c.

Referenced by CmdError(), CmdResp1Error(), CmdResp2Error(), CmdResp3Error(), CmdResp6Error(), FindSCR(), IsCardProgramming(), SD_ReadBlock(), SD_SendSDStatus(), and SD_WaitWriteOperation().


STM32F10x Standard Peripherals Firmware Library: STM32_EVAL_SDIO_SD_Private_Macros

STM32_EVAL_SDIO_SD_Private_Macros

STM32_EVAL_SDIO_SD


STM32F10x Standard Peripherals Firmware Library: STM32_EVAL_SDIO_SD_Private_Variables

Variables

STM32_EVAL_SDIO_SD_Private_Variables

STM32_EVAL_SDIO_SD

Variables

static uint32_t | CardType = SDIO_STD_CAPACITY_SD_CARD_V1_1
static uint32_t | CID_Tab [4]
static uint32_t | CSD_Tab [4]
static uint32_t | RCA = 0
SD_CardInfo SDCardInfo
SDIO_CmdInitTypeDef SDIO_CmdInitStructure
SDIO_DataInitTypeDef SDIO_DataInitStructure
SDIO_InitTypeDef SDIO_InitStructure
static uint8_t | SDSTATUS_Tab [16]
__IO uint32_t | StopCondition = 0
__IO uint32_t | TransferEnd = 0
__IO SD_Error | TransferError = SD_OK

Variable Documentation

uint32_t CardType = SDIO_STD_CAPACITY_SD_CARD_V1_1 [static]

Definition at line 312 of file stm32_eval_sdio_sd.c.

Referenced by SD_EnableWideBusOperation(), SD_Erase(), SD_GetCardInfo(), SD_InitializeCards(), SD_PowerON(), SD_ReadBlock(), SD_ReadMultiBlocks(), SD_WriteBlock(), and SD_WriteMultiBlocks().

uint32_t CID_Tab[4]

Definition at line 313 of file stm32_eval_sdio_sd.c.

Referenced by SD_GetCardInfo(), SD_GetCIDRegister(), and SD_InitializeCards().

uint32_t CSD_Tab[4] [static]

Definition at line 313 of file stm32_eval_sdio_sd.c.

Referenced by SD_Erase(), SD_GetCardInfo(), SD_GetCSDRegister(), and SD_InitializeCards().

uint32_t RCA = 0

Definition at line 313 of file stm32_eval_sdio_sd.c.

Referenced by FindSCR(), IsCardProgramming(), SD_GetCardInfo(), SD_InitializeCards(), SD_SendSDStatus(), SD_SendStatus(), SD_WriteMultiBlocks(), and SDEnWideBus().

SD_CardInfo SDCardInfo

Definition at line 318 of file stm32_eval_sdio_sd.c.

SDIO_CmdInitTypeDef SDIO_CmdInitStructure

Definition at line 321 of file stm32_eval_sdio_sd.c.

SDIO_DataInitTypeDef SDIO_DataInitStructure

Definition at line 322 of file stm32_eval_sdio_sd.c.

SDIO_InitTypeDef SDIO_InitStructure

Definition at line 320 of file stm32_eval_sdio_sd.c.

uint8_t SDSTATUS_Tab[16] [static]

Definition at line 314 of file stm32_eval_sdio_sd.c.

Referenced by SD_GetCardStatus().

__IO uint32_t StopCondition = 0

Definition at line 315 of file stm32_eval_sdio_sd.c.

Referenced by SD_ProcessIRQSrc(), SD_ReadBlock(), SD_ReadMultiBlocks(), SD_WriteBlock(), and SD_WriteMultiBlocks().

__IO uint32_t TransferEnd = 0

Definition at line 317 of file stm32_eval_sdio_sd.c.

Referenced by SD_ProcessIRQSrc(), SD_ReadBlock(), SD_ReadMultiBlocks(), SD_WaitReadOperation(), SD_WaitWriteOperation(), SD_WriteBlock(), and SD_WriteMultiBlocks().

__IO SD_Error TransferError = SD_OK

Definition at line 316 of file stm32_eval_sdio_sd.c.

Referenced by SD_ProcessIRQSrc(), SD_ReadBlock(), SD_ReadMultiBlocks(), SD_WaitReadOperation(), SD_WaitWriteOperation(), SD_WriteBlock(), and SD_WriteMultiBlocks().


STM32F10x Standard Peripherals Firmware Library: STM32_EVAL_SDIO_SD_Private_Function_Prototypes

STM32_EVAL_SDIO_SD_Private_Function_Prototypes

STM32_EVAL_SDIO_SD


STM32F10x Standard Peripherals Firmware Library: STM32_EVAL_SDIO_SD_Private_Functions

Functions

STM32_EVAL_SDIO_SD_Private_Functions

STM32_EVAL_SDIO_SD

Functions

static SD_Error | CmdError (void)
Checks for error conditions for CMD0.
static SD_Error | CmdResp1Error (uint8_t cmd)
Checks for error conditions for R1 response.
static SD_Error | CmdResp2Error (void)
Checks for error conditions for R2 (CID or CSD) response.
static SD_Error | CmdResp3Error (void)
Checks for error conditions for R3 (OCR) response.
static SD_Error | CmdResp6Error (uint8_t cmd, uint16_t *prca)
Checks for error conditions for R6 (RCA) response.
static SD_Error | CmdResp7Error (void)
Checks for error conditions for R7 response.
uint8_t | convert_from_bytes_to_power_of_two (uint16_t NumberOfBytes)
Converts the number of bytes in power of two and returns the power.
static SD_Error | FindSCR (uint16_t rca, uint32_t *pscr)
Find the SD card SCR register value.
static SD_Error | IsCardProgramming (uint8_t *pstatus)
Checks if the SD card is in programming state.
void | SD_DeInit (void)
DeInitializes the SDIO interface.
uint8_t | SD_Detect (void)
Detect if SD card is correctly plugged in the memory slot.
SD_Error | SD_EnableWideBusOperation (uint32_t WideMode)
Enables wide bus opeartion for the requeseted card if supported by card.
SD_Error | SD_Erase (uint32_t startaddr, uint32_t endaddr)
Allows to erase memory area specified for the given card.
SD_Error | SD_GetCardInfo (SD_CardInfo *cardinfo)
Returns information about specific card.
SD_Error | SD_GetCardStatus (SD_CardStatus *cardstatus)
Enables wide bus opeartion for the requeseted card if supported by card.
SDCardState | SD_GetState (void)
Returns the current card's state.
SDTransferState | SD_GetStatus (void)
Gets the cuurent sd card data transfer status.
SDTransferState | SD_GetTransferState (void)
Gets the cuurent data transfer state.
SD_Error | SD_Init (void)
Initializes the SD Card and put it into StandBy State (Ready for data transfer).
SD_Error | SD_InitializeCards (void)
Intialises all cards or single card as the case may be Card(s) come into standby state.
SD_Error | SD_PowerOFF (void)
Turns the SDIO output signals off.
SD_Error | SD_PowerON (void)
Enquires cards about their operating voltage and configures clock controls.
SD_Error | SD_ProcessIRQSrc (void)
Allows to process all the interrupts that are high.
SD_Error | SD_ReadBlock (uint8_t *readbuff, uint32_t ReadAddr, uint16_t BlockSize)
Allows to read one block from a specified address in a card.
SD_Error | SD_ReadMultiBlocks (uint8_t *readbuff, uint32_t ReadAddr, uint16_t BlockSize, uint32_t NumberOfBlocks)
Allows to read blocks from a specified address in a card.
SD_Error | SD_SelectDeselect (uint32_t addr)
Selects od Deselects the corresponding card.
SD_Error | SD_SendSDStatus (uint32_t *psdstatus)
Returns the current SD card's status.
SD_Error | SD_SendStatus (uint32_t *pcardstatus)
Returns the current card's status.
SD_Error | SD_StopTransfer (void)
Aborts an ongoing data transfer.
SD_Error | SD_WaitReadOperation (void)
This function waits until the SDIO DMA data transfer is finished.
SD_Error | SD_WaitWriteOperation (void)
This function waits until the SDIO DMA data transfer is finished.
SD_Error | SD_WriteBlock (uint8_t *writebuff, uint32_t WriteAddr, uint16_t BlockSize)
Allows to write one block starting from a specified address in a card.
SD_Error | SD_WriteMultiBlocks (uint8_t *writebuff, uint32_t WriteAddr, uint16_t BlockSize, uint32_t NumberOfBlocks)
Allows to write blocks starting from a specified address in a card.
static SD_Error | SDEnWideBus (FunctionalState NewState)
Enables or disables the SDIO wide bus mode.

Function Documentation

static SD_Error CmdError ( void ) [static]

Checks for error conditions for CMD0.

Parameters:
None
Return values:
SD_Error,: SD Card Error code.

< 10000

Definition at line 1871 of file stm32_eval_sdio_sd.c.

References RESET, SD_CMD_RSP_TIMEOUT, SD_OK, SDIO_ClearFlag(), SDIO_CMD0TIMEOUT, SDIO_FLAG_CMDSENT, SDIO_GetFlagStatus(), and SDIO_STATIC_FLAGS.

Referenced by SD_PowerON().

static SD_Error CmdResp1Error ( uint8_t cmd ) [static]

Checks for error conditions for R1 response.

Parameters:
cmd,: The sent command index.
Return values:
SD_Error,: SD Card Error code.

Definition at line 1937 of file stm32_eval_sdio_sd.c.

References SD_OCR_ERRORBITS, SDIO, SDIO_FLAG_CCRCFAIL, SDIO_FLAG_CMDREND, SDIO_FLAG_CTIMEOUT, and SDIO_STATIC_FLAGS.

Referenced by FindSCR(), SD_Erase(), SD_PowerON(), SD_ProcessIRQSrc(), SD_ReadBlock(), SD_ReadMultiBlocks(), SD_SelectDeselect(), SD_SendSDStatus(), SD_SendStatus(), SD_StopTransfer(), SD_WriteBlock(), SD_WriteMultiBlocks(), and SDEnWideBus().

static SD_Error CmdResp2Error ( void ) [static]

Checks for error conditions for R2 (CID or CSD) response.

Parameters:
None
Return values:
SD_Error,: SD Card Error code.

Definition at line 1981 of file stm32_eval_sdio_sd.c.

References SD_CMD_CRC_FAIL, SD_CMD_RSP_TIMEOUT, SD_OK, SDIO, SDIO_ClearFlag(), SDIO_FLAG_CCRCFAIL, SDIO_FLAG_CMDREND, SDIO_FLAG_CTIMEOUT, SDIO_STATIC_FLAGS, and status.

Referenced by SD_InitializeCards().

static SD_Error CmdResp3Error ( void ) [static]

Checks for error conditions for R3 (OCR) response.

Parameters:
None
Return values:
SD_Error,: SD Card Error code.

Definition at line 1953 of file stm32_eval_sdio_sd.c.

References SD_CMD_RSP_TIMEOUT, SD_OK, SDIO, SDIO_ClearFlag(), SDIO_FLAG_CCRCFAIL, SDIO_FLAG_CMDREND, SDIO_FLAG_CTIMEOUT, SDIO_STATIC_FLAGS, and status.

Referenced by SD_PowerON().

static SD_Error CmdResp6Error | ( | uint8_t | cmd,
 |  | uint16_t * | prca
 | ) |  | [static]

Checks for error conditions for R6 (RCA) response.

Parameters:
cmd,: The sent command index.
prca,: pointer to the variable that will contain the SD card relative address RCA.
Return values:
SD_Error,: SD Card Error code.

< We have received response, retrieve it.

Definition at line 2019 of file stm32_eval_sdio_sd.c.

References SD_ALLZERO, SD_CMD_CRC_FAIL, SD_CMD_RSP_TIMEOUT, SD_COM_CRC_FAILED, SD_GENERAL_UNKNOWN_ERROR, SD_ILLEGAL_CMD, SD_OK, SD_R6_COM_CRC_FAILED, SD_R6_GENERAL_UNKNOWN_ERROR, SD_R6_ILLEGAL_CMD, SDIO, SDIO_ClearFlag(), SDIO_FLAG_CCRCFAIL, SDIO_FLAG_CMDREND, SDIO_FLAG_CTIMEOUT, SDIO_GetCommandResponse(), SDIO_GetResponse(), SDIO_RESP1, SDIO_STATIC_FLAGS, and status.

Referenced by SD_InitializeCards().

static SD_Error CmdResp7Error ( void ) [static]

Checks for error conditions for R7 response.

Parameters:
None
Return values:
SD_Error,: SD Card Error code.

< Card is not V2.0 complient or card does not support the set voltage range

< Card is SD V2.0 compliant

Definition at line 1900 of file stm32_eval_sdio_sd.c.

References SD_CMD_RSP_TIMEOUT, SD_OK, SDIO, SDIO_ClearFlag(), SDIO_CMD0TIMEOUT, SDIO_FLAG_CCRCFAIL, SDIO_FLAG_CMDREND, SDIO_FLAG_CTIMEOUT, and status.

Referenced by SD_PowerON().

uint8_t convert_from_bytes_to_power_of_two ( uint16_t NumberOfBytes )

Converts the number of bytes in power of two and returns the power.

Parameters:
NumberOfBytes,: number of bytes.
Return values:
None

Definition at line 2470 of file stm32_eval_sdio_sd.c.

static SD_Error FindSCR | ( | uint16_t | rca,
 |  | uint32_t * | pscr
 | ) |  | [static]

Find the SD card SCR register value.

Parameters:
rca,: selected card address.
pscr,: pointer to the buffer that will contain the SCR value.
Return values:
SD_Error,: SD Card Error code.

< Set Block Size To 8 Bytes

< Send CMD55 APP_CMD with argument as card's RCA

< Send ACMD51 SD_APP_SEND_SCR with argument as 0

Definition at line 2361 of file stm32_eval_sdio_sd.c.

References CmdResp1Error(), index, RCA, RESET, SD_0TO7BITS, SD_16TO23BITS, SD_24TO31BITS, SD_8TO15BITS, SD_CMD_APP_CMD, SD_CMD_SD_APP_SEND_SCR, SD_CMD_SET_BLOCKLEN, SD_DATA_CRC_FAIL, SD_DATA_TIMEOUT, SD_DATATIMEOUT, SD_OK, SD_RX_OVERRUN, SD_START_BIT_ERR, SDIO, SDIO_CmdInitTypeDef::SDIO_Argument, SDIO_ClearFlag(), SDIO_CmdInitTypeDef::SDIO_CmdIndex, SDIO_CmdInitTypeDef::SDIO_CPSM, SDIO_CPSM_Enable, SDIO_DataInitTypeDef::SDIO_DataBlockSize, SDIO_DataBlockSize_8b, SDIO_DataConfig(), SDIO_DataInitTypeDef::SDIO_DataLength, SDIO_DataInitTypeDef::SDIO_DataTimeOut, SDIO_DataInitTypeDef::SDIO_DPSM, SDIO_DPSM_Enable, SDIO_FLAG_DBCKEND, SDIO_FLAG_DCRCFAIL, SDIO_FLAG_DTIMEOUT, SDIO_FLAG_RXDAVL, SDIO_FLAG_RXOVERR, SDIO_FLAG_STBITERR, SDIO_GetFlagStatus(), SDIO_ReadData(), SDIO_CmdInitTypeDef::SDIO_Response, SDIO_Response_Short, SDIO_SendCommand(), SDIO_STATIC_FLAGS, SDIO_DataInitTypeDef::SDIO_TransferDir, SDIO_TransferDir_ToSDIO, SDIO_DataInitTypeDef::SDIO_TransferMode, SDIO_TransferMode_Block, SDIO_CmdInitTypeDef::SDIO_Wait, and SDIO_Wait_No.

Referenced by SDEnWideBus().

static SD_Error IsCardProgramming ( uint8_t * pstatus ) [static]

Checks if the SD card is in programming state.

Parameters:
pstatus,: pointer to the variable that will contain the SD card state.
Return values:
SD_Error,: SD Card Error code.

< Check response received is of desired command

< We have received response, retrieve it for analysis

< Find out card status

Definition at line 2202 of file stm32_eval_sdio_sd.c.

References RCA, SD_ADDR_MISALIGNED, SD_ADDR_OUT_OF_RANGE, SD_AKE_SEQ_ERROR, SD_ALLZERO, SD_BAD_ERASE_PARAM, SD_BLOCK_LEN_ERR, SD_CARD_ECC_DISABLED, SD_CARD_ECC_FAILED, SD_CC_ERROR, SD_CID_CSD_OVERWRITE, SD_CMD_CRC_FAIL, SD_CMD_RSP_TIMEOUT, SD_CMD_SEND_STATUS, SD_COM_CRC_FAILED, SD_ERASE_RESET, SD_ERASE_SEQ_ERR, SD_GENERAL_UNKNOWN_ERROR, SD_ILLEGAL_CMD, SD_LOCK_UNLOCK_FAILED, SD_OCR_ADDR_MISALIGNED, SD_OCR_ADDR_OUT_OF_RANGE, SD_OCR_AKE_SEQ_ERROR, SD_OCR_BAD_ERASE_PARAM, SD_OCR_BLOCK_LEN_ERR, SD_OCR_CARD_ECC_DISABLED, SD_OCR_CARD_ECC_FAILED, SD_OCR_CC_ERROR, SD_OCR_CID_CSD_OVERWRIETE, SD_OCR_COM_CRC_FAILED, SD_OCR_ERASE_RESET, SD_OCR_ERASE_SEQ_ERR, SD_OCR_ERRORBITS, SD_OCR_GENERAL_UNKNOWN_ERROR, SD_OCR_ILLEGAL_CMD, SD_OCR_LOCK_UNLOCK_FAILED, SD_OCR_STREAM_READ_UNDERRUN, SD_OCR_STREAM_WRITE_OVERRUN, SD_OCR_WP_ERASE_SKIP, SD_OCR_WRITE_PROT_VIOLATION, SD_OK, SD_STREAM_READ_UNDERRUN, SD_STREAM_WRITE_OVERRUN, SD_WP_ERASE_SKIP, SD_WRITE_PROT_VIOLATION, SDIO, SDIO_CmdInitTypeDef::SDIO_Argument, SDIO_ClearFlag(), SDIO_CmdInitTypeDef::SDIO_CmdIndex, SDIO_CmdInitTypeDef::SDIO_CPSM, SDIO_CPSM_Enable, SDIO_FLAG_CCRCFAIL, SDIO_FLAG_CMDREND, SDIO_FLAG_CTIMEOUT, SDIO_GetCommandResponse(), SDIO_GetResponse(), SDIO_RESP1, SDIO_CmdInitTypeDef::SDIO_Response, SDIO_Response_Short, SDIO_SendCommand(), SDIO_STATIC_FLAGS, SDIO_CmdInitTypeDef::SDIO_Wait, SDIO_Wait_No, and status.

Referenced by SD_Erase().

void SD_DeInit ( void )

DeInitializes the SDIO interface.

Parameters:
None
Return values:
None

Definition at line 356 of file stm32_eval_sdio_sd.c.

uint8_t SD_Detect ( void )

Detect if SD card is correctly plugged in the memory slot.

Parameters:
None
Return values:
Return if SD is detected or not

< Check GPIO to detect SD

Definition at line 482 of file stm32_eval_sdio_sd.c.

Referenced by main(), and SD_GetState().

SD_Error SD_EnableWideBusOperation ( uint32_t WideMode )

Enables wide bus opeartion for the requeseted card if supported by card.

Parameters:
WideMode,: Specifies the SD card wide bus mode. This parameter can be one of the following values:

  • SDIO_BusWide_8b: 8-bit data transfer (Only for MMC)
  • SDIO_BusWide_4b: 4-bit data transfer
  • SDIO_BusWide_1b: 1-bit data transfer
Return values:
SD_Error,: SD Card Error code.

< MMC Card doesn't support this feature

< Configure the SDIO peripheral

< Configure the SDIO peripheral

Definition at line 1046 of file stm32_eval_sdio_sd.c.

References CardType, DISABLE, ENABLE, SD_OK, SD_UNSUPPORTED_FEATURE, SDEnWideBus(), SDIO_InitTypeDef::SDIO_BusWide, SDIO_BusWide_1b, SDIO_BusWide_4b, SDIO_BusWide_8b, SDIO_InitTypeDef::SDIO_ClockBypass, SDIO_ClockBypass_Disable, SDIO_InitTypeDef::SDIO_ClockDiv, SDIO_InitTypeDef::SDIO_ClockEdge, SDIO_ClockEdge_Rising, SDIO_InitTypeDef::SDIO_ClockPowerSave, SDIO_ClockPowerSave_Disable, SDIO_InitTypeDef::SDIO_HardwareFlowControl, SDIO_HardwareFlowControl_Disable, SDIO_HIGH_CAPACITY_SD_CARD, SDIO_Init(), SDIO_MULTIMEDIA_CARD, SDIO_STD_CAPACITY_SD_CARD_V1_1, SDIO_STD_CAPACITY_SD_CARD_V2_0, and SDIO_TRANSFER_CLK_DIV.

Referenced by SD_Init().

SD_Error SD_Erase | ( | uint32_t | startaddr,
 |  | uint32_t | endaddr
 | ) |  |

Allows to erase memory area specified for the given card.

Parameters:
startaddr,: the start address.
endaddr,: the end address.
Return values:
SD_Error,: SD Card Error code.

< Check if the card coomnd class supports erase command

< Send CMD32 SD_ERASE_GRP_START with argument as addr

Definition at line 1613 of file stm32_eval_sdio_sd.c.

References CardType, CmdResp1Error(), CSD_Tab, delay(), IsCardProgramming(), SD_CARD_LOCKED, SD_CARD_PROGRAMMING, SD_CARD_RECEIVING, SD_CCCC_ERASE, SD_CMD_ERASE, SD_CMD_SD_ERASE_GRP_END, SD_CMD_SD_ERASE_GRP_START, SD_LOCK_UNLOCK_FAILED, SD_OK, SD_REQUEST_NOT_APPLICABLE, SDIO, SDIO_CmdInitTypeDef::SDIO_Argument, SDIO_CmdInitTypeDef::SDIO_CmdIndex, SDIO_CmdInitTypeDef::SDIO_CPSM, SDIO_CPSM_Enable, SDIO_GetResponse(), SDIO_HIGH_CAPACITY_SD_CARD, SDIO_RESP1, SDIO_CmdInitTypeDef::SDIO_Response, SDIO_Response_Short, SDIO_SendCommand(), SDIO_STD_CAPACITY_SD_CARD_V1_1, SDIO_STD_CAPACITY_SD_CARD_V2_0, SDIO_CmdInitTypeDef::SDIO_Wait, and SDIO_Wait_No.

Referenced by SD_EraseTest().

SD_Error SD_GetCardInfo ( SD_CardInfo * cardinfo )

Returns information about specific card.

Parameters:
cardinfo,: pointer to a SD_CardInfo structure that contains all SD card information.
Return values:
SD_Error,: SD Card Error code.

< Byte 0

< Byte 1

< Byte 2

< Byte 3

< Byte 4

< Byte 5

< Byte 6

< Reserved

< Byte 7

< Byte 8

< Byte 9

< Byte 10

< Byte 7

< Byte 8

< Byte 9

< Byte 10

< Byte 11

< Byte 12

< Byte 13

< Byte 14

< Byte 15

< Byte 0

< Byte 1

< Byte 2

< Byte 3

< Byte 4

< Byte 5

< Byte 6

< Byte 7

< Byte 8

< Byte 9

< Byte 10

< Byte 11

< Byte 12

< Byte 13

< Byte 14

< Byte 15

Definition at line 749 of file stm32_eval_sdio_sd.c.

Referenced by SD_Init().

SD_Error SD_GetCardStatus ( SD_CardStatus * cardstatus )

Enables wide bus opeartion for the requeseted card if supported by card.

Parameters:
WideMode,: Specifies the SD card wide bus mode. This parameter can be one of the following values:

  • SDIO_BusWide_8b: 8-bit data transfer (Only for MMC)
  • SDIO_BusWide_4b: 4-bit data transfer
  • SDIO_BusWide_1b: 1-bit data transfer
Return values:
SD_Error,: SD Card Error code.

< Byte 0

< Byte 2

< Byte 3

< Byte 4

< Byte 5

< Byte 6

< Byte 7

< Byte 8

< Byte 9

< Byte 10

< Byte 11

< Byte 12

< Byte 13

< Byte 13

Definition at line 961 of file stm32_eval_sdio_sd.c.

References SD_CardStatus::AU_SIZE, SD_CardStatus::DAT_BUS_WIDTH, SD_CardStatus::ERASE_OFFSET, SD_CardStatus::ERASE_SIZE, SD_CardStatus::ERASE_TIMEOUT, SD_CardStatus::PERFORMANCE_MOVE, SD_CardStatus::SD_CARD_TYPE, SD_OK, SD_SendSDStatus(), SDSTATUS_Tab, SD_CardStatus::SECURED_MODE, SD_CardStatus::SIZE_OF_PROTECTED_AREA, and SD_CardStatus::SPEED_CLASS.

SDCardState SD_GetState ( void )

Returns the current card's state.

Parameters:
None
Return values:
SDCardState,: SD Card Error or SD Card Current State.

Definition at line 456 of file stm32_eval_sdio_sd.c.

References SD_CARD_ERROR, SD_Detect(), SD_OK, SD_PRESENT, and SD_SendStatus().

Referenced by SD_GetStatus().

SDTransferState SD_GetStatus ( void )

Gets the cuurent sd card data transfer status.

Parameters:
None
Return values:
SDTransferState,: Data Transfer state. This value can be:

  • SD_TRANSFER_OK: No data transfer is acting
  • SD_TRANSFER_BUSY: Data transfer is acting

Definition at line 431 of file stm32_eval_sdio_sd.c.

Referenced by SD_EraseTest(), SD_MultiBlockTest(), and SD_SingleBlockTest().

SDTransferState SD_GetTransferState ( void )

Gets the cuurent data transfer state.

Parameters:
None
Return values:
SDTransferState,: Data Transfer state. This value can be:

  • SD_TRANSFER_OK: No data transfer is acting
  • SD_TRANSFER_BUSY: Data transfer is acting

Definition at line 1578 of file stm32_eval_sdio_sd.c.

References SD_TRANSFER_BUSY, SD_TRANSFER_OK, SDIO, SDIO_FLAG_RXACT, and SDIO_FLAG_TXACT.

SD_Error SD_Init ( void )

Initializes the SD Card and put it into StandBy State (Ready for data transfer).

Parameters:
None
Return values:
SD_Error,: SD Card Error code.

< CMD Response TimeOut (wait for CMDSENT flag)

< CMD Response TimeOut (wait for CMDSENT flag)

< SDIOCLK = HCLK, SDIO_CK = HCLK/(2 + SDIO_TRANSFER_CLK_DIV)

< on STM32F2xx devices, SDIOCLK is fixed to 48MHz

Definition at line 367 of file stm32_eval_sdio_sd.c.

Referenced by main().

SD_Error SD_InitializeCards ( void )

Intialises all cards or single card as the case may be Card(s) come into standby state.

Parameters:
None
Return values:
SD_Error,: SD Card Error code.

< Send CMD2 ALL_SEND_CID

< Send CMD3 SET_REL_ADDR with argument 0

< SD Card publishes its RCA.

< Send CMD9 SEND_CSD with argument as card's RCA

< All cards get intialized

Definition at line 660 of file stm32_eval_sdio_sd.c.

References CardType, CID_Tab, CmdResp2Error(), CmdResp6Error(), CSD_Tab, RCA, SD_CMD_ALL_SEND_CID, SD_CMD_SEND_CSD, SD_CMD_SET_REL_ADDR, SD_OK, SD_REQUEST_NOT_APPLICABLE, SDIO_CmdInitTypeDef::SDIO_Argument, SDIO_CmdInitTypeDef::SDIO_CmdIndex, SDIO_CmdInitTypeDef::SDIO_CPSM, SDIO_CPSM_Enable, SDIO_GetPowerState(), SDIO_GetResponse(), SDIO_HIGH_CAPACITY_SD_CARD, SDIO_PowerState_OFF, SDIO_RESP1, SDIO_RESP2, SDIO_RESP3, SDIO_RESP4, SDIO_CmdInitTypeDef::SDIO_Response, SDIO_Response_Long, SDIO_Response_Short, SDIO_SECURE_DIGITAL_IO_CARD, SDIO_SECURE_DIGITAL_IO_COMBO_CARD, SDIO_SendCommand(), SDIO_STD_CAPACITY_SD_CARD_V1_1, SDIO_STD_CAPACITY_SD_CARD_V2_0, SDIO_CmdInitTypeDef::SDIO_Wait, and SDIO_Wait_No.

Referenced by SD_Init().

SD_Error SD_PowerOFF ( void )

Turns the SDIO output signals off.

Parameters:
None
Return values:
SD_Error,: SD Card Error code.

< Set Power State to OFF

Definition at line 644 of file stm32_eval_sdio_sd.c.

References SD_OK, SDIO_PowerState_OFF, and SDIO_SetPowerState().

SD_Error SD_PowerON ( void )

Enquires cards about their operating voltage and configures clock controls.

Parameters:
None
Return values:
SD_Error,: SD Card Error code.

< Power ON Sequence -----------------------------------------------------

< Configure the SDIO peripheral

< SDIOCLK = HCLK, SDIO_CK = HCLK/(2 + SDIO_INIT_CLK_DIV)

< on STM32F2xx devices, SDIOCLK is fixed to 48MHz

< SDIO_CK for initialization should not exceed 400 KHz

< Set Power State to ON

< Enable SDIO Clock

< CMD0: GO_IDLE_STATE ---------------------------------------------------

< No CMD response required

< CMD Response TimeOut (wait for CMDSENT flag)

< Send CMD8 to verify SD card interface operating condition

< Argument: - [31:12]: Reserved (shall be set to '0')

  • [11:8]: Supply Voltage (VHS) 0x1 (Range: 2.7-3.6 V)
  • [7:0]: Check Pattern (recommended 0xAA)

< CMD Response: R7

< SD Card 2.0

< CMD55

< If errorstatus is Command TimeOut, it is a MMC card

< If errorstatus is SD_OK it is a SD card: SD card 2.0 (voltage range mismatch) or SD card 1.x

< SD CARD

< Send ACMD41 SD_APP_OP_COND with Argument 0x80100000

< SEND CMD55 APP_CMD with RCA as 0

Definition at line 500 of file stm32_eval_sdio_sd.c.

References CardType, CmdError(), CmdResp1Error(), CmdResp3Error(), CmdResp7Error(), ENABLE, SD_CHECK_PATTERN, SD_CMD_APP_CMD, SD_CMD_GO_IDLE_STATE, SD_CMD_SD_APP_OP_COND, SD_HIGH_CAPACITY, SD_INVALID_VOLTRANGE, SD_MAX_VOLT_TRIAL, SD_OK, SD_STD_CAPACITY, SD_VOLTAGE_WINDOW_SD, SDIO_CmdInitTypeDef::SDIO_Argument, SDIO_InitTypeDef::SDIO_BusWide, SDIO_BusWide_1b, SDIO_InitTypeDef::SDIO_ClockBypass, SDIO_ClockBypass_Disable, SDIO_ClockCmd(), SDIO_InitTypeDef::SDIO_ClockDiv, SDIO_InitTypeDef::SDIO_ClockEdge, SDIO_ClockEdge_Rising, SDIO_InitTypeDef::SDIO_ClockPowerSave, SDIO_ClockPowerSave_Disable, SDIO_CmdInitTypeDef::SDIO_CmdIndex, SDIO_CmdInitTypeDef::SDIO_CPSM, SDIO_CPSM_Enable, SDIO_GetResponse(), SDIO_InitTypeDef::SDIO_HardwareFlowControl, SDIO_HardwareFlowControl_Disable, SDIO_HIGH_CAPACITY_SD_CARD, SDIO_Init(), SDIO_INIT_CLK_DIV, SDIO_PowerState_ON, SDIO_RESP1, SDIO_CmdInitTypeDef::SDIO_Response, SDIO_Response_No, SDIO_Response_Short, SDIO_SEND_IF_COND, SDIO_SendCommand(), SDIO_SetPowerState(), SDIO_STD_CAPACITY_SD_CARD_V2_0, SDIO_CmdInitTypeDef::SDIO_Wait, and SDIO_Wait_No.

Referenced by SD_Init().

SD_Error SD_ProcessIRQSrc ( void )

Allows to process all the interrupts that are high.

Parameters:
None
Return values:
SD_Error,: SD Card Error code.

Definition at line 1848 of file stm32_eval_sdio_sd.c.

References CmdResp1Error(), DISABLE, SD_CMD_STOP_TRANSMISSION, SD_OK, SDIO, SDIO_ClearITPendingBit(), SDIO_IT_DATAEND, SDIO_ITConfig(), StopCondition, TransferEnd, and TransferError.

Referenced by SDIO_IRQHandler().

SD_Error SD_ReadBlock | ( | uint8_t * | readbuff,
 |  | uint32_t | ReadAddr,
 |  | uint16_t | BlockSize
 | ) |  |

Allows to read one block from a specified address in a card.

The Data transfer can be managed by DMA mode or Polling mode.

Note:
This operation should be followed by two functions to check if the DMA Controller and SD Card status.
  • SD_ReadWaitOperation(): this function insure that the DMA controller has finished all data transfer.
  • SD_GetStatus(): to check that the SD Card has finished the data transfer and it is ready for data.
Parameters:
readbuff,: pointer to the buffer that will contain the received data
ReadAddr,: Address from where data are to be read.
BlockSize,: the SD card Data block size. The Block size should be 512.
Return values:
SD_Error,: SD Card Error code.

< Send CMD17 READ_SINGLE_BLOCK

Definition at line 1136 of file stm32_eval_sdio_sd.c.

Referenced by SD_SingleBlockTest().

SD_Error SD_ReadMultiBlocks | ( | uint8_t * | readbuff,
 |  | uint32_t | ReadAddr,
 |  | uint16_t | BlockSize,
 |  | uint32_t | NumberOfBlocks
 | ) |  |

Allows to read blocks from a specified address in a card.

The Data transfer can be managed by DMA mode or Polling mode.

Note:
This operation should be followed by two functions to check if the DMA Controller and SD Card status.
  • SD_ReadWaitOperation(): this function insure that the DMA controller has finished all data transfer.
  • SD_GetStatus(): to check that the SD Card has finished the data transfer and it is ready for data.
Parameters:
readbuff,: pointer to the buffer that will contain the received data.
ReadAddr,: Address from where data are to be read.
BlockSize,: the SD card Data block size. The Block size should be 512.
NumberOfBlocks,: number of blocks to be read.
Return values:
SD_Error,: SD Card Error code.

< Send CMD18 READ_MULT_BLOCK with argument data address

Definition at line 1251 of file stm32_eval_sdio_sd.c.

Referenced by SD_EraseTest(), and SD_MultiBlockTest().

SD_Error SD_SelectDeselect ( uint32_t addr )

Selects od Deselects the corresponding card.

Parameters:
addr,: Address of the Card to be selected.
Return values:
SD_Error,: SD Card Error code.

< Send CMD7 SDIO_SEL_DESEL_CARD

Definition at line 1105 of file stm32_eval_sdio_sd.c.

References CmdResp1Error(), SD_CMD_SEL_DESEL_CARD, SD_OK, SDIO_CmdInitTypeDef::SDIO_Argument, SDIO_CmdInitTypeDef::SDIO_CmdIndex, SDIO_CmdInitTypeDef::SDIO_CPSM, SDIO_CPSM_Enable, SDIO_CmdInitTypeDef::SDIO_Response, SDIO_Response_Short, SDIO_SendCommand(), SDIO_CmdInitTypeDef::SDIO_Wait, and SDIO_Wait_No.

Referenced by SD_Init().

SD_Error SD_SendSDStatus ( uint32_t * psdstatus )

Returns the current SD card's status.

Parameters:
psdstatus,: pointer to the buffer that will contain the SD card status (SD Status register).
Return values:
SD_Error,: SD Card Error code.

< Send ACMD13 SD_APP_STAUS with argument as card's RCA.

Definition at line 1732 of file stm32_eval_sdio_sd.c.

References CmdResp1Error(), RCA, RESET, SD_CARD_LOCKED, SD_CMD_APP_CMD, SD_CMD_SD_APP_STAUS, SD_CMD_SET_BLOCKLEN, SD_DATA_CRC_FAIL, SD_DATA_TIMEOUT, SD_DATATIMEOUT, SD_LOCK_UNLOCK_FAILED, SD_OK, SD_RX_OVERRUN, SD_START_BIT_ERR, SDIO, SDIO_CmdInitTypeDef::SDIO_Argument, SDIO_ClearFlag(), SDIO_CmdInitTypeDef::SDIO_CmdIndex, SDIO_CmdInitTypeDef::SDIO_CPSM, SDIO_CPSM_Enable, SDIO_DataInitTypeDef::SDIO_DataBlockSize, SDIO_DataBlockSize_64b, SDIO_DataConfig(), SDIO_DataInitTypeDef::SDIO_DataLength, SDIO_DataInitTypeDef::SDIO_DataTimeOut, SDIO_DataInitTypeDef::SDIO_DPSM, SDIO_DPSM_Enable, SDIO_FLAG_DBCKEND, SDIO_FLAG_DCRCFAIL, SDIO_FLAG_DTIMEOUT, SDIO_FLAG_RXDAVL, SDIO_FLAG_RXFIFOHF, SDIO_FLAG_RXOVERR, SDIO_FLAG_STBITERR, SDIO_GetFlagStatus(), SDIO_GetResponse(), SDIO_ReadData(), SDIO_RESP1, SDIO_CmdInitTypeDef::SDIO_Response, SDIO_Response_Short, SDIO_SendCommand(), SDIO_STATIC_FLAGS, SDIO_DataInitTypeDef::SDIO_TransferDir, SDIO_TransferDir_ToSDIO, SDIO_DataInitTypeDef::SDIO_TransferMode, SDIO_TransferMode_Block, SDIO_CmdInitTypeDef::SDIO_Wait, and SDIO_Wait_No.

Referenced by SD_GetCardStatus().

SD_Error SD_SendStatus ( uint32_t * pcardstatus )

Returns the current card's status.

Parameters:
pcardstatus,: pointer to the buffer that will contain the SD card status (Card Status register).
Return values:
SD_Error,: SD Card Error code.

Definition at line 1708 of file stm32_eval_sdio_sd.c.

References CmdResp1Error(), RCA, SD_CMD_SEND_STATUS, SD_OK, and SDIO.

Referenced by SD_GetState().

SD_Error SD_StopTransfer ( void )

Aborts an ongoing data transfer.

Parameters:
None
Return values:
SD_Error,: SD Card Error code.

< Send CMD12 STOP_TRANSMISSION

Definition at line 1595 of file stm32_eval_sdio_sd.c.

References CmdResp1Error(), SD_CMD_STOP_TRANSMISSION, SD_OK, and SDIO.

SD_Error SD_WaitReadOperation ( void )

This function waits until the SDIO DMA data transfer is finished.

This function should be called after SDIO_ReadMultiBlocks() function to insure that all data sent by the card are already transferred by the DMA controller.

Parameters:
None.
Return values:
SD_Error,: SD Card Error code.

Definition at line 1319 of file stm32_eval_sdio_sd.c.

References RESET, SD_DMAEndOfTransferStatus(), SD_OK, TransferEnd, and TransferError.

Referenced by SD_EraseTest(), SD_MultiBlockTest(), and SD_SingleBlockTest().

SD_Error SD_WaitWriteOperation ( void )

This function waits until the SDIO DMA data transfer is finished.

This function should be called after SDIO_WriteBlock() and SDIO_WriteMultiBlocks() function to insure that all data sent by the card are already transferred by the DMA controller.

Parameters:
None.
Return values:
SD_Error,: SD Card Error code.

Definition at line 1552 of file stm32_eval_sdio_sd.c.

References RESET, SD_DMAEndOfTransferStatus(), SD_OK, SDIO_ClearFlag(), SDIO_STATIC_FLAGS, TransferEnd, and TransferError.

Referenced by SD_MultiBlockTest(), and SD_SingleBlockTest().

SD_Error SD_WriteBlock | ( | uint8_t * | writebuff,
 |  | uint32_t | WriteAddr,
 |  | uint16_t | BlockSize
 | ) |  |

Allows to write one block starting from a specified address in a card.

The Data transfer can be managed by DMA mode or Polling mode.

Note:
This operation should be followed by two functions to check if the DMA Controller and SD Card status.
  • SD_ReadWaitOperation(): this function insure that the DMA controller has finished all data transfer.
  • SD_GetStatus(): to check that the SD Card has finished the data transfer and it is ready for data.
Parameters:
writebuff,: pointer to the buffer that contain the data to be transferred.
WriteAddr,: Address from where data are to be read.
BlockSize,: the SD card Data block size. The Block size should be 512.
Return values:
SD_Error,: SD Card Error code.

< In case of single data block transfer no need of stop command at all

Definition at line 1348 of file stm32_eval_sdio_sd.c.

Referenced by SD_SingleBlockTest().

SD_Error SD_WriteMultiBlocks | ( | uint8_t * | writebuff,
 |  | uint32_t | WriteAddr,
 |  | uint16_t | BlockSize,
 |  | uint32_t | NumberOfBlocks
 | ) |  |

Allows to write blocks starting from a specified address in a card.

The Data transfer can be managed by DMA mode only.

Note:
This operation should be followed by two functions to check if the DMA Controller and SD Card status.
  • SD_ReadWaitOperation(): this function insure that the DMA controller has finished all data transfer.
  • SD_GetStatus(): to check that the SD Card has finished the data transfer and it is ready for data.
Parameters:
WriteAddr,: Address from where data are to be read.
writebuff,: pointer to the buffer that contain the data to be transferred.
BlockSize,: the SD card Data block size. The Block size should be 512.
NumberOfBlocks,: number of blocks to be written.
Return values:
SD_Error,: SD Card Error code.

Definition at line 1466 of file stm32_eval_sdio_sd.c.

Referenced by SD_MultiBlockTest().

static SD_Error SDEnWideBus ( FunctionalState NewState ) [static]

Enables or disables the SDIO wide bus mode.

Parameters:
NewState,: new state of the SDIO wide bus mode. This parameter can be: ENABLE or DISABLE.
Return values:
SD_Error,: SD Card Error code.

< If requested card supports wide bus operation

< Send CMD55 APP_CMD with argument as card's RCA.

< If requested card supports 1 bit mode operation

< Send CMD55 APP_CMD with argument as card's RCA.

Definition at line 2088 of file stm32_eval_sdio_sd.c.

References CmdResp1Error(), ENABLE, FindSCR(), RCA, SD_ALLZERO, SD_CARD_LOCKED, SD_CMD_APP_CMD, SD_CMD_APP_SD_SET_BUSWIDTH, SD_LOCK_UNLOCK_FAILED, SD_OK, SD_REQUEST_NOT_APPLICABLE, SD_SINGLE_BUS_SUPPORT, SD_WIDE_BUS_SUPPORT, SDIO_CmdInitTypeDef::SDIO_Argument, SDIO_CmdInitTypeDef::SDIO_CmdIndex, SDIO_CmdInitTypeDef::SDIO_CPSM, SDIO_CPSM_Enable, SDIO_GetResponse(), SDIO_RESP1, SDIO_CmdInitTypeDef::SDIO_Response, SDIO_Response_Short, SDIO_SendCommand(), SDIO_CmdInitTypeDef::SDIO_Wait, and SDIO_Wait_No.

Referenced by SD_EnableWideBusOperation().


STM32F10x Standard Peripherals Firmware Library: STM32_EVAL_SDIO_SD_Exported_Types

Data Structures | Enumerations

STM32_EVAL_SDIO_SD_Exported_Types

STM32_EVAL_SDIO_SD

Data Structures

struct | SD_CardInfo
SD Card information. More...
struct | SD_CardStatus
SD Card Status. More...
struct | SD_CID
Card Identification Data: CID Register. More...
struct | SD_CSD
Card Specific Data: CSD Register. More...

Enumerations

enum SD_Error {
SD_CMD_CRC_FAIL = (1), SD_DATA_CRC_FAIL = (2), SD_CMD_RSP_TIMEOUT = (3), SD_DATA_TIMEOUT = (4),
SD_TX_UNDERRUN = (5), SD_RX_OVERRUN = (6), SD_START_BIT_ERR = (7), SD_CMD_OUT_OF_RANGE = (8),
SD_ADDR_MISALIGNED = (9), SD_BLOCK_LEN_ERR = (10), SD_ERASE_SEQ_ERR = (11), SD_BAD_ERASE_PARAM = (12),
SD_WRITE_PROT_VIOLATION = (13), SD_LOCK_UNLOCK_FAILED = (14), SD_COM_CRC_FAILED = (15), SD_ILLEGAL_CMD = (16),
SD_CARD_ECC_FAILED = (17), SD_CC_ERROR = (18), SD_GENERAL_UNKNOWN_ERROR = (19), SD_STREAM_READ_UNDERRUN = (20),
SD_STREAM_WRITE_OVERRUN = (21), SD_CID_CSD_OVERWRITE = (22), SD_WP_ERASE_SKIP = (23), SD_CARD_ECC_DISABLED = (24),
SD_ERASE_RESET = (25), SD_AKE_SEQ_ERROR = (26), SD_INVALID_VOLTRANGE = (27), SD_ADDR_OUT_OF_RANGE = (28),
SD_SWITCH_ERROR = (29), SD_SDIO_DISABLED = (30), SD_SDIO_FUNCTION_BUSY = (31), SD_SDIO_FUNCTION_FAILED = (32),
SD_SDIO_UNKNOWN_FUNCTION = (33), SD_INTERNAL_ERROR, SD_NOT_CONFIGURED, SD_REQUEST_PENDING,
SD_REQUEST_NOT_APPLICABLE, SD_INVALID_PARAMETER, SD_UNSUPPORTED_FEATURE, SD_UNSUPPORTED_HW,
SD_ERROR, SD_OK = 0, SD_RESPONSE_NO_ERROR = (0x00), SD_IN_IDLE_STATE = (0x01),
SD_ERASE_RESET = (0x02), SD_ILLEGAL_COMMAND = (0x04), SD_COM_CRC_ERROR = (0x08), SD_ERASE_SEQUENCE_ERROR = (0x10),
SD_ADDRESS_ERROR = (0x20), SD_PARAMETER_ERROR = (0x40), SD_RESPONSE_FAILURE = (0xFF), SD_DATA_OK = (0x05),
SD_DATA_CRC_ERROR = (0x0B), SD_DATA_WRITE_ERROR = (0x0D), SD_DATA_OTHER_ERROR = (0xFF)
}
enum SDCardState {
SD_CARD_READY = ((uint32_t)0x00000001), SD_CARD_IDENTIFICATION = ((uint32_t)0x00000002), SD_CARD_STANDBY = ((uint32_t)0x00000003), SD_CARD_TRANSFER = ((uint32_t)0x00000004),
SD_CARD_SENDING = ((uint32_t)0x00000005), SD_CARD_RECEIVING = ((uint32_t)0x00000006), SD_CARD_PROGRAMMING = ((uint32_t)0x00000007), SD_CARD_DISCONNECTED = ((uint32_t)0x00000008),
SD_CARD_ERROR = ((uint32_t)0x000000FF)
}

SD Card States.

More...
enum | SDTransferState { SD_TRANSFER_OK = 0, SD_TRANSFER_BUSY = 1, SD_TRANSFER_ERROR }

SDIO Transfer state.

More...

Enumeration Type Documentation

enum SD_Error
Enumerator:
SD_CMD_CRC_FAIL

SDIO specific error defines.

Command response received (but CRC check failed)

SD_DATA_CRC_FAIL

Data bock sent/received (CRC check Failed)

SD_CMD_RSP_TIMEOUT

Command response timeout

SD_DATA_TIMEOUT

Data time out

SD_TX_UNDERRUN

Transmit FIFO under-run

SD_RX_OVERRUN

Receive FIFO over-run

SD_START_BIT_ERR

Start bit not detected on all data signals in widE bus mode

SD_CMD_OUT_OF_RANGE

CMD's argument was out of range.

SD_ADDR_MISALIGNED

Misaligned address

SD_BLOCK_LEN_ERR

Transferred block length is not allowed for the card or the number of transferred bytes does not match the block length

SD_ERASE_SEQ_ERR

An error in the sequence of erase command occurs.

SD_BAD_ERASE_PARAM

An Invalid selection for erase groups

SD_WRITE_PROT_VIOLATION

Attempt to program a write protect block

SD_LOCK_UNLOCK_FAILED

Sequence or password error has been detected in unlock command or if there was an attempt to access a locked card

SD_COM_CRC_FAILED

CRC check of the previous command failed

SD_ILLEGAL_CMD

Command is not legal for the card state

SD_CARD_ECC_FAILED

Card internal ECC was applied but failed to correct the data

SD_CC_ERROR

Internal card controller error

SD_GENERAL_UNKNOWN_ERROR

General or Unknown error

SD_STREAM_READ_UNDERRUN

The card could not sustain data transfer in stream read operation.

SD_STREAM_WRITE_OVERRUN

The card could not sustain data programming in stream mode

SD_CID_CSD_OVERWRITE

CID/CSD overwrite error

SD_WP_ERASE_SKIP

only partial address space was erased

SD_CARD_ECC_DISABLED

Command has been executed without using internal ECC

SD_ERASE_RESET

Erase sequence was cleared before executing because an out of erase sequence command was received

SD_AKE_SEQ_ERROR

Error in sequence of authentication.

SD_INVALID_VOLTRANGE
SD_ADDR_OUT_OF_RANGE
SD_SWITCH_ERROR
SD_SDIO_DISABLED
SD_SDIO_FUNCTION_BUSY
SD_SDIO_FUNCTION_FAILED
SD_SDIO_UNKNOWN_FUNCTION
SD_INTERNAL_ERROR

Standard error defines.

SD_NOT_CONFIGURED
SD_REQUEST_PENDING
SD_REQUEST_NOT_APPLICABLE
SD_INVALID_PARAMETER
SD_UNSUPPORTED_FEATURE
SD_UNSUPPORTED_HW
SD_ERROR
SD_OK
SD_RESPONSE_NO_ERROR

SD reponses and error flags.

SD_IN_IDLE_STATE
SD_ERASE_RESET
SD_ILLEGAL_COMMAND
SD_COM_CRC_ERROR
SD_ERASE_SEQUENCE_ERROR
SD_ADDRESS_ERROR
SD_PARAMETER_ERROR
SD_RESPONSE_FAILURE
SD_DATA_OK

Data response error.

SD_DATA_CRC_ERROR
SD_DATA_WRITE_ERROR
SD_DATA_OTHER_ERROR

Definition at line 53 of file stm32_eval_sdio_sd.h.

enum SDCardState

SD Card States.

Enumerator:
SD_CARD_READY
SD_CARD_IDENTIFICATION
SD_CARD_STANDBY
SD_CARD_TRANSFER
SD_CARD_SENDING
SD_CARD_RECEIVING
SD_CARD_PROGRAMMING
SD_CARD_DISCONNECTED
SD_CARD_ERROR

Definition at line 119 of file stm32_eval_sdio_sd.h.

enum SDTransferState

SDIO Transfer state.

Enumerator:
SD_TRANSFER_OK
SD_TRANSFER_BUSY
SD_TRANSFER_ERROR

Definition at line 109 of file stm32_eval_sdio_sd.h.


STM32F10x Standard Peripherals Firmware Library: SD_CardInfo Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

SD_CardInfo Struct Reference
STM32_EVAL_SDIO_SD_Exported_Types | STM32_EVAL_SPI_SD_Exported_Types

SD Card information. More...

#include <stm32_eval_sdio_sd.h>

Data Fields

uint32_t | CardBlockSize
uint32_t | CardCapacity
uint8_t | CardType
uint16_t | RCA
SD_CID SD_cid
SD_CSD SD_csd

Detailed Description

SD Card information.

Definition at line 215 of file stm32_eval_sdio_sd.h.

Field Documentation

uint32_t SD_CardInfo::CardBlockSize

Card Block Size

Definition at line 220 of file stm32_eval_sdio_sd.h.

Referenced by SD_GetCardInfo().

uint32_t SD_CardInfo::CardCapacity

Card Capacity

Definition at line 219 of file stm32_eval_sdio_sd.h.

Referenced by SD_GetCardInfo().

uint8_t SD_CardInfo::CardType

Definition at line 222 of file stm32_eval_sdio_sd.h.

Referenced by SD_GetCardInfo().

uint16_t SD_CardInfo::RCA

Definition at line 221 of file stm32_eval_sdio_sd.h.

Referenced by SD_GetCardInfo(), and SD_Init().

SD_CID SD_CardInfo::SD_cid

Definition at line 218 of file stm32_eval_sdio_sd.h.

Referenced by SD_GetCardInfo().

SD_CSD SD_CardInfo::SD_csd

Definition at line 217 of file stm32_eval_sdio_sd.h.

Referenced by SD_GetCardInfo().

The documentation for this struct was generated from the following files:
  • stm32_eval_sdio_sd.h
  • stm32_eval_spi_sd.h


STM32F10x Standard Peripherals Firmware Library: SD_CardStatus Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

SD_CardStatus Struct Reference
STM32_EVAL_SDIO_SD_Exported_Types

SD Card Status. More...

#include <stm32_eval_sdio_sd.h>

Data Fields

__IO uint8_t | AU_SIZE
__IO uint8_t | DAT_BUS_WIDTH
__IO uint8_t | ERASE_OFFSET
__IO uint16_t | ERASE_SIZE
__IO uint8_t | ERASE_TIMEOUT
__IO uint8_t | PERFORMANCE_MOVE
__IO uint16_t | SD_CARD_TYPE
__IO uint8_t | SECURED_MODE
__IO uint32_t | SIZE_OF_PROTECTED_AREA
__IO uint8_t | SPEED_CLASS

Detailed Description

SD Card Status.

Definition at line 197 of file stm32_eval_sdio_sd.h.

Field Documentation

__IO uint8_t SD_CardStatus::AU_SIZE

Definition at line 205 of file stm32_eval_sdio_sd.h.

Referenced by SD_GetCardStatus().

__IO uint8_t SD_CardStatus::DAT_BUS_WIDTH

Definition at line 199 of file stm32_eval_sdio_sd.h.

Referenced by SD_GetCardStatus().

__IO uint8_t SD_CardStatus::ERASE_OFFSET

Definition at line 208 of file stm32_eval_sdio_sd.h.

Referenced by SD_GetCardStatus().

__IO uint16_t SD_CardStatus::ERASE_SIZE

Definition at line 206 of file stm32_eval_sdio_sd.h.

Referenced by SD_GetCardStatus().

__IO uint8_t SD_CardStatus::ERASE_TIMEOUT

Definition at line 207 of file stm32_eval_sdio_sd.h.

Referenced by SD_GetCardStatus().

__IO uint8_t SD_CardStatus::PERFORMANCE_MOVE

Definition at line 204 of file stm32_eval_sdio_sd.h.

Referenced by SD_GetCardStatus().

__IO uint16_t SD_CardStatus::SD_CARD_TYPE

Definition at line 201 of file stm32_eval_sdio_sd.h.

Referenced by SD_GetCardStatus().

__IO uint8_t SD_CardStatus::SECURED_MODE

Definition at line 200 of file stm32_eval_sdio_sd.h.

Referenced by SD_GetCardStatus().

__IO uint32_t SD_CardStatus::SIZE_OF_PROTECTED_AREA

Definition at line 202 of file stm32_eval_sdio_sd.h.

Referenced by SD_GetCardStatus().

__IO uint8_t SD_CardStatus::SPEED_CLASS

Definition at line 203 of file stm32_eval_sdio_sd.h.

Referenced by SD_GetCardStatus().

The documentation for this struct was generated from the following file:
  • stm32_eval_sdio_sd.h


STM32F10x Standard Peripherals Firmware Library: SD_CID Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

SD_CID Struct Reference
STM32_EVAL_SDIO_SD_Exported_Types | STM32_EVAL_SPI_SD_Exported_Types

Card Identification Data: CID Register. More...

#include <stm32_eval_sdio_sd.h>

Data Fields

__IO uint8_t | CID_CRC
__IO uint16_t | ManufactDate
__IO uint8_t | ManufacturerID
__IO uint16_t | OEM_AppliID
__IO uint32_t | ProdName1
__IO uint8_t | ProdName2
__IO uint8_t | ProdRev
__IO uint32_t | ProdSN
__IO uint8_t | Reserved1
__IO uint8_t | Reserved2

Detailed Description

Card Identification Data: CID Register.

Definition at line 180 of file stm32_eval_sdio_sd.h.

Field Documentation

__IO uint8_t SD_CID::CID_CRC

CID CRC

Definition at line 190 of file stm32_eval_sdio_sd.h.

Referenced by SD_GetCardInfo(), and SD_GetCIDRegister().

__IO uint16_t SD_CID::ManufactDate

Manufacturing Date

Definition at line 189 of file stm32_eval_sdio_sd.h.

Referenced by SD_GetCardInfo(), and SD_GetCIDRegister().

__IO uint8_t SD_CID::ManufacturerID

ManufacturerID

Definition at line 182 of file stm32_eval_sdio_sd.h.

Referenced by SD_GetCardInfo(), and SD_GetCIDRegister().

__IO uint16_t SD_CID::OEM_AppliID

OEM/Application ID

Definition at line 183 of file stm32_eval_sdio_sd.h.

Referenced by SD_GetCardInfo(), and SD_GetCIDRegister().

__IO uint32_t SD_CID::ProdName1

Product Name part1

Definition at line 184 of file stm32_eval_sdio_sd.h.

Referenced by SD_GetCardInfo(), and SD_GetCIDRegister().

__IO uint8_t SD_CID::ProdName2

Product Name part2

Definition at line 185 of file stm32_eval_sdio_sd.h.

Referenced by SD_GetCardInfo(), and SD_GetCIDRegister().

__IO uint8_t SD_CID::ProdRev

Product Revision

Definition at line 186 of file stm32_eval_sdio_sd.h.

Referenced by SD_GetCardInfo(), and SD_GetCIDRegister().

__IO uint32_t SD_CID::ProdSN

Product Serial Number

Definition at line 187 of file stm32_eval_sdio_sd.h.

Referenced by SD_GetCardInfo(), and SD_GetCIDRegister().

__IO uint8_t SD_CID::Reserved1

Reserved1

Definition at line 188 of file stm32_eval_sdio_sd.h.

Referenced by SD_GetCardInfo(), and SD_GetCIDRegister().

__IO uint8_t SD_CID::Reserved2

always 1

Definition at line 191 of file stm32_eval_sdio_sd.h.

Referenced by SD_GetCardInfo(), and SD_GetCIDRegister().

The documentation for this struct was generated from the following files:
  • stm32_eval_sdio_sd.h
  • stm32_eval_spi_sd.h


STM32F10x Standard Peripherals Firmware Library: SD_CSD Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

SD_CSD Struct Reference
STM32_EVAL_SDIO_SD_Exported_Types | STM32_EVAL_SPI_SD_Exported_Types

Card Specific Data: CSD Register. More...

#include <stm32_eval_sdio_sd.h>

Data Fields

__IO uint16_t | CardComdClasses
__IO uint8_t | ContentProtectAppli
__IO uint8_t | CopyFlag
__IO uint8_t | CSD_CRC
__IO uint8_t | CSDStruct
__IO uint32_t | DeviceSize
__IO uint8_t | DeviceSizeMul
__IO uint8_t | DSRImpl
__IO uint8_t | ECC
__IO uint8_t | EraseGrMul
__IO uint8_t | EraseGrSize
__IO uint8_t | FileFormat
__IO uint8_t | FileFormatGrouop
__IO uint8_t | ManDeflECC
__IO uint8_t | MaxBusClkFrec
__IO uint8_t | MaxRdCurrentVDDMax
__IO uint8_t | MaxRdCurrentVDDMin
__IO uint8_t | MaxWrBlockLen
__IO uint8_t | MaxWrCurrentVDDMax
__IO uint8_t | MaxWrCurrentVDDMin
__IO uint8_t | NSAC
__IO uint8_t | PartBlockRead
__IO uint8_t | PermWrProtect
__IO uint8_t | RdBlockLen
__IO uint8_t | RdBlockMisalign
__IO uint8_t | Reserved1
__IO uint8_t | Reserved2
__IO uint8_t | Reserved3
__IO uint8_t | Reserved4
__IO uint8_t | SysSpecVersion
__IO uint8_t | TAAC
__IO uint8_t | TempWrProtect
__IO uint8_t | WrBlockMisalign
__IO uint8_t | WriteBlockPaPartial
__IO uint8_t | WrProtectGrEnable
__IO uint8_t | WrProtectGrSize
__IO uint8_t | WrSpeedFact

Detailed Description

Card Specific Data: CSD Register.

Definition at line 136 of file stm32_eval_sdio_sd.h.

Field Documentation

__IO uint16_t SD_CSD::CardComdClasses

Card command classes

Definition at line 144 of file stm32_eval_sdio_sd.h.

Referenced by SD_GetCardInfo(), and SD_GetCSDRegister().

__IO uint8_t SD_CSD::ContentProtectAppli

Content protection application

Definition at line 166 of file stm32_eval_sdio_sd.h.

Referenced by SD_GetCardInfo(), and SD_GetCSDRegister().

__IO uint8_t SD_CSD::CopyFlag

Copy flag (OTP)

Definition at line 168 of file stm32_eval_sdio_sd.h.

Referenced by SD_GetCardInfo(), and SD_GetCSDRegister().

__IO uint8_t SD_CSD::CSD_CRC

CSD CRC

Definition at line 173 of file stm32_eval_sdio_sd.h.

Referenced by SD_GetCardInfo(), and SD_GetCSDRegister().

__IO uint8_t SD_CSD::CSDStruct

CSD structure

Definition at line 138 of file stm32_eval_sdio_sd.h.

Referenced by SD_GetCardInfo(), and SD_GetCSDRegister().

__IO uint32_t SD_CSD::DeviceSize

Device Size

Definition at line 151 of file stm32_eval_sdio_sd.h.

Referenced by SD_GetCardInfo(), and SD_GetCSDRegister().

__IO uint8_t SD_CSD::DeviceSizeMul

Device size multiplier

Definition at line 156 of file stm32_eval_sdio_sd.h.

Referenced by SD_GetCardInfo(), and SD_GetCSDRegister().

__IO uint8_t SD_CSD::DSRImpl

DSR implemented

Definition at line 149 of file stm32_eval_sdio_sd.h.

Referenced by SD_GetCardInfo(), and SD_GetCSDRegister().

__IO uint8_t SD_CSD::ECC

ECC code

Definition at line 172 of file stm32_eval_sdio_sd.h.

Referenced by SD_GetCardInfo(), and SD_GetCSDRegister().

__IO uint8_t SD_CSD::EraseGrMul

Erase group size multiplier

Definition at line 158 of file stm32_eval_sdio_sd.h.

Referenced by SD_GetCardInfo(), and SD_GetCSDRegister().

__IO uint8_t SD_CSD::EraseGrSize

Erase group size

Definition at line 157 of file stm32_eval_sdio_sd.h.

Referenced by SD_GetCardInfo(), and SD_GetCSDRegister().

__IO uint8_t SD_CSD::FileFormat

File Format

Definition at line 171 of file stm32_eval_sdio_sd.h.

Referenced by SD_GetCardInfo(), and SD_GetCSDRegister().

__IO uint8_t SD_CSD::FileFormatGrouop

File format group

Definition at line 167 of file stm32_eval_sdio_sd.h.

Referenced by SD_GetCardInfo(), and SD_GetCSDRegister().

__IO uint8_t SD_CSD::ManDeflECC

Manufacturer default ECC

Definition at line 161 of file stm32_eval_sdio_sd.h.

Referenced by SD_GetCardInfo(), and SD_GetCSDRegister().

__IO uint8_t SD_CSD::MaxBusClkFrec

Max. bus clock frequency

Definition at line 143 of file stm32_eval_sdio_sd.h.

Referenced by SD_GetCardInfo(), and SD_GetCSDRegister().

__IO uint8_t SD_CSD::MaxRdCurrentVDDMax

Max. read current @ VDD max

Definition at line 153 of file stm32_eval_sdio_sd.h.

Referenced by SD_GetCardInfo(), and SD_GetCSDRegister().

__IO uint8_t SD_CSD::MaxRdCurrentVDDMin

Max. read current @ VDD min

Definition at line 152 of file stm32_eval_sdio_sd.h.

Referenced by SD_GetCardInfo(), and SD_GetCSDRegister().

__IO uint8_t SD_CSD::MaxWrBlockLen

Max. write data block length

Definition at line 163 of file stm32_eval_sdio_sd.h.

Referenced by SD_GetCardInfo(), and SD_GetCSDRegister().

__IO uint8_t SD_CSD::MaxWrCurrentVDDMax

Max. write current @ VDD max

Definition at line 155 of file stm32_eval_sdio_sd.h.

Referenced by SD_GetCardInfo(), and SD_GetCSDRegister().

__IO uint8_t SD_CSD::MaxWrCurrentVDDMin

Max. write current @ VDD min

Definition at line 154 of file stm32_eval_sdio_sd.h.

Referenced by SD_GetCardInfo(), and SD_GetCSDRegister().

__IO uint8_t SD_CSD::NSAC

Data read access-time 2 in CLK cycles

Definition at line 142 of file stm32_eval_sdio_sd.h.

Referenced by SD_GetCardInfo(), and SD_GetCSDRegister().

__IO uint8_t SD_CSD::PartBlockRead

Partial blocks for read allowed

Definition at line 146 of file stm32_eval_sdio_sd.h.

Referenced by SD_GetCardInfo(), and SD_GetCSDRegister().

__IO uint8_t SD_CSD::PermWrProtect

Permanent write protection

Definition at line 169 of file stm32_eval_sdio_sd.h.

Referenced by SD_GetCardInfo(), and SD_GetCSDRegister().

__IO uint8_t SD_CSD::RdBlockLen

Max. read data block length

Definition at line 145 of file stm32_eval_sdio_sd.h.

Referenced by SD_GetCardInfo(), and SD_GetCSDRegister().

__IO uint8_t SD_CSD::RdBlockMisalign

Read block misalignment

Definition at line 148 of file stm32_eval_sdio_sd.h.

Referenced by SD_GetCardInfo(), and SD_GetCSDRegister().

__IO uint8_t SD_CSD::Reserved1

Reserved

Definition at line 140 of file stm32_eval_sdio_sd.h.

Referenced by SD_GetCardInfo(), and SD_GetCSDRegister().

__IO uint8_t SD_CSD::Reserved2

Reserved

Definition at line 150 of file stm32_eval_sdio_sd.h.

Referenced by SD_GetCardInfo(), and SD_GetCSDRegister().

__IO uint8_t SD_CSD::Reserved3

Reserded

Definition at line 165 of file stm32_eval_sdio_sd.h.

Referenced by SD_GetCardInfo(), and SD_GetCSDRegister().

__IO uint8_t SD_CSD::Reserved4

always 1

Definition at line 174 of file stm32_eval_sdio_sd.h.

Referenced by SD_GetCardInfo(), and SD_GetCSDRegister().

__IO uint8_t SD_CSD::SysSpecVersion

System specification version

Definition at line 139 of file stm32_eval_sdio_sd.h.

Referenced by SD_GetCardInfo(), and SD_GetCSDRegister().

__IO uint8_t SD_CSD::TAAC

Data read access-time 1

Definition at line 141 of file stm32_eval_sdio_sd.h.

Referenced by SD_GetCardInfo(), and SD_GetCSDRegister().

__IO uint8_t SD_CSD::TempWrProtect

Temporary write protection

Definition at line 170 of file stm32_eval_sdio_sd.h.

Referenced by SD_GetCardInfo(), and SD_GetCSDRegister().

__IO uint8_t SD_CSD::WrBlockMisalign

Write block misalignment

Definition at line 147 of file stm32_eval_sdio_sd.h.

Referenced by SD_GetCardInfo(), and SD_GetCSDRegister().

__IO uint8_t SD_CSD::WriteBlockPaPartial

Partial blocks for write allowed

Definition at line 164 of file stm32_eval_sdio_sd.h.

Referenced by SD_GetCardInfo(), and SD_GetCSDRegister().

__IO uint8_t SD_CSD::WrProtectGrEnable

Write protect group enable

Definition at line 160 of file stm32_eval_sdio_sd.h.

Referenced by SD_GetCardInfo(), and SD_GetCSDRegister().

__IO uint8_t SD_CSD::WrProtectGrSize

Write protect group size

Definition at line 159 of file stm32_eval_sdio_sd.h.

Referenced by SD_GetCardInfo(), and SD_GetCSDRegister().

__IO uint8_t SD_CSD::WrSpeedFact

Write speed factor

Definition at line 162 of file stm32_eval_sdio_sd.h.

Referenced by SD_GetCardInfo(), and SD_GetCSDRegister().

The documentation for this struct was generated from the following files:
  • stm32_eval_sdio_sd.h
  • stm32_eval_spi_sd.h


STM32F10x Standard Peripherals Firmware Library: STM32_EVAL_SDIO_SD_Exported_Constants

Defines

STM32_EVAL_SDIO_SD_Exported_Constants

STM32_EVAL_SDIO_SD

Defines

#define | SD_CMD_ALL_SEND_CID ((uint8_t)2)
#define | SD_CMD_APP_CMD ((uint8_t)55)
#define | SD_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6)
Following commands are SD Card Specific commands.
#define | SD_CMD_CLR_WRITE_PROT ((uint8_t)29)
#define | SD_CMD_ERASE ((uint8_t)38)
#define | SD_CMD_ERASE_GRP_END ((uint8_t)36)
#define | SD_CMD_ERASE_GRP_START ((uint8_t)35)
#define | SD_CMD_FAST_IO ((uint8_t)39)
#define | SD_CMD_GEN_CMD ((uint8_t)56)
#define | SD_CMD_GO_IDLE_STATE ((uint8_t)0)
SDIO Commands Index.
#define | SD_CMD_GO_INACTIVE_STATE ((uint8_t)15)
#define | SD_CMD_GO_IRQ_STATE ((uint8_t)40)
#define | SD_CMD_HS_BUSTEST_READ ((uint8_t)14)
#define | SD_CMD_HS_BUSTEST_WRITE ((uint8_t)19)
#define | SD_CMD_HS_SEND_EXT_CSD ((uint8_t)8)
#define | SD_CMD_HS_SWITCH ((uint8_t)6)
#define | SD_CMD_LOCK_UNLOCK ((uint8_t)42)
#define | SD_CMD_NO_CMD ((uint8_t)64)
#define | SD_CMD_PROG_CID ((uint8_t)26)
#define | SD_CMD_PROG_CSD ((uint8_t)27)
#define | SD_CMD_READ_DAT_UNTIL_STOP ((uint8_t)11)
#define | SD_CMD_READ_MULT_BLOCK ((uint8_t)18)
#define | SD_CMD_READ_SINGLE_BLOCK ((uint8_t)17)
#define | SD_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49)
#define | SD_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48)
#define | SD_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46)
#define | SD_CMD_SD_APP_GET_MID ((uint8_t)44)
#define | SD_CMD_SD_APP_GET_MKB ((uint8_t)43)
Following commands are SD Card Specific security commands.
#define | SD_CMD_SD_APP_OP_COND ((uint8_t)41)
#define | SD_CMD_SD_APP_SECURE_ERASE ((uint8_t)38)
#define | SD_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18)
#define | SD_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48)
#define | SD_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25)
#define | SD_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22)
#define | SD_CMD_SD_APP_SEND_SCR ((uint8_t)51)
#define | SD_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47)
#define | SD_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45)
#define | SD_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42)
#define | SD_CMD_SD_APP_STAUS ((uint8_t)13)
#define | SD_CMD_SD_ERASE_GRP_END ((uint8_t)33)
#define | SD_CMD_SD_ERASE_GRP_START ((uint8_t)32)
#define | SD_CMD_SDIO_RW_DIRECT ((uint8_t)52)
#define | SD_CMD_SDIO_RW_EXTENDED ((uint8_t)53)
#define | SD_CMD_SDIO_SEN_OP_COND ((uint8_t)5)
#define | SD_CMD_SEL_DESEL_CARD ((uint8_t)7)
#define | SD_CMD_SEND_CID ((uint8_t)10)
#define | SD_CMD_SEND_CSD ((uint8_t)9)
#define | SD_CMD_SEND_OP_COND ((uint8_t)1)
#define | SD_CMD_SEND_STATUS ((uint8_t)13)
#define | SD_CMD_SEND_WRITE_PROT ((uint8_t)30)
#define | SD_CMD_SET_BLOCK_COUNT ((uint8_t)23)
#define | SD_CMD_SET_BLOCKLEN ((uint8_t)16)
#define | SD_CMD_SET_DSR ((uint8_t)4)
#define | SD_CMD_SET_REL_ADDR ((uint8_t)3)
#define | SD_CMD_SET_WRITE_PROT ((uint8_t)28)
#define | SD_CMD_STOP_TRANSMISSION ((uint8_t)12)
#define | SD_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20)
#define | SD_CMD_WRITE_MULT_BLOCK ((uint8_t)25)
#define | SD_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24)
#define | SD_DMA_MODE ((uint32_t)0x00000000)
#define | SD_NOT_PRESENT ((uint8_t)0x00)
#define | SD_PRESENT ((uint8_t)0x01)
SD detection on its memory slot.
#define | SDIO_HIGH_CAPACITY_MMC_CARD ((uint32_t)0x00000007)
#define | SDIO_HIGH_CAPACITY_SD_CARD ((uint32_t)0x00000002)
#define | SDIO_HIGH_SPEED_MULTIMEDIA_CARD ((uint32_t)0x00000005)
#define | SDIO_MULTIMEDIA_CARD ((uint32_t)0x00000003)
#define | SDIO_SECURE_DIGITAL_IO_CARD ((uint32_t)0x00000004)
#define | SDIO_SECURE_DIGITAL_IO_COMBO_CARD ((uint32_t)0x00000006)
#define | SDIO_STD_CAPACITY_SD_CARD_V1_1 ((uint32_t)0x00000000)
Supported SD Memory Cards.
#define | SDIO_STD_CAPACITY_SD_CARD_V2_0 ((uint32_t)0x00000001)

Define Documentation

#define SD_CMD_ALL_SEND_CID ((uint8_t)2)

Definition at line 238 of file stm32_eval_sdio_sd.h.

Referenced by SD_InitializeCards().

#define SD_CMD_APP_CMD ((uint8_t)55)

Definition at line 279 of file stm32_eval_sdio_sd.h.

Referenced by FindSCR(), SD_PowerON(), SD_SendSDStatus(), SD_WriteMultiBlocks(), and SDEnWideBus().

#define SD_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6)

Following commands are SD Card Specific commands.

SDIO_APP_CMD should be sent before sending these commands. For SD Card only

Definition at line 287 of file stm32_eval_sdio_sd.h.

Referenced by SDEnWideBus().

#define SD_CMD_CLR_WRITE_PROT ((uint8_t)29)

Definition at line 263 of file stm32_eval_sdio_sd.h.

#define SD_CMD_ERASE ((uint8_t)38)

Definition at line 275 of file stm32_eval_sdio_sd.h.

Referenced by SD_Erase().

#define SD_CMD_ERASE_GRP_END ((uint8_t)36)

To set the address of the last write block of the continuous range to be erased. (For MMC card only spec 3.31)

Definition at line 272 of file stm32_eval_sdio_sd.h.

#define SD_CMD_ERASE_GRP_START ((uint8_t)35)

To set the address of the first write block to be erased. (For MMC card only spec 3.31)

Definition at line 269 of file stm32_eval_sdio_sd.h.

#define SD_CMD_FAST_IO ((uint8_t)39)

SD Card doesn't support it

Definition at line 276 of file stm32_eval_sdio_sd.h.

#define SD_CMD_GEN_CMD ((uint8_t)56)

Definition at line 280 of file stm32_eval_sdio_sd.h.

#define SD_CMD_GO_IDLE_STATE ((uint8_t)0)

SDIO Commands Index.

Definition at line 236 of file stm32_eval_sdio_sd.h.

Referenced by SD_GoIdleState(), and SD_PowerON().

#define SD_CMD_GO_INACTIVE_STATE ((uint8_t)15)

Definition at line 251 of file stm32_eval_sdio_sd.h.

#define SD_CMD_GO_IRQ_STATE ((uint8_t)40)

SD Card doesn't support it

Definition at line 277 of file stm32_eval_sdio_sd.h.

#define SD_CMD_HS_BUSTEST_READ ((uint8_t)14)

Definition at line 250 of file stm32_eval_sdio_sd.h.

#define SD_CMD_HS_BUSTEST_WRITE ((uint8_t)19)

Definition at line 255 of file stm32_eval_sdio_sd.h.

#define SD_CMD_HS_SEND_EXT_CSD ((uint8_t)8)

Definition at line 244 of file stm32_eval_sdio_sd.h.

#define SD_CMD_HS_SWITCH ((uint8_t)6)

Definition at line 242 of file stm32_eval_sdio_sd.h.

#define SD_CMD_LOCK_UNLOCK ((uint8_t)42)

Definition at line 278 of file stm32_eval_sdio_sd.h.

#define SD_CMD_NO_CMD ((uint8_t)64)

Definition at line 281 of file stm32_eval_sdio_sd.h.

#define SD_CMD_PROG_CID ((uint8_t)26)

reserved for manufacturers

Definition at line 260 of file stm32_eval_sdio_sd.h.

#define SD_CMD_PROG_CSD ((uint8_t)27)

Definition at line 261 of file stm32_eval_sdio_sd.h.

#define SD_CMD_READ_DAT_UNTIL_STOP ((uint8_t)11)

SD Card doesn't support it

Definition at line 247 of file stm32_eval_sdio_sd.h.

#define SD_CMD_READ_MULT_BLOCK ((uint8_t)18)

Definition at line 254 of file stm32_eval_sdio_sd.h.

Referenced by SD_ReadMultiBlocks().

#define SD_CMD_READ_SINGLE_BLOCK ((uint8_t)17)

Definition at line 253 of file stm32_eval_sdio_sd.h.

Referenced by SD_ReadBlock(), and SD_ReadMultiBlocks().

#define SD_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49)

For SD Card only

Definition at line 309 of file stm32_eval_sdio_sd.h.

#define SD_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48)

For SD Card only

Definition at line 305 of file stm32_eval_sdio_sd.h.

#define SD_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46)

For SD Card only

Definition at line 303 of file stm32_eval_sdio_sd.h.

#define SD_CMD_SD_APP_GET_MID ((uint8_t)44)

For SD Card only

Definition at line 301 of file stm32_eval_sdio_sd.h.

#define SD_CMD_SD_APP_GET_MKB ((uint8_t)43)

Following commands are SD Card Specific security commands.

SDIO_APP_CMD should be sent before sending these commands. For SD Card only

Definition at line 300 of file stm32_eval_sdio_sd.h.

#define SD_CMD_SD_APP_OP_COND ((uint8_t)41)

For SD Card only

Definition at line 290 of file stm32_eval_sdio_sd.h.

Referenced by SD_PowerON().

#define SD_CMD_SD_APP_SECURE_ERASE ((uint8_t)38)

For SD Card only

Definition at line 308 of file stm32_eval_sdio_sd.h.

#define SD_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18)

For SD Card only

Definition at line 306 of file stm32_eval_sdio_sd.h.

#define SD_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48)

For SD Card only

Definition at line 310 of file stm32_eval_sdio_sd.h.

#define SD_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25)

For SD Card only

Definition at line 307 of file stm32_eval_sdio_sd.h.

#define SD_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22)

For SD Card only

Definition at line 289 of file stm32_eval_sdio_sd.h.

#define SD_CMD_SD_APP_SEND_SCR ((uint8_t)51)

For SD Card only

Definition at line 292 of file stm32_eval_sdio_sd.h.

Referenced by FindSCR().

#define SD_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47)

For SD Card only

Definition at line 304 of file stm32_eval_sdio_sd.h.

#define SD_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45)

For SD Card only

Definition at line 302 of file stm32_eval_sdio_sd.h.

#define SD_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42)

For SD Card only

Definition at line 291 of file stm32_eval_sdio_sd.h.

#define SD_CMD_SD_APP_STAUS ((uint8_t)13)

For SD Card only

Definition at line 288 of file stm32_eval_sdio_sd.h.

Referenced by SD_SendSDStatus().

#define SD_CMD_SD_ERASE_GRP_END ((uint8_t)33)

To set the address of the last write block of the continuous range to be erased. (For SD card only)

Definition at line 267 of file stm32_eval_sdio_sd.h.

Referenced by SD_Erase().

#define SD_CMD_SD_ERASE_GRP_START ((uint8_t)32)

To set the address of the first write block to be erased. (For SD card only)

Definition at line 265 of file stm32_eval_sdio_sd.h.

Referenced by SD_Erase().

#define SD_CMD_SDIO_RW_DIRECT ((uint8_t)52)

For SD I/O Card only

Definition at line 293 of file stm32_eval_sdio_sd.h.

#define SD_CMD_SDIO_RW_EXTENDED ((uint8_t)53)

For SD I/O Card only

Definition at line 294 of file stm32_eval_sdio_sd.h.

#define SD_CMD_SDIO_SEN_OP_COND ((uint8_t)5)

Definition at line 241 of file stm32_eval_sdio_sd.h.

#define SD_CMD_SEL_DESEL_CARD ((uint8_t)7)

Definition at line 243 of file stm32_eval_sdio_sd.h.

Referenced by SD_SelectDeselect().

#define SD_CMD_SEND_CID ((uint8_t)10)

Definition at line 246 of file stm32_eval_sdio_sd.h.

Referenced by SD_GetCIDRegister().

#define SD_CMD_SEND_CSD ((uint8_t)9)

Definition at line 245 of file stm32_eval_sdio_sd.h.

Referenced by SD_GetCSDRegister(), and SD_InitializeCards().

#define SD_CMD_SEND_OP_COND ((uint8_t)1)

Definition at line 237 of file stm32_eval_sdio_sd.h.

Referenced by SD_GoIdleState().

#define SD_CMD_SEND_STATUS ((uint8_t)13)

Definition at line 249 of file stm32_eval_sdio_sd.h.

Referenced by IsCardProgramming(), SD_GetStatus(), and SD_SendStatus().

#define SD_CMD_SEND_WRITE_PROT ((uint8_t)30)

Definition at line 264 of file stm32_eval_sdio_sd.h.

#define SD_CMD_SET_BLOCK_COUNT ((uint8_t)23)

SD Card doesn't support it

Definition at line 257 of file stm32_eval_sdio_sd.h.

Referenced by SD_WriteMultiBlocks().

#define SD_CMD_SET_BLOCKLEN ((uint8_t)16)

Definition at line 252 of file stm32_eval_sdio_sd.h.

Referenced by FindSCR(), SD_ReadMultiBlocks(), and SD_SendSDStatus().

#define SD_CMD_SET_DSR ((uint8_t)4)

Definition at line 240 of file stm32_eval_sdio_sd.h.

#define SD_CMD_SET_REL_ADDR ((uint8_t)3)

SDIO_SEND_REL_ADDR for SD Card

Definition at line 239 of file stm32_eval_sdio_sd.h.

Referenced by SD_InitializeCards().

#define SD_CMD_SET_WRITE_PROT ((uint8_t)28)

Definition at line 262 of file stm32_eval_sdio_sd.h.

#define SD_CMD_STOP_TRANSMISSION ((uint8_t)12)

Definition at line 248 of file stm32_eval_sdio_sd.h.

Referenced by SD_ProcessIRQSrc(), and SD_StopTransfer().

#define SD_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20)

SD Card doesn't support it

Definition at line 256 of file stm32_eval_sdio_sd.h.

#define SD_CMD_WRITE_MULT_BLOCK ((uint8_t)25)

Definition at line 259 of file stm32_eval_sdio_sd.h.

Referenced by SD_WriteMultiBlocks().

#define SD_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24)

Definition at line 258 of file stm32_eval_sdio_sd.h.

Referenced by SD_WriteBlock(), and SD_WriteMultiBlocks().

#define SD_DMA_MODE ((uint32_t)0x00000000)

Definition at line 313 of file stm32_eval_sdio_sd.h.

#define SD_NOT_PRESENT ((uint8_t)0x00)

Definition at line 320 of file stm32_eval_sdio_sd.h.

Referenced by SD_Detect().

#define SD_PRESENT ((uint8_t)0x01)

SD detection on its memory slot.

Definition at line 319 of file stm32_eval_sdio_sd.h.

Referenced by main(), SD_Detect(), and SD_GetState().

#define SDIO_HIGH_CAPACITY_MMC_CARD ((uint32_t)0x00000007)

Definition at line 332 of file stm32_eval_sdio_sd.h.

#define SDIO_HIGH_CAPACITY_SD_CARD ((uint32_t)0x00000002)

Definition at line 327 of file stm32_eval_sdio_sd.h.

Referenced by SD_EnableWideBusOperation(), SD_Erase(), SD_GetCardInfo(), SD_InitializeCards(), SD_PowerON(), SD_ReadBlock(), SD_ReadMultiBlocks(), SD_WriteBlock(), and SD_WriteMultiBlocks().

#define SDIO_HIGH_SPEED_MULTIMEDIA_CARD ((uint32_t)0x00000005)

Definition at line 330 of file stm32_eval_sdio_sd.h.

#define SDIO_MULTIMEDIA_CARD ((uint32_t)0x00000003)

Definition at line 328 of file stm32_eval_sdio_sd.h.

Referenced by SD_EnableWideBusOperation().

#define SDIO_SECURE_DIGITAL_IO_CARD ((uint32_t)0x00000004)

Definition at line 329 of file stm32_eval_sdio_sd.h.

Referenced by SD_InitializeCards().

#define SDIO_SECURE_DIGITAL_IO_COMBO_CARD ((uint32_t)0x00000006)

Definition at line 331 of file stm32_eval_sdio_sd.h.

Referenced by SD_InitializeCards().

#define SDIO_STD_CAPACITY_SD_CARD_V1_1 ((uint32_t)0x00000000)

Supported SD Memory Cards.

Definition at line 325 of file stm32_eval_sdio_sd.h.

Referenced by SD_EnableWideBusOperation(), SD_Erase(), SD_GetCardInfo(), and SD_InitializeCards().

#define SDIO_STD_CAPACITY_SD_CARD_V2_0 ((uint32_t)0x00000001)

Definition at line 326 of file stm32_eval_sdio_sd.h.

Referenced by SD_EnableWideBusOperation(), SD_Erase(), SD_GetCardInfo(), SD_InitializeCards(), and SD_PowerON().


STM32F10x Standard Peripherals Firmware Library: STM32_EVAL_SDIO_SD_Exported_Macros

STM32_EVAL_SDIO_SD_Exported_Macros

STM32_EVAL_SDIO_SD


STM32F10x Standard Peripherals Firmware Library: STM32_EVAL_SDIO_SD_Exported_Functions

Functions

STM32_EVAL_SDIO_SD_Exported_Functions

STM32_EVAL_SDIO_SD

Functions

void | SD_DeInit (void)
DeInitializes the SDIO interface.
uint8_t | SD_Detect (void)
Detect if SD card is correctly plugged in the memory slot.
SD_Error | SD_EnableWideBusOperation (uint32_t WideMode)
Enables wide bus opeartion for the requeseted card if supported by card.
SD_Error | SD_Erase (uint32_t startaddr, uint32_t endaddr)
Allows to erase memory area specified for the given card.
SD_Error | SD_GetCardInfo (SD_CardInfo *cardinfo)
Returns information about specific card.
SD_Error | SD_GetCardStatus (SD_CardStatus *cardstatus)
Enables wide bus opeartion for the requeseted card if supported by card.
SDCardState | SD_GetState (void)
Returns the current card's state.
SDTransferState | SD_GetStatus (void)
Gets the cuurent sd card data transfer status.
SDTransferState | SD_GetTransferState (void)
Gets the cuurent data transfer state.
SD_Error | SD_Init (void)
Initializes the SD Card and put it into StandBy State (Ready for data transfer).
SD_Error | SD_InitializeCards (void)
Intialises all cards or single card as the case may be Card(s) come into standby state.
SD_Error | SD_PowerOFF (void)
Turns the SDIO output signals off.
SD_Error | SD_PowerON (void)
Enquires cards about their operating voltage and configures clock controls.
SD_Error | SD_ProcessIRQSrc (void)
Allows to process all the interrupts that are high.
SD_Error | SD_ReadBlock (uint8_t *readbuff, uint32_t ReadAddr, uint16_t BlockSize)
Allows to read one block from a specified address in a card.
SD_Error | SD_ReadMultiBlocks (uint8_t *readbuff, uint32_t ReadAddr, uint16_t BlockSize, uint32_t NumberOfBlocks)
Allows to read blocks from a specified address in a card.
SD_Error | SD_SelectDeselect (uint32_t addr)
Selects od Deselects the corresponding card.
SD_Error | SD_SendSDStatus (uint32_t *psdstatus)
Returns the current SD card's status.
SD_Error | SD_SendStatus (uint32_t *pcardstatus)
Returns the current card's status.
SD_Error | SD_StopTransfer (void)
Aborts an ongoing data transfer.
SD_Error | SD_WaitReadOperation (void)
This function waits until the SDIO DMA data transfer is finished.
SD_Error | SD_WaitWriteOperation (void)
This function waits until the SDIO DMA data transfer is finished.
SD_Error | SD_WriteBlock (uint8_t *writebuff, uint32_t WriteAddr, uint16_t BlockSize)
Allows to write one block starting from a specified address in a card.
SD_Error | SD_WriteMultiBlocks (uint8_t *writebuff, uint32_t WriteAddr, uint16_t BlockSize, uint32_t NumberOfBlocks)
Allows to write blocks starting from a specified address in a card.

Function Documentation

void SD_DeInit ( void )

DeInitializes the SDIO interface.

Parameters:
None
Return values:
None DeInitializes the SDIO interface.
Parameters:
None
Return values:
None

Definition at line 356 of file stm32_eval_sdio_sd.c.

uint8_t SD_Detect ( void )

Detect if SD card is correctly plugged in the memory slot.

Parameters:
None
Return values:
Return if SD is detected or not

< Check GPIO to detect SD

< Check GPIO to detect SD

Definition at line 482 of file stm32_eval_sdio_sd.c.

SD_Error SD_EnableWideBusOperation ( uint32_t WideMode )

Enables wide bus opeartion for the requeseted card if supported by card.

Parameters:
WideMode,: Specifies the SD card wide bus mode. This parameter can be one of the following values:

  • SDIO_BusWide_8b: 8-bit data transfer (Only for MMC)
  • SDIO_BusWide_4b: 4-bit data transfer
  • SDIO_BusWide_1b: 1-bit data transfer
Return values:
SD_Error,: SD Card Error code.

< MMC Card doesn't support this feature

< Configure the SDIO peripheral

< Configure the SDIO peripheral

Definition at line 1046 of file stm32_eval_sdio_sd.c.

References CardType, DISABLE, ENABLE, SD_OK, SD_UNSUPPORTED_FEATURE, SDEnWideBus(), SDIO_InitTypeDef::SDIO_BusWide, SDIO_BusWide_1b, SDIO_BusWide_4b, SDIO_BusWide_8b, SDIO_InitTypeDef::SDIO_ClockBypass, SDIO_ClockBypass_Disable, SDIO_InitTypeDef::SDIO_ClockDiv, SDIO_InitTypeDef::SDIO_ClockEdge, SDIO_ClockEdge_Rising, SDIO_InitTypeDef::SDIO_ClockPowerSave, SDIO_ClockPowerSave_Disable, SDIO_InitTypeDef::SDIO_HardwareFlowControl, SDIO_HardwareFlowControl_Disable, SDIO_HIGH_CAPACITY_SD_CARD, SDIO_Init(), SDIO_MULTIMEDIA_CARD, SDIO_STD_CAPACITY_SD_CARD_V1_1, SDIO_STD_CAPACITY_SD_CARD_V2_0, and SDIO_TRANSFER_CLK_DIV.

Referenced by SD_Init().

SD_Error SD_Erase | ( | uint32_t | startaddr,
 |  | uint32_t | endaddr
 | ) |  |

Allows to erase memory area specified for the given card.

Parameters:
startaddr,: the start address.
endaddr,: the end address.
Return values:
SD_Error,: SD Card Error code.

< Check if the card coomnd class supports erase command

< Send CMD32 SD_ERASE_GRP_START with argument as addr

Definition at line 1613 of file stm32_eval_sdio_sd.c.

References CardType, CmdResp1Error(), CSD_Tab, delay(), IsCardProgramming(), SD_CARD_LOCKED, SD_CARD_PROGRAMMING, SD_CARD_RECEIVING, SD_CCCC_ERASE, SD_CMD_ERASE, SD_CMD_SD_ERASE_GRP_END, SD_CMD_SD_ERASE_GRP_START, SD_LOCK_UNLOCK_FAILED, SD_OK, SD_REQUEST_NOT_APPLICABLE, SDIO, SDIO_CmdInitTypeDef::SDIO_Argument, SDIO_CmdInitTypeDef::SDIO_CmdIndex, SDIO_CmdInitTypeDef::SDIO_CPSM, SDIO_CPSM_Enable, SDIO_GetResponse(), SDIO_HIGH_CAPACITY_SD_CARD, SDIO_RESP1, SDIO_CmdInitTypeDef::SDIO_Response, SDIO_Response_Short, SDIO_SendCommand(), SDIO_STD_CAPACITY_SD_CARD_V1_1, SDIO_STD_CAPACITY_SD_CARD_V2_0, SDIO_CmdInitTypeDef::SDIO_Wait, and SDIO_Wait_No.

Referenced by SD_EraseTest().

SD_Error SD_GetCardInfo ( SD_CardInfo * cardinfo )

Returns information about specific card.

Parameters:
cardinfo,: pointer to a SD_CardInfo structure that contains all SD card information.
Return values:
SD_Error,: SD Card Error code.
Parameters:
cardinfo,: pointer to a SD_CardInfo structure that contains all SD card information.
Return values:
The SD Response:

  • SD_RESPONSE_FAILURE: Sequence failed
  • SD_RESPONSE_NO_ERROR: Sequence succeed

< Byte 0

< Byte 1

< Byte 2

< Byte 3

< Byte 4

< Byte 5

< Byte 6

< Reserved

< Byte 7

< Byte 8

< Byte 9

< Byte 10

< Byte 7

< Byte 8

< Byte 9

< Byte 10

< Byte 11

< Byte 12

< Byte 13

< Byte 14

< Byte 15

< Byte 0

< Byte 1

< Byte 2

< Byte 3

< Byte 4

< Byte 5

< Byte 6

< Byte 7

< Byte 8

< Byte 9

< Byte 10

< Byte 11

< Byte 12

< Byte 13

< Byte 14

< Byte 15

< Returns the reponse

Definition at line 749 of file stm32_eval_sdio_sd.c.

SD_Error SD_GetCardStatus ( SD_CardStatus * cardstatus )

Enables wide bus opeartion for the requeseted card if supported by card.

Parameters:
WideMode,: Specifies the SD card wide bus mode. This parameter can be one of the following values:

  • SDIO_BusWide_8b: 8-bit data transfer (Only for MMC)
  • SDIO_BusWide_4b: 4-bit data transfer
  • SDIO_BusWide_1b: 1-bit data transfer
Return values:
SD_Error,: SD Card Error code.

< Byte 0

< Byte 2

< Byte 3

< Byte 4

< Byte 5

< Byte 6

< Byte 7

< Byte 8

< Byte 9

< Byte 10

< Byte 11

< Byte 12

< Byte 13

< Byte 13

Definition at line 961 of file stm32_eval_sdio_sd.c.

References SD_CardStatus::AU_SIZE, SD_CardStatus::DAT_BUS_WIDTH, SD_CardStatus::ERASE_OFFSET, SD_CardStatus::ERASE_SIZE, SD_CardStatus::ERASE_TIMEOUT, SD_CardStatus::PERFORMANCE_MOVE, SD_CardStatus::SD_CARD_TYPE, SD_OK, SD_SendSDStatus(), SDSTATUS_Tab, SD_CardStatus::SECURED_MODE, SD_CardStatus::SIZE_OF_PROTECTED_AREA, and SD_CardStatus::SPEED_CLASS.

SDCardState SD_GetState ( void )

Returns the current card's state.

Parameters:
None
Return values:
SDCardState,: SD Card Error or SD Card Current State.

Definition at line 456 of file stm32_eval_sdio_sd.c.

References SD_CARD_ERROR, SD_Detect(), SD_OK, SD_PRESENT, and SD_SendStatus().

Referenced by SD_GetStatus().

SDTransferState SD_GetStatus ( void )

Gets the cuurent sd card data transfer status.

Parameters:
None
Return values:
SDTransferState,: Data Transfer state. This value can be:

  • SD_TRANSFER_OK: No data transfer is acting
  • SD_TRANSFER_BUSY: Data transfer is acting

Gets the cuurent sd card data transfer status.

Parameters:
None
Return values:
The SD status.

< SD chip select low

< Send CMD13 (SD_SEND_STATUS) to get SD status

< SD chip select high

< Send dummy byte 0xFF

Definition at line 431 of file stm32_eval_sdio_sd.c.

SDTransferState SD_GetTransferState ( void )

Gets the cuurent data transfer state.

Parameters:
None
Return values:
SDTransferState,: Data Transfer state. This value can be:

  • SD_TRANSFER_OK: No data transfer is acting
  • SD_TRANSFER_BUSY: Data transfer is acting

Definition at line 1578 of file stm32_eval_sdio_sd.c.

References SD_TRANSFER_BUSY, SD_TRANSFER_OK, SDIO, SDIO_FLAG_RXACT, and SDIO_FLAG_TXACT.

SD_Error SD_Init ( void )

Initializes the SD Card and put it into StandBy State (Ready for data transfer).

Parameters:
None
Return values:
SD_Error,: SD Card Error code.

Initializes the SD Card and put it into StandBy State (Ready for data transfer).

Parameters:
None
Return values:
The SD Response:

  • SD_RESPONSE_FAILURE: Sequence failed
  • SD_RESPONSE_NO_ERROR: Sequence succeed

< CMD Response TimeOut (wait for CMDSENT flag)

< CMD Response TimeOut (wait for CMDSENT flag)

< SDIOCLK = HCLK, SDIO_CK = HCLK/(2 + SDIO_TRANSFER_CLK_DIV)

< on STM32F2xx devices, SDIOCLK is fixed to 48MHz

< Initialize SD_SPI

< SD chip select high

< Send dummy byte 0xFF, 10 times with CS high

< Rise CS and MOSI for 80 clocks cycles

< Send dummy byte 0xFF

< SD initialized and set to SPI mode properly

Definition at line 367 of file stm32_eval_sdio_sd.c.

SD_Error SD_InitializeCards ( void )

Intialises all cards or single card as the case may be Card(s) come into standby state.

Parameters:
None
Return values:
SD_Error,: SD Card Error code.

< Send CMD2 ALL_SEND_CID

< Send CMD3 SET_REL_ADDR with argument 0

< SD Card publishes its RCA.

< Send CMD9 SEND_CSD with argument as card's RCA

< All cards get intialized

Definition at line 660 of file stm32_eval_sdio_sd.c.

References CardType, CID_Tab, CmdResp2Error(), CmdResp6Error(), CSD_Tab, RCA, SD_CMD_ALL_SEND_CID, SD_CMD_SEND_CSD, SD_CMD_SET_REL_ADDR, SD_OK, SD_REQUEST_NOT_APPLICABLE, SDIO_CmdInitTypeDef::SDIO_Argument, SDIO_CmdInitTypeDef::SDIO_CmdIndex, SDIO_CmdInitTypeDef::SDIO_CPSM, SDIO_CPSM_Enable, SDIO_GetPowerState(), SDIO_GetResponse(), SDIO_HIGH_CAPACITY_SD_CARD, SDIO_PowerState_OFF, SDIO_RESP1, SDIO_RESP2, SDIO_RESP3, SDIO_RESP4, SDIO_CmdInitTypeDef::SDIO_Response, SDIO_Response_Long, SDIO_Response_Short, SDIO_SECURE_DIGITAL_IO_CARD, SDIO_SECURE_DIGITAL_IO_COMBO_CARD, SDIO_SendCommand(), SDIO_STD_CAPACITY_SD_CARD_V1_1, SDIO_STD_CAPACITY_SD_CARD_V2_0, SDIO_CmdInitTypeDef::SDIO_Wait, and SDIO_Wait_No.

Referenced by SD_Init().

SD_Error SD_PowerOFF ( void )

Turns the SDIO output signals off.

Parameters:
None
Return values:
SD_Error,: SD Card Error code.

< Set Power State to OFF

Definition at line 644 of file stm32_eval_sdio_sd.c.

References SD_OK, SDIO_PowerState_OFF, and SDIO_SetPowerState().

SD_Error SD_PowerON ( void )

Enquires cards about their operating voltage and configures clock controls.

Parameters:
None
Return values:
SD_Error,: SD Card Error code.

< Power ON Sequence -----------------------------------------------------

< Configure the SDIO peripheral

< SDIOCLK = HCLK, SDIO_CK = HCLK/(2 + SDIO_INIT_CLK_DIV)

< on STM32F2xx devices, SDIOCLK is fixed to 48MHz

< SDIO_CK for initialization should not exceed 400 KHz

< Set Power State to ON

< Enable SDIO Clock

< CMD0: GO_IDLE_STATE ---------------------------------------------------

< No CMD response required

< CMD Response TimeOut (wait for CMDSENT flag)

< Send CMD8 to verify SD card interface operating condition

< Argument: - [31:12]: Reserved (shall be set to '0')

  • [11:8]: Supply Voltage (VHS) 0x1 (Range: 2.7-3.6 V)
  • [7:0]: Check Pattern (recommended 0xAA)

< CMD Response: R7

< SD Card 2.0

< CMD55

< If errorstatus is Command TimeOut, it is a MMC card

< If errorstatus is SD_OK it is a SD card: SD card 2.0 (voltage range mismatch) or SD card 1.x

< SD CARD

< Send ACMD41 SD_APP_OP_COND with Argument 0x80100000

< SEND CMD55 APP_CMD with RCA as 0

Definition at line 500 of file stm32_eval_sdio_sd.c.

References CardType, CmdError(), CmdResp1Error(), CmdResp3Error(), CmdResp7Error(), ENABLE, SD_CHECK_PATTERN, SD_CMD_APP_CMD, SD_CMD_GO_IDLE_STATE, SD_CMD_SD_APP_OP_COND, SD_HIGH_CAPACITY, SD_INVALID_VOLTRANGE, SD_MAX_VOLT_TRIAL, SD_OK, SD_STD_CAPACITY, SD_VOLTAGE_WINDOW_SD, SDIO_CmdInitTypeDef::SDIO_Argument, SDIO_InitTypeDef::SDIO_BusWide, SDIO_BusWide_1b, SDIO_InitTypeDef::SDIO_ClockBypass, SDIO_ClockBypass_Disable, SDIO_ClockCmd(), SDIO_InitTypeDef::SDIO_ClockDiv, SDIO_InitTypeDef::SDIO_ClockEdge, SDIO_ClockEdge_Rising, SDIO_InitTypeDef::SDIO_ClockPowerSave, SDIO_ClockPowerSave_Disable, SDIO_CmdInitTypeDef::SDIO_CmdIndex, SDIO_CmdInitTypeDef::SDIO_CPSM, SDIO_CPSM_Enable, SDIO_GetResponse(), SDIO_InitTypeDef::SDIO_HardwareFlowControl, SDIO_HardwareFlowControl_Disable, SDIO_HIGH_CAPACITY_SD_CARD, SDIO_Init(), SDIO_INIT_CLK_DIV, SDIO_PowerState_ON, SDIO_RESP1, SDIO_CmdInitTypeDef::SDIO_Response, SDIO_Response_No, SDIO_Response_Short, SDIO_SEND_IF_COND, SDIO_SendCommand(), SDIO_SetPowerState(), SDIO_STD_CAPACITY_SD_CARD_V2_0, SDIO_CmdInitTypeDef::SDIO_Wait, and SDIO_Wait_No.

Referenced by SD_Init().

SD_Error SD_ProcessIRQSrc ( void )

Allows to process all the interrupts that are high.

Parameters:
None
Return values:
SD_Error,: SD Card Error code.

Definition at line 1848 of file stm32_eval_sdio_sd.c.

References CmdResp1Error(), DISABLE, SD_CMD_STOP_TRANSMISSION, SD_OK, SDIO, SDIO_ClearITPendingBit(), SDIO_IT_DATAEND, SDIO_ITConfig(), StopCondition, TransferEnd, and TransferError.

Referenced by SDIO_IRQHandler().

SD_Error SD_ReadBlock | ( | uint8_t * | pBuffer,
 |  | uint32_t | ReadAddr,
 |  | uint16_t | BlockSize
 | ) |  |

Allows to read one block from a specified address in a card.

The Data transfer can be managed by DMA mode or Polling mode.

Note:
This operation should be followed by two functions to check if the DMA Controller and SD Card status.
  • SD_ReadWaitOperation(): this function insure that the DMA controller has finished all data transfer.
  • SD_GetStatus(): to check that the SD Card has finished the data transfer and it is ready for data.
Parameters:
readbuff,: pointer to the buffer that will contain the received data
ReadAddr,: Address from where data are to be read.
BlockSize,: the SD card Data block size. The Block size should be 512.
Return values:
SD_Error,: SD Card Error code.

Allows to read one block from a specified address in a card.

Parameters:
pBuffer,: pointer to the buffer that receives the data read from the SD.
ReadAddr,: SD's internal address to read from.
BlockSize,: the SD card Data block size.
Return values:
The SD Response:

  • SD_RESPONSE_FAILURE: Sequence failed
  • SD_RESPONSE_NO_ERROR: Sequence succeed

< Send CMD17 READ_SINGLE_BLOCK

< SD chip select low

< Send CMD17 (SD_CMD_READ_SINGLE_BLOCK) to read one block

< Check if the SD acknowledged the read block command: R1 response (0x00: no errors)

< Now look for the data token to signify the start of the data

< Read the SD block data : read NumByteToRead data

< Save the received data

< Point to the next location where the byte read will be saved

< Set response value to success

< Send dummy byte: 8 Clock pulses of delay

< Returns the reponse

Definition at line 1136 of file stm32_eval_sdio_sd.c.

SD_Error SD_ReadMultiBlocks | ( | uint8_t * | pBuffer,
 |  | uint32_t | ReadAddr,
 |  | uint16_t | BlockSize,
 |  | uint32_t | NumberOfBlocks
 | ) |  |

Allows to read blocks from a specified address in a card.

The Data transfer can be managed by DMA mode or Polling mode.

Note:
This operation should be followed by two functions to check if the DMA Controller and SD Card status.
  • SD_ReadWaitOperation(): this function insure that the DMA controller has finished all data transfer.
  • SD_GetStatus(): to check that the SD Card has finished the data transfer and it is ready for data.
Parameters:
readbuff,: pointer to the buffer that will contain the received data.
ReadAddr,: Address from where data are to be read.
BlockSize,: the SD card Data block size. The Block size should be 512.
NumberOfBlocks,: number of blocks to be read.
Return values:
SD_Error,: SD Card Error code.

Allows to read blocks from a specified address in a card.

Parameters:
pBuffer,: pointer to the buffer that receives the data read from the SD.
ReadAddr,: SD's internal address to read from.
BlockSize,: the SD card Data block size.
NumberOfBlocks,: number of blocks to be read.
Return values:
The SD Response:

  • SD_RESPONSE_FAILURE: Sequence failed
  • SD_RESPONSE_NO_ERROR: Sequence succeed

< Send CMD18 READ_MULT_BLOCK with argument data address

< SD chip select low

< Data transfer

< Send CMD17 (SD_CMD_READ_SINGLE_BLOCK) to read one block

< Check if the SD acknowledged the read block command: R1 response (0x00: no errors)

< Read the SD block data : read NumByteToRead data

< Read the pointed data

< Point to the next location where the byte read will be saved

< get CRC bytes (not really needed by us, but required by SD)

< Set response value to success

< Set response value to failure

< Send dummy byte: 8 Clock pulses of delay

< Returns the reponse

Definition at line 1251 of file stm32_eval_sdio_sd.c.

SD_Error SD_SelectDeselect ( uint32_t addr )

Selects od Deselects the corresponding card.

Parameters:
addr,: Address of the Card to be selected.
Return values:
SD_Error,: SD Card Error code.

< Send CMD7 SDIO_SEL_DESEL_CARD

Definition at line 1105 of file stm32_eval_sdio_sd.c.

References CmdResp1Error(), SD_CMD_SEL_DESEL_CARD, SD_OK, SDIO_CmdInitTypeDef::SDIO_Argument, SDIO_CmdInitTypeDef::SDIO_CmdIndex, SDIO_CmdInitTypeDef::SDIO_CPSM, SDIO_CPSM_Enable, SDIO_CmdInitTypeDef::SDIO_Response, SDIO_Response_Short, SDIO_SendCommand(), SDIO_CmdInitTypeDef::SDIO_Wait, and SDIO_Wait_No.

Referenced by SD_Init().

SD_Error SD_SendSDStatus ( uint32_t * psdstatus )

Returns the current SD card's status.

Parameters:
psdstatus,: pointer to the buffer that will contain the SD card status (SD Status register).
Return values:
SD_Error,: SD Card Error code.

< Send ACMD13 SD_APP_STAUS with argument as card's RCA.

Definition at line 1732 of file stm32_eval_sdio_sd.c.

References CmdResp1Error(), RCA, RESET, SD_CARD_LOCKED, SD_CMD_APP_CMD, SD_CMD_SD_APP_STAUS, SD_CMD_SET_BLOCKLEN, SD_DATA_CRC_FAIL, SD_DATA_TIMEOUT, SD_DATATIMEOUT, SD_LOCK_UNLOCK_FAILED, SD_OK, SD_RX_OVERRUN, SD_START_BIT_ERR, SDIO, SDIO_CmdInitTypeDef::SDIO_Argument, SDIO_ClearFlag(), SDIO_CmdInitTypeDef::SDIO_CmdIndex, SDIO_CmdInitTypeDef::SDIO_CPSM, SDIO_CPSM_Enable, SDIO_DataInitTypeDef::SDIO_DataBlockSize, SDIO_DataBlockSize_64b, SDIO_DataConfig(), SDIO_DataInitTypeDef::SDIO_DataLength, SDIO_DataInitTypeDef::SDIO_DataTimeOut, SDIO_DataInitTypeDef::SDIO_DPSM, SDIO_DPSM_Enable, SDIO_FLAG_DBCKEND, SDIO_FLAG_DCRCFAIL, SDIO_FLAG_DTIMEOUT, SDIO_FLAG_RXDAVL, SDIO_FLAG_RXFIFOHF, SDIO_FLAG_RXOVERR, SDIO_FLAG_STBITERR, SDIO_GetFlagStatus(), SDIO_GetResponse(), SDIO_ReadData(), SDIO_RESP1, SDIO_CmdInitTypeDef::SDIO_Response, SDIO_Response_Short, SDIO_SendCommand(), SDIO_STATIC_FLAGS, SDIO_DataInitTypeDef::SDIO_TransferDir, SDIO_TransferDir_ToSDIO, SDIO_DataInitTypeDef::SDIO_TransferMode, SDIO_TransferMode_Block, SDIO_CmdInitTypeDef::SDIO_Wait, and SDIO_Wait_No.

Referenced by SD_GetCardStatus().

SD_Error SD_SendStatus ( uint32_t * pcardstatus )

Returns the current card's status.

Parameters:
pcardstatus,: pointer to the buffer that will contain the SD card status (Card Status register).
Return values:
SD_Error,: SD Card Error code.

Definition at line 1708 of file stm32_eval_sdio_sd.c.

References CmdResp1Error(), RCA, SD_CMD_SEND_STATUS, SD_OK, and SDIO.

Referenced by SD_GetState().

SD_Error SD_StopTransfer ( void )

Aborts an ongoing data transfer.

Parameters:
None
Return values:
SD_Error,: SD Card Error code.

< Send CMD12 STOP_TRANSMISSION

Definition at line 1595 of file stm32_eval_sdio_sd.c.

References CmdResp1Error(), SD_CMD_STOP_TRANSMISSION, SD_OK, and SDIO.

SD_Error SD_WaitReadOperation ( void )

This function waits until the SDIO DMA data transfer is finished.

This function should be called after SDIO_ReadMultiBlocks() function to insure that all data sent by the card are already transferred by the DMA controller.

Parameters:
None.
Return values:
SD_Error,: SD Card Error code.

Definition at line 1319 of file stm32_eval_sdio_sd.c.

References RESET, SD_DMAEndOfTransferStatus(), SD_OK, TransferEnd, and TransferError.

Referenced by SD_EraseTest(), SD_MultiBlockTest(), and SD_SingleBlockTest().

SD_Error SD_WaitWriteOperation ( void )

This function waits until the SDIO DMA data transfer is finished.

This function should be called after SDIO_WriteBlock() and SDIO_WriteMultiBlocks() function to insure that all data sent by the card are already transferred by the DMA controller.

Parameters:
None.
Return values:
SD_Error,: SD Card Error code.

Definition at line 1552 of file stm32_eval_sdio_sd.c.

References RESET, SD_DMAEndOfTransferStatus(), SD_OK, SDIO_ClearFlag(), SDIO_STATIC_FLAGS, TransferEnd, and TransferError.

Referenced by SD_MultiBlockTest(), and SD_SingleBlockTest().

SD_Error SD_WriteBlock | ( | uint8_t * | pBuffer,
 |  | uint32_t | WriteAddr,
 |  | uint16_t | BlockSize
 | ) |  |

Allows to write one block starting from a specified address in a card.

The Data transfer can be managed by DMA mode or Polling mode.

Note:
This operation should be followed by two functions to check if the DMA Controller and SD Card status.
  • SD_ReadWaitOperation(): this function insure that the DMA controller has finished all data transfer.
  • SD_GetStatus(): to check that the SD Card has finished the data transfer and it is ready for data.
Parameters:
writebuff,: pointer to the buffer that contain the data to be transferred.
WriteAddr,: Address from where data are to be read.
BlockSize,: the SD card Data block size. The Block size should be 512.
Return values:
SD_Error,: SD Card Error code.

Allows to write one block starting from a specified address in a card.

Parameters:
pBuffer,: pointer to the buffer containing the data to be written on the SD.
WriteAddr,: address to write on.
BlockSize,: the SD card Data block size.
Return values:
The SD Response:

  • SD_RESPONSE_FAILURE: Sequence failed
  • SD_RESPONSE_NO_ERROR: Sequence succeed

< In case of single data block transfer no need of stop command at all

< SD chip select low

< Send CMD24 (SD_CMD_WRITE_SINGLE_BLOCK) to write multiple block

< Check if the SD acknowledged the write block command: R1 response (0x00: no errors)

< Send a dummy byte

< Send the data token to signify the start of the data

< Write the block data to SD : write count data by block

< Send the pointed byte

< Point to the next location where the byte read will be saved

< Read data response

< Send dummy byte: 8 Clock pulses of delay

< Returns the reponse

Definition at line 1348 of file stm32_eval_sdio_sd.c.

SD_Error SD_WriteMultiBlocks | ( | uint8_t * | pBuffer,
 |  | uint32_t | WriteAddr,
 |  | uint16_t | BlockSize,
 |  | uint32_t | NumberOfBlocks
 | ) |  |

Allows to write blocks starting from a specified address in a card.

The Data transfer can be managed by DMA mode only.

Note:
This operation should be followed by two functions to check if the DMA Controller and SD Card status.
  • SD_ReadWaitOperation(): this function insure that the DMA controller has finished all data transfer.
  • SD_GetStatus(): to check that the SD Card has finished the data transfer and it is ready for data.
Parameters:
WriteAddr,: Address from where data are to be read.
writebuff,: pointer to the buffer that contain the data to be transferred.
BlockSize,: the SD card Data block size. The Block size should be 512.
NumberOfBlocks,: number of blocks to be written.
Return values:
SD_Error,: SD Card Error code.

Allows to write blocks starting from a specified address in a card.

Parameters:
pBuffer,: pointer to the buffer containing the data to be written on the SD.
WriteAddr,: address to write on.
BlockSize,: the SD card Data block size.
NumberOfBlocks,: number of blocks to be written.
Return values:
The SD Response:

  • SD_RESPONSE_FAILURE: Sequence failed
  • SD_RESPONSE_NO_ERROR: Sequence succeed

< SD chip select low

< Data transfer

< Send CMD24 (SD_CMD_WRITE_SINGLE_BLOCK) to write blocks

< Check if the SD acknowledged the write block command: R1 response (0x00: no errors)

< Send the data token to signify the start of the data

< Write the block data to SD : write count data by block

< Send the pointed byte

< Point to the next location where the byte read will be saved

< Put CRC bytes (not really needed by us, but required by SD)

< Read data response

< Set response value to success

< Set response value to failure

< Send dummy byte: 8 Clock pulses of delay

< Returns the reponse

Definition at line 1466 of file stm32_eval_sdio_sd.c.


STM32F10x Standard Peripherals Firmware Library: STM32_EVAL_SPI_FLASH_Private_Types

STM32_EVAL_SPI_FLASH_Private_Types

STM32_EVAL_SPI_FLASH


STM32F10x Standard Peripherals Firmware Library: STM32_EVAL_SPI_FLASH_Private_Defines

STM32_EVAL_SPI_FLASH_Private_Defines

STM32_EVAL_SPI_FLASH


STM32F10x Standard Peripherals Firmware Library: STM32_EVAL_SPI_FLASH_Private_Macros

STM32_EVAL_SPI_FLASH_Private_Macros

STM32_EVAL_SPI_FLASH


STM32F10x Standard Peripherals Firmware Library: STM32_EVAL_SPI_FLASH_Private_Variables

STM32_EVAL_SPI_FLASH_Private_Variables

STM32_EVAL_SPI_FLASH


STM32F10x Standard Peripherals Firmware Library: STM32_EVAL_SPI_FLASH_Private_Function_Prototypes

STM32_EVAL_SPI_FLASH_Private_Function_Prototypes

STM32_EVAL_SPI_FLASH


STM32F10x Standard Peripherals Firmware Library: STM32_EVAL_SPI_FLASH_Private_Functions

Functions

STM32_EVAL_SPI_FLASH_Private_Functions

STM32_EVAL_SPI_FLASH

Functions

void | sFLASH_DeInit (void)
DeInitializes the peripherals used by the SPI FLASH driver.
void | sFLASH_EraseBulk (void)
Erases the entire FLASH.
void | sFLASH_EraseSector (uint32_t SectorAddr)
Erases the specified FLASH sector.
void | sFLASH_Init (void)
Initializes the peripherals used by the SPI FLASH driver.
void | sFLASH_ReadBuffer (uint8_t *pBuffer, uint32_t ReadAddr, uint16_t NumByteToRead)
Reads a block of data from the FLASH.
uint8_t | sFLASH_ReadByte (void)
Reads a byte from the SPI Flash.
uint32_t | sFLASH_ReadID (void)
Reads FLASH identification.
uint8_t | sFLASH_SendByte (uint8_t byte)
Sends a byte through the SPI interface and return the byte received from the SPI bus.
uint16_t | sFLASH_SendHalfWord (uint16_t HalfWord)
Sends a Half Word through the SPI interface and return the Half Word received from the SPI bus.
void | sFLASH_StartReadSequence (uint32_t ReadAddr)
Initiates a read data byte (READ) sequence from the Flash.
void | sFLASH_WaitForWriteEnd (void)
Polls the status of the Write In Progress (WIP) flag in the FLASH's status register and loop until write opertaion has completed.
void | sFLASH_WriteBuffer (uint8_t *pBuffer, uint32_t WriteAddr, uint16_t NumByteToWrite)
Writes block of data to the FLASH.
void | sFLASH_WriteEnable (void)
Enables the write access to the FLASH.
void | sFLASH_WritePage (uint8_t *pBuffer, uint32_t WriteAddr, uint16_t NumByteToWrite)
Writes more than one byte to the FLASH with a single WRITE cycle (Page WRITE sequence).

Function Documentation

void sFLASH_DeInit ( void )

DeInitializes the peripherals used by the SPI FLASH driver.

High layer functions.

Parameters:
None
Return values:
None

Definition at line 115 of file stm32_eval_spi_flash.c.

References sFLASH_LowLevel_DeInit().

void sFLASH_EraseBulk ( void )

Erases the entire FLASH.

Parameters:
None
Return values:
None

< Send write enable instruction

< Bulk Erase

< Select the FLASH: Chip Select low

< Send Bulk Erase instruction

< Deselect the FLASH: Chip Select high

< Wait the end of Flash writing

Definition at line 188 of file stm32_eval_spi_flash.c.

References sFLASH_CMD_BE, sFLASH_CS_HIGH, sFLASH_CS_LOW, sFLASH_SendByte(), sFLASH_WaitForWriteEnd(), and sFLASH_WriteEnable().

void sFLASH_EraseSector ( uint32_t SectorAddr )

Erases the specified FLASH sector.

Parameters:
SectorAddr,: address of the sector to erase.
Return values:
None

< Send write enable instruction

< Sector Erase

< Select the FLASH: Chip Select low

< Send Sector Erase instruction

< Send SectorAddr high nibble address byte

< Send SectorAddr medium nibble address byte

< Send SectorAddr low nibble address byte

< Deselect the FLASH: Chip Select high

< Wait the end of Flash writing

Definition at line 160 of file stm32_eval_spi_flash.c.

References sFLASH_CMD_SE, sFLASH_CS_HIGH, sFLASH_CS_LOW, sFLASH_SendByte(), sFLASH_WaitForWriteEnd(), and sFLASH_WriteEnable().

Referenced by main().

void sFLASH_Init ( void )

Initializes the peripherals used by the SPI FLASH driver.

Parameters:
None
Return values:
None

< Deselect the FLASH: Chip Select high

< SPI configuration

< Enable the sFLASH_SPI

Definition at line 125 of file stm32_eval_spi_flash.c.

References ENABLE, sFLASH_CS_HIGH, sFLASH_LowLevel_Init(), sFLASH_SPI, SPI_InitTypeDef::SPI_BaudRatePrescaler, SPI_BaudRatePrescaler_2, SPI_BaudRatePrescaler_4, SPI_Cmd(), SPI_InitTypeDef::SPI_CPHA, SPI_CPHA_2Edge, SPI_InitTypeDef::SPI_CPOL, SPI_CPOL_High, SPI_InitTypeDef::SPI_CRCPolynomial, SPI_InitTypeDef::SPI_DataSize, SPI_DataSize_8b, SPI_InitTypeDef::SPI_Direction, SPI_Direction_2Lines_FullDuplex, SPI_InitTypeDef::SPI_FirstBit, SPI_FirstBit_MSB, SPI_Init(), SPI_InitStructure, SPI_InitTypeDef::SPI_Mode, SPI_Mode_Master, SPI_InitTypeDef::SPI_NSS, and SPI_NSS_Soft.

Referenced by main().

void sFLASH_ReadBuffer | ( | uint8_t * | pBuffer,
 |  | uint32_t | ReadAddr,
 |  | uint16_t | NumByteToRead
 | ) |  |

Reads a block of data from the FLASH.

Parameters:
pBuffer,: pointer to the buffer that receives the data read from the FLASH.
ReadAddr,: FLASH's internal address to read from.
NumByteToRead,: number of bytes to read from the FLASH.
Return values:
None

< Select the FLASH: Chip Select low

< Send "Read from Memory " instruction

< Send ReadAddr high nibble address byte to read from

< Send ReadAddr medium nibble address byte to read from

< Send ReadAddr low nibble address byte to read from

< while there is data to be read

< Read a byte from the FLASH

< Point to the next location where the byte read will be saved

Definition at line 335 of file stm32_eval_spi_flash.c.

References sFLASH_CMD_READ, sFLASH_CS_HIGH, sFLASH_CS_LOW, sFLASH_DUMMY_BYTE, and sFLASH_SendByte().

Referenced by main().

uint8_t sFLASH_ReadByte ( void )

Reads a byte from the SPI Flash.

Low layer functions.

Note:
This function must be used only if the Start_Read_Sequence function has been previously called.
Parameters:
None
Return values:
Byte Read from the SPI Flash.

Definition at line 427 of file stm32_eval_spi_flash.c.

References sFLASH_DUMMY_BYTE, and sFLASH_SendByte().

uint32_t sFLASH_ReadID ( void )

Reads FLASH identification.

Parameters:
None
Return values:
FLASH identification

< Select the FLASH: Chip Select low

< Send "RDID " instruction

< Read a byte from the FLASH

< Read a byte from the FLASH

< Read a byte from the FLASH

< Deselect the FLASH: Chip Select high

Definition at line 367 of file stm32_eval_spi_flash.c.

References sFLASH_CS_HIGH, sFLASH_CS_LOW, sFLASH_DUMMY_BYTE, and sFLASH_SendByte().

Referenced by main().

uint8_t sFLASH_SendByte ( uint8_t byte )

Sends a byte through the SPI interface and return the byte received from the SPI bus.

Parameters:
byte,: byte to send.
Return values:
The value of the received byte.

< Loop while DR register in not emplty

< Send byte through the SPI1 peripheral

< Wait to receive a byte

< Return the byte read from the SPI bus

Definition at line 438 of file stm32_eval_spi_flash.c.

References RESET, sFLASH_SPI, SPI_I2S_FLAG_RXNE, SPI_I2S_FLAG_TXE, SPI_I2S_GetFlagStatus(), SPI_I2S_ReceiveData(), and SPI_I2S_SendData().

Referenced by sFLASH_EraseBulk(), sFLASH_EraseSector(), sFLASH_ReadBuffer(), sFLASH_ReadByte(), sFLASH_ReadID(), sFLASH_StartReadSequence(), sFLASH_WaitForWriteEnd(), sFLASH_WriteEnable(), and sFLASH_WritePage().

uint16_t sFLASH_SendHalfWord ( uint16_t HalfWord )

Sends a Half Word through the SPI interface and return the Half Word received from the SPI bus.

Parameters:
HalfWord,: Half Word to send.
Return values:
The value of the received Half Word.

< Loop while DR register in not emplty

< Send Half Word through the sFLASH peripheral

< Wait to receive a Half Word

< Return the Half Word read from the SPI bus

Definition at line 459 of file stm32_eval_spi_flash.c.

References RESET, sFLASH_SPI, SPI_I2S_FLAG_RXNE, SPI_I2S_FLAG_TXE, SPI_I2S_GetFlagStatus(), SPI_I2S_ReceiveData(), and SPI_I2S_SendData().

void sFLASH_StartReadSequence ( uint32_t ReadAddr )

Initiates a read data byte (READ) sequence from the Flash.

This is done by driving the /CS line low to select the device, then the READ instruction is transmitted followed by 3 bytes address. This function exit and keep the /CS line low, so the Flash still being selected. With this technique the whole content of the Flash is read with a single READ instruction.

Parameters:
ReadAddr,: FLASH's internal address to read from.
Return values:
None

< Select the FLASH: Chip Select low

< Send "Read from Memory " instruction

< Send the 24-bit address of the address to read from -------------------

< Send ReadAddr high nibble address byte

< Send ReadAddr medium nibble address byte

< Send ReadAddr low nibble address byte

Definition at line 403 of file stm32_eval_spi_flash.c.

References sFLASH_CMD_READ, sFLASH_CS_LOW, and sFLASH_SendByte().

void sFLASH_WaitForWriteEnd ( void )

Polls the status of the Write In Progress (WIP) flag in the FLASH's status register and loop until write opertaion has completed.

Parameters:
None
Return values:
None

< Select the FLASH: Chip Select low

< Send "Read Status Register" instruction

< Loop as long as the memory is busy with a write cycle

< Send a dummy byte to generate the clock needed by the FLASH and put the value of the status register in FLASH_Status variable

< Deselect the FLASH: Chip Select high

Definition at line 497 of file stm32_eval_spi_flash.c.

References SET, sFLASH_CMD_RDSR, sFLASH_CS_HIGH, sFLASH_CS_LOW, sFLASH_DUMMY_BYTE, sFLASH_SendByte(), and sFLASH_WIP_FLAG.

Referenced by sFLASH_EraseBulk(), sFLASH_EraseSector(), and sFLASH_WritePage().

void sFLASH_WriteBuffer | ( | uint8_t * | pBuffer,
 |  | uint32_t | WriteAddr,
 |  | uint16_t | NumByteToWrite
 | ) |  |

Writes block of data to the FLASH.

In this function, the number of WRITE cycles are reduced, using Page WRITE sequence.

Parameters:
pBuffer,: pointer to the buffer containing the data to be written to the FLASH.
WriteAddr,: FLASH's internal address to write to.
NumByteToWrite,: number of bytes to write to the FLASH.
Return values:
None

< WriteAddr is sFLASH_PAGESIZE aligned

< NumByteToWrite < sFLASH_PAGESIZE

< NumByteToWrite > sFLASH_PAGESIZE

< WriteAddr is not sFLASH_PAGESIZE aligned

< NumByteToWrite < sFLASH_PAGESIZE

< (NumByteToWrite + WriteAddr) > sFLASH_PAGESIZE

< NumByteToWrite > sFLASH_PAGESIZE

Definition at line 257 of file stm32_eval_spi_flash.c.

References sFLASH_SPI_PAGESIZE, and sFLASH_WritePage().

Referenced by main().

void sFLASH_WriteEnable ( void )

Enables the write access to the FLASH.

Parameters:
None
Return values:
None

< Select the FLASH: Chip Select low

< Send "Write Enable" instruction

< Deselect the FLASH: Chip Select high

Definition at line 479 of file stm32_eval_spi_flash.c.

References sFLASH_CMD_WREN, sFLASH_CS_HIGH, sFLASH_CS_LOW, and sFLASH_SendByte().

Referenced by sFLASH_EraseBulk(), sFLASH_EraseSector(), and sFLASH_WritePage().

void sFLASH_WritePage | ( | uint8_t * | pBuffer,
 |  | uint32_t | WriteAddr,
 |  | uint16_t | NumByteToWrite
 | ) |  |

Writes more than one byte to the FLASH with a single WRITE cycle (Page WRITE sequence).

Note:
The number of byte can't exceed the FLASH page size.
Parameters:
pBuffer,: pointer to the buffer containing the data to be written to the FLASH.
WriteAddr,: FLASH's internal address to write to.
NumByteToWrite,: number of bytes to write to the FLASH, must be equal or less than "sFLASH_PAGESIZE" value.
Return values:
None

< Enable the write access to the FLASH

< Select the FLASH: Chip Select low

< Send "Write to Memory " instruction

< Send WriteAddr high nibble address byte to write to

< Send WriteAddr medium nibble address byte to write to

< Send WriteAddr low nibble address byte to write to

< while there is data to be written on the FLASH

< Send the current byte

< Point on the next byte to be written

< Wait the end of Flash writing

Definition at line 216 of file stm32_eval_spi_flash.c.

References sFLASH_CMD_WRITE, sFLASH_CS_HIGH, sFLASH_CS_LOW, sFLASH_SendByte(), sFLASH_WaitForWriteEnd(), and sFLASH_WriteEnable().

Referenced by sFLASH_WriteBuffer().


STM32F10x Standard Peripherals Firmware Library: STM32_EVAL_SPI_FLASH_Exported_Types

STM32_EVAL_SPI_FLASH_Exported_Types

STM32_EVAL_SPI_FLASH


STM32F10x Standard Peripherals Firmware Library: STM32_EVAL_SPI_FLASH_Exported_Constants

Defines

STM32_EVAL_SPI_FLASH_Exported_Constants

STM32_EVAL_SPI_FLASH

Defines

#define | sFLASH_CMD_BE 0xC7
#define | sFLASH_CMD_RDID 0x9F
#define | sFLASH_CMD_RDSR 0x05
#define | sFLASH_CMD_READ 0x03
#define | sFLASH_CMD_SE 0xD8
#define | sFLASH_CMD_WREN 0x06
#define | sFLASH_CMD_WRITE 0x02
M25P SPI Flash supported commands.
#define | sFLASH_CMD_WRSR 0x01
#define | sFLASH_DUMMY_BYTE 0xA5
#define | sFLASH_M25P128_ID 0x202018
#define | sFLASH_M25P64_ID 0x202017
#define | sFLASH_SPI_PAGESIZE 0x100
#define | sFLASH_WIP_FLAG 0x01

Define Documentation

#define sFLASH_CMD_BE 0xC7

Bulk Erase instruction

Definition at line 70 of file stm32_eval_spi_flash.h.

Referenced by sFLASH_EraseBulk().

#define sFLASH_CMD_RDID 0x9F

Read identification

Definition at line 68 of file stm32_eval_spi_flash.h.

#define sFLASH_CMD_RDSR 0x05

Read Status Register instruction

Definition at line 67 of file stm32_eval_spi_flash.h.

Referenced by sFLASH_WaitForWriteEnd().

#define sFLASH_CMD_READ 0x03

Read from Memory instruction

Definition at line 66 of file stm32_eval_spi_flash.h.

Referenced by sFLASH_ReadBuffer(), and sFLASH_StartReadSequence().

#define sFLASH_CMD_SE 0xD8

Sector Erase instruction

Definition at line 69 of file stm32_eval_spi_flash.h.

Referenced by sFLASH_EraseSector().

#define sFLASH_CMD_WREN 0x06

Write enable instruction

Definition at line 65 of file stm32_eval_spi_flash.h.

Referenced by sFLASH_WriteEnable().

#define sFLASH_CMD_WRITE 0x02

M25P SPI Flash supported commands.

Write to Memory instruction

Definition at line 63 of file stm32_eval_spi_flash.h.

Referenced by sFLASH_WritePage().

#define sFLASH_CMD_WRSR 0x01

Write Status Register instruction

Definition at line 64 of file stm32_eval_spi_flash.h.

#define sFLASH_DUMMY_BYTE 0xA5

Definition at line 74 of file stm32_eval_spi_flash.h.

Referenced by sFLASH_ReadBuffer(), sFLASH_ReadByte(), sFLASH_ReadID(), and sFLASH_WaitForWriteEnd().

#define sFLASH_M25P128_ID 0x202018

Definition at line 77 of file stm32_eval_spi_flash.h.

#define sFLASH_M25P64_ID 0x202017

Definition at line 78 of file stm32_eval_spi_flash.h.

#define sFLASH_SPI_PAGESIZE 0x100

Definition at line 75 of file stm32_eval_spi_flash.h.

Referenced by sFLASH_WriteBuffer().

#define sFLASH_WIP_FLAG 0x01

Write In Progress (WIP) flag

Definition at line 72 of file stm32_eval_spi_flash.h.

Referenced by sFLASH_WaitForWriteEnd().


STM32F10x Standard Peripherals Firmware Library: STM32_EVAL_SPI_FLASH_Exported_Macros

Defines

STM32_EVAL_SPI_FLASH_Exported_Macros

STM32_EVAL_SPI_FLASH

Defines

#define | sFLASH_CS_HIGH() GPIO_SetBits(sFLASH_CS_GPIO_PORT, sFLASH_CS_PIN)
Deselect sFLASH: Chip Select pin high.
#define | sFLASH_CS_LOW() GPIO_ResetBits(sFLASH_CS_GPIO_PORT, sFLASH_CS_PIN)
Select sFLASH: Chip Select pin low.

Define Documentation

#define sFLASH_CS_HIGH ( ) GPIO_SetBits(sFLASH_CS_GPIO_PORT, sFLASH_CS_PIN)

Deselect sFLASH: Chip Select pin high.

Definition at line 94 of file stm32_eval_spi_flash.h.

Referenced by sFLASH_EraseBulk(), sFLASH_EraseSector(), sFLASH_Init(), sFLASH_ReadBuffer(), sFLASH_ReadID(), sFLASH_WaitForWriteEnd(), sFLASH_WriteEnable(), and sFLASH_WritePage().

#define sFLASH_CS_LOW ( ) GPIO_ResetBits(sFLASH_CS_GPIO_PORT, sFLASH_CS_PIN)

Select sFLASH: Chip Select pin low.

Definition at line 90 of file stm32_eval_spi_flash.h.

Referenced by sFLASH_EraseBulk(), sFLASH_EraseSector(), sFLASH_ReadBuffer(), sFLASH_ReadID(), sFLASH_StartReadSequence(), sFLASH_WaitForWriteEnd(), sFLASH_WriteEnable(), and sFLASH_WritePage().


STM32F10x Standard Peripherals Firmware Library: STM32_EVAL_SPI_FLASH_Exported_Functions

Functions

STM32_EVAL_SPI_FLASH_Exported_Functions

STM32_EVAL_SPI_FLASH

Functions

void | sFLASH_DeInit (void)
High layer functions.
void | sFLASH_EraseBulk (void)
Erases the entire FLASH.
void | sFLASH_EraseSector (uint32_t SectorAddr)
Erases the specified FLASH sector.
void | sFLASH_Init (void)
Initializes the peripherals used by the SPI FLASH driver.
void | sFLASH_ReadBuffer (uint8_t *pBuffer, uint32_t ReadAddr, uint16_t NumByteToRead)
Reads a block of data from the FLASH.
uint8_t | sFLASH_ReadByte (void)
Low layer functions.
uint32_t | sFLASH_ReadID (void)
Reads FLASH identification.
uint8_t | sFLASH_SendByte (uint8_t byte)
Sends a byte through the SPI interface and return the byte received from the SPI bus.
uint16_t | sFLASH_SendHalfWord (uint16_t HalfWord)
Sends a Half Word through the SPI interface and return the Half Word received from the SPI bus.
void | sFLASH_StartReadSequence (uint32_t ReadAddr)
Initiates a read data byte (READ) sequence from the Flash.
void | sFLASH_WaitForWriteEnd (void)
Polls the status of the Write In Progress (WIP) flag in the FLASH's status register and loop until write opertaion has completed.
void | sFLASH_WriteBuffer (uint8_t *pBuffer, uint32_t WriteAddr, uint16_t NumByteToWrite)
Writes block of data to the FLASH.
void | sFLASH_WriteEnable (void)
Enables the write access to the FLASH.
void | sFLASH_WritePage (uint8_t *pBuffer, uint32_t WriteAddr, uint16_t NumByteToWrite)
Writes more than one byte to the FLASH with a single WRITE cycle (Page WRITE sequence).

Function Documentation

void sFLASH_DeInit ( void )

High layer functions.

High layer functions.

Parameters:
None
Return values:
None

Definition at line 115 of file stm32_eval_spi_flash.c.

References sFLASH_LowLevel_DeInit().

void sFLASH_EraseBulk ( void )

Erases the entire FLASH.

Parameters:
None
Return values:
None

< Send write enable instruction

< Bulk Erase

< Select the FLASH: Chip Select low

< Send Bulk Erase instruction

< Deselect the FLASH: Chip Select high

< Wait the end of Flash writing

Definition at line 188 of file stm32_eval_spi_flash.c.

References sFLASH_CMD_BE, sFLASH_CS_HIGH, sFLASH_CS_LOW, sFLASH_SendByte(), sFLASH_WaitForWriteEnd(), and sFLASH_WriteEnable().

void sFLASH_EraseSector ( uint32_t SectorAddr )

Erases the specified FLASH sector.

Parameters:
SectorAddr,: address of the sector to erase.
Return values:
None

< Send write enable instruction

< Sector Erase

< Select the FLASH: Chip Select low

< Send Sector Erase instruction

< Send SectorAddr high nibble address byte

< Send SectorAddr medium nibble address byte

< Send SectorAddr low nibble address byte

< Deselect the FLASH: Chip Select high

< Wait the end of Flash writing

Definition at line 160 of file stm32_eval_spi_flash.c.

References sFLASH_CMD_SE, sFLASH_CS_HIGH, sFLASH_CS_LOW, sFLASH_SendByte(), sFLASH_WaitForWriteEnd(), and sFLASH_WriteEnable().

Referenced by main().

void sFLASH_Init ( void )

Initializes the peripherals used by the SPI FLASH driver.

Parameters:
None
Return values:
None

< Deselect the FLASH: Chip Select high

< SPI configuration

< Enable the sFLASH_SPI

Definition at line 125 of file stm32_eval_spi_flash.c.

References ENABLE, sFLASH_CS_HIGH, sFLASH_LowLevel_Init(), sFLASH_SPI, SPI_InitTypeDef::SPI_BaudRatePrescaler, SPI_BaudRatePrescaler_2, SPI_BaudRatePrescaler_4, SPI_Cmd(), SPI_InitTypeDef::SPI_CPHA, SPI_CPHA_2Edge, SPI_InitTypeDef::SPI_CPOL, SPI_CPOL_High, SPI_InitTypeDef::SPI_CRCPolynomial, SPI_InitTypeDef::SPI_DataSize, SPI_DataSize_8b, SPI_InitTypeDef::SPI_Direction, SPI_Direction_2Lines_FullDuplex, SPI_InitTypeDef::SPI_FirstBit, SPI_FirstBit_MSB, SPI_Init(), SPI_InitStructure, SPI_InitTypeDef::SPI_Mode, SPI_Mode_Master, SPI_InitTypeDef::SPI_NSS, and SPI_NSS_Soft.

Referenced by main().

void sFLASH_ReadBuffer | ( | uint8_t * | pBuffer,
 |  | uint32_t | ReadAddr,
 |  | uint16_t | NumByteToRead
 | ) |  |

Reads a block of data from the FLASH.

Parameters:
pBuffer,: pointer to the buffer that receives the data read from the FLASH.
ReadAddr,: FLASH's internal address to read from.
NumByteToRead,: number of bytes to read from the FLASH.
Return values:
None

< Select the FLASH: Chip Select low

< Send "Read from Memory " instruction

< Send ReadAddr high nibble address byte to read from

< Send ReadAddr medium nibble address byte to read from

< Send ReadAddr low nibble address byte to read from

< while there is data to be read

< Read a byte from the FLASH

< Point to the next location where the byte read will be saved

Definition at line 335 of file stm32_eval_spi_flash.c.

References sFLASH_CMD_READ, sFLASH_CS_HIGH, sFLASH_CS_LOW, sFLASH_DUMMY_BYTE, and sFLASH_SendByte().

Referenced by main().

uint8_t sFLASH_ReadByte ( void )

Low layer functions.

Low layer functions.

Note:
This function must be used only if the Start_Read_Sequence function has been previously called.
Parameters:
None
Return values:
Byte Read from the SPI Flash.

Definition at line 427 of file stm32_eval_spi_flash.c.

References sFLASH_DUMMY_BYTE, and sFLASH_SendByte().

uint32_t sFLASH_ReadID ( void )

Reads FLASH identification.

Parameters:
None
Return values:
FLASH identification

< Select the FLASH: Chip Select low

< Send "RDID " instruction

< Read a byte from the FLASH

< Read a byte from the FLASH

< Read a byte from the FLASH

< Deselect the FLASH: Chip Select high

Definition at line 367 of file stm32_eval_spi_flash.c.

References sFLASH_CS_HIGH, sFLASH_CS_LOW, sFLASH_DUMMY_BYTE, and sFLASH_SendByte().

Referenced by main().

uint8_t sFLASH_SendByte ( uint8_t byte )

Sends a byte through the SPI interface and return the byte received from the SPI bus.

Parameters:
byte,: byte to send.
Return values:
The value of the received byte.

< Loop while DR register in not emplty

< Send byte through the SPI1 peripheral

< Wait to receive a byte

< Return the byte read from the SPI bus

Definition at line 438 of file stm32_eval_spi_flash.c.

References RESET, sFLASH_SPI, SPI_I2S_FLAG_RXNE, SPI_I2S_FLAG_TXE, SPI_I2S_GetFlagStatus(), SPI_I2S_ReceiveData(), and SPI_I2S_SendData().

Referenced by sFLASH_EraseBulk(), sFLASH_EraseSector(), sFLASH_ReadBuffer(), sFLASH_ReadByte(), sFLASH_ReadID(), sFLASH_StartReadSequence(), sFLASH_WaitForWriteEnd(), sFLASH_WriteEnable(), and sFLASH_WritePage().

uint16_t sFLASH_SendHalfWord ( uint16_t HalfWord )

Sends a Half Word through the SPI interface and return the Half Word received from the SPI bus.

Parameters:
HalfWord,: Half Word to send.
Return values:
The value of the received Half Word.

< Loop while DR register in not emplty

< Send Half Word through the sFLASH peripheral

< Wait to receive a Half Word

< Return the Half Word read from the SPI bus

Definition at line 459 of file stm32_eval_spi_flash.c.

References RESET, sFLASH_SPI, SPI_I2S_FLAG_RXNE, SPI_I2S_FLAG_TXE, SPI_I2S_GetFlagStatus(), SPI_I2S_ReceiveData(), and SPI_I2S_SendData().

void sFLASH_StartReadSequence ( uint32_t ReadAddr )

Initiates a read data byte (READ) sequence from the Flash.

This is done by driving the /CS line low to select the device, then the READ instruction is transmitted followed by 3 bytes address. This function exit and keep the /CS line low, so the Flash still being selected. With this technique the whole content of the Flash is read with a single READ instruction.

Parameters:
ReadAddr,: FLASH's internal address to read from.
Return values:
None

< Select the FLASH: Chip Select low

< Send "Read from Memory " instruction

< Send the 24-bit address of the address to read from -------------------

< Send ReadAddr high nibble address byte

< Send ReadAddr medium nibble address byte

< Send ReadAddr low nibble address byte

Definition at line 403 of file stm32_eval_spi_flash.c.

References sFLASH_CMD_READ, sFLASH_CS_LOW, and sFLASH_SendByte().

void sFLASH_WaitForWriteEnd ( void )

Polls the status of the Write In Progress (WIP) flag in the FLASH's status register and loop until write opertaion has completed.

Parameters:
None
Return values:
None

< Select the FLASH: Chip Select low

< Send "Read Status Register" instruction

< Loop as long as the memory is busy with a write cycle

< Send a dummy byte to generate the clock needed by the FLASH and put the value of the status register in FLASH_Status variable

< Deselect the FLASH: Chip Select high

Definition at line 497 of file stm32_eval_spi_flash.c.

References SET, sFLASH_CMD_RDSR, sFLASH_CS_HIGH, sFLASH_CS_LOW, sFLASH_DUMMY_BYTE, sFLASH_SendByte(), and sFLASH_WIP_FLAG.

Referenced by sFLASH_EraseBulk(), sFLASH_EraseSector(), and sFLASH_WritePage().

void sFLASH_WriteBuffer | ( | uint8_t * | pBuffer,
 |  | uint32_t | WriteAddr,
 |  | uint16_t | NumByteToWrite
 | ) |  |

Writes block of data to the FLASH.

In this function, the number of WRITE cycles are reduced, using Page WRITE sequence.

Parameters:
pBuffer,: pointer to the buffer containing the data to be written to the FLASH.
WriteAddr,: FLASH's internal address to write to.
NumByteToWrite,: number of bytes to write to the FLASH.
Return values:
None

< WriteAddr is sFLASH_PAGESIZE aligned

< NumByteToWrite < sFLASH_PAGESIZE

< NumByteToWrite > sFLASH_PAGESIZE

< WriteAddr is not sFLASH_PAGESIZE aligned

< NumByteToWrite < sFLASH_PAGESIZE

< (NumByteToWrite + WriteAddr) > sFLASH_PAGESIZE

< NumByteToWrite > sFLASH_PAGESIZE

Definition at line 257 of file stm32_eval_spi_flash.c.

References sFLASH_SPI_PAGESIZE, and sFLASH_WritePage().

Referenced by main().

void sFLASH_WriteEnable ( void )

Enables the write access to the FLASH.

Parameters:
None
Return values:
None

< Select the FLASH: Chip Select low

< Send "Write Enable" instruction

< Deselect the FLASH: Chip Select high

Definition at line 479 of file stm32_eval_spi_flash.c.

References sFLASH_CMD_WREN, sFLASH_CS_HIGH, sFLASH_CS_LOW, and sFLASH_SendByte().

Referenced by sFLASH_EraseBulk(), sFLASH_EraseSector(), and sFLASH_WritePage().

void sFLASH_WritePage | ( | uint8_t * | pBuffer,
 |  | uint32_t | WriteAddr,
 |  | uint16_t | NumByteToWrite
 | ) |  |

Writes more than one byte to the FLASH with a single WRITE cycle (Page WRITE sequence).

Note:
The number of byte can't exceed the FLASH page size.
Parameters:
pBuffer,: pointer to the buffer containing the data to be written to the FLASH.
WriteAddr,: FLASH's internal address to write to.
NumByteToWrite,: number of bytes to write to the FLASH, must be equal or less than "sFLASH_PAGESIZE" value.
Return values:
None

< Enable the write access to the FLASH

< Select the FLASH: Chip Select low

< Send "Write to Memory " instruction

< Send WriteAddr high nibble address byte to write to

< Send WriteAddr medium nibble address byte to write to

< Send WriteAddr low nibble address byte to write to

< while there is data to be written on the FLASH

< Send the current byte

< Point on the next byte to be written

< Wait the end of Flash writing

Definition at line 216 of file stm32_eval_spi_flash.c.

References sFLASH_CMD_WRITE, sFLASH_CS_HIGH, sFLASH_CS_LOW, sFLASH_SendByte(), sFLASH_WaitForWriteEnd(), and sFLASH_WriteEnable().

Referenced by sFLASH_WriteBuffer().


STM32F10x Standard Peripherals Firmware Library: STM32_EVAL_SPI_SD_Private_Types

STM32_EVAL_SPI_SD_Private_Types

STM32_EVAL_SPI_SD


STM32F10x Standard Peripherals Firmware Library: STM32_EVAL_SPI_SD_Private_Defines

STM32_EVAL_SPI_SD_Private_Defines

STM32_EVAL_SPI_SD


STM32F10x Standard Peripherals Firmware Library: STM32_EVAL_SPI_SD_Private_Macros

STM32_EVAL_SPI_SD_Private_Macros

STM32_EVAL_SPI_SD


STM32F10x Standard Peripherals Firmware Library: STM32_EVAL_SPI_SD_Private_Variables

STM32_EVAL_SPI_SD_Private_Variables

STM32_EVAL_SPI_SD


STM32F10x Standard Peripherals Firmware Library: STM32_EVAL_SPI_SD_Private_Function_Prototypes

STM32_EVAL_SPI_SD_Private_Function_Prototypes

STM32_EVAL_SPI_SD


STM32F10x Standard Peripherals Firmware Library: STM32_EVAL_SPI_SD_Private_Functions

Functions

STM32_EVAL_SPI_SD_Private_Functions

STM32_EVAL_SPI_SD

Functions

void | SD_DeInit (void)
DeInitializes the SD/SD communication.
uint8_t | SD_Detect (void)
Detect if SD card is correctly plugged in the memory slot.
SD_Error | SD_GetCardInfo (SD_CardInfo *cardinfo)
Returns information about specific card.
SD_Error | SD_GetCIDRegister (SD_CID *SD_cid)
Read the CID card register.
SD_Error | SD_GetCSDRegister (SD_CSD *SD_csd)
Read the CSD card register.
uint8_t | SD_GetDataResponse (void)
Get SD card data response.
SD_Error | SD_GetResponse (uint8_t Response)
Returns the SD response.
uint16_t | SD_GetStatus (void)
Returns the SD status.
SD_Error | SD_GoIdleState (void)
Put SD in Idle state.
SD_Error | SD_Init (void)
Initializes the SD/SD communication.
SD_Error | SD_ReadBlock (uint8_t *pBuffer, uint32_t ReadAddr, uint16_t BlockSize)
Reads a block of data from the SD.
uint8_t | SD_ReadByte (void)
Read a byte from the SD.
SD_Error | SD_ReadMultiBlocks (uint8_t *pBuffer, uint32_t ReadAddr, uint16_t BlockSize, uint32_t NumberOfBlocks)
Reads multiple block of data from the SD.
void | SD_SendCmd (uint8_t Cmd, uint32_t Arg, uint8_t Crc)
Send 5 bytes command to the SD card.
SD_Error | SD_WriteBlock (uint8_t *pBuffer, uint32_t WriteAddr, uint16_t BlockSize)
Writes a block on the SD.
uint8_t | SD_WriteByte (uint8_t Data)
Write a byte on the SD.
SD_Error | SD_WriteMultiBlocks (uint8_t *pBuffer, uint32_t WriteAddr, uint16_t BlockSize, uint32_t NumberOfBlocks)
Writes many blocks on the SD.

Function Documentation

void SD_DeInit ( void )

DeInitializes the SD/SD communication.

DeInitializes the SDIO interface.

Parameters:
None
Return values:
None

Definition at line 114 of file stm32_eval_spi_sd.c.

References SD_LowLevel_DeInit().

uint8_t SD_Detect ( void )

Detect if SD card is correctly plugged in the memory slot.

Parameters:
None
Return values:
Return if SD is detected or not

< Check GPIO to detect SD

Definition at line 153 of file stm32_eval_spi_sd.c.

References Bit_RESET, GPIO_ReadInputData(), GPIO_ReadInputDataBit(), SD_DETECT_GPIO_PORT, SD_DETECT_PIN, SD_NOT_PRESENT, SD_PRESENT, and status.

SD_Error SD_GetCardInfo ( SD_CardInfo * cardinfo )

Returns information about specific card.

Parameters:
cardinfo,: pointer to a SD_CardInfo structure that contains all SD card information.
Return values:
The SD Response:

  • SD_RESPONSE_FAILURE: Sequence failed
  • SD_RESPONSE_NO_ERROR: Sequence succeed

< Returns the reponse

Definition at line 173 of file stm32_eval_spi_sd.c.

References SD_CardInfo::CardBlockSize, SD_CardInfo::CardCapacity, SD_CSD::CardComdClasses, CardType, SD_CardInfo::CardType, SD_CID::CID_CRC, CID_Tab, SD_CSD::ContentProtectAppli, SD_CSD::CopyFlag, SD_CSD::CSD_CRC, CSD_Tab, SD_CSD::CSDStruct, SD_CSD::DeviceSize, SD_CSD::DeviceSizeMul, SD_CSD::DSRImpl, SD_CSD::ECC, SD_CSD::EraseGrMul, SD_CSD::EraseGrSize, SD_CSD::FileFormat, SD_CSD::FileFormatGrouop, SD_CSD::ManDeflECC, SD_CID::ManufactDate, SD_CID::ManufacturerID, SD_CSD::MaxBusClkFrec, SD_CSD::MaxRdCurrentVDDMax, SD_CSD::MaxRdCurrentVDDMin, SD_CSD::MaxWrBlockLen, SD_CSD::MaxWrCurrentVDDMax, SD_CSD::MaxWrCurrentVDDMin, SD_CSD::NSAC, SD_CID::OEM_AppliID, SD_CSD::PartBlockRead, SD_CSD::PermWrProtect, SD_CID::ProdName1, SD_CID::ProdName2, SD_CID::ProdRev, SD_CID::ProdSN, RCA, SD_CardInfo::RCA, SD_CSD::RdBlockLen, SD_CSD::RdBlockMisalign, SD_CID::Reserved1, SD_CSD::Reserved1, SD_CID::Reserved2, SD_CSD::Reserved2, SD_CSD::Reserved3, SD_CSD::Reserved4, SD_CardInfo::SD_cid, SD_CardInfo::SD_csd, SD_GetCIDRegister(), SD_GetCSDRegister(), SD_OK, SD_RESPONSE_FAILURE, SDIO_HIGH_CAPACITY_SD_CARD, SDIO_STD_CAPACITY_SD_CARD_V1_1, SDIO_STD_CAPACITY_SD_CARD_V2_0, status, SD_CSD::SysSpecVersion, SD_CSD::TAAC, SD_CSD::TempWrProtect, SD_CSD::WrBlockMisalign, SD_CSD::WriteBlockPaPartial, SD_CSD::WrProtectGrEnable, SD_CSD::WrProtectGrSize, and SD_CSD::WrSpeedFact.

SD_Error SD_GetCIDRegister ( SD_CID * SD_cid )

Read the CID card register.

Reading the contents of the CID register in SPI mode is a simple read-block transaction.

Parameters:
SD_cid,: pointer on an CID register structure
Return values:
The SD Response:

  • SD_RESPONSE_FAILURE: Sequence failed
  • SD_RESPONSE_NO_ERROR: Sequence succeed

< SD chip select low

< Send CMD10 (CID register)

< Wait for response in the R1 format (0x00 is no errors)

< Store CID register value on CID_Tab

< Set response value to success

< Send dummy byte: 8 Clock pulses of delay

< Byte 0

< Byte 1

< Byte 2

< Byte 3

< Byte 4

< Byte 5

< Byte 6

< Byte 7

< Byte 8

< Byte 9

< Byte 10

< Byte 11

< Byte 12

< Byte 13

< Byte 14

< Byte 15

< Return the reponse

Definition at line 555 of file stm32_eval_spi_sd.c.

References SD_CID::CID_CRC, CID_Tab, SD_CID::ManufactDate, SD_CID::ManufacturerID, SD_CID::OEM_AppliID, SD_CID::ProdName1, SD_CID::ProdName2, SD_CID::ProdRev, SD_CID::ProdSN, SD_CID::Reserved1, SD_CID::Reserved2, SD_CMD_SEND_CID, SD_CS_HIGH, SD_CS_LOW, SD_DUMMY_BYTE, SD_GetResponse(), SD_ReadByte(), SD_RESPONSE_FAILURE, SD_RESPONSE_NO_ERROR, SD_SendCmd(), SD_START_DATA_SINGLE_BLOCK_READ, and SD_WriteByte().

Referenced by SD_GetCardInfo().

SD_Error SD_GetCSDRegister ( SD_CSD * SD_csd )

Read the CSD card register.

Reading the contents of the CSD register in SPI mode is a simple read-block transaction.

Parameters:
SD_csd,: pointer on an SCD register structure
Return values:
The SD Response:

  • SD_RESPONSE_FAILURE: Sequence failed
  • SD_RESPONSE_NO_ERROR: Sequence succeed

< SD chip select low

< Send CMD9 (CSD register) or CMD10(CSD register)

< Wait for response in the R1 format (0x00 is no errors)

< Store CSD register value on CSD_Tab

< Set response value to success

< Send dummy byte: 8 Clock pulses of delay

< Byte 0

< Byte 1

< Byte 2

< Byte 3

< Byte 4

< Byte 5

< Byte 6

< Reserved

< Byte 7

< Byte 8

< Byte 9

< Byte 10

< Byte 11

< Byte 12

< Byte 13

< Byte 14

< Byte 15

< Return the reponse

Definition at line 433 of file stm32_eval_spi_sd.c.

References SD_CSD::CardComdClasses, SD_CSD::ContentProtectAppli, SD_CSD::CopyFlag, SD_CSD::CSD_CRC, CSD_Tab, SD_CSD::CSDStruct, SD_CSD::DeviceSize, SD_CSD::DeviceSizeMul, SD_CSD::DSRImpl, SD_CSD::ECC, SD_CSD::EraseGrMul, SD_CSD::EraseGrSize, SD_CSD::FileFormat, SD_CSD::FileFormatGrouop, SD_CSD::ManDeflECC, SD_CSD::MaxBusClkFrec, SD_CSD::MaxRdCurrentVDDMax, SD_CSD::MaxRdCurrentVDDMin, SD_CSD::MaxWrBlockLen, SD_CSD::MaxWrCurrentVDDMax, SD_CSD::MaxWrCurrentVDDMin, SD_CSD::NSAC, SD_CSD::PartBlockRead, SD_CSD::PermWrProtect, SD_CSD::RdBlockLen, SD_CSD::RdBlockMisalign, SD_CSD::Reserved1, SD_CSD::Reserved2, SD_CSD::Reserved3, SD_CSD::Reserved4, SD_CMD_SEND_CSD, SD_CS_HIGH, SD_CS_LOW, SD_DUMMY_BYTE, SD_GetResponse(), SD_ReadByte(), SD_RESPONSE_FAILURE, SD_RESPONSE_NO_ERROR, SD_SendCmd(), SD_START_DATA_SINGLE_BLOCK_READ, SD_WriteByte(), SD_CSD::SysSpecVersion, SD_CSD::TAAC, SD_CSD::TempWrProtect, SD_CSD::WrBlockMisalign, SD_CSD::WriteBlockPaPartial, SD_CSD::WrProtectGrEnable, SD_CSD::WrProtectGrSize, and SD_CSD::WrSpeedFact.

Referenced by SD_GetCardInfo().

uint8_t SD_GetDataResponse ( void )

Get SD card data response.

Parameters:
None
Return values:
The SD status: Read data response xxx0<status>1

  • status 010: Data accecpted
  • status 101: Data rejected due to a crc error
  • status 110: Data rejected due to a Write error.
  • status 111: Data rejected due to other error.

< Read resonse

< Mask unused bits

< Increment loop counter

< Return response

Definition at line 683 of file stm32_eval_spi_sd.c.

References SD_DATA_CRC_ERROR, SD_DATA_OK, SD_DATA_OTHER_ERROR, SD_DATA_WRITE_ERROR, and SD_ReadByte().

Referenced by SD_WriteBlock(), and SD_WriteMultiBlocks().

SD_Error SD_GetResponse ( uint8_t Response )

Returns the SD response.

Parameters:
None
Return values:
The SD Response:

  • SD_RESPONSE_FAILURE: Sequence failed
  • SD_RESPONSE_NO_ERROR: Sequence succeed

< Check if response is got or a timeout is happen

< After time out

< Right response got

Definition at line 732 of file stm32_eval_spi_sd.c.

References SD_ReadByte(), SD_RESPONSE_FAILURE, and SD_RESPONSE_NO_ERROR.

Referenced by SD_GetCIDRegister(), SD_GetCSDRegister(), SD_GoIdleState(), SD_ReadBlock(), SD_ReadMultiBlocks(), SD_WriteBlock(), and SD_WriteMultiBlocks().

uint16_t SD_GetStatus ( void )

Returns the SD status.

Gets the cuurent sd card data transfer status.

Parameters:
None
Return values:
The SD status.

< SD chip select low

< Send CMD13 (SD_SEND_STATUS) to get SD status

< SD chip select high

< Send dummy byte 0xFF

Definition at line 758 of file stm32_eval_spi_sd.c.

References SD_CARD_ERROR, SD_CARD_TRANSFER, SD_CMD_SEND_STATUS, SD_CS_HIGH, SD_CS_LOW, SD_DUMMY_BYTE, SD_GetState(), SD_ReadByte(), SD_SendCmd(), SD_TRANSFER_BUSY, SD_TRANSFER_ERROR, SD_TRANSFER_OK, SD_WriteByte(), and Status.

SD_Error SD_GoIdleState ( void )

Put SD in Idle state.

Parameters:
None
Return values:
The SD Response:

  • SD_RESPONSE_FAILURE: Sequence failed
  • SD_RESPONSE_NO_ERROR: Sequence succeed

< SD chip select low

< Send CMD0 (SD_CMD_GO_IDLE_STATE) to put SD in SPI mode

< Wait for In Idle State Response (R1 Format) equal to 0x01

< No Idle State Response: return response failue

< SD chip select high

< Send Dummy byte 0xFF

< SD chip select low

< Send CMD1 (Activates the card process) until response equal to 0x0

< Wait for no error Response (R1 Format) equal to 0x00

< SD chip select high

< Send dummy byte 0xFF

Definition at line 787 of file stm32_eval_spi_sd.c.

References SD_CMD_GO_IDLE_STATE, SD_CMD_SEND_OP_COND, SD_CS_HIGH, SD_CS_LOW, SD_DUMMY_BYTE, SD_GetResponse(), SD_IN_IDLE_STATE, SD_RESPONSE_FAILURE, SD_RESPONSE_NO_ERROR, SD_SendCmd(), and SD_WriteByte().

Referenced by SD_Init().

SD_Error SD_Init ( void )

Initializes the SD/SD communication.

Initializes the SD Card and put it into StandBy State (Ready for data transfer).

Parameters:
None
Return values:
The SD Response:

  • SD_RESPONSE_FAILURE: Sequence failed
  • SD_RESPONSE_NO_ERROR: Sequence succeed

< Initialize SD_SPI

< SD chip select high

< Send dummy byte 0xFF, 10 times with CS high

< Rise CS and MOSI for 80 clocks cycles

< Send dummy byte 0xFF

< SD initialized and set to SPI mode properly

Definition at line 126 of file stm32_eval_spi_sd.c.

References SD_CardInfo::RCA, SD_CS_HIGH, SD_DUMMY_BYTE, SD_EnableWideBusOperation(), SD_GetCardInfo(), SD_GoIdleState(), SD_InitializeCards(), SD_LowLevel_Init(), SD_OK, SD_PowerON(), SD_SelectDeselect(), SD_WriteByte(), SDIO_InitTypeDef::SDIO_BusWide, SDIO_BusWide_1b, SDIO_BusWide_4b, SDIO_InitTypeDef::SDIO_ClockBypass, SDIO_ClockBypass_Disable, SDIO_InitTypeDef::SDIO_ClockDiv, SDIO_InitTypeDef::SDIO_ClockEdge, SDIO_ClockEdge_Rising, SDIO_InitTypeDef::SDIO_ClockPowerSave, SDIO_ClockPowerSave_Disable, SDIO_DeInit(), SDIO_InitTypeDef::SDIO_HardwareFlowControl, SDIO_HardwareFlowControl_Disable, SDIO_Init(), and SDIO_TRANSFER_CLK_DIV.

SD_Error SD_ReadBlock | ( | uint8_t * | pBuffer,
 |  | uint32_t | ReadAddr,
 |  | uint16_t | BlockSize
 | ) |  |

Reads a block of data from the SD.

Allows to read one block from a specified address in a card.

Parameters:
pBuffer,: pointer to the buffer that receives the data read from the SD.
ReadAddr,: SD's internal address to read from.
BlockSize,: the SD card Data block size.
Return values:
The SD Response:

  • SD_RESPONSE_FAILURE: Sequence failed
  • SD_RESPONSE_NO_ERROR: Sequence succeed

< SD chip select low

< Send CMD17 (SD_CMD_READ_SINGLE_BLOCK) to read one block

< Check if the SD acknowledged the read block command: R1 response (0x00: no errors)

< Now look for the data token to signify the start of the data

< Read the SD block data : read NumByteToRead data

< Save the received data

< Point to the next location where the byte read will be saved

< Set response value to success

< Send dummy byte: 8 Clock pulses of delay

< Returns the reponse

Definition at line 198 of file stm32_eval_spi_sd.c.

References CardType, CmdResp1Error(), ENABLE, RESET, SD_CMD_READ_SINGLE_BLOCK, SD_CS_HIGH, SD_CS_LOW, SD_DATA_CRC_FAIL, SD_DATA_TIMEOUT, SD_DATATIMEOUT, SD_DUMMY_BYTE, SD_GetResponse(), SD_LowLevel_DMA_RxConfig(), SD_OK, SD_ReadByte(), SD_RESPONSE_FAILURE, SD_RESPONSE_NO_ERROR, SD_RX_OVERRUN, SD_SendCmd(), SD_START_BIT_ERR, SD_START_DATA_SINGLE_BLOCK_READ, SD_WriteByte(), SDIO, SDIO_CmdInitTypeDef::SDIO_Argument, SDIO_ClearFlag(), SDIO_CmdInitTypeDef::SDIO_CmdIndex, SDIO_CmdInitTypeDef::SDIO_CPSM, SDIO_CPSM_Enable, SDIO_DataInitTypeDef::SDIO_DataBlockSize, SDIO_DataConfig(), SDIO_DataInitTypeDef::SDIO_DataLength, SDIO_DataInitTypeDef::SDIO_DataTimeOut, SDIO_DMACmd(), SDIO_DataInitTypeDef::SDIO_DPSM, SDIO_DPSM_Enable, SDIO_FLAG_DBCKEND, SDIO_FLAG_DCRCFAIL, SDIO_FLAG_DTIMEOUT, SDIO_FLAG_RXDAVL, SDIO_FLAG_RXFIFOHF, SDIO_FLAG_RXOVERR, SDIO_FLAG_STBITERR, SDIO_GetFlagStatus(), SDIO_HIGH_CAPACITY_SD_CARD, SDIO_IT_DATAEND, SDIO_ITConfig(), SDIO_ReadData(), SDIO_CmdInitTypeDef::SDIO_Response, SDIO_Response_Short, SDIO_SendCommand(), SDIO_STATIC_FLAGS, SDIO_DataInitTypeDef::SDIO_TransferDir, SDIO_TransferDir_ToSDIO, SDIO_DataInitTypeDef::SDIO_TransferMode, SDIO_TransferMode_Block, SDIO_CmdInitTypeDef::SDIO_Wait, SDIO_Wait_No, StopCondition, TransferEnd, and TransferError.

uint8_t SD_ReadByte ( void )

Read a byte from the SD.

Parameters:
None
Return values:
The received byte.

< Wait until the transmit buffer is empty

< Wait until a data is received

< Return the shifted data

Definition at line 857 of file stm32_eval_spi_sd.c.

References Data, RESET, SD_DUMMY_BYTE, SD_SPI, SPI_I2S_FLAG_RXNE, SPI_I2S_FLAG_TXE, SPI_I2S_GetFlagStatus(), SPI_I2S_ReceiveData(), and SPI_I2S_SendData().

Referenced by SD_GetCIDRegister(), SD_GetCSDRegister(), SD_GetDataResponse(), SD_GetResponse(), SD_GetStatus(), SD_ReadBlock(), SD_ReadMultiBlocks(), SD_WriteBlock(), and SD_WriteMultiBlocks().

SD_Error SD_ReadMultiBlocks | ( | uint8_t * | pBuffer,
 |  | uint32_t | ReadAddr,
 |  | uint16_t | BlockSize,
 |  | uint32_t | NumberOfBlocks
 | ) |  |

Reads multiple block of data from the SD.

Allows to read blocks from a specified address in a card.

Parameters:
pBuffer,: pointer to the buffer that receives the data read from the SD.
ReadAddr,: SD's internal address to read from.
BlockSize,: the SD card Data block size.
NumberOfBlocks,: number of blocks to be read.
Return values:
The SD Response:

  • SD_RESPONSE_FAILURE: Sequence failed
  • SD_RESPONSE_NO_ERROR: Sequence succeed

< SD chip select low

< Data transfer

< Send CMD17 (SD_CMD_READ_SINGLE_BLOCK) to read one block

< Check if the SD acknowledged the read block command: R1 response (0x00: no errors)

< Read the SD block data : read NumByteToRead data

< Read the pointed data

< Point to the next location where the byte read will be saved

< get CRC bytes (not really needed by us, but required by SD)

< Set response value to success

< Set response value to failure

< Send dummy byte: 8 Clock pulses of delay

< Returns the reponse

Definition at line 252 of file stm32_eval_spi_sd.c.

References CardType, CmdResp1Error(), ENABLE, SD_CMD_READ_MULT_BLOCK, SD_CMD_READ_SINGLE_BLOCK, SD_CMD_SET_BLOCKLEN, SD_CS_HIGH, SD_CS_LOW, SD_DATATIMEOUT, SD_DUMMY_BYTE, SD_GetResponse(), SD_LowLevel_DMA_RxConfig(), SD_OK, SD_ReadByte(), SD_RESPONSE_FAILURE, SD_RESPONSE_NO_ERROR, SD_SendCmd(), SD_START_DATA_SINGLE_BLOCK_READ, SD_WriteByte(), SDIO, SDIO_CmdInitTypeDef::SDIO_Argument, SDIO_CmdInitTypeDef::SDIO_CmdIndex, SDIO_CmdInitTypeDef::SDIO_CPSM, SDIO_CPSM_Enable, SDIO_DataInitTypeDef::SDIO_DataBlockSize, SDIO_DataConfig(), SDIO_DataInitTypeDef::SDIO_DataLength, SDIO_DataInitTypeDef::SDIO_DataTimeOut, SDIO_DMACmd(), SDIO_DataInitTypeDef::SDIO_DPSM, SDIO_DPSM_Enable, SDIO_HIGH_CAPACITY_SD_CARD, SDIO_IT_DATAEND, SDIO_ITConfig(), SDIO_CmdInitTypeDef::SDIO_Response, SDIO_Response_Short, SDIO_SendCommand(), SDIO_DataInitTypeDef::SDIO_TransferDir, SDIO_TransferDir_ToSDIO, SDIO_DataInitTypeDef::SDIO_TransferMode, SDIO_TransferMode_Block, SDIO_CmdInitTypeDef::SDIO_Wait, SDIO_Wait_No, StopCondition, TransferEnd, and TransferError.

void SD_SendCmd | ( | uint8_t | Cmd,
 |  | uint32_t | Arg,
 |  | uint8_t | Crc
 | ) |  |

Send 5 bytes command to the SD card.

Parameters:
Cmd,: The user expected command to send to SD card.
Arg,: The command argument.
Crc,: The CRC.
Return values:
None

< Construct byte 1

< Construct byte 2

< Construct byte 3

< Construct byte 4

< Construct byte 5

< Construct CRC: byte 6

< Send the Cmd bytes

Definition at line 650 of file stm32_eval_spi_sd.c.

References SD_WriteByte().

Referenced by SD_GetCIDRegister(), SD_GetCSDRegister(), SD_GetStatus(), SD_GoIdleState(), SD_ReadBlock(), SD_ReadMultiBlocks(), SD_WriteBlock(), and SD_WriteMultiBlocks().

SD_Error SD_WriteBlock | ( | uint8_t * | pBuffer,
 |  | uint32_t | WriteAddr,
 |  | uint16_t | BlockSize
 | ) |  |

Writes a block on the SD.

Allows to write one block starting from a specified address in a card.

Parameters:
pBuffer,: pointer to the buffer containing the data to be written on the SD.
WriteAddr,: address to write on.
BlockSize,: the SD card Data block size.
Return values:
The SD Response:

  • SD_RESPONSE_FAILURE: Sequence failed
  • SD_RESPONSE_NO_ERROR: Sequence succeed

< SD chip select low

< Send CMD24 (SD_CMD_WRITE_SINGLE_BLOCK) to write multiple block

< Check if the SD acknowledged the write block command: R1 response (0x00: no errors)

< Send a dummy byte

< Send the data token to signify the start of the data

< Write the block data to SD : write count data by block

< Send the pointed byte

< Point to the next location where the byte read will be saved

< Read data response

< Send dummy byte: 8 Clock pulses of delay

< Returns the reponse

Definition at line 312 of file stm32_eval_spi_sd.c.

References CardType, CmdResp1Error(), ENABLE, RESET, SD_CMD_WRITE_SINGLE_BLOCK, SD_CS_HIGH, SD_CS_LOW, SD_DATA_CRC_FAIL, SD_DATA_OK, SD_DATA_TIMEOUT, SD_DATATIMEOUT, SD_DUMMY_BYTE, SD_GetDataResponse(), SD_GetResponse(), SD_LowLevel_DMA_TxConfig(), SD_OK, SD_ReadByte(), SD_RESPONSE_FAILURE, SD_RESPONSE_NO_ERROR, SD_SendCmd(), SD_START_BIT_ERR, SD_TX_UNDERRUN, SD_WriteByte(), SDIO, SDIO_CmdInitTypeDef::SDIO_Argument, SDIO_ClearFlag(), SDIO_CmdInitTypeDef::SDIO_CmdIndex, SDIO_CmdInitTypeDef::SDIO_CPSM, SDIO_CPSM_Enable, SDIO_DataInitTypeDef::SDIO_DataBlockSize, SDIO_DataConfig(), SDIO_DataInitTypeDef::SDIO_DataLength, SDIO_DataInitTypeDef::SDIO_DataTimeOut, SDIO_DMACmd(), SDIO_DataInitTypeDef::SDIO_DPSM, SDIO_DPSM_Enable, SDIO_FLAG_DBCKEND, SDIO_FLAG_DCRCFAIL, SDIO_FLAG_DTIMEOUT, SDIO_FLAG_STBITERR, SDIO_FLAG_TXFIFOHE, SDIO_FLAG_TXUNDERR, SDIO_GetFlagStatus(), SDIO_HIGH_CAPACITY_SD_CARD, SDIO_IT_DATAEND, SDIO_ITConfig(), SDIO_CmdInitTypeDef::SDIO_Response, SDIO_Response_Short, SDIO_SendCommand(), SDIO_DataInitTypeDef::SDIO_TransferDir, SDIO_TransferDir_ToCard, SDIO_DataInitTypeDef::SDIO_TransferMode, SDIO_TransferMode_Block, SDIO_CmdInitTypeDef::SDIO_Wait, SDIO_Wait_No, SDIO_WriteData(), StopCondition, TransferEnd, and TransferError.

uint8_t SD_WriteByte ( uint8_t Data )

Write a byte on the SD.

Parameters:
Data,: byte to send.
Return values:
None

< Wait until the transmit buffer is empty

< Wait to receive a byte

Definition at line 833 of file stm32_eval_spi_sd.c.

References RESET, SD_SPI, SPI_I2S_FLAG_RXNE, SPI_I2S_FLAG_TXE, SPI_I2S_GetFlagStatus(), SPI_I2S_ReceiveData(), and SPI_I2S_SendData().

Referenced by SD_GetCIDRegister(), SD_GetCSDRegister(), SD_GetStatus(), SD_GoIdleState(), SD_Init(), SD_ReadBlock(), SD_ReadMultiBlocks(), SD_SendCmd(), SD_WriteBlock(), and SD_WriteMultiBlocks().

SD_Error SD_WriteMultiBlocks | ( | uint8_t * | pBuffer,
 |  | uint32_t | WriteAddr,
 |  | uint16_t | BlockSize,
 |  | uint32_t | NumberOfBlocks
 | ) |  |

Writes many blocks on the SD.

Allows to write blocks starting from a specified address in a card.

Parameters:
pBuffer,: pointer to the buffer containing the data to be written on the SD.
WriteAddr,: address to write on.
BlockSize,: the SD card Data block size.
NumberOfBlocks,: number of blocks to be written.
Return values:
The SD Response:

  • SD_RESPONSE_FAILURE: Sequence failed
  • SD_RESPONSE_NO_ERROR: Sequence succeed

< SD chip select low

< Data transfer

< Send CMD24 (SD_CMD_WRITE_SINGLE_BLOCK) to write blocks

< Check if the SD acknowledged the write block command: R1 response (0x00: no errors)

< Send the data token to signify the start of the data

< Write the block data to SD : write count data by block

< Send the pointed byte

< Point to the next location where the byte read will be saved

< Put CRC bytes (not really needed by us, but required by SD)

< Read data response

< Set response value to success

< Set response value to failure

< Send dummy byte: 8 Clock pulses of delay

< Returns the reponse

Definition at line 370 of file stm32_eval_spi_sd.c.

References CardType, CmdResp1Error(), ENABLE, RCA, SD_CMD_APP_CMD, SD_CMD_SET_BLOCK_COUNT, SD_CMD_WRITE_MULT_BLOCK, SD_CMD_WRITE_SINGLE_BLOCK, SD_CS_HIGH, SD_CS_LOW, SD_DATA_OK, SD_DATATIMEOUT, SD_DUMMY_BYTE, SD_GetDataResponse(), SD_GetResponse(), SD_LowLevel_DMA_TxConfig(), SD_OK, SD_ReadByte(), SD_RESPONSE_FAILURE, SD_RESPONSE_NO_ERROR, SD_SendCmd(), SD_START_DATA_SINGLE_BLOCK_WRITE, SD_WriteByte(), SDIO, SDIO_CmdInitTypeDef::SDIO_Argument, SDIO_CmdInitTypeDef::SDIO_CmdIndex, SDIO_CmdInitTypeDef::SDIO_CPSM, SDIO_CPSM_Enable, SDIO_DataInitTypeDef::SDIO_DataBlockSize, SDIO_DataConfig(), SDIO_DataInitTypeDef::SDIO_DataLength, SDIO_DataInitTypeDef::SDIO_DataTimeOut, SDIO_DMACmd(), SDIO_DataInitTypeDef::SDIO_DPSM, SDIO_DPSM_Enable, SDIO_HIGH_CAPACITY_SD_CARD, SDIO_IT_DATAEND, SDIO_ITConfig(), SDIO_CmdInitTypeDef::SDIO_Response, SDIO_Response_Short, SDIO_SendCommand(), SDIO_DataInitTypeDef::SDIO_TransferDir, SDIO_TransferDir_ToCard, SDIO_DataInitTypeDef::SDIO_TransferMode, SDIO_TransferMode_Block, SDIO_CmdInitTypeDef::SDIO_Wait, SDIO_Wait_No, StopCondition, TransferEnd, and TransferError.


STM32F10x Standard Peripherals Firmware Library: STM32_EVAL_SPI_SD_Exported_Types

Data Structures | Enumerations

STM32_EVAL_SPI_SD_Exported_Types

STM32_EVAL_SPI_SD

Data Structures

struct | SD_CardInfo
SD Card information. More...
struct | SD_CID
Card Identification Data: CID Register. More...
struct | SD_CSD
Card Specific Data: CSD Register. More...

Enumerations

enum SD_Error {
SD_CMD_CRC_FAIL = (1), SD_DATA_CRC_FAIL = (2), SD_CMD_RSP_TIMEOUT = (3), SD_DATA_TIMEOUT = (4),
SD_TX_UNDERRUN = (5), SD_RX_OVERRUN = (6), SD_START_BIT_ERR = (7), SD_CMD_OUT_OF_RANGE = (8),
SD_ADDR_MISALIGNED = (9), SD_BLOCK_LEN_ERR = (10), SD_ERASE_SEQ_ERR = (11), SD_BAD_ERASE_PARAM = (12),
SD_WRITE_PROT_VIOLATION = (13), SD_LOCK_UNLOCK_FAILED = (14), SD_COM_CRC_FAILED = (15), SD_ILLEGAL_CMD = (16),
SD_CARD_ECC_FAILED = (17), SD_CC_ERROR = (18), SD_GENERAL_UNKNOWN_ERROR = (19), SD_STREAM_READ_UNDERRUN = (20),
SD_STREAM_WRITE_OVERRUN = (21), SD_CID_CSD_OVERWRITE = (22), SD_WP_ERASE_SKIP = (23), SD_CARD_ECC_DISABLED = (24),
SD_ERASE_RESET = (25), SD_AKE_SEQ_ERROR = (26), SD_INVALID_VOLTRANGE = (27), SD_ADDR_OUT_OF_RANGE = (28),
SD_SWITCH_ERROR = (29), SD_SDIO_DISABLED = (30), SD_SDIO_FUNCTION_BUSY = (31), SD_SDIO_FUNCTION_FAILED = (32),
SD_SDIO_UNKNOWN_FUNCTION = (33), SD_INTERNAL_ERROR, SD_NOT_CONFIGURED, SD_REQUEST_PENDING,
SD_REQUEST_NOT_APPLICABLE, SD_INVALID_PARAMETER, SD_UNSUPPORTED_FEATURE, SD_UNSUPPORTED_HW,
SD_ERROR, SD_OK = 0, SD_RESPONSE_NO_ERROR = (0x00), SD_IN_IDLE_STATE = (0x01),
SD_ERASE_RESET = (0x02), SD_ILLEGAL_COMMAND = (0x04), SD_COM_CRC_ERROR = (0x08), SD_ERASE_SEQUENCE_ERROR = (0x10),
SD_ADDRESS_ERROR = (0x20), SD_PARAMETER_ERROR = (0x40), SD_RESPONSE_FAILURE = (0xFF), SD_DATA_OK = (0x05),
SD_DATA_CRC_ERROR = (0x0B), SD_DATA_WRITE_ERROR = (0x0D), SD_DATA_OTHER_ERROR = (0xFF)
}

Enumeration Type Documentation

enum SD_Error
Enumerator:
SD_CMD_CRC_FAIL

SDIO specific error defines.

Command response received (but CRC check failed)

SD_DATA_CRC_FAIL

Data bock sent/received (CRC check Failed)

SD_CMD_RSP_TIMEOUT

Command response timeout

SD_DATA_TIMEOUT

Data time out

SD_TX_UNDERRUN

Transmit FIFO under-run

SD_RX_OVERRUN

Receive FIFO over-run

SD_START_BIT_ERR

Start bit not detected on all data signals in widE bus mode

SD_CMD_OUT_OF_RANGE

CMD's argument was out of range.

SD_ADDR_MISALIGNED

Misaligned address

SD_BLOCK_LEN_ERR

Transferred block length is not allowed for the card or the number of transferred bytes does not match the block length

SD_ERASE_SEQ_ERR

An error in the sequence of erase command occurs.

SD_BAD_ERASE_PARAM

An Invalid selection for erase groups

SD_WRITE_PROT_VIOLATION

Attempt to program a write protect block

SD_LOCK_UNLOCK_FAILED

Sequence or password error has been detected in unlock command or if there was an attempt to access a locked card

SD_COM_CRC_FAILED

CRC check of the previous command failed

SD_ILLEGAL_CMD

Command is not legal for the card state

SD_CARD_ECC_FAILED

Card internal ECC was applied but failed to correct the data

SD_CC_ERROR

Internal card controller error

SD_GENERAL_UNKNOWN_ERROR

General or Unknown error

SD_STREAM_READ_UNDERRUN

The card could not sustain data transfer in stream read operation.

SD_STREAM_WRITE_OVERRUN

The card could not sustain data programming in stream mode

SD_CID_CSD_OVERWRITE

CID/CSD overwrite error

SD_WP_ERASE_SKIP

only partial address space was erased

SD_CARD_ECC_DISABLED

Command has been executed without using internal ECC

SD_ERASE_RESET

Erase sequence was cleared before executing because an out of erase sequence command was received

SD_AKE_SEQ_ERROR

Error in sequence of authentication.

SD_INVALID_VOLTRANGE
SD_ADDR_OUT_OF_RANGE
SD_SWITCH_ERROR
SD_SDIO_DISABLED
SD_SDIO_FUNCTION_BUSY
SD_SDIO_FUNCTION_FAILED
SD_SDIO_UNKNOWN_FUNCTION
SD_INTERNAL_ERROR

Standard error defines.

SD_NOT_CONFIGURED
SD_REQUEST_PENDING
SD_REQUEST_NOT_APPLICABLE
SD_INVALID_PARAMETER
SD_UNSUPPORTED_FEATURE
SD_UNSUPPORTED_HW
SD_ERROR
SD_OK
SD_RESPONSE_NO_ERROR

SD reponses and error flags.

SD_IN_IDLE_STATE
SD_ERASE_RESET
SD_ILLEGAL_COMMAND
SD_COM_CRC_ERROR
SD_ERASE_SEQUENCE_ERROR
SD_ADDRESS_ERROR
SD_PARAMETER_ERROR
SD_RESPONSE_FAILURE
SD_DATA_OK

Data response error.

SD_DATA_CRC_ERROR
SD_DATA_WRITE_ERROR
SD_DATA_OTHER_ERROR

Definition at line 54 of file stm32_eval_spi_sd.h.


STM32F10x Standard Peripherals Firmware Library: STM32_EVAL_SPI_SD_Exported_Constants

Defines

STM32_EVAL_SPI_SD_Exported_Constants

STM32_EVAL_SPI_SD

Defines

#define | SD_BLOCK_SIZE 0x200
Block Size.
#define | SD_CMD_CLR_WRITE_PROT 29
#define | SD_CMD_ERASE 38
#define | SD_CMD_ERASE_GRP_END 36
#define | SD_CMD_ERASE_GRP_START 35
#define | SD_CMD_GO_IDLE_STATE 0
Commands: CMDxx = CMD-number | 0x40.
#define | SD_CMD_PROG_CSD 27
#define | SD_CMD_READ_MULT_BLOCK 18
#define | SD_CMD_READ_SINGLE_BLOCK 17
#define | SD_CMD_SD_ERASE_GRP_END 33
#define | SD_CMD_SD_ERASE_GRP_START 32
#define | SD_CMD_SEND_CID 10
#define | SD_CMD_SEND_CSD 9
#define | SD_CMD_SEND_OP_COND 1
#define | SD_CMD_SEND_STATUS 13
#define | SD_CMD_SEND_WRITE_PROT 30
#define | SD_CMD_SET_BLOCK_COUNT 23
#define | SD_CMD_SET_BLOCKLEN 16
#define | SD_CMD_SET_WRITE_PROT 28
#define | SD_CMD_STOP_TRANSMISSION 12
#define | SD_CMD_UNTAG_ERASE_GROUP 37
#define | SD_CMD_UNTAG_SECTOR 34
#define | SD_CMD_WRITE_MULT_BLOCK 25
#define | SD_CMD_WRITE_SINGLE_BLOCK 24
#define | SD_DUMMY_BYTE 0xFF
Dummy byte.
#define | SD_NOT_PRESENT ((uint8_t)0x00)
#define | SD_PRESENT ((uint8_t)0x01)
SD detection on its memory slot.
#define | SD_START_DATA_MULTIPLE_BLOCK_READ 0xFE
#define | SD_START_DATA_MULTIPLE_BLOCK_WRITE 0xFD
#define | SD_START_DATA_SINGLE_BLOCK_READ 0xFE
Start Data tokens: Tokens (necessary because at nop/idle (and CS active) only 0xff is on the data/command line)
#define | SD_START_DATA_SINGLE_BLOCK_WRITE 0xFE
#define | SD_STOP_DATA_MULTIPLE_BLOCK_WRITE 0xFD

Define Documentation

#define SD_BLOCK_SIZE 0x200

Block Size.

Definition at line 161 of file stm32_eval_spi_sd.h.

#define SD_CMD_CLR_WRITE_PROT 29

CMD29 = 0x5D

Definition at line 203 of file stm32_eval_spi_sd.h.

#define SD_CMD_ERASE 38

CMD38 = 0x66

Definition at line 211 of file stm32_eval_spi_sd.h.

#define SD_CMD_ERASE_GRP_END 36

CMD36 = 0x64

Definition at line 209 of file stm32_eval_spi_sd.h.

#define SD_CMD_ERASE_GRP_START 35

CMD35 = 0x63

Definition at line 208 of file stm32_eval_spi_sd.h.

#define SD_CMD_GO_IDLE_STATE 0

Commands: CMDxx = CMD-number | 0x40.

CMD0 = 0x40

Definition at line 189 of file stm32_eval_spi_sd.h.

#define SD_CMD_PROG_CSD 27

CMD27 = 0x5B

Definition at line 201 of file stm32_eval_spi_sd.h.

#define SD_CMD_READ_MULT_BLOCK 18

CMD18 = 0x52

Definition at line 197 of file stm32_eval_spi_sd.h.

#define SD_CMD_READ_SINGLE_BLOCK 17

CMD17 = 0x51

Definition at line 196 of file stm32_eval_spi_sd.h.

#define SD_CMD_SD_ERASE_GRP_END 33

CMD33 = 0x61

Definition at line 206 of file stm32_eval_spi_sd.h.

#define SD_CMD_SD_ERASE_GRP_START 32

CMD32 = 0x60

Definition at line 205 of file stm32_eval_spi_sd.h.

#define SD_CMD_SEND_CID 10

CMD10 = 0x4A

Definition at line 192 of file stm32_eval_spi_sd.h.

#define SD_CMD_SEND_CSD 9

CMD9 = 0x49

Definition at line 191 of file stm32_eval_spi_sd.h.

#define SD_CMD_SEND_OP_COND 1

CMD1 = 0x41

Definition at line 190 of file stm32_eval_spi_sd.h.

#define SD_CMD_SEND_STATUS 13

CMD13 = 0x4D

Definition at line 194 of file stm32_eval_spi_sd.h.

#define SD_CMD_SEND_WRITE_PROT 30

CMD30 = 0x5E

Definition at line 204 of file stm32_eval_spi_sd.h.

#define SD_CMD_SET_BLOCK_COUNT 23

CMD23 = 0x57

Definition at line 198 of file stm32_eval_spi_sd.h.

#define SD_CMD_SET_BLOCKLEN 16

CMD16 = 0x50

Definition at line 195 of file stm32_eval_spi_sd.h.

#define SD_CMD_SET_WRITE_PROT 28

CMD28 = 0x5C

Definition at line 202 of file stm32_eval_spi_sd.h.

#define SD_CMD_STOP_TRANSMISSION 12

CMD12 = 0x4C

Definition at line 193 of file stm32_eval_spi_sd.h.

#define SD_CMD_UNTAG_ERASE_GROUP 37

CMD37 = 0x65

Definition at line 210 of file stm32_eval_spi_sd.h.

#define SD_CMD_UNTAG_SECTOR 34

CMD34 = 0x62

Definition at line 207 of file stm32_eval_spi_sd.h.

#define SD_CMD_WRITE_MULT_BLOCK 25

CMD25 = 0x59

Definition at line 200 of file stm32_eval_spi_sd.h.

#define SD_CMD_WRITE_SINGLE_BLOCK 24

CMD24 = 0x58

Definition at line 199 of file stm32_eval_spi_sd.h.

#define SD_DUMMY_BYTE 0xFF

Dummy byte.

Definition at line 166 of file stm32_eval_spi_sd.h.

Referenced by SD_GetCIDRegister(), SD_GetCSDRegister(), SD_GetStatus(), SD_GoIdleState(), SD_Init(), SD_ReadBlock(), SD_ReadByte(), SD_ReadMultiBlocks(), SD_WriteBlock(), and SD_WriteMultiBlocks().

#define SD_NOT_PRESENT ((uint8_t)0x00)

Definition at line 183 of file stm32_eval_spi_sd.h.

#define SD_PRESENT ((uint8_t)0x01)

SD detection on its memory slot.

Definition at line 182 of file stm32_eval_spi_sd.h.

#define SD_START_DATA_MULTIPLE_BLOCK_READ 0xFE

Data token start byte, Start Multiple Block Read

Definition at line 174 of file stm32_eval_spi_sd.h.

#define SD_START_DATA_MULTIPLE_BLOCK_WRITE 0xFD

Data token start byte, Start Multiple Block Write

Definition at line 176 of file stm32_eval_spi_sd.h.

#define SD_START_DATA_SINGLE_BLOCK_READ 0xFE

Start Data tokens: Tokens (necessary because at nop/idle (and CS active) only 0xff is on the data/command line)

Data token start byte, Start Single Block Read

Definition at line 173 of file stm32_eval_spi_sd.h.

Referenced by SD_GetCIDRegister(), SD_GetCSDRegister(), SD_ReadBlock(), and SD_ReadMultiBlocks().

#define SD_START_DATA_SINGLE_BLOCK_WRITE 0xFE

Data token start byte, Start Single Block Write

Definition at line 175 of file stm32_eval_spi_sd.h.

Referenced by SD_WriteMultiBlocks().

#define SD_STOP_DATA_MULTIPLE_BLOCK_WRITE 0xFD

Data toke stop byte, Stop Multiple Block Write

Definition at line 177 of file stm32_eval_spi_sd.h.


STM32F10x Standard Peripherals Firmware Library: STM32_EVAL_SPI_SD_Exported_Macros

Defines

STM32_EVAL_SPI_SD_Exported_Macros

STM32_EVAL_SPI_SD

Defines

#define | SD_CS_HIGH() GPIO_SetBits(SD_CS_GPIO_PORT, SD_CS_PIN)
Deselect SD Card: ChipSelect pin high.
#define | SD_CS_LOW() GPIO_ResetBits(SD_CS_GPIO_PORT, SD_CS_PIN)
Select SD Card: ChipSelect pin low.

Define Documentation

#define SD_CS_HIGH ( ) GPIO_SetBits(SD_CS_GPIO_PORT, SD_CS_PIN)

Deselect SD Card: ChipSelect pin high.

Definition at line 227 of file stm32_eval_spi_sd.h.

Referenced by SD_GetCIDRegister(), SD_GetCSDRegister(), SD_GetStatus(), SD_GoIdleState(), SD_Init(), SD_ReadBlock(), SD_ReadMultiBlocks(), SD_WriteBlock(), and SD_WriteMultiBlocks().

#define SD_CS_LOW ( ) GPIO_ResetBits(SD_CS_GPIO_PORT, SD_CS_PIN)

Select SD Card: ChipSelect pin low.

Definition at line 223 of file stm32_eval_spi_sd.h.

Referenced by SD_GetCIDRegister(), SD_GetCSDRegister(), SD_GetStatus(), SD_GoIdleState(), SD_ReadBlock(), SD_ReadMultiBlocks(), SD_WriteBlock(), and SD_WriteMultiBlocks().


STM32F10x Standard Peripherals Firmware Library: STM32_EVAL_SPI_SD_Exported_Functions

Functions

STM32_EVAL_SPI_SD_Exported_Functions

STM32_EVAL_SPI_SD

Functions

void | SD_DeInit (void)
DeInitializes the SDIO interface.
uint8_t | SD_Detect (void)
Detect if SD card is correctly plugged in the memory slot.
SD_Error | SD_GetCardInfo (SD_CardInfo *cardinfo)
Returns information about specific card.
SD_Error | SD_GetCIDRegister (SD_CID *SD_cid)
Read the CID card register.
SD_Error | SD_GetCSDRegister (SD_CSD *SD_csd)
Read the CSD card register.
uint8_t | SD_GetDataResponse (void)
Get SD card data response.
SD_Error | SD_GetResponse (uint8_t Response)
Returns the SD response.
uint16_t | SD_GetStatus (void)
Gets the cuurent sd card data transfer status.
SD_Error | SD_GoIdleState (void)
Put SD in Idle state.
SD_Error | SD_Init (void)
Initializes the SD Card and put it into StandBy State (Ready for data transfer).
SD_Error | SD_ReadBlock (uint8_t *pBuffer, uint32_t ReadAddr, uint16_t BlockSize)
Allows to read one block from a specified address in a card.
uint8_t | SD_ReadByte (void)
Read a byte from the SD.
SD_Error | SD_ReadMultiBlocks (uint8_t *pBuffer, uint32_t ReadAddr, uint16_t BlockSize, uint32_t NumberOfBlocks)
Allows to read blocks from a specified address in a card.
void | SD_SendCmd (uint8_t Cmd, uint32_t Arg, uint8_t Crc)
Send 5 bytes command to the SD card.
SD_Error | SD_WriteBlock (uint8_t *pBuffer, uint32_t WriteAddr, uint16_t BlockSize)
Allows to write one block starting from a specified address in a card.
uint8_t | SD_WriteByte (uint8_t byte)
Write a byte on the SD.
SD_Error | SD_WriteMultiBlocks (uint8_t *pBuffer, uint32_t WriteAddr, uint16_t BlockSize, uint32_t NumberOfBlocks)
Allows to write blocks starting from a specified address in a card.

Function Documentation

void SD_DeInit ( void )

DeInitializes the SDIO interface.

Parameters:
None
Return values:
None DeInitializes the SDIO interface.
Parameters:
None
Return values:
None

Definition at line 356 of file stm32_eval_sdio_sd.c.

References SD_LowLevel_DeInit().

uint8_t SD_Detect ( void )

Detect if SD card is correctly plugged in the memory slot.

Parameters:
None
Return values:
Return if SD is detected or not

< Check GPIO to detect SD

< Check GPIO to detect SD

Definition at line 482 of file stm32_eval_sdio_sd.c.

References Bit_RESET, GPIO_ReadInputData(), GPIO_ReadInputDataBit(), SD_DETECT_GPIO_PORT, SD_DETECT_PIN, SD_NOT_PRESENT, SD_PRESENT, and status.

Referenced by main(), and SD_GetState().

SD_Error SD_GetCardInfo ( SD_CardInfo * cardinfo )

Returns information about specific card.

Parameters:
cardinfo,: pointer to a SD_CardInfo structure that contains all SD card information.
Return values:
SD_Error,: SD Card Error code.
Parameters:
cardinfo,: pointer to a SD_CardInfo structure that contains all SD card information.
Return values:
The SD Response:

  • SD_RESPONSE_FAILURE: Sequence failed
  • SD_RESPONSE_NO_ERROR: Sequence succeed

< Byte 0

< Byte 1

< Byte 2

< Byte 3

< Byte 4

< Byte 5

< Byte 6

< Reserved

< Byte 7

< Byte 8

< Byte 9

< Byte 10

< Byte 7

< Byte 8

< Byte 9

< Byte 10

< Byte 11

< Byte 12

< Byte 13

< Byte 14

< Byte 15

< Byte 0

< Byte 1

< Byte 2

< Byte 3

< Byte 4

< Byte 5

< Byte 6

< Byte 7

< Byte 8

< Byte 9

< Byte 10

< Byte 11

< Byte 12

< Byte 13

< Byte 14

< Byte 15

< Returns the reponse

Definition at line 749 of file stm32_eval_sdio_sd.c.

References SD_CardInfo::CardBlockSize, SD_CardInfo::CardCapacity, SD_CSD::CardComdClasses, CardType, SD_CardInfo::CardType, SD_CID::CID_CRC, CID_Tab, SD_CSD::ContentProtectAppli, SD_CSD::CopyFlag, SD_CSD::CSD_CRC, CSD_Tab, SD_CSD::CSDStruct, SD_CSD::DeviceSize, SD_CSD::DeviceSizeMul, SD_CSD::DSRImpl, SD_CSD::ECC, SD_CSD::EraseGrMul, SD_CSD::EraseGrSize, SD_CSD::FileFormat, SD_CSD::FileFormatGrouop, SD_CSD::ManDeflECC, SD_CID::ManufactDate, SD_CID::ManufacturerID, SD_CSD::MaxBusClkFrec, SD_CSD::MaxRdCurrentVDDMax, SD_CSD::MaxRdCurrentVDDMin, SD_CSD::MaxWrBlockLen, SD_CSD::MaxWrCurrentVDDMax, SD_CSD::MaxWrCurrentVDDMin, SD_CSD::NSAC, SD_CID::OEM_AppliID, SD_CSD::PartBlockRead, SD_CSD::PermWrProtect, SD_CID::ProdName1, SD_CID::ProdName2, SD_CID::ProdRev, SD_CID::ProdSN, RCA, SD_CardInfo::RCA, SD_CSD::RdBlockLen, SD_CSD::RdBlockMisalign, SD_CID::Reserved1, SD_CSD::Reserved1, SD_CID::Reserved2, SD_CSD::Reserved2, SD_CSD::Reserved3, SD_CSD::Reserved4, SD_CardInfo::SD_cid, SD_CardInfo::SD_csd, SD_GetCIDRegister(), SD_GetCSDRegister(), SD_OK, SD_RESPONSE_FAILURE, SDIO_HIGH_CAPACITY_SD_CARD, SDIO_STD_CAPACITY_SD_CARD_V1_1, SDIO_STD_CAPACITY_SD_CARD_V2_0, status, SD_CSD::SysSpecVersion, SD_CSD::TAAC, SD_CSD::TempWrProtect, SD_CSD::WrBlockMisalign, SD_CSD::WriteBlockPaPartial, SD_CSD::WrProtectGrEnable, SD_CSD::WrProtectGrSize, and SD_CSD::WrSpeedFact.

Referenced by SD_Init().

SD_Error SD_GetCIDRegister ( SD_CID * SD_cid )

Read the CID card register.

Reading the contents of the CID register in SPI mode is a simple read-block transaction.

Parameters:
SD_cid,: pointer on an CID register structure
Return values:
The SD Response:

  • SD_RESPONSE_FAILURE: Sequence failed
  • SD_RESPONSE_NO_ERROR: Sequence succeed

< SD chip select low

< Send CMD10 (CID register)

< Wait for response in the R1 format (0x00 is no errors)

< Store CID register value on CID_Tab

< Set response value to success

< Send dummy byte: 8 Clock pulses of delay

< Byte 0

< Byte 1

< Byte 2

< Byte 3

< Byte 4

< Byte 5

< Byte 6

< Byte 7

< Byte 8

< Byte 9

< Byte 10

< Byte 11

< Byte 12

< Byte 13

< Byte 14

< Byte 15

< Return the reponse

Definition at line 555 of file stm32_eval_spi_sd.c.

References SD_CID::CID_CRC, CID_Tab, SD_CID::ManufactDate, SD_CID::ManufacturerID, SD_CID::OEM_AppliID, SD_CID::ProdName1, SD_CID::ProdName2, SD_CID::ProdRev, SD_CID::ProdSN, SD_CID::Reserved1, SD_CID::Reserved2, SD_CMD_SEND_CID, SD_CS_HIGH, SD_CS_LOW, SD_DUMMY_BYTE, SD_GetResponse(), SD_ReadByte(), SD_RESPONSE_FAILURE, SD_RESPONSE_NO_ERROR, SD_SendCmd(), SD_START_DATA_SINGLE_BLOCK_READ, and SD_WriteByte().

Referenced by SD_GetCardInfo().

SD_Error SD_GetCSDRegister ( SD_CSD * SD_csd )

Read the CSD card register.

Reading the contents of the CSD register in SPI mode is a simple read-block transaction.

Parameters:
SD_csd,: pointer on an SCD register structure
Return values:
The SD Response:

  • SD_RESPONSE_FAILURE: Sequence failed
  • SD_RESPONSE_NO_ERROR: Sequence succeed

< SD chip select low

< Send CMD9 (CSD register) or CMD10(CSD register)

< Wait for response in the R1 format (0x00 is no errors)

< Store CSD register value on CSD_Tab

< Set response value to success

< Send dummy byte: 8 Clock pulses of delay

< Byte 0

< Byte 1

< Byte 2

< Byte 3

< Byte 4

< Byte 5

< Byte 6

< Reserved

< Byte 7

< Byte 8

< Byte 9

< Byte 10

< Byte 11

< Byte 12

< Byte 13

< Byte 14

< Byte 15

< Return the reponse

Definition at line 433 of file stm32_eval_spi_sd.c.

References SD_CSD::CardComdClasses, SD_CSD::ContentProtectAppli, SD_CSD::CopyFlag, SD_CSD::CSD_CRC, CSD_Tab, SD_CSD::CSDStruct, SD_CSD::DeviceSize, SD_CSD::DeviceSizeMul, SD_CSD::DSRImpl, SD_CSD::ECC, SD_CSD::EraseGrMul, SD_CSD::EraseGrSize, SD_CSD::FileFormat, SD_CSD::FileFormatGrouop, SD_CSD::ManDeflECC, SD_CSD::MaxBusClkFrec, SD_CSD::MaxRdCurrentVDDMax, SD_CSD::MaxRdCurrentVDDMin, SD_CSD::MaxWrBlockLen, SD_CSD::MaxWrCurrentVDDMax, SD_CSD::MaxWrCurrentVDDMin, SD_CSD::NSAC, SD_CSD::PartBlockRead, SD_CSD::PermWrProtect, SD_CSD::RdBlockLen, SD_CSD::RdBlockMisalign, SD_CSD::Reserved1, SD_CSD::Reserved2, SD_CSD::Reserved3, SD_CSD::Reserved4, SD_CMD_SEND_CSD, SD_CS_HIGH, SD_CS_LOW, SD_DUMMY_BYTE, SD_GetResponse(), SD_ReadByte(), SD_RESPONSE_FAILURE, SD_RESPONSE_NO_ERROR, SD_SendCmd(), SD_START_DATA_SINGLE_BLOCK_READ, SD_WriteByte(), SD_CSD::SysSpecVersion, SD_CSD::TAAC, SD_CSD::TempWrProtect, SD_CSD::WrBlockMisalign, SD_CSD::WriteBlockPaPartial, SD_CSD::WrProtectGrEnable, SD_CSD::WrProtectGrSize, and SD_CSD::WrSpeedFact.

Referenced by SD_GetCardInfo().

uint8_t SD_GetDataResponse ( void )

Get SD card data response.

Parameters:
None
Return values:
The SD status: Read data response xxx0<status>1

  • status 010: Data accecpted
  • status 101: Data rejected due to a crc error
  • status 110: Data rejected due to a Write error.
  • status 111: Data rejected due to other error.

< Read resonse

< Mask unused bits

< Increment loop counter

< Return response

Definition at line 683 of file stm32_eval_spi_sd.c.

References SD_DATA_CRC_ERROR, SD_DATA_OK, SD_DATA_OTHER_ERROR, SD_DATA_WRITE_ERROR, and SD_ReadByte().

Referenced by SD_WriteBlock(), and SD_WriteMultiBlocks().

SD_Error SD_GetResponse ( uint8_t Response )

Returns the SD response.

Parameters:
None
Return values:
The SD Response:

  • SD_RESPONSE_FAILURE: Sequence failed
  • SD_RESPONSE_NO_ERROR: Sequence succeed

< Check if response is got or a timeout is happen

< After time out

< Right response got

Definition at line 732 of file stm32_eval_spi_sd.c.

References SD_ReadByte(), SD_RESPONSE_FAILURE, and SD_RESPONSE_NO_ERROR.

Referenced by SD_GetCIDRegister(), SD_GetCSDRegister(), SD_GoIdleState(), SD_ReadBlock(), SD_ReadMultiBlocks(), SD_WriteBlock(), and SD_WriteMultiBlocks().

uint16_t SD_GetStatus ( void )

Gets the cuurent sd card data transfer status.

Parameters:
None
Return values:
SDTransferState,: Data Transfer state. This value can be:

  • SD_TRANSFER_OK: No data transfer is acting
  • SD_TRANSFER_BUSY: Data transfer is acting

Gets the cuurent sd card data transfer status.

Parameters:
None
Return values:
The SD status.

< SD chip select low

< Send CMD13 (SD_SEND_STATUS) to get SD status

< SD chip select high

< Send dummy byte 0xFF

Definition at line 431 of file stm32_eval_sdio_sd.c.

References SD_CARD_ERROR, SD_CARD_TRANSFER, SD_CMD_SEND_STATUS, SD_CS_HIGH, SD_CS_LOW, SD_DUMMY_BYTE, SD_GetState(), SD_ReadByte(), SD_SendCmd(), SD_TRANSFER_BUSY, SD_TRANSFER_ERROR, SD_TRANSFER_OK, SD_WriteByte(), and Status.

Referenced by SD_EraseTest(), SD_MultiBlockTest(), and SD_SingleBlockTest().

SD_Error SD_GoIdleState ( void )

Put SD in Idle state.

Parameters:
None
Return values:
The SD Response:

  • SD_RESPONSE_FAILURE: Sequence failed
  • SD_RESPONSE_NO_ERROR: Sequence succeed

< SD chip select low

< Send CMD0 (SD_CMD_GO_IDLE_STATE) to put SD in SPI mode

< Wait for In Idle State Response (R1 Format) equal to 0x01

< No Idle State Response: return response failue

< SD chip select high

< Send Dummy byte 0xFF

< SD chip select low

< Send CMD1 (Activates the card process) until response equal to 0x0

< Wait for no error Response (R1 Format) equal to 0x00

< SD chip select high

< Send dummy byte 0xFF

Definition at line 787 of file stm32_eval_spi_sd.c.

References SD_CMD_GO_IDLE_STATE, SD_CMD_SEND_OP_COND, SD_CS_HIGH, SD_CS_LOW, SD_DUMMY_BYTE, SD_GetResponse(), SD_IN_IDLE_STATE, SD_RESPONSE_FAILURE, SD_RESPONSE_NO_ERROR, SD_SendCmd(), and SD_WriteByte().

Referenced by SD_Init().

SD_Error SD_Init ( void )

Initializes the SD Card and put it into StandBy State (Ready for data transfer).

Parameters:
None
Return values:
SD_Error,: SD Card Error code.

Initializes the SD Card and put it into StandBy State (Ready for data transfer).

Parameters:
None
Return values:
The SD Response:

  • SD_RESPONSE_FAILURE: Sequence failed
  • SD_RESPONSE_NO_ERROR: Sequence succeed

< CMD Response TimeOut (wait for CMDSENT flag)

< CMD Response TimeOut (wait for CMDSENT flag)

< SDIOCLK = HCLK, SDIO_CK = HCLK/(2 + SDIO_TRANSFER_CLK_DIV)

< on STM32F2xx devices, SDIOCLK is fixed to 48MHz

< Initialize SD_SPI

< SD chip select high

< Send dummy byte 0xFF, 10 times with CS high

< Rise CS and MOSI for 80 clocks cycles

< Send dummy byte 0xFF

< SD initialized and set to SPI mode properly

Definition at line 367 of file stm32_eval_sdio_sd.c.

References SD_CardInfo::RCA, SD_CS_HIGH, SD_DUMMY_BYTE, SD_EnableWideBusOperation(), SD_GetCardInfo(), SD_GoIdleState(), SD_InitializeCards(), SD_LowLevel_Init(), SD_OK, SD_PowerON(), SD_SelectDeselect(), SD_WriteByte(), SDIO_InitTypeDef::SDIO_BusWide, SDIO_BusWide_1b, SDIO_BusWide_4b, SDIO_InitTypeDef::SDIO_ClockBypass, SDIO_ClockBypass_Disable, SDIO_InitTypeDef::SDIO_ClockDiv, SDIO_InitTypeDef::SDIO_ClockEdge, SDIO_ClockEdge_Rising, SDIO_InitTypeDef::SDIO_ClockPowerSave, SDIO_ClockPowerSave_Disable, SDIO_DeInit(), SDIO_InitTypeDef::SDIO_HardwareFlowControl, SDIO_HardwareFlowControl_Disable, SDIO_Init(), and SDIO_TRANSFER_CLK_DIV.

Referenced by main().

SD_Error SD_ReadBlock | ( | uint8_t * | pBuffer,
 |  | uint32_t | ReadAddr,
 |  | uint16_t | BlockSize
 | ) |  |

Allows to read one block from a specified address in a card.

The Data transfer can be managed by DMA mode or Polling mode.

Note:
This operation should be followed by two functions to check if the DMA Controller and SD Card status.
  • SD_ReadWaitOperation(): this function insure that the DMA controller has finished all data transfer.
  • SD_GetStatus(): to check that the SD Card has finished the data transfer and it is ready for data.
Parameters:
readbuff,: pointer to the buffer that will contain the received data
ReadAddr,: Address from where data are to be read.
BlockSize,: the SD card Data block size. The Block size should be 512.
Return values:
SD_Error,: SD Card Error code.

Allows to read one block from a specified address in a card.

Parameters:
pBuffer,: pointer to the buffer that receives the data read from the SD.
ReadAddr,: SD's internal address to read from.
BlockSize,: the SD card Data block size.
Return values:
The SD Response:

  • SD_RESPONSE_FAILURE: Sequence failed
  • SD_RESPONSE_NO_ERROR: Sequence succeed

< Send CMD17 READ_SINGLE_BLOCK

< SD chip select low

< Send CMD17 (SD_CMD_READ_SINGLE_BLOCK) to read one block

< Check if the SD acknowledged the read block command: R1 response (0x00: no errors)

< Now look for the data token to signify the start of the data

< Read the SD block data : read NumByteToRead data

< Save the received data

< Point to the next location where the byte read will be saved

< Set response value to success

< Send dummy byte: 8 Clock pulses of delay

< Returns the reponse

Definition at line 1136 of file stm32_eval_sdio_sd.c.

References CardType, CmdResp1Error(), ENABLE, RESET, SD_CMD_READ_SINGLE_BLOCK, SD_CS_HIGH, SD_CS_LOW, SD_DATA_CRC_FAIL, SD_DATA_TIMEOUT, SD_DATATIMEOUT, SD_DUMMY_BYTE, SD_GetResponse(), SD_LowLevel_DMA_RxConfig(), SD_OK, SD_ReadByte(), SD_RESPONSE_FAILURE, SD_RESPONSE_NO_ERROR, SD_RX_OVERRUN, SD_SendCmd(), SD_START_BIT_ERR, SD_START_DATA_SINGLE_BLOCK_READ, SD_WriteByte(), SDIO, SDIO_CmdInitTypeDef::SDIO_Argument, SDIO_ClearFlag(), SDIO_CmdInitTypeDef::SDIO_CmdIndex, SDIO_CmdInitTypeDef::SDIO_CPSM, SDIO_CPSM_Enable, SDIO_DataInitTypeDef::SDIO_DataBlockSize, SDIO_DataConfig(), SDIO_DataInitTypeDef::SDIO_DataLength, SDIO_DataInitTypeDef::SDIO_DataTimeOut, SDIO_DMACmd(), SDIO_DataInitTypeDef::SDIO_DPSM, SDIO_DPSM_Enable, SDIO_FLAG_DBCKEND, SDIO_FLAG_DCRCFAIL, SDIO_FLAG_DTIMEOUT, SDIO_FLAG_RXDAVL, SDIO_FLAG_RXFIFOHF, SDIO_FLAG_RXOVERR, SDIO_FLAG_STBITERR, SDIO_GetFlagStatus(), SDIO_HIGH_CAPACITY_SD_CARD, SDIO_IT_DATAEND, SDIO_ITConfig(), SDIO_ReadData(), SDIO_CmdInitTypeDef::SDIO_Response, SDIO_Response_Short, SDIO_SendCommand(), SDIO_STATIC_FLAGS, SDIO_DataInitTypeDef::SDIO_TransferDir, SDIO_TransferDir_ToSDIO, SDIO_DataInitTypeDef::SDIO_TransferMode, SDIO_TransferMode_Block, SDIO_CmdInitTypeDef::SDIO_Wait, SDIO_Wait_No, StopCondition, TransferEnd, and TransferError.

Referenced by SD_SingleBlockTest().

uint8_t SD_ReadByte ( void )

Read a byte from the SD.

Parameters:
None
Return values:
The received byte.

< Wait until the transmit buffer is empty

< Wait until a data is received

< Return the shifted data

Definition at line 857 of file stm32_eval_spi_sd.c.

References Data, RESET, SD_DUMMY_BYTE, SD_SPI, SPI_I2S_FLAG_RXNE, SPI_I2S_FLAG_TXE, SPI_I2S_GetFlagStatus(), SPI_I2S_ReceiveData(), and SPI_I2S_SendData().

Referenced by SD_GetCIDRegister(), SD_GetCSDRegister(), SD_GetDataResponse(), SD_GetResponse(), SD_GetStatus(), SD_ReadBlock(), SD_ReadMultiBlocks(), SD_WriteBlock(), and SD_WriteMultiBlocks().

SD_Error SD_ReadMultiBlocks | ( | uint8_t * | pBuffer,
 |  | uint32_t | ReadAddr,
 |  | uint16_t | BlockSize,
 |  | uint32_t | NumberOfBlocks
 | ) |  |

Allows to read blocks from a specified address in a card.

The Data transfer can be managed by DMA mode or Polling mode.

Note:
This operation should be followed by two functions to check if the DMA Controller and SD Card status.
  • SD_ReadWaitOperation(): this function insure that the DMA controller has finished all data transfer.
  • SD_GetStatus(): to check that the SD Card has finished the data transfer and it is ready for data.
Parameters:
readbuff,: pointer to the buffer that will contain the received data.
ReadAddr,: Address from where data are to be read.
BlockSize,: the SD card Data block size. The Block size should be 512.
NumberOfBlocks,: number of blocks to be read.
Return values:
SD_Error,: SD Card Error code.

Allows to read blocks from a specified address in a card.

Parameters:
pBuffer,: pointer to the buffer that receives the data read from the SD.
ReadAddr,: SD's internal address to read from.
BlockSize,: the SD card Data block size.
NumberOfBlocks,: number of blocks to be read.
Return values:
The SD Response:

  • SD_RESPONSE_FAILURE: Sequence failed
  • SD_RESPONSE_NO_ERROR: Sequence succeed

< Send CMD18 READ_MULT_BLOCK with argument data address

< SD chip select low

< Data transfer

< Send CMD17 (SD_CMD_READ_SINGLE_BLOCK) to read one block

< Check if the SD acknowledged the read block command: R1 response (0x00: no errors)

< Read the SD block data : read NumByteToRead data

< Read the pointed data

< Point to the next location where the byte read will be saved

< get CRC bytes (not really needed by us, but required by SD)

< Set response value to success

< Set response value to failure

< Send dummy byte: 8 Clock pulses of delay

< Returns the reponse

Definition at line 1251 of file stm32_eval_sdio_sd.c.

References CardType, CmdResp1Error(), ENABLE, SD_CMD_READ_MULT_BLOCK, SD_CMD_READ_SINGLE_BLOCK, SD_CMD_SET_BLOCKLEN, SD_CS_HIGH, SD_CS_LOW, SD_DATATIMEOUT, SD_DUMMY_BYTE, SD_GetResponse(), SD_LowLevel_DMA_RxConfig(), SD_OK, SD_ReadByte(), SD_RESPONSE_FAILURE, SD_RESPONSE_NO_ERROR, SD_SendCmd(), SD_START_DATA_SINGLE_BLOCK_READ, SD_WriteByte(), SDIO, SDIO_CmdInitTypeDef::SDIO_Argument, SDIO_CmdInitTypeDef::SDIO_CmdIndex, SDIO_CmdInitTypeDef::SDIO_CPSM, SDIO_CPSM_Enable, SDIO_DataInitTypeDef::SDIO_DataBlockSize, SDIO_DataConfig(), SDIO_DataInitTypeDef::SDIO_DataLength, SDIO_DataInitTypeDef::SDIO_DataTimeOut, SDIO_DMACmd(), SDIO_DataInitTypeDef::SDIO_DPSM, SDIO_DPSM_Enable, SDIO_HIGH_CAPACITY_SD_CARD, SDIO_IT_DATAEND, SDIO_ITConfig(), SDIO_CmdInitTypeDef::SDIO_Response, SDIO_Response_Short, SDIO_SendCommand(), SDIO_DataInitTypeDef::SDIO_TransferDir, SDIO_TransferDir_ToSDIO, SDIO_DataInitTypeDef::SDIO_TransferMode, SDIO_TransferMode_Block, SDIO_CmdInitTypeDef::SDIO_Wait, SDIO_Wait_No, StopCondition, TransferEnd, and TransferError.

Referenced by SD_EraseTest(), and SD_MultiBlockTest().

void SD_SendCmd | ( | uint8_t | Cmd,
 |  | uint32_t | Arg,
 |  | uint8_t | Crc
 | ) |  |

Send 5 bytes command to the SD card.

Parameters:
Cmd,: The user expected command to send to SD card.
Arg,: The command argument.
Crc,: The CRC.
Return values:
None

< Construct byte 1

< Construct byte 2

< Construct byte 3

< Construct byte 4

< Construct byte 5

< Construct CRC: byte 6

< Send the Cmd bytes

Definition at line 650 of file stm32_eval_spi_sd.c.

References SD_WriteByte().

Referenced by SD_GetCIDRegister(), SD_GetCSDRegister(), SD_GetStatus(), SD_GoIdleState(), SD_ReadBlock(), SD_ReadMultiBlocks(), SD_WriteBlock(), and SD_WriteMultiBlocks().

SD_Error SD_WriteBlock | ( | uint8_t * | pBuffer,
 |  | uint32_t | WriteAddr,
 |  | uint16_t | BlockSize
 | ) |  |

Allows to write one block starting from a specified address in a card.

The Data transfer can be managed by DMA mode or Polling mode.

Note:
This operation should be followed by two functions to check if the DMA Controller and SD Card status.
  • SD_ReadWaitOperation(): this function insure that the DMA controller has finished all data transfer.
  • SD_GetStatus(): to check that the SD Card has finished the data transfer and it is ready for data.
Parameters:
writebuff,: pointer to the buffer that contain the data to be transferred.
WriteAddr,: Address from where data are to be read.
BlockSize,: the SD card Data block size. The Block size should be 512.
Return values:
SD_Error,: SD Card Error code.

Allows to write one block starting from a specified address in a card.

Parameters:
pBuffer,: pointer to the buffer containing the data to be written on the SD.
WriteAddr,: address to write on.
BlockSize,: the SD card Data block size.
Return values:
The SD Response:

  • SD_RESPONSE_FAILURE: Sequence failed
  • SD_RESPONSE_NO_ERROR: Sequence succeed

< In case of single data block transfer no need of stop command at all

< SD chip select low

< Send CMD24 (SD_CMD_WRITE_SINGLE_BLOCK) to write multiple block

< Check if the SD acknowledged the write block command: R1 response (0x00: no errors)

< Send a dummy byte

< Send the data token to signify the start of the data

< Write the block data to SD : write count data by block

< Send the pointed byte

< Point to the next location where the byte read will be saved

< Read data response

< Send dummy byte: 8 Clock pulses of delay

< Returns the reponse

Definition at line 1348 of file stm32_eval_sdio_sd.c.

References CardType, CmdResp1Error(), ENABLE, RESET, SD_CMD_WRITE_SINGLE_BLOCK, SD_CS_HIGH, SD_CS_LOW, SD_DATA_CRC_FAIL, SD_DATA_OK, SD_DATA_TIMEOUT, SD_DATATIMEOUT, SD_DUMMY_BYTE, SD_GetDataResponse(), SD_GetResponse(), SD_LowLevel_DMA_TxConfig(), SD_OK, SD_ReadByte(), SD_RESPONSE_FAILURE, SD_RESPONSE_NO_ERROR, SD_SendCmd(), SD_START_BIT_ERR, SD_TX_UNDERRUN, SD_WriteByte(), SDIO, SDIO_CmdInitTypeDef::SDIO_Argument, SDIO_ClearFlag(), SDIO_CmdInitTypeDef::SDIO_CmdIndex, SDIO_CmdInitTypeDef::SDIO_CPSM, SDIO_CPSM_Enable, SDIO_DataInitTypeDef::SDIO_DataBlockSize, SDIO_DataConfig(), SDIO_DataInitTypeDef::SDIO_DataLength, SDIO_DataInitTypeDef::SDIO_DataTimeOut, SDIO_DMACmd(), SDIO_DataInitTypeDef::SDIO_DPSM, SDIO_DPSM_Enable, SDIO_FLAG_DBCKEND, SDIO_FLAG_DCRCFAIL, SDIO_FLAG_DTIMEOUT, SDIO_FLAG_STBITERR, SDIO_FLAG_TXFIFOHE, SDIO_FLAG_TXUNDERR, SDIO_GetFlagStatus(), SDIO_HIGH_CAPACITY_SD_CARD, SDIO_IT_DATAEND, SDIO_ITConfig(), SDIO_CmdInitTypeDef::SDIO_Response, SDIO_Response_Short, SDIO_SendCommand(), SDIO_DataInitTypeDef::SDIO_TransferDir, SDIO_TransferDir_ToCard, SDIO_DataInitTypeDef::SDIO_TransferMode, SDIO_TransferMode_Block, SDIO_CmdInitTypeDef::SDIO_Wait, SDIO_Wait_No, SDIO_WriteData(), StopCondition, TransferEnd, and TransferError.

Referenced by SD_SingleBlockTest().

uint8_t SD_WriteByte ( uint8_t Data )

Write a byte on the SD.

Parameters:
Data,: byte to send.
Return values:
None

< Wait until the transmit buffer is empty

< Wait to receive a byte

Definition at line 833 of file stm32_eval_spi_sd.c.

References RESET, SD_SPI, SPI_I2S_FLAG_RXNE, SPI_I2S_FLAG_TXE, SPI_I2S_GetFlagStatus(), SPI_I2S_ReceiveData(), and SPI_I2S_SendData().

Referenced by SD_GetCIDRegister(), SD_GetCSDRegister(), SD_GetStatus(), SD_GoIdleState(), SD_Init(), SD_ReadBlock(), SD_ReadMultiBlocks(), SD_SendCmd(), SD_WriteBlock(), and SD_WriteMultiBlocks().

SD_Error SD_WriteMultiBlocks | ( | uint8_t * | pBuffer,
 |  | uint32_t | WriteAddr,
 |  | uint16_t | BlockSize,
 |  | uint32_t | NumberOfBlocks
 | ) |  |

Allows to write blocks starting from a specified address in a card.

The Data transfer can be managed by DMA mode only.

Note:
This operation should be followed by two functions to check if the DMA Controller and SD Card status.
  • SD_ReadWaitOperation(): this function insure that the DMA controller has finished all data transfer.
  • SD_GetStatus(): to check that the SD Card has finished the data transfer and it is ready for data.
Parameters:
WriteAddr,: Address from where data are to be read.
writebuff,: pointer to the buffer that contain the data to be transferred.
BlockSize,: the SD card Data block size. The Block size should be 512.
NumberOfBlocks,: number of blocks to be written.
Return values:
SD_Error,: SD Card Error code.

Allows to write blocks starting from a specified address in a card.

Parameters:
pBuffer,: pointer to the buffer containing the data to be written on the SD.
WriteAddr,: address to write on.
BlockSize,: the SD card Data block size.
NumberOfBlocks,: number of blocks to be written.
Return values:
The SD Response:

  • SD_RESPONSE_FAILURE: Sequence failed
  • SD_RESPONSE_NO_ERROR: Sequence succeed

< SD chip select low

< Data transfer

< Send CMD24 (SD_CMD_WRITE_SINGLE_BLOCK) to write blocks

< Check if the SD acknowledged the write block command: R1 response (0x00: no errors)

< Send the data token to signify the start of the data

< Write the block data to SD : write count data by block

< Send the pointed byte

< Point to the next location where the byte read will be saved

< Put CRC bytes (not really needed by us, but required by SD)

< Read data response

< Set response value to success

< Set response value to failure

< Send dummy byte: 8 Clock pulses of delay

< Returns the reponse

Definition at line 1466 of file stm32_eval_sdio_sd.c.

References CardType, CmdResp1Error(), ENABLE, RCA, SD_CMD_APP_CMD, SD_CMD_SET_BLOCK_COUNT, SD_CMD_WRITE_MULT_BLOCK, SD_CMD_WRITE_SINGLE_BLOCK, SD_CS_HIGH, SD_CS_LOW, SD_DATA_OK, SD_DATATIMEOUT, SD_DUMMY_BYTE, SD_GetDataResponse(), SD_GetResponse(), SD_LowLevel_DMA_TxConfig(), SD_OK, SD_ReadByte(), SD_RESPONSE_FAILURE, SD_RESPONSE_NO_ERROR, SD_SendCmd(), SD_START_DATA_SINGLE_BLOCK_WRITE, SD_WriteByte(), SDIO, SDIO_CmdInitTypeDef::SDIO_Argument, SDIO_CmdInitTypeDef::SDIO_CmdIndex, SDIO_CmdInitTypeDef::SDIO_CPSM, SDIO_CPSM_Enable, SDIO_DataInitTypeDef::SDIO_DataBlockSize, SDIO_DataConfig(), SDIO_DataInitTypeDef::SDIO_DataLength, SDIO_DataInitTypeDef::SDIO_DataTimeOut, SDIO_DMACmd(), SDIO_DataInitTypeDef::SDIO_DPSM, SDIO_DPSM_Enable, SDIO_HIGH_CAPACITY_SD_CARD, SDIO_IT_DATAEND, SDIO_ITConfig(), SDIO_CmdInitTypeDef::SDIO_Response, SDIO_Response_Short, SDIO_SendCommand(), SDIO_DataInitTypeDef::SDIO_TransferDir, SDIO_TransferDir_ToCard, SDIO_DataInitTypeDef::SDIO_TransferMode, SDIO_TransferMode_Block, SDIO_CmdInitTypeDef::SDIO_Wait, SDIO_Wait_No, StopCondition, TransferEnd, and TransferError.

Referenced by SD_MultiBlockTest().


STM32F10x Standard Peripherals Firmware Library: STM32100B_EVAL_LOW_LEVEL_Private_TypesDefinitions

STM32100B_EVAL_LOW_LEVEL_Private_TypesDefinitions

STM32100B_EVAL_LOW_LEVEL


STM32F10x Standard Peripherals Firmware Library: STM32100B_EVAL_LOW_LEVEL_Private_Defines

STM32100B_EVAL_LOW_LEVEL_Private_Defines

STM32100B_EVAL_LOW_LEVEL


STM32F10x Standard Peripherals Firmware Library: STM32100B_EVAL_LOW_LEVEL_Private_Macros

STM32100B_EVAL_LOW_LEVEL_Private_Macros

STM32100B_EVAL_LOW_LEVEL


STM32F10x Standard Peripherals Firmware Library: STM32100B_EVAL_LOW_LEVEL_Private_Variables

Variables

STM32100B_EVAL_LOW_LEVEL_Private_Variables

STM32100B_EVAL_LOW_LEVEL

Variables

const uint32_t | BUTTON_CLK [BUTTONn]
const uint16_t | BUTTON_EXTI_LINE [BUTTONn]
const uint16_t | BUTTON_IRQn [BUTTONn]
const uint16_t | BUTTON_PIN [BUTTONn]
const uint16_t | BUTTON_PIN_SOURCE [BUTTONn]
GPIO_TypeDef * | BUTTON_PORT [BUTTONn]
const uint16_t | BUTTON_PORT_SOURCE [BUTTONn]
const uint16_t | COM_RX_PIN [COMn] = {EVAL_COM1_RX_PIN, EVAL_COM2_RX_PIN}
GPIO_TypeDef * | COM_RX_PORT [COMn] = {EVAL_COM1_RX_GPIO_PORT, EVAL_COM2_RX_GPIO_PORT}
const uint32_t | COM_RX_PORT_CLK [COMn] = {EVAL_COM1_RX_GPIO_CLK, EVAL_COM2_RX_GPIO_CLK}
const uint16_t | COM_TX_PIN [COMn] = {EVAL_COM1_TX_PIN, EVAL_COM2_TX_PIN}
GPIO_TypeDef * | COM_TX_PORT [COMn] = {EVAL_COM1_TX_GPIO_PORT, EVAL_COM2_TX_GPIO_PORT}
const uint32_t | COM_TX_PORT_CLK [COMn] = {EVAL_COM1_TX_GPIO_CLK, EVAL_COM2_TX_GPIO_CLK}
USART_TypeDef * | COM_USART [COMn] = {EVAL_COM1, EVAL_COM2}
const uint32_t | COM_USART_CLK [COMn] = {EVAL_COM1_CLK, EVAL_COM2_CLK}
const uint32_t | GPIO_CLK [LEDn]
const uint16_t | GPIO_PIN [LEDn]
GPIO_TypeDef * | GPIO_PORT [LEDn]

Variable Documentation

const uint32_t BUTTON_CLK[BUTTONn]
Initial value:
 {WAKEUP_BUTTON_GPIO_CLK, TAMPER_BUTTON_GPIO_CLK,
                                      KEY_BUTTON_GPIO_CLK, RIGHT_BUTTON_GPIO_CLK,
                                      LEFT_BUTTON_GPIO_CLK, UP_BUTTON_GPIO_CLK,
                                      DOWN_BUTTON_GPIO_CLK, SEL_BUTTON_GPIO_CLK}

Definition at line 95 of file stm32100b_eval.c.

Referenced by STM_EVAL_PBInit().

const uint16_t BUTTON_EXTI_LINE[BUTTONn]
Initial value:
 {WAKEUP_BUTTON_EXTI_LINE,
                                            TAMPER_BUTTON_EXTI_LINE,
                                            KEY_BUTTON_EXTI_LINE,
                                            RIGHT_BUTTON_EXTI_LINE,
                                            LEFT_BUTTON_EXTI_LINE,
                                            UP_BUTTON_EXTI_LINE,
                                            DOWN_BUTTON_EXTI_LINE,
                                            SEL_BUTTON_EXTI_LINE}

Definition at line 100 of file stm32100b_eval.c.

Referenced by STM_EVAL_PBInit().

const uint16_t BUTTON_IRQn[BUTTONn]
Initial value:
 {WAKEUP_BUTTON_EXTI_IRQn, TAMPER_BUTTON_EXTI_IRQn,
                                       KEY_BUTTON_EXTI_IRQn, RIGHT_BUTTON_EXTI_IRQn,
                                       LEFT_BUTTON_EXTI_IRQn, UP_BUTTON_EXTI_IRQn,
                                       DOWN_BUTTON_EXTI_IRQn, SEL_BUTTON_EXTI_IRQn}

Definition at line 127 of file stm32100b_eval.c.

Referenced by STM_EVAL_PBInit().

const uint16_t BUTTON_PIN[BUTTONn]
Initial value:
 {WAKEUP_BUTTON_PIN, TAMPER_BUTTON_PIN,
                                      KEY_BUTTON_PIN, RIGHT_BUTTON_PIN,
                                      LEFT_BUTTON_PIN, UP_BUTTON_PIN,
                                      DOWN_BUTTON_PIN, SEL_BUTTON_PIN}

Definition at line 90 of file stm32100b_eval.c.

Referenced by STM_EVAL_PBGetState(), and STM_EVAL_PBInit().

const uint16_t BUTTON_PIN_SOURCE[BUTTONn]
Initial value:
 {WAKEUP_BUTTON_EXTI_PIN_SOURCE,
                                             TAMPER_BUTTON_EXTI_PIN_SOURCE,
                                             KEY_BUTTON_EXTI_PIN_SOURCE,
                                             RIGHT_BUTTON_EXTI_PIN_SOURCE,
                                             LEFT_BUTTON_EXTI_PIN_SOURCE,
                                             UP_BUTTON_EXTI_PIN_SOURCE,
                                             DOWN_BUTTON_EXTI_PIN_SOURCE,
                                             SEL_BUTTON_EXTI_PIN_SOURCE}

Definition at line 118 of file stm32100b_eval.c.

Referenced by STM_EVAL_PBInit().

GPIO_TypeDef* BUTTON_PORT[BUTTONn]
Initial value:
 {WAKEUP_BUTTON_GPIO_PORT, TAMPER_BUTTON_GPIO_PORT,
                                      KEY_BUTTON_GPIO_PORT, RIGHT_BUTTON_GPIO_PORT,
                                      LEFT_BUTTON_GPIO_PORT, UP_BUTTON_GPIO_PORT,
                                      DOWN_BUTTON_GPIO_PORT, SEL_BUTTON_GPIO_PORT}

Definition at line 85 of file stm32100b_eval.c.

const uint16_t BUTTON_PORT_SOURCE[BUTTONn]
Initial value:
 {WAKEUP_BUTTON_EXTI_PORT_SOURCE,
                                              TAMPER_BUTTON_EXTI_PORT_SOURCE,
                                              KEY_BUTTON_EXTI_PORT_SOURCE,
                                              RIGHT_BUTTON_EXTI_PORT_SOURCE,
                                              LEFT_BUTTON_EXTI_PORT_SOURCE,
                                              UP_BUTTON_EXTI_PORT_SOURCE,
                                              DOWN_BUTTON_EXTI_PORT_SOURCE,
                                              SEL_BUTTON_EXTI_PORT_SOURCE}

Definition at line 109 of file stm32100b_eval.c.

Referenced by STM_EVAL_PBInit().

const uint16_t COM_RX_PIN[COMn] = {EVAL_COM1_RX_PIN, EVAL_COM2_RX_PIN}

Definition at line 146 of file stm32100b_eval.c.

Referenced by STM_EVAL_COMInit().

GPIO_TypeDef* COM_RX_PORT[COMn] = {EVAL_COM1_RX_GPIO_PORT, EVAL_COM2_RX_GPIO_PORT}

Definition at line 136 of file stm32100b_eval.c.

const uint32_t COM_RX_PORT_CLK[COMn] = {EVAL_COM1_RX_GPIO_CLK, EVAL_COM2_RX_GPIO_CLK}

Definition at line 142 of file stm32100b_eval.c.

Referenced by STM_EVAL_COMInit().

const uint16_t COM_TX_PIN[COMn] = {EVAL_COM1_TX_PIN, EVAL_COM2_TX_PIN}

Definition at line 144 of file stm32100b_eval.c.

Referenced by STM_EVAL_COMInit().

GPIO_TypeDef* COM_TX_PORT[COMn] = {EVAL_COM1_TX_GPIO_PORT, EVAL_COM2_TX_GPIO_PORT}

Definition at line 134 of file stm32100b_eval.c.

const uint32_t COM_TX_PORT_CLK[COMn] = {EVAL_COM1_TX_GPIO_CLK, EVAL_COM2_TX_GPIO_CLK}

Definition at line 140 of file stm32100b_eval.c.

Referenced by STM_EVAL_COMInit().

USART_TypeDef* COM_USART[COMn] = {EVAL_COM1, EVAL_COM2}

Definition at line 132 of file stm32100b_eval.c.

const uint32_t COM_USART_CLK[COMn] = {EVAL_COM1_CLK, EVAL_COM2_CLK}

Definition at line 138 of file stm32100b_eval.c.

Referenced by STM_EVAL_COMInit().

const uint32_t GPIO_CLK[LEDn]
Initial value:
 {LED1_GPIO_CLK, LED2_GPIO_CLK, LED3_GPIO_CLK,
                                 LED4_GPIO_CLK}

Definition at line 82 of file stm32100b_eval.c.

Referenced by STM_EVAL_LEDInit().

const uint16_t GPIO_PIN[LEDn]
Initial value:
 {LED1_PIN, LED2_PIN, LED3_PIN,
                                 LED4_PIN}

Definition at line 80 of file stm32100b_eval.c.

Referenced by STM_EVAL_LEDInit(), STM_EVAL_LEDOff(), STM_EVAL_LEDOn(), and STM_EVAL_LEDToggle().

GPIO_TypeDef* GPIO_PORT[LEDn]
Initial value:
 {LED1_GPIO_PORT, LED2_GPIO_PORT, LED3_GPIO_PORT,
                                 LED4_GPIO_PORT}

Definition at line 78 of file stm32100b_eval.c.


STM32F10x Standard Peripherals Firmware Library: STM32100B_EVAL_LOW_LEVEL_Private_FunctionPrototypes

STM32100B_EVAL_LOW_LEVEL_Private_FunctionPrototypes

STM32100B_EVAL_LOW_LEVEL


STM32F10x Standard Peripherals Firmware Library: STM32100B_EVAL_LOW_LEVEL_Private_Functions

Functions

STM32100B_EVAL_LOW_LEVEL_Private_Functions

STM32100B_EVAL_LOW_LEVEL

Functions

void | LM75_LowLevel_DeInit (void)
DeInitializes the LM75_I2C.
void | LM75_LowLevel_Init (void)
Initializes the LM75_I2C.
void | SD_LowLevel_DeInit (void)
DeInitializes the SD/SD communication.
void | SD_LowLevel_Init (void)
Initializes the SD_SPI and CS pins.
void | sFLASH_LowLevel_DeInit (void)
DeInitializes the peripherals used by the SPI FLASH driver.
void | sFLASH_LowLevel_Init (void)
Initializes the peripherals used by the SPI FLASH driver.
void | STM_EVAL_COMInit (COM_TypeDef COM, USART_InitTypeDef *USART_InitStruct)
Configures COM port.
void | STM_EVAL_LEDInit (Led_TypeDef Led)
Configures LED GPIO.
void | STM_EVAL_LEDOff (Led_TypeDef Led)
Turns selected LED Off.
void | STM_EVAL_LEDOn (Led_TypeDef Led)
Turns selected LED On.
void | STM_EVAL_LEDToggle (Led_TypeDef Led)
Toggles the selected LED.
uint32_t | STM_EVAL_PBGetState (Button_TypeDef Button)
Returns the selected Button state.
void | STM_EVAL_PBInit (Button_TypeDef Button, ButtonMode_TypeDef Button_Mode)
Configures Button GPIO and EXTI Line.

Function Documentation

void LM75_LowLevel_DeInit ( void )

DeInitializes the LM75_I2C.

Parameters:
None
Return values:
None

< Disable LM75_I2C

< DeInitializes the LM75_I2C

< LM75_I2C Periph clock disable

< Configure LM75_I2C pins: SCL

< Configure LM75_I2C pins: SDA

< Configure LM75_I2C pin: SMBUS ALERT

Definition at line 544 of file stm32100b_eval.c.

Referenced by LM75_DeInit().

void LM75_LowLevel_Init ( void )

Initializes the LM75_I2C.

Parameters:
None
Return values:
None

< LM75_I2C Periph clock enable

< LM75_I2C_SCL_GPIO_CLK, LM75_I2C_SDA_GPIO_CLK and LM75_I2C_SMBUSALERT_GPIO_CLK Periph clock enable

< Configure LM75_I2C pins: SCL

< Configure LM75_I2C pins: SDA

< Configure LM75_I2C pin: SMBUS ALERT

Definition at line 575 of file stm32100b_eval.c.

Referenced by LM75_Init().

void SD_LowLevel_DeInit ( void )

DeInitializes the SD/SD communication.

Parameters:
None
Return values:
None

< SD_SPI disable

< DeInitializes the SD_SPI

< SD_SPI Periph clock disable

< Configure SD_SPI pins: SCK

< Configure SD_SPI pins: MISO

< Configure SD_SPI pins: MOSI

< Configure SD_SPI_CS_PIN pin: SD Card CS pin

< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin

Definition at line 373 of file stm32100b_eval.c.

Referenced by SD_DeInit().

void SD_LowLevel_Init ( void )

Initializes the SD_SPI and CS pins.

Parameters:
None
Return values:
None

< SD_SPI_CS_GPIO, SD_SPI_MOSI_GPIO, SD_SPI_MISO_GPIO, SD_SPI_DETECT_GPIO and SD_SPI_SCK_GPIO Periph clock enable

< SD_SPI Periph clock enable

< Configure SD_SPI pins: SCK

< Configure SD_SPI pins: MOSI

< Configure SD_SPI pins: MISO

< Configure SD_SPI_CS_PIN pin: SD Card CS pin

< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin

< SD_SPI Config

< SD_SPI enable

Definition at line 410 of file stm32100b_eval.c.

Referenced by SD_Init().

void sFLASH_LowLevel_DeInit ( void )

DeInitializes the peripherals used by the SPI FLASH driver.

Parameters:
None
Return values:
None

< Disable the sFLASH_SPI

< DeInitializes the sFLASH_SPI

< sFLASH_SPI Periph clock disable

< Configure sFLASH_SPI pins: SCK

< Configure sFLASH_SPI pins: MISO

< Configure sFLASH_SPI pins: MOSI

< Configure sFLASH_CS_PIN pin: sFLASH Card CS pin

Definition at line 470 of file stm32100b_eval.c.

Referenced by sFLASH_DeInit().

void sFLASH_LowLevel_Init ( void )

Initializes the peripherals used by the SPI FLASH driver.

Parameters:
None
Return values:
None

< sFLASH_SPI_CS_GPIO, sFLASH_SPI_MOSI_GPIO, sFLASH_SPI_MISO_GPIO and sFLASH_SPI_SCK_GPIO Periph clock enable

< sFLASH_SPI Periph clock enable

< Configure sFLASH_SPI pins: SCK

< Configure sFLASH_SPI pins: MOSI

< Configure sFLASH_SPI pins: MISO

< Configure sFLASH_CS_PIN pin: sFLASH Card CS pin

Definition at line 506 of file stm32100b_eval.c.

Referenced by sFLASH_Init().

void STM_EVAL_COMInit | ( | COM_TypeDef | COM,
 |  | USART_InitTypeDef * | USART_InitStruct
 | ) |  |

Configures COM port.

Parameters:
COM,: Specifies the COM port to be configured. This parameter can be one of following parameters:

  • COM1
  • COM2
USART_InitStruct,: pointer to a USART_InitTypeDef structure that contains the configuration information for the specified USART peripheral.
Return values:
None

Definition at line 330 of file stm32100b_eval.c.

Referenced by main().

void STM_EVAL_LEDInit ( Led_TypeDef Led )

Configures LED GPIO.

Parameters:
Led,: Specifies the Led to be configured. This parameter can be one of following parameters:

  • LED1
  • LED2
  • LED3
  • LED4
Return values:
None

Definition at line 176 of file stm32100b_eval.c.

Referenced by main().

void STM_EVAL_LEDOff ( Led_TypeDef Led )

Turns selected LED Off.

Parameters:
Led,: Specifies the Led to be set off. This parameter can be one of following parameters:

  • LED1
  • LED2
  • LED3
  • LED4
Return values:
None

Definition at line 216 of file stm32100b_eval.c.

Referenced by ADC1_2_IRQHandler(), EXTI15_10_IRQHandler(), LED_Display(), main(), SD_EraseTest(), SD_MultiBlockTest(), and SD_SingleBlockTest().

void STM_EVAL_LEDOn ( Led_TypeDef Led )

Turns selected LED On.

Parameters:
Led,: Specifies the Led to be set on. This parameter can be one of following parameters:

  • LED1
  • LED2
  • LED3
  • LED4
Return values:
None

Definition at line 201 of file stm32100b_eval.c.

Referenced by ADC1_2_IRQHandler(), CEC_IRQHandler(), EXTI15_10_IRQHandler(), EXTI9_5_IRQHandler(), LED_Display(), main(), MemManage_Handler(), RTC_Configuration(), SD_EraseTest(), SD_MultiBlockTest(), SD_SingleBlockTest(), and TAMPER_IRQHandler().

void STM_EVAL_LEDToggle ( Led_TypeDef Led )

Toggles the selected LED.

Parameters:
Led,: Specifies the Led to be toggled. This parameter can be one of following parameters:

  • LED1
  • LED2
  • LED3
  • LED4
Return values:
None

Definition at line 231 of file stm32100b_eval.c.

Referenced by DMA1_Channel5_IRQHandler(), DMA1_Channel6_IRQHandler(), EXTI0_IRQHandler(), EXTI9_5_IRQHandler(), main(), PVD_IRQHandler(), RTC_IRQHandler(), RTCAlarm_IRQHandler(), SysTick_Handler(), TIM2_IRQHandler(), TIM3_IRQHandler(), and TIM4_IRQHandler().

uint32_t STM_EVAL_PBGetState ( Button_TypeDef Button )

Returns the selected Button state.

Parameters:
Button,: Specifies the Button to be checked. This parameter can be one of following parameters:

  • BUTTON_WAKEUP: Wakeup Push Button
  • BUTTON_TAMPER: Tamper Push Button
  • BUTTON_KEY: Key Push Button
  • BUTTON_RIGHT: Joystick Right Push Button
  • BUTTON_LEFT: Joystick Left Push Button
  • BUTTON_UP: Joystick Up Push Button
  • BUTTON_DOWN: Joystick Down Push Button
  • BUTTON_SEL: Joystick Sel Push Button
Return values:
The Button GPIO pin value.

Definition at line 314 of file stm32100b_eval.c.

Referenced by main(), and ReadKey().

void STM_EVAL_PBInit | ( | Button_TypeDef | Button,
 |  | ButtonMode_TypeDef | Button_Mode
 | ) |  |

Configures Button GPIO and EXTI Line.

Parameters:
Button,: Specifies the Button to be configured. This parameter can be one of following parameters:

  • BUTTON_WAKEUP: Wakeup Push Button
  • BUTTON_TAMPER: Tamper Push Button
  • BUTTON_KEY: Key Push Button
  • BUTTON_RIGHT: Joystick Right Push Button
  • BUTTON_LEFT: Joystick Left Push Button
  • BUTTON_UP: Joystick Up Push Button
  • BUTTON_DOWN: Joystick Down Push Button
  • BUTTON_SEL: Joystick Sel Push Button
Button_Mode,: Specifies Button mode. This parameter can be one of following parameters:

  • BUTTON_MODE_GPIO: Button will be used as simple IO
  • BUTTON_MODE_EXTI: Button will be connected to EXTI line with interrupt generation capability
Return values:
None

Definition at line 255 of file stm32100b_eval.c.

Referenced by main().


STM32F10x Standard Peripherals Firmware Library: STM32100B_EVAL_LOW_LEVEL_Exported_Types

STM32100B_EVAL_LOW_LEVEL_Exported_Types

STM32100B_EVAL_LOW_LEVEL


STM32F10x Standard Peripherals Firmware Library: STM32100B_EVAL_LOW_LEVEL_LED

Defines

STM32100B_EVAL_LOW_LEVEL_LED

STM32100B_EVAL_LOW_LEVEL_Exported_Constants

Defines

#define | LED1_GPIO_CLK RCC_APB2Periph_GPIOC
#define | LED1_GPIO_PORT GPIOC
#define | LED1_PIN GPIO_Pin_6
#define | LED2_GPIO_CLK RCC_APB2Periph_GPIOC
#define | LED2_GPIO_PORT GPIOC
#define | LED2_PIN GPIO_Pin_7
#define | LED3_GPIO_CLK RCC_APB2Periph_GPIOC
#define | LED3_GPIO_PORT GPIOC
#define | LED3_PIN GPIO_Pin_8
#define | LED4_GPIO_CLK RCC_APB2Periph_GPIOC
#define | LED4_GPIO_PORT GPIOC
#define | LED4_PIN GPIO_Pin_9
#define | LEDn 4

Define Documentation

#define LED1_GPIO_CLK RCC_APB2Periph_GPIOC

Definition at line 67 of file stm32100b_eval.h.

#define LED1_GPIO_PORT GPIOC

Definition at line 66 of file stm32100b_eval.h.

#define LED1_PIN GPIO_Pin_6

Definition at line 65 of file stm32100b_eval.h.

#define LED2_GPIO_CLK RCC_APB2Periph_GPIOC

Definition at line 71 of file stm32100b_eval.h.

#define LED2_GPIO_PORT GPIOC

Definition at line 70 of file stm32100b_eval.h.

#define LED2_PIN GPIO_Pin_7

Definition at line 69 of file stm32100b_eval.h.

#define LED3_GPIO_CLK RCC_APB2Periph_GPIOC

Definition at line 75 of file stm32100b_eval.h.

#define LED3_GPIO_PORT GPIOC

Definition at line 74 of file stm32100b_eval.h.

#define LED3_PIN GPIO_Pin_8

Definition at line 73 of file stm32100b_eval.h.

#define LED4_GPIO_CLK RCC_APB2Periph_GPIOC

Definition at line 79 of file stm32100b_eval.h.

#define LED4_GPIO_PORT GPIOC

Definition at line 78 of file stm32100b_eval.h.

#define LED4_PIN GPIO_Pin_9

Definition at line 77 of file stm32100b_eval.h.

#define LEDn 4

Definition at line 64 of file stm32100b_eval.h.


STM32F10x Standard Peripherals Firmware Library: STM32100B_EVAL_LOW_LEVEL_BUTTON

Defines

STM32100B_EVAL_LOW_LEVEL_BUTTON

STM32100B_EVAL_LOW_LEVEL_Exported_Constants

Defines

#define | BUTTONn 8
#define | DOWN_BUTTON_EXTI_IRQn EXTI15_10_IRQn
#define | DOWN_BUTTON_EXTI_LINE EXTI_Line14
#define | DOWN_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource14
#define | DOWN_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOD
#define | DOWN_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOD
#define | DOWN_BUTTON_GPIO_PORT GPIOD
#define | DOWN_BUTTON_PIN GPIO_Pin_14
Joystick Down push-button.
#define | KEY_BUTTON_EXTI_IRQn EXTI9_5_IRQn
#define | KEY_BUTTON_EXTI_LINE EXTI_Line9
#define | KEY_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource9
#define | KEY_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOB
#define | KEY_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOB
#define | KEY_BUTTON_GPIO_PORT GPIOB
#define | KEY_BUTTON_PIN GPIO_Pin_9
Key push-button.
#define | LEFT_BUTTON_EXTI_IRQn EXTI0_IRQn
#define | LEFT_BUTTON_EXTI_LINE EXTI_Line0
#define | LEFT_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource0
#define | LEFT_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOE
#define | LEFT_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOE
#define | LEFT_BUTTON_GPIO_PORT GPIOE
#define | LEFT_BUTTON_PIN GPIO_Pin_0
Joystick Left push-button.
#define | RIGHT_BUTTON_EXTI_IRQn EXTI1_IRQn
#define | RIGHT_BUTTON_EXTI_LINE EXTI_Line1
#define | RIGHT_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource1
#define | RIGHT_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOE
#define | RIGHT_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOE
#define | RIGHT_BUTTON_GPIO_PORT GPIOE
#define | RIGHT_BUTTON_PIN GPIO_Pin_1
Joystick Right push-button.
#define | SEL_BUTTON_EXTI_IRQn EXTI15_10_IRQn
#define | SEL_BUTTON_EXTI_LINE EXTI_Line12
#define | SEL_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource12
#define | SEL_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOD
#define | SEL_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOD
#define | SEL_BUTTON_GPIO_PORT GPIOD
#define | SEL_BUTTON_PIN GPIO_Pin_12
Joystick Sel push-button.
#define | TAMPER_BUTTON_EXTI_IRQn EXTI15_10_IRQn
#define | TAMPER_BUTTON_EXTI_LINE EXTI_Line13
#define | TAMPER_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource13
#define | TAMPER_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOC
#define | TAMPER_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOC
#define | TAMPER_BUTTON_GPIO_PORT GPIOC
#define | TAMPER_BUTTON_PIN GPIO_Pin_13
Tamper push-button.
#define | UP_BUTTON_EXTI_IRQn EXTI9_5_IRQn
#define | UP_BUTTON_EXTI_LINE EXTI_Line8
#define | UP_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource8
#define | UP_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOD
#define | UP_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOD
#define | UP_BUTTON_GPIO_PORT GPIOD
#define | UP_BUTTON_PIN GPIO_Pin_8
Joystick Up push-button.
#define | WAKEUP_BUTTON_EXTI_IRQn EXTI0_IRQn
#define | WAKEUP_BUTTON_EXTI_LINE EXTI_Line0
#define | WAKEUP_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource0
#define | WAKEUP_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOA
#define | WAKEUP_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOA
#define | WAKEUP_BUTTON_GPIO_PORT GPIOA
#define | WAKEUP_BUTTON_PIN GPIO_Pin_0
Wakeup push-button.

Define Documentation

#define BUTTONn 8

Definition at line 88 of file stm32100b_eval.h.

#define DOWN_BUTTON_EXTI_IRQn EXTI15_10_IRQn

Definition at line 159 of file stm32100b_eval.h.

#define DOWN_BUTTON_EXTI_LINE EXTI_Line14

Definition at line 156 of file stm32100b_eval.h.

#define DOWN_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource14

Definition at line 158 of file stm32100b_eval.h.

#define DOWN_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOD

Definition at line 157 of file stm32100b_eval.h.

#define DOWN_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOD

Definition at line 155 of file stm32100b_eval.h.

#define DOWN_BUTTON_GPIO_PORT GPIOD

Definition at line 154 of file stm32100b_eval.h.

#define DOWN_BUTTON_PIN GPIO_Pin_14

Joystick Down push-button.

Definition at line 153 of file stm32100b_eval.h.

#define KEY_BUTTON_EXTI_IRQn EXTI9_5_IRQn

Definition at line 119 of file stm32100b_eval.h.

#define KEY_BUTTON_EXTI_LINE EXTI_Line9

Definition at line 116 of file stm32100b_eval.h.

Referenced by EXTI9_5_IRQHandler().

#define KEY_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource9

Definition at line 118 of file stm32100b_eval.h.

#define KEY_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOB

Definition at line 117 of file stm32100b_eval.h.

#define KEY_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOB

Definition at line 115 of file stm32100b_eval.h.

#define KEY_BUTTON_GPIO_PORT GPIOB

Definition at line 114 of file stm32100b_eval.h.

#define KEY_BUTTON_PIN GPIO_Pin_9

Key push-button.

Definition at line 113 of file stm32100b_eval.h.

#define LEFT_BUTTON_EXTI_IRQn EXTI0_IRQn

Definition at line 139 of file stm32100b_eval.h.

#define LEFT_BUTTON_EXTI_LINE EXTI_Line0

Definition at line 136 of file stm32100b_eval.h.

#define LEFT_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource0

Definition at line 138 of file stm32100b_eval.h.

#define LEFT_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOE

Definition at line 137 of file stm32100b_eval.h.

#define LEFT_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOE

Definition at line 135 of file stm32100b_eval.h.

#define LEFT_BUTTON_GPIO_PORT GPIOE

Definition at line 134 of file stm32100b_eval.h.

#define LEFT_BUTTON_PIN GPIO_Pin_0

Joystick Left push-button.

Definition at line 133 of file stm32100b_eval.h.

#define RIGHT_BUTTON_EXTI_IRQn EXTI1_IRQn

Definition at line 129 of file stm32100b_eval.h.

#define RIGHT_BUTTON_EXTI_LINE EXTI_Line1

Definition at line 126 of file stm32100b_eval.h.

#define RIGHT_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource1

Definition at line 128 of file stm32100b_eval.h.

#define RIGHT_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOE

Definition at line 127 of file stm32100b_eval.h.

#define RIGHT_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOE

Definition at line 125 of file stm32100b_eval.h.

#define RIGHT_BUTTON_GPIO_PORT GPIOE

Definition at line 124 of file stm32100b_eval.h.

#define RIGHT_BUTTON_PIN GPIO_Pin_1

Joystick Right push-button.

Definition at line 123 of file stm32100b_eval.h.

#define SEL_BUTTON_EXTI_IRQn EXTI15_10_IRQn

Definition at line 169 of file stm32100b_eval.h.

#define SEL_BUTTON_EXTI_LINE EXTI_Line12

Definition at line 166 of file stm32100b_eval.h.

#define SEL_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource12

Definition at line 168 of file stm32100b_eval.h.

#define SEL_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOD

Definition at line 167 of file stm32100b_eval.h.

#define SEL_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOD

Definition at line 165 of file stm32100b_eval.h.

#define SEL_BUTTON_GPIO_PORT GPIOD

Definition at line 164 of file stm32100b_eval.h.

#define SEL_BUTTON_PIN GPIO_Pin_12

Joystick Sel push-button.

Definition at line 163 of file stm32100b_eval.h.

#define TAMPER_BUTTON_EXTI_IRQn EXTI15_10_IRQn

Definition at line 109 of file stm32100b_eval.h.

#define TAMPER_BUTTON_EXTI_LINE EXTI_Line13

Definition at line 106 of file stm32100b_eval.h.

#define TAMPER_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource13

Definition at line 108 of file stm32100b_eval.h.

#define TAMPER_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOC

Definition at line 107 of file stm32100b_eval.h.

#define TAMPER_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOC

Definition at line 105 of file stm32100b_eval.h.

#define TAMPER_BUTTON_GPIO_PORT GPIOC

Definition at line 104 of file stm32100b_eval.h.

#define TAMPER_BUTTON_PIN GPIO_Pin_13

Tamper push-button.

Definition at line 103 of file stm32100b_eval.h.

#define UP_BUTTON_EXTI_IRQn EXTI9_5_IRQn

Definition at line 149 of file stm32100b_eval.h.

#define UP_BUTTON_EXTI_LINE EXTI_Line8

Definition at line 146 of file stm32100b_eval.h.

#define UP_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource8

Definition at line 148 of file stm32100b_eval.h.

#define UP_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOD

Definition at line 147 of file stm32100b_eval.h.

#define UP_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOD

Definition at line 145 of file stm32100b_eval.h.

#define UP_BUTTON_GPIO_PORT GPIOD

Definition at line 144 of file stm32100b_eval.h.

#define UP_BUTTON_PIN GPIO_Pin_8

Joystick Up push-button.

Definition at line 143 of file stm32100b_eval.h.

#define WAKEUP_BUTTON_EXTI_IRQn EXTI0_IRQn

Definition at line 99 of file stm32100b_eval.h.

Referenced by EXTI9_5_IRQHandler(), and SysTick_Handler().

#define WAKEUP_BUTTON_EXTI_LINE EXTI_Line0

Definition at line 96 of file stm32100b_eval.h.

Referenced by EXTI0_IRQHandler().

#define WAKEUP_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource0

Definition at line 98 of file stm32100b_eval.h.

#define WAKEUP_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOA

Definition at line 97 of file stm32100b_eval.h.

#define WAKEUP_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOA

Definition at line 95 of file stm32100b_eval.h.

#define WAKEUP_BUTTON_GPIO_PORT GPIOA

Definition at line 94 of file stm32100b_eval.h.

#define WAKEUP_BUTTON_PIN GPIO_Pin_0

Wakeup push-button.

Definition at line 93 of file stm32100b_eval.h.


STM32F10x Standard Peripherals Firmware Library: STM32100B_EVAL_LOW_LEVEL_COM

Defines

STM32100B_EVAL_LOW_LEVEL_COM

STM32100B_EVAL_LOW_LEVEL_Exported_Constants

Defines

#define | COMn 2
#define | EVAL_COM1 USART1
Definition for COM port1, connected to USART1.
#define | EVAL_COM1_CLK RCC_APB2Periph_USART1
#define | EVAL_COM1_IRQn USART1_IRQn
#define | EVAL_COM1_RX_GPIO_CLK RCC_APB2Periph_GPIOA
#define | EVAL_COM1_RX_GPIO_PORT GPIOA
#define | EVAL_COM1_RX_PIN GPIO_Pin_10
#define | EVAL_COM1_TX_GPIO_CLK RCC_APB2Periph_GPIOA
#define | EVAL_COM1_TX_GPIO_PORT GPIOA
#define | EVAL_COM1_TX_PIN GPIO_Pin_9
#define | EVAL_COM2 USART2
Definition for COM port2, connected to USART2 (USART2 pins remapped on GPIOD)
#define | EVAL_COM2_CLK RCC_APB1Periph_USART2
#define | EVAL_COM2_IRQn USART2_IRQn
#define | EVAL_COM2_RX_GPIO_CLK RCC_APB2Periph_GPIOD
#define | EVAL_COM2_RX_GPIO_PORT GPIOD
#define | EVAL_COM2_RX_PIN GPIO_Pin_6
#define | EVAL_COM2_TX_GPIO_CLK RCC_APB2Periph_GPIOD
#define | EVAL_COM2_TX_GPIO_PORT GPIOD
#define | EVAL_COM2_TX_PIN GPIO_Pin_5

Define Documentation

#define COMn 2

Definition at line 177 of file stm32100b_eval.h.

#define EVAL_COM1 USART1

Definition for COM port1, connected to USART1.

Definition at line 182 of file stm32100b_eval.h.

Referenced by main(), and USARTx_IRQHandler().

#define EVAL_COM1_CLK RCC_APB2Periph_USART1

Definition at line 183 of file stm32100b_eval.h.

#define EVAL_COM1_IRQn USART1_IRQn

Definition at line 190 of file stm32100b_eval.h.

#define EVAL_COM1_RX_GPIO_CLK RCC_APB2Periph_GPIOA

Definition at line 189 of file stm32100b_eval.h.

#define EVAL_COM1_RX_GPIO_PORT GPIOA

Definition at line 188 of file stm32100b_eval.h.

#define EVAL_COM1_RX_PIN GPIO_Pin_10

Definition at line 187 of file stm32100b_eval.h.

#define EVAL_COM1_TX_GPIO_CLK RCC_APB2Periph_GPIOA

Definition at line 186 of file stm32100b_eval.h.

#define EVAL_COM1_TX_GPIO_PORT GPIOA

Definition at line 185 of file stm32100b_eval.h.

#define EVAL_COM1_TX_PIN GPIO_Pin_9

Definition at line 184 of file stm32100b_eval.h.

#define EVAL_COM2 USART2

Definition for COM port2, connected to USART2 (USART2 pins remapped on GPIOD)

Definition at line 195 of file stm32100b_eval.h.

#define EVAL_COM2_CLK RCC_APB1Periph_USART2

Definition at line 196 of file stm32100b_eval.h.

#define EVAL_COM2_IRQn USART2_IRQn

Definition at line 203 of file stm32100b_eval.h.

#define EVAL_COM2_RX_GPIO_CLK RCC_APB2Periph_GPIOD

Definition at line 202 of file stm32100b_eval.h.

#define EVAL_COM2_RX_GPIO_PORT GPIOD

Definition at line 201 of file stm32100b_eval.h.

#define EVAL_COM2_RX_PIN GPIO_Pin_6

Definition at line 200 of file stm32100b_eval.h.

#define EVAL_COM2_TX_GPIO_CLK RCC_APB2Periph_GPIOD

Definition at line 199 of file stm32100b_eval.h.

#define EVAL_COM2_TX_GPIO_PORT GPIOD

Definition at line 198 of file stm32100b_eval.h.

#define EVAL_COM2_TX_PIN GPIO_Pin_5

Definition at line 197 of file stm32100b_eval.h.


STM32F10x Standard Peripherals Firmware Library: STM32100B_EVAL_LOW_LEVEL_SD_SPI

Defines

STM32100B_EVAL_LOW_LEVEL_SD_SPI

STM32100B_EVAL_LOW_LEVEL_Exported_Constants

Defines

#define | SD_CS_GPIO_CLK RCC_APB2Periph_GPIOC
#define | SD_CS_GPIO_PORT GPIOC
#define | SD_CS_PIN GPIO_Pin_12
#define | SD_DETECT_GPIO_CLK RCC_APB2Periph_GPIOE
#define | SD_DETECT_GPIO_PORT GPIOE
#define | SD_DETECT_PIN GPIO_Pin_7
#define | SD_SPI SPI1
SD SPI Interface pins.
#define | SD_SPI_CLK RCC_APB2Periph_SPI1
#define | SD_SPI_MISO_GPIO_CLK RCC_APB2Periph_GPIOA
#define | SD_SPI_MISO_GPIO_PORT GPIOA
#define | SD_SPI_MISO_PIN GPIO_Pin_6
#define | SD_SPI_MOSI_GPIO_CLK RCC_APB2Periph_GPIOA
#define | SD_SPI_MOSI_GPIO_PORT GPIOA
#define | SD_SPI_MOSI_PIN GPIO_Pin_7
#define | SD_SPI_SCK_GPIO_CLK RCC_APB2Periph_GPIOA
#define | SD_SPI_SCK_GPIO_PORT GPIOA
#define | SD_SPI_SCK_PIN GPIO_Pin_5

Define Documentation

#define SD_CS_GPIO_CLK RCC_APB2Periph_GPIOC

Definition at line 228 of file stm32100b_eval.h.

Referenced by SD_LowLevel_Init().

#define SD_CS_GPIO_PORT GPIOC

Definition at line 227 of file stm32100b_eval.h.

Referenced by SD_LowLevel_DeInit(), and SD_LowLevel_Init().

#define SD_CS_PIN GPIO_Pin_12

Definition at line 226 of file stm32100b_eval.h.

Referenced by SD_LowLevel_DeInit(), and SD_LowLevel_Init().

#define SD_DETECT_GPIO_CLK RCC_APB2Periph_GPIOE

Definition at line 231 of file stm32100b_eval.h.

Referenced by SD_LowLevel_Init().

#define SD_DETECT_GPIO_PORT GPIOE

Definition at line 230 of file stm32100b_eval.h.

Referenced by SD_Detect(), SD_LowLevel_DeInit(), and SD_LowLevel_Init().

#define SD_DETECT_PIN GPIO_Pin_7

Definition at line 229 of file stm32100b_eval.h.

Referenced by SD_Detect(), SD_LowLevel_DeInit(), and SD_LowLevel_Init().

#define SD_SPI SPI1

SD SPI Interface pins.

Definition at line 215 of file stm32100b_eval.h.

Referenced by SD_LowLevel_DeInit(), SD_LowLevel_Init(), SD_ReadByte(), and SD_WriteByte().

#define SD_SPI_CLK RCC_APB2Periph_SPI1

Definition at line 216 of file stm32100b_eval.h.

Referenced by SD_LowLevel_DeInit(), and SD_LowLevel_Init().

#define SD_SPI_MISO_GPIO_CLK RCC_APB2Periph_GPIOA

Definition at line 222 of file stm32100b_eval.h.

Referenced by SD_LowLevel_Init().

#define SD_SPI_MISO_GPIO_PORT GPIOA

Definition at line 221 of file stm32100b_eval.h.

Referenced by SD_LowLevel_DeInit(), and SD_LowLevel_Init().

#define SD_SPI_MISO_PIN GPIO_Pin_6

Definition at line 220 of file stm32100b_eval.h.

Referenced by SD_LowLevel_DeInit(), and SD_LowLevel_Init().

#define SD_SPI_MOSI_GPIO_CLK RCC_APB2Periph_GPIOA

Definition at line 225 of file stm32100b_eval.h.

Referenced by SD_LowLevel_Init().

#define SD_SPI_MOSI_GPIO_PORT GPIOA

Definition at line 224 of file stm32100b_eval.h.

Referenced by SD_LowLevel_DeInit(), and SD_LowLevel_Init().

#define SD_SPI_MOSI_PIN GPIO_Pin_7

Definition at line 223 of file stm32100b_eval.h.

Referenced by SD_LowLevel_DeInit(), and SD_LowLevel_Init().

#define SD_SPI_SCK_GPIO_CLK RCC_APB2Periph_GPIOA

Definition at line 219 of file stm32100b_eval.h.

Referenced by SD_LowLevel_Init().

#define SD_SPI_SCK_GPIO_PORT GPIOA

Definition at line 218 of file stm32100b_eval.h.

Referenced by SD_LowLevel_DeInit(), and SD_LowLevel_Init().

#define SD_SPI_SCK_PIN GPIO_Pin_5

Definition at line 217 of file stm32100b_eval.h.

Referenced by SD_LowLevel_DeInit(), and SD_LowLevel_Init().


STM32F10x Standard Peripherals Firmware Library: STM32100B_EVAL_LOW_LEVEL_M25P_FLASH_SPI

Defines

STM32100B_EVAL_LOW_LEVEL_M25P_FLASH_SPI

STM32100B_EVAL_LOW_LEVEL_Exported_Constants

Defines

#define | sFLASH_CS_GPIO_CLK RCC_APB2Periph_GPIOD
#define | sFLASH_CS_GPIO_PORT GPIOD
#define | sFLASH_CS_PIN GPIO_Pin_9
#define | sFLASH_SPI SPI1
M25P FLASH SPI Interface pins.
#define | sFLASH_SPI_CLK RCC_APB2Periph_SPI1
#define | sFLASH_SPI_MISO_GPIO_CLK RCC_APB2Periph_GPIOA
#define | sFLASH_SPI_MISO_GPIO_PORT GPIOA
#define | sFLASH_SPI_MISO_PIN GPIO_Pin_6
#define | sFLASH_SPI_MOSI_GPIO_CLK RCC_APB2Periph_GPIOA
#define | sFLASH_SPI_MOSI_GPIO_PORT GPIOA
#define | sFLASH_SPI_MOSI_PIN GPIO_Pin_7
#define | sFLASH_SPI_SCK_GPIO_CLK RCC_APB2Periph_GPIOA
#define | sFLASH_SPI_SCK_GPIO_PORT GPIOA
#define | sFLASH_SPI_SCK_PIN GPIO_Pin_5

Define Documentation

#define sFLASH_CS_GPIO_CLK RCC_APB2Periph_GPIOD

Definition at line 256 of file stm32100b_eval.h.

Referenced by sFLASH_LowLevel_Init().

#define sFLASH_CS_GPIO_PORT GPIOD

Definition at line 255 of file stm32100b_eval.h.

Referenced by sFLASH_LowLevel_DeInit(), and sFLASH_LowLevel_Init().

#define sFLASH_CS_PIN GPIO_Pin_9

Definition at line 254 of file stm32100b_eval.h.

Referenced by sFLASH_LowLevel_DeInit(), and sFLASH_LowLevel_Init().

#define sFLASH_SPI SPI1

M25P FLASH SPI Interface pins.

Definition at line 243 of file stm32100b_eval.h.

Referenced by sFLASH_Init(), sFLASH_LowLevel_DeInit(), sFLASH_SendByte(), and sFLASH_SendHalfWord().

#define sFLASH_SPI_CLK RCC_APB2Periph_SPI1

Definition at line 244 of file stm32100b_eval.h.

Referenced by sFLASH_LowLevel_DeInit(), and sFLASH_LowLevel_Init().

#define sFLASH_SPI_MISO_GPIO_CLK RCC_APB2Periph_GPIOA

Definition at line 250 of file stm32100b_eval.h.

Referenced by sFLASH_LowLevel_Init().

#define sFLASH_SPI_MISO_GPIO_PORT GPIOA

Definition at line 249 of file stm32100b_eval.h.

Referenced by sFLASH_LowLevel_DeInit(), and sFLASH_LowLevel_Init().

#define sFLASH_SPI_MISO_PIN GPIO_Pin_6

Definition at line 248 of file stm32100b_eval.h.

Referenced by sFLASH_LowLevel_DeInit(), and sFLASH_LowLevel_Init().

#define sFLASH_SPI_MOSI_GPIO_CLK RCC_APB2Periph_GPIOA

Definition at line 253 of file stm32100b_eval.h.

Referenced by sFLASH_LowLevel_Init().

#define sFLASH_SPI_MOSI_GPIO_PORT GPIOA

Definition at line 252 of file stm32100b_eval.h.

Referenced by sFLASH_LowLevel_DeInit(), and sFLASH_LowLevel_Init().

#define sFLASH_SPI_MOSI_PIN GPIO_Pin_7

Definition at line 251 of file stm32100b_eval.h.

Referenced by sFLASH_LowLevel_DeInit(), and sFLASH_LowLevel_Init().

#define sFLASH_SPI_SCK_GPIO_CLK RCC_APB2Periph_GPIOA

Definition at line 247 of file stm32100b_eval.h.

Referenced by sFLASH_LowLevel_Init().

#define sFLASH_SPI_SCK_GPIO_PORT GPIOA

Definition at line 246 of file stm32100b_eval.h.

Referenced by sFLASH_LowLevel_DeInit(), and sFLASH_LowLevel_Init().

#define sFLASH_SPI_SCK_PIN GPIO_Pin_5

Definition at line 245 of file stm32100b_eval.h.

Referenced by sFLASH_LowLevel_DeInit(), and sFLASH_LowLevel_Init().


STM32F10x Standard Peripherals Firmware Library: STM32100B_EVAL_LOW_LEVEL_TSENSOR_I2C

Defines

STM32100B_EVAL_LOW_LEVEL_TSENSOR_I2C

STM32100B_EVAL_LOW_LEVEL_Exported_Constants

Defines

#define | LM75_DMA_CLK RCC_AHBPeriph_DMA1
#define | LM75_DMA_RX_CHANNEL DMA1_Channel7
#define | LM75_DMA_RX_TCFLAG DMA1_FLAG_TC7
#define | LM75_DMA_TX_CHANNEL DMA1_Channel6
#define | LM75_DMA_TX_TCFLAG DMA1_FLAG_TC6
#define | LM75_I2C I2C1
LM75 Temperature Sensor I2C Interface pins.
#define | LM75_I2C_CLK RCC_APB1Periph_I2C1
#define | LM75_I2C_DR ((uint32_t)0x40005410)
#define | LM75_I2C_SCL_GPIO_CLK RCC_APB2Periph_GPIOB
#define | LM75_I2C_SCL_GPIO_PORT GPIOB
#define | LM75_I2C_SCL_PIN GPIO_Pin_6
#define | LM75_I2C_SDA_GPIO_CLK RCC_APB2Periph_GPIOB
#define | LM75_I2C_SDA_GPIO_PORT GPIOB
#define | LM75_I2C_SDA_PIN GPIO_Pin_7
#define | LM75_I2C_SMBUSALERT_GPIO_CLK RCC_APB2Periph_GPIOB
#define | LM75_I2C_SMBUSALERT_GPIO_PORT GPIOB
#define | LM75_I2C_SMBUSALERT_PIN GPIO_Pin_5

Define Documentation

#define LM75_DMA_CLK RCC_AHBPeriph_DMA1

Definition at line 281 of file stm32100b_eval.h.

Referenced by LM75_DMA_Config().

#define LM75_DMA_RX_CHANNEL DMA1_Channel7

Definition at line 283 of file stm32100b_eval.h.

Referenced by LM75_DMA_Config(), LM75_ReadConfReg(), LM75_ReadReg(), LM75_ReadTemp(), and LM75_ShutDown().

#define LM75_DMA_RX_TCFLAG DMA1_FLAG_TC7

Definition at line 285 of file stm32100b_eval.h.

Referenced by LM75_ReadConfReg(), LM75_ReadReg(), LM75_ReadTemp(), and LM75_ShutDown().

#define LM75_DMA_TX_CHANNEL DMA1_Channel6

Definition at line 282 of file stm32100b_eval.h.

Referenced by LM75_DMA_Config(), LM75_ShutDown(), LM75_WriteConfReg(), and LM75_WriteReg().

#define LM75_DMA_TX_TCFLAG DMA1_FLAG_TC6

Definition at line 284 of file stm32100b_eval.h.

Referenced by LM75_ShutDown(), LM75_WriteConfReg(), and LM75_WriteReg().

#define LM75_I2C I2C1

LM75 Temperature Sensor I2C Interface pins.

Definition at line 268 of file stm32100b_eval.h.

Referenced by I2C1_ER_IRQHandler(), LM75_GetStatus(), LM75_Init(), LM75_LowLevel_DeInit(), LM75_ReadConfReg(), LM75_ReadReg(), LM75_ReadTemp(), LM75_ShutDown(), LM75_WriteConfReg(), LM75_WriteReg(), and main().

#define LM75_I2C_CLK RCC_APB1Periph_I2C1

Definition at line 269 of file stm32100b_eval.h.

Referenced by LM75_LowLevel_DeInit(), and LM75_LowLevel_Init().

#define LM75_I2C_DR ((uint32_t)0x40005410)

Definition at line 279 of file stm32100b_eval.h.

Referenced by LM75_DMA_Config().

#define LM75_I2C_SCL_GPIO_CLK RCC_APB2Periph_GPIOB

Definition at line 272 of file stm32100b_eval.h.

Referenced by LM75_LowLevel_Init().

#define LM75_I2C_SCL_GPIO_PORT GPIOB

Definition at line 271 of file stm32100b_eval.h.

Referenced by LM75_LowLevel_DeInit(), and LM75_LowLevel_Init().

#define LM75_I2C_SCL_PIN GPIO_Pin_6

Definition at line 270 of file stm32100b_eval.h.

Referenced by LM75_LowLevel_DeInit(), and LM75_LowLevel_Init().

#define LM75_I2C_SDA_GPIO_CLK RCC_APB2Periph_GPIOB

Definition at line 275 of file stm32100b_eval.h.

Referenced by LM75_LowLevel_Init().

#define LM75_I2C_SDA_GPIO_PORT GPIOB

Definition at line 274 of file stm32100b_eval.h.

Referenced by LM75_LowLevel_DeInit(), and LM75_LowLevel_Init().

#define LM75_I2C_SDA_PIN GPIO_Pin_7

Definition at line 273 of file stm32100b_eval.h.

Referenced by LM75_LowLevel_DeInit(), and LM75_LowLevel_Init().

#define LM75_I2C_SMBUSALERT_GPIO_CLK RCC_APB2Periph_GPIOB

Definition at line 278 of file stm32100b_eval.h.

Referenced by LM75_LowLevel_Init().

#define LM75_I2C_SMBUSALERT_GPIO_PORT GPIOB

Definition at line 277 of file stm32100b_eval.h.

Referenced by LM75_LowLevel_DeInit(), and LM75_LowLevel_Init().

#define LM75_I2C_SMBUSALERT_PIN GPIO_Pin_5

Definition at line 276 of file stm32100b_eval.h.

Referenced by LM75_LowLevel_DeInit(), and LM75_LowLevel_Init().


STM32F10x Standard Peripherals Firmware Library: STM32100B_EVAL_LOW_LEVEL_Exported_Macros

STM32100B_EVAL_LOW_LEVEL_Exported_Macros

STM32100B_EVAL_LOW_LEVEL


STM32F10x Standard Peripherals Firmware Library: STM32100B_EVAL_LOW_LEVEL_Exported_Functions

Functions

STM32100B_EVAL_LOW_LEVEL_Exported_Functions

STM32100B_EVAL_LOW_LEVEL

Functions

void | LM75_LowLevel_DeInit (void)
DeInitializes the LM75_I2C.
void | LM75_LowLevel_Init (void)
Initializes the LM75_I2C.
void | SD_LowLevel_DeInit (void)
DeInitializes the SD/SD communication.
void | SD_LowLevel_Init (void)
Initializes the SD_SPI and CS pins.
void | sFLASH_LowLevel_DeInit (void)
DeInitializes the peripherals used by the SPI FLASH driver.
void | sFLASH_LowLevel_Init (void)
Initializes the peripherals used by the SPI FLASH driver.
void | STM_EVAL_COMInit (COM_TypeDef COM, USART_InitTypeDef *USART_InitStruct)
Configures COM port.
void | STM_EVAL_LEDInit (Led_TypeDef Led)
Configures LED GPIO.
void | STM_EVAL_LEDOff (Led_TypeDef Led)
Turns selected LED Off.
void | STM_EVAL_LEDOn (Led_TypeDef Led)
Turns selected LED On.
void | STM_EVAL_LEDToggle (Led_TypeDef Led)
Toggles the selected LED.
uint32_t | STM_EVAL_PBGetState (Button_TypeDef Button)
Returns the selected Button state.
void | STM_EVAL_PBInit (Button_TypeDef Button, ButtonMode_TypeDef Button_Mode)
Configures Button GPIO and EXTI Line.

Function Documentation

void LM75_LowLevel_DeInit ( void )

DeInitializes the LM75_I2C.

Parameters:
None
Return values:
None

< Disable LM75_I2C

< DeInitializes the LM75_I2C

< LM75_I2C Periph clock disable

< Configure LM75_I2C pins: SCL

< Configure LM75_I2C pins: SDA

< Configure LM75_I2C pin: SMBUS ALERT

< Disable LM75_I2C

< DeInitializes the LM75_I2C

< LM75_I2C Periph clock disable

< Configure LM75_I2C pins: SCL

< Configure LM75_I2C pins: SDA

< Configure LM75_I2C pin: SMBUS ALERT

< Disable LM75_I2C

< DeInitializes the LM75_I2C

< LM75_I2C Periph clock disable

< Configure LM75_I2C pins: SCL

< Configure LM75_I2C pins: SDA

< Configure LM75_I2C pin: SMBUS ALERT

< Disable LM75_I2C

< DeInitializes the LM75_I2C

< LM75_I2C Periph clock disable

< Configure LM75_I2C pins: SCL

< Configure LM75_I2C pins: SDA

< Configure LM75_I2C pin: SMBUS ALERT

< Disable LM75_I2C

< DeInitializes the LM75_I2C

< LM75_I2C Periph clock disable

< Configure LM75_I2C pins: SCL

< Configure LM75_I2C pins: SDA

< Configure LM75_I2C pin: SMBUS ALERT

Definition at line 544 of file stm32100b_eval.c.

void LM75_LowLevel_Init ( void )

Initializes the LM75_I2C.

Parameters:
None
Return values:
None
Parameters:
None
Return values:
None

< LM75_I2C Periph clock enable

< LM75_I2C_SCL_GPIO_CLK, LM75_I2C_SDA_GPIO_CLK and LM75_I2C_SMBUSALERT_GPIO_CLK Periph clock enable

< Configure LM75_I2C pins: SCL

< Configure LM75_I2C pins: SDA

< Configure LM75_I2C pin: SMBUS ALERT

< LM75_I2C Periph clock enable

< LM75_I2C_SCL_GPIO_CLK, LM75_I2C_SDA_GPIO_CLK and LM75_I2C_SMBUSALERT_GPIO_CLK Periph clock enable

< Configure LM75_I2C pins: SCL

< Configure LM75_I2C pins: SDA

< Configure LM75_I2C pin: SMBUS ALERT

< LM75_I2C Periph clock enable

< LM75_I2C_SCL_GPIO_CLK, LM75_I2C_SDA_GPIO_CLK and LM75_I2C_SMBUSALERT_GPIO_CLK Periph clock enable

< Configure LM75_I2C pins: SCL

< Configure LM75_I2C pins: SDA

< Configure LM75_I2C pin: SMBUS ALERT

< LM75_I2C Periph clock enable

< LM75_I2C_SCL_GPIO_CLK, LM75_I2C_SDA_GPIO_CLK and LM75_I2C_SMBUSALERT_GPIO_CLK Periph clock enable

< Configure LM75_I2C pins: SCL

< Configure LM75_I2C pins: SDA

< Configure LM75_I2C pin: SMBUS ALERT

< LM75_I2C Periph clock enable

< LM75_I2C_SCL_GPIO_CLK, LM75_I2C_SDA_GPIO_CLK and LM75_I2C_SMBUSALERT_GPIO_CLK Periph clock enable

< Configure LM75_I2C pins: SCL

< Configure LM75_I2C pins: SDA

< Configure LM75_I2C pin: SMBUS ALERT

Definition at line 575 of file stm32100b_eval.c.

void SD_LowLevel_DeInit ( void )

DeInitializes the SD/SD communication.

Parameters:
None
Return values:
None DeInitializes the SD/SD communication.
Parameters:
None
Return values:
None

< SD_SPI disable

< DeInitializes the SD_SPI

< SD_SPI Periph clock disable

< Configure SD_SPI pins: SCK

< Configure SD_SPI pins: MISO

< Configure SD_SPI pins: MOSI

< Configure SD_SPI_CS_PIN pin: SD Card CS pin

< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin

< SD_SPI disable

< DeInitializes the SD_SPI

< SD_SPI Periph clock disable

< Configure SD_SPI pins: SCK

< Configure SD_SPI pins: MISO

< Configure SD_SPI pins: MOSI

< Configure SD_SPI_CS_PIN pin: SD Card CS pin

< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin

< SD_SPI disable

< DeInitializes the SD_SPI

< SD_SPI Periph clock disable

< Configure SD_SPI pins: SCK

< Configure SD_SPI pins: MISO

< Configure SD_SPI pins: MOSI

< Configure SD_SPI_CS_PIN pin: SD Card CS pin

< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin

< SD_SPI disable

< DeInitializes the SD_SPI

< SD_SPI Periph clock disable

< DeRemap SPI3 Pins

< Configure SD_SPI pins: SCK

< Configure SD_SPI pins: MISO

< Configure SD_SPI pins: MOSI

< Configure SD_SPI_CS_PIN pin: SD Card CS pin

< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin

< Disable SDIO Clock

< Set Power State to OFF

< DeInitializes the SDIO peripheral

< Disable the SDIO AHB Clock

< Configure PC.08, PC.09, PC.10, PC.11, PC.12 pin: D0, D1, D2, D3, CLK pin

< Configure PD.02 CMD line

< SD_SPI disable

< DeInitializes the SD_SPI

< SD_SPI Periph clock disable

< Configure SD_SPI pins: SCK

< Configure SD_SPI pins: MISO

< Configure SD_SPI pins: MOSI

< Configure SD_SPI_CS_PIN pin: SD Card CS pin

< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin

Definition at line 373 of file stm32100b_eval.c.

void SD_LowLevel_Init ( void )

Initializes the SD_SPI and CS pins.

Parameters:
None
Return values:
None Initializes the SD_SPI and CS pins.
Parameters:
None
Return values:
None

< SD_SPI_CS_GPIO, SD_SPI_MOSI_GPIO, SD_SPI_MISO_GPIO, SD_SPI_DETECT_GPIO and SD_SPI_SCK_GPIO Periph clock enable

< SD_SPI Periph clock enable

< Configure SD_SPI pins: SCK

< Configure SD_SPI pins: MOSI

< Configure SD_SPI pins: MISO

< Configure SD_SPI_CS_PIN pin: SD Card CS pin

< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin

< SD_SPI Config

< SD_SPI enable

< SD_SPI_CS_GPIO, SD_SPI_MOSI_GPIO, SD_SPI_MISO_GPIO, SD_SPI_DETECT_GPIO and SD_SPI_SCK_GPIO Periph clock enable

< SD_SPI Periph clock enable

< Configure SD_SPI pins: SCK

< Configure SD_SPI pins: MOSI

< Configure SD_SPI pins: MISO

< Configure SD_SPI_CS_PIN pin: SD Card CS pin

< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin

< SD_SPI Config

< SD_SPI enable

< SD_SPI_CS_GPIO, SD_SPI_MOSI_GPIO, SD_SPI_MISO_GPIO, SD_SPI_DETECT_GPIO and SD_SPI_SCK_GPIO Periph clock enable

< SD_SPI Periph clock enable

< Configure SD_SPI pins: SCK

< Configure SD_SPI pins: MOSI

< Configure SD_SPI pins: MISO

< Configure SD_SPI_CS_PIN pin: SD Card CS pin

< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin

< SD_SPI Config

< SD_SPI enable

< SD_SPI_CS_GPIO, SD_SPI_MOSI_GPIO, SD_SPI_MISO_GPIO, SD_SPI_DETECT_GPIO and SD_SPI_SCK_GPIO Periph clock enable

< SD_SPI Periph clock enable

< AFIO Periph clock enable

< Remap SPI3 Pins

< Configure SD_SPI pins: SCK

< Configure SD_SPI pins: MOSI

< Configure SD_SPI pins: MISO

< Configure SD_SPI_CS_PIN pin: SD Card CS pin

< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin

< SD_SPI Config

< SD_SPI enable

< GPIOC and GPIOD Periph clock enable

< Configure PC.08, PC.09, PC.10, PC.11, PC.12 pin: D0, D1, D2, D3, CLK pin

< Configure PD.02 CMD line

< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin

< Enable the SDIO AHB Clock

< Enable the DMA2 Clock

< SD_SPI_CS_GPIO, SD_SPI_MOSI_GPIO, SD_SPI_MISO_GPIO, SD_SPI_DETECT_GPIO and SD_SPI_SCK_GPIO Periph clock enable

< SD_SPI Periph clock enable

< Configure SD_SPI pins: SCK

< Configure SD_SPI pins: MISO

< Configure SD_SPI pins: MOSI

< Configure SD_SPI_CS_PIN pin: SD Card CS pin

< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin

< SD_SPI Config

< SD_SPI enable

Definition at line 410 of file stm32100b_eval.c.

void sFLASH_LowLevel_DeInit ( void )

DeInitializes the peripherals used by the SPI FLASH driver.

Parameters:
None
Return values:
None

< Disable the sFLASH_SPI

< DeInitializes the sFLASH_SPI

< sFLASH_SPI Periph clock disable

< Configure sFLASH_SPI pins: SCK

< Configure sFLASH_SPI pins: MISO

< Configure sFLASH_SPI pins: MOSI

< Configure sFLASH_CS_PIN pin: sFLASH Card CS pin

< Disable the sFLASH_SPI

< DeInitializes the sFLASH_SPI

< sFLASH_SPI Periph clock disable

< Configure sFLASH_SPI pins: SCK

< Configure sFLASH_SPI pins: MISO

< Configure sFLASH_SPI pins: MOSI

< Configure sFLASH_CS_PIN pin: sFLASH Card CS pin

< Disable the sFLASH_SPI

< DeInitializes the sFLASH_SPI

< sFLASH_SPI Periph clock disable

< Configure sFLASH_SPI pins: SCK

< Configure sFLASH_SPI pins: MISO

< Configure sFLASH_SPI pins: MOSI

< Configure sFLASH_CS_PIN pin: sFLASH Card CS pin

< Disable the sFLASH_SPI

< DeInitializes the sFLASH_SPI

< sFLASH_SPI Periph clock disable

< Configure sFLASH_SPI pins: SCK

< Configure sFLASH_SPI pins: MISO

< Configure sFLASH_SPI pins: MOSI

< Configure sFLASH_CS_PIN pin: sFLASH Card CS pin

Definition at line 470 of file stm32100b_eval.c.

void sFLASH_LowLevel_Init ( void )

Initializes the peripherals used by the SPI FLASH driver.

Parameters:
None
Return values:
None

< sFLASH_SPI_CS_GPIO, sFLASH_SPI_MOSI_GPIO, sFLASH_SPI_MISO_GPIO and sFLASH_SPI_SCK_GPIO Periph clock enable

< sFLASH_SPI Periph clock enable

< Configure sFLASH_SPI pins: SCK

< Configure sFLASH_SPI pins: MOSI

< Configure sFLASH_SPI pins: MISO

< Configure sFLASH_CS_PIN pin: sFLASH Card CS pin

< sFLASH_SPI_CS_GPIO, sFLASH_SPI_MOSI_GPIO, sFLASH_SPI_MISO_GPIO and sFLASH_SPI_SCK_GPIO Periph clock enable

< sFLASH_SPI Periph clock enable

< Configure sFLASH_SPI pins: SCK

< Configure sFLASH_SPI pins: MOSI

< Configure sFLASH_SPI pins: MISO

< Configure sFLASH_CS_PIN pin: sFLASH Card CS pin

< sFLASH_SPI_CS_GPIO, sFLASH_SPI_MOSI_GPIO, sFLASH_SPI_MISO_GPIO and sFLASH_SPI_SCK_GPIO Periph clock enable

< sFLASH_SPI Periph clock enable

< Configure sFLASH_SPI pins: SCK

< Configure sFLASH_SPI pins: MOSI

< Configure sFLASH_SPI pins: MISO

< Configure sFLASH_CS_PIN pin: sFLASH Card CS pin

< sFLASH_SPI_CS_GPIO, sFLASH_SPI_MOSI_GPIO, sFLASH_SPI_MISO_GPIO and sFLASH_SPI_SCK_GPIO Periph clock enable

< sFLASH_SPI Periph clock enable

< Configure sFLASH_SPI pins: SCK

< Configure sFLASH_SPI pins: MOSI

< Configure sFLASH_SPI pins: MISO

< Configure sFLASH_CS_PIN pin: sFLASH Card CS pin

Definition at line 506 of file stm32100b_eval.c.

void STM_EVAL_COMInit | ( | COM_TypeDef | COM,
 |  | USART_InitTypeDef * | USART_InitStruct
 | ) |  |

Configures COM port.

Parameters:
COM,: Specifies the COM port to be configured. This parameter can be one of following parameters:

  • COM1
  • COM2
USART_InitStruct,: pointer to a USART_InitTypeDef structure that contains the configuration information for the specified USART peripheral.
Return values:
None

Definition at line 330 of file stm32100b_eval.c.

void STM_EVAL_LEDInit ( Led_TypeDef Led )

Configures LED GPIO.

Parameters:
Led,: Specifies the Led to be configured. This parameter can be one of following parameters:

  • LED1
  • LED2
  • LED3
  • LED4
Return values:
None

Definition at line 176 of file stm32100b_eval.c.

void STM_EVAL_LEDOff ( Led_TypeDef Led )

Turns selected LED Off.

Parameters:
Led,: Specifies the Led to be set off. This parameter can be one of following parameters:

  • LED1
  • LED2
  • LED3
  • LED4
Return values:
None

Definition at line 216 of file stm32100b_eval.c.

void STM_EVAL_LEDOn ( Led_TypeDef Led )

Turns selected LED On.

Parameters:
Led,: Specifies the Led to be set on. This parameter can be one of following parameters:

  • LED1
  • LED2
  • LED3
  • LED4
Return values:
None

Definition at line 201 of file stm32100b_eval.c.

void STM_EVAL_LEDToggle ( Led_TypeDef Led )

Toggles the selected LED.

Parameters:
Led,: Specifies the Led to be toggled. This parameter can be one of following parameters:

  • LED1
  • LED2
  • LED3
  • LED4
Return values:
None

Definition at line 231 of file stm32100b_eval.c.

uint32_t STM_EVAL_PBGetState ( Button_TypeDef Button )

Returns the selected Button state.

Parameters:
Button,: Specifies the Button to be checked. This parameter can be one of following parameters:

  • BUTTON_WAKEUP: Wakeup Push Button
  • BUTTON_TAMPER: Tamper Push Button
  • BUTTON_KEY: Key Push Button
  • BUTTON_RIGHT: Joystick Right Push Button
  • BUTTON_LEFT: Joystick Left Push Button
  • BUTTON_UP: Joystick Up Push Button
  • BUTTON_DOWN: Joystick Down Push Button
  • BUTTON_SEL: Joystick Sel Push Button
Return values:
The Button GPIO pin value.
Parameters:
Button,: Specifies the Button to be checked. This parameter can be one of following parameters:

  • BUTTON_KEY: Key Push Button
  • BUTTON_RIGHT: Joystick Right Push Button
  • BUTTON_LEFT: Joystick Left Push Button
  • BUTTON_UP: Joystick Up Push Button
  • BUTTON_DOWN: Joystick Down Push Button
  • BUTTON_SEL: Joystick Sel Push Button
Return values:
- When Button > 1, the Button GPIO pin value is returned.

  • When Button = 0 or 1, error code (0xFF) is returned.

Definition at line 314 of file stm32100b_eval.c.

void STM_EVAL_PBInit | ( | Button_TypeDef | Button,
 |  | ButtonMode_TypeDef | Button_Mode
 | ) |  |

Configures Button GPIO and EXTI Line.

Parameters:
Button,: Specifies the Button to be configured. This parameter can be one of following parameters:

  • BUTTON_WAKEUP: Wakeup Push Button
  • BUTTON_TAMPER: Tamper Push Button
  • BUTTON_KEY: Key Push Button
  • BUTTON_RIGHT: Joystick Right Push Button
  • BUTTON_LEFT: Joystick Left Push Button
  • BUTTON_UP: Joystick Up Push Button
  • BUTTON_DOWN: Joystick Down Push Button
  • BUTTON_SEL: Joystick Sel Push Button
Button_Mode,: Specifies Button mode. This parameter can be one of following parameters:

  • BUTTON_MODE_GPIO: Button will be used as simple IO
  • BUTTON_MODE_EXTI: Button will be connected to EXTI line with interrupt generation capability
Return values:
None
Parameters:
Button,: Specifies the Button to be configured. This parameter can be one of following parameters:

  • BUTTON_KEY: Key Push Button
  • BUTTON_RIGHT: Joystick Right Push Button
  • BUTTON_LEFT: Joystick Left Push Button
  • BUTTON_UP: Joystick Up Push Button
  • BUTTON_DOWN: Joystick Down Push Button
  • BUTTON_SEL: Joystick Sel Push Button
Button_Mode,: Specifies Button mode. This parameter can be one of following parameters:

  • BUTTON_MODE_GPIO: Button will be used as simple IO
  • BUTTON_MODE_EXTI: Button will be connected to EXTI line with interrupt generation capability
Return values:
None

Definition at line 255 of file stm32100b_eval.c.


STM32F10x Standard Peripherals Firmware Library: STM32100B_EVAL_CEC_Private_Types

STM32100B_EVAL_CEC_Private_Types

STM32100B_EVAL_CEC


STM32F10x Standard Peripherals Firmware Library: STM32100B_EVAL_CEC_Private_Defines

STM32100B_EVAL_CEC_Private_Defines

STM32100B_EVAL_CEC


STM32F10x Standard Peripherals Firmware Library: STM32100B_EVAL_CEC_Private_Macros

STM32100B_EVAL_CEC_Private_Macros

STM32100B_EVAL_CEC


STM32F10x Standard Peripherals Firmware Library: STM32100B_EVAL_CEC_Private_Variables

Variables

STM32100B_EVAL_CEC_Private_Variables

STM32100B_EVAL_CEC

Variables

__IO uint8_t | AbortReason = 0
__IO uint32_t | BufferCount = 0
__IO uint8_t | BufferPointer [15]
__IO uint8_t | CECDevicesNumber = 0
__IO uint8_t | DeviceCount = 0
__IO uint8_t | DeviceType = 0
__IO uint8_t | FeatureOpcode = 0
HDMI_CEC_Map | HDMI_CEC_DeviceMap [14]
uint8_t * | HDMI_CEC_Follower_String [13][2]
HDMI_CEC_Map HDMI_CEC_MapStruct
HDMI_CEC_Message HDMI_CEC_RX_MessageStructPrivate
HDMI_CEC_Message HDMI_CEC_TX_MessageStructPrivate
HDMI_CEC_Message HDMI_CEC_TX_MessageStructure
__IO uint8_t | MyLogicalAddress = 0
__IO uint16_t | MyPhysicalAddress = 0
__IO uint32_t | ReceivedFrame = 0
__IO uint32_t | ReceiveStatus = 0
__IO uint8_t | RecepErrorCode = 0
__IO uint32_t | RxCounter = 0
__IO uint32_t | SendFrame = 0
__IO uint32_t | SendStatus = 0
__IO uint8_t | TransErrorCode = 0
__IO uint32_t | TxCounter = 0

Variable Documentation

__IO uint8_t AbortReason = 0

Definition at line 93 of file stm32100b_eval_cec.c.

Referenced by HDMI_CEC_CommandCallBack().

__IO uint32_t BufferCount = 0

Definition at line 73 of file stm32100b_eval_cec.c.

Referenced by HDMI_CEC_TransmitMessage().

__IO uint8_t BufferPointer[15]

Definition at line 74 of file stm32100b_eval_cec.c.

Referenced by HDMI_CEC_ProcessIRQSrc(), and HDMI_CEC_TransmitMessage().

__IO uint8_t CECDevicesNumber = 0

Definition at line 86 of file stm32100b_eval_cec.c.

Referenced by HDMI_CEC_CheckConnectedDevices().

__IO uint8_t DeviceCount = 0

Definition at line 94 of file stm32100b_eval_cec.c.

Referenced by HDMI_CEC_CommandCallBack().

__IO uint8_t DeviceType = 0

Definition at line 81 of file stm32100b_eval_cec.c.

Referenced by HDMI_CEC_ReportPhysicalAddress(), and LogicalAddressAllocation().

__IO uint8_t FeatureOpcode = 0

Definition at line 92 of file stm32100b_eval_cec.c.

Referenced by HDMI_CEC_CommandCallBack().

HDMI_CEC_Map HDMI_CEC_DeviceMap[14]

Definition at line 97 of file stm32100b_eval_cec.c.

uint8_t* HDMI_CEC_Follower_String[13][2]
Initial value:
  {
    {(uint8_t *)"         TV         ", (uint8_t *)"0"},
    {(uint8_t *)"Recording Device 1  ", (uint8_t *)"0"},
    {(uint8_t *)"Recording Device 2  ", (uint8_t *)"0"},
    {(uint8_t *)"    Tuner 1         ", (uint8_t *)"0"},
    {(uint8_t *)" Playback Device 1  ", (uint8_t *)"0"},
    {(uint8_t *)"   Audio System     ", (uint8_t *)"0"},
    {(uint8_t *)"    Tuner 2         ", (uint8_t *)"0"},
    {(uint8_t *)"    Tuner 3         ", (uint8_t *)"0"},
    {(uint8_t *)" Playback Device 2  ", (uint8_t *)"0"},
    {(uint8_t *)"Recording Device 3  ", (uint8_t *)"0"},
    {(uint8_t *)"      Tuner 4       ", (uint8_t *)"0"},
    {(uint8_t *)" Playback Device 3  ", (uint8_t *)"0"},
    {(uint8_t *)"     Broadcast      ", (uint8_t *)"1"}
  }

Definition at line 100 of file stm32100b_eval_cec.c.

Referenced by HDMI_CEC_CheckConnectedDevices(), and HDMI_CEC_CommandCallBack().

HDMI_CEC_Map HDMI_CEC_MapStruct

Definition at line 96 of file stm32100b_eval_cec.c.

Referenced by HDMI_CEC_CommandCallBack().

HDMI_CEC_Message HDMI_CEC_RX_MessageStructPrivate

Definition at line 89 of file stm32100b_eval_cec.c.

HDMI_CEC_Message HDMI_CEC_TX_MessageStructPrivate

Definition at line 88 of file stm32100b_eval_cec.c.

HDMI_CEC_Message HDMI_CEC_TX_MessageStructure

Definition at line 90 of file stm32100b_eval_cec.c.

Referenced by HDMI_CEC_TransmitMessage().

__IO uint8_t MyLogicalAddress = 0

Definition at line 79 of file stm32100b_eval_cec.c.

Referenced by HDMI_CEC_CheckConnectedDevices(), HDMI_CEC_CommandCallBack(), HDMI_CEC_Init(), HDMI_CEC_ReportPhysicalAddress(), and LogicalAddressAllocation().

__IO uint16_t MyPhysicalAddress = 0

Definition at line 80 of file stm32100b_eval_cec.c.

Referenced by HDMI_CEC_ReportPhysicalAddress(), and PhysicalAddressDiscovery().

__IO uint32_t ReceivedFrame = 0

Definition at line 71 of file stm32100b_eval_cec.c.

__IO uint32_t ReceiveStatus = 0

Definition at line 75 of file stm32100b_eval_cec.c.

Referenced by HDMI_CEC_ProcessIRQSrc().

__IO uint8_t RecepErrorCode = 0

Definition at line 78 of file stm32100b_eval_cec.c.

__IO uint32_t RxCounter = 0

Definition at line 73 of file stm32100b_eval_cec.c.

__IO uint32_t SendFrame = 0

Definition at line 72 of file stm32100b_eval_cec.c.

Referenced by HDMI_CEC_ProcessIRQSrc(), and HDMI_CEC_TransmitMessage().

__IO uint32_t SendStatus = 0

Definition at line 76 of file stm32100b_eval_cec.c.

Referenced by HDMI_CEC_ProcessIRQSrc(), and HDMI_CEC_TransmitMessage().

__IO uint8_t TransErrorCode = 0

Definition at line 77 of file stm32100b_eval_cec.c.

__IO uint32_t TxCounter = 0

Definition at line 73 of file stm32100b_eval_cec.c.


STM32F10x Standard Peripherals Firmware Library: STM32100B_EVAL_CEC_Private_Function_Prototypes

STM32100B_EVAL_CEC_Private_Function_Prototypes

STM32100B_EVAL_CEC


STM32F10x Standard Peripherals Firmware Library: STM32100B_EVAL_CEC_Private_Functions

Functions

STM32100B_EVAL_CEC_Private_Functions

STM32100B_EVAL_CEC

Functions

HDMI_CEC_Error | HDMI_CEC_CheckConnectedDevices (void)
Check the connected CEC devices.
void | HDMI_CEC_CommandCallBack (void)
Handle CEC command receive callback.
HDMI_CEC_Error | HDMI_CEC_GetErrorStatus (void)
Get the ESR register status.
HDMI_CEC_Error | HDMI_CEC_Init (void)
Initializes the HDMI CEC.
void | HDMI_CEC_ProcessIRQSrc (void)
Allows to process all the interrupts that are high.
HDMI_CEC_Error | HDMI_CEC_ReportPhysicalAddress (void)
Report physical address to all other devices thus allowing any device to create a map of the network.
HDMI_CEC_Error HDMI_CEC_TransmitMessage (HDMI_CEC_Message *HDMI_CEC_TX_MessageStructure)
Transmit message by taking data from typedef struct CEC_Meassage.
static HDMI_CEC_Error | LogicalAddressAllocation (void)
Allocate the logical address.
static HDMI_CEC_Error | PhysicalAddressDiscovery (void)
Physical address discovery.

Function Documentation

HDMI_CEC_Error HDMI_CEC_CheckConnectedDevices ( void )

Check the connected CEC devices.

Parameters:
None
Return values:
HDMI_CEC_Error

Definition at line 671 of file stm32100b_eval_cec.c.

Referenced by HDMI_CEC_Init().

void HDMI_CEC_CommandCallBack ( void )

Handle CEC command receive callback.

When receiving the STANDBY Opcode commande, the system is entred in Stop mode and when wakeup, the PLL is configured as system clock and the HSI is selected as PLL source.

Parameters:
None
Return values:
None

Definition at line 510 of file stm32100b_eval_cec.c.

HDMI_CEC_Error HDMI_CEC_GetErrorStatus ( void )

Get the ESR register status.

Parameters:
None
Return values:
HDMI_CEC_Error,: CEC Error code

Definition at line 343 of file stm32100b_eval_cec.c.

Referenced by HDMI_CEC_CheckConnectedDevices(), HDMI_CEC_ProcessIRQSrc(), and LogicalAddressAllocation().

HDMI_CEC_Error HDMI_CEC_Init ( void )

Initializes the HDMI CEC.

Parameters:
None
Return values:
HDMI_CEC_Error,: CEC Error code

Definition at line 143 of file stm32100b_eval_cec.c.

void HDMI_CEC_ProcessIRQSrc ( void )

Allows to process all the interrupts that are high.

Parameters:
None
Return values:
None

Definition at line 393 of file stm32100b_eval_cec.c.

HDMI_CEC_Error HDMI_CEC_ReportPhysicalAddress ( void )

Report physical address to all other devices thus allowing any device to create a map of the network.

Parameters:
None
Return values:
HDMI_CEC_Error,: CEC Error code.

Definition at line 485 of file stm32100b_eval_cec.c.

Referenced by HDMI_CEC_CommandCallBack(), and HDMI_CEC_Init().

HDMI_CEC_Error HDMI_CEC_TransmitMessage ( HDMI_CEC_Message * HDMI_CEC_TX_MessageStructure )

Transmit message by taking data from typedef struct CEC_Meassage.

Parameters:
CEC_TX_MessageStructure,: pointer to an CEC_Message structure that contains the message to be sent.
Return values:
HDMI_CEC_Error,: CEC Error code

Definition at line 286 of file stm32100b_eval_cec.c.

Referenced by HDMI_CEC_CommandCallBack(), and HDMI_CEC_ReportPhysicalAddress().

static HDMI_CEC_Error LogicalAddressAllocation ( void ) [static]

Allocate the logical address.

Parameters:
None
Return values:
HDMI_CEC_Error,: CEC Error code.

Definition at line 1211 of file stm32100b_eval_cec.c.

References CEC_ClearFlag(), CEC_EndOfMessageCmd(), CEC_FLAG_TBTRF, CEC_FLAG_TERR, CEC_GetFlagStatus(), CEC_OwnAddressConfig(), CEC_SendDataByte(), CEC_StartOfMessage(), DeviceType, DISABLE, ENABLE, HDMI_CEC_AUDIOSYSTEM, HDMI_CEC_BLOCK_ACKNOWLEDGE, HDMI_CEC_DEVICE_UNREGISTRED, HDMI_CEC_GetErrorStatus(), HDMI_CEC_OK, HDMI_CEC_PLAYBACK, HDMI_CEC_RECORDING, HDMI_CEC_ROOT, HDMI_CEC_TIMEOUT, HDMI_CEC_TIMEOUT_VALUE, HDMI_CEC_TUNER, HDMI_CEC_TV, MyLogicalAddress, and RESET.

Referenced by HDMI_CEC_Init().

static HDMI_CEC_Error PhysicalAddressDiscovery ( void ) [static]

Physical address discovery.

Parameters:
None
Return values:
HDMI_CEC_Error,: CEC Error code.

Definition at line 1093 of file stm32100b_eval_cec.c.

References DISABLE, ENABLE, GPIO_ReadInputDataBit(), HDMI_CEC_HPD_GPIO_PORT, HDMI_CEC_HPD_PIN, HDMI_CEC_I2C, HDMI_CEC_OK, HDMI_CEC_ROOT, I2C_AcknowledgeConfig(), I2C_CheckEvent(), I2C_Direction_Receiver, I2C_Direction_Transmitter, I2C_EVENT_MASTER_BYTE_RECEIVED, I2C_EVENT_MASTER_BYTE_TRANSMITTED, I2C_EVENT_MASTER_MODE_SELECT, I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED, I2C_FLAG_BUSY, I2C_GenerateSTART(), I2C_GenerateSTOP(), I2C_GetFlagStatus(), I2C_ReceiveData(), I2C_Send7bitAddress(), I2C_SendData(), index, MyPhysicalAddress, and RESET.

Referenced by HDMI_CEC_Init().


STM32F10x Standard Peripherals Firmware Library: STM32100B_EVAL_CEC_Exported_Types

Data Structures | Defines | Enumerations

STM32100B_EVAL_CEC_Exported_Types

STM32100B_EVAL_CEC

Data Structures

struct | HDMI_CEC_Map
struct | HDMI_CEC_Message
CEC Init Structure definition. More...

Defines

#define | HDMI_CEC_TIMEOUT_VALUE ((uint32_t)0x001FFFFF)
#define | HDMI_CEC_TX_MESSAGE_LENGTH_MAX ((uint32_t)0x0000000E)

Enumerations

enum HDMI_CEC_Error {
HDMI_CEC_BIT_TIMING = (1), HDMI_CEC_BIT_PERIOD = (2), HDMI_CEC_RX_BLOCK_FINISHED = (3), HDMI_CEC_START_BIT = (4),
HDMI_CEC_BLOCK_ACKNOWLEDGE = (5), HDMI_CEC_LINE = (6), HDMI_CEC_TX_BLOCK_FINISHED = (7), HDMI_CEC_DEVICE_UNREGISTRED = (8),
HDMI_CEC_TIMEOUT = (9), HDMI_CEC_OK = (10), HDMI_CEC_BIT_TIMING = (1), HDMI_CEC_BIT_PERIOD = (2),
HDMI_CEC_RX_BLOCK_FINISHED = (3), HDMI_CEC_START_BIT = (4), HDMI_CEC_BLOCK_ACKNOWLEDGE = (5), HDMI_CEC_LINE = (6),
HDMI_CEC_TX_BLOCK_FINISHED = (7), HDMI_CEC_DEVICE_UNREGISTRED = (8), HDMI_CEC_TIMEOUT = (9), HDMI_CEC_OK = (10)
}

Define Documentation

#define HDMI_CEC_TIMEOUT_VALUE ((uint32_t)0x001FFFFF)

Definition at line 80 of file stm32100b_eval_cec.h.

Referenced by HDMI_CEC_CheckConnectedDevices(), HDMI_CEC_TransmitMessage(), and LogicalAddressAllocation().

#define HDMI_CEC_TX_MESSAGE_LENGTH_MAX ((uint32_t)0x0000000E)

Definition at line 79 of file stm32100b_eval_cec.h.

Enumeration Type Documentation

enum HDMI_CEC_Error
Enumerator:
HDMI_CEC_BIT_TIMING

CEC Bit Timing Error

HDMI_CEC_BIT_PERIOD

CEC Bit Period Error

HDMI_CEC_RX_BLOCK_FINISHED

CEC Receive Block finished Error

HDMI_CEC_START_BIT

CEC Start Bit Error

HDMI_CEC_BLOCK_ACKNOWLEDGE

CEC Block Acknowledge Error

HDMI_CEC_LINE

CEC Line Error

HDMI_CEC_TX_BLOCK_FINISHED

CEC Transmit Block Transfer finished Error

HDMI_CEC_DEVICE_UNREGISTRED

CEC Device Unregistred

HDMI_CEC_TIMEOUT

CEC TimeOut

HDMI_CEC_OK

CEC OK

HDMI_CEC_BIT_TIMING

CEC Bit Timing Error

HDMI_CEC_BIT_PERIOD

CEC Bit Period Error

HDMI_CEC_RX_BLOCK_FINISHED

CEC Receive Block finished Error

HDMI_CEC_START_BIT

CEC Start Bit Error

HDMI_CEC_BLOCK_ACKNOWLEDGE

CEC Block Acknowledge Error

HDMI_CEC_LINE

CEC Line Error

HDMI_CEC_TX_BLOCK_FINISHED

CEC Transmit Block Transfer finished Error

HDMI_CEC_DEVICE_UNREGISTRED

CEC Device Unregistred

HDMI_CEC_TIMEOUT

CEC TimeOut

HDMI_CEC_OK

CEC OK

Definition at line 54 of file stm32100b_eval_cec.h.


STM32F10x Standard Peripherals Firmware Library: HDMI_CEC_Map Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

HDMI_CEC_Map Struct Reference
STM32100B_EVAL_CEC_Exported_Types | STM32100E_EVAL_CEC_Exported_Types

#include <stm32100b_eval_cec.h>

Data Fields

__IO uint8_t | DeviceType
__IO uint8_t | LogicalAddress
__IO uint8_t | PhysicalAddress_A
__IO uint8_t | PhysicalAddress_B
__IO uint8_t | PhysicalAddress_C
__IO uint8_t | PhysicalAddress_D

Detailed Description

Definition at line 68 of file stm32100b_eval_cec.h.

Field Documentation

__IO uint8_t HDMI_CEC_Map::DeviceType

Definition at line 75 of file stm32100b_eval_cec.h.

Referenced by HDMI_CEC_CommandCallBack().

__IO uint8_t HDMI_CEC_Map::LogicalAddress

Definition at line 74 of file stm32100b_eval_cec.h.

Referenced by HDMI_CEC_CommandCallBack().

__IO uint8_t HDMI_CEC_Map::PhysicalAddress_A

Definition at line 70 of file stm32100b_eval_cec.h.

Referenced by HDMI_CEC_CommandCallBack().

__IO uint8_t HDMI_CEC_Map::PhysicalAddress_B

Definition at line 71 of file stm32100b_eval_cec.h.

Referenced by HDMI_CEC_CommandCallBack().

__IO uint8_t HDMI_CEC_Map::PhysicalAddress_C

Definition at line 72 of file stm32100b_eval_cec.h.

Referenced by HDMI_CEC_CommandCallBack().

__IO uint8_t HDMI_CEC_Map::PhysicalAddress_D

Definition at line 73 of file stm32100b_eval_cec.h.

Referenced by HDMI_CEC_CommandCallBack().

The documentation for this struct was generated from the following files:
  • stm32100b_eval_cec.h
  • stm32100e_eval_cec.h


STM32F10x Standard Peripherals Firmware Library: HDMI_CEC_Message Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

HDMI_CEC_Message Struct Reference
STM32100B_EVAL_CEC_Exported_Types | STM32100E_EVAL_CEC_Exported_Types

CEC Init Structure definition. More...

#include <stm32100b_eval_cec.h>

Data Fields

__IO uint8_t | Header
__IO uint8_t | Opcode
__IO uint8_t | Operande [HDMI_CEC_TX_MESSAGE_LENGTH_MAX]
__IO uint8_t | RxMessageLength
__IO uint8_t | TxMessageLength

Detailed Description

CEC Init Structure definition.

Definition at line 85 of file stm32100b_eval_cec.h.

Field Documentation

__IO uint8_t HDMI_CEC_Message::Header

Definition at line 87 of file stm32100b_eval_cec.h.

Referenced by HDMI_CEC_CommandCallBack(), HDMI_CEC_ProcessIRQSrc(), HDMI_CEC_ReportPhysicalAddress(), and HDMI_CEC_TransmitMessage().

__IO uint8_t HDMI_CEC_Message::Opcode

Definition at line 88 of file stm32100b_eval_cec.h.

Referenced by HDMI_CEC_CommandCallBack(), HDMI_CEC_ProcessIRQSrc(), HDMI_CEC_ReportPhysicalAddress(), and HDMI_CEC_TransmitMessage().

__IO uint8_t HDMI_CEC_Message::Operande

Definition at line 89 of file stm32100b_eval_cec.h.

Referenced by HDMI_CEC_CommandCallBack(), HDMI_CEC_ProcessIRQSrc(), HDMI_CEC_ReportPhysicalAddress(), and HDMI_CEC_TransmitMessage().

__IO uint8_t HDMI_CEC_Message::RxMessageLength

Definition at line 91 of file stm32100b_eval_cec.h.

Referenced by HDMI_CEC_ProcessIRQSrc().

__IO uint8_t HDMI_CEC_Message::TxMessageLength

Definition at line 90 of file stm32100b_eval_cec.h.

Referenced by HDMI_CEC_CommandCallBack(), HDMI_CEC_ProcessIRQSrc(), HDMI_CEC_ReportPhysicalAddress(), and HDMI_CEC_TransmitMessage().

The documentation for this struct was generated from the following files:
  • stm32100b_eval_cec.h
  • stm32100e_eval_cec.h


STM32F10x Standard Peripherals Firmware Library: STM32100B_EVAL_CEC_Exported_Constants

Defines

STM32100B_EVAL_CEC_Exported_Constants

STM32100B_EVAL_CEC

Defines

#define | HDMI_CEC_AUDIOSYSTEM 0x05
#define | HDMI_CEC_CANNOTPROVIDE_SOURCE 0x02
#define | HDMI_CEC_HPD_GPIO_CLK RCC_APB2Periph_GPIOB
#define | HDMI_CEC_HPD_GPIO_PORT GPIOB
#define | HDMI_CEC_HPD_PIN GPIO_Pin_12
HDMI CEC HPD (Hot Plug Detect) Interface pin.
#define | HDMI_CEC_I2C I2C2
#define | HDMI_CEC_I2C_CLK RCC_APB1Periph_I2C2
#define | HDMI_CEC_I2C_CLOCK_SPEED 100000
#define | HDMI_CEC_I2C_GPIO_CLK RCC_APB2Periph_GPIOB
#define | HDMI_CEC_I2C_GPIO_PORT GPIOB
#define | HDMI_CEC_I2C_SCL_PIN GPIO_Pin_10
HDMI CEC I2C Interface pins.
#define | HDMI_CEC_I2C_SDA_PIN GPIO_Pin_11
#define | HDMI_CEC_I2C_SLAVE_ADDRESS7 0xA0
#define | HDMI_CEC_INVALID_OPERAND 0x03
#define | HDMI_CEC_LINE_GPIO_CLK RCC_APB2Periph_GPIOB
#define | HDMI_CEC_LINE_GPIO_PORT GPIOB
#define | HDMI_CEC_LINE_PIN GPIO_Pin_8
HDMI CEC Interface pin.
#define | HDMI_CEC_NOT_CORRECT_MODETORESPOND 0x01
#define | HDMI_CEC_OPCODE_ABORT ((uint8_t) 0xFF)
#define | HDMI_CEC_OPCODE_ACTIVE_SOURCE ((uint8_t) 0x82)
HDMI CEC specific commands.
#define | HDMI_CEC_OPCODE_CEC_VERSION ((uint8_t) 0x9E)
#define | HDMI_CEC_OPCODE_CLEAR_ANALOGUE_TIMER ((uint8_t) 0x33)
#define | HDMI_CEC_OPCODE_CLEAR_DIGITAL_TIMER ((uint8_t) 0x99)
#define | HDMI_CEC_OPCODE_CLEAR_EXTERNAL_TIMER ((uint8_t) 0xA1)
#define | HDMI_CEC_OPCODE_DECK_CONTROL ((uint8_t) 0x42)
#define | HDMI_CEC_OPCODE_DECK_STATUS ((uint8_t) 0x1B)
#define | HDMI_CEC_OPCODE_DEVICE_VENDOR_ID ((uint8_t) 0x87)
#define | HDMI_CEC_OPCODE_FEATURE_ABORT ((uint8_t) 0x00)
#define | HDMI_CEC_OPCODE_GET_CEC_VERSION ((uint8_t) 0x9F)
#define | HDMI_CEC_OPCODE_GET_MENU_LANGUAGE ((uint8_t) 0x91)
#define | HDMI_CEC_OPCODE_GIVE_AUDIO_STATUS ((uint8_t) 0x71)
#define | HDMI_CEC_OPCODE_GIVE_DECK_STATUS ((uint8_t) 0x1A)
#define | HDMI_CEC_OPCODE_GIVE_DEVICE_POWER_STATUS ((uint8_t) 0x8F)
#define | HDMI_CEC_OPCODE_GIVE_DEVICE_VENDOR_ID ((uint8_t) 0x8C)
#define | HDMI_CEC_OPCODE_GIVE_OSD_NAME ((uint8_t) 0x46)
#define | HDMI_CEC_OPCODE_GIVE_PHYSICAL_ADDRESS ((uint8_t) 0x83)
#define | HDMI_CEC_OPCODE_GIVE_SYSTEM_AUDIO_MODE_STATUS ((uint8_t) 0x7D)
#define | HDMI_CEC_OPCODE_GIVE_TUNER_DEVICE_STATUS ((uint8_t) 0x08)
#define | HDMI_CEC_OPCODE_IMAGE_VIEW_ON ((uint8_t) 0x04)
#define | HDMI_CEC_OPCODE_INACTIVE_SOURCE ((uint8_t) 0x9D)
#define | HDMI_CEC_OPCODE_MENU_REQUEST ((uint8_t) 0x8D)
#define | HDMI_CEC_OPCODE_MENU_STATUS ((uint8_t) 0x8E)
#define | HDMI_CEC_OPCODE_PLAY ((uint8_t) 0x41)
#define | HDMI_CEC_OPCODE_RECORD_OFF ((uint8_t) 0x0B)
#define | HDMI_CEC_OPCODE_RECORD_ON ((uint8_t) 0x09)
#define | HDMI_CEC_OPCODE_RECORD_STATUS ((uint8_t) 0x0A)
#define | HDMI_CEC_OPCODE_RECORD_TV_SCREEN ((uint8_t) 0x0F)
#define | HDMI_CEC_OPCODE_REPORT_AUDIO_STATUS ((uint8_t) 0x7A)
#define | HDMI_CEC_OPCODE_REPORT_PHYSICAL_ADDRESS ((uint8_t) 0x84)
#define | HDMI_CEC_OPCODE_REPORT_POWER_STATUS ((uint8_t) 0x90)
#define | HDMI_CEC_OPCODE_REQUEST_ACTIVE_SOURCE ((uint8_t) 0x85)
#define | HDMI_CEC_OPCODE_ROUTING_CHANGE ((uint8_t) 0x80)
#define | HDMI_CEC_OPCODE_ROUTING_INFORMATION ((uint8_t) 0x81)
#define | HDMI_CEC_OPCODE_SELECT_ANALOGUE_SERVICE ((uint8_t) 0x92)
#define | HDMI_CEC_OPCODE_SELECT_DIGITAL_SERVICE ((uint8_t) 0x93)
#define | HDMI_CEC_OPCODE_SET_ANALOGUE_TIMER ((uint8_t) 0x34)
#define | HDMI_CEC_OPCODE_SET_AUDIO_RATE ((uint8_t) 0x9A)
#define | HDMI_CEC_OPCODE_SET_DIGITAL_TIMER ((uint8_t) 0x97)
#define | HDMI_CEC_OPCODE_SET_EXTERNAL_TIMER ((uint8_t) 0xA2)
#define | HDMI_CEC_OPCODE_SET_MENU_LANGUAGE ((uint8_t) 0x32)
#define | HDMI_CEC_OPCODE_SET_OSD_NAME ((uint8_t) 0x47)
#define | HDMI_CEC_OPCODE_SET_OSD_STRING ((uint8_t) 0x64)
#define | HDMI_CEC_OPCODE_SET_STREAM_PATH ((uint8_t) 0x86)
#define | HDMI_CEC_OPCODE_SET_SYSTEM_AUDIO_MODE ((uint8_t) 0x72)
#define | HDMI_CEC_OPCODE_SET_TIMER_PROGRAM_TITLE ((uint8_t) 0x67)
#define | HDMI_CEC_OPCODE_STANDBY ((uint8_t) 0x36)
#define | HDMI_CEC_OPCODE_SYSTEM_AUDIO_MODE_REQUEST ((uint8_t) 0x70)
#define | HDMI_CEC_OPCODE_SYSTEM_AUDIO_MODE_STATUS ((uint8_t) 0x7E)
#define | HDMI_CEC_OPCODE_TEXT_VIEW_ON ((uint8_t) 0x0D)
#define | HDMI_CEC_OPCODE_TIMER_CLEARED_STATUS ((uint8_t) 0x43)
#define | HDMI_CEC_OPCODE_TIMER_STATUS ((uint8_t) 0x35)
#define | HDMI_CEC_OPCODE_TUNER_DEVICE_STATUS ((uint8_t) 0x07)
#define | HDMI_CEC_OPCODE_TUNER_STEP_DECREMENT ((uint8_t) 0x06)
#define | HDMI_CEC_OPCODE_TUNER_STEP_INCREMENT ((uint8_t) 0x05)
#define | HDMI_CEC_OPCODE_USER_CONTROL_PRESSED ((uint8_t) 0x44)
#define | HDMI_CEC_OPCODE_USER_CONTROL_RELEASED ((uint8_t) 0x45)
#define | HDMI_CEC_OPCODE_VENDOR_COMMAND ((uint8_t) 0x89)
#define | HDMI_CEC_OPCODE_VENDOR_COMMAND_WITH_ID ((uint8_t) 0xA0)
#define | HDMI_CEC_OPCODE_VENDOR_REMOTE_BUTTON_DOWN ((uint8_t) 0x8A)
#define | HDMI_CEC_OPCODE_VENDOR_REMOTE_BUTTON_UP ((uint8_t) 0x8B)
#define | HDMI_CEC_PLAYBACK 0x04
#define | HDMI_CEC_RECORDING 0x01
#define | HDMI_CEC_REFUSED 0x04
#define | HDMI_CEC_ROOT 0x00
HDMI CEC Root (Mainly for TV with a fixed physical address (0.0.0.0)) If you want to configure the STM32100B-EVAL board as CEC Root (Sink) change the following define to 0x1.
#define | HDMI_CEC_TUNER 0x03
#define | HDMI_CEC_TV 0x00
CEC device types.
#define | HDMI_CEC_UNRECOGNIZED_OPCODE 0x00
Reason for Abort feature.
#define | HDMI_CEC_VERSION 0x04
To select if the DDC Channel will be used for physical address discovery or not.

Define Documentation

#define HDMI_CEC_AUDIOSYSTEM 0x05

Definition at line 109 of file stm32100b_eval_cec.h.

Referenced by LogicalAddressAllocation().

#define HDMI_CEC_CANNOTPROVIDE_SOURCE 0x02

Definition at line 165 of file stm32100b_eval_cec.h.

#define HDMI_CEC_HPD_GPIO_CLK RCC_APB2Periph_GPIOB

Definition at line 127 of file stm32100b_eval_cec.h.

Referenced by HDMI_CEC_Init().

#define HDMI_CEC_HPD_GPIO_PORT GPIOB

Definition at line 126 of file stm32100b_eval_cec.h.

Referenced by HDMI_CEC_Init(), and PhysicalAddressDiscovery().

#define HDMI_CEC_HPD_PIN GPIO_Pin_12

HDMI CEC HPD (Hot Plug Detect) Interface pin.

Definition at line 125 of file stm32100b_eval_cec.h.

Referenced by HDMI_CEC_Init(), and PhysicalAddressDiscovery().

#define HDMI_CEC_I2C I2C2

Definition at line 119 of file stm32100b_eval_cec.h.

Referenced by HDMI_CEC_Init(), and PhysicalAddressDiscovery().

#define HDMI_CEC_I2C_CLK RCC_APB1Periph_I2C2

Definition at line 120 of file stm32100b_eval_cec.h.

Referenced by HDMI_CEC_Init().

#define HDMI_CEC_I2C_CLOCK_SPEED 100000

Definition at line 137 of file stm32100b_eval_cec.h.

Referenced by HDMI_CEC_Init().

#define HDMI_CEC_I2C_GPIO_CLK RCC_APB2Periph_GPIOB

Definition at line 118 of file stm32100b_eval_cec.h.

Referenced by HDMI_CEC_Init().

#define HDMI_CEC_I2C_GPIO_PORT GPIOB

Definition at line 117 of file stm32100b_eval_cec.h.

Referenced by HDMI_CEC_Init().

#define HDMI_CEC_I2C_SCL_PIN GPIO_Pin_10

HDMI CEC I2C Interface pins.

Definition at line 115 of file stm32100b_eval_cec.h.

Referenced by HDMI_CEC_Init().

#define HDMI_CEC_I2C_SDA_PIN GPIO_Pin_11

Definition at line 116 of file stm32100b_eval_cec.h.

Referenced by HDMI_CEC_Init().

#define HDMI_CEC_I2C_SLAVE_ADDRESS7 0xA0

Definition at line 136 of file stm32100b_eval_cec.h.

Referenced by HDMI_CEC_Init().

#define HDMI_CEC_INVALID_OPERAND 0x03

Definition at line 166 of file stm32100b_eval_cec.h.

#define HDMI_CEC_LINE_GPIO_CLK RCC_APB2Periph_GPIOB

Definition at line 134 of file stm32100b_eval_cec.h.

Referenced by HDMI_CEC_Init().

#define HDMI_CEC_LINE_GPIO_PORT GPIOB

Definition at line 133 of file stm32100b_eval_cec.h.

Referenced by HDMI_CEC_Init().

#define HDMI_CEC_LINE_PIN GPIO_Pin_8

HDMI CEC Interface pin.

Definition at line 132 of file stm32100b_eval_cec.h.

Referenced by HDMI_CEC_Init().

#define HDMI_CEC_NOT_CORRECT_MODETORESPOND 0x01

Definition at line 164 of file stm32100b_eval_cec.h.

#define HDMI_CEC_OPCODE_ABORT ((uint8_t) 0xFF)

Definition at line 226 of file stm32100b_eval_cec.h.

#define HDMI_CEC_OPCODE_ACTIVE_SOURCE ((uint8_t) 0x82)

HDMI CEC specific commands.

Definition at line 172 of file stm32100b_eval_cec.h.

#define HDMI_CEC_OPCODE_CEC_VERSION ((uint8_t) 0x9E)

Definition at line 194 of file stm32100b_eval_cec.h.

Referenced by HDMI_CEC_CommandCallBack().

#define HDMI_CEC_OPCODE_CLEAR_ANALOGUE_TIMER ((uint8_t) 0x33)

Definition at line 185 of file stm32100b_eval_cec.h.

#define HDMI_CEC_OPCODE_CLEAR_DIGITAL_TIMER ((uint8_t) 0x99)

Definition at line 186 of file stm32100b_eval_cec.h.

#define HDMI_CEC_OPCODE_CLEAR_EXTERNAL_TIMER ((uint8_t) 0xA1)

Definition at line 187 of file stm32100b_eval_cec.h.

#define HDMI_CEC_OPCODE_DECK_CONTROL ((uint8_t) 0x42)

Definition at line 200 of file stm32100b_eval_cec.h.

#define HDMI_CEC_OPCODE_DECK_STATUS ((uint8_t) 0x1B)

Definition at line 201 of file stm32100b_eval_cec.h.

#define HDMI_CEC_OPCODE_DEVICE_VENDOR_ID ((uint8_t) 0x87)

Definition at line 210 of file stm32100b_eval_cec.h.

#define HDMI_CEC_OPCODE_FEATURE_ABORT ((uint8_t) 0x00)

Definition at line 225 of file stm32100b_eval_cec.h.

Referenced by HDMI_CEC_CommandCallBack().

#define HDMI_CEC_OPCODE_GET_CEC_VERSION ((uint8_t) 0x9F)

Definition at line 195 of file stm32100b_eval_cec.h.

Referenced by HDMI_CEC_CommandCallBack().

#define HDMI_CEC_OPCODE_GET_MENU_LANGUAGE ((uint8_t) 0x91)

Definition at line 197 of file stm32100b_eval_cec.h.

#define HDMI_CEC_OPCODE_GIVE_AUDIO_STATUS ((uint8_t) 0x71)

Definition at line 227 of file stm32100b_eval_cec.h.

#define HDMI_CEC_OPCODE_GIVE_DECK_STATUS ((uint8_t) 0x1A)

Definition at line 202 of file stm32100b_eval_cec.h.

#define HDMI_CEC_OPCODE_GIVE_DEVICE_POWER_STATUS ((uint8_t) 0x8F)

Definition at line 223 of file stm32100b_eval_cec.h.

#define HDMI_CEC_OPCODE_GIVE_DEVICE_VENDOR_ID ((uint8_t) 0x8C)

Definition at line 211 of file stm32100b_eval_cec.h.

#define HDMI_CEC_OPCODE_GIVE_OSD_NAME ((uint8_t) 0x46)

Definition at line 217 of file stm32100b_eval_cec.h.

Referenced by HDMI_CEC_CommandCallBack().

#define HDMI_CEC_OPCODE_GIVE_PHYSICAL_ADDRESS ((uint8_t) 0x83)

Definition at line 196 of file stm32100b_eval_cec.h.

Referenced by HDMI_CEC_CommandCallBack().

#define HDMI_CEC_OPCODE_GIVE_SYSTEM_AUDIO_MODE_STATUS ((uint8_t) 0x7D)

Definition at line 228 of file stm32100b_eval_cec.h.

#define HDMI_CEC_OPCODE_GIVE_TUNER_DEVICE_STATUS ((uint8_t) 0x08)

Definition at line 204 of file stm32100b_eval_cec.h.

#define HDMI_CEC_OPCODE_IMAGE_VIEW_ON ((uint8_t) 0x04)

Definition at line 173 of file stm32100b_eval_cec.h.

#define HDMI_CEC_OPCODE_INACTIVE_SOURCE ((uint8_t) 0x9D)

Definition at line 175 of file stm32100b_eval_cec.h.

#define HDMI_CEC_OPCODE_MENU_REQUEST ((uint8_t) 0x8D)

Definition at line 219 of file stm32100b_eval_cec.h.

#define HDMI_CEC_OPCODE_MENU_STATUS ((uint8_t) 0x8E)

Definition at line 220 of file stm32100b_eval_cec.h.

#define HDMI_CEC_OPCODE_PLAY ((uint8_t) 0x41)

Definition at line 203 of file stm32100b_eval_cec.h.

#define HDMI_CEC_OPCODE_RECORD_OFF ((uint8_t) 0x0B)

Definition at line 181 of file stm32100b_eval_cec.h.

#define HDMI_CEC_OPCODE_RECORD_ON ((uint8_t) 0x09)

Definition at line 182 of file stm32100b_eval_cec.h.

#define HDMI_CEC_OPCODE_RECORD_STATUS ((uint8_t) 0x0A)

Definition at line 183 of file stm32100b_eval_cec.h.

#define HDMI_CEC_OPCODE_RECORD_TV_SCREEN ((uint8_t) 0x0F)

Definition at line 184 of file stm32100b_eval_cec.h.

#define HDMI_CEC_OPCODE_REPORT_AUDIO_STATUS ((uint8_t) 0x7A)

Definition at line 229 of file stm32100b_eval_cec.h.

#define HDMI_CEC_OPCODE_REPORT_PHYSICAL_ADDRESS ((uint8_t) 0x84)

Definition at line 198 of file stm32100b_eval_cec.h.

Referenced by HDMI_CEC_CommandCallBack(), and HDMI_CEC_ReportPhysicalAddress().

#define HDMI_CEC_OPCODE_REPORT_POWER_STATUS ((uint8_t) 0x90)

Definition at line 224 of file stm32100b_eval_cec.h.

#define HDMI_CEC_OPCODE_REQUEST_ACTIVE_SOURCE ((uint8_t) 0x85)

Definition at line 176 of file stm32100b_eval_cec.h.

#define HDMI_CEC_OPCODE_ROUTING_CHANGE ((uint8_t) 0x80)

Definition at line 177 of file stm32100b_eval_cec.h.

Referenced by HDMI_CEC_CommandCallBack().

#define HDMI_CEC_OPCODE_ROUTING_INFORMATION ((uint8_t) 0x81)

Definition at line 178 of file stm32100b_eval_cec.h.

#define HDMI_CEC_OPCODE_SELECT_ANALOGUE_SERVICE ((uint8_t) 0x92)

Definition at line 205 of file stm32100b_eval_cec.h.

#define HDMI_CEC_OPCODE_SELECT_DIGITAL_SERVICE ((uint8_t) 0x93)

Definition at line 206 of file stm32100b_eval_cec.h.

#define HDMI_CEC_OPCODE_SET_ANALOGUE_TIMER ((uint8_t) 0x34)

Definition at line 188 of file stm32100b_eval_cec.h.

#define HDMI_CEC_OPCODE_SET_AUDIO_RATE ((uint8_t) 0x9A)

Definition at line 233 of file stm32100b_eval_cec.h.

#define HDMI_CEC_OPCODE_SET_DIGITAL_TIMER ((uint8_t) 0x97)

Definition at line 189 of file stm32100b_eval_cec.h.

#define HDMI_CEC_OPCODE_SET_EXTERNAL_TIMER ((uint8_t) 0xA2)

Definition at line 190 of file stm32100b_eval_cec.h.

#define HDMI_CEC_OPCODE_SET_MENU_LANGUAGE ((uint8_t) 0x32)

Definition at line 199 of file stm32100b_eval_cec.h.

#define HDMI_CEC_OPCODE_SET_OSD_NAME ((uint8_t) 0x47)

Definition at line 218 of file stm32100b_eval_cec.h.

Referenced by HDMI_CEC_CommandCallBack().

#define HDMI_CEC_OPCODE_SET_OSD_STRING ((uint8_t) 0x64)

Definition at line 216 of file stm32100b_eval_cec.h.

#define HDMI_CEC_OPCODE_SET_STREAM_PATH ((uint8_t) 0x86)

Definition at line 179 of file stm32100b_eval_cec.h.

#define HDMI_CEC_OPCODE_SET_SYSTEM_AUDIO_MODE ((uint8_t) 0x72)

Definition at line 230 of file stm32100b_eval_cec.h.

#define HDMI_CEC_OPCODE_SET_TIMER_PROGRAM_TITLE ((uint8_t) 0x67)

Definition at line 191 of file stm32100b_eval_cec.h.

#define HDMI_CEC_OPCODE_STANDBY ((uint8_t) 0x36)

Definition at line 180 of file stm32100b_eval_cec.h.

Referenced by HDMI_CEC_CommandCallBack().

#define HDMI_CEC_OPCODE_SYSTEM_AUDIO_MODE_REQUEST ((uint8_t) 0x70)

Definition at line 231 of file stm32100b_eval_cec.h.

#define HDMI_CEC_OPCODE_SYSTEM_AUDIO_MODE_STATUS ((uint8_t) 0x7E)

Definition at line 232 of file stm32100b_eval_cec.h.

#define HDMI_CEC_OPCODE_TEXT_VIEW_ON ((uint8_t) 0x0D)

Definition at line 174 of file stm32100b_eval_cec.h.

#define HDMI_CEC_OPCODE_TIMER_CLEARED_STATUS ((uint8_t) 0x43)

Definition at line 192 of file stm32100b_eval_cec.h.

#define HDMI_CEC_OPCODE_TIMER_STATUS ((uint8_t) 0x35)

Definition at line 193 of file stm32100b_eval_cec.h.

#define HDMI_CEC_OPCODE_TUNER_DEVICE_STATUS ((uint8_t) 0x07)

Definition at line 207 of file stm32100b_eval_cec.h.

#define HDMI_CEC_OPCODE_TUNER_STEP_DECREMENT ((uint8_t) 0x06)

Definition at line 208 of file stm32100b_eval_cec.h.

#define HDMI_CEC_OPCODE_TUNER_STEP_INCREMENT ((uint8_t) 0x05)

Definition at line 209 of file stm32100b_eval_cec.h.

#define HDMI_CEC_OPCODE_USER_CONTROL_PRESSED ((uint8_t) 0x44)

Definition at line 221 of file stm32100b_eval_cec.h.

#define HDMI_CEC_OPCODE_USER_CONTROL_RELEASED ((uint8_t) 0x45)

Definition at line 222 of file stm32100b_eval_cec.h.

#define HDMI_CEC_OPCODE_VENDOR_COMMAND ((uint8_t) 0x89)

Definition at line 212 of file stm32100b_eval_cec.h.

#define HDMI_CEC_OPCODE_VENDOR_COMMAND_WITH_ID ((uint8_t) 0xA0)

Definition at line 213 of file stm32100b_eval_cec.h.

#define HDMI_CEC_OPCODE_VENDOR_REMOTE_BUTTON_DOWN ((uint8_t) 0x8A)

Definition at line 214 of file stm32100b_eval_cec.h.

#define HDMI_CEC_OPCODE_VENDOR_REMOTE_BUTTON_UP ((uint8_t) 0x8B)

Definition at line 215 of file stm32100b_eval_cec.h.

#define HDMI_CEC_PLAYBACK 0x04

Definition at line 108 of file stm32100b_eval_cec.h.

Referenced by LogicalAddressAllocation().

#define HDMI_CEC_RECORDING 0x01

Definition at line 106 of file stm32100b_eval_cec.h.

Referenced by LogicalAddressAllocation().

#define HDMI_CEC_REFUSED 0x04

Definition at line 167 of file stm32100b_eval_cec.h.

Referenced by HDMI_CEC_CommandCallBack().

#define HDMI_CEC_ROOT 0x00

HDMI CEC Root (Mainly for TV with a fixed physical address (0.0.0.0)) If you want to configure the STM32100B-EVAL board as CEC Root (Sink) change the following define to 0x1.

Definition at line 144 of file stm32100b_eval_cec.h.

Referenced by LogicalAddressAllocation(), and PhysicalAddressDiscovery().

#define HDMI_CEC_TUNER 0x03

Definition at line 107 of file stm32100b_eval_cec.h.

Referenced by LogicalAddressAllocation().

#define HDMI_CEC_TV 0x00

CEC device types.

Definition at line 105 of file stm32100b_eval_cec.h.

Referenced by LogicalAddressAllocation().

#define HDMI_CEC_UNRECOGNIZED_OPCODE 0x00

Reason for Abort feature.

Definition at line 163 of file stm32100b_eval_cec.h.

#define HDMI_CEC_VERSION 0x04

To select if the DDC Channel will be used for physical address discovery or not.

To use the DDC Channel to read the EDID structure uncomment the following line. If the device is configured as HMDI source it should read his own physical address from the sink that is connected to. CEC version: V1.3a

Definition at line 158 of file stm32100b_eval_cec.h.

Referenced by HDMI_CEC_CommandCallBack().


STM32F10x Standard Peripherals Firmware Library: STM32100B_EVAL_CEC_Exported_Macros

Defines

STM32100B_EVAL_CEC_Exported_Macros

STM32100B_EVAL_CEC

Defines

#define | HDMI_CEC_HPD_HIGH() GPIO_SetBits(HDMI_CEC_HPD_GPIO_PORT, HDMI_CEC_HPD_PIN)
#define | HDMI_CEC_HPD_LOW() GPIO_ResetBits(HDMI_CEC_HPD_GPIO_PORT, HDMI_CEC_HPD_PIN)

Define Documentation

#define HDMI_CEC_HPD_HIGH ( ) GPIO_SetBits(HDMI_CEC_HPD_GPIO_PORT, HDMI_CEC_HPD_PIN)

Definition at line 246 of file stm32100b_eval_cec.h.

#define HDMI_CEC_HPD_LOW ( ) GPIO_ResetBits(HDMI_CEC_HPD_GPIO_PORT, HDMI_CEC_HPD_PIN)

Definition at line 244 of file stm32100b_eval_cec.h.


STM32F10x Standard Peripherals Firmware Library: STM32100B_EVAL_CEC_Exported_Functions

Functions

STM32100B_EVAL_CEC_Exported_Functions

STM32100B_EVAL_CEC

Functions

HDMI_CEC_Error | HDMI_CEC_CheckConnectedDevices (void)
Check the connected CEC devices.
void | HDMI_CEC_CommandCallBack (void)
Handle CEC command receive callback.
HDMI_CEC_Error | HDMI_CEC_GetErrorStatus (void)
Get the ESR register status.
HDMI_CEC_Error | HDMI_CEC_Init (void)
Initializes the HDMI CEC.
void | HDMI_CEC_ProcessIRQSrc (void)
Allows to process all the interrupts that are high.
HDMI_CEC_Error | HDMI_CEC_ReportPhysicalAddress (void)
Report physical address to all other devices thus allowing any device to create a map of the network.
HDMI_CEC_Error HDMI_CEC_TransmitMessage (HDMI_CEC_Message *HDMI_CEC_TX_MessageStructure)
Transmit message by taking data from typedef struct CEC_Meassage.

Function Documentation

HDMI_CEC_Error HDMI_CEC_CheckConnectedDevices ( void )

Check the connected CEC devices.

Parameters:
None
Return values:
HDMI_CEC_Error

Definition at line 671 of file stm32100b_eval_cec.c.

void HDMI_CEC_CommandCallBack ( void )

Handle CEC command receive callback.

When receiving the STANDBY Opcode commande, the system is entred in Stop mode and when wakeup, the PLL is configured as system clock and the HSI is selected as PLL source.

Parameters:
None
Return values:
None

Definition at line 510 of file stm32100b_eval_cec.c.

HDMI_CEC_Error HDMI_CEC_GetErrorStatus ( void )

Get the ESR register status.

Parameters:
None
Return values:
HDMI_CEC_Error,: CEC Error code

Definition at line 343 of file stm32100b_eval_cec.c.

HDMI_CEC_Error HDMI_CEC_Init ( void )

Initializes the HDMI CEC.

Parameters:
None
Return values:
HDMI_CEC_Error,: CEC Error code

Definition at line 143 of file stm32100b_eval_cec.c.

void HDMI_CEC_ProcessIRQSrc ( void )

Allows to process all the interrupts that are high.

Parameters:
None
Return values:
None

Definition at line 393 of file stm32100b_eval_cec.c.

HDMI_CEC_Error HDMI_CEC_ReportPhysicalAddress ( void )

Report physical address to all other devices thus allowing any device to create a map of the network.

Parameters:
None
Return values:
HDMI_CEC_Error,: CEC Error code.

Definition at line 485 of file stm32100b_eval_cec.c.

HDMI_CEC_Error HDMI_CEC_TransmitMessage ( HDMI_CEC_Message * HDMI_CEC_TX_MessageStructure )

Transmit message by taking data from typedef struct CEC_Meassage.

Parameters:
CEC_TX_MessageStructure,: pointer to an CEC_Message structure that contains the message to be sent.
Return values:
HDMI_CEC_Error,: CEC Error code

Definition at line 286 of file stm32100b_eval_cec.c.


STM32F10x Standard Peripherals Firmware Library: STM32100B_EVAL_LCD_Private_Types

STM32100B_EVAL_LCD_Private_Types

STM32100B_EVAL_LCD


STM32F10x Standard Peripherals Firmware Library: STM32100B_EVAL_LCD_Private_Defines

Defines

STM32100B_EVAL_LCD_Private_Defines

STM32100B_EVAL_LCD

Defines

#define | LCD_HX8312 0x8312
#define | LCD_ILI9320 0x9320
#define | LCD_READ_REG 0x03
#define | LCD_SPFD5408 0x5408
#define | LCD_WRITE_REG 0x02
#define | MAX_POLY_CORNERS 200
#define | POLY_X(Z) ((int32_t)((Points + Z)->Y))
#define | POLY_Y(Z) ((int32_t)((Points + Z)->X))
#define | READ_STATUS 0x01
#define | SET_INDEX 0x00
#define | START_BYTE 0x70

Define Documentation

#define LCD_HX8312 0x8312

Definition at line 58 of file stm32100b_eval_lcd.c.

Referenced by LCD_DisplayOff(), LCD_DisplayOn(), LCD_DrawCircle(), LCD_DrawLine(), LCD_PowerOn(), LCD_SetCursor(), LCD_SetDisplayWindow(), LCD_Setup(), LCD_SPIConfig(), LCD_WindowModeDisable(), LCD_WriteRAM(), LCD_WriteReg(), and STM32100B_LCD_Init().

#define LCD_ILI9320 0x9320

Definition at line 57 of file stm32100b_eval_lcd.c.

Referenced by LCD_Clear(), LCD_DisplayOff(), LCD_DisplayOn(), LCD_DrawChar(), LCD_DrawCircle(), LCD_DrawLine(), LCD_DrawMonoPict(), LCD_PowerOn(), LCD_SetCursor(), LCD_SetDisplayWindow(), LCD_Setup(), LCD_SPIConfig(), LCD_WindowModeDisable(), LCD_WriteRAM(), LCD_WriteReg(), and STM32100B_LCD_Init().

#define LCD_READ_REG 0x03

Definition at line 64 of file stm32100b_eval_lcd.c.

Referenced by LCD_ReadReg().

#define LCD_SPFD5408 0x5408

Definition at line 59 of file stm32100b_eval_lcd.c.

Referenced by LCD_Clear(), LCD_DisplayOff(), LCD_DisplayOn(), LCD_DrawChar(), LCD_DrawCircle(), LCD_DrawLine(), LCD_DrawMonoPict(), LCD_PowerOn(), LCD_SetCursor(), LCD_SetDisplayWindow(), LCD_Setup(), LCD_SPIConfig(), LCD_WindowModeDisable(), LCD_WriteRAM(), LCD_WriteReg(), and STM32100B_LCD_Init().

#define LCD_WRITE_REG 0x02

Definition at line 63 of file stm32100b_eval_lcd.c.

Referenced by LCD_WriteRAM_Prepare(), and LCD_WriteRegILI9320().

#define MAX_POLY_CORNERS 200

Definition at line 65 of file stm32100b_eval_lcd.c.

Referenced by LCD_FillPolyLine().

#define POLY_X ( Z ) ((int32_t)((Points + Z)->Y))

Definition at line 67 of file stm32100b_eval_lcd.c.

Referenced by LCD_FillPolyLine().

#define POLY_Y ( Z ) ((int32_t)((Points + Z)->X))

Definition at line 66 of file stm32100b_eval_lcd.c.

Referenced by LCD_FillPolyLine().

#define READ_STATUS 0x01

Definition at line 62 of file stm32100b_eval_lcd.c.

#define SET_INDEX 0x00

Definition at line 61 of file stm32100b_eval_lcd.c.

Referenced by LCD_WriteRegIndex().

#define START_BYTE 0x70

Definition at line 60 of file stm32100b_eval_lcd.c.

Referenced by LCD_ReadReg(), LCD_WriteRAM_Prepare(), LCD_WriteRegILI9320(), and LCD_WriteRegIndex().


STM32F10x Standard Peripherals Firmware Library: STM32100B_EVAL_LCD_Private_Macros

Defines

STM32100B_EVAL_LCD_Private_Macros

STM32100B_EVAL_LCD

Defines

#define ABS(X) ((X) > 0 ? (X) : -(X))

Define Documentation

#define ABS ( X ) ((X) > 0 ? (X) : -(X))

Definition at line 75 of file stm32100b_eval_lcd.c.

Referenced by LCD_DrawUniLine().


STM32F10x Standard Peripherals Firmware Library: STM32100B_EVAL_LCD_Private_Variables

Variables

STM32100B_EVAL_LCD_Private_Variables

STM32100B_EVAL_LCD

Variables

static __IO uint16_t | BackColor = 0xFFFF
static sFONT * | LCD_Currentfonts
static __IO uint32_t | LCDType = LCD_ILI9320
static __IO uint16_t | TextColor = 0x0000

Variable Documentation

__IO uint16_t BackColor = 0xFFFF

Definition at line 85 of file stm32100b_eval_lcd.c.

Referenced by LCD_DrawChar(), LCD_DrawFullCircle(), LCD_DrawFullRect(), LCD_DrawMonoPict(), LCD_FillPolyLine(), LCD_GetColors(), LCD_SetBackColor(), and LCD_SetColors().

sFONT* LCD_Currentfonts [static]

Definition at line 83 of file stm32100b_eval_lcd.c.

Referenced by LCD_GetFont().

__IO uint32_t LCDType = LCD_ILI9320 [static]

Definition at line 86 of file stm32100b_eval_lcd.c.

Referenced by LCD_Clear(), LCD_DisplayOff(), LCD_DisplayOn(), LCD_DrawChar(), LCD_DrawCircle(), LCD_DrawLine(), LCD_DrawMonoPict(), LCD_PowerOn(), LCD_SetCursor(), LCD_SetDisplayWindow(), LCD_Setup(), LCD_SPIConfig(), LCD_WindowModeDisable(), LCD_WriteRAM(), LCD_WriteReg(), and STM32100B_LCD_Init().

__IO uint16_t TextColor = 0x0000 [static]

Definition at line 85 of file stm32100b_eval_lcd.c.

Referenced by LCD_DrawChar(), LCD_DrawCircle(), LCD_DrawFullCircle(), LCD_DrawFullRect(), LCD_DrawLine(), LCD_DrawMonoPict(), LCD_FillPolyLine(), LCD_GetColors(), LCD_SetColors(), and LCD_SetTextColor().


STM32F10x Standard Peripherals Firmware Library: STM32100B_EVAL_LCD_Private_Function_Prototypes

STM32100B_EVAL_LCD_Private_Function_Prototypes

STM32100B_EVAL_LCD


STM32F10x Standard Peripherals Firmware Library: STM32100B_EVAL_LCD_Private_Functions

Functions

STM32100B_EVAL_LCD_Private_Functions

STM32100B_EVAL_LCD

Functions

static void | delay (vu32 nCount)
Inserts a delay time.
void | LCD_Clear (uint16_t Color)
Clears the hole LCD.
void | LCD_ClearLine (uint8_t Line)
Clears the selected line.
void | LCD_ClosedPolyLine (pPoint Points, uint16_t PointCount)
Displays a closed polyline (between many points).
void | LCD_ClosedPolyLineRelative (pPoint Points, uint16_t PointCount)
Displays a closed relative polyline (between many points).
void | LCD_CtrlLinesConfig (void)
Configures LCD control lines in Output Push-Pull mode.
void | LCD_CtrlLinesWrite (GPIO_TypeDef *GPIOx, uint16_t CtrlPins, BitAction BitVal)
Sets or reset LCD control lines.
void | LCD_DeInit (void)
DeInitializes the LCD.
void | LCD_DisplayChar (uint8_t Line, uint16_t Column, uint8_t Ascii)
Displays one character (16dots width, 24dots height).
void | LCD_DisplayOff (void)
Disables the Display.
void | LCD_DisplayOn (void)
Enables the Display.
void | LCD_DisplayStringLine (uint8_t Line, uint8_t *ptr)
Displays a maximum of 20 char on the LCD.
void | LCD_DrawChar (uint8_t Xpos, uint16_t Ypos, const uint16_t *c)
Draws a character on LCD.
void | LCD_DrawCircle (uint8_t Xpos, uint16_t Ypos, uint16_t Radius)
Displays a circle.
void | LCD_DrawFullCircle (uint16_t Xpos, uint16_t Ypos, uint16_t Radius)
Displays a full circle.
void | LCD_DrawFullRect (uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height)
Displays a full rectangle.
void | LCD_DrawLine (uint8_t Xpos, uint16_t Ypos, uint16_t Length, uint8_t Direction)
Displays a line.
void | LCD_DrawMonoPict (const uint32_t *Pict)
Displays a monocolor picture.
void | LCD_DrawRect (uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width)
Displays a rectangle.
void | LCD_DrawUniLine (uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2)
Displays an uni line (between two points).
void | LCD_FillPolyLine (pPoint Points, uint16_t PointCount)
Displays a full polyline (between many points).
void | LCD_GetColors (__IO uint16_t *_TextColor, __IO uint16_t *_BackColor)
Gets the LCD Text and Background colors.
sFONT * | LCD_GetFont (void)
Gets the Text Font.
void | LCD_nCS_StartByte (uint8_t Start_Byte)
Reset LCD control line(/CS) and Send Start-Byte.
void | LCD_PolyLine (pPoint Points, uint16_t PointCount)
Displays an polyline (between many points).
void | LCD_PolyLineRelative (pPoint Points, uint16_t PointCount)
Displays a relative polyline (between many points).
static void | LCD_PolyLineRelativeClosed (pPoint Points, uint16_t PointCount, uint16_t Closed)
Displays an relative polyline (between many points).
void | LCD_PowerOn (void)
Power on the LCD.
uint16_t | LCD_ReadReg (uint8_t LCD_Reg)
Reads the selected LCD Register.
void | LCD_SetBackColor (__IO uint16_t Color)
Sets the Background color.
void | LCD_SetColors (__IO uint16_t _TextColor, __IO uint16_t _BackColor)
Sets the LCD Text and Background colors.
void | LCD_SetCursor (uint8_t Xpos, uint16_t Ypos)
Sets the cursor position.
void | LCD_SetDisplayWindow (uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width)
Sets a display window.
void | LCD_SetFont (sFONT *fonts)
Sets the Text Font.
void | LCD_SetTextColor (__IO uint16_t Color)
Sets the Text color.
void | LCD_Setup (void)
Setups the LCD.
void | LCD_SPIConfig (void)
Configures the LCD_SPI interface.
void | LCD_WindowModeDisable (void)
Disables LCD Window mode.
void | LCD_WriteRAM (uint16_t RGB_Code)
Writes to the LCD RAM.
void | LCD_WriteRAM_Prepare (void)
Prepare to write to the LCD RAM.
void | LCD_WriteRAMWord (uint16_t RGB_Code)
Writes 1 word to the LCD RAM.
void | LCD_WriteReg (uint8_t LCD_Reg, uint16_t LCD_RegValue)
Writes to the selected LCD register.
static void | LCD_WriteRegHX8312 (uint8_t LCD_Reg, uint8_t LCD_RegValue)
Writes to the selected LCD HX8312 register.
static void | LCD_WriteRegILI9320 (uint8_t LCD_Reg, uint16_t LCD_RegValue)
Writes to the selected LCD ILI9320 register.
void | LCD_WriteRegIndex (uint8_t LCD_Reg)
Writes index to select the LCD register.
static void | PutPixel (int16_t x, int16_t y)
Displays a pixel.
void | STM32100B_LCD_Init (void)
Initializes the LCD.

Function Documentation

static void delay ( vu32 nCount ) [static]

Inserts a delay time.

Parameters:
nCount,: specifies the delay time length.
Return values:
None

Definition at line 1847 of file stm32100b_eval_lcd.c.

References index.

Referenced by SD_Erase().

void LCD_Clear ( uint16_t Color )

Clears the hole LCD.

Parameters:
Color,: the color of the background.
Return values:
None

Definition at line 544 of file stm32100b_eval_lcd.c.

Referenced by main(), and sEE_TIMEOUT_UserCallback().

void LCD_ClearLine ( uint8_t Line )

Clears the selected line.

Parameters:
Line,: the Line to be cleared. This parameter can be one of the following values:

  • Linex: where x can be 0..n
Return values:
None

Definition at line 525 of file stm32100b_eval_lcd.c.

Referenced by main().

void LCD_ClosedPolyLine | ( | pPoint | Points,
 |  | uint16_t | PointCount
 | ) |  |

Displays a closed polyline (between many points).

Parameters:
Points,: pointer to the points array.
PointCount,: Number of points.
Return values:
None

Definition at line 1236 of file stm32100b_eval_lcd.c.

void LCD_ClosedPolyLineRelative | ( | pPoint | Points,
 |  | uint16_t | PointCount
 | ) |  |

Displays a closed relative polyline (between many points).

Parameters:
Points,: pointer to the points array.
PointCount,: Number of points.
Return values:
None

Definition at line 1259 of file stm32100b_eval_lcd.c.

void LCD_CtrlLinesConfig ( void )

Configures LCD control lines in Output Push-Pull mode.

Parameters:
None
Return values:
None

Definition at line 1724 of file stm32100b_eval_lcd.c.

Referenced by LCD_Setup(), STM32100E_LCD_Init(), and STM3210E_LCD_Init().

void LCD_CtrlLinesWrite | ( | GPIO_TypeDef * | GPIOx,
 |  | uint16_t | CtrlPins,
 |  | BitAction | BitVal
 | ) |  |

Sets or reset LCD control lines.

Parameters:
GPIOx,: where x can be B or D to select the GPIO peripheral.
CtrlPins,: the Control line. This parameter can be:

  • LCD_NCS_PIN: Chip Select pin
  • LCD_NWR_PIN: Read/Write Selection pin
  • LCD_RS_PIN: Register/RAM Selection pin
BitVal,: specifies the value to be written to the selected bit. This parameter can be:

  • Bit_RESET: to clear the port pin
  • Bit_SET: to set the port pin
Return values:
None

Definition at line 1763 of file stm32100b_eval_lcd.c.

Referenced by LCD_Clear(), LCD_CtrlLinesConfig(), LCD_DrawChar(), LCD_DrawLine(), LCD_DrawMonoPict(), LCD_nCS_StartByte(), LCD_ReadReg(), LCD_WriteRAM(), LCD_WriteRAMWord(), LCD_WriteReg(), LCD_WriteRegHX8312(), LCD_WriteRegILI9320(), and LCD_WriteRegIndex().

void LCD_DeInit ( void )

DeInitializes the LCD.

Parameters:
None
Return values:
None

< LCD Display Off

< LCD_SPI disable

< LCD_SPI DeInit

< Disable SPI clock

Definition at line 116 of file stm32100b_eval_lcd.c.

void LCD_DisplayChar | ( | uint8_t | Line,
 |  | uint16_t | Column,
 |  | uint8_t | Ascii
 | ) |  |

Displays one character (16dots width, 24dots height).

Parameters:
Line,: the Line where to display the character shape . This parameter can be one of the following values:

  • Linex: where x can be 0..9
Column,: start column address.
Ascii,: character ascii code, must be between 0x20 and 0x7E.
Return values:
None

Definition at line 640 of file stm32100b_eval_lcd.c.

Referenced by LCD_ClearLine(), LCD_DisplayStringLine(), and main().

void LCD_DisplayOff ( void )

Disables the Display.

Parameters:
None
Return values:
None

Definition at line 1702 of file stm32100b_eval_lcd.c.

Referenced by LCD_DeInit(), and STM32L152_LCD_DeInit().

void LCD_DisplayOn ( void )

Enables the Display.

Parameters:
None
Return values:
None

Definition at line 1677 of file stm32100b_eval_lcd.c.

void LCD_DisplayStringLine | ( | uint8_t | Line,
 |  | uint8_t * | ptr
 | ) |  |

Displays a maximum of 20 char on the LCD.

Parameters:
Line,: the Line where to display the character shape . This parameter can be one of the following values:

  • Linex: where x can be 0..9
*ptr,: pointer to string to display on LCD.
Return values:
None

Definition at line 655 of file stm32100b_eval_lcd.c.

Referenced by EXTI15_10_IRQHandler(), LED_Display(), main(), and sEE_TIMEOUT_UserCallback().

void LCD_DrawChar | ( | uint8_t | Xpos,
 |  | uint16_t | Ypos,
 |  | const uint16_t * | c
 | ) |  |

Draws a character on LCD.

Parameters:
Xpos,: the Line where to display the character shape.
Ypos,: start column address.
c,: pointer to the character data.
Return values:
None

Definition at line 593 of file stm32100b_eval_lcd.c.

Referenced by LCD_DisplayChar().

void LCD_DrawCircle | ( | uint8_t | Xpos,
 |  | uint16_t | Ypos,
 |  | uint16_t | Radius
 | ) |  |

Displays a circle.

Parameters:
Xpos,: specifies the X position.
Ypos,: specifies the Y position.
Radius
Return values:
None

Definition at line 817 of file stm32100b_eval_lcd.c.

Referenced by LCD_DrawFullCircle().

void LCD_DrawFullCircle | ( | uint16_t | Xpos,
 |  | uint16_t | Ypos,
 |  | uint16_t | Radius
 | ) |  |

Displays a full circle.

Parameters:
Xpos,: specifies the X position.
Ypos,: specifies the Y position.
Radius
Return values:
None

Definition at line 1057 of file stm32100b_eval_lcd.c.

void LCD_DrawFullRect | ( | uint16_t | Xpos,
 |  | uint16_t | Ypos,
 |  | uint16_t | Width,
 |  | uint16_t | Height
 | ) |  |

Displays a full rectangle.

Parameters:
Xpos,: specifies the X position.
Ypos,: specifies the Y position.
Height,: rectangle height.
Width,: rectangle width.
Return values:
None

Definition at line 1026 of file stm32100b_eval_lcd.c.

void LCD_DrawLine | ( | uint8_t | Xpos,
 |  | uint16_t | Ypos,
 |  | uint16_t | Length,
 |  | uint8_t | Direction
 | ) |  |

Displays a line.

Parameters:
Xpos,: specifies the X position.
Ypos,: specifies the Y position.
Length,: line length.
Direction,: line direction. This parameter can be one of the following values: Vertical or Horizontal.
Return values:
None

Definition at line 753 of file stm32100b_eval_lcd.c.

Referenced by LCD_DrawFullCircle(), LCD_DrawFullRect(), LCD_DrawRect(), LCD_FillPolyLine(), and PutPixel().

void LCD_DrawMonoPict ( const uint32_t * Pict )

Displays a monocolor picture.

Parameters:
Pict,: pointer to the picture array.
Return values:
None

Definition at line 926 of file stm32100b_eval_lcd.c.

void LCD_DrawRect | ( | uint8_t | Xpos,
 |  | uint16_t | Ypos,
 |  | uint8_t | Height,
 |  | uint16_t | Width
 | ) |  |

Displays a rectangle.

Parameters:
Xpos,: specifies the X position.
Ypos,: specifies the Y position.
Height,: display rectangle height.
Width,: display rectangle width.
Return values:
None

Definition at line 800 of file stm32100b_eval_lcd.c.

Referenced by main().

void LCD_DrawUniLine | ( | uint16_t | x1,
 |  | uint16_t | y1,
 |  | uint16_t | x2,
 |  | uint16_t | y2
 | ) |  |

Displays an uni line (between two points).

Parameters:
x1,: specifies the point 1 x position.
y1,: specifies the point 1 y position.
x2,: specifies the point 2 x position.
y2,: specifies the point 2 y position.
Return values:
None

Definition at line 1107 of file stm32100b_eval_lcd.c.

Referenced by LCD_ClosedPolyLine(), LCD_PolyLine(), and LCD_PolyLineRelativeClosed().

void LCD_FillPolyLine | ( | pPoint | Points,
 |  | uint16_t | PointCount
 | ) |  |

Displays a full polyline (between many points).

Parameters:
Points,: pointer to the points array.
PointCount,: Number of points.
Return values:
None

Definition at line 1271 of file stm32100b_eval_lcd.c.

void LCD_GetColors | ( | __IO uint16_t * | _TextColor,
 |  | __IO uint16_t * | _BackColor
 | ) |  |

Gets the LCD Text and Background colors.

Parameters:
_TextColor,: pointer to the variable that will contain the Text Color.
_BackColor,: pointer to the variable that will contain the Background Color.
Return values:
None

Definition at line 472 of file stm32100b_eval_lcd.c.

sFONT* LCD_GetFont ( void )

Gets the Text Font.

Parameters:
None.
Return values:
the used font.

Definition at line 513 of file stm32100b_eval_lcd.c.

void LCD_nCS_StartByte ( uint8_t Start_Byte )

Reset LCD control line(/CS) and Send Start-Byte.

Parameters:
Start_Byte,: the Start-Byte to be sent
Return values:
None

Definition at line 1377 of file stm32100b_eval_lcd.c.

Referenced by LCD_ReadReg(), LCD_WriteRAM_Prepare(), LCD_WriteReg(), LCD_WriteRegILI9320(), and LCD_WriteRegIndex().

void LCD_PolyLine | ( | pPoint | Points,
 |  | uint16_t | PointCount
 | ) |  |

Displays an polyline (between many points).

Parameters:
Points,: pointer to the points array.
PointCount,: Number of points.
Return values:
None

Definition at line 1180 of file stm32100b_eval_lcd.c.

Referenced by LCD_ClosedPolyLine().

void LCD_PolyLineRelative | ( | pPoint | Points,
 |  | uint16_t | PointCount
 | ) |  |

Displays a relative polyline (between many points).

Parameters:
Points,: pointer to the points array.
PointCount,: Number of points.
Return values:
None

Definition at line 1248 of file stm32100b_eval_lcd.c.

static void LCD_PolyLineRelativeClosed | ( | pPoint | Points,
 |  | uint16_t | PointCount,
 |  | uint16_t | Closed
 | ) |  | [static]

Displays an relative polyline (between many points).

Parameters:
Points,: pointer to the points array.
PointCount,: Number of points.
Closed,: specifies if the draw is closed or not. 1: closed, 0 : not closed.
Return values:
None

Definition at line 1206 of file stm32100b_eval_lcd.c.

References LCD_DrawUniLine(), Point::X, and Point::Y.

Referenced by LCD_ClosedPolyLineRelative(), and LCD_PolyLineRelative().

void LCD_PowerOn ( void )

Power on the LCD.

Parameters:
None
Return values:
None

Definition at line 1629 of file stm32100b_eval_lcd.c.

uint16_t LCD_ReadReg ( uint8_t LCD_Reg )

Reads the selected LCD Register.

Parameters:
LCD_Reg,: address of the selected register.
Return values:
LCD Register Value.

Definition at line 1452 of file stm32100b_eval_lcd.c.

Referenced by STM32100B_LCD_Init(), STM32100E_LCD_Init(), STM3210B_LCD_Init(), STM3210E_LCD_Init(), and STM32L152_LCD_Init().

void LCD_SetBackColor ( __IO uint16_t Color )

Sets the Background color.

Parameters:
Color,: specifies the Background color code RGB(5-6-5).
Return values:
None

Definition at line 493 of file stm32100b_eval_lcd.c.

Referenced by main().

void LCD_SetColors | ( | __IO uint16_t | _TextColor,
 |  | __IO uint16_t | _BackColor
 | ) |  |

Sets the LCD Text and Background colors.

Parameters:
_TextColor,: specifies the Text Color.
_BackColor,: specifies the Background Color.
Return values:
None

Definition at line 458 of file stm32100b_eval_lcd.c.

void LCD_SetCursor | ( | uint8_t | Xpos,
 |  | uint16_t | Ypos
 | ) |  |

Sets the cursor position.

Parameters:
Xpos,: specifies the X position.
Ypos,: specifies the Y position.
Return values:
None

Definition at line 570 of file stm32100b_eval_lcd.c.

Referenced by LCD_Clear(), LCD_DrawChar(), LCD_DrawCircle(), LCD_DrawLine(), LCD_DrawMonoPict(), and LCD_SetDisplayWindow().

void LCD_SetDisplayWindow | ( | uint8_t | Xpos,
 |  | uint16_t | Ypos,
 |  | uint8_t | Height,
 |  | uint16_t | Width
 | ) |  |

Sets a display window.

Parameters:
Xpos,: specifies the X buttom left position.
Ypos,: specifies the Y buttom left position.
Height,: display window height.
Width,: display window width.
Return values:
None

Definition at line 680 of file stm32100b_eval_lcd.c.

Referenced by LCD_WindowModeDisable().

void LCD_SetFont ( sFONT * fonts )

Sets the Text Font.

Parameters:
fonts,: specifies the font to be used.
Return values:
None

Definition at line 503 of file stm32100b_eval_lcd.c.

Referenced by main(), STM32100B_LCD_Init(), STM32100E_LCD_Init(), STM3210B_LCD_Init(), STM3210C_LCD_Init(), STM3210E_LCD_Init(), and STM32L152_LCD_Init().

void LCD_SetTextColor ( __IO uint16_t Color )

Sets the Text color.

Parameters:
Color,: specifies the Text color code RGB(5-6-5).
Return values:
None

Definition at line 482 of file stm32100b_eval_lcd.c.

Referenced by LCD_DrawFullCircle(), LCD_DrawFullRect(), LCD_FillPolyLine(), and main().

void LCD_Setup ( void )

Setups the LCD.

Parameters:
None
Return values:
None

Definition at line 160 of file stm32100b_eval_lcd.c.

Referenced by STM32100B_LCD_Init(), STM3210B_LCD_Init(), STM3210C_LCD_Init(), and STM32L152_LCD_Init().

void LCD_SPIConfig ( void )

Configures the LCD_SPI interface.

Parameters:
None
Return values:
None

Definition at line 1775 of file stm32100b_eval_lcd.c.

Referenced by LCD_Setup().

void LCD_WindowModeDisable ( void )

Disables LCD Window mode.

Parameters:
None
Return values:
None

Definition at line 729 of file stm32100b_eval_lcd.c.

void LCD_WriteRAM ( uint16_t RGB_Code )

Writes to the LCD RAM.

Parameters:
RGB_Code,: the pixel color in RGB mode (5-6-5).
Return values:
None

Definition at line 1594 of file stm32100b_eval_lcd.c.

Referenced by LCD_Clear(), LCD_DrawChar(), LCD_DrawCircle(), LCD_DrawLine(), LCD_DrawMonoPict(), LCD_WriteBMP(), and LCD_WriteRAMWord().

void LCD_WriteRAM_Prepare ( void )

Prepare to write to the LCD RAM.

Parameters:
None
Return values:
None

Definition at line 1518 of file stm32100b_eval_lcd.c.

Referenced by LCD_Clear(), LCD_DrawChar(), LCD_DrawCircle(), LCD_DrawLine(), LCD_DrawMonoPict(), LCD_WriteBMP(), and LCD_WriteRAMWord().

void LCD_WriteRAMWord ( uint16_t RGB_Code )

Writes 1 word to the LCD RAM.

Parameters:
RGB_Code,: the pixel color in RGB mode (5-6-5).
Return values:
None

Definition at line 1532 of file stm32100b_eval_lcd.c.

Referenced by LCD_DrawCircle(), and LCD_DrawLine().

void LCD_WriteReg | ( | uint8_t | LCD_Reg,
 |  | uint16_t | LCD_RegValue
 | ) |  |

Writes to the selected LCD register.

Parameters:
LCD_Reg,: address of the selected register.
LCD_RegValue,: value to write to the selected register.
Return values:
None

Definition at line 1576 of file stm32100b_eval_lcd.c.

Referenced by LCD_DisplayOff(), LCD_DisplayOn(), LCD_PowerOn(), LCD_SetCursor(), LCD_SetDisplayWindow(), LCD_Setup(), LCD_WindowModeDisable(), LCD_WriteBMP(), STM32100E_LCD_Init(), and STM3210E_LCD_Init().

static void LCD_WriteRegHX8312 | ( | uint8_t | LCD_Reg,
 |  | uint8_t | LCD_RegValue
 | ) |  | [static]

Writes to the selected LCD HX8312 register.

Parameters:
LCD_Reg,: address of the selected register.
LCD_RegValue,: value to write to the selected register.
Return values:
None

Definition at line 1549 of file stm32100b_eval_lcd.c.

References Bit_RESET, Bit_SET, LCD_CtrlLinesWrite(), LCD_NCS_GPIO_PORT, LCD_NCS_PIN, LCD_NWR_GPIO_PORT, LCD_NWR_PIN, LCD_RS_GPIO_PORT, LCD_RS_PIN, LCD_SPI, RESET, SPI_I2S_FLAG_BSY, SPI_I2S_GetFlagStatus(), and SPI_I2S_SendData().

Referenced by LCD_WriteReg().

static void LCD_WriteRegILI9320 | ( | uint8_t | LCD_Reg,
 |  | uint16_t | LCD_RegValue
 | ) |  | [static]

Writes to the selected LCD ILI9320 register.

Parameters:
LCD_Reg,: address of the selected register.
LCD_RegValue,: value to write to the selected register.
Return values:
None

Definition at line 1422 of file stm32100b_eval_lcd.c.

References Bit_SET, LCD_CtrlLinesWrite(), LCD_NCS_GPIO_PORT, LCD_NCS_PIN, LCD_nCS_StartByte(), LCD_SPI, LCD_WRITE_REG, LCD_WriteRegIndex(), RESET, SPI_I2S_FLAG_BSY, SPI_I2S_GetFlagStatus(), SPI_I2S_SendData(), and START_BYTE.

Referenced by LCD_WriteReg().

void LCD_WriteRegIndex ( uint8_t LCD_Reg )

Writes index to select the LCD register.

Parameters:
LCD_Reg,: address of the selected register.
Return values:
None

Definition at line 1394 of file stm32100b_eval_lcd.c.

Referenced by LCD_ReadReg(), LCD_WriteRAM_Prepare(), LCD_WriteReg(), and LCD_WriteRegILI9320().

static void PutPixel | ( | int16_t | x,
 |  | int16_t | y
 | ) |  | [static]

Displays a pixel.

Parameters:
x,: pixel x.
y,: pixel y.
Return values:
None

Definition at line 1832 of file stm32100b_eval_lcd.c.

References LCD_DIR_HORIZONTAL, and LCD_DrawLine().

Referenced by LCD_DrawUniLine(), and LCD_FillPolyLine().

void STM32100B_LCD_Init ( void )

Initializes the LCD.

Parameters:
None
Return values:
None

Definition at line 427 of file stm32100b_eval_lcd.c.

References LCD_DEFAULT_FONT, LCD_HX8312, LCD_ILI9320, LCD_ReadReg(), LCD_REG_0, LCD_SetFont(), LCD_Setup(), LCD_SPFD5408, and LCDType.

Referenced by main().


STM32F10x Standard Peripherals Firmware Library: STM32100B_EVAL_LCD_Exported_Types

Data Structures | Typedefs

STM32100B_EVAL_LCD_Exported_Types

STM32100B_EVAL_LCD

Data Structures

struct | Point

Typedefs

typedef struct Point * | pPoint

Typedef Documentation

typedef struct Point * pPoint


STM32F10x Standard Peripherals Firmware Library: Point Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

Point Struct Reference
STM32100B_EVAL_LCD_Exported_Types | STM32100E_EVAL_LCD_Exported_Types | STM3210B_EVAL_LCD_Exported_Types | STM3210C_EVAL_LCD_Exported_Types | STM3210E_EVAL_LCD_Exported_Types | STM32L152_EVAL_LCD_Exported_Types

#include <stm32100b_eval_lcd.h>

Data Fields

int16_t | X
int16_t | Y

Detailed Description

Definition at line 55 of file stm32100b_eval_lcd.h.

Field Documentation

int16_t Point::X

Definition at line 57 of file stm32100b_eval_lcd.h.

Referenced by LCD_ClosedPolyLine(), LCD_FillPolyLine(), LCD_PolyLine(), and LCD_PolyLineRelativeClosed().

int16_t Point::Y

Definition at line 58 of file stm32100b_eval_lcd.h.

Referenced by LCD_ClosedPolyLine(), LCD_FillPolyLine(), LCD_PolyLine(), and LCD_PolyLineRelativeClosed().

The documentation for this struct was generated from the following files:
  • stm32100b_eval_lcd.h
  • stm32100e_eval_lcd.h
  • stm3210b_eval_lcd.h
  • stm3210c_eval_lcd.h
  • stm3210e_eval_lcd.h
  • stm32l152_eval_lcd.h


STM32F10x Standard Peripherals Firmware Library: STM32100B_EVAL_LCD_Exported_Constants

Defines

STM32100B_EVAL_LCD_Exported_Constants

STM32100B_EVAL_LCD

Defines

#define | _delay_ delay
Uncomment the line below if you want to use LCD_DrawBMP function to display a bitmap picture on the LCD.
#define | LCD_COLOR_BLACK 0x0000
#define | LCD_COLOR_BLUE 0x001F
#define | LCD_COLOR_BLUE2 0x051F
#define | LCD_COLOR_CYAN 0x7FFF
#define | LCD_COLOR_GREEN 0x07E0
#define | LCD_COLOR_GREY 0xF7DE
#define | LCD_COLOR_MAGENTA 0xF81F
#define | LCD_COLOR_RED 0xF800
#define | LCD_COLOR_WHITE 0xFFFF
LCD color.
#define | LCD_COLOR_YELLOW 0xFFE0
#define | LCD_DEFAULT_FONT Font16x24
LCD default font.
#define | LCD_DIR_HORIZONTAL 0x0000
LCD Direction.
#define | LCD_DIR_VERTICAL 0x0001
#define | LCD_LINE_0 LINE(0)
LCD Lines depending on the chosen fonts.
#define | LCD_LINE_1 LINE(1)
#define | LCD_LINE_10 LINE(10)
#define | LCD_LINE_11 LINE(11)
#define | LCD_LINE_12 LINE(12)
#define | LCD_LINE_13 LINE(13)
#define | LCD_LINE_14 LINE(14)
#define | LCD_LINE_15 LINE(15)
#define | LCD_LINE_16 LINE(16)
#define | LCD_LINE_17 LINE(17)
#define | LCD_LINE_18 LINE(18)
#define | LCD_LINE_19 LINE(19)
#define | LCD_LINE_2 LINE(2)
#define | LCD_LINE_20 LINE(20)
#define | LCD_LINE_21 LINE(21)
#define | LCD_LINE_22 LINE(22)
#define | LCD_LINE_23 LINE(23)
#define | LCD_LINE_24 LINE(24)
#define | LCD_LINE_25 LINE(25)
#define | LCD_LINE_26 LINE(26)
#define | LCD_LINE_27 LINE(27)
#define | LCD_LINE_28 LINE(28)
#define | LCD_LINE_29 LINE(29)
#define | LCD_LINE_3 LINE(3)
#define | LCD_LINE_4 LINE(4)
#define | LCD_LINE_5 LINE(5)
#define | LCD_LINE_6 LINE(6)
#define | LCD_LINE_7 LINE(7)
#define | LCD_LINE_8 LINE(8)
#define | LCD_LINE_9 LINE(9)
#define | LCD_NCS_GPIO_CLK RCC_APB2Periph_GPIOB
#define | LCD_NCS_GPIO_PORT GPIOB
#define | LCD_NCS_PIN GPIO_Pin_2
LCD Control pins.
#define | LCD_NWR_GPIO_CLK RCC_APB2Periph_GPIOD
#define | LCD_NWR_GPIO_PORT GPIOD
#define | LCD_NWR_PIN GPIO_Pin_15
#define | LCD_PIXEL_HEIGHT 0x00F0
#define | LCD_PIXEL_WIDTH 0x0140
LCD Size (Width and Height)
#define | LCD_REG_0 0x00
LCD Registers.
#define | LCD_REG_1 0x01
#define | LCD_REG_10 0x0A
#define | LCD_REG_106 0x6A
#define | LCD_REG_118 0x76
#define | LCD_REG_12 0x0C
#define | LCD_REG_128 0x80
#define | LCD_REG_129 0x81
#define | LCD_REG_13 0x0D
#define | LCD_REG_130 0x82
#define | LCD_REG_131 0x83
#define | LCD_REG_132 0x84
#define | LCD_REG_133 0x85
#define | LCD_REG_134 0x86
#define | LCD_REG_135 0x87
#define | LCD_REG_136 0x88
#define | LCD_REG_137 0x89
#define | LCD_REG_139 0x8B
#define | LCD_REG_14 0x0E
#define | LCD_REG_140 0x8C
#define | LCD_REG_141 0x8D
#define | LCD_REG_143 0x8F
#define | LCD_REG_144 0x90
#define | LCD_REG_145 0x91
#define | LCD_REG_146 0x92
#define | LCD_REG_147 0x93
#define | LCD_REG_148 0x94
#define | LCD_REG_149 0x95
#define | LCD_REG_15 0x0F
#define | LCD_REG_150 0x96
#define | LCD_REG_151 0x97
#define | LCD_REG_152 0x98
#define | LCD_REG_153 0x99
#define | LCD_REG_154 0x9A
#define | LCD_REG_157 0x9D
#define | LCD_REG_16 0x10
#define | LCD_REG_17 0x11
#define | LCD_REG_18 0x12
#define | LCD_REG_19 0x13
#define | LCD_REG_192 0xC0
#define | LCD_REG_193 0xC1
#define | LCD_REG_2 0x02
#define | LCD_REG_20 0x14
#define | LCD_REG_21 0x15
#define | LCD_REG_22 0x16
#define | LCD_REG_227 0xE3
#define | LCD_REG_229 0xE5
#define | LCD_REG_23 0x17
#define | LCD_REG_231 0xE7
#define | LCD_REG_239 0xEF
#define | LCD_REG_24 0x18
#define | LCD_REG_25 0x19
#define | LCD_REG_26 0x1A
#define | LCD_REG_27 0x1B
#define | LCD_REG_28 0x1C
#define | LCD_REG_29 0x1D
#define | LCD_REG_3 0x03
#define | LCD_REG_30 0x1E
#define | LCD_REG_31 0x1F
#define | LCD_REG_32 0x20
#define | LCD_REG_33 0x21
#define | LCD_REG_34 0x22
#define | LCD_REG_36 0x24
#define | LCD_REG_37 0x25
#define | LCD_REG_4 0x04
#define | LCD_REG_40 0x28
#define | LCD_REG_41 0x29
#define | LCD_REG_43 0x2B
#define | LCD_REG_45 0x2D
#define | LCD_REG_48 0x30
#define | LCD_REG_49 0x31
#define | LCD_REG_5 0x05
#define | LCD_REG_50 0x32
#define | LCD_REG_51 0x33
#define | LCD_REG_52 0x34
#define | LCD_REG_53 0x35
#define | LCD_REG_54 0x36
#define | LCD_REG_55 0x37
#define | LCD_REG_56 0x38
#define | LCD_REG_57 0x39
#define | LCD_REG_59 0x3B
#define | LCD_REG_6 0x06
#define | LCD_REG_60 0x3C
#define | LCD_REG_61 0x3D
#define | LCD_REG_62 0x3E
#define | LCD_REG_63 0x3F
#define | LCD_REG_64 0x40
#define | LCD_REG_65 0x41
#define | LCD_REG_66 0x42
#define | LCD_REG_67 0x43
#define | LCD_REG_68 0x44
#define | LCD_REG_69 0x45
#define | LCD_REG_7 0x07
#define | LCD_REG_70 0x46
#define | LCD_REG_71 0x47
#define | LCD_REG_72 0x48
#define | LCD_REG_73 0x49
#define | LCD_REG_74 0x4A
#define | LCD_REG_75 0x4B
#define | LCD_REG_76 0x4C
#define | LCD_REG_77 0x4D
#define | LCD_REG_78 0x4E
#define | LCD_REG_79 0x4F
#define | LCD_REG_8 0x08
#define | LCD_REG_80 0x50
#define | LCD_REG_81 0x51
#define | LCD_REG_82 0x52
#define | LCD_REG_83 0x53
#define | LCD_REG_9 0x09
#define | LCD_REG_96 0x60
#define | LCD_REG_97 0x61
#define | LCD_RS_GPIO_CLK RCC_APB2Periph_GPIOD
#define | LCD_RS_GPIO_PORT GPIOD
#define | LCD_RS_PIN GPIO_Pin_7
#define | LCD_SPI SPI2
LCD SPI Interface pins.
#define | LCD_SPI_CLK RCC_APB1Periph_SPI2
#define | LCD_SPI_MISO_GPIO_CLK RCC_APB2Periph_GPIOB
#define | LCD_SPI_MISO_GPIO_PORT GPIOB
#define | LCD_SPI_MISO_PIN GPIO_Pin_14
#define | LCD_SPI_MOSI_GPIO_CLK RCC_APB2Periph_GPIOB
#define | LCD_SPI_MOSI_GPIO_PORT GPIOB
#define | LCD_SPI_MOSI_PIN GPIO_Pin_15
#define | LCD_SPI_SCK_GPIO_CLK RCC_APB2Periph_GPIOB
#define | LCD_SPI_SCK_GPIO_PORT GPIOB
#define | LCD_SPI_SCK_PIN GPIO_Pin_13

Define Documentation

#define _delay_ delay

Uncomment the line below if you want to use LCD_DrawBMP function to display a bitmap picture on the LCD.

This function assumes that the bitmap file is loaded in the SPI Flash (mounted on STM32100B-EVAL board), however user can tailor it according to his application hardware requirement. Uncomment the line below if you want to use user defined Delay function (for precise timing), otherwise default _delay_ function defined within this driver is used (less precise timing).

Definition at line 89 of file stm32100b_eval_lcd.h.

Referenced by IOE_Reset(), IOE_TS_Config(), LCD_DisplayOff(), LCD_DisplayOn(), LCD_PowerOn(), LCD_Setup(), STM32100E_LCD_Init(), and STM3210E_LCD_Init().

#define LCD_COLOR_BLACK 0x0000

Definition at line 242 of file stm32100b_eval_lcd.h.

#define LCD_COLOR_BLUE 0x001F

Definition at line 244 of file stm32100b_eval_lcd.h.

Referenced by main().

#define LCD_COLOR_BLUE2 0x051F

Definition at line 245 of file stm32100b_eval_lcd.h.

#define LCD_COLOR_CYAN 0x7FFF

Definition at line 249 of file stm32100b_eval_lcd.h.

#define LCD_COLOR_GREEN 0x07E0

Definition at line 248 of file stm32100b_eval_lcd.h.

Referenced by main().

#define LCD_COLOR_GREY 0xF7DE

Definition at line 243 of file stm32100b_eval_lcd.h.

#define LCD_COLOR_MAGENTA 0xF81F

Definition at line 247 of file stm32100b_eval_lcd.h.

#define LCD_COLOR_RED 0xF800

Definition at line 246 of file stm32100b_eval_lcd.h.

Referenced by main(), and sEE_TIMEOUT_UserCallback().

#define LCD_COLOR_WHITE 0xFFFF

LCD color.

Definition at line 241 of file stm32100b_eval_lcd.h.

Referenced by main().

#define LCD_COLOR_YELLOW 0xFFE0

Definition at line 250 of file stm32100b_eval_lcd.h.

#define LCD_DEFAULT_FONT Font16x24

LCD default font.

Definition at line 290 of file stm32100b_eval_lcd.h.

Referenced by STM32100B_LCD_Init(), STM32100E_LCD_Init(), STM3210B_LCD_Init(), STM3210C_LCD_Init(), STM3210E_LCD_Init(), and STM32L152_LCD_Init().

#define LCD_DIR_HORIZONTAL 0x0000

LCD Direction.

Definition at line 295 of file stm32100b_eval_lcd.h.

Referenced by LCD_DrawFullCircle(), LCD_DrawFullRect(), LCD_DrawLine(), LCD_DrawRect(), LCD_FillPolyLine(), and PutPixel().

#define LCD_DIR_VERTICAL 0x0001

Definition at line 296 of file stm32100b_eval_lcd.h.

Referenced by LCD_DrawFullRect(), and LCD_DrawRect().

#define LCD_LINE_0 LINE(0)

LCD Lines depending on the chosen fonts.

Definition at line 255 of file stm32100b_eval_lcd.h.

Referenced by main().

#define LCD_LINE_1 LINE(1)

Definition at line 256 of file stm32100b_eval_lcd.h.

Referenced by main().

#define LCD_LINE_10 LINE(10)

Definition at line 265 of file stm32100b_eval_lcd.h.

#define LCD_LINE_11 LINE(11)

Definition at line 266 of file stm32100b_eval_lcd.h.

#define LCD_LINE_12 LINE(12)

Definition at line 267 of file stm32100b_eval_lcd.h.

Referenced by main().

#define LCD_LINE_13 LINE(13)

Definition at line 268 of file stm32100b_eval_lcd.h.

Referenced by main().

#define LCD_LINE_14 LINE(14)

Definition at line 269 of file stm32100b_eval_lcd.h.

#define LCD_LINE_15 LINE(15)

Definition at line 270 of file stm32100b_eval_lcd.h.

Referenced by main().

#define LCD_LINE_16 LINE(16)

Definition at line 271 of file stm32100b_eval_lcd.h.

Referenced by main().

#define LCD_LINE_17 LINE(17)

Definition at line 272 of file stm32100b_eval_lcd.h.

#define LCD_LINE_18 LINE(18)

Definition at line 273 of file stm32100b_eval_lcd.h.

Referenced by main().

#define LCD_LINE_19 LINE(19)

Definition at line 274 of file stm32100b_eval_lcd.h.

Referenced by main().

#define LCD_LINE_2 LINE(2)

Definition at line 257 of file stm32100b_eval_lcd.h.

Referenced by main().

#define LCD_LINE_20 LINE(20)

Definition at line 275 of file stm32100b_eval_lcd.h.

#define LCD_LINE_21 LINE(21)

Definition at line 276 of file stm32100b_eval_lcd.h.

#define LCD_LINE_22 LINE(22)

Definition at line 277 of file stm32100b_eval_lcd.h.

#define LCD_LINE_23 LINE(23)

Definition at line 278 of file stm32100b_eval_lcd.h.

#define LCD_LINE_24 LINE(24)

Definition at line 279 of file stm32100b_eval_lcd.h.

#define LCD_LINE_25 LINE(25)

Definition at line 280 of file stm32100b_eval_lcd.h.

#define LCD_LINE_26 LINE(26)

Definition at line 281 of file stm32100b_eval_lcd.h.

#define LCD_LINE_27 LINE(27)

Definition at line 282 of file stm32100b_eval_lcd.h.

#define LCD_LINE_28 LINE(28)

Definition at line 283 of file stm32100b_eval_lcd.h.

#define LCD_LINE_29 LINE(29)

Definition at line 284 of file stm32100b_eval_lcd.h.

#define LCD_LINE_3 LINE(3)

Definition at line 258 of file stm32100b_eval_lcd.h.

Referenced by main().

#define LCD_LINE_4 LINE(4)

Definition at line 259 of file stm32100b_eval_lcd.h.

Referenced by main(), and sEE_TIMEOUT_UserCallback().

#define LCD_LINE_5 LINE(5)

Definition at line 260 of file stm32100b_eval_lcd.h.

Referenced by LED_Display(), main(), and sEE_TIMEOUT_UserCallback().

#define LCD_LINE_6 LINE(6)

Definition at line 261 of file stm32100b_eval_lcd.h.

Referenced by LED_Display(), main(), and sEE_TIMEOUT_UserCallback().

#define LCD_LINE_7 LINE(7)

Definition at line 262 of file stm32100b_eval_lcd.h.

Referenced by LED_Display(), and main().

#define LCD_LINE_8 LINE(8)

Definition at line 263 of file stm32100b_eval_lcd.h.

Referenced by main().

#define LCD_LINE_9 LINE(9)

Definition at line 264 of file stm32100b_eval_lcd.h.

Referenced by main().

#define LCD_NCS_GPIO_CLK RCC_APB2Periph_GPIOB

Definition at line 98 of file stm32100b_eval_lcd.h.

Referenced by LCD_CtrlLinesConfig().

#define LCD_NCS_GPIO_PORT GPIOB

Definition at line 97 of file stm32100b_eval_lcd.h.

Referenced by LCD_Clear(), LCD_CtrlLinesConfig(), LCD_DeInit(), LCD_DrawChar(), LCD_DrawLine(), LCD_DrawMonoPict(), LCD_nCS_StartByte(), LCD_ReadReg(), LCD_WriteRAM(), LCD_WriteRAMWord(), LCD_WriteReg(), LCD_WriteRegHX8312(), LCD_WriteRegILI9320(), LCD_WriteRegIndex(), and STM32L152_LCD_DeInit().

#define LCD_NCS_PIN GPIO_Pin_2

LCD Control pins.

Definition at line 96 of file stm32100b_eval_lcd.h.

Referenced by LCD_Clear(), LCD_CtrlLinesConfig(), LCD_DeInit(), LCD_DrawChar(), LCD_DrawLine(), LCD_DrawMonoPict(), LCD_nCS_StartByte(), LCD_ReadReg(), LCD_WriteRAM(), LCD_WriteRAMWord(), LCD_WriteReg(), LCD_WriteRegHX8312(), LCD_WriteRegILI9320(), LCD_WriteRegIndex(), and STM32L152_LCD_DeInit().

#define LCD_NWR_GPIO_CLK RCC_APB2Periph_GPIOD

Definition at line 101 of file stm32100b_eval_lcd.h.

Referenced by LCD_CtrlLinesConfig().

#define LCD_NWR_GPIO_PORT GPIOD

Definition at line 100 of file stm32100b_eval_lcd.h.

Referenced by LCD_CtrlLinesConfig(), LCD_DeInit(), LCD_WriteRAM(), and LCD_WriteRegHX8312().

#define LCD_NWR_PIN GPIO_Pin_15

Definition at line 99 of file stm32100b_eval_lcd.h.

Referenced by LCD_CtrlLinesConfig(), LCD_DeInit(), LCD_WriteRAM(), and LCD_WriteRegHX8312().

#define LCD_PIXEL_HEIGHT 0x00F0

Definition at line 302 of file stm32100b_eval_lcd.h.

#define LCD_PIXEL_WIDTH 0x0140

LCD Size (Width and Height)

Definition at line 301 of file stm32100b_eval_lcd.h.

Referenced by LCD_ClearLine(), LCD_DisplayStringLine(), and LCD_DrawMonoPict().

#define LCD_REG_0 0x00

LCD Registers.

Definition at line 125 of file stm32100b_eval_lcd.h.

Referenced by LCD_DisplayOff(), LCD_DisplayOn(), LCD_Setup(), STM32100B_LCD_Init(), STM32100E_LCD_Init(), STM3210B_LCD_Init(), STM3210E_LCD_Init(), and STM32L152_LCD_Init().

#define LCD_REG_1 0x01

Definition at line 126 of file stm32100b_eval_lcd.h.

Referenced by LCD_DisplayOn(), LCD_SetDisplayWindow(), LCD_Setup(), LCD_WindowModeDisable(), STM32100E_LCD_Init(), and STM3210E_LCD_Init().

#define LCD_REG_10 0x0A

Definition at line 135 of file stm32100b_eval_lcd.h.

Referenced by LCD_Setup(), STM32100E_LCD_Init(), and STM3210E_LCD_Init().

#define LCD_REG_106 0x6A

Definition at line 202 of file stm32100b_eval_lcd.h.

Referenced by LCD_Setup(), STM32100E_LCD_Init(), and STM3210E_LCD_Init().

#define LCD_REG_118 0x76

Definition at line 203 of file stm32100b_eval_lcd.h.

Referenced by LCD_Setup().

#define LCD_REG_12 0x0C

Definition at line 136 of file stm32100b_eval_lcd.h.

Referenced by LCD_Setup(), STM32100E_LCD_Init(), and STM3210E_LCD_Init().

#define LCD_REG_128 0x80

Definition at line 204 of file stm32100b_eval_lcd.h.

Referenced by LCD_Setup(), STM32100E_LCD_Init(), and STM3210E_LCD_Init().

#define LCD_REG_129 0x81

Definition at line 205 of file stm32100b_eval_lcd.h.

Referenced by LCD_Setup(), STM32100E_LCD_Init(), and STM3210E_LCD_Init().

#define LCD_REG_13 0x0D

Definition at line 137 of file stm32100b_eval_lcd.h.

Referenced by LCD_Setup(), STM32100E_LCD_Init(), and STM3210E_LCD_Init().

#define LCD_REG_130 0x82

Definition at line 206 of file stm32100b_eval_lcd.h.

Referenced by LCD_Setup(), STM32100E_LCD_Init(), and STM3210E_LCD_Init().

#define LCD_REG_131 0x83

Definition at line 207 of file stm32100b_eval_lcd.h.

Referenced by LCD_Setup(), STM32100E_LCD_Init(), and STM3210E_LCD_Init().

#define LCD_REG_132 0x84

Definition at line 208 of file stm32100b_eval_lcd.h.

Referenced by LCD_Setup(), STM32100E_LCD_Init(), and STM3210E_LCD_Init().

#define LCD_REG_133 0x85

Definition at line 209 of file stm32100b_eval_lcd.h.

Referenced by LCD_Setup(), STM32100E_LCD_Init(), and STM3210E_LCD_Init().

#define LCD_REG_134 0x86

Definition at line 210 of file stm32100b_eval_lcd.h.

Referenced by LCD_Setup().

#define LCD_REG_135 0x87

Definition at line 211 of file stm32100b_eval_lcd.h.

Referenced by LCD_Setup().

#define LCD_REG_136 0x88

Definition at line 212 of file stm32100b_eval_lcd.h.

Referenced by LCD_Setup().

#define LCD_REG_137 0x89

Definition at line 213 of file stm32100b_eval_lcd.h.

Referenced by LCD_Setup().

#define LCD_REG_139 0x8B

Definition at line 214 of file stm32100b_eval_lcd.h.

Referenced by LCD_Setup().

#define LCD_REG_14 0x0E

Definition at line 138 of file stm32100b_eval_lcd.h.

Referenced by LCD_Setup().

#define LCD_REG_140 0x8C

Definition at line 215 of file stm32100b_eval_lcd.h.

#define LCD_REG_141 0x8D

Definition at line 216 of file stm32100b_eval_lcd.h.

Referenced by LCD_Setup().

#define LCD_REG_143 0x8F

Definition at line 217 of file stm32100b_eval_lcd.h.

Referenced by LCD_Setup().

#define LCD_REG_144 0x90

Definition at line 218 of file stm32100b_eval_lcd.h.

Referenced by LCD_Setup(), STM32100E_LCD_Init(), and STM3210E_LCD_Init().

#define LCD_REG_145 0x91

Definition at line 219 of file stm32100b_eval_lcd.h.

Referenced by LCD_Setup().

#define LCD_REG_146 0x92

Definition at line 220 of file stm32100b_eval_lcd.h.

Referenced by LCD_Setup(), STM32100E_LCD_Init(), and STM3210E_LCD_Init().

#define LCD_REG_147 0x93

Definition at line 221 of file stm32100b_eval_lcd.h.

Referenced by LCD_Setup(), STM32100E_LCD_Init(), and STM3210E_LCD_Init().

#define LCD_REG_148 0x94

Definition at line 222 of file stm32100b_eval_lcd.h.

Referenced by LCD_Setup().

#define LCD_REG_149 0x95

Definition at line 223 of file stm32100b_eval_lcd.h.

Referenced by LCD_Setup(), STM32100E_LCD_Init(), and STM3210E_LCD_Init().

#define LCD_REG_15 0x0F

Definition at line 139 of file stm32100b_eval_lcd.h.

Referenced by LCD_Setup(), STM32100E_LCD_Init(), and STM3210E_LCD_Init().

#define LCD_REG_150 0x96

Definition at line 224 of file stm32100b_eval_lcd.h.

Referenced by LCD_Setup().

#define LCD_REG_151 0x97

Definition at line 225 of file stm32100b_eval_lcd.h.

Referenced by LCD_Setup(), STM32100E_LCD_Init(), and STM3210E_LCD_Init().

#define LCD_REG_152 0x98

Definition at line 226 of file stm32100b_eval_lcd.h.

Referenced by LCD_Setup(), STM32100E_LCD_Init(), and STM3210E_LCD_Init().

#define LCD_REG_153 0x99

Definition at line 227 of file stm32100b_eval_lcd.h.

Referenced by LCD_Setup().

#define LCD_REG_154 0x9A

Definition at line 228 of file stm32100b_eval_lcd.h.

Referenced by LCD_Setup().

#define LCD_REG_157 0x9D

Definition at line 229 of file stm32100b_eval_lcd.h.

Referenced by LCD_Setup().

#define LCD_REG_16 0x10

Definition at line 140 of file stm32100b_eval_lcd.h.

Referenced by LCD_PowerOn(), LCD_Setup(), STM32100E_LCD_Init(), and STM3210E_LCD_Init().

#define LCD_REG_17 0x11

Definition at line 141 of file stm32100b_eval_lcd.h.

Referenced by LCD_PowerOn(), LCD_Setup(), STM32100E_LCD_Init(), and STM3210E_LCD_Init().

#define LCD_REG_18 0x12

Definition at line 142 of file stm32100b_eval_lcd.h.

Referenced by LCD_PowerOn(), LCD_Setup(), STM32100E_LCD_Init(), and STM3210E_LCD_Init().

#define LCD_REG_19 0x13

Definition at line 143 of file stm32100b_eval_lcd.h.

Referenced by LCD_PowerOn(), LCD_Setup(), STM32100E_LCD_Init(), and STM3210E_LCD_Init().

#define LCD_REG_192 0xC0

Definition at line 230 of file stm32100b_eval_lcd.h.

Referenced by LCD_Setup().

#define LCD_REG_193 0xC1

Definition at line 231 of file stm32100b_eval_lcd.h.

#define LCD_REG_2 0x02

Definition at line 127 of file stm32100b_eval_lcd.h.

Referenced by LCD_Setup(), STM32100E_LCD_Init(), and STM3210E_LCD_Init().

#define LCD_REG_20 0x14

Definition at line 144 of file stm32100b_eval_lcd.h.

Referenced by LCD_Setup().

#define LCD_REG_21 0x15

Definition at line 145 of file stm32100b_eval_lcd.h.

Referenced by LCD_Setup().

#define LCD_REG_22 0x16

Definition at line 146 of file stm32100b_eval_lcd.h.

Referenced by LCD_Setup().

#define LCD_REG_227 0xE3

Definition at line 232 of file stm32100b_eval_lcd.h.

Referenced by LCD_Setup().

#define LCD_REG_229 0xE5

Definition at line 233 of file stm32100b_eval_lcd.h.

Referenced by LCD_Setup(), STM32100E_LCD_Init(), and STM3210E_LCD_Init().

#define LCD_REG_23 0x17

Definition at line 147 of file stm32100b_eval_lcd.h.

Referenced by LCD_Setup().

#define LCD_REG_231 0xE7

Definition at line 234 of file stm32100b_eval_lcd.h.

Referenced by LCD_Setup().

#define LCD_REG_239 0xEF

Definition at line 235 of file stm32100b_eval_lcd.h.

Referenced by LCD_Setup().

#define LCD_REG_24 0x18

Definition at line 148 of file stm32100b_eval_lcd.h.

Referenced by LCD_PowerOn(), and LCD_Setup().

#define LCD_REG_25 0x19

Definition at line 149 of file stm32100b_eval_lcd.h.

Referenced by LCD_Setup().

#define LCD_REG_26 0x1A

Definition at line 150 of file stm32100b_eval_lcd.h.

Referenced by LCD_Setup().

#define LCD_REG_27 0x1B

Definition at line 151 of file stm32100b_eval_lcd.h.

Referenced by LCD_PowerOn(), and LCD_Setup().

#define LCD_REG_28 0x1C

Definition at line 152 of file stm32100b_eval_lcd.h.

Referenced by LCD_PowerOn(), and LCD_Setup().

#define LCD_REG_29 0x1D

Definition at line 153 of file stm32100b_eval_lcd.h.

Referenced by LCD_Setup().

#define LCD_REG_3 0x03

Definition at line 128 of file stm32100b_eval_lcd.h.

Referenced by LCD_Setup(), LCD_WindowModeDisable(), LCD_WriteBMP(), STM32100E_LCD_Init(), and STM3210E_LCD_Init().

#define LCD_REG_30 0x1E

Definition at line 154 of file stm32100b_eval_lcd.h.

Referenced by LCD_PowerOn(), and LCD_Setup().

#define LCD_REG_31 0x1F

Definition at line 155 of file stm32100b_eval_lcd.h.

Referenced by LCD_PowerOn(), and LCD_Setup().

#define LCD_REG_32 0x20

Definition at line 156 of file stm32100b_eval_lcd.h.

Referenced by LCD_PowerOn(), LCD_SetCursor(), LCD_Setup(), STM32100E_LCD_Init(), and STM3210E_LCD_Init().

#define LCD_REG_33 0x21

Definition at line 157 of file stm32100b_eval_lcd.h.

Referenced by LCD_SetCursor(), LCD_Setup(), STM32100E_LCD_Init(), and STM3210E_LCD_Init().

#define LCD_REG_34 0x22

Definition at line 158 of file stm32100b_eval_lcd.h.

Referenced by LCD_ReadRAM(), and LCD_WriteRAM_Prepare().

#define LCD_REG_36 0x24

Definition at line 159 of file stm32100b_eval_lcd.h.

Referenced by LCD_PowerOn(), and LCD_Setup().

#define LCD_REG_37 0x25

Definition at line 160 of file stm32100b_eval_lcd.h.

Referenced by LCD_Setup().

#define LCD_REG_4 0x04

Definition at line 129 of file stm32100b_eval_lcd.h.

Referenced by LCD_Setup(), STM32100E_LCD_Init(), and STM3210E_LCD_Init().

#define LCD_REG_40 0x28

Definition at line 161 of file stm32100b_eval_lcd.h.

Referenced by LCD_Setup().

#define LCD_REG_41 0x29

Definition at line 162 of file stm32100b_eval_lcd.h.

Referenced by LCD_PowerOn(), LCD_Setup(), STM32100E_LCD_Init(), and STM3210E_LCD_Init().

#define LCD_REG_43 0x2B

Definition at line 163 of file stm32100b_eval_lcd.h.

Referenced by LCD_Setup().

#define LCD_REG_45 0x2D

Definition at line 164 of file stm32100b_eval_lcd.h.

#define LCD_REG_48 0x30

Definition at line 165 of file stm32100b_eval_lcd.h.

Referenced by LCD_Setup(), STM32100E_LCD_Init(), and STM3210E_LCD_Init().

#define LCD_REG_49 0x31

Definition at line 166 of file stm32100b_eval_lcd.h.

Referenced by LCD_Setup(), STM32100E_LCD_Init(), and STM3210E_LCD_Init().

#define LCD_REG_5 0x05

Definition at line 130 of file stm32100b_eval_lcd.h.

Referenced by LCD_DisplayOn(), LCD_SetDisplayWindow(), LCD_Setup(), and LCD_WindowModeDisable().

#define LCD_REG_50 0x32

Definition at line 167 of file stm32100b_eval_lcd.h.

Referenced by LCD_Setup(), STM32100E_LCD_Init(), and STM3210E_LCD_Init().

#define LCD_REG_51 0x33

Definition at line 168 of file stm32100b_eval_lcd.h.

Referenced by LCD_Setup(), STM32100E_LCD_Init(), and STM3210E_LCD_Init().

#define LCD_REG_52 0x34

Definition at line 169 of file stm32100b_eval_lcd.h.

Referenced by LCD_Setup(), STM32100E_LCD_Init(), and STM3210E_LCD_Init().

#define LCD_REG_53 0x35

Definition at line 170 of file stm32100b_eval_lcd.h.

Referenced by LCD_Setup(), STM32100E_LCD_Init(), and STM3210E_LCD_Init().

#define LCD_REG_54 0x36

Definition at line 171 of file stm32100b_eval_lcd.h.

Referenced by LCD_Setup(), STM32100E_LCD_Init(), and STM3210E_LCD_Init().

#define LCD_REG_55 0x37

Definition at line 172 of file stm32100b_eval_lcd.h.

Referenced by LCD_Setup(), STM32100E_LCD_Init(), and STM3210E_LCD_Init().

#define LCD_REG_56 0x38

Definition at line 173 of file stm32100b_eval_lcd.h.

Referenced by LCD_Setup(), STM32100E_LCD_Init(), and STM3210E_LCD_Init().

#define LCD_REG_57 0x39

Definition at line 174 of file stm32100b_eval_lcd.h.

Referenced by LCD_Setup(), STM32100E_LCD_Init(), and STM3210E_LCD_Init().

#define LCD_REG_59 0x3B

Definition at line 175 of file stm32100b_eval_lcd.h.

Referenced by LCD_DisplayOff(), LCD_DisplayOn(), LCD_Setup(), STM32100E_LCD_Init(), and STM3210E_LCD_Init().

#define LCD_REG_6 0x06

Definition at line 131 of file stm32100b_eval_lcd.h.

#define LCD_REG_60 0x3C

Definition at line 176 of file stm32100b_eval_lcd.h.

Referenced by LCD_Setup(), STM32100E_LCD_Init(), and STM3210E_LCD_Init().

#define LCD_REG_61 0x3D

Definition at line 177 of file stm32100b_eval_lcd.h.

Referenced by LCD_Setup(), STM32100E_LCD_Init(), and STM3210E_LCD_Init().

#define LCD_REG_62 0x3E

Definition at line 178 of file stm32100b_eval_lcd.h.

Referenced by LCD_Setup(), STM32100E_LCD_Init(), and STM3210E_LCD_Init().

#define LCD_REG_63 0x3F

Definition at line 179 of file stm32100b_eval_lcd.h.

Referenced by LCD_Setup(), STM32100E_LCD_Init(), and STM3210E_LCD_Init().

#define LCD_REG_64 0x40

Definition at line 180 of file stm32100b_eval_lcd.h.

Referenced by LCD_Setup().

#define LCD_REG_65 0x41

Definition at line 181 of file stm32100b_eval_lcd.h.

Referenced by LCD_Setup().

#define LCD_REG_66 0x42

Definition at line 182 of file stm32100b_eval_lcd.h.

Referenced by LCD_SetCursor(), and LCD_Setup().

#define LCD_REG_67 0x43

Definition at line 183 of file stm32100b_eval_lcd.h.

Referenced by LCD_SetCursor(), and LCD_Setup().

#define LCD_REG_68 0x44

Definition at line 184 of file stm32100b_eval_lcd.h.

Referenced by LCD_SetCursor(), and LCD_Setup().

#define LCD_REG_69 0x45

Definition at line 185 of file stm32100b_eval_lcd.h.

Referenced by LCD_SetDisplayWindow(), and LCD_Setup().

#define LCD_REG_7 0x07

Definition at line 132 of file stm32100b_eval_lcd.h.

Referenced by LCD_DisplayOff(), LCD_DisplayOn(), LCD_PowerOn(), LCD_Setup(), STM32100E_LCD_Init(), and STM3210E_LCD_Init().

#define LCD_REG_70 0x46

Definition at line 186 of file stm32100b_eval_lcd.h.

Referenced by LCD_SetDisplayWindow(), and LCD_Setup().

#define LCD_REG_71 0x47

Definition at line 187 of file stm32100b_eval_lcd.h.

Referenced by LCD_SetDisplayWindow(), and LCD_Setup().

#define LCD_REG_72 0x48

Definition at line 188 of file stm32100b_eval_lcd.h.

Referenced by LCD_SetDisplayWindow(), and LCD_Setup().

#define LCD_REG_73 0x49

Definition at line 189 of file stm32100b_eval_lcd.h.

Referenced by LCD_SetDisplayWindow(), and LCD_Setup().

#define LCD_REG_74 0x4A

Definition at line 190 of file stm32100b_eval_lcd.h.

Referenced by LCD_SetDisplayWindow(), and LCD_Setup().

#define LCD_REG_75 0x4B

Definition at line 191 of file stm32100b_eval_lcd.h.

Referenced by LCD_Setup().

#define LCD_REG_76 0x4C

Definition at line 192 of file stm32100b_eval_lcd.h.

Referenced by LCD_Setup().

#define LCD_REG_77 0x4D

Definition at line 193 of file stm32100b_eval_lcd.h.

#define LCD_REG_78 0x4E

Definition at line 194 of file stm32100b_eval_lcd.h.

Referenced by LCD_Setup().

#define LCD_REG_79 0x4F

Definition at line 195 of file stm32100b_eval_lcd.h.

Referenced by LCD_Setup().

#define LCD_REG_8 0x08

Definition at line 133 of file stm32100b_eval_lcd.h.

Referenced by LCD_Setup(), STM32100E_LCD_Init(), and STM3210E_LCD_Init().

#define LCD_REG_80 0x50

Definition at line 196 of file stm32100b_eval_lcd.h.

Referenced by LCD_SetDisplayWindow(), LCD_Setup(), STM32100E_LCD_Init(), and STM3210E_LCD_Init().

#define LCD_REG_81 0x51

Definition at line 197 of file stm32100b_eval_lcd.h.

Referenced by LCD_SetDisplayWindow(), LCD_Setup(), STM32100E_LCD_Init(), and STM3210E_LCD_Init().

#define LCD_REG_82 0x52

Definition at line 198 of file stm32100b_eval_lcd.h.

Referenced by LCD_SetDisplayWindow(), LCD_Setup(), STM32100E_LCD_Init(), and STM3210E_LCD_Init().

#define LCD_REG_83 0x53

Definition at line 199 of file stm32100b_eval_lcd.h.

Referenced by LCD_SetDisplayWindow(), LCD_Setup(), STM32100E_LCD_Init(), and STM3210E_LCD_Init().

#define LCD_REG_9 0x09

Definition at line 134 of file stm32100b_eval_lcd.h.

Referenced by LCD_Setup(), STM32100E_LCD_Init(), and STM3210E_LCD_Init().

#define LCD_REG_96 0x60

Definition at line 200 of file stm32100b_eval_lcd.h.

Referenced by LCD_Setup(), STM32100E_LCD_Init(), and STM3210E_LCD_Init().

#define LCD_REG_97 0x61

Definition at line 201 of file stm32100b_eval_lcd.h.

Referenced by LCD_Setup(), STM32100E_LCD_Init(), and STM3210E_LCD_Init().

#define LCD_RS_GPIO_CLK RCC_APB2Periph_GPIOD

Definition at line 104 of file stm32100b_eval_lcd.h.

Referenced by LCD_CtrlLinesConfig().

#define LCD_RS_GPIO_PORT GPIOD

Definition at line 103 of file stm32100b_eval_lcd.h.

Referenced by LCD_CtrlLinesConfig(), LCD_DeInit(), LCD_WriteRAM(), and LCD_WriteRegHX8312().

#define LCD_RS_PIN GPIO_Pin_7

Definition at line 102 of file stm32100b_eval_lcd.h.

Referenced by LCD_CtrlLinesConfig(), LCD_DeInit(), LCD_WriteRAM(), and LCD_WriteRegHX8312().

#define LCD_SPI SPI2

LCD SPI Interface pins.

Definition at line 109 of file stm32100b_eval_lcd.h.

Referenced by LCD_DeInit(), LCD_nCS_StartByte(), LCD_ReadReg(), LCD_SPIConfig(), LCD_WriteRAM(), LCD_WriteReg(), LCD_WriteRegHX8312(), LCD_WriteRegILI9320(), LCD_WriteRegIndex(), and STM32L152_LCD_DeInit().

#define LCD_SPI_CLK RCC_APB1Periph_SPI2

Definition at line 110 of file stm32100b_eval_lcd.h.

Referenced by LCD_DeInit(), LCD_SPIConfig(), and STM32L152_LCD_DeInit().

#define LCD_SPI_MISO_GPIO_CLK RCC_APB2Periph_GPIOB

Definition at line 116 of file stm32100b_eval_lcd.h.

Referenced by LCD_SPIConfig().

#define LCD_SPI_MISO_GPIO_PORT GPIOB

Definition at line 115 of file stm32100b_eval_lcd.h.

Referenced by LCD_DeInit(), LCD_SPIConfig(), and STM32L152_LCD_DeInit().

#define LCD_SPI_MISO_PIN GPIO_Pin_14

Definition at line 114 of file stm32100b_eval_lcd.h.

Referenced by LCD_DeInit(), LCD_SPIConfig(), and STM32L152_LCD_DeInit().

#define LCD_SPI_MOSI_GPIO_CLK RCC_APB2Periph_GPIOB

Definition at line 119 of file stm32100b_eval_lcd.h.

Referenced by LCD_SPIConfig().

#define LCD_SPI_MOSI_GPIO_PORT GPIOB

Definition at line 118 of file stm32100b_eval_lcd.h.

Referenced by LCD_DeInit(), LCD_SPIConfig(), and STM32L152_LCD_DeInit().

#define LCD_SPI_MOSI_PIN GPIO_Pin_15

Definition at line 117 of file stm32100b_eval_lcd.h.

Referenced by LCD_DeInit(), LCD_SPIConfig(), and STM32L152_LCD_DeInit().

#define LCD_SPI_SCK_GPIO_CLK RCC_APB2Periph_GPIOB

Definition at line 113 of file stm32100b_eval_lcd.h.

Referenced by LCD_SPIConfig().

#define LCD_SPI_SCK_GPIO_PORT GPIOB

Definition at line 112 of file stm32100b_eval_lcd.h.

Referenced by LCD_DeInit(), LCD_SPIConfig(), and STM32L152_LCD_DeInit().

#define LCD_SPI_SCK_PIN GPIO_Pin_13

Definition at line 111 of file stm32100b_eval_lcd.h.

Referenced by LCD_DeInit(), LCD_SPIConfig(), and STM32L152_LCD_DeInit().


STM32F10x Standard Peripherals Firmware Library: STM32100B_EVAL_LCD_Exported_Macros

Defines

STM32100B_EVAL_LCD_Exported_Macros

STM32100B_EVAL_LCD

Defines

#define ASSEMBLE_RGB(R, G, B) ((((R)& 0xF8) << 8) | (((G) & 0xFC) << 3) | (((B) & 0xF8) >> 3))

Define Documentation

#define ASSEMBLE_RGB | ( | R,
 |  | G,
 |  | B
 | ) | ((((R)& 0xF8) << 8) | (((G) & 0xFC) << 3) | (((B) & 0xF8) >> 3))

Definition at line 311 of file stm32100b_eval_lcd.h.


STM32F10x Standard Peripherals Firmware Library: STM32100B_EVAL_LCD_Exported_Functions

Functions

STM32100B_EVAL_LCD_Exported_Functions

STM32100B_EVAL_LCD

Functions

void | LCD_Clear (uint16_t Color)
Clears the hole LCD.
void | LCD_ClearLine (uint8_t Line)
Clears the selected line.
void | LCD_ClosedPolyLine (pPoint Points, uint16_t PointCount)
Displays a closed polyline (between many points).
void | LCD_ClosedPolyLineRelative (pPoint Points, uint16_t PointCount)
Displays a closed relative polyline (between many points).
void | LCD_CtrlLinesConfig (void)
Configures LCD control lines in Output Push-Pull mode.
void | LCD_CtrlLinesWrite (GPIO_TypeDef *GPIOx, uint16_t CtrlPins, BitAction BitVal)
Sets or reset LCD control lines.
void | LCD_DeInit (void)
DeInitializes the LCD.
void | LCD_DisplayChar (uint8_t Line, uint16_t Column, uint8_t Ascii)
Displays one character (16dots width, 24dots height).
void | LCD_DisplayOff (void)
Disables the Display.
void | LCD_DisplayOn (void)
Enables the Display.
void | LCD_DisplayStringLine (uint8_t Line, uint8_t *ptr)
Displays a maximum of 20 char on the LCD.
void | LCD_DrawBMP (uint32_t BmpAddress)
void | LCD_DrawChar (uint8_t Xpos, uint16_t Ypos, const uint16_t *c)
Draws a character on LCD.
void | LCD_DrawCircle (uint8_t Xpos, uint16_t Ypos, uint16_t Radius)
Displays a circle.
void | LCD_DrawFullCircle (uint16_t Xpos, uint16_t Ypos, uint16_t Radius)
Displays a full circle.
void | LCD_DrawFullRect (uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height)
Displays a full rectangle.
void | LCD_DrawLine (uint8_t Xpos, uint16_t Ypos, uint16_t Length, uint8_t Direction)
Displays a line.
void | LCD_DrawMonoPict (const uint32_t *Pict)
Displays a monocolor picture.
void | LCD_DrawRect (uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width)
Displays a rectangle.
void | LCD_DrawUniLine (uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2)
Displays an uni line (between two points).
void | LCD_FillPolyLine (pPoint Points, uint16_t PointCount)
Displays a full polyline (between many points).
void | LCD_GetColors (__IO uint16_t *_TextColor, __IO uint16_t *_BackColor)
Gets the LCD Text and Background colors.
sFONT * | LCD_GetFont (void)
Gets the Text Font.
void | LCD_nCS_StartByte (uint8_t Start_Byte)
Reset LCD control line(/CS) and Send Start-Byte.
void | LCD_PolyLine (pPoint Points, uint16_t PointCount)
Displays an polyline (between many points).
void | LCD_PolyLineRelative (pPoint Points, uint16_t PointCount)
Displays a relative polyline (between many points).
void | LCD_PowerOn (void)
Power on the LCD.
uint16_t | LCD_ReadReg (uint8_t LCD_Reg)
Reads the selected LCD Register.
void | LCD_SetBackColor (__IO uint16_t Color)
Sets the Background color.
void | LCD_SetColors (__IO uint16_t _TextColor, __IO uint16_t _BackColor)
Sets the LCD Text and Background colors.
void | LCD_SetCursor (uint8_t Xpos, uint16_t Ypos)
Sets the cursor position.
void | LCD_SetDisplayWindow (uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width)
Sets a display window.
void | LCD_SetFont (sFONT *fonts)
Sets the Text Font.
void | LCD_SetTextColor (__IO uint16_t Color)
Sets the Text color.
void | LCD_Setup (void)
Setups the LCD.
void | LCD_SPIConfig (void)
Configures the LCD_SPI interface.
void | LCD_WindowModeDisable (void)
Disables LCD Window mode.
void | LCD_WriteRAM (uint16_t RGB_Code)
Writes to the LCD RAM.
void | LCD_WriteRAM_Prepare (void)
Prepare to write to the LCD RAM.
void | LCD_WriteRAMWord (uint16_t RGB_Code)
Writes 1 word to the LCD RAM.
void | LCD_WriteReg (uint8_t LCD_Reg, uint16_t LCD_RegValue)
Writes to the selected LCD register.
void | LCD_WriteRegIndex (uint8_t LCD_Reg)
Writes index to select the LCD register.
void | STM32100B_LCD_Init (void)
Initializes the LCD.

Function Documentation

void LCD_Clear ( uint16_t Color )

Clears the hole LCD.

Parameters:
Color,: the color of the background.
Return values:
None

Definition at line 544 of file stm32100b_eval_lcd.c.

void LCD_ClearLine ( uint8_t Line )

Clears the selected line.

Parameters:
Line,: the Line to be cleared. This parameter can be one of the following values:

  • Linex: where x can be 0..n
Return values:
None

Definition at line 525 of file stm32100b_eval_lcd.c.

void LCD_ClosedPolyLine | ( | pPoint | Points,
 |  | uint16_t | PointCount
 | ) |  |

Displays a closed polyline (between many points).

Parameters:
Points,: pointer to the points array.
PointCount,: Number of points.
Return values:
None

Definition at line 1236 of file stm32100b_eval_lcd.c.

void LCD_ClosedPolyLineRelative | ( | pPoint | Points,
 |  | uint16_t | PointCount
 | ) |  |

Displays a closed relative polyline (between many points).

Parameters:
Points,: pointer to the points array.
PointCount,: Number of points.
Return values:
None

Definition at line 1259 of file stm32100b_eval_lcd.c.

void LCD_CtrlLinesConfig ( void )

Configures LCD control lines in Output Push-Pull mode.

Parameters:
None
Return values:
None Configures LCD control lines in Output Push-Pull mode.
Parameters:
None
Return values:
None

Definition at line 1724 of file stm32100b_eval_lcd.c.

void LCD_CtrlLinesWrite | ( | GPIO_TypeDef * | GPIOx,
 |  | uint16_t | CtrlPins,
 |  | BitAction | BitVal
 | ) |  |

Sets or reset LCD control lines.

Parameters:
GPIOx,: where x can be B or D to select the GPIO peripheral.
CtrlPins,: the Control line. This parameter can be:

  • LCD_NCS_PIN: Chip Select pin
  • LCD_NWR_PIN: Read/Write Selection pin
  • LCD_RS_PIN: Register/RAM Selection pin
BitVal,: specifies the value to be written to the selected bit. This parameter can be:

  • Bit_RESET: to clear the port pin
  • Bit_SET: to set the port pin
Return values:
None
Parameters:
GPIOx,: where x can be B or D to select the GPIO peripheral.
CtrlPins,: the Control line. This parameter can be:

  • LCD_NCS_PIN: Chip Select pin
BitVal,: specifies the value to be written to the selected bit. This parameter can be:

  • Bit_RESET: to clear the port pin
  • Bit_SET: to set the port pin
Return values:
None

Definition at line 1763 of file stm32100b_eval_lcd.c.

void LCD_DeInit ( void )

DeInitializes the LCD.

Parameters:
None
Return values:
None

< LCD Display Off

< LCD_SPI disable

< LCD_SPI DeInit

< Disable SPI clock

< LCD Display Off

< LCD_SPI DeInit

< LCD Display Off

< LCD_SPI disable

< LCD_SPI DeInit

< Disable SPI clock

< LCD Display Off

< LCD_SPI disable

< LCD_SPI DeInit

< Disable SPI clock

< LCD Display Off

< LCD_SPI DeInit

Definition at line 116 of file stm32100b_eval_lcd.c.

void LCD_DisplayChar | ( | uint8_t | Line,
 |  | uint16_t | Column,
 |  | uint8_t | Ascii
 | ) |  |

Displays one character (16dots width, 24dots height).

Parameters:
Line,: the Line where to display the character shape . This parameter can be one of the following values:

  • Linex: where x can be 0..9
Column,: start column address.
Ascii,: character ascii code, must be between 0x20 and 0x7E.
Return values:
None

Definition at line 640 of file stm32100b_eval_lcd.c.

void LCD_DisplayOff ( void )

Disables the Display.

Parameters:
None
Return values:
None

Definition at line 1702 of file stm32100b_eval_lcd.c.

void LCD_DisplayOn ( void )

Enables the Display.

Parameters:
None
Return values:
None

Definition at line 1677 of file stm32100b_eval_lcd.c.

void LCD_DisplayStringLine | ( | uint8_t | Line,
 |  | uint8_t * | ptr
 | ) |  |

Displays a maximum of 20 char on the LCD.

Parameters:
Line,: the Line where to display the character shape . This parameter can be one of the following values:

  • Linex: where x can be 0..9
*ptr,: pointer to string to display on LCD.
Return values:
None

Definition at line 655 of file stm32100b_eval_lcd.c.

void LCD_DrawBMP ( uint32_t BmpAddress )
void LCD_DrawChar | ( | uint8_t | Xpos,
 |  | uint16_t | Ypos,
 |  | const uint16_t * | c
 | ) |  |

Draws a character on LCD.

Parameters:
Xpos,: the Line where to display the character shape.
Ypos,: start column address.
c,: pointer to the character data.
Return values:
None

Definition at line 593 of file stm32100b_eval_lcd.c.

void LCD_DrawCircle | ( | uint8_t | Xpos,
 |  | uint16_t | Ypos,
 |  | uint16_t | Radius
 | ) |  |

Displays a circle.

Parameters:
Xpos,: specifies the X position.
Ypos,: specifies the Y position.
Radius
Return values:
None

Definition at line 817 of file stm32100b_eval_lcd.c.

void LCD_DrawFullCircle | ( | uint16_t | Xpos,
 |  | uint16_t | Ypos,
 |  | uint16_t | Radius
 | ) |  |

Displays a full circle.

Parameters:
Xpos,: specifies the X position.
Ypos,: specifies the Y position.
Radius
Return values:
None

Definition at line 1057 of file stm32100b_eval_lcd.c.

void LCD_DrawFullRect | ( | uint16_t | Xpos,
 |  | uint16_t | Ypos,
 |  | uint16_t | Width,
 |  | uint16_t | Height
 | ) |  |

Displays a full rectangle.

Parameters:
Xpos,: specifies the X position.
Ypos,: specifies the Y position.
Height,: rectangle height.
Width,: rectangle width.
Return values:
None

Definition at line 1026 of file stm32100b_eval_lcd.c.

void LCD_DrawLine | ( | uint8_t | Xpos,
 |  | uint16_t | Ypos,
 |  | uint16_t | Length,
 |  | uint8_t | Direction
 | ) |  |

Displays a line.

Parameters:
Xpos,: specifies the X position.
Ypos,: specifies the Y position.
Length,: line length.
Direction,: line direction. This parameter can be one of the following values: Vertical or Horizontal.
Return values:
None

Definition at line 753 of file stm32100b_eval_lcd.c.

void LCD_DrawMonoPict ( const uint32_t * Pict )

Displays a monocolor picture.

Parameters:
Pict,: pointer to the picture array.
Return values:
None

Definition at line 926 of file stm32100b_eval_lcd.c.

void LCD_DrawRect | ( | uint8_t | Xpos,
 |  | uint16_t | Ypos,
 |  | uint8_t | Height,
 |  | uint16_t | Width
 | ) |  |

Displays a rectangle.

Parameters:
Xpos,: specifies the X position.
Ypos,: specifies the Y position.
Height,: display rectangle height.
Width,: display rectangle width.
Return values:
None

Definition at line 800 of file stm32100b_eval_lcd.c.

void LCD_DrawUniLine | ( | uint16_t | x1,
 |  | uint16_t | y1,
 |  | uint16_t | x2,
 |  | uint16_t | y2
 | ) |  |

Displays an uni line (between two points).

Parameters:
x1,: specifies the point 1 x position.
y1,: specifies the point 1 y position.
x2,: specifies the point 2 x position.
y2,: specifies the point 2 y position.
Return values:
None

Definition at line 1107 of file stm32100b_eval_lcd.c.

void LCD_FillPolyLine | ( | pPoint | Points,
 |  | uint16_t | PointCount
 | ) |  |

Displays a full polyline (between many points).

Parameters:
Points,: pointer to the points array.
PointCount,: Number of points.
Return values:
None

Definition at line 1271 of file stm32100b_eval_lcd.c.

void LCD_GetColors | ( | __IO uint16_t * | _TextColor,
 |  | __IO uint16_t * | _BackColor
 | ) |  |

Gets the LCD Text and Background colors.

Parameters:
_TextColor,: pointer to the variable that will contain the Text Color.
_BackColor,: pointer to the variable that will contain the Background Color.
Return values:
None

Definition at line 472 of file stm32100b_eval_lcd.c.

sFONT* LCD_GetFont ( void )

Gets the Text Font.

Parameters:
None.
Return values:
the used font.

Definition at line 513 of file stm32100b_eval_lcd.c.

void LCD_nCS_StartByte ( uint8_t Start_Byte )

Reset LCD control line(/CS) and Send Start-Byte.

Parameters:
Start_Byte,: the Start-Byte to be sent
Return values:
None

Definition at line 1377 of file stm32100b_eval_lcd.c.

void LCD_PolyLine | ( | pPoint | Points,
 |  | uint16_t | PointCount
 | ) |  |

Displays an polyline (between many points).

Parameters:
Points,: pointer to the points array.
PointCount,: Number of points.
Return values:
None

Definition at line 1180 of file stm32100b_eval_lcd.c.

void LCD_PolyLineRelative | ( | pPoint | Points,
 |  | uint16_t | PointCount
 | ) |  |

Displays a relative polyline (between many points).

Parameters:
Points,: pointer to the points array.
PointCount,: Number of points.
Return values:
None

Definition at line 1248 of file stm32100b_eval_lcd.c.

void LCD_PowerOn ( void )

Power on the LCD.

Parameters:
None
Return values:
None

Definition at line 1629 of file stm32100b_eval_lcd.c.

uint16_t LCD_ReadReg ( uint8_t LCD_Reg )

Reads the selected LCD Register.

Parameters:
LCD_Reg,: address of the selected register.
Return values:
LCD Register Value.
Parameters:
None
Return values:
LCD Register Value.

Definition at line 1452 of file stm32100b_eval_lcd.c.

void LCD_SetBackColor ( __IO uint16_t Color )

Sets the Background color.

Parameters:
Color,: specifies the Background color code RGB(5-6-5).
Return values:
None

Definition at line 493 of file stm32100b_eval_lcd.c.

void LCD_SetColors | ( | __IO uint16_t | _TextColor,
 |  | __IO uint16_t | _BackColor
 | ) |  |

Sets the LCD Text and Background colors.

Parameters:
_TextColor,: specifies the Text Color.
_BackColor,: specifies the Background Color.
Return values:
None

Definition at line 458 of file stm32100b_eval_lcd.c.

void LCD_SetCursor | ( | uint8_t | Xpos,
 |  | uint16_t | Ypos
 | ) |  |

Sets the cursor position.

Parameters:
Xpos,: specifies the X position.
Ypos,: specifies the Y position.
Return values:
None

Definition at line 570 of file stm32100b_eval_lcd.c.

void LCD_SetDisplayWindow | ( | uint8_t | Xpos,
 |  | uint16_t | Ypos,
 |  | uint8_t | Height,
 |  | uint16_t | Width
 | ) |  |

Sets a display window.

Parameters:
Xpos,: specifies the X buttom left position.
Ypos,: specifies the Y buttom left position.
Height,: display window height.
Width,: display window width.
Return values:
None

Definition at line 680 of file stm32100b_eval_lcd.c.

void LCD_SetFont ( sFONT * fonts )

Sets the Text Font.

Parameters:
fonts,: specifies the font to be used.
Return values:
None

Definition at line 503 of file stm32100b_eval_lcd.c.

void LCD_SetTextColor ( __IO uint16_t Color )

Sets the Text color.

Parameters:
Color,: specifies the Text color code RGB(5-6-5).
Return values:
None

Definition at line 482 of file stm32100b_eval_lcd.c.

void LCD_Setup ( void )

Setups the LCD.

Parameters:
None
Return values:
None

Definition at line 160 of file stm32100b_eval_lcd.c.

void LCD_SPIConfig ( void )

Configures the LCD_SPI interface.

Parameters:
None
Return values:
None

Definition at line 1775 of file stm32100b_eval_lcd.c.

void LCD_WindowModeDisable ( void )

Disables LCD Window mode.

Parameters:
None
Return values:
None

Definition at line 729 of file stm32100b_eval_lcd.c.

void LCD_WriteRAM ( uint16_t RGB_Code )

Writes to the LCD RAM.

Parameters:
RGB_Code,: the pixel color in RGB mode (5-6-5).
Return values:
None

Definition at line 1594 of file stm32100b_eval_lcd.c.

void LCD_WriteRAM_Prepare ( void )

Prepare to write to the LCD RAM.

Parameters:
None
Return values:
None

Definition at line 1518 of file stm32100b_eval_lcd.c.

void LCD_WriteRAMWord ( uint16_t RGB_Code )

Writes 1 word to the LCD RAM.

Parameters:
RGB_Code,: the pixel color in RGB mode (5-6-5).
Return values:
None

Definition at line 1532 of file stm32100b_eval_lcd.c.

void LCD_WriteReg | ( | uint8_t | LCD_Reg,
 |  | uint16_t | LCD_RegValue
 | ) |  |

Writes to the selected LCD register.

Parameters:
LCD_Reg,: address of the selected register.
LCD_RegValue,: value to write to the selected register.
Return values:
None Writes to the selected LCD register.
Parameters:
LCD_Reg,: address of the selected register.
LCD_RegValue,: value to write to the selected register.
Return values:
None

Definition at line 1576 of file stm32100b_eval_lcd.c.

void LCD_WriteRegIndex ( uint8_t LCD_Reg )

Writes index to select the LCD register.

Parameters:
LCD_Reg,: address of the selected register.
Return values:
None

Definition at line 1394 of file stm32100b_eval_lcd.c.

void STM32100B_LCD_Init ( void )

Initializes the LCD.

Parameters:
None
Return values:
None

Definition at line 427 of file stm32100b_eval_lcd.c.

References LCD_DEFAULT_FONT, LCD_HX8312, LCD_ILI9320, LCD_ReadReg(), LCD_REG_0, LCD_SetFont(), LCD_Setup(), LCD_SPFD5408, and LCDType.

Referenced by main().


STM32F10x Standard Peripherals Firmware Library: STM32100E_EVAL_LOW_LEVEL_Private_TypesDefinitions

STM32100E_EVAL_LOW_LEVEL_Private_TypesDefinitions

STM32100E_EVAL_LOW_LEVEL


STM32F10x Standard Peripherals Firmware Library: STM32100E_EVAL_LOW_LEVEL_Private_Defines

STM32100E_EVAL_LOW_LEVEL_Private_Defines

STM32100E_EVAL_LOW_LEVEL


STM32F10x Standard Peripherals Firmware Library: STM32100E_EVAL_LOW_LEVEL_Private_Macros

STM32100E_EVAL_LOW_LEVEL_Private_Macros

STM32100E_EVAL_LOW_LEVEL


STM32F10x Standard Peripherals Firmware Library: STM32100E_EVAL_LOW_LEVEL_Private_Variables

Variables

STM32100E_EVAL_LOW_LEVEL_Private_Variables

STM32100E_EVAL_LOW_LEVEL

Variables

const uint32_t | BUTTON_CLK [BUTTONn]
const uint16_t | BUTTON_EXTI_LINE [BUTTONn]
const uint16_t | BUTTON_IRQn [BUTTONn]
const uint16_t | BUTTON_PIN [BUTTONn]
const uint16_t | BUTTON_PIN_SOURCE [BUTTONn]
GPIO_TypeDef * | BUTTON_PORT [BUTTONn]
const uint16_t | BUTTON_PORT_SOURCE [BUTTONn]
const uint16_t | COM_RX_PIN [COMn] = {EVAL_COM1_RX_PIN, EVAL_COM2_RX_PIN}
GPIO_TypeDef * | COM_RX_PORT [COMn] = {EVAL_COM1_RX_GPIO_PORT, EVAL_COM2_RX_GPIO_PORT}
const uint32_t | COM_RX_PORT_CLK [COMn] = {EVAL_COM1_RX_GPIO_CLK, EVAL_COM2_RX_GPIO_CLK}
const uint16_t | COM_TX_PIN [COMn] = {EVAL_COM1_TX_PIN, EVAL_COM2_TX_PIN}
GPIO_TypeDef * | COM_TX_PORT [COMn] = {EVAL_COM1_TX_GPIO_PORT, EVAL_COM2_TX_GPIO_PORT}
const uint32_t | COM_TX_PORT_CLK [COMn] = {EVAL_COM1_TX_GPIO_CLK, EVAL_COM2_TX_GPIO_CLK}
USART_TypeDef * | COM_USART [COMn] = {EVAL_COM1, EVAL_COM2}
const uint32_t | COM_USART_CLK [COMn] = {EVAL_COM1_CLK, EVAL_COM2_CLK}
const uint32_t | GPIO_CLK [LEDn]
const uint16_t | GPIO_PIN [LEDn]
GPIO_TypeDef * | GPIO_PORT [LEDn]
DMA_InitTypeDef sEEDMA_InitStructure

Variable Documentation

const uint32_t BUTTON_CLK[BUTTONn]
Initial value:
 {WAKEUP_BUTTON_GPIO_CLK, TAMPER_BUTTON_GPIO_CLK,
                                      KEY_BUTTON_GPIO_CLK, RIGHT_BUTTON_GPIO_CLK,
                                      LEFT_BUTTON_GPIO_CLK, UP_BUTTON_GPIO_CLK,
                                      DOWN_BUTTON_GPIO_CLK, SEL_BUTTON_GPIO_CLK}

Definition at line 96 of file stm32100e_eval.c.

const uint16_t BUTTON_EXTI_LINE[BUTTONn]
Initial value:
 {WAKEUP_BUTTON_EXTI_LINE,
                                            TAMPER_BUTTON_EXTI_LINE,
                                            KEY_BUTTON_EXTI_LINE,
                                            RIGHT_BUTTON_EXTI_LINE,
                                            LEFT_BUTTON_EXTI_LINE,
                                            UP_BUTTON_EXTI_LINE,
                                            DOWN_BUTTON_EXTI_LINE,
                                            SEL_BUTTON_EXTI_LINE}

Definition at line 101 of file stm32100e_eval.c.

const uint16_t BUTTON_IRQn[BUTTONn]
Initial value:
 {WAKEUP_BUTTON_EXTI_IRQn, TAMPER_BUTTON_EXTI_IRQn,
                                       KEY_BUTTON_EXTI_IRQn, RIGHT_BUTTON_EXTI_IRQn,
                                       LEFT_BUTTON_EXTI_IRQn, UP_BUTTON_EXTI_IRQn,
                                       DOWN_BUTTON_EXTI_IRQn, SEL_BUTTON_EXTI_IRQn}

Definition at line 128 of file stm32100e_eval.c.

const uint16_t BUTTON_PIN[BUTTONn]
Initial value:
 {WAKEUP_BUTTON_PIN, TAMPER_BUTTON_PIN,
                                      KEY_BUTTON_PIN, RIGHT_BUTTON_PIN,
                                      LEFT_BUTTON_PIN, UP_BUTTON_PIN,
                                      DOWN_BUTTON_PIN, SEL_BUTTON_PIN}

Definition at line 91 of file stm32100e_eval.c.

const uint16_t BUTTON_PIN_SOURCE[BUTTONn]
Initial value:
 {WAKEUP_BUTTON_EXTI_PIN_SOURCE,
                                             TAMPER_BUTTON_EXTI_PIN_SOURCE,
                                             KEY_BUTTON_EXTI_PIN_SOURCE,
                                             RIGHT_BUTTON_EXTI_PIN_SOURCE,
                                             LEFT_BUTTON_EXTI_PIN_SOURCE,
                                             UP_BUTTON_EXTI_PIN_SOURCE,
                                             DOWN_BUTTON_EXTI_PIN_SOURCE,
                                             SEL_BUTTON_EXTI_PIN_SOURCE}

Definition at line 119 of file stm32100e_eval.c.

GPIO_TypeDef* BUTTON_PORT[BUTTONn]
Initial value:
 {WAKEUP_BUTTON_GPIO_PORT, TAMPER_BUTTON_GPIO_PORT,
                                      KEY_BUTTON_GPIO_PORT, RIGHT_BUTTON_GPIO_PORT,
                                      LEFT_BUTTON_GPIO_PORT, UP_BUTTON_GPIO_PORT,
                                      DOWN_BUTTON_GPIO_PORT, SEL_BUTTON_GPIO_PORT}

Definition at line 86 of file stm32100e_eval.c.

const uint16_t BUTTON_PORT_SOURCE[BUTTONn]
Initial value:
 {WAKEUP_BUTTON_EXTI_PORT_SOURCE,
                                              TAMPER_BUTTON_EXTI_PORT_SOURCE,
                                              KEY_BUTTON_EXTI_PORT_SOURCE,
                                              RIGHT_BUTTON_EXTI_PORT_SOURCE,
                                              LEFT_BUTTON_EXTI_PORT_SOURCE,
                                              UP_BUTTON_EXTI_PORT_SOURCE,
                                              DOWN_BUTTON_EXTI_PORT_SOURCE,
                                              SEL_BUTTON_EXTI_PORT_SOURCE}

Definition at line 110 of file stm32100e_eval.c.

const uint16_t COM_RX_PIN[COMn] = {EVAL_COM1_RX_PIN, EVAL_COM2_RX_PIN}

Definition at line 147 of file stm32100e_eval.c.

GPIO_TypeDef* COM_RX_PORT[COMn] = {EVAL_COM1_RX_GPIO_PORT, EVAL_COM2_RX_GPIO_PORT}

Definition at line 137 of file stm32100e_eval.c.

const uint32_t COM_RX_PORT_CLK[COMn] = {EVAL_COM1_RX_GPIO_CLK, EVAL_COM2_RX_GPIO_CLK}

Definition at line 143 of file stm32100e_eval.c.

const uint16_t COM_TX_PIN[COMn] = {EVAL_COM1_TX_PIN, EVAL_COM2_TX_PIN}

Definition at line 145 of file stm32100e_eval.c.

GPIO_TypeDef* COM_TX_PORT[COMn] = {EVAL_COM1_TX_GPIO_PORT, EVAL_COM2_TX_GPIO_PORT}

Definition at line 135 of file stm32100e_eval.c.

const uint32_t COM_TX_PORT_CLK[COMn] = {EVAL_COM1_TX_GPIO_CLK, EVAL_COM2_TX_GPIO_CLK}

Definition at line 141 of file stm32100e_eval.c.

USART_TypeDef* COM_USART[COMn] = {EVAL_COM1, EVAL_COM2}

Definition at line 133 of file stm32100e_eval.c.

const uint32_t COM_USART_CLK[COMn] = {EVAL_COM1_CLK, EVAL_COM2_CLK}

Definition at line 139 of file stm32100e_eval.c.

const uint32_t GPIO_CLK[LEDn]
Initial value:
 {LED1_GPIO_CLK, LED2_GPIO_CLK, LED3_GPIO_CLK,
                                 LED4_GPIO_CLK}

Definition at line 83 of file stm32100e_eval.c.

const uint16_t GPIO_PIN[LEDn]
Initial value:
 {LED1_PIN, LED2_PIN, LED3_PIN,
                                 LED4_PIN}

Definition at line 81 of file stm32100e_eval.c.

GPIO_TypeDef* GPIO_PORT[LEDn]
Initial value:
 {LED1_GPIO_PORT, LED2_GPIO_PORT, LED3_GPIO_PORT,
                                 LED4_GPIO_PORT}

Definition at line 79 of file stm32100e_eval.c.

DMA_InitTypeDef sEEDMA_InitStructure

Definition at line 149 of file stm32100e_eval.c.


STM32F10x Standard Peripherals Firmware Library: STM32100E_EVAL_LOW_LEVEL_Private_FunctionPrototypes

STM32100E_EVAL_LOW_LEVEL_Private_FunctionPrototypes

STM32100E_EVAL_LOW_LEVEL


STM32F10x Standard Peripherals Firmware Library: STM32100E_EVAL_LOW_LEVEL_Private_Functions

Functions

STM32100E_EVAL_LOW_LEVEL_Private_Functions

STM32100E_EVAL_LOW_LEVEL

Functions

void | LM75_LowLevel_DeInit (void)
DeInitializes the LM75_I2C.
void | LM75_LowLevel_Init (void)
Initializes the LM75_I2C.
void | SD_LowLevel_DeInit (void)
DeInitializes the SD/SD communication.
void | SD_LowLevel_Init (void)
Initializes the SD_SPI and CS pins.
void | sEE_LowLevel_DeInit (void)
DeInitializes peripherals used by the I2C EEPROM driver.
void | sEE_LowLevel_DMAConfig (uint32_t pBuffer, uint32_t BufferSize, uint32_t Direction)
Initializes DMA channel used by the I2C EEPROM driver.
void | sEE_LowLevel_Init (void)
Initializes peripherals used by the I2C EEPROM driver.
void | sFLASH_LowLevel_DeInit (void)
DeInitializes the peripherals used by the SPI FLASH driver.
void | sFLASH_LowLevel_Init (void)
Initializes the peripherals used by the SPI FLASH driver.
void | STM_EVAL_COMInit (COM_TypeDef COM, USART_InitTypeDef *USART_InitStruct)
Configures COM port.
void | STM_EVAL_LEDInit (Led_TypeDef Led)
Configures LED GPIO.
void | STM_EVAL_LEDOff (Led_TypeDef Led)
Turns selected LED Off.
void | STM_EVAL_LEDOn (Led_TypeDef Led)
Turns selected LED On.
void | STM_EVAL_LEDToggle (Led_TypeDef Led)
Toggles the selected LED.
uint32_t | STM_EVAL_PBGetState (Button_TypeDef Button)
Returns the selected Button state.
void | STM_EVAL_PBInit (Button_TypeDef Button, ButtonMode_TypeDef Button_Mode)
Configures Button GPIO and EXTI Line.

Function Documentation

void LM75_LowLevel_DeInit ( void )

DeInitializes the LM75_I2C.

Parameters:
None
Return values:
None

< Disable LM75_I2C

< DeInitializes the LM75_I2C

< LM75_I2C Periph clock disable

< Configure LM75_I2C pins: SCL

< Configure LM75_I2C pins: SDA

< Configure LM75_I2C pin: SMBUS ALERT

Definition at line 683 of file stm32100e_eval.c.

References DISABLE, GPIO_Init(), GPIO_InitStructure, GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_IN_FLOATING, GPIO_InitTypeDef::GPIO_Pin, I2C_Cmd(), I2C_DeInit(), LM75_I2C, LM75_I2C_CLK, LM75_I2C_SCL_GPIO_PORT, LM75_I2C_SCL_PIN, LM75_I2C_SDA_GPIO_PORT, LM75_I2C_SDA_PIN, LM75_I2C_SMBUSALERT_GPIO_PORT, LM75_I2C_SMBUSALERT_PIN, and RCC_APB1PeriphClockCmd().

void LM75_LowLevel_Init ( void )

Initializes the LM75_I2C.

Parameters:
None
Return values:
None

< LM75_I2C Periph clock enable

< LM75_I2C_SCL_GPIO_CLK, LM75_I2C_SDA_GPIO_CLK and LM75_I2C_SMBUSALERT_GPIO_CLK Periph clock enable

< Configure LM75_I2C pins: SCL

< Configure LM75_I2C pins: SDA

< Configure LM75_I2C pin: SMBUS ALERT

Definition at line 714 of file stm32100e_eval.c.

References ENABLE, GPIO_Init(), GPIO_InitStructure, GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_AF_OD, GPIO_Mode_IPU, GPIO_InitTypeDef::GPIO_Pin, GPIO_InitTypeDef::GPIO_Speed, GPIO_Speed_50MHz, LM75_I2C_CLK, LM75_I2C_SCL_GPIO_CLK, LM75_I2C_SCL_GPIO_PORT, LM75_I2C_SCL_PIN, LM75_I2C_SDA_GPIO_CLK, LM75_I2C_SDA_GPIO_PORT, LM75_I2C_SDA_PIN, LM75_I2C_SMBUSALERT_GPIO_CLK, LM75_I2C_SMBUSALERT_GPIO_PORT, LM75_I2C_SMBUSALERT_PIN, RCC_APB1PeriphClockCmd(), and RCC_APB2PeriphClockCmd().

void SD_LowLevel_DeInit ( void )

DeInitializes the SD/SD communication.

Parameters:
None
Return values:
None

< SD_SPI disable

< DeInitializes the SD_SPI

< SD_SPI Periph clock disable

< Configure SD_SPI pins: SCK

< Configure SD_SPI pins: MISO

< Configure SD_SPI pins: MOSI

< Configure SD_SPI_CS_PIN pin: SD Card CS pin

< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin

Definition at line 372 of file stm32100e_eval.c.

References DISABLE, GPIO_Init(), GPIO_InitStructure, GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_IN_FLOATING, GPIO_InitTypeDef::GPIO_Pin, RCC_APB1PeriphClockCmd(), SD_CS_GPIO_PORT, SD_CS_PIN, SD_DETECT_GPIO_PORT, SD_DETECT_PIN, SD_SPI, SD_SPI_CLK, SD_SPI_MISO_GPIO_PORT, SD_SPI_MISO_PIN, SD_SPI_MOSI_GPIO_PORT, SD_SPI_MOSI_PIN, SD_SPI_SCK_GPIO_PORT, SD_SPI_SCK_PIN, SPI_Cmd(), and SPI_I2S_DeInit().

void SD_LowLevel_Init ( void )

Initializes the SD_SPI and CS pins.

Parameters:
None
Return values:
None

< SD_SPI_CS_GPIO, SD_SPI_MOSI_GPIO, SD_SPI_MISO_GPIO, SD_SPI_DETECT_GPIO and SD_SPI_SCK_GPIO Periph clock enable

< SD_SPI Periph clock enable

< Configure SD_SPI pins: SCK

< Configure SD_SPI pins: MOSI

< Configure SD_SPI pins: MISO

< Configure SD_SPI_CS_PIN pin: SD Card CS pin

< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin

< SD_SPI Config

< SD_SPI enable

Definition at line 409 of file stm32100e_eval.c.

References ENABLE, GPIO_Init(), GPIO_InitStructure, GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_AF_PP, GPIO_Mode_IPU, GPIO_Mode_Out_PP, GPIO_InitTypeDef::GPIO_Pin, GPIO_InitTypeDef::GPIO_Speed, GPIO_Speed_50MHz, RCC_APB1PeriphClockCmd(), RCC_APB2PeriphClockCmd(), SD_CS_GPIO_CLK, SD_CS_GPIO_PORT, SD_CS_PIN, SD_DETECT_GPIO_CLK, SD_DETECT_GPIO_PORT, SD_DETECT_PIN, SD_SPI, SD_SPI_CLK, SD_SPI_MISO_GPIO_CLK, SD_SPI_MISO_GPIO_PORT, SD_SPI_MISO_PIN, SD_SPI_MOSI_GPIO_CLK, SD_SPI_MOSI_GPIO_PORT, SD_SPI_MOSI_PIN, SD_SPI_SCK_GPIO_CLK, SD_SPI_SCK_GPIO_PORT, SD_SPI_SCK_PIN, SPI_InitTypeDef::SPI_BaudRatePrescaler, SPI_BaudRatePrescaler_2, SPI_Cmd(), SPI_InitTypeDef::SPI_CPHA, SPI_CPHA_2Edge, SPI_InitTypeDef::SPI_CPOL, SPI_CPOL_High, SPI_InitTypeDef::SPI_CRCPolynomial, SPI_InitTypeDef::SPI_DataSize, SPI_DataSize_8b, SPI_InitTypeDef::SPI_Direction, SPI_Direction_2Lines_FullDuplex, SPI_InitTypeDef::SPI_FirstBit, SPI_FirstBit_MSB, SPI_Init(), SPI_InitStructure, SPI_InitTypeDef::SPI_Mode, SPI_Mode_Master, SPI_InitTypeDef::SPI_NSS, and SPI_NSS_Soft.

void sEE_LowLevel_DeInit ( void )

DeInitializes peripherals used by the I2C EEPROM driver.

Parameters:
None
Return values:
None

< sEE_I2C Periph clock disable

< GPIO configuration

< Configure sEE_I2C pins: SCL

< Configure sEE_I2C pins: SDA

Definition at line 466 of file stm32100e_eval.c.

Referenced by sEE_DeInit().

void sEE_LowLevel_DMAConfig | ( | uint32_t | pBuffer,
 |  | uint32_t | BufferSize,
 |  | uint32_t | Direction
 | ) |  |

Initializes DMA channel used by the I2C EEPROM driver.

Parameters:
None
Return values:
None

Definition at line 583 of file stm32100e_eval.c.

Referenced by sEE_ReadBuffer(), and sEE_WritePage().

void sEE_LowLevel_Init ( void )

Initializes peripherals used by the I2C EEPROM driver.

Parameters:
None
Return values:
None

< sEE_I2C_SCL_GPIO_CLK and sEE_I2C_SDA_GPIO_CLK Periph clock enable

< sEE_I2C Periph clock enable

< GPIO configuration

< Configure sEE_I2C pins: SCL

< Configure sEE_I2C pins: SDA

< I2C DMA TX and RX channels configuration

Definition at line 515 of file stm32100e_eval.c.

Referenced by sEE_Init().

void sFLASH_LowLevel_DeInit ( void )

DeInitializes the peripherals used by the SPI FLASH driver.

Parameters:
None
Return values:
None

< Disable the sFLASH_SPI

< DeInitializes the sFLASH_SPI

< sFLASH_SPI Periph clock disable

< Configure sFLASH_SPI pins: SCK

< Configure sFLASH_SPI pins: MISO

< Configure sFLASH_SPI pins: MOSI

< Configure sFLASH_CS_PIN pin: sFLASH Card CS pin

Definition at line 609 of file stm32100e_eval.c.

References DISABLE, GPIO_Init(), GPIO_InitStructure, GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_IN_FLOATING, GPIO_InitTypeDef::GPIO_Pin, RCC_APB2PeriphClockCmd(), sFLASH_CS_GPIO_PORT, sFLASH_CS_PIN, sFLASH_SPI, sFLASH_SPI_CLK, sFLASH_SPI_MISO_GPIO_PORT, sFLASH_SPI_MISO_PIN, sFLASH_SPI_MOSI_GPIO_PORT, sFLASH_SPI_MOSI_PIN, sFLASH_SPI_SCK_GPIO_PORT, sFLASH_SPI_SCK_PIN, SPI_Cmd(), and SPI_I2S_DeInit().

void sFLASH_LowLevel_Init ( void )

Initializes the peripherals used by the SPI FLASH driver.

Parameters:
None
Return values:
None

< sFLASH_SPI_CS_GPIO, sFLASH_SPI_MOSI_GPIO, sFLASH_SPI_MISO_GPIO and sFLASH_SPI_SCK_GPIO Periph clock enable

< sFLASH_SPI Periph clock enable

< Configure sFLASH_SPI pins: SCK

< Configure sFLASH_SPI pins: MOSI

< Configure sFLASH_SPI pins: MISO

< Configure sFLASH_CS_PIN pin: sFLASH Card CS pin

Definition at line 645 of file stm32100e_eval.c.

References ENABLE, GPIO_Init(), GPIO_InitStructure, GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_AF_PP, GPIO_Mode_IN_FLOATING, GPIO_Mode_Out_PP, GPIO_InitTypeDef::GPIO_Pin, GPIO_InitTypeDef::GPIO_Speed, GPIO_Speed_50MHz, RCC_APB2PeriphClockCmd(), sFLASH_CS_GPIO_CLK, sFLASH_CS_GPIO_PORT, sFLASH_CS_PIN, sFLASH_SPI_CLK, sFLASH_SPI_MISO_GPIO_CLK, sFLASH_SPI_MISO_GPIO_PORT, sFLASH_SPI_MISO_PIN, sFLASH_SPI_MOSI_GPIO_CLK, sFLASH_SPI_MOSI_GPIO_PORT, sFLASH_SPI_MOSI_PIN, sFLASH_SPI_SCK_GPIO_CLK, sFLASH_SPI_SCK_GPIO_PORT, and sFLASH_SPI_SCK_PIN.

void STM_EVAL_COMInit | ( | COM_TypeDef | COM,
 |  | USART_InitTypeDef * | USART_InitStruct
 | ) |  |

Configures COM port.

Parameters:
COM,: Specifies the COM port to be configured. This parameter can be one of following parameters:

  • COM1
  • COM2
USART_InitStruct,: pointer to a USART_InitTypeDef structure that contains the configuration information for the specified USART peripheral.
Return values:
None

Definition at line 332 of file stm32100e_eval.c.

References COM1, COM_RX_PIN, COM_RX_PORT_CLK, COM_TX_PIN, COM_TX_PORT_CLK, COM_USART_CLK, ENABLE, GPIO_Init(), GPIO_InitStructure, GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_AF_PP, GPIO_Mode_IN_FLOATING, GPIO_InitTypeDef::GPIO_Pin, GPIO_InitTypeDef::GPIO_Speed, GPIO_Speed_50MHz, RCC_APB1PeriphClockCmd(), RCC_APB2Periph_AFIO, RCC_APB2PeriphClockCmd(), USART_Cmd(), and USART_Init().

void STM_EVAL_LEDInit ( Led_TypeDef Led )

Configures LED GPIO.

Parameters:
Led,: Specifies the Led to be configured. This parameter can be one of following parameters:

  • LED1
  • LED2
  • LED3
  • LED4
Return values:
None

Definition at line 179 of file stm32100e_eval.c.

References ENABLE, GPIO_CLK, GPIO_Init(), GPIO_InitStructure, GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_Out_PP, GPIO_PIN, GPIO_InitTypeDef::GPIO_Pin, GPIO_InitTypeDef::GPIO_Speed, GPIO_Speed_50MHz, and RCC_APB2PeriphClockCmd().

void STM_EVAL_LEDOff ( Led_TypeDef Led )

Turns selected LED Off.

Parameters:
Led,: Specifies the Led to be set off. This parameter can be one of following parameters:

  • LED1
  • LED2
  • LED3
  • LED4
Return values:
None

Definition at line 219 of file stm32100e_eval.c.

References GPIO_TypeDef::BRR, and GPIO_PIN.

void STM_EVAL_LEDOn ( Led_TypeDef Led )

Turns selected LED On.

Parameters:
Led,: Specifies the Led to be set on. This parameter can be one of following parameters:

  • LED1
  • LED2
  • LED3
  • LED4
Return values:
None

Definition at line 204 of file stm32100e_eval.c.

References GPIO_TypeDef::BSRR, and GPIO_PIN.

void STM_EVAL_LEDToggle ( Led_TypeDef Led )

Toggles the selected LED.

Parameters:
Led,: Specifies the Led to be toggled. This parameter can be one of following parameters:

  • LED1
  • LED2
  • LED3
  • LED4
Return values:
None

Definition at line 234 of file stm32100e_eval.c.

References GPIO_PIN, and GPIO_TypeDef::ODR.

uint32_t STM_EVAL_PBGetState ( Button_TypeDef Button )

Returns the selected Button state.

Parameters:
Button,: Specifies the Button to be checked. This parameter can be one of following parameters:

  • BUTTON_WAKEUP: Wakeup Push Button
  • BUTTON_TAMPER: Tamper Push Button
  • BUTTON_KEY: Key Push Button
  • BUTTON_RIGHT: Joystick Right Push Button
  • BUTTON_LEFT: Joystick Left Push Button
  • BUTTON_UP: Joystick Up Push Button
  • BUTTON_DOWN: Joystick Down Push Button
  • BUTTON_SEL: Joystick Sel Push Button
Return values:
The Button GPIO pin value.

Definition at line 317 of file stm32100e_eval.c.

References BUTTON_PIN, and GPIO_ReadInputDataBit().

void STM_EVAL_PBInit | ( | Button_TypeDef | Button,
 |  | ButtonMode_TypeDef | Button_Mode
 | ) |  |

Configures Button GPIO and EXTI Line.

Parameters:
Button,: Specifies the Button to be configured. This parameter can be one of following parameters:

  • BUTTON_WAKEUP: Wakeup Push Button
  • BUTTON_TAMPER: Tamper Push Button
  • BUTTON_KEY: Key Push Button
  • BUTTON_RIGHT: Joystick Right Push Button
  • BUTTON_LEFT: Joystick Left Push Button
  • BUTTON_UP: Joystick Up Push Button
  • BUTTON_DOWN: Joystick Down Push Button
  • BUTTON_SEL: Joystick Sel Push Button
Button_Mode,: Specifies Button mode. This parameter can be one of following parameters:

  • BUTTON_MODE_GPIO: Button will be used as simple IO
  • BUTTON_MODE_EXTI: Button will be connected to EXTI line with interrupt generation capability
Return values:
None

Definition at line 258 of file stm32100e_eval.c.

References BUTTON_CLK, BUTTON_EXTI_LINE, BUTTON_IRQn, BUTTON_MODE_EXTI, BUTTON_PIN, BUTTON_PIN_SOURCE, BUTTON_PORT_SOURCE, BUTTON_WAKEUP, ENABLE, EXTI_Init(), EXTI_InitStructure, EXTI_InitTypeDef::EXTI_Line, EXTI_InitTypeDef::EXTI_LineCmd, EXTI_InitTypeDef::EXTI_Mode, EXTI_Mode_Interrupt, EXTI_InitTypeDef::EXTI_Trigger, EXTI_Trigger_Falling, EXTI_Trigger_Rising, GPIO_EXTILineConfig(), GPIO_Init(), GPIO_InitStructure, GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_IN_FLOATING, GPIO_InitTypeDef::GPIO_Pin, NVIC_Init(), NVIC_InitStructure, NVIC_InitTypeDef::NVIC_IRQChannel, NVIC_InitTypeDef::NVIC_IRQChannelCmd, NVIC_InitTypeDef::NVIC_IRQChannelPreemptionPriority, NVIC_InitTypeDef::NVIC_IRQChannelSubPriority, RCC_APB2Periph_AFIO, and RCC_APB2PeriphClockCmd().


STM32F10x Standard Peripherals Firmware Library: STM32100E_EVAL_LOW_LEVEL_Exported_Types

STM32100E_EVAL_LOW_LEVEL_Exported_Types

STM32100E_EVAL_LOW_LEVEL


STM32F10x Standard Peripherals Firmware Library: STM32100E_EVAL_LOW_LEVEL_LED

Defines

STM32100E_EVAL_LOW_LEVEL_LED

STM32100E_EVAL_LOW_LEVEL_Exported_Constants

Defines

#define | LED1_GPIO_CLK RCC_APB2Periph_GPIOF
#define | LED1_GPIO_PORT GPIOF
#define | LED1_PIN GPIO_Pin_6
#define | LED2_GPIO_CLK RCC_APB2Periph_GPIOF
#define | LED2_GPIO_PORT GPIOF
#define | LED2_PIN GPIO_Pin_7
#define | LED3_GPIO_CLK RCC_APB2Periph_GPIOF
#define | LED3_GPIO_PORT GPIOF
#define | LED3_PIN GPIO_Pin_8
#define | LED4_GPIO_CLK RCC_APB2Periph_GPIOF
#define | LED4_GPIO_PORT GPIOF
#define | LED4_PIN GPIO_Pin_9
#define | LEDn 4

Define Documentation

#define LED1_GPIO_CLK RCC_APB2Periph_GPIOF

Definition at line 68 of file stm32100e_eval.h.

#define LED1_GPIO_PORT GPIOF

Definition at line 67 of file stm32100e_eval.h.

#define LED1_PIN GPIO_Pin_6

Definition at line 66 of file stm32100e_eval.h.

#define LED2_GPIO_CLK RCC_APB2Periph_GPIOF

Definition at line 72 of file stm32100e_eval.h.

#define LED2_GPIO_PORT GPIOF

Definition at line 71 of file stm32100e_eval.h.

#define LED2_PIN GPIO_Pin_7

Definition at line 70 of file stm32100e_eval.h.

#define LED3_GPIO_CLK RCC_APB2Periph_GPIOF

Definition at line 76 of file stm32100e_eval.h.

#define LED3_GPIO_PORT GPIOF

Definition at line 75 of file stm32100e_eval.h.

#define LED3_PIN GPIO_Pin_8

Definition at line 74 of file stm32100e_eval.h.

#define LED4_GPIO_CLK RCC_APB2Periph_GPIOF

Definition at line 80 of file stm32100e_eval.h.

#define LED4_GPIO_PORT GPIOF

Definition at line 79 of file stm32100e_eval.h.

#define LED4_PIN GPIO_Pin_9

Definition at line 78 of file stm32100e_eval.h.

#define LEDn 4

Definition at line 64 of file stm32100e_eval.h.


STM32F10x Standard Peripherals Firmware Library: STM32100E_EVAL_LOW_LEVEL_BUTTON

Defines

STM32100E_EVAL_LOW_LEVEL_BUTTON

STM32100E_EVAL_LOW_LEVEL_Exported_Constants

Defines

#define | BUTTONn 8
#define | DOWN_BUTTON_EXTI_IRQn EXTI15_10_IRQn
#define | DOWN_BUTTON_EXTI_LINE EXTI_Line11
#define | DOWN_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource11
#define | DOWN_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOG
#define | DOWN_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOG
#define | DOWN_BUTTON_GPIO_PORT GPIOG
#define | DOWN_BUTTON_PIN GPIO_Pin_11
Joystick Down push-button.
#define | KEY_BUTTON_EXTI_IRQn EXTI9_5_IRQn
#define | KEY_BUTTON_EXTI_LINE EXTI_Line8
#define | KEY_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource8
#define | KEY_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOG
#define | KEY_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOG
#define | KEY_BUTTON_GPIO_PORT GPIOG
#define | KEY_BUTTON_PIN GPIO_Pin_8
Key push-button.
#define | LEFT_BUTTON_EXTI_IRQn EXTI15_10_IRQn
#define | LEFT_BUTTON_EXTI_LINE EXTI_Line14
#define | LEFT_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource14
#define | LEFT_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOG
#define | LEFT_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOG
#define | LEFT_BUTTON_GPIO_PORT GPIOG
#define | LEFT_BUTTON_PIN GPIO_Pin_14
Joystick Left push-button.
#define | RIGHT_BUTTON_EXTI_IRQn EXTI15_10_IRQn
#define | RIGHT_BUTTON_EXTI_LINE EXTI_Line13
#define | RIGHT_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource13
#define | RIGHT_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOG
#define | RIGHT_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOG
#define | RIGHT_BUTTON_GPIO_PORT GPIOG
#define | RIGHT_BUTTON_PIN GPIO_Pin_13
Joystick Right push-button.
#define | SEL_BUTTON_EXTI_IRQn EXTI9_5_IRQn
#define | SEL_BUTTON_EXTI_LINE EXTI_Line7
#define | SEL_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource7
#define | SEL_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOG
#define | SEL_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOG
#define | SEL_BUTTON_GPIO_PORT GPIOG
#define | SEL_BUTTON_PIN GPIO_Pin_7
Joystick Sel push-button.
#define | TAMPER_BUTTON_EXTI_IRQn EXTI15_10_IRQn
#define | TAMPER_BUTTON_EXTI_LINE EXTI_Line13
#define | TAMPER_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource13
#define | TAMPER_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOC
#define | TAMPER_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOC
#define | TAMPER_BUTTON_GPIO_PORT GPIOC
#define | TAMPER_BUTTON_PIN GPIO_Pin_13
Tamper push-button.
#define | UP_BUTTON_EXTI_IRQn EXTI15_10_IRQn
#define | UP_BUTTON_EXTI_LINE EXTI_Line15
#define | UP_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource15
#define | UP_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOG
#define | UP_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOG
#define | UP_BUTTON_GPIO_PORT GPIOG
#define | UP_BUTTON_PIN GPIO_Pin_15
Joystick Up push-button.
#define | WAKEUP_BUTTON_EXTI_IRQn EXTI0_IRQn
#define | WAKEUP_BUTTON_EXTI_LINE EXTI_Line0
#define | WAKEUP_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource0
#define | WAKEUP_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOA
#define | WAKEUP_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOA
#define | WAKEUP_BUTTON_GPIO_PORT GPIOA
#define | WAKEUP_BUTTON_PIN GPIO_Pin_0
Wakeup push-button.

Define Documentation

#define BUTTONn 8

Definition at line 89 of file stm32100e_eval.h.

#define DOWN_BUTTON_EXTI_IRQn EXTI15_10_IRQn

Definition at line 160 of file stm32100e_eval.h.

#define DOWN_BUTTON_EXTI_LINE EXTI_Line11

Definition at line 157 of file stm32100e_eval.h.

#define DOWN_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource11

Definition at line 159 of file stm32100e_eval.h.

#define DOWN_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOG

Definition at line 158 of file stm32100e_eval.h.

#define DOWN_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOG

Definition at line 156 of file stm32100e_eval.h.

#define DOWN_BUTTON_GPIO_PORT GPIOG

Definition at line 155 of file stm32100e_eval.h.

#define DOWN_BUTTON_PIN GPIO_Pin_11

Joystick Down push-button.

Definition at line 154 of file stm32100e_eval.h.

#define KEY_BUTTON_EXTI_IRQn EXTI9_5_IRQn

Definition at line 120 of file stm32100e_eval.h.

#define KEY_BUTTON_EXTI_LINE EXTI_Line8

Definition at line 117 of file stm32100e_eval.h.

#define KEY_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource8

Definition at line 119 of file stm32100e_eval.h.

#define KEY_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOG

Definition at line 118 of file stm32100e_eval.h.

#define KEY_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOG

Definition at line 116 of file stm32100e_eval.h.

#define KEY_BUTTON_GPIO_PORT GPIOG

Definition at line 115 of file stm32100e_eval.h.

#define KEY_BUTTON_PIN GPIO_Pin_8

Key push-button.

Definition at line 114 of file stm32100e_eval.h.

#define LEFT_BUTTON_EXTI_IRQn EXTI15_10_IRQn

Definition at line 140 of file stm32100e_eval.h.

#define LEFT_BUTTON_EXTI_LINE EXTI_Line14

Definition at line 137 of file stm32100e_eval.h.

#define LEFT_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource14

Definition at line 139 of file stm32100e_eval.h.

#define LEFT_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOG

Definition at line 138 of file stm32100e_eval.h.

#define LEFT_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOG

Definition at line 136 of file stm32100e_eval.h.

#define LEFT_BUTTON_GPIO_PORT GPIOG

Definition at line 135 of file stm32100e_eval.h.

#define LEFT_BUTTON_PIN GPIO_Pin_14

Joystick Left push-button.

Definition at line 134 of file stm32100e_eval.h.

#define RIGHT_BUTTON_EXTI_IRQn EXTI15_10_IRQn

Definition at line 130 of file stm32100e_eval.h.

#define RIGHT_BUTTON_EXTI_LINE EXTI_Line13

Definition at line 127 of file stm32100e_eval.h.

#define RIGHT_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource13

Definition at line 129 of file stm32100e_eval.h.

#define RIGHT_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOG

Definition at line 128 of file stm32100e_eval.h.

#define RIGHT_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOG

Definition at line 126 of file stm32100e_eval.h.

#define RIGHT_BUTTON_GPIO_PORT GPIOG

Definition at line 125 of file stm32100e_eval.h.

#define RIGHT_BUTTON_PIN GPIO_Pin_13

Joystick Right push-button.

Definition at line 124 of file stm32100e_eval.h.

#define SEL_BUTTON_EXTI_IRQn EXTI9_5_IRQn

Definition at line 170 of file stm32100e_eval.h.

#define SEL_BUTTON_EXTI_LINE EXTI_Line7

Definition at line 167 of file stm32100e_eval.h.

#define SEL_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource7

Definition at line 169 of file stm32100e_eval.h.

#define SEL_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOG

Definition at line 168 of file stm32100e_eval.h.

#define SEL_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOG

Definition at line 166 of file stm32100e_eval.h.

#define SEL_BUTTON_GPIO_PORT GPIOG

Definition at line 165 of file stm32100e_eval.h.

#define SEL_BUTTON_PIN GPIO_Pin_7

Joystick Sel push-button.

Definition at line 164 of file stm32100e_eval.h.

#define TAMPER_BUTTON_EXTI_IRQn EXTI15_10_IRQn

Definition at line 110 of file stm32100e_eval.h.

#define TAMPER_BUTTON_EXTI_LINE EXTI_Line13

Definition at line 107 of file stm32100e_eval.h.

#define TAMPER_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource13

Definition at line 109 of file stm32100e_eval.h.

#define TAMPER_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOC

Definition at line 108 of file stm32100e_eval.h.

#define TAMPER_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOC

Definition at line 106 of file stm32100e_eval.h.

#define TAMPER_BUTTON_GPIO_PORT GPIOC

Definition at line 105 of file stm32100e_eval.h.

#define TAMPER_BUTTON_PIN GPIO_Pin_13

Tamper push-button.

Definition at line 104 of file stm32100e_eval.h.

#define UP_BUTTON_EXTI_IRQn EXTI15_10_IRQn

Definition at line 150 of file stm32100e_eval.h.

#define UP_BUTTON_EXTI_LINE EXTI_Line15

Definition at line 147 of file stm32100e_eval.h.

#define UP_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource15

Definition at line 149 of file stm32100e_eval.h.

#define UP_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOG

Definition at line 148 of file stm32100e_eval.h.

#define UP_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOG

Definition at line 146 of file stm32100e_eval.h.

#define UP_BUTTON_GPIO_PORT GPIOG

Definition at line 145 of file stm32100e_eval.h.

#define UP_BUTTON_PIN GPIO_Pin_15

Joystick Up push-button.

Definition at line 144 of file stm32100e_eval.h.

#define WAKEUP_BUTTON_EXTI_IRQn EXTI0_IRQn

Definition at line 100 of file stm32100e_eval.h.

#define WAKEUP_BUTTON_EXTI_LINE EXTI_Line0

Definition at line 97 of file stm32100e_eval.h.

#define WAKEUP_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource0

Definition at line 99 of file stm32100e_eval.h.

#define WAKEUP_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOA

Definition at line 98 of file stm32100e_eval.h.

#define WAKEUP_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOA

Definition at line 96 of file stm32100e_eval.h.

#define WAKEUP_BUTTON_GPIO_PORT GPIOA

Definition at line 95 of file stm32100e_eval.h.

#define WAKEUP_BUTTON_PIN GPIO_Pin_0

Wakeup push-button.

Definition at line 94 of file stm32100e_eval.h.


STM32F10x Standard Peripherals Firmware Library: STM32100E_EVAL_LOW_LEVEL_COM

Defines

STM32100E_EVAL_LOW_LEVEL_COM

STM32100E_EVAL_LOW_LEVEL_Exported_Constants

Defines

#define | COMn 2
#define | EVAL_COM1 USART1
Definition for COM port1, connected to USART1.
#define | EVAL_COM1_CLK RCC_APB2Periph_USART1
#define | EVAL_COM1_IRQn USART1_IRQn
#define | EVAL_COM1_RX_GPIO_CLK RCC_APB2Periph_GPIOA
#define | EVAL_COM1_RX_GPIO_PORT GPIOA
#define | EVAL_COM1_RX_PIN GPIO_Pin_10
#define | EVAL_COM1_TX_GPIO_CLK RCC_APB2Periph_GPIOA
#define | EVAL_COM1_TX_GPIO_PORT GPIOA
#define | EVAL_COM1_TX_PIN GPIO_Pin_9
#define | EVAL_COM2 USART2
Definition for COM port2, connected to USART2.
#define | EVAL_COM2_CLK RCC_APB1Periph_USART2
#define | EVAL_COM2_IRQn USART2_IRQn
#define | EVAL_COM2_RX_GPIO_CLK RCC_APB2Periph_GPIOA
#define | EVAL_COM2_RX_GPIO_PORT GPIOA
#define | EVAL_COM2_RX_PIN GPIO_Pin_3
#define | EVAL_COM2_TX_GPIO_CLK RCC_APB2Periph_GPIOA
#define | EVAL_COM2_TX_GPIO_PORT GPIOA
#define | EVAL_COM2_TX_PIN GPIO_Pin_2

Define Documentation

#define COMn 2

Definition at line 178 of file stm32100e_eval.h.

#define EVAL_COM1 USART1

Definition for COM port1, connected to USART1.

Definition at line 183 of file stm32100e_eval.h.

#define EVAL_COM1_CLK RCC_APB2Periph_USART1

Definition at line 184 of file stm32100e_eval.h.

#define EVAL_COM1_IRQn USART1_IRQn

Definition at line 191 of file stm32100e_eval.h.

#define EVAL_COM1_RX_GPIO_CLK RCC_APB2Periph_GPIOA

Definition at line 190 of file stm32100e_eval.h.

#define EVAL_COM1_RX_GPIO_PORT GPIOA

Definition at line 189 of file stm32100e_eval.h.

#define EVAL_COM1_RX_PIN GPIO_Pin_10

Definition at line 188 of file stm32100e_eval.h.

#define EVAL_COM1_TX_GPIO_CLK RCC_APB2Periph_GPIOA

Definition at line 187 of file stm32100e_eval.h.

#define EVAL_COM1_TX_GPIO_PORT GPIOA

Definition at line 186 of file stm32100e_eval.h.

#define EVAL_COM1_TX_PIN GPIO_Pin_9

Definition at line 185 of file stm32100e_eval.h.

#define EVAL_COM2 USART2

Definition for COM port2, connected to USART2.

Definition at line 196 of file stm32100e_eval.h.

#define EVAL_COM2_CLK RCC_APB1Periph_USART2

Definition at line 197 of file stm32100e_eval.h.

#define EVAL_COM2_IRQn USART2_IRQn

Definition at line 204 of file stm32100e_eval.h.

#define EVAL_COM2_RX_GPIO_CLK RCC_APB2Periph_GPIOA

Definition at line 203 of file stm32100e_eval.h.

#define EVAL_COM2_RX_GPIO_PORT GPIOA

Definition at line 202 of file stm32100e_eval.h.

#define EVAL_COM2_RX_PIN GPIO_Pin_3

Definition at line 201 of file stm32100e_eval.h.

#define EVAL_COM2_TX_GPIO_CLK RCC_APB2Periph_GPIOA

Definition at line 200 of file stm32100e_eval.h.

#define EVAL_COM2_TX_GPIO_PORT GPIOA

Definition at line 199 of file stm32100e_eval.h.

#define EVAL_COM2_TX_PIN GPIO_Pin_2

Definition at line 198 of file stm32100e_eval.h.


STM32F10x Standard Peripherals Firmware Library: STM32100E_EVAL_LOW_LEVEL_SD_FLASH

Defines

STM32100E_EVAL_LOW_LEVEL_SD_FLASH

STM32100E_EVAL_LOW_LEVEL_Exported_Constants

Defines

#define | SD_CS_GPIO_CLK RCC_APB2Periph_GPIOG
#define | SD_CS_GPIO_PORT GPIOG
#define | SD_CS_PIN GPIO_Pin_6
#define | SD_DETECT_GPIO_CLK RCC_APB2Periph_GPIOF
#define | SD_DETECT_GPIO_PORT GPIOF
#define | SD_DETECT_PIN GPIO_Pin_11
#define | SD_SPI SPI2
SD SPI Interface pins.
#define | SD_SPI_CLK RCC_APB1Periph_SPI2
#define | SD_SPI_MISO_GPIO_CLK RCC_APB2Periph_GPIOB
#define | SD_SPI_MISO_GPIO_PORT GPIOB
#define | SD_SPI_MISO_PIN GPIO_Pin_14
#define | SD_SPI_MOSI_GPIO_CLK RCC_APB2Periph_GPIOB
#define | SD_SPI_MOSI_GPIO_PORT GPIOB
#define | SD_SPI_MOSI_PIN GPIO_Pin_15
#define | SD_SPI_SCK_GPIO_CLK RCC_APB2Periph_GPIOB
#define | SD_SPI_SCK_GPIO_PORT GPIOB
#define | SD_SPI_SCK_PIN GPIO_Pin_13

Define Documentation

#define SD_CS_GPIO_CLK RCC_APB2Periph_GPIOG

Definition at line 229 of file stm32100e_eval.h.

#define SD_CS_GPIO_PORT GPIOG

Definition at line 228 of file stm32100e_eval.h.

#define SD_CS_PIN GPIO_Pin_6

Definition at line 227 of file stm32100e_eval.h.

#define SD_DETECT_GPIO_CLK RCC_APB2Periph_GPIOF

Definition at line 232 of file stm32100e_eval.h.

#define SD_DETECT_GPIO_PORT GPIOF

Definition at line 231 of file stm32100e_eval.h.

#define SD_DETECT_PIN GPIO_Pin_11

Definition at line 230 of file stm32100e_eval.h.

#define SD_SPI SPI2

SD SPI Interface pins.

Definition at line 216 of file stm32100e_eval.h.

#define SD_SPI_CLK RCC_APB1Periph_SPI2

Definition at line 217 of file stm32100e_eval.h.

#define SD_SPI_MISO_GPIO_CLK RCC_APB2Periph_GPIOB

Definition at line 223 of file stm32100e_eval.h.

#define SD_SPI_MISO_GPIO_PORT GPIOB

Definition at line 222 of file stm32100e_eval.h.

#define SD_SPI_MISO_PIN GPIO_Pin_14

Definition at line 221 of file stm32100e_eval.h.

#define SD_SPI_MOSI_GPIO_CLK RCC_APB2Periph_GPIOB

Definition at line 226 of file stm32100e_eval.h.

#define SD_SPI_MOSI_GPIO_PORT GPIOB

Definition at line 225 of file stm32100e_eval.h.

#define SD_SPI_MOSI_PIN GPIO_Pin_15

Definition at line 224 of file stm32100e_eval.h.

#define SD_SPI_SCK_GPIO_CLK RCC_APB2Periph_GPIOB

Definition at line 220 of file stm32100e_eval.h.

#define SD_SPI_SCK_GPIO_PORT GPIOB

Definition at line 219 of file stm32100e_eval.h.

#define SD_SPI_SCK_PIN GPIO_Pin_13

Definition at line 218 of file stm32100e_eval.h.


STM32F10x Standard Peripherals Firmware Library: STM3210C_EVAL_LOW_LEVEL_I2C_EE

Defines

STM3210C_EVAL_LOW_LEVEL_I2C_EE

STM32100E_EVAL_LOW_LEVEL_Exported_Constants | STM3210C_EVAL_LOW_LEVEL_Exported_Constants

Defines

#define | sEE_DIRECTION_RX 1
#define | sEE_DIRECTION_RX 1
#define | sEE_DIRECTION_TX 0
#define | sEE_DIRECTION_TX 0
#define | sEE_I2C I2C2
I2C EEPROM Interface pins.
#define | sEE_I2C I2C1
I2C EEPROM Interface pins.
#define | sEE_I2C_CLK RCC_APB1Periph_I2C2
#define | sEE_I2C_CLK RCC_APB1Periph_I2C1
#define | sEE_I2C_DMA DMA1
#define | sEE_I2C_DMA DMA1
#define | sEE_I2C_DMA_CHANNEL_RX DMA1_Channel7
#define | sEE_I2C_DMA_CHANNEL_RX DMA1_Channel5
#define | sEE_I2C_DMA_CHANNEL_TX DMA1_Channel6
#define | sEE_I2C_DMA_CHANNEL_TX DMA1_Channel4
#define | sEE_I2C_DMA_CLK RCC_AHBPeriph_DMA1
#define | sEE_I2C_DMA_CLK RCC_AHBPeriph_DMA1
#define | sEE_I2C_DMA_FLAG_RX_GL DMA1_IT_GL5
#define | sEE_I2C_DMA_FLAG_RX_GL DMA1_IT_GL7
#define | sEE_I2C_DMA_FLAG_RX_TC DMA1_IT_TC7
#define | sEE_I2C_DMA_FLAG_RX_TC DMA1_IT_TC5
#define | sEE_I2C_DMA_FLAG_TX_GL DMA1_IT_GL6
#define | sEE_I2C_DMA_FLAG_TX_GL DMA1_IT_GL4
#define | sEE_I2C_DMA_FLAG_TX_TC DMA1_IT_TC6
#define | sEE_I2C_DMA_FLAG_TX_TC DMA1_IT_TC4
#define | sEE_I2C_DMA_PREPRIO 0
#define | sEE_I2C_DMA_PREPRIO 0
#define | sEE_I2C_DMA_RX_IRQHandler DMA1_Channel5_IRQHandler
#define | sEE_I2C_DMA_RX_IRQHandler DMA1_Channel7_IRQHandler
#define | sEE_I2C_DMA_RX_IRQn DMA1_Channel5_IRQn
#define | sEE_I2C_DMA_RX_IRQn DMA1_Channel7_IRQn
#define | sEE_I2C_DMA_SUBPRIO 0
#define | sEE_I2C_DMA_SUBPRIO 0
#define | sEE_I2C_DMA_TX_IRQHandler DMA1_Channel4_IRQHandler
#define | sEE_I2C_DMA_TX_IRQHandler DMA1_Channel6_IRQHandler
#define | sEE_I2C_DMA_TX_IRQn DMA1_Channel4_IRQn
#define | sEE_I2C_DMA_TX_IRQn DMA1_Channel6_IRQn
#define | sEE_I2C_DR_Address ((uint32_t)0x40005810)
#define | sEE_I2C_DR_Address ((uint32_t)0x40005410)
#define | sEE_I2C_SCL_GPIO_CLK RCC_APB2Periph_GPIOB
#define | sEE_I2C_SCL_GPIO_CLK RCC_APB2Periph_GPIOB
#define | sEE_I2C_SCL_GPIO_PORT GPIOB
#define | sEE_I2C_SCL_GPIO_PORT GPIOB
#define | sEE_I2C_SCL_PIN GPIO_Pin_6
#define | sEE_I2C_SCL_PIN GPIO_Pin_10
#define | sEE_I2C_SDA_GPIO_CLK RCC_APB2Periph_GPIOB
#define | sEE_I2C_SDA_GPIO_CLK RCC_APB2Periph_GPIOB
#define | sEE_I2C_SDA_GPIO_PORT GPIOB
#define | sEE_I2C_SDA_GPIO_PORT GPIOB
#define | sEE_I2C_SDA_PIN GPIO_Pin_7
#define | sEE_I2C_SDA_PIN GPIO_Pin_11
#define | sEE_M24C64_32
#define | sEE_M24C64_32
#define | sEE_TIME_CONST 24
#define | sEE_TIME_CONST 72
#define | sEE_USE_DMA
#define | sEE_USE_DMA

Define Documentation

#define sEE_DIRECTION_RX 1

Definition at line 273 of file stm32100e_eval.h.

Referenced by sEE_ReadBuffer().

#define sEE_DIRECTION_RX 1

Definition at line 214 of file stm3210c_eval.h.

#define sEE_DIRECTION_TX 0

Definition at line 272 of file stm32100e_eval.h.

Referenced by sEE_LowLevel_DMAConfig(), and sEE_WritePage().

#define sEE_DIRECTION_TX 0

Definition at line 213 of file stm3210c_eval.h.

#define sEE_I2C I2C2

I2C EEPROM Interface pins.

Definition at line 244 of file stm32100e_eval.h.

Referenced by sEE_I2C_DMA_RX_IRQHandler(), sEE_I2C_DMA_TX_IRQHandler(), sEE_Init(), sEE_LowLevel_DeInit(), sEE_ReadBuffer(), sEE_WaitEepromStandbyState(), and sEE_WritePage().

#define sEE_I2C I2C1

I2C EEPROM Interface pins.

Definition at line 185 of file stm3210c_eval.h.

#define sEE_I2C_CLK RCC_APB1Periph_I2C2

Definition at line 245 of file stm32100e_eval.h.

Referenced by sEE_LowLevel_DeInit(), and sEE_LowLevel_Init().

#define sEE_I2C_CLK RCC_APB1Periph_I2C1

Definition at line 186 of file stm3210c_eval.h.

#define sEE_I2C_DMA DMA1

Definition at line 195 of file stm3210c_eval.h.

#define sEE_I2C_DMA DMA1

Definition at line 254 of file stm32100e_eval.h.

#define sEE_I2C_DMA_CHANNEL_RX DMA1_Channel7

Definition at line 197 of file stm3210c_eval.h.

#define sEE_I2C_DMA_CHANNEL_RX DMA1_Channel5

Definition at line 256 of file stm32100e_eval.h.

Referenced by sEE_I2C_DMA_RX_IRQHandler(), sEE_LowLevel_DeInit(), sEE_LowLevel_DMAConfig(), sEE_LowLevel_Init(), and sEE_ReadBuffer().

#define sEE_I2C_DMA_CHANNEL_TX DMA1_Channel6

Definition at line 196 of file stm3210c_eval.h.

#define sEE_I2C_DMA_CHANNEL_TX DMA1_Channel4

Definition at line 255 of file stm32100e_eval.h.

Referenced by sEE_I2C_DMA_TX_IRQHandler(), sEE_LowLevel_DeInit(), sEE_LowLevel_DMAConfig(), sEE_LowLevel_Init(), and sEE_WritePage().

#define sEE_I2C_DMA_CLK RCC_AHBPeriph_DMA1

Definition at line 261 of file stm32100e_eval.h.

Referenced by sEE_LowLevel_Init().

#define sEE_I2C_DMA_CLK RCC_AHBPeriph_DMA1

Definition at line 202 of file stm3210c_eval.h.

#define sEE_I2C_DMA_FLAG_RX_GL DMA1_IT_GL5

Definition at line 260 of file stm32100e_eval.h.

Referenced by sEE_I2C_DMA_RX_IRQHandler().

#define sEE_I2C_DMA_FLAG_RX_GL DMA1_IT_GL7

Definition at line 201 of file stm3210c_eval.h.

#define sEE_I2C_DMA_FLAG_RX_TC DMA1_IT_TC7

Definition at line 200 of file stm3210c_eval.h.

#define sEE_I2C_DMA_FLAG_RX_TC DMA1_IT_TC5

Definition at line 259 of file stm32100e_eval.h.

Referenced by sEE_I2C_DMA_RX_IRQHandler().

#define sEE_I2C_DMA_FLAG_TX_GL DMA1_IT_GL6

Definition at line 199 of file stm3210c_eval.h.

#define sEE_I2C_DMA_FLAG_TX_GL DMA1_IT_GL4

Definition at line 258 of file stm32100e_eval.h.

Referenced by sEE_I2C_DMA_TX_IRQHandler().

#define sEE_I2C_DMA_FLAG_TX_TC DMA1_IT_TC6

Definition at line 198 of file stm3210c_eval.h.

#define sEE_I2C_DMA_FLAG_TX_TC DMA1_IT_TC4

Definition at line 257 of file stm32100e_eval.h.

Referenced by sEE_I2C_DMA_TX_IRQHandler().

#define sEE_I2C_DMA_PREPRIO 0

Definition at line 269 of file stm32100e_eval.h.

Referenced by sEE_LowLevel_DeInit(), and sEE_LowLevel_Init().

#define sEE_I2C_DMA_PREPRIO 0

Definition at line 210 of file stm3210c_eval.h.

#define sEE_I2C_DMA_RX_IRQHandler DMA1_Channel5_IRQHandler

Definition at line 268 of file stm32100e_eval.h.

#define sEE_I2C_DMA_RX_IRQHandler DMA1_Channel7_IRQHandler

Definition at line 209 of file stm3210c_eval.h.

#define sEE_I2C_DMA_RX_IRQn DMA1_Channel5_IRQn

Definition at line 266 of file stm32100e_eval.h.

Referenced by sEE_LowLevel_DeInit(), and sEE_LowLevel_Init().

#define sEE_I2C_DMA_RX_IRQn DMA1_Channel7_IRQn

Definition at line 207 of file stm3210c_eval.h.

#define sEE_I2C_DMA_SUBPRIO 0

Definition at line 270 of file stm32100e_eval.h.

Referenced by sEE_LowLevel_DeInit(), and sEE_LowLevel_Init().

#define sEE_I2C_DMA_SUBPRIO 0

Definition at line 211 of file stm3210c_eval.h.

#define sEE_I2C_DMA_TX_IRQHandler DMA1_Channel4_IRQHandler

Definition at line 267 of file stm32100e_eval.h.

#define sEE_I2C_DMA_TX_IRQHandler DMA1_Channel6_IRQHandler

Definition at line 208 of file stm3210c_eval.h.

#define sEE_I2C_DMA_TX_IRQn DMA1_Channel4_IRQn

Definition at line 265 of file stm32100e_eval.h.

Referenced by sEE_LowLevel_DeInit(), and sEE_LowLevel_Init().

#define sEE_I2C_DMA_TX_IRQn DMA1_Channel6_IRQn

Definition at line 206 of file stm3210c_eval.h.

#define sEE_I2C_DR_Address ((uint32_t)0x40005810)

Definition at line 262 of file stm32100e_eval.h.

Referenced by sEE_LowLevel_Init().

#define sEE_I2C_DR_Address ((uint32_t)0x40005410)

Definition at line 203 of file stm3210c_eval.h.

#define sEE_I2C_SCL_GPIO_CLK RCC_APB2Periph_GPIOB

Definition at line 189 of file stm3210c_eval.h.

#define sEE_I2C_SCL_GPIO_CLK RCC_APB2Periph_GPIOB

Definition at line 248 of file stm32100e_eval.h.

Referenced by sEE_LowLevel_Init().

#define sEE_I2C_SCL_GPIO_PORT GPIOB

Definition at line 188 of file stm3210c_eval.h.

#define sEE_I2C_SCL_GPIO_PORT GPIOB

Definition at line 247 of file stm32100e_eval.h.

Referenced by sEE_LowLevel_DeInit(), and sEE_LowLevel_Init().

#define sEE_I2C_SCL_PIN GPIO_Pin_6

Definition at line 187 of file stm3210c_eval.h.

#define sEE_I2C_SCL_PIN GPIO_Pin_10

Definition at line 246 of file stm32100e_eval.h.

Referenced by sEE_LowLevel_DeInit(), and sEE_LowLevel_Init().

#define sEE_I2C_SDA_GPIO_CLK RCC_APB2Periph_GPIOB

Definition at line 192 of file stm3210c_eval.h.

#define sEE_I2C_SDA_GPIO_CLK RCC_APB2Periph_GPIOB

Definition at line 251 of file stm32100e_eval.h.

Referenced by sEE_LowLevel_Init().

#define sEE_I2C_SDA_GPIO_PORT GPIOB

Definition at line 191 of file stm3210c_eval.h.

#define sEE_I2C_SDA_GPIO_PORT GPIOB

Definition at line 250 of file stm32100e_eval.h.

Referenced by sEE_LowLevel_DeInit(), and sEE_LowLevel_Init().

#define sEE_I2C_SDA_PIN GPIO_Pin_7

Definition at line 190 of file stm3210c_eval.h.

#define sEE_I2C_SDA_PIN GPIO_Pin_11

Definition at line 249 of file stm32100e_eval.h.

Referenced by sEE_LowLevel_DeInit(), and sEE_LowLevel_Init().

#define sEE_M24C64_32

Definition at line 252 of file stm32100e_eval.h.

#define sEE_M24C64_32

Definition at line 193 of file stm3210c_eval.h.

#define sEE_TIME_CONST 24

Definition at line 278 of file stm32100e_eval.h.

#define sEE_TIME_CONST 72

Definition at line 219 of file stm3210c_eval.h.

#define sEE_USE_DMA

Definition at line 263 of file stm32100e_eval.h.

#define sEE_USE_DMA

Definition at line 204 of file stm3210c_eval.h.


STM32F10x Standard Peripherals Firmware Library: STM32100E_EVAL_LOW_LEVEL_M25P_FLASH_SPI

Defines

STM32100E_EVAL_LOW_LEVEL_M25P_FLASH_SPI

STM32100E_EVAL_LOW_LEVEL_Exported_Constants

Defines

#define | sFLASH_CS_GPIO_CLK RCC_APB2Periph_GPIOE
#define | sFLASH_CS_GPIO_PORT GPIOE
#define | sFLASH_CS_PIN GPIO_Pin_6
#define | sFLASH_SPI SPI1
M25P FLASH SPI Interface pins.
#define | sFLASH_SPI_CLK RCC_APB2Periph_SPI1
#define | sFLASH_SPI_MISO_GPIO_CLK RCC_APB2Periph_GPIOA
#define | sFLASH_SPI_MISO_GPIO_PORT GPIOA
#define | sFLASH_SPI_MISO_PIN GPIO_Pin_6
#define | sFLASH_SPI_MOSI_GPIO_CLK RCC_APB2Periph_GPIOA
#define | sFLASH_SPI_MOSI_GPIO_PORT GPIOA
#define | sFLASH_SPI_MOSI_PIN GPIO_Pin_7
#define | sFLASH_SPI_SCK_GPIO_CLK RCC_APB2Periph_GPIOA
#define | sFLASH_SPI_SCK_GPIO_PORT GPIOA
#define | sFLASH_SPI_SCK_PIN GPIO_Pin_5

Define Documentation

#define sFLASH_CS_GPIO_CLK RCC_APB2Periph_GPIOE

Definition at line 303 of file stm32100e_eval.h.

#define sFLASH_CS_GPIO_PORT GPIOE

Definition at line 302 of file stm32100e_eval.h.

#define sFLASH_CS_PIN GPIO_Pin_6

Definition at line 301 of file stm32100e_eval.h.

#define sFLASH_SPI SPI1

M25P FLASH SPI Interface pins.

Definition at line 290 of file stm32100e_eval.h.

#define sFLASH_SPI_CLK RCC_APB2Periph_SPI1

Definition at line 291 of file stm32100e_eval.h.

#define sFLASH_SPI_MISO_GPIO_CLK RCC_APB2Periph_GPIOA

Definition at line 297 of file stm32100e_eval.h.

#define sFLASH_SPI_MISO_GPIO_PORT GPIOA

Definition at line 296 of file stm32100e_eval.h.

#define sFLASH_SPI_MISO_PIN GPIO_Pin_6

Definition at line 295 of file stm32100e_eval.h.

#define sFLASH_SPI_MOSI_GPIO_CLK RCC_APB2Periph_GPIOA

Definition at line 300 of file stm32100e_eval.h.

#define sFLASH_SPI_MOSI_GPIO_PORT GPIOA

Definition at line 299 of file stm32100e_eval.h.

#define sFLASH_SPI_MOSI_PIN GPIO_Pin_7

Definition at line 298 of file stm32100e_eval.h.

#define sFLASH_SPI_SCK_GPIO_CLK RCC_APB2Periph_GPIOA

Definition at line 294 of file stm32100e_eval.h.

#define sFLASH_SPI_SCK_GPIO_PORT GPIOA

Definition at line 293 of file stm32100e_eval.h.

#define sFLASH_SPI_SCK_PIN GPIO_Pin_5

Definition at line 292 of file stm32100e_eval.h.


STM32F10x Standard Peripherals Firmware Library: STM32100E_EVAL_LOW_LEVEL_TSENSOR_I2C

Defines

STM32100E_EVAL_LOW_LEVEL_TSENSOR_I2C

STM32100E_EVAL_LOW_LEVEL_Exported_Constants

Defines

#define | LM75_DMA_CLK RCC_AHBPeriph_DMA1
#define | LM75_DMA_RX_CHANNEL DMA1_Channel5
#define | LM75_DMA_RX_TCFLAG DMA1_FLAG_TC5
#define | LM75_DMA_TX_CHANNEL DMA1_Channel4
#define | LM75_DMA_TX_TCFLAG DMA1_FLAG_TC4
#define | LM75_I2C I2C2
LM75 Temperature Sensor I2C Interface pins.
#define | LM75_I2C_CLK RCC_APB1Periph_I2C2
#define | LM75_I2C_DR ((uint32_t)0x40005810)
#define | LM75_I2C_SCL_GPIO_CLK RCC_APB2Periph_GPIOB
#define | LM75_I2C_SCL_GPIO_PORT GPIOB
#define | LM75_I2C_SCL_PIN GPIO_Pin_10
#define | LM75_I2C_SDA_GPIO_CLK RCC_APB2Periph_GPIOB
#define | LM75_I2C_SDA_GPIO_PORT GPIOB
#define | LM75_I2C_SDA_PIN GPIO_Pin_11
#define | LM75_I2C_SMBUSALERT_GPIO_CLK RCC_APB2Periph_GPIOB
#define | LM75_I2C_SMBUSALERT_GPIO_PORT GPIOB
#define | LM75_I2C_SMBUSALERT_PIN GPIO_Pin_12

Define Documentation

#define LM75_DMA_CLK RCC_AHBPeriph_DMA1

Definition at line 329 of file stm32100e_eval.h.

#define LM75_DMA_RX_CHANNEL DMA1_Channel5

Definition at line 331 of file stm32100e_eval.h.

#define LM75_DMA_RX_TCFLAG DMA1_FLAG_TC5

Definition at line 333 of file stm32100e_eval.h.

#define LM75_DMA_TX_CHANNEL DMA1_Channel4

Definition at line 330 of file stm32100e_eval.h.

#define LM75_DMA_TX_TCFLAG DMA1_FLAG_TC4

Definition at line 332 of file stm32100e_eval.h.

#define LM75_I2C I2C2

LM75 Temperature Sensor I2C Interface pins.

Definition at line 316 of file stm32100e_eval.h.

#define LM75_I2C_CLK RCC_APB1Periph_I2C2

Definition at line 317 of file stm32100e_eval.h.

#define LM75_I2C_DR ((uint32_t)0x40005810)

Definition at line 327 of file stm32100e_eval.h.

#define LM75_I2C_SCL_GPIO_CLK RCC_APB2Periph_GPIOB

Definition at line 320 of file stm32100e_eval.h.

#define LM75_I2C_SCL_GPIO_PORT GPIOB

Definition at line 319 of file stm32100e_eval.h.

#define LM75_I2C_SCL_PIN GPIO_Pin_10

Definition at line 318 of file stm32100e_eval.h.

#define LM75_I2C_SDA_GPIO_CLK RCC_APB2Periph_GPIOB

Definition at line 323 of file stm32100e_eval.h.

#define LM75_I2C_SDA_GPIO_PORT GPIOB

Definition at line 322 of file stm32100e_eval.h.

#define LM75_I2C_SDA_PIN GPIO_Pin_11

Definition at line 321 of file stm32100e_eval.h.

#define LM75_I2C_SMBUSALERT_GPIO_CLK RCC_APB2Periph_GPIOB

Definition at line 326 of file stm32100e_eval.h.

#define LM75_I2C_SMBUSALERT_GPIO_PORT GPIOB

Definition at line 325 of file stm32100e_eval.h.

#define LM75_I2C_SMBUSALERT_PIN GPIO_Pin_12

Definition at line 324 of file stm32100e_eval.h.


STM32F10x Standard Peripherals Firmware Library: STM32100E_EVAL_LOW_LEVEL_Exported_Macros

STM32100E_EVAL_LOW_LEVEL_Exported_Macros

STM32100E_EVAL_LOW_LEVEL


STM32F10x Standard Peripherals Firmware Library: STM32100E_EVAL_LOW_LEVEL_Exported_Functions

Functions

STM32100E_EVAL_LOW_LEVEL_Exported_Functions

STM32100E_EVAL_LOW_LEVEL

Functions

void | LM75_LowLevel_DeInit (void)
DeInitializes the LM75_I2C.
void | LM75_LowLevel_Init (void)
Initializes the LM75_I2C.
void | SD_LowLevel_DeInit (void)
DeInitializes the SD/SD communication.
void | SD_LowLevel_Init (void)
Initializes the SD_SPI and CS pins.
void | sEE_LowLevel_DeInit (void)
DeInitializes peripherals used by the I2C EEPROM driver.
void | sEE_LowLevel_DMAConfig (uint32_t pBuffer, uint32_t BufferSize, uint32_t Direction)
Initializes DMA channel used by the I2C EEPROM driver.
void | sEE_LowLevel_Init (void)
Initializes peripherals used by the I2C EEPROM driver.
void | sFLASH_LowLevel_DeInit (void)
DeInitializes the peripherals used by the SPI FLASH driver.
void | sFLASH_LowLevel_Init (void)
Initializes the peripherals used by the SPI FLASH driver.
void | STM_EVAL_COMInit (COM_TypeDef COM, USART_InitTypeDef *USART_InitStruct)
Configures COM port.
void | STM_EVAL_LEDInit (Led_TypeDef Led)
Configures LED GPIO.
void | STM_EVAL_LEDOff (Led_TypeDef Led)
Turns selected LED Off.
void | STM_EVAL_LEDOn (Led_TypeDef Led)
Turns selected LED On.
void | STM_EVAL_LEDToggle (Led_TypeDef Led)
Toggles the selected LED.
uint32_t | STM_EVAL_PBGetState (Button_TypeDef Button)
Returns the selected Button state.
void | STM_EVAL_PBInit (Button_TypeDef Button, ButtonMode_TypeDef Button_Mode)
Configures Button GPIO and EXTI Line.

Function Documentation

void LM75_LowLevel_DeInit ( void )

DeInitializes the LM75_I2C.

Parameters:
None
Return values:
None

< Disable LM75_I2C

< DeInitializes the LM75_I2C

< LM75_I2C Periph clock disable

< Configure LM75_I2C pins: SCL

< Configure LM75_I2C pins: SDA

< Configure LM75_I2C pin: SMBUS ALERT

< Disable LM75_I2C

< DeInitializes the LM75_I2C

< LM75_I2C Periph clock disable

< Configure LM75_I2C pins: SCL

< Configure LM75_I2C pins: SDA

< Configure LM75_I2C pin: SMBUS ALERT

< Disable LM75_I2C

< DeInitializes the LM75_I2C

< LM75_I2C Periph clock disable

< Configure LM75_I2C pins: SCL

< Configure LM75_I2C pins: SDA

< Configure LM75_I2C pin: SMBUS ALERT

< Disable LM75_I2C

< DeInitializes the LM75_I2C

< LM75_I2C Periph clock disable

< Configure LM75_I2C pins: SCL

< Configure LM75_I2C pins: SDA

< Configure LM75_I2C pin: SMBUS ALERT

< Disable LM75_I2C

< DeInitializes the LM75_I2C

< LM75_I2C Periph clock disable

< Configure LM75_I2C pins: SCL

< Configure LM75_I2C pins: SDA

< Configure LM75_I2C pin: SMBUS ALERT

Definition at line 544 of file stm32100b_eval.c.

void LM75_LowLevel_Init ( void )

Initializes the LM75_I2C.

Parameters:
None
Return values:
None
Parameters:
None
Return values:
None

< LM75_I2C Periph clock enable

< LM75_I2C_SCL_GPIO_CLK, LM75_I2C_SDA_GPIO_CLK and LM75_I2C_SMBUSALERT_GPIO_CLK Periph clock enable

< Configure LM75_I2C pins: SCL

< Configure LM75_I2C pins: SDA

< Configure LM75_I2C pin: SMBUS ALERT

< LM75_I2C Periph clock enable

< LM75_I2C_SCL_GPIO_CLK, LM75_I2C_SDA_GPIO_CLK and LM75_I2C_SMBUSALERT_GPIO_CLK Periph clock enable

< Configure LM75_I2C pins: SCL

< Configure LM75_I2C pins: SDA

< Configure LM75_I2C pin: SMBUS ALERT

< LM75_I2C Periph clock enable

< LM75_I2C_SCL_GPIO_CLK, LM75_I2C_SDA_GPIO_CLK and LM75_I2C_SMBUSALERT_GPIO_CLK Periph clock enable

< Configure LM75_I2C pins: SCL

< Configure LM75_I2C pins: SDA

< Configure LM75_I2C pin: SMBUS ALERT

< LM75_I2C Periph clock enable

< LM75_I2C_SCL_GPIO_CLK, LM75_I2C_SDA_GPIO_CLK and LM75_I2C_SMBUSALERT_GPIO_CLK Periph clock enable

< Configure LM75_I2C pins: SCL

< Configure LM75_I2C pins: SDA

< Configure LM75_I2C pin: SMBUS ALERT

< LM75_I2C Periph clock enable

< LM75_I2C_SCL_GPIO_CLK, LM75_I2C_SDA_GPIO_CLK and LM75_I2C_SMBUSALERT_GPIO_CLK Periph clock enable

< Configure LM75_I2C pins: SCL

< Configure LM75_I2C pins: SDA

< Configure LM75_I2C pin: SMBUS ALERT

Definition at line 575 of file stm32100b_eval.c.

void SD_LowLevel_DeInit ( void )

DeInitializes the SD/SD communication.

Parameters:
None
Return values:
None DeInitializes the SD/SD communication.
Parameters:
None
Return values:
None

< SD_SPI disable

< DeInitializes the SD_SPI

< SD_SPI Periph clock disable

< Configure SD_SPI pins: SCK

< Configure SD_SPI pins: MISO

< Configure SD_SPI pins: MOSI

< Configure SD_SPI_CS_PIN pin: SD Card CS pin

< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin

< SD_SPI disable

< DeInitializes the SD_SPI

< SD_SPI Periph clock disable

< Configure SD_SPI pins: SCK

< Configure SD_SPI pins: MISO

< Configure SD_SPI pins: MOSI

< Configure SD_SPI_CS_PIN pin: SD Card CS pin

< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin

< SD_SPI disable

< DeInitializes the SD_SPI

< SD_SPI Periph clock disable

< Configure SD_SPI pins: SCK

< Configure SD_SPI pins: MISO

< Configure SD_SPI pins: MOSI

< Configure SD_SPI_CS_PIN pin: SD Card CS pin

< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin

< SD_SPI disable

< DeInitializes the SD_SPI

< SD_SPI Periph clock disable

< DeRemap SPI3 Pins

< Configure SD_SPI pins: SCK

< Configure SD_SPI pins: MISO

< Configure SD_SPI pins: MOSI

< Configure SD_SPI_CS_PIN pin: SD Card CS pin

< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin

< Disable SDIO Clock

< Set Power State to OFF

< DeInitializes the SDIO peripheral

< Disable the SDIO AHB Clock

< Configure PC.08, PC.09, PC.10, PC.11, PC.12 pin: D0, D1, D2, D3, CLK pin

< Configure PD.02 CMD line

< SD_SPI disable

< DeInitializes the SD_SPI

< SD_SPI Periph clock disable

< Configure SD_SPI pins: SCK

< Configure SD_SPI pins: MISO

< Configure SD_SPI pins: MOSI

< Configure SD_SPI_CS_PIN pin: SD Card CS pin

< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin

Definition at line 373 of file stm32100b_eval.c.

void SD_LowLevel_Init ( void )

Initializes the SD_SPI and CS pins.

Parameters:
None
Return values:
None Initializes the SD_SPI and CS pins.
Parameters:
None
Return values:
None

< SD_SPI_CS_GPIO, SD_SPI_MOSI_GPIO, SD_SPI_MISO_GPIO, SD_SPI_DETECT_GPIO and SD_SPI_SCK_GPIO Periph clock enable

< SD_SPI Periph clock enable

< Configure SD_SPI pins: SCK

< Configure SD_SPI pins: MOSI

< Configure SD_SPI pins: MISO

< Configure SD_SPI_CS_PIN pin: SD Card CS pin

< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin

< SD_SPI Config

< SD_SPI enable

< SD_SPI_CS_GPIO, SD_SPI_MOSI_GPIO, SD_SPI_MISO_GPIO, SD_SPI_DETECT_GPIO and SD_SPI_SCK_GPIO Periph clock enable

< SD_SPI Periph clock enable

< Configure SD_SPI pins: SCK

< Configure SD_SPI pins: MOSI

< Configure SD_SPI pins: MISO

< Configure SD_SPI_CS_PIN pin: SD Card CS pin

< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin

< SD_SPI Config

< SD_SPI enable

< SD_SPI_CS_GPIO, SD_SPI_MOSI_GPIO, SD_SPI_MISO_GPIO, SD_SPI_DETECT_GPIO and SD_SPI_SCK_GPIO Periph clock enable

< SD_SPI Periph clock enable

< Configure SD_SPI pins: SCK

< Configure SD_SPI pins: MOSI

< Configure SD_SPI pins: MISO

< Configure SD_SPI_CS_PIN pin: SD Card CS pin

< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin

< SD_SPI Config

< SD_SPI enable

< SD_SPI_CS_GPIO, SD_SPI_MOSI_GPIO, SD_SPI_MISO_GPIO, SD_SPI_DETECT_GPIO and SD_SPI_SCK_GPIO Periph clock enable

< SD_SPI Periph clock enable

< AFIO Periph clock enable

< Remap SPI3 Pins

< Configure SD_SPI pins: SCK

< Configure SD_SPI pins: MOSI

< Configure SD_SPI pins: MISO

< Configure SD_SPI_CS_PIN pin: SD Card CS pin

< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin

< SD_SPI Config

< SD_SPI enable

< GPIOC and GPIOD Periph clock enable

< Configure PC.08, PC.09, PC.10, PC.11, PC.12 pin: D0, D1, D2, D3, CLK pin

< Configure PD.02 CMD line

< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin

< Enable the SDIO AHB Clock

< Enable the DMA2 Clock

< SD_SPI_CS_GPIO, SD_SPI_MOSI_GPIO, SD_SPI_MISO_GPIO, SD_SPI_DETECT_GPIO and SD_SPI_SCK_GPIO Periph clock enable

< SD_SPI Periph clock enable

< Configure SD_SPI pins: SCK

< Configure SD_SPI pins: MISO

< Configure SD_SPI pins: MOSI

< Configure SD_SPI_CS_PIN pin: SD Card CS pin

< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin

< SD_SPI Config

< SD_SPI enable

Definition at line 410 of file stm32100b_eval.c.

void sEE_LowLevel_DeInit ( void )

DeInitializes peripherals used by the I2C EEPROM driver.

Parameters:
None
Return values:
None

< sEE_I2C Periph clock disable

< GPIO configuration

< Configure sEE_I2C pins: SCL

< Configure sEE_I2C pins: SDA

< sEE_I2C Periph clock disable

< GPIO configuration

< Configure sEE_I2C pins: SCL

< Configure sEE_I2C pins: SDA

< sEE_I2C Periph clock disable

< GPIO configuration

< Configure sEE_I2C pins: SCL

< Configure sEE_I2C pins: SDA

Definition at line 466 of file stm32100e_eval.c.

void sEE_LowLevel_DMAConfig | ( | uint32_t | pBuffer,
 |  | uint32_t | BufferSize,
 |  | uint32_t | Direction
 | ) |  |

Initializes DMA channel used by the I2C EEPROM driver.

Parameters:
None
Return values:
None

Definition at line 583 of file stm32100e_eval.c.

void sEE_LowLevel_Init ( void )

Initializes peripherals used by the I2C EEPROM driver.

Parameters:
None
Return values:
None

< sEE_I2C_SCL_GPIO_CLK and sEE_I2C_SDA_GPIO_CLK Periph clock enable

< sEE_I2C Periph clock enable

< GPIO configuration

< Configure sEE_I2C pins: SCL

< Configure sEE_I2C pins: SDA

< I2C DMA TX and RX channels configuration

< sEE_I2C_SCL_GPIO_CLK and sEE_I2C_SDA_GPIO_CLK Periph clock enable

< sEE_I2C Periph clock enable

< GPIO configuration

< Configure sEE_I2C pins: SCL

< Configure sEE_I2C pins: SDA

< I2C DMA TX and RX channels configuration

< sEE_I2C Periph clock enable

< sEE_I2C_SCL_GPIO_CLK and sEE_I2C_SDA_GPIO_CLK Periph clock enable

< GPIO configuration

< Configure sEE_I2C pins: SCL

< Configure sEE_I2C pins: SDA

< I2C DMA TX and RX channels configuration

Definition at line 515 of file stm32100e_eval.c.

void sFLASH_LowLevel_DeInit ( void )

DeInitializes the peripherals used by the SPI FLASH driver.

Parameters:
None
Return values:
None

< Disable the sFLASH_SPI

< DeInitializes the sFLASH_SPI

< sFLASH_SPI Periph clock disable

< Configure sFLASH_SPI pins: SCK

< Configure sFLASH_SPI pins: MISO

< Configure sFLASH_SPI pins: MOSI

< Configure sFLASH_CS_PIN pin: sFLASH Card CS pin

< Disable the sFLASH_SPI

< DeInitializes the sFLASH_SPI

< sFLASH_SPI Periph clock disable

< Configure sFLASH_SPI pins: SCK

< Configure sFLASH_SPI pins: MISO

< Configure sFLASH_SPI pins: MOSI

< Configure sFLASH_CS_PIN pin: sFLASH Card CS pin

< Disable the sFLASH_SPI

< DeInitializes the sFLASH_SPI

< sFLASH_SPI Periph clock disable

< Configure sFLASH_SPI pins: SCK

< Configure sFLASH_SPI pins: MISO

< Configure sFLASH_SPI pins: MOSI

< Configure sFLASH_CS_PIN pin: sFLASH Card CS pin

< Disable the sFLASH_SPI

< DeInitializes the sFLASH_SPI

< sFLASH_SPI Periph clock disable

< Configure sFLASH_SPI pins: SCK

< Configure sFLASH_SPI pins: MISO

< Configure sFLASH_SPI pins: MOSI

< Configure sFLASH_CS_PIN pin: sFLASH Card CS pin

Definition at line 470 of file stm32100b_eval.c.

void sFLASH_LowLevel_Init ( void )

Initializes the peripherals used by the SPI FLASH driver.

Parameters:
None
Return values:
None

< sFLASH_SPI_CS_GPIO, sFLASH_SPI_MOSI_GPIO, sFLASH_SPI_MISO_GPIO and sFLASH_SPI_SCK_GPIO Periph clock enable

< sFLASH_SPI Periph clock enable

< Configure sFLASH_SPI pins: SCK

< Configure sFLASH_SPI pins: MOSI

< Configure sFLASH_SPI pins: MISO

< Configure sFLASH_CS_PIN pin: sFLASH Card CS pin

< sFLASH_SPI_CS_GPIO, sFLASH_SPI_MOSI_GPIO, sFLASH_SPI_MISO_GPIO and sFLASH_SPI_SCK_GPIO Periph clock enable

< sFLASH_SPI Periph clock enable

< Configure sFLASH_SPI pins: SCK

< Configure sFLASH_SPI pins: MOSI

< Configure sFLASH_SPI pins: MISO

< Configure sFLASH_CS_PIN pin: sFLASH Card CS pin

< sFLASH_SPI_CS_GPIO, sFLASH_SPI_MOSI_GPIO, sFLASH_SPI_MISO_GPIO and sFLASH_SPI_SCK_GPIO Periph clock enable

< sFLASH_SPI Periph clock enable

< Configure sFLASH_SPI pins: SCK

< Configure sFLASH_SPI pins: MOSI

< Configure sFLASH_SPI pins: MISO

< Configure sFLASH_CS_PIN pin: sFLASH Card CS pin

< sFLASH_SPI_CS_GPIO, sFLASH_SPI_MOSI_GPIO, sFLASH_SPI_MISO_GPIO and sFLASH_SPI_SCK_GPIO Periph clock enable

< sFLASH_SPI Periph clock enable

< Configure sFLASH_SPI pins: SCK

< Configure sFLASH_SPI pins: MOSI

< Configure sFLASH_SPI pins: MISO

< Configure sFLASH_CS_PIN pin: sFLASH Card CS pin

Definition at line 506 of file stm32100b_eval.c.

void STM_EVAL_COMInit | ( | COM_TypeDef | COM,
 |  | USART_InitTypeDef * | USART_InitStruct
 | ) |  |

Configures COM port.

Parameters:
COM,: Specifies the COM port to be configured. This parameter can be one of following parameters:

  • COM1
  • COM2
USART_InitStruct,: pointer to a USART_InitTypeDef structure that contains the configuration information for the specified USART peripheral.
Return values:
None

Definition at line 330 of file stm32100b_eval.c.

void STM_EVAL_LEDInit ( Led_TypeDef Led )

Configures LED GPIO.

Parameters:
Led,: Specifies the Led to be configured. This parameter can be one of following parameters:

  • LED1
  • LED2
  • LED3
  • LED4
Return values:
None

Definition at line 176 of file stm32100b_eval.c.

void STM_EVAL_LEDOff ( Led_TypeDef Led )

Turns selected LED Off.

Parameters:
Led,: Specifies the Led to be set off. This parameter can be one of following parameters:

  • LED1
  • LED2
  • LED3
  • LED4
Return values:
None

Definition at line 216 of file stm32100b_eval.c.

void STM_EVAL_LEDOn ( Led_TypeDef Led )

Turns selected LED On.

Parameters:
Led,: Specifies the Led to be set on. This parameter can be one of following parameters:

  • LED1
  • LED2
  • LED3
  • LED4
Return values:
None

Definition at line 201 of file stm32100b_eval.c.

void STM_EVAL_LEDToggle ( Led_TypeDef Led )

Toggles the selected LED.

Parameters:
Led,: Specifies the Led to be toggled. This parameter can be one of following parameters:

  • LED1
  • LED2
  • LED3
  • LED4
Return values:
None

Definition at line 231 of file stm32100b_eval.c.

uint32_t STM_EVAL_PBGetState ( Button_TypeDef Button )

Returns the selected Button state.

Parameters:
Button,: Specifies the Button to be checked. This parameter can be one of following parameters:

  • BUTTON_WAKEUP: Wakeup Push Button
  • BUTTON_TAMPER: Tamper Push Button
  • BUTTON_KEY: Key Push Button
  • BUTTON_RIGHT: Joystick Right Push Button
  • BUTTON_LEFT: Joystick Left Push Button
  • BUTTON_UP: Joystick Up Push Button
  • BUTTON_DOWN: Joystick Down Push Button
  • BUTTON_SEL: Joystick Sel Push Button
Return values:
The Button GPIO pin value.
Parameters:
Button,: Specifies the Button to be checked. This parameter can be one of following parameters:

  • BUTTON_KEY: Key Push Button
  • BUTTON_RIGHT: Joystick Right Push Button
  • BUTTON_LEFT: Joystick Left Push Button
  • BUTTON_UP: Joystick Up Push Button
  • BUTTON_DOWN: Joystick Down Push Button
  • BUTTON_SEL: Joystick Sel Push Button
Return values:
- When Button > 1, the Button GPIO pin value is returned.

  • When Button = 0 or 1, error code (0xFF) is returned.

Definition at line 314 of file stm32100b_eval.c.

void STM_EVAL_PBInit | ( | Button_TypeDef | Button,
 |  | ButtonMode_TypeDef | Button_Mode
 | ) |  |

Configures Button GPIO and EXTI Line.

Parameters:
Button,: Specifies the Button to be configured. This parameter can be one of following parameters:

  • BUTTON_WAKEUP: Wakeup Push Button
  • BUTTON_TAMPER: Tamper Push Button
  • BUTTON_KEY: Key Push Button
  • BUTTON_RIGHT: Joystick Right Push Button
  • BUTTON_LEFT: Joystick Left Push Button
  • BUTTON_UP: Joystick Up Push Button
  • BUTTON_DOWN: Joystick Down Push Button
  • BUTTON_SEL: Joystick Sel Push Button
Button_Mode,: Specifies Button mode. This parameter can be one of following parameters:

  • BUTTON_MODE_GPIO: Button will be used as simple IO
  • BUTTON_MODE_EXTI: Button will be connected to EXTI line with interrupt generation capability
Return values:
None
Parameters:
Button,: Specifies the Button to be configured. This parameter can be one of following parameters:

  • BUTTON_KEY: Key Push Button
  • BUTTON_RIGHT: Joystick Right Push Button
  • BUTTON_LEFT: Joystick Left Push Button
  • BUTTON_UP: Joystick Up Push Button
  • BUTTON_DOWN: Joystick Down Push Button
  • BUTTON_SEL: Joystick Sel Push Button
Button_Mode,: Specifies Button mode. This parameter can be one of following parameters:

  • BUTTON_MODE_GPIO: Button will be used as simple IO
  • BUTTON_MODE_EXTI: Button will be connected to EXTI line with interrupt generation capability
Return values:
None

Definition at line 255 of file stm32100b_eval.c.


STM32F10x Standard Peripherals Firmware Library: STM32100E_EVAL_CEC_Private_Types

STM32100E_EVAL_CEC_Private_Types

STM32100E_EVAL_CEC


STM32F10x Standard Peripherals Firmware Library: STM32100E_EVAL_CEC_Private_Defines

STM32100E_EVAL_CEC_Private_Defines

STM32100E_EVAL_CEC


STM32F10x Standard Peripherals Firmware Library: STM32100E_EVAL_CEC_Private_Macros

STM32100E_EVAL_CEC_Private_Macros

STM32100E_EVAL_CEC


STM32F10x Standard Peripherals Firmware Library: STM32100E_EVAL_CEC_Private_Variables

Variables

STM32100E_EVAL_CEC_Private_Variables

STM32100E_EVAL_CEC

Variables

__IO uint8_t | AbortReason = 0
__IO uint32_t | BufferCount = 0
__IO uint8_t | BufferPointer [15]
__IO uint8_t | CECDevicesNumber = 0
__IO uint8_t | DeviceCount = 0
__IO uint8_t | DeviceType = 0
__IO uint8_t | FeatureOpcode = 0
HDMI_CEC_Map | HDMI_CEC_DeviceMap [14]
uint8_t * | HDMI_CEC_Follower_String [13][2]
HDMI_CEC_Map HDMI_CEC_MapStruct
HDMI_CEC_Message HDMI_CEC_RX_MessageStructPrivate
HDMI_CEC_Message HDMI_CEC_TX_MessageStructPrivate
HDMI_CEC_Message HDMI_CEC_TX_MessageStructure
__IO uint8_t | MyLogicalAddress = 0
__IO uint16_t | MyPhysicalAddress = 0
__IO uint32_t | ReceivedFrame = 0
__IO uint32_t | ReceiveStatus = 0
__IO uint8_t | RecepErrorCode = 0
__IO uint32_t | RxCounter = 0
__IO uint32_t | SendFrame = 0
__IO uint32_t | SendStatus = 0
__IO uint8_t | TransErrorCode = 0
__IO uint32_t | TxCounter = 0

Variable Documentation

__IO uint8_t AbortReason = 0

Definition at line 93 of file stm32100e_eval_cec.c.

__IO uint32_t BufferCount = 0

Definition at line 73 of file stm32100e_eval_cec.c.

__IO uint8_t BufferPointer[15]

Definition at line 74 of file stm32100e_eval_cec.c.

__IO uint8_t CECDevicesNumber = 0

Definition at line 86 of file stm32100e_eval_cec.c.

__IO uint8_t DeviceCount = 0

Definition at line 94 of file stm32100e_eval_cec.c.

__IO uint8_t DeviceType = 0

Definition at line 81 of file stm32100e_eval_cec.c.

__IO uint8_t FeatureOpcode = 0

Definition at line 92 of file stm32100e_eval_cec.c.

HDMI_CEC_Map HDMI_CEC_DeviceMap[14]

Definition at line 97 of file stm32100e_eval_cec.c.

uint8_t* HDMI_CEC_Follower_String[13][2]
Initial value:
  {
    {(uint8_t*)"         TV         ", (uint8_t*)"0"},
    {(uint8_t*)"Recording Device 1  ", (uint8_t*)"0"},
    {(uint8_t*)"Recording Device 2  ", (uint8_t*)"0"},
    {(uint8_t*)"    Tuner 1         ", (uint8_t*)"0"},
    {(uint8_t*)" Playback Device 1  ", (uint8_t*)"0"},
    {(uint8_t*)"   Audio System     ", (uint8_t*)"0"},
    {(uint8_t*)"    Tuner 2         ", (uint8_t*)"0"},
    {(uint8_t*)"    Tuner 3         ", (uint8_t*)"0"},
    {(uint8_t*)" Playback Device 2  ", (uint8_t*)"0"},
    {(uint8_t*)"Recording Device 3  ", (uint8_t*)"0"},
    {(uint8_t*)"      Tuner 4       ", (uint8_t*)"0"},
    {(uint8_t*)" Playback Device 3  ", (uint8_t*)"0"},
    {(uint8_t*)"     Broadcast      ", (uint8_t*)"1"}
  }

Definition at line 100 of file stm32100e_eval_cec.c.

HDMI_CEC_Map HDMI_CEC_MapStruct

Definition at line 96 of file stm32100e_eval_cec.c.

HDMI_CEC_Message HDMI_CEC_RX_MessageStructPrivate

Definition at line 89 of file stm32100e_eval_cec.c.

HDMI_CEC_Message HDMI_CEC_TX_MessageStructPrivate

Definition at line 88 of file stm32100e_eval_cec.c.

HDMI_CEC_Message HDMI_CEC_TX_MessageStructure

Definition at line 90 of file stm32100e_eval_cec.c.

__IO uint8_t MyLogicalAddress = 0

Definition at line 79 of file stm32100e_eval_cec.c.

__IO uint16_t MyPhysicalAddress = 0

Definition at line 80 of file stm32100e_eval_cec.c.

__IO uint32_t ReceivedFrame = 0

Definition at line 71 of file stm32100e_eval_cec.c.

Referenced by CEC_IRQHandler(), HDMI_CEC_ProcessIRQSrc(), and main().

__IO uint32_t ReceiveStatus = 0

Definition at line 75 of file stm32100e_eval_cec.c.

__IO uint8_t RecepErrorCode = 0

Definition at line 78 of file stm32100e_eval_cec.c.

__IO uint32_t RxCounter = 0

Definition at line 73 of file stm32100e_eval_cec.c.

__IO uint32_t SendFrame = 0

Definition at line 72 of file stm32100e_eval_cec.c.

__IO uint32_t SendStatus = 0

Definition at line 76 of file stm32100e_eval_cec.c.

__IO uint8_t TransErrorCode = 0

Definition at line 77 of file stm32100e_eval_cec.c.

__IO uint32_t TxCounter = 0

Definition at line 73 of file stm32100e_eval_cec.c.


STM32F10x Standard Peripherals Firmware Library: STM32100E_EVAL_CEC_Private_Function_Prototypes

STM32100E_EVAL_CEC_Private_Function_Prototypes

STM32100E_EVAL_CEC


STM32F10x Standard Peripherals Firmware Library: STM32100E_EVAL_CEC_Private_Functions

Functions

STM32100E_EVAL_CEC_Private_Functions

STM32100E_EVAL_CEC

Functions

HDMI_CEC_Error | HDMI_CEC_CheckConnectedDevices (void)
Check the connected CEC devices.
void | HDMI_CEC_CommandCallBack (void)
Handle CEC command receive callback.
HDMI_CEC_Error | HDMI_CEC_GetErrorStatus (void)
Get the ESR register status.
HDMI_CEC_Error | HDMI_CEC_Init (void)
Initializes the HDMI CEC.
void | HDMI_CEC_ProcessIRQSrc (void)
Allows to process all the interrupts that are high.
HDMI_CEC_Error | HDMI_CEC_ReportPhysicalAddress (void)
Report physical address to all other devices thus allowing any device to create a map of the network.
HDMI_CEC_Error HDMI_CEC_TransmitMessage (HDMI_CEC_Message *HDMI_CEC_TX_MessageStructure)
Transmit message by taking data from typedef struct CEC_Meassage.
static HDMI_CEC_Error | LogicalAddressAllocation (void)
Allocate the logical address.
static HDMI_CEC_Error | PhysicalAddressDiscovery (void)
Physical address discovery.

Function Documentation

HDMI_CEC_Error HDMI_CEC_CheckConnectedDevices ( void )

Check the connected CEC devices.

Parameters:
None
Return values:
HDMI_CEC_Error

Definition at line 671 of file stm32100e_eval_cec.c.

References CEC_ClearFlag(), CEC_EndOfMessageCmd(), CEC_FLAG_TBTRF, CEC_FLAG_TERR, CEC_GetFlagStatus(), CEC_OwnAddressConfig(), CEC_SendDataByte(), CEC_StartOfMessage(), CECDevicesNumber, DISABLE, ENABLE, HDMI_CEC_Follower_String, HDMI_CEC_GetErrorStatus(), HDMI_CEC_OK, HDMI_CEC_TIMEOUT, HDMI_CEC_TIMEOUT_VALUE, MyLogicalAddress, and RESET.

void HDMI_CEC_CommandCallBack ( void )

Handle CEC command receive callback.

When receiving the STANDBY Opcode commande, the system is entred in Stop mode and when wakeup, the PLL is configured as system clock and the HSI is selected as PLL source.

Parameters:
None
Return values:
None

Definition at line 510 of file stm32100e_eval_cec.c.

References AbortReason, DeviceCount, HDMI_CEC_Map::DeviceType, DISABLE, ENABLE, EXTI_ClearITPendingBit(), EXTI_Init(), EXTI_InitStructure, EXTI_InitTypeDef::EXTI_Line, EXTI_Line8, EXTI_InitTypeDef::EXTI_LineCmd, EXTI_InitTypeDef::EXTI_Mode, EXTI_Mode_Interrupt, EXTI_InitTypeDef::EXTI_Trigger, EXTI_Trigger_Falling, FeatureOpcode, GPIO_EXTILineConfig(), GPIO_PinSource8, GPIO_PortSourceGPIOB, HDMI_CEC_Follower_String, HDMI_CEC_MapStruct, HDMI_CEC_OK, HDMI_CEC_OPCODE_CEC_VERSION, HDMI_CEC_OPCODE_FEATURE_ABORT, HDMI_CEC_OPCODE_GET_CEC_VERSION, HDMI_CEC_OPCODE_GIVE_OSD_NAME, HDMI_CEC_OPCODE_GIVE_PHYSICAL_ADDRESS, HDMI_CEC_OPCODE_REPORT_PHYSICAL_ADDRESS, HDMI_CEC_OPCODE_ROUTING_CHANGE, HDMI_CEC_OPCODE_SET_OSD_NAME, HDMI_CEC_OPCODE_STANDBY, HDMI_CEC_REFUSED, HDMI_CEC_ReportPhysicalAddress(), HDMI_CEC_TransmitMessage(), HDMI_CEC_VERSION, HDMI_CEC_Message::Header, HDMI_CEC_Map::LogicalAddress, MyLogicalAddress, HDMI_CEC_Message::Opcode, HDMI_CEC_Message::Operande, HDMI_CEC_Map::PhysicalAddress_A, HDMI_CEC_Map::PhysicalAddress_B, HDMI_CEC_Map::PhysicalAddress_C, HDMI_CEC_Map::PhysicalAddress_D, PWR_EnterSTOPMode(), PWR_Regulator_ON, PWR_STOPEntry_WFI, RCC_FLAG_PLLRDY, RCC_GetFlagStatus(), RCC_GetSYSCLKSource(), RCC_PLLCmd(), RCC_PLLConfig(), RCC_PLLMul_6, RCC_PLLSource_HSI_Div2, RCC_SYSCLKConfig(), RCC_SYSCLKSource_PLLCLK, RESET, and HDMI_CEC_Message::TxMessageLength.

HDMI_CEC_Error HDMI_CEC_GetErrorStatus ( void )

Get the ESR register status.

Parameters:
None
Return values:
HDMI_CEC_Error,: CEC Error code

Definition at line 343 of file stm32100e_eval_cec.c.

References CEC_ClearFlag(), CEC_FLAG_ACKE, CEC_FLAG_BPE, CEC_FLAG_BTE, CEC_FLAG_LINE, CEC_FLAG_RBTFE, CEC_FLAG_RERR, CEC_FLAG_SBE, CEC_FLAG_TBTFE, CEC_FLAG_TERR, CEC_GetFlagStatus(), HDMI_CEC_BIT_PERIOD, HDMI_CEC_BIT_TIMING, HDMI_CEC_BLOCK_ACKNOWLEDGE, HDMI_CEC_LINE, HDMI_CEC_OK, HDMI_CEC_RX_BLOCK_FINISHED, HDMI_CEC_START_BIT, HDMI_CEC_TX_BLOCK_FINISHED, and RESET.

HDMI_CEC_Error HDMI_CEC_Init ( void )

Initializes the HDMI CEC.

Parameters:
None
Return values:
HDMI_CEC_Error,: CEC Error code

Definition at line 143 of file stm32100e_eval_cec.c.

References CEC_InitTypeDef::CEC_BitPeriodMode, CEC_BitPeriodStdMode, CEC_InitTypeDef::CEC_BitTimingMode, CEC_BitTimingStdMode, CEC_Cmd(), CEC_DeInit(), CEC_Init(), CEC_InitStructure, CEC_ITConfig(), CEC_OwnAddressConfig(), CEC_SetPrescaler(), ENABLE, GPIO_Init(), GPIO_InitStructure, GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_AF_OD, GPIO_Mode_IPD, GPIO_InitTypeDef::GPIO_Pin, GPIO_InitTypeDef::GPIO_Speed, GPIO_Speed_50MHz, HDMI_CEC_CheckConnectedDevices(), HDMI_CEC_HPD_GPIO_CLK, HDMI_CEC_HPD_GPIO_PORT, HDMI_CEC_HPD_PIN, HDMI_CEC_I2C, HDMI_CEC_I2C_CLK, HDMI_CEC_I2C_CLOCK_SPEED, HDMI_CEC_I2C_GPIO_CLK, HDMI_CEC_I2C_GPIO_PORT, HDMI_CEC_I2C_SCL_PIN, HDMI_CEC_I2C_SDA_PIN, HDMI_CEC_I2C_SLAVE_ADDRESS7, HDMI_CEC_LINE_GPIO_CLK, HDMI_CEC_LINE_GPIO_PORT, HDMI_CEC_LINE_PIN, HDMI_CEC_OK, HDMI_CEC_ReportPhysicalAddress(), I2C_InitTypeDef::I2C_Ack, I2C_Ack_Enable, I2C_InitTypeDef::I2C_AcknowledgedAddress, I2C_AcknowledgedAddress_7bit, I2C_InitTypeDef::I2C_ClockSpeed, I2C_Cmd(), I2C_InitTypeDef::I2C_DutyCycle, I2C_DutyCycle_2, I2C_Init(), I2C_InitStructure, I2C_InitTypeDef::I2C_Mode, I2C_Mode_I2C, I2C_InitTypeDef::I2C_OwnAddress1, LogicalAddressAllocation(), MyLogicalAddress, PhysicalAddressDiscovery(), RCC_APB1Periph_CEC, RCC_APB1PeriphClockCmd(), and RCC_APB2PeriphClockCmd().

void HDMI_CEC_ProcessIRQSrc ( void )

Allows to process all the interrupts that are high.

Parameters:
None
Return values:
None

Definition at line 393 of file stm32100e_eval_cec.c.

References BufferPointer, CEC_ClearFlag(), CEC_EndOfMessageCmd(), CEC_FLAG_RBTF, CEC_FLAG_REOM, CEC_FLAG_RERR, CEC_FLAG_RSOM, CEC_FLAG_TBTRF, CEC_FLAG_TEOM, CEC_FLAG_TERR, CEC_GetFlagStatus(), CEC_ReceiveDataByte(), CEC_SendDataByte(), DISABLE, ENABLE, HDMI_CEC_GetErrorStatus(), HDMI_CEC_Message::Header, HDMI_CEC_Message::Opcode, HDMI_CEC_Message::Operande, ReceivedFrame, ReceiveStatus, RecepErrorCode, RxCounter, HDMI_CEC_Message::RxMessageLength, SendFrame, SendStatus, SUCCESS, TransErrorCode, TxCounter, and HDMI_CEC_Message::TxMessageLength.

HDMI_CEC_Error HDMI_CEC_ReportPhysicalAddress ( void )

Report physical address to all other devices thus allowing any device to create a map of the network.

Parameters:
None
Return values:
HDMI_CEC_Error,: CEC Error code.

Definition at line 485 of file stm32100e_eval_cec.c.

References DeviceType, HDMI_CEC_OK, HDMI_CEC_OPCODE_REPORT_PHYSICAL_ADDRESS, HDMI_CEC_TransmitMessage(), HDMI_CEC_Message::Header, MyLogicalAddress, MyPhysicalAddress, HDMI_CEC_Message::Opcode, HDMI_CEC_Message::Operande, and HDMI_CEC_Message::TxMessageLength.

HDMI_CEC_Error HDMI_CEC_TransmitMessage ( HDMI_CEC_Message * HDMI_CEC_TX_MessageStructure )

Transmit message by taking data from typedef struct CEC_Meassage.

Parameters:
CEC_TX_MessageStructure,: pointer to an CEC_Message structure that contains the message to be sent.
Return values:
HDMI_CEC_Error,: CEC Error code

Definition at line 286 of file stm32100e_eval_cec.c.

References BufferCount, BufferPointer, CEC_ClearFlag(), CEC_FLAG_TBTRF, CEC_FLAG_TERR, CEC_SendDataByte(), CEC_StartOfMessage(), HDMI_CEC_OK, HDMI_CEC_TIMEOUT, HDMI_CEC_TIMEOUT_VALUE, HDMI_CEC_TX_MessageStructure, HDMI_CEC_Message::Header, j, HDMI_CEC_Message::Opcode, HDMI_CEC_Message::Operande, SendFrame, SendStatus, TransErrorCode, TxCounter, and HDMI_CEC_Message::TxMessageLength.

static HDMI_CEC_Error LogicalAddressAllocation ( void ) [static]

Allocate the logical address.

Parameters:
None
Return values:
HDMI_CEC_Error,: CEC Error code.

Definition at line 1211 of file stm32100e_eval_cec.c.

References CEC_ClearFlag(), CEC_EndOfMessageCmd(), CEC_FLAG_TBTRF, CEC_FLAG_TERR, CEC_GetFlagStatus(), CEC_OwnAddressConfig(), CEC_SendDataByte(), CEC_StartOfMessage(), DeviceType, DISABLE, ENABLE, HDMI_CEC_AUDIOSYSTEM, HDMI_CEC_BLOCK_ACKNOWLEDGE, HDMI_CEC_DEVICE_UNREGISTRED, HDMI_CEC_GetErrorStatus(), HDMI_CEC_OK, HDMI_CEC_PLAYBACK, HDMI_CEC_RECORDING, HDMI_CEC_ROOT, HDMI_CEC_TIMEOUT, HDMI_CEC_TIMEOUT_VALUE, HDMI_CEC_TUNER, HDMI_CEC_TV, MyLogicalAddress, and RESET.

Referenced by HDMI_CEC_Init().

static HDMI_CEC_Error PhysicalAddressDiscovery ( void ) [static]

Physical address discovery.

Parameters:
None
Return values:
HDMI_CEC_Error,: CEC Error code.

Definition at line 1093 of file stm32100e_eval_cec.c.

References DISABLE, ENABLE, GPIO_ReadInputDataBit(), HDMI_CEC_HPD_GPIO_PORT, HDMI_CEC_HPD_PIN, HDMI_CEC_I2C, HDMI_CEC_OK, HDMI_CEC_ROOT, I2C_AcknowledgeConfig(), I2C_CheckEvent(), I2C_Direction_Receiver, I2C_Direction_Transmitter, I2C_EVENT_MASTER_BYTE_RECEIVED, I2C_EVENT_MASTER_BYTE_TRANSMITTED, I2C_EVENT_MASTER_MODE_SELECT, I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED, I2C_FLAG_BUSY, I2C_GenerateSTART(), I2C_GenerateSTOP(), I2C_GetFlagStatus(), I2C_ReceiveData(), I2C_Send7bitAddress(), I2C_SendData(), index, MyPhysicalAddress, and RESET.

Referenced by HDMI_CEC_Init().


STM32F10x Standard Peripherals Firmware Library: STM32100E_EVAL_CEC_Exported_Types

Data Structures | Defines | Enumerations

STM32100E_EVAL_CEC_Exported_Types

STM32100E_EVAL_CEC

Data Structures

struct | HDMI_CEC_Map
struct | HDMI_CEC_Message
CEC Init Structure definition. More...

Defines

#define | HDMI_CEC_TIMEOUT_VALUE ((uint32_t)0x001FFFFF)
#define | HDMI_CEC_TX_MESSAGE_LENGTH_MAX ((uint32_t)0x0000000E)

Enumerations

enum HDMI_CEC_Error {
HDMI_CEC_BIT_TIMING = (1), HDMI_CEC_BIT_PERIOD = (2), HDMI_CEC_RX_BLOCK_FINISHED = (3), HDMI_CEC_START_BIT = (4),
HDMI_CEC_BLOCK_ACKNOWLEDGE = (5), HDMI_CEC_LINE = (6), HDMI_CEC_TX_BLOCK_FINISHED = (7), HDMI_CEC_DEVICE_UNREGISTRED = (8),
HDMI_CEC_TIMEOUT = (9), HDMI_CEC_OK = (10), HDMI_CEC_BIT_TIMING = (1), HDMI_CEC_BIT_PERIOD = (2),
HDMI_CEC_RX_BLOCK_FINISHED = (3), HDMI_CEC_START_BIT = (4), HDMI_CEC_BLOCK_ACKNOWLEDGE = (5), HDMI_CEC_LINE = (6),
HDMI_CEC_TX_BLOCK_FINISHED = (7), HDMI_CEC_DEVICE_UNREGISTRED = (8), HDMI_CEC_TIMEOUT = (9), HDMI_CEC_OK = (10)
}

Define Documentation

#define HDMI_CEC_TIMEOUT_VALUE ((uint32_t)0x001FFFFF)

Definition at line 80 of file stm32100e_eval_cec.h.

#define HDMI_CEC_TX_MESSAGE_LENGTH_MAX ((uint32_t)0x0000000E)

Definition at line 79 of file stm32100e_eval_cec.h.

Enumeration Type Documentation

enum HDMI_CEC_Error
Enumerator:
HDMI_CEC_BIT_TIMING

CEC Bit Timing Error

HDMI_CEC_BIT_PERIOD

CEC Bit Period Error

HDMI_CEC_RX_BLOCK_FINISHED

CEC Receive Block finished Error

HDMI_CEC_START_BIT

CEC Start Bit Error

HDMI_CEC_BLOCK_ACKNOWLEDGE

CEC Block Acknowledge Error

HDMI_CEC_LINE

CEC Line Error

HDMI_CEC_TX_BLOCK_FINISHED

CEC Transmit Block Transfer finished Error

HDMI_CEC_DEVICE_UNREGISTRED

CEC Device Unregistred

HDMI_CEC_TIMEOUT

CEC TimeOut

HDMI_CEC_OK

CEC OK

HDMI_CEC_BIT_TIMING

CEC Bit Timing Error

HDMI_CEC_BIT_PERIOD

CEC Bit Period Error

HDMI_CEC_RX_BLOCK_FINISHED

CEC Receive Block finished Error

HDMI_CEC_START_BIT

CEC Start Bit Error

HDMI_CEC_BLOCK_ACKNOWLEDGE

CEC Block Acknowledge Error

HDMI_CEC_LINE

CEC Line Error

HDMI_CEC_TX_BLOCK_FINISHED

CEC Transmit Block Transfer finished Error

HDMI_CEC_DEVICE_UNREGISTRED

CEC Device Unregistred

HDMI_CEC_TIMEOUT

CEC TimeOut

HDMI_CEC_OK

CEC OK

Definition at line 54 of file stm32100e_eval_cec.h.


STM32F10x Standard Peripherals Firmware Library: STM32100E_EVAL_CEC_Exported_Constants

Defines

STM32100E_EVAL_CEC_Exported_Constants

STM32100E_EVAL_CEC

Defines

#define | HDMI_CEC_AUDIOSYSTEM 0x05
#define | HDMI_CEC_CANNOTPROVIDE_SOURCE 0x02
#define | HDMI_CEC_HPD_GPIO_CLK RCC_APB2Periph_GPIOB
#define | HDMI_CEC_HPD_GPIO_PORT GPIOB
#define | HDMI_CEC_HPD_PIN GPIO_Pin_9
HDMI CEC HPD (Hot Plug Detect) Interface pin.
#define | HDMI_CEC_I2C I2C1
#define | HDMI_CEC_I2C_CLK RCC_APB1Periph_I2C1
#define | HDMI_CEC_I2C_CLOCK_SPEED 100000
#define | HDMI_CEC_I2C_GPIO_CLK RCC_APB2Periph_GPIOB
#define | HDMI_CEC_I2C_GPIO_PORT GPIOB
#define | HDMI_CEC_I2C_SCL_PIN GPIO_Pin_6
HDMI CEC I2C Interface pins.
#define | HDMI_CEC_I2C_SDA_PIN GPIO_Pin_7
#define | HDMI_CEC_I2C_SLAVE_ADDRESS7 0xA0
#define | HDMI_CEC_INVALID_OPERAND 0x03
#define | HDMI_CEC_LINE_GPIO_CLK RCC_APB2Periph_GPIOB
#define | HDMI_CEC_LINE_GPIO_PORT GPIOB
#define | HDMI_CEC_LINE_PIN GPIO_Pin_8
HDMI CEC Interface pin.
#define | HDMI_CEC_NOT_CORRECT_MODETORESPOND 0x01
#define | HDMI_CEC_OPCODE_ABORT ((uint8_t) 0xFF)
#define | HDMI_CEC_OPCODE_ACTIVE_SOURCE ((uint8_t) 0x82)
HDMI CEC specific commands.
#define | HDMI_CEC_OPCODE_CEC_VERSION ((uint8_t) 0x9E)
#define | HDMI_CEC_OPCODE_CLEAR_ANALOGUE_TIMER ((uint8_t) 0x33)
#define | HDMI_CEC_OPCODE_CLEAR_DIGITAL_TIMER ((uint8_t) 0x99)
#define | HDMI_CEC_OPCODE_CLEAR_EXTERNAL_TIMER ((uint8_t) 0xA1)
#define | HDMI_CEC_OPCODE_DECK_CONTROL ((uint8_t) 0x42)
#define | HDMI_CEC_OPCODE_DECK_STATUS ((uint8_t) 0x1B)
#define | HDMI_CEC_OPCODE_DEVICE_VENDOR_ID ((uint8_t) 0x87)
#define | HDMI_CEC_OPCODE_FEATURE_ABORT ((uint8_t) 0x00)
#define | HDMI_CEC_OPCODE_GET_CEC_VERSION ((uint8_t) 0x9F)
#define | HDMI_CEC_OPCODE_GET_MENU_LANGUAGE ((uint8_t) 0x91)
#define | HDMI_CEC_OPCODE_GIVE_AUDIO_STATUS ((uint8_t) 0x71)
#define | HDMI_CEC_OPCODE_GIVE_DECK_STATUS ((uint8_t) 0x1A)
#define | HDMI_CEC_OPCODE_GIVE_DEVICE_POWER_STATUS ((uint8_t) 0x8F)
#define | HDMI_CEC_OPCODE_GIVE_DEVICE_VENDOR_ID ((uint8_t) 0x8C)
#define | HDMI_CEC_OPCODE_GIVE_OSD_NAME ((uint8_t) 0x46)
#define | HDMI_CEC_OPCODE_GIVE_PHYSICAL_ADDRESS ((uint8_t) 0x83)
#define | HDMI_CEC_OPCODE_GIVE_SYSTEM_AUDIO_MODE_STATUS ((uint8_t) 0x7D)
#define | HDMI_CEC_OPCODE_GIVE_TUNER_DEVICE_STATUS ((uint8_t) 0x08)
#define | HDMI_CEC_OPCODE_IMAGE_VIEW_ON ((uint8_t) 0x04)
#define | HDMI_CEC_OPCODE_INACTIVE_SOURCE ((uint8_t) 0x9D)
#define | HDMI_CEC_OPCODE_MENU_REQUEST ((uint8_t) 0x8D)
#define | HDMI_CEC_OPCODE_MENU_STATUS ((uint8_t) 0x8E)
#define | HDMI_CEC_OPCODE_PLAY ((uint8_t) 0x41)
#define | HDMI_CEC_OPCODE_RECORD_OFF ((uint8_t) 0x0B)
#define | HDMI_CEC_OPCODE_RECORD_ON ((uint8_t) 0x09)
#define | HDMI_CEC_OPCODE_RECORD_STATUS ((uint8_t) 0x0A)
#define | HDMI_CEC_OPCODE_RECORD_TV_SCREEN ((uint8_t) 0x0F)
#define | HDMI_CEC_OPCODE_REPORT_AUDIO_STATUS ((uint8_t) 0x7A)
#define | HDMI_CEC_OPCODE_REPORT_PHYSICAL_ADDRESS ((uint8_t) 0x84)
#define | HDMI_CEC_OPCODE_REPORT_POWER_STATUS ((uint8_t) 0x90)
#define | HDMI_CEC_OPCODE_REQUEST_ACTIVE_SOURCE ((uint8_t) 0x85)
#define | HDMI_CEC_OPCODE_ROUTING_CHANGE ((uint8_t) 0x80)
#define | HDMI_CEC_OPCODE_ROUTING_INFORMATION ((uint8_t) 0x81)
#define | HDMI_CEC_OPCODE_SELECT_ANALOGUE_SERVICE ((uint8_t) 0x92)
#define | HDMI_CEC_OPCODE_SELECT_DIGITAL_SERVICE ((uint8_t) 0x93)
#define | HDMI_CEC_OPCODE_SET_ANALOGUE_TIMER ((uint8_t) 0x34)
#define | HDMI_CEC_OPCODE_SET_AUDIO_RATE ((uint8_t) 0x9A)
#define | HDMI_CEC_OPCODE_SET_DIGITAL_TIMER ((uint8_t) 0x97)
#define | HDMI_CEC_OPCODE_SET_EXTERNAL_TIMER ((uint8_t) 0xA2)
#define | HDMI_CEC_OPCODE_SET_MENU_LANGUAGE ((uint8_t) 0x32)
#define | HDMI_CEC_OPCODE_SET_OSD_NAME ((uint8_t) 0x47)
#define | HDMI_CEC_OPCODE_SET_OSD_STRING ((uint8_t) 0x64)
#define | HDMI_CEC_OPCODE_SET_STREAM_PATH ((uint8_t) 0x86)
#define | HDMI_CEC_OPCODE_SET_SYSTEM_AUDIO_MODE ((uint8_t) 0x72)
#define | HDMI_CEC_OPCODE_SET_TIMER_PROGRAM_TITLE ((uint8_t) 0x67)
#define | HDMI_CEC_OPCODE_STANDBY ((uint8_t) 0x36)
#define | HDMI_CEC_OPCODE_SYSTEM_AUDIO_MODE_REQUEST ((uint8_t) 0x70)
#define | HDMI_CEC_OPCODE_SYSTEM_AUDIO_MODE_STATUS ((uint8_t) 0x7E)
#define | HDMI_CEC_OPCODE_TEXT_VIEW_ON ((uint8_t) 0x0D)
#define | HDMI_CEC_OPCODE_TIMER_CLEARED_STATUS ((uint8_t) 0x43)
#define | HDMI_CEC_OPCODE_TIMER_STATUS ((uint8_t) 0x35)
#define | HDMI_CEC_OPCODE_TUNER_DEVICE_STATUS ((uint8_t) 0x07)
#define | HDMI_CEC_OPCODE_TUNER_STEP_DECREMENT ((uint8_t) 0x06)
#define | HDMI_CEC_OPCODE_TUNER_STEP_INCREMENT ((uint8_t) 0x05)
#define | HDMI_CEC_OPCODE_USER_CONTROL_PRESSED ((uint8_t) 0x44)
#define | HDMI_CEC_OPCODE_USER_CONTROL_RELEASED ((uint8_t) 0x45)
#define | HDMI_CEC_OPCODE_VENDOR_COMMAND ((uint8_t) 0x89)
#define | HDMI_CEC_OPCODE_VENDOR_COMMAND_WITH_ID ((uint8_t) 0xA0)
#define | HDMI_CEC_OPCODE_VENDOR_REMOTE_BUTTON_DOWN ((uint8_t) 0x8A)
#define | HDMI_CEC_OPCODE_VENDOR_REMOTE_BUTTON_UP ((uint8_t) 0x8B)
#define | HDMI_CEC_PLAYBACK 0x04
#define | HDMI_CEC_RECORDING 0x01
#define | HDMI_CEC_REFUSED 0x04
#define | HDMI_CEC_ROOT 0x00
HDMI CEC Root (Mainly for TV with a fixed physical address (0.0.0.0)) If you want to configure the STM32100E-EVAL board as CEC Root (Sink) change the following define to 0x1.
#define | HDMI_CEC_TUNER 0x03
#define | HDMI_CEC_TV 0x00
CEC device types.
#define | HDMI_CEC_UNRECOGNIZED_OPCODE 0x00
Reason for Abort feature.
#define | HDMI_CEC_VERSION 0x04
To select if the DDC Channel will be used for physical address discovery or not.

Define Documentation

#define HDMI_CEC_AUDIOSYSTEM 0x05

Definition at line 109 of file stm32100e_eval_cec.h.

#define HDMI_CEC_CANNOTPROVIDE_SOURCE 0x02

Definition at line 165 of file stm32100e_eval_cec.h.

#define HDMI_CEC_HPD_GPIO_CLK RCC_APB2Periph_GPIOB

Definition at line 127 of file stm32100e_eval_cec.h.

#define HDMI_CEC_HPD_GPIO_PORT GPIOB

Definition at line 126 of file stm32100e_eval_cec.h.

#define HDMI_CEC_HPD_PIN GPIO_Pin_9

HDMI CEC HPD (Hot Plug Detect) Interface pin.

Definition at line 125 of file stm32100e_eval_cec.h.

#define HDMI_CEC_I2C I2C1

Definition at line 119 of file stm32100e_eval_cec.h.

#define HDMI_CEC_I2C_CLK RCC_APB1Periph_I2C1

Definition at line 120 of file stm32100e_eval_cec.h.

#define HDMI_CEC_I2C_CLOCK_SPEED 100000

Definition at line 137 of file stm32100e_eval_cec.h.

#define HDMI_CEC_I2C_GPIO_CLK RCC_APB2Periph_GPIOB

Definition at line 118 of file stm32100e_eval_cec.h.

#define HDMI_CEC_I2C_GPIO_PORT GPIOB

Definition at line 117 of file stm32100e_eval_cec.h.

#define HDMI_CEC_I2C_SCL_PIN GPIO_Pin_6

HDMI CEC I2C Interface pins.

Definition at line 115 of file stm32100e_eval_cec.h.

#define HDMI_CEC_I2C_SDA_PIN GPIO_Pin_7

Definition at line 116 of file stm32100e_eval_cec.h.

#define HDMI_CEC_I2C_SLAVE_ADDRESS7 0xA0

Definition at line 136 of file stm32100e_eval_cec.h.

#define HDMI_CEC_INVALID_OPERAND 0x03

Definition at line 166 of file stm32100e_eval_cec.h.

#define HDMI_CEC_LINE_GPIO_CLK RCC_APB2Periph_GPIOB

Definition at line 134 of file stm32100e_eval_cec.h.

#define HDMI_CEC_LINE_GPIO_PORT GPIOB

Definition at line 133 of file stm32100e_eval_cec.h.

#define HDMI_CEC_LINE_PIN GPIO_Pin_8

HDMI CEC Interface pin.

Definition at line 132 of file stm32100e_eval_cec.h.

#define HDMI_CEC_NOT_CORRECT_MODETORESPOND 0x01

Definition at line 164 of file stm32100e_eval_cec.h.

#define HDMI_CEC_OPCODE_ABORT ((uint8_t) 0xFF)

Definition at line 226 of file stm32100e_eval_cec.h.

#define HDMI_CEC_OPCODE_ACTIVE_SOURCE ((uint8_t) 0x82)

HDMI CEC specific commands.

Definition at line 172 of file stm32100e_eval_cec.h.

#define HDMI_CEC_OPCODE_CEC_VERSION ((uint8_t) 0x9E)

Definition at line 194 of file stm32100e_eval_cec.h.

#define HDMI_CEC_OPCODE_CLEAR_ANALOGUE_TIMER ((uint8_t) 0x33)

Definition at line 185 of file stm32100e_eval_cec.h.

#define HDMI_CEC_OPCODE_CLEAR_DIGITAL_TIMER ((uint8_t) 0x99)

Definition at line 186 of file stm32100e_eval_cec.h.

#define HDMI_CEC_OPCODE_CLEAR_EXTERNAL_TIMER ((uint8_t) 0xA1)

Definition at line 187 of file stm32100e_eval_cec.h.

#define HDMI_CEC_OPCODE_DECK_CONTROL ((uint8_t) 0x42)

Definition at line 200 of file stm32100e_eval_cec.h.

#define HDMI_CEC_OPCODE_DECK_STATUS ((uint8_t) 0x1B)

Definition at line 201 of file stm32100e_eval_cec.h.

#define HDMI_CEC_OPCODE_DEVICE_VENDOR_ID ((uint8_t) 0x87)

Definition at line 210 of file stm32100e_eval_cec.h.

#define HDMI_CEC_OPCODE_FEATURE_ABORT ((uint8_t) 0x00)

Definition at line 225 of file stm32100e_eval_cec.h.

#define HDMI_CEC_OPCODE_GET_CEC_VERSION ((uint8_t) 0x9F)

Definition at line 195 of file stm32100e_eval_cec.h.

#define HDMI_CEC_OPCODE_GET_MENU_LANGUAGE ((uint8_t) 0x91)

Definition at line 197 of file stm32100e_eval_cec.h.

#define HDMI_CEC_OPCODE_GIVE_AUDIO_STATUS ((uint8_t) 0x71)

Definition at line 227 of file stm32100e_eval_cec.h.

#define HDMI_CEC_OPCODE_GIVE_DECK_STATUS ((uint8_t) 0x1A)

Definition at line 202 of file stm32100e_eval_cec.h.

#define HDMI_CEC_OPCODE_GIVE_DEVICE_POWER_STATUS ((uint8_t) 0x8F)

Definition at line 223 of file stm32100e_eval_cec.h.

#define HDMI_CEC_OPCODE_GIVE_DEVICE_VENDOR_ID ((uint8_t) 0x8C)

Definition at line 211 of file stm32100e_eval_cec.h.

#define HDMI_CEC_OPCODE_GIVE_OSD_NAME ((uint8_t) 0x46)

Definition at line 217 of file stm32100e_eval_cec.h.

#define HDMI_CEC_OPCODE_GIVE_PHYSICAL_ADDRESS ((uint8_t) 0x83)

Definition at line 196 of file stm32100e_eval_cec.h.

#define HDMI_CEC_OPCODE_GIVE_SYSTEM_AUDIO_MODE_STATUS ((uint8_t) 0x7D)

Definition at line 228 of file stm32100e_eval_cec.h.

#define HDMI_CEC_OPCODE_GIVE_TUNER_DEVICE_STATUS ((uint8_t) 0x08)

Definition at line 204 of file stm32100e_eval_cec.h.

#define HDMI_CEC_OPCODE_IMAGE_VIEW_ON ((uint8_t) 0x04)

Definition at line 173 of file stm32100e_eval_cec.h.

#define HDMI_CEC_OPCODE_INACTIVE_SOURCE ((uint8_t) 0x9D)

Definition at line 175 of file stm32100e_eval_cec.h.

#define HDMI_CEC_OPCODE_MENU_REQUEST ((uint8_t) 0x8D)

Definition at line 219 of file stm32100e_eval_cec.h.

#define HDMI_CEC_OPCODE_MENU_STATUS ((uint8_t) 0x8E)

Definition at line 220 of file stm32100e_eval_cec.h.

#define HDMI_CEC_OPCODE_PLAY ((uint8_t) 0x41)

Definition at line 203 of file stm32100e_eval_cec.h.

#define HDMI_CEC_OPCODE_RECORD_OFF ((uint8_t) 0x0B)

Definition at line 181 of file stm32100e_eval_cec.h.

#define HDMI_CEC_OPCODE_RECORD_ON ((uint8_t) 0x09)

Definition at line 182 of file stm32100e_eval_cec.h.

#define HDMI_CEC_OPCODE_RECORD_STATUS ((uint8_t) 0x0A)

Definition at line 183 of file stm32100e_eval_cec.h.

#define HDMI_CEC_OPCODE_RECORD_TV_SCREEN ((uint8_t) 0x0F)

Definition at line 184 of file stm32100e_eval_cec.h.

#define HDMI_CEC_OPCODE_REPORT_AUDIO_STATUS ((uint8_t) 0x7A)

Definition at line 229 of file stm32100e_eval_cec.h.

#define HDMI_CEC_OPCODE_REPORT_PHYSICAL_ADDRESS ((uint8_t) 0x84)

Definition at line 198 of file stm32100e_eval_cec.h.

#define HDMI_CEC_OPCODE_REPORT_POWER_STATUS ((uint8_t) 0x90)

Definition at line 224 of file stm32100e_eval_cec.h.

#define HDMI_CEC_OPCODE_REQUEST_ACTIVE_SOURCE ((uint8_t) 0x85)

Definition at line 176 of file stm32100e_eval_cec.h.

#define HDMI_CEC_OPCODE_ROUTING_CHANGE ((uint8_t) 0x80)

Definition at line 177 of file stm32100e_eval_cec.h.

#define HDMI_CEC_OPCODE_ROUTING_INFORMATION ((uint8_t) 0x81)

Definition at line 178 of file stm32100e_eval_cec.h.

#define HDMI_CEC_OPCODE_SELECT_ANALOGUE_SERVICE ((uint8_t) 0x92)

Definition at line 205 of file stm32100e_eval_cec.h.

#define HDMI_CEC_OPCODE_SELECT_DIGITAL_SERVICE ((uint8_t) 0x93)

Definition at line 206 of file stm32100e_eval_cec.h.

#define HDMI_CEC_OPCODE_SET_ANALOGUE_TIMER ((uint8_t) 0x34)

Definition at line 188 of file stm32100e_eval_cec.h.

#define HDMI_CEC_OPCODE_SET_AUDIO_RATE ((uint8_t) 0x9A)

Definition at line 233 of file stm32100e_eval_cec.h.

#define HDMI_CEC_OPCODE_SET_DIGITAL_TIMER ((uint8_t) 0x97)

Definition at line 189 of file stm32100e_eval_cec.h.

#define HDMI_CEC_OPCODE_SET_EXTERNAL_TIMER ((uint8_t) 0xA2)

Definition at line 190 of file stm32100e_eval_cec.h.

#define HDMI_CEC_OPCODE_SET_MENU_LANGUAGE ((uint8_t) 0x32)

Definition at line 199 of file stm32100e_eval_cec.h.

#define HDMI_CEC_OPCODE_SET_OSD_NAME ((uint8_t) 0x47)

Definition at line 218 of file stm32100e_eval_cec.h.

#define HDMI_CEC_OPCODE_SET_OSD_STRING ((uint8_t) 0x64)

Definition at line 216 of file stm32100e_eval_cec.h.

#define HDMI_CEC_OPCODE_SET_STREAM_PATH ((uint8_t) 0x86)

Definition at line 179 of file stm32100e_eval_cec.h.

#define HDMI_CEC_OPCODE_SET_SYSTEM_AUDIO_MODE ((uint8_t) 0x72)

Definition at line 230 of file stm32100e_eval_cec.h.

#define HDMI_CEC_OPCODE_SET_TIMER_PROGRAM_TITLE ((uint8_t) 0x67)

Definition at line 191 of file stm32100e_eval_cec.h.

#define HDMI_CEC_OPCODE_STANDBY ((uint8_t) 0x36)

Definition at line 180 of file stm32100e_eval_cec.h.

#define HDMI_CEC_OPCODE_SYSTEM_AUDIO_MODE_REQUEST ((uint8_t) 0x70)

Definition at line 231 of file stm32100e_eval_cec.h.

#define HDMI_CEC_OPCODE_SYSTEM_AUDIO_MODE_STATUS ((uint8_t) 0x7E)

Definition at line 232 of file stm32100e_eval_cec.h.

#define HDMI_CEC_OPCODE_TEXT_VIEW_ON ((uint8_t) 0x0D)

Definition at line 174 of file stm32100e_eval_cec.h.

#define HDMI_CEC_OPCODE_TIMER_CLEARED_STATUS ((uint8_t) 0x43)

Definition at line 192 of file stm32100e_eval_cec.h.

#define HDMI_CEC_OPCODE_TIMER_STATUS ((uint8_t) 0x35)

Definition at line 193 of file stm32100e_eval_cec.h.

#define HDMI_CEC_OPCODE_TUNER_DEVICE_STATUS ((uint8_t) 0x07)

Definition at line 207 of file stm32100e_eval_cec.h.

#define HDMI_CEC_OPCODE_TUNER_STEP_DECREMENT ((uint8_t) 0x06)

Definition at line 208 of file stm32100e_eval_cec.h.

#define HDMI_CEC_OPCODE_TUNER_STEP_INCREMENT ((uint8_t) 0x05)

Definition at line 209 of file stm32100e_eval_cec.h.

#define HDMI_CEC_OPCODE_USER_CONTROL_PRESSED ((uint8_t) 0x44)

Definition at line 221 of file stm32100e_eval_cec.h.

#define HDMI_CEC_OPCODE_USER_CONTROL_RELEASED ((uint8_t) 0x45)

Definition at line 222 of file stm32100e_eval_cec.h.

#define HDMI_CEC_OPCODE_VENDOR_COMMAND ((uint8_t) 0x89)

Definition at line 212 of file stm32100e_eval_cec.h.

#define HDMI_CEC_OPCODE_VENDOR_COMMAND_WITH_ID ((uint8_t) 0xA0)

Definition at line 213 of file stm32100e_eval_cec.h.

#define HDMI_CEC_OPCODE_VENDOR_REMOTE_BUTTON_DOWN ((uint8_t) 0x8A)

Definition at line 214 of file stm32100e_eval_cec.h.

#define HDMI_CEC_OPCODE_VENDOR_REMOTE_BUTTON_UP ((uint8_t) 0x8B)

Definition at line 215 of file stm32100e_eval_cec.h.

#define HDMI_CEC_PLAYBACK 0x04

Definition at line 108 of file stm32100e_eval_cec.h.

#define HDMI_CEC_RECORDING 0x01

Definition at line 106 of file stm32100e_eval_cec.h.

#define HDMI_CEC_REFUSED 0x04

Definition at line 167 of file stm32100e_eval_cec.h.

#define HDMI_CEC_ROOT 0x00

HDMI CEC Root (Mainly for TV with a fixed physical address (0.0.0.0)) If you want to configure the STM32100E-EVAL board as CEC Root (Sink) change the following define to 0x1.

Definition at line 144 of file stm32100e_eval_cec.h.

#define HDMI_CEC_TUNER 0x03

Definition at line 107 of file stm32100e_eval_cec.h.

#define HDMI_CEC_TV 0x00

CEC device types.

Definition at line 105 of file stm32100e_eval_cec.h.

#define HDMI_CEC_UNRECOGNIZED_OPCODE 0x00

Reason for Abort feature.

Definition at line 163 of file stm32100e_eval_cec.h.

#define HDMI_CEC_VERSION 0x04

To select if the DDC Channel will be used for physical address discovery or not.

To use the DDC Channel to read the EDID structure uncomment the following line. If the device is configured as HMDI source it should read his own physical address from the sink that is connected to. CEC version: V1.3a

Definition at line 158 of file stm32100e_eval_cec.h.


STM32F10x Standard Peripherals Firmware Library: STM32100E_EVAL_CEC_Exported_Macros

Defines

STM32100E_EVAL_CEC_Exported_Macros

STM32100E_EVAL_CEC

Defines

#define | HDMI_CEC_HPD_HIGH() GPIO_SetBits(HDMI_CEC_HPD_GPIO_PORT, HDMI_CEC_HPD_PIN)
#define | HDMI_CEC_HPD_LOW() GPIO_ResetBits(HDMI_CEC_HPD_GPIO_PORT, HDMI_CEC_HPD_PIN)

Define Documentation

#define HDMI_CEC_HPD_HIGH ( ) GPIO_SetBits(HDMI_CEC_HPD_GPIO_PORT, HDMI_CEC_HPD_PIN)

Definition at line 246 of file stm32100e_eval_cec.h.

#define HDMI_CEC_HPD_LOW ( ) GPIO_ResetBits(HDMI_CEC_HPD_GPIO_PORT, HDMI_CEC_HPD_PIN)

Definition at line 244 of file stm32100e_eval_cec.h.


STM32F10x Standard Peripherals Firmware Library: STM32100E_EVAL_CEC_Exported_Functions

Functions

STM32100E_EVAL_CEC_Exported_Functions

STM32100E_EVAL_CEC

Functions

HDMI_CEC_Error | HDMI_CEC_CheckConnectedDevices (void)
Check the connected CEC devices.
void | HDMI_CEC_CommandCallBack (void)
Handle CEC command receive callback.
HDMI_CEC_Error | HDMI_CEC_GetErrorStatus (void)
Get the ESR register status.
HDMI_CEC_Error | HDMI_CEC_Init (void)
Initializes the HDMI CEC.
void | HDMI_CEC_ProcessIRQSrc (void)
Allows to process all the interrupts that are high.
HDMI_CEC_Error | HDMI_CEC_ReportPhysicalAddress (void)
Report physical address to all other devices thus allowing any device to create a map of the network.
HDMI_CEC_Error HDMI_CEC_TransmitMessage (HDMI_CEC_Message *HDMI_CEC_TX_MessageStructure)
Transmit message by taking data from typedef struct CEC_Meassage.

Function Documentation

HDMI_CEC_Error HDMI_CEC_CheckConnectedDevices ( void )

Check the connected CEC devices.

Parameters:
None
Return values:
HDMI_CEC_Error

Definition at line 671 of file stm32100b_eval_cec.c.

References CEC_ClearFlag(), CEC_EndOfMessageCmd(), CEC_FLAG_TBTRF, CEC_FLAG_TERR, CEC_GetFlagStatus(), CEC_OwnAddressConfig(), CEC_SendDataByte(), CEC_StartOfMessage(), CECDevicesNumber, DISABLE, ENABLE, HDMI_CEC_Follower_String, HDMI_CEC_GetErrorStatus(), HDMI_CEC_OK, HDMI_CEC_TIMEOUT, HDMI_CEC_TIMEOUT_VALUE, MyLogicalAddress, and RESET.

Referenced by HDMI_CEC_Init().

void HDMI_CEC_CommandCallBack ( void )

Handle CEC command receive callback.

When receiving the STANDBY Opcode commande, the system is entred in Stop mode and when wakeup, the PLL is configured as system clock and the HSI is selected as PLL source.

Parameters:
None
Return values:
None

Definition at line 510 of file stm32100b_eval_cec.c.

References AbortReason, DeviceCount, HDMI_CEC_Map::DeviceType, DISABLE, ENABLE, EXTI_ClearITPendingBit(), EXTI_Init(), EXTI_InitStructure, EXTI_InitTypeDef::EXTI_Line, EXTI_Line8, EXTI_InitTypeDef::EXTI_LineCmd, EXTI_InitTypeDef::EXTI_Mode, EXTI_Mode_Interrupt, EXTI_InitTypeDef::EXTI_Trigger, EXTI_Trigger_Falling, FeatureOpcode, GPIO_EXTILineConfig(), GPIO_PinSource8, GPIO_PortSourceGPIOB, HDMI_CEC_Follower_String, HDMI_CEC_MapStruct, HDMI_CEC_OK, HDMI_CEC_OPCODE_CEC_VERSION, HDMI_CEC_OPCODE_FEATURE_ABORT, HDMI_CEC_OPCODE_GET_CEC_VERSION, HDMI_CEC_OPCODE_GIVE_OSD_NAME, HDMI_CEC_OPCODE_GIVE_PHYSICAL_ADDRESS, HDMI_CEC_OPCODE_REPORT_PHYSICAL_ADDRESS, HDMI_CEC_OPCODE_ROUTING_CHANGE, HDMI_CEC_OPCODE_SET_OSD_NAME, HDMI_CEC_OPCODE_STANDBY, HDMI_CEC_REFUSED, HDMI_CEC_ReportPhysicalAddress(), HDMI_CEC_TransmitMessage(), HDMI_CEC_VERSION, HDMI_CEC_Message::Header, HDMI_CEC_Map::LogicalAddress, MyLogicalAddress, HDMI_CEC_Message::Opcode, HDMI_CEC_Message::Operande, HDMI_CEC_Map::PhysicalAddress_A, HDMI_CEC_Map::PhysicalAddress_B, HDMI_CEC_Map::PhysicalAddress_C, HDMI_CEC_Map::PhysicalAddress_D, PWR_EnterSTOPMode(), PWR_Regulator_ON, PWR_STOPEntry_WFI, RCC_FLAG_PLLRDY, RCC_GetFlagStatus(), RCC_GetSYSCLKSource(), RCC_PLLCmd(), RCC_PLLConfig(), RCC_PLLMul_6, RCC_PLLSource_HSI_Div2, RCC_SYSCLKConfig(), RCC_SYSCLKSource_PLLCLK, RESET, and HDMI_CEC_Message::TxMessageLength.

HDMI_CEC_Error HDMI_CEC_GetErrorStatus ( void )

Get the ESR register status.

Parameters:
None
Return values:
HDMI_CEC_Error,: CEC Error code

Definition at line 343 of file stm32100b_eval_cec.c.

References CEC_ClearFlag(), CEC_FLAG_ACKE, CEC_FLAG_BPE, CEC_FLAG_BTE, CEC_FLAG_LINE, CEC_FLAG_RBTFE, CEC_FLAG_RERR, CEC_FLAG_SBE, CEC_FLAG_TBTFE, CEC_FLAG_TERR, CEC_GetFlagStatus(), HDMI_CEC_BIT_PERIOD, HDMI_CEC_BIT_TIMING, HDMI_CEC_BLOCK_ACKNOWLEDGE, HDMI_CEC_LINE, HDMI_CEC_OK, HDMI_CEC_RX_BLOCK_FINISHED, HDMI_CEC_START_BIT, HDMI_CEC_TX_BLOCK_FINISHED, and RESET.

Referenced by HDMI_CEC_CheckConnectedDevices(), HDMI_CEC_ProcessIRQSrc(), and LogicalAddressAllocation().

HDMI_CEC_Error HDMI_CEC_Init ( void )

Initializes the HDMI CEC.

Parameters:
None
Return values:
HDMI_CEC_Error,: CEC Error code

Definition at line 143 of file stm32100b_eval_cec.c.

References CEC_InitTypeDef::CEC_BitPeriodMode, CEC_BitPeriodStdMode, CEC_InitTypeDef::CEC_BitTimingMode, CEC_BitTimingStdMode, CEC_Cmd(), CEC_DeInit(), CEC_Init(), CEC_InitStructure, CEC_ITConfig(), CEC_OwnAddressConfig(), CEC_SetPrescaler(), ENABLE, GPIO_Init(), GPIO_InitStructure, GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_AF_OD, GPIO_Mode_IPD, GPIO_InitTypeDef::GPIO_Pin, GPIO_InitTypeDef::GPIO_Speed, GPIO_Speed_50MHz, HDMI_CEC_CheckConnectedDevices(), HDMI_CEC_HPD_GPIO_CLK, HDMI_CEC_HPD_GPIO_PORT, HDMI_CEC_HPD_PIN, HDMI_CEC_I2C, HDMI_CEC_I2C_CLK, HDMI_CEC_I2C_CLOCK_SPEED, HDMI_CEC_I2C_GPIO_CLK, HDMI_CEC_I2C_GPIO_PORT, HDMI_CEC_I2C_SCL_PIN, HDMI_CEC_I2C_SDA_PIN, HDMI_CEC_I2C_SLAVE_ADDRESS7, HDMI_CEC_LINE_GPIO_CLK, HDMI_CEC_LINE_GPIO_PORT, HDMI_CEC_LINE_PIN, HDMI_CEC_OK, HDMI_CEC_ReportPhysicalAddress(), I2C_InitTypeDef::I2C_Ack, I2C_Ack_Enable, I2C_InitTypeDef::I2C_AcknowledgedAddress, I2C_AcknowledgedAddress_7bit, I2C_InitTypeDef::I2C_ClockSpeed, I2C_Cmd(), I2C_InitTypeDef::I2C_DutyCycle, I2C_DutyCycle_2, I2C_Init(), I2C_InitStructure, I2C_InitTypeDef::I2C_Mode, I2C_Mode_I2C, I2C_InitTypeDef::I2C_OwnAddress1, LogicalAddressAllocation(), MyLogicalAddress, PhysicalAddressDiscovery(), RCC_APB1Periph_CEC, RCC_APB1PeriphClockCmd(), and RCC_APB2PeriphClockCmd().

void HDMI_CEC_ProcessIRQSrc ( void )

Allows to process all the interrupts that are high.

Parameters:
None
Return values:
None

Definition at line 393 of file stm32100b_eval_cec.c.

References BufferPointer, CEC_ClearFlag(), CEC_EndOfMessageCmd(), CEC_FLAG_RBTF, CEC_FLAG_REOM, CEC_FLAG_RERR, CEC_FLAG_RSOM, CEC_FLAG_TBTRF, CEC_FLAG_TEOM, CEC_FLAG_TERR, CEC_GetFlagStatus(), CEC_ReceiveDataByte(), CEC_SendDataByte(), DISABLE, ENABLE, HDMI_CEC_GetErrorStatus(), HDMI_CEC_Message::Header, HDMI_CEC_Message::Opcode, HDMI_CEC_Message::Operande, ReceivedFrame, ReceiveStatus, RecepErrorCode, RxCounter, HDMI_CEC_Message::RxMessageLength, SendFrame, SendStatus, SUCCESS, TransErrorCode, TxCounter, and HDMI_CEC_Message::TxMessageLength.

HDMI_CEC_Error HDMI_CEC_ReportPhysicalAddress ( void )

Report physical address to all other devices thus allowing any device to create a map of the network.

Parameters:
None
Return values:
HDMI_CEC_Error,: CEC Error code.

Definition at line 485 of file stm32100b_eval_cec.c.

References DeviceType, HDMI_CEC_OK, HDMI_CEC_OPCODE_REPORT_PHYSICAL_ADDRESS, HDMI_CEC_TransmitMessage(), HDMI_CEC_Message::Header, MyLogicalAddress, MyPhysicalAddress, HDMI_CEC_Message::Opcode, HDMI_CEC_Message::Operande, and HDMI_CEC_Message::TxMessageLength.

Referenced by HDMI_CEC_CommandCallBack(), and HDMI_CEC_Init().

HDMI_CEC_Error HDMI_CEC_TransmitMessage ( HDMI_CEC_Message * HDMI_CEC_TX_MessageStructure )

Transmit message by taking data from typedef struct CEC_Meassage.

Parameters:
CEC_TX_MessageStructure,: pointer to an CEC_Message structure that contains the message to be sent.
Return values:
HDMI_CEC_Error,: CEC Error code

Definition at line 286 of file stm32100b_eval_cec.c.

References BufferCount, BufferPointer, CEC_ClearFlag(), CEC_FLAG_TBTRF, CEC_FLAG_TERR, CEC_SendDataByte(), CEC_StartOfMessage(), HDMI_CEC_OK, HDMI_CEC_TIMEOUT, HDMI_CEC_TIMEOUT_VALUE, HDMI_CEC_TX_MessageStructure, HDMI_CEC_Message::Header, j, HDMI_CEC_Message::Opcode, HDMI_CEC_Message::Operande, SendFrame, SendStatus, TransErrorCode, TxCounter, and HDMI_CEC_Message::TxMessageLength.

Referenced by HDMI_CEC_CommandCallBack(), and HDMI_CEC_ReportPhysicalAddress().


STM32F10x Standard Peripherals Firmware Library: STM32100E_EVAL_IOE_Private_TypesDefinitions

STM32100E_EVAL_IOE_Private_TypesDefinitions

STM32100E_EVAL_IOE


STM32F10x Standard Peripherals Firmware Library: STM32100E_EVAL_IOE_Private_Defines

Defines

STM32100E_EVAL_IOE_Private_Defines

STM32100E_EVAL_IOE

Defines

#define TIMEOUT_MAX 0x1000

Define Documentation

#define TIMEOUT_MAX 0x1000

Definition at line 72 of file stm32100e_eval_ioe.c.

Referenced by I2C_ReadDataBuffer(), I2C_ReadDeviceRegister(), and I2C_WriteDeviceRegister().


STM32F10x Standard Peripherals Firmware Library: STM32100E_EVAL_IOE_Private_Macros

STM32100E_EVAL_IOE_Private_Macros

STM32100E_EVAL_IOE


STM32F10x Standard Peripherals Firmware Library: STM32100E_EVAL_IOE_Private_Variables

Variables

STM32100E_EVAL_IOE_Private_Variables

STM32100E_EVAL_IOE

Variables

uint32_t IOE_TimeOut = TIMEOUT_MAX
TS_STATE TS_State

Variable Documentation

uint32_t IOE_TimeOut = TIMEOUT_MAX

Definition at line 91 of file stm32100e_eval_ioe.c.

Referenced by I2C_ReadDataBuffer(), I2C_ReadDeviceRegister(), I2C_WriteDeviceRegister(), and IOE_IsOperational().

TS_STATE TS_State

Definition at line 89 of file stm32100e_eval_ioe.c.

Referenced by EXTI15_10_IRQHandler(), IOE_TS_GetState(), and main().


STM32F10x Standard Peripherals Firmware Library: STM32100E_EVAL_IOE_Private_FunctionPrototypes

STM32100E_EVAL_IOE_Private_FunctionPrototypes

STM32100E_EVAL_IOE


STM32F10x Standard Peripherals Firmware Library: STM32100E_EVAL_IOE_Private_Functions

Functions

STM32100E_EVAL_IOE_Private_Functions

STM32100E_EVAL_IOE

Functions

static void | delay (__IO uint32_t nCount)
Inserts a delay time.
uint16_t | I2C_ReadDataBuffer (uint8_t DeviceAddr, uint32_t RegisterAddr)
Reads a buffer of 2 bytes from the device registers.
uint8_t | I2C_ReadDeviceRegister (uint8_t DeviceAddr, uint8_t RegisterAddr)
Reads a register of the device through I2C.
uint8_t | I2C_WriteDeviceRegister (uint8_t DeviceAddr, uint8_t RegisterAddr, uint8_t RegisterValue)
Writes a value in a register of the device through I2C.
uint8_t | IOE_ClearGITPending (uint8_t DeviceAddr, uint8_t Global_IT)
Clears the selected Global interrupt pending bit(s)
uint8_t | IOE_ClearIOITPending (uint8_t DeviceAddr, uint8_t IO_IT)
Clears the selected IO interrupt pending bit(s).
uint8_t | IOE_Config (void)
Initializes and Configures the IO_Expanders Functionalities (Touch Screen ..) and configures all STM32100E-EVAL necessary hardware (GPIOs, APB clocks ..).
static void | IOE_DMA_Config (IOE_DMADirection_TypeDef Direction, uint8_t *buffer)
Configure the DMA Peripheral used to handle communication via I2C.
static void | IOE_EXTI_Config (void)
Configures the IO expander Interrupt line and GPIO in EXTI mode.
uint8_t | IOE_FnctCmd (uint8_t DeviceAddr, uint8_t Fct, FunctionalState NewState)
Configures the selcted IO Expander functionalities.
FlagStatus | IOE_GetGITStatus (uint8_t DeviceAddr, uint8_t Global_IT)
Checks the selected Global interrupt source pending bit.
FlagStatus | IOE_GetIOITStatus (uint8_t DeviceAddr, uint8_t IO_IT)
Checks the status of the selected IO interrupt pending bit.
uint8_t | IOE_GITCmd (uint8_t DeviceAddr, FunctionalState NewState)
Enables or disables the Global interrupt.
uint8_t | IOE_GITConfig (uint8_t DeviceAddr, uint8_t Global_IT, FunctionalState NewState)
Configures the selected source to generate or not a global interrupt.
static void | IOE_GPIO_Config (void)
Initializes the GPIO pins used by the IO expander.
static void | IOE_I2C_Config (void)
Configure the I2C Peripheral used to communicate with IO_Expanders.
uint8_t | IOE_IOAFConfig (uint8_t DeviceAddr, uint8_t IO_Pin, FunctionalState NewState)
Configures the selected pin to be in Alternate function or not.
uint8_t | IOE_IOEdgeConfig (uint8_t DeviceAddr, uint8_t IO_Pin, uint8_t Edge)
Configures the Edge for which a transition is detectable for the the selected pin.
uint8_t | IOE_IOITConfig (uint8_t DeviceAddr, uint8_t IO_IT, FunctionalState NewState)
Configures the selected pins to generate an interrupt or not.
uint8_t | IOE_IOPinConfig (uint8_t DeviceAddr, uint8_t IO_Pin, uint8_t Direction)
Configures the selected pin direction (to be an input or an output)
uint8_t | IOE_IsOperational (uint8_t DeviceAddr)
Checks if the selected device is correctly configured and communicates correctly ont the I2C bus.
uint8_t | IOE_ITConfig (uint32_t IOE_ITSRC_Source)
Configures The selected interrupts on the IO Expanders.
uint8_t | IOE_ITOutConfig (uint8_t Polarity, uint8_t Type)
Configures the Interrupt line active state and format (level/edge)
uint16_t | IOE_ReadID (uint8_t DeviceAddr)
Reads the selected device's ID.
uint8_t | IOE_ReadIOPin (uint32_t IO_Pin)
Returns the status of the selected input IO pin.
uint8_t | IOE_Reset (uint8_t DeviceAddr)
Resets the IO Expander by Software (SYS_CTRL1, RESET bit).
uint8_t | IOE_TempSens_Config (void)
Configures and enables the Temperature sensor module.
uint32_t | IOE_TempSens_GetData (void)
Returns the temperature row value (in 16 bit format).
uint8_t | IOE_TS_Config (void)
Configures the touch Screen Controller (Single point detection)
TS_STATE * | IOE_TS_GetState (void)
Returns Status and positions of the Touch screen.
static uint16_t | IOE_TS_Read_X (void)
Return Touch Screen X position value.
static uint16_t | IOE_TS_Read_Y (void)
Return Touch Screen Y position value.
static uint16_t | IOE_TS_Read_Z (void)
Return Touch Screen Z position value.
uint8_t | IOE_WriteIOPin (uint8_t IO_Pin, IOE_BitValue_TypeDef BitVal)
Writes a bit value to an output IO pin.

Function Documentation

static void delay ( __IO uint32_t nCount ) [static]

Inserts a delay time.

Parameters:
nCount,: specifies the delay time length.
Return values:
None

Definition at line 1377 of file stm32100e_eval_ioe.c.

References index.

uint16_t I2C_ReadDataBuffer | ( | uint8_t | DeviceAddr,
 |  | uint32_t | RegisterAddr
 | ) |  |

Reads a buffer of 2 bytes from the device registers.

Parameters:
DeviceAddr,: The address of the device, could be : IOE_1_ADDR.
RegisterAddr,: The target register adress (between 00x and 0x24)
Return values:
A pointer to the buffer containing the two returned bytes (in halfword).

Definition at line 1061 of file stm32100e_eval_ioe.c.

Referenced by IOE_TS_Read_X(), IOE_TS_Read_Y(), and IOE_TS_Read_Z().

uint8_t I2C_ReadDeviceRegister | ( | uint8_t | DeviceAddr,
 |  | uint8_t | RegisterAddr
 | ) |  |

Reads a register of the device through I2C.

Parameters:
DeviceAddr,: The address of the device, could be : IOE_1_ADDR.
RegisterAddr,: The target register adress (between 00x and 0x24)
Return values:
The value of the read register (0xAA if Timout occured)

Definition at line 965 of file stm32100e_eval_ioe.c.

Referenced by I2C_WriteDeviceRegister(), IOE_FnctCmd(), IOE_GetGITStatus(), IOE_GetIOITStatus(), IOE_GITCmd(), IOE_GITConfig(), IOE_IOAFConfig(), IOE_IOEdgeConfig(), IOE_IOITConfig(), IOE_IOPinConfig(), IOE_ITConfig(), IOE_ITOutConfig(), IOE_JoyStickGetState(), IOE_ReadID(), IOE_ReadIOPin(), IOE_TempSens_Config(), IOE_TempSens_GetData(), IOE_TS_Config(), and IOE_TS_GetState().

uint8_t I2C_WriteDeviceRegister | ( | uint8_t | DeviceAddr,
 |  | uint8_t | RegisterAddr,
 |  | uint8_t | RegisterValue
 | ) |  |

Writes a value in a register of the device through I2C.

Parameters:
DeviceAddr,: The address of the IOExpander, could be : IOE_1_ADDR.
RegisterAddr,: The target register adress
RegisterValue,: The target register value to be written
Return values:
IOE_OK,: if all operations are OK. Other value if error.

Definition at line 865 of file stm32100e_eval_ioe.c.

Referenced by IOE_ClearGITPending(), IOE_ClearIOITPending(), IOE_FnctCmd(), IOE_GITCmd(), IOE_GITConfig(), IOE_IOAFConfig(), IOE_IOEdgeConfig(), IOE_IOITConfig(), IOE_IOPinConfig(), IOE_ITOutConfig(), IOE_Reset(), IOE_TempSens_Config(), IOE_TempSens_GetData(), IOE_TS_Config(), IOE_TS_GetState(), and IOE_WriteIOPin().

uint8_t IOE_ClearGITPending | ( | uint8_t | DeviceAddr,
 |  | uint8_t | Global_IT
 | ) |  |

Clears the selected Global interrupt pending bit(s)

Parameters:
DeviceAddr,: The address of the IOExpander, could be : IOE_1_ADDR.
Global_IT,: the Global interrupt to be cleared, could be any combination of the following values:

  • Global_IT_GPIO : All IOs interrupt
  • Global_IT_ADC : ADC interrupt
  • Global_IT_TEMP : Temperature Sensor interrupts
  • Global_IT_FE : Touch Screen Controller FIFO Error interrupt
  • Global_IT_FF : Touch Screen Controller FIFO Full interrupt
  • Global_IT_FOV : Touch Screen Controller FIFO Overrun interrupt
  • Global_IT_FTH : Touch Screen Controller FIFO Threshold interrupt
  • Global_IT_TOUCH : Touch Screen Controller Touch Detected interrupt
Return values:
IOE_OK,: if all initializations are OK. Other value if error.

Definition at line 374 of file stm32100e_eval_ioe.c.

Referenced by EXTI15_10_IRQHandler().

uint8_t IOE_ClearIOITPending | ( | uint8_t | DeviceAddr,
 |  | uint8_t | IO_IT
 | ) |  |

Clears the selected IO interrupt pending bit(s).

Parameters:
DeviceAddr,: The address of the IOExpander, could be : IOE_1_ADDR.
IO_IT,: the IO interrupt to be checked could be IO_ITx Where x can be from 0 to 7.
Return values:
IOE_OK,: if all initializations are OK. Other value if error.

Definition at line 414 of file stm32100e_eval_ioe.c.

Referenced by EXTI15_10_IRQHandler().

uint8_t IOE_Config ( void )

Initializes and Configures the IO_Expanders Functionalities (Touch Screen ..) and configures all STM32100E-EVAL necessary hardware (GPIOs, APB clocks ..).

Configuration and initialization functions.

Parameters:
None
Return values:
IOE_OK if all initializations done correctly. Other value if error.

Definition at line 129 of file stm32100e_eval_ioe.c.

Referenced by main().

static void IOE_DMA_Config | ( | IOE_DMADirection_TypeDef | Direction,
 |  | uint8_t * | buffer
 | ) |  | [static]

Configure the DMA Peripheral used to handle communication via I2C.

Parameters:
None
Return values:
None

Definition at line 1281 of file stm32100e_eval_ioe.c.

References DMA_InitTypeDef::DMA_BufferSize, DMA_DeInit(), DMA_InitTypeDef::DMA_DIR, DMA_DIR_PeripheralDST, DMA_DIR_PeripheralSRC, DMA_Init(), DMA_InitStructure, DMA_InitTypeDef::DMA_M2M, DMA_M2M_Disable, DMA_InitTypeDef::DMA_MemoryBaseAddr, DMA_InitTypeDef::DMA_MemoryDataSize, DMA_MemoryDataSize_Byte, DMA_InitTypeDef::DMA_MemoryInc, DMA_MemoryInc_Enable, DMA_InitTypeDef::DMA_Mode, DMA_Mode_Normal, DMA_InitTypeDef::DMA_PeripheralBaseAddr, DMA_InitTypeDef::DMA_PeripheralDataSize, DMA_PeripheralDataSize_Byte, DMA_InitTypeDef::DMA_PeripheralInc, DMA_PeripheralInc_Disable, DMA_InitTypeDef::DMA_Priority, DMA_Priority_VeryHigh, ENABLE, IOE_DMA_CLK, IOE_DMA_RX, IOE_DMA_RX_CHANNEL, IOE_DMA_TX, IOE_DMA_TX_CHANNEL, IOE_I2C_DR, and RCC_AHBPeriphClockCmd().

Referenced by I2C_ReadDataBuffer(), I2C_ReadDeviceRegister(), and I2C_WriteDeviceRegister().

static void IOE_EXTI_Config ( void ) [static]

Configures the IO expander Interrupt line and GPIO in EXTI mode.

Parameters:
None
Return values:
None

Definition at line 1339 of file stm32100e_eval_ioe.c.

References ENABLE, EXTI_Init(), EXTI_InitStructure, EXTI_InitTypeDef::EXTI_Line, EXTI_InitTypeDef::EXTI_LineCmd, EXTI_InitTypeDef::EXTI_Mode, EXTI_Mode_Interrupt, EXTI_InitTypeDef::EXTI_Trigger, EXTI_Trigger_Rising_Falling, GPIO_EXTILineConfig(), GPIO_Init(), GPIO_InitStructure, GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_IN_FLOATING, GPIO_InitTypeDef::GPIO_Pin, IOE_IT_EXTI_IRQn, IOE_IT_EXTI_LINE, IOE_IT_EXTI_PIN_SOURCE, IOE_IT_EXTI_PORT_SOURCE, IOE_IT_GPIO_CLK, IOE_IT_GPIO_PORT, IOE_IT_PIN, NVIC_Init(), NVIC_InitStructure, NVIC_InitTypeDef::NVIC_IRQChannel, NVIC_InitTypeDef::NVIC_IRQChannelCmd, NVIC_InitTypeDef::NVIC_IRQChannelPreemptionPriority, NVIC_InitTypeDef::NVIC_IRQChannelSubPriority, RCC_APB2Periph_AFIO, and RCC_APB2PeriphClockCmd().

Referenced by IOE_ITConfig().

uint8_t IOE_FnctCmd | ( | uint8_t | DeviceAddr,
 |  | uint8_t | Fct,
 |  | FunctionalState | NewState
 | ) |  |

Configures the selcted IO Expander functionalities.

Parameters:
DeviceAddr,: The address of the IOExpander, could be : IOE_1_ADDR.
Fct,: the functions to be configured. could be any combination of the following values:

  • IOE_IO_FCT : IO function
  • IOE_TS_FCT : Touch Screen function
  • IOE_ADC_FCT : ADC function
  • IOE_TEMPSENS_FCT : Tempreature Sensor function
Return values:
IOE_OK,: if all initializations are OK. Other value if error.

Definition at line 507 of file stm32100e_eval_ioe.c.

Referenced by IOE_Config().

FlagStatus IOE_GetGITStatus | ( | uint8_t | DeviceAddr,
 |  | uint8_t | Global_IT
 | ) |  |

Checks the selected Global interrupt source pending bit.

Interrupts Mangement functions.

Parameters:
DeviceAddr,: The address of the IOExpander, could be : IOE_1_ADDR.
Global_IT,: the Global interrupt source to be checked, could be:

  • Global_IT_GPIO : All IOs interrupt
  • Global_IT_ADC : ADC interrupt
  • Global_IT_TEMP : Temperature Sensor interrupts
  • Global_IT_FE : Touch Screen Controller FIFO Error interrupt
  • Global_IT_FF : Touch Screen Controller FIFO Full interrupt
  • Global_IT_FOV : Touch Screen Controller FIFO Overrun interrupt
  • Global_IT_FTH : Touch Screen Controller FIFO Threshold interrupt
  • Global_IT_TOUCH : Touch Screen Controller Touch Detected interrupt
Return values:
Status of the checked flag. Could be SET or RESET.

Definition at line 342 of file stm32100e_eval_ioe.c.

Referenced by EXTI15_10_IRQHandler().

FlagStatus IOE_GetIOITStatus | ( | uint8_t | DeviceAddr,
 |  | uint8_t | IO_IT
 | ) |  |

Checks the status of the selected IO interrupt pending bit.

Parameters:
DeviceAddr,: The address of the IOExpander, could be : IOE_1_ADDR.
IO_IT,: the IO interrupt to be checked could be IO_ITx Where x can be from 0 to 7.
Return values:
Status of the checked flag. Could be SET or RESET.

Definition at line 390 of file stm32100e_eval_ioe.c.

uint8_t IOE_GITCmd | ( | uint8_t | DeviceAddr,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the Global interrupt.

Parameters:
DeviceAddr,: The address of the IOExpander, could be :I OE_1_ADDR.
NewState,: could be ENABLE or DISABLE.
Return values:
IOE_OK,: if all initializations are OK. Other value if error.

Definition at line 568 of file stm32100e_eval_ioe.c.

Referenced by IOE_ITConfig().

uint8_t IOE_GITConfig | ( | uint8_t | DeviceAddr,
 |  | uint8_t | Global_IT,
 |  | FunctionalState | NewState
 | ) |  |

Configures the selected source to generate or not a global interrupt.

Parameters:
DeviceAddr,: The address of the IOExpander, could be : IOE_1_ADDR
Global_IT,: the interrupt source to be configured, could be:

  • Global_IT_GPIO : All IOs interrupt
  • Global_IT_ADC : ADC interrupt
  • Global_IT_TEMP : Temperature Sensor interrupts
  • Global_IT_FE : Touch Screen Controller FIFO Error interrupt
  • Global_IT_FF : Touch Screen Controller FIFO Full interrupt
  • Global_IT_FOV : Touch Screen Controller FIFO Overrun interrupt
  • Global_IT_FTH : Touch Screen Controller FIFO Threshold interrupt
  • Global_IT_TOUCH : Touch Screen Controller Touch Detected interrupt
Return values:
IOE_OK,: if all initializations are OK. Other value if error.

Definition at line 607 of file stm32100e_eval_ioe.c.

Referenced by IOE_ITConfig().

static void IOE_GPIO_Config ( void ) [static]

Initializes the GPIO pins used by the IO expander.

Parameters:
None
Return values:
None

Definition at line 1219 of file stm32100e_eval_ioe.c.

References DISABLE, ENABLE, GPIO_EXTILineConfig(), GPIO_Init(), GPIO_InitStructure, GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_AF_OD, GPIO_Mode_IPU, GPIO_InitTypeDef::GPIO_Pin, GPIO_InitTypeDef::GPIO_Speed, GPIO_Speed_10MHz, IOE_I2C_CLK, IOE_I2C_SCL_GPIO_CLK, IOE_I2C_SCL_GPIO_PORT, IOE_I2C_SCL_PIN, IOE_I2C_SDA_GPIO_CLK, IOE_I2C_SDA_GPIO_PORT, IOE_I2C_SDA_PIN, IOE_IT_EXTI_PIN_SOURCE, IOE_IT_EXTI_PORT_SOURCE, IOE_IT_GPIO_CLK, IOE_IT_GPIO_PORT, IOE_IT_PIN, RCC_APB1PeriphClockCmd(), RCC_APB1PeriphResetCmd(), RCC_APB2Periph_AFIO, and RCC_APB2PeriphClockCmd().

Referenced by IOE_Config().

static void IOE_I2C_Config ( void ) [static]

Configure the I2C Peripheral used to communicate with IO_Expanders.

Parameters:
None
Return values:
None

Definition at line 1259 of file stm32100e_eval_ioe.c.

References I2C_InitTypeDef::I2C_Ack, I2C_Ack_Enable, I2C_InitTypeDef::I2C_AcknowledgedAddress, I2C_AcknowledgedAddress_7bit, I2C_InitTypeDef::I2C_ClockSpeed, I2C_InitTypeDef::I2C_DutyCycle, I2C_DutyCycle_2, I2C_Init(), I2C_InitStructure, I2C_InitTypeDef::I2C_Mode, I2C_Mode_I2C, I2C_InitTypeDef::I2C_OwnAddress1, IOE_I2C, and IOE_I2C_SPEED.

Referenced by IOE_Config().

uint8_t IOE_IOAFConfig | ( | uint8_t | DeviceAddr,
 |  | uint8_t | IO_Pin,
 |  | FunctionalState | NewState
 | ) |  |

Configures the selected pin to be in Alternate function or not.

Parameters:
DeviceAddr,: The address of the IOExpander, could be : IOE_1_ADDR.
IO_Pin,: IO_Pin_x, Where x can be from 0 to 7.
NewState,: State of the AF for the selected pin, could be ENABLE or DISABLE.
Return values:
IOE_OK,: if all initializations are OK. Other value if error.

Definition at line 761 of file stm32100e_eval_ioe.c.

Referenced by IOE_Config().

uint8_t IOE_IOEdgeConfig | ( | uint8_t | DeviceAddr,
 |  | uint8_t | IO_Pin,
 |  | uint8_t | Edge
 | ) |  |

Configures the Edge for which a transition is detectable for the the selected pin.

Parameters:
DeviceAddr,: The address of the IOExpander, could be : IOE_1_ADDR.
IO_Pin,: IO_Pin_x, Where x can be from 0 to 7.
Edge,: The edge which will be detected. This parameter can be one or a a combination of follwing values: EDGE_FALLING and EDGE_RISING .
Return values:
IOE_OK,: if all initializations are OK. Other value if error.

Definition at line 795 of file stm32100e_eval_ioe.c.

Referenced by IOE_Config().

uint8_t IOE_IOITConfig | ( | uint8_t | DeviceAddr,
 |  | uint8_t | IO_IT,
 |  | FunctionalState | NewState
 | ) |  |

Configures the selected pins to generate an interrupt or not.

Parameters:
DeviceAddr,: The address of the IOExpander, could be : IOE_1_ADDR.
IO_IT,: The IO interrupt to be configured. This parameter could be any combination of the following values:

  • IO_IT_x: where x can be from 0 to 7.
NewState,: could be ENABLE or DISABLE.
Return values:
IOE_OK,: if all initializations are OK. Other value if error.

Definition at line 640 of file stm32100e_eval_ioe.c.

Referenced by IOE_ITConfig().

uint8_t IOE_IOPinConfig | ( | uint8_t | DeviceAddr,
 |  | uint8_t | IO_Pin,
 |  | uint8_t | Direction
 | ) |  |

Configures the selected pin direction (to be an input or an output)

Parameters:
DeviceAddr,: The address of the IOExpander, could be : IOE_1_ADDR.
IO_Pin,: IO_Pin_x: Where x can be from 0 to 7.
Direction,: could be Direction_IN or Direction_OUT.
Return values:
IOE_OK,: if all initializations are OK. Other value if error.

Definition at line 539 of file stm32100e_eval_ioe.c.

Referenced by IOE_Config().

uint8_t IOE_IsOperational ( uint8_t DeviceAddr )

Checks if the selected device is correctly configured and communicates correctly ont the I2C bus.

IO-Expander Control functions.

Parameters:
DeviceAddr,: The address of the IOExpander, could be : IOE_1_ADDR.
Return values:
IOE_OK if IOE is operational. Other value if failure.

Definition at line 437 of file stm32100e_eval_ioe.c.

Referenced by IOE_Config().

uint8_t IOE_ITConfig ( uint32_t IOE_ITSRC_Source )

Configures The selected interrupts on the IO Expanders.

Parameters:
IOE_ITSRC_Source,: the source of the interrupts. Could be one or a combination of the following parameters:

  • IOE_ITSRC_TSC: Touch Screen interrupts.
Return values:
IOE_OK,: if all initializations are OK. Other value if error.

Definition at line 169 of file stm32100e_eval_ioe.c.

Referenced by main().

uint8_t IOE_ITOutConfig | ( | uint8_t | Polarity,
 |  | uint8_t | Type
 | ) |  |

Configures the Interrupt line active state and format (level/edge)

Parameters:
Polarity,: could be

  • Polarity_Low: Interrupt line is active Low/Falling edge
  • Polarity_High: Interrupt line is active High/Rising edge
Type,: Interrupt line activity type, could be one of the following values

  • Type_Level: Interrupt line is active in level model
  • Type_Edge: Interrupt line is active in edge model
Return values:
IOE_OK,: if all initializations are OK. Other value if error.

Definition at line 838 of file stm32100e_eval_ioe.c.

Referenced by IOE_ITConfig().

uint16_t IOE_ReadID ( uint8_t DeviceAddr )

Reads the selected device's ID.

Parameters:
DeviceAddr,: The address of the IOExpander, could be : IOE_1_ADDR.
Return values:
The Device ID (two bytes).

Definition at line 483 of file stm32100e_eval_ioe.c.

Referenced by IOE_IsOperational().

uint8_t IOE_ReadIOPin ( uint32_t IO_Pin )

Returns the status of the selected input IO pin.

Parameters:
IO_Pin,: The input pin to be read. IO_Pin_x: Where x can be from 0 to 7.

  • JOY_IO_PINS: Joystick IO pins (use IOE_JoyStickGetState for these pins)
Return values:
None

Definition at line 239 of file stm32100e_eval_ioe.c.

uint8_t IOE_Reset ( uint8_t DeviceAddr )

Resets the IO Expander by Software (SYS_CTRL1, RESET bit).

Parameters:
DeviceAddr,: The address of the IOExpander, could be : IOE_1_ADDR.
Return values:
IOE_OK,: if all initializations are OK. Other value if error.

Definition at line 463 of file stm32100e_eval_ioe.c.

Referenced by IOE_Config().

uint8_t IOE_TempSens_Config ( void )

Configures and enables the Temperature sensor module.

Parameters:
None
Return values:
IOE_OK if all initializations are OK. Other value if error.

Definition at line 734 of file stm32100e_eval_ioe.c.

Referenced by IOE_Config().

uint32_t IOE_TempSens_GetData ( void )

Returns the temperature row value (in 16 bit format).

Temperature Sensor functions.

Parameters:
None
Return values:
The temperature row value.

Definition at line 310 of file stm32100e_eval_ioe.c.

uint8_t IOE_TS_Config ( void )

Configures the touch Screen Controller (Single point detection)

Low Layer functions.

Parameters:
None
Return values:
IOE_OK if all initializations are OK. Other value if error.

Definition at line 669 of file stm32100e_eval_ioe.c.

Referenced by IOE_Config().

TS_STATE* IOE_TS_GetState ( void )

Returns Status and positions of the Touch screen.

Touch Screen controller functions.

Parameters:
None
Return values:
Pointer to TS_STATE structure holding Touch Screen information.

Definition at line 270 of file stm32100e_eval_ioe.c.

Referenced by EXTI15_10_IRQHandler(), and main().

static uint16_t IOE_TS_Read_X ( void ) [static]

Return Touch Screen X position value.

Parameters:
None
Return values:
X position.

Definition at line 1161 of file stm32100e_eval_ioe.c.

References I2C_ReadDataBuffer(), IOE_1_ADDR, and IOE_REG_TSC_DATA_Y.

Referenced by IOE_TS_GetState().

static uint16_t IOE_TS_Read_Y ( void ) [static]

Return Touch Screen Y position value.

Parameters:
None
Return values:
Y position.

Definition at line 1183 of file stm32100e_eval_ioe.c.

References I2C_ReadDataBuffer(), IOE_1_ADDR, and IOE_REG_TSC_DATA_X.

Referenced by IOE_TS_GetState().

static uint16_t IOE_TS_Read_Z ( void ) [static]

Return Touch Screen Z position value.

Parameters:
None
Return values:
Z position.

Definition at line 1202 of file stm32100e_eval_ioe.c.

References I2C_ReadDataBuffer(), IOE_1_ADDR, and IOE_REG_TSC_DATA_Z.

Referenced by IOE_TS_GetState().

uint8_t IOE_WriteIOPin | ( | uint8_t | IO_Pin,
 |  | IOE_BitValue_TypeDef | BitVal
 | ) |  |

Writes a bit value to an output IO pin.

IO pins control functions.

Parameters:
IO_Pin,: The output pin to be set or reset. IO_Pin_x: Where x can be from 0 to 7.
BitVal,: The value to be set. This parameter can be one of the following values: BitSet or BitReset. See IOE_BitVal_TypeDef.
Return values:
IOE_OK or PARAM_ERROR

Definition at line 202 of file stm32100e_eval_ioe.c.

Referenced by IOE_Config().


STM32F10x Standard Peripherals Firmware Library: STM32100E_EVAL_IOE_Exported_Types

Data Structures | Enumerations

STM32100E_EVAL_IOE_Exported_Types

STM32100E_EVAL_IOE

Data Structures

struct | TS_STATE
Touch Screen Information structure. More...

Enumerations

enum | IOE_BitValue_TypeDef { BitReset = 0, BitSet = 1, BitReset = 0, BitSet = 1 }

IO bit values.

More...
enum | IOE_DMADirection_TypeDef { IOE_DMA_TX = 0, IOE_DMA_RX = 1, IOE_DMA_TX = 0, IOE_DMA_RX = 1 }

IOE DMA Direction.

More...
enum IOE_Status_TypDef {
IOE_OK = 0, IOE_FAILURE, IOE_TIMEOUT, PARAM_ERROR,
IOE1_NOT_OPERATIONAL, IOE_OK = 0, IOE_FAILURE, IOE_TIMEOUT,
PARAM_ERROR, IOE1_NOT_OPERATIONAL, IOE2_NOT_OPERATIONAL
}

IO_Expander Error codes.

More...

Enumeration Type Documentation

enum IOE_BitValue_TypeDef

IO bit values.

Enumerator:
BitReset
BitSet
BitReset
BitSet

Definition at line 93 of file stm32100e_eval_ioe.h.

enum IOE_DMADirection_TypeDef

IOE DMA Direction.

Enumerator:
IOE_DMA_TX
IOE_DMA_RX
IOE_DMA_TX
IOE_DMA_RX

Definition at line 102 of file stm32100e_eval_ioe.h.

enum IOE_Status_TypDef

IO_Expander Error codes.

Enumerator:
IOE_OK
IOE_FAILURE
IOE_TIMEOUT
PARAM_ERROR
IOE1_NOT_OPERATIONAL
IOE_OK
IOE_FAILURE
IOE_TIMEOUT
PARAM_ERROR
IOE1_NOT_OPERATIONAL
IOE2_NOT_OPERATIONAL

Definition at line 81 of file stm32100e_eval_ioe.h.


STM32F10x Standard Peripherals Firmware Library: TS_STATE Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

TS_STATE Struct Reference
STM32100E_EVAL_IOE_Exported_Types | STM3210C_EVAL_IOE_Exported_Types

Touch Screen Information structure. More...

#include <stm32100e_eval_ioe.h>

Data Fields

uint16_t | TouchDetected
uint16_t | X
uint16_t | Y
uint16_t | Z

Detailed Description

Touch Screen Information structure.

Definition at line 69 of file stm32100e_eval_ioe.h.

Field Documentation

uint16_t TS_STATE::TouchDetected

Definition at line 71 of file stm32100e_eval_ioe.h.

Referenced by EXTI15_10_IRQHandler(), IOE_TS_Config(), IOE_TS_GetState(), and main().

uint16_t TS_STATE::X

Definition at line 72 of file stm32100e_eval_ioe.h.

Referenced by EXTI15_10_IRQHandler(), IOE_TS_Config(), IOE_TS_GetState(), and main().

uint16_t TS_STATE::Y

Definition at line 73 of file stm32100e_eval_ioe.h.

Referenced by EXTI15_10_IRQHandler(), IOE_TS_Config(), IOE_TS_GetState(), and main().

uint16_t TS_STATE::Z

Definition at line 74 of file stm32100e_eval_ioe.h.

Referenced by IOE_TS_Config(), and IOE_TS_GetState().

The documentation for this struct was generated from the following files:
  • stm32100e_eval_ioe.h
  • stm3210c_eval_ioe.h


STM32F10x Standard Peripherals Firmware Library: STM32100E_EVAL_IOE_Exported_Constants

Defines

STM32100E_EVAL_IOE_Exported_Constants

STM32100E_EVAL_IOE

Defines

#define | _delay_ delay
Uncomment the line below to enable verfying each written byte in write operation.
#define | ALL_IT 0xFF
#define | Direction_IN 0x00
IO Pin directions.
#define | Direction_OUT 0x01
#define | EDGE_FALLING 0x01
Edge detection value.
#define | EDGE_RISING 0x02
#define | IO1_IN_ALL_PINS (uint32_t)(IO_Pin_ALL)
IO Exapanders Pins definition.
#define | IO1_OUT_ALL_PINS (uint32_t)(IO_Pin_ALL)
#define | IO_IT_0 0x01
IO Interrupts.
#define | IO_IT_1 0x02
#define | IO_IT_2 0x04
#define | IO_IT_3 0x08
#define | IO_IT_4 0x10
#define | IO_IT_5 0x20
#define | IO_IT_6 0x40
#define | IO_IT_7 0x80
#define | IO_Pin_0 0x01
IO Pins.
#define | IO_Pin_1 0x02
#define | IO_Pin_2 0x04
#define | IO_Pin_3 0x08
#define | IO_Pin_4 0x10
#define | IO_Pin_5 0x20
#define | IO_Pin_6 0x40
#define | IO_Pin_7 0x80
#define | IO_Pin_ALL 0xFF
#define | IOE_1_ADDR 0x82
The 7 bits IO Expanders adresses and chip IDs.
#define | IOE_ADC_FCT 0x01
IO Expander Functionalities definitions.
#define | IOE_DMA DMA1
IOE DMA definitions.
#define | IOE_DMA_CLK RCC_AHBPeriph_DMA1
#define | IOE_DMA_RX_CHANNEL DMA1_Channel5
#define | IOE_DMA_RX_TCFLAG DMA1_FLAG_TC5
#define | IOE_DMA_TX_CHANNEL DMA1_Channel4
#define | IOE_DMA_TX_TCFLAG DMA1_FLAG_TC4
#define | IOE_GIT_ADC 0x40
#define | IOE_GIT_EN 0x01
Global interrupt Enable bit.
#define | IOE_GIT_FE 0x10
#define | IOE_GIT_FF 0x08
#define | IOE_GIT_FOV 0x04
#define | IOE_GIT_FTH 0x02
#define | IOE_GIT_GPIO 0x80
Glaobal Interrupts definitions.
#define | IOE_GIT_TEMP 0x20
#define | IOE_GIT_TOUCH 0x01
#define | IOE_I2C I2C2
I2C port definitions.
#define | IOE_I2C_CLK RCC_APB1Periph_I2C2
#define | IOE_I2C_DR ((uint32_t)0x40005810)
#define | IOE_I2C_SCL_GPIO_CLK RCC_APB2Periph_GPIOB
#define | IOE_I2C_SCL_GPIO_PORT GPIOB
#define | IOE_I2C_SCL_PIN GPIO_Pin_10
#define | IOE_I2C_SDA_GPIO_CLK RCC_APB2Periph_GPIOB
#define | IOE_I2C_SDA_GPIO_PORT GPIOB
#define | IOE_I2C_SDA_PIN GPIO_Pin_11
#define | IOE_I2C_SPEED 300000
#define | IOE_IO_FCT 0x04
#define | IOE_IT_EXTI_IRQn EXTI15_10_IRQn
#define | IOE_IT_EXTI_LINE EXTI_Line12
#define | IOE_IT_EXTI_PIN_SOURCE GPIO_PinSource12
#define | IOE_IT_EXTI_PORT_SOURCE GPIO_PortSourceGPIOA
#define | IOE_IT_GPIO_CLK RCC_APB2Periph_GPIOA
#define | IOE_IT_GPIO_PORT GPIOA
#define | IOE_IT_PIN GPIO_Pin_12
IO Expander Interrupt line on EXTI.
#define | IOE_ITSRC_TEMPSENS 0x08
#define | IOE_ITSRC_TSC 0x01
Interrupt source configuration definitons.
#define | IOE_REG_ADC_CAPT 0x22
#define | IOE_REG_ADC_CTRL1 0x20
#define | IOE_REG_ADC_CTRL2 0x21
#define | IOE_REG_ADC_DATA_CH0 0x30
#define | IOE_REG_ADC_DATA_CH1 0x32
#define | IOE_REG_ADC_DATA_CH2 0x34
#define | IOE_REG_ADC_DATA_CH3 0x36
#define | IOE_REG_ADC_DATA_CH4 0x38
#define | IOE_REG_ADC_DATA_CH5 0x3A
#define | IOE_REG_ADC_DATA_CH6 0x3B
#define | IOE_REG_ADC_DATA_CH7 0x3C
#define | IOE_REG_ADC_INT_EN 0x0E
ADC Registers.
#define | IOE_REG_ADC_INT_STA 0x0F
#define | IOE_REG_CHP_ID 0x00
Identification registers.
#define | IOE_REG_FIFO_SIZE 0x4C
#define | IOE_REG_FIFO_STA 0x4B
#define | IOE_REG_FIFO_TH 0x4A
#define | IOE_REG_GPIO_AF 0x17
#define | IOE_REG_GPIO_CLR_PIN 0x11
#define | IOE_REG_GPIO_DIR 0x13
#define | IOE_REG_GPIO_ED 0x14
#define | IOE_REG_GPIO_FE 0x16
#define | IOE_REG_GPIO_INT_EN 0x0C
#define | IOE_REG_GPIO_INT_STA 0x0D
#define | IOE_REG_GPIO_MP_STA 0x12
#define | IOE_REG_GPIO_RE 0x15
#define | IOE_REG_GPIO_SET_PIN 0x10
GPIO Registers.
#define | IOE_REG_ID_VER 0x02
#define | IOE_REG_INT_CTRL 0x09
Interrupt Control register.
#define | IOE_REG_INT_EN 0x0A
#define | IOE_REG_INT_STA 0x0B
#define | IOE_REG_SPI_CFG 0x08
#define | IOE_REG_SYS_CTRL1 0x03
General Control Registers.
#define | IOE_REG_SYS_CTRL2 0x04
#define | IOE_REG_TEMP_CTRL 0x60
Temperature Sensor registers.
#define | IOE_REG_TEMP_DATA 0x61
#define | IOE_REG_TEMP_TH 0x62
#define | IOE_REG_TSC_CFG 0x41
#define | IOE_REG_TSC_CTRL 0x40
TouchScreen Registers.
#define | IOE_REG_TSC_DATA 0x57
#define | IOE_REG_TSC_DATA_X 0x4D
#define | IOE_REG_TSC_DATA_XYZ 0x52
#define | IOE_REG_TSC_DATA_Y 0x4F
#define | IOE_REG_TSC_DATA_Z 0x51
#define | IOE_REG_TSC_FRACT_XYZ 0x56
#define | IOE_REG_TSC_I_DRIVE 0x58
#define | IOE_REG_TSC_SHIELD 0x59
#define | IOE_REG_WDM_BL_X 0x46
#define | IOE_REG_WDM_BL_Y 0x48
#define | IOE_REG_WDM_TR_X 0x42
#define | IOE_REG_WDM_TR_Y 0x44
#define | IOE_TEMPSENS_FCT 0x08
#define | IOE_TS_FCT 0x02
#define | IOE_TS_IT (uint8_t)(IO_IT_0 | IO_IT_1 | IO_IT_2)
#define | Polarity_High 0x04
#define | Polarity_Low 0x00
Interrupt Line output parameters.
#define | STMPE811_ID 0x0811
#define | TOUCH_IO_ALL (uint32_t)(IO_Pin_1 | IO_Pin_2 | IO_Pin_3 | IO_Pin_4)
#define | TOUCH_XD IO_Pin_2 /* IO_Exapnader_1 */
#define | TOUCH_XU IO_Pin_4 /* IO_Exapnader_1 */
#define | TOUCH_YD IO_Pin_1 /* IO_Exapnader_1 */
Touch Screen Pins definition.
#define | TOUCH_YU IO_Pin_3 /* IO_Exapnader_1 */
#define | Type_Edge 0x02
#define | Type_Level 0x00

Define Documentation

#define _delay_ delay

Uncomment the line below to enable verfying each written byte in write operation.

The I2C_WriteDeviceRegister() function will then compare the written and read data and return error status if a mismatch occurs. Uncomment the line below if you want to use user defined Delay function (for precise timing), otherwise default _delay_ function defined within this driver is used (less precise timing). Uncomment the line below if you want to use user timeout callback. Function prototypes is declared in this file but function body may be implemented into user application.

Definition at line 143 of file stm32100e_eval_ioe.h.

#define ALL_IT 0xFF

Definition at line 361 of file stm32100e_eval_ioe.h.

Referenced by EXTI15_10_IRQHandler().

#define Direction_IN 0x00

IO Pin directions.

Definition at line 339 of file stm32100e_eval_ioe.h.

Referenced by IOE_Config(), and IOE_IOPinConfig().

#define Direction_OUT 0x01

Definition at line 340 of file stm32100e_eval_ioe.h.

Referenced by IOE_Config().

#define EDGE_FALLING 0x01

Edge detection value.

Definition at line 367 of file stm32100e_eval_ioe.h.

Referenced by IOE_Config(), and IOE_IOEdgeConfig().

#define EDGE_RISING 0x02

Definition at line 368 of file stm32100e_eval_ioe.h.

Referenced by IOE_Config(), and IOE_IOEdgeConfig().

#define IO1_IN_ALL_PINS (uint32_t)(IO_Pin_ALL)

IO Exapanders Pins definition.

Definition at line 225 of file stm32100e_eval_ioe.h.

Referenced by IOE_ReadIOPin().

#define IO1_OUT_ALL_PINS (uint32_t)(IO_Pin_ALL)

Definition at line 226 of file stm32100e_eval_ioe.h.

Referenced by IOE_WriteIOPin().

#define IO_IT_0 0x01

IO Interrupts.

Definition at line 353 of file stm32100e_eval_ioe.h.

#define IO_IT_1 0x02

Definition at line 354 of file stm32100e_eval_ioe.h.

#define IO_IT_2 0x04

Definition at line 355 of file stm32100e_eval_ioe.h.

#define IO_IT_3 0x08

Definition at line 356 of file stm32100e_eval_ioe.h.

#define IO_IT_4 0x10

Definition at line 357 of file stm32100e_eval_ioe.h.

#define IO_IT_5 0x20

Definition at line 358 of file stm32100e_eval_ioe.h.

#define IO_IT_6 0x40

Definition at line 359 of file stm32100e_eval_ioe.h.

#define IO_IT_7 0x80

Definition at line 360 of file stm32100e_eval_ioe.h.

#define IO_Pin_0 0x01

IO Pins.

Definition at line 326 of file stm32100e_eval_ioe.h.

#define IO_Pin_1 0x02

Definition at line 327 of file stm32100e_eval_ioe.h.

#define IO_Pin_2 0x04

Definition at line 328 of file stm32100e_eval_ioe.h.

#define IO_Pin_3 0x08

Definition at line 329 of file stm32100e_eval_ioe.h.

#define IO_Pin_4 0x10

Definition at line 330 of file stm32100e_eval_ioe.h.

#define IO_Pin_5 0x20

Definition at line 331 of file stm32100e_eval_ioe.h.

#define IO_Pin_6 0x40

Definition at line 332 of file stm32100e_eval_ioe.h.

#define IO_Pin_7 0x80

Definition at line 333 of file stm32100e_eval_ioe.h.

#define IO_Pin_ALL 0xFF

Definition at line 334 of file stm32100e_eval_ioe.h.

#define IOE_1_ADDR 0x82

The 7 bits IO Expanders adresses and chip IDs.

Definition at line 189 of file stm32100e_eval_ioe.h.

Referenced by EXTI15_10_IRQHandler(), IOE_Config(), IOE_ITConfig(), IOE_ITOutConfig(), IOE_ReadIOPin(), IOE_TempSens_Config(), IOE_TempSens_GetData(), IOE_TS_Config(), IOE_TS_GetState(), IOE_TS_Read_X(), IOE_TS_Read_Y(), IOE_TS_Read_Z(), and IOE_WriteIOPin().

#define IOE_ADC_FCT 0x01

IO Expander Functionalities definitions.

Definition at line 199 of file stm32100e_eval_ioe.h.

Referenced by IOE_Config(), IOE_TempSens_Config(), and IOE_TS_Config().

#define IOE_DMA DMA1

IOE DMA definitions.

Definition at line 166 of file stm32100e_eval_ioe.h.

#define IOE_DMA_CLK RCC_AHBPeriph_DMA1

Definition at line 167 of file stm32100e_eval_ioe.h.

Referenced by IOE_DMA_Config().

#define IOE_DMA_RX_CHANNEL DMA1_Channel5

Definition at line 169 of file stm32100e_eval_ioe.h.

Referenced by I2C_ReadDataBuffer(), I2C_ReadDeviceRegister(), and IOE_DMA_Config().

#define IOE_DMA_RX_TCFLAG DMA1_FLAG_TC5

Definition at line 171 of file stm32100e_eval_ioe.h.

Referenced by I2C_ReadDataBuffer(), and I2C_ReadDeviceRegister().

#define IOE_DMA_TX_CHANNEL DMA1_Channel4

Definition at line 168 of file stm32100e_eval_ioe.h.

Referenced by I2C_WriteDeviceRegister(), and IOE_DMA_Config().

#define IOE_DMA_TX_TCFLAG DMA1_FLAG_TC4

Definition at line 170 of file stm32100e_eval_ioe.h.

Referenced by I2C_WriteDeviceRegister().

#define IOE_GIT_ADC 0x40

Definition at line 214 of file stm32100e_eval_ioe.h.

#define IOE_GIT_EN 0x01

Global interrupt Enable bit.

Definition at line 373 of file stm32100e_eval_ioe.h.

Referenced by IOE_GITCmd().

#define IOE_GIT_FE 0x10

Definition at line 216 of file stm32100e_eval_ioe.h.

#define IOE_GIT_FF 0x08

Definition at line 217 of file stm32100e_eval_ioe.h.

#define IOE_GIT_FOV 0x04

Definition at line 218 of file stm32100e_eval_ioe.h.

Referenced by IOE_ITConfig(), and IOE_TS_Config().

#define IOE_GIT_FTH 0x02

Definition at line 219 of file stm32100e_eval_ioe.h.

Referenced by IOE_ITConfig(), and IOE_TS_Config().

#define IOE_GIT_GPIO 0x80

Glaobal Interrupts definitions.

Definition at line 213 of file stm32100e_eval_ioe.h.

Referenced by EXTI15_10_IRQHandler(), and IOE_ITConfig().

#define IOE_GIT_TEMP 0x20

Definition at line 215 of file stm32100e_eval_ioe.h.

#define IOE_GIT_TOUCH 0x01

Definition at line 220 of file stm32100e_eval_ioe.h.

Referenced by IOE_ITConfig(), and IOE_TS_Config().

#define IOE_I2C I2C2

I2C port definitions.

Definition at line 152 of file stm32100e_eval_ioe.h.

Referenced by I2C_ReadDataBuffer(), I2C_ReadDeviceRegister(), I2C_WriteDeviceRegister(), and IOE_I2C_Config().

#define IOE_I2C_CLK RCC_APB1Periph_I2C2

Definition at line 153 of file stm32100e_eval_ioe.h.

Referenced by IOE_GPIO_Config().

#define IOE_I2C_DR ((uint32_t)0x40005810)

Definition at line 160 of file stm32100e_eval_ioe.h.

Referenced by IOE_DMA_Config().

#define IOE_I2C_SCL_GPIO_CLK RCC_APB2Periph_GPIOB

Definition at line 156 of file stm32100e_eval_ioe.h.

Referenced by IOE_GPIO_Config().

#define IOE_I2C_SCL_GPIO_PORT GPIOB

Definition at line 155 of file stm32100e_eval_ioe.h.

Referenced by IOE_GPIO_Config().

#define IOE_I2C_SCL_PIN GPIO_Pin_10

Definition at line 154 of file stm32100e_eval_ioe.h.

Referenced by IOE_GPIO_Config().

#define IOE_I2C_SDA_GPIO_CLK RCC_APB2Periph_GPIOB

Definition at line 159 of file stm32100e_eval_ioe.h.

Referenced by IOE_GPIO_Config().

#define IOE_I2C_SDA_GPIO_PORT GPIOB

Definition at line 158 of file stm32100e_eval_ioe.h.

Referenced by IOE_GPIO_Config().

#define IOE_I2C_SDA_PIN GPIO_Pin_11

Definition at line 157 of file stm32100e_eval_ioe.h.

Referenced by IOE_GPIO_Config().

#define IOE_I2C_SPEED 300000

Definition at line 161 of file stm32100e_eval_ioe.h.

Referenced by IOE_I2C_Config().

#define IOE_IO_FCT 0x04

Definition at line 201 of file stm32100e_eval_ioe.h.

Referenced by IOE_Config().

#define IOE_IT_EXTI_IRQn EXTI15_10_IRQn

Definition at line 183 of file stm32100e_eval_ioe.h.

Referenced by IOE_EXTI_Config().

#define IOE_IT_EXTI_LINE EXTI_Line12

Definition at line 182 of file stm32100e_eval_ioe.h.

Referenced by EXTI15_10_IRQHandler(), and IOE_EXTI_Config().

#define IOE_IT_EXTI_PIN_SOURCE GPIO_PinSource12

Definition at line 181 of file stm32100e_eval_ioe.h.

Referenced by IOE_EXTI_Config(), and IOE_GPIO_Config().

#define IOE_IT_EXTI_PORT_SOURCE GPIO_PortSourceGPIOA

Definition at line 180 of file stm32100e_eval_ioe.h.

Referenced by IOE_EXTI_Config(), and IOE_GPIO_Config().

#define IOE_IT_GPIO_CLK RCC_APB2Periph_GPIOA

Definition at line 179 of file stm32100e_eval_ioe.h.

Referenced by IOE_EXTI_Config(), and IOE_GPIO_Config().

#define IOE_IT_GPIO_PORT GPIOA

Definition at line 178 of file stm32100e_eval_ioe.h.

Referenced by IOE_EXTI_Config(), and IOE_GPIO_Config().

#define IOE_IT_PIN GPIO_Pin_12

IO Expander Interrupt line on EXTI.

Definition at line 177 of file stm32100e_eval_ioe.h.

Referenced by IOE_EXTI_Config(), and IOE_GPIO_Config().

#define IOE_ITSRC_TEMPSENS 0x08

Definition at line 208 of file stm32100e_eval_ioe.h.

#define IOE_ITSRC_TSC 0x01

Interrupt source configuration definitons.

Definition at line 207 of file stm32100e_eval_ioe.h.

Referenced by IOE_ITConfig(), and main().

#define IOE_REG_ADC_CAPT 0x22

Definition at line 273 of file stm32100e_eval_ioe.h.

#define IOE_REG_ADC_CTRL1 0x20

Definition at line 271 of file stm32100e_eval_ioe.h.

Referenced by IOE_TS_Config().

#define IOE_REG_ADC_CTRL2 0x21

Definition at line 272 of file stm32100e_eval_ioe.h.

Referenced by IOE_TS_Config().

#define IOE_REG_ADC_DATA_CH0 0x30

Definition at line 274 of file stm32100e_eval_ioe.h.

#define IOE_REG_ADC_DATA_CH1 0x32

Definition at line 275 of file stm32100e_eval_ioe.h.

#define IOE_REG_ADC_DATA_CH2 0x34

Definition at line 276 of file stm32100e_eval_ioe.h.

#define IOE_REG_ADC_DATA_CH3 0x36

Definition at line 277 of file stm32100e_eval_ioe.h.

#define IOE_REG_ADC_DATA_CH4 0x38

Definition at line 278 of file stm32100e_eval_ioe.h.

#define IOE_REG_ADC_DATA_CH5 0x3A

Definition at line 279 of file stm32100e_eval_ioe.h.

#define IOE_REG_ADC_DATA_CH6 0x3B

Definition at line 280 of file stm32100e_eval_ioe.h.

#define IOE_REG_ADC_DATA_CH7 0x3C

Definition at line 281 of file stm32100e_eval_ioe.h.

#define IOE_REG_ADC_INT_EN 0x0E

ADC Registers.

Definition at line 269 of file stm32100e_eval_ioe.h.

#define IOE_REG_ADC_INT_STA 0x0F

Definition at line 270 of file stm32100e_eval_ioe.h.

#define IOE_REG_CHP_ID 0x00

Identification registers.

Definition at line 235 of file stm32100e_eval_ioe.h.

#define IOE_REG_FIFO_SIZE 0x4C

Definition at line 294 of file stm32100e_eval_ioe.h.

#define IOE_REG_FIFO_STA 0x4B

Definition at line 293 of file stm32100e_eval_ioe.h.

Referenced by IOE_TS_Config(), and IOE_TS_GetState().

#define IOE_REG_FIFO_TH 0x4A

Definition at line 292 of file stm32100e_eval_ioe.h.

Referenced by IOE_TS_Config().

#define IOE_REG_GPIO_AF 0x17

Definition at line 264 of file stm32100e_eval_ioe.h.

Referenced by IOE_IOAFConfig(), and IOE_TS_Config().

#define IOE_REG_GPIO_CLR_PIN 0x11

Definition at line 258 of file stm32100e_eval_ioe.h.

Referenced by IOE_WriteIOPin().

#define IOE_REG_GPIO_DIR 0x13

Definition at line 260 of file stm32100e_eval_ioe.h.

Referenced by IOE_IOPinConfig().

#define IOE_REG_GPIO_ED 0x14

Definition at line 261 of file stm32100e_eval_ioe.h.

Referenced by IOE_ClearIOITPending().

#define IOE_REG_GPIO_FE 0x16

Definition at line 263 of file stm32100e_eval_ioe.h.

Referenced by IOE_ClearIOITPending(), and IOE_IOEdgeConfig().

#define IOE_REG_GPIO_INT_EN 0x0C

Definition at line 251 of file stm32100e_eval_ioe.h.

Referenced by IOE_IOITConfig().

#define IOE_REG_GPIO_INT_STA 0x0D

Definition at line 252 of file stm32100e_eval_ioe.h.

Referenced by IOE_ClearIOITPending(), IOE_GetIOITStatus(), and IOE_ITConfig().

#define IOE_REG_GPIO_MP_STA 0x12

Definition at line 259 of file stm32100e_eval_ioe.h.

Referenced by IOE_JoyStickGetState(), and IOE_ReadIOPin().

#define IOE_REG_GPIO_RE 0x15

Definition at line 262 of file stm32100e_eval_ioe.h.

Referenced by IOE_ClearIOITPending(), and IOE_IOEdgeConfig().

#define IOE_REG_GPIO_SET_PIN 0x10

GPIO Registers.

Definition at line 257 of file stm32100e_eval_ioe.h.

Referenced by IOE_WriteIOPin().

#define IOE_REG_ID_VER 0x02

Definition at line 236 of file stm32100e_eval_ioe.h.

#define IOE_REG_INT_CTRL 0x09

Interrupt Control register.

Definition at line 248 of file stm32100e_eval_ioe.h.

Referenced by IOE_GITCmd(), and IOE_ITOutConfig().

#define IOE_REG_INT_EN 0x0A

Definition at line 249 of file stm32100e_eval_ioe.h.

Referenced by IOE_GITConfig(), and IOE_TS_Config().

#define IOE_REG_INT_STA 0x0B

Definition at line 250 of file stm32100e_eval_ioe.h.

Referenced by IOE_ClearGITPending(), IOE_GetGITStatus(), and IOE_TS_Config().

#define IOE_REG_SPI_CFG 0x08

Definition at line 243 of file stm32100e_eval_ioe.h.

#define IOE_REG_SYS_CTRL1 0x03

General Control Registers.

Definition at line 241 of file stm32100e_eval_ioe.h.

Referenced by IOE_Reset().

#define IOE_REG_SYS_CTRL2 0x04

Definition at line 242 of file stm32100e_eval_ioe.h.

Referenced by IOE_FnctCmd(), IOE_TempSens_Config(), and IOE_TS_Config().

#define IOE_REG_TEMP_CTRL 0x60

Temperature Sensor registers.

Definition at line 307 of file stm32100e_eval_ioe.h.

Referenced by IOE_TempSens_Config(), and IOE_TempSens_GetData().

#define IOE_REG_TEMP_DATA 0x61

Definition at line 308 of file stm32100e_eval_ioe.h.

Referenced by IOE_TempSens_GetData().

#define IOE_REG_TEMP_TH 0x62

Definition at line 309 of file stm32100e_eval_ioe.h.

#define IOE_REG_TSC_CFG 0x41

Definition at line 287 of file stm32100e_eval_ioe.h.

Referenced by IOE_TS_Config().

#define IOE_REG_TSC_CTRL 0x40

TouchScreen Registers.

Definition at line 286 of file stm32100e_eval_ioe.h.

Referenced by IOE_TS_Config(), and IOE_TS_GetState().

#define IOE_REG_TSC_DATA 0x57

Definition at line 300 of file stm32100e_eval_ioe.h.

#define IOE_REG_TSC_DATA_X 0x4D

Definition at line 295 of file stm32100e_eval_ioe.h.

Referenced by IOE_TS_Read_Y().

#define IOE_REG_TSC_DATA_XYZ 0x52

Definition at line 298 of file stm32100e_eval_ioe.h.

#define IOE_REG_TSC_DATA_Y 0x4F

Definition at line 296 of file stm32100e_eval_ioe.h.

Referenced by IOE_TS_Read_X().

#define IOE_REG_TSC_DATA_Z 0x51

Definition at line 297 of file stm32100e_eval_ioe.h.

Referenced by IOE_TS_Read_Z().

#define IOE_REG_TSC_FRACT_XYZ 0x56

Definition at line 299 of file stm32100e_eval_ioe.h.

Referenced by IOE_TS_Config().

#define IOE_REG_TSC_I_DRIVE 0x58

Definition at line 301 of file stm32100e_eval_ioe.h.

Referenced by IOE_TS_Config().

#define IOE_REG_TSC_SHIELD 0x59

Definition at line 302 of file stm32100e_eval_ioe.h.

#define IOE_REG_WDM_BL_X 0x46

Definition at line 290 of file stm32100e_eval_ioe.h.

#define IOE_REG_WDM_BL_Y 0x48

Definition at line 291 of file stm32100e_eval_ioe.h.

#define IOE_REG_WDM_TR_X 0x42

Definition at line 288 of file stm32100e_eval_ioe.h.

#define IOE_REG_WDM_TR_Y 0x44

Definition at line 289 of file stm32100e_eval_ioe.h.

#define IOE_TEMPSENS_FCT 0x08

Definition at line 202 of file stm32100e_eval_ioe.h.

Referenced by IOE_Config(), and IOE_TempSens_Config().

#define IOE_TS_FCT 0x02

Definition at line 200 of file stm32100e_eval_ioe.h.

Referenced by IOE_Config(), and IOE_TS_Config().

#define IOE_TS_IT (uint8_t)(IO_IT_0 | IO_IT_1 | IO_IT_2)

Definition at line 362 of file stm32100e_eval_ioe.h.

Referenced by EXTI15_10_IRQHandler().

#define Polarity_High 0x04

Definition at line 346 of file stm32100e_eval_ioe.h.

Referenced by IOE_ITConfig().

#define Polarity_Low 0x00

Interrupt Line output parameters.

Definition at line 345 of file stm32100e_eval_ioe.h.

Referenced by IOE_ITConfig().

#define STMPE811_ID 0x0811

Definition at line 190 of file stm32100e_eval_ioe.h.

Referenced by IOE_IsOperational().

#define TOUCH_IO_ALL (uint32_t)(IO_Pin_1 | IO_Pin_2 | IO_Pin_3 | IO_Pin_4)

Definition at line 321 of file stm32100e_eval_ioe.h.

Referenced by IOE_TS_Config().

#define TOUCH_XD IO_Pin_2 /* IO_Exapnader_1 */

Definition at line 318 of file stm32100e_eval_ioe.h.

#define TOUCH_XU IO_Pin_4 /* IO_Exapnader_1 */

Definition at line 320 of file stm32100e_eval_ioe.h.

#define TOUCH_YD IO_Pin_1 /* IO_Exapnader_1 */

Touch Screen Pins definition.

Definition at line 317 of file stm32100e_eval_ioe.h.

#define TOUCH_YU IO_Pin_3 /* IO_Exapnader_1 */

Definition at line 319 of file stm32100e_eval_ioe.h.

#define Type_Edge 0x02

Definition at line 348 of file stm32100e_eval_ioe.h.

#define Type_Level 0x00

Definition at line 347 of file stm32100e_eval_ioe.h.

Referenced by IOE_ITConfig().


STM32F10x Standard Peripherals Firmware Library: STM32100E_EVAL_IOE_Exported_Macros

STM32100E_EVAL_IOE_Exported_Macros

STM32100E_EVAL_IOE


STM32F10x Standard Peripherals Firmware Library: STM32100E_EVAL_IOE_Exported_Functions

Defines | Functions

STM32100E_EVAL_IOE_Exported_Functions

STM32100E_EVAL_IOE

Defines

#define | IOE_TimeoutUserCallback() IOE_TIMEOUT
Timeout user callback function.

Functions

uint16_t | I2C_ReadDataBuffer (uint8_t DeviceAddr, uint32_t RegisterAddr)
Reads a buffer of 2 bytes from the device registers.
uint8_t | I2C_ReadDeviceRegister (uint8_t DeviceAddr, uint8_t RegisterAddr)
Reads a register of the device through I2C.
uint8_t | I2C_WriteDeviceRegister (uint8_t DeviceAddr, uint8_t RegisterAddr, uint8_t RegisterValue)
Writes a value in a register of the device through I2C.
uint8_t | IOE_ClearGITPending (uint8_t DeviceAddr, uint8_t IO_IT)
Clears the selected Global interrupt pending bit(s)
uint8_t | IOE_ClearIOITPending (uint8_t DeviceAddr, uint8_t IO_IT)
Clears the selected IO interrupt pending bit(s).
uint8_t | IOE_Config (void)
Configuration and initialization functions.
uint8_t | IOE_FnctCmd (uint8_t DeviceAddr, uint8_t Fct, FunctionalState NewState)
Configures the selcted IO Expander functionalities.
FlagStatus | IOE_GetGITStatus (uint8_t DeviceAddr, uint8_t Global_IT)
Interrupts Mangement functions.
FlagStatus | IOE_GetIOITStatus (uint8_t DeviceAddr, uint8_t IO_IT)
Checks the status of the selected IO interrupt pending bit.
uint8_t | IOE_GITCmd (uint8_t DeviceAddr, FunctionalState NewState)
Enables or disables the Global interrupt.
uint8_t | IOE_GITConfig (uint8_t DeviceAddr, uint8_t Global_IT, FunctionalState NewState)
Configures the selected source to generate or not a global interrupt.
uint8_t | IOE_IOAFConfig (uint8_t DeviceAddr, uint8_t IO_Pin, FunctionalState NewState)
Configures the selected pin to be in Alternate function or not.
uint8_t | IOE_IOEdgeConfig (uint8_t DeviceAddr, uint8_t IO_Pin, uint8_t Edge)
Configures the Edge for which a transition is detectable for the the selected pin.
uint8_t | IOE_IOITConfig (uint8_t DeviceAddr, uint8_t IO_IT, FunctionalState NewState)
Configures the selected pins to generate an interrupt or not.
uint8_t | IOE_IOPinConfig (uint8_t DeviceAddr, uint8_t IO_Pin, uint8_t Direction)
Configures the selected pin direction (to be an input or an output)
uint8_t | IOE_IsOperational (uint8_t DeviceAddr)
IO-Expander Control functions.
uint8_t | IOE_ITConfig (uint32_t IOE_ITSRC_Source)
Configures The selected interrupts on the IO Expanders.
uint8_t | IOE_ITOutConfig (uint8_t Polarity, uint8_t Type)
Configures the Interrupt line active state and format (level/edge)
uint16_t | IOE_ReadID (uint8_t DeviceAddr)
Reads the selected device's ID.
uint8_t | IOE_ReadIOPin (uint32_t IO_Pin)
Returns the status of the selected input IO pin.
uint8_t | IOE_Reset (uint8_t DeviceAddr)
Resets the IO Expander by Software (SYS_CTRL1, RESET bit).
uint8_t | IOE_TempSens_Config (void)
Configures and enables the Temperature sensor module.
uint32_t | IOE_TempSens_GetData (void)
Temperature Sensor functions.
uint8_t | IOE_TS_Config (void)
Low Layer functions.
TS_STATE * | IOE_TS_GetState (void)
Touch Screen controller functions.
uint8_t | IOE_WriteIOPin (uint8_t IO_Pin, IOE_BitValue_TypeDef BitVal)
IO pins control functions.

Define Documentation

#define IOE_TimeoutUserCallback ( ) IOE_TIMEOUT

Timeout user callback function.

This function is called when a timeout condition occurs during communication with IO Expander. Only protoype of this function is decalred in IO Expander driver. Its implementation may be done into user application. This function may typically stop current operations and reset the I2C peripheral and IO Expander. To enable this function use uncomment the define USE_TIMEOUT_USER_CALLBACK at the top of this file.

Definition at line 412 of file stm32100e_eval_ioe.h.

Referenced by I2C_ReadDataBuffer(), I2C_ReadDeviceRegister(), I2C_WriteDeviceRegister(), and IOE_IsOperational().

Function Documentation

uint16_t I2C_ReadDataBuffer | ( | uint8_t | DeviceAddr,
 |  | uint32_t | RegisterAddr
 | ) |  |

Reads a buffer of 2 bytes from the device registers.

Parameters:
DeviceAddr,: The address of the device, could be : IOE_1_ADDR.
RegisterAddr,: The target register adress (between 00x and 0x24)
Return values:
A pointer to the buffer containing the two returned bytes (in halfword).
Parameters:
DeviceAddr,: The address of the device, could be : IOE_1_ADDR or IOE_2_ADDR.
RegisterAddr,: The target register adress (between 00x and 0x24)
Return values:
A pointer to the buffer containing the two returned bytes (in halfword).

Definition at line 1061 of file stm32100e_eval_ioe.c.

uint8_t I2C_ReadDeviceRegister | ( | uint8_t | DeviceAddr,
 |  | uint8_t | RegisterAddr
 | ) |  |

Reads a register of the device through I2C.

Parameters:
DeviceAddr,: The address of the device, could be : IOE_1_ADDR.
RegisterAddr,: The target register adress (between 00x and 0x24)
Return values:
The value of the read register (0xAA if Timout occured)
Parameters:
DeviceAddr,: The address of the device, could be : IOE_1_ADDR or IOE_2_ADDR.
RegisterAddr,: The target register adress (between 00x and 0x24)
Return values:
The value of the read register (0xAA if Timout occured)

Definition at line 965 of file stm32100e_eval_ioe.c.

uint8_t I2C_WriteDeviceRegister | ( | uint8_t | DeviceAddr,
 |  | uint8_t | RegisterAddr,
 |  | uint8_t | RegisterValue
 | ) |  |

Writes a value in a register of the device through I2C.

Parameters:
DeviceAddr,: The address of the IOExpander, could be : IOE_1_ADDR.
RegisterAddr,: The target register adress
RegisterValue,: The target register value to be written
Return values:
IOE_OK,: if all operations are OK. Other value if error.
Parameters:
DeviceAddr,: The address of the IOExpander, could be : IOE_1_ADDR or IOE_2_ADDR.
RegisterAddr,: The target register adress
RegisterValue,: The target register value to be written
Return values:
IOE_OK,: if all operations are OK. Other value if error.

Definition at line 865 of file stm32100e_eval_ioe.c.

uint8_t IOE_ClearGITPending | ( | uint8_t | DeviceAddr,
 |  | uint8_t | Global_IT
 | ) |  |

Clears the selected Global interrupt pending bit(s)

Parameters:
DeviceAddr,: The address of the IOExpander, could be : IOE_1_ADDR.
Global_IT,: the Global interrupt to be cleared, could be any combination of the following values:

  • Global_IT_GPIO : All IOs interrupt
  • Global_IT_ADC : ADC interrupt
  • Global_IT_TEMP : Temperature Sensor interrupts
  • Global_IT_FE : Touch Screen Controller FIFO Error interrupt
  • Global_IT_FF : Touch Screen Controller FIFO Full interrupt
  • Global_IT_FOV : Touch Screen Controller FIFO Overrun interrupt
  • Global_IT_FTH : Touch Screen Controller FIFO Threshold interrupt
  • Global_IT_TOUCH : Touch Screen Controller Touch Detected interrupt
Return values:
IOE_OK,: if all initializations are OK. Other value if error.
Parameters:
DeviceAddr,: The address of the IOExpander, could be : IOE_1_ADDR or IOE_2_ADDR.
Global_IT,: the Global interrupt to be cleared, could be any combination of the following values:

  • Global_IT_GPIO : All IOs interrupt
  • Global_IT_ADC : ADC interrupt
  • Global_IT_TEMP : Temperature Sensor interrupts
  • Global_IT_FE : Touch Screen Controller FIFO Error interrupt
  • Global_IT_FF : Touch Screen Controller FIFO Full interrupt
  • Global_IT_FOV : Touch Screen Controller FIFO Overrun interrupt
  • Global_IT_FTH : Touch Screen Controller FIFO Threshold interrupt
  • Global_IT_TOUCH : Touch Screen Controller Touch Detected interrupt
Return values:
IOE_OK,: if all initializations are OK. Other value if error.

Definition at line 374 of file stm32100e_eval_ioe.c.

uint8_t IOE_ClearIOITPending | ( | uint8_t | DeviceAddr,
 |  | uint8_t | IO_IT
 | ) |  |

Clears the selected IO interrupt pending bit(s).

Parameters:
DeviceAddr,: The address of the IOExpander, could be : IOE_1_ADDR.
IO_IT,: the IO interrupt to be checked could be IO_ITx Where x can be from 0 to 7.
Return values:
IOE_OK,: if all initializations are OK. Other value if error.
Parameters:
DeviceAddr,: The address of the IOExpander, could be : IOE_1_ADDR or IOE_2_ADDR.
IO_IT,: the IO interrupt to be checked could be IO_ITx Where x can be from 0 to 7.
Return values:
IOE_OK,: if all initializations are OK. Other value if error.

Definition at line 414 of file stm32100e_eval_ioe.c.

uint8_t IOE_Config ( void )

Configuration and initialization functions.

Configuration and initialization functions.

Parameters:
None
Return values:
IOE_OK if all initializations done correctly. Other value if error.

Definition at line 129 of file stm32100e_eval_ioe.c.

uint8_t IOE_FnctCmd | ( | uint8_t | DeviceAddr,
 |  | uint8_t | Fct,
 |  | FunctionalState | NewState
 | ) |  |

Configures the selcted IO Expander functionalities.

Parameters:
DeviceAddr,: The address of the IOExpander, could be : IOE_1_ADDR.
Fct,: the functions to be configured. could be any combination of the following values:

  • IOE_IO_FCT : IO function
  • IOE_TS_FCT : Touch Screen function
  • IOE_ADC_FCT : ADC function
  • IOE_TEMPSENS_FCT : Tempreature Sensor function
Return values:
IOE_OK,: if all initializations are OK. Other value if error.
Parameters:
DeviceAddr,: The address of the IOExpander, could be : IOE_1_ADDR or IOE_2_ADDR.
IOE_TEMPSENS_FCT,: the functions to be configured. could be any combination of the following values:

  • IOE_IO_FCT : IO function
  • IOE_TS_FCT : Touch Screen function
  • IOE_ADC_FCT : ADC function
  • IOE_TEMPSENS_FCT : Tempreature Sensor function
Return values:
IOE_OK,: if all initializations are OK. Other value if error.

Definition at line 507 of file stm32100e_eval_ioe.c.

FlagStatus IOE_GetGITStatus | ( | uint8_t | DeviceAddr,
 |  | uint8_t | Global_IT
 | ) |  |

Interrupts Mangement functions.

Interrupts Mangement functions.

Parameters:
DeviceAddr,: The address of the IOExpander, could be : IOE_1_ADDR.
Global_IT,: the Global interrupt source to be checked, could be:

  • Global_IT_GPIO : All IOs interrupt
  • Global_IT_ADC : ADC interrupt
  • Global_IT_TEMP : Temperature Sensor interrupts
  • Global_IT_FE : Touch Screen Controller FIFO Error interrupt
  • Global_IT_FF : Touch Screen Controller FIFO Full interrupt
  • Global_IT_FOV : Touch Screen Controller FIFO Overrun interrupt
  • Global_IT_FTH : Touch Screen Controller FIFO Threshold interrupt
  • Global_IT_TOUCH : Touch Screen Controller Touch Detected interrupt
Return values:
Status of the checked flag. Could be SET or RESET.

Interrupts Mangement functions.

Parameters:
DeviceAddr,: The address of the IOExpander, could be : IOE_1_ADDR or IOE_2_ADDR.
Global_IT,: the Global interrupt source to be checked, could be:

  • Global_IT_GPIO : All IOs interrupt
  • Global_IT_ADC : ADC interrupt
  • Global_IT_TEMP : Temperature Sensor interrupts
  • Global_IT_FE : Touch Screen Controller FIFO Error interrupt
  • Global_IT_FF : Touch Screen Controller FIFO Full interrupt
  • Global_IT_FOV : Touch Screen Controller FIFO Overrun interrupt
  • Global_IT_FTH : Touch Screen Controller FIFO Threshold interrupt
  • Global_IT_TOUCH : Touch Screen Controller Touch Detected interrupt
Return values:
Status of the checked flag. Could be SET or RESET.

Definition at line 342 of file stm32100e_eval_ioe.c.

FlagStatus IOE_GetIOITStatus | ( | uint8_t | DeviceAddr,
 |  | uint8_t | IO_IT
 | ) |  |

Checks the status of the selected IO interrupt pending bit.

Parameters:
DeviceAddr,: The address of the IOExpander, could be : IOE_1_ADDR.
IO_IT,: the IO interrupt to be checked could be IO_ITx Where x can be from 0 to 7.
Return values:
Status of the checked flag. Could be SET or RESET.
Parameters:
DeviceAddr,: The address of the IOExpander, could be : IOE_1_ADDR or IOE_2_ADDR.
IO_IT,: the IO interrupt to be checked could be IO_ITx Where x can be from 0 to 7.
Return values:
Status of the checked flag. Could be SET or RESET.

Definition at line 390 of file stm32100e_eval_ioe.c.

uint8_t IOE_GITCmd | ( | uint8_t | DeviceAddr,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the Global interrupt.

Parameters:
DeviceAddr,: The address of the IOExpander, could be :I OE_1_ADDR.
NewState,: could be ENABLE or DISABLE.
Return values:
IOE_OK,: if all initializations are OK. Other value if error.
Parameters:
DeviceAddr,: The address of the IOExpander, could be :I OE_1_ADDR or IOE_2_ADDR.
NewState,: could be ENABLE or DISABLE.
Return values:
IOE_OK,: if all initializations are OK. Other value if error.

Definition at line 568 of file stm32100e_eval_ioe.c.

uint8_t IOE_GITConfig | ( | uint8_t | DeviceAddr,
 |  | uint8_t | Global_IT,
 |  | FunctionalState | NewState
 | ) |  |

Configures the selected source to generate or not a global interrupt.

Parameters:
DeviceAddr,: The address of the IOExpander, could be : IOE_1_ADDR
Global_IT,: the interrupt source to be configured, could be:

  • Global_IT_GPIO : All IOs interrupt
  • Global_IT_ADC : ADC interrupt
  • Global_IT_TEMP : Temperature Sensor interrupts
  • Global_IT_FE : Touch Screen Controller FIFO Error interrupt
  • Global_IT_FF : Touch Screen Controller FIFO Full interrupt
  • Global_IT_FOV : Touch Screen Controller FIFO Overrun interrupt
  • Global_IT_FTH : Touch Screen Controller FIFO Threshold interrupt
  • Global_IT_TOUCH : Touch Screen Controller Touch Detected interrupt
Return values:
IOE_OK,: if all initializations are OK. Other value if error.
Parameters:
DeviceAddr,: The address of the IOExpander, could be : IOE_1_ADDR or IOE_2_ADDR.
Global_IT,: the interrupt source to be configured, could be:

  • Global_IT_GPIO : All IOs interrupt
  • Global_IT_ADC : ADC interrupt
  • Global_IT_TEMP : Temperature Sensor interrupts
  • Global_IT_FE : Touch Screen Controller FIFO Error interrupt
  • Global_IT_FF : Touch Screen Controller FIFO Full interrupt
  • Global_IT_FOV : Touch Screen Controller FIFO Overrun interrupt
  • Global_IT_FTH : Touch Screen Controller FIFO Threshold interrupt
  • Global_IT_TOUCH : Touch Screen Controller Touch Detected interrupt
Return values:
IOE_OK,: if all initializations are OK. Other value if error.

Definition at line 607 of file stm32100e_eval_ioe.c.

uint8_t IOE_IOAFConfig | ( | uint8_t | DeviceAddr,
 |  | uint8_t | IO_Pin,
 |  | FunctionalState | NewState
 | ) |  |

Configures the selected pin to be in Alternate function or not.

Parameters:
DeviceAddr,: The address of the IOExpander, could be : IOE_1_ADDR.
IO_Pin,: IO_Pin_x, Where x can be from 0 to 7.
NewState,: State of the AF for the selected pin, could be ENABLE or DISABLE.
Return values:
IOE_OK,: if all initializations are OK. Other value if error.
Parameters:
DeviceAddr,: The address of the IOExpander, could be : IOE_1_ADDR or IOE_2_ADDR.
IO_Pin,: IO_Pin_x, Where x can be from 0 to 7.
NewState,: State of the AF for the selected pin, could be ENABLE or DISABLE.
Return values:
IOE_OK,: if all initializations are OK. Other value if error.

Definition at line 761 of file stm32100e_eval_ioe.c.

uint8_t IOE_IOEdgeConfig | ( | uint8_t | DeviceAddr,
 |  | uint8_t | IO_Pin,
 |  | uint8_t | Edge
 | ) |  |

Configures the Edge for which a transition is detectable for the the selected pin.

Parameters:
DeviceAddr,: The address of the IOExpander, could be : IOE_1_ADDR.
IO_Pin,: IO_Pin_x, Where x can be from 0 to 7.
Edge,: The edge which will be detected. This parameter can be one or a a combination of follwing values: EDGE_FALLING and EDGE_RISING .
Return values:
IOE_OK,: if all initializations are OK. Other value if error.
Parameters:
DeviceAddr,: The address of the IOExpander, could be : IOE_1_ADDR or IOE_2_ADDR.
IO_Pin,: IO_Pin_x, Where x can be from 0 to 7.
Edge,: The edge which will be detected. This parameter can be one or a a combination of follwing values: EDGE_FALLING and EDGE_RISING .
Return values:
IOE_OK,: if all initializations are OK. Other value if error.

Definition at line 795 of file stm32100e_eval_ioe.c.

uint8_t IOE_IOITConfig | ( | uint8_t | DeviceAddr,
 |  | uint8_t | IO_IT,
 |  | FunctionalState | NewState
 | ) |  |

Configures the selected pins to generate an interrupt or not.

Parameters:
DeviceAddr,: The address of the IOExpander, could be : IOE_1_ADDR.
IO_IT,: The IO interrupt to be configured. This parameter could be any combination of the following values:

  • IO_IT_x: where x can be from 0 to 7.
NewState,: could be ENABLE or DISABLE.
Return values:
IOE_OK,: if all initializations are OK. Other value if error.
Parameters:
DeviceAddr,: The address of the IOExpander, could be : IOE_1_ADDR or IOE_2_ADDR.
IO_IT,: The IO interrupt to be configured. This parameter could be any combination of the following values:

  • IO_IT_x: where x can be from 0 to 7.
NewState,: could be ENABLE or DISABLE.
Return values:
IOE_OK,: if all initializations are OK. Other value if error.

Definition at line 640 of file stm32100e_eval_ioe.c.

uint8_t IOE_IOPinConfig | ( | uint8_t | DeviceAddr,
 |  | uint8_t | IO_Pin,
 |  | uint8_t | Direction
 | ) |  |

Configures the selected pin direction (to be an input or an output)

Parameters:
DeviceAddr,: The address of the IOExpander, could be : IOE_1_ADDR.
IO_Pin,: IO_Pin_x: Where x can be from 0 to 7.
Direction,: could be Direction_IN or Direction_OUT.
Return values:
IOE_OK,: if all initializations are OK. Other value if error.
Parameters:
DeviceAddr,: The address of the IOExpander, could be : IOE_1_ADDR or IOE_2_ADDR.
IO_Pin,: IO_Pin_x: Where x can be from 0 to 7.
Direction,: could be Direction_IN or Direction_OUT.
Return values:
IOE_OK,: if all initializations are OK. Other value if error.

Definition at line 539 of file stm32100e_eval_ioe.c.

uint8_t IOE_IsOperational ( uint8_t DeviceAddr )

IO-Expander Control functions.

IO-Expander Control functions.

Parameters:
DeviceAddr,: The address of the IOExpander, could be : IOE_1_ADDR.
Return values:
IOE_OK if IOE is operational. Other value if failure.

IO-Expander Control functions.

Parameters:
DeviceAddr,: The address of the IOExpander, could be : IOE_1_ADDR or IOE_2_ADDR.
Return values:
IOE_OK if IOE is operational. Other value if failure.

Definition at line 437 of file stm32100e_eval_ioe.c.

uint8_t IOE_ITConfig ( uint32_t IOE_ITSRC_Source )

Configures The selected interrupts on the IO Expanders.

Parameters:
IOE_ITSRC_Source,: the source of the interrupts. Could be one or a combination of the following parameters:

  • IOE_ITSRC_TSC: Touch Screen interrupts.
Return values:
IOE_OK,: if all initializations are OK. Other value if error.
Parameters:
IOE_ITSRC_Source,: the source of the interrupts. Could be one or a combination of the following parameters:

  • IOE_ITSRC_JOYSTICK: Joystick IO intputs.
  • IOE_ITSRC_TSC: Touch Screen interrupts.
  • IOE_ITSRC_INMEMS: MEMS interrupt lines.
Return values:
IOE_OK,: if all initializations are OK. Other value if error.

Definition at line 169 of file stm32100e_eval_ioe.c.

uint8_t IOE_ITOutConfig | ( | uint8_t | Polarity,
 |  | uint8_t | Type
 | ) |  |

Configures the Interrupt line active state and format (level/edge)

Parameters:
Polarity,: could be

  • Polarity_Low: Interrupt line is active Low/Falling edge
  • Polarity_High: Interrupt line is active High/Rising edge
Type,: Interrupt line activity type, could be one of the following values

  • Type_Level: Interrupt line is active in level model
  • Type_Edge: Interrupt line is active in edge model
Return values:
IOE_OK,: if all initializations are OK. Other value if error.

Definition at line 838 of file stm32100e_eval_ioe.c.

uint16_t IOE_ReadID ( uint8_t DeviceAddr )

Reads the selected device's ID.

Parameters:
DeviceAddr,: The address of the IOExpander, could be : IOE_1_ADDR.
Return values:
The Device ID (two bytes).
Parameters:
DeviceAddr,: The address of the IOExpander, could be : IOE_1_ADDR or IOE_2_ADDR.
Return values:
The Device ID (two bytes).

Definition at line 483 of file stm32100e_eval_ioe.c.

uint8_t IOE_ReadIOPin ( uint32_t IO_Pin )

Returns the status of the selected input IO pin.

Parameters:
IO_Pin,: The input pin to be read. IO_Pin_x: Where x can be from 0 to 7.

  • JOY_IO_PINS: Joystick IO pins (use IOE_JoyStickGetState for these pins)
Return values:
None
Parameters:
IO_Pin,: The input pin to be read. This parameter can be one of the following values:

  • MEMS_INT1_PIN: MEMS interrupt line 1.
  • MEMS_INT2_PIN: MEMS interrupt line 2.
  • JOY_IO_PINS: Joystick IO pins (use IOE_JoyStickGetState for these pins)
Return values:
None

Definition at line 239 of file stm32100e_eval_ioe.c.

uint8_t IOE_Reset ( uint8_t DeviceAddr )

Resets the IO Expander by Software (SYS_CTRL1, RESET bit).

Parameters:
DeviceAddr,: The address of the IOExpander, could be : IOE_1_ADDR.
Return values:
IOE_OK,: if all initializations are OK. Other value if error.
Parameters:
DeviceAddr,: The address of the IOExpander, could be : IOE_1_ADDR or IOE_2_ADDR.
Return values:
IOE_OK,: if all initializations are OK. Other value if error.

Definition at line 463 of file stm32100e_eval_ioe.c.

uint8_t IOE_TempSens_Config ( void )

Configures and enables the Temperature sensor module.

Parameters:
None
Return values:
IOE_OK if all initializations are OK. Other value if error.

Definition at line 734 of file stm32100e_eval_ioe.c.

uint32_t IOE_TempSens_GetData ( void )

Temperature Sensor functions.

Temperature Sensor functions.

Parameters:
None
Return values:
The temperature row value.

Definition at line 310 of file stm32100e_eval_ioe.c.

uint8_t IOE_TS_Config ( void )

Low Layer functions.

Low Layer functions.

Parameters:
None
Return values:
IOE_OK if all initializations are OK. Other value if error.

Definition at line 669 of file stm32100e_eval_ioe.c.

TS_STATE* IOE_TS_GetState ( void )

Touch Screen controller functions.

Touch Screen controller functions.

Parameters:
None
Return values:
Pointer to TS_STATE structure holding Touch Screen information.

Definition at line 270 of file stm32100e_eval_ioe.c.

uint8_t IOE_WriteIOPin | ( | uint8_t | IO_Pin,
 |  | IOE_BitValue_TypeDef | BitVal
 | ) |  |

IO pins control functions.

IO pins control functions.

Parameters:
IO_Pin,: The output pin to be set or reset. IO_Pin_x: Where x can be from 0 to 7.
BitVal,: The value to be set. This parameter can be one of the following values: BitSet or BitReset. See IOE_BitVal_TypeDef.
Return values:
IOE_OK or PARAM_ERROR

IO pins control functions.

Parameters:
IO_Pin,: The output pin to be set or reset. This parameter can be one of the following values:

  • AUDIO_RESET_PIN: Audio codec reset pin
  • MII_INT_PIN: Ethernet Phy MII interrupt pin
  • VBAT_DIV_PIN: Battery devider pin
BitVal,: The value to be set. This parameter can be one of the following values: BitSet or BitReset. See IOE_BitVal_TypeDef.
Return values:
IOE_OK or PARAM_ERROR

Definition at line 202 of file stm32100e_eval_ioe.c.


STM32F10x Standard Peripherals Firmware Library: LCD_TypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

LCD_TypeDef Struct Reference
STM32100E_EVAL_LCD_Private_TypesDefinitions | STM3210E_EVAL_LCD_Private_TypesDefinitions

Data Fields

__IO uint16_t | LCD_RAM
__IO uint16_t | LCD_REG

Detailed Description

Definition at line 50 of file stm32100e_eval_lcd.c.

Field Documentation

__IO uint16_t LCD_TypeDef::LCD_RAM

Definition at line 53 of file stm32100e_eval_lcd.c.

__IO uint16_t LCD_TypeDef::LCD_REG

Definition at line 52 of file stm32100e_eval_lcd.c.

The documentation for this struct was generated from the following files:
  • stm32100e_eval_lcd.c
  • stm3210e_eval_lcd.c


STM32F10x Standard Peripherals Firmware Library: STM32100E_EVAL_LCD_Private_Defines

Defines

STM32100E_EVAL_LCD_Private_Defines

STM32100E_EVAL_LCD

Defines

#define | LCD ((LCD_TypeDef *) LCD_BASE)
#define | LCD_BASE ((uint32_t)(0x60000000 | 0x0C000000))
#define | MAX_POLY_CORNERS 200
#define | POLY_X(Z) ((int32_t)((Points + Z)->Y))
#define | POLY_Y(Z) ((int32_t)((Points + Z)->X))

Define Documentation

#define LCD ((LCD_TypeDef *) LCD_BASE)

Definition at line 65 of file stm32100e_eval_lcd.c.

Referenced by LCD_Clear(), LCD_GLASS_Clear(), LCD_GLASS_ClearChar(), LCD_GLASS_WriteChar(), LCD_ReadRAM(), LCD_ReadReg(), LCD_WriteRAM(), LCD_WriteRAM_Prepare(), and LCD_WriteReg().

#define LCD_BASE ((uint32_t)(0x60000000 | 0x0C000000))

Definition at line 64 of file stm32100e_eval_lcd.c.

#define MAX_POLY_CORNERS 200

Definition at line 66 of file stm32100e_eval_lcd.c.

Referenced by LCD_FillPolyLine().

#define POLY_X ( Z ) ((int32_t)((Points + Z)->Y))

Definition at line 68 of file stm32100e_eval_lcd.c.

Referenced by LCD_FillPolyLine().

#define POLY_Y ( Z ) ((int32_t)((Points + Z)->X))

Definition at line 67 of file stm32100e_eval_lcd.c.

Referenced by LCD_FillPolyLine().


STM32F10x Standard Peripherals Firmware Library: STM32100E_EVAL_LCD_Private_Macros

Defines

STM32100E_EVAL_LCD_Private_Macros

STM32100E_EVAL_LCD

Defines

#define ABS(X) ((X) > 0 ? (X) : -(X))

Define Documentation

#define ABS ( X ) ((X) > 0 ? (X) : -(X))

Definition at line 76 of file stm32100e_eval_lcd.c.

Referenced by LCD_DrawUniLine().


STM32F10x Standard Peripherals Firmware Library: STM32100E_EVAL_LCD_Private_Variables

Variables

STM32100E_EVAL_LCD_Private_Variables

STM32100E_EVAL_LCD

Variables

static __IO uint16_t | BackColor = 0xFFFF
static sFONT * | LCD_Currentfonts
static __IO uint16_t | TextColor = 0x0000

Variable Documentation

__IO uint16_t BackColor = 0xFFFF

Definition at line 86 of file stm32100e_eval_lcd.c.

sFONT* LCD_Currentfonts [static]

Definition at line 84 of file stm32100e_eval_lcd.c.

Referenced by LCD_GetFont().

__IO uint16_t TextColor = 0x0000 [static]

Definition at line 86 of file stm32100e_eval_lcd.c.

Referenced by LCD_DrawChar(), LCD_DrawCircle(), LCD_DrawFullCircle(), LCD_DrawFullRect(), LCD_DrawLine(), LCD_DrawMonoPict(), LCD_FillPolyLine(), LCD_GetColors(), LCD_SetColors(), and LCD_SetTextColor().


STM32F10x Standard Peripherals Firmware Library: STM32100E_EVAL_LCD_Private_FunctionPrototypes

STM32100E_EVAL_LCD_Private_FunctionPrototypes

STM32100E_EVAL_LCD


STM32F10x Standard Peripherals Firmware Library: STM32100E_EVAL_LCD_Private_Functions

Functions

STM32100E_EVAL_LCD_Private_Functions

STM32100E_EVAL_LCD

Functions

static void | delay (vu32 nCount)
Inserts a delay time.
void | LCD_Clear (uint16_t Color)
Clears the hole LCD.
void | LCD_ClearLine (uint8_t Line)
Clears the selected line.
void | LCD_ClosedPolyLine (pPoint Points, uint16_t PointCount)
Displays a closed polyline (between many points).
void | LCD_ClosedPolyLineRelative (pPoint Points, uint16_t PointCount)
Displays a closed relative polyline (between many points).
void | LCD_CtrlLinesConfig (void)
Configures LCD Control lines (FSMC Pins) in alternate function mode.
void | LCD_DeInit (void)
DeInitializes the LCD.
void | LCD_DisplayChar (uint8_t Line, uint16_t Column, uint8_t Ascii)
Displays one character (16dots width, 24dots height).
void | LCD_DisplayOff (void)
Disables the Display.
void | LCD_DisplayOn (void)
Enables the Display.
void | LCD_DisplayStringLine (uint8_t Line, uint8_t *ptr)
Displays a maximum of 20 char on the LCD.
void | LCD_DrawChar (uint8_t Xpos, uint16_t Ypos, const uint16_t *c)
Draws a character on LCD.
void | LCD_DrawCircle (uint8_t Xpos, uint16_t Ypos, uint16_t Radius)
Displays a circle.
void | LCD_DrawFullCircle (uint16_t Xpos, uint16_t Ypos, uint16_t Radius)
Displays a full circle.
void | LCD_DrawFullRect (uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height)
Displays a full rectangle.
void | LCD_DrawLine (uint8_t Xpos, uint16_t Ypos, uint16_t Length, uint8_t Direction)
Displays a line.
void | LCD_DrawMonoPict (const uint32_t *Pict)
Displays a monocolor picture.
void | LCD_DrawRect (uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width)
Displays a rectangle.
void | LCD_DrawUniLine (uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2)
Displays an uni line (between two points).
void | LCD_FillPolyLine (pPoint Points, uint16_t PointCount)
Displays a full polyline (between many points).
void | LCD_FSMCConfig (void)
Configures the Parallel interface (FSMC) for LCD(Parallel mode)
void | LCD_GetColors (__IO uint16_t *_TextColor, __IO uint16_t *_BackColor)
Gets the LCD Text and Background colors.
sFONT * | LCD_GetFont (void)
Gets the Text Font.
void | LCD_PolyLine (pPoint Points, uint16_t PointCount)
Displays an polyline (between many points).
void | LCD_PolyLineRelative (pPoint Points, uint16_t PointCount)
Displays a relative polyline (between many points).
static void | LCD_PolyLineRelativeClosed (pPoint Points, uint16_t PointCount, uint16_t Closed)
Displays an relative polyline (between many points).
void | LCD_PowerOn (void)
Power on the LCD.
uint16_t | LCD_ReadRAM (void)
Reads the LCD RAM.
uint16_t | LCD_ReadReg (uint8_t LCD_Reg)
Reads the selected LCD Register.
void | LCD_SetBackColor (__IO uint16_t Color)
Sets the Background color.
void | LCD_SetColors (__IO uint16_t _TextColor, __IO uint16_t _BackColor)
Sets the LCD Text and Background colors.
void | LCD_SetCursor (uint8_t Xpos, uint16_t Ypos)
Sets the cursor position.
void | LCD_SetDisplayWindow (uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width)
Sets a display window.
void | LCD_SetFont (sFONT *fonts)
Sets the Text Font.
void | LCD_SetTextColor (__IO uint16_t Color)
Sets the Text color.
void | LCD_WindowModeDisable (void)
Disables LCD Window mode.
void | LCD_WriteBMP (uint32_t BmpAddress)
Displays a bitmap picture loaded in the internal Flash.
void | LCD_WriteRAM (uint16_t RGB_Code)
Writes to the LCD RAM.
void | LCD_WriteRAM_Prepare (void)
Prepare to write to the LCD RAM.
void | LCD_WriteReg (uint8_t LCD_Reg, uint16_t LCD_RegValue)
Writes to the selected LCD register.
static void | PutPixel (int16_t x, int16_t y)
Displays a pixel.
void | STM32100E_LCD_Init (void)
Initializes the LCD.

Function Documentation

static void delay ( vu32 nCount ) [static]

Inserts a delay time.

Parameters:
nCount,: specifies the delay time length.
Return values:
None

Definition at line 1391 of file stm32100e_eval_lcd.c.

References index.

void LCD_Clear ( uint16_t Color )

Clears the hole LCD.

Parameters:
Color,: the color of the background.
Return values:
None

Definition at line 489 of file stm32100e_eval_lcd.c.

References index, LCD, LCD_SetCursor(), and LCD_WriteRAM_Prepare().

void LCD_ClearLine ( uint8_t Line )

Clears the selected line.

Parameters:
Line,: the Line to be cleared. This parameter can be one of the following values:

  • Linex: where x can be 0..n
Return values:
None

Definition at line 470 of file stm32100e_eval_lcd.c.

References LCD_DisplayChar(), LCD_PIXEL_WIDTH, and _tFont::Width.

void LCD_ClosedPolyLine | ( | pPoint | Points,
 |  | uint16_t | PointCount
 | ) |  |

Displays a closed polyline (between many points).

Parameters:
Points,: pointer to the points array.
PointCount,: Number of points.
Return values:
None

Definition at line 1032 of file stm32100e_eval_lcd.c.

References LCD_DrawUniLine(), LCD_PolyLine(), Point::X, and Point::Y.

void LCD_ClosedPolyLineRelative | ( | pPoint | Points,
 |  | uint16_t | PointCount
 | ) |  |

Displays a closed relative polyline (between many points).

Parameters:
Points,: pointer to the points array.
PointCount,: Number of points.
Return values:
None

Definition at line 1055 of file stm32100e_eval_lcd.c.

References LCD_PolyLineRelativeClosed().

void LCD_CtrlLinesConfig ( void )

Configures LCD Control lines (FSMC Pins) in alternate function mode.

Configures LCD control lines in Output Push-Pull mode.

Parameters:
None
Return values:
None

Definition at line 1288 of file stm32100e_eval_lcd.c.

References ENABLE, GPIO_Init(), GPIO_InitStructure, GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_AF_PP, GPIO_InitTypeDef::GPIO_Pin, GPIO_Pin_0, GPIO_Pin_1, GPIO_Pin_10, GPIO_Pin_11, GPIO_Pin_12, GPIO_Pin_13, GPIO_Pin_14, GPIO_Pin_15, GPIO_Pin_4, GPIO_Pin_5, GPIO_Pin_7, GPIO_Pin_8, GPIO_Pin_9, GPIO_InitTypeDef::GPIO_Speed, GPIO_Speed_50MHz, GPIOD, GPIOE, GPIOF, GPIOG, RCC_AHBPeriph_FSMC, RCC_AHBPeriphClockCmd(), RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE, RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, and RCC_APB2PeriphClockCmd().

void LCD_DeInit ( void )

DeInitializes the LCD.

Parameters:
None
Return values:
None

< LCD Display Off

< LCD_SPI DeInit

Definition at line 115 of file stm32100e_eval_lcd.c.

References ENABLE, FSMC_Bank1_NORSRAM4, FSMC_NORSRAMCmd(), FSMC_NORSRAMDeInit(), GPIO_Init(), GPIO_InitStructure, GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_IN_FLOATING, GPIO_InitTypeDef::GPIO_Pin, GPIO_Pin_0, GPIO_Pin_1, GPIO_Pin_10, GPIO_Pin_11, GPIO_Pin_12, GPIO_Pin_13, GPIO_Pin_14, GPIO_Pin_15, GPIO_Pin_4, GPIO_Pin_5, GPIO_Pin_7, GPIO_Pin_8, GPIO_Pin_9, GPIOD, GPIOE, GPIOF, GPIOG, and LCD_DisplayOff().

void LCD_DisplayChar | ( | uint8_t | Line,
 |  | uint16_t | Column,
 |  | uint8_t | Ascii
 | ) |  |

Displays one character (16dots width, 24dots height).

Parameters:
Line,: the Line where to display the character shape . This parameter can be one of the following values:

  • Linex: where x can be 0..9
Column,: start column address.
Ascii,: character ascii code, must be between 0x20 and 0x7E.
Return values:
None

Definition at line 562 of file stm32100e_eval_lcd.c.

References _tFont::Height, LCD_DrawChar(), and _tFont::table.

void LCD_DisplayOff ( void )

Disables the Display.

Parameters:
None
Return values:
None

Definition at line 1276 of file stm32100e_eval_lcd.c.

References LCD_REG_7, and LCD_WriteReg().

void LCD_DisplayOn ( void )

Enables the Display.

Parameters:
None
Return values:
None

Definition at line 1264 of file stm32100e_eval_lcd.c.

References LCD_REG_7, and LCD_WriteReg().

void LCD_DisplayStringLine | ( | uint8_t | Line,
 |  | uint8_t * | ptr
 | ) |  |

Displays a maximum of 20 char on the LCD.

Parameters:
Line,: the Line where to display the character shape . This parameter can be one of the following values:

  • Linex: where x can be 0..9
*ptr,: pointer to string to display on LCD.
Return values:
None

Definition at line 577 of file stm32100e_eval_lcd.c.

References LCD_DisplayChar(), LCD_PIXEL_WIDTH, and _tFont::Width.

void LCD_DrawChar | ( | uint8_t | Xpos,
 |  | uint16_t | Ypos,
 |  | const uint16_t * | c
 | ) |  |

Draws a character on LCD.

Parameters:
Xpos,: the Line where to display the character shape.
Ypos,: start column address.
c,: pointer to the character data.
Return values:
None

Definition at line 522 of file stm32100e_eval_lcd.c.

References BackColor, _tFont::Height, index, LCD_SetCursor(), LCD_WriteRAM(), LCD_WriteRAM_Prepare(), TextColor, and _tFont::Width.

void LCD_DrawCircle | ( | uint8_t | Xpos,
 |  | uint16_t | Ypos,
 |  | uint16_t | Radius
 | ) |  |

Displays a circle.

Parameters:
Xpos,: specifies the X position.
Ypos,: specifies the Y position.
Radius
Return values:
None

Definition at line 702 of file stm32100e_eval_lcd.c.

References LCD_SetCursor(), LCD_WriteRAM(), LCD_WriteRAM_Prepare(), and TextColor.

void LCD_DrawFullCircle | ( | uint16_t | Xpos,
 |  | uint16_t | Ypos,
 |  | uint16_t | Radius
 | ) |  |

Displays a full circle.

Parameters:
Xpos,: specifies the X position.
Ypos,: specifies the Y position.
Radius
Return values:
None

Definition at line 853 of file stm32100e_eval_lcd.c.

References BackColor, LCD_DIR_HORIZONTAL, LCD_DrawCircle(), LCD_DrawLine(), LCD_SetTextColor(), and TextColor.

void LCD_DrawFullRect | ( | uint16_t | Xpos,
 |  | uint16_t | Ypos,
 |  | uint16_t | Width,
 |  | uint16_t | Height
 | ) |  |

Displays a full rectangle.

Parameters:
Xpos,: specifies the X position.
Ypos,: specifies the Y position.
Height,: rectangle height.
Width,: rectangle width.
Return values:
None

Definition at line 822 of file stm32100e_eval_lcd.c.

References BackColor, LCD_DIR_HORIZONTAL, LCD_DIR_VERTICAL, LCD_DrawLine(), LCD_SetTextColor(), and TextColor.

void LCD_DrawLine | ( | uint8_t | Xpos,
 |  | uint16_t | Ypos,
 |  | uint16_t | Length,
 |  | uint8_t | Direction
 | ) |  |

Displays a line.

Parameters:
Xpos,: specifies the X position.
Ypos,: specifies the Y position.
Length,: line length.
Direction,: line direction. This parameter can be one of the following values: Vertical or Horizontal.
Return values:
None

Definition at line 651 of file stm32100e_eval_lcd.c.

References LCD_DIR_HORIZONTAL, LCD_SetCursor(), LCD_WriteRAM(), LCD_WriteRAM_Prepare(), and TextColor.

void LCD_DrawMonoPict ( const uint32_t * Pict )

Displays a monocolor picture.

Parameters:
Pict,: pointer to the picture array.
Return values:
None

Definition at line 757 of file stm32100e_eval_lcd.c.

References BackColor, index, LCD_PIXEL_WIDTH, LCD_SetCursor(), LCD_WriteRAM(), LCD_WriteRAM_Prepare(), and TextColor.

void LCD_DrawRect | ( | uint8_t | Xpos,
 |  | uint16_t | Ypos,
 |  | uint8_t | Height,
 |  | uint16_t | Width
 | ) |  |

Displays a rectangle.

Parameters:
Xpos,: specifies the X position.
Ypos,: specifies the Y position.
Height,: display rectangle height.
Width,: display rectangle width.
Return values:
None

Definition at line 685 of file stm32100e_eval_lcd.c.

References LCD_DIR_HORIZONTAL, LCD_DIR_VERTICAL, and LCD_DrawLine().

void LCD_DrawUniLine | ( | uint16_t | x1,
 |  | uint16_t | y1,
 |  | uint16_t | x2,
 |  | uint16_t | y2
 | ) |  |

Displays an uni line (between two points).

Parameters:
x1,: specifies the point 1 x position.
y1,: specifies the point 1 y position.
x2,: specifies the point 2 x position.
y2,: specifies the point 2 y position.
Return values:
None

Definition at line 903 of file stm32100e_eval_lcd.c.

References ABS, and PutPixel().

void LCD_FillPolyLine | ( | pPoint | Points,
 |  | uint16_t | PointCount
 | ) |  |

Displays a full polyline (between many points).

Parameters:
Points,: pointer to the points array.
PointCount,: Number of points.
Return values:
None

Definition at line 1067 of file stm32100e_eval_lcd.c.

References BackColor, j, LCD_DIR_HORIZONTAL, LCD_DrawLine(), LCD_SetTextColor(), MAX_POLY_CORNERS, POLY_X, POLY_Y, PutPixel(), TextColor, Point::X, and Point::Y.

void LCD_FSMCConfig ( void )

Configures the Parallel interface (FSMC) for LCD(Parallel mode)

Parameters:
None
Return values:
None

Definition at line 1328 of file stm32100e_eval_lcd.c.

Referenced by STM32100E_LCD_Init(), and STM3210E_LCD_Init().

void LCD_GetColors | ( | __IO uint16_t * | _TextColor,
 |  | __IO uint16_t * | _BackColor
 | ) |  |

Gets the LCD Text and Background colors.

Parameters:
_TextColor,: pointer to the variable that will contain the Text Color.
_BackColor,: pointer to the variable that will contain the Background Color.
Return values:
None

Definition at line 417 of file stm32100e_eval_lcd.c.

References BackColor, and TextColor.

sFONT* LCD_GetFont ( void )

Gets the Text Font.

Parameters:
None.
Return values:
the used font.

Definition at line 458 of file stm32100e_eval_lcd.c.

References LCD_Currentfonts.

void LCD_PolyLine | ( | pPoint | Points,
 |  | uint16_t | PointCount
 | ) |  |

Displays an polyline (between many points).

Parameters:
Points,: pointer to the points array.
PointCount,: Number of points.
Return values:
None

Definition at line 976 of file stm32100e_eval_lcd.c.

References LCD_DrawUniLine(), Point::X, and Point::Y.

void LCD_PolyLineRelative | ( | pPoint | Points,
 |  | uint16_t | PointCount
 | ) |  |

Displays a relative polyline (between many points).

Parameters:
Points,: pointer to the points array.
PointCount,: Number of points.
Return values:
None

Definition at line 1044 of file stm32100e_eval_lcd.c.

References LCD_PolyLineRelativeClosed().

static void LCD_PolyLineRelativeClosed | ( | pPoint | Points,
 |  | uint16_t | PointCount,
 |  | uint16_t | Closed
 | ) |  | [static]

Displays an relative polyline (between many points).

Parameters:
Points,: pointer to the points array.
PointCount,: Number of points.
Closed,: specifies if the draw is closed or not. 1: closed, 0 : not closed.
Return values:
None

Definition at line 1002 of file stm32100e_eval_lcd.c.

References LCD_DrawUniLine(), Point::X, and Point::Y.

Referenced by LCD_ClosedPolyLineRelative(), and LCD_PolyLineRelative().

void LCD_PowerOn ( void )

Power on the LCD.

Parameters:
None
Return values:
None

Definition at line 1239 of file stm32100e_eval_lcd.c.

References _delay_, LCD_REG_16, LCD_REG_17, LCD_REG_18, LCD_REG_19, LCD_REG_41, LCD_REG_7, and LCD_WriteReg().

uint16_t LCD_ReadRAM ( void )

Reads the LCD RAM.

Parameters:
None
Return values:
LCD RAM Value.

Definition at line 1225 of file stm32100e_eval_lcd.c.

uint16_t LCD_ReadReg ( uint8_t LCD_Reg )

Reads the selected LCD Register.

Parameters:
LCD_Reg,: address of the selected register.
Return values:
LCD Register Value.

Definition at line 1188 of file stm32100e_eval_lcd.c.

References LCD.

void LCD_SetBackColor ( __IO uint16_t Color )

Sets the Background color.

Parameters:
Color,: specifies the Background color code RGB(5-6-5).
Return values:
None

Definition at line 438 of file stm32100e_eval_lcd.c.

References BackColor.

void LCD_SetColors | ( | __IO uint16_t | _TextColor,
 |  | __IO uint16_t | _BackColor
 | ) |  |

Sets the LCD Text and Background colors.

Parameters:
_TextColor,: specifies the Text Color.
_BackColor,: specifies the Background Color.
Return values:
None

Definition at line 403 of file stm32100e_eval_lcd.c.

References BackColor, and TextColor.

void LCD_SetCursor | ( | uint8_t | Xpos,
 |  | uint16_t | Ypos
 | ) |  |

Sets the cursor position.

Parameters:
Xpos,: specifies the X position.
Ypos,: specifies the Y position.
Return values:
None

Definition at line 508 of file stm32100e_eval_lcd.c.

References LCD_REG_32, LCD_REG_33, and LCD_WriteReg().

void LCD_SetDisplayWindow | ( | uint8_t | Xpos,
 |  | uint16_t | Ypos,
 |  | uint8_t | Height,
 |  | uint16_t | Width
 | ) |  |

Sets a display window.

Parameters:
Xpos,: specifies the X buttom left position.
Ypos,: specifies the Y buttom left position.
Height,: display window height.
Width,: display window width.
Return values:
None

Definition at line 602 of file stm32100e_eval_lcd.c.

References LCD_REG_80, LCD_REG_81, LCD_REG_82, LCD_REG_83, LCD_SetCursor(), and LCD_WriteReg().

void LCD_SetFont ( sFONT * fonts )

Sets the Text Font.

Parameters:
fonts,: specifies the font to be used.
Return values:
None

Definition at line 448 of file stm32100e_eval_lcd.c.

void LCD_SetTextColor ( __IO uint16_t Color )

Sets the Text color.

Parameters:
Color,: specifies the Text color code RGB(5-6-5).
Return values:
None

Definition at line 427 of file stm32100e_eval_lcd.c.

References TextColor.

void LCD_WindowModeDisable ( void )

Disables LCD Window mode.

Parameters:
None
Return values:
None

Definition at line 635 of file stm32100e_eval_lcd.c.

References LCD_REG_3, LCD_SetDisplayWindow(), and LCD_WriteReg().

void LCD_WriteBMP ( uint32_t BmpAddress )

Displays a bitmap picture loaded in the internal Flash.

Parameters:
BmpAddress,: Bmp picture address in the internal Flash.
Return values:
None

Definition at line 784 of file stm32100e_eval_lcd.c.

void LCD_WriteRAM ( uint16_t RGB_Code )

Writes to the LCD RAM.

Parameters:
RGB_Code,: the pixel color in RGB mode (5-6-5).
Return values:
None

Definition at line 1213 of file stm32100e_eval_lcd.c.

References LCD.

void LCD_WriteRAM_Prepare ( void )

Prepare to write to the LCD RAM.

Parameters:
None
Return values:
None

Definition at line 1202 of file stm32100e_eval_lcd.c.

References LCD, and LCD_REG_34.

void LCD_WriteReg | ( | uint8_t | LCD_Reg,
 |  | uint16_t | LCD_RegValue
 | ) |  |

Writes to the selected LCD register.

Parameters:
LCD_Reg,: address of the selected register.
LCD_RegValue,: value to write to the selected register.
Return values:
None

Definition at line 1174 of file stm32100e_eval_lcd.c.

References LCD.

static void PutPixel | ( | int16_t | x,
 |  | int16_t | y
 | ) |  | [static]

Displays a pixel.

Parameters:
x,: pixel x.
y,: pixel y.
Return values:
None

Definition at line 1376 of file stm32100e_eval_lcd.c.

References LCD_DIR_HORIZONTAL, and LCD_DrawLine().

Referenced by LCD_DrawUniLine(), and LCD_FillPolyLine().

void STM32100E_LCD_Init ( void )

Initializes the LCD.

Parameters:
None
Return values:
None

Definition at line 154 of file stm32100e_eval_lcd.c.

References _delay_, LCD_CtrlLinesConfig(), LCD_DEFAULT_FONT, LCD_FSMCConfig(), LCD_ReadReg(), LCD_REG_0, LCD_REG_1, LCD_REG_10, LCD_REG_106, LCD_REG_12, LCD_REG_128, LCD_REG_129, LCD_REG_13, LCD_REG_130, LCD_REG_131, LCD_REG_132, LCD_REG_133, LCD_REG_144, LCD_REG_146, LCD_REG_147, LCD_REG_149, LCD_REG_15, LCD_REG_151, LCD_REG_152, LCD_REG_16, LCD_REG_17, LCD_REG_18, LCD_REG_19, LCD_REG_2, LCD_REG_229, LCD_REG_3, LCD_REG_32, LCD_REG_33, LCD_REG_4, LCD_REG_41, LCD_REG_48, LCD_REG_49, LCD_REG_50, LCD_REG_51, LCD_REG_52, LCD_REG_53, LCD_REG_54, LCD_REG_55, LCD_REG_56, LCD_REG_57, LCD_REG_58, LCD_REG_59, LCD_REG_60, LCD_REG_61, LCD_REG_62, LCD_REG_63, LCD_REG_7, LCD_REG_8, LCD_REG_80, LCD_REG_81, LCD_REG_82, LCD_REG_83, LCD_REG_9, LCD_REG_96, LCD_REG_97, LCD_SetFont(), and LCD_WriteReg().

Referenced by main().


STM32F10x Standard Peripherals Firmware Library: STM32100E_EVAL_LCD_Exported_Types

Data Structures | Typedefs

STM32100E_EVAL_LCD_Exported_Types

STM32100E_EVAL_LCD

Data Structures

struct | Point

Typedefs

typedef struct Point * | pPoint

Typedef Documentation

typedef struct Point * pPoint


STM32F10x Standard Peripherals Firmware Library: STM32100E_EVAL_LCD_Exported_Constants

Defines

STM32100E_EVAL_LCD_Exported_Constants

STM32100E_EVAL_LCD

Defines

#define | _delay_ delay
Uncomment the line below if you want to use user defined Delay function (for precise timing), otherwise default _delay_ function defined within this driver is used (less precise timing).
#define | LCD_COLOR_BLACK 0x0000
#define | LCD_COLOR_BLUE 0x001F
#define | LCD_COLOR_BLUE2 0x051F
#define | LCD_COLOR_CYAN 0x7FFF
#define | LCD_COLOR_GREEN 0x07E0
#define | LCD_COLOR_GREY 0xF7DE
#define | LCD_COLOR_MAGENTA 0xF81F
#define | LCD_COLOR_RED 0xF800
#define | LCD_COLOR_WHITE 0xFFFF
LCD color.
#define | LCD_COLOR_YELLOW 0xFFE0
#define | LCD_DEFAULT_FONT Font16x24
LCD default font.
#define | LCD_DIR_HORIZONTAL 0x0000
LCD Direction.
#define | LCD_DIR_VERTICAL 0x0001
#define | LCD_LINE_0 LINE(0)
LCD Lines depending on the chosen fonts.
#define | LCD_LINE_1 LINE(1)
#define | LCD_LINE_10 LINE(10)
#define | LCD_LINE_11 LINE(11)
#define | LCD_LINE_12 LINE(12)
#define | LCD_LINE_13 LINE(13)
#define | LCD_LINE_14 LINE(14)
#define | LCD_LINE_15 LINE(15)
#define | LCD_LINE_16 LINE(16)
#define | LCD_LINE_17 LINE(17)
#define | LCD_LINE_18 LINE(18)
#define | LCD_LINE_19 LINE(19)
#define | LCD_LINE_2 LINE(2)
#define | LCD_LINE_20 LINE(20)
#define | LCD_LINE_21 LINE(21)
#define | LCD_LINE_22 LINE(22)
#define | LCD_LINE_23 LINE(23)
#define | LCD_LINE_24 LINE(24)
#define | LCD_LINE_25 LINE(25)
#define | LCD_LINE_26 LINE(26)
#define | LCD_LINE_27 LINE(27)
#define | LCD_LINE_28 LINE(28)
#define | LCD_LINE_29 LINE(29)
#define | LCD_LINE_3 LINE(3)
#define | LCD_LINE_4 LINE(4)
#define | LCD_LINE_5 LINE(5)
#define | LCD_LINE_6 LINE(6)
#define | LCD_LINE_7 LINE(7)
#define | LCD_LINE_8 LINE(8)
#define | LCD_LINE_9 LINE(9)
#define | LCD_PIXEL_HEIGHT 0x00F0
#define | LCD_PIXEL_WIDTH 0x0140
LCD Size (Width and Height)
#define | LCD_REG_0 0x00
LCD Registers.
#define | LCD_REG_1 0x01
#define | LCD_REG_10 0x0A
#define | LCD_REG_106 0x6A
#define | LCD_REG_118 0x76
#define | LCD_REG_12 0x0C
#define | LCD_REG_128 0x80
#define | LCD_REG_129 0x81
#define | LCD_REG_13 0x0D
#define | LCD_REG_130 0x82
#define | LCD_REG_131 0x83
#define | LCD_REG_132 0x84
#define | LCD_REG_133 0x85
#define | LCD_REG_134 0x86
#define | LCD_REG_135 0x87
#define | LCD_REG_136 0x88
#define | LCD_REG_137 0x89
#define | LCD_REG_139 0x8B
#define | LCD_REG_14 0x0E
#define | LCD_REG_140 0x8C
#define | LCD_REG_141 0x8D
#define | LCD_REG_143 0x8F
#define | LCD_REG_144 0x90
#define | LCD_REG_145 0x91
#define | LCD_REG_146 0x92
#define | LCD_REG_147 0x93
#define | LCD_REG_148 0x94
#define | LCD_REG_149 0x95
#define | LCD_REG_15 0x0F
#define | LCD_REG_150 0x96
#define | LCD_REG_151 0x97
#define | LCD_REG_152 0x98
#define | LCD_REG_153 0x99
#define | LCD_REG_154 0x9A
#define | LCD_REG_157 0x9D
#define | LCD_REG_16 0x10
#define | LCD_REG_17 0x11
#define | LCD_REG_18 0x12
#define | LCD_REG_19 0x13
#define | LCD_REG_192 0xC0
#define | LCD_REG_193 0xC1
#define | LCD_REG_2 0x02
#define | LCD_REG_20 0x14
#define | LCD_REG_21 0x15
#define | LCD_REG_22 0x16
#define | LCD_REG_229 0xE5
#define | LCD_REG_23 0x17
#define | LCD_REG_24 0x18
#define | LCD_REG_25 0x19
#define | LCD_REG_26 0x1A
#define | LCD_REG_27 0x1B
#define | LCD_REG_28 0x1C
#define | LCD_REG_29 0x1D
#define | LCD_REG_3 0x03
#define | LCD_REG_30 0x1E
#define | LCD_REG_31 0x1F
#define | LCD_REG_32 0x20
#define | LCD_REG_33 0x21
#define | LCD_REG_34 0x22
#define | LCD_REG_36 0x24
#define | LCD_REG_37 0x25
#define | LCD_REG_4 0x04
#define | LCD_REG_40 0x28
#define | LCD_REG_41 0x29
#define | LCD_REG_43 0x2B
#define | LCD_REG_45 0x2D
#define | LCD_REG_48 0x30
#define | LCD_REG_49 0x31
#define | LCD_REG_5 0x05
#define | LCD_REG_50 0x32
#define | LCD_REG_51 0x33
#define | LCD_REG_52 0x34
#define | LCD_REG_53 0x35
#define | LCD_REG_54 0x36
#define | LCD_REG_55 0x37
#define | LCD_REG_56 0x38
#define | LCD_REG_57 0x39
#define | LCD_REG_58 0x3A
#define | LCD_REG_59 0x3B
#define | LCD_REG_6 0x06
#define | LCD_REG_60 0x3C
#define | LCD_REG_61 0x3D
#define | LCD_REG_62 0x3E
#define | LCD_REG_63 0x3F
#define | LCD_REG_64 0x40
#define | LCD_REG_65 0x41
#define | LCD_REG_66 0x42
#define | LCD_REG_67 0x43
#define | LCD_REG_68 0x44
#define | LCD_REG_69 0x45
#define | LCD_REG_7 0x07
#define | LCD_REG_70 0x46
#define | LCD_REG_71 0x47
#define | LCD_REG_72 0x48
#define | LCD_REG_73 0x49
#define | LCD_REG_74 0x4A
#define | LCD_REG_75 0x4B
#define | LCD_REG_76 0x4C
#define | LCD_REG_77 0x4D
#define | LCD_REG_78 0x4E
#define | LCD_REG_79 0x4F
#define | LCD_REG_8 0x08
#define | LCD_REG_80 0x50
#define | LCD_REG_81 0x51
#define | LCD_REG_82 0x52
#define | LCD_REG_83 0x53
#define | LCD_REG_9 0x09
#define | LCD_REG_96 0x60
#define | LCD_REG_97 0x61

Define Documentation

#define _delay_ delay

Uncomment the line below if you want to use user defined Delay function (for precise timing), otherwise default _delay_ function defined within this driver is used (less precise timing).

Definition at line 79 of file stm32100e_eval_lcd.h.

#define LCD_COLOR_BLACK 0x0000

Definition at line 199 of file stm32100e_eval_lcd.h.

#define LCD_COLOR_BLUE 0x001F

Definition at line 201 of file stm32100e_eval_lcd.h.

#define LCD_COLOR_BLUE2 0x051F

Definition at line 202 of file stm32100e_eval_lcd.h.

#define LCD_COLOR_CYAN 0x7FFF

Definition at line 206 of file stm32100e_eval_lcd.h.

#define LCD_COLOR_GREEN 0x07E0

Definition at line 205 of file stm32100e_eval_lcd.h.

#define LCD_COLOR_GREY 0xF7DE

Definition at line 200 of file stm32100e_eval_lcd.h.

#define LCD_COLOR_MAGENTA 0xF81F

Definition at line 204 of file stm32100e_eval_lcd.h.

#define LCD_COLOR_RED 0xF800

Definition at line 203 of file stm32100e_eval_lcd.h.

#define LCD_COLOR_WHITE 0xFFFF

LCD color.

Definition at line 198 of file stm32100e_eval_lcd.h.

#define LCD_COLOR_YELLOW 0xFFE0

Definition at line 207 of file stm32100e_eval_lcd.h.

#define LCD_DEFAULT_FONT Font16x24

LCD default font.

Definition at line 246 of file stm32100e_eval_lcd.h.

#define LCD_DIR_HORIZONTAL 0x0000

LCD Direction.

Definition at line 251 of file stm32100e_eval_lcd.h.

#define LCD_DIR_VERTICAL 0x0001

Definition at line 252 of file stm32100e_eval_lcd.h.

#define LCD_LINE_0 LINE(0)

LCD Lines depending on the chosen fonts.

Definition at line 212 of file stm32100e_eval_lcd.h.

#define LCD_LINE_1 LINE(1)

Definition at line 213 of file stm32100e_eval_lcd.h.

#define LCD_LINE_10 LINE(10)

Definition at line 222 of file stm32100e_eval_lcd.h.

#define LCD_LINE_11 LINE(11)

Definition at line 223 of file stm32100e_eval_lcd.h.

#define LCD_LINE_12 LINE(12)

Definition at line 224 of file stm32100e_eval_lcd.h.

#define LCD_LINE_13 LINE(13)

Definition at line 225 of file stm32100e_eval_lcd.h.

#define LCD_LINE_14 LINE(14)

Definition at line 226 of file stm32100e_eval_lcd.h.

#define LCD_LINE_15 LINE(15)

Definition at line 227 of file stm32100e_eval_lcd.h.

#define LCD_LINE_16 LINE(16)

Definition at line 228 of file stm32100e_eval_lcd.h.

#define LCD_LINE_17 LINE(17)

Definition at line 229 of file stm32100e_eval_lcd.h.

#define LCD_LINE_18 LINE(18)

Definition at line 230 of file stm32100e_eval_lcd.h.

#define LCD_LINE_19 LINE(19)

Definition at line 231 of file stm32100e_eval_lcd.h.

#define LCD_LINE_2 LINE(2)

Definition at line 214 of file stm32100e_eval_lcd.h.

#define LCD_LINE_20 LINE(20)

Definition at line 232 of file stm32100e_eval_lcd.h.

#define LCD_LINE_21 LINE(21)

Definition at line 233 of file stm32100e_eval_lcd.h.

#define LCD_LINE_22 LINE(22)

Definition at line 234 of file stm32100e_eval_lcd.h.

#define LCD_LINE_23 LINE(23)

Definition at line 235 of file stm32100e_eval_lcd.h.

#define LCD_LINE_24 LINE(24)

Definition at line 236 of file stm32100e_eval_lcd.h.

#define LCD_LINE_25 LINE(25)

Definition at line 237 of file stm32100e_eval_lcd.h.

#define LCD_LINE_26 LINE(26)

Definition at line 238 of file stm32100e_eval_lcd.h.

#define LCD_LINE_27 LINE(27)

Definition at line 239 of file stm32100e_eval_lcd.h.

#define LCD_LINE_28 LINE(28)

Definition at line 240 of file stm32100e_eval_lcd.h.

#define LCD_LINE_29 LINE(29)

Definition at line 241 of file stm32100e_eval_lcd.h.

#define LCD_LINE_3 LINE(3)

Definition at line 215 of file stm32100e_eval_lcd.h.

#define LCD_LINE_4 LINE(4)

Definition at line 216 of file stm32100e_eval_lcd.h.

#define LCD_LINE_5 LINE(5)

Definition at line 217 of file stm32100e_eval_lcd.h.

#define LCD_LINE_6 LINE(6)

Definition at line 218 of file stm32100e_eval_lcd.h.

#define LCD_LINE_7 LINE(7)

Definition at line 219 of file stm32100e_eval_lcd.h.

#define LCD_LINE_8 LINE(8)

Definition at line 220 of file stm32100e_eval_lcd.h.

#define LCD_LINE_9 LINE(9)

Definition at line 221 of file stm32100e_eval_lcd.h.

#define LCD_PIXEL_HEIGHT 0x00F0

Definition at line 258 of file stm32100e_eval_lcd.h.

#define LCD_PIXEL_WIDTH 0x0140

LCD Size (Width and Height)

Definition at line 257 of file stm32100e_eval_lcd.h.

#define LCD_REG_0 0x00

LCD Registers.

Definition at line 85 of file stm32100e_eval_lcd.h.

#define LCD_REG_1 0x01

Definition at line 86 of file stm32100e_eval_lcd.h.

#define LCD_REG_10 0x0A

Definition at line 95 of file stm32100e_eval_lcd.h.

#define LCD_REG_106 0x6A

Definition at line 163 of file stm32100e_eval_lcd.h.

#define LCD_REG_118 0x76

Definition at line 164 of file stm32100e_eval_lcd.h.

#define LCD_REG_12 0x0C

Definition at line 96 of file stm32100e_eval_lcd.h.

#define LCD_REG_128 0x80

Definition at line 165 of file stm32100e_eval_lcd.h.

#define LCD_REG_129 0x81

Definition at line 166 of file stm32100e_eval_lcd.h.

#define LCD_REG_13 0x0D

Definition at line 97 of file stm32100e_eval_lcd.h.

#define LCD_REG_130 0x82

Definition at line 167 of file stm32100e_eval_lcd.h.

#define LCD_REG_131 0x83

Definition at line 168 of file stm32100e_eval_lcd.h.

#define LCD_REG_132 0x84

Definition at line 169 of file stm32100e_eval_lcd.h.

#define LCD_REG_133 0x85

Definition at line 170 of file stm32100e_eval_lcd.h.

#define LCD_REG_134 0x86

Definition at line 171 of file stm32100e_eval_lcd.h.

#define LCD_REG_135 0x87

Definition at line 172 of file stm32100e_eval_lcd.h.

#define LCD_REG_136 0x88

Definition at line 173 of file stm32100e_eval_lcd.h.

#define LCD_REG_137 0x89

Definition at line 174 of file stm32100e_eval_lcd.h.

#define LCD_REG_139 0x8B

Definition at line 175 of file stm32100e_eval_lcd.h.

#define LCD_REG_14 0x0E

Definition at line 98 of file stm32100e_eval_lcd.h.

#define LCD_REG_140 0x8C

Definition at line 176 of file stm32100e_eval_lcd.h.

#define LCD_REG_141 0x8D

Definition at line 177 of file stm32100e_eval_lcd.h.

#define LCD_REG_143 0x8F

Definition at line 178 of file stm32100e_eval_lcd.h.

#define LCD_REG_144 0x90

Definition at line 179 of file stm32100e_eval_lcd.h.

#define LCD_REG_145 0x91

Definition at line 180 of file stm32100e_eval_lcd.h.

#define LCD_REG_146 0x92

Definition at line 181 of file stm32100e_eval_lcd.h.

#define LCD_REG_147 0x93

Definition at line 182 of file stm32100e_eval_lcd.h.

#define LCD_REG_148 0x94

Definition at line 183 of file stm32100e_eval_lcd.h.

#define LCD_REG_149 0x95

Definition at line 184 of file stm32100e_eval_lcd.h.

#define LCD_REG_15 0x0F

Definition at line 99 of file stm32100e_eval_lcd.h.

#define LCD_REG_150 0x96

Definition at line 185 of file stm32100e_eval_lcd.h.

#define LCD_REG_151 0x97

Definition at line 186 of file stm32100e_eval_lcd.h.

#define LCD_REG_152 0x98

Definition at line 187 of file stm32100e_eval_lcd.h.

#define LCD_REG_153 0x99

Definition at line 188 of file stm32100e_eval_lcd.h.

#define LCD_REG_154 0x9A

Definition at line 189 of file stm32100e_eval_lcd.h.

#define LCD_REG_157 0x9D

Definition at line 190 of file stm32100e_eval_lcd.h.

#define LCD_REG_16 0x10

Definition at line 100 of file stm32100e_eval_lcd.h.

#define LCD_REG_17 0x11

Definition at line 101 of file stm32100e_eval_lcd.h.

#define LCD_REG_18 0x12

Definition at line 102 of file stm32100e_eval_lcd.h.

#define LCD_REG_19 0x13

Definition at line 103 of file stm32100e_eval_lcd.h.

#define LCD_REG_192 0xC0

Definition at line 191 of file stm32100e_eval_lcd.h.

#define LCD_REG_193 0xC1

Definition at line 192 of file stm32100e_eval_lcd.h.

#define LCD_REG_2 0x02

Definition at line 87 of file stm32100e_eval_lcd.h.

#define LCD_REG_20 0x14

Definition at line 104 of file stm32100e_eval_lcd.h.

#define LCD_REG_21 0x15

Definition at line 105 of file stm32100e_eval_lcd.h.

#define LCD_REG_22 0x16

Definition at line 106 of file stm32100e_eval_lcd.h.

#define LCD_REG_229 0xE5

Definition at line 193 of file stm32100e_eval_lcd.h.

#define LCD_REG_23 0x17

Definition at line 107 of file stm32100e_eval_lcd.h.

#define LCD_REG_24 0x18

Definition at line 108 of file stm32100e_eval_lcd.h.

#define LCD_REG_25 0x19

Definition at line 109 of file stm32100e_eval_lcd.h.

#define LCD_REG_26 0x1A

Definition at line 110 of file stm32100e_eval_lcd.h.

#define LCD_REG_27 0x1B

Definition at line 111 of file stm32100e_eval_lcd.h.

#define LCD_REG_28 0x1C

Definition at line 112 of file stm32100e_eval_lcd.h.

#define LCD_REG_29 0x1D

Definition at line 113 of file stm32100e_eval_lcd.h.

#define LCD_REG_3 0x03

Definition at line 88 of file stm32100e_eval_lcd.h.

#define LCD_REG_30 0x1E

Definition at line 114 of file stm32100e_eval_lcd.h.

#define LCD_REG_31 0x1F

Definition at line 115 of file stm32100e_eval_lcd.h.

#define LCD_REG_32 0x20

Definition at line 116 of file stm32100e_eval_lcd.h.

#define LCD_REG_33 0x21

Definition at line 117 of file stm32100e_eval_lcd.h.

#define LCD_REG_34 0x22

Definition at line 118 of file stm32100e_eval_lcd.h.

#define LCD_REG_36 0x24

Definition at line 119 of file stm32100e_eval_lcd.h.

#define LCD_REG_37 0x25

Definition at line 120 of file stm32100e_eval_lcd.h.

#define LCD_REG_4 0x04

Definition at line 89 of file stm32100e_eval_lcd.h.

#define LCD_REG_40 0x28

Definition at line 121 of file stm32100e_eval_lcd.h.

#define LCD_REG_41 0x29

Definition at line 122 of file stm32100e_eval_lcd.h.

#define LCD_REG_43 0x2B

Definition at line 123 of file stm32100e_eval_lcd.h.

#define LCD_REG_45 0x2D

Definition at line 124 of file stm32100e_eval_lcd.h.

#define LCD_REG_48 0x30

Definition at line 125 of file stm32100e_eval_lcd.h.

#define LCD_REG_49 0x31

Definition at line 126 of file stm32100e_eval_lcd.h.

#define LCD_REG_5 0x05

Definition at line 90 of file stm32100e_eval_lcd.h.

#define LCD_REG_50 0x32

Definition at line 127 of file stm32100e_eval_lcd.h.

#define LCD_REG_51 0x33

Definition at line 128 of file stm32100e_eval_lcd.h.

#define LCD_REG_52 0x34

Definition at line 129 of file stm32100e_eval_lcd.h.

#define LCD_REG_53 0x35

Definition at line 130 of file stm32100e_eval_lcd.h.

#define LCD_REG_54 0x36

Definition at line 131 of file stm32100e_eval_lcd.h.

#define LCD_REG_55 0x37

Definition at line 132 of file stm32100e_eval_lcd.h.

#define LCD_REG_56 0x38

Definition at line 133 of file stm32100e_eval_lcd.h.

#define LCD_REG_57 0x39

Definition at line 134 of file stm32100e_eval_lcd.h.

#define LCD_REG_58 0x3A

Definition at line 135 of file stm32100e_eval_lcd.h.

Referenced by STM32100E_LCD_Init(), and STM3210E_LCD_Init().

#define LCD_REG_59 0x3B

Definition at line 136 of file stm32100e_eval_lcd.h.

#define LCD_REG_6 0x06

Definition at line 91 of file stm32100e_eval_lcd.h.

#define LCD_REG_60 0x3C

Definition at line 137 of file stm32100e_eval_lcd.h.

#define LCD_REG_61 0x3D

Definition at line 138 of file stm32100e_eval_lcd.h.

#define LCD_REG_62 0x3E

Definition at line 139 of file stm32100e_eval_lcd.h.

#define LCD_REG_63 0x3F

Definition at line 140 of file stm32100e_eval_lcd.h.

#define LCD_REG_64 0x40

Definition at line 141 of file stm32100e_eval_lcd.h.

#define LCD_REG_65 0x41

Definition at line 142 of file stm32100e_eval_lcd.h.

#define LCD_REG_66 0x42

Definition at line 143 of file stm32100e_eval_lcd.h.

#define LCD_REG_67 0x43

Definition at line 144 of file stm32100e_eval_lcd.h.

#define LCD_REG_68 0x44

Definition at line 145 of file stm32100e_eval_lcd.h.

#define LCD_REG_69 0x45

Definition at line 146 of file stm32100e_eval_lcd.h.

#define LCD_REG_7 0x07

Definition at line 92 of file stm32100e_eval_lcd.h.

#define LCD_REG_70 0x46

Definition at line 147 of file stm32100e_eval_lcd.h.

#define LCD_REG_71 0x47

Definition at line 148 of file stm32100e_eval_lcd.h.

#define LCD_REG_72 0x48

Definition at line 149 of file stm32100e_eval_lcd.h.

#define LCD_REG_73 0x49

Definition at line 150 of file stm32100e_eval_lcd.h.

#define LCD_REG_74 0x4A

Definition at line 151 of file stm32100e_eval_lcd.h.

#define LCD_REG_75 0x4B

Definition at line 152 of file stm32100e_eval_lcd.h.

#define LCD_REG_76 0x4C

Definition at line 153 of file stm32100e_eval_lcd.h.

#define LCD_REG_77 0x4D

Definition at line 154 of file stm32100e_eval_lcd.h.

#define LCD_REG_78 0x4E

Definition at line 155 of file stm32100e_eval_lcd.h.

#define LCD_REG_79 0x4F

Definition at line 156 of file stm32100e_eval_lcd.h.

#define LCD_REG_8 0x08

Definition at line 93 of file stm32100e_eval_lcd.h.

#define LCD_REG_80 0x50

Definition at line 157 of file stm32100e_eval_lcd.h.

#define LCD_REG_81 0x51

Definition at line 158 of file stm32100e_eval_lcd.h.

#define LCD_REG_82 0x52

Definition at line 159 of file stm32100e_eval_lcd.h.

#define LCD_REG_83 0x53

Definition at line 160 of file stm32100e_eval_lcd.h.

#define LCD_REG_9 0x09

Definition at line 94 of file stm32100e_eval_lcd.h.

#define LCD_REG_96 0x60

Definition at line 161 of file stm32100e_eval_lcd.h.

#define LCD_REG_97 0x61

Definition at line 162 of file stm32100e_eval_lcd.h.


STM32F10x Standard Peripherals Firmware Library: STM32100E_EVAL_LCD_Exported_Macros

Defines

STM32100E_EVAL_LCD_Exported_Macros

STM32100E_EVAL_LCD

Defines

#define ASSEMBLE_RGB(R, G, B) ((((R)& 0xF8) << 8) | (((G) & 0xFC) << 3) | (((B) & 0xF8) >> 3))

Define Documentation

#define ASSEMBLE_RGB | ( | R,
 |  | G,
 |  | B
 | ) | ((((R)& 0xF8) << 8) | (((G) & 0xFC) << 3) | (((B) & 0xF8) >> 3))

Definition at line 267 of file stm32100e_eval_lcd.h.


STM32F10x Standard Peripherals Firmware Library: STM32100E_EVAL_LCD_Exported_Functions

STM32100E_EVAL_LCD_Exported_Functions

STM32100E_EVAL_LCD


STM32F10x Standard Peripherals Firmware Library: STM32100E_EVAL_FSMC_ONENAND_Private_Types

STM32100E_EVAL_FSMC_ONENAND_Private_Types

STM32100E_EVAL_FSMC_ONENAND


STM32F10x Standard Peripherals Firmware Library: STM32100E_EVAL_FSMC_ONENAND_Private_Defines

Defines

STM32100E_EVAL_FSMC_ONENAND_Private_Defines

STM32100E_EVAL_FSMC_ONENAND

Defines

#define | BANK1_ONENAND1_ADDR ((uint32_t)0x60000000)
#define | ONENAND_BOOTPARTITION_ADDR ((uint32_t)BANK1_ONENAND1_ADDR)

Define Documentation

#define BANK1_ONENAND1_ADDR ((uint32_t)0x60000000)

Definition at line 55 of file stm32100e_eval_fsmc_onenand.c.

Referenced by OneNAND_AsynchronousRead(), OneNAND_EraseBlock(), OneNAND_ReadControllerStatus(), OneNAND_ReadID(), OneNAND_ReadStatus(), OneNAND_SynchronousRead(), OneNAND_UnlockBlock(), and OneNAND_WriteBuffer().

#define ONENAND_BOOTPARTITION_ADDR ((uint32_t)BANK1_ONENAND1_ADDR)

Definition at line 56 of file stm32100e_eval_fsmc_onenand.c.

Referenced by OneNAND_Reset().


STM32F10x Standard Peripherals Firmware Library: STM32100E_EVAL_FSMC_ONENAND_Private_Macros

Defines

STM32100E_EVAL_FSMC_ONENAND_Private_Macros

STM32100E_EVAL_FSMC_ONENAND

Defines

#define OneNAND_WRITE(Address, Data) (*(__IO uint16_t *)(Address) = (Data))

Define Documentation

#define OneNAND_WRITE | ( | Address,
 |  | Data
 | ) | (*(__IO uint16_t *)(Address) = (Data))

Definition at line 66 of file stm32100e_eval_fsmc_onenand.c.

Referenced by OneNAND_AsynchronousRead(), OneNAND_Reset(), and OneNAND_SynchronousRead().


STM32F10x Standard Peripherals Firmware Library: STM32100E_EVAL_FSMC_ONENAND_Private_Variables

STM32100E_EVAL_FSMC_ONENAND_Private_Variables

STM32100E_EVAL_FSMC_ONENAND


STM32F10x Standard Peripherals Firmware Library: STM32100E_EVAL_FSMC_ONENAND_Private_Function_Prototypes

STM32100E_EVAL_FSMC_ONENAND_Private_Function_Prototypes

STM32100E_EVAL_FSMC_ONENAND


STM32F10x Standard Peripherals Firmware Library: STM32100E_EVAL_FSMC_ONENAND_Private_Functions

Functions

STM32100E_EVAL_FSMC_ONENAND_Private_Functions

STM32100E_EVAL_FSMC_ONENAND

Functions

void | OneNAND_AsynchronousRead (uint16_t *pBuffer, OneNAND_ADDRESS Address, uint32_t NumHalfwordToRead)
Reads a block of data from the OneNAND memory using asynchronous mode.
uint16_t | OneNAND_EraseBlock (uint32_t BlockNumber)
Erases the specified OneNAND memory block (128Kb).
void | OneNAND_Init (void)
Configures the FSMC and GPIOs to interface with the OneNAND memory.
uint16_t | OneNAND_ReadControllerStatus (void)
Reads the OneNAND Controller status.
void | OneNAND_ReadID (OneNAND_IDTypeDef *OneNAND_ID)
Reads OneNAND memory's Manufacturer and Device Code.
uint16_t | OneNAND_ReadStatus (void)
Reads the OneNAND memory Interrupt status.
void | OneNAND_Reset (void)
Resets the OneNAND memory.
void | OneNAND_SynchronousRead (uint16_t *pBuffer, OneNAND_ADDRESS Address, uint32_t NumHalfwordToRead)
Reads a block of data from the OneNAND memory using synchronous mode.
uint16_t | OneNAND_UnlockBlock (uint32_t BlockNumber)
Unlocks the specified OneNAND memory block (128Kb).
uint16_t | OneNAND_WriteBuffer (uint16_t *pBuffer, OneNAND_ADDRESS Address, uint32_t NumHalfwordToWrite)
Writes a Half-word buffer to the OneNAND memory.

Function Documentation

void OneNAND_AsynchronousRead | ( | uint16_t * | pBuffer,
 |  | OneNAND_ADDRESS | Address,
 |  | uint32_t | NumHalfwordToRead
 | ) |  |

Reads a block of data from the OneNAND memory using asynchronous mode.

Parameters:
pBuffer,: pointer to the buffer that receives the data read from the OneNAND memory.
ReadAddr,: OneNAND memory internal address to read from.
NumHalfwordToRead,: number of half-words to read.
Return values:
None

Definition at line 356 of file stm32100e_eval_fsmc_onenand.c.

References BANK1_ONENAND1_ADDR, OneNAND_ADDRESS::Block, index, OneNAND_CMD_LOAD, OneNAND_DATA_RAM_1_0_ADD, OneNAND_DATA_RAM_1_0_REG, OneNAND_REG_COMMAND, OneNAND_REG_CONTROLSTATUS, OneNAND_REG_INTERRUPT, OneNAND_REG_STARTADDRESINT8_T, OneNAND_REG_STARTADDRESS1, OneNAND_REG_STARTBUFFER, OneNAND_REG_SYSTEMCONFIGURATION, OneNAND_WRITE, OneNAND_ADDRESS::Page, and status.

Referenced by main().

uint16_t OneNAND_EraseBlock ( uint32_t BlockNumber )

Erases the specified OneNAND memory block (128Kb).

Parameters:
BlockNumber,: specifies the block number to be erased. This parameter should be between 0 and 511.
Return values:
OneNAND memory Interrupt Status.

Definition at line 261 of file stm32100e_eval_fsmc_onenand.c.

References BANK1_ONENAND1_ADDR, OneNAND_CMD_ERASE, OneNAND_REG_COMMAND, OneNAND_REG_CONTROLSTATUS, OneNAND_REG_INTERRUPT, OneNAND_REG_STARTADDRESS1, and status.

Referenced by main().

void OneNAND_Init ( void )

Configures the FSMC and GPIOs to interface with the OneNAND memory.

This function must be called before any write/read operation on the OneNAND.

Parameters:
None
Return values:
None

< OneNAND Data lines configuration

< OneNAND Address lines configuration

< CLK, NOE and NWE configuration

< NE1 configuration

< NL configuration

< NWAIT configuration

Definition at line 100 of file stm32100e_eval_fsmc_onenand.c.

References DISABLE, ENABLE, FSMC_NORSRAMTimingInitTypeDef::FSMC_AccessMode, FSMC_AccessMode_B, FSMC_NORSRAMTimingInitTypeDef::FSMC_AddressHoldTime, FSMC_NORSRAMTimingInitTypeDef::FSMC_AddressSetupTime, FSMC_NORSRAMInitTypeDef::FSMC_AsynchronousWait, FSMC_AsynchronousWait_Disable, FSMC_NORSRAMInitTypeDef::FSMC_Bank, FSMC_Bank1_NORSRAM1, FSMC_NORSRAMInitTypeDef::FSMC_BurstAccessMode, FSMC_BurstAccessMode_Enable, FSMC_NORSRAMTimingInitTypeDef::FSMC_BusTurnAroundDuration, FSMC_NORSRAMTimingInitTypeDef::FSMC_CLKDivision, FSMC_NORSRAMInitTypeDef::FSMC_DataAddressMux, FSMC_DataAddressMux_Disable, FSMC_NORSRAMTimingInitTypeDef::FSMC_DataLatency, FSMC_NORSRAMTimingInitTypeDef::FSMC_DataSetupTime, FSMC_NORSRAMInitTypeDef::FSMC_ExtendedMode, FSMC_ExtendedMode_Disable, FSMC_NORSRAMInitTypeDef::FSMC_MemoryDataWidth, FSMC_MemoryDataWidth_16b, FSMC_NORSRAMInitTypeDef::FSMC_MemoryType, FSMC_MemoryType_NOR, FSMC_NORSRAMCmd(), FSMC_NORSRAMInit(), FSMC_NORSRAMInitTypeDef::FSMC_ReadWriteTimingStruct, FSMC_NORSRAMInitTypeDef::FSMC_WaitSignal, FSMC_WaitSignal_Enable, FSMC_NORSRAMInitTypeDef::FSMC_WaitSignalActive, FSMC_WaitSignalActive_BeforeWaitState, FSMC_NORSRAMInitTypeDef::FSMC_WaitSignalPolarity, FSMC_WaitSignalPolarity_Low, FSMC_NORSRAMInitTypeDef::FSMC_WrapMode, FSMC_WrapMode_Disable, FSMC_NORSRAMInitTypeDef::FSMC_WriteBurst, FSMC_WriteBurst_Disable, FSMC_NORSRAMInitTypeDef::FSMC_WriteOperation, FSMC_WriteOperation_Enable, FSMC_NORSRAMInitTypeDef::FSMC_WriteTimingStruct, GPIO_Init(), GPIO_InitStructure, GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_AF_PP, GPIO_Mode_IN_FLOATING, GPIO_InitTypeDef::GPIO_Pin, GPIO_Pin_0, GPIO_Pin_1, GPIO_Pin_10, GPIO_Pin_11, GPIO_Pin_12, GPIO_Pin_13, GPIO_Pin_14, GPIO_Pin_15, GPIO_Pin_2, GPIO_Pin_3, GPIO_Pin_4, GPIO_Pin_5, GPIO_Pin_6, GPIO_Pin_7, GPIO_Pin_8, GPIO_Pin_9, GPIO_PinRemapConfig(), GPIO_Remap_FSMC_NADV, GPIO_InitTypeDef::GPIO_Speed, GPIO_Speed_50MHz, GPIOB, GPIOD, GPIOE, GPIOF, GPIOG, RCC_AHBPeriph_FSMC, RCC_AHBPeriphClockCmd(), RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOB, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE, RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, and RCC_APB2PeriphClockCmd().

Referenced by main().

uint16_t OneNAND_ReadControllerStatus ( void )

Reads the OneNAND Controller status.

Parameters:
None
Return values:
OneNAND Controller Status.

Definition at line 454 of file stm32100e_eval_fsmc_onenand.c.

References BANK1_ONENAND1_ADDR, OneNAND_REG_CONTROLSTATUS, and status.

void OneNAND_ReadID ( OneNAND_IDTypeDef * OneNAND_ID )

Reads OneNAND memory's Manufacturer and Device Code.

Parameters:
OneNAND_ID,: pointer to a OneNAND_IDTypeDef structure which will hold the Manufacturer and Device Code.
Return values:
None

Definition at line 200 of file stm32100e_eval_fsmc_onenand.c.

References BANK1_ONENAND1_ADDR, OneNAND_IDTypeDef::Device_ID, OneNAND_IDTypeDef::Manufacturer_ID, OneNAND_REG_CONTROLSTATUS, OneNAND_REG_DEVICEID, OneNAND_REG_MANUFACTERID, OneNAND_REG_SYSTEMCONFIGURATION, and status.

Referenced by main().

uint16_t OneNAND_ReadStatus ( void )

Reads the OneNAND memory Interrupt status.

Parameters:
None
Return values:
OneNAND memory Interrupt Status.

Definition at line 441 of file stm32100e_eval_fsmc_onenand.c.

References BANK1_ONENAND1_ADDR, OneNAND_REG_INTERRUPT, and status.

void OneNAND_Reset ( void )

Resets the OneNAND memory.

Parameters:
None
Return values:
None

Definition at line 189 of file stm32100e_eval_fsmc_onenand.c.

References ONENAND_BOOTPARTITION_ADDR, OneNAND_CMD_RESET, and OneNAND_WRITE.

void OneNAND_SynchronousRead | ( | uint16_t * | pBuffer,
 |  | OneNAND_ADDRESS | Address,
 |  | uint32_t | NumHalfwordToRead
 | ) |  |

Reads a block of data from the OneNAND memory using synchronous mode.

Parameters:
pBuffer,: pointer to the buffer that receives the data read from the OneNAND memory.
ReadAddr,: OneNAND memory internal address to read from.
NumHalfwordToRead,: number of half-words to read.
Return values:
None

Definition at line 401 of file stm32100e_eval_fsmc_onenand.c.

References BANK1_ONENAND1_ADDR, OneNAND_ADDRESS::Block, index, OneNAND_CMD_LOAD, OneNAND_DATA_RAM_1_0_ADD, OneNAND_DATA_RAM_1_0_REG, OneNAND_REG_COMMAND, OneNAND_REG_CONTROLSTATUS, OneNAND_REG_INTERRUPT, OneNAND_REG_STARTADDRESINT8_T, OneNAND_REG_STARTADDRESS1, OneNAND_REG_STARTBUFFER, OneNAND_REG_SYSTEMCONFIGURATION, OneNAND_WRITE, OneNAND_ADDRESS::Page, and status.

Referenced by main().

uint16_t OneNAND_UnlockBlock ( uint32_t BlockNumber )

Unlocks the specified OneNAND memory block (128Kb).

Parameters:
BlockNumber,: specifies the block number to be erased. This parameter should be between 0 and 511.
Return values:
OneNAND memory Interrupt Status.

Definition at line 225 of file stm32100e_eval_fsmc_onenand.c.

References BANK1_ONENAND1_ADDR, OneNAND_CMD_UNLOCK, OneNAND_REG_COMMAND, OneNAND_REG_CONTROLSTATUS, OneNAND_REG_INTERRUPT, OneNAND_REG_STARTBLOCKADDRESS, and status.

Referenced by main().

uint16_t OneNAND_WriteBuffer | ( | uint16_t * | pBuffer,
 |  | OneNAND_ADDRESS | Address,
 |  | uint32_t | NumHalfwordToWrite
 | ) |  |

Writes a Half-word buffer to the OneNAND memory.

Parameters:
pBuffer,: pointer to buffer.
WriteAddr,: OneNAND memory internal address from which the data will be written.
NumHalfwordToWrite,: number of half-words to write.
Return values:
OneNAND memory Controller Status.

Definition at line 308 of file stm32100e_eval_fsmc_onenand.c.

References BANK1_ONENAND1_ADDR, OneNAND_ADDRESS::Block, OneNAND_CMD_PROGRAM, OneNAND_DATA_RAM_0_0_ADD, OneNAND_DATA_RAM_0_0_REG, OneNAND_REG_COMMAND, OneNAND_REG_CONTROLSTATUS, OneNAND_REG_INTERRUPT, OneNAND_REG_STARTADDRESINT8_T, OneNAND_REG_STARTADDRESS1, OneNAND_REG_STARTBUFFER, OneNAND_ADDRESS::Page, and status.

Referenced by main().


STM32F10x Standard Peripherals Firmware Library: STM32100E_EVAL_FSMC_ONENAND_Exported_Types

Data Structures | Enumerations

STM32100E_EVAL_FSMC_ONENAND_Exported_Types

STM32100E_EVAL_FSMC_ONENAND

Data Structures

struct | OneNAND_ADDRESS
struct | OneNAND_IDTypeDef

Enumerations

enum | OneNAND_Status { OneNAND_SUCCESS = 0, OneNAND_ONGOING, OneNAND_ERROR, OneNAND_TIMEOUT }

Enumeration Type Documentation

enum OneNAND_Status
Enumerator:
OneNAND_SUCCESS
OneNAND_ONGOING
OneNAND_ERROR
OneNAND_TIMEOUT

Definition at line 60 of file stm32100e_eval_fsmc_onenand.h.


STM32F10x Standard Peripherals Firmware Library: OneNAND_ADDRESS Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

OneNAND_ADDRESS Struct Reference
STM32100E_EVAL_FSMC_ONENAND_Exported_Types

#include <stm32100e_eval_fsmc_onenand.h>

Data Fields

uint16_t | Block
uint16_t | Page

Detailed Description

Definition at line 68 of file stm32100e_eval_fsmc_onenand.h.

Field Documentation

uint16_t OneNAND_ADDRESS::Block

Definition at line 70 of file stm32100e_eval_fsmc_onenand.h.

Referenced by main(), OneNAND_AsynchronousRead(), OneNAND_SynchronousRead(), and OneNAND_WriteBuffer().

uint16_t OneNAND_ADDRESS::Page

Definition at line 71 of file stm32100e_eval_fsmc_onenand.h.

Referenced by main(), OneNAND_AsynchronousRead(), OneNAND_SynchronousRead(), and OneNAND_WriteBuffer().

The documentation for this struct was generated from the following file:
  • stm32100e_eval_fsmc_onenand.h


STM32F10x Standard Peripherals Firmware Library: OneNAND_IDTypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

OneNAND_IDTypeDef Struct Reference
STM32100E_EVAL_FSMC_ONENAND_Exported_Types

#include <stm32100e_eval_fsmc_onenand.h>

Data Fields

uint16_t | Device_ID
uint16_t | Manufacturer_ID

Detailed Description

Definition at line 53 of file stm32100e_eval_fsmc_onenand.h.

Field Documentation

uint16_t OneNAND_IDTypeDef::Device_ID

Definition at line 56 of file stm32100e_eval_fsmc_onenand.h.

Referenced by main(), and OneNAND_ReadID().

uint16_t OneNAND_IDTypeDef::Manufacturer_ID

Definition at line 55 of file stm32100e_eval_fsmc_onenand.h.

Referenced by main(), and OneNAND_ReadID().

The documentation for this struct was generated from the following file:
  • stm32100e_eval_fsmc_onenand.h


STM32F10x Standard Peripherals Firmware Library: STM32100E_EVAL_FSMC_ONENAND_Exported_Constants

Defines

STM32100E_EVAL_FSMC_ONENAND_Exported_Constants

STM32100E_EVAL_FSMC_ONENAND

Defines

#define | OneNAND_CMD_ERASE ((uint16_t)0x0094)
OneNAND memory command.
#define | OneNAND_CMD_LOAD ((uint16_t)0x0000)
#define | OneNAND_CMD_PROGRAM ((uint16_t)0x0080)
#define | OneNAND_CMD_READ_ID ((uint16_t)0x0090)
#define | OneNAND_CMD_RESET ((uint16_t)0x00F0)
#define | OneNAND_CMD_UNLOCK ((uint16_t)0x0023)
#define | OneNAND_DATA_RAM_0_0_ADD ((uint32_t)0x0400)
OneNand Memory partition description.
#define | OneNAND_DATA_RAM_0_0_REG ((uint32_t)0x0800)
#define | OneNAND_DATA_RAM_0_1_ADD ((uint32_t)0x0600)
#define | OneNAND_DATA_RAM_0_1_REG ((uint32_t)0x0900)
#define | OneNAND_DATA_RAM_0_2_ADD ((uint32_t)0x0800)
#define | OneNAND_DATA_RAM_0_2_REG ((uint32_t)0x0A00)
#define | OneNAND_DATA_RAM_0_3_ADD ((uint32_t)0x0A00)
#define | OneNAND_DATA_RAM_0_3_REG ((uint32_t)0x0B00)
#define | OneNAND_DATA_RAM_1_0_ADD ((uint32_t)0x0C00)
#define | OneNAND_DATA_RAM_1_0_REG ((uint32_t)0x0C00)
#define | OneNAND_DATA_RAM_1_1_ADD ((uint32_t)0x0E00)
#define | OneNAND_DATA_RAM_1_1_REG ((uint32_t)0x0D00)
#define | OneNAND_DATA_RAM_1_2_ADD ((uint32_t)0x1000)
#define | OneNAND_DATA_RAM_1_2_REG ((uint32_t)0x0E00)
#define | OneNAND_DATA_RAM_1_3_ADD ((uint32_t)0x1200)
#define | OneNAND_DATA_RAM_1_3_REG ((uint32_t)0x0F00)
#define | OneNAND_REG_AMOUNTOFBUFFERS ((uint32_t)0x1E00A)
#define | OneNAND_REG_BOOTBUFFERSIZE ((uint32_t)0x1E008)
#define | OneNAND_REG_COMMAND ((uint32_t)0x1E440)
#define | OneNAND_REG_CONTROLSTATUS ((uint32_t)0x1E480)
#define | OneNAND_REG_DATABUFFERSIZE ((uint32_t)0x1E006)
#define | OneNAND_REG_DEVICEID ((uint32_t)0x1E002)
#define | OneNAND_REG_INTERRUPT ((uint32_t)0x1E482)
#define | OneNAND_REG_MANUFACTERID ((uint32_t)0x1E000)
OneNand Register description.
#define | OneNAND_REG_STARTADDRESINT8_T ((uint32_t)0x1E20E)
#define | OneNAND_REG_STARTADDRESS1 ((uint32_t)0x1E200)
#define | OneNAND_REG_STARTADDRESS3 ((uint32_t)0x1E204)
#define | OneNAND_REG_STARTADDRESS4 ((uint32_t)0x1E206)
#define | OneNAND_REG_STARTBLOCKADDRESS ((uint32_t)0x1E498)
#define | OneNAND_REG_STARTBUFFER ((uint32_t)0x1E400)
#define | OneNAND_REG_SYSTEMCONFIGURATION ((uint32_t)0x1E442)
#define | OneNAND_REG_TECHNOLOGY ((uint32_t)0x1E00C)
#define | OneNAND_REG_WRITEPROTECTIONSTATUS ((uint32_t)0x1E49C)

Define Documentation

#define OneNAND_CMD_ERASE ((uint16_t)0x0094)

OneNAND memory command.

Definition at line 83 of file stm32100e_eval_fsmc_onenand.h.

Referenced by OneNAND_EraseBlock().

#define OneNAND_CMD_LOAD ((uint16_t)0x0000)

Definition at line 88 of file stm32100e_eval_fsmc_onenand.h.

Referenced by OneNAND_AsynchronousRead(), and OneNAND_SynchronousRead().

#define OneNAND_CMD_PROGRAM ((uint16_t)0x0080)

Definition at line 84 of file stm32100e_eval_fsmc_onenand.h.

Referenced by OneNAND_WriteBuffer().

#define OneNAND_CMD_READ_ID ((uint16_t)0x0090)

Definition at line 86 of file stm32100e_eval_fsmc_onenand.h.

#define OneNAND_CMD_RESET ((uint16_t)0x00F0)

Definition at line 85 of file stm32100e_eval_fsmc_onenand.h.

Referenced by OneNAND_Reset().

#define OneNAND_CMD_UNLOCK ((uint16_t)0x0023)

Definition at line 87 of file stm32100e_eval_fsmc_onenand.h.

Referenced by OneNAND_UnlockBlock().

#define OneNAND_DATA_RAM_0_0_ADD ((uint32_t)0x0400)

OneNand Memory partition description.

Definition at line 115 of file stm32100e_eval_fsmc_onenand.h.

Referenced by OneNAND_WriteBuffer().

#define OneNAND_DATA_RAM_0_0_REG ((uint32_t)0x0800)

Definition at line 116 of file stm32100e_eval_fsmc_onenand.h.

Referenced by OneNAND_WriteBuffer().

#define OneNAND_DATA_RAM_0_1_ADD ((uint32_t)0x0600)

Definition at line 118 of file stm32100e_eval_fsmc_onenand.h.

#define OneNAND_DATA_RAM_0_1_REG ((uint32_t)0x0900)

Definition at line 119 of file stm32100e_eval_fsmc_onenand.h.

#define OneNAND_DATA_RAM_0_2_ADD ((uint32_t)0x0800)

Definition at line 121 of file stm32100e_eval_fsmc_onenand.h.

#define OneNAND_DATA_RAM_0_2_REG ((uint32_t)0x0A00)

Definition at line 122 of file stm32100e_eval_fsmc_onenand.h.

#define OneNAND_DATA_RAM_0_3_ADD ((uint32_t)0x0A00)

Definition at line 124 of file stm32100e_eval_fsmc_onenand.h.

#define OneNAND_DATA_RAM_0_3_REG ((uint32_t)0x0B00)

Definition at line 125 of file stm32100e_eval_fsmc_onenand.h.

#define OneNAND_DATA_RAM_1_0_ADD ((uint32_t)0x0C00)

Definition at line 127 of file stm32100e_eval_fsmc_onenand.h.

Referenced by OneNAND_AsynchronousRead(), and OneNAND_SynchronousRead().

#define OneNAND_DATA_RAM_1_0_REG ((uint32_t)0x0C00)

Definition at line 128 of file stm32100e_eval_fsmc_onenand.h.

Referenced by OneNAND_AsynchronousRead(), and OneNAND_SynchronousRead().

#define OneNAND_DATA_RAM_1_1_ADD ((uint32_t)0x0E00)

Definition at line 130 of file stm32100e_eval_fsmc_onenand.h.

#define OneNAND_DATA_RAM_1_1_REG ((uint32_t)0x0D00)

Definition at line 131 of file stm32100e_eval_fsmc_onenand.h.

#define OneNAND_DATA_RAM_1_2_ADD ((uint32_t)0x1000)

Definition at line 133 of file stm32100e_eval_fsmc_onenand.h.

#define OneNAND_DATA_RAM_1_2_REG ((uint32_t)0x0E00)

Definition at line 134 of file stm32100e_eval_fsmc_onenand.h.

#define OneNAND_DATA_RAM_1_3_ADD ((uint32_t)0x1200)

Definition at line 136 of file stm32100e_eval_fsmc_onenand.h.

#define OneNAND_DATA_RAM_1_3_REG ((uint32_t)0x0F00)

Definition at line 137 of file stm32100e_eval_fsmc_onenand.h.

#define OneNAND_REG_AMOUNTOFBUFFERS ((uint32_t)0x1E00A)

Definition at line 97 of file stm32100e_eval_fsmc_onenand.h.

#define OneNAND_REG_BOOTBUFFERSIZE ((uint32_t)0x1E008)

Definition at line 96 of file stm32100e_eval_fsmc_onenand.h.

#define OneNAND_REG_COMMAND ((uint32_t)0x1E440)

Definition at line 105 of file stm32100e_eval_fsmc_onenand.h.

Referenced by OneNAND_AsynchronousRead(), OneNAND_EraseBlock(), OneNAND_SynchronousRead(), OneNAND_UnlockBlock(), and OneNAND_WriteBuffer().

#define OneNAND_REG_CONTROLSTATUS ((uint32_t)0x1E480)

Definition at line 107 of file stm32100e_eval_fsmc_onenand.h.

Referenced by OneNAND_AsynchronousRead(), OneNAND_EraseBlock(), OneNAND_ReadControllerStatus(), OneNAND_ReadID(), OneNAND_SynchronousRead(), OneNAND_UnlockBlock(), and OneNAND_WriteBuffer().

#define OneNAND_REG_DATABUFFERSIZE ((uint32_t)0x1E006)

Definition at line 95 of file stm32100e_eval_fsmc_onenand.h.

#define OneNAND_REG_DEVICEID ((uint32_t)0x1E002)

Definition at line 94 of file stm32100e_eval_fsmc_onenand.h.

Referenced by OneNAND_ReadID().

#define OneNAND_REG_INTERRUPT ((uint32_t)0x1E482)

Definition at line 108 of file stm32100e_eval_fsmc_onenand.h.

Referenced by OneNAND_AsynchronousRead(), OneNAND_EraseBlock(), OneNAND_ReadStatus(), OneNAND_SynchronousRead(), OneNAND_UnlockBlock(), and OneNAND_WriteBuffer().

#define OneNAND_REG_MANUFACTERID ((uint32_t)0x1E000)

OneNand Register description.

Definition at line 93 of file stm32100e_eval_fsmc_onenand.h.

Referenced by OneNAND_ReadID().

#define OneNAND_REG_STARTADDRESINT8_T ((uint32_t)0x1E20E)

Definition at line 102 of file stm32100e_eval_fsmc_onenand.h.

Referenced by OneNAND_AsynchronousRead(), OneNAND_SynchronousRead(), and OneNAND_WriteBuffer().

#define OneNAND_REG_STARTADDRESS1 ((uint32_t)0x1E200)

Definition at line 99 of file stm32100e_eval_fsmc_onenand.h.

Referenced by OneNAND_AsynchronousRead(), OneNAND_EraseBlock(), OneNAND_SynchronousRead(), and OneNAND_WriteBuffer().

#define OneNAND_REG_STARTADDRESS3 ((uint32_t)0x1E204)

Definition at line 100 of file stm32100e_eval_fsmc_onenand.h.

#define OneNAND_REG_STARTADDRESS4 ((uint32_t)0x1E206)

Definition at line 101 of file stm32100e_eval_fsmc_onenand.h.

#define OneNAND_REG_STARTBLOCKADDRESS ((uint32_t)0x1E498)

Definition at line 109 of file stm32100e_eval_fsmc_onenand.h.

Referenced by OneNAND_UnlockBlock().

#define OneNAND_REG_STARTBUFFER ((uint32_t)0x1E400)

Definition at line 103 of file stm32100e_eval_fsmc_onenand.h.

Referenced by OneNAND_AsynchronousRead(), OneNAND_SynchronousRead(), and OneNAND_WriteBuffer().

#define OneNAND_REG_SYSTEMCONFIGURATION ((uint32_t)0x1E442)

Definition at line 106 of file stm32100e_eval_fsmc_onenand.h.

Referenced by OneNAND_AsynchronousRead(), OneNAND_ReadID(), and OneNAND_SynchronousRead().

#define OneNAND_REG_TECHNOLOGY ((uint32_t)0x1E00C)

Definition at line 98 of file stm32100e_eval_fsmc_onenand.h.

#define OneNAND_REG_WRITEPROTECTIONSTATUS ((uint32_t)0x1E49C)

Definition at line 110 of file stm32100e_eval_fsmc_onenand.h.


STM32F10x Standard Peripherals Firmware Library: STM32100E_EVAL_FSMC_ONENAND_Exported_Macros

STM32100E_EVAL_FSMC_ONENAND_Exported_Macros

STM32100E_EVAL_FSMC_ONENAND


STM32F10x Standard Peripherals Firmware Library: STM32100E_EVAL_FSMC_ONENAND_Exported_Functions

Functions

STM32100E_EVAL_FSMC_ONENAND_Exported_Functions

STM32100E_EVAL_FSMC_ONENAND

Functions

void | OneNAND_AsynchronousRead (uint16_t *pBuffer, OneNAND_ADDRESS Address, uint32_t NumHalfwordToRead)
Reads a block of data from the OneNAND memory using asynchronous mode.
uint16_t | OneNAND_EraseBlock (uint32_t BlockNumber)
Erases the specified OneNAND memory block (128Kb).
void | OneNAND_Init (void)
Configures the FSMC and GPIOs to interface with the OneNAND memory.
uint16_t | OneNAND_ReadControllerStatus (void)
Reads the OneNAND Controller status.
void | OneNAND_ReadID (OneNAND_IDTypeDef *OneNAND_ID)
Reads OneNAND memory's Manufacturer and Device Code.
uint16_t | OneNAND_ReadStatus (void)
Reads the OneNAND memory Interrupt status.
void | OneNAND_Reset (void)
Resets the OneNAND memory.
void | OneNAND_SynchronousRead (uint16_t *pBuffer, OneNAND_ADDRESS Address, uint32_t NumHalfwordToRead)
Reads a block of data from the OneNAND memory using synchronous mode.
uint16_t | OneNAND_UnlockBlock (uint32_t BlockNumber)
Unlocks the specified OneNAND memory block (128Kb).
uint16_t | OneNAND_WriteBuffer (uint16_t *pBuffer, OneNAND_ADDRESS Address, uint32_t NumHalfwordToWrite)
Writes a Half-word buffer to the OneNAND memory.

Function Documentation

void OneNAND_AsynchronousRead | ( | uint16_t * | pBuffer,
 |  | OneNAND_ADDRESS | Address,
 |  | uint32_t | NumHalfwordToRead
 | ) |  |

Reads a block of data from the OneNAND memory using asynchronous mode.

Parameters:
pBuffer,: pointer to the buffer that receives the data read from the OneNAND memory.
ReadAddr,: OneNAND memory internal address to read from.
NumHalfwordToRead,: number of half-words to read.
Return values:
None

Definition at line 356 of file stm32100e_eval_fsmc_onenand.c.

References BANK1_ONENAND1_ADDR, OneNAND_ADDRESS::Block, index, OneNAND_CMD_LOAD, OneNAND_DATA_RAM_1_0_ADD, OneNAND_DATA_RAM_1_0_REG, OneNAND_REG_COMMAND, OneNAND_REG_CONTROLSTATUS, OneNAND_REG_INTERRUPT, OneNAND_REG_STARTADDRESINT8_T, OneNAND_REG_STARTADDRESS1, OneNAND_REG_STARTBUFFER, OneNAND_REG_SYSTEMCONFIGURATION, OneNAND_WRITE, OneNAND_ADDRESS::Page, and status.

Referenced by main().

uint16_t OneNAND_EraseBlock ( uint32_t BlockNumber )

Erases the specified OneNAND memory block (128Kb).

Parameters:
BlockNumber,: specifies the block number to be erased. This parameter should be between 0 and 511.
Return values:
OneNAND memory Interrupt Status.

Definition at line 261 of file stm32100e_eval_fsmc_onenand.c.

References BANK1_ONENAND1_ADDR, OneNAND_CMD_ERASE, OneNAND_REG_COMMAND, OneNAND_REG_CONTROLSTATUS, OneNAND_REG_INTERRUPT, OneNAND_REG_STARTADDRESS1, and status.

Referenced by main().

void OneNAND_Init ( void )

Configures the FSMC and GPIOs to interface with the OneNAND memory.

This function must be called before any write/read operation on the OneNAND.

Parameters:
None
Return values:
None

< OneNAND Data lines configuration

< OneNAND Address lines configuration

< CLK, NOE and NWE configuration

< NE1 configuration

< NL configuration

< NWAIT configuration

Definition at line 100 of file stm32100e_eval_fsmc_onenand.c.

References DISABLE, ENABLE, FSMC_NORSRAMTimingInitTypeDef::FSMC_AccessMode, FSMC_AccessMode_B, FSMC_NORSRAMTimingInitTypeDef::FSMC_AddressHoldTime, FSMC_NORSRAMTimingInitTypeDef::FSMC_AddressSetupTime, FSMC_NORSRAMInitTypeDef::FSMC_AsynchronousWait, FSMC_AsynchronousWait_Disable, FSMC_NORSRAMInitTypeDef::FSMC_Bank, FSMC_Bank1_NORSRAM1, FSMC_NORSRAMInitTypeDef::FSMC_BurstAccessMode, FSMC_BurstAccessMode_Enable, FSMC_NORSRAMTimingInitTypeDef::FSMC_BusTurnAroundDuration, FSMC_NORSRAMTimingInitTypeDef::FSMC_CLKDivision, FSMC_NORSRAMInitTypeDef::FSMC_DataAddressMux, FSMC_DataAddressMux_Disable, FSMC_NORSRAMTimingInitTypeDef::FSMC_DataLatency, FSMC_NORSRAMTimingInitTypeDef::FSMC_DataSetupTime, FSMC_NORSRAMInitTypeDef::FSMC_ExtendedMode, FSMC_ExtendedMode_Disable, FSMC_NORSRAMInitTypeDef::FSMC_MemoryDataWidth, FSMC_MemoryDataWidth_16b, FSMC_NORSRAMInitTypeDef::FSMC_MemoryType, FSMC_MemoryType_NOR, FSMC_NORSRAMCmd(), FSMC_NORSRAMInit(), FSMC_NORSRAMInitTypeDef::FSMC_ReadWriteTimingStruct, FSMC_NORSRAMInitTypeDef::FSMC_WaitSignal, FSMC_WaitSignal_Enable, FSMC_NORSRAMInitTypeDef::FSMC_WaitSignalActive, FSMC_WaitSignalActive_BeforeWaitState, FSMC_NORSRAMInitTypeDef::FSMC_WaitSignalPolarity, FSMC_WaitSignalPolarity_Low, FSMC_NORSRAMInitTypeDef::FSMC_WrapMode, FSMC_WrapMode_Disable, FSMC_NORSRAMInitTypeDef::FSMC_WriteBurst, FSMC_WriteBurst_Disable, FSMC_NORSRAMInitTypeDef::FSMC_WriteOperation, FSMC_WriteOperation_Enable, FSMC_NORSRAMInitTypeDef::FSMC_WriteTimingStruct, GPIO_Init(), GPIO_InitStructure, GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_AF_PP, GPIO_Mode_IN_FLOATING, GPIO_InitTypeDef::GPIO_Pin, GPIO_Pin_0, GPIO_Pin_1, GPIO_Pin_10, GPIO_Pin_11, GPIO_Pin_12, GPIO_Pin_13, GPIO_Pin_14, GPIO_Pin_15, GPIO_Pin_2, GPIO_Pin_3, GPIO_Pin_4, GPIO_Pin_5, GPIO_Pin_6, GPIO_Pin_7, GPIO_Pin_8, GPIO_Pin_9, GPIO_PinRemapConfig(), GPIO_Remap_FSMC_NADV, GPIO_InitTypeDef::GPIO_Speed, GPIO_Speed_50MHz, GPIOB, GPIOD, GPIOE, GPIOF, GPIOG, RCC_AHBPeriph_FSMC, RCC_AHBPeriphClockCmd(), RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOB, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE, RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, and RCC_APB2PeriphClockCmd().

Referenced by main().

uint16_t OneNAND_ReadControllerStatus ( void )

Reads the OneNAND Controller status.

Parameters:
None
Return values:
OneNAND Controller Status.

Definition at line 454 of file stm32100e_eval_fsmc_onenand.c.

References BANK1_ONENAND1_ADDR, OneNAND_REG_CONTROLSTATUS, and status.

void OneNAND_ReadID ( OneNAND_IDTypeDef * OneNAND_ID )

Reads OneNAND memory's Manufacturer and Device Code.

Parameters:
OneNAND_ID,: pointer to a OneNAND_IDTypeDef structure which will hold the Manufacturer and Device Code.
Return values:
None

Definition at line 200 of file stm32100e_eval_fsmc_onenand.c.

References BANK1_ONENAND1_ADDR, OneNAND_IDTypeDef::Device_ID, OneNAND_IDTypeDef::Manufacturer_ID, OneNAND_REG_CONTROLSTATUS, OneNAND_REG_DEVICEID, OneNAND_REG_MANUFACTERID, OneNAND_REG_SYSTEMCONFIGURATION, and status.

Referenced by main().

uint16_t OneNAND_ReadStatus ( void )

Reads the OneNAND memory Interrupt status.

Parameters:
None
Return values:
OneNAND memory Interrupt Status.

Definition at line 441 of file stm32100e_eval_fsmc_onenand.c.

References BANK1_ONENAND1_ADDR, OneNAND_REG_INTERRUPT, and status.

void OneNAND_Reset ( void )

Resets the OneNAND memory.

Parameters:
None
Return values:
None

Definition at line 189 of file stm32100e_eval_fsmc_onenand.c.

References ONENAND_BOOTPARTITION_ADDR, OneNAND_CMD_RESET, and OneNAND_WRITE.

void OneNAND_SynchronousRead | ( | uint16_t * | pBuffer,
 |  | OneNAND_ADDRESS | Address,
 |  | uint32_t | NumHalfwordToRead
 | ) |  |

Reads a block of data from the OneNAND memory using synchronous mode.

Parameters:
pBuffer,: pointer to the buffer that receives the data read from the OneNAND memory.
ReadAddr,: OneNAND memory internal address to read from.
NumHalfwordToRead,: number of half-words to read.
Return values:
None

Definition at line 401 of file stm32100e_eval_fsmc_onenand.c.

References BANK1_ONENAND1_ADDR, OneNAND_ADDRESS::Block, index, OneNAND_CMD_LOAD, OneNAND_DATA_RAM_1_0_ADD, OneNAND_DATA_RAM_1_0_REG, OneNAND_REG_COMMAND, OneNAND_REG_CONTROLSTATUS, OneNAND_REG_INTERRUPT, OneNAND_REG_STARTADDRESINT8_T, OneNAND_REG_STARTADDRESS1, OneNAND_REG_STARTBUFFER, OneNAND_REG_SYSTEMCONFIGURATION, OneNAND_WRITE, OneNAND_ADDRESS::Page, and status.

Referenced by main().

uint16_t OneNAND_UnlockBlock ( uint32_t BlockNumber )

Unlocks the specified OneNAND memory block (128Kb).

Parameters:
BlockNumber,: specifies the block number to be erased. This parameter should be between 0 and 511.
Return values:
OneNAND memory Interrupt Status.

Definition at line 225 of file stm32100e_eval_fsmc_onenand.c.

References BANK1_ONENAND1_ADDR, OneNAND_CMD_UNLOCK, OneNAND_REG_COMMAND, OneNAND_REG_CONTROLSTATUS, OneNAND_REG_INTERRUPT, OneNAND_REG_STARTBLOCKADDRESS, and status.

Referenced by main().

uint16_t OneNAND_WriteBuffer | ( | uint16_t * | pBuffer,
 |  | OneNAND_ADDRESS | Address,
 |  | uint32_t | NumHalfwordToWrite
 | ) |  |

Writes a Half-word buffer to the OneNAND memory.

Parameters:
pBuffer,: pointer to buffer.
WriteAddr,: OneNAND memory internal address from which the data will be written.
NumHalfwordToWrite,: number of half-words to write.
Return values:
OneNAND memory Controller Status.

Definition at line 308 of file stm32100e_eval_fsmc_onenand.c.

References BANK1_ONENAND1_ADDR, OneNAND_ADDRESS::Block, OneNAND_CMD_PROGRAM, OneNAND_DATA_RAM_0_0_ADD, OneNAND_DATA_RAM_0_0_REG, OneNAND_REG_COMMAND, OneNAND_REG_CONTROLSTATUS, OneNAND_REG_INTERRUPT, OneNAND_REG_STARTADDRESINT8_T, OneNAND_REG_STARTADDRESS1, OneNAND_REG_STARTBUFFER, OneNAND_ADDRESS::Page, and status.

Referenced by main().


STM32F10x Standard Peripherals Firmware Library: STM32100E_EVAL_FSMC_SRAM_Private_Types

STM32100E_EVAL_FSMC_SRAM_Private_Types

STM32100E_EVAL_FSMC_SRAM


STM32F10x Standard Peripherals Firmware Library: STM32100E_EVAL_FSMC_SRAM_Private_Defines

Defines

STM32100E_EVAL_FSMC_SRAM_Private_Defines

STM32100E_EVAL_FSMC_SRAM

Defines

#define Bank1_SRAM3_ADDR ((uint32_t)0x68000000)
FSMC Bank 1 NOR/SRAM3.

Define Documentation

#define Bank1_SRAM3_ADDR ((uint32_t)0x68000000)

FSMC Bank 1 NOR/SRAM3.

Definition at line 58 of file stm32100e_eval_fsmc_sram.c.

Referenced by SRAM_ReadBuffer(), and SRAM_WriteBuffer().


STM32F10x Standard Peripherals Firmware Library: STM32100E_EVAL_FSMC_SRAM_Private_Macros

STM32100E_EVAL_FSMC_SRAM_Private_Macros

STM32100E_EVAL_FSMC_SRAM


STM32F10x Standard Peripherals Firmware Library: STM32100E_EVAL_FSMC_SRAM_Private_Variables

STM32100E_EVAL_FSMC_SRAM_Private_Variables

STM32100E_EVAL_FSMC_SRAM


STM32F10x Standard Peripherals Firmware Library: STM32100E_EVAL_FSMC_SRAM_Private_Function_Prototypes

STM32100E_EVAL_FSMC_SRAM_Private_Function_Prototypes

STM32100E_EVAL_FSMC_SRAM


STM32F10x Standard Peripherals Firmware Library: STM32100E_EVAL_FSMC_SRAM_Private_Functions

Functions

STM32100E_EVAL_FSMC_SRAM_Private_Functions

STM32100E_EVAL_FSMC_SRAM

Functions

void | SRAM_Init (void)
Configures the FSMC and GPIOs to interface with the SRAM memory.
void | SRAM_ReadBuffer (uint16_t *pBuffer, uint32_t ReadAddr, uint32_t NumHalfwordToRead)
Reads a block of data from the FSMC SRAM memory.
void | SRAM_WriteBuffer (uint16_t *pBuffer, uint32_t WriteAddr, uint32_t NumHalfwordToWrite)
Writes a Half-word buffer to the FSMC SRAM memory.

Function Documentation

void SRAM_Init ( void )

Configures the FSMC and GPIOs to interface with the SRAM memory.

This function must be called before any write/read operation on the SRAM.

Parameters:
None
Return values:
None

< SRAM Data lines configuration

< SRAM Address lines configuration

< NOE and NWE configuration

< NE3 configuration

< NBL0, NBL1 configuration

< Enable FSMC Bank1_SRAM Bank

Definition at line 99 of file stm32100e_eval_fsmc_sram.c.

Referenced by main().

void SRAM_ReadBuffer | ( | uint16_t * | pBuffer,
 |  | uint32_t | ReadAddr,
 |  | uint32_t | NumHalfwordToRead
 | ) |  |

Reads a block of data from the FSMC SRAM memory.

Parameters:
pBuffer | : pointer to the buffer that receives the data read from the SRAM memory.
ReadAddr | : SRAM memory internal address to read from.
NumHalfwordToRead | : number of half-words to read.
Return values:
None

< while there is data to read

< Read a half-word from the memory

< Increment the address

Definition at line 205 of file stm32100e_eval_fsmc_sram.c.

Referenced by main().

void SRAM_WriteBuffer | ( | uint16_t * | pBuffer,
 |  | uint32_t | WriteAddr,
 |  | uint32_t | NumHalfwordToWrite
 | ) |  |

Writes a Half-word buffer to the FSMC SRAM memory.

Parameters:
pBuffer | : pointer to buffer.
WriteAddr | : SRAM memory internal address from which the data will be written.
NumHalfwordToWrite | : number of half-words to write.
Return values:
None

< while there is data to write

< Transfer data to the memory

< Increment the address

Definition at line 185 of file stm32100e_eval_fsmc_sram.c.

Referenced by main().


STM32F10x Standard Peripherals Firmware Library: STM32100E_EVAL_FSMC_SRAM_Exported_Types

STM32100E_EVAL_FSMC_SRAM_Exported_Types

STM32100E_EVAL_FSMC_SRAM


STM32F10x Standard Peripherals Firmware Library: STM32100E_EVAL_FSMC_SRAM_Exported_Constants

STM32100E_EVAL_FSMC_SRAM_Exported_Constants

STM32100E_EVAL_FSMC_SRAM


STM32F10x Standard Peripherals Firmware Library: STM32100E_EVAL_FSMC_SRAM_Exported_Macros

STM32100E_EVAL_FSMC_SRAM_Exported_Macros

STM32100E_EVAL_FSMC_SRAM


STM32F10x Standard Peripherals Firmware Library: STM32100E_EVAL_FSMC_SRAM_Exported_Functions

Functions

STM32100E_EVAL_FSMC_SRAM_Exported_Functions

STM32100E_EVAL_FSMC_SRAM

Functions

void | SRAM_Init (void)
Configures the FSMC and GPIOs to interface with the SRAM memory.
void | SRAM_ReadBuffer (uint16_t *pBuffer, uint32_t ReadAddr, uint32_t NumHalfwordToRead)
Reads a block of data from the FSMC SRAM memory.
void | SRAM_WriteBuffer (uint16_t *pBuffer, uint32_t WriteAddr, uint32_t NumHalfwordToWrite)
Writes a Half-word buffer to the FSMC SRAM memory.

Function Documentation

void SRAM_Init ( void )

Configures the FSMC and GPIOs to interface with the SRAM memory.

This function must be called before any write/read operation on the SRAM.

Parameters:
None
Return values:
None

< SRAM Data lines configuration

< SRAM Address lines configuration

< NOE and NWE configuration

< NE3 configuration

< NBL0, NBL1 configuration

< Enable FSMC Bank1_SRAM Bank

< SRAM Data lines configuration

< SRAM Address lines configuration

< NOE and NWE configuration

< NE3 configuration

< NBL0, NBL1 configuration

< Enable FSMC Bank1_SRAM Bank

Definition at line 99 of file stm32100e_eval_fsmc_sram.c.

void SRAM_ReadBuffer | ( | uint16_t * | pBuffer,
 |  | uint32_t | ReadAddr,
 |  | uint32_t | NumHalfwordToRead
 | ) |  |

Reads a block of data from the FSMC SRAM memory.

Parameters:
pBuffer | : pointer to the buffer that receives the data read from the SRAM memory.
ReadAddr | : SRAM memory internal address to read from.
NumHalfwordToRead | : number of half-words to read.
Return values:
None

< while there is data to read

< Read a half-word from the memory

< Increment the address

< while there is data to read

< Read a half-word from the memory

< Increment the address

Definition at line 205 of file stm32100e_eval_fsmc_sram.c.

void SRAM_WriteBuffer | ( | uint16_t * | pBuffer,
 |  | uint32_t | WriteAddr,
 |  | uint32_t | NumHalfwordToWrite
 | ) |  |

Writes a Half-word buffer to the FSMC SRAM memory.

Parameters:
pBuffer | : pointer to buffer.
WriteAddr | : SRAM memory internal address from which the data will be written.
NumHalfwordToWrite | : number of half-words to write.
Return values:
None

< while there is data to write

< Transfer data to the memory

< Increment the address

< while there is data to write

< Transfer data to the memory

< Increment the address

Definition at line 185 of file stm32100e_eval_fsmc_sram.c.


STM32F10x Standard Peripherals Firmware Library: STM3210B_EVAL_LOW_LEVEL_Private_TypesDefinitions

STM3210B_EVAL_LOW_LEVEL_Private_TypesDefinitions

STM3210B_EVAL_LOW_LEVEL


STM32F10x Standard Peripherals Firmware Library: STM3210B_EVAL_LOW_LEVEL_Private_Defines

STM3210B_EVAL_LOW_LEVEL_Private_Defines

STM3210B_EVAL_LOW_LEVEL


STM32F10x Standard Peripherals Firmware Library: STM3210B_EVAL_LOW_LEVEL_Private_Macros

STM3210B_EVAL_LOW_LEVEL_Private_Macros

STM3210B_EVAL_LOW_LEVEL


STM32F10x Standard Peripherals Firmware Library: STM3210B_EVAL_LOW_LEVEL_Private_Variables

Variables

STM3210B_EVAL_LOW_LEVEL_Private_Variables

STM3210B_EVAL_LOW_LEVEL

Variables

const uint32_t | BUTTON_CLK [BUTTONn]
const uint16_t | BUTTON_EXTI_LINE [BUTTONn]
const uint16_t | BUTTON_IRQn [BUTTONn]
const uint16_t | BUTTON_PIN [BUTTONn]
const uint16_t | BUTTON_PIN_SOURCE [BUTTONn]
GPIO_TypeDef * | BUTTON_PORT [BUTTONn]
const uint16_t | BUTTON_PORT_SOURCE [BUTTONn]
const uint16_t | COM_RX_PIN [COMn] = {EVAL_COM1_RX_PIN, EVAL_COM2_RX_PIN}
GPIO_TypeDef * | COM_RX_PORT [COMn] = {EVAL_COM1_RX_GPIO_PORT, EVAL_COM2_RX_GPIO_PORT}
const uint32_t | COM_RX_PORT_CLK [COMn] = {EVAL_COM1_RX_GPIO_CLK, EVAL_COM2_RX_GPIO_CLK}
const uint16_t | COM_TX_PIN [COMn] = {EVAL_COM1_TX_PIN, EVAL_COM2_TX_PIN}
GPIO_TypeDef * | COM_TX_PORT [COMn] = {EVAL_COM1_TX_GPIO_PORT, EVAL_COM2_TX_GPIO_PORT}
const uint32_t | COM_TX_PORT_CLK [COMn] = {EVAL_COM1_TX_GPIO_CLK, EVAL_COM2_TX_GPIO_CLK}
USART_TypeDef * | COM_USART [COMn] = {EVAL_COM1, EVAL_COM2}
const uint32_t | COM_USART_CLK [COMn] = {EVAL_COM1_CLK, EVAL_COM2_CLK}
const uint32_t | GPIO_CLK [LEDn]
const uint16_t | GPIO_PIN [LEDn]
GPIO_TypeDef * | GPIO_PORT [LEDn]

Variable Documentation

const uint32_t BUTTON_CLK[BUTTONn]
Initial value:
 {WAKEUP_BUTTON_GPIO_CLK, TAMPER_BUTTON_GPIO_CLK,
                                      KEY_BUTTON_GPIO_CLK, RIGHT_BUTTON_GPIO_CLK,
                                      LEFT_BUTTON_GPIO_CLK, UP_BUTTON_GPIO_CLK,
                                      DOWN_BUTTON_GPIO_CLK, SEL_BUTTON_GPIO_CLK}

Definition at line 93 of file stm3210b_eval.c.

const uint16_t BUTTON_EXTI_LINE[BUTTONn]
Initial value:
 {WAKEUP_BUTTON_EXTI_LINE,
                                            TAMPER_BUTTON_EXTI_LINE,
                                            KEY_BUTTON_EXTI_LINE,
                                            RIGHT_BUTTON_EXTI_LINE,
                                            LEFT_BUTTON_EXTI_LINE,
                                            UP_BUTTON_EXTI_LINE,
                                            DOWN_BUTTON_EXTI_LINE,
                                            SEL_BUTTON_EXTI_LINE}

Definition at line 98 of file stm3210b_eval.c.

const uint16_t BUTTON_IRQn[BUTTONn]
Initial value:
 {WAKEUP_BUTTON_EXTI_IRQn, TAMPER_BUTTON_EXTI_IRQn,
                                       KEY_BUTTON_EXTI_IRQn, RIGHT_BUTTON_EXTI_IRQn,
                                       LEFT_BUTTON_EXTI_IRQn, UP_BUTTON_EXTI_IRQn,
                                       DOWN_BUTTON_EXTI_IRQn, SEL_BUTTON_EXTI_IRQn}

Definition at line 125 of file stm3210b_eval.c.

const uint16_t BUTTON_PIN[BUTTONn]
Initial value:
 {WAKEUP_BUTTON_PIN, TAMPER_BUTTON_PIN,
                                      KEY_BUTTON_PIN, RIGHT_BUTTON_PIN,
                                      LEFT_BUTTON_PIN, UP_BUTTON_PIN,
                                      DOWN_BUTTON_PIN, SEL_BUTTON_PIN}

Definition at line 88 of file stm3210b_eval.c.

const uint16_t BUTTON_PIN_SOURCE[BUTTONn]
Initial value:
 {WAKEUP_BUTTON_EXTI_PIN_SOURCE,
                                             TAMPER_BUTTON_EXTI_PIN_SOURCE,
                                             KEY_BUTTON_EXTI_PIN_SOURCE,
                                             RIGHT_BUTTON_EXTI_PIN_SOURCE,
                                             LEFT_BUTTON_EXTI_PIN_SOURCE,
                                             UP_BUTTON_EXTI_PIN_SOURCE,
                                             DOWN_BUTTON_EXTI_PIN_SOURCE,
                                             SEL_BUTTON_EXTI_PIN_SOURCE}

Definition at line 116 of file stm3210b_eval.c.

GPIO_TypeDef* BUTTON_PORT[BUTTONn]
Initial value:
 {WAKEUP_BUTTON_GPIO_PORT, TAMPER_BUTTON_GPIO_PORT,
                                      KEY_BUTTON_GPIO_PORT, RIGHT_BUTTON_GPIO_PORT,
                                      LEFT_BUTTON_GPIO_PORT, UP_BUTTON_GPIO_PORT,
                                      DOWN_BUTTON_GPIO_PORT, SEL_BUTTON_GPIO_PORT}

Definition at line 83 of file stm3210b_eval.c.

const uint16_t BUTTON_PORT_SOURCE[BUTTONn]
Initial value:
 {WAKEUP_BUTTON_EXTI_PORT_SOURCE,
                                              TAMPER_BUTTON_EXTI_PORT_SOURCE,
                                              KEY_BUTTON_EXTI_PORT_SOURCE,
                                              RIGHT_BUTTON_EXTI_PORT_SOURCE,
                                              LEFT_BUTTON_EXTI_PORT_SOURCE,
                                              UP_BUTTON_EXTI_PORT_SOURCE,
                                              DOWN_BUTTON_EXTI_PORT_SOURCE,
                                              SEL_BUTTON_EXTI_PORT_SOURCE}

Definition at line 107 of file stm3210b_eval.c.

const uint16_t COM_RX_PIN[COMn] = {EVAL_COM1_RX_PIN, EVAL_COM2_RX_PIN}

Definition at line 144 of file stm3210b_eval.c.

GPIO_TypeDef* COM_RX_PORT[COMn] = {EVAL_COM1_RX_GPIO_PORT, EVAL_COM2_RX_GPIO_PORT}

Definition at line 134 of file stm3210b_eval.c.

const uint32_t COM_RX_PORT_CLK[COMn] = {EVAL_COM1_RX_GPIO_CLK, EVAL_COM2_RX_GPIO_CLK}

Definition at line 140 of file stm3210b_eval.c.

const uint16_t COM_TX_PIN[COMn] = {EVAL_COM1_TX_PIN, EVAL_COM2_TX_PIN}

Definition at line 142 of file stm3210b_eval.c.

GPIO_TypeDef* COM_TX_PORT[COMn] = {EVAL_COM1_TX_GPIO_PORT, EVAL_COM2_TX_GPIO_PORT}

Definition at line 132 of file stm3210b_eval.c.

const uint32_t COM_TX_PORT_CLK[COMn] = {EVAL_COM1_TX_GPIO_CLK, EVAL_COM2_TX_GPIO_CLK}

Definition at line 138 of file stm3210b_eval.c.

USART_TypeDef* COM_USART[COMn] = {EVAL_COM1, EVAL_COM2}

Definition at line 130 of file stm3210b_eval.c.

const uint32_t COM_USART_CLK[COMn] = {EVAL_COM1_CLK, EVAL_COM2_CLK}

Definition at line 136 of file stm3210b_eval.c.

const uint32_t GPIO_CLK[LEDn]
Initial value:
 {LED1_GPIO_CLK, LED2_GPIO_CLK, LED3_GPIO_CLK,
                                 LED4_GPIO_CLK}

Definition at line 80 of file stm3210b_eval.c.

const uint16_t GPIO_PIN[LEDn]
Initial value:
 {LED1_PIN, LED2_PIN, LED3_PIN,
                                 LED4_PIN}

Definition at line 78 of file stm3210b_eval.c.

GPIO_TypeDef* GPIO_PORT[LEDn]
Initial value:
 {LED1_GPIO_PORT, LED2_GPIO_PORT, LED3_GPIO_PORT,
                                 LED4_GPIO_PORT}

Definition at line 76 of file stm3210b_eval.c.


STM32F10x Standard Peripherals Firmware Library: STM3210B_EVAL_LOW_LEVEL_Private_FunctionPrototypes

STM3210B_EVAL_LOW_LEVEL_Private_FunctionPrototypes

STM3210B_EVAL_LOW_LEVEL


STM32F10x Standard Peripherals Firmware Library: STM3210B_EVAL_LOW_LEVEL_Private_Functions

Functions

STM3210B_EVAL_LOW_LEVEL_Private_Functions

STM3210B_EVAL_LOW_LEVEL

Functions

void | LM75_LowLevel_DeInit (void)
DeInitializes the LM75_I2C.
void | LM75_LowLevel_Init (void)
Initializes the LM75_I2C.
void | SD_LowLevel_DeInit (void)
DeInitializes the SD/SD communication.
void | SD_LowLevel_Init (void)
Initializes the SD_SPI and CS pins.
void | sFLASH_LowLevel_DeInit (void)
DeInitializes the peripherals used by the SPI FLASH driver.
void | sFLASH_LowLevel_Init (void)
Initializes the peripherals used by the SPI FLASH driver.
void | STM_EVAL_COMInit (COM_TypeDef COM, USART_InitTypeDef *USART_InitStruct)
Configures COM port.
void | STM_EVAL_LEDInit (Led_TypeDef Led)
Configures LED GPIO.
void | STM_EVAL_LEDOff (Led_TypeDef Led)
Turns selected LED Off.
void | STM_EVAL_LEDOn (Led_TypeDef Led)
Turns selected LED On.
void | STM_EVAL_LEDToggle (Led_TypeDef Led)
Toggles the selected LED.
uint32_t | STM_EVAL_PBGetState (Button_TypeDef Button)
Returns the selected Button state.
void | STM_EVAL_PBInit (Button_TypeDef Button, ButtonMode_TypeDef Button_Mode)
Configures Button GPIO and EXTI Line.

Function Documentation

void LM75_LowLevel_DeInit ( void )

DeInitializes the LM75_I2C.

Parameters:
None
Return values:
None

< Disable LM75_I2C

< DeInitializes the LM75_I2C

< LM75_I2C Periph clock disable

< Configure LM75_I2C pins: SCL

< Configure LM75_I2C pins: SDA

< Configure LM75_I2C pin: SMBUS ALERT

Definition at line 540 of file stm3210b_eval.c.

References DISABLE, GPIO_Init(), GPIO_InitStructure, GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_IN_FLOATING, GPIO_InitTypeDef::GPIO_Pin, I2C_Cmd(), I2C_DeInit(), LM75_I2C, LM75_I2C_CLK, LM75_I2C_SCL_GPIO_PORT, LM75_I2C_SCL_PIN, LM75_I2C_SDA_GPIO_PORT, LM75_I2C_SDA_PIN, LM75_I2C_SMBUSALERT_GPIO_PORT, LM75_I2C_SMBUSALERT_PIN, and RCC_APB1PeriphClockCmd().

void LM75_LowLevel_Init ( void )

Initializes the LM75_I2C.

Parameters:
None
Return values:
None

< LM75_I2C Periph clock enable

< LM75_I2C_SCL_GPIO_CLK, LM75_I2C_SDA_GPIO_CLK and LM75_I2C_SMBUSALERT_GPIO_CLK Periph clock enable

< Configure LM75_I2C pins: SCL

< Configure LM75_I2C pins: SDA

< Configure LM75_I2C pin: SMBUS ALERT

Definition at line 571 of file stm3210b_eval.c.

References ENABLE, GPIO_Init(), GPIO_InitStructure, GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_AF_OD, GPIO_Mode_IPU, GPIO_InitTypeDef::GPIO_Pin, GPIO_InitTypeDef::GPIO_Speed, GPIO_Speed_50MHz, LM75_I2C_CLK, LM75_I2C_SCL_GPIO_CLK, LM75_I2C_SCL_GPIO_PORT, LM75_I2C_SCL_PIN, LM75_I2C_SDA_GPIO_CLK, LM75_I2C_SDA_GPIO_PORT, LM75_I2C_SDA_PIN, LM75_I2C_SMBUSALERT_GPIO_CLK, LM75_I2C_SMBUSALERT_GPIO_PORT, LM75_I2C_SMBUSALERT_PIN, RCC_APB1PeriphClockCmd(), and RCC_APB2PeriphClockCmd().

void SD_LowLevel_DeInit ( void )

DeInitializes the SD/SD communication.

Parameters:
None
Return values:
None

< SD_SPI disable

< DeInitializes the SD_SPI

< SD_SPI Periph clock disable

< Configure SD_SPI pins: SCK

< Configure SD_SPI pins: MISO

< Configure SD_SPI pins: MOSI

< Configure SD_SPI_CS_PIN pin: SD Card CS pin

< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin

Definition at line 370 of file stm3210b_eval.c.

References DISABLE, GPIO_Init(), GPIO_InitStructure, GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_IN_FLOATING, GPIO_InitTypeDef::GPIO_Pin, RCC_APB2PeriphClockCmd(), SD_CS_GPIO_PORT, SD_CS_PIN, SD_DETECT_GPIO_PORT, SD_DETECT_PIN, SD_SPI, SD_SPI_CLK, SD_SPI_MISO_GPIO_PORT, SD_SPI_MISO_PIN, SD_SPI_MOSI_GPIO_PORT, SD_SPI_MOSI_PIN, SD_SPI_SCK_GPIO_PORT, SD_SPI_SCK_PIN, SPI_Cmd(), and SPI_I2S_DeInit().

void SD_LowLevel_Init ( void )

Initializes the SD_SPI and CS pins.

Parameters:
None
Return values:
None

< SD_SPI_CS_GPIO, SD_SPI_MOSI_GPIO, SD_SPI_MISO_GPIO, SD_SPI_DETECT_GPIO and SD_SPI_SCK_GPIO Periph clock enable

< SD_SPI Periph clock enable

< Configure SD_SPI pins: SCK

< Configure SD_SPI pins: MOSI

< Configure SD_SPI pins: MISO

< Configure SD_SPI_CS_PIN pin: SD Card CS pin

< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin

< SD_SPI Config

< SD_SPI enable

Definition at line 407 of file stm3210b_eval.c.

References ENABLE, GPIO_Init(), GPIO_InitStructure, GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_AF_PP, GPIO_Mode_IN_FLOATING, GPIO_Mode_IPU, GPIO_Mode_Out_PP, GPIO_InitTypeDef::GPIO_Pin, GPIO_InitTypeDef::GPIO_Speed, GPIO_Speed_50MHz, RCC_APB2PeriphClockCmd(), SD_CS_GPIO_CLK, SD_CS_GPIO_PORT, SD_CS_PIN, SD_DETECT_GPIO_CLK, SD_DETECT_GPIO_PORT, SD_DETECT_PIN, SD_SPI, SD_SPI_CLK, SD_SPI_MISO_GPIO_CLK, SD_SPI_MISO_GPIO_PORT, SD_SPI_MISO_PIN, SD_SPI_MOSI_GPIO_CLK, SD_SPI_MOSI_GPIO_PORT, SD_SPI_MOSI_PIN, SD_SPI_SCK_GPIO_CLK, SD_SPI_SCK_GPIO_PORT, SD_SPI_SCK_PIN, SPI_InitTypeDef::SPI_BaudRatePrescaler, SPI_BaudRatePrescaler_4, SPI_Cmd(), SPI_InitTypeDef::SPI_CPHA, SPI_CPHA_2Edge, SPI_InitTypeDef::SPI_CPOL, SPI_CPOL_High, SPI_InitTypeDef::SPI_CRCPolynomial, SPI_InitTypeDef::SPI_DataSize, SPI_DataSize_8b, SPI_InitTypeDef::SPI_Direction, SPI_Direction_2Lines_FullDuplex, SPI_InitTypeDef::SPI_FirstBit, SPI_FirstBit_MSB, SPI_Init(), SPI_InitStructure, SPI_InitTypeDef::SPI_Mode, SPI_Mode_Master, SPI_InitTypeDef::SPI_NSS, and SPI_NSS_Soft.

void sFLASH_LowLevel_DeInit ( void )

DeInitializes the peripherals used by the SPI FLASH driver.

Parameters:
None
Return values:
None

< Disable the sFLASH_SPI

< DeInitializes the sFLASH_SPI

< sFLASH_SPI Periph clock disable

< Configure sFLASH_SPI pins: SCK

< Configure sFLASH_SPI pins: MISO

< Configure sFLASH_SPI pins: MOSI

< Configure sFLASH_CS_PIN pin: sFLASH Card CS pin

Definition at line 466 of file stm3210b_eval.c.

References DISABLE, GPIO_Init(), GPIO_InitStructure, GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_IN_FLOATING, GPIO_InitTypeDef::GPIO_Pin, RCC_APB2PeriphClockCmd(), sFLASH_CS_GPIO_PORT, sFLASH_CS_PIN, sFLASH_SPI, sFLASH_SPI_CLK, sFLASH_SPI_MISO_GPIO_PORT, sFLASH_SPI_MISO_PIN, sFLASH_SPI_MOSI_GPIO_PORT, sFLASH_SPI_MOSI_PIN, sFLASH_SPI_SCK_GPIO_PORT, sFLASH_SPI_SCK_PIN, SPI_Cmd(), and SPI_I2S_DeInit().

void sFLASH_LowLevel_Init ( void )

Initializes the peripherals used by the SPI FLASH driver.

Parameters:
None
Return values:
None

< sFLASH_SPI_CS_GPIO, sFLASH_SPI_MOSI_GPIO, sFLASH_SPI_MISO_GPIO and sFLASH_SPI_SCK_GPIO Periph clock enable

< sFLASH_SPI Periph clock enable

< Configure sFLASH_SPI pins: SCK

< Configure sFLASH_SPI pins: MOSI

< Configure sFLASH_SPI pins: MISO

< Configure sFLASH_CS_PIN pin: sFLASH Card CS pin

Definition at line 502 of file stm3210b_eval.c.

References ENABLE, GPIO_Init(), GPIO_InitStructure, GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_AF_PP, GPIO_Mode_IN_FLOATING, GPIO_Mode_Out_PP, GPIO_InitTypeDef::GPIO_Pin, GPIO_InitTypeDef::GPIO_Speed, GPIO_Speed_50MHz, RCC_APB2PeriphClockCmd(), sFLASH_CS_GPIO_CLK, sFLASH_CS_GPIO_PORT, sFLASH_CS_PIN, sFLASH_SPI_CLK, sFLASH_SPI_MISO_GPIO_CLK, sFLASH_SPI_MISO_GPIO_PORT, sFLASH_SPI_MISO_PIN, sFLASH_SPI_MOSI_GPIO_CLK, sFLASH_SPI_MOSI_GPIO_PORT, sFLASH_SPI_MOSI_PIN, sFLASH_SPI_SCK_GPIO_CLK, sFLASH_SPI_SCK_GPIO_PORT, and sFLASH_SPI_SCK_PIN.

void STM_EVAL_COMInit | ( | COM_TypeDef | COM,
 |  | USART_InitTypeDef * | USART_InitStruct
 | ) |  |

Configures COM port.

Parameters:
COM,: Specifies the COM port to be configured. This parameter can be one of following parameters:

  • COM1
  • COM2
USART_InitStruct,: pointer to a USART_InitTypeDef structure that contains the configuration information for the specified USART peripheral.
Return values:
None

Definition at line 328 of file stm3210b_eval.c.

References COM1, COM_RX_PIN, COM_RX_PORT_CLK, COM_TX_PIN, COM_TX_PORT_CLK, COM_USART_CLK, ENABLE, GPIO_Init(), GPIO_InitStructure, GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_AF_PP, GPIO_Mode_IN_FLOATING, GPIO_InitTypeDef::GPIO_Pin, GPIO_PinRemapConfig(), GPIO_Remap_USART2, GPIO_InitTypeDef::GPIO_Speed, GPIO_Speed_50MHz, RCC_APB1PeriphClockCmd(), RCC_APB2Periph_AFIO, RCC_APB2PeriphClockCmd(), USART_Cmd(), and USART_Init().

void STM_EVAL_LEDInit ( Led_TypeDef Led )

Configures LED GPIO.

Parameters:
Led,: Specifies the Led to be configured. This parameter can be one of following parameters:

  • LED1
  • LED2
  • LED3
  • LED4
Return values:
None

Definition at line 175 of file stm3210b_eval.c.

References ENABLE, GPIO_CLK, GPIO_Init(), GPIO_InitStructure, GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_Out_PP, GPIO_PIN, GPIO_InitTypeDef::GPIO_Pin, GPIO_InitTypeDef::GPIO_Speed, GPIO_Speed_50MHz, and RCC_APB2PeriphClockCmd().

void STM_EVAL_LEDOff ( Led_TypeDef Led )

Turns selected LED Off.

Parameters:
Led,: Specifies the Led to be set off. This parameter can be one of following parameters:

  • LED1
  • LED2
  • LED3
  • LED4
Return values:
None

Definition at line 215 of file stm3210b_eval.c.

References GPIO_TypeDef::BRR, and GPIO_PIN.

void STM_EVAL_LEDOn ( Led_TypeDef Led )

Turns selected LED On.

Parameters:
Led,: Specifies the Led to be set on. This parameter can be one of following parameters:

  • LED1
  • LED2
  • LED3
  • LED4
Return values:
None

Definition at line 200 of file stm3210b_eval.c.

References GPIO_TypeDef::BSRR, and GPIO_PIN.

void STM_EVAL_LEDToggle ( Led_TypeDef Led )

Toggles the selected LED.

Parameters:
Led,: Specifies the Led to be toggled. This parameter can be one of following parameters:

  • LED1
  • LED2
  • LED3
  • LED4
Return values:
None

Definition at line 230 of file stm3210b_eval.c.

References GPIO_PIN, and GPIO_TypeDef::ODR.

uint32_t STM_EVAL_PBGetState ( Button_TypeDef Button )

Returns the selected Button state.

Parameters:
Button,: Specifies the Button to be checked. This parameter can be one of following parameters:

  • BUTTON_WAKEUP: Wakeup Push Button
  • BUTTON_TAMPER: Tamper Push Button
  • BUTTON_KEY: Key Push Button
  • BUTTON_RIGHT: Joystick Right Push Button
  • BUTTON_LEFT: Joystick Left Push Button
  • BUTTON_UP: Joystick Up Push Button
  • BUTTON_DOWN: Joystick Down Push Button
  • BUTTON_SEL: Joystick Sel Push Button
Return values:
The Button GPIO pin value.

Definition at line 313 of file stm3210b_eval.c.

References BUTTON_PIN, and GPIO_ReadInputDataBit().

void STM_EVAL_PBInit | ( | Button_TypeDef | Button,
 |  | ButtonMode_TypeDef | Button_Mode
 | ) |  |

Configures Button GPIO and EXTI Line.

Parameters:
Button,: Specifies the Button to be configured. This parameter can be one of following parameters:

  • BUTTON_WAKEUP: Wakeup Push Button
  • BUTTON_TAMPER: Tamper Push Button
  • BUTTON_KEY: Key Push Button
  • BUTTON_RIGHT: Joystick Right Push Button
  • BUTTON_LEFT: Joystick Left Push Button
  • BUTTON_UP: Joystick Up Push Button
  • BUTTON_DOWN: Joystick Down Push Button
  • BUTTON_SEL: Joystick Sel Push Button
Button_Mode,: Specifies Button mode. This parameter can be one of following parameters:

  • BUTTON_MODE_GPIO: Button will be used as simple IO
  • BUTTON_MODE_EXTI: Button will be connected to EXTI line with interrupt generation capability
Return values:
None

Definition at line 254 of file stm3210b_eval.c.

References BUTTON_CLK, BUTTON_EXTI_LINE, BUTTON_IRQn, BUTTON_MODE_EXTI, BUTTON_PIN, BUTTON_PIN_SOURCE, BUTTON_PORT_SOURCE, BUTTON_WAKEUP, ENABLE, EXTI_Init(), EXTI_InitStructure, EXTI_InitTypeDef::EXTI_Line, EXTI_InitTypeDef::EXTI_LineCmd, EXTI_InitTypeDef::EXTI_Mode, EXTI_Mode_Interrupt, EXTI_InitTypeDef::EXTI_Trigger, EXTI_Trigger_Falling, EXTI_Trigger_Rising, GPIO_EXTILineConfig(), GPIO_Init(), GPIO_InitStructure, GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_IN_FLOATING, GPIO_InitTypeDef::GPIO_Pin, NVIC_Init(), NVIC_InitStructure, NVIC_InitTypeDef::NVIC_IRQChannel, NVIC_InitTypeDef::NVIC_IRQChannelCmd, NVIC_InitTypeDef::NVIC_IRQChannelPreemptionPriority, NVIC_InitTypeDef::NVIC_IRQChannelSubPriority, RCC_APB2Periph_AFIO, and RCC_APB2PeriphClockCmd().


STM32F10x Standard Peripherals Firmware Library: STM3210B_EVAL_LOW_LEVEL_Exported_Types

STM3210B_EVAL_LOW_LEVEL_Exported_Types

STM3210B_EVAL_LOW_LEVEL


STM32F10x Standard Peripherals Firmware Library: STM3210B_EVAL_LOW_LEVEL_LED

Defines

STM3210B_EVAL_LOW_LEVEL_LED

STM3210B_EVAL_LOW_LEVEL_Exported_Constants

Defines

#define | LED1_GPIO_CLK RCC_APB2Periph_GPIOC
#define | LED1_GPIO_PORT GPIOC
#define | LED1_PIN GPIO_Pin_6
#define | LED2_GPIO_CLK RCC_APB2Periph_GPIOC
#define | LED2_GPIO_PORT GPIOC
#define | LED2_PIN GPIO_Pin_7
#define | LED3_GPIO_CLK RCC_APB2Periph_GPIOC
#define | LED3_GPIO_PORT GPIOC
#define | LED3_PIN GPIO_Pin_8
#define | LED4_GPIO_CLK RCC_APB2Periph_GPIOC
#define | LED4_GPIO_PORT GPIOC
#define | LED4_PIN GPIO_Pin_9
#define | LEDn 4

Define Documentation

#define LED1_GPIO_CLK RCC_APB2Periph_GPIOC

Definition at line 70 of file stm3210b_eval.h.

#define LED1_GPIO_PORT GPIOC

Definition at line 69 of file stm3210b_eval.h.

#define LED1_PIN GPIO_Pin_6

Definition at line 68 of file stm3210b_eval.h.

#define LED2_GPIO_CLK RCC_APB2Periph_GPIOC

Definition at line 74 of file stm3210b_eval.h.

#define LED2_GPIO_PORT GPIOC

Definition at line 73 of file stm3210b_eval.h.

#define LED2_PIN GPIO_Pin_7

Definition at line 72 of file stm3210b_eval.h.

#define LED3_GPIO_CLK RCC_APB2Periph_GPIOC

Definition at line 78 of file stm3210b_eval.h.

#define LED3_GPIO_PORT GPIOC

Definition at line 77 of file stm3210b_eval.h.

#define LED3_PIN GPIO_Pin_8

Definition at line 76 of file stm3210b_eval.h.

#define LED4_GPIO_CLK RCC_APB2Periph_GPIOC

Definition at line 82 of file stm3210b_eval.h.

#define LED4_GPIO_PORT GPIOC

Definition at line 81 of file stm3210b_eval.h.

#define LED4_PIN GPIO_Pin_9

Definition at line 80 of file stm3210b_eval.h.

#define LEDn 4

Definition at line 67 of file stm3210b_eval.h.


STM32F10x Standard Peripherals Firmware Library: STM3210B_EVAL_LOW_LEVEL_BUTTON

Defines

STM3210B_EVAL_LOW_LEVEL_BUTTON

STM3210B_EVAL_LOW_LEVEL_Exported_Constants

Defines

#define | BUTTONn 8
#define | DOWN_BUTTON_EXTI_IRQn EXTI15_10_IRQn
#define | DOWN_BUTTON_EXTI_LINE EXTI_Line14
#define | DOWN_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource14
#define | DOWN_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOD
#define | DOWN_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOD
#define | DOWN_BUTTON_GPIO_PORT GPIOD
#define | DOWN_BUTTON_PIN GPIO_Pin_14
Joystick Down push-button.
#define | KEY_BUTTON_EXTI_IRQn EXTI9_5_IRQn
#define | KEY_BUTTON_EXTI_LINE EXTI_Line9
#define | KEY_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource9
#define | KEY_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOB
#define | KEY_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOB
#define | KEY_BUTTON_GPIO_PORT GPIOB
#define | KEY_BUTTON_PIN GPIO_Pin_9
Key push-button.
#define | LEFT_BUTTON_EXTI_IRQn EXTI1_IRQn
#define | LEFT_BUTTON_EXTI_LINE EXTI_Line1
#define | LEFT_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource1
#define | LEFT_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOE
#define | LEFT_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOE
#define | LEFT_BUTTON_GPIO_PORT GPIOE
#define | LEFT_BUTTON_PIN GPIO_Pin_1
Joystick Left push-button.
#define | RIGHT_BUTTON_EXTI_IRQn EXTI0_IRQn
#define | RIGHT_BUTTON_EXTI_LINE EXTI_Line0
#define | RIGHT_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource0
#define | RIGHT_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOE
#define | RIGHT_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOE
#define | RIGHT_BUTTON_GPIO_PORT GPIOE
#define | RIGHT_BUTTON_PIN GPIO_Pin_0
Joystick Right push-button.
#define | SEL_BUTTON_EXTI_IRQn EXTI15_10_IRQn
#define | SEL_BUTTON_EXTI_LINE EXTI_Line12
#define | SEL_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource12
#define | SEL_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOD
#define | SEL_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOD
#define | SEL_BUTTON_GPIO_PORT GPIOD
#define | SEL_BUTTON_PIN GPIO_Pin_12
Joystick Sel push-button.
#define | TAMPER_BUTTON_EXTI_IRQn EXTI15_10_IRQn
#define | TAMPER_BUTTON_EXTI_LINE EXTI_Line13
#define | TAMPER_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource13
#define | TAMPER_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOC
#define | TAMPER_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOC
#define | TAMPER_BUTTON_GPIO_PORT GPIOC
#define | TAMPER_BUTTON_PIN GPIO_Pin_13
Tamper push-button.
#define | UP_BUTTON_EXTI_IRQn EXTI9_5_IRQn
#define | UP_BUTTON_EXTI_LINE EXTI_Line8
#define | UP_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource8
#define | UP_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOD
#define | UP_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOD
#define | UP_BUTTON_GPIO_PORT GPIOD
#define | UP_BUTTON_PIN GPIO_Pin_8
Joystick Up push-button.
#define | WAKEUP_BUTTON_EXTI_IRQn EXTI0_IRQn
#define | WAKEUP_BUTTON_EXTI_LINE EXTI_Line0
#define | WAKEUP_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource0
#define | WAKEUP_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOA
#define | WAKEUP_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOA
#define | WAKEUP_BUTTON_GPIO_PORT GPIOA
#define | WAKEUP_BUTTON_PIN GPIO_Pin_0
Wakeup push-button.

Define Documentation

#define BUTTONn 8

Definition at line 91 of file stm3210b_eval.h.

#define DOWN_BUTTON_EXTI_IRQn EXTI15_10_IRQn

Definition at line 162 of file stm3210b_eval.h.

#define DOWN_BUTTON_EXTI_LINE EXTI_Line14

Definition at line 159 of file stm3210b_eval.h.

#define DOWN_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource14

Definition at line 161 of file stm3210b_eval.h.

#define DOWN_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOD

Definition at line 160 of file stm3210b_eval.h.

#define DOWN_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOD

Definition at line 158 of file stm3210b_eval.h.

#define DOWN_BUTTON_GPIO_PORT GPIOD

Definition at line 157 of file stm3210b_eval.h.

#define DOWN_BUTTON_PIN GPIO_Pin_14

Joystick Down push-button.

Definition at line 156 of file stm3210b_eval.h.

#define KEY_BUTTON_EXTI_IRQn EXTI9_5_IRQn

Definition at line 122 of file stm3210b_eval.h.

#define KEY_BUTTON_EXTI_LINE EXTI_Line9

Definition at line 119 of file stm3210b_eval.h.

#define KEY_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource9

Definition at line 121 of file stm3210b_eval.h.

#define KEY_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOB

Definition at line 120 of file stm3210b_eval.h.

#define KEY_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOB

Definition at line 118 of file stm3210b_eval.h.

#define KEY_BUTTON_GPIO_PORT GPIOB

Definition at line 117 of file stm3210b_eval.h.

#define KEY_BUTTON_PIN GPIO_Pin_9

Key push-button.

Definition at line 116 of file stm3210b_eval.h.

#define LEFT_BUTTON_EXTI_IRQn EXTI1_IRQn

Definition at line 142 of file stm3210b_eval.h.

#define LEFT_BUTTON_EXTI_LINE EXTI_Line1

Definition at line 139 of file stm3210b_eval.h.

#define LEFT_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource1

Definition at line 141 of file stm3210b_eval.h.

#define LEFT_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOE

Definition at line 140 of file stm3210b_eval.h.

#define LEFT_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOE

Definition at line 138 of file stm3210b_eval.h.

#define LEFT_BUTTON_GPIO_PORT GPIOE

Definition at line 137 of file stm3210b_eval.h.

#define LEFT_BUTTON_PIN GPIO_Pin_1

Joystick Left push-button.

Definition at line 136 of file stm3210b_eval.h.

#define RIGHT_BUTTON_EXTI_IRQn EXTI0_IRQn

Definition at line 132 of file stm3210b_eval.h.

#define RIGHT_BUTTON_EXTI_LINE EXTI_Line0

Definition at line 129 of file stm3210b_eval.h.

#define RIGHT_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource0

Definition at line 131 of file stm3210b_eval.h.

#define RIGHT_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOE

Definition at line 130 of file stm3210b_eval.h.

#define RIGHT_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOE

Definition at line 128 of file stm3210b_eval.h.

#define RIGHT_BUTTON_GPIO_PORT GPIOE

Definition at line 127 of file stm3210b_eval.h.

#define RIGHT_BUTTON_PIN GPIO_Pin_0

Joystick Right push-button.

Definition at line 126 of file stm3210b_eval.h.

#define SEL_BUTTON_EXTI_IRQn EXTI15_10_IRQn

Definition at line 172 of file stm3210b_eval.h.

#define SEL_BUTTON_EXTI_LINE EXTI_Line12

Definition at line 169 of file stm3210b_eval.h.

#define SEL_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource12

Definition at line 171 of file stm3210b_eval.h.

#define SEL_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOD

Definition at line 170 of file stm3210b_eval.h.

#define SEL_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOD

Definition at line 168 of file stm3210b_eval.h.

#define SEL_BUTTON_GPIO_PORT GPIOD

Definition at line 167 of file stm3210b_eval.h.

#define SEL_BUTTON_PIN GPIO_Pin_12

Joystick Sel push-button.

Definition at line 166 of file stm3210b_eval.h.

#define TAMPER_BUTTON_EXTI_IRQn EXTI15_10_IRQn

Definition at line 112 of file stm3210b_eval.h.

#define TAMPER_BUTTON_EXTI_LINE EXTI_Line13

Definition at line 109 of file stm3210b_eval.h.

#define TAMPER_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource13

Definition at line 111 of file stm3210b_eval.h.

#define TAMPER_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOC

Definition at line 110 of file stm3210b_eval.h.

#define TAMPER_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOC

Definition at line 108 of file stm3210b_eval.h.

#define TAMPER_BUTTON_GPIO_PORT GPIOC

Definition at line 107 of file stm3210b_eval.h.

#define TAMPER_BUTTON_PIN GPIO_Pin_13

Tamper push-button.

Definition at line 106 of file stm3210b_eval.h.

#define UP_BUTTON_EXTI_IRQn EXTI9_5_IRQn

Definition at line 152 of file stm3210b_eval.h.

#define UP_BUTTON_EXTI_LINE EXTI_Line8

Definition at line 149 of file stm3210b_eval.h.

#define UP_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource8

Definition at line 151 of file stm3210b_eval.h.

#define UP_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOD

Definition at line 150 of file stm3210b_eval.h.

#define UP_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOD

Definition at line 148 of file stm3210b_eval.h.

#define UP_BUTTON_GPIO_PORT GPIOD

Definition at line 147 of file stm3210b_eval.h.

#define UP_BUTTON_PIN GPIO_Pin_8

Joystick Up push-button.

Definition at line 146 of file stm3210b_eval.h.

#define WAKEUP_BUTTON_EXTI_IRQn EXTI0_IRQn

Definition at line 102 of file stm3210b_eval.h.

#define WAKEUP_BUTTON_EXTI_LINE EXTI_Line0

Definition at line 99 of file stm3210b_eval.h.

#define WAKEUP_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource0

Definition at line 101 of file stm3210b_eval.h.

#define WAKEUP_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOA

Definition at line 100 of file stm3210b_eval.h.

#define WAKEUP_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOA

Definition at line 98 of file stm3210b_eval.h.

#define WAKEUP_BUTTON_GPIO_PORT GPIOA

Definition at line 97 of file stm3210b_eval.h.

#define WAKEUP_BUTTON_PIN GPIO_Pin_0

Wakeup push-button.

Definition at line 96 of file stm3210b_eval.h.


STM32F10x Standard Peripherals Firmware Library: STM3210B_EVAL_LOW_LEVEL_COM

Defines

STM3210B_EVAL_LOW_LEVEL_COM

STM3210B_EVAL_LOW_LEVEL_Exported_Constants

Defines

#define | COMn 2
#define | EVAL_COM1 USART1
Definition for COM port1, connected to USART1.
#define | EVAL_COM1_CLK RCC_APB2Periph_USART1
#define | EVAL_COM1_IRQn USART1_IRQn
#define | EVAL_COM1_RX_GPIO_CLK RCC_APB2Periph_GPIOA
#define | EVAL_COM1_RX_GPIO_PORT GPIOA
#define | EVAL_COM1_RX_PIN GPIO_Pin_10
#define | EVAL_COM1_TX_GPIO_CLK RCC_APB2Periph_GPIOA
#define | EVAL_COM1_TX_GPIO_PORT GPIOA
#define | EVAL_COM1_TX_PIN GPIO_Pin_9
#define | EVAL_COM2 USART2
Definition for COM port2, connected to USART2 (USART2 pins remapped on GPIOD)
#define | EVAL_COM2_CLK RCC_APB1Periph_USART2
#define | EVAL_COM2_IRQn USART2_IRQn
#define | EVAL_COM2_RX_GPIO_CLK RCC_APB2Periph_GPIOD
#define | EVAL_COM2_RX_GPIO_PORT GPIOD
#define | EVAL_COM2_RX_PIN GPIO_Pin_6
#define | EVAL_COM2_TX_GPIO_CLK RCC_APB2Periph_GPIOD
#define | EVAL_COM2_TX_GPIO_PORT GPIOD
#define | EVAL_COM2_TX_PIN GPIO_Pin_5

Define Documentation

#define COMn 2

Definition at line 180 of file stm3210b_eval.h.

#define EVAL_COM1 USART1

Definition for COM port1, connected to USART1.

Definition at line 185 of file stm3210b_eval.h.

#define EVAL_COM1_CLK RCC_APB2Periph_USART1

Definition at line 186 of file stm3210b_eval.h.

#define EVAL_COM1_IRQn USART1_IRQn

Definition at line 193 of file stm3210b_eval.h.

#define EVAL_COM1_RX_GPIO_CLK RCC_APB2Periph_GPIOA

Definition at line 192 of file stm3210b_eval.h.

#define EVAL_COM1_RX_GPIO_PORT GPIOA

Definition at line 191 of file stm3210b_eval.h.

#define EVAL_COM1_RX_PIN GPIO_Pin_10

Definition at line 190 of file stm3210b_eval.h.

#define EVAL_COM1_TX_GPIO_CLK RCC_APB2Periph_GPIOA

Definition at line 189 of file stm3210b_eval.h.

#define EVAL_COM1_TX_GPIO_PORT GPIOA

Definition at line 188 of file stm3210b_eval.h.

#define EVAL_COM1_TX_PIN GPIO_Pin_9

Definition at line 187 of file stm3210b_eval.h.

#define EVAL_COM2 USART2

Definition for COM port2, connected to USART2 (USART2 pins remapped on GPIOD)

Definition at line 198 of file stm3210b_eval.h.

#define EVAL_COM2_CLK RCC_APB1Periph_USART2

Definition at line 199 of file stm3210b_eval.h.

#define EVAL_COM2_IRQn USART2_IRQn

Definition at line 206 of file stm3210b_eval.h.

#define EVAL_COM2_RX_GPIO_CLK RCC_APB2Periph_GPIOD

Definition at line 205 of file stm3210b_eval.h.

#define EVAL_COM2_RX_GPIO_PORT GPIOD

Definition at line 204 of file stm3210b_eval.h.

#define EVAL_COM2_RX_PIN GPIO_Pin_6

Definition at line 203 of file stm3210b_eval.h.

#define EVAL_COM2_TX_GPIO_CLK RCC_APB2Periph_GPIOD

Definition at line 202 of file stm3210b_eval.h.

#define EVAL_COM2_TX_GPIO_PORT GPIOD

Definition at line 201 of file stm3210b_eval.h.

#define EVAL_COM2_TX_PIN GPIO_Pin_5

Definition at line 200 of file stm3210b_eval.h.


STM32F10x Standard Peripherals Firmware Library: STM3210B_EVAL_LOW_LEVEL_SD_SPI

Defines

STM3210B_EVAL_LOW_LEVEL_SD_SPI

STM3210B_EVAL_LOW_LEVEL_Exported_Constants

Defines

#define | SD_CS_GPIO_CLK RCC_APB2Periph_GPIOC
#define | SD_CS_GPIO_PORT GPIOC
#define | SD_CS_PIN GPIO_Pin_12
#define | SD_DETECT_GPIO_CLK RCC_APB2Periph_GPIOE
#define | SD_DETECT_GPIO_PORT GPIOE
#define | SD_DETECT_PIN GPIO_Pin_7
#define | SD_SPI SPI1
SD SPI Interface pins.
#define | SD_SPI_CLK RCC_APB2Periph_SPI1
#define | SD_SPI_MISO_GPIO_CLK RCC_APB2Periph_GPIOA
#define | SD_SPI_MISO_GPIO_PORT GPIOA
#define | SD_SPI_MISO_PIN GPIO_Pin_6
#define | SD_SPI_MOSI_GPIO_CLK RCC_APB2Periph_GPIOA
#define | SD_SPI_MOSI_GPIO_PORT GPIOA
#define | SD_SPI_MOSI_PIN GPIO_Pin_7
#define | SD_SPI_SCK_GPIO_CLK RCC_APB2Periph_GPIOA
#define | SD_SPI_SCK_GPIO_PORT GPIOA
#define | SD_SPI_SCK_PIN GPIO_Pin_5

Define Documentation

#define SD_CS_GPIO_CLK RCC_APB2Periph_GPIOC

Definition at line 231 of file stm3210b_eval.h.

#define SD_CS_GPIO_PORT GPIOC

Definition at line 230 of file stm3210b_eval.h.

#define SD_CS_PIN GPIO_Pin_12

Definition at line 229 of file stm3210b_eval.h.

#define SD_DETECT_GPIO_CLK RCC_APB2Periph_GPIOE

Definition at line 234 of file stm3210b_eval.h.

#define SD_DETECT_GPIO_PORT GPIOE

Definition at line 233 of file stm3210b_eval.h.

#define SD_DETECT_PIN GPIO_Pin_7

Definition at line 232 of file stm3210b_eval.h.

#define SD_SPI SPI1

SD SPI Interface pins.

Definition at line 218 of file stm3210b_eval.h.

#define SD_SPI_CLK RCC_APB2Periph_SPI1

Definition at line 219 of file stm3210b_eval.h.

#define SD_SPI_MISO_GPIO_CLK RCC_APB2Periph_GPIOA

Definition at line 225 of file stm3210b_eval.h.

#define SD_SPI_MISO_GPIO_PORT GPIOA

Definition at line 224 of file stm3210b_eval.h.

#define SD_SPI_MISO_PIN GPIO_Pin_6

Definition at line 223 of file stm3210b_eval.h.

#define SD_SPI_MOSI_GPIO_CLK RCC_APB2Periph_GPIOA

Definition at line 228 of file stm3210b_eval.h.

#define SD_SPI_MOSI_GPIO_PORT GPIOA

Definition at line 227 of file stm3210b_eval.h.

#define SD_SPI_MOSI_PIN GPIO_Pin_7

Definition at line 226 of file stm3210b_eval.h.

#define SD_SPI_SCK_GPIO_CLK RCC_APB2Periph_GPIOA

Definition at line 222 of file stm3210b_eval.h.

#define SD_SPI_SCK_GPIO_PORT GPIOA

Definition at line 221 of file stm3210b_eval.h.

#define SD_SPI_SCK_PIN GPIO_Pin_5

Definition at line 220 of file stm3210b_eval.h.


STM32F10x Standard Peripherals Firmware Library: STM3210B_EVAL_LOW_LEVEL_M25P_FLASH_SPI

Defines

STM3210B_EVAL_LOW_LEVEL_M25P_FLASH_SPI

STM3210B_EVAL_LOW_LEVEL_Exported_Constants

Defines

#define | sFLASH_CS_GPIO_CLK RCC_APB2Periph_GPIOA
#define | sFLASH_CS_GPIO_PORT GPIOA
#define | sFLASH_CS_PIN GPIO_Pin_4
#define | sFLASH_SPI SPI1
M25P FLASH SPI Interface pins.
#define | sFLASH_SPI_CLK RCC_APB2Periph_SPI1
#define | sFLASH_SPI_MISO_GPIO_CLK RCC_APB2Periph_GPIOA
#define | sFLASH_SPI_MISO_GPIO_PORT GPIOA
#define | sFLASH_SPI_MISO_PIN GPIO_Pin_6
#define | sFLASH_SPI_MOSI_GPIO_CLK RCC_APB2Periph_GPIOA
#define | sFLASH_SPI_MOSI_GPIO_PORT GPIOA
#define | sFLASH_SPI_MOSI_PIN GPIO_Pin_7
#define | sFLASH_SPI_SCK_GPIO_CLK RCC_APB2Periph_GPIOA
#define | sFLASH_SPI_SCK_GPIO_PORT GPIOA
#define | sFLASH_SPI_SCK_PIN GPIO_Pin_5

Define Documentation

#define sFLASH_CS_GPIO_CLK RCC_APB2Periph_GPIOA

Definition at line 259 of file stm3210b_eval.h.

#define sFLASH_CS_GPIO_PORT GPIOA

Definition at line 258 of file stm3210b_eval.h.

#define sFLASH_CS_PIN GPIO_Pin_4

Definition at line 257 of file stm3210b_eval.h.

#define sFLASH_SPI SPI1

M25P FLASH SPI Interface pins.

Definition at line 246 of file stm3210b_eval.h.

#define sFLASH_SPI_CLK RCC_APB2Periph_SPI1

Definition at line 247 of file stm3210b_eval.h.

#define sFLASH_SPI_MISO_GPIO_CLK RCC_APB2Periph_GPIOA

Definition at line 253 of file stm3210b_eval.h.

#define sFLASH_SPI_MISO_GPIO_PORT GPIOA

Definition at line 252 of file stm3210b_eval.h.

#define sFLASH_SPI_MISO_PIN GPIO_Pin_6

Definition at line 251 of file stm3210b_eval.h.

#define sFLASH_SPI_MOSI_GPIO_CLK RCC_APB2Periph_GPIOA

Definition at line 256 of file stm3210b_eval.h.

#define sFLASH_SPI_MOSI_GPIO_PORT GPIOA

Definition at line 255 of file stm3210b_eval.h.

#define sFLASH_SPI_MOSI_PIN GPIO_Pin_7

Definition at line 254 of file stm3210b_eval.h.

#define sFLASH_SPI_SCK_GPIO_CLK RCC_APB2Periph_GPIOA

Definition at line 250 of file stm3210b_eval.h.

#define sFLASH_SPI_SCK_GPIO_PORT GPIOA

Definition at line 249 of file stm3210b_eval.h.

#define sFLASH_SPI_SCK_PIN GPIO_Pin_5

Definition at line 248 of file stm3210b_eval.h.


STM32F10x Standard Peripherals Firmware Library: STM3210B_EVAL_LOW_LEVEL_TSENSOR_I2C

Defines

STM3210B_EVAL_LOW_LEVEL_TSENSOR_I2C

STM3210B_EVAL_LOW_LEVEL_Exported_Constants

Defines

#define | LM75_DMA_CLK RCC_AHBPeriph_DMA1
#define | LM75_DMA_RX_CHANNEL DMA1_Channel7
#define | LM75_DMA_RX_TCFLAG DMA1_FLAG_TC7
#define | LM75_DMA_TX_CHANNEL DMA1_Channel6
#define | LM75_DMA_TX_TCFLAG DMA1_FLAG_TC6
#define | LM75_I2C I2C1
LM75 Temperature Sensor I2C Interface pins.
#define | LM75_I2C_CLK RCC_APB1Periph_I2C1
#define | LM75_I2C_DR ((uint32_t)0x40005410)
#define | LM75_I2C_SCL_GPIO_CLK RCC_APB2Periph_GPIOB
#define | LM75_I2C_SCL_GPIO_PORT GPIOB
#define | LM75_I2C_SCL_PIN GPIO_Pin_6
#define | LM75_I2C_SDA_GPIO_CLK RCC_APB2Periph_GPIOB
#define | LM75_I2C_SDA_GPIO_PORT GPIOB
#define | LM75_I2C_SDA_PIN GPIO_Pin_7
#define | LM75_I2C_SMBUSALERT_GPIO_CLK RCC_APB2Periph_GPIOB
#define | LM75_I2C_SMBUSALERT_GPIO_PORT GPIOB
#define | LM75_I2C_SMBUSALERT_PIN GPIO_Pin_5

Define Documentation

#define LM75_DMA_CLK RCC_AHBPeriph_DMA1

Definition at line 284 of file stm3210b_eval.h.

#define LM75_DMA_RX_CHANNEL DMA1_Channel7

Definition at line 286 of file stm3210b_eval.h.

#define LM75_DMA_RX_TCFLAG DMA1_FLAG_TC7

Definition at line 288 of file stm3210b_eval.h.

#define LM75_DMA_TX_CHANNEL DMA1_Channel6

Definition at line 285 of file stm3210b_eval.h.

#define LM75_DMA_TX_TCFLAG DMA1_FLAG_TC6

Definition at line 287 of file stm3210b_eval.h.

#define LM75_I2C I2C1

LM75 Temperature Sensor I2C Interface pins.

Definition at line 271 of file stm3210b_eval.h.

#define LM75_I2C_CLK RCC_APB1Periph_I2C1

Definition at line 272 of file stm3210b_eval.h.

#define LM75_I2C_DR ((uint32_t)0x40005410)

Definition at line 282 of file stm3210b_eval.h.

#define LM75_I2C_SCL_GPIO_CLK RCC_APB2Periph_GPIOB

Definition at line 275 of file stm3210b_eval.h.

#define LM75_I2C_SCL_GPIO_PORT GPIOB

Definition at line 274 of file stm3210b_eval.h.

#define LM75_I2C_SCL_PIN GPIO_Pin_6

Definition at line 273 of file stm3210b_eval.h.

#define LM75_I2C_SDA_GPIO_CLK RCC_APB2Periph_GPIOB

Definition at line 278 of file stm3210b_eval.h.

#define LM75_I2C_SDA_GPIO_PORT GPIOB

Definition at line 277 of file stm3210b_eval.h.

#define LM75_I2C_SDA_PIN GPIO_Pin_7

Definition at line 276 of file stm3210b_eval.h.

#define LM75_I2C_SMBUSALERT_GPIO_CLK RCC_APB2Periph_GPIOB

Definition at line 281 of file stm3210b_eval.h.

#define LM75_I2C_SMBUSALERT_GPIO_PORT GPIOB

Definition at line 280 of file stm3210b_eval.h.

#define LM75_I2C_SMBUSALERT_PIN GPIO_Pin_5

Definition at line 279 of file stm3210b_eval.h.


STM32F10x Standard Peripherals Firmware Library: STM3210B_EVAL_LOW_LEVEL_Exported_Macros

STM3210B_EVAL_LOW_LEVEL_Exported_Macros

STM3210B_EVAL_LOW_LEVEL


STM32F10x Standard Peripherals Firmware Library: STM3210B_EVAL_LOW_LEVEL_Exported_Functions

Functions

STM3210B_EVAL_LOW_LEVEL_Exported_Functions

STM3210B_EVAL_LOW_LEVEL

Functions

void | LM75_LowLevel_DeInit (void)
DeInitializes the LM75_I2C.
void | LM75_LowLevel_Init (void)
Initializes the LM75_I2C.
void | SD_LowLevel_DeInit (void)
DeInitializes the SD/SD communication.
void | SD_LowLevel_Init (void)
Initializes the SD_SPI and CS pins.
void | sFLASH_LowLevel_DeInit (void)
DeInitializes the peripherals used by the SPI FLASH driver.
void | sFLASH_LowLevel_Init (void)
Initializes the peripherals used by the SPI FLASH driver.
void | STM_EVAL_COMInit (COM_TypeDef COM, USART_InitTypeDef *USART_InitStruct)
Configures COM port.
void | STM_EVAL_LEDInit (Led_TypeDef Led)
Configures LED GPIO.
void | STM_EVAL_LEDOff (Led_TypeDef Led)
Turns selected LED Off.
void | STM_EVAL_LEDOn (Led_TypeDef Led)
Turns selected LED On.
void | STM_EVAL_LEDToggle (Led_TypeDef Led)
Toggles the selected LED.
uint32_t | STM_EVAL_PBGetState (Button_TypeDef Button)
Returns the selected Button state.
void | STM_EVAL_PBInit (Button_TypeDef Button, ButtonMode_TypeDef Button_Mode)
Configures Button GPIO and EXTI Line.

Function Documentation

void LM75_LowLevel_DeInit ( void )

DeInitializes the LM75_I2C.

Parameters:
None
Return values:
None

< Disable LM75_I2C

< DeInitializes the LM75_I2C

< LM75_I2C Periph clock disable

< Configure LM75_I2C pins: SCL

< Configure LM75_I2C pins: SDA

< Configure LM75_I2C pin: SMBUS ALERT

< Disable LM75_I2C

< DeInitializes the LM75_I2C

< LM75_I2C Periph clock disable

< Configure LM75_I2C pins: SCL

< Configure LM75_I2C pins: SDA

< Configure LM75_I2C pin: SMBUS ALERT

< Disable LM75_I2C

< DeInitializes the LM75_I2C

< LM75_I2C Periph clock disable

< Configure LM75_I2C pins: SCL

< Configure LM75_I2C pins: SDA

< Configure LM75_I2C pin: SMBUS ALERT

< Disable LM75_I2C

< DeInitializes the LM75_I2C

< LM75_I2C Periph clock disable

< Configure LM75_I2C pins: SCL

< Configure LM75_I2C pins: SDA

< Configure LM75_I2C pin: SMBUS ALERT

< Disable LM75_I2C

< DeInitializes the LM75_I2C

< LM75_I2C Periph clock disable

< Configure LM75_I2C pins: SCL

< Configure LM75_I2C pins: SDA

< Configure LM75_I2C pin: SMBUS ALERT

Definition at line 544 of file stm32100b_eval.c.

void LM75_LowLevel_Init ( void )

Initializes the LM75_I2C.

Parameters:
None
Return values:
None
Parameters:
None
Return values:
None

< LM75_I2C Periph clock enable

< LM75_I2C_SCL_GPIO_CLK, LM75_I2C_SDA_GPIO_CLK and LM75_I2C_SMBUSALERT_GPIO_CLK Periph clock enable

< Configure LM75_I2C pins: SCL

< Configure LM75_I2C pins: SDA

< Configure LM75_I2C pin: SMBUS ALERT

< LM75_I2C Periph clock enable

< LM75_I2C_SCL_GPIO_CLK, LM75_I2C_SDA_GPIO_CLK and LM75_I2C_SMBUSALERT_GPIO_CLK Periph clock enable

< Configure LM75_I2C pins: SCL

< Configure LM75_I2C pins: SDA

< Configure LM75_I2C pin: SMBUS ALERT

< LM75_I2C Periph clock enable

< LM75_I2C_SCL_GPIO_CLK, LM75_I2C_SDA_GPIO_CLK and LM75_I2C_SMBUSALERT_GPIO_CLK Periph clock enable

< Configure LM75_I2C pins: SCL

< Configure LM75_I2C pins: SDA

< Configure LM75_I2C pin: SMBUS ALERT

< LM75_I2C Periph clock enable

< LM75_I2C_SCL_GPIO_CLK, LM75_I2C_SDA_GPIO_CLK and LM75_I2C_SMBUSALERT_GPIO_CLK Periph clock enable

< Configure LM75_I2C pins: SCL

< Configure LM75_I2C pins: SDA

< Configure LM75_I2C pin: SMBUS ALERT

< LM75_I2C Periph clock enable

< LM75_I2C_SCL_GPIO_CLK, LM75_I2C_SDA_GPIO_CLK and LM75_I2C_SMBUSALERT_GPIO_CLK Periph clock enable

< Configure LM75_I2C pins: SCL

< Configure LM75_I2C pins: SDA

< Configure LM75_I2C pin: SMBUS ALERT

Definition at line 575 of file stm32100b_eval.c.

void SD_LowLevel_DeInit ( void )

DeInitializes the SD/SD communication.

Parameters:
None
Return values:
None DeInitializes the SD/SD communication.
Parameters:
None
Return values:
None

< SD_SPI disable

< DeInitializes the SD_SPI

< SD_SPI Periph clock disable

< Configure SD_SPI pins: SCK

< Configure SD_SPI pins: MISO

< Configure SD_SPI pins: MOSI

< Configure SD_SPI_CS_PIN pin: SD Card CS pin

< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin

< SD_SPI disable

< DeInitializes the SD_SPI

< SD_SPI Periph clock disable

< Configure SD_SPI pins: SCK

< Configure SD_SPI pins: MISO

< Configure SD_SPI pins: MOSI

< Configure SD_SPI_CS_PIN pin: SD Card CS pin

< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin

< SD_SPI disable

< DeInitializes the SD_SPI

< SD_SPI Periph clock disable

< Configure SD_SPI pins: SCK

< Configure SD_SPI pins: MISO

< Configure SD_SPI pins: MOSI

< Configure SD_SPI_CS_PIN pin: SD Card CS pin

< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin

< SD_SPI disable

< DeInitializes the SD_SPI

< SD_SPI Periph clock disable

< DeRemap SPI3 Pins

< Configure SD_SPI pins: SCK

< Configure SD_SPI pins: MISO

< Configure SD_SPI pins: MOSI

< Configure SD_SPI_CS_PIN pin: SD Card CS pin

< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin

< Disable SDIO Clock

< Set Power State to OFF

< DeInitializes the SDIO peripheral

< Disable the SDIO AHB Clock

< Configure PC.08, PC.09, PC.10, PC.11, PC.12 pin: D0, D1, D2, D3, CLK pin

< Configure PD.02 CMD line

< SD_SPI disable

< DeInitializes the SD_SPI

< SD_SPI Periph clock disable

< Configure SD_SPI pins: SCK

< Configure SD_SPI pins: MISO

< Configure SD_SPI pins: MOSI

< Configure SD_SPI_CS_PIN pin: SD Card CS pin

< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin

Definition at line 373 of file stm32100b_eval.c.

void SD_LowLevel_Init ( void )

Initializes the SD_SPI and CS pins.

Parameters:
None
Return values:
None Initializes the SD_SPI and CS pins.
Parameters:
None
Return values:
None

< SD_SPI_CS_GPIO, SD_SPI_MOSI_GPIO, SD_SPI_MISO_GPIO, SD_SPI_DETECT_GPIO and SD_SPI_SCK_GPIO Periph clock enable

< SD_SPI Periph clock enable

< Configure SD_SPI pins: SCK

< Configure SD_SPI pins: MOSI

< Configure SD_SPI pins: MISO

< Configure SD_SPI_CS_PIN pin: SD Card CS pin

< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin

< SD_SPI Config

< SD_SPI enable

< SD_SPI_CS_GPIO, SD_SPI_MOSI_GPIO, SD_SPI_MISO_GPIO, SD_SPI_DETECT_GPIO and SD_SPI_SCK_GPIO Periph clock enable

< SD_SPI Periph clock enable

< Configure SD_SPI pins: SCK

< Configure SD_SPI pins: MOSI

< Configure SD_SPI pins: MISO

< Configure SD_SPI_CS_PIN pin: SD Card CS pin

< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin

< SD_SPI Config

< SD_SPI enable

< SD_SPI_CS_GPIO, SD_SPI_MOSI_GPIO, SD_SPI_MISO_GPIO, SD_SPI_DETECT_GPIO and SD_SPI_SCK_GPIO Periph clock enable

< SD_SPI Periph clock enable

< Configure SD_SPI pins: SCK

< Configure SD_SPI pins: MOSI

< Configure SD_SPI pins: MISO

< Configure SD_SPI_CS_PIN pin: SD Card CS pin

< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin

< SD_SPI Config

< SD_SPI enable

< SD_SPI_CS_GPIO, SD_SPI_MOSI_GPIO, SD_SPI_MISO_GPIO, SD_SPI_DETECT_GPIO and SD_SPI_SCK_GPIO Periph clock enable

< SD_SPI Periph clock enable

< AFIO Periph clock enable

< Remap SPI3 Pins

< Configure SD_SPI pins: SCK

< Configure SD_SPI pins: MOSI

< Configure SD_SPI pins: MISO

< Configure SD_SPI_CS_PIN pin: SD Card CS pin

< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin

< SD_SPI Config

< SD_SPI enable

< GPIOC and GPIOD Periph clock enable

< Configure PC.08, PC.09, PC.10, PC.11, PC.12 pin: D0, D1, D2, D3, CLK pin

< Configure PD.02 CMD line

< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin

< Enable the SDIO AHB Clock

< Enable the DMA2 Clock

< SD_SPI_CS_GPIO, SD_SPI_MOSI_GPIO, SD_SPI_MISO_GPIO, SD_SPI_DETECT_GPIO and SD_SPI_SCK_GPIO Periph clock enable

< SD_SPI Periph clock enable

< Configure SD_SPI pins: SCK

< Configure SD_SPI pins: MISO

< Configure SD_SPI pins: MOSI

< Configure SD_SPI_CS_PIN pin: SD Card CS pin

< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin

< SD_SPI Config

< SD_SPI enable

Definition at line 410 of file stm32100b_eval.c.

void sFLASH_LowLevel_DeInit ( void )

DeInitializes the peripherals used by the SPI FLASH driver.

Parameters:
None
Return values:
None

< Disable the sFLASH_SPI

< DeInitializes the sFLASH_SPI

< sFLASH_SPI Periph clock disable

< Configure sFLASH_SPI pins: SCK

< Configure sFLASH_SPI pins: MISO

< Configure sFLASH_SPI pins: MOSI

< Configure sFLASH_CS_PIN pin: sFLASH Card CS pin

< Disable the sFLASH_SPI

< DeInitializes the sFLASH_SPI

< sFLASH_SPI Periph clock disable

< Configure sFLASH_SPI pins: SCK

< Configure sFLASH_SPI pins: MISO

< Configure sFLASH_SPI pins: MOSI

< Configure sFLASH_CS_PIN pin: sFLASH Card CS pin

< Disable the sFLASH_SPI

< DeInitializes the sFLASH_SPI

< sFLASH_SPI Periph clock disable

< Configure sFLASH_SPI pins: SCK

< Configure sFLASH_SPI pins: MISO

< Configure sFLASH_SPI pins: MOSI

< Configure sFLASH_CS_PIN pin: sFLASH Card CS pin

< Disable the sFLASH_SPI

< DeInitializes the sFLASH_SPI

< sFLASH_SPI Periph clock disable

< Configure sFLASH_SPI pins: SCK

< Configure sFLASH_SPI pins: MISO

< Configure sFLASH_SPI pins: MOSI

< Configure sFLASH_CS_PIN pin: sFLASH Card CS pin

Definition at line 470 of file stm32100b_eval.c.

void sFLASH_LowLevel_Init ( void )

Initializes the peripherals used by the SPI FLASH driver.

Parameters:
None
Return values:
None

< sFLASH_SPI_CS_GPIO, sFLASH_SPI_MOSI_GPIO, sFLASH_SPI_MISO_GPIO and sFLASH_SPI_SCK_GPIO Periph clock enable

< sFLASH_SPI Periph clock enable

< Configure sFLASH_SPI pins: SCK

< Configure sFLASH_SPI pins: MOSI

< Configure sFLASH_SPI pins: MISO

< Configure sFLASH_CS_PIN pin: sFLASH Card CS pin

< sFLASH_SPI_CS_GPIO, sFLASH_SPI_MOSI_GPIO, sFLASH_SPI_MISO_GPIO and sFLASH_SPI_SCK_GPIO Periph clock enable

< sFLASH_SPI Periph clock enable

< Configure sFLASH_SPI pins: SCK

< Configure sFLASH_SPI pins: MOSI

< Configure sFLASH_SPI pins: MISO

< Configure sFLASH_CS_PIN pin: sFLASH Card CS pin

< sFLASH_SPI_CS_GPIO, sFLASH_SPI_MOSI_GPIO, sFLASH_SPI_MISO_GPIO and sFLASH_SPI_SCK_GPIO Periph clock enable

< sFLASH_SPI Periph clock enable

< Configure sFLASH_SPI pins: SCK

< Configure sFLASH_SPI pins: MOSI

< Configure sFLASH_SPI pins: MISO

< Configure sFLASH_CS_PIN pin: sFLASH Card CS pin

< sFLASH_SPI_CS_GPIO, sFLASH_SPI_MOSI_GPIO, sFLASH_SPI_MISO_GPIO and sFLASH_SPI_SCK_GPIO Periph clock enable

< sFLASH_SPI Periph clock enable

< Configure sFLASH_SPI pins: SCK

< Configure sFLASH_SPI pins: MOSI

< Configure sFLASH_SPI pins: MISO

< Configure sFLASH_CS_PIN pin: sFLASH Card CS pin

Definition at line 506 of file stm32100b_eval.c.

void STM_EVAL_COMInit | ( | COM_TypeDef | COM,
 |  | USART_InitTypeDef * | USART_InitStruct
 | ) |  |

Configures COM port.

Parameters:
COM,: Specifies the COM port to be configured. This parameter can be one of following parameters:

  • COM1
  • COM2
USART_InitStruct,: pointer to a USART_InitTypeDef structure that contains the configuration information for the specified USART peripheral.
Return values:
None

Definition at line 330 of file stm32100b_eval.c.

void STM_EVAL_LEDInit ( Led_TypeDef Led )

Configures LED GPIO.

Parameters:
Led,: Specifies the Led to be configured. This parameter can be one of following parameters:

  • LED1
  • LED2
  • LED3
  • LED4
Return values:
None

Definition at line 176 of file stm32100b_eval.c.

void STM_EVAL_LEDOff ( Led_TypeDef Led )

Turns selected LED Off.

Parameters:
Led,: Specifies the Led to be set off. This parameter can be one of following parameters:

  • LED1
  • LED2
  • LED3
  • LED4
Return values:
None

Definition at line 216 of file stm32100b_eval.c.

void STM_EVAL_LEDOn ( Led_TypeDef Led )

Turns selected LED On.

Parameters:
Led,: Specifies the Led to be set on. This parameter can be one of following parameters:

  • LED1
  • LED2
  • LED3
  • LED4
Return values:
None

Definition at line 201 of file stm32100b_eval.c.

void STM_EVAL_LEDToggle ( Led_TypeDef Led )

Toggles the selected LED.

Parameters:
Led,: Specifies the Led to be toggled. This parameter can be one of following parameters:

  • LED1
  • LED2
  • LED3
  • LED4
Return values:
None

Definition at line 231 of file stm32100b_eval.c.

uint32_t STM_EVAL_PBGetState ( Button_TypeDef Button )

Returns the selected Button state.

Parameters:
Button,: Specifies the Button to be checked. This parameter can be one of following parameters:

  • BUTTON_WAKEUP: Wakeup Push Button
  • BUTTON_TAMPER: Tamper Push Button
  • BUTTON_KEY: Key Push Button
  • BUTTON_RIGHT: Joystick Right Push Button
  • BUTTON_LEFT: Joystick Left Push Button
  • BUTTON_UP: Joystick Up Push Button
  • BUTTON_DOWN: Joystick Down Push Button
  • BUTTON_SEL: Joystick Sel Push Button
Return values:
The Button GPIO pin value.
Parameters:
Button,: Specifies the Button to be checked. This parameter can be one of following parameters:

  • BUTTON_KEY: Key Push Button
  • BUTTON_RIGHT: Joystick Right Push Button
  • BUTTON_LEFT: Joystick Left Push Button
  • BUTTON_UP: Joystick Up Push Button
  • BUTTON_DOWN: Joystick Down Push Button
  • BUTTON_SEL: Joystick Sel Push Button
Return values:
- When Button > 1, the Button GPIO pin value is returned.

  • When Button = 0 or 1, error code (0xFF) is returned.

Definition at line 314 of file stm32100b_eval.c.

void STM_EVAL_PBInit | ( | Button_TypeDef | Button,
 |  | ButtonMode_TypeDef | Button_Mode
 | ) |  |

Configures Button GPIO and EXTI Line.

Parameters:
Button,: Specifies the Button to be configured. This parameter can be one of following parameters:

  • BUTTON_WAKEUP: Wakeup Push Button
  • BUTTON_TAMPER: Tamper Push Button
  • BUTTON_KEY: Key Push Button
  • BUTTON_RIGHT: Joystick Right Push Button
  • BUTTON_LEFT: Joystick Left Push Button
  • BUTTON_UP: Joystick Up Push Button
  • BUTTON_DOWN: Joystick Down Push Button
  • BUTTON_SEL: Joystick Sel Push Button
Button_Mode,: Specifies Button mode. This parameter can be one of following parameters:

  • BUTTON_MODE_GPIO: Button will be used as simple IO
  • BUTTON_MODE_EXTI: Button will be connected to EXTI line with interrupt generation capability
Return values:
None
Parameters:
Button,: Specifies the Button to be configured. This parameter can be one of following parameters:

  • BUTTON_KEY: Key Push Button
  • BUTTON_RIGHT: Joystick Right Push Button
  • BUTTON_LEFT: Joystick Left Push Button
  • BUTTON_UP: Joystick Up Push Button
  • BUTTON_DOWN: Joystick Down Push Button
  • BUTTON_SEL: Joystick Sel Push Button
Button_Mode,: Specifies Button mode. This parameter can be one of following parameters:

  • BUTTON_MODE_GPIO: Button will be used as simple IO
  • BUTTON_MODE_EXTI: Button will be connected to EXTI line with interrupt generation capability
Return values:
None

Definition at line 255 of file stm32100b_eval.c.


STM32F10x Standard Peripherals Firmware Library: STM3210B_EVAL_LCD_Private_Types

STM3210B_EVAL_LCD_Private_Types

STM3210B_EVAL_LCD


STM32F10x Standard Peripherals Firmware Library: STM3210B_EVAL_LCD_Private_Defines

Defines

STM3210B_EVAL_LCD_Private_Defines

STM3210B_EVAL_LCD

Defines

#define | LCD_HX8312 0x8312
#define | LCD_ILI9320 0x9320
#define | LCD_READ_REG 0x03
#define | LCD_SPFD5408 0x5408
#define | LCD_WRITE_REG 0x02
#define | MAX_POLY_CORNERS 200
#define | POLY_X(Z) ((int32_t)((Points + Z)->Y))
#define | POLY_Y(Z) ((int32_t)((Points + Z)->X))
#define | READ_STATUS 0x01
#define | SET_INDEX 0x00
#define | START_BYTE 0x70

Define Documentation

#define LCD_HX8312 0x8312

Definition at line 59 of file stm3210b_eval_lcd.c.

Referenced by LCD_DisplayOff(), LCD_DisplayOn(), LCD_DrawCircle(), LCD_DrawLine(), LCD_PowerOn(), LCD_SetCursor(), LCD_SetDisplayWindow(), LCD_Setup(), LCD_SPIConfig(), LCD_WindowModeDisable(), LCD_WriteRAM(), LCD_WriteReg(), and STM3210B_LCD_Init().

#define LCD_ILI9320 0x9320

Definition at line 58 of file stm3210b_eval_lcd.c.

Referenced by LCD_Clear(), LCD_DisplayOff(), LCD_DisplayOn(), LCD_DrawChar(), LCD_DrawCircle(), LCD_DrawLine(), LCD_DrawMonoPict(), LCD_PowerOn(), LCD_SetCursor(), LCD_SetDisplayWindow(), LCD_Setup(), LCD_SPIConfig(), LCD_WindowModeDisable(), LCD_WriteRAM(), LCD_WriteReg(), and STM3210B_LCD_Init().

#define LCD_READ_REG 0x03

Definition at line 65 of file stm3210b_eval_lcd.c.

Referenced by LCD_ReadReg().

#define LCD_SPFD5408 0x5408

Definition at line 60 of file stm3210b_eval_lcd.c.

Referenced by LCD_Clear(), LCD_DisplayOff(), LCD_DisplayOn(), LCD_DrawChar(), LCD_DrawCircle(), LCD_DrawLine(), LCD_DrawMonoPict(), LCD_PowerOn(), LCD_SetCursor(), LCD_SetDisplayWindow(), LCD_Setup(), LCD_SPIConfig(), LCD_WindowModeDisable(), LCD_WriteRAM(), LCD_WriteReg(), and STM3210B_LCD_Init().

#define LCD_WRITE_REG 0x02

Definition at line 64 of file stm3210b_eval_lcd.c.

Referenced by LCD_WriteRAM_Prepare(), and LCD_WriteRegILI9320().

#define MAX_POLY_CORNERS 200

Definition at line 66 of file stm3210b_eval_lcd.c.

Referenced by LCD_FillPolyLine().

#define POLY_X ( Z ) ((int32_t)((Points + Z)->Y))

Definition at line 68 of file stm3210b_eval_lcd.c.

Referenced by LCD_FillPolyLine().

#define POLY_Y ( Z ) ((int32_t)((Points + Z)->X))

Definition at line 67 of file stm3210b_eval_lcd.c.

Referenced by LCD_FillPolyLine().

#define READ_STATUS 0x01

Definition at line 63 of file stm3210b_eval_lcd.c.

#define SET_INDEX 0x00

Definition at line 62 of file stm3210b_eval_lcd.c.

Referenced by LCD_WriteRegIndex().

#define START_BYTE 0x70

Definition at line 61 of file stm3210b_eval_lcd.c.

Referenced by LCD_ReadReg(), LCD_WriteRAM_Prepare(), LCD_WriteRegILI9320(), and LCD_WriteRegIndex().


STM32F10x Standard Peripherals Firmware Library: STM3210B_EVAL_LCD_Private_Macros

Defines

STM3210B_EVAL_LCD_Private_Macros

STM3210B_EVAL_LCD

Defines

#define ABS(X) ((X) > 0 ? (X) : -(X))

Define Documentation

#define ABS ( X ) ((X) > 0 ? (X) : -(X))

Definition at line 77 of file stm3210b_eval_lcd.c.

Referenced by LCD_DrawUniLine().


STM32F10x Standard Peripherals Firmware Library: STM3210B_EVAL_LCD_Private_Variables

Variables

STM3210B_EVAL_LCD_Private_Variables

STM3210B_EVAL_LCD

Variables

static __IO uint16_t | BackColor = 0xFFFF
static sFONT * | LCD_Currentfonts
static __IO uint32_t | LCDType = LCD_ILI9320
static __IO uint16_t | TextColor = 0x0000

Variable Documentation

__IO uint16_t BackColor = 0xFFFF

Definition at line 88 of file stm3210b_eval_lcd.c.

sFONT* LCD_Currentfonts [static]

Definition at line 86 of file stm3210b_eval_lcd.c.

Referenced by LCD_GetFont().

__IO uint32_t LCDType = LCD_ILI9320 [static]

Definition at line 89 of file stm3210b_eval_lcd.c.

Referenced by LCD_Clear(), LCD_DisplayOff(), LCD_DisplayOn(), LCD_DrawChar(), LCD_DrawCircle(), LCD_DrawLine(), LCD_DrawMonoPict(), LCD_PowerOn(), LCD_SetCursor(), LCD_SetDisplayWindow(), LCD_Setup(), LCD_SPIConfig(), LCD_WindowModeDisable(), LCD_WriteRAM(), LCD_WriteReg(), and STM3210B_LCD_Init().

__IO uint16_t TextColor = 0x0000 [static]

Definition at line 88 of file stm3210b_eval_lcd.c.

Referenced by LCD_DrawChar(), LCD_DrawCircle(), LCD_DrawFullCircle(), LCD_DrawFullRect(), LCD_DrawLine(), LCD_DrawMonoPict(), LCD_FillPolyLine(), LCD_GetColors(), LCD_SetColors(), and LCD_SetTextColor().


STM32F10x Standard Peripherals Firmware Library: STM3210B_EVAL_LCD_Private_Function_Prototypes

STM3210B_EVAL_LCD_Private_Function_Prototypes

STM3210B_EVAL_LCD


STM32F10x Standard Peripherals Firmware Library: STM3210B_EVAL_LCD_Private_Functions

Functions

STM3210B_EVAL_LCD_Private_Functions

STM3210B_EVAL_LCD

Functions

static void | delay (vu32 nCount)
Inserts a delay time.
void | LCD_Clear (uint16_t Color)
Clears the hole LCD.
void | LCD_ClearLine (uint8_t Line)
Clears the selected line.
void | LCD_ClosedPolyLine (pPoint Points, uint16_t PointCount)
Displays a closed polyline (between many points).
void | LCD_ClosedPolyLineRelative (pPoint Points, uint16_t PointCount)
Displays a closed relative polyline (between many points).
void | LCD_CtrlLinesConfig (void)
Configures LCD control lines in Output Push-Pull mode.
void | LCD_CtrlLinesWrite (GPIO_TypeDef *GPIOx, uint16_t CtrlPins, BitAction BitVal)
Sets or reset LCD control lines.
void | LCD_DeInit (void)
DeInitializes the LCD.
void | LCD_DisplayChar (uint8_t Line, uint16_t Column, uint8_t Ascii)
Displays one character (16dots width, 24dots height).
void | LCD_DisplayOff (void)
Disables the Display.
void | LCD_DisplayOn (void)
Enables the Display.
void | LCD_DisplayStringLine (uint8_t Line, uint8_t *ptr)
Displays a maximum of 20 char on the LCD.
void | LCD_DrawChar (uint8_t Xpos, uint16_t Ypos, const uint16_t *c)
Draws a character on LCD.
void | LCD_DrawCircle (uint8_t Xpos, uint16_t Ypos, uint16_t Radius)
Displays a circle.
void | LCD_DrawFullCircle (uint16_t Xpos, uint16_t Ypos, uint16_t Radius)
Displays a full circle.
void | LCD_DrawFullRect (uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height)
Displays a full rectangle.
void | LCD_DrawLine (uint8_t Xpos, uint16_t Ypos, uint16_t Length, uint8_t Direction)
Displays a line.
void | LCD_DrawMonoPict (const uint32_t *Pict)
Displays a monocolor picture.
void | LCD_DrawRect (uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width)
Displays a rectangle.
void | LCD_DrawUniLine (uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2)
Displays an uni line (between two points).
void | LCD_FillPolyLine (pPoint Points, uint16_t PointCount)
Displays a full polyline (between many points).
void | LCD_GetColors (__IO uint16_t *_TextColor, __IO uint16_t *_BackColor)
Gets the LCD Text and Background colors.
sFONT * | LCD_GetFont (void)
Gets the Text Font.
void | LCD_nCS_StartByte (uint8_t Start_Byte)
Reset LCD control line(/CS) and Send Start-Byte.
void | LCD_PolyLine (pPoint Points, uint16_t PointCount)
Displays an polyline (between many points).
void | LCD_PolyLineRelative (pPoint Points, uint16_t PointCount)
Displays a relative polyline (between many points).
static void | LCD_PolyLineRelativeClosed (pPoint Points, uint16_t PointCount, uint16_t Closed)
Displays an relative polyline (between many points).
void | LCD_PowerOn (void)
Power on the LCD.
uint16_t | LCD_ReadReg (uint8_t LCD_Reg)
Reads the selected LCD Register.
void | LCD_SetBackColor (__IO uint16_t Color)
Sets the Background color.
void | LCD_SetColors (__IO uint16_t _TextColor, __IO uint16_t _BackColor)
Sets the LCD Text and Background colors.
void | LCD_SetCursor (uint8_t Xpos, uint16_t Ypos)
Sets the cursor position.
void | LCD_SetDisplayWindow (uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width)
Sets a display window.
void | LCD_SetFont (sFONT *fonts)
Sets the Text Font.
void | LCD_SetTextColor (__IO uint16_t Color)
Sets the Text color.
void | LCD_Setup (void)
Setups the LCD.
void | LCD_SPIConfig (void)
Configures the LCD_SPI interface.
void | LCD_WindowModeDisable (void)
Disables LCD Window mode.
void | LCD_WriteRAM (uint16_t RGB_Code)
Writes to the LCD RAM.
void | LCD_WriteRAM_Prepare (void)
Prepare to write to the LCD RAM.
void | LCD_WriteRAMWord (uint16_t RGB_Code)
Writes 1 word to the LCD RAM.
void | LCD_WriteReg (uint8_t LCD_Reg, uint16_t LCD_RegValue)
Writes to the selected LCD register.
static void | LCD_WriteRegHX8312 (uint8_t LCD_Reg, uint8_t LCD_RegValue)
Writes to the selected LCD HX8312 register.
static void | LCD_WriteRegILI9320 (uint8_t LCD_Reg, uint16_t LCD_RegValue)
Writes to the selected LCD ILI9320 register.
void | LCD_WriteRegIndex (uint8_t LCD_Reg)
Writes index to select the LCD register.
static void | PutPixel (int16_t x, int16_t y)
Displays a pixel.
void | STM3210B_LCD_Init (void)
Initializes the LCD.

Function Documentation

static void delay ( vu32 nCount ) [static]

Inserts a delay time.

Parameters:
nCount,: specifies the delay time length.
Return values:
None

Definition at line 1850 of file stm3210b_eval_lcd.c.

References index.

void LCD_Clear ( uint16_t Color )

Clears the hole LCD.

Parameters:
Color,: the color of the background.
Return values:
None

Definition at line 547 of file stm3210b_eval_lcd.c.

References Bit_SET, index, LCD_CtrlLinesWrite(), LCD_ILI9320, LCD_NCS_GPIO_PORT, LCD_NCS_PIN, LCD_SetCursor(), LCD_SPFD5408, LCD_WriteRAM(), LCD_WriteRAM_Prepare(), and LCDType.

void LCD_ClearLine ( uint8_t Line )

Clears the selected line.

Parameters:
Line,: the Line to be cleared. This parameter can be one of the following values:

  • Linex: where x can be 0..n
Return values:
None

Definition at line 528 of file stm3210b_eval_lcd.c.

References LCD_DisplayChar(), LCD_PIXEL_WIDTH, and _tFont::Width.

void LCD_ClosedPolyLine | ( | pPoint | Points,
 |  | uint16_t | PointCount
 | ) |  |

Displays a closed polyline (between many points).

Parameters:
Points,: pointer to the points array.
PointCount,: Number of points.
Return values:
None

Definition at line 1240 of file stm3210b_eval_lcd.c.

References LCD_DrawUniLine(), LCD_PolyLine(), Point::X, and Point::Y.

void LCD_ClosedPolyLineRelative | ( | pPoint | Points,
 |  | uint16_t | PointCount
 | ) |  |

Displays a closed relative polyline (between many points).

Parameters:
Points,: pointer to the points array.
PointCount,: Number of points.
Return values:
None

Definition at line 1263 of file stm3210b_eval_lcd.c.

References LCD_PolyLineRelativeClosed().

void LCD_CtrlLinesConfig ( void )

Configures LCD control lines in Output Push-Pull mode.

Parameters:
None
Return values:
None

Definition at line 1728 of file stm3210b_eval_lcd.c.

References Bit_SET, ENABLE, GPIO_Init(), GPIO_InitStructure, GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_Out_PP, GPIO_InitTypeDef::GPIO_Pin, GPIO_InitTypeDef::GPIO_Speed, GPIO_Speed_50MHz, LCD_CtrlLinesWrite(), LCD_NCS_GPIO_CLK, LCD_NCS_GPIO_PORT, LCD_NCS_PIN, LCD_NWR_GPIO_CLK, LCD_NWR_GPIO_PORT, LCD_NWR_PIN, LCD_RS_GPIO_CLK, LCD_RS_GPIO_PORT, LCD_RS_PIN, and RCC_APB2PeriphClockCmd().

void LCD_CtrlLinesWrite | ( | GPIO_TypeDef * | GPIOx,
 |  | uint16_t | CtrlPins,
 |  | BitAction | BitVal
 | ) |  |

Sets or reset LCD control lines.

Parameters:
GPIOx,: where x can be B or D to select the GPIO peripheral.
CtrlPins,: the Control line. This parameter can be:

  • LCD_NCS_PIN: Chip Select pin
  • LCD_NWR_PIN: Read/Write Selection pin
  • LCD_RS_PIN: Register/RAM Selection pin
BitVal,: specifies the value to be written to the selected bit. This parameter can be:

  • Bit_RESET: to clear the port pin
  • Bit_SET: to set the port pin
Return values:
None

Definition at line 1767 of file stm3210b_eval_lcd.c.

References GPIO_WriteBit().

void LCD_DeInit ( void )

DeInitializes the LCD.

Parameters:
None
Return values:
None

< LCD Display Off

< LCD_SPI disable

< LCD_SPI DeInit

< Disable SPI clock

Definition at line 120 of file stm3210b_eval_lcd.c.

References DISABLE, GPIO_Init(), GPIO_InitStructure, GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_IN_FLOATING, GPIO_InitTypeDef::GPIO_Pin, LCD_DisplayOff(), LCD_NCS_GPIO_PORT, LCD_NCS_PIN, LCD_NWR_GPIO_PORT, LCD_NWR_PIN, LCD_RS_GPIO_PORT, LCD_RS_PIN, LCD_SPI, LCD_SPI_CLK, LCD_SPI_MISO_GPIO_PORT, LCD_SPI_MISO_PIN, LCD_SPI_MOSI_GPIO_PORT, LCD_SPI_MOSI_PIN, LCD_SPI_SCK_GPIO_PORT, LCD_SPI_SCK_PIN, RCC_APB1PeriphClockCmd(), SPI_Cmd(), and SPI_I2S_DeInit().

void LCD_DisplayChar | ( | uint8_t | Line,
 |  | uint16_t | Column,
 |  | uint8_t | Ascii
 | ) |  |

Displays one character (16dots width, 24dots height).

Parameters:
Line,: the Line where to display the character shape . This parameter can be one of the following values:

  • Linex: where x can be 0..9
Column,: start column address.
Ascii,: character ascii code, must be between 0x20 and 0x7E.
Return values:
None

Definition at line 643 of file stm3210b_eval_lcd.c.

References _tFont::Height, LCD_DrawChar(), and _tFont::table.

void LCD_DisplayOff ( void )

Disables the Display.

Parameters:
None
Return values:
None

Definition at line 1706 of file stm3210b_eval_lcd.c.

References _delay_, LCD_HX8312, LCD_ILI9320, LCD_REG_0, LCD_REG_59, LCD_REG_7, LCD_SPFD5408, LCD_WriteReg(), and LCDType.

void LCD_DisplayOn ( void )

Enables the Display.

Parameters:
None
Return values:
None

Definition at line 1681 of file stm3210b_eval_lcd.c.

References _delay_, LCD_HX8312, LCD_ILI9320, LCD_REG_0, LCD_REG_1, LCD_REG_5, LCD_REG_59, LCD_REG_7, LCD_SPFD5408, LCD_WriteReg(), and LCDType.

void LCD_DisplayStringLine | ( | uint8_t | Line,
 |  | uint8_t * | ptr
 | ) |  |

Displays a maximum of 20 char on the LCD.

Parameters:
Line,: the Line where to display the character shape . This parameter can be one of the following values:

  • Linex: where x can be 0..9
*ptr,: pointer to string to display on LCD.
Return values:
None

Definition at line 658 of file stm3210b_eval_lcd.c.

References LCD_DisplayChar(), LCD_PIXEL_WIDTH, and _tFont::Width.

void LCD_DrawChar | ( | uint8_t | Xpos,
 |  | uint16_t | Ypos,
 |  | const uint16_t * | c
 | ) |  |

Draws a character on LCD.

Parameters:
Xpos,: the Line where to display the character shape.
Ypos,: start column address.
c,: pointer to the character data.
Return values:
None

Definition at line 596 of file stm3210b_eval_lcd.c.

References BackColor, Bit_SET, _tFont::Height, index, LCD_CtrlLinesWrite(), LCD_ILI9320, LCD_NCS_GPIO_PORT, LCD_NCS_PIN, LCD_SetCursor(), LCD_SPFD5408, LCD_WriteRAM(), LCD_WriteRAM_Prepare(), LCDType, TextColor, and _tFont::Width.

void LCD_DrawCircle | ( | uint8_t | Xpos,
 |  | uint16_t | Ypos,
 |  | uint16_t | Radius
 | ) |  |

Displays a circle.

Parameters:
Xpos,: specifies the X position.
Ypos,: specifies the Y position.
Radius
Return values:
None

Definition at line 821 of file stm3210b_eval_lcd.c.

References LCD_HX8312, LCD_ILI9320, LCD_SetCursor(), LCD_SPFD5408, LCD_WriteRAM(), LCD_WriteRAMWord(), LCDType, and TextColor.

void LCD_DrawFullCircle | ( | uint16_t | Xpos,
 |  | uint16_t | Ypos,
 |  | uint16_t | Radius
 | ) |  |

Displays a full circle.

Parameters:
Xpos,: specifies the X position.
Ypos,: specifies the Y position.
Radius
Return values:
None

Definition at line 1061 of file stm3210b_eval_lcd.c.

References BackColor, LCD_DIR_HORIZONTAL, LCD_DrawCircle(), LCD_DrawLine(), LCD_SetTextColor(), and TextColor.

void LCD_DrawFullRect | ( | uint16_t | Xpos,
 |  | uint16_t | Ypos,
 |  | uint16_t | Width,
 |  | uint16_t | Height
 | ) |  |

Displays a full rectangle.

Parameters:
Xpos,: specifies the X position.
Ypos,: specifies the Y position.
Height,: rectangle height.
Width,: rectangle width.
Return values:
None

Definition at line 1030 of file stm3210b_eval_lcd.c.

References BackColor, LCD_DIR_HORIZONTAL, LCD_DIR_VERTICAL, LCD_DrawLine(), LCD_SetTextColor(), and TextColor.

void LCD_DrawLine | ( | uint8_t | Xpos,
 |  | uint16_t | Ypos,
 |  | uint16_t | Length,
 |  | uint8_t | Direction
 | ) |  |

Displays a line.

Parameters:
Xpos,: specifies the X position.
Ypos,: specifies the Y position.
Length,: line length.
Direction,: line direction. This parameter can be one of the following values: Vertical or Horizontal.
Return values:
None

Definition at line 757 of file stm3210b_eval_lcd.c.

References Bit_SET, LCD_CtrlLinesWrite(), LCD_DIR_HORIZONTAL, LCD_HX8312, LCD_ILI9320, LCD_NCS_GPIO_PORT, LCD_NCS_PIN, LCD_SetCursor(), LCD_SPFD5408, LCD_WriteRAM(), LCD_WriteRAM_Prepare(), LCD_WriteRAMWord(), LCDType, and TextColor.

void LCD_DrawMonoPict ( const uint32_t * Pict )

Displays a monocolor picture.

Parameters:
Pict,: pointer to the picture array.
Return values:
None

Definition at line 930 of file stm3210b_eval_lcd.c.

References BackColor, Bit_SET, index, LCD_CtrlLinesWrite(), LCD_ILI9320, LCD_NCS_GPIO_PORT, LCD_NCS_PIN, LCD_PIXEL_WIDTH, LCD_SetCursor(), LCD_SPFD5408, LCD_WriteRAM(), LCD_WriteRAM_Prepare(), LCDType, and TextColor.

void LCD_DrawRect | ( | uint8_t | Xpos,
 |  | uint16_t | Ypos,
 |  | uint8_t | Height,
 |  | uint16_t | Width
 | ) |  |

Displays a rectangle.

Parameters:
Xpos,: specifies the X position.
Ypos,: specifies the Y position.
Height,: display rectangle height.
Width,: display rectangle width.
Return values:
None

Definition at line 804 of file stm3210b_eval_lcd.c.

References LCD_DIR_HORIZONTAL, LCD_DIR_VERTICAL, and LCD_DrawLine().

void LCD_DrawUniLine | ( | uint16_t | x1,
 |  | uint16_t | y1,
 |  | uint16_t | x2,
 |  | uint16_t | y2
 | ) |  |

Displays an uni line (between two points).

Parameters:
x1,: specifies the point 1 x position.
y1,: specifies the point 1 y position.
x2,: specifies the point 2 x position.
y2,: specifies the point 2 y position.
Return values:
None

Definition at line 1111 of file stm3210b_eval_lcd.c.

References ABS, and PutPixel().

void LCD_FillPolyLine | ( | pPoint | Points,
 |  | uint16_t | PointCount
 | ) |  |

Displays a full polyline (between many points).

Parameters:
Points,: pointer to the points array.
PointCount,: Number of points.
Return values:
None

Definition at line 1275 of file stm3210b_eval_lcd.c.

References BackColor, j, LCD_DIR_HORIZONTAL, LCD_DrawLine(), LCD_SetTextColor(), MAX_POLY_CORNERS, POLY_X, POLY_Y, PutPixel(), TextColor, Point::X, and Point::Y.

void LCD_GetColors | ( | __IO uint16_t * | _TextColor,
 |  | __IO uint16_t * | _BackColor
 | ) |  |

Gets the LCD Text and Background colors.

Parameters:
_TextColor,: pointer to the variable that will contain the Text Color.
_BackColor,: pointer to the variable that will contain the Background Color.
Return values:
None

Definition at line 475 of file stm3210b_eval_lcd.c.

References BackColor, and TextColor.

sFONT* LCD_GetFont ( void )

Gets the Text Font.

Parameters:
None.
Return values:
the used font.

Definition at line 516 of file stm3210b_eval_lcd.c.

References LCD_Currentfonts.

void LCD_nCS_StartByte ( uint8_t Start_Byte )

Reset LCD control line(/CS) and Send Start-Byte.

Parameters:
Start_Byte,: the Start-Byte to be sent
Return values:
None

Definition at line 1381 of file stm3210b_eval_lcd.c.

References Bit_RESET, LCD_CtrlLinesWrite(), LCD_NCS_GPIO_PORT, LCD_NCS_PIN, LCD_SPI, RESET, SPI_I2S_FLAG_BSY, SPI_I2S_GetFlagStatus(), and SPI_I2S_SendData().

void LCD_PolyLine | ( | pPoint | Points,
 |  | uint16_t | PointCount
 | ) |  |

Displays an polyline (between many points).

Parameters:
Points,: pointer to the points array.
PointCount,: Number of points.
Return values:
None

Definition at line 1184 of file stm3210b_eval_lcd.c.

References LCD_DrawUniLine(), Point::X, and Point::Y.

void LCD_PolyLineRelative | ( | pPoint | Points,
 |  | uint16_t | PointCount
 | ) |  |

Displays a relative polyline (between many points).

Parameters:
Points,: pointer to the points array.
PointCount,: Number of points.
Return values:
None

Definition at line 1252 of file stm3210b_eval_lcd.c.

References LCD_PolyLineRelativeClosed().

static void LCD_PolyLineRelativeClosed | ( | pPoint | Points,
 |  | uint16_t | PointCount,
 |  | uint16_t | Closed
 | ) |  | [static]

Displays an relative polyline (between many points).

Parameters:
Points,: pointer to the points array.
PointCount,: Number of points.
Closed,: specifies if the draw is closed or not. 1: closed, 0 : not closed.
Return values:
None

Definition at line 1210 of file stm3210b_eval_lcd.c.

References LCD_DrawUniLine(), Point::X, and Point::Y.

Referenced by LCD_ClosedPolyLineRelative(), and LCD_PolyLineRelative().

void LCD_PowerOn ( void )

Power on the LCD.

Parameters:
None
Return values:
None

Definition at line 1633 of file stm3210b_eval_lcd.c.

References _delay_, LCD_HX8312, LCD_ILI9320, LCD_REG_16, LCD_REG_17, LCD_REG_18, LCD_REG_19, LCD_REG_24, LCD_REG_27, LCD_REG_28, LCD_REG_30, LCD_REG_31, LCD_REG_32, LCD_REG_36, LCD_REG_41, LCD_REG_7, LCD_SPFD5408, LCD_WriteReg(), and LCDType.

uint16_t LCD_ReadReg ( uint8_t LCD_Reg )

Reads the selected LCD Register.

Parameters:
LCD_Reg,: address of the selected register.
Return values:
LCD Register Value.

Definition at line 1456 of file stm3210b_eval_lcd.c.

References Bit_SET, LCD_CtrlLinesWrite(), LCD_NCS_GPIO_PORT, LCD_NCS_PIN, LCD_nCS_StartByte(), LCD_READ_REG, LCD_SPI, LCD_WriteRegIndex(), RESET, SPI_I2S_FLAG_BSY, SPI_I2S_FLAG_RXNE, SPI_I2S_GetFlagStatus(), SPI_I2S_ReceiveData(), SPI_I2S_SendData(), and START_BYTE.

void LCD_SetBackColor ( __IO uint16_t Color )

Sets the Background color.

Parameters:
Color,: specifies the Background color code RGB(5-6-5).
Return values:
None

Definition at line 496 of file stm3210b_eval_lcd.c.

References BackColor.

void LCD_SetColors | ( | __IO uint16_t | _TextColor,
 |  | __IO uint16_t | _BackColor
 | ) |  |

Sets the LCD Text and Background colors.

Parameters:
_TextColor,: specifies the Text Color.
_BackColor,: specifies the Background Color.
Return values:
None

Definition at line 461 of file stm3210b_eval_lcd.c.

References BackColor, and TextColor.

void LCD_SetCursor | ( | uint8_t | Xpos,
 |  | uint16_t | Ypos
 | ) |  |

Sets the cursor position.

Parameters:
Xpos,: specifies the X position.
Ypos,: specifies the Y position.
Return values:
None

Definition at line 573 of file stm3210b_eval_lcd.c.

References LCD_HX8312, LCD_ILI9320, LCD_REG_32, LCD_REG_33, LCD_REG_66, LCD_REG_67, LCD_REG_68, LCD_SPFD5408, LCD_WriteReg(), and LCDType.

void LCD_SetDisplayWindow | ( | uint8_t | Xpos,
 |  | uint16_t | Ypos,
 |  | uint8_t | Height,
 |  | uint16_t | Width
 | ) |  |

Sets a display window.

Parameters:
Xpos,: specifies the X buttom left position.
Ypos,: specifies the Y buttom left position.
Height,: display window height.
Width,: display window width.
Return values:
None

Definition at line 683 of file stm3210b_eval_lcd.c.

References LCD_HX8312, LCD_ILI9320, LCD_REG_1, LCD_REG_5, LCD_REG_69, LCD_REG_70, LCD_REG_71, LCD_REG_72, LCD_REG_73, LCD_REG_74, LCD_REG_80, LCD_REG_81, LCD_REG_82, LCD_REG_83, LCD_SetCursor(), LCD_SPFD5408, LCD_WriteReg(), and LCDType.

void LCD_SetFont ( sFONT * fonts )

Sets the Text Font.

Parameters:
fonts,: specifies the font to be used.
Return values:
None

Definition at line 506 of file stm3210b_eval_lcd.c.

void LCD_SetTextColor ( __IO uint16_t Color )

Sets the Text color.

Parameters:
Color,: specifies the Text color code RGB(5-6-5).
Return values:
None

Definition at line 485 of file stm3210b_eval_lcd.c.

References TextColor.

void LCD_Setup ( void )

Setups the LCD.

Parameters:
None
Return values:
None

Definition at line 164 of file stm3210b_eval_lcd.c.

References _delay_, LCD_CtrlLinesConfig(), LCD_HX8312, LCD_ILI9320, LCD_REG_0, LCD_REG_1, LCD_REG_10, LCD_REG_106, LCD_REG_118, LCD_REG_12, LCD_REG_128, LCD_REG_129, LCD_REG_13, LCD_REG_130, LCD_REG_131, LCD_REG_132, LCD_REG_133, LCD_REG_134, LCD_REG_135, LCD_REG_136, LCD_REG_137, LCD_REG_139, LCD_REG_14, LCD_REG_141, LCD_REG_143, LCD_REG_144, LCD_REG_145, LCD_REG_146, LCD_REG_147, LCD_REG_148, LCD_REG_149, LCD_REG_15, LCD_REG_150, LCD_REG_151, LCD_REG_152, LCD_REG_153, LCD_REG_154, LCD_REG_157, LCD_REG_16, LCD_REG_17, LCD_REG_18, LCD_REG_19, LCD_REG_192, LCD_REG_2, LCD_REG_20, LCD_REG_21, LCD_REG_22, LCD_REG_227, LCD_REG_229, LCD_REG_23, LCD_REG_231, LCD_REG_239, LCD_REG_24, LCD_REG_25, LCD_REG_26, LCD_REG_27, LCD_REG_28, LCD_REG_29, LCD_REG_3, LCD_REG_30, LCD_REG_31, LCD_REG_32, LCD_REG_33, LCD_REG_36, LCD_REG_37, LCD_REG_4, LCD_REG_40, LCD_REG_41, LCD_REG_43, LCD_REG_48, LCD_REG_49, LCD_REG_5, LCD_REG_50, LCD_REG_51, LCD_REG_52, LCD_REG_53, LCD_REG_54, LCD_REG_55, LCD_REG_56, LCD_REG_57, LCD_REG_59, LCD_REG_60, LCD_REG_61, LCD_REG_62, LCD_REG_63, LCD_REG_64, LCD_REG_65, LCD_REG_66, LCD_REG_67, LCD_REG_68, LCD_REG_69, LCD_REG_7, LCD_REG_70, LCD_REG_71, LCD_REG_72, LCD_REG_73, LCD_REG_74, LCD_REG_75, LCD_REG_76, LCD_REG_78, LCD_REG_79, LCD_REG_8, LCD_REG_80, LCD_REG_81, LCD_REG_82, LCD_REG_83, LCD_REG_9, LCD_REG_96, LCD_REG_97, LCD_SPFD5408, LCD_SPIConfig(), LCD_WriteReg(), and LCDType.

void LCD_SPIConfig ( void )

Configures the LCD_SPI interface.

Parameters:
None
Return values:
None

Definition at line 1778 of file stm3210b_eval_lcd.c.

References ENABLE, GPIO_Init(), GPIO_InitStructure, GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_AF_PP, GPIO_InitTypeDef::GPIO_Pin, GPIO_InitTypeDef::GPIO_Speed, GPIO_Speed_50MHz, LCD_HX8312, LCD_ILI9320, LCD_SPFD5408, LCD_SPI, LCD_SPI_CLK, LCD_SPI_MISO_GPIO_CLK, LCD_SPI_MISO_GPIO_PORT, LCD_SPI_MISO_PIN, LCD_SPI_MOSI_GPIO_CLK, LCD_SPI_MOSI_GPIO_PORT, LCD_SPI_MOSI_PIN, LCD_SPI_SCK_GPIO_CLK, LCD_SPI_SCK_GPIO_PORT, LCD_SPI_SCK_PIN, LCDType, RCC_APB1PeriphClockCmd(), RCC_APB2PeriphClockCmd(), SPI_InitTypeDef::SPI_BaudRatePrescaler, SPI_BaudRatePrescaler_2, SPI_Cmd(), SPI_InitTypeDef::SPI_CPHA, SPI_CPHA_1Edge, SPI_CPHA_2Edge, SPI_InitTypeDef::SPI_CPOL, SPI_CPOL_High, SPI_CPOL_Low, SPI_InitTypeDef::SPI_DataSize, SPI_DataSize_16b, SPI_DataSize_8b, SPI_InitTypeDef::SPI_Direction, SPI_Direction_2Lines_FullDuplex, SPI_InitTypeDef::SPI_FirstBit, SPI_FirstBit_MSB, SPI_I2S_DeInit(), SPI_Init(), SPI_InitStructure, SPI_InitTypeDef::SPI_Mode, SPI_Mode_Master, SPI_InitTypeDef::SPI_NSS, and SPI_NSS_Soft.

void LCD_WindowModeDisable ( void )

Disables LCD Window mode.

Parameters:
None
Return values:
None

Definition at line 732 of file stm3210b_eval_lcd.c.

References LCD_HX8312, LCD_ILI9320, LCD_REG_1, LCD_REG_3, LCD_REG_5, LCD_SetDisplayWindow(), LCD_SPFD5408, LCD_WriteReg(), and LCDType.

void LCD_WriteRAM ( uint16_t RGB_Code )

Writes to the LCD RAM.

Parameters:
RGB_Code,: the pixel color in RGB mode (5-6-5).
Return values:
None

Definition at line 1598 of file stm3210b_eval_lcd.c.

References Bit_RESET, Bit_SET, LCD_CtrlLinesWrite(), LCD_HX8312, LCD_ILI9320, LCD_NCS_GPIO_PORT, LCD_NCS_PIN, LCD_NWR_GPIO_PORT, LCD_NWR_PIN, LCD_RS_GPIO_PORT, LCD_RS_PIN, LCD_SPFD5408, LCD_SPI, LCDType, RESET, SPI_I2S_FLAG_BSY, SPI_I2S_GetFlagStatus(), and SPI_I2S_SendData().

void LCD_WriteRAM_Prepare ( void )

Prepare to write to the LCD RAM.

Parameters:
None
Return values:
None

Definition at line 1522 of file stm3210b_eval_lcd.c.

References LCD_nCS_StartByte(), LCD_REG_34, LCD_WRITE_REG, LCD_WriteRegIndex(), and START_BYTE.

void LCD_WriteRAMWord ( uint16_t RGB_Code )

Writes 1 word to the LCD RAM.

Parameters:
RGB_Code,: the pixel color in RGB mode (5-6-5).
Return values:
None

Definition at line 1536 of file stm3210b_eval_lcd.c.

References Bit_SET, LCD_CtrlLinesWrite(), LCD_NCS_GPIO_PORT, LCD_NCS_PIN, LCD_WriteRAM(), and LCD_WriteRAM_Prepare().

void LCD_WriteReg | ( | uint8_t | LCD_Reg,
 |  | uint16_t | LCD_RegValue
 | ) |  |

Writes to the selected LCD register.

Parameters:
LCD_Reg,: address of the selected register.
LCD_RegValue,: value to write to the selected register.
Return values:
None

Definition at line 1580 of file stm3210b_eval_lcd.c.

References LCD_HX8312, LCD_ILI9320, LCD_SPFD5408, LCD_WriteRegHX8312(), LCD_WriteRegILI9320(), and LCDType.

static void LCD_WriteRegHX8312 | ( | uint8_t | LCD_Reg,
 |  | uint8_t | LCD_RegValue
 | ) |  | [static]

Writes to the selected LCD HX8312 register.

Parameters:
LCD_Reg,: address of the selected register.
LCD_RegValue,: value to write to the selected register.
Return values:
None

Definition at line 1553 of file stm3210b_eval_lcd.c.

References Bit_RESET, Bit_SET, LCD_CtrlLinesWrite(), LCD_NCS_GPIO_PORT, LCD_NCS_PIN, LCD_NWR_GPIO_PORT, LCD_NWR_PIN, LCD_RS_GPIO_PORT, LCD_RS_PIN, LCD_SPI, RESET, SPI_I2S_FLAG_BSY, SPI_I2S_GetFlagStatus(), and SPI_I2S_SendData().

Referenced by LCD_WriteReg().

static void LCD_WriteRegILI9320 | ( | uint8_t | LCD_Reg,
 |  | uint16_t | LCD_RegValue
 | ) |  | [static]

Writes to the selected LCD ILI9320 register.

Parameters:
LCD_Reg,: address of the selected register.
LCD_RegValue,: value to write to the selected register.
Return values:
None

Definition at line 1426 of file stm3210b_eval_lcd.c.

References Bit_SET, LCD_CtrlLinesWrite(), LCD_NCS_GPIO_PORT, LCD_NCS_PIN, LCD_nCS_StartByte(), LCD_SPI, LCD_WRITE_REG, LCD_WriteRegIndex(), RESET, SPI_I2S_FLAG_BSY, SPI_I2S_GetFlagStatus(), SPI_I2S_SendData(), and START_BYTE.

Referenced by LCD_WriteReg().

void LCD_WriteRegIndex ( uint8_t LCD_Reg )

Writes index to select the LCD register.

Parameters:
LCD_Reg,: address of the selected register.
Return values:
None

Definition at line 1398 of file stm3210b_eval_lcd.c.

References Bit_SET, LCD_CtrlLinesWrite(), LCD_NCS_GPIO_PORT, LCD_NCS_PIN, LCD_nCS_StartByte(), LCD_SPI, RESET, SET_INDEX, SPI_I2S_FLAG_BSY, SPI_I2S_GetFlagStatus(), SPI_I2S_SendData(), and START_BYTE.

static void PutPixel | ( | int16_t | x,
 |  | int16_t | y
 | ) |  | [static]

Displays a pixel.

Parameters:
x,: pixel x.
y,: pixel y.
Return values:
None

Definition at line 1835 of file stm3210b_eval_lcd.c.

References LCD_DIR_HORIZONTAL, and LCD_DrawLine().

Referenced by LCD_DrawUniLine(), and LCD_FillPolyLine().

void STM3210B_LCD_Init ( void )

Initializes the LCD.

Parameters:
None
Return values:
None

Definition at line 430 of file stm3210b_eval_lcd.c.

References LCD_DEFAULT_FONT, LCD_HX8312, LCD_ILI9320, LCD_ReadReg(), LCD_REG_0, LCD_SetFont(), LCD_Setup(), LCD_SPFD5408, and LCDType.

Referenced by main().


STM32F10x Standard Peripherals Firmware Library: STM3210B_EVAL_LCD_Exported_Types

Data Structures | Typedefs

STM3210B_EVAL_LCD_Exported_Types

STM3210B_EVAL_LCD

Data Structures

struct | Point

Typedefs

typedef struct Point * | pPoint

Typedef Documentation

typedef struct Point * pPoint


STM32F10x Standard Peripherals Firmware Library: STM3210B_EVAL_LCD_Exported_Constants

Defines

STM3210B_EVAL_LCD_Exported_Constants

STM3210B_EVAL_LCD

Defines

#define | _delay_ delay
Uncomment the line below if you want to use LCD_DrawBMP function to display a bitmap picture on the LCD.
#define | LCD_COLOR_BLACK 0x0000
#define | LCD_COLOR_BLUE 0x001F
#define | LCD_COLOR_BLUE2 0x051F
#define | LCD_COLOR_CYAN 0x7FFF
#define | LCD_COLOR_GREEN 0x07E0
#define | LCD_COLOR_GREY 0xF7DE
#define | LCD_COLOR_MAGENTA 0xF81F
#define | LCD_COLOR_RED 0xF800
#define | LCD_COLOR_WHITE 0xFFFF
LCD color.
#define | LCD_COLOR_YELLOW 0xFFE0
#define | LCD_DEFAULT_FONT Font16x24
LCD default font.
#define | LCD_DIR_HORIZONTAL 0x0000
LCD Direction.
#define | LCD_DIR_VERTICAL 0x0001
#define | LCD_LINE_0 LINE(0)
LCD Lines depending on the chosen fonts.
#define | LCD_LINE_1 LINE(1)
#define | LCD_LINE_10 LINE(10)
#define | LCD_LINE_11 LINE(11)
#define | LCD_LINE_12 LINE(12)
#define | LCD_LINE_13 LINE(13)
#define | LCD_LINE_14 LINE(14)
#define | LCD_LINE_15 LINE(15)
#define | LCD_LINE_16 LINE(16)
#define | LCD_LINE_17 LINE(17)
#define | LCD_LINE_18 LINE(18)
#define | LCD_LINE_19 LINE(19)
#define | LCD_LINE_2 LINE(2)
#define | LCD_LINE_20 LINE(20)
#define | LCD_LINE_21 LINE(21)
#define | LCD_LINE_22 LINE(22)
#define | LCD_LINE_23 LINE(23)
#define | LCD_LINE_24 LINE(24)
#define | LCD_LINE_25 LINE(25)
#define | LCD_LINE_26 LINE(26)
#define | LCD_LINE_27 LINE(27)
#define | LCD_LINE_28 LINE(28)
#define | LCD_LINE_29 LINE(29)
#define | LCD_LINE_3 LINE(3)
#define | LCD_LINE_4 LINE(4)
#define | LCD_LINE_5 LINE(5)
#define | LCD_LINE_6 LINE(6)
#define | LCD_LINE_7 LINE(7)
#define | LCD_LINE_8 LINE(8)
#define | LCD_LINE_9 LINE(9)
#define | LCD_NCS_GPIO_CLK RCC_APB2Periph_GPIOB
#define | LCD_NCS_GPIO_PORT GPIOB
#define | LCD_NCS_PIN GPIO_Pin_2
LCD Control pins.
#define | LCD_NWR_GPIO_CLK RCC_APB2Periph_GPIOD
#define | LCD_NWR_GPIO_PORT GPIOD
#define | LCD_NWR_PIN GPIO_Pin_15
#define | LCD_PIXEL_HEIGHT 0x00F0
#define | LCD_PIXEL_WIDTH 0x0140
LCD Size (Width and Height)
#define | LCD_REG_0 0x00
LCD Registers.
#define | LCD_REG_1 0x01
#define | LCD_REG_10 0x0A
#define | LCD_REG_106 0x6A
#define | LCD_REG_118 0x76
#define | LCD_REG_12 0x0C
#define | LCD_REG_128 0x80
#define | LCD_REG_129 0x81
#define | LCD_REG_13 0x0D
#define | LCD_REG_130 0x82
#define | LCD_REG_131 0x83
#define | LCD_REG_132 0x84
#define | LCD_REG_133 0x85
#define | LCD_REG_134 0x86
#define | LCD_REG_135 0x87
#define | LCD_REG_136 0x88
#define | LCD_REG_137 0x89
#define | LCD_REG_139 0x8B
#define | LCD_REG_14 0x0E
#define | LCD_REG_140 0x8C
#define | LCD_REG_141 0x8D
#define | LCD_REG_143 0x8F
#define | LCD_REG_144 0x90
#define | LCD_REG_145 0x91
#define | LCD_REG_146 0x92
#define | LCD_REG_147 0x93
#define | LCD_REG_148 0x94
#define | LCD_REG_149 0x95
#define | LCD_REG_15 0x0F
#define | LCD_REG_150 0x96
#define | LCD_REG_151 0x97
#define | LCD_REG_152 0x98
#define | LCD_REG_153 0x99
#define | LCD_REG_154 0x9A
#define | LCD_REG_157 0x9D
#define | LCD_REG_16 0x10
#define | LCD_REG_17 0x11
#define | LCD_REG_18 0x12
#define | LCD_REG_19 0x13
#define | LCD_REG_192 0xC0
#define | LCD_REG_193 0xC1
#define | LCD_REG_2 0x02
#define | LCD_REG_20 0x14
#define | LCD_REG_21 0x15
#define | LCD_REG_22 0x16
#define | LCD_REG_227 0xE3
#define | LCD_REG_229 0xE5
#define | LCD_REG_23 0x17
#define | LCD_REG_231 0xE7
#define | LCD_REG_239 0xEF
#define | LCD_REG_24 0x18
#define | LCD_REG_25 0x19
#define | LCD_REG_26 0x1A
#define | LCD_REG_27 0x1B
#define | LCD_REG_28 0x1C
#define | LCD_REG_29 0x1D
#define | LCD_REG_3 0x03
#define | LCD_REG_30 0x1E
#define | LCD_REG_31 0x1F
#define | LCD_REG_32 0x20
#define | LCD_REG_33 0x21
#define | LCD_REG_34 0x22
#define | LCD_REG_36 0x24
#define | LCD_REG_37 0x25
#define | LCD_REG_4 0x04
#define | LCD_REG_40 0x28
#define | LCD_REG_41 0x29
#define | LCD_REG_43 0x2B
#define | LCD_REG_45 0x2D
#define | LCD_REG_48 0x30
#define | LCD_REG_49 0x31
#define | LCD_REG_5 0x05
#define | LCD_REG_50 0x32
#define | LCD_REG_51 0x33
#define | LCD_REG_52 0x34
#define | LCD_REG_53 0x35
#define | LCD_REG_54 0x36
#define | LCD_REG_55 0x37
#define | LCD_REG_56 0x38
#define | LCD_REG_57 0x39
#define | LCD_REG_59 0x3B
#define | LCD_REG_6 0x06
#define | LCD_REG_60 0x3C
#define | LCD_REG_61 0x3D
#define | LCD_REG_62 0x3E
#define | LCD_REG_63 0x3F
#define | LCD_REG_64 0x40
#define | LCD_REG_65 0x41
#define | LCD_REG_66 0x42
#define | LCD_REG_67 0x43
#define | LCD_REG_68 0x44
#define | LCD_REG_69 0x45
#define | LCD_REG_7 0x07
#define | LCD_REG_70 0x46
#define | LCD_REG_71 0x47
#define | LCD_REG_72 0x48
#define | LCD_REG_73 0x49
#define | LCD_REG_74 0x4A
#define | LCD_REG_75 0x4B
#define | LCD_REG_76 0x4C
#define | LCD_REG_77 0x4D
#define | LCD_REG_78 0x4E
#define | LCD_REG_79 0x4F
#define | LCD_REG_8 0x08
#define | LCD_REG_80 0x50
#define | LCD_REG_81 0x51
#define | LCD_REG_82 0x52
#define | LCD_REG_83 0x53
#define | LCD_REG_9 0x09
#define | LCD_REG_96 0x60
#define | LCD_REG_97 0x61
#define | LCD_RS_GPIO_CLK RCC_APB2Periph_GPIOD
#define | LCD_RS_GPIO_PORT GPIOD
#define | LCD_RS_PIN GPIO_Pin_7
#define | LCD_SPI SPI2
LCD SPI Interface pins.
#define | LCD_SPI_CLK RCC_APB1Periph_SPI2
#define | LCD_SPI_MISO_GPIO_CLK RCC_APB2Periph_GPIOB
#define | LCD_SPI_MISO_GPIO_PORT GPIOB
#define | LCD_SPI_MISO_PIN GPIO_Pin_14
#define | LCD_SPI_MOSI_GPIO_CLK RCC_APB2Periph_GPIOB
#define | LCD_SPI_MOSI_GPIO_PORT GPIOB
#define | LCD_SPI_MOSI_PIN GPIO_Pin_15
#define | LCD_SPI_SCK_GPIO_CLK RCC_APB2Periph_GPIOB
#define | LCD_SPI_SCK_GPIO_PORT GPIOB
#define | LCD_SPI_SCK_PIN GPIO_Pin_13

Define Documentation

#define _delay_ delay

Uncomment the line below if you want to use LCD_DrawBMP function to display a bitmap picture on the LCD.

This function assumes that the bitmap file is loaded in the SPI Flash (mounted on STM3210B-EVAL board), however user can tailor it according to his application hardware requirement. Uncomment the line below if you want to use user defined Delay function (for precise timing), otherwise default _delay_ function defined within this driver is used (less precise timing).

Definition at line 91 of file stm3210b_eval_lcd.h.

#define LCD_COLOR_BLACK 0x0000

Definition at line 243 of file stm3210b_eval_lcd.h.

#define LCD_COLOR_BLUE 0x001F

Definition at line 245 of file stm3210b_eval_lcd.h.

#define LCD_COLOR_BLUE2 0x051F

Definition at line 246 of file stm3210b_eval_lcd.h.

#define LCD_COLOR_CYAN 0x7FFF

Definition at line 250 of file stm3210b_eval_lcd.h.

#define LCD_COLOR_GREEN 0x07E0

Definition at line 249 of file stm3210b_eval_lcd.h.

#define LCD_COLOR_GREY 0xF7DE

Definition at line 244 of file stm3210b_eval_lcd.h.

#define LCD_COLOR_MAGENTA 0xF81F

Definition at line 248 of file stm3210b_eval_lcd.h.

#define LCD_COLOR_RED 0xF800

Definition at line 247 of file stm3210b_eval_lcd.h.

#define LCD_COLOR_WHITE 0xFFFF

LCD color.

Definition at line 242 of file stm3210b_eval_lcd.h.

#define LCD_COLOR_YELLOW 0xFFE0

Definition at line 251 of file stm3210b_eval_lcd.h.

#define LCD_DEFAULT_FONT Font16x24

LCD default font.

Definition at line 290 of file stm3210b_eval_lcd.h.

#define LCD_DIR_HORIZONTAL 0x0000

LCD Direction.

Definition at line 295 of file stm3210b_eval_lcd.h.

#define LCD_DIR_VERTICAL 0x0001

Definition at line 296 of file stm3210b_eval_lcd.h.

#define LCD_LINE_0 LINE(0)

LCD Lines depending on the chosen fonts.

Definition at line 256 of file stm3210b_eval_lcd.h.

#define LCD_LINE_1 LINE(1)

Definition at line 257 of file stm3210b_eval_lcd.h.

#define LCD_LINE_10 LINE(10)

Definition at line 266 of file stm3210b_eval_lcd.h.

#define LCD_LINE_11 LINE(11)

Definition at line 267 of file stm3210b_eval_lcd.h.

#define LCD_LINE_12 LINE(12)

Definition at line 268 of file stm3210b_eval_lcd.h.

#define LCD_LINE_13 LINE(13)

Definition at line 269 of file stm3210b_eval_lcd.h.

#define LCD_LINE_14 LINE(14)

Definition at line 270 of file stm3210b_eval_lcd.h.

#define LCD_LINE_15 LINE(15)

Definition at line 271 of file stm3210b_eval_lcd.h.

#define LCD_LINE_16 LINE(16)

Definition at line 272 of file stm3210b_eval_lcd.h.

#define LCD_LINE_17 LINE(17)

Definition at line 273 of file stm3210b_eval_lcd.h.

#define LCD_LINE_18 LINE(18)

Definition at line 274 of file stm3210b_eval_lcd.h.

#define LCD_LINE_19 LINE(19)

Definition at line 275 of file stm3210b_eval_lcd.h.

#define LCD_LINE_2 LINE(2)

Definition at line 258 of file stm3210b_eval_lcd.h.

#define LCD_LINE_20 LINE(20)

Definition at line 276 of file stm3210b_eval_lcd.h.

#define LCD_LINE_21 LINE(21)

Definition at line 277 of file stm3210b_eval_lcd.h.

#define LCD_LINE_22 LINE(22)

Definition at line 278 of file stm3210b_eval_lcd.h.

#define LCD_LINE_23 LINE(23)

Definition at line 279 of file stm3210b_eval_lcd.h.

#define LCD_LINE_24 LINE(24)

Definition at line 280 of file stm3210b_eval_lcd.h.

#define LCD_LINE_25 LINE(25)

Definition at line 281 of file stm3210b_eval_lcd.h.

#define LCD_LINE_26 LINE(26)

Definition at line 282 of file stm3210b_eval_lcd.h.

#define LCD_LINE_27 LINE(27)

Definition at line 283 of file stm3210b_eval_lcd.h.

#define LCD_LINE_28 LINE(28)

Definition at line 284 of file stm3210b_eval_lcd.h.

#define LCD_LINE_29 LINE(29)

Definition at line 285 of file stm3210b_eval_lcd.h.

#define LCD_LINE_3 LINE(3)

Definition at line 259 of file stm3210b_eval_lcd.h.

#define LCD_LINE_4 LINE(4)

Definition at line 260 of file stm3210b_eval_lcd.h.

#define LCD_LINE_5 LINE(5)

Definition at line 261 of file stm3210b_eval_lcd.h.

#define LCD_LINE_6 LINE(6)

Definition at line 262 of file stm3210b_eval_lcd.h.

#define LCD_LINE_7 LINE(7)

Definition at line 263 of file stm3210b_eval_lcd.h.

#define LCD_LINE_8 LINE(8)

Definition at line 264 of file stm3210b_eval_lcd.h.

#define LCD_LINE_9 LINE(9)

Definition at line 265 of file stm3210b_eval_lcd.h.

#define LCD_NCS_GPIO_CLK RCC_APB2Periph_GPIOB

Definition at line 100 of file stm3210b_eval_lcd.h.

#define LCD_NCS_GPIO_PORT GPIOB

Definition at line 99 of file stm3210b_eval_lcd.h.

#define LCD_NCS_PIN GPIO_Pin_2

LCD Control pins.

Definition at line 98 of file stm3210b_eval_lcd.h.

#define LCD_NWR_GPIO_CLK RCC_APB2Periph_GPIOD

Definition at line 103 of file stm3210b_eval_lcd.h.

#define LCD_NWR_GPIO_PORT GPIOD

Definition at line 102 of file stm3210b_eval_lcd.h.

#define LCD_NWR_PIN GPIO_Pin_15

Definition at line 101 of file stm3210b_eval_lcd.h.

#define LCD_PIXEL_HEIGHT 0x00F0

Definition at line 302 of file stm3210b_eval_lcd.h.

#define LCD_PIXEL_WIDTH 0x0140

LCD Size (Width and Height)

Definition at line 301 of file stm3210b_eval_lcd.h.

#define LCD_REG_0 0x00

LCD Registers.

Definition at line 126 of file stm3210b_eval_lcd.h.

#define LCD_REG_1 0x01

Definition at line 127 of file stm3210b_eval_lcd.h.

#define LCD_REG_10 0x0A

Definition at line 136 of file stm3210b_eval_lcd.h.

#define LCD_REG_106 0x6A

Definition at line 203 of file stm3210b_eval_lcd.h.

#define LCD_REG_118 0x76

Definition at line 204 of file stm3210b_eval_lcd.h.

#define LCD_REG_12 0x0C

Definition at line 137 of file stm3210b_eval_lcd.h.

#define LCD_REG_128 0x80

Definition at line 205 of file stm3210b_eval_lcd.h.

#define LCD_REG_129 0x81

Definition at line 206 of file stm3210b_eval_lcd.h.

#define LCD_REG_13 0x0D

Definition at line 138 of file stm3210b_eval_lcd.h.

#define LCD_REG_130 0x82

Definition at line 207 of file stm3210b_eval_lcd.h.

#define LCD_REG_131 0x83

Definition at line 208 of file stm3210b_eval_lcd.h.

#define LCD_REG_132 0x84

Definition at line 209 of file stm3210b_eval_lcd.h.

#define LCD_REG_133 0x85

Definition at line 210 of file stm3210b_eval_lcd.h.

#define LCD_REG_134 0x86

Definition at line 211 of file stm3210b_eval_lcd.h.

#define LCD_REG_135 0x87

Definition at line 212 of file stm3210b_eval_lcd.h.

#define LCD_REG_136 0x88

Definition at line 213 of file stm3210b_eval_lcd.h.

#define LCD_REG_137 0x89

Definition at line 214 of file stm3210b_eval_lcd.h.

#define LCD_REG_139 0x8B

Definition at line 215 of file stm3210b_eval_lcd.h.

#define LCD_REG_14 0x0E

Definition at line 139 of file stm3210b_eval_lcd.h.

#define LCD_REG_140 0x8C

Definition at line 216 of file stm3210b_eval_lcd.h.

#define LCD_REG_141 0x8D

Definition at line 217 of file stm3210b_eval_lcd.h.

#define LCD_REG_143 0x8F

Definition at line 218 of file stm3210b_eval_lcd.h.

#define LCD_REG_144 0x90

Definition at line 219 of file stm3210b_eval_lcd.h.

#define LCD_REG_145 0x91

Definition at line 220 of file stm3210b_eval_lcd.h.

#define LCD_REG_146 0x92

Definition at line 221 of file stm3210b_eval_lcd.h.

#define LCD_REG_147 0x93

Definition at line 222 of file stm3210b_eval_lcd.h.

#define LCD_REG_148 0x94

Definition at line 223 of file stm3210b_eval_lcd.h.

#define LCD_REG_149 0x95

Definition at line 224 of file stm3210b_eval_lcd.h.

#define LCD_REG_15 0x0F

Definition at line 140 of file stm3210b_eval_lcd.h.

#define LCD_REG_150 0x96

Definition at line 225 of file stm3210b_eval_lcd.h.

#define LCD_REG_151 0x97

Definition at line 226 of file stm3210b_eval_lcd.h.

#define LCD_REG_152 0x98

Definition at line 227 of file stm3210b_eval_lcd.h.

#define LCD_REG_153 0x99

Definition at line 228 of file stm3210b_eval_lcd.h.

#define LCD_REG_154 0x9A

Definition at line 229 of file stm3210b_eval_lcd.h.

#define LCD_REG_157 0x9D

Definition at line 230 of file stm3210b_eval_lcd.h.

#define LCD_REG_16 0x10

Definition at line 141 of file stm3210b_eval_lcd.h.

#define LCD_REG_17 0x11

Definition at line 142 of file stm3210b_eval_lcd.h.

#define LCD_REG_18 0x12

Definition at line 143 of file stm3210b_eval_lcd.h.

#define LCD_REG_19 0x13

Definition at line 144 of file stm3210b_eval_lcd.h.

#define LCD_REG_192 0xC0

Definition at line 231 of file stm3210b_eval_lcd.h.

#define LCD_REG_193 0xC1

Definition at line 232 of file stm3210b_eval_lcd.h.

#define LCD_REG_2 0x02

Definition at line 128 of file stm3210b_eval_lcd.h.

#define LCD_REG_20 0x14

Definition at line 145 of file stm3210b_eval_lcd.h.

#define LCD_REG_21 0x15

Definition at line 146 of file stm3210b_eval_lcd.h.

#define LCD_REG_22 0x16

Definition at line 147 of file stm3210b_eval_lcd.h.

#define LCD_REG_227 0xE3

Definition at line 233 of file stm3210b_eval_lcd.h.

#define LCD_REG_229 0xE5

Definition at line 234 of file stm3210b_eval_lcd.h.

#define LCD_REG_23 0x17

Definition at line 148 of file stm3210b_eval_lcd.h.

#define LCD_REG_231 0xE7

Definition at line 235 of file stm3210b_eval_lcd.h.

#define LCD_REG_239 0xEF

Definition at line 236 of file stm3210b_eval_lcd.h.

#define LCD_REG_24 0x18

Definition at line 149 of file stm3210b_eval_lcd.h.

#define LCD_REG_25 0x19

Definition at line 150 of file stm3210b_eval_lcd.h.

#define LCD_REG_26 0x1A

Definition at line 151 of file stm3210b_eval_lcd.h.

#define LCD_REG_27 0x1B

Definition at line 152 of file stm3210b_eval_lcd.h.

#define LCD_REG_28 0x1C

Definition at line 153 of file stm3210b_eval_lcd.h.

#define LCD_REG_29 0x1D

Definition at line 154 of file stm3210b_eval_lcd.h.

#define LCD_REG_3 0x03

Definition at line 129 of file stm3210b_eval_lcd.h.

#define LCD_REG_30 0x1E

Definition at line 155 of file stm3210b_eval_lcd.h.

#define LCD_REG_31 0x1F

Definition at line 156 of file stm3210b_eval_lcd.h.

#define LCD_REG_32 0x20

Definition at line 157 of file stm3210b_eval_lcd.h.

#define LCD_REG_33 0x21

Definition at line 158 of file stm3210b_eval_lcd.h.

#define LCD_REG_34 0x22

Definition at line 159 of file stm3210b_eval_lcd.h.

#define LCD_REG_36 0x24

Definition at line 160 of file stm3210b_eval_lcd.h.

#define LCD_REG_37 0x25

Definition at line 161 of file stm3210b_eval_lcd.h.

#define LCD_REG_4 0x04

Definition at line 130 of file stm3210b_eval_lcd.h.

#define LCD_REG_40 0x28

Definition at line 162 of file stm3210b_eval_lcd.h.

#define LCD_REG_41 0x29

Definition at line 163 of file stm3210b_eval_lcd.h.

#define LCD_REG_43 0x2B

Definition at line 164 of file stm3210b_eval_lcd.h.

#define LCD_REG_45 0x2D

Definition at line 165 of file stm3210b_eval_lcd.h.

#define LCD_REG_48 0x30

Definition at line 166 of file stm3210b_eval_lcd.h.

#define LCD_REG_49 0x31

Definition at line 167 of file stm3210b_eval_lcd.h.

#define LCD_REG_5 0x05

Definition at line 131 of file stm3210b_eval_lcd.h.

#define LCD_REG_50 0x32

Definition at line 168 of file stm3210b_eval_lcd.h.

#define LCD_REG_51 0x33

Definition at line 169 of file stm3210b_eval_lcd.h.

#define LCD_REG_52 0x34

Definition at line 170 of file stm3210b_eval_lcd.h.

#define LCD_REG_53 0x35

Definition at line 171 of file stm3210b_eval_lcd.h.

#define LCD_REG_54 0x36

Definition at line 172 of file stm3210b_eval_lcd.h.

#define LCD_REG_55 0x37

Definition at line 173 of file stm3210b_eval_lcd.h.

#define LCD_REG_56 0x38

Definition at line 174 of file stm3210b_eval_lcd.h.

#define LCD_REG_57 0x39

Definition at line 175 of file stm3210b_eval_lcd.h.

#define LCD_REG_59 0x3B

Definition at line 176 of file stm3210b_eval_lcd.h.

#define LCD_REG_6 0x06

Definition at line 132 of file stm3210b_eval_lcd.h.

#define LCD_REG_60 0x3C

Definition at line 177 of file stm3210b_eval_lcd.h.

#define LCD_REG_61 0x3D

Definition at line 178 of file stm3210b_eval_lcd.h.

#define LCD_REG_62 0x3E

Definition at line 179 of file stm3210b_eval_lcd.h.

#define LCD_REG_63 0x3F

Definition at line 180 of file stm3210b_eval_lcd.h.

#define LCD_REG_64 0x40

Definition at line 181 of file stm3210b_eval_lcd.h.

#define LCD_REG_65 0x41

Definition at line 182 of file stm3210b_eval_lcd.h.

#define LCD_REG_66 0x42

Definition at line 183 of file stm3210b_eval_lcd.h.

#define LCD_REG_67 0x43

Definition at line 184 of file stm3210b_eval_lcd.h.

#define LCD_REG_68 0x44

Definition at line 185 of file stm3210b_eval_lcd.h.

#define LCD_REG_69 0x45

Definition at line 186 of file stm3210b_eval_lcd.h.

#define LCD_REG_7 0x07

Definition at line 133 of file stm3210b_eval_lcd.h.

#define LCD_REG_70 0x46

Definition at line 187 of file stm3210b_eval_lcd.h.

#define LCD_REG_71 0x47

Definition at line 188 of file stm3210b_eval_lcd.h.

#define LCD_REG_72 0x48

Definition at line 189 of file stm3210b_eval_lcd.h.

#define LCD_REG_73 0x49

Definition at line 190 of file stm3210b_eval_lcd.h.

#define LCD_REG_74 0x4A

Definition at line 191 of file stm3210b_eval_lcd.h.

#define LCD_REG_75 0x4B

Definition at line 192 of file stm3210b_eval_lcd.h.

#define LCD_REG_76 0x4C

Definition at line 193 of file stm3210b_eval_lcd.h.

#define LCD_REG_77 0x4D

Definition at line 194 of file stm3210b_eval_lcd.h.

#define LCD_REG_78 0x4E

Definition at line 195 of file stm3210b_eval_lcd.h.

#define LCD_REG_79 0x4F

Definition at line 196 of file stm3210b_eval_lcd.h.

#define LCD_REG_8 0x08

Definition at line 134 of file stm3210b_eval_lcd.h.

#define LCD_REG_80 0x50

Definition at line 197 of file stm3210b_eval_lcd.h.

#define LCD_REG_81 0x51

Definition at line 198 of file stm3210b_eval_lcd.h.

#define LCD_REG_82 0x52

Definition at line 199 of file stm3210b_eval_lcd.h.

#define LCD_REG_83 0x53

Definition at line 200 of file stm3210b_eval_lcd.h.

#define LCD_REG_9 0x09

Definition at line 135 of file stm3210b_eval_lcd.h.

#define LCD_REG_96 0x60

Definition at line 201 of file stm3210b_eval_lcd.h.

#define LCD_REG_97 0x61

Definition at line 202 of file stm3210b_eval_lcd.h.

#define LCD_RS_GPIO_CLK RCC_APB2Periph_GPIOD

Definition at line 106 of file stm3210b_eval_lcd.h.

#define LCD_RS_GPIO_PORT GPIOD

Definition at line 105 of file stm3210b_eval_lcd.h.

#define LCD_RS_PIN GPIO_Pin_7

Definition at line 104 of file stm3210b_eval_lcd.h.

#define LCD_SPI SPI2

LCD SPI Interface pins.

Definition at line 111 of file stm3210b_eval_lcd.h.

#define LCD_SPI_CLK RCC_APB1Periph_SPI2

Definition at line 112 of file stm3210b_eval_lcd.h.

#define LCD_SPI_MISO_GPIO_CLK RCC_APB2Periph_GPIOB

Definition at line 118 of file stm3210b_eval_lcd.h.

#define LCD_SPI_MISO_GPIO_PORT GPIOB

Definition at line 117 of file stm3210b_eval_lcd.h.

#define LCD_SPI_MISO_PIN GPIO_Pin_14

Definition at line 116 of file stm3210b_eval_lcd.h.

#define LCD_SPI_MOSI_GPIO_CLK RCC_APB2Periph_GPIOB

Definition at line 121 of file stm3210b_eval_lcd.h.

#define LCD_SPI_MOSI_GPIO_PORT GPIOB

Definition at line 120 of file stm3210b_eval_lcd.h.

#define LCD_SPI_MOSI_PIN GPIO_Pin_15

Definition at line 119 of file stm3210b_eval_lcd.h.

#define LCD_SPI_SCK_GPIO_CLK RCC_APB2Periph_GPIOB

Definition at line 115 of file stm3210b_eval_lcd.h.

#define LCD_SPI_SCK_GPIO_PORT GPIOB

Definition at line 114 of file stm3210b_eval_lcd.h.

#define LCD_SPI_SCK_PIN GPIO_Pin_13

Definition at line 113 of file stm3210b_eval_lcd.h.


STM32F10x Standard Peripherals Firmware Library: STM3210B_EVAL_LCD_Exported_Macros

Defines

STM3210B_EVAL_LCD_Exported_Macros

STM3210B_EVAL_LCD

Defines

#define ASSEMBLE_RGB(R, G, B) ((((R)& 0xF8) << 8) | (((G) & 0xFC) << 3) | (((B) & 0xF8) >> 3))

Define Documentation

#define ASSEMBLE_RGB | ( | R,
 |  | G,
 |  | B
 | ) | ((((R)& 0xF8) << 8) | (((G) & 0xFC) << 3) | (((B) & 0xF8) >> 3))

Definition at line 311 of file stm3210b_eval_lcd.h.


STM32F10x Standard Peripherals Firmware Library: STM3210B_EVAL_LCD_Exported_Functions

Functions

STM3210B_EVAL_LCD_Exported_Functions

STM3210B_EVAL_LCD

Functions

void | LCD_Clear (uint16_t Color)
Clears the hole LCD.
void | LCD_ClearLine (uint8_t Line)
Clears the selected line.
void | LCD_ClosedPolyLine (pPoint Points, uint16_t PointCount)
Displays a closed polyline (between many points).
void | LCD_ClosedPolyLineRelative (pPoint Points, uint16_t PointCount)
Displays a closed relative polyline (between many points).
void | LCD_CtrlLinesConfig (void)
Configures LCD control lines in Output Push-Pull mode.
void | LCD_CtrlLinesWrite (GPIO_TypeDef *GPIOx, uint16_t CtrlPins, BitAction BitVal)
Sets or reset LCD control lines.
void | LCD_DeInit (void)
DeInitializes the LCD.
void | LCD_DisplayChar (uint8_t Line, uint16_t Column, uint8_t Ascii)
Displays one character (16dots width, 24dots height).
void | LCD_DisplayOff (void)
Disables the Display.
void | LCD_DisplayOn (void)
Enables the Display.
void | LCD_DisplayStringLine (uint8_t Line, uint8_t *ptr)
Displays a maximum of 20 char on the LCD.
void | LCD_DrawBMP (uint32_t BmpAddress)
void | LCD_DrawChar (uint8_t Xpos, uint16_t Ypos, const uint16_t *c)
Draws a character on LCD.
void | LCD_DrawCircle (uint8_t Xpos, uint16_t Ypos, uint16_t Radius)
Displays a circle.
void | LCD_DrawFullCircle (uint16_t Xpos, uint16_t Ypos, uint16_t Radius)
Displays a full circle.
void | LCD_DrawFullRect (uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height)
Displays a full rectangle.
void | LCD_DrawLine (uint8_t Xpos, uint16_t Ypos, uint16_t Length, uint8_t Direction)
Displays a line.
void | LCD_DrawMonoPict (const uint32_t *Pict)
Displays a monocolor picture.
void | LCD_DrawRect (uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width)
Displays a rectangle.
void | LCD_DrawUniLine (uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2)
Displays an uni line (between two points).
void | LCD_FillPolyLine (pPoint Points, uint16_t PointCount)
Displays a full polyline (between many points).
void | LCD_GetColors (__IO uint16_t *_TextColor, __IO uint16_t *_BackColor)
Gets the LCD Text and Background colors.
sFONT * | LCD_GetFont (void)
Gets the Text Font.
void | LCD_nCS_StartByte (uint8_t Start_Byte)
Reset LCD control line(/CS) and Send Start-Byte.
void | LCD_PolyLine (pPoint Points, uint16_t PointCount)
Displays an polyline (between many points).
void | LCD_PolyLineRelative (pPoint Points, uint16_t PointCount)
Displays a relative polyline (between many points).
void | LCD_PowerOn (void)
Power on the LCD.
uint16_t | LCD_ReadReg (uint8_t LCD_Reg)
Reads the selected LCD Register.
void | LCD_SetBackColor (__IO uint16_t Color)
Sets the Background color.
void | LCD_SetColors (__IO uint16_t _TextColor, __IO uint16_t _BackColor)
Sets the LCD Text and Background colors.
void | LCD_SetCursor (uint8_t Xpos, uint16_t Ypos)
Sets the cursor position.
void | LCD_SetDisplayWindow (uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width)
Sets a display window.
void | LCD_SetFont (sFONT *fonts)
Sets the Text Font.
void | LCD_SetTextColor (__IO uint16_t Color)
Sets the Text color.
void | LCD_Setup (void)
Setups the LCD.
void | LCD_SPIConfig (void)
Configures the LCD_SPI interface.
void | LCD_WindowModeDisable (void)
Disables LCD Window mode.
void | LCD_WriteRAM (uint16_t RGB_Code)
Writes to the LCD RAM.
void | LCD_WriteRAM_Prepare (void)
Prepare to write to the LCD RAM.
void | LCD_WriteRAMWord (uint16_t RGB_Code)
Writes 1 word to the LCD RAM.
void | LCD_WriteReg (uint8_t LCD_Reg, uint16_t LCD_RegValue)
Writes to the selected LCD register.
void | LCD_WriteRegIndex (uint8_t LCD_Reg)
Writes index to select the LCD register.
void | STM3210B_LCD_Init (void)
Initializes the LCD.

Function Documentation

void LCD_Clear ( uint16_t Color )

Clears the hole LCD.

Parameters:
Color,: the color of the background.
Return values:
None

Definition at line 544 of file stm32100b_eval_lcd.c.

void LCD_ClearLine ( uint8_t Line )

Clears the selected line.

Parameters:
Line,: the Line to be cleared. This parameter can be one of the following values:

  • Linex: where x can be 0..n
Return values:
None

Definition at line 525 of file stm32100b_eval_lcd.c.

void LCD_ClosedPolyLine | ( | pPoint | Points,
 |  | uint16_t | PointCount
 | ) |  |

Displays a closed polyline (between many points).

Parameters:
Points,: pointer to the points array.
PointCount,: Number of points.
Return values:
None

Definition at line 1236 of file stm32100b_eval_lcd.c.

void LCD_ClosedPolyLineRelative | ( | pPoint | Points,
 |  | uint16_t | PointCount
 | ) |  |

Displays a closed relative polyline (between many points).

Parameters:
Points,: pointer to the points array.
PointCount,: Number of points.
Return values:
None

Definition at line 1259 of file stm32100b_eval_lcd.c.

void LCD_CtrlLinesConfig ( void )

Configures LCD control lines in Output Push-Pull mode.

Parameters:
None
Return values:
None Configures LCD control lines in Output Push-Pull mode.
Parameters:
None
Return values:
None

Definition at line 1724 of file stm32100b_eval_lcd.c.

void LCD_CtrlLinesWrite | ( | GPIO_TypeDef * | GPIOx,
 |  | uint16_t | CtrlPins,
 |  | BitAction | BitVal
 | ) |  |

Sets or reset LCD control lines.

Parameters:
GPIOx,: where x can be B or D to select the GPIO peripheral.
CtrlPins,: the Control line. This parameter can be:

  • LCD_NCS_PIN: Chip Select pin
  • LCD_NWR_PIN: Read/Write Selection pin
  • LCD_RS_PIN: Register/RAM Selection pin
BitVal,: specifies the value to be written to the selected bit. This parameter can be:

  • Bit_RESET: to clear the port pin
  • Bit_SET: to set the port pin
Return values:
None
Parameters:
GPIOx,: where x can be B or D to select the GPIO peripheral.
CtrlPins,: the Control line. This parameter can be:

  • LCD_NCS_PIN: Chip Select pin
BitVal,: specifies the value to be written to the selected bit. This parameter can be:

  • Bit_RESET: to clear the port pin
  • Bit_SET: to set the port pin
Return values:
None

Definition at line 1763 of file stm32100b_eval_lcd.c.

void LCD_DeInit ( void )

DeInitializes the LCD.

Parameters:
None
Return values:
None

< LCD Display Off

< LCD_SPI disable

< LCD_SPI DeInit

< Disable SPI clock

< LCD Display Off

< LCD_SPI DeInit

< LCD Display Off

< LCD_SPI disable

< LCD_SPI DeInit

< Disable SPI clock

< LCD Display Off

< LCD_SPI disable

< LCD_SPI DeInit

< Disable SPI clock

< LCD Display Off

< LCD_SPI DeInit

Definition at line 116 of file stm32100b_eval_lcd.c.

void LCD_DisplayChar | ( | uint8_t | Line,
 |  | uint16_t | Column,
 |  | uint8_t | Ascii
 | ) |  |

Displays one character (16dots width, 24dots height).

Parameters:
Line,: the Line where to display the character shape . This parameter can be one of the following values:

  • Linex: where x can be 0..9
Column,: start column address.
Ascii,: character ascii code, must be between 0x20 and 0x7E.
Return values:
None

Definition at line 640 of file stm32100b_eval_lcd.c.

void LCD_DisplayOff ( void )

Disables the Display.

Parameters:
None
Return values:
None

Definition at line 1702 of file stm32100b_eval_lcd.c.

void LCD_DisplayOn ( void )

Enables the Display.

Parameters:
None
Return values:
None

Definition at line 1677 of file stm32100b_eval_lcd.c.

void LCD_DisplayStringLine | ( | uint8_t | Line,
 |  | uint8_t * | ptr
 | ) |  |

Displays a maximum of 20 char on the LCD.

Parameters:
Line,: the Line where to display the character shape . This parameter can be one of the following values:

  • Linex: where x can be 0..9
*ptr,: pointer to string to display on LCD.
Return values:
None

Definition at line 655 of file stm32100b_eval_lcd.c.

void LCD_DrawBMP ( uint32_t BmpAddress )
void LCD_DrawChar | ( | uint8_t | Xpos,
 |  | uint16_t | Ypos,
 |  | const uint16_t * | c
 | ) |  |

Draws a character on LCD.

Parameters:
Xpos,: the Line where to display the character shape.
Ypos,: start column address.
c,: pointer to the character data.
Return values:
None

Definition at line 593 of file stm32100b_eval_lcd.c.

void LCD_DrawCircle | ( | uint8_t | Xpos,
 |  | uint16_t | Ypos,
 |  | uint16_t | Radius
 | ) |  |

Displays a circle.

Parameters:
Xpos,: specifies the X position.
Ypos,: specifies the Y position.
Radius
Return values:
None

Definition at line 817 of file stm32100b_eval_lcd.c.

void LCD_DrawFullCircle | ( | uint16_t | Xpos,
 |  | uint16_t | Ypos,
 |  | uint16_t | Radius
 | ) |  |

Displays a full circle.

Parameters:
Xpos,: specifies the X position.
Ypos,: specifies the Y position.
Radius
Return values:
None

Definition at line 1057 of file stm32100b_eval_lcd.c.

void LCD_DrawFullRect | ( | uint16_t | Xpos,
 |  | uint16_t | Ypos,
 |  | uint16_t | Width,
 |  | uint16_t | Height
 | ) |  |

Displays a full rectangle.

Parameters:
Xpos,: specifies the X position.
Ypos,: specifies the Y position.
Height,: rectangle height.
Width,: rectangle width.
Return values:
None

Definition at line 1026 of file stm32100b_eval_lcd.c.

void LCD_DrawLine | ( | uint8_t | Xpos,
 |  | uint16_t | Ypos,
 |  | uint16_t | Length,
 |  | uint8_t | Direction
 | ) |  |

Displays a line.

Parameters:
Xpos,: specifies the X position.
Ypos,: specifies the Y position.
Length,: line length.
Direction,: line direction. This parameter can be one of the following values: Vertical or Horizontal.
Return values:
None

Definition at line 753 of file stm32100b_eval_lcd.c.

void LCD_DrawMonoPict ( const uint32_t * Pict )

Displays a monocolor picture.

Parameters:
Pict,: pointer to the picture array.
Return values:
None

Definition at line 926 of file stm32100b_eval_lcd.c.

void LCD_DrawRect | ( | uint8_t | Xpos,
 |  | uint16_t | Ypos,
 |  | uint8_t | Height,
 |  | uint16_t | Width
 | ) |  |

Displays a rectangle.

Parameters:
Xpos,: specifies the X position.
Ypos,: specifies the Y position.
Height,: display rectangle height.
Width,: display rectangle width.
Return values:
None

Definition at line 800 of file stm32100b_eval_lcd.c.

void LCD_DrawUniLine | ( | uint16_t | x1,
 |  | uint16_t | y1,
 |  | uint16_t | x2,
 |  | uint16_t | y2
 | ) |  |

Displays an uni line (between two points).

Parameters:
x1,: specifies the point 1 x position.
y1,: specifies the point 1 y position.
x2,: specifies the point 2 x position.
y2,: specifies the point 2 y position.
Return values:
None

Definition at line 1107 of file stm32100b_eval_lcd.c.

void LCD_FillPolyLine | ( | pPoint | Points,
 |  | uint16_t | PointCount
 | ) |  |

Displays a full polyline (between many points).

Parameters:
Points,: pointer to the points array.
PointCount,: Number of points.
Return values:
None

Definition at line 1271 of file stm32100b_eval_lcd.c.

void LCD_GetColors | ( | __IO uint16_t * | _TextColor,
 |  | __IO uint16_t * | _BackColor
 | ) |  |

Gets the LCD Text and Background colors.

Parameters:
_TextColor,: pointer to the variable that will contain the Text Color.
_BackColor,: pointer to the variable that will contain the Background Color.
Return values:
None

Definition at line 472 of file stm32100b_eval_lcd.c.

sFONT* LCD_GetFont ( void )

Gets the Text Font.

Parameters:
None.
Return values:
the used font.

Definition at line 513 of file stm32100b_eval_lcd.c.

void LCD_nCS_StartByte ( uint8_t Start_Byte )

Reset LCD control line(/CS) and Send Start-Byte.

Parameters:
Start_Byte,: the Start-Byte to be sent
Return values:
None

Definition at line 1377 of file stm32100b_eval_lcd.c.

void LCD_PolyLine | ( | pPoint | Points,
 |  | uint16_t | PointCount
 | ) |  |

Displays an polyline (between many points).

Parameters:
Points,: pointer to the points array.
PointCount,: Number of points.
Return values:
None

Definition at line 1180 of file stm32100b_eval_lcd.c.

void LCD_PolyLineRelative | ( | pPoint | Points,
 |  | uint16_t | PointCount
 | ) |  |

Displays a relative polyline (between many points).

Parameters:
Points,: pointer to the points array.
PointCount,: Number of points.
Return values:
None

Definition at line 1248 of file stm32100b_eval_lcd.c.

void LCD_PowerOn ( void )

Power on the LCD.

Parameters:
None
Return values:
None

Definition at line 1629 of file stm32100b_eval_lcd.c.

uint16_t LCD_ReadReg ( uint8_t LCD_Reg )

Reads the selected LCD Register.

Parameters:
LCD_Reg,: address of the selected register.
Return values:
LCD Register Value.
Parameters:
None
Return values:
LCD Register Value.

Definition at line 1452 of file stm32100b_eval_lcd.c.

void LCD_SetBackColor ( __IO uint16_t Color )

Sets the Background color.

Parameters:
Color,: specifies the Background color code RGB(5-6-5).
Return values:
None

Definition at line 493 of file stm32100b_eval_lcd.c.

void LCD_SetColors | ( | __IO uint16_t | _TextColor,
 |  | __IO uint16_t | _BackColor
 | ) |  |

Sets the LCD Text and Background colors.

Parameters:
_TextColor,: specifies the Text Color.
_BackColor,: specifies the Background Color.
Return values:
None

Definition at line 458 of file stm32100b_eval_lcd.c.

void LCD_SetCursor | ( | uint8_t | Xpos,
 |  | uint16_t | Ypos
 | ) |  |

Sets the cursor position.

Parameters:
Xpos,: specifies the X position.
Ypos,: specifies the Y position.
Return values:
None

Definition at line 570 of file stm32100b_eval_lcd.c.

void LCD_SetDisplayWindow | ( | uint8_t | Xpos,
 |  | uint16_t | Ypos,
 |  | uint8_t | Height,
 |  | uint16_t | Width
 | ) |  |

Sets a display window.

Parameters:
Xpos,: specifies the X buttom left position.
Ypos,: specifies the Y buttom left position.
Height,: display window height.
Width,: display window width.
Return values:
None

Definition at line 680 of file stm32100b_eval_lcd.c.

void LCD_SetFont ( sFONT * fonts )

Sets the Text Font.

Parameters:
fonts,: specifies the font to be used.
Return values:
None

Definition at line 503 of file stm32100b_eval_lcd.c.

void LCD_SetTextColor ( __IO uint16_t Color )

Sets the Text color.

Parameters:
Color,: specifies the Text color code RGB(5-6-5).
Return values:
None

Definition at line 482 of file stm32100b_eval_lcd.c.

void LCD_Setup ( void )

Setups the LCD.

Parameters:
None
Return values:
None

Definition at line 160 of file stm32100b_eval_lcd.c.

void LCD_SPIConfig ( void )

Configures the LCD_SPI interface.

Parameters:
None
Return values:
None

Definition at line 1775 of file stm32100b_eval_lcd.c.

void LCD_WindowModeDisable ( void )

Disables LCD Window mode.

Parameters:
None
Return values:
None

Definition at line 729 of file stm32100b_eval_lcd.c.

void LCD_WriteRAM ( uint16_t RGB_Code )

Writes to the LCD RAM.

Parameters:
RGB_Code,: the pixel color in RGB mode (5-6-5).
Return values:
None

Definition at line 1594 of file stm32100b_eval_lcd.c.

void LCD_WriteRAM_Prepare ( void )

Prepare to write to the LCD RAM.

Parameters:
None
Return values:
None

Definition at line 1518 of file stm32100b_eval_lcd.c.

void LCD_WriteRAMWord ( uint16_t RGB_Code )

Writes 1 word to the LCD RAM.

Parameters:
RGB_Code,: the pixel color in RGB mode (5-6-5).
Return values:
None

Definition at line 1532 of file stm32100b_eval_lcd.c.

void LCD_WriteReg | ( | uint8_t | LCD_Reg,
 |  | uint16_t | LCD_RegValue
 | ) |  |

Writes to the selected LCD register.

Parameters:
LCD_Reg,: address of the selected register.
LCD_RegValue,: value to write to the selected register.
Return values:
None Writes to the selected LCD register.
Parameters:
LCD_Reg,: address of the selected register.
LCD_RegValue,: value to write to the selected register.
Return values:
None

Definition at line 1576 of file stm32100b_eval_lcd.c.

void LCD_WriteRegIndex ( uint8_t LCD_Reg )

Writes index to select the LCD register.

Parameters:
LCD_Reg,: address of the selected register.
Return values:
None

Definition at line 1394 of file stm32100b_eval_lcd.c.

void STM3210B_LCD_Init ( void )

Initializes the LCD.

Parameters:
None
Return values:
None

Definition at line 430 of file stm3210b_eval_lcd.c.

References LCD_DEFAULT_FONT, LCD_HX8312, LCD_ILI9320, LCD_ReadReg(), LCD_REG_0, LCD_SetFont(), LCD_Setup(), LCD_SPFD5408, and LCDType.

Referenced by main().


STM32F10x Standard Peripherals Firmware Library: STM3210C_EVAL_LOW_LEVEL_Private_TypesDefinitions

STM3210C_EVAL_LOW_LEVEL_Private_TypesDefinitions

STM3210C_EVAL_LOW_LEVEL


STM32F10x Standard Peripherals Firmware Library: STM3210C_EVAL_LOW_LEVEL_Private_Defines

STM3210C_EVAL_LOW_LEVEL_Private_Defines

STM3210C_EVAL_LOW_LEVEL


STM32F10x Standard Peripherals Firmware Library: STM3210C_EVAL_LOW_LEVEL_Private_Macros

STM3210C_EVAL_LOW_LEVEL_Private_Macros

STM3210C_EVAL_LOW_LEVEL


STM32F10x Standard Peripherals Firmware Library: STM3210C_EVAL_LOW_LEVEL_Private_Variables

Variables

STM3210C_EVAL_LOW_LEVEL_Private_Variables

STM3210C_EVAL_LOW_LEVEL

Variables

const uint32_t | BUTTON_CLK [BUTTONn]
const uint16_t | BUTTON_EXTI_LINE [BUTTONn]
const uint16_t | BUTTON_IRQn [BUTTONn]
const uint16_t | BUTTON_PIN [BUTTONn]
const uint16_t | BUTTON_PIN_SOURCE [BUTTONn]
GPIO_TypeDef * | BUTTON_PORT [BUTTONn]
const uint16_t | BUTTON_PORT_SOURCE [BUTTONn]
const uint16_t | COM_RX_PIN [COMn] = {EVAL_COM1_RX_PIN}
GPIO_TypeDef * | COM_RX_PORT [COMn] = {EVAL_COM1_RX_GPIO_PORT}
const uint32_t | COM_RX_PORT_CLK [COMn] = {EVAL_COM1_RX_GPIO_CLK}
const uint16_t | COM_TX_PIN [COMn] = {EVAL_COM1_TX_PIN}
GPIO_TypeDef * | COM_TX_PORT [COMn] = {EVAL_COM1_TX_GPIO_PORT}
const uint32_t | COM_TX_PORT_CLK [COMn] = {EVAL_COM1_TX_GPIO_CLK}
USART_TypeDef * | COM_USART [COMn] = {EVAL_COM1}
const uint32_t | COM_USART_CLK [COMn] = {EVAL_COM1_CLK}
const uint32_t | GPIO_CLK [LEDn]
const uint16_t | GPIO_PIN [LEDn]
GPIO_TypeDef * | GPIO_PORT [LEDn]
DMA_InitTypeDef sEEDMA_InitStructure

Variable Documentation

const uint32_t BUTTON_CLK[BUTTONn]
Initial value:
 {WAKEUP_BUTTON_GPIO_CLK, TAMPER_BUTTON_GPIO_CLK,
                                      KEY_BUTTON_GPIO_CLK}

Definition at line 91 of file stm3210c_eval.c.

const uint16_t BUTTON_EXTI_LINE[BUTTONn]
Initial value:
 {WAKEUP_BUTTON_EXTI_LINE,
                                            TAMPER_BUTTON_EXTI_LINE,
                                            KEY_BUTTON_EXTI_LINE}

Definition at line 94 of file stm3210c_eval.c.

const uint16_t BUTTON_IRQn[BUTTONn]
Initial value:
 {WAKEUP_BUTTON_EXTI_IRQn, TAMPER_BUTTON_EXTI_IRQn,
                                       KEY_BUTTON_EXTI_IRQn}

Definition at line 106 of file stm3210c_eval.c.

const uint16_t BUTTON_PIN[BUTTONn]
Initial value:
 {WAKEUP_BUTTON_PIN, TAMPER_BUTTON_PIN,
                                      KEY_BUTTON_PIN}

Definition at line 88 of file stm3210c_eval.c.

const uint16_t BUTTON_PIN_SOURCE[BUTTONn]
Initial value:
 {WAKEUP_BUTTON_EXTI_PIN_SOURCE,
                                             TAMPER_BUTTON_EXTI_PIN_SOURCE,
                                             KEY_BUTTON_EXTI_PIN_SOURCE}

Definition at line 102 of file stm3210c_eval.c.

GPIO_TypeDef* BUTTON_PORT[BUTTONn]
Initial value:
 {WAKEUP_BUTTON_GPIO_PORT, TAMPER_BUTTON_GPIO_PORT,
                                      KEY_BUTTON_GPIO_PORT}

Definition at line 85 of file stm3210c_eval.c.

const uint16_t BUTTON_PORT_SOURCE[BUTTONn]
Initial value:
 {WAKEUP_BUTTON_EXTI_PORT_SOURCE,
                                              TAMPER_BUTTON_EXTI_PORT_SOURCE,
                                              KEY_BUTTON_EXTI_PORT_SOURCE}

Definition at line 98 of file stm3210c_eval.c.

const uint16_t COM_RX_PIN[COMn] = {EVAL_COM1_RX_PIN}

Definition at line 123 of file stm3210c_eval.c.

GPIO_TypeDef* COM_RX_PORT[COMn] = {EVAL_COM1_RX_GPIO_PORT}

Definition at line 113 of file stm3210c_eval.c.

const uint32_t COM_RX_PORT_CLK[COMn] = {EVAL_COM1_RX_GPIO_CLK}

Definition at line 119 of file stm3210c_eval.c.

const uint16_t COM_TX_PIN[COMn] = {EVAL_COM1_TX_PIN}

Definition at line 121 of file stm3210c_eval.c.

GPIO_TypeDef* COM_TX_PORT[COMn] = {EVAL_COM1_TX_GPIO_PORT}

Definition at line 111 of file stm3210c_eval.c.

const uint32_t COM_TX_PORT_CLK[COMn] = {EVAL_COM1_TX_GPIO_CLK}

Definition at line 117 of file stm3210c_eval.c.

USART_TypeDef* COM_USART[COMn] = {EVAL_COM1}

Definition at line 109 of file stm3210c_eval.c.

const uint32_t COM_USART_CLK[COMn] = {EVAL_COM1_CLK}

Definition at line 115 of file stm3210c_eval.c.

const uint32_t GPIO_CLK[LEDn]
Initial value:
 {LED1_GPIO_CLK, LED2_GPIO_CLK, LED3_GPIO_CLK,
                                 LED4_GPIO_CLK}

Definition at line 82 of file stm3210c_eval.c.

const uint16_t GPIO_PIN[LEDn]
Initial value:
 {LED1_PIN, LED2_PIN, LED3_PIN,
                                 LED4_PIN}

Definition at line 80 of file stm3210c_eval.c.

GPIO_TypeDef* GPIO_PORT[LEDn]
Initial value:
 {LED1_GPIO_PORT, LED2_GPIO_PORT, LED3_GPIO_PORT,
                                 LED4_GPIO_PORT}

Definition at line 78 of file stm3210c_eval.c.

DMA_InitTypeDef sEEDMA_InitStructure

Definition at line 125 of file stm3210c_eval.c.


STM32F10x Standard Peripherals Firmware Library: STM3210C_EVAL_LOW_LEVEL_Private_FunctionPrototypes

STM3210C_EVAL_LOW_LEVEL_Private_FunctionPrototypes

STM3210C_EVAL_LOW_LEVEL


STM32F10x Standard Peripherals Firmware Library: STM3210C_EVAL_LOW_LEVEL_Private_Functions

Functions

STM3210C_EVAL_LOW_LEVEL_Private_Functions

STM3210C_EVAL_LOW_LEVEL

Functions

void | SD_LowLevel_DeInit (void)
DeInitializes the SD/SD communication.
void | SD_LowLevel_Init (void)
Initializes the SD_SPI and CS pins.
void | sEE_LowLevel_DeInit (void)
DeInitializes peripherals used by the I2C EEPROM driver.
void | sEE_LowLevel_DMAConfig (uint32_t pBuffer, uint32_t BufferSize, uint32_t Direction)
Initializes DMA channel used by the I2C EEPROM driver.
void | sEE_LowLevel_Init (void)
Initializes peripherals used by the I2C EEPROM driver.
void | STM_EVAL_COMInit (COM_TypeDef COM, USART_InitTypeDef *USART_InitStruct)
Configures COM port.
void | STM_EVAL_LEDInit (Led_TypeDef Led)
Configures LED GPIO.
void | STM_EVAL_LEDOff (Led_TypeDef Led)
Turns selected LED Off.
void | STM_EVAL_LEDOn (Led_TypeDef Led)
Turns selected LED On.
void | STM_EVAL_LEDToggle (Led_TypeDef Led)
Toggles the selected LED.
uint32_t | STM_EVAL_PBGetState (Button_TypeDef Button)
Returns the selected Button state.
void | STM_EVAL_PBInit (Button_TypeDef Button, ButtonMode_TypeDef Button_Mode)
Configures Button GPIO and EXTI Line.

Function Documentation

void SD_LowLevel_DeInit ( void )

DeInitializes the SD/SD communication.

Parameters:
None
Return values:
None

< SD_SPI disable

< DeInitializes the SD_SPI

< SD_SPI Periph clock disable

< DeRemap SPI3 Pins

< Configure SD_SPI pins: SCK

< Configure SD_SPI pins: MISO

< Configure SD_SPI pins: MOSI

< Configure SD_SPI_CS_PIN pin: SD Card CS pin

< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin

Definition at line 344 of file stm3210c_eval.c.

References DISABLE, GPIO_Init(), GPIO_InitStructure, GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_IN_FLOATING, GPIO_InitTypeDef::GPIO_Pin, GPIO_PinRemapConfig(), GPIO_Remap_SPI3, RCC_APB1PeriphClockCmd(), SD_CS_GPIO_PORT, SD_CS_PIN, SD_DETECT_GPIO_PORT, SD_DETECT_PIN, SD_SPI, SD_SPI_CLK, SD_SPI_MISO_GPIO_PORT, SD_SPI_MISO_PIN, SD_SPI_MOSI_GPIO_PORT, SD_SPI_MOSI_PIN, SD_SPI_SCK_GPIO_PORT, SD_SPI_SCK_PIN, SPI_Cmd(), and SPI_I2S_DeInit().

void SD_LowLevel_Init ( void )

Initializes the SD_SPI and CS pins.

Parameters:
None
Return values:
None

< SD_SPI_CS_GPIO, SD_SPI_MOSI_GPIO, SD_SPI_MISO_GPIO, SD_SPI_DETECT_GPIO and SD_SPI_SCK_GPIO Periph clock enable

< SD_SPI Periph clock enable

< AFIO Periph clock enable

< Remap SPI3 Pins

< Configure SD_SPI pins: SCK

< Configure SD_SPI pins: MOSI

< Configure SD_SPI pins: MISO

< Configure SD_SPI_CS_PIN pin: SD Card CS pin

< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin

< SD_SPI Config

< SD_SPI enable

Definition at line 383 of file stm3210c_eval.c.

References ENABLE, GPIO_Init(), GPIO_InitStructure, GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_AF_PP, GPIO_Mode_IN_FLOATING, GPIO_Mode_IPU, GPIO_Mode_Out_PP, GPIO_InitTypeDef::GPIO_Pin, GPIO_PinRemapConfig(), GPIO_Remap_SPI3, GPIO_InitTypeDef::GPIO_Speed, GPIO_Speed_50MHz, RCC_APB1PeriphClockCmd(), RCC_APB2Periph_AFIO, RCC_APB2PeriphClockCmd(), SD_CS_GPIO_CLK, SD_CS_GPIO_PORT, SD_CS_PIN, SD_DETECT_GPIO_CLK, SD_DETECT_GPIO_PORT, SD_DETECT_PIN, SD_SPI, SD_SPI_CLK, SD_SPI_MISO_GPIO_CLK, SD_SPI_MISO_GPIO_PORT, SD_SPI_MISO_PIN, SD_SPI_MOSI_GPIO_CLK, SD_SPI_MOSI_GPIO_PORT, SD_SPI_MOSI_PIN, SD_SPI_SCK_GPIO_CLK, SD_SPI_SCK_GPIO_PORT, SD_SPI_SCK_PIN, SPI_InitTypeDef::SPI_BaudRatePrescaler, SPI_BaudRatePrescaler_2, SPI_Cmd(), SPI_InitTypeDef::SPI_CPHA, SPI_CPHA_2Edge, SPI_InitTypeDef::SPI_CPOL, SPI_CPOL_High, SPI_InitTypeDef::SPI_CRCPolynomial, SPI_InitTypeDef::SPI_DataSize, SPI_DataSize_8b, SPI_InitTypeDef::SPI_Direction, SPI_Direction_2Lines_FullDuplex, SPI_InitTypeDef::SPI_FirstBit, SPI_FirstBit_MSB, SPI_Init(), SPI_InitStructure, SPI_InitTypeDef::SPI_Mode, SPI_Mode_Master, SPI_InitTypeDef::SPI_NSS, and SPI_NSS_Soft.

void sEE_LowLevel_DeInit ( void )

DeInitializes peripherals used by the I2C EEPROM driver.

Parameters:
None
Return values:
None

< sEE_I2C Periph clock disable

< GPIO configuration

< Configure sEE_I2C pins: SCL

< Configure sEE_I2C pins: SDA

Definition at line 445 of file stm3210c_eval.c.

References DISABLE, DMA_Cmd(), DMA_DeInit(), GPIO_Init(), GPIO_InitStructure, GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_IN_FLOATING, GPIO_InitTypeDef::GPIO_Pin, I2C_Cmd(), I2C_DeInit(), NVIC_Init(), NVIC_InitStructure, NVIC_InitTypeDef::NVIC_IRQChannel, NVIC_InitTypeDef::NVIC_IRQChannelCmd, NVIC_InitTypeDef::NVIC_IRQChannelPreemptionPriority, NVIC_InitTypeDef::NVIC_IRQChannelSubPriority, RCC_APB1PeriphClockCmd(), sEE_I2C, sEE_I2C_CLK, sEE_I2C_DMA_CHANNEL_RX, sEE_I2C_DMA_CHANNEL_TX, sEE_I2C_DMA_PREPRIO, sEE_I2C_DMA_RX_IRQn, sEE_I2C_DMA_SUBPRIO, sEE_I2C_DMA_TX_IRQn, sEE_I2C_SCL_GPIO_PORT, sEE_I2C_SCL_PIN, sEE_I2C_SDA_GPIO_PORT, and sEE_I2C_SDA_PIN.

void sEE_LowLevel_DMAConfig | ( | uint32_t | pBuffer,
 |  | uint32_t | BufferSize,
 |  | uint32_t | Direction
 | ) |  |

Initializes DMA channel used by the I2C EEPROM driver.

Parameters:
None
Return values:
None

Definition at line 563 of file stm3210c_eval.c.

References DMA_InitTypeDef::DMA_BufferSize, DMA_InitTypeDef::DMA_DIR, DMA_DIR_PeripheralDST, DMA_DIR_PeripheralSRC, DMA_Init(), DMA_InitTypeDef::DMA_MemoryBaseAddr, sEE_DIRECTION_TX, sEE_I2C_DMA_CHANNEL_RX, and sEE_I2C_DMA_CHANNEL_TX.

void sEE_LowLevel_Init ( void )

Initializes peripherals used by the I2C EEPROM driver.

Parameters:
None
Return values:
None

< sEE_I2C_SCL_GPIO_CLK and sEE_I2C_SDA_GPIO_CLK Periph clock enable

< sEE_I2C Periph clock enable

< GPIO configuration

< Configure sEE_I2C pins: SCL

< Configure sEE_I2C pins: SDA

< I2C DMA TX and RX channels configuration

Definition at line 494 of file stm3210c_eval.c.

References DMA_InitTypeDef::DMA_BufferSize, DMA_DeInit(), DMA_InitTypeDef::DMA_DIR, DMA_DIR_PeripheralDST, DMA_Init(), DMA_IT_TC, DMA_ITConfig(), DMA_InitTypeDef::DMA_M2M, DMA_M2M_Disable, DMA_InitTypeDef::DMA_MemoryBaseAddr, DMA_InitTypeDef::DMA_MemoryDataSize, DMA_MemoryDataSize_Byte, DMA_InitTypeDef::DMA_MemoryInc, DMA_MemoryInc_Enable, DMA_InitTypeDef::DMA_Mode, DMA_Mode_Normal, DMA_InitTypeDef::DMA_PeripheralBaseAddr, DMA_InitTypeDef::DMA_PeripheralDataSize, DMA_InitTypeDef::DMA_PeripheralInc, DMA_PeripheralInc_Disable, DMA_InitTypeDef::DMA_Priority, DMA_Priority_VeryHigh, ENABLE, GPIO_Init(), GPIO_InitStructure, GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_AF_OD, GPIO_InitTypeDef::GPIO_Pin, GPIO_InitTypeDef::GPIO_Speed, GPIO_Speed_50MHz, NVIC_Init(), NVIC_InitStructure, NVIC_InitTypeDef::NVIC_IRQChannel, NVIC_InitTypeDef::NVIC_IRQChannelCmd, NVIC_InitTypeDef::NVIC_IRQChannelPreemptionPriority, NVIC_InitTypeDef::NVIC_IRQChannelSubPriority, RCC_AHBPeriphClockCmd(), RCC_APB1PeriphClockCmd(), RCC_APB2PeriphClockCmd(), sEE_I2C_CLK, sEE_I2C_DMA_CHANNEL_RX, sEE_I2C_DMA_CHANNEL_TX, sEE_I2C_DMA_CLK, sEE_I2C_DMA_PREPRIO, sEE_I2C_DMA_RX_IRQn, sEE_I2C_DMA_SUBPRIO, sEE_I2C_DMA_TX_IRQn, sEE_I2C_DR_Address, sEE_I2C_SCL_GPIO_CLK, sEE_I2C_SCL_GPIO_PORT, sEE_I2C_SCL_PIN, sEE_I2C_SDA_GPIO_CLK, sEE_I2C_SDA_GPIO_PORT, and sEE_I2C_SDA_PIN.

void STM_EVAL_COMInit | ( | COM_TypeDef | COM,
 |  | USART_InitTypeDef * | USART_InitStruct
 | ) |  |

Configures COM port.

Parameters:
COM,: Specifies the COM port to be configured. This parameter can be one of following parameters:

  • COM1
  • COM2
USART_InitStruct,: pointer to a USART_InitTypeDef structure that contains the configuration information for the specified USART peripheral.
Return values:
None

Definition at line 307 of file stm3210c_eval.c.

References COM1, COM_RX_PIN, COM_RX_PORT_CLK, COM_TX_PIN, COM_TX_PORT_CLK, COM_USART_CLK, ENABLE, GPIO_Init(), GPIO_InitStructure, GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_AF_PP, GPIO_Mode_IN_FLOATING, GPIO_InitTypeDef::GPIO_Pin, GPIO_PinRemapConfig(), GPIO_Remap_USART2, GPIO_InitTypeDef::GPIO_Speed, GPIO_Speed_50MHz, RCC_APB1PeriphClockCmd(), RCC_APB2Periph_AFIO, RCC_APB2PeriphClockCmd(), USART_Cmd(), and USART_Init().

void STM_EVAL_LEDInit ( Led_TypeDef Led )

Configures LED GPIO.

Parameters:
Led,: Specifies the Led to be configured. This parameter can be one of following parameters:

  • LED1
  • LED2
  • LED3
  • LED4
Return values:
None

Definition at line 153 of file stm3210c_eval.c.

References ENABLE, GPIO_CLK, GPIO_Init(), GPIO_InitStructure, GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_Out_PP, GPIO_PIN, GPIO_InitTypeDef::GPIO_Pin, GPIO_InitTypeDef::GPIO_Speed, GPIO_Speed_50MHz, and RCC_APB2PeriphClockCmd().

void STM_EVAL_LEDOff ( Led_TypeDef Led )

Turns selected LED Off.

Parameters:
Led,: Specifies the Led to be set off. This parameter can be one of following parameters:

  • LED1
  • LED2
  • LED3
  • LED4
Return values:
None

Definition at line 193 of file stm3210c_eval.c.

References GPIO_TypeDef::BRR, and GPIO_PIN.

void STM_EVAL_LEDOn ( Led_TypeDef Led )

Turns selected LED On.

Parameters:
Led,: Specifies the Led to be set on. This parameter can be one of following parameters:

  • LED1
  • LED2
  • LED3
  • LED4
Return values:
None

Definition at line 178 of file stm3210c_eval.c.

References GPIO_TypeDef::BSRR, and GPIO_PIN.

void STM_EVAL_LEDToggle ( Led_TypeDef Led )

Toggles the selected LED.

Parameters:
Led,: Specifies the Led to be toggled. This parameter can be one of following parameters:

  • LED1
  • LED2
  • LED3
  • LED4
Return values:
None

Definition at line 208 of file stm3210c_eval.c.

References GPIO_PIN, and GPIO_TypeDef::ODR.

uint32_t STM_EVAL_PBGetState ( Button_TypeDef Button )

Returns the selected Button state.

Parameters:
Button,: Specifies the Button to be checked. This parameter can be one of following parameters:

  • BUTTON_WAKEUP: Wakeup Push Button
  • BUTTON_TAMPER: Tamper Push Button
  • BUTTON_KEY: Key Push Button
  • BUTTON_RIGHT: Joystick Right Push Button
  • BUTTON_LEFT: Joystick Left Push Button
  • BUTTON_UP: Joystick Up Push Button
  • BUTTON_DOWN: Joystick Down Push Button
  • BUTTON_SEL: Joystick Sel Push Button
Return values:
The Button GPIO pin value.

Definition at line 291 of file stm3210c_eval.c.

References BUTTON_PIN, and GPIO_ReadInputDataBit().

void STM_EVAL_PBInit | ( | Button_TypeDef | Button,
 |  | ButtonMode_TypeDef | Button_Mode
 | ) |  |

Configures Button GPIO and EXTI Line.

Parameters:
Button,: Specifies the Button to be configured. This parameter can be one of following parameters:

  • BUTTON_WAKEUP: Wakeup Push Button
  • BUTTON_TAMPER: Tamper Push Button
  • BUTTON_KEY: Key Push Button
  • BUTTON_RIGHT: Joystick Right Push Button
  • BUTTON_LEFT: Joystick Left Push Button
  • BUTTON_UP: Joystick Up Push Button
  • BUTTON_DOWN: Joystick Down Push Button
  • BUTTON_SEL: Joystick Sel Push Button
Button_Mode,: Specifies Button mode. This parameter can be one of following parameters:

  • BUTTON_MODE_GPIO: Button will be used as simple IO
  • BUTTON_MODE_EXTI: Button will be connected to EXTI line with interrupt generation capability
Return values:
None

Definition at line 232 of file stm3210c_eval.c.

References BUTTON_CLK, BUTTON_EXTI_LINE, BUTTON_IRQn, BUTTON_MODE_EXTI, BUTTON_PIN, BUTTON_PIN_SOURCE, BUTTON_PORT_SOURCE, BUTTON_WAKEUP, ENABLE, EXTI_Init(), EXTI_InitStructure, EXTI_InitTypeDef::EXTI_Line, EXTI_InitTypeDef::EXTI_LineCmd, EXTI_InitTypeDef::EXTI_Mode, EXTI_Mode_Interrupt, EXTI_InitTypeDef::EXTI_Trigger, EXTI_Trigger_Falling, EXTI_Trigger_Rising, GPIO_EXTILineConfig(), GPIO_Init(), GPIO_InitStructure, GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_IN_FLOATING, GPIO_InitTypeDef::GPIO_Pin, NVIC_Init(), NVIC_InitStructure, NVIC_InitTypeDef::NVIC_IRQChannel, NVIC_InitTypeDef::NVIC_IRQChannelCmd, NVIC_InitTypeDef::NVIC_IRQChannelPreemptionPriority, NVIC_InitTypeDef::NVIC_IRQChannelSubPriority, RCC_APB2Periph_AFIO, and RCC_APB2PeriphClockCmd().


STM32F10x Standard Peripherals Firmware Library: STM3210C_EVAL_LOW_LEVEL_Exported_Types

STM3210C_EVAL_LOW_LEVEL_Exported_Types

STM3210C_EVAL_LOW_LEVEL


STM32F10x Standard Peripherals Firmware Library: STM3210C_EVAL_LOW_LEVEL_LED

Defines

STM3210C_EVAL_LOW_LEVEL_LED

STM3210C_EVAL_LOW_LEVEL_Exported_Constants

Defines

#define | LED1_GPIO_CLK RCC_APB2Periph_GPIOD
#define | LED1_GPIO_PORT GPIOD
#define | LED1_PIN GPIO_Pin_7
#define | LED2_GPIO_CLK RCC_APB2Periph_GPIOD
#define | LED2_GPIO_PORT GPIOD
#define | LED2_PIN GPIO_Pin_13
#define | LED3_GPIO_CLK RCC_APB2Periph_GPIOD
#define | LED3_GPIO_PORT GPIOD
#define | LED3_PIN GPIO_Pin_3
#define | LED4_GPIO_CLK RCC_APB2Periph_GPIOD
#define | LED4_GPIO_PORT GPIOD
#define | LED4_PIN GPIO_Pin_4
#define | LEDn 4

Define Documentation

#define LED1_GPIO_CLK RCC_APB2Periph_GPIOD

Definition at line 67 of file stm3210c_eval.h.

#define LED1_GPIO_PORT GPIOD

Definition at line 66 of file stm3210c_eval.h.

#define LED1_PIN GPIO_Pin_7

Definition at line 65 of file stm3210c_eval.h.

#define LED2_GPIO_CLK RCC_APB2Periph_GPIOD

Definition at line 71 of file stm3210c_eval.h.

#define LED2_GPIO_PORT GPIOD

Definition at line 70 of file stm3210c_eval.h.

#define LED2_PIN GPIO_Pin_13

Definition at line 69 of file stm3210c_eval.h.

#define LED3_GPIO_CLK RCC_APB2Periph_GPIOD

Definition at line 75 of file stm3210c_eval.h.

#define LED3_GPIO_PORT GPIOD

Definition at line 74 of file stm3210c_eval.h.

#define LED3_PIN GPIO_Pin_3

Definition at line 73 of file stm3210c_eval.h.

#define LED4_GPIO_CLK RCC_APB2Periph_GPIOD

Definition at line 79 of file stm3210c_eval.h.

#define LED4_GPIO_PORT GPIOD

Definition at line 78 of file stm3210c_eval.h.

#define LED4_PIN GPIO_Pin_4

Definition at line 77 of file stm3210c_eval.h.

#define LEDn 4

Definition at line 63 of file stm3210c_eval.h.


STM32F10x Standard Peripherals Firmware Library: STM3210C_EVAL_LOW_LEVEL_BUTTON

Defines

STM3210C_EVAL_LOW_LEVEL_BUTTON

STM3210C_EVAL_LOW_LEVEL_Exported_Constants

Defines

#define | BUTTONn 3
#define | KEY_BUTTON_EXTI_IRQn EXTI9_5_IRQn
#define | KEY_BUTTON_EXTI_LINE EXTI_Line9
#define | KEY_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource9
#define | KEY_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOB
#define | KEY_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOB
#define | KEY_BUTTON_GPIO_PORT GPIOB
#define | KEY_BUTTON_PIN GPIO_Pin_9
Key push-button.
#define | TAMPER_BUTTON_EXTI_IRQn EXTI15_10_IRQn
#define | TAMPER_BUTTON_EXTI_LINE EXTI_Line13
#define | TAMPER_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource13
#define | TAMPER_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOC
#define | TAMPER_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOC
#define | TAMPER_BUTTON_GPIO_PORT GPIOC
#define | TAMPER_BUTTON_PIN GPIO_Pin_13
Tamper push-button.
#define | WAKEUP_BUTTON_EXTI_IRQn EXTI0_IRQn
#define | WAKEUP_BUTTON_EXTI_LINE EXTI_Line0
#define | WAKEUP_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource0
#define | WAKEUP_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOA
#define | WAKEUP_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOA
#define | WAKEUP_BUTTON_GPIO_PORT GPIOA
#define | WAKEUP_BUTTON_PIN GPIO_Pin_0
Wakeup push-button.

Define Documentation

#define BUTTONn 3

Joystick pins are connected to an IO Expander (accessible through I2C1 interface)

Definition at line 89 of file stm3210c_eval.h.

#define KEY_BUTTON_EXTI_IRQn EXTI9_5_IRQn

Definition at line 124 of file stm3210c_eval.h.

#define KEY_BUTTON_EXTI_LINE EXTI_Line9

Definition at line 121 of file stm3210c_eval.h.

#define KEY_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource9

Definition at line 123 of file stm3210c_eval.h.

#define KEY_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOB

Definition at line 122 of file stm3210c_eval.h.

#define KEY_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOB

Definition at line 120 of file stm3210c_eval.h.

#define KEY_BUTTON_GPIO_PORT GPIOB

Definition at line 119 of file stm3210c_eval.h.

#define KEY_BUTTON_PIN GPIO_Pin_9

Key push-button.

Definition at line 118 of file stm3210c_eval.h.

#define TAMPER_BUTTON_EXTI_IRQn EXTI15_10_IRQn

Definition at line 113 of file stm3210c_eval.h.

#define TAMPER_BUTTON_EXTI_LINE EXTI_Line13

Definition at line 110 of file stm3210c_eval.h.

#define TAMPER_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource13

Definition at line 112 of file stm3210c_eval.h.

#define TAMPER_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOC

Definition at line 111 of file stm3210c_eval.h.

#define TAMPER_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOC

Definition at line 109 of file stm3210c_eval.h.

#define TAMPER_BUTTON_GPIO_PORT GPIOC

Definition at line 108 of file stm3210c_eval.h.

#define TAMPER_BUTTON_PIN GPIO_Pin_13

Tamper push-button.

Definition at line 107 of file stm3210c_eval.h.

#define WAKEUP_BUTTON_EXTI_IRQn EXTI0_IRQn

Definition at line 102 of file stm3210c_eval.h.

#define WAKEUP_BUTTON_EXTI_LINE EXTI_Line0

Definition at line 99 of file stm3210c_eval.h.

#define WAKEUP_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource0

Definition at line 101 of file stm3210c_eval.h.

#define WAKEUP_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOA

Definition at line 100 of file stm3210c_eval.h.

#define WAKEUP_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOA

Definition at line 98 of file stm3210c_eval.h.

#define WAKEUP_BUTTON_GPIO_PORT GPIOA

Definition at line 97 of file stm3210c_eval.h.

#define WAKEUP_BUTTON_PIN GPIO_Pin_0

Wakeup push-button.

Definition at line 96 of file stm3210c_eval.h.


STM32F10x Standard Peripherals Firmware Library: STM3210C_EVAL_LOW_LEVEL_COM

Defines

STM3210C_EVAL_LOW_LEVEL_COM

STM3210C_EVAL_LOW_LEVEL_Exported_Constants

Defines

#define | COMn 1
#define | EVAL_COM1 USART2
Definition for COM port1, connected to USART2 (USART2 pins remapped on GPIOD)
#define | EVAL_COM1_CLK RCC_APB1Periph_USART2
#define | EVAL_COM1_IRQn USART2_IRQn
#define | EVAL_COM1_RX_GPIO_CLK RCC_APB2Periph_GPIOD
#define | EVAL_COM1_RX_GPIO_PORT GPIOD
#define | EVAL_COM1_RX_PIN GPIO_Pin_6
#define | EVAL_COM1_TX_GPIO_CLK RCC_APB2Periph_GPIOD
#define | EVAL_COM1_TX_GPIO_PORT GPIOD
#define | EVAL_COM1_TX_PIN GPIO_Pin_5

Define Documentation

#define COMn 1

Definition at line 132 of file stm3210c_eval.h.

#define EVAL_COM1 USART2

Definition for COM port1, connected to USART2 (USART2 pins remapped on GPIOD)

Definition at line 137 of file stm3210c_eval.h.

#define EVAL_COM1_CLK RCC_APB1Periph_USART2

Definition at line 138 of file stm3210c_eval.h.

#define EVAL_COM1_IRQn USART2_IRQn

Definition at line 145 of file stm3210c_eval.h.

#define EVAL_COM1_RX_GPIO_CLK RCC_APB2Periph_GPIOD

Definition at line 144 of file stm3210c_eval.h.

#define EVAL_COM1_RX_GPIO_PORT GPIOD

Definition at line 143 of file stm3210c_eval.h.

#define EVAL_COM1_RX_PIN GPIO_Pin_6

Definition at line 142 of file stm3210c_eval.h.

#define EVAL_COM1_TX_GPIO_CLK RCC_APB2Periph_GPIOD

Definition at line 141 of file stm3210c_eval.h.

#define EVAL_COM1_TX_GPIO_PORT GPIOD

Definition at line 140 of file stm3210c_eval.h.

#define EVAL_COM1_TX_PIN GPIO_Pin_5

Definition at line 139 of file stm3210c_eval.h.


STM32F10x Standard Peripherals Firmware Library: STM3210B_EVAL_SD_SPI

Defines

STM3210B_EVAL_SD_SPI

STM3210C_EVAL_LOW_LEVEL_Exported_Constants

Defines

#define | SD_CS_GPIO_CLK RCC_APB2Periph_GPIOA
#define | SD_CS_GPIO_PORT GPIOA
#define | SD_CS_PIN GPIO_Pin_4
#define | SD_DETECT_GPIO_CLK RCC_APB2Periph_GPIOE
#define | SD_DETECT_GPIO_PORT GPIOE
#define | SD_DETECT_PIN GPIO_Pin_0
#define | SD_SPI SPI3
SD SPI Interface pins.
#define | SD_SPI_CLK RCC_APB1Periph_SPI3
#define | SD_SPI_MISO_GPIO_CLK RCC_APB2Periph_GPIOC
#define | SD_SPI_MISO_GPIO_PORT GPIOC
#define | SD_SPI_MISO_PIN GPIO_Pin_11
#define | SD_SPI_MOSI_GPIO_CLK RCC_APB2Periph_GPIOC
#define | SD_SPI_MOSI_GPIO_PORT GPIOC
#define | SD_SPI_MOSI_PIN GPIO_Pin_12
#define | SD_SPI_SCK_GPIO_CLK RCC_APB2Periph_GPIOC
#define | SD_SPI_SCK_GPIO_PORT GPIOC
#define | SD_SPI_SCK_PIN GPIO_Pin_10

Define Documentation

#define SD_CS_GPIO_CLK RCC_APB2Periph_GPIOA

Definition at line 170 of file stm3210c_eval.h.

#define SD_CS_GPIO_PORT GPIOA

Definition at line 169 of file stm3210c_eval.h.

#define SD_CS_PIN GPIO_Pin_4

Definition at line 168 of file stm3210c_eval.h.

#define SD_DETECT_GPIO_CLK RCC_APB2Periph_GPIOE

Definition at line 173 of file stm3210c_eval.h.

#define SD_DETECT_GPIO_PORT GPIOE

Definition at line 172 of file stm3210c_eval.h.

#define SD_DETECT_PIN GPIO_Pin_0

Definition at line 171 of file stm3210c_eval.h.

#define SD_SPI SPI3

SD SPI Interface pins.

Definition at line 157 of file stm3210c_eval.h.

#define SD_SPI_CLK RCC_APB1Periph_SPI3

Definition at line 158 of file stm3210c_eval.h.

#define SD_SPI_MISO_GPIO_CLK RCC_APB2Periph_GPIOC

Definition at line 164 of file stm3210c_eval.h.

#define SD_SPI_MISO_GPIO_PORT GPIOC

Definition at line 163 of file stm3210c_eval.h.

#define SD_SPI_MISO_PIN GPIO_Pin_11

Definition at line 162 of file stm3210c_eval.h.

#define SD_SPI_MOSI_GPIO_CLK RCC_APB2Periph_GPIOC

Definition at line 167 of file stm3210c_eval.h.

#define SD_SPI_MOSI_GPIO_PORT GPIOC

Definition at line 166 of file stm3210c_eval.h.

#define SD_SPI_MOSI_PIN GPIO_Pin_12

Definition at line 165 of file stm3210c_eval.h.

#define SD_SPI_SCK_GPIO_CLK RCC_APB2Periph_GPIOC

Definition at line 161 of file stm3210c_eval.h.

#define SD_SPI_SCK_GPIO_PORT GPIOC

Definition at line 160 of file stm3210c_eval.h.

#define SD_SPI_SCK_PIN GPIO_Pin_10

Definition at line 159 of file stm3210c_eval.h.


STM32F10x Standard Peripherals Firmware Library: STM3210C_EVAL_LOW_LEVEL_Exported_Macros

STM3210C_EVAL_LOW_LEVEL_Exported_Macros

STM3210C_EVAL_LOW_LEVEL


STM32F10x Standard Peripherals Firmware Library: STM3210C_EVAL_LOW_LEVEL_Exported_Functions

Functions

STM3210C_EVAL_LOW_LEVEL_Exported_Functions

STM3210C_EVAL_LOW_LEVEL

Functions

void | SD_LowLevel_DeInit (void)
DeInitializes the SD/SD communication.
void | SD_LowLevel_Init (void)
Initializes the SD_SPI and CS pins.
void | sEE_LowLevel_DeInit (void)
DeInitializes peripherals used by the I2C EEPROM driver.
void | sEE_LowLevel_DMAConfig (uint32_t pBuffer, uint32_t BufferSize, uint32_t Direction)
Initializes DMA channel used by the I2C EEPROM driver.
void | sEE_LowLevel_Init (void)
Initializes peripherals used by the I2C EEPROM driver.
void | STM_EVAL_COMInit (COM_TypeDef COM, USART_InitTypeDef *USART_InitStruct)
Configures COM port.
void | STM_EVAL_LEDInit (Led_TypeDef Led)
Configures LED GPIO.
void | STM_EVAL_LEDOff (Led_TypeDef Led)
Turns selected LED Off.
void | STM_EVAL_LEDOn (Led_TypeDef Led)
Turns selected LED On.
void | STM_EVAL_LEDToggle (Led_TypeDef Led)
Toggles the selected LED.
uint32_t | STM_EVAL_PBGetState (Button_TypeDef Button)
Returns the selected Button state.
void | STM_EVAL_PBInit (Button_TypeDef Button, ButtonMode_TypeDef Button_Mode)
Configures Button GPIO and EXTI Line.

Function Documentation

void SD_LowLevel_DeInit ( void )

DeInitializes the SD/SD communication.

Parameters:
None
Return values:
None DeInitializes the SD/SD communication.
Parameters:
None
Return values:
None

< SD_SPI disable

< DeInitializes the SD_SPI

< SD_SPI Periph clock disable

< Configure SD_SPI pins: SCK

< Configure SD_SPI pins: MISO

< Configure SD_SPI pins: MOSI

< Configure SD_SPI_CS_PIN pin: SD Card CS pin

< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin

< SD_SPI disable

< DeInitializes the SD_SPI

< SD_SPI Periph clock disable

< Configure SD_SPI pins: SCK

< Configure SD_SPI pins: MISO

< Configure SD_SPI pins: MOSI

< Configure SD_SPI_CS_PIN pin: SD Card CS pin

< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin

< SD_SPI disable

< DeInitializes the SD_SPI

< SD_SPI Periph clock disable

< Configure SD_SPI pins: SCK

< Configure SD_SPI pins: MISO

< Configure SD_SPI pins: MOSI

< Configure SD_SPI_CS_PIN pin: SD Card CS pin

< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin

< SD_SPI disable

< DeInitializes the SD_SPI

< SD_SPI Periph clock disable

< DeRemap SPI3 Pins

< Configure SD_SPI pins: SCK

< Configure SD_SPI pins: MISO

< Configure SD_SPI pins: MOSI

< Configure SD_SPI_CS_PIN pin: SD Card CS pin

< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin

< Disable SDIO Clock

< Set Power State to OFF

< DeInitializes the SDIO peripheral

< Disable the SDIO AHB Clock

< Configure PC.08, PC.09, PC.10, PC.11, PC.12 pin: D0, D1, D2, D3, CLK pin

< Configure PD.02 CMD line

< SD_SPI disable

< DeInitializes the SD_SPI

< SD_SPI Periph clock disable

< Configure SD_SPI pins: SCK

< Configure SD_SPI pins: MISO

< Configure SD_SPI pins: MOSI

< Configure SD_SPI_CS_PIN pin: SD Card CS pin

< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin

Definition at line 373 of file stm32100b_eval.c.

void SD_LowLevel_Init ( void )

Initializes the SD_SPI and CS pins.

Parameters:
None
Return values:
None Initializes the SD_SPI and CS pins.
Parameters:
None
Return values:
None

< SD_SPI_CS_GPIO, SD_SPI_MOSI_GPIO, SD_SPI_MISO_GPIO, SD_SPI_DETECT_GPIO and SD_SPI_SCK_GPIO Periph clock enable

< SD_SPI Periph clock enable

< Configure SD_SPI pins: SCK

< Configure SD_SPI pins: MOSI

< Configure SD_SPI pins: MISO

< Configure SD_SPI_CS_PIN pin: SD Card CS pin

< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin

< SD_SPI Config

< SD_SPI enable

< SD_SPI_CS_GPIO, SD_SPI_MOSI_GPIO, SD_SPI_MISO_GPIO, SD_SPI_DETECT_GPIO and SD_SPI_SCK_GPIO Periph clock enable

< SD_SPI Periph clock enable

< Configure SD_SPI pins: SCK

< Configure SD_SPI pins: MOSI

< Configure SD_SPI pins: MISO

< Configure SD_SPI_CS_PIN pin: SD Card CS pin

< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin

< SD_SPI Config

< SD_SPI enable

< SD_SPI_CS_GPIO, SD_SPI_MOSI_GPIO, SD_SPI_MISO_GPIO, SD_SPI_DETECT_GPIO and SD_SPI_SCK_GPIO Periph clock enable

< SD_SPI Periph clock enable

< Configure SD_SPI pins: SCK

< Configure SD_SPI pins: MOSI

< Configure SD_SPI pins: MISO

< Configure SD_SPI_CS_PIN pin: SD Card CS pin

< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin

< SD_SPI Config

< SD_SPI enable

< SD_SPI_CS_GPIO, SD_SPI_MOSI_GPIO, SD_SPI_MISO_GPIO, SD_SPI_DETECT_GPIO and SD_SPI_SCK_GPIO Periph clock enable

< SD_SPI Periph clock enable

< AFIO Periph clock enable

< Remap SPI3 Pins

< Configure SD_SPI pins: SCK

< Configure SD_SPI pins: MOSI

< Configure SD_SPI pins: MISO

< Configure SD_SPI_CS_PIN pin: SD Card CS pin

< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin

< SD_SPI Config

< SD_SPI enable

< GPIOC and GPIOD Periph clock enable

< Configure PC.08, PC.09, PC.10, PC.11, PC.12 pin: D0, D1, D2, D3, CLK pin

< Configure PD.02 CMD line

< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin

< Enable the SDIO AHB Clock

< Enable the DMA2 Clock

< SD_SPI_CS_GPIO, SD_SPI_MOSI_GPIO, SD_SPI_MISO_GPIO, SD_SPI_DETECT_GPIO and SD_SPI_SCK_GPIO Periph clock enable

< SD_SPI Periph clock enable

< Configure SD_SPI pins: SCK

< Configure SD_SPI pins: MISO

< Configure SD_SPI pins: MOSI

< Configure SD_SPI_CS_PIN pin: SD Card CS pin

< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin

< SD_SPI Config

< SD_SPI enable

Definition at line 410 of file stm32100b_eval.c.

void sEE_LowLevel_DeInit ( void )

DeInitializes peripherals used by the I2C EEPROM driver.

Parameters:
None
Return values:
None

< sEE_I2C Periph clock disable

< GPIO configuration

< Configure sEE_I2C pins: SCL

< Configure sEE_I2C pins: SDA

< sEE_I2C Periph clock disable

< GPIO configuration

< Configure sEE_I2C pins: SCL

< Configure sEE_I2C pins: SDA

< sEE_I2C Periph clock disable

< GPIO configuration

< Configure sEE_I2C pins: SCL

< Configure sEE_I2C pins: SDA

Definition at line 466 of file stm32100e_eval.c.

void sEE_LowLevel_DMAConfig | ( | uint32_t | pBuffer,
 |  | uint32_t | BufferSize,
 |  | uint32_t | Direction
 | ) |  |

Initializes DMA channel used by the I2C EEPROM driver.

Parameters:
None
Return values:
None

Definition at line 583 of file stm32100e_eval.c.

void sEE_LowLevel_Init ( void )

Initializes peripherals used by the I2C EEPROM driver.

Parameters:
None
Return values:
None

< sEE_I2C_SCL_GPIO_CLK and sEE_I2C_SDA_GPIO_CLK Periph clock enable

< sEE_I2C Periph clock enable

< GPIO configuration

< Configure sEE_I2C pins: SCL

< Configure sEE_I2C pins: SDA

< I2C DMA TX and RX channels configuration

< sEE_I2C_SCL_GPIO_CLK and sEE_I2C_SDA_GPIO_CLK Periph clock enable

< sEE_I2C Periph clock enable

< GPIO configuration

< Configure sEE_I2C pins: SCL

< Configure sEE_I2C pins: SDA

< I2C DMA TX and RX channels configuration

< sEE_I2C Periph clock enable

< sEE_I2C_SCL_GPIO_CLK and sEE_I2C_SDA_GPIO_CLK Periph clock enable

< GPIO configuration

< Configure sEE_I2C pins: SCL

< Configure sEE_I2C pins: SDA

< I2C DMA TX and RX channels configuration

Definition at line 515 of file stm32100e_eval.c.

void STM_EVAL_COMInit | ( | COM_TypeDef | COM,
 |  | USART_InitTypeDef * | USART_InitStruct
 | ) |  |

Configures COM port.

Parameters:
COM,: Specifies the COM port to be configured. This parameter can be one of following parameters:

  • COM1
  • COM2
USART_InitStruct,: pointer to a USART_InitTypeDef structure that contains the configuration information for the specified USART peripheral.
Return values:
None

Definition at line 330 of file stm32100b_eval.c.

void STM_EVAL_LEDInit ( Led_TypeDef Led )

Configures LED GPIO.

Parameters:
Led,: Specifies the Led to be configured. This parameter can be one of following parameters:

  • LED1
  • LED2
  • LED3
  • LED4
Return values:
None

Definition at line 176 of file stm32100b_eval.c.

void STM_EVAL_LEDOff ( Led_TypeDef Led )

Turns selected LED Off.

Parameters:
Led,: Specifies the Led to be set off. This parameter can be one of following parameters:

  • LED1
  • LED2
  • LED3
  • LED4
Return values:
None

Definition at line 216 of file stm32100b_eval.c.

void STM_EVAL_LEDOn ( Led_TypeDef Led )

Turns selected LED On.

Parameters:
Led,: Specifies the Led to be set on. This parameter can be one of following parameters:

  • LED1
  • LED2
  • LED3
  • LED4
Return values:
None

Definition at line 201 of file stm32100b_eval.c.

void STM_EVAL_LEDToggle ( Led_TypeDef Led )

Toggles the selected LED.

Parameters:
Led,: Specifies the Led to be toggled. This parameter can be one of following parameters:

  • LED1
  • LED2
  • LED3
  • LED4
Return values:
None

Definition at line 231 of file stm32100b_eval.c.

uint32_t STM_EVAL_PBGetState ( Button_TypeDef Button )

Returns the selected Button state.

Parameters:
Button,: Specifies the Button to be checked. This parameter can be one of following parameters:

  • BUTTON_WAKEUP: Wakeup Push Button
  • BUTTON_TAMPER: Tamper Push Button
  • BUTTON_KEY: Key Push Button
  • BUTTON_RIGHT: Joystick Right Push Button
  • BUTTON_LEFT: Joystick Left Push Button
  • BUTTON_UP: Joystick Up Push Button
  • BUTTON_DOWN: Joystick Down Push Button
  • BUTTON_SEL: Joystick Sel Push Button
Return values:
The Button GPIO pin value.
Parameters:
Button,: Specifies the Button to be checked. This parameter can be one of following parameters:

  • BUTTON_KEY: Key Push Button
  • BUTTON_RIGHT: Joystick Right Push Button
  • BUTTON_LEFT: Joystick Left Push Button
  • BUTTON_UP: Joystick Up Push Button
  • BUTTON_DOWN: Joystick Down Push Button
  • BUTTON_SEL: Joystick Sel Push Button
Return values:
- When Button > 1, the Button GPIO pin value is returned.

  • When Button = 0 or 1, error code (0xFF) is returned.

Definition at line 314 of file stm32100b_eval.c.

void STM_EVAL_PBInit | ( | Button_TypeDef | Button,
 |  | ButtonMode_TypeDef | Button_Mode
 | ) |  |

Configures Button GPIO and EXTI Line.

Parameters:
Button,: Specifies the Button to be configured. This parameter can be one of following parameters:

  • BUTTON_WAKEUP: Wakeup Push Button
  • BUTTON_TAMPER: Tamper Push Button
  • BUTTON_KEY: Key Push Button
  • BUTTON_RIGHT: Joystick Right Push Button
  • BUTTON_LEFT: Joystick Left Push Button
  • BUTTON_UP: Joystick Up Push Button
  • BUTTON_DOWN: Joystick Down Push Button
  • BUTTON_SEL: Joystick Sel Push Button
Button_Mode,: Specifies Button mode. This parameter can be one of following parameters:

  • BUTTON_MODE_GPIO: Button will be used as simple IO
  • BUTTON_MODE_EXTI: Button will be connected to EXTI line with interrupt generation capability
Return values:
None
Parameters:
Button,: Specifies the Button to be configured. This parameter can be one of following parameters:

  • BUTTON_KEY: Key Push Button
  • BUTTON_RIGHT: Joystick Right Push Button
  • BUTTON_LEFT: Joystick Left Push Button
  • BUTTON_UP: Joystick Up Push Button
  • BUTTON_DOWN: Joystick Down Push Button
  • BUTTON_SEL: Joystick Sel Push Button
Button_Mode,: Specifies Button mode. This parameter can be one of following parameters:

  • BUTTON_MODE_GPIO: Button will be used as simple IO
  • BUTTON_MODE_EXTI: Button will be connected to EXTI line with interrupt generation capability
Return values:
None

Definition at line 255 of file stm32100b_eval.c.


STM32F10x Standard Peripherals Firmware Library: STM3210C_EVAL_IOE_Private_TypesDefinitions

STM3210C_EVAL_IOE_Private_TypesDefinitions

STM3210C_EVAL_IOE


STM32F10x Standard Peripherals Firmware Library: STM3210C_EVAL_IOE_Private_Defines

Defines

STM3210C_EVAL_IOE_Private_Defines

STM3210C_EVAL_IOE

Defines

#define | TIMEOUT_MAX 0x1000
#define | TS_CONVERSION_DELAY 0x10000

Define Documentation

#define TIMEOUT_MAX 0x1000

Definition at line 72 of file stm3210c_eval_ioe.c.

Referenced by I2C_ReadDataBuffer(), I2C_ReadDeviceRegister(), and I2C_WriteDeviceRegister().

#define TS_CONVERSION_DELAY 0x10000

Definition at line 74 of file stm3210c_eval_ioe.c.

Referenced by IOE_TS_GetState().


STM32F10x Standard Peripherals Firmware Library: STM3210C_EVAL_IOE_Private_Macros

STM3210C_EVAL_IOE_Private_Macros

STM3210C_EVAL_IOE


STM32F10x Standard Peripherals Firmware Library: STM3210C_EVAL_IOE_Private_Variables

Variables

STM3210C_EVAL_IOE_Private_Variables

STM3210C_EVAL_IOE

Variables

uint32_t IOE_TimeOut = TIMEOUT_MAX
TS_STATE TS_State

Variable Documentation

uint32_t IOE_TimeOut = TIMEOUT_MAX

Definition at line 96 of file stm3210c_eval_ioe.c.

TS_STATE TS_State

Definition at line 94 of file stm3210c_eval_ioe.c.


STM32F10x Standard Peripherals Firmware Library: STM3210C_EVAL_IOE_Private_FunctionPrototypes

STM3210C_EVAL_IOE_Private_FunctionPrototypes

STM3210C_EVAL_IOE


STM32F10x Standard Peripherals Firmware Library: STM3210C_EVAL_IOE_Private_Functions

Functions

STM3210C_EVAL_IOE_Private_Functions

STM3210C_EVAL_IOE

Functions

static void | delay (__IO uint32_t nCount)
Inserts a delay time.
uint16_t | I2C_ReadDataBuffer (uint8_t DeviceAddr, uint32_t RegisterAddr)
Reads a buffer of 2 bytes from the device registers.
uint8_t | I2C_ReadDeviceRegister (uint8_t DeviceAddr, uint8_t RegisterAddr)
Reads a register of the device through I2C.
uint8_t | I2C_WriteDeviceRegister (uint8_t DeviceAddr, uint8_t RegisterAddr, uint8_t RegisterValue)
Writes a value in a register of the device through I2C.
uint8_t | IOE_ClearGITPending (uint8_t DeviceAddr, uint8_t Global_IT)
Clears the selected Global interrupt pending bit(s)
uint8_t | IOE_ClearIOITPending (uint8_t DeviceAddr, uint8_t IO_IT)
Clears the selected IO interrupt pending bit(s).
uint8_t | IOE_Config (void)
Initializes and Configures the two IO_Expanders Functionalities (IOs, Touch Screen ..) and configures all STM3210C-EVAL necessary hardware (GPIOs, APB clocks ..).
static void | IOE_DMA_Config (IOE_DMADirection_TypeDef Direction, uint8_t *buffer)
Configure the DMA Peripheral used to handle communication via I2C.
static void | IOE_EXTI_Config (void)
Configures the IO expander Interrupt line and GPIO in EXTI mode.
uint8_t | IOE_FnctCmd (uint8_t DeviceAddr, uint8_t Fct, FunctionalState NewState)
Configures the selcted IO Expander functionalities.
FlagStatus | IOE_GetGITStatus (uint8_t DeviceAddr, uint8_t Global_IT)
Checks the selected Global interrupt source pending bit.
FlagStatus | IOE_GetIOITStatus (uint8_t DeviceAddr, uint8_t IO_IT)
Checks the status of the selected IO interrupt pending bit.
uint8_t | IOE_GITCmd (uint8_t DeviceAddr, FunctionalState NewState)
Enables or disables the Global interrupt.
uint8_t | IOE_GITConfig (uint8_t DeviceAddr, uint8_t Global_IT, FunctionalState NewState)
Configures the selected source to generate or not a global interrupt.
static void | IOE_GPIO_Config (void)
Initializes the GPIO pins used by the IO expander.
static void | IOE_I2C_Config (void)
Configure the I2C Peripheral used to communicate with IO_Expanders.
uint8_t | IOE_IOAFConfig (uint8_t DeviceAddr, uint8_t IO_Pin, FunctionalState NewState)
Configures the selected pin to be in Alternate function or not.
uint8_t | IOE_IOEdgeConfig (uint8_t DeviceAddr, uint8_t IO_Pin, uint8_t Edge)
Configures the Edge for which a transition is detectable for the the selected pin.
uint8_t | IOE_IOITConfig (uint8_t DeviceAddr, uint8_t IO_IT, FunctionalState NewState)
Configures the selected pins to generate an interrupt or not.
uint8_t | IOE_IOPinConfig (uint8_t DeviceAddr, uint8_t IO_Pin, uint8_t Direction)
Configures the selected pin direction (to be an input or an output)
uint8_t | IOE_IsOperational (uint8_t DeviceAddr)
Checks if the selected device is correctly configured and communicates correctly ont the I2C bus.
uint8_t | IOE_ITConfig (uint32_t IOE_ITSRC_Source)
Configures The selected interrupts on the IO Expanders.
uint8_t | IOE_ITOutConfig (uint8_t Polarity, uint8_t Type)
Configures the Interrupt line active state and format (level/edge)
JOYState_TypeDef | IOE_JoyStickGetState (void)
Returns the current Joystick status.
uint16_t | IOE_ReadID (uint8_t DeviceAddr)
Reads the selected device's ID.
uint8_t | IOE_ReadIOPin (uint32_t IO_Pin)
Returns the status of the selected input IO pin.
uint8_t | IOE_Reset (uint8_t DeviceAddr)
Resets the IO Expander by Software (SYS_CTRL1, RESET bit).
uint8_t | IOE_TempSens_Config (void)
Configures and enables the Temperature sensor module.
uint32_t | IOE_TempSens_GetData (void)
Returns the temperature row value (in 16 bit format).
uint8_t | IOE_TS_Config (void)
Configures the touch Screen Controller (Single point detection)
TS_STATE * | IOE_TS_GetState (void)
Returns Status and positions of the Touch screen.
static uint16_t | IOE_TS_Read_X (void)
Return Touch Screen X position value.
static uint16_t | IOE_TS_Read_Y (void)
Return Touch Screen Y position value.
static uint16_t | IOE_TS_Read_Z (void)
Return Touch Screen Z position value.
uint8_t | IOE_WriteIOPin (uint8_t IO_Pin, IOE_BitValue_TypeDef BitVal)
Writes a bit value to an output IO pin.

Function Documentation

static void delay ( __IO uint32_t nCount ) [static]

Inserts a delay time.

Parameters:
nCount,: specifies the delay time length.
Return values:
None

Definition at line 1566 of file stm3210c_eval_ioe.c.

References index.

uint16_t I2C_ReadDataBuffer | ( | uint8_t | DeviceAddr,
 |  | uint32_t | RegisterAddr
 | ) |  |

Reads a buffer of 2 bytes from the device registers.

Parameters:
DeviceAddr,: The address of the device, could be : IOE_1_ADDR or IOE_2_ADDR.
RegisterAddr,: The target register adress (between 00x and 0x24)
Return values:
A pointer to the buffer containing the two returned bytes (in halfword).

Definition at line 1251 of file stm3210c_eval_ioe.c.

References DISABLE, DMA_ClearFlag(), DMA_Cmd(), DMA_GetFlagStatus(), ENABLE, I2C_CheckEvent(), I2C_Direction_Receiver, I2C_Direction_Transmitter, I2C_DMACmd(), I2C_DMALastTransferCmd(), I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED, I2C_FLAG_BTF, I2C_FLAG_SB, I2C_FLAG_TXE, I2C_GenerateSTART(), I2C_GenerateSTOP(), I2C_GetFlagStatus(), I2C_Send7bitAddress(), I2C_SendData(), IOE_DMA_Config(), IOE_DMA_RX, IOE_DMA_RX_CHANNEL, IOE_DMA_RX_TCFLAG, IOE_I2C, IOE_TimeOut, IOE_TimeoutUserCallback, and TIMEOUT_MAX.

uint8_t I2C_ReadDeviceRegister | ( | uint8_t | DeviceAddr,
 |  | uint8_t | RegisterAddr
 | ) |  |

Reads a register of the device through I2C.

Parameters:
DeviceAddr,: The address of the device, could be : IOE_1_ADDR or IOE_2_ADDR.
RegisterAddr,: The target register adress (between 00x and 0x24)
Return values:
The value of the read register (0xAA if Timout occured)

Definition at line 1154 of file stm3210c_eval_ioe.c.

References DISABLE, DMA_ClearFlag(), DMA_Cmd(), DMA_GetFlagStatus(), ENABLE, I2C_CheckEvent(), I2C_Direction_Receiver, I2C_Direction_Transmitter, I2C_DMACmd(), I2C_DMALastTransferCmd(), I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED, I2C_FLAG_BTF, I2C_FLAG_SB, I2C_FLAG_TXE, I2C_GenerateSTART(), I2C_GenerateSTOP(), I2C_GetFlagStatus(), I2C_Send7bitAddress(), I2C_SendData(), IOE_DMA_Config(), IOE_DMA_RX, IOE_DMA_RX_CHANNEL, IOE_DMA_RX_TCFLAG, IOE_I2C, IOE_TimeOut, IOE_TimeoutUserCallback, and TIMEOUT_MAX.

uint8_t I2C_WriteDeviceRegister | ( | uint8_t | DeviceAddr,
 |  | uint8_t | RegisterAddr,
 |  | uint8_t | RegisterValue
 | ) |  |

Writes a value in a register of the device through I2C.

Parameters:
DeviceAddr,: The address of the IOExpander, could be : IOE_1_ADDR or IOE_2_ADDR.
RegisterAddr,: The target register adress
RegisterValue,: The target register value to be written
Return values:
IOE_OK,: if all operations are OK. Other value if error.

Definition at line 1053 of file stm3210c_eval_ioe.c.

References DISABLE, DMA_ClearFlag(), DMA_Cmd(), DMA_GetFlagStatus(), ENABLE, I2C_CheckEvent(), I2C_Direction_Transmitter, I2C_DMACmd(), I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED, I2C_FLAG_BTF, I2C_FLAG_SB, I2C_FLAG_TXE, I2C_GenerateSTART(), I2C_GenerateSTOP(), I2C_GetFlagStatus(), I2C_ReadDeviceRegister(), I2C_Send7bitAddress(), I2C_SendData(), IOE_DMA_Config(), IOE_DMA_TX, IOE_DMA_TX_CHANNEL, IOE_DMA_TX_TCFLAG, IOE_FAILURE, IOE_I2C, IOE_TimeOut, IOE_TimeoutUserCallback, RESET, and TIMEOUT_MAX.

uint8_t IOE_ClearGITPending | ( | uint8_t | DeviceAddr,
 |  | uint8_t | Global_IT
 | ) |  |

Clears the selected Global interrupt pending bit(s)

Parameters:
DeviceAddr,: The address of the IOExpander, could be : IOE_1_ADDR or IOE_2_ADDR.
Global_IT,: the Global interrupt to be cleared, could be any combination of the following values:

  • Global_IT_GPIO : All IOs interrupt
  • Global_IT_ADC : ADC interrupt
  • Global_IT_TEMP : Temperature Sensor interrupts
  • Global_IT_FE : Touch Screen Controller FIFO Error interrupt
  • Global_IT_FF : Touch Screen Controller FIFO Full interrupt
  • Global_IT_FOV : Touch Screen Controller FIFO Overrun interrupt
  • Global_IT_FTH : Touch Screen Controller FIFO Threshold interrupt
  • Global_IT_TOUCH : Touch Screen Controller Touch Detected interrupt
Return values:
IOE_OK,: if all initializations are OK. Other value if error.

Definition at line 536 of file stm3210c_eval_ioe.c.

References I2C_WriteDeviceRegister(), IOE_OK, and IOE_REG_INT_STA.

uint8_t IOE_ClearIOITPending | ( | uint8_t | DeviceAddr,
 |  | uint8_t | IO_IT
 | ) |  |

Clears the selected IO interrupt pending bit(s).

Parameters:
DeviceAddr,: The address of the IOExpander, could be : IOE_1_ADDR or IOE_2_ADDR.
IO_IT,: the IO interrupt to be checked could be IO_ITx Where x can be from 0 to 7.
Return values:
IOE_OK,: if all initializations are OK. Other value if error.

Definition at line 578 of file stm3210c_eval_ioe.c.

References I2C_WriteDeviceRegister(), IOE_2_ADDR, IOE_OK, IOE_REG_GPIO_ED, IOE_REG_GPIO_FE, IOE_REG_GPIO_INT_STA, and IOE_REG_GPIO_RE.

uint8_t IOE_Config ( void )

Initializes and Configures the two IO_Expanders Functionalities (IOs, Touch Screen ..) and configures all STM3210C-EVAL necessary hardware (GPIOs, APB clocks ..).

Configuration and initialization functions.

Parameters:
None
Return values:
IOE_OK if all initializations done correctly. Other value if error.

Definition at line 135 of file stm3210c_eval_ioe.c.

References AUDIO_RESET_PIN, BitReset, Direction_IN, Direction_OUT, EDGE_FALLING, EDGE_RISING, ENABLE, IOE1_NOT_OPERATIONAL, IOE2_NOT_OPERATIONAL, IOE_1_ADDR, IOE_2_ADDR, IOE_ADC_FCT, IOE_FnctCmd(), IOE_GPIO_Config(), IOE_I2C_Config(), IOE_IO_FCT, IOE_IOAFConfig(), IOE_IOEdgeConfig(), IOE_IOPinConfig(), IOE_IsOperational(), IOE_OK, IOE_Reset(), IOE_TempSens_Config(), IOE_TEMPSENS_FCT, IOE_TS_Config(), IOE_TS_FCT, IOE_WriteIOPin(), JOY_IO_PINS, MEMS_INT1_PIN, MEMS_INT2_PIN, MII_INT_PIN, and VBAT_DIV_PIN.

static void IOE_DMA_Config | ( | IOE_DMADirection_TypeDef | Direction,
 |  | uint8_t * | buffer
 | ) |  | [static]

Configure the DMA Peripheral used to handle communication via I2C.

Parameters:
None
Return values:
None

Definition at line 1470 of file stm3210c_eval_ioe.c.

References DMA_InitTypeDef::DMA_BufferSize, DMA_DeInit(), DMA_InitTypeDef::DMA_DIR, DMA_DIR_PeripheralDST, DMA_DIR_PeripheralSRC, DMA_Init(), DMA_InitStructure, DMA_InitTypeDef::DMA_M2M, DMA_M2M_Disable, DMA_InitTypeDef::DMA_MemoryBaseAddr, DMA_InitTypeDef::DMA_MemoryDataSize, DMA_MemoryDataSize_Byte, DMA_InitTypeDef::DMA_MemoryInc, DMA_MemoryInc_Enable, DMA_InitTypeDef::DMA_Mode, DMA_Mode_Normal, DMA_InitTypeDef::DMA_PeripheralBaseAddr, DMA_InitTypeDef::DMA_PeripheralDataSize, DMA_PeripheralDataSize_Byte, DMA_InitTypeDef::DMA_PeripheralInc, DMA_PeripheralInc_Disable, DMA_InitTypeDef::DMA_Priority, DMA_Priority_VeryHigh, ENABLE, IOE_DMA_CLK, IOE_DMA_RX, IOE_DMA_RX_CHANNEL, IOE_DMA_TX, IOE_DMA_TX_CHANNEL, IOE_I2C_DR, and RCC_AHBPeriphClockCmd().

Referenced by I2C_ReadDataBuffer(), I2C_ReadDeviceRegister(), and I2C_WriteDeviceRegister().

static void IOE_EXTI_Config ( void ) [static]

Configures the IO expander Interrupt line and GPIO in EXTI mode.

Parameters:
None
Return values:
None

Definition at line 1528 of file stm3210c_eval_ioe.c.

References ENABLE, EXTI_Init(), EXTI_InitStructure, EXTI_InitTypeDef::EXTI_Line, EXTI_InitTypeDef::EXTI_LineCmd, EXTI_InitTypeDef::EXTI_Mode, EXTI_Mode_Interrupt, EXTI_InitTypeDef::EXTI_Trigger, EXTI_Trigger_Rising_Falling, GPIO_EXTILineConfig(), GPIO_Init(), GPIO_InitStructure, GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_IN_FLOATING, GPIO_InitTypeDef::GPIO_Pin, IOE_IT_EXTI_IRQn, IOE_IT_EXTI_LINE, IOE_IT_EXTI_PIN_SOURCE, IOE_IT_EXTI_PORT_SOURCE, IOE_IT_GPIO_CLK, IOE_IT_GPIO_PORT, IOE_IT_PIN, NVIC_Init(), NVIC_InitStructure, NVIC_InitTypeDef::NVIC_IRQChannel, NVIC_InitTypeDef::NVIC_IRQChannelCmd, NVIC_InitTypeDef::NVIC_IRQChannelPreemptionPriority, NVIC_InitTypeDef::NVIC_IRQChannelSubPriority, RCC_APB2Periph_AFIO, and RCC_APB2PeriphClockCmd().

Referenced by IOE_ITConfig().

uint8_t IOE_FnctCmd | ( | uint8_t | DeviceAddr,
 |  | uint8_t | Fct,
 |  | FunctionalState | NewState
 | ) |  |

Configures the selcted IO Expander functionalities.

Parameters:
DeviceAddr,: The address of the IOExpander, could be : IOE_1_ADDR or IOE_2_ADDR.
IOE_TEMPSENS_FCT,: the functions to be configured. could be any combination of the following values:

  • IOE_IO_FCT : IO function
  • IOE_TS_FCT : Touch Screen function
  • IOE_ADC_FCT : ADC function
  • IOE_TEMPSENS_FCT : Tempreature Sensor function
Return values:
IOE_OK,: if all initializations are OK. Other value if error.

Definition at line 676 of file stm3210c_eval_ioe.c.

References DISABLE, I2C_ReadDeviceRegister(), I2C_WriteDeviceRegister(), IOE_OK, and IOE_REG_SYS_CTRL2.

FlagStatus IOE_GetGITStatus | ( | uint8_t | DeviceAddr,
 |  | uint8_t | Global_IT
 | ) |  |

Checks the selected Global interrupt source pending bit.

Interrupts Mangement functions.

Parameters:
DeviceAddr,: The address of the IOExpander, could be : IOE_1_ADDR or IOE_2_ADDR.
Global_IT,: the Global interrupt source to be checked, could be:

  • Global_IT_GPIO : All IOs interrupt
  • Global_IT_ADC : ADC interrupt
  • Global_IT_TEMP : Temperature Sensor interrupts
  • Global_IT_FE : Touch Screen Controller FIFO Error interrupt
  • Global_IT_FF : Touch Screen Controller FIFO Full interrupt
  • Global_IT_FOV : Touch Screen Controller FIFO Overrun interrupt
  • Global_IT_FTH : Touch Screen Controller FIFO Threshold interrupt
  • Global_IT_TOUCH : Touch Screen Controller Touch Detected interrupt
Return values:
Status of the checked flag. Could be SET or RESET.

Definition at line 503 of file stm3210c_eval_ioe.c.

References I2C_ReadDeviceRegister(), IOE_REG_INT_STA, RESET, and SET.

FlagStatus IOE_GetIOITStatus | ( | uint8_t | DeviceAddr,
 |  | uint8_t | IO_IT
 | ) |  |

Checks the status of the selected IO interrupt pending bit.

Parameters:
DeviceAddr,: The address of the IOExpander, could be : IOE_1_ADDR or IOE_2_ADDR.
IO_IT,: the IO interrupt to be checked could be IO_ITx Where x can be from 0 to 7.
Return values:
Status of the checked flag. Could be SET or RESET.

Definition at line 553 of file stm3210c_eval_ioe.c.

References I2C_ReadDeviceRegister(), IOE_REG_GPIO_INT_STA, RESET, and SET.

uint8_t IOE_GITCmd | ( | uint8_t | DeviceAddr,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the Global interrupt.

Parameters:
DeviceAddr,: The address of the IOExpander, could be :I OE_1_ADDR or IOE_2_ADDR.
NewState,: could be ENABLE or DISABLE.
Return values:
IOE_OK,: if all initializations are OK. Other value if error.

Definition at line 739 of file stm3210c_eval_ioe.c.

References DISABLE, I2C_ReadDeviceRegister(), I2C_WriteDeviceRegister(), IOE_GIT_EN, IOE_OK, and IOE_REG_INT_CTRL.

uint8_t IOE_GITConfig | ( | uint8_t | DeviceAddr,
 |  | uint8_t | Global_IT,
 |  | FunctionalState | NewState
 | ) |  |

Configures the selected source to generate or not a global interrupt.

Parameters:
DeviceAddr,: The address of the IOExpander, could be : IOE_1_ADDR or IOE_2_ADDR.
Global_IT,: the interrupt source to be configured, could be:

  • Global_IT_GPIO : All IOs interrupt
  • Global_IT_ADC : ADC interrupt
  • Global_IT_TEMP : Temperature Sensor interrupts
  • Global_IT_FE : Touch Screen Controller FIFO Error interrupt
  • Global_IT_FF : Touch Screen Controller FIFO Full interrupt
  • Global_IT_FOV : Touch Screen Controller FIFO Overrun interrupt
  • Global_IT_FTH : Touch Screen Controller FIFO Threshold interrupt
  • Global_IT_TOUCH : Touch Screen Controller Touch Detected interrupt
Return values:
IOE_OK,: if all initializations are OK. Other value if error.

Definition at line 779 of file stm3210c_eval_ioe.c.

References DISABLE, I2C_ReadDeviceRegister(), I2C_WriteDeviceRegister(), IOE_OK, and IOE_REG_INT_EN.

static void IOE_GPIO_Config ( void ) [static]

Initializes the GPIO pins used by the IO expander.

Parameters:
None
Return values:
None

Definition at line 1409 of file stm3210c_eval_ioe.c.

References DISABLE, ENABLE, GPIO_EXTILineConfig(), GPIO_Init(), GPIO_InitStructure, GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_AF_OD, GPIO_Mode_IPU, GPIO_InitTypeDef::GPIO_Pin, GPIO_InitTypeDef::GPIO_Speed, GPIO_Speed_10MHz, IOE_I2C_CLK, IOE_I2C_SCL_GPIO_CLK, IOE_I2C_SCL_GPIO_PORT, IOE_I2C_SCL_PIN, IOE_I2C_SDA_GPIO_CLK, IOE_I2C_SDA_GPIO_PORT, IOE_I2C_SDA_PIN, IOE_IT_EXTI_PIN_SOURCE, IOE_IT_EXTI_PORT_SOURCE, IOE_IT_GPIO_CLK, IOE_IT_GPIO_PORT, IOE_IT_PIN, RCC_APB1PeriphClockCmd(), RCC_APB1PeriphResetCmd(), RCC_APB2Periph_AFIO, and RCC_APB2PeriphClockCmd().

Referenced by IOE_Config().

static void IOE_I2C_Config ( void ) [static]

Configure the I2C Peripheral used to communicate with IO_Expanders.

Parameters:
None
Return values:
None

Definition at line 1449 of file stm3210c_eval_ioe.c.

References I2C_InitTypeDef::I2C_Ack, I2C_Ack_Enable, I2C_InitTypeDef::I2C_AcknowledgedAddress, I2C_AcknowledgedAddress_7bit, I2C_InitTypeDef::I2C_ClockSpeed, I2C_InitTypeDef::I2C_DutyCycle, I2C_DutyCycle_2, I2C_Init(), I2C_InitStructure, I2C_InitTypeDef::I2C_Mode, I2C_Mode_I2C, I2C_InitTypeDef::I2C_OwnAddress1, IOE_I2C, and IOE_I2C_SPEED.

Referenced by IOE_Config().

uint8_t IOE_IOAFConfig | ( | uint8_t | DeviceAddr,
 |  | uint8_t | IO_Pin,
 |  | FunctionalState | NewState
 | ) |  |

Configures the selected pin to be in Alternate function or not.

Parameters:
DeviceAddr,: The address of the IOExpander, could be : IOE_1_ADDR or IOE_2_ADDR.
IO_Pin,: IO_Pin_x, Where x can be from 0 to 7.
NewState,: State of the AF for the selected pin, could be ENABLE or DISABLE.
Return values:
IOE_OK,: if all initializations are OK. Other value if error.

Definition at line 935 of file stm3210c_eval_ioe.c.

References DISABLE, I2C_ReadDeviceRegister(), I2C_WriteDeviceRegister(), IOE_OK, and IOE_REG_GPIO_AF.

uint8_t IOE_IOEdgeConfig | ( | uint8_t | DeviceAddr,
 |  | uint8_t | IO_Pin,
 |  | uint8_t | Edge
 | ) |  |

Configures the Edge for which a transition is detectable for the the selected pin.

Parameters:
DeviceAddr,: The address of the IOExpander, could be : IOE_1_ADDR or IOE_2_ADDR.
IO_Pin,: IO_Pin_x, Where x can be from 0 to 7.
Edge,: The edge which will be detected. This parameter can be one or a a combination of follwing values: EDGE_FALLING and EDGE_RISING .
Return values:
IOE_OK,: if all initializations are OK. Other value if error.

Definition at line 970 of file stm3210c_eval_ioe.c.

References EDGE_FALLING, EDGE_RISING, I2C_ReadDeviceRegister(), I2C_WriteDeviceRegister(), IOE_OK, IOE_REG_GPIO_FE, and IOE_REG_GPIO_RE.

uint8_t IOE_IOITConfig | ( | uint8_t | DeviceAddr,
 |  | uint8_t | IO_IT,
 |  | FunctionalState | NewState
 | ) |  |

Configures the selected pins to generate an interrupt or not.

Parameters:
DeviceAddr,: The address of the IOExpander, could be : IOE_1_ADDR or IOE_2_ADDR.
IO_IT,: The IO interrupt to be configured. This parameter could be any combination of the following values:

  • IO_IT_x: where x can be from 0 to 7.
NewState,: could be ENABLE or DISABLE.
Return values:
IOE_OK,: if all initializations are OK. Other value if error.

Definition at line 813 of file stm3210c_eval_ioe.c.

References DISABLE, I2C_ReadDeviceRegister(), I2C_WriteDeviceRegister(), IOE_OK, and IOE_REG_GPIO_INT_EN.

uint8_t IOE_IOPinConfig | ( | uint8_t | DeviceAddr,
 |  | uint8_t | IO_Pin,
 |  | uint8_t | Direction
 | ) |  |

Configures the selected pin direction (to be an input or an output)

Parameters:
DeviceAddr,: The address of the IOExpander, could be : IOE_1_ADDR or IOE_2_ADDR.
IO_Pin,: IO_Pin_x: Where x can be from 0 to 7.
Direction,: could be Direction_IN or Direction_OUT.
Return values:
IOE_OK,: if all initializations are OK. Other value if error.

Definition at line 709 of file stm3210c_eval_ioe.c.

References Direction_IN, I2C_ReadDeviceRegister(), I2C_WriteDeviceRegister(), IOE_OK, and IOE_REG_GPIO_DIR.

uint8_t IOE_IsOperational ( uint8_t DeviceAddr )

Checks if the selected device is correctly configured and communicates correctly ont the I2C bus.

IO-Expander Control functions.

Parameters:
DeviceAddr,: The address of the IOExpander, could be : IOE_1_ADDR or IOE_2_ADDR.
Return values:
IOE_OK if IOE is operational. Other value if failure.

Definition at line 603 of file stm3210c_eval_ioe.c.

References IOE_FAILURE, IOE_OK, IOE_ReadID(), IOE_TimeOut, IOE_TimeoutUserCallback, and STMPE811_ID.

uint8_t IOE_ITConfig ( uint32_t IOE_ITSRC_Source )

Configures The selected interrupts on the IO Expanders.

Parameters:
IOE_ITSRC_Source,: the source of the interrupts. Could be one or a combination of the following parameters:

  • IOE_ITSRC_JOYSTICK: Joystick IO intputs.
  • IOE_ITSRC_TSC: Touch Screen interrupts.
  • IOE_ITSRC_INMEMS: MEMS interrupt lines.
Return values:
IOE_OK,: if all initializations are OK. Other value if error.

Definition at line 218 of file stm3210c_eval_ioe.c.

References ENABLE, I2C_ReadDeviceRegister(), IOE_1_ADDR, IOE_2_ADDR, IOE_EXTI_Config(), IOE_GIT_FOV, IOE_GIT_FTH, IOE_GIT_GPIO, IOE_GIT_TOUCH, IOE_GITCmd(), IOE_GITConfig(), IOE_INMEMS_IT, IOE_IOITConfig(), IOE_ITOutConfig(), IOE_ITSRC_INMEMS, IOE_ITSRC_JOYSTICK, IOE_ITSRC_TSC, IOE_JOY_IT, IOE_OK, IOE_REG_GPIO_INT_STA, Polarity_High, Polarity_Low, and Type_Level.

uint8_t IOE_ITOutConfig | ( | uint8_t | Polarity,
 |  | uint8_t | Type
 | ) |  |

Configures the Interrupt line active state and format (level/edge)

Parameters:
Polarity,: could be

  • Polarity_Low: Interrupt line is active Low/Falling edge
  • Polarity_High: Interrupt line is active High/Rising edge
Type,: Interrupt line activity type, could be one of the following values

  • Type_Level: Interrupt line is active in level model
  • Type_Edge: Interrupt line is active in edge model
Return values:
IOE_OK,: if all initializations are OK. Other value if error.

Definition at line 1013 of file stm3210c_eval_ioe.c.

References I2C_ReadDeviceRegister(), I2C_WriteDeviceRegister(), IOE_1_ADDR, IOE_2_ADDR, IOE_OK, and IOE_REG_INT_CTRL.

JOYState_TypeDef IOE_JoyStickGetState ( void )

Returns the current Joystick status.

Parameters:
None
Return values:
The code of the Joystick key pressed:

  • JOY_NONE
  • JOY_SEL
  • JOY_DOWN
  • JOY_LEFT
  • JOY_RIGHT
  • JOY_UP

Definition at line 383 of file stm3210c_eval_ioe.c.

References I2C_ReadDeviceRegister(), IOE_2_ADDR, IOE_REG_GPIO_MP_STA, JOY_DOWN, JOY_IO_DOWN, JOY_IO_LEFT, JOY_IO_NONE, JOY_IO_RIGHT, JOY_IO_SEL, JOY_IO_UP, JOY_LEFT, JOY_NONE, JOY_RIGHT, JOY_SEL, and JOY_UP.

Referenced by EXTI15_10_IRQHandler(), main(), and ReadKey().

uint16_t IOE_ReadID ( uint8_t DeviceAddr )

Reads the selected device's ID.

Parameters:
DeviceAddr,: The address of the IOExpander, could be : IOE_1_ADDR or IOE_2_ADDR.
Return values:
The Device ID (two bytes).

Definition at line 651 of file stm3210c_eval_ioe.c.

References I2C_ReadDeviceRegister().

uint8_t IOE_ReadIOPin ( uint32_t IO_Pin )

Returns the status of the selected input IO pin.

Parameters:
IO_Pin,: The input pin to be read. This parameter can be one of the following values:

  • MEMS_INT1_PIN: MEMS interrupt line 1.
  • MEMS_INT2_PIN: MEMS interrupt line 2.
  • JOY_IO_PINS: Joystick IO pins (use IOE_JoyStickGetState for these pins)
Return values:
None

Definition at line 341 of file stm3210c_eval_ioe.c.

References BitReset, BitSet, I2C_ReadDeviceRegister(), IO1_IN_ALL_PINS, IO2_IN_ALL_PINS, IOE_1_ADDR, IOE_2_ADDR, IOE_REG_GPIO_MP_STA, and PARAM_ERROR.

uint8_t IOE_Reset ( uint8_t DeviceAddr )

Resets the IO Expander by Software (SYS_CTRL1, RESET bit).

Parameters:
DeviceAddr,: The address of the IOExpander, could be : IOE_1_ADDR or IOE_2_ADDR.
Return values:
IOE_OK,: if all initializations are OK. Other value if error.

Definition at line 630 of file stm3210c_eval_ioe.c.

References _delay_, I2C_WriteDeviceRegister(), IOE_OK, and IOE_REG_SYS_CTRL1.

uint8_t IOE_TempSens_Config ( void )

Configures and enables the Temperature sensor module.

Parameters:
None
Return values:
IOE_OK if all initializations are OK. Other value if error.

Definition at line 907 of file stm3210c_eval_ioe.c.

References I2C_ReadDeviceRegister(), I2C_WriteDeviceRegister(), IOE_1_ADDR, IOE_2_ADDR, IOE_ADC_FCT, IOE_OK, IOE_REG_SYS_CTRL2, IOE_REG_TEMP_CTRL, and IOE_TEMPSENS_FCT.

uint32_t IOE_TempSens_GetData ( void )

Returns the temperature row value (in 16 bit format).

Temperature Sensor functions.

Parameters:
None
Return values:
The temperature row value.

Definition at line 470 of file stm3210c_eval_ioe.c.

References I2C_ReadDeviceRegister(), I2C_WriteDeviceRegister(), IOE_1_ADDR, IOE_2_ADDR, IOE_REG_TEMP_CTRL, and IOE_REG_TEMP_DATA.

uint8_t IOE_TS_Config ( void )

Configures the touch Screen Controller (Single point detection)

Low Layer functions.

Parameters:
None
Return values:
IOE_OK if all initializations are OK. Other value if error.

Definition at line 842 of file stm3210c_eval_ioe.c.

References _delay_, I2C_ReadDeviceRegister(), I2C_WriteDeviceRegister(), IOE_1_ADDR, IOE_ADC_FCT, IOE_GIT_FOV, IOE_GIT_FTH, IOE_GIT_TOUCH, IOE_OK, IOE_REG_ADC_CTRL1, IOE_REG_ADC_CTRL2, IOE_REG_FIFO_STA, IOE_REG_FIFO_TH, IOE_REG_GPIO_AF, IOE_REG_INT_EN, IOE_REG_INT_STA, IOE_REG_SYS_CTRL2, IOE_REG_TSC_CFG, IOE_REG_TSC_CTRL, IOE_REG_TSC_FRACT_XYZ, IOE_REG_TSC_I_DRIVE, IOE_TS_FCT, TOUCH_IO_ALL, TS_STATE::TouchDetected, TS_STATE::X, TS_STATE::Y, and TS_STATE::Z.

TS_STATE* IOE_TS_GetState ( void )

Returns Status and positions of the Touch screen.

Touch Screen controller functions.

Parameters:
None
Return values:
Pointer to TS_STATE structure holding Touch Screen information.

Definition at line 425 of file stm3210c_eval_ioe.c.

References I2C_ReadDeviceRegister(), I2C_WriteDeviceRegister(), IOE_1_ADDR, IOE_REG_FIFO_STA, IOE_REG_TSC_CTRL, IOE_TS_Read_X(), IOE_TS_Read_Y(), IOE_TS_Read_Z(), TS_STATE::TouchDetected, TS_CONVERSION_DELAY, TS_State, TS_STATE::X, TS_STATE::Y, and TS_STATE::Z.

static uint16_t IOE_TS_Read_X ( void ) [static]

Return Touch Screen X position value.

Parameters:
None
Return values:
X position.

Definition at line 1351 of file stm3210c_eval_ioe.c.

References I2C_ReadDataBuffer(), IOE_1_ADDR, and IOE_REG_TSC_DATA_Y.

Referenced by IOE_TS_GetState().

static uint16_t IOE_TS_Read_Y ( void ) [static]

Return Touch Screen Y position value.

Parameters:
None
Return values:
Y position.

Definition at line 1373 of file stm3210c_eval_ioe.c.

References I2C_ReadDataBuffer(), IOE_1_ADDR, and IOE_REG_TSC_DATA_X.

Referenced by IOE_TS_GetState().

static uint16_t IOE_TS_Read_Z ( void ) [static]

Return Touch Screen Z position value.

Parameters:
None
Return values:
Z position.

Definition at line 1392 of file stm3210c_eval_ioe.c.

References I2C_ReadDataBuffer(), IOE_1_ADDR, and IOE_REG_TSC_DATA_Z.

Referenced by IOE_TS_GetState().

uint8_t IOE_WriteIOPin | ( | uint8_t | IO_Pin,
 |  | IOE_BitValue_TypeDef | BitVal
 | ) |  |

Writes a bit value to an output IO pin.

IO pins control functions.

Parameters:
IO_Pin,: The output pin to be set or reset. This parameter can be one of the following values:

  • AUDIO_RESET_PIN: Audio codec reset pin
  • MII_INT_PIN: Ethernet Phy MII interrupt pin
  • VBAT_DIV_PIN: Battery devider pin
BitVal,: The value to be set. This parameter can be one of the following values: BitSet or BitReset. See IOE_BitVal_TypeDef.
Return values:
IOE_OK or PARAM_ERROR

Definition at line 298 of file stm3210c_eval_ioe.c.

References BitReset, I2C_WriteDeviceRegister(), IO1_OUT_ALL_PINS, IO2_OUT_ALL_PINS, IOE_1_ADDR, IOE_2_ADDR, IOE_OK, IOE_REG_GPIO_CLR_PIN, IOE_REG_GPIO_SET_PIN, and PARAM_ERROR.


STM32F10x Standard Peripherals Firmware Library: STM3210C_EVAL_IOE_Exported_Types

Data Structures | Enumerations

STM3210C_EVAL_IOE_Exported_Types

STM3210C_EVAL_IOE

Data Structures

struct | TS_STATE
Touch Screen Information structure. More...

Enumerations

enum | IOE_BitValue_TypeDef { BitReset = 0, BitSet = 1, BitReset = 0, BitSet = 1 }

IO bit values.

More...
enum | IOE_DMADirection_TypeDef { IOE_DMA_TX = 0, IOE_DMA_RX = 1, IOE_DMA_TX = 0, IOE_DMA_RX = 1 }

IOE DMA Direction.

More...
enum IOE_Status_TypDef {
IOE_OK = 0, IOE_FAILURE, IOE_TIMEOUT, PARAM_ERROR,
IOE1_NOT_OPERATIONAL, IOE_OK = 0, IOE_FAILURE, IOE_TIMEOUT,
PARAM_ERROR, IOE1_NOT_OPERATIONAL, IOE2_NOT_OPERATIONAL
}

IO_Expander Error codes.

More...
enum JOYState_TypeDef {
JOY_NONE = 0, JOY_SEL = 1, JOY_DOWN = 2, JOY_LEFT = 3,
JOY_RIGHT = 4, JOY_UP = 5, JOY_NONE = 0, JOY_SEL = 1,
JOY_DOWN = 2, JOY_LEFT = 3, JOY_RIGHT = 4, JOY_UP = 5
}

Joystick State definitions.

More...

Enumeration Type Documentation

enum IOE_BitValue_TypeDef

IO bit values.

Enumerator:
BitReset
BitSet
BitReset
BitSet

Definition at line 109 of file stm3210c_eval_ioe.h.

enum IOE_DMADirection_TypeDef

IOE DMA Direction.

Enumerator:
IOE_DMA_TX
IOE_DMA_RX
IOE_DMA_TX
IOE_DMA_RX

Definition at line 118 of file stm3210c_eval_ioe.h.

enum IOE_Status_TypDef

IO_Expander Error codes.

Enumerator:
IOE_OK
IOE_FAILURE
IOE_TIMEOUT
PARAM_ERROR
IOE1_NOT_OPERATIONAL
IOE_OK
IOE_FAILURE
IOE_TIMEOUT
PARAM_ERROR
IOE1_NOT_OPERATIONAL
IOE2_NOT_OPERATIONAL

Definition at line 96 of file stm3210c_eval_ioe.h.

enum JOYState_TypeDef

Joystick State definitions.

Enumerator:
JOY_NONE
JOY_SEL
JOY_DOWN
JOY_LEFT
JOY_RIGHT
JOY_UP
JOY_NONE
JOY_SEL
JOY_DOWN
JOY_LEFT
JOY_RIGHT
JOY_UP

Definition at line 81 of file stm3210c_eval_ioe.h.


STM32F10x Standard Peripherals Firmware Library: STM3210C_EVAL_IOE_Exported_Constants

Defines

STM3210C_EVAL_IOE_Exported_Constants

STM3210C_EVAL_IOE

Defines

#define | _delay_ delay
Uncomment the line below to enable verfying each written byte in write operation.
#define | ALL_IT 0xFF
#define | AUDIO_RESET_PIN IO_Pin_2 /* IO_Exapnader_2 */
Eval Board IO Pins definition.
#define | Direction_IN 0x00
IO Pin directions.
#define | Direction_OUT 0x01
#define | EDGE_FALLING 0x01
Edge detection value.
#define | EDGE_RISING 0x02
#define | IO1_IN_ALL_PINS (uint32_t)(MEMS_INT1_PIN | MEMS_INT2_PIN)
Eval Board both IO Exapanders Pins definition.
#define | IO1_OUT_ALL_PINS (uint32_t)(VBAT_DIV_PIN)
#define | IO2_IN_ALL_PINS (uint32_t)(JOY_IO_PINS)
#define | IO2_OUT_ALL_PINS (uint32_t)(AUDIO_RESET_PIN | MII_INT_PIN)
#define | IO_IT_0 0x01
IO Interrupts.
#define | IO_IT_1 0x02
#define | IO_IT_2 0x04
#define | IO_IT_3 0x08
#define | IO_IT_4 0x10
#define | IO_IT_5 0x20
#define | IO_IT_6 0x40
#define | IO_IT_7 0x80
#define | IO_Pin_0 0x01
IO Pins.
#define | IO_Pin_1 0x02
#define | IO_Pin_2 0x04
#define | IO_Pin_3 0x08
#define | IO_Pin_4 0x10
#define | IO_Pin_5 0x20
#define | IO_Pin_6 0x40
#define | IO_Pin_7 0x80
#define | IO_Pin_ALL 0xFF
#define | IOE_1_ADDR 0x82
The 7 bits IO Expanders adresses and chip IDs.
#define | IOE_2_ADDR 0x88
#define | IOE_ADC_FCT 0x01
IO Expander Functionalities definitions.
#define | IOE_DMA DMA1
IOE DMA definitions.
#define | IOE_DMA_CLK RCC_AHBPeriph_DMA1
#define | IOE_DMA_RX_CHANNEL DMA1_Channel7
#define | IOE_DMA_RX_TCFLAG DMA1_FLAG_TC7
#define | IOE_DMA_TX_CHANNEL DMA1_Channel6
#define | IOE_DMA_TX_TCFLAG DMA1_FLAG_TC6
#define | IOE_GIT_ADC 0x40
#define | IOE_GIT_EN 0x01
Global interrupt Enable bit.
#define | IOE_GIT_FE 0x10
#define | IOE_GIT_FF 0x08
#define | IOE_GIT_FOV 0x04
#define | IOE_GIT_FTH 0x02
#define | IOE_GIT_GPIO 0x80
Glaobal Interrupts definitions.
#define | IOE_GIT_TEMP 0x20
#define | IOE_GIT_TOUCH 0x01
#define | IOE_I2C I2C1
I2C port definitions.
#define | IOE_I2C_CLK RCC_APB1Periph_I2C1
#define | IOE_I2C_DR ((uint32_t)0x40005410)
#define | IOE_I2C_SCL_GPIO_CLK RCC_APB2Periph_GPIOB
#define | IOE_I2C_SCL_GPIO_PORT GPIOB
#define | IOE_I2C_SCL_PIN GPIO_Pin_6
#define | IOE_I2C_SDA_GPIO_CLK RCC_APB2Periph_GPIOB
#define | IOE_I2C_SDA_GPIO_PORT GPIOB
#define | IOE_I2C_SDA_PIN GPIO_Pin_7
#define | IOE_I2C_SPEED 300000
#define | IOE_INMEMS_IT (uint8_t)(IO_IT_2 | IO_IT_3)
#define | IOE_IO_FCT 0x04
#define | IOE_IT_EXTI_IRQn EXTI15_10_IRQn
#define | IOE_IT_EXTI_LINE EXTI_Line14
#define | IOE_IT_EXTI_PIN_SOURCE GPIO_PinSource14
#define | IOE_IT_EXTI_PORT_SOURCE GPIO_PortSourceGPIOB
#define | IOE_IT_GPIO_CLK RCC_APB2Periph_GPIOB
#define | IOE_IT_GPIO_PORT GPIOB
#define | IOE_IT_PIN GPIO_Pin_14
IO Expander Interrupt line on EXTI.
#define | IOE_ITSRC_INMEMS 0x02
#define | IOE_ITSRC_JOYSTICK 0x04
#define | IOE_ITSRC_TEMPSENS 0x08
#define | IOE_ITSRC_TSC 0x01
Interrupt source configuration definitons.
#define | IOE_JOY_IT (uint8_t)(IO_IT_3 | IO_IT_4 | IO_IT_5 | IO_IT_6 | IO_IT_7)
#define | IOE_REG_ADC_CAPT 0x22
#define | IOE_REG_ADC_CTRL1 0x20
#define | IOE_REG_ADC_CTRL2 0x21
#define | IOE_REG_ADC_DATA_CH0 0x30
#define | IOE_REG_ADC_DATA_CH1 0x32
#define | IOE_REG_ADC_DATA_CH2 0x34
#define | IOE_REG_ADC_DATA_CH3 0x36
#define | IOE_REG_ADC_DATA_CH4 0x38
#define | IOE_REG_ADC_DATA_CH5 0x3A
#define | IOE_REG_ADC_DATA_CH6 0x3B
#define | IOE_REG_ADC_DATA_CH7 0x3C
#define | IOE_REG_ADC_INT_EN 0x0E
ADC Registers.
#define | IOE_REG_ADC_INT_STA 0x0F
#define | IOE_REG_CHP_ID 0x00
Identification registers.
#define | IOE_REG_FIFO_SIZE 0x4C
#define | IOE_REG_FIFO_STA 0x4B
#define | IOE_REG_FIFO_TH 0x4A
#define | IOE_REG_GPIO_AF 0x17
#define | IOE_REG_GPIO_CLR_PIN 0x11
#define | IOE_REG_GPIO_DIR 0x13
#define | IOE_REG_GPIO_ED 0x14
#define | IOE_REG_GPIO_FE 0x16
#define | IOE_REG_GPIO_INT_EN 0x0C
#define | IOE_REG_GPIO_INT_STA 0x0D
#define | IOE_REG_GPIO_MP_STA 0x12
#define | IOE_REG_GPIO_RE 0x15
#define | IOE_REG_GPIO_SET_PIN 0x10
GPIO Registers.
#define | IOE_REG_ID_VER 0x02
#define | IOE_REG_INT_CTRL 0x09
Interrupt Control register.
#define | IOE_REG_INT_EN 0x0A
#define | IOE_REG_INT_STA 0x0B
#define | IOE_REG_SPI_CFG 0x08
#define | IOE_REG_SYS_CTRL1 0x03
General Control Registers.
#define | IOE_REG_SYS_CTRL2 0x04
#define | IOE_REG_TEMP_CTRL 0x60
Temperature Sensor registers.
#define | IOE_REG_TEMP_DATA 0x61
#define | IOE_REG_TEMP_TH 0x62
#define | IOE_REG_TSC_CFG 0x41
#define | IOE_REG_TSC_CTRL 0x40
TouchScreen Registers.
#define | IOE_REG_TSC_DATA 0x57
#define | IOE_REG_TSC_DATA_X 0x4D
#define | IOE_REG_TSC_DATA_XYZ 0x52
#define | IOE_REG_TSC_DATA_Y 0x4F
#define | IOE_REG_TSC_DATA_Z 0x51
#define | IOE_REG_TSC_FRACT_XYZ 0x56
#define | IOE_REG_TSC_I_DRIVE 0x58
#define | IOE_REG_TSC_SHIELD 0x59
#define | IOE_REG_WDM_BL_X 0x46
#define | IOE_REG_WDM_BL_Y 0x48
#define | IOE_REG_WDM_TR_X 0x42
#define | IOE_REG_WDM_TR_Y 0x44
#define | IOE_TEMPSENS_FCT 0x08
#define | IOE_TS_FCT 0x02
#define | IOE_TS_IT (uint8_t)(IO_IT_0 | IO_IT_1 | IO_IT_2)
#define | JOY_IO_DOWN IO_Pin_6
#define | JOY_IO_LEFT IO_Pin_5
#define | JOY_IO_NONE JOY_IO_PINS
#define | JOY_IO_PINS (uint32_t)(IO_Pin_3 | IO_Pin_4 | IO_Pin_5 | IO_Pin_6 | IO_Pin_7)
#define | JOY_IO_RIGHT IO_Pin_4
#define | JOY_IO_SEL IO_Pin_7
JOYSTICK Pins definition.
#define | JOY_IO_UP IO_Pin_3
#define | MEMS_INT1_PIN IO_Pin_3 /* IO_Exapnader_1 */
#define | MEMS_INT2_PIN IO_Pin_2 /* IO_Exapnader_1 */
#define | MII_INT_PIN IO_Pin_0 /* IO_Exapnader_2 */
#define | Polarity_High 0x04
#define | Polarity_Low 0x00
Interrupt Line output parameters.
#define | STMPE811_ID 0x0811
#define | TOUCH_IO_ALL (uint32_t)(IO_Pin_1 | IO_Pin_2 | IO_Pin_3 | IO_Pin_4)
#define | TOUCH_XD IO_Pin_2 /* IO_Exapnader_1 */
#define | TOUCH_XU IO_Pin_4 /* IO_Exapnader_1 */
#define | TOUCH_YD IO_Pin_1 /* IO_Exapnader_1 */
Touch Screen Pins definition.
#define | TOUCH_YU IO_Pin_3 /* IO_Exapnader_1 */
#define | Type_Edge 0x02
#define | Type_Level 0x00
#define | VBAT_DIV_PIN IO_Pin_0 /* IO_Exapnader_1 */

Define Documentation

#define _delay_ delay

Uncomment the line below to enable verfying each written byte in write operation.

The I2C_WriteDeviceRegister() function will then compare the written and read data and return error status if a mismatch occurs. Uncomment the line below if you want to use user defined Delay function (for precise timing), otherwise default _delay_ function defined within this driver is used (less precise timing). Uncomment the line below if you want to use user timeout callback. Function prototypes is declared in this file but function body may be implemented into user application.

Definition at line 160 of file stm3210c_eval_ioe.h.

#define ALL_IT 0xFF

Definition at line 404 of file stm3210c_eval_ioe.h.

#define AUDIO_RESET_PIN IO_Pin_2 /* IO_Exapnader_2 */

Eval Board IO Pins definition.

Definition at line 205 of file stm3210c_eval_ioe.h.

Referenced by IOE_Config().

#define Direction_IN 0x00

IO Pin directions.

Definition at line 382 of file stm3210c_eval_ioe.h.

#define Direction_OUT 0x01

Definition at line 383 of file stm3210c_eval_ioe.h.

#define EDGE_FALLING 0x01

Edge detection value.

Definition at line 412 of file stm3210c_eval_ioe.h.

#define EDGE_RISING 0x02

Definition at line 413 of file stm3210c_eval_ioe.h.

#define IO1_IN_ALL_PINS (uint32_t)(MEMS_INT1_PIN | MEMS_INT2_PIN)

Eval Board both IO Exapanders Pins definition.

Definition at line 215 of file stm3210c_eval_ioe.h.

#define IO1_OUT_ALL_PINS (uint32_t)(VBAT_DIV_PIN)

Definition at line 217 of file stm3210c_eval_ioe.h.

#define IO2_IN_ALL_PINS (uint32_t)(JOY_IO_PINS)

Definition at line 216 of file stm3210c_eval_ioe.h.

Referenced by IOE_ReadIOPin().

#define IO2_OUT_ALL_PINS (uint32_t)(AUDIO_RESET_PIN | MII_INT_PIN)

Definition at line 218 of file stm3210c_eval_ioe.h.

Referenced by IOE_WriteIOPin().

#define IO_IT_0 0x01

IO Interrupts.

Definition at line 396 of file stm3210c_eval_ioe.h.

#define IO_IT_1 0x02

Definition at line 397 of file stm3210c_eval_ioe.h.

#define IO_IT_2 0x04

Definition at line 398 of file stm3210c_eval_ioe.h.

#define IO_IT_3 0x08

Definition at line 399 of file stm3210c_eval_ioe.h.

#define IO_IT_4 0x10

Definition at line 400 of file stm3210c_eval_ioe.h.

#define IO_IT_5 0x20

Definition at line 401 of file stm3210c_eval_ioe.h.

#define IO_IT_6 0x40

Definition at line 402 of file stm3210c_eval_ioe.h.

#define IO_IT_7 0x80

Definition at line 403 of file stm3210c_eval_ioe.h.

#define IO_Pin_0 0x01

IO Pins.

Definition at line 369 of file stm3210c_eval_ioe.h.

#define IO_Pin_1 0x02

Definition at line 370 of file stm3210c_eval_ioe.h.

#define IO_Pin_2 0x04

Definition at line 371 of file stm3210c_eval_ioe.h.

#define IO_Pin_3 0x08

Definition at line 372 of file stm3210c_eval_ioe.h.

#define IO_Pin_4 0x10

Definition at line 373 of file stm3210c_eval_ioe.h.

#define IO_Pin_5 0x20

Definition at line 374 of file stm3210c_eval_ioe.h.

#define IO_Pin_6 0x40

Definition at line 375 of file stm3210c_eval_ioe.h.

#define IO_Pin_7 0x80

Definition at line 376 of file stm3210c_eval_ioe.h.

#define IO_Pin_ALL 0xFF

Definition at line 377 of file stm3210c_eval_ioe.h.

#define IOE_1_ADDR 0x82

The 7 bits IO Expanders adresses and chip IDs.

Definition at line 223 of file stm3210c_eval_ioe.h.

#define IOE_2_ADDR 0x88

Definition at line 224 of file stm3210c_eval_ioe.h.

Referenced by EXTI15_10_IRQHandler(), IOE_ClearIOITPending(), IOE_Config(), IOE_ITConfig(), IOE_ITOutConfig(), IOE_JoyStickGetState(), IOE_ReadIOPin(), IOE_TempSens_Config(), IOE_TempSens_GetData(), and IOE_WriteIOPin().

#define IOE_ADC_FCT 0x01

IO Expander Functionalities definitions.

Definition at line 234 of file stm3210c_eval_ioe.h.

#define IOE_DMA DMA1

IOE DMA definitions.

Definition at line 183 of file stm3210c_eval_ioe.h.

#define IOE_DMA_CLK RCC_AHBPeriph_DMA1

Definition at line 184 of file stm3210c_eval_ioe.h.

#define IOE_DMA_RX_CHANNEL DMA1_Channel7

Definition at line 186 of file stm3210c_eval_ioe.h.

#define IOE_DMA_RX_TCFLAG DMA1_FLAG_TC7

Definition at line 188 of file stm3210c_eval_ioe.h.

#define IOE_DMA_TX_CHANNEL DMA1_Channel6

Definition at line 185 of file stm3210c_eval_ioe.h.

#define IOE_DMA_TX_TCFLAG DMA1_FLAG_TC6

Definition at line 187 of file stm3210c_eval_ioe.h.

#define IOE_GIT_ADC 0x40

Definition at line 251 of file stm3210c_eval_ioe.h.

#define IOE_GIT_EN 0x01

Global interrupt Enable bit.

Definition at line 418 of file stm3210c_eval_ioe.h.

#define IOE_GIT_FE 0x10

Definition at line 253 of file stm3210c_eval_ioe.h.

#define IOE_GIT_FF 0x08

Definition at line 254 of file stm3210c_eval_ioe.h.

#define IOE_GIT_FOV 0x04

Definition at line 255 of file stm3210c_eval_ioe.h.

#define IOE_GIT_FTH 0x02

Definition at line 256 of file stm3210c_eval_ioe.h.

#define IOE_GIT_GPIO 0x80

Glaobal Interrupts definitions.

Definition at line 250 of file stm3210c_eval_ioe.h.

#define IOE_GIT_TEMP 0x20

Definition at line 252 of file stm3210c_eval_ioe.h.

#define IOE_GIT_TOUCH 0x01

Definition at line 257 of file stm3210c_eval_ioe.h.

#define IOE_I2C I2C1

I2C port definitions.

Definition at line 169 of file stm3210c_eval_ioe.h.

#define IOE_I2C_CLK RCC_APB1Periph_I2C1

Definition at line 170 of file stm3210c_eval_ioe.h.

#define IOE_I2C_DR ((uint32_t)0x40005410)

Definition at line 177 of file stm3210c_eval_ioe.h.

#define IOE_I2C_SCL_GPIO_CLK RCC_APB2Periph_GPIOB

Definition at line 173 of file stm3210c_eval_ioe.h.

#define IOE_I2C_SCL_GPIO_PORT GPIOB

Definition at line 172 of file stm3210c_eval_ioe.h.

#define IOE_I2C_SCL_PIN GPIO_Pin_6

Definition at line 171 of file stm3210c_eval_ioe.h.

#define IOE_I2C_SDA_GPIO_CLK RCC_APB2Periph_GPIOB

Definition at line 176 of file stm3210c_eval_ioe.h.

#define IOE_I2C_SDA_GPIO_PORT GPIOB

Definition at line 175 of file stm3210c_eval_ioe.h.

#define IOE_I2C_SDA_PIN GPIO_Pin_7

Definition at line 174 of file stm3210c_eval_ioe.h.

#define IOE_I2C_SPEED 300000

Definition at line 178 of file stm3210c_eval_ioe.h.

#define IOE_INMEMS_IT (uint8_t)(IO_IT_2 | IO_IT_3)

Definition at line 407 of file stm3210c_eval_ioe.h.

Referenced by IOE_ITConfig().

#define IOE_IO_FCT 0x04

Definition at line 236 of file stm3210c_eval_ioe.h.

#define IOE_IT_EXTI_IRQn EXTI15_10_IRQn

Definition at line 200 of file stm3210c_eval_ioe.h.

#define IOE_IT_EXTI_LINE EXTI_Line14

Definition at line 199 of file stm3210c_eval_ioe.h.

#define IOE_IT_EXTI_PIN_SOURCE GPIO_PinSource14

Definition at line 198 of file stm3210c_eval_ioe.h.

#define IOE_IT_EXTI_PORT_SOURCE GPIO_PortSourceGPIOB

Definition at line 197 of file stm3210c_eval_ioe.h.

#define IOE_IT_GPIO_CLK RCC_APB2Periph_GPIOB

Definition at line 196 of file stm3210c_eval_ioe.h.

#define IOE_IT_GPIO_PORT GPIOB

Definition at line 195 of file stm3210c_eval_ioe.h.

#define IOE_IT_PIN GPIO_Pin_14

IO Expander Interrupt line on EXTI.

Definition at line 194 of file stm3210c_eval_ioe.h.

#define IOE_ITSRC_INMEMS 0x02

Definition at line 243 of file stm3210c_eval_ioe.h.

Referenced by IOE_ITConfig().

#define IOE_ITSRC_JOYSTICK 0x04

Definition at line 244 of file stm3210c_eval_ioe.h.

Referenced by IOE_ITConfig(), and main().

#define IOE_ITSRC_TEMPSENS 0x08

Definition at line 245 of file stm3210c_eval_ioe.h.

#define IOE_ITSRC_TSC 0x01

Interrupt source configuration definitons.

Definition at line 242 of file stm3210c_eval_ioe.h.

#define IOE_JOY_IT (uint8_t)(IO_IT_3 | IO_IT_4 | IO_IT_5 | IO_IT_6 | IO_IT_7)

Definition at line 405 of file stm3210c_eval_ioe.h.

Referenced by EXTI15_10_IRQHandler(), and IOE_ITConfig().

#define IOE_REG_ADC_CAPT 0x22

Definition at line 304 of file stm3210c_eval_ioe.h.

#define IOE_REG_ADC_CTRL1 0x20

Definition at line 302 of file stm3210c_eval_ioe.h.

#define IOE_REG_ADC_CTRL2 0x21

Definition at line 303 of file stm3210c_eval_ioe.h.

#define IOE_REG_ADC_DATA_CH0 0x30

Definition at line 305 of file stm3210c_eval_ioe.h.

#define IOE_REG_ADC_DATA_CH1 0x32

Definition at line 306 of file stm3210c_eval_ioe.h.

#define IOE_REG_ADC_DATA_CH2 0x34

Definition at line 307 of file stm3210c_eval_ioe.h.

#define IOE_REG_ADC_DATA_CH3 0x36

Definition at line 308 of file stm3210c_eval_ioe.h.

#define IOE_REG_ADC_DATA_CH4 0x38

Definition at line 309 of file stm3210c_eval_ioe.h.

#define IOE_REG_ADC_DATA_CH5 0x3A

Definition at line 310 of file stm3210c_eval_ioe.h.

#define IOE_REG_ADC_DATA_CH6 0x3B

Definition at line 311 of file stm3210c_eval_ioe.h.

#define IOE_REG_ADC_DATA_CH7 0x3C

Definition at line 312 of file stm3210c_eval_ioe.h.

#define IOE_REG_ADC_INT_EN 0x0E

ADC Registers.

Definition at line 300 of file stm3210c_eval_ioe.h.

#define IOE_REG_ADC_INT_STA 0x0F

Definition at line 301 of file stm3210c_eval_ioe.h.

#define IOE_REG_CHP_ID 0x00

Identification registers.

Definition at line 266 of file stm3210c_eval_ioe.h.

#define IOE_REG_FIFO_SIZE 0x4C

Definition at line 325 of file stm3210c_eval_ioe.h.

#define IOE_REG_FIFO_STA 0x4B

Definition at line 324 of file stm3210c_eval_ioe.h.

#define IOE_REG_FIFO_TH 0x4A

Definition at line 323 of file stm3210c_eval_ioe.h.

#define IOE_REG_GPIO_AF 0x17

Definition at line 295 of file stm3210c_eval_ioe.h.

#define IOE_REG_GPIO_CLR_PIN 0x11

Definition at line 289 of file stm3210c_eval_ioe.h.

#define IOE_REG_GPIO_DIR 0x13

Definition at line 291 of file stm3210c_eval_ioe.h.

#define IOE_REG_GPIO_ED 0x14

Definition at line 292 of file stm3210c_eval_ioe.h.

#define IOE_REG_GPIO_FE 0x16

Definition at line 294 of file stm3210c_eval_ioe.h.

#define IOE_REG_GPIO_INT_EN 0x0C

Definition at line 282 of file stm3210c_eval_ioe.h.

#define IOE_REG_GPIO_INT_STA 0x0D

Definition at line 283 of file stm3210c_eval_ioe.h.

#define IOE_REG_GPIO_MP_STA 0x12

Definition at line 290 of file stm3210c_eval_ioe.h.

#define IOE_REG_GPIO_RE 0x15

Definition at line 293 of file stm3210c_eval_ioe.h.

#define IOE_REG_GPIO_SET_PIN 0x10

GPIO Registers.

Definition at line 288 of file stm3210c_eval_ioe.h.

#define IOE_REG_ID_VER 0x02

Definition at line 267 of file stm3210c_eval_ioe.h.

#define IOE_REG_INT_CTRL 0x09

Interrupt Control register.

Definition at line 279 of file stm3210c_eval_ioe.h.

#define IOE_REG_INT_EN 0x0A

Definition at line 280 of file stm3210c_eval_ioe.h.

#define IOE_REG_INT_STA 0x0B

Definition at line 281 of file stm3210c_eval_ioe.h.

#define IOE_REG_SPI_CFG 0x08

Definition at line 274 of file stm3210c_eval_ioe.h.

#define IOE_REG_SYS_CTRL1 0x03

General Control Registers.

Definition at line 272 of file stm3210c_eval_ioe.h.

#define IOE_REG_SYS_CTRL2 0x04

Definition at line 273 of file stm3210c_eval_ioe.h.

#define IOE_REG_TEMP_CTRL 0x60

Temperature Sensor registers.

Definition at line 338 of file stm3210c_eval_ioe.h.

#define IOE_REG_TEMP_DATA 0x61

Definition at line 339 of file stm3210c_eval_ioe.h.

#define IOE_REG_TEMP_TH 0x62

Definition at line 340 of file stm3210c_eval_ioe.h.

#define IOE_REG_TSC_CFG 0x41

Definition at line 318 of file stm3210c_eval_ioe.h.

#define IOE_REG_TSC_CTRL 0x40

TouchScreen Registers.

Definition at line 317 of file stm3210c_eval_ioe.h.

#define IOE_REG_TSC_DATA 0x57

Definition at line 331 of file stm3210c_eval_ioe.h.

#define IOE_REG_TSC_DATA_X 0x4D

Definition at line 326 of file stm3210c_eval_ioe.h.

#define IOE_REG_TSC_DATA_XYZ 0x52

Definition at line 329 of file stm3210c_eval_ioe.h.

#define IOE_REG_TSC_DATA_Y 0x4F

Definition at line 327 of file stm3210c_eval_ioe.h.

#define IOE_REG_TSC_DATA_Z 0x51

Definition at line 328 of file stm3210c_eval_ioe.h.

#define IOE_REG_TSC_FRACT_XYZ 0x56

Definition at line 330 of file stm3210c_eval_ioe.h.

#define IOE_REG_TSC_I_DRIVE 0x58

Definition at line 332 of file stm3210c_eval_ioe.h.

#define IOE_REG_TSC_SHIELD 0x59

Definition at line 333 of file stm3210c_eval_ioe.h.

#define IOE_REG_WDM_BL_X 0x46

Definition at line 321 of file stm3210c_eval_ioe.h.

#define IOE_REG_WDM_BL_Y 0x48

Definition at line 322 of file stm3210c_eval_ioe.h.

#define IOE_REG_WDM_TR_X 0x42

Definition at line 319 of file stm3210c_eval_ioe.h.

#define IOE_REG_WDM_TR_Y 0x44

Definition at line 320 of file stm3210c_eval_ioe.h.

#define IOE_TEMPSENS_FCT 0x08

Definition at line 237 of file stm3210c_eval_ioe.h.

#define IOE_TS_FCT 0x02

Definition at line 235 of file stm3210c_eval_ioe.h.

#define IOE_TS_IT (uint8_t)(IO_IT_0 | IO_IT_1 | IO_IT_2)

Definition at line 406 of file stm3210c_eval_ioe.h.

#define JOY_IO_DOWN IO_Pin_6

Definition at line 359 of file stm3210c_eval_ioe.h.

Referenced by IOE_JoyStickGetState().

#define JOY_IO_LEFT IO_Pin_5

Definition at line 360 of file stm3210c_eval_ioe.h.

Referenced by IOE_JoyStickGetState().

#define JOY_IO_NONE JOY_IO_PINS

Definition at line 363 of file stm3210c_eval_ioe.h.

Referenced by IOE_JoyStickGetState().

#define JOY_IO_PINS (uint32_t)(IO_Pin_3 | IO_Pin_4 | IO_Pin_5 | IO_Pin_6 | IO_Pin_7)

Definition at line 364 of file stm3210c_eval_ioe.h.

Referenced by IOE_Config().

#define JOY_IO_RIGHT IO_Pin_4

Definition at line 361 of file stm3210c_eval_ioe.h.

Referenced by IOE_JoyStickGetState().

#define JOY_IO_SEL IO_Pin_7

JOYSTICK Pins definition.

Definition at line 358 of file stm3210c_eval_ioe.h.

Referenced by IOE_JoyStickGetState().

#define JOY_IO_UP IO_Pin_3

Definition at line 362 of file stm3210c_eval_ioe.h.

Referenced by IOE_JoyStickGetState().

#define MEMS_INT1_PIN IO_Pin_3 /* IO_Exapnader_1 */

Definition at line 208 of file stm3210c_eval_ioe.h.

Referenced by IOE_Config().

#define MEMS_INT2_PIN IO_Pin_2 /* IO_Exapnader_1 */

Definition at line 209 of file stm3210c_eval_ioe.h.

Referenced by IOE_Config().

#define MII_INT_PIN IO_Pin_0 /* IO_Exapnader_2 */

Definition at line 206 of file stm3210c_eval_ioe.h.

Referenced by IOE_Config().

#define Polarity_High 0x04

Definition at line 389 of file stm3210c_eval_ioe.h.

#define Polarity_Low 0x00

Interrupt Line output parameters.

Definition at line 388 of file stm3210c_eval_ioe.h.

#define STMPE811_ID 0x0811

Definition at line 225 of file stm3210c_eval_ioe.h.

#define TOUCH_IO_ALL (uint32_t)(IO_Pin_1 | IO_Pin_2 | IO_Pin_3 | IO_Pin_4)

Definition at line 353 of file stm3210c_eval_ioe.h.

#define TOUCH_XD IO_Pin_2 /* IO_Exapnader_1 */

Definition at line 350 of file stm3210c_eval_ioe.h.

#define TOUCH_XU IO_Pin_4 /* IO_Exapnader_1 */

Definition at line 352 of file stm3210c_eval_ioe.h.

#define TOUCH_YD IO_Pin_1 /* IO_Exapnader_1 */

Touch Screen Pins definition.

Definition at line 349 of file stm3210c_eval_ioe.h.

#define TOUCH_YU IO_Pin_3 /* IO_Exapnader_1 */

Definition at line 351 of file stm3210c_eval_ioe.h.

#define Type_Edge 0x02

Definition at line 391 of file stm3210c_eval_ioe.h.

#define Type_Level 0x00

Definition at line 390 of file stm3210c_eval_ioe.h.

#define VBAT_DIV_PIN IO_Pin_0 /* IO_Exapnader_1 */

Definition at line 207 of file stm3210c_eval_ioe.h.

Referenced by IOE_Config().


STM32F10x Standard Peripherals Firmware Library: STM3210C_EVAL_IOE_Exported_Macros

STM3210C_EVAL_IOE_Exported_Macros

STM3210C_EVAL_IOE


STM32F10x Standard Peripherals Firmware Library: STM3210C_EVAL_IOE_Exported_Functions

Defines | Functions

STM3210C_EVAL_IOE_Exported_Functions

STM3210C_EVAL_IOE

Defines

#define | IOE_TimeoutUserCallback() IOE_TIMEOUT
Timeout user callback function.

Functions

uint16_t | I2C_ReadDataBuffer (uint8_t DeviceAddr, uint32_t RegisterAddr)
Reads a buffer of 2 bytes from the device registers.
uint8_t | I2C_ReadDeviceRegister (uint8_t DeviceAddr, uint8_t RegisterAddr)
Reads a register of the device through I2C.
uint8_t | I2C_WriteDeviceRegister (uint8_t DeviceAddr, uint8_t RegisterAddr, uint8_t RegisterValue)
Writes a value in a register of the device through I2C.
uint8_t | IOE_ClearGITPending (uint8_t DeviceAddr, uint8_t IO_IT)
Clears the selected Global interrupt pending bit(s)
uint8_t | IOE_ClearIOITPending (uint8_t DeviceAddr, uint8_t IO_IT)
Clears the selected IO interrupt pending bit(s).
uint8_t | IOE_Config (void)
Configuration and initialization functions.
uint8_t | IOE_FnctCmd (uint8_t DeviceAddr, uint8_t Fct, FunctionalState NewState)
Configures the selcted IO Expander functionalities.
FlagStatus | IOE_GetGITStatus (uint8_t DeviceAddr, uint8_t Global_IT)
Interrupts Mangement functions.
FlagStatus | IOE_GetIOITStatus (uint8_t DeviceAddr, uint8_t IO_IT)
Checks the status of the selected IO interrupt pending bit.
uint8_t | IOE_GITCmd (uint8_t DeviceAddr, FunctionalState NewState)
Enables or disables the Global interrupt.
uint8_t | IOE_GITConfig (uint8_t DeviceAddr, uint8_t Global_IT, FunctionalState NewState)
Configures the selected source to generate or not a global interrupt.
uint8_t | IOE_IOAFConfig (uint8_t DeviceAddr, uint8_t IO_Pin, FunctionalState NewState)
Configures the selected pin to be in Alternate function or not.
uint8_t | IOE_IOEdgeConfig (uint8_t DeviceAddr, uint8_t IO_Pin, uint8_t Edge)
Configures the Edge for which a transition is detectable for the the selected pin.
uint8_t | IOE_IOITConfig (uint8_t DeviceAddr, uint8_t IO_IT, FunctionalState NewState)
Configures the selected pins to generate an interrupt or not.
uint8_t | IOE_IOPinConfig (uint8_t DeviceAddr, uint8_t IO_Pin, uint8_t Direction)
Configures the selected pin direction (to be an input or an output)
uint8_t | IOE_IsOperational (uint8_t DeviceAddr)
IO-Expander Control functions.
uint8_t | IOE_ITConfig (uint32_t IOE_ITSRC_Source)
Configures The selected interrupts on the IO Expanders.
uint8_t | IOE_ITOutConfig (uint8_t Polarity, uint8_t Type)
Configures the Interrupt line active state and format (level/edge)
JOYState_TypeDef | IOE_JoyStickGetState (void)
Returns the current Joystick status.
uint16_t | IOE_ReadID (uint8_t DeviceAddr)
Reads the selected device's ID.
uint8_t | IOE_ReadIOPin (uint32_t IO_Pin)
Returns the status of the selected input IO pin.
uint8_t | IOE_Reset (uint8_t DeviceAddr)
Resets the IO Expander by Software (SYS_CTRL1, RESET bit).
uint8_t | IOE_TempSens_Config (void)
Configures and enables the Temperature sensor module.
uint32_t | IOE_TempSens_GetData (void)
Temperature Sensor functions.
uint8_t | IOE_TS_Config (void)
Low Layer functions.
TS_STATE * | IOE_TS_GetState (void)
Touch Screen controller functions.
uint8_t | IOE_WriteIOPin (uint8_t IO_Pin, IOE_BitValue_TypeDef BitVal)
IO pins control functions.

Define Documentation

#define IOE_TimeoutUserCallback ( ) IOE_TIMEOUT

Timeout user callback function.

This function is called when a timeout condition occurs during communication with IO Expander. Only protoype of this function is decalred in IO Expander driver. Its implementation may be done into user application. This function may typically stop current operations and reset the I2C peripheral and IO Expander. To enable this function use uncomment the define USE_TIMEOUT_USER_CALLBACK at the top of this file.

Definition at line 457 of file stm3210c_eval_ioe.h.

Function Documentation

uint16_t I2C_ReadDataBuffer | ( | uint8_t | DeviceAddr,
 |  | uint32_t | RegisterAddr
 | ) |  |

Reads a buffer of 2 bytes from the device registers.

Parameters:
DeviceAddr,: The address of the device, could be : IOE_1_ADDR.
RegisterAddr,: The target register adress (between 00x and 0x24)
Return values:
A pointer to the buffer containing the two returned bytes (in halfword).
Parameters:
DeviceAddr,: The address of the device, could be : IOE_1_ADDR or IOE_2_ADDR.
RegisterAddr,: The target register adress (between 00x and 0x24)
Return values:
A pointer to the buffer containing the two returned bytes (in halfword).

Definition at line 1061 of file stm32100e_eval_ioe.c.

References DISABLE, DMA_ClearFlag(), DMA_Cmd(), DMA_GetFlagStatus(), ENABLE, I2C_CheckEvent(), I2C_Direction_Receiver, I2C_Direction_Transmitter, I2C_DMACmd(), I2C_DMALastTransferCmd(), I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED, I2C_FLAG_BTF, I2C_FLAG_SB, I2C_FLAG_TXE, I2C_GenerateSTART(), I2C_GenerateSTOP(), I2C_GetFlagStatus(), I2C_Send7bitAddress(), I2C_SendData(), IOE_DMA_Config(), IOE_DMA_RX, IOE_DMA_RX_CHANNEL, IOE_DMA_RX_TCFLAG, IOE_I2C, IOE_TimeOut, IOE_TimeoutUserCallback, and TIMEOUT_MAX.

Referenced by IOE_TS_Read_X(), IOE_TS_Read_Y(), and IOE_TS_Read_Z().

uint8_t I2C_ReadDeviceRegister | ( | uint8_t | DeviceAddr,
 |  | uint8_t | RegisterAddr
 | ) |  |

Reads a register of the device through I2C.

Parameters:
DeviceAddr,: The address of the device, could be : IOE_1_ADDR.
RegisterAddr,: The target register adress (between 00x and 0x24)
Return values:
The value of the read register (0xAA if Timout occured)
Parameters:
DeviceAddr,: The address of the device, could be : IOE_1_ADDR or IOE_2_ADDR.
RegisterAddr,: The target register adress (between 00x and 0x24)
Return values:
The value of the read register (0xAA if Timout occured)

Definition at line 965 of file stm32100e_eval_ioe.c.

References DISABLE, DMA_ClearFlag(), DMA_Cmd(), DMA_GetFlagStatus(), ENABLE, I2C_CheckEvent(), I2C_Direction_Receiver, I2C_Direction_Transmitter, I2C_DMACmd(), I2C_DMALastTransferCmd(), I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED, I2C_FLAG_BTF, I2C_FLAG_SB, I2C_FLAG_TXE, I2C_GenerateSTART(), I2C_GenerateSTOP(), I2C_GetFlagStatus(), I2C_Send7bitAddress(), I2C_SendData(), IOE_DMA_Config(), IOE_DMA_RX, IOE_DMA_RX_CHANNEL, IOE_DMA_RX_TCFLAG, IOE_I2C, IOE_TimeOut, IOE_TimeoutUserCallback, and TIMEOUT_MAX.

Referenced by I2C_WriteDeviceRegister(), IOE_FnctCmd(), IOE_GetGITStatus(), IOE_GetIOITStatus(), IOE_GITCmd(), IOE_GITConfig(), IOE_IOAFConfig(), IOE_IOEdgeConfig(), IOE_IOITConfig(), IOE_IOPinConfig(), IOE_ITConfig(), IOE_ITOutConfig(), IOE_JoyStickGetState(), IOE_ReadID(), IOE_ReadIOPin(), IOE_TempSens_Config(), IOE_TempSens_GetData(), IOE_TS_Config(), and IOE_TS_GetState().

uint8_t I2C_WriteDeviceRegister | ( | uint8_t | DeviceAddr,
 |  | uint8_t | RegisterAddr,
 |  | uint8_t | RegisterValue
 | ) |  |

Writes a value in a register of the device through I2C.

Parameters:
DeviceAddr,: The address of the IOExpander, could be : IOE_1_ADDR.
RegisterAddr,: The target register adress
RegisterValue,: The target register value to be written
Return values:
IOE_OK,: if all operations are OK. Other value if error.
Parameters:
DeviceAddr,: The address of the IOExpander, could be : IOE_1_ADDR or IOE_2_ADDR.
RegisterAddr,: The target register adress
RegisterValue,: The target register value to be written
Return values:
IOE_OK,: if all operations are OK. Other value if error.

Definition at line 865 of file stm32100e_eval_ioe.c.

References DISABLE, DMA_ClearFlag(), DMA_Cmd(), DMA_GetFlagStatus(), ENABLE, I2C_CheckEvent(), I2C_Direction_Transmitter, I2C_DMACmd(), I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED, I2C_FLAG_BTF, I2C_FLAG_SB, I2C_FLAG_TXE, I2C_GenerateSTART(), I2C_GenerateSTOP(), I2C_GetFlagStatus(), I2C_ReadDeviceRegister(), I2C_Send7bitAddress(), I2C_SendData(), IOE_DMA_Config(), IOE_DMA_TX, IOE_DMA_TX_CHANNEL, IOE_DMA_TX_TCFLAG, IOE_FAILURE, IOE_I2C, IOE_TimeOut, IOE_TimeoutUserCallback, RESET, and TIMEOUT_MAX.

Referenced by IOE_ClearGITPending(), IOE_ClearIOITPending(), IOE_FnctCmd(), IOE_GITCmd(), IOE_GITConfig(), IOE_IOAFConfig(), IOE_IOEdgeConfig(), IOE_IOITConfig(), IOE_IOPinConfig(), IOE_ITOutConfig(), IOE_Reset(), IOE_TempSens_Config(), IOE_TempSens_GetData(), IOE_TS_Config(), IOE_TS_GetState(), and IOE_WriteIOPin().

uint8_t IOE_ClearGITPending | ( | uint8_t | DeviceAddr,
 |  | uint8_t | Global_IT
 | ) |  |

Clears the selected Global interrupt pending bit(s)

Parameters:
DeviceAddr,: The address of the IOExpander, could be : IOE_1_ADDR.
Global_IT,: the Global interrupt to be cleared, could be any combination of the following values:

  • Global_IT_GPIO : All IOs interrupt
  • Global_IT_ADC : ADC interrupt
  • Global_IT_TEMP : Temperature Sensor interrupts
  • Global_IT_FE : Touch Screen Controller FIFO Error interrupt
  • Global_IT_FF : Touch Screen Controller FIFO Full interrupt
  • Global_IT_FOV : Touch Screen Controller FIFO Overrun interrupt
  • Global_IT_FTH : Touch Screen Controller FIFO Threshold interrupt
  • Global_IT_TOUCH : Touch Screen Controller Touch Detected interrupt
Return values:
IOE_OK,: if all initializations are OK. Other value if error.
Parameters:
DeviceAddr,: The address of the IOExpander, could be : IOE_1_ADDR or IOE_2_ADDR.
Global_IT,: the Global interrupt to be cleared, could be any combination of the following values:

  • Global_IT_GPIO : All IOs interrupt
  • Global_IT_ADC : ADC interrupt
  • Global_IT_TEMP : Temperature Sensor interrupts
  • Global_IT_FE : Touch Screen Controller FIFO Error interrupt
  • Global_IT_FF : Touch Screen Controller FIFO Full interrupt
  • Global_IT_FOV : Touch Screen Controller FIFO Overrun interrupt
  • Global_IT_FTH : Touch Screen Controller FIFO Threshold interrupt
  • Global_IT_TOUCH : Touch Screen Controller Touch Detected interrupt
Return values:
IOE_OK,: if all initializations are OK. Other value if error.

Definition at line 374 of file stm32100e_eval_ioe.c.

References I2C_WriteDeviceRegister(), IOE_OK, and IOE_REG_INT_STA.

Referenced by EXTI15_10_IRQHandler().

uint8_t IOE_ClearIOITPending | ( | uint8_t | DeviceAddr,
 |  | uint8_t | IO_IT
 | ) |  |

Clears the selected IO interrupt pending bit(s).

Parameters:
DeviceAddr,: The address of the IOExpander, could be : IOE_1_ADDR.
IO_IT,: the IO interrupt to be checked could be IO_ITx Where x can be from 0 to 7.
Return values:
IOE_OK,: if all initializations are OK. Other value if error.
Parameters:
DeviceAddr,: The address of the IOExpander, could be : IOE_1_ADDR or IOE_2_ADDR.
IO_IT,: the IO interrupt to be checked could be IO_ITx Where x can be from 0 to 7.
Return values:
IOE_OK,: if all initializations are OK. Other value if error.

Definition at line 414 of file stm32100e_eval_ioe.c.

References I2C_WriteDeviceRegister(), IOE_2_ADDR, IOE_OK, IOE_REG_GPIO_ED, IOE_REG_GPIO_FE, IOE_REG_GPIO_INT_STA, and IOE_REG_GPIO_RE.

Referenced by EXTI15_10_IRQHandler().

uint8_t IOE_Config ( void )

Configuration and initialization functions.

Configuration and initialization functions.

Parameters:
None
Return values:
IOE_OK if all initializations done correctly. Other value if error.

Definition at line 129 of file stm32100e_eval_ioe.c.

References AUDIO_RESET_PIN, BitReset, Direction_IN, Direction_OUT, EDGE_FALLING, EDGE_RISING, ENABLE, IOE1_NOT_OPERATIONAL, IOE2_NOT_OPERATIONAL, IOE_1_ADDR, IOE_2_ADDR, IOE_ADC_FCT, IOE_FnctCmd(), IOE_GPIO_Config(), IOE_I2C_Config(), IOE_IO_FCT, IOE_IOAFConfig(), IOE_IOEdgeConfig(), IOE_IOPinConfig(), IOE_IsOperational(), IOE_OK, IOE_Reset(), IOE_TempSens_Config(), IOE_TEMPSENS_FCT, IOE_TS_Config(), IOE_TS_FCT, IOE_WriteIOPin(), JOY_IO_PINS, MEMS_INT1_PIN, MEMS_INT2_PIN, MII_INT_PIN, and VBAT_DIV_PIN.

Referenced by main().

uint8_t IOE_FnctCmd | ( | uint8_t | DeviceAddr,
 |  | uint8_t | Fct,
 |  | FunctionalState | NewState
 | ) |  |

Configures the selcted IO Expander functionalities.

Parameters:
DeviceAddr,: The address of the IOExpander, could be : IOE_1_ADDR.
Fct,: the functions to be configured. could be any combination of the following values:

  • IOE_IO_FCT : IO function
  • IOE_TS_FCT : Touch Screen function
  • IOE_ADC_FCT : ADC function
  • IOE_TEMPSENS_FCT : Tempreature Sensor function
Return values:
IOE_OK,: if all initializations are OK. Other value if error.
Parameters:
DeviceAddr,: The address of the IOExpander, could be : IOE_1_ADDR or IOE_2_ADDR.
IOE_TEMPSENS_FCT,: the functions to be configured. could be any combination of the following values:

  • IOE_IO_FCT : IO function
  • IOE_TS_FCT : Touch Screen function
  • IOE_ADC_FCT : ADC function
  • IOE_TEMPSENS_FCT : Tempreature Sensor function
Return values:
IOE_OK,: if all initializations are OK. Other value if error.

Definition at line 507 of file stm32100e_eval_ioe.c.

References DISABLE, I2C_ReadDeviceRegister(), I2C_WriteDeviceRegister(), IOE_OK, and IOE_REG_SYS_CTRL2.

Referenced by IOE_Config().

FlagStatus IOE_GetGITStatus | ( | uint8_t | DeviceAddr,
 |  | uint8_t | Global_IT
 | ) |  |

Interrupts Mangement functions.

Interrupts Mangement functions.

Parameters:
DeviceAddr,: The address of the IOExpander, could be : IOE_1_ADDR.
Global_IT,: the Global interrupt source to be checked, could be:

  • Global_IT_GPIO : All IOs interrupt
  • Global_IT_ADC : ADC interrupt
  • Global_IT_TEMP : Temperature Sensor interrupts
  • Global_IT_FE : Touch Screen Controller FIFO Error interrupt
  • Global_IT_FF : Touch Screen Controller FIFO Full interrupt
  • Global_IT_FOV : Touch Screen Controller FIFO Overrun interrupt
  • Global_IT_FTH : Touch Screen Controller FIFO Threshold interrupt
  • Global_IT_TOUCH : Touch Screen Controller Touch Detected interrupt
Return values:
Status of the checked flag. Could be SET or RESET.

Interrupts Mangement functions.

Parameters:
DeviceAddr,: The address of the IOExpander, could be : IOE_1_ADDR or IOE_2_ADDR.
Global_IT,: the Global interrupt source to be checked, could be:

  • Global_IT_GPIO : All IOs interrupt
  • Global_IT_ADC : ADC interrupt
  • Global_IT_TEMP : Temperature Sensor interrupts
  • Global_IT_FE : Touch Screen Controller FIFO Error interrupt
  • Global_IT_FF : Touch Screen Controller FIFO Full interrupt
  • Global_IT_FOV : Touch Screen Controller FIFO Overrun interrupt
  • Global_IT_FTH : Touch Screen Controller FIFO Threshold interrupt
  • Global_IT_TOUCH : Touch Screen Controller Touch Detected interrupt
Return values:
Status of the checked flag. Could be SET or RESET.

Definition at line 342 of file stm32100e_eval_ioe.c.

References I2C_ReadDeviceRegister(), IOE_REG_INT_STA, RESET, and SET.

Referenced by EXTI15_10_IRQHandler().

FlagStatus IOE_GetIOITStatus | ( | uint8_t | DeviceAddr,
 |  | uint8_t | IO_IT
 | ) |  |

Checks the status of the selected IO interrupt pending bit.

Parameters:
DeviceAddr,: The address of the IOExpander, could be : IOE_1_ADDR.
IO_IT,: the IO interrupt to be checked could be IO_ITx Where x can be from 0 to 7.
Return values:
Status of the checked flag. Could be SET or RESET.
Parameters:
DeviceAddr,: The address of the IOExpander, could be : IOE_1_ADDR or IOE_2_ADDR.
IO_IT,: the IO interrupt to be checked could be IO_ITx Where x can be from 0 to 7.
Return values:
Status of the checked flag. Could be SET or RESET.

Definition at line 390 of file stm32100e_eval_ioe.c.

References I2C_ReadDeviceRegister(), IOE_REG_GPIO_INT_STA, RESET, and SET.

uint8_t IOE_GITCmd | ( | uint8_t | DeviceAddr,
 |  | FunctionalState | NewState
 | ) |  |

Enables or disables the Global interrupt.

Parameters:
DeviceAddr,: The address of the IOExpander, could be :I OE_1_ADDR.
NewState,: could be ENABLE or DISABLE.
Return values:
IOE_OK,: if all initializations are OK. Other value if error.
Parameters:
DeviceAddr,: The address of the IOExpander, could be :I OE_1_ADDR or IOE_2_ADDR.
NewState,: could be ENABLE or DISABLE.
Return values:
IOE_OK,: if all initializations are OK. Other value if error.

Definition at line 568 of file stm32100e_eval_ioe.c.

References DISABLE, I2C_ReadDeviceRegister(), I2C_WriteDeviceRegister(), IOE_GIT_EN, IOE_OK, and IOE_REG_INT_CTRL.

Referenced by IOE_ITConfig().

uint8_t IOE_GITConfig | ( | uint8_t | DeviceAddr,
 |  | uint8_t | Global_IT,
 |  | FunctionalState | NewState
 | ) |  |

Configures the selected source to generate or not a global interrupt.

Parameters:
DeviceAddr,: The address of the IOExpander, could be : IOE_1_ADDR
Global_IT,: the interrupt source to be configured, could be:

  • Global_IT_GPIO : All IOs interrupt
  • Global_IT_ADC : ADC interrupt
  • Global_IT_TEMP : Temperature Sensor interrupts
  • Global_IT_FE : Touch Screen Controller FIFO Error interrupt
  • Global_IT_FF : Touch Screen Controller FIFO Full interrupt
  • Global_IT_FOV : Touch Screen Controller FIFO Overrun interrupt
  • Global_IT_FTH : Touch Screen Controller FIFO Threshold interrupt
  • Global_IT_TOUCH : Touch Screen Controller Touch Detected interrupt
Return values:
IOE_OK,: if all initializations are OK. Other value if error.
Parameters:
DeviceAddr,: The address of the IOExpander, could be : IOE_1_ADDR or IOE_2_ADDR.
Global_IT,: the interrupt source to be configured, could be:

  • Global_IT_GPIO : All IOs interrupt
  • Global_IT_ADC : ADC interrupt
  • Global_IT_TEMP : Temperature Sensor interrupts
  • Global_IT_FE : Touch Screen Controller FIFO Error interrupt
  • Global_IT_FF : Touch Screen Controller FIFO Full interrupt
  • Global_IT_FOV : Touch Screen Controller FIFO Overrun interrupt
  • Global_IT_FTH : Touch Screen Controller FIFO Threshold interrupt
  • Global_IT_TOUCH : Touch Screen Controller Touch Detected interrupt
Return values:
IOE_OK,: if all initializations are OK. Other value if error.

Definition at line 607 of file stm32100e_eval_ioe.c.

References DISABLE, I2C_ReadDeviceRegister(), I2C_WriteDeviceRegister(), IOE_OK, and IOE_REG_INT_EN.

Referenced by IOE_ITConfig().

uint8_t IOE_IOAFConfig | ( | uint8_t | DeviceAddr,
 |  | uint8_t | IO_Pin,
 |  | FunctionalState | NewState
 | ) |  |

Configures the selected pin to be in Alternate function or not.

Parameters:
DeviceAddr,: The address of the IOExpander, could be : IOE_1_ADDR.
IO_Pin,: IO_Pin_x, Where x can be from 0 to 7.
NewState,: State of the AF for the selected pin, could be ENABLE or DISABLE.
Return values:
IOE_OK,: if all initializations are OK. Other value if error.
Parameters:
DeviceAddr,: The address of the IOExpander, could be : IOE_1_ADDR or IOE_2_ADDR.
IO_Pin,: IO_Pin_x, Where x can be from 0 to 7.
NewState,: State of the AF for the selected pin, could be ENABLE or DISABLE.
Return values:
IOE_OK,: if all initializations are OK. Other value if error.

Definition at line 761 of file stm32100e_eval_ioe.c.

References DISABLE, I2C_ReadDeviceRegister(), I2C_WriteDeviceRegister(), IOE_OK, and IOE_REG_GPIO_AF.

Referenced by IOE_Config().

uint8_t IOE_IOEdgeConfig | ( | uint8_t | DeviceAddr,
 |  | uint8_t | IO_Pin,
 |  | uint8_t | Edge
 | ) |  |

Configures the Edge for which a transition is detectable for the the selected pin.

Parameters:
DeviceAddr,: The address of the IOExpander, could be : IOE_1_ADDR.
IO_Pin,: IO_Pin_x, Where x can be from 0 to 7.
Edge,: The edge which will be detected. This parameter can be one or a a combination of follwing values: EDGE_FALLING and EDGE_RISING .
Return values:
IOE_OK,: if all initializations are OK. Other value if error.
Parameters:
DeviceAddr,: The address of the IOExpander, could be : IOE_1_ADDR or IOE_2_ADDR.
IO_Pin,: IO_Pin_x, Where x can be from 0 to 7.
Edge,: The edge which will be detected. This parameter can be one or a a combination of follwing values: EDGE_FALLING and EDGE_RISING .
Return values:
IOE_OK,: if all initializations are OK. Other value if error.

Definition at line 795 of file stm32100e_eval_ioe.c.

References EDGE_FALLING, EDGE_RISING, I2C_ReadDeviceRegister(), I2C_WriteDeviceRegister(), IOE_OK, IOE_REG_GPIO_FE, and IOE_REG_GPIO_RE.

Referenced by IOE_Config().

uint8_t IOE_IOITConfig | ( | uint8_t | DeviceAddr,
 |  | uint8_t | IO_IT,
 |  | FunctionalState | NewState
 | ) |  |

Configures the selected pins to generate an interrupt or not.

Parameters:
DeviceAddr,: The address of the IOExpander, could be : IOE_1_ADDR.
IO_IT,: The IO interrupt to be configured. This parameter could be any combination of the following values:

  • IO_IT_x: where x can be from 0 to 7.
NewState,: could be ENABLE or DISABLE.
Return values:
IOE_OK,: if all initializations are OK. Other value if error.
Parameters:
DeviceAddr,: The address of the IOExpander, could be : IOE_1_ADDR or IOE_2_ADDR.
IO_IT,: The IO interrupt to be configured. This parameter could be any combination of the following values:

  • IO_IT_x: where x can be from 0 to 7.
NewState,: could be ENABLE or DISABLE.
Return values:
IOE_OK,: if all initializations are OK. Other value if error.

Definition at line 640 of file stm32100e_eval_ioe.c.

References DISABLE, I2C_ReadDeviceRegister(), I2C_WriteDeviceRegister(), IOE_OK, and IOE_REG_GPIO_INT_EN.

Referenced by IOE_ITConfig().

uint8_t IOE_IOPinConfig | ( | uint8_t | DeviceAddr,
 |  | uint8_t | IO_Pin,
 |  | uint8_t | Direction
 | ) |  |

Configures the selected pin direction (to be an input or an output)

Parameters:
DeviceAddr,: The address of the IOExpander, could be : IOE_1_ADDR.
IO_Pin,: IO_Pin_x: Where x can be from 0 to 7.
Direction,: could be Direction_IN or Direction_OUT.
Return values:
IOE_OK,: if all initializations are OK. Other value if error.
Parameters:
DeviceAddr,: The address of the IOExpander, could be : IOE_1_ADDR or IOE_2_ADDR.
IO_Pin,: IO_Pin_x: Where x can be from 0 to 7.
Direction,: could be Direction_IN or Direction_OUT.
Return values:
IOE_OK,: if all initializations are OK. Other value if error.

Definition at line 539 of file stm32100e_eval_ioe.c.

References Direction_IN, I2C_ReadDeviceRegister(), I2C_WriteDeviceRegister(), IOE_OK, and IOE_REG_GPIO_DIR.

Referenced by IOE_Config().

uint8_t IOE_IsOperational ( uint8_t DeviceAddr )

IO-Expander Control functions.

IO-Expander Control functions.

Parameters:
DeviceAddr,: The address of the IOExpander, could be : IOE_1_ADDR.
Return values:
IOE_OK if IOE is operational. Other value if failure.

IO-Expander Control functions.

Parameters:
DeviceAddr,: The address of the IOExpander, could be : IOE_1_ADDR or IOE_2_ADDR.
Return values:
IOE_OK if IOE is operational. Other value if failure.

Definition at line 437 of file stm32100e_eval_ioe.c.

References IOE_FAILURE, IOE_OK, IOE_ReadID(), IOE_TimeOut, IOE_TimeoutUserCallback, and STMPE811_ID.

Referenced by IOE_Config().

uint8_t IOE_ITConfig ( uint32_t IOE_ITSRC_Source )

Configures The selected interrupts on the IO Expanders.

Parameters:
IOE_ITSRC_Source,: the source of the interrupts. Could be one or a combination of the following parameters:

  • IOE_ITSRC_TSC: Touch Screen interrupts.
Return values:
IOE_OK,: if all initializations are OK. Other value if error.
Parameters:
IOE_ITSRC_Source,: the source of the interrupts. Could be one or a combination of the following parameters:

  • IOE_ITSRC_JOYSTICK: Joystick IO intputs.
  • IOE_ITSRC_TSC: Touch Screen interrupts.
  • IOE_ITSRC_INMEMS: MEMS interrupt lines.
Return values:
IOE_OK,: if all initializations are OK. Other value if error.

Definition at line 169 of file stm32100e_eval_ioe.c.

References ENABLE, I2C_ReadDeviceRegister(), IOE_1_ADDR, IOE_2_ADDR, IOE_EXTI_Config(), IOE_GIT_FOV, IOE_GIT_FTH, IOE_GIT_GPIO, IOE_GIT_TOUCH, IOE_GITCmd(), IOE_GITConfig(), IOE_INMEMS_IT, IOE_IOITConfig(), IOE_ITOutConfig(), IOE_ITSRC_INMEMS, IOE_ITSRC_JOYSTICK, IOE_ITSRC_TSC, IOE_JOY_IT, IOE_OK, IOE_REG_GPIO_INT_STA, Polarity_High, Polarity_Low, and Type_Level.

Referenced by main().

uint8_t IOE_ITOutConfig | ( | uint8_t | Polarity,
 |  | uint8_t | Type
 | ) |  |

Configures the Interrupt line active state and format (level/edge)

Parameters:
Polarity,: could be

  • Polarity_Low: Interrupt line is active Low/Falling edge
  • Polarity_High: Interrupt line is active High/Rising edge
Type,: Interrupt line activity type, could be one of the following values

  • Type_Level: Interrupt line is active in level model
  • Type_Edge: Interrupt line is active in edge model
Return values:
IOE_OK,: if all initializations are OK. Other value if error.

Definition at line 838 of file stm32100e_eval_ioe.c.

References I2C_ReadDeviceRegister(), I2C_WriteDeviceRegister(), IOE_1_ADDR, IOE_2_ADDR, IOE_OK, and IOE_REG_INT_CTRL.

Referenced by IOE_ITConfig().

JOYState_TypeDef IOE_JoyStickGetState ( void )

Returns the current Joystick status.

Parameters:
None
Return values:
The code of the Joystick key pressed:

  • JOY_NONE
  • JOY_SEL
  • JOY_DOWN
  • JOY_LEFT
  • JOY_RIGHT
  • JOY_UP

Definition at line 383 of file stm3210c_eval_ioe.c.

References I2C_ReadDeviceRegister(), IOE_2_ADDR, IOE_REG_GPIO_MP_STA, JOY_DOWN, JOY_IO_DOWN, JOY_IO_LEFT, JOY_IO_NONE, JOY_IO_RIGHT, JOY_IO_SEL, JOY_IO_UP, JOY_LEFT, JOY_NONE, JOY_RIGHT, JOY_SEL, and JOY_UP.

Referenced by EXTI15_10_IRQHandler(), main(), and ReadKey().

uint16_t IOE_ReadID ( uint8_t DeviceAddr )

Reads the selected device's ID.

Parameters:
DeviceAddr,: The address of the IOExpander, could be : IOE_1_ADDR.
Return values:
The Device ID (two bytes).
Parameters:
DeviceAddr,: The address of the IOExpander, could be : IOE_1_ADDR or IOE_2_ADDR.
Return values:
The Device ID (two bytes).

Definition at line 483 of file stm32100e_eval_ioe.c.

References I2C_ReadDeviceRegister().

Referenced by IOE_IsOperational().

uint8_t IOE_ReadIOPin ( uint32_t IO_Pin )

Returns the status of the selected input IO pin.

Parameters:
IO_Pin,: The input pin to be read. IO_Pin_x: Where x can be from 0 to 7.

  • JOY_IO_PINS: Joystick IO pins (use IOE_JoyStickGetState for these pins)
Return values:
None
Parameters:
IO_Pin,: The input pin to be read. This parameter can be one of the following values:

  • MEMS_INT1_PIN: MEMS interrupt line 1.
  • MEMS_INT2_PIN: MEMS interrupt line 2.
  • JOY_IO_PINS: Joystick IO pins (use IOE_JoyStickGetState for these pins)
Return values:
None

Definition at line 239 of file stm32100e_eval_ioe.c.

References BitReset, BitSet, I2C_ReadDeviceRegister(), IO1_IN_ALL_PINS, IO2_IN_ALL_PINS, IOE_1_ADDR, IOE_2_ADDR, IOE_REG_GPIO_MP_STA, and PARAM_ERROR.

uint8_t IOE_Reset ( uint8_t DeviceAddr )

Resets the IO Expander by Software (SYS_CTRL1, RESET bit).

Parameters:
DeviceAddr,: The address of the IOExpander, could be : IOE_1_ADDR.
Return values:
IOE_OK,: if all initializations are OK. Other value if error.
Parameters:
DeviceAddr,: The address of the IOExpander, could be : IOE_1_ADDR or IOE_2_ADDR.
Return values:
IOE_OK,: if all initializations are OK. Other value if error.

Definition at line 463 of file stm32100e_eval_ioe.c.

References _delay_, I2C_WriteDeviceRegister(), IOE_OK, and IOE_REG_SYS_CTRL1.

Referenced by IOE_Config().

uint8_t IOE_TempSens_Config ( void )

Configures and enables the Temperature sensor module.

Parameters:
None
Return values:
IOE_OK if all initializations are OK. Other value if error.

Definition at line 734 of file stm32100e_eval_ioe.c.

References I2C_ReadDeviceRegister(), I2C_WriteDeviceRegister(), IOE_1_ADDR, IOE_2_ADDR, IOE_ADC_FCT, IOE_OK, IOE_REG_SYS_CTRL2, IOE_REG_TEMP_CTRL, and IOE_TEMPSENS_FCT.

Referenced by IOE_Config().

uint32_t IOE_TempSens_GetData ( void )

Temperature Sensor functions.

Temperature Sensor functions.

Parameters:
None
Return values:
The temperature row value.

Definition at line 310 of file stm32100e_eval_ioe.c.

References I2C_ReadDeviceRegister(), I2C_WriteDeviceRegister(), IOE_1_ADDR, IOE_2_ADDR, IOE_REG_TEMP_CTRL, and IOE_REG_TEMP_DATA.

uint8_t IOE_TS_Config ( void )

Low Layer functions.

Low Layer functions.

Parameters:
None
Return values:
IOE_OK if all initializations are OK. Other value if error.

Definition at line 669 of file stm32100e_eval_ioe.c.

References _delay_, I2C_ReadDeviceRegister(), I2C_WriteDeviceRegister(), IOE_1_ADDR, IOE_ADC_FCT, IOE_GIT_FOV, IOE_GIT_FTH, IOE_GIT_TOUCH, IOE_OK, IOE_REG_ADC_CTRL1, IOE_REG_ADC_CTRL2, IOE_REG_FIFO_STA, IOE_REG_FIFO_TH, IOE_REG_GPIO_AF, IOE_REG_INT_EN, IOE_REG_INT_STA, IOE_REG_SYS_CTRL2, IOE_REG_TSC_CFG, IOE_REG_TSC_CTRL, IOE_REG_TSC_FRACT_XYZ, IOE_REG_TSC_I_DRIVE, IOE_TS_FCT, TOUCH_IO_ALL, TS_STATE::TouchDetected, TS_STATE::X, TS_STATE::Y, and TS_STATE::Z.

Referenced by IOE_Config().

TS_STATE* IOE_TS_GetState ( void )

Touch Screen controller functions.

Touch Screen controller functions.

Parameters:
None
Return values:
Pointer to TS_STATE structure holding Touch Screen information.

Definition at line 270 of file stm32100e_eval_ioe.c.

References I2C_ReadDeviceRegister(), I2C_WriteDeviceRegister(), IOE_1_ADDR, IOE_REG_FIFO_STA, IOE_REG_TSC_CTRL, IOE_TS_Read_X(), IOE_TS_Read_Y(), IOE_TS_Read_Z(), TS_STATE::TouchDetected, TS_CONVERSION_DELAY, TS_State, TS_STATE::X, TS_STATE::Y, and TS_STATE::Z.

Referenced by EXTI15_10_IRQHandler(), and main().

uint8_t IOE_WriteIOPin | ( | uint8_t | IO_Pin,
 |  | IOE_BitValue_TypeDef | BitVal
 | ) |  |

IO pins control functions.

IO pins control functions.

Parameters:
IO_Pin,: The output pin to be set or reset. IO_Pin_x: Where x can be from 0 to 7.
BitVal,: The value to be set. This parameter can be one of the following values: BitSet or BitReset. See IOE_BitVal_TypeDef.
Return values:
IOE_OK or PARAM_ERROR

IO pins control functions.

Parameters:
IO_Pin,: The output pin to be set or reset. This parameter can be one of the following values:

  • AUDIO_RESET_PIN: Audio codec reset pin
  • MII_INT_PIN: Ethernet Phy MII interrupt pin
  • VBAT_DIV_PIN: Battery devider pin
BitVal,: The value to be set. This parameter can be one of the following values: BitSet or BitReset. See IOE_BitVal_TypeDef.
Return values:
IOE_OK or PARAM_ERROR

Definition at line 202 of file stm32100e_eval_ioe.c.

References BitReset, I2C_WriteDeviceRegister(), IO1_OUT_ALL_PINS, IO2_OUT_ALL_PINS, IOE_1_ADDR, IOE_2_ADDR, IOE_OK, IOE_REG_GPIO_CLR_PIN, IOE_REG_GPIO_SET_PIN, and PARAM_ERROR.

Referenced by IOE_Config().


STM32F10x Standard Peripherals Firmware Library: STM3210C_EVAL_LCD_Private_TypesDefinitions

STM3210C_EVAL_LCD_Private_TypesDefinitions

STM3210C_EVAL_LCD


STM32F10x Standard Peripherals Firmware Library: STM3210C_EVAL_LCD_Private_Defines

Defines

STM3210C_EVAL_LCD_Private_Defines

STM3210C_EVAL_LCD

Defines

#define | LCD_READ_REG 0x03
#define | LCD_WRITE_REG 0x02
#define | MAX_POLY_CORNERS 200
#define | POLY_X(Z) ((int32_t)((Points + Z)->Y))
#define | POLY_Y(Z) ((int32_t)((Points + Z)->X))
#define | READ_STATUS 0x01
#define | SET_INDEX 0x00
#define | START_BYTE 0x70

Define Documentation

#define LCD_READ_REG 0x03

Definition at line 60 of file stm3210c_eval_lcd.c.

Referenced by LCD_ReadReg().

#define LCD_WRITE_REG 0x02

Definition at line 59 of file stm3210c_eval_lcd.c.

Referenced by LCD_WriteRAM_Prepare(), and LCD_WriteReg().

#define MAX_POLY_CORNERS 200

Definition at line 61 of file stm3210c_eval_lcd.c.

Referenced by LCD_FillPolyLine().

#define POLY_X ( Z ) ((int32_t)((Points + Z)->Y))

Definition at line 63 of file stm3210c_eval_lcd.c.

Referenced by LCD_FillPolyLine().

#define POLY_Y ( Z ) ((int32_t)((Points + Z)->X))

Definition at line 62 of file stm3210c_eval_lcd.c.

Referenced by LCD_FillPolyLine().

#define READ_STATUS 0x01

Definition at line 58 of file stm3210c_eval_lcd.c.

#define SET_INDEX 0x00

Definition at line 57 of file stm3210c_eval_lcd.c.

Referenced by LCD_WriteRegIndex().

#define START_BYTE 0x70

Definition at line 56 of file stm3210c_eval_lcd.c.

Referenced by LCD_ReadReg(), LCD_WriteRAM_Prepare(), LCD_WriteReg(), and LCD_WriteRegIndex().


STM32F10x Standard Peripherals Firmware Library: STM3210C_EVAL_LCD_Private_Macros

Defines

STM3210C_EVAL_LCD_Private_Macros

STM3210C_EVAL_LCD

Defines

#define ABS(X) ((X) > 0 ? (X) : -(X))

Define Documentation

#define ABS ( X ) ((X) > 0 ? (X) : -(X))

Definition at line 72 of file stm3210c_eval_lcd.c.

Referenced by LCD_DrawUniLine().


STM32F10x Standard Peripherals Firmware Library: STM3210C_EVAL_LCD_Private_Variables

Variables

STM3210C_EVAL_LCD_Private_Variables

STM3210C_EVAL_LCD

Variables

static __IO uint16_t | BackColor = 0xFFFF
static sFONT * | LCD_Currentfonts
static __IO uint16_t | TextColor = 0x0000

Variable Documentation

__IO uint16_t BackColor = 0xFFFF

Definition at line 83 of file stm3210c_eval_lcd.c.

sFONT* LCD_Currentfonts [static]

Definition at line 81 of file stm3210c_eval_lcd.c.

Referenced by LCD_GetFont().

__IO uint16_t TextColor = 0x0000 [static]

Definition at line 83 of file stm3210c_eval_lcd.c.

Referenced by LCD_DrawChar(), LCD_DrawCircle(), LCD_DrawFullCircle(), LCD_DrawFullRect(), LCD_DrawLine(), LCD_DrawMonoPict(), LCD_FillPolyLine(), LCD_GetColors(), LCD_SetColors(), and LCD_SetTextColor().


STM32F10x Standard Peripherals Firmware Library: STM3210C_EVAL_LCD_Private_FunctionPrototypes

STM3210C_EVAL_LCD_Private_FunctionPrototypes

STM3210C_EVAL_LCD


STM32F10x Standard Peripherals Firmware Library: STM3210C_EVAL_LCD_Private_Functions

Functions

STM3210C_EVAL_LCD_Private_Functions

STM3210C_EVAL_LCD

Functions

static void | delay (__IO uint32_t nCount)
Inserts a delay time.
void | LCD_Clear (uint16_t Color)
Clears the hole LCD.
void | LCD_ClearLine (uint8_t Line)
Clears the selected line.
void | LCD_ClosedPolyLine (pPoint Points, uint16_t PointCount)
Displays a closed polyline (between many points).
void | LCD_ClosedPolyLineRelative (pPoint Points, uint16_t PointCount)
Displays a closed relative polyline (between many points).
void | LCD_CtrlLinesConfig (void)
Configures LCD control lines in Output Push-Pull mode.
void | LCD_CtrlLinesWrite (GPIO_TypeDef *GPIOx, uint16_t CtrlPins, BitAction BitVal)
Sets or reset LCD control lines.
void | LCD_DeInit (void)
DeInitializes the LCD.
void | LCD_DisplayChar (uint8_t Line, uint16_t Column, uint8_t Ascii)
Displays one character (16dots width, 24dots height).
void | LCD_DisplayOff (void)
Disables the Display.
void | LCD_DisplayOn (void)
Enables the Display.
void | LCD_DisplayStringLine (uint8_t Line, uint8_t *ptr)
Displays a maximum of 20 char on the LCD.
void | LCD_DrawChar (uint8_t Xpos, uint16_t Ypos, const uint16_t *c)
Draws a character on LCD.
void | LCD_DrawCircle (uint8_t Xpos, uint16_t Ypos, uint16_t Radius)
Displays a circle.
void | LCD_DrawFullCircle (uint16_t Xpos, uint16_t Ypos, uint16_t Radius)
Displays a full circle.
void | LCD_DrawFullRect (uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height)
Displays a full rectangle.
void | LCD_DrawLine (uint8_t Xpos, uint16_t Ypos, uint16_t Length, uint8_t Direction)
Displays a line.
void | LCD_DrawMonoPict (const uint32_t *Pict)
Displays a monocolor picture.
void | LCD_DrawRect (uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width)
Displays a rectangle.
void | LCD_DrawUniLine (uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2)
Displays an uni line (between two points).
void | LCD_FillPolyLine (pPoint Points, uint16_t PointCount)
Displays a full polyline (between many points).
void | LCD_GetColors (__IO uint16_t *_TextColor, __IO uint16_t *_BackColor)
Gets the LCD Text and Background colors.
sFONT * | LCD_GetFont (void)
Gets the Text Font.
void | LCD_nCS_StartByte (uint8_t Start_Byte)
Reset LCD control line(/CS) and Send Start-Byte.
void | LCD_PolyLine (pPoint Points, uint16_t PointCount)
Displays an polyline (between many points).
void | LCD_PolyLineRelative (pPoint Points, uint16_t PointCount)
Displays a relative polyline (between many points).
static void | LCD_PolyLineRelativeClosed (pPoint Points, uint16_t PointCount, uint16_t Closed)
Displays an relative polyline (between many points).
void | LCD_PowerOn (void)
Power on the LCD.
uint16_t | LCD_ReadReg (uint8_t LCD_Reg)
Reads the selected LCD Register.
void | LCD_SetBackColor (__IO uint16_t Color)
Sets the Background color.
void | LCD_SetColors (__IO uint16_t _TextColor, __IO uint16_t _BackColor)
Sets the LCD Text and Background colors.
void | LCD_SetCursor (uint8_t Xpos, uint16_t Ypos)
Sets the cursor position.
void | LCD_SetDisplayWindow (uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width)
Sets a display window.
void | LCD_SetFont (sFONT *fonts)
Sets the Text Font.
void | LCD_SetTextColor (__IO uint16_t Color)
Sets the Text color.
void | LCD_Setup (void)
Setups the LCD.
void | LCD_SPIConfig (void)
Configures the LCD_SPI interface.
void | LCD_WindowModeDisable (void)
Disables LCD Window mode.
void | LCD_WriteRAM (uint16_t RGB_Code)
Writes to the LCD RAM.
void | LCD_WriteRAM_Prepare (void)
Prepare to write to the LCD RAM.
void | LCD_WriteRAMWord (uint16_t RGB_Code)
Writes 1 word to the LCD RAM.
void | LCD_WriteReg (uint8_t LCD_Reg, uint16_t LCD_RegValue)
Writes to the selected LCD register.
void | LCD_WriteRegIndex (uint8_t LCD_Reg)
Writes index to select the LCD register.
static void | PutPixel (int16_t x, int16_t y)
Displays a pixel.
void | STM3210C_LCD_Init (void)
Initializes the LCD.

Function Documentation

static void delay ( __IO uint32_t nCount ) [static]

Inserts a delay time.

Parameters:
nCount,: specifies the delay time length.
Return values:
None

Definition at line 1379 of file stm3210c_eval_lcd.c.

References index.

void LCD_Clear ( uint16_t Color )

Clears the hole LCD.

Parameters:
Color,: the color of the background.
Return values:
None

Definition at line 332 of file stm3210c_eval_lcd.c.

References Bit_SET, index, LCD_CtrlLinesWrite(), LCD_NCS_GPIO_PORT, LCD_NCS_PIN, LCD_SetCursor(), LCD_WriteRAM(), and LCD_WriteRAM_Prepare().

void LCD_ClearLine ( uint8_t Line )

Clears the selected line.

Parameters:
Line,: the Line to be cleared. This parameter can be one of the following values:

  • Linex: where x can be 0..n
Return values:
None

Definition at line 313 of file stm3210c_eval_lcd.c.

References LCD_DisplayChar(), LCD_PIXEL_WIDTH, and _tFont::Width.

void LCD_ClosedPolyLine | ( | pPoint | Points,
 |  | uint16_t | PointCount
 | ) |  |

Displays a closed polyline (between many points).

Parameters:
Points,: pointer to the points array.
PointCount,: Number of points.
Return values:
None

Definition at line 927 of file stm3210c_eval_lcd.c.

References LCD_DrawUniLine(), LCD_PolyLine(), Point::X, and Point::Y.

void LCD_ClosedPolyLineRelative | ( | pPoint | Points,
 |  | uint16_t | PointCount
 | ) |  |

Displays a closed relative polyline (between many points).

Parameters:
Points,: pointer to the points array.
PointCount,: Number of points.
Return values:
None

Definition at line 950 of file stm3210c_eval_lcd.c.

References LCD_PolyLineRelativeClosed().

void LCD_CtrlLinesConfig ( void )

Configures LCD control lines in Output Push-Pull mode.

Parameters:
None
Return values:
None

Definition at line 1279 of file stm3210c_eval_lcd.c.

References ENABLE, GPIO_Init(), GPIO_InitStructure, GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_Out_PP, GPIO_InitTypeDef::GPIO_Pin, GPIO_InitTypeDef::GPIO_Speed, GPIO_Speed_50MHz, LCD_NCS_GPIO_CLK, LCD_NCS_GPIO_PORT, LCD_NCS_PIN, and RCC_APB2PeriphClockCmd().

void LCD_CtrlLinesWrite | ( | GPIO_TypeDef * | GPIOx,
 |  | uint16_t | CtrlPins,
 |  | BitAction | BitVal
 | ) |  |

Sets or reset LCD control lines.

Parameters:
GPIOx,: where x can be B or D to select the GPIO peripheral.
CtrlPins,: the Control line. This parameter can be:

  • LCD_NCS_PIN: Chip Select pin
BitVal,: specifies the value to be written to the selected bit. This parameter can be:

  • Bit_RESET: to clear the port pin
  • Bit_SET: to set the port pin
Return values:
None

Definition at line 1304 of file stm3210c_eval_lcd.c.

References GPIO_WriteBit().

void LCD_DeInit ( void )

DeInitializes the LCD.

Parameters:
None
Return values:
None

< LCD Display Off

< LCD_SPI disable

< LCD_SPI DeInit

< Disable SPI clock

Definition at line 111 of file stm3210c_eval_lcd.c.

References DISABLE, GPIO_Init(), GPIO_InitStructure, GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_IN_FLOATING, GPIO_InitTypeDef::GPIO_Pin, GPIO_PinRemapConfig(), GPIO_Remap_SPI3, LCD_DisplayOff(), LCD_NCS_GPIO_PORT, LCD_NCS_PIN, LCD_SPI, LCD_SPI_CLK, LCD_SPI_MISO_GPIO_PORT, LCD_SPI_MISO_PIN, LCD_SPI_MOSI_GPIO_PORT, LCD_SPI_MOSI_PIN, LCD_SPI_SCK_GPIO_PORT, LCD_SPI_SCK_PIN, RCC_APB1PeriphClockCmd(), SPI_Cmd(), and SPI_I2S_DeInit().

void LCD_DisplayChar | ( | uint8_t | Line,
 |  | uint16_t | Column,
 |  | uint8_t | Ascii
 | ) |  |

Displays one character (16dots width, 24dots height).

Parameters:
Line,: the Line where to display the character shape . This parameter can be one of the following values:

  • Linex: where x can be 0..9
Column,: start column address.
Ascii,: character ascii code, must be between 0x20 and 0x7E.
Return values:
None

Definition at line 408 of file stm3210c_eval_lcd.c.

References _tFont::Height, LCD_DrawChar(), and _tFont::table.

void LCD_DisplayOff ( void )

Disables the Display.

Parameters:
None
Return values:
None

Definition at line 1268 of file stm3210c_eval_lcd.c.

References LCD_REG_7, and LCD_WriteReg().

void LCD_DisplayOn ( void )

Enables the Display.

Parameters:
None
Return values:
None

Definition at line 1256 of file stm3210c_eval_lcd.c.

References LCD_REG_7, and LCD_WriteReg().

void LCD_DisplayStringLine | ( | uint8_t | Line,
 |  | uint8_t * | ptr
 | ) |  |

Displays a maximum of 20 char on the LCD.

Parameters:
Line,: the Line where to display the character shape . This parameter can be one of the following values:

  • Linex: where x can be 0..9
*ptr,: pointer to string to display on LCD.
Return values:
None

Definition at line 423 of file stm3210c_eval_lcd.c.

References LCD_DisplayChar(), LCD_PIXEL_WIDTH, and _tFont::Width.

void LCD_DrawChar | ( | uint8_t | Xpos,
 |  | uint16_t | Ypos,
 |  | const uint16_t * | c
 | ) |  |

Draws a character on LCD.

Parameters:
Xpos,: the Line where to display the character shape.
Ypos,: start column address.
c,: pointer to the character data.
Return values:
None

Definition at line 367 of file stm3210c_eval_lcd.c.

References BackColor, Bit_SET, _tFont::Height, index, LCD_CtrlLinesWrite(), LCD_NCS_GPIO_PORT, LCD_NCS_PIN, LCD_SetCursor(), LCD_WriteRAM(), LCD_WriteRAM_Prepare(), TextColor, and _tFont::Width.

void LCD_DrawCircle | ( | uint8_t | Xpos,
 |  | uint16_t | Ypos,
 |  | uint16_t | Radius
 | ) |  |

Displays a circle.

Parameters:
Xpos,: specifies the X position.
Ypos,: specifies the Y position.
Radius
Return values:
None

Definition at line 548 of file stm3210c_eval_lcd.c.

References LCD_SetCursor(), LCD_WriteRAMWord(), and TextColor.

void LCD_DrawFullCircle | ( | uint16_t | Xpos,
 |  | uint16_t | Ypos,
 |  | uint16_t | Radius
 | ) |  |

Displays a full circle.

Parameters:
Xpos,: specifies the X position.
Ypos,: specifies the Y position.
Radius
Return values:
None

Definition at line 748 of file stm3210c_eval_lcd.c.

References BackColor, LCD_DIR_HORIZONTAL, LCD_DrawCircle(), LCD_DrawLine(), LCD_SetTextColor(), and TextColor.

void LCD_DrawFullRect | ( | uint16_t | Xpos,
 |  | uint16_t | Ypos,
 |  | uint16_t | Width,
 |  | uint16_t | Height
 | ) |  |

Displays a full rectangle.

Parameters:
Xpos,: specifies the X position.
Ypos,: specifies the Y position.
Height,: rectangle height.
Width,: rectangle width.
Return values:
None

Definition at line 717 of file stm3210c_eval_lcd.c.

References BackColor, LCD_DIR_HORIZONTAL, LCD_DIR_VERTICAL, LCD_DrawLine(), LCD_SetTextColor(), and TextColor.

void LCD_DrawLine | ( | uint8_t | Xpos,
 |  | uint16_t | Ypos,
 |  | uint16_t | Length,
 |  | uint8_t | Direction
 | ) |  |

Displays a line.

Parameters:
Xpos,: specifies the X position.
Ypos,: specifies the Y position.
Length,: line length.
Direction,: line direction. This parameter can be one of the following values: Vertical or Horizontal.
Return values:
None

Definition at line 497 of file stm3210c_eval_lcd.c.

References Bit_SET, LCD_CtrlLinesWrite(), LCD_DIR_HORIZONTAL, LCD_NCS_GPIO_PORT, LCD_NCS_PIN, LCD_SetCursor(), LCD_WriteRAM(), LCD_WriteRAM_Prepare(), LCD_WriteRAMWord(), and TextColor.

void LCD_DrawMonoPict ( const uint32_t * Pict )

Displays a monocolor picture.

Parameters:
Pict,: pointer to the picture array.
Return values:
None

Definition at line 594 of file stm3210c_eval_lcd.c.

References BackColor, Bit_SET, index, LCD_CtrlLinesWrite(), LCD_NCS_GPIO_PORT, LCD_NCS_PIN, LCD_PIXEL_WIDTH, LCD_SetCursor(), LCD_WriteRAM(), LCD_WriteRAM_Prepare(), and TextColor.

void LCD_DrawRect | ( | uint8_t | Xpos,
 |  | uint16_t | Ypos,
 |  | uint8_t | Height,
 |  | uint16_t | Width
 | ) |  |

Displays a rectangle.

Parameters:
Xpos,: specifies the X position.
Ypos,: specifies the Y position.
Height,: display rectangle height.
Width,: display rectangle width.
Return values:
None

Definition at line 531 of file stm3210c_eval_lcd.c.

References LCD_DIR_HORIZONTAL, LCD_DIR_VERTICAL, and LCD_DrawLine().

void LCD_DrawUniLine | ( | uint16_t | x1,
 |  | uint16_t | y1,
 |  | uint16_t | x2,
 |  | uint16_t | y2
 | ) |  |

Displays an uni line (between two points).

Parameters:
x1,: specifies the point 1 x position.
y1,: specifies the point 1 y position.
x2,: specifies the point 2 x position.
y2,: specifies the point 2 y position.
Return values:
None

Definition at line 798 of file stm3210c_eval_lcd.c.

References ABS, and PutPixel().

void LCD_FillPolyLine | ( | pPoint | Points,
 |  | uint16_t | PointCount
 | ) |  |

Displays a full polyline (between many points).

Parameters:
Points,: pointer to the points array.
PointCount,: Number of points.
Return values:
None

Definition at line 962 of file stm3210c_eval_lcd.c.

References BackColor, j, LCD_DIR_HORIZONTAL, LCD_DrawLine(), LCD_SetTextColor(), MAX_POLY_CORNERS, POLY_X, POLY_Y, PutPixel(), TextColor, Point::X, and Point::Y.

void LCD_GetColors | ( | __IO uint16_t * | _TextColor,
 |  | __IO uint16_t * | _BackColor
 | ) |  |

Gets the LCD Text and Background colors.

Parameters:
_TextColor,: pointer to the variable that will contain the Text Color.
_BackColor,: pointer to the variable that will contain the Background Color.
Return values:
None

Definition at line 260 of file stm3210c_eval_lcd.c.

References BackColor, and TextColor.

sFONT* LCD_GetFont ( void )

Gets the Text Font.

Parameters:
None.
Return values:
the used font.

Definition at line 301 of file stm3210c_eval_lcd.c.

References LCD_Currentfonts.

void LCD_nCS_StartByte ( uint8_t Start_Byte )

Reset LCD control line(/CS) and Send Start-Byte.

Parameters:
Start_Byte,: the Start-Byte to be sent
Return values:
None

Definition at line 1068 of file stm3210c_eval_lcd.c.

References Bit_RESET, LCD_CtrlLinesWrite(), LCD_NCS_GPIO_PORT, LCD_NCS_PIN, LCD_SPI, RESET, SPI_I2S_FLAG_BSY, SPI_I2S_GetFlagStatus(), and SPI_I2S_SendData().

void LCD_PolyLine | ( | pPoint | Points,
 |  | uint16_t | PointCount
 | ) |  |

Displays an polyline (between many points).

Parameters:
Points,: pointer to the points array.
PointCount,: Number of points.
Return values:
None

Definition at line 871 of file stm3210c_eval_lcd.c.

References LCD_DrawUniLine(), Point::X, and Point::Y.

void LCD_PolyLineRelative | ( | pPoint | Points,
 |  | uint16_t | PointCount
 | ) |  |

Displays a relative polyline (between many points).

Parameters:
Points,: pointer to the points array.
PointCount,: Number of points.
Return values:
None

Definition at line 939 of file stm3210c_eval_lcd.c.

References LCD_PolyLineRelativeClosed().

static void LCD_PolyLineRelativeClosed | ( | pPoint | Points,
 |  | uint16_t | PointCount,
 |  | uint16_t | Closed
 | ) |  | [static]

Displays an relative polyline (between many points).

Parameters:
Points,: pointer to the points array.
PointCount,: Number of points.
Closed,: specifies if the draw is closed or not. 1: closed, 0 : not closed.
Return values:
None

Definition at line 897 of file stm3210c_eval_lcd.c.

References LCD_DrawUniLine(), Point::X, and Point::Y.

Referenced by LCD_ClosedPolyLineRelative(), and LCD_PolyLineRelative().

void LCD_PowerOn ( void )

Power on the LCD.

Parameters:
None
Return values:
None

Definition at line 1232 of file stm3210c_eval_lcd.c.

References _delay_, LCD_REG_16, LCD_REG_17, LCD_REG_18, LCD_REG_19, LCD_REG_41, LCD_REG_7, and LCD_WriteReg().

uint16_t LCD_ReadReg ( uint8_t LCD_Reg )

Reads the selected LCD Register.

Parameters:
None
Return values:
LCD Register Value.

Definition at line 1104 of file stm3210c_eval_lcd.c.

References Bit_SET, LCD_CtrlLinesWrite(), LCD_NCS_GPIO_PORT, LCD_NCS_PIN, LCD_nCS_StartByte(), LCD_READ_REG, LCD_SPI, LCD_WriteRegIndex(), RESET, SPI_I2S_FLAG_BSY, SPI_I2S_FLAG_RXNE, SPI_I2S_GetFlagStatus(), SPI_I2S_ReceiveData(), SPI_I2S_SendData(), and START_BYTE.

void LCD_SetBackColor ( __IO uint16_t Color )

Sets the Background color.

Parameters:
Color,: specifies the Background color code RGB(5-6-5).
Return values:
None

Definition at line 281 of file stm3210c_eval_lcd.c.

References BackColor.

void LCD_SetColors | ( | __IO uint16_t | _TextColor,
 |  | __IO uint16_t | _BackColor
 | ) |  |

Sets the LCD Text and Background colors.

Parameters:
_TextColor,: specifies the Text Color.
_BackColor,: specifies the Background Color.
Return values:
None

Definition at line 246 of file stm3210c_eval_lcd.c.

References BackColor, and TextColor.

void LCD_SetCursor | ( | uint8_t | Xpos,
 |  | uint16_t | Ypos
 | ) |  |

Sets the cursor position.

Parameters:
Xpos,: specifies the X position.
Ypos,: specifies the Y position.
Return values:
None

Definition at line 353 of file stm3210c_eval_lcd.c.

References LCD_REG_32, LCD_REG_33, and LCD_WriteReg().

void LCD_SetDisplayWindow | ( | uint8_t | Xpos,
 |  | uint16_t | Ypos,
 |  | uint8_t | Height,
 |  | uint16_t | Width
 | ) |  |

Sets a display window.

Parameters:
Xpos,: specifies the X buttom left position.
Ypos,: specifies the Y buttom left position.
Height,: display window height.
Width,: display window width.
Return values:
None

Definition at line 448 of file stm3210c_eval_lcd.c.

References LCD_REG_80, LCD_REG_81, LCD_REG_82, LCD_REG_83, LCD_SetCursor(), and LCD_WriteReg().

void LCD_SetFont ( sFONT * fonts )

Sets the Text Font.

Parameters:
fonts,: specifies the font to be used.
Return values:
None

Definition at line 291 of file stm3210c_eval_lcd.c.

void LCD_SetTextColor ( __IO uint16_t Color )

Sets the Text color.

Parameters:
Color,: specifies the Text color code RGB(5-6-5).
Return values:
None

Definition at line 270 of file stm3210c_eval_lcd.c.

References TextColor.

void LCD_Setup ( void )

Setups the LCD.

Parameters:
None
Return values:
None

Definition at line 149 of file stm3210c_eval_lcd.c.

References _delay_, LCD_CtrlLinesConfig(), LCD_REG_0, LCD_REG_1, LCD_REG_10, LCD_REG_106, LCD_REG_12, LCD_REG_128, LCD_REG_129, LCD_REG_13, LCD_REG_130, LCD_REG_131, LCD_REG_132, LCD_REG_133, LCD_REG_144, LCD_REG_146, LCD_REG_147, LCD_REG_149, LCD_REG_15, LCD_REG_151, LCD_REG_152, LCD_REG_16, LCD_REG_17, LCD_REG_18, LCD_REG_19, LCD_REG_2, LCD_REG_229, LCD_REG_3, LCD_REG_32, LCD_REG_33, LCD_REG_4, LCD_REG_41, LCD_REG_48, LCD_REG_49, LCD_REG_50, LCD_REG_53, LCD_REG_54, LCD_REG_55, LCD_REG_56, LCD_REG_57, LCD_REG_60, LCD_REG_61, LCD_REG_7, LCD_REG_8, LCD_REG_80, LCD_REG_81, LCD_REG_82, LCD_REG_83, LCD_REG_9, LCD_REG_96, LCD_REG_97, LCD_SPIConfig(), and LCD_WriteReg().

void LCD_SPIConfig ( void )

Configures the LCD_SPI interface.

Parameters:
None
Return values:
None

Definition at line 1316 of file stm3210c_eval_lcd.c.

References ENABLE, GPIO_Init(), GPIO_InitStructure, GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_AF_PP, GPIO_InitTypeDef::GPIO_Pin, GPIO_PinRemapConfig(), GPIO_Remap_SPI3, GPIO_InitTypeDef::GPIO_Speed, GPIO_Speed_50MHz, LCD_SPI, LCD_SPI_CLK, LCD_SPI_MISO_GPIO_CLK, LCD_SPI_MISO_GPIO_PORT, LCD_SPI_MISO_PIN, LCD_SPI_MOSI_GPIO_CLK, LCD_SPI_MOSI_GPIO_PORT, LCD_SPI_MOSI_PIN, LCD_SPI_SCK_GPIO_CLK, LCD_SPI_SCK_GPIO_PORT, LCD_SPI_SCK_PIN, RCC_APB1PeriphClockCmd(), RCC_APB2Periph_AFIO, RCC_APB2PeriphClockCmd(), SPI_InitTypeDef::SPI_BaudRatePrescaler, SPI_BaudRatePrescaler_2, SPI_Cmd(), SPI_InitTypeDef::SPI_CPHA, SPI_CPHA_2Edge, SPI_InitTypeDef::SPI_CPOL, SPI_CPOL_High, SPI_InitTypeDef::SPI_DataSize, SPI_DataSize_8b, SPI_InitTypeDef::SPI_Direction, SPI_Direction_2Lines_FullDuplex, SPI_InitTypeDef::SPI_FirstBit, SPI_FirstBit_MSB, SPI_I2S_DeInit(), SPI_Init(), SPI_InitStructure, SPI_InitTypeDef::SPI_Mode, SPI_Mode_Master, SPI_InitTypeDef::SPI_NSS, and SPI_NSS_Soft.

void LCD_WindowModeDisable ( void )

Disables LCD Window mode.

Parameters:
None
Return values:
None

Definition at line 481 of file stm3210c_eval_lcd.c.

References LCD_REG_3, LCD_SetDisplayWindow(), and LCD_WriteReg().

void LCD_WriteRAM ( uint16_t RGB_Code )

Writes to the LCD RAM.

Parameters:
RGB_Code,: the pixel color in RGB mode (5-6-5).
Return values:
None

Definition at line 1214 of file stm3210c_eval_lcd.c.

References LCD_SPI, RESET, SPI_I2S_FLAG_BSY, SPI_I2S_GetFlagStatus(), and SPI_I2S_SendData().

void LCD_WriteRAM_Prepare ( void )

Prepare to write to the LCD RAM.

Parameters:
None
Return values:
None

Definition at line 1163 of file stm3210c_eval_lcd.c.

References LCD_nCS_StartByte(), LCD_REG_34, LCD_WRITE_REG, LCD_WriteRegIndex(), and START_BYTE.

void LCD_WriteRAMWord ( uint16_t RGB_Code )

Writes 1 word to the LCD RAM.

Parameters:
RGB_Code,: the pixel color in RGB mode (5-6-5).
Return values:
None

Definition at line 1176 of file stm3210c_eval_lcd.c.

References Bit_SET, LCD_CtrlLinesWrite(), LCD_NCS_GPIO_PORT, LCD_NCS_PIN, LCD_WriteRAM(), and LCD_WriteRAM_Prepare().

void LCD_WriteReg | ( | uint8_t | LCD_Reg,
 |  | uint16_t | LCD_RegValue
 | ) |  |

Writes to the selected LCD register.

Parameters:
LCD_Reg,: address of the selected register.
LCD_RegValue,: value to write to the selected register.
Return values:
None

Definition at line 1190 of file stm3210c_eval_lcd.c.

References Bit_SET, LCD_CtrlLinesWrite(), LCD_NCS_GPIO_PORT, LCD_NCS_PIN, LCD_nCS_StartByte(), LCD_SPI, LCD_WRITE_REG, LCD_WriteRegIndex(), RESET, SPI_I2S_FLAG_BSY, SPI_I2S_GetFlagStatus(), SPI_I2S_SendData(), and START_BYTE.

void LCD_WriteRegIndex ( uint8_t LCD_Reg )

Writes index to select the LCD register.

Parameters:
LCD_Reg,: address of the selected register.
Return values:
None

Definition at line 1082 of file stm3210c_eval_lcd.c.

References Bit_SET, LCD_CtrlLinesWrite(), LCD_NCS_GPIO_PORT, LCD_NCS_PIN, LCD_nCS_StartByte(), LCD_SPI, RESET, SET_INDEX, SPI_I2S_FLAG_BSY, SPI_I2S_GetFlagStatus(), SPI_I2S_SendData(), and START_BYTE.

static void PutPixel | ( | int16_t | x,
 |  | int16_t | y
 | ) |  | [static]

Displays a pixel.

Parameters:
x,: pixel x.
y,: pixel y.
Return values:
None

Definition at line 1364 of file stm3210c_eval_lcd.c.

References LCD_DIR_HORIZONTAL, and LCD_DrawLine().

Referenced by LCD_DrawUniLine(), and LCD_FillPolyLine().

void STM3210C_LCD_Init ( void )

Initializes the LCD.

Parameters:
None
Return values:
None

Definition at line 233 of file stm3210c_eval_lcd.c.

References LCD_DEFAULT_FONT, LCD_SetFont(), and LCD_Setup().

Referenced by main().


STM32F10x Standard Peripherals Firmware Library: STM3210C_EVAL_LCD_Exported_Types

Data Structures | Typedefs

STM3210C_EVAL_LCD_Exported_Types

STM3210C_EVAL_LCD

Data Structures

struct | Point

Typedefs

typedef struct Point * | pPoint

Typedef Documentation

typedef struct Point * pPoint


STM32F10x Standard Peripherals Firmware Library: STM3210C_EVAL_LCD_Exported_Constants

Defines

STM3210C_EVAL_LCD_Exported_Constants

STM3210C_EVAL_LCD

Defines

#define | _delay_ delay
Uncomment the line below if you want to use LCD_DrawBMP function to display a bitmap picture on the LCD.
#define | LCD_COLOR_BLACK 0x0000
#define | LCD_COLOR_BLUE 0x001F
#define | LCD_COLOR_BLUE2 0x051F
#define | LCD_COLOR_CYAN 0x7FFF
#define | LCD_COLOR_GREEN 0x07E0
#define | LCD_COLOR_GREY 0xF7DE
#define | LCD_COLOR_MAGENTA 0xF81F
#define | LCD_COLOR_RED 0xF800
#define | LCD_COLOR_WHITE 0xFFFF
LCD color.
#define | LCD_COLOR_YELLOW 0xFFE0
#define | LCD_DEFAULT_FONT Font16x24
LCD default font.
#define | LCD_DIR_HORIZONTAL 0x0000
LCD Direction.
#define | LCD_DIR_VERTICAL 0x0001
#define | LCD_LINE_0 LINE(0)
LCD Lines depending on the chosen fonts.
#define | LCD_LINE_1 LINE(1)
#define | LCD_LINE_10 LINE(10)
#define | LCD_LINE_11 LINE(11)
#define | LCD_LINE_12 LINE(12)
#define | LCD_LINE_13 LINE(13)
#define | LCD_LINE_14 LINE(14)
#define | LCD_LINE_15 LINE(15)
#define | LCD_LINE_16 LINE(16)
#define | LCD_LINE_17 LINE(17)
#define | LCD_LINE_18 LINE(18)
#define | LCD_LINE_19 LINE(19)
#define | LCD_LINE_2 LINE(2)
#define | LCD_LINE_20 LINE(20)
#define | LCD_LINE_21 LINE(21)
#define | LCD_LINE_22 LINE(22)
#define | LCD_LINE_23 LINE(23)
#define | LCD_LINE_24 LINE(24)
#define | LCD_LINE_25 LINE(25)
#define | LCD_LINE_26 LINE(26)
#define | LCD_LINE_27 LINE(27)
#define | LCD_LINE_28 LINE(28)
#define | LCD_LINE_29 LINE(29)
#define | LCD_LINE_3 LINE(3)
#define | LCD_LINE_4 LINE(4)
#define | LCD_LINE_5 LINE(5)
#define | LCD_LINE_6 LINE(6)
#define | LCD_LINE_7 LINE(7)
#define | LCD_LINE_8 LINE(8)
#define | LCD_LINE_9 LINE(9)
#define | LCD_NCS_GPIO_CLK RCC_APB2Periph_GPIOB
#define | LCD_NCS_GPIO_PORT GPIOB
#define | LCD_NCS_PIN GPIO_Pin_2
LCD Control pins.
#define | LCD_PIXEL_HEIGHT 0x00F0
#define | LCD_PIXEL_WIDTH 0x0140
LCD Size (Width and Height)
#define | LCD_REG_0 0x00
LCD Registers.
#define | LCD_REG_1 0x01
#define | LCD_REG_10 0x0A
#define | LCD_REG_106 0x6A
#define | LCD_REG_118 0x76
#define | LCD_REG_12 0x0C
#define | LCD_REG_128 0x80
#define | LCD_REG_129 0x81
#define | LCD_REG_13 0x0D
#define | LCD_REG_130 0x82
#define | LCD_REG_131 0x83
#define | LCD_REG_132 0x84
#define | LCD_REG_133 0x85
#define | LCD_REG_134 0x86
#define | LCD_REG_135 0x87
#define | LCD_REG_136 0x88
#define | LCD_REG_137 0x89
#define | LCD_REG_139 0x8B
#define | LCD_REG_14 0x0E
#define | LCD_REG_140 0x8C
#define | LCD_REG_141 0x8D
#define | LCD_REG_143 0x8F
#define | LCD_REG_144 0x90
#define | LCD_REG_145 0x91
#define | LCD_REG_146 0x92
#define | LCD_REG_147 0x93
#define | LCD_REG_148 0x94
#define | LCD_REG_149 0x95
#define | LCD_REG_15 0x0F
#define | LCD_REG_150 0x96
#define | LCD_REG_151 0x97
#define | LCD_REG_152 0x98
#define | LCD_REG_153 0x99
#define | LCD_REG_154 0x9A
#define | LCD_REG_157 0x9D
#define | LCD_REG_16 0x10
#define | LCD_REG_17 0x11
#define | LCD_REG_18 0x12
#define | LCD_REG_19 0x13
#define | LCD_REG_192 0xC0
#define | LCD_REG_193 0xC1
#define | LCD_REG_2 0x02
#define | LCD_REG_20 0x14
#define | LCD_REG_21 0x15
#define | LCD_REG_22 0x16
#define | LCD_REG_229 0xE5
#define | LCD_REG_23 0x17
#define | LCD_REG_24 0x18
#define | LCD_REG_25 0x19
#define | LCD_REG_26 0x1A
#define | LCD_REG_27 0x1B
#define | LCD_REG_28 0x1C
#define | LCD_REG_29 0x1D
#define | LCD_REG_3 0x03
#define | LCD_REG_30 0x1E
#define | LCD_REG_31 0x1F
#define | LCD_REG_32 0x20
#define | LCD_REG_33 0x21
#define | LCD_REG_34 0x22
#define | LCD_REG_36 0x24
#define | LCD_REG_37 0x25
#define | LCD_REG_4 0x04
#define | LCD_REG_40 0x28
#define | LCD_REG_41 0x29
#define | LCD_REG_43 0x2B
#define | LCD_REG_45 0x2D
#define | LCD_REG_48 0x30
#define | LCD_REG_49 0x31
#define | LCD_REG_5 0x05
#define | LCD_REG_50 0x32
#define | LCD_REG_51 0x33
#define | LCD_REG_52 0x34
#define | LCD_REG_53 0x35
#define | LCD_REG_54 0x36
#define | LCD_REG_55 0x37
#define | LCD_REG_56 0x38
#define | LCD_REG_57 0x39
#define | LCD_REG_59 0x3B
#define | LCD_REG_6 0x06
#define | LCD_REG_60 0x3C
#define | LCD_REG_61 0x3D
#define | LCD_REG_62 0x3E
#define | LCD_REG_63 0x3F
#define | LCD_REG_64 0x40
#define | LCD_REG_65 0x41
#define | LCD_REG_66 0x42
#define | LCD_REG_67 0x43
#define | LCD_REG_68 0x44
#define | LCD_REG_69 0x45
#define | LCD_REG_7 0x07
#define | LCD_REG_70 0x46
#define | LCD_REG_71 0x47
#define | LCD_REG_72 0x48
#define | LCD_REG_73 0x49
#define | LCD_REG_74 0x4A
#define | LCD_REG_75 0x4B
#define | LCD_REG_76 0x4C
#define | LCD_REG_77 0x4D
#define | LCD_REG_78 0x4E
#define | LCD_REG_79 0x4F
#define | LCD_REG_8 0x08
#define | LCD_REG_80 0x50
#define | LCD_REG_81 0x51
#define | LCD_REG_82 0x52
#define | LCD_REG_83 0x53
#define | LCD_REG_9 0x09
#define | LCD_REG_96 0x60
#define | LCD_REG_97 0x61
#define | LCD_SPI SPI3
LCD SPI Interface pins.
#define | LCD_SPI_CLK RCC_APB1Periph_SPI3
#define | LCD_SPI_MISO_GPIO_CLK RCC_APB2Periph_GPIOC
#define | LCD_SPI_MISO_GPIO_PORT GPIOC
#define | LCD_SPI_MISO_PIN GPIO_Pin_11
#define | LCD_SPI_MOSI_GPIO_CLK RCC_APB2Periph_GPIOC
#define | LCD_SPI_MOSI_GPIO_PORT GPIOC
#define | LCD_SPI_MOSI_PIN GPIO_Pin_12
#define | LCD_SPI_SCK_GPIO_CLK RCC_APB2Periph_GPIOC
#define | LCD_SPI_SCK_GPIO_PORT GPIOC
#define | LCD_SPI_SCK_PIN GPIO_Pin_10

Define Documentation

#define _delay_ delay

Uncomment the line below if you want to use LCD_DrawBMP function to display a bitmap picture on the LCD.

This function assumes that the bitmap file is loaded in the SPI Flash (mounted on STM3210C-EVAL board), however user can tailor it according to his application hardware requirement. Uncomment the line below if you want to use user defined Delay function (for precise timing), otherwise default _delay_ function defined within this driver is used (less precise timing).

Definition at line 88 of file stm3210c_eval_lcd.h.

#define LCD_COLOR_BLACK 0x0000

Definition at line 229 of file stm3210c_eval_lcd.h.

#define LCD_COLOR_BLUE 0x001F

Definition at line 231 of file stm3210c_eval_lcd.h.

#define LCD_COLOR_BLUE2 0x051F

Definition at line 232 of file stm3210c_eval_lcd.h.

#define LCD_COLOR_CYAN 0x7FFF

Definition at line 236 of file stm3210c_eval_lcd.h.

#define LCD_COLOR_GREEN 0x07E0

Definition at line 235 of file stm3210c_eval_lcd.h.

#define LCD_COLOR_GREY 0xF7DE

Definition at line 230 of file stm3210c_eval_lcd.h.

#define LCD_COLOR_MAGENTA 0xF81F

Definition at line 234 of file stm3210c_eval_lcd.h.

#define LCD_COLOR_RED 0xF800

Definition at line 233 of file stm3210c_eval_lcd.h.

#define LCD_COLOR_WHITE 0xFFFF

LCD color.

Definition at line 228 of file stm3210c_eval_lcd.h.

#define LCD_COLOR_YELLOW 0xFFE0

Definition at line 237 of file stm3210c_eval_lcd.h.

#define LCD_DEFAULT_FONT Font16x24

LCD default font.

Definition at line 276 of file stm3210c_eval_lcd.h.

#define LCD_DIR_HORIZONTAL 0x0000

LCD Direction.

Definition at line 281 of file stm3210c_eval_lcd.h.

#define LCD_DIR_VERTICAL 0x0001

Definition at line 282 of file stm3210c_eval_lcd.h.

#define LCD_LINE_0 LINE(0)

LCD Lines depending on the chosen fonts.

Definition at line 242 of file stm3210c_eval_lcd.h.

#define LCD_LINE_1 LINE(1)

Definition at line 243 of file stm3210c_eval_lcd.h.

#define LCD_LINE_10 LINE(10)

Definition at line 252 of file stm3210c_eval_lcd.h.

#define LCD_LINE_11 LINE(11)

Definition at line 253 of file stm3210c_eval_lcd.h.

#define LCD_LINE_12 LINE(12)

Definition at line 254 of file stm3210c_eval_lcd.h.

#define LCD_LINE_13 LINE(13)

Definition at line 255 of file stm3210c_eval_lcd.h.

#define LCD_LINE_14 LINE(14)

Definition at line 256 of file stm3210c_eval_lcd.h.

#define LCD_LINE_15 LINE(15)

Definition at line 257 of file stm3210c_eval_lcd.h.

#define LCD_LINE_16 LINE(16)

Definition at line 258 of file stm3210c_eval_lcd.h.

#define LCD_LINE_17 LINE(17)

Definition at line 259 of file stm3210c_eval_lcd.h.

#define LCD_LINE_18 LINE(18)

Definition at line 260 of file stm3210c_eval_lcd.h.

#define LCD_LINE_19 LINE(19)

Definition at line 261 of file stm3210c_eval_lcd.h.

#define LCD_LINE_2 LINE(2)

Definition at line 244 of file stm3210c_eval_lcd.h.

#define LCD_LINE_20 LINE(20)

Definition at line 262 of file stm3210c_eval_lcd.h.

#define LCD_LINE_21 LINE(21)

Definition at line 263 of file stm3210c_eval_lcd.h.

#define LCD_LINE_22 LINE(22)

Definition at line 264 of file stm3210c_eval_lcd.h.

#define LCD_LINE_23 LINE(23)

Definition at line 265 of file stm3210c_eval_lcd.h.

#define LCD_LINE_24 LINE(24)

Definition at line 266 of file stm3210c_eval_lcd.h.

#define LCD_LINE_25 LINE(25)

Definition at line 267 of file stm3210c_eval_lcd.h.

#define LCD_LINE_26 LINE(26)

Definition at line 268 of file stm3210c_eval_lcd.h.

#define LCD_LINE_27 LINE(27)

Definition at line 269 of file stm3210c_eval_lcd.h.

#define LCD_LINE_28 LINE(28)

Definition at line 270 of file stm3210c_eval_lcd.h.

#define LCD_LINE_29 LINE(29)

Definition at line 271 of file stm3210c_eval_lcd.h.

#define LCD_LINE_3 LINE(3)

Definition at line 245 of file stm3210c_eval_lcd.h.

#define LCD_LINE_4 LINE(4)

Definition at line 246 of file stm3210c_eval_lcd.h.

#define LCD_LINE_5 LINE(5)

Definition at line 247 of file stm3210c_eval_lcd.h.

#define LCD_LINE_6 LINE(6)

Definition at line 248 of file stm3210c_eval_lcd.h.

#define LCD_LINE_7 LINE(7)

Definition at line 249 of file stm3210c_eval_lcd.h.

#define LCD_LINE_8 LINE(8)

Definition at line 250 of file stm3210c_eval_lcd.h.

#define LCD_LINE_9 LINE(9)

Definition at line 251 of file stm3210c_eval_lcd.h.

#define LCD_NCS_GPIO_CLK RCC_APB2Periph_GPIOB

Definition at line 96 of file stm3210c_eval_lcd.h.

#define LCD_NCS_GPIO_PORT GPIOB

Definition at line 95 of file stm3210c_eval_lcd.h.

#define LCD_NCS_PIN GPIO_Pin_2

LCD Control pins.

Definition at line 94 of file stm3210c_eval_lcd.h.

#define LCD_PIXEL_HEIGHT 0x00F0

Definition at line 288 of file stm3210c_eval_lcd.h.

#define LCD_PIXEL_WIDTH 0x0140

LCD Size (Width and Height)

Definition at line 287 of file stm3210c_eval_lcd.h.

#define LCD_REG_0 0x00

LCD Registers.

Definition at line 116 of file stm3210c_eval_lcd.h.

#define LCD_REG_1 0x01

Definition at line 117 of file stm3210c_eval_lcd.h.

#define LCD_REG_10 0x0A

Definition at line 126 of file stm3210c_eval_lcd.h.

#define LCD_REG_106 0x6A

Definition at line 193 of file stm3210c_eval_lcd.h.

#define LCD_REG_118 0x76

Definition at line 194 of file stm3210c_eval_lcd.h.

#define LCD_REG_12 0x0C

Definition at line 127 of file stm3210c_eval_lcd.h.

#define LCD_REG_128 0x80

Definition at line 195 of file stm3210c_eval_lcd.h.

#define LCD_REG_129 0x81

Definition at line 196 of file stm3210c_eval_lcd.h.

#define LCD_REG_13 0x0D

Definition at line 128 of file stm3210c_eval_lcd.h.

#define LCD_REG_130 0x82

Definition at line 197 of file stm3210c_eval_lcd.h.

#define LCD_REG_131 0x83

Definition at line 198 of file stm3210c_eval_lcd.h.

#define LCD_REG_132 0x84

Definition at line 199 of file stm3210c_eval_lcd.h.

#define LCD_REG_133 0x85

Definition at line 200 of file stm3210c_eval_lcd.h.

#define LCD_REG_134 0x86

Definition at line 201 of file stm3210c_eval_lcd.h.

#define LCD_REG_135 0x87

Definition at line 202 of file stm3210c_eval_lcd.h.

#define LCD_REG_136 0x88

Definition at line 203 of file stm3210c_eval_lcd.h.

#define LCD_REG_137 0x89

Definition at line 204 of file stm3210c_eval_lcd.h.

#define LCD_REG_139 0x8B

Definition at line 205 of file stm3210c_eval_lcd.h.

#define LCD_REG_14 0x0E

Definition at line 129 of file stm3210c_eval_lcd.h.

#define LCD_REG_140 0x8C

Definition at line 206 of file stm3210c_eval_lcd.h.

#define LCD_REG_141 0x8D

Definition at line 207 of file stm3210c_eval_lcd.h.

#define LCD_REG_143 0x8F

Definition at line 208 of file stm3210c_eval_lcd.h.

#define LCD_REG_144 0x90

Definition at line 209 of file stm3210c_eval_lcd.h.

#define LCD_REG_145 0x91

Definition at line 210 of file stm3210c_eval_lcd.h.

#define LCD_REG_146 0x92

Definition at line 211 of file stm3210c_eval_lcd.h.

#define LCD_REG_147 0x93

Definition at line 212 of file stm3210c_eval_lcd.h.

#define LCD_REG_148 0x94

Definition at line 213 of file stm3210c_eval_lcd.h.

#define LCD_REG_149 0x95

Definition at line 214 of file stm3210c_eval_lcd.h.

#define LCD_REG_15 0x0F

Definition at line 130 of file stm3210c_eval_lcd.h.

#define LCD_REG_150 0x96

Definition at line 215 of file stm3210c_eval_lcd.h.

#define LCD_REG_151 0x97

Definition at line 216 of file stm3210c_eval_lcd.h.

#define LCD_REG_152 0x98

Definition at line 217 of file stm3210c_eval_lcd.h.

#define LCD_REG_153 0x99

Definition at line 218 of file stm3210c_eval_lcd.h.

#define LCD_REG_154 0x9A

Definition at line 219 of file stm3210c_eval_lcd.h.

#define LCD_REG_157 0x9D

Definition at line 220 of file stm3210c_eval_lcd.h.

#define LCD_REG_16 0x10

Definition at line 131 of file stm3210c_eval_lcd.h.

#define LCD_REG_17 0x11

Definition at line 132 of file stm3210c_eval_lcd.h.

#define LCD_REG_18 0x12

Definition at line 133 of file stm3210c_eval_lcd.h.

#define LCD_REG_19 0x13

Definition at line 134 of file stm3210c_eval_lcd.h.

#define LCD_REG_192 0xC0

Definition at line 221 of file stm3210c_eval_lcd.h.

#define LCD_REG_193 0xC1

Definition at line 222 of file stm3210c_eval_lcd.h.

#define LCD_REG_2 0x02

Definition at line 118 of file stm3210c_eval_lcd.h.

#define LCD_REG_20 0x14

Definition at line 135 of file stm3210c_eval_lcd.h.

#define LCD_REG_21 0x15

Definition at line 136 of file stm3210c_eval_lcd.h.

#define LCD_REG_22 0x16

Definition at line 137 of file stm3210c_eval_lcd.h.

#define LCD_REG_229 0xE5

Definition at line 223 of file stm3210c_eval_lcd.h.

#define LCD_REG_23 0x17

Definition at line 138 of file stm3210c_eval_lcd.h.

#define LCD_REG_24 0x18

Definition at line 139 of file stm3210c_eval_lcd.h.

#define LCD_REG_25 0x19

Definition at line 140 of file stm3210c_eval_lcd.h.

#define LCD_REG_26 0x1A

Definition at line 141 of file stm3210c_eval_lcd.h.

#define LCD_REG_27 0x1B

Definition at line 142 of file stm3210c_eval_lcd.h.

#define LCD_REG_28 0x1C

Definition at line 143 of file stm3210c_eval_lcd.h.

#define LCD_REG_29 0x1D

Definition at line 144 of file stm3210c_eval_lcd.h.

#define LCD_REG_3 0x03

Definition at line 119 of file stm3210c_eval_lcd.h.

#define LCD_REG_30 0x1E

Definition at line 145 of file stm3210c_eval_lcd.h.

#define LCD_REG_31 0x1F

Definition at line 146 of file stm3210c_eval_lcd.h.

#define LCD_REG_32 0x20

Definition at line 147 of file stm3210c_eval_lcd.h.

#define LCD_REG_33 0x21

Definition at line 148 of file stm3210c_eval_lcd.h.

#define LCD_REG_34 0x22

Definition at line 149 of file stm3210c_eval_lcd.h.

#define LCD_REG_36 0x24

Definition at line 150 of file stm3210c_eval_lcd.h.

#define LCD_REG_37 0x25

Definition at line 151 of file stm3210c_eval_lcd.h.

#define LCD_REG_4 0x04

Definition at line 120 of file stm3210c_eval_lcd.h.

#define LCD_REG_40 0x28

Definition at line 152 of file stm3210c_eval_lcd.h.

#define LCD_REG_41 0x29

Definition at line 153 of file stm3210c_eval_lcd.h.

#define LCD_REG_43 0x2B

Definition at line 154 of file stm3210c_eval_lcd.h.

#define LCD_REG_45 0x2D

Definition at line 155 of file stm3210c_eval_lcd.h.

#define LCD_REG_48 0x30

Definition at line 156 of file stm3210c_eval_lcd.h.

#define LCD_REG_49 0x31

Definition at line 157 of file stm3210c_eval_lcd.h.

#define LCD_REG_5 0x05

Definition at line 121 of file stm3210c_eval_lcd.h.

#define LCD_REG_50 0x32

Definition at line 158 of file stm3210c_eval_lcd.h.

#define LCD_REG_51 0x33

Definition at line 159 of file stm3210c_eval_lcd.h.

#define LCD_REG_52 0x34

Definition at line 160 of file stm3210c_eval_lcd.h.

#define LCD_REG_53 0x35

Definition at line 161 of file stm3210c_eval_lcd.h.

#define LCD_REG_54 0x36

Definition at line 162 of file stm3210c_eval_lcd.h.

#define LCD_REG_55 0x37

Definition at line 163 of file stm3210c_eval_lcd.h.

#define LCD_REG_56 0x38

Definition at line 164 of file stm3210c_eval_lcd.h.

#define LCD_REG_57 0x39

Definition at line 165 of file stm3210c_eval_lcd.h.

#define LCD_REG_59 0x3B

Definition at line 166 of file stm3210c_eval_lcd.h.

#define LCD_REG_6 0x06

Definition at line 122 of file stm3210c_eval_lcd.h.

#define LCD_REG_60 0x3C

Definition at line 167 of file stm3210c_eval_lcd.h.

#define LCD_REG_61 0x3D

Definition at line 168 of file stm3210c_eval_lcd.h.

#define LCD_REG_62 0x3E

Definition at line 169 of file stm3210c_eval_lcd.h.

#define LCD_REG_63 0x3F

Definition at line 170 of file stm3210c_eval_lcd.h.

#define LCD_REG_64 0x40

Definition at line 171 of file stm3210c_eval_lcd.h.

#define LCD_REG_65 0x41

Definition at line 172 of file stm3210c_eval_lcd.h.

#define LCD_REG_66 0x42

Definition at line 173 of file stm3210c_eval_lcd.h.

#define LCD_REG_67 0x43

Definition at line 174 of file stm3210c_eval_lcd.h.

#define LCD_REG_68 0x44

Definition at line 175 of file stm3210c_eval_lcd.h.

#define LCD_REG_69 0x45

Definition at line 176 of file stm3210c_eval_lcd.h.

#define LCD_REG_7 0x07

Definition at line 123 of file stm3210c_eval_lcd.h.

#define LCD_REG_70 0x46

Definition at line 177 of file stm3210c_eval_lcd.h.

#define LCD_REG_71 0x47

Definition at line 178 of file stm3210c_eval_lcd.h.

#define LCD_REG_72 0x48

Definition at line 179 of file stm3210c_eval_lcd.h.

#define LCD_REG_73 0x49

Definition at line 180 of file stm3210c_eval_lcd.h.

#define LCD_REG_74 0x4A

Definition at line 181 of file stm3210c_eval_lcd.h.

#define LCD_REG_75 0x4B

Definition at line 182 of file stm3210c_eval_lcd.h.

#define LCD_REG_76 0x4C

Definition at line 183 of file stm3210c_eval_lcd.h.

#define LCD_REG_77 0x4D

Definition at line 184 of file stm3210c_eval_lcd.h.

#define LCD_REG_78 0x4E

Definition at line 185 of file stm3210c_eval_lcd.h.

#define LCD_REG_79 0x4F

Definition at line 186 of file stm3210c_eval_lcd.h.

#define LCD_REG_8 0x08

Definition at line 124 of file stm3210c_eval_lcd.h.

#define LCD_REG_80 0x50

Definition at line 187 of file stm3210c_eval_lcd.h.

#define LCD_REG_81 0x51

Definition at line 188 of file stm3210c_eval_lcd.h.

#define LCD_REG_82 0x52

Definition at line 189 of file stm3210c_eval_lcd.h.

#define LCD_REG_83 0x53

Definition at line 190 of file stm3210c_eval_lcd.h.

#define LCD_REG_9 0x09

Definition at line 125 of file stm3210c_eval_lcd.h.

#define LCD_REG_96 0x60

Definition at line 191 of file stm3210c_eval_lcd.h.

#define LCD_REG_97 0x61

Definition at line 192 of file stm3210c_eval_lcd.h.

#define LCD_SPI SPI3

LCD SPI Interface pins.

Definition at line 101 of file stm3210c_eval_lcd.h.

#define LCD_SPI_CLK RCC_APB1Periph_SPI3

Definition at line 102 of file stm3210c_eval_lcd.h.

#define LCD_SPI_MISO_GPIO_CLK RCC_APB2Periph_GPIOC

Definition at line 108 of file stm3210c_eval_lcd.h.

#define LCD_SPI_MISO_GPIO_PORT GPIOC

Definition at line 107 of file stm3210c_eval_lcd.h.

#define LCD_SPI_MISO_PIN GPIO_Pin_11

Definition at line 106 of file stm3210c_eval_lcd.h.

#define LCD_SPI_MOSI_GPIO_CLK RCC_APB2Periph_GPIOC

Definition at line 111 of file stm3210c_eval_lcd.h.

#define LCD_SPI_MOSI_GPIO_PORT GPIOC

Definition at line 110 of file stm3210c_eval_lcd.h.

#define LCD_SPI_MOSI_PIN GPIO_Pin_12

Definition at line 109 of file stm3210c_eval_lcd.h.

#define LCD_SPI_SCK_GPIO_CLK RCC_APB2Periph_GPIOC

Definition at line 105 of file stm3210c_eval_lcd.h.

#define LCD_SPI_SCK_GPIO_PORT GPIOC

Definition at line 104 of file stm3210c_eval_lcd.h.

#define LCD_SPI_SCK_PIN GPIO_Pin_10

Definition at line 103 of file stm3210c_eval_lcd.h.


STM32F10x Standard Peripherals Firmware Library: STM3210C_EVAL_LCD_Exported_Macros

Defines

STM3210C_EVAL_LCD_Exported_Macros

STM3210C_EVAL_LCD

Defines

#define ASSEMBLE_RGB(R, G, B) ((((R)& 0xF8) << 8) | (((G) & 0xFC) << 3) | (((B) & 0xF8) >> 3))

Define Documentation

#define ASSEMBLE_RGB | ( | R,
 |  | G,
 |  | B
 | ) | ((((R)& 0xF8) << 8) | (((G) & 0xFC) << 3) | (((B) & 0xF8) >> 3))

Definition at line 297 of file stm3210c_eval_lcd.h.


STM32F10x Standard Peripherals Firmware Library: STM3210C_EVAL_LCD_Exported_Functions

Functions

STM3210C_EVAL_LCD_Exported_Functions

STM3210C_EVAL_LCD

Functions

void | LCD_Clear (uint16_t Color)
Clears the hole LCD.
void | LCD_ClearLine (uint8_t Line)
Clears the selected line.
void | LCD_ClosedPolyLine (pPoint Points, uint16_t PointCount)
Displays a closed polyline (between many points).
void | LCD_ClosedPolyLineRelative (pPoint Points, uint16_t PointCount)
Displays a closed relative polyline (between many points).
void | LCD_CtrlLinesConfig (void)
Configures LCD control lines in Output Push-Pull mode.
void | LCD_CtrlLinesWrite (GPIO_TypeDef *GPIOx, uint16_t CtrlPins, BitAction BitVal)
Sets or reset LCD control lines.
void | LCD_DeInit (void)
DeInitializes the LCD.
void | LCD_DisplayChar (uint8_t Line, uint16_t Column, uint8_t Ascii)
Displays one character (16dots width, 24dots height).
void | LCD_DisplayOff (void)
Disables the Display.
void | LCD_DisplayOn (void)
Enables the Display.
void | LCD_DisplayStringLine (uint8_t Line, uint8_t *ptr)
Displays a maximum of 20 char on the LCD.
void | LCD_DrawChar (uint8_t Xpos, uint16_t Ypos, const uint16_t *c)
Draws a character on LCD.
void | LCD_DrawCircle (uint8_t Xpos, uint16_t Ypos, uint16_t Radius)
Displays a circle.
void | LCD_DrawFullCircle (uint16_t Xpos, uint16_t Ypos, uint16_t Radius)
Displays a full circle.
void | LCD_DrawFullRect (uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height)
Displays a full rectangle.
void | LCD_DrawLine (uint8_t Xpos, uint16_t Ypos, uint16_t Length, uint8_t Direction)
Displays a line.
void | LCD_DrawMonoPict (const uint32_t *Pict)
Displays a monocolor picture.
void | LCD_DrawRect (uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width)
Displays a rectangle.
void | LCD_DrawUniLine (uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2)
Displays an uni line (between two points).
void | LCD_FillPolyLine (pPoint Points, uint16_t PointCount)
Displays a full polyline (between many points).
void | LCD_GetColors (__IO uint16_t *_TextColor, __IO uint16_t *_BackColor)
Gets the LCD Text and Background colors.
sFONT * | LCD_GetFont (void)
Gets the Text Font.
void | LCD_nCS_StartByte (uint8_t Start_Byte)
Reset LCD control line(/CS) and Send Start-Byte.
void | LCD_PolyLine (pPoint Points, uint16_t PointCount)
Displays an polyline (between many points).
void | LCD_PolyLineRelative (pPoint Points, uint16_t PointCount)
Displays a relative polyline (between many points).
void | LCD_PowerOn (void)
Power on the LCD.
uint16_t | LCD_ReadReg (uint8_t LCD_Reg)
Reads the selected LCD Register.
void | LCD_SetBackColor (__IO uint16_t Color)
Sets the Background color.
void | LCD_SetColors (__IO uint16_t _TextColor, __IO uint16_t _BackColor)
Sets the LCD Text and Background colors.
void | LCD_SetCursor (uint8_t Xpos, uint16_t Ypos)
Sets the cursor position.
void | LCD_SetDisplayWindow (uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width)
Sets a display window.
void | LCD_SetFont (sFONT *fonts)
Sets the Text Font.
void | LCD_SetTextColor (__IO uint16_t Color)
Sets the Text color.
void | LCD_Setup (void)
Setups the LCD.
void | LCD_SPIConfig (void)
Configures the LCD_SPI interface.
void | LCD_WindowModeDisable (void)
Disables LCD Window mode.
void | LCD_WriteRAM (uint16_t RGB_Code)
Writes to the LCD RAM.
void | LCD_WriteRAM_Prepare (void)
Prepare to write to the LCD RAM.
void | LCD_WriteRAMWord (uint16_t RGB_Code)
Writes 1 word to the LCD RAM.
void | LCD_WriteReg (uint8_t LCD_Reg, uint16_t LCD_RegValue)
Writes to the selected LCD register.
void | LCD_WriteRegIndex (uint8_t LCD_Reg)
Writes index to select the LCD register.
void | STM3210C_LCD_Init (void)
Initializes the LCD.

Function Documentation

void LCD_Clear ( uint16_t Color )

Clears the hole LCD.

Parameters:
Color,: the color of the background.
Return values:
None

Definition at line 544 of file stm32100b_eval_lcd.c.

void LCD_ClearLine ( uint8_t Line )

Clears the selected line.

Parameters:
Line,: the Line to be cleared. This parameter can be one of the following values:

  • Linex: where x can be 0..n
Return values:
None

Definition at line 525 of file stm32100b_eval_lcd.c.

void LCD_ClosedPolyLine | ( | pPoint | Points,
 |  | uint16_t | PointCount
 | ) |  |

Displays a closed polyline (between many points).

Parameters:
Points,: pointer to the points array.
PointCount,: Number of points.
Return values:
None

Definition at line 1236 of file stm32100b_eval_lcd.c.

void LCD_ClosedPolyLineRelative | ( | pPoint | Points,
 |  | uint16_t | PointCount
 | ) |  |

Displays a closed relative polyline (between many points).

Parameters:
Points,: pointer to the points array.
PointCount,: Number of points.
Return values:
None

Definition at line 1259 of file stm32100b_eval_lcd.c.

void LCD_CtrlLinesConfig ( void )

Configures LCD control lines in Output Push-Pull mode.

Parameters:
None
Return values:
None Configures LCD control lines in Output Push-Pull mode.
Parameters:
None
Return values:
None

Definition at line 1724 of file stm32100b_eval_lcd.c.

void LCD_CtrlLinesWrite | ( | GPIO_TypeDef * | GPIOx,
 |  | uint16_t | CtrlPins,
 |  | BitAction | BitVal
 | ) |  |

Sets or reset LCD control lines.

Parameters:
GPIOx,: where x can be B or D to select the GPIO peripheral.
CtrlPins,: the Control line. This parameter can be:

  • LCD_NCS_PIN: Chip Select pin
  • LCD_NWR_PIN: Read/Write Selection pin
  • LCD_RS_PIN: Register/RAM Selection pin
BitVal,: specifies the value to be written to the selected bit. This parameter can be:

  • Bit_RESET: to clear the port pin
  • Bit_SET: to set the port pin
Return values:
None
Parameters:
GPIOx,: where x can be B or D to select the GPIO peripheral.
CtrlPins,: the Control line. This parameter can be:

  • LCD_NCS_PIN: Chip Select pin
BitVal,: specifies the value to be written to the selected bit. This parameter can be:

  • Bit_RESET: to clear the port pin
  • Bit_SET: to set the port pin
Return values:
None

Definition at line 1763 of file stm32100b_eval_lcd.c.

void LCD_DeInit ( void )

DeInitializes the LCD.

Parameters:
None
Return values:
None

< LCD Display Off

< LCD_SPI disable

< LCD_SPI DeInit

< Disable SPI clock

< LCD Display Off

< LCD_SPI DeInit

< LCD Display Off

< LCD_SPI disable

< LCD_SPI DeInit

< Disable SPI clock

< LCD Display Off

< LCD_SPI disable

< LCD_SPI DeInit

< Disable SPI clock

< LCD Display Off

< LCD_SPI DeInit

Definition at line 116 of file stm32100b_eval_lcd.c.

void LCD_DisplayChar | ( | uint8_t | Line,
 |  | uint16_t | Column,
 |  | uint8_t | Ascii
 | ) |  |

Displays one character (16dots width, 24dots height).

Parameters:
Line,: the Line where to display the character shape . This parameter can be one of the following values:

  • Linex: where x can be 0..9
Column,: start column address.
Ascii,: character ascii code, must be between 0x20 and 0x7E.
Return values:
None

Definition at line 640 of file stm32100b_eval_lcd.c.

void LCD_DisplayOff ( void )

Disables the Display.

Parameters:
None
Return values:
None

Definition at line 1702 of file stm32100b_eval_lcd.c.

void LCD_DisplayOn ( void )

Enables the Display.

Parameters:
None
Return values:
None

Definition at line 1677 of file stm32100b_eval_lcd.c.

void LCD_DisplayStringLine | ( | uint8_t | Line,
 |  | uint8_t * | ptr
 | ) |  |

Displays a maximum of 20 char on the LCD.

Parameters:
Line,: the Line where to display the character shape . This parameter can be one of the following values:

  • Linex: where x can be 0..9
*ptr,: pointer to string to display on LCD.
Return values:
None

Definition at line 655 of file stm32100b_eval_lcd.c.

void LCD_DrawChar | ( | uint8_t | Xpos,
 |  | uint16_t | Ypos,
 |  | const uint16_t * | c
 | ) |  |

Draws a character on LCD.

Parameters:
Xpos,: the Line where to display the character shape.
Ypos,: start column address.
c,: pointer to the character data.
Return values:
None

Definition at line 593 of file stm32100b_eval_lcd.c.

void LCD_DrawCircle | ( | uint8_t | Xpos,
 |  | uint16_t | Ypos,
 |  | uint16_t | Radius
 | ) |  |

Displays a circle.

Parameters:
Xpos,: specifies the X position.
Ypos,: specifies the Y position.
Radius
Return values:
None

Definition at line 817 of file stm32100b_eval_lcd.c.

void LCD_DrawFullCircle | ( | uint16_t | Xpos,
 |  | uint16_t | Ypos,
 |  | uint16_t | Radius
 | ) |  |

Displays a full circle.

Parameters:
Xpos,: specifies the X position.
Ypos,: specifies the Y position.
Radius
Return values:
None

Definition at line 1057 of file stm32100b_eval_lcd.c.

void LCD_DrawFullRect | ( | uint16_t | Xpos,
 |  | uint16_t | Ypos,
 |  | uint16_t | Width,
 |  | uint16_t | Height
 | ) |  |

Displays a full rectangle.

Parameters:
Xpos,: specifies the X position.
Ypos,: specifies the Y position.
Height,: rectangle height.
Width,: rectangle width.
Return values:
None

Definition at line 1026 of file stm32100b_eval_lcd.c.

void LCD_DrawLine | ( | uint8_t | Xpos,
 |  | uint16_t | Ypos,
 |  | uint16_t | Length,
 |  | uint8_t | Direction
 | ) |  |

Displays a line.

Parameters:
Xpos,: specifies the X position.
Ypos,: specifies the Y position.
Length,: line length.
Direction,: line direction. This parameter can be one of the following values: Vertical or Horizontal.
Return values:
None

Definition at line 753 of file stm32100b_eval_lcd.c.

void LCD_DrawMonoPict ( const uint32_t * Pict )

Displays a monocolor picture.

Parameters:
Pict,: pointer to the picture array.
Return values:
None

Definition at line 926 of file stm32100b_eval_lcd.c.

void LCD_DrawRect | ( | uint8_t | Xpos,
 |  | uint16_t | Ypos,
 |  | uint8_t | Height,
 |  | uint16_t | Width
 | ) |  |

Displays a rectangle.

Parameters:
Xpos,: specifies the X position.
Ypos,: specifies the Y position.
Height,: display rectangle height.
Width,: display rectangle width.
Return values:
None

Definition at line 800 of file stm32100b_eval_lcd.c.

void LCD_DrawUniLine | ( | uint16_t | x1,
 |  | uint16_t | y1,
 |  | uint16_t | x2,
 |  | uint16_t | y2
 | ) |  |

Displays an uni line (between two points).

Parameters:
x1,: specifies the point 1 x position.
y1,: specifies the point 1 y position.
x2,: specifies the point 2 x position.
y2,: specifies the point 2 y position.
Return values:
None

Definition at line 1107 of file stm32100b_eval_lcd.c.

void LCD_FillPolyLine | ( | pPoint | Points,
 |  | uint16_t | PointCount
 | ) |  |

Displays a full polyline (between many points).

Parameters:
Points,: pointer to the points array.
PointCount,: Number of points.
Return values:
None

Definition at line 1271 of file stm32100b_eval_lcd.c.

void LCD_GetColors | ( | __IO uint16_t * | _TextColor,
 |  | __IO uint16_t * | _BackColor
 | ) |  |

Gets the LCD Text and Background colors.

Parameters:
_TextColor,: pointer to the variable that will contain the Text Color.
_BackColor,: pointer to the variable that will contain the Background Color.
Return values:
None

Definition at line 472 of file stm32100b_eval_lcd.c.

sFONT* LCD_GetFont ( void )

Gets the Text Font.

Parameters:
None.
Return values:
the used font.

Definition at line 513 of file stm32100b_eval_lcd.c.

void LCD_nCS_StartByte ( uint8_t Start_Byte )

Reset LCD control line(/CS) and Send Start-Byte.

Parameters:
Start_Byte,: the Start-Byte to be sent
Return values:
None

Definition at line 1377 of file stm32100b_eval_lcd.c.

void LCD_PolyLine | ( | pPoint | Points,
 |  | uint16_t | PointCount
 | ) |  |

Displays an polyline (between many points).

Parameters:
Points,: pointer to the points array.
PointCount,: Number of points.
Return values:
None

Definition at line 1180 of file stm32100b_eval_lcd.c.

void LCD_PolyLineRelative | ( | pPoint | Points,
 |  | uint16_t | PointCount
 | ) |  |

Displays a relative polyline (between many points).

Parameters:
Points,: pointer to the points array.
PointCount,: Number of points.
Return values:
None

Definition at line 1248 of file stm32100b_eval_lcd.c.

void LCD_PowerOn ( void )

Power on the LCD.

Parameters:
None
Return values:
None

Definition at line 1629 of file stm32100b_eval_lcd.c.

uint16_t LCD_ReadReg ( uint8_t LCD_Reg )

Reads the selected LCD Register.

Parameters:
LCD_Reg,: address of the selected register.
Return values:
LCD Register Value.
Parameters:
None
Return values:
LCD Register Value.

Definition at line 1452 of file stm32100b_eval_lcd.c.

void LCD_SetBackColor ( __IO uint16_t Color )

Sets the Background color.

Parameters:
Color,: specifies the Background color code RGB(5-6-5).
Return values:
None

Definition at line 493 of file stm32100b_eval_lcd.c.

void LCD_SetColors | ( | __IO uint16_t | _TextColor,
 |  | __IO uint16_t | _BackColor
 | ) |  |

Sets the LCD Text and Background colors.

Parameters:
_TextColor,: specifies the Text Color.
_BackColor,: specifies the Background Color.
Return values:
None

Definition at line 458 of file stm32100b_eval_lcd.c.

void LCD_SetCursor | ( | uint8_t | Xpos,
 |  | uint16_t | Ypos
 | ) |  |

Sets the cursor position.

Parameters:
Xpos,: specifies the X position.
Ypos,: specifies the Y position.
Return values:
None

Definition at line 570 of file stm32100b_eval_lcd.c.

void LCD_SetDisplayWindow | ( | uint8_t | Xpos,
 |  | uint16_t | Ypos,
 |  | uint8_t | Height,
 |  | uint16_t | Width
 | ) |  |

Sets a display window.

Parameters:
Xpos,: specifies the X buttom left position.
Ypos,: specifies the Y buttom left position.
Height,: display window height.
Width,: display window width.
Return values:
None

Definition at line 680 of file stm32100b_eval_lcd.c.

void LCD_SetFont ( sFONT * fonts )

Sets the Text Font.

Parameters:
fonts,: specifies the font to be used.
Return values:
None

Definition at line 503 of file stm32100b_eval_lcd.c.

void LCD_SetTextColor ( __IO uint16_t Color )

Sets the Text color.

Parameters:
Color,: specifies the Text color code RGB(5-6-5).
Return values:
None

Definition at line 482 of file stm32100b_eval_lcd.c.

void LCD_Setup ( void )

Setups the LCD.

Parameters:
None
Return values:
None

Definition at line 160 of file stm32100b_eval_lcd.c.

void LCD_SPIConfig ( void )

Configures the LCD_SPI interface.

Parameters:
None
Return values:
None

Definition at line 1775 of file stm32100b_eval_lcd.c.

void LCD_WindowModeDisable ( void )

Disables LCD Window mode.

Parameters:
None
Return values:
None

Definition at line 729 of file stm32100b_eval_lcd.c.

void LCD_WriteRAM ( uint16_t RGB_Code )

Writes to the LCD RAM.

Parameters:
RGB_Code,: the pixel color in RGB mode (5-6-5).
Return values:
None

Definition at line 1594 of file stm32100b_eval_lcd.c.

void LCD_WriteRAM_Prepare ( void )

Prepare to write to the LCD RAM.

Parameters:
None
Return values:
None

Definition at line 1518 of file stm32100b_eval_lcd.c.

void LCD_WriteRAMWord ( uint16_t RGB_Code )

Writes 1 word to the LCD RAM.

Parameters:
RGB_Code,: the pixel color in RGB mode (5-6-5).
Return values:
None

Definition at line 1532 of file stm32100b_eval_lcd.c.

void LCD_WriteReg | ( | uint8_t | LCD_Reg,
 |  | uint16_t | LCD_RegValue
 | ) |  |

Writes to the selected LCD register.

Parameters:
LCD_Reg,: address of the selected register.
LCD_RegValue,: value to write to the selected register.
Return values:
None Writes to the selected LCD register.
Parameters:
LCD_Reg,: address of the selected register.
LCD_RegValue,: value to write to the selected register.
Return values:
None

Definition at line 1576 of file stm32100b_eval_lcd.c.

void LCD_WriteRegIndex ( uint8_t LCD_Reg )

Writes index to select the LCD register.

Parameters:
LCD_Reg,: address of the selected register.
Return values:
None

Definition at line 1394 of file stm32100b_eval_lcd.c.

void STM3210C_LCD_Init ( void )

Initializes the LCD.

Parameters:
None
Return values:
None

Definition at line 233 of file stm3210c_eval_lcd.c.

References LCD_DEFAULT_FONT, LCD_SetFont(), and LCD_Setup().

Referenced by main().


STM32F10x Standard Peripherals Firmware Library: STM3210E_EVAL_LOW_LEVEL_Private_TypesDefinitions

STM3210E_EVAL_LOW_LEVEL_Private_TypesDefinitions

STM3210E_EVAL_LOW_LEVEL


STM32F10x Standard Peripherals Firmware Library: STM3210E_EVAL_LOW_LEVEL_Private_Defines

STM3210E_EVAL_LOW_LEVEL_Private_Defines

STM3210E_EVAL_LOW_LEVEL


STM32F10x Standard Peripherals Firmware Library: STM3210E_EVAL_LOW_LEVEL_Private_Macros

STM3210E_EVAL_LOW_LEVEL_Private_Macros

STM3210E_EVAL_LOW_LEVEL


STM32F10x Standard Peripherals Firmware Library: STM3210E_EVAL_LOW_LEVEL_Private_Variables

Variables

STM3210E_EVAL_LOW_LEVEL_Private_Variables

STM3210E_EVAL_LOW_LEVEL

Variables

const uint32_t | BUTTON_CLK [BUTTONn]
const uint16_t | BUTTON_EXTI_LINE [BUTTONn]
const uint16_t | BUTTON_IRQn [BUTTONn]
const uint16_t | BUTTON_PIN [BUTTONn]
const uint16_t | BUTTON_PIN_SOURCE [BUTTONn]
GPIO_TypeDef * | BUTTON_PORT [BUTTONn]
const uint16_t | BUTTON_PORT_SOURCE [BUTTONn]
const uint16_t | COM_RX_PIN [COMn] = {EVAL_COM1_RX_PIN, EVAL_COM2_RX_PIN}
GPIO_TypeDef * | COM_RX_PORT [COMn] = {EVAL_COM1_RX_GPIO_PORT, EVAL_COM2_RX_GPIO_PORT}
const uint32_t | COM_RX_PORT_CLK [COMn] = {EVAL_COM1_RX_GPIO_CLK, EVAL_COM2_RX_GPIO_CLK}
const uint16_t | COM_TX_PIN [COMn] = {EVAL_COM1_TX_PIN, EVAL_COM2_TX_PIN}
GPIO_TypeDef * | COM_TX_PORT [COMn] = {EVAL_COM1_TX_GPIO_PORT, EVAL_COM2_TX_GPIO_PORT}
const uint32_t | COM_TX_PORT_CLK [COMn] = {EVAL_COM1_TX_GPIO_CLK, EVAL_COM2_TX_GPIO_CLK}
USART_TypeDef * | COM_USART [COMn] = {EVAL_COM1, EVAL_COM2}
const uint32_t | COM_USART_CLK [COMn] = {EVAL_COM1_CLK, EVAL_COM2_CLK}
const uint32_t | GPIO_CLK [LEDn]
const uint16_t | GPIO_PIN [LEDn]
GPIO_TypeDef * | GPIO_PORT [LEDn]

Variable Documentation

const uint32_t BUTTON_CLK[BUTTONn]
Initial value:
 {WAKEUP_BUTTON_GPIO_CLK, TAMPER_BUTTON_GPIO_CLK,
                                      KEY_BUTTON_GPIO_CLK, RIGHT_BUTTON_GPIO_CLK,
                                      LEFT_BUTTON_GPIO_CLK, UP_BUTTON_GPIO_CLK,
                                      DOWN_BUTTON_GPIO_CLK, SEL_BUTTON_GPIO_CLK}

Definition at line 97 of file stm3210e_eval.c.

const uint16_t BUTTON_EXTI_LINE[BUTTONn]
Initial value:
 {WAKEUP_BUTTON_EXTI_LINE,
                                            TAMPER_BUTTON_EXTI_LINE,
                                            KEY_BUTTON_EXTI_LINE,
                                            RIGHT_BUTTON_EXTI_LINE,
                                            LEFT_BUTTON_EXTI_LINE,
                                            UP_BUTTON_EXTI_LINE,
                                            DOWN_BUTTON_EXTI_LINE,
                                            SEL_BUTTON_EXTI_LINE}

Definition at line 102 of file stm3210e_eval.c.

const uint16_t BUTTON_IRQn[BUTTONn]
Initial value:
 {WAKEUP_BUTTON_EXTI_IRQn, TAMPER_BUTTON_EXTI_IRQn,
                                       KEY_BUTTON_EXTI_IRQn, RIGHT_BUTTON_EXTI_IRQn,
                                       LEFT_BUTTON_EXTI_IRQn, UP_BUTTON_EXTI_IRQn,
                                       DOWN_BUTTON_EXTI_IRQn, SEL_BUTTON_EXTI_IRQn}

Definition at line 129 of file stm3210e_eval.c.

const uint16_t BUTTON_PIN[BUTTONn]
Initial value:
 {WAKEUP_BUTTON_PIN, TAMPER_BUTTON_PIN,
                                      KEY_BUTTON_PIN, RIGHT_BUTTON_PIN,
                                      LEFT_BUTTON_PIN, UP_BUTTON_PIN,
                                      DOWN_BUTTON_PIN, SEL_BUTTON_PIN}

Definition at line 92 of file stm3210e_eval.c.

const uint16_t BUTTON_PIN_SOURCE[BUTTONn]
Initial value:
 {WAKEUP_BUTTON_EXTI_PIN_SOURCE,
                                             TAMPER_BUTTON_EXTI_PIN_SOURCE,
                                             KEY_BUTTON_EXTI_PIN_SOURCE,
                                             RIGHT_BUTTON_EXTI_PIN_SOURCE,
                                             LEFT_BUTTON_EXTI_PIN_SOURCE,
                                             UP_BUTTON_EXTI_PIN_SOURCE,
                                             DOWN_BUTTON_EXTI_PIN_SOURCE,
                                             SEL_BUTTON_EXTI_PIN_SOURCE}

Definition at line 120 of file stm3210e_eval.c.

GPIO_TypeDef* BUTTON_PORT[BUTTONn]
Initial value:
 {WAKEUP_BUTTON_GPIO_PORT, TAMPER_BUTTON_GPIO_PORT,
                                      KEY_BUTTON_GPIO_PORT, RIGHT_BUTTON_GPIO_PORT,
                                      LEFT_BUTTON_GPIO_PORT, UP_BUTTON_GPIO_PORT,
                                      DOWN_BUTTON_GPIO_PORT, SEL_BUTTON_GPIO_PORT}

Definition at line 87 of file stm3210e_eval.c.

const uint16_t BUTTON_PORT_SOURCE[BUTTONn]
Initial value:
 {WAKEUP_BUTTON_EXTI_PORT_SOURCE,
                                              TAMPER_BUTTON_EXTI_PORT_SOURCE,
                                              KEY_BUTTON_EXTI_PORT_SOURCE,
                                              RIGHT_BUTTON_EXTI_PORT_SOURCE,
                                              LEFT_BUTTON_EXTI_PORT_SOURCE,
                                              UP_BUTTON_EXTI_PORT_SOURCE,
                                              DOWN_BUTTON_EXTI_PORT_SOURCE,
                                              SEL_BUTTON_EXTI_PORT_SOURCE}

Definition at line 111 of file stm3210e_eval.c.

const uint16_t COM_RX_PIN[COMn] = {EVAL_COM1_RX_PIN, EVAL_COM2_RX_PIN}

Definition at line 148 of file stm3210e_eval.c.

GPIO_TypeDef* COM_RX_PORT[COMn] = {EVAL_COM1_RX_GPIO_PORT, EVAL_COM2_RX_GPIO_PORT}

Definition at line 138 of file stm3210e_eval.c.

const uint32_t COM_RX_PORT_CLK[COMn] = {EVAL_COM1_RX_GPIO_CLK, EVAL_COM2_RX_GPIO_CLK}

Definition at line 144 of file stm3210e_eval.c.

const uint16_t COM_TX_PIN[COMn] = {EVAL_COM1_TX_PIN, EVAL_COM2_TX_PIN}

Definition at line 146 of file stm3210e_eval.c.

GPIO_TypeDef* COM_TX_PORT[COMn] = {EVAL_COM1_TX_GPIO_PORT, EVAL_COM2_TX_GPIO_PORT}

Definition at line 136 of file stm3210e_eval.c.

const uint32_t COM_TX_PORT_CLK[COMn] = {EVAL_COM1_TX_GPIO_CLK, EVAL_COM2_TX_GPIO_CLK}

Definition at line 142 of file stm3210e_eval.c.

USART_TypeDef* COM_USART[COMn] = {EVAL_COM1, EVAL_COM2}

Definition at line 134 of file stm3210e_eval.c.

const uint32_t COM_USART_CLK[COMn] = {EVAL_COM1_CLK, EVAL_COM2_CLK}

Definition at line 140 of file stm3210e_eval.c.

const uint32_t GPIO_CLK[LEDn]
Initial value:
 {LED1_GPIO_CLK, LED2_GPIO_CLK, LED3_GPIO_CLK,
                                 LED4_GPIO_CLK}

Definition at line 84 of file stm3210e_eval.c.

const uint16_t GPIO_PIN[LEDn]
Initial value:
 {LED1_PIN, LED2_PIN, LED3_PIN,
                                 LED4_PIN}

Definition at line 82 of file stm3210e_eval.c.

GPIO_TypeDef* GPIO_PORT[LEDn]
Initial value:
 {LED1_GPIO_PORT, LED2_GPIO_PORT, LED3_GPIO_PORT,
                                 LED4_GPIO_PORT}

Definition at line 80 of file stm3210e_eval.c.


STM32F10x Standard Peripherals Firmware Library: STM3210E_EVAL_LOW_LEVEL_Private_FunctionPrototypes

STM3210E_EVAL_LOW_LEVEL_Private_FunctionPrototypes

STM3210E_EVAL_LOW_LEVEL


STM32F10x Standard Peripherals Firmware Library: STM3210E_EVAL_LOW_LEVEL_Private_Functions

Functions

STM3210E_EVAL_LOW_LEVEL_Private_Functions

STM3210E_EVAL_LOW_LEVEL

Functions

void | LM75_LowLevel_DeInit (void)
DeInitializes the LM75_I2C.
void | LM75_LowLevel_Init (void)
Initializes the LM75_I2C.
uint32_t | SD_DMAEndOfTransferStatus (void)
Returns the DMA End Of Transfer Status.
void | SD_LowLevel_DeInit (void)
DeInitializes the SDIO interface.
void | SD_LowLevel_DMA_RxConfig (uint32_t *BufferDST, uint32_t BufferSize)
Configures the DMA2 Channel4 for SDIO Rx request.
void | SD_LowLevel_DMA_TxConfig (uint32_t *BufferSRC, uint32_t BufferSize)
Configures the DMA2 Channel4 for SDIO Tx request.
void | SD_LowLevel_Init (void)
Initializes the SD Card and put it into StandBy State (Ready for data transfer).
void | sFLASH_LowLevel_DeInit (void)
DeInitializes the peripherals used by the SPI FLASH driver.
void | sFLASH_LowLevel_Init (void)
Initializes the peripherals used by the SPI FLASH driver.
void | STM_EVAL_COMInit (COM_TypeDef COM, USART_InitTypeDef *USART_InitStruct)
Configures COM port.
void | STM_EVAL_LEDInit (Led_TypeDef Led)
Configures LED GPIO.
void | STM_EVAL_LEDOff (Led_TypeDef Led)
Turns selected LED Off.
void | STM_EVAL_LEDOn (Led_TypeDef Led)
Turns selected LED On.
void | STM_EVAL_LEDToggle (Led_TypeDef Led)
Toggles the selected LED.
uint32_t | STM_EVAL_PBGetState (Button_TypeDef Button)
Returns the selected Button state.
void | STM_EVAL_PBInit (Button_TypeDef Button, ButtonMode_TypeDef Button_Mode)
Configures Button GPIO and EXTI Line.

Function Documentation

void LM75_LowLevel_DeInit ( void )

DeInitializes the LM75_I2C.

Parameters:
None
Return values:
None

< Disable LM75_I2C

< DeInitializes the LM75_I2C

< LM75_I2C Periph clock disable

< Configure LM75_I2C pins: SCL

< Configure LM75_I2C pins: SDA

< Configure LM75_I2C pin: SMBUS ALERT

Definition at line 588 of file stm3210e_eval.c.

References DISABLE, GPIO_Init(), GPIO_InitStructure, GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_IN_FLOATING, GPIO_InitTypeDef::GPIO_Pin, I2C_Cmd(), I2C_DeInit(), LM75_I2C, LM75_I2C_CLK, LM75_I2C_SCL_GPIO_PORT, LM75_I2C_SCL_PIN, LM75_I2C_SDA_GPIO_PORT, LM75_I2C_SDA_PIN, LM75_I2C_SMBUSALERT_GPIO_PORT, LM75_I2C_SMBUSALERT_PIN, and RCC_APB1PeriphClockCmd().

void LM75_LowLevel_Init ( void )

Initializes the LM75_I2C.

Parameters:
None
Return values:
None

< LM75_I2C Periph clock enable

< LM75_I2C_SCL_GPIO_CLK, LM75_I2C_SDA_GPIO_CLK and LM75_I2C_SMBUSALERT_GPIO_CLK Periph clock enable

< Configure LM75_I2C pins: SCL

< Configure LM75_I2C pins: SDA

< Configure LM75_I2C pin: SMBUS ALERT

Definition at line 619 of file stm3210e_eval.c.

References ENABLE, GPIO_Init(), GPIO_InitStructure, GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_AF_OD, GPIO_Mode_IPU, GPIO_InitTypeDef::GPIO_Pin, GPIO_InitTypeDef::GPIO_Speed, GPIO_Speed_50MHz, LM75_I2C_CLK, LM75_I2C_SCL_GPIO_CLK, LM75_I2C_SCL_GPIO_PORT, LM75_I2C_SCL_PIN, LM75_I2C_SDA_GPIO_CLK, LM75_I2C_SDA_GPIO_PORT, LM75_I2C_SDA_PIN, LM75_I2C_SMBUSALERT_GPIO_CLK, LM75_I2C_SMBUSALERT_GPIO_PORT, LM75_I2C_SMBUSALERT_PIN, RCC_APB1PeriphClockCmd(), and RCC_APB2PeriphClockCmd().

uint32_t SD_DMAEndOfTransferStatus ( void )

Returns the DMA End Of Transfer Status.

Parameters:
None
Return values:
DMA SDIO Channel Status.

Definition at line 504 of file stm3210e_eval.c.

References DMA2_FLAG_TC4, and DMA_GetFlagStatus().

Referenced by SD_WaitReadOperation(), and SD_WaitWriteOperation().

void SD_LowLevel_DeInit ( void )

DeInitializes the SDIO interface.

DeInitializes the SD/SD communication.

Parameters:
None
Return values:
None

< Disable SDIO Clock

< Set Power State to OFF

< DeInitializes the SDIO peripheral

< Disable the SDIO AHB Clock

< Configure PC.08, PC.09, PC.10, PC.11, PC.12 pin: D0, D1, D2, D3, CLK pin

< Configure PD.02 CMD line

Definition at line 371 of file stm3210e_eval.c.

References DISABLE, GPIO_Init(), GPIO_InitStructure, GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_IN_FLOATING, GPIO_InitTypeDef::GPIO_Pin, GPIO_Pin_10, GPIO_Pin_11, GPIO_Pin_12, GPIO_Pin_2, GPIO_Pin_8, GPIO_Pin_9, GPIOC, GPIOD, RCC_AHBPeriph_SDIO, RCC_AHBPeriphClockCmd(), SDIO_ClockCmd(), SDIO_DeInit(), SDIO_PowerState_OFF, and SDIO_SetPowerState().

void SD_LowLevel_DMA_RxConfig | ( | uint32_t * | BufferDST,
 |  | uint32_t | BufferSize
 | ) |  |

Configures the DMA2 Channel4 for SDIO Rx request.

Parameters:
BufferDST,: pointer to the destination buffer
BufferSize,: buffer size
Return values:
None

< DMA2 Channel4 disable

< DMA2 Channel4 Config

< DMA2 Channel4 enable

Definition at line 472 of file stm3210e_eval.c.

References DISABLE, DMA2_Channel4, DMA2_FLAG_GL4, DMA2_FLAG_HT4, DMA2_FLAG_TC4, DMA2_FLAG_TE4, DMA_InitTypeDef::DMA_BufferSize, DMA_ClearFlag(), DMA_Cmd(), DMA_InitTypeDef::DMA_DIR, DMA_DIR_PeripheralSRC, DMA_Init(), DMA_InitStructure, DMA_InitTypeDef::DMA_M2M, DMA_M2M_Disable, DMA_InitTypeDef::DMA_MemoryBaseAddr, DMA_InitTypeDef::DMA_MemoryDataSize, DMA_MemoryDataSize_Word, DMA_InitTypeDef::DMA_MemoryInc, DMA_MemoryInc_Enable, DMA_InitTypeDef::DMA_Mode, DMA_Mode_Normal, DMA_InitTypeDef::DMA_PeripheralBaseAddr, DMA_InitTypeDef::DMA_PeripheralDataSize, DMA_PeripheralDataSize_Word, DMA_InitTypeDef::DMA_PeripheralInc, DMA_PeripheralInc_Disable, DMA_InitTypeDef::DMA_Priority, DMA_Priority_High, ENABLE, and SDIO_FIFO_ADDRESS.

Referenced by SD_ReadBlock(), and SD_ReadMultiBlocks().

void SD_LowLevel_DMA_TxConfig | ( | uint32_t * | BufferSRC,
 |  | uint32_t | BufferSize
 | ) |  |

Configures the DMA2 Channel4 for SDIO Tx request.

Parameters:
BufferSRC,: pointer to the source buffer
BufferSize,: buffer size
Return values:
None

< DMA2 Channel4 disable

< DMA2 Channel4 Config

< DMA2 Channel4 enable

Definition at line 438 of file stm3210e_eval.c.

References DISABLE, DMA2_Channel4, DMA2_FLAG_GL4, DMA2_FLAG_HT4, DMA2_FLAG_TC4, DMA2_FLAG_TE4, DMA_InitTypeDef::DMA_BufferSize, DMA_ClearFlag(), DMA_Cmd(), DMA_InitTypeDef::DMA_DIR, DMA_DIR_PeripheralDST, DMA_Init(), DMA_InitStructure, DMA_InitTypeDef::DMA_M2M, DMA_M2M_Disable, DMA_InitTypeDef::DMA_MemoryBaseAddr, DMA_InitTypeDef::DMA_MemoryDataSize, DMA_MemoryDataSize_Word, DMA_InitTypeDef::DMA_MemoryInc, DMA_MemoryInc_Enable, DMA_InitTypeDef::DMA_Mode, DMA_Mode_Normal, DMA_InitTypeDef::DMA_PeripheralBaseAddr, DMA_InitTypeDef::DMA_PeripheralDataSize, DMA_PeripheralDataSize_Word, DMA_InitTypeDef::DMA_PeripheralInc, DMA_PeripheralInc_Disable, DMA_InitTypeDef::DMA_Priority, DMA_Priority_High, ENABLE, and SDIO_FIFO_ADDRESS.

Referenced by SD_WriteBlock(), and SD_WriteMultiBlocks().

void SD_LowLevel_Init ( void )

Initializes the SD Card and put it into StandBy State (Ready for data transfer).

Initializes the SD_SPI and CS pins.

Parameters:
None
Return values:
None

< GPIOC and GPIOD Periph clock enable

< Configure PC.08, PC.09, PC.10, PC.11, PC.12 pin: D0, D1, D2, D3, CLK pin

< Configure PD.02 CMD line

< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin

< Enable the SDIO AHB Clock

< Enable the DMA2 Clock

Definition at line 403 of file stm3210e_eval.c.

References ENABLE, GPIO_Init(), GPIO_InitStructure, GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_AF_PP, GPIO_Mode_IPU, GPIO_InitTypeDef::GPIO_Pin, GPIO_Pin_10, GPIO_Pin_11, GPIO_Pin_12, GPIO_Pin_2, GPIO_Pin_8, GPIO_Pin_9, GPIO_InitTypeDef::GPIO_Speed, GPIO_Speed_50MHz, GPIOC, GPIOD, RCC_AHBPeriph_DMA2, RCC_AHBPeriph_SDIO, RCC_AHBPeriphClockCmd(), RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2PeriphClockCmd(), SD_DETECT_GPIO_CLK, SD_DETECT_GPIO_PORT, and SD_DETECT_PIN.

void sFLASH_LowLevel_DeInit ( void )

DeInitializes the peripherals used by the SPI FLASH driver.

Parameters:
None
Return values:
None

< Disable the sFLASH_SPI

< DeInitializes the sFLASH_SPI

< sFLASH_SPI Periph clock disable

< Configure sFLASH_SPI pins: SCK

< Configure sFLASH_SPI pins: MISO

< Configure sFLASH_SPI pins: MOSI

< Configure sFLASH_CS_PIN pin: sFLASH Card CS pin

Definition at line 514 of file stm3210e_eval.c.

References DISABLE, GPIO_Init(), GPIO_InitStructure, GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_IN_FLOATING, GPIO_InitTypeDef::GPIO_Pin, RCC_APB2PeriphClockCmd(), sFLASH_CS_GPIO_PORT, sFLASH_CS_PIN, sFLASH_SPI, sFLASH_SPI_CLK, sFLASH_SPI_MISO_GPIO_PORT, sFLASH_SPI_MISO_PIN, sFLASH_SPI_MOSI_GPIO_PORT, sFLASH_SPI_MOSI_PIN, sFLASH_SPI_SCK_GPIO_PORT, sFLASH_SPI_SCK_PIN, SPI_Cmd(), and SPI_I2S_DeInit().

void sFLASH_LowLevel_Init ( void )

Initializes the peripherals used by the SPI FLASH driver.

Parameters:
None
Return values:
None

< sFLASH_SPI_CS_GPIO, sFLASH_SPI_MOSI_GPIO, sFLASH_SPI_MISO_GPIO and sFLASH_SPI_SCK_GPIO Periph clock enable

< sFLASH_SPI Periph clock enable

< Configure sFLASH_SPI pins: SCK

< Configure sFLASH_SPI pins: MOSI

< Configure sFLASH_SPI pins: MISO

< Configure sFLASH_CS_PIN pin: sFLASH Card CS pin

Definition at line 550 of file stm3210e_eval.c.

References ENABLE, GPIO_Init(), GPIO_InitStructure, GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_AF_PP, GPIO_Mode_IN_FLOATING, GPIO_Mode_Out_PP, GPIO_InitTypeDef::GPIO_Pin, GPIO_InitTypeDef::GPIO_Speed, GPIO_Speed_50MHz, RCC_APB2PeriphClockCmd(), sFLASH_CS_GPIO_CLK, sFLASH_CS_GPIO_PORT, sFLASH_CS_PIN, sFLASH_SPI_CLK, sFLASH_SPI_MISO_GPIO_CLK, sFLASH_SPI_MISO_GPIO_PORT, sFLASH_SPI_MISO_PIN, sFLASH_SPI_MOSI_GPIO_CLK, sFLASH_SPI_MOSI_GPIO_PORT, sFLASH_SPI_MOSI_PIN, sFLASH_SPI_SCK_GPIO_CLK, sFLASH_SPI_SCK_GPIO_PORT, and sFLASH_SPI_SCK_PIN.

void STM_EVAL_COMInit | ( | COM_TypeDef | COM,
 |  | USART_InitTypeDef * | USART_InitStruct
 | ) |  |

Configures COM port.

Parameters:
COM,: Specifies the COM port to be configured. This parameter can be one of following parameters:

  • COM1
  • COM2
USART_InitStruct,: pointer to a USART_InitTypeDef structure that contains the configuration information for the specified USART peripheral.
Return values:
None

Definition at line 331 of file stm3210e_eval.c.

References COM1, COM_RX_PIN, COM_RX_PORT_CLK, COM_TX_PIN, COM_TX_PORT_CLK, COM_USART_CLK, ENABLE, GPIO_Init(), GPIO_InitStructure, GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_AF_PP, GPIO_Mode_IN_FLOATING, GPIO_InitTypeDef::GPIO_Pin, GPIO_InitTypeDef::GPIO_Speed, GPIO_Speed_50MHz, RCC_APB1PeriphClockCmd(), RCC_APB2Periph_AFIO, RCC_APB2PeriphClockCmd(), USART_Cmd(), and USART_Init().

void STM_EVAL_LEDInit ( Led_TypeDef Led )

Configures LED GPIO.

Parameters:
Led,: Specifies the Led to be configured. This parameter can be one of following parameters:

  • LED1
  • LED2
  • LED3
  • LED4
Return values:
None

Definition at line 178 of file stm3210e_eval.c.

References ENABLE, GPIO_CLK, GPIO_Init(), GPIO_InitStructure, GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_Out_PP, GPIO_PIN, GPIO_InitTypeDef::GPIO_Pin, GPIO_InitTypeDef::GPIO_Speed, GPIO_Speed_50MHz, and RCC_APB2PeriphClockCmd().

void STM_EVAL_LEDOff ( Led_TypeDef Led )

Turns selected LED Off.

Parameters:
Led,: Specifies the Led to be set off. This parameter can be one of following parameters:

  • LED1
  • LED2
  • LED3
  • LED4
Return values:
None

Definition at line 218 of file stm3210e_eval.c.

References GPIO_TypeDef::BRR, and GPIO_PIN.

void STM_EVAL_LEDOn ( Led_TypeDef Led )

Turns selected LED On.

Parameters:
Led,: Specifies the Led to be set on. This parameter can be one of following parameters:

  • LED1
  • LED2
  • LED3
  • LED4
Return values:
None

Definition at line 203 of file stm3210e_eval.c.

References GPIO_TypeDef::BSRR, and GPIO_PIN.

void STM_EVAL_LEDToggle ( Led_TypeDef Led )

Toggles the selected LED.

Parameters:
Led,: Specifies the Led to be toggled. This parameter can be one of following parameters:

  • LED1
  • LED2
  • LED3
  • LED4
Return values:
None

Definition at line 233 of file stm3210e_eval.c.

References GPIO_PIN, and GPIO_TypeDef::ODR.

uint32_t STM_EVAL_PBGetState ( Button_TypeDef Button )

Returns the selected Button state.

Parameters:
Button,: Specifies the Button to be checked. This parameter can be one of following parameters:

  • BUTTON_WAKEUP: Wakeup Push Button
  • BUTTON_TAMPER: Tamper Push Button
  • BUTTON_KEY: Key Push Button
  • BUTTON_RIGHT: Joystick Right Push Button
  • BUTTON_LEFT: Joystick Left Push Button
  • BUTTON_UP: Joystick Up Push Button
  • BUTTON_DOWN: Joystick Down Push Button
  • BUTTON_SEL: Joystick Sel Push Button
Return values:
The Button GPIO pin value.

Definition at line 316 of file stm3210e_eval.c.

References BUTTON_PIN, and GPIO_ReadInputDataBit().

void STM_EVAL_PBInit | ( | Button_TypeDef | Button,
 |  | ButtonMode_TypeDef | Button_Mode
 | ) |  |

Configures Button GPIO and EXTI Line.

Parameters:
Button,: Specifies the Button to be configured. This parameter can be one of following parameters:

  • BUTTON_WAKEUP: Wakeup Push Button
  • BUTTON_TAMPER: Tamper Push Button
  • BUTTON_KEY: Key Push Button
  • BUTTON_RIGHT: Joystick Right Push Button
  • BUTTON_LEFT: Joystick Left Push Button
  • BUTTON_UP: Joystick Up Push Button
  • BUTTON_DOWN: Joystick Down Push Button
  • BUTTON_SEL: Joystick Sel Push Button
Button_Mode,: Specifies Button mode. This parameter can be one of following parameters:

  • BUTTON_MODE_GPIO: Button will be used as simple IO
  • BUTTON_MODE_EXTI: Button will be connected to EXTI line with interrupt generation capability
Return values:
None

Definition at line 257 of file stm3210e_eval.c.

References BUTTON_CLK, BUTTON_EXTI_LINE, BUTTON_IRQn, BUTTON_MODE_EXTI, BUTTON_PIN, BUTTON_PIN_SOURCE, BUTTON_PORT_SOURCE, BUTTON_WAKEUP, ENABLE, EXTI_Init(), EXTI_InitStructure, EXTI_InitTypeDef::EXTI_Line, EXTI_InitTypeDef::EXTI_LineCmd, EXTI_InitTypeDef::EXTI_Mode, EXTI_Mode_Interrupt, EXTI_InitTypeDef::EXTI_Trigger, EXTI_Trigger_Falling, EXTI_Trigger_Rising, GPIO_EXTILineConfig(), GPIO_Init(), GPIO_InitStructure, GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_IN_FLOATING, GPIO_InitTypeDef::GPIO_Pin, NVIC_Init(), NVIC_InitStructure, NVIC_InitTypeDef::NVIC_IRQChannel, NVIC_InitTypeDef::NVIC_IRQChannelCmd, NVIC_InitTypeDef::NVIC_IRQChannelPreemptionPriority, NVIC_InitTypeDef::NVIC_IRQChannelSubPriority, RCC_APB2Periph_AFIO, and RCC_APB2PeriphClockCmd().


STM32F10x Standard Peripherals Firmware Library: STM3210E_EVAL_LOW_LEVEL_Exported_Types

STM3210E_EVAL_LOW_LEVEL_Exported_Types

STM3210E_EVAL_LOW_LEVEL


STM32F10x Standard Peripherals Firmware Library: STM3210E_EVAL_LOW_LEVEL_LED

Defines

STM3210E_EVAL_LOW_LEVEL_LED

STM3210E_EVAL_LOW_LEVEL_Exported_Constants

Defines

#define | LED1_GPIO_CLK RCC_APB2Periph_GPIOF
#define | LED1_GPIO_PORT GPIOF
#define | LED1_PIN GPIO_Pin_6
#define | LED2_GPIO_CLK RCC_APB2Periph_GPIOF
#define | LED2_GPIO_PORT GPIOF
#define | LED2_PIN GPIO_Pin_7
#define | LED3_GPIO_CLK RCC_APB2Periph_GPIOF
#define | LED3_GPIO_PORT GPIOF
#define | LED3_PIN GPIO_Pin_8
#define | LED4_GPIO_CLK RCC_APB2Periph_GPIOF
#define | LED4_GPIO_PORT GPIOF
#define | LED4_PIN GPIO_Pin_9
#define | LEDn 4

Define Documentation

#define LED1_GPIO_CLK RCC_APB2Periph_GPIOF

Definition at line 68 of file stm3210e_eval.h.

#define LED1_GPIO_PORT GPIOF

Definition at line 67 of file stm3210e_eval.h.

#define LED1_PIN GPIO_Pin_6

Definition at line 66 of file stm3210e_eval.h.

#define LED2_GPIO_CLK RCC_APB2Periph_GPIOF

Definition at line 72 of file stm3210e_eval.h.

#define LED2_GPIO_PORT GPIOF

Definition at line 71 of file stm3210e_eval.h.

#define LED2_PIN GPIO_Pin_7

Definition at line 70 of file stm3210e_eval.h.

#define LED3_GPIO_CLK RCC_APB2Periph_GPIOF

Definition at line 76 of file stm3210e_eval.h.

#define LED3_GPIO_PORT GPIOF

Definition at line 75 of file stm3210e_eval.h.

#define LED3_PIN GPIO_Pin_8

Definition at line 74 of file stm3210e_eval.h.

#define LED4_GPIO_CLK RCC_APB2Periph_GPIOF

Definition at line 80 of file stm3210e_eval.h.

#define LED4_GPIO_PORT GPIOF

Definition at line 79 of file stm3210e_eval.h.

#define LED4_PIN GPIO_Pin_9

Definition at line 78 of file stm3210e_eval.h.

#define LEDn 4

Definition at line 64 of file stm3210e_eval.h.


STM32F10x Standard Peripherals Firmware Library: STM3210E_EVAL_LOW_LEVEL_BUTTON

Defines

STM3210E_EVAL_LOW_LEVEL_BUTTON

STM3210E_EVAL_LOW_LEVEL_Exported_Constants

Defines

#define | BUTTONn 8
#define | DOWN_BUTTON_EXTI_IRQn EXTI3_IRQn
#define | DOWN_BUTTON_EXTI_LINE EXTI_Line3
#define | DOWN_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource3
#define | DOWN_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOD
#define | DOWN_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOD
#define | DOWN_BUTTON_GPIO_PORT GPIOD
#define | DOWN_BUTTON_PIN GPIO_Pin_3
Joystick Down push-button.
#define | KEY_BUTTON_EXTI_IRQn EXTI9_5_IRQn
#define | KEY_BUTTON_EXTI_LINE EXTI_Line8
#define | KEY_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource8
#define | KEY_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOG
#define | KEY_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOG
#define | KEY_BUTTON_GPIO_PORT GPIOG
#define | KEY_BUTTON_PIN GPIO_Pin_8
Key push-button.
#define | LEFT_BUTTON_EXTI_IRQn EXTI15_10_IRQn
#define | LEFT_BUTTON_EXTI_LINE EXTI_Line14
#define | LEFT_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource14
#define | LEFT_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOG
#define | LEFT_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOG
#define | LEFT_BUTTON_GPIO_PORT GPIOG
#define | LEFT_BUTTON_PIN GPIO_Pin_14
Joystick Left push-button.
#define | RIGHT_BUTTON_EXTI_IRQn EXTI15_10_IRQn
#define | RIGHT_BUTTON_EXTI_LINE EXTI_Line13
#define | RIGHT_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource13
#define | RIGHT_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOG
#define | RIGHT_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOG
#define | RIGHT_BUTTON_GPIO_PORT GPIOG
#define | RIGHT_BUTTON_PIN GPIO_Pin_13
Joystick Right push-button.
#define | SEL_BUTTON_EXTI_IRQn EXTI9_5_IRQn
#define | SEL_BUTTON_EXTI_LINE EXTI_Line7
#define | SEL_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource7
#define | SEL_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOG
#define | SEL_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOG
#define | SEL_BUTTON_GPIO_PORT GPIOG
#define | SEL_BUTTON_PIN GPIO_Pin_7
Joystick Sel push-button.
#define | TAMPER_BUTTON_EXTI_IRQn EXTI15_10_IRQn
#define | TAMPER_BUTTON_EXTI_LINE EXTI_Line13
#define | TAMPER_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource13
#define | TAMPER_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOC
#define | TAMPER_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOC
#define | TAMPER_BUTTON_GPIO_PORT GPIOC
#define | TAMPER_BUTTON_PIN GPIO_Pin_13
Tamper push-button.
#define | UP_BUTTON_EXTI_IRQn EXTI15_10_IRQn
#define | UP_BUTTON_EXTI_LINE EXTI_Line15
#define | UP_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource15
#define | UP_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOG
#define | UP_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOG
#define | UP_BUTTON_GPIO_PORT GPIOG
#define | UP_BUTTON_PIN GPIO_Pin_15
Joystick Up push-button.
#define | WAKEUP_BUTTON_EXTI_IRQn EXTI0_IRQn
#define | WAKEUP_BUTTON_EXTI_LINE EXTI_Line0
#define | WAKEUP_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource0
#define | WAKEUP_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOA
#define | WAKEUP_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOA
#define | WAKEUP_BUTTON_GPIO_PORT GPIOA
#define | WAKEUP_BUTTON_PIN GPIO_Pin_0
Wakeup push-button.

Define Documentation

#define BUTTONn 8

Definition at line 89 of file stm3210e_eval.h.

#define DOWN_BUTTON_EXTI_IRQn EXTI3_IRQn

Definition at line 160 of file stm3210e_eval.h.

#define DOWN_BUTTON_EXTI_LINE EXTI_Line3

Definition at line 157 of file stm3210e_eval.h.

#define DOWN_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource3

Definition at line 159 of file stm3210e_eval.h.

#define DOWN_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOD

Definition at line 158 of file stm3210e_eval.h.

#define DOWN_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOD

Definition at line 156 of file stm3210e_eval.h.

#define DOWN_BUTTON_GPIO_PORT GPIOD

Definition at line 155 of file stm3210e_eval.h.

#define DOWN_BUTTON_PIN GPIO_Pin_3

Joystick Down push-button.

Definition at line 154 of file stm3210e_eval.h.

#define KEY_BUTTON_EXTI_IRQn EXTI9_5_IRQn

Definition at line 120 of file stm3210e_eval.h.

#define KEY_BUTTON_EXTI_LINE EXTI_Line8

Definition at line 117 of file stm3210e_eval.h.

#define KEY_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource8

Definition at line 119 of file stm3210e_eval.h.

#define KEY_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOG

Definition at line 118 of file stm3210e_eval.h.

#define KEY_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOG

Definition at line 116 of file stm3210e_eval.h.

#define KEY_BUTTON_GPIO_PORT GPIOG

Definition at line 115 of file stm3210e_eval.h.

#define KEY_BUTTON_PIN GPIO_Pin_8

Key push-button.

Definition at line 114 of file stm3210e_eval.h.

#define LEFT_BUTTON_EXTI_IRQn EXTI15_10_IRQn

Definition at line 140 of file stm3210e_eval.h.

#define LEFT_BUTTON_EXTI_LINE EXTI_Line14

Definition at line 137 of file stm3210e_eval.h.

#define LEFT_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource14

Definition at line 139 of file stm3210e_eval.h.

#define LEFT_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOG

Definition at line 138 of file stm3210e_eval.h.

#define LEFT_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOG

Definition at line 136 of file stm3210e_eval.h.

#define LEFT_BUTTON_GPIO_PORT GPIOG

Definition at line 135 of file stm3210e_eval.h.

#define LEFT_BUTTON_PIN GPIO_Pin_14

Joystick Left push-button.

Definition at line 134 of file stm3210e_eval.h.

#define RIGHT_BUTTON_EXTI_IRQn EXTI15_10_IRQn

Definition at line 130 of file stm3210e_eval.h.

#define RIGHT_BUTTON_EXTI_LINE EXTI_Line13

Definition at line 127 of file stm3210e_eval.h.

#define RIGHT_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource13

Definition at line 129 of file stm3210e_eval.h.

#define RIGHT_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOG

Definition at line 128 of file stm3210e_eval.h.

#define RIGHT_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOG

Definition at line 126 of file stm3210e_eval.h.

#define RIGHT_BUTTON_GPIO_PORT GPIOG

Definition at line 125 of file stm3210e_eval.h.

#define RIGHT_BUTTON_PIN GPIO_Pin_13

Joystick Right push-button.

Definition at line 124 of file stm3210e_eval.h.

#define SEL_BUTTON_EXTI_IRQn EXTI9_5_IRQn

Definition at line 170 of file stm3210e_eval.h.

#define SEL_BUTTON_EXTI_LINE EXTI_Line7

Definition at line 167 of file stm3210e_eval.h.

#define SEL_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource7

Definition at line 169 of file stm3210e_eval.h.

#define SEL_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOG

Definition at line 168 of file stm3210e_eval.h.

#define SEL_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOG

Definition at line 166 of file stm3210e_eval.h.

#define SEL_BUTTON_GPIO_PORT GPIOG

Definition at line 165 of file stm3210e_eval.h.

#define SEL_BUTTON_PIN GPIO_Pin_7

Joystick Sel push-button.

Definition at line 164 of file stm3210e_eval.h.

#define TAMPER_BUTTON_EXTI_IRQn EXTI15_10_IRQn

Definition at line 110 of file stm3210e_eval.h.

#define TAMPER_BUTTON_EXTI_LINE EXTI_Line13

Definition at line 107 of file stm3210e_eval.h.

#define TAMPER_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource13

Definition at line 109 of file stm3210e_eval.h.

#define TAMPER_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOC

Definition at line 108 of file stm3210e_eval.h.

#define TAMPER_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOC

Definition at line 106 of file stm3210e_eval.h.

#define TAMPER_BUTTON_GPIO_PORT GPIOC

Definition at line 105 of file stm3210e_eval.h.

#define TAMPER_BUTTON_PIN GPIO_Pin_13

Tamper push-button.

Definition at line 104 of file stm3210e_eval.h.

#define UP_BUTTON_EXTI_IRQn EXTI15_10_IRQn

Definition at line 150 of file stm3210e_eval.h.

#define UP_BUTTON_EXTI_LINE EXTI_Line15

Definition at line 147 of file stm3210e_eval.h.

#define UP_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource15

Definition at line 149 of file stm3210e_eval.h.

#define UP_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOG

Definition at line 148 of file stm3210e_eval.h.

#define UP_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOG

Definition at line 146 of file stm3210e_eval.h.

#define UP_BUTTON_GPIO_PORT GPIOG

Definition at line 145 of file stm3210e_eval.h.

#define UP_BUTTON_PIN GPIO_Pin_15

Joystick Up push-button.

Definition at line 144 of file stm3210e_eval.h.

#define WAKEUP_BUTTON_EXTI_IRQn EXTI0_IRQn

Definition at line 100 of file stm3210e_eval.h.

#define WAKEUP_BUTTON_EXTI_LINE EXTI_Line0

Definition at line 97 of file stm3210e_eval.h.

#define WAKEUP_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource0

Definition at line 99 of file stm3210e_eval.h.

#define WAKEUP_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOA

Definition at line 98 of file stm3210e_eval.h.

#define WAKEUP_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOA

Definition at line 96 of file stm3210e_eval.h.

#define WAKEUP_BUTTON_GPIO_PORT GPIOA

Definition at line 95 of file stm3210e_eval.h.

#define WAKEUP_BUTTON_PIN GPIO_Pin_0

Wakeup push-button.

Definition at line 94 of file stm3210e_eval.h.


STM32F10x Standard Peripherals Firmware Library: STM3210E_EVAL_LOW_LEVEL_COM

Defines

STM3210E_EVAL_LOW_LEVEL_COM

STM3210E_EVAL_LOW_LEVEL_Exported_Constants

Defines

#define | COMn 2
#define | EVAL_COM1 USART1
Definition for COM port1, connected to USART1.
#define | EVAL_COM1_CLK RCC_APB2Periph_USART1
#define | EVAL_COM1_IRQn USART1_IRQn
#define | EVAL_COM1_RX_GPIO_CLK RCC_APB2Periph_GPIOA
#define | EVAL_COM1_RX_GPIO_PORT GPIOA
#define | EVAL_COM1_RX_PIN GPIO_Pin_10
#define | EVAL_COM1_TX_GPIO_CLK RCC_APB2Periph_GPIOA
#define | EVAL_COM1_TX_GPIO_PORT GPIOA
#define | EVAL_COM1_TX_PIN GPIO_Pin_9
#define | EVAL_COM2 USART2
Definition for COM port2, connected to USART2.
#define | EVAL_COM2_CLK RCC_APB1Periph_USART2
#define | EVAL_COM2_IRQn USART2_IRQn
#define | EVAL_COM2_RX_GPIO_CLK RCC_APB2Periph_GPIOA
#define | EVAL_COM2_RX_GPIO_PORT GPIOA
#define | EVAL_COM2_RX_PIN GPIO_Pin_3
#define | EVAL_COM2_TX_GPIO_CLK RCC_APB2Periph_GPIOA
#define | EVAL_COM2_TX_GPIO_PORT GPIOA
#define | EVAL_COM2_TX_PIN GPIO_Pin_2

Define Documentation

#define COMn 2

Definition at line 178 of file stm3210e_eval.h.

#define EVAL_COM1 USART1

Definition for COM port1, connected to USART1.

Definition at line 183 of file stm3210e_eval.h.

#define EVAL_COM1_CLK RCC_APB2Periph_USART1

Definition at line 184 of file stm3210e_eval.h.

#define EVAL_COM1_IRQn USART1_IRQn

Definition at line 191 of file stm3210e_eval.h.

#define EVAL_COM1_RX_GPIO_CLK RCC_APB2Periph_GPIOA

Definition at line 190 of file stm3210e_eval.h.

#define EVAL_COM1_RX_GPIO_PORT GPIOA

Definition at line 189 of file stm3210e_eval.h.

#define EVAL_COM1_RX_PIN GPIO_Pin_10

Definition at line 188 of file stm3210e_eval.h.

#define EVAL_COM1_TX_GPIO_CLK RCC_APB2Periph_GPIOA

Definition at line 187 of file stm3210e_eval.h.

#define EVAL_COM1_TX_GPIO_PORT GPIOA

Definition at line 186 of file stm3210e_eval.h.

#define EVAL_COM1_TX_PIN GPIO_Pin_9

Definition at line 185 of file stm3210e_eval.h.

#define EVAL_COM2 USART2

Definition for COM port2, connected to USART2.

Definition at line 196 of file stm3210e_eval.h.

#define EVAL_COM2_CLK RCC_APB1Periph_USART2

Definition at line 197 of file stm3210e_eval.h.

#define EVAL_COM2_IRQn USART2_IRQn

Definition at line 204 of file stm3210e_eval.h.

#define EVAL_COM2_RX_GPIO_CLK RCC_APB2Periph_GPIOA

Definition at line 203 of file stm3210e_eval.h.

#define EVAL_COM2_RX_GPIO_PORT GPIOA

Definition at line 202 of file stm3210e_eval.h.

#define EVAL_COM2_RX_PIN GPIO_Pin_3

Definition at line 201 of file stm3210e_eval.h.

#define EVAL_COM2_TX_GPIO_CLK RCC_APB2Periph_GPIOA

Definition at line 200 of file stm3210e_eval.h.

#define EVAL_COM2_TX_GPIO_PORT GPIOA

Definition at line 199 of file stm3210e_eval.h.

#define EVAL_COM2_TX_PIN GPIO_Pin_2

Definition at line 198 of file stm3210e_eval.h.


STM32F10x Standard Peripherals Firmware Library: STM3210E_EVAL_LOW_LEVEL_SD_FLASH

Defines

STM3210E_EVAL_LOW_LEVEL_SD_FLASH

STM3210E_EVAL_LOW_LEVEL_Exported_Constants

Defines

#define | SD_DETECT_GPIO_CLK RCC_APB2Periph_GPIOF
#define | SD_DETECT_GPIO_PORT GPIOF
#define | SD_DETECT_PIN GPIO_Pin_11
SD FLASH SDIO Interface.
#define | SDIO_FIFO_ADDRESS ((uint32_t)0x40018080)
#define | SDIO_INIT_CLK_DIV ((uint8_t)0xB2)
SDIO Intialization Frequency (400KHz max)
#define | SDIO_TRANSFER_CLK_DIV ((uint8_t)0x00)
SDIO Data Transfer Frequency (25MHz max)

Define Documentation

#define SD_DETECT_GPIO_CLK RCC_APB2Periph_GPIOF

Definition at line 219 of file stm3210e_eval.h.

#define SD_DETECT_GPIO_PORT GPIOF

Definition at line 218 of file stm3210e_eval.h.

#define SD_DETECT_PIN GPIO_Pin_11

SD FLASH SDIO Interface.

Definition at line 217 of file stm3210e_eval.h.

#define SDIO_FIFO_ADDRESS ((uint32_t)0x40018080)

Definition at line 221 of file stm3210e_eval.h.

Referenced by SD_LowLevel_DMA_RxConfig(), and SD_LowLevel_DMA_TxConfig().

#define SDIO_INIT_CLK_DIV ((uint8_t)0xB2)

SDIO Intialization Frequency (400KHz max)

Definition at line 225 of file stm3210e_eval.h.

Referenced by SD_PowerON().

#define SDIO_TRANSFER_CLK_DIV ((uint8_t)0x00)

SDIO Data Transfer Frequency (25MHz max)

Definition at line 229 of file stm3210e_eval.h.

Referenced by SD_EnableWideBusOperation(), and SD_Init().


STM32F10x Standard Peripherals Firmware Library: STM3210E_EVAL_LOW_LEVEL_M25P_FLASH_SPI

Defines

STM3210E_EVAL_LOW_LEVEL_M25P_FLASH_SPI

STM3210E_EVAL_LOW_LEVEL_Exported_Constants

Defines

#define | sFLASH_CS_GPIO_CLK RCC_APB2Periph_GPIOB
#define | sFLASH_CS_GPIO_PORT GPIOB
#define | sFLASH_CS_PIN GPIO_Pin_2
#define | sFLASH_SPI SPI1
M25P FLASH SPI Interface pins.
#define | sFLASH_SPI_CLK RCC_APB2Periph_SPI1
#define | sFLASH_SPI_MISO_GPIO_CLK RCC_APB2Periph_GPIOA
#define | sFLASH_SPI_MISO_GPIO_PORT GPIOA
#define | sFLASH_SPI_MISO_PIN GPIO_Pin_6
#define | sFLASH_SPI_MOSI_GPIO_CLK RCC_APB2Periph_GPIOA
#define | sFLASH_SPI_MOSI_GPIO_PORT GPIOA
#define | sFLASH_SPI_MOSI_PIN GPIO_Pin_7
#define | sFLASH_SPI_SCK_GPIO_CLK RCC_APB2Periph_GPIOA
#define | sFLASH_SPI_SCK_GPIO_PORT GPIOA
#define | sFLASH_SPI_SCK_PIN GPIO_Pin_5

Define Documentation

#define sFLASH_CS_GPIO_CLK RCC_APB2Periph_GPIOB

Definition at line 254 of file stm3210e_eval.h.

#define sFLASH_CS_GPIO_PORT GPIOB

Definition at line 253 of file stm3210e_eval.h.

#define sFLASH_CS_PIN GPIO_Pin_2

Definition at line 252 of file stm3210e_eval.h.

#define sFLASH_SPI SPI1

M25P FLASH SPI Interface pins.

Definition at line 241 of file stm3210e_eval.h.

#define sFLASH_SPI_CLK RCC_APB2Periph_SPI1

Definition at line 242 of file stm3210e_eval.h.

#define sFLASH_SPI_MISO_GPIO_CLK RCC_APB2Periph_GPIOA

Definition at line 248 of file stm3210e_eval.h.

#define sFLASH_SPI_MISO_GPIO_PORT GPIOA

Definition at line 247 of file stm3210e_eval.h.

#define sFLASH_SPI_MISO_PIN GPIO_Pin_6

Definition at line 246 of file stm3210e_eval.h.

#define sFLASH_SPI_MOSI_GPIO_CLK RCC_APB2Periph_GPIOA

Definition at line 251 of file stm3210e_eval.h.

#define sFLASH_SPI_MOSI_GPIO_PORT GPIOA

Definition at line 250 of file stm3210e_eval.h.

#define sFLASH_SPI_MOSI_PIN GPIO_Pin_7

Definition at line 249 of file stm3210e_eval.h.

#define sFLASH_SPI_SCK_GPIO_CLK RCC_APB2Periph_GPIOA

Definition at line 245 of file stm3210e_eval.h.

#define sFLASH_SPI_SCK_GPIO_PORT GPIOA

Definition at line 244 of file stm3210e_eval.h.

#define sFLASH_SPI_SCK_PIN GPIO_Pin_5

Definition at line 243 of file stm3210e_eval.h.


STM32F10x Standard Peripherals Firmware Library: STM3210E_EVAL_LOW_LEVEL_TSENSOR_I2C

Defines

STM3210E_EVAL_LOW_LEVEL_TSENSOR_I2C

STM3210E_EVAL_LOW_LEVEL_Exported_Constants

Defines

#define | LM75_DMA_CLK RCC_AHBPeriph_DMA1
#define | LM75_DMA_RX_CHANNEL DMA1_Channel7
#define | LM75_DMA_RX_TCFLAG DMA1_FLAG_TC7
#define | LM75_DMA_TX_CHANNEL DMA1_Channel6
#define | LM75_DMA_TX_TCFLAG DMA1_FLAG_TC6
#define | LM75_I2C I2C1
LM75 Temperature Sensor I2C Interface pins.
#define | LM75_I2C_CLK RCC_APB1Periph_I2C1
#define | LM75_I2C_DR ((uint32_t)0x40005410)
#define | LM75_I2C_SCL_GPIO_CLK RCC_APB2Periph_GPIOB
#define | LM75_I2C_SCL_GPIO_PORT GPIOB
#define | LM75_I2C_SCL_PIN GPIO_Pin_6
#define | LM75_I2C_SDA_GPIO_CLK RCC_APB2Periph_GPIOB
#define | LM75_I2C_SDA_GPIO_PORT GPIOB
#define | LM75_I2C_SDA_PIN GPIO_Pin_7
#define | LM75_I2C_SMBUSALERT_GPIO_CLK RCC_APB2Periph_GPIOB
#define | LM75_I2C_SMBUSALERT_GPIO_PORT GPIOB
#define | LM75_I2C_SMBUSALERT_PIN GPIO_Pin_5

Define Documentation

#define LM75_DMA_CLK RCC_AHBPeriph_DMA1

Definition at line 279 of file stm3210e_eval.h.

#define LM75_DMA_RX_CHANNEL DMA1_Channel7

Definition at line 281 of file stm3210e_eval.h.

#define LM75_DMA_RX_TCFLAG DMA1_FLAG_TC7

Definition at line 283 of file stm3210e_eval.h.

#define LM75_DMA_TX_CHANNEL DMA1_Channel6

Definition at line 280 of file stm3210e_eval.h.

#define LM75_DMA_TX_TCFLAG DMA1_FLAG_TC6

Definition at line 282 of file stm3210e_eval.h.

#define LM75_I2C I2C1

LM75 Temperature Sensor I2C Interface pins.

Definition at line 266 of file stm3210e_eval.h.

#define LM75_I2C_CLK RCC_APB1Periph_I2C1

Definition at line 267 of file stm3210e_eval.h.

#define LM75_I2C_DR ((uint32_t)0x40005410)

Definition at line 277 of file stm3210e_eval.h.

#define LM75_I2C_SCL_GPIO_CLK RCC_APB2Periph_GPIOB

Definition at line 270 of file stm3210e_eval.h.

#define LM75_I2C_SCL_GPIO_PORT GPIOB

Definition at line 269 of file stm3210e_eval.h.

#define LM75_I2C_SCL_PIN GPIO_Pin_6

Definition at line 268 of file stm3210e_eval.h.

#define LM75_I2C_SDA_GPIO_CLK RCC_APB2Periph_GPIOB

Definition at line 273 of file stm3210e_eval.h.

#define LM75_I2C_SDA_GPIO_PORT GPIOB

Definition at line 272 of file stm3210e_eval.h.

#define LM75_I2C_SDA_PIN GPIO_Pin_7

Definition at line 271 of file stm3210e_eval.h.

#define LM75_I2C_SMBUSALERT_GPIO_CLK RCC_APB2Periph_GPIOB

Definition at line 276 of file stm3210e_eval.h.

#define LM75_I2C_SMBUSALERT_GPIO_PORT GPIOB

Definition at line 275 of file stm3210e_eval.h.

#define LM75_I2C_SMBUSALERT_PIN GPIO_Pin_5

Definition at line 274 of file stm3210e_eval.h.


STM32F10x Standard Peripherals Firmware Library: STM3210E_EVAL_LOW_LEVEL_Exported_Macros

STM3210E_EVAL_LOW_LEVEL_Exported_Macros

STM3210E_EVAL_LOW_LEVEL


STM32F10x Standard Peripherals Firmware Library: STM3210E_EVAL_LOW_LEVEL_Exported_Functions

Functions

STM3210E_EVAL_LOW_LEVEL_Exported_Functions

STM3210E_EVAL_LOW_LEVEL

Functions

void | LM75_LowLevel_DeInit (void)
DeInitializes the LM75_I2C.
void | LM75_LowLevel_Init (void)
Initializes the LM75_I2C.
uint32_t | SD_DMAEndOfTransferStatus (void)
Returns the DMA End Of Transfer Status.
void | SD_LowLevel_DeInit (void)
DeInitializes the SD/SD communication.
void | SD_LowLevel_DMA_RxConfig (uint32_t *BufferDST, uint32_t BufferSize)
Configures the DMA2 Channel4 for SDIO Rx request.
void | SD_LowLevel_DMA_TxConfig (uint32_t *BufferSRC, uint32_t BufferSize)
Configures the DMA2 Channel4 for SDIO Tx request.
void | SD_LowLevel_Init (void)
Initializes the SD_SPI and CS pins.
void | sFLASH_LowLevel_DeInit (void)
DeInitializes the peripherals used by the SPI FLASH driver.
void | sFLASH_LowLevel_Init (void)
Initializes the peripherals used by the SPI FLASH driver.
void | STM_EVAL_COMInit (COM_TypeDef COM, USART_InitTypeDef *USART_InitStruct)
Configures COM port.
void | STM_EVAL_LEDInit (Led_TypeDef Led)
Configures LED GPIO.
void | STM_EVAL_LEDOff (Led_TypeDef Led)
Turns selected LED Off.
void | STM_EVAL_LEDOn (Led_TypeDef Led)
Turns selected LED On.
void | STM_EVAL_LEDToggle (Led_TypeDef Led)
Toggles the selected LED.
uint32_t | STM_EVAL_PBGetState (Button_TypeDef Button)
Returns the selected Button state.
void | STM_EVAL_PBInit (Button_TypeDef Button, ButtonMode_TypeDef Button_Mode)
Configures Button GPIO and EXTI Line.

Function Documentation

void LM75_LowLevel_DeInit ( void )

DeInitializes the LM75_I2C.

Parameters:
None
Return values:
None

< Disable LM75_I2C

< DeInitializes the LM75_I2C

< LM75_I2C Periph clock disable

< Configure LM75_I2C pins: SCL

< Configure LM75_I2C pins: SDA

< Configure LM75_I2C pin: SMBUS ALERT

< Disable LM75_I2C

< DeInitializes the LM75_I2C

< LM75_I2C Periph clock disable

< Configure LM75_I2C pins: SCL

< Configure LM75_I2C pins: SDA

< Configure LM75_I2C pin: SMBUS ALERT

< Disable LM75_I2C

< DeInitializes the LM75_I2C

< LM75_I2C Periph clock disable

< Configure LM75_I2C pins: SCL

< Configure LM75_I2C pins: SDA

< Configure LM75_I2C pin: SMBUS ALERT

< Disable LM75_I2C

< DeInitializes the LM75_I2C

< LM75_I2C Periph clock disable

< Configure LM75_I2C pins: SCL

< Configure LM75_I2C pins: SDA

< Configure LM75_I2C pin: SMBUS ALERT

< Disable LM75_I2C

< DeInitializes the LM75_I2C

< LM75_I2C Periph clock disable

< Configure LM75_I2C pins: SCL

< Configure LM75_I2C pins: SDA

< Configure LM75_I2C pin: SMBUS ALERT

Definition at line 544 of file stm32100b_eval.c.

void LM75_LowLevel_Init ( void )

Initializes the LM75_I2C.

Parameters:
None
Return values:
None
Parameters:
None
Return values:
None

< LM75_I2C Periph clock enable

< LM75_I2C_SCL_GPIO_CLK, LM75_I2C_SDA_GPIO_CLK and LM75_I2C_SMBUSALERT_GPIO_CLK Periph clock enable

< Configure LM75_I2C pins: SCL

< Configure LM75_I2C pins: SDA

< Configure LM75_I2C pin: SMBUS ALERT

< LM75_I2C Periph clock enable

< LM75_I2C_SCL_GPIO_CLK, LM75_I2C_SDA_GPIO_CLK and LM75_I2C_SMBUSALERT_GPIO_CLK Periph clock enable

< Configure LM75_I2C pins: SCL

< Configure LM75_I2C pins: SDA

< Configure LM75_I2C pin: SMBUS ALERT

< LM75_I2C Periph clock enable

< LM75_I2C_SCL_GPIO_CLK, LM75_I2C_SDA_GPIO_CLK and LM75_I2C_SMBUSALERT_GPIO_CLK Periph clock enable

< Configure LM75_I2C pins: SCL

< Configure LM75_I2C pins: SDA

< Configure LM75_I2C pin: SMBUS ALERT

< LM75_I2C Periph clock enable

< LM75_I2C_SCL_GPIO_CLK, LM75_I2C_SDA_GPIO_CLK and LM75_I2C_SMBUSALERT_GPIO_CLK Periph clock enable

< Configure LM75_I2C pins: SCL

< Configure LM75_I2C pins: SDA

< Configure LM75_I2C pin: SMBUS ALERT

< LM75_I2C Periph clock enable

< LM75_I2C_SCL_GPIO_CLK, LM75_I2C_SDA_GPIO_CLK and LM75_I2C_SMBUSALERT_GPIO_CLK Periph clock enable

< Configure LM75_I2C pins: SCL

< Configure LM75_I2C pins: SDA

< Configure LM75_I2C pin: SMBUS ALERT

Definition at line 575 of file stm32100b_eval.c.

uint32_t SD_DMAEndOfTransferStatus ( void )

Returns the DMA End Of Transfer Status.

Parameters:
None
Return values:
DMA SDIO Channel Status.

Definition at line 504 of file stm3210e_eval.c.

References DMA2_FLAG_TC4, and DMA_GetFlagStatus().

Referenced by SD_WaitReadOperation(), and SD_WaitWriteOperation().

void SD_LowLevel_DeInit ( void )

DeInitializes the SD/SD communication.

Parameters:
None
Return values:
None DeInitializes the SD/SD communication.
Parameters:
None
Return values:
None

< SD_SPI disable

< DeInitializes the SD_SPI

< SD_SPI Periph clock disable

< Configure SD_SPI pins: SCK

< Configure SD_SPI pins: MISO

< Configure SD_SPI pins: MOSI

< Configure SD_SPI_CS_PIN pin: SD Card CS pin

< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin

< SD_SPI disable

< DeInitializes the SD_SPI

< SD_SPI Periph clock disable

< Configure SD_SPI pins: SCK

< Configure SD_SPI pins: MISO

< Configure SD_SPI pins: MOSI

< Configure SD_SPI_CS_PIN pin: SD Card CS pin

< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin

< SD_SPI disable

< DeInitializes the SD_SPI

< SD_SPI Periph clock disable

< Configure SD_SPI pins: SCK

< Configure SD_SPI pins: MISO

< Configure SD_SPI pins: MOSI

< Configure SD_SPI_CS_PIN pin: SD Card CS pin

< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin

< SD_SPI disable

< DeInitializes the SD_SPI

< SD_SPI Periph clock disable

< DeRemap SPI3 Pins

< Configure SD_SPI pins: SCK

< Configure SD_SPI pins: MISO

< Configure SD_SPI pins: MOSI

< Configure SD_SPI_CS_PIN pin: SD Card CS pin

< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin

< Disable SDIO Clock

< Set Power State to OFF

< DeInitializes the SDIO peripheral

< Disable the SDIO AHB Clock

< Configure PC.08, PC.09, PC.10, PC.11, PC.12 pin: D0, D1, D2, D3, CLK pin

< Configure PD.02 CMD line

< SD_SPI disable

< DeInitializes the SD_SPI

< SD_SPI Periph clock disable

< Configure SD_SPI pins: SCK

< Configure SD_SPI pins: MISO

< Configure SD_SPI pins: MOSI

< Configure SD_SPI_CS_PIN pin: SD Card CS pin

< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin

Definition at line 373 of file stm32100b_eval.c.

void SD_LowLevel_DMA_RxConfig | ( | uint32_t * | BufferDST,
 |  | uint32_t | BufferSize
 | ) |  |

Configures the DMA2 Channel4 for SDIO Rx request.

Parameters:
BufferDST,: pointer to the destination buffer
BufferSize,: buffer size
Return values:
None

< DMA2 Channel4 disable

< DMA2 Channel4 Config

< DMA2 Channel4 enable

Definition at line 472 of file stm3210e_eval.c.

References DISABLE, DMA2_Channel4, DMA2_FLAG_GL4, DMA2_FLAG_HT4, DMA2_FLAG_TC4, DMA2_FLAG_TE4, DMA_InitTypeDef::DMA_BufferSize, DMA_ClearFlag(), DMA_Cmd(), DMA_InitTypeDef::DMA_DIR, DMA_DIR_PeripheralSRC, DMA_Init(), DMA_InitStructure, DMA_InitTypeDef::DMA_M2M, DMA_M2M_Disable, DMA_InitTypeDef::DMA_MemoryBaseAddr, DMA_InitTypeDef::DMA_MemoryDataSize, DMA_MemoryDataSize_Word, DMA_InitTypeDef::DMA_MemoryInc, DMA_MemoryInc_Enable, DMA_InitTypeDef::DMA_Mode, DMA_Mode_Normal, DMA_InitTypeDef::DMA_PeripheralBaseAddr, DMA_InitTypeDef::DMA_PeripheralDataSize, DMA_PeripheralDataSize_Word, DMA_InitTypeDef::DMA_PeripheralInc, DMA_PeripheralInc_Disable, DMA_InitTypeDef::DMA_Priority, DMA_Priority_High, ENABLE, and SDIO_FIFO_ADDRESS.

Referenced by SD_ReadBlock(), and SD_ReadMultiBlocks().

void SD_LowLevel_DMA_TxConfig | ( | uint32_t * | BufferSRC,
 |  | uint32_t | BufferSize
 | ) |  |

Configures the DMA2 Channel4 for SDIO Tx request.

Parameters:
BufferSRC,: pointer to the source buffer
BufferSize,: buffer size
Return values:
None

< DMA2 Channel4 disable

< DMA2 Channel4 Config

< DMA2 Channel4 enable

Definition at line 438 of file stm3210e_eval.c.

References DISABLE, DMA2_Channel4, DMA2_FLAG_GL4, DMA2_FLAG_HT4, DMA2_FLAG_TC4, DMA2_FLAG_TE4, DMA_InitTypeDef::DMA_BufferSize, DMA_ClearFlag(), DMA_Cmd(), DMA_InitTypeDef::DMA_DIR, DMA_DIR_PeripheralDST, DMA_Init(), DMA_InitStructure, DMA_InitTypeDef::DMA_M2M, DMA_M2M_Disable, DMA_InitTypeDef::DMA_MemoryBaseAddr, DMA_InitTypeDef::DMA_MemoryDataSize, DMA_MemoryDataSize_Word, DMA_InitTypeDef::DMA_MemoryInc, DMA_MemoryInc_Enable, DMA_InitTypeDef::DMA_Mode, DMA_Mode_Normal, DMA_InitTypeDef::DMA_PeripheralBaseAddr, DMA_InitTypeDef::DMA_PeripheralDataSize, DMA_PeripheralDataSize_Word, DMA_InitTypeDef::DMA_PeripheralInc, DMA_PeripheralInc_Disable, DMA_InitTypeDef::DMA_Priority, DMA_Priority_High, ENABLE, and SDIO_FIFO_ADDRESS.

Referenced by SD_WriteBlock(), and SD_WriteMultiBlocks().

void SD_LowLevel_Init ( void )

Initializes the SD_SPI and CS pins.

Parameters:
None
Return values:
None Initializes the SD_SPI and CS pins.
Parameters:
None
Return values:
None

< SD_SPI_CS_GPIO, SD_SPI_MOSI_GPIO, SD_SPI_MISO_GPIO, SD_SPI_DETECT_GPIO and SD_SPI_SCK_GPIO Periph clock enable

< SD_SPI Periph clock enable

< Configure SD_SPI pins: SCK

< Configure SD_SPI pins: MOSI

< Configure SD_SPI pins: MISO

< Configure SD_SPI_CS_PIN pin: SD Card CS pin

< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin

< SD_SPI Config

< SD_SPI enable

< SD_SPI_CS_GPIO, SD_SPI_MOSI_GPIO, SD_SPI_MISO_GPIO, SD_SPI_DETECT_GPIO and SD_SPI_SCK_GPIO Periph clock enable

< SD_SPI Periph clock enable

< Configure SD_SPI pins: SCK

< Configure SD_SPI pins: MOSI

< Configure SD_SPI pins: MISO

< Configure SD_SPI_CS_PIN pin: SD Card CS pin

< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin

< SD_SPI Config

< SD_SPI enable

< SD_SPI_CS_GPIO, SD_SPI_MOSI_GPIO, SD_SPI_MISO_GPIO, SD_SPI_DETECT_GPIO and SD_SPI_SCK_GPIO Periph clock enable

< SD_SPI Periph clock enable

< Configure SD_SPI pins: SCK

< Configure SD_SPI pins: MOSI

< Configure SD_SPI pins: MISO

< Configure SD_SPI_CS_PIN pin: SD Card CS pin

< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin

< SD_SPI Config

< SD_SPI enable

< SD_SPI_CS_GPIO, SD_SPI_MOSI_GPIO, SD_SPI_MISO_GPIO, SD_SPI_DETECT_GPIO and SD_SPI_SCK_GPIO Periph clock enable

< SD_SPI Periph clock enable

< AFIO Periph clock enable

< Remap SPI3 Pins

< Configure SD_SPI pins: SCK

< Configure SD_SPI pins: MOSI

< Configure SD_SPI pins: MISO

< Configure SD_SPI_CS_PIN pin: SD Card CS pin

< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin

< SD_SPI Config

< SD_SPI enable

< GPIOC and GPIOD Periph clock enable

< Configure PC.08, PC.09, PC.10, PC.11, PC.12 pin: D0, D1, D2, D3, CLK pin

< Configure PD.02 CMD line

< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin

< Enable the SDIO AHB Clock

< Enable the DMA2 Clock

< SD_SPI_CS_GPIO, SD_SPI_MOSI_GPIO, SD_SPI_MISO_GPIO, SD_SPI_DETECT_GPIO and SD_SPI_SCK_GPIO Periph clock enable

< SD_SPI Periph clock enable

< Configure SD_SPI pins: SCK

< Configure SD_SPI pins: MISO

< Configure SD_SPI pins: MOSI

< Configure SD_SPI_CS_PIN pin: SD Card CS pin

< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin

< SD_SPI Config

< SD_SPI enable

Definition at line 410 of file stm32100b_eval.c.

void sFLASH_LowLevel_DeInit ( void )

DeInitializes the peripherals used by the SPI FLASH driver.

Parameters:
None
Return values:
None

< Disable the sFLASH_SPI

< DeInitializes the sFLASH_SPI

< sFLASH_SPI Periph clock disable

< Configure sFLASH_SPI pins: SCK

< Configure sFLASH_SPI pins: MISO

< Configure sFLASH_SPI pins: MOSI

< Configure sFLASH_CS_PIN pin: sFLASH Card CS pin

< Disable the sFLASH_SPI

< DeInitializes the sFLASH_SPI

< sFLASH_SPI Periph clock disable

< Configure sFLASH_SPI pins: SCK

< Configure sFLASH_SPI pins: MISO

< Configure sFLASH_SPI pins: MOSI

< Configure sFLASH_CS_PIN pin: sFLASH Card CS pin

< Disable the sFLASH_SPI

< DeInitializes the sFLASH_SPI

< sFLASH_SPI Periph clock disable

< Configure sFLASH_SPI pins: SCK

< Configure sFLASH_SPI pins: MISO

< Configure sFLASH_SPI pins: MOSI

< Configure sFLASH_CS_PIN pin: sFLASH Card CS pin

< Disable the sFLASH_SPI

< DeInitializes the sFLASH_SPI

< sFLASH_SPI Periph clock disable

< Configure sFLASH_SPI pins: SCK

< Configure sFLASH_SPI pins: MISO

< Configure sFLASH_SPI pins: MOSI

< Configure sFLASH_CS_PIN pin: sFLASH Card CS pin

Definition at line 470 of file stm32100b_eval.c.

References DISABLE, GPIO_Init(), GPIO_InitStructure, GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_IN_FLOATING, GPIO_InitTypeDef::GPIO_Pin, RCC_APB2PeriphClockCmd(), sFLASH_CS_GPIO_PORT, sFLASH_CS_PIN, sFLASH_SPI, sFLASH_SPI_CLK, sFLASH_SPI_MISO_GPIO_PORT, sFLASH_SPI_MISO_PIN, sFLASH_SPI_MOSI_GPIO_PORT, sFLASH_SPI_MOSI_PIN, sFLASH_SPI_SCK_GPIO_PORT, sFLASH_SPI_SCK_PIN, SPI_Cmd(), and SPI_I2S_DeInit().

Referenced by sFLASH_DeInit().

void sFLASH_LowLevel_Init ( void )

Initializes the peripherals used by the SPI FLASH driver.

Parameters:
None
Return values:
None

< sFLASH_SPI_CS_GPIO, sFLASH_SPI_MOSI_GPIO, sFLASH_SPI_MISO_GPIO and sFLASH_SPI_SCK_GPIO Periph clock enable

< sFLASH_SPI Periph clock enable

< Configure sFLASH_SPI pins: SCK

< Configure sFLASH_SPI pins: MOSI

< Configure sFLASH_SPI pins: MISO

< Configure sFLASH_CS_PIN pin: sFLASH Card CS pin

< sFLASH_SPI_CS_GPIO, sFLASH_SPI_MOSI_GPIO, sFLASH_SPI_MISO_GPIO and sFLASH_SPI_SCK_GPIO Periph clock enable

< sFLASH_SPI Periph clock enable

< Configure sFLASH_SPI pins: SCK

< Configure sFLASH_SPI pins: MOSI

< Configure sFLASH_SPI pins: MISO

< Configure sFLASH_CS_PIN pin: sFLASH Card CS pin

< sFLASH_SPI_CS_GPIO, sFLASH_SPI_MOSI_GPIO, sFLASH_SPI_MISO_GPIO and sFLASH_SPI_SCK_GPIO Periph clock enable

< sFLASH_SPI Periph clock enable

< Configure sFLASH_SPI pins: SCK

< Configure sFLASH_SPI pins: MOSI

< Configure sFLASH_SPI pins: MISO

< Configure sFLASH_CS_PIN pin: sFLASH Card CS pin

< sFLASH_SPI_CS_GPIO, sFLASH_SPI_MOSI_GPIO, sFLASH_SPI_MISO_GPIO and sFLASH_SPI_SCK_GPIO Periph clock enable

< sFLASH_SPI Periph clock enable

< Configure sFLASH_SPI pins: SCK

< Configure sFLASH_SPI pins: MOSI

< Configure sFLASH_SPI pins: MISO

< Configure sFLASH_CS_PIN pin: sFLASH Card CS pin

Definition at line 506 of file stm32100b_eval.c.

References ENABLE, GPIO_Init(), GPIO_InitStructure, GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_AF_PP, GPIO_Mode_IN_FLOATING, GPIO_Mode_Out_PP, GPIO_InitTypeDef::GPIO_Pin, GPIO_InitTypeDef::GPIO_Speed, GPIO_Speed_50MHz, RCC_APB2PeriphClockCmd(), sFLASH_CS_GPIO_CLK, sFLASH_CS_GPIO_PORT, sFLASH_CS_PIN, sFLASH_SPI_CLK, sFLASH_SPI_MISO_GPIO_CLK, sFLASH_SPI_MISO_GPIO_PORT, sFLASH_SPI_MISO_PIN, sFLASH_SPI_MOSI_GPIO_CLK, sFLASH_SPI_MOSI_GPIO_PORT, sFLASH_SPI_MOSI_PIN, sFLASH_SPI_SCK_GPIO_CLK, sFLASH_SPI_SCK_GPIO_PORT, and sFLASH_SPI_SCK_PIN.

Referenced by sFLASH_Init().

void STM_EVAL_COMInit | ( | COM_TypeDef | COM,
 |  | USART_InitTypeDef * | USART_InitStruct
 | ) |  |

Configures COM port.

Parameters:
COM,: Specifies the COM port to be configured. This parameter can be one of following parameters:

  • COM1
  • COM2
USART_InitStruct,: pointer to a USART_InitTypeDef structure that contains the configuration information for the specified USART peripheral.
Return values:
None

Definition at line 330 of file stm32100b_eval.c.

void STM_EVAL_LEDInit ( Led_TypeDef Led )

Configures LED GPIO.

Parameters:
Led,: Specifies the Led to be configured. This parameter can be one of following parameters:

  • LED1
  • LED2
  • LED3
  • LED4
Return values:
None

Definition at line 176 of file stm32100b_eval.c.

void STM_EVAL_LEDOff ( Led_TypeDef Led )

Turns selected LED Off.

Parameters:
Led,: Specifies the Led to be set off. This parameter can be one of following parameters:

  • LED1
  • LED2
  • LED3
  • LED4
Return values:
None

Definition at line 216 of file stm32100b_eval.c.

void STM_EVAL_LEDOn ( Led_TypeDef Led )

Turns selected LED On.

Parameters:
Led,: Specifies the Led to be set on. This parameter can be one of following parameters:

  • LED1
  • LED2
  • LED3
  • LED4
Return values:
None

Definition at line 201 of file stm32100b_eval.c.

void STM_EVAL_LEDToggle ( Led_TypeDef Led )

Toggles the selected LED.

Parameters:
Led,: Specifies the Led to be toggled. This parameter can be one of following parameters:

  • LED1
  • LED2
  • LED3
  • LED4
Return values:
None

Definition at line 231 of file stm32100b_eval.c.

uint32_t STM_EVAL_PBGetState ( Button_TypeDef Button )

Returns the selected Button state.

Parameters:
Button,: Specifies the Button to be checked. This parameter can be one of following parameters:

  • BUTTON_WAKEUP: Wakeup Push Button
  • BUTTON_TAMPER: Tamper Push Button
  • BUTTON_KEY: Key Push Button
  • BUTTON_RIGHT: Joystick Right Push Button
  • BUTTON_LEFT: Joystick Left Push Button
  • BUTTON_UP: Joystick Up Push Button
  • BUTTON_DOWN: Joystick Down Push Button
  • BUTTON_SEL: Joystick Sel Push Button
Return values:
The Button GPIO pin value.
Parameters:
Button,: Specifies the Button to be checked. This parameter can be one of following parameters:

  • BUTTON_KEY: Key Push Button
  • BUTTON_RIGHT: Joystick Right Push Button
  • BUTTON_LEFT: Joystick Left Push Button
  • BUTTON_UP: Joystick Up Push Button
  • BUTTON_DOWN: Joystick Down Push Button
  • BUTTON_SEL: Joystick Sel Push Button
Return values:
- When Button > 1, the Button GPIO pin value is returned.

  • When Button = 0 or 1, error code (0xFF) is returned.

Definition at line 314 of file stm32100b_eval.c.

void STM_EVAL_PBInit | ( | Button_TypeDef | Button,
 |  | ButtonMode_TypeDef | Button_Mode
 | ) |  |

Configures Button GPIO and EXTI Line.

Parameters:
Button,: Specifies the Button to be configured. This parameter can be one of following parameters:

  • BUTTON_WAKEUP: Wakeup Push Button
  • BUTTON_TAMPER: Tamper Push Button
  • BUTTON_KEY: Key Push Button
  • BUTTON_RIGHT: Joystick Right Push Button
  • BUTTON_LEFT: Joystick Left Push Button
  • BUTTON_UP: Joystick Up Push Button
  • BUTTON_DOWN: Joystick Down Push Button
  • BUTTON_SEL: Joystick Sel Push Button
Button_Mode,: Specifies Button mode. This parameter can be one of following parameters:

  • BUTTON_MODE_GPIO: Button will be used as simple IO
  • BUTTON_MODE_EXTI: Button will be connected to EXTI line with interrupt generation capability
Return values:
None
Parameters:
Button,: Specifies the Button to be configured. This parameter can be one of following parameters:

  • BUTTON_KEY: Key Push Button
  • BUTTON_RIGHT: Joystick Right Push Button
  • BUTTON_LEFT: Joystick Left Push Button
  • BUTTON_UP: Joystick Up Push Button
  • BUTTON_DOWN: Joystick Down Push Button
  • BUTTON_SEL: Joystick Sel Push Button
Button_Mode,: Specifies Button mode. This parameter can be one of following parameters:

  • BUTTON_MODE_GPIO: Button will be used as simple IO
  • BUTTON_MODE_EXTI: Button will be connected to EXTI line with interrupt generation capability
Return values:
None

Definition at line 255 of file stm32100b_eval.c.


STM32F10x Standard Peripherals Firmware Library: STM3210E_EVAL_LCD_Private_Defines

Defines

STM3210E_EVAL_LCD_Private_Defines

STM3210E_EVAL_LCD

Defines

#define | LCD ((LCD_TypeDef *) LCD_BASE)
#define | LCD_BASE ((uint32_t)(0x60000000 | 0x0C000000))
#define | MAX_POLY_CORNERS 200
#define | POLY_X(Z) ((int32_t)((Points + Z)->Y))
#define | POLY_Y(Z) ((int32_t)((Points + Z)->X))

Define Documentation

#define LCD ((LCD_TypeDef *) LCD_BASE)

Definition at line 65 of file stm3210e_eval_lcd.c.

Referenced by LCD_Clear(), LCD_ReadRAM(), LCD_ReadReg(), LCD_WriteRAM(), LCD_WriteRAM_Prepare(), and LCD_WriteReg().

#define LCD_BASE ((uint32_t)(0x60000000 | 0x0C000000))

Definition at line 64 of file stm3210e_eval_lcd.c.

#define MAX_POLY_CORNERS 200

Definition at line 66 of file stm3210e_eval_lcd.c.

Referenced by LCD_FillPolyLine().

#define POLY_X ( Z ) ((int32_t)((Points + Z)->Y))

Definition at line 68 of file stm3210e_eval_lcd.c.

Referenced by LCD_FillPolyLine().

#define POLY_Y ( Z ) ((int32_t)((Points + Z)->X))

Definition at line 67 of file stm3210e_eval_lcd.c.

Referenced by LCD_FillPolyLine().


STM32F10x Standard Peripherals Firmware Library: STM3210E_EVAL_LCD_Private_Macros

Defines

STM3210E_EVAL_LCD_Private_Macros

STM3210E_EVAL_LCD

Defines

#define ABS(X) ((X) > 0 ? (X) : -(X))

Define Documentation

#define ABS ( X ) ((X) > 0 ? (X) : -(X))

Definition at line 76 of file stm3210e_eval_lcd.c.

Referenced by LCD_DrawUniLine().


STM32F10x Standard Peripherals Firmware Library: STM3210E_EVAL_LCD_Private_Variables

Variables

STM3210E_EVAL_LCD_Private_Variables

STM3210E_EVAL_LCD

Variables

static __IO uint16_t | BackColor = 0xFFFF
static sFONT * | LCD_Currentfonts
static __IO uint16_t | TextColor = 0x0000

Variable Documentation

__IO uint16_t BackColor = 0xFFFF

Definition at line 86 of file stm3210e_eval_lcd.c.

sFONT* LCD_Currentfonts [static]

Definition at line 84 of file stm3210e_eval_lcd.c.

Referenced by LCD_GetFont().

__IO uint16_t TextColor = 0x0000 [static]

Definition at line 86 of file stm3210e_eval_lcd.c.

Referenced by LCD_DrawChar(), LCD_DrawCircle(), LCD_DrawFullCircle(), LCD_DrawFullRect(), LCD_DrawLine(), LCD_DrawMonoPict(), LCD_FillPolyLine(), LCD_GetColors(), LCD_SetColors(), and LCD_SetTextColor().


STM32F10x Standard Peripherals Firmware Library: STM3210E_EVAL_LCD_Private_FunctionPrototypes

STM3210E_EVAL_LCD_Private_FunctionPrototypes

STM3210E_EVAL_LCD


STM32F10x Standard Peripherals Firmware Library: STM3210E_EVAL_LCD_Private_Functions

Functions

STM3210E_EVAL_LCD_Private_Functions

STM3210E_EVAL_LCD

Functions

static void | delay (vu32 nCount)
Inserts a delay time.
void | LCD_Clear (uint16_t Color)
Clears the hole LCD.
void | LCD_ClearLine (uint8_t Line)
Clears the selected line.
void | LCD_ClosedPolyLine (pPoint Points, uint16_t PointCount)
Displays a closed polyline (between many points).
void | LCD_ClosedPolyLineRelative (pPoint Points, uint16_t PointCount)
Displays a closed relative polyline (between many points).
void | LCD_CtrlLinesConfig (void)
Configures LCD Control lines (FSMC Pins) in alternate function mode.
void | LCD_DeInit (void)
DeInitializes the LCD.
void | LCD_DisplayChar (uint8_t Line, uint16_t Column, uint8_t Ascii)
Displays one character (16dots width, 24dots height).
void | LCD_DisplayOff (void)
Disables the Display.
void | LCD_DisplayOn (void)
Enables the Display.
void | LCD_DisplayStringLine (uint8_t Line, uint8_t *ptr)
Displays a maximum of 20 char on the LCD.
void | LCD_DrawChar (uint8_t Xpos, uint16_t Ypos, const uint16_t *c)
Draws a character on LCD.
void | LCD_DrawCircle (uint8_t Xpos, uint16_t Ypos, uint16_t Radius)
Displays a circle.
void | LCD_DrawFullCircle (uint16_t Xpos, uint16_t Ypos, uint16_t Radius)
Displays a full circle.
void | LCD_DrawFullRect (uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height)
Displays a full rectangle.
void | LCD_DrawLine (uint8_t Xpos, uint16_t Ypos, uint16_t Length, uint8_t Direction)
Displays a line.
void | LCD_DrawMonoPict (const uint32_t *Pict)
Displays a monocolor picture.
void | LCD_DrawRect (uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width)
Displays a rectangle.
void | LCD_DrawUniLine (uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2)
Displays an uni line (between two points).
void | LCD_FillPolyLine (pPoint Points, uint16_t PointCount)
Displays a full polyline (between many points).
void | LCD_FSMCConfig (void)
Configures the Parallel interface (FSMC) for LCD(Parallel mode)
void | LCD_GetColors (__IO uint16_t *_TextColor, __IO uint16_t *_BackColor)
Gets the LCD Text and Background colors.
sFONT * | LCD_GetFont (void)
Gets the Text Font.
void | LCD_PolyLine (pPoint Points, uint16_t PointCount)
Displays an polyline (between many points).
void | LCD_PolyLineRelative (pPoint Points, uint16_t PointCount)
Displays a relative polyline (between many points).
static void | LCD_PolyLineRelativeClosed (pPoint Points, uint16_t PointCount, uint16_t Closed)
Displays an relative polyline (between many points).
void | LCD_PowerOn (void)
Power on the LCD.
uint16_t | LCD_ReadRAM (void)
Reads the LCD RAM.
uint16_t | LCD_ReadReg (uint8_t LCD_Reg)
Reads the selected LCD Register.
void | LCD_SetBackColor (__IO uint16_t Color)
Sets the Background color.
void | LCD_SetColors (__IO uint16_t _TextColor, __IO uint16_t _BackColor)
Sets the LCD Text and Background colors.
void | LCD_SetCursor (uint8_t Xpos, uint16_t Ypos)
Sets the cursor position.
void | LCD_SetDisplayWindow (uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width)
Sets a display window.
void | LCD_SetFont (sFONT *fonts)
Sets the Text Font.
void | LCD_SetTextColor (__IO uint16_t Color)
Sets the Text color.
void | LCD_WindowModeDisable (void)
Disables LCD Window mode.
void | LCD_WriteBMP (uint32_t BmpAddress)
Displays a bitmap picture loaded in the internal Flash.
void | LCD_WriteRAM (uint16_t RGB_Code)
Writes to the LCD RAM.
void | LCD_WriteRAM_Prepare (void)
Prepare to write to the LCD RAM.
void | LCD_WriteReg (uint8_t LCD_Reg, uint16_t LCD_RegValue)
Writes to the selected LCD register.
static void | PutPixel (int16_t x, int16_t y)
Displays a pixel.
void | STM3210E_LCD_Init (void)
Initializes the LCD.

Function Documentation

static void delay ( vu32 nCount ) [static]

Inserts a delay time.

Parameters:
nCount,: specifies the delay time length.
Return values:
None

Definition at line 1301 of file stm3210e_eval_lcd.c.

References index.

void LCD_Clear ( uint16_t Color )

Clears the hole LCD.

Parameters:
Color,: the color of the background.
Return values:
None

Definition at line 403 of file stm3210e_eval_lcd.c.

References index, LCD, LCD_SetCursor(), and LCD_WriteRAM_Prepare().

void LCD_ClearLine ( uint8_t Line )

Clears the selected line.

Parameters:
Line,: the Line to be cleared. This parameter can be one of the following values:

  • Linex: where x can be 0..n
Return values:
None

Definition at line 384 of file stm3210e_eval_lcd.c.

References LCD_DisplayChar(), LCD_PIXEL_WIDTH, and _tFont::Width.

void LCD_ClosedPolyLine | ( | pPoint | Points,
 |  | uint16_t | PointCount
 | ) |  |

Displays a closed polyline (between many points).

Parameters:
Points,: pointer to the points array.
PointCount,: Number of points.
Return values:
None

Definition at line 946 of file stm3210e_eval_lcd.c.

References LCD_DrawUniLine(), LCD_PolyLine(), Point::X, and Point::Y.

void LCD_ClosedPolyLineRelative | ( | pPoint | Points,
 |  | uint16_t | PointCount
 | ) |  |

Displays a closed relative polyline (between many points).

Parameters:
Points,: pointer to the points array.
PointCount,: Number of points.
Return values:
None

Definition at line 969 of file stm3210e_eval_lcd.c.

References LCD_PolyLineRelativeClosed().

void LCD_CtrlLinesConfig ( void )

Configures LCD Control lines (FSMC Pins) in alternate function mode.

Configures LCD control lines in Output Push-Pull mode.

Parameters:
None
Return values:
None

Definition at line 1202 of file stm3210e_eval_lcd.c.

References ENABLE, GPIO_Init(), GPIO_InitStructure, GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_AF_PP, GPIO_InitTypeDef::GPIO_Pin, GPIO_Pin_0, GPIO_Pin_1, GPIO_Pin_10, GPIO_Pin_11, GPIO_Pin_12, GPIO_Pin_13, GPIO_Pin_14, GPIO_Pin_15, GPIO_Pin_4, GPIO_Pin_5, GPIO_Pin_7, GPIO_Pin_8, GPIO_Pin_9, GPIO_InitTypeDef::GPIO_Speed, GPIO_Speed_50MHz, GPIOD, GPIOE, GPIOF, GPIOG, RCC_AHBPeriph_FSMC, RCC_AHBPeriphClockCmd(), RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE, RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, and RCC_APB2PeriphClockCmd().

void LCD_DeInit ( void )

DeInitializes the LCD.

Parameters:
None
Return values:
None

< LCD Display Off

< LCD_SPI DeInit

Definition at line 115 of file stm3210e_eval_lcd.c.

References DISABLE, ENABLE, FSMC_Bank1_NORSRAM4, FSMC_NORSRAMCmd(), FSMC_NORSRAMDeInit(), GPIO_Init(), GPIO_InitStructure, GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_IN_FLOATING, GPIO_InitTypeDef::GPIO_Pin, GPIO_Pin_0, GPIO_Pin_1, GPIO_Pin_10, GPIO_Pin_11, GPIO_Pin_12, GPIO_Pin_13, GPIO_Pin_14, GPIO_Pin_15, GPIO_Pin_4, GPIO_Pin_5, GPIO_Pin_7, GPIO_Pin_8, GPIO_Pin_9, GPIOD, GPIOE, GPIOF, GPIOG, LCD_DisplayOff(), LCD_NCS_GPIO_PORT, LCD_NCS_PIN, LCD_NWR_GPIO_PORT, LCD_NWR_PIN, LCD_RS_GPIO_PORT, LCD_RS_PIN, LCD_SPI, LCD_SPI_CLK, LCD_SPI_MISO_GPIO_PORT, LCD_SPI_MISO_PIN, LCD_SPI_MOSI_GPIO_PORT, LCD_SPI_MOSI_PIN, LCD_SPI_SCK_GPIO_PORT, LCD_SPI_SCK_PIN, RCC_APB1PeriphClockCmd(), SPI_Cmd(), and SPI_I2S_DeInit().

void LCD_DisplayChar | ( | uint8_t | Line,
 |  | uint16_t | Column,
 |  | uint8_t | Ascii
 | ) |  |

Displays one character (16dots width, 24dots height).

Parameters:
Line,: the Line where to display the character shape . This parameter can be one of the following values:

  • Linex: where x can be 0..9
Column,: start column address.
Ascii,: character ascii code, must be between 0x20 and 0x7E.
Return values:
None

Definition at line 476 of file stm3210e_eval_lcd.c.

References _tFont::Height, LCD_DrawChar(), and _tFont::table.

void LCD_DisplayOff ( void )

Disables the Display.

Parameters:
None
Return values:
None

Definition at line 1190 of file stm3210e_eval_lcd.c.

References LCD_REG_7, and LCD_WriteReg().

void LCD_DisplayOn ( void )

Enables the Display.

Parameters:
None
Return values:
None

Definition at line 1178 of file stm3210e_eval_lcd.c.

References LCD_REG_7, and LCD_WriteReg().

void LCD_DisplayStringLine | ( | uint8_t | Line,
 |  | uint8_t * | ptr
 | ) |  |

Displays a maximum of 20 char on the LCD.

Parameters:
Line,: the Line where to display the character shape . This parameter can be one of the following values:

  • Linex: where x can be 0..9
*ptr,: pointer to string to display on LCD.
Return values:
None

Definition at line 491 of file stm3210e_eval_lcd.c.

References LCD_DisplayChar(), LCD_PIXEL_WIDTH, and _tFont::Width.

void LCD_DrawChar | ( | uint8_t | Xpos,
 |  | uint16_t | Ypos,
 |  | const uint16_t * | c
 | ) |  |

Draws a character on LCD.

Parameters:
Xpos,: the Line where to display the character shape.
Ypos,: start column address.
c,: pointer to the character data.
Return values:
None

Definition at line 436 of file stm3210e_eval_lcd.c.

References BackColor, _tFont::Height, index, LCD_SetCursor(), LCD_WriteRAM(), LCD_WriteRAM_Prepare(), TextColor, and _tFont::Width.

void LCD_DrawCircle | ( | uint8_t | Xpos,
 |  | uint16_t | Ypos,
 |  | uint16_t | Radius
 | ) |  |

Displays a circle.

Parameters:
Xpos,: specifies the X position.
Ypos,: specifies the Y position.
Radius
Return values:
None

Definition at line 616 of file stm3210e_eval_lcd.c.

References LCD_SetCursor(), LCD_WriteRAM(), LCD_WriteRAM_Prepare(), and TextColor.

void LCD_DrawFullCircle | ( | uint16_t | Xpos,
 |  | uint16_t | Ypos,
 |  | uint16_t | Radius
 | ) |  |

Displays a full circle.

Parameters:
Xpos,: specifies the X position.
Ypos,: specifies the Y position.
Radius
Return values:
None

Definition at line 767 of file stm3210e_eval_lcd.c.

References BackColor, LCD_DIR_HORIZONTAL, LCD_DrawCircle(), LCD_DrawLine(), LCD_SetTextColor(), and TextColor.

void LCD_DrawFullRect | ( | uint16_t | Xpos,
 |  | uint16_t | Ypos,
 |  | uint16_t | Width,
 |  | uint16_t | Height
 | ) |  |

Displays a full rectangle.

Parameters:
Xpos,: specifies the X position.
Ypos,: specifies the Y position.
Height,: rectangle height.
Width,: rectangle width.
Return values:
None

Definition at line 736 of file stm3210e_eval_lcd.c.

References BackColor, LCD_DIR_HORIZONTAL, LCD_DIR_VERTICAL, LCD_DrawLine(), LCD_SetTextColor(), and TextColor.

void LCD_DrawLine | ( | uint8_t | Xpos,
 |  | uint16_t | Ypos,
 |  | uint16_t | Length,
 |  | uint8_t | Direction
 | ) |  |

Displays a line.

Parameters:
Xpos,: specifies the X position.
Ypos,: specifies the Y position.
Length,: line length.
Direction,: line direction. This parameter can be one of the following values: Vertical or Horizontal.
Return values:
None

Definition at line 565 of file stm3210e_eval_lcd.c.

References LCD_DIR_HORIZONTAL, LCD_SetCursor(), LCD_WriteRAM(), LCD_WriteRAM_Prepare(), and TextColor.

void LCD_DrawMonoPict ( const uint32_t * Pict )

Displays a monocolor picture.

Parameters:
Pict,: pointer to the picture array.
Return values:
None

Definition at line 671 of file stm3210e_eval_lcd.c.

References BackColor, index, LCD_PIXEL_WIDTH, LCD_SetCursor(), LCD_WriteRAM(), LCD_WriteRAM_Prepare(), and TextColor.

void LCD_DrawRect | ( | uint8_t | Xpos,
 |  | uint16_t | Ypos,
 |  | uint8_t | Height,
 |  | uint16_t | Width
 | ) |  |

Displays a rectangle.

Parameters:
Xpos,: specifies the X position.
Ypos,: specifies the Y position.
Height,: display rectangle height.
Width,: display rectangle width.
Return values:
None

Definition at line 599 of file stm3210e_eval_lcd.c.

References LCD_DIR_HORIZONTAL, LCD_DIR_VERTICAL, and LCD_DrawLine().

void LCD_DrawUniLine | ( | uint16_t | x1,
 |  | uint16_t | y1,
 |  | uint16_t | x2,
 |  | uint16_t | y2
 | ) |  |

Displays an uni line (between two points).

Parameters:
x1,: specifies the point 1 x position.
y1,: specifies the point 1 y position.
x2,: specifies the point 2 x position.
y2,: specifies the point 2 y position.
Return values:
None

Definition at line 817 of file stm3210e_eval_lcd.c.

References ABS, and PutPixel().

void LCD_FillPolyLine | ( | pPoint | Points,
 |  | uint16_t | PointCount
 | ) |  |

Displays a full polyline (between many points).

Parameters:
Points,: pointer to the points array.
PointCount,: Number of points.
Return values:
None

Definition at line 981 of file stm3210e_eval_lcd.c.

References BackColor, j, LCD_DIR_HORIZONTAL, LCD_DrawLine(), LCD_SetTextColor(), MAX_POLY_CORNERS, POLY_X, POLY_Y, PutPixel(), TextColor, Point::X, and Point::Y.

void LCD_FSMCConfig ( void )

Configures the Parallel interface (FSMC) for LCD(Parallel mode)

Parameters:
None
Return values:
None

Definition at line 1238 of file stm3210e_eval_lcd.c.

References ENABLE, FSMC_NORSRAMTimingInitTypeDef::FSMC_AccessMode, FSMC_AccessMode_A, FSMC_NORSRAMTimingInitTypeDef::FSMC_AddressHoldTime, FSMC_NORSRAMTimingInitTypeDef::FSMC_AddressSetupTime, FSMC_NORSRAMInitTypeDef::FSMC_AsynchronousWait, FSMC_AsynchronousWait_Disable, FSMC_NORSRAMInitTypeDef::FSMC_Bank, FSMC_Bank1_NORSRAM4, FSMC_NORSRAMInitTypeDef::FSMC_BurstAccessMode, FSMC_BurstAccessMode_Disable, FSMC_NORSRAMTimingInitTypeDef::FSMC_BusTurnAroundDuration, FSMC_NORSRAMTimingInitTypeDef::FSMC_CLKDivision, FSMC_NORSRAMInitTypeDef::FSMC_DataAddressMux, FSMC_DataAddressMux_Disable, FSMC_NORSRAMTimingInitTypeDef::FSMC_DataLatency, FSMC_NORSRAMTimingInitTypeDef::FSMC_DataSetupTime, FSMC_NORSRAMInitTypeDef::FSMC_ExtendedMode, FSMC_ExtendedMode_Disable, FSMC_NORSRAMInitTypeDef::FSMC_MemoryDataWidth, FSMC_MemoryDataWidth_16b, FSMC_NORSRAMInitTypeDef::FSMC_MemoryType, FSMC_MemoryType_SRAM, FSMC_NORSRAMCmd(), FSMC_NORSRAMInit(), FSMC_NORSRAMInitTypeDef::FSMC_ReadWriteTimingStruct, FSMC_NORSRAMInitTypeDef::FSMC_WaitSignal, FSMC_WaitSignal_Disable, FSMC_NORSRAMInitTypeDef::FSMC_WaitSignalActive, FSMC_WaitSignalActive_BeforeWaitState, FSMC_NORSRAMInitTypeDef::FSMC_WaitSignalPolarity, FSMC_WaitSignalPolarity_Low, FSMC_NORSRAMInitTypeDef::FSMC_WrapMode, FSMC_WrapMode_Disable, FSMC_NORSRAMInitTypeDef::FSMC_WriteBurst, FSMC_WriteBurst_Disable, FSMC_NORSRAMInitTypeDef::FSMC_WriteOperation, FSMC_WriteOperation_Enable, and FSMC_NORSRAMInitTypeDef::FSMC_WriteTimingStruct.

void LCD_GetColors | ( | __IO uint16_t * | _TextColor,
 |  | __IO uint16_t * | _BackColor
 | ) |  |

Gets the LCD Text and Background colors.

Parameters:
_TextColor,: pointer to the variable that will contain the Text Color.
_BackColor,: pointer to the variable that will contain the Background Color.
Return values:
None

Definition at line 331 of file stm3210e_eval_lcd.c.

References BackColor, and TextColor.

sFONT* LCD_GetFont ( void )

Gets the Text Font.

Parameters:
None.
Return values:
the used font.

Definition at line 372 of file stm3210e_eval_lcd.c.

References LCD_Currentfonts.

void LCD_PolyLine | ( | pPoint | Points,
 |  | uint16_t | PointCount
 | ) |  |

Displays an polyline (between many points).

Parameters:
Points,: pointer to the points array.
PointCount,: Number of points.
Return values:
None

Definition at line 890 of file stm3210e_eval_lcd.c.

References LCD_DrawUniLine(), Point::X, and Point::Y.

void LCD_PolyLineRelative | ( | pPoint | Points,
 |  | uint16_t | PointCount
 | ) |  |

Displays a relative polyline (between many points).

Parameters:
Points,: pointer to the points array.
PointCount,: Number of points.
Return values:
None

Definition at line 958 of file stm3210e_eval_lcd.c.

References LCD_PolyLineRelativeClosed().

static void LCD_PolyLineRelativeClosed | ( | pPoint | Points,
 |  | uint16_t | PointCount,
 |  | uint16_t | Closed
 | ) |  | [static]

Displays an relative polyline (between many points).

Parameters:
Points,: pointer to the points array.
PointCount,: Number of points.
Closed,: specifies if the draw is closed or not. 1: closed, 0 : not closed.
Return values:
None

Definition at line 916 of file stm3210e_eval_lcd.c.

References LCD_DrawUniLine(), Point::X, and Point::Y.

Referenced by LCD_ClosedPolyLineRelative(), and LCD_PolyLineRelative().

void LCD_PowerOn ( void )

Power on the LCD.

Parameters:
None
Return values:
None

Definition at line 1153 of file stm3210e_eval_lcd.c.

References _delay_, LCD_REG_16, LCD_REG_17, LCD_REG_18, LCD_REG_19, LCD_REG_41, LCD_REG_7, and LCD_WriteReg().

uint16_t LCD_ReadRAM ( void )

Reads the LCD RAM.

Parameters:
None
Return values:
LCD RAM Value.

Definition at line 1139 of file stm3210e_eval_lcd.c.

References LCD, and LCD_REG_34.

uint16_t LCD_ReadReg ( uint8_t LCD_Reg )

Reads the selected LCD Register.

Parameters:
LCD_Reg,: address of the selected register.
Return values:
LCD Register Value.

Definition at line 1102 of file stm3210e_eval_lcd.c.

References LCD.

void LCD_SetBackColor ( __IO uint16_t Color )

Sets the Background color.

Parameters:
Color,: specifies the Background color code RGB(5-6-5).
Return values:
None

Definition at line 352 of file stm3210e_eval_lcd.c.

References BackColor.

void LCD_SetColors | ( | __IO uint16_t | _TextColor,
 |  | __IO uint16_t | _BackColor
 | ) |  |

Sets the LCD Text and Background colors.

Parameters:
_TextColor,: specifies the Text Color.
_BackColor,: specifies the Background Color.
Return values:
None

Definition at line 317 of file stm3210e_eval_lcd.c.

References BackColor, and TextColor.

void LCD_SetCursor | ( | uint8_t | Xpos,
 |  | uint16_t | Ypos
 | ) |  |

Sets the cursor position.

Parameters:
Xpos,: specifies the X position.
Ypos,: specifies the Y position.
Return values:
None

Definition at line 422 of file stm3210e_eval_lcd.c.

References LCD_REG_32, LCD_REG_33, and LCD_WriteReg().

void LCD_SetDisplayWindow | ( | uint8_t | Xpos,
 |  | uint16_t | Ypos,
 |  | uint8_t | Height,
 |  | uint16_t | Width
 | ) |  |

Sets a display window.

Parameters:
Xpos,: specifies the X buttom left position.
Ypos,: specifies the Y buttom left position.
Height,: display window height.
Width,: display window width.
Return values:
None

Definition at line 516 of file stm3210e_eval_lcd.c.

References LCD_REG_80, LCD_REG_81, LCD_REG_82, LCD_REG_83, LCD_SetCursor(), and LCD_WriteReg().

void LCD_SetFont ( sFONT * fonts )

Sets the Text Font.

Parameters:
fonts,: specifies the font to be used.
Return values:
None

Definition at line 362 of file stm3210e_eval_lcd.c.

void LCD_SetTextColor ( __IO uint16_t Color )

Sets the Text color.

Parameters:
Color,: specifies the Text color code RGB(5-6-5).
Return values:
None

Definition at line 341 of file stm3210e_eval_lcd.c.

References TextColor.

void LCD_WindowModeDisable ( void )

Disables LCD Window mode.

Parameters:
None
Return values:
None

Definition at line 549 of file stm3210e_eval_lcd.c.

References LCD_REG_3, LCD_SetDisplayWindow(), and LCD_WriteReg().

void LCD_WriteBMP ( uint32_t BmpAddress )

Displays a bitmap picture loaded in the internal Flash.

Parameters:
BmpAddress,: Bmp picture address in the internal Flash.
Return values:
None

Definition at line 698 of file stm3210e_eval_lcd.c.

References index, LCD_REG_3, LCD_WriteRAM(), LCD_WriteRAM_Prepare(), and LCD_WriteReg().

void LCD_WriteRAM ( uint16_t RGB_Code )

Writes to the LCD RAM.

Parameters:
RGB_Code,: the pixel color in RGB mode (5-6-5).
Return values:
None

Definition at line 1127 of file stm3210e_eval_lcd.c.

References LCD.

void LCD_WriteRAM_Prepare ( void )

Prepare to write to the LCD RAM.

Parameters:
None
Return values:
None

Definition at line 1116 of file stm3210e_eval_lcd.c.

References LCD, and LCD_REG_34.

void LCD_WriteReg | ( | uint8_t | LCD_Reg,
 |  | uint16_t | LCD_RegValue
 | ) |  |

Writes to the selected LCD register.

Parameters:
LCD_Reg,: address of the selected register.
LCD_RegValue,: value to write to the selected register.
Return values:
None

Definition at line 1088 of file stm3210e_eval_lcd.c.

References LCD.

static void PutPixel | ( | int16_t | x,
 |  | int16_t | y
 | ) |  | [static]

Displays a pixel.

Parameters:
x,: pixel x.
y,: pixel y.
Return values:
None

Definition at line 1286 of file stm3210e_eval_lcd.c.

References LCD_DIR_HORIZONTAL, and LCD_DrawLine().

Referenced by LCD_DrawUniLine(), and LCD_FillPolyLine().

void STM3210E_LCD_Init ( void )

Initializes the LCD.

Parameters:
None
Return values:
None

Definition at line 154 of file stm3210e_eval_lcd.c.

References _delay_, LCD_CtrlLinesConfig(), LCD_DEFAULT_FONT, LCD_FSMCConfig(), LCD_ReadReg(), LCD_REG_0, LCD_REG_1, LCD_REG_10, LCD_REG_106, LCD_REG_12, LCD_REG_128, LCD_REG_129, LCD_REG_13, LCD_REG_130, LCD_REG_131, LCD_REG_132, LCD_REG_133, LCD_REG_144, LCD_REG_146, LCD_REG_147, LCD_REG_149, LCD_REG_15, LCD_REG_151, LCD_REG_152, LCD_REG_16, LCD_REG_17, LCD_REG_18, LCD_REG_19, LCD_REG_2, LCD_REG_229, LCD_REG_3, LCD_REG_32, LCD_REG_33, LCD_REG_4, LCD_REG_41, LCD_REG_48, LCD_REG_49, LCD_REG_50, LCD_REG_51, LCD_REG_52, LCD_REG_53, LCD_REG_54, LCD_REG_55, LCD_REG_56, LCD_REG_57, LCD_REG_58, LCD_REG_59, LCD_REG_60, LCD_REG_61, LCD_REG_62, LCD_REG_63, LCD_REG_7, LCD_REG_8, LCD_REG_80, LCD_REG_81, LCD_REG_82, LCD_REG_83, LCD_REG_9, LCD_REG_96, LCD_REG_97, LCD_SetFont(), and LCD_WriteReg().

Referenced by main().


STM32F10x Standard Peripherals Firmware Library: STM3210E_EVAL_LCD_Exported_Types

Data Structures | Typedefs

STM3210E_EVAL_LCD_Exported_Types

STM3210E_EVAL_LCD

Data Structures

struct | Point

Typedefs

typedef struct Point * | pPoint

Typedef Documentation

typedef struct Point * pPoint


STM32F10x Standard Peripherals Firmware Library: STM3210E_EVAL_LCD_Exported_Constants

Defines

STM3210E_EVAL_LCD_Exported_Constants

STM3210E_EVAL_LCD

Defines

#define | _delay_ delay
Uncomment the line below if you want to use user defined Delay function (for precise timing), otherwise default _delay_ function defined within this driver is used (less precise timing).
#define | LCD_COLOR_BLACK 0x0000
#define | LCD_COLOR_BLUE 0x001F
#define | LCD_COLOR_BLUE2 0x051F
#define | LCD_COLOR_CYAN 0x7FFF
#define | LCD_COLOR_GREEN 0x07E0
#define | LCD_COLOR_GREY 0xF7DE
#define | LCD_COLOR_MAGENTA 0xF81F
#define | LCD_COLOR_RED 0xF800
#define | LCD_COLOR_WHITE 0xFFFF
LCD color.
#define | LCD_COLOR_YELLOW 0xFFE0
#define | LCD_DEFAULT_FONT Font16x24
LCD default font.
#define | LCD_DIR_HORIZONTAL 0x0000
LCD Direction.
#define | LCD_DIR_VERTICAL 0x0001
#define | LCD_LINE_0 LINE(0)
LCD Lines depending on the chosen fonts.
#define | LCD_LINE_1 LINE(1)
#define | LCD_LINE_10 LINE(10)
#define | LCD_LINE_11 LINE(11)
#define | LCD_LINE_12 LINE(12)
#define | LCD_LINE_13 LINE(13)
#define | LCD_LINE_14 LINE(14)
#define | LCD_LINE_15 LINE(15)
#define | LCD_LINE_16 LINE(16)
#define | LCD_LINE_17 LINE(17)
#define | LCD_LINE_18 LINE(18)
#define | LCD_LINE_19 LINE(19)
#define | LCD_LINE_2 LINE(2)
#define | LCD_LINE_20 LINE(20)
#define | LCD_LINE_21 LINE(21)
#define | LCD_LINE_22 LINE(22)
#define | LCD_LINE_23 LINE(23)
#define | LCD_LINE_24 LINE(24)
#define | LCD_LINE_25 LINE(25)
#define | LCD_LINE_26 LINE(26)
#define | LCD_LINE_27 LINE(27)
#define | LCD_LINE_28 LINE(28)
#define | LCD_LINE_29 LINE(29)
#define | LCD_LINE_3 LINE(3)
#define | LCD_LINE_4 LINE(4)
#define | LCD_LINE_5 LINE(5)
#define | LCD_LINE_6 LINE(6)
#define | LCD_LINE_7 LINE(7)
#define | LCD_LINE_8 LINE(8)
#define | LCD_LINE_9 LINE(9)
#define | LCD_PIXEL_HEIGHT 0x00F0
#define | LCD_PIXEL_WIDTH 0x0140
LCD Size (Width and Height)
#define | LCD_REG_0 0x00
LCD Registers.
#define | LCD_REG_1 0x01
#define | LCD_REG_10 0x0A
#define | LCD_REG_106 0x6A
#define | LCD_REG_118 0x76
#define | LCD_REG_12 0x0C
#define | LCD_REG_128 0x80
#define | LCD_REG_129 0x81
#define | LCD_REG_13 0x0D
#define | LCD_REG_130 0x82
#define | LCD_REG_131 0x83
#define | LCD_REG_132 0x84
#define | LCD_REG_133 0x85
#define | LCD_REG_134 0x86
#define | LCD_REG_135 0x87
#define | LCD_REG_136 0x88
#define | LCD_REG_137 0x89
#define | LCD_REG_139 0x8B
#define | LCD_REG_14 0x0E
#define | LCD_REG_140 0x8C
#define | LCD_REG_141 0x8D
#define | LCD_REG_143 0x8F
#define | LCD_REG_144 0x90
#define | LCD_REG_145 0x91
#define | LCD_REG_146 0x92
#define | LCD_REG_147 0x93
#define | LCD_REG_148 0x94
#define | LCD_REG_149 0x95
#define | LCD_REG_15 0x0F
#define | LCD_REG_150 0x96
#define | LCD_REG_151 0x97
#define | LCD_REG_152 0x98
#define | LCD_REG_153 0x99
#define | LCD_REG_154 0x9A
#define | LCD_REG_157 0x9D
#define | LCD_REG_16 0x10
#define | LCD_REG_17 0x11
#define | LCD_REG_18 0x12
#define | LCD_REG_19 0x13
#define | LCD_REG_192 0xC0
#define | LCD_REG_193 0xC1
#define | LCD_REG_2 0x02
#define | LCD_REG_20 0x14
#define | LCD_REG_21 0x15
#define | LCD_REG_22 0x16
#define | LCD_REG_229 0xE5
#define | LCD_REG_23 0x17
#define | LCD_REG_24 0x18
#define | LCD_REG_25 0x19
#define | LCD_REG_26 0x1A
#define | LCD_REG_27 0x1B
#define | LCD_REG_28 0x1C
#define | LCD_REG_29 0x1D
#define | LCD_REG_3 0x03
#define | LCD_REG_30 0x1E
#define | LCD_REG_31 0x1F
#define | LCD_REG_32 0x20
#define | LCD_REG_33 0x21
#define | LCD_REG_34 0x22
#define | LCD_REG_36 0x24
#define | LCD_REG_37 0x25
#define | LCD_REG_4 0x04
#define | LCD_REG_40 0x28
#define | LCD_REG_41 0x29
#define | LCD_REG_43 0x2B
#define | LCD_REG_45 0x2D
#define | LCD_REG_48 0x30
#define | LCD_REG_49 0x31
#define | LCD_REG_5 0x05
#define | LCD_REG_50 0x32
#define | LCD_REG_51 0x33
#define | LCD_REG_52 0x34
#define | LCD_REG_53 0x35
#define | LCD_REG_54 0x36
#define | LCD_REG_55 0x37
#define | LCD_REG_56 0x38
#define | LCD_REG_57 0x39
#define | LCD_REG_58 0x3A
#define | LCD_REG_59 0x3B
#define | LCD_REG_6 0x06
#define | LCD_REG_60 0x3C
#define | LCD_REG_61 0x3D
#define | LCD_REG_62 0x3E
#define | LCD_REG_63 0x3F
#define | LCD_REG_64 0x40
#define | LCD_REG_65 0x41
#define | LCD_REG_66 0x42
#define | LCD_REG_67 0x43
#define | LCD_REG_68 0x44
#define | LCD_REG_69 0x45
#define | LCD_REG_7 0x07
#define | LCD_REG_70 0x46
#define | LCD_REG_71 0x47
#define | LCD_REG_72 0x48
#define | LCD_REG_73 0x49
#define | LCD_REG_74 0x4A
#define | LCD_REG_75 0x4B
#define | LCD_REG_76 0x4C
#define | LCD_REG_77 0x4D
#define | LCD_REG_78 0x4E
#define | LCD_REG_79 0x4F
#define | LCD_REG_8 0x08
#define | LCD_REG_80 0x50
#define | LCD_REG_81 0x51
#define | LCD_REG_82 0x52
#define | LCD_REG_83 0x53
#define | LCD_REG_9 0x09
#define | LCD_REG_96 0x60
#define | LCD_REG_97 0x61

Define Documentation

#define _delay_ delay

Uncomment the line below if you want to use user defined Delay function (for precise timing), otherwise default _delay_ function defined within this driver is used (less precise timing).

Definition at line 79 of file stm3210e_eval_lcd.h.

#define LCD_COLOR_BLACK 0x0000

Definition at line 199 of file stm3210e_eval_lcd.h.

#define LCD_COLOR_BLUE 0x001F

Definition at line 201 of file stm3210e_eval_lcd.h.

#define LCD_COLOR_BLUE2 0x051F

Definition at line 202 of file stm3210e_eval_lcd.h.

#define LCD_COLOR_CYAN 0x7FFF

Definition at line 206 of file stm3210e_eval_lcd.h.

#define LCD_COLOR_GREEN 0x07E0

Definition at line 205 of file stm3210e_eval_lcd.h.

#define LCD_COLOR_GREY 0xF7DE

Definition at line 200 of file stm3210e_eval_lcd.h.

#define LCD_COLOR_MAGENTA 0xF81F

Definition at line 204 of file stm3210e_eval_lcd.h.

#define LCD_COLOR_RED 0xF800

Definition at line 203 of file stm3210e_eval_lcd.h.

#define LCD_COLOR_WHITE 0xFFFF

LCD color.

Definition at line 198 of file stm3210e_eval_lcd.h.

#define LCD_COLOR_YELLOW 0xFFE0

Definition at line 207 of file stm3210e_eval_lcd.h.

#define LCD_DEFAULT_FONT Font16x24

LCD default font.

Definition at line 246 of file stm3210e_eval_lcd.h.

#define LCD_DIR_HORIZONTAL 0x0000

LCD Direction.

Definition at line 251 of file stm3210e_eval_lcd.h.

#define LCD_DIR_VERTICAL 0x0001

Definition at line 252 of file stm3210e_eval_lcd.h.

#define LCD_LINE_0 LINE(0)

LCD Lines depending on the chosen fonts.

Definition at line 212 of file stm3210e_eval_lcd.h.

#define LCD_LINE_1 LINE(1)

Definition at line 213 of file stm3210e_eval_lcd.h.

#define LCD_LINE_10 LINE(10)

Definition at line 222 of file stm3210e_eval_lcd.h.

#define LCD_LINE_11 LINE(11)

Definition at line 223 of file stm3210e_eval_lcd.h.

#define LCD_LINE_12 LINE(12)

Definition at line 224 of file stm3210e_eval_lcd.h.

#define LCD_LINE_13 LINE(13)

Definition at line 225 of file stm3210e_eval_lcd.h.

#define LCD_LINE_14 LINE(14)

Definition at line 226 of file stm3210e_eval_lcd.h.

#define LCD_LINE_15 LINE(15)

Definition at line 227 of file stm3210e_eval_lcd.h.

#define LCD_LINE_16 LINE(16)

Definition at line 228 of file stm3210e_eval_lcd.h.

#define LCD_LINE_17 LINE(17)

Definition at line 229 of file stm3210e_eval_lcd.h.

#define LCD_LINE_18 LINE(18)

Definition at line 230 of file stm3210e_eval_lcd.h.

#define LCD_LINE_19 LINE(19)

Definition at line 231 of file stm3210e_eval_lcd.h.

#define LCD_LINE_2 LINE(2)

Definition at line 214 of file stm3210e_eval_lcd.h.

#define LCD_LINE_20 LINE(20)

Definition at line 232 of file stm3210e_eval_lcd.h.

#define LCD_LINE_21 LINE(21)

Definition at line 233 of file stm3210e_eval_lcd.h.

#define LCD_LINE_22 LINE(22)

Definition at line 234 of file stm3210e_eval_lcd.h.

#define LCD_LINE_23 LINE(23)

Definition at line 235 of file stm3210e_eval_lcd.h.

#define LCD_LINE_24 LINE(24)

Definition at line 236 of file stm3210e_eval_lcd.h.

#define LCD_LINE_25 LINE(25)

Definition at line 237 of file stm3210e_eval_lcd.h.

#define LCD_LINE_26 LINE(26)

Definition at line 238 of file stm3210e_eval_lcd.h.

#define LCD_LINE_27 LINE(27)

Definition at line 239 of file stm3210e_eval_lcd.h.

#define LCD_LINE_28 LINE(28)

Definition at line 240 of file stm3210e_eval_lcd.h.

#define LCD_LINE_29 LINE(29)

Definition at line 241 of file stm3210e_eval_lcd.h.

#define LCD_LINE_3 LINE(3)

Definition at line 215 of file stm3210e_eval_lcd.h.

#define LCD_LINE_4 LINE(4)

Definition at line 216 of file stm3210e_eval_lcd.h.

#define LCD_LINE_5 LINE(5)

Definition at line 217 of file stm3210e_eval_lcd.h.

#define LCD_LINE_6 LINE(6)

Definition at line 218 of file stm3210e_eval_lcd.h.

#define LCD_LINE_7 LINE(7)

Definition at line 219 of file stm3210e_eval_lcd.h.

#define LCD_LINE_8 LINE(8)

Definition at line 220 of file stm3210e_eval_lcd.h.

#define LCD_LINE_9 LINE(9)

Definition at line 221 of file stm3210e_eval_lcd.h.

#define LCD_PIXEL_HEIGHT 0x00F0

Definition at line 258 of file stm3210e_eval_lcd.h.

#define LCD_PIXEL_WIDTH 0x0140

LCD Size (Width and Height)

Definition at line 257 of file stm3210e_eval_lcd.h.

#define LCD_REG_0 0x00

LCD Registers.

Definition at line 85 of file stm3210e_eval_lcd.h.

#define LCD_REG_1 0x01

Definition at line 86 of file stm3210e_eval_lcd.h.

#define LCD_REG_10 0x0A

Definition at line 95 of file stm3210e_eval_lcd.h.

#define LCD_REG_106 0x6A

Definition at line 163 of file stm3210e_eval_lcd.h.

#define LCD_REG_118 0x76

Definition at line 164 of file stm3210e_eval_lcd.h.

#define LCD_REG_12 0x0C

Definition at line 96 of file stm3210e_eval_lcd.h.

#define LCD_REG_128 0x80

Definition at line 165 of file stm3210e_eval_lcd.h.

#define LCD_REG_129 0x81

Definition at line 166 of file stm3210e_eval_lcd.h.

#define LCD_REG_13 0x0D

Definition at line 97 of file stm3210e_eval_lcd.h.

#define LCD_REG_130 0x82

Definition at line 167 of file stm3210e_eval_lcd.h.

#define LCD_REG_131 0x83

Definition at line 168 of file stm3210e_eval_lcd.h.

#define LCD_REG_132 0x84

Definition at line 169 of file stm3210e_eval_lcd.h.

#define LCD_REG_133 0x85

Definition at line 170 of file stm3210e_eval_lcd.h.

#define LCD_REG_134 0x86

Definition at line 171 of file stm3210e_eval_lcd.h.

#define LCD_REG_135 0x87

Definition at line 172 of file stm3210e_eval_lcd.h.

#define LCD_REG_136 0x88

Definition at line 173 of file stm3210e_eval_lcd.h.

#define LCD_REG_137 0x89

Definition at line 174 of file stm3210e_eval_lcd.h.

#define LCD_REG_139 0x8B

Definition at line 175 of file stm3210e_eval_lcd.h.

#define LCD_REG_14 0x0E

Definition at line 98 of file stm3210e_eval_lcd.h.

#define LCD_REG_140 0x8C

Definition at line 176 of file stm3210e_eval_lcd.h.

#define LCD_REG_141 0x8D

Definition at line 177 of file stm3210e_eval_lcd.h.

#define LCD_REG_143 0x8F

Definition at line 178 of file stm3210e_eval_lcd.h.

#define LCD_REG_144 0x90

Definition at line 179 of file stm3210e_eval_lcd.h.

#define LCD_REG_145 0x91

Definition at line 180 of file stm3210e_eval_lcd.h.

#define LCD_REG_146 0x92

Definition at line 181 of file stm3210e_eval_lcd.h.

#define LCD_REG_147 0x93

Definition at line 182 of file stm3210e_eval_lcd.h.

#define LCD_REG_148 0x94

Definition at line 183 of file stm3210e_eval_lcd.h.

#define LCD_REG_149 0x95

Definition at line 184 of file stm3210e_eval_lcd.h.

#define LCD_REG_15 0x0F

Definition at line 99 of file stm3210e_eval_lcd.h.

#define LCD_REG_150 0x96

Definition at line 185 of file stm3210e_eval_lcd.h.

#define LCD_REG_151 0x97

Definition at line 186 of file stm3210e_eval_lcd.h.

#define LCD_REG_152 0x98

Definition at line 187 of file stm3210e_eval_lcd.h.

#define LCD_REG_153 0x99

Definition at line 188 of file stm3210e_eval_lcd.h.

#define LCD_REG_154 0x9A

Definition at line 189 of file stm3210e_eval_lcd.h.

#define LCD_REG_157 0x9D

Definition at line 190 of file stm3210e_eval_lcd.h.

#define LCD_REG_16 0x10

Definition at line 100 of file stm3210e_eval_lcd.h.

#define LCD_REG_17 0x11

Definition at line 101 of file stm3210e_eval_lcd.h.

#define LCD_REG_18 0x12

Definition at line 102 of file stm3210e_eval_lcd.h.

#define LCD_REG_19 0x13

Definition at line 103 of file stm3210e_eval_lcd.h.

#define LCD_REG_192 0xC0

Definition at line 191 of file stm3210e_eval_lcd.h.

#define LCD_REG_193 0xC1

Definition at line 192 of file stm3210e_eval_lcd.h.

#define LCD_REG_2 0x02

Definition at line 87 of file stm3210e_eval_lcd.h.

#define LCD_REG_20 0x14

Definition at line 104 of file stm3210e_eval_lcd.h.

#define LCD_REG_21 0x15

Definition at line 105 of file stm3210e_eval_lcd.h.

#define LCD_REG_22 0x16

Definition at line 106 of file stm3210e_eval_lcd.h.

#define LCD_REG_229 0xE5

Definition at line 193 of file stm3210e_eval_lcd.h.

#define LCD_REG_23 0x17

Definition at line 107 of file stm3210e_eval_lcd.h.

#define LCD_REG_24 0x18

Definition at line 108 of file stm3210e_eval_lcd.h.

#define LCD_REG_25 0x19

Definition at line 109 of file stm3210e_eval_lcd.h.

#define LCD_REG_26 0x1A

Definition at line 110 of file stm3210e_eval_lcd.h.

#define LCD_REG_27 0x1B

Definition at line 111 of file stm3210e_eval_lcd.h.

#define LCD_REG_28 0x1C

Definition at line 112 of file stm3210e_eval_lcd.h.

#define LCD_REG_29 0x1D

Definition at line 113 of file stm3210e_eval_lcd.h.

#define LCD_REG_3 0x03

Definition at line 88 of file stm3210e_eval_lcd.h.

#define LCD_REG_30 0x1E

Definition at line 114 of file stm3210e_eval_lcd.h.

#define LCD_REG_31 0x1F

Definition at line 115 of file stm3210e_eval_lcd.h.

#define LCD_REG_32 0x20

Definition at line 116 of file stm3210e_eval_lcd.h.

#define LCD_REG_33 0x21

Definition at line 117 of file stm3210e_eval_lcd.h.

#define LCD_REG_34 0x22

Definition at line 118 of file stm3210e_eval_lcd.h.

#define LCD_REG_36 0x24

Definition at line 119 of file stm3210e_eval_lcd.h.

#define LCD_REG_37 0x25

Definition at line 120 of file stm3210e_eval_lcd.h.

#define LCD_REG_4 0x04

Definition at line 89 of file stm3210e_eval_lcd.h.

#define LCD_REG_40 0x28

Definition at line 121 of file stm3210e_eval_lcd.h.

#define LCD_REG_41 0x29

Definition at line 122 of file stm3210e_eval_lcd.h.

#define LCD_REG_43 0x2B

Definition at line 123 of file stm3210e_eval_lcd.h.

#define LCD_REG_45 0x2D

Definition at line 124 of file stm3210e_eval_lcd.h.

#define LCD_REG_48 0x30

Definition at line 125 of file stm3210e_eval_lcd.h.

#define LCD_REG_49 0x31

Definition at line 126 of file stm3210e_eval_lcd.h.

#define LCD_REG_5 0x05

Definition at line 90 of file stm3210e_eval_lcd.h.

#define LCD_REG_50 0x32

Definition at line 127 of file stm3210e_eval_lcd.h.

#define LCD_REG_51 0x33

Definition at line 128 of file stm3210e_eval_lcd.h.

#define LCD_REG_52 0x34

Definition at line 129 of file stm3210e_eval_lcd.h.

#define LCD_REG_53 0x35

Definition at line 130 of file stm3210e_eval_lcd.h.

#define LCD_REG_54 0x36

Definition at line 131 of file stm3210e_eval_lcd.h.

#define LCD_REG_55 0x37

Definition at line 132 of file stm3210e_eval_lcd.h.

#define LCD_REG_56 0x38

Definition at line 133 of file stm3210e_eval_lcd.h.

#define LCD_REG_57 0x39

Definition at line 134 of file stm3210e_eval_lcd.h.

#define LCD_REG_58 0x3A

Definition at line 135 of file stm3210e_eval_lcd.h.

#define LCD_REG_59 0x3B

Definition at line 136 of file stm3210e_eval_lcd.h.

#define LCD_REG_6 0x06

Definition at line 91 of file stm3210e_eval_lcd.h.

#define LCD_REG_60 0x3C

Definition at line 137 of file stm3210e_eval_lcd.h.

#define LCD_REG_61 0x3D

Definition at line 138 of file stm3210e_eval_lcd.h.

#define LCD_REG_62 0x3E

Definition at line 139 of file stm3210e_eval_lcd.h.

#define LCD_REG_63 0x3F

Definition at line 140 of file stm3210e_eval_lcd.h.

#define LCD_REG_64 0x40

Definition at line 141 of file stm3210e_eval_lcd.h.

#define LCD_REG_65 0x41

Definition at line 142 of file stm3210e_eval_lcd.h.

#define LCD_REG_66 0x42

Definition at line 143 of file stm3210e_eval_lcd.h.

#define LCD_REG_67 0x43

Definition at line 144 of file stm3210e_eval_lcd.h.

#define LCD_REG_68 0x44

Definition at line 145 of file stm3210e_eval_lcd.h.

#define LCD_REG_69 0x45

Definition at line 146 of file stm3210e_eval_lcd.h.

#define LCD_REG_7 0x07

Definition at line 92 of file stm3210e_eval_lcd.h.

#define LCD_REG_70 0x46

Definition at line 147 of file stm3210e_eval_lcd.h.

#define LCD_REG_71 0x47

Definition at line 148 of file stm3210e_eval_lcd.h.

#define LCD_REG_72 0x48

Definition at line 149 of file stm3210e_eval_lcd.h.

#define LCD_REG_73 0x49

Definition at line 150 of file stm3210e_eval_lcd.h.

#define LCD_REG_74 0x4A

Definition at line 151 of file stm3210e_eval_lcd.h.

#define LCD_REG_75 0x4B

Definition at line 152 of file stm3210e_eval_lcd.h.

#define LCD_REG_76 0x4C

Definition at line 153 of file stm3210e_eval_lcd.h.

#define LCD_REG_77 0x4D

Definition at line 154 of file stm3210e_eval_lcd.h.

#define LCD_REG_78 0x4E

Definition at line 155 of file stm3210e_eval_lcd.h.

#define LCD_REG_79 0x4F

Definition at line 156 of file stm3210e_eval_lcd.h.

#define LCD_REG_8 0x08

Definition at line 93 of file stm3210e_eval_lcd.h.

#define LCD_REG_80 0x50

Definition at line 157 of file stm3210e_eval_lcd.h.

#define LCD_REG_81 0x51

Definition at line 158 of file stm3210e_eval_lcd.h.

#define LCD_REG_82 0x52

Definition at line 159 of file stm3210e_eval_lcd.h.

#define LCD_REG_83 0x53

Definition at line 160 of file stm3210e_eval_lcd.h.

#define LCD_REG_9 0x09

Definition at line 94 of file stm3210e_eval_lcd.h.

#define LCD_REG_96 0x60

Definition at line 161 of file stm3210e_eval_lcd.h.

#define LCD_REG_97 0x61

Definition at line 162 of file stm3210e_eval_lcd.h.


STM32F10x Standard Peripherals Firmware Library: STM3210E_EVAL_LCD_Exported_Macros

Defines

STM3210E_EVAL_LCD_Exported_Macros

STM3210E_EVAL_LCD

Defines

#define ASSEMBLE_RGB(R, G, B) ((((R)& 0xF8) << 8) | (((G) & 0xFC) << 3) | (((B) & 0xF8) >> 3))

Define Documentation

#define ASSEMBLE_RGB | ( | R,
 |  | G,
 |  | B
 | ) | ((((R)& 0xF8) << 8) | (((G) & 0xFC) << 3) | (((B) & 0xF8) >> 3))

Definition at line 267 of file stm3210e_eval_lcd.h.


STM32F10x Standard Peripherals Firmware Library: STM3210E_EVAL_LCD_Exported_Functions

STM3210E_EVAL_LCD_Exported_Functions

STM3210E_EVAL_LCD


STM32F10x Standard Peripherals Firmware Library: STM3210E_EVAL_FSMC_NAND_Private_Types

STM3210E_EVAL_FSMC_NAND_Private_Types

STM3210E_EVAL_FSMC_NAND


STM32F10x Standard Peripherals Firmware Library: STM3210E_EVAL_FSMC_NAND_Private_Defines

Defines

STM3210E_EVAL_FSMC_NAND_Private_Defines

STM3210E_EVAL_FSMC_NAND

Defines

#define | Bank2_NAND_ADDR ((uint32_t)0x70000000)
#define | Bank_NAND_ADDR Bank2_NAND_ADDR
#define | FSMC_Bank_NAND FSMC_Bank2_NAND
FSMC Bank 2.

Define Documentation

#define Bank2_NAND_ADDR ((uint32_t)0x70000000)

Definition at line 60 of file stm3210e_eval_fsmc_nand.c.

#define Bank_NAND_ADDR Bank2_NAND_ADDR

Definition at line 59 of file stm3210e_eval_fsmc_nand.c.

Referenced by NAND_EraseBlock(), NAND_ReadID(), NAND_ReadSmallPage(), NAND_ReadSpareArea(), NAND_ReadStatus(), NAND_Reset(), NAND_WriteSmallPage(), and NAND_WriteSpareArea().

#define FSMC_Bank_NAND FSMC_Bank2_NAND

FSMC Bank 2.

Definition at line 58 of file stm3210e_eval_fsmc_nand.c.


STM32F10x Standard Peripherals Firmware Library: STM3210E_EVAL_FSMC_NAND_Private_Macros

Defines

STM3210E_EVAL_FSMC_NAND_Private_Macros

STM3210E_EVAL_FSMC_NAND

Defines

#define ROW_ADDRESS (Address.Page + (Address.Block + (Address.Zone * NAND_ZONE_SIZE)) * NAND_BLOCK_SIZE)

Define Documentation

#define ROW_ADDRESS (Address.Page + (Address.Block + (Address.Zone * NAND_ZONE_SIZE)) * NAND_BLOCK_SIZE)

Definition at line 68 of file stm3210e_eval_fsmc_nand.c.

Referenced by NAND_EraseBlock(), NAND_ReadSmallPage(), NAND_ReadSpareArea(), NAND_WriteSmallPage(), and NAND_WriteSpareArea().


STM32F10x Standard Peripherals Firmware Library: STM3210E_EVAL_FSMC_NAND_Private_Variables

STM3210E_EVAL_FSMC_NAND_Private_Variables

STM3210E_EVAL_FSMC_NAND


STM32F10x Standard Peripherals Firmware Library: STM3210E_EVAL_FSMC_NAND_Private_Function_Prototypes

STM3210E_EVAL_FSMC_NAND_Private_Function_Prototypes

STM3210E_EVAL_FSMC_NAND


STM32F10x Standard Peripherals Firmware Library: STM3210E_EVAL_FSMC_NAND_Private_Functions

Functions

STM3210E_EVAL_FSMC_NAND_Private_Functions

STM3210E_EVAL_FSMC_NAND

Functions

uint32_t | NAND_AddressIncrement (NAND_ADDRESS *Address)
Increment the NAND memory address.
uint32_t | NAND_EraseBlock (NAND_ADDRESS Address)
This routine erase complete block from NAND FLASH.
uint32_t | NAND_GetStatus (void)
Get the NAND operation status.
void | NAND_Init (void)
Configures the FSMC and GPIOs to interface with the NAND memory.
void | NAND_ReadID (NAND_IDTypeDef *NAND_ID)
Reads NAND memory's ID.
uint32_t | NAND_ReadSmallPage (uint8_t *pBuffer, NAND_ADDRESS Address, uint32_t NumPageToRead)
This routine is for sequential read from one or several 512 Bytes Page size.
uint32_t | NAND_ReadSpareArea (uint8_t *pBuffer, NAND_ADDRESS Address, uint32_t NumSpareAreaToRead)
This routine read the spare area information from the specified pages addresses.
uint32_t | NAND_ReadStatus (void)
Reads the NAND memory status using the Read status command.
uint32_t | NAND_Reset (void)
This routine reset the NAND FLASH.
uint32_t | NAND_WriteSmallPage (uint8_t *pBuffer, NAND_ADDRESS Address, uint32_t NumPageToWrite)
This routine is for writing one or several 512 Bytes Page size.
uint32_t | NAND_WriteSpareArea (uint8_t *pBuffer, NAND_ADDRESS Address, uint32_t NumSpareAreaTowrite)
This routine write the spare area information for the specified pages addresses.

Function Documentation

uint32_t NAND_AddressIncrement ( NAND_ADDRESS * Address )

Increment the NAND memory address.

Parameters:
Address,: address to be incremented.
Return values:
The new status of the increment address operation. It can be:

  • NAND_VALID_ADDRESS: When the new address is valid address
  • NAND_INVALID_ADDRESS: When the new address is invalid address

Definition at line 500 of file stm3210e_eval_fsmc_nand.c.

References NAND_ADDRESS::Block, NAND_BLOCK_SIZE, NAND_INVALID_ADDRESS, NAND_MAX_ZONE, NAND_VALID_ADDRESS, NAND_ZONE_SIZE, NAND_ADDRESS::Page, status, and NAND_ADDRESS::Zone.

Referenced by NAND_ReadSmallPage(), NAND_ReadSpareArea(), NAND_WriteSmallPage(), and NAND_WriteSpareArea().

uint32_t NAND_EraseBlock ( NAND_ADDRESS Address )

This routine erase complete block from NAND FLASH.

Parameters:
Address,: Any address into block to be erased
Return values:
New status of the NAND operation. This parameter can be:

  • NAND_TIMEOUT_ERROR: when the previous operation generate a Timeout error
  • NAND_READY: when memory is ready for the next operation

Definition at line 406 of file stm3210e_eval_fsmc_nand.c.

References ADDR_1st_CYCLE, ADDR_2nd_CYCLE, ADDR_3rd_CYCLE, ADDR_AREA, Bank_NAND_ADDR, CMD_AREA, NAND_CMD_ERASE0, NAND_CMD_ERASE1, NAND_GetStatus(), and ROW_ADDRESS.

Referenced by main().

uint32_t NAND_GetStatus ( void )

Get the NAND operation status.

Parameters:
None
Return values:
New status of the NAND operation. This parameter can be:

  • NAND_TIMEOUT_ERROR: when the previous operation generate a Timeout error
  • NAND_READY: when memory is ready for the next operation

< Wait for a NAND operation to complete or a TIMEOUT to occur

Definition at line 439 of file stm3210e_eval_fsmc_nand.c.

References NAND_ReadStatus(), NAND_READY, NAND_TIMEOUT_ERROR, and status.

Referenced by NAND_EraseBlock(), NAND_ReadSmallPage(), NAND_ReadSpareArea(), NAND_WriteSmallPage(), and NAND_WriteSpareArea().

void NAND_Init ( void )

Configures the FSMC and GPIOs to interface with the NAND memory.

This function must be called before any write/read operation on the NAND.

Parameters:
None
Return values:
None

< CLE, ALE, D0->D3, NOE, NWE and NCE2 NAND pin configuration

< D4->D7 NAND pin configuration

< NWAIT NAND pin configuration

< INT2 NAND pin configuration

< FSMC NAND Bank Cmd Test

Definition at line 101 of file stm3210e_eval_fsmc_nand.c.

References ENABLE, FSMC_NANDInitTypeDef::FSMC_AttributeSpaceTimingStruct, FSMC_NANDInitTypeDef::FSMC_Bank, FSMC_Bank2_NAND, FSMC_NANDInitTypeDef::FSMC_CommonSpaceTimingStruct, FSMC_NANDInitTypeDef::FSMC_ECC, FSMC_ECC_Enable, FSMC_NANDInitTypeDef::FSMC_ECCPageSize, FSMC_ECCPageSize_512Bytes, FSMC_NAND_PCCARDTimingInitTypeDef::FSMC_HiZSetupTime, FSMC_NAND_PCCARDTimingInitTypeDef::FSMC_HoldSetupTime, FSMC_NANDInitTypeDef::FSMC_MemoryDataWidth, FSMC_MemoryDataWidth_8b, FSMC_NANDCmd(), FSMC_NANDInit(), FSMC_NAND_PCCARDTimingInitTypeDef::FSMC_SetupTime, FSMC_NANDInitTypeDef::FSMC_TARSetupTime, FSMC_NANDInitTypeDef::FSMC_TCLRSetupTime, FSMC_NANDInitTypeDef::FSMC_Waitfeature, FSMC_Waitfeature_Enable, FSMC_NAND_PCCARDTimingInitTypeDef::FSMC_WaitSetupTime, GPIO_Init(), GPIO_InitStructure, GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_AF_PP, GPIO_Mode_IPU, GPIO_InitTypeDef::GPIO_Pin, GPIO_Pin_0, GPIO_Pin_1, GPIO_Pin_10, GPIO_Pin_11, GPIO_Pin_12, GPIO_Pin_14, GPIO_Pin_15, GPIO_Pin_4, GPIO_Pin_5, GPIO_Pin_6, GPIO_Pin_7, GPIO_Pin_8, GPIO_Pin_9, GPIO_InitTypeDef::GPIO_Speed, GPIO_Speed_50MHz, GPIOD, GPIOE, GPIOG, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE, RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, and RCC_APB2PeriphClockCmd().

Referenced by main().

void NAND_ReadID ( NAND_IDTypeDef * NAND_ID )

Reads NAND memory's ID.

Parameters:
NAND_ID,: pointer to a NAND_IDTypeDef structure which will hold the Manufacturer and Device ID.
Return values:
None

< Send Command to the command area

< Sequence to read ID from NAND flash

Definition at line 165 of file stm3210e_eval_fsmc_nand.c.

References ADDR_1st_CYCLE, ADDR_2nd_CYCLE, ADDR_3rd_CYCLE, ADDR_4th_CYCLE, ADDR_AREA, Bank_NAND_ADDR, CMD_AREA, DATA_AREA, NAND_IDTypeDef::Device_ID, NAND_IDTypeDef::Fourth_ID, NAND_IDTypeDef::Maker_ID, and NAND_IDTypeDef::Third_ID.

Referenced by main().

uint32_t NAND_ReadSmallPage | ( | uint8_t * | pBuffer,
 |  | NAND_ADDRESS | Address,
 |  | uint32_t | NumPageToRead
 | ) |  |

This routine is for sequential read from one or several 512 Bytes Page size.

Parameters:
pBuffer,: pointer on the Buffer to fill
Address,: First page address
NumPageToRead,: Number of page to read
Return values:
New status of the NAND operation. This parameter can be:

  • NAND_TIMEOUT_ERROR: when the previous operation generate a Timeout error
  • NAND_READY: when memory is ready for the next operation And the new status of the increment address operation. It can be:
  • NAND_VALID_ADDRESS: When the new address is valid address
  • NAND_INVALID_ADDRESS: When the new address is invalid address

< Page Read command and page address

< Calculate the size

< Get Data into Buffer

< Calculate page address

Definition at line 252 of file stm3210e_eval_fsmc_nand.c.

References ADDR_1st_CYCLE, ADDR_2nd_CYCLE, ADDR_3rd_CYCLE, ADDR_AREA, Bank_NAND_ADDR, CMD_AREA, DATA_AREA, index, NAND_AddressIncrement(), NAND_CMD_AREA_A, NAND_GetStatus(), NAND_PAGE_SIZE, NAND_READY, NAND_VALID_ADDRESS, ROW_ADDRESS, and status.

Referenced by main().

uint32_t NAND_ReadSpareArea | ( | uint8_t * | pBuffer,
 |  | NAND_ADDRESS | Address,
 |  | uint32_t | NumSpareAreaToRead
 | ) |  |

This routine read the spare area information from the specified pages addresses.

Parameters:
pBuffer,: pointer on the Buffer to fill
Address,: First page address
NumSpareAreaToRead,: Number of Spare Area to read
Return values:
New status of the NAND operation. This parameter can be:

  • NAND_TIMEOUT_ERROR: when the previous operation generate a Timeout error
  • NAND_READY: when memory is ready for the next operation And the new status of the increment address operation. It can be:
  • NAND_VALID_ADDRESS: When the new address is valid address
  • NAND_INVALID_ADDRESS: When the new address is invalid address

< Page Read command and page address

< Data Read

< Get Data into Buffer

< Calculate page address

Definition at line 361 of file stm3210e_eval_fsmc_nand.c.

References ADDR_1st_CYCLE, ADDR_2nd_CYCLE, ADDR_3rd_CYCLE, ADDR_AREA, Bank_NAND_ADDR, CMD_AREA, DATA_AREA, index, NAND_AddressIncrement(), NAND_CMD_AREA_C, NAND_GetStatus(), NAND_READY, NAND_SPARE_AREA_SIZE, NAND_VALID_ADDRESS, ROW_ADDRESS, and status.

uint32_t NAND_ReadStatus ( void )

Reads the NAND memory status using the Read status command.

Parameters:
None
Return values:
The status of the NAND memory. This parameter can be:

  • NAND_BUSY: when memory is busy
  • NAND_READY: when memory is ready for the next operation
  • NAND_ERROR: when the previous operation gererates error

< Read status operation ------------------------------------

Definition at line 469 of file stm3210e_eval_fsmc_nand.c.

References Bank_NAND_ADDR, CMD_AREA, NAND_BUSY, NAND_CMD_STATUS, NAND_ERROR, NAND_READY, and status.

Referenced by NAND_GetStatus().

uint32_t NAND_Reset ( void )

This routine reset the NAND FLASH.

Parameters:
None
Return values:
NAND_READY

Definition at line 424 of file stm3210e_eval_fsmc_nand.c.

References Bank_NAND_ADDR, CMD_AREA, NAND_CMD_RESET, and NAND_READY.

uint32_t NAND_WriteSmallPage | ( | uint8_t * | pBuffer,
 |  | NAND_ADDRESS | Address,
 |  | uint32_t | NumPageToWrite
 | ) |  |

This routine is for writing one or several 512 Bytes Page size.

Parameters:
pBuffer,: pointer on the Buffer containing data to be written
Address,: First page address
NumPageToWrite,: Number of page to write
Return values:
New status of the NAND operation. This parameter can be:

  • NAND_TIMEOUT_ERROR: when the previous operation generate a Timeout error
  • NAND_READY: when memory is ready for the next operation And the new status of the increment address operation. It can be:
  • NAND_VALID_ADDRESS: When the new address is valid address
  • NAND_INVALID_ADDRESS: When the new address is invalid address

< Page write command and address

< Calculate the size

< Write data

< Check status for successful operation

< Calculate Next small page Address

Definition at line 195 of file stm3210e_eval_fsmc_nand.c.

References ADDR_1st_CYCLE, ADDR_2nd_CYCLE, ADDR_3rd_CYCLE, ADDR_AREA, Bank_NAND_ADDR, CMD_AREA, DATA_AREA, index, NAND_AddressIncrement(), NAND_CMD_AREA_A, NAND_CMD_WRITE0, NAND_CMD_WRITE_TRUE1, NAND_GetStatus(), NAND_PAGE_SIZE, NAND_READY, NAND_VALID_ADDRESS, ROW_ADDRESS, and status.

Referenced by main().

uint32_t NAND_WriteSpareArea | ( | uint8_t * | pBuffer,
 |  | NAND_ADDRESS | Address,
 |  | uint32_t | NumSpareAreaTowrite
 | ) |  |

This routine write the spare area information for the specified pages addresses.

Parameters:
pBuffer,: pointer on the Buffer containing data to be written
Address,: First page address
NumSpareAreaTowrite,: Number of Spare Area to write
Return values:
New status of the NAND operation. This parameter can be:

  • NAND_TIMEOUT_ERROR: when the previous operation generate a Timeout error
  • NAND_READY: when memory is ready for the next operation And the new status of the increment address operation. It can be:
  • NAND_VALID_ADDRESS: When the new address is valid address
  • NAND_INVALID_ADDRESS: When the new address is invalid address

< Page write Spare area command and address

< Calculate the size

< Write the data

< Check status for successful operation

< Calculate Next page Address

Definition at line 303 of file stm3210e_eval_fsmc_nand.c.

References ADDR_1st_CYCLE, ADDR_2nd_CYCLE, ADDR_3rd_CYCLE, ADDR_AREA, Bank_NAND_ADDR, CMD_AREA, DATA_AREA, index, NAND_AddressIncrement(), NAND_CMD_AREA_C, NAND_CMD_WRITE0, NAND_CMD_WRITE_TRUE1, NAND_GetStatus(), NAND_READY, NAND_SPARE_AREA_SIZE, NAND_VALID_ADDRESS, ROW_ADDRESS, and status.


STM32F10x Standard Peripherals Firmware Library: NAND_ADDRESS Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

NAND_ADDRESS Struct Reference
STM3210E_EVAL_FSMC_NAND_Exported_Types

#include <stm3210e_eval_fsmc_nand.h>

Data Fields

uint16_t | Block
uint16_t | Page
uint16_t | Zone

Detailed Description

Definition at line 61 of file stm3210e_eval_fsmc_nand.h.

Field Documentation

uint16_t NAND_ADDRESS::Block

Definition at line 64 of file stm3210e_eval_fsmc_nand.h.

Referenced by main(), and NAND_AddressIncrement().

uint16_t NAND_ADDRESS::Page

Definition at line 65 of file stm3210e_eval_fsmc_nand.h.

Referenced by main(), and NAND_AddressIncrement().

uint16_t NAND_ADDRESS::Zone

Definition at line 63 of file stm3210e_eval_fsmc_nand.h.

Referenced by main(), and NAND_AddressIncrement().

The documentation for this struct was generated from the following file:
  • stm3210e_eval_fsmc_nand.h


STM32F10x Standard Peripherals Firmware Library: NAND_IDTypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

NAND_IDTypeDef Struct Reference
STM3210E_EVAL_FSMC_NAND_Exported_Types

#include <stm3210e_eval_fsmc_nand.h>

Data Fields

uint8_t | Device_ID
uint8_t | Fourth_ID
uint8_t | Maker_ID
uint8_t | Third_ID

Detailed Description

Definition at line 53 of file stm3210e_eval_fsmc_nand.h.

Field Documentation

uint8_t NAND_IDTypeDef::Device_ID

Definition at line 56 of file stm3210e_eval_fsmc_nand.h.

Referenced by main(), and NAND_ReadID().

uint8_t NAND_IDTypeDef::Fourth_ID

Definition at line 58 of file stm3210e_eval_fsmc_nand.h.

Referenced by NAND_ReadID().

uint8_t NAND_IDTypeDef::Maker_ID

Definition at line 55 of file stm3210e_eval_fsmc_nand.h.

Referenced by main(), and NAND_ReadID().

uint8_t NAND_IDTypeDef::Third_ID

Definition at line 57 of file stm3210e_eval_fsmc_nand.h.

Referenced by NAND_ReadID().

The documentation for this struct was generated from the following file:
  • stm3210e_eval_fsmc_nand.h


STM32F10x Standard Peripherals Firmware Library: STM3210E_EVAL_FSMC_NAND_Exported_Constants

Defines

STM3210E_EVAL_FSMC_NAND_Exported_Constants

STM3210E_EVAL_FSMC_NAND

Defines

#define | ADDR_1st_CYCLE(ADDR) (uint8_t)((ADDR)& 0xFF)
FSMC NAND memory address computation.
#define | ADDR_2nd_CYCLE(ADDR) (uint8_t)(((ADDR)& 0xFF00) >> 8)
#define | ADDR_3rd_CYCLE(ADDR) (uint8_t)(((ADDR)& 0xFF0000) >> 16)
#define | ADDR_4th_CYCLE(ADDR) (uint8_t)(((ADDR)& 0xFF000000) >> 24)
#define | ADDR_AREA (uint32_t)(1<<17)
#define | CMD_AREA (uint32_t)(1<<16)
NAND Area definition for STM3210E-EVAL Board RevD.
#define | DATA_AREA ((uint32_t)0x00000000)
#define | NAND_BLOCK_SIZE ((uint16_t)0x0020)
#define | NAND_BUSY ((uint32_t)0x00000000)
#define | NAND_CMD_AREA_A ((uint8_t)0x00)
FSMC NAND memory command.
#define | NAND_CMD_AREA_B ((uint8_t)0x01)
#define | NAND_CMD_AREA_C ((uint8_t)0x50)
#define | NAND_CMD_ERASE0 ((uint8_t)0x60)
#define | NAND_CMD_ERASE1 ((uint8_t)0xD0)
#define | NAND_CMD_LOCK_STATUS ((uint8_t)0x7A)
#define | NAND_CMD_READID ((uint8_t)0x90)
#define | NAND_CMD_RESET ((uint8_t)0xFF)
#define | NAND_CMD_STATUS ((uint8_t)0x70)
#define | NAND_CMD_WRITE0 ((uint8_t)0x80)
#define | NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10)
#define | NAND_ERROR ((uint32_t)0x00000001)
#define | NAND_INVALID_ADDRESS ((uint32_t)0x00000200)
#define | NAND_MAX_ZONE ((uint16_t)0x0004)
#define | NAND_PAGE_SIZE ((uint16_t)0x0200)
FSMC NAND memory parameters.
#define | NAND_READY ((uint32_t)0x00000040)
#define | NAND_SPARE_AREA_SIZE ((uint16_t)0x0010)
#define | NAND_TIMEOUT_ERROR ((uint32_t)0x00000400)
#define | NAND_VALID_ADDRESS ((uint32_t)0x00000100)
NAND memory status.
#define | NAND_ZONE_SIZE ((uint16_t)0x0400)

Define Documentation

#define ADDR_1st_CYCLE ( ADDR ) (uint8_t)((ADDR)& 0xFF)

FSMC NAND memory address computation.

Definition at line 122 of file stm3210e_eval_fsmc_nand.h.

Referenced by NAND_EraseBlock(), NAND_ReadID(), NAND_ReadSmallPage(), NAND_ReadSpareArea(), NAND_WriteSmallPage(), and NAND_WriteSpareArea().

#define ADDR_2nd_CYCLE ( ADDR ) (uint8_t)(((ADDR)& 0xFF00) >> 8)

Definition at line 123 of file stm3210e_eval_fsmc_nand.h.

Referenced by NAND_EraseBlock(), NAND_ReadID(), NAND_ReadSmallPage(), NAND_ReadSpareArea(), NAND_WriteSmallPage(), and NAND_WriteSpareArea().

#define ADDR_3rd_CYCLE ( ADDR ) (uint8_t)(((ADDR)& 0xFF0000) >> 16)

Definition at line 124 of file stm3210e_eval_fsmc_nand.h.

Referenced by NAND_EraseBlock(), NAND_ReadID(), NAND_ReadSmallPage(), NAND_ReadSpareArea(), NAND_WriteSmallPage(), and NAND_WriteSpareArea().

#define ADDR_4th_CYCLE ( ADDR ) (uint8_t)(((ADDR)& 0xFF000000) >> 24)

Definition at line 125 of file stm3210e_eval_fsmc_nand.h.

Referenced by NAND_ReadID().

#define ADDR_AREA (uint32_t)(1<<17)

Definition at line 78 of file stm3210e_eval_fsmc_nand.h.

Referenced by NAND_EraseBlock(), NAND_ReadID(), NAND_ReadSmallPage(), NAND_ReadSpareArea(), NAND_WriteSmallPage(), and NAND_WriteSpareArea().

#define CMD_AREA (uint32_t)(1<<16)

NAND Area definition for STM3210E-EVAL Board RevD.

Definition at line 77 of file stm3210e_eval_fsmc_nand.h.

Referenced by NAND_EraseBlock(), NAND_ReadID(), NAND_ReadSmallPage(), NAND_ReadSpareArea(), NAND_ReadStatus(), NAND_Reset(), NAND_WriteSmallPage(), and NAND_WriteSpareArea().

#define DATA_AREA ((uint32_t)0x00000000)

Definition at line 80 of file stm3210e_eval_fsmc_nand.h.

Referenced by NAND_ReadID(), NAND_ReadSmallPage(), NAND_ReadSpareArea(), NAND_WriteSmallPage(), and NAND_WriteSpareArea().

#define NAND_BLOCK_SIZE ((uint16_t)0x0020)

Definition at line 114 of file stm3210e_eval_fsmc_nand.h.

Referenced by NAND_AddressIncrement().

#define NAND_BUSY ((uint32_t)0x00000000)

Definition at line 106 of file stm3210e_eval_fsmc_nand.h.

Referenced by NAND_ReadStatus().

#define NAND_CMD_AREA_A ((uint8_t)0x00)

FSMC NAND memory command.

Definition at line 85 of file stm3210e_eval_fsmc_nand.h.

Referenced by NAND_ReadSmallPage(), and NAND_WriteSmallPage().

#define NAND_CMD_AREA_B ((uint8_t)0x01)

Definition at line 86 of file stm3210e_eval_fsmc_nand.h.

#define NAND_CMD_AREA_C ((uint8_t)0x50)

Definition at line 87 of file stm3210e_eval_fsmc_nand.h.

Referenced by NAND_ReadSpareArea(), and NAND_WriteSpareArea().

#define NAND_CMD_ERASE0 ((uint8_t)0x60)

Definition at line 92 of file stm3210e_eval_fsmc_nand.h.

Referenced by NAND_EraseBlock().

#define NAND_CMD_ERASE1 ((uint8_t)0xD0)

Definition at line 93 of file stm3210e_eval_fsmc_nand.h.

Referenced by NAND_EraseBlock().

#define NAND_CMD_LOCK_STATUS ((uint8_t)0x7A)

Definition at line 97 of file stm3210e_eval_fsmc_nand.h.

#define NAND_CMD_READID ((uint8_t)0x90)

Definition at line 95 of file stm3210e_eval_fsmc_nand.h.

#define NAND_CMD_RESET ((uint8_t)0xFF)

Definition at line 98 of file stm3210e_eval_fsmc_nand.h.

Referenced by NAND_Reset().

#define NAND_CMD_STATUS ((uint8_t)0x70)

Definition at line 96 of file stm3210e_eval_fsmc_nand.h.

Referenced by NAND_ReadStatus().

#define NAND_CMD_WRITE0 ((uint8_t)0x80)

Definition at line 89 of file stm3210e_eval_fsmc_nand.h.

Referenced by NAND_WriteSmallPage(), and NAND_WriteSpareArea().

#define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10)

Definition at line 90 of file stm3210e_eval_fsmc_nand.h.

Referenced by NAND_WriteSmallPage(), and NAND_WriteSpareArea().

#define NAND_ERROR ((uint32_t)0x00000001)

Definition at line 107 of file stm3210e_eval_fsmc_nand.h.

Referenced by NAND_ReadStatus().

#define NAND_INVALID_ADDRESS ((uint32_t)0x00000200)

Definition at line 104 of file stm3210e_eval_fsmc_nand.h.

Referenced by NAND_AddressIncrement().

#define NAND_MAX_ZONE ((uint16_t)0x0004)

Definition at line 117 of file stm3210e_eval_fsmc_nand.h.

Referenced by NAND_AddressIncrement().

#define NAND_PAGE_SIZE ((uint16_t)0x0200)

FSMC NAND memory parameters.

Definition at line 113 of file stm3210e_eval_fsmc_nand.h.

Referenced by NAND_ReadSmallPage(), and NAND_WriteSmallPage().

#define NAND_READY ((uint32_t)0x00000040)

Definition at line 108 of file stm3210e_eval_fsmc_nand.h.

Referenced by NAND_GetStatus(), NAND_ReadSmallPage(), NAND_ReadSpareArea(), NAND_ReadStatus(), NAND_Reset(), NAND_WriteSmallPage(), and NAND_WriteSpareArea().

#define NAND_SPARE_AREA_SIZE ((uint16_t)0x0010)

Definition at line 116 of file stm3210e_eval_fsmc_nand.h.

Referenced by NAND_ReadSpareArea(), and NAND_WriteSpareArea().

#define NAND_TIMEOUT_ERROR ((uint32_t)0x00000400)

Definition at line 105 of file stm3210e_eval_fsmc_nand.h.

Referenced by NAND_GetStatus().

#define NAND_VALID_ADDRESS ((uint32_t)0x00000100)

NAND memory status.

Definition at line 103 of file stm3210e_eval_fsmc_nand.h.

Referenced by NAND_AddressIncrement(), NAND_ReadSmallPage(), NAND_ReadSpareArea(), NAND_WriteSmallPage(), and NAND_WriteSpareArea().

#define NAND_ZONE_SIZE ((uint16_t)0x0400)

Definition at line 115 of file stm3210e_eval_fsmc_nand.h.

Referenced by NAND_AddressIncrement().


STM32F10x Standard Peripherals Firmware Library: STM3210E_EVAL_FSMC_NAND_Exported_Macros

STM3210E_EVAL_FSMC_NAND_Exported_Macros

STM3210E_EVAL_FSMC_NAND


STM32F10x Standard Peripherals Firmware Library: STM3210E_EVAL_FSMC_NAND_Exported_Functions

Functions

STM3210E_EVAL_FSMC_NAND_Exported_Functions

STM3210E_EVAL_FSMC_NAND

Functions

uint32_t | NAND_AddressIncrement (NAND_ADDRESS *Address)
Increment the NAND memory address.
uint32_t | NAND_EraseBlock (NAND_ADDRESS Address)
This routine erase complete block from NAND FLASH.
uint32_t | NAND_GetStatus (void)
Get the NAND operation status.
void | NAND_Init (void)
Configures the FSMC and GPIOs to interface with the NAND memory.
void | NAND_ReadID (NAND_IDTypeDef *NAND_ID)
Reads NAND memory's ID.
uint32_t | NAND_ReadSmallPage (uint8_t *pBuffer, NAND_ADDRESS Address, uint32_t NumPageToRead)
This routine is for sequential read from one or several 512 Bytes Page size.
uint32_t | NAND_ReadSpareArea (uint8_t *pBuffer, NAND_ADDRESS Address, uint32_t NumSpareAreaToRead)
This routine read the spare area information from the specified pages addresses.
uint32_t | NAND_ReadStatus (void)
Reads the NAND memory status using the Read status command.
uint32_t | NAND_Reset (void)
This routine reset the NAND FLASH.
uint32_t | NAND_WriteSmallPage (uint8_t *pBuffer, NAND_ADDRESS Address, uint32_t NumPageToWrite)
This routine is for writing one or several 512 Bytes Page size.
uint32_t | NAND_WriteSpareArea (uint8_t *pBuffer, NAND_ADDRESS Address, uint32_t NumSpareAreaTowrite)
This routine write the spare area information for the specified pages addresses.

Function Documentation

uint32_t NAND_AddressIncrement ( NAND_ADDRESS * Address )

Increment the NAND memory address.

Parameters:
Address,: address to be incremented.
Return values:
The new status of the increment address operation. It can be:

  • NAND_VALID_ADDRESS: When the new address is valid address
  • NAND_INVALID_ADDRESS: When the new address is invalid address

Definition at line 500 of file stm3210e_eval_fsmc_nand.c.

References NAND_ADDRESS::Block, NAND_BLOCK_SIZE, NAND_INVALID_ADDRESS, NAND_MAX_ZONE, NAND_VALID_ADDRESS, NAND_ZONE_SIZE, NAND_ADDRESS::Page, status, and NAND_ADDRESS::Zone.

Referenced by NAND_ReadSmallPage(), NAND_ReadSpareArea(), NAND_WriteSmallPage(), and NAND_WriteSpareArea().

uint32_t NAND_EraseBlock ( NAND_ADDRESS Address )

This routine erase complete block from NAND FLASH.

Parameters:
Address,: Any address into block to be erased
Return values:
New status of the NAND operation. This parameter can be:

  • NAND_TIMEOUT_ERROR: when the previous operation generate a Timeout error
  • NAND_READY: when memory is ready for the next operation

Definition at line 406 of file stm3210e_eval_fsmc_nand.c.

References ADDR_1st_CYCLE, ADDR_2nd_CYCLE, ADDR_3rd_CYCLE, ADDR_AREA, Bank_NAND_ADDR, CMD_AREA, NAND_CMD_ERASE0, NAND_CMD_ERASE1, NAND_GetStatus(), and ROW_ADDRESS.

Referenced by main().

uint32_t NAND_GetStatus ( void )

Get the NAND operation status.

Parameters:
None
Return values:
New status of the NAND operation. This parameter can be:

  • NAND_TIMEOUT_ERROR: when the previous operation generate a Timeout error
  • NAND_READY: when memory is ready for the next operation

< Wait for a NAND operation to complete or a TIMEOUT to occur

Definition at line 439 of file stm3210e_eval_fsmc_nand.c.

References NAND_ReadStatus(), NAND_READY, NAND_TIMEOUT_ERROR, and status.

Referenced by NAND_EraseBlock(), NAND_ReadSmallPage(), NAND_ReadSpareArea(), NAND_WriteSmallPage(), and NAND_WriteSpareArea().

void NAND_Init ( void )

Configures the FSMC and GPIOs to interface with the NAND memory.

This function must be called before any write/read operation on the NAND.

Parameters:
None
Return values:
None

< CLE, ALE, D0->D3, NOE, NWE and NCE2 NAND pin configuration

< D4->D7 NAND pin configuration

< NWAIT NAND pin configuration

< INT2 NAND pin configuration

< FSMC NAND Bank Cmd Test

Definition at line 101 of file stm3210e_eval_fsmc_nand.c.

References ENABLE, FSMC_NANDInitTypeDef::FSMC_AttributeSpaceTimingStruct, FSMC_NANDInitTypeDef::FSMC_Bank, FSMC_Bank2_NAND, FSMC_NANDInitTypeDef::FSMC_CommonSpaceTimingStruct, FSMC_NANDInitTypeDef::FSMC_ECC, FSMC_ECC_Enable, FSMC_NANDInitTypeDef::FSMC_ECCPageSize, FSMC_ECCPageSize_512Bytes, FSMC_NAND_PCCARDTimingInitTypeDef::FSMC_HiZSetupTime, FSMC_NAND_PCCARDTimingInitTypeDef::FSMC_HoldSetupTime, FSMC_NANDInitTypeDef::FSMC_MemoryDataWidth, FSMC_MemoryDataWidth_8b, FSMC_NANDCmd(), FSMC_NANDInit(), FSMC_NAND_PCCARDTimingInitTypeDef::FSMC_SetupTime, FSMC_NANDInitTypeDef::FSMC_TARSetupTime, FSMC_NANDInitTypeDef::FSMC_TCLRSetupTime, FSMC_NANDInitTypeDef::FSMC_Waitfeature, FSMC_Waitfeature_Enable, FSMC_NAND_PCCARDTimingInitTypeDef::FSMC_WaitSetupTime, GPIO_Init(), GPIO_InitStructure, GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_AF_PP, GPIO_Mode_IPU, GPIO_InitTypeDef::GPIO_Pin, GPIO_Pin_0, GPIO_Pin_1, GPIO_Pin_10, GPIO_Pin_11, GPIO_Pin_12, GPIO_Pin_14, GPIO_Pin_15, GPIO_Pin_4, GPIO_Pin_5, GPIO_Pin_6, GPIO_Pin_7, GPIO_Pin_8, GPIO_Pin_9, GPIO_InitTypeDef::GPIO_Speed, GPIO_Speed_50MHz, GPIOD, GPIOE, GPIOG, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE, RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, and RCC_APB2PeriphClockCmd().

Referenced by main().

void NAND_ReadID ( NAND_IDTypeDef * NAND_ID )

Reads NAND memory's ID.

Parameters:
NAND_ID,: pointer to a NAND_IDTypeDef structure which will hold the Manufacturer and Device ID.
Return values:
None

< Send Command to the command area

< Sequence to read ID from NAND flash

Definition at line 165 of file stm3210e_eval_fsmc_nand.c.

References ADDR_1st_CYCLE, ADDR_2nd_CYCLE, ADDR_3rd_CYCLE, ADDR_4th_CYCLE, ADDR_AREA, Bank_NAND_ADDR, CMD_AREA, DATA_AREA, NAND_IDTypeDef::Device_ID, NAND_IDTypeDef::Fourth_ID, NAND_IDTypeDef::Maker_ID, and NAND_IDTypeDef::Third_ID.

Referenced by main().

uint32_t NAND_ReadSmallPage | ( | uint8_t * | pBuffer,
 |  | NAND_ADDRESS | Address,
 |  | uint32_t | NumPageToRead
 | ) |  |

This routine is for sequential read from one or several 512 Bytes Page size.

Parameters:
pBuffer,: pointer on the Buffer to fill
Address,: First page address
NumPageToRead,: Number of page to read
Return values:
New status of the NAND operation. This parameter can be:

  • NAND_TIMEOUT_ERROR: when the previous operation generate a Timeout error
  • NAND_READY: when memory is ready for the next operation And the new status of the increment address operation. It can be:
  • NAND_VALID_ADDRESS: When the new address is valid address
  • NAND_INVALID_ADDRESS: When the new address is invalid address

< Page Read command and page address

< Calculate the size

< Get Data into Buffer

< Calculate page address

Definition at line 252 of file stm3210e_eval_fsmc_nand.c.

References ADDR_1st_CYCLE, ADDR_2nd_CYCLE, ADDR_3rd_CYCLE, ADDR_AREA, Bank_NAND_ADDR, CMD_AREA, DATA_AREA, index, NAND_AddressIncrement(), NAND_CMD_AREA_A, NAND_GetStatus(), NAND_PAGE_SIZE, NAND_READY, NAND_VALID_ADDRESS, ROW_ADDRESS, and status.

Referenced by main().

uint32_t NAND_ReadSpareArea | ( | uint8_t * | pBuffer,
 |  | NAND_ADDRESS | Address,
 |  | uint32_t | NumSpareAreaToRead
 | ) |  |

This routine read the spare area information from the specified pages addresses.

Parameters:
pBuffer,: pointer on the Buffer to fill
Address,: First page address
NumSpareAreaToRead,: Number of Spare Area to read
Return values:
New status of the NAND operation. This parameter can be:

  • NAND_TIMEOUT_ERROR: when the previous operation generate a Timeout error
  • NAND_READY: when memory is ready for the next operation And the new status of the increment address operation. It can be:
  • NAND_VALID_ADDRESS: When the new address is valid address
  • NAND_INVALID_ADDRESS: When the new address is invalid address

< Page Read command and page address

< Data Read

< Get Data into Buffer

< Calculate page address

Definition at line 361 of file stm3210e_eval_fsmc_nand.c.

References ADDR_1st_CYCLE, ADDR_2nd_CYCLE, ADDR_3rd_CYCLE, ADDR_AREA, Bank_NAND_ADDR, CMD_AREA, DATA_AREA, index, NAND_AddressIncrement(), NAND_CMD_AREA_C, NAND_GetStatus(), NAND_READY, NAND_SPARE_AREA_SIZE, NAND_VALID_ADDRESS, ROW_ADDRESS, and status.

uint32_t NAND_ReadStatus ( void )

Reads the NAND memory status using the Read status command.

Parameters:
None
Return values:
The status of the NAND memory. This parameter can be:

  • NAND_BUSY: when memory is busy
  • NAND_READY: when memory is ready for the next operation
  • NAND_ERROR: when the previous operation gererates error

< Read status operation ------------------------------------

Definition at line 469 of file stm3210e_eval_fsmc_nand.c.

References Bank_NAND_ADDR, CMD_AREA, NAND_BUSY, NAND_CMD_STATUS, NAND_ERROR, NAND_READY, and status.

Referenced by NAND_GetStatus().

uint32_t NAND_Reset ( void )

This routine reset the NAND FLASH.

Parameters:
None
Return values:
NAND_READY

Definition at line 424 of file stm3210e_eval_fsmc_nand.c.

References Bank_NAND_ADDR, CMD_AREA, NAND_CMD_RESET, and NAND_READY.

uint32_t NAND_WriteSmallPage | ( | uint8_t * | pBuffer,
 |  | NAND_ADDRESS | Address,
 |  | uint32_t | NumPageToWrite
 | ) |  |

This routine is for writing one or several 512 Bytes Page size.

Parameters:
pBuffer,: pointer on the Buffer containing data to be written
Address,: First page address
NumPageToWrite,: Number of page to write
Return values:
New status of the NAND operation. This parameter can be:

  • NAND_TIMEOUT_ERROR: when the previous operation generate a Timeout error
  • NAND_READY: when memory is ready for the next operation And the new status of the increment address operation. It can be:
  • NAND_VALID_ADDRESS: When the new address is valid address
  • NAND_INVALID_ADDRESS: When the new address is invalid address

< Page write command and address

< Calculate the size

< Write data

< Check status for successful operation

< Calculate Next small page Address

Definition at line 195 of file stm3210e_eval_fsmc_nand.c.

References ADDR_1st_CYCLE, ADDR_2nd_CYCLE, ADDR_3rd_CYCLE, ADDR_AREA, Bank_NAND_ADDR, CMD_AREA, DATA_AREA, index, NAND_AddressIncrement(), NAND_CMD_AREA_A, NAND_CMD_WRITE0, NAND_CMD_WRITE_TRUE1, NAND_GetStatus(), NAND_PAGE_SIZE, NAND_READY, NAND_VALID_ADDRESS, ROW_ADDRESS, and status.

Referenced by main().

uint32_t NAND_WriteSpareArea | ( | uint8_t * | pBuffer,
 |  | NAND_ADDRESS | Address,
 |  | uint32_t | NumSpareAreaTowrite
 | ) |  |

This routine write the spare area information for the specified pages addresses.

Parameters:
pBuffer,: pointer on the Buffer containing data to be written
Address,: First page address
NumSpareAreaTowrite,: Number of Spare Area to write
Return values:
New status of the NAND operation. This parameter can be:

  • NAND_TIMEOUT_ERROR: when the previous operation generate a Timeout error
  • NAND_READY: when memory is ready for the next operation And the new status of the increment address operation. It can be:
  • NAND_VALID_ADDRESS: When the new address is valid address
  • NAND_INVALID_ADDRESS: When the new address is invalid address

< Page write Spare area command and address

< Calculate the size

< Write the data

< Check status for successful operation

< Calculate Next page Address

Definition at line 303 of file stm3210e_eval_fsmc_nand.c.

References ADDR_1st_CYCLE, ADDR_2nd_CYCLE, ADDR_3rd_CYCLE, ADDR_AREA, Bank_NAND_ADDR, CMD_AREA, DATA_AREA, index, NAND_AddressIncrement(), NAND_CMD_AREA_C, NAND_CMD_WRITE0, NAND_CMD_WRITE_TRUE1, NAND_GetStatus(), NAND_READY, NAND_SPARE_AREA_SIZE, NAND_VALID_ADDRESS, ROW_ADDRESS, and status.


STM32F10x Standard Peripherals Firmware Library: STM3210E_EVAL_FSMC_NOR_Private_Types

STM3210E_EVAL_FSMC_NOR_Private_Types

STM3210E_EVAL_FSMC_NOR


STM32F10x Standard Peripherals Firmware Library: STM3210E_EVAL_FSMC_NOR_Private_Defines

Defines

STM3210E_EVAL_FSMC_NOR_Private_Defines

STM3210E_EVAL_FSMC_NOR

Defines

#define | Bank1_NOR2_ADDR ((uint32_t)0x64000000)
FSMC Bank 1 NOR/SRAM2.
#define | BlockErase_Timeout ((uint32_t)0x00A00000)
#define | ChipErase_Timeout ((uint32_t)0x30000000)
#define | Program_Timeout ((uint32_t)0x00001400)

Define Documentation

#define Bank1_NOR2_ADDR ((uint32_t)0x64000000)

FSMC Bank 1 NOR/SRAM2.

Definition at line 57 of file stm3210e_eval_fsmc_nor.c.

Referenced by NOR_EraseBlock(), NOR_GetStatus(), NOR_ReadBuffer(), NOR_ReadHalfWord(), NOR_Reset(), NOR_ReturnToReadMode(), and NOR_WriteHalfWord().

#define BlockErase_Timeout ((uint32_t)0x00A00000)

Definition at line 60 of file stm3210e_eval_fsmc_nor.c.

Referenced by NOR_EraseBlock().

#define ChipErase_Timeout ((uint32_t)0x30000000)

Definition at line 61 of file stm3210e_eval_fsmc_nor.c.

Referenced by NOR_EraseChip().

#define Program_Timeout ((uint32_t)0x00001400)

Definition at line 62 of file stm3210e_eval_fsmc_nor.c.

Referenced by NOR_ProgramBuffer(), and NOR_WriteHalfWord().


STM32F10x Standard Peripherals Firmware Library: STM3210E_EVAL_FSMC_NOR_Private_Macros

Defines

STM3210E_EVAL_FSMC_NOR_Private_Macros

STM3210E_EVAL_FSMC_NOR

Defines

#define | ADDR_SHIFT(A) (Bank1_NOR2_ADDR + (2 * (A)))
#define | NOR_WRITE(Address, Data) (*(__IO uint16_t *)(Address) = (Data))

Define Documentation

#define ADDR_SHIFT ( A ) (Bank1_NOR2_ADDR + (2 * (A)))

Definition at line 71 of file stm3210e_eval_fsmc_nor.c.

Referenced by NOR_EraseBlock(), NOR_EraseChip(), NOR_ProgramBuffer(), NOR_ReadBuffer(), NOR_ReadHalfWord(), NOR_ReadID(), NOR_Reset(), and NOR_WriteHalfWord().

#define NOR_WRITE | ( | Address,
 |  | Data
 | ) | (*(__IO uint16_t *)(Address) = (Data))

Definition at line 72 of file stm3210e_eval_fsmc_nor.c.

Referenced by NOR_EraseBlock(), NOR_EraseChip(), NOR_ProgramBuffer(), NOR_ReadBuffer(), NOR_ReadHalfWord(), NOR_ReadID(), NOR_Reset(), NOR_ReturnToReadMode(), and NOR_WriteHalfWord().


STM32F10x Standard Peripherals Firmware Library: STM3210E_EVAL_FSMC_NOR_Private_Variables

STM3210E_EVAL_FSMC_NOR_Private_Variables

STM3210E_EVAL_FSMC_NOR


STM32F10x Standard Peripherals Firmware Library: STM3210E_EVAL_FSMC_NOR_Private_Functions

Functions

STM3210E_EVAL_FSMC_NOR_Private_Functions

STM3210E_EVAL_FSMC_NOR

Functions

NOR_Status | NOR_EraseBlock (uint32_t BlockAddr)
Erases the specified Nor memory block.
NOR_Status | NOR_EraseChip (void)
Erases the entire chip.
NOR_Status | NOR_GetStatus (uint32_t Timeout)
Returns the NOR operation status.
void | NOR_Init (void)
Configures the FSMC and GPIOs to interface with the NOR memory.
NOR_Status | NOR_ProgramBuffer (uint16_t *pBuffer, uint32_t WriteAddr, uint32_t NumHalfwordToWrite)
Writes a half-word buffer to the FSMC NOR memory.
void | NOR_ReadBuffer (uint16_t *pBuffer, uint32_t ReadAddr, uint32_t NumHalfwordToRead)
Reads a block of data from the FSMC NOR memory.
uint16_t | NOR_ReadHalfWord (uint32_t ReadAddr)
Reads a half-word from the NOR memory.
void | NOR_ReadID (NOR_IDTypeDef *NOR_ID)
Reads NOR memory's Manufacturer and Device Code.
NOR_Status | NOR_Reset (void)
Returns the NOR memory to Read mode and resets the errors in the NOR memory Status Register.
NOR_Status | NOR_ReturnToReadMode (void)
Returns the NOR memory to Read mode.
NOR_Status | NOR_WriteBuffer (uint16_t *pBuffer, uint32_t WriteAddr, uint32_t NumHalfwordToWrite)
Writes a half-word buffer to the FSMC NOR memory.
NOR_Status | NOR_WriteHalfWord (uint32_t WriteAddr, uint16_t Data)
Writes a half-word to the NOR memory.

Function Documentation

NOR_Status NOR_EraseBlock ( uint32_t BlockAddr )

Erases the specified Nor memory block.

Parameters:
BlockAddr,: address of the block to erase.
Return values:
NOR_Status,: The returned value can be: NOR_SUCCESS, NOR_ERROR or NOR_TIMEOUT

Definition at line 211 of file stm3210e_eval_fsmc_nor.c.

References ADDR_SHIFT, Bank1_NOR2_ADDR, BlockErase_Timeout, NOR_GetStatus(), and NOR_WRITE.

Referenced by main().

NOR_Status NOR_EraseChip ( void )

Erases the entire chip.

Parameters:
None
Return values:
NOR_Status,: The returned value can be: NOR_SUCCESS, NOR_ERROR or NOR_TIMEOUT

Definition at line 229 of file stm3210e_eval_fsmc_nor.c.

References ADDR_SHIFT, ChipErase_Timeout, NOR_GetStatus(), and NOR_WRITE.

NOR_Status NOR_GetStatus ( uint32_t Timeout )

Returns the NOR operation status.

Parameters:
Timeout,: NOR progamming Timeout
Return values:
NOR_Status,: The returned value can be: NOR_SUCCESS, NOR_ERROR or NOR_TIMEOUT

< Poll on NOR memory Ready/Busy signal ----------------------------------

< Read DQ6 and DQ5

< If DQ6 did not toggle between the two reads then return NOR_Success

Definition at line 398 of file stm3210e_eval_fsmc_nor.c.

References Bank1_NOR2_ADDR, GPIO_Pin_6, GPIO_ReadInputDataBit(), GPIOD, NOR_ERROR, NOR_ONGOING, NOR_SUCCESS, NOR_TIMEOUT, RESET, and status.

Referenced by NOR_EraseBlock(), NOR_EraseChip(), NOR_ProgramBuffer(), and NOR_WriteHalfWord().

void NOR_Init ( void )

Configures the FSMC and GPIOs to interface with the NOR memory.

This function must be called before any write/read operation on the NOR.

Parameters:
None
Return values:
None

< NOR Data lines configuration

< NOR Address lines configuration

< NOE and NWE configuration

< NE2 configuration

< Configure PD6 for NOR memory Ready/Busy signal

< Enable FSMC Bank1_NOR Bank

Definition at line 105 of file stm3210e_eval_fsmc_nor.c.

References ENABLE, FSMC_NORSRAMTimingInitTypeDef::FSMC_AccessMode, FSMC_AccessMode_B, FSMC_NORSRAMTimingInitTypeDef::FSMC_AddressHoldTime, FSMC_NORSRAMTimingInitTypeDef::FSMC_AddressSetupTime, FSMC_NORSRAMInitTypeDef::FSMC_AsynchronousWait, FSMC_AsynchronousWait_Disable, FSMC_NORSRAMInitTypeDef::FSMC_Bank, FSMC_Bank1_NORSRAM2, FSMC_NORSRAMInitTypeDef::FSMC_BurstAccessMode, FSMC_BurstAccessMode_Disable, FSMC_NORSRAMTimingInitTypeDef::FSMC_BusTurnAroundDuration, FSMC_NORSRAMTimingInitTypeDef::FSMC_CLKDivision, FSMC_NORSRAMInitTypeDef::FSMC_DataAddressMux, FSMC_DataAddressMux_Disable, FSMC_NORSRAMTimingInitTypeDef::FSMC_DataLatency, FSMC_NORSRAMTimingInitTypeDef::FSMC_DataSetupTime, FSMC_NORSRAMInitTypeDef::FSMC_ExtendedMode, FSMC_ExtendedMode_Disable, FSMC_NORSRAMInitTypeDef::FSMC_MemoryDataWidth, FSMC_MemoryDataWidth_16b, FSMC_NORSRAMInitTypeDef::FSMC_MemoryType, FSMC_MemoryType_NOR, FSMC_NORSRAMCmd(), FSMC_NORSRAMInit(), FSMC_NORSRAMInitTypeDef::FSMC_ReadWriteTimingStruct, FSMC_NORSRAMInitTypeDef::FSMC_WaitSignal, FSMC_WaitSignal_Disable, FSMC_NORSRAMInitTypeDef::FSMC_WaitSignalActive, FSMC_WaitSignalActive_BeforeWaitState, FSMC_NORSRAMInitTypeDef::FSMC_WaitSignalPolarity, FSMC_WaitSignalPolarity_Low, FSMC_NORSRAMInitTypeDef::FSMC_WrapMode, FSMC_WrapMode_Disable, FSMC_NORSRAMInitTypeDef::FSMC_WriteBurst, FSMC_WriteBurst_Disable, FSMC_NORSRAMInitTypeDef::FSMC_WriteOperation, FSMC_WriteOperation_Enable, FSMC_NORSRAMInitTypeDef::FSMC_WriteTimingStruct, GPIO_Init(), GPIO_InitStructure, GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_AF_PP, GPIO_Mode_IN_FLOATING, GPIO_InitTypeDef::GPIO_Pin, GPIO_Pin_0, GPIO_Pin_1, GPIO_Pin_10, GPIO_Pin_11, GPIO_Pin_12, GPIO_Pin_13, GPIO_Pin_14, GPIO_Pin_15, GPIO_Pin_2, GPIO_Pin_3, GPIO_Pin_4, GPIO_Pin_5, GPIO_Pin_6, GPIO_Pin_7, GPIO_Pin_8, GPIO_Pin_9, GPIO_InitTypeDef::GPIO_Speed, GPIO_Speed_50MHz, GPIOD, GPIOE, GPIOF, GPIOG, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE, RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, and RCC_APB2PeriphClockCmd().

Referenced by main().

NOR_Status NOR_ProgramBuffer | ( | uint16_t * | pBuffer,
 |  | uint32_t | WriteAddr,
 |  | uint32_t | NumHalfwordToWrite
 | ) |  |

Writes a half-word buffer to the FSMC NOR memory.

This function must be used only with S29GL128P NOR memory.

Parameters:
pBuffer,: pointer to buffer.
WriteAddr,: NOR memory internal address from which the data will be written.
NumHalfwordToWrite,: number of Half words to write. The maximum allowed value is 32 Half words (64 bytes).
Return values:
NOR_Status,: The returned value can be: NOR_SUCCESS, NOR_ERROR or NOR_TIMEOUT

< Initialize variables

< Issue unlock command sequence

< Write Write Buffer Load Command

< Load Data into NOR Buffer

< Store last loaded address & data value (for polling)

Definition at line 294 of file stm3210e_eval_fsmc_nor.c.

References ADDR_SHIFT, NOR_GetStatus(), NOR_WRITE, and Program_Timeout.

void NOR_ReadBuffer | ( | uint16_t * | pBuffer,
 |  | uint32_t | ReadAddr,
 |  | uint32_t | NumHalfwordToRead
 | ) |  |

Reads a block of data from the FSMC NOR memory.

Parameters:
pBuffer,: pointer to the buffer that receives the data read from the NOR memory.
ReadAddr,: NOR memory internal address to read from.
NumHalfwordToRead : number of Half word to read.
Return values:
None

< while there is data to read

< Read a Halfword from the NOR

Definition at line 351 of file stm3210e_eval_fsmc_nor.c.

References ADDR_SHIFT, Bank1_NOR2_ADDR, and NOR_WRITE.

Referenced by main().

uint16_t NOR_ReadHalfWord ( uint32_t ReadAddr )

Reads a half-word from the NOR memory.

Parameters:
ReadAddr,: NOR memory internal address to read from.
Return values:
Half-word read from the NOR memory

Definition at line 334 of file stm3210e_eval_fsmc_nor.c.

References ADDR_SHIFT, Bank1_NOR2_ADDR, and NOR_WRITE.

void NOR_ReadID ( NOR_IDTypeDef * NOR_ID )

Reads NOR memory's Manufacturer and Device Code.

Parameters:
NOR_ID,: pointer to a NOR_IDTypeDef structure which will hold the Manufacturer and Device Code.
Return values:
None

Definition at line 193 of file stm3210e_eval_fsmc_nor.c.

References ADDR_SHIFT, NOR_IDTypeDef::Device_Code1, NOR_IDTypeDef::Device_Code2, NOR_IDTypeDef::Device_Code3, NOR_IDTypeDef::Manufacturer_Code, and NOR_WRITE.

Referenced by main().

NOR_Status NOR_Reset ( void )

Returns the NOR memory to Read mode and resets the errors in the NOR memory Status Register.

Parameters:
None
Return values:
NOR_SUCCESS

Definition at line 383 of file stm3210e_eval_fsmc_nor.c.

References ADDR_SHIFT, Bank1_NOR2_ADDR, NOR_SUCCESS, and NOR_WRITE.

NOR_Status NOR_ReturnToReadMode ( void )

Returns the NOR memory to Read mode.

Parameters:
None
Return values:
NOR_SUCCESS

Definition at line 370 of file stm3210e_eval_fsmc_nor.c.

References Bank1_NOR2_ADDR, NOR_SUCCESS, and NOR_WRITE.

Referenced by main().

NOR_Status NOR_WriteBuffer | ( | uint16_t * | pBuffer,
 |  | uint32_t | WriteAddr,
 |  | uint32_t | NumHalfwordToWrite
 | ) |  |

Writes a half-word buffer to the FSMC NOR memory.

Parameters:
pBuffer,: pointer to buffer.
WriteAddr,: NOR memory internal address from which the data will be written.
NumHalfwordToWrite,: number of Half words to write.
Return values:
NOR_Status,: The returned value can be: NOR_SUCCESS, NOR_ERROR or NOR_TIMEOUT

< Transfer data to the memory

Definition at line 267 of file stm3210e_eval_fsmc_nor.c.

References NOR_ONGOING, NOR_SUCCESS, NOR_WriteHalfWord(), and status.

Referenced by main().

NOR_Status NOR_WriteHalfWord | ( | uint32_t | WriteAddr,
 |  | uint16_t | Data
 | ) |  |

Writes a half-word to the NOR memory.

Parameters:
WriteAddr,: NOR memory internal address to write to.
Data,: Data to write.
Return values:
NOR_Status,: The returned value can be: NOR_SUCCESS, NOR_ERROR or NOR_TIMEOUT

Definition at line 248 of file stm3210e_eval_fsmc_nor.c.

References ADDR_SHIFT, Bank1_NOR2_ADDR, NOR_GetStatus(), NOR_WRITE, and Program_Timeout.

Referenced by NOR_WriteBuffer().


STM32F10x Standard Peripherals Firmware Library: STM3210E_EVAL_FSMC_NOR_Exported_Types

Data Structures | Enumerations

STM3210E_EVAL_FSMC_NOR_Exported_Types

STM3210E_EVAL_FSMC_NOR

Data Structures

struct | NOR_IDTypeDef

Enumerations

enum | NOR_Status { NOR_SUCCESS = 0, NOR_ONGOING, NOR_ERROR, NOR_TIMEOUT }

Enumeration Type Documentation

enum NOR_Status
Enumerator:
NOR_SUCCESS
NOR_ONGOING
NOR_ERROR
NOR_TIMEOUT

Definition at line 62 of file stm3210e_eval_fsmc_nor.h.


STM32F10x Standard Peripherals Firmware Library: NOR_IDTypeDef Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields

NOR_IDTypeDef Struct Reference
STM3210E_EVAL_FSMC_NOR_Exported_Types

#include <stm3210e_eval_fsmc_nor.h>

Data Fields

uint16_t | Device_Code1
uint16_t | Device_Code2
uint16_t | Device_Code3
uint16_t | Manufacturer_Code

Detailed Description

Definition at line 53 of file stm3210e_eval_fsmc_nor.h.

Field Documentation

uint16_t NOR_IDTypeDef::Device_Code1

Definition at line 56 of file stm3210e_eval_fsmc_nor.h.

Referenced by NOR_ReadID().

uint16_t NOR_IDTypeDef::Device_Code2

Definition at line 57 of file stm3210e_eval_fsmc_nor.h.

Referenced by NOR_ReadID().

uint16_t NOR_IDTypeDef::Device_Code3

Definition at line 58 of file stm3210e_eval_fsmc_nor.h.

Referenced by NOR_ReadID().

uint16_t NOR_IDTypeDef::Manufacturer_Code

Definition at line 55 of file stm3210e_eval_fsmc_nor.h.

Referenced by NOR_ReadID().

The documentation for this struct was generated from the following file:
  • stm3210e_eval_fsmc_nor.h


STM32F10x Standard Peripherals Firmware Library: STM3210E_EVAL_FSMC_NOR_Exported_Constants

STM3210E_EVAL_FSMC_NOR_Exported_Constants

STM3210E_EVAL_FSMC_NOR


STM32F10x Standard Peripherals Firmware Library: STM3210E_EVAL_FSMC_NOR_Exported_Macros

STM3210E_EVAL_FSMC_NOR_Exported_Macros

STM3210E_EVAL_FSMC_NOR


STM32F10x Standard Peripherals Firmware Library: STM3210E_EVAL_FSMC_NOR_Exported_Functions

Functions

STM3210E_EVAL_FSMC_NOR_Exported_Functions

STM3210E_EVAL_FSMC_NOR

Functions

NOR_Status | NOR_EraseBlock (uint32_t BlockAddr)
Erases the specified Nor memory block.
NOR_Status | NOR_EraseChip (void)
Erases the entire chip.
NOR_Status | NOR_GetStatus (uint32_t Timeout)
Returns the NOR operation status.
void | NOR_Init (void)
Configures the FSMC and GPIOs to interface with the NOR memory.
NOR_Status | NOR_ProgramBuffer (uint16_t *pBuffer, uint32_t WriteAddr, uint32_t NumHalfwordToWrite)
Writes a half-word buffer to the FSMC NOR memory.
void | NOR_ReadBuffer (uint16_t *pBuffer, uint32_t ReadAddr, uint32_t NumHalfwordToRead)
Reads a block of data from the FSMC NOR memory.
uint16_t | NOR_ReadHalfWord (uint32_t ReadAddr)
Reads a half-word from the NOR memory.
void | NOR_ReadID (NOR_IDTypeDef *NOR_ID)
Reads NOR memory's Manufacturer and Device Code.
NOR_Status | NOR_Reset (void)
Returns the NOR memory to Read mode and resets the errors in the NOR memory Status Register.
NOR_Status | NOR_ReturnToReadMode (void)
Returns the NOR memory to Read mode.
NOR_Status | NOR_WriteBuffer (uint16_t *pBuffer, uint32_t WriteAddr, uint32_t NumHalfwordToWrite)
Writes a half-word buffer to the FSMC NOR memory.
NOR_Status | NOR_WriteHalfWord (uint32_t WriteAddr, uint16_t Data)
Writes a half-word to the NOR memory.

Function Documentation

NOR_Status NOR_EraseBlock ( uint32_t BlockAddr )

Erases the specified Nor memory block.

Parameters:
BlockAddr,: address of the block to erase.
Return values:
NOR_Status,: The returned value can be: NOR_SUCCESS, NOR_ERROR or NOR_TIMEOUT

Definition at line 211 of file stm3210e_eval_fsmc_nor.c.

References ADDR_SHIFT, Bank1_NOR2_ADDR, BlockErase_Timeout, NOR_GetStatus(), and NOR_WRITE.

Referenced by main().

NOR_Status NOR_EraseChip ( void )

Erases the entire chip.

Parameters:
None
Return values:
NOR_Status,: The returned value can be: NOR_SUCCESS, NOR_ERROR or NOR_TIMEOUT

Definition at line 229 of file stm3210e_eval_fsmc_nor.c.

References ADDR_SHIFT, ChipErase_Timeout, NOR_GetStatus(), and NOR_WRITE.

NOR_Status NOR_GetStatus ( uint32_t Timeout )

Returns the NOR operation status.

Parameters:
Timeout,: NOR progamming Timeout
Return values:
NOR_Status,: The returned value can be: NOR_SUCCESS, NOR_ERROR or NOR_TIMEOUT

< Poll on NOR memory Ready/Busy signal ----------------------------------

< Read DQ6 and DQ5

< If DQ6 did not toggle between the two reads then return NOR_Success

Definition at line 398 of file stm3210e_eval_fsmc_nor.c.

References Bank1_NOR2_ADDR, GPIO_Pin_6, GPIO_ReadInputDataBit(), GPIOD, NOR_ERROR, NOR_ONGOING, NOR_SUCCESS, NOR_TIMEOUT, RESET, and status.

Referenced by NOR_EraseBlock(), NOR_EraseChip(), NOR_ProgramBuffer(), and NOR_WriteHalfWord().

void NOR_Init ( void )

Configures the FSMC and GPIOs to interface with the NOR memory.

This function must be called before any write/read operation on the NOR.

Parameters:
None
Return values:
None

< NOR Data lines configuration

< NOR Address lines configuration

< NOE and NWE configuration

< NE2 configuration

< Configure PD6 for NOR memory Ready/Busy signal

< Enable FSMC Bank1_NOR Bank

Definition at line 105 of file stm3210e_eval_fsmc_nor.c.

References ENABLE, FSMC_NORSRAMTimingInitTypeDef::FSMC_AccessMode, FSMC_AccessMode_B, FSMC_NORSRAMTimingInitTypeDef::FSMC_AddressHoldTime, FSMC_NORSRAMTimingInitTypeDef::FSMC_AddressSetupTime, FSMC_NORSRAMInitTypeDef::FSMC_AsynchronousWait, FSMC_AsynchronousWait_Disable, FSMC_NORSRAMInitTypeDef::FSMC_Bank, FSMC_Bank1_NORSRAM2, FSMC_NORSRAMInitTypeDef::FSMC_BurstAccessMode, FSMC_BurstAccessMode_Disable, FSMC_NORSRAMTimingInitTypeDef::FSMC_BusTurnAroundDuration, FSMC_NORSRAMTimingInitTypeDef::FSMC_CLKDivision, FSMC_NORSRAMInitTypeDef::FSMC_DataAddressMux, FSMC_DataAddressMux_Disable, FSMC_NORSRAMTimingInitTypeDef::FSMC_DataLatency, FSMC_NORSRAMTimingInitTypeDef::FSMC_DataSetupTime, FSMC_NORSRAMInitTypeDef::FSMC_ExtendedMode, FSMC_ExtendedMode_Disable, FSMC_NORSRAMInitTypeDef::FSMC_MemoryDataWidth, FSMC_MemoryDataWidth_16b, FSMC_NORSRAMInitTypeDef::FSMC_MemoryType, FSMC_MemoryType_NOR, FSMC_NORSRAMCmd(), FSMC_NORSRAMInit(), FSMC_NORSRAMInitTypeDef::FSMC_ReadWriteTimingStruct, FSMC_NORSRAMInitTypeDef::FSMC_WaitSignal, FSMC_WaitSignal_Disable, FSMC_NORSRAMInitTypeDef::FSMC_WaitSignalActive, FSMC_WaitSignalActive_BeforeWaitState, FSMC_NORSRAMInitTypeDef::FSMC_WaitSignalPolarity, FSMC_WaitSignalPolarity_Low, FSMC_NORSRAMInitTypeDef::FSMC_WrapMode, FSMC_WrapMode_Disable, FSMC_NORSRAMInitTypeDef::FSMC_WriteBurst, FSMC_WriteBurst_Disable, FSMC_NORSRAMInitTypeDef::FSMC_WriteOperation, FSMC_WriteOperation_Enable, FSMC_NORSRAMInitTypeDef::FSMC_WriteTimingStruct, GPIO_Init(), GPIO_InitStructure, GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_AF_PP, GPIO_Mode_IN_FLOATING, GPIO_InitTypeDef::GPIO_Pin, GPIO_Pin_0, GPIO_Pin_1, GPIO_Pin_10, GPIO_Pin_11, GPIO_Pin_12, GPIO_Pin_13, GPIO_Pin_14, GPIO_Pin_15, GPIO_Pin_2, GPIO_Pin_3, GPIO_Pin_4, GPIO_Pin_5, GPIO_Pin_6, GPIO_Pin_7, GPIO_Pin_8, GPIO_Pin_9, GPIO_InitTypeDef::GPIO_Speed, GPIO_Speed_50MHz, GPIOD, GPIOE, GPIOF, GPIOG, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE, RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, and RCC_APB2PeriphClockCmd().

Referenced by main().

NOR_Status NOR_ProgramBuffer | ( | uint16_t * | pBuffer,
 |  | uint32_t | WriteAddr,
 |  | uint32_t | NumHalfwordToWrite
 | ) |  |

Writes a half-word buffer to the FSMC NOR memory.

This function must be used only with S29GL128P NOR memory.

Parameters:
pBuffer,: pointer to buffer.
WriteAddr,: NOR memory internal address from which the data will be written.
NumHalfwordToWrite,: number of Half words to write. The maximum allowed value is 32 Half words (64 bytes).
Return values:
NOR_Status,: The returned value can be: NOR_SUCCESS, NOR_ERROR or NOR_TIMEOUT

< Initialize variables

< Issue unlock command sequence

< Write Write Buffer Load Command

< Load Data into NOR Buffer

< Store last loaded address & data value (for polling)

Definition at line 294 of file stm3210e_eval_fsmc_nor.c.

References ADDR_SHIFT, NOR_GetStatus(), NOR_WRITE, and Program_Timeout.

void NOR_ReadBuffer | ( | uint16_t * | pBuffer,
 |  | uint32_t | ReadAddr,
 |  | uint32_t | NumHalfwordToRead
 | ) |  |

Reads a block of data from the FSMC NOR memory.

Parameters:
pBuffer,: pointer to the buffer that receives the data read from the NOR memory.
ReadAddr,: NOR memory internal address to read from.
NumHalfwordToRead : number of Half word to read.
Return values:
None

< while there is data to read

< Read a Halfword from the NOR

Definition at line 351 of file stm3210e_eval_fsmc_nor.c.

References ADDR_SHIFT, Bank1_NOR2_ADDR, and NOR_WRITE.

Referenced by main().

uint16_t NOR_ReadHalfWord ( uint32_t ReadAddr )

Reads a half-word from the NOR memory.

Parameters:
ReadAddr,: NOR memory internal address to read from.
Return values:
Half-word read from the NOR memory

Definition at line 334 of file stm3210e_eval_fsmc_nor.c.

References ADDR_SHIFT, Bank1_NOR2_ADDR, and NOR_WRITE.

void NOR_ReadID ( NOR_IDTypeDef * NOR_ID )

Reads NOR memory's Manufacturer and Device Code.

Parameters:
NOR_ID,: pointer to a NOR_IDTypeDef structure which will hold the Manufacturer and Device Code.
Return values:
None

Definition at line 193 of file stm3210e_eval_fsmc_nor.c.

References ADDR_SHIFT, NOR_IDTypeDef::Device_Code1, NOR_IDTypeDef::Device_Code2, NOR_IDTypeDef::Device_Code3, NOR_IDTypeDef::Manufacturer_Code, and NOR_WRITE.

Referenced by main().

NOR_Status NOR_Reset ( void )

Returns the NOR memory to Read mode and resets the errors in the NOR memory Status Register.

Parameters:
None
Return values:
NOR_SUCCESS

Definition at line 383 of file stm3210e_eval_fsmc_nor.c.

References ADDR_SHIFT, Bank1_NOR2_ADDR, NOR_SUCCESS, and NOR_WRITE.

NOR_Status NOR_ReturnToReadMode ( void )

Returns the NOR memory to Read mode.

Parameters:
None
Return values:
NOR_SUCCESS

Definition at line 370 of file stm3210e_eval_fsmc_nor.c.

References Bank1_NOR2_ADDR, NOR_SUCCESS, and NOR_WRITE.

Referenced by main().

NOR_Status NOR_WriteBuffer | ( | uint16_t * | pBuffer,
 |  | uint32_t | WriteAddr,
 |  | uint32_t | NumHalfwordToWrite
 | ) |  |

Writes a half-word buffer to the FSMC NOR memory.

Parameters:
pBuffer,: pointer to buffer.
WriteAddr,: NOR memory internal address from which the data will be written.
NumHalfwordToWrite,: number of Half words to write.
Return values:
NOR_Status,: The returned value can be: NOR_SUCCESS, NOR_ERROR or NOR_TIMEOUT

< Transfer data to the memory

Definition at line 267 of file stm3210e_eval_fsmc_nor.c.

References NOR_ONGOING, NOR_SUCCESS, NOR_WriteHalfWord(), and status.

Referenced by main().

NOR_Status NOR_WriteHalfWord | ( | uint32_t | WriteAddr,
 |  | uint16_t | Data
 | ) |  |

Writes a half-word to the NOR memory.

Parameters:
WriteAddr,: NOR memory internal address to write to.
Data,: Data to write.
Return values:
NOR_Status,: The returned value can be: NOR_SUCCESS, NOR_ERROR or NOR_TIMEOUT

Definition at line 248 of file stm3210e_eval_fsmc_nor.c.

References ADDR_SHIFT, Bank1_NOR2_ADDR, NOR_GetStatus(), NOR_WRITE, and Program_Timeout.

Referenced by NOR_WriteBuffer().


STM32F10x Standard Peripherals Firmware Library: STM3210E_EVAL_FSMC_SRAM_Private_Types

STM3210E_EVAL_FSMC_SRAM_Private_Types

STM3210E_EVAL_FSMC_SRAM


STM32F10x Standard Peripherals Firmware Library: STM3210E_EVAL_FSMC_SRAM_Private_Defines

Defines

STM3210E_EVAL_FSMC_SRAM_Private_Defines

STM3210E_EVAL_FSMC_SRAM

Defines

#define Bank1_SRAM3_ADDR ((uint32_t)0x68000000)
FSMC Bank 1 NOR/SRAM3.

Define Documentation

#define Bank1_SRAM3_ADDR ((uint32_t)0x68000000)

FSMC Bank 1 NOR/SRAM3.

Definition at line 58 of file stm3210e_eval_fsmc_sram.c.

Referenced by SRAM_ReadBuffer(), and SRAM_WriteBuffer().


STM32F10x Standard Peripherals Firmware Library: STM3210E_EVAL_FSMC_SRAM_Private_Macros

STM3210E_EVAL_FSMC_SRAM_Private_Macros

STM3210E_EVAL_FSMC_SRAM


STM32F10x Standard Peripherals Firmware Library: STM3210E_EVAL_FSMC_SRAM_Private_Variables

STM3210E_EVAL_FSMC_SRAM_Private_Variables

STM3210E_EVAL_FSMC_SRAM


STM32F10x Standard Peripherals Firmware Library: STM3210E_EVAL_FSMC_SRAM_Private_Function_Prototypes

STM3210E_EVAL_FSMC_SRAM_Private_Function_Prototypes

STM3210E_EVAL_FSMC_SRAM


STM32F10x Standard Peripherals Firmware Library: STM3210E_EVAL_FSMC_SRAM_Private_Functions

Functions

STM3210E_EVAL_FSMC_SRAM_Private_Functions

STM3210E_EVAL_FSMC_SRAM

Functions

void | SRAM_Init (void)
Configures the FSMC and GPIOs to interface with the SRAM memory.
void | SRAM_ReadBuffer (uint16_t *pBuffer, uint32_t ReadAddr, uint32_t NumHalfwordToRead)
Reads a block of data from the FSMC SRAM memory.
void | SRAM_WriteBuffer (uint16_t *pBuffer, uint32_t WriteAddr, uint32_t NumHalfwordToWrite)
Writes a Half-word buffer to the FSMC SRAM memory.

Function Documentation

void SRAM_Init ( void )

Configures the FSMC and GPIOs to interface with the SRAM memory.

This function must be called before any write/read operation on the SRAM.

Parameters:
None
Return values:
None

< SRAM Data lines configuration

< SRAM Address lines configuration

< NOE and NWE configuration

< NE3 configuration

< NBL0, NBL1 configuration

< Enable FSMC Bank1_SRAM Bank

Definition at line 99 of file stm3210e_eval_fsmc_sram.c.

References ENABLE, FSMC_NORSRAMTimingInitTypeDef::FSMC_AccessMode, FSMC_AccessMode_A, FSMC_NORSRAMTimingInitTypeDef::FSMC_AddressHoldTime, FSMC_NORSRAMTimingInitTypeDef::FSMC_AddressSetupTime, FSMC_NORSRAMInitTypeDef::FSMC_AsynchronousWait, FSMC_AsynchronousWait_Disable, FSMC_NORSRAMInitTypeDef::FSMC_Bank, FSMC_Bank1_NORSRAM3, FSMC_NORSRAMInitTypeDef::FSMC_BurstAccessMode, FSMC_BurstAccessMode_Disable, FSMC_NORSRAMTimingInitTypeDef::FSMC_BusTurnAroundDuration, FSMC_NORSRAMTimingInitTypeDef::FSMC_CLKDivision, FSMC_NORSRAMInitTypeDef::FSMC_DataAddressMux, FSMC_DataAddressMux_Disable, FSMC_NORSRAMTimingInitTypeDef::FSMC_DataLatency, FSMC_NORSRAMTimingInitTypeDef::FSMC_DataSetupTime, FSMC_NORSRAMInitTypeDef::FSMC_ExtendedMode, FSMC_ExtendedMode_Disable, FSMC_NORSRAMInitTypeDef::FSMC_MemoryDataWidth, FSMC_MemoryDataWidth_16b, FSMC_NORSRAMInitTypeDef::FSMC_MemoryType, FSMC_MemoryType_SRAM, FSMC_NORSRAMCmd(), FSMC_NORSRAMInit(), FSMC_NORSRAMInitTypeDef::FSMC_ReadWriteTimingStruct, FSMC_NORSRAMInitTypeDef::FSMC_WaitSignal, FSMC_WaitSignal_Disable, FSMC_NORSRAMInitTypeDef::FSMC_WaitSignalActive, FSMC_WaitSignalActive_BeforeWaitState, FSMC_NORSRAMInitTypeDef::FSMC_WaitSignalPolarity, FSMC_WaitSignalPolarity_Low, FSMC_NORSRAMInitTypeDef::FSMC_WrapMode, FSMC_WrapMode_Disable, FSMC_NORSRAMInitTypeDef::FSMC_WriteBurst, FSMC_WriteBurst_Disable, FSMC_NORSRAMInitTypeDef::FSMC_WriteOperation, FSMC_WriteOperation_Enable, FSMC_NORSRAMInitTypeDef::FSMC_WriteTimingStruct, GPIO_Init(), GPIO_InitStructure, GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_AF_PP, GPIO_InitTypeDef::GPIO_Pin, GPIO_Pin_0, GPIO_Pin_1, GPIO_Pin_10, GPIO_Pin_11, GPIO_Pin_12, GPIO_Pin_13, GPIO_Pin_14, GPIO_Pin_15, GPIO_Pin_2, GPIO_Pin_3, GPIO_Pin_4, GPIO_Pin_5, GPIO_Pin_7, GPIO_Pin_8, GPIO_Pin_9, GPIO_InitTypeDef::GPIO_Speed, GPIO_Speed_50MHz, GPIOD, GPIOE, GPIOF, GPIOG, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE, RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, and RCC_APB2PeriphClockCmd().

void SRAM_ReadBuffer | ( | uint16_t * | pBuffer,
 |  | uint32_t | ReadAddr,
 |  | uint32_t | NumHalfwordToRead
 | ) |  |

Reads a block of data from the FSMC SRAM memory.

Parameters:
pBuffer | : pointer to the buffer that receives the data read from the SRAM memory.
ReadAddr | : SRAM memory internal address to read from.
NumHalfwordToRead | : number of half-words to read.
Return values:
None

< while there is data to read

< Read a half-word from the memory

< Increment the address

Definition at line 205 of file stm3210e_eval_fsmc_sram.c.

References Bank1_SRAM3_ADDR.

void SRAM_WriteBuffer | ( | uint16_t * | pBuffer,
 |  | uint32_t | WriteAddr,
 |  | uint32_t | NumHalfwordToWrite
 | ) |  |

Writes a Half-word buffer to the FSMC SRAM memory.

Parameters:
pBuffer | : pointer to buffer.
WriteAddr | : SRAM memory internal address from which the data will be written.
NumHalfwordToWrite | : number of half-words to write.
Return values:
None

< while there is data to write

< Transfer data to the memory

< Increment the address

Definition at line 185 of file stm3210e_eval_fsmc_sram.c.

References Bank1_SRAM3_ADDR.


STM32F10x Standard Peripherals Firmware Library: STM3210E_EVAL_FSMC_SRAM_Exported_Types

STM3210E_EVAL_FSMC_SRAM_Exported_Types

STM3210E_EVAL_FSMC_SRAM


STM32F10x Standard Peripherals Firmware Library: STM3210E_EVAL_FSMC_SRAM_Exported_Constants

STM3210E_EVAL_FSMC_SRAM_Exported_Constants

STM3210E_EVAL_FSMC_SRAM


STM32F10x Standard Peripherals Firmware Library: STM3210E_EVAL_FSMC_SRAM_Exported_Macros

STM3210E_EVAL_FSMC_SRAM_Exported_Macros

STM3210E_EVAL_FSMC_SRAM


STM32F10x Standard Peripherals Firmware Library: STM3210E_EVAL_FSMC_SRAM_Exported_Functions

Functions

STM3210E_EVAL_FSMC_SRAM_Exported_Functions

STM3210E_EVAL_FSMC_SRAM

Functions

void | SRAM_Init (void)
Configures the FSMC and GPIOs to interface with the SRAM memory.
void | SRAM_ReadBuffer (uint16_t *pBuffer, uint32_t ReadAddr, uint32_t NumHalfwordToRead)
Reads a block of data from the FSMC SRAM memory.
void | SRAM_WriteBuffer (uint16_t *pBuffer, uint32_t WriteAddr, uint32_t NumHalfwordToWrite)
Writes a Half-word buffer to the FSMC SRAM memory.

Function Documentation

void SRAM_Init ( void )

Configures the FSMC and GPIOs to interface with the SRAM memory.

This function must be called before any write/read operation on the SRAM.

Parameters:
None
Return values:
None

< SRAM Data lines configuration

< SRAM Address lines configuration

< NOE and NWE configuration

< NE3 configuration

< NBL0, NBL1 configuration

< Enable FSMC Bank1_SRAM Bank

< SRAM Data lines configuration

< SRAM Address lines configuration

< NOE and NWE configuration

< NE3 configuration

< NBL0, NBL1 configuration

< Enable FSMC Bank1_SRAM Bank

Definition at line 99 of file stm32100e_eval_fsmc_sram.c.

References ENABLE, FSMC_NORSRAMTimingInitTypeDef::FSMC_AccessMode, FSMC_AccessMode_A, FSMC_NORSRAMTimingInitTypeDef::FSMC_AddressHoldTime, FSMC_NORSRAMTimingInitTypeDef::FSMC_AddressSetupTime, FSMC_NORSRAMInitTypeDef::FSMC_AsynchronousWait, FSMC_AsynchronousWait_Disable, FSMC_NORSRAMInitTypeDef::FSMC_Bank, FSMC_Bank1_NORSRAM3, FSMC_NORSRAMInitTypeDef::FSMC_BurstAccessMode, FSMC_BurstAccessMode_Disable, FSMC_NORSRAMTimingInitTypeDef::FSMC_BusTurnAroundDuration, FSMC_NORSRAMTimingInitTypeDef::FSMC_CLKDivision, FSMC_NORSRAMInitTypeDef::FSMC_DataAddressMux, FSMC_DataAddressMux_Disable, FSMC_NORSRAMTimingInitTypeDef::FSMC_DataLatency, FSMC_NORSRAMTimingInitTypeDef::FSMC_DataSetupTime, FSMC_NORSRAMInitTypeDef::FSMC_ExtendedMode, FSMC_ExtendedMode_Disable, FSMC_NORSRAMInitTypeDef::FSMC_MemoryDataWidth, FSMC_MemoryDataWidth_16b, FSMC_NORSRAMInitTypeDef::FSMC_MemoryType, FSMC_MemoryType_SRAM, FSMC_NORSRAMCmd(), FSMC_NORSRAMInit(), FSMC_NORSRAMInitTypeDef::FSMC_ReadWriteTimingStruct, FSMC_NORSRAMInitTypeDef::FSMC_WaitSignal, FSMC_WaitSignal_Disable, FSMC_NORSRAMInitTypeDef::FSMC_WaitSignalActive, FSMC_WaitSignalActive_BeforeWaitState, FSMC_NORSRAMInitTypeDef::FSMC_WaitSignalPolarity, FSMC_WaitSignalPolarity_Low, FSMC_NORSRAMInitTypeDef::FSMC_WrapMode, FSMC_WrapMode_Disable, FSMC_NORSRAMInitTypeDef::FSMC_WriteBurst, FSMC_WriteBurst_Disable, FSMC_NORSRAMInitTypeDef::FSMC_WriteOperation, FSMC_WriteOperation_Enable, FSMC_NORSRAMInitTypeDef::FSMC_WriteTimingStruct, GPIO_Init(), GPIO_InitStructure, GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_AF_PP, GPIO_InitTypeDef::GPIO_Pin, GPIO_Pin_0, GPIO_Pin_1, GPIO_Pin_10, GPIO_Pin_11, GPIO_Pin_12, GPIO_Pin_13, GPIO_Pin_14, GPIO_Pin_15, GPIO_Pin_2, GPIO_Pin_3, GPIO_Pin_4, GPIO_Pin_5, GPIO_Pin_7, GPIO_Pin_8, GPIO_Pin_9, GPIO_InitTypeDef::GPIO_Speed, GPIO_Speed_50MHz, GPIOD, GPIOE, GPIOF, GPIOG, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE, RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, and RCC_APB2PeriphClockCmd().

Referenced by main().

void SRAM_ReadBuffer | ( | uint16_t * | pBuffer,
 |  | uint32_t | ReadAddr,
 |  | uint32_t | NumHalfwordToRead
 | ) |  |

Reads a block of data from the FSMC SRAM memory.

Parameters:
pBuffer | : pointer to the buffer that receives the data read from the SRAM memory.
ReadAddr | : SRAM memory internal address to read from.
NumHalfwordToRead | : number of half-words to read.
Return values:
None

< while there is data to read

< Read a half-word from the memory

< Increment the address

< while there is data to read

< Read a half-word from the memory

< Increment the address

Definition at line 205 of file stm32100e_eval_fsmc_sram.c.

References Bank1_SRAM3_ADDR.

Referenced by main().

void SRAM_WriteBuffer | ( | uint16_t * | pBuffer,
 |  | uint32_t | WriteAddr,
 |  | uint32_t | NumHalfwordToWrite
 | ) |  |

Writes a Half-word buffer to the FSMC SRAM memory.

Parameters:
pBuffer | : pointer to buffer.
WriteAddr | : SRAM memory internal address from which the data will be written.
NumHalfwordToWrite | : number of half-words to write.
Return values:
None

< while there is data to write

< Transfer data to the memory

< Increment the address

< while there is data to write

< Transfer data to the memory

< Increment the address

Definition at line 185 of file stm32100e_eval_fsmc_sram.c.

References Bank1_SRAM3_ADDR.

Referenced by main().


STM32F10x Standard Peripherals Firmware Library: STM32L152_EVAL_LOW_LEVEL_Private_TypesDefinitions

STM32L152_EVAL_LOW_LEVEL_Private_TypesDefinitions

STM32L152_EVAL_LOW_LEVEL


STM32F10x Standard Peripherals Firmware Library: STM32L152_EVAL_LOW_LEVEL_Private_Defines

STM32L152_EVAL_LOW_LEVEL_Private_Defines

STM32L152_EVAL_LOW_LEVEL


STM32F10x Standard Peripherals Firmware Library: STM32L152_EVAL_LOW_LEVEL_Private_Macros

STM32L152_EVAL_LOW_LEVEL_Private_Macros

STM32L152_EVAL_LOW_LEVEL


STM32F10x Standard Peripherals Firmware Library: STM32L152_EVAL_LOW_LEVEL_Private_Variables

Variables

STM32L152_EVAL_LOW_LEVEL_Private_Variables

STM32L152_EVAL_LOW_LEVEL

Variables

const uint32_t | BUTTON_CLK [BUTTONn]
const uint16_t | BUTTON_EXTI_LINE [BUTTONn]
const uint16_t | BUTTON_IRQn [BUTTONn]
const uint16_t | BUTTON_PIN [BUTTONn]
const uint16_t | BUTTON_PIN_SOURCE [BUTTONn]
GPIO_TypeDef * | BUTTON_PORT [BUTTONn]
const uint16_t | BUTTON_PORT_SOURCE [BUTTONn]
const uint16_t | COM_RX_AF [COMn] = {EVAL_COM1_RX_AF, EVAL_COM2_RX_AF}
const uint16_t | COM_RX_PIN [COMn] = {EVAL_COM1_RX_PIN, EVAL_COM2_RX_PIN}
const uint16_t | COM_RX_PIN_SOURCE [COMn] = {EVAL_COM1_RX_SOURCE, EVAL_COM2_RX_SOURCE}
GPIO_TypeDef * | COM_RX_PORT [COMn] = {EVAL_COM1_RX_GPIO_PORT, EVAL_COM2_RX_GPIO_PORT}
const uint32_t | COM_RX_PORT_CLK [COMn] = {EVAL_COM1_RX_GPIO_CLK, EVAL_COM2_RX_GPIO_CLK}
const uint16_t | COM_TX_AF [COMn] = {EVAL_COM1_TX_AF, EVAL_COM2_TX_AF}
const uint16_t | COM_TX_PIN [COMn] = {EVAL_COM1_TX_PIN, EVAL_COM2_TX_PIN}
const uint16_t | COM_TX_PIN_SOURCE [COMn] = {EVAL_COM1_TX_SOURCE, EVAL_COM2_TX_SOURCE}
GPIO_TypeDef * | COM_TX_PORT [COMn] = {EVAL_COM1_TX_GPIO_PORT, EVAL_COM2_TX_GPIO_PORT}
const uint32_t | COM_TX_PORT_CLK [COMn] = {EVAL_COM1_TX_GPIO_CLK, EVAL_COM2_TX_GPIO_CLK}
USART_TypeDef * | COM_USART [COMn] = {EVAL_COM1, EVAL_COM2}
const uint32_t | COM_USART_CLK [COMn] = {EVAL_COM1_CLK, EVAL_COM2_CLK}
const uint32_t | GPIO_CLK [LEDn]
const uint16_t | GPIO_PIN [LEDn]
GPIO_TypeDef * | GPIO_PORT [LEDn]
DMA_InitTypeDef sEEDMA_InitStructure

Variable Documentation

const uint32_t BUTTON_CLK[BUTTONn]
Initial value:
 {KEY_BUTTON_GPIO_CLK, RIGHT_BUTTON_GPIO_CLK,
                                      LEFT_BUTTON_GPIO_CLK, UP_BUTTON_GPIO_CLK,
                                      DOWN_BUTTON_GPIO_CLK, SEL_BUTTON_GPIO_CLK}

Definition at line 92 of file stm32l152_eval.c.

const uint16_t BUTTON_EXTI_LINE[BUTTONn]
Initial value:
 {KEY_BUTTON_EXTI_LINE,
                                            RIGHT_BUTTON_EXTI_LINE,
                                            LEFT_BUTTON_EXTI_LINE,
                                            UP_BUTTON_EXTI_LINE,
                                            DOWN_BUTTON_EXTI_LINE,
                                            SEL_BUTTON_EXTI_LINE}

Definition at line 96 of file stm32l152_eval.c.

const uint16_t BUTTON_IRQn[BUTTONn]
Initial value:
 {KEY_BUTTON_EXTI_IRQn, RIGHT_BUTTON_EXTI_IRQn,
                                       LEFT_BUTTON_EXTI_IRQn, UP_BUTTON_EXTI_IRQn,
                                       DOWN_BUTTON_EXTI_IRQn, SEL_BUTTON_EXTI_IRQn}

Definition at line 117 of file stm32l152_eval.c.

const uint16_t BUTTON_PIN[BUTTONn]
Initial value:
 {KEY_BUTTON_PIN, RIGHT_BUTTON_PIN,
                                      LEFT_BUTTON_PIN, UP_BUTTON_PIN,
                                      DOWN_BUTTON_PIN, SEL_BUTTON_PIN}

Definition at line 88 of file stm32l152_eval.c.

const uint16_t BUTTON_PIN_SOURCE[BUTTONn]
Initial value:
 {KEY_BUTTON_EXTI_PIN_SOURCE,
                                             RIGHT_BUTTON_EXTI_PIN_SOURCE,
                                             LEFT_BUTTON_EXTI_PIN_SOURCE,
                                             UP_BUTTON_EXTI_PIN_SOURCE,
                                             DOWN_BUTTON_EXTI_PIN_SOURCE,
                                             SEL_BUTTON_EXTI_PIN_SOURCE}

Definition at line 110 of file stm32l152_eval.c.

GPIO_TypeDef* BUTTON_PORT[BUTTONn]
Initial value:
 {KEY_BUTTON_GPIO_PORT, RIGHT_BUTTON_GPIO_PORT,
                                      LEFT_BUTTON_GPIO_PORT, UP_BUTTON_GPIO_PORT,
                                      DOWN_BUTTON_GPIO_PORT, SEL_BUTTON_GPIO_PORT}

Definition at line 84 of file stm32l152_eval.c.

const uint16_t BUTTON_PORT_SOURCE[BUTTONn]
Initial value:
 {KEY_BUTTON_EXTI_PORT_SOURCE,
                                              RIGHT_BUTTON_EXTI_PORT_SOURCE,
                                              LEFT_BUTTON_EXTI_PORT_SOURCE,
                                              UP_BUTTON_EXTI_PORT_SOURCE,
                                              DOWN_BUTTON_EXTI_PORT_SOURCE,
                                              SEL_BUTTON_EXTI_PORT_SOURCE}

Definition at line 103 of file stm32l152_eval.c.

const uint16_t COM_RX_AF[COMn] = {EVAL_COM1_RX_AF, EVAL_COM2_RX_AF}

Definition at line 143 of file stm32l152_eval.c.

Referenced by STM_EVAL_COMInit().

const uint16_t COM_RX_PIN[COMn] = {EVAL_COM1_RX_PIN, EVAL_COM2_RX_PIN}

Definition at line 135 of file stm32l152_eval.c.

const uint16_t COM_RX_PIN_SOURCE[COMn] = {EVAL_COM1_RX_SOURCE, EVAL_COM2_RX_SOURCE}

Definition at line 139 of file stm32l152_eval.c.

Referenced by STM_EVAL_COMInit().

GPIO_TypeDef* COM_RX_PORT[COMn] = {EVAL_COM1_RX_GPIO_PORT, EVAL_COM2_RX_GPIO_PORT}

Definition at line 125 of file stm32l152_eval.c.

const uint32_t COM_RX_PORT_CLK[COMn] = {EVAL_COM1_RX_GPIO_CLK, EVAL_COM2_RX_GPIO_CLK}

Definition at line 131 of file stm32l152_eval.c.

const uint16_t COM_TX_AF[COMn] = {EVAL_COM1_TX_AF, EVAL_COM2_TX_AF}

Definition at line 141 of file stm32l152_eval.c.

Referenced by STM_EVAL_COMInit().

const uint16_t COM_TX_PIN[COMn] = {EVAL_COM1_TX_PIN, EVAL_COM2_TX_PIN}

Definition at line 133 of file stm32l152_eval.c.

const uint16_t COM_TX_PIN_SOURCE[COMn] = {EVAL_COM1_TX_SOURCE, EVAL_COM2_TX_SOURCE}

Definition at line 137 of file stm32l152_eval.c.

Referenced by STM_EVAL_COMInit().

GPIO_TypeDef* COM_TX_PORT[COMn] = {EVAL_COM1_TX_GPIO_PORT, EVAL_COM2_TX_GPIO_PORT}

Definition at line 123 of file stm32l152_eval.c.

const uint32_t COM_TX_PORT_CLK[COMn] = {EVAL_COM1_TX_GPIO_CLK, EVAL_COM2_TX_GPIO_CLK}

Definition at line 129 of file stm32l152_eval.c.

USART_TypeDef* COM_USART[COMn] = {EVAL_COM1, EVAL_COM2}

Definition at line 121 of file stm32l152_eval.c.

const uint32_t COM_USART_CLK[COMn] = {EVAL_COM1_CLK, EVAL_COM2_CLK}

Definition at line 127 of file stm32l152_eval.c.

const uint32_t GPIO_CLK[LEDn]
Initial value:
 {LED1_GPIO_CLK, LED2_GPIO_CLK, LED3_GPIO_CLK,
                                 LED4_GPIO_CLK}

Definition at line 81 of file stm32l152_eval.c.

const uint16_t GPIO_PIN[LEDn]
Initial value:
 {LED1_PIN, LED2_PIN, LED3_PIN,
                                 LED4_PIN}

Definition at line 79 of file stm32l152_eval.c.

GPIO_TypeDef* GPIO_PORT[LEDn]
Initial value:
 {LED1_GPIO_PORT, LED2_GPIO_PORT, LED3_GPIO_PORT,
                                 LED4_GPIO_PORT}

Definition at line 77 of file stm32l152_eval.c.

DMA_InitTypeDef sEEDMA_InitStructure

Definition at line 145 of file stm32l152_eval.c.


STM32F10x Standard Peripherals Firmware Library: STM32L152_EVAL_LOW_LEVEL_Private_FunctionPrototypes

STM32L152_EVAL_LOW_LEVEL_Private_FunctionPrototypes

STM32L152_EVAL_LOW_LEVEL


STM32F10x Standard Peripherals Firmware Library: STM32L152_EVAL_LOW_LEVEL_Private_Functions

Functions

STM32L152_EVAL_LOW_LEVEL_Private_Functions

STM32L152_EVAL_LOW_LEVEL

Functions

void | LM75_LowLevel_DeInit (void)
DeInitializes the LM75_I2C.
void | LM75_LowLevel_Init (void)
Initializes the LM75_I2C.
void | SD_LowLevel_DeInit (void)
DeInitializes the SPI interface.
void | SD_LowLevel_Init (void)
Initializes the SD Card and put it into StandBy State (Ready for data transfer).
void | sEE_LowLevel_DeInit (void)
DeInitializes peripherals used by the I2C EEPROM driver.
void | sEE_LowLevel_DMAConfig (uint32_t pBuffer, uint32_t BufferSize, uint32_t Direction)
Initializes DMA channel used by the I2C EEPROM driver.
void | sEE_LowLevel_Init (void)
Initializes peripherals used by the I2C EEPROM driver.
void | STM_EVAL_COMInit (COM_TypeDef COM, USART_InitTypeDef *USART_InitStruct)
Configures COM port.
void | STM_EVAL_LEDInit (Led_TypeDef Led)
Configures LED GPIO.
void | STM_EVAL_LEDOff (Led_TypeDef Led)
Turns selected LED Off.
void | STM_EVAL_LEDOn (Led_TypeDef Led)
Turns selected LED On.
void | STM_EVAL_LEDToggle (Led_TypeDef Led)
Toggles the selected LED.
uint32_t | STM_EVAL_PBGetState (Button_TypeDef Button)
Returns the selected Button state.
void | STM_EVAL_PBInit (Button_TypeDef Button, ButtonMode_TypeDef Button_Mode)
Configures Button GPIO and EXTI Line.

Function Documentation

void LM75_LowLevel_DeInit ( void )

DeInitializes the LM75_I2C.

Parameters:
None
Return values:
None

< Disable LM75_I2C

< DeInitializes the LM75_I2C

< LM75_I2C Periph clock disable

< Configure LM75_I2C pins: SCL

< Configure LM75_I2C pins: SDA

< Configure LM75_I2C pin: SMBUS ALERT

Definition at line 497 of file stm32l152_eval.c.

References DISABLE, GPIO_Init(), GPIO_InitStructure, GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_IN_FLOATING, GPIO_InitTypeDef::GPIO_Pin, I2C_Cmd(), I2C_DeInit(), LM75_I2C, LM75_I2C_CLK, LM75_I2C_SCL_GPIO_PORT, LM75_I2C_SCL_PIN, LM75_I2C_SDA_GPIO_PORT, LM75_I2C_SDA_PIN, LM75_I2C_SMBUSALERT_GPIO_PORT, LM75_I2C_SMBUSALERT_PIN, and RCC_APB1PeriphClockCmd().

void LM75_LowLevel_Init ( void )

Initializes the LM75_I2C.

Parameters:
None
Return values:
None

< LM75_I2C Periph clock enable

< LM75_I2C_SCL_GPIO_CLK, LM75_I2C_SDA_GPIO_CLK and LM75_I2C_SMBUSALERT_GPIO_CLK Periph clock enable

< Configure LM75_I2C pins: SCL

< Configure LM75_I2C pins: SDA

< Configure LM75_I2C pin: SMBUS ALERT

Definition at line 530 of file stm32l152_eval.c.

References ENABLE, GPIO_Init(), GPIO_InitStructure, GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_AF_OD, GPIO_Mode_IPU, GPIO_InitTypeDef::GPIO_Pin, GPIO_InitTypeDef::GPIO_Speed, GPIO_Speed_50MHz, LM75_I2C_CLK, LM75_I2C_SCL_AF, LM75_I2C_SCL_GPIO_CLK, LM75_I2C_SCL_GPIO_PORT, LM75_I2C_SCL_PIN, LM75_I2C_SCL_SOURCE, LM75_I2C_SDA_AF, LM75_I2C_SDA_GPIO_CLK, LM75_I2C_SDA_GPIO_PORT, LM75_I2C_SDA_PIN, LM75_I2C_SDA_SOURCE, LM75_I2C_SMBUSALERT_AF, LM75_I2C_SMBUSALERT_GPIO_CLK, LM75_I2C_SMBUSALERT_GPIO_PORT, LM75_I2C_SMBUSALERT_PIN, LM75_I2C_SMBUSALERT_SOURCE, RCC_AHBPeriphClockCmd(), RCC_APB1PeriphClockCmd(), and RCC_APB2PeriphClockCmd().

void SD_LowLevel_DeInit ( void )

DeInitializes the SPI interface.

DeInitializes the SD/SD communication.

Parameters:
None
Return values:
None

< SD_SPI disable

< DeInitializes the SD_SPI

< SD_SPI Periph clock disable

< Configure SD_SPI pins: SCK

< Configure SD_SPI pins: MISO

< Configure SD_SPI pins: MOSI

< Configure SD_SPI_CS_PIN pin: SD Card CS pin

< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin

Definition at line 385 of file stm32l152_eval.c.

References DISABLE, GPIO_Init(), GPIO_InitStructure, GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_IN_FLOATING, GPIO_InitTypeDef::GPIO_Pin, RCC_APB1PeriphClockCmd(), RCC_APB2PeriphClockCmd(), SD_CS_GPIO_PORT, SD_CS_PIN, SD_DETECT_GPIO_PORT, SD_DETECT_PIN, SD_SPI, SD_SPI_CLK, SD_SPI_MISO_GPIO_PORT, SD_SPI_MISO_PIN, SD_SPI_MOSI_GPIO_PORT, SD_SPI_MOSI_PIN, SD_SPI_SCK_GPIO_PORT, SD_SPI_SCK_PIN, SPI_Cmd(), and SPI_I2S_DeInit().

void SD_LowLevel_Init ( void )

Initializes the SD Card and put it into StandBy State (Ready for data transfer).

Initializes the SD_SPI and CS pins.

Parameters:
None
Return values:
None

< SD_SPI_CS_GPIO, SD_SPI_MOSI_GPIO, SD_SPI_MISO_GPIO, SD_SPI_DETECT_GPIO and SD_SPI_SCK_GPIO Periph clock enable

< SD_SPI Periph clock enable

< Configure SD_SPI pins: SCK

< Configure SD_SPI pins: MISO

< Configure SD_SPI pins: MOSI

< Configure SD_SPI_CS_PIN pin: SD Card CS pin

< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin

< SD_SPI Config

< SD_SPI enable

Definition at line 424 of file stm32l152_eval.c.

References ENABLE, GPIO_Init(), GPIO_InitStructure, GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_AF_PP, GPIO_Mode_IN_FLOATING, GPIO_Mode_IPU, GPIO_Mode_Out_PP, GPIO_InitTypeDef::GPIO_Pin, GPIO_InitTypeDef::GPIO_Speed, GPIO_Speed_50MHz, RCC_AHBPeriphClockCmd(), RCC_APB1PeriphClockCmd(), RCC_APB2PeriphClockCmd(), SD_CS_GPIO_CLK, SD_CS_GPIO_PORT, SD_CS_PIN, SD_DETECT_GPIO_CLK, SD_DETECT_GPIO_PORT, SD_DETECT_PIN, SD_SPI, SD_SPI_CLK, SD_SPI_MISO_AF, SD_SPI_MISO_GPIO_CLK, SD_SPI_MISO_GPIO_PORT, SD_SPI_MISO_PIN, SD_SPI_MISO_SOURCE, SD_SPI_MOSI_AF, SD_SPI_MOSI_GPIO_CLK, SD_SPI_MOSI_GPIO_PORT, SD_SPI_MOSI_PIN, SD_SPI_MOSI_SOURCE, SD_SPI_SCK_AF, SD_SPI_SCK_GPIO_CLK, SD_SPI_SCK_GPIO_PORT, SD_SPI_SCK_PIN, SD_SPI_SCK_SOURCE, SPI_InitTypeDef::SPI_BaudRatePrescaler, SPI_BaudRatePrescaler_2, SPI_Cmd(), SPI_InitTypeDef::SPI_CPHA, SPI_CPHA_2Edge, SPI_InitTypeDef::SPI_CPOL, SPI_CPOL_High, SPI_InitTypeDef::SPI_CRCPolynomial, SPI_InitTypeDef::SPI_DataSize, SPI_DataSize_8b, SPI_InitTypeDef::SPI_Direction, SPI_Direction_2Lines_FullDuplex, SPI_InitTypeDef::SPI_FirstBit, SPI_FirstBit_MSB, SPI_Init(), SPI_InitStructure, SPI_InitTypeDef::SPI_Mode, SPI_Mode_Master, SPI_InitTypeDef::SPI_NSS, and SPI_NSS_Soft.

void sEE_LowLevel_DeInit ( void )

DeInitializes peripherals used by the I2C EEPROM driver.

Parameters:
None
Return values:
None

< sEE_I2C Periph clock disable

< GPIO configuration

< Configure sEE_I2C pins: SCL

< Configure sEE_I2C pins: SDA

Definition at line 574 of file stm32l152_eval.c.

References DISABLE, DMA_Cmd(), DMA_DeInit(), GPIO_Init(), GPIO_InitStructure, GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_IN_FLOATING, GPIO_InitTypeDef::GPIO_Pin, I2C_Cmd(), I2C_DeInit(), NVIC_Init(), NVIC_InitStructure, NVIC_InitTypeDef::NVIC_IRQChannel, NVIC_InitTypeDef::NVIC_IRQChannelCmd, NVIC_InitTypeDef::NVIC_IRQChannelPreemptionPriority, NVIC_InitTypeDef::NVIC_IRQChannelSubPriority, RCC_APB1PeriphClockCmd(), sEE_I2C, sEE_I2C_CLK, sEE_I2C_DMA_CHANNEL_RX, sEE_I2C_DMA_CHANNEL_TX, sEE_I2C_DMA_PREPRIO, sEE_I2C_DMA_RX_IRQn, sEE_I2C_DMA_SUBPRIO, sEE_I2C_DMA_TX_IRQn, sEE_I2C_SCL_GPIO_PORT, sEE_I2C_SCL_PIN, sEE_I2C_SDA_GPIO_PORT, and sEE_I2C_SDA_PIN.

void sEE_LowLevel_DMAConfig | ( | uint32_t | pBuffer,
 |  | uint32_t | BufferSize,
 |  | uint32_t | Direction
 | ) |  |

Initializes DMA channel used by the I2C EEPROM driver.

Parameters:
None
Return values:
None

Definition at line 708 of file stm32l152_eval.c.

References DMA_InitTypeDef::DMA_BufferSize, DMA_InitTypeDef::DMA_DIR, DMA_DIR_PeripheralDST, DMA_DIR_PeripheralSRC, DMA_Init(), DMA_InitTypeDef::DMA_MemoryBaseAddr, sEE_DIRECTION_TX, sEE_I2C_DMA_CHANNEL_RX, and sEE_I2C_DMA_CHANNEL_TX.

void sEE_LowLevel_Init ( void )

Initializes peripherals used by the I2C EEPROM driver.

Parameters:
None
Return values:
None

< sEE_I2C Periph clock enable

< sEE_I2C_SCL_GPIO_CLK and sEE_I2C_SDA_GPIO_CLK Periph clock enable

< GPIO configuration

< Configure sEE_I2C pins: SCL

< Configure sEE_I2C pins: SDA

< I2C DMA TX and RX channels configuration

Definition at line 624 of file stm32l152_eval.c.

References DISABLE, DMA_InitTypeDef::DMA_BufferSize, DMA_DeInit(), DMA_InitTypeDef::DMA_DIR, DMA_DIR_PeripheralDST, DMA_Init(), DMA_IT_TC, DMA_ITConfig(), DMA_InitTypeDef::DMA_M2M, DMA_M2M_Disable, DMA_InitTypeDef::DMA_MemoryBaseAddr, DMA_InitTypeDef::DMA_MemoryDataSize, DMA_MemoryDataSize_Byte, DMA_InitTypeDef::DMA_MemoryInc, DMA_MemoryInc_Enable, DMA_InitTypeDef::DMA_Mode, DMA_Mode_Normal, DMA_InitTypeDef::DMA_PeripheralBaseAddr, DMA_InitTypeDef::DMA_PeripheralDataSize, DMA_InitTypeDef::DMA_PeripheralInc, DMA_PeripheralInc_Disable, DMA_InitTypeDef::DMA_Priority, DMA_Priority_VeryHigh, ENABLE, GPIO_Init(), GPIO_InitStructure, GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_AF_OD, GPIO_InitTypeDef::GPIO_Pin, GPIO_InitTypeDef::GPIO_Speed, GPIO_Speed_50MHz, NVIC_Init(), NVIC_InitStructure, NVIC_InitTypeDef::NVIC_IRQChannel, NVIC_InitTypeDef::NVIC_IRQChannelCmd, NVIC_InitTypeDef::NVIC_IRQChannelPreemptionPriority, NVIC_InitTypeDef::NVIC_IRQChannelSubPriority, RCC_AHBPeriphClockCmd(), RCC_APB1PeriphClockCmd(), RCC_APB1PeriphResetCmd(), RCC_APB2PeriphClockCmd(), sEE_I2C_CLK, sEE_I2C_DMA_CHANNEL_RX, sEE_I2C_DMA_CHANNEL_TX, sEE_I2C_DMA_CLK, sEE_I2C_DMA_PREPRIO, sEE_I2C_DMA_RX_IRQn, sEE_I2C_DMA_SUBPRIO, sEE_I2C_DMA_TX_IRQn, sEE_I2C_DR_Address, sEE_I2C_SCL_AF, sEE_I2C_SCL_GPIO_CLK, sEE_I2C_SCL_GPIO_PORT, sEE_I2C_SCL_PIN, sEE_I2C_SCL_SOURCE, sEE_I2C_SDA_AF, sEE_I2C_SDA_GPIO_CLK, sEE_I2C_SDA_GPIO_PORT, sEE_I2C_SDA_PIN, and sEE_I2C_SDA_SOURCE.

void STM_EVAL_COMInit | ( | COM_TypeDef | COM,
 |  | USART_InitTypeDef * | USART_InitStruct
 | ) |  |

Configures COM port.

Parameters:
COM,: Specifies the COM port to be configured. This parameter can be one of following parameters:

  • COM1
  • COM2
USART_InitStruct,: pointer to a USART_InitTypeDef structure that contains the configuration information for the specified USART peripheral.
Return values:
None

Definition at line 345 of file stm32l152_eval.c.

References COM1, COM_RX_AF, COM_RX_PIN, COM_RX_PIN_SOURCE, COM_RX_PORT_CLK, COM_TX_AF, COM_TX_PIN, COM_TX_PIN_SOURCE, COM_TX_PORT_CLK, COM_USART_CLK, ENABLE, GPIO_Init(), GPIO_InitStructure, GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_AF_PP, GPIO_Mode_IN_FLOATING, GPIO_InitTypeDef::GPIO_Pin, GPIO_PinRemapConfig(), GPIO_Remap_USART2, GPIO_InitTypeDef::GPIO_Speed, GPIO_Speed_50MHz, RCC_AHBPeriphClockCmd(), RCC_APB1PeriphClockCmd(), RCC_APB2Periph_AFIO, RCC_APB2PeriphClockCmd(), USART_Cmd(), and USART_Init().

void STM_EVAL_LEDInit ( Led_TypeDef Led )

Configures LED GPIO.

Parameters:
Led,: Specifies the Led to be configured. This parameter can be one of following parameters:

  • LED1
  • LED2
  • LED3
  • LED4
Return values:
None

Definition at line 174 of file stm32l152_eval.c.

References ENABLE, GPIO_CLK, GPIO_Init(), GPIO_InitStructure, GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_Out_PP, GPIO_PIN, GPIO_InitTypeDef::GPIO_Pin, GPIO_InitTypeDef::GPIO_Speed, GPIO_Speed_50MHz, RCC_AHBPeriphClockCmd(), and RCC_APB2PeriphClockCmd().

void STM_EVAL_LEDOff ( Led_TypeDef Led )

Turns selected LED Off.

Parameters:
Led,: Specifies the Led to be set off. This parameter can be one of following parameters:

  • LED1
  • LED2
  • LED3
  • LED4
Return values:
None

Definition at line 216 of file stm32l152_eval.c.

References GPIO_TypeDef::BRR, and GPIO_PIN.

void STM_EVAL_LEDOn ( Led_TypeDef Led )

Turns selected LED On.

Parameters:
Led,: Specifies the Led to be set on. This parameter can be one of following parameters:

  • LED1
  • LED2
  • LED3
  • LED4
Return values:
None

Definition at line 201 of file stm32l152_eval.c.

References GPIO_TypeDef::BSRR, and GPIO_PIN.

void STM_EVAL_LEDToggle ( Led_TypeDef Led )

Toggles the selected LED.

Parameters:
Led,: Specifies the Led to be toggled. This parameter can be one of following parameters:

  • LED1
  • LED2
  • LED3
  • LED4
Return values:
None

Definition at line 231 of file stm32l152_eval.c.

References GPIO_PIN, and GPIO_TypeDef::ODR.

uint32_t STM_EVAL_PBGetState ( Button_TypeDef Button )

Returns the selected Button state.

Parameters:
Button,: Specifies the Button to be checked. This parameter can be one of following parameters:

  • BUTTON_KEY: Key Push Button
  • BUTTON_RIGHT: Joystick Right Push Button
  • BUTTON_LEFT: Joystick Left Push Button
  • BUTTON_UP: Joystick Up Push Button
  • BUTTON_DOWN: Joystick Down Push Button
  • BUTTON_SEL: Joystick Sel Push Button
Return values:
- When Button > 1, the Button GPIO pin value is returned.

  • When Button = 0 or 1, error code (0xFF) is returned.

Definition at line 320 of file stm32l152_eval.c.

References BUTTON_PIN, and GPIO_ReadInputDataBit().

void STM_EVAL_PBInit | ( | Button_TypeDef | Button,
 |  | ButtonMode_TypeDef | Button_Mode
 | ) |  |

Configures Button GPIO and EXTI Line.

Parameters:
Button,: Specifies the Button to be configured. This parameter can be one of following parameters:

  • BUTTON_KEY: Key Push Button
  • BUTTON_RIGHT: Joystick Right Push Button
  • BUTTON_LEFT: Joystick Left Push Button
  • BUTTON_UP: Joystick Up Push Button
  • BUTTON_DOWN: Joystick Down Push Button
  • BUTTON_SEL: Joystick Sel Push Button
Button_Mode,: Specifies Button mode. This parameter can be one of following parameters:

  • BUTTON_MODE_GPIO: Button will be used as simple IO
  • BUTTON_MODE_EXTI: Button will be connected to EXTI line with interrupt generation capability
Return values:
None

Definition at line 253 of file stm32l152_eval.c.

References BUTTON_CLK, BUTTON_EXTI_LINE, BUTTON_IRQn, BUTTON_KEY, BUTTON_MODE_EXTI, BUTTON_PIN, BUTTON_PIN_SOURCE, BUTTON_PORT_SOURCE, BUTTON_WAKEUP, ENABLE, EXTI_Init(), EXTI_InitStructure, EXTI_InitTypeDef::EXTI_Line, EXTI_InitTypeDef::EXTI_LineCmd, EXTI_InitTypeDef::EXTI_Mode, EXTI_Mode_Interrupt, EXTI_InitTypeDef::EXTI_Trigger, EXTI_Trigger_Falling, EXTI_Trigger_Rising, GPIO_EXTILineConfig(), GPIO_Init(), GPIO_InitStructure, GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_IN_FLOATING, GPIO_InitTypeDef::GPIO_Pin, NVIC_Init(), NVIC_InitStructure, NVIC_InitTypeDef::NVIC_IRQChannel, NVIC_InitTypeDef::NVIC_IRQChannelCmd, NVIC_InitTypeDef::NVIC_IRQChannelPreemptionPriority, NVIC_InitTypeDef::NVIC_IRQChannelSubPriority, RCC_AHBPeriphClockCmd(), RCC_APB2Periph_AFIO, and RCC_APB2PeriphClockCmd().


STM32F10x Standard Peripherals Firmware Library: STM32L152_EVAL_LOW_LEVEL_Exported_Types

STM32L152_EVAL_LOW_LEVEL_Exported_Types

STM32L152_EVAL_LOW_LEVEL


STM32F10x Standard Peripherals Firmware Library: STM32L152_EVAL_LOW_LEVEL_LED

Defines

STM32L152_EVAL_LOW_LEVEL_LED

STM32L152_EVAL_LOW_LEVEL_Exported_Constants

Defines

#define | LED1_GPIO_CLK RCC_AHBPeriph_GPIOD
#define | LED1_GPIO_PORT GPIOD
#define | LED1_PIN GPIO_Pin_0
#define | LED2_GPIO_CLK RCC_AHBPeriph_GPIOD
#define | LED2_GPIO_PORT GPIOD
#define | LED2_PIN GPIO_Pin_1
#define | LED3_GPIO_CLK RCC_AHBPeriph_GPIOD
#define | LED3_GPIO_PORT GPIOD
#define | LED3_PIN GPIO_Pin_4
#define | LED4_GPIO_CLK RCC_AHBPeriph_GPIOD
#define | LED4_GPIO_PORT GPIOD
#define | LED4_PIN GPIO_Pin_5
#define | LEDn 4

Define Documentation

#define LED1_GPIO_CLK RCC_AHBPeriph_GPIOD

Definition at line 68 of file stm32l152_eval.h.

#define LED1_GPIO_PORT GPIOD

Definition at line 67 of file stm32l152_eval.h.

#define LED1_PIN GPIO_Pin_0

Definition at line 66 of file stm32l152_eval.h.

#define LED2_GPIO_CLK RCC_AHBPeriph_GPIOD

Definition at line 72 of file stm32l152_eval.h.

#define LED2_GPIO_PORT GPIOD

Definition at line 71 of file stm32l152_eval.h.

#define LED2_PIN GPIO_Pin_1

Definition at line 70 of file stm32l152_eval.h.

#define LED3_GPIO_CLK RCC_AHBPeriph_GPIOD

Definition at line 76 of file stm32l152_eval.h.

#define LED3_GPIO_PORT GPIOD

Definition at line 75 of file stm32l152_eval.h.

#define LED3_PIN GPIO_Pin_4

Definition at line 74 of file stm32l152_eval.h.

#define LED4_GPIO_CLK RCC_AHBPeriph_GPIOD

Definition at line 80 of file stm32l152_eval.h.

#define LED4_GPIO_PORT GPIOD

Definition at line 79 of file stm32l152_eval.h.

#define LED4_PIN GPIO_Pin_5

Definition at line 78 of file stm32l152_eval.h.

#define LEDn 4

Definition at line 64 of file stm32l152_eval.h.


STM32F10x Standard Peripherals Firmware Library: STM32L152_EVAL_LOW_LEVEL_BUTTON

Defines

STM32L152_EVAL_LOW_LEVEL_BUTTON

STM32L152_EVAL_LOW_LEVEL_Exported_Constants

Defines

#define | BUTTONn 6
#define | DOWN_BUTTON_EXTI_IRQn EXTI15_10_IRQn
#define | DOWN_BUTTON_EXTI_LINE EXTI_Line10
#define | DOWN_BUTTON_EXTI_PIN_SOURCE EXTI_PinSource10
#define | DOWN_BUTTON_EXTI_PORT_SOURCE EXTI_PortSourceGPIOE
#define | DOWN_BUTTON_GPIO_CLK RCC_AHBPeriph_GPIOE
#define | DOWN_BUTTON_GPIO_PORT GPIOE
#define | DOWN_BUTTON_PIN GPIO_Pin_10
Joystick Down push-button.
#define | KEY_BUTTON_EXTI_IRQn EXTI0_IRQn
#define | KEY_BUTTON_EXTI_LINE EXTI_Line0
#define | KEY_BUTTON_EXTI_PIN_SOURCE EXTI_PinSource0
#define | KEY_BUTTON_EXTI_PORT_SOURCE EXTI_PortSourceGPIOA
#define | KEY_BUTTON_GPIO_CLK RCC_AHBPeriph_GPIOA
#define | KEY_BUTTON_GPIO_PORT GPIOA
#define | KEY_BUTTON_PIN GPIO_Pin_0
Key push-button.
#define | LEFT_BUTTON_EXTI_IRQn EXTI15_10_IRQn
#define | LEFT_BUTTON_EXTI_LINE EXTI_Line12
#define | LEFT_BUTTON_EXTI_PIN_SOURCE EXTI_PinSource12
#define | LEFT_BUTTON_EXTI_PORT_SOURCE EXTI_PortSourceGPIOE
#define | LEFT_BUTTON_GPIO_CLK RCC_AHBPeriph_GPIOE
#define | LEFT_BUTTON_GPIO_PORT GPIOE
#define | LEFT_BUTTON_PIN GPIO_Pin_12
Joystick Left push-button.
#define | RIGHT_BUTTON_EXTI_IRQn EXTI15_10_IRQn
#define | RIGHT_BUTTON_EXTI_LINE EXTI_Line11
#define | RIGHT_BUTTON_EXTI_PIN_SOURCE EXTI_PinSource11
#define | RIGHT_BUTTON_EXTI_PORT_SOURCE EXTI_PortSourceGPIOE
#define | RIGHT_BUTTON_GPIO_CLK RCC_AHBPeriph_GPIOE
#define | RIGHT_BUTTON_GPIO_PORT GPIOE
#define | RIGHT_BUTTON_PIN GPIO_Pin_11
Joystick Right push-button.
#define | SEL_BUTTON_EXTI_IRQn EXTI9_5_IRQn
#define | SEL_BUTTON_EXTI_LINE EXTI_Line8
#define | SEL_BUTTON_EXTI_PIN_SOURCE EXTI_PinSource8
#define | SEL_BUTTON_EXTI_PORT_SOURCE EXTI_PortSourceGPIOE
#define | SEL_BUTTON_GPIO_CLK RCC_AHBPeriph_GPIOE
#define | SEL_BUTTON_GPIO_PORT GPIOE
#define | SEL_BUTTON_PIN GPIO_Pin_8
Joystick Sel push-button.
#define | UP_BUTTON_EXTI_IRQn EXTI9_5_IRQn
#define | UP_BUTTON_EXTI_LINE EXTI_Line9
#define | UP_BUTTON_EXTI_PIN_SOURCE EXTI_PinSource9
#define | UP_BUTTON_EXTI_PORT_SOURCE EXTI_PortSourceGPIOE
#define | UP_BUTTON_GPIO_CLK RCC_AHBPeriph_GPIOE
#define | UP_BUTTON_GPIO_PORT GPIOE
#define | UP_BUTTON_PIN GPIO_Pin_9
Joystick Up push-button.

Define Documentation

#define BUTTONn 6

Definition at line 89 of file stm32l152_eval.h.

#define DOWN_BUTTON_EXTI_IRQn EXTI15_10_IRQn

Definition at line 146 of file stm32l152_eval.h.

#define DOWN_BUTTON_EXTI_LINE EXTI_Line10

Definition at line 143 of file stm32l152_eval.h.

#define DOWN_BUTTON_EXTI_PIN_SOURCE EXTI_PinSource10

Definition at line 145 of file stm32l152_eval.h.

#define DOWN_BUTTON_EXTI_PORT_SOURCE EXTI_PortSourceGPIOE

Definition at line 144 of file stm32l152_eval.h.

#define DOWN_BUTTON_GPIO_CLK RCC_AHBPeriph_GPIOE

Definition at line 142 of file stm32l152_eval.h.

#define DOWN_BUTTON_GPIO_PORT GPIOE

Definition at line 141 of file stm32l152_eval.h.

#define DOWN_BUTTON_PIN GPIO_Pin_10

Joystick Down push-button.

Definition at line 140 of file stm32l152_eval.h.

#define KEY_BUTTON_EXTI_IRQn EXTI0_IRQn

Definition at line 102 of file stm32l152_eval.h.

#define KEY_BUTTON_EXTI_LINE EXTI_Line0

Definition at line 99 of file stm32l152_eval.h.

#define KEY_BUTTON_EXTI_PIN_SOURCE EXTI_PinSource0

Definition at line 101 of file stm32l152_eval.h.

#define KEY_BUTTON_EXTI_PORT_SOURCE EXTI_PortSourceGPIOA

Definition at line 100 of file stm32l152_eval.h.

#define KEY_BUTTON_GPIO_CLK RCC_AHBPeriph_GPIOA

Definition at line 98 of file stm32l152_eval.h.

#define KEY_BUTTON_GPIO_PORT GPIOA

Definition at line 97 of file stm32l152_eval.h.

#define KEY_BUTTON_PIN GPIO_Pin_0

Key push-button.

Definition at line 96 of file stm32l152_eval.h.

#define LEFT_BUTTON_EXTI_IRQn EXTI15_10_IRQn

Definition at line 124 of file stm32l152_eval.h.

#define LEFT_BUTTON_EXTI_LINE EXTI_Line12

Definition at line 121 of file stm32l152_eval.h.

#define LEFT_BUTTON_EXTI_PIN_SOURCE EXTI_PinSource12

Definition at line 123 of file stm32l152_eval.h.

#define LEFT_BUTTON_EXTI_PORT_SOURCE EXTI_PortSourceGPIOE

Definition at line 122 of file stm32l152_eval.h.

#define LEFT_BUTTON_GPIO_CLK RCC_AHBPeriph_GPIOE

Definition at line 120 of file stm32l152_eval.h.

#define LEFT_BUTTON_GPIO_PORT GPIOE

Definition at line 119 of file stm32l152_eval.h.

#define LEFT_BUTTON_PIN GPIO_Pin_12

Joystick Left push-button.

Definition at line 118 of file stm32l152_eval.h.

#define RIGHT_BUTTON_EXTI_IRQn EXTI15_10_IRQn

Definition at line 113 of file stm32l152_eval.h.

#define RIGHT_BUTTON_EXTI_LINE EXTI_Line11

Definition at line 110 of file stm32l152_eval.h.

#define RIGHT_BUTTON_EXTI_PIN_SOURCE EXTI_PinSource11

Definition at line 112 of file stm32l152_eval.h.

#define RIGHT_BUTTON_EXTI_PORT_SOURCE EXTI_PortSourceGPIOE

Definition at line 111 of file stm32l152_eval.h.

#define RIGHT_BUTTON_GPIO_CLK RCC_AHBPeriph_GPIOE

Definition at line 109 of file stm32l152_eval.h.

#define RIGHT_BUTTON_GPIO_PORT GPIOE

Definition at line 108 of file stm32l152_eval.h.

#define RIGHT_BUTTON_PIN GPIO_Pin_11

Joystick Right push-button.

Definition at line 107 of file stm32l152_eval.h.

#define SEL_BUTTON_EXTI_IRQn EXTI9_5_IRQn

Definition at line 157 of file stm32l152_eval.h.

#define SEL_BUTTON_EXTI_LINE EXTI_Line8

Definition at line 154 of file stm32l152_eval.h.

#define SEL_BUTTON_EXTI_PIN_SOURCE EXTI_PinSource8

Definition at line 156 of file stm32l152_eval.h.

#define SEL_BUTTON_EXTI_PORT_SOURCE EXTI_PortSourceGPIOE

Definition at line 155 of file stm32l152_eval.h.

#define SEL_BUTTON_GPIO_CLK RCC_AHBPeriph_GPIOE

Definition at line 153 of file stm32l152_eval.h.

#define SEL_BUTTON_GPIO_PORT GPIOE

Definition at line 152 of file stm32l152_eval.h.

#define SEL_BUTTON_PIN GPIO_Pin_8

Joystick Sel push-button.

Definition at line 151 of file stm32l152_eval.h.

#define UP_BUTTON_EXTI_IRQn EXTI9_5_IRQn

Definition at line 135 of file stm32l152_eval.h.

#define UP_BUTTON_EXTI_LINE EXTI_Line9

Definition at line 132 of file stm32l152_eval.h.

#define UP_BUTTON_EXTI_PIN_SOURCE EXTI_PinSource9

Definition at line 134 of file stm32l152_eval.h.

#define UP_BUTTON_EXTI_PORT_SOURCE EXTI_PortSourceGPIOE

Definition at line 133 of file stm32l152_eval.h.

#define UP_BUTTON_GPIO_CLK RCC_AHBPeriph_GPIOE

Definition at line 131 of file stm32l152_eval.h.

#define UP_BUTTON_GPIO_PORT GPIOE

Definition at line 130 of file stm32l152_eval.h.

#define UP_BUTTON_PIN GPIO_Pin_9

Joystick Up push-button.

Definition at line 129 of file stm32l152_eval.h.


STM32F10x Standard Peripherals Firmware Library: STM32L152_EVAL_LOW_LEVEL_COM

Defines

STM32L152_EVAL_LOW_LEVEL_COM

STM32L152_EVAL_LOW_LEVEL_Exported_Constants

Defines

#define | COMn 2
#define | EVAL_COM1 USART2
Definition for COM port1, connected to USART2.
#define | EVAL_COM1_CLK RCC_APB1Periph_USART2
#define | EVAL_COM1_CTS_AF GPIO_AF_USART2
#define | EVAL_COM1_CTS_GPIO_CLK RCC_AHBPeriph_GPIOD
#define | EVAL_COM1_CTS_GPIO_PORT GPIOD
#define | EVAL_COM1_CTS_PIN GPIO_Pin_3
#define | EVAL_COM1_CTS_SOURCE GPIO_PinSource3
#define | EVAL_COM1_IRQn USART2_IRQn
#define | EVAL_COM1_RTS_AF GPIO_AF_USART2
#define | EVAL_COM1_RTS_GPIO_CLK RCC_AHBPeriph_GPIOD
#define | EVAL_COM1_RTS_GPIO_PORT GPIOD
#define | EVAL_COM1_RTS_PIN GPIO_Pin_4
#define | EVAL_COM1_RTS_SOURCE GPIO_PinSource4
#define | EVAL_COM1_RX_AF GPIO_AF_USART2
#define | EVAL_COM1_RX_GPIO_CLK RCC_AHBPeriph_GPIOD
#define | EVAL_COM1_RX_GPIO_PORT GPIOD
#define | EVAL_COM1_RX_PIN GPIO_Pin_6
#define | EVAL_COM1_RX_SOURCE GPIO_PinSource6
#define | EVAL_COM1_TX_AF GPIO_AF_USART2
#define | EVAL_COM1_TX_GPIO_CLK RCC_AHBPeriph_GPIOD
#define | EVAL_COM1_TX_GPIO_PORT GPIOD
#define | EVAL_COM1_TX_PIN GPIO_Pin_5
#define | EVAL_COM1_TX_SOURCE GPIO_PinSource5
#define | EVAL_COM2 USART3
Definition for COM port2, connected to USART3.
#define | EVAL_COM2_CLK RCC_APB1Periph_USART3
#define | EVAL_COM2_IRQn USART3_IRQn
#define | EVAL_COM2_RX_AF GPIO_AF_USART3
#define | EVAL_COM2_RX_GPIO_CLK RCC_AHBPeriph_GPIOC
#define | EVAL_COM2_RX_GPIO_PORT GPIOC
#define | EVAL_COM2_RX_PIN GPIO_Pin_11
#define | EVAL_COM2_RX_SOURCE GPIO_PinSource11
#define | EVAL_COM2_TX_AF GPIO_AF_USART3
#define | EVAL_COM2_TX_GPIO_CLK RCC_AHBPeriph_GPIOC
#define | EVAL_COM2_TX_GPIO_PORT GPIOC
#define | EVAL_COM2_TX_PIN GPIO_Pin_10
#define | EVAL_COM2_TX_SOURCE GPIO_PinSource10

Define Documentation

#define COMn 2

Definition at line 166 of file stm32l152_eval.h.

#define EVAL_COM1 USART2

Definition for COM port1, connected to USART2.

Definition at line 171 of file stm32l152_eval.h.

#define EVAL_COM1_CLK RCC_APB1Periph_USART2

Definition at line 172 of file stm32l152_eval.h.

#define EVAL_COM1_CTS_AF GPIO_AF_USART2

Definition at line 196 of file stm32l152_eval.h.

#define EVAL_COM1_CTS_GPIO_CLK RCC_AHBPeriph_GPIOD

Definition at line 194 of file stm32l152_eval.h.

#define EVAL_COM1_CTS_GPIO_PORT GPIOD

Definition at line 193 of file stm32l152_eval.h.

#define EVAL_COM1_CTS_PIN GPIO_Pin_3

Definition at line 192 of file stm32l152_eval.h.

#define EVAL_COM1_CTS_SOURCE GPIO_PinSource3

Definition at line 195 of file stm32l152_eval.h.

#define EVAL_COM1_IRQn USART2_IRQn

Definition at line 198 of file stm32l152_eval.h.

#define EVAL_COM1_RTS_AF GPIO_AF_USART2

Definition at line 190 of file stm32l152_eval.h.

#define EVAL_COM1_RTS_GPIO_CLK RCC_AHBPeriph_GPIOD

Definition at line 188 of file stm32l152_eval.h.

#define EVAL_COM1_RTS_GPIO_PORT GPIOD

Definition at line 187 of file stm32l152_eval.h.

#define EVAL_COM1_RTS_PIN GPIO_Pin_4

Definition at line 186 of file stm32l152_eval.h.

#define EVAL_COM1_RTS_SOURCE GPIO_PinSource4

Definition at line 189 of file stm32l152_eval.h.

#define EVAL_COM1_RX_AF GPIO_AF_USART2

Definition at line 184 of file stm32l152_eval.h.

#define EVAL_COM1_RX_GPIO_CLK RCC_AHBPeriph_GPIOD

Definition at line 182 of file stm32l152_eval.h.

#define EVAL_COM1_RX_GPIO_PORT GPIOD

Definition at line 181 of file stm32l152_eval.h.

#define EVAL_COM1_RX_PIN GPIO_Pin_6

Definition at line 180 of file stm32l152_eval.h.

#define EVAL_COM1_RX_SOURCE GPIO_PinSource6

Definition at line 183 of file stm32l152_eval.h.

#define EVAL_COM1_TX_AF GPIO_AF_USART2

Definition at line 178 of file stm32l152_eval.h.

#define EVAL_COM1_TX_GPIO_CLK RCC_AHBPeriph_GPIOD

Definition at line 176 of file stm32l152_eval.h.

#define EVAL_COM1_TX_GPIO_PORT GPIOD

Definition at line 175 of file stm32l152_eval.h.

#define EVAL_COM1_TX_PIN GPIO_Pin_5

Definition at line 174 of file stm32l152_eval.h.

#define EVAL_COM1_TX_SOURCE GPIO_PinSource5

Definition at line 177 of file stm32l152_eval.h.

#define EVAL_COM2 USART3

Definition for COM port2, connected to USART3.

Definition at line 203 of file stm32l152_eval.h.

#define EVAL_COM2_CLK RCC_APB1Periph_USART3

Definition at line 204 of file stm32l152_eval.h.

#define EVAL_COM2_IRQn USART3_IRQn

Definition at line 218 of file stm32l152_eval.h.

#define EVAL_COM2_RX_AF GPIO_AF_USART3

Definition at line 216 of file stm32l152_eval.h.

#define EVAL_COM2_RX_GPIO_CLK RCC_AHBPeriph_GPIOC

Definition at line 214 of file stm32l152_eval.h.

#define EVAL_COM2_RX_GPIO_PORT GPIOC

Definition at line 213 of file stm32l152_eval.h.

#define EVAL_COM2_RX_PIN GPIO_Pin_11

Definition at line 212 of file stm32l152_eval.h.

#define EVAL_COM2_RX_SOURCE GPIO_PinSource11

Definition at line 215 of file stm32l152_eval.h.

#define EVAL_COM2_TX_AF GPIO_AF_USART3

Definition at line 210 of file stm32l152_eval.h.

#define EVAL_COM2_TX_GPIO_CLK RCC_AHBPeriph_GPIOC

Definition at line 208 of file stm32l152_eval.h.

#define EVAL_COM2_TX_GPIO_PORT GPIOC

Definition at line 207 of file stm32l152_eval.h.

#define EVAL_COM2_TX_PIN GPIO_Pin_10

Definition at line 206 of file stm32l152_eval.h.

#define EVAL_COM2_TX_SOURCE GPIO_PinSource10

Definition at line 209 of file stm32l152_eval.h.


STM32F10x Standard Peripherals Firmware Library: STM32L152_EVAL_LOW_LEVEL_SD_FLASH

Defines

STM32L152_EVAL_LOW_LEVEL_SD_FLASH

STM32L152_EVAL_LOW_LEVEL_Exported_Constants

Defines

#define | SD_CS_GPIO_CLK RCC_AHBPeriph_GPIOD
#define | SD_CS_GPIO_PORT GPIOD
#define | SD_CS_PIN GPIO_Pin_7
#define | SD_DETECT_EXTI_IRQn EXTI9_5_IRQn
#define | SD_DETECT_EXTI_LINE EXTI_Line6
#define | SD_DETECT_EXTI_PIN_SOURCE EXTI_PinSource6
#define | SD_DETECT_EXTI_PORT_SOURCE EXTI_PortSourceGPIOE
#define | SD_DETECT_GPIO_CLK RCC_AHBPeriph_GPIOE
#define | SD_DETECT_GPIO_PORT GPIOE
#define | SD_DETECT_PIN GPIO_Pin_6
#define | SD_SPI SPI2
SD Card SPI Interface.
#define | SD_SPI_CLK RCC_APB1Periph_SPI2
#define | SD_SPI_MISO_AF GPIO_AF_SPI2
#define | SD_SPI_MISO_GPIO_CLK RCC_AHBPeriph_GPIOB
#define | SD_SPI_MISO_GPIO_PORT GPIOB
#define | SD_SPI_MISO_PIN GPIO_Pin_14
#define | SD_SPI_MISO_SOURCE GPIO_PinSource14
#define | SD_SPI_MOSI_AF GPIO_AF_SPI2
#define | SD_SPI_MOSI_GPIO_CLK RCC_AHBPeriph_GPIOB
#define | SD_SPI_MOSI_GPIO_PORT GPIOB
#define | SD_SPI_MOSI_PIN GPIO_Pin_15
#define | SD_SPI_MOSI_SOURCE GPIO_PinSource15
#define | SD_SPI_SCK_AF GPIO_AF_SPI2
#define | SD_SPI_SCK_GPIO_CLK RCC_AHBPeriph_GPIOB
#define | SD_SPI_SCK_GPIO_PORT GPIOB
#define | SD_SPI_SCK_PIN GPIO_Pin_13
#define | SD_SPI_SCK_SOURCE GPIO_PinSource13

Define Documentation

#define SD_CS_GPIO_CLK RCC_AHBPeriph_GPIOD

Definition at line 249 of file stm32l152_eval.h.

#define SD_CS_GPIO_PORT GPIOD

Definition at line 248 of file stm32l152_eval.h.

#define SD_CS_PIN GPIO_Pin_7

Definition at line 247 of file stm32l152_eval.h.

#define SD_DETECT_EXTI_IRQn EXTI9_5_IRQn

Definition at line 257 of file stm32l152_eval.h.

#define SD_DETECT_EXTI_LINE EXTI_Line6

Definition at line 251 of file stm32l152_eval.h.

#define SD_DETECT_EXTI_PIN_SOURCE EXTI_PinSource6

Definition at line 252 of file stm32l152_eval.h.

#define SD_DETECT_EXTI_PORT_SOURCE EXTI_PortSourceGPIOE

Definition at line 256 of file stm32l152_eval.h.

#define SD_DETECT_GPIO_CLK RCC_AHBPeriph_GPIOE

Definition at line 255 of file stm32l152_eval.h.

#define SD_DETECT_GPIO_PORT GPIOE

Definition at line 254 of file stm32l152_eval.h.

#define SD_DETECT_PIN GPIO_Pin_6

Definition at line 250 of file stm32l152_eval.h.

#define SD_SPI SPI2

SD Card SPI Interface.

Definition at line 230 of file stm32l152_eval.h.

#define SD_SPI_CLK RCC_APB1Periph_SPI2

Definition at line 231 of file stm32l152_eval.h.

#define SD_SPI_MISO_AF GPIO_AF_SPI2

Definition at line 241 of file stm32l152_eval.h.

Referenced by SD_LowLevel_Init().

#define SD_SPI_MISO_GPIO_CLK RCC_AHBPeriph_GPIOB

Definition at line 239 of file stm32l152_eval.h.

#define SD_SPI_MISO_GPIO_PORT GPIOB

Definition at line 238 of file stm32l152_eval.h.

#define SD_SPI_MISO_PIN GPIO_Pin_14

Definition at line 237 of file stm32l152_eval.h.

#define SD_SPI_MISO_SOURCE GPIO_PinSource14

Definition at line 240 of file stm32l152_eval.h.

Referenced by SD_LowLevel_Init().

#define SD_SPI_MOSI_AF GPIO_AF_SPI2

Definition at line 246 of file stm32l152_eval.h.

Referenced by SD_LowLevel_Init().

#define SD_SPI_MOSI_GPIO_CLK RCC_AHBPeriph_GPIOB

Definition at line 244 of file stm32l152_eval.h.

#define SD_SPI_MOSI_GPIO_PORT GPIOB

Definition at line 243 of file stm32l152_eval.h.

#define SD_SPI_MOSI_PIN GPIO_Pin_15

Definition at line 242 of file stm32l152_eval.h.

#define SD_SPI_MOSI_SOURCE GPIO_PinSource15

Definition at line 245 of file stm32l152_eval.h.

Referenced by SD_LowLevel_Init().

#define SD_SPI_SCK_AF GPIO_AF_SPI2

Definition at line 236 of file stm32l152_eval.h.

Referenced by SD_LowLevel_Init().

#define SD_SPI_SCK_GPIO_CLK RCC_AHBPeriph_GPIOB

Definition at line 234 of file stm32l152_eval.h.

#define SD_SPI_SCK_GPIO_PORT GPIOB

Definition at line 233 of file stm32l152_eval.h.

#define SD_SPI_SCK_PIN GPIO_Pin_13

Definition at line 232 of file stm32l152_eval.h.

#define SD_SPI_SCK_SOURCE GPIO_PinSource13

Definition at line 235 of file stm32l152_eval.h.

Referenced by SD_LowLevel_Init().


STM32F10x Standard Peripherals Firmware Library: STM32L152_EVAL_LOW_LEVEL_TSENSOR_I2C

Defines

STM32L152_EVAL_LOW_LEVEL_TSENSOR_I2C

STM32L152_EVAL_LOW_LEVEL_Exported_Constants

Defines

#define | LM75_DMA_CLK RCC_AHBPeriph_DMA1
#define | LM75_DMA_RX_CHANNEL DMA1_Channel7
#define | LM75_DMA_RX_TCFLAG DMA1_FLAG_TC7
#define | LM75_DMA_TX_CHANNEL DMA1_Channel6
#define | LM75_DMA_TX_TCFLAG DMA1_FLAG_TC6
#define | LM75_I2C I2C1
LM75 Temperature Sensor I2C Interface pins.
#define | LM75_I2C_CLK RCC_APB1Periph_I2C1
#define | LM75_I2C_DR ((uint32_t)0x40005410)
#define | LM75_I2C_SCL_AF GPIO_AF_I2C1
#define | LM75_I2C_SCL_GPIO_CLK RCC_AHBPeriph_GPIOB
#define | LM75_I2C_SCL_GPIO_PORT GPIOB
#define | LM75_I2C_SCL_PIN GPIO_Pin_6
#define | LM75_I2C_SCL_SOURCE GPIO_PinSource6
#define | LM75_I2C_SDA_AF GPIO_AF_I2C1
#define | LM75_I2C_SDA_GPIO_CLK RCC_AHBPeriph_GPIOB
#define | LM75_I2C_SDA_GPIO_PORT GPIOB
#define | LM75_I2C_SDA_PIN GPIO_Pin_7
#define | LM75_I2C_SDA_SOURCE GPIO_PinSource7
#define | LM75_I2C_SMBUSALERT_AF GPIO_AF_I2C1
#define | LM75_I2C_SMBUSALERT_GPIO_CLK RCC_AHBPeriph_GPIOB
#define | LM75_I2C_SMBUSALERT_GPIO_PORT GPIOB
#define | LM75_I2C_SMBUSALERT_PIN GPIO_Pin_5
#define | LM75_I2C_SMBUSALERT_SOURCE GPIO_PinSource5

Define Documentation

#define LM75_DMA_CLK RCC_AHBPeriph_DMA1

Definition at line 287 of file stm32l152_eval.h.

#define LM75_DMA_RX_CHANNEL DMA1_Channel7

Definition at line 289 of file stm32l152_eval.h.

#define LM75_DMA_RX_TCFLAG DMA1_FLAG_TC7

Definition at line 291 of file stm32l152_eval.h.

#define LM75_DMA_TX_CHANNEL DMA1_Channel6

Definition at line 288 of file stm32l152_eval.h.

#define LM75_DMA_TX_TCFLAG DMA1_FLAG_TC6

Definition at line 290 of file stm32l152_eval.h.

#define LM75_I2C I2C1

LM75 Temperature Sensor I2C Interface pins.

Definition at line 268 of file stm32l152_eval.h.

#define LM75_I2C_CLK RCC_APB1Periph_I2C1

Definition at line 269 of file stm32l152_eval.h.

#define LM75_I2C_DR ((uint32_t)0x40005410)

Definition at line 285 of file stm32l152_eval.h.

#define LM75_I2C_SCL_AF GPIO_AF_I2C1

Definition at line 274 of file stm32l152_eval.h.

Referenced by LM75_LowLevel_Init().

#define LM75_I2C_SCL_GPIO_CLK RCC_AHBPeriph_GPIOB

Definition at line 272 of file stm32l152_eval.h.

#define LM75_I2C_SCL_GPIO_PORT GPIOB

Definition at line 271 of file stm32l152_eval.h.

#define LM75_I2C_SCL_PIN GPIO_Pin_6

Definition at line 270 of file stm32l152_eval.h.

#define LM75_I2C_SCL_SOURCE GPIO_PinSource6

Definition at line 273 of file stm32l152_eval.h.

Referenced by LM75_LowLevel_Init().

#define LM75_I2C_SDA_AF GPIO_AF_I2C1

Definition at line 279 of file stm32l152_eval.h.

Referenced by LM75_LowLevel_Init().

#define LM75_I2C_SDA_GPIO_CLK RCC_AHBPeriph_GPIOB

Definition at line 277 of file stm32l152_eval.h.

#define LM75_I2C_SDA_GPIO_PORT GPIOB

Definition at line 276 of file stm32l152_eval.h.

#define LM75_I2C_SDA_PIN GPIO_Pin_7

Definition at line 275 of file stm32l152_eval.h.

#define LM75_I2C_SDA_SOURCE GPIO_PinSource7

Definition at line 278 of file stm32l152_eval.h.

Referenced by LM75_LowLevel_Init().

#define LM75_I2C_SMBUSALERT_AF GPIO_AF_I2C1

Definition at line 284 of file stm32l152_eval.h.

Referenced by LM75_LowLevel_Init().

#define LM75_I2C_SMBUSALERT_GPIO_CLK RCC_AHBPeriph_GPIOB

Definition at line 282 of file stm32l152_eval.h.

#define LM75_I2C_SMBUSALERT_GPIO_PORT GPIOB

Definition at line 281 of file stm32l152_eval.h.

#define LM75_I2C_SMBUSALERT_PIN GPIO_Pin_5

Definition at line 280 of file stm32l152_eval.h.

#define LM75_I2C_SMBUSALERT_SOURCE GPIO_PinSource5

Definition at line 283 of file stm32l152_eval.h.

Referenced by LM75_LowLevel_Init().


STM32F10x Standard Peripherals Firmware Library: STM32L152_EVAL_LOW_LEVEL_I2C_EE

Defines

STM32L152_EVAL_LOW_LEVEL_I2C_EE

STM32L152_EVAL_LOW_LEVEL_Exported_Constants

Defines

#define | sEE_DIRECTION_RX 1
#define | sEE_DIRECTION_TX 0
#define | sEE_I2C I2C1
I2C EEPROM Interface pins.
#define | sEE_I2C_CLK RCC_APB1Periph_I2C1
#define | sEE_I2C_DMA DMA1
#define | sEE_I2C_DMA_CHANNEL_RX DMA1_Channel7
#define | sEE_I2C_DMA_CHANNEL_TX DMA1_Channel6
#define | sEE_I2C_DMA_CLK RCC_AHBPeriph_DMA1
#define | sEE_I2C_DMA_FLAG_RX_GL DMA1_IT_GL7
#define | sEE_I2C_DMA_FLAG_RX_TC DMA1_IT_TC7
#define | sEE_I2C_DMA_FLAG_TX_GL DMA1_IT_GL6
#define | sEE_I2C_DMA_FLAG_TX_TC DMA1_IT_TC6
#define | sEE_I2C_DMA_PREPRIO 0
#define | sEE_I2C_DMA_RX_IRQHandler DMA1_Channel7_IRQHandler
#define | sEE_I2C_DMA_RX_IRQn DMA1_Channel7_IRQn
#define | sEE_I2C_DMA_SUBPRIO 0
#define | sEE_I2C_DMA_TX_IRQHandler DMA1_Channel6_IRQHandler
#define | sEE_I2C_DMA_TX_IRQn DMA1_Channel6_IRQn
#define | sEE_I2C_DR_Address ((uint32_t)0x40005410)
#define | sEE_I2C_SCL_AF GPIO_AF_I2C1
#define | sEE_I2C_SCL_GPIO_CLK RCC_AHBPeriph_GPIOB
#define | sEE_I2C_SCL_GPIO_PORT GPIOB
#define | sEE_I2C_SCL_PIN GPIO_Pin_6
#define | sEE_I2C_SCL_SOURCE GPIO_PinSource6
#define | sEE_I2C_SDA_AF GPIO_AF_I2C1
#define | sEE_I2C_SDA_GPIO_CLK RCC_AHBPeriph_GPIOB
#define | sEE_I2C_SDA_GPIO_PORT GPIOB
#define | sEE_I2C_SDA_PIN GPIO_Pin_7
#define | sEE_I2C_SDA_SOURCE GPIO_PinSource7
#define | sEE_M24C64_32
#define | sEE_TIME_CONST 24
#define | sEE_USE_DMA

Define Documentation

#define sEE_DIRECTION_RX 1

Definition at line 337 of file stm32l152_eval.h.

#define sEE_DIRECTION_TX 0

Definition at line 336 of file stm32l152_eval.h.

#define sEE_I2C I2C1

I2C EEPROM Interface pins.

Definition at line 304 of file stm32l152_eval.h.

#define sEE_I2C_CLK RCC_APB1Periph_I2C1

Definition at line 305 of file stm32l152_eval.h.

#define sEE_I2C_DMA DMA1

Definition at line 318 of file stm32l152_eval.h.

#define sEE_I2C_DMA_CHANNEL_RX DMA1_Channel7

Definition at line 320 of file stm32l152_eval.h.

#define sEE_I2C_DMA_CHANNEL_TX DMA1_Channel6

Definition at line 319 of file stm32l152_eval.h.

#define sEE_I2C_DMA_CLK RCC_AHBPeriph_DMA1

Definition at line 325 of file stm32l152_eval.h.

#define sEE_I2C_DMA_FLAG_RX_GL DMA1_IT_GL7

Definition at line 324 of file stm32l152_eval.h.

#define sEE_I2C_DMA_FLAG_RX_TC DMA1_IT_TC7

Definition at line 323 of file stm32l152_eval.h.

#define sEE_I2C_DMA_FLAG_TX_GL DMA1_IT_GL6

Definition at line 322 of file stm32l152_eval.h.

#define sEE_I2C_DMA_FLAG_TX_TC DMA1_IT_TC6

Definition at line 321 of file stm32l152_eval.h.

#define sEE_I2C_DMA_PREPRIO 0

Definition at line 333 of file stm32l152_eval.h.

#define sEE_I2C_DMA_RX_IRQHandler DMA1_Channel7_IRQHandler

Definition at line 332 of file stm32l152_eval.h.

#define sEE_I2C_DMA_RX_IRQn DMA1_Channel7_IRQn

Definition at line 330 of file stm32l152_eval.h.

#define sEE_I2C_DMA_SUBPRIO 0

Definition at line 334 of file stm32l152_eval.h.

#define sEE_I2C_DMA_TX_IRQHandler DMA1_Channel6_IRQHandler

Definition at line 331 of file stm32l152_eval.h.

#define sEE_I2C_DMA_TX_IRQn DMA1_Channel6_IRQn

Definition at line 329 of file stm32l152_eval.h.

#define sEE_I2C_DR_Address ((uint32_t)0x40005410)

Definition at line 326 of file stm32l152_eval.h.

#define sEE_I2C_SCL_AF GPIO_AF_I2C1

Definition at line 310 of file stm32l152_eval.h.

Referenced by sEE_LowLevel_Init().

#define sEE_I2C_SCL_GPIO_CLK RCC_AHBPeriph_GPIOB

Definition at line 308 of file stm32l152_eval.h.

#define sEE_I2C_SCL_GPIO_PORT GPIOB

Definition at line 307 of file stm32l152_eval.h.

#define sEE_I2C_SCL_PIN GPIO_Pin_6

Definition at line 306 of file stm32l152_eval.h.

#define sEE_I2C_SCL_SOURCE GPIO_PinSource6

Definition at line 309 of file stm32l152_eval.h.

Referenced by sEE_LowLevel_Init().

#define sEE_I2C_SDA_AF GPIO_AF_I2C1

Definition at line 315 of file stm32l152_eval.h.

Referenced by sEE_LowLevel_Init().

#define sEE_I2C_SDA_GPIO_CLK RCC_AHBPeriph_GPIOB

Definition at line 313 of file stm32l152_eval.h.

#define sEE_I2C_SDA_GPIO_PORT GPIOB

Definition at line 312 of file stm32l152_eval.h.

#define sEE_I2C_SDA_PIN GPIO_Pin_7

Definition at line 311 of file stm32l152_eval.h.

#define sEE_I2C_SDA_SOURCE GPIO_PinSource7

Definition at line 314 of file stm32l152_eval.h.

Referenced by sEE_LowLevel_Init().

#define sEE_M24C64_32

Definition at line 316 of file stm32l152_eval.h.

#define sEE_TIME_CONST 24

Definition at line 342 of file stm32l152_eval.h.

#define sEE_USE_DMA

Definition at line 327 of file stm32l152_eval.h.


STM32F10x Standard Peripherals Firmware Library: STM32L152_EVAL_LOW_LEVEL_Exported_Macros

STM32L152_EVAL_LOW_LEVEL_Exported_Macros

STM32L152_EVAL_LOW_LEVEL


STM32F10x Standard Peripherals Firmware Library: STM32L152_EVAL_LOW_LEVEL_Exported_Functions

Functions

STM32L152_EVAL_LOW_LEVEL_Exported_Functions

STM32L152_EVAL_LOW_LEVEL

Functions

void | LM75_LowLevel_DeInit (void)
DeInitializes the LM75_I2C.
void | LM75_LowLevel_Init (void)
Initializes the LM75_I2C.
void | SD_LowLevel_DeInit (void)
DeInitializes the SD/SD communication.
void | SD_LowLevel_Init (void)
Initializes the SD_SPI and CS pins.
void | sEE_LowLevel_DeInit (void)
DeInitializes peripherals used by the I2C EEPROM driver.
void | sEE_LowLevel_DMAConfig (uint32_t pBuffer, uint32_t BufferSize, uint32_t Direction)
Initializes DMA channel used by the I2C EEPROM driver.
void | sEE_LowLevel_Init (void)
Initializes peripherals used by the I2C EEPROM driver.
void | STM_EVAL_COMInit (COM_TypeDef COM, USART_InitTypeDef *USART_InitStruct)
Configures COM port.
void | STM_EVAL_LEDInit (Led_TypeDef Led)
Configures LED GPIO.
void | STM_EVAL_LEDOff (Led_TypeDef Led)
Turns selected LED Off.
void | STM_EVAL_LEDOn (Led_TypeDef Led)
Turns selected LED On.
void | STM_EVAL_LEDToggle (Led_TypeDef Led)
Toggles the selected LED.
uint32_t | STM_EVAL_PBGetState (Button_TypeDef Button)
Returns the selected Button state.
void | STM_EVAL_PBInit (Button_TypeDef Button, ButtonMode_TypeDef Button_Mode)
Configures Button GPIO and EXTI Line.

Function Documentation

void LM75_LowLevel_DeInit ( void )

DeInitializes the LM75_I2C.

Parameters:
None
Return values:
None

< Disable LM75_I2C

< DeInitializes the LM75_I2C

< LM75_I2C Periph clock disable

< Configure LM75_I2C pins: SCL

< Configure LM75_I2C pins: SDA

< Configure LM75_I2C pin: SMBUS ALERT

< Disable LM75_I2C

< DeInitializes the LM75_I2C

< LM75_I2C Periph clock disable

< Configure LM75_I2C pins: SCL

< Configure LM75_I2C pins: SDA

< Configure LM75_I2C pin: SMBUS ALERT

< Disable LM75_I2C

< DeInitializes the LM75_I2C

< LM75_I2C Periph clock disable

< Configure LM75_I2C pins: SCL

< Configure LM75_I2C pins: SDA

< Configure LM75_I2C pin: SMBUS ALERT

< Disable LM75_I2C

< DeInitializes the LM75_I2C

< LM75_I2C Periph clock disable

< Configure LM75_I2C pins: SCL

< Configure LM75_I2C pins: SDA

< Configure LM75_I2C pin: SMBUS ALERT

< Disable LM75_I2C

< DeInitializes the LM75_I2C

< LM75_I2C Periph clock disable

< Configure LM75_I2C pins: SCL

< Configure LM75_I2C pins: SDA

< Configure LM75_I2C pin: SMBUS ALERT

Definition at line 544 of file stm32100b_eval.c.

References DISABLE, GPIO_Init(), GPIO_InitStructure, GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_IN_FLOATING, GPIO_InitTypeDef::GPIO_Pin, I2C_Cmd(), I2C_DeInit(), LM75_I2C, LM75_I2C_CLK, LM75_I2C_SCL_GPIO_PORT, LM75_I2C_SCL_PIN, LM75_I2C_SDA_GPIO_PORT, LM75_I2C_SDA_PIN, LM75_I2C_SMBUSALERT_GPIO_PORT, LM75_I2C_SMBUSALERT_PIN, and RCC_APB1PeriphClockCmd().

Referenced by LM75_DeInit().

void LM75_LowLevel_Init ( void )

Initializes the LM75_I2C.

Parameters:
None
Return values:
None
Parameters:
None
Return values:
None

< LM75_I2C Periph clock enable

< LM75_I2C_SCL_GPIO_CLK, LM75_I2C_SDA_GPIO_CLK and LM75_I2C_SMBUSALERT_GPIO_CLK Periph clock enable

< Configure LM75_I2C pins: SCL

< Configure LM75_I2C pins: SDA

< Configure LM75_I2C pin: SMBUS ALERT

< LM75_I2C Periph clock enable

< LM75_I2C_SCL_GPIO_CLK, LM75_I2C_SDA_GPIO_CLK and LM75_I2C_SMBUSALERT_GPIO_CLK Periph clock enable

< Configure LM75_I2C pins: SCL

< Configure LM75_I2C pins: SDA

< Configure LM75_I2C pin: SMBUS ALERT

< LM75_I2C Periph clock enable

< LM75_I2C_SCL_GPIO_CLK, LM75_I2C_SDA_GPIO_CLK and LM75_I2C_SMBUSALERT_GPIO_CLK Periph clock enable

< Configure LM75_I2C pins: SCL

< Configure LM75_I2C pins: SDA

< Configure LM75_I2C pin: SMBUS ALERT

< LM75_I2C Periph clock enable

< LM75_I2C_SCL_GPIO_CLK, LM75_I2C_SDA_GPIO_CLK and LM75_I2C_SMBUSALERT_GPIO_CLK Periph clock enable

< Configure LM75_I2C pins: SCL

< Configure LM75_I2C pins: SDA

< Configure LM75_I2C pin: SMBUS ALERT

< LM75_I2C Periph clock enable

< LM75_I2C_SCL_GPIO_CLK, LM75_I2C_SDA_GPIO_CLK and LM75_I2C_SMBUSALERT_GPIO_CLK Periph clock enable

< Configure LM75_I2C pins: SCL

< Configure LM75_I2C pins: SDA

< Configure LM75_I2C pin: SMBUS ALERT

Definition at line 575 of file stm32100b_eval.c.

References ENABLE, GPIO_Init(), GPIO_InitStructure, GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_AF_OD, GPIO_Mode_IPU, GPIO_InitTypeDef::GPIO_Pin, GPIO_InitTypeDef::GPIO_Speed, GPIO_Speed_50MHz, LM75_I2C_CLK, LM75_I2C_SCL_AF, LM75_I2C_SCL_GPIO_CLK, LM75_I2C_SCL_GPIO_PORT, LM75_I2C_SCL_PIN, LM75_I2C_SCL_SOURCE, LM75_I2C_SDA_AF, LM75_I2C_SDA_GPIO_CLK, LM75_I2C_SDA_GPIO_PORT, LM75_I2C_SDA_PIN, LM75_I2C_SDA_SOURCE, LM75_I2C_SMBUSALERT_AF, LM75_I2C_SMBUSALERT_GPIO_CLK, LM75_I2C_SMBUSALERT_GPIO_PORT, LM75_I2C_SMBUSALERT_PIN, LM75_I2C_SMBUSALERT_SOURCE, RCC_AHBPeriphClockCmd(), RCC_APB1PeriphClockCmd(), and RCC_APB2PeriphClockCmd().

Referenced by LM75_Init().

void SD_LowLevel_DeInit ( void )

DeInitializes the SD/SD communication.

Parameters:
None
Return values:
None DeInitializes the SD/SD communication.
Parameters:
None
Return values:
None

< SD_SPI disable

< DeInitializes the SD_SPI

< SD_SPI Periph clock disable

< Configure SD_SPI pins: SCK

< Configure SD_SPI pins: MISO

< Configure SD_SPI pins: MOSI

< Configure SD_SPI_CS_PIN pin: SD Card CS pin

< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin

< SD_SPI disable

< DeInitializes the SD_SPI

< SD_SPI Periph clock disable

< Configure SD_SPI pins: SCK

< Configure SD_SPI pins: MISO

< Configure SD_SPI pins: MOSI

< Configure SD_SPI_CS_PIN pin: SD Card CS pin

< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin

< SD_SPI disable

< DeInitializes the SD_SPI

< SD_SPI Periph clock disable

< Configure SD_SPI pins: SCK

< Configure SD_SPI pins: MISO

< Configure SD_SPI pins: MOSI

< Configure SD_SPI_CS_PIN pin: SD Card CS pin

< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin

< SD_SPI disable

< DeInitializes the SD_SPI

< SD_SPI Periph clock disable

< DeRemap SPI3 Pins

< Configure SD_SPI pins: SCK

< Configure SD_SPI pins: MISO

< Configure SD_SPI pins: MOSI

< Configure SD_SPI_CS_PIN pin: SD Card CS pin

< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin

< Disable SDIO Clock

< Set Power State to OFF

< DeInitializes the SDIO peripheral

< Disable the SDIO AHB Clock

< Configure PC.08, PC.09, PC.10, PC.11, PC.12 pin: D0, D1, D2, D3, CLK pin

< Configure PD.02 CMD line

< SD_SPI disable

< DeInitializes the SD_SPI

< SD_SPI Periph clock disable

< Configure SD_SPI pins: SCK

< Configure SD_SPI pins: MISO

< Configure SD_SPI pins: MOSI

< Configure SD_SPI_CS_PIN pin: SD Card CS pin

< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin

Definition at line 373 of file stm32100b_eval.c.

References DISABLE, GPIO_Init(), GPIO_InitStructure, GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_IN_FLOATING, GPIO_InitTypeDef::GPIO_Pin, GPIO_Pin_10, GPIO_Pin_11, GPIO_Pin_12, GPIO_Pin_2, GPIO_Pin_8, GPIO_Pin_9, GPIO_PinRemapConfig(), GPIO_Remap_SPI3, GPIOC, GPIOD, RCC_AHBPeriph_SDIO, RCC_AHBPeriphClockCmd(), RCC_APB1PeriphClockCmd(), RCC_APB2PeriphClockCmd(), SD_CS_GPIO_PORT, SD_CS_PIN, SD_DETECT_GPIO_PORT, SD_DETECT_PIN, SD_SPI, SD_SPI_CLK, SD_SPI_MISO_GPIO_PORT, SD_SPI_MISO_PIN, SD_SPI_MOSI_GPIO_PORT, SD_SPI_MOSI_PIN, SD_SPI_SCK_GPIO_PORT, SD_SPI_SCK_PIN, SDIO_ClockCmd(), SDIO_DeInit(), SDIO_PowerState_OFF, SDIO_SetPowerState(), SPI_Cmd(), and SPI_I2S_DeInit().

Referenced by SD_DeInit().

void SD_LowLevel_Init ( void )

Initializes the SD_SPI and CS pins.

Parameters:
None
Return values:
None Initializes the SD_SPI and CS pins.
Parameters:
None
Return values:
None

< SD_SPI_CS_GPIO, SD_SPI_MOSI_GPIO, SD_SPI_MISO_GPIO, SD_SPI_DETECT_GPIO and SD_SPI_SCK_GPIO Periph clock enable

< SD_SPI Periph clock enable

< Configure SD_SPI pins: SCK

< Configure SD_SPI pins: MOSI

< Configure SD_SPI pins: MISO

< Configure SD_SPI_CS_PIN pin: SD Card CS pin

< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin

< SD_SPI Config

< SD_SPI enable

< SD_SPI_CS_GPIO, SD_SPI_MOSI_GPIO, SD_SPI_MISO_GPIO, SD_SPI_DETECT_GPIO and SD_SPI_SCK_GPIO Periph clock enable

< SD_SPI Periph clock enable

< Configure SD_SPI pins: SCK

< Configure SD_SPI pins: MOSI

< Configure SD_SPI pins: MISO

< Configure SD_SPI_CS_PIN pin: SD Card CS pin

< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin

< SD_SPI Config

< SD_SPI enable

< SD_SPI_CS_GPIO, SD_SPI_MOSI_GPIO, SD_SPI_MISO_GPIO, SD_SPI_DETECT_GPIO and SD_SPI_SCK_GPIO Periph clock enable

< SD_SPI Periph clock enable

< Configure SD_SPI pins: SCK

< Configure SD_SPI pins: MOSI

< Configure SD_SPI pins: MISO

< Configure SD_SPI_CS_PIN pin: SD Card CS pin

< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin

< SD_SPI Config

< SD_SPI enable

< SD_SPI_CS_GPIO, SD_SPI_MOSI_GPIO, SD_SPI_MISO_GPIO, SD_SPI_DETECT_GPIO and SD_SPI_SCK_GPIO Periph clock enable

< SD_SPI Periph clock enable

< AFIO Periph clock enable

< Remap SPI3 Pins

< Configure SD_SPI pins: SCK

< Configure SD_SPI pins: MOSI

< Configure SD_SPI pins: MISO

< Configure SD_SPI_CS_PIN pin: SD Card CS pin

< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin

< SD_SPI Config

< SD_SPI enable

< GPIOC and GPIOD Periph clock enable

< Configure PC.08, PC.09, PC.10, PC.11, PC.12 pin: D0, D1, D2, D3, CLK pin

< Configure PD.02 CMD line

< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin

< Enable the SDIO AHB Clock

< Enable the DMA2 Clock

< SD_SPI_CS_GPIO, SD_SPI_MOSI_GPIO, SD_SPI_MISO_GPIO, SD_SPI_DETECT_GPIO and SD_SPI_SCK_GPIO Periph clock enable

< SD_SPI Periph clock enable

< Configure SD_SPI pins: SCK

< Configure SD_SPI pins: MISO

< Configure SD_SPI pins: MOSI

< Configure SD_SPI_CS_PIN pin: SD Card CS pin

< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin

< SD_SPI Config

< SD_SPI enable

Definition at line 410 of file stm32100b_eval.c.

References ENABLE, GPIO_Init(), GPIO_InitStructure, GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_AF_PP, GPIO_Mode_IN_FLOATING, GPIO_Mode_IPU, GPIO_Mode_Out_PP, GPIO_InitTypeDef::GPIO_Pin, GPIO_Pin_10, GPIO_Pin_11, GPIO_Pin_12, GPIO_Pin_2, GPIO_Pin_8, GPIO_Pin_9, GPIO_PinRemapConfig(), GPIO_Remap_SPI3, GPIO_InitTypeDef::GPIO_Speed, GPIO_Speed_50MHz, GPIOC, GPIOD, RCC_AHBPeriph_DMA2, RCC_AHBPeriph_SDIO, RCC_AHBPeriphClockCmd(), RCC_APB1PeriphClockCmd(), RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2PeriphClockCmd(), SD_CS_GPIO_CLK, SD_CS_GPIO_PORT, SD_CS_PIN, SD_DETECT_GPIO_CLK, SD_DETECT_GPIO_PORT, SD_DETECT_PIN, SD_SPI, SD_SPI_CLK, SD_SPI_MISO_AF, SD_SPI_MISO_GPIO_CLK, SD_SPI_MISO_GPIO_PORT, SD_SPI_MISO_PIN, SD_SPI_MISO_SOURCE, SD_SPI_MOSI_AF, SD_SPI_MOSI_GPIO_CLK, SD_SPI_MOSI_GPIO_PORT, SD_SPI_MOSI_PIN, SD_SPI_MOSI_SOURCE, SD_SPI_SCK_AF, SD_SPI_SCK_GPIO_CLK, SD_SPI_SCK_GPIO_PORT, SD_SPI_SCK_PIN, SD_SPI_SCK_SOURCE, SPI_InitTypeDef::SPI_BaudRatePrescaler, SPI_BaudRatePrescaler_2, SPI_BaudRatePrescaler_4, SPI_Cmd(), SPI_InitTypeDef::SPI_CPHA, SPI_CPHA_2Edge, SPI_InitTypeDef::SPI_CPOL, SPI_CPOL_High, SPI_InitTypeDef::SPI_CRCPolynomial, SPI_InitTypeDef::SPI_DataSize, SPI_DataSize_8b, SPI_InitTypeDef::SPI_Direction, SPI_Direction_2Lines_FullDuplex, SPI_InitTypeDef::SPI_FirstBit, SPI_FirstBit_MSB, SPI_Init(), SPI_InitStructure, SPI_InitTypeDef::SPI_Mode, SPI_Mode_Master, SPI_InitTypeDef::SPI_NSS, and SPI_NSS_Soft.

Referenced by SD_Init().

void sEE_LowLevel_DeInit ( void )

DeInitializes peripherals used by the I2C EEPROM driver.

Parameters:
None
Return values:
None

< sEE_I2C Periph clock disable

< GPIO configuration

< Configure sEE_I2C pins: SCL

< Configure sEE_I2C pins: SDA

< sEE_I2C Periph clock disable

< GPIO configuration

< Configure sEE_I2C pins: SCL

< Configure sEE_I2C pins: SDA

< sEE_I2C Periph clock disable

< GPIO configuration

< Configure sEE_I2C pins: SCL

< Configure sEE_I2C pins: SDA

Definition at line 466 of file stm32100e_eval.c.

References DISABLE, DMA_Cmd(), DMA_DeInit(), GPIO_Init(), GPIO_InitStructure, GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_IN_FLOATING, GPIO_InitTypeDef::GPIO_Pin, I2C_Cmd(), I2C_DeInit(), NVIC_Init(), NVIC_InitStructure, NVIC_InitTypeDef::NVIC_IRQChannel, NVIC_InitTypeDef::NVIC_IRQChannelCmd, NVIC_InitTypeDef::NVIC_IRQChannelPreemptionPriority, NVIC_InitTypeDef::NVIC_IRQChannelSubPriority, RCC_APB1PeriphClockCmd(), sEE_I2C, sEE_I2C_CLK, sEE_I2C_DMA_CHANNEL_RX, sEE_I2C_DMA_CHANNEL_TX, sEE_I2C_DMA_PREPRIO, sEE_I2C_DMA_RX_IRQn, sEE_I2C_DMA_SUBPRIO, sEE_I2C_DMA_TX_IRQn, sEE_I2C_SCL_GPIO_PORT, sEE_I2C_SCL_PIN, sEE_I2C_SDA_GPIO_PORT, and sEE_I2C_SDA_PIN.

Referenced by sEE_DeInit().

void sEE_LowLevel_DMAConfig | ( | uint32_t | pBuffer,
 |  | uint32_t | BufferSize,
 |  | uint32_t | Direction
 | ) |  |

Initializes DMA channel used by the I2C EEPROM driver.

Parameters:
None
Return values:
None

Definition at line 583 of file stm32100e_eval.c.

References DMA_InitTypeDef::DMA_BufferSize, DMA_InitTypeDef::DMA_DIR, DMA_DIR_PeripheralDST, DMA_DIR_PeripheralSRC, DMA_Init(), DMA_InitTypeDef::DMA_MemoryBaseAddr, sEE_DIRECTION_TX, sEE_I2C_DMA_CHANNEL_RX, and sEE_I2C_DMA_CHANNEL_TX.

Referenced by sEE_ReadBuffer(), and sEE_WritePage().

void sEE_LowLevel_Init ( void )

Initializes peripherals used by the I2C EEPROM driver.

Parameters:
None
Return values:
None

< sEE_I2C_SCL_GPIO_CLK and sEE_I2C_SDA_GPIO_CLK Periph clock enable

< sEE_I2C Periph clock enable

< GPIO configuration

< Configure sEE_I2C pins: SCL

< Configure sEE_I2C pins: SDA

< I2C DMA TX and RX channels configuration

< sEE_I2C_SCL_GPIO_CLK and sEE_I2C_SDA_GPIO_CLK Periph clock enable

< sEE_I2C Periph clock enable

< GPIO configuration

< Configure sEE_I2C pins: SCL

< Configure sEE_I2C pins: SDA

< I2C DMA TX and RX channels configuration

< sEE_I2C Periph clock enable

< sEE_I2C_SCL_GPIO_CLK and sEE_I2C_SDA_GPIO_CLK Periph clock enable

< GPIO configuration

< Configure sEE_I2C pins: SCL

< Configure sEE_I2C pins: SDA

< I2C DMA TX and RX channels configuration

Definition at line 515 of file stm32100e_eval.c.

References DISABLE, DMA_InitTypeDef::DMA_BufferSize, DMA_DeInit(), DMA_InitTypeDef::DMA_DIR, DMA_DIR_PeripheralDST, DMA_Init(), DMA_IT_TC, DMA_ITConfig(), DMA_InitTypeDef::DMA_M2M, DMA_M2M_Disable, DMA_InitTypeDef::DMA_MemoryBaseAddr, DMA_InitTypeDef::DMA_MemoryDataSize, DMA_MemoryDataSize_Byte, DMA_InitTypeDef::DMA_MemoryInc, DMA_MemoryInc_Enable, DMA_InitTypeDef::DMA_Mode, DMA_Mode_Normal, DMA_InitTypeDef::DMA_PeripheralBaseAddr, DMA_InitTypeDef::DMA_PeripheralDataSize, DMA_InitTypeDef::DMA_PeripheralInc, DMA_PeripheralInc_Disable, DMA_InitTypeDef::DMA_Priority, DMA_Priority_VeryHigh, ENABLE, GPIO_Init(), GPIO_InitStructure, GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_AF_OD, GPIO_InitTypeDef::GPIO_Pin, GPIO_InitTypeDef::GPIO_Speed, GPIO_Speed_50MHz, NVIC_Init(), NVIC_InitStructure, NVIC_InitTypeDef::NVIC_IRQChannel, NVIC_InitTypeDef::NVIC_IRQChannelCmd, NVIC_InitTypeDef::NVIC_IRQChannelPreemptionPriority, NVIC_InitTypeDef::NVIC_IRQChannelSubPriority, RCC_AHBPeriphClockCmd(), RCC_APB1PeriphClockCmd(), RCC_APB1PeriphResetCmd(), RCC_APB2PeriphClockCmd(), sEE_I2C_CLK, sEE_I2C_DMA_CHANNEL_RX, sEE_I2C_DMA_CHANNEL_TX, sEE_I2C_DMA_CLK, sEE_I2C_DMA_PREPRIO, sEE_I2C_DMA_RX_IRQn, sEE_I2C_DMA_SUBPRIO, sEE_I2C_DMA_TX_IRQn, sEE_I2C_DR_Address, sEE_I2C_SCL_AF, sEE_I2C_SCL_GPIO_CLK, sEE_I2C_SCL_GPIO_PORT, sEE_I2C_SCL_PIN, sEE_I2C_SCL_SOURCE, sEE_I2C_SDA_AF, sEE_I2C_SDA_GPIO_CLK, sEE_I2C_SDA_GPIO_PORT, sEE_I2C_SDA_PIN, and sEE_I2C_SDA_SOURCE.

Referenced by sEE_Init().

void STM_EVAL_COMInit | ( | COM_TypeDef | COM,
 |  | USART_InitTypeDef * | USART_InitStruct
 | ) |  |

Configures COM port.

Parameters:
COM,: Specifies the COM port to be configured. This parameter can be one of following parameters:

  • COM1
  • COM2
USART_InitStruct,: pointer to a USART_InitTypeDef structure that contains the configuration information for the specified USART peripheral.
Return values:
None

Definition at line 330 of file stm32100b_eval.c.

References COM1, COM_RX_AF, COM_RX_PIN, COM_RX_PIN_SOURCE, COM_RX_PORT_CLK, COM_TX_AF, COM_TX_PIN, COM_TX_PIN_SOURCE, COM_TX_PORT_CLK, COM_USART_CLK, ENABLE, GPIO_Init(), GPIO_InitStructure, GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_AF_PP, GPIO_Mode_IN_FLOATING, GPIO_InitTypeDef::GPIO_Pin, GPIO_PinRemapConfig(), GPIO_Remap_USART2, GPIO_InitTypeDef::GPIO_Speed, GPIO_Speed_50MHz, RCC_AHBPeriphClockCmd(), RCC_APB1PeriphClockCmd(), RCC_APB2Periph_AFIO, RCC_APB2PeriphClockCmd(), USART_Cmd(), and USART_Init().

Referenced by main().

void STM_EVAL_LEDInit ( Led_TypeDef Led )

Configures LED GPIO.

Parameters:
Led,: Specifies the Led to be configured. This parameter can be one of following parameters:

  • LED1
  • LED2
  • LED3
  • LED4
Return values:
None

Definition at line 176 of file stm32100b_eval.c.

References ENABLE, GPIO_CLK, GPIO_Init(), GPIO_InitStructure, GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_Out_PP, GPIO_PIN, GPIO_InitTypeDef::GPIO_Pin, GPIO_InitTypeDef::GPIO_Speed, GPIO_Speed_50MHz, RCC_AHBPeriphClockCmd(), and RCC_APB2PeriphClockCmd().

Referenced by main().

void STM_EVAL_LEDOff ( Led_TypeDef Led )

Turns selected LED Off.

Parameters:
Led,: Specifies the Led to be set off. This parameter can be one of following parameters:

  • LED1
  • LED2
  • LED3
  • LED4
Return values:
None

Definition at line 216 of file stm32100b_eval.c.

References GPIO_TypeDef::BRR, and GPIO_PIN.

Referenced by ADC1_2_IRQHandler(), EXTI15_10_IRQHandler(), LED_Display(), main(), SD_EraseTest(), SD_MultiBlockTest(), and SD_SingleBlockTest().

void STM_EVAL_LEDOn ( Led_TypeDef Led )

Turns selected LED On.

Parameters:
Led,: Specifies the Led to be set on. This parameter can be one of following parameters:

  • LED1
  • LED2
  • LED3
  • LED4
Return values:
None

Definition at line 201 of file stm32100b_eval.c.

References GPIO_TypeDef::BSRR, and GPIO_PIN.

Referenced by ADC1_2_IRQHandler(), CEC_IRQHandler(), EXTI15_10_IRQHandler(), EXTI9_5_IRQHandler(), LED_Display(), main(), MemManage_Handler(), RTC_Configuration(), SD_EraseTest(), SD_MultiBlockTest(), SD_SingleBlockTest(), and TAMPER_IRQHandler().

void STM_EVAL_LEDToggle ( Led_TypeDef Led )

Toggles the selected LED.

Parameters:
Led,: Specifies the Led to be toggled. This parameter can be one of following parameters:

  • LED1
  • LED2
  • LED3
  • LED4
Return values:
None

Definition at line 231 of file stm32100b_eval.c.

References GPIO_PIN, and GPIO_TypeDef::ODR.

Referenced by DMA1_Channel5_IRQHandler(), DMA1_Channel6_IRQHandler(), EXTI0_IRQHandler(), EXTI9_5_IRQHandler(), main(), PVD_IRQHandler(), RTC_IRQHandler(), RTCAlarm_IRQHandler(), SysTick_Handler(), TIM2_IRQHandler(), TIM3_IRQHandler(), and TIM4_IRQHandler().

uint32_t STM_EVAL_PBGetState ( Button_TypeDef Button )

Returns the selected Button state.

Parameters:
Button,: Specifies the Button to be checked. This parameter can be one of following parameters:

  • BUTTON_WAKEUP: Wakeup Push Button
  • BUTTON_TAMPER: Tamper Push Button
  • BUTTON_KEY: Key Push Button
  • BUTTON_RIGHT: Joystick Right Push Button
  • BUTTON_LEFT: Joystick Left Push Button
  • BUTTON_UP: Joystick Up Push Button
  • BUTTON_DOWN: Joystick Down Push Button
  • BUTTON_SEL: Joystick Sel Push Button
Return values:
The Button GPIO pin value.
Parameters:
Button,: Specifies the Button to be checked. This parameter can be one of following parameters:

  • BUTTON_KEY: Key Push Button
  • BUTTON_RIGHT: Joystick Right Push Button
  • BUTTON_LEFT: Joystick Left Push Button
  • BUTTON_UP: Joystick Up Push Button
  • BUTTON_DOWN: Joystick Down Push Button
  • BUTTON_SEL: Joystick Sel Push Button
Return values:
- When Button > 1, the Button GPIO pin value is returned.

  • When Button = 0 or 1, error code (0xFF) is returned.

Definition at line 314 of file stm32100b_eval.c.

References BUTTON_PIN, and GPIO_ReadInputDataBit().

Referenced by main(), and ReadKey().

void STM_EVAL_PBInit | ( | Button_TypeDef | Button,
 |  | ButtonMode_TypeDef | Button_Mode
 | ) |  |

Configures Button GPIO and EXTI Line.

Parameters:
Button,: Specifies the Button to be configured. This parameter can be one of following parameters:

  • BUTTON_WAKEUP: Wakeup Push Button
  • BUTTON_TAMPER: Tamper Push Button
  • BUTTON_KEY: Key Push Button
  • BUTTON_RIGHT: Joystick Right Push Button
  • BUTTON_LEFT: Joystick Left Push Button
  • BUTTON_UP: Joystick Up Push Button
  • BUTTON_DOWN: Joystick Down Push Button
  • BUTTON_SEL: Joystick Sel Push Button
Button_Mode,: Specifies Button mode. This parameter can be one of following parameters:

  • BUTTON_MODE_GPIO: Button will be used as simple IO
  • BUTTON_MODE_EXTI: Button will be connected to EXTI line with interrupt generation capability
Return values:
None
Parameters:
Button,: Specifies the Button to be configured. This parameter can be one of following parameters:

  • BUTTON_KEY: Key Push Button
  • BUTTON_RIGHT: Joystick Right Push Button
  • BUTTON_LEFT: Joystick Left Push Button
  • BUTTON_UP: Joystick Up Push Button
  • BUTTON_DOWN: Joystick Down Push Button
  • BUTTON_SEL: Joystick Sel Push Button
Button_Mode,: Specifies Button mode. This parameter can be one of following parameters:

  • BUTTON_MODE_GPIO: Button will be used as simple IO
  • BUTTON_MODE_EXTI: Button will be connected to EXTI line with interrupt generation capability
Return values:
None

Definition at line 255 of file stm32100b_eval.c.

References BUTTON_CLK, BUTTON_EXTI_LINE, BUTTON_IRQn, BUTTON_KEY, BUTTON_MODE_EXTI, BUTTON_PIN, BUTTON_PIN_SOURCE, BUTTON_PORT_SOURCE, BUTTON_WAKEUP, ENABLE, EXTI_Init(), EXTI_InitStructure, EXTI_InitTypeDef::EXTI_Line, EXTI_InitTypeDef::EXTI_LineCmd, EXTI_InitTypeDef::EXTI_Mode, EXTI_Mode_Interrupt, EXTI_InitTypeDef::EXTI_Trigger, EXTI_Trigger_Falling, EXTI_Trigger_Rising, GPIO_EXTILineConfig(), GPIO_Init(), GPIO_InitStructure, GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_IN_FLOATING, GPIO_InitTypeDef::GPIO_Pin, NVIC_Init(), NVIC_InitStructure, NVIC_InitTypeDef::NVIC_IRQChannel, NVIC_InitTypeDef::NVIC_IRQChannelCmd, NVIC_InitTypeDef::NVIC_IRQChannelPreemptionPriority, NVIC_InitTypeDef::NVIC_IRQChannelSubPriority, RCC_AHBPeriphClockCmd(), RCC_APB2Periph_AFIO, and RCC_APB2PeriphClockCmd().

Referenced by main().


STM32F10x Standard Peripherals Firmware Library: STM32L152_EVAL_GLASS_LCD_Private_Types

STM32L152_EVAL_GLASS_LCD_Private_Types

STM32L152_EVAL_GLASS_LCD


STM32F10x Standard Peripherals Firmware Library: STM32L152_EVAL_GLASS_LCD_Private_Defines

STM32L152_EVAL_GLASS_LCD_Private_Defines

STM32L152_EVAL_GLASS_LCD


STM32F10x Standard Peripherals Firmware Library: STM32L152_EVAL_GLASS_LCD_Private_Macros

STM32L152_EVAL_GLASS_LCD_Private_Macros

STM32L152_EVAL_GLASS_LCD


STM32F10x Standard Peripherals Firmware Library: STM32L152_EVAL_GLASS_LCD_Private_Variables

Variables

STM32L152_EVAL_GLASS_LCD_Private_Variables

STM32L152_EVAL_GLASS_LCD

Variables

uint8_t | digit [4]
LETTERS AND NUMBERS MAPPING DEFINITION.
__I uint16_t | LetterMap [26]
__I uint16_t | mask [4] = {0xF000, 0x0F00, 0x00F0, 0x000F}
__I uint16_t | NumberMap [10]
__I uint8_t | shift [4] = {0x0C, 0x08, 0x04, 0x00}

Variable Documentation

uint8_t digit[4]

LETTERS AND NUMBERS MAPPING DEFINITION.

================================================================================
                              GLASS LCD MAPPING
================================================================================
               A
      --  ----------
    X \/  |\   |I  /|
         F| H  |  J |B
          |  \ | /  |
          --G-- --K--
          |   /| \  |
        E |  L |  N |C
          | /  |M  \|   _
          -----------  | |DP
              D         -

A LCD character coding is based on the following matrix:

{ X , F , E , D  }
{ I , J , K , N  }
{ A , B , C , DP }
{ H , G , L , M  }

The character A for example is:
-------------------------------
 { 0 , 1 , 1 , 0 }
 { 0 , 0 , 1 , 0 }
 { 1 , 1 , 1 , 0 }
 { 0 , 1 , 0 , 0 }
-------------------
=  4   D   7   0   hex

=> 'A' = 0x4D70

Definition at line 114 of file stm32l152_eval_glass_lcd.c.

Referenced by Convert(), and LCD_GLASS_WriteChar().

__I uint16_t LetterMap[26]
Initial value:
{

0x4D70, 0x6469, 0x4111, 0x6449, 0x4911, 0x4910, 0x4171, 0x0D70, 0x6009,

0x0451, 0x0B12, 0x0111, 0x8750, 0x8552, 0x4551, 0x4D30, 0x4553, 0x4D32,

0x4961, 0x6008, 0x0551, 0x0390, 0x05D2, 0x8282, 0x8208, 0x4281
}

Definition at line 119 of file stm32l152_eval_glass_lcd.c.

Referenced by Convert().

__I uint16_t mask[4] = {0xF000, 0x0F00, 0x00F0, 0x000F}

Definition at line 115 of file stm32l152_eval_glass_lcd.c.

Referenced by Convert().

__I uint16_t NumberMap[10]
Initial value:

{

0x47D1, 0x0640, 0x4C31, 0x4C61, 0x0D60, 0x4961, 0x4971, 0x4440, 0x4D71, 0x4D61
}

Definition at line 129 of file stm32l152_eval_glass_lcd.c.

Referenced by Convert().

__I uint8_t shift[4] = {0x0C, 0x08, 0x04, 0x00}

Definition at line 116 of file stm32l152_eval_glass_lcd.c.

Referenced by Convert().


STM32F10x Standard Peripherals Firmware Library: STM32L152_EVAL_LCD_Private_Function_Prototypes

STM32L152_EVAL_LCD_Private_Function_Prototypes

STM32L152_EVAL_GLASS_LCD | STM32L152_EVAL_LCD


STM32F10x Standard Peripherals Firmware Library: STM32L152_EVAL_LCD_Private_Functions

Functions

STM32L152_EVAL_LCD_Private_Functions

STM32L152_EVAL_GLASS_LCD | STM32L152_EVAL_LCD

Functions

static void | Convert (uint8_t *c, Point_Typedef point, Apostrophe_Typedef apostrophe)
Converts an ascii char to an LCD digit.
static void | delay (__IO uint32_t nCount)
Inserts a delay time.
void | LCD_Clear (uint16_t Color)
Clears the hole LCD.
void | LCD_ClearLine (uint8_t Line)
Clears the selected line.
void | LCD_ClosedPolyLine (pPoint Points, uint16_t PointCount)
Displays a closed polyline (between many points).
void | LCD_ClosedPolyLineRelative (pPoint Points, uint16_t PointCount)
Displays a closed relative polyline (between many points).
void | LCD_CtrlLinesConfig (void)
Configures LCD control lines in Output Push-Pull mode.
void | LCD_CtrlLinesWrite (GPIO_TypeDef *GPIOx, uint16_t CtrlPins, BitAction BitVal)
Sets or reset LCD control lines.
void | LCD_DisplayChar (uint8_t Line, uint16_t Column, uint8_t Ascii)
Displays one character (16dots width, 24dots height).
void | LCD_DisplayOff (void)
Disables the Display.
void | LCD_DisplayOn (void)
Enables the Display.
void | LCD_DisplayStringLine (uint8_t Line, uint8_t *ptr)
Displays a maximum of 20 char on the LCD.
void | LCD_DrawChar (uint8_t Xpos, uint16_t Ypos, const uint16_t *c)
Draws a character on LCD.
void | LCD_DrawCircle (uint8_t Xpos, uint16_t Ypos, uint16_t Radius)
Displays a circle.
void | LCD_DrawFullCircle (uint16_t Xpos, uint16_t Ypos, uint16_t Radius)
Displays a full circle.
void | LCD_DrawFullRect (uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height)
Displays a full rectangle.
void | LCD_DrawLine (uint8_t Xpos, uint16_t Ypos, uint16_t Length, uint8_t Direction)
Displays a line.
void | LCD_DrawMonoPict (const uint32_t *Pict)
Displays a monocolor picture.
void | LCD_DrawRect (uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width)
Displays a rectangle.
void | LCD_DrawUniLine (uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2)
Displays an uni line (between two points).
void | LCD_FillPolyLine (pPoint Points, uint16_t PointCount)
Displays a full polyline (between many points).
void | LCD_GetColors (__IO uint16_t *_TextColor, __IO uint16_t *_BackColor)
Gets the LCD Text and Background colors.
sFONT * | LCD_GetFont (void)
Gets the Text Font.
void | LCD_GLASS_Clear (void)
This function Clear the whole LCD RAM.
void | LCD_GLASS_ClearChar (uint8_t position)
This function Clear a char in the LCD RAM.
void | LCD_GLASS_DisplayChar (uint8_t *ch, Point_Typedef point, Apostrophe_Typedef apostrophe, uint8_t position)
This function writes a char in the LCD RAM.
void | LCD_GLASS_DisplayString (uint8_t *ptr)
This function writes a char in the LCD RAM.
void | LCD_GLASS_Init (void)
Configures the LCD GLASS relative GPIO port IOs and LCD peripheral.
void | LCD_GLASS_ScrollString (uint8_t *ptr, uint16_t nScroll, uint16_t ScrollSpeed)
Display a string in scrolling mode.
void | LCD_GLASS_WriteChar (uint8_t *ch, Point_Typedef point, Apostrophe_Typedef apostrophe, uint8_t position)
This function writes a char in the LCD RAM.
static void | LCD_GPIOConfig (void)
Configures the LCD Segments and Coms GPIOs.
void | LCD_nCS_StartByte (uint8_t Start_Byte)
Reset LCD control line(/CS) and Send Start-Byte.
void | LCD_PolyLine (pPoint Points, uint16_t PointCount)
Displays an polyline (between many points).
void | LCD_PolyLineRelative (pPoint Points, uint16_t PointCount)
Displays a relative polyline (between many points).
static void | LCD_PolyLineRelativeClosed (pPoint Points, uint16_t PointCount, uint16_t Closed)
Displays an relative polyline (between many points).
void | LCD_PowerOn (void)
Power on the LCD.
uint16_t | LCD_ReadReg (uint8_t LCD_Reg)
Reads the selected LCD Register.
void | LCD_SetBackColor (__IO uint16_t Color)
Sets the Background color.
void | LCD_SetColors (__IO uint16_t _TextColor, __IO uint16_t _BackColor)
Sets the LCD Text and Background colors.
void | LCD_SetCursor (uint8_t Xpos, uint16_t Ypos)
Sets the cursor position.
void | LCD_SetDisplayWindow (uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width)
Sets a display window.
void | LCD_SetFont (sFONT *fonts)
Sets the Text Font.
void | LCD_SetTextColor (__IO uint16_t Color)
Sets the Text color.
void | LCD_Setup (void)
Setups the LCD.
void | LCD_SPIConfig (void)
Configures the LCD_SPI interface.
void | LCD_WindowModeDisable (void)
Disables LCD Window mode.
void | LCD_WriteRAM (uint16_t RGB_Code)
Writes to the LCD RAM.
void | LCD_WriteRAM_Prepare (void)
Prepare to write to the LCD RAM.
void | LCD_WriteRAMWord (uint16_t RGB_Code)
Writes 1 word to the LCD RAM.
void | LCD_WriteReg (uint8_t LCD_Reg, uint16_t LCD_RegValue)
Writes to the selected LCD ILI9320 register.
void | LCD_WriteRegIndex (uint8_t LCD_Reg)
Writes index to select the LCD register.
static void | PutPixel (int16_t x, int16_t y)
Displays a pixel.
void | STM32L152_LCD_DeInit (void)
DeInitializes the LCD.
void | STM32L152_LCD_Init (void)
Initializes the LCD.

Function Documentation

static void Convert | ( | uint8_t * | c,
 |  | Point_Typedef | point,
 |  | Apostrophe_Typedef | apostrophe
 | ) |  | [static]

Converts an ascii char to an LCD digit.

Parameters:
c,: Char to display.
point,: A point to add in front of char. This parameter can be one of the following values:

  • POINT_OFF : No point to add in front of char.
  • POINT_ON : Add a point in front of char.
apostrophe,: Flag indicating if a apostrophe has to be add in front of displayed character. This parameter can be one of the following values:

  • APOSTROPHE_OFF : No apostrophe to add in back of char.
  • APOSTROPHE_ON : Add an apostrophe in back of char.
Return values:
None

< The character c is a letter in upper case

Definition at line 627 of file stm32l152_eval_glass_lcd.c.

References APOSTROPHE_ON, digit, LetterMap, mask, NumberMap, POINT_ON, and shift.

Referenced by LCD_GLASS_WriteChar().

static void delay ( __IO uint32_t nCount ) [static]

Inserts a delay time.

Parameters:
nCount,: specifies the delay time length.
Return values:
None

Definition at line 1501 of file stm32l152_eval_lcd.c.

References index.

void LCD_Clear ( uint16_t Color )

Clears the hole LCD.

Parameters:
Color,: the color of the background.
Return values:
None

Definition at line 424 of file stm32l152_eval_lcd.c.

References Bit_SET, index, LCD_CtrlLinesWrite(), LCD_ILI9320, LCD_NCS_GPIO_PORT, LCD_NCS_PIN, LCD_SetCursor(), LCD_SPFD5408, LCD_WriteRAM(), LCD_WriteRAM_Prepare(), and LCDType.

void LCD_ClearLine ( uint8_t Line )

Clears the selected line.

Parameters:
Line,: the Line to be cleared. This parameter can be one of the following values:

  • Linex: where x can be 0..n
Return values:
None

Definition at line 404 of file stm32l152_eval_lcd.c.

References LCD_DisplayChar(), LCD_PIXEL_WIDTH, and _tFont::Width.

void LCD_ClosedPolyLine | ( | pPoint | Points,
 |  | uint16_t | PointCount
 | ) |  |

Displays a closed polyline (between many points).

Parameters:
Points,: pointer to the points array.
PointCount,: Number of points.
Return values:
None

Definition at line 1005 of file stm32l152_eval_lcd.c.

References LCD_DrawUniLine(), LCD_PolyLine(), Point::X, and Point::Y.

void LCD_ClosedPolyLineRelative | ( | pPoint | Points,
 |  | uint16_t | PointCount
 | ) |  |

Displays a closed relative polyline (between many points).

Parameters:
Points,: pointer to the points array.
PointCount,: Number of points.
Return values:
None

Definition at line 1028 of file stm32l152_eval_lcd.c.

References LCD_PolyLineRelativeClosed().

void LCD_CtrlLinesConfig ( void )

Configures LCD control lines in Output Push-Pull mode.

Parameters:
None
Return values:
None

Definition at line 1382 of file stm32l152_eval_lcd.c.

References Bit_SET, ENABLE, GPIO_Init(), GPIO_InitStructure, GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_Out_PP, GPIO_InitTypeDef::GPIO_Pin, GPIO_InitTypeDef::GPIO_Speed, GPIO_Speed_2MHz, GPIO_Speed_50MHz, LCD_CtrlLinesWrite(), LCD_NCS_GPIO_CLK, LCD_NCS_GPIO_PORT, LCD_NCS_PIN, LCD_NWR_GPIO_CLK, LCD_NWR_GPIO_PORT, LCD_NWR_PIN, LCD_RS_GPIO_CLK, LCD_RS_GPIO_PORT, LCD_RS_PIN, RCC_AHBPeriphClockCmd(), and RCC_APB2PeriphClockCmd().

void LCD_CtrlLinesWrite | ( | GPIO_TypeDef * | GPIOx,
 |  | uint16_t | CtrlPins,
 |  | BitAction | BitVal
 | ) |  |

Sets or reset LCD control lines.

Parameters:
GPIOx,: where x can be B or D to select the GPIO peripheral.
CtrlPins,: the Control line. This parameter can be:

  • LCD_NCS_PIN: Chip Select pin
  • LCD_NWR_PIN: Read/Write Selection pin
  • LCD_RS_PIN: Register/RAM Selection pin
BitVal,: specifies the value to be written to the selected bit. This parameter can be:

  • Bit_RESET: to clear the port pin
  • Bit_SET: to set the port pin
Return values:
None

Definition at line 1414 of file stm32l152_eval_lcd.c.

References GPIO_WriteBit().

void LCD_DisplayChar | ( | uint8_t | Line,
 |  | uint16_t | Column,
 |  | uint8_t | Ascii
 | ) |  |

Displays one character (16dots width, 24dots height).

Parameters:
Line,: the Line where to display the character shape . This parameter can be one of the following values:

  • Linex: where x can be 0..9
Column,: start column address.
Ascii,: character ascii code, must be between 0x20 and 0x7E.
Return values:
None

Definition at line 505 of file stm32l152_eval_lcd.c.

References _tFont::Height, LCD_DrawChar(), and _tFont::table.

void LCD_DisplayOff ( void )

Disables the Display.

Parameters:
None
Return values:
None

Definition at line 1370 of file stm32l152_eval_lcd.c.

References _delay_, LCD_HX8312, LCD_ILI9320, LCD_REG_0, LCD_REG_59, LCD_REG_7, LCD_SPFD5408, LCD_WriteReg(), and LCDType.

void LCD_DisplayOn ( void )

Enables the Display.

Parameters:
None
Return values:
None

Definition at line 1358 of file stm32l152_eval_lcd.c.

References _delay_, LCD_HX8312, LCD_ILI9320, LCD_REG_0, LCD_REG_1, LCD_REG_5, LCD_REG_59, LCD_REG_7, LCD_SPFD5408, LCD_WriteReg(), and LCDType.

void LCD_DisplayStringLine | ( | uint8_t | Line,
 |  | uint8_t * | ptr
 | ) |  |

Displays a maximum of 20 char on the LCD.

Parameters:
Line,: the Line where to display the character shape . This parameter can be one of the following values:

  • Linex: where x can be 0..9
*ptr,: pointer to string to display on LCD.
Return values:
None

Definition at line 520 of file stm32l152_eval_lcd.c.

References LCD_DisplayChar(), LCD_PIXEL_WIDTH, and _tFont::Width.

void LCD_DrawChar | ( | uint8_t | Xpos,
 |  | uint16_t | Ypos,
 |  | const uint16_t * | c
 | ) |  |

Draws a character on LCD.

Parameters:
Xpos,: the Line where to display the character shape.
Ypos,: start column address.
c,: pointer to the character data.
Return values:
None

Definition at line 462 of file stm32l152_eval_lcd.c.

References BackColor, Bit_SET, _tFont::Height, index, LCD_CtrlLinesWrite(), LCD_ILI9320, LCD_NCS_GPIO_PORT, LCD_NCS_PIN, LCD_SetCursor(), LCD_SPFD5408, LCD_WriteRAM(), LCD_WriteRAM_Prepare(), LCDType, TextColor, and _tFont::Width.

void LCD_DrawCircle | ( | uint8_t | Xpos,
 |  | uint16_t | Ypos,
 |  | uint16_t | Radius
 | ) |  |

Displays a circle.

Parameters:
Xpos,: specifies the X position.
Ypos,: specifies the Y position.
Radius
Return values:
None

Definition at line 647 of file stm32l152_eval_lcd.c.

References LCD_HX8312, LCD_ILI9320, LCD_SetCursor(), LCD_SPFD5408, LCD_WriteRAM(), LCD_WriteRAMWord(), LCDType, and TextColor.

void LCD_DrawFullCircle | ( | uint16_t | Xpos,
 |  | uint16_t | Ypos,
 |  | uint16_t | Radius
 | ) |  |

Displays a full circle.

Parameters:
Xpos,: specifies the X position.
Ypos,: specifies the Y position.
Radius
Return values:
None

Definition at line 826 of file stm32l152_eval_lcd.c.

References BackColor, LCD_DIR_HORIZONTAL, LCD_DrawCircle(), LCD_DrawLine(), LCD_SetTextColor(), and TextColor.

void LCD_DrawFullRect | ( | uint16_t | Xpos,
 |  | uint16_t | Ypos,
 |  | uint16_t | Width,
 |  | uint16_t | Height
 | ) |  |

Displays a full rectangle.

Parameters:
Xpos,: specifies the X position.
Ypos,: specifies the Y position.
Height,: rectangle height.
Width,: rectangle width.
Return values:
None

Definition at line 795 of file stm32l152_eval_lcd.c.

References BackColor, LCD_DIR_HORIZONTAL, LCD_DIR_VERTICAL, LCD_DrawLine(), LCD_SetTextColor(), and TextColor.

void LCD_DrawLine | ( | uint8_t | Xpos,
 |  | uint16_t | Ypos,
 |  | uint16_t | Length,
 |  | uint8_t | Direction
 | ) |  |

Displays a line.

Parameters:
Xpos,: specifies the X position.
Ypos,: specifies the Y position.
Length,: line length.
Direction,: line direction. This parameter can be one of the following values: Vertical or Horizontal.
Return values:
None

Definition at line 594 of file stm32l152_eval_lcd.c.

References Bit_SET, LCD_CtrlLinesWrite(), LCD_DIR_HORIZONTAL, LCD_HX8312, LCD_ILI9320, LCD_NCS_GPIO_PORT, LCD_NCS_PIN, LCD_SetCursor(), LCD_SPFD5408, LCD_WriteRAM(), LCD_WriteRAM_Prepare(), LCD_WriteRAMWord(), LCDType, and TextColor.

void LCD_DrawMonoPict ( const uint32_t * Pict )

Displays a monocolor picture.

Parameters:
Pict,: pointer to the picture array.
Return values:
None

Definition at line 701 of file stm32l152_eval_lcd.c.

References BackColor, Bit_SET, index, LCD_CtrlLinesWrite(), LCD_ILI9320, LCD_NCS_GPIO_PORT, LCD_NCS_PIN, LCD_PIXEL_WIDTH, LCD_SetCursor(), LCD_SPFD5408, LCD_WriteRAM(), LCD_WriteRAM_Prepare(), LCDType, and TextColor.

void LCD_DrawRect | ( | uint8_t | Xpos,
 |  | uint16_t | Ypos,
 |  | uint8_t | Height,
 |  | uint16_t | Width
 | ) |  |

Displays a rectangle.

Parameters:
Xpos,: specifies the X position.
Ypos,: specifies the Y position.
Height,: display rectangle height.
Width,: display rectangle width.
Return values:
None

Definition at line 630 of file stm32l152_eval_lcd.c.

References LCD_DIR_HORIZONTAL, LCD_DIR_VERTICAL, and LCD_DrawLine().

void LCD_DrawUniLine | ( | uint16_t | x1,
 |  | uint16_t | y1,
 |  | uint16_t | x2,
 |  | uint16_t | y2
 | ) |  |

Displays an uni line (between two points).

Parameters:
x1,: specifies the point 1 x position.
y1,: specifies the point 1 y position.
x2,: specifies the point 2 x position.
y2,: specifies the point 2 y position.
Return values:
None

Definition at line 876 of file stm32l152_eval_lcd.c.

References ABS, and PutPixel().

void LCD_FillPolyLine | ( | pPoint | Points,
 |  | uint16_t | PointCount
 | ) |  |

Displays a full polyline (between many points).

Parameters:
Points,: pointer to the points array.
PointCount,: Number of points.
Return values:
None

Definition at line 1040 of file stm32l152_eval_lcd.c.

References BackColor, j, LCD_DIR_HORIZONTAL, LCD_DrawLine(), LCD_SetTextColor(), MAX_POLY_CORNERS, POLY_X, POLY_Y, PutPixel(), TextColor, Point::X, and Point::Y.

void LCD_GetColors | ( | __IO uint16_t * | _TextColor,
 |  | __IO uint16_t * | _BackColor
 | ) |  |

Gets the LCD Text and Background colors.

Parameters:
_TextColor,: pointer to the variable that will contain the Text Color.
_BackColor,: pointer to the variable that will contain the Background Color.
Return values:
None

Definition at line 351 of file stm32l152_eval_lcd.c.

References BackColor, and TextColor.

sFONT* LCD_GetFont ( void )

Gets the Text Font.

Parameters:
None.
Return values:
the used font.

Definition at line 392 of file stm32l152_eval_lcd.c.

References LCD_Currentfonts.

void LCD_GLASS_Clear ( void )

This function Clear the whole LCD RAM.

Parameters:
None
Return values:
None

Definition at line 603 of file stm32l152_eval_glass_lcd.c.

References LCD.

Referenced by LCD_GLASS_ScrollString().

void LCD_GLASS_ClearChar ( uint8_t position )

This function Clear a char in the LCD RAM.

Parameters:
position,: Position in the LCD of the caracter to write. This parameter can be any value in range [0:7].
Return values:
None

< Clear the corresponding segments (SEG0, SEG1, SEG2, SEG3)

< Clear the corresponding segments (SEG4, SEG5, SEG6, SEG10)

< Clear the corresponding segments (SEG11, SEG16, SEG18, SEG19)

< Clear the corresponding segments (SEG20, SEG21, SEG22, SEG23)

< Clear the corresponding segments (SEG28, SEG29, SEG30, SEG31)

< Clear the corresponding segments (SEG32, SEG33, SEG34, SEG35)

< Clear the corresponding segments (SEG36, SEG37, SEG38, SEG39)

< Clear the corresponding segments (SEG40, SEG41, SEG42, SEG43)

Definition at line 528 of file stm32l152_eval_glass_lcd.c.

References LCD.

void LCD_GLASS_DisplayChar | ( | uint8_t * | ch,
 |  | Point_Typedef | point,
 |  | Apostrophe_Typedef | apostrophe,
 |  | uint8_t | position
 | ) |  |

This function writes a char in the LCD RAM.

Parameters:
ch,: The character to dispaly.
point,: A point to add in front of char. This parameter can be one of the following values:

  • POINT_OFF: No point to add in front of char.
  • POINT_ON: Add a point in front of char.
apostrophe,: Flag indicating if a apostrophe has to be add in front of displayed character. This parameter can be one of the following values:

  • APOSTROPHE_OFF: No apostrophe to add in back of char.
  • APOSTROPHE_ON: Add an apostrophe in back of char.
position,: Position in the LCD of the caracter to write. This parameter can be any value in range [0:7].
Return values:
None

< Wait Until the last LCD RAM update finish

< Requesy LCD RAM update

Definition at line 214 of file stm32l152_eval_glass_lcd.c.

References LCD_GLASS_WriteChar(), and RESET.

void LCD_GLASS_DisplayString ( uint8_t * ptr )

This function writes a char in the LCD RAM.

Parameters:
ptr,: Pointer to string to display on the LCD Glass.
Return values:
None

< Wait Until the last LCD RAM update finish

< Display one character on LCD

< Point on the next character

< Increment the character counter

Definition at line 232 of file stm32l152_eval_glass_lcd.c.

References APOSTROPHE_OFF, LCD_GLASS_WriteChar(), POINT_OFF, and RESET.

Referenced by LCD_GLASS_ScrollString().

void LCD_GLASS_Init ( void )

Configures the LCD GLASS relative GPIO port IOs and LCD peripheral.

Parameters:
None
Return values:
None

< Configure the LCD Glass GPIO pins

< Configure the LCD interface -------------------------------------------

< Enable LCD APB1 Clock

< Configure the Pulse On Duration

< Configure the LCD Contrast (3.51V)

< Wait Until the LCD FCR register is synchronized

< Enable LCD peripheral

< Wait Until the LCD is enabled

Definition at line 160 of file stm32l152_eval_glass_lcd.c.

References ENABLE, LCD_GPIOConfig(), RCC_APB1PeriphClockCmd(), and RESET.

void LCD_GLASS_ScrollString | ( | uint8_t * | ptr,
 |  | uint16_t | nScroll,
 |  | uint16_t | ScrollSpeed
 | ) |  |

Display a string in scrolling mode.

Note:
The LCD should be cleared before to start the write operation.
Parameters:
ptr,: Pointer to string to display on the LCD Glass.
nScroll,: Specifies how many time the message will be scrolled
ScrollSpeed,: Speciifes the speed of the scroll. Low value gives higher speed.
Return values:
None

Definition at line 411 of file stm32l152_eval_glass_lcd.c.

References delay(), LCD_GLASS_Clear(), and LCD_GLASS_DisplayString().

void LCD_GLASS_WriteChar | ( | uint8_t * | ch,
 |  | Point_Typedef | point,
 |  | Apostrophe_Typedef | apostrophe,
 |  | uint8_t | position
 | ) |  |

This function writes a char in the LCD RAM.

Parameters:
ch,: The character to dispaly.
point,: A point to add in front of char. This parameter can be one of the following values:

  • POINT_OFF : No point to add in front of char.
  • POINT_ON : Add a point in front of char.
apostrophe,: Flag indicating if a apostrophe has to be add in front of displayed character. This parameter can be one of the following values:

  • APOSTROPHE_OFF : No apostrophe to add in back of char.
  • APOSTROPHE_ON : Add an apostrophe in back of char.
position,: Position in the LCD of the caracter to write. This parameter can be any value in range [0:7].
Return values:
None

< Convert the corresponding character

< Clear the corresponding segments (SEG0, SEG1, SEG2, SEG3)

< Write the corresponding segments (SEG0, SEG1, SEG2, SEG3)

< Clear the corresponding segments (SEG4, SEG5, SEG6, SEG10)

< Write the corresponding segments (SEG4, SEG5, SEG6, SEG10)

< Clear the corresponding segments (SEG11, SEG16, SEG18, SEG19)

< Write the corresponding segments (SEG11, SEG16, SEG18, SEG19)

< Clear the corresponding segments (SEG20, SEG21, SEG22, SEG23)

< Write the corresponding segments (SEG20, SEG21, SEG22, SEG23)

< Clear the corresponding segments (SEG28, SEG29, SEG30, SEG31)

< Write the corresponding segments (SEG28, SEG29, SEG30, SEG31)

< Clear the corresponding segments (SEG32, SEG33, SEG34, SEG35)

< Write the corresponding segments (SEG32, SEG33, SEG34, SEG35)

< Clear the corresponding segments (SEG36, SEG37, SEG38, SEG39)

< Write the corresponding segments (SEG36, SEG37, SEG38, SEG39)

< Clear the corresponding segments (SEG40, SEG41, SEG42, SEG43)

< Write the corresponding segments (SEG40, SEG41, SEG42, SEG43)

Definition at line 271 of file stm32l152_eval_glass_lcd.c.

References Convert(), digit, and LCD.

Referenced by LCD_GLASS_DisplayChar(), and LCD_GLASS_DisplayString().

static void LCD_GPIOConfig ( void ) [static]

Configures the LCD Segments and Coms GPIOs.

Parameters:
None
Return values:
None

< Enable GPIOA, GPIOB, GPIOC, GPIOD and GPIOE AHB Clocks

< Connect PA.08 to LCD COM0

< Connect PA.09 to LCD COM1

< Connect PA.10 to LCD COM2

< Connect PB.09 to LCD COM3

< Connect PA.01 to LCD SEG0

< Connect PA.02 to LCD SEG1

< Connect PA.03 to LCD SEG2

< Connect PA.06 to LCD SEG3

< Connect PA.07 to LCD SEG4

< Connect PB.00 to LCD SEG5

< Connect PB.01 to LCD SEG6

< Connect PB.10 to LCD SEG10

< Connect PB.11 to LCD SEG11

< Connect PB.08 to LCD SEG16

< Connect PC.00 to LCD SEG18

< Connect PC.01 to LCD SEG19

< Connect PC.02 to LCD SEG20

< Connect PC.03 to LCD SEG21

< Connect PC.04 to LCD SEG22

< Connect PC.05 to LCD SEG23

< Connect PD.08 to LCD SEG28

< Connect PD.09 to LCD SEG29

< Connect PD.10 to LCD SEG30

< Connect PD.11 to LCD SEG31

< Connect PD.12 to LCD SEG32

< Connect PD.13 to LCD SEG33

< Connect PD.14 to LCD SEG34

< Connect PD.15 to LCD SEG35

< Connect PE.00 to LCD SEG36

< Connect PE.01 to LCD SEG37

< Connect PE.02 to LCD SEG38

< Connect PE.03 to LCD SEG39

< Connect PC.10 to LCD SEG40

< Connect PC.11 to LCD SEG41

< Connect PC.12 to LCD SEG42

< Connect PD.02 to LCD SEG43

Definition at line 674 of file stm32l152_eval_glass_lcd.c.

References ENABLE, GPIO_Init(), GPIO_InitStructure, GPIO_InitTypeDef::GPIO_Mode, GPIO_InitTypeDef::GPIO_Pin, GPIO_Pin_0, GPIO_Pin_1, GPIO_Pin_10, GPIO_Pin_11, GPIO_Pin_12, GPIO_Pin_13, GPIO_Pin_14, GPIO_Pin_15, GPIO_Pin_2, GPIO_Pin_3, GPIO_Pin_4, GPIO_Pin_5, GPIO_Pin_6, GPIO_Pin_7, GPIO_Pin_8, GPIO_Pin_9, GPIO_PinSource0, GPIO_PinSource1, GPIO_PinSource10, GPIO_PinSource11, GPIO_PinSource12, GPIO_PinSource13, GPIO_PinSource14, GPIO_PinSource15, GPIO_PinSource2, GPIO_PinSource3, GPIO_PinSource4, GPIO_PinSource5, GPIO_PinSource6, GPIO_PinSource7, GPIO_PinSource8, GPIO_PinSource9, GPIO_InitTypeDef::GPIO_Speed, GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, and RCC_AHBPeriphClockCmd().

Referenced by LCD_GLASS_Init().

void LCD_nCS_StartByte ( uint8_t Start_Byte )

Reset LCD control line(/CS) and Send Start-Byte.

Parameters:
Start_Byte,: the Start-Byte to be sent
Return values:
None

Definition at line 1146 of file stm32l152_eval_lcd.c.

References Bit_RESET, LCD_CtrlLinesWrite(), LCD_NCS_GPIO_PORT, LCD_NCS_PIN, LCD_SPI, RESET, SPI_I2S_FLAG_BSY, SPI_I2S_GetFlagStatus(), and SPI_I2S_SendData().

void LCD_PolyLine | ( | pPoint | Points,
 |  | uint16_t | PointCount
 | ) |  |

Displays an polyline (between many points).

Parameters:
Points,: pointer to the points array.
PointCount,: Number of points.
Return values:
None

Definition at line 949 of file stm32l152_eval_lcd.c.

References LCD_DrawUniLine(), Point::X, and Point::Y.

void LCD_PolyLineRelative | ( | pPoint | Points,
 |  | uint16_t | PointCount
 | ) |  |

Displays a relative polyline (between many points).

Parameters:
Points,: pointer to the points array.
PointCount,: Number of points.
Return values:
None

Definition at line 1017 of file stm32l152_eval_lcd.c.

References LCD_PolyLineRelativeClosed().

static void LCD_PolyLineRelativeClosed | ( | pPoint | Points,
 |  | uint16_t | PointCount,
 |  | uint16_t | Closed
 | ) |  | [static]

Displays an relative polyline (between many points).

Parameters:
Points,: pointer to the points array.
PointCount,: Number of points.
Closed,: specifies if the draw is closed or not. 1: closed, 0 : not closed.
Return values:
None

Definition at line 975 of file stm32l152_eval_lcd.c.

References LCD_DrawUniLine(), Point::X, and Point::Y.

Referenced by LCD_ClosedPolyLineRelative(), and LCD_PolyLineRelative().

void LCD_PowerOn ( void )

Power on the LCD.

Parameters:
None
Return values:
None

Definition at line 1333 of file stm32l152_eval_lcd.c.

References _delay_, LCD_HX8312, LCD_ILI9320, LCD_REG_16, LCD_REG_17, LCD_REG_18, LCD_REG_19, LCD_REG_24, LCD_REG_27, LCD_REG_28, LCD_REG_30, LCD_REG_31, LCD_REG_32, LCD_REG_36, LCD_REG_41, LCD_REG_7, LCD_SPFD5408, LCD_WriteReg(), and LCDType.

uint16_t LCD_ReadReg ( uint8_t LCD_Reg )

Reads the selected LCD Register.

Parameters:
LCD_Reg,: address of the selected register.
Return values:
LCD Register Value.

Definition at line 1221 of file stm32l152_eval_lcd.c.

References Bit_SET, LCD_CtrlLinesWrite(), LCD_NCS_GPIO_PORT, LCD_NCS_PIN, LCD_nCS_StartByte(), LCD_READ_REG, LCD_SPI, LCD_WriteRegIndex(), RESET, SPI_I2S_FLAG_BSY, SPI_I2S_FLAG_RXNE, SPI_I2S_GetFlagStatus(), SPI_I2S_ReceiveData(), SPI_I2S_SendData(), and START_BYTE.

void LCD_SetBackColor ( __IO uint16_t Color )

Sets the Background color.

Parameters:
Color,: specifies the Background color code RGB(5-6-5).
Return values:
None

Definition at line 372 of file stm32l152_eval_lcd.c.

References BackColor.

void LCD_SetColors | ( | __IO uint16_t | _TextColor,
 |  | __IO uint16_t | _BackColor
 | ) |  |

Sets the LCD Text and Background colors.

Parameters:
_TextColor,: specifies the Text Color.
_BackColor,: specifies the Background Color.
Return values:
None

Definition at line 337 of file stm32l152_eval_lcd.c.

References BackColor, and TextColor.

void LCD_SetCursor | ( | uint8_t | Xpos,
 |  | uint16_t | Ypos
 | ) |  |

Sets the cursor position.

Parameters:
Xpos,: specifies the X position.
Ypos,: specifies the Y position.
Return values:
None

Definition at line 448 of file stm32l152_eval_lcd.c.

References LCD_HX8312, LCD_ILI9320, LCD_REG_32, LCD_REG_33, LCD_REG_66, LCD_REG_67, LCD_REG_68, LCD_SPFD5408, LCD_WriteReg(), and LCDType.

void LCD_SetDisplayWindow | ( | uint8_t | Xpos,
 |  | uint16_t | Ypos,
 |  | uint8_t | Height,
 |  | uint16_t | Width
 | ) |  |

Sets a display window.

Parameters:
Xpos,: specifies the X buttom left position.
Ypos,: specifies the Y buttom left position.
Height,: display window height.
Width,: display window width.
Return values:
None

Definition at line 545 of file stm32l152_eval_lcd.c.

References LCD_HX8312, LCD_ILI9320, LCD_REG_1, LCD_REG_5, LCD_REG_69, LCD_REG_70, LCD_REG_71, LCD_REG_72, LCD_REG_73, LCD_REG_74, LCD_REG_80, LCD_REG_81, LCD_REG_82, LCD_REG_83, LCD_SetCursor(), LCD_SPFD5408, LCD_WriteReg(), and LCDType.

void LCD_SetFont ( sFONT * fonts )

Sets the Text Font.

Parameters:
fonts,: specifies the font to be used.
Return values:
None

Definition at line 382 of file stm32l152_eval_lcd.c.

void LCD_SetTextColor ( __IO uint16_t Color )

Sets the Text color.

Parameters:
Color,: specifies the Text color code RGB(5-6-5).
Return values:
None

Definition at line 361 of file stm32l152_eval_lcd.c.

References TextColor.

void LCD_Setup ( void )

Setups the LCD.

Parameters:
None
Return values:
None

Definition at line 151 of file stm32l152_eval_lcd.c.

References _delay_, LCD_CtrlLinesConfig(), LCD_HX8312, LCD_ILI9320, LCD_REG_0, LCD_REG_1, LCD_REG_10, LCD_REG_106, LCD_REG_118, LCD_REG_12, LCD_REG_128, LCD_REG_129, LCD_REG_13, LCD_REG_130, LCD_REG_131, LCD_REG_132, LCD_REG_133, LCD_REG_134, LCD_REG_135, LCD_REG_136, LCD_REG_137, LCD_REG_139, LCD_REG_14, LCD_REG_141, LCD_REG_143, LCD_REG_144, LCD_REG_145, LCD_REG_146, LCD_REG_147, LCD_REG_148, LCD_REG_149, LCD_REG_15, LCD_REG_150, LCD_REG_151, LCD_REG_152, LCD_REG_153, LCD_REG_154, LCD_REG_157, LCD_REG_16, LCD_REG_17, LCD_REG_18, LCD_REG_19, LCD_REG_192, LCD_REG_2, LCD_REG_20, LCD_REG_21, LCD_REG_22, LCD_REG_227, LCD_REG_229, LCD_REG_23, LCD_REG_231, LCD_REG_239, LCD_REG_24, LCD_REG_25, LCD_REG_26, LCD_REG_27, LCD_REG_28, LCD_REG_29, LCD_REG_3, LCD_REG_30, LCD_REG_31, LCD_REG_32, LCD_REG_33, LCD_REG_36, LCD_REG_37, LCD_REG_4, LCD_REG_40, LCD_REG_41, LCD_REG_43, LCD_REG_48, LCD_REG_49, LCD_REG_5, LCD_REG_50, LCD_REG_51, LCD_REG_52, LCD_REG_53, LCD_REG_54, LCD_REG_55, LCD_REG_56, LCD_REG_57, LCD_REG_59, LCD_REG_60, LCD_REG_61, LCD_REG_62, LCD_REG_63, LCD_REG_64, LCD_REG_65, LCD_REG_66, LCD_REG_67, LCD_REG_68, LCD_REG_69, LCD_REG_7, LCD_REG_70, LCD_REG_71, LCD_REG_72, LCD_REG_73, LCD_REG_74, LCD_REG_75, LCD_REG_76, LCD_REG_78, LCD_REG_79, LCD_REG_8, LCD_REG_80, LCD_REG_81, LCD_REG_82, LCD_REG_83, LCD_REG_9, LCD_REG_96, LCD_REG_97, LCD_SPFD5408, LCD_SPIConfig(), LCD_WriteReg(), and LCDType.

void LCD_SPIConfig ( void )

Configures the LCD_SPI interface.

Parameters:
None
Return values:
None

Definition at line 1426 of file stm32l152_eval_lcd.c.

References ENABLE, GPIO_Init(), GPIO_InitStructure, GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_AF_PP, GPIO_InitTypeDef::GPIO_Pin, GPIO_InitTypeDef::GPIO_Speed, GPIO_Speed_50MHz, LCD_HX8312, LCD_ILI9320, LCD_SPFD5408, LCD_SPI, LCD_SPI_CLK, LCD_SPI_MISO_AF, LCD_SPI_MISO_GPIO_CLK, LCD_SPI_MISO_GPIO_PORT, LCD_SPI_MISO_PIN, LCD_SPI_MISO_SOURCE, LCD_SPI_MOSI_AF, LCD_SPI_MOSI_GPIO_CLK, LCD_SPI_MOSI_GPIO_PORT, LCD_SPI_MOSI_PIN, LCD_SPI_MOSI_SOURCE, LCD_SPI_SCK_AF, LCD_SPI_SCK_GPIO_CLK, LCD_SPI_SCK_GPIO_PORT, LCD_SPI_SCK_PIN, LCD_SPI_SCK_SOURCE, LCDType, RCC_AHBPeriphClockCmd(), RCC_APB1PeriphClockCmd(), RCC_APB2PeriphClockCmd(), SPI_InitTypeDef::SPI_BaudRatePrescaler, SPI_BaudRatePrescaler_2, SPI_Cmd(), SPI_InitTypeDef::SPI_CPHA, SPI_CPHA_1Edge, SPI_CPHA_2Edge, SPI_InitTypeDef::SPI_CPOL, SPI_CPOL_High, SPI_CPOL_Low, SPI_InitTypeDef::SPI_CRCPolynomial, SPI_InitTypeDef::SPI_DataSize, SPI_DataSize_16b, SPI_DataSize_8b, SPI_InitTypeDef::SPI_Direction, SPI_Direction_2Lines_FullDuplex, SPI_InitTypeDef::SPI_FirstBit, SPI_FirstBit_MSB, SPI_I2S_DeInit(), SPI_Init(), SPI_InitStructure, SPI_InitTypeDef::SPI_Mode, SPI_Mode_Master, SPI_InitTypeDef::SPI_NSS, and SPI_NSS_Soft.

void LCD_WindowModeDisable ( void )

Disables LCD Window mode.

Parameters:
None
Return values:
None

Definition at line 579 of file stm32l152_eval_lcd.c.

References LCD_HX8312, LCD_ILI9320, LCD_REG_1, LCD_REG_3, LCD_REG_5, LCD_SetDisplayWindow(), LCD_SPFD5408, LCD_WriteReg(), and LCDType.

void LCD_WriteRAM ( uint16_t RGB_Code )

Writes to the LCD RAM.

Parameters:
RGB_Code,: the pixel color in RGB mode (5-6-5).
Return values:
None

Definition at line 1315 of file stm32l152_eval_lcd.c.

References Bit_RESET, Bit_SET, LCD_CtrlLinesWrite(), LCD_HX8312, LCD_ILI9320, LCD_NCS_GPIO_PORT, LCD_NCS_PIN, LCD_NWR_GPIO_PORT, LCD_NWR_PIN, LCD_RS_GPIO_PORT, LCD_RS_PIN, LCD_SPFD5408, LCD_SPI, LCDType, RESET, SPI_I2S_FLAG_BSY, SPI_I2S_GetFlagStatus(), and SPI_I2S_SendData().

void LCD_WriteRAM_Prepare ( void )

Prepare to write to the LCD RAM.

Parameters:
None
Return values:
None

Definition at line 1287 of file stm32l152_eval_lcd.c.

References LCD_nCS_StartByte(), LCD_REG_34, LCD_WRITE_REG, LCD_WriteRegIndex(), and START_BYTE.

void LCD_WriteRAMWord ( uint16_t RGB_Code )

Writes 1 word to the LCD RAM.

Parameters:
RGB_Code,: the pixel color in RGB mode (5-6-5).
Return values:
None

Definition at line 1301 of file stm32l152_eval_lcd.c.

References Bit_SET, LCD_CtrlLinesWrite(), LCD_NCS_GPIO_PORT, LCD_NCS_PIN, LCD_WriteRAM(), and LCD_WriteRAM_Prepare().

void LCD_WriteReg | ( | uint8_t | LCD_Reg,
 |  | uint16_t | LCD_RegValue
 | ) |  |

Writes to the selected LCD ILI9320 register.

Writes to the selected LCD register.

Parameters:
LCD_Reg,: address of the selected register.
LCD_RegValue,: value to write to the selected register.
Return values:
None

Definition at line 1191 of file stm32l152_eval_lcd.c.

References Bit_SET, LCD_CtrlLinesWrite(), LCD_HX8312, LCD_ILI9320, LCD_NCS_GPIO_PORT, LCD_NCS_PIN, LCD_nCS_StartByte(), LCD_SPFD5408, LCD_SPI, LCD_WRITE_REG, LCD_WriteRegHX8312(), LCD_WriteRegILI9320(), LCD_WriteRegIndex(), LCDType, RESET, and START_BYTE.

void LCD_WriteRegIndex ( uint8_t LCD_Reg )

Writes index to select the LCD register.

Parameters:
LCD_Reg,: address of the selected register.
Return values:
None

Definition at line 1163 of file stm32l152_eval_lcd.c.

References Bit_SET, LCD_CtrlLinesWrite(), LCD_NCS_GPIO_PORT, LCD_NCS_PIN, LCD_nCS_StartByte(), LCD_SPI, RESET, SET_INDEX, SPI_I2S_FLAG_BSY, SPI_I2S_GetFlagStatus(), SPI_I2S_SendData(), and START_BYTE.

static void PutPixel | ( | int16_t | x,
 |  | int16_t | y
 | ) |  | [static]

Displays a pixel.

Parameters:
x,: pixel x.
y,: pixel y.
Return values:
None

Definition at line 1486 of file stm32l152_eval_lcd.c.

References LCD_DIR_HORIZONTAL, and LCD_DrawLine().

Referenced by LCD_DrawUniLine(), and LCD_FillPolyLine().

void STM32L152_LCD_DeInit ( void )

DeInitializes the LCD.

Parameters:
None
Return values:
None

< LCD Display Off

< LCD_SPI disable

< LCD_SPI DeInit

< Disable SPI clock

Definition at line 113 of file stm32l152_eval_lcd.c.

References DISABLE, GPIO_Init(), GPIO_InitStructure, GPIO_InitTypeDef::GPIO_Mode, GPIO_InitTypeDef::GPIO_Pin, LCD_DisplayOff(), LCD_NCS_GPIO_PORT, LCD_NCS_PIN, LCD_SPI, LCD_SPI_CLK, LCD_SPI_MISO_GPIO_PORT, LCD_SPI_MISO_PIN, LCD_SPI_MOSI_GPIO_PORT, LCD_SPI_MOSI_PIN, LCD_SPI_SCK_GPIO_PORT, LCD_SPI_SCK_PIN, RCC_APB1PeriphClockCmd(), and SPI_Cmd().

void STM32L152_LCD_Init ( void )

Initializes the LCD.

Parameters:
None
Return values:
None

Definition at line 311 of file stm32l152_eval_lcd.c.

References LCD_DEFAULT_FONT, LCD_ILI9320, LCD_ReadReg(), LCD_REG_0, LCD_SetFont(), LCD_Setup(), LCD_SPFD5408, and LCDType.


STM32F10x Standard Peripherals Firmware Library: STM32L152_EVAL_GLASS_LCD_Exported_Types

Enumerations

STM32L152_EVAL_GLASS_LCD_Exported_Types

STM32L152_EVAL_GLASS_LCD

Enumerations

enum | Apostrophe_Typedef { APOSTROPHE_OFF = 0, APOSTROPHE_ON = 1 }
enum | Point_Typedef { POINT_OFF = 0, POINT_ON = 1 }

Enumeration Type Documentation

enum Apostrophe_Typedef
Enumerator:
APOSTROPHE_OFF
APOSTROPHE_ON

Definition at line 59 of file stm32l152_eval_glass_lcd.h.

enum Point_Typedef
Enumerator:
POINT_OFF
POINT_ON

Definition at line 53 of file stm32l152_eval_glass_lcd.h.


STM32F10x Standard Peripherals Firmware Library: STM32L152_EVAL_GLASS_LCD_Exported_Constants

STM32L152_EVAL_GLASS_LCD_Exported_Constants

STM32L152_EVAL_GLASS_LCD


STM32F10x Standard Peripherals Firmware Library: STM32L152_EVAL_GLASS_LCD_Exported_Macros

STM32L152_EVAL_GLASS_LCD_Exported_Macros

STM32L152_EVAL_GLASS_LCD


STM32F10x Standard Peripherals Firmware Library: STM32L152_EVAL_GLASS_LCD_Exported_Functions

Functions

STM32L152_EVAL_GLASS_LCD_Exported_Functions

STM32L152_EVAL_GLASS_LCD

Functions

void | LCD_GLASS_Clear (void)
This function Clear the whole LCD RAM.
void | LCD_GLASS_ClearChar (uint8_t position)
This function Clear a char in the LCD RAM.
void | LCD_GLASS_DisplayChar (uint8_t *ch, Point_Typedef point, Apostrophe_Typedef apostrophe, uint8_t position)
This function writes a char in the LCD RAM.
void | LCD_GLASS_DisplayString (uint8_t *ptr)
This function writes a char in the LCD RAM.
void | LCD_GLASS_Init (void)
Configures the LCD GLASS relative GPIO port IOs and LCD peripheral.
void | LCD_GLASS_ScrollString (uint8_t *ptr, uint16_t nScroll, uint16_t ScrollSpeed)
Display a string in scrolling mode.
void | LCD_GLASS_WriteChar (uint8_t *ch, Point_Typedef point, Apostrophe_Typedef apostrophe, uint8_t position)
This function writes a char in the LCD RAM.

Function Documentation

void LCD_GLASS_Clear ( void )

This function Clear the whole LCD RAM.

Parameters:
None
Return values:
None

Definition at line 603 of file stm32l152_eval_glass_lcd.c.

References LCD.

Referenced by LCD_GLASS_ScrollString().

void LCD_GLASS_ClearChar ( uint8_t position )

This function Clear a char in the LCD RAM.

Parameters:
position,: Position in the LCD of the caracter to write. This parameter can be any value in range [0:7].
Return values:
None

< Clear the corresponding segments (SEG0, SEG1, SEG2, SEG3)

< Clear the corresponding segments (SEG4, SEG5, SEG6, SEG10)

< Clear the corresponding segments (SEG11, SEG16, SEG18, SEG19)

< Clear the corresponding segments (SEG20, SEG21, SEG22, SEG23)

< Clear the corresponding segments (SEG28, SEG29, SEG30, SEG31)

< Clear the corresponding segments (SEG32, SEG33, SEG34, SEG35)

< Clear the corresponding segments (SEG36, SEG37, SEG38, SEG39)

< Clear the corresponding segments (SEG40, SEG41, SEG42, SEG43)

Definition at line 528 of file stm32l152_eval_glass_lcd.c.

References LCD.

void LCD_GLASS_DisplayChar | ( | uint8_t * | ch,
 |  | Point_Typedef | point,
 |  | Apostrophe_Typedef | apostrophe,
 |  | uint8_t | position
 | ) |  |

This function writes a char in the LCD RAM.

Parameters:
ch,: The character to dispaly.
point,: A point to add in front of char. This parameter can be one of the following values:

  • POINT_OFF: No point to add in front of char.
  • POINT_ON: Add a point in front of char.
apostrophe,: Flag indicating if a apostrophe has to be add in front of displayed character. This parameter can be one of the following values:

  • APOSTROPHE_OFF: No apostrophe to add in back of char.
  • APOSTROPHE_ON: Add an apostrophe in back of char.
position,: Position in the LCD of the caracter to write. This parameter can be any value in range [0:7].
Return values:
None

< Wait Until the last LCD RAM update finish

< Requesy LCD RAM update

Definition at line 214 of file stm32l152_eval_glass_lcd.c.

References LCD_GLASS_WriteChar(), and RESET.

void LCD_GLASS_DisplayString ( uint8_t * ptr )

This function writes a char in the LCD RAM.

Parameters:
ptr,: Pointer to string to display on the LCD Glass.
Return values:
None

< Wait Until the last LCD RAM update finish

< Display one character on LCD

< Point on the next character

< Increment the character counter

Definition at line 232 of file stm32l152_eval_glass_lcd.c.

References APOSTROPHE_OFF, LCD_GLASS_WriteChar(), POINT_OFF, and RESET.

Referenced by LCD_GLASS_ScrollString().

void LCD_GLASS_Init ( void )

Configures the LCD GLASS relative GPIO port IOs and LCD peripheral.

Parameters:
None
Return values:
None

< Configure the LCD Glass GPIO pins

< Configure the LCD interface -------------------------------------------

< Enable LCD APB1 Clock

< Configure the Pulse On Duration

< Configure the LCD Contrast (3.51V)

< Wait Until the LCD FCR register is synchronized

< Enable LCD peripheral

< Wait Until the LCD is enabled

Definition at line 160 of file stm32l152_eval_glass_lcd.c.

References ENABLE, LCD_GPIOConfig(), RCC_APB1PeriphClockCmd(), and RESET.

void LCD_GLASS_ScrollString | ( | uint8_t * | ptr,
 |  | uint16_t | nScroll,
 |  | uint16_t | ScrollSpeed
 | ) |  |

Display a string in scrolling mode.

Note:
The LCD should be cleared before to start the write operation.
Parameters:
ptr,: Pointer to string to display on the LCD Glass.
nScroll,: Specifies how many time the message will be scrolled
ScrollSpeed,: Speciifes the speed of the scroll. Low value gives higher speed.
Return values:
None

Definition at line 411 of file stm32l152_eval_glass_lcd.c.

References delay(), LCD_GLASS_Clear(), and LCD_GLASS_DisplayString().

void LCD_GLASS_WriteChar | ( | uint8_t * | ch,
 |  | Point_Typedef | point,
 |  | Apostrophe_Typedef | apostrophe,
 |  | uint8_t | position
 | ) |  |

This function writes a char in the LCD RAM.

Parameters:
ch,: The character to dispaly.
point,: A point to add in front of char. This parameter can be one of the following values:

  • POINT_OFF : No point to add in front of char.
  • POINT_ON : Add a point in front of char.
apostrophe,: Flag indicating if a apostrophe has to be add in front of displayed character. This parameter can be one of the following values:

  • APOSTROPHE_OFF : No apostrophe to add in back of char.
  • APOSTROPHE_ON : Add an apostrophe in back of char.
position,: Position in the LCD of the caracter to write. This parameter can be any value in range [0:7].
Return values:
None

< Convert the corresponding character

< Clear the corresponding segments (SEG0, SEG1, SEG2, SEG3)

< Write the corresponding segments (SEG0, SEG1, SEG2, SEG3)

< Clear the corresponding segments (SEG4, SEG5, SEG6, SEG10)

< Write the corresponding segments (SEG4, SEG5, SEG6, SEG10)

< Clear the corresponding segments (SEG11, SEG16, SEG18, SEG19)

< Write the corresponding segments (SEG11, SEG16, SEG18, SEG19)

< Clear the corresponding segments (SEG20, SEG21, SEG22, SEG23)

< Write the corresponding segments (SEG20, SEG21, SEG22, SEG23)

< Clear the corresponding segments (SEG28, SEG29, SEG30, SEG31)

< Write the corresponding segments (SEG28, SEG29, SEG30, SEG31)

< Clear the corresponding segments (SEG32, SEG33, SEG34, SEG35)

< Write the corresponding segments (SEG32, SEG33, SEG34, SEG35)

< Clear the corresponding segments (SEG36, SEG37, SEG38, SEG39)

< Write the corresponding segments (SEG36, SEG37, SEG38, SEG39)

< Clear the corresponding segments (SEG40, SEG41, SEG42, SEG43)

< Write the corresponding segments (SEG40, SEG41, SEG42, SEG43)

Definition at line 271 of file stm32l152_eval_glass_lcd.c.

References Convert(), digit, and LCD.

Referenced by LCD_GLASS_DisplayChar(), and LCD_GLASS_DisplayString().


STM32F10x Standard Peripherals Firmware Library: STM32L152_EVAL_LCD_Private_Types

STM32L152_EVAL_LCD_Private_Types

STM32L152_EVAL_LCD


STM32F10x Standard Peripherals Firmware Library: STM32L152_EVAL_LCD_Private_Defines

Defines

STM32L152_EVAL_LCD_Private_Defines

STM32L152_EVAL_LCD

Defines

#define | LCD_ILI9320 0x9320
#define | LCD_READ_REG 0x03
#define | LCD_SPFD5408 0x5408
#define | LCD_WRITE_REG 0x02
#define | MAX_POLY_CORNERS 200
#define | POLY_X(Z) ((int32_t)((Points + Z)->Y))
#define | POLY_Y(Z) ((int32_t)((Points + Z)->X))
#define | READ_STATUS 0x01
#define | SET_INDEX 0x00
#define | START_BYTE 0x70

Define Documentation

#define LCD_ILI9320 0x9320

Definition at line 57 of file stm32l152_eval_lcd.c.

Referenced by LCD_Setup(), and STM32L152_LCD_Init().

#define LCD_READ_REG 0x03

Definition at line 63 of file stm32l152_eval_lcd.c.

Referenced by LCD_ReadReg().

#define LCD_SPFD5408 0x5408

Definition at line 58 of file stm32l152_eval_lcd.c.

Referenced by LCD_Setup(), and STM32L152_LCD_Init().

#define LCD_WRITE_REG 0x02

Definition at line 62 of file stm32l152_eval_lcd.c.

Referenced by LCD_WriteRAM_Prepare(), and LCD_WriteReg().

#define MAX_POLY_CORNERS 200

Definition at line 64 of file stm32l152_eval_lcd.c.

Referenced by LCD_FillPolyLine().

#define POLY_X ( Z ) ((int32_t)((Points + Z)->Y))

Definition at line 66 of file stm32l152_eval_lcd.c.

Referenced by LCD_FillPolyLine().

#define POLY_Y ( Z ) ((int32_t)((Points + Z)->X))

Definition at line 65 of file stm32l152_eval_lcd.c.

Referenced by LCD_FillPolyLine().

#define READ_STATUS 0x01

Definition at line 61 of file stm32l152_eval_lcd.c.

#define SET_INDEX 0x00

Definition at line 60 of file stm32l152_eval_lcd.c.

Referenced by LCD_WriteRegIndex().

#define START_BYTE 0x70

Definition at line 59 of file stm32l152_eval_lcd.c.

Referenced by LCD_ReadReg(), LCD_WriteRAM_Prepare(), LCD_WriteReg(), and LCD_WriteRegIndex().


STM32F10x Standard Peripherals Firmware Library: STM32L152_EVAL_LCD_Private_Macros

Defines

STM32L152_EVAL_LCD_Private_Macros

STM32L152_EVAL_LCD

Defines

#define ABS(X) ((X) > 0 ? (X) : -(X))

Define Documentation

#define ABS ( X ) ((X) > 0 ? (X) : -(X))

Definition at line 74 of file stm32l152_eval_lcd.c.

Referenced by LCD_DrawUniLine().


STM32F10x Standard Peripherals Firmware Library: STM32L152_EVAL_LCD_Private_Variables

Variables

STM32L152_EVAL_LCD_Private_Variables

STM32L152_EVAL_LCD

Variables

static __IO uint16_t | BackColor = 0xFFFF
static sFONT * | LCD_Currentfonts
static __IO uint32_t | LCDType = LCD_SPFD5408
static __IO uint16_t | TextColor = 0x0000

Variable Documentation

__IO uint16_t BackColor = 0xFFFF

Definition at line 84 of file stm32l152_eval_lcd.c.

sFONT* LCD_Currentfonts [static]

Definition at line 82 of file stm32l152_eval_lcd.c.

Referenced by LCD_GetFont().

__IO uint32_t LCDType = LCD_SPFD5408 [static]

Definition at line 85 of file stm32l152_eval_lcd.c.

Referenced by LCD_Setup(), and STM32L152_LCD_Init().

__IO uint16_t TextColor = 0x0000 [static]

Definition at line 84 of file stm32l152_eval_lcd.c.

Referenced by LCD_DrawChar(), LCD_DrawCircle(), LCD_DrawFullCircle(), LCD_DrawFullRect(), LCD_DrawLine(), LCD_DrawMonoPict(), LCD_FillPolyLine(), LCD_GetColors(), LCD_SetColors(), and LCD_SetTextColor().


STM32F10x Standard Peripherals Firmware Library: STM32L152_EVAL_LCD_Exported_Types

Data Structures | Typedefs

STM32L152_EVAL_LCD_Exported_Types

STM32L152_EVAL_LCD

Data Structures

struct | Point

Typedefs

typedef struct Point * | pPoint

Typedef Documentation

typedef struct Point * pPoint


STM32F10x Standard Peripherals Firmware Library: STM32L152_EVAL_LCD_Exported_Constants

Defines

STM32L152_EVAL_LCD_Exported_Constants

STM32L152_EVAL_LCD

Defines

#define | _delay_ delay
Uncomment the line below if you want to use LCD_DrawBMP function to display a bitmap picture on the LCD.
#define | LCD_COLOR_BLACK 0x0000
#define | LCD_COLOR_BLUE 0x001F
#define | LCD_COLOR_BLUE2 0x051F
#define | LCD_COLOR_CYAN 0x7FFF
#define | LCD_COLOR_GREEN 0x07E0
#define | LCD_COLOR_GREY 0xF7DE
#define | LCD_COLOR_MAGENTA 0xF81F
#define | LCD_COLOR_RED 0xF800
#define | LCD_COLOR_WHITE 0xFFFF
LCD color.
#define | LCD_COLOR_YELLOW 0xFFE0
#define | LCD_DEFAULT_FONT Font16x24
LCD default font.
#define | LCD_DIR_HORIZONTAL 0x0000
LCD Direction.
#define | LCD_DIR_VERTICAL 0x0001
#define | LCD_LINE_0 LINE(0)
LCD Lines depending on the chosen fonts.
#define | LCD_LINE_1 LINE(1)
#define | LCD_LINE_10 LINE(10)
#define | LCD_LINE_11 LINE(11)
#define | LCD_LINE_12 LINE(12)
#define | LCD_LINE_13 LINE(13)
#define | LCD_LINE_14 LINE(14)
#define | LCD_LINE_15 LINE(15)
#define | LCD_LINE_16 LINE(16)
#define | LCD_LINE_17 LINE(17)
#define | LCD_LINE_18 LINE(18)
#define | LCD_LINE_19 LINE(19)
#define | LCD_LINE_2 LINE(2)
#define | LCD_LINE_20 LINE(20)
#define | LCD_LINE_21 LINE(21)
#define | LCD_LINE_22 LINE(22)
#define | LCD_LINE_23 LINE(23)
#define | LCD_LINE_24 LINE(24)
#define | LCD_LINE_25 LINE(25)
#define | LCD_LINE_26 LINE(26)
#define | LCD_LINE_27 LINE(27)
#define | LCD_LINE_28 LINE(28)
#define | LCD_LINE_29 LINE(29)
#define | LCD_LINE_3 LINE(3)
#define | LCD_LINE_4 LINE(4)
#define | LCD_LINE_5 LINE(5)
#define | LCD_LINE_6 LINE(6)
#define | LCD_LINE_7 LINE(7)
#define | LCD_LINE_8 LINE(8)
#define | LCD_LINE_9 LINE(9)
#define | LCD_NCS_GPIO_CLK RCC_AHBPeriph_GPIOH
#define | LCD_NCS_GPIO_PORT GPIOH
#define | LCD_NCS_PIN GPIO_Pin_2
LCD Control pins.
#define | LCD_PIXEL_HEIGHT 0x00F0
#define | LCD_PIXEL_WIDTH 0x0140
LCD Size (Width and Height)
#define | LCD_REG_0 0x00
LCD Registers.
#define | LCD_REG_1 0x01
#define | LCD_REG_10 0x0A
#define | LCD_REG_106 0x6A
#define | LCD_REG_118 0x76
#define | LCD_REG_12 0x0C
#define | LCD_REG_128 0x80
#define | LCD_REG_129 0x81
#define | LCD_REG_13 0x0D
#define | LCD_REG_130 0x82
#define | LCD_REG_131 0x83
#define | LCD_REG_132 0x84
#define | LCD_REG_133 0x85
#define | LCD_REG_134 0x86
#define | LCD_REG_135 0x87
#define | LCD_REG_136 0x88
#define | LCD_REG_137 0x89
#define | LCD_REG_139 0x8B
#define | LCD_REG_14 0x0E
#define | LCD_REG_140 0x8C
#define | LCD_REG_141 0x8D
#define | LCD_REG_143 0x8F
#define | LCD_REG_144 0x90
#define | LCD_REG_145 0x91
#define | LCD_REG_146 0x92
#define | LCD_REG_147 0x93
#define | LCD_REG_148 0x94
#define | LCD_REG_149 0x95
#define | LCD_REG_15 0x0F
#define | LCD_REG_150 0x96
#define | LCD_REG_151 0x97
#define | LCD_REG_152 0x98
#define | LCD_REG_153 0x99
#define | LCD_REG_154 0x9A
#define | LCD_REG_157 0x9D
#define | LCD_REG_16 0x10
#define | LCD_REG_17 0x11
#define | LCD_REG_18 0x12
#define | LCD_REG_19 0x13
#define | LCD_REG_192 0xC0
#define | LCD_REG_193 0xC1
#define | LCD_REG_2 0x02
#define | LCD_REG_20 0x14
#define | LCD_REG_21 0x15
#define | LCD_REG_22 0x16
#define | LCD_REG_227 0xE3
#define | LCD_REG_229 0xE5
#define | LCD_REG_23 0x17
#define | LCD_REG_231 0xE7
#define | LCD_REG_239 0xEF
#define | LCD_REG_24 0x18
#define | LCD_REG_25 0x19
#define | LCD_REG_26 0x1A
#define | LCD_REG_27 0x1B
#define | LCD_REG_28 0x1C
#define | LCD_REG_29 0x1D
#define | LCD_REG_3 0x03
#define | LCD_REG_30 0x1E
#define | LCD_REG_31 0x1F
#define | LCD_REG_32 0x20
#define | LCD_REG_33 0x21
#define | LCD_REG_34 0x22
#define | LCD_REG_36 0x24
#define | LCD_REG_37 0x25
#define | LCD_REG_4 0x04
#define | LCD_REG_40 0x28
#define | LCD_REG_41 0x29
#define | LCD_REG_43 0x2B
#define | LCD_REG_45 0x2D
#define | LCD_REG_48 0x30
#define | LCD_REG_49 0x31
#define | LCD_REG_5 0x05
#define | LCD_REG_50 0x32
#define | LCD_REG_51 0x33
#define | LCD_REG_52 0x34
#define | LCD_REG_53 0x35
#define | LCD_REG_54 0x36
#define | LCD_REG_55 0x37
#define | LCD_REG_56 0x38
#define | LCD_REG_57 0x39
#define | LCD_REG_59 0x3B
#define | LCD_REG_6 0x06
#define | LCD_REG_60 0x3C
#define | LCD_REG_61 0x3D
#define | LCD_REG_62 0x3E
#define | LCD_REG_63 0x3F
#define | LCD_REG_64 0x40
#define | LCD_REG_65 0x41
#define | LCD_REG_66 0x42
#define | LCD_REG_67 0x43
#define | LCD_REG_68 0x44
#define | LCD_REG_69 0x45
#define | LCD_REG_7 0x07
#define | LCD_REG_70 0x46
#define | LCD_REG_71 0x47
#define | LCD_REG_72 0x48
#define | LCD_REG_73 0x49
#define | LCD_REG_74 0x4A
#define | LCD_REG_75 0x4B
#define | LCD_REG_76 0x4C
#define | LCD_REG_77 0x4D
#define | LCD_REG_78 0x4E
#define | LCD_REG_79 0x4F
#define | LCD_REG_8 0x08
#define | LCD_REG_80 0x50
#define | LCD_REG_81 0x51
#define | LCD_REG_82 0x52
#define | LCD_REG_83 0x53
#define | LCD_REG_9 0x09
#define | LCD_REG_96 0x60
#define | LCD_REG_97 0x61
#define | LCD_SPI SPI1
#define | LCD_SPI_CLK RCC_APB2Periph_SPI1
#define | LCD_SPI_MISO_AF GPIO_AF_SPI1
#define | LCD_SPI_MISO_GPIO_CLK RCC_AHBPeriph_GPIOE
#define | LCD_SPI_MISO_GPIO_PORT GPIOE
#define | LCD_SPI_MISO_PIN GPIO_Pin_14
#define | LCD_SPI_MISO_SOURCE GPIO_PinSource14
#define | LCD_SPI_MOSI_AF GPIO_AF_SPI1
#define | LCD_SPI_MOSI_GPIO_CLK RCC_AHBPeriph_GPIOE
#define | LCD_SPI_MOSI_GPIO_PORT GPIOE
#define | LCD_SPI_MOSI_PIN GPIO_Pin_15
#define | LCD_SPI_MOSI_SOURCE GPIO_PinSource15
#define | LCD_SPI_SCK_AF GPIO_AF_SPI1
#define | LCD_SPI_SCK_GPIO_CLK RCC_AHBPeriph_GPIOE
#define | LCD_SPI_SCK_GPIO_PORT GPIOE
#define | LCD_SPI_SCK_PIN GPIO_Pin_13
LCD SPI Interface pins.
#define | LCD_SPI_SCK_SOURCE GPIO_PinSource13

Define Documentation

#define _delay_ delay

Uncomment the line below if you want to use LCD_DrawBMP function to display a bitmap picture on the LCD.

This function assumes that the bitmap file is loaded in the SPI Flash (mounted on STM32L152-EVAL board), however user can tailor it according to his application hardware requirement. Uncomment the line below if you want to use user defined Delay function (for precise timing), otherwise default _delay_ function defined within this driver is used (less precise timing).

Definition at line 89 of file stm32l152_eval_lcd.h.

#define LCD_COLOR_BLACK 0x0000

Definition at line 242 of file stm32l152_eval_lcd.h.

#define LCD_COLOR_BLUE 0x001F

Definition at line 244 of file stm32l152_eval_lcd.h.

#define LCD_COLOR_BLUE2 0x051F

Definition at line 245 of file stm32l152_eval_lcd.h.

#define LCD_COLOR_CYAN 0x7FFF

Definition at line 249 of file stm32l152_eval_lcd.h.

#define LCD_COLOR_GREEN 0x07E0

Definition at line 248 of file stm32l152_eval_lcd.h.

#define LCD_COLOR_GREY 0xF7DE

Definition at line 243 of file stm32l152_eval_lcd.h.

#define LCD_COLOR_MAGENTA 0xF81F

Definition at line 247 of file stm32l152_eval_lcd.h.

#define LCD_COLOR_RED 0xF800

Definition at line 246 of file stm32l152_eval_lcd.h.

#define LCD_COLOR_WHITE 0xFFFF

LCD color.

Definition at line 241 of file stm32l152_eval_lcd.h.

#define LCD_COLOR_YELLOW 0xFFE0

Definition at line 250 of file stm32l152_eval_lcd.h.

#define LCD_DEFAULT_FONT Font16x24

LCD default font.

Definition at line 290 of file stm32l152_eval_lcd.h.

#define LCD_DIR_HORIZONTAL 0x0000

LCD Direction.

Definition at line 295 of file stm32l152_eval_lcd.h.

#define LCD_DIR_VERTICAL 0x0001

Definition at line 296 of file stm32l152_eval_lcd.h.

#define LCD_LINE_0 LINE(0)

LCD Lines depending on the chosen fonts.

Definition at line 255 of file stm32l152_eval_lcd.h.

#define LCD_LINE_1 LINE(1)

Definition at line 256 of file stm32l152_eval_lcd.h.

#define LCD_LINE_10 LINE(10)

Definition at line 265 of file stm32l152_eval_lcd.h.

#define LCD_LINE_11 LINE(11)

Definition at line 266 of file stm32l152_eval_lcd.h.

#define LCD_LINE_12 LINE(12)

Definition at line 267 of file stm32l152_eval_lcd.h.

#define LCD_LINE_13 LINE(13)

Definition at line 268 of file stm32l152_eval_lcd.h.

#define LCD_LINE_14 LINE(14)

Definition at line 269 of file stm32l152_eval_lcd.h.

#define LCD_LINE_15 LINE(15)

Definition at line 270 of file stm32l152_eval_lcd.h.

#define LCD_LINE_16 LINE(16)

Definition at line 271 of file stm32l152_eval_lcd.h.

#define LCD_LINE_17 LINE(17)

Definition at line 272 of file stm32l152_eval_lcd.h.

#define LCD_LINE_18 LINE(18)

Definition at line 273 of file stm32l152_eval_lcd.h.

#define LCD_LINE_19 LINE(19)

Definition at line 274 of file stm32l152_eval_lcd.h.

#define LCD_LINE_2 LINE(2)

Definition at line 257 of file stm32l152_eval_lcd.h.

#define LCD_LINE_20 LINE(20)

Definition at line 275 of file stm32l152_eval_lcd.h.

#define LCD_LINE_21 LINE(21)

Definition at line 276 of file stm32l152_eval_lcd.h.

#define LCD_LINE_22 LINE(22)

Definition at line 277 of file stm32l152_eval_lcd.h.

#define LCD_LINE_23 LINE(23)

Definition at line 278 of file stm32l152_eval_lcd.h.

#define LCD_LINE_24 LINE(24)

Definition at line 279 of file stm32l152_eval_lcd.h.

#define LCD_LINE_25 LINE(25)

Definition at line 280 of file stm32l152_eval_lcd.h.

#define LCD_LINE_26 LINE(26)

Definition at line 281 of file stm32l152_eval_lcd.h.

#define LCD_LINE_27 LINE(27)

Definition at line 282 of file stm32l152_eval_lcd.h.

#define LCD_LINE_28 LINE(28)

Definition at line 283 of file stm32l152_eval_lcd.h.

#define LCD_LINE_29 LINE(29)

Definition at line 284 of file stm32l152_eval_lcd.h.

#define LCD_LINE_3 LINE(3)

Definition at line 258 of file stm32l152_eval_lcd.h.

#define LCD_LINE_4 LINE(4)

Definition at line 259 of file stm32l152_eval_lcd.h.

#define LCD_LINE_5 LINE(5)

Definition at line 260 of file stm32l152_eval_lcd.h.

#define LCD_LINE_6 LINE(6)

Definition at line 261 of file stm32l152_eval_lcd.h.

#define LCD_LINE_7 LINE(7)

Definition at line 262 of file stm32l152_eval_lcd.h.

#define LCD_LINE_8 LINE(8)

Definition at line 263 of file stm32l152_eval_lcd.h.

#define LCD_LINE_9 LINE(9)

Definition at line 264 of file stm32l152_eval_lcd.h.

#define LCD_NCS_GPIO_CLK RCC_AHBPeriph_GPIOH

Definition at line 98 of file stm32l152_eval_lcd.h.

#define LCD_NCS_GPIO_PORT GPIOH

Definition at line 97 of file stm32l152_eval_lcd.h.

#define LCD_NCS_PIN GPIO_Pin_2

LCD Control pins.

Definition at line 96 of file stm32l152_eval_lcd.h.

#define LCD_PIXEL_HEIGHT 0x00F0

Definition at line 302 of file stm32l152_eval_lcd.h.

#define LCD_PIXEL_WIDTH 0x0140

LCD Size (Width and Height)

Definition at line 301 of file stm32l152_eval_lcd.h.

#define LCD_REG_0 0x00

LCD Registers.

Definition at line 125 of file stm32l152_eval_lcd.h.

#define LCD_REG_1 0x01

Definition at line 126 of file stm32l152_eval_lcd.h.

#define LCD_REG_10 0x0A

Definition at line 135 of file stm32l152_eval_lcd.h.

#define LCD_REG_106 0x6A

Definition at line 202 of file stm32l152_eval_lcd.h.

#define LCD_REG_118 0x76

Definition at line 203 of file stm32l152_eval_lcd.h.

#define LCD_REG_12 0x0C

Definition at line 136 of file stm32l152_eval_lcd.h.

#define LCD_REG_128 0x80

Definition at line 204 of file stm32l152_eval_lcd.h.

#define LCD_REG_129 0x81

Definition at line 205 of file stm32l152_eval_lcd.h.

#define LCD_REG_13 0x0D

Definition at line 137 of file stm32l152_eval_lcd.h.

#define LCD_REG_130 0x82

Definition at line 206 of file stm32l152_eval_lcd.h.

#define LCD_REG_131 0x83

Definition at line 207 of file stm32l152_eval_lcd.h.

#define LCD_REG_132 0x84

Definition at line 208 of file stm32l152_eval_lcd.h.

#define LCD_REG_133 0x85

Definition at line 209 of file stm32l152_eval_lcd.h.

#define LCD_REG_134 0x86

Definition at line 210 of file stm32l152_eval_lcd.h.

#define LCD_REG_135 0x87

Definition at line 211 of file stm32l152_eval_lcd.h.

#define LCD_REG_136 0x88

Definition at line 212 of file stm32l152_eval_lcd.h.

#define LCD_REG_137 0x89

Definition at line 213 of file stm32l152_eval_lcd.h.

#define LCD_REG_139 0x8B

Definition at line 214 of file stm32l152_eval_lcd.h.

#define LCD_REG_14 0x0E

Definition at line 138 of file stm32l152_eval_lcd.h.

#define LCD_REG_140 0x8C

Definition at line 215 of file stm32l152_eval_lcd.h.

#define LCD_REG_141 0x8D

Definition at line 216 of file stm32l152_eval_lcd.h.

#define LCD_REG_143 0x8F

Definition at line 217 of file stm32l152_eval_lcd.h.

#define LCD_REG_144 0x90

Definition at line 218 of file stm32l152_eval_lcd.h.

#define LCD_REG_145 0x91

Definition at line 219 of file stm32l152_eval_lcd.h.

#define LCD_REG_146 0x92

Definition at line 220 of file stm32l152_eval_lcd.h.

#define LCD_REG_147 0x93

Definition at line 221 of file stm32l152_eval_lcd.h.

#define LCD_REG_148 0x94

Definition at line 222 of file stm32l152_eval_lcd.h.

#define LCD_REG_149 0x95

Definition at line 223 of file stm32l152_eval_lcd.h.

#define LCD_REG_15 0x0F

Definition at line 139 of file stm32l152_eval_lcd.h.

#define LCD_REG_150 0x96

Definition at line 224 of file stm32l152_eval_lcd.h.

#define LCD_REG_151 0x97

Definition at line 225 of file stm32l152_eval_lcd.h.

#define LCD_REG_152 0x98

Definition at line 226 of file stm32l152_eval_lcd.h.

#define LCD_REG_153 0x99

Definition at line 227 of file stm32l152_eval_lcd.h.

#define LCD_REG_154 0x9A

Definition at line 228 of file stm32l152_eval_lcd.h.

#define LCD_REG_157 0x9D

Definition at line 229 of file stm32l152_eval_lcd.h.

#define LCD_REG_16 0x10

Definition at line 140 of file stm32l152_eval_lcd.h.

#define LCD_REG_17 0x11

Definition at line 141 of file stm32l152_eval_lcd.h.

#define LCD_REG_18 0x12

Definition at line 142 of file stm32l152_eval_lcd.h.

#define LCD_REG_19 0x13

Definition at line 143 of file stm32l152_eval_lcd.h.

#define LCD_REG_192 0xC0

Definition at line 230 of file stm32l152_eval_lcd.h.

#define LCD_REG_193 0xC1

Definition at line 231 of file stm32l152_eval_lcd.h.

#define LCD_REG_2 0x02

Definition at line 127 of file stm32l152_eval_lcd.h.

#define LCD_REG_20 0x14

Definition at line 144 of file stm32l152_eval_lcd.h.

#define LCD_REG_21 0x15

Definition at line 145 of file stm32l152_eval_lcd.h.

#define LCD_REG_22 0x16

Definition at line 146 of file stm32l152_eval_lcd.h.

#define LCD_REG_227 0xE3

Definition at line 232 of file stm32l152_eval_lcd.h.

#define LCD_REG_229 0xE5

Definition at line 233 of file stm32l152_eval_lcd.h.

#define LCD_REG_23 0x17

Definition at line 147 of file stm32l152_eval_lcd.h.

#define LCD_REG_231 0xE7

Definition at line 234 of file stm32l152_eval_lcd.h.

#define LCD_REG_239 0xEF

Definition at line 235 of file stm32l152_eval_lcd.h.

#define LCD_REG_24 0x18

Definition at line 148 of file stm32l152_eval_lcd.h.

#define LCD_REG_25 0x19

Definition at line 149 of file stm32l152_eval_lcd.h.

#define LCD_REG_26 0x1A

Definition at line 150 of file stm32l152_eval_lcd.h.

#define LCD_REG_27 0x1B

Definition at line 151 of file stm32l152_eval_lcd.h.

#define LCD_REG_28 0x1C

Definition at line 152 of file stm32l152_eval_lcd.h.

#define LCD_REG_29 0x1D

Definition at line 153 of file stm32l152_eval_lcd.h.

#define LCD_REG_3 0x03

Definition at line 128 of file stm32l152_eval_lcd.h.

#define LCD_REG_30 0x1E

Definition at line 154 of file stm32l152_eval_lcd.h.

#define LCD_REG_31 0x1F

Definition at line 155 of file stm32l152_eval_lcd.h.

#define LCD_REG_32 0x20

Definition at line 156 of file stm32l152_eval_lcd.h.

#define LCD_REG_33 0x21

Definition at line 157 of file stm32l152_eval_lcd.h.

#define LCD_REG_34 0x22

Definition at line 158 of file stm32l152_eval_lcd.h.

#define LCD_REG_36 0x24

Definition at line 159 of file stm32l152_eval_lcd.h.

#define LCD_REG_37 0x25

Definition at line 160 of file stm32l152_eval_lcd.h.

#define LCD_REG_4 0x04

Definition at line 129 of file stm32l152_eval_lcd.h.

#define LCD_REG_40 0x28

Definition at line 161 of file stm32l152_eval_lcd.h.

#define LCD_REG_41 0x29

Definition at line 162 of file stm32l152_eval_lcd.h.

#define LCD_REG_43 0x2B

Definition at line 163 of file stm32l152_eval_lcd.h.

#define LCD_REG_45 0x2D

Definition at line 164 of file stm32l152_eval_lcd.h.

#define LCD_REG_48 0x30

Definition at line 165 of file stm32l152_eval_lcd.h.

#define LCD_REG_49 0x31

Definition at line 166 of file stm32l152_eval_lcd.h.

#define LCD_REG_5 0x05

Definition at line 130 of file stm32l152_eval_lcd.h.

#define LCD_REG_50 0x32

Definition at line 167 of file stm32l152_eval_lcd.h.

#define LCD_REG_51 0x33

Definition at line 168 of file stm32l152_eval_lcd.h.

#define LCD_REG_52 0x34

Definition at line 169 of file stm32l152_eval_lcd.h.

#define LCD_REG_53 0x35

Definition at line 170 of file stm32l152_eval_lcd.h.

#define LCD_REG_54 0x36

Definition at line 171 of file stm32l152_eval_lcd.h.

#define LCD_REG_55 0x37

Definition at line 172 of file stm32l152_eval_lcd.h.

#define LCD_REG_56 0x38

Definition at line 173 of file stm32l152_eval_lcd.h.

#define LCD_REG_57 0x39

Definition at line 174 of file stm32l152_eval_lcd.h.

#define LCD_REG_59 0x3B

Definition at line 175 of file stm32l152_eval_lcd.h.

#define LCD_REG_6 0x06

Definition at line 131 of file stm32l152_eval_lcd.h.

#define LCD_REG_60 0x3C

Definition at line 176 of file stm32l152_eval_lcd.h.

#define LCD_REG_61 0x3D

Definition at line 177 of file stm32l152_eval_lcd.h.

#define LCD_REG_62 0x3E

Definition at line 178 of file stm32l152_eval_lcd.h.

#define LCD_REG_63 0x3F

Definition at line 179 of file stm32l152_eval_lcd.h.

#define LCD_REG_64 0x40

Definition at line 180 of file stm32l152_eval_lcd.h.

#define LCD_REG_65 0x41

Definition at line 181 of file stm32l152_eval_lcd.h.

#define LCD_REG_66 0x42

Definition at line 182 of file stm32l152_eval_lcd.h.

#define LCD_REG_67 0x43

Definition at line 183 of file stm32l152_eval_lcd.h.

#define LCD_REG_68 0x44

Definition at line 184 of file stm32l152_eval_lcd.h.

#define LCD_REG_69 0x45

Definition at line 185 of file stm32l152_eval_lcd.h.

#define LCD_REG_7 0x07

Definition at line 132 of file stm32l152_eval_lcd.h.

#define LCD_REG_70 0x46

Definition at line 186 of file stm32l152_eval_lcd.h.

#define LCD_REG_71 0x47

Definition at line 187 of file stm32l152_eval_lcd.h.

#define LCD_REG_72 0x48

Definition at line 188 of file stm32l152_eval_lcd.h.

#define LCD_REG_73 0x49

Definition at line 189 of file stm32l152_eval_lcd.h.

#define LCD_REG_74 0x4A

Definition at line 190 of file stm32l152_eval_lcd.h.

#define LCD_REG_75 0x4B

Definition at line 191 of file stm32l152_eval_lcd.h.

#define LCD_REG_76 0x4C

Definition at line 192 of file stm32l152_eval_lcd.h.

#define LCD_REG_77 0x4D

Definition at line 193 of file stm32l152_eval_lcd.h.

#define LCD_REG_78 0x4E

Definition at line 194 of file stm32l152_eval_lcd.h.

#define LCD_REG_79 0x4F

Definition at line 195 of file stm32l152_eval_lcd.h.

#define LCD_REG_8 0x08

Definition at line 133 of file stm32l152_eval_lcd.h.

#define LCD_REG_80 0x50

Definition at line 196 of file stm32l152_eval_lcd.h.

#define LCD_REG_81 0x51

Definition at line 197 of file stm32l152_eval_lcd.h.

#define LCD_REG_82 0x52

Definition at line 198 of file stm32l152_eval_lcd.h.

#define LCD_REG_83 0x53

Definition at line 199 of file stm32l152_eval_lcd.h.

#define LCD_REG_9 0x09

Definition at line 134 of file stm32l152_eval_lcd.h.

#define LCD_REG_96 0x60

Definition at line 200 of file stm32l152_eval_lcd.h.

#define LCD_REG_97 0x61

Definition at line 201 of file stm32l152_eval_lcd.h.

#define LCD_SPI SPI1

Definition at line 118 of file stm32l152_eval_lcd.h.

#define LCD_SPI_CLK RCC_APB2Periph_SPI1

Definition at line 119 of file stm32l152_eval_lcd.h.

#define LCD_SPI_MISO_AF GPIO_AF_SPI1

Definition at line 112 of file stm32l152_eval_lcd.h.

Referenced by LCD_SPIConfig().

#define LCD_SPI_MISO_GPIO_CLK RCC_AHBPeriph_GPIOE

Definition at line 110 of file stm32l152_eval_lcd.h.

#define LCD_SPI_MISO_GPIO_PORT GPIOE

Definition at line 109 of file stm32l152_eval_lcd.h.

#define LCD_SPI_MISO_PIN GPIO_Pin_14

Definition at line 108 of file stm32l152_eval_lcd.h.

#define LCD_SPI_MISO_SOURCE GPIO_PinSource14

Definition at line 111 of file stm32l152_eval_lcd.h.

Referenced by LCD_SPIConfig().

#define LCD_SPI_MOSI_AF GPIO_AF_SPI1

Definition at line 117 of file stm32l152_eval_lcd.h.

Referenced by LCD_SPIConfig().

#define LCD_SPI_MOSI_GPIO_CLK RCC_AHBPeriph_GPIOE

Definition at line 115 of file stm32l152_eval_lcd.h.

#define LCD_SPI_MOSI_GPIO_PORT GPIOE

Definition at line 114 of file stm32l152_eval_lcd.h.

#define LCD_SPI_MOSI_PIN GPIO_Pin_15

Definition at line 113 of file stm32l152_eval_lcd.h.

#define LCD_SPI_MOSI_SOURCE GPIO_PinSource15

Definition at line 116 of file stm32l152_eval_lcd.h.

Referenced by LCD_SPIConfig().

#define LCD_SPI_SCK_AF GPIO_AF_SPI1

Definition at line 107 of file stm32l152_eval_lcd.h.

Referenced by LCD_SPIConfig().

#define LCD_SPI_SCK_GPIO_CLK RCC_AHBPeriph_GPIOE

Definition at line 105 of file stm32l152_eval_lcd.h.

#define LCD_SPI_SCK_GPIO_PORT GPIOE

Definition at line 104 of file stm32l152_eval_lcd.h.

#define LCD_SPI_SCK_PIN GPIO_Pin_13

LCD SPI Interface pins.

Definition at line 103 of file stm32l152_eval_lcd.h.

#define LCD_SPI_SCK_SOURCE GPIO_PinSource13

Definition at line 106 of file stm32l152_eval_lcd.h.

Referenced by LCD_SPIConfig().


STM32F10x Standard Peripherals Firmware Library: STM32L152_EVAL_LCD_Exported_Macros

Defines

STM32L152_EVAL_LCD_Exported_Macros

STM32L152_EVAL_LCD

Defines

#define ASSEMBLE_RGB(R, G, B) ((((R)& 0xF8) << 8) | (((G) & 0xFC) << 3) | (((B) & 0xF8) >> 3))

Define Documentation

#define ASSEMBLE_RGB | ( | R,
 |  | G,
 |  | B
 | ) | ((((R)& 0xF8) << 8) | (((G) & 0xFC) << 3) | (((B) & 0xF8) >> 3))

Definition at line 311 of file stm32l152_eval_lcd.h.


STM32F10x Standard Peripherals Firmware Library: STM32L152_EVAL_LCD_Exported_Functions

Functions

STM32L152_EVAL_LCD_Exported_Functions

STM32L152_EVAL_LCD

Functions

void | LCD_Clear (uint16_t Color)
Clears the hole LCD.
void | LCD_ClearLine (uint8_t Line)
Clears the selected line.
void | LCD_ClosedPolyLine (pPoint Points, uint16_t PointCount)
Displays a closed polyline (between many points).
void | LCD_ClosedPolyLineRelative (pPoint Points, uint16_t PointCount)
Displays a closed relative polyline (between many points).
void | LCD_CtrlLinesConfig (void)
Configures LCD control lines in Output Push-Pull mode.
void | LCD_CtrlLinesWrite (GPIO_TypeDef *GPIOx, uint16_t CtrlPins, BitAction BitVal)
Sets or reset LCD control lines.
void | LCD_DisplayChar (uint8_t Line, uint16_t Column, uint8_t Ascii)
Displays one character (16dots width, 24dots height).
void | LCD_DisplayOff (void)
Disables the Display.
void | LCD_DisplayOn (void)
Enables the Display.
void | LCD_DisplayStringLine (uint8_t Line, uint8_t *ptr)
Displays a maximum of 20 char on the LCD.
void | LCD_DrawBMP (uint32_t BmpAddress)
void | LCD_DrawChar (uint8_t Xpos, uint16_t Ypos, const uint16_t *c)
Draws a character on LCD.
void | LCD_DrawCircle (uint8_t Xpos, uint16_t Ypos, uint16_t Radius)
Displays a circle.
void | LCD_DrawFullCircle (uint16_t Xpos, uint16_t Ypos, uint16_t Radius)
Displays a full circle.
void | LCD_DrawFullRect (uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height)
Displays a full rectangle.
void | LCD_DrawLine (uint8_t Xpos, uint16_t Ypos, uint16_t Length, uint8_t Direction)
Displays a line.
void | LCD_DrawMonoPict (const uint32_t *Pict)
Displays a monocolor picture.
void | LCD_DrawRect (uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width)
Displays a rectangle.
void | LCD_DrawUniLine (uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2)
Displays an uni line (between two points).
void | LCD_FillPolyLine (pPoint Points, uint16_t PointCount)
Displays a full polyline (between many points).
void | LCD_GetColors (__IO uint16_t *_TextColor, __IO uint16_t *_BackColor)
Gets the LCD Text and Background colors.
sFONT * | LCD_GetFont (void)
Gets the Text Font.
void | LCD_nCS_StartByte (uint8_t Start_Byte)
Reset LCD control line(/CS) and Send Start-Byte.
void | LCD_PolyLine (pPoint Points, uint16_t PointCount)
Displays an polyline (between many points).
void | LCD_PolyLineRelative (pPoint Points, uint16_t PointCount)
Displays a relative polyline (between many points).
void | LCD_PowerOn (void)
Power on the LCD.
uint16_t | LCD_ReadReg (uint8_t LCD_Reg)
Reads the selected LCD Register.
void | LCD_SetBackColor (__IO uint16_t Color)
Sets the Background color.
void | LCD_SetColors (__IO uint16_t _TextColor, __IO uint16_t _BackColor)
Sets the LCD Text and Background colors.
void | LCD_SetCursor (uint8_t Xpos, uint16_t Ypos)
Sets the cursor position.
void | LCD_SetDisplayWindow (uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width)
Sets a display window.
void | LCD_SetFont (sFONT *fonts)
Sets the Text Font.
void | LCD_SetTextColor (__IO uint16_t Color)
Sets the Text color.
void | LCD_Setup (void)
Setups the LCD.
void | LCD_SPIConfig (void)
Configures the LCD_SPI interface.
void | LCD_WindowModeDisable (void)
Disables LCD Window mode.
void | LCD_WriteRAM (uint16_t RGB_Code)
Writes to the LCD RAM.
void | LCD_WriteRAM_Prepare (void)
Prepare to write to the LCD RAM.
void | LCD_WriteRAMWord (uint16_t RGB_Code)
Writes 1 word to the LCD RAM.
void | LCD_WriteReg (uint8_t LCD_Reg, uint16_t LCD_RegValue)
Writes to the selected LCD register.
void | LCD_WriteRegIndex (uint8_t LCD_Reg)
Writes index to select the LCD register.
void | STM32L152_LCD_DeInit (void)
DeInitializes the LCD.
void | STM32L152_LCD_Init (void)
Initializes the LCD.

Function Documentation

void LCD_Clear ( uint16_t Color )

Clears the hole LCD.

Parameters:
Color,: the color of the background.
Return values:
None

Definition at line 544 of file stm32100b_eval_lcd.c.

References Bit_SET, index, LCD, LCD_CtrlLinesWrite(), LCD_ILI9320, LCD_NCS_GPIO_PORT, LCD_NCS_PIN, LCD_SetCursor(), LCD_SPFD5408, LCD_WriteRAM(), LCD_WriteRAM_Prepare(), and LCDType.

Referenced by main(), and sEE_TIMEOUT_UserCallback().

void LCD_ClearLine ( uint8_t Line )

Clears the selected line.

Parameters:
Line,: the Line to be cleared. This parameter can be one of the following values:

  • Linex: where x can be 0..n
Return values:
None

Definition at line 525 of file stm32100b_eval_lcd.c.

References LCD_DisplayChar(), LCD_PIXEL_WIDTH, and _tFont::Width.

Referenced by main().

void LCD_ClosedPolyLine | ( | pPoint | Points,
 |  | uint16_t | PointCount
 | ) |  |

Displays a closed polyline (between many points).

Parameters:
Points,: pointer to the points array.
PointCount,: Number of points.
Return values:
None

Definition at line 1236 of file stm32100b_eval_lcd.c.

References LCD_DrawUniLine(), LCD_PolyLine(), Point::X, and Point::Y.

void LCD_ClosedPolyLineRelative | ( | pPoint | Points,
 |  | uint16_t | PointCount
 | ) |  |

Displays a closed relative polyline (between many points).

Parameters:
Points,: pointer to the points array.
PointCount,: Number of points.
Return values:
None

Definition at line 1259 of file stm32100b_eval_lcd.c.

References LCD_PolyLineRelativeClosed().

void LCD_CtrlLinesConfig ( void )

Configures LCD control lines in Output Push-Pull mode.

Parameters:
None
Return values:
None Configures LCD control lines in Output Push-Pull mode.
Parameters:
None
Return values:
None

Definition at line 1724 of file stm32100b_eval_lcd.c.

References Bit_SET, ENABLE, GPIO_Init(), GPIO_InitStructure, GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_AF_PP, GPIO_Mode_Out_PP, GPIO_InitTypeDef::GPIO_Pin, GPIO_Pin_0, GPIO_Pin_1, GPIO_Pin_10, GPIO_Pin_11, GPIO_Pin_12, GPIO_Pin_13, GPIO_Pin_14, GPIO_Pin_15, GPIO_Pin_4, GPIO_Pin_5, GPIO_Pin_7, GPIO_Pin_8, GPIO_Pin_9, GPIO_InitTypeDef::GPIO_Speed, GPIO_Speed_2MHz, GPIO_Speed_50MHz, GPIOD, GPIOE, GPIOF, GPIOG, LCD_CtrlLinesWrite(), LCD_NCS_GPIO_CLK, LCD_NCS_GPIO_PORT, LCD_NCS_PIN, LCD_NWR_GPIO_CLK, LCD_NWR_GPIO_PORT, LCD_NWR_PIN, LCD_RS_GPIO_CLK, LCD_RS_GPIO_PORT, LCD_RS_PIN, RCC_AHBPeriph_FSMC, RCC_AHBPeriphClockCmd(), RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE, RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, and RCC_APB2PeriphClockCmd().

Referenced by LCD_Setup(), STM32100E_LCD_Init(), and STM3210E_LCD_Init().

void LCD_CtrlLinesWrite | ( | GPIO_TypeDef * | GPIOx,
 |  | uint16_t | CtrlPins,
 |  | BitAction | BitVal
 | ) |  |

Sets or reset LCD control lines.

Parameters:
GPIOx,: where x can be B or D to select the GPIO peripheral.
CtrlPins,: the Control line. This parameter can be:

  • LCD_NCS_PIN: Chip Select pin
  • LCD_NWR_PIN: Read/Write Selection pin
  • LCD_RS_PIN: Register/RAM Selection pin
BitVal,: specifies the value to be written to the selected bit. This parameter can be:

  • Bit_RESET: to clear the port pin
  • Bit_SET: to set the port pin
Return values:
None
Parameters:
GPIOx,: where x can be B or D to select the GPIO peripheral.
CtrlPins,: the Control line. This parameter can be:

  • LCD_NCS_PIN: Chip Select pin
BitVal,: specifies the value to be written to the selected bit. This parameter can be:

  • Bit_RESET: to clear the port pin
  • Bit_SET: to set the port pin
Return values:
None

Definition at line 1763 of file stm32100b_eval_lcd.c.

References GPIO_WriteBit().

Referenced by LCD_Clear(), LCD_CtrlLinesConfig(), LCD_DrawChar(), LCD_DrawLine(), LCD_DrawMonoPict(), LCD_nCS_StartByte(), LCD_ReadReg(), LCD_WriteRAM(), LCD_WriteRAMWord(), LCD_WriteReg(), LCD_WriteRegHX8312(), LCD_WriteRegILI9320(), and LCD_WriteRegIndex().

void LCD_DisplayChar | ( | uint8_t | Line,
 |  | uint16_t | Column,
 |  | uint8_t | Ascii
 | ) |  |

Displays one character (16dots width, 24dots height).

Parameters:
Line,: the Line where to display the character shape . This parameter can be one of the following values:

  • Linex: where x can be 0..9
Column,: start column address.
Ascii,: character ascii code, must be between 0x20 and 0x7E.
Return values:
None

Definition at line 640 of file stm32100b_eval_lcd.c.

References _tFont::Height, LCD_DrawChar(), and _tFont::table.

Referenced by LCD_ClearLine(), LCD_DisplayStringLine(), and main().

void LCD_DisplayOff ( void )

Disables the Display.

Parameters:
None
Return values:
None

Definition at line 1702 of file stm32100b_eval_lcd.c.

References _delay_, LCD_HX8312, LCD_ILI9320, LCD_REG_0, LCD_REG_59, LCD_REG_7, LCD_SPFD5408, LCD_WriteReg(), and LCDType.

Referenced by LCD_DeInit(), and STM32L152_LCD_DeInit().

void LCD_DisplayOn ( void )

Enables the Display.

Parameters:
None
Return values:
None

Definition at line 1677 of file stm32100b_eval_lcd.c.

References _delay_, LCD_HX8312, LCD_ILI9320, LCD_REG_0, LCD_REG_1, LCD_REG_5, LCD_REG_59, LCD_REG_7, LCD_SPFD5408, LCD_WriteReg(), and LCDType.

void LCD_DisplayStringLine | ( | uint8_t | Line,
 |  | uint8_t * | ptr
 | ) |  |

Displays a maximum of 20 char on the LCD.

Parameters:
Line,: the Line where to display the character shape . This parameter can be one of the following values:

  • Linex: where x can be 0..9
*ptr,: pointer to string to display on LCD.
Return values:
None

Definition at line 655 of file stm32100b_eval_lcd.c.

References LCD_DisplayChar(), LCD_PIXEL_WIDTH, and _tFont::Width.

Referenced by EXTI15_10_IRQHandler(), LED_Display(), main(), and sEE_TIMEOUT_UserCallback().

void LCD_DrawBMP ( uint32_t BmpAddress )
void LCD_DrawChar | ( | uint8_t | Xpos,
 |  | uint16_t | Ypos,
 |  | const uint16_t * | c
 | ) |  |

Draws a character on LCD.

Parameters:
Xpos,: the Line where to display the character shape.
Ypos,: start column address.
c,: pointer to the character data.
Return values:
None

Definition at line 593 of file stm32100b_eval_lcd.c.

References BackColor, Bit_SET, _tFont::Height, index, LCD_CtrlLinesWrite(), LCD_ILI9320, LCD_NCS_GPIO_PORT, LCD_NCS_PIN, LCD_SetCursor(), LCD_SPFD5408, LCD_WriteRAM(), LCD_WriteRAM_Prepare(), LCDType, TextColor, and _tFont::Width.

Referenced by LCD_DisplayChar().

void LCD_DrawCircle | ( | uint8_t | Xpos,
 |  | uint16_t | Ypos,
 |  | uint16_t | Radius
 | ) |  |

Displays a circle.

Parameters:
Xpos,: specifies the X position.
Ypos,: specifies the Y position.
Radius
Return values:
None

Definition at line 817 of file stm32100b_eval_lcd.c.

References LCD_HX8312, LCD_ILI9320, LCD_SetCursor(), LCD_SPFD5408, LCD_WriteRAM(), LCD_WriteRAM_Prepare(), LCD_WriteRAMWord(), LCDType, and TextColor.

Referenced by LCD_DrawFullCircle().

void LCD_DrawFullCircle | ( | uint16_t | Xpos,
 |  | uint16_t | Ypos,
 |  | uint16_t | Radius
 | ) |  |

Displays a full circle.

Parameters:
Xpos,: specifies the X position.
Ypos,: specifies the Y position.
Radius
Return values:
None

Definition at line 1057 of file stm32100b_eval_lcd.c.

References BackColor, LCD_DIR_HORIZONTAL, LCD_DrawCircle(), LCD_DrawLine(), LCD_SetTextColor(), and TextColor.

void LCD_DrawFullRect | ( | uint16_t | Xpos,
 |  | uint16_t | Ypos,
 |  | uint16_t | Width,
 |  | uint16_t | Height
 | ) |  |

Displays a full rectangle.

Parameters:
Xpos,: specifies the X position.
Ypos,: specifies the Y position.
Height,: rectangle height.
Width,: rectangle width.
Return values:
None

Definition at line 1026 of file stm32100b_eval_lcd.c.

References BackColor, LCD_DIR_HORIZONTAL, LCD_DIR_VERTICAL, LCD_DrawLine(), LCD_SetTextColor(), and TextColor.

void LCD_DrawLine | ( | uint8_t | Xpos,
 |  | uint16_t | Ypos,
 |  | uint16_t | Length,
 |  | uint8_t | Direction
 | ) |  |

Displays a line.

Parameters:
Xpos,: specifies the X position.
Ypos,: specifies the Y position.
Length,: line length.
Direction,: line direction. This parameter can be one of the following values: Vertical or Horizontal.
Return values:
None

Definition at line 753 of file stm32100b_eval_lcd.c.

References Bit_SET, LCD_CtrlLinesWrite(), LCD_DIR_HORIZONTAL, LCD_HX8312, LCD_ILI9320, LCD_NCS_GPIO_PORT, LCD_NCS_PIN, LCD_SetCursor(), LCD_SPFD5408, LCD_WriteRAM(), LCD_WriteRAM_Prepare(), LCD_WriteRAMWord(), LCDType, and TextColor.

Referenced by LCD_DrawFullCircle(), LCD_DrawFullRect(), LCD_DrawRect(), LCD_FillPolyLine(), and PutPixel().

void LCD_DrawMonoPict ( const uint32_t * Pict )

Displays a monocolor picture.

Parameters:
Pict,: pointer to the picture array.
Return values:
None

Definition at line 926 of file stm32100b_eval_lcd.c.

References BackColor, Bit_SET, index, LCD_CtrlLinesWrite(), LCD_ILI9320, LCD_NCS_GPIO_PORT, LCD_NCS_PIN, LCD_PIXEL_WIDTH, LCD_SetCursor(), LCD_SPFD5408, LCD_WriteRAM(), LCD_WriteRAM_Prepare(), LCDType, and TextColor.

void LCD_DrawRect | ( | uint8_t | Xpos,
 |  | uint16_t | Ypos,
 |  | uint8_t | Height,
 |  | uint16_t | Width
 | ) |  |

Displays a rectangle.

Parameters:
Xpos,: specifies the X position.
Ypos,: specifies the Y position.
Height,: display rectangle height.
Width,: display rectangle width.
Return values:
None

Definition at line 800 of file stm32100b_eval_lcd.c.

References LCD_DIR_HORIZONTAL, LCD_DIR_VERTICAL, and LCD_DrawLine().

Referenced by main().

void LCD_DrawUniLine | ( | uint16_t | x1,
 |  | uint16_t | y1,
 |  | uint16_t | x2,
 |  | uint16_t | y2
 | ) |  |

Displays an uni line (between two points).

Parameters:
x1,: specifies the point 1 x position.
y1,: specifies the point 1 y position.
x2,: specifies the point 2 x position.
y2,: specifies the point 2 y position.
Return values:
None

Definition at line 1107 of file stm32100b_eval_lcd.c.

References ABS, and PutPixel().

Referenced by LCD_ClosedPolyLine(), LCD_PolyLine(), and LCD_PolyLineRelativeClosed().

void LCD_FillPolyLine | ( | pPoint | Points,
 |  | uint16_t | PointCount
 | ) |  |

Displays a full polyline (between many points).

Parameters:
Points,: pointer to the points array.
PointCount,: Number of points.
Return values:
None

Definition at line 1271 of file stm32100b_eval_lcd.c.

References BackColor, j, LCD_DIR_HORIZONTAL, LCD_DrawLine(), LCD_SetTextColor(), MAX_POLY_CORNERS, POLY_X, POLY_Y, PutPixel(), TextColor, Point::X, and Point::Y.

void LCD_GetColors | ( | __IO uint16_t * | _TextColor,
 |  | __IO uint16_t * | _BackColor
 | ) |  |

Gets the LCD Text and Background colors.

Parameters:
_TextColor,: pointer to the variable that will contain the Text Color.
_BackColor,: pointer to the variable that will contain the Background Color.
Return values:
None

Definition at line 472 of file stm32100b_eval_lcd.c.

References BackColor, and TextColor.

sFONT* LCD_GetFont ( void )

Gets the Text Font.

Parameters:
None.
Return values:
the used font.

Definition at line 513 of file stm32100b_eval_lcd.c.

References LCD_Currentfonts.

void LCD_nCS_StartByte ( uint8_t Start_Byte )

Reset LCD control line(/CS) and Send Start-Byte.

Parameters:
Start_Byte,: the Start-Byte to be sent
Return values:
None

Definition at line 1377 of file stm32100b_eval_lcd.c.

References Bit_RESET, LCD_CtrlLinesWrite(), LCD_NCS_GPIO_PORT, LCD_NCS_PIN, LCD_SPI, RESET, SPI_I2S_FLAG_BSY, SPI_I2S_GetFlagStatus(), and SPI_I2S_SendData().

Referenced by LCD_ReadReg(), LCD_WriteRAM_Prepare(), LCD_WriteReg(), LCD_WriteRegILI9320(), and LCD_WriteRegIndex().

void LCD_PolyLine | ( | pPoint | Points,
 |  | uint16_t | PointCount
 | ) |  |

Displays an polyline (between many points).

Parameters:
Points,: pointer to the points array.
PointCount,: Number of points.
Return values:
None

Definition at line 1180 of file stm32100b_eval_lcd.c.

References LCD_DrawUniLine(), Point::X, and Point::Y.

Referenced by LCD_ClosedPolyLine().

void LCD_PolyLineRelative | ( | pPoint | Points,
 |  | uint16_t | PointCount
 | ) |  |

Displays a relative polyline (between many points).

Parameters:
Points,: pointer to the points array.
PointCount,: Number of points.
Return values:
None

Definition at line 1248 of file stm32100b_eval_lcd.c.

References LCD_PolyLineRelativeClosed().

void LCD_PowerOn ( void )

Power on the LCD.

Parameters:
None
Return values:
None

Definition at line 1629 of file stm32100b_eval_lcd.c.

References _delay_, LCD_HX8312, LCD_ILI9320, LCD_REG_16, LCD_REG_17, LCD_REG_18, LCD_REG_19, LCD_REG_24, LCD_REG_27, LCD_REG_28, LCD_REG_30, LCD_REG_31, LCD_REG_32, LCD_REG_36, LCD_REG_41, LCD_REG_7, LCD_SPFD5408, LCD_WriteReg(), and LCDType.

uint16_t LCD_ReadReg ( uint8_t LCD_Reg )

Reads the selected LCD Register.

Parameters:
LCD_Reg,: address of the selected register.
Return values:
LCD Register Value.
Parameters:
None
Return values:
LCD Register Value.

Definition at line 1452 of file stm32100b_eval_lcd.c.

References Bit_SET, LCD, LCD_CtrlLinesWrite(), LCD_NCS_GPIO_PORT, LCD_NCS_PIN, LCD_nCS_StartByte(), LCD_READ_REG, LCD_SPI, LCD_WriteRegIndex(), RESET, SPI_I2S_FLAG_BSY, SPI_I2S_FLAG_RXNE, SPI_I2S_GetFlagStatus(), SPI_I2S_ReceiveData(), SPI_I2S_SendData(), and START_BYTE.

Referenced by STM32100B_LCD_Init(), STM32100E_LCD_Init(), STM3210B_LCD_Init(), STM3210E_LCD_Init(), and STM32L152_LCD_Init().

void LCD_SetBackColor ( __IO uint16_t Color )

Sets the Background color.

Parameters:
Color,: specifies the Background color code RGB(5-6-5).
Return values:
None

Definition at line 493 of file stm32100b_eval_lcd.c.

References BackColor.

Referenced by main().

void LCD_SetColors | ( | __IO uint16_t | _TextColor,
 |  | __IO uint16_t | _BackColor
 | ) |  |

Sets the LCD Text and Background colors.

Parameters:
_TextColor,: specifies the Text Color.
_BackColor,: specifies the Background Color.
Return values:
None

Definition at line 458 of file stm32100b_eval_lcd.c.

References BackColor, and TextColor.

void LCD_SetCursor | ( | uint8_t | Xpos,
 |  | uint16_t | Ypos
 | ) |  |

Sets the cursor position.

Parameters:
Xpos,: specifies the X position.
Ypos,: specifies the Y position.
Return values:
None

Definition at line 570 of file stm32100b_eval_lcd.c.

References LCD_HX8312, LCD_ILI9320, LCD_REG_32, LCD_REG_33, LCD_REG_66, LCD_REG_67, LCD_REG_68, LCD_SPFD5408, LCD_WriteReg(), and LCDType.

Referenced by LCD_Clear(), LCD_DrawChar(), LCD_DrawCircle(), LCD_DrawLine(), LCD_DrawMonoPict(), and LCD_SetDisplayWindow().

void LCD_SetDisplayWindow | ( | uint8_t | Xpos,
 |  | uint16_t | Ypos,
 |  | uint8_t | Height,
 |  | uint16_t | Width
 | ) |  |

Sets a display window.

Parameters:
Xpos,: specifies the X buttom left position.
Ypos,: specifies the Y buttom left position.
Height,: display window height.
Width,: display window width.
Return values:
None

Definition at line 680 of file stm32100b_eval_lcd.c.

References LCD_HX8312, LCD_ILI9320, LCD_REG_1, LCD_REG_5, LCD_REG_69, LCD_REG_70, LCD_REG_71, LCD_REG_72, LCD_REG_73, LCD_REG_74, LCD_REG_80, LCD_REG_81, LCD_REG_82, LCD_REG_83, LCD_SetCursor(), LCD_SPFD5408, LCD_WriteReg(), and LCDType.

Referenced by LCD_WindowModeDisable().

void LCD_SetFont ( sFONT * fonts )

Sets the Text Font.

Parameters:
fonts,: specifies the font to be used.
Return values:
None

Definition at line 503 of file stm32100b_eval_lcd.c.

Referenced by main(), STM32100B_LCD_Init(), STM32100E_LCD_Init(), STM3210B_LCD_Init(), STM3210C_LCD_Init(), STM3210E_LCD_Init(), and STM32L152_LCD_Init().

void LCD_SetTextColor ( __IO uint16_t Color )

Sets the Text color.

Parameters:
Color,: specifies the Text color code RGB(5-6-5).
Return values:
None

Definition at line 482 of file stm32100b_eval_lcd.c.

References TextColor.

Referenced by LCD_DrawFullCircle(), LCD_DrawFullRect(), LCD_FillPolyLine(), and main().

void LCD_Setup ( void )

Setups the LCD.

Parameters:
None
Return values:
None

Definition at line 160 of file stm32100b_eval_lcd.c.

References _delay_, LCD_CtrlLinesConfig(), LCD_HX8312, LCD_ILI9320, LCD_REG_0, LCD_REG_1, LCD_REG_10, LCD_REG_106, LCD_REG_118, LCD_REG_12, LCD_REG_128, LCD_REG_129, LCD_REG_13, LCD_REG_130, LCD_REG_131, LCD_REG_132, LCD_REG_133, LCD_REG_134, LCD_REG_135, LCD_REG_136, LCD_REG_137, LCD_REG_139, LCD_REG_14, LCD_REG_141, LCD_REG_143, LCD_REG_144, LCD_REG_145, LCD_REG_146, LCD_REG_147, LCD_REG_148, LCD_REG_149, LCD_REG_15, LCD_REG_150, LCD_REG_151, LCD_REG_152, LCD_REG_153, LCD_REG_154, LCD_REG_157, LCD_REG_16, LCD_REG_17, LCD_REG_18, LCD_REG_19, LCD_REG_192, LCD_REG_2, LCD_REG_20, LCD_REG_21, LCD_REG_22, LCD_REG_227, LCD_REG_229, LCD_REG_23, LCD_REG_231, LCD_REG_239, LCD_REG_24, LCD_REG_25, LCD_REG_26, LCD_REG_27, LCD_REG_28, LCD_REG_29, LCD_REG_3, LCD_REG_30, LCD_REG_31, LCD_REG_32, LCD_REG_33, LCD_REG_36, LCD_REG_37, LCD_REG_4, LCD_REG_40, LCD_REG_41, LCD_REG_43, LCD_REG_48, LCD_REG_49, LCD_REG_5, LCD_REG_50, LCD_REG_51, LCD_REG_52, LCD_REG_53, LCD_REG_54, LCD_REG_55, LCD_REG_56, LCD_REG_57, LCD_REG_59, LCD_REG_60, LCD_REG_61, LCD_REG_62, LCD_REG_63, LCD_REG_64, LCD_REG_65, LCD_REG_66, LCD_REG_67, LCD_REG_68, LCD_REG_69, LCD_REG_7, LCD_REG_70, LCD_REG_71, LCD_REG_72, LCD_REG_73, LCD_REG_74, LCD_REG_75, LCD_REG_76, LCD_REG_78, LCD_REG_79, LCD_REG_8, LCD_REG_80, LCD_REG_81, LCD_REG_82, LCD_REG_83, LCD_REG_9, LCD_REG_96, LCD_REG_97, LCD_SPFD5408, LCD_SPIConfig(), LCD_WriteReg(), and LCDType.

Referenced by STM32100B_LCD_Init(), STM3210B_LCD_Init(), STM3210C_LCD_Init(), and STM32L152_LCD_Init().

void LCD_SPIConfig ( void )

Configures the LCD_SPI interface.

Parameters:
None
Return values:
None

Definition at line 1775 of file stm32100b_eval_lcd.c.

References ENABLE, GPIO_Init(), GPIO_InitStructure, GPIO_InitTypeDef::GPIO_Mode, GPIO_Mode_AF_PP, GPIO_InitTypeDef::GPIO_Pin, GPIO_PinRemapConfig(), GPIO_Remap_SPI3, GPIO_InitTypeDef::GPIO_Speed, GPIO_Speed_50MHz, LCD_HX8312, LCD_ILI9320, LCD_SPFD5408, LCD_SPI, LCD_SPI_CLK, LCD_SPI_MISO_AF, LCD_SPI_MISO_GPIO_CLK, LCD_SPI_MISO_GPIO_PORT, LCD_SPI_MISO_PIN, LCD_SPI_MISO_SOURCE, LCD_SPI_MOSI_AF, LCD_SPI_MOSI_GPIO_CLK, LCD_SPI_MOSI_GPIO_PORT, LCD_SPI_MOSI_PIN, LCD_SPI_MOSI_SOURCE, LCD_SPI_SCK_AF, LCD_SPI_SCK_GPIO_CLK, LCD_SPI_SCK_GPIO_PORT, LCD_SPI_SCK_PIN, LCD_SPI_SCK_SOURCE, LCDType, RCC_AHBPeriphClockCmd(), RCC_APB1PeriphClockCmd(), RCC_APB2Periph_AFIO, RCC_APB2PeriphClockCmd(), SPI_InitTypeDef::SPI_BaudRatePrescaler, SPI_BaudRatePrescaler_2, SPI_Cmd(), SPI_InitTypeDef::SPI_CPHA, SPI_CPHA_1Edge, SPI_CPHA_2Edge, SPI_InitTypeDef::SPI_CPOL, SPI_CPOL_High, SPI_CPOL_Low, SPI_InitTypeDef::SPI_CRCPolynomial, SPI_InitTypeDef::SPI_DataSize, SPI_DataSize_16b, SPI_DataSize_8b, SPI_InitTypeDef::SPI_Direction, SPI_Direction_2Lines_FullDuplex, SPI_InitTypeDef::SPI_FirstBit, SPI_FirstBit_MSB, SPI_I2S_DeInit(), SPI_Init(), SPI_InitStructure, SPI_InitTypeDef::SPI_Mode, SPI_Mode_Master, SPI_InitTypeDef::SPI_NSS, and SPI_NSS_Soft.

Referenced by LCD_Setup().

void LCD_WindowModeDisable ( void )

Disables LCD Window mode.

Parameters:
None
Return values:
None

Definition at line 729 of file stm32100b_eval_lcd.c.

References LCD_HX8312, LCD_ILI9320, LCD_REG_1, LCD_REG_3, LCD_REG_5, LCD_SetDisplayWindow(), LCD_SPFD5408, LCD_WriteReg(), and LCDType.

void LCD_WriteRAM ( uint16_t RGB_Code )

Writes to the LCD RAM.

Parameters:
RGB_Code,: the pixel color in RGB mode (5-6-5).
Return values:
None

Definition at line 1594 of file stm32100b_eval_lcd.c.

References Bit_RESET, Bit_SET, LCD, LCD_CtrlLinesWrite(), LCD_HX8312, LCD_ILI9320, LCD_NCS_GPIO_PORT, LCD_NCS_PIN, LCD_NWR_GPIO_PORT, LCD_NWR_PIN, LCD_RS_GPIO_PORT, LCD_RS_PIN, LCD_SPFD5408, LCD_SPI, LCDType, RESET, SPI_I2S_FLAG_BSY, SPI_I2S_GetFlagStatus(), and SPI_I2S_SendData().

Referenced by LCD_Clear(), LCD_DrawChar(), LCD_DrawCircle(), LCD_DrawLine(), LCD_DrawMonoPict(), LCD_WriteBMP(), and LCD_WriteRAMWord().

void LCD_WriteRAM_Prepare ( void )

Prepare to write to the LCD RAM.

Parameters:
None
Return values:
None

Definition at line 1518 of file stm32100b_eval_lcd.c.

References LCD, LCD_nCS_StartByte(), LCD_REG_34, LCD_WRITE_REG, LCD_WriteRegIndex(), and START_BYTE.

Referenced by LCD_Clear(), LCD_DrawChar(), LCD_DrawCircle(), LCD_DrawLine(), LCD_DrawMonoPict(), LCD_WriteBMP(), and LCD_WriteRAMWord().

void LCD_WriteRAMWord ( uint16_t RGB_Code )

Writes 1 word to the LCD RAM.

Parameters:
RGB_Code,: the pixel color in RGB mode (5-6-5).
Return values:
None

Definition at line 1532 of file stm32100b_eval_lcd.c.

References Bit_SET, LCD_CtrlLinesWrite(), LCD_NCS_GPIO_PORT, LCD_NCS_PIN, LCD_WriteRAM(), and LCD_WriteRAM_Prepare().

Referenced by LCD_DrawCircle(), and LCD_DrawLine().

void LCD_WriteReg | ( | uint8_t | LCD_Reg,
 |  | uint16_t | LCD_RegValue
 | ) |  |

Writes to the selected LCD register.

Parameters:
LCD_Reg,: address of the selected register.
LCD_RegValue,: value to write to the selected register.
Return values:
None Writes to the selected LCD register.
Parameters:
LCD_Reg,: address of the selected register.
LCD_RegValue,: value to write to the selected register.
Return values:
None

Definition at line 1576 of file stm32100b_eval_lcd.c.

References Bit_SET, LCD, LCD_CtrlLinesWrite(), LCD_HX8312, LCD_ILI9320, LCD_NCS_GPIO_PORT, LCD_NCS_PIN, LCD_nCS_StartByte(), LCD_SPFD5408, LCD_SPI, LCD_WRITE_REG, LCD_WriteRegHX8312(), LCD_WriteRegILI9320(), LCD_WriteRegIndex(), LCDType, RESET, SPI_I2S_FLAG_BSY, SPI_I2S_GetFlagStatus(), SPI_I2S_SendData(), and START_BYTE.

Referenced by LCD_DisplayOff(), LCD_DisplayOn(), LCD_PowerOn(), LCD_SetCursor(), LCD_SetDisplayWindow(), LCD_Setup(), LCD_WindowModeDisable(), LCD_WriteBMP(), STM32100E_LCD_Init(), and STM3210E_LCD_Init().

void LCD_WriteRegIndex ( uint8_t LCD_Reg )

Writes index to select the LCD register.

Parameters:
LCD_Reg,: address of the selected register.
Return values:
None

Definition at line 1394 of file stm32100b_eval_lcd.c.

References Bit_SET, LCD_CtrlLinesWrite(), LCD_NCS_GPIO_PORT, LCD_NCS_PIN, LCD_nCS_StartByte(), LCD_SPI, RESET, SET_INDEX, SPI_I2S_FLAG_BSY, SPI_I2S_GetFlagStatus(), SPI_I2S_SendData(), and START_BYTE.

Referenced by LCD_ReadReg(), LCD_WriteRAM_Prepare(), LCD_WriteReg(), and LCD_WriteRegILI9320().

void STM32L152_LCD_DeInit ( void )

DeInitializes the LCD.

Parameters:
None
Return values:
None

< LCD Display Off

< LCD_SPI disable

< LCD_SPI DeInit

< Disable SPI clock

Definition at line 113 of file stm32l152_eval_lcd.c.

References DISABLE, GPIO_Init(), GPIO_InitStructure, GPIO_InitTypeDef::GPIO_Mode, GPIO_InitTypeDef::GPIO_Pin, LCD_DisplayOff(), LCD_NCS_GPIO_PORT, LCD_NCS_PIN, LCD_SPI, LCD_SPI_CLK, LCD_SPI_MISO_GPIO_PORT, LCD_SPI_MISO_PIN, LCD_SPI_MOSI_GPIO_PORT, LCD_SPI_MOSI_PIN, LCD_SPI_SCK_GPIO_PORT, LCD_SPI_SCK_PIN, RCC_APB1PeriphClockCmd(), and SPI_Cmd().

void STM32L152_LCD_Init ( void )

Initializes the LCD.

Parameters:
None
Return values:
None

Definition at line 311 of file stm32l152_eval_lcd.c.

References LCD_DEFAULT_FONT, LCD_ILI9320, LCD_ReadReg(), LCD_REG_0, LCD_SetFont(), LCD_Setup(), LCD_SPFD5408, and LCDType.


STM32F10x Standard Peripherals Firmware Library: STM32L152_EVAL_I2C_EE_Private_Types

STM32L152_EVAL_I2C_EE_Private_Types

STM32L152_EVAL_I2C_EE


STM32F10x Standard Peripherals Firmware Library: STM32L152_EVAL_I2C_EE_Private_Defines

STM32L152_EVAL_I2C_EE_Private_Defines

STM32L152_EVAL_I2C_EE


STM32F10x Standard Peripherals Firmware Library: STM32L152_EVAL_I2C_EE_Private_Macros

STM32L152_EVAL_I2C_EE_Private_Macros

STM32L152_EVAL_I2C_EE


STM32F10x Standard Peripherals Firmware Library: STM32L152_EVAL_I2C_EE_Private_Variables

Variables

STM32L152_EVAL_I2C_EE_Private_Variables

STM32L152_EVAL_I2C_EE

Variables

__IO uint16_t | sEEAddress = 0
__IO uint8_t | sEEDataNum
__IO uint16_t * | sEEDataReadPointer
__IO uint8_t * | sEEDataWritePointer
__IO uint32_t | sEETimeout = sEE_LONG_TIMEOUT

Variable Documentation

__IO uint16_t sEEAddress = 0

Definition at line 112 of file stm32l152_eval_i2c_ee.c.

__IO uint8_t sEEDataNum

Definition at line 116 of file stm32l152_eval_i2c_ee.c.

__IO uint16_t* sEEDataReadPointer

Definition at line 114 of file stm32l152_eval_i2c_ee.c.

__IO uint8_t* sEEDataWritePointer

Definition at line 115 of file stm32l152_eval_i2c_ee.c.

__IO uint32_t sEETimeout = sEE_LONG_TIMEOUT

Definition at line 113 of file stm32l152_eval_i2c_ee.c.


STM32F10x Standard Peripherals Firmware Library: STM32L152_EVAL_I2C_EE_Private_Function_Prototypes

STM32L152_EVAL_I2C_EE_Private_Function_Prototypes

STM32L152_EVAL_I2C_EE


STM32F10x Standard Peripherals Firmware Library: STM32L152_EVAL_I2C_EE_Private_Functions

Functions

STM32L152_EVAL_I2C_EE_Private_Functions

STM32L152_EVAL_I2C_EE

Functions

void | sEE_DeInit (void)
DeInitializes peripherals used by the I2C EEPROM driver.
void | sEE_I2C_DMA_RX_IRQHandler (void)
This function handles the DMA Rx Channel interrupt Handler.
void | sEE_I2C_DMA_TX_IRQHandler (void)
This function handles the DMA Tx Channel interrupt Handler.
void | sEE_Init (void)
Initializes peripherals used by the I2C EEPROM driver.
uint32_t | sEE_ReadBuffer (uint8_t *pBuffer, uint16_t ReadAddr, uint16_t *NumByteToRead)
Reads a block of data from the EEPROM.
uint32_t | sEE_WaitEepromStandbyState (void)
Wait for EEPROM Standby state.
void | sEE_WriteBuffer (uint8_t *pBuffer, uint16_t WriteAddr, uint16_t NumByteToWrite)
Writes buffer of data to the I2C EEPROM.
uint32_t | sEE_WritePage (uint8_t *pBuffer, uint16_t WriteAddr, uint8_t *NumByteToWrite)
Writes more than one byte to the EEPROM with a single WRITE cycle.

Function Documentation

void sEE_DeInit ( void )

DeInitializes peripherals used by the I2C EEPROM driver.

Parameters:
None
Return values:
None

Definition at line 139 of file stm32l152_eval_i2c_ee.c.

References sEE_LowLevel_DeInit().

void sEE_I2C_DMA_RX_IRQHandler ( void )

This function handles the DMA Rx Channel interrupt Handler.

Parameters:
None
Return values:
None

< Send STOP Condition

Definition at line 758 of file stm32l152_eval_i2c_ee.c.

References DISABLE, DMA_ClearFlag(), DMA_Cmd(), DMA_GetFlagStatus(), ENABLE, I2C_GenerateSTOP(), RESET, sEE_I2C, sEE_I2C_DMA_CHANNEL_RX, sEE_I2C_DMA_FLAG_RX_GL, sEE_I2C_DMA_FLAG_RX_TC, and sEEDataReadPointer.

void sEE_I2C_DMA_TX_IRQHandler ( void )

This function handles the DMA Tx Channel interrupt Handler.

Parameters:
None
Return values:
None

< Wait till all data have been physically transferred on the bus

Definition at line 729 of file stm32l152_eval_i2c_ee.c.

References DISABLE, DMA_ClearFlag(), DMA_Cmd(), DMA_GetFlagStatus(), ENABLE, I2C_FLAG_BTF, I2C_GenerateSTOP(), I2C_GetFlagStatus(), RESET, sEE_I2C, sEE_I2C_DMA_CHANNEL_TX, sEE_I2C_DMA_FLAG_TX_GL, sEE_I2C_DMA_FLAG_TX_TC, sEE_LONG_TIMEOUT, sEE_TIMEOUT_UserCallback(), sEEDataWritePointer, and sEETimeout.

void sEE_Init ( void )

Initializes peripherals used by the I2C EEPROM driver.

Parameters:
None
Return values:
None

< I2C configuration

< sEE_M24C64_32

Definition at line 149 of file stm32l152_eval_i2c_ee.c.

References ENABLE, I2C_InitTypeDef::I2C_Ack, I2C_Ack_Enable, I2C_InitTypeDef::I2C_AcknowledgedAddress, I2C_AcknowledgedAddress_7bit, I2C_InitTypeDef::I2C_ClockSpeed, I2C_Cmd(), I2C_DMACmd(), I2C_InitTypeDef::I2C_DutyCycle, I2C_DutyCycle_2, I2C_Init(), I2C_InitStructure, I2C_InitTypeDef::I2C_Mode, I2C_Mode_I2C, I2C_InitTypeDef::I2C_OwnAddress1, I2C_SLAVE_ADDRESS7, I2C_SPEED, sEE_HW_ADDRESS, sEE_I2C, sEE_LowLevel_Init(), and sEEAddress.

uint32_t sEE_ReadBuffer | ( | uint8_t * | pBuffer,
 |  | uint16_t | ReadAddr,
 |  | uint16_t * | NumByteToRead
 | ) |  |

Reads a block of data from the EEPROM.

Parameters:
pBuffer | : pointer to the buffer that receives the data read from the EEPROM.
ReadAddr | : EEPROM's internal address to start reading from.
NumByteToRead | : pointer to the variable holding number of bytes to be read from the EEPROM.
Note:
The variable pointed by NumByteToRead is reset to 0 when all the data are read from the EEPROM. Application should monitor this variable in order know when the transfer is complete.
When number of data to be read is higher than 1, this function just configures the communication and enable the DMA channel to transfer data. Meanwhile, the user application may perform other tasks. When number of data to be read is 1, then the DMA is not used. The byte is read in polling mode.
Return values:
sEE_OK (0) if operation is correctly performed, else return value different from sEE_OK (0) or the timeout user callback.

< While the bus is busy

< Test on EV5 and clear it (cleared by reading SR1 then writing to DR)

< Test on EV6 and clear it

< Test on EV8 and clear it

< Test on EV5 and clear it (cleared by reading SR1 then writing to DR)

< Send STOP Condition

< Decrement the read bytes counter

< Test on EV6 and clear it

Definition at line 220 of file stm32l152_eval_i2c_ee.c.

References DISABLE, DMA_Cmd(), ENABLE, I2C_AcknowledgeConfig(), I2C_CheckEvent(), I2C_CR1_STOP, I2C_Direction_Receiver, I2C_Direction_Transmitter, I2C_DMALastTransferCmd(), I2C_EVENT_MASTER_BYTE_TRANSMITTED, I2C_EVENT_MASTER_BYTE_TRANSMITTING, I2C_EVENT_MASTER_MODE_SELECT, I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED, I2C_FLAG_ADDR, I2C_FLAG_BTF, I2C_FLAG_BUSY, I2C_FLAG_RXNE, I2C_GenerateSTART(), I2C_GenerateSTOP(), I2C_GetFlagStatus(), I2C_ReceiveData(), I2C_Send7bitAddress(), I2C_SendData(), RESET, sEE_DIRECTION_RX, sEE_EnterCriticalSection_UserCallback(), sEE_ExitCriticalSection_UserCallback(), sEE_FLAG_TIMEOUT, sEE_I2C, sEE_I2C_DMA_CHANNEL_RX, sEE_LONG_TIMEOUT, sEE_LowLevel_DMAConfig(), sEE_OK, sEE_TIMEOUT_UserCallback(), sEEAddress, sEEDataReadPointer, and sEETimeout.

uint32_t sEE_WaitEepromStandbyState ( void )

Wait for EEPROM Standby state.

Note:
This function allows to wait and check that EEPROM has finished the last operation. It is mostly used after Write operation: after receiving the buffer to be written, the EEPROM may need additional time to actually perform the write operation. During this time, it doesn't answer to I2C packets addressed to it. Once the write operation is complete the EEPROM responds to its address.
Parameters:
None
Return values:
sEE_OK (0) if operation is correctly performed, else return value different from sEE_OK (0) or the timeout user callback.

< While the bus is busy

< Send START condition

< Test on EV5 and clear it

< STOP condition

< Clear AF flag

Definition at line 652 of file stm32l152_eval_i2c_ee.c.

References ENABLE, I2C_CheckEvent(), I2C_ClearFlag(), I2C_Direction_Transmitter, I2C_EVENT_MASTER_MODE_SELECT, I2C_FLAG_AF, I2C_FLAG_BUSY, I2C_GenerateSTART(), I2C_GenerateSTOP(), I2C_GetFlagStatus(), I2C_Send7bitAddress(), I2C_SR1_ADDR, I2C_SR1_AF, sEE_FLAG_TIMEOUT, sEE_I2C, sEE_LONG_TIMEOUT, sEE_MAX_TRIALS_NUMBER, sEE_OK, sEE_TIMEOUT_UserCallback(), sEEAddress, and sEETimeout.

void sEE_WriteBuffer | ( | uint8_t * | pBuffer,
 |  | uint16_t | WriteAddr,
 |  | uint16_t | NumByteToWrite
 | ) |  |

Writes buffer of data to the I2C EEPROM.

Parameters:
pBuffer | : pointer to the buffer containing the data to be written to the EEPROM.
WriteAddr | : EEPROM's internal address to write to.
NumByteToWrite | : number of bytes to write to the EEPROM.
Return values:
None

< If WriteAddr is sEE_PAGESIZE aligned

< If NumByteToWrite < sEE_PAGESIZE

< If NumByteToWrite < sEE_PAGESIZE

< If the number of data to be written is more than the remaining space in the current page:

< Write the data conained in same page

< Write the remaining data in the following page

Definition at line 473 of file stm32l152_eval_i2c_ee.c.

References sEE_LONG_TIMEOUT, sEE_PAGESIZE, sEE_TIMEOUT_UserCallback(), sEE_WaitEepromStandbyState(), sEE_WritePage(), sEEDataNum, and sEETimeout.

uint32_t sEE_WritePage | ( | uint8_t * | pBuffer,
 |  | uint16_t | WriteAddr,
 |  | uint8_t * | NumByteToWrite
 | ) |  |

Writes more than one byte to the EEPROM with a single WRITE cycle.

Note:
The number of bytes (combined to write start address) must not cross the EEPROM page boundary. This function can only write into the boundaries of an EEPROM page. This function doesn't check on boundaries condition (in this driver the function sEE_WriteBuffer() which calls sEE_WritePage() is responsible of checking on Page boundaries).
Parameters:
pBuffer | : pointer to the buffer containing the data to be written to the EEPROM.
WriteAddr | : EEPROM's internal address to write to.
NumByteToWrite | : pointer to the variable holding number of bytes to be written into the EEPROM.
Note:
The variable pointed by NumByteToWrite is reset to 0 when all the data are written to the EEPROM. Application should monitor this variable in order know when the transfer is complete.
This function just configure the communication and enable the DMA channel to transfer data. Meanwhile, the user application may perform other tasks in parallel.
Return values:
sEE_OK (0) if operation is correctly performed, else return value different from sEE_OK (0) or the timeout user callback.

< While the bus is busy

< Test on EV5 and clear it

< Test on EV6 and clear it

< Test on EV8 and clear it

Definition at line 390 of file stm32l152_eval_i2c_ee.c.

References DMA_Cmd(), ENABLE, I2C_CheckEvent(), I2C_Direction_Transmitter, I2C_EVENT_MASTER_BYTE_TRANSMITTED, I2C_EVENT_MASTER_BYTE_TRANSMITTING, I2C_EVENT_MASTER_MODE_SELECT, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED, I2C_FLAG_BUSY, I2C_GenerateSTART(), I2C_GetFlagStatus(), I2C_Send7bitAddress(), I2C_SendData(), sEE_DIRECTION_TX, sEE_FLAG_TIMEOUT, sEE_I2C, sEE_I2C_DMA_CHANNEL_TX, sEE_LONG_TIMEOUT, sEE_LowLevel_DMAConfig(), sEE_OK, sEE_TIMEOUT_UserCallback(), sEEAddress, sEEDataWritePointer, and sEETimeout.


STM32F10x Standard Peripherals Firmware Library: STM32L152_EVAL_I2C_EE_Exported_Types

STM32L152_EVAL_I2C_EE_Exported_Types

STM32L152_EVAL_I2C_EE


STM32F10x Standard Peripherals Firmware Library: STM32L152_EVAL_I2C_EE_Exported_Constants

Defines

STM32L152_EVAL_I2C_EE_Exported_Constants

STM32L152_EVAL_I2C_EE

Defines

#define | I2C_SLAVE_ADDRESS7 0xA0
#define | I2C_SPEED 200000
#define | sEE_FAIL 1
#define | sEE_FLAG_TIMEOUT ((uint32_t)0x1000)
#define | sEE_LONG_TIMEOUT ((uint32_t)(10 * sEE_FLAG_TIMEOUT))
#define | sEE_M24C64_32
#define | sEE_MAX_TRIALS_NUMBER 300
#define | sEE_OK 0
#define | sEE_STATE_BUSY 1
#define | sEE_STATE_ERROR 2
#define | sEE_STATE_READY 0

Define Documentation

#define I2C_SLAVE_ADDRESS7 0xA0

Definition at line 95 of file stm32l152_eval_i2c_ee.h.

#define I2C_SPEED 200000

Definition at line 94 of file stm32l152_eval_i2c_ee.h.

#define sEE_FAIL 1

Definition at line 120 of file stm32l152_eval_i2c_ee.h.

#define sEE_FLAG_TIMEOUT ((uint32_t)0x1000)

Definition at line 108 of file stm32l152_eval_i2c_ee.h.

#define sEE_LONG_TIMEOUT ((uint32_t)(10 * sEE_FLAG_TIMEOUT))

Definition at line 109 of file stm32l152_eval_i2c_ee.h.

#define sEE_M24C64_32

Definition at line 74 of file stm32l152_eval_i2c_ee.h.

#define sEE_MAX_TRIALS_NUMBER 300

Definition at line 112 of file stm32l152_eval_i2c_ee.h.

#define sEE_OK 0

Definition at line 119 of file stm32l152_eval_i2c_ee.h.

#define sEE_STATE_BUSY 1

Definition at line 116 of file stm32l152_eval_i2c_ee.h.

#define sEE_STATE_ERROR 2

Definition at line 117 of file stm32l152_eval_i2c_ee.h.

#define sEE_STATE_READY 0

Definition at line 115 of file stm32l152_eval_i2c_ee.h.


STM32F10x Standard Peripherals Firmware Library: STM32L152_EVAL_I2C_EE_Exported_Macros

STM32L152_EVAL_I2C_EE_Exported_Macros

STM32L152_EVAL_I2C_EE


STM32F10x Standard Peripherals Firmware Library: STM32L152_EVAL_I2C_EE_Exported_Functions

Functions

STM32L152_EVAL_I2C_EE_Exported_Functions

STM32L152_EVAL_I2C_EE

Functions

void | sEE_DeInit (void)
DeInitializes peripherals used by the I2C EEPROM driver.
void | sEE_Init (void)
Initializes peripherals used by the I2C EEPROM driver.
uint32_t | sEE_ReadBuffer (uint8_t *pBuffer, uint16_t ReadAddr, uint16_t *NumByteToRead)
Reads a block of data from the EEPROM.
uint32_t | sEE_TIMEOUT_UserCallback (void)
Example of timeout situation management.
uint32_t | sEE_WaitEepromStandbyState (void)
Wait for EEPROM Standby state.
void | sEE_WriteBuffer (uint8_t *pBuffer, uint16_t WriteAddr, uint16_t NumByteToWrite)
Writes buffer of data to the I2C EEPROM.
uint32_t | sEE_WritePage (uint8_t *pBuffer, uint16_t WriteAddr, uint8_t *NumByteToWrite)
Writes more than one byte to the EEPROM with a single WRITE cycle.

Function Documentation

void sEE_DeInit ( void )

DeInitializes peripherals used by the I2C EEPROM driver.

Parameters:
None
Return values:
None

Definition at line 137 of file stm32_eval_i2c_ee.c.

References sEE_LowLevel_DeInit().

Referenced by main().

void sEE_Init ( void )

Initializes peripherals used by the I2C EEPROM driver.

Parameters:
None
Return values:
None

< I2C configuration

< Select the EEPROM address according to the state of E0, E1, E2 pins

< sEE_M24C64_32

< I2C configuration

< sEE_M24C64_32

Definition at line 147 of file stm32_eval_i2c_ee.c.

References ENABLE, I2C_InitTypeDef::I2C_Ack, I2C_Ack_Enable, I2C_InitTypeDef::I2C_AcknowledgedAddress, I2C_AcknowledgedAddress_7bit, I2C_InitTypeDef::I2C_ClockSpeed, I2C_Cmd(), I2C_DMACmd(), I2C_InitTypeDef::I2C_DutyCycle, I2C_DutyCycle_2, I2C_Init(), I2C_InitStructure, I2C_InitTypeDef::I2C_Mode, I2C_Mode_I2C, I2C_InitTypeDef::I2C_OwnAddress1, I2C_SLAVE_ADDRESS7, I2C_SPEED, sEE_HW_ADDRESS, sEE_I2C, sEE_LowLevel_Init(), and sEEAddress.

Referenced by main().

uint32_t sEE_ReadBuffer | ( | uint8_t * | pBuffer,
 |  | uint16_t | ReadAddr,
 |  | uint16_t * | NumByteToRead
 | ) |  |

Reads a block of data from the EEPROM.

Parameters:
pBuffer | : pointer to the buffer that receives the data read from the EEPROM.
ReadAddr | : EEPROM's internal address to start reading from.
NumByteToRead | : pointer to the variable holding number of bytes to be read from the EEPROM.
Note:
The variable pointed by NumByteToRead is reset to 0 when all the data are read from the EEPROM. Application should monitor this variable in order know when the transfer is complete.
When number of data to be read is higher than 1, this function just configures the communication and enable the DMA channel to transfer data. Meanwhile, the user application may perform other tasks. When number of data to be read is 1, then the DMA is not used. The byte is read in polling mode.
Return values:
sEE_OK (0) if operation is correctly performed, else return value different from sEE_OK (0) or the timeout user callback.

< While the bus is busy

< Test on EV5 and clear it (cleared by reading SR1 then writing to DR)

< Test on EV6 and clear it

< Test on EV8 and clear it

< sEE_M24C08

< Test on EV8 and clear it

< Test on EV5 and clear it (cleared by reading SR1 then writing to DR)

< Send STOP Condition

< Decrement the read bytes counter

< Test on EV6 and clear it

< While the bus is busy

< Test on EV5 and clear it (cleared by reading SR1 then writing to DR)

< Test on EV6 and clear it

< Test on EV8 and clear it

< Test on EV5 and clear it (cleared by reading SR1 then writing to DR)

< Send STOP Condition

< Decrement the read bytes counter

< Test on EV6 and clear it

Definition at line 218 of file stm32_eval_i2c_ee.c.

References DISABLE, DMA_Cmd(), ENABLE, I2C_AcknowledgeConfig(), I2C_CheckEvent(), I2C_CR1_STOP, I2C_Direction_Receiver, I2C_Direction_Transmitter, I2C_DMALastTransferCmd(), I2C_EVENT_MASTER_BYTE_TRANSMITTED, I2C_EVENT_MASTER_BYTE_TRANSMITTING, I2C_EVENT_MASTER_MODE_SELECT, I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED, I2C_FLAG_ADDR, I2C_FLAG_BTF, I2C_FLAG_BUSY, I2C_FLAG_RXNE, I2C_GenerateSTART(), I2C_GenerateSTOP(), I2C_GetFlagStatus(), I2C_ReceiveData(), I2C_Send7bitAddress(), I2C_SendData(), RESET, sEE_DIRECTION_RX, sEE_EnterCriticalSection_UserCallback(), sEE_ExitCriticalSection_UserCallback(), sEE_FLAG_TIMEOUT, sEE_I2C, sEE_I2C_DMA_CHANNEL_RX, sEE_LONG_TIMEOUT, sEE_LowLevel_DMAConfig(), sEE_OK, sEE_TIMEOUT_UserCallback(), sEEAddress, sEEDataReadPointer, and sEETimeout.

Referenced by main().

uint32_t sEE_TIMEOUT_UserCallback ( void )

Example of timeout situation management.

Parameters:
None.
Return values:
None.

Definition at line 267 of file STM32F10x_StdPeriph_Examples/I2C/EEPROM/main.c.

References LCD_Clear(), LCD_COLOR_RED, LCD_DisplayStringLine(), LCD_LINE_4, LCD_LINE_5, and LCD_LINE_6.

Referenced by sEE_I2C_DMA_TX_IRQHandler(), sEE_ReadBuffer(), sEE_WaitEepromStandbyState(), sEE_WriteBuffer(), and sEE_WritePage().

uint32_t sEE_WaitEepromStandbyState ( void )

Wait for EEPROM Standby state.

Note:
This function allows to wait and check that EEPROM has finished the last Write operation. It is mostly used after Write operation: after receiving the buffer to be written, the EEPROM may need additional time to actually perform the write operation. During this time, it doesn't answer to I2C packets addressed to it. Once the write operation is complete the EEPROM responds to its address.
It is not necessary to call this function after sEE_WriteBuffer() function (sEE_WriteBuffer() already calls this function after each write page operation).
Parameters:
None
Return values:
sEE_OK (0) if operation is correctly performed, else return value different from sEE_OK (0) or the timeout user callback.
Note:
This function allows to wait and check that EEPROM has finished the last operation. It is mostly used after Write operation: after receiving the buffer to be written, the EEPROM may need additional time to actually perform the write operation. During this time, it doesn't answer to I2C packets addressed to it. Once the write operation is complete the EEPROM responds to its address.
Parameters:
None
Return values:
sEE_OK (0) if operation is correctly performed, else return value different from sEE_OK (0) or the timeout user callback.

< While the bus is busy

< Send START condition

< Test on EV5 and clear it

< STOP condition

< Clear AF flag

< While the bus is busy

< Send START condition

< Test on EV5 and clear it

< STOP condition

< Clear AF flag

Definition at line 660 of file stm32_eval_i2c_ee.c.

References ENABLE, I2C_CheckEvent(), I2C_ClearFlag(), I2C_Direction_Transmitter, I2C_EVENT_MASTER_MODE_SELECT, I2C_FLAG_AF, I2C_FLAG_BUSY, I2C_GenerateSTART(), I2C_GenerateSTOP(), I2C_GetFlagStatus(), I2C_Send7bitAddress(), I2C_SR1_ADDR, I2C_SR1_AF, sEE_FLAG_TIMEOUT, sEE_I2C, sEE_LONG_TIMEOUT, sEE_MAX_TRIALS_NUMBER, sEE_OK, sEE_TIMEOUT_UserCallback(), sEEAddress, and sEETimeout.

Referenced by sEE_WriteBuffer().

void sEE_WriteBuffer | ( | uint8_t * | pBuffer,
 |  | uint16_t | WriteAddr,
 |  | uint16_t | NumByteToWrite
 | ) |  |

Writes buffer of data to the I2C EEPROM.

Parameters:
pBuffer | : pointer to the buffer containing the data to be written to the EEPROM.
WriteAddr | : EEPROM's internal address to write to.
NumByteToWrite | : number of bytes to write to the EEPROM.
Return values:
None

< If WriteAddr is sEE_PAGESIZE aligned

< If NumByteToWrite < sEE_PAGESIZE

< If NumByteToWrite < sEE_PAGESIZE

< If the number of data to be written is more than the remaining space in the current page:

< Write the data conained in same page

< Write the remaining data in the following page

< If WriteAddr is sEE_PAGESIZE aligned

< If NumByteToWrite < sEE_PAGESIZE

< If NumByteToWrite < sEE_PAGESIZE

< If the number of data to be written is more than the remaining space in the current page:

< Write the data conained in same page

< Write the remaining data in the following page

Definition at line 477 of file stm32_eval_i2c_ee.c.

References sEE_LONG_TIMEOUT, sEE_PAGESIZE, sEE_TIMEOUT_UserCallback(), sEE_WaitEepromStandbyState(), sEE_WritePage(), sEEDataNum, and sEETimeout.

Referenced by main().

uint32_t sEE_WritePage | ( | uint8_t * | pBuffer,
 |  | uint16_t | WriteAddr,
 |  | uint8_t * | NumByteToWrite
 | ) |  |

Writes more than one byte to the EEPROM with a single WRITE cycle.

Note:
The number of bytes (combined to write start address) must not cross the EEPROM page boundary. This function can only write into the boundaries of an EEPROM page. This function doesn't check on boundaries condition (in this driver the function sEE_WriteBuffer() which calls sEE_WritePage() is responsible of checking on Page boundaries).
Parameters:
pBuffer | : pointer to the buffer containing the data to be written to the EEPROM.
WriteAddr | : EEPROM's internal address to write to.
NumByteToWrite | : pointer to the variable holding number of bytes to be written into the EEPROM.
Note:
The variable pointed by NumByteToWrite is reset to 0 when all the data are written to the EEPROM. Application should monitor this variable in order know when the transfer is complete.
This function just configure the communication and enable the DMA channel to transfer data. Meanwhile, the user application may perform other tasks in parallel.
Return values:
sEE_OK (0) if operation is correctly performed, else return value different from sEE_OK (0) or the timeout user callback.

< While the bus is busy

< Test on EV5 and clear it

< Test on EV6 and clear it

< Test on EV8 and clear it

< sEE_M24C08

< Test on EV8 and clear it

< While the bus is busy

< Test on EV5 and clear it

< Test on EV6 and clear it

< Test on EV8 and clear it

Definition at line 394 of file stm32_eval_i2c_ee.c.

References DMA_Cmd(), ENABLE, I2C_CheckEvent(), I2C_Direction_Transmitter, I2C_EVENT_MASTER_BYTE_TRANSMITTED, I2C_EVENT_MASTER_BYTE_TRANSMITTING, I2C_EVENT_MASTER_MODE_SELECT, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED, I2C_FLAG_BUSY, I2C_GenerateSTART(), I2C_GetFlagStatus(), I2C_Send7bitAddress(), I2C_SendData(), sEE_DIRECTION_TX, sEE_FLAG_TIMEOUT, sEE_I2C, sEE_I2C_DMA_CHANNEL_TX, sEE_LONG_TIMEOUT, sEE_LowLevel_DMAConfig(), sEE_OK, sEE_TIMEOUT_UserCallback(), sEEAddress, sEEDataWritePointer, and sEETimeout.

Referenced by sEE_WriteBuffer().


STM32F10x Standard Peripherals Firmware Library: Data Fields

  • Data Structures
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  • n
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  • s
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- a -

  • ACR : FLASH_TypeDef
  • ADC_ContinuousConvMode : ADC_InitTypeDef
  • ADC_DataAlign : ADC_InitTypeDef
  • ADC_ExternalTrigConv : ADC_InitTypeDef
  • ADC_Mode : ADC_InitTypeDef
  • ADC_NbrOfChannel : ADC_InitTypeDef
  • ADC_ScanConvMode : ADC_InitTypeDef
  • ADCCLK_Frequency : RCC_ClocksTypeDef
  • AHBENR : RCC_TypeDef
  • ALRH : RTC_TypeDef
  • ALRL : RTC_TypeDef
  • APB1ENR : RCC_TypeDef
  • APB1RSTR : RCC_TypeDef
  • APB2ENR : RCC_TypeDef
  • APB2RSTR : RCC_TypeDef
  • AR : FLASH_TypeDef
  • ARG : SDIO_TypeDef
  • ARR : TIM_TypeDef
  • AU_SIZE : SD_CardStatus


STM32F10x Standard Peripherals Firmware Library: accesspermission.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • CortexM3
  • MPU
Defines | Functions

accesspermission.c File Reference

Access rights configuration using Cortex-M3 MPU regions. More...

#include "main.h"

Go to the source code of this file.

Defines

#define | ARRAY_ADDRESS_START (0x20002000UL)
#define | ARRAY_REGION_NUMBER (0x03UL << MPU_RNR_REGION_Pos)
#define | ARRAY_SIZE (0x09UL << 0UL)

Functions

void | accesspermission (void)
This function configure the access right using Cortex-M3 MPU regions.

Detailed Description

Access rights configuration using Cortex-M3 MPU regions.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file accesspermission.c.


STM32F10x Standard Peripherals Firmware Library: fonts.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • Common
Variables

fonts.c File Reference

This file provides text fonts for STM32xx-EVAL's LCD driver. More...

#include "fonts.h"

Go to the source code of this file.

Variables

const uint16_t | ASCII12x12_Table []
const uint16_t | ASCII16x24_Table []
const uint16_t | ASCII8x12_Table []
const uint16_t | ASCII8x8_Table []
sFONT Font12x12
sFONT Font16x24
sFONT Font8x12
sFONT Font8x8

Detailed Description

This file provides text fonts for STM32xx-EVAL's LCD driver.

Author:
MCD Application Team
Version:
V4.5.0
Date:
07-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file fonts.c.


STM32F10x Standard Peripherals Firmware Library: fonts.h File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • Common
Data Structures | Defines | Typedefs | Variables

fonts.h File Reference

Header for fonts.c. More...

#include <stdint.h>

Go to the source code of this file.

Data Structures

struct | _tFont

Defines

#define | LINE(x) ((x) * (((sFONT *)LCD_GetFont())->Height))

Typedefs

typedef struct _tFont | sFONT

Variables

sFONT Font12x12
sFONT Font16x24
sFONT Font8x12
sFONT Font8x8

Detailed Description

Header for fonts.c.

Author:
MCD Application Team
Version:
V4.5.0
Date:
07-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file fonts.h.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • ADC
  • 3ADCs_DMA
Defines | Functions | Variables

STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c File Reference

Main program body. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | ADC1_DR_Address ((uint32_t)0x4001244C)
#define | ADC3_DR_Address ((uint32_t)0x40013C4C)

Functions

void | GPIO_Configuration (void)
Configures the different GPIO ports.
int | main (void)
Main program.
void | NVIC_Configuration (void)
Configures Vector Table base location.
void | RCC_Configuration (void)
Configures the different system clocks.

Variables

__IO uint16_t | ADC1ConvertedValue = 0
__IO uint16_t | ADC3ConvertedValue = 0
ADC_InitTypeDef ADC_InitStructure
DMA_InitTypeDef DMA_InitStructure

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • ADC
  • ADC1_DMA
Defines | Functions | Variables

STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/main.c File Reference

Main program body. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | ADC1_DR_Address ((uint32_t)0x4001244C)

Functions

void | GPIO_Configuration (void)
Configures the different GPIO ports.
int | main (void)
Main program.
void | RCC_Configuration (void)
Configures the different system clocks.

Variables

ADC_InitTypeDef ADC_InitStructure
__IO uint16_t | ADCConvertedValue
DMA_InitTypeDef DMA_InitStructure

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • ADC
  • AnalogWatchdog
Functions | Variables

STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/main.c File Reference

Main program body. More...

#include "stm32f10x.h"
#include "stm32_eval.h"

Go to the source code of this file.

Functions

void | GPIO_Configuration (void)
Configures the different GPIO ports.
int | main (void)
Main program.
void | NVIC_Configuration (void)
Configures NVIC and Vector Table base location.
void | RCC_Configuration (void)
Configures the different system clocks.

Variables

ADC_InitTypeDef ADC_InitStructure

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • ADC
  • ExtLinesTrigger
Defines | Functions | Variables

STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/main.c File Reference

Main program body. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | ADC1_DR_Address ((uint32_t)0x4001244C)

Functions

void | EXTI_Configuration (void)
Configures the different EXTI lines.
void | GPIO_Configuration (void)
Configures the different GPIO ports.
int | main (void)
Main program.
void | NVIC_Configuration (void)
Configures NVIC and Vector Table base location.
void | RCC_Configuration (void)
Configures the different system clocks.

Variables

ADC_InitTypeDef ADC_InitStructure
__IO uint16_t | ADC_InjectedConvertedValueTab [32]
__IO uint16_t | ADC_RegularConvertedValueTab [64]
DMA_InitTypeDef DMA_InitStructure

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • ADC
  • RegSimul_DualMode
Defines | Functions | Variables

STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/main.c File Reference

Main program body. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | ADC1_DR_Address ((uint32_t)0x4001244C)

Functions

void | GPIO_Configuration (void)
Configures the different GPIO ports.
int | main (void)
Main program.
void | RCC_Configuration (void)
Configures the different system clocks.

Variables

__IO uint32_t | ADC_DualConvertedValueTab [16]
ADC_InitTypeDef ADC_InitStructure
DMA_InitTypeDef DMA_InitStructure

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • ADC
  • TIMTrigger_AutoInjection
Defines | Functions | Variables

STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/main.c File Reference

Main program body. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | ADC1_DR_Address ((uint32_t)0x4001244C)

Functions

void | GPIO_Configuration (void)
Configures the different GPIO ports.
int | main (void)
Main program.
void | NVIC_Configuration (void)
Configures NVIC and Vector Table base location.
void | RCC_Configuration (void)
Configures the different system clocks.

Variables

ADC_InitTypeDef ADC_InitStructure
__IO uint16_t | ADC_InjectedConvertedValueTab [32]
__IO uint16_t | ADC_RegularConvertedValueTab [32]
DMA_InitTypeDef DMA_InitStructure
TIM_OCInitTypeDef TIM_OCInitStructure
TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • BKP
  • Backup_Data
Defines | Functions | Variables

STM32F10x_StdPeriph_Examples/BKP/Backup_Data/main.c File Reference

Main program body. More...

#include "stm32f10x.h"
#include "stm32_eval.h"

Go to the source code of this file.

Defines

#define | BKP_DR_NUMBER 42

Functions

uint8_t | CheckBackupReg (uint16_t FirstBackupData)
Checks if the Backup DRx registers values are correct or not.
int | main (void)
Main program.
void | WriteToBackupReg (uint16_t FirstBackupData)
Writes data Backup DRx registers.

Variables

uint16_t | BKPDataReg [BKP_DR_NUMBER]

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/BKP/Backup_Data/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • BKP
  • Tamper
Defines | Functions | Variables

STM32F10x_StdPeriph_Examples/BKP/Tamper/main.c File Reference

Main program body. More...

#include "main.h"

Go to the source code of this file.

Defines

#define | BKP_DR_NUMBER 42

Functions

uint32_t | CheckBackupReg (uint16_t FirstBackupData)
Checks if the Backup DRx registers values are correct or not.
void | GPIO_Configuration (void)
Configures the different GPIO ports.
uint32_t | IsBackupRegReset (void)
Checks if the Backup DRx registers are reset or not.
int | main (void)
Main program.
void | NVIC_Configuration (void)
Configures NVIC and Vector Table base location.
void | WriteToBackupReg (uint16_t FirstBackupData)
Writes data Backup DRx registers.

Variables

uint16_t | BKPDataReg [BKP_DR_NUMBER]

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/BKP/Tamper/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • CAN
  • DualCAN
Defines | Functions | Variables

STM32F10x_StdPeriph_Examples/CAN/DualCAN/main.c File Reference

Main program body. More...

#include "stm32_eval.h"
#include "stm3210c_eval_lcd.h"

Go to the source code of this file.

Defines

#define | CAN_BAUDRATE 1000

Functions

void | CAN_Config (void)
Configures CAN1 and CAN2.
void | Delay (void)
Delay.
void | Init_RxMes (CanRxMsg *RxMessage)
Initializes a Rx Message.
void | LED_Display (uint8_t Ledstatus)
Turn ON/OFF the dedicate led.
int | main (void)
Main program.
void | NVIC_Config (void)
Configures the NVIC for CAN.

Variables

CAN_FilterInitTypeDef CAN_FilterInitStructure
CAN_InitTypeDef CAN_InitStructure
CanTxMsg TxMessage

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/CAN/DualCAN/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • CAN
  • LoopBack
Defines | Enumerations | Functions | Variables

STM32F10x_StdPeriph_Examples/CAN/LoopBack/main.c File Reference

Main program body. More...

#include "stm32f10x.h"
#include "stm32_eval.h"

Go to the source code of this file.

Defines

#define | __CAN1_USED__
#define | CANx CAN1

Enumerations

enum TestStatus {
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED
}

Functions

TestStatus | CAN_Interrupt (void)
Configures the CAN, transmit and receive using interrupt.
TestStatus | CAN_Polling (void)
Configures the CAN, transmit and receive by polling.
int | main (void)
Main program.
void | NVIC_Configuration (void)
Configures the NVIC and Vector Table base address.

Variables

__IO uint32_t | ret = 0
volatile TestStatus | TestRx

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/CAN/LoopBack/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • CAN
  • Networking
Defines | Functions | Variables

STM32F10x_StdPeriph_Examples/CAN/Networking/main.c File Reference

Main program body. More...

#include "stm32f10x.h"
#include "platform_config.h"

Go to the source code of this file.

Defines

#define | __CAN1_USED__
#define | CANx CAN2
#define | GPIO_CAN GPIO_CAN2
#define | GPIO_CAN GPIO_CAN2
#define | GPIO_Pin_CAN_RX GPIO_Pin_CAN2_RX
#define | GPIO_Pin_CAN_TX GPIO_Pin_CAN2_TX
#define | GPIO_Remapping_CAN GPIO_Remap_CAN2
#define | KEY_NOT_PRESSED 0x00
#define | KEY_PRESSED 0x01

Functions

void | CAN_Config (void)
Configures the CAN.
void | Delay (void)
Delay.
void | Init_RxMes (CanRxMsg *RxMessage)
Initializes a Rx Message.
void | LED_Display (uint8_t Ledstatus)
Turn ON/OFF the dedicate led.
int | main (void)
Main program.
void | NVIC_Config (void)
Configures the NVIC for CAN.

Variables

CAN_FilterInitTypeDef CAN_FilterInitStructure
CAN_InitTypeDef CAN_InitStructure
uint8_t | KeyNumber = 0x0
CanTxMsg TxMessage

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/CAN/Networking/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • CEC
  • DataExchangeInterrupt
Enumerations | Functions | Variables

STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/main.c File Reference

Main program body. More...

#include "stm32f10x.h"
#include "stm32_eval.h"

Go to the source code of this file.

Enumerations

enum TestStatus {
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED
}

Functions

TestStatus | Buffercmp (uint8_t *pBuffer1, uint8_t *pBuffer2, uint16_t BufferLength)
Compares two buffers.
void | GPIO_Configuration (void)
Configures the different GPIO ports.
int | main (void)
Main program.
void | NVIC_Configuration (void)
Configures the different NVIC interrupts.
void | RCC_Configuration (void)
Configures the different system clocks.

Variables

uint8_t | ByteNumber = 10
CEC_InitTypeDef CEC_InitStructure
uint8_t | ReceiveBuffer [10]
__IO uint8_t | ReceivedFrame
volatile TestStatus | TransferStatus = FAILED
uint8_t | TransmitBuffer [10]

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • CortexM3
  • BitBand
Defines | Functions | Variables

STM32F10x_StdPeriph_Examples/CortexM3/BitBand/main.c File Reference

Main program body. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | RAM_BASE 0x20000000
#define | RAM_BB_BASE 0x22000000
#define | Var_GetBit_BB(VarAddr, BitNumber) (*(__IO uint32_t *) (RAM_BB_BASE | ((VarAddr - RAM_BASE) << 5) | ((BitNumber) << 2)))
#define | Var_ResetBit_BB(VarAddr, BitNumber) (*(__IO uint32_t *) (RAM_BB_BASE | ((VarAddr - RAM_BASE) << 5) | ((BitNumber) << 2)) = 0)
#define | Var_SetBit_BB(VarAddr, BitNumber) (*(__IO uint32_t *) (RAM_BB_BASE | ((VarAddr - RAM_BASE) << 5) | ((BitNumber) << 2)) = 1)

Functions

int | main (void)
Main program.

Variables

__IO uint32_t | Var
__IO uint32_t | VarAddr = 0
__IO uint32_t | VarBitValue = 0

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/CortexM3/BitBand/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • CortexM3
  • Mode_Privilege
Defines | Functions | Variables

STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/main.c File Reference

Main program body. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SP_MAIN 0x00
#define | SP_PROCESS 0x02
#define | SP_PROCESS_SIZE 0x200
#define | THREAD_MODE_PRIVILEGED 0x00
#define | THREAD_MODE_UNPRIVILEGED 0x01

Functions

int | main (void)
Main program.

Variables

__IO uint32_t | CurrentStack = 0
__IO uint32_t | Index = 0
__IO uint8_t | PSPMemAlloc [SP_PROCESS_SIZE]
__IO uint32_t | PSPValue = 0
__IO uint32_t | ThreadMode = 0

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • CortexM3
  • MPU
Defines | Functions

STM32F10x_StdPeriph_Examples/CortexM3/MPU/main.c File Reference

Main program body. More...

#include "main.h"
#include "stm32_eval.h"

Go to the source code of this file.

Defines

#define | ACCESS_PERMISSION

Functions

int | main (void)
Main program.
void | MPU_SETUP (void)
Configures the main MPU regions.

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/CortexM3/MPU/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • CRC
  • CRC_Calculation
Defines | Functions | Variables

STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/main.c File Reference

Main program body. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | BUFFER_SIZE 114

Functions

void | Delay (__IO uint32_t nCount)
Inserts a delay time.
int | main (void)
Main program.

Variables

__IO uint32_t | CRCValue = 0
static const uint32_t | DataBuffer [BUFFER_SIZE]

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • DAC
  • DualModeDMA_SineWave
Defines | Functions | Variables

STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/main.c File Reference

Main program body. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | DAC_DHR12RD_Address 0x40007420

Functions

void | Delay (__IO uint32_t nCount)
Inserts a delay time.
void | GPIO_Configuration (void)
Configures the different GPIO ports.
int | main (void)
Main program.
void | RCC_Configuration (void)
Configures the different system clocks.

Variables

DAC_InitTypeDef DAC_InitStructure
DMA_InitTypeDef DMA_InitStructure
uint32_t | DualSine12bit [32]
uint32_t | Idx = 0
const uint16_t | Sine12bit [32]
TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • DAC
  • OneChannel_NoiseWave
Functions | Variables

STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/main.c File Reference

Main program body. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | Delay (__IO uint32_t nCount)
Inserts a delay time.
void | GPIO_Configuration (void)
Configures the different GPIO ports.
int | main (void)
Main program.
void | RCC_Configuration (void)
Configures the different system clocks.

Variables

DAC_InitTypeDef DAC_InitStructure

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • DAC
  • OneChannelDMA_Escalator
Defines | Functions | Variables

STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/main.c File Reference

Main program body. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | DAC_DHR8R1_Address 0x40007410

Functions

void | Delay (__IO uint32_t nCount)
Inserts a delay time.
void | GPIO_Configuration (void)
Configures the different GPIO ports.
int | main (void)
Main program.
void | RCC_Configuration (void)
Configures the different system clocks.

Variables

DAC_InitTypeDef DAC_InitStructure
DMA_InitTypeDef DMA_InitStructure
const uint8_t | Escalator8bit [6] = {0x0, 0x33, 0x66, 0x99, 0xCC, 0xFF}

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • DAC
  • TwoChannels_TriangleWave
Functions | Variables

STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/main.c File Reference

Main program body. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | Delay (__IO uint32_t nCount)
Inserts a delay time.
void | GPIO_Configuration (void)
Configures the different GPIO ports.
int | main (void)
Main program.
void | RCC_Configuration (void)
Configures the different system clocks.

Variables

DAC_InitTypeDef DAC_InitStructure
TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • DMA
  • ADC_TIM1
Defines | Functions | Variables

STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/main.c File Reference

Main program body. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | ADC1_DR_Address 0x4001244C
#define | TIM1_CCR1_Address 0x40012C34

Functions

void | GPIO_Configuration (void)
Configures the different GPIO ports.
int | main (void)
Main program.
void | RCC_Configuration (void)
Configures the different system clocks.

Variables

ADC_InitTypeDef ADC_InitStructure
DMA_InitTypeDef DMA_InitStructure
TIM_OCInitTypeDef TIM_OCInitStructure
TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • DMA
  • FLASH_RAM
Defines | Enumerations | Functions | Variables

STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/main.c File Reference

Main program body. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | BufferSize 32

Enumerations

enum TestStatus {
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED
}

Functions

TestStatus | Buffercmp (const uint32_t *pBuffer, uint32_t *pBuffer1, uint16_t BufferLength)
Compares two buffers.
int | main (void)
Main program.
void | NVIC_Configuration (void)
Configure the nested vectored interrupt controller.
void | RCC_Configuration (void)
Configures the different system clocks.

Variables

__IO uint32_t | CurrDataCounterBegin = 0
__IO uint32_t | CurrDataCounterEnd = 0x01
DMA_InitTypeDef DMA_InitStructure
uint32_t | DST_Buffer [BufferSize]
const uint32_t | SRC_Const_Buffer [BufferSize]
TestStatus | TransferStatus = FAILED

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • DMA
  • FSMC
Defines | Enumerations | Functions | Variables

STM32F10x_StdPeriph_Examples/DMA/FSMC/main.c File Reference

Main program body. More...

#include "stm3210e_eval_fsmc_sram.h"

Go to the source code of this file.

Defines

#define | Bank1_SRAM3_ADDR ((uint32_t)0x68000000)
#define | BufferSize 32

Enumerations

enum TestStatus {
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED
}

Functions

TestStatus | Buffercmp (const uint32_t *pBuffer, uint32_t *pBuffer1, uint16_t BufferLength)
Compares two buffers.
int | main (void)
Main program.
void | RCC_Configuration (void)
Configures the different system clocks.

Variables

DMA_InitTypeDef DMA_InitStructure
uint8_t | DST_Buffer [4 *BufferSize]
uint32_t | Idx = 0
const uint32_t | SRC_Const_Buffer [BufferSize]
volatile TestStatus | TransferStatus

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/DMA/FSMC/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • DMA
  • I2C_RAM
Defines | Enumerations | Functions | Variables

STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/main.c File Reference

Main program body. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | BufferSize 8
#define | ClockSpeed 100000
#define | I2C1_DR_Address 0x40005410
#define | I2C1_SLAVE_ADDRESS7 0x30
#define | I2C2_DR_Address 0x40005810
#define | I2C2_SLAVE_ADDRESS7 0x30

Enumerations

enum TestStatus {
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED
}

Functions

TestStatus | Buffercmp (uint8_t *pBuffer, uint8_t *pBuffer1, uint16_t BufferLength)
Compares two buffers.
void | GPIO_Configuration (void)
Configures the different GPIO ports.
int | main (void)
Main program.
void | RCC_Configuration (void)
Configures the different system clocks.

Variables

DMA_InitTypeDef DMA_InitStructure
uint8_t | I2C1_Buffer_Tx [BufferSize] = {1, 2, 3, 4, 5, 6, 7, 8}
uint8_t | I2C2_Buffer_Rx [BufferSize]
I2C_InitTypeDef I2C_InitStructure
uint8_t | Rx_Idx = 0
volatile TestStatus | TransferStatus
uint8_t | Tx_Idx = 0

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • DMA
  • SPI_RAM
Defines | Enumerations | Functions | Variables

STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/main.c File Reference

Main program body. More...

#include "stm32f10x.h"
#include "platform_config.h"
#include "stm32_eval.h"

Go to the source code of this file.

Defines

#define | BufferSize 32
#define | CRCPolynomial 7

Enumerations

enum TestStatus {
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED
}

Functions

TestStatus | Buffercmp (uint8_t *pBuffer, uint8_t *pBuffer1, uint16_t BufferLength)
Compares two buffers.
void | GPIO_Configuration (void)
Configures the different GPIO ports.
int | main (void)
Main program.
void | RCC_Configuration (void)
Configures the different system clocks.

Variables

DMA_InitTypeDef DMA_InitStructure
SPI_InitTypeDef SPI_InitStructure
uint8_t | SPI_MASTER_Buffer_Rx [BufferSize]
uint8_t | SPI_MASTER_Buffer_Tx [BufferSize]
volatile uint8_t | SPI_MASTERCRCValue = 0
uint8_t | SPI_SLAVE_Buffer_Rx [BufferSize]
uint8_t | SPI_SLAVE_Buffer_Tx [BufferSize]
volatile uint8_t | SPI_SLAVECRCValue = 0
volatile TestStatus | TransferStatus1 = FAILED
volatile TestStatus | TransferStatus2 = FAILED

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • EXTI
  • EXTI_Config
Functions | Variables

STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/main.c File Reference

Main program body. More...

#include "stm32f10x.h"
#include "stm32_eval.h"

Go to the source code of this file.

Functions

void | EXTI0_Config (void)
Configure PA.00 in interrupt mode.
void | EXTI9_5_Config (void)
Configure PB.09 or PG.08 in interrupt mode.
int | main (void)
Main program.

Variables

EXTI_InitTypeDef EXTI_InitStructure
GPIO_InitTypeDef GPIO_InitStructure
NVIC_InitTypeDef NVIC_InitStructure

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • FLASH
  • Dual_Boot
Defines | Enumerations | Functions | Variables

STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/main.c File Reference

Main program body. More...

#include "main.h"

Go to the source code of this file.

Defines

#define | BANK1_START_ADDRESS 0x08000000
#define | BANK2_START_ADDRESS 0x08080000
#define | MESSAGE1 " STM32 XL Density "
#define | MESSAGE10 " 0x0 the base @ of Bank1/2"
#define | MESSAGE11 " Operation Failed !"
#define | MESSAGE12 "Bank 1/2 base @ -> 0"
#define | MESSAGE2 " Device running on "
#define | MESSAGE3 " STM3210E-EVAL "
#define | MESSAGE5 " Joystick-DOWN: reset BFB2"
#define | MESSAGE6 " bit to Boot from Bank2 "
#define | MESSAGE7 " Joystick-UP: set BFB2 "
#define | MESSAGE8 " bit to Boot from Bank1 "
#define | MESSAGE9 " Joystick-SEL: program to "

Enumerations

enum TestStatus {
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED
}

Functions

void | Delay (__IO uint32_t nTime)
Inserts a delay time.
int | main (void)
Main program.
void | TimingDelay_Decrement (void)
Decrements the TimingDelay variable.

Variables

RCC_ClocksTypeDef RCC_Clocks
static __IO uint32_t | TimingDelay
USART_InitTypeDef USART_InitStructure

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • FLASH
  • Program
Defines | Enumerations | Functions | Variables

STM32F10x_StdPeriph_Examples/FLASH/Program/main.c File Reference

Main program body. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | BANK1_WRITE_END_ADDR ((uint32_t)0x0800C000)
#define | BANK1_WRITE_START_ADDR ((uint32_t)0x08008000)
#define | FLASH_PAGE_SIZE ((uint16_t)0x400)

Enumerations

enum TestStatus {
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED
}

Functions

int | main (void)
Main program.

Variables

uint32_t | Address = 0x00
uint32_t | Data = 0x3210ABCD
uint32_t | EraseCounter = 0x00
volatile FLASH_Status | FLASHStatus = FLASH_COMPLETE
volatile TestStatus | MemoryProgramStatus = PASSED
uint32_t | NbrOfPage = 0x00

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/FLASH/Program/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • FLASH
  • Write_Protection
Defines | Enumerations | Functions | Variables

STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/main.c File Reference

Main program body. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | BANK1_WRITE_END_ADDR ((uint32_t)0x08008000)
#define | BANK1_WRITE_START_ADDR ((uint32_t)0x08006000)
#define | FLASH_PAGE_SIZE ((uint16_t)0x400)
#define | FLASH_PAGES_TO_BE_PROTECTED (FLASH_WRProt_Pages24to27 | FLASH_WRProt_Pages28to31)
#define | WRITE_PROTECTION_DISABLE

Enumerations

enum TestStatus {
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED
}

Functions

int | main (void)
Main program.

Variables

uint32_t | Address = 0x0
uint16_t | Data = 0x1753
uint32_t | EraseCounter = 0x0
volatile FLASH_Status | FLASHStatus = FLASH_COMPLETE
volatile TestStatus | MemoryProgramStatus = PASSED
uint32_t | NbrOfPage
uint32_t | ProtectedPages = 0x0
uint32_t | WRPR_Value = 0xFFFFFFFF

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • FSMC
  • NAND
Defines | Functions | Variables

STM32F10x_StdPeriph_Examples/FSMC/NAND/main.c File Reference

Main program body. More...

#include "stm3210e_eval_fsmc_nand.h"
#include "stm32_eval.h"

Go to the source code of this file.

Defines

#define | BUFFER_SIZE 0x400
#define | NAND_ST_DeviceID 0x76
#define | NAND_ST_MakerID 0x20

Functions

void | Fill_Buffer (uint8_t *pBuffer, uint16_t BufferLenght, uint32_t Offset)
Fill the buffer.
int | main (void)
Main program.

Variables

uint32_t | j = 0
NAND_IDTypeDef NAND_ID
uint32_t | PageNumber = 2
uint8_t | RxBuffer [BUFFER_SIZE]
uint32_t | status = 0
uint8_t | TxBuffer [BUFFER_SIZE]
NAND_ADDRESS WriteReadAddr
uint32_t | WriteReadStatus = 0

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/FSMC/NAND/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • FSMC
  • NOR
Defines | Functions | Variables

STM32F10x_StdPeriph_Examples/FSMC/NOR/main.c File Reference

Main program body. More...

#include "stm3210e_eval_fsmc_nor.h"
#include "stm32_eval.h"

Go to the source code of this file.

Defines

#define | BUFFER_SIZE 0x400
#define | WRITE_READ_ADDR 0x8000

Functions

void | Fill_Buffer (uint16_t *pBuffer, uint16_t BufferLenght, uint32_t Offset)
Fill the global buffer.
int | main (void)
Main program.
void | RCC_Configuration (void)
Configures the different system clocks.

Variables

uint32_t | Index = 0
NOR_IDTypeDef NOR_ID
uint16_t | RxBuffer [BUFFER_SIZE]
uint16_t | TxBuffer [BUFFER_SIZE]
uint32_t | WriteReadStatus = 0

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/FSMC/NOR/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • FSMC
  • NOR_CodeExecute
  • binary
Functions

STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/main.c File Reference

Main program body. More...

#include "stm32f10x.h"
#include "stm32_eval.h"

Go to the source code of this file.

Functions

void | Delay (__IO uint32_t nCount)
Inserts a delay time.
int | main (void)
Main program.

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • FSMC
  • NOR_CodeExecute
Defines | Typedefs | Functions | Variables

STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/main.c File Reference

Main program body. More...

#include "stm3210e_eval_fsmc_nor.h"

Go to the source code of this file.

Defines

#define | ApplicationAddress ((uint32_t)0x64000000)

Typedefs

typedef void(* | pFunction )(void)

Functions

int | main (void)
Main program.

Variables

pFunction Jump_To_Application
__IO uint32_t | JumpAddress

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • FSMC
  • OneNAND
Defines | Functions | Variables

STM32F10x_StdPeriph_Examples/FSMC/OneNAND/main.c File Reference

Main program body. More...

#include "stm32_eval.h"
#include "stm32100e_eval_fsmc_onenand.h"

Go to the source code of this file.

Defines

#define | OneNAND_BUFFER_SIZE 0x0400
#define | OneNAND_NUMBER_OF_PAGE_PER_BLOCK 0x0040
#define | OneNAND_SAMSUNG_DEVICE_ID 0x0025
#define | OneNAND_SAMSUNG_MANUFACTURER_ID 0x00EC
#define | OneNAND_WRITE_BLOCK_NUMBER 0x0000
#define | OneNAND_WRITE_PAGE_NUMBER 0x0000

Functions

void | Fill_hBuffer (uint16_t *pBuffer, uint16_t BufferLenght, uint32_t Offset)
Fills a global 16-bit buffer.
int | main (void)
Main program.

Variables

OneNAND_ADDRESS Address
uint32_t | j = 0
OneNAND_IDTypeDef OneNAND_ID
uint32_t | PageIndex = 0
uint16_t | RxBuffer_A [OneNAND_BUFFER_SIZE]
uint16_t | RxBuffer_S [OneNAND_BUFFER_SIZE]
uint32_t | Status = 0
uint16_t | TxBuffer [OneNAND_BUFFER_SIZE]

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/FSMC/OneNAND/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • FSMC
  • SRAM
Defines | Functions | Variables

STM32F10x_StdPeriph_Examples/FSMC/SRAM/main.c File Reference

Main program body. More...

#include "stm3210e_eval_fsmc_sram.h"
#include "stm32_eval.h"

Go to the source code of this file.

Defines

#define | BUFFER_SIZE 0x400
#define | WRITE_READ_ADDR 0x8000

Functions

void | Fill_Buffer (uint16_t *pBuffer, uint16_t BufferLenght, uint32_t Offset)
Fill the global buffer.
int | main (void)
Main program.

Variables

uint32_t | Index = 0
uint16_t | RxBuffer [BUFFER_SIZE]
uint16_t | TxBuffer [BUFFER_SIZE]
uint32_t | WriteReadStatus = 0

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/FSMC/SRAM/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
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  • SRAM_DataMemory
Functions | Variables

STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/main.c File Reference

Main program body. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

int | main (void)
Main program.

Variables

uint32_t | Index
__IO uint32_t | MSPValue = 0
uint32_t | Tab [1024]
__IO uint32_t | TabAddr

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • GPIO
  • IOToggle
Functions | Variables

STM32F10x_StdPeriph_Examples/GPIO/IOToggle/main.c File Reference

Main program body. More...

#include "stm32f10x.h"
#include "stm32_eval.h"

Go to the source code of this file.

Functions

int main (void)
Main program.

Variables

GPIO_InitTypeDef GPIO_InitStructure

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/GPIO/IOToggle/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • GPIO
  • JTAG_Remap
Functions | Variables

STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/main.c File Reference

Main program body. More...

#include "stm32f10x.h"
#include "stm32_eval.h"

Go to the source code of this file.

Functions

void | Delay (__IO uint32_t nCount)
Inserts a delay time.
int | main (void)
Main program.
void | RCC_Configuration (void)
Configures the different system clocks.

Variables

GPIO_InitTypeDef GPIO_InitStructure

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • I2C
  • EEPROM
Defines | Enumerations | Functions | Variables

STM32F10x_StdPeriph_Examples/I2C/EEPROM/main.c File Reference

Main program body. More...

#include "stm32_eval_i2c_ee.h"

Go to the source code of this file.

Defines

#define | BUFFER_SIZE1 (countof(Tx1_Buffer)-1)
#define | BUFFER_SIZE2 (countof(Tx2_Buffer)-1)
#define | countof(a) (sizeof(a) / sizeof(*(a)))
#define | ENABLE_LCD_MSG_DISPLAY
#define | sEE_READ_ADDRESS1 0x50
#define | sEE_READ_ADDRESS2 (sEE_READ_ADDRESS1 + BUFFER_SIZE1)
#define | sEE_WRITE_ADDRESS1 0x50
#define | sEE_WRITE_ADDRESS2 (sEE_WRITE_ADDRESS1 + BUFFER_SIZE1)

Enumerations

enum TestStatus {
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED
}

Functions

TestStatus | Buffercmp (uint8_t *pBuffer1, uint8_t *pBuffer2, uint16_t BufferLength)
Compares two buffers.
int | main (void)
Main program.
uint32_t | sEE_TIMEOUT_UserCallback (void)
Example of timeout situation management.

Variables

volatile uint16_t | NumDataRead = 0
uint8_t | Rx1_Buffer [BUFFER_SIZE1]
uint8_t | Rx2_Buffer [BUFFER_SIZE2]
volatile TestStatus | TransferStatus1 = FAILED
volatile TestStatus | TransferStatus2 = FAILED
uint8_t | Tx1_Buffer []
uint8_t | Tx2_Buffer []

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/I2C/EEPROM/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • I2C
  • I2C_TSENSOR
Defines | Enumerations | Functions | Variables

STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/main.c File Reference

Main program body. More...

#include "stm32f10x.h"
#include <stdlib.h>
#include "stm32_eval_i2c_tsensor.h"
#include "stm32_eval.h"

Go to the source code of this file.

Defines

#define | TEMPERATURE_THYS 31
#define | TEMPERATURE_TOS 32

Enumerations

enum TestStatus {
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED
}

Functions

int | main (void)
Main program.
void | NVIC_Configuration (void)
Configures the different interrupt.

Variables

uint32_t | index = 0
__IO uint8_t | SMbusAlertOccurred = 0
static uint8_t | TempCelsiusDisplay [] = " +abc.d C "
static uint8_t | TempFahrenheitDisplay [] = " +abc.d F "
static int32_t | TempValue = 0
static int32_t | TempValueCelsius = 0
static int32_t | TempValueFahrenheit = 0

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • I2C
  • IOExpander
Defines | Functions

STM32F10x_StdPeriph_Examples/I2C/IOExpander/main.c File Reference

Main program body. More...

#include "main.h"

Go to the source code of this file.

Defines

#define | MESSAGE2 " Example on how to "
#define | MESSAGE3 " use the IO Expander"

Functions

int | main (void)
Main program.

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/I2C/IOExpander/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • I2S
  • Interrupt
Enumerations | Functions | Variables

STM32F10x_StdPeriph_Examples/I2S/Interrupt/main.c File Reference

Main program body. More...

#include "stm32f10x.h"

Go to the source code of this file.

Enumerations

enum TestStatus {
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED
}

Functions

TestStatus | Buffercmp (uint16_t *pBuffer1, uint16_t *pBuffer2, uint16_t BufferLength)
Compares two buffers.
TestStatus | Buffercmp24bits (uint16_t *pBuffer1, uint16_t *pBuffer2, uint16_t BufferLength)
Compares two buffers in 24 bits data format.
void | GPIO_Configuration (void)
Configures the different GPIO ports.
int | main (void)
Main program.
void | NVIC_Configuration (void)
Configure the nested vectored interrupt controller.
void | RCC_Configuration (void)
Configures the different system clocks.

Variables

ErrorStatus HSEStartUpStatus
uint16_t | I2S2_Buffer_Rx [32]
const uint16_t | I2S3_Buffer_Tx [32]
I2S_InitTypeDef I2S_InitStructure
__IO uint32_t | RxIdx = 0
TestStatus | TransferStatus1 = FAILED
TestStatus | TransferStatus2 = FAILED
__IO uint32_t | TxIdx = 0

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/I2S/Interrupt/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • I2S
  • SPI_I2S_Switch
Defines | Enumerations | Functions | Variables

STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/main.c File Reference

Main program body. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | BufferSize 32

Enumerations

enum TestStatus {
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED
}

Functions

TestStatus | Buffercmp (uint16_t *pBuffer1, uint16_t *pBuffer2, uint16_t BufferLength)
Compares two buffers.
void | GPIO_Configuration (void)
Configures the different GPIO ports.
int | main (void)
Main program.
void | RCC_Configuration (void)
Configures the different system clocks.

Variables

ErrorStatus HSEStartUpStatus
__IO uint16_t | I2S2_Buffer_Rx [BufferSize]
uint16_t | I2S3_Buffer_Tx [BufferSize]
I2S_InitTypeDef I2S_InitStructure
__IO uint8_t | RxIdx = 0
__IO uint16_t | SPI2_Buffer_Rx [BufferSize]
uint16_t | SPI3_Buffer_Tx [BufferSize]
SPI_InitTypeDef SPI_InitStructure
volatile TestStatus | TransferStatus1 = FAILED
volatile TestStatus | TransferStatus2 = FAILED
volatile TestStatus | TransferStatus3 = FAILED
__IO uint8_t | TxIdx = 0

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • IWDG
  • IWDG_Reset
Defines | Functions | Variables

STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/main.c File Reference

Main program body. More...

#include "stm32f10x.h"
#include "stm32_eval.h"

Go to the source code of this file.

Defines

#define | LSI_TIM_MEASURE

Functions

void | Delay (__IO uint32_t nTime)
Inserts a delay time.
int | main (void)
Main program.
void | TIM5_ConfigForLSI (void)
Configures TIM5 to measure the LSI oscillator frequency.

Variables

__IO uint16_t | CaptureNumber
__IO uint32_t | LsiFreq = 40000
__IO uint32_t | TimingDelay = 0

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • Lib_DEBUG
  • RunTime_Check
Defines | Functions | Variables

STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/main.c File Reference

Main program body. More...

#include "stm32f10x.h"
#include "stm32f10x_ip_dbg.h"
#include "stm32_eval.h"
#include <stdio.h>

Go to the source code of this file.

Defines

#define | PUTCHAR_PROTOTYPE int fputc(int ch, FILE *f)

Functions

int | main (void)
Main program.

Variables

USART_InitTypeDef USART_InitStructure

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • NVIC
  • DMA_WFIMode
Defines | Functions | Variables

STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/main.c File Reference

Main program body. More...

#include "stm32f10x.h"
#include "stm32_eval.h"

Go to the source code of this file.

Defines

#define | USARTy_DMA1_Channel DMA1_Channel5
#define | USARTy_DMA1_IRQn DMA1_Channel5_IRQn
#define | USARTy_DR_Address 0x40013804

Functions

uint8_t | Buffercmp16 (uint16_t *pBuffer1, uint16_t *pBuffer2, uint16_t BufferLength)
Compares two buffers.
void | Delay (__IO uint32_t nCount)
Inserts a delay time.
void | DMA_Configuration (void)
Configures the used DMA Channel.
int | main (void)
Main program.
void | RCC_Configuration (void)
Configures the different system clocks.

Variables

DMA_InitTypeDef DMA_InitStructure
uint16_t | DST_Buffer [10] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
__IO uint32_t | LowPowerMode = 0
NVIC_InitTypeDef NVIC_InitStructure
USART_InitTypeDef USART_InitStructure

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • NVIC
  • IRQ_Mask
Functions

STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/main.c File Reference

Main program body. More...

#include "stm32f10x.h"
#include "stm32_eval.h"

Go to the source code of this file.

Functions

int | main (void)
Main program.
void | TIM_Config (void)
Configures the used Timers.

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • NVIC
  • IRQ_Priority
Functions | Variables

STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/main.c File Reference

Main program body. More...

#include "stm32f10x.h"
#include "stm32_eval.h"

Go to the source code of this file.

Functions

void | Delay (__IO uint32_t nCount)
Inserts a delay time.
int | main (void)
Main program.
void | NVIC_Config (void)
Configures the NVIC interrupts.

Variables

__IO uint8_t | PreemptionOccured = 0
__IO uint8_t | PreemptionPriorityValue = 0

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • NVIC
  • VectorTable_Relocation
Functions | Variables

STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/main.c File Reference

Main program body. More...

#include "main.h"

Go to the source code of this file.

Functions

void | Delay (__IO uint32_t nTime)
Inserts a delay time.
int | main (void)
Main program.
void | TimingDelay_Decrement (void)
Decrements the TimingDelay variable.

Variables

static __IO uint32_t | TimingDelay

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • PWR
  • PVD
Functions

STM32F10x_StdPeriph_Examples/PWR/PVD/main.c File Reference

Main program body. More...

#include "stm32f10x.h"
#include "stm32_eval.h"

Go to the source code of this file.

Functions

void | EXTI_Configuration (void)
Configures EXTI Lines.
int | main (void)
Main program.
void | NVIC_Configuration (void)
Configures NVIC and Vector Table base location.

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/PWR/PVD/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • PWR
  • STANDBY
Functions

STM32F10x_StdPeriph_Examples/PWR/STANDBY/main.c File Reference

Main program body. More...

#include "stm32f10x.h"
#include "stm32_eval.h"

Go to the source code of this file.

Functions

int | main (void)
Main program.
void | RTC_Configuration (void)
Configures RTC clock source and prescaler.
void | SysTick_Configuration (void)
Configures the SysTick to generate an interrupt each 250 ms.

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/PWR/STANDBY/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • PWR
  • STOP
Functions | Variables

STM32F10x_StdPeriph_Examples/PWR/STOP/main.c File Reference

Main program body. More...

#include "stm32f10x.h"
#include "stm32_eval.h"

Go to the source code of this file.

Functions

void | Delay (__IO uint32_t nTime)
Inserts a delay time.
void | EXTI_Configuration (void)
Configures EXTI Lines.
int | main (void)
Main program.
void | NVIC_Configuration (void)
Configures NVIC and Vector Table base location.
void | RTC_Configuration (void)
Configures RTC clock source and prescaler.
void | SYSCLKConfig_STOP (void)
Configures system clock after wake-up from STOP: enable HSE, PLL and select PLL as system clock source.
void | SysTick_Configuration (void)
Configures the SysTick to generate an interrupt each 1 millisecond.

Variables

ErrorStatus HSEStartUpStatus
__IO uint32_t | TimingDelay

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/PWR/STOP/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • RCC
  • RCC_ClockConfig
Defines | Functions | Variables

STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/main.c File Reference

Main program body. More...

#include "main.h"

Go to the source code of this file.

Defines

#define | DELAY_COUNT 0x3FFFF

Functions

void | Delay (__IO uint32_t nCount)
Inserts a delay time.
int | main (void)
Main program.
void | NVIC_Configuration (void)
Configures Vector Table base location.
void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SetSysClockTo24 (void)
Sets System clock frequency to 24MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
void | SetSysClockTo36 (void)
Sets System clock frequency to 36MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
void | SetSysClockTo48 (void)
Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
void | SetSysClockTo56 (void)
Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
void | SetSysClockTo72 (void)
Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
void | SetSysClockToHSE (void)
Selects HSE as System clock source and configure HCLK, PCLK2 and PCLK1 prescalers.

Variables

GPIO_InitTypeDef GPIO_InitStructure
ErrorStatus HSEStartUpStatus
RCC_ClocksTypeDef RCC_ClockFreq

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • RTC
  • Calendar
Defines | Functions | Variables

STM32F10x_StdPeriph_Examples/RTC/Calendar/main.c File Reference

Main program body. More...

#include "stm32f10x.h"
#include "stm32_eval.h"
#include <stdio.h>

Go to the source code of this file.

Defines

#define | PUTCHAR_PROTOTYPE int fputc(int ch, FILE *f)
#define | RTCClockOutput_Enable

Functions

int | main (void)
Main program.
void | NVIC_Configuration (void)
Configures the nested vectored interrupt controller.
void | RTC_Configuration (void)
Configures the RTC.
void | Time_Adjust (void)
Adjusts time.
void | Time_Display (uint32_t TimeVar)
Displays the current time.
uint32_t | Time_Regulate (void)
Returns the time entered by user, using Hyperterminal.
void | Time_Show (void)
Shows the current time (HH:MM:SS) on the Hyperterminal.
uint8_t | USART_Scanf (uint32_t value)

Variables

__IO uint32_t | TimeDisplay = 0
USART_InitTypeDef USART_InitStructure

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/RTC/Calendar/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • RTC
  • LSI_Calib
Defines | Functions | Variables

STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/main.c File Reference

Main program body. More...

#include "main.h"
#include <stdio.h>

Go to the source code of this file.

Defines

#define | RTCClockOutput_Enable

Functions

uint32_t | GetVar_OperationComplete (void)
Returns OperationComplete value.
uint32_t | IncrementVar_OperationComplete (void)
Increments OperationComplete variable and return its value before increment operation.
int | main (void)
Main program.
void | NVIC_Configuration (void)
Configures the nested vectored interrupt controller.
void | RTC_Configuration (void)
Configures the RTC.
void | SetVar_PeriodValue (uint32_t Value)
Sets the PeriodValue variable with input parameter.

Variables

__IO uint32_t | LsiFreq = 0
__IO uint32_t | OperationComplete = 0
__IO uint32_t | PeriodValue = 0
RCC_ClocksTypeDef RCC_Clocks
TIM_ICInitTypeDef TIM_ICInitStructure
TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • SDIO
  • uSDCard
Defines | Enumerations | Functions | Variables

STM32F10x_StdPeriph_Examples/SDIO/uSDCard/main.c File Reference

Main program body. More...

#include "stm32f10x.h"
#include "stm32_eval_sdio_sd.h"

Go to the source code of this file.

Defines

#define | BLOCK_SIZE 512
#define | MULTI_BUFFER_SIZE (BLOCK_SIZE * NUMBER_OF_BLOCKS)
#define | NUMBER_OF_BLOCKS 32
#define | SD_OPERATION_BLOCK 1
#define | SD_OPERATION_END 3
#define | SD_OPERATION_ERASE 0
#define | SD_OPERATION_MULTI_BLOCK 2

Enumerations

enum TestStatus {
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED
}

Functions

TestStatus | Buffercmp (uint8_t *pBuffer1, uint8_t *pBuffer2, uint32_t BufferLength)
Compares two buffers.
TestStatus | eBuffercmp (uint8_t *pBuffer, uint32_t BufferLength)
Checks if a buffer has all its values are equal to zero.
void | Fill_Buffer (uint8_t *pBuffer, uint32_t BufferLength, uint32_t Offset)
Fills buffer with user predefined data.
int | main (void)
Main program.
void | NVIC_Configuration (void)
Configures SDIO IRQ channel.
void | SD_EraseTest (void)
Tests the SD card erase operation.
void | SD_MultiBlockTest (void)
Tests the SD card Multiple Blocks operations.
void | SD_SingleBlockTest (void)
Tests the SD card Single Blocks operations.

Variables

uint8_t | Buffer_Block_Rx [BLOCK_SIZE]
uint8_t | Buffer_Block_Tx [BLOCK_SIZE]
uint8_t | Buffer_MultiBlock_Rx [MULTI_BUFFER_SIZE]
uint8_t | Buffer_MultiBlock_Tx [MULTI_BUFFER_SIZE]
volatile TestStatus | EraseStatus = FAILED
__IO uint32_t | SDCardOperation = SD_OPERATION_ERASE
SD_Error | Status = SD_OK
volatile TestStatus | TransferStatus1 = FAILED
volatile TestStatus | TransferStatus2 = FAILED

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/SDIO/uSDCard/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • SPI
  • CRC
Defines | Enumerations | Functions | Variables

STM32F10x_StdPeriph_Examples/SPI/CRC/main.c File Reference

Main program body. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | BufferSize 32

Enumerations

enum TestStatus {
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED
}

Functions

TestStatus | Buffercmp (uint16_t *pBuffer1, uint16_t *pBuffer2, uint16_t BufferLength)
Compares two buffers.
void | GPIO_Configuration (void)
Configures the different GPIO ports.
int | main (void)
Main program.
void | RCC_Configuration (void)
Configures the different system clocks.

Variables

__IO uint16_t | CRC1Value = 0
__IO uint16_t | CRC2Value = 0
uint32_t | RxIdx = 0
uint16_t | SPI1_Buffer_Rx [BufferSize]
uint16_t | SPI1_Buffer_Tx [BufferSize]
uint16_t | SPI2_Buffer_Rx [BufferSize]
uint16_t | SPI2_Buffer_Tx [BufferSize]
SPI_InitTypeDef SPI_InitStructure
volatile TestStatus | TransferStatus1 = FAILED
volatile TestStatus | TransferStatus2 = FAILED
uint32_t | TxIdx = 0

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/SPI/CRC/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • SPI
  • DMA
Defines | Enumerations | Functions | Variables

STM32F10x_StdPeriph_Examples/SPI/DMA/main.c File Reference

Main program body. More...

#include "stm32f10x.h"
#include "platform_config.h"

Go to the source code of this file.

Defines

#define | BufferSize 32

Enumerations

enum TestStatus {
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED
}

Functions

TestStatus | Buffercmp (uint8_t *pBuffer1, uint8_t *pBuffer2, uint16_t BufferLength)
Compares two buffers.
void | GPIO_Configuration (void)
Configures the different GPIO ports.
int | main (void)
Main program.
void | RCC_Configuration (void)
Configures the different system clocks.

Variables

DMA_InitTypeDef DMA_InitStructure
GPIO_InitTypeDef GPIO_InitStructure
SPI_InitTypeDef SPI_InitStructure
uint8_t | SPI_MASTER_Buffer_Tx [BufferSize]
uint8_t | SPI_SLAVE_Buffer_Rx [BufferSize]
volatile TestStatus | TransferStatus = FAILED
__IO uint8_t | TxIdx = 0

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/SPI/DMA/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • SPI
  • FullDuplex_SoftNSS
Defines | Enumerations | Functions | Variables

STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/main.c File Reference

Main program body. More...

#include "stm32f10x.h"
#include "platform_config.h"

Go to the source code of this file.

Defines

#define | BufferSize 32

Enumerations

enum TestStatus {
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED
}

Functions

TestStatus | Buffercmp (uint8_t *pBuffer1, uint8_t *pBuffer2, uint16_t BufferLength)
Compares two buffers.
void | GPIO_Configuration (uint16_t SPIy_Mode, uint16_t SPIz_Mode)
Configures the different SPIy and SPIz GPIO ports.
int | main (void)
Main program.
void | RCC_Configuration (void)
Configures the different system clocks.

Variables

__IO uint8_t | k = 0
__IO uint8_t | RxIdx = 0
SPI_InitTypeDef SPI_InitStructure
uint8_t | SPIy_Buffer_Rx [BufferSize]
uint8_t | SPIy_Buffer_Tx [BufferSize]
uint8_t | SPIz_Buffer_Rx [BufferSize]
uint8_t | SPIz_Buffer_Tx [BufferSize]
volatile TestStatus | TransferStatus1 = FAILED
volatile TestStatus | TransferStatus2 = FAILED
volatile TestStatus | TransferStatus3 = FAILED
volatile TestStatus | TransferStatus4 = FAILED
__IO uint8_t | TxIdx = 0

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • SPI
  • Simplex_Interrupt
Defines | Enumerations | Functions | Variables

STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/main.c File Reference

Main program body. More...

#include "stm32f10x.h"
#include "platform_config.h"

Go to the source code of this file.

Defines

#define | BufferSize 32

Enumerations

enum TestStatus {
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED
}

Functions

TestStatus | Buffercmp (uint8_t *pBuffer1, uint8_t *pBuffer2, uint16_t BufferLength)
Compares two buffers.
void | GPIO_Configuration (void)
Configures the different GPIO ports.
int | main (void)
Main program.
void | NVIC_Configuration (void)
Configure the nested vectored interrupt controller.
void | RCC_Configuration (void)
Configures the different system clocks.

Variables

__IO uint8_t | RxIdx = 0
SPI_InitTypeDef SPI_InitStructure
uint8_t | SPI_MASTER_Buffer_Tx [BufferSize]
uint8_t | SPI_SLAVE_Buffer_Rx [BufferSize]
volatile TestStatus | TransferStatus = FAILED
__IO uint8_t | TxIdx = 0

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • SPI
  • SPI_FLASH
Defines | Enumerations | Functions | Variables

STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/main.c File Reference

Main program body. More...

#include "stm32_eval.h"
#include "stm32_eval_spi_flash.h"

Go to the source code of this file.

Defines

#define | BufferSize (countof(Tx_Buffer)-1)
#define | countof(a) (sizeof(a) / sizeof(*(a)))
#define | FLASH_ReadAddress FLASH_WriteAddress
#define | FLASH_SectorToErase FLASH_WriteAddress
#define | FLASH_WriteAddress 0x700000
#define | sFLASH_ID sFLASH_M25P64_ID

Enumerations

enum TestStatus {
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED
}

Functions

TestStatus | Buffercmp (uint8_t *pBuffer1, uint8_t *pBuffer2, uint16_t BufferLength)
Compares two buffers.
int | main (void)
Main program.

Variables

__IO uint32_t | FlashID = 0
__IO uint8_t | Index = 0x0
uint8_t | Rx_Buffer [BufferSize]
volatile TestStatus | TransferStatus1 = FAILED
volatile TestStatus | TransferStatus2 = PASSED
uint8_t | Tx_Buffer [] = "STM32F10x SPI Firmware Library Example: communication with an M25P SPI FLASH"

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • SysTick
  • TimeBase
Functions | Variables

STM32F10x_StdPeriph_Examples/SysTick/TimeBase/main.c File Reference

Main program body. More...

#include "main.h"

Go to the source code of this file.

Functions

void | Delay (__IO uint32_t nTime)
Inserts a delay time.
int | main (void)
Main program.
void | TimingDelay_Decrement (void)
Decrements the TimingDelay variable.

Variables

static __IO uint32_t | TimingDelay

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/SysTick/TimeBase/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • TIM
  • 6Steps
Functions | Variables

STM32F10x_StdPeriph_Examples/TIM/6Steps/main.c File Reference

Main program body. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | GPIO_Configuration (void)
Configure the TIM1 Pins.
int | main (void)
Main program.
void | NVIC_Configuration (void)
Configures the nested vectored interrupt controller.
void | RCC_Configuration (void)
Configures the different system clocks.
void | SysTick_Configuration (void)
Configures the SysTick.

Variables

uint16_t | CCR1_Val = 32767
uint16_t | CCR2_Val = 24575
uint16_t | CCR3_Val = 16383
uint16_t | CCR4_Val = 8191
TIM_BDTRInitTypeDef TIM_BDTRInitStructure
TIM_OCInitTypeDef TIM_OCInitStructure
TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/TIM/6Steps/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • TIM
  • 7PWM_Output
Functions | Variables

STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/main.c File Reference

Main program body. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | GPIO_Configuration (void)
Configure the TIM1 Pins.
int | main (void)
Main program.
void | RCC_Configuration (void)
Configures the different system clocks.

Variables

uint16_t | Channel1Pulse = 0
uint16_t | Channel2Pulse = 0
uint16_t | Channel3Pulse = 0
uint16_t | Channel4Pulse = 0
TIM_OCInitTypeDef TIM_OCInitStructure
TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure
uint16_t | TimerPeriod = 0

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • TIM
  • Cascade_Synchro
Functions | Variables

STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/main.c File Reference

Main program body. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | GPIO_Configuration (void)
Configure the GPIOD Pins.
int | main (void)
Main program.
void | RCC_Configuration (void)
Configures the different system clocks.

Variables

TIM_OCInitTypeDef TIM_OCInitStructure
TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • TIM
  • ComplementarySignals
Functions | Variables

STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/main.c File Reference

Main program body. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | GPIO_Configuration (void)
Configure the TIM1 Pins.
int | main (void)
Main program.
void | RCC_Configuration (void)
Configures the different system clocks.

Variables

uint16_t | Channel1Pulse = 0
uint16_t | Channel2Pulse = 0
uint16_t | Channel3Pulse = 0
TIM_BDTRInitTypeDef TIM_BDTRInitStructure
TIM_OCInitTypeDef TIM_OCInitStructure
TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure
uint16_t | TimerPeriod = 0

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
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  • STM32F10x_StdPeriph_Examples
  • TIM
  • DMA
Defines | Functions | Variables

STM32F10x_StdPeriph_Examples/TIM/DMA/main.c File Reference

Main program body. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | TIM1_CCR3_Address 0x40012C3C

Functions

void | DMA_Configuration (void)
Configures the DMA.
void | GPIO_Configuration (void)
Configure the TIM1 Pins.
int | main (void)
Main program.
void | RCC_Configuration (void)
Configures the different system clocks.

Variables

uint16_t | SRC_Buffer [3] = {0, 0, 0}
TIM_OCInitTypeDef TIM_OCInitStructure
TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure
uint16_t | TimerPeriod = 0

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/TIM/DMA/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • TIM
  • DMABurst
Defines | Functions | Variables

STM32F10x_StdPeriph_Examples/TIM/DMABurst/main.c File Reference

Main program body. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | TIM1_DMAR_ADDRESS ((uint32_t)0x40012C4C)

Functions

int | main (void)
Main program.

Variables

DMA_InitTypeDef DMA_InitStructure
GPIO_InitTypeDef GPIO_InitStructure
uint16_t | SRC_Buffer [6] = {0x0FFF, 0x0000, 0x0555}
TIM_OCInitTypeDef TIM_OCInitStructure
TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/TIM/DMABurst/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • TIM
  • ExtTrigger_Synchro
Functions | Variables

STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/main.c File Reference

Main program body. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | GPIO_Configuration (void)
Configure the GPIO Pins.
int | main (void)
Main program.
void | RCC_Configuration (void)
Configures the different system clocks.

Variables

TIM_ICInitTypeDef TIM_ICInitStructure
TIM_OCInitTypeDef TIM_OCInitStructure
TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • TIM
  • InputCapture
Functions | Variables

STM32F10x_StdPeriph_Examples/TIM/InputCapture/main.c File Reference

Main program body. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | GPIO_Configuration (void)
Configure the GPIOD Pins.
int | main (void)
Main program.
void | NVIC_Configuration (void)
Configure the nested vectored interrupt controller.
void | RCC_Configuration (void)
Configures the different system clocks.

Variables

TIM_ICInitTypeDef TIM_ICInitStructure

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/TIM/InputCapture/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • TIM
  • OCActive
Functions | Variables

STM32F10x_StdPeriph_Examples/TIM/OCActive/main.c File Reference

Main program body. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | GPIO_Configuration (void)
Configure the TIM3 and the GPIOE Pins.
int | main (void)
Main program.
void | RCC_Configuration (void)
Configures the different system clocks.

Variables

uint16_t | CCR1_Val = 1000
uint16_t | CCR2_Val = 500
uint16_t | CCR3_Val = 250
uint16_t | CCR4_Val = 125
uint16_t | PrescalerValue = 0
TIM_OCInitTypeDef TIM_OCInitStructure
TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/TIM/OCActive/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • TIM
  • OCInactive
Functions | Variables

STM32F10x_StdPeriph_Examples/TIM/OCInactive/main.c File Reference

Main program body. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | GPIO_Configuration (void)
Configure the GPIOD Pins.
int | main (void)
Main program.
void | NVIC_Configuration (void)
Configure the nested vectored interrupt controller.
void | RCC_Configuration (void)
Configures the different system clocks.

Variables

uint16_t | CCR1_Val = 1000
uint16_t | CCR2_Val = 500
uint16_t | CCR3_Val = 250
uint16_t | CCR4_Val = 125
uint16_t | PrescalerValue = 0
TIM_OCInitTypeDef TIM_OCInitStructure
TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/TIM/OCInactive/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • TIM
  • OCToggle
Functions | Variables

STM32F10x_StdPeriph_Examples/TIM/OCToggle/main.c File Reference

Main program body. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | GPIO_Configuration (void)
Configure the TIM3 Pins.
int | main (void)
Main program.
void | NVIC_Configuration (void)
Configure the nested vectored interrupt controller.
void | RCC_Configuration (void)
Configures the different system clocks.

Variables

__IO uint16_t | CCR1_Val = 32768
__IO uint16_t | CCR2_Val = 16384
__IO uint16_t | CCR3_Val = 8192
__IO uint16_t | CCR4_Val = 4096
uint16_t | PrescalerValue = 0
TIM_OCInitTypeDef TIM_OCInitStructure
TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/TIM/OCToggle/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • TIM
  • OnePulse
Functions | Variables

STM32F10x_StdPeriph_Examples/TIM/OnePulse/main.c File Reference

Main program body. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | GPIO_Configuration (void)
Configure the GPIOD Pins.
int | main (void)
Main program.
void | RCC_Configuration (void)
Configures the different system clocks.

Variables

uint16_t | PrescalerValue = 0
TIM_ICInitTypeDef TIM_ICInitStructure
TIM_OCInitTypeDef TIM_OCInitStructure
TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/TIM/OnePulse/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • TIM
  • Parallel_Synchro
Functions | Variables

STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/main.c File Reference

Main program body. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | GPIO_Configuration (void)
Configure the GPIO Pins.
int | main (void)
Main program.
void | RCC_Configuration (void)
Configures the different system clocks.

Variables

TIM_OCInitTypeDef TIM_OCInitStructure
TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • TIM
  • PWM_Input
Functions | Variables

STM32F10x_StdPeriph_Examples/TIM/PWM_Input/main.c File Reference

Main program body. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | GPIO_Configuration (void)
Configure the GPIO Pins.
int | main (void)
Main program.
void | NVIC_Configuration (void)
Configure the nested vectored interrupt controller.
void | RCC_Configuration (void)
Configures the different system clocks.

Variables

TIM_ICInitTypeDef TIM_ICInitStructure

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/TIM/PWM_Input/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • TIM
  • PWM_Output
Functions | Variables

STM32F10x_StdPeriph_Examples/TIM/PWM_Output/main.c File Reference

Main program body. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | GPIO_Configuration (void)
Configure the TIM3 Ouput Channels.
int | main (void)
Main program.
void | RCC_Configuration (void)
Configures the different system clocks.

Variables

uint16_t | CCR1_Val = 333
uint16_t | CCR2_Val = 249
uint16_t | CCR3_Val = 166
uint16_t | CCR4_Val = 83
uint16_t | PrescalerValue = 0
TIM_OCInitTypeDef TIM_OCInitStructure
TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/TIM/PWM_Output/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • TIM
  • TIM10_PWMOutput
Functions | Variables

STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/main.c File Reference

Main program body. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | GPIO_Configuration (void)
Configure TIM10 pin.
int | main (void)
Main program.
void | RCC_Configuration (void)
Configures the different system clocks.

Variables

uint16_t | CCR1Val = 249
uint16_t | PrescalerValue = 0
TIM_OCInitTypeDef TIM_OCInitStructure
TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • TIM
  • TIM15_ComplementarySignals
Functions | Variables

STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/main.c File Reference

Main program body. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | GPIO_Configuration (void)
Configure the TIM1 Pins.
int | main (void)
Main program.
void | RCC_Configuration (void)
Configures the different system clocks.

Variables

uint16_t | CCR1_Val = 32767
TIM_BDTRInitTypeDef TIM_BDTRInitStructure
TIM_OCInitTypeDef TIM_OCInitStructure
TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • TIM
  • TIM1_Synchro
Functions | Variables

STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/main.c File Reference

Main program body. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | GPIO_Configuration (void)
Configures TIM1, TIM3 and TIM4 Pins.
int | main (void)
Main program.
void | RCC_Configuration (void)
Configures the different system clocks.

Variables

TIM_BDTRInitTypeDef TIM_BDTRInitStructure
TIM_OCInitTypeDef TIM_OCInitStructure
TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • TIM
  • TIM9_OCToggle
Functions | Variables

STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/main.c File Reference

Main program body. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | GPIO_Configuration (void)
Configure TIM9 pins.
int | main (void)
Main program.
void | NVIC_Configuration (void)
Configure the nested vectored interrupt controller.

Variables

__IO uint16_t | CCR1Val = 32768
__IO uint16_t | CCR2Val = 16384
uint16_t | PrescalerValue = 0
TIM_OCInitTypeDef TIM_OCInitStructure
TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • TIM
  • TimeBase
Functions | Variables

STM32F10x_StdPeriph_Examples/TIM/TimeBase/main.c File Reference

Main program body. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | GPIO_Configuration (void)
Configure the GPIO Pins.
int | main (void)
Main program.
void | NVIC_Configuration (void)
Configure the nested vectored interrupt controller.
void | RCC_Configuration (void)
Configures the different system clocks.

Variables

__IO uint16_t | CCR1_Val = 40961
__IO uint16_t | CCR2_Val = 27309
__IO uint16_t | CCR3_Val = 13654
__IO uint16_t | CCR4_Val = 6826
uint16_t | PrescalerValue = 0
TIM_OCInitTypeDef TIM_OCInitStructure
TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/TIM/TimeBase/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • USART
  • DMA_Interrupt
Defines | Enumerations | Functions | Variables

STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/main.c File Reference

Main program body. More...

#include "stm32f10x.h"
#include "platform_config.h"

Go to the source code of this file.

Defines

#define | countof(a) (sizeof(a) / sizeof(*(a)))
#define | TxBufferSize1 (countof(TxBuffer1) - 1)
#define | TxBufferSize2 (countof(TxBuffer2) - 1)

Enumerations

enum TestStatus {
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED
}

Functions

TestStatus | Buffercmp (uint8_t *pBuffer1, uint8_t *pBuffer2, uint16_t BufferLength)
Compares two buffers.
void | DMA_Configuration (void)
Configures the DMA.
void | GPIO_Configuration (void)
Configures the different GPIO ports.
int | main (void)
Main program.
void | NVIC_Configuration (void)
Configures the nested vectored interrupt controller.
void | RCC_Configuration (void)
Configures the different system clocks.

Variables

uint32_t | index = 0
uint8_t | NbrOfDataToRead = TxBufferSize1
uint8_t | RxBuffer1 [TxBufferSize2]
uint8_t | RxBuffer2 [TxBufferSize1]
volatile TestStatus | TransferStatus1 = FAILED
volatile TestStatus | TransferStatus2 = FAILED
uint8_t | TxBuffer1 [] = "USART DMA Interrupt: USARTy -> USARTz using DMA Tx and Rx Flag"
uint8_t | TxBuffer2 [] = "USART DMA Interrupt: USARTz -> USARTy using DMA Tx and Rx Interrupt"
USART_InitTypeDef USART_InitStructure

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • USART
  • DMA_Polling
Defines | Enumerations | Functions | Variables

STM32F10x_StdPeriph_Examples/USART/DMA_Polling/main.c File Reference

Main program body. More...

#include "stm32f10x.h"
#include "platform_config.h"

Go to the source code of this file.

Defines

#define | countof(a) (sizeof(a) / sizeof(*(a)))
#define | TxBufferSize1 (countof(TxBuffer1) - 1)
#define | TxBufferSize2 (countof(TxBuffer2) - 1)

Enumerations

enum TestStatus {
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED
}

Functions

TestStatus | Buffercmp (uint8_t *pBuffer1, uint8_t *pBuffer2, uint16_t BufferLength)
Compares two buffers.
void | DMA_Configuration (void)
Configures the DMA.
void | GPIO_Configuration (void)
Configures the different GPIO ports.
int | main (void)
Main program.
void | RCC_Configuration (void)
Configures the different system clocks.

Variables

uint8_t | RxBuffer1 [TxBufferSize2]
uint8_t | RxBuffer2 [TxBufferSize1]
volatile TestStatus | TransferStatus1 = FAILED
volatile TestStatus | TransferStatus2 = FAILED
uint8_t | TxBuffer1 [] = "USART DMA Polling: USARTy -> USARTz using DMA"
uint8_t | TxBuffer2 [] = "USART DMA Polling: USARTz -> USARTy using DMA"
USART_InitTypeDef USART_InitStructure

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/USART/DMA_Polling/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • USART
  • HalfDuplex
Defines | Enumerations | Functions | Variables

STM32F10x_StdPeriph_Examples/USART/HalfDuplex/main.c File Reference

Main program body. More...

#include "stm32f10x.h"
#include "platform_config.h"

Go to the source code of this file.

Defines

#define | countof(a) (sizeof(a) / sizeof(*(a)))
#define | TxBufferSize1 (countof(TxBuffer1) - 1)
#define | TxBufferSize2 (countof(TxBuffer2) - 1)

Enumerations

enum TestStatus {
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED
}

Functions

TestStatus | Buffercmp (uint8_t *pBuffer1, uint8_t *pBuffer2, uint16_t BufferLength)
Compares two buffers.
void | GPIO_Configuration (void)
Configures the different GPIO ports.
int | main (void)
Main program.
void | RCC_Configuration (void)
Configures the different system clocks.

Variables

uint32_t | NbrOfDataToRead1 = TxBufferSize2
uint32_t | NbrOfDataToRead2 = TxBufferSize1
uint8_t | RxBuffer1 [TxBufferSize2]
uint8_t | RxBuffer2 [TxBufferSize1]
uint8_t | RxCounter1 = 0
uint8_t | RxCounter2 = 0
volatile TestStatus | TransferStatus1 = FAILED
volatile TestStatus | TransferStatus2 = FAILED
uint8_t | TxBuffer1 [] = "USART Half Duplex: USARTy -> USARTz using HalfDuplex mode"
uint8_t | TxBuffer2 [] = "USART Half Duplex: USARTz -> USARTy using HalfDuplex mode"
uint8_t | TxCounter1 = 0
uint8_t | TxCounter2 = 0
USART_InitTypeDef USART_InitStructure

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/USART/HalfDuplex/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • USART
  • HyperTerminal_HwFlowControl
Defines | Functions | Variables

STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/main.c File Reference

Main program body. More...

#include "stm32f10x.h"
#include "platform_config.h"

Go to the source code of this file.

Defines

#define | countof(a) (sizeof(a) / sizeof(*(a)))
#define | RxBufferSize 0xFF
#define | TxBufferSize (countof(TxBuffer) - 1)

Functions

void | GPIO_Configuration (void)
Configures the different GPIO ports.
int | main (void)
Main program.
void | RCC_Configuration (void)
Configures the different system clocks.

Variables

uint8_t | NbrOfDataToTransfer = TxBufferSize
uint8_t | RxBuffer [RxBufferSize]
uint8_t | RxCounter = 0
uint8_t | TxBuffer []
uint8_t | TxCounter = 0
USART_InitTypeDef USART_InitStructure

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • USART
  • HyperTerminal_Interrupt
Defines | Functions | Variables

STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/main.c File Reference

Main program body. More...

#include "stm32f10x.h"
#include "stm32_eval.h"

Go to the source code of this file.

Defines

#define | USARTx_IRQn USART1_IRQn

Functions

int | main (void)
Main program.
void | NVIC_Configuration (void)
Configures the nested vectored interrupt controller.

Variables

USART_InitTypeDef USART_InitStructure

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • USART
  • Interrupt
Defines | Enumerations | Functions | Variables

STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c File Reference

Main program body. More...

#include "stm32f10x.h"
#include "platform_config.h"

Go to the source code of this file.

Defines

#define | countof(a) (sizeof(a) / sizeof(*(a)))
#define | RxBufferSize1 TxBufferSize2
#define | RxBufferSize2 TxBufferSize1
#define | TxBufferSize1 (countof(TxBuffer1) - 1)
#define | TxBufferSize2 (countof(TxBuffer2) - 1)

Enumerations

enum TestStatus {
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED
}

Functions

TestStatus | Buffercmp (uint8_t *pBuffer1, uint8_t *pBuffer2, uint16_t BufferLength)
Compares two buffers.
void | GPIO_Configuration (void)
Configures the different GPIO ports.
int | main (void)
Main program.
void | NVIC_Configuration (void)
Configures the nested vectored interrupt controller.
void | RCC_Configuration (void)
Configures the different system clocks.

Variables

uint8_t | NbrOfDataToRead1 = RxBufferSize1
uint8_t | NbrOfDataToRead2 = RxBufferSize2
uint8_t | NbrOfDataToTransfer1 = TxBufferSize1
uint8_t | NbrOfDataToTransfer2 = TxBufferSize2
uint8_t | RxBuffer1 [RxBufferSize1]
uint8_t | RxBuffer2 [RxBufferSize2]
__IO uint8_t | RxCounter1 = 0x00
__IO uint8_t | RxCounter2 = 0x00
__IO TestStatus | TransferStatus1 = FAILED
__IO TestStatus | TransferStatus2 = FAILED
uint8_t | TxBuffer1 [] = "USART Interrupt Example: USARTy -> USARTz using Interrupt"
uint8_t | TxBuffer2 [] = "USART Interrupt Example: USARTz -> USARTy using Interrupt"
__IO uint8_t | TxCounter1 = 0x00
__IO uint8_t | TxCounter2 = 0x00
USART_InitTypeDef USART_InitStructure

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • USART
  • IrDA
  • Receive
Functions | Variables

STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/main.c File Reference

Main program body. More...

#include "stm32f10x.h"
#include "platform_config.h"

Go to the source code of this file.

Functions

void | GPIO_Configuration (void)
Configures the different GPIO ports.
int | main (void)
Main program.
void | RCC_Configuration (void)
Configures the different system clocks.

Variables

JOYState_TypeDef | ReceivedData = JOY_NONE
USART_InitTypeDef USART_InitStructure

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • USART
  • IrDA
  • Transmit
Functions | Variables

STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/main.c File Reference

Main program body. More...

#include "stm32f10x.h"
#include "platform_config.h"

Go to the source code of this file.

Functions

void | GPIO_Configuration (void)
Configures the different GPIO ports.
int | main (void)
Main program.
void | RCC_Configuration (void)
Configures the different system clocks.
JOYState_TypeDef | ReadKey (void)
Reads key from board.

Variables

JOYState_TypeDef | MyKey = JOY_NONE
USART_InitTypeDef USART_InitStructure

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • USART
  • MultiProcessor
Functions | Variables

STM32F10x_StdPeriph_Examples/USART/MultiProcessor/main.c File Reference

Main program body. More...

#include "stm32f10x.h"
#include "platform_config.h"

Go to the source code of this file.

Functions

void | Delay (__IO uint32_t nCount)
Inserts a delay time.
void | GPIO_Configuration (void)
Configures the different GPIO ports.
int | main (void)
Main program.
void | RCC_Configuration (void)
Configures the different system clocks.

Variables

USART_InitTypeDef USART_InitStructure

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/USART/MultiProcessor/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • USART
  • Polling
Defines | Enumerations | Functions | Variables

STM32F10x_StdPeriph_Examples/USART/Polling/main.c File Reference

Main program body. More...

#include "stm32f10x.h"
#include "platform_config.h"

Go to the source code of this file.

Defines

#define | countof(a) (sizeof(a) / sizeof(*(a)))
#define | TxBufferSize (countof(TxBuffer))

Enumerations

enum TestStatus {
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED
}

Functions

TestStatus | Buffercmp (uint8_t *pBuffer1, uint8_t *pBuffer2, uint16_t BufferLength)
Compares two buffers.
void | GPIO_Configuration (void)
Configures the different GPIO ports.
int | main (void)
Main program.
void | RCC_Configuration (void)
Configures the different system clocks.

Variables

__IO uint8_t | index = 0
uint8_t | RxBuffer [TxBufferSize]
__IO uint8_t | RxCounter = 0
volatile TestStatus | TransferStatus = FAILED
uint8_t | TxBuffer [] = "Buffer Send from USARTy to USARTz using Flags"
__IO uint8_t | TxCounter = 0
USART_InitTypeDef USART_InitStructure

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/USART/Polling/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • USART
  • Printf
Defines | Functions | Variables

STM32F10x_StdPeriph_Examples/USART/Printf/main.c File Reference

Main program body. More...

#include "stm32f10x.h"
#include "stm32_eval.h"
#include <stdio.h>

Go to the source code of this file.

Defines

#define | PUTCHAR_PROTOTYPE int fputc(int ch, FILE *f)

Functions

int | main (void)
Main program.

Variables

USART_InitTypeDef USART_InitStructure

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/USART/Printf/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • USART
  • Smartcard
Data Structures | Defines | Enumerations | Functions | Variables

STM32F10x_StdPeriph_Examples/USART/Smartcard/main.c File Reference

Main program body. More...

#include "stm32f10x.h"
#include "platform_config.h"

Go to the source code of this file.

Data Structures

struct | SC_ATR

Defines

#define | HIST_LENGHT 20
#define | SC_Receive_Timeout 0x4000
#define | SETUP_LENGHT 20
#define | T0_PROTOCOL 0x00

Enumerations

enum TestStatus {
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED
}

Functions

void | EXTI_Configuration (void)
Configures the External Interrupts controller.
void | GPIO_Configuration (void)
Configures the different GPIO ports.
int | main (void)
Main program.
void | NVIC_Configuration (void)
Configures the nested vectored interrupt controller.
void | RCC_Configuration (void)
Configures the different system clocks.
uint8_t | SC_decode_Answer2reset (__IO uint8_t *card)
Decode the Card ATR Response.

Variables

volatile TestStatus | ATRDecodeStatus = FAILED
__IO uint32_t | CardInserted = 0
__IO uint32_t | CardProtocol = 1
__IO uint32_t | Counter = 0
__IO uint8_t | DST_Buffer [50]
__IO uint32_t | index = 0
SC_ATR SC_A2R
USART_ClockInitTypeDef USART_ClockInitStructure
USART_InitTypeDef USART_InitStructure

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/USART/Smartcard/main.c.

Define Documentation

#define HIST_LENGHT 20

Definition at line 29 of file STM32F10x_StdPeriph_Examples/USART/Smartcard/main.c.

Referenced by SC_decode_Answer2reset().

#define SC_Receive_Timeout 0x4000

Definition at line 30 of file STM32F10x_StdPeriph_Examples/USART/Smartcard/main.c.

Referenced by main().

#define SETUP_LENGHT 20

Definition at line 28 of file STM32F10x_StdPeriph_Examples/USART/Smartcard/main.c.

Referenced by SC_decode_Answer2reset().

#define T0_PROTOCOL 0x00

Definition at line 27 of file STM32F10x_StdPeriph_Examples/USART/Smartcard/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • USART
  • Synchronous
Defines | Enumerations | Functions | Variables

STM32F10x_StdPeriph_Examples/USART/Synchronous/main.c File Reference

Main program body. More...

#include "stm32f10x.h"
#include "platform_config.h"

Go to the source code of this file.

Defines

#define | countof(a) (sizeof(a) / sizeof(*(a)))
#define | DYMMY_BYTE 0x00
#define | TxBufferSize1 (countof(TxBuffer1) - 1)
#define | TxBufferSize2 (countof(TxBuffer2) - 1)

Enumerations

enum TestStatus {
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED,
FAILED = 0, PASSED = !FAILED, FAILED = 0, PASSED = !FAILED
}

Functions

TestStatus | Buffercmp (uint8_t *pBuffer1, uint8_t *pBuffer2, uint16_t BufferLength)
Compares two buffers.
void | GPIO_Configuration (void)
Configures the different GPIO ports.
int | main (void)
Main program.
void | RCC_Configuration (void)
Configures the different system clocks.
void | SPI_Configuration (void)
Configures the SPI.

Variables

__IO uint8_t | NbrOfDataToRead1 = TxBufferSize2
__IO uint8_t | NbrOfDataToRead2 = TxBufferSize1
uint8_t | RxBuffer1 [TxBufferSize2]
uint8_t | RxBuffer2 [TxBufferSize1]
__IO uint8_t | RxCounter1 = 0
__IO uint8_t | RxCounter2 = 0
volatile TestStatus | TransferStatus1 = FAILED
volatile TestStatus | TransferStatus2 = FAILED
uint8_t | TxBuffer1 [] = "USART Synchronous Example: USARTy -> SPIy using TXE and RXNE Flags"
uint8_t | TxBuffer2 [] = "USART Synchronous Example: SPIy -> USARTy using TXE and RXNE Flags"
__IO uint8_t | TxCounter1 = 0
__IO uint8_t | TxCounter2 = 0
USART_ClockInitTypeDef USART_ClockInitStructure
USART_InitTypeDef USART_InitStructure

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/USART/Synchronous/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • WWDG
  • WWDG_Reset
Functions | Variables

STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/main.c File Reference

Main program body. More...

#include "stm32f10x.h"
#include "stm32_eval.h"

Go to the source code of this file.

Functions

void | Delay (__IO uint32_t nTime)
Inserts a delay time.
int | main (void)
Main program.

Variables

__IO uint32_t | TimingDelay = 0

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/main.c.


STM32F10x Standard Peripherals Firmware Library: main.c File Reference

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Template
Defines | Functions | Variables

STM32F10x_StdPeriph_Template/main.c File Reference

Main program body. More...

#include "stm32f10x.h"
#include "stm32_eval.h"
#include <stdio.h>

Go to the source code of this file.

Defines

#define | PUTCHAR_PROTOTYPE int fputc(int ch, FILE *f)

Functions

int | main (void)
Main program.

Variables

USART_InitTypeDef USART_InitStructure

Detailed Description

Main program body.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Template/main.c.


STM32F10x Standard Peripherals Firmware Library: main.h File Reference

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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • BKP
  • Tamper
Functions

BKP/Tamper/main.h File Reference

Header for main.c module. More...

#include "stm32f10x.h"
#include "stm32_eval.h"

Go to the source code of this file.

Functions

uint32_t IsBackupRegReset (void)
Checks if the Backup DRx registers are reset or not.

Detailed Description

Header for main.c module.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file BKP/Tamper/main.h.


STM32F10x Standard Peripherals Firmware Library: main.h File Reference

  • File List
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  • Project
  • STM32F10x_StdPeriph_Examples
  • CortexM3
  • MPU
Defines | Functions

CortexM3/MPU/main.h File Reference

Header for main.c module. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | FLASH_ADDRESS_START (0x08000000)
#define | FLASH_REGION_NUMBER (0x01UL << MPU_RNR_REGION_Pos)
#define | FLASH_SIZE (0x27UL << 0UL)
#define | PERIPH_ADDRESS_START (0x40000000)
#define | PERIPH_REGION_NUMBER (0x02UL << MPU_RNR_REGION_Pos)
#define | PERIPH_SIZE (0x39UL << 0UL)
#define | portMPU_REGION_PRIVILEGED_READ_ONLY (0x05UL << MPU_RASR_AP_Pos)
#define | portMPU_REGION_PRIVILEGED_READ_WRITE (0x01UL << MPU_RASR_AP_Pos)
#define | portMPU_REGION_READ_ONLY (0x06UL << MPU_RASR_AP_Pos)
#define | portMPU_REGION_READ_WRITE (0x03UL << MPU_RASR_AP_Pos)
#define | RAM_ADDRESS_START (0x20000000UL)
#define | RAM_REGION_NUMBER (0x00UL << MPU_RNR_REGION_Pos)
#define | RAM_SIZE (0x19UL << 0UL)

Functions

void | accesspermission (void)
This function configure the access right using Cortex-M3 MPU regions.

Detailed Description

Header for main.c module.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file CortexM3/MPU/main.h.

Define Documentation

#define FLASH_ADDRESS_START (0x08000000)

Definition at line 38 of file CortexM3/MPU/main.h.

Referenced by MPU_SETUP().

#define FLASH_REGION_NUMBER (0x01UL << MPU_RNR_REGION_Pos)

Definition at line 45 of file CortexM3/MPU/main.h.

Referenced by MPU_SETUP().

#define FLASH_SIZE (0x27UL << 0UL)

Definition at line 39 of file CortexM3/MPU/main.h.

Referenced by MPU_SETUP().

#define PERIPH_ADDRESS_START (0x40000000)

Definition at line 36 of file CortexM3/MPU/main.h.

Referenced by MPU_SETUP().

#define PERIPH_REGION_NUMBER (0x02UL << MPU_RNR_REGION_Pos)

Definition at line 46 of file CortexM3/MPU/main.h.

Referenced by MPU_SETUP().

#define PERIPH_SIZE (0x39UL << 0UL)

Definition at line 37 of file CortexM3/MPU/main.h.

Referenced by MPU_SETUP().

#define portMPU_REGION_PRIVILEGED_READ_ONLY (0x05UL << MPU_RASR_AP_Pos)

Definition at line 41 of file CortexM3/MPU/main.h.

Referenced by accesspermission().

#define portMPU_REGION_PRIVILEGED_READ_WRITE (0x01UL << MPU_RASR_AP_Pos)

Definition at line 43 of file CortexM3/MPU/main.h.

#define portMPU_REGION_READ_ONLY (0x06UL << MPU_RASR_AP_Pos)

Definition at line 42 of file CortexM3/MPU/main.h.

#define portMPU_REGION_READ_WRITE (0x03UL << MPU_RASR_AP_Pos)

Definition at line 40 of file CortexM3/MPU/main.h.

Referenced by MPU_SETUP().

#define RAM_ADDRESS_START (0x20000000UL)

Definition at line 34 of file CortexM3/MPU/main.h.

Referenced by MPU_SETUP().

#define RAM_REGION_NUMBER (0x00UL << MPU_RNR_REGION_Pos)

Definition at line 44 of file CortexM3/MPU/main.h.

Referenced by MPU_SETUP().

#define RAM_SIZE (0x19UL << 0UL)

Definition at line 35 of file CortexM3/MPU/main.h.

Referenced by MPU_SETUP().


STM32F10x Standard Peripherals Firmware Library: main.h File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • FLASH
  • Dual_Boot
Functions

FLASH/Dual_Boot/main.h File Reference

Header for main.c module. More...

#include "stm32f10x.h"
#include "stm32_eval.h"
#include "stm3210e_eval_lcd.h"

Go to the source code of this file.

Functions

void TimingDelay_Decrement (void)
Decrements the TimingDelay variable.

Detailed Description

Header for main.c module.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file FLASH/Dual_Boot/main.h.


STM32F10x Standard Peripherals Firmware Library: main.h File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • I2C
  • IOExpander
Defines

I2C/IOExpander/main.h File Reference

Header for main.c module. More...

#include "stm32f10x.h"
#include "stm32_eval.h"
#include <stdio.h>

Go to the source code of this file.

Defines

#define IOE_INTERRUPT_MODE

Detailed Description

Header for main.c module.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file I2C/IOExpander/main.h.

Define Documentation

#define IOE_INTERRUPT_MODE

Definition at line 49 of file I2C/IOExpander/main.h.


STM32F10x Standard Peripherals Firmware Library: main.h File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • NVIC
  • VectorTable_Relocation
Functions

NVIC/VectorTable_Relocation/main.h File Reference

Header for main.c module. More...

#include "stm32f10x.h"
#include "stm32_eval.h"

Go to the source code of this file.

Functions

void TimingDelay_Decrement (void)
Decrements the TimingDelay variable.

Detailed Description

Header for main.c module.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file NVIC/VectorTable_Relocation/main.h.


STM32F10x Standard Peripherals Firmware Library: main.h File Reference

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • RCC
  • RCC_ClockConfig
Defines

RCC/RCC_ClockConfig/main.h File Reference

Header for main.c module. More...

#include "stm32f10x.h"
#include "stm32_eval.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_24MHz
#define | SYSCLK_FREQ_72MHz

Detailed Description

Header for main.c module.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file RCC/RCC_ClockConfig/main.h.

Define Documentation

#define SYSCLK_FREQ_24MHz

Definition at line 35 of file RCC/RCC_ClockConfig/main.h.

#define SYSCLK_FREQ_72MHz

Definition at line 41 of file RCC/RCC_ClockConfig/main.h.


STM32F10x Standard Peripherals Firmware Library: main.h File Reference

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • RTC
  • LSI_Calib
Functions

RTC/LSI_Calib/main.h File Reference

Header file for main.c. More...

#include "stm32f10x.h"
#include "stm32_eval.h"

Go to the source code of this file.

Functions

uint32_t | GetVar_OperationComplete (void)
Returns OperationComplete value.
uint32_t | IncrementVar_OperationComplete (void)
Increments OperationComplete variable and return its value before increment operation.
void | SetVar_PeriodValue (uint32_t Value)
Sets the PeriodValue variable with input parameter.

Detailed Description

Header file for main.c.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file RTC/LSI_Calib/main.h.


STM32F10x Standard Peripherals Firmware Library: main.h File Reference

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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • SysTick
  • TimeBase
Functions

SysTick/TimeBase/main.h File Reference

Header for main.c module. More...

#include "stm32f10x.h"
#include "stm32_eval.h"

Go to the source code of this file.

Functions

void TimingDelay_Decrement (void)
Decrements the TimingDelay variable.

Detailed Description

Header for main.c module.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file SysTick/TimeBase/main.h.


STM32F10x Standard Peripherals Firmware Library: misc.c File Reference

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  • Libraries
  • STM32F10x_StdPeriph_Driver
  • src
Defines | Functions

misc.c File Reference

This file provides all the miscellaneous firmware functions (add-on to CMSIS functions). More...

#include "misc.h"

Go to the source code of this file.

Defines

#define | AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)

Functions

void | NVIC_Init (NVIC_InitTypeDef *NVIC_InitStruct)
Initializes the NVIC peripheral according to the specified parameters in the NVIC_InitStruct.
void | NVIC_PriorityGroupConfig (uint32_t NVIC_PriorityGroup)
Configures the priority grouping: pre-emption priority and subpriority.
void | NVIC_SetVectorTable (uint32_t NVIC_VectTab, uint32_t Offset)
Sets the vector table location and Offset.
void | NVIC_SystemLPConfig (uint8_t LowPowerMode, FunctionalState NewState)
Selects the condition for the system to enter low power mode.
void | SysTick_CLKSourceConfig (uint32_t SysTick_CLKSource)
Configures the SysTick clock source.

Detailed Description

This file provides all the miscellaneous firmware functions (add-on to CMSIS functions).

Author:
MCD Application Team
Version:
V3.5.0
Date:
11-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file misc.c.


STM32F10x Standard Peripherals Firmware Library: misc.h File Reference

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  • inc
Data Structures | Defines | Functions

misc.h File Reference

This file contains all the functions prototypes for the miscellaneous firmware library functions (add-on to CMSIS functions). More...

#include "stm32f10x.h"

Go to the source code of this file.

Data Structures

struct | NVIC_InitTypeDef
NVIC Init Structure definition. More...

Defines

#define | IS_NVIC_LP(LP)
#define | IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF)
#define | IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
#define | IS_NVIC_PRIORITY_GROUP(GROUP)
#define | IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
#define | IS_NVIC_VECTTAB(VECTTAB)
#define | IS_SYSTICK_CLK_SOURCE(SOURCE)
#define | NVIC_LP_SEVONPEND ((uint8_t)0x10)
#define | NVIC_LP_SLEEPDEEP ((uint8_t)0x04)
#define | NVIC_LP_SLEEPONEXIT ((uint8_t)0x02)
#define | NVIC_PriorityGroup_0 ((uint32_t)0x700)
#define | NVIC_PriorityGroup_1 ((uint32_t)0x600)
#define | NVIC_PriorityGroup_2 ((uint32_t)0x500)
#define | NVIC_PriorityGroup_3 ((uint32_t)0x400)
#define | NVIC_PriorityGroup_4 ((uint32_t)0x300)
#define | NVIC_VectTab_FLASH ((uint32_t)0x08000000)
#define | NVIC_VectTab_RAM ((uint32_t)0x20000000)
#define | SysTick_CLKSource_HCLK ((uint32_t)0x00000004)
#define | SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)

Functions

void | NVIC_Init (NVIC_InitTypeDef *NVIC_InitStruct)
Initializes the NVIC peripheral according to the specified parameters in the NVIC_InitStruct.
void | NVIC_PriorityGroupConfig (uint32_t NVIC_PriorityGroup)
Configures the priority grouping: pre-emption priority and subpriority.
void | NVIC_SetVectorTable (uint32_t NVIC_VectTab, uint32_t Offset)
Sets the vector table location and Offset.
void | NVIC_SystemLPConfig (uint8_t LowPowerMode, FunctionalState NewState)
Selects the condition for the system to enter low power mode.
void | SysTick_CLKSourceConfig (uint32_t SysTick_CLKSource)
Configures the SysTick clock source.

Detailed Description

This file contains all the functions prototypes for the miscellaneous firmware library functions (add-on to CMSIS functions).

Author:
MCD Application Team
Version:
V3.5.0
Date:
11-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file misc.h.


STM32F10x Standard Peripherals Firmware Library: platform_config.h File Reference

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • CAN
  • Networking
Defines

CAN/Networking/platform_config.h File Reference

Evaluation board specific configuration file. More...

#include "stm32_eval.h"

Go to the source code of this file.

Defines

#define | GPIO_CAN1 GPIOD
#define | GPIO_CAN2 GPIOB
#define | GPIO_Pin_CAN1_RX GPIO_Pin_0
#define | GPIO_Pin_CAN1_TX GPIO_Pin_1
#define | GPIO_Pin_CAN2_RX GPIO_Pin_5
#define | GPIO_Pin_CAN2_TX GPIO_Pin_6
#define | GPIO_Remapping_CAN1 GPIO_Remap2_CAN1
#define | GPIO_Remapping_CAN2 GPIO_Remap_CAN2
#define | RCC_APB2Periph_GPIO_CAN1 RCC_APB2Periph_GPIOD
#define | RCC_APB2Periph_GPIO_CAN2 RCC_APB2Periph_GPIOB
#define | USE_STM3210C_EVAL

Detailed Description

Evaluation board specific configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file CAN/Networking/platform_config.h.

Define Documentation

#define GPIO_CAN1 GPIOD

Definition at line 57 of file CAN/Networking/platform_config.h.

#define GPIO_CAN2 GPIOB

Definition at line 63 of file CAN/Networking/platform_config.h.

#define GPIO_Pin_CAN1_RX GPIO_Pin_0

Definition at line 58 of file CAN/Networking/platform_config.h.

#define GPIO_Pin_CAN1_TX GPIO_Pin_1

Definition at line 59 of file CAN/Networking/platform_config.h.

#define GPIO_Pin_CAN2_RX GPIO_Pin_5

Definition at line 64 of file CAN/Networking/platform_config.h.

#define GPIO_Pin_CAN2_TX GPIO_Pin_6

Definition at line 65 of file CAN/Networking/platform_config.h.

#define GPIO_Remapping_CAN1 GPIO_Remap2_CAN1

Definition at line 56 of file CAN/Networking/platform_config.h.

#define GPIO_Remapping_CAN2 GPIO_Remap_CAN2

Definition at line 62 of file CAN/Networking/platform_config.h.

#define RCC_APB2Periph_GPIO_CAN1 RCC_APB2Periph_GPIOD

Definition at line 55 of file CAN/Networking/platform_config.h.

#define RCC_APB2Periph_GPIO_CAN2 RCC_APB2Periph_GPIOB

Definition at line 61 of file CAN/Networking/platform_config.h.

#define USE_STM3210C_EVAL

Definition at line 36 of file CAN/Networking/platform_config.h.


STM32F10x Standard Peripherals Firmware Library: platform_config.h File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • DMA
  • SPI_RAM
Defines

DMA/SPI_RAM/platform_config.h File Reference

Evaluation board specific configuration file. More...

Go to the source code of this file.

Defines

#define USE_STM3210C_EVAL

Detailed Description

Evaluation board specific configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file DMA/SPI_RAM/platform_config.h.

Define Documentation

#define USE_STM3210C_EVAL

Definition at line 37 of file DMA/SPI_RAM/platform_config.h.


STM32F10x Standard Peripherals Firmware Library: platform_config.h File Reference

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • SPI
  • DMA
Defines

SPI/DMA/platform_config.h File Reference

Evaluation board specific configuration file. More...

Go to the source code of this file.

Defines

#define USE_STM3210C_EVAL

Detailed Description

Evaluation board specific configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file SPI/DMA/platform_config.h.

Define Documentation

#define USE_STM3210C_EVAL

Definition at line 36 of file SPI/DMA/platform_config.h.


STM32F10x Standard Peripherals Firmware Library: platform_config.h File Reference

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • SPI
  • FullDuplex_SoftNSS
Defines

SPI/FullDuplex_SoftNSS/platform_config.h File Reference

Evaluation board specific configuration file. More...

Go to the source code of this file.

Defines

#define USE_STM3210C_EVAL

Detailed Description

Evaluation board specific configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file SPI/FullDuplex_SoftNSS/platform_config.h.

Define Documentation

#define USE_STM3210C_EVAL

Definition at line 37 of file SPI/FullDuplex_SoftNSS/platform_config.h.


STM32F10x Standard Peripherals Firmware Library: platform_config.h File Reference

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • SPI
  • Simplex_Interrupt
Defines

SPI/Simplex_Interrupt/platform_config.h File Reference

Evaluation board specific configuration file. More...

Go to the source code of this file.

Defines

#define USE_STM3210C_EVAL

Detailed Description

Evaluation board specific configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file SPI/Simplex_Interrupt/platform_config.h.

Define Documentation

#define USE_STM3210C_EVAL

Definition at line 37 of file SPI/Simplex_Interrupt/platform_config.h.


STM32F10x Standard Peripherals Firmware Library: platform_config.h File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • USART
  • DMA_Interrupt
Defines

USART/DMA_Interrupt/platform_config.h File Reference

Evaluation board specific configuration file. More...

Go to the source code of this file.

Defines

#define USE_STM3210C_EVAL

Detailed Description

Evaluation board specific configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file USART/DMA_Interrupt/platform_config.h.

Define Documentation

#define USE_STM3210C_EVAL

Definition at line 37 of file USART/DMA_Interrupt/platform_config.h.


STM32F10x Standard Peripherals Firmware Library: platform_config.h File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • USART
  • DMA_Polling
Defines

USART/DMA_Polling/platform_config.h File Reference

Evaluation board specific configuration file. More...

Go to the source code of this file.

Defines

#define USE_STM3210C_EVAL

Detailed Description

Evaluation board specific configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file USART/DMA_Polling/platform_config.h.

Define Documentation

#define USE_STM3210C_EVAL

Definition at line 37 of file USART/DMA_Polling/platform_config.h.


STM32F10x Standard Peripherals Firmware Library: platform_config.h File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • USART
  • HalfDuplex
Defines

USART/HalfDuplex/platform_config.h File Reference

Evaluation board specific configuration file. More...

Go to the source code of this file.

Defines

#define USE_STM3210C_EVAL

Detailed Description

Evaluation board specific configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file USART/HalfDuplex/platform_config.h.

Define Documentation

#define USE_STM3210C_EVAL

Definition at line 37 of file USART/HalfDuplex/platform_config.h.


STM32F10x Standard Peripherals Firmware Library: platform_config.h File Reference

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Defines

USART/HyperTerminal_HwFlowControl/platform_config.h File Reference

Evaluation board specific configuration file. More...

Go to the source code of this file.

Defines

#define | GPIO_CTSPin GPIO_Pin_0
#define | GPIO_RTSPin GPIO_Pin_1
#define | GPIO_RxPin GPIO_Pin_3
#define | GPIO_TxPin GPIO_Pin_2
#define | GPIOx GPIOA
#define | RCC_APB2Periph_GPIOx RCC_APB2Periph_GPIOA
#define | USE_STM3210E_EVAL

Detailed Description

Evaluation board specific configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file USART/HyperTerminal_HwFlowControl/platform_config.h.

Define Documentation

#define GPIO_CTSPin GPIO_Pin_0

Definition at line 51 of file USART/HyperTerminal_HwFlowControl/platform_config.h.

#define GPIO_RTSPin GPIO_Pin_1

Definition at line 50 of file USART/HyperTerminal_HwFlowControl/platform_config.h.

#define GPIO_RxPin GPIO_Pin_3

Definition at line 53 of file USART/HyperTerminal_HwFlowControl/platform_config.h.

#define GPIO_TxPin GPIO_Pin_2

Definition at line 52 of file USART/HyperTerminal_HwFlowControl/platform_config.h.

#define GPIOx GPIOA

Definition at line 48 of file USART/HyperTerminal_HwFlowControl/platform_config.h.

#define RCC_APB2Periph_GPIOx RCC_APB2Periph_GPIOA

Definition at line 49 of file USART/HyperTerminal_HwFlowControl/platform_config.h.

#define USE_STM3210E_EVAL

Definition at line 36 of file USART/HyperTerminal_HwFlowControl/platform_config.h.


STM32F10x Standard Peripherals Firmware Library: platform_config.h File Reference

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Defines

USART/Interrupt/platform_config.h File Reference

Evaluation board specific configuration file. More...

Go to the source code of this file.

Defines

#define | USARTy USART1
#define | USARTy_CLK RCC_APB2Periph_USART1
#define | USARTy_GPIO GPIOA
#define | USARTy_GPIO_CLK RCC_APB2Periph_GPIOA
#define | USARTy_IRQHandler USART1_IRQHandler
#define | USARTy_IRQn USART1_IRQn
#define | USARTy_RxPin GPIO_Pin_10
#define | USARTy_TxPin GPIO_Pin_9
#define | USARTz USART2
#define | USARTz_CLK RCC_APB1Periph_USART2
#define | USARTz_GPIO GPIOA
#define | USARTz_GPIO_CLK RCC_APB2Periph_GPIOA
#define | USARTz_IRQHandler USART2_IRQHandler
#define | USARTz_IRQn USART2_IRQn
#define | USARTz_RxPin GPIO_Pin_3
#define | USARTz_TxPin GPIO_Pin_2
#define | USE_STM32100E_EVAL

Detailed Description

Evaluation board specific configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file USART/Interrupt/platform_config.h.

Define Documentation

#define USARTy USART1

Definition at line 63 of file USART/Interrupt/platform_config.h.

Referenced by EXTI0_IRQHandler(), main(), and USARTy_IRQHandler().

#define USARTy_CLK RCC_APB2Periph_USART1

Definition at line 65 of file USART/Interrupt/platform_config.h.

#define USARTy_GPIO GPIOA

Definition at line 64 of file USART/Interrupt/platform_config.h.

#define USARTy_GPIO_CLK RCC_APB2Periph_GPIOA

Definition at line 66 of file USART/Interrupt/platform_config.h.

#define USARTy_IRQHandler USART1_IRQHandler

Definition at line 70 of file USART/Interrupt/platform_config.h.

#define USARTy_IRQn USART1_IRQn

Definition at line 69 of file USART/Interrupt/platform_config.h.

#define USARTy_RxPin GPIO_Pin_10

Definition at line 67 of file USART/Interrupt/platform_config.h.

#define USARTy_TxPin GPIO_Pin_9

Definition at line 68 of file USART/Interrupt/platform_config.h.

#define USARTz USART2

Definition at line 72 of file USART/Interrupt/platform_config.h.

Referenced by EXTI9_5_IRQHandler(), main(), and USARTz_IRQHandler().

#define USARTz_CLK RCC_APB1Periph_USART2

Definition at line 74 of file USART/Interrupt/platform_config.h.

#define USARTz_GPIO GPIOA

Definition at line 73 of file USART/Interrupt/platform_config.h.

#define USARTz_GPIO_CLK RCC_APB2Periph_GPIOA

Definition at line 75 of file USART/Interrupt/platform_config.h.

#define USARTz_IRQHandler USART2_IRQHandler

Definition at line 79 of file USART/Interrupt/platform_config.h.

#define USARTz_IRQn USART2_IRQn

Definition at line 78 of file USART/Interrupt/platform_config.h.

#define USARTz_RxPin GPIO_Pin_3

Definition at line 76 of file USART/Interrupt/platform_config.h.

#define USARTz_TxPin GPIO_Pin_2

Definition at line 77 of file USART/Interrupt/platform_config.h.

#define USE_STM32100E_EVAL

Definition at line 37 of file USART/Interrupt/platform_config.h.


STM32F10x Standard Peripherals Firmware Library: platform_config.h File Reference

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  • Receive
Defines

USART/IrDA/Receive/platform_config.h File Reference

Evaluation board specific configuration file. More...

#include "stm32_eval.h"

Go to the source code of this file.

Defines

#define USE_STM3210C_EVAL

Detailed Description

Evaluation board specific configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file USART/IrDA/Receive/platform_config.h.

Define Documentation

#define USE_STM3210C_EVAL

Definition at line 38 of file USART/IrDA/Receive/platform_config.h.


STM32F10x Standard Peripherals Firmware Library: platform_config.h File Reference

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  • STM32F10x_StdPeriph_Examples
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  • Transmit
Defines

USART/IrDA/Transmit/platform_config.h File Reference

Evaluation board specific configuration file. More...

#include "stm32_eval.h"

Go to the source code of this file.

Defines

#define USE_STM32100E_EVAL

Detailed Description

Evaluation board specific configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file USART/IrDA/Transmit/platform_config.h.

Define Documentation

#define USE_STM32100E_EVAL

Definition at line 41 of file USART/IrDA/Transmit/platform_config.h.


STM32F10x Standard Peripherals Firmware Library: platform_config.h File Reference

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  • MultiProcessor
Defines

USART/MultiProcessor/platform_config.h File Reference

Evaluation board specific configuration file. More...

#include "stm32_eval.h"

Go to the source code of this file.

Defines

#define USE_STM3210C_EVAL

Detailed Description

Evaluation board specific configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file USART/MultiProcessor/platform_config.h.

Define Documentation

#define USE_STM3210C_EVAL

Definition at line 38 of file USART/MultiProcessor/platform_config.h.


STM32F10x Standard Peripherals Firmware Library: platform_config.h File Reference

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  • STM32F10x_StdPeriph_Lib_V3.5.0
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  • STM32F10x_StdPeriph_Examples
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  • Polling
Defines

USART/Polling/platform_config.h File Reference

Evaluation board specific configuration file. More...

Go to the source code of this file.

Defines

#define USE_STM3210C_EVAL

Detailed Description

Evaluation board specific configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file USART/Polling/platform_config.h.

Define Documentation

#define USE_STM3210C_EVAL

Definition at line 36 of file USART/Polling/platform_config.h.


STM32F10x Standard Peripherals Firmware Library: platform_config.h File Reference

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Defines

USART/Smartcard/platform_config.h File Reference

Evaluation board specific configuration file. More...

Go to the source code of this file.

Defines

#define USE_STM3210C_EVAL

Detailed Description

Evaluation board specific configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file USART/Smartcard/platform_config.h.

Define Documentation

#define USE_STM3210C_EVAL

Definition at line 35 of file USART/Smartcard/platform_config.h.


STM32F10x Standard Peripherals Firmware Library: platform_config.h File Reference

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  • Project
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  • Synchronous
Defines

USART/Synchronous/platform_config.h File Reference

Evaluation board specific configuration file. More...

Go to the source code of this file.

Defines

#define USE_STM3210E_EVAL

Detailed Description

Evaluation board specific configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file USART/Synchronous/platform_config.h.

Define Documentation

#define USE_STM3210E_EVAL

Definition at line 36 of file USART/Synchronous/platform_config.h.


STM32F10x Standard Peripherals Firmware Library: stm32100b_eval.c File Reference

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  • Utilities
  • STM32_EVAL
  • STM32100B_EVAL
Functions | Variables

stm32100b_eval.c File Reference

This file provides

  • set of firmware functions to manage Leds, push-button and COM ports
  • low level initialization functions for SD card (on SPI), SPI serial flash (sFLASH) and temperature sensor (LM75) available on STM32100B-EVAL evaluation board from STMicroelectronics.
More...

#include "stm32100b_eval.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_i2c.h"

Go to the source code of this file.

Functions

void | LM75_LowLevel_DeInit (void)
DeInitializes the LM75_I2C.
void | LM75_LowLevel_Init (void)
Initializes the LM75_I2C.
void | SD_LowLevel_DeInit (void)
DeInitializes the SD/SD communication.
void | SD_LowLevel_Init (void)
Initializes the SD_SPI and CS pins.
void | sFLASH_LowLevel_DeInit (void)
DeInitializes the peripherals used by the SPI FLASH driver.
void | sFLASH_LowLevel_Init (void)
Initializes the peripherals used by the SPI FLASH driver.
void | STM_EVAL_COMInit (COM_TypeDef COM, USART_InitTypeDef *USART_InitStruct)
Configures COM port.
void | STM_EVAL_LEDInit (Led_TypeDef Led)
Configures LED GPIO.
void | STM_EVAL_LEDOff (Led_TypeDef Led)
Turns selected LED Off.
void | STM_EVAL_LEDOn (Led_TypeDef Led)
Turns selected LED On.
void | STM_EVAL_LEDToggle (Led_TypeDef Led)
Toggles the selected LED.
uint32_t | STM_EVAL_PBGetState (Button_TypeDef Button)
Returns the selected Button state.
void | STM_EVAL_PBInit (Button_TypeDef Button, ButtonMode_TypeDef Button_Mode)
Configures Button GPIO and EXTI Line.

Variables

const uint32_t | BUTTON_CLK [BUTTONn]
const uint16_t | BUTTON_EXTI_LINE [BUTTONn]
const uint16_t | BUTTON_IRQn [BUTTONn]
const uint16_t | BUTTON_PIN [BUTTONn]
const uint16_t | BUTTON_PIN_SOURCE [BUTTONn]
GPIO_TypeDef * | BUTTON_PORT [BUTTONn]
const uint16_t | BUTTON_PORT_SOURCE [BUTTONn]
const uint16_t | COM_RX_PIN [COMn] = {EVAL_COM1_RX_PIN, EVAL_COM2_RX_PIN}
GPIO_TypeDef * | COM_RX_PORT [COMn] = {EVAL_COM1_RX_GPIO_PORT, EVAL_COM2_RX_GPIO_PORT}
const uint32_t | COM_RX_PORT_CLK [COMn] = {EVAL_COM1_RX_GPIO_CLK, EVAL_COM2_RX_GPIO_CLK}
const uint16_t | COM_TX_PIN [COMn] = {EVAL_COM1_TX_PIN, EVAL_COM2_TX_PIN}
GPIO_TypeDef * | COM_TX_PORT [COMn] = {EVAL_COM1_TX_GPIO_PORT, EVAL_COM2_TX_GPIO_PORT}
const uint32_t | COM_TX_PORT_CLK [COMn] = {EVAL_COM1_TX_GPIO_CLK, EVAL_COM2_TX_GPIO_CLK}
USART_TypeDef * | COM_USART [COMn] = {EVAL_COM1, EVAL_COM2}
const uint32_t | COM_USART_CLK [COMn] = {EVAL_COM1_CLK, EVAL_COM2_CLK}
const uint32_t | GPIO_CLK [LEDn]
const uint16_t | GPIO_PIN [LEDn]
GPIO_TypeDef * | GPIO_PORT [LEDn]

Detailed Description

This file provides

  • set of firmware functions to manage Leds, push-button and COM ports
  • low level initialization functions for SD card (on SPI), SPI serial flash (sFLASH) and temperature sensor (LM75) available on STM32100B-EVAL evaluation board from STMicroelectronics.
Author:
MCD Application Team
Version:
V4.5.0
Date:
07-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm32100b_eval.c.


STM32F10x Standard Peripherals Firmware Library: stm32100b_eval.h File Reference

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  • Utilities
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  • STM32100B_EVAL
Defines | Functions

stm32100b_eval.h File Reference

This file contains definitions for STM32100B_EVAL's Leds, push-buttons COM ports, SD Card on SPI, sFLASH on SPI and Temperature Sensor LM75 on I2C hardware resources. More...

#include "stm32_eval.h"

Go to the source code of this file.

Defines

#define | BUTTONn 8
#define | COMn 2
#define | DOWN_BUTTON_EXTI_IRQn EXTI15_10_IRQn
#define | DOWN_BUTTON_EXTI_LINE EXTI_Line14
#define | DOWN_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource14
#define | DOWN_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOD
#define | DOWN_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOD
#define | DOWN_BUTTON_GPIO_PORT GPIOD
#define | DOWN_BUTTON_PIN GPIO_Pin_14
Joystick Down push-button.
#define | EVAL_COM1 USART1
Definition for COM port1, connected to USART1.
#define | EVAL_COM1_CLK RCC_APB2Periph_USART1
#define | EVAL_COM1_IRQn USART1_IRQn
#define | EVAL_COM1_RX_GPIO_CLK RCC_APB2Periph_GPIOA
#define | EVAL_COM1_RX_GPIO_PORT GPIOA
#define | EVAL_COM1_RX_PIN GPIO_Pin_10
#define | EVAL_COM1_TX_GPIO_CLK RCC_APB2Periph_GPIOA
#define | EVAL_COM1_TX_GPIO_PORT GPIOA
#define | EVAL_COM1_TX_PIN GPIO_Pin_9
#define | EVAL_COM2 USART2
Definition for COM port2, connected to USART2 (USART2 pins remapped on GPIOD)
#define | EVAL_COM2_CLK RCC_APB1Periph_USART2
#define | EVAL_COM2_IRQn USART2_IRQn
#define | EVAL_COM2_RX_GPIO_CLK RCC_APB2Periph_GPIOD
#define | EVAL_COM2_RX_GPIO_PORT GPIOD
#define | EVAL_COM2_RX_PIN GPIO_Pin_6
#define | EVAL_COM2_TX_GPIO_CLK RCC_APB2Periph_GPIOD
#define | EVAL_COM2_TX_GPIO_PORT GPIOD
#define | EVAL_COM2_TX_PIN GPIO_Pin_5
#define | KEY_BUTTON_EXTI_IRQn EXTI9_5_IRQn
#define | KEY_BUTTON_EXTI_LINE EXTI_Line9
#define | KEY_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource9
#define | KEY_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOB
#define | KEY_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOB
#define | KEY_BUTTON_GPIO_PORT GPIOB
#define | KEY_BUTTON_PIN GPIO_Pin_9
Key push-button.
#define | LED1_GPIO_CLK RCC_APB2Periph_GPIOC
#define | LED1_GPIO_PORT GPIOC
#define | LED1_PIN GPIO_Pin_6
#define | LED2_GPIO_CLK RCC_APB2Periph_GPIOC
#define | LED2_GPIO_PORT GPIOC
#define | LED2_PIN GPIO_Pin_7
#define | LED3_GPIO_CLK RCC_APB2Periph_GPIOC
#define | LED3_GPIO_PORT GPIOC
#define | LED3_PIN GPIO_Pin_8
#define | LED4_GPIO_CLK RCC_APB2Periph_GPIOC
#define | LED4_GPIO_PORT GPIOC
#define | LED4_PIN GPIO_Pin_9
#define | LEDn 4
#define | LEFT_BUTTON_EXTI_IRQn EXTI0_IRQn
#define | LEFT_BUTTON_EXTI_LINE EXTI_Line0
#define | LEFT_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource0
#define | LEFT_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOE
#define | LEFT_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOE
#define | LEFT_BUTTON_GPIO_PORT GPIOE
#define | LEFT_BUTTON_PIN GPIO_Pin_0
Joystick Left push-button.
#define | LM75_DMA_CLK RCC_AHBPeriph_DMA1
#define | LM75_DMA_RX_CHANNEL DMA1_Channel7
#define | LM75_DMA_RX_TCFLAG DMA1_FLAG_TC7
#define | LM75_DMA_TX_CHANNEL DMA1_Channel6
#define | LM75_DMA_TX_TCFLAG DMA1_FLAG_TC6
#define | LM75_I2C I2C1
LM75 Temperature Sensor I2C Interface pins.
#define | LM75_I2C_CLK RCC_APB1Periph_I2C1
#define | LM75_I2C_DR ((uint32_t)0x40005410)
#define | LM75_I2C_SCL_GPIO_CLK RCC_APB2Periph_GPIOB
#define | LM75_I2C_SCL_GPIO_PORT GPIOB
#define | LM75_I2C_SCL_PIN GPIO_Pin_6
#define | LM75_I2C_SDA_GPIO_CLK RCC_APB2Periph_GPIOB
#define | LM75_I2C_SDA_GPIO_PORT GPIOB
#define | LM75_I2C_SDA_PIN GPIO_Pin_7
#define | LM75_I2C_SMBUSALERT_GPIO_CLK RCC_APB2Periph_GPIOB
#define | LM75_I2C_SMBUSALERT_GPIO_PORT GPIOB
#define | LM75_I2C_SMBUSALERT_PIN GPIO_Pin_5
#define | RIGHT_BUTTON_EXTI_IRQn EXTI1_IRQn
#define | RIGHT_BUTTON_EXTI_LINE EXTI_Line1
#define | RIGHT_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource1
#define | RIGHT_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOE
#define | RIGHT_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOE
#define | RIGHT_BUTTON_GPIO_PORT GPIOE
#define | RIGHT_BUTTON_PIN GPIO_Pin_1
Joystick Right push-button.
#define | SD_CS_GPIO_CLK RCC_APB2Periph_GPIOC
#define | SD_CS_GPIO_PORT GPIOC
#define | SD_CS_PIN GPIO_Pin_12
#define | SD_DETECT_GPIO_CLK RCC_APB2Periph_GPIOE
#define | SD_DETECT_GPIO_PORT GPIOE
#define | SD_DETECT_PIN GPIO_Pin_7
#define | SD_SPI SPI1
SD SPI Interface pins.
#define | SD_SPI_CLK RCC_APB2Periph_SPI1
#define | SD_SPI_MISO_GPIO_CLK RCC_APB2Periph_GPIOA
#define | SD_SPI_MISO_GPIO_PORT GPIOA
#define | SD_SPI_MISO_PIN GPIO_Pin_6
#define | SD_SPI_MOSI_GPIO_CLK RCC_APB2Periph_GPIOA
#define | SD_SPI_MOSI_GPIO_PORT GPIOA
#define | SD_SPI_MOSI_PIN GPIO_Pin_7
#define | SD_SPI_SCK_GPIO_CLK RCC_APB2Periph_GPIOA
#define | SD_SPI_SCK_GPIO_PORT GPIOA
#define | SD_SPI_SCK_PIN GPIO_Pin_5
#define | SEL_BUTTON_EXTI_IRQn EXTI15_10_IRQn
#define | SEL_BUTTON_EXTI_LINE EXTI_Line12
#define | SEL_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource12
#define | SEL_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOD
#define | SEL_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOD
#define | SEL_BUTTON_GPIO_PORT GPIOD
#define | SEL_BUTTON_PIN GPIO_Pin_12
Joystick Sel push-button.
#define | sFLASH_CS_GPIO_CLK RCC_APB2Periph_GPIOD
#define | sFLASH_CS_GPIO_PORT GPIOD
#define | sFLASH_CS_PIN GPIO_Pin_9
#define | sFLASH_SPI SPI1
M25P FLASH SPI Interface pins.
#define | sFLASH_SPI_CLK RCC_APB2Periph_SPI1
#define | sFLASH_SPI_MISO_GPIO_CLK RCC_APB2Periph_GPIOA
#define | sFLASH_SPI_MISO_GPIO_PORT GPIOA
#define | sFLASH_SPI_MISO_PIN GPIO_Pin_6
#define | sFLASH_SPI_MOSI_GPIO_CLK RCC_APB2Periph_GPIOA
#define | sFLASH_SPI_MOSI_GPIO_PORT GPIOA
#define | sFLASH_SPI_MOSI_PIN GPIO_Pin_7
#define | sFLASH_SPI_SCK_GPIO_CLK RCC_APB2Periph_GPIOA
#define | sFLASH_SPI_SCK_GPIO_PORT GPIOA
#define | sFLASH_SPI_SCK_PIN GPIO_Pin_5
#define | TAMPER_BUTTON_EXTI_IRQn EXTI15_10_IRQn
#define | TAMPER_BUTTON_EXTI_LINE EXTI_Line13
#define | TAMPER_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource13
#define | TAMPER_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOC
#define | TAMPER_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOC
#define | TAMPER_BUTTON_GPIO_PORT GPIOC
#define | TAMPER_BUTTON_PIN GPIO_Pin_13
Tamper push-button.
#define | UP_BUTTON_EXTI_IRQn EXTI9_5_IRQn
#define | UP_BUTTON_EXTI_LINE EXTI_Line8
#define | UP_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource8
#define | UP_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOD
#define | UP_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOD
#define | UP_BUTTON_GPIO_PORT GPIOD
#define | UP_BUTTON_PIN GPIO_Pin_8
Joystick Up push-button.
#define | WAKEUP_BUTTON_EXTI_IRQn EXTI0_IRQn
#define | WAKEUP_BUTTON_EXTI_LINE EXTI_Line0
#define | WAKEUP_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource0
#define | WAKEUP_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOA
#define | WAKEUP_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOA
#define | WAKEUP_BUTTON_GPIO_PORT GPIOA
#define | WAKEUP_BUTTON_PIN GPIO_Pin_0
Wakeup push-button.

Functions

void | LM75_LowLevel_DeInit (void)
DeInitializes the LM75_I2C.
void | LM75_LowLevel_Init (void)
Initializes the LM75_I2C.
void | SD_LowLevel_DeInit (void)
DeInitializes the SD/SD communication.
void | SD_LowLevel_Init (void)
Initializes the SD_SPI and CS pins.
void | sFLASH_LowLevel_DeInit (void)
DeInitializes the peripherals used by the SPI FLASH driver.
void | sFLASH_LowLevel_Init (void)
Initializes the peripherals used by the SPI FLASH driver.
void | STM_EVAL_COMInit (COM_TypeDef COM, USART_InitTypeDef *USART_InitStruct)
Configures COM port.
void | STM_EVAL_LEDInit (Led_TypeDef Led)
Configures LED GPIO.
void | STM_EVAL_LEDOff (Led_TypeDef Led)
Turns selected LED Off.
void | STM_EVAL_LEDOn (Led_TypeDef Led)
Turns selected LED On.
void | STM_EVAL_LEDToggle (Led_TypeDef Led)
Toggles the selected LED.
uint32_t | STM_EVAL_PBGetState (Button_TypeDef Button)
Returns the selected Button state.
void | STM_EVAL_PBInit (Button_TypeDef Button, ButtonMode_TypeDef Button_Mode)
Configures Button GPIO and EXTI Line.

Detailed Description

This file contains definitions for STM32100B_EVAL's Leds, push-buttons COM ports, SD Card on SPI, sFLASH on SPI and Temperature Sensor LM75 on I2C hardware resources.

Author:
MCD Application Team
Version:
V4.5.0
Date:
07-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm32100b_eval.h.


STM32F10x Standard Peripherals Firmware Library: stm32100b_eval_cec.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • STM32100B_EVAL
Functions | Variables

stm32100b_eval_cec.c File Reference

This file provides all the STM32100B-EVAL HDMI-CEC firmware functions. More...

#include "stm32100b_eval_cec.h"

Go to the source code of this file.

Functions

HDMI_CEC_Error | HDMI_CEC_CheckConnectedDevices (void)
Check the connected CEC devices.
void | HDMI_CEC_CommandCallBack (void)
Handle CEC command receive callback.
HDMI_CEC_Error | HDMI_CEC_GetErrorStatus (void)
Get the ESR register status.
HDMI_CEC_Error | HDMI_CEC_Init (void)
Initializes the HDMI CEC.
void | HDMI_CEC_ProcessIRQSrc (void)
Allows to process all the interrupts that are high.
HDMI_CEC_Error | HDMI_CEC_ReportPhysicalAddress (void)
Report physical address to all other devices thus allowing any device to create a map of the network.
HDMI_CEC_Error HDMI_CEC_TransmitMessage (HDMI_CEC_Message *HDMI_CEC_TX_MessageStructure)
Transmit message by taking data from typedef struct CEC_Meassage.
static HDMI_CEC_Error | LogicalAddressAllocation (void)
Allocate the logical address.
static HDMI_CEC_Error | PhysicalAddressDiscovery (void)
Physical address discovery.

Variables

__IO uint8_t | AbortReason = 0
__IO uint32_t | BufferCount = 0
__IO uint8_t | BufferPointer [15]
__IO uint8_t | CECDevicesNumber = 0
__IO uint8_t | DeviceCount = 0
__IO uint8_t | DeviceType = 0
__IO uint8_t | FeatureOpcode = 0
HDMI_CEC_Map | HDMI_CEC_DeviceMap [14]
uint8_t * | HDMI_CEC_Follower_String [13][2]
HDMI_CEC_Map HDMI_CEC_MapStruct
HDMI_CEC_Message HDMI_CEC_RX_MessageStructPrivate
HDMI_CEC_Message HDMI_CEC_TX_MessageStructPrivate
HDMI_CEC_Message HDMI_CEC_TX_MessageStructure
__IO uint8_t | MyLogicalAddress = 0
__IO uint16_t | MyPhysicalAddress = 0
__IO uint32_t | ReceivedFrame = 0
__IO uint32_t | ReceiveStatus = 0
__IO uint8_t | RecepErrorCode = 0
__IO uint32_t | RxCounter = 0
__IO uint32_t | SendFrame = 0
__IO uint32_t | SendStatus = 0
__IO uint8_t | TransErrorCode = 0
__IO uint32_t | TxCounter = 0

Detailed Description

This file provides all the STM32100B-EVAL HDMI-CEC firmware functions.

Author:
MCD Application Team
Version:
V4.5.0
Date:
07-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm32100b_eval_cec.c.


STM32F10x Standard Peripherals Firmware Library: stm32100b_eval_cec.h File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • STM32100B_EVAL
Data Structures | Defines | Enumerations | Functions

stm32100b_eval_cec.h File Reference

This file contains all the functions prototypes for the stm32100b_eval_cec firmware driver. More...

#include "stm32f10x.h"

Go to the source code of this file.

Data Structures

struct | HDMI_CEC_Map
struct | HDMI_CEC_Message
CEC Init Structure definition. More...

Defines

#define | HDMI_CEC_AUDIOSYSTEM 0x05
#define | HDMI_CEC_CANNOTPROVIDE_SOURCE 0x02
#define | HDMI_CEC_HPD_GPIO_CLK RCC_APB2Periph_GPIOB
#define | HDMI_CEC_HPD_GPIO_PORT GPIOB
#define | HDMI_CEC_HPD_HIGH() GPIO_SetBits(HDMI_CEC_HPD_GPIO_PORT, HDMI_CEC_HPD_PIN)
#define | HDMI_CEC_HPD_LOW() GPIO_ResetBits(HDMI_CEC_HPD_GPIO_PORT, HDMI_CEC_HPD_PIN)
#define | HDMI_CEC_HPD_PIN GPIO_Pin_12
HDMI CEC HPD (Hot Plug Detect) Interface pin.
#define | HDMI_CEC_I2C I2C2
#define | HDMI_CEC_I2C_CLK RCC_APB1Periph_I2C2
#define | HDMI_CEC_I2C_CLOCK_SPEED 100000
#define | HDMI_CEC_I2C_GPIO_CLK RCC_APB2Periph_GPIOB
#define | HDMI_CEC_I2C_GPIO_PORT GPIOB
#define | HDMI_CEC_I2C_SCL_PIN GPIO_Pin_10
HDMI CEC I2C Interface pins.
#define | HDMI_CEC_I2C_SDA_PIN GPIO_Pin_11
#define | HDMI_CEC_I2C_SLAVE_ADDRESS7 0xA0
#define | HDMI_CEC_INVALID_OPERAND 0x03
#define | HDMI_CEC_LINE_GPIO_CLK RCC_APB2Periph_GPIOB
#define | HDMI_CEC_LINE_GPIO_PORT GPIOB
#define | HDMI_CEC_LINE_PIN GPIO_Pin_8
HDMI CEC Interface pin.
#define | HDMI_CEC_NOT_CORRECT_MODETORESPOND 0x01
#define | HDMI_CEC_OPCODE_ABORT ((uint8_t) 0xFF)
#define | HDMI_CEC_OPCODE_ACTIVE_SOURCE ((uint8_t) 0x82)
HDMI CEC specific commands.
#define | HDMI_CEC_OPCODE_CEC_VERSION ((uint8_t) 0x9E)
#define | HDMI_CEC_OPCODE_CLEAR_ANALOGUE_TIMER ((uint8_t) 0x33)
#define | HDMI_CEC_OPCODE_CLEAR_DIGITAL_TIMER ((uint8_t) 0x99)
#define | HDMI_CEC_OPCODE_CLEAR_EXTERNAL_TIMER ((uint8_t) 0xA1)
#define | HDMI_CEC_OPCODE_DECK_CONTROL ((uint8_t) 0x42)
#define | HDMI_CEC_OPCODE_DECK_STATUS ((uint8_t) 0x1B)
#define | HDMI_CEC_OPCODE_DEVICE_VENDOR_ID ((uint8_t) 0x87)
#define | HDMI_CEC_OPCODE_FEATURE_ABORT ((uint8_t) 0x00)
#define | HDMI_CEC_OPCODE_GET_CEC_VERSION ((uint8_t) 0x9F)
#define | HDMI_CEC_OPCODE_GET_MENU_LANGUAGE ((uint8_t) 0x91)
#define | HDMI_CEC_OPCODE_GIVE_AUDIO_STATUS ((uint8_t) 0x71)
#define | HDMI_CEC_OPCODE_GIVE_DECK_STATUS ((uint8_t) 0x1A)
#define | HDMI_CEC_OPCODE_GIVE_DEVICE_POWER_STATUS ((uint8_t) 0x8F)
#define | HDMI_CEC_OPCODE_GIVE_DEVICE_VENDOR_ID ((uint8_t) 0x8C)
#define | HDMI_CEC_OPCODE_GIVE_OSD_NAME ((uint8_t) 0x46)
#define | HDMI_CEC_OPCODE_GIVE_PHYSICAL_ADDRESS ((uint8_t) 0x83)
#define | HDMI_CEC_OPCODE_GIVE_SYSTEM_AUDIO_MODE_STATUS ((uint8_t) 0x7D)
#define | HDMI_CEC_OPCODE_GIVE_TUNER_DEVICE_STATUS ((uint8_t) 0x08)
#define | HDMI_CEC_OPCODE_IMAGE_VIEW_ON ((uint8_t) 0x04)
#define | HDMI_CEC_OPCODE_INACTIVE_SOURCE ((uint8_t) 0x9D)
#define | HDMI_CEC_OPCODE_MENU_REQUEST ((uint8_t) 0x8D)
#define | HDMI_CEC_OPCODE_MENU_STATUS ((uint8_t) 0x8E)
#define | HDMI_CEC_OPCODE_PLAY ((uint8_t) 0x41)
#define | HDMI_CEC_OPCODE_RECORD_OFF ((uint8_t) 0x0B)
#define | HDMI_CEC_OPCODE_RECORD_ON ((uint8_t) 0x09)
#define | HDMI_CEC_OPCODE_RECORD_STATUS ((uint8_t) 0x0A)
#define | HDMI_CEC_OPCODE_RECORD_TV_SCREEN ((uint8_t) 0x0F)
#define | HDMI_CEC_OPCODE_REPORT_AUDIO_STATUS ((uint8_t) 0x7A)
#define | HDMI_CEC_OPCODE_REPORT_PHYSICAL_ADDRESS ((uint8_t) 0x84)
#define | HDMI_CEC_OPCODE_REPORT_POWER_STATUS ((uint8_t) 0x90)
#define | HDMI_CEC_OPCODE_REQUEST_ACTIVE_SOURCE ((uint8_t) 0x85)
#define | HDMI_CEC_OPCODE_ROUTING_CHANGE ((uint8_t) 0x80)
#define | HDMI_CEC_OPCODE_ROUTING_INFORMATION ((uint8_t) 0x81)
#define | HDMI_CEC_OPCODE_SELECT_ANALOGUE_SERVICE ((uint8_t) 0x92)
#define | HDMI_CEC_OPCODE_SELECT_DIGITAL_SERVICE ((uint8_t) 0x93)
#define | HDMI_CEC_OPCODE_SET_ANALOGUE_TIMER ((uint8_t) 0x34)
#define | HDMI_CEC_OPCODE_SET_AUDIO_RATE ((uint8_t) 0x9A)
#define | HDMI_CEC_OPCODE_SET_DIGITAL_TIMER ((uint8_t) 0x97)
#define | HDMI_CEC_OPCODE_SET_EXTERNAL_TIMER ((uint8_t) 0xA2)
#define | HDMI_CEC_OPCODE_SET_MENU_LANGUAGE ((uint8_t) 0x32)
#define | HDMI_CEC_OPCODE_SET_OSD_NAME ((uint8_t) 0x47)
#define | HDMI_CEC_OPCODE_SET_OSD_STRING ((uint8_t) 0x64)
#define | HDMI_CEC_OPCODE_SET_STREAM_PATH ((uint8_t) 0x86)
#define | HDMI_CEC_OPCODE_SET_SYSTEM_AUDIO_MODE ((uint8_t) 0x72)
#define | HDMI_CEC_OPCODE_SET_TIMER_PROGRAM_TITLE ((uint8_t) 0x67)
#define | HDMI_CEC_OPCODE_STANDBY ((uint8_t) 0x36)
#define | HDMI_CEC_OPCODE_SYSTEM_AUDIO_MODE_REQUEST ((uint8_t) 0x70)
#define | HDMI_CEC_OPCODE_SYSTEM_AUDIO_MODE_STATUS ((uint8_t) 0x7E)
#define | HDMI_CEC_OPCODE_TEXT_VIEW_ON ((uint8_t) 0x0D)
#define | HDMI_CEC_OPCODE_TIMER_CLEARED_STATUS ((uint8_t) 0x43)
#define | HDMI_CEC_OPCODE_TIMER_STATUS ((uint8_t) 0x35)
#define | HDMI_CEC_OPCODE_TUNER_DEVICE_STATUS ((uint8_t) 0x07)
#define | HDMI_CEC_OPCODE_TUNER_STEP_DECREMENT ((uint8_t) 0x06)
#define | HDMI_CEC_OPCODE_TUNER_STEP_INCREMENT ((uint8_t) 0x05)
#define | HDMI_CEC_OPCODE_USER_CONTROL_PRESSED ((uint8_t) 0x44)
#define | HDMI_CEC_OPCODE_USER_CONTROL_RELEASED ((uint8_t) 0x45)
#define | HDMI_CEC_OPCODE_VENDOR_COMMAND ((uint8_t) 0x89)
#define | HDMI_CEC_OPCODE_VENDOR_COMMAND_WITH_ID ((uint8_t) 0xA0)
#define | HDMI_CEC_OPCODE_VENDOR_REMOTE_BUTTON_DOWN ((uint8_t) 0x8A)
#define | HDMI_CEC_OPCODE_VENDOR_REMOTE_BUTTON_UP ((uint8_t) 0x8B)
#define | HDMI_CEC_PLAYBACK 0x04
#define | HDMI_CEC_RECORDING 0x01
#define | HDMI_CEC_REFUSED 0x04
#define | HDMI_CEC_ROOT 0x00
HDMI CEC Root (Mainly for TV with a fixed physical address (0.0.0.0)) If you want to configure the STM32100B-EVAL board as CEC Root (Sink) change the following define to 0x1.
#define | HDMI_CEC_TIMEOUT_VALUE ((uint32_t)0x001FFFFF)
#define | HDMI_CEC_TUNER 0x03
#define | HDMI_CEC_TV 0x00
CEC device types.
#define | HDMI_CEC_TX_MESSAGE_LENGTH_MAX ((uint32_t)0x0000000E)
#define | HDMI_CEC_UNRECOGNIZED_OPCODE 0x00
Reason for Abort feature.
#define | HDMI_CEC_VERSION 0x04
To select if the DDC Channel will be used for physical address discovery or not.

Enumerations

enum HDMI_CEC_Error {
HDMI_CEC_BIT_TIMING = (1), HDMI_CEC_BIT_PERIOD = (2), HDMI_CEC_RX_BLOCK_FINISHED = (3), HDMI_CEC_START_BIT = (4),
HDMI_CEC_BLOCK_ACKNOWLEDGE = (5), HDMI_CEC_LINE = (6), HDMI_CEC_TX_BLOCK_FINISHED = (7), HDMI_CEC_DEVICE_UNREGISTRED = (8),
HDMI_CEC_TIMEOUT = (9), HDMI_CEC_OK = (10), HDMI_CEC_BIT_TIMING = (1), HDMI_CEC_BIT_PERIOD = (2),
HDMI_CEC_RX_BLOCK_FINISHED = (3), HDMI_CEC_START_BIT = (4), HDMI_CEC_BLOCK_ACKNOWLEDGE = (5), HDMI_CEC_LINE = (6),
HDMI_CEC_TX_BLOCK_FINISHED = (7), HDMI_CEC_DEVICE_UNREGISTRED = (8), HDMI_CEC_TIMEOUT = (9), HDMI_CEC_OK = (10)
}

Functions

HDMI_CEC_Error | HDMI_CEC_CheckConnectedDevices (void)
Check the connected CEC devices.
void | HDMI_CEC_CommandCallBack (void)
Handle CEC command receive callback.
HDMI_CEC_Error | HDMI_CEC_GetErrorStatus (void)
Get the ESR register status.
HDMI_CEC_Error | HDMI_CEC_Init (void)
Initializes the HDMI CEC.
void | HDMI_CEC_ProcessIRQSrc (void)
Allows to process all the interrupts that are high.
HDMI_CEC_Error | HDMI_CEC_ReportPhysicalAddress (void)
Report physical address to all other devices thus allowing any device to create a map of the network.
HDMI_CEC_Error HDMI_CEC_TransmitMessage (HDMI_CEC_Message *HDMI_CEC_TX_MessageStructure)
Transmit message by taking data from typedef struct CEC_Meassage.

Detailed Description

This file contains all the functions prototypes for the stm32100b_eval_cec firmware driver.

Author:
MCD Application Team
Version:
V4.5.0
Date:
07-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm32100b_eval_cec.h.


STM32F10x Standard Peripherals Firmware Library: stm32100b_eval_lcd.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • STM32100B_EVAL
Defines | Functions | Variables

stm32100b_eval_lcd.c File Reference

This file includes the LCD driver for AM-240320LTNQW00H (LCD_HX8312), AM-240320L8TNQW00H (LCD_ILI9320), AM-240320LDTNQW00H (LCD_SPFD5408B) Liquid Crystal Display Module of STM32100B-EVAL board. More...

#include "stm32100b_eval_lcd.h"
#include "../Common/fonts.c"

Go to the source code of this file.

Defines

#define | ABS(X) ((X) > 0 ? (X) : -(X))
#define | LCD_HX8312 0x8312
#define | LCD_ILI9320 0x9320
#define | LCD_READ_REG 0x03
#define | LCD_SPFD5408 0x5408
#define | LCD_WRITE_REG 0x02
#define | MAX_POLY_CORNERS 200
#define | POLY_X(Z) ((int32_t)((Points + Z)->Y))
#define | POLY_Y(Z) ((int32_t)((Points + Z)->X))
#define | READ_STATUS 0x01
#define | SET_INDEX 0x00
#define | START_BYTE 0x70

Functions

static void | delay (vu32 nCount)
Inserts a delay time.
void | LCD_Clear (uint16_t Color)
Clears the hole LCD.
void | LCD_ClearLine (uint8_t Line)
Clears the selected line.
void | LCD_ClosedPolyLine (pPoint Points, uint16_t PointCount)
Displays a closed polyline (between many points).
void | LCD_ClosedPolyLineRelative (pPoint Points, uint16_t PointCount)
Displays a closed relative polyline (between many points).
void | LCD_CtrlLinesConfig (void)
Configures LCD control lines in Output Push-Pull mode.
void | LCD_CtrlLinesWrite (GPIO_TypeDef *GPIOx, uint16_t CtrlPins, BitAction BitVal)
Sets or reset LCD control lines.
void | LCD_DeInit (void)
DeInitializes the LCD.
void | LCD_DisplayChar (uint8_t Line, uint16_t Column, uint8_t Ascii)
Displays one character (16dots width, 24dots height).
void | LCD_DisplayOff (void)
Disables the Display.
void | LCD_DisplayOn (void)
Enables the Display.
void | LCD_DisplayStringLine (uint8_t Line, uint8_t *ptr)
Displays a maximum of 20 char on the LCD.
void | LCD_DrawChar (uint8_t Xpos, uint16_t Ypos, const uint16_t *c)
Draws a character on LCD.
void | LCD_DrawCircle (uint8_t Xpos, uint16_t Ypos, uint16_t Radius)
Displays a circle.
void | LCD_DrawFullCircle (uint16_t Xpos, uint16_t Ypos, uint16_t Radius)
Displays a full circle.
void | LCD_DrawFullRect (uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height)
Displays a full rectangle.
void | LCD_DrawLine (uint8_t Xpos, uint16_t Ypos, uint16_t Length, uint8_t Direction)
Displays a line.
void | LCD_DrawMonoPict (const uint32_t *Pict)
Displays a monocolor picture.
void | LCD_DrawRect (uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width)
Displays a rectangle.
void | LCD_DrawUniLine (uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2)
Displays an uni line (between two points).
void | LCD_FillPolyLine (pPoint Points, uint16_t PointCount)
Displays a full polyline (between many points).
void | LCD_GetColors (__IO uint16_t *_TextColor, __IO uint16_t *_BackColor)
Gets the LCD Text and Background colors.
sFONT * | LCD_GetFont (void)
Gets the Text Font.
void | LCD_nCS_StartByte (uint8_t Start_Byte)
Reset LCD control line(/CS) and Send Start-Byte.
void | LCD_PolyLine (pPoint Points, uint16_t PointCount)
Displays an polyline (between many points).
void | LCD_PolyLineRelative (pPoint Points, uint16_t PointCount)
Displays a relative polyline (between many points).
static void | LCD_PolyLineRelativeClosed (pPoint Points, uint16_t PointCount, uint16_t Closed)
Displays an relative polyline (between many points).
void | LCD_PowerOn (void)
Power on the LCD.
uint16_t | LCD_ReadReg (uint8_t LCD_Reg)
Reads the selected LCD Register.
void | LCD_SetBackColor (__IO uint16_t Color)
Sets the Background color.
void | LCD_SetColors (__IO uint16_t _TextColor, __IO uint16_t _BackColor)
Sets the LCD Text and Background colors.
void | LCD_SetCursor (uint8_t Xpos, uint16_t Ypos)
Sets the cursor position.
void | LCD_SetDisplayWindow (uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width)
Sets a display window.
void | LCD_SetFont (sFONT *fonts)
Sets the Text Font.
void | LCD_SetTextColor (__IO uint16_t Color)
Sets the Text color.
void | LCD_Setup (void)
Setups the LCD.
void | LCD_SPIConfig (void)
Configures the LCD_SPI interface.
void | LCD_WindowModeDisable (void)
Disables LCD Window mode.
void | LCD_WriteRAM (uint16_t RGB_Code)
Writes to the LCD RAM.
void | LCD_WriteRAM_Prepare (void)
Prepare to write to the LCD RAM.
void | LCD_WriteRAMWord (uint16_t RGB_Code)
Writes 1 word to the LCD RAM.
void | LCD_WriteReg (uint8_t LCD_Reg, uint16_t LCD_RegValue)
Writes to the selected LCD register.
static void | LCD_WriteRegHX8312 (uint8_t LCD_Reg, uint8_t LCD_RegValue)
Writes to the selected LCD HX8312 register.
static void | LCD_WriteRegILI9320 (uint8_t LCD_Reg, uint16_t LCD_RegValue)
Writes to the selected LCD ILI9320 register.
void | LCD_WriteRegIndex (uint8_t LCD_Reg)
Writes index to select the LCD register.
static void | PutPixel (int16_t x, int16_t y)
Displays a pixel.
void | STM32100B_LCD_Init (void)
Initializes the LCD.

Variables

static __IO uint16_t | BackColor = 0xFFFF
static sFONT * | LCD_Currentfonts
static __IO uint32_t | LCDType = LCD_ILI9320
static __IO uint16_t | TextColor = 0x0000

Detailed Description

This file includes the LCD driver for AM-240320LTNQW00H (LCD_HX8312), AM-240320L8TNQW00H (LCD_ILI9320), AM-240320LDTNQW00H (LCD_SPFD5408B) Liquid Crystal Display Module of STM32100B-EVAL board.

Author:
MCD Application Team
Version:
V4.5.0
Date:
07-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm32100b_eval_lcd.c.


STM32F10x Standard Peripherals Firmware Library: stm32100b_eval_lcd.h File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • STM32100B_EVAL
Data Structures | Defines | Typedefs | Functions

stm32100b_eval_lcd.h File Reference

This file contains all the functions prototypes for the stm32100b_eval_lcd firmware driver. More...

#include "stm32f10x.h"
#include "../Common/fonts.h"

Go to the source code of this file.

Data Structures

struct | Point

Defines

#define | _delay_ delay
Uncomment the line below if you want to use LCD_DrawBMP function to display a bitmap picture on the LCD.
#define | ASSEMBLE_RGB(R, G, B) ((((R)& 0xF8) << 8) | (((G) & 0xFC) << 3) | (((B) & 0xF8) >> 3))
#define | LCD_COLOR_BLACK 0x0000
#define | LCD_COLOR_BLUE 0x001F
#define | LCD_COLOR_BLUE2 0x051F
#define | LCD_COLOR_CYAN 0x7FFF
#define | LCD_COLOR_GREEN 0x07E0
#define | LCD_COLOR_GREY 0xF7DE
#define | LCD_COLOR_MAGENTA 0xF81F
#define | LCD_COLOR_RED 0xF800
#define | LCD_COLOR_WHITE 0xFFFF
LCD color.
#define | LCD_COLOR_YELLOW 0xFFE0
#define | LCD_DEFAULT_FONT Font16x24
LCD default font.
#define | LCD_DIR_HORIZONTAL 0x0000
LCD Direction.
#define | LCD_DIR_VERTICAL 0x0001
#define | LCD_LINE_0 LINE(0)
LCD Lines depending on the chosen fonts.
#define | LCD_LINE_1 LINE(1)
#define | LCD_LINE_10 LINE(10)
#define | LCD_LINE_11 LINE(11)
#define | LCD_LINE_12 LINE(12)
#define | LCD_LINE_13 LINE(13)
#define | LCD_LINE_14 LINE(14)
#define | LCD_LINE_15 LINE(15)
#define | LCD_LINE_16 LINE(16)
#define | LCD_LINE_17 LINE(17)
#define | LCD_LINE_18 LINE(18)
#define | LCD_LINE_19 LINE(19)
#define | LCD_LINE_2 LINE(2)
#define | LCD_LINE_20 LINE(20)
#define | LCD_LINE_21 LINE(21)
#define | LCD_LINE_22 LINE(22)
#define | LCD_LINE_23 LINE(23)
#define | LCD_LINE_24 LINE(24)
#define | LCD_LINE_25 LINE(25)
#define | LCD_LINE_26 LINE(26)
#define | LCD_LINE_27 LINE(27)
#define | LCD_LINE_28 LINE(28)
#define | LCD_LINE_29 LINE(29)
#define | LCD_LINE_3 LINE(3)
#define | LCD_LINE_4 LINE(4)
#define | LCD_LINE_5 LINE(5)
#define | LCD_LINE_6 LINE(6)
#define | LCD_LINE_7 LINE(7)
#define | LCD_LINE_8 LINE(8)
#define | LCD_LINE_9 LINE(9)
#define | LCD_NCS_GPIO_CLK RCC_APB2Periph_GPIOB
#define | LCD_NCS_GPIO_PORT GPIOB
#define | LCD_NCS_PIN GPIO_Pin_2
LCD Control pins.
#define | LCD_NWR_GPIO_CLK RCC_APB2Periph_GPIOD
#define | LCD_NWR_GPIO_PORT GPIOD
#define | LCD_NWR_PIN GPIO_Pin_15
#define | LCD_PIXEL_HEIGHT 0x00F0
#define | LCD_PIXEL_WIDTH 0x0140
LCD Size (Width and Height)
#define | LCD_REG_0 0x00
LCD Registers.
#define | LCD_REG_1 0x01
#define | LCD_REG_10 0x0A
#define | LCD_REG_106 0x6A
#define | LCD_REG_118 0x76
#define | LCD_REG_12 0x0C
#define | LCD_REG_128 0x80
#define | LCD_REG_129 0x81
#define | LCD_REG_13 0x0D
#define | LCD_REG_130 0x82
#define | LCD_REG_131 0x83
#define | LCD_REG_132 0x84
#define | LCD_REG_133 0x85
#define | LCD_REG_134 0x86
#define | LCD_REG_135 0x87
#define | LCD_REG_136 0x88
#define | LCD_REG_137 0x89
#define | LCD_REG_139 0x8B
#define | LCD_REG_14 0x0E
#define | LCD_REG_140 0x8C
#define | LCD_REG_141 0x8D
#define | LCD_REG_143 0x8F
#define | LCD_REG_144 0x90
#define | LCD_REG_145 0x91
#define | LCD_REG_146 0x92
#define | LCD_REG_147 0x93
#define | LCD_REG_148 0x94
#define | LCD_REG_149 0x95
#define | LCD_REG_15 0x0F
#define | LCD_REG_150 0x96
#define | LCD_REG_151 0x97
#define | LCD_REG_152 0x98
#define | LCD_REG_153 0x99
#define | LCD_REG_154 0x9A
#define | LCD_REG_157 0x9D
#define | LCD_REG_16 0x10
#define | LCD_REG_17 0x11
#define | LCD_REG_18 0x12
#define | LCD_REG_19 0x13
#define | LCD_REG_192 0xC0
#define | LCD_REG_193 0xC1
#define | LCD_REG_2 0x02
#define | LCD_REG_20 0x14
#define | LCD_REG_21 0x15
#define | LCD_REG_22 0x16
#define | LCD_REG_227 0xE3
#define | LCD_REG_229 0xE5
#define | LCD_REG_23 0x17
#define | LCD_REG_231 0xE7
#define | LCD_REG_239 0xEF
#define | LCD_REG_24 0x18
#define | LCD_REG_25 0x19
#define | LCD_REG_26 0x1A
#define | LCD_REG_27 0x1B
#define | LCD_REG_28 0x1C
#define | LCD_REG_29 0x1D
#define | LCD_REG_3 0x03
#define | LCD_REG_30 0x1E
#define | LCD_REG_31 0x1F
#define | LCD_REG_32 0x20
#define | LCD_REG_33 0x21
#define | LCD_REG_34 0x22
#define | LCD_REG_36 0x24
#define | LCD_REG_37 0x25
#define | LCD_REG_4 0x04
#define | LCD_REG_40 0x28
#define | LCD_REG_41 0x29
#define | LCD_REG_43 0x2B
#define | LCD_REG_45 0x2D
#define | LCD_REG_48 0x30
#define | LCD_REG_49 0x31
#define | LCD_REG_5 0x05
#define | LCD_REG_50 0x32
#define | LCD_REG_51 0x33
#define | LCD_REG_52 0x34
#define | LCD_REG_53 0x35
#define | LCD_REG_54 0x36
#define | LCD_REG_55 0x37
#define | LCD_REG_56 0x38
#define | LCD_REG_57 0x39
#define | LCD_REG_59 0x3B
#define | LCD_REG_6 0x06
#define | LCD_REG_60 0x3C
#define | LCD_REG_61 0x3D
#define | LCD_REG_62 0x3E
#define | LCD_REG_63 0x3F
#define | LCD_REG_64 0x40
#define | LCD_REG_65 0x41
#define | LCD_REG_66 0x42
#define | LCD_REG_67 0x43
#define | LCD_REG_68 0x44
#define | LCD_REG_69 0x45
#define | LCD_REG_7 0x07
#define | LCD_REG_70 0x46
#define | LCD_REG_71 0x47
#define | LCD_REG_72 0x48
#define | LCD_REG_73 0x49
#define | LCD_REG_74 0x4A
#define | LCD_REG_75 0x4B
#define | LCD_REG_76 0x4C
#define | LCD_REG_77 0x4D
#define | LCD_REG_78 0x4E
#define | LCD_REG_79 0x4F
#define | LCD_REG_8 0x08
#define | LCD_REG_80 0x50
#define | LCD_REG_81 0x51
#define | LCD_REG_82 0x52
#define | LCD_REG_83 0x53
#define | LCD_REG_9 0x09
#define | LCD_REG_96 0x60
#define | LCD_REG_97 0x61
#define | LCD_RS_GPIO_CLK RCC_APB2Periph_GPIOD
#define | LCD_RS_GPIO_PORT GPIOD
#define | LCD_RS_PIN GPIO_Pin_7
#define | LCD_SPI SPI2
LCD SPI Interface pins.
#define | LCD_SPI_CLK RCC_APB1Periph_SPI2
#define | LCD_SPI_MISO_GPIO_CLK RCC_APB2Periph_GPIOB
#define | LCD_SPI_MISO_GPIO_PORT GPIOB
#define | LCD_SPI_MISO_PIN GPIO_Pin_14
#define | LCD_SPI_MOSI_GPIO_CLK RCC_APB2Periph_GPIOB
#define | LCD_SPI_MOSI_GPIO_PORT GPIOB
#define | LCD_SPI_MOSI_PIN GPIO_Pin_15
#define | LCD_SPI_SCK_GPIO_CLK RCC_APB2Periph_GPIOB
#define | LCD_SPI_SCK_GPIO_PORT GPIOB
#define | LCD_SPI_SCK_PIN GPIO_Pin_13

Typedefs

typedef struct Point * | pPoint

Functions

void | LCD_Clear (uint16_t Color)
Clears the hole LCD.
void | LCD_ClearLine (uint8_t Line)
Clears the selected line.
void | LCD_ClosedPolyLine (pPoint Points, uint16_t PointCount)
Displays a closed polyline (between many points).
void | LCD_ClosedPolyLineRelative (pPoint Points, uint16_t PointCount)
Displays a closed relative polyline (between many points).
void | LCD_CtrlLinesConfig (void)
Configures LCD control lines in Output Push-Pull mode.
void | LCD_CtrlLinesWrite (GPIO_TypeDef *GPIOx, uint16_t CtrlPins, BitAction BitVal)
Sets or reset LCD control lines.
void | LCD_DeInit (void)
DeInitializes the LCD.
void | LCD_DisplayChar (uint8_t Line, uint16_t Column, uint8_t Ascii)
Displays one character (16dots width, 24dots height).
void | LCD_DisplayOff (void)
Disables the Display.
void | LCD_DisplayOn (void)
Enables the Display.
void | LCD_DisplayStringLine (uint8_t Line, uint8_t *ptr)
Displays a maximum of 20 char on the LCD.
void | LCD_DrawBMP (uint32_t BmpAddress)
void | LCD_DrawChar (uint8_t Xpos, uint16_t Ypos, const uint16_t *c)
Draws a character on LCD.
void | LCD_DrawCircle (uint8_t Xpos, uint16_t Ypos, uint16_t Radius)
Displays a circle.
void | LCD_DrawFullCircle (uint16_t Xpos, uint16_t Ypos, uint16_t Radius)
Displays a full circle.
void | LCD_DrawFullRect (uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height)
Displays a full rectangle.
void | LCD_DrawLine (uint8_t Xpos, uint16_t Ypos, uint16_t Length, uint8_t Direction)
Displays a line.
void | LCD_DrawMonoPict (const uint32_t *Pict)
Displays a monocolor picture.
void | LCD_DrawRect (uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width)
Displays a rectangle.
void | LCD_DrawUniLine (uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2)
Displays an uni line (between two points).
void | LCD_FillPolyLine (pPoint Points, uint16_t PointCount)
Displays a full polyline (between many points).
void | LCD_GetColors (__IO uint16_t *_TextColor, __IO uint16_t *_BackColor)
Gets the LCD Text and Background colors.
sFONT * | LCD_GetFont (void)
Gets the Text Font.
void | LCD_nCS_StartByte (uint8_t Start_Byte)
Reset LCD control line(/CS) and Send Start-Byte.
void | LCD_PolyLine (pPoint Points, uint16_t PointCount)
Displays an polyline (between many points).
void | LCD_PolyLineRelative (pPoint Points, uint16_t PointCount)
Displays a relative polyline (between many points).
void | LCD_PowerOn (void)
Power on the LCD.
uint16_t | LCD_ReadReg (uint8_t LCD_Reg)
Reads the selected LCD Register.
void | LCD_SetBackColor (__IO uint16_t Color)
Sets the Background color.
void | LCD_SetColors (__IO uint16_t _TextColor, __IO uint16_t _BackColor)
Sets the LCD Text and Background colors.
void | LCD_SetCursor (uint8_t Xpos, uint16_t Ypos)
Sets the cursor position.
void | LCD_SetDisplayWindow (uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width)
Sets a display window.
void | LCD_SetFont (sFONT *fonts)
Sets the Text Font.
void | LCD_SetTextColor (__IO uint16_t Color)
Sets the Text color.
void | LCD_Setup (void)
Setups the LCD.
void | LCD_SPIConfig (void)
Configures the LCD_SPI interface.
void | LCD_WindowModeDisable (void)
Disables LCD Window mode.
void | LCD_WriteRAM (uint16_t RGB_Code)
Writes to the LCD RAM.
void | LCD_WriteRAM_Prepare (void)
Prepare to write to the LCD RAM.
void | LCD_WriteRAMWord (uint16_t RGB_Code)
Writes 1 word to the LCD RAM.
void | LCD_WriteReg (uint8_t LCD_Reg, uint16_t LCD_RegValue)
Writes to the selected LCD register.
void | LCD_WriteRegIndex (uint8_t LCD_Reg)
Writes index to select the LCD register.
void | STM32100B_LCD_Init (void)
Initializes the LCD.

Detailed Description

This file contains all the functions prototypes for the stm32100b_eval_lcd firmware driver.

Author:
MCD Application Team
Version:
V4.5.0
Date:
07-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm32100b_eval_lcd.h.


STM32F10x Standard Peripherals Firmware Library: stm32100e_eval.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • STM32100E_EVAL
Functions | Variables

stm32100e_eval.c File Reference

This file provides

  • set of firmware functions to manage Leds, push-button and COM ports
  • low level initialization functions for SD card (on SDIO), SPI serial flash (sFLASH) and temperature sensor (LM75) available on STM32100E-EVAL evaluation board from STMicroelectronics.
More...

#include "stm32100e_eval.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_dma.h"

Go to the source code of this file.

Functions

void | LM75_LowLevel_DeInit (void)
DeInitializes the LM75_I2C.
void | LM75_LowLevel_Init (void)
Initializes the LM75_I2C.
void | SD_LowLevel_DeInit (void)
DeInitializes the SD/SD communication.
void | SD_LowLevel_Init (void)
Initializes the SD_SPI and CS pins.
void | sEE_LowLevel_DeInit (void)
DeInitializes peripherals used by the I2C EEPROM driver.
void | sEE_LowLevel_DMAConfig (uint32_t pBuffer, uint32_t BufferSize, uint32_t Direction)
Initializes DMA channel used by the I2C EEPROM driver.
void | sEE_LowLevel_Init (void)
Initializes peripherals used by the I2C EEPROM driver.
void | sFLASH_LowLevel_DeInit (void)
DeInitializes the peripherals used by the SPI FLASH driver.
void | sFLASH_LowLevel_Init (void)
Initializes the peripherals used by the SPI FLASH driver.
void | STM_EVAL_COMInit (COM_TypeDef COM, USART_InitTypeDef *USART_InitStruct)
Configures COM port.
void | STM_EVAL_LEDInit (Led_TypeDef Led)
Configures LED GPIO.
void | STM_EVAL_LEDOff (Led_TypeDef Led)
Turns selected LED Off.
void | STM_EVAL_LEDOn (Led_TypeDef Led)
Turns selected LED On.
void | STM_EVAL_LEDToggle (Led_TypeDef Led)
Toggles the selected LED.
uint32_t | STM_EVAL_PBGetState (Button_TypeDef Button)
Returns the selected Button state.
void | STM_EVAL_PBInit (Button_TypeDef Button, ButtonMode_TypeDef Button_Mode)
Configures Button GPIO and EXTI Line.

Variables

const uint32_t | BUTTON_CLK [BUTTONn]
const uint16_t | BUTTON_EXTI_LINE [BUTTONn]
const uint16_t | BUTTON_IRQn [BUTTONn]
const uint16_t | BUTTON_PIN [BUTTONn]
const uint16_t | BUTTON_PIN_SOURCE [BUTTONn]
GPIO_TypeDef * | BUTTON_PORT [BUTTONn]
const uint16_t | BUTTON_PORT_SOURCE [BUTTONn]
const uint16_t | COM_RX_PIN [COMn] = {EVAL_COM1_RX_PIN, EVAL_COM2_RX_PIN}
GPIO_TypeDef * | COM_RX_PORT [COMn] = {EVAL_COM1_RX_GPIO_PORT, EVAL_COM2_RX_GPIO_PORT}
const uint32_t | COM_RX_PORT_CLK [COMn] = {EVAL_COM1_RX_GPIO_CLK, EVAL_COM2_RX_GPIO_CLK}
const uint16_t | COM_TX_PIN [COMn] = {EVAL_COM1_TX_PIN, EVAL_COM2_TX_PIN}
GPIO_TypeDef * | COM_TX_PORT [COMn] = {EVAL_COM1_TX_GPIO_PORT, EVAL_COM2_TX_GPIO_PORT}
const uint32_t | COM_TX_PORT_CLK [COMn] = {EVAL_COM1_TX_GPIO_CLK, EVAL_COM2_TX_GPIO_CLK}
USART_TypeDef * | COM_USART [COMn] = {EVAL_COM1, EVAL_COM2}
const uint32_t | COM_USART_CLK [COMn] = {EVAL_COM1_CLK, EVAL_COM2_CLK}
const uint32_t | GPIO_CLK [LEDn]
const uint16_t | GPIO_PIN [LEDn]
GPIO_TypeDef * | GPIO_PORT [LEDn]
DMA_InitTypeDef sEEDMA_InitStructure

Detailed Description

This file provides

  • set of firmware functions to manage Leds, push-button and COM ports
  • low level initialization functions for SD card (on SDIO), SPI serial flash (sFLASH) and temperature sensor (LM75) available on STM32100E-EVAL evaluation board from STMicroelectronics.
Author:
MCD Application Team
Version:
V4.5.0
Date:
07-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm32100e_eval.c.


STM32F10x Standard Peripherals Firmware Library: stm32100e_eval.h File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • STM32100E_EVAL
Defines | Functions

stm32100e_eval.h File Reference

This file contains definitions for STM32100E_EVAL's Leds, push-buttons COM ports, sFLASH (on SPI) and Temperature Sensor LM75 (on I2C) hardware resources. More...

#include "stm32_eval.h"

Go to the source code of this file.

Defines

#define | BUTTONn 8
#define | COMn 2
#define | DOWN_BUTTON_EXTI_IRQn EXTI15_10_IRQn
#define | DOWN_BUTTON_EXTI_LINE EXTI_Line11
#define | DOWN_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource11
#define | DOWN_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOG
#define | DOWN_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOG
#define | DOWN_BUTTON_GPIO_PORT GPIOG
#define | DOWN_BUTTON_PIN GPIO_Pin_11
Joystick Down push-button.
#define | EVAL_COM1 USART1
Definition for COM port1, connected to USART1.
#define | EVAL_COM1_CLK RCC_APB2Periph_USART1
#define | EVAL_COM1_IRQn USART1_IRQn
#define | EVAL_COM1_RX_GPIO_CLK RCC_APB2Periph_GPIOA
#define | EVAL_COM1_RX_GPIO_PORT GPIOA
#define | EVAL_COM1_RX_PIN GPIO_Pin_10
#define | EVAL_COM1_TX_GPIO_CLK RCC_APB2Periph_GPIOA
#define | EVAL_COM1_TX_GPIO_PORT GPIOA
#define | EVAL_COM1_TX_PIN GPIO_Pin_9
#define | EVAL_COM2 USART2
Definition for COM port2, connected to USART2.
#define | EVAL_COM2_CLK RCC_APB1Periph_USART2
#define | EVAL_COM2_IRQn USART2_IRQn
#define | EVAL_COM2_RX_GPIO_CLK RCC_APB2Periph_GPIOA
#define | EVAL_COM2_RX_GPIO_PORT GPIOA
#define | EVAL_COM2_RX_PIN GPIO_Pin_3
#define | EVAL_COM2_TX_GPIO_CLK RCC_APB2Periph_GPIOA
#define | EVAL_COM2_TX_GPIO_PORT GPIOA
#define | EVAL_COM2_TX_PIN GPIO_Pin_2
#define | KEY_BUTTON_EXTI_IRQn EXTI9_5_IRQn
#define | KEY_BUTTON_EXTI_LINE EXTI_Line8
#define | KEY_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource8
#define | KEY_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOG
#define | KEY_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOG
#define | KEY_BUTTON_GPIO_PORT GPIOG
#define | KEY_BUTTON_PIN GPIO_Pin_8
Key push-button.
#define | LED1_GPIO_CLK RCC_APB2Periph_GPIOF
#define | LED1_GPIO_PORT GPIOF
#define | LED1_PIN GPIO_Pin_6
#define | LED2_GPIO_CLK RCC_APB2Periph_GPIOF
#define | LED2_GPIO_PORT GPIOF
#define | LED2_PIN GPIO_Pin_7
#define | LED3_GPIO_CLK RCC_APB2Periph_GPIOF
#define | LED3_GPIO_PORT GPIOF
#define | LED3_PIN GPIO_Pin_8
#define | LED4_GPIO_CLK RCC_APB2Periph_GPIOF
#define | LED4_GPIO_PORT GPIOF
#define | LED4_PIN GPIO_Pin_9
#define | LEDn 4
#define | LEFT_BUTTON_EXTI_IRQn EXTI15_10_IRQn
#define | LEFT_BUTTON_EXTI_LINE EXTI_Line14
#define | LEFT_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource14
#define | LEFT_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOG
#define | LEFT_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOG
#define | LEFT_BUTTON_GPIO_PORT GPIOG
#define | LEFT_BUTTON_PIN GPIO_Pin_14
Joystick Left push-button.
#define | LM75_DMA_CLK RCC_AHBPeriph_DMA1
#define | LM75_DMA_RX_CHANNEL DMA1_Channel5
#define | LM75_DMA_RX_TCFLAG DMA1_FLAG_TC5
#define | LM75_DMA_TX_CHANNEL DMA1_Channel4
#define | LM75_DMA_TX_TCFLAG DMA1_FLAG_TC4
#define | LM75_I2C I2C2
LM75 Temperature Sensor I2C Interface pins.
#define | LM75_I2C_CLK RCC_APB1Periph_I2C2
#define | LM75_I2C_DR ((uint32_t)0x40005810)
#define | LM75_I2C_SCL_GPIO_CLK RCC_APB2Periph_GPIOB
#define | LM75_I2C_SCL_GPIO_PORT GPIOB
#define | LM75_I2C_SCL_PIN GPIO_Pin_10
#define | LM75_I2C_SDA_GPIO_CLK RCC_APB2Periph_GPIOB
#define | LM75_I2C_SDA_GPIO_PORT GPIOB
#define | LM75_I2C_SDA_PIN GPIO_Pin_11
#define | LM75_I2C_SMBUSALERT_GPIO_CLK RCC_APB2Periph_GPIOB
#define | LM75_I2C_SMBUSALERT_GPIO_PORT GPIOB
#define | LM75_I2C_SMBUSALERT_PIN GPIO_Pin_12
#define | RIGHT_BUTTON_EXTI_IRQn EXTI15_10_IRQn
#define | RIGHT_BUTTON_EXTI_LINE EXTI_Line13
#define | RIGHT_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource13
#define | RIGHT_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOG
#define | RIGHT_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOG
#define | RIGHT_BUTTON_GPIO_PORT GPIOG
#define | RIGHT_BUTTON_PIN GPIO_Pin_13
Joystick Right push-button.
#define | SD_CS_GPIO_CLK RCC_APB2Periph_GPIOG
#define | SD_CS_GPIO_PORT GPIOG
#define | SD_CS_PIN GPIO_Pin_6
#define | SD_DETECT_GPIO_CLK RCC_APB2Periph_GPIOF
#define | SD_DETECT_GPIO_PORT GPIOF
#define | SD_DETECT_PIN GPIO_Pin_11
#define | SD_SPI SPI2
SD SPI Interface pins.
#define | SD_SPI_CLK RCC_APB1Periph_SPI2
#define | SD_SPI_MISO_GPIO_CLK RCC_APB2Periph_GPIOB
#define | SD_SPI_MISO_GPIO_PORT GPIOB
#define | SD_SPI_MISO_PIN GPIO_Pin_14
#define | SD_SPI_MOSI_GPIO_CLK RCC_APB2Periph_GPIOB
#define | SD_SPI_MOSI_GPIO_PORT GPIOB
#define | SD_SPI_MOSI_PIN GPIO_Pin_15
#define | SD_SPI_SCK_GPIO_CLK RCC_APB2Periph_GPIOB
#define | SD_SPI_SCK_GPIO_PORT GPIOB
#define | SD_SPI_SCK_PIN GPIO_Pin_13
#define | sEE_DIRECTION_RX 1
#define | sEE_DIRECTION_TX 0
#define | sEE_I2C I2C2
I2C EEPROM Interface pins.
#define | sEE_I2C_CLK RCC_APB1Periph_I2C2
#define | sEE_I2C_DMA DMA1
#define | sEE_I2C_DMA_CHANNEL_RX DMA1_Channel5
#define | sEE_I2C_DMA_CHANNEL_TX DMA1_Channel4
#define | sEE_I2C_DMA_CLK RCC_AHBPeriph_DMA1
#define | sEE_I2C_DMA_FLAG_RX_GL DMA1_IT_GL5
#define | sEE_I2C_DMA_FLAG_RX_TC DMA1_IT_TC5
#define | sEE_I2C_DMA_FLAG_TX_GL DMA1_IT_GL4
#define | sEE_I2C_DMA_FLAG_TX_TC DMA1_IT_TC4
#define | sEE_I2C_DMA_PREPRIO 0
#define | sEE_I2C_DMA_RX_IRQHandler DMA1_Channel5_IRQHandler
#define | sEE_I2C_DMA_RX_IRQn DMA1_Channel5_IRQn
#define | sEE_I2C_DMA_SUBPRIO 0
#define | sEE_I2C_DMA_TX_IRQHandler DMA1_Channel4_IRQHandler
#define | sEE_I2C_DMA_TX_IRQn DMA1_Channel4_IRQn
#define | sEE_I2C_DR_Address ((uint32_t)0x40005810)
#define | sEE_I2C_SCL_GPIO_CLK RCC_APB2Periph_GPIOB
#define | sEE_I2C_SCL_GPIO_PORT GPIOB
#define | sEE_I2C_SCL_PIN GPIO_Pin_10
#define | sEE_I2C_SDA_GPIO_CLK RCC_APB2Periph_GPIOB
#define | sEE_I2C_SDA_GPIO_PORT GPIOB
#define | sEE_I2C_SDA_PIN GPIO_Pin_11
#define | sEE_M24C64_32
#define | sEE_TIME_CONST 24
#define | sEE_USE_DMA
#define | SEL_BUTTON_EXTI_IRQn EXTI9_5_IRQn
#define | SEL_BUTTON_EXTI_LINE EXTI_Line7
#define | SEL_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource7
#define | SEL_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOG
#define | SEL_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOG
#define | SEL_BUTTON_GPIO_PORT GPIOG
#define | SEL_BUTTON_PIN GPIO_Pin_7
Joystick Sel push-button.
#define | sFLASH_CS_GPIO_CLK RCC_APB2Periph_GPIOE
#define | sFLASH_CS_GPIO_PORT GPIOE
#define | sFLASH_CS_PIN GPIO_Pin_6
#define | sFLASH_SPI SPI1
M25P FLASH SPI Interface pins.
#define | sFLASH_SPI_CLK RCC_APB2Periph_SPI1
#define | sFLASH_SPI_MISO_GPIO_CLK RCC_APB2Periph_GPIOA
#define | sFLASH_SPI_MISO_GPIO_PORT GPIOA
#define | sFLASH_SPI_MISO_PIN GPIO_Pin_6
#define | sFLASH_SPI_MOSI_GPIO_CLK RCC_APB2Periph_GPIOA
#define | sFLASH_SPI_MOSI_GPIO_PORT GPIOA
#define | sFLASH_SPI_MOSI_PIN GPIO_Pin_7
#define | sFLASH_SPI_SCK_GPIO_CLK RCC_APB2Periph_GPIOA
#define | sFLASH_SPI_SCK_GPIO_PORT GPIOA
#define | sFLASH_SPI_SCK_PIN GPIO_Pin_5
#define | TAMPER_BUTTON_EXTI_IRQn EXTI15_10_IRQn
#define | TAMPER_BUTTON_EXTI_LINE EXTI_Line13
#define | TAMPER_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource13
#define | TAMPER_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOC
#define | TAMPER_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOC
#define | TAMPER_BUTTON_GPIO_PORT GPIOC
#define | TAMPER_BUTTON_PIN GPIO_Pin_13
Tamper push-button.
#define | UP_BUTTON_EXTI_IRQn EXTI15_10_IRQn
#define | UP_BUTTON_EXTI_LINE EXTI_Line15
#define | UP_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource15
#define | UP_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOG
#define | UP_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOG
#define | UP_BUTTON_GPIO_PORT GPIOG
#define | UP_BUTTON_PIN GPIO_Pin_15
Joystick Up push-button.
#define | WAKEUP_BUTTON_EXTI_IRQn EXTI0_IRQn
#define | WAKEUP_BUTTON_EXTI_LINE EXTI_Line0
#define | WAKEUP_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource0
#define | WAKEUP_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOA
#define | WAKEUP_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOA
#define | WAKEUP_BUTTON_GPIO_PORT GPIOA
#define | WAKEUP_BUTTON_PIN GPIO_Pin_0
Wakeup push-button.

Functions

void | LM75_LowLevel_DeInit (void)
DeInitializes the LM75_I2C.
void | LM75_LowLevel_Init (void)
Initializes the LM75_I2C.
void | SD_LowLevel_DeInit (void)
DeInitializes the SD/SD communication.
void | SD_LowLevel_Init (void)
Initializes the SD_SPI and CS pins.
void | sEE_LowLevel_DeInit (void)
DeInitializes peripherals used by the I2C EEPROM driver.
void | sEE_LowLevel_DMAConfig (uint32_t pBuffer, uint32_t BufferSize, uint32_t Direction)
Initializes DMA channel used by the I2C EEPROM driver.
void | sEE_LowLevel_Init (void)
Initializes peripherals used by the I2C EEPROM driver.
void | sFLASH_LowLevel_DeInit (void)
DeInitializes the peripherals used by the SPI FLASH driver.
void | sFLASH_LowLevel_Init (void)
Initializes the peripherals used by the SPI FLASH driver.
void | STM_EVAL_COMInit (COM_TypeDef COM, USART_InitTypeDef *USART_InitStruct)
Configures COM port.
void | STM_EVAL_LEDInit (Led_TypeDef Led)
Configures LED GPIO.
void | STM_EVAL_LEDOff (Led_TypeDef Led)
Turns selected LED Off.
void | STM_EVAL_LEDOn (Led_TypeDef Led)
Turns selected LED On.
void | STM_EVAL_LEDToggle (Led_TypeDef Led)
Toggles the selected LED.
uint32_t | STM_EVAL_PBGetState (Button_TypeDef Button)
Returns the selected Button state.
void | STM_EVAL_PBInit (Button_TypeDef Button, ButtonMode_TypeDef Button_Mode)
Configures Button GPIO and EXTI Line.

Detailed Description

This file contains definitions for STM32100E_EVAL's Leds, push-buttons COM ports, sFLASH (on SPI) and Temperature Sensor LM75 (on I2C) hardware resources.

Author:
MCD Application Team
Version:
V4.5.0
Date:
07-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm32100e_eval.h.


STM32F10x Standard Peripherals Firmware Library: stm32100e_eval_cec.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • STM32100E_EVAL
Functions | Variables

stm32100e_eval_cec.c File Reference

This file provides all the STM32100E-EVAL HDMI-CEC firmware functions. More...

#include "stm32100e_eval_cec.h"

Go to the source code of this file.

Functions

HDMI_CEC_Error | HDMI_CEC_CheckConnectedDevices (void)
Check the connected CEC devices.
void | HDMI_CEC_CommandCallBack (void)
Handle CEC command receive callback.
HDMI_CEC_Error | HDMI_CEC_GetErrorStatus (void)
Get the ESR register status.
HDMI_CEC_Error | HDMI_CEC_Init (void)
Initializes the HDMI CEC.
void | HDMI_CEC_ProcessIRQSrc (void)
Allows to process all the interrupts that are high.
HDMI_CEC_Error | HDMI_CEC_ReportPhysicalAddress (void)
Report physical address to all other devices thus allowing any device to create a map of the network.
HDMI_CEC_Error HDMI_CEC_TransmitMessage (HDMI_CEC_Message *HDMI_CEC_TX_MessageStructure)
Transmit message by taking data from typedef struct CEC_Meassage.
static HDMI_CEC_Error | LogicalAddressAllocation (void)
Allocate the logical address.
static HDMI_CEC_Error | PhysicalAddressDiscovery (void)
Physical address discovery.

Variables

__IO uint8_t | AbortReason = 0
__IO uint32_t | BufferCount = 0
__IO uint8_t | BufferPointer [15]
__IO uint8_t | CECDevicesNumber = 0
__IO uint8_t | DeviceCount = 0
__IO uint8_t | DeviceType = 0
__IO uint8_t | FeatureOpcode = 0
HDMI_CEC_Map | HDMI_CEC_DeviceMap [14]
uint8_t * | HDMI_CEC_Follower_String [13][2]
HDMI_CEC_Map HDMI_CEC_MapStruct
HDMI_CEC_Message HDMI_CEC_RX_MessageStructPrivate
HDMI_CEC_Message HDMI_CEC_TX_MessageStructPrivate
HDMI_CEC_Message HDMI_CEC_TX_MessageStructure
__IO uint8_t | MyLogicalAddress = 0
__IO uint16_t | MyPhysicalAddress = 0
__IO uint32_t | ReceivedFrame = 0
__IO uint32_t | ReceiveStatus = 0
__IO uint8_t | RecepErrorCode = 0
__IO uint32_t | RxCounter = 0
__IO uint32_t | SendFrame = 0
__IO uint32_t | SendStatus = 0
__IO uint8_t | TransErrorCode = 0
__IO uint32_t | TxCounter = 0

Detailed Description

This file provides all the STM32100E-EVAL HDMI-CEC firmware functions.

Author:
MCD Application Team
Version:
V4.5.0
Date:
07-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm32100e_eval_cec.c.


STM32F10x Standard Peripherals Firmware Library: stm32100e_eval_cec.h File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • STM32100E_EVAL
Data Structures | Defines | Enumerations | Functions

stm32100e_eval_cec.h File Reference

This file contains all the functions prototypes for the stm32100e_eval_cec firmware driver. More...

#include "stm32f10x.h"

Go to the source code of this file.

Data Structures

struct | HDMI_CEC_Map
struct | HDMI_CEC_Message
CEC Init Structure definition. More...

Defines

#define | HDMI_CEC_AUDIOSYSTEM 0x05
#define | HDMI_CEC_CANNOTPROVIDE_SOURCE 0x02
#define | HDMI_CEC_HPD_GPIO_CLK RCC_APB2Periph_GPIOB
#define | HDMI_CEC_HPD_GPIO_PORT GPIOB
#define | HDMI_CEC_HPD_HIGH() GPIO_SetBits(HDMI_CEC_HPD_GPIO_PORT, HDMI_CEC_HPD_PIN)
#define | HDMI_CEC_HPD_LOW() GPIO_ResetBits(HDMI_CEC_HPD_GPIO_PORT, HDMI_CEC_HPD_PIN)
#define | HDMI_CEC_HPD_PIN GPIO_Pin_9
HDMI CEC HPD (Hot Plug Detect) Interface pin.
#define | HDMI_CEC_I2C I2C1
#define | HDMI_CEC_I2C_CLK RCC_APB1Periph_I2C1
#define | HDMI_CEC_I2C_CLOCK_SPEED 100000
#define | HDMI_CEC_I2C_GPIO_CLK RCC_APB2Periph_GPIOB
#define | HDMI_CEC_I2C_GPIO_PORT GPIOB
#define | HDMI_CEC_I2C_SCL_PIN GPIO_Pin_6
HDMI CEC I2C Interface pins.
#define | HDMI_CEC_I2C_SDA_PIN GPIO_Pin_7
#define | HDMI_CEC_I2C_SLAVE_ADDRESS7 0xA0
#define | HDMI_CEC_INVALID_OPERAND 0x03
#define | HDMI_CEC_LINE_GPIO_CLK RCC_APB2Periph_GPIOB
#define | HDMI_CEC_LINE_GPIO_PORT GPIOB
#define | HDMI_CEC_LINE_PIN GPIO_Pin_8
HDMI CEC Interface pin.
#define | HDMI_CEC_NOT_CORRECT_MODETORESPOND 0x01
#define | HDMI_CEC_OPCODE_ABORT ((uint8_t) 0xFF)
#define | HDMI_CEC_OPCODE_ACTIVE_SOURCE ((uint8_t) 0x82)
HDMI CEC specific commands.
#define | HDMI_CEC_OPCODE_CEC_VERSION ((uint8_t) 0x9E)
#define | HDMI_CEC_OPCODE_CLEAR_ANALOGUE_TIMER ((uint8_t) 0x33)
#define | HDMI_CEC_OPCODE_CLEAR_DIGITAL_TIMER ((uint8_t) 0x99)
#define | HDMI_CEC_OPCODE_CLEAR_EXTERNAL_TIMER ((uint8_t) 0xA1)
#define | HDMI_CEC_OPCODE_DECK_CONTROL ((uint8_t) 0x42)
#define | HDMI_CEC_OPCODE_DECK_STATUS ((uint8_t) 0x1B)
#define | HDMI_CEC_OPCODE_DEVICE_VENDOR_ID ((uint8_t) 0x87)
#define | HDMI_CEC_OPCODE_FEATURE_ABORT ((uint8_t) 0x00)
#define | HDMI_CEC_OPCODE_GET_CEC_VERSION ((uint8_t) 0x9F)
#define | HDMI_CEC_OPCODE_GET_MENU_LANGUAGE ((uint8_t) 0x91)
#define | HDMI_CEC_OPCODE_GIVE_AUDIO_STATUS ((uint8_t) 0x71)
#define | HDMI_CEC_OPCODE_GIVE_DECK_STATUS ((uint8_t) 0x1A)
#define | HDMI_CEC_OPCODE_GIVE_DEVICE_POWER_STATUS ((uint8_t) 0x8F)
#define | HDMI_CEC_OPCODE_GIVE_DEVICE_VENDOR_ID ((uint8_t) 0x8C)
#define | HDMI_CEC_OPCODE_GIVE_OSD_NAME ((uint8_t) 0x46)
#define | HDMI_CEC_OPCODE_GIVE_PHYSICAL_ADDRESS ((uint8_t) 0x83)
#define | HDMI_CEC_OPCODE_GIVE_SYSTEM_AUDIO_MODE_STATUS ((uint8_t) 0x7D)
#define | HDMI_CEC_OPCODE_GIVE_TUNER_DEVICE_STATUS ((uint8_t) 0x08)
#define | HDMI_CEC_OPCODE_IMAGE_VIEW_ON ((uint8_t) 0x04)
#define | HDMI_CEC_OPCODE_INACTIVE_SOURCE ((uint8_t) 0x9D)
#define | HDMI_CEC_OPCODE_MENU_REQUEST ((uint8_t) 0x8D)
#define | HDMI_CEC_OPCODE_MENU_STATUS ((uint8_t) 0x8E)
#define | HDMI_CEC_OPCODE_PLAY ((uint8_t) 0x41)
#define | HDMI_CEC_OPCODE_RECORD_OFF ((uint8_t) 0x0B)
#define | HDMI_CEC_OPCODE_RECORD_ON ((uint8_t) 0x09)
#define | HDMI_CEC_OPCODE_RECORD_STATUS ((uint8_t) 0x0A)
#define | HDMI_CEC_OPCODE_RECORD_TV_SCREEN ((uint8_t) 0x0F)
#define | HDMI_CEC_OPCODE_REPORT_AUDIO_STATUS ((uint8_t) 0x7A)
#define | HDMI_CEC_OPCODE_REPORT_PHYSICAL_ADDRESS ((uint8_t) 0x84)
#define | HDMI_CEC_OPCODE_REPORT_POWER_STATUS ((uint8_t) 0x90)
#define | HDMI_CEC_OPCODE_REQUEST_ACTIVE_SOURCE ((uint8_t) 0x85)
#define | HDMI_CEC_OPCODE_ROUTING_CHANGE ((uint8_t) 0x80)
#define | HDMI_CEC_OPCODE_ROUTING_INFORMATION ((uint8_t) 0x81)
#define | HDMI_CEC_OPCODE_SELECT_ANALOGUE_SERVICE ((uint8_t) 0x92)
#define | HDMI_CEC_OPCODE_SELECT_DIGITAL_SERVICE ((uint8_t) 0x93)
#define | HDMI_CEC_OPCODE_SET_ANALOGUE_TIMER ((uint8_t) 0x34)
#define | HDMI_CEC_OPCODE_SET_AUDIO_RATE ((uint8_t) 0x9A)
#define | HDMI_CEC_OPCODE_SET_DIGITAL_TIMER ((uint8_t) 0x97)
#define | HDMI_CEC_OPCODE_SET_EXTERNAL_TIMER ((uint8_t) 0xA2)
#define | HDMI_CEC_OPCODE_SET_MENU_LANGUAGE ((uint8_t) 0x32)
#define | HDMI_CEC_OPCODE_SET_OSD_NAME ((uint8_t) 0x47)
#define | HDMI_CEC_OPCODE_SET_OSD_STRING ((uint8_t) 0x64)
#define | HDMI_CEC_OPCODE_SET_STREAM_PATH ((uint8_t) 0x86)
#define | HDMI_CEC_OPCODE_SET_SYSTEM_AUDIO_MODE ((uint8_t) 0x72)
#define | HDMI_CEC_OPCODE_SET_TIMER_PROGRAM_TITLE ((uint8_t) 0x67)
#define | HDMI_CEC_OPCODE_STANDBY ((uint8_t) 0x36)
#define | HDMI_CEC_OPCODE_SYSTEM_AUDIO_MODE_REQUEST ((uint8_t) 0x70)
#define | HDMI_CEC_OPCODE_SYSTEM_AUDIO_MODE_STATUS ((uint8_t) 0x7E)
#define | HDMI_CEC_OPCODE_TEXT_VIEW_ON ((uint8_t) 0x0D)
#define | HDMI_CEC_OPCODE_TIMER_CLEARED_STATUS ((uint8_t) 0x43)
#define | HDMI_CEC_OPCODE_TIMER_STATUS ((uint8_t) 0x35)
#define | HDMI_CEC_OPCODE_TUNER_DEVICE_STATUS ((uint8_t) 0x07)
#define | HDMI_CEC_OPCODE_TUNER_STEP_DECREMENT ((uint8_t) 0x06)
#define | HDMI_CEC_OPCODE_TUNER_STEP_INCREMENT ((uint8_t) 0x05)
#define | HDMI_CEC_OPCODE_USER_CONTROL_PRESSED ((uint8_t) 0x44)
#define | HDMI_CEC_OPCODE_USER_CONTROL_RELEASED ((uint8_t) 0x45)
#define | HDMI_CEC_OPCODE_VENDOR_COMMAND ((uint8_t) 0x89)
#define | HDMI_CEC_OPCODE_VENDOR_COMMAND_WITH_ID ((uint8_t) 0xA0)
#define | HDMI_CEC_OPCODE_VENDOR_REMOTE_BUTTON_DOWN ((uint8_t) 0x8A)
#define | HDMI_CEC_OPCODE_VENDOR_REMOTE_BUTTON_UP ((uint8_t) 0x8B)
#define | HDMI_CEC_PLAYBACK 0x04
#define | HDMI_CEC_RECORDING 0x01
#define | HDMI_CEC_REFUSED 0x04
#define | HDMI_CEC_ROOT 0x00
HDMI CEC Root (Mainly for TV with a fixed physical address (0.0.0.0)) If you want to configure the STM32100E-EVAL board as CEC Root (Sink) change the following define to 0x1.
#define | HDMI_CEC_TIMEOUT_VALUE ((uint32_t)0x001FFFFF)
#define | HDMI_CEC_TUNER 0x03
#define | HDMI_CEC_TV 0x00
CEC device types.
#define | HDMI_CEC_TX_MESSAGE_LENGTH_MAX ((uint32_t)0x0000000E)
#define | HDMI_CEC_UNRECOGNIZED_OPCODE 0x00
Reason for Abort feature.
#define | HDMI_CEC_VERSION 0x04
To select if the DDC Channel will be used for physical address discovery or not.

Enumerations

enum HDMI_CEC_Error {
HDMI_CEC_BIT_TIMING = (1), HDMI_CEC_BIT_PERIOD = (2), HDMI_CEC_RX_BLOCK_FINISHED = (3), HDMI_CEC_START_BIT = (4),
HDMI_CEC_BLOCK_ACKNOWLEDGE = (5), HDMI_CEC_LINE = (6), HDMI_CEC_TX_BLOCK_FINISHED = (7), HDMI_CEC_DEVICE_UNREGISTRED = (8),
HDMI_CEC_TIMEOUT = (9), HDMI_CEC_OK = (10), HDMI_CEC_BIT_TIMING = (1), HDMI_CEC_BIT_PERIOD = (2),
HDMI_CEC_RX_BLOCK_FINISHED = (3), HDMI_CEC_START_BIT = (4), HDMI_CEC_BLOCK_ACKNOWLEDGE = (5), HDMI_CEC_LINE = (6),
HDMI_CEC_TX_BLOCK_FINISHED = (7), HDMI_CEC_DEVICE_UNREGISTRED = (8), HDMI_CEC_TIMEOUT = (9), HDMI_CEC_OK = (10)
}

Functions

HDMI_CEC_Error | HDMI_CEC_CheckConnectedDevices (void)
Check the connected CEC devices.
void | HDMI_CEC_CommandCallBack (void)
Handle CEC command receive callback.
HDMI_CEC_Error | HDMI_CEC_GetErrorStatus (void)
Get the ESR register status.
HDMI_CEC_Error | HDMI_CEC_Init (void)
Initializes the HDMI CEC.
void | HDMI_CEC_ProcessIRQSrc (void)
Allows to process all the interrupts that are high.
HDMI_CEC_Error | HDMI_CEC_ReportPhysicalAddress (void)
Report physical address to all other devices thus allowing any device to create a map of the network.
HDMI_CEC_Error HDMI_CEC_TransmitMessage (HDMI_CEC_Message *HDMI_CEC_TX_MessageStructure)
Transmit message by taking data from typedef struct CEC_Meassage.

Detailed Description

This file contains all the functions prototypes for the stm32100e_eval_cec firmware driver.

Author:
MCD Application Team
Version:
V4.5.0
Date:
07-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm32100e_eval_cec.h.


STM32F10x Standard Peripherals Firmware Library: stm32100e_eval_fsmc_onenand.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • STM32100E_EVAL
Defines | Functions

stm32100e_eval_fsmc_onenand.c File Reference

This file provides a set of functions needed to drive the KFG1216U2A/B-DIB6 OneNAND memory mounted on STM32100E-EVAL board. More...

#include "stm32100e_eval_fsmc_onenand.h"

Go to the source code of this file.

Defines

#define | BANK1_ONENAND1_ADDR ((uint32_t)0x60000000)
#define | ONENAND_BOOTPARTITION_ADDR ((uint32_t)BANK1_ONENAND1_ADDR)
#define | OneNAND_WRITE(Address, Data) (*(__IO uint16_t *)(Address) = (Data))

Functions

void | OneNAND_AsynchronousRead (uint16_t *pBuffer, OneNAND_ADDRESS Address, uint32_t NumHalfwordToRead)
Reads a block of data from the OneNAND memory using asynchronous mode.
uint16_t | OneNAND_EraseBlock (uint32_t BlockNumber)
Erases the specified OneNAND memory block (128Kb).
void | OneNAND_Init (void)
Configures the FSMC and GPIOs to interface with the OneNAND memory.
uint16_t | OneNAND_ReadControllerStatus (void)
Reads the OneNAND Controller status.
void | OneNAND_ReadID (OneNAND_IDTypeDef *OneNAND_ID)
Reads OneNAND memory's Manufacturer and Device Code.
uint16_t | OneNAND_ReadStatus (void)
Reads the OneNAND memory Interrupt status.
void | OneNAND_Reset (void)
Resets the OneNAND memory.
void | OneNAND_SynchronousRead (uint16_t *pBuffer, OneNAND_ADDRESS Address, uint32_t NumHalfwordToRead)
Reads a block of data from the OneNAND memory using synchronous mode.
uint16_t | OneNAND_UnlockBlock (uint32_t BlockNumber)
Unlocks the specified OneNAND memory block (128Kb).
uint16_t | OneNAND_WriteBuffer (uint16_t *pBuffer, OneNAND_ADDRESS Address, uint32_t NumHalfwordToWrite)
Writes a Half-word buffer to the OneNAND memory.

Detailed Description

This file provides a set of functions needed to drive the KFG1216U2A/B-DIB6 OneNAND memory mounted on STM32100E-EVAL board.

Author:
MCD Application Team
Version:
V4.5.0
Date:
07-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm32100e_eval_fsmc_onenand.c.


STM32F10x Standard Peripherals Firmware Library: stm32100e_eval_fsmc_onenand.h File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • STM32100E_EVAL
Data Structures | Defines | Enumerations | Functions

stm32100e_eval_fsmc_onenand.h File Reference

This file contains all the functions prototypes for the stm32100e_eval_fsmc_onenand firmware driver. More...

#include "stm32f10x.h"

Go to the source code of this file.

Data Structures

struct | OneNAND_ADDRESS
struct | OneNAND_IDTypeDef

Defines

#define | OneNAND_CMD_ERASE ((uint16_t)0x0094)
OneNAND memory command.
#define | OneNAND_CMD_LOAD ((uint16_t)0x0000)
#define | OneNAND_CMD_PROGRAM ((uint16_t)0x0080)
#define | OneNAND_CMD_READ_ID ((uint16_t)0x0090)
#define | OneNAND_CMD_RESET ((uint16_t)0x00F0)
#define | OneNAND_CMD_UNLOCK ((uint16_t)0x0023)
#define | OneNAND_DATA_RAM_0_0_ADD ((uint32_t)0x0400)
OneNand Memory partition description.
#define | OneNAND_DATA_RAM_0_0_REG ((uint32_t)0x0800)
#define | OneNAND_DATA_RAM_0_1_ADD ((uint32_t)0x0600)
#define | OneNAND_DATA_RAM_0_1_REG ((uint32_t)0x0900)
#define | OneNAND_DATA_RAM_0_2_ADD ((uint32_t)0x0800)
#define | OneNAND_DATA_RAM_0_2_REG ((uint32_t)0x0A00)
#define | OneNAND_DATA_RAM_0_3_ADD ((uint32_t)0x0A00)
#define | OneNAND_DATA_RAM_0_3_REG ((uint32_t)0x0B00)
#define | OneNAND_DATA_RAM_1_0_ADD ((uint32_t)0x0C00)
#define | OneNAND_DATA_RAM_1_0_REG ((uint32_t)0x0C00)
#define | OneNAND_DATA_RAM_1_1_ADD ((uint32_t)0x0E00)
#define | OneNAND_DATA_RAM_1_1_REG ((uint32_t)0x0D00)
#define | OneNAND_DATA_RAM_1_2_ADD ((uint32_t)0x1000)
#define | OneNAND_DATA_RAM_1_2_REG ((uint32_t)0x0E00)
#define | OneNAND_DATA_RAM_1_3_ADD ((uint32_t)0x1200)
#define | OneNAND_DATA_RAM_1_3_REG ((uint32_t)0x0F00)
#define | OneNAND_REG_AMOUNTOFBUFFERS ((uint32_t)0x1E00A)
#define | OneNAND_REG_BOOTBUFFERSIZE ((uint32_t)0x1E008)
#define | OneNAND_REG_COMMAND ((uint32_t)0x1E440)
#define | OneNAND_REG_CONTROLSTATUS ((uint32_t)0x1E480)
#define | OneNAND_REG_DATABUFFERSIZE ((uint32_t)0x1E006)
#define | OneNAND_REG_DEVICEID ((uint32_t)0x1E002)
#define | OneNAND_REG_INTERRUPT ((uint32_t)0x1E482)
#define | OneNAND_REG_MANUFACTERID ((uint32_t)0x1E000)
OneNand Register description.
#define | OneNAND_REG_STARTADDRESINT8_T ((uint32_t)0x1E20E)
#define | OneNAND_REG_STARTADDRESS1 ((uint32_t)0x1E200)
#define | OneNAND_REG_STARTADDRESS3 ((uint32_t)0x1E204)
#define | OneNAND_REG_STARTADDRESS4 ((uint32_t)0x1E206)
#define | OneNAND_REG_STARTBLOCKADDRESS ((uint32_t)0x1E498)
#define | OneNAND_REG_STARTBUFFER ((uint32_t)0x1E400)
#define | OneNAND_REG_SYSTEMCONFIGURATION ((uint32_t)0x1E442)
#define | OneNAND_REG_TECHNOLOGY ((uint32_t)0x1E00C)
#define | OneNAND_REG_WRITEPROTECTIONSTATUS ((uint32_t)0x1E49C)

Enumerations

enum | OneNAND_Status { OneNAND_SUCCESS = 0, OneNAND_ONGOING, OneNAND_ERROR, OneNAND_TIMEOUT }

Functions

void | OneNAND_AsynchronousRead (uint16_t *pBuffer, OneNAND_ADDRESS Address, uint32_t NumHalfwordToRead)
Reads a block of data from the OneNAND memory using asynchronous mode.
uint16_t | OneNAND_EraseBlock (uint32_t BlockNumber)
Erases the specified OneNAND memory block (128Kb).
void | OneNAND_Init (void)
Configures the FSMC and GPIOs to interface with the OneNAND memory.
uint16_t | OneNAND_ReadControllerStatus (void)
Reads the OneNAND Controller status.
void | OneNAND_ReadID (OneNAND_IDTypeDef *OneNAND_ID)
Reads OneNAND memory's Manufacturer and Device Code.
uint16_t | OneNAND_ReadStatus (void)
Reads the OneNAND memory Interrupt status.
void | OneNAND_Reset (void)
Resets the OneNAND memory.
void | OneNAND_SynchronousRead (uint16_t *pBuffer, OneNAND_ADDRESS Address, uint32_t NumHalfwordToRead)
Reads a block of data from the OneNAND memory using synchronous mode.
uint16_t | OneNAND_UnlockBlock (uint32_t BlockNumber)
Unlocks the specified OneNAND memory block (128Kb).
uint16_t | OneNAND_WriteBuffer (uint16_t *pBuffer, OneNAND_ADDRESS Address, uint32_t NumHalfwordToWrite)
Writes a Half-word buffer to the OneNAND memory.

Detailed Description

This file contains all the functions prototypes for the stm32100e_eval_fsmc_onenand firmware driver.

Author:
MCD Application Team
Version:
V4.5.0
Date:
07-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm32100e_eval_fsmc_onenand.h.


STM32F10x Standard Peripherals Firmware Library: stm32100e_eval_fsmc_sram.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • STM32100E_EVAL
Defines | Functions

stm32100e_eval_fsmc_sram.c File Reference

This file provides a set of functions needed to drive the IS61WV102416BLL SRAM memory mounted on STM32100E-EVAL board. More...

#include "stm32100e_eval_fsmc_sram.h"

Go to the source code of this file.

Defines

#define | Bank1_SRAM3_ADDR ((uint32_t)0x68000000)
FSMC Bank 1 NOR/SRAM3.

Functions

void | SRAM_Init (void)
Configures the FSMC and GPIOs to interface with the SRAM memory.
void | SRAM_ReadBuffer (uint16_t *pBuffer, uint32_t ReadAddr, uint32_t NumHalfwordToRead)
Reads a block of data from the FSMC SRAM memory.
void | SRAM_WriteBuffer (uint16_t *pBuffer, uint32_t WriteAddr, uint32_t NumHalfwordToWrite)
Writes a Half-word buffer to the FSMC SRAM memory.

Detailed Description

This file provides a set of functions needed to drive the IS61WV102416BLL SRAM memory mounted on STM32100E-EVAL board.

Author:
MCD Application Team
Version:
V4.5.0
Date:
07-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm32100e_eval_fsmc_sram.c.


STM32F10x Standard Peripherals Firmware Library: stm32100e_eval_fsmc_sram.h File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • STM32100E_EVAL
Functions

stm32100e_eval_fsmc_sram.h File Reference

This file contains all the functions prototypes for the stm32100e_eval_fsmc_sram firmware driver. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | SRAM_Init (void)
Configures the FSMC and GPIOs to interface with the SRAM memory.
void | SRAM_ReadBuffer (uint16_t *pBuffer, uint32_t ReadAddr, uint32_t NumHalfwordToRead)
Reads a block of data from the FSMC SRAM memory.
void | SRAM_WriteBuffer (uint16_t *pBuffer, uint32_t WriteAddr, uint32_t NumHalfwordToWrite)
Writes a Half-word buffer to the FSMC SRAM memory.

Detailed Description

This file contains all the functions prototypes for the stm32100e_eval_fsmc_sram firmware driver.

Author:
MCD Application Team
Version:
V4.5.0
Date:
07-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm32100e_eval_fsmc_sram.h.


STM32F10x Standard Peripherals Firmware Library: stm32100e_eval_ioe.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • STM32100E_EVAL
Defines | Functions | Variables

stm32100e_eval_ioe.c File Reference

This file includes the IO Expander driver for STMPE811 IO Expander devices. More...

#include "stm32100e_eval_ioe.h"

Go to the source code of this file.

Defines

#define | TIMEOUT_MAX 0x1000

Functions

static void | delay (__IO uint32_t nCount)
Inserts a delay time.
uint16_t | I2C_ReadDataBuffer (uint8_t DeviceAddr, uint32_t RegisterAddr)
Reads a buffer of 2 bytes from the device registers.
uint8_t | I2C_ReadDeviceRegister (uint8_t DeviceAddr, uint8_t RegisterAddr)
Reads a register of the device through I2C.
uint8_t | I2C_WriteDeviceRegister (uint8_t DeviceAddr, uint8_t RegisterAddr, uint8_t RegisterValue)
Writes a value in a register of the device through I2C.
uint8_t | IOE_ClearGITPending (uint8_t DeviceAddr, uint8_t Global_IT)
Clears the selected Global interrupt pending bit(s)
uint8_t | IOE_ClearIOITPending (uint8_t DeviceAddr, uint8_t IO_IT)
Clears the selected IO interrupt pending bit(s).
uint8_t | IOE_Config (void)
Initializes and Configures the IO_Expanders Functionalities (Touch Screen ..) and configures all STM32100E-EVAL necessary hardware (GPIOs, APB clocks ..).
static void | IOE_DMA_Config (IOE_DMADirection_TypeDef Direction, uint8_t *buffer)
Configure the DMA Peripheral used to handle communication via I2C.
static void | IOE_EXTI_Config (void)
Configures the IO expander Interrupt line and GPIO in EXTI mode.
uint8_t | IOE_FnctCmd (uint8_t DeviceAddr, uint8_t Fct, FunctionalState NewState)
Configures the selcted IO Expander functionalities.
FlagStatus | IOE_GetGITStatus (uint8_t DeviceAddr, uint8_t Global_IT)
Checks the selected Global interrupt source pending bit.
FlagStatus | IOE_GetIOITStatus (uint8_t DeviceAddr, uint8_t IO_IT)
Checks the status of the selected IO interrupt pending bit.
uint8_t | IOE_GITCmd (uint8_t DeviceAddr, FunctionalState NewState)
Enables or disables the Global interrupt.
uint8_t | IOE_GITConfig (uint8_t DeviceAddr, uint8_t Global_IT, FunctionalState NewState)
Configures the selected source to generate or not a global interrupt.
static void | IOE_GPIO_Config (void)
Initializes the GPIO pins used by the IO expander.
static void | IOE_I2C_Config (void)
Configure the I2C Peripheral used to communicate with IO_Expanders.
uint8_t | IOE_IOAFConfig (uint8_t DeviceAddr, uint8_t IO_Pin, FunctionalState NewState)
Configures the selected pin to be in Alternate function or not.
uint8_t | IOE_IOEdgeConfig (uint8_t DeviceAddr, uint8_t IO_Pin, uint8_t Edge)
Configures the Edge for which a transition is detectable for the the selected pin.
uint8_t | IOE_IOITConfig (uint8_t DeviceAddr, uint8_t IO_IT, FunctionalState NewState)
Configures the selected pins to generate an interrupt or not.
uint8_t | IOE_IOPinConfig (uint8_t DeviceAddr, uint8_t IO_Pin, uint8_t Direction)
Configures the selected pin direction (to be an input or an output)
uint8_t | IOE_IsOperational (uint8_t DeviceAddr)
Checks if the selected device is correctly configured and communicates correctly ont the I2C bus.
uint8_t | IOE_ITConfig (uint32_t IOE_ITSRC_Source)
Configures The selected interrupts on the IO Expanders.
uint8_t | IOE_ITOutConfig (uint8_t Polarity, uint8_t Type)
Configures the Interrupt line active state and format (level/edge)
uint16_t | IOE_ReadID (uint8_t DeviceAddr)
Reads the selected device's ID.
uint8_t | IOE_ReadIOPin (uint32_t IO_Pin)
Returns the status of the selected input IO pin.
uint8_t | IOE_Reset (uint8_t DeviceAddr)
Resets the IO Expander by Software (SYS_CTRL1, RESET bit).
uint8_t | IOE_TempSens_Config (void)
Configures and enables the Temperature sensor module.
uint32_t | IOE_TempSens_GetData (void)
Returns the temperature row value (in 16 bit format).
uint8_t | IOE_TS_Config (void)
Configures the touch Screen Controller (Single point detection)
TS_STATE * | IOE_TS_GetState (void)
Returns Status and positions of the Touch screen.
static uint16_t | IOE_TS_Read_X (void)
Return Touch Screen X position value.
static uint16_t | IOE_TS_Read_Y (void)
Return Touch Screen Y position value.
static uint16_t | IOE_TS_Read_Z (void)
Return Touch Screen Z position value.
uint8_t | IOE_WriteIOPin (uint8_t IO_Pin, IOE_BitValue_TypeDef BitVal)
Writes a bit value to an output IO pin.

Variables

uint32_t | IOE_TimeOut = TIMEOUT_MAX
TS_STATE TS_State

Detailed Description

This file includes the IO Expander driver for STMPE811 IO Expander devices.

Author:
MCD Application Team
Version:
V4.5.0
Date:
07-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm32100e_eval_ioe.c.


STM32F10x Standard Peripherals Firmware Library: stm32100e_eval_ioe.h File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • STM32100E_EVAL
Data Structures | Defines | Enumerations | Functions

stm32100e_eval_ioe.h File Reference

This file contains all the functions prototypes for the IO Expander firmware driver. More...

#include "stm32f10x.h"

Go to the source code of this file.

Data Structures

struct | TS_STATE
Touch Screen Information structure. More...

Defines

#define | _delay_ delay
Uncomment the line below to enable verfying each written byte in write operation.
#define | ALL_IT 0xFF
#define | Direction_IN 0x00
IO Pin directions.
#define | Direction_OUT 0x01
#define | EDGE_FALLING 0x01
Edge detection value.
#define | EDGE_RISING 0x02
#define | IO1_IN_ALL_PINS (uint32_t)(IO_Pin_ALL)
IO Exapanders Pins definition.
#define | IO1_OUT_ALL_PINS (uint32_t)(IO_Pin_ALL)
#define | IO_IT_0 0x01
IO Interrupts.
#define | IO_IT_1 0x02
#define | IO_IT_2 0x04
#define | IO_IT_3 0x08
#define | IO_IT_4 0x10
#define | IO_IT_5 0x20
#define | IO_IT_6 0x40
#define | IO_IT_7 0x80
#define | IO_Pin_0 0x01
IO Pins.
#define | IO_Pin_1 0x02
#define | IO_Pin_2 0x04
#define | IO_Pin_3 0x08
#define | IO_Pin_4 0x10
#define | IO_Pin_5 0x20
#define | IO_Pin_6 0x40
#define | IO_Pin_7 0x80
#define | IO_Pin_ALL 0xFF
#define | IOE_1_ADDR 0x82
The 7 bits IO Expanders adresses and chip IDs.
#define | IOE_ADC_FCT 0x01
IO Expander Functionalities definitions.
#define | IOE_DMA DMA1
IOE DMA definitions.
#define | IOE_DMA_CLK RCC_AHBPeriph_DMA1
#define | IOE_DMA_RX_CHANNEL DMA1_Channel5
#define | IOE_DMA_RX_TCFLAG DMA1_FLAG_TC5
#define | IOE_DMA_TX_CHANNEL DMA1_Channel4
#define | IOE_DMA_TX_TCFLAG DMA1_FLAG_TC4
#define | IOE_GIT_ADC 0x40
#define | IOE_GIT_EN 0x01
Global interrupt Enable bit.
#define | IOE_GIT_FE 0x10
#define | IOE_GIT_FF 0x08
#define | IOE_GIT_FOV 0x04
#define | IOE_GIT_FTH 0x02
#define | IOE_GIT_GPIO 0x80
Glaobal Interrupts definitions.
#define | IOE_GIT_TEMP 0x20
#define | IOE_GIT_TOUCH 0x01
#define | IOE_I2C I2C2
I2C port definitions.
#define | IOE_I2C_CLK RCC_APB1Periph_I2C2
#define | IOE_I2C_DR ((uint32_t)0x40005810)
#define | IOE_I2C_SCL_GPIO_CLK RCC_APB2Periph_GPIOB
#define | IOE_I2C_SCL_GPIO_PORT GPIOB
#define | IOE_I2C_SCL_PIN GPIO_Pin_10
#define | IOE_I2C_SDA_GPIO_CLK RCC_APB2Periph_GPIOB
#define | IOE_I2C_SDA_GPIO_PORT GPIOB
#define | IOE_I2C_SDA_PIN GPIO_Pin_11
#define | IOE_I2C_SPEED 300000
#define | IOE_IO_FCT 0x04
#define | IOE_IT_EXTI_IRQn EXTI15_10_IRQn
#define | IOE_IT_EXTI_LINE EXTI_Line12
#define | IOE_IT_EXTI_PIN_SOURCE GPIO_PinSource12
#define | IOE_IT_EXTI_PORT_SOURCE GPIO_PortSourceGPIOA
#define | IOE_IT_GPIO_CLK RCC_APB2Periph_GPIOA
#define | IOE_IT_GPIO_PORT GPIOA
#define | IOE_IT_PIN GPIO_Pin_12
IO Expander Interrupt line on EXTI.
#define | IOE_ITSRC_TEMPSENS 0x08
#define | IOE_ITSRC_TSC 0x01
Interrupt source configuration definitons.
#define | IOE_REG_ADC_CAPT 0x22
#define | IOE_REG_ADC_CTRL1 0x20
#define | IOE_REG_ADC_CTRL2 0x21
#define | IOE_REG_ADC_DATA_CH0 0x30
#define | IOE_REG_ADC_DATA_CH1 0x32
#define | IOE_REG_ADC_DATA_CH2 0x34
#define | IOE_REG_ADC_DATA_CH3 0x36
#define | IOE_REG_ADC_DATA_CH4 0x38
#define | IOE_REG_ADC_DATA_CH5 0x3A
#define | IOE_REG_ADC_DATA_CH6 0x3B
#define | IOE_REG_ADC_DATA_CH7 0x3C
#define | IOE_REG_ADC_INT_EN 0x0E
ADC Registers.
#define | IOE_REG_ADC_INT_STA 0x0F
#define | IOE_REG_CHP_ID 0x00
Identification registers.
#define | IOE_REG_FIFO_SIZE 0x4C
#define | IOE_REG_FIFO_STA 0x4B
#define | IOE_REG_FIFO_TH 0x4A
#define | IOE_REG_GPIO_AF 0x17
#define | IOE_REG_GPIO_CLR_PIN 0x11
#define | IOE_REG_GPIO_DIR 0x13
#define | IOE_REG_GPIO_ED 0x14
#define | IOE_REG_GPIO_FE 0x16
#define | IOE_REG_GPIO_INT_EN 0x0C
#define | IOE_REG_GPIO_INT_STA 0x0D
#define | IOE_REG_GPIO_MP_STA 0x12
#define | IOE_REG_GPIO_RE 0x15
#define | IOE_REG_GPIO_SET_PIN 0x10
GPIO Registers.
#define | IOE_REG_ID_VER 0x02
#define | IOE_REG_INT_CTRL 0x09
Interrupt Control register.
#define | IOE_REG_INT_EN 0x0A
#define | IOE_REG_INT_STA 0x0B
#define | IOE_REG_SPI_CFG 0x08
#define | IOE_REG_SYS_CTRL1 0x03
General Control Registers.
#define | IOE_REG_SYS_CTRL2 0x04
#define | IOE_REG_TEMP_CTRL 0x60
Temperature Sensor registers.
#define | IOE_REG_TEMP_DATA 0x61
#define | IOE_REG_TEMP_TH 0x62
#define | IOE_REG_TSC_CFG 0x41
#define | IOE_REG_TSC_CTRL 0x40
TouchScreen Registers.
#define | IOE_REG_TSC_DATA 0x57
#define | IOE_REG_TSC_DATA_X 0x4D
#define | IOE_REG_TSC_DATA_XYZ 0x52
#define | IOE_REG_TSC_DATA_Y 0x4F
#define | IOE_REG_TSC_DATA_Z 0x51
#define | IOE_REG_TSC_FRACT_XYZ 0x56
#define | IOE_REG_TSC_I_DRIVE 0x58
#define | IOE_REG_TSC_SHIELD 0x59
#define | IOE_REG_WDM_BL_X 0x46
#define | IOE_REG_WDM_BL_Y 0x48
#define | IOE_REG_WDM_TR_X 0x42
#define | IOE_REG_WDM_TR_Y 0x44
#define | IOE_TEMPSENS_FCT 0x08
#define | IOE_TimeoutUserCallback() IOE_TIMEOUT
Timeout user callback function.
#define | IOE_TS_FCT 0x02
#define | IOE_TS_IT (uint8_t)(IO_IT_0 | IO_IT_1 | IO_IT_2)
#define | Polarity_High 0x04
#define | Polarity_Low 0x00
Interrupt Line output parameters.
#define | STMPE811_ID 0x0811
#define | TOUCH_IO_ALL (uint32_t)(IO_Pin_1 | IO_Pin_2 | IO_Pin_3 | IO_Pin_4)
#define | TOUCH_XD IO_Pin_2 /* IO_Exapnader_1 */
#define | TOUCH_XU IO_Pin_4 /* IO_Exapnader_1 */
#define | TOUCH_YD IO_Pin_1 /* IO_Exapnader_1 */
Touch Screen Pins definition.
#define | TOUCH_YU IO_Pin_3 /* IO_Exapnader_1 */
#define | Type_Edge 0x02
#define | Type_Level 0x00

Enumerations

enum | IOE_BitValue_TypeDef { BitReset = 0, BitSet = 1, BitReset = 0, BitSet = 1 }

IO bit values.

More...
enum | IOE_DMADirection_TypeDef { IOE_DMA_TX = 0, IOE_DMA_RX = 1, IOE_DMA_TX = 0, IOE_DMA_RX = 1 }

IOE DMA Direction.

More...
enum IOE_Status_TypDef {
IOE_OK = 0, IOE_FAILURE, IOE_TIMEOUT, PARAM_ERROR,
IOE1_NOT_OPERATIONAL, IOE_OK = 0, IOE_FAILURE, IOE_TIMEOUT,
PARAM_ERROR, IOE1_NOT_OPERATIONAL, IOE2_NOT_OPERATIONAL
}

IO_Expander Error codes.

More...

Functions

uint16_t | I2C_ReadDataBuffer (uint8_t DeviceAddr, uint32_t RegisterAddr)
Reads a buffer of 2 bytes from the device registers.
uint8_t | I2C_ReadDeviceRegister (uint8_t DeviceAddr, uint8_t RegisterAddr)
Reads a register of the device through I2C.
uint8_t | I2C_WriteDeviceRegister (uint8_t DeviceAddr, uint8_t RegisterAddr, uint8_t RegisterValue)
Writes a value in a register of the device through I2C.
uint8_t | IOE_ClearGITPending (uint8_t DeviceAddr, uint8_t IO_IT)
Clears the selected Global interrupt pending bit(s)
uint8_t | IOE_ClearIOITPending (uint8_t DeviceAddr, uint8_t IO_IT)
Clears the selected IO interrupt pending bit(s).
uint8_t | IOE_Config (void)
Configuration and initialization functions.
uint8_t | IOE_FnctCmd (uint8_t DeviceAddr, uint8_t Fct, FunctionalState NewState)
Configures the selcted IO Expander functionalities.
FlagStatus | IOE_GetGITStatus (uint8_t DeviceAddr, uint8_t Global_IT)
Interrupts Mangement functions.
FlagStatus | IOE_GetIOITStatus (uint8_t DeviceAddr, uint8_t IO_IT)
Checks the status of the selected IO interrupt pending bit.
uint8_t | IOE_GITCmd (uint8_t DeviceAddr, FunctionalState NewState)
Enables or disables the Global interrupt.
uint8_t | IOE_GITConfig (uint8_t DeviceAddr, uint8_t Global_IT, FunctionalState NewState)
Configures the selected source to generate or not a global interrupt.
uint8_t | IOE_IOAFConfig (uint8_t DeviceAddr, uint8_t IO_Pin, FunctionalState NewState)
Configures the selected pin to be in Alternate function or not.
uint8_t | IOE_IOEdgeConfig (uint8_t DeviceAddr, uint8_t IO_Pin, uint8_t Edge)
Configures the Edge for which a transition is detectable for the the selected pin.
uint8_t | IOE_IOITConfig (uint8_t DeviceAddr, uint8_t IO_IT, FunctionalState NewState)
Configures the selected pins to generate an interrupt or not.
uint8_t | IOE_IOPinConfig (uint8_t DeviceAddr, uint8_t IO_Pin, uint8_t Direction)
Configures the selected pin direction (to be an input or an output)
uint8_t | IOE_IsOperational (uint8_t DeviceAddr)
IO-Expander Control functions.
uint8_t | IOE_ITConfig (uint32_t IOE_ITSRC_Source)
Configures The selected interrupts on the IO Expanders.
uint8_t | IOE_ITOutConfig (uint8_t Polarity, uint8_t Type)
Configures the Interrupt line active state and format (level/edge)
uint16_t | IOE_ReadID (uint8_t DeviceAddr)
Reads the selected device's ID.
uint8_t | IOE_ReadIOPin (uint32_t IO_Pin)
Returns the status of the selected input IO pin.
uint8_t | IOE_Reset (uint8_t DeviceAddr)
Resets the IO Expander by Software (SYS_CTRL1, RESET bit).
uint8_t | IOE_TempSens_Config (void)
Configures and enables the Temperature sensor module.
uint32_t | IOE_TempSens_GetData (void)
Temperature Sensor functions.
uint8_t | IOE_TS_Config (void)
Low Layer functions.
TS_STATE * | IOE_TS_GetState (void)
Touch Screen controller functions.
uint8_t | IOE_WriteIOPin (uint8_t IO_Pin, IOE_BitValue_TypeDef BitVal)
IO pins control functions.

Detailed Description

This file contains all the functions prototypes for the IO Expander firmware driver.

Author:
MCD Application Team
Version:
V4.5.0
Date:
07-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm32100e_eval_ioe.h.


STM32F10x Standard Peripherals Firmware Library: stm32100e_eval_lcd.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • STM32100E_EVAL
Data Structures | Defines | Functions | Variables

stm32100e_eval_lcd.c File Reference

This file includes the LCD driver for AM-240320L8TNQW00H (LCD_ILI9320), AM240320D5TOQW01H (LCD_ILI9325) and AM-240320LDTNQW00H (LCD_SPFD5408B) Liquid Crystal Display Module of STM32100E-EVAL board. More...

#include "stm32100e_eval_lcd.h"
#include "../Common/fonts.c"

Go to the source code of this file.

Data Structures

struct | LCD_TypeDef

Defines

#define | ABS(X) ((X) > 0 ? (X) : -(X))
#define | LCD ((LCD_TypeDef *) LCD_BASE)
#define | LCD_BASE ((uint32_t)(0x60000000 | 0x0C000000))
#define | MAX_POLY_CORNERS 200
#define | POLY_X(Z) ((int32_t)((Points + Z)->Y))
#define | POLY_Y(Z) ((int32_t)((Points + Z)->X))

Functions

static void | delay (vu32 nCount)
Inserts a delay time.
void | LCD_Clear (uint16_t Color)
Clears the hole LCD.
void | LCD_ClearLine (uint8_t Line)
Clears the selected line.
void | LCD_ClosedPolyLine (pPoint Points, uint16_t PointCount)
Displays a closed polyline (between many points).
void | LCD_ClosedPolyLineRelative (pPoint Points, uint16_t PointCount)
Displays a closed relative polyline (between many points).
void | LCD_CtrlLinesConfig (void)
Configures LCD Control lines (FSMC Pins) in alternate function mode.
void | LCD_DeInit (void)
DeInitializes the LCD.
void | LCD_DisplayChar (uint8_t Line, uint16_t Column, uint8_t Ascii)
Displays one character (16dots width, 24dots height).
void | LCD_DisplayOff (void)
Disables the Display.
void | LCD_DisplayOn (void)
Enables the Display.
void | LCD_DisplayStringLine (uint8_t Line, uint8_t *ptr)
Displays a maximum of 20 char on the LCD.
void | LCD_DrawChar (uint8_t Xpos, uint16_t Ypos, const uint16_t *c)
Draws a character on LCD.
void | LCD_DrawCircle (uint8_t Xpos, uint16_t Ypos, uint16_t Radius)
Displays a circle.
void | LCD_DrawFullCircle (uint16_t Xpos, uint16_t Ypos, uint16_t Radius)
Displays a full circle.
void | LCD_DrawFullRect (uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height)
Displays a full rectangle.
void | LCD_DrawLine (uint8_t Xpos, uint16_t Ypos, uint16_t Length, uint8_t Direction)
Displays a line.
void | LCD_DrawMonoPict (const uint32_t *Pict)
Displays a monocolor picture.
void | LCD_DrawRect (uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width)
Displays a rectangle.
void | LCD_DrawUniLine (uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2)
Displays an uni line (between two points).
void | LCD_FillPolyLine (pPoint Points, uint16_t PointCount)
Displays a full polyline (between many points).
void | LCD_FSMCConfig (void)
Configures the Parallel interface (FSMC) for LCD(Parallel mode)
void | LCD_GetColors (__IO uint16_t *_TextColor, __IO uint16_t *_BackColor)
Gets the LCD Text and Background colors.
sFONT * | LCD_GetFont (void)
Gets the Text Font.
void | LCD_PolyLine (pPoint Points, uint16_t PointCount)
Displays an polyline (between many points).
void | LCD_PolyLineRelative (pPoint Points, uint16_t PointCount)
Displays a relative polyline (between many points).
static void | LCD_PolyLineRelativeClosed (pPoint Points, uint16_t PointCount, uint16_t Closed)
Displays an relative polyline (between many points).
void | LCD_PowerOn (void)
Power on the LCD.
uint16_t | LCD_ReadRAM (void)
Reads the LCD RAM.
uint16_t | LCD_ReadReg (uint8_t LCD_Reg)
Reads the selected LCD Register.
void | LCD_SetBackColor (__IO uint16_t Color)
Sets the Background color.
void | LCD_SetColors (__IO uint16_t _TextColor, __IO uint16_t _BackColor)
Sets the LCD Text and Background colors.
void | LCD_SetCursor (uint8_t Xpos, uint16_t Ypos)
Sets the cursor position.
void | LCD_SetDisplayWindow (uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width)
Sets a display window.
void | LCD_SetFont (sFONT *fonts)
Sets the Text Font.
void | LCD_SetTextColor (__IO uint16_t Color)
Sets the Text color.
void | LCD_WindowModeDisable (void)
Disables LCD Window mode.
void | LCD_WriteBMP (uint32_t BmpAddress)
Displays a bitmap picture loaded in the internal Flash.
void | LCD_WriteRAM (uint16_t RGB_Code)
Writes to the LCD RAM.
void | LCD_WriteRAM_Prepare (void)
Prepare to write to the LCD RAM.
void | LCD_WriteReg (uint8_t LCD_Reg, uint16_t LCD_RegValue)
Writes to the selected LCD register.
static void | PutPixel (int16_t x, int16_t y)
Displays a pixel.
void | STM32100E_LCD_Init (void)
Initializes the LCD.

Variables

static __IO uint16_t | BackColor = 0xFFFF
static sFONT * | LCD_Currentfonts
static __IO uint16_t | TextColor = 0x0000

Detailed Description

This file includes the LCD driver for AM-240320L8TNQW00H (LCD_ILI9320), AM240320D5TOQW01H (LCD_ILI9325) and AM-240320LDTNQW00H (LCD_SPFD5408B) Liquid Crystal Display Module of STM32100E-EVAL board.

Author:
MCD Application Team
Version:
V4.5.0
Date:
07-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm32100e_eval_lcd.c.


STM32F10x Standard Peripherals Firmware Library: stm32100e_eval_lcd.h File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • STM32100E_EVAL
Data Structures | Defines | Typedefs | Functions

stm32100e_eval_lcd.h File Reference

This file contains all the functions prototypes for the stm32100e_eval_lcd firmware driver. More...

#include "stm32f10x.h"
#include "../Common/fonts.h"

Go to the source code of this file.

Data Structures

struct | Point

Defines

#define | _delay_ delay
Uncomment the line below if you want to use user defined Delay function (for precise timing), otherwise default _delay_ function defined within this driver is used (less precise timing).
#define | ASSEMBLE_RGB(R, G, B) ((((R)& 0xF8) << 8) | (((G) & 0xFC) << 3) | (((B) & 0xF8) >> 3))
#define | LCD_COLOR_BLACK 0x0000
#define | LCD_COLOR_BLUE 0x001F
#define | LCD_COLOR_BLUE2 0x051F
#define | LCD_COLOR_CYAN 0x7FFF
#define | LCD_COLOR_GREEN 0x07E0
#define | LCD_COLOR_GREY 0xF7DE
#define | LCD_COLOR_MAGENTA 0xF81F
#define | LCD_COLOR_RED 0xF800
#define | LCD_COLOR_WHITE 0xFFFF
LCD color.
#define | LCD_COLOR_YELLOW 0xFFE0
#define | LCD_DEFAULT_FONT Font16x24
LCD default font.
#define | LCD_DIR_HORIZONTAL 0x0000
LCD Direction.
#define | LCD_DIR_VERTICAL 0x0001
#define | LCD_LINE_0 LINE(0)
LCD Lines depending on the chosen fonts.
#define | LCD_LINE_1 LINE(1)
#define | LCD_LINE_10 LINE(10)
#define | LCD_LINE_11 LINE(11)
#define | LCD_LINE_12 LINE(12)
#define | LCD_LINE_13 LINE(13)
#define | LCD_LINE_14 LINE(14)
#define | LCD_LINE_15 LINE(15)
#define | LCD_LINE_16 LINE(16)
#define | LCD_LINE_17 LINE(17)
#define | LCD_LINE_18 LINE(18)
#define | LCD_LINE_19 LINE(19)
#define | LCD_LINE_2 LINE(2)
#define | LCD_LINE_20 LINE(20)
#define | LCD_LINE_21 LINE(21)
#define | LCD_LINE_22 LINE(22)
#define | LCD_LINE_23 LINE(23)
#define | LCD_LINE_24 LINE(24)
#define | LCD_LINE_25 LINE(25)
#define | LCD_LINE_26 LINE(26)
#define | LCD_LINE_27 LINE(27)
#define | LCD_LINE_28 LINE(28)
#define | LCD_LINE_29 LINE(29)
#define | LCD_LINE_3 LINE(3)
#define | LCD_LINE_4 LINE(4)
#define | LCD_LINE_5 LINE(5)
#define | LCD_LINE_6 LINE(6)
#define | LCD_LINE_7 LINE(7)
#define | LCD_LINE_8 LINE(8)
#define | LCD_LINE_9 LINE(9)
#define | LCD_PIXEL_HEIGHT 0x00F0
#define | LCD_PIXEL_WIDTH 0x0140
LCD Size (Width and Height)
#define | LCD_REG_0 0x00
LCD Registers.
#define | LCD_REG_1 0x01
#define | LCD_REG_10 0x0A
#define | LCD_REG_106 0x6A
#define | LCD_REG_118 0x76
#define | LCD_REG_12 0x0C
#define | LCD_REG_128 0x80
#define | LCD_REG_129 0x81
#define | LCD_REG_13 0x0D
#define | LCD_REG_130 0x82
#define | LCD_REG_131 0x83
#define | LCD_REG_132 0x84
#define | LCD_REG_133 0x85
#define | LCD_REG_134 0x86
#define | LCD_REG_135 0x87
#define | LCD_REG_136 0x88
#define | LCD_REG_137 0x89
#define | LCD_REG_139 0x8B
#define | LCD_REG_14 0x0E
#define | LCD_REG_140 0x8C
#define | LCD_REG_141 0x8D
#define | LCD_REG_143 0x8F
#define | LCD_REG_144 0x90
#define | LCD_REG_145 0x91
#define | LCD_REG_146 0x92
#define | LCD_REG_147 0x93
#define | LCD_REG_148 0x94
#define | LCD_REG_149 0x95
#define | LCD_REG_15 0x0F
#define | LCD_REG_150 0x96
#define | LCD_REG_151 0x97
#define | LCD_REG_152 0x98
#define | LCD_REG_153 0x99
#define | LCD_REG_154 0x9A
#define | LCD_REG_157 0x9D
#define | LCD_REG_16 0x10
#define | LCD_REG_17 0x11
#define | LCD_REG_18 0x12
#define | LCD_REG_19 0x13
#define | LCD_REG_192 0xC0
#define | LCD_REG_193 0xC1
#define | LCD_REG_2 0x02
#define | LCD_REG_20 0x14
#define | LCD_REG_21 0x15
#define | LCD_REG_22 0x16
#define | LCD_REG_229 0xE5
#define | LCD_REG_23 0x17
#define | LCD_REG_24 0x18
#define | LCD_REG_25 0x19
#define | LCD_REG_26 0x1A
#define | LCD_REG_27 0x1B
#define | LCD_REG_28 0x1C
#define | LCD_REG_29 0x1D
#define | LCD_REG_3 0x03
#define | LCD_REG_30 0x1E
#define | LCD_REG_31 0x1F
#define | LCD_REG_32 0x20
#define | LCD_REG_33 0x21
#define | LCD_REG_34 0x22
#define | LCD_REG_36 0x24
#define | LCD_REG_37 0x25
#define | LCD_REG_4 0x04
#define | LCD_REG_40 0x28
#define | LCD_REG_41 0x29
#define | LCD_REG_43 0x2B
#define | LCD_REG_45 0x2D
#define | LCD_REG_48 0x30
#define | LCD_REG_49 0x31
#define | LCD_REG_5 0x05
#define | LCD_REG_50 0x32
#define | LCD_REG_51 0x33
#define | LCD_REG_52 0x34
#define | LCD_REG_53 0x35
#define | LCD_REG_54 0x36
#define | LCD_REG_55 0x37
#define | LCD_REG_56 0x38
#define | LCD_REG_57 0x39
#define | LCD_REG_58 0x3A
#define | LCD_REG_59 0x3B
#define | LCD_REG_6 0x06
#define | LCD_REG_60 0x3C
#define | LCD_REG_61 0x3D
#define | LCD_REG_62 0x3E
#define | LCD_REG_63 0x3F
#define | LCD_REG_64 0x40
#define | LCD_REG_65 0x41
#define | LCD_REG_66 0x42
#define | LCD_REG_67 0x43
#define | LCD_REG_68 0x44
#define | LCD_REG_69 0x45
#define | LCD_REG_7 0x07
#define | LCD_REG_70 0x46
#define | LCD_REG_71 0x47
#define | LCD_REG_72 0x48
#define | LCD_REG_73 0x49
#define | LCD_REG_74 0x4A
#define | LCD_REG_75 0x4B
#define | LCD_REG_76 0x4C
#define | LCD_REG_77 0x4D
#define | LCD_REG_78 0x4E
#define | LCD_REG_79 0x4F
#define | LCD_REG_8 0x08
#define | LCD_REG_80 0x50
#define | LCD_REG_81 0x51
#define | LCD_REG_82 0x52
#define | LCD_REG_83 0x53
#define | LCD_REG_9 0x09
#define | LCD_REG_96 0x60
#define | LCD_REG_97 0x61

Typedefs

typedef struct Point * | pPoint

Functions

void | LCD_Clear (uint16_t Color)
Clears the hole LCD.
void | LCD_ClearLine (uint8_t Line)
Clears the selected line.
void | LCD_ClosedPolyLine (pPoint Points, uint16_t PointCount)
Displays a closed polyline (between many points).
void | LCD_ClosedPolyLineRelative (pPoint Points, uint16_t PointCount)
Displays a closed relative polyline (between many points).
void | LCD_CtrlLinesConfig (void)
Configures LCD control lines in Output Push-Pull mode.
void | LCD_DeInit (void)
DeInitializes the LCD.
void | LCD_DisplayChar (uint8_t Line, uint16_t Column, uint8_t Ascii)
Displays one character (16dots width, 24dots height).
void | LCD_DisplayOff (void)
Disables the Display.
void | LCD_DisplayOn (void)
Enables the Display.
void | LCD_DisplayStringLine (uint8_t Line, uint8_t *ptr)
Displays a maximum of 20 char on the LCD.
void | LCD_DrawChar (uint8_t Xpos, uint16_t Ypos, const uint16_t *c)
Draws a character on LCD.
void | LCD_DrawCircle (uint8_t Xpos, uint16_t Ypos, uint16_t Radius)
Displays a circle.
void | LCD_DrawFullCircle (uint16_t Xpos, uint16_t Ypos, uint16_t Radius)
Displays a full circle.
void | LCD_DrawFullRect (uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height)
Displays a full rectangle.
void | LCD_DrawLine (uint8_t Xpos, uint16_t Ypos, uint16_t Length, uint8_t Direction)
Displays a line.
void | LCD_DrawMonoPict (const uint32_t *Pict)
Displays a monocolor picture.
void | LCD_DrawRect (uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width)
Displays a rectangle.
void | LCD_DrawUniLine (uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2)
Displays an uni line (between two points).
void | LCD_FillPolyLine (pPoint Points, uint16_t PointCount)
Displays a full polyline (between many points).
void | LCD_FSMCConfig (void)
Configures the Parallel interface (FSMC) for LCD(Parallel mode)
void | LCD_GetColors (__IO uint16_t *_TextColor, __IO uint16_t *_BackColor)
Gets the LCD Text and Background colors.
sFONT * | LCD_GetFont (void)
Gets the Text Font.
void | LCD_PolyLine (pPoint Points, uint16_t PointCount)
Displays an polyline (between many points).
void | LCD_PolyLineRelative (pPoint Points, uint16_t PointCount)
Displays a relative polyline (between many points).
void | LCD_PowerOn (void)
Power on the LCD.
uint16_t | LCD_ReadRAM (void)
Reads the LCD RAM.
uint16_t | LCD_ReadReg (uint8_t LCD_Reg)
Reads the selected LCD Register.
void | LCD_SetBackColor (__IO uint16_t Color)
Sets the Background color.
void | LCD_SetColors (__IO uint16_t _TextColor, __IO uint16_t _BackColor)
Sets the LCD Text and Background colors.
void | LCD_SetCursor (uint8_t Xpos, uint16_t Ypos)
Sets the cursor position.
void | LCD_SetDisplayWindow (uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width)
Sets a display window.
void | LCD_SetFont (sFONT *fonts)
Sets the Text Font.
void | LCD_SetTextColor (__IO uint16_t Color)
Sets the Text color.
void | LCD_WindowModeDisable (void)
Disables LCD Window mode.
void | LCD_WriteBMP (uint32_t BmpAddress)
Displays a bitmap picture loaded in the internal Flash.
void | LCD_WriteRAM (uint16_t RGB_Code)
Writes to the LCD RAM.
void | LCD_WriteRAM_Prepare (void)
Prepare to write to the LCD RAM.
void | LCD_WriteReg (uint8_t LCD_Reg, uint16_t LCD_RegValue)
Writes to the selected LCD register.
void | STM32100E_LCD_Init (void)
Initializes the LCD.

Detailed Description

This file contains all the functions prototypes for the stm32100e_eval_lcd firmware driver.

Author:
MCD Application Team
Version:
V4.5.0
Date:
07-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm32100e_eval_lcd.h.


STM32F10x Standard Peripherals Firmware Library: stm3210b_eval.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • STM3210B_EVAL
Functions | Variables

stm3210b_eval.c File Reference

This file provides

  • set of firmware functions to manage Leds, push-button and COM ports
  • low level initialization functions for SD card (on SPI), SPI serial flash (sFLASH) and temperature sensor (LM75) available on STM3210B-EVAL evaluation board from STMicroelectronics.
More...

#include "stm3210b_eval.h"

Go to the source code of this file.

Functions

void | LM75_LowLevel_DeInit (void)
DeInitializes the LM75_I2C.
void | LM75_LowLevel_Init (void)
Initializes the LM75_I2C.
void | SD_LowLevel_DeInit (void)
DeInitializes the SD/SD communication.
void | SD_LowLevel_Init (void)
Initializes the SD_SPI and CS pins.
void | sFLASH_LowLevel_DeInit (void)
DeInitializes the peripherals used by the SPI FLASH driver.
void | sFLASH_LowLevel_Init (void)
Initializes the peripherals used by the SPI FLASH driver.
void | STM_EVAL_COMInit (COM_TypeDef COM, USART_InitTypeDef *USART_InitStruct)
Configures COM port.
void | STM_EVAL_LEDInit (Led_TypeDef Led)
Configures LED GPIO.
void | STM_EVAL_LEDOff (Led_TypeDef Led)
Turns selected LED Off.
void | STM_EVAL_LEDOn (Led_TypeDef Led)
Turns selected LED On.
void | STM_EVAL_LEDToggle (Led_TypeDef Led)
Toggles the selected LED.
uint32_t | STM_EVAL_PBGetState (Button_TypeDef Button)
Returns the selected Button state.
void | STM_EVAL_PBInit (Button_TypeDef Button, ButtonMode_TypeDef Button_Mode)
Configures Button GPIO and EXTI Line.

Variables

const uint32_t | BUTTON_CLK [BUTTONn]
const uint16_t | BUTTON_EXTI_LINE [BUTTONn]
const uint16_t | BUTTON_IRQn [BUTTONn]
const uint16_t | BUTTON_PIN [BUTTONn]
const uint16_t | BUTTON_PIN_SOURCE [BUTTONn]
GPIO_TypeDef * | BUTTON_PORT [BUTTONn]
const uint16_t | BUTTON_PORT_SOURCE [BUTTONn]
const uint16_t | COM_RX_PIN [COMn] = {EVAL_COM1_RX_PIN, EVAL_COM2_RX_PIN}
GPIO_TypeDef * | COM_RX_PORT [COMn] = {EVAL_COM1_RX_GPIO_PORT, EVAL_COM2_RX_GPIO_PORT}
const uint32_t | COM_RX_PORT_CLK [COMn] = {EVAL_COM1_RX_GPIO_CLK, EVAL_COM2_RX_GPIO_CLK}
const uint16_t | COM_TX_PIN [COMn] = {EVAL_COM1_TX_PIN, EVAL_COM2_TX_PIN}
GPIO_TypeDef * | COM_TX_PORT [COMn] = {EVAL_COM1_TX_GPIO_PORT, EVAL_COM2_TX_GPIO_PORT}
const uint32_t | COM_TX_PORT_CLK [COMn] = {EVAL_COM1_TX_GPIO_CLK, EVAL_COM2_TX_GPIO_CLK}
USART_TypeDef * | COM_USART [COMn] = {EVAL_COM1, EVAL_COM2}
const uint32_t | COM_USART_CLK [COMn] = {EVAL_COM1_CLK, EVAL_COM2_CLK}
const uint32_t | GPIO_CLK [LEDn]
const uint16_t | GPIO_PIN [LEDn]
GPIO_TypeDef * | GPIO_PORT [LEDn]

Detailed Description

This file provides

  • set of firmware functions to manage Leds, push-button and COM ports
  • low level initialization functions for SD card (on SPI), SPI serial flash (sFLASH) and temperature sensor (LM75) available on STM3210B-EVAL evaluation board from STMicroelectronics.
Author:
MCD Application Team
Version:
V4.5.0
Date:
07-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm3210b_eval.c.


STM32F10x Standard Peripherals Firmware Library: stm3210b_eval.h File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • STM3210B_EVAL
Defines | Functions

stm3210b_eval.h File Reference

This file contains definitions for STM3210B_EVAL's Leds, push-buttons COM ports, SD Card (on SPI), sFLASH (on SPI) and Temperature sensor LM75 (on I2C) hardware resources. More...

#include "stm32_eval.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_i2c.h"

Go to the source code of this file.

Defines

#define | BUTTONn 8
#define | COMn 2
#define | DOWN_BUTTON_EXTI_IRQn EXTI15_10_IRQn
#define | DOWN_BUTTON_EXTI_LINE EXTI_Line14
#define | DOWN_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource14
#define | DOWN_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOD
#define | DOWN_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOD
#define | DOWN_BUTTON_GPIO_PORT GPIOD
#define | DOWN_BUTTON_PIN GPIO_Pin_14
Joystick Down push-button.
#define | EVAL_COM1 USART1
Definition for COM port1, connected to USART1.
#define | EVAL_COM1_CLK RCC_APB2Periph_USART1
#define | EVAL_COM1_IRQn USART1_IRQn
#define | EVAL_COM1_RX_GPIO_CLK RCC_APB2Periph_GPIOA
#define | EVAL_COM1_RX_GPIO_PORT GPIOA
#define | EVAL_COM1_RX_PIN GPIO_Pin_10
#define | EVAL_COM1_TX_GPIO_CLK RCC_APB2Periph_GPIOA
#define | EVAL_COM1_TX_GPIO_PORT GPIOA
#define | EVAL_COM1_TX_PIN GPIO_Pin_9
#define | EVAL_COM2 USART2
Definition for COM port2, connected to USART2 (USART2 pins remapped on GPIOD)
#define | EVAL_COM2_CLK RCC_APB1Periph_USART2
#define | EVAL_COM2_IRQn USART2_IRQn
#define | EVAL_COM2_RX_GPIO_CLK RCC_APB2Periph_GPIOD
#define | EVAL_COM2_RX_GPIO_PORT GPIOD
#define | EVAL_COM2_RX_PIN GPIO_Pin_6
#define | EVAL_COM2_TX_GPIO_CLK RCC_APB2Periph_GPIOD
#define | EVAL_COM2_TX_GPIO_PORT GPIOD
#define | EVAL_COM2_TX_PIN GPIO_Pin_5
#define | KEY_BUTTON_EXTI_IRQn EXTI9_5_IRQn
#define | KEY_BUTTON_EXTI_LINE EXTI_Line9
#define | KEY_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource9
#define | KEY_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOB
#define | KEY_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOB
#define | KEY_BUTTON_GPIO_PORT GPIOB
#define | KEY_BUTTON_PIN GPIO_Pin_9
Key push-button.
#define | LED1_GPIO_CLK RCC_APB2Periph_GPIOC
#define | LED1_GPIO_PORT GPIOC
#define | LED1_PIN GPIO_Pin_6
#define | LED2_GPIO_CLK RCC_APB2Periph_GPIOC
#define | LED2_GPIO_PORT GPIOC
#define | LED2_PIN GPIO_Pin_7
#define | LED3_GPIO_CLK RCC_APB2Periph_GPIOC
#define | LED3_GPIO_PORT GPIOC
#define | LED3_PIN GPIO_Pin_8
#define | LED4_GPIO_CLK RCC_APB2Periph_GPIOC
#define | LED4_GPIO_PORT GPIOC
#define | LED4_PIN GPIO_Pin_9
#define | LEDn 4
#define | LEFT_BUTTON_EXTI_IRQn EXTI1_IRQn
#define | LEFT_BUTTON_EXTI_LINE EXTI_Line1
#define | LEFT_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource1
#define | LEFT_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOE
#define | LEFT_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOE
#define | LEFT_BUTTON_GPIO_PORT GPIOE
#define | LEFT_BUTTON_PIN GPIO_Pin_1
Joystick Left push-button.
#define | LM75_DMA_CLK RCC_AHBPeriph_DMA1
#define | LM75_DMA_RX_CHANNEL DMA1_Channel7
#define | LM75_DMA_RX_TCFLAG DMA1_FLAG_TC7
#define | LM75_DMA_TX_CHANNEL DMA1_Channel6
#define | LM75_DMA_TX_TCFLAG DMA1_FLAG_TC6
#define | LM75_I2C I2C1
LM75 Temperature Sensor I2C Interface pins.
#define | LM75_I2C_CLK RCC_APB1Periph_I2C1
#define | LM75_I2C_DR ((uint32_t)0x40005410)
#define | LM75_I2C_SCL_GPIO_CLK RCC_APB2Periph_GPIOB
#define | LM75_I2C_SCL_GPIO_PORT GPIOB
#define | LM75_I2C_SCL_PIN GPIO_Pin_6
#define | LM75_I2C_SDA_GPIO_CLK RCC_APB2Periph_GPIOB
#define | LM75_I2C_SDA_GPIO_PORT GPIOB
#define | LM75_I2C_SDA_PIN GPIO_Pin_7
#define | LM75_I2C_SMBUSALERT_GPIO_CLK RCC_APB2Periph_GPIOB
#define | LM75_I2C_SMBUSALERT_GPIO_PORT GPIOB
#define | LM75_I2C_SMBUSALERT_PIN GPIO_Pin_5
#define | RIGHT_BUTTON_EXTI_IRQn EXTI0_IRQn
#define | RIGHT_BUTTON_EXTI_LINE EXTI_Line0
#define | RIGHT_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource0
#define | RIGHT_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOE
#define | RIGHT_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOE
#define | RIGHT_BUTTON_GPIO_PORT GPIOE
#define | RIGHT_BUTTON_PIN GPIO_Pin_0
Joystick Right push-button.
#define | SD_CS_GPIO_CLK RCC_APB2Periph_GPIOC
#define | SD_CS_GPIO_PORT GPIOC
#define | SD_CS_PIN GPIO_Pin_12
#define | SD_DETECT_GPIO_CLK RCC_APB2Periph_GPIOE
#define | SD_DETECT_GPIO_PORT GPIOE
#define | SD_DETECT_PIN GPIO_Pin_7
#define | SD_SPI SPI1
SD SPI Interface pins.
#define | SD_SPI_CLK RCC_APB2Periph_SPI1
#define | SD_SPI_MISO_GPIO_CLK RCC_APB2Periph_GPIOA
#define | SD_SPI_MISO_GPIO_PORT GPIOA
#define | SD_SPI_MISO_PIN GPIO_Pin_6
#define | SD_SPI_MOSI_GPIO_CLK RCC_APB2Periph_GPIOA
#define | SD_SPI_MOSI_GPIO_PORT GPIOA
#define | SD_SPI_MOSI_PIN GPIO_Pin_7
#define | SD_SPI_SCK_GPIO_CLK RCC_APB2Periph_GPIOA
#define | SD_SPI_SCK_GPIO_PORT GPIOA
#define | SD_SPI_SCK_PIN GPIO_Pin_5
#define | SEL_BUTTON_EXTI_IRQn EXTI15_10_IRQn
#define | SEL_BUTTON_EXTI_LINE EXTI_Line12
#define | SEL_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource12
#define | SEL_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOD
#define | SEL_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOD
#define | SEL_BUTTON_GPIO_PORT GPIOD
#define | SEL_BUTTON_PIN GPIO_Pin_12
Joystick Sel push-button.
#define | sFLASH_CS_GPIO_CLK RCC_APB2Periph_GPIOA
#define | sFLASH_CS_GPIO_PORT GPIOA
#define | sFLASH_CS_PIN GPIO_Pin_4
#define | sFLASH_SPI SPI1
M25P FLASH SPI Interface pins.
#define | sFLASH_SPI_CLK RCC_APB2Periph_SPI1
#define | sFLASH_SPI_MISO_GPIO_CLK RCC_APB2Periph_GPIOA
#define | sFLASH_SPI_MISO_GPIO_PORT GPIOA
#define | sFLASH_SPI_MISO_PIN GPIO_Pin_6
#define | sFLASH_SPI_MOSI_GPIO_CLK RCC_APB2Periph_GPIOA
#define | sFLASH_SPI_MOSI_GPIO_PORT GPIOA
#define | sFLASH_SPI_MOSI_PIN GPIO_Pin_7
#define | sFLASH_SPI_SCK_GPIO_CLK RCC_APB2Periph_GPIOA
#define | sFLASH_SPI_SCK_GPIO_PORT GPIOA
#define | sFLASH_SPI_SCK_PIN GPIO_Pin_5
#define | TAMPER_BUTTON_EXTI_IRQn EXTI15_10_IRQn
#define | TAMPER_BUTTON_EXTI_LINE EXTI_Line13
#define | TAMPER_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource13
#define | TAMPER_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOC
#define | TAMPER_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOC
#define | TAMPER_BUTTON_GPIO_PORT GPIOC
#define | TAMPER_BUTTON_PIN GPIO_Pin_13
Tamper push-button.
#define | UP_BUTTON_EXTI_IRQn EXTI9_5_IRQn
#define | UP_BUTTON_EXTI_LINE EXTI_Line8
#define | UP_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource8
#define | UP_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOD
#define | UP_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOD
#define | UP_BUTTON_GPIO_PORT GPIOD
#define | UP_BUTTON_PIN GPIO_Pin_8
Joystick Up push-button.
#define | WAKEUP_BUTTON_EXTI_IRQn EXTI0_IRQn
#define | WAKEUP_BUTTON_EXTI_LINE EXTI_Line0
#define | WAKEUP_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource0
#define | WAKEUP_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOA
#define | WAKEUP_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOA
#define | WAKEUP_BUTTON_GPIO_PORT GPIOA
#define | WAKEUP_BUTTON_PIN GPIO_Pin_0
Wakeup push-button.

Functions

void | LM75_LowLevel_DeInit (void)
DeInitializes the LM75_I2C.
void | LM75_LowLevel_Init (void)
Initializes the LM75_I2C.
void | SD_LowLevel_DeInit (void)
DeInitializes the SD/SD communication.
void | SD_LowLevel_Init (void)
Initializes the SD_SPI and CS pins.
void | sFLASH_LowLevel_DeInit (void)
DeInitializes the peripherals used by the SPI FLASH driver.
void | sFLASH_LowLevel_Init (void)
Initializes the peripherals used by the SPI FLASH driver.
void | STM_EVAL_COMInit (COM_TypeDef COM, USART_InitTypeDef *USART_InitStruct)
Configures COM port.
void | STM_EVAL_LEDInit (Led_TypeDef Led)
Configures LED GPIO.
void | STM_EVAL_LEDOff (Led_TypeDef Led)
Turns selected LED Off.
void | STM_EVAL_LEDOn (Led_TypeDef Led)
Turns selected LED On.
void | STM_EVAL_LEDToggle (Led_TypeDef Led)
Toggles the selected LED.
uint32_t | STM_EVAL_PBGetState (Button_TypeDef Button)
Returns the selected Button state.
void | STM_EVAL_PBInit (Button_TypeDef Button, ButtonMode_TypeDef Button_Mode)
Configures Button GPIO and EXTI Line.

Detailed Description

This file contains definitions for STM3210B_EVAL's Leds, push-buttons COM ports, SD Card (on SPI), sFLASH (on SPI) and Temperature sensor LM75 (on I2C) hardware resources.

Author:
MCD Application Team
Version:
V4.5.0
Date:
07-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm3210b_eval.h.


STM32F10x Standard Peripherals Firmware Library: stm3210b_eval_lcd.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • STM3210B_EVAL
Defines | Functions | Variables

stm3210b_eval_lcd.c File Reference

This file includes the LCD driver for AM-240320LTNQW00H (LCD_HX8312), AM-240320L8TNQW00H (LCD_ILI9320), AM-240320LDTNQW00H (LCD_SPFD5408B) Liquid Crystal Display Module of STM3210B-EVAL board. More...

#include "stm3210b_eval_lcd.h"
#include "../Common/fonts.c"

Go to the source code of this file.

Defines

#define | ABS(X) ((X) > 0 ? (X) : -(X))
#define | LCD_HX8312 0x8312
#define | LCD_ILI9320 0x9320
#define | LCD_READ_REG 0x03
#define | LCD_SPFD5408 0x5408
#define | LCD_WRITE_REG 0x02
#define | MAX_POLY_CORNERS 200
#define | POLY_X(Z) ((int32_t)((Points + Z)->Y))
#define | POLY_Y(Z) ((int32_t)((Points + Z)->X))
#define | READ_STATUS 0x01
#define | SET_INDEX 0x00
#define | START_BYTE 0x70

Functions

static void | delay (vu32 nCount)
Inserts a delay time.
void | LCD_Clear (uint16_t Color)
Clears the hole LCD.
void | LCD_ClearLine (uint8_t Line)
Clears the selected line.
void | LCD_ClosedPolyLine (pPoint Points, uint16_t PointCount)
Displays a closed polyline (between many points).
void | LCD_ClosedPolyLineRelative (pPoint Points, uint16_t PointCount)
Displays a closed relative polyline (between many points).
void | LCD_CtrlLinesConfig (void)
Configures LCD control lines in Output Push-Pull mode.
void | LCD_CtrlLinesWrite (GPIO_TypeDef *GPIOx, uint16_t CtrlPins, BitAction BitVal)
Sets or reset LCD control lines.
void | LCD_DeInit (void)
DeInitializes the LCD.
void | LCD_DisplayChar (uint8_t Line, uint16_t Column, uint8_t Ascii)
Displays one character (16dots width, 24dots height).
void | LCD_DisplayOff (void)
Disables the Display.
void | LCD_DisplayOn (void)
Enables the Display.
void | LCD_DisplayStringLine (uint8_t Line, uint8_t *ptr)
Displays a maximum of 20 char on the LCD.
void | LCD_DrawChar (uint8_t Xpos, uint16_t Ypos, const uint16_t *c)
Draws a character on LCD.
void | LCD_DrawCircle (uint8_t Xpos, uint16_t Ypos, uint16_t Radius)
Displays a circle.
void | LCD_DrawFullCircle (uint16_t Xpos, uint16_t Ypos, uint16_t Radius)
Displays a full circle.
void | LCD_DrawFullRect (uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height)
Displays a full rectangle.
void | LCD_DrawLine (uint8_t Xpos, uint16_t Ypos, uint16_t Length, uint8_t Direction)
Displays a line.
void | LCD_DrawMonoPict (const uint32_t *Pict)
Displays a monocolor picture.
void | LCD_DrawRect (uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width)
Displays a rectangle.
void | LCD_DrawUniLine (uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2)
Displays an uni line (between two points).
void | LCD_FillPolyLine (pPoint Points, uint16_t PointCount)
Displays a full polyline (between many points).
void | LCD_GetColors (__IO uint16_t *_TextColor, __IO uint16_t *_BackColor)
Gets the LCD Text and Background colors.
sFONT * | LCD_GetFont (void)
Gets the Text Font.
void | LCD_nCS_StartByte (uint8_t Start_Byte)
Reset LCD control line(/CS) and Send Start-Byte.
void | LCD_PolyLine (pPoint Points, uint16_t PointCount)
Displays an polyline (between many points).
void | LCD_PolyLineRelative (pPoint Points, uint16_t PointCount)
Displays a relative polyline (between many points).
static void | LCD_PolyLineRelativeClosed (pPoint Points, uint16_t PointCount, uint16_t Closed)
Displays an relative polyline (between many points).
void | LCD_PowerOn (void)
Power on the LCD.
uint16_t | LCD_ReadReg (uint8_t LCD_Reg)
Reads the selected LCD Register.
void | LCD_SetBackColor (__IO uint16_t Color)
Sets the Background color.
void | LCD_SetColors (__IO uint16_t _TextColor, __IO uint16_t _BackColor)
Sets the LCD Text and Background colors.
void | LCD_SetCursor (uint8_t Xpos, uint16_t Ypos)
Sets the cursor position.
void | LCD_SetDisplayWindow (uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width)
Sets a display window.
void | LCD_SetFont (sFONT *fonts)
Sets the Text Font.
void | LCD_SetTextColor (__IO uint16_t Color)
Sets the Text color.
void | LCD_Setup (void)
Setups the LCD.
void | LCD_SPIConfig (void)
Configures the LCD_SPI interface.
void | LCD_WindowModeDisable (void)
Disables LCD Window mode.
void | LCD_WriteRAM (uint16_t RGB_Code)
Writes to the LCD RAM.
void | LCD_WriteRAM_Prepare (void)
Prepare to write to the LCD RAM.
void | LCD_WriteRAMWord (uint16_t RGB_Code)
Writes 1 word to the LCD RAM.
void | LCD_WriteReg (uint8_t LCD_Reg, uint16_t LCD_RegValue)
Writes to the selected LCD register.
static void | LCD_WriteRegHX8312 (uint8_t LCD_Reg, uint8_t LCD_RegValue)
Writes to the selected LCD HX8312 register.
static void | LCD_WriteRegILI9320 (uint8_t LCD_Reg, uint16_t LCD_RegValue)
Writes to the selected LCD ILI9320 register.
void | LCD_WriteRegIndex (uint8_t LCD_Reg)
Writes index to select the LCD register.
static void | PutPixel (int16_t x, int16_t y)
Displays a pixel.
void | STM3210B_LCD_Init (void)
Initializes the LCD.

Variables

static __IO uint16_t | BackColor = 0xFFFF
static sFONT * | LCD_Currentfonts
static __IO uint32_t | LCDType = LCD_ILI9320
static __IO uint16_t | TextColor = 0x0000

Detailed Description

This file includes the LCD driver for AM-240320LTNQW00H (LCD_HX8312), AM-240320L8TNQW00H (LCD_ILI9320), AM-240320LDTNQW00H (LCD_SPFD5408B) Liquid Crystal Display Module of STM3210B-EVAL board.

Author:
MCD Application Team
Version:
V4.5.0
Date:
07-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm3210b_eval_lcd.c.


STM32F10x Standard Peripherals Firmware Library: stm3210b_eval_lcd.h File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • STM3210B_EVAL
Data Structures | Defines | Typedefs | Functions

stm3210b_eval_lcd.h File Reference

This file contains all the functions prototypes for the stm3210b_eval_lcd firmware driver. More...

#include "stm32f10x.h"
#include "../Common/fonts.h"

Go to the source code of this file.

Data Structures

struct | Point

Defines

#define | _delay_ delay
Uncomment the line below if you want to use LCD_DrawBMP function to display a bitmap picture on the LCD.
#define | ASSEMBLE_RGB(R, G, B) ((((R)& 0xF8) << 8) | (((G) & 0xFC) << 3) | (((B) & 0xF8) >> 3))
#define | LCD_COLOR_BLACK 0x0000
#define | LCD_COLOR_BLUE 0x001F
#define | LCD_COLOR_BLUE2 0x051F
#define | LCD_COLOR_CYAN 0x7FFF
#define | LCD_COLOR_GREEN 0x07E0
#define | LCD_COLOR_GREY 0xF7DE
#define | LCD_COLOR_MAGENTA 0xF81F
#define | LCD_COLOR_RED 0xF800
#define | LCD_COLOR_WHITE 0xFFFF
LCD color.
#define | LCD_COLOR_YELLOW 0xFFE0
#define | LCD_DEFAULT_FONT Font16x24
LCD default font.
#define | LCD_DIR_HORIZONTAL 0x0000
LCD Direction.
#define | LCD_DIR_VERTICAL 0x0001
#define | LCD_LINE_0 LINE(0)
LCD Lines depending on the chosen fonts.
#define | LCD_LINE_1 LINE(1)
#define | LCD_LINE_10 LINE(10)
#define | LCD_LINE_11 LINE(11)
#define | LCD_LINE_12 LINE(12)
#define | LCD_LINE_13 LINE(13)
#define | LCD_LINE_14 LINE(14)
#define | LCD_LINE_15 LINE(15)
#define | LCD_LINE_16 LINE(16)
#define | LCD_LINE_17 LINE(17)
#define | LCD_LINE_18 LINE(18)
#define | LCD_LINE_19 LINE(19)
#define | LCD_LINE_2 LINE(2)
#define | LCD_LINE_20 LINE(20)
#define | LCD_LINE_21 LINE(21)
#define | LCD_LINE_22 LINE(22)
#define | LCD_LINE_23 LINE(23)
#define | LCD_LINE_24 LINE(24)
#define | LCD_LINE_25 LINE(25)
#define | LCD_LINE_26 LINE(26)
#define | LCD_LINE_27 LINE(27)
#define | LCD_LINE_28 LINE(28)
#define | LCD_LINE_29 LINE(29)
#define | LCD_LINE_3 LINE(3)
#define | LCD_LINE_4 LINE(4)
#define | LCD_LINE_5 LINE(5)
#define | LCD_LINE_6 LINE(6)
#define | LCD_LINE_7 LINE(7)
#define | LCD_LINE_8 LINE(8)
#define | LCD_LINE_9 LINE(9)
#define | LCD_NCS_GPIO_CLK RCC_APB2Periph_GPIOB
#define | LCD_NCS_GPIO_PORT GPIOB
#define | LCD_NCS_PIN GPIO_Pin_2
LCD Control pins.
#define | LCD_NWR_GPIO_CLK RCC_APB2Periph_GPIOD
#define | LCD_NWR_GPIO_PORT GPIOD
#define | LCD_NWR_PIN GPIO_Pin_15
#define | LCD_PIXEL_HEIGHT 0x00F0
#define | LCD_PIXEL_WIDTH 0x0140
LCD Size (Width and Height)
#define | LCD_REG_0 0x00
LCD Registers.
#define | LCD_REG_1 0x01
#define | LCD_REG_10 0x0A
#define | LCD_REG_106 0x6A
#define | LCD_REG_118 0x76
#define | LCD_REG_12 0x0C
#define | LCD_REG_128 0x80
#define | LCD_REG_129 0x81
#define | LCD_REG_13 0x0D
#define | LCD_REG_130 0x82
#define | LCD_REG_131 0x83
#define | LCD_REG_132 0x84
#define | LCD_REG_133 0x85
#define | LCD_REG_134 0x86
#define | LCD_REG_135 0x87
#define | LCD_REG_136 0x88
#define | LCD_REG_137 0x89
#define | LCD_REG_139 0x8B
#define | LCD_REG_14 0x0E
#define | LCD_REG_140 0x8C
#define | LCD_REG_141 0x8D
#define | LCD_REG_143 0x8F
#define | LCD_REG_144 0x90
#define | LCD_REG_145 0x91
#define | LCD_REG_146 0x92
#define | LCD_REG_147 0x93
#define | LCD_REG_148 0x94
#define | LCD_REG_149 0x95
#define | LCD_REG_15 0x0F
#define | LCD_REG_150 0x96
#define | LCD_REG_151 0x97
#define | LCD_REG_152 0x98
#define | LCD_REG_153 0x99
#define | LCD_REG_154 0x9A
#define | LCD_REG_157 0x9D
#define | LCD_REG_16 0x10
#define | LCD_REG_17 0x11
#define | LCD_REG_18 0x12
#define | LCD_REG_19 0x13
#define | LCD_REG_192 0xC0
#define | LCD_REG_193 0xC1
#define | LCD_REG_2 0x02
#define | LCD_REG_20 0x14
#define | LCD_REG_21 0x15
#define | LCD_REG_22 0x16
#define | LCD_REG_227 0xE3
#define | LCD_REG_229 0xE5
#define | LCD_REG_23 0x17
#define | LCD_REG_231 0xE7
#define | LCD_REG_239 0xEF
#define | LCD_REG_24 0x18
#define | LCD_REG_25 0x19
#define | LCD_REG_26 0x1A
#define | LCD_REG_27 0x1B
#define | LCD_REG_28 0x1C
#define | LCD_REG_29 0x1D
#define | LCD_REG_3 0x03
#define | LCD_REG_30 0x1E
#define | LCD_REG_31 0x1F
#define | LCD_REG_32 0x20
#define | LCD_REG_33 0x21
#define | LCD_REG_34 0x22
#define | LCD_REG_36 0x24
#define | LCD_REG_37 0x25
#define | LCD_REG_4 0x04
#define | LCD_REG_40 0x28
#define | LCD_REG_41 0x29
#define | LCD_REG_43 0x2B
#define | LCD_REG_45 0x2D
#define | LCD_REG_48 0x30
#define | LCD_REG_49 0x31
#define | LCD_REG_5 0x05
#define | LCD_REG_50 0x32
#define | LCD_REG_51 0x33
#define | LCD_REG_52 0x34
#define | LCD_REG_53 0x35
#define | LCD_REG_54 0x36
#define | LCD_REG_55 0x37
#define | LCD_REG_56 0x38
#define | LCD_REG_57 0x39
#define | LCD_REG_59 0x3B
#define | LCD_REG_6 0x06
#define | LCD_REG_60 0x3C
#define | LCD_REG_61 0x3D
#define | LCD_REG_62 0x3E
#define | LCD_REG_63 0x3F
#define | LCD_REG_64 0x40
#define | LCD_REG_65 0x41
#define | LCD_REG_66 0x42
#define | LCD_REG_67 0x43
#define | LCD_REG_68 0x44
#define | LCD_REG_69 0x45
#define | LCD_REG_7 0x07
#define | LCD_REG_70 0x46
#define | LCD_REG_71 0x47
#define | LCD_REG_72 0x48
#define | LCD_REG_73 0x49
#define | LCD_REG_74 0x4A
#define | LCD_REG_75 0x4B
#define | LCD_REG_76 0x4C
#define | LCD_REG_77 0x4D
#define | LCD_REG_78 0x4E
#define | LCD_REG_79 0x4F
#define | LCD_REG_8 0x08
#define | LCD_REG_80 0x50
#define | LCD_REG_81 0x51
#define | LCD_REG_82 0x52
#define | LCD_REG_83 0x53
#define | LCD_REG_9 0x09
#define | LCD_REG_96 0x60
#define | LCD_REG_97 0x61
#define | LCD_RS_GPIO_CLK RCC_APB2Periph_GPIOD
#define | LCD_RS_GPIO_PORT GPIOD
#define | LCD_RS_PIN GPIO_Pin_7
#define | LCD_SPI SPI2
LCD SPI Interface pins.
#define | LCD_SPI_CLK RCC_APB1Periph_SPI2
#define | LCD_SPI_MISO_GPIO_CLK RCC_APB2Periph_GPIOB
#define | LCD_SPI_MISO_GPIO_PORT GPIOB
#define | LCD_SPI_MISO_PIN GPIO_Pin_14
#define | LCD_SPI_MOSI_GPIO_CLK RCC_APB2Periph_GPIOB
#define | LCD_SPI_MOSI_GPIO_PORT GPIOB
#define | LCD_SPI_MOSI_PIN GPIO_Pin_15
#define | LCD_SPI_SCK_GPIO_CLK RCC_APB2Periph_GPIOB
#define | LCD_SPI_SCK_GPIO_PORT GPIOB
#define | LCD_SPI_SCK_PIN GPIO_Pin_13

Typedefs

typedef struct Point * | pPoint

Functions

void | LCD_Clear (uint16_t Color)
Clears the hole LCD.
void | LCD_ClearLine (uint8_t Line)
Clears the selected line.
void | LCD_ClosedPolyLine (pPoint Points, uint16_t PointCount)
Displays a closed polyline (between many points).
void | LCD_ClosedPolyLineRelative (pPoint Points, uint16_t PointCount)
Displays a closed relative polyline (between many points).
void | LCD_CtrlLinesConfig (void)
Configures LCD control lines in Output Push-Pull mode.
void | LCD_CtrlLinesWrite (GPIO_TypeDef *GPIOx, uint16_t CtrlPins, BitAction BitVal)
Sets or reset LCD control lines.
void | LCD_DeInit (void)
DeInitializes the LCD.
void | LCD_DisplayChar (uint8_t Line, uint16_t Column, uint8_t Ascii)
Displays one character (16dots width, 24dots height).
void | LCD_DisplayOff (void)
Disables the Display.
void | LCD_DisplayOn (void)
Enables the Display.
void | LCD_DisplayStringLine (uint8_t Line, uint8_t *ptr)
Displays a maximum of 20 char on the LCD.
void | LCD_DrawBMP (uint32_t BmpAddress)
void | LCD_DrawChar (uint8_t Xpos, uint16_t Ypos, const uint16_t *c)
Draws a character on LCD.
void | LCD_DrawCircle (uint8_t Xpos, uint16_t Ypos, uint16_t Radius)
Displays a circle.
void | LCD_DrawFullCircle (uint16_t Xpos, uint16_t Ypos, uint16_t Radius)
Displays a full circle.
void | LCD_DrawFullRect (uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height)
Displays a full rectangle.
void | LCD_DrawLine (uint8_t Xpos, uint16_t Ypos, uint16_t Length, uint8_t Direction)
Displays a line.
void | LCD_DrawMonoPict (const uint32_t *Pict)
Displays a monocolor picture.
void | LCD_DrawRect (uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width)
Displays a rectangle.
void | LCD_DrawUniLine (uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2)
Displays an uni line (between two points).
void | LCD_FillPolyLine (pPoint Points, uint16_t PointCount)
Displays a full polyline (between many points).
void | LCD_GetColors (__IO uint16_t *_TextColor, __IO uint16_t *_BackColor)
Gets the LCD Text and Background colors.
sFONT * | LCD_GetFont (void)
Gets the Text Font.
void | LCD_nCS_StartByte (uint8_t Start_Byte)
Reset LCD control line(/CS) and Send Start-Byte.
void | LCD_PolyLine (pPoint Points, uint16_t PointCount)
Displays an polyline (between many points).
void | LCD_PolyLineRelative (pPoint Points, uint16_t PointCount)
Displays a relative polyline (between many points).
void | LCD_PowerOn (void)
Power on the LCD.
uint16_t | LCD_ReadReg (uint8_t LCD_Reg)
Reads the selected LCD Register.
void | LCD_SetBackColor (__IO uint16_t Color)
Sets the Background color.
void | LCD_SetColors (__IO uint16_t _TextColor, __IO uint16_t _BackColor)
Sets the LCD Text and Background colors.
void | LCD_SetCursor (uint8_t Xpos, uint16_t Ypos)
Sets the cursor position.
void | LCD_SetDisplayWindow (uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width)
Sets a display window.
void | LCD_SetFont (sFONT *fonts)
Sets the Text Font.
void | LCD_SetTextColor (__IO uint16_t Color)
Sets the Text color.
void | LCD_Setup (void)
Setups the LCD.
void | LCD_SPIConfig (void)
Configures the LCD_SPI interface.
void | LCD_WindowModeDisable (void)
Disables LCD Window mode.
void | LCD_WriteRAM (uint16_t RGB_Code)
Writes to the LCD RAM.
void | LCD_WriteRAM_Prepare (void)
Prepare to write to the LCD RAM.
void | LCD_WriteRAMWord (uint16_t RGB_Code)
Writes 1 word to the LCD RAM.
void | LCD_WriteReg (uint8_t LCD_Reg, uint16_t LCD_RegValue)
Writes to the selected LCD register.
void | LCD_WriteRegIndex (uint8_t LCD_Reg)
Writes index to select the LCD register.
void | STM3210B_LCD_Init (void)
Initializes the LCD.

Detailed Description

This file contains all the functions prototypes for the stm3210b_eval_lcd firmware driver.

Author:
MCD Application Team
Version:
V4.5.0
Date:
07-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm3210b_eval_lcd.h.


STM32F10x Standard Peripherals Firmware Library: stm3210c_eval.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • STM3210C_EVAL
Functions | Variables

stm3210c_eval.c File Reference

This file provides

  • set of firmware functions to manage Leds, push-button and COM ports
  • low level initialization functions for SD card (on SPI) and I2C serial EEPROM (sEE) available on STM3210C-EVAL evaluation board from STMicroelectronics.
More...

#include "stm3210c_eval.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_dma.h"

Go to the source code of this file.

Functions

void | SD_LowLevel_DeInit (void)
DeInitializes the SD/SD communication.
void | SD_LowLevel_Init (void)
Initializes the SD_SPI and CS pins.
void | sEE_LowLevel_DeInit (void)
DeInitializes peripherals used by the I2C EEPROM driver.
void | sEE_LowLevel_DMAConfig (uint32_t pBuffer, uint32_t BufferSize, uint32_t Direction)
Initializes DMA channel used by the I2C EEPROM driver.
void | sEE_LowLevel_Init (void)
Initializes peripherals used by the I2C EEPROM driver.
void | STM_EVAL_COMInit (COM_TypeDef COM, USART_InitTypeDef *USART_InitStruct)
Configures COM port.
void | STM_EVAL_LEDInit (Led_TypeDef Led)
Configures LED GPIO.
void | STM_EVAL_LEDOff (Led_TypeDef Led)
Turns selected LED Off.
void | STM_EVAL_LEDOn (Led_TypeDef Led)
Turns selected LED On.
void | STM_EVAL_LEDToggle (Led_TypeDef Led)
Toggles the selected LED.
uint32_t | STM_EVAL_PBGetState (Button_TypeDef Button)
Returns the selected Button state.
void | STM_EVAL_PBInit (Button_TypeDef Button, ButtonMode_TypeDef Button_Mode)
Configures Button GPIO and EXTI Line.

Variables

const uint32_t | BUTTON_CLK [BUTTONn]
const uint16_t | BUTTON_EXTI_LINE [BUTTONn]
const uint16_t | BUTTON_IRQn [BUTTONn]
const uint16_t | BUTTON_PIN [BUTTONn]
const uint16_t | BUTTON_PIN_SOURCE [BUTTONn]
GPIO_TypeDef * | BUTTON_PORT [BUTTONn]
const uint16_t | BUTTON_PORT_SOURCE [BUTTONn]
const uint16_t | COM_RX_PIN [COMn] = {EVAL_COM1_RX_PIN}
GPIO_TypeDef * | COM_RX_PORT [COMn] = {EVAL_COM1_RX_GPIO_PORT}
const uint32_t | COM_RX_PORT_CLK [COMn] = {EVAL_COM1_RX_GPIO_CLK}
const uint16_t | COM_TX_PIN [COMn] = {EVAL_COM1_TX_PIN}
GPIO_TypeDef * | COM_TX_PORT [COMn] = {EVAL_COM1_TX_GPIO_PORT}
const uint32_t | COM_TX_PORT_CLK [COMn] = {EVAL_COM1_TX_GPIO_CLK}
USART_TypeDef * | COM_USART [COMn] = {EVAL_COM1}
const uint32_t | COM_USART_CLK [COMn] = {EVAL_COM1_CLK}
const uint32_t | GPIO_CLK [LEDn]
const uint16_t | GPIO_PIN [LEDn]
GPIO_TypeDef * | GPIO_PORT [LEDn]
DMA_InitTypeDef sEEDMA_InitStructure

Detailed Description

This file provides

  • set of firmware functions to manage Leds, push-button and COM ports
  • low level initialization functions for SD card (on SPI) and I2C serial EEPROM (sEE) available on STM3210C-EVAL evaluation board from STMicroelectronics.
Author:
MCD Application Team
Version:
V4.5.0
Date:
07-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm3210c_eval.c.


STM32F10x Standard Peripherals Firmware Library: stm3210c_eval.h File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • STM3210C_EVAL
Defines | Functions

stm3210c_eval.h File Reference

This file contains definitions for STM3210C_EVAL's Leds, push-buttons COM ports, SD Card on SPI and sEE on I2C hardware resources. More...

#include "stm32_eval.h"

Go to the source code of this file.

Defines

#define | BUTTONn 3
#define | COMn 1
#define | EVAL_COM1 USART2
Definition for COM port1, connected to USART2 (USART2 pins remapped on GPIOD)
#define | EVAL_COM1_CLK RCC_APB1Periph_USART2
#define | EVAL_COM1_IRQn USART2_IRQn
#define | EVAL_COM1_RX_GPIO_CLK RCC_APB2Periph_GPIOD
#define | EVAL_COM1_RX_GPIO_PORT GPIOD
#define | EVAL_COM1_RX_PIN GPIO_Pin_6
#define | EVAL_COM1_TX_GPIO_CLK RCC_APB2Periph_GPIOD
#define | EVAL_COM1_TX_GPIO_PORT GPIOD
#define | EVAL_COM1_TX_PIN GPIO_Pin_5
#define | KEY_BUTTON_EXTI_IRQn EXTI9_5_IRQn
#define | KEY_BUTTON_EXTI_LINE EXTI_Line9
#define | KEY_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource9
#define | KEY_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOB
#define | KEY_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOB
#define | KEY_BUTTON_GPIO_PORT GPIOB
#define | KEY_BUTTON_PIN GPIO_Pin_9
Key push-button.
#define | LED1_GPIO_CLK RCC_APB2Periph_GPIOD
#define | LED1_GPIO_PORT GPIOD
#define | LED1_PIN GPIO_Pin_7
#define | LED2_GPIO_CLK RCC_APB2Periph_GPIOD
#define | LED2_GPIO_PORT GPIOD
#define | LED2_PIN GPIO_Pin_13
#define | LED3_GPIO_CLK RCC_APB2Periph_GPIOD
#define | LED3_GPIO_PORT GPIOD
#define | LED3_PIN GPIO_Pin_3
#define | LED4_GPIO_CLK RCC_APB2Periph_GPIOD
#define | LED4_GPIO_PORT GPIOD
#define | LED4_PIN GPIO_Pin_4
#define | LEDn 4
#define | SD_CS_GPIO_CLK RCC_APB2Periph_GPIOA
#define | SD_CS_GPIO_PORT GPIOA
#define | SD_CS_PIN GPIO_Pin_4
#define | SD_DETECT_GPIO_CLK RCC_APB2Periph_GPIOE
#define | SD_DETECT_GPIO_PORT GPIOE
#define | SD_DETECT_PIN GPIO_Pin_0
#define | SD_SPI SPI3
SD SPI Interface pins.
#define | SD_SPI_CLK RCC_APB1Periph_SPI3
#define | SD_SPI_MISO_GPIO_CLK RCC_APB2Periph_GPIOC
#define | SD_SPI_MISO_GPIO_PORT GPIOC
#define | SD_SPI_MISO_PIN GPIO_Pin_11
#define | SD_SPI_MOSI_GPIO_CLK RCC_APB2Periph_GPIOC
#define | SD_SPI_MOSI_GPIO_PORT GPIOC
#define | SD_SPI_MOSI_PIN GPIO_Pin_12
#define | SD_SPI_SCK_GPIO_CLK RCC_APB2Periph_GPIOC
#define | SD_SPI_SCK_GPIO_PORT GPIOC
#define | SD_SPI_SCK_PIN GPIO_Pin_10
#define | sEE_DIRECTION_RX 1
#define | sEE_DIRECTION_TX 0
#define | sEE_I2C I2C1
I2C EEPROM Interface pins.
#define | sEE_I2C_CLK RCC_APB1Periph_I2C1
#define | sEE_I2C_DMA DMA1
#define | sEE_I2C_DMA_CHANNEL_RX DMA1_Channel7
#define | sEE_I2C_DMA_CHANNEL_TX DMA1_Channel6
#define | sEE_I2C_DMA_CLK RCC_AHBPeriph_DMA1
#define | sEE_I2C_DMA_FLAG_RX_GL DMA1_IT_GL7
#define | sEE_I2C_DMA_FLAG_RX_TC DMA1_IT_TC7
#define | sEE_I2C_DMA_FLAG_TX_GL DMA1_IT_GL6
#define | sEE_I2C_DMA_FLAG_TX_TC DMA1_IT_TC6
#define | sEE_I2C_DMA_PREPRIO 0
#define | sEE_I2C_DMA_RX_IRQHandler DMA1_Channel7_IRQHandler
#define | sEE_I2C_DMA_RX_IRQn DMA1_Channel7_IRQn
#define | sEE_I2C_DMA_SUBPRIO 0
#define | sEE_I2C_DMA_TX_IRQHandler DMA1_Channel6_IRQHandler
#define | sEE_I2C_DMA_TX_IRQn DMA1_Channel6_IRQn
#define | sEE_I2C_DR_Address ((uint32_t)0x40005410)
#define | sEE_I2C_SCL_GPIO_CLK RCC_APB2Periph_GPIOB
#define | sEE_I2C_SCL_GPIO_PORT GPIOB
#define | sEE_I2C_SCL_PIN GPIO_Pin_6
#define | sEE_I2C_SDA_GPIO_CLK RCC_APB2Periph_GPIOB
#define | sEE_I2C_SDA_GPIO_PORT GPIOB
#define | sEE_I2C_SDA_PIN GPIO_Pin_7
#define | sEE_M24C64_32
#define | sEE_TIME_CONST 72
#define | sEE_USE_DMA
#define | TAMPER_BUTTON_EXTI_IRQn EXTI15_10_IRQn
#define | TAMPER_BUTTON_EXTI_LINE EXTI_Line13
#define | TAMPER_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource13
#define | TAMPER_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOC
#define | TAMPER_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOC
#define | TAMPER_BUTTON_GPIO_PORT GPIOC
#define | TAMPER_BUTTON_PIN GPIO_Pin_13
Tamper push-button.
#define | WAKEUP_BUTTON_EXTI_IRQn EXTI0_IRQn
#define | WAKEUP_BUTTON_EXTI_LINE EXTI_Line0
#define | WAKEUP_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource0
#define | WAKEUP_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOA
#define | WAKEUP_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOA
#define | WAKEUP_BUTTON_GPIO_PORT GPIOA
#define | WAKEUP_BUTTON_PIN GPIO_Pin_0
Wakeup push-button.

Functions

void | SD_LowLevel_DeInit (void)
DeInitializes the SD/SD communication.
void | SD_LowLevel_Init (void)
Initializes the SD_SPI and CS pins.
void | sEE_LowLevel_DeInit (void)
DeInitializes peripherals used by the I2C EEPROM driver.
void | sEE_LowLevel_DMAConfig (uint32_t pBuffer, uint32_t BufferSize, uint32_t Direction)
Initializes DMA channel used by the I2C EEPROM driver.
void | sEE_LowLevel_Init (void)
Initializes peripherals used by the I2C EEPROM driver.
void | STM_EVAL_COMInit (COM_TypeDef COM, USART_InitTypeDef *USART_InitStruct)
Configures COM port.
void | STM_EVAL_LEDInit (Led_TypeDef Led)
Configures LED GPIO.
void | STM_EVAL_LEDOff (Led_TypeDef Led)
Turns selected LED Off.
void | STM_EVAL_LEDOn (Led_TypeDef Led)
Turns selected LED On.
void | STM_EVAL_LEDToggle (Led_TypeDef Led)
Toggles the selected LED.
uint32_t | STM_EVAL_PBGetState (Button_TypeDef Button)
Returns the selected Button state.
void | STM_EVAL_PBInit (Button_TypeDef Button, ButtonMode_TypeDef Button_Mode)
Configures Button GPIO and EXTI Line.

Detailed Description

This file contains definitions for STM3210C_EVAL's Leds, push-buttons COM ports, SD Card on SPI and sEE on I2C hardware resources.

Author:
MCD Application Team
Version:
V4.5.0
Date:
07-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 210 STMicroelectronics

Definition in file stm3210c_eval.h.


STM32F10x Standard Peripherals Firmware Library: stm3210c_eval_ioe.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • STM3210C_EVAL
Defines | Functions | Variables

stm3210c_eval_ioe.c File Reference

This file includes the IO Expander driver for STMPE811 IO Expander devices. More...

#include "stm3210c_eval_ioe.h"

Go to the source code of this file.

Defines

#define | TIMEOUT_MAX 0x1000
#define | TS_CONVERSION_DELAY 0x10000

Functions

static void | delay (__IO uint32_t nCount)
Inserts a delay time.
uint16_t | I2C_ReadDataBuffer (uint8_t DeviceAddr, uint32_t RegisterAddr)
Reads a buffer of 2 bytes from the device registers.
uint8_t | I2C_ReadDeviceRegister (uint8_t DeviceAddr, uint8_t RegisterAddr)
Reads a register of the device through I2C.
uint8_t | I2C_WriteDeviceRegister (uint8_t DeviceAddr, uint8_t RegisterAddr, uint8_t RegisterValue)
Writes a value in a register of the device through I2C.
uint8_t | IOE_ClearGITPending (uint8_t DeviceAddr, uint8_t Global_IT)
Clears the selected Global interrupt pending bit(s)
uint8_t | IOE_ClearIOITPending (uint8_t DeviceAddr, uint8_t IO_IT)
Clears the selected IO interrupt pending bit(s).
uint8_t | IOE_Config (void)
Initializes and Configures the two IO_Expanders Functionalities (IOs, Touch Screen ..) and configures all STM3210C-EVAL necessary hardware (GPIOs, APB clocks ..).
static void | IOE_DMA_Config (IOE_DMADirection_TypeDef Direction, uint8_t *buffer)
Configure the DMA Peripheral used to handle communication via I2C.
static void | IOE_EXTI_Config (void)
Configures the IO expander Interrupt line and GPIO in EXTI mode.
uint8_t | IOE_FnctCmd (uint8_t DeviceAddr, uint8_t Fct, FunctionalState NewState)
Configures the selcted IO Expander functionalities.
FlagStatus | IOE_GetGITStatus (uint8_t DeviceAddr, uint8_t Global_IT)
Checks the selected Global interrupt source pending bit.
FlagStatus | IOE_GetIOITStatus (uint8_t DeviceAddr, uint8_t IO_IT)
Checks the status of the selected IO interrupt pending bit.
uint8_t | IOE_GITCmd (uint8_t DeviceAddr, FunctionalState NewState)
Enables or disables the Global interrupt.
uint8_t | IOE_GITConfig (uint8_t DeviceAddr, uint8_t Global_IT, FunctionalState NewState)
Configures the selected source to generate or not a global interrupt.
static void | IOE_GPIO_Config (void)
Initializes the GPIO pins used by the IO expander.
static void | IOE_I2C_Config (void)
Configure the I2C Peripheral used to communicate with IO_Expanders.
uint8_t | IOE_IOAFConfig (uint8_t DeviceAddr, uint8_t IO_Pin, FunctionalState NewState)
Configures the selected pin to be in Alternate function or not.
uint8_t | IOE_IOEdgeConfig (uint8_t DeviceAddr, uint8_t IO_Pin, uint8_t Edge)
Configures the Edge for which a transition is detectable for the the selected pin.
uint8_t | IOE_IOITConfig (uint8_t DeviceAddr, uint8_t IO_IT, FunctionalState NewState)
Configures the selected pins to generate an interrupt or not.
uint8_t | IOE_IOPinConfig (uint8_t DeviceAddr, uint8_t IO_Pin, uint8_t Direction)
Configures the selected pin direction (to be an input or an output)
uint8_t | IOE_IsOperational (uint8_t DeviceAddr)
Checks if the selected device is correctly configured and communicates correctly ont the I2C bus.
uint8_t | IOE_ITConfig (uint32_t IOE_ITSRC_Source)
Configures The selected interrupts on the IO Expanders.
uint8_t | IOE_ITOutConfig (uint8_t Polarity, uint8_t Type)
Configures the Interrupt line active state and format (level/edge)
JOYState_TypeDef | IOE_JoyStickGetState (void)
Returns the current Joystick status.
uint16_t | IOE_ReadID (uint8_t DeviceAddr)
Reads the selected device's ID.
uint8_t | IOE_ReadIOPin (uint32_t IO_Pin)
Returns the status of the selected input IO pin.
uint8_t | IOE_Reset (uint8_t DeviceAddr)
Resets the IO Expander by Software (SYS_CTRL1, RESET bit).
uint8_t | IOE_TempSens_Config (void)
Configures and enables the Temperature sensor module.
uint32_t | IOE_TempSens_GetData (void)
Returns the temperature row value (in 16 bit format).
uint8_t | IOE_TS_Config (void)
Configures the touch Screen Controller (Single point detection)
TS_STATE * | IOE_TS_GetState (void)
Returns Status and positions of the Touch screen.
static uint16_t | IOE_TS_Read_X (void)
Return Touch Screen X position value.
static uint16_t | IOE_TS_Read_Y (void)
Return Touch Screen Y position value.
static uint16_t | IOE_TS_Read_Z (void)
Return Touch Screen Z position value.
uint8_t | IOE_WriteIOPin (uint8_t IO_Pin, IOE_BitValue_TypeDef BitVal)
Writes a bit value to an output IO pin.

Variables

uint32_t | IOE_TimeOut = TIMEOUT_MAX
TS_STATE TS_State

Detailed Description

This file includes the IO Expander driver for STMPE811 IO Expander devices.

Author:
MCD Application Team
Version:
V4.5.0
Date:
07-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm3210c_eval_ioe.c.


STM32F10x Standard Peripherals Firmware Library: stm3210c_eval_ioe.h File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • STM3210C_EVAL
Data Structures | Defines | Enumerations | Functions

stm3210c_eval_ioe.h File Reference

This file contains all the functions prototypes for the IO Expander firmware driver. More...

#include "stm32f10x.h"

Go to the source code of this file.

Data Structures

struct | TS_STATE
Touch Screen Information structure. More...

Defines

#define | _delay_ delay
Uncomment the line below to enable verfying each written byte in write operation.
#define | ALL_IT 0xFF
#define | AUDIO_RESET_PIN IO_Pin_2 /* IO_Exapnader_2 */
Eval Board IO Pins definition.
#define | Direction_IN 0x00
IO Pin directions.
#define | Direction_OUT 0x01
#define | EDGE_FALLING 0x01
Edge detection value.
#define | EDGE_RISING 0x02
#define | IO1_IN_ALL_PINS (uint32_t)(MEMS_INT1_PIN | MEMS_INT2_PIN)
Eval Board both IO Exapanders Pins definition.
#define | IO1_OUT_ALL_PINS (uint32_t)(VBAT_DIV_PIN)
#define | IO2_IN_ALL_PINS (uint32_t)(JOY_IO_PINS)
#define | IO2_OUT_ALL_PINS (uint32_t)(AUDIO_RESET_PIN | MII_INT_PIN)
#define | IO_IT_0 0x01
IO Interrupts.
#define | IO_IT_1 0x02
#define | IO_IT_2 0x04
#define | IO_IT_3 0x08
#define | IO_IT_4 0x10
#define | IO_IT_5 0x20
#define | IO_IT_6 0x40
#define | IO_IT_7 0x80
#define | IO_Pin_0 0x01
IO Pins.
#define | IO_Pin_1 0x02
#define | IO_Pin_2 0x04
#define | IO_Pin_3 0x08
#define | IO_Pin_4 0x10
#define | IO_Pin_5 0x20
#define | IO_Pin_6 0x40
#define | IO_Pin_7 0x80
#define | IO_Pin_ALL 0xFF
#define | IOE_1_ADDR 0x82
The 7 bits IO Expanders adresses and chip IDs.
#define | IOE_2_ADDR 0x88
#define | IOE_ADC_FCT 0x01
IO Expander Functionalities definitions.
#define | IOE_DMA DMA1
IOE DMA definitions.
#define | IOE_DMA_CLK RCC_AHBPeriph_DMA1
#define | IOE_DMA_RX_CHANNEL DMA1_Channel7
#define | IOE_DMA_RX_TCFLAG DMA1_FLAG_TC7
#define | IOE_DMA_TX_CHANNEL DMA1_Channel6
#define | IOE_DMA_TX_TCFLAG DMA1_FLAG_TC6
#define | IOE_GIT_ADC 0x40
#define | IOE_GIT_EN 0x01
Global interrupt Enable bit.
#define | IOE_GIT_FE 0x10
#define | IOE_GIT_FF 0x08
#define | IOE_GIT_FOV 0x04
#define | IOE_GIT_FTH 0x02
#define | IOE_GIT_GPIO 0x80
Glaobal Interrupts definitions.
#define | IOE_GIT_TEMP 0x20
#define | IOE_GIT_TOUCH 0x01
#define | IOE_I2C I2C1
I2C port definitions.
#define | IOE_I2C_CLK RCC_APB1Periph_I2C1
#define | IOE_I2C_DR ((uint32_t)0x40005410)
#define | IOE_I2C_SCL_GPIO_CLK RCC_APB2Periph_GPIOB
#define | IOE_I2C_SCL_GPIO_PORT GPIOB
#define | IOE_I2C_SCL_PIN GPIO_Pin_6
#define | IOE_I2C_SDA_GPIO_CLK RCC_APB2Periph_GPIOB
#define | IOE_I2C_SDA_GPIO_PORT GPIOB
#define | IOE_I2C_SDA_PIN GPIO_Pin_7
#define | IOE_I2C_SPEED 300000
#define | IOE_INMEMS_IT (uint8_t)(IO_IT_2 | IO_IT_3)
#define | IOE_IO_FCT 0x04
#define | IOE_IT_EXTI_IRQn EXTI15_10_IRQn
#define | IOE_IT_EXTI_LINE EXTI_Line14
#define | IOE_IT_EXTI_PIN_SOURCE GPIO_PinSource14
#define | IOE_IT_EXTI_PORT_SOURCE GPIO_PortSourceGPIOB
#define | IOE_IT_GPIO_CLK RCC_APB2Periph_GPIOB
#define | IOE_IT_GPIO_PORT GPIOB
#define | IOE_IT_PIN GPIO_Pin_14
IO Expander Interrupt line on EXTI.
#define | IOE_ITSRC_INMEMS 0x02
#define | IOE_ITSRC_JOYSTICK 0x04
#define | IOE_ITSRC_TEMPSENS 0x08
#define | IOE_ITSRC_TSC 0x01
Interrupt source configuration definitons.
#define | IOE_JOY_IT (uint8_t)(IO_IT_3 | IO_IT_4 | IO_IT_5 | IO_IT_6 | IO_IT_7)
#define | IOE_REG_ADC_CAPT 0x22
#define | IOE_REG_ADC_CTRL1 0x20
#define | IOE_REG_ADC_CTRL2 0x21
#define | IOE_REG_ADC_DATA_CH0 0x30
#define | IOE_REG_ADC_DATA_CH1 0x32
#define | IOE_REG_ADC_DATA_CH2 0x34
#define | IOE_REG_ADC_DATA_CH3 0x36
#define | IOE_REG_ADC_DATA_CH4 0x38
#define | IOE_REG_ADC_DATA_CH5 0x3A
#define | IOE_REG_ADC_DATA_CH6 0x3B
#define | IOE_REG_ADC_DATA_CH7 0x3C
#define | IOE_REG_ADC_INT_EN 0x0E
ADC Registers.
#define | IOE_REG_ADC_INT_STA 0x0F
#define | IOE_REG_CHP_ID 0x00
Identification registers.
#define | IOE_REG_FIFO_SIZE 0x4C
#define | IOE_REG_FIFO_STA 0x4B
#define | IOE_REG_FIFO_TH 0x4A
#define | IOE_REG_GPIO_AF 0x17
#define | IOE_REG_GPIO_CLR_PIN 0x11
#define | IOE_REG_GPIO_DIR 0x13
#define | IOE_REG_GPIO_ED 0x14
#define | IOE_REG_GPIO_FE 0x16
#define | IOE_REG_GPIO_INT_EN 0x0C
#define | IOE_REG_GPIO_INT_STA 0x0D
#define | IOE_REG_GPIO_MP_STA 0x12
#define | IOE_REG_GPIO_RE 0x15
#define | IOE_REG_GPIO_SET_PIN 0x10
GPIO Registers.
#define | IOE_REG_ID_VER 0x02
#define | IOE_REG_INT_CTRL 0x09
Interrupt Control register.
#define | IOE_REG_INT_EN 0x0A
#define | IOE_REG_INT_STA 0x0B
#define | IOE_REG_SPI_CFG 0x08
#define | IOE_REG_SYS_CTRL1 0x03
General Control Registers.
#define | IOE_REG_SYS_CTRL2 0x04
#define | IOE_REG_TEMP_CTRL 0x60
Temperature Sensor registers.
#define | IOE_REG_TEMP_DATA 0x61
#define | IOE_REG_TEMP_TH 0x62
#define | IOE_REG_TSC_CFG 0x41
#define | IOE_REG_TSC_CTRL 0x40
TouchScreen Registers.
#define | IOE_REG_TSC_DATA 0x57
#define | IOE_REG_TSC_DATA_X 0x4D
#define | IOE_REG_TSC_DATA_XYZ 0x52
#define | IOE_REG_TSC_DATA_Y 0x4F
#define | IOE_REG_TSC_DATA_Z 0x51
#define | IOE_REG_TSC_FRACT_XYZ 0x56
#define | IOE_REG_TSC_I_DRIVE 0x58
#define | IOE_REG_TSC_SHIELD 0x59
#define | IOE_REG_WDM_BL_X 0x46
#define | IOE_REG_WDM_BL_Y 0x48
#define | IOE_REG_WDM_TR_X 0x42
#define | IOE_REG_WDM_TR_Y 0x44
#define | IOE_TEMPSENS_FCT 0x08
#define | IOE_TimeoutUserCallback() IOE_TIMEOUT
Timeout user callback function.
#define | IOE_TS_FCT 0x02
#define | IOE_TS_IT (uint8_t)(IO_IT_0 | IO_IT_1 | IO_IT_2)
#define | JOY_IO_DOWN IO_Pin_6
#define | JOY_IO_LEFT IO_Pin_5
#define | JOY_IO_NONE JOY_IO_PINS
#define | JOY_IO_PINS (uint32_t)(IO_Pin_3 | IO_Pin_4 | IO_Pin_5 | IO_Pin_6 | IO_Pin_7)
#define | JOY_IO_RIGHT IO_Pin_4
#define | JOY_IO_SEL IO_Pin_7
JOYSTICK Pins definition.
#define | JOY_IO_UP IO_Pin_3
#define | MEMS_INT1_PIN IO_Pin_3 /* IO_Exapnader_1 */
#define | MEMS_INT2_PIN IO_Pin_2 /* IO_Exapnader_1 */
#define | MII_INT_PIN IO_Pin_0 /* IO_Exapnader_2 */
#define | Polarity_High 0x04
#define | Polarity_Low 0x00
Interrupt Line output parameters.
#define | STMPE811_ID 0x0811
#define | TOUCH_IO_ALL (uint32_t)(IO_Pin_1 | IO_Pin_2 | IO_Pin_3 | IO_Pin_4)
#define | TOUCH_XD IO_Pin_2 /* IO_Exapnader_1 */
#define | TOUCH_XU IO_Pin_4 /* IO_Exapnader_1 */
#define | TOUCH_YD IO_Pin_1 /* IO_Exapnader_1 */
Touch Screen Pins definition.
#define | TOUCH_YU IO_Pin_3 /* IO_Exapnader_1 */
#define | Type_Edge 0x02
#define | Type_Level 0x00
#define | VBAT_DIV_PIN IO_Pin_0 /* IO_Exapnader_1 */

Enumerations

enum | IOE_BitValue_TypeDef { BitReset = 0, BitSet = 1, BitReset = 0, BitSet = 1 }

IO bit values.

More...
enum | IOE_DMADirection_TypeDef { IOE_DMA_TX = 0, IOE_DMA_RX = 1, IOE_DMA_TX = 0, IOE_DMA_RX = 1 }

IOE DMA Direction.

More...
enum IOE_Status_TypDef {
IOE_OK = 0, IOE_FAILURE, IOE_TIMEOUT, PARAM_ERROR,
IOE1_NOT_OPERATIONAL, IOE_OK = 0, IOE_FAILURE, IOE_TIMEOUT,
PARAM_ERROR, IOE1_NOT_OPERATIONAL, IOE2_NOT_OPERATIONAL
}

IO_Expander Error codes.

More...
enum JOYState_TypeDef {
JOY_NONE = 0, JOY_SEL = 1, JOY_DOWN = 2, JOY_LEFT = 3,
JOY_RIGHT = 4, JOY_UP = 5, JOY_NONE = 0, JOY_SEL = 1,
JOY_DOWN = 2, JOY_LEFT = 3, JOY_RIGHT = 4, JOY_UP = 5
}

Joystick State definitions.

More...

Functions

uint16_t | I2C_ReadDataBuffer (uint8_t DeviceAddr, uint32_t RegisterAddr)
Reads a buffer of 2 bytes from the device registers.
uint8_t | I2C_ReadDeviceRegister (uint8_t DeviceAddr, uint8_t RegisterAddr)
Reads a register of the device through I2C.
uint8_t | I2C_WriteDeviceRegister (uint8_t DeviceAddr, uint8_t RegisterAddr, uint8_t RegisterValue)
Writes a value in a register of the device through I2C.
uint8_t | IOE_ClearGITPending (uint8_t DeviceAddr, uint8_t IO_IT)
Clears the selected Global interrupt pending bit(s)
uint8_t | IOE_ClearIOITPending (uint8_t DeviceAddr, uint8_t IO_IT)
Clears the selected IO interrupt pending bit(s).
uint8_t | IOE_Config (void)
Configuration and initialization functions.
uint8_t | IOE_FnctCmd (uint8_t DeviceAddr, uint8_t Fct, FunctionalState NewState)
Configures the selcted IO Expander functionalities.
FlagStatus | IOE_GetGITStatus (uint8_t DeviceAddr, uint8_t Global_IT)
Interrupts Mangement functions.
FlagStatus | IOE_GetIOITStatus (uint8_t DeviceAddr, uint8_t IO_IT)
Checks the status of the selected IO interrupt pending bit.
uint8_t | IOE_GITCmd (uint8_t DeviceAddr, FunctionalState NewState)
Enables or disables the Global interrupt.
uint8_t | IOE_GITConfig (uint8_t DeviceAddr, uint8_t Global_IT, FunctionalState NewState)
Configures the selected source to generate or not a global interrupt.
uint8_t | IOE_IOAFConfig (uint8_t DeviceAddr, uint8_t IO_Pin, FunctionalState NewState)
Configures the selected pin to be in Alternate function or not.
uint8_t | IOE_IOEdgeConfig (uint8_t DeviceAddr, uint8_t IO_Pin, uint8_t Edge)
Configures the Edge for which a transition is detectable for the the selected pin.
uint8_t | IOE_IOITConfig (uint8_t DeviceAddr, uint8_t IO_IT, FunctionalState NewState)
Configures the selected pins to generate an interrupt or not.
uint8_t | IOE_IOPinConfig (uint8_t DeviceAddr, uint8_t IO_Pin, uint8_t Direction)
Configures the selected pin direction (to be an input or an output)
uint8_t | IOE_IsOperational (uint8_t DeviceAddr)
IO-Expander Control functions.
uint8_t | IOE_ITConfig (uint32_t IOE_ITSRC_Source)
Configures The selected interrupts on the IO Expanders.
uint8_t | IOE_ITOutConfig (uint8_t Polarity, uint8_t Type)
Configures the Interrupt line active state and format (level/edge)
JOYState_TypeDef | IOE_JoyStickGetState (void)
Returns the current Joystick status.
uint16_t | IOE_ReadID (uint8_t DeviceAddr)
Reads the selected device's ID.
uint8_t | IOE_ReadIOPin (uint32_t IO_Pin)
Returns the status of the selected input IO pin.
uint8_t | IOE_Reset (uint8_t DeviceAddr)
Resets the IO Expander by Software (SYS_CTRL1, RESET bit).
uint8_t | IOE_TempSens_Config (void)
Configures and enables the Temperature sensor module.
uint32_t | IOE_TempSens_GetData (void)
Temperature Sensor functions.
uint8_t | IOE_TS_Config (void)
Low Layer functions.
TS_STATE * | IOE_TS_GetState (void)
Touch Screen controller functions.
uint8_t | IOE_WriteIOPin (uint8_t IO_Pin, IOE_BitValue_TypeDef BitVal)
IO pins control functions.

Detailed Description

This file contains all the functions prototypes for the IO Expander firmware driver.

Author:
MCD Application Team
Version:
V4.5.0
Date:
07-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm3210c_eval_ioe.h.


STM32F10x Standard Peripherals Firmware Library: stm3210c_eval_lcd.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • STM3210C_EVAL
Defines | Functions | Variables

stm3210c_eval_lcd.c File Reference

This file includes the LCD driver for AM-240320L8TNQW00H (LCD_ILI9320) Liquid Crystal Display Module of STM3210C-EVAL board. More...

#include "stm3210c_eval_lcd.h"
#include "../Common/fonts.c"

Go to the source code of this file.

Defines

#define | ABS(X) ((X) > 0 ? (X) : -(X))
#define | LCD_READ_REG 0x03
#define | LCD_WRITE_REG 0x02
#define | MAX_POLY_CORNERS 200
#define | POLY_X(Z) ((int32_t)((Points + Z)->Y))
#define | POLY_Y(Z) ((int32_t)((Points + Z)->X))
#define | READ_STATUS 0x01
#define | SET_INDEX 0x00
#define | START_BYTE 0x70

Functions

static void | delay (__IO uint32_t nCount)
Inserts a delay time.
void | LCD_Clear (uint16_t Color)
Clears the hole LCD.
void | LCD_ClearLine (uint8_t Line)
Clears the selected line.
void | LCD_ClosedPolyLine (pPoint Points, uint16_t PointCount)
Displays a closed polyline (between many points).
void | LCD_ClosedPolyLineRelative (pPoint Points, uint16_t PointCount)
Displays a closed relative polyline (between many points).
void | LCD_CtrlLinesConfig (void)
Configures LCD control lines in Output Push-Pull mode.
void | LCD_CtrlLinesWrite (GPIO_TypeDef *GPIOx, uint16_t CtrlPins, BitAction BitVal)
Sets or reset LCD control lines.
void | LCD_DeInit (void)
DeInitializes the LCD.
void | LCD_DisplayChar (uint8_t Line, uint16_t Column, uint8_t Ascii)
Displays one character (16dots width, 24dots height).
void | LCD_DisplayOff (void)
Disables the Display.
void | LCD_DisplayOn (void)
Enables the Display.
void | LCD_DisplayStringLine (uint8_t Line, uint8_t *ptr)
Displays a maximum of 20 char on the LCD.
void | LCD_DrawChar (uint8_t Xpos, uint16_t Ypos, const uint16_t *c)
Draws a character on LCD.
void | LCD_DrawCircle (uint8_t Xpos, uint16_t Ypos, uint16_t Radius)
Displays a circle.
void | LCD_DrawFullCircle (uint16_t Xpos, uint16_t Ypos, uint16_t Radius)
Displays a full circle.
void | LCD_DrawFullRect (uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height)
Displays a full rectangle.
void | LCD_DrawLine (uint8_t Xpos, uint16_t Ypos, uint16_t Length, uint8_t Direction)
Displays a line.
void | LCD_DrawMonoPict (const uint32_t *Pict)
Displays a monocolor picture.
void | LCD_DrawRect (uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width)
Displays a rectangle.
void | LCD_DrawUniLine (uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2)
Displays an uni line (between two points).
void | LCD_FillPolyLine (pPoint Points, uint16_t PointCount)
Displays a full polyline (between many points).
void | LCD_GetColors (__IO uint16_t *_TextColor, __IO uint16_t *_BackColor)
Gets the LCD Text and Background colors.
sFONT * | LCD_GetFont (void)
Gets the Text Font.
void | LCD_nCS_StartByte (uint8_t Start_Byte)
Reset LCD control line(/CS) and Send Start-Byte.
void | LCD_PolyLine (pPoint Points, uint16_t PointCount)
Displays an polyline (between many points).
void | LCD_PolyLineRelative (pPoint Points, uint16_t PointCount)
Displays a relative polyline (between many points).
static void | LCD_PolyLineRelativeClosed (pPoint Points, uint16_t PointCount, uint16_t Closed)
Displays an relative polyline (between many points).
void | LCD_PowerOn (void)
Power on the LCD.
uint16_t | LCD_ReadReg (uint8_t LCD_Reg)
Reads the selected LCD Register.
void | LCD_SetBackColor (__IO uint16_t Color)
Sets the Background color.
void | LCD_SetColors (__IO uint16_t _TextColor, __IO uint16_t _BackColor)
Sets the LCD Text and Background colors.
void | LCD_SetCursor (uint8_t Xpos, uint16_t Ypos)
Sets the cursor position.
void | LCD_SetDisplayWindow (uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width)
Sets a display window.
void | LCD_SetFont (sFONT *fonts)
Sets the Text Font.
void | LCD_SetTextColor (__IO uint16_t Color)
Sets the Text color.
void | LCD_Setup (void)
Setups the LCD.
void | LCD_SPIConfig (void)
Configures the LCD_SPI interface.
void | LCD_WindowModeDisable (void)
Disables LCD Window mode.
void | LCD_WriteRAM (uint16_t RGB_Code)
Writes to the LCD RAM.
void | LCD_WriteRAM_Prepare (void)
Prepare to write to the LCD RAM.
void | LCD_WriteRAMWord (uint16_t RGB_Code)
Writes 1 word to the LCD RAM.
void | LCD_WriteReg (uint8_t LCD_Reg, uint16_t LCD_RegValue)
Writes to the selected LCD register.
void | LCD_WriteRegIndex (uint8_t LCD_Reg)
Writes index to select the LCD register.
static void | PutPixel (int16_t x, int16_t y)
Displays a pixel.
void | STM3210C_LCD_Init (void)
Initializes the LCD.

Variables

static __IO uint16_t | BackColor = 0xFFFF
static sFONT * | LCD_Currentfonts
static __IO uint16_t | TextColor = 0x0000

Detailed Description

This file includes the LCD driver for AM-240320L8TNQW00H (LCD_ILI9320) Liquid Crystal Display Module of STM3210C-EVAL board.

Author:
MCD Application Team
Version:
V4.5.0
Date:
07-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm3210c_eval_lcd.c.


STM32F10x Standard Peripherals Firmware Library: stm3210c_eval_lcd.h File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • STM3210C_EVAL
Data Structures | Defines | Typedefs | Functions

stm3210c_eval_lcd.h File Reference

This file contains all the functions prototypes for the lcd firmware driver. More...

#include "stm32f10x.h"
#include "../Common/fonts.h"

Go to the source code of this file.

Data Structures

struct | Point

Defines

#define | _delay_ delay
Uncomment the line below if you want to use LCD_DrawBMP function to display a bitmap picture on the LCD.
#define | ASSEMBLE_RGB(R, G, B) ((((R)& 0xF8) << 8) | (((G) & 0xFC) << 3) | (((B) & 0xF8) >> 3))
#define | LCD_COLOR_BLACK 0x0000
#define | LCD_COLOR_BLUE 0x001F
#define | LCD_COLOR_BLUE2 0x051F
#define | LCD_COLOR_CYAN 0x7FFF
#define | LCD_COLOR_GREEN 0x07E0
#define | LCD_COLOR_GREY 0xF7DE
#define | LCD_COLOR_MAGENTA 0xF81F
#define | LCD_COLOR_RED 0xF800
#define | LCD_COLOR_WHITE 0xFFFF
LCD color.
#define | LCD_COLOR_YELLOW 0xFFE0
#define | LCD_DEFAULT_FONT Font16x24
LCD default font.
#define | LCD_DIR_HORIZONTAL 0x0000
LCD Direction.
#define | LCD_DIR_VERTICAL 0x0001
#define | LCD_LINE_0 LINE(0)
LCD Lines depending on the chosen fonts.
#define | LCD_LINE_1 LINE(1)
#define | LCD_LINE_10 LINE(10)
#define | LCD_LINE_11 LINE(11)
#define | LCD_LINE_12 LINE(12)
#define | LCD_LINE_13 LINE(13)
#define | LCD_LINE_14 LINE(14)
#define | LCD_LINE_15 LINE(15)
#define | LCD_LINE_16 LINE(16)
#define | LCD_LINE_17 LINE(17)
#define | LCD_LINE_18 LINE(18)
#define | LCD_LINE_19 LINE(19)
#define | LCD_LINE_2 LINE(2)
#define | LCD_LINE_20 LINE(20)
#define | LCD_LINE_21 LINE(21)
#define | LCD_LINE_22 LINE(22)
#define | LCD_LINE_23 LINE(23)
#define | LCD_LINE_24 LINE(24)
#define | LCD_LINE_25 LINE(25)
#define | LCD_LINE_26 LINE(26)
#define | LCD_LINE_27 LINE(27)
#define | LCD_LINE_28 LINE(28)
#define | LCD_LINE_29 LINE(29)
#define | LCD_LINE_3 LINE(3)
#define | LCD_LINE_4 LINE(4)
#define | LCD_LINE_5 LINE(5)
#define | LCD_LINE_6 LINE(6)
#define | LCD_LINE_7 LINE(7)
#define | LCD_LINE_8 LINE(8)
#define | LCD_LINE_9 LINE(9)
#define | LCD_NCS_GPIO_CLK RCC_APB2Periph_GPIOB
#define | LCD_NCS_GPIO_PORT GPIOB
#define | LCD_NCS_PIN GPIO_Pin_2
LCD Control pins.
#define | LCD_PIXEL_HEIGHT 0x00F0
#define | LCD_PIXEL_WIDTH 0x0140
LCD Size (Width and Height)
#define | LCD_REG_0 0x00
LCD Registers.
#define | LCD_REG_1 0x01
#define | LCD_REG_10 0x0A
#define | LCD_REG_106 0x6A
#define | LCD_REG_118 0x76
#define | LCD_REG_12 0x0C
#define | LCD_REG_128 0x80
#define | LCD_REG_129 0x81
#define | LCD_REG_13 0x0D
#define | LCD_REG_130 0x82
#define | LCD_REG_131 0x83
#define | LCD_REG_132 0x84
#define | LCD_REG_133 0x85
#define | LCD_REG_134 0x86
#define | LCD_REG_135 0x87
#define | LCD_REG_136 0x88
#define | LCD_REG_137 0x89
#define | LCD_REG_139 0x8B
#define | LCD_REG_14 0x0E
#define | LCD_REG_140 0x8C
#define | LCD_REG_141 0x8D
#define | LCD_REG_143 0x8F
#define | LCD_REG_144 0x90
#define | LCD_REG_145 0x91
#define | LCD_REG_146 0x92
#define | LCD_REG_147 0x93
#define | LCD_REG_148 0x94
#define | LCD_REG_149 0x95
#define | LCD_REG_15 0x0F
#define | LCD_REG_150 0x96
#define | LCD_REG_151 0x97
#define | LCD_REG_152 0x98
#define | LCD_REG_153 0x99
#define | LCD_REG_154 0x9A
#define | LCD_REG_157 0x9D
#define | LCD_REG_16 0x10
#define | LCD_REG_17 0x11
#define | LCD_REG_18 0x12
#define | LCD_REG_19 0x13
#define | LCD_REG_192 0xC0
#define | LCD_REG_193 0xC1
#define | LCD_REG_2 0x02
#define | LCD_REG_20 0x14
#define | LCD_REG_21 0x15
#define | LCD_REG_22 0x16
#define | LCD_REG_229 0xE5
#define | LCD_REG_23 0x17
#define | LCD_REG_24 0x18
#define | LCD_REG_25 0x19
#define | LCD_REG_26 0x1A
#define | LCD_REG_27 0x1B
#define | LCD_REG_28 0x1C
#define | LCD_REG_29 0x1D
#define | LCD_REG_3 0x03
#define | LCD_REG_30 0x1E
#define | LCD_REG_31 0x1F
#define | LCD_REG_32 0x20
#define | LCD_REG_33 0x21
#define | LCD_REG_34 0x22
#define | LCD_REG_36 0x24
#define | LCD_REG_37 0x25
#define | LCD_REG_4 0x04
#define | LCD_REG_40 0x28
#define | LCD_REG_41 0x29
#define | LCD_REG_43 0x2B
#define | LCD_REG_45 0x2D
#define | LCD_REG_48 0x30
#define | LCD_REG_49 0x31
#define | LCD_REG_5 0x05
#define | LCD_REG_50 0x32
#define | LCD_REG_51 0x33
#define | LCD_REG_52 0x34
#define | LCD_REG_53 0x35
#define | LCD_REG_54 0x36
#define | LCD_REG_55 0x37
#define | LCD_REG_56 0x38
#define | LCD_REG_57 0x39
#define | LCD_REG_59 0x3B
#define | LCD_REG_6 0x06
#define | LCD_REG_60 0x3C
#define | LCD_REG_61 0x3D
#define | LCD_REG_62 0x3E
#define | LCD_REG_63 0x3F
#define | LCD_REG_64 0x40
#define | LCD_REG_65 0x41
#define | LCD_REG_66 0x42
#define | LCD_REG_67 0x43
#define | LCD_REG_68 0x44
#define | LCD_REG_69 0x45
#define | LCD_REG_7 0x07
#define | LCD_REG_70 0x46
#define | LCD_REG_71 0x47
#define | LCD_REG_72 0x48
#define | LCD_REG_73 0x49
#define | LCD_REG_74 0x4A
#define | LCD_REG_75 0x4B
#define | LCD_REG_76 0x4C
#define | LCD_REG_77 0x4D
#define | LCD_REG_78 0x4E
#define | LCD_REG_79 0x4F
#define | LCD_REG_8 0x08
#define | LCD_REG_80 0x50
#define | LCD_REG_81 0x51
#define | LCD_REG_82 0x52
#define | LCD_REG_83 0x53
#define | LCD_REG_9 0x09
#define | LCD_REG_96 0x60
#define | LCD_REG_97 0x61
#define | LCD_SPI SPI3
LCD SPI Interface pins.
#define | LCD_SPI_CLK RCC_APB1Periph_SPI3
#define | LCD_SPI_MISO_GPIO_CLK RCC_APB2Periph_GPIOC
#define | LCD_SPI_MISO_GPIO_PORT GPIOC
#define | LCD_SPI_MISO_PIN GPIO_Pin_11
#define | LCD_SPI_MOSI_GPIO_CLK RCC_APB2Periph_GPIOC
#define | LCD_SPI_MOSI_GPIO_PORT GPIOC
#define | LCD_SPI_MOSI_PIN GPIO_Pin_12
#define | LCD_SPI_SCK_GPIO_CLK RCC_APB2Periph_GPIOC
#define | LCD_SPI_SCK_GPIO_PORT GPIOC
#define | LCD_SPI_SCK_PIN GPIO_Pin_10

Typedefs

typedef struct Point * | pPoint

Functions

void | LCD_Clear (uint16_t Color)
Clears the hole LCD.
void | LCD_ClearLine (uint8_t Line)
Clears the selected line.
void | LCD_ClosedPolyLine (pPoint Points, uint16_t PointCount)
Displays a closed polyline (between many points).
void | LCD_ClosedPolyLineRelative (pPoint Points, uint16_t PointCount)
Displays a closed relative polyline (between many points).
void | LCD_CtrlLinesConfig (void)
Configures LCD control lines in Output Push-Pull mode.
void | LCD_CtrlLinesWrite (GPIO_TypeDef *GPIOx, uint16_t CtrlPins, BitAction BitVal)
Sets or reset LCD control lines.
void | LCD_DeInit (void)
DeInitializes the LCD.
void | LCD_DisplayChar (uint8_t Line, uint16_t Column, uint8_t Ascii)
Displays one character (16dots width, 24dots height).
void | LCD_DisplayOff (void)
Disables the Display.
void | LCD_DisplayOn (void)
Enables the Display.
void | LCD_DisplayStringLine (uint8_t Line, uint8_t *ptr)
Displays a maximum of 20 char on the LCD.
void | LCD_DrawChar (uint8_t Xpos, uint16_t Ypos, const uint16_t *c)
Draws a character on LCD.
void | LCD_DrawCircle (uint8_t Xpos, uint16_t Ypos, uint16_t Radius)
Displays a circle.
void | LCD_DrawFullCircle (uint16_t Xpos, uint16_t Ypos, uint16_t Radius)
Displays a full circle.
void | LCD_DrawFullRect (uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height)
Displays a full rectangle.
void | LCD_DrawLine (uint8_t Xpos, uint16_t Ypos, uint16_t Length, uint8_t Direction)
Displays a line.
void | LCD_DrawMonoPict (const uint32_t *Pict)
Displays a monocolor picture.
void | LCD_DrawRect (uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width)
Displays a rectangle.
void | LCD_DrawUniLine (uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2)
Displays an uni line (between two points).
void | LCD_FillPolyLine (pPoint Points, uint16_t PointCount)
Displays a full polyline (between many points).
void | LCD_GetColors (__IO uint16_t *_TextColor, __IO uint16_t *_BackColor)
Gets the LCD Text and Background colors.
sFONT * | LCD_GetFont (void)
Gets the Text Font.
void | LCD_nCS_StartByte (uint8_t Start_Byte)
Reset LCD control line(/CS) and Send Start-Byte.
void | LCD_PolyLine (pPoint Points, uint16_t PointCount)
Displays an polyline (between many points).
void | LCD_PolyLineRelative (pPoint Points, uint16_t PointCount)
Displays a relative polyline (between many points).
void | LCD_PowerOn (void)
Power on the LCD.
uint16_t | LCD_ReadReg (uint8_t LCD_Reg)
Reads the selected LCD Register.
void | LCD_SetBackColor (__IO uint16_t Color)
Sets the Background color.
void | LCD_SetColors (__IO uint16_t _TextColor, __IO uint16_t _BackColor)
Sets the LCD Text and Background colors.
void | LCD_SetCursor (uint8_t Xpos, uint16_t Ypos)
Sets the cursor position.
void | LCD_SetDisplayWindow (uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width)
Sets a display window.
void | LCD_SetFont (sFONT *fonts)
Sets the Text Font.
void | LCD_SetTextColor (__IO uint16_t Color)
Sets the Text color.
void | LCD_Setup (void)
Setups the LCD.
void | LCD_SPIConfig (void)
Configures the LCD_SPI interface.
void | LCD_WindowModeDisable (void)
Disables LCD Window mode.
void | LCD_WriteRAM (uint16_t RGB_Code)
Writes to the LCD RAM.
void | LCD_WriteRAM_Prepare (void)
Prepare to write to the LCD RAM.
void | LCD_WriteRAMWord (uint16_t RGB_Code)
Writes 1 word to the LCD RAM.
void | LCD_WriteReg (uint8_t LCD_Reg, uint16_t LCD_RegValue)
Writes to the selected LCD register.
void | LCD_WriteRegIndex (uint8_t LCD_Reg)
Writes index to select the LCD register.
void | STM3210C_LCD_Init (void)
Initializes the LCD.

Detailed Description

This file contains all the functions prototypes for the lcd firmware driver.

Author:
MCD Application Team
Version:
V4.5.0
Date:
07-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm3210c_eval_lcd.h.


STM32F10x Standard Peripherals Firmware Library: stm3210e_eval.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • STM3210E_EVAL
Functions | Variables

stm3210e_eval.c File Reference

This file provides

  • set of firmware functions to manage Leds, push-button and COM ports
  • low level initialization functions for SD card (on SDIO), SPI serial flash (sFLASH) and temperature sensor (LM75) available on STM3210E-EVAL evaluation board from STMicroelectronics.
More...

#include "stm3210e_eval.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_dma.h"

Go to the source code of this file.

Functions

void | LM75_LowLevel_DeInit (void)
DeInitializes the LM75_I2C.
void | LM75_LowLevel_Init (void)
Initializes the LM75_I2C.
uint32_t | SD_DMAEndOfTransferStatus (void)
Returns the DMA End Of Transfer Status.
void | SD_LowLevel_DeInit (void)
DeInitializes the SDIO interface.
void | SD_LowLevel_DMA_RxConfig (uint32_t *BufferDST, uint32_t BufferSize)
Configures the DMA2 Channel4 for SDIO Rx request.
void | SD_LowLevel_DMA_TxConfig (uint32_t *BufferSRC, uint32_t BufferSize)
Configures the DMA2 Channel4 for SDIO Tx request.
void | SD_LowLevel_Init (void)
Initializes the SD Card and put it into StandBy State (Ready for data transfer).
void | sFLASH_LowLevel_DeInit (void)
DeInitializes the peripherals used by the SPI FLASH driver.
void | sFLASH_LowLevel_Init (void)
Initializes the peripherals used by the SPI FLASH driver.
void | STM_EVAL_COMInit (COM_TypeDef COM, USART_InitTypeDef *USART_InitStruct)
Configures COM port.
void | STM_EVAL_LEDInit (Led_TypeDef Led)
Configures LED GPIO.
void | STM_EVAL_LEDOff (Led_TypeDef Led)
Turns selected LED Off.
void | STM_EVAL_LEDOn (Led_TypeDef Led)
Turns selected LED On.
void | STM_EVAL_LEDToggle (Led_TypeDef Led)
Toggles the selected LED.
uint32_t | STM_EVAL_PBGetState (Button_TypeDef Button)
Returns the selected Button state.
void | STM_EVAL_PBInit (Button_TypeDef Button, ButtonMode_TypeDef Button_Mode)
Configures Button GPIO and EXTI Line.

Variables

const uint32_t | BUTTON_CLK [BUTTONn]
const uint16_t | BUTTON_EXTI_LINE [BUTTONn]
const uint16_t | BUTTON_IRQn [BUTTONn]
const uint16_t | BUTTON_PIN [BUTTONn]
const uint16_t | BUTTON_PIN_SOURCE [BUTTONn]
GPIO_TypeDef * | BUTTON_PORT [BUTTONn]
const uint16_t | BUTTON_PORT_SOURCE [BUTTONn]
const uint16_t | COM_RX_PIN [COMn] = {EVAL_COM1_RX_PIN, EVAL_COM2_RX_PIN}
GPIO_TypeDef * | COM_RX_PORT [COMn] = {EVAL_COM1_RX_GPIO_PORT, EVAL_COM2_RX_GPIO_PORT}
const uint32_t | COM_RX_PORT_CLK [COMn] = {EVAL_COM1_RX_GPIO_CLK, EVAL_COM2_RX_GPIO_CLK}
const uint16_t | COM_TX_PIN [COMn] = {EVAL_COM1_TX_PIN, EVAL_COM2_TX_PIN}
GPIO_TypeDef * | COM_TX_PORT [COMn] = {EVAL_COM1_TX_GPIO_PORT, EVAL_COM2_TX_GPIO_PORT}
const uint32_t | COM_TX_PORT_CLK [COMn] = {EVAL_COM1_TX_GPIO_CLK, EVAL_COM2_TX_GPIO_CLK}
USART_TypeDef * | COM_USART [COMn] = {EVAL_COM1, EVAL_COM2}
const uint32_t | COM_USART_CLK [COMn] = {EVAL_COM1_CLK, EVAL_COM2_CLK}
const uint32_t | GPIO_CLK [LEDn]
const uint16_t | GPIO_PIN [LEDn]
GPIO_TypeDef * | GPIO_PORT [LEDn]

Detailed Description

This file provides

  • set of firmware functions to manage Leds, push-button and COM ports
  • low level initialization functions for SD card (on SDIO), SPI serial flash (sFLASH) and temperature sensor (LM75) available on STM3210E-EVAL evaluation board from STMicroelectronics.
Author:
MCD Application Team
Version:
V4.5.0
Date:
07-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm3210e_eval.c.


STM32F10x Standard Peripherals Firmware Library: stm3210e_eval.h File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • STM3210E_EVAL
Defines | Functions

stm3210e_eval.h File Reference

This file contains definitions for STM3210E_EVAL's Leds, push-buttons COM ports, sFLASH (on SPI) and Temperature Sensor LM75 (on I2C) hardware resources. More...

#include "stm32_eval.h"

Go to the source code of this file.

Defines

#define | BUTTONn 8
#define | COMn 2
#define | DOWN_BUTTON_EXTI_IRQn EXTI3_IRQn
#define | DOWN_BUTTON_EXTI_LINE EXTI_Line3
#define | DOWN_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource3
#define | DOWN_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOD
#define | DOWN_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOD
#define | DOWN_BUTTON_GPIO_PORT GPIOD
#define | DOWN_BUTTON_PIN GPIO_Pin_3
Joystick Down push-button.
#define | EVAL_COM1 USART1
Definition for COM port1, connected to USART1.
#define | EVAL_COM1_CLK RCC_APB2Periph_USART1
#define | EVAL_COM1_IRQn USART1_IRQn
#define | EVAL_COM1_RX_GPIO_CLK RCC_APB2Periph_GPIOA
#define | EVAL_COM1_RX_GPIO_PORT GPIOA
#define | EVAL_COM1_RX_PIN GPIO_Pin_10
#define | EVAL_COM1_TX_GPIO_CLK RCC_APB2Periph_GPIOA
#define | EVAL_COM1_TX_GPIO_PORT GPIOA
#define | EVAL_COM1_TX_PIN GPIO_Pin_9
#define | EVAL_COM2 USART2
Definition for COM port2, connected to USART2.
#define | EVAL_COM2_CLK RCC_APB1Periph_USART2
#define | EVAL_COM2_IRQn USART2_IRQn
#define | EVAL_COM2_RX_GPIO_CLK RCC_APB2Periph_GPIOA
#define | EVAL_COM2_RX_GPIO_PORT GPIOA
#define | EVAL_COM2_RX_PIN GPIO_Pin_3
#define | EVAL_COM2_TX_GPIO_CLK RCC_APB2Periph_GPIOA
#define | EVAL_COM2_TX_GPIO_PORT GPIOA
#define | EVAL_COM2_TX_PIN GPIO_Pin_2
#define | KEY_BUTTON_EXTI_IRQn EXTI9_5_IRQn
#define | KEY_BUTTON_EXTI_LINE EXTI_Line8
#define | KEY_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource8
#define | KEY_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOG
#define | KEY_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOG
#define | KEY_BUTTON_GPIO_PORT GPIOG
#define | KEY_BUTTON_PIN GPIO_Pin_8
Key push-button.
#define | LED1_GPIO_CLK RCC_APB2Periph_GPIOF
#define | LED1_GPIO_PORT GPIOF
#define | LED1_PIN GPIO_Pin_6
#define | LED2_GPIO_CLK RCC_APB2Periph_GPIOF
#define | LED2_GPIO_PORT GPIOF
#define | LED2_PIN GPIO_Pin_7
#define | LED3_GPIO_CLK RCC_APB2Periph_GPIOF
#define | LED3_GPIO_PORT GPIOF
#define | LED3_PIN GPIO_Pin_8
#define | LED4_GPIO_CLK RCC_APB2Periph_GPIOF
#define | LED4_GPIO_PORT GPIOF
#define | LED4_PIN GPIO_Pin_9
#define | LEDn 4
#define | LEFT_BUTTON_EXTI_IRQn EXTI15_10_IRQn
#define | LEFT_BUTTON_EXTI_LINE EXTI_Line14
#define | LEFT_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource14
#define | LEFT_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOG
#define | LEFT_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOG
#define | LEFT_BUTTON_GPIO_PORT GPIOG
#define | LEFT_BUTTON_PIN GPIO_Pin_14
Joystick Left push-button.
#define | LM75_DMA_CLK RCC_AHBPeriph_DMA1
#define | LM75_DMA_RX_CHANNEL DMA1_Channel7
#define | LM75_DMA_RX_TCFLAG DMA1_FLAG_TC7
#define | LM75_DMA_TX_CHANNEL DMA1_Channel6
#define | LM75_DMA_TX_TCFLAG DMA1_FLAG_TC6
#define | LM75_I2C I2C1
LM75 Temperature Sensor I2C Interface pins.
#define | LM75_I2C_CLK RCC_APB1Periph_I2C1
#define | LM75_I2C_DR ((uint32_t)0x40005410)
#define | LM75_I2C_SCL_GPIO_CLK RCC_APB2Periph_GPIOB
#define | LM75_I2C_SCL_GPIO_PORT GPIOB
#define | LM75_I2C_SCL_PIN GPIO_Pin_6
#define | LM75_I2C_SDA_GPIO_CLK RCC_APB2Periph_GPIOB
#define | LM75_I2C_SDA_GPIO_PORT GPIOB
#define | LM75_I2C_SDA_PIN GPIO_Pin_7
#define | LM75_I2C_SMBUSALERT_GPIO_CLK RCC_APB2Periph_GPIOB
#define | LM75_I2C_SMBUSALERT_GPIO_PORT GPIOB
#define | LM75_I2C_SMBUSALERT_PIN GPIO_Pin_5
#define | RIGHT_BUTTON_EXTI_IRQn EXTI15_10_IRQn
#define | RIGHT_BUTTON_EXTI_LINE EXTI_Line13
#define | RIGHT_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource13
#define | RIGHT_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOG
#define | RIGHT_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOG
#define | RIGHT_BUTTON_GPIO_PORT GPIOG
#define | RIGHT_BUTTON_PIN GPIO_Pin_13
Joystick Right push-button.
#define | SD_DETECT_GPIO_CLK RCC_APB2Periph_GPIOF
#define | SD_DETECT_GPIO_PORT GPIOF
#define | SD_DETECT_PIN GPIO_Pin_11
SD FLASH SDIO Interface.
#define | SDIO_FIFO_ADDRESS ((uint32_t)0x40018080)
#define | SDIO_INIT_CLK_DIV ((uint8_t)0xB2)
SDIO Intialization Frequency (400KHz max)
#define | SDIO_TRANSFER_CLK_DIV ((uint8_t)0x00)
SDIO Data Transfer Frequency (25MHz max)
#define | SEL_BUTTON_EXTI_IRQn EXTI9_5_IRQn
#define | SEL_BUTTON_EXTI_LINE EXTI_Line7
#define | SEL_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource7
#define | SEL_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOG
#define | SEL_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOG
#define | SEL_BUTTON_GPIO_PORT GPIOG
#define | SEL_BUTTON_PIN GPIO_Pin_7
Joystick Sel push-button.
#define | sFLASH_CS_GPIO_CLK RCC_APB2Periph_GPIOB
#define | sFLASH_CS_GPIO_PORT GPIOB
#define | sFLASH_CS_PIN GPIO_Pin_2
#define | sFLASH_SPI SPI1
M25P FLASH SPI Interface pins.
#define | sFLASH_SPI_CLK RCC_APB2Periph_SPI1
#define | sFLASH_SPI_MISO_GPIO_CLK RCC_APB2Periph_GPIOA
#define | sFLASH_SPI_MISO_GPIO_PORT GPIOA
#define | sFLASH_SPI_MISO_PIN GPIO_Pin_6
#define | sFLASH_SPI_MOSI_GPIO_CLK RCC_APB2Periph_GPIOA
#define | sFLASH_SPI_MOSI_GPIO_PORT GPIOA
#define | sFLASH_SPI_MOSI_PIN GPIO_Pin_7
#define | sFLASH_SPI_SCK_GPIO_CLK RCC_APB2Periph_GPIOA
#define | sFLASH_SPI_SCK_GPIO_PORT GPIOA
#define | sFLASH_SPI_SCK_PIN GPIO_Pin_5
#define | TAMPER_BUTTON_EXTI_IRQn EXTI15_10_IRQn
#define | TAMPER_BUTTON_EXTI_LINE EXTI_Line13
#define | TAMPER_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource13
#define | TAMPER_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOC
#define | TAMPER_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOC
#define | TAMPER_BUTTON_GPIO_PORT GPIOC
#define | TAMPER_BUTTON_PIN GPIO_Pin_13
Tamper push-button.
#define | UP_BUTTON_EXTI_IRQn EXTI15_10_IRQn
#define | UP_BUTTON_EXTI_LINE EXTI_Line15
#define | UP_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource15
#define | UP_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOG
#define | UP_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOG
#define | UP_BUTTON_GPIO_PORT GPIOG
#define | UP_BUTTON_PIN GPIO_Pin_15
Joystick Up push-button.
#define | WAKEUP_BUTTON_EXTI_IRQn EXTI0_IRQn
#define | WAKEUP_BUTTON_EXTI_LINE EXTI_Line0
#define | WAKEUP_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource0
#define | WAKEUP_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOA
#define | WAKEUP_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOA
#define | WAKEUP_BUTTON_GPIO_PORT GPIOA
#define | WAKEUP_BUTTON_PIN GPIO_Pin_0
Wakeup push-button.

Functions

void | LM75_LowLevel_DeInit (void)
DeInitializes the LM75_I2C.
void | LM75_LowLevel_Init (void)
Initializes the LM75_I2C.
uint32_t | SD_DMAEndOfTransferStatus (void)
Returns the DMA End Of Transfer Status.
void | SD_LowLevel_DeInit (void)
DeInitializes the SD/SD communication.
void | SD_LowLevel_DMA_RxConfig (uint32_t *BufferDST, uint32_t BufferSize)
Configures the DMA2 Channel4 for SDIO Rx request.
void | SD_LowLevel_DMA_TxConfig (uint32_t *BufferSRC, uint32_t BufferSize)
Configures the DMA2 Channel4 for SDIO Tx request.
void | SD_LowLevel_Init (void)
Initializes the SD_SPI and CS pins.
void | sFLASH_LowLevel_DeInit (void)
DeInitializes the peripherals used by the SPI FLASH driver.
void | sFLASH_LowLevel_Init (void)
Initializes the peripherals used by the SPI FLASH driver.
void | STM_EVAL_COMInit (COM_TypeDef COM, USART_InitTypeDef *USART_InitStruct)
Configures COM port.
void | STM_EVAL_LEDInit (Led_TypeDef Led)
Configures LED GPIO.
void | STM_EVAL_LEDOff (Led_TypeDef Led)
Turns selected LED Off.
void | STM_EVAL_LEDOn (Led_TypeDef Led)
Turns selected LED On.
void | STM_EVAL_LEDToggle (Led_TypeDef Led)
Toggles the selected LED.
uint32_t | STM_EVAL_PBGetState (Button_TypeDef Button)
Returns the selected Button state.
void | STM_EVAL_PBInit (Button_TypeDef Button, ButtonMode_TypeDef Button_Mode)
Configures Button GPIO and EXTI Line.

Detailed Description

This file contains definitions for STM3210E_EVAL's Leds, push-buttons COM ports, sFLASH (on SPI) and Temperature Sensor LM75 (on I2C) hardware resources.

Author:
MCD Application Team
Version:
V4.5.0
Date:
07-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm3210e_eval.h.


STM32F10x Standard Peripherals Firmware Library: stm3210e_eval_fsmc_nand.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • STM3210E_EVAL
Defines | Functions

stm3210e_eval_fsmc_nand.c File Reference

This file provides a set of functions needed to drive the NAND512W3A2 memory mounted on STM3210E-EVAL board. More...

#include "stm3210e_eval_fsmc_nand.h"

Go to the source code of this file.

Defines

#define | Bank2_NAND_ADDR ((uint32_t)0x70000000)
#define | Bank_NAND_ADDR Bank2_NAND_ADDR
#define | FSMC_Bank_NAND FSMC_Bank2_NAND
FSMC Bank 2.
#define | ROW_ADDRESS (Address.Page + (Address.Block + (Address.Zone * NAND_ZONE_SIZE)) * NAND_BLOCK_SIZE)

Functions

uint32_t | NAND_AddressIncrement (NAND_ADDRESS *Address)
Increment the NAND memory address.
uint32_t | NAND_EraseBlock (NAND_ADDRESS Address)
This routine erase complete block from NAND FLASH.
uint32_t | NAND_GetStatus (void)
Get the NAND operation status.
void | NAND_Init (void)
Configures the FSMC and GPIOs to interface with the NAND memory.
void | NAND_ReadID (NAND_IDTypeDef *NAND_ID)
Reads NAND memory's ID.
uint32_t | NAND_ReadSmallPage (uint8_t *pBuffer, NAND_ADDRESS Address, uint32_t NumPageToRead)
This routine is for sequential read from one or several 512 Bytes Page size.
uint32_t | NAND_ReadSpareArea (uint8_t *pBuffer, NAND_ADDRESS Address, uint32_t NumSpareAreaToRead)
This routine read the spare area information from the specified pages addresses.
uint32_t | NAND_ReadStatus (void)
Reads the NAND memory status using the Read status command.
uint32_t | NAND_Reset (void)
This routine reset the NAND FLASH.
uint32_t | NAND_WriteSmallPage (uint8_t *pBuffer, NAND_ADDRESS Address, uint32_t NumPageToWrite)
This routine is for writing one or several 512 Bytes Page size.
uint32_t | NAND_WriteSpareArea (uint8_t *pBuffer, NAND_ADDRESS Address, uint32_t NumSpareAreaTowrite)
This routine write the spare area information for the specified pages addresses.

Detailed Description

This file provides a set of functions needed to drive the NAND512W3A2 memory mounted on STM3210E-EVAL board.

Author:
MCD Application Team
Version:
V4.5.0
Date:
07-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm3210e_eval_fsmc_nand.c.


STM32F10x Standard Peripherals Firmware Library: stm3210e_eval_fsmc_nand.h File Reference

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
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Data Structures | Defines | Functions

stm3210e_eval_fsmc_nand.h File Reference

This file contains all the functions prototypes for the stm3210e_eval_fsmc_nand firmware driver. More...

#include "stm32f10x.h"

Go to the source code of this file.

Data Structures

struct | NAND_ADDRESS
struct | NAND_IDTypeDef

Defines

#define | ADDR_1st_CYCLE(ADDR) (uint8_t)((ADDR)& 0xFF)
FSMC NAND memory address computation.
#define | ADDR_2nd_CYCLE(ADDR) (uint8_t)(((ADDR)& 0xFF00) >> 8)
#define | ADDR_3rd_CYCLE(ADDR) (uint8_t)(((ADDR)& 0xFF0000) >> 16)
#define | ADDR_4th_CYCLE(ADDR) (uint8_t)(((ADDR)& 0xFF000000) >> 24)
#define | ADDR_AREA (uint32_t)(1<<17)
#define | CMD_AREA (uint32_t)(1<<16)
NAND Area definition for STM3210E-EVAL Board RevD.
#define | DATA_AREA ((uint32_t)0x00000000)
#define | NAND_BLOCK_SIZE ((uint16_t)0x0020)
#define | NAND_BUSY ((uint32_t)0x00000000)
#define | NAND_CMD_AREA_A ((uint8_t)0x00)
FSMC NAND memory command.
#define | NAND_CMD_AREA_B ((uint8_t)0x01)
#define | NAND_CMD_AREA_C ((uint8_t)0x50)
#define | NAND_CMD_ERASE0 ((uint8_t)0x60)
#define | NAND_CMD_ERASE1 ((uint8_t)0xD0)
#define | NAND_CMD_LOCK_STATUS ((uint8_t)0x7A)
#define | NAND_CMD_READID ((uint8_t)0x90)
#define | NAND_CMD_RESET ((uint8_t)0xFF)
#define | NAND_CMD_STATUS ((uint8_t)0x70)
#define | NAND_CMD_WRITE0 ((uint8_t)0x80)
#define | NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10)
#define | NAND_ERROR ((uint32_t)0x00000001)
#define | NAND_INVALID_ADDRESS ((uint32_t)0x00000200)
#define | NAND_MAX_ZONE ((uint16_t)0x0004)
#define | NAND_PAGE_SIZE ((uint16_t)0x0200)
FSMC NAND memory parameters.
#define | NAND_READY ((uint32_t)0x00000040)
#define | NAND_SPARE_AREA_SIZE ((uint16_t)0x0010)
#define | NAND_TIMEOUT_ERROR ((uint32_t)0x00000400)
#define | NAND_VALID_ADDRESS ((uint32_t)0x00000100)
NAND memory status.
#define | NAND_ZONE_SIZE ((uint16_t)0x0400)

Functions

uint32_t | NAND_AddressIncrement (NAND_ADDRESS *Address)
Increment the NAND memory address.
uint32_t | NAND_EraseBlock (NAND_ADDRESS Address)
This routine erase complete block from NAND FLASH.
uint32_t | NAND_GetStatus (void)
Get the NAND operation status.
void | NAND_Init (void)
Configures the FSMC and GPIOs to interface with the NAND memory.
void | NAND_ReadID (NAND_IDTypeDef *NAND_ID)
Reads NAND memory's ID.
uint32_t | NAND_ReadSmallPage (uint8_t *pBuffer, NAND_ADDRESS Address, uint32_t NumPageToRead)
This routine is for sequential read from one or several 512 Bytes Page size.
uint32_t | NAND_ReadSpareArea (uint8_t *pBuffer, NAND_ADDRESS Address, uint32_t NumSpareAreaToRead)
This routine read the spare area information from the specified pages addresses.
uint32_t | NAND_ReadStatus (void)
Reads the NAND memory status using the Read status command.
uint32_t | NAND_Reset (void)
This routine reset the NAND FLASH.
uint32_t | NAND_WriteSmallPage (uint8_t *pBuffer, NAND_ADDRESS Address, uint32_t NumPageToWrite)
This routine is for writing one or several 512 Bytes Page size.
uint32_t | NAND_WriteSpareArea (uint8_t *pBuffer, NAND_ADDRESS Address, uint32_t NumSpareAreaTowrite)
This routine write the spare area information for the specified pages addresses.

Detailed Description

This file contains all the functions prototypes for the stm3210e_eval_fsmc_nand firmware driver.

Author:
MCD Application Team
Version:
V4.5.0
Date:
07-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm3210e_eval_fsmc_nand.h.


STM32F10x Standard Peripherals Firmware Library: stm3210e_eval_fsmc_nor.c File Reference

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  • STM32F10x_StdPeriph_Lib_V3.5.0
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Defines | Functions

stm3210e_eval_fsmc_nor.c File Reference

This file provides a set of functions needed to drive the M29W128FL, M29W128GL and S29GL128P NOR memories mounted on STM3210E-EVAL board. More...

#include "stm3210e_eval_fsmc_nor.h"

Go to the source code of this file.

Defines

#define | ADDR_SHIFT(A) (Bank1_NOR2_ADDR + (2 * (A)))
#define | Bank1_NOR2_ADDR ((uint32_t)0x64000000)
FSMC Bank 1 NOR/SRAM2.
#define | BlockErase_Timeout ((uint32_t)0x00A00000)
#define | ChipErase_Timeout ((uint32_t)0x30000000)
#define | NOR_WRITE(Address, Data) (*(__IO uint16_t *)(Address) = (Data))
#define | Program_Timeout ((uint32_t)0x00001400)

Functions

NOR_Status | NOR_EraseBlock (uint32_t BlockAddr)
Erases the specified Nor memory block.
NOR_Status | NOR_EraseChip (void)
Erases the entire chip.
NOR_Status | NOR_GetStatus (uint32_t Timeout)
Returns the NOR operation status.
void | NOR_Init (void)
Configures the FSMC and GPIOs to interface with the NOR memory.
NOR_Status | NOR_ProgramBuffer (uint16_t *pBuffer, uint32_t WriteAddr, uint32_t NumHalfwordToWrite)
Writes a half-word buffer to the FSMC NOR memory.
void | NOR_ReadBuffer (uint16_t *pBuffer, uint32_t ReadAddr, uint32_t NumHalfwordToRead)
Reads a block of data from the FSMC NOR memory.
uint16_t | NOR_ReadHalfWord (uint32_t ReadAddr)
Reads a half-word from the NOR memory.
void | NOR_ReadID (NOR_IDTypeDef *NOR_ID)
Reads NOR memory's Manufacturer and Device Code.
NOR_Status | NOR_Reset (void)
Returns the NOR memory to Read mode and resets the errors in the NOR memory Status Register.
NOR_Status | NOR_ReturnToReadMode (void)
Returns the NOR memory to Read mode.
NOR_Status | NOR_WriteBuffer (uint16_t *pBuffer, uint32_t WriteAddr, uint32_t NumHalfwordToWrite)
Writes a half-word buffer to the FSMC NOR memory.
NOR_Status | NOR_WriteHalfWord (uint32_t WriteAddr, uint16_t Data)
Writes a half-word to the NOR memory.

Detailed Description

This file provides a set of functions needed to drive the M29W128FL, M29W128GL and S29GL128P NOR memories mounted on STM3210E-EVAL board.

Author:
MCD Application Team
Version:
V4.5.0
Date:
07-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm3210e_eval_fsmc_nor.c.


STM32F10x Standard Peripherals Firmware Library: stm3210e_eval_fsmc_nor.h File Reference

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
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  • STM3210E_EVAL
Data Structures | Enumerations | Functions

stm3210e_eval_fsmc_nor.h File Reference

This file contains all the functions prototypes for the stm3210e_eval_fsmc_nor firmware driver. More...

#include "stm32f10x.h"

Go to the source code of this file.

Data Structures

struct | NOR_IDTypeDef

Enumerations

enum | NOR_Status { NOR_SUCCESS = 0, NOR_ONGOING, NOR_ERROR, NOR_TIMEOUT }

Functions

NOR_Status | NOR_EraseBlock (uint32_t BlockAddr)
Erases the specified Nor memory block.
NOR_Status | NOR_EraseChip (void)
Erases the entire chip.
NOR_Status | NOR_GetStatus (uint32_t Timeout)
Returns the NOR operation status.
void | NOR_Init (void)
Configures the FSMC and GPIOs to interface with the NOR memory.
NOR_Status | NOR_ProgramBuffer (uint16_t *pBuffer, uint32_t WriteAddr, uint32_t NumHalfwordToWrite)
Writes a half-word buffer to the FSMC NOR memory.
void | NOR_ReadBuffer (uint16_t *pBuffer, uint32_t ReadAddr, uint32_t NumHalfwordToRead)
Reads a block of data from the FSMC NOR memory.
uint16_t | NOR_ReadHalfWord (uint32_t ReadAddr)
Reads a half-word from the NOR memory.
void | NOR_ReadID (NOR_IDTypeDef *NOR_ID)
Reads NOR memory's Manufacturer and Device Code.
NOR_Status | NOR_Reset (void)
Returns the NOR memory to Read mode and resets the errors in the NOR memory Status Register.
NOR_Status | NOR_ReturnToReadMode (void)
Returns the NOR memory to Read mode.
NOR_Status | NOR_WriteBuffer (uint16_t *pBuffer, uint32_t WriteAddr, uint32_t NumHalfwordToWrite)
Writes a half-word buffer to the FSMC NOR memory.
NOR_Status | NOR_WriteHalfWord (uint32_t WriteAddr, uint16_t Data)
Writes a half-word to the NOR memory.

Detailed Description

This file contains all the functions prototypes for the stm3210e_eval_fsmc_nor firmware driver.

Author:
MCD Application Team
Version:
V4.5.0
Date:
07-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm3210e_eval_fsmc_nor.h.


STM32F10x Standard Peripherals Firmware Library: stm3210e_eval_fsmc_sram.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • STM3210E_EVAL
Defines | Functions

stm3210e_eval_fsmc_sram.c File Reference

This file provides a set of functions needed to drive the IS61WV51216BLL SRAM memory mounted on STM3210E-EVAL board. More...

#include "stm3210e_eval_fsmc_sram.h"

Go to the source code of this file.

Defines

#define | Bank1_SRAM3_ADDR ((uint32_t)0x68000000)
FSMC Bank 1 NOR/SRAM3.

Functions

void | SRAM_Init (void)
Configures the FSMC and GPIOs to interface with the SRAM memory.
void | SRAM_ReadBuffer (uint16_t *pBuffer, uint32_t ReadAddr, uint32_t NumHalfwordToRead)
Reads a block of data from the FSMC SRAM memory.
void | SRAM_WriteBuffer (uint16_t *pBuffer, uint32_t WriteAddr, uint32_t NumHalfwordToWrite)
Writes a Half-word buffer to the FSMC SRAM memory.

Detailed Description

This file provides a set of functions needed to drive the IS61WV51216BLL SRAM memory mounted on STM3210E-EVAL board.

Author:
MCD Application Team
Version:
V4.5.0
Date:
07-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm3210e_eval_fsmc_sram.c.


STM32F10x Standard Peripherals Firmware Library: stm3210e_eval_fsmc_sram.h File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • STM3210E_EVAL
Functions

stm3210e_eval_fsmc_sram.h File Reference

This file contains all the functions prototypes for the stm3210e_eval_fsmc_sram firmware driver. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | SRAM_Init (void)
Configures the FSMC and GPIOs to interface with the SRAM memory.
void | SRAM_ReadBuffer (uint16_t *pBuffer, uint32_t ReadAddr, uint32_t NumHalfwordToRead)
Reads a block of data from the FSMC SRAM memory.
void | SRAM_WriteBuffer (uint16_t *pBuffer, uint32_t WriteAddr, uint32_t NumHalfwordToWrite)
Writes a Half-word buffer to the FSMC SRAM memory.

Detailed Description

This file contains all the functions prototypes for the stm3210e_eval_fsmc_sram firmware driver.

Author:
MCD Application Team
Version:
V4.5.0
Date:
07-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm3210e_eval_fsmc_sram.h.


STM32F10x Standard Peripherals Firmware Library: stm3210e_eval_lcd.c File Reference

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
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  • STM3210E_EVAL
Data Structures | Defines | Functions | Variables

stm3210e_eval_lcd.c File Reference

This file includes the LCD driver for AM-240320L8TNQW00H (LCD_ILI9320) and AM-240320LDTNQW00H (LCD_SPFD5408B) Liquid Crystal Display Module of STM3210E-EVAL board. More...

#include "stm3210e_eval_lcd.h"
#include "../Common/fonts.c"

Go to the source code of this file.

Data Structures

struct | LCD_TypeDef

Defines

#define | ABS(X) ((X) > 0 ? (X) : -(X))
#define | LCD ((LCD_TypeDef *) LCD_BASE)
#define | LCD_BASE ((uint32_t)(0x60000000 | 0x0C000000))
#define | MAX_POLY_CORNERS 200
#define | POLY_X(Z) ((int32_t)((Points + Z)->Y))
#define | POLY_Y(Z) ((int32_t)((Points + Z)->X))

Functions

static void | delay (vu32 nCount)
Inserts a delay time.
void | LCD_Clear (uint16_t Color)
Clears the hole LCD.
void | LCD_ClearLine (uint8_t Line)
Clears the selected line.
void | LCD_ClosedPolyLine (pPoint Points, uint16_t PointCount)
Displays a closed polyline (between many points).
void | LCD_ClosedPolyLineRelative (pPoint Points, uint16_t PointCount)
Displays a closed relative polyline (between many points).
void | LCD_CtrlLinesConfig (void)
Configures LCD Control lines (FSMC Pins) in alternate function mode.
void | LCD_DeInit (void)
DeInitializes the LCD.
void | LCD_DisplayChar (uint8_t Line, uint16_t Column, uint8_t Ascii)
Displays one character (16dots width, 24dots height).
void | LCD_DisplayOff (void)
Disables the Display.
void | LCD_DisplayOn (void)
Enables the Display.
void | LCD_DisplayStringLine (uint8_t Line, uint8_t *ptr)
Displays a maximum of 20 char on the LCD.
void | LCD_DrawChar (uint8_t Xpos, uint16_t Ypos, const uint16_t *c)
Draws a character on LCD.
void | LCD_DrawCircle (uint8_t Xpos, uint16_t Ypos, uint16_t Radius)
Displays a circle.
void | LCD_DrawFullCircle (uint16_t Xpos, uint16_t Ypos, uint16_t Radius)
Displays a full circle.
void | LCD_DrawFullRect (uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height)
Displays a full rectangle.
void | LCD_DrawLine (uint8_t Xpos, uint16_t Ypos, uint16_t Length, uint8_t Direction)
Displays a line.
void | LCD_DrawMonoPict (const uint32_t *Pict)
Displays a monocolor picture.
void | LCD_DrawRect (uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width)
Displays a rectangle.
void | LCD_DrawUniLine (uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2)
Displays an uni line (between two points).
void | LCD_FillPolyLine (pPoint Points, uint16_t PointCount)
Displays a full polyline (between many points).
void | LCD_FSMCConfig (void)
Configures the Parallel interface (FSMC) for LCD(Parallel mode)
void | LCD_GetColors (__IO uint16_t *_TextColor, __IO uint16_t *_BackColor)
Gets the LCD Text and Background colors.
sFONT * | LCD_GetFont (void)
Gets the Text Font.
void | LCD_PolyLine (pPoint Points, uint16_t PointCount)
Displays an polyline (between many points).
void | LCD_PolyLineRelative (pPoint Points, uint16_t PointCount)
Displays a relative polyline (between many points).
static void | LCD_PolyLineRelativeClosed (pPoint Points, uint16_t PointCount, uint16_t Closed)
Displays an relative polyline (between many points).
void | LCD_PowerOn (void)
Power on the LCD.
uint16_t | LCD_ReadRAM (void)
Reads the LCD RAM.
uint16_t | LCD_ReadReg (uint8_t LCD_Reg)
Reads the selected LCD Register.
void | LCD_SetBackColor (__IO uint16_t Color)
Sets the Background color.
void | LCD_SetColors (__IO uint16_t _TextColor, __IO uint16_t _BackColor)
Sets the LCD Text and Background colors.
void | LCD_SetCursor (uint8_t Xpos, uint16_t Ypos)
Sets the cursor position.
void | LCD_SetDisplayWindow (uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width)
Sets a display window.
void | LCD_SetFont (sFONT *fonts)
Sets the Text Font.
void | LCD_SetTextColor (__IO uint16_t Color)
Sets the Text color.
void | LCD_WindowModeDisable (void)
Disables LCD Window mode.
void | LCD_WriteBMP (uint32_t BmpAddress)
Displays a bitmap picture loaded in the internal Flash.
void | LCD_WriteRAM (uint16_t RGB_Code)
Writes to the LCD RAM.
void | LCD_WriteRAM_Prepare (void)
Prepare to write to the LCD RAM.
void | LCD_WriteReg (uint8_t LCD_Reg, uint16_t LCD_RegValue)
Writes to the selected LCD register.
static void | PutPixel (int16_t x, int16_t y)
Displays a pixel.
void | STM3210E_LCD_Init (void)
Initializes the LCD.

Variables

static __IO uint16_t | BackColor = 0xFFFF
static sFONT * | LCD_Currentfonts
static __IO uint16_t | TextColor = 0x0000

Detailed Description

This file includes the LCD driver for AM-240320L8TNQW00H (LCD_ILI9320) and AM-240320LDTNQW00H (LCD_SPFD5408B) Liquid Crystal Display Module of STM3210E-EVAL board.

Author:
MCD Application Team
Version:
V4.5.0
Date:
07-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm3210e_eval_lcd.c.


STM32F10x Standard Peripherals Firmware Library: stm3210e_eval_lcd.h File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • STM3210E_EVAL
Data Structures | Defines | Typedefs | Functions

stm3210e_eval_lcd.h File Reference

This file contains all the functions prototypes for the stm3210e_eval_lcd firmware driver. More...

#include "stm32f10x.h"
#include "../Common/fonts.h"

Go to the source code of this file.

Data Structures

struct | Point

Defines

#define | _delay_ delay
Uncomment the line below if you want to use user defined Delay function (for precise timing), otherwise default _delay_ function defined within this driver is used (less precise timing).
#define | ASSEMBLE_RGB(R, G, B) ((((R)& 0xF8) << 8) | (((G) & 0xFC) << 3) | (((B) & 0xF8) >> 3))
#define | LCD_COLOR_BLACK 0x0000
#define | LCD_COLOR_BLUE 0x001F
#define | LCD_COLOR_BLUE2 0x051F
#define | LCD_COLOR_CYAN 0x7FFF
#define | LCD_COLOR_GREEN 0x07E0
#define | LCD_COLOR_GREY 0xF7DE
#define | LCD_COLOR_MAGENTA 0xF81F
#define | LCD_COLOR_RED 0xF800
#define | LCD_COLOR_WHITE 0xFFFF
LCD color.
#define | LCD_COLOR_YELLOW 0xFFE0
#define | LCD_DEFAULT_FONT Font16x24
LCD default font.
#define | LCD_DIR_HORIZONTAL 0x0000
LCD Direction.
#define | LCD_DIR_VERTICAL 0x0001
#define | LCD_LINE_0 LINE(0)
LCD Lines depending on the chosen fonts.
#define | LCD_LINE_1 LINE(1)
#define | LCD_LINE_10 LINE(10)
#define | LCD_LINE_11 LINE(11)
#define | LCD_LINE_12 LINE(12)
#define | LCD_LINE_13 LINE(13)
#define | LCD_LINE_14 LINE(14)
#define | LCD_LINE_15 LINE(15)
#define | LCD_LINE_16 LINE(16)
#define | LCD_LINE_17 LINE(17)
#define | LCD_LINE_18 LINE(18)
#define | LCD_LINE_19 LINE(19)
#define | LCD_LINE_2 LINE(2)
#define | LCD_LINE_20 LINE(20)
#define | LCD_LINE_21 LINE(21)
#define | LCD_LINE_22 LINE(22)
#define | LCD_LINE_23 LINE(23)
#define | LCD_LINE_24 LINE(24)
#define | LCD_LINE_25 LINE(25)
#define | LCD_LINE_26 LINE(26)
#define | LCD_LINE_27 LINE(27)
#define | LCD_LINE_28 LINE(28)
#define | LCD_LINE_29 LINE(29)
#define | LCD_LINE_3 LINE(3)
#define | LCD_LINE_4 LINE(4)
#define | LCD_LINE_5 LINE(5)
#define | LCD_LINE_6 LINE(6)
#define | LCD_LINE_7 LINE(7)
#define | LCD_LINE_8 LINE(8)
#define | LCD_LINE_9 LINE(9)
#define | LCD_PIXEL_HEIGHT 0x00F0
#define | LCD_PIXEL_WIDTH 0x0140
LCD Size (Width and Height)
#define | LCD_REG_0 0x00
LCD Registers.
#define | LCD_REG_1 0x01
#define | LCD_REG_10 0x0A
#define | LCD_REG_106 0x6A
#define | LCD_REG_118 0x76
#define | LCD_REG_12 0x0C
#define | LCD_REG_128 0x80
#define | LCD_REG_129 0x81
#define | LCD_REG_13 0x0D
#define | LCD_REG_130 0x82
#define | LCD_REG_131 0x83
#define | LCD_REG_132 0x84
#define | LCD_REG_133 0x85
#define | LCD_REG_134 0x86
#define | LCD_REG_135 0x87
#define | LCD_REG_136 0x88
#define | LCD_REG_137 0x89
#define | LCD_REG_139 0x8B
#define | LCD_REG_14 0x0E
#define | LCD_REG_140 0x8C
#define | LCD_REG_141 0x8D
#define | LCD_REG_143 0x8F
#define | LCD_REG_144 0x90
#define | LCD_REG_145 0x91
#define | LCD_REG_146 0x92
#define | LCD_REG_147 0x93
#define | LCD_REG_148 0x94
#define | LCD_REG_149 0x95
#define | LCD_REG_15 0x0F
#define | LCD_REG_150 0x96
#define | LCD_REG_151 0x97
#define | LCD_REG_152 0x98
#define | LCD_REG_153 0x99
#define | LCD_REG_154 0x9A
#define | LCD_REG_157 0x9D
#define | LCD_REG_16 0x10
#define | LCD_REG_17 0x11
#define | LCD_REG_18 0x12
#define | LCD_REG_19 0x13
#define | LCD_REG_192 0xC0
#define | LCD_REG_193 0xC1
#define | LCD_REG_2 0x02
#define | LCD_REG_20 0x14
#define | LCD_REG_21 0x15
#define | LCD_REG_22 0x16
#define | LCD_REG_229 0xE5
#define | LCD_REG_23 0x17
#define | LCD_REG_24 0x18
#define | LCD_REG_25 0x19
#define | LCD_REG_26 0x1A
#define | LCD_REG_27 0x1B
#define | LCD_REG_28 0x1C
#define | LCD_REG_29 0x1D
#define | LCD_REG_3 0x03
#define | LCD_REG_30 0x1E
#define | LCD_REG_31 0x1F
#define | LCD_REG_32 0x20
#define | LCD_REG_33 0x21
#define | LCD_REG_34 0x22
#define | LCD_REG_36 0x24
#define | LCD_REG_37 0x25
#define | LCD_REG_4 0x04
#define | LCD_REG_40 0x28
#define | LCD_REG_41 0x29
#define | LCD_REG_43 0x2B
#define | LCD_REG_45 0x2D
#define | LCD_REG_48 0x30
#define | LCD_REG_49 0x31
#define | LCD_REG_5 0x05
#define | LCD_REG_50 0x32
#define | LCD_REG_51 0x33
#define | LCD_REG_52 0x34
#define | LCD_REG_53 0x35
#define | LCD_REG_54 0x36
#define | LCD_REG_55 0x37
#define | LCD_REG_56 0x38
#define | LCD_REG_57 0x39
#define | LCD_REG_58 0x3A
#define | LCD_REG_59 0x3B
#define | LCD_REG_6 0x06
#define | LCD_REG_60 0x3C
#define | LCD_REG_61 0x3D
#define | LCD_REG_62 0x3E
#define | LCD_REG_63 0x3F
#define | LCD_REG_64 0x40
#define | LCD_REG_65 0x41
#define | LCD_REG_66 0x42
#define | LCD_REG_67 0x43
#define | LCD_REG_68 0x44
#define | LCD_REG_69 0x45
#define | LCD_REG_7 0x07
#define | LCD_REG_70 0x46
#define | LCD_REG_71 0x47
#define | LCD_REG_72 0x48
#define | LCD_REG_73 0x49
#define | LCD_REG_74 0x4A
#define | LCD_REG_75 0x4B
#define | LCD_REG_76 0x4C
#define | LCD_REG_77 0x4D
#define | LCD_REG_78 0x4E
#define | LCD_REG_79 0x4F
#define | LCD_REG_8 0x08
#define | LCD_REG_80 0x50
#define | LCD_REG_81 0x51
#define | LCD_REG_82 0x52
#define | LCD_REG_83 0x53
#define | LCD_REG_9 0x09
#define | LCD_REG_96 0x60
#define | LCD_REG_97 0x61

Typedefs

typedef struct Point * | pPoint

Functions

void | LCD_Clear (uint16_t Color)
Clears the hole LCD.
void | LCD_ClearLine (uint8_t Line)
Clears the selected line.
void | LCD_ClosedPolyLine (pPoint Points, uint16_t PointCount)
Displays a closed polyline (between many points).
void | LCD_ClosedPolyLineRelative (pPoint Points, uint16_t PointCount)
Displays a closed relative polyline (between many points).
void | LCD_CtrlLinesConfig (void)
Configures LCD control lines in Output Push-Pull mode.
void | LCD_DeInit (void)
DeInitializes the LCD.
void | LCD_DisplayChar (uint8_t Line, uint16_t Column, uint8_t Ascii)
Displays one character (16dots width, 24dots height).
void | LCD_DisplayOff (void)
Disables the Display.
void | LCD_DisplayOn (void)
Enables the Display.
void | LCD_DisplayStringLine (uint8_t Line, uint8_t *ptr)
Displays a maximum of 20 char on the LCD.
void | LCD_DrawChar (uint8_t Xpos, uint16_t Ypos, const uint16_t *c)
Draws a character on LCD.
void | LCD_DrawCircle (uint8_t Xpos, uint16_t Ypos, uint16_t Radius)
Displays a circle.
void | LCD_DrawFullCircle (uint16_t Xpos, uint16_t Ypos, uint16_t Radius)
Displays a full circle.
void | LCD_DrawFullRect (uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height)
Displays a full rectangle.
void | LCD_DrawLine (uint8_t Xpos, uint16_t Ypos, uint16_t Length, uint8_t Direction)
Displays a line.
void | LCD_DrawMonoPict (const uint32_t *Pict)
Displays a monocolor picture.
void | LCD_DrawRect (uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width)
Displays a rectangle.
void | LCD_DrawUniLine (uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2)
Displays an uni line (between two points).
void | LCD_FillPolyLine (pPoint Points, uint16_t PointCount)
Displays a full polyline (between many points).
void | LCD_FSMCConfig (void)
Configures the Parallel interface (FSMC) for LCD(Parallel mode)
void | LCD_GetColors (__IO uint16_t *_TextColor, __IO uint16_t *_BackColor)
Gets the LCD Text and Background colors.
sFONT * | LCD_GetFont (void)
Gets the Text Font.
void | LCD_PolyLine (pPoint Points, uint16_t PointCount)
Displays an polyline (between many points).
void | LCD_PolyLineRelative (pPoint Points, uint16_t PointCount)
Displays a relative polyline (between many points).
void | LCD_PowerOn (void)
Power on the LCD.
uint16_t | LCD_ReadRAM (void)
Reads the LCD RAM.
uint16_t | LCD_ReadReg (uint8_t LCD_Reg)
Reads the selected LCD Register.
void | LCD_SetBackColor (__IO uint16_t Color)
Sets the Background color.
void | LCD_SetColors (__IO uint16_t _TextColor, __IO uint16_t _BackColor)
Sets the LCD Text and Background colors.
void | LCD_SetCursor (uint8_t Xpos, uint16_t Ypos)
Sets the cursor position.
void | LCD_SetDisplayWindow (uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width)
Sets a display window.
void | LCD_SetFont (sFONT *fonts)
Sets the Text Font.
void | LCD_SetTextColor (__IO uint16_t Color)
Sets the Text color.
void | LCD_WindowModeDisable (void)
Disables LCD Window mode.
void | LCD_WriteBMP (uint32_t BmpAddress)
Displays a bitmap picture loaded in the internal Flash.
void | LCD_WriteRAM (uint16_t RGB_Code)
Writes to the LCD RAM.
void | LCD_WriteRAM_Prepare (void)
Prepare to write to the LCD RAM.
void | LCD_WriteReg (uint8_t LCD_Reg, uint16_t LCD_RegValue)
Writes to the selected LCD register.
void | STM3210E_LCD_Init (void)
Initializes the LCD.

Detailed Description

This file contains all the functions prototypes for the stm3210e_eval_lcd firmware driver.

Author:
MCD Application Team
Version:
V4.5.0
Date:
07-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm3210e_eval_lcd.h.


STM32F10x Standard Peripherals Firmware Library: stm32_eval.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL

stm32_eval.c File Reference

STM32xx-EVAL abstraction layer. This file should be added to the main application to use the provided functions that manage Leds, push-buttons, COM ports and low level HW resources initialization of the different modules available on STM32 evaluation boards from STMicroelectronics. More...

#include "stm32_eval.h"

Go to the source code of this file.

Detailed Description

STM32xx-EVAL abstraction layer. This file should be added to the main application to use the provided functions that manage Leds, push-buttons, COM ports and low level HW resources initialization of the different modules available on STM32 evaluation boards from STMicroelectronics.

Author:
MCD Application Team
Version:
V4.5.0
Date:
07-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm32_eval.c.


STM32F10x Standard Peripherals Firmware Library: stm32_eval.h File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
Defines | Enumerations

stm32_eval.h File Reference

Header file for stm32_eval.c module. More...

Go to the source code of this file.

Defines

#define | Black LCD_COLOR_BLACK
#define | Blue LCD_COLOR_BLUE
#define | Blue2 LCD_COLOR_BLUE2
#define | Button_DOWN BUTTON_DOWN
#define | Button_KEY BUTTON_KEY
#define | Button_LEFT BUTTON_LEFT
#define | Button_Mode_TypeDef ButtonMode_TypeDef
#define | Button_RIGHT BUTTON_RIGHT
#define | Button_SEL BUTTON_SEL
#define | Button_TAMPER BUTTON_TAMPER
#define | Button_UP BUTTON_UP
#define | Button_WAKEUP BUTTON_WAKEUP
Uncomment the line corresponding to the STMicroelectronics evaluation board used in your application.
#define | Cyan LCD_COLOR_CYAN
#define | Green LCD_COLOR_GREEN
#define | Grey LCD_COLOR_GREY
#define | Horizontal LCD_DIR_HORIZONTAL
#define | JOY_CENTER JOY_SEL
#define | JOY_State_TypeDef JOYState_TypeDef
#define | LCD_RSNWR_GPIO_CLK LCD_NWR_GPIO_CLK
LCD Defines Legacy.
#define | LCD_SPI_GPIO_CLK LCD_SPI_SCK_GPIO_CLK
#define | LCD_SPI_GPIO_PORT LCD_SPI_SCK_GPIO_PORT
#define | Line0 LCD_LINE_0
#define | Line1 LCD_LINE_1
#define | Line2 LCD_LINE_2
#define | Line3 LCD_LINE_3
#define | Line4 LCD_LINE_4
#define | Line5 LCD_LINE_5
#define | Line6 LCD_LINE_6
#define | Line7 LCD_LINE_7
#define | Line8 LCD_LINE_8
#define | Line9 LCD_LINE_9
#define | Magenta LCD_COLOR_MAGENTA
#define | Mode_EXTI BUTTON_MODE_EXTI
#define | Mode_GPIO BUTTON_MODE_GPIO
#define | R0 LCD_REG_0
#define | R1 LCD_REG_1
#define | R10 LCD_REG_10
#define | R106 LCD_REG_106
#define | R118 LCD_REG_118
#define | R12 LCD_REG_12
#define | R128 LCD_REG_128
#define | R129 LCD_REG_129
#define | R13 LCD_REG_13
#define | R130 LCD_REG_130
#define | R131 LCD_REG_131
#define | R132 LCD_REG_132
#define | R133 LCD_REG_133
#define | R134 LCD_REG_134
#define | R135 LCD_REG_135
#define | R136 LCD_REG_136
#define | R137 LCD_REG_137
#define | R139 LCD_REG_139
#define | R14 LCD_REG_14
#define | R140 LCD_REG_140
#define | R141 LCD_REG_141
#define | R143 LCD_REG_143
#define | R144 LCD_REG_144
#define | R145 LCD_REG_145
#define | R146 LCD_REG_146
#define | R147 LCD_REG_147
#define | R148 LCD_REG_148
#define | R149 LCD_REG_149
#define | R15 LCD_REG_15
#define | R150 LCD_REG_150
#define | R151 LCD_REG_151
#define | R152 LCD_REG_152
#define | R153 LCD_REG_153
#define | R154 LCD_REG_154
#define | R157 LCD_REG_157
#define | R16 LCD_REG_16
#define | R17 LCD_REG_17
#define | R18 LCD_REG_18
#define | R19 LCD_REG_19
#define | R192 LCD_REG_192
#define | R193 LCD_REG_193
#define | R2 LCD_REG_2
#define | R20 LCD_REG_20
#define | R21 LCD_REG_21
#define | R22 LCD_REG_22
#define | R227 LCD_REG_227
#define | R229 LCD_REG_229
#define | R23 LCD_REG_23
#define | R231 LCD_REG_231
#define | R239 LCD_REG_239
#define | R24 LCD_REG_24
#define | R25 LCD_REG_25
#define | R26 LCD_REG_26
#define | R27 LCD_REG_27
#define | R28 LCD_REG_28
#define | R29 LCD_REG_29
#define | R3 LCD_REG_3
#define | R30 LCD_REG_30
#define | R31 LCD_REG_31
#define | R32 LCD_REG_32
#define | R33 LCD_REG_33
#define | R34 LCD_REG_34
#define | R36 LCD_REG_36
#define | R37 LCD_REG_37
#define | R4 LCD_REG_4
#define | R40 LCD_REG_40
#define | R41 LCD_REG_41
#define | R43 LCD_REG_43
#define | R45 LCD_REG_45
#define | R48 LCD_REG_48
#define | R49 LCD_REG_49
#define | R5 LCD_REG_5
#define | R50 LCD_REG_50
#define | R51 LCD_REG_51
#define | R52 LCD_REG_52
#define | R53 LCD_REG_53
#define | R54 LCD_REG_54
#define | R55 LCD_REG_55
#define | R56 LCD_REG_56
#define | R57 LCD_REG_57
#define | R59 LCD_REG_59
#define | R6 LCD_REG_6
#define | R60 LCD_REG_60
#define | R61 LCD_REG_61
#define | R62 LCD_REG_62
#define | R63 LCD_REG_63
#define | R64 LCD_REG_64
#define | R65 LCD_REG_65
#define | R66 LCD_REG_66
#define | R67 LCD_REG_67
#define | R68 LCD_REG_68
#define | R69 LCD_REG_69
#define | R7 LCD_REG_7
#define | R70 LCD_REG_70
#define | R71 LCD_REG_71
#define | R72 LCD_REG_72
#define | R73 LCD_REG_73
#define | R74 LCD_REG_74
#define | R75 LCD_REG_75
#define | R76 LCD_REG_76
#define | R77 LCD_REG_77
#define | R78 LCD_REG_78
#define | R79 LCD_REG_79
#define | R8 LCD_REG_8
#define | R80 LCD_REG_80
#define | R81 LCD_REG_81
#define | R82 LCD_REG_82
#define | R83 LCD_REG_83
#define | R9 LCD_REG_9
#define | R96 LCD_REG_96
#define | R97 LCD_REG_97
#define | Red LCD_COLOR_RED
#define | Vertical LCD_DIR_VERTICAL
#define | White LCD_COLOR_WHITE
#define | Yellow LCD_COLOR_YELLOW

Enumerations

enum Button_TypeDef {
BUTTON_WAKEUP = 0, BUTTON_TAMPER = 1, BUTTON_KEY = 2, BUTTON_RIGHT = 3,
BUTTON_LEFT = 4, BUTTON_UP = 5, BUTTON_DOWN = 6, BUTTON_SEL = 7
}
enum | ButtonMode_TypeDef { BUTTON_MODE_GPIO = 0, BUTTON_MODE_EXTI = 1 }
enum | COM_TypeDef { COM1 = 0, COM2 = 1 }
enum JOYState_TypeDef {
JOY_NONE = 0, JOY_SEL = 1, JOY_DOWN = 2, JOY_LEFT = 3,
JOY_RIGHT = 4, JOY_UP = 5, JOY_NONE = 0, JOY_SEL = 1,
JOY_DOWN = 2, JOY_LEFT = 3, JOY_RIGHT = 4, JOY_UP = 5
}
enum | Led_TypeDef { LED1 = 0, LED2 = 1, LED3 = 2, LED4 = 3 }

Detailed Description

Header file for stm32_eval.c module.

Author:
MCD Application Team
Version:
V4.5.0
Date:
07-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm32_eval.h.


STM32F10x Standard Peripherals Firmware Library: stm32_eval_i2c_ee.c File Reference

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • Common
Functions | Variables

stm32_eval_i2c_ee.c File Reference

This file provides a set of functions needed to manage the I2C M24CXX EEPROM memory mounted on STM32xx-EVAL board (refer to stm32_eval.h to know about the boards supporting this memory). More...

#include "stm32_eval_i2c_ee.h"

Go to the source code of this file.

Functions

void | sEE_DeInit (void)
DeInitializes peripherals used by the I2C EEPROM driver.
void | sEE_EnterCriticalSection_UserCallback (void)
Start critical section: these callbacks should be typically used to disable interrupts when entering a critical section of I2C communication You may use default callbacks provided into this driver by uncommenting the define USE_DEFAULT_CRITICAL_CALLBACK.
void | sEE_ExitCriticalSection_UserCallback (void)
Start and End of critical section: these callbacks should be typically used to re-enable interrupts when exiting a critical section of I2C communication You may use default callbacks provided into this driver by uncommenting the define USE_DEFAULT_CRITICAL_CALLBACK.
void | sEE_I2C_DMA_RX_IRQHandler (void)
This function handles the DMA Rx Channel interrupt Handler.
void | sEE_I2C_DMA_TX_IRQHandler (void)
This function handles the DMA Tx Channel interrupt Handler.
void | sEE_Init (void)
Initializes peripherals used by the I2C EEPROM driver.
uint32_t | sEE_ReadBuffer (uint8_t *pBuffer, uint16_t ReadAddr, uint16_t *NumByteToRead)
Reads a block of data from the EEPROM.
uint32_t | sEE_WaitEepromStandbyState (void)
Wait for EEPROM Standby state.
void | sEE_WriteBuffer (uint8_t *pBuffer, uint16_t WriteAddr, uint16_t NumByteToWrite)
Writes buffer of data to the I2C EEPROM.
uint32_t | sEE_WritePage (uint8_t *pBuffer, uint16_t WriteAddr, uint8_t *NumByteToWrite)
Writes more than one byte to the EEPROM with a single WRITE cycle.

Variables

__IO uint16_t | sEEAddress = 0
__IO uint8_t | sEEDataNum
__IO uint16_t * | sEEDataReadPointer
__IO uint8_t * | sEEDataWritePointer
__IO uint32_t | sEETimeout = sEE_LONG_TIMEOUT

Detailed Description

This file provides a set of functions needed to manage the I2C M24CXX EEPROM memory mounted on STM32xx-EVAL board (refer to stm32_eval.h to know about the boards supporting this memory).

Author:
MCD Application Team
Version:
V4.5.0
Date:
07-March-2011 =================================================================== Note: This driver is intended for STM32F10x families devices only. ===================================================================

It implements a high level communication layer for read and write from/to this memory. The needed STM32 hardware resources (I2C and GPIO) are defined in stm32xx_eval.h file, and the initialization is performed in sEE_LowLevel_Init() function declared in stm32xx_eval.c file. You can easily tailor this driver to any other development board, by just adapting the defines for hardware resources and sEE_LowLevel_Init() function.

Note:
In this driver, basic read and write functions (sEE_ReadBuffer() and sEE_WritePage()) use the DMA to perform the data transfer to/from EEPROM memory (except when number of requested data is equal to 1). Thus, after calling these two functions, user application may perform other tasks while DMA is transferring data. The application should then monitor the variable holding the number of data in order to determine when the transfer is completed (variable decremented to 0). Stopping transfer tasks are performed into DMA interrupt handlers (which are integrated into this driver).

+-----------------------------------------------------------------+ | Pin assignment | +---------------------------------------+-----------+-------------+ | STM32 I2C Pins | sEE | Pin | +---------------------------------------+-----------+-------------+ | . | E0(GND) | 1 (0V) | | . | E1(GND) | 2 (0V) | | . | E2(GND) | 3 (0V) | | . | E0(VSS) | 4 (0V) | | sEE_I2C_SDA_PIN/ SDA | SDA | 5 | | sEE_I2C_SCL_PIN/ SCL | SCL | 6 | | . | /WC(VDD)| 7 (3.3V) | | . | VDD | 8 (3.3V) | +---------------------------------------+-----------+-------------+

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm32_eval_i2c_ee.c.


STM32F10x Standard Peripherals Firmware Library: stm32_eval_i2c_ee.h File Reference

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
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  • STM32_EVAL
  • Common
Defines | Functions

stm32_eval_i2c_ee.h File Reference

This file contains all the functions prototypes for the stm32_eval_i2c_ee firmware driver. More...

#include "stm32_eval.h"

Go to the source code of this file.

Defines

#define | I2C_SLAVE_ADDRESS7 0xA0
#define | I2C_SPEED 300000
#define | sEE_FAIL 1
#define | sEE_FLAG_TIMEOUT ((uint32_t)0x1000)
#define | sEE_HW_ADDRESS 0xA0
#define | sEE_LONG_TIMEOUT ((uint32_t)(10 * sEE_FLAG_TIMEOUT))
#define | sEE_M24C64_32
#define | sEE_MAX_TRIALS_NUMBER 150
#define | sEE_OK 0
#define | sEE_PAGESIZE 32
#define | sEE_STATE_BUSY 1
#define | sEE_STATE_ERROR 2
#define | sEE_STATE_READY 0
#define | USE_DEFAULT_CRITICAL_CALLBACK

Functions

void | sEE_DeInit (void)
DeInitializes peripherals used by the I2C EEPROM driver.
void | sEE_EnterCriticalSection_UserCallback (void)
Start critical section: these callbacks should be typically used to disable interrupts when entering a critical section of I2C communication You may use default callbacks provided into this driver by uncommenting the define USE_DEFAULT_CRITICAL_CALLBACK.
void | sEE_ExitCriticalSection_UserCallback (void)
Start and End of critical section: these callbacks should be typically used to re-enable interrupts when exiting a critical section of I2C communication You may use default callbacks provided into this driver by uncommenting the define USE_DEFAULT_CRITICAL_CALLBACK.
void | sEE_Init (void)
Initializes peripherals used by the I2C EEPROM driver.
uint32_t | sEE_ReadBuffer (uint8_t *pBuffer, uint16_t ReadAddr, uint16_t *NumByteToRead)
Reads a block of data from the EEPROM.
uint32_t | sEE_TIMEOUT_UserCallback (void)
Example of timeout situation management.
uint32_t | sEE_WaitEepromStandbyState (void)
Wait for EEPROM Standby state.
void | sEE_WriteBuffer (uint8_t *pBuffer, uint16_t WriteAddr, uint16_t NumByteToWrite)
Writes buffer of data to the I2C EEPROM.
uint32_t | sEE_WritePage (uint8_t *pBuffer, uint16_t WriteAddr, uint8_t *NumByteToWrite)
Writes more than one byte to the EEPROM with a single WRITE cycle.

Detailed Description

This file contains all the functions prototypes for the stm32_eval_i2c_ee firmware driver.

Author:
MCD Application Team
Version:
V4.5.0
Date:
07-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm32_eval_i2c_ee.h.


STM32F10x Standard Peripherals Firmware Library: stm32_eval_i2c_tsensor.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • Common
Defines | Functions | Variables

stm32_eval_i2c_tsensor.c File Reference

This file provides a set of functions needed to manage the I2C LM75 temperature sensor mounted on STM32xx-EVAL board (refer to stm32_eval.h to know about the boards supporting this sensor). It implements a high level communication layer for read and write from/to this sensor. The needed STM32 hardware resources (I2C and GPIO) are defined in stm32xx_eval.h file, and the initialization is performed in LM75_LowLevel_Init() function declared in stm32xx_eval.c file. More...

#include "stm32_eval_i2c_tsensor.h"

Go to the source code of this file.

Defines

#define | LM75_SD_RESET 0xFE
#define | LM75_SD_SET 0x01

Functions

void | LM75_DeInit (void)
DeInitializes the LM75_I2C.
static void | LM75_DMA_Config (LM75_DMADirection_TypeDef Direction, uint8_t *buffer, uint8_t NumData)
Configure the DMA Peripheral used to handle communication via I2C.
ErrorStatus | LM75_GetStatus (void)
Checks the LM75 status.
void | LM75_Init (void)
Initializes the LM75_I2C.
uint8_t | LM75_ReadConfReg (void)
Read the configuration register from the LM75.
uint16_t | LM75_ReadReg (uint8_t RegName)
Read the specified register from the LM75.
uint16_t | LM75_ReadTemp (void)
Read Temperature register of LM75: double temperature value.
uint8_t | LM75_ShutDown (FunctionalState NewState)
Enables or disables the LM75.
uint8_t | LM75_WriteConfReg (uint8_t RegValue)
Write to the configuration register of the LM75.
uint8_t | LM75_WriteReg (uint8_t RegName, uint16_t RegValue)
Write to the specified register of the LM75.

Variables

__IO uint32_t | LM75_Timeout = LM75_LONG_TIMEOUT

Detailed Description

This file provides a set of functions needed to manage the I2C LM75 temperature sensor mounted on STM32xx-EVAL board (refer to stm32_eval.h to know about the boards supporting this sensor). It implements a high level communication layer for read and write from/to this sensor. The needed STM32 hardware resources (I2C and GPIO) are defined in stm32xx_eval.h file, and the initialization is performed in LM75_LowLevel_Init() function declared in stm32xx_eval.c file.

Author:
MCD Application Team
Version:
V4.5.0
Date:
07-March-2011 Note: ----- This driver uses the DMA method to send and receive data on I2C bus, which allows higher efficiency and reliability of the communication.

You can easily tailor this driver to any other development board, by just adapting the defines for hardware resources and LM75_LowLevel_Init() function.

+-----------------------------------------------------------------+ | Pin assignment | +---------------------------------------+-----------+-------------+ | STM32 I2C Pins | STLM75 | Pin | +---------------------------------------+-----------+-------------+ | LM75_I2C_SDA_PIN/ SDA | SDA | 1 | | LM75_I2C_SCL_PIN/ SCL | SCL | 2 | | LM75_I2C_SMBUSALERT_PIN/ SMBUS ALERT | OS/INT | 3 | | . | GND | 4 (0V) | | . | GND | 5 (0V) | | . | GND | 6 (0V) | | . | GND | 7 (0V) | | . | VDD | 8 (3.3V)| +---------------------------------------+-----------+-------------+

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm32_eval_i2c_tsensor.c.


STM32F10x Standard Peripherals Firmware Library: stm32_eval_i2c_tsensor.h File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • Common
Defines | Enumerations | Functions

stm32_eval_i2c_tsensor.h File Reference

This file contains all the functions prototypes for the stm32_eval_i2c_tsensor firmware driver. More...

#include "stm32_eval.h"

Go to the source code of this file.

Defines

#define | I2C_TIMEOUT ((uint32_t)0x3FFFF)
#define | LM75_ADDR 0x90
#define | LM75_FLAG_TIMEOUT ((uint32_t)0x1000)
#define | LM75_I2C_SPEED 100000
#define | LM75_LONG_TIMEOUT ((uint32_t)(10 * LM75_FLAG_TIMEOUT))
#define | LM75_REG_CONF 0x01
#define | LM75_REG_TEMP 0x00
Block Size.
#define | LM75_REG_THYS 0x02
#define | LM75_REG_TOS 0x03
#define | LM75_TIMEOUT_UserCallback() LM75_FAIL
Timeout user callback function.

Enumerations

enum | LM75_DMADirection_TypeDef { LM75_DMA_TX = 0, LM75_DMA_RX = 1 }

IOE DMA Direction.

More...
enum | LM75_Status_TypDef { LM75_OK = 0, LM75_FAIL }

TSENSOR Status.

More...

Functions

void | LM75_DeInit (void)
DeInitializes the LM75_I2C.
ErrorStatus | LM75_GetStatus (void)
Checks the LM75 status.
void | LM75_Init (void)
Initializes the LM75_I2C.
uint8_t | LM75_ReadConfReg (void)
Read the configuration register from the LM75.
uint16_t | LM75_ReadReg (uint8_t RegName)
Read the specified register from the LM75.
uint16_t | LM75_ReadTemp (void)
Read Temperature register of LM75: double temperature value.
uint8_t | LM75_ShutDown (FunctionalState NewState)
Enables or disables the LM75.
uint8_t | LM75_WriteConfReg (uint8_t RegValue)
Write to the configuration register of the LM75.
uint8_t | LM75_WriteReg (uint8_t RegName, uint16_t RegValue)
Write to the specified register of the LM75.

Detailed Description

This file contains all the functions prototypes for the stm32_eval_i2c_tsensor firmware driver.

Author:
MCD Application Team
Version:
V4.5.0
Date:
07-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm32_eval_i2c_tsensor.h.


STM32F10x Standard Peripherals Firmware Library: stm32_eval_sdio_sd.c File Reference

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • Common
Defines | Functions | Variables

stm32_eval_sdio_sd.c File Reference

This file provides a set of functions needed to manage the SDIO SD Card memory mounted on STM32xx-EVAL board (refer to stm32_eval.h to know about the boards supporting this memory). More...

#include "stm32_eval_sdio_sd.h"

Go to the source code of this file.

Defines

#define | NULL 0
SDIO Static flags, TimeOut, FIFO Address.
#define | SD_0TO7BITS ((uint32_t)0x000000FF)
#define | SD_16TO23BITS ((uint32_t)0x00FF0000)
#define | SD_24TO31BITS ((uint32_t)0xFF000000)
#define | SD_8TO15BITS ((uint32_t)0x0000FF00)
#define | SD_ALLZERO ((uint32_t)0x00000000)
#define | SD_CARD_LOCKED ((uint32_t)0x02000000)
#define | SD_CCCC_ERASE ((uint32_t)0x00000020)
#define | SD_CCCC_LOCK_UNLOCK ((uint32_t)0x00000080)
Command Class Supported.
#define | SD_CCCC_WRITE_PROT ((uint32_t)0x00000040)
#define | SD_CHECK_PATTERN ((uint32_t)0x000001AA)
#define | SD_DATATIMEOUT ((uint32_t)0xFFFFFFFF)
#define | SD_HALFFIFO ((uint32_t)0x00000008)
#define | SD_HALFFIFOBYTES ((uint32_t)0x00000020)
#define | SD_HIGH_CAPACITY ((uint32_t)0x40000000)
#define | SD_MAX_DATA_LENGTH ((uint32_t)0x01FFFFFF)
#define | SD_MAX_VOLT_TRIAL ((uint32_t)0x0000FFFF)
#define | SD_OCR_ADDR_MISALIGNED ((uint32_t)0x40000000)
#define | SD_OCR_ADDR_OUT_OF_RANGE ((uint32_t)0x80000000)
Mask for errors Card Status R1 (OCR Register)
#define | SD_OCR_AKE_SEQ_ERROR ((uint32_t)0x00000008)
#define | SD_OCR_BAD_ERASE_PARAM ((uint32_t)0x08000000)
#define | SD_OCR_BLOCK_LEN_ERR ((uint32_t)0x20000000)
#define | SD_OCR_CARD_ECC_DISABLED ((uint32_t)0x00004000)
#define | SD_OCR_CARD_ECC_FAILED ((uint32_t)0x00200000)
#define | SD_OCR_CC_ERROR ((uint32_t)0x00100000)
#define | SD_OCR_CID_CSD_OVERWRIETE ((uint32_t)0x00010000)
#define | SD_OCR_COM_CRC_FAILED ((uint32_t)0x00800000)
#define | SD_OCR_ERASE_RESET ((uint32_t)0x00002000)
#define | SD_OCR_ERASE_SEQ_ERR ((uint32_t)0x10000000)
#define | SD_OCR_ERRORBITS ((uint32_t)0xFDFFE008)
#define | SD_OCR_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00080000)
#define | SD_OCR_ILLEGAL_CMD ((uint32_t)0x00400000)
#define | SD_OCR_LOCK_UNLOCK_FAILED ((uint32_t)0x01000000)
#define | SD_OCR_STREAM_READ_UNDERRUN ((uint32_t)0x00040000)
#define | SD_OCR_STREAM_WRITE_OVERRUN ((uint32_t)0x00020000)
#define | SD_OCR_WP_ERASE_SKIP ((uint32_t)0x00008000)
#define | SD_OCR_WRITE_PROT_VIOLATION ((uint32_t)0x04000000)
#define | SD_R6_COM_CRC_FAILED ((uint32_t)0x00008000)
#define | SD_R6_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00002000)
Masks for R6 Response.
#define | SD_R6_ILLEGAL_CMD ((uint32_t)0x00004000)
#define | SD_SINGLE_BUS_SUPPORT ((uint32_t)0x00010000)
#define | SD_STD_CAPACITY ((uint32_t)0x00000000)
#define | SD_VOLTAGE_WINDOW_SD ((uint32_t)0x80100000)
#define | SD_WIDE_BUS_SUPPORT ((uint32_t)0x00040000)
#define | SDIO_CMD0TIMEOUT ((uint32_t)0x00010000)
#define | SDIO_SEND_IF_COND ((uint32_t)0x00000008)
Following commands are SD Card Specific commands.
#define | SDIO_STATIC_FLAGS ((uint32_t)0x000005FF)

Functions

static SD_Error | CmdError (void)
Checks for error conditions for CMD0.
static SD_Error | CmdResp1Error (uint8_t cmd)
Checks for error conditions for R1 response.
static SD_Error | CmdResp2Error (void)
Checks for error conditions for R2 (CID or CSD) response.
static SD_Error | CmdResp3Error (void)
Checks for error conditions for R3 (OCR) response.
static SD_Error | CmdResp6Error (uint8_t cmd, uint16_t *prca)
Checks for error conditions for R6 (RCA) response.
static SD_Error | CmdResp7Error (void)
Checks for error conditions for R7 response.
uint8_t | convert_from_bytes_to_power_of_two (uint16_t NumberOfBytes)
Converts the number of bytes in power of two and returns the power.
static SD_Error | FindSCR (uint16_t rca, uint32_t *pscr)
Find the SD card SCR register value.
static SD_Error | IsCardProgramming (uint8_t *pstatus)
Checks if the SD card is in programming state.
void | SD_DeInit (void)
DeInitializes the SDIO interface.
uint8_t | SD_Detect (void)
Detect if SD card is correctly plugged in the memory slot.
SD_Error | SD_EnableWideBusOperation (uint32_t WideMode)
Enables wide bus opeartion for the requeseted card if supported by card.
SD_Error | SD_Erase (uint32_t startaddr, uint32_t endaddr)
Allows to erase memory area specified for the given card.
SD_Error | SD_GetCardInfo (SD_CardInfo *cardinfo)
Returns information about specific card.
SD_Error | SD_GetCardStatus (SD_CardStatus *cardstatus)
Enables wide bus opeartion for the requeseted card if supported by card.
SDCardState | SD_GetState (void)
Returns the current card's state.
SDTransferState | SD_GetStatus (void)
Gets the cuurent sd card data transfer status.
SDTransferState | SD_GetTransferState (void)
Gets the cuurent data transfer state.
SD_Error | SD_Init (void)
Initializes the SD Card and put it into StandBy State (Ready for data transfer).
SD_Error | SD_InitializeCards (void)
Intialises all cards or single card as the case may be Card(s) come into standby state.
SD_Error | SD_PowerOFF (void)
Turns the SDIO output signals off.
SD_Error | SD_PowerON (void)
Enquires cards about their operating voltage and configures clock controls.
SD_Error | SD_ProcessIRQSrc (void)
Allows to process all the interrupts that are high.
SD_Error | SD_ReadBlock (uint8_t *readbuff, uint32_t ReadAddr, uint16_t BlockSize)
Allows to read one block from a specified address in a card.
SD_Error | SD_ReadMultiBlocks (uint8_t *readbuff, uint32_t ReadAddr, uint16_t BlockSize, uint32_t NumberOfBlocks)
Allows to read blocks from a specified address in a card.
SD_Error | SD_SelectDeselect (uint32_t addr)
Selects od Deselects the corresponding card.
SD_Error | SD_SendSDStatus (uint32_t *psdstatus)
Returns the current SD card's status.
SD_Error | SD_SendStatus (uint32_t *pcardstatus)
Returns the current card's status.
SD_Error | SD_StopTransfer (void)
Aborts an ongoing data transfer.
SD_Error | SD_WaitReadOperation (void)
This function waits until the SDIO DMA data transfer is finished.
SD_Error | SD_WaitWriteOperation (void)
This function waits until the SDIO DMA data transfer is finished.
SD_Error | SD_WriteBlock (uint8_t *writebuff, uint32_t WriteAddr, uint16_t BlockSize)
Allows to write one block starting from a specified address in a card.
SD_Error | SD_WriteMultiBlocks (uint8_t *writebuff, uint32_t WriteAddr, uint16_t BlockSize, uint32_t NumberOfBlocks)
Allows to write blocks starting from a specified address in a card.
static SD_Error | SDEnWideBus (FunctionalState NewState)
Enables or disables the SDIO wide bus mode.

Variables

static uint32_t | CardType = SDIO_STD_CAPACITY_SD_CARD_V1_1
static uint32_t | CID_Tab [4]
static uint32_t | CSD_Tab [4]
static uint32_t | RCA = 0
SD_CardInfo SDCardInfo
SDIO_CmdInitTypeDef SDIO_CmdInitStructure
SDIO_DataInitTypeDef SDIO_DataInitStructure
SDIO_InitTypeDef SDIO_InitStructure
static uint8_t | SDSTATUS_Tab [16]
__IO uint32_t | StopCondition = 0
__IO uint32_t | TransferEnd = 0
__IO SD_Error | TransferError = SD_OK

Detailed Description

This file provides a set of functions needed to manage the SDIO SD Card memory mounted on STM32xx-EVAL board (refer to stm32_eval.h to know about the boards supporting this memory).

Author:
MCD Application Team
Version:
V4.5.0
Date:
07-March-2011
  *
  *          ===================================================================
  *                                   How to use this driver
  *          ===================================================================
  *          It implements a high level communication layer for read and write
  *          from/to this memory. The needed STM32 hardware resources (SDIO and
  *          GPIO) are defined in stm32xx_eval.h file, and the initialization is
  *          performed in SD_LowLevel_Init() function declared in stm32xx_eval.c
  *          file.
  *          You can easily tailor this driver to any other development board,
  *          by just adapting the defines for hardware resources and
  *          SD_LowLevel_Init() function.
  *
  *          A - SD Card Initialization and configuration
  *          ============================================
  *            - To initialize the SD Card, use the SD_Init() function.  It
  *              Initializes the SD Card and put it into StandBy State (Ready
  *              for data transfer). This function provide the following operations:
  *
  *              1 - Apply the SD Card initialization process at 400KHz and check
  *                  the SD Card type (Standard Capacity or High Capacity). You
  *                  can change or adapt this frequency by adjusting the
  *                  "SDIO_INIT_CLK_DIV" define inside the stm32xx_eval.h file.
  *                  The SD Card frequency (SDIO_CK) is computed as follows:
  *
  *                     +---------------------------------------------+
  *                     | SDIO_CK = SDIOCLK / (SDIO_INIT_CLK_DIV + 2) |
  *                     +---------------------------------------------+
  *
  *                  In initialization mode and according to the SD Card standard,
  *                  make sure that the SDIO_CK frequency don't exceed 400KHz.
  *
  *              2 - Get the SD CID and CSD data. All these information are
  *                  managed by the SDCardInfo structure. This structure provide
  *                  also ready computed SD Card capacity and Block size.
  *
  *              3 - Configure the SD Card Data transfer frequency. By Default,
  *                  the card transfer frequency is set to 24MHz. You can change
  *                  or adapt this frequency by adjusting the "SDIO_TRANSFER_CLK_DIV"
  *                  define inside the stm32xx_eval.h file.
  *                  The SD Card frequency (SDIO_CK) is computed as follows:
  *
  *                     +---------------------------------------------+
  *                     | SDIO_CK = SDIOCLK / (SDIO_INIT_CLK_DIV + 2) |
  *                     +---------------------------------------------+
  *
  *                  In transfer mode and according to the SD Card standard,
  *                  make sure that the SDIO_CK frequency don't exceed 25MHz
  *                  and 50MHz in High-speed mode switch.
  *                  To be able to use a frequency higher than 24MHz, you should
  *                  use the SDIO peripheral in bypass mode. Refer to the
  *                  corresponding reference manual for more details.
  *
  *              4 -  Select the corresponding SD Card according to the address
  *                   read with the step 2.
  *
  *              5 -  Configure the SD Card in wide bus mode: 4-bits data.
  *
  *          B - SD Card Read operation
  *          ==========================
  *           - You can read SD card by using two function: SD_ReadBlock() and
  *             SD_ReadMultiBlocks() functions. These functions support only
  *             512-byte block length.
  *           - The SD_ReadBlock() function read only one block (512-byte). This
  *             function can transfer the data using DMA controller or using
  *             polling mode. To select between DMA or polling mode refer to
  *             "SD_DMA_MODE" or "SD_POLLING_MODE" inside the stm32_eval_sdio_sd.h
  *             file and uncomment the corresponding line. By default the SD DMA
  *             mode is selected
  *           - The SD_ReadMultiBlocks() function read only mutli blocks (multiple
  *             of 512-byte).
  *           - Any read operation should be followed by two functions to check
  *             if the DMA Controller and SD Card status.
  *              - SD_ReadWaitOperation(): this function insure that the DMA
  *                controller has finished all data transfer.
  *              - SD_GetStatus(): to check that the SD Card has finished the
  *                data transfer and it is ready for data.
  *
  *           - The DMA transfer is finished by the SDIO Data End interrupt. User
  *             has to call the SD_ProcessIRQ() function inside the SDIO_IRQHandler().
  *             Don't forget to enable the SDIO_IRQn interrupt using the NVIC controller.
  *
  *          C - SD Card Write operation
  *          ===========================
  *           - You can write SD card by using two function: SD_WriteBlock() and
  *             SD_WriteMultiBlocks() functions. These functions support only
  *             512-byte block length.
  *           - The SD_WriteBlock() function write only one block (512-byte). This
  *             function can transfer the data using DMA controller or using
  *             polling mode. To select between DMA or polling mode refer to
  *             "SD_DMA_MODE" or "SD_POLLING_MODE" inside the stm32_eval_sdio_sd.h
  *             file and uncomment the corresponding line. By default the SD DMA
  *             mode is selected
  *           - The SD_WriteMultiBlocks() function write only mutli blocks (multiple
  *             of 512-byte).
  *           - Any write operation should be followed by two functions to check
  *             if the DMA Controller and SD Card status.
  *              - SD_ReadWaitOperation(): this function insure that the DMA
  *                controller has finished all data transfer.
  *              - SD_GetStatus(): to check that the SD Card has finished the
  *                data transfer and it is ready for data.
  *
  *           - The DMA transfer is finished by the SDIO Data End interrupt. User
  *             has to call the SD_ProcessIRQ() function inside the SDIO_IRQHandler().
  *             Don't forget to enable the SDIO_IRQn interrupt using the NVIC controller.

  *
  *          D - SD card status
  *          ==================
  *           - At any time, you can check the SD Card status and get the SD card
  *             state by using the SD_GetStatus() function. This function checks
  *             first if the SD card is still connected and then get the internal
  *             SD Card transfer state.
  *           - You can also get the SD card SD Status register by using the
  *             SD_SendSDStatus() function.
  *
  *          E - Programming Model
  *          =====================
  *             Status = SD_Init(); // Initialization Step as described in section A
  *
  *             // SDIO Interrupt ENABLE
  *             NVIC_InitStructure.NVIC_IRQChannel = SDIO_IRQn;
  *             NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
  *             NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
  *             NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
  *             NVIC_Init(&NVIC_InitStructure);
  *
  *             // Write operation as described in Section C
  *             Status = SD_WriteBlock(buffer, address, 512);
  *             Status = SD_WaitWriteOperation();
  *             while(SD_GetStatus() != SD_TRANSFER_OK);
  *
  *             Status = SD_WriteMultiBlocks(buffer, address, 512, NUMBEROFBLOCKS);
  *             Status = SD_WaitWriteOperation();
  *             while(SD_GetStatus() != SD_TRANSFER_OK);
  *
  *             // Read operation as described in Section B
  *             Status = SD_ReadBlock(buffer, address, 512);
  *             Status = SD_WaitReadOperation();
  *             while(SD_GetStatus() != SD_TRANSFER_OK);
  *
  *             Status = SD_ReadMultiBlocks(buffer, address, 512, NUMBEROFBLOCKS);
  *             Status = SD_WaitReadOperation();
  *             while(SD_GetStatus() != SD_TRANSFER_OK);
  *
  *
  *          STM32 SDIO Pin assignment
  *          =========================
  *          +-----------------------------------------------------------+
  *          |                     Pin assignment                        |
  *          +-----------------------------+---------------+-------------+
  *          |  STM32 SDIO Pins            |     SD        |    Pin      |
  *          +-----------------------------+---------------+-------------+
  *          |      SDIO D2                |   D2          |    1        |
  *          |      SDIO D3                |   D3          |    2        |
  *          |      SDIO CMD               |   CMD         |    3        |
  *          |                             |   VCC         |    4 (3.3 V)|
  *          |      SDIO CLK               |   CLK         |    5        |
  *          |                             |   GND         |    6 (0 V)  |
  *          |      SDIO D0                |   D0          |    7        |
  *          |      SDIO D1                |   D1          |    8        |
  *          +-----------------------------+---------------+-------------+
  *
  *
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm32_eval_sdio_sd.c.


STM32F10x Standard Peripherals Firmware Library: stm32_eval_sdio_sd.h File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • Common
Data Structures | Defines | Enumerations | Functions

stm32_eval_sdio_sd.h File Reference

This file contains all the functions prototypes for the SD Card stm32_eval_sdio_sd driver firmware library. More...

#include "stm32_eval.h"

Go to the source code of this file.

Data Structures

struct | SD_CardInfo
SD Card information. More...
struct | SD_CardStatus
SD Card Status. More...
struct | SD_CID
Card Identification Data: CID Register. More...
struct | SD_CSD
Card Specific Data: CSD Register. More...

Defines

#define | SD_CMD_ALL_SEND_CID ((uint8_t)2)
#define | SD_CMD_APP_CMD ((uint8_t)55)
#define | SD_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6)
Following commands are SD Card Specific commands.
#define | SD_CMD_CLR_WRITE_PROT ((uint8_t)29)
#define | SD_CMD_ERASE ((uint8_t)38)
#define | SD_CMD_ERASE_GRP_END ((uint8_t)36)
#define | SD_CMD_ERASE_GRP_START ((uint8_t)35)
#define | SD_CMD_FAST_IO ((uint8_t)39)
#define | SD_CMD_GEN_CMD ((uint8_t)56)
#define | SD_CMD_GO_IDLE_STATE ((uint8_t)0)
SDIO Commands Index.
#define | SD_CMD_GO_INACTIVE_STATE ((uint8_t)15)
#define | SD_CMD_GO_IRQ_STATE ((uint8_t)40)
#define | SD_CMD_HS_BUSTEST_READ ((uint8_t)14)
#define | SD_CMD_HS_BUSTEST_WRITE ((uint8_t)19)
#define | SD_CMD_HS_SEND_EXT_CSD ((uint8_t)8)
#define | SD_CMD_HS_SWITCH ((uint8_t)6)
#define | SD_CMD_LOCK_UNLOCK ((uint8_t)42)
#define | SD_CMD_NO_CMD ((uint8_t)64)
#define | SD_CMD_PROG_CID ((uint8_t)26)
#define | SD_CMD_PROG_CSD ((uint8_t)27)
#define | SD_CMD_READ_DAT_UNTIL_STOP ((uint8_t)11)
#define | SD_CMD_READ_MULT_BLOCK ((uint8_t)18)
#define | SD_CMD_READ_SINGLE_BLOCK ((uint8_t)17)
#define | SD_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49)
#define | SD_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48)
#define | SD_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46)
#define | SD_CMD_SD_APP_GET_MID ((uint8_t)44)
#define | SD_CMD_SD_APP_GET_MKB ((uint8_t)43)
Following commands are SD Card Specific security commands.
#define | SD_CMD_SD_APP_OP_COND ((uint8_t)41)
#define | SD_CMD_SD_APP_SECURE_ERASE ((uint8_t)38)
#define | SD_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18)
#define | SD_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48)
#define | SD_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25)
#define | SD_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22)
#define | SD_CMD_SD_APP_SEND_SCR ((uint8_t)51)
#define | SD_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47)
#define | SD_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45)
#define | SD_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42)
#define | SD_CMD_SD_APP_STAUS ((uint8_t)13)
#define | SD_CMD_SD_ERASE_GRP_END ((uint8_t)33)
#define | SD_CMD_SD_ERASE_GRP_START ((uint8_t)32)
#define | SD_CMD_SDIO_RW_DIRECT ((uint8_t)52)
#define | SD_CMD_SDIO_RW_EXTENDED ((uint8_t)53)
#define | SD_CMD_SDIO_SEN_OP_COND ((uint8_t)5)
#define | SD_CMD_SEL_DESEL_CARD ((uint8_t)7)
#define | SD_CMD_SEND_CID ((uint8_t)10)
#define | SD_CMD_SEND_CSD ((uint8_t)9)
#define | SD_CMD_SEND_OP_COND ((uint8_t)1)
#define | SD_CMD_SEND_STATUS ((uint8_t)13)
#define | SD_CMD_SEND_WRITE_PROT ((uint8_t)30)
#define | SD_CMD_SET_BLOCK_COUNT ((uint8_t)23)
#define | SD_CMD_SET_BLOCKLEN ((uint8_t)16)
#define | SD_CMD_SET_DSR ((uint8_t)4)
#define | SD_CMD_SET_REL_ADDR ((uint8_t)3)
#define | SD_CMD_SET_WRITE_PROT ((uint8_t)28)
#define | SD_CMD_STOP_TRANSMISSION ((uint8_t)12)
#define | SD_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20)
#define | SD_CMD_WRITE_MULT_BLOCK ((uint8_t)25)
#define | SD_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24)
#define | SD_DMA_MODE ((uint32_t)0x00000000)
#define | SD_NOT_PRESENT ((uint8_t)0x00)
#define | SD_PRESENT ((uint8_t)0x01)
SD detection on its memory slot.
#define | SDIO_HIGH_CAPACITY_MMC_CARD ((uint32_t)0x00000007)
#define | SDIO_HIGH_CAPACITY_SD_CARD ((uint32_t)0x00000002)
#define | SDIO_HIGH_SPEED_MULTIMEDIA_CARD ((uint32_t)0x00000005)
#define | SDIO_MULTIMEDIA_CARD ((uint32_t)0x00000003)
#define | SDIO_SECURE_DIGITAL_IO_CARD ((uint32_t)0x00000004)
#define | SDIO_SECURE_DIGITAL_IO_COMBO_CARD ((uint32_t)0x00000006)
#define | SDIO_STD_CAPACITY_SD_CARD_V1_1 ((uint32_t)0x00000000)
Supported SD Memory Cards.
#define | SDIO_STD_CAPACITY_SD_CARD_V2_0 ((uint32_t)0x00000001)

Enumerations

enum SD_Error {
SD_CMD_CRC_FAIL = (1), SD_DATA_CRC_FAIL = (2), SD_CMD_RSP_TIMEOUT = (3), SD_DATA_TIMEOUT = (4),
SD_TX_UNDERRUN = (5), SD_RX_OVERRUN = (6), SD_START_BIT_ERR = (7), SD_CMD_OUT_OF_RANGE = (8),
SD_ADDR_MISALIGNED = (9), SD_BLOCK_LEN_ERR = (10), SD_ERASE_SEQ_ERR = (11), SD_BAD_ERASE_PARAM = (12),
SD_WRITE_PROT_VIOLATION = (13), SD_LOCK_UNLOCK_FAILED = (14), SD_COM_CRC_FAILED = (15), SD_ILLEGAL_CMD = (16),
SD_CARD_ECC_FAILED = (17), SD_CC_ERROR = (18), SD_GENERAL_UNKNOWN_ERROR = (19), SD_STREAM_READ_UNDERRUN = (20),
SD_STREAM_WRITE_OVERRUN = (21), SD_CID_CSD_OVERWRITE = (22), SD_WP_ERASE_SKIP = (23), SD_CARD_ECC_DISABLED = (24),
SD_ERASE_RESET = (25), SD_AKE_SEQ_ERROR = (26), SD_INVALID_VOLTRANGE = (27), SD_ADDR_OUT_OF_RANGE = (28),
SD_SWITCH_ERROR = (29), SD_SDIO_DISABLED = (30), SD_SDIO_FUNCTION_BUSY = (31), SD_SDIO_FUNCTION_FAILED = (32),
SD_SDIO_UNKNOWN_FUNCTION = (33), SD_INTERNAL_ERROR, SD_NOT_CONFIGURED, SD_REQUEST_PENDING,
SD_REQUEST_NOT_APPLICABLE, SD_INVALID_PARAMETER, SD_UNSUPPORTED_FEATURE, SD_UNSUPPORTED_HW,
SD_ERROR, SD_OK = 0, SD_RESPONSE_NO_ERROR = (0x00), SD_IN_IDLE_STATE = (0x01),
SD_ERASE_RESET = (0x02), SD_ILLEGAL_COMMAND = (0x04), SD_COM_CRC_ERROR = (0x08), SD_ERASE_SEQUENCE_ERROR = (0x10),
SD_ADDRESS_ERROR = (0x20), SD_PARAMETER_ERROR = (0x40), SD_RESPONSE_FAILURE = (0xFF), SD_DATA_OK = (0x05),
SD_DATA_CRC_ERROR = (0x0B), SD_DATA_WRITE_ERROR = (0x0D), SD_DATA_OTHER_ERROR = (0xFF)
}
enum SDCardState {
SD_CARD_READY = ((uint32_t)0x00000001), SD_CARD_IDENTIFICATION = ((uint32_t)0x00000002), SD_CARD_STANDBY = ((uint32_t)0x00000003), SD_CARD_TRANSFER = ((uint32_t)0x00000004),
SD_CARD_SENDING = ((uint32_t)0x00000005), SD_CARD_RECEIVING = ((uint32_t)0x00000006), SD_CARD_PROGRAMMING = ((uint32_t)0x00000007), SD_CARD_DISCONNECTED = ((uint32_t)0x00000008),
SD_CARD_ERROR = ((uint32_t)0x000000FF)
}

SD Card States.

More...
enum | SDTransferState { SD_TRANSFER_OK = 0, SD_TRANSFER_BUSY = 1, SD_TRANSFER_ERROR }

SDIO Transfer state.

More...

Functions

void | SD_DeInit (void)
DeInitializes the SDIO interface.
uint8_t | SD_Detect (void)
Detect if SD card is correctly plugged in the memory slot.
SD_Error | SD_EnableWideBusOperation (uint32_t WideMode)
Enables wide bus opeartion for the requeseted card if supported by card.
SD_Error | SD_Erase (uint32_t startaddr, uint32_t endaddr)
Allows to erase memory area specified for the given card.
SD_Error | SD_GetCardInfo (SD_CardInfo *cardinfo)
Returns information about specific card.
SD_Error | SD_GetCardStatus (SD_CardStatus *cardstatus)
Enables wide bus opeartion for the requeseted card if supported by card.
SDCardState | SD_GetState (void)
Returns the current card's state.
SDTransferState | SD_GetStatus (void)
Gets the cuurent sd card data transfer status.
SDTransferState | SD_GetTransferState (void)
Gets the cuurent data transfer state.
SD_Error | SD_Init (void)
Initializes the SD Card and put it into StandBy State (Ready for data transfer).
SD_Error | SD_InitializeCards (void)
Intialises all cards or single card as the case may be Card(s) come into standby state.
SD_Error | SD_PowerOFF (void)
Turns the SDIO output signals off.
SD_Error | SD_PowerON (void)
Enquires cards about their operating voltage and configures clock controls.
SD_Error | SD_ProcessIRQSrc (void)
Allows to process all the interrupts that are high.
SD_Error | SD_ReadBlock (uint8_t *readbuff, uint32_t ReadAddr, uint16_t BlockSize)
Allows to read one block from a specified address in a card.
SD_Error | SD_ReadMultiBlocks (uint8_t *readbuff, uint32_t ReadAddr, uint16_t BlockSize, uint32_t NumberOfBlocks)
Allows to read blocks from a specified address in a card.
SD_Error | SD_SelectDeselect (uint32_t addr)
Selects od Deselects the corresponding card.
SD_Error | SD_SendSDStatus (uint32_t *psdstatus)
Returns the current SD card's status.
SD_Error | SD_SendStatus (uint32_t *pcardstatus)
Returns the current card's status.
SD_Error | SD_StopTransfer (void)
Aborts an ongoing data transfer.
SD_Error | SD_WaitReadOperation (void)
This function waits until the SDIO DMA data transfer is finished.
SD_Error | SD_WaitWriteOperation (void)
This function waits until the SDIO DMA data transfer is finished.
SD_Error | SD_WriteBlock (uint8_t *writebuff, uint32_t WriteAddr, uint16_t BlockSize)
Allows to write one block starting from a specified address in a card.
SD_Error | SD_WriteMultiBlocks (uint8_t *writebuff, uint32_t WriteAddr, uint16_t BlockSize, uint32_t NumberOfBlocks)
Allows to write blocks starting from a specified address in a card.

Detailed Description

This file contains all the functions prototypes for the SD Card stm32_eval_sdio_sd driver firmware library.

Author:
MCD Application Team
Version:
V4.5.0
Date:
07-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm32_eval_sdio_sd.h.


STM32F10x Standard Peripherals Firmware Library: stm32_eval_spi_flash.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • Common
Functions

stm32_eval_spi_flash.c File Reference

This file provides a set of functions needed to manage the SPI M25Pxxx FLASH memory mounted on STM32xx-EVAL board (refer to stm32_eval.h to know about the boards supporting this memory). It implements a high level communication layer for read and write from/to this memory. The needed STM32 hardware resources (SPI and GPIO) are defined in stm32xx_eval.h file, and the initialization is performed in sFLASH_LowLevel_Init() function declared in stm32xx_eval.c file. You can easily tailor this driver to any other development board, by just adapting the defines for hardware resources and sFLASH_LowLevel_Init() function. More...

#include "stm32_eval_spi_flash.h"

Go to the source code of this file.

Functions

void | sFLASH_DeInit (void)
DeInitializes the peripherals used by the SPI FLASH driver.
void | sFLASH_EraseBulk (void)
Erases the entire FLASH.
void | sFLASH_EraseSector (uint32_t SectorAddr)
Erases the specified FLASH sector.
void | sFLASH_Init (void)
Initializes the peripherals used by the SPI FLASH driver.
void | sFLASH_ReadBuffer (uint8_t *pBuffer, uint32_t ReadAddr, uint16_t NumByteToRead)
Reads a block of data from the FLASH.
uint8_t | sFLASH_ReadByte (void)
Reads a byte from the SPI Flash.
uint32_t | sFLASH_ReadID (void)
Reads FLASH identification.
uint8_t | sFLASH_SendByte (uint8_t byte)
Sends a byte through the SPI interface and return the byte received from the SPI bus.
uint16_t | sFLASH_SendHalfWord (uint16_t HalfWord)
Sends a Half Word through the SPI interface and return the Half Word received from the SPI bus.
void | sFLASH_StartReadSequence (uint32_t ReadAddr)
Initiates a read data byte (READ) sequence from the Flash.
void | sFLASH_WaitForWriteEnd (void)
Polls the status of the Write In Progress (WIP) flag in the FLASH's status register and loop until write opertaion has completed.
void | sFLASH_WriteBuffer (uint8_t *pBuffer, uint32_t WriteAddr, uint16_t NumByteToWrite)
Writes block of data to the FLASH.
void | sFLASH_WriteEnable (void)
Enables the write access to the FLASH.
void | sFLASH_WritePage (uint8_t *pBuffer, uint32_t WriteAddr, uint16_t NumByteToWrite)
Writes more than one byte to the FLASH with a single WRITE cycle (Page WRITE sequence).

Detailed Description

This file provides a set of functions needed to manage the SPI M25Pxxx FLASH memory mounted on STM32xx-EVAL board (refer to stm32_eval.h to know about the boards supporting this memory). It implements a high level communication layer for read and write from/to this memory. The needed STM32 hardware resources (SPI and GPIO) are defined in stm32xx_eval.h file, and the initialization is performed in sFLASH_LowLevel_Init() function declared in stm32xx_eval.c file. You can easily tailor this driver to any other development board, by just adapting the defines for hardware resources and sFLASH_LowLevel_Init() function.

Author:
MCD Application Team
Version:
V4.5.0
Date:
07-March-2011 +-----------------------------------------------------------+ | Pin assignment | +-----------------------------+---------------+-------------+ | STM32 SPI Pins | sFLASH | Pin | +-----------------------------+---------------+-------------+ | sFLASH_CS_PIN | ChipSelect(/S)| 1 | | sFLASH_SPI_MISO_PIN / MISO | DataOut(Q) | 2 | | | VCC | 3 (3.3 V)| | | GND | 4 (0 V) | | sFLASH_SPI_MOSI_PIN / MOSI | DataIn(D) | 5 | | sFLASH_SPI_SCK_PIN / SCLK | Clock(C) | 6 | | | VCC | 7 (3.3 V)| | | VCC | 8 (3.3 V)| +-----------------------------+---------------+-------------+
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm32_eval_spi_flash.c.


STM32F10x Standard Peripherals Firmware Library: stm32_eval_spi_flash.h File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • Common
Defines | Functions

stm32_eval_spi_flash.h File Reference

This file contains all the functions prototypes for the stm32_eval_spi_flash firmware driver. More...

#include "stm32_eval.h"

Go to the source code of this file.

Defines

#define | sFLASH_CMD_BE 0xC7
#define | sFLASH_CMD_RDID 0x9F
#define | sFLASH_CMD_RDSR 0x05
#define | sFLASH_CMD_READ 0x03
#define | sFLASH_CMD_SE 0xD8
#define | sFLASH_CMD_WREN 0x06
#define | sFLASH_CMD_WRITE 0x02
M25P SPI Flash supported commands.
#define | sFLASH_CMD_WRSR 0x01
#define | sFLASH_CS_HIGH() GPIO_SetBits(sFLASH_CS_GPIO_PORT, sFLASH_CS_PIN)
Deselect sFLASH: Chip Select pin high.
#define | sFLASH_CS_LOW() GPIO_ResetBits(sFLASH_CS_GPIO_PORT, sFLASH_CS_PIN)
Select sFLASH: Chip Select pin low.
#define | sFLASH_DUMMY_BYTE 0xA5
#define | sFLASH_M25P128_ID 0x202018
#define | sFLASH_M25P64_ID 0x202017
#define | sFLASH_SPI_PAGESIZE 0x100
#define | sFLASH_WIP_FLAG 0x01

Functions

void | sFLASH_DeInit (void)
High layer functions.
void | sFLASH_EraseBulk (void)
Erases the entire FLASH.
void | sFLASH_EraseSector (uint32_t SectorAddr)
Erases the specified FLASH sector.
void | sFLASH_Init (void)
Initializes the peripherals used by the SPI FLASH driver.
void | sFLASH_ReadBuffer (uint8_t *pBuffer, uint32_t ReadAddr, uint16_t NumByteToRead)
Reads a block of data from the FLASH.
uint8_t | sFLASH_ReadByte (void)
Low layer functions.
uint32_t | sFLASH_ReadID (void)
Reads FLASH identification.
uint8_t | sFLASH_SendByte (uint8_t byte)
Sends a byte through the SPI interface and return the byte received from the SPI bus.
uint16_t | sFLASH_SendHalfWord (uint16_t HalfWord)
Sends a Half Word through the SPI interface and return the Half Word received from the SPI bus.
void | sFLASH_StartReadSequence (uint32_t ReadAddr)
Initiates a read data byte (READ) sequence from the Flash.
void | sFLASH_WaitForWriteEnd (void)
Polls the status of the Write In Progress (WIP) flag in the FLASH's status register and loop until write opertaion has completed.
void | sFLASH_WriteBuffer (uint8_t *pBuffer, uint32_t WriteAddr, uint16_t NumByteToWrite)
Writes block of data to the FLASH.
void | sFLASH_WriteEnable (void)
Enables the write access to the FLASH.
void | sFLASH_WritePage (uint8_t *pBuffer, uint32_t WriteAddr, uint16_t NumByteToWrite)
Writes more than one byte to the FLASH with a single WRITE cycle (Page WRITE sequence).

Detailed Description

This file contains all the functions prototypes for the stm32_eval_spi_flash firmware driver.

Author:
MCD Application Team
Version:
V4.5.0
Date:
07-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm32_eval_spi_flash.h.


STM32F10x Standard Peripherals Firmware Library: stm32_eval_spi_sd.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • Common
Functions

stm32_eval_spi_sd.c File Reference

This file provides a set of functions needed to manage the SPI SD Card memory mounted on STM32xx-EVAL board (refer to stm32_eval.h to know about the boards supporting this memory). It implements a high level communication layer for read and write from/to this memory. The needed STM32 hardware resources (SPI and GPIO) are defined in stm32xx_eval.h file, and the initialization is performed in SD_LowLevel_Init() function declared in stm32xx_eval.c file. You can easily tailor this driver to any other development board, by just adapting the defines for hardware resources and SD_LowLevel_Init() function. More...

#include "stm32_eval_spi_sd.h"

Go to the source code of this file.

Functions

void | SD_DeInit (void)
DeInitializes the SD/SD communication.
uint8_t | SD_Detect (void)
Detect if SD card is correctly plugged in the memory slot.
SD_Error | SD_GetCardInfo (SD_CardInfo *cardinfo)
Returns information about specific card.
SD_Error | SD_GetCIDRegister (SD_CID *SD_cid)
Read the CID card register.
SD_Error | SD_GetCSDRegister (SD_CSD *SD_csd)
Read the CSD card register.
uint8_t | SD_GetDataResponse (void)
Get SD card data response.
SD_Error | SD_GetResponse (uint8_t Response)
Returns the SD response.
uint16_t | SD_GetStatus (void)
Returns the SD status.
SD_Error | SD_GoIdleState (void)
Put SD in Idle state.
SD_Error | SD_Init (void)
Initializes the SD/SD communication.
SD_Error | SD_ReadBlock (uint8_t *pBuffer, uint32_t ReadAddr, uint16_t BlockSize)
Reads a block of data from the SD.
uint8_t | SD_ReadByte (void)
Read a byte from the SD.
SD_Error | SD_ReadMultiBlocks (uint8_t *pBuffer, uint32_t ReadAddr, uint16_t BlockSize, uint32_t NumberOfBlocks)
Reads multiple block of data from the SD.
void | SD_SendCmd (uint8_t Cmd, uint32_t Arg, uint8_t Crc)
Send 5 bytes command to the SD card.
SD_Error | SD_WriteBlock (uint8_t *pBuffer, uint32_t WriteAddr, uint16_t BlockSize)
Writes a block on the SD.
uint8_t | SD_WriteByte (uint8_t Data)
Write a byte on the SD.
SD_Error | SD_WriteMultiBlocks (uint8_t *pBuffer, uint32_t WriteAddr, uint16_t BlockSize, uint32_t NumberOfBlocks)
Writes many blocks on the SD.

Detailed Description

This file provides a set of functions needed to manage the SPI SD Card memory mounted on STM32xx-EVAL board (refer to stm32_eval.h to know about the boards supporting this memory). It implements a high level communication layer for read and write from/to this memory. The needed STM32 hardware resources (SPI and GPIO) are defined in stm32xx_eval.h file, and the initialization is performed in SD_LowLevel_Init() function declared in stm32xx_eval.c file. You can easily tailor this driver to any other development board, by just adapting the defines for hardware resources and SD_LowLevel_Init() function.

Author:
MCD Application Team
Version:
V4.5.0
Date:
07-March-2011 +-------------------------------------------------------+ | Pin assignment | +-------------------------+---------------+-------------+ | STM32 SPI Pins | SD | Pin | +-------------------------+---------------+-------------+ | SD_SPI_CS_PIN | ChipSelect | 1 | | SD_SPI_MOSI_PIN / MOSI | DataIn | 2 | | | GND | 3 (0 V) | | | VDD | 4 (3.3 V)| | SD_SPI_SCK_PIN / SCLK | Clock | 5 | | | GND | 6 (0 V) | | SD_SPI_MISO_PIN / MISO | DataOut | 7 | +-------------------------+---------------+-------------+
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm32_eval_spi_sd.c.


STM32F10x Standard Peripherals Firmware Library: stm32_eval_spi_sd.h File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • Common
Data Structures | Defines | Enumerations | Functions

stm32_eval_spi_sd.h File Reference

This file contains all the functions prototypes for the stm32_eval_spi_sd firmware driver. More...

#include "stm32_eval.h"

Go to the source code of this file.

Data Structures

struct | SD_CardInfo
SD Card information. More...
struct | SD_CID
Card Identification Data: CID Register. More...
struct | SD_CSD
Card Specific Data: CSD Register. More...

Defines

#define | SD_BLOCK_SIZE 0x200
Block Size.
#define | SD_CMD_CLR_WRITE_PROT 29
#define | SD_CMD_ERASE 38
#define | SD_CMD_ERASE_GRP_END 36
#define | SD_CMD_ERASE_GRP_START 35
#define | SD_CMD_GO_IDLE_STATE 0
Commands: CMDxx = CMD-number | 0x40.
#define | SD_CMD_PROG_CSD 27
#define | SD_CMD_READ_MULT_BLOCK 18
#define | SD_CMD_READ_SINGLE_BLOCK 17
#define | SD_CMD_SD_ERASE_GRP_END 33
#define | SD_CMD_SD_ERASE_GRP_START 32
#define | SD_CMD_SEND_CID 10
#define | SD_CMD_SEND_CSD 9
#define | SD_CMD_SEND_OP_COND 1
#define | SD_CMD_SEND_STATUS 13
#define | SD_CMD_SEND_WRITE_PROT 30
#define | SD_CMD_SET_BLOCK_COUNT 23
#define | SD_CMD_SET_BLOCKLEN 16
#define | SD_CMD_SET_WRITE_PROT 28
#define | SD_CMD_STOP_TRANSMISSION 12
#define | SD_CMD_UNTAG_ERASE_GROUP 37
#define | SD_CMD_UNTAG_SECTOR 34
#define | SD_CMD_WRITE_MULT_BLOCK 25
#define | SD_CMD_WRITE_SINGLE_BLOCK 24
#define | SD_CS_HIGH() GPIO_SetBits(SD_CS_GPIO_PORT, SD_CS_PIN)
Deselect SD Card: ChipSelect pin high.
#define | SD_CS_LOW() GPIO_ResetBits(SD_CS_GPIO_PORT, SD_CS_PIN)
Select SD Card: ChipSelect pin low.
#define | SD_DUMMY_BYTE 0xFF
Dummy byte.
#define | SD_NOT_PRESENT ((uint8_t)0x00)
#define | SD_PRESENT ((uint8_t)0x01)
SD detection on its memory slot.
#define | SD_START_DATA_MULTIPLE_BLOCK_READ 0xFE
#define | SD_START_DATA_MULTIPLE_BLOCK_WRITE 0xFD
#define | SD_START_DATA_SINGLE_BLOCK_READ 0xFE
Start Data tokens: Tokens (necessary because at nop/idle (and CS active) only 0xff is on the data/command line)
#define | SD_START_DATA_SINGLE_BLOCK_WRITE 0xFE
#define | SD_STOP_DATA_MULTIPLE_BLOCK_WRITE 0xFD

Enumerations

enum SD_Error {
SD_CMD_CRC_FAIL = (1), SD_DATA_CRC_FAIL = (2), SD_CMD_RSP_TIMEOUT = (3), SD_DATA_TIMEOUT = (4),
SD_TX_UNDERRUN = (5), SD_RX_OVERRUN = (6), SD_START_BIT_ERR = (7), SD_CMD_OUT_OF_RANGE = (8),
SD_ADDR_MISALIGNED = (9), SD_BLOCK_LEN_ERR = (10), SD_ERASE_SEQ_ERR = (11), SD_BAD_ERASE_PARAM = (12),
SD_WRITE_PROT_VIOLATION = (13), SD_LOCK_UNLOCK_FAILED = (14), SD_COM_CRC_FAILED = (15), SD_ILLEGAL_CMD = (16),
SD_CARD_ECC_FAILED = (17), SD_CC_ERROR = (18), SD_GENERAL_UNKNOWN_ERROR = (19), SD_STREAM_READ_UNDERRUN = (20),
SD_STREAM_WRITE_OVERRUN = (21), SD_CID_CSD_OVERWRITE = (22), SD_WP_ERASE_SKIP = (23), SD_CARD_ECC_DISABLED = (24),
SD_ERASE_RESET = (25), SD_AKE_SEQ_ERROR = (26), SD_INVALID_VOLTRANGE = (27), SD_ADDR_OUT_OF_RANGE = (28),
SD_SWITCH_ERROR = (29), SD_SDIO_DISABLED = (30), SD_SDIO_FUNCTION_BUSY = (31), SD_SDIO_FUNCTION_FAILED = (32),
SD_SDIO_UNKNOWN_FUNCTION = (33), SD_INTERNAL_ERROR, SD_NOT_CONFIGURED, SD_REQUEST_PENDING,
SD_REQUEST_NOT_APPLICABLE, SD_INVALID_PARAMETER, SD_UNSUPPORTED_FEATURE, SD_UNSUPPORTED_HW,
SD_ERROR, SD_OK = 0, SD_RESPONSE_NO_ERROR = (0x00), SD_IN_IDLE_STATE = (0x01),
SD_ERASE_RESET = (0x02), SD_ILLEGAL_COMMAND = (0x04), SD_COM_CRC_ERROR = (0x08), SD_ERASE_SEQUENCE_ERROR = (0x10),
SD_ADDRESS_ERROR = (0x20), SD_PARAMETER_ERROR = (0x40), SD_RESPONSE_FAILURE = (0xFF), SD_DATA_OK = (0x05),
SD_DATA_CRC_ERROR = (0x0B), SD_DATA_WRITE_ERROR = (0x0D), SD_DATA_OTHER_ERROR = (0xFF)
}

Functions

void | SD_DeInit (void)
DeInitializes the SDIO interface.
uint8_t | SD_Detect (void)
Detect if SD card is correctly plugged in the memory slot.
SD_Error | SD_GetCardInfo (SD_CardInfo *cardinfo)
Returns information about specific card.
SD_Error | SD_GetCIDRegister (SD_CID *SD_cid)
Read the CID card register.
SD_Error | SD_GetCSDRegister (SD_CSD *SD_csd)
Read the CSD card register.
uint8_t | SD_GetDataResponse (void)
Get SD card data response.
SD_Error | SD_GetResponse (uint8_t Response)
Returns the SD response.
uint16_t | SD_GetStatus (void)
Gets the cuurent sd card data transfer status.
SD_Error | SD_GoIdleState (void)
Put SD in Idle state.
SD_Error | SD_Init (void)
Initializes the SD Card and put it into StandBy State (Ready for data transfer).
SD_Error | SD_ReadBlock (uint8_t *pBuffer, uint32_t ReadAddr, uint16_t BlockSize)
Allows to read one block from a specified address in a card.
uint8_t | SD_ReadByte (void)
Read a byte from the SD.
SD_Error | SD_ReadMultiBlocks (uint8_t *pBuffer, uint32_t ReadAddr, uint16_t BlockSize, uint32_t NumberOfBlocks)
Allows to read blocks from a specified address in a card.
void | SD_SendCmd (uint8_t Cmd, uint32_t Arg, uint8_t Crc)
Send 5 bytes command to the SD card.
SD_Error | SD_WriteBlock (uint8_t *pBuffer, uint32_t WriteAddr, uint16_t BlockSize)
Allows to write one block starting from a specified address in a card.
uint8_t | SD_WriteByte (uint8_t byte)
Write a byte on the SD.
SD_Error | SD_WriteMultiBlocks (uint8_t *pBuffer, uint32_t WriteAddr, uint16_t BlockSize, uint32_t NumberOfBlocks)
Allows to write blocks starting from a specified address in a card.

Detailed Description

This file contains all the functions prototypes for the stm32_eval_spi_sd firmware driver.

Author:
MCD Application Team
Version:
V4.5.0
Date:
07-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm32_eval_spi_sd.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x.h File Reference

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  • STM32F10x_StdPeriph_Lib_V3.5.0
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  • STM32F10x
Data Structures | Defines | Typedefs | Enumerations

stm32f10x.h File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer Header File. This file contains all the peripheral register's definitions, bits definitions and memory mapping for STM32F10x Connectivity line, High density, High density value line, Medium density, Medium density Value line, Low density, Low density Value line and XL-density devices. More...

#include "core_cm3.h"
#include "system_stm32f10x.h"
#include <stdint.h>

Go to the source code of this file.

Data Structures

struct | ADC_TypeDef
Analog to Digital Converter. More...
struct | AFIO_TypeDef
Alternate Function I/O. More...
struct | BKP_TypeDef
Backup Registers. More...
struct | CAN_FIFOMailBox_TypeDef
Controller Area Network FIFOMailBox. More...
struct | CAN_FilterRegister_TypeDef
Controller Area Network FilterRegister. More...
struct | CAN_TxMailBox_TypeDef
Controller Area Network TxMailBox. More...
struct | CAN_TypeDef
Controller Area Network. More...
struct | CEC_TypeDef
Consumer Electronics Control (CEC) More...
struct | CRC_TypeDef
CRC calculation unit. More...
struct | DAC_TypeDef
Digital to Analog Converter. More...
struct | DBGMCU_TypeDef
Debug MCU. More...
struct | DMA_Channel_TypeDef
DMA Controller. More...
struct | DMA_TypeDef
struct | ETH_TypeDef
Ethernet MAC. More...
struct | EXTI_TypeDef
External Interrupt/Event Controller. More...
struct | FLASH_TypeDef
FLASH Registers. More...
struct | FSMC_Bank1_TypeDef
Flexible Static Memory Controller. More...
struct | FSMC_Bank1E_TypeDef
Flexible Static Memory Controller Bank1E. More...
struct | FSMC_Bank2_TypeDef
Flexible Static Memory Controller Bank2. More...
struct | FSMC_Bank3_TypeDef
Flexible Static Memory Controller Bank3. More...
struct | FSMC_Bank4_TypeDef
Flexible Static Memory Controller Bank4. More...
struct | GPIO_TypeDef
General Purpose I/O. More...
struct | I2C_TypeDef
Inter Integrated Circuit Interface. More...
struct | IWDG_TypeDef
Independent WATCHDOG. More...
struct | OB_TypeDef
Option Bytes Registers. More...
struct | PWR_TypeDef
Power Control. More...
struct | RCC_TypeDef
Reset and Clock Control. More...
struct | RTC_TypeDef
Real-Time Clock. More...
struct | SDIO_TypeDef
SD host Interface. More...
struct | SPI_TypeDef
Serial Peripheral Interface. More...
struct | TIM_TypeDef
TIM. More...
struct | USART_TypeDef
Universal Synchronous Asynchronous Receiver Transmitter. More...
struct | WWDG_TypeDef
Window WATCHDOG. More...

Defines

#define | __MPU_PRESENT 0
Configuration of the Cortex-M3 Processor and Core Peripherals.
#define | __NVIC_PRIO_BITS 4
#define | __STM32F10X_STDPERIPH_VERSION
#define | __STM32F10X_STDPERIPH_VERSION_MAIN (0x03)
STM32F10x Standard Peripheral Library version number.
#define | __STM32F10X_STDPERIPH_VERSION_RC (0x00)
#define | __STM32F10X_STDPERIPH_VERSION_SUB1 (0x05)
#define | __STM32F10X_STDPERIPH_VERSION_SUB2 (0x00)
#define | __Vendor_SysTickConfig 0
#define | ADC1 ((ADC_TypeDef *) ADC1_BASE)
#define | ADC1_BASE (APB2PERIPH_BASE + 0x2400)
#define | ADC2 ((ADC_TypeDef *) ADC2_BASE)
#define | ADC2_BASE (APB2PERIPH_BASE + 0x2800)
#define | ADC3 ((ADC_TypeDef *) ADC3_BASE)
#define | ADC3_BASE (APB2PERIPH_BASE + 0x3C00)
#define | ADC_CR1_AWDCH ((uint32_t)0x0000001F)
#define | ADC_CR1_AWDCH_0 ((uint32_t)0x00000001)
#define | ADC_CR1_AWDCH_1 ((uint32_t)0x00000002)
#define | ADC_CR1_AWDCH_2 ((uint32_t)0x00000004)
#define | ADC_CR1_AWDCH_3 ((uint32_t)0x00000008)
#define | ADC_CR1_AWDCH_4 ((uint32_t)0x00000010)
#define | ADC_CR1_AWDEN ((uint32_t)0x00800000)
#define | ADC_CR1_AWDIE ((uint32_t)0x00000040)
#define | ADC_CR1_AWDSGL ((uint32_t)0x00000200)
#define | ADC_CR1_DISCEN ((uint32_t)0x00000800)
#define | ADC_CR1_DISCNUM ((uint32_t)0x0000E000)
#define | ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000)
#define | ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000)
#define | ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000)
#define | ADC_CR1_DUALMOD ((uint32_t)0x000F0000)
#define | ADC_CR1_DUALMOD_0 ((uint32_t)0x00010000)
#define | ADC_CR1_DUALMOD_1 ((uint32_t)0x00020000)
#define | ADC_CR1_DUALMOD_2 ((uint32_t)0x00040000)
#define | ADC_CR1_DUALMOD_3 ((uint32_t)0x00080000)
#define | ADC_CR1_EOCIE ((uint32_t)0x00000020)
#define | ADC_CR1_JAUTO ((uint32_t)0x00000400)
#define | ADC_CR1_JAWDEN ((uint32_t)0x00400000)
#define | ADC_CR1_JDISCEN ((uint32_t)0x00001000)
#define | ADC_CR1_JEOCIE ((uint32_t)0x00000080)
#define | ADC_CR1_SCAN ((uint32_t)0x00000100)
#define | ADC_CR2_ADON ((uint32_t)0x00000001)
#define | ADC_CR2_ALIGN ((uint32_t)0x00000800)
#define | ADC_CR2_CAL ((uint32_t)0x00000004)
#define | ADC_CR2_CONT ((uint32_t)0x00000002)
#define | ADC_CR2_DMA ((uint32_t)0x00000100)
#define | ADC_CR2_EXTSEL ((uint32_t)0x000E0000)
#define | ADC_CR2_EXTSEL_0 ((uint32_t)0x00020000)
#define | ADC_CR2_EXTSEL_1 ((uint32_t)0x00040000)
#define | ADC_CR2_EXTSEL_2 ((uint32_t)0x00080000)
#define | ADC_CR2_EXTTRIG ((uint32_t)0x00100000)
#define | ADC_CR2_JEXTSEL ((uint32_t)0x00007000)
#define | ADC_CR2_JEXTSEL_0 ((uint32_t)0x00001000)
#define | ADC_CR2_JEXTSEL_1 ((uint32_t)0x00002000)
#define | ADC_CR2_JEXTSEL_2 ((uint32_t)0x00004000)
#define | ADC_CR2_JEXTTRIG ((uint32_t)0x00008000)
#define | ADC_CR2_JSWSTART ((uint32_t)0x00200000)
#define | ADC_CR2_RSTCAL ((uint32_t)0x00000008)
#define | ADC_CR2_SWSTART ((uint32_t)0x00400000)
#define | ADC_CR2_TSVREFE ((uint32_t)0x00800000)
#define | ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000)
#define | ADC_DR_DATA ((uint32_t)0x0000FFFF)
#define | ADC_HTR_HT ((uint16_t)0x0FFF)
#define | ADC_JDR1_JDATA ((uint16_t)0xFFFF)
#define | ADC_JDR2_JDATA ((uint16_t)0xFFFF)
#define | ADC_JDR3_JDATA ((uint16_t)0xFFFF)
#define | ADC_JDR4_JDATA ((uint16_t)0xFFFF)
#define | ADC_JOFR1_JOFFSET1 ((uint16_t)0x0FFF)
#define | ADC_JOFR2_JOFFSET2 ((uint16_t)0x0FFF)
#define | ADC_JOFR3_JOFFSET3 ((uint16_t)0x0FFF)
#define | ADC_JOFR4_JOFFSET4 ((uint16_t)0x0FFF)
#define | ADC_JSQR_JL ((uint32_t)0x00300000)
#define | ADC_JSQR_JL_0 ((uint32_t)0x00100000)
#define | ADC_JSQR_JL_1 ((uint32_t)0x00200000)
#define | ADC_JSQR_JSQ1 ((uint32_t)0x0000001F)
#define | ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001)
#define | ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002)
#define | ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004)
#define | ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008)
#define | ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010)
#define | ADC_JSQR_JSQ2 ((uint32_t)0x000003E0)
#define | ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020)
#define | ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040)
#define | ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080)
#define | ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100)
#define | ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200)
#define | ADC_JSQR_JSQ3 ((uint32_t)0x00007C00)
#define | ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400)
#define | ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800)
#define | ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000)
#define | ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000)
#define | ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000)
#define | ADC_JSQR_JSQ4 ((uint32_t)0x000F8000)
#define | ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000)
#define | ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000)
#define | ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000)
#define | ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000)
#define | ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000)
#define | ADC_LTR_LT ((uint16_t)0x0FFF)
#define | ADC_SMPR1_SMP10 ((uint32_t)0x00000007)
#define | ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001)
#define | ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002)
#define | ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004)
#define | ADC_SMPR1_SMP11 ((uint32_t)0x00000038)
#define | ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008)
#define | ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010)
#define | ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020)
#define | ADC_SMPR1_SMP12 ((uint32_t)0x000001C0)
#define | ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040)
#define | ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080)
#define | ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100)
#define | ADC_SMPR1_SMP13 ((uint32_t)0x00000E00)
#define | ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200)
#define | ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400)
#define | ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800)
#define | ADC_SMPR1_SMP14 ((uint32_t)0x00007000)
#define | ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000)
#define | ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000)
#define | ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000)
#define | ADC_SMPR1_SMP15 ((uint32_t)0x00038000)
#define | ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000)
#define | ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000)
#define | ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000)
#define | ADC_SMPR1_SMP16 ((uint32_t)0x001C0000)
#define | ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000)
#define | ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000)
#define | ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000)
#define | ADC_SMPR1_SMP17 ((uint32_t)0x00E00000)
#define | ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000)
#define | ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000)
#define | ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000)
#define | ADC_SMPR2_SMP0 ((uint32_t)0x00000007)
#define | ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001)
#define | ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002)
#define | ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004)
#define | ADC_SMPR2_SMP1 ((uint32_t)0x00000038)
#define | ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008)
#define | ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010)
#define | ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020)
#define | ADC_SMPR2_SMP2 ((uint32_t)0x000001C0)
#define | ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040)
#define | ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080)
#define | ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100)
#define | ADC_SMPR2_SMP3 ((uint32_t)0x00000E00)
#define | ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200)
#define | ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400)
#define | ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800)
#define | ADC_SMPR2_SMP4 ((uint32_t)0x00007000)
#define | ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000)
#define | ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000)
#define | ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000)
#define | ADC_SMPR2_SMP5 ((uint32_t)0x00038000)
#define | ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000)
#define | ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000)
#define | ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000)
#define | ADC_SMPR2_SMP6 ((uint32_t)0x001C0000)
#define | ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000)
#define | ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000)
#define | ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000)
#define | ADC_SMPR2_SMP7 ((uint32_t)0x00E00000)
#define | ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000)
#define | ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000)
#define | ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000)
#define | ADC_SMPR2_SMP8 ((uint32_t)0x07000000)
#define | ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000)
#define | ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000)
#define | ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000)
#define | ADC_SMPR2_SMP9 ((uint32_t)0x38000000)
#define | ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000)
#define | ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000)
#define | ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000)
#define | ADC_SQR1_L ((uint32_t)0x00F00000)
#define | ADC_SQR1_L_0 ((uint32_t)0x00100000)
#define | ADC_SQR1_L_1 ((uint32_t)0x00200000)
#define | ADC_SQR1_L_2 ((uint32_t)0x00400000)
#define | ADC_SQR1_L_3 ((uint32_t)0x00800000)
#define | ADC_SQR1_SQ13 ((uint32_t)0x0000001F)
#define | ADC_SQR1_SQ13_0 ((uint32_t)0x00000001)
#define | ADC_SQR1_SQ13_1 ((uint32_t)0x00000002)
#define | ADC_SQR1_SQ13_2 ((uint32_t)0x00000004)
#define | ADC_SQR1_SQ13_3 ((uint32_t)0x00000008)
#define | ADC_SQR1_SQ13_4 ((uint32_t)0x00000010)
#define | ADC_SQR1_SQ14 ((uint32_t)0x000003E0)
#define | ADC_SQR1_SQ14_0 ((uint32_t)0x00000020)
#define | ADC_SQR1_SQ14_1 ((uint32_t)0x00000040)
#define | ADC_SQR1_SQ14_2 ((uint32_t)0x00000080)
#define | ADC_SQR1_SQ14_3 ((uint32_t)0x00000100)
#define | ADC_SQR1_SQ14_4 ((uint32_t)0x00000200)
#define | ADC_SQR1_SQ15 ((uint32_t)0x00007C00)
#define | ADC_SQR1_SQ15_0 ((uint32_t)0x00000400)
#define | ADC_SQR1_SQ15_1 ((uint32_t)0x00000800)
#define | ADC_SQR1_SQ15_2 ((uint32_t)0x00001000)
#define | ADC_SQR1_SQ15_3 ((uint32_t)0x00002000)
#define | ADC_SQR1_SQ15_4 ((uint32_t)0x00004000)
#define | ADC_SQR1_SQ16 ((uint32_t)0x000F8000)
#define | ADC_SQR1_SQ16_0 ((uint32_t)0x00008000)
#define | ADC_SQR1_SQ16_1 ((uint32_t)0x00010000)
#define | ADC_SQR1_SQ16_2 ((uint32_t)0x00020000)
#define | ADC_SQR1_SQ16_3 ((uint32_t)0x00040000)
#define | ADC_SQR1_SQ16_4 ((uint32_t)0x00080000)
#define | ADC_SQR2_SQ10 ((uint32_t)0x000F8000)
#define | ADC_SQR2_SQ10_0 ((uint32_t)0x00008000)
#define | ADC_SQR2_SQ10_1 ((uint32_t)0x00010000)
#define | ADC_SQR2_SQ10_2 ((uint32_t)0x00020000)
#define | ADC_SQR2_SQ10_3 ((uint32_t)0x00040000)
#define | ADC_SQR2_SQ10_4 ((uint32_t)0x00080000)
#define | ADC_SQR2_SQ11 ((uint32_t)0x01F00000)
#define | ADC_SQR2_SQ11_0 ((uint32_t)0x00100000)
#define | ADC_SQR2_SQ11_1 ((uint32_t)0x00200000)
#define | ADC_SQR2_SQ11_2 ((uint32_t)0x00400000)
#define | ADC_SQR2_SQ11_3 ((uint32_t)0x00800000)
#define | ADC_SQR2_SQ11_4 ((uint32_t)0x01000000)
#define | ADC_SQR2_SQ12 ((uint32_t)0x3E000000)
#define | ADC_SQR2_SQ12_0 ((uint32_t)0x02000000)
#define | ADC_SQR2_SQ12_1 ((uint32_t)0x04000000)
#define | ADC_SQR2_SQ12_2 ((uint32_t)0x08000000)
#define | ADC_SQR2_SQ12_3 ((uint32_t)0x10000000)
#define | ADC_SQR2_SQ12_4 ((uint32_t)0x20000000)
#define | ADC_SQR2_SQ7 ((uint32_t)0x0000001F)
#define | ADC_SQR2_SQ7_0 ((uint32_t)0x00000001)
#define | ADC_SQR2_SQ7_1 ((uint32_t)0x00000002)
#define | ADC_SQR2_SQ7_2 ((uint32_t)0x00000004)
#define | ADC_SQR2_SQ7_3 ((uint32_t)0x00000008)
#define | ADC_SQR2_SQ7_4 ((uint32_t)0x00000010)
#define | ADC_SQR2_SQ8 ((uint32_t)0x000003E0)
#define | ADC_SQR2_SQ8_0 ((uint32_t)0x00000020)
#define | ADC_SQR2_SQ8_1 ((uint32_t)0x00000040)
#define | ADC_SQR2_SQ8_2 ((uint32_t)0x00000080)
#define | ADC_SQR2_SQ8_3 ((uint32_t)0x00000100)
#define | ADC_SQR2_SQ8_4 ((uint32_t)0x00000200)
#define | ADC_SQR2_SQ9 ((uint32_t)0x00007C00)
#define | ADC_SQR2_SQ9_0 ((uint32_t)0x00000400)
#define | ADC_SQR2_SQ9_1 ((uint32_t)0x00000800)
#define | ADC_SQR2_SQ9_2 ((uint32_t)0x00001000)
#define | ADC_SQR2_SQ9_3 ((uint32_t)0x00002000)
#define | ADC_SQR2_SQ9_4 ((uint32_t)0x00004000)
#define | ADC_SQR3_SQ1 ((uint32_t)0x0000001F)
#define | ADC_SQR3_SQ1_0 ((uint32_t)0x00000001)
#define | ADC_SQR3_SQ1_1 ((uint32_t)0x00000002)
#define | ADC_SQR3_SQ1_2 ((uint32_t)0x00000004)
#define | ADC_SQR3_SQ1_3 ((uint32_t)0x00000008)
#define | ADC_SQR3_SQ1_4 ((uint32_t)0x00000010)
#define | ADC_SQR3_SQ2 ((uint32_t)0x000003E0)
#define | ADC_SQR3_SQ2_0 ((uint32_t)0x00000020)
#define | ADC_SQR3_SQ2_1 ((uint32_t)0x00000040)
#define | ADC_SQR3_SQ2_2 ((uint32_t)0x00000080)
#define | ADC_SQR3_SQ2_3 ((uint32_t)0x00000100)
#define | ADC_SQR3_SQ2_4 ((uint32_t)0x00000200)
#define | ADC_SQR3_SQ3 ((uint32_t)0x00007C00)
#define | ADC_SQR3_SQ3_0 ((uint32_t)0x00000400)
#define | ADC_SQR3_SQ3_1 ((uint32_t)0x00000800)
#define | ADC_SQR3_SQ3_2 ((uint32_t)0x00001000)
#define | ADC_SQR3_SQ3_3 ((uint32_t)0x00002000)
#define | ADC_SQR3_SQ3_4 ((uint32_t)0x00004000)
#define | ADC_SQR3_SQ4 ((uint32_t)0x000F8000)
#define | ADC_SQR3_SQ4_0 ((uint32_t)0x00008000)
#define | ADC_SQR3_SQ4_1 ((uint32_t)0x00010000)
#define | ADC_SQR3_SQ4_2 ((uint32_t)0x00020000)
#define | ADC_SQR3_SQ4_3 ((uint32_t)0x00040000)
#define | ADC_SQR3_SQ4_4 ((uint32_t)0x00080000)
#define | ADC_SQR3_SQ5 ((uint32_t)0x01F00000)
#define | ADC_SQR3_SQ5_0 ((uint32_t)0x00100000)
#define | ADC_SQR3_SQ5_1 ((uint32_t)0x00200000)
#define | ADC_SQR3_SQ5_2 ((uint32_t)0x00400000)
#define | ADC_SQR3_SQ5_3 ((uint32_t)0x00800000)
#define | ADC_SQR3_SQ5_4 ((uint32_t)0x01000000)
#define | ADC_SQR3_SQ6 ((uint32_t)0x3E000000)
#define | ADC_SQR3_SQ6_0 ((uint32_t)0x02000000)
#define | ADC_SQR3_SQ6_1 ((uint32_t)0x04000000)
#define | ADC_SQR3_SQ6_2 ((uint32_t)0x08000000)
#define | ADC_SQR3_SQ6_3 ((uint32_t)0x10000000)
#define | ADC_SQR3_SQ6_4 ((uint32_t)0x20000000)
#define | ADC_SR_AWD ((uint8_t)0x01)
#define | ADC_SR_EOC ((uint8_t)0x02)
#define | ADC_SR_JEOC ((uint8_t)0x04)
#define | ADC_SR_JSTRT ((uint8_t)0x08)
#define | ADC_SR_STRT ((uint8_t)0x10)
#define | AFIO ((AFIO_TypeDef *) AFIO_BASE)
#define | AFIO_BASE (APB2PERIPH_BASE + 0x0000)
#define | AFIO_EVCR_EVOE ((uint8_t)0x80)
#define | AFIO_EVCR_PIN ((uint8_t)0x0F)
#define | AFIO_EVCR_PIN_0 ((uint8_t)0x01)
#define | AFIO_EVCR_PIN_1 ((uint8_t)0x02)
#define | AFIO_EVCR_PIN_2 ((uint8_t)0x04)
#define | AFIO_EVCR_PIN_3 ((uint8_t)0x08)
#define | AFIO_EVCR_PIN_PX0 ((uint8_t)0x00)
#define | AFIO_EVCR_PIN_PX1 ((uint8_t)0x01)
#define | AFIO_EVCR_PIN_PX10 ((uint8_t)0x0A)
#define | AFIO_EVCR_PIN_PX11 ((uint8_t)0x0B)
#define | AFIO_EVCR_PIN_PX12 ((uint8_t)0x0C)
#define | AFIO_EVCR_PIN_PX13 ((uint8_t)0x0D)
#define | AFIO_EVCR_PIN_PX14 ((uint8_t)0x0E)
#define | AFIO_EVCR_PIN_PX15 ((uint8_t)0x0F)
#define | AFIO_EVCR_PIN_PX2 ((uint8_t)0x02)
#define | AFIO_EVCR_PIN_PX3 ((uint8_t)0x03)
#define | AFIO_EVCR_PIN_PX4 ((uint8_t)0x04)
#define | AFIO_EVCR_PIN_PX5 ((uint8_t)0x05)
#define | AFIO_EVCR_PIN_PX6 ((uint8_t)0x06)
#define | AFIO_EVCR_PIN_PX7 ((uint8_t)0x07)
#define | AFIO_EVCR_PIN_PX8 ((uint8_t)0x08)
#define | AFIO_EVCR_PIN_PX9 ((uint8_t)0x09)
#define | AFIO_EVCR_PORT ((uint8_t)0x70)
#define | AFIO_EVCR_PORT_0 ((uint8_t)0x10)
#define | AFIO_EVCR_PORT_1 ((uint8_t)0x20)
#define | AFIO_EVCR_PORT_2 ((uint8_t)0x40)
#define | AFIO_EVCR_PORT_PA ((uint8_t)0x00)
#define | AFIO_EVCR_PORT_PB ((uint8_t)0x10)
#define | AFIO_EVCR_PORT_PC ((uint8_t)0x20)
#define | AFIO_EVCR_PORT_PD ((uint8_t)0x30)
#define | AFIO_EVCR_PORT_PE ((uint8_t)0x40)
#define | AFIO_EXTICR1_EXTI0 ((uint16_t)0x000F)
#define | AFIO_EXTICR1_EXTI0_PA ((uint16_t)0x0000)
#define | AFIO_EXTICR1_EXTI0_PB ((uint16_t)0x0001)
#define | AFIO_EXTICR1_EXTI0_PC ((uint16_t)0x0002)
#define | AFIO_EXTICR1_EXTI0_PD ((uint16_t)0x0003)
#define | AFIO_EXTICR1_EXTI0_PE ((uint16_t)0x0004)
#define | AFIO_EXTICR1_EXTI0_PF ((uint16_t)0x0005)
#define | AFIO_EXTICR1_EXTI0_PG ((uint16_t)0x0006)
#define | AFIO_EXTICR1_EXTI1 ((uint16_t)0x00F0)
#define | AFIO_EXTICR1_EXTI1_PA ((uint16_t)0x0000)
#define | AFIO_EXTICR1_EXTI1_PB ((uint16_t)0x0010)
#define | AFIO_EXTICR1_EXTI1_PC ((uint16_t)0x0020)
#define | AFIO_EXTICR1_EXTI1_PD ((uint16_t)0x0030)
#define | AFIO_EXTICR1_EXTI1_PE ((uint16_t)0x0040)
#define | AFIO_EXTICR1_EXTI1_PF ((uint16_t)0x0050)
#define | AFIO_EXTICR1_EXTI1_PG ((uint16_t)0x0060)
#define | AFIO_EXTICR1_EXTI2 ((uint16_t)0x0F00)
#define | AFIO_EXTICR1_EXTI2_PA ((uint16_t)0x0000)
#define | AFIO_EXTICR1_EXTI2_PB ((uint16_t)0x0100)
#define | AFIO_EXTICR1_EXTI2_PC ((uint16_t)0x0200)
#define | AFIO_EXTICR1_EXTI2_PD ((uint16_t)0x0300)
#define | AFIO_EXTICR1_EXTI2_PE ((uint16_t)0x0400)
#define | AFIO_EXTICR1_EXTI2_PF ((uint16_t)0x0500)
#define | AFIO_EXTICR1_EXTI2_PG ((uint16_t)0x0600)
#define | AFIO_EXTICR1_EXTI3 ((uint16_t)0xF000)
#define | AFIO_EXTICR1_EXTI3_PA ((uint16_t)0x0000)
#define | AFIO_EXTICR1_EXTI3_PB ((uint16_t)0x1000)
#define | AFIO_EXTICR1_EXTI3_PC ((uint16_t)0x2000)
#define | AFIO_EXTICR1_EXTI3_PD ((uint16_t)0x3000)
#define | AFIO_EXTICR1_EXTI3_PE ((uint16_t)0x4000)
#define | AFIO_EXTICR1_EXTI3_PF ((uint16_t)0x5000)
#define | AFIO_EXTICR1_EXTI3_PG ((uint16_t)0x6000)
#define | AFIO_EXTICR2_EXTI4 ((uint16_t)0x000F)
#define | AFIO_EXTICR2_EXTI4_PA ((uint16_t)0x0000)
#define | AFIO_EXTICR2_EXTI4_PB ((uint16_t)0x0001)
#define | AFIO_EXTICR2_EXTI4_PC ((uint16_t)0x0002)
#define | AFIO_EXTICR2_EXTI4_PD ((uint16_t)0x0003)
#define | AFIO_EXTICR2_EXTI4_PE ((uint16_t)0x0004)
#define | AFIO_EXTICR2_EXTI4_PF ((uint16_t)0x0005)
#define | AFIO_EXTICR2_EXTI4_PG ((uint16_t)0x0006)
#define | AFIO_EXTICR2_EXTI5 ((uint16_t)0x00F0)
#define | AFIO_EXTICR2_EXTI5_PA ((uint16_t)0x0000)
#define | AFIO_EXTICR2_EXTI5_PB ((uint16_t)0x0010)
#define | AFIO_EXTICR2_EXTI5_PC ((uint16_t)0x0020)
#define | AFIO_EXTICR2_EXTI5_PD ((uint16_t)0x0030)
#define | AFIO_EXTICR2_EXTI5_PE ((uint16_t)0x0040)
#define | AFIO_EXTICR2_EXTI5_PF ((uint16_t)0x0050)
#define | AFIO_EXTICR2_EXTI5_PG ((uint16_t)0x0060)
#define | AFIO_EXTICR2_EXTI6 ((uint16_t)0x0F00)
#define | AFIO_EXTICR2_EXTI6_PA ((uint16_t)0x0000)
#define | AFIO_EXTICR2_EXTI6_PB ((uint16_t)0x0100)
#define | AFIO_EXTICR2_EXTI6_PC ((uint16_t)0x0200)
#define | AFIO_EXTICR2_EXTI6_PD ((uint16_t)0x0300)
#define | AFIO_EXTICR2_EXTI6_PE ((uint16_t)0x0400)
#define | AFIO_EXTICR2_EXTI6_PF ((uint16_t)0x0500)
#define | AFIO_EXTICR2_EXTI6_PG ((uint16_t)0x0600)
#define | AFIO_EXTICR2_EXTI7 ((uint16_t)0xF000)
#define | AFIO_EXTICR2_EXTI7_PA ((uint16_t)0x0000)
#define | AFIO_EXTICR2_EXTI7_PB ((uint16_t)0x1000)
#define | AFIO_EXTICR2_EXTI7_PC ((uint16_t)0x2000)
#define | AFIO_EXTICR2_EXTI7_PD ((uint16_t)0x3000)
#define | AFIO_EXTICR2_EXTI7_PE ((uint16_t)0x4000)
#define | AFIO_EXTICR2_EXTI7_PF ((uint16_t)0x5000)
#define | AFIO_EXTICR2_EXTI7_PG ((uint16_t)0x6000)
#define | AFIO_EXTICR3_EXTI10 ((uint16_t)0x0F00)
#define | AFIO_EXTICR3_EXTI10_PA ((uint16_t)0x0000)
#define | AFIO_EXTICR3_EXTI10_PB ((uint16_t)0x0100)
#define | AFIO_EXTICR3_EXTI10_PC ((uint16_t)0x0200)
#define | AFIO_EXTICR3_EXTI10_PD ((uint16_t)0x0300)
#define | AFIO_EXTICR3_EXTI10_PE ((uint16_t)0x0400)
#define | AFIO_EXTICR3_EXTI10_PF ((uint16_t)0x0500)
#define | AFIO_EXTICR3_EXTI10_PG ((uint16_t)0x0600)
#define | AFIO_EXTICR3_EXTI11 ((uint16_t)0xF000)
#define | AFIO_EXTICR3_EXTI11_PA ((uint16_t)0x0000)
#define | AFIO_EXTICR3_EXTI11_PB ((uint16_t)0x1000)
#define | AFIO_EXTICR3_EXTI11_PC ((uint16_t)0x2000)
#define | AFIO_EXTICR3_EXTI11_PD ((uint16_t)0x3000)
#define | AFIO_EXTICR3_EXTI11_PE ((uint16_t)0x4000)
#define | AFIO_EXTICR3_EXTI11_PF ((uint16_t)0x5000)
#define | AFIO_EXTICR3_EXTI11_PG ((uint16_t)0x6000)
#define | AFIO_EXTICR3_EXTI8 ((uint16_t)0x000F)
#define | AFIO_EXTICR3_EXTI8_PA ((uint16_t)0x0000)
#define | AFIO_EXTICR3_EXTI8_PB ((uint16_t)0x0001)
#define | AFIO_EXTICR3_EXTI8_PC ((uint16_t)0x0002)
#define | AFIO_EXTICR3_EXTI8_PD ((uint16_t)0x0003)
#define | AFIO_EXTICR3_EXTI8_PE ((uint16_t)0x0004)
#define | AFIO_EXTICR3_EXTI8_PF ((uint16_t)0x0005)
#define | AFIO_EXTICR3_EXTI8_PG ((uint16_t)0x0006)
#define | AFIO_EXTICR3_EXTI9 ((uint16_t)0x00F0)
#define | AFIO_EXTICR3_EXTI9_PA ((uint16_t)0x0000)
#define | AFIO_EXTICR3_EXTI9_PB ((uint16_t)0x0010)
#define | AFIO_EXTICR3_EXTI9_PC ((uint16_t)0x0020)
#define | AFIO_EXTICR3_EXTI9_PD ((uint16_t)0x0030)
#define | AFIO_EXTICR3_EXTI9_PE ((uint16_t)0x0040)
#define | AFIO_EXTICR3_EXTI9_PF ((uint16_t)0x0050)
#define | AFIO_EXTICR3_EXTI9_PG ((uint16_t)0x0060)
#define | AFIO_EXTICR4_EXTI12 ((uint16_t)0x000F)
#define | AFIO_EXTICR4_EXTI12_PA ((uint16_t)0x0000)
#define | AFIO_EXTICR4_EXTI12_PB ((uint16_t)0x0001)
#define | AFIO_EXTICR4_EXTI12_PC ((uint16_t)0x0002)
#define | AFIO_EXTICR4_EXTI12_PD ((uint16_t)0x0003)
#define | AFIO_EXTICR4_EXTI12_PE ((uint16_t)0x0004)
#define | AFIO_EXTICR4_EXTI12_PF ((uint16_t)0x0005)
#define | AFIO_EXTICR4_EXTI12_PG ((uint16_t)0x0006)
#define | AFIO_EXTICR4_EXTI13 ((uint16_t)0x00F0)
#define | AFIO_EXTICR4_EXTI13_PA ((uint16_t)0x0000)
#define | AFIO_EXTICR4_EXTI13_PB ((uint16_t)0x0010)
#define | AFIO_EXTICR4_EXTI13_PC ((uint16_t)0x0020)
#define | AFIO_EXTICR4_EXTI13_PD ((uint16_t)0x0030)
#define | AFIO_EXTICR4_EXTI13_PE ((uint16_t)0x0040)
#define | AFIO_EXTICR4_EXTI13_PF ((uint16_t)0x0050)
#define | AFIO_EXTICR4_EXTI13_PG ((uint16_t)0x0060)
#define | AFIO_EXTICR4_EXTI14 ((uint16_t)0x0F00)
#define | AFIO_EXTICR4_EXTI14_PA ((uint16_t)0x0000)
#define | AFIO_EXTICR4_EXTI14_PB ((uint16_t)0x0100)
#define | AFIO_EXTICR4_EXTI14_PC ((uint16_t)0x0200)
#define | AFIO_EXTICR4_EXTI14_PD ((uint16_t)0x0300)
#define | AFIO_EXTICR4_EXTI14_PE ((uint16_t)0x0400)
#define | AFIO_EXTICR4_EXTI14_PF ((uint16_t)0x0500)
#define | AFIO_EXTICR4_EXTI14_PG ((uint16_t)0x0600)
#define | AFIO_EXTICR4_EXTI15 ((uint16_t)0xF000)
#define | AFIO_EXTICR4_EXTI15_PA ((uint16_t)0x0000)
#define | AFIO_EXTICR4_EXTI15_PB ((uint16_t)0x1000)
#define | AFIO_EXTICR4_EXTI15_PC ((uint16_t)0x2000)
#define | AFIO_EXTICR4_EXTI15_PD ((uint16_t)0x3000)
#define | AFIO_EXTICR4_EXTI15_PE ((uint16_t)0x4000)
#define | AFIO_EXTICR4_EXTI15_PF ((uint16_t)0x5000)
#define | AFIO_EXTICR4_EXTI15_PG ((uint16_t)0x6000)
#define | AFIO_MAPR_ADC1_ETRGINJ_REMAP ((uint32_t)0x00020000)
#define | AFIO_MAPR_ADC1_ETRGREG_REMAP ((uint32_t)0x00040000)
#define | AFIO_MAPR_ADC2_ETRGINJ_REMAP ((uint32_t)0x00080000)
#define | AFIO_MAPR_ADC2_ETRGREG_REMAP ((uint32_t)0x00100000)
#define | AFIO_MAPR_CAN_REMAP ((uint32_t)0x00006000)
#define | AFIO_MAPR_CAN_REMAP_0 ((uint32_t)0x00002000)
#define | AFIO_MAPR_CAN_REMAP_1 ((uint32_t)0x00004000)
#define | AFIO_MAPR_CAN_REMAP_REMAP1 ((uint32_t)0x00000000)
#define | AFIO_MAPR_CAN_REMAP_REMAP2 ((uint32_t)0x00004000)
#define | AFIO_MAPR_CAN_REMAP_REMAP3 ((uint32_t)0x00006000)
#define | AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002)
#define | AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000)
#define | AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001)
#define | AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000)
#define | AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000)
#define | AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000)
#define | AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000)
#define | AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000)
#define | AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000)
#define | AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000)
#define | AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000)
#define | AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0)
#define | AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040)
#define | AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080)
#define | AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0)
#define | AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000)
#define | AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040)
#define | AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300)
#define | AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100)
#define | AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200)
#define | AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300)
#define | AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000)
#define | AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100)
#define | AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200)
#define | AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00)
#define | AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400)
#define | AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800)
#define | AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00)
#define | AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000)
#define | AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800)
#define | AFIO_MAPR_TIM4_REMAP ((uint32_t)0x00001000)
#define | AFIO_MAPR_TIM5CH4_IREMAP ((uint32_t)0x00010000)
#define | AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004)
#define | AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008)
#define | AFIO_MAPR_USART3_REMAP ((uint32_t)0x00000030)
#define | AFIO_MAPR_USART3_REMAP_0 ((uint32_t)0x00000010)
#define | AFIO_MAPR_USART3_REMAP_1 ((uint32_t)0x00000020)
#define | AFIO_MAPR_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030)
#define | AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000)
#define | AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010)
#define | AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
#define | APB1PERIPH_BASE PERIPH_BASE
#define | APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
#define | BKP ((BKP_TypeDef *) BKP_BASE)
#define | BKP_BASE (APB1PERIPH_BASE + 0x6C00)
#define | BKP_CR_TPAL ((uint8_t)0x02)
#define | BKP_CR_TPE ((uint8_t)0x01)
#define | BKP_CSR_CTE ((uint16_t)0x0001)
#define | BKP_CSR_CTI ((uint16_t)0x0002)
#define | BKP_CSR_TEF ((uint16_t)0x0100)
#define | BKP_CSR_TIF ((uint16_t)0x0200)
#define | BKP_CSR_TPIE ((uint16_t)0x0004)
#define | BKP_DR10_D ((uint16_t)0xFFFF)
#define | BKP_DR11_D ((uint16_t)0xFFFF)
#define | BKP_DR12_D ((uint16_t)0xFFFF)
#define | BKP_DR13_D ((uint16_t)0xFFFF)
#define | BKP_DR14_D ((uint16_t)0xFFFF)
#define | BKP_DR15_D ((uint16_t)0xFFFF)
#define | BKP_DR16_D ((uint16_t)0xFFFF)
#define | BKP_DR17_D ((uint16_t)0xFFFF)
#define | BKP_DR18_D ((uint16_t)0xFFFF)
#define | BKP_DR19_D ((uint16_t)0xFFFF)
#define | BKP_DR1_D ((uint16_t)0xFFFF)
#define | BKP_DR20_D ((uint16_t)0xFFFF)
#define | BKP_DR21_D ((uint16_t)0xFFFF)
#define | BKP_DR22_D ((uint16_t)0xFFFF)
#define | BKP_DR23_D ((uint16_t)0xFFFF)
#define | BKP_DR24_D ((uint16_t)0xFFFF)
#define | BKP_DR25_D ((uint16_t)0xFFFF)
#define | BKP_DR26_D ((uint16_t)0xFFFF)
#define | BKP_DR27_D ((uint16_t)0xFFFF)
#define | BKP_DR28_D ((uint16_t)0xFFFF)
#define | BKP_DR29_D ((uint16_t)0xFFFF)
#define | BKP_DR2_D ((uint16_t)0xFFFF)
#define | BKP_DR30_D ((uint16_t)0xFFFF)
#define | BKP_DR31_D ((uint16_t)0xFFFF)
#define | BKP_DR32_D ((uint16_t)0xFFFF)
#define | BKP_DR33_D ((uint16_t)0xFFFF)
#define | BKP_DR34_D ((uint16_t)0xFFFF)
#define | BKP_DR35_D ((uint16_t)0xFFFF)
#define | BKP_DR36_D ((uint16_t)0xFFFF)
#define | BKP_DR37_D ((uint16_t)0xFFFF)
#define | BKP_DR38_D ((uint16_t)0xFFFF)
#define | BKP_DR39_D ((uint16_t)0xFFFF)
#define | BKP_DR3_D ((uint16_t)0xFFFF)
#define | BKP_DR40_D ((uint16_t)0xFFFF)
#define | BKP_DR41_D ((uint16_t)0xFFFF)
#define | BKP_DR42_D ((uint16_t)0xFFFF)
#define | BKP_DR4_D ((uint16_t)0xFFFF)
#define | BKP_DR5_D ((uint16_t)0xFFFF)
#define | BKP_DR6_D ((uint16_t)0xFFFF)
#define | BKP_DR7_D ((uint16_t)0xFFFF)
#define | BKP_DR8_D ((uint16_t)0xFFFF)
#define | BKP_DR9_D ((uint16_t)0xFFFF)
#define | BKP_RTCCR_ASOE ((uint16_t)0x0100)
#define | BKP_RTCCR_ASOS ((uint16_t)0x0200)
#define | BKP_RTCCR_CAL ((uint16_t)0x007F)
#define | BKP_RTCCR_CCO ((uint16_t)0x0080)
#define | CAN1 ((CAN_TypeDef *) CAN1_BASE)
#define | CAN1_BASE (APB1PERIPH_BASE + 0x6400)
#define | CAN2 ((CAN_TypeDef *) CAN2_BASE)
#define | CAN2_BASE (APB1PERIPH_BASE + 0x6800)
#define | CAN_BTR_BRP ((uint32_t)0x000003FF)
#define | CAN_BTR_LBKM ((uint32_t)0x40000000)
#define | CAN_BTR_SILM ((uint32_t)0x80000000)
#define | CAN_BTR_SJW ((uint32_t)0x03000000)
#define | CAN_BTR_TS1 ((uint32_t)0x000F0000)
#define | CAN_BTR_TS2 ((uint32_t)0x00700000)
#define | CAN_ESR_BOFF ((uint32_t)0x00000004)
#define | CAN_ESR_EPVF ((uint32_t)0x00000002)
#define | CAN_ESR_EWGF ((uint32_t)0x00000001)
#define | CAN_ESR_LEC ((uint32_t)0x00000070)
#define | CAN_ESR_LEC_0 ((uint32_t)0x00000010)
#define | CAN_ESR_LEC_1 ((uint32_t)0x00000020)
#define | CAN_ESR_LEC_2 ((uint32_t)0x00000040)
#define | CAN_ESR_REC ((uint32_t)0xFF000000)
#define | CAN_ESR_TEC ((uint32_t)0x00FF0000)
#define | CAN_F0R1_FB0 ((uint32_t)0x00000001)
#define | CAN_F0R1_FB1 ((uint32_t)0x00000002)
#define | CAN_F0R1_FB10 ((uint32_t)0x00000400)
#define | CAN_F0R1_FB11 ((uint32_t)0x00000800)
#define | CAN_F0R1_FB12 ((uint32_t)0x00001000)
#define | CAN_F0R1_FB13 ((uint32_t)0x00002000)
#define | CAN_F0R1_FB14 ((uint32_t)0x00004000)
#define | CAN_F0R1_FB15 ((uint32_t)0x00008000)
#define | CAN_F0R1_FB16 ((uint32_t)0x00010000)
#define | CAN_F0R1_FB17 ((uint32_t)0x00020000)
#define | CAN_F0R1_FB18 ((uint32_t)0x00040000)
#define | CAN_F0R1_FB19 ((uint32_t)0x00080000)
#define | CAN_F0R1_FB2 ((uint32_t)0x00000004)
#define | CAN_F0R1_FB20 ((uint32_t)0x00100000)
#define | CAN_F0R1_FB21 ((uint32_t)0x00200000)
#define | CAN_F0R1_FB22 ((uint32_t)0x00400000)
#define | CAN_F0R1_FB23 ((uint32_t)0x00800000)
#define | CAN_F0R1_FB24 ((uint32_t)0x01000000)
#define | CAN_F0R1_FB25 ((uint32_t)0x02000000)
#define | CAN_F0R1_FB26 ((uint32_t)0x04000000)
#define | CAN_F0R1_FB27 ((uint32_t)0x08000000)
#define | CAN_F0R1_FB28 ((uint32_t)0x10000000)
#define | CAN_F0R1_FB29 ((uint32_t)0x20000000)
#define | CAN_F0R1_FB3 ((uint32_t)0x00000008)
#define | CAN_F0R1_FB30 ((uint32_t)0x40000000)
#define | CAN_F0R1_FB31 ((uint32_t)0x80000000)
#define | CAN_F0R1_FB4 ((uint32_t)0x00000010)
#define | CAN_F0R1_FB5 ((uint32_t)0x00000020)
#define | CAN_F0R1_FB6 ((uint32_t)0x00000040)
#define | CAN_F0R1_FB7 ((uint32_t)0x00000080)
#define | CAN_F0R1_FB8 ((uint32_t)0x00000100)
#define | CAN_F0R1_FB9 ((uint32_t)0x00000200)
#define | CAN_F0R2_FB0 ((uint32_t)0x00000001)
#define | CAN_F0R2_FB1 ((uint32_t)0x00000002)
#define | CAN_F0R2_FB10 ((uint32_t)0x00000400)
#define | CAN_F0R2_FB11 ((uint32_t)0x00000800)
#define | CAN_F0R2_FB12 ((uint32_t)0x00001000)
#define | CAN_F0R2_FB13 ((uint32_t)0x00002000)
#define | CAN_F0R2_FB14 ((uint32_t)0x00004000)
#define | CAN_F0R2_FB15 ((uint32_t)0x00008000)
#define | CAN_F0R2_FB16 ((uint32_t)0x00010000)
#define | CAN_F0R2_FB17 ((uint32_t)0x00020000)
#define | CAN_F0R2_FB18 ((uint32_t)0x00040000)
#define | CAN_F0R2_FB19 ((uint32_t)0x00080000)
#define | CAN_F0R2_FB2 ((uint32_t)0x00000004)
#define | CAN_F0R2_FB20 ((uint32_t)0x00100000)
#define | CAN_F0R2_FB21 ((uint32_t)0x00200000)
#define | CAN_F0R2_FB22 ((uint32_t)0x00400000)
#define | CAN_F0R2_FB23 ((uint32_t)0x00800000)
#define | CAN_F0R2_FB24 ((uint32_t)0x01000000)
#define | CAN_F0R2_FB25 ((uint32_t)0x02000000)
#define | CAN_F0R2_FB26 ((uint32_t)0x04000000)
#define | CAN_F0R2_FB27 ((uint32_t)0x08000000)
#define | CAN_F0R2_FB28 ((uint32_t)0x10000000)
#define | CAN_F0R2_FB29 ((uint32_t)0x20000000)
#define | CAN_F0R2_FB3 ((uint32_t)0x00000008)
#define | CAN_F0R2_FB30 ((uint32_t)0x40000000)
#define | CAN_F0R2_FB31 ((uint32_t)0x80000000)
#define | CAN_F0R2_FB4 ((uint32_t)0x00000010)
#define | CAN_F0R2_FB5 ((uint32_t)0x00000020)
#define | CAN_F0R2_FB6 ((uint32_t)0x00000040)
#define | CAN_F0R2_FB7 ((uint32_t)0x00000080)
#define | CAN_F0R2_FB8 ((uint32_t)0x00000100)
#define | CAN_F0R2_FB9 ((uint32_t)0x00000200)
#define | CAN_F10R1_FB0 ((uint32_t)0x00000001)
#define | CAN_F10R1_FB1 ((uint32_t)0x00000002)
#define | CAN_F10R1_FB10 ((uint32_t)0x00000400)
#define | CAN_F10R1_FB11 ((uint32_t)0x00000800)
#define | CAN_F10R1_FB12 ((uint32_t)0x00001000)
#define | CAN_F10R1_FB13 ((uint32_t)0x00002000)
#define | CAN_F10R1_FB14 ((uint32_t)0x00004000)
#define | CAN_F10R1_FB15 ((uint32_t)0x00008000)
#define | CAN_F10R1_FB16 ((uint32_t)0x00010000)
#define | CAN_F10R1_FB17 ((uint32_t)0x00020000)
#define | CAN_F10R1_FB18 ((uint32_t)0x00040000)
#define | CAN_F10R1_FB19 ((uint32_t)0x00080000)
#define | CAN_F10R1_FB2 ((uint32_t)0x00000004)
#define | CAN_F10R1_FB20 ((uint32_t)0x00100000)
#define | CAN_F10R1_FB21 ((uint32_t)0x00200000)
#define | CAN_F10R1_FB22 ((uint32_t)0x00400000)
#define | CAN_F10R1_FB23 ((uint32_t)0x00800000)
#define | CAN_F10R1_FB24 ((uint32_t)0x01000000)
#define | CAN_F10R1_FB25 ((uint32_t)0x02000000)
#define | CAN_F10R1_FB26 ((uint32_t)0x04000000)
#define | CAN_F10R1_FB27 ((uint32_t)0x08000000)
#define | CAN_F10R1_FB28 ((uint32_t)0x10000000)
#define | CAN_F10R1_FB29 ((uint32_t)0x20000000)
#define | CAN_F10R1_FB3 ((uint32_t)0x00000008)
#define | CAN_F10R1_FB30 ((uint32_t)0x40000000)
#define | CAN_F10R1_FB31 ((uint32_t)0x80000000)
#define | CAN_F10R1_FB4 ((uint32_t)0x00000010)
#define | CAN_F10R1_FB5 ((uint32_t)0x00000020)
#define | CAN_F10R1_FB6 ((uint32_t)0x00000040)
#define | CAN_F10R1_FB7 ((uint32_t)0x00000080)
#define | CAN_F10R1_FB8 ((uint32_t)0x00000100)
#define | CAN_F10R1_FB9 ((uint32_t)0x00000200)
#define | CAN_F10R2_FB0 ((uint32_t)0x00000001)
#define | CAN_F10R2_FB1 ((uint32_t)0x00000002)
#define | CAN_F10R2_FB10 ((uint32_t)0x00000400)
#define | CAN_F10R2_FB11 ((uint32_t)0x00000800)
#define | CAN_F10R2_FB12 ((uint32_t)0x00001000)
#define | CAN_F10R2_FB13 ((uint32_t)0x00002000)
#define | CAN_F10R2_FB14 ((uint32_t)0x00004000)
#define | CAN_F10R2_FB15 ((uint32_t)0x00008000)
#define | CAN_F10R2_FB16 ((uint32_t)0x00010000)
#define | CAN_F10R2_FB17 ((uint32_t)0x00020000)
#define | CAN_F10R2_FB18 ((uint32_t)0x00040000)
#define | CAN_F10R2_FB19 ((uint32_t)0x00080000)
#define | CAN_F10R2_FB2 ((uint32_t)0x00000004)
#define | CAN_F10R2_FB20 ((uint32_t)0x00100000)
#define | CAN_F10R2_FB21 ((uint32_t)0x00200000)
#define | CAN_F10R2_FB22 ((uint32_t)0x00400000)
#define | CAN_F10R2_FB23 ((uint32_t)0x00800000)
#define | CAN_F10R2_FB24 ((uint32_t)0x01000000)
#define | CAN_F10R2_FB25 ((uint32_t)0x02000000)
#define | CAN_F10R2_FB26 ((uint32_t)0x04000000)
#define | CAN_F10R2_FB27 ((uint32_t)0x08000000)
#define | CAN_F10R2_FB28 ((uint32_t)0x10000000)
#define | CAN_F10R2_FB29 ((uint32_t)0x20000000)
#define | CAN_F10R2_FB3 ((uint32_t)0x00000008)
#define | CAN_F10R2_FB30 ((uint32_t)0x40000000)
#define | CAN_F10R2_FB31 ((uint32_t)0x80000000)
#define | CAN_F10R2_FB4 ((uint32_t)0x00000010)
#define | CAN_F10R2_FB5 ((uint32_t)0x00000020)
#define | CAN_F10R2_FB6 ((uint32_t)0x00000040)
#define | CAN_F10R2_FB7 ((uint32_t)0x00000080)
#define | CAN_F10R2_FB8 ((uint32_t)0x00000100)
#define | CAN_F10R2_FB9 ((uint32_t)0x00000200)
#define | CAN_F11R1_FB0 ((uint32_t)0x00000001)
#define | CAN_F11R1_FB1 ((uint32_t)0x00000002)
#define | CAN_F11R1_FB10 ((uint32_t)0x00000400)
#define | CAN_F11R1_FB11 ((uint32_t)0x00000800)
#define | CAN_F11R1_FB12 ((uint32_t)0x00001000)
#define | CAN_F11R1_FB13 ((uint32_t)0x00002000)
#define | CAN_F11R1_FB14 ((uint32_t)0x00004000)
#define | CAN_F11R1_FB15 ((uint32_t)0x00008000)
#define | CAN_F11R1_FB16 ((uint32_t)0x00010000)
#define | CAN_F11R1_FB17 ((uint32_t)0x00020000)
#define | CAN_F11R1_FB18 ((uint32_t)0x00040000)
#define | CAN_F11R1_FB19 ((uint32_t)0x00080000)
#define | CAN_F11R1_FB2 ((uint32_t)0x00000004)
#define | CAN_F11R1_FB20 ((uint32_t)0x00100000)
#define | CAN_F11R1_FB21 ((uint32_t)0x00200000)
#define | CAN_F11R1_FB22 ((uint32_t)0x00400000)
#define | CAN_F11R1_FB23 ((uint32_t)0x00800000)
#define | CAN_F11R1_FB24 ((uint32_t)0x01000000)
#define | CAN_F11R1_FB25 ((uint32_t)0x02000000)
#define | CAN_F11R1_FB26 ((uint32_t)0x04000000)
#define | CAN_F11R1_FB27 ((uint32_t)0x08000000)
#define | CAN_F11R1_FB28 ((uint32_t)0x10000000)
#define | CAN_F11R1_FB29 ((uint32_t)0x20000000)
#define | CAN_F11R1_FB3 ((uint32_t)0x00000008)
#define | CAN_F11R1_FB30 ((uint32_t)0x40000000)
#define | CAN_F11R1_FB31 ((uint32_t)0x80000000)
#define | CAN_F11R1_FB4 ((uint32_t)0x00000010)
#define | CAN_F11R1_FB5 ((uint32_t)0x00000020)
#define | CAN_F11R1_FB6 ((uint32_t)0x00000040)
#define | CAN_F11R1_FB7 ((uint32_t)0x00000080)
#define | CAN_F11R1_FB8 ((uint32_t)0x00000100)
#define | CAN_F11R1_FB9 ((uint32_t)0x00000200)
#define | CAN_F11R2_FB0 ((uint32_t)0x00000001)
#define | CAN_F11R2_FB1 ((uint32_t)0x00000002)
#define | CAN_F11R2_FB10 ((uint32_t)0x00000400)
#define | CAN_F11R2_FB11 ((uint32_t)0x00000800)
#define | CAN_F11R2_FB12 ((uint32_t)0x00001000)
#define | CAN_F11R2_FB13 ((uint32_t)0x00002000)
#define | CAN_F11R2_FB14 ((uint32_t)0x00004000)
#define | CAN_F11R2_FB15 ((uint32_t)0x00008000)
#define | CAN_F11R2_FB16 ((uint32_t)0x00010000)
#define | CAN_F11R2_FB17 ((uint32_t)0x00020000)
#define | CAN_F11R2_FB18 ((uint32_t)0x00040000)
#define | CAN_F11R2_FB19 ((uint32_t)0x00080000)
#define | CAN_F11R2_FB2 ((uint32_t)0x00000004)
#define | CAN_F11R2_FB20 ((uint32_t)0x00100000)
#define | CAN_F11R2_FB21 ((uint32_t)0x00200000)
#define | CAN_F11R2_FB22 ((uint32_t)0x00400000)
#define | CAN_F11R2_FB23 ((uint32_t)0x00800000)
#define | CAN_F11R2_FB24 ((uint32_t)0x01000000)
#define | CAN_F11R2_FB25 ((uint32_t)0x02000000)
#define | CAN_F11R2_FB26 ((uint32_t)0x04000000)
#define | CAN_F11R2_FB27 ((uint32_t)0x08000000)
#define | CAN_F11R2_FB28 ((uint32_t)0x10000000)
#define | CAN_F11R2_FB29 ((uint32_t)0x20000000)
#define | CAN_F11R2_FB3 ((uint32_t)0x00000008)
#define | CAN_F11R2_FB30 ((uint32_t)0x40000000)
#define | CAN_F11R2_FB31 ((uint32_t)0x80000000)
#define | CAN_F11R2_FB4 ((uint32_t)0x00000010)
#define | CAN_F11R2_FB5 ((uint32_t)0x00000020)
#define | CAN_F11R2_FB6 ((uint32_t)0x00000040)
#define | CAN_F11R2_FB7 ((uint32_t)0x00000080)
#define | CAN_F11R2_FB8 ((uint32_t)0x00000100)
#define | CAN_F11R2_FB9 ((uint32_t)0x00000200)
#define | CAN_F12R1_FB0 ((uint32_t)0x00000001)
#define | CAN_F12R1_FB1 ((uint32_t)0x00000002)
#define | CAN_F12R1_FB10 ((uint32_t)0x00000400)
#define | CAN_F12R1_FB11 ((uint32_t)0x00000800)
#define | CAN_F12R1_FB12 ((uint32_t)0x00001000)
#define | CAN_F12R1_FB13 ((uint32_t)0x00002000)
#define | CAN_F12R1_FB14 ((uint32_t)0x00004000)
#define | CAN_F12R1_FB15 ((uint32_t)0x00008000)
#define | CAN_F12R1_FB16 ((uint32_t)0x00010000)
#define | CAN_F12R1_FB17 ((uint32_t)0x00020000)
#define | CAN_F12R1_FB18 ((uint32_t)0x00040000)
#define | CAN_F12R1_FB19 ((uint32_t)0x00080000)
#define | CAN_F12R1_FB2 ((uint32_t)0x00000004)
#define | CAN_F12R1_FB20 ((uint32_t)0x00100000)
#define | CAN_F12R1_FB21 ((uint32_t)0x00200000)
#define | CAN_F12R1_FB22 ((uint32_t)0x00400000)
#define | CAN_F12R1_FB23 ((uint32_t)0x00800000)
#define | CAN_F12R1_FB24 ((uint32_t)0x01000000)
#define | CAN_F12R1_FB25 ((uint32_t)0x02000000)
#define | CAN_F12R1_FB26 ((uint32_t)0x04000000)
#define | CAN_F12R1_FB27 ((uint32_t)0x08000000)
#define | CAN_F12R1_FB28 ((uint32_t)0x10000000)
#define | CAN_F12R1_FB29 ((uint32_t)0x20000000)
#define | CAN_F12R1_FB3 ((uint32_t)0x00000008)
#define | CAN_F12R1_FB30 ((uint32_t)0x40000000)
#define | CAN_F12R1_FB31 ((uint32_t)0x80000000)
#define | CAN_F12R1_FB4 ((uint32_t)0x00000010)
#define | CAN_F12R1_FB5 ((uint32_t)0x00000020)
#define | CAN_F12R1_FB6 ((uint32_t)0x00000040)
#define | CAN_F12R1_FB7 ((uint32_t)0x00000080)
#define | CAN_F12R1_FB8 ((uint32_t)0x00000100)
#define | CAN_F12R1_FB9 ((uint32_t)0x00000200)
#define | CAN_F12R2_FB0 ((uint32_t)0x00000001)
#define | CAN_F12R2_FB1 ((uint32_t)0x00000002)
#define | CAN_F12R2_FB10 ((uint32_t)0x00000400)
#define | CAN_F12R2_FB11 ((uint32_t)0x00000800)
#define | CAN_F12R2_FB12 ((uint32_t)0x00001000)
#define | CAN_F12R2_FB13 ((uint32_t)0x00002000)
#define | CAN_F12R2_FB14 ((uint32_t)0x00004000)
#define | CAN_F12R2_FB15 ((uint32_t)0x00008000)
#define | CAN_F12R2_FB16 ((uint32_t)0x00010000)
#define | CAN_F12R2_FB17 ((uint32_t)0x00020000)
#define | CAN_F12R2_FB18 ((uint32_t)0x00040000)
#define | CAN_F12R2_FB19 ((uint32_t)0x00080000)
#define | CAN_F12R2_FB2 ((uint32_t)0x00000004)
#define | CAN_F12R2_FB20 ((uint32_t)0x00100000)
#define | CAN_F12R2_FB21 ((uint32_t)0x00200000)
#define | CAN_F12R2_FB22 ((uint32_t)0x00400000)
#define | CAN_F12R2_FB23 ((uint32_t)0x00800000)
#define | CAN_F12R2_FB24 ((uint32_t)0x01000000)
#define | CAN_F12R2_FB25 ((uint32_t)0x02000000)
#define | CAN_F12R2_FB26 ((uint32_t)0x04000000)
#define | CAN_F12R2_FB27 ((uint32_t)0x08000000)
#define | CAN_F12R2_FB28 ((uint32_t)0x10000000)
#define | CAN_F12R2_FB29 ((uint32_t)0x20000000)
#define | CAN_F12R2_FB3 ((uint32_t)0x00000008)
#define | CAN_F12R2_FB30 ((uint32_t)0x40000000)
#define | CAN_F12R2_FB31 ((uint32_t)0x80000000)
#define | CAN_F12R2_FB4 ((uint32_t)0x00000010)
#define | CAN_F12R2_FB5 ((uint32_t)0x00000020)
#define | CAN_F12R2_FB6 ((uint32_t)0x00000040)
#define | CAN_F12R2_FB7 ((uint32_t)0x00000080)
#define | CAN_F12R2_FB8 ((uint32_t)0x00000100)
#define | CAN_F12R2_FB9 ((uint32_t)0x00000200)
#define | CAN_F13R1_FB0 ((uint32_t)0x00000001)
#define | CAN_F13R1_FB1 ((uint32_t)0x00000002)
#define | CAN_F13R1_FB10 ((uint32_t)0x00000400)
#define | CAN_F13R1_FB11 ((uint32_t)0x00000800)
#define | CAN_F13R1_FB12 ((uint32_t)0x00001000)
#define | CAN_F13R1_FB13 ((uint32_t)0x00002000)
#define | CAN_F13R1_FB14 ((uint32_t)0x00004000)
#define | CAN_F13R1_FB15 ((uint32_t)0x00008000)
#define | CAN_F13R1_FB16 ((uint32_t)0x00010000)
#define | CAN_F13R1_FB17 ((uint32_t)0x00020000)
#define | CAN_F13R1_FB18 ((uint32_t)0x00040000)
#define | CAN_F13R1_FB19 ((uint32_t)0x00080000)
#define | CAN_F13R1_FB2 ((uint32_t)0x00000004)
#define | CAN_F13R1_FB20 ((uint32_t)0x00100000)
#define | CAN_F13R1_FB21 ((uint32_t)0x00200000)
#define | CAN_F13R1_FB22 ((uint32_t)0x00400000)
#define | CAN_F13R1_FB23 ((uint32_t)0x00800000)
#define | CAN_F13R1_FB24 ((uint32_t)0x01000000)
#define | CAN_F13R1_FB25 ((uint32_t)0x02000000)
#define | CAN_F13R1_FB26 ((uint32_t)0x04000000)
#define | CAN_F13R1_FB27 ((uint32_t)0x08000000)
#define | CAN_F13R1_FB28 ((uint32_t)0x10000000)
#define | CAN_F13R1_FB29 ((uint32_t)0x20000000)
#define | CAN_F13R1_FB3 ((uint32_t)0x00000008)
#define | CAN_F13R1_FB30 ((uint32_t)0x40000000)
#define | CAN_F13R1_FB31 ((uint32_t)0x80000000)
#define | CAN_F13R1_FB4 ((uint32_t)0x00000010)
#define | CAN_F13R1_FB5 ((uint32_t)0x00000020)
#define | CAN_F13R1_FB6 ((uint32_t)0x00000040)
#define | CAN_F13R1_FB7 ((uint32_t)0x00000080)
#define | CAN_F13R1_FB8 ((uint32_t)0x00000100)
#define | CAN_F13R1_FB9 ((uint32_t)0x00000200)
#define | CAN_F13R2_FB0 ((uint32_t)0x00000001)
#define | CAN_F13R2_FB1 ((uint32_t)0x00000002)
#define | CAN_F13R2_FB10 ((uint32_t)0x00000400)
#define | CAN_F13R2_FB11 ((uint32_t)0x00000800)
#define | CAN_F13R2_FB12 ((uint32_t)0x00001000)
#define | CAN_F13R2_FB13 ((uint32_t)0x00002000)
#define | CAN_F13R2_FB14 ((uint32_t)0x00004000)
#define | CAN_F13R2_FB15 ((uint32_t)0x00008000)
#define | CAN_F13R2_FB16 ((uint32_t)0x00010000)
#define | CAN_F13R2_FB17 ((uint32_t)0x00020000)
#define | CAN_F13R2_FB18 ((uint32_t)0x00040000)
#define | CAN_F13R2_FB19 ((uint32_t)0x00080000)
#define | CAN_F13R2_FB2 ((uint32_t)0x00000004)
#define | CAN_F13R2_FB20 ((uint32_t)0x00100000)
#define | CAN_F13R2_FB21 ((uint32_t)0x00200000)
#define | CAN_F13R2_FB22 ((uint32_t)0x00400000)
#define | CAN_F13R2_FB23 ((uint32_t)0x00800000)
#define | CAN_F13R2_FB24 ((uint32_t)0x01000000)
#define | CAN_F13R2_FB25 ((uint32_t)0x02000000)
#define | CAN_F13R2_FB26 ((uint32_t)0x04000000)
#define | CAN_F13R2_FB27 ((uint32_t)0x08000000)
#define | CAN_F13R2_FB28 ((uint32_t)0x10000000)
#define | CAN_F13R2_FB29 ((uint32_t)0x20000000)
#define | CAN_F13R2_FB3 ((uint32_t)0x00000008)
#define | CAN_F13R2_FB30 ((uint32_t)0x40000000)
#define | CAN_F13R2_FB31 ((uint32_t)0x80000000)
#define | CAN_F13R2_FB4 ((uint32_t)0x00000010)
#define | CAN_F13R2_FB5 ((uint32_t)0x00000020)
#define | CAN_F13R2_FB6 ((uint32_t)0x00000040)
#define | CAN_F13R2_FB7 ((uint32_t)0x00000080)
#define | CAN_F13R2_FB8 ((uint32_t)0x00000100)
#define | CAN_F13R2_FB9 ((uint32_t)0x00000200)
#define | CAN_F1R1_FB0 ((uint32_t)0x00000001)
#define | CAN_F1R1_FB1 ((uint32_t)0x00000002)
#define | CAN_F1R1_FB10 ((uint32_t)0x00000400)
#define | CAN_F1R1_FB11 ((uint32_t)0x00000800)
#define | CAN_F1R1_FB12 ((uint32_t)0x00001000)
#define | CAN_F1R1_FB13 ((uint32_t)0x00002000)
#define | CAN_F1R1_FB14 ((uint32_t)0x00004000)
#define | CAN_F1R1_FB15 ((uint32_t)0x00008000)
#define | CAN_F1R1_FB16 ((uint32_t)0x00010000)
#define | CAN_F1R1_FB17 ((uint32_t)0x00020000)
#define | CAN_F1R1_FB18 ((uint32_t)0x00040000)
#define | CAN_F1R1_FB19 ((uint32_t)0x00080000)
#define | CAN_F1R1_FB2 ((uint32_t)0x00000004)
#define | CAN_F1R1_FB20 ((uint32_t)0x00100000)
#define | CAN_F1R1_FB21 ((uint32_t)0x00200000)
#define | CAN_F1R1_FB22 ((uint32_t)0x00400000)
#define | CAN_F1R1_FB23 ((uint32_t)0x00800000)
#define | CAN_F1R1_FB24 ((uint32_t)0x01000000)
#define | CAN_F1R1_FB25 ((uint32_t)0x02000000)
#define | CAN_F1R1_FB26 ((uint32_t)0x04000000)
#define | CAN_F1R1_FB27 ((uint32_t)0x08000000)
#define | CAN_F1R1_FB28 ((uint32_t)0x10000000)
#define | CAN_F1R1_FB29 ((uint32_t)0x20000000)
#define | CAN_F1R1_FB3 ((uint32_t)0x00000008)
#define | CAN_F1R1_FB30 ((uint32_t)0x40000000)
#define | CAN_F1R1_FB31 ((uint32_t)0x80000000)
#define | CAN_F1R1_FB4 ((uint32_t)0x00000010)
#define | CAN_F1R1_FB5 ((uint32_t)0x00000020)
#define | CAN_F1R1_FB6 ((uint32_t)0x00000040)
#define | CAN_F1R1_FB7 ((uint32_t)0x00000080)
#define | CAN_F1R1_FB8 ((uint32_t)0x00000100)
#define | CAN_F1R1_FB9 ((uint32_t)0x00000200)
#define | CAN_F1R2_FB0 ((uint32_t)0x00000001)
#define | CAN_F1R2_FB1 ((uint32_t)0x00000002)
#define | CAN_F1R2_FB10 ((uint32_t)0x00000400)
#define | CAN_F1R2_FB11 ((uint32_t)0x00000800)
#define | CAN_F1R2_FB12 ((uint32_t)0x00001000)
#define | CAN_F1R2_FB13 ((uint32_t)0x00002000)
#define | CAN_F1R2_FB14 ((uint32_t)0x00004000)
#define | CAN_F1R2_FB15 ((uint32_t)0x00008000)
#define | CAN_F1R2_FB16 ((uint32_t)0x00010000)
#define | CAN_F1R2_FB17 ((uint32_t)0x00020000)
#define | CAN_F1R2_FB18 ((uint32_t)0x00040000)
#define | CAN_F1R2_FB19 ((uint32_t)0x00080000)
#define | CAN_F1R2_FB2 ((uint32_t)0x00000004)
#define | CAN_F1R2_FB20 ((uint32_t)0x00100000)
#define | CAN_F1R2_FB21 ((uint32_t)0x00200000)
#define | CAN_F1R2_FB22 ((uint32_t)0x00400000)
#define | CAN_F1R2_FB23 ((uint32_t)0x00800000)
#define | CAN_F1R2_FB24 ((uint32_t)0x01000000)
#define | CAN_F1R2_FB25 ((uint32_t)0x02000000)
#define | CAN_F1R2_FB26 ((uint32_t)0x04000000)
#define | CAN_F1R2_FB27 ((uint32_t)0x08000000)
#define | CAN_F1R2_FB28 ((uint32_t)0x10000000)
#define | CAN_F1R2_FB29 ((uint32_t)0x20000000)
#define | CAN_F1R2_FB3 ((uint32_t)0x00000008)
#define | CAN_F1R2_FB30 ((uint32_t)0x40000000)
#define | CAN_F1R2_FB31 ((uint32_t)0x80000000)
#define | CAN_F1R2_FB4 ((uint32_t)0x00000010)
#define | CAN_F1R2_FB5 ((uint32_t)0x00000020)
#define | CAN_F1R2_FB6 ((uint32_t)0x00000040)
#define | CAN_F1R2_FB7 ((uint32_t)0x00000080)
#define | CAN_F1R2_FB8 ((uint32_t)0x00000100)
#define | CAN_F1R2_FB9 ((uint32_t)0x00000200)
#define | CAN_F2R1_FB0 ((uint32_t)0x00000001)
#define | CAN_F2R1_FB1 ((uint32_t)0x00000002)
#define | CAN_F2R1_FB10 ((uint32_t)0x00000400)
#define | CAN_F2R1_FB11 ((uint32_t)0x00000800)
#define | CAN_F2R1_FB12 ((uint32_t)0x00001000)
#define | CAN_F2R1_FB13 ((uint32_t)0x00002000)
#define | CAN_F2R1_FB14 ((uint32_t)0x00004000)
#define | CAN_F2R1_FB15 ((uint32_t)0x00008000)
#define | CAN_F2R1_FB16 ((uint32_t)0x00010000)
#define | CAN_F2R1_FB17 ((uint32_t)0x00020000)
#define | CAN_F2R1_FB18 ((uint32_t)0x00040000)
#define | CAN_F2R1_FB19 ((uint32_t)0x00080000)
#define | CAN_F2R1_FB2 ((uint32_t)0x00000004)
#define | CAN_F2R1_FB20 ((uint32_t)0x00100000)
#define | CAN_F2R1_FB21 ((uint32_t)0x00200000)
#define | CAN_F2R1_FB22 ((uint32_t)0x00400000)
#define | CAN_F2R1_FB23 ((uint32_t)0x00800000)
#define | CAN_F2R1_FB24 ((uint32_t)0x01000000)
#define | CAN_F2R1_FB25 ((uint32_t)0x02000000)
#define | CAN_F2R1_FB26 ((uint32_t)0x04000000)
#define | CAN_F2R1_FB27 ((uint32_t)0x08000000)
#define | CAN_F2R1_FB28 ((uint32_t)0x10000000)
#define | CAN_F2R1_FB29 ((uint32_t)0x20000000)
#define | CAN_F2R1_FB3 ((uint32_t)0x00000008)
#define | CAN_F2R1_FB30 ((uint32_t)0x40000000)
#define | CAN_F2R1_FB31 ((uint32_t)0x80000000)
#define | CAN_F2R1_FB4 ((uint32_t)0x00000010)
#define | CAN_F2R1_FB5 ((uint32_t)0x00000020)
#define | CAN_F2R1_FB6 ((uint32_t)0x00000040)
#define | CAN_F2R1_FB7 ((uint32_t)0x00000080)
#define | CAN_F2R1_FB8 ((uint32_t)0x00000100)
#define | CAN_F2R1_FB9 ((uint32_t)0x00000200)
#define | CAN_F2R2_FB0 ((uint32_t)0x00000001)
#define | CAN_F2R2_FB1 ((uint32_t)0x00000002)
#define | CAN_F2R2_FB10 ((uint32_t)0x00000400)
#define | CAN_F2R2_FB11 ((uint32_t)0x00000800)
#define | CAN_F2R2_FB12 ((uint32_t)0x00001000)
#define | CAN_F2R2_FB13 ((uint32_t)0x00002000)
#define | CAN_F2R2_FB14 ((uint32_t)0x00004000)
#define | CAN_F2R2_FB15 ((uint32_t)0x00008000)
#define | CAN_F2R2_FB16 ((uint32_t)0x00010000)
#define | CAN_F2R2_FB17 ((uint32_t)0x00020000)
#define | CAN_F2R2_FB18 ((uint32_t)0x00040000)
#define | CAN_F2R2_FB19 ((uint32_t)0x00080000)
#define | CAN_F2R2_FB2 ((uint32_t)0x00000004)
#define | CAN_F2R2_FB20 ((uint32_t)0x00100000)
#define | CAN_F2R2_FB21 ((uint32_t)0x00200000)
#define | CAN_F2R2_FB22 ((uint32_t)0x00400000)
#define | CAN_F2R2_FB23 ((uint32_t)0x00800000)
#define | CAN_F2R2_FB24 ((uint32_t)0x01000000)
#define | CAN_F2R2_FB25 ((uint32_t)0x02000000)
#define | CAN_F2R2_FB26 ((uint32_t)0x04000000)
#define | CAN_F2R2_FB27 ((uint32_t)0x08000000)
#define | CAN_F2R2_FB28 ((uint32_t)0x10000000)
#define | CAN_F2R2_FB29 ((uint32_t)0x20000000)
#define | CAN_F2R2_FB3 ((uint32_t)0x00000008)
#define | CAN_F2R2_FB30 ((uint32_t)0x40000000)
#define | CAN_F2R2_FB31 ((uint32_t)0x80000000)
#define | CAN_F2R2_FB4 ((uint32_t)0x00000010)
#define | CAN_F2R2_FB5 ((uint32_t)0x00000020)
#define | CAN_F2R2_FB6 ((uint32_t)0x00000040)
#define | CAN_F2R2_FB7 ((uint32_t)0x00000080)
#define | CAN_F2R2_FB8 ((uint32_t)0x00000100)
#define | CAN_F2R2_FB9 ((uint32_t)0x00000200)
#define | CAN_F3R1_FB0 ((uint32_t)0x00000001)
#define | CAN_F3R1_FB1 ((uint32_t)0x00000002)
#define | CAN_F3R1_FB10 ((uint32_t)0x00000400)
#define | CAN_F3R1_FB11 ((uint32_t)0x00000800)
#define | CAN_F3R1_FB12 ((uint32_t)0x00001000)
#define | CAN_F3R1_FB13 ((uint32_t)0x00002000)
#define | CAN_F3R1_FB14 ((uint32_t)0x00004000)
#define | CAN_F3R1_FB15 ((uint32_t)0x00008000)
#define | CAN_F3R1_FB16 ((uint32_t)0x00010000)
#define | CAN_F3R1_FB17 ((uint32_t)0x00020000)
#define | CAN_F3R1_FB18 ((uint32_t)0x00040000)
#define | CAN_F3R1_FB19 ((uint32_t)0x00080000)
#define | CAN_F3R1_FB2 ((uint32_t)0x00000004)
#define | CAN_F3R1_FB20 ((uint32_t)0x00100000)
#define | CAN_F3R1_FB21 ((uint32_t)0x00200000)
#define | CAN_F3R1_FB22 ((uint32_t)0x00400000)
#define | CAN_F3R1_FB23 ((uint32_t)0x00800000)
#define | CAN_F3R1_FB24 ((uint32_t)0x01000000)
#define | CAN_F3R1_FB25 ((uint32_t)0x02000000)
#define | CAN_F3R1_FB26 ((uint32_t)0x04000000)
#define | CAN_F3R1_FB27 ((uint32_t)0x08000000)
#define | CAN_F3R1_FB28 ((uint32_t)0x10000000)
#define | CAN_F3R1_FB29 ((uint32_t)0x20000000)
#define | CAN_F3R1_FB3 ((uint32_t)0x00000008)
#define | CAN_F3R1_FB30 ((uint32_t)0x40000000)
#define | CAN_F3R1_FB31 ((uint32_t)0x80000000)
#define | CAN_F3R1_FB4 ((uint32_t)0x00000010)
#define | CAN_F3R1_FB5 ((uint32_t)0x00000020)
#define | CAN_F3R1_FB6 ((uint32_t)0x00000040)
#define | CAN_F3R1_FB7 ((uint32_t)0x00000080)
#define | CAN_F3R1_FB8 ((uint32_t)0x00000100)
#define | CAN_F3R1_FB9 ((uint32_t)0x00000200)
#define | CAN_F3R2_FB0 ((uint32_t)0x00000001)
#define | CAN_F3R2_FB1 ((uint32_t)0x00000002)
#define | CAN_F3R2_FB10 ((uint32_t)0x00000400)
#define | CAN_F3R2_FB11 ((uint32_t)0x00000800)
#define | CAN_F3R2_FB12 ((uint32_t)0x00001000)
#define | CAN_F3R2_FB13 ((uint32_t)0x00002000)
#define | CAN_F3R2_FB14 ((uint32_t)0x00004000)
#define | CAN_F3R2_FB15 ((uint32_t)0x00008000)
#define | CAN_F3R2_FB16 ((uint32_t)0x00010000)
#define | CAN_F3R2_FB17 ((uint32_t)0x00020000)
#define | CAN_F3R2_FB18 ((uint32_t)0x00040000)
#define | CAN_F3R2_FB19 ((uint32_t)0x00080000)
#define | CAN_F3R2_FB2 ((uint32_t)0x00000004)
#define | CAN_F3R2_FB20 ((uint32_t)0x00100000)
#define | CAN_F3R2_FB21 ((uint32_t)0x00200000)
#define | CAN_F3R2_FB22 ((uint32_t)0x00400000)
#define | CAN_F3R2_FB23 ((uint32_t)0x00800000)
#define | CAN_F3R2_FB24 ((uint32_t)0x01000000)
#define | CAN_F3R2_FB25 ((uint32_t)0x02000000)
#define | CAN_F3R2_FB26 ((uint32_t)0x04000000)
#define | CAN_F3R2_FB27 ((uint32_t)0x08000000)
#define | CAN_F3R2_FB28 ((uint32_t)0x10000000)
#define | CAN_F3R2_FB29 ((uint32_t)0x20000000)
#define | CAN_F3R2_FB3 ((uint32_t)0x00000008)
#define | CAN_F3R2_FB30 ((uint32_t)0x40000000)
#define | CAN_F3R2_FB31 ((uint32_t)0x80000000)
#define | CAN_F3R2_FB4 ((uint32_t)0x00000010)
#define | CAN_F3R2_FB5 ((uint32_t)0x00000020)
#define | CAN_F3R2_FB6 ((uint32_t)0x00000040)
#define | CAN_F3R2_FB7 ((uint32_t)0x00000080)
#define | CAN_F3R2_FB8 ((uint32_t)0x00000100)
#define | CAN_F3R2_FB9 ((uint32_t)0x00000200)
#define | CAN_F4R1_FB0 ((uint32_t)0x00000001)
#define | CAN_F4R1_FB1 ((uint32_t)0x00000002)
#define | CAN_F4R1_FB10 ((uint32_t)0x00000400)
#define | CAN_F4R1_FB11 ((uint32_t)0x00000800)
#define | CAN_F4R1_FB12 ((uint32_t)0x00001000)
#define | CAN_F4R1_FB13 ((uint32_t)0x00002000)
#define | CAN_F4R1_FB14 ((uint32_t)0x00004000)
#define | CAN_F4R1_FB15 ((uint32_t)0x00008000)
#define | CAN_F4R1_FB16 ((uint32_t)0x00010000)
#define | CAN_F4R1_FB17 ((uint32_t)0x00020000)
#define | CAN_F4R1_FB18 ((uint32_t)0x00040000)
#define | CAN_F4R1_FB19 ((uint32_t)0x00080000)
#define | CAN_F4R1_FB2 ((uint32_t)0x00000004)
#define | CAN_F4R1_FB20 ((uint32_t)0x00100000)
#define | CAN_F4R1_FB21 ((uint32_t)0x00200000)
#define | CAN_F4R1_FB22 ((uint32_t)0x00400000)
#define | CAN_F4R1_FB23 ((uint32_t)0x00800000)
#define | CAN_F4R1_FB24 ((uint32_t)0x01000000)
#define | CAN_F4R1_FB25 ((uint32_t)0x02000000)
#define | CAN_F4R1_FB26 ((uint32_t)0x04000000)
#define | CAN_F4R1_FB27 ((uint32_t)0x08000000)
#define | CAN_F4R1_FB28 ((uint32_t)0x10000000)
#define | CAN_F4R1_FB29 ((uint32_t)0x20000000)
#define | CAN_F4R1_FB3 ((uint32_t)0x00000008)
#define | CAN_F4R1_FB30 ((uint32_t)0x40000000)
#define | CAN_F4R1_FB31 ((uint32_t)0x80000000)
#define | CAN_F4R1_FB4 ((uint32_t)0x00000010)
#define | CAN_F4R1_FB5 ((uint32_t)0x00000020)
#define | CAN_F4R1_FB6 ((uint32_t)0x00000040)
#define | CAN_F4R1_FB7 ((uint32_t)0x00000080)
#define | CAN_F4R1_FB8 ((uint32_t)0x00000100)
#define | CAN_F4R1_FB9 ((uint32_t)0x00000200)
#define | CAN_F4R2_FB0 ((uint32_t)0x00000001)
#define | CAN_F4R2_FB1 ((uint32_t)0x00000002)
#define | CAN_F4R2_FB10 ((uint32_t)0x00000400)
#define | CAN_F4R2_FB11 ((uint32_t)0x00000800)
#define | CAN_F4R2_FB12 ((uint32_t)0x00001000)
#define | CAN_F4R2_FB13 ((uint32_t)0x00002000)
#define | CAN_F4R2_FB14 ((uint32_t)0x00004000)
#define | CAN_F4R2_FB15 ((uint32_t)0x00008000)
#define | CAN_F4R2_FB16 ((uint32_t)0x00010000)
#define | CAN_F4R2_FB17 ((uint32_t)0x00020000)
#define | CAN_F4R2_FB18 ((uint32_t)0x00040000)
#define | CAN_F4R2_FB19 ((uint32_t)0x00080000)
#define | CAN_F4R2_FB2 ((uint32_t)0x00000004)
#define | CAN_F4R2_FB20 ((uint32_t)0x00100000)
#define | CAN_F4R2_FB21 ((uint32_t)0x00200000)
#define | CAN_F4R2_FB22 ((uint32_t)0x00400000)
#define | CAN_F4R2_FB23 ((uint32_t)0x00800000)
#define | CAN_F4R2_FB24 ((uint32_t)0x01000000)
#define | CAN_F4R2_FB25 ((uint32_t)0x02000000)
#define | CAN_F4R2_FB26 ((uint32_t)0x04000000)
#define | CAN_F4R2_FB27 ((uint32_t)0x08000000)
#define | CAN_F4R2_FB28 ((uint32_t)0x10000000)
#define | CAN_F4R2_FB29 ((uint32_t)0x20000000)
#define | CAN_F4R2_FB3 ((uint32_t)0x00000008)
#define | CAN_F4R2_FB30 ((uint32_t)0x40000000)
#define | CAN_F4R2_FB31 ((uint32_t)0x80000000)
#define | CAN_F4R2_FB4 ((uint32_t)0x00000010)
#define | CAN_F4R2_FB5 ((uint32_t)0x00000020)
#define | CAN_F4R2_FB6 ((uint32_t)0x00000040)
#define | CAN_F4R2_FB7 ((uint32_t)0x00000080)
#define | CAN_F4R2_FB8 ((uint32_t)0x00000100)
#define | CAN_F4R2_FB9 ((uint32_t)0x00000200)
#define | CAN_F5R1_FB0 ((uint32_t)0x00000001)
#define | CAN_F5R1_FB1 ((uint32_t)0x00000002)
#define | CAN_F5R1_FB10 ((uint32_t)0x00000400)
#define | CAN_F5R1_FB11 ((uint32_t)0x00000800)
#define | CAN_F5R1_FB12 ((uint32_t)0x00001000)
#define | CAN_F5R1_FB13 ((uint32_t)0x00002000)
#define | CAN_F5R1_FB14 ((uint32_t)0x00004000)
#define | CAN_F5R1_FB15 ((uint32_t)0x00008000)
#define | CAN_F5R1_FB16 ((uint32_t)0x00010000)
#define | CAN_F5R1_FB17 ((uint32_t)0x00020000)
#define | CAN_F5R1_FB18 ((uint32_t)0x00040000)
#define | CAN_F5R1_FB19 ((uint32_t)0x00080000)
#define | CAN_F5R1_FB2 ((uint32_t)0x00000004)
#define | CAN_F5R1_FB20 ((uint32_t)0x00100000)
#define | CAN_F5R1_FB21 ((uint32_t)0x00200000)
#define | CAN_F5R1_FB22 ((uint32_t)0x00400000)
#define | CAN_F5R1_FB23 ((uint32_t)0x00800000)
#define | CAN_F5R1_FB24 ((uint32_t)0x01000000)
#define | CAN_F5R1_FB25 ((uint32_t)0x02000000)
#define | CAN_F5R1_FB26 ((uint32_t)0x04000000)
#define | CAN_F5R1_FB27 ((uint32_t)0x08000000)
#define | CAN_F5R1_FB28 ((uint32_t)0x10000000)
#define | CAN_F5R1_FB29 ((uint32_t)0x20000000)
#define | CAN_F5R1_FB3 ((uint32_t)0x00000008)
#define | CAN_F5R1_FB30 ((uint32_t)0x40000000)
#define | CAN_F5R1_FB31 ((uint32_t)0x80000000)
#define | CAN_F5R1_FB4 ((uint32_t)0x00000010)
#define | CAN_F5R1_FB5 ((uint32_t)0x00000020)
#define | CAN_F5R1_FB6 ((uint32_t)0x00000040)
#define | CAN_F5R1_FB7 ((uint32_t)0x00000080)
#define | CAN_F5R1_FB8 ((uint32_t)0x00000100)
#define | CAN_F5R1_FB9 ((uint32_t)0x00000200)
#define | CAN_F5R2_FB0 ((uint32_t)0x00000001)
#define | CAN_F5R2_FB1 ((uint32_t)0x00000002)
#define | CAN_F5R2_FB10 ((uint32_t)0x00000400)
#define | CAN_F5R2_FB11 ((uint32_t)0x00000800)
#define | CAN_F5R2_FB12 ((uint32_t)0x00001000)
#define | CAN_F5R2_FB13 ((uint32_t)0x00002000)
#define | CAN_F5R2_FB14 ((uint32_t)0x00004000)
#define | CAN_F5R2_FB15 ((uint32_t)0x00008000)
#define | CAN_F5R2_FB16 ((uint32_t)0x00010000)
#define | CAN_F5R2_FB17 ((uint32_t)0x00020000)
#define | CAN_F5R2_FB18 ((uint32_t)0x00040000)
#define | CAN_F5R2_FB19 ((uint32_t)0x00080000)
#define | CAN_F5R2_FB2 ((uint32_t)0x00000004)
#define | CAN_F5R2_FB20 ((uint32_t)0x00100000)
#define | CAN_F5R2_FB21 ((uint32_t)0x00200000)
#define | CAN_F5R2_FB22 ((uint32_t)0x00400000)
#define | CAN_F5R2_FB23 ((uint32_t)0x00800000)
#define | CAN_F5R2_FB24 ((uint32_t)0x01000000)
#define | CAN_F5R2_FB25 ((uint32_t)0x02000000)
#define | CAN_F5R2_FB26 ((uint32_t)0x04000000)
#define | CAN_F5R2_FB27 ((uint32_t)0x08000000)
#define | CAN_F5R2_FB28 ((uint32_t)0x10000000)
#define | CAN_F5R2_FB29 ((uint32_t)0x20000000)
#define | CAN_F5R2_FB3 ((uint32_t)0x00000008)
#define | CAN_F5R2_FB30 ((uint32_t)0x40000000)
#define | CAN_F5R2_FB31 ((uint32_t)0x80000000)
#define | CAN_F5R2_FB4 ((uint32_t)0x00000010)
#define | CAN_F5R2_FB5 ((uint32_t)0x00000020)
#define | CAN_F5R2_FB6 ((uint32_t)0x00000040)
#define | CAN_F5R2_FB7 ((uint32_t)0x00000080)
#define | CAN_F5R2_FB8 ((uint32_t)0x00000100)
#define | CAN_F5R2_FB9 ((uint32_t)0x00000200)
#define | CAN_F6R1_FB0 ((uint32_t)0x00000001)
#define | CAN_F6R1_FB1 ((uint32_t)0x00000002)
#define | CAN_F6R1_FB10 ((uint32_t)0x00000400)
#define | CAN_F6R1_FB11 ((uint32_t)0x00000800)
#define | CAN_F6R1_FB12 ((uint32_t)0x00001000)
#define | CAN_F6R1_FB13 ((uint32_t)0x00002000)
#define | CAN_F6R1_FB14 ((uint32_t)0x00004000)
#define | CAN_F6R1_FB15 ((uint32_t)0x00008000)
#define | CAN_F6R1_FB16 ((uint32_t)0x00010000)
#define | CAN_F6R1_FB17 ((uint32_t)0x00020000)
#define | CAN_F6R1_FB18 ((uint32_t)0x00040000)
#define | CAN_F6R1_FB19 ((uint32_t)0x00080000)
#define | CAN_F6R1_FB2 ((uint32_t)0x00000004)
#define | CAN_F6R1_FB20 ((uint32_t)0x00100000)
#define | CAN_F6R1_FB21 ((uint32_t)0x00200000)
#define | CAN_F6R1_FB22 ((uint32_t)0x00400000)
#define | CAN_F6R1_FB23 ((uint32_t)0x00800000)
#define | CAN_F6R1_FB24 ((uint32_t)0x01000000)
#define | CAN_F6R1_FB25 ((uint32_t)0x02000000)
#define | CAN_F6R1_FB26 ((uint32_t)0x04000000)
#define | CAN_F6R1_FB27 ((uint32_t)0x08000000)
#define | CAN_F6R1_FB28 ((uint32_t)0x10000000)
#define | CAN_F6R1_FB29 ((uint32_t)0x20000000)
#define | CAN_F6R1_FB3 ((uint32_t)0x00000008)
#define | CAN_F6R1_FB30 ((uint32_t)0x40000000)
#define | CAN_F6R1_FB31 ((uint32_t)0x80000000)
#define | CAN_F6R1_FB4 ((uint32_t)0x00000010)
#define | CAN_F6R1_FB5 ((uint32_t)0x00000020)
#define | CAN_F6R1_FB6 ((uint32_t)0x00000040)
#define | CAN_F6R1_FB7 ((uint32_t)0x00000080)
#define | CAN_F6R1_FB8 ((uint32_t)0x00000100)
#define | CAN_F6R1_FB9 ((uint32_t)0x00000200)
#define | CAN_F6R2_FB0 ((uint32_t)0x00000001)
#define | CAN_F6R2_FB1 ((uint32_t)0x00000002)
#define | CAN_F6R2_FB10 ((uint32_t)0x00000400)
#define | CAN_F6R2_FB11 ((uint32_t)0x00000800)
#define | CAN_F6R2_FB12 ((uint32_t)0x00001000)
#define | CAN_F6R2_FB13 ((uint32_t)0x00002000)
#define | CAN_F6R2_FB14 ((uint32_t)0x00004000)
#define | CAN_F6R2_FB15 ((uint32_t)0x00008000)
#define | CAN_F6R2_FB16 ((uint32_t)0x00010000)
#define | CAN_F6R2_FB17 ((uint32_t)0x00020000)
#define | CAN_F6R2_FB18 ((uint32_t)0x00040000)
#define | CAN_F6R2_FB19 ((uint32_t)0x00080000)
#define | CAN_F6R2_FB2 ((uint32_t)0x00000004)
#define | CAN_F6R2_FB20 ((uint32_t)0x00100000)
#define | CAN_F6R2_FB21 ((uint32_t)0x00200000)
#define | CAN_F6R2_FB22 ((uint32_t)0x00400000)
#define | CAN_F6R2_FB23 ((uint32_t)0x00800000)
#define | CAN_F6R2_FB24 ((uint32_t)0x01000000)
#define | CAN_F6R2_FB25 ((uint32_t)0x02000000)
#define | CAN_F6R2_FB26 ((uint32_t)0x04000000)
#define | CAN_F6R2_FB27 ((uint32_t)0x08000000)
#define | CAN_F6R2_FB28 ((uint32_t)0x10000000)
#define | CAN_F6R2_FB29 ((uint32_t)0x20000000)
#define | CAN_F6R2_FB3 ((uint32_t)0x00000008)
#define | CAN_F6R2_FB30 ((uint32_t)0x40000000)
#define | CAN_F6R2_FB31 ((uint32_t)0x80000000)
#define | CAN_F6R2_FB4 ((uint32_t)0x00000010)
#define | CAN_F6R2_FB5 ((uint32_t)0x00000020)
#define | CAN_F6R2_FB6 ((uint32_t)0x00000040)
#define | CAN_F6R2_FB7 ((uint32_t)0x00000080)
#define | CAN_F6R2_FB8 ((uint32_t)0x00000100)
#define | CAN_F6R2_FB9 ((uint32_t)0x00000200)
#define | CAN_F7R1_FB0 ((uint32_t)0x00000001)
#define | CAN_F7R1_FB1 ((uint32_t)0x00000002)
#define | CAN_F7R1_FB10 ((uint32_t)0x00000400)
#define | CAN_F7R1_FB11 ((uint32_t)0x00000800)
#define | CAN_F7R1_FB12 ((uint32_t)0x00001000)
#define | CAN_F7R1_FB13 ((uint32_t)0x00002000)
#define | CAN_F7R1_FB14 ((uint32_t)0x00004000)
#define | CAN_F7R1_FB15 ((uint32_t)0x00008000)
#define | CAN_F7R1_FB16 ((uint32_t)0x00010000)
#define | CAN_F7R1_FB17 ((uint32_t)0x00020000)
#define | CAN_F7R1_FB18 ((uint32_t)0x00040000)
#define | CAN_F7R1_FB19 ((uint32_t)0x00080000)
#define | CAN_F7R1_FB2 ((uint32_t)0x00000004)
#define | CAN_F7R1_FB20 ((uint32_t)0x00100000)
#define | CAN_F7R1_FB21 ((uint32_t)0x00200000)
#define | CAN_F7R1_FB22 ((uint32_t)0x00400000)
#define | CAN_F7R1_FB23 ((uint32_t)0x00800000)
#define | CAN_F7R1_FB24 ((uint32_t)0x01000000)
#define | CAN_F7R1_FB25 ((uint32_t)0x02000000)
#define | CAN_F7R1_FB26 ((uint32_t)0x04000000)
#define | CAN_F7R1_FB27 ((uint32_t)0x08000000)
#define | CAN_F7R1_FB28 ((uint32_t)0x10000000)
#define | CAN_F7R1_FB29 ((uint32_t)0x20000000)
#define | CAN_F7R1_FB3 ((uint32_t)0x00000008)
#define | CAN_F7R1_FB30 ((uint32_t)0x40000000)
#define | CAN_F7R1_FB31 ((uint32_t)0x80000000)
#define | CAN_F7R1_FB4 ((uint32_t)0x00000010)
#define | CAN_F7R1_FB5 ((uint32_t)0x00000020)
#define | CAN_F7R1_FB6 ((uint32_t)0x00000040)
#define | CAN_F7R1_FB7 ((uint32_t)0x00000080)
#define | CAN_F7R1_FB8 ((uint32_t)0x00000100)
#define | CAN_F7R1_FB9 ((uint32_t)0x00000200)
#define | CAN_F7R2_FB0 ((uint32_t)0x00000001)
#define | CAN_F7R2_FB1 ((uint32_t)0x00000002)
#define | CAN_F7R2_FB10 ((uint32_t)0x00000400)
#define | CAN_F7R2_FB11 ((uint32_t)0x00000800)
#define | CAN_F7R2_FB12 ((uint32_t)0x00001000)
#define | CAN_F7R2_FB13 ((uint32_t)0x00002000)
#define | CAN_F7R2_FB14 ((uint32_t)0x00004000)
#define | CAN_F7R2_FB15 ((uint32_t)0x00008000)
#define | CAN_F7R2_FB16 ((uint32_t)0x00010000)
#define | CAN_F7R2_FB17 ((uint32_t)0x00020000)
#define | CAN_F7R2_FB18 ((uint32_t)0x00040000)
#define | CAN_F7R2_FB19 ((uint32_t)0x00080000)
#define | CAN_F7R2_FB2 ((uint32_t)0x00000004)
#define | CAN_F7R2_FB20 ((uint32_t)0x00100000)
#define | CAN_F7R2_FB21 ((uint32_t)0x00200000)
#define | CAN_F7R2_FB22 ((uint32_t)0x00400000)
#define | CAN_F7R2_FB23 ((uint32_t)0x00800000)
#define | CAN_F7R2_FB24 ((uint32_t)0x01000000)
#define | CAN_F7R2_FB25 ((uint32_t)0x02000000)
#define | CAN_F7R2_FB26 ((uint32_t)0x04000000)
#define | CAN_F7R2_FB27 ((uint32_t)0x08000000)
#define | CAN_F7R2_FB28 ((uint32_t)0x10000000)
#define | CAN_F7R2_FB29 ((uint32_t)0x20000000)
#define | CAN_F7R2_FB3 ((uint32_t)0x00000008)
#define | CAN_F7R2_FB30 ((uint32_t)0x40000000)
#define | CAN_F7R2_FB31 ((uint32_t)0x80000000)
#define | CAN_F7R2_FB4 ((uint32_t)0x00000010)
#define | CAN_F7R2_FB5 ((uint32_t)0x00000020)
#define | CAN_F7R2_FB6 ((uint32_t)0x00000040)
#define | CAN_F7R2_FB7 ((uint32_t)0x00000080)
#define | CAN_F7R2_FB8 ((uint32_t)0x00000100)
#define | CAN_F7R2_FB9 ((uint32_t)0x00000200)
#define | CAN_F8R1_FB0 ((uint32_t)0x00000001)
#define | CAN_F8R1_FB1 ((uint32_t)0x00000002)
#define | CAN_F8R1_FB10 ((uint32_t)0x00000400)
#define | CAN_F8R1_FB11 ((uint32_t)0x00000800)
#define | CAN_F8R1_FB12 ((uint32_t)0x00001000)
#define | CAN_F8R1_FB13 ((uint32_t)0x00002000)
#define | CAN_F8R1_FB14 ((uint32_t)0x00004000)
#define | CAN_F8R1_FB15 ((uint32_t)0x00008000)
#define | CAN_F8R1_FB16 ((uint32_t)0x00010000)
#define | CAN_F8R1_FB17 ((uint32_t)0x00020000)
#define | CAN_F8R1_FB18 ((uint32_t)0x00040000)
#define | CAN_F8R1_FB19 ((uint32_t)0x00080000)
#define | CAN_F8R1_FB2 ((uint32_t)0x00000004)
#define | CAN_F8R1_FB20 ((uint32_t)0x00100000)
#define | CAN_F8R1_FB21 ((uint32_t)0x00200000)
#define | CAN_F8R1_FB22 ((uint32_t)0x00400000)
#define | CAN_F8R1_FB23 ((uint32_t)0x00800000)
#define | CAN_F8R1_FB24 ((uint32_t)0x01000000)
#define | CAN_F8R1_FB25 ((uint32_t)0x02000000)
#define | CAN_F8R1_FB26 ((uint32_t)0x04000000)
#define | CAN_F8R1_FB27 ((uint32_t)0x08000000)
#define | CAN_F8R1_FB28 ((uint32_t)0x10000000)
#define | CAN_F8R1_FB29 ((uint32_t)0x20000000)
#define | CAN_F8R1_FB3 ((uint32_t)0x00000008)
#define | CAN_F8R1_FB30 ((uint32_t)0x40000000)
#define | CAN_F8R1_FB31 ((uint32_t)0x80000000)
#define | CAN_F8R1_FB4 ((uint32_t)0x00000010)
#define | CAN_F8R1_FB5 ((uint32_t)0x00000020)
#define | CAN_F8R1_FB6 ((uint32_t)0x00000040)
#define | CAN_F8R1_FB7 ((uint32_t)0x00000080)
#define | CAN_F8R1_FB8 ((uint32_t)0x00000100)
#define | CAN_F8R1_FB9 ((uint32_t)0x00000200)
#define | CAN_F8R2_FB0 ((uint32_t)0x00000001)
#define | CAN_F8R2_FB1 ((uint32_t)0x00000002)
#define | CAN_F8R2_FB10 ((uint32_t)0x00000400)
#define | CAN_F8R2_FB11 ((uint32_t)0x00000800)
#define | CAN_F8R2_FB12 ((uint32_t)0x00001000)
#define | CAN_F8R2_FB13 ((uint32_t)0x00002000)
#define | CAN_F8R2_FB14 ((uint32_t)0x00004000)
#define | CAN_F8R2_FB15 ((uint32_t)0x00008000)
#define | CAN_F8R2_FB16 ((uint32_t)0x00010000)
#define | CAN_F8R2_FB17 ((uint32_t)0x00020000)
#define | CAN_F8R2_FB18 ((uint32_t)0x00040000)
#define | CAN_F8R2_FB19 ((uint32_t)0x00080000)
#define | CAN_F8R2_FB2 ((uint32_t)0x00000004)
#define | CAN_F8R2_FB20 ((uint32_t)0x00100000)
#define | CAN_F8R2_FB21 ((uint32_t)0x00200000)
#define | CAN_F8R2_FB22 ((uint32_t)0x00400000)
#define | CAN_F8R2_FB23 ((uint32_t)0x00800000)
#define | CAN_F8R2_FB24 ((uint32_t)0x01000000)
#define | CAN_F8R2_FB25 ((uint32_t)0x02000000)
#define | CAN_F8R2_FB26 ((uint32_t)0x04000000)
#define | CAN_F8R2_FB27 ((uint32_t)0x08000000)
#define | CAN_F8R2_FB28 ((uint32_t)0x10000000)
#define | CAN_F8R2_FB29 ((uint32_t)0x20000000)
#define | CAN_F8R2_FB3 ((uint32_t)0x00000008)
#define | CAN_F8R2_FB30 ((uint32_t)0x40000000)
#define | CAN_F8R2_FB31 ((uint32_t)0x80000000)
#define | CAN_F8R2_FB4 ((uint32_t)0x00000010)
#define | CAN_F8R2_FB5 ((uint32_t)0x00000020)
#define | CAN_F8R2_FB6 ((uint32_t)0x00000040)
#define | CAN_F8R2_FB7 ((uint32_t)0x00000080)
#define | CAN_F8R2_FB8 ((uint32_t)0x00000100)
#define | CAN_F8R2_FB9 ((uint32_t)0x00000200)
#define | CAN_F9R1_FB0 ((uint32_t)0x00000001)
#define | CAN_F9R1_FB1 ((uint32_t)0x00000002)
#define | CAN_F9R1_FB10 ((uint32_t)0x00000400)
#define | CAN_F9R1_FB11 ((uint32_t)0x00000800)
#define | CAN_F9R1_FB12 ((uint32_t)0x00001000)
#define | CAN_F9R1_FB13 ((uint32_t)0x00002000)
#define | CAN_F9R1_FB14 ((uint32_t)0x00004000)
#define | CAN_F9R1_FB15 ((uint32_t)0x00008000)
#define | CAN_F9R1_FB16 ((uint32_t)0x00010000)
#define | CAN_F9R1_FB17 ((uint32_t)0x00020000)
#define | CAN_F9R1_FB18 ((uint32_t)0x00040000)
#define | CAN_F9R1_FB19 ((uint32_t)0x00080000)
#define | CAN_F9R1_FB2 ((uint32_t)0x00000004)
#define | CAN_F9R1_FB20 ((uint32_t)0x00100000)
#define | CAN_F9R1_FB21 ((uint32_t)0x00200000)
#define | CAN_F9R1_FB22 ((uint32_t)0x00400000)
#define | CAN_F9R1_FB23 ((uint32_t)0x00800000)
#define | CAN_F9R1_FB24 ((uint32_t)0x01000000)
#define | CAN_F9R1_FB25 ((uint32_t)0x02000000)
#define | CAN_F9R1_FB26 ((uint32_t)0x04000000)
#define | CAN_F9R1_FB27 ((uint32_t)0x08000000)
#define | CAN_F9R1_FB28 ((uint32_t)0x10000000)
#define | CAN_F9R1_FB29 ((uint32_t)0x20000000)
#define | CAN_F9R1_FB3 ((uint32_t)0x00000008)
#define | CAN_F9R1_FB30 ((uint32_t)0x40000000)
#define | CAN_F9R1_FB31 ((uint32_t)0x80000000)
#define | CAN_F9R1_FB4 ((uint32_t)0x00000010)
#define | CAN_F9R1_FB5 ((uint32_t)0x00000020)
#define | CAN_F9R1_FB6 ((uint32_t)0x00000040)
#define | CAN_F9R1_FB7 ((uint32_t)0x00000080)
#define | CAN_F9R1_FB8 ((uint32_t)0x00000100)
#define | CAN_F9R1_FB9 ((uint32_t)0x00000200)
#define | CAN_F9R2_FB0 ((uint32_t)0x00000001)
#define | CAN_F9R2_FB1 ((uint32_t)0x00000002)
#define | CAN_F9R2_FB10 ((uint32_t)0x00000400)
#define | CAN_F9R2_FB11 ((uint32_t)0x00000800)
#define | CAN_F9R2_FB12 ((uint32_t)0x00001000)
#define | CAN_F9R2_FB13 ((uint32_t)0x00002000)
#define | CAN_F9R2_FB14 ((uint32_t)0x00004000)
#define | CAN_F9R2_FB15 ((uint32_t)0x00008000)
#define | CAN_F9R2_FB16 ((uint32_t)0x00010000)
#define | CAN_F9R2_FB17 ((uint32_t)0x00020000)
#define | CAN_F9R2_FB18 ((uint32_t)0x00040000)
#define | CAN_F9R2_FB19 ((uint32_t)0x00080000)
#define | CAN_F9R2_FB2 ((uint32_t)0x00000004)
#define | CAN_F9R2_FB20 ((uint32_t)0x00100000)
#define | CAN_F9R2_FB21 ((uint32_t)0x00200000)
#define | CAN_F9R2_FB22 ((uint32_t)0x00400000)
#define | CAN_F9R2_FB23 ((uint32_t)0x00800000)
#define | CAN_F9R2_FB24 ((uint32_t)0x01000000)
#define | CAN_F9R2_FB25 ((uint32_t)0x02000000)
#define | CAN_F9R2_FB26 ((uint32_t)0x04000000)
#define | CAN_F9R2_FB27 ((uint32_t)0x08000000)
#define | CAN_F9R2_FB28 ((uint32_t)0x10000000)
#define | CAN_F9R2_FB29 ((uint32_t)0x20000000)
#define | CAN_F9R2_FB3 ((uint32_t)0x00000008)
#define | CAN_F9R2_FB30 ((uint32_t)0x40000000)
#define | CAN_F9R2_FB31 ((uint32_t)0x80000000)
#define | CAN_F9R2_FB4 ((uint32_t)0x00000010)
#define | CAN_F9R2_FB5 ((uint32_t)0x00000020)
#define | CAN_F9R2_FB6 ((uint32_t)0x00000040)
#define | CAN_F9R2_FB7 ((uint32_t)0x00000080)
#define | CAN_F9R2_FB8 ((uint32_t)0x00000100)
#define | CAN_F9R2_FB9 ((uint32_t)0x00000200)
#define | CAN_FA1R_FACT ((uint16_t)0x3FFF)
#define | CAN_FA1R_FACT0 ((uint16_t)0x0001)
#define | CAN_FA1R_FACT1 ((uint16_t)0x0002)
#define | CAN_FA1R_FACT10 ((uint16_t)0x0400)
#define | CAN_FA1R_FACT11 ((uint16_t)0x0800)
#define | CAN_FA1R_FACT12 ((uint16_t)0x1000)
#define | CAN_FA1R_FACT13 ((uint16_t)0x2000)
#define | CAN_FA1R_FACT2 ((uint16_t)0x0004)
#define | CAN_FA1R_FACT3 ((uint16_t)0x0008)
#define | CAN_FA1R_FACT4 ((uint16_t)0x0010)
#define | CAN_FA1R_FACT5 ((uint16_t)0x0020)
#define | CAN_FA1R_FACT6 ((uint16_t)0x0040)
#define | CAN_FA1R_FACT7 ((uint16_t)0x0080)
#define | CAN_FA1R_FACT8 ((uint16_t)0x0100)
#define | CAN_FA1R_FACT9 ((uint16_t)0x0200)
#define | CAN_FFA1R_FFA ((uint16_t)0x3FFF)
#define | CAN_FFA1R_FFA0 ((uint16_t)0x0001)
#define | CAN_FFA1R_FFA1 ((uint16_t)0x0002)
#define | CAN_FFA1R_FFA10 ((uint16_t)0x0400)
#define | CAN_FFA1R_FFA11 ((uint16_t)0x0800)
#define | CAN_FFA1R_FFA12 ((uint16_t)0x1000)
#define | CAN_FFA1R_FFA13 ((uint16_t)0x2000)
#define | CAN_FFA1R_FFA2 ((uint16_t)0x0004)
#define | CAN_FFA1R_FFA3 ((uint16_t)0x0008)
#define | CAN_FFA1R_FFA4 ((uint16_t)0x0010)
#define | CAN_FFA1R_FFA5 ((uint16_t)0x0020)
#define | CAN_FFA1R_FFA6 ((uint16_t)0x0040)
#define | CAN_FFA1R_FFA7 ((uint16_t)0x0080)
#define | CAN_FFA1R_FFA8 ((uint16_t)0x0100)
#define | CAN_FFA1R_FFA9 ((uint16_t)0x0200)
#define | CAN_FM1R_FBM ((uint16_t)0x3FFF)
#define | CAN_FM1R_FBM0 ((uint16_t)0x0001)
#define | CAN_FM1R_FBM1 ((uint16_t)0x0002)
#define | CAN_FM1R_FBM10 ((uint16_t)0x0400)
#define | CAN_FM1R_FBM11 ((uint16_t)0x0800)
#define | CAN_FM1R_FBM12 ((uint16_t)0x1000)
#define | CAN_FM1R_FBM13 ((uint16_t)0x2000)
#define | CAN_FM1R_FBM2 ((uint16_t)0x0004)
#define | CAN_FM1R_FBM3 ((uint16_t)0x0008)
#define | CAN_FM1R_FBM4 ((uint16_t)0x0010)
#define | CAN_FM1R_FBM5 ((uint16_t)0x0020)
#define | CAN_FM1R_FBM6 ((uint16_t)0x0040)
#define | CAN_FM1R_FBM7 ((uint16_t)0x0080)
#define | CAN_FM1R_FBM8 ((uint16_t)0x0100)
#define | CAN_FM1R_FBM9 ((uint16_t)0x0200)
#define | CAN_FMR_FINIT ((uint8_t)0x01)
#define | CAN_FS1R_FSC ((uint16_t)0x3FFF)
#define | CAN_FS1R_FSC0 ((uint16_t)0x0001)
#define | CAN_FS1R_FSC1 ((uint16_t)0x0002)
#define | CAN_FS1R_FSC10 ((uint16_t)0x0400)
#define | CAN_FS1R_FSC11 ((uint16_t)0x0800)
#define | CAN_FS1R_FSC12 ((uint16_t)0x1000)
#define | CAN_FS1R_FSC13 ((uint16_t)0x2000)
#define | CAN_FS1R_FSC2 ((uint16_t)0x0004)
#define | CAN_FS1R_FSC3 ((uint16_t)0x0008)
#define | CAN_FS1R_FSC4 ((uint16_t)0x0010)
#define | CAN_FS1R_FSC5 ((uint16_t)0x0020)
#define | CAN_FS1R_FSC6 ((uint16_t)0x0040)
#define | CAN_FS1R_FSC7 ((uint16_t)0x0080)
#define | CAN_FS1R_FSC8 ((uint16_t)0x0100)
#define | CAN_FS1R_FSC9 ((uint16_t)0x0200)
#define | CAN_IER_BOFIE ((uint32_t)0x00000400)
#define | CAN_IER_EPVIE ((uint32_t)0x00000200)
#define | CAN_IER_ERRIE ((uint32_t)0x00008000)
#define | CAN_IER_EWGIE ((uint32_t)0x00000100)
#define | CAN_IER_FFIE0 ((uint32_t)0x00000004)
#define | CAN_IER_FFIE1 ((uint32_t)0x00000020)
#define | CAN_IER_FMPIE0 ((uint32_t)0x00000002)
#define | CAN_IER_FMPIE1 ((uint32_t)0x00000010)
#define | CAN_IER_FOVIE0 ((uint32_t)0x00000008)
#define | CAN_IER_FOVIE1 ((uint32_t)0x00000040)
#define | CAN_IER_LECIE ((uint32_t)0x00000800)
#define | CAN_IER_SLKIE ((uint32_t)0x00020000)
#define | CAN_IER_TMEIE ((uint32_t)0x00000001)
#define | CAN_IER_WKUIE ((uint32_t)0x00010000)
#define | CAN_MCR_ABOM ((uint16_t)0x0040)
#define | CAN_MCR_AWUM ((uint16_t)0x0020)
#define | CAN_MCR_INRQ ((uint16_t)0x0001)
#define | CAN_MCR_NART ((uint16_t)0x0010)
#define | CAN_MCR_RESET ((uint16_t)0x8000)
#define | CAN_MCR_RFLM ((uint16_t)0x0008)
#define | CAN_MCR_SLEEP ((uint16_t)0x0002)
#define | CAN_MCR_TTCM ((uint16_t)0x0080)
#define | CAN_MCR_TXFP ((uint16_t)0x0004)
#define | CAN_MSR_ERRI ((uint16_t)0x0004)
#define | CAN_MSR_INAK ((uint16_t)0x0001)
#define | CAN_MSR_RX ((uint16_t)0x0800)
#define | CAN_MSR_RXM ((uint16_t)0x0200)
#define | CAN_MSR_SAMP ((uint16_t)0x0400)
#define | CAN_MSR_SLAK ((uint16_t)0x0002)
#define | CAN_MSR_SLAKI ((uint16_t)0x0010)
#define | CAN_MSR_TXM ((uint16_t)0x0100)
#define | CAN_MSR_WKUI ((uint16_t)0x0008)
#define | CAN_RDH0R_DATA4 ((uint32_t)0x000000FF)
#define | CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00)
#define | CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000)
#define | CAN_RDH0R_DATA7 ((uint32_t)0xFF000000)
#define | CAN_RDH1R_DATA4 ((uint32_t)0x000000FF)
#define | CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00)
#define | CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000)
#define | CAN_RDH1R_DATA7 ((uint32_t)0xFF000000)
#define | CAN_RDL0R_DATA0 ((uint32_t)0x000000FF)
#define | CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00)
#define | CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000)
#define | CAN_RDL0R_DATA3 ((uint32_t)0xFF000000)
#define | CAN_RDL1R_DATA0 ((uint32_t)0x000000FF)
#define | CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00)
#define | CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000)
#define | CAN_RDL1R_DATA3 ((uint32_t)0xFF000000)
#define | CAN_RDT0R_DLC ((uint32_t)0x0000000F)
#define | CAN_RDT0R_FMI ((uint32_t)0x0000FF00)
#define | CAN_RDT0R_TIME ((uint32_t)0xFFFF0000)
#define | CAN_RDT1R_DLC ((uint32_t)0x0000000F)
#define | CAN_RDT1R_FMI ((uint32_t)0x0000FF00)
#define | CAN_RDT1R_TIME ((uint32_t)0xFFFF0000)
#define | CAN_RF0R_FMP0 ((uint8_t)0x03)
#define | CAN_RF0R_FOVR0 ((uint8_t)0x10)
#define | CAN_RF0R_FULL0 ((uint8_t)0x08)
#define | CAN_RF0R_RFOM0 ((uint8_t)0x20)
#define | CAN_RF1R_FMP1 ((uint8_t)0x03)
#define | CAN_RF1R_FOVR1 ((uint8_t)0x10)
#define | CAN_RF1R_FULL1 ((uint8_t)0x08)
#define | CAN_RF1R_RFOM1 ((uint8_t)0x20)
#define | CAN_RI0R_EXID ((uint32_t)0x001FFFF8)
#define | CAN_RI0R_IDE ((uint32_t)0x00000004)
#define | CAN_RI0R_RTR ((uint32_t)0x00000002)
#define | CAN_RI0R_STID ((uint32_t)0xFFE00000)
#define | CAN_RI1R_EXID ((uint32_t)0x001FFFF8)
#define | CAN_RI1R_IDE ((uint32_t)0x00000004)
#define | CAN_RI1R_RTR ((uint32_t)0x00000002)
#define | CAN_RI1R_STID ((uint32_t)0xFFE00000)
#define | CAN_TDH0R_DATA4 ((uint32_t)0x000000FF)
#define | CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00)
#define | CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000)
#define | CAN_TDH0R_DATA7 ((uint32_t)0xFF000000)
#define | CAN_TDH1R_DATA4 ((uint32_t)0x000000FF)
#define | CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00)
#define | CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000)
#define | CAN_TDH1R_DATA7 ((uint32_t)0xFF000000)
#define | CAN_TDH2R_DATA4 ((uint32_t)0x000000FF)
#define | CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00)
#define | CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000)
#define | CAN_TDH2R_DATA7 ((uint32_t)0xFF000000)
#define | CAN_TDL0R_DATA0 ((uint32_t)0x000000FF)
#define | CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00)
#define | CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000)
#define | CAN_TDL0R_DATA3 ((uint32_t)0xFF000000)
#define | CAN_TDL1R_DATA0 ((uint32_t)0x000000FF)
#define | CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00)
#define | CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000)
#define | CAN_TDL1R_DATA3 ((uint32_t)0xFF000000)
#define | CAN_TDL2R_DATA0 ((uint32_t)0x000000FF)
#define | CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00)
#define | CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000)
#define | CAN_TDL2R_DATA3 ((uint32_t)0xFF000000)
#define | CAN_TDT0R_DLC ((uint32_t)0x0000000F)
#define | CAN_TDT0R_TGT ((uint32_t)0x00000100)
#define | CAN_TDT0R_TIME ((uint32_t)0xFFFF0000)
#define | CAN_TDT1R_DLC ((uint32_t)0x0000000F)
#define | CAN_TDT1R_TGT ((uint32_t)0x00000100)
#define | CAN_TDT1R_TIME ((uint32_t)0xFFFF0000)
#define | CAN_TDT2R_DLC ((uint32_t)0x0000000F)
#define | CAN_TDT2R_TGT ((uint32_t)0x00000100)
#define | CAN_TDT2R_TIME ((uint32_t)0xFFFF0000)
#define | CAN_TI0R_EXID ((uint32_t)0x001FFFF8)
#define | CAN_TI0R_IDE ((uint32_t)0x00000004)
#define | CAN_TI0R_RTR ((uint32_t)0x00000002)
#define | CAN_TI0R_STID ((uint32_t)0xFFE00000)
#define | CAN_TI0R_TXRQ ((uint32_t)0x00000001)
#define | CAN_TI1R_EXID ((uint32_t)0x001FFFF8)
#define | CAN_TI1R_IDE ((uint32_t)0x00000004)
#define | CAN_TI1R_RTR ((uint32_t)0x00000002)
#define | CAN_TI1R_STID ((uint32_t)0xFFE00000)
#define | CAN_TI1R_TXRQ ((uint32_t)0x00000001)
#define | CAN_TI2R_EXID ((uint32_t)0x001FFFF8)
#define | CAN_TI2R_IDE ((uint32_t)0x00000004)
#define | CAN_TI2R_RTR ((uint32_t)0x00000002)
#define | CAN_TI2R_STID ((uint32_t)0xFFE00000)
#define | CAN_TI2R_TXRQ ((uint32_t)0x00000001)
#define | CAN_TSR_ABRQ0 ((uint32_t)0x00000080)
#define | CAN_TSR_ABRQ1 ((uint32_t)0x00008000)
#define | CAN_TSR_ABRQ2 ((uint32_t)0x00800000)
#define | CAN_TSR_ALST0 ((uint32_t)0x00000004)
#define | CAN_TSR_ALST1 ((uint32_t)0x00000400)
#define | CAN_TSR_ALST2 ((uint32_t)0x00040000)
#define | CAN_TSR_CODE ((uint32_t)0x03000000)
#define | CAN_TSR_LOW ((uint32_t)0xE0000000)
#define | CAN_TSR_LOW0 ((uint32_t)0x20000000)
#define | CAN_TSR_LOW1 ((uint32_t)0x40000000)
#define | CAN_TSR_LOW2 ((uint32_t)0x80000000)
#define | CAN_TSR_RQCP0 ((uint32_t)0x00000001)
#define | CAN_TSR_RQCP1 ((uint32_t)0x00000100)
#define | CAN_TSR_RQCP2 ((uint32_t)0x00010000)
#define | CAN_TSR_TERR0 ((uint32_t)0x00000008)
#define | CAN_TSR_TERR1 ((uint32_t)0x00000800)
#define | CAN_TSR_TERR2 ((uint32_t)0x00080000)
#define | CAN_TSR_TME ((uint32_t)0x1C000000)
#define | CAN_TSR_TME0 ((uint32_t)0x04000000)
#define | CAN_TSR_TME1 ((uint32_t)0x08000000)
#define | CAN_TSR_TME2 ((uint32_t)0x10000000)
#define | CAN_TSR_TXOK0 ((uint32_t)0x00000002)
#define | CAN_TSR_TXOK1 ((uint32_t)0x00000200)
#define | CAN_TSR_TXOK2 ((uint32_t)0x00020000)
#define | CEC ((CEC_TypeDef *) CEC_BASE)
#define | CEC_BASE (APB1PERIPH_BASE + 0x7800)
#define | CEC_CFGR_BPEM ((uint16_t)0x0008)
#define | CEC_CFGR_BTEM ((uint16_t)0x0004)
#define | CEC_CFGR_IE ((uint16_t)0x0002)
#define | CEC_CFGR_PE ((uint16_t)0x0001)
#define | CEC_CSR_RBTF ((uint16_t)0x0080)
#define | CEC_CSR_REOM ((uint16_t)0x0020)
#define | CEC_CSR_RERR ((uint16_t)0x0040)
#define | CEC_CSR_RSOM ((uint16_t)0x0010)
#define | CEC_CSR_TBTRF ((uint16_t)0x0008)
#define | CEC_CSR_TEOM ((uint16_t)0x0002)
#define | CEC_CSR_TERR ((uint16_t)0x0004)
#define | CEC_CSR_TSOM ((uint16_t)0x0001)
#define | CEC_ESR_ACKE ((uint16_t)0x0010)
#define | CEC_ESR_BPE ((uint16_t)0x0002)
#define | CEC_ESR_BTE ((uint16_t)0x0001)
#define | CEC_ESR_LINE ((uint16_t)0x0020)
#define | CEC_ESR_RBTFE ((uint16_t)0x0004)
#define | CEC_ESR_SBE ((uint16_t)0x0008)
#define | CEC_ESR_TBTFE ((uint16_t)0x0040)
#define | CEC_OAR_OA ((uint16_t)0x000F)
#define | CEC_OAR_OA_0 ((uint16_t)0x0001)
#define | CEC_OAR_OA_1 ((uint16_t)0x0002)
#define | CEC_OAR_OA_2 ((uint16_t)0x0004)
#define | CEC_OAR_OA_3 ((uint16_t)0x0008)
#define | CEC_PRES_PRES ((uint16_t)0x3FFF)
#define | CEC_RXD_RXD ((uint16_t)0x00FF)
#define | CEC_TXD_TXD ((uint16_t)0x00FF)
#define | CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
#define | CLEAR_REG(REG) ((REG) = (0x0))
#define | CRC ((CRC_TypeDef *) CRC_BASE)
#define | CRC_BASE (AHBPERIPH_BASE + 0x3000)
#define | CRC_CR_RESET ((uint8_t)0x01)
#define | CRC_DR_DR ((uint32_t)0xFFFFFFFF)
#define | CRC_IDR_IDR ((uint8_t)0xFF)
#define | DAC ((DAC_TypeDef *) DAC_BASE)
#define | DAC_BASE (APB1PERIPH_BASE + 0x7400)
#define | DAC_CR_BOFF1 ((uint32_t)0x00000002)
#define | DAC_CR_BOFF2 ((uint32_t)0x00020000)
#define | DAC_CR_DMAEN1 ((uint32_t)0x00001000)
#define | DAC_CR_DMAEN2 ((uint32_t)0x10000000)
#define | DAC_CR_EN1 ((uint32_t)0x00000001)
#define | DAC_CR_EN2 ((uint32_t)0x00010000)
#define | DAC_CR_MAMP1 ((uint32_t)0x00000F00)
#define | DAC_CR_MAMP1_0 ((uint32_t)0x00000100)
#define | DAC_CR_MAMP1_1 ((uint32_t)0x00000200)
#define | DAC_CR_MAMP1_2 ((uint32_t)0x00000400)
#define | DAC_CR_MAMP1_3 ((uint32_t)0x00000800)
#define | DAC_CR_MAMP2 ((uint32_t)0x0F000000)
#define | DAC_CR_MAMP2_0 ((uint32_t)0x01000000)
#define | DAC_CR_MAMP2_1 ((uint32_t)0x02000000)
#define | DAC_CR_MAMP2_2 ((uint32_t)0x04000000)
#define | DAC_CR_MAMP2_3 ((uint32_t)0x08000000)
#define | DAC_CR_TEN1 ((uint32_t)0x00000004)
#define | DAC_CR_TEN2 ((uint32_t)0x00040000)
#define | DAC_CR_TSEL1 ((uint32_t)0x00000038)
#define | DAC_CR_TSEL1_0 ((uint32_t)0x00000008)
#define | DAC_CR_TSEL1_1 ((uint32_t)0x00000010)
#define | DAC_CR_TSEL1_2 ((uint32_t)0x00000020)
#define | DAC_CR_TSEL2 ((uint32_t)0x00380000)
#define | DAC_CR_TSEL2_0 ((uint32_t)0x00080000)
#define | DAC_CR_TSEL2_1 ((uint32_t)0x00100000)
#define | DAC_CR_TSEL2_2 ((uint32_t)0x00200000)
#define | DAC_CR_WAVE1 ((uint32_t)0x000000C0)
#define | DAC_CR_WAVE1_0 ((uint32_t)0x00000040)
#define | DAC_CR_WAVE1_1 ((uint32_t)0x00000080)
#define | DAC_CR_WAVE2 ((uint32_t)0x00C00000)
#define | DAC_CR_WAVE2_0 ((uint32_t)0x00400000)
#define | DAC_CR_WAVE2_1 ((uint32_t)0x00800000)
#define | DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0)
#define | DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0)
#define | DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0)
#define | DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000)
#define | DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF)
#define | DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF)
#define | DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF)
#define | DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000)
#define | DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF)
#define | DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF)
#define | DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF)
#define | DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00)
#define | DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF)
#define | DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF)
#define | DAC_SR_DMAUDR1 ((uint32_t)0x00002000)
#define | DAC_SR_DMAUDR2 ((uint32_t)0x20000000)
#define | DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01)
#define | DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02)
#define | DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
#define | DBGMCU_BASE ((uint32_t)0xE0042000)
#define | DBGMCU_CR_DBG_CAN1_STOP ((uint32_t)0x00004000)
#define | DBGMCU_CR_DBG_CAN2_STOP ((uint32_t)0x00200000)
#define | DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000)
#define | DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000)
#define | DBGMCU_CR_DBG_IWDG_STOP ((uint32_t)0x00000100)
#define | DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001)
#define | DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004)
#define | DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002)
#define | DBGMCU_CR_DBG_TIM10_STOP ((uint32_t)0x20000000)
#define | DBGMCU_CR_DBG_TIM11_STOP ((uint32_t)0x40000000)
#define | DBGMCU_CR_DBG_TIM12_STOP ((uint32_t)0x02000000)
#define | DBGMCU_CR_DBG_TIM13_STOP ((uint32_t)0x04000000)
#define | DBGMCU_CR_DBG_TIM14_STOP ((uint32_t)0x08000000)
#define | DBGMCU_CR_DBG_TIM15_STOP ((uint32_t)0x00400000)
#define | DBGMCU_CR_DBG_TIM16_STOP ((uint32_t)0x00800000)
#define | DBGMCU_CR_DBG_TIM17_STOP ((uint32_t)0x01000000)
#define | DBGMCU_CR_DBG_TIM1_STOP ((uint32_t)0x00000400)
#define | DBGMCU_CR_DBG_TIM2_STOP ((uint32_t)0x00000800)
#define | DBGMCU_CR_DBG_TIM3_STOP ((uint32_t)0x00001000)
#define | DBGMCU_CR_DBG_TIM4_STOP ((uint32_t)0x00002000)
#define | DBGMCU_CR_DBG_TIM5_STOP ((uint32_t)0x00040000)
#define | DBGMCU_CR_DBG_TIM6_STOP ((uint32_t)0x00080000)
#define | DBGMCU_CR_DBG_TIM7_STOP ((uint32_t)0x00100000)
#define | DBGMCU_CR_DBG_TIM8_STOP ((uint32_t)0x00020000)
#define | DBGMCU_CR_DBG_TIM9_STOP ((uint32_t)0x10000000)
#define | DBGMCU_CR_DBG_WWDG_STOP ((uint32_t)0x00000200)
#define | DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020)
#define | DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0)
#define | DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040)
#define | DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080)
#define | DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF)
#define | DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000)
#define | DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000)
#define | DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000)
#define | DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000)
#define | DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000)
#define | DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000)
#define | DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000)
#define | DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000)
#define | DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000)
#define | DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000)
#define | DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000)
#define | DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000)
#define | DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000)
#define | DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000)
#define | DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000)
#define | DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000)
#define | DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000)
#define | DMA1 ((DMA_TypeDef *) DMA1_BASE)
#define | DMA1_BASE (AHBPERIPH_BASE + 0x0000)
#define | DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
#define | DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008)
#define | DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
#define | DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C)
#define | DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
#define | DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030)
#define | DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
#define | DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044)
#define | DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
#define | DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058)
#define | DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
#define | DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C)
#define | DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
#define | DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080)
#define | DMA2 ((DMA_TypeDef *) DMA2_BASE)
#define | DMA2_BASE (AHBPERIPH_BASE + 0x0400)
#define | DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
#define | DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408)
#define | DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
#define | DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C)
#define | DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
#define | DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430)
#define | DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
#define | DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444)
#define | DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
#define | DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458)
#define | DMA_CCR1_CIRC ((uint16_t)0x0020)
#define | DMA_CCR1_DIR ((uint16_t)0x0010)
#define | DMA_CCR1_EN ((uint16_t)0x0001)
#define | DMA_CCR1_HTIE ((uint16_t)0x0004)
#define | DMA_CCR1_MEM2MEM ((uint16_t)0x4000)
#define | DMA_CCR1_MINC ((uint16_t)0x0080)
#define | DMA_CCR1_MSIZE ((uint16_t)0x0C00)
#define | DMA_CCR1_MSIZE_0 ((uint16_t)0x0400)
#define | DMA_CCR1_MSIZE_1 ((uint16_t)0x0800)
#define | DMA_CCR1_PINC ((uint16_t)0x0040)
#define | DMA_CCR1_PL ((uint16_t)0x3000)
#define | DMA_CCR1_PL_0 ((uint16_t)0x1000)
#define | DMA_CCR1_PL_1 ((uint16_t)0x2000)
#define | DMA_CCR1_PSIZE ((uint16_t)0x0300)
#define | DMA_CCR1_PSIZE_0 ((uint16_t)0x0100)
#define | DMA_CCR1_PSIZE_1 ((uint16_t)0x0200)
#define | DMA_CCR1_TCIE ((uint16_t)0x0002)
#define | DMA_CCR1_TEIE ((uint16_t)0x0008)
#define | DMA_CCR2_CIRC ((uint16_t)0x0020)
#define | DMA_CCR2_DIR ((uint16_t)0x0010)
#define | DMA_CCR2_EN ((uint16_t)0x0001)
#define | DMA_CCR2_HTIE ((uint16_t)0x0004)
#define | DMA_CCR2_MEM2MEM ((uint16_t)0x4000)
#define | DMA_CCR2_MINC ((uint16_t)0x0080)
#define | DMA_CCR2_MSIZE ((uint16_t)0x0C00)
#define | DMA_CCR2_MSIZE_0 ((uint16_t)0x0400)
#define | DMA_CCR2_MSIZE_1 ((uint16_t)0x0800)
#define | DMA_CCR2_PINC ((uint16_t)0x0040)
#define | DMA_CCR2_PL ((uint16_t)0x3000)
#define | DMA_CCR2_PL_0 ((uint16_t)0x1000)
#define | DMA_CCR2_PL_1 ((uint16_t)0x2000)
#define | DMA_CCR2_PSIZE ((uint16_t)0x0300)
#define | DMA_CCR2_PSIZE_0 ((uint16_t)0x0100)
#define | DMA_CCR2_PSIZE_1 ((uint16_t)0x0200)
#define | DMA_CCR2_TCIE ((uint16_t)0x0002)
#define | DMA_CCR2_TEIE ((uint16_t)0x0008)
#define | DMA_CCR3_CIRC ((uint16_t)0x0020)
#define | DMA_CCR3_DIR ((uint16_t)0x0010)
#define | DMA_CCR3_EN ((uint16_t)0x0001)
#define | DMA_CCR3_HTIE ((uint16_t)0x0004)
#define | DMA_CCR3_MEM2MEM ((uint16_t)0x4000)
#define | DMA_CCR3_MINC ((uint16_t)0x0080)
#define | DMA_CCR3_MSIZE ((uint16_t)0x0C00)
#define | DMA_CCR3_MSIZE_0 ((uint16_t)0x0400)
#define | DMA_CCR3_MSIZE_1 ((uint16_t)0x0800)
#define | DMA_CCR3_PINC ((uint16_t)0x0040)
#define | DMA_CCR3_PL ((uint16_t)0x3000)
#define | DMA_CCR3_PL_0 ((uint16_t)0x1000)
#define | DMA_CCR3_PL_1 ((uint16_t)0x2000)
#define | DMA_CCR3_PSIZE ((uint16_t)0x0300)
#define | DMA_CCR3_PSIZE_0 ((uint16_t)0x0100)
#define | DMA_CCR3_PSIZE_1 ((uint16_t)0x0200)
#define | DMA_CCR3_TCIE ((uint16_t)0x0002)
#define | DMA_CCR3_TEIE ((uint16_t)0x0008)
#define | DMA_CCR4_CIRC ((uint16_t)0x0020)
#define | DMA_CCR4_DIR ((uint16_t)0x0010)
#define | DMA_CCR4_EN ((uint16_t)0x0001)
#define | DMA_CCR4_HTIE ((uint16_t)0x0004)
#define | DMA_CCR4_MEM2MEM ((uint16_t)0x4000)
#define | DMA_CCR4_MINC ((uint16_t)0x0080)
#define | DMA_CCR4_MSIZE ((uint16_t)0x0C00)
#define | DMA_CCR4_MSIZE_0 ((uint16_t)0x0400)
#define | DMA_CCR4_MSIZE_1 ((uint16_t)0x0800)
#define | DMA_CCR4_PINC ((uint16_t)0x0040)
#define | DMA_CCR4_PL ((uint16_t)0x3000)
#define | DMA_CCR4_PL_0 ((uint16_t)0x1000)
#define | DMA_CCR4_PL_1 ((uint16_t)0x2000)
#define | DMA_CCR4_PSIZE ((uint16_t)0x0300)
#define | DMA_CCR4_PSIZE_0 ((uint16_t)0x0100)
#define | DMA_CCR4_PSIZE_1 ((uint16_t)0x0200)
#define | DMA_CCR4_TCIE ((uint16_t)0x0002)
#define | DMA_CCR4_TEIE ((uint16_t)0x0008)
#define | DMA_CCR5_CIRC ((uint16_t)0x0020)
#define | DMA_CCR5_DIR ((uint16_t)0x0010)
#define | DMA_CCR5_EN ((uint16_t)0x0001)
#define | DMA_CCR5_HTIE ((uint16_t)0x0004)
#define | DMA_CCR5_MEM2MEM ((uint16_t)0x4000)
#define | DMA_CCR5_MINC ((uint16_t)0x0080)
#define | DMA_CCR5_MSIZE ((uint16_t)0x0C00)
#define | DMA_CCR5_MSIZE_0 ((uint16_t)0x0400)
#define | DMA_CCR5_MSIZE_1 ((uint16_t)0x0800)
#define | DMA_CCR5_PINC ((uint16_t)0x0040)
#define | DMA_CCR5_PL ((uint16_t)0x3000)
#define | DMA_CCR5_PL_0 ((uint16_t)0x1000)
#define | DMA_CCR5_PL_1 ((uint16_t)0x2000)
#define | DMA_CCR5_PSIZE ((uint16_t)0x0300)
#define | DMA_CCR5_PSIZE_0 ((uint16_t)0x0100)
#define | DMA_CCR5_PSIZE_1 ((uint16_t)0x0200)
#define | DMA_CCR5_TCIE ((uint16_t)0x0002)
#define | DMA_CCR5_TEIE ((uint16_t)0x0008)
#define | DMA_CCR6_CIRC ((uint16_t)0x0020)
#define | DMA_CCR6_DIR ((uint16_t)0x0010)
#define | DMA_CCR6_EN ((uint16_t)0x0001)
#define | DMA_CCR6_HTIE ((uint16_t)0x0004)
#define | DMA_CCR6_MEM2MEM ((uint16_t)0x4000)
#define | DMA_CCR6_MINC ((uint16_t)0x0080)
#define | DMA_CCR6_MSIZE ((uint16_t)0x0C00)
#define | DMA_CCR6_MSIZE_0 ((uint16_t)0x0400)
#define | DMA_CCR6_MSIZE_1 ((uint16_t)0x0800)
#define | DMA_CCR6_PINC ((uint16_t)0x0040)
#define | DMA_CCR6_PL ((uint16_t)0x3000)
#define | DMA_CCR6_PL_0 ((uint16_t)0x1000)
#define | DMA_CCR6_PL_1 ((uint16_t)0x2000)
#define | DMA_CCR6_PSIZE ((uint16_t)0x0300)
#define | DMA_CCR6_PSIZE_0 ((uint16_t)0x0100)
#define | DMA_CCR6_PSIZE_1 ((uint16_t)0x0200)
#define | DMA_CCR6_TCIE ((uint16_t)0x0002)
#define | DMA_CCR6_TEIE ((uint16_t)0x0008)
#define | DMA_CCR7_CIRC ((uint16_t)0x0020)
#define | DMA_CCR7_DIR ((uint16_t)0x0010)
#define | DMA_CCR7_EN ((uint16_t)0x0001)
#define | DMA_CCR7_HTIE ((uint16_t)0x0004)
#define | DMA_CCR7_MEM2MEM ((uint16_t)0x4000)
#define | DMA_CCR7_MINC ((uint16_t)0x0080)
#define | DMA_CCR7_MSIZE ((uint16_t)0x0C00)
#define | DMA_CCR7_MSIZE_0 ((uint16_t)0x0400)
#define | DMA_CCR7_MSIZE_1 ((uint16_t)0x0800)
#define | DMA_CCR7_PINC ((uint16_t)0x0040)
#define | DMA_CCR7_PL ((uint16_t)0x3000)
#define | DMA_CCR7_PL_0 ((uint16_t)0x1000)
#define | DMA_CCR7_PL_1 ((uint16_t)0x2000)
#define | DMA_CCR7_PSIZE , ((uint16_t)0x0300)
#define | DMA_CCR7_PSIZE_0 ((uint16_t)0x0100)
#define | DMA_CCR7_PSIZE_1 ((uint16_t)0x0200)
#define | DMA_CCR7_TCIE ((uint16_t)0x0002)
#define | DMA_CCR7_TEIE ((uint16_t)0x0008)
#define | DMA_CMAR1_MA ((uint32_t)0xFFFFFFFF)
#define | DMA_CMAR2_MA ((uint32_t)0xFFFFFFFF)
#define | DMA_CMAR3_MA ((uint32_t)0xFFFFFFFF)
#define | DMA_CMAR4_MA ((uint32_t)0xFFFFFFFF)
#define | DMA_CMAR5_MA ((uint32_t)0xFFFFFFFF)
#define | DMA_CMAR6_MA ((uint32_t)0xFFFFFFFF)
#define | DMA_CMAR7_MA ((uint32_t)0xFFFFFFFF)
#define | DMA_CNDTR1_NDT ((uint16_t)0xFFFF)
#define | DMA_CNDTR2_NDT ((uint16_t)0xFFFF)
#define | DMA_CNDTR3_NDT ((uint16_t)0xFFFF)
#define | DMA_CNDTR4_NDT ((uint16_t)0xFFFF)
#define | DMA_CNDTR5_NDT ((uint16_t)0xFFFF)
#define | DMA_CNDTR6_NDT ((uint16_t)0xFFFF)
#define | DMA_CNDTR7_NDT ((uint16_t)0xFFFF)
#define | DMA_CPAR1_PA ((uint32_t)0xFFFFFFFF)
#define | DMA_CPAR2_PA ((uint32_t)0xFFFFFFFF)
#define | DMA_CPAR3_PA ((uint32_t)0xFFFFFFFF)
#define | DMA_CPAR4_PA ((uint32_t)0xFFFFFFFF)
#define | DMA_CPAR5_PA ((uint32_t)0xFFFFFFFF)
#define | DMA_CPAR6_PA ((uint32_t)0xFFFFFFFF)
#define | DMA_CPAR7_PA ((uint32_t)0xFFFFFFFF)
#define | DMA_IFCR_CGIF1 ((uint32_t)0x00000001)
#define | DMA_IFCR_CGIF2 ((uint32_t)0x00000010)
#define | DMA_IFCR_CGIF3 ((uint32_t)0x00000100)
#define | DMA_IFCR_CGIF4 ((uint32_t)0x00001000)
#define | DMA_IFCR_CGIF5 ((uint32_t)0x00010000)
#define | DMA_IFCR_CGIF6 ((uint32_t)0x00100000)
#define | DMA_IFCR_CGIF7 ((uint32_t)0x01000000)
#define | DMA_IFCR_CHTIF1 ((uint32_t)0x00000004)
#define | DMA_IFCR_CHTIF2 ((uint32_t)0x00000040)
#define | DMA_IFCR_CHTIF3 ((uint32_t)0x00000400)
#define | DMA_IFCR_CHTIF4 ((uint32_t)0x00004000)
#define | DMA_IFCR_CHTIF5 ((uint32_t)0x00040000)
#define | DMA_IFCR_CHTIF6 ((uint32_t)0x00400000)
#define | DMA_IFCR_CHTIF7 ((uint32_t)0x04000000)
#define | DMA_IFCR_CTCIF1 ((uint32_t)0x00000002)
#define | DMA_IFCR_CTCIF2 ((uint32_t)0x00000020)
#define | DMA_IFCR_CTCIF3 ((uint32_t)0x00000200)
#define | DMA_IFCR_CTCIF4 ((uint32_t)0x00002000)
#define | DMA_IFCR_CTCIF5 ((uint32_t)0x00020000)
#define | DMA_IFCR_CTCIF6 ((uint32_t)0x00200000)
#define | DMA_IFCR_CTCIF7 ((uint32_t)0x02000000)
#define | DMA_IFCR_CTEIF1 ((uint32_t)0x00000008)
#define | DMA_IFCR_CTEIF2 ((uint32_t)0x00000080)
#define | DMA_IFCR_CTEIF3 ((uint32_t)0x00000800)
#define | DMA_IFCR_CTEIF4 ((uint32_t)0x00008000)
#define | DMA_IFCR_CTEIF5 ((uint32_t)0x00080000)
#define | DMA_IFCR_CTEIF6 ((uint32_t)0x00800000)
#define | DMA_IFCR_CTEIF7 ((uint32_t)0x08000000)
#define | DMA_ISR_GIF1 ((uint32_t)0x00000001)
#define | DMA_ISR_GIF2 ((uint32_t)0x00000010)
#define | DMA_ISR_GIF3 ((uint32_t)0x00000100)
#define | DMA_ISR_GIF4 ((uint32_t)0x00001000)
#define | DMA_ISR_GIF5 ((uint32_t)0x00010000)
#define | DMA_ISR_GIF6 ((uint32_t)0x00100000)
#define | DMA_ISR_GIF7 ((uint32_t)0x01000000)
#define | DMA_ISR_HTIF1 ((uint32_t)0x00000004)
#define | DMA_ISR_HTIF2 ((uint32_t)0x00000040)
#define | DMA_ISR_HTIF3 ((uint32_t)0x00000400)
#define | DMA_ISR_HTIF4 ((uint32_t)0x00004000)
#define | DMA_ISR_HTIF5 ((uint32_t)0x00040000)
#define | DMA_ISR_HTIF6 ((uint32_t)0x00400000)
#define | DMA_ISR_HTIF7 ((uint32_t)0x04000000)
#define | DMA_ISR_TCIF1 ((uint32_t)0x00000002)
#define | DMA_ISR_TCIF2 ((uint32_t)0x00000020)
#define | DMA_ISR_TCIF3 ((uint32_t)0x00000200)
#define | DMA_ISR_TCIF4 ((uint32_t)0x00002000)
#define | DMA_ISR_TCIF5 ((uint32_t)0x00020000)
#define | DMA_ISR_TCIF6 ((uint32_t)0x00200000)
#define | DMA_ISR_TCIF7 ((uint32_t)0x02000000)
#define | DMA_ISR_TEIF1 ((uint32_t)0x00000008)
#define | DMA_ISR_TEIF2 ((uint32_t)0x00000080)
#define | DMA_ISR_TEIF3 ((uint32_t)0x00000800)
#define | DMA_ISR_TEIF4 ((uint32_t)0x00008000)
#define | DMA_ISR_TEIF5 ((uint32_t)0x00080000)
#define | DMA_ISR_TEIF6 ((uint32_t)0x00800000)
#define | DMA_ISR_TEIF7 ((uint32_t)0x08000000)
#define | ETH ((ETH_TypeDef *) ETH_BASE)
#define | ETH_BASE (AHBPERIPH_BASE + 0x8000)
#define | ETH_DMA_BASE (ETH_BASE + 0x1000)
#define | ETH_MAC_BASE (ETH_BASE)
#define | ETH_MMC_BASE (ETH_BASE + 0x0100)
#define | ETH_PTP_BASE (ETH_BASE + 0x0700)
#define | EXTI ((EXTI_TypeDef *) EXTI_BASE)
#define | EXTI_BASE (APB2PERIPH_BASE + 0x0400)
#define | EXTI_EMR_MR0 ((uint32_t)0x00000001)
#define | EXTI_EMR_MR1 ((uint32_t)0x00000002)
#define | EXTI_EMR_MR10 ((uint32_t)0x00000400)
#define | EXTI_EMR_MR11 ((uint32_t)0x00000800)
#define | EXTI_EMR_MR12 ((uint32_t)0x00001000)
#define | EXTI_EMR_MR13 ((uint32_t)0x00002000)
#define | EXTI_EMR_MR14 ((uint32_t)0x00004000)
#define | EXTI_EMR_MR15 ((uint32_t)0x00008000)
#define | EXTI_EMR_MR16 ((uint32_t)0x00010000)
#define | EXTI_EMR_MR17 ((uint32_t)0x00020000)
#define | EXTI_EMR_MR18 ((uint32_t)0x00040000)
#define | EXTI_EMR_MR19 ((uint32_t)0x00080000)
#define | EXTI_EMR_MR2 ((uint32_t)0x00000004)
#define | EXTI_EMR_MR3 ((uint32_t)0x00000008)
#define | EXTI_EMR_MR4 ((uint32_t)0x00000010)
#define | EXTI_EMR_MR5 ((uint32_t)0x00000020)
#define | EXTI_EMR_MR6 ((uint32_t)0x00000040)
#define | EXTI_EMR_MR7 ((uint32_t)0x00000080)
#define | EXTI_EMR_MR8 ((uint32_t)0x00000100)
#define | EXTI_EMR_MR9 ((uint32_t)0x00000200)
#define | EXTI_FTSR_TR0 ((uint32_t)0x00000001)
#define | EXTI_FTSR_TR1 ((uint32_t)0x00000002)
#define | EXTI_FTSR_TR10 ((uint32_t)0x00000400)
#define | EXTI_FTSR_TR11 ((uint32_t)0x00000800)
#define | EXTI_FTSR_TR12 ((uint32_t)0x00001000)
#define | EXTI_FTSR_TR13 ((uint32_t)0x00002000)
#define | EXTI_FTSR_TR14 ((uint32_t)0x00004000)
#define | EXTI_FTSR_TR15 ((uint32_t)0x00008000)
#define | EXTI_FTSR_TR16 ((uint32_t)0x00010000)
#define | EXTI_FTSR_TR17 ((uint32_t)0x00020000)
#define | EXTI_FTSR_TR18 ((uint32_t)0x00040000)
#define | EXTI_FTSR_TR19 ((uint32_t)0x00080000)
#define | EXTI_FTSR_TR2 ((uint32_t)0x00000004)
#define | EXTI_FTSR_TR3 ((uint32_t)0x00000008)
#define | EXTI_FTSR_TR4 ((uint32_t)0x00000010)
#define | EXTI_FTSR_TR5 ((uint32_t)0x00000020)
#define | EXTI_FTSR_TR6 ((uint32_t)0x00000040)
#define | EXTI_FTSR_TR7 ((uint32_t)0x00000080)
#define | EXTI_FTSR_TR8 ((uint32_t)0x00000100)
#define | EXTI_FTSR_TR9 ((uint32_t)0x00000200)
#define | EXTI_IMR_MR0 ((uint32_t)0x00000001)
#define | EXTI_IMR_MR1 ((uint32_t)0x00000002)
#define | EXTI_IMR_MR10 ((uint32_t)0x00000400)
#define | EXTI_IMR_MR11 ((uint32_t)0x00000800)
#define | EXTI_IMR_MR12 ((uint32_t)0x00001000)
#define | EXTI_IMR_MR13 ((uint32_t)0x00002000)
#define | EXTI_IMR_MR14 ((uint32_t)0x00004000)
#define | EXTI_IMR_MR15 ((uint32_t)0x00008000)
#define | EXTI_IMR_MR16 ((uint32_t)0x00010000)
#define | EXTI_IMR_MR17 ((uint32_t)0x00020000)
#define | EXTI_IMR_MR18 ((uint32_t)0x00040000)
#define | EXTI_IMR_MR19 ((uint32_t)0x00080000)
#define | EXTI_IMR_MR2 ((uint32_t)0x00000004)
#define | EXTI_IMR_MR3 ((uint32_t)0x00000008)
#define | EXTI_IMR_MR4 ((uint32_t)0x00000010)
#define | EXTI_IMR_MR5 ((uint32_t)0x00000020)
#define | EXTI_IMR_MR6 ((uint32_t)0x00000040)
#define | EXTI_IMR_MR7 ((uint32_t)0x00000080)
#define | EXTI_IMR_MR8 ((uint32_t)0x00000100)
#define | EXTI_IMR_MR9 ((uint32_t)0x00000200)
#define | EXTI_PR_PR0 ((uint32_t)0x00000001)
#define | EXTI_PR_PR1 ((uint32_t)0x00000002)
#define | EXTI_PR_PR10 ((uint32_t)0x00000400)
#define | EXTI_PR_PR11 ((uint32_t)0x00000800)
#define | EXTI_PR_PR12 ((uint32_t)0x00001000)
#define | EXTI_PR_PR13 ((uint32_t)0x00002000)
#define | EXTI_PR_PR14 ((uint32_t)0x00004000)
#define | EXTI_PR_PR15 ((uint32_t)0x00008000)
#define | EXTI_PR_PR16 ((uint32_t)0x00010000)
#define | EXTI_PR_PR17 ((uint32_t)0x00020000)
#define | EXTI_PR_PR18 ((uint32_t)0x00040000)
#define | EXTI_PR_PR19 ((uint32_t)0x00080000)
#define | EXTI_PR_PR2 ((uint32_t)0x00000004)
#define | EXTI_PR_PR3 ((uint32_t)0x00000008)
#define | EXTI_PR_PR4 ((uint32_t)0x00000010)
#define | EXTI_PR_PR5 ((uint32_t)0x00000020)
#define | EXTI_PR_PR6 ((uint32_t)0x00000040)
#define | EXTI_PR_PR7 ((uint32_t)0x00000080)
#define | EXTI_PR_PR8 ((uint32_t)0x00000100)
#define | EXTI_PR_PR9 ((uint32_t)0x00000200)
#define | EXTI_RTSR_TR0 ((uint32_t)0x00000001)
#define | EXTI_RTSR_TR1 ((uint32_t)0x00000002)
#define | EXTI_RTSR_TR10 ((uint32_t)0x00000400)
#define | EXTI_RTSR_TR11 ((uint32_t)0x00000800)
#define | EXTI_RTSR_TR12 ((uint32_t)0x00001000)
#define | EXTI_RTSR_TR13 ((uint32_t)0x00002000)
#define | EXTI_RTSR_TR14 ((uint32_t)0x00004000)
#define | EXTI_RTSR_TR15 ((uint32_t)0x00008000)
#define | EXTI_RTSR_TR16 ((uint32_t)0x00010000)
#define | EXTI_RTSR_TR17 ((uint32_t)0x00020000)
#define | EXTI_RTSR_TR18 ((uint32_t)0x00040000)
#define | EXTI_RTSR_TR19 ((uint32_t)0x00080000)
#define | EXTI_RTSR_TR2 ((uint32_t)0x00000004)
#define | EXTI_RTSR_TR3 ((uint32_t)0x00000008)
#define | EXTI_RTSR_TR4 ((uint32_t)0x00000010)
#define | EXTI_RTSR_TR5 ((uint32_t)0x00000020)
#define | EXTI_RTSR_TR6 ((uint32_t)0x00000040)
#define | EXTI_RTSR_TR7 ((uint32_t)0x00000080)
#define | EXTI_RTSR_TR8 ((uint32_t)0x00000100)
#define | EXTI_RTSR_TR9 ((uint32_t)0x00000200)
#define | EXTI_SWIER_SWIER0 ((uint32_t)0x00000001)
#define | EXTI_SWIER_SWIER1 ((uint32_t)0x00000002)
#define | EXTI_SWIER_SWIER10 ((uint32_t)0x00000400)
#define | EXTI_SWIER_SWIER11 ((uint32_t)0x00000800)
#define | EXTI_SWIER_SWIER12 ((uint32_t)0x00001000)
#define | EXTI_SWIER_SWIER13 ((uint32_t)0x00002000)
#define | EXTI_SWIER_SWIER14 ((uint32_t)0x00004000)
#define | EXTI_SWIER_SWIER15 ((uint32_t)0x00008000)
#define | EXTI_SWIER_SWIER16 ((uint32_t)0x00010000)
#define | EXTI_SWIER_SWIER17 ((uint32_t)0x00020000)
#define | EXTI_SWIER_SWIER18 ((uint32_t)0x00040000)
#define | EXTI_SWIER_SWIER19 ((uint32_t)0x00080000)
#define | EXTI_SWIER_SWIER2 ((uint32_t)0x00000004)
#define | EXTI_SWIER_SWIER3 ((uint32_t)0x00000008)
#define | EXTI_SWIER_SWIER4 ((uint32_t)0x00000010)
#define | EXTI_SWIER_SWIER5 ((uint32_t)0x00000020)
#define | EXTI_SWIER_SWIER6 ((uint32_t)0x00000040)
#define | EXTI_SWIER_SWIER7 ((uint32_t)0x00000080)
#define | EXTI_SWIER_SWIER8 ((uint32_t)0x00000100)
#define | EXTI_SWIER_SWIER9 ((uint32_t)0x00000200)
#define | FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
#define | FLASH_ACR_HLFCYA ((uint8_t)0x08)
#define | FLASH_ACR_LATENCY ((uint8_t)0x03)
#define | FLASH_ACR_LATENCY_0 ((uint8_t)0x00)
#define | FLASH_ACR_LATENCY_1 ((uint8_t)0x01)
#define | FLASH_ACR_LATENCY_2 ((uint8_t)0x02)
#define | FLASH_ACR_PRFTBE ((uint8_t)0x10)
#define | FLASH_ACR_PRFTBS ((uint8_t)0x20)
#define | FLASH_AR_FAR ((uint32_t)0xFFFFFFFF)
#define | FLASH_BASE ((uint32_t)0x08000000)
#define | FLASH_CR_EOPIE ((uint16_t)0x1000)
#define | FLASH_CR_ERRIE ((uint16_t)0x0400)
#define | FLASH_CR_LOCK ((uint16_t)0x0080)
#define | FLASH_CR_MER ((uint16_t)0x0004)
#define | FLASH_CR_OPTER ((uint16_t)0x0020)
#define | FLASH_CR_OPTPG ((uint16_t)0x0010)
#define | FLASH_CR_OPTWRE ((uint16_t)0x0200)
#define | FLASH_CR_PER ((uint16_t)0x0002)
#define | FLASH_CR_PG ((uint16_t)0x0001)
#define | FLASH_CR_STRT ((uint16_t)0x0040)
#define | FLASH_Data0_Data0 ((uint32_t)0x000000FF)
#define | FLASH_Data0_nData0 ((uint32_t)0x0000FF00)
#define | FLASH_Data1_Data1 ((uint32_t)0x00FF0000)
#define | FLASH_Data1_nData1 ((uint32_t)0xFF000000)
#define | FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF)
#define | FLASH_OBR_BFB2 ((uint16_t)0x0020)
#define | FLASH_OBR_nRST_STDBY ((uint16_t)0x0010)
#define | FLASH_OBR_nRST_STOP ((uint16_t)0x0008)
#define | FLASH_OBR_OPTERR ((uint16_t)0x0001)
#define | FLASH_OBR_RDPRT ((uint16_t)0x0002)
#define | FLASH_OBR_USER ((uint16_t)0x03FC)
#define | FLASH_OBR_WDG_SW ((uint16_t)0x0004)
#define | FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF)
#define | FLASH_R_BASE (AHBPERIPH_BASE + 0x2000)
#define | FLASH_RDP_nRDP ((uint32_t)0x0000FF00)
#define | FLASH_RDP_RDP ((uint32_t)0x000000FF)
#define | FLASH_SR_BSY ((uint8_t)0x01)
#define | FLASH_SR_EOP ((uint8_t)0x20)
#define | FLASH_SR_PGERR ((uint8_t)0x04)
#define | FLASH_SR_WRPRTERR ((uint8_t)0x10)
#define | FLASH_USER_nUSER ((uint32_t)0xFF000000)
#define | FLASH_USER_USER ((uint32_t)0x00FF0000)
#define | FLASH_WRP0_nWRP0 ((uint32_t)0x0000FF00)
#define | FLASH_WRP0_WRP0 ((uint32_t)0x000000FF)
#define | FLASH_WRP1_nWRP1 ((uint32_t)0xFF000000)
#define | FLASH_WRP1_WRP1 ((uint32_t)0x00FF0000)
#define | FLASH_WRP2_nWRP2 ((uint32_t)0x0000FF00)
#define | FLASH_WRP2_WRP2 ((uint32_t)0x000000FF)
#define | FLASH_WRP3_nWRP3 ((uint32_t)0xFF000000)
#define | FLASH_WRP3_WRP3 ((uint32_t)0x00FF0000)
#define | FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF)
#define | FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
#define | FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000)
#define | FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
#define | FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104)
#define | FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE)
#define | FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060)
#define | FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE)
#define | FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080)
#define | FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
#define | FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0)
#define | FSMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000)
#define | FSMC_BCR1_BURSTEN ((uint32_t)0x00000100)
#define | FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000)
#define | FSMC_BCR1_EXTMOD ((uint32_t)0x00004000)
#define | FSMC_BCR1_FACCEN ((uint32_t)0x00000040)
#define | FSMC_BCR1_MBKEN ((uint32_t)0x00000001)
#define | FSMC_BCR1_MTYP ((uint32_t)0x0000000C)
#define | FSMC_BCR1_MTYP_0 ((uint32_t)0x00000004)
#define | FSMC_BCR1_MTYP_1 ((uint32_t)0x00000008)
#define | FSMC_BCR1_MUXEN ((uint32_t)0x00000002)
#define | FSMC_BCR1_MWID ((uint32_t)0x00000030)
#define | FSMC_BCR1_MWID_0 ((uint32_t)0x00000010)
#define | FSMC_BCR1_MWID_1 ((uint32_t)0x00000020)
#define | FSMC_BCR1_WAITCFG ((uint32_t)0x00000800)
#define | FSMC_BCR1_WAITEN ((uint32_t)0x00002000)
#define | FSMC_BCR1_WAITPOL ((uint32_t)0x00000200)
#define | FSMC_BCR1_WRAPMOD ((uint32_t)0x00000400)
#define | FSMC_BCR1_WREN ((uint32_t)0x00001000)
#define | FSMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000)
#define | FSMC_BCR2_BURSTEN ((uint32_t)0x00000100)
#define | FSMC_BCR2_CBURSTRW ((uint32_t)0x00080000)
#define | FSMC_BCR2_EXTMOD ((uint32_t)0x00004000)
#define | FSMC_BCR2_FACCEN ((uint32_t)0x00000040)
#define | FSMC_BCR2_MBKEN ((uint32_t)0x00000001)
#define | FSMC_BCR2_MTYP ((uint32_t)0x0000000C)
#define | FSMC_BCR2_MTYP_0 ((uint32_t)0x00000004)
#define | FSMC_BCR2_MTYP_1 ((uint32_t)0x00000008)
#define | FSMC_BCR2_MUXEN ((uint32_t)0x00000002)
#define | FSMC_BCR2_MWID ((uint32_t)0x00000030)
#define | FSMC_BCR2_MWID_0 ((uint32_t)0x00000010)
#define | FSMC_BCR2_MWID_1 ((uint32_t)0x00000020)
#define | FSMC_BCR2_WAITCFG ((uint32_t)0x00000800)
#define | FSMC_BCR2_WAITEN ((uint32_t)0x00002000)
#define | FSMC_BCR2_WAITPOL ((uint32_t)0x00000200)
#define | FSMC_BCR2_WRAPMOD ((uint32_t)0x00000400)
#define | FSMC_BCR2_WREN ((uint32_t)0x00001000)
#define | FSMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000)
#define | FSMC_BCR3_BURSTEN ((uint32_t)0x00000100)
#define | FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000)
#define | FSMC_BCR3_EXTMOD ((uint32_t)0x00004000)
#define | FSMC_BCR3_FACCEN ((uint32_t)0x00000040)
#define | FSMC_BCR3_MBKEN ((uint32_t)0x00000001)
#define | FSMC_BCR3_MTYP ((uint32_t)0x0000000C)
#define | FSMC_BCR3_MTYP_0 ((uint32_t)0x00000004)
#define | FSMC_BCR3_MTYP_1 ((uint32_t)0x00000008)
#define | FSMC_BCR3_MUXEN ((uint32_t)0x00000002)
#define | FSMC_BCR3_MWID ((uint32_t)0x00000030)
#define | FSMC_BCR3_MWID_0 ((uint32_t)0x00000010)
#define | FSMC_BCR3_MWID_1 ((uint32_t)0x00000020)
#define | FSMC_BCR3_WAITCFG ((uint32_t)0x00000800)
#define | FSMC_BCR3_WAITEN ((uint32_t)0x00002000)
#define | FSMC_BCR3_WAITPOL ((uint32_t)0x00000200)
#define | FSMC_BCR3_WRAPMOD ((uint32_t)0x00000400)
#define | FSMC_BCR3_WREN ((uint32_t)0x00001000)
#define | FSMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000)
#define | FSMC_BCR4_BURSTEN ((uint32_t)0x00000100)
#define | FSMC_BCR4_CBURSTRW ((uint32_t)0x00080000)
#define | FSMC_BCR4_EXTMOD ((uint32_t)0x00004000)
#define | FSMC_BCR4_FACCEN ((uint32_t)0x00000040)
#define | FSMC_BCR4_MBKEN ((uint32_t)0x00000001)
#define | FSMC_BCR4_MTYP ((uint32_t)0x0000000C)
#define | FSMC_BCR4_MTYP_0 ((uint32_t)0x00000004)
#define | FSMC_BCR4_MTYP_1 ((uint32_t)0x00000008)
#define | FSMC_BCR4_MUXEN ((uint32_t)0x00000002)
#define | FSMC_BCR4_MWID ((uint32_t)0x00000030)
#define | FSMC_BCR4_MWID_0 ((uint32_t)0x00000010)
#define | FSMC_BCR4_MWID_1 ((uint32_t)0x00000020)
#define | FSMC_BCR4_WAITCFG ((uint32_t)0x00000800)
#define | FSMC_BCR4_WAITEN ((uint32_t)0x00002000)
#define | FSMC_BCR4_WAITPOL ((uint32_t)0x00000200)
#define | FSMC_BCR4_WRAPMOD ((uint32_t)0x00000400)
#define | FSMC_BCR4_WREN ((uint32_t)0x00001000)
#define | FSMC_BTR1_ACCMOD ((uint32_t)0x30000000)
#define | FSMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000)
#define | FSMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000)
#define | FSMC_BTR1_ADDHLD ((uint32_t)0x000000F0)
#define | FSMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010)
#define | FSMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020)
#define | FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040)
#define | FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080)
#define | FSMC_BTR1_ADDSET ((uint32_t)0x0000000F)
#define | FSMC_BTR1_ADDSET_0 ((uint32_t)0x00000001)
#define | FSMC_BTR1_ADDSET_1 ((uint32_t)0x00000002)
#define | FSMC_BTR1_ADDSET_2 ((uint32_t)0x00000004)
#define | FSMC_BTR1_ADDSET_3 ((uint32_t)0x00000008)
#define | FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000)
#define | FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000)
#define | FSMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000)
#define | FSMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000)
#define | FSMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000)
#define | FSMC_BTR1_CLKDIV ((uint32_t)0x00F00000)
#define | FSMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000)
#define | FSMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000)
#define | FSMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000)
#define | FSMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000)
#define | FSMC_BTR1_DATAST ((uint32_t)0x0000FF00)
#define | FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100)
#define | FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200)
#define | FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400)
#define | FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800)
#define | FSMC_BTR1_DATLAT ((uint32_t)0x0F000000)
#define | FSMC_BTR1_DATLAT_0 ((uint32_t)0x01000000)
#define | FSMC_BTR1_DATLAT_1 ((uint32_t)0x02000000)
#define | FSMC_BTR1_DATLAT_2 ((uint32_t)0x04000000)
#define | FSMC_BTR1_DATLAT_3 ((uint32_t)0x08000000)
#define | FSMC_BTR2_ACCMOD ((uint32_t)0x30000000)
#define | FSMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000)
#define | FSMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000)
#define | FSMC_BTR2_ADDHLD ((uint32_t)0x000000F0)
#define | FSMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010)
#define | FSMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020)
#define | FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040)
#define | FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080)
#define | FSMC_BTR2_ADDSET ((uint32_t)0x0000000F)
#define | FSMC_BTR2_ADDSET_0 ((uint32_t)0x00000001)
#define | FSMC_BTR2_ADDSET_1 ((uint32_t)0x00000002)
#define | FSMC_BTR2_ADDSET_2 ((uint32_t)0x00000004)
#define | FSMC_BTR2_ADDSET_3 ((uint32_t)0x00000008)
#define | FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000)
#define | FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000)
#define | FSMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000)
#define | FSMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000)
#define | FSMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000)
#define | FSMC_BTR2_CLKDIV ((uint32_t)0x00F00000)
#define | FSMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000)
#define | FSMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000)
#define | FSMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000)
#define | FSMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000)
#define | FSMC_BTR2_DATAST ((uint32_t)0x0000FF00)
#define | FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100)
#define | FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200)
#define | FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400)
#define | FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800)
#define | FSMC_BTR2_DATLAT ((uint32_t)0x0F000000)
#define | FSMC_BTR2_DATLAT_0 ((uint32_t)0x01000000)
#define | FSMC_BTR2_DATLAT_1 ((uint32_t)0x02000000)
#define | FSMC_BTR2_DATLAT_2 ((uint32_t)0x04000000)
#define | FSMC_BTR2_DATLAT_3 ((uint32_t)0x08000000)
#define | FSMC_BTR3_ACCMOD ((uint32_t)0x30000000)
#define | FSMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000)
#define | FSMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000)
#define | FSMC_BTR3_ADDHLD ((uint32_t)0x000000F0)
#define | FSMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010)
#define | FSMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020)
#define | FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040)
#define | FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080)
#define | FSMC_BTR3_ADDSET ((uint32_t)0x0000000F)
#define | FSMC_BTR3_ADDSET_0 ((uint32_t)0x00000001)
#define | FSMC_BTR3_ADDSET_1 ((uint32_t)0x00000002)
#define | FSMC_BTR3_ADDSET_2 ((uint32_t)0x00000004)
#define | FSMC_BTR3_ADDSET_3 ((uint32_t)0x00000008)
#define | FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000)
#define | FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000)
#define | FSMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000)
#define | FSMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000)
#define | FSMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000)
#define | FSMC_BTR3_CLKDIV ((uint32_t)0x00F00000)
#define | FSMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000)
#define | FSMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000)
#define | FSMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000)
#define | FSMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000)
#define | FSMC_BTR3_DATAST ((uint32_t)0x0000FF00)
#define | FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100)
#define | FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200)
#define | FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400)
#define | FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800)
#define | FSMC_BTR3_DATLAT ((uint32_t)0x0F000000)
#define | FSMC_BTR3_DATLAT_0 ((uint32_t)0x01000000)
#define | FSMC_BTR3_DATLAT_1 ((uint32_t)0x02000000)
#define | FSMC_BTR3_DATLAT_2 ((uint32_t)0x04000000)
#define | FSMC_BTR3_DATLAT_3 ((uint32_t)0x08000000)
#define | FSMC_BTR4_ACCMOD ((uint32_t)0x30000000)
#define | FSMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000)
#define | FSMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000)
#define | FSMC_BTR4_ADDHLD ((uint32_t)0x000000F0)
#define | FSMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010)
#define | FSMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020)
#define | FSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040)
#define | FSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080)
#define | FSMC_BTR4_ADDSET ((uint32_t)0x0000000F)
#define | FSMC_BTR4_ADDSET_0 ((uint32_t)0x00000001)
#define | FSMC_BTR4_ADDSET_1 ((uint32_t)0x00000002)
#define | FSMC_BTR4_ADDSET_2 ((uint32_t)0x00000004)
#define | FSMC_BTR4_ADDSET_3 ((uint32_t)0x00000008)
#define | FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000)
#define | FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000)
#define | FSMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000)
#define | FSMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000)
#define | FSMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000)
#define | FSMC_BTR4_CLKDIV ((uint32_t)0x00F00000)
#define | FSMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000)
#define | FSMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000)
#define | FSMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000)
#define | FSMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000)
#define | FSMC_BTR4_DATAST ((uint32_t)0x0000FF00)
#define | FSMC_BTR4_DATAST_0 ((uint32_t)0x00000100)
#define | FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200)
#define | FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400)
#define | FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800)
#define | FSMC_BTR4_DATLAT ((uint32_t)0x0F000000)
#define | FSMC_BTR4_DATLAT_0 ((uint32_t)0x01000000)
#define | FSMC_BTR4_DATLAT_1 ((uint32_t)0x02000000)
#define | FSMC_BTR4_DATLAT_2 ((uint32_t)0x04000000)
#define | FSMC_BTR4_DATLAT_3 ((uint32_t)0x08000000)
#define | FSMC_BWTR1_ACCMOD ((uint32_t)0x30000000)
#define | FSMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000)
#define | FSMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000)
#define | FSMC_BWTR1_ADDHLD ((uint32_t)0x000000F0)
#define | FSMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010)
#define | FSMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020)
#define | FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040)
#define | FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080)
#define | FSMC_BWTR1_ADDSET ((uint32_t)0x0000000F)
#define | FSMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001)
#define | FSMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002)
#define | FSMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004)
#define | FSMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008)
#define | FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000)
#define | FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000)
#define | FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000)
#define | FSMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000)
#define | FSMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000)
#define | FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00)
#define | FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100)
#define | FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200)
#define | FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400)
#define | FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800)
#define | FSMC_BWTR1_DATLAT ((uint32_t)0x0F000000)
#define | FSMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000)
#define | FSMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000)
#define | FSMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000)
#define | FSMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000)
#define | FSMC_BWTR2_ACCMOD ((uint32_t)0x30000000)
#define | FSMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000)
#define | FSMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000)
#define | FSMC_BWTR2_ADDHLD ((uint32_t)0x000000F0)
#define | FSMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010)
#define | FSMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020)
#define | FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040)
#define | FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080)
#define | FSMC_BWTR2_ADDSET ((uint32_t)0x0000000F)
#define | FSMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001)
#define | FSMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002)
#define | FSMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004)
#define | FSMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008)
#define | FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000)
#define | FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000)
#define | FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000)
#define | FSMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000)
#define | FSMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000)
#define | FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00)
#define | FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100)
#define | FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200)
#define | FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400)
#define | FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800)
#define | FSMC_BWTR2_DATLAT ((uint32_t)0x0F000000)
#define | FSMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000)
#define | FSMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000)
#define | FSMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000)
#define | FSMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000)
#define | FSMC_BWTR3_ACCMOD ((uint32_t)0x30000000)
#define | FSMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000)
#define | FSMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000)
#define | FSMC_BWTR3_ADDHLD ((uint32_t)0x000000F0)
#define | FSMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010)
#define | FSMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020)
#define | FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040)
#define | FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080)
#define | FSMC_BWTR3_ADDSET ((uint32_t)0x0000000F)
#define | FSMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001)
#define | FSMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002)
#define | FSMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004)
#define | FSMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008)
#define | FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000)
#define | FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000)
#define | FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000)
#define | FSMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000)
#define | FSMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000)
#define | FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00)
#define | FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100)
#define | FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200)
#define | FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400)
#define | FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800)
#define | FSMC_BWTR3_DATLAT ((uint32_t)0x0F000000)
#define | FSMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000)
#define | FSMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000)
#define | FSMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000)
#define | FSMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000)
#define | FSMC_BWTR4_ACCMOD ((uint32_t)0x30000000)
#define | FSMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000)
#define | FSMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000)
#define | FSMC_BWTR4_ADDHLD ((uint32_t)0x000000F0)
#define | FSMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010)
#define | FSMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020)
#define | FSMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040)
#define | FSMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080)
#define | FSMC_BWTR4_ADDSET ((uint32_t)0x0000000F)
#define | FSMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001)
#define | FSMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002)
#define | FSMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004)
#define | FSMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008)
#define | FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000)
#define | FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000)
#define | FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000)
#define | FSMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000)
#define | FSMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000)
#define | FSMC_BWTR4_DATAST ((uint32_t)0x0000FF00)
#define | FSMC_BWTR4_DATAST_0 ((uint32_t)0x00000100)
#define | FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200)
#define | FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400)
#define | FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800)
#define | FSMC_BWTR4_DATLAT ((uint32_t)0x0F000000)
#define | FSMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000)
#define | FSMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000)
#define | FSMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000)
#define | FSMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000)
#define | FSMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF)
#define | FSMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF)
#define | FSMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000)
#define | FSMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000)
#define | FSMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000)
#define | FSMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000)
#define | FSMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000)
#define | FSMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000)
#define | FSMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000)
#define | FSMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000)
#define | FSMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000)
#define | FSMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000)
#define | FSMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000)
#define | FSMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000)
#define | FSMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000)
#define | FSMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000)
#define | FSMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000)
#define | FSMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000)
#define | FSMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000)
#define | FSMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000)
#define | FSMC_PATT2_ATTSET2 ((uint32_t)0x000000FF)
#define | FSMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001)
#define | FSMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002)
#define | FSMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004)
#define | FSMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008)
#define | FSMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010)
#define | FSMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020)
#define | FSMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040)
#define | FSMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080)
#define | FSMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00)
#define | FSMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100)
#define | FSMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200)
#define | FSMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400)
#define | FSMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800)
#define | FSMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000)
#define | FSMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000)
#define | FSMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000)
#define | FSMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000)
#define | FSMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000)
#define | FSMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000)
#define | FSMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000)
#define | FSMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000)
#define | FSMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000)
#define | FSMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000)
#define | FSMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000)
#define | FSMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000)
#define | FSMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000)
#define | FSMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000)
#define | FSMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000)
#define | FSMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000)
#define | FSMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000)
#define | FSMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000)
#define | FSMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000)
#define | FSMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000)
#define | FSMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000)
#define | FSMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000)
#define | FSMC_PATT3_ATTSET3 ((uint32_t)0x000000FF)
#define | FSMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001)
#define | FSMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002)
#define | FSMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004)
#define | FSMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008)
#define | FSMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010)
#define | FSMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020)
#define | FSMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040)
#define | FSMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080)
#define | FSMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00)
#define | FSMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100)
#define | FSMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200)
#define | FSMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400)
#define | FSMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800)
#define | FSMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000)
#define | FSMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000)
#define | FSMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000)
#define | FSMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000)
#define | FSMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000)
#define | FSMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000)
#define | FSMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000)
#define | FSMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000)
#define | FSMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000)
#define | FSMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000)
#define | FSMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000)
#define | FSMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000)
#define | FSMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000)
#define | FSMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000)
#define | FSMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000)
#define | FSMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000)
#define | FSMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000)
#define | FSMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000)
#define | FSMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000)
#define | FSMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000)
#define | FSMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000)
#define | FSMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000)
#define | FSMC_PATT4_ATTSET4 ((uint32_t)0x000000FF)
#define | FSMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001)
#define | FSMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002)
#define | FSMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004)
#define | FSMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008)
#define | FSMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010)
#define | FSMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020)
#define | FSMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040)
#define | FSMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080)
#define | FSMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00)
#define | FSMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100)
#define | FSMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200)
#define | FSMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400)
#define | FSMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800)
#define | FSMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000)
#define | FSMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000)
#define | FSMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000)
#define | FSMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000)
#define | FSMC_PCR2_ECCEN ((uint32_t)0x00000040)
#define | FSMC_PCR2_ECCPS ((uint32_t)0x000E0000)
#define | FSMC_PCR2_ECCPS_0 ((uint32_t)0x00020000)
#define | FSMC_PCR2_ECCPS_1 ((uint32_t)0x00040000)
#define | FSMC_PCR2_ECCPS_2 ((uint32_t)0x00080000)
#define | FSMC_PCR2_PBKEN ((uint32_t)0x00000004)
#define | FSMC_PCR2_PTYP ((uint32_t)0x00000008)
#define | FSMC_PCR2_PWAITEN ((uint32_t)0x00000002)
#define | FSMC_PCR2_PWID ((uint32_t)0x00000030)
#define | FSMC_PCR2_PWID_0 ((uint32_t)0x00000010)
#define | FSMC_PCR2_PWID_1 ((uint32_t)0x00000020)
#define | FSMC_PCR2_TAR ((uint32_t)0x0001E000)
#define | FSMC_PCR2_TAR_0 ((uint32_t)0x00002000)
#define | FSMC_PCR2_TAR_1 ((uint32_t)0x00004000)
#define | FSMC_PCR2_TAR_2 ((uint32_t)0x00008000)
#define | FSMC_PCR2_TAR_3 ((uint32_t)0x00010000)
#define | FSMC_PCR2_TCLR ((uint32_t)0x00001E00)
#define | FSMC_PCR2_TCLR_0 ((uint32_t)0x00000200)
#define | FSMC_PCR2_TCLR_1 ((uint32_t)0x00000400)
#define | FSMC_PCR2_TCLR_2 ((uint32_t)0x00000800)
#define | FSMC_PCR2_TCLR_3 ((uint32_t)0x00001000)
#define | FSMC_PCR3_ECCEN ((uint32_t)0x00000040)
#define | FSMC_PCR3_ECCPS ((uint32_t)0x000E0000)
#define | FSMC_PCR3_ECCPS_0 ((uint32_t)0x00020000)
#define | FSMC_PCR3_ECCPS_1 ((uint32_t)0x00040000)
#define | FSMC_PCR3_ECCPS_2 ((uint32_t)0x00080000)
#define | FSMC_PCR3_PBKEN ((uint32_t)0x00000004)
#define | FSMC_PCR3_PTYP ((uint32_t)0x00000008)
#define | FSMC_PCR3_PWAITEN ((uint32_t)0x00000002)
#define | FSMC_PCR3_PWID ((uint32_t)0x00000030)
#define | FSMC_PCR3_PWID_0 ((uint32_t)0x00000010)
#define | FSMC_PCR3_PWID_1 ((uint32_t)0x00000020)
#define | FSMC_PCR3_TAR ((uint32_t)0x0001E000)
#define | FSMC_PCR3_TAR_0 ((uint32_t)0x00002000)
#define | FSMC_PCR3_TAR_1 ((uint32_t)0x00004000)
#define | FSMC_PCR3_TAR_2 ((uint32_t)0x00008000)
#define | FSMC_PCR3_TAR_3 ((uint32_t)0x00010000)
#define | FSMC_PCR3_TCLR ((uint32_t)0x00001E00)
#define | FSMC_PCR3_TCLR_0 ((uint32_t)0x00000200)
#define | FSMC_PCR3_TCLR_1 ((uint32_t)0x00000400)
#define | FSMC_PCR3_TCLR_2 ((uint32_t)0x00000800)
#define | FSMC_PCR3_TCLR_3 ((uint32_t)0x00001000)
#define | FSMC_PCR4_ECCEN ((uint32_t)0x00000040)
#define | FSMC_PCR4_ECCPS ((uint32_t)0x000E0000)
#define | FSMC_PCR4_ECCPS_0 ((uint32_t)0x00020000)
#define | FSMC_PCR4_ECCPS_1 ((uint32_t)0x00040000)
#define | FSMC_PCR4_ECCPS_2 ((uint32_t)0x00080000)
#define | FSMC_PCR4_PBKEN ((uint32_t)0x00000004)
#define | FSMC_PCR4_PTYP ((uint32_t)0x00000008)
#define | FSMC_PCR4_PWAITEN ((uint32_t)0x00000002)
#define | FSMC_PCR4_PWID ((uint32_t)0x00000030)
#define | FSMC_PCR4_PWID_0 ((uint32_t)0x00000010)
#define | FSMC_PCR4_PWID_1 ((uint32_t)0x00000020)
#define | FSMC_PCR4_TAR ((uint32_t)0x0001E000)
#define | FSMC_PCR4_TAR_0 ((uint32_t)0x00002000)
#define | FSMC_PCR4_TAR_1 ((uint32_t)0x00004000)
#define | FSMC_PCR4_TAR_2 ((uint32_t)0x00008000)
#define | FSMC_PCR4_TAR_3 ((uint32_t)0x00010000)
#define | FSMC_PCR4_TCLR ((uint32_t)0x00001E00)
#define | FSMC_PCR4_TCLR_0 ((uint32_t)0x00000200)
#define | FSMC_PCR4_TCLR_1 ((uint32_t)0x00000400)
#define | FSMC_PCR4_TCLR_2 ((uint32_t)0x00000800)
#define | FSMC_PCR4_TCLR_3 ((uint32_t)0x00001000)
#define | FSMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000)
#define | FSMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000)
#define | FSMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000)
#define | FSMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000)
#define | FSMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000)
#define | FSMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000)
#define | FSMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000)
#define | FSMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000)
#define | FSMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000)
#define | FSMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000)
#define | FSMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000)
#define | FSMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000)
#define | FSMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000)
#define | FSMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000)
#define | FSMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000)
#define | FSMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000)
#define | FSMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000)
#define | FSMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000)
#define | FSMC_PIO4_IOSET4 ((uint32_t)0x000000FF)
#define | FSMC_PIO4_IOSET4_0 ((uint32_t)0x00000001)
#define | FSMC_PIO4_IOSET4_1 ((uint32_t)0x00000002)
#define | FSMC_PIO4_IOSET4_2 ((uint32_t)0x00000004)
#define | FSMC_PIO4_IOSET4_3 ((uint32_t)0x00000008)
#define | FSMC_PIO4_IOSET4_4 ((uint32_t)0x00000010)
#define | FSMC_PIO4_IOSET4_5 ((uint32_t)0x00000020)
#define | FSMC_PIO4_IOSET4_6 ((uint32_t)0x00000040)
#define | FSMC_PIO4_IOSET4_7 ((uint32_t)0x00000080)
#define | FSMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00)
#define | FSMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100)
#define | FSMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200)
#define | FSMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400)
#define | FSMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800)
#define | FSMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000)
#define | FSMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000)
#define | FSMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000)
#define | FSMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000)
#define | FSMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000)
#define | FSMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000)
#define | FSMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000)
#define | FSMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000)
#define | FSMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000)
#define | FSMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000)
#define | FSMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000)
#define | FSMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000)
#define | FSMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000)
#define | FSMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000)
#define | FSMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000)
#define | FSMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000)
#define | FSMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000)
#define | FSMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000)
#define | FSMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000)
#define | FSMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000)
#define | FSMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000)
#define | FSMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000)
#define | FSMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF)
#define | FSMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001)
#define | FSMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002)
#define | FSMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004)
#define | FSMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008)
#define | FSMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010)
#define | FSMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020)
#define | FSMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040)
#define | FSMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080)
#define | FSMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00)
#define | FSMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100)
#define | FSMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200)
#define | FSMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400)
#define | FSMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800)
#define | FSMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000)
#define | FSMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000)
#define | FSMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000)
#define | FSMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000)
#define | FSMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000)
#define | FSMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000)
#define | FSMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000)
#define | FSMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000)
#define | FSMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000)
#define | FSMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000)
#define | FSMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000)
#define | FSMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000)
#define | FSMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000)
#define | FSMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000)
#define | FSMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000)
#define | FSMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000)
#define | FSMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000)
#define | FSMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000)
#define | FSMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000)
#define | FSMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000)
#define | FSMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000)
#define | FSMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000)
#define | FSMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF)
#define | FSMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001)
#define | FSMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002)
#define | FSMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004)
#define | FSMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008)
#define | FSMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010)
#define | FSMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020)
#define | FSMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040)
#define | FSMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080)
#define | FSMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00)
#define | FSMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100)
#define | FSMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200)
#define | FSMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400)
#define | FSMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800)
#define | FSMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000)
#define | FSMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000)
#define | FSMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000)
#define | FSMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000)
#define | FSMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000)
#define | FSMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000)
#define | FSMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000)
#define | FSMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000)
#define | FSMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000)
#define | FSMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000)
#define | FSMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000)
#define | FSMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000)
#define | FSMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000)
#define | FSMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000)
#define | FSMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000)
#define | FSMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000)
#define | FSMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000)
#define | FSMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000)
#define | FSMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000)
#define | FSMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000)
#define | FSMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000)
#define | FSMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000)
#define | FSMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF)
#define | FSMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001)
#define | FSMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002)
#define | FSMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004)
#define | FSMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008)
#define | FSMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010)
#define | FSMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020)
#define | FSMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040)
#define | FSMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080)
#define | FSMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00)
#define | FSMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100)
#define | FSMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200)
#define | FSMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400)
#define | FSMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800)
#define | FSMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000)
#define | FSMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000)
#define | FSMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000)
#define | FSMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000)
#define | FSMC_R_BASE ((uint32_t)0xA0000000)
#define | FSMC_SR2_FEMPT ((uint8_t)0x40)
#define | FSMC_SR2_IFEN ((uint8_t)0x20)
#define | FSMC_SR2_IFS ((uint8_t)0x04)
#define | FSMC_SR2_ILEN ((uint8_t)0x10)
#define | FSMC_SR2_ILS ((uint8_t)0x02)
#define | FSMC_SR2_IREN ((uint8_t)0x08)
#define | FSMC_SR2_IRS ((uint8_t)0x01)
#define | FSMC_SR3_FEMPT ((uint8_t)0x40)
#define | FSMC_SR3_IFEN ((uint8_t)0x20)
#define | FSMC_SR3_IFS ((uint8_t)0x04)
#define | FSMC_SR3_ILEN ((uint8_t)0x10)
#define | FSMC_SR3_ILS ((uint8_t)0x02)
#define | FSMC_SR3_IREN ((uint8_t)0x08)
#define | FSMC_SR3_IRS ((uint8_t)0x01)
#define | FSMC_SR4_FEMPT ((uint8_t)0x40)
#define | FSMC_SR4_IFEN ((uint8_t)0x20)
#define | FSMC_SR4_IFS ((uint8_t)0x04)
#define | FSMC_SR4_ILEN ((uint8_t)0x10)
#define | FSMC_SR4_ILS ((uint8_t)0x02)
#define | FSMC_SR4_IREN ((uint8_t)0x08)
#define | FSMC_SR4_IRS ((uint8_t)0x01)
#define | GPIO_BRR_BR0 ((uint16_t)0x0001)
#define | GPIO_BRR_BR1 ((uint16_t)0x0002)
#define | GPIO_BRR_BR10 ((uint16_t)0x0400)
#define | GPIO_BRR_BR11 ((uint16_t)0x0800)
#define | GPIO_BRR_BR12 ((uint16_t)0x1000)
#define | GPIO_BRR_BR13 ((uint16_t)0x2000)
#define | GPIO_BRR_BR14 ((uint16_t)0x4000)
#define | GPIO_BRR_BR15 ((uint16_t)0x8000)
#define | GPIO_BRR_BR2 ((uint16_t)0x0004)
#define | GPIO_BRR_BR3 ((uint16_t)0x0008)
#define | GPIO_BRR_BR4 ((uint16_t)0x0010)
#define | GPIO_BRR_BR5 ((uint16_t)0x0020)
#define | GPIO_BRR_BR6 ((uint16_t)0x0040)
#define | GPIO_BRR_BR7 ((uint16_t)0x0080)
#define | GPIO_BRR_BR8 ((uint16_t)0x0100)
#define | GPIO_BRR_BR9 ((uint16_t)0x0200)
#define | GPIO_BSRR_BR0 ((uint32_t)0x00010000)
#define | GPIO_BSRR_BR1 ((uint32_t)0x00020000)
#define | GPIO_BSRR_BR10 ((uint32_t)0x04000000)
#define | GPIO_BSRR_BR11 ((uint32_t)0x08000000)
#define | GPIO_BSRR_BR12 ((uint32_t)0x10000000)
#define | GPIO_BSRR_BR13 ((uint32_t)0x20000000)
#define | GPIO_BSRR_BR14 ((uint32_t)0x40000000)
#define | GPIO_BSRR_BR15 ((uint32_t)0x80000000)
#define | GPIO_BSRR_BR2 ((uint32_t)0x00040000)
#define | GPIO_BSRR_BR3 ((uint32_t)0x00080000)
#define | GPIO_BSRR_BR4 ((uint32_t)0x00100000)
#define | GPIO_BSRR_BR5 ((uint32_t)0x00200000)
#define | GPIO_BSRR_BR6 ((uint32_t)0x00400000)
#define | GPIO_BSRR_BR7 ((uint32_t)0x00800000)
#define | GPIO_BSRR_BR8 ((uint32_t)0x01000000)
#define | GPIO_BSRR_BR9 ((uint32_t)0x02000000)
#define | GPIO_BSRR_BS0 ((uint32_t)0x00000001)
#define | GPIO_BSRR_BS1 ((uint32_t)0x00000002)
#define | GPIO_BSRR_BS10 ((uint32_t)0x00000400)
#define | GPIO_BSRR_BS11 ((uint32_t)0x00000800)
#define | GPIO_BSRR_BS12 ((uint32_t)0x00001000)
#define | GPIO_BSRR_BS13 ((uint32_t)0x00002000)
#define | GPIO_BSRR_BS14 ((uint32_t)0x00004000)
#define | GPIO_BSRR_BS15 ((uint32_t)0x00008000)
#define | GPIO_BSRR_BS2 ((uint32_t)0x00000004)
#define | GPIO_BSRR_BS3 ((uint32_t)0x00000008)
#define | GPIO_BSRR_BS4 ((uint32_t)0x00000010)
#define | GPIO_BSRR_BS5 ((uint32_t)0x00000020)
#define | GPIO_BSRR_BS6 ((uint32_t)0x00000040)
#define | GPIO_BSRR_BS7 ((uint32_t)0x00000080)
#define | GPIO_BSRR_BS8 ((uint32_t)0x00000100)
#define | GPIO_BSRR_BS9 ((uint32_t)0x00000200)
#define | GPIO_CRH_CNF ((uint32_t)0xCCCCCCCC)
#define | GPIO_CRH_CNF10 ((uint32_t)0x00000C00)
#define | GPIO_CRH_CNF10_0 ((uint32_t)0x00000400)
#define | GPIO_CRH_CNF10_1 ((uint32_t)0x00000800)
#define | GPIO_CRH_CNF11 ((uint32_t)0x0000C000)
#define | GPIO_CRH_CNF11_0 ((uint32_t)0x00004000)
#define | GPIO_CRH_CNF11_1 ((uint32_t)0x00008000)
#define | GPIO_CRH_CNF12 ((uint32_t)0x000C0000)
#define | GPIO_CRH_CNF12_0 ((uint32_t)0x00040000)
#define | GPIO_CRH_CNF12_1 ((uint32_t)0x00080000)
#define | GPIO_CRH_CNF13 ((uint32_t)0x00C00000)
#define | GPIO_CRH_CNF13_0 ((uint32_t)0x00400000)
#define | GPIO_CRH_CNF13_1 ((uint32_t)0x00800000)
#define | GPIO_CRH_CNF14 ((uint32_t)0x0C000000)
#define | GPIO_CRH_CNF14_0 ((uint32_t)0x04000000)
#define | GPIO_CRH_CNF14_1 ((uint32_t)0x08000000)
#define | GPIO_CRH_CNF15 ((uint32_t)0xC0000000)
#define | GPIO_CRH_CNF15_0 ((uint32_t)0x40000000)
#define | GPIO_CRH_CNF15_1 ((uint32_t)0x80000000)
#define | GPIO_CRH_CNF8 ((uint32_t)0x0000000C)
#define | GPIO_CRH_CNF8_0 ((uint32_t)0x00000004)
#define | GPIO_CRH_CNF8_1 ((uint32_t)0x00000008)
#define | GPIO_CRH_CNF9 ((uint32_t)0x000000C0)
#define | GPIO_CRH_CNF9_0 ((uint32_t)0x00000040)
#define | GPIO_CRH_CNF9_1 ((uint32_t)0x00000080)
#define | GPIO_CRH_MODE ((uint32_t)0x33333333)
#define | GPIO_CRH_MODE10 ((uint32_t)0x00000300)
#define | GPIO_CRH_MODE10_0 ((uint32_t)0x00000100)
#define | GPIO_CRH_MODE10_1 ((uint32_t)0x00000200)
#define | GPIO_CRH_MODE11 ((uint32_t)0x00003000)
#define | GPIO_CRH_MODE11_0 ((uint32_t)0x00001000)
#define | GPIO_CRH_MODE11_1 ((uint32_t)0x00002000)
#define | GPIO_CRH_MODE12 ((uint32_t)0x00030000)
#define | GPIO_CRH_MODE12_0 ((uint32_t)0x00010000)
#define | GPIO_CRH_MODE12_1 ((uint32_t)0x00020000)
#define | GPIO_CRH_MODE13 ((uint32_t)0x00300000)
#define | GPIO_CRH_MODE13_0 ((uint32_t)0x00100000)
#define | GPIO_CRH_MODE13_1 ((uint32_t)0x00200000)
#define | GPIO_CRH_MODE14 ((uint32_t)0x03000000)
#define | GPIO_CRH_MODE14_0 ((uint32_t)0x01000000)
#define | GPIO_CRH_MODE14_1 ((uint32_t)0x02000000)
#define | GPIO_CRH_MODE15 ((uint32_t)0x30000000)
#define | GPIO_CRH_MODE15_0 ((uint32_t)0x10000000)
#define | GPIO_CRH_MODE15_1 ((uint32_t)0x20000000)
#define | GPIO_CRH_MODE8 ((uint32_t)0x00000003)
#define | GPIO_CRH_MODE8_0 ((uint32_t)0x00000001)
#define | GPIO_CRH_MODE8_1 ((uint32_t)0x00000002)
#define | GPIO_CRH_MODE9 ((uint32_t)0x00000030)
#define | GPIO_CRH_MODE9_0 ((uint32_t)0x00000010)
#define | GPIO_CRH_MODE9_1 ((uint32_t)0x00000020)
#define | GPIO_CRL_CNF ((uint32_t)0xCCCCCCCC)
#define | GPIO_CRL_CNF0 ((uint32_t)0x0000000C)
#define | GPIO_CRL_CNF0_0 ((uint32_t)0x00000004)
#define | GPIO_CRL_CNF0_1 ((uint32_t)0x00000008)
#define | GPIO_CRL_CNF1 ((uint32_t)0x000000C0)
#define | GPIO_CRL_CNF1_0 ((uint32_t)0x00000040)
#define | GPIO_CRL_CNF1_1 ((uint32_t)0x00000080)
#define | GPIO_CRL_CNF2 ((uint32_t)0x00000C00)
#define | GPIO_CRL_CNF2_0 ((uint32_t)0x00000400)
#define | GPIO_CRL_CNF2_1 ((uint32_t)0x00000800)
#define | GPIO_CRL_CNF3 ((uint32_t)0x0000C000)
#define | GPIO_CRL_CNF3_0 ((uint32_t)0x00004000)
#define | GPIO_CRL_CNF3_1 ((uint32_t)0x00008000)
#define | GPIO_CRL_CNF4 ((uint32_t)0x000C0000)
#define | GPIO_CRL_CNF4_0 ((uint32_t)0x00040000)
#define | GPIO_CRL_CNF4_1 ((uint32_t)0x00080000)
#define | GPIO_CRL_CNF5 ((uint32_t)0x00C00000)
#define | GPIO_CRL_CNF5_0 ((uint32_t)0x00400000)
#define | GPIO_CRL_CNF5_1 ((uint32_t)0x00800000)
#define | GPIO_CRL_CNF6 ((uint32_t)0x0C000000)
#define | GPIO_CRL_CNF6_0 ((uint32_t)0x04000000)
#define | GPIO_CRL_CNF6_1 ((uint32_t)0x08000000)
#define | GPIO_CRL_CNF7 ((uint32_t)0xC0000000)
#define | GPIO_CRL_CNF7_0 ((uint32_t)0x40000000)
#define | GPIO_CRL_CNF7_1 ((uint32_t)0x80000000)
#define | GPIO_CRL_MODE ((uint32_t)0x33333333)
#define | GPIO_CRL_MODE0 ((uint32_t)0x00000003)
#define | GPIO_CRL_MODE0_0 ((uint32_t)0x00000001)
#define | GPIO_CRL_MODE0_1 ((uint32_t)0x00000002)
#define | GPIO_CRL_MODE1 ((uint32_t)0x00000030)
#define | GPIO_CRL_MODE1_0 ((uint32_t)0x00000010)
#define | GPIO_CRL_MODE1_1 ((uint32_t)0x00000020)
#define | GPIO_CRL_MODE2 ((uint32_t)0x00000300)
#define | GPIO_CRL_MODE2_0 ((uint32_t)0x00000100)
#define | GPIO_CRL_MODE2_1 ((uint32_t)0x00000200)
#define | GPIO_CRL_MODE3 ((uint32_t)0x00003000)
#define | GPIO_CRL_MODE3_0 ((uint32_t)0x00001000)
#define | GPIO_CRL_MODE3_1 ((uint32_t)0x00002000)
#define | GPIO_CRL_MODE4 ((uint32_t)0x00030000)
#define | GPIO_CRL_MODE4_0 ((uint32_t)0x00010000)
#define | GPIO_CRL_MODE4_1 ((uint32_t)0x00020000)
#define | GPIO_CRL_MODE5 ((uint32_t)0x00300000)
#define | GPIO_CRL_MODE5_0 ((uint32_t)0x00100000)
#define | GPIO_CRL_MODE5_1 ((uint32_t)0x00200000)
#define | GPIO_CRL_MODE6 ((uint32_t)0x03000000)
#define | GPIO_CRL_MODE6_0 ((uint32_t)0x01000000)
#define | GPIO_CRL_MODE6_1 ((uint32_t)0x02000000)
#define | GPIO_CRL_MODE7 ((uint32_t)0x30000000)
#define | GPIO_CRL_MODE7_0 ((uint32_t)0x10000000)
#define | GPIO_CRL_MODE7_1 ((uint32_t)0x20000000)
#define | GPIO_IDR_IDR0 ((uint16_t)0x0001)
#define | GPIO_IDR_IDR1 ((uint16_t)0x0002)
#define | GPIO_IDR_IDR10 ((uint16_t)0x0400)
#define | GPIO_IDR_IDR11 ((uint16_t)0x0800)
#define | GPIO_IDR_IDR12 ((uint16_t)0x1000)
#define | GPIO_IDR_IDR13 ((uint16_t)0x2000)
#define | GPIO_IDR_IDR14 ((uint16_t)0x4000)
#define | GPIO_IDR_IDR15 ((uint16_t)0x8000)
#define | GPIO_IDR_IDR2 ((uint16_t)0x0004)
#define | GPIO_IDR_IDR3 ((uint16_t)0x0008)
#define | GPIO_IDR_IDR4 ((uint16_t)0x0010)
#define | GPIO_IDR_IDR5 ((uint16_t)0x0020)
#define | GPIO_IDR_IDR6 ((uint16_t)0x0040)
#define | GPIO_IDR_IDR7 ((uint16_t)0x0080)
#define | GPIO_IDR_IDR8 ((uint16_t)0x0100)
#define | GPIO_IDR_IDR9 ((uint16_t)0x0200)
#define | GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
#define | GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
#define | GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
#define | GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
#define | GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
#define | GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
#define | GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
#define | GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
#define | GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
#define | GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
#define | GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
#define | GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
#define | GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
#define | GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
#define | GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
#define | GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
#define | GPIO_LCKR_LCKK ((uint32_t)0x00010000)
#define | GPIO_ODR_ODR0 ((uint16_t)0x0001)
#define | GPIO_ODR_ODR1 ((uint16_t)0x0002)
#define | GPIO_ODR_ODR10 ((uint16_t)0x0400)
#define | GPIO_ODR_ODR11 ((uint16_t)0x0800)
#define | GPIO_ODR_ODR12 ((uint16_t)0x1000)
#define | GPIO_ODR_ODR13 ((uint16_t)0x2000)
#define | GPIO_ODR_ODR14 ((uint16_t)0x4000)
#define | GPIO_ODR_ODR15 ((uint16_t)0x8000)
#define | GPIO_ODR_ODR2 ((uint16_t)0x0004)
#define | GPIO_ODR_ODR3 ((uint16_t)0x0008)
#define | GPIO_ODR_ODR4 ((uint16_t)0x0010)
#define | GPIO_ODR_ODR5 ((uint16_t)0x0020)
#define | GPIO_ODR_ODR6 ((uint16_t)0x0040)
#define | GPIO_ODR_ODR7 ((uint16_t)0x0080)
#define | GPIO_ODR_ODR8 ((uint16_t)0x0100)
#define | GPIO_ODR_ODR9 ((uint16_t)0x0200)
#define | GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
#define | GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
#define | GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
#define | GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
#define | GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
#define | GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
#define | GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
#define | GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
#define | GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
#define | GPIOE_BASE (APB2PERIPH_BASE + 0x1800)
#define | GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
#define | GPIOF_BASE (APB2PERIPH_BASE + 0x1C00)
#define | GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
#define | GPIOG_BASE (APB2PERIPH_BASE + 0x2000)
#define | HSE_STARTUP_TIMEOUT ((uint16_t)0x0500)
In the following line adjust the External High Speed oscillator (HSE) Startup Timeout value.
#define | HSE_VALUE ((uint32_t)8000000)
Comment the line below if you will not use the peripherals drivers.
#define | HSE_Value HSE_VALUE
#define | HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT
#define | HSI_VALUE ((uint32_t)8000000)
#define | HSI_Value HSI_VALUE
#define | I2C1 ((I2C_TypeDef *) I2C1_BASE)
#define | I2C1_BASE (APB1PERIPH_BASE + 0x5400)
#define | I2C2 ((I2C_TypeDef *) I2C2_BASE)
#define | I2C2_BASE (APB1PERIPH_BASE + 0x5800)
#define | I2C_CCR_CCR ((uint16_t)0x0FFF)
#define | I2C_CCR_DUTY ((uint16_t)0x4000)
#define | I2C_CCR_FS ((uint16_t)0x8000)
#define | I2C_CR1_ACK ((uint16_t)0x0400)
#define | I2C_CR1_ALERT ((uint16_t)0x2000)
#define | I2C_CR1_ENARP ((uint16_t)0x0010)
#define | I2C_CR1_ENGC ((uint16_t)0x0040)
#define | I2C_CR1_ENPEC ((uint16_t)0x0020)
#define | I2C_CR1_NOSTRETCH ((uint16_t)0x0080)
#define | I2C_CR1_PE ((uint16_t)0x0001)
#define | I2C_CR1_PEC ((uint16_t)0x1000)
#define | I2C_CR1_POS ((uint16_t)0x0800)
#define | I2C_CR1_SMBTYPE ((uint16_t)0x0008)
#define | I2C_CR1_SMBUS ((uint16_t)0x0002)
#define | I2C_CR1_START ((uint16_t)0x0100)
#define | I2C_CR1_STOP ((uint16_t)0x0200)
#define | I2C_CR1_SWRST ((uint16_t)0x8000)
#define | I2C_CR2_DMAEN ((uint16_t)0x0800)
#define | I2C_CR2_FREQ ((uint16_t)0x003F)
#define | I2C_CR2_FREQ_0 ((uint16_t)0x0001)
#define | I2C_CR2_FREQ_1 ((uint16_t)0x0002)
#define | I2C_CR2_FREQ_2 ((uint16_t)0x0004)
#define | I2C_CR2_FREQ_3 ((uint16_t)0x0008)
#define | I2C_CR2_FREQ_4 ((uint16_t)0x0010)
#define | I2C_CR2_FREQ_5 ((uint16_t)0x0020)
#define | I2C_CR2_ITBUFEN ((uint16_t)0x0400)
#define | I2C_CR2_ITERREN ((uint16_t)0x0100)
#define | I2C_CR2_ITEVTEN ((uint16_t)0x0200)
#define | I2C_CR2_LAST ((uint16_t)0x1000)
#define | I2C_DR_DR ((uint8_t)0xFF)
#define | I2C_OAR1_ADD0 ((uint16_t)0x0001)
#define | I2C_OAR1_ADD1 ((uint16_t)0x0002)
#define | I2C_OAR1_ADD1_7 ((uint16_t)0x00FE)
#define | I2C_OAR1_ADD2 ((uint16_t)0x0004)
#define | I2C_OAR1_ADD3 ((uint16_t)0x0008)
#define | I2C_OAR1_ADD4 ((uint16_t)0x0010)
#define | I2C_OAR1_ADD5 ((uint16_t)0x0020)
#define | I2C_OAR1_ADD6 ((uint16_t)0x0040)
#define | I2C_OAR1_ADD7 ((uint16_t)0x0080)
#define | I2C_OAR1_ADD8 ((uint16_t)0x0100)
#define | I2C_OAR1_ADD8_9 ((uint16_t)0x0300)
#define | I2C_OAR1_ADD9 ((uint16_t)0x0200)
#define | I2C_OAR1_ADDMODE ((uint16_t)0x8000)
#define | I2C_OAR2_ADD2 ((uint8_t)0xFE)
#define | I2C_OAR2_ENDUAL ((uint8_t)0x01)
#define | I2C_SR1_ADD10 ((uint16_t)0x0008)
#define | I2C_SR1_ADDR ((uint16_t)0x0002)
#define | I2C_SR1_AF ((uint16_t)0x0400)
#define | I2C_SR1_ARLO ((uint16_t)0x0200)
#define | I2C_SR1_BERR ((uint16_t)0x0100)
#define | I2C_SR1_BTF ((uint16_t)0x0004)
#define | I2C_SR1_OVR ((uint16_t)0x0800)
#define | I2C_SR1_PECERR ((uint16_t)0x1000)
#define | I2C_SR1_RXNE ((uint16_t)0x0040)
#define | I2C_SR1_SB ((uint16_t)0x0001)
#define | I2C_SR1_SMBALERT ((uint16_t)0x8000)
#define | I2C_SR1_STOPF ((uint16_t)0x0010)
#define | I2C_SR1_TIMEOUT ((uint16_t)0x4000)
#define | I2C_SR1_TXE ((uint16_t)0x0080)
#define | I2C_SR2_BUSY ((uint16_t)0x0002)
#define | I2C_SR2_DUALF ((uint16_t)0x0080)
#define | I2C_SR2_GENCALL ((uint16_t)0x0010)
#define | I2C_SR2_MSL ((uint16_t)0x0001)
#define | I2C_SR2_PEC ((uint16_t)0xFF00)
#define | I2C_SR2_SMBDEFAULT ((uint16_t)0x0020)
#define | I2C_SR2_SMBHOST ((uint16_t)0x0040)
#define | I2C_SR2_TRA ((uint16_t)0x0004)
#define | I2C_TRISE_TRISE ((uint8_t)0x3F)
#define | IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
#define | IWDG ((IWDG_TypeDef *) IWDG_BASE)
#define | IWDG_BASE (APB1PERIPH_BASE + 0x3000)
#define | IWDG_KR_KEY ((uint16_t)0xFFFF)
#define | IWDG_PR_PR ((uint8_t)0x07)
#define | IWDG_PR_PR_0 ((uint8_t)0x01)
#define | IWDG_PR_PR_1 ((uint8_t)0x02)
#define | IWDG_PR_PR_2 ((uint8_t)0x04)
#define | IWDG_RLR_RL ((uint16_t)0x0FFF)
#define | IWDG_SR_PVU ((uint8_t)0x01)
#define | IWDG_SR_RVU ((uint8_t)0x02)
#define | MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
#define | NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF)
#define | NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001)
#define | NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002)
#define | NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400)
#define | NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800)
#define | NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000)
#define | NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000)
#define | NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000)
#define | NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000)
#define | NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000)
#define | NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000)
#define | NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000)
#define | NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000)
#define | NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004)
#define | NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000)
#define | NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000)
#define | NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000)
#define | NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000)
#define | NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000)
#define | NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000)
#define | NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000)
#define | NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000)
#define | NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000)
#define | NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000)
#define | NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008)
#define | NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000)
#define | NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000)
#define | NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010)
#define | NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020)
#define | NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040)
#define | NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080)
#define | NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100)
#define | NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200)
#define | NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF)
#define | NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001)
#define | NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002)
#define | NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400)
#define | NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800)
#define | NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000)
#define | NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000)
#define | NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000)
#define | NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000)
#define | NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000)
#define | NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000)
#define | NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000)
#define | NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000)
#define | NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004)
#define | NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000)
#define | NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000)
#define | NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000)
#define | NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000)
#define | NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000)
#define | NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000)
#define | NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000)
#define | NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000)
#define | NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000)
#define | NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000)
#define | NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008)
#define | NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000)
#define | NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000)
#define | NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010)
#define | NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020)
#define | NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040)
#define | NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080)
#define | NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100)
#define | NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200)
#define | NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF)
#define | NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001)
#define | NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002)
#define | NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400)
#define | NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800)
#define | NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000)
#define | NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000)
#define | NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000)
#define | NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000)
#define | NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000)
#define | NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000)
#define | NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000)
#define | NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000)
#define | NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004)
#define | NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000)
#define | NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000)
#define | NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000)
#define | NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000)
#define | NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000)
#define | NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000)
#define | NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000)
#define | NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000)
#define | NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000)
#define | NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000)
#define | NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008)
#define | NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000)
#define | NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000)
#define | NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010)
#define | NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020)
#define | NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040)
#define | NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080)
#define | NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100)
#define | NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200)
#define | NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF)
#define | NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00)
#define | NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000)
#define | NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000)
#define | NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF)
#define | NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00)
#define | NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000)
#define | NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000)
#define | NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000)
#define | NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000)
#define | NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF)
#define | NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00)
#define | NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF)
#define | NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00)
#define | NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000)
#define | NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000)
#define | NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF)
#define | NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00)
#define | NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000)
#define | NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000)
#define | NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF)
#define | NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00)
#define | NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000)
#define | NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000)
#define | NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF)
#define | NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00)
#define | NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000)
#define | NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000)
#define | NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF)
#define | NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00)
#define | NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000)
#define | NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000)
#define | NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF)
#define | NVIC_ISER_SETENA_0 ((uint32_t)0x00000001)
#define | NVIC_ISER_SETENA_1 ((uint32_t)0x00000002)
#define | NVIC_ISER_SETENA_10 ((uint32_t)0x00000400)
#define | NVIC_ISER_SETENA_11 ((uint32_t)0x00000800)
#define | NVIC_ISER_SETENA_12 ((uint32_t)0x00001000)
#define | NVIC_ISER_SETENA_13 ((uint32_t)0x00002000)
#define | NVIC_ISER_SETENA_14 ((uint32_t)0x00004000)
#define | NVIC_ISER_SETENA_15 ((uint32_t)0x00008000)
#define | NVIC_ISER_SETENA_16 ((uint32_t)0x00010000)
#define | NVIC_ISER_SETENA_17 ((uint32_t)0x00020000)
#define | NVIC_ISER_SETENA_18 ((uint32_t)0x00040000)
#define | NVIC_ISER_SETENA_19 ((uint32_t)0x00080000)
#define | NVIC_ISER_SETENA_2 ((uint32_t)0x00000004)
#define | NVIC_ISER_SETENA_20 ((uint32_t)0x00100000)
#define | NVIC_ISER_SETENA_21 ((uint32_t)0x00200000)
#define | NVIC_ISER_SETENA_22 ((uint32_t)0x00400000)
#define | NVIC_ISER_SETENA_23 ((uint32_t)0x00800000)
#define | NVIC_ISER_SETENA_24 ((uint32_t)0x01000000)
#define | NVIC_ISER_SETENA_25 ((uint32_t)0x02000000)
#define | NVIC_ISER_SETENA_26 ((uint32_t)0x04000000)
#define | NVIC_ISER_SETENA_27 ((uint32_t)0x08000000)
#define | NVIC_ISER_SETENA_28 ((uint32_t)0x10000000)
#define | NVIC_ISER_SETENA_29 ((uint32_t)0x20000000)
#define | NVIC_ISER_SETENA_3 ((uint32_t)0x00000008)
#define | NVIC_ISER_SETENA_30 ((uint32_t)0x40000000)
#define | NVIC_ISER_SETENA_31 ((uint32_t)0x80000000)
#define | NVIC_ISER_SETENA_4 ((uint32_t)0x00000010)
#define | NVIC_ISER_SETENA_5 ((uint32_t)0x00000020)
#define | NVIC_ISER_SETENA_6 ((uint32_t)0x00000040)
#define | NVIC_ISER_SETENA_7 ((uint32_t)0x00000080)
#define | NVIC_ISER_SETENA_8 ((uint32_t)0x00000100)
#define | NVIC_ISER_SETENA_9 ((uint32_t)0x00000200)
#define | NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF)
#define | NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001)
#define | NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002)
#define | NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400)
#define | NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800)
#define | NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000)
#define | NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000)
#define | NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000)
#define | NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000)
#define | NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000)
#define | NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000)
#define | NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000)
#define | NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000)
#define | NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004)
#define | NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000)
#define | NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000)
#define | NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000)
#define | NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000)
#define | NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000)
#define | NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000)
#define | NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000)
#define | NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000)
#define | NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000)
#define | NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000)
#define | NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008)
#define | NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000)
#define | NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000)
#define | NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010)
#define | NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020)
#define | NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040)
#define | NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080)
#define | NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100)
#define | NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200)
#define | OB ((OB_TypeDef *) OB_BASE)
#define | OB_BASE ((uint32_t)0x1FFFF800)
#define | PERIPH_BASE ((uint32_t)0x40000000)
#define | PERIPH_BB_BASE ((uint32_t)0x42000000)
#define | PWR ((PWR_TypeDef *) PWR_BASE)
#define | PWR_BASE (APB1PERIPH_BASE + 0x7000)
#define | PWR_CR_CSBF ((uint16_t)0x0008)
#define | PWR_CR_CWUF ((uint16_t)0x0004)
#define | PWR_CR_DBP ((uint16_t)0x0100)
#define | PWR_CR_LPDS ((uint16_t)0x0001)
#define | PWR_CR_PDDS ((uint16_t)0x0002)
#define | PWR_CR_PLS ((uint16_t)0x00E0)
#define | PWR_CR_PLS_0 ((uint16_t)0x0020)
#define | PWR_CR_PLS_1 ((uint16_t)0x0040)
#define | PWR_CR_PLS_2 ((uint16_t)0x0080)
#define | PWR_CR_PLS_2V2 ((uint16_t)0x0000)
#define | PWR_CR_PLS_2V3 ((uint16_t)0x0020)
#define | PWR_CR_PLS_2V4 ((uint16_t)0x0040)
#define | PWR_CR_PLS_2V5 ((uint16_t)0x0060)
#define | PWR_CR_PLS_2V6 ((uint16_t)0x0080)
#define | PWR_CR_PLS_2V7 ((uint16_t)0x00A0)
#define | PWR_CR_PLS_2V8 ((uint16_t)0x00C0)
#define | PWR_CR_PLS_2V9 ((uint16_t)0x00E0)
#define | PWR_CR_PVDE ((uint16_t)0x0010)
#define | PWR_CSR_EWUP ((uint16_t)0x0100)
#define | PWR_CSR_PVDO ((uint16_t)0x0004)
#define | PWR_CSR_SBF ((uint16_t)0x0002)
#define | PWR_CSR_WUF ((uint16_t)0x0001)
#define | RCC ((RCC_TypeDef *) RCC_BASE)
#define | RCC_AHBENR_CRCEN ((uint16_t)0x0040)
#define | RCC_AHBENR_DMA1EN ((uint16_t)0x0001)
#define | RCC_AHBENR_FLITFEN ((uint16_t)0x0010)
#define | RCC_AHBENR_SRAMEN ((uint16_t)0x0004)
#define | RCC_APB1ENR_BKPEN ((uint32_t)0x08000000)
#define | RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000)
#define | RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000)
#define | RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000)
#define | RCC_APB1ENR_PWREN ((uint32_t)0x10000000)
#define | RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000)
#define | RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001)
#define | RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002)
#define | RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004)
#define | RCC_APB1ENR_USART2EN ((uint32_t)0x00020000)
#define | RCC_APB1ENR_USART3EN ((uint32_t)0x00040000)
#define | RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800)
#define | RCC_APB1RSTR_BKPRST ((uint32_t)0x08000000)
#define | RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000)
#define | RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000)
#define | RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000)
#define | RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000)
#define | RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000)
#define | RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001)
#define | RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002)
#define | RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004)
#define | RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000)
#define | RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000)
#define | RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800)
#define | RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200)
#define | RCC_APB2ENR_ADC2EN ((uint32_t)0x00000400)
#define | RCC_APB2ENR_AFIOEN ((uint32_t)0x00000001)
#define | RCC_APB2ENR_IOPAEN ((uint32_t)0x00000004)
#define | RCC_APB2ENR_IOPBEN ((uint32_t)0x00000008)
#define | RCC_APB2ENR_IOPCEN ((uint32_t)0x00000010)
#define | RCC_APB2ENR_IOPDEN ((uint32_t)0x00000020)
#define | RCC_APB2ENR_IOPEEN ((uint32_t)0x00000040)
#define | RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000)
#define | RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800)
#define | RCC_APB2ENR_USART1EN ((uint32_t)0x00004000)
#define | RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200)
#define | RCC_APB2RSTR_ADC2RST ((uint32_t)0x00000400)
#define | RCC_APB2RSTR_AFIORST ((uint32_t)0x00000001)
#define | RCC_APB2RSTR_IOPARST ((uint32_t)0x00000004)
#define | RCC_APB2RSTR_IOPBRST ((uint32_t)0x00000008)
#define | RCC_APB2RSTR_IOPCRST ((uint32_t)0x00000010)
#define | RCC_APB2RSTR_IOPDRST ((uint32_t)0x00000020)
#define | RCC_APB2RSTR_IOPERST ((uint32_t)0x00000040)
#define | RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000)
#define | RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800)
#define | RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000)
#define | RCC_BASE (AHBPERIPH_BASE + 0x1000)
#define | RCC_BDCR_BDRST ((uint32_t)0x00010000)
#define | RCC_BDCR_LSEBYP ((uint32_t)0x00000004)
#define | RCC_BDCR_LSEON ((uint32_t)0x00000001)
#define | RCC_BDCR_LSERDY ((uint32_t)0x00000002)
#define | RCC_BDCR_RTCEN ((uint32_t)0x00008000)
#define | RCC_BDCR_RTCSEL ((uint32_t)0x00000300)
#define | RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100)
#define | RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200)
#define | RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300)
#define | RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100)
#define | RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200)
#define | RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000)
#define | RCC_CFGR_ADCPRE ((uint32_t)0x0000C000)
#define | RCC_CFGR_ADCPRE_0 ((uint32_t)0x00004000)
#define | RCC_CFGR_ADCPRE_1 ((uint32_t)0x00008000)
#define | RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000)
#define | RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000)
#define | RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000)
#define | RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000)
#define | RCC_CFGR_HPRE ((uint32_t)0x000000F0)
#define | RCC_CFGR_HPRE_0 ((uint32_t)0x00000010)
#define | RCC_CFGR_HPRE_1 ((uint32_t)0x00000020)
#define | RCC_CFGR_HPRE_2 ((uint32_t)0x00000040)
#define | RCC_CFGR_HPRE_3 ((uint32_t)0x00000080)
#define | RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000)
#define | RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0)
#define | RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0)
#define | RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080)
#define | RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0)
#define | RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090)
#define | RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0)
#define | RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0)
#define | RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0)
#define | RCC_CFGR_MCO ((uint32_t)0x07000000)
#define | RCC_CFGR_MCO_0 ((uint32_t)0x01000000)
#define | RCC_CFGR_MCO_1 ((uint32_t)0x02000000)
#define | RCC_CFGR_MCO_2 ((uint32_t)0x04000000)
#define | RCC_CFGR_MCO_HSE ((uint32_t)0x06000000)
#define | RCC_CFGR_MCO_HSI ((uint32_t)0x05000000)
#define | RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000)
#define | RCC_CFGR_MCO_PLL ((uint32_t)0x07000000)
#define | RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000)
#define | RCC_CFGR_PLLMULL ((uint32_t)0x003C0000)
#define | RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000)
#define | RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000)
#define | RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000)
#define | RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000)
#define | RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000)
#define | RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000)
#define | RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000)
#define | RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000)
#define | RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000)
#define | RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000)
#define | RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000)
#define | RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000)
#define | RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000)
#define | RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000)
#define | RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000)
#define | RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000)
#define | RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000)
#define | RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000)
#define | RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000)
#define | RCC_CFGR_PLLSRC ((uint32_t)0x00010000)
#define | RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000)
#define | RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000)
#define | RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000)
#define | RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000)
#define | RCC_CFGR_PLLXTPRE_HSE_Div2 ((uint32_t)0x00020000)
#define | RCC_CFGR_PPRE1 ((uint32_t)0x00000700)
#define | RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100)
#define | RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200)
#define | RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400)
#define | RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000)
#define | RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700)
#define | RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400)
#define | RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500)
#define | RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600)
#define | RCC_CFGR_PPRE2 ((uint32_t)0x00003800)
#define | RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800)
#define | RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000)
#define | RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000)
#define | RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000)
#define | RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800)
#define | RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000)
#define | RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800)
#define | RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000)
#define | RCC_CFGR_SW ((uint32_t)0x00000003)
#define | RCC_CFGR_SW_0 ((uint32_t)0x00000001)
#define | RCC_CFGR_SW_1 ((uint32_t)0x00000002)
#define | RCC_CFGR_SW_HSE ((uint32_t)0x00000001)
#define | RCC_CFGR_SW_HSI ((uint32_t)0x00000000)
#define | RCC_CFGR_SW_PLL ((uint32_t)0x00000002)
#define | RCC_CFGR_SWS ((uint32_t)0x0000000C)
#define | RCC_CFGR_SWS_0 ((uint32_t)0x00000004)
#define | RCC_CFGR_SWS_1 ((uint32_t)0x00000008)
#define | RCC_CFGR_SWS_HSE ((uint32_t)0x00000004)
#define | RCC_CFGR_SWS_HSI ((uint32_t)0x00000000)
#define | RCC_CFGR_SWS_PLL ((uint32_t)0x00000008)
#define | RCC_CFGR_USBPRE ((uint32_t)0x00400000)
#define | RCC_CIR_CSSC ((uint32_t)0x00800000)
#define | RCC_CIR_CSSF ((uint32_t)0x00000080)
#define | RCC_CIR_HSERDYC ((uint32_t)0x00080000)
#define | RCC_CIR_HSERDYF ((uint32_t)0x00000008)
#define | RCC_CIR_HSERDYIE ((uint32_t)0x00000800)
#define | RCC_CIR_HSIRDYC ((uint32_t)0x00040000)
#define | RCC_CIR_HSIRDYF ((uint32_t)0x00000004)
#define | RCC_CIR_HSIRDYIE ((uint32_t)0x00000400)
#define | RCC_CIR_LSERDYC ((uint32_t)0x00020000)
#define | RCC_CIR_LSERDYF ((uint32_t)0x00000002)
#define | RCC_CIR_LSERDYIE ((uint32_t)0x00000200)
#define | RCC_CIR_LSIRDYC ((uint32_t)0x00010000)
#define | RCC_CIR_LSIRDYF ((uint32_t)0x00000001)
#define | RCC_CIR_LSIRDYIE ((uint32_t)0x00000100)
#define | RCC_CIR_PLLRDYC ((uint32_t)0x00100000)
#define | RCC_CIR_PLLRDYF ((uint32_t)0x00000010)
#define | RCC_CIR_PLLRDYIE ((uint32_t)0x00001000)
#define | RCC_CR_CSSON ((uint32_t)0x00080000)
#define | RCC_CR_HSEBYP ((uint32_t)0x00040000)
#define | RCC_CR_HSEON ((uint32_t)0x00010000)
#define | RCC_CR_HSERDY ((uint32_t)0x00020000)
#define | RCC_CR_HSICAL ((uint32_t)0x0000FF00)
#define | RCC_CR_HSION ((uint32_t)0x00000001)
#define | RCC_CR_HSIRDY ((uint32_t)0x00000002)
#define | RCC_CR_HSITRIM ((uint32_t)0x000000F8)
#define | RCC_CR_PLLON ((uint32_t)0x01000000)
#define | RCC_CR_PLLRDY ((uint32_t)0x02000000)
#define | RCC_CSR_IWDGRSTF ((uint32_t)0x20000000)
#define | RCC_CSR_LPWRRSTF ((uint32_t)0x80000000)
#define | RCC_CSR_LSION ((uint32_t)0x00000001)
#define | RCC_CSR_LSIRDY ((uint32_t)0x00000002)
#define | RCC_CSR_PINRSTF ((uint32_t)0x04000000)
#define | RCC_CSR_PORRSTF ((uint32_t)0x08000000)
#define | RCC_CSR_RMVF ((uint32_t)0x01000000)
#define | RCC_CSR_SFTRSTF ((uint32_t)0x10000000)
#define | RCC_CSR_WWDGRSTF ((uint32_t)0x40000000)
#define | READ_BIT(REG, BIT) ((REG) & (BIT))
#define | READ_REG(REG) ((REG))
#define | RTC ((RTC_TypeDef *) RTC_BASE)
#define | RTC_ALRH_RTC_ALR ((uint16_t)0xFFFF)
#define | RTC_ALRL_RTC_ALR ((uint16_t)0xFFFF)
#define | RTC_BASE (APB1PERIPH_BASE + 0x2800)
#define | RTC_CNTH_RTC_CNT ((uint16_t)0xFFFF)
#define | RTC_CNTL_RTC_CNT ((uint16_t)0xFFFF)
#define | RTC_CRH_ALRIE ((uint8_t)0x02)
#define | RTC_CRH_OWIE ((uint8_t)0x04)
#define | RTC_CRH_SECIE ((uint8_t)0x01)
#define | RTC_CRL_ALRF ((uint8_t)0x02)
#define | RTC_CRL_CNF ((uint8_t)0x10)
#define | RTC_CRL_OWF ((uint8_t)0x04)
#define | RTC_CRL_RSF ((uint8_t)0x08)
#define | RTC_CRL_RTOFF ((uint8_t)0x20)
#define | RTC_CRL_SECF ((uint8_t)0x01)
#define | RTC_DIVH_RTC_DIV ((uint16_t)0x000F)
#define | RTC_DIVL_RTC_DIV ((uint16_t)0xFFFF)
#define | RTC_PRLH_PRL ((uint16_t)0x000F)
#define | RTC_PRLL_PRL ((uint16_t)0xFFFF)
#define | SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF)
#define | SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000)
#define | SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700)
#define | SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000)
#define | SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100)
#define | SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200)
#define | SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300)
#define | SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400)
#define | SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500)
#define | SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600)
#define | SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700)
#define | SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100)
#define | SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200)
#define | SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400)
#define | SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004)
#define | SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002)
#define | SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000)
#define | SCB_AIRCR_VECTRESET ((uint32_t)0x00000001)
#define | SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF)
#define | SCB_CCR_BFHFNMIGN ((uint16_t)0x0100)
#define | SCB_CCR_DIV_0_TRP ((uint16_t)0x0010)
#define | SCB_CCR_NONBASETHRDENA ((uint16_t)0x0001)
#define | SCB_CCR_STKALIGN ((uint16_t)0x0200)
#define | SCB_CCR_UNALIGN_TRP ((uint16_t)0x0008)
#define | SCB_CCR_USERSETMPEND ((uint16_t)0x0002)
#define | SCB_CFSR_BFARVALID ((uint32_t)0x00008000)
#define | SCB_CFSR_DACCVIOL ((uint32_t)0x00000002)
#define | SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000)
#define | SCB_CFSR_IACCVIOL ((uint32_t)0x00000001)
#define | SCB_CFSR_IBUSERR ((uint32_t)0x00000100)
#define | SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400)
#define | SCB_CFSR_INVPC ((uint32_t)0x00040000)
#define | SCB_CFSR_INVSTATE ((uint32_t)0x00020000)
#define | SCB_CFSR_MMARVALID ((uint32_t)0x00000080)
#define | SCB_CFSR_MSTKERR ((uint32_t)0x00000010)
#define | SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008)
#define | SCB_CFSR_NOCP ((uint32_t)0x00080000)
#define | SCB_CFSR_PRECISERR ((uint32_t)0x00000200)
#define | SCB_CFSR_STKERR ((uint32_t)0x00001000)
#define | SCB_CFSR_UNALIGNED ((uint32_t)0x01000000)
#define | SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000)
#define | SCB_CFSR_UNSTKERR ((uint32_t)0x00000800)
#define | SCB_CPUID_Constant ((uint32_t)0x000F0000)
#define | SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000)
#define | SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0)
#define | SCB_CPUID_REVISION ((uint32_t)0x0000000F)
#define | SCB_CPUID_VARIANT ((uint32_t)0x00F00000)
#define | SCB_DFSR_BKPT ((uint8_t)0x02)
#define | SCB_DFSR_DWTTRAP ((uint8_t)0x04)
#define | SCB_DFSR_EXTERNAL ((uint8_t)0x10)
#define | SCB_DFSR_HALTED ((uint8_t)0x01)
#define | SCB_DFSR_VCATCH ((uint8_t)0x08)
#define | SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000)
#define | SCB_HFSR_FORCED ((uint32_t)0x40000000)
#define | SCB_HFSR_VECTTBL ((uint32_t)0x00000002)
#define | SCB_ICSR_ISRPENDING ((uint32_t)0x00400000)
#define | SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000)
#define | SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000)
#define | SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000)
#define | SCB_ICSR_PENDSTSET ((uint32_t)0x04000000)
#define | SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000)
#define | SCB_ICSR_PENDSVSET ((uint32_t)0x10000000)
#define | SCB_ICSR_RETTOBASE ((uint32_t)0x00000800)
#define | SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF)
#define | SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000)
#define | SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF)
#define | SCB_SCR_SEVONPEND ((uint8_t)0x10)
#define | SCB_SCR_SLEEPDEEP ((uint8_t)0x04)
#define | SCB_SCR_SLEEPONEXIT ((uint8_t)0x02)
#define | SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002)
#define | SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000)
#define | SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000)
#define | SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001)
#define | SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000)
#define | SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000)
#define | SCB_SHCSR_MONITORACT ((uint32_t)0x00000100)
#define | SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400)
#define | SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080)
#define | SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000)
#define | SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800)
#define | SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008)
#define | SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000)
#define | SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000)
#define | SCB_SHPR_PRI_N ((uint32_t)0x000000FF)
#define | SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00)
#define | SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000)
#define | SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000)
#define | SCB_VTOR_TBLBASE ((uint32_t)0x20000000)
#define | SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80)
#define | SDIO ((SDIO_TypeDef *) SDIO_BASE)
#define | SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF)
#define | SDIO_BASE (PERIPH_BASE + 0x18000)
#define | SDIO_CLKCR_BYPASS ((uint16_t)0x0400)
#define | SDIO_CLKCR_CLKDIV ((uint16_t)0x00FF)
#define | SDIO_CLKCR_CLKEN ((uint16_t)0x0100)
#define | SDIO_CLKCR_HWFC_EN ((uint16_t)0x4000)
#define | SDIO_CLKCR_NEGEDGE ((uint16_t)0x2000)
#define | SDIO_CLKCR_PWRSAV ((uint16_t)0x0200)
#define | SDIO_CLKCR_WIDBUS ((uint16_t)0x1800)
#define | SDIO_CLKCR_WIDBUS_0 ((uint16_t)0x0800)
#define | SDIO_CLKCR_WIDBUS_1 ((uint16_t)0x1000)
#define | SDIO_CMD_CEATACMD ((uint16_t)0x4000)
#define | SDIO_CMD_CMDINDEX ((uint16_t)0x003F)
#define | SDIO_CMD_CPSMEN ((uint16_t)0x0400)
#define | SDIO_CMD_ENCMDCOMPL ((uint16_t)0x1000)
#define | SDIO_CMD_NIEN ((uint16_t)0x2000)
#define | SDIO_CMD_SDIOSUSPEND ((uint16_t)0x0800)
#define | SDIO_CMD_WAITINT ((uint16_t)0x0100)
#define | SDIO_CMD_WAITPEND ((uint16_t)0x0200)
#define | SDIO_CMD_WAITRESP ((uint16_t)0x00C0)
#define | SDIO_CMD_WAITRESP_0 ((uint16_t)0x0040)
#define | SDIO_CMD_WAITRESP_1 ((uint16_t)0x0080)
#define | SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF)
#define | SDIO_DCTRL_DBLOCKSIZE ((uint16_t)0x00F0)
#define | SDIO_DCTRL_DBLOCKSIZE_0 ((uint16_t)0x0010)
#define | SDIO_DCTRL_DBLOCKSIZE_1 ((uint16_t)0x0020)
#define | SDIO_DCTRL_DBLOCKSIZE_2 ((uint16_t)0x0040)
#define | SDIO_DCTRL_DBLOCKSIZE_3 ((uint16_t)0x0080)
#define | SDIO_DCTRL_DMAEN ((uint16_t)0x0008)
#define | SDIO_DCTRL_DTDIR ((uint16_t)0x0002)
#define | SDIO_DCTRL_DTEN ((uint16_t)0x0001)
#define | SDIO_DCTRL_DTMODE ((uint16_t)0x0004)
#define | SDIO_DCTRL_RWMOD ((uint16_t)0x0400)
#define | SDIO_DCTRL_RWSTART ((uint16_t)0x0100)
#define | SDIO_DCTRL_RWSTOP ((uint16_t)0x0200)
#define | SDIO_DCTRL_SDIOEN ((uint16_t)0x0800)
#define | SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF)
#define | SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF)
#define | SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF)
#define | SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF)
#define | SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001)
#define | SDIO_ICR_CEATAENDC ((uint32_t)0x00800000)
#define | SDIO_ICR_CMDRENDC ((uint32_t)0x00000040)
#define | SDIO_ICR_CMDSENTC ((uint32_t)0x00000080)
#define | SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004)
#define | SDIO_ICR_DATAENDC ((uint32_t)0x00000100)
#define | SDIO_ICR_DBCKENDC ((uint32_t)0x00000400)
#define | SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002)
#define | SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008)
#define | SDIO_ICR_RXOVERRC ((uint32_t)0x00000020)
#define | SDIO_ICR_SDIOITC ((uint32_t)0x00400000)
#define | SDIO_ICR_STBITERRC ((uint32_t)0x00000200)
#define | SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010)
#define | SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001)
#define | SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000)
#define | SDIO_MASK_CMDACTIE ((uint32_t)0x00000800)
#define | SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040)
#define | SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080)
#define | SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004)
#define | SDIO_MASK_DATAENDIE ((uint32_t)0x00000100)
#define | SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400)
#define | SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002)
#define | SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008)
#define | SDIO_MASK_RXACTIE ((uint32_t)0x00002000)
#define | SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000)
#define | SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000)
#define | SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000)
#define | SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000)
#define | SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020)
#define | SDIO_MASK_SDIOITIE ((uint32_t)0x00400000)
#define | SDIO_MASK_STBITERRIE ((uint32_t)0x00000200)
#define | SDIO_MASK_TXACTIE ((uint32_t)0x00001000)
#define | SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000)
#define | SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000)
#define | SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000)
#define | SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000)
#define | SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010)
#define | SDIO_POWER_PWRCTRL ((uint8_t)0x03)
#define | SDIO_POWER_PWRCTRL_0 ((uint8_t)0x01)
#define | SDIO_POWER_PWRCTRL_1 ((uint8_t)0x02)
#define | SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF)
#define | SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF)
#define | SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF)
#define | SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF)
#define | SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF)
#define | SDIO_RESPCMD_RESPCMD ((uint8_t)0x3F)
#define | SDIO_STA_CCRCFAIL ((uint32_t)0x00000001)
#define | SDIO_STA_CEATAEND ((uint32_t)0x00800000)
#define | SDIO_STA_CMDACT ((uint32_t)0x00000800)
#define | SDIO_STA_CMDREND ((uint32_t)0x00000040)
#define | SDIO_STA_CMDSENT ((uint32_t)0x00000080)
#define | SDIO_STA_CTIMEOUT ((uint32_t)0x00000004)
#define | SDIO_STA_DATAEND ((uint32_t)0x00000100)
#define | SDIO_STA_DBCKEND ((uint32_t)0x00000400)
#define | SDIO_STA_DCRCFAIL ((uint32_t)0x00000002)
#define | SDIO_STA_DTIMEOUT ((uint32_t)0x00000008)
#define | SDIO_STA_RXACT ((uint32_t)0x00002000)
#define | SDIO_STA_RXDAVL ((uint32_t)0x00200000)
#define | SDIO_STA_RXFIFOE ((uint32_t)0x00080000)
#define | SDIO_STA_RXFIFOF ((uint32_t)0x00020000)
#define | SDIO_STA_RXFIFOHF ((uint32_t)0x00008000)
#define | SDIO_STA_RXOVERR ((uint32_t)0x00000020)
#define | SDIO_STA_SDIOIT ((uint32_t)0x00400000)
#define | SDIO_STA_STBITERR ((uint32_t)0x00000200)
#define | SDIO_STA_TXACT ((uint32_t)0x00001000)
#define | SDIO_STA_TXDAVL ((uint32_t)0x00100000)
#define | SDIO_STA_TXFIFOE ((uint32_t)0x00040000)
#define | SDIO_STA_TXFIFOF ((uint32_t)0x00010000)
#define | SDIO_STA_TXFIFOHE ((uint32_t)0x00004000)
#define | SDIO_STA_TXUNDERR ((uint32_t)0x00000010)
#define | SET_BIT(REG, BIT) ((REG) |= (BIT))
#define | SPI1 ((SPI_TypeDef *) SPI1_BASE)
#define | SPI1_BASE (APB2PERIPH_BASE + 0x3000)
#define | SPI2 ((SPI_TypeDef *) SPI2_BASE)
#define | SPI2_BASE (APB1PERIPH_BASE + 0x3800)
#define | SPI3 ((SPI_TypeDef *) SPI3_BASE)
#define | SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
#define | SPI_CR1_BIDIMODE ((uint16_t)0x8000)
#define | SPI_CR1_BIDIOE ((uint16_t)0x4000)
#define | SPI_CR1_BR ((uint16_t)0x0038)
#define | SPI_CR1_BR_0 ((uint16_t)0x0008)
#define | SPI_CR1_BR_1 ((uint16_t)0x0010)
#define | SPI_CR1_BR_2 ((uint16_t)0x0020)
#define | SPI_CR1_CPHA ((uint16_t)0x0001)
#define | SPI_CR1_CPOL ((uint16_t)0x0002)
#define | SPI_CR1_CRCEN ((uint16_t)0x2000)
#define | SPI_CR1_CRCNEXT ((uint16_t)0x1000)
#define | SPI_CR1_DFF ((uint16_t)0x0800)
#define | SPI_CR1_LSBFIRST ((uint16_t)0x0080)
#define | SPI_CR1_MSTR ((uint16_t)0x0004)
#define | SPI_CR1_RXONLY ((uint16_t)0x0400)
#define | SPI_CR1_SPE ((uint16_t)0x0040)
#define | SPI_CR1_SSI ((uint16_t)0x0100)
#define | SPI_CR1_SSM ((uint16_t)0x0200)
#define | SPI_CR2_ERRIE ((uint8_t)0x20)
#define | SPI_CR2_RXDMAEN ((uint8_t)0x01)
#define | SPI_CR2_RXNEIE ((uint8_t)0x40)
#define | SPI_CR2_SSOE ((uint8_t)0x04)
#define | SPI_CR2_TXDMAEN ((uint8_t)0x02)
#define | SPI_CR2_TXEIE ((uint8_t)0x80)
#define | SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF)
#define | SPI_DR_DR ((uint16_t)0xFFFF)
#define | SPI_I2SCFGR_CHLEN ((uint16_t)0x0001)
#define | SPI_I2SCFGR_CKPOL ((uint16_t)0x0008)
#define | SPI_I2SCFGR_DATLEN ((uint16_t)0x0006)
#define | SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002)
#define | SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004)
#define | SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300)
#define | SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100)
#define | SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200)
#define | SPI_I2SCFGR_I2SE ((uint16_t)0x0400)
#define | SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800)
#define | SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030)
#define | SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010)
#define | SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020)
#define | SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080)
#define | SPI_I2SPR_I2SDIV ((uint16_t)0x00FF)
#define | SPI_I2SPR_MCKOE ((uint16_t)0x0200)
#define | SPI_I2SPR_ODD ((uint16_t)0x0100)
#define | SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF)
#define | SPI_SR_BSY ((uint8_t)0x80)
#define | SPI_SR_CHSIDE ((uint8_t)0x04)
#define | SPI_SR_CRCERR ((uint8_t)0x10)
#define | SPI_SR_MODF ((uint8_t)0x20)
#define | SPI_SR_OVR ((uint8_t)0x40)
#define | SPI_SR_RXNE ((uint8_t)0x01)
#define | SPI_SR_TXE ((uint8_t)0x02)
#define | SPI_SR_UDR ((uint8_t)0x08)
#define | SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF)
#define | SRAM_BASE ((uint32_t)0x20000000)
#define | SRAM_BB_BASE ((uint32_t)0x22000000)
#define | SysTick_CALIB_NOREF ((uint32_t)0x80000000)
#define | SysTick_CALIB_SKEW ((uint32_t)0x40000000)
#define | SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF)
#define | SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004)
#define | SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000)
#define | SysTick_CTRL_ENABLE ((uint32_t)0x00000001)
#define | SysTick_CTRL_TICKINT ((uint32_t)0x00000002)
#define | SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF)
#define | SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF)
#define | TIM1 ((TIM_TypeDef *) TIM1_BASE)
#define | TIM10 ((TIM_TypeDef *) TIM10_BASE)
#define | TIM10_BASE (APB2PERIPH_BASE + 0x5000)
#define | TIM11 ((TIM_TypeDef *) TIM11_BASE)
#define | TIM11_BASE (APB2PERIPH_BASE + 0x5400)
#define | TIM12 ((TIM_TypeDef *) TIM12_BASE)
#define | TIM12_BASE (APB1PERIPH_BASE + 0x1800)
#define | TIM13 ((TIM_TypeDef *) TIM13_BASE)
#define | TIM13_BASE (APB1PERIPH_BASE + 0x1C00)
#define | TIM14 ((TIM_TypeDef *) TIM14_BASE)
#define | TIM14_BASE (APB1PERIPH_BASE + 0x2000)
#define | TIM15 ((TIM_TypeDef *) TIM15_BASE)
#define | TIM15_BASE (APB2PERIPH_BASE + 0x4000)
#define | TIM16 ((TIM_TypeDef *) TIM16_BASE)
#define | TIM16_BASE (APB2PERIPH_BASE + 0x4400)
#define | TIM17 ((TIM_TypeDef *) TIM17_BASE)
#define | TIM17_BASE (APB2PERIPH_BASE + 0x4800)
#define | TIM1_BASE (APB2PERIPH_BASE + 0x2C00)
#define | TIM2 ((TIM_TypeDef *) TIM2_BASE)
#define | TIM2_BASE (APB1PERIPH_BASE + 0x0000)
#define | TIM3 ((TIM_TypeDef *) TIM3_BASE)
#define | TIM3_BASE (APB1PERIPH_BASE + 0x0400)
#define | TIM4 ((TIM_TypeDef *) TIM4_BASE)
#define | TIM4_BASE (APB1PERIPH_BASE + 0x0800)
#define | TIM5 ((TIM_TypeDef *) TIM5_BASE)
#define | TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
#define | TIM6 ((TIM_TypeDef *) TIM6_BASE)
#define | TIM6_BASE (APB1PERIPH_BASE + 0x1000)
#define | TIM7 ((TIM_TypeDef *) TIM7_BASE)
#define | TIM7_BASE (APB1PERIPH_BASE + 0x1400)
#define | TIM8 ((TIM_TypeDef *) TIM8_BASE)
#define | TIM8_BASE (APB2PERIPH_BASE + 0x3400)
#define | TIM9 ((TIM_TypeDef *) TIM9_BASE)
#define | TIM9_BASE (APB2PERIPH_BASE + 0x4C00)
#define | TIM_ARR_ARR ((uint16_t)0xFFFF)
#define | TIM_BDTR_AOE ((uint16_t)0x4000)
#define | TIM_BDTR_BKE ((uint16_t)0x1000)
#define | TIM_BDTR_BKP ((uint16_t)0x2000)
#define | TIM_BDTR_DTG ((uint16_t)0x00FF)
#define | TIM_BDTR_DTG_0 ((uint16_t)0x0001)
#define | TIM_BDTR_DTG_1 ((uint16_t)0x0002)
#define | TIM_BDTR_DTG_2 ((uint16_t)0x0004)
#define | TIM_BDTR_DTG_3 ((uint16_t)0x0008)
#define | TIM_BDTR_DTG_4 ((uint16_t)0x0010)
#define | TIM_BDTR_DTG_5 ((uint16_t)0x0020)
#define | TIM_BDTR_DTG_6 ((uint16_t)0x0040)
#define | TIM_BDTR_DTG_7 ((uint16_t)0x0080)
#define | TIM_BDTR_LOCK ((uint16_t)0x0300)
#define | TIM_BDTR_LOCK_0 ((uint16_t)0x0100)
#define | TIM_BDTR_LOCK_1 ((uint16_t)0x0200)
#define | TIM_BDTR_MOE ((uint16_t)0x8000)
#define | TIM_BDTR_OSSI ((uint16_t)0x0400)
#define | TIM_BDTR_OSSR ((uint16_t)0x0800)
#define | TIM_CCER_CC1E ((uint16_t)0x0001)
#define | TIM_CCER_CC1NE ((uint16_t)0x0004)
#define | TIM_CCER_CC1NP ((uint16_t)0x0008)
#define | TIM_CCER_CC1P ((uint16_t)0x0002)
#define | TIM_CCER_CC2E ((uint16_t)0x0010)
#define | TIM_CCER_CC2NE ((uint16_t)0x0040)
#define | TIM_CCER_CC2NP ((uint16_t)0x0080)
#define | TIM_CCER_CC2P ((uint16_t)0x0020)
#define | TIM_CCER_CC3E ((uint16_t)0x0100)
#define | TIM_CCER_CC3NE ((uint16_t)0x0400)
#define | TIM_CCER_CC3NP ((uint16_t)0x0800)
#define | TIM_CCER_CC3P ((uint16_t)0x0200)
#define | TIM_CCER_CC4E ((uint16_t)0x1000)
#define | TIM_CCER_CC4NP ((uint16_t)0x8000)
#define | TIM_CCER_CC4P ((uint16_t)0x2000)
#define | TIM_CCMR1_CC1S ((uint16_t)0x0003)
#define | TIM_CCMR1_CC1S_0 ((uint16_t)0x0001)
#define | TIM_CCMR1_CC1S_1 ((uint16_t)0x0002)
#define | TIM_CCMR1_CC2S ((uint16_t)0x0300)
#define | TIM_CCMR1_CC2S_0 ((uint16_t)0x0100)
#define | TIM_CCMR1_CC2S_1 ((uint16_t)0x0200)
#define | TIM_CCMR1_IC1F ((uint16_t)0x00F0)
#define | TIM_CCMR1_IC1F_0 ((uint16_t)0x0010)
#define | TIM_CCMR1_IC1F_1 ((uint16_t)0x0020)
#define | TIM_CCMR1_IC1F_2 ((uint16_t)0x0040)
#define | TIM_CCMR1_IC1F_3 ((uint16_t)0x0080)
#define | TIM_CCMR1_IC1PSC ((uint16_t)0x000C)
#define | TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004)
#define | TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008)
#define | TIM_CCMR1_IC2F ((uint16_t)0xF000)
#define | TIM_CCMR1_IC2F_0 ((uint16_t)0x1000)
#define | TIM_CCMR1_IC2F_1 ((uint16_t)0x2000)
#define | TIM_CCMR1_IC2F_2 ((uint16_t)0x4000)
#define | TIM_CCMR1_IC2F_3 ((uint16_t)0x8000)
#define | TIM_CCMR1_IC2PSC ((uint16_t)0x0C00)
#define | TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400)
#define | TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800)
#define | TIM_CCMR1_OC1CE ((uint16_t)0x0080)
#define | TIM_CCMR1_OC1FE ((uint16_t)0x0004)
#define | TIM_CCMR1_OC1M ((uint16_t)0x0070)
#define | TIM_CCMR1_OC1M_0 ((uint16_t)0x0010)
#define | TIM_CCMR1_OC1M_1 ((uint16_t)0x0020)
#define | TIM_CCMR1_OC1M_2 ((uint16_t)0x0040)
#define | TIM_CCMR1_OC1PE ((uint16_t)0x0008)
#define | TIM_CCMR1_OC2CE ((uint16_t)0x8000)
#define | TIM_CCMR1_OC2FE ((uint16_t)0x0400)
#define | TIM_CCMR1_OC2M ((uint16_t)0x7000)
#define | TIM_CCMR1_OC2M_0 ((uint16_t)0x1000)
#define | TIM_CCMR1_OC2M_1 ((uint16_t)0x2000)
#define | TIM_CCMR1_OC2M_2 ((uint16_t)0x4000)
#define | TIM_CCMR1_OC2PE ((uint16_t)0x0800)
#define | TIM_CCMR2_CC3S ((uint16_t)0x0003)
#define | TIM_CCMR2_CC3S_0 ((uint16_t)0x0001)
#define | TIM_CCMR2_CC3S_1 ((uint16_t)0x0002)
#define | TIM_CCMR2_CC4S ((uint16_t)0x0300)
#define | TIM_CCMR2_CC4S_0 ((uint16_t)0x0100)
#define | TIM_CCMR2_CC4S_1 ((uint16_t)0x0200)
#define | TIM_CCMR2_IC3F ((uint16_t)0x00F0)
#define | TIM_CCMR2_IC3F_0 ((uint16_t)0x0010)
#define | TIM_CCMR2_IC3F_1 ((uint16_t)0x0020)
#define | TIM_CCMR2_IC3F_2 ((uint16_t)0x0040)
#define | TIM_CCMR2_IC3F_3 ((uint16_t)0x0080)
#define | TIM_CCMR2_IC3PSC ((uint16_t)0x000C)
#define | TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004)
#define | TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008)
#define | TIM_CCMR2_IC4F ((uint16_t)0xF000)
#define | TIM_CCMR2_IC4F_0 ((uint16_t)0x1000)
#define | TIM_CCMR2_IC4F_1 ((uint16_t)0x2000)
#define | TIM_CCMR2_IC4F_2 ((uint16_t)0x4000)
#define | TIM_CCMR2_IC4F_3 ((uint16_t)0x8000)
#define | TIM_CCMR2_IC4PSC ((uint16_t)0x0C00)
#define | TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400)
#define | TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800)
#define | TIM_CCMR2_OC3CE ((uint16_t)0x0080)
#define | TIM_CCMR2_OC3FE ((uint16_t)0x0004)
#define | TIM_CCMR2_OC3M ((uint16_t)0x0070)
#define | TIM_CCMR2_OC3M_0 ((uint16_t)0x0010)
#define | TIM_CCMR2_OC3M_1 ((uint16_t)0x0020)
#define | TIM_CCMR2_OC3M_2 ((uint16_t)0x0040)
#define | TIM_CCMR2_OC3PE ((uint16_t)0x0008)
#define | TIM_CCMR2_OC4CE ((uint16_t)0x8000)
#define | TIM_CCMR2_OC4FE ((uint16_t)0x0400)
#define | TIM_CCMR2_OC4M ((uint16_t)0x7000)
#define | TIM_CCMR2_OC4M_0 ((uint16_t)0x1000)
#define | TIM_CCMR2_OC4M_1 ((uint16_t)0x2000)
#define | TIM_CCMR2_OC4M_2 ((uint16_t)0x4000)
#define | TIM_CCMR2_OC4PE ((uint16_t)0x0800)
#define | TIM_CCR1_CCR1 ((uint16_t)0xFFFF)
#define | TIM_CCR2_CCR2 ((uint16_t)0xFFFF)
#define | TIM_CCR3_CCR3 ((uint16_t)0xFFFF)
#define | TIM_CCR4_CCR4 ((uint16_t)0xFFFF)
#define | TIM_CNT_CNT ((uint16_t)0xFFFF)
#define | TIM_CR1_ARPE ((uint16_t)0x0080)
#define | TIM_CR1_CEN ((uint16_t)0x0001)
#define | TIM_CR1_CKD ((uint16_t)0x0300)
#define | TIM_CR1_CKD_0 ((uint16_t)0x0100)
#define | TIM_CR1_CKD_1 ((uint16_t)0x0200)
#define | TIM_CR1_CMS ((uint16_t)0x0060)
#define | TIM_CR1_CMS_0 ((uint16_t)0x0020)
#define | TIM_CR1_CMS_1 ((uint16_t)0x0040)
#define | TIM_CR1_DIR ((uint16_t)0x0010)
#define | TIM_CR1_OPM ((uint16_t)0x0008)
#define | TIM_CR1_UDIS ((uint16_t)0x0002)
#define | TIM_CR1_URS ((uint16_t)0x0004)
#define | TIM_CR2_CCDS ((uint16_t)0x0008)
#define | TIM_CR2_CCPC ((uint16_t)0x0001)
#define | TIM_CR2_CCUS ((uint16_t)0x0004)
#define | TIM_CR2_MMS ((uint16_t)0x0070)
#define | TIM_CR2_MMS_0 ((uint16_t)0x0010)
#define | TIM_CR2_MMS_1 ((uint16_t)0x0020)
#define | TIM_CR2_MMS_2 ((uint16_t)0x0040)
#define | TIM_CR2_OIS1 ((uint16_t)0x0100)
#define | TIM_CR2_OIS1N ((uint16_t)0x0200)
#define | TIM_CR2_OIS2 ((uint16_t)0x0400)
#define | TIM_CR2_OIS2N ((uint16_t)0x0800)
#define | TIM_CR2_OIS3 ((uint16_t)0x1000)
#define | TIM_CR2_OIS3N ((uint16_t)0x2000)
#define | TIM_CR2_OIS4 ((uint16_t)0x4000)
#define | TIM_CR2_TI1S ((uint16_t)0x0080)
#define | TIM_DCR_DBA ((uint16_t)0x001F)
#define | TIM_DCR_DBA_0 ((uint16_t)0x0001)
#define | TIM_DCR_DBA_1 ((uint16_t)0x0002)
#define | TIM_DCR_DBA_2 ((uint16_t)0x0004)
#define | TIM_DCR_DBA_3 ((uint16_t)0x0008)
#define | TIM_DCR_DBA_4 ((uint16_t)0x0010)
#define | TIM_DCR_DBL ((uint16_t)0x1F00)
#define | TIM_DCR_DBL_0 ((uint16_t)0x0100)
#define | TIM_DCR_DBL_1 ((uint16_t)0x0200)
#define | TIM_DCR_DBL_2 ((uint16_t)0x0400)
#define | TIM_DCR_DBL_3 ((uint16_t)0x0800)
#define | TIM_DCR_DBL_4 ((uint16_t)0x1000)
#define | TIM_DIER_BIE ((uint16_t)0x0080)
#define | TIM_DIER_CC1DE ((uint16_t)0x0200)
#define | TIM_DIER_CC1IE ((uint16_t)0x0002)
#define | TIM_DIER_CC2DE ((uint16_t)0x0400)
#define | TIM_DIER_CC2IE ((uint16_t)0x0004)
#define | TIM_DIER_CC3DE ((uint16_t)0x0800)
#define | TIM_DIER_CC3IE ((uint16_t)0x0008)
#define | TIM_DIER_CC4DE ((uint16_t)0x1000)
#define | TIM_DIER_CC4IE ((uint16_t)0x0010)
#define | TIM_DIER_COMDE ((uint16_t)0x2000)
#define | TIM_DIER_COMIE ((uint16_t)0x0020)
#define | TIM_DIER_TDE ((uint16_t)0x4000)
#define | TIM_DIER_TIE ((uint16_t)0x0040)
#define | TIM_DIER_UDE ((uint16_t)0x0100)
#define | TIM_DIER_UIE ((uint16_t)0x0001)
#define | TIM_DMAR_DMAB ((uint16_t)0xFFFF)
#define | TIM_EGR_BG ((uint8_t)0x80)
#define | TIM_EGR_CC1G ((uint8_t)0x02)
#define | TIM_EGR_CC2G ((uint8_t)0x04)
#define | TIM_EGR_CC3G ((uint8_t)0x08)
#define | TIM_EGR_CC4G ((uint8_t)0x10)
#define | TIM_EGR_COMG ((uint8_t)0x20)
#define | TIM_EGR_TG ((uint8_t)0x40)
#define | TIM_EGR_UG ((uint8_t)0x01)
#define | TIM_PSC_PSC ((uint16_t)0xFFFF)
#define | TIM_RCR_REP ((uint8_t)0xFF)
#define | TIM_SMCR_ECE ((uint16_t)0x4000)
#define | TIM_SMCR_ETF ((uint16_t)0x0F00)
#define | TIM_SMCR_ETF_0 ((uint16_t)0x0100)
#define | TIM_SMCR_ETF_1 ((uint16_t)0x0200)
#define | TIM_SMCR_ETF_2 ((uint16_t)0x0400)
#define | TIM_SMCR_ETF_3 ((uint16_t)0x0800)
#define | TIM_SMCR_ETP ((uint16_t)0x8000)
#define | TIM_SMCR_ETPS ((uint16_t)0x3000)
#define | TIM_SMCR_ETPS_0 ((uint16_t)0x1000)
#define | TIM_SMCR_ETPS_1 ((uint16_t)0x2000)
#define | TIM_SMCR_MSM ((uint16_t)0x0080)
#define | TIM_SMCR_SMS ((uint16_t)0x0007)
#define | TIM_SMCR_SMS_0 ((uint16_t)0x0001)
#define | TIM_SMCR_SMS_1 ((uint16_t)0x0002)
#define | TIM_SMCR_SMS_2 ((uint16_t)0x0004)
#define | TIM_SMCR_TS ((uint16_t)0x0070)
#define | TIM_SMCR_TS_0 ((uint16_t)0x0010)
#define | TIM_SMCR_TS_1 ((uint16_t)0x0020)
#define | TIM_SMCR_TS_2 ((uint16_t)0x0040)
#define | TIM_SR_BIF ((uint16_t)0x0080)
#define | TIM_SR_CC1IF ((uint16_t)0x0002)
#define | TIM_SR_CC1OF ((uint16_t)0x0200)
#define | TIM_SR_CC2IF ((uint16_t)0x0004)
#define | TIM_SR_CC2OF ((uint16_t)0x0400)
#define | TIM_SR_CC3IF ((uint16_t)0x0008)
#define | TIM_SR_CC3OF ((uint16_t)0x0800)
#define | TIM_SR_CC4IF ((uint16_t)0x0010)
#define | TIM_SR_CC4OF ((uint16_t)0x1000)
#define | TIM_SR_COMIF ((uint16_t)0x0020)
#define | TIM_SR_TIF ((uint16_t)0x0040)
#define | TIM_SR_UIF ((uint16_t)0x0001)
#define | UART4 ((USART_TypeDef *) UART4_BASE)
#define | UART4_BASE (APB1PERIPH_BASE + 0x4C00)
#define | UART5 ((USART_TypeDef *) UART5_BASE)
#define | UART5_BASE (APB1PERIPH_BASE + 0x5000)
#define | USART1 ((USART_TypeDef *) USART1_BASE)
#define | USART1_BASE (APB2PERIPH_BASE + 0x3800)
#define | USART2 ((USART_TypeDef *) USART2_BASE)
#define | USART2_BASE (APB1PERIPH_BASE + 0x4400)
#define | USART3 ((USART_TypeDef *) USART3_BASE)
#define | USART3_BASE (APB1PERIPH_BASE + 0x4800)
#define | USART_BRR_DIV_Fraction ((uint16_t)0x000F)
#define | USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0)
#define | USART_CR1_IDLEIE ((uint16_t)0x0010)
#define | USART_CR1_M ((uint16_t)0x1000)
#define | USART_CR1_OVER8 ((uint16_t)0x8000)
#define | USART_CR1_PCE ((uint16_t)0x0400)
#define | USART_CR1_PEIE ((uint16_t)0x0100)
#define | USART_CR1_PS ((uint16_t)0x0200)
#define | USART_CR1_RE ((uint16_t)0x0004)
#define | USART_CR1_RWU ((uint16_t)0x0002)
#define | USART_CR1_RXNEIE ((uint16_t)0x0020)
#define | USART_CR1_SBK ((uint16_t)0x0001)
#define | USART_CR1_TCIE ((uint16_t)0x0040)
#define | USART_CR1_TE ((uint16_t)0x0008)
#define | USART_CR1_TXEIE ((uint16_t)0x0080)
#define | USART_CR1_UE ((uint16_t)0x2000)
#define | USART_CR1_WAKE ((uint16_t)0x0800)
#define | USART_CR2_ADD ((uint16_t)0x000F)
#define | USART_CR2_CLKEN ((uint16_t)0x0800)
#define | USART_CR2_CPHA ((uint16_t)0x0200)
#define | USART_CR2_CPOL ((uint16_t)0x0400)
#define | USART_CR2_LBCL ((uint16_t)0x0100)
#define | USART_CR2_LBDIE ((uint16_t)0x0040)
#define | USART_CR2_LBDL ((uint16_t)0x0020)
#define | USART_CR2_LINEN ((uint16_t)0x4000)
#define | USART_CR2_STOP ((uint16_t)0x3000)
#define | USART_CR2_STOP_0 ((uint16_t)0x1000)
#define | USART_CR2_STOP_1 ((uint16_t)0x2000)
#define | USART_CR3_CTSE ((uint16_t)0x0200)
#define | USART_CR3_CTSIE ((uint16_t)0x0400)
#define | USART_CR3_DMAR ((uint16_t)0x0040)
#define | USART_CR3_DMAT ((uint16_t)0x0080)
#define | USART_CR3_EIE ((uint16_t)0x0001)
#define | USART_CR3_HDSEL ((uint16_t)0x0008)
#define | USART_CR3_IREN ((uint16_t)0x0002)
#define | USART_CR3_IRLP ((uint16_t)0x0004)
#define | USART_CR3_NACK ((uint16_t)0x0010)
#define | USART_CR3_ONEBIT ((uint16_t)0x0800)
#define | USART_CR3_RTSE ((uint16_t)0x0100)
#define | USART_CR3_SCEN ((uint16_t)0x0020)
#define | USART_DR_DR ((uint16_t)0x01FF)
#define | USART_GTPR_GT ((uint16_t)0xFF00)
#define | USART_GTPR_PSC ((uint16_t)0x00FF)
#define | USART_GTPR_PSC_0 ((uint16_t)0x0001)
#define | USART_GTPR_PSC_1 ((uint16_t)0x0002)
#define | USART_GTPR_PSC_2 ((uint16_t)0x0004)
#define | USART_GTPR_PSC_3 ((uint16_t)0x0008)
#define | USART_GTPR_PSC_4 ((uint16_t)0x0010)
#define | USART_GTPR_PSC_5 ((uint16_t)0x0020)
#define | USART_GTPR_PSC_6 ((uint16_t)0x0040)
#define | USART_GTPR_PSC_7 ((uint16_t)0x0080)
#define | USART_SR_CTS ((uint16_t)0x0200)
#define | USART_SR_FE ((uint16_t)0x0002)
#define | USART_SR_IDLE ((uint16_t)0x0010)
#define | USART_SR_LBD ((uint16_t)0x0100)
#define | USART_SR_NE ((uint16_t)0x0004)
#define | USART_SR_ORE ((uint16_t)0x0008)
#define | USART_SR_PE ((uint16_t)0x0001)
#define | USART_SR_RXNE ((uint16_t)0x0020)
#define | USART_SR_TC ((uint16_t)0x0040)
#define | USART_SR_TXE ((uint16_t)0x0080)
#define | USB_ADDR0_RX_ADDR0_RX ((uint16_t)0xFFFE)
#define | USB_ADDR0_TX_ADDR0_TX ((uint16_t)0xFFFE)
#define | USB_ADDR1_RX_ADDR1_RX ((uint16_t)0xFFFE)
#define | USB_ADDR1_TX_ADDR1_TX ((uint16_t)0xFFFE)
#define | USB_ADDR2_RX_ADDR2_RX ((uint16_t)0xFFFE)
#define | USB_ADDR2_TX_ADDR2_TX ((uint16_t)0xFFFE)
#define | USB_ADDR3_RX_ADDR3_RX ((uint16_t)0xFFFE)
#define | USB_ADDR3_TX_ADDR3_TX ((uint16_t)0xFFFE)
#define | USB_ADDR4_RX_ADDR4_RX ((uint16_t)0xFFFE)
#define | USB_ADDR4_TX_ADDR4_TX ((uint16_t)0xFFFE)
#define | USB_ADDR5_RX_ADDR5_RX ((uint16_t)0xFFFE)
#define | USB_ADDR5_TX_ADDR5_TX ((uint16_t)0xFFFE)
#define | USB_ADDR6_RX_ADDR6_RX ((uint16_t)0xFFFE)
#define | USB_ADDR6_TX_ADDR6_TX ((uint16_t)0xFFFE)
#define | USB_ADDR7_RX_ADDR7_RX ((uint16_t)0xFFFE)
#define | USB_ADDR7_TX_ADDR7_TX ((uint16_t)0xFFFE)
#define | USB_BTABLE_BTABLE ((uint16_t)0xFFF8)
#define | USB_CNTR_CTRM ((uint16_t)0x8000)
#define | USB_CNTR_ERRM ((uint16_t)0x2000)
#define | USB_CNTR_ESOFM ((uint16_t)0x0100)
#define | USB_CNTR_FRES ((uint16_t)0x0001)
#define | USB_CNTR_FSUSP ((uint16_t)0x0008)
#define | USB_CNTR_LP_MODE ((uint16_t)0x0004)
#define | USB_CNTR_PDWN ((uint16_t)0x0002)
#define | USB_CNTR_PMAOVRM ((uint16_t)0x4000)
#define | USB_CNTR_RESETM ((uint16_t)0x0400)
#define | USB_CNTR_RESUME ((uint16_t)0x0010)
#define | USB_CNTR_SOFM ((uint16_t)0x0200)
#define | USB_CNTR_SUSPM ((uint16_t)0x0800)
#define | USB_CNTR_WKUPM ((uint16_t)0x1000)
#define | USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000)
#define | USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF)
#define | USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00)
#define | USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400)
#define | USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800)
#define | USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000)
#define | USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000)
#define | USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000)
#define | USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000)
#define | USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000)
#define | USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000)
#define | USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000)
#define | USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000)
#define | USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000)
#define | USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000)
#define | USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000)
#define | USB_COUNT0_RX_BLSIZE ((uint16_t)0x8000)
#define | USB_COUNT0_RX_COUNT0_RX ((uint16_t)0x03FF)
#define | USB_COUNT0_RX_NUM_BLOCK ((uint16_t)0x7C00)
#define | USB_COUNT0_RX_NUM_BLOCK_0 ((uint16_t)0x0400)
#define | USB_COUNT0_RX_NUM_BLOCK_1 ((uint16_t)0x0800)
#define | USB_COUNT0_RX_NUM_BLOCK_2 ((uint16_t)0x1000)
#define | USB_COUNT0_RX_NUM_BLOCK_3 ((uint16_t)0x2000)
#define | USB_COUNT0_RX_NUM_BLOCK_4 ((uint16_t)0x4000)
#define | USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF)
#define | USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000)
#define | USB_COUNT0_TX_COUNT0_TX ((uint16_t)0x03FF)
#define | USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000)
#define | USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF)
#define | USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00)
#define | USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400)
#define | USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800)
#define | USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000)
#define | USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000)
#define | USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000)
#define | USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000)
#define | USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000)
#define | USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000)
#define | USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000)
#define | USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000)
#define | USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000)
#define | USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000)
#define | USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000)
#define | USB_COUNT1_RX_BLSIZE ((uint16_t)0x8000)
#define | USB_COUNT1_RX_COUNT1_RX ((uint16_t)0x03FF)
#define | USB_COUNT1_RX_NUM_BLOCK ((uint16_t)0x7C00)
#define | USB_COUNT1_RX_NUM_BLOCK_0 ((uint16_t)0x0400)
#define | USB_COUNT1_RX_NUM_BLOCK_1 ((uint16_t)0x0800)
#define | USB_COUNT1_RX_NUM_BLOCK_2 ((uint16_t)0x1000)
#define | USB_COUNT1_RX_NUM_BLOCK_3 ((uint16_t)0x2000)
#define | USB_COUNT1_RX_NUM_BLOCK_4 ((uint16_t)0x4000)
#define | USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF)
#define | USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000)
#define | USB_COUNT1_TX_COUNT1_TX ((uint16_t)0x03FF)
#define | USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000)
#define | USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF)
#define | USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00)
#define | USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400)
#define | USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800)
#define | USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000)
#define | USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000)
#define | USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000)
#define | USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000)
#define | USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000)
#define | USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000)
#define | USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000)
#define | USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000)
#define | USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000)
#define | USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000)
#define | USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000)
#define | USB_COUNT2_RX_BLSIZE ((uint16_t)0x8000)
#define | USB_COUNT2_RX_COUNT2_RX ((uint16_t)0x03FF)
#define | USB_COUNT2_RX_NUM_BLOCK ((uint16_t)0x7C00)
#define | USB_COUNT2_RX_NUM_BLOCK_0 ((uint16_t)0x0400)
#define | USB_COUNT2_RX_NUM_BLOCK_1 ((uint16_t)0x0800)
#define | USB_COUNT2_RX_NUM_BLOCK_2 ((uint16_t)0x1000)
#define | USB_COUNT2_RX_NUM_BLOCK_3 ((uint16_t)0x2000)
#define | USB_COUNT2_RX_NUM_BLOCK_4 ((uint16_t)0x4000)
#define | USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF)
#define | USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000)
#define | USB_COUNT2_TX_COUNT2_TX ((uint16_t)0x03FF)
#define | USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000)
#define | USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF)
#define | USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00)
#define | USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400)
#define | USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800)
#define | USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000)
#define | USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000)
#define | USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000)
#define | USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000)
#define | USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000)
#define | USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000)
#define | USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000)
#define | USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000)
#define | USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000)
#define | USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000)
#define | USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000)
#define | USB_COUNT3_RX_BLSIZE ((uint16_t)0x8000)
#define | USB_COUNT3_RX_COUNT3_RX ((uint16_t)0x03FF)
#define | USB_COUNT3_RX_NUM_BLOCK ((uint16_t)0x7C00)
#define | USB_COUNT3_RX_NUM_BLOCK_0 ((uint16_t)0x0400)
#define | USB_COUNT3_RX_NUM_BLOCK_1 ((uint16_t)0x0800)
#define | USB_COUNT3_RX_NUM_BLOCK_2 ((uint16_t)0x1000)
#define | USB_COUNT3_RX_NUM_BLOCK_3 ((uint16_t)0x2000)
#define | USB_COUNT3_RX_NUM_BLOCK_4 ((uint16_t)0x4000)
#define | USB_COUNT3_TX_0_COUNT3_TX_0 ((uint16_t)0x000003FF)
#define | USB_COUNT3_TX_1_COUNT3_TX_1 ((uint16_t)0x03FF0000)
#define | USB_COUNT3_TX_COUNT3_TX ((uint16_t)0x03FF)
#define | USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000)
#define | USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF)
#define | USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00)
#define | USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400)
#define | USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800)
#define | USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000)
#define | USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000)
#define | USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000)
#define | USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000)
#define | USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000)
#define | USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000)
#define | USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000)
#define | USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000)
#define | USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000)
#define | USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000)
#define | USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000)
#define | USB_COUNT4_RX_BLSIZE ((uint16_t)0x8000)
#define | USB_COUNT4_RX_COUNT4_RX ((uint16_t)0x03FF)
#define | USB_COUNT4_RX_NUM_BLOCK ((uint16_t)0x7C00)
#define | USB_COUNT4_RX_NUM_BLOCK_0 ((uint16_t)0x0400)
#define | USB_COUNT4_RX_NUM_BLOCK_1 ((uint16_t)0x0800)
#define | USB_COUNT4_RX_NUM_BLOCK_2 ((uint16_t)0x1000)
#define | USB_COUNT4_RX_NUM_BLOCK_3 ((uint16_t)0x2000)
#define | USB_COUNT4_RX_NUM_BLOCK_4 ((uint16_t)0x4000)
#define | USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF)
#define | USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000)
#define | USB_COUNT4_TX_COUNT4_TX ((uint16_t)0x03FF)
#define | USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000)
#define | USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF)
#define | USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00)
#define | USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400)
#define | USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800)
#define | USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000)
#define | USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000)
#define | USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000)
#define | USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000)
#define | USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000)
#define | USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000)
#define | USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000)
#define | USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000)
#define | USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000)
#define | USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000)
#define | USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000)
#define | USB_COUNT5_RX_BLSIZE ((uint16_t)0x8000)
#define | USB_COUNT5_RX_COUNT5_RX ((uint16_t)0x03FF)
#define | USB_COUNT5_RX_NUM_BLOCK ((uint16_t)0x7C00)
#define | USB_COUNT5_RX_NUM_BLOCK_0 ((uint16_t)0x0400)
#define | USB_COUNT5_RX_NUM_BLOCK_1 ((uint16_t)0x0800)
#define | USB_COUNT5_RX_NUM_BLOCK_2 ((uint16_t)0x1000)
#define | USB_COUNT5_RX_NUM_BLOCK_3 ((uint16_t)0x2000)
#define | USB_COUNT5_RX_NUM_BLOCK_4 ((uint16_t)0x4000)
#define | USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF)
#define | USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000)
#define | USB_COUNT5_TX_COUNT5_TX ((uint16_t)0x03FF)
#define | USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000)
#define | USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF)
#define | USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00)
#define | USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400)
#define | USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800)
#define | USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000)
#define | USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000)
#define | USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000)
#define | USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000)
#define | USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000)
#define | USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000)
#define | USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000)
#define | USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000)
#define | USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000)
#define | USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000)
#define | USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000)
#define | USB_COUNT6_RX_BLSIZE ((uint16_t)0x8000)
#define | USB_COUNT6_RX_COUNT6_RX ((uint16_t)0x03FF)
#define | USB_COUNT6_RX_NUM_BLOCK ((uint16_t)0x7C00)
#define | USB_COUNT6_RX_NUM_BLOCK_0 ((uint16_t)0x0400)
#define | USB_COUNT6_RX_NUM_BLOCK_1 ((uint16_t)0x0800)
#define | USB_COUNT6_RX_NUM_BLOCK_2 ((uint16_t)0x1000)
#define | USB_COUNT6_RX_NUM_BLOCK_3 ((uint16_t)0x2000)
#define | USB_COUNT6_RX_NUM_BLOCK_4 ((uint16_t)0x4000)
#define | USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF)
#define | USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000)
#define | USB_COUNT6_TX_COUNT6_TX ((uint16_t)0x03FF)
#define | USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000)
#define | USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF)
#define | USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00)
#define | USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400)
#define | USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800)
#define | USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000)
#define | USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000)
#define | USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000)
#define | USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000)
#define | USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000)
#define | USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000)
#define | USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000)
#define | USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000)
#define | USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000)
#define | USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000)
#define | USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000)
#define | USB_COUNT7_RX_BLSIZE ((uint16_t)0x8000)
#define | USB_COUNT7_RX_COUNT7_RX ((uint16_t)0x03FF)
#define | USB_COUNT7_RX_NUM_BLOCK ((uint16_t)0x7C00)
#define | USB_COUNT7_RX_NUM_BLOCK_0 ((uint16_t)0x0400)
#define | USB_COUNT7_RX_NUM_BLOCK_1 ((uint16_t)0x0800)
#define | USB_COUNT7_RX_NUM_BLOCK_2 ((uint16_t)0x1000)
#define | USB_COUNT7_RX_NUM_BLOCK_3 ((uint16_t)0x2000)
#define | USB_COUNT7_RX_NUM_BLOCK_4 ((uint16_t)0x4000)
#define | USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF)
#define | USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000)
#define | USB_COUNT7_TX_COUNT7_TX ((uint16_t)0x03FF)
#define | USB_DADDR_ADD ((uint8_t)0x7F)
#define | USB_DADDR_ADD0 ((uint8_t)0x01)
#define | USB_DADDR_ADD1 ((uint8_t)0x02)
#define | USB_DADDR_ADD2 ((uint8_t)0x04)
#define | USB_DADDR_ADD3 ((uint8_t)0x08)
#define | USB_DADDR_ADD4 ((uint8_t)0x10)
#define | USB_DADDR_ADD5 ((uint8_t)0x20)
#define | USB_DADDR_ADD6 ((uint8_t)0x40)
#define | USB_DADDR_EF ((uint8_t)0x80)
#define | USB_EP0R_CTR_RX ((uint16_t)0x8000)
#define | USB_EP0R_CTR_TX ((uint16_t)0x0080)
#define | USB_EP0R_DTOG_RX ((uint16_t)0x4000)
#define | USB_EP0R_DTOG_TX ((uint16_t)0x0040)
#define | USB_EP0R_EA ((uint16_t)0x000F)
#define | USB_EP0R_EP_KIND ((uint16_t)0x0100)
#define | USB_EP0R_EP_TYPE ((uint16_t)0x0600)
#define | USB_EP0R_EP_TYPE_0 ((uint16_t)0x0200)
#define | USB_EP0R_EP_TYPE_1 ((uint16_t)0x0400)
#define | USB_EP0R_SETUP ((uint16_t)0x0800)
#define | USB_EP0R_STAT_RX ((uint16_t)0x3000)
#define | USB_EP0R_STAT_RX_0 ((uint16_t)0x1000)
#define | USB_EP0R_STAT_RX_1 ((uint16_t)0x2000)
#define | USB_EP0R_STAT_TX ((uint16_t)0x0030)
#define | USB_EP0R_STAT_TX_0 ((uint16_t)0x0010)
#define | USB_EP0R_STAT_TX_1 ((uint16_t)0x0020)
#define | USB_EP1R_CTR_RX ((uint16_t)0x8000)
#define | USB_EP1R_CTR_TX ((uint16_t)0x0080)
#define | USB_EP1R_DTOG_RX ((uint16_t)0x4000)
#define | USB_EP1R_DTOG_TX ((uint16_t)0x0040)
#define | USB_EP1R_EA ((uint16_t)0x000F)
#define | USB_EP1R_EP_KIND ((uint16_t)0x0100)
#define | USB_EP1R_EP_TYPE ((uint16_t)0x0600)
#define | USB_EP1R_EP_TYPE_0 ((uint16_t)0x0200)
#define | USB_EP1R_EP_TYPE_1 ((uint16_t)0x0400)
#define | USB_EP1R_SETUP ((uint16_t)0x0800)
#define | USB_EP1R_STAT_RX ((uint16_t)0x3000)
#define | USB_EP1R_STAT_RX_0 ((uint16_t)0x1000)
#define | USB_EP1R_STAT_RX_1 ((uint16_t)0x2000)
#define | USB_EP1R_STAT_TX ((uint16_t)0x0030)
#define | USB_EP1R_STAT_TX_0 ((uint16_t)0x0010)
#define | USB_EP1R_STAT_TX_1 ((uint16_t)0x0020)
#define | USB_EP2R_CTR_RX ((uint16_t)0x8000)
#define | USB_EP2R_CTR_TX ((uint16_t)0x0080)
#define | USB_EP2R_DTOG_RX ((uint16_t)0x4000)
#define | USB_EP2R_DTOG_TX ((uint16_t)0x0040)
#define | USB_EP2R_EA ((uint16_t)0x000F)
#define | USB_EP2R_EP_KIND ((uint16_t)0x0100)
#define | USB_EP2R_EP_TYPE ((uint16_t)0x0600)
#define | USB_EP2R_EP_TYPE_0 ((uint16_t)0x0200)
#define | USB_EP2R_EP_TYPE_1 ((uint16_t)0x0400)
#define | USB_EP2R_SETUP ((uint16_t)0x0800)
#define | USB_EP2R_STAT_RX ((uint16_t)0x3000)
#define | USB_EP2R_STAT_RX_0 ((uint16_t)0x1000)
#define | USB_EP2R_STAT_RX_1 ((uint16_t)0x2000)
#define | USB_EP2R_STAT_TX ((uint16_t)0x0030)
#define | USB_EP2R_STAT_TX_0 ((uint16_t)0x0010)
#define | USB_EP2R_STAT_TX_1 ((uint16_t)0x0020)
#define | USB_EP3R_CTR_RX ((uint16_t)0x8000)
#define | USB_EP3R_CTR_TX ((uint16_t)0x0080)
#define | USB_EP3R_DTOG_RX ((uint16_t)0x4000)
#define | USB_EP3R_DTOG_TX ((uint16_t)0x0040)
#define | USB_EP3R_EA ((uint16_t)0x000F)
#define | USB_EP3R_EP_KIND ((uint16_t)0x0100)
#define | USB_EP3R_EP_TYPE ((uint16_t)0x0600)
#define | USB_EP3R_EP_TYPE_0 ((uint16_t)0x0200)
#define | USB_EP3R_EP_TYPE_1 ((uint16_t)0x0400)
#define | USB_EP3R_SETUP ((uint16_t)0x0800)
#define | USB_EP3R_STAT_RX ((uint16_t)0x3000)
#define | USB_EP3R_STAT_RX_0 ((uint16_t)0x1000)
#define | USB_EP3R_STAT_RX_1 ((uint16_t)0x2000)
#define | USB_EP3R_STAT_TX ((uint16_t)0x0030)
#define | USB_EP3R_STAT_TX_0 ((uint16_t)0x0010)
#define | USB_EP3R_STAT_TX_1 ((uint16_t)0x0020)
#define | USB_EP4R_CTR_RX ((uint16_t)0x8000)
#define | USB_EP4R_CTR_TX ((uint16_t)0x0080)
#define | USB_EP4R_DTOG_RX ((uint16_t)0x4000)
#define | USB_EP4R_DTOG_TX ((uint16_t)0x0040)
#define | USB_EP4R_EA ((uint16_t)0x000F)
#define | USB_EP4R_EP_KIND ((uint16_t)0x0100)
#define | USB_EP4R_EP_TYPE ((uint16_t)0x0600)
#define | USB_EP4R_EP_TYPE_0 ((uint16_t)0x0200)
#define | USB_EP4R_EP_TYPE_1 ((uint16_t)0x0400)
#define | USB_EP4R_SETUP ((uint16_t)0x0800)
#define | USB_EP4R_STAT_RX ((uint16_t)0x3000)
#define | USB_EP4R_STAT_RX_0 ((uint16_t)0x1000)
#define | USB_EP4R_STAT_RX_1 ((uint16_t)0x2000)
#define | USB_EP4R_STAT_TX ((uint16_t)0x0030)
#define | USB_EP4R_STAT_TX_0 ((uint16_t)0x0010)
#define | USB_EP4R_STAT_TX_1 ((uint16_t)0x0020)
#define | USB_EP5R_CTR_RX ((uint16_t)0x8000)
#define | USB_EP5R_CTR_TX ((uint16_t)0x0080)
#define | USB_EP5R_DTOG_RX ((uint16_t)0x4000)
#define | USB_EP5R_DTOG_TX ((uint16_t)0x0040)
#define | USB_EP5R_EA ((uint16_t)0x000F)
#define | USB_EP5R_EP_KIND ((uint16_t)0x0100)
#define | USB_EP5R_EP_TYPE ((uint16_t)0x0600)
#define | USB_EP5R_EP_TYPE_0 ((uint16_t)0x0200)
#define | USB_EP5R_EP_TYPE_1 ((uint16_t)0x0400)
#define | USB_EP5R_SETUP ((uint16_t)0x0800)
#define | USB_EP5R_STAT_RX ((uint16_t)0x3000)
#define | USB_EP5R_STAT_RX_0 ((uint16_t)0x1000)
#define | USB_EP5R_STAT_RX_1 ((uint16_t)0x2000)
#define | USB_EP5R_STAT_TX ((uint16_t)0x0030)
#define | USB_EP5R_STAT_TX_0 ((uint16_t)0x0010)
#define | USB_EP5R_STAT_TX_1 ((uint16_t)0x0020)
#define | USB_EP6R_CTR_RX ((uint16_t)0x8000)
#define | USB_EP6R_CTR_TX ((uint16_t)0x0080)
#define | USB_EP6R_DTOG_RX ((uint16_t)0x4000)
#define | USB_EP6R_DTOG_TX ((uint16_t)0x0040)
#define | USB_EP6R_EA ((uint16_t)0x000F)
#define | USB_EP6R_EP_KIND ((uint16_t)0x0100)
#define | USB_EP6R_EP_TYPE ((uint16_t)0x0600)
#define | USB_EP6R_EP_TYPE_0 ((uint16_t)0x0200)
#define | USB_EP6R_EP_TYPE_1 ((uint16_t)0x0400)
#define | USB_EP6R_SETUP ((uint16_t)0x0800)
#define | USB_EP6R_STAT_RX ((uint16_t)0x3000)
#define | USB_EP6R_STAT_RX_0 ((uint16_t)0x1000)
#define | USB_EP6R_STAT_RX_1 ((uint16_t)0x2000)
#define | USB_EP6R_STAT_TX ((uint16_t)0x0030)
#define | USB_EP6R_STAT_TX_0 ((uint16_t)0x0010)
#define | USB_EP6R_STAT_TX_1 ((uint16_t)0x0020)
#define | USB_EP7R_CTR_RX ((uint16_t)0x8000)
#define | USB_EP7R_CTR_TX ((uint16_t)0x0080)
#define | USB_EP7R_DTOG_RX ((uint16_t)0x4000)
#define | USB_EP7R_DTOG_TX ((uint16_t)0x0040)
#define | USB_EP7R_EA ((uint16_t)0x000F)
#define | USB_EP7R_EP_KIND ((uint16_t)0x0100)
#define | USB_EP7R_EP_TYPE ((uint16_t)0x0600)
#define | USB_EP7R_EP_TYPE_0 ((uint16_t)0x0200)
#define | USB_EP7R_EP_TYPE_1 ((uint16_t)0x0400)
#define | USB_EP7R_SETUP ((uint16_t)0x0800)
#define | USB_EP7R_STAT_RX ((uint16_t)0x3000)
#define | USB_EP7R_STAT_RX_0 ((uint16_t)0x1000)
#define | USB_EP7R_STAT_RX_1 ((uint16_t)0x2000)
#define | USB_EP7R_STAT_TX ((uint16_t)0x0030)
#define | USB_EP7R_STAT_TX_0 ((uint16_t)0x0010)
#define | USB_EP7R_STAT_TX_1 ((uint16_t)0x0020)
#define | USB_FNR_FN ((uint16_t)0x07FF)
#define | USB_FNR_LCK ((uint16_t)0x2000)
#define | USB_FNR_LSOF ((uint16_t)0x1800)
#define | USB_FNR_RXDM ((uint16_t)0x4000)
#define | USB_FNR_RXDP ((uint16_t)0x8000)
#define | USB_ISTR_CTR ((uint16_t)0x8000)
#define | USB_ISTR_DIR ((uint16_t)0x0010)
#define | USB_ISTR_EP_ID ((uint16_t)0x000F)
#define | USB_ISTR_ERR ((uint16_t)0x2000)
#define | USB_ISTR_ESOF ((uint16_t)0x0100)
#define | USB_ISTR_PMAOVR ((uint16_t)0x4000)
#define | USB_ISTR_RESET ((uint16_t)0x0400)
#define | USB_ISTR_SOF ((uint16_t)0x0200)
#define | USB_ISTR_SUSP ((uint16_t)0x0800)
#define | USB_ISTR_WKUP ((uint16_t)0x1000)
#define | WRITE_REG(REG, VAL) ((REG) = (VAL))
#define | WWDG ((WWDG_TypeDef *) WWDG_BASE)
#define | WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
#define | WWDG_CFR_EWI ((uint16_t)0x0200)
#define | WWDG_CFR_W ((uint16_t)0x007F)
#define | WWDG_CFR_W0 ((uint16_t)0x0001)
#define | WWDG_CFR_W1 ((uint16_t)0x0002)
#define | WWDG_CFR_W2 ((uint16_t)0x0004)
#define | WWDG_CFR_W3 ((uint16_t)0x0008)
#define | WWDG_CFR_W4 ((uint16_t)0x0010)
#define | WWDG_CFR_W5 ((uint16_t)0x0020)
#define | WWDG_CFR_W6 ((uint16_t)0x0040)
#define | WWDG_CFR_WDGTB ((uint16_t)0x0180)
#define | WWDG_CFR_WDGTB0 ((uint16_t)0x0080)
#define | WWDG_CFR_WDGTB1 ((uint16_t)0x0100)
#define | WWDG_CR_T ((uint8_t)0x7F)
#define | WWDG_CR_T0 ((uint8_t)0x01)
#define | WWDG_CR_T1 ((uint8_t)0x02)
#define | WWDG_CR_T2 ((uint8_t)0x04)
#define | WWDG_CR_T3 ((uint8_t)0x08)
#define | WWDG_CR_T4 ((uint8_t)0x10)
#define | WWDG_CR_T5 ((uint8_t)0x20)
#define | WWDG_CR_T6 ((uint8_t)0x40)
#define | WWDG_CR_WDGA ((uint8_t)0x80)
#define | WWDG_SR_EWIF ((uint8_t)0x01)

Typedefs

typedef enum IRQn | IRQn_Type
STM32F10x Interrupt Number Definition, according to the selected device in Library_configuration_section.
typedef enum FlagStatus | ITStatus
typedef int16_t | s16
typedef int32_t | s32
typedef int8_t | s8
typedef const int16_t | sc16
typedef const int32_t | sc32
typedef const int8_t | sc8
typedef uint16_t | u16
typedef uint32_t | u32
typedef uint8_t | u8
typedef const uint16_t | uc16
typedef const uint32_t | uc32
typedef const uint8_t | uc8
typedef __IO int16_t | vs16
typedef __IO int32_t | vs32
typedef __IO int8_t | vs8
typedef __I int16_t | vsc16
typedef __I int32_t | vsc32
typedef __I int8_t | vsc8
typedef __IO uint16_t | vu16
typedef __IO uint32_t | vu32
typedef __IO uint8_t | vu8
typedef __I uint16_t | vuc16
typedef __I uint32_t | vuc32
typedef __I uint8_t | vuc8

Enumerations

enum | ErrorStatus { ERROR = 0, SUCCESS = !ERROR }
enum | FlagStatus { RESET = 0, SET = !RESET }
enum | FunctionalState { DISABLE = 0, ENABLE = !DISABLE }
enum IRQn {
NonMaskableInt_IRQn = -14, MemoryManagement_IRQn = -12, BusFault_IRQn = -11, UsageFault_IRQn = -10,
SVCall_IRQn = -5, DebugMonitor_IRQn = -4, PendSV_IRQn = -2, SysTick_IRQn = -1,
WWDG_IRQn = 0, PVD_IRQn = 1, TAMPER_IRQn = 2, RTC_IRQn = 3,
FLASH_IRQn = 4, RCC_IRQn = 5, EXTI0_IRQn = 6, EXTI1_IRQn = 7,
EXTI2_IRQn = 8, EXTI3_IRQn = 9, EXTI4_IRQn = 10, DMA1_Channel1_IRQn = 11,
DMA1_Channel2_IRQn = 12, DMA1_Channel3_IRQn = 13, DMA1_Channel4_IRQn = 14, DMA1_Channel5_IRQn = 15,
DMA1_Channel6_IRQn = 16, DMA1_Channel7_IRQn = 17
}

STM32F10x Interrupt Number Definition, according to the selected device in Library_configuration_section.

More...

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer Header File. This file contains all the peripheral register's definitions, bits definitions and memory mapping for STM32F10x Connectivity line, High density, High density value line, Medium density, Medium density Value line, Low density, Low density Value line and XL-density devices.

Author:
MCD Application Team
Version:
V3.5.0
Date:
11-March-2011 The file is the unique include file that the application programmer is using in the C source code, usually in main.c. This file contains:
  • Configuration section that allows to select:
    • The device used in the target application
    • To use or not the peripheral’s drivers in application code(i.e. code will be based on direct access to peripheral’s registers rather than drivers API), this option is controlled by "#define USE_STDPERIPH_DRIVER"
    • To change few application-specific parameters such as the HSE crystal frequency
  • Data structures and the address mapping for all peripherals
  • Peripheral's registers declarations and bits definition
  • Macros to access peripheral’s registers hardware
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm32f10x.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_adc.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Libraries
  • STM32F10x_StdPeriph_Driver
  • src
Defines | Functions

stm32f10x_adc.c File Reference

This file provides all the ADC firmware functions. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_rcc.h"

Go to the source code of this file.

Defines

#define | CR1_AWDCH_Reset ((uint32_t)0xFFFFFFE0)
#define | CR1_AWDMode_Reset ((uint32_t)0xFF3FFDFF)
#define | CR1_CLEAR_Mask ((uint32_t)0xFFF0FEFF)
#define | CR1_DISCEN_Reset ((uint32_t)0xFFFFF7FF)
#define | CR1_DISCEN_Set ((uint32_t)0x00000800)
#define | CR1_DISCNUM_Reset ((uint32_t)0xFFFF1FFF)
#define | CR1_JAUTO_Reset ((uint32_t)0xFFFFFBFF)
#define | CR1_JAUTO_Set ((uint32_t)0x00000400)
#define | CR1_JDISCEN_Reset ((uint32_t)0xFFFFEFFF)
#define | CR1_JDISCEN_Set ((uint32_t)0x00001000)
#define | CR2_ADON_Reset ((uint32_t)0xFFFFFFFE)
#define | CR2_ADON_Set ((uint32_t)0x00000001)
#define | CR2_CAL_Set ((uint32_t)0x00000004)
#define | CR2_CLEAR_Mask ((uint32_t)0xFFF1F7FD)
#define | CR2_DMA_Reset ((uint32_t)0xFFFFFEFF)
#define | CR2_DMA_Set ((uint32_t)0x00000100)
#define | CR2_EXTTRIG_Reset ((uint32_t)0xFFEFFFFF)
#define | CR2_EXTTRIG_Set ((uint32_t)0x00100000)
#define | CR2_EXTTRIG_SWSTART_Reset ((uint32_t)0xFFAFFFFF)
#define | CR2_EXTTRIG_SWSTART_Set ((uint32_t)0x00500000)
#define | CR2_JEXTSEL_Reset ((uint32_t)0xFFFF8FFF)
#define | CR2_JEXTTRIG_JSWSTART_Reset ((uint32_t)0xFFDF7FFF)
#define | CR2_JEXTTRIG_JSWSTART_Set ((uint32_t)0x00208000)
#define | CR2_JEXTTRIG_Reset ((uint32_t)0xFFFF7FFF)
#define | CR2_JEXTTRIG_Set ((uint32_t)0x00008000)
#define | CR2_JSWSTART_Set ((uint32_t)0x00200000)
#define | CR2_RSTCAL_Set ((uint32_t)0x00000008)
#define | CR2_SWSTART_Set ((uint32_t)0x00400000)
#define | CR2_TSVREFE_Reset ((uint32_t)0xFF7FFFFF)
#define | CR2_TSVREFE_Set ((uint32_t)0x00800000)
#define | DR_ADDRESS ((uint32_t)0x4001244C)
#define | JDR_Offset ((uint8_t)0x28)
#define | JSQR_JL_Reset ((uint32_t)0xFFCFFFFF)
#define | JSQR_JL_Set ((uint32_t)0x00300000)
#define | JSQR_JSQ_Set ((uint32_t)0x0000001F)
#define | SMPR1_SMP_Set ((uint32_t)0x00000007)
#define | SMPR2_SMP_Set ((uint32_t)0x00000007)
#define | SQR1_CLEAR_Mask ((uint32_t)0xFF0FFFFF)
#define | SQR1_SQ_Set ((uint32_t)0x0000001F)
#define | SQR2_SQ_Set ((uint32_t)0x0000001F)
#define | SQR3_SQ_Set ((uint32_t)0x0000001F)

Functions

void | ADC_AnalogWatchdogCmd (ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog)
Enables or disables the analog watchdog on single/all regular or injected channels.
void | ADC_AnalogWatchdogSingleChannelConfig (ADC_TypeDef *ADCx, uint8_t ADC_Channel)
Configures the analog watchdog guarded single channel.
void | ADC_AnalogWatchdogThresholdsConfig (ADC_TypeDef *ADCx, uint16_t HighThreshold, uint16_t LowThreshold)
Configures the high and low thresholds of the analog watchdog.
void | ADC_AutoInjectedConvCmd (ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the selected ADC automatic injected group conversion after regular one.
void | ADC_ClearFlag (ADC_TypeDef *ADCx, uint8_t ADC_FLAG)
Clears the ADCx's pending flags.
void | ADC_ClearITPendingBit (ADC_TypeDef *ADCx, uint16_t ADC_IT)
Clears the ADCx's interrupt pending bits.
void | ADC_Cmd (ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the specified ADC peripheral.
void | ADC_DeInit (ADC_TypeDef *ADCx)
Deinitializes the ADCx peripheral registers to their default reset values.
void | ADC_DiscModeChannelCountConfig (ADC_TypeDef *ADCx, uint8_t Number)
Configures the discontinuous mode for the selected ADC regular group channel.
void | ADC_DiscModeCmd (ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the discontinuous mode on regular group channel for the specified ADC.
void | ADC_DMACmd (ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the specified ADC DMA request.
void | ADC_ExternalTrigConvCmd (ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the ADCx conversion through external trigger.
void | ADC_ExternalTrigInjectedConvCmd (ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the ADCx injected channels conversion through external trigger.
void | ADC_ExternalTrigInjectedConvConfig (ADC_TypeDef *ADCx, uint32_t ADC_ExternalTrigInjecConv)
Configures the ADCx external trigger for injected channels conversion.
FlagStatus | ADC_GetCalibrationStatus (ADC_TypeDef *ADCx)
Gets the selected ADC calibration status.
uint16_t | ADC_GetConversionValue (ADC_TypeDef *ADCx)
Returns the last ADCx conversion result data for regular channel.
uint32_t | ADC_GetDualModeConversionValue (void)
Returns the last ADC1 and ADC2 conversion result data in dual mode.
FlagStatus | ADC_GetFlagStatus (ADC_TypeDef *ADCx, uint8_t ADC_FLAG)
Checks whether the specified ADC flag is set or not.
uint16_t | ADC_GetInjectedConversionValue (ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel)
Returns the ADC injected channel conversion result.
ITStatus | ADC_GetITStatus (ADC_TypeDef *ADCx, uint16_t ADC_IT)
Checks whether the specified ADC interrupt has occurred or not.
FlagStatus | ADC_GetResetCalibrationStatus (ADC_TypeDef *ADCx)
Gets the selected ADC reset calibration registers status.
FlagStatus | ADC_GetSoftwareStartConvStatus (ADC_TypeDef *ADCx)
Gets the selected ADC Software start conversion Status.
FlagStatus | ADC_GetSoftwareStartInjectedConvCmdStatus (ADC_TypeDef *ADCx)
Gets the selected ADC Software start injected conversion Status.
void | ADC_Init (ADC_TypeDef *ADCx, ADC_InitTypeDef *ADC_InitStruct)
Initializes the ADCx peripheral according to the specified parameters in the ADC_InitStruct.
void | ADC_InjectedChannelConfig (ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
Configures for the selected ADC injected channel its corresponding rank in the sequencer and its sample time.
void | ADC_InjectedDiscModeCmd (ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the discontinuous mode for injected group channel for the specified ADC.
void | ADC_InjectedSequencerLengthConfig (ADC_TypeDef *ADCx, uint8_t Length)
Configures the sequencer length for injected channels.
void | ADC_ITConfig (ADC_TypeDef *ADCx, uint16_t ADC_IT, FunctionalState NewState)
Enables or disables the specified ADC interrupts.
void | ADC_RegularChannelConfig (ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
Configures for the selected ADC regular channel its corresponding rank in the sequencer and its sample time.
void | ADC_ResetCalibration (ADC_TypeDef *ADCx)
Resets the selected ADC calibration registers.
void | ADC_SetInjectedOffset (ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset)
Set the injected channels conversion value offset.
void | ADC_SoftwareStartConvCmd (ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the selected ADC software start conversion .
void | ADC_SoftwareStartInjectedConvCmd (ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the selected ADC start of the injected channels conversion.
void | ADC_StartCalibration (ADC_TypeDef *ADCx)
Starts the selected ADC calibration process.
void | ADC_StructInit (ADC_InitTypeDef *ADC_InitStruct)
Fills each ADC_InitStruct member with its default value.
void | ADC_TempSensorVrefintCmd (FunctionalState NewState)
Enables or disables the temperature sensor and Vrefint channel.

Detailed Description

This file provides all the ADC firmware functions.

Author:
MCD Application Team
Version:
V3.5.0
Date:
11-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm32f10x_adc.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_adc.h File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
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  • inc
Data Structures | Defines | Functions

stm32f10x_adc.h File Reference

This file contains all the functions prototypes for the ADC firmware library. More...

#include "stm32f10x.h"

Go to the source code of this file.

Data Structures

struct | ADC_InitTypeDef
ADC Init structure definition. More...

Defines

#define | ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000)
#define | ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000)
#define | ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000)
#define | ADC_AnalogWatchdog_None ((uint32_t)0x00000000)
#define | ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200)
#define | ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200)
#define | ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200)
#define | ADC_Channel_0 ((uint8_t)0x00)
#define | ADC_Channel_1 ((uint8_t)0x01)
#define | ADC_Channel_10 ((uint8_t)0x0A)
#define | ADC_Channel_11 ((uint8_t)0x0B)
#define | ADC_Channel_12 ((uint8_t)0x0C)
#define | ADC_Channel_13 ((uint8_t)0x0D)
#define | ADC_Channel_14 ((uint8_t)0x0E)
#define | ADC_Channel_15 ((uint8_t)0x0F)
#define | ADC_Channel_16 ((uint8_t)0x10)
#define | ADC_Channel_17 ((uint8_t)0x11)
#define | ADC_Channel_2 ((uint8_t)0x02)
#define | ADC_Channel_3 ((uint8_t)0x03)
#define | ADC_Channel_4 ((uint8_t)0x04)
#define | ADC_Channel_5 ((uint8_t)0x05)
#define | ADC_Channel_6 ((uint8_t)0x06)
#define | ADC_Channel_7 ((uint8_t)0x07)
#define | ADC_Channel_8 ((uint8_t)0x08)
#define | ADC_Channel_9 ((uint8_t)0x09)
#define | ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16)
#define | ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17)
#define | ADC_DataAlign_Left ((uint32_t)0x00000800)
#define | ADC_DataAlign_Right ((uint32_t)0x00000000)
#define | ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO ((uint32_t)0x000C0000)
#define | ADC_ExternalTrigConv_None ((uint32_t)0x000E0000)
#define | ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000)
#define | ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00020000)
#define | ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x00040000)
#define | ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x00060000)
#define | ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x00020000)
#define | ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x00000000)
#define | ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x00080000)
#define | ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x000A0000)
#define | ADC_ExternalTrigConv_T5_CC1 ((uint32_t)0x000A0000)
#define | ADC_ExternalTrigConv_T5_CC3 ((uint32_t)0x000C0000)
#define | ADC_ExternalTrigConv_T8_CC1 ((uint32_t)0x00060000)
#define | ADC_ExternalTrigConv_T8_TRGO ((uint32_t)0x00080000)
#define | ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 ((uint32_t)0x00006000)
#define | ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000)
#define | ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00001000)
#define | ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00000000)
#define | ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00003000)
#define | ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00002000)
#define | ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00004000)
#define | ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00002000)
#define | ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00005000)
#define | ADC_ExternalTrigInjecConv_T5_CC4 ((uint32_t)0x00006000)
#define | ADC_ExternalTrigInjecConv_T5_TRGO ((uint32_t)0x00005000)
#define | ADC_ExternalTrigInjecConv_T8_CC2 ((uint32_t)0x00003000)
#define | ADC_ExternalTrigInjecConv_T8_CC4 ((uint32_t)0x00004000)
#define | ADC_FLAG_AWD ((uint8_t)0x01)
#define | ADC_FLAG_EOC ((uint8_t)0x02)
#define | ADC_FLAG_JEOC ((uint8_t)0x04)
#define | ADC_FLAG_JSTRT ((uint8_t)0x08)
#define | ADC_FLAG_STRT ((uint8_t)0x10)
#define | ADC_InjectedChannel_1 ((uint8_t)0x14)
#define | ADC_InjectedChannel_2 ((uint8_t)0x18)
#define | ADC_InjectedChannel_3 ((uint8_t)0x1C)
#define | ADC_InjectedChannel_4 ((uint8_t)0x20)
#define | ADC_IT_AWD ((uint16_t)0x0140)
#define | ADC_IT_EOC ((uint16_t)0x0220)
#define | ADC_IT_JEOC ((uint16_t)0x0480)
#define | ADC_Mode_AlterTrig ((uint32_t)0x00090000)
#define | ADC_Mode_FastInterl ((uint32_t)0x00070000)
#define | ADC_Mode_Independent ((uint32_t)0x00000000)
#define | ADC_Mode_InjecSimult ((uint32_t)0x00050000)
#define | ADC_Mode_InjecSimult_FastInterl ((uint32_t)0x00030000)
#define | ADC_Mode_InjecSimult_SlowInterl ((uint32_t)0x00040000)
#define | ADC_Mode_RegInjecSimult ((uint32_t)0x00010000)
#define | ADC_Mode_RegSimult ((uint32_t)0x00060000)
#define | ADC_Mode_RegSimult_AlterTrig ((uint32_t)0x00020000)
#define | ADC_Mode_SlowInterl ((uint32_t)0x00080000)
#define | ADC_SampleTime_13Cycles5 ((uint8_t)0x02)
#define | ADC_SampleTime_1Cycles5 ((uint8_t)0x00)
#define | ADC_SampleTime_239Cycles5 ((uint8_t)0x07)
#define | ADC_SampleTime_28Cycles5 ((uint8_t)0x03)
#define | ADC_SampleTime_41Cycles5 ((uint8_t)0x04)
#define | ADC_SampleTime_55Cycles5 ((uint8_t)0x05)
#define | ADC_SampleTime_71Cycles5 ((uint8_t)0x06)
#define | ADC_SampleTime_7Cycles5 ((uint8_t)0x01)
#define | IS_ADC_ALL_PERIPH(PERIPH)
#define | IS_ADC_ANALOG_WATCHDOG(WATCHDOG)
#define | IS_ADC_CHANNEL(CHANNEL)
#define | IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint8_t)0xE0) == 0x00) && ((FLAG) != 0x00))
#define | IS_ADC_DATA_ALIGN(ALIGN)
#define | IS_ADC_DMA_PERIPH(PERIPH)
#define | IS_ADC_EXT_INJEC_TRIG(INJTRIG)
#define | IS_ADC_EXT_TRIG(REGTRIG)
#define | IS_ADC_GET_FLAG(FLAG)
#define | IS_ADC_GET_IT(IT)
#define | IS_ADC_INJECTED_CHANNEL(CHANNEL)
#define | IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4))
#define | IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4))
#define | IS_ADC_IT(IT) ((((IT) & (uint16_t)0xF81F) == 0x00) && ((IT) != 0x00))
#define | IS_ADC_MODE(MODE)
#define | IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF)
#define | IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))
#define | IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10))
#define | IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10))
#define | IS_ADC_SAMPLE_TIME(TIME)
#define | IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF)

Functions

void | ADC_AnalogWatchdogCmd (ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog)
Enables or disables the analog watchdog on single/all regular or injected channels.
void | ADC_AnalogWatchdogSingleChannelConfig (ADC_TypeDef *ADCx, uint8_t ADC_Channel)
Configures the analog watchdog guarded single channel.
void | ADC_AnalogWatchdogThresholdsConfig (ADC_TypeDef *ADCx, uint16_t HighThreshold, uint16_t LowThreshold)
Configures the high and low thresholds of the analog watchdog.
void | ADC_AutoInjectedConvCmd (ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the selected ADC automatic injected group conversion after regular one.
void | ADC_ClearFlag (ADC_TypeDef *ADCx, uint8_t ADC_FLAG)
Clears the ADCx's pending flags.
void | ADC_ClearITPendingBit (ADC_TypeDef *ADCx, uint16_t ADC_IT)
Clears the ADCx's interrupt pending bits.
void | ADC_Cmd (ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the specified ADC peripheral.
void | ADC_DeInit (ADC_TypeDef *ADCx)
Deinitializes the ADCx peripheral registers to their default reset values.
void | ADC_DiscModeChannelCountConfig (ADC_TypeDef *ADCx, uint8_t Number)
Configures the discontinuous mode for the selected ADC regular group channel.
void | ADC_DiscModeCmd (ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the discontinuous mode on regular group channel for the specified ADC.
void | ADC_DMACmd (ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the specified ADC DMA request.
void | ADC_ExternalTrigConvCmd (ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the ADCx conversion through external trigger.
void | ADC_ExternalTrigInjectedConvCmd (ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the ADCx injected channels conversion through external trigger.
void | ADC_ExternalTrigInjectedConvConfig (ADC_TypeDef *ADCx, uint32_t ADC_ExternalTrigInjecConv)
Configures the ADCx external trigger for injected channels conversion.
FlagStatus | ADC_GetCalibrationStatus (ADC_TypeDef *ADCx)
Gets the selected ADC calibration status.
uint16_t | ADC_GetConversionValue (ADC_TypeDef *ADCx)
Returns the last ADCx conversion result data for regular channel.
uint32_t | ADC_GetDualModeConversionValue (void)
Returns the last ADC1 and ADC2 conversion result data in dual mode.
FlagStatus | ADC_GetFlagStatus (ADC_TypeDef *ADCx, uint8_t ADC_FLAG)
Checks whether the specified ADC flag is set or not.
uint16_t | ADC_GetInjectedConversionValue (ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel)
Returns the ADC injected channel conversion result.
ITStatus | ADC_GetITStatus (ADC_TypeDef *ADCx, uint16_t ADC_IT)
Checks whether the specified ADC interrupt has occurred or not.
FlagStatus | ADC_GetResetCalibrationStatus (ADC_TypeDef *ADCx)
Gets the selected ADC reset calibration registers status.
FlagStatus | ADC_GetSoftwareStartConvStatus (ADC_TypeDef *ADCx)
Gets the selected ADC Software start conversion Status.
FlagStatus | ADC_GetSoftwareStartInjectedConvCmdStatus (ADC_TypeDef *ADCx)
Gets the selected ADC Software start injected conversion Status.
void | ADC_Init (ADC_TypeDef *ADCx, ADC_InitTypeDef *ADC_InitStruct)
Initializes the ADCx peripheral according to the specified parameters in the ADC_InitStruct.
void | ADC_InjectedChannelConfig (ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
Configures for the selected ADC injected channel its corresponding rank in the sequencer and its sample time.
void | ADC_InjectedDiscModeCmd (ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the discontinuous mode for injected group channel for the specified ADC.
void | ADC_InjectedSequencerLengthConfig (ADC_TypeDef *ADCx, uint8_t Length)
Configures the sequencer length for injected channels.
void | ADC_ITConfig (ADC_TypeDef *ADCx, uint16_t ADC_IT, FunctionalState NewState)
Enables or disables the specified ADC interrupts.
void | ADC_RegularChannelConfig (ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
Configures for the selected ADC regular channel its corresponding rank in the sequencer and its sample time.
void | ADC_ResetCalibration (ADC_TypeDef *ADCx)
Resets the selected ADC calibration registers.
void | ADC_SetInjectedOffset (ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset)
Set the injected channels conversion value offset.
void | ADC_SoftwareStartConvCmd (ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the selected ADC software start conversion .
void | ADC_SoftwareStartInjectedConvCmd (ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the selected ADC start of the injected channels conversion.
void | ADC_StartCalibration (ADC_TypeDef *ADCx)
Starts the selected ADC calibration process.
void | ADC_StructInit (ADC_InitTypeDef *ADC_InitStruct)
Fills each ADC_InitStruct member with its default value.
void | ADC_TempSensorVrefintCmd (FunctionalState NewState)
Enables or disables the temperature sensor and Vrefint channel.

Detailed Description

This file contains all the functions prototypes for the ADC firmware library.

Author:
MCD Application Team
Version:
V3.5.0
Date:
11-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm32f10x_adc.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_bkp.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Libraries
  • STM32F10x_StdPeriph_Driver
  • src
Defines | Functions

stm32f10x_bkp.c File Reference

This file provides all the BKP firmware functions. More...

#include "stm32f10x_bkp.h"
#include "stm32f10x_rcc.h"

Go to the source code of this file.

Defines

#define | BKP_OFFSET (BKP_BASE - PERIPH_BASE)
#define | CR_OFFSET (BKP_OFFSET + 0x30)
#define | CR_TPAL_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPAL_BitNumber * 4))
#define | CR_TPE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPE_BitNumber * 4))
#define | CSR_OFFSET (BKP_OFFSET + 0x34)
#define | CSR_TEF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEF_BitNumber * 4))
#define | CSR_TIF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TIF_BitNumber * 4))
#define | CSR_TPIE_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TPIE_BitNumber * 4))
#define | RTCCR_CAL_MASK ((uint16_t)0xFF80)
#define | RTCCR_MASK ((uint16_t)0xFC7F)
#define | TEF_BitNumber 0x08
#define | TIF_BitNumber 0x09
#define | TPAL_BitNumber 0x01
#define | TPE_BitNumber 0x00
#define | TPIE_BitNumber 0x02

Functions

void | BKP_ClearFlag (void)
Clears Tamper Pin Event pending flag.
void | BKP_ClearITPendingBit (void)
Clears Tamper Pin Interrupt pending bit.
void | BKP_DeInit (void)
Deinitializes the BKP peripheral registers to their default reset values.
FlagStatus | BKP_GetFlagStatus (void)
Checks whether the Tamper Pin Event flag is set or not.
ITStatus | BKP_GetITStatus (void)
Checks whether the Tamper Pin Interrupt has occurred or not.
void | BKP_ITConfig (FunctionalState NewState)
Enables or disables the Tamper Pin Interrupt.
uint16_t | BKP_ReadBackupRegister (uint16_t BKP_DR)
Reads data from the specified Data Backup Register.
void | BKP_RTCOutputConfig (uint16_t BKP_RTCOutputSource)
Select the RTC output source to output on the Tamper pin.
void | BKP_SetRTCCalibrationValue (uint8_t CalibrationValue)
Sets RTC Clock Calibration value.
void | BKP_TamperPinCmd (FunctionalState NewState)
Enables or disables the Tamper Pin activation.
void | BKP_TamperPinLevelConfig (uint16_t BKP_TamperPinLevel)
Configures the Tamper Pin active level.
void | BKP_WriteBackupRegister (uint16_t BKP_DR, uint16_t Data)
Writes user data to the specified Data Backup Register.

Detailed Description

This file provides all the BKP firmware functions.

Author:
MCD Application Team
Version:
V3.5.0
Date:
11-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm32f10x_bkp.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_bkp.h File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Libraries
  • STM32F10x_StdPeriph_Driver
  • inc
Defines | Functions

stm32f10x_bkp.h File Reference

This file contains all the functions prototypes for the BKP firmware library. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | BKP_DR1 ((uint16_t)0x0004)
#define | BKP_DR10 ((uint16_t)0x0028)
#define | BKP_DR11 ((uint16_t)0x0040)
#define | BKP_DR12 ((uint16_t)0x0044)
#define | BKP_DR13 ((uint16_t)0x0048)
#define | BKP_DR14 ((uint16_t)0x004C)
#define | BKP_DR15 ((uint16_t)0x0050)
#define | BKP_DR16 ((uint16_t)0x0054)
#define | BKP_DR17 ((uint16_t)0x0058)
#define | BKP_DR18 ((uint16_t)0x005C)
#define | BKP_DR19 ((uint16_t)0x0060)
#define | BKP_DR2 ((uint16_t)0x0008)
#define | BKP_DR20 ((uint16_t)0x0064)
#define | BKP_DR21 ((uint16_t)0x0068)
#define | BKP_DR22 ((uint16_t)0x006C)
#define | BKP_DR23 ((uint16_t)0x0070)
#define | BKP_DR24 ((uint16_t)0x0074)
#define | BKP_DR25 ((uint16_t)0x0078)
#define | BKP_DR26 ((uint16_t)0x007C)
#define | BKP_DR27 ((uint16_t)0x0080)
#define | BKP_DR28 ((uint16_t)0x0084)
#define | BKP_DR29 ((uint16_t)0x0088)
#define | BKP_DR3 ((uint16_t)0x000C)
#define | BKP_DR30 ((uint16_t)0x008C)
#define | BKP_DR31 ((uint16_t)0x0090)
#define | BKP_DR32 ((uint16_t)0x0094)
#define | BKP_DR33 ((uint16_t)0x0098)
#define | BKP_DR34 ((uint16_t)0x009C)
#define | BKP_DR35 ((uint16_t)0x00A0)
#define | BKP_DR36 ((uint16_t)0x00A4)
#define | BKP_DR37 ((uint16_t)0x00A8)
#define | BKP_DR38 ((uint16_t)0x00AC)
#define | BKP_DR39 ((uint16_t)0x00B0)
#define | BKP_DR4 ((uint16_t)0x0010)
#define | BKP_DR40 ((uint16_t)0x00B4)
#define | BKP_DR41 ((uint16_t)0x00B8)
#define | BKP_DR42 ((uint16_t)0x00BC)
#define | BKP_DR5 ((uint16_t)0x0014)
#define | BKP_DR6 ((uint16_t)0x0018)
#define | BKP_DR7 ((uint16_t)0x001C)
#define | BKP_DR8 ((uint16_t)0x0020)
#define | BKP_DR9 ((uint16_t)0x0024)
#define | BKP_RTCOutputSource_Alarm ((uint16_t)0x0100)
#define | BKP_RTCOutputSource_CalibClock ((uint16_t)0x0080)
#define | BKP_RTCOutputSource_None ((uint16_t)0x0000)
#define | BKP_RTCOutputSource_Second ((uint16_t)0x0300)
#define | BKP_TamperPinLevel_High ((uint16_t)0x0000)
#define | BKP_TamperPinLevel_Low ((uint16_t)0x0001)
#define | IS_BKP_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x7F)
#define | IS_BKP_DR(DR)
#define | IS_BKP_RTC_OUTPUT_SOURCE(SOURCE)
#define | IS_BKP_TAMPER_PIN_LEVEL(LEVEL)

Functions

void | BKP_ClearFlag (void)
Clears Tamper Pin Event pending flag.
void | BKP_ClearITPendingBit (void)
Clears Tamper Pin Interrupt pending bit.
void | BKP_DeInit (void)
Deinitializes the BKP peripheral registers to their default reset values.
FlagStatus | BKP_GetFlagStatus (void)
Checks whether the Tamper Pin Event flag is set or not.
ITStatus | BKP_GetITStatus (void)
Checks whether the Tamper Pin Interrupt has occurred or not.
void | BKP_ITConfig (FunctionalState NewState)
Enables or disables the Tamper Pin Interrupt.
uint16_t | BKP_ReadBackupRegister (uint16_t BKP_DR)
Reads data from the specified Data Backup Register.
void | BKP_RTCOutputConfig (uint16_t BKP_RTCOutputSource)
Select the RTC output source to output on the Tamper pin.
void | BKP_SetRTCCalibrationValue (uint8_t CalibrationValue)
Sets RTC Clock Calibration value.
void | BKP_TamperPinCmd (FunctionalState NewState)
Enables or disables the Tamper Pin activation.
void | BKP_TamperPinLevelConfig (uint16_t BKP_TamperPinLevel)
Configures the Tamper Pin active level.
void | BKP_WriteBackupRegister (uint16_t BKP_DR, uint16_t Data)
Writes user data to the specified Data Backup Register.

Detailed Description

This file contains all the functions prototypes for the BKP firmware library.

Author:
MCD Application Team
Version:
V3.5.0
Date:
11-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm32f10x_bkp.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_can.c File Reference

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
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  • STM32F10x_StdPeriph_Driver
  • src
Defines | Functions

stm32f10x_can.c File Reference

This file provides all the CAN firmware functions. More...

#include "stm32f10x_can.h"
#include "stm32f10x_rcc.h"

Go to the source code of this file.

Defines

#define | CAN_FLAGS_ESR ((uint32_t)0x00F00000)
#define | CAN_FLAGS_MSR ((uint32_t)0x01000000)
#define | CAN_FLAGS_RF0R ((uint32_t)0x02000000)
#define | CAN_FLAGS_RF1R ((uint32_t)0x04000000)
#define | CAN_FLAGS_TSR ((uint32_t)0x08000000)
#define | CAN_MODE_MASK ((uint32_t) 0x00000003)
#define | CAN_TXMAILBOX_0 ((uint8_t)0x00)
#define | CAN_TXMAILBOX_1 ((uint8_t)0x01)
#define | CAN_TXMAILBOX_2 ((uint8_t)0x02)
#define | FMR_FINIT ((uint32_t)0x00000001)
#define | INAK_TIMEOUT ((uint32_t)0x0000FFFF)
#define | MCR_DBF ((uint32_t)0x00010000)
#define | SLAK_TIMEOUT ((uint32_t)0x0000FFFF)
#define | TMIDxR_TXRQ ((uint32_t)0x00000001)

Functions

void | CAN_CancelTransmit (CAN_TypeDef *CANx, uint8_t Mailbox)
Cancels a transmit request.
void | CAN_ClearFlag (CAN_TypeDef *CANx, uint32_t CAN_FLAG)
Clears the CAN's pending flags.
void | CAN_ClearITPendingBit (CAN_TypeDef *CANx, uint32_t CAN_IT)
Clears the CANx's interrupt pending bits.
void | CAN_DBGFreeze (CAN_TypeDef *CANx, FunctionalState NewState)
Enables or disables the DBG Freeze for CAN.
void | CAN_DeInit (CAN_TypeDef *CANx)
Deinitializes the CAN peripheral registers to their default reset values.
void | CAN_FIFORelease (CAN_TypeDef *CANx, uint8_t FIFONumber)
Releases the specified FIFO.
void | CAN_FilterInit (CAN_FilterInitTypeDef *CAN_FilterInitStruct)
Initializes the CAN peripheral according to the specified parameters in the CAN_FilterInitStruct.
FlagStatus | CAN_GetFlagStatus (CAN_TypeDef *CANx, uint32_t CAN_FLAG)
Checks whether the specified CAN flag is set or not.
ITStatus | CAN_GetITStatus (CAN_TypeDef *CANx, uint32_t CAN_IT)
Checks whether the specified CANx interrupt has occurred or not.
uint8_t | CAN_GetLastErrorCode (CAN_TypeDef *CANx)
Returns the CANx's last error code (LEC).
uint8_t | CAN_GetLSBTransmitErrorCounter (CAN_TypeDef *CANx)
Returns the LSB of the 9-bit CANx Transmit Error Counter(TEC).
uint8_t | CAN_GetReceiveErrorCounter (CAN_TypeDef *CANx)
Returns the CANx Receive Error Counter (REC).
uint8_t | CAN_Init (CAN_TypeDef *CANx, CAN_InitTypeDef *CAN_InitStruct)
Initializes the CAN peripheral according to the specified parameters in the CAN_InitStruct.
void | CAN_ITConfig (CAN_TypeDef *CANx, uint32_t CAN_IT, FunctionalState NewState)
Enables or disables the specified CANx interrupts.
uint8_t | CAN_MessagePending (CAN_TypeDef *CANx, uint8_t FIFONumber)
Returns the number of pending messages.
uint8_t | CAN_OperatingModeRequest (CAN_TypeDef *CANx, uint8_t CAN_OperatingMode)
Select the CAN Operation mode.
void | CAN_Receive (CAN_TypeDef *CANx, uint8_t FIFONumber, CanRxMsg *RxMessage)
Receives a message.
void | CAN_SlaveStartBank (uint8_t CAN_BankNumber)
Select the start bank filter for slave CAN.
uint8_t | CAN_Sleep (CAN_TypeDef *CANx)
Enters the low power mode.
void | CAN_StructInit (CAN_InitTypeDef *CAN_InitStruct)
Fills each CAN_InitStruct member with its default value.
uint8_t | CAN_Transmit (CAN_TypeDef *CANx, CanTxMsg *TxMessage)
Initiates the transmission of a message.
uint8_t | CAN_TransmitStatus (CAN_TypeDef *CANx, uint8_t TransmitMailbox)
Checks the transmission of a message.
void | CAN_TTComModeCmd (CAN_TypeDef *CANx, FunctionalState NewState)
Enables or disabes the CAN Time TriggerOperation communication mode.
uint8_t | CAN_WakeUp (CAN_TypeDef *CANx)
Wakes the CAN up.
static ITStatus | CheckITStatus (uint32_t CAN_Reg, uint32_t It_Bit)
Checks whether the CAN interrupt has occurred or not.

Detailed Description

This file provides all the CAN firmware functions.

Author:
MCD Application Team
Version:
V3.5.0
Date:
11-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm32f10x_can.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_can.h File Reference

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Libraries
  • STM32F10x_StdPeriph_Driver
  • inc
Data Structures | Defines | Functions

stm32f10x_can.h File Reference

This file contains all the functions prototypes for the CAN firmware library. More...

#include "stm32f10x.h"

Go to the source code of this file.

Data Structures

struct | CAN_FilterInitTypeDef
CAN filter init structure definition. More...
struct | CAN_InitTypeDef
CAN init structure definition. More...
struct | CanRxMsg
CAN Rx message structure definition. More...
struct | CanTxMsg
CAN Tx message structure definition. More...

Defines

#define | CAN_BS1_10tq ((uint8_t)0x09)
#define | CAN_BS1_11tq ((uint8_t)0x0A)
#define | CAN_BS1_12tq ((uint8_t)0x0B)
#define | CAN_BS1_13tq ((uint8_t)0x0C)
#define | CAN_BS1_14tq ((uint8_t)0x0D)
#define | CAN_BS1_15tq ((uint8_t)0x0E)
#define | CAN_BS1_16tq ((uint8_t)0x0F)
#define | CAN_BS1_1tq ((uint8_t)0x00)
#define | CAN_BS1_2tq ((uint8_t)0x01)
#define | CAN_BS1_3tq ((uint8_t)0x02)
#define | CAN_BS1_4tq ((uint8_t)0x03)
#define | CAN_BS1_5tq ((uint8_t)0x04)
#define | CAN_BS1_6tq ((uint8_t)0x05)
#define | CAN_BS1_7tq ((uint8_t)0x06)
#define | CAN_BS1_8tq ((uint8_t)0x07)
#define | CAN_BS1_9tq ((uint8_t)0x08)
#define | CAN_BS2_1tq ((uint8_t)0x00)
#define | CAN_BS2_2tq ((uint8_t)0x01)
#define | CAN_BS2_3tq ((uint8_t)0x02)
#define | CAN_BS2_4tq ((uint8_t)0x03)
#define | CAN_BS2_5tq ((uint8_t)0x04)
#define | CAN_BS2_6tq ((uint8_t)0x05)
#define | CAN_BS2_7tq ((uint8_t)0x06)
#define | CAN_BS2_8tq ((uint8_t)0x07)
#define | CAN_ErrorCode_ACKErr ((uint8_t)0x30)
#define | CAN_ErrorCode_BitDominantErr ((uint8_t)0x50)
#define | CAN_ErrorCode_BitRecessiveErr ((uint8_t)0x40)
#define | CAN_ErrorCode_CRCErr ((uint8_t)0x60)
#define | CAN_ErrorCode_FormErr ((uint8_t)0x20)
#define | CAN_ErrorCode_NoErr ((uint8_t)0x00)
#define | CAN_ErrorCode_SoftwareSetErr ((uint8_t)0x70)
#define | CAN_ErrorCode_StuffErr ((uint8_t)0x10)
#define | CAN_FIFO0 ((uint8_t)0x00)
#define | CAN_FIFO1 ((uint8_t)0x01)
#define | CAN_Filter_FIFO0 ((uint8_t)0x00)
#define | CAN_Filter_FIFO1 ((uint8_t)0x01)
#define | CAN_FilterFIFO0 CAN_Filter_FIFO0
#define | CAN_FilterFIFO1 CAN_Filter_FIFO1
#define | CAN_FilterMode_IdList ((uint8_t)0x01)
#define | CAN_FilterMode_IdMask ((uint8_t)0x00)
#define | CAN_FilterScale_16bit ((uint8_t)0x00)
#define | CAN_FilterScale_32bit ((uint8_t)0x01)
#define | CAN_FLAG_BOF ((uint32_t)0x10F00004)
#define | CAN_FLAG_EPV ((uint32_t)0x10F00002)
#define | CAN_FLAG_EWG ((uint32_t)0x10F00001)
#define | CAN_FLAG_FF0 ((uint32_t)0x32000008)
#define | CAN_FLAG_FF1 ((uint32_t)0x34000008)
#define | CAN_FLAG_FMP0 ((uint32_t)0x12000003)
#define | CAN_FLAG_FMP1 ((uint32_t)0x14000003)
#define | CAN_FLAG_FOV0 ((uint32_t)0x32000010)
#define | CAN_FLAG_FOV1 ((uint32_t)0x34000010)
#define | CAN_FLAG_LEC ((uint32_t)0x30F00070)
#define | CAN_FLAG_RQCP0 ((uint32_t)0x38000001)
#define | CAN_FLAG_RQCP1 ((uint32_t)0x38000100)
#define | CAN_FLAG_RQCP2 ((uint32_t)0x38010000)
#define | CAN_FLAG_SLAK ((uint32_t)0x31000012)
#define | CAN_FLAG_WKU ((uint32_t)0x31000008)
#define | CAN_ID_EXT CAN_Id_Extended
#define | CAN_Id_Extended ((uint32_t)0x00000004)
#define | CAN_Id_Standard ((uint32_t)0x00000000)
#define | CAN_ID_STD CAN_Id_Standard
#define | CAN_InitStatus_Failed ((uint8_t)0x00)
#define | CAN_InitStatus_Success ((uint8_t)0x01)
#define | CAN_IT_BOF ((uint32_t)0x00000400)
#define | CAN_IT_EPV ((uint32_t)0x00000200)
#define | CAN_IT_ERR ((uint32_t)0x00008000)
#define | CAN_IT_EWG ((uint32_t)0x00000100)
#define | CAN_IT_FF0 ((uint32_t)0x00000004)
#define | CAN_IT_FF1 ((uint32_t)0x00000020)
#define | CAN_IT_FMP0 ((uint32_t)0x00000002)
#define | CAN_IT_FMP1 ((uint32_t)0x00000010)
#define | CAN_IT_FOV0 ((uint32_t)0x00000008)
#define | CAN_IT_FOV1 ((uint32_t)0x00000040)
#define | CAN_IT_LEC ((uint32_t)0x00000800)
#define | CAN_IT_RQCP0 CAN_IT_TME
#define | CAN_IT_RQCP1 CAN_IT_TME
#define | CAN_IT_RQCP2 CAN_IT_TME
#define | CAN_IT_SLK ((uint32_t)0x00020000)
#define | CAN_IT_TME ((uint32_t)0x00000001)
#define | CAN_IT_WKU ((uint32_t)0x00010000)
#define | CAN_Mode_LoopBack ((uint8_t)0x01)
#define | CAN_Mode_Normal ((uint8_t)0x00)
#define | CAN_Mode_Silent ((uint8_t)0x02)
#define | CAN_Mode_Silent_LoopBack ((uint8_t)0x03)
#define | CAN_ModeStatus_Failed ((uint8_t)0x00)
#define | CAN_ModeStatus_Success ((uint8_t)!CAN_ModeStatus_Failed)
#define | CAN_NO_MB CAN_TxStatus_NoMailBox
#define | CAN_OperatingMode_Initialization ((uint8_t)0x00)
#define | CAN_OperatingMode_Normal ((uint8_t)0x01)
#define | CAN_OperatingMode_Sleep ((uint8_t)0x02)
#define | CAN_RTR_Data ((uint32_t)0x00000000)
#define | CAN_RTR_DATA CAN_RTR_Data
#define | CAN_RTR_Remote ((uint32_t)0x00000002)
#define | CAN_RTR_REMOTE CAN_RTR_Remote
#define | CAN_SJW_1tq ((uint8_t)0x00)
#define | CAN_SJW_2tq ((uint8_t)0x01)
#define | CAN_SJW_3tq ((uint8_t)0x02)
#define | CAN_SJW_4tq ((uint8_t)0x03)
#define | CAN_Sleep_Failed ((uint8_t)0x00)
#define | CAN_Sleep_Ok ((uint8_t)0x01)
#define | CAN_TxStatus_Failed ((uint8_t)0x00)
#define | CAN_TxStatus_NoMailBox ((uint8_t)0x04)
#define | CAN_TxStatus_Ok ((uint8_t)0x01)
#define | CAN_TxStatus_Pending ((uint8_t)0x02)
#define | CAN_WakeUp_Failed ((uint8_t)0x00)
#define | CAN_WakeUp_Ok ((uint8_t)0x01)
#define | CANINITFAILED CAN_InitStatus_Failed
#define | CANINITOK CAN_InitStatus_Success
#define | CANSLEEPFAILED CAN_Sleep_Failed
#define | CANSLEEPOK CAN_Sleep_Ok
#define | CANTXFAILE CAN_TxStatus_Failed
#define | CANTXOK CAN_TxStatus_Ok
#define | CANTXPENDING CAN_TxStatus_Pending
#define | CANWAKEUPFAILED CAN_WakeUp_Failed
#define | CANWAKEUPOK CAN_WakeUp_Ok
#define | IS_CAN_ALL_PERIPH(PERIPH)
#define | IS_CAN_BANKNUMBER(BANKNUMBER) (((BANKNUMBER) >= 1) && ((BANKNUMBER) <= 27))
#define | IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16tq)
#define | IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8tq)
#define | IS_CAN_CLEAR_FLAG(FLAG)
#define | IS_CAN_CLEAR_IT(IT)
#define | IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08))
#define | IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF))
#define | IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
#define | IS_CAN_FILTER_FIFO(FIFO)
#define | IS_CAN_FILTER_MODE(MODE)
#define | IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 13)
#define | IS_CAN_FILTER_SCALE(SCALE)
#define | IS_CAN_GET_FLAG(FLAG)
#define | IS_CAN_IDTYPE(IDTYPE)
#define | IS_CAN_IT(IT)
#define | IS_CAN_MODE(MODE)
#define | IS_CAN_OPERATING_MODE(MODE)
#define | IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))
#define | IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_Data) || ((RTR) == CAN_RTR_Remote))
#define | IS_CAN_SJW(SJW)
#define | IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF))
#define | IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))

Functions

void | CAN_CancelTransmit (CAN_TypeDef *CANx, uint8_t Mailbox)
Cancels a transmit request.
void | CAN_ClearFlag (CAN_TypeDef *CANx, uint32_t CAN_FLAG)
Clears the CAN's pending flags.
void | CAN_ClearITPendingBit (CAN_TypeDef *CANx, uint32_t CAN_IT)
Clears the CANx's interrupt pending bits.
void | CAN_DBGFreeze (CAN_TypeDef *CANx, FunctionalState NewState)
Enables or disables the DBG Freeze for CAN.
void | CAN_DeInit (CAN_TypeDef *CANx)
Deinitializes the CAN peripheral registers to their default reset values.
void | CAN_FIFORelease (CAN_TypeDef *CANx, uint8_t FIFONumber)
Releases the specified FIFO.
void | CAN_FilterInit (CAN_FilterInitTypeDef *CAN_FilterInitStruct)
Initializes the CAN peripheral according to the specified parameters in the CAN_FilterInitStruct.
FlagStatus | CAN_GetFlagStatus (CAN_TypeDef *CANx, uint32_t CAN_FLAG)
Checks whether the specified CAN flag is set or not.
ITStatus | CAN_GetITStatus (CAN_TypeDef *CANx, uint32_t CAN_IT)
Checks whether the specified CANx interrupt has occurred or not.
uint8_t | CAN_GetLastErrorCode (CAN_TypeDef *CANx)
Returns the CANx's last error code (LEC).
uint8_t | CAN_GetLSBTransmitErrorCounter (CAN_TypeDef *CANx)
Returns the LSB of the 9-bit CANx Transmit Error Counter(TEC).
uint8_t | CAN_GetReceiveErrorCounter (CAN_TypeDef *CANx)
Returns the CANx Receive Error Counter (REC).
uint8_t | CAN_Init (CAN_TypeDef *CANx, CAN_InitTypeDef *CAN_InitStruct)
Initializes the CAN peripheral according to the specified parameters in the CAN_InitStruct.
void | CAN_ITConfig (CAN_TypeDef *CANx, uint32_t CAN_IT, FunctionalState NewState)
Enables or disables the specified CANx interrupts.
uint8_t | CAN_MessagePending (CAN_TypeDef *CANx, uint8_t FIFONumber)
Returns the number of pending messages.
uint8_t | CAN_OperatingModeRequest (CAN_TypeDef *CANx, uint8_t CAN_OperatingMode)
Select the CAN Operation mode.
void | CAN_Receive (CAN_TypeDef *CANx, uint8_t FIFONumber, CanRxMsg *RxMessage)
Receives a message.
void | CAN_SlaveStartBank (uint8_t CAN_BankNumber)
Select the start bank filter for slave CAN.
uint8_t | CAN_Sleep (CAN_TypeDef *CANx)
Enters the low power mode.
void | CAN_StructInit (CAN_InitTypeDef *CAN_InitStruct)
Fills each CAN_InitStruct member with its default value.
uint8_t | CAN_Transmit (CAN_TypeDef *CANx, CanTxMsg *TxMessage)
Initiates the transmission of a message.
uint8_t | CAN_TransmitStatus (CAN_TypeDef *CANx, uint8_t TransmitMailbox)
Checks the transmission of a message.
void | CAN_TTComModeCmd (CAN_TypeDef *CANx, FunctionalState NewState)
Enables or disabes the CAN Time TriggerOperation communication mode.
uint8_t | CAN_WakeUp (CAN_TypeDef *CANx)
Wakes the CAN up.

Detailed Description

This file contains all the functions prototypes for the CAN firmware library.

Author:
MCD Application Team
Version:
V3.5.0
Date:
11-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm32f10x_can.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_cec.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Libraries
  • STM32F10x_StdPeriph_Driver
  • src
Defines | Functions

stm32f10x_cec.c File Reference

This file provides all the CEC firmware functions. More...

#include "stm32f10x_cec.h"
#include "stm32f10x_rcc.h"

Go to the source code of this file.

Defines

#define | CEC_OFFSET (CEC_BASE - PERIPH_BASE)
#define | CFGR_CLEAR_Mask (uint8_t)(0xF3)
#define | CFGR_IE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (IE_BitNumber * 4))
#define | CFGR_OFFSET (CEC_OFFSET + 0x00)
#define | CFGR_PE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (PE_BitNumber * 4))
#define | CSR_OFFSET (CEC_OFFSET + 0x10)
#define | CSR_TEOM_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEOM_BitNumber * 4))
#define | CSR_TSOM_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TSOM_BitNumber * 4))
#define | FLAG_Mask ((uint32_t)0x00FFFFFF)
#define | IE_BitNumber 0x01
#define | PE_BitNumber 0x00
#define | TEOM_BitNumber 0x01
#define | TSOM_BitNumber 0x00

Functions

void | CEC_ClearFlag (uint32_t CEC_FLAG)
Clears the CEC's pending flags.
void | CEC_ClearITPendingBit (uint16_t CEC_IT)
Clears the CEC's interrupt pending bits.
void | CEC_Cmd (FunctionalState NewState)
Enables or disables the specified CEC peripheral.
void | CEC_DeInit (void)
Deinitializes the CEC peripheral registers to their default reset values.
void | CEC_EndOfMessageCmd (FunctionalState NewState)
Transmits message with or without an EOM bit.
FlagStatus | CEC_GetFlagStatus (uint32_t CEC_FLAG)
Gets the CEC flag status.
ITStatus | CEC_GetITStatus (uint8_t CEC_IT)
Checks whether the specified CEC interrupt has occurred or not.
void | CEC_Init (CEC_InitTypeDef *CEC_InitStruct)
Initializes the CEC peripheral according to the specified parameters in the CEC_InitStruct.
void | CEC_ITConfig (FunctionalState NewState)
Enables or disables the CEC interrupt.
void | CEC_OwnAddressConfig (uint8_t CEC_OwnAddress)
Defines the Own Address of the CEC device.
uint8_t | CEC_ReceiveDataByte (void)
Returns the most recent received data by the CEC peripheral.
void | CEC_SendDataByte (uint8_t Data)
Transmits single data through the CEC peripheral.
void | CEC_SetPrescaler (uint16_t CEC_Prescaler)
Sets the CEC prescaler value.
void | CEC_StartOfMessage (void)
Starts a new message.

Detailed Description

This file provides all the CEC firmware functions.

Author:
MCD Application Team
Version:
V3.5.0
Date:
11-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm32f10x_cec.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_cec.h File Reference

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Libraries
  • STM32F10x_StdPeriph_Driver
  • inc
Data Structures | Defines | Functions

stm32f10x_cec.h File Reference

This file contains all the functions prototypes for the CEC firmware library. More...

#include "stm32f10x.h"

Go to the source code of this file.

Data Structures

struct | CEC_InitTypeDef
CEC Init structure definition. More...

Defines

#define | CEC_BitPeriodFlexibleMode CEC_CFGR_BPEM
#define | CEC_BitPeriodStdMode ((uint16_t)0x00)
#define | CEC_BitTimingErrFreeMode CEC_CFGR_BTEM
#define | CEC_BitTimingStdMode ((uint16_t)0x00)
#define | CEC_FLAG_ACKE ((uint32_t)0x10100000)
#define | CEC_FLAG_BPE ((uint32_t)0x10020000)
#define | CEC_FLAG_BTE ((uint32_t)0x10010000)
ESR register flags.
#define | CEC_FLAG_LINE ((uint32_t)0x10200000)
#define | CEC_FLAG_RBTF ((uint32_t)0x00000080)
#define | CEC_FLAG_RBTFE ((uint32_t)0x10040000)
#define | CEC_FLAG_REOM ((uint32_t)0x00000020)
#define | CEC_FLAG_RERR ((uint32_t)0x00000040)
#define | CEC_FLAG_RSOM ((uint32_t)0x00000010)
#define | CEC_FLAG_SBE ((uint32_t)0x10080000)
#define | CEC_FLAG_TBTFE ((uint32_t)0x10400000)
#define | CEC_FLAG_TBTRF ((uint32_t)0x00000008)
#define | CEC_FLAG_TEOM ((uint32_t)0x00000002)
CSR register flags.
#define | CEC_FLAG_TERR ((uint32_t)0x00000004)
#define | CEC_IT_RBTF CEC_CSR_RBTF
#define | CEC_IT_RERR CEC_CSR_RERR
#define | CEC_IT_TBTRF CEC_CSR_TBTRF
#define | CEC_IT_TERR CEC_CSR_TERR
#define | IS_CEC_ADDRESS(ADDRESS) ((ADDRESS) < 0x10)
#define | IS_CEC_BIT_PERIOD_ERROR_MODE(MODE)
#define | IS_CEC_BIT_TIMING_ERROR_MODE(MODE)
#define | IS_CEC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFF03) == 0x00) && ((FLAG) != 0x00))
#define | IS_CEC_GET_FLAG(FLAG)
#define | IS_CEC_GET_IT(IT)
#define | IS_CEC_PRESCALER(PRESCALER) ((PRESCALER) <= 0x3FFF)

Functions

void | CEC_ClearFlag (uint32_t CEC_FLAG)
Clears the CEC's pending flags.
void | CEC_ClearITPendingBit (uint16_t CEC_IT)
Clears the CEC's interrupt pending bits.
void | CEC_Cmd (FunctionalState NewState)
Enables or disables the specified CEC peripheral.
void | CEC_DeInit (void)
Deinitializes the CEC peripheral registers to their default reset values.
void | CEC_EndOfMessageCmd (FunctionalState NewState)
Transmits message with or without an EOM bit.
FlagStatus | CEC_GetFlagStatus (uint32_t CEC_FLAG)
Gets the CEC flag status.
ITStatus | CEC_GetITStatus (uint8_t CEC_IT)
Checks whether the specified CEC interrupt has occurred or not.
void | CEC_Init (CEC_InitTypeDef *CEC_InitStruct)
Initializes the CEC peripheral according to the specified parameters in the CEC_InitStruct.
void | CEC_ITConfig (FunctionalState NewState)
Enables or disables the CEC interrupt.
void | CEC_OwnAddressConfig (uint8_t CEC_OwnAddress)
Defines the Own Address of the CEC device.
uint8_t | CEC_ReceiveDataByte (void)
Returns the most recent received data by the CEC peripheral.
void | CEC_SendDataByte (uint8_t Data)
Transmits single data through the CEC peripheral.
void | CEC_SetPrescaler (uint16_t CEC_Prescaler)
Sets the CEC prescaler value.
void | CEC_StartOfMessage (void)
Starts a new message.

Detailed Description

This file contains all the functions prototypes for the CEC firmware library.

Author:
MCD Application Team
Version:
V3.5.0
Date:
11-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm32f10x_cec.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
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  • STM32F10x_StdPeriph_Examples
  • ADC
  • 3ADCs_DMA
Defines

STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 72 of file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_conf.h.

Referenced by ADC_AnalogWatchdogCmd(), ADC_AnalogWatchdogSingleChannelConfig(), ADC_AnalogWatchdogThresholdsConfig(), ADC_AutoInjectedConvCmd(), ADC_ClearFlag(), ADC_ClearITPendingBit(), ADC_Cmd(), ADC_DeInit(), ADC_DiscModeChannelCountConfig(), ADC_DiscModeCmd(), ADC_DMACmd(), ADC_ExternalTrigConvCmd(), ADC_ExternalTrigInjectedConvCmd(), ADC_ExternalTrigInjectedConvConfig(), ADC_GetCalibrationStatus(), ADC_GetConversionValue(), ADC_GetFlagStatus(), ADC_GetInjectedConversionValue(), ADC_GetITStatus(), ADC_GetResetCalibrationStatus(), ADC_GetSoftwareStartConvStatus(), ADC_GetSoftwareStartInjectedConvCmdStatus(), ADC_Init(), ADC_InjectedChannelConfig(), ADC_InjectedDiscModeCmd(), ADC_InjectedSequencerLengthConfig(), ADC_ITConfig(), ADC_RegularChannelConfig(), ADC_ResetCalibration(), ADC_SetInjectedOffset(), ADC_SoftwareStartConvCmd(), ADC_SoftwareStartInjectedConvCmd(), ADC_StartCalibration(), ADC_TempSensorVrefintCmd(), BKP_ITConfig(), BKP_ReadBackupRegister(), BKP_RTCOutputConfig(), BKP_SetRTCCalibrationValue(), BKP_TamperPinCmd(), BKP_TamperPinLevelConfig(), BKP_WriteBackupRegister(), CAN_CancelTransmit(), CAN_ClearFlag(), CAN_ClearITPendingBit(), CAN_DBGFreeze(), CAN_DeInit(), CAN_FIFORelease(), CAN_FilterInit(), CAN_GetFlagStatus(), CAN_GetITStatus(), CAN_GetLastErrorCode(), CAN_GetLSBTransmitErrorCounter(), CAN_GetReceiveErrorCounter(), CAN_Init(), CAN_ITConfig(), CAN_MessagePending(), CAN_OperatingModeRequest(), CAN_Receive(), CAN_SlaveStartBank(), CAN_Sleep(), CAN_Transmit(), CAN_TransmitStatus(), CAN_TTComModeCmd(), CAN_WakeUp(), CEC_ClearFlag(), CEC_ClearITPendingBit(), CEC_Cmd(), CEC_EndOfMessageCmd(), CEC_GetFlagStatus(), CEC_GetITStatus(), CEC_Init(), CEC_ITConfig(), CEC_OwnAddressConfig(), CEC_SetPrescaler(), DAC_Cmd(), DAC_DMACmd(), DAC_DualSoftwareTriggerCmd(), DAC_GetDataOutputValue(), DAC_Init(), DAC_SetChannel1Data(), DAC_SetChannel2Data(), DAC_SetDualChannelData(), DAC_SoftwareTriggerCmd(), DAC_WaveGenerationCmd(), DBGMCU_Config(), DMA_ClearFlag(), DMA_ClearITPendingBit(), DMA_Cmd(), DMA_DeInit(), DMA_GetCurrDataCounter(), DMA_GetFlagStatus(), DMA_GetITStatus(), DMA_Init(), DMA_ITConfig(), DMA_SetCurrDataCounter(), EXTI_ClearFlag(), EXTI_ClearITPendingBit(), EXTI_GenerateSWInterrupt(), EXTI_GetFlagStatus(), EXTI_GetITStatus(), EXTI_Init(), FLASH_ClearFlag(), FLASH_EnableWriteProtection(), FLASH_ErasePage(), FLASH_GetFlagStatus(), FLASH_HalfCycleAccessCmd(), FLASH_ITConfig(), FLASH_PrefetchBufferCmd(), FLASH_ProgramHalfWord(), FLASH_ProgramOptionByteData(), FLASH_ProgramWord(), FLASH_ReadOutProtection(), FLASH_SetLatency(), FLASH_UserOptionByteConfig(), FSMC_ClearFlag(), FSMC_ClearITPendingBit(), FSMC_GetFlagStatus(), FSMC_GetITStatus(), FSMC_ITConfig(), FSMC_NANDCmd(), FSMC_NANDDeInit(), FSMC_NANDECCCmd(), FSMC_NANDInit(), FSMC_NORSRAMCmd(), FSMC_NORSRAMDeInit(), FSMC_NORSRAMInit(), FSMC_PCCARDCmd(), FSMC_PCCARDInit(), GPIO_DeInit(), GPIO_ETH_MediaInterfaceConfig(), GPIO_EventOutputCmd(), GPIO_EventOutputConfig(), GPIO_EXTILineConfig(), GPIO_Init(), GPIO_PinLockConfig(), GPIO_PinRemapConfig(), GPIO_ReadInputData(), GPIO_ReadInputDataBit(), GPIO_ReadOutputData(), GPIO_ReadOutputDataBit(), GPIO_ResetBits(), GPIO_SetBits(), GPIO_Write(), GPIO_WriteBit(), I2C_AcknowledgeConfig(), I2C_ARPCmd(), I2C_CalculatePEC(), I2C_CheckEvent(), I2C_ClearFlag(), I2C_ClearITPendingBit(), I2C_Cmd(), I2C_DeInit(), I2C_DMACmd(), I2C_DMALastTransferCmd(), I2C_DualAddressCmd(), I2C_FastModeDutyCycleConfig(), I2C_GeneralCallCmd(), I2C_GenerateSTART(), I2C_GenerateSTOP(), I2C_GetFlagStatus(), I2C_GetITStatus(), I2C_GetLastEvent(), I2C_GetPEC(), I2C_Init(), I2C_ITConfig(), I2C_NACKPositionConfig(), I2C_OwnAddress2Config(), I2C_PECPositionConfig(), I2C_ReadRegister(), I2C_ReceiveData(), I2C_Send7bitAddress(), I2C_SendData(), I2C_SMBusAlertConfig(), I2C_SoftwareResetCmd(), I2C_StretchClockCmd(), I2C_TransmitPEC(), I2S_Cmd(), I2S_Init(), IWDG_GetFlagStatus(), IWDG_SetPrescaler(), IWDG_SetReload(), IWDG_WriteAccessCmd(), NVIC_Init(), NVIC_PriorityGroupConfig(), NVIC_SetVectorTable(), NVIC_SystemLPConfig(), PWR_BackupAccessCmd(), PWR_ClearFlag(), PWR_EnterSTOPMode(), PWR_GetFlagStatus(), PWR_PVDCmd(), PWR_PVDLevelConfig(), PWR_WakeUpPinCmd(), RCC_ADCCLKConfig(), RCC_AdjustHSICalibrationValue(), RCC_AHBPeriphClockCmd(), RCC_APB1PeriphClockCmd(), RCC_APB1PeriphResetCmd(), RCC_APB2PeriphClockCmd(), RCC_APB2PeriphResetCmd(), RCC_BackupResetCmd(), RCC_ClearITPendingBit(), RCC_ClockSecuritySystemCmd(), RCC_GetFlagStatus(), RCC_GetITStatus(), RCC_HCLKConfig(), RCC_HSEConfig(), RCC_HSICmd(), RCC_ITConfig(), RCC_LSEConfig(), RCC_LSICmd(), RCC_MCOConfig(), RCC_PCLK1Config(), RCC_PCLK2Config(), RCC_PLLCmd(), RCC_PLLConfig(), RCC_RTCCLKCmd(), RCC_RTCCLKConfig(), RCC_SYSCLKConfig(), RCC_USBCLKConfig(), RTC_ClearFlag(), RTC_ClearITPendingBit(), RTC_GetFlagStatus(), RTC_GetITStatus(), RTC_ITConfig(), RTC_SetPrescaler(), SDIO_CEATAITCmd(), SDIO_ClearFlag(), SDIO_ClearITPendingBit(), SDIO_ClockCmd(), SDIO_CommandCompletionCmd(), SDIO_DataConfig(), SDIO_DMACmd(), SDIO_GetFlagStatus(), SDIO_GetITStatus(), SDIO_GetResponse(), SDIO_Init(), SDIO_ITConfig(), SDIO_SendCEATACmd(), SDIO_SendCommand(), SDIO_SendSDIOSuspendCmd(), SDIO_SetPowerState(), SDIO_SetSDIOOperation(), SDIO_SetSDIOReadWaitMode(), SDIO_StartSDIOReadWait(), SDIO_StopSDIOReadWait(), SPI_BiDirectionalLineConfig(), SPI_CalculateCRC(), SPI_Cmd(), SPI_DataSizeConfig(), SPI_GetCRC(), SPI_GetCRCPolynomial(), SPI_I2S_ClearFlag(), SPI_I2S_ClearITPendingBit(), SPI_I2S_DeInit(), SPI_I2S_DMACmd(), SPI_I2S_GetFlagStatus(), SPI_I2S_GetITStatus(), SPI_I2S_ITConfig(), SPI_I2S_ReceiveData(), SPI_I2S_SendData(), SPI_Init(), SPI_NSSInternalSoftwareConfig(), SPI_SSOutputCmd(), SPI_TransmitCRC(), SysTick_CLKSourceConfig(), TIM_ARRPreloadConfig(), TIM_BDTRConfig(), TIM_CCPreloadControl(), TIM_CCxCmd(), TIM_CCxNCmd(), TIM_ClearFlag(), TIM_ClearITPendingBit(), TIM_ClearOC1Ref(), TIM_ClearOC2Ref(), TIM_ClearOC3Ref(), TIM_ClearOC4Ref(), TIM_Cmd(), TIM_CounterModeConfig(), TIM_CtrlPWMOutputs(), TIM_DeInit(), TIM_DMACmd(), TIM_DMAConfig(), TIM_EncoderInterfaceConfig(), TIM_ETRClockMode1Config(), TIM_ETRClockMode2Config(), TIM_ETRConfig(), TIM_ForcedOC1Config(), TIM_ForcedOC2Config(), TIM_ForcedOC3Config(), TIM_ForcedOC4Config(), TIM_GenerateEvent(), TIM_GetCapture1(), TIM_GetCapture2(), TIM_GetCapture3(), TIM_GetCapture4(), TIM_GetCounter(), TIM_GetFlagStatus(), TIM_GetITStatus(), TIM_GetPrescaler(), TIM_ICInit(), TIM_InternalClockConfig(), TIM_ITConfig(), TIM_ITRxExternalClockConfig(), TIM_OC1FastConfig(), TIM_OC1Init(), TIM_OC1NPolarityConfig(), TIM_OC1PolarityConfig(), TIM_OC1PreloadConfig(), TIM_OC2FastConfig(), TIM_OC2Init(), TIM_OC2NPolarityConfig(), TIM_OC2PolarityConfig(), TIM_OC2PreloadConfig(), TIM_OC3FastConfig(), TIM_OC3Init(), TIM_OC3NPolarityConfig(), TIM_OC3PolarityConfig(), TIM_OC3PreloadConfig(), TIM_OC4FastConfig(), TIM_OC4Init(), TIM_OC4PolarityConfig(), TIM_OC4PreloadConfig(), TIM_PrescalerConfig(), TIM_PWMIConfig(), TIM_SelectCCDMA(), TIM_SelectCOM(), TIM_SelectHallSensor(), TIM_SelectInputTrigger(), TIM_SelectMasterSlaveMode(), TIM_SelectOCxM(), TIM_SelectOnePulseMode(), TIM_SelectOutputTrigger(), TIM_SelectSlaveMode(), TIM_SetAutoreload(), TIM_SetClockDivision(), TIM_SetCompare1(), TIM_SetCompare2(), TIM_SetCompare3(), TIM_SetCompare4(), TIM_SetCounter(), TIM_SetIC1Prescaler(), TIM_SetIC2Prescaler(), TIM_SetIC3Prescaler(), TIM_SetIC4Prescaler(), TIM_TimeBaseInit(), TIM_TIxExternalClockConfig(), TIM_UpdateDisableConfig(), TIM_UpdateRequestConfig(), USART_ClearFlag(), USART_ClearITPendingBit(), USART_ClockInit(), USART_Cmd(), USART_DeInit(), USART_DMACmd(), USART_GetFlagStatus(), USART_GetITStatus(), USART_HalfDuplexCmd(), USART_Init(), USART_IrDACmd(), USART_IrDAConfig(), USART_ITConfig(), USART_LINBreakDetectLengthConfig(), USART_LINCmd(), USART_OneBitMethodCmd(), USART_OverSampling8Cmd(), USART_ReceiveData(), USART_ReceiverWakeUpCmd(), USART_SendBreak(), USART_SendData(), USART_SetAddress(), USART_SetGuardTime(), USART_SetPrescaler(), USART_SmartCardCmd(), USART_SmartCardNACKCmd(), USART_WakeUpConfig(), WWDG_Enable(), WWDG_SetCounter(), WWDG_SetPrescaler(), and WWDG_SetWindowValue().


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • ADC
  • ADC1_DMA
Defines

STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 72 of file STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • ADC
  • AnalogWatchdog
Defines

STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 72 of file STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • ADC
  • ExtLinesTrigger
Defines

STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 72 of file STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • ADC
  • RegSimul_DualMode
Defines

STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 72 of file STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • ADC
  • TIMTrigger_AutoInjection
Defines

STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 72 of file STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

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  • Project
  • STM32F10x_StdPeriph_Examples
  • BKP
  • Backup_Data
Defines

STM32F10x_StdPeriph_Examples/BKP/Backup_Data/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/BKP/Backup_Data/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 72 of file STM32F10x_StdPeriph_Examples/BKP/Backup_Data/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • BKP
  • Tamper
Defines

STM32F10x_StdPeriph_Examples/BKP/Tamper/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/BKP/Tamper/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 72 of file STM32F10x_StdPeriph_Examples/BKP/Tamper/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • CAN
  • DualCAN
Defines

STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 72 of file STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • CAN
  • LoopBack
Defines

STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 72 of file STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • CAN
  • Networking
Defines

STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 72 of file STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • CEC
  • DataExchangeInterrupt
Defines

STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0)
#define | CEC_DEVICE1 1
#define | FOLLOWER 0x02
#define | MY_DEVICE_ADDRESS 0x01

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 89 of file STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_conf.h.

#define CEC_DEVICE1 1

Definition at line 59 of file STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_conf.h.

#define FOLLOWER 0x02

Definition at line 67 of file STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_conf.h.

Referenced by EXTI9_5_IRQHandler().

#define MY_DEVICE_ADDRESS 0x01

Definition at line 64 of file STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_conf.h.

Referenced by EXTI9_5_IRQHandler(), and main().


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

  • File List
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  • Project
  • STM32F10x_StdPeriph_Examples
  • CortexM3
  • BitBand
Defines

STM32F10x_StdPeriph_Examples/CortexM3/BitBand/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/CortexM3/BitBand/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 71 of file STM32F10x_StdPeriph_Examples/CortexM3/BitBand/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

  • File List
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  • Project
  • STM32F10x_StdPeriph_Examples
  • CortexM3
  • Mode_Privilege
Defines

STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 71 of file STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • CortexM3
  • MPU
Defines

STM32F10x_StdPeriph_Examples/CortexM3/MPU/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/CortexM3/MPU/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 71 of file STM32F10x_StdPeriph_Examples/CortexM3/MPU/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

  • File List
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  • CRC_Calculation
Defines

STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 72 of file STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

  • File List
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  • DualModeDMA_SineWave
Defines

STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 72 of file STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

  • File List
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  • Project
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  • OneChannel_NoiseWave
Defines

STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 72 of file STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

  • File List
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  • Project
  • STM32F10x_StdPeriph_Examples
  • DAC
  • OneChannelDMA_Escalator
Defines

STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 72 of file STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

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  • Project
  • STM32F10x_StdPeriph_Examples
  • DAC
  • TwoChannels_TriangleWave
Defines

STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 72 of file STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • DMA
  • ADC_TIM1
Defines

STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 72 of file STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

  • File List
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  • Project
  • STM32F10x_StdPeriph_Examples
  • DMA
  • FLASH_RAM
Defines

STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 73 of file STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

  • File List
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  • Project
  • STM32F10x_StdPeriph_Examples
  • DMA
  • FSMC
Defines

STM32F10x_StdPeriph_Examples/DMA/FSMC/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/DMA/FSMC/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 72 of file STM32F10x_StdPeriph_Examples/DMA/FSMC/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • DMA
  • I2C_RAM
Defines

STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 72 of file STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

  • File List
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  • Project
  • STM32F10x_StdPeriph_Examples
  • DMA
  • SPI_RAM
Defines

STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 72 of file STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

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  • EXTI
  • EXTI_Config
Defines

STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 72 of file STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

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  • Dual_Boot
Defines

STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 72 of file STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

  • File List
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  • Project
  • STM32F10x_StdPeriph_Examples
  • FLASH
  • Program
Defines

STM32F10x_StdPeriph_Examples/FLASH/Program/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/FLASH/Program/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 72 of file STM32F10x_StdPeriph_Examples/FLASH/Program/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • FLASH
  • Write_Protection
Defines

STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 73 of file STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

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  • Project
  • STM32F10x_StdPeriph_Examples
  • FSMC
  • NAND
Defines

STM32F10x_StdPeriph_Examples/FSMC/NAND/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/FSMC/NAND/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 72 of file STM32F10x_StdPeriph_Examples/FSMC/NAND/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

  • File List
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  • Project
  • STM32F10x_StdPeriph_Examples
  • FSMC
  • NOR
Defines

STM32F10x_StdPeriph_Examples/FSMC/NOR/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/FSMC/NOR/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 72 of file STM32F10x_StdPeriph_Examples/FSMC/NOR/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • FSMC
  • NOR_CodeExecute
  • binary
Defines

STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 72 of file STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • FSMC
  • NOR_CodeExecute
Defines

STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 72 of file STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • FSMC
  • OneNAND
Defines

STM32F10x_StdPeriph_Examples/FSMC/OneNAND/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/FSMC/OneNAND/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 72 of file STM32F10x_StdPeriph_Examples/FSMC/OneNAND/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

  • File List
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  • FSMC
  • SRAM
Defines

STM32F10x_StdPeriph_Examples/FSMC/SRAM/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/FSMC/SRAM/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 72 of file STM32F10x_StdPeriph_Examples/FSMC/SRAM/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

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  • FSMC
  • SRAM_DataMemory
Defines

STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 72 of file STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

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  • STM32F10x_StdPeriph_Lib_V3.5.0
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  • STM32F10x_StdPeriph_Examples
  • GPIO
  • IOToggle
Defines

STM32F10x_StdPeriph_Examples/GPIO/IOToggle/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/GPIO/IOToggle/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 72 of file STM32F10x_StdPeriph_Examples/GPIO/IOToggle/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

  • File List
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  • Project
  • STM32F10x_StdPeriph_Examples
  • GPIO
  • JTAG_Remap
Defines

STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 72 of file STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • I2C
  • EEPROM
Defines | Functions

STM32F10x_StdPeriph_Examples/I2C/EEPROM/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
The assert_param macro is used for function's parameters check.
#define | USE_FULL_ASSERT

Functions

void | assert_failed (uint8_t *file, uint32_t line)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/I2C/EEPROM/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))

The assert_param macro is used for function's parameters check.

Parameters:
expr,: If expr is false, it calls assert_failed function which reports the name of the source file and the source line number of the call that failed. If expr is true, it returns no value.
Return values:
None

Definition at line 68 of file STM32F10x_StdPeriph_Examples/I2C/EEPROM/stm32f10x_conf.h.

#define USE_FULL_ASSERT

Function Documentation

void assert_failed | ( | uint8_t * | file,
 |  | uint32_t | line
 | ) |  |


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • I2C
  • I2C_TSENSOR
Defines

STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 72 of file STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

  • File List
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  • Project
  • STM32F10x_StdPeriph_Examples
  • I2C
  • IOExpander
Defines

STM32F10x_StdPeriph_Examples/I2C/IOExpander/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/I2C/IOExpander/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 72 of file STM32F10x_StdPeriph_Examples/I2C/IOExpander/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

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Defines

STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 72 of file STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

  • File List
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  • Project
  • STM32F10x_StdPeriph_Examples
  • I2S
  • SPI_I2S_Switch
Defines

STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 74 of file STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • IWDG
  • IWDG_Reset
Defines

STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 72 of file STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

  • File List
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  • Lib_DEBUG
  • RunTime_Check
Defines

STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0)
#define | USE_FULL_ASSERT 1

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 72 of file STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/stm32f10x_conf.h.

#define USE_FULL_ASSERT 1

Definition at line 56 of file STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

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  • NVIC
  • DMA_WFIMode
Defines

STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 72 of file STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

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  • IRQ_Mask
Defines

STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 72 of file STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

  • File List
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  • Project
  • STM32F10x_StdPeriph_Examples
  • NVIC
  • IRQ_Priority
Defines

STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 72 of file STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • NVIC
  • VectorTable_Relocation
Defines

STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 72 of file STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • PWR
  • PVD
Defines

STM32F10x_StdPeriph_Examples/PWR/PVD/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/PWR/PVD/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 72 of file STM32F10x_StdPeriph_Examples/PWR/PVD/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

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  • Project
  • STM32F10x_StdPeriph_Examples
  • PWR
  • STANDBY
Defines

STM32F10x_StdPeriph_Examples/PWR/STANDBY/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/PWR/STANDBY/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 72 of file STM32F10x_StdPeriph_Examples/PWR/STANDBY/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

  • File List
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  • Project
  • STM32F10x_StdPeriph_Examples
  • PWR
  • STOP
Defines

STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 72 of file STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • RCC
  • RCC_ClockConfig
Defines

STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 72 of file STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • RTC
  • Calendar
Defines

STM32F10x_StdPeriph_Examples/RTC/Calendar/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/RTC/Calendar/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 73 of file STM32F10x_StdPeriph_Examples/RTC/Calendar/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

  • File List
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  • RTC
  • LSI_Calib
Defines

STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 72 of file STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

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  • uSDCard
Defines

STM32F10x_StdPeriph_Examples/SDIO/uSDCard/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/SDIO/uSDCard/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 72 of file STM32F10x_StdPeriph_Examples/SDIO/uSDCard/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

  • File List
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  • Project
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  • SPI
  • CRC
Defines

STM32F10x_StdPeriph_Examples/SPI/CRC/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/SPI/CRC/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 72 of file STM32F10x_StdPeriph_Examples/SPI/CRC/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

  • File List
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  • Project
  • STM32F10x_StdPeriph_Examples
  • SPI
  • DMA
Defines

STM32F10x_StdPeriph_Examples/SPI/DMA/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/SPI/DMA/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 72 of file STM32F10x_StdPeriph_Examples/SPI/DMA/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • SPI
  • FullDuplex_SoftNSS
Defines

STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 73 of file STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • SPI
  • Simplex_Interrupt
Defines

STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 72 of file STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

  • File List
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  • Project
  • STM32F10x_StdPeriph_Examples
  • SPI
  • SPI_FLASH
Defines

STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 72 of file STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • SysTick
  • TimeBase
Defines

STM32F10x_StdPeriph_Examples/SysTick/TimeBase/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/SysTick/TimeBase/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 72 of file STM32F10x_StdPeriph_Examples/SysTick/TimeBase/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • TIM
  • 6Steps
Defines

STM32F10x_StdPeriph_Examples/TIM/6Steps/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/TIM/6Steps/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 73 of file STM32F10x_StdPeriph_Examples/TIM/6Steps/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

  • File List
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  • TIM
  • 7PWM_Output
Defines

STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 73 of file STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

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  • Cascade_Synchro
Defines

STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 72 of file STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

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  • ComplementarySignals
Defines

STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 72 of file STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

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  • DMA
Defines

STM32F10x_StdPeriph_Examples/TIM/DMA/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/TIM/DMA/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 72 of file STM32F10x_StdPeriph_Examples/TIM/DMA/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

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  • Project
  • STM32F10x_StdPeriph_Examples
  • TIM
  • DMABurst
Defines

STM32F10x_StdPeriph_Examples/TIM/DMABurst/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/TIM/DMABurst/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 72 of file STM32F10x_StdPeriph_Examples/TIM/DMABurst/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

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  • Project
  • STM32F10x_StdPeriph_Examples
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  • ExtTrigger_Synchro
Defines

STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 72 of file STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

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  • Project
  • STM32F10x_StdPeriph_Examples
  • TIM
  • InputCapture
Defines

STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 72 of file STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

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  • STM32F10x_StdPeriph_Examples
  • TIM
  • OCActive
Defines

STM32F10x_StdPeriph_Examples/TIM/OCActive/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/TIM/OCActive/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 72 of file STM32F10x_StdPeriph_Examples/TIM/OCActive/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

  • File List
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  • Project
  • STM32F10x_StdPeriph_Examples
  • TIM
  • OCInactive
Defines

STM32F10x_StdPeriph_Examples/TIM/OCInactive/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/TIM/OCInactive/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 72 of file STM32F10x_StdPeriph_Examples/TIM/OCInactive/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

  • File List
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  • Project
  • STM32F10x_StdPeriph_Examples
  • TIM
  • OCToggle
Defines

STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 72 of file STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

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  • STM32F10x_StdPeriph_Examples
  • TIM
  • OnePulse
Defines

STM32F10x_StdPeriph_Examples/TIM/OnePulse/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/TIM/OnePulse/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 72 of file STM32F10x_StdPeriph_Examples/TIM/OnePulse/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

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  • Parallel_Synchro
Defines

STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 72 of file STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

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  • PWM_Input
Defines

STM32F10x_StdPeriph_Examples/TIM/PWM_Input/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/TIM/PWM_Input/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 72 of file STM32F10x_StdPeriph_Examples/TIM/PWM_Input/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

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  • PWM_Output
Defines

STM32F10x_StdPeriph_Examples/TIM/PWM_Output/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/TIM/PWM_Output/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 72 of file STM32F10x_StdPeriph_Examples/TIM/PWM_Output/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

  • File List
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  • Project
  • STM32F10x_StdPeriph_Examples
  • TIM
  • TIM10_PWMOutput
Defines

STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 72 of file STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

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  • Project
  • STM32F10x_StdPeriph_Examples
  • TIM
  • TIM15_ComplementarySignals
Defines

STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 72 of file STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

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  • Project
  • STM32F10x_StdPeriph_Examples
  • TIM
  • TIM1_Synchro
Defines

STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 73 of file STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

  • File List
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  • Project
  • STM32F10x_StdPeriph_Examples
  • TIM
  • TIM9_OCToggle
Defines

STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 72 of file STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

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  • Project
  • STM32F10x_StdPeriph_Examples
  • TIM
  • TimeBase
Defines

STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 72 of file STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • USART
  • DMA_Interrupt
Defines

STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 71 of file STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • USART
  • DMA_Polling
Defines

STM32F10x_StdPeriph_Examples/USART/DMA_Polling/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/USART/DMA_Polling/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 71 of file STM32F10x_StdPeriph_Examples/USART/DMA_Polling/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

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  • HalfDuplex
Defines

STM32F10x_StdPeriph_Examples/USART/HalfDuplex/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/USART/HalfDuplex/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 71 of file STM32F10x_StdPeriph_Examples/USART/HalfDuplex/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

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  • HyperTerminal_HwFlowControl
Defines

STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 71 of file STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

  • File List
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  • Project
  • STM32F10x_StdPeriph_Examples
  • USART
  • HyperTerminal_Interrupt
Defines

STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 71 of file STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

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  • Project
  • STM32F10x_StdPeriph_Examples
  • USART
  • Interrupt
Defines

STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 71 of file STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

  • File List
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  • Project
  • STM32F10x_StdPeriph_Examples
  • USART
  • IrDA
  • Receive
Defines

STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 71 of file STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

  • File List
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  • Project
  • STM32F10x_StdPeriph_Examples
  • USART
  • IrDA
  • Transmit
Defines

STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 71 of file STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

  • File List
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  • Project
  • STM32F10x_StdPeriph_Examples
  • USART
  • MultiProcessor
Defines

STM32F10x_StdPeriph_Examples/USART/MultiProcessor/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/USART/MultiProcessor/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 71 of file STM32F10x_StdPeriph_Examples/USART/MultiProcessor/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

  • File List
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  • Project
  • STM32F10x_StdPeriph_Examples
  • USART
  • Polling
Defines

STM32F10x_StdPeriph_Examples/USART/Polling/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/USART/Polling/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 71 of file STM32F10x_StdPeriph_Examples/USART/Polling/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • USART
  • Printf
Defines

STM32F10x_StdPeriph_Examples/USART/Printf/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/USART/Printf/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 71 of file STM32F10x_StdPeriph_Examples/USART/Printf/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • USART
  • Smartcard
Defines

STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 72 of file STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • USART
  • Synchronous
Defines

STM32F10x_StdPeriph_Examples/USART/Synchronous/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/USART/Synchronous/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 72 of file STM32F10x_StdPeriph_Examples/USART/Synchronous/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • WWDG
  • WWDG_Reset
Defines

STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 72 of file STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Template
Defines

STM32F10x_StdPeriph_Template/stm32f10x_conf.h File Reference

Library configuration file. More...

#include "stm32f10x_adc.h"
#include "stm32f10x_bkp.h"
#include "stm32f10x_can.h"
#include "stm32f10x_cec.h"
#include "stm32f10x_crc.h"
#include "stm32f10x_dac.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_dma.h"
#include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x_iwdg.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_rtc.h"
#include "stm32f10x_sdio.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_wwdg.h"
#include "misc.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0)

Detailed Description

Library configuration file.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Template/stm32f10x_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0)

Definition at line 72 of file STM32F10x_StdPeriph_Template/stm32f10x_conf.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_crc.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Libraries
  • STM32F10x_StdPeriph_Driver
  • src
Functions

stm32f10x_crc.c File Reference

This file provides all the CRC firmware functions. More...

#include "stm32f10x_crc.h"

Go to the source code of this file.

Functions

uint32_t | CRC_CalcBlockCRC (uint32_t pBuffer[], uint32_t BufferLength)
Computes the 32-bit CRC of a given buffer of data word(32-bit).
uint32_t | CRC_CalcCRC (uint32_t Data)
Computes the 32-bit CRC of a given data word(32-bit).
uint32_t | CRC_GetCRC (void)
Returns the current CRC value.
uint8_t | CRC_GetIDRegister (void)
Returns the 8-bit data stored in the Independent Data(ID) register.
void | CRC_ResetDR (void)
Resets the CRC Data register (DR).
void | CRC_SetIDRegister (uint8_t IDValue)
Stores a 8-bit data in the Independent Data(ID) register.

Detailed Description

This file provides all the CRC firmware functions.

Author:
MCD Application Team
Version:
V3.5.0
Date:
11-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm32f10x_crc.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_crc.h File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Libraries
  • STM32F10x_StdPeriph_Driver
  • inc
Functions

stm32f10x_crc.h File Reference

This file contains all the functions prototypes for the CRC firmware library. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

uint32_t | CRC_CalcBlockCRC (uint32_t pBuffer[], uint32_t BufferLength)
Computes the 32-bit CRC of a given buffer of data word(32-bit).
uint32_t | CRC_CalcCRC (uint32_t Data)
Computes the 32-bit CRC of a given data word(32-bit).
uint32_t | CRC_GetCRC (void)
Returns the current CRC value.
uint8_t | CRC_GetIDRegister (void)
Returns the 8-bit data stored in the Independent Data(ID) register.
void | CRC_ResetDR (void)
Resets the CRC Data register (DR).
void | CRC_SetIDRegister (uint8_t IDValue)
Stores a 8-bit data in the Independent Data(ID) register.

Detailed Description

This file contains all the functions prototypes for the CRC firmware library.

Author:
MCD Application Team
Version:
V3.5.0
Date:
11-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm32f10x_crc.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_dac.c File Reference

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Libraries
  • STM32F10x_StdPeriph_Driver
  • src
Defines | Functions

stm32f10x_dac.c File Reference

This file provides all the DAC firmware functions. More...

#include "stm32f10x_dac.h"
#include "stm32f10x_rcc.h"

Go to the source code of this file.

Defines

#define | CR_CLEAR_MASK ((uint32_t)0x00000FFE)
#define | DHR12R1_OFFSET ((uint32_t)0x00000008)
#define | DHR12R2_OFFSET ((uint32_t)0x00000014)
#define | DHR12RD_OFFSET ((uint32_t)0x00000020)
#define | DOR_OFFSET ((uint32_t)0x0000002C)
#define | DUAL_SWTRIG_RESET ((uint32_t)0xFFFFFFFC)
#define | DUAL_SWTRIG_SET ((uint32_t)0x00000003)

Functions

void | DAC_Cmd (uint32_t DAC_Channel, FunctionalState NewState)
Enables or disables the specified DAC channel.
void | DAC_DeInit (void)
Deinitializes the DAC peripheral registers to their default reset values.
void | DAC_DMACmd (uint32_t DAC_Channel, FunctionalState NewState)
Enables or disables the specified DAC channel DMA request.
void | DAC_DualSoftwareTriggerCmd (FunctionalState NewState)
Enables or disables simultaneously the two DAC channels software triggers.
uint16_t | DAC_GetDataOutputValue (uint32_t DAC_Channel)
Returns the last data output value of the selected DAC channel.
void | DAC_Init (uint32_t DAC_Channel, DAC_InitTypeDef *DAC_InitStruct)
Initializes the DAC peripheral according to the specified parameters in the DAC_InitStruct.
void | DAC_SetChannel1Data (uint32_t DAC_Align, uint16_t Data)
Set the specified data holding register value for DAC channel1.
void | DAC_SetChannel2Data (uint32_t DAC_Align, uint16_t Data)
Set the specified data holding register value for DAC channel2.
void | DAC_SetDualChannelData (uint32_t DAC_Align, uint16_t Data2, uint16_t Data1)
Set the specified data holding register value for dual channel DAC.
void | DAC_SoftwareTriggerCmd (uint32_t DAC_Channel, FunctionalState NewState)
Enables or disables the selected DAC channel software trigger.
void | DAC_StructInit (DAC_InitTypeDef *DAC_InitStruct)
Fills each DAC_InitStruct member with its default value.
void | DAC_WaveGenerationCmd (uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState)
Enables or disables the selected DAC channel wave generation.

Detailed Description

This file provides all the DAC firmware functions.

Author:
MCD Application Team
Version:
V3.5.0
Date:
11-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm32f10x_dac.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_dac.h File Reference

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Libraries
  • STM32F10x_StdPeriph_Driver
  • inc
Data Structures | Defines | Functions

stm32f10x_dac.h File Reference

This file contains all the functions prototypes for the DAC firmware library. More...

#include "stm32f10x.h"

Go to the source code of this file.

Data Structures

struct | DAC_InitTypeDef
DAC Init structure definition. More...

Defines

#define | DAC_Align_12b_L ((uint32_t)0x00000004)
#define | DAC_Align_12b_R ((uint32_t)0x00000000)
#define | DAC_Align_8b_R ((uint32_t)0x00000008)
#define | DAC_Channel_1 ((uint32_t)0x00000000)
#define | DAC_Channel_2 ((uint32_t)0x00000010)
#define | DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000)
#define | DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00)
#define | DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00)
#define | DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100)
#define | DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200)
#define | DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300)
#define | DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400)
#define | DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500)
#define | DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600)
#define | DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700)
#define | DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800)
#define | DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900)
#define | DAC_OutputBuffer_Disable ((uint32_t)0x00000002)
#define | DAC_OutputBuffer_Enable ((uint32_t)0x00000000)
#define | DAC_TriangleAmplitude_1 ((uint32_t)0x00000000)
#define | DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900)
#define | DAC_TriangleAmplitude_127 ((uint32_t)0x00000600)
#define | DAC_TriangleAmplitude_15 ((uint32_t)0x00000300)
#define | DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00)
#define | DAC_TriangleAmplitude_255 ((uint32_t)0x00000700)
#define | DAC_TriangleAmplitude_3 ((uint32_t)0x00000100)
#define | DAC_TriangleAmplitude_31 ((uint32_t)0x00000400)
#define | DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00)
#define | DAC_TriangleAmplitude_511 ((uint32_t)0x00000800)
#define | DAC_TriangleAmplitude_63 ((uint32_t)0x00000500)
#define | DAC_TriangleAmplitude_7 ((uint32_t)0x00000200)
#define | DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034)
#define | DAC_Trigger_None ((uint32_t)0x00000000)
#define | DAC_Trigger_Software ((uint32_t)0x0000003C)
#define | DAC_Trigger_T15_TRGO ((uint32_t)0x0000001C)
#define | DAC_Trigger_T2_TRGO ((uint32_t)0x00000024)
#define | DAC_Trigger_T3_TRGO ((uint32_t)0x0000000C)
#define | DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C)
#define | DAC_Trigger_T5_TRGO ((uint32_t)0x0000001C)
#define | DAC_Trigger_T6_TRGO ((uint32_t)0x00000004)
#define | DAC_Trigger_T7_TRGO ((uint32_t)0x00000014)
#define | DAC_Trigger_T8_TRGO ((uint32_t)0x0000000C)
#define | DAC_Wave_Noise ((uint32_t)0x00000040)
#define | DAC_Wave_Triangle ((uint32_t)0x00000080)
#define | DAC_WaveGeneration_Noise ((uint32_t)0x00000040)
#define | DAC_WaveGeneration_None ((uint32_t)0x00000000)
#define | DAC_WaveGeneration_Triangle ((uint32_t)0x00000080)
#define | IS_DAC_ALIGN(ALIGN)
#define | IS_DAC_CHANNEL(CHANNEL)
#define | IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
#define | IS_DAC_GENERATE_WAVE(WAVE)
#define | IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE)
#define | IS_DAC_OUTPUT_BUFFER_STATE(STATE)
#define | IS_DAC_TRIGGER(TRIGGER)
#define | IS_DAC_WAVE(WAVE)

Functions

void | DAC_Cmd (uint32_t DAC_Channel, FunctionalState NewState)
Enables or disables the specified DAC channel.
void | DAC_DeInit (void)
Deinitializes the DAC peripheral registers to their default reset values.
void | DAC_DMACmd (uint32_t DAC_Channel, FunctionalState NewState)
Enables or disables the specified DAC channel DMA request.
void | DAC_DualSoftwareTriggerCmd (FunctionalState NewState)
Enables or disables simultaneously the two DAC channels software triggers.
uint16_t | DAC_GetDataOutputValue (uint32_t DAC_Channel)
Returns the last data output value of the selected DAC channel.
void | DAC_Init (uint32_t DAC_Channel, DAC_InitTypeDef *DAC_InitStruct)
Initializes the DAC peripheral according to the specified parameters in the DAC_InitStruct.
void | DAC_SetChannel1Data (uint32_t DAC_Align, uint16_t Data)
Set the specified data holding register value for DAC channel1.
void | DAC_SetChannel2Data (uint32_t DAC_Align, uint16_t Data)
Set the specified data holding register value for DAC channel2.
void | DAC_SetDualChannelData (uint32_t DAC_Align, uint16_t Data2, uint16_t Data1)
Set the specified data holding register value for dual channel DAC.
void | DAC_SoftwareTriggerCmd (uint32_t DAC_Channel, FunctionalState NewState)
Enables or disables the selected DAC channel software trigger.
void | DAC_StructInit (DAC_InitTypeDef *DAC_InitStruct)
Fills each DAC_InitStruct member with its default value.
void | DAC_WaveGenerationCmd (uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState)
Enables or disables the selected DAC channel wave generation.

Detailed Description

This file contains all the functions prototypes for the DAC firmware library.

Author:
MCD Application Team
Version:
V3.5.0
Date:
11-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm32f10x_dac.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_dbgmcu.c File Reference

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  • STM32F10x_StdPeriph_Lib_V3.5.0
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  • STM32F10x_StdPeriph_Driver
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Defines | Functions

stm32f10x_dbgmcu.c File Reference

This file provides all the DBGMCU firmware functions. More...

#include "stm32f10x_dbgmcu.h"

Go to the source code of this file.

Defines

#define | IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)

Functions

void | DBGMCU_Config (uint32_t DBGMCU_Periph, FunctionalState NewState)
Configures the specified peripheral and low power mode behavior when the MCU under Debug mode.
uint32_t | DBGMCU_GetDEVID (void)
Returns the device identifier.
uint32_t | DBGMCU_GetREVID (void)
Returns the device revision identifier.

Detailed Description

This file provides all the DBGMCU firmware functions.

Author:
MCD Application Team
Version:
V3.5.0
Date:
11-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm32f10x_dbgmcu.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_dbgmcu.h File Reference

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  • STM32F10x_StdPeriph_Lib_V3.5.0
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Defines | Functions

stm32f10x_dbgmcu.h File Reference

This file contains all the functions prototypes for the DBGMCU firmware library. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | DBGMCU_CAN1_STOP ((uint32_t)0x00004000)
#define | DBGMCU_CAN2_STOP ((uint32_t)0x00200000)
#define | DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000)
#define | DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000)
#define | DBGMCU_IWDG_STOP ((uint32_t)0x00000100)
#define | DBGMCU_SLEEP ((uint32_t)0x00000001)
#define | DBGMCU_STANDBY ((uint32_t)0x00000004)
#define | DBGMCU_STOP ((uint32_t)0x00000002)
#define | DBGMCU_TIM10_STOP ((uint32_t)0x20000000)
#define | DBGMCU_TIM11_STOP ((uint32_t)0x40000000)
#define | DBGMCU_TIM12_STOP ((uint32_t)0x02000000)
#define | DBGMCU_TIM13_STOP ((uint32_t)0x04000000)
#define | DBGMCU_TIM14_STOP ((uint32_t)0x08000000)
#define | DBGMCU_TIM15_STOP ((uint32_t)0x00400000)
#define | DBGMCU_TIM16_STOP ((uint32_t)0x00800000)
#define | DBGMCU_TIM17_STOP ((uint32_t)0x01000000)
#define | DBGMCU_TIM1_STOP ((uint32_t)0x00000400)
#define | DBGMCU_TIM2_STOP ((uint32_t)0x00000800)
#define | DBGMCU_TIM3_STOP ((uint32_t)0x00001000)
#define | DBGMCU_TIM4_STOP ((uint32_t)0x00002000)
#define | DBGMCU_TIM5_STOP ((uint32_t)0x00040000)
#define | DBGMCU_TIM6_STOP ((uint32_t)0x00080000)
#define | DBGMCU_TIM7_STOP ((uint32_t)0x00100000)
#define | DBGMCU_TIM8_STOP ((uint32_t)0x00020000)
#define | DBGMCU_TIM9_STOP ((uint32_t)0x10000000)
#define | DBGMCU_WWDG_STOP ((uint32_t)0x00000200)
#define | IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0x800000F8) == 0x00) && ((PERIPH) != 0x00))

Functions

void | DBGMCU_Config (uint32_t DBGMCU_Periph, FunctionalState NewState)
Configures the specified peripheral and low power mode behavior when the MCU under Debug mode.
uint32_t | DBGMCU_GetDEVID (void)
Returns the device identifier.
uint32_t | DBGMCU_GetREVID (void)
Returns the device revision identifier.

Detailed Description

This file contains all the functions prototypes for the DBGMCU firmware library.

Author:
MCD Application Team
Version:
V3.5.0
Date:
11-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm32f10x_dbgmcu.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_dma.c File Reference

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Defines | Functions

stm32f10x_dma.c File Reference

This file provides all the DMA firmware functions. More...

#include "stm32f10x_dma.h"
#include "stm32f10x_rcc.h"

Go to the source code of this file.

Defines

#define | CCR_CLEAR_Mask ((uint32_t)0xFFFF800F)
#define | DMA1_Channel1_IT_Mask ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))
#define | DMA1_Channel2_IT_Mask ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))
#define | DMA1_Channel3_IT_Mask ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))
#define | DMA1_Channel4_IT_Mask ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))
#define | DMA1_Channel5_IT_Mask ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))
#define | DMA1_Channel6_IT_Mask ((uint32_t)(DMA_ISR_GIF6 | DMA_ISR_TCIF6 | DMA_ISR_HTIF6 | DMA_ISR_TEIF6))
#define | DMA1_Channel7_IT_Mask ((uint32_t)(DMA_ISR_GIF7 | DMA_ISR_TCIF7 | DMA_ISR_HTIF7 | DMA_ISR_TEIF7))
#define | DMA2_Channel1_IT_Mask ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))
#define | DMA2_Channel2_IT_Mask ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))
#define | DMA2_Channel3_IT_Mask ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))
#define | DMA2_Channel4_IT_Mask ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))
#define | DMA2_Channel5_IT_Mask ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))
#define | FLAG_Mask ((uint32_t)0x10000000)

Functions

void | DMA_ClearFlag (uint32_t DMAy_FLAG)
Clears the DMAy Channelx's pending flags.
void | DMA_ClearITPendingBit (uint32_t DMAy_IT)
Clears the DMAy Channelx's interrupt pending bits.
void | DMA_Cmd (DMA_Channel_TypeDef *DMAy_Channelx, FunctionalState NewState)
Enables or disables the specified DMAy Channelx.
void | DMA_DeInit (DMA_Channel_TypeDef *DMAy_Channelx)
Deinitializes the DMAy Channelx registers to their default reset values.
uint16_t | DMA_GetCurrDataCounter (DMA_Channel_TypeDef *DMAy_Channelx)
Returns the number of remaining data units in the current DMAy Channelx transfer.
FlagStatus | DMA_GetFlagStatus (uint32_t DMAy_FLAG)
Checks whether the specified DMAy Channelx flag is set or not.
ITStatus | DMA_GetITStatus (uint32_t DMAy_IT)
Checks whether the specified DMAy Channelx interrupt has occurred or not.
void | DMA_Init (DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitTypeDef *DMA_InitStruct)
Initializes the DMAy Channelx according to the specified parameters in the DMA_InitStruct.
void | DMA_ITConfig (DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)
Enables or disables the specified DMAy Channelx interrupts.
void | DMA_SetCurrDataCounter (DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber)
Sets the number of data units in the current DMAy Channelx transfer.
void | DMA_StructInit (DMA_InitTypeDef *DMA_InitStruct)
Fills each DMA_InitStruct member with its default value.

Detailed Description

This file provides all the DMA firmware functions.

Author:
MCD Application Team
Version:
V3.5.0
Date:
11-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm32f10x_dma.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_dma.h File Reference

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Data Structures | Defines | Functions

stm32f10x_dma.h File Reference

This file contains all the functions prototypes for the DMA firmware library. More...

#include "stm32f10x.h"

Go to the source code of this file.

Data Structures

struct | DMA_InitTypeDef
DMA Init structure definition. More...

Defines

#define | DMA1_FLAG_GL1 ((uint32_t)0x00000001)
#define | DMA1_FLAG_GL2 ((uint32_t)0x00000010)
#define | DMA1_FLAG_GL3 ((uint32_t)0x00000100)
#define | DMA1_FLAG_GL4 ((uint32_t)0x00001000)
#define | DMA1_FLAG_GL5 ((uint32_t)0x00010000)
#define | DMA1_FLAG_GL6 ((uint32_t)0x00100000)
#define | DMA1_FLAG_GL7 ((uint32_t)0x01000000)
#define | DMA1_FLAG_HT1 ((uint32_t)0x00000004)
#define | DMA1_FLAG_HT2 ((uint32_t)0x00000040)
#define | DMA1_FLAG_HT3 ((uint32_t)0x00000400)
#define | DMA1_FLAG_HT4 ((uint32_t)0x00004000)
#define | DMA1_FLAG_HT5 ((uint32_t)0x00040000)
#define | DMA1_FLAG_HT6 ((uint32_t)0x00400000)
#define | DMA1_FLAG_HT7 ((uint32_t)0x04000000)
#define | DMA1_FLAG_TC1 ((uint32_t)0x00000002)
#define | DMA1_FLAG_TC2 ((uint32_t)0x00000020)
#define | DMA1_FLAG_TC3 ((uint32_t)0x00000200)
#define | DMA1_FLAG_TC4 ((uint32_t)0x00002000)
#define | DMA1_FLAG_TC5 ((uint32_t)0x00020000)
#define | DMA1_FLAG_TC6 ((uint32_t)0x00200000)
#define | DMA1_FLAG_TC7 ((uint32_t)0x02000000)
#define | DMA1_FLAG_TE1 ((uint32_t)0x00000008)
#define | DMA1_FLAG_TE2 ((uint32_t)0x00000080)
#define | DMA1_FLAG_TE3 ((uint32_t)0x00000800)
#define | DMA1_FLAG_TE4 ((uint32_t)0x00008000)
#define | DMA1_FLAG_TE5 ((uint32_t)0x00080000)
#define | DMA1_FLAG_TE6 ((uint32_t)0x00800000)
#define | DMA1_FLAG_TE7 ((uint32_t)0x08000000)
#define | DMA1_IT_GL1 ((uint32_t)0x00000001)
#define | DMA1_IT_GL2 ((uint32_t)0x00000010)
#define | DMA1_IT_GL3 ((uint32_t)0x00000100)
#define | DMA1_IT_GL4 ((uint32_t)0x00001000)
#define | DMA1_IT_GL5 ((uint32_t)0x00010000)
#define | DMA1_IT_GL6 ((uint32_t)0x00100000)
#define | DMA1_IT_GL7 ((uint32_t)0x01000000)
#define | DMA1_IT_HT1 ((uint32_t)0x00000004)
#define | DMA1_IT_HT2 ((uint32_t)0x00000040)
#define | DMA1_IT_HT3 ((uint32_t)0x00000400)
#define | DMA1_IT_HT4 ((uint32_t)0x00004000)
#define | DMA1_IT_HT5 ((uint32_t)0x00040000)
#define | DMA1_IT_HT6 ((uint32_t)0x00400000)
#define | DMA1_IT_HT7 ((uint32_t)0x04000000)
#define | DMA1_IT_TC1 ((uint32_t)0x00000002)
#define | DMA1_IT_TC2 ((uint32_t)0x00000020)
#define | DMA1_IT_TC3 ((uint32_t)0x00000200)
#define | DMA1_IT_TC4 ((uint32_t)0x00002000)
#define | DMA1_IT_TC5 ((uint32_t)0x00020000)
#define | DMA1_IT_TC6 ((uint32_t)0x00200000)
#define | DMA1_IT_TC7 ((uint32_t)0x02000000)
#define | DMA1_IT_TE1 ((uint32_t)0x00000008)
#define | DMA1_IT_TE2 ((uint32_t)0x00000080)
#define | DMA1_IT_TE3 ((uint32_t)0x00000800)
#define | DMA1_IT_TE4 ((uint32_t)0x00008000)
#define | DMA1_IT_TE5 ((uint32_t)0x00080000)
#define | DMA1_IT_TE6 ((uint32_t)0x00800000)
#define | DMA1_IT_TE7 ((uint32_t)0x08000000)
#define | DMA2_FLAG_GL1 ((uint32_t)0x10000001)
#define | DMA2_FLAG_GL2 ((uint32_t)0x10000010)
#define | DMA2_FLAG_GL3 ((uint32_t)0x10000100)
#define | DMA2_FLAG_GL4 ((uint32_t)0x10001000)
#define | DMA2_FLAG_GL5 ((uint32_t)0x10010000)
#define | DMA2_FLAG_HT1 ((uint32_t)0x10000004)
#define | DMA2_FLAG_HT2 ((uint32_t)0x10000040)
#define | DMA2_FLAG_HT3 ((uint32_t)0x10000400)
#define | DMA2_FLAG_HT4 ((uint32_t)0x10004000)
#define | DMA2_FLAG_HT5 ((uint32_t)0x10040000)
#define | DMA2_FLAG_TC1 ((uint32_t)0x10000002)
#define | DMA2_FLAG_TC2 ((uint32_t)0x10000020)
#define | DMA2_FLAG_TC3 ((uint32_t)0x10000200)
#define | DMA2_FLAG_TC4 ((uint32_t)0x10002000)
#define | DMA2_FLAG_TC5 ((uint32_t)0x10020000)
#define | DMA2_FLAG_TE1 ((uint32_t)0x10000008)
#define | DMA2_FLAG_TE2 ((uint32_t)0x10000080)
#define | DMA2_FLAG_TE3 ((uint32_t)0x10000800)
#define | DMA2_FLAG_TE4 ((uint32_t)0x10008000)
#define | DMA2_FLAG_TE5 ((uint32_t)0x10080000)
#define | DMA2_IT_GL1 ((uint32_t)0x10000001)
#define | DMA2_IT_GL2 ((uint32_t)0x10000010)
#define | DMA2_IT_GL3 ((uint32_t)0x10000100)
#define | DMA2_IT_GL4 ((uint32_t)0x10001000)
#define | DMA2_IT_GL5 ((uint32_t)0x10010000)
#define | DMA2_IT_HT1 ((uint32_t)0x10000004)
#define | DMA2_IT_HT2 ((uint32_t)0x10000040)
#define | DMA2_IT_HT3 ((uint32_t)0x10000400)
#define | DMA2_IT_HT4 ((uint32_t)0x10004000)
#define | DMA2_IT_HT5 ((uint32_t)0x10040000)
#define | DMA2_IT_TC1 ((uint32_t)0x10000002)
#define | DMA2_IT_TC2 ((uint32_t)0x10000020)
#define | DMA2_IT_TC3 ((uint32_t)0x10000200)
#define | DMA2_IT_TC4 ((uint32_t)0x10002000)
#define | DMA2_IT_TC5 ((uint32_t)0x10020000)
#define | DMA2_IT_TE1 ((uint32_t)0x10000008)
#define | DMA2_IT_TE2 ((uint32_t)0x10000080)
#define | DMA2_IT_TE3 ((uint32_t)0x10000800)
#define | DMA2_IT_TE4 ((uint32_t)0x10008000)
#define | DMA2_IT_TE5 ((uint32_t)0x10080000)
#define | DMA_DIR_PeripheralDST ((uint32_t)0x00000010)
#define | DMA_DIR_PeripheralSRC ((uint32_t)0x00000000)
#define | DMA_IT_HT ((uint32_t)0x00000004)
#define | DMA_IT_TC ((uint32_t)0x00000002)
#define | DMA_IT_TE ((uint32_t)0x00000008)
#define | DMA_M2M_Disable ((uint32_t)0x00000000)
#define | DMA_M2M_Enable ((uint32_t)0x00004000)
#define | DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)
#define | DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400)
#define | DMA_MemoryDataSize_Word ((uint32_t)0x00000800)
#define | DMA_MemoryInc_Disable ((uint32_t)0x00000000)
#define | DMA_MemoryInc_Enable ((uint32_t)0x00000080)
#define | DMA_Mode_Circular ((uint32_t)0x00000020)
#define | DMA_Mode_Normal ((uint32_t)0x00000000)
#define | DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000)
#define | DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100)
#define | DMA_PeripheralDataSize_Word ((uint32_t)0x00000200)
#define | DMA_PeripheralInc_Disable ((uint32_t)0x00000000)
#define | DMA_PeripheralInc_Enable ((uint32_t)0x00000040)
#define | DMA_Priority_High ((uint32_t)0x00002000)
#define | DMA_Priority_Low ((uint32_t)0x00000000)
#define | DMA_Priority_Medium ((uint32_t)0x00001000)
#define | DMA_Priority_VeryHigh ((uint32_t)0x00003000)
#define | IS_DMA_ALL_PERIPH(PERIPH)
#define | IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
#define | IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00))
#define | IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00))
#define | IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00))
#define | IS_DMA_DIR(DIR)
#define | IS_DMA_GET_FLAG(FLAG)
#define | IS_DMA_GET_IT(IT)
#define | IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Enable) || ((STATE) == DMA_M2M_Disable))
#define | IS_DMA_MEMORY_DATA_SIZE(SIZE)
#define | IS_DMA_MEMORY_INC_STATE(STATE)
#define | IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Circular) || ((MODE) == DMA_Mode_Normal))
#define | IS_DMA_PERIPHERAL_DATA_SIZE(SIZE)
#define | IS_DMA_PERIPHERAL_INC_STATE(STATE)
#define | IS_DMA_PRIORITY(PRIORITY)

Functions

void | DMA_ClearFlag (uint32_t DMAy_FLAG)
Clears the DMAy Channelx's pending flags.
void | DMA_ClearITPendingBit (uint32_t DMAy_IT)
Clears the DMAy Channelx's interrupt pending bits.
void | DMA_Cmd (DMA_Channel_TypeDef *DMAy_Channelx, FunctionalState NewState)
Enables or disables the specified DMAy Channelx.
void | DMA_DeInit (DMA_Channel_TypeDef *DMAy_Channelx)
Deinitializes the DMAy Channelx registers to their default reset values.
uint16_t | DMA_GetCurrDataCounter (DMA_Channel_TypeDef *DMAy_Channelx)
Returns the number of remaining data units in the current DMAy Channelx transfer.
FlagStatus | DMA_GetFlagStatus (uint32_t DMAy_FLAG)
Checks whether the specified DMAy Channelx flag is set or not.
ITStatus | DMA_GetITStatus (uint32_t DMAy_IT)
Checks whether the specified DMAy Channelx interrupt has occurred or not.
void | DMA_Init (DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitTypeDef *DMA_InitStruct)
Initializes the DMAy Channelx according to the specified parameters in the DMA_InitStruct.
void | DMA_ITConfig (DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)
Enables or disables the specified DMAy Channelx interrupts.
void | DMA_SetCurrDataCounter (DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber)
Sets the number of data units in the current DMAy Channelx transfer.
void | DMA_StructInit (DMA_InitTypeDef *DMA_InitStruct)
Fills each DMA_InitStruct member with its default value.

Detailed Description

This file contains all the functions prototypes for the DMA firmware library.

Author:
MCD Application Team
Version:
V3.5.0
Date:
11-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm32f10x_dma.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_exti.c File Reference

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Libraries
  • STM32F10x_StdPeriph_Driver
  • src
Defines | Functions

stm32f10x_exti.c File Reference

This file provides all the EXTI firmware functions. More...

#include "stm32f10x_exti.h"

Go to the source code of this file.

Defines

#define | EXTI_LINENONE ((uint32_t)0x00000)

Functions

void | EXTI_ClearFlag (uint32_t EXTI_Line)
Clears the EXTI's line pending flags.
void | EXTI_ClearITPendingBit (uint32_t EXTI_Line)
Clears the EXTI's line pending bits.
void | EXTI_DeInit (void)
Deinitializes the EXTI peripheral registers to their default reset values.
void | EXTI_GenerateSWInterrupt (uint32_t EXTI_Line)
Generates a Software interrupt.
FlagStatus | EXTI_GetFlagStatus (uint32_t EXTI_Line)
Checks whether the specified EXTI line flag is set or not.
ITStatus | EXTI_GetITStatus (uint32_t EXTI_Line)
Checks whether the specified EXTI line is asserted or not.
void | EXTI_Init (EXTI_InitTypeDef *EXTI_InitStruct)
Initializes the EXTI peripheral according to the specified parameters in the EXTI_InitStruct.
void | EXTI_StructInit (EXTI_InitTypeDef *EXTI_InitStruct)
Fills each EXTI_InitStruct member with its reset value.

Detailed Description

This file provides all the EXTI firmware functions.

Author:
MCD Application Team
Version:
V3.5.0
Date:
11-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm32f10x_exti.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_exti.h File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Libraries
  • STM32F10x_StdPeriph_Driver
  • inc
Data Structures | Defines | Enumerations | Functions

stm32f10x_exti.h File Reference

This file contains all the functions prototypes for the EXTI firmware library. More...

#include "stm32f10x.h"

Go to the source code of this file.

Data Structures

struct | EXTI_InitTypeDef
EXTI Init Structure definition. More...

Defines

#define | EXTI_Line0 ((uint32_t)0x00001)
#define | EXTI_Line1 ((uint32_t)0x00002)
#define | EXTI_Line10 ((uint32_t)0x00400)
#define | EXTI_Line11 ((uint32_t)0x00800)
#define | EXTI_Line12 ((uint32_t)0x01000)
#define | EXTI_Line13 ((uint32_t)0x02000)
#define | EXTI_Line14 ((uint32_t)0x04000)
#define | EXTI_Line15 ((uint32_t)0x08000)
#define | EXTI_Line16 ((uint32_t)0x10000)
#define | EXTI_Line17 ((uint32_t)0x20000)
#define | EXTI_Line18 ((uint32_t)0x40000)
#define | EXTI_Line19 ((uint32_t)0x80000)
#define | EXTI_Line2 ((uint32_t)0x00004)
#define | EXTI_Line3 ((uint32_t)0x00008)
#define | EXTI_Line4 ((uint32_t)0x00010)
#define | EXTI_Line5 ((uint32_t)0x00020)
#define | EXTI_Line6 ((uint32_t)0x00040)
#define | EXTI_Line7 ((uint32_t)0x00080)
#define | EXTI_Line8 ((uint32_t)0x00100)
#define | EXTI_Line9 ((uint32_t)0x00200)
#define | IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFFF00000) == 0x00) && ((LINE) != (uint16_t)0x00))
#define | IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))
#define | IS_EXTI_TRIGGER(TRIGGER)
#define | IS_GET_EXTI_LINE(LINE)

Enumerations

enum | EXTIMode_TypeDef { EXTI_Mode_Interrupt = 0x00, EXTI_Mode_Event = 0x04 }

EXTI mode enumeration.

More...
enum | EXTITrigger_TypeDef { EXTI_Trigger_Rising = 0x08, EXTI_Trigger_Falling = 0x0C, EXTI_Trigger_Rising_Falling = 0x10 }

EXTI Trigger enumeration.

More...

Functions

void | EXTI_ClearFlag (uint32_t EXTI_Line)
Clears the EXTI's line pending flags.
void | EXTI_ClearITPendingBit (uint32_t EXTI_Line)
Clears the EXTI's line pending bits.
void | EXTI_DeInit (void)
Deinitializes the EXTI peripheral registers to their default reset values.
void | EXTI_GenerateSWInterrupt (uint32_t EXTI_Line)
Generates a Software interrupt.
FlagStatus | EXTI_GetFlagStatus (uint32_t EXTI_Line)
Checks whether the specified EXTI line flag is set or not.
ITStatus | EXTI_GetITStatus (uint32_t EXTI_Line)
Checks whether the specified EXTI line is asserted or not.
void | EXTI_Init (EXTI_InitTypeDef *EXTI_InitStruct)
Initializes the EXTI peripheral according to the specified parameters in the EXTI_InitStruct.
void | EXTI_StructInit (EXTI_InitTypeDef *EXTI_InitStruct)
Fills each EXTI_InitStruct member with its reset value.

Detailed Description

This file contains all the functions prototypes for the EXTI firmware library.

Author:
MCD Application Team
Version:
V3.5.0
Date:
11-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm32f10x_exti.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_flash.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Libraries
  • STM32F10x_StdPeriph_Driver
  • src
Defines | Functions

stm32f10x_flash.c File Reference

This file provides all the FLASH firmware functions. More...

#include "stm32f10x_flash.h"

Go to the source code of this file.

Defines

#define | ACR_HLFCYA_Mask ((uint32_t)0xFFFFFFF7)
#define | ACR_LATENCY_Mask ((uint32_t)0x00000038)
#define | ACR_PRFTBE_Mask ((uint32_t)0xFFFFFFEF)
#define | ACR_PRFTBS_Mask ((uint32_t)0x00000020)
#define | CR_LOCK_Set ((uint32_t)0x00000080)
#define | CR_MER_Reset ((uint32_t)0x00001FFB)
#define | CR_MER_Set ((uint32_t)0x00000004)
#define | CR_OPTER_Reset ((uint32_t)0x00001FDF)
#define | CR_OPTER_Set ((uint32_t)0x00000020)
#define | CR_OPTPG_Reset ((uint32_t)0x00001FEF)
#define | CR_OPTPG_Set ((uint32_t)0x00000010)
#define | CR_PER_Reset ((uint32_t)0x00001FFD)
#define | CR_PER_Set ((uint32_t)0x00000002)
#define | CR_PG_Reset ((uint32_t)0x00001FFE)
#define | CR_PG_Set ((uint32_t)0x00000001)
#define | CR_STRT_Set ((uint32_t)0x00000040)
#define | EraseTimeout ((uint32_t)0x000B0000)
#define | FLASH_BANK1_END_ADDRESS ((uint32_t)0x807FFFF)
#define | FLASH_KEY1 ((uint32_t)0x45670123)
#define | FLASH_KEY2 ((uint32_t)0xCDEF89AB)
#define | OB_USER_BFB2 ((uint16_t)0x0008)
#define | ProgramTimeout ((uint32_t)0x00002000)
#define | RDP_Key ((uint16_t)0x00A5)
#define | RDPRT_Mask ((uint32_t)0x00000002)
#define | WRP0_Mask ((uint32_t)0x000000FF)
#define | WRP1_Mask ((uint32_t)0x0000FF00)
#define | WRP2_Mask ((uint32_t)0x00FF0000)
#define | WRP3_Mask ((uint32_t)0xFF000000)

Functions

void | FLASH_ClearFlag (uint32_t FLASH_FLAG)
Clears the FLASH's pending flags.
FLASH_Status | FLASH_EnableWriteProtection (uint32_t FLASH_Pages)
Write protects the desired pages.
FLASH_Status | FLASH_EraseAllBank1Pages (void)
Erases all Bank1 FLASH pages.
FLASH_Status | FLASH_EraseAllPages (void)
Erases all FLASH pages.
FLASH_Status | FLASH_EraseOptionBytes (void)
Erases the FLASH option bytes.
FLASH_Status | FLASH_ErasePage (uint32_t Page_Address)
Erases a specified FLASH page.
FLASH_Status | FLASH_GetBank1Status (void)
Returns the FLASH Bank1 Status.
FlagStatus | FLASH_GetFlagStatus (uint32_t FLASH_FLAG)
Checks whether the specified FLASH flag is set or not.
FlagStatus | FLASH_GetPrefetchBufferStatus (void)
Checks whether the FLASH Prefetch Buffer status is set or not.
FlagStatus | FLASH_GetReadOutProtectionStatus (void)
Checks whether the FLASH Read Out Protection Status is set or not.
FLASH_Status | FLASH_GetStatus (void)
Returns the FLASH Status.
uint32_t | FLASH_GetUserOptionByte (void)
Returns the FLASH User Option Bytes values.
uint32_t | FLASH_GetWriteProtectionOptionByte (void)
Returns the FLASH Write Protection Option Bytes Register value.
void | FLASH_HalfCycleAccessCmd (uint32_t FLASH_HalfCycleAccess)
Enables or disables the Half cycle flash access.
void | FLASH_ITConfig (uint32_t FLASH_IT, FunctionalState NewState)
Enables or disables the specified FLASH interrupts.
void | FLASH_Lock (void)
Locks the FLASH Program Erase Controller.
void | FLASH_LockBank1 (void)
Locks the FLASH Bank1 Program Erase Controller.
void | FLASH_PrefetchBufferCmd (uint32_t FLASH_PrefetchBuffer)
Enables or disables the Prefetch Buffer.
FLASH_Status | FLASH_ProgramHalfWord (uint32_t Address, uint16_t Data)
Programs a half word at a specified address.
FLASH_Status | FLASH_ProgramOptionByteData (uint32_t Address, uint8_t Data)
Programs a half word at a specified Option Byte Data address.
FLASH_Status | FLASH_ProgramWord (uint32_t Address, uint32_t Data)
Programs a word at a specified address.
FLASH_Status | FLASH_ReadOutProtection (FunctionalState NewState)
Enables or disables the read out protection.
void | FLASH_SetLatency (uint32_t FLASH_Latency)
Sets the code latency value.
void | FLASH_Unlock (void)
Unlocks the FLASH Program Erase Controller.
void | FLASH_UnlockBank1 (void)
Unlocks the FLASH Bank1 Program Erase Controller.
FLASH_Status | FLASH_UserOptionByteConfig (uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY)
Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
FLASH_Status | FLASH_WaitForLastBank1Operation (uint32_t Timeout)
Waits for a Flash operation on Bank1 to complete or a TIMEOUT to occur.
FLASH_Status | FLASH_WaitForLastOperation (uint32_t Timeout)
Waits for a Flash operation to complete or a TIMEOUT to occur.

Detailed Description

This file provides all the FLASH firmware functions.

Author:
MCD Application Team
Version:
V3.5.0
Date:
11-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm32f10x_flash.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_flash.h File Reference

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Libraries
  • STM32F10x_StdPeriph_Driver
  • inc
Defines | Enumerations | Functions

stm32f10x_flash.h File Reference

This file contains all the functions prototypes for the FLASH firmware library. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY
#define | FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP
#define | FLASH_FLAG_BANK1_PGERR FLASH_FLAG_PGERR
#define | FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR
#define | FLASH_FLAG_BSY ((uint32_t)0x00000001)
#define | FLASH_FLAG_EOP ((uint32_t)0x00000020)
#define | FLASH_FLAG_OPTERR ((uint32_t)0x00000001)
#define | FLASH_FLAG_PGERR ((uint32_t)0x00000004)
#define | FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010)
#define | FLASH_HalfCycleAccess_Disable ((uint32_t)0x00000000)
#define | FLASH_HalfCycleAccess_Enable ((uint32_t)0x00000008)
#define | FLASH_IT_BANK1_EOP FLASH_IT_EOP
#define | FLASH_IT_BANK1_ERROR FLASH_IT_ERROR
#define | FLASH_IT_EOP ((uint32_t)0x00001000)
#define | FLASH_IT_ERROR ((uint32_t)0x00000400)
#define | FLASH_Latency_0 ((uint32_t)0x00000000)
#define | FLASH_Latency_1 ((uint32_t)0x00000001)
#define | FLASH_Latency_2 ((uint32_t)0x00000002)
#define | FLASH_PrefetchBuffer_Disable ((uint32_t)0x00000000)
#define | FLASH_PrefetchBuffer_Enable ((uint32_t)0x00000010)
#define | FLASH_WRProt_AllPages ((uint32_t)0xFFFFFFFF)
#define | FLASH_WRProt_Pages0to1 ((uint32_t)0x00000001)
#define | FLASH_WRProt_Pages0to3 ((uint32_t)0x00000001)
#define | FLASH_WRProt_Pages100to103 ((uint32_t)0x02000000)
#define | FLASH_WRProt_Pages104to107 ((uint32_t)0x04000000)
#define | FLASH_WRProt_Pages108to111 ((uint32_t)0x08000000)
#define | FLASH_WRProt_Pages10to11 ((uint32_t)0x00000020)
#define | FLASH_WRProt_Pages112to115 ((uint32_t)0x10000000)
#define | FLASH_WRProt_Pages116to119 ((uint32_t)0x20000000)
#define | FLASH_WRProt_Pages120to123 ((uint32_t)0x40000000)
#define | FLASH_WRProt_Pages124to127 ((uint32_t)0x80000000)
#define | FLASH_WRProt_Pages12to13 ((uint32_t)0x00000040)
#define | FLASH_WRProt_Pages12to15 ((uint32_t)0x00000008)
#define | FLASH_WRProt_Pages14to15 ((uint32_t)0x00000080)
#define | FLASH_WRProt_Pages16to17 ((uint32_t)0x00000100)
#define | FLASH_WRProt_Pages16to19 ((uint32_t)0x00000010)
#define | FLASH_WRProt_Pages18to19 ((uint32_t)0x00000200)
#define | FLASH_WRProt_Pages20to21 ((uint32_t)0x00000400)
#define | FLASH_WRProt_Pages20to23 ((uint32_t)0x00000020)
#define | FLASH_WRProt_Pages22to23 ((uint32_t)0x00000800)
#define | FLASH_WRProt_Pages24to25 ((uint32_t)0x00001000)
#define | FLASH_WRProt_Pages24to27 ((uint32_t)0x00000040)
#define | FLASH_WRProt_Pages26to27 ((uint32_t)0x00002000)
#define | FLASH_WRProt_Pages28to29 ((uint32_t)0x00004000)
#define | FLASH_WRProt_Pages28to31 ((uint32_t)0x00000080)
#define | FLASH_WRProt_Pages2to3 ((uint32_t)0x00000002)
#define | FLASH_WRProt_Pages30to31 ((uint32_t)0x00008000)
#define | FLASH_WRProt_Pages32to33 ((uint32_t)0x00010000)
#define | FLASH_WRProt_Pages32to35 ((uint32_t)0x00000100)
#define | FLASH_WRProt_Pages34to35 ((uint32_t)0x00020000)
#define | FLASH_WRProt_Pages36to37 ((uint32_t)0x00040000)
#define | FLASH_WRProt_Pages36to39 ((uint32_t)0x00000200)
#define | FLASH_WRProt_Pages38to39 ((uint32_t)0x00080000)
#define | FLASH_WRProt_Pages40to41 ((uint32_t)0x00100000)
#define | FLASH_WRProt_Pages40to43 ((uint32_t)0x00000400)
#define | FLASH_WRProt_Pages42to43 ((uint32_t)0x00200000)
#define | FLASH_WRProt_Pages44to45 ((uint32_t)0x00400000)
#define | FLASH_WRProt_Pages44to47 ((uint32_t)0x00000800)
#define | FLASH_WRProt_Pages46to47 ((uint32_t)0x00800000)
#define | FLASH_WRProt_Pages48to49 ((uint32_t)0x01000000)
#define | FLASH_WRProt_Pages48to51 ((uint32_t)0x00001000)
#define | FLASH_WRProt_Pages4to5 ((uint32_t)0x00000004)
#define | FLASH_WRProt_Pages4to7 ((uint32_t)0x00000002)
#define | FLASH_WRProt_Pages50to51 ((uint32_t)0x02000000)
#define | FLASH_WRProt_Pages52to53 ((uint32_t)0x04000000)
#define | FLASH_WRProt_Pages52to55 ((uint32_t)0x00002000)
#define | FLASH_WRProt_Pages54to55 ((uint32_t)0x08000000)
#define | FLASH_WRProt_Pages56to57 ((uint32_t)0x10000000)
#define | FLASH_WRProt_Pages56to59 ((uint32_t)0x00004000)
#define | FLASH_WRProt_Pages58to59 ((uint32_t)0x20000000)
#define | FLASH_WRProt_Pages60to61 ((uint32_t)0x40000000)
#define | FLASH_WRProt_Pages60to63 ((uint32_t)0x00008000)
#define | FLASH_WRProt_Pages62to127 ((uint32_t)0x80000000)
#define | FLASH_WRProt_Pages62to255 ((uint32_t)0x80000000)
#define | FLASH_WRProt_Pages62to511 ((uint32_t)0x80000000)
#define | FLASH_WRProt_Pages64to67 ((uint32_t)0x00010000)
#define | FLASH_WRProt_Pages68to71 ((uint32_t)0x00020000)
#define | FLASH_WRProt_Pages6to7 ((uint32_t)0x00000008)
#define | FLASH_WRProt_Pages72to75 ((uint32_t)0x00040000)
#define | FLASH_WRProt_Pages76to79 ((uint32_t)0x00080000)
#define | FLASH_WRProt_Pages80to83 ((uint32_t)0x00100000)
#define | FLASH_WRProt_Pages84to87 ((uint32_t)0x00200000)
#define | FLASH_WRProt_Pages88to91 ((uint32_t)0x00400000)
#define | FLASH_WRProt_Pages8to11 ((uint32_t)0x00000004)
#define | FLASH_WRProt_Pages8to9 ((uint32_t)0x00000010)
#define | FLASH_WRProt_Pages92to95 ((uint32_t)0x00800000)
#define | FLASH_WRProt_Pages96to99 ((uint32_t)0x01000000)
#define | IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x080FFFFF))
#define | IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000))
#define | IS_FLASH_GET_FLAG(FLAG)
#define | IS_FLASH_HALFCYCLEACCESS_STATE(STATE)
#define | IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFFEBFF) == 0x00000000) && (((IT) != 0x00000000)))
#define | IS_FLASH_LATENCY(LATENCY)
#define | IS_FLASH_PREFETCHBUFFER_STATE(STATE)
#define | IS_FLASH_WRPROT_PAGE(PAGE) (((PAGE) != 0x00000000))
#define | IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == 0x1FFFF804) || ((ADDRESS) == 0x1FFFF806))
#define | IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
#define | IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST))
#define | IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST))
#define | OB_IWDG_HW ((uint16_t)0x0000)
#define | OB_IWDG_SW ((uint16_t)0x0001)
#define | OB_STDBY_NoRST ((uint16_t)0x0004)
#define | OB_STDBY_RST ((uint16_t)0x0000)
#define | OB_STOP_NoRST ((uint16_t)0x0002)
#define | OB_STOP_RST ((uint16_t)0x0000)

Enumerations

enum FLASH_Status {
FLASH_BUSY = 1, FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE,
FLASH_TIMEOUT
}

FLASH Status.

More...

Functions

void | FLASH_ClearFlag (uint32_t FLASH_FLAG)
Clears the FLASH's pending flags.
FLASH_Status | FLASH_EnableWriteProtection (uint32_t FLASH_Pages)
Write protects the desired pages.
FLASH_Status | FLASH_EraseAllBank1Pages (void)
Erases all Bank1 FLASH pages.
FLASH_Status | FLASH_EraseAllPages (void)
Erases all FLASH pages.
FLASH_Status | FLASH_EraseOptionBytes (void)
Erases the FLASH option bytes.
FLASH_Status | FLASH_ErasePage (uint32_t Page_Address)
Erases a specified FLASH page.
FLASH_Status | FLASH_GetBank1Status (void)
Returns the FLASH Bank1 Status.
FlagStatus | FLASH_GetFlagStatus (uint32_t FLASH_FLAG)
Checks whether the specified FLASH flag is set or not.
FlagStatus | FLASH_GetPrefetchBufferStatus (void)
Checks whether the FLASH Prefetch Buffer status is set or not.
FlagStatus | FLASH_GetReadOutProtectionStatus (void)
Checks whether the FLASH Read Out Protection Status is set or not.
FLASH_Status | FLASH_GetStatus (void)
Returns the FLASH Status.
uint32_t | FLASH_GetUserOptionByte (void)
Returns the FLASH User Option Bytes values.
uint32_t | FLASH_GetWriteProtectionOptionByte (void)
Returns the FLASH Write Protection Option Bytes Register value.
void | FLASH_HalfCycleAccessCmd (uint32_t FLASH_HalfCycleAccess)
Enables or disables the Half cycle flash access.
void | FLASH_ITConfig (uint32_t FLASH_IT, FunctionalState NewState)
Enables or disables the specified FLASH interrupts.
void | FLASH_Lock (void)
Locks the FLASH Program Erase Controller.
void | FLASH_LockBank1 (void)
Locks the FLASH Bank1 Program Erase Controller.
void | FLASH_PrefetchBufferCmd (uint32_t FLASH_PrefetchBuffer)
Enables or disables the Prefetch Buffer.
FLASH_Status | FLASH_ProgramHalfWord (uint32_t Address, uint16_t Data)
Programs a half word at a specified address.
FLASH_Status | FLASH_ProgramOptionByteData (uint32_t Address, uint8_t Data)
Programs a half word at a specified Option Byte Data address.
FLASH_Status | FLASH_ProgramWord (uint32_t Address, uint32_t Data)
Programs a word at a specified address.
FLASH_Status | FLASH_ReadOutProtection (FunctionalState NewState)
Enables or disables the read out protection.
void | FLASH_SetLatency (uint32_t FLASH_Latency)
Sets the code latency value.
void | FLASH_Unlock (void)
Unlocks the FLASH Program Erase Controller.
void | FLASH_UnlockBank1 (void)
Unlocks the FLASH Bank1 Program Erase Controller.
FLASH_Status | FLASH_UserOptionByteConfig (uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY)
Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
FLASH_Status | FLASH_WaitForLastBank1Operation (uint32_t Timeout)
Waits for a Flash operation on Bank1 to complete or a TIMEOUT to occur.
FLASH_Status | FLASH_WaitForLastOperation (uint32_t Timeout)
Waits for a Flash operation to complete or a TIMEOUT to occur.

Detailed Description

This file contains all the functions prototypes for the FLASH firmware library.

Author:
MCD Application Team
Version:
V3.5.0
Date:
11-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm32f10x_flash.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_fsmc.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Libraries
  • STM32F10x_StdPeriph_Driver
  • src
Defines | Functions

stm32f10x_fsmc.c File Reference

This file provides all the FSMC firmware functions. More...

#include "stm32f10x_fsmc.h"
#include "stm32f10x_rcc.h"

Go to the source code of this file.

Defines

#define | BCR_FACCEN_Set ((uint32_t)0x00000040)
#define | BCR_MBKEN_Reset ((uint32_t)0x000FFFFE)
#define | BCR_MBKEN_Set ((uint32_t)0x00000001)
#define | PCR_ECCEN_Reset ((uint32_t)0x000FFFBF)
#define | PCR_ECCEN_Set ((uint32_t)0x00000040)
#define | PCR_MemoryType_NAND ((uint32_t)0x00000008)
#define | PCR_PBKEN_Reset ((uint32_t)0x000FFFFB)
#define | PCR_PBKEN_Set ((uint32_t)0x00000004)

Functions

void | FSMC_ClearFlag (uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
Clears the FSMC's pending flags.
void | FSMC_ClearITPendingBit (uint32_t FSMC_Bank, uint32_t FSMC_IT)
Clears the FSMC's interrupt pending bits.
uint32_t | FSMC_GetECC (uint32_t FSMC_Bank)
Returns the error correction code register value.
FlagStatus | FSMC_GetFlagStatus (uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
Checks whether the specified FSMC flag is set or not.
ITStatus | FSMC_GetITStatus (uint32_t FSMC_Bank, uint32_t FSMC_IT)
Checks whether the specified FSMC interrupt has occurred or not.
void | FSMC_ITConfig (uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState)
Enables or disables the specified FSMC interrupts.
void | FSMC_NANDCmd (uint32_t FSMC_Bank, FunctionalState NewState)
Enables or disables the specified NAND Memory Bank.
void | FSMC_NANDDeInit (uint32_t FSMC_Bank)
Deinitializes the FSMC NAND Banks registers to their default reset values.
void | FSMC_NANDECCCmd (uint32_t FSMC_Bank, FunctionalState NewState)
Enables or disables the FSMC NAND ECC feature.
void | FSMC_NANDInit (FSMC_NANDInitTypeDef *FSMC_NANDInitStruct)
Initializes the FSMC NAND Banks according to the specified parameters in the FSMC_NANDInitStruct.
void | FSMC_NANDStructInit (FSMC_NANDInitTypeDef *FSMC_NANDInitStruct)
Fills each FSMC_NANDInitStruct member with its default value.
void | FSMC_NORSRAMCmd (uint32_t FSMC_Bank, FunctionalState NewState)
Enables or disables the specified NOR/SRAM Memory Bank.
void | FSMC_NORSRAMDeInit (uint32_t FSMC_Bank)
Deinitializes the FSMC NOR/SRAM Banks registers to their default reset values.
void | FSMC_NORSRAMInit (FSMC_NORSRAMInitTypeDef *FSMC_NORSRAMInitStruct)
Initializes the FSMC NOR/SRAM Banks according to the specified parameters in the FSMC_NORSRAMInitStruct.
void | FSMC_NORSRAMStructInit (FSMC_NORSRAMInitTypeDef *FSMC_NORSRAMInitStruct)
Fills each FSMC_NORSRAMInitStruct member with its default value.
void | FSMC_PCCARDCmd (FunctionalState NewState)
Enables or disables the PCCARD Memory Bank.
void | FSMC_PCCARDDeInit (void)
Deinitializes the FSMC PCCARD Bank registers to their default reset values.
void | FSMC_PCCARDInit (FSMC_PCCARDInitTypeDef *FSMC_PCCARDInitStruct)
Initializes the FSMC PCCARD Bank according to the specified parameters in the FSMC_PCCARDInitStruct.
void | FSMC_PCCARDStructInit (FSMC_PCCARDInitTypeDef *FSMC_PCCARDInitStruct)
Fills each FSMC_PCCARDInitStruct member with its default value.

Detailed Description

This file provides all the FSMC firmware functions.

Author:
MCD Application Team
Version:
V3.5.0
Date:
11-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm32f10x_fsmc.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_fsmc.h File Reference

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
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Data Structures | Defines | Functions

stm32f10x_fsmc.h File Reference

This file contains all the functions prototypes for the FSMC firmware library. More...

#include "stm32f10x.h"

Go to the source code of this file.

Data Structures

struct | FSMC_NAND_PCCARDTimingInitTypeDef
Timing parameters For FSMC NAND and PCCARD Banks. More...
struct | FSMC_NANDInitTypeDef
FSMC NAND Init structure definition. More...
struct | FSMC_NORSRAMInitTypeDef
FSMC NOR/SRAM Init structure definition. More...
struct | FSMC_NORSRAMTimingInitTypeDef
Timing parameters For NOR/SRAM Banks. More...
struct | FSMC_PCCARDInitTypeDef
FSMC PCCARD Init structure definition. More...

Defines

#define | FSMC_AccessMode_A ((uint32_t)0x00000000)
#define | FSMC_AccessMode_B ((uint32_t)0x10000000)
#define | FSMC_AccessMode_C ((uint32_t)0x20000000)
#define | FSMC_AccessMode_D ((uint32_t)0x30000000)
#define | FSMC_AsynchronousWait_Disable ((uint32_t)0x00000000)
#define | FSMC_AsynchronousWait_Enable ((uint32_t)0x00008000)
#define | FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000)
#define | FSMC_Bank1_NORSRAM2 ((uint32_t)0x00000002)
#define | FSMC_Bank1_NORSRAM3 ((uint32_t)0x00000004)
#define | FSMC_Bank1_NORSRAM4 ((uint32_t)0x00000006)
#define | FSMC_Bank2_NAND ((uint32_t)0x00000010)
#define | FSMC_Bank3_NAND ((uint32_t)0x00000100)
#define | FSMC_Bank4_PCCARD ((uint32_t)0x00001000)
#define | FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000)
#define | FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100)
#define | FSMC_DataAddressMux_Disable ((uint32_t)0x00000000)
#define | FSMC_DataAddressMux_Enable ((uint32_t)0x00000002)
#define | FSMC_ECC_Disable ((uint32_t)0x00000000)
#define | FSMC_ECC_Enable ((uint32_t)0x00000040)
#define | FSMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000)
#define | FSMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000)
#define | FSMC_ECCPageSize_256Bytes ((uint32_t)0x00000000)
#define | FSMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000)
#define | FSMC_ECCPageSize_512Bytes ((uint32_t)0x00020000)
#define | FSMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000)
#define | FSMC_ExtendedMode_Disable ((uint32_t)0x00000000)
#define | FSMC_ExtendedMode_Enable ((uint32_t)0x00004000)
#define | FSMC_FLAG_FallingEdge ((uint32_t)0x00000004)
#define | FSMC_FLAG_FEMPT ((uint32_t)0x00000040)
#define | FSMC_FLAG_Level ((uint32_t)0x00000002)
#define | FSMC_FLAG_RisingEdge ((uint32_t)0x00000001)
#define | FSMC_IT_FallingEdge ((uint32_t)0x00000020)
#define | FSMC_IT_Level ((uint32_t)0x00000010)
#define | FSMC_IT_RisingEdge ((uint32_t)0x00000008)
#define | FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010)
#define | FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000)
#define | FSMC_MemoryType_NOR ((uint32_t)0x00000008)
#define | FSMC_MemoryType_PSRAM ((uint32_t)0x00000004)
#define | FSMC_MemoryType_SRAM ((uint32_t)0x00000000)
#define | FSMC_Waitfeature_Disable ((uint32_t)0x00000000)
#define | FSMC_Waitfeature_Enable ((uint32_t)0x00000002)
#define | FSMC_WaitSignal_Disable ((uint32_t)0x00000000)
#define | FSMC_WaitSignal_Enable ((uint32_t)0x00002000)
#define | FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000)
#define | FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800)
#define | FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200)
#define | FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000)
#define | FSMC_WrapMode_Disable ((uint32_t)0x00000000)
#define | FSMC_WrapMode_Enable ((uint32_t)0x00000400)
#define | FSMC_WriteBurst_Disable ((uint32_t)0x00000000)
#define | FSMC_WriteBurst_Enable ((uint32_t)0x00080000)
#define | FSMC_WriteOperation_Disable ((uint32_t)0x00000000)
#define | FSMC_WriteOperation_Enable ((uint32_t)0x00001000)
#define | IS_FSMC_ACCESS_MODE(MODE)
#define | IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF)
#define | IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF)
#define | IS_FSMC_ASYNWAIT(STATE)
#define | IS_FSMC_BURSTMODE(STATE)
#define | IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
#define | IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF)
#define | IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF)
#define | IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF))
#define | IS_FSMC_ECC_STATE(STATE)
#define | IS_FSMC_ECCPAGE_SIZE(SIZE)
#define | IS_FSMC_EXTENDED_MODE(MODE)
#define | IS_FSMC_GET_FLAG(FLAG)
#define | IS_FSMC_GET_IT(IT)
#define | IS_FSMC_GETFLAG_BANK(BANK)
#define | IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF)
#define | IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF)
#define | IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000))
#define | IS_FSMC_IT_BANK(BANK)
#define | IS_FSMC_MEMORY(MEMORY)
#define | IS_FSMC_MEMORY_WIDTH(WIDTH)
#define | IS_FSMC_MUX(MUX)
#define | IS_FSMC_NAND_BANK(BANK)
#define | IS_FSMC_NORSRAM_BANK(BANK)
#define | IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF)
#define | IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF)
#define | IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF)
#define | IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF)
#define | IS_FSMC_WAIT_FEATURE(FEATURE)
#define | IS_FSMC_WAIT_POLARITY(POLARITY)
#define | IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE)
#define | IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF)
#define | IS_FSMC_WAITE_SIGNAL(SIGNAL)
#define | IS_FSMC_WRAP_MODE(MODE)
#define | IS_FSMC_WRITE_BURST(BURST)
#define | IS_FSMC_WRITE_OPERATION(OPERATION)

Functions

void | FSMC_ClearFlag (uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
Clears the FSMC's pending flags.
void | FSMC_ClearITPendingBit (uint32_t FSMC_Bank, uint32_t FSMC_IT)
Clears the FSMC's interrupt pending bits.
uint32_t | FSMC_GetECC (uint32_t FSMC_Bank)
Returns the error correction code register value.
FlagStatus | FSMC_GetFlagStatus (uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
Checks whether the specified FSMC flag is set or not.
ITStatus | FSMC_GetITStatus (uint32_t FSMC_Bank, uint32_t FSMC_IT)
Checks whether the specified FSMC interrupt has occurred or not.
void | FSMC_ITConfig (uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState)
Enables or disables the specified FSMC interrupts.
void | FSMC_NANDCmd (uint32_t FSMC_Bank, FunctionalState NewState)
Enables or disables the specified NAND Memory Bank.
void | FSMC_NANDDeInit (uint32_t FSMC_Bank)
Deinitializes the FSMC NAND Banks registers to their default reset values.
void | FSMC_NANDECCCmd (uint32_t FSMC_Bank, FunctionalState NewState)
Enables or disables the FSMC NAND ECC feature.
void | FSMC_NANDInit (FSMC_NANDInitTypeDef *FSMC_NANDInitStruct)
Initializes the FSMC NAND Banks according to the specified parameters in the FSMC_NANDInitStruct.
void | FSMC_NANDStructInit (FSMC_NANDInitTypeDef *FSMC_NANDInitStruct)
Fills each FSMC_NANDInitStruct member with its default value.
void | FSMC_NORSRAMCmd (uint32_t FSMC_Bank, FunctionalState NewState)
Enables or disables the specified NOR/SRAM Memory Bank.
void | FSMC_NORSRAMDeInit (uint32_t FSMC_Bank)
Deinitializes the FSMC NOR/SRAM Banks registers to their default reset values.
void | FSMC_NORSRAMInit (FSMC_NORSRAMInitTypeDef *FSMC_NORSRAMInitStruct)
Initializes the FSMC NOR/SRAM Banks according to the specified parameters in the FSMC_NORSRAMInitStruct.
void | FSMC_NORSRAMStructInit (FSMC_NORSRAMInitTypeDef *FSMC_NORSRAMInitStruct)
Fills each FSMC_NORSRAMInitStruct member with its default value.
void | FSMC_PCCARDCmd (FunctionalState NewState)
Enables or disables the PCCARD Memory Bank.
void | FSMC_PCCARDDeInit (void)
Deinitializes the FSMC PCCARD Bank registers to their default reset values.
void | FSMC_PCCARDInit (FSMC_PCCARDInitTypeDef *FSMC_PCCARDInitStruct)
Initializes the FSMC PCCARD Bank according to the specified parameters in the FSMC_PCCARDInitStruct.
void | FSMC_PCCARDStructInit (FSMC_PCCARDInitTypeDef *FSMC_PCCARDInitStruct)
Fills each FSMC_PCCARDInitStruct member with its default value.

Detailed Description

This file contains all the functions prototypes for the FSMC firmware library.

Author:
MCD Application Team
Version:
V3.5.0
Date:
11-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm32f10x_fsmc.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_gpio.c File Reference

  • File List
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  • STM32F10x_StdPeriph_Driver
  • src
Defines | Functions

stm32f10x_gpio.c File Reference

This file provides all the GPIO firmware functions. More...

#include "stm32f10x_gpio.h"
#include "stm32f10x_rcc.h"

Go to the source code of this file.

Defines

#define | AFIO_OFFSET (AFIO_BASE - PERIPH_BASE)
#define | DBGAFR_LOCATION_MASK ((uint32_t)0x00200000)
#define | DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000)
#define | DBGAFR_POSITION_MASK ((uint32_t)0x000F0000)
#define | DBGAFR_SWJCFG_MASK ((uint32_t)0xF0FFFFFF)
#define | EVCR_EVOE_BB (PERIPH_BB_BASE + (EVCR_OFFSET * 32) + (EVOE_BitNumber * 4))
#define | EVCR_OFFSET (AFIO_OFFSET + 0x00)
#define | EVCR_PORTPINCONFIG_MASK ((uint16_t)0xFF80)
#define | EVOE_BitNumber ((uint8_t)0x07)
#define | LSB_MASK ((uint16_t)0xFFFF)
#define | MAPR_MII_RMII_SEL_BB (PERIPH_BB_BASE + (MAPR_OFFSET * 32) + (MII_RMII_SEL_BitNumber * 4))
#define | MAPR_OFFSET (AFIO_OFFSET + 0x04)
#define | MII_RMII_SEL_BitNumber ((u8)0x17)

Functions

void | GPIO_AFIODeInit (void)
Deinitializes the Alternate Functions (remap, event control and EXTI configuration) registers to their default reset values.
void | GPIO_DeInit (GPIO_TypeDef *GPIOx)
Deinitializes the GPIOx peripheral registers to their default reset values.
void | GPIO_ETH_MediaInterfaceConfig (uint32_t GPIO_ETH_MediaInterface)
Selects the Ethernet media interface.
void | GPIO_EventOutputCmd (FunctionalState NewState)
Enables or disables the Event Output.
void | GPIO_EventOutputConfig (uint8_t GPIO_PortSource, uint8_t GPIO_PinSource)
Selects the GPIO pin used as Event output.
void | GPIO_EXTILineConfig (uint8_t GPIO_PortSource, uint8_t GPIO_PinSource)
Selects the GPIO pin used as EXTI Line.
void | GPIO_Init (GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct)
Initializes the GPIOx peripheral according to the specified parameters in the GPIO_InitStruct.
void | GPIO_PinLockConfig (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Locks GPIO Pins configuration registers.
void | GPIO_PinRemapConfig (uint32_t GPIO_Remap, FunctionalState NewState)
Changes the mapping of the specified pin.
uint16_t | GPIO_ReadInputData (GPIO_TypeDef *GPIOx)
Reads the specified GPIO input data port.
uint8_t | GPIO_ReadInputDataBit (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Reads the specified input port pin.
uint16_t | GPIO_ReadOutputData (GPIO_TypeDef *GPIOx)
Reads the specified GPIO output data port.
uint8_t | GPIO_ReadOutputDataBit (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Reads the specified output data port bit.
void | GPIO_ResetBits (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Clears the selected data port bits.
void | GPIO_SetBits (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Sets the selected data port bits.
void | GPIO_StructInit (GPIO_InitTypeDef *GPIO_InitStruct)
Fills each GPIO_InitStruct member with its default value.
void | GPIO_Write (GPIO_TypeDef *GPIOx, uint16_t PortVal)
Writes data to the specified GPIO data port.
void | GPIO_WriteBit (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
Sets or clears the selected data port bit.

Detailed Description

This file provides all the GPIO firmware functions.

Author:
MCD Application Team
Version:
V3.5.0
Date:
11-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm32f10x_gpio.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_gpio.h File Reference

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
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  • inc
Data Structures | Defines | Enumerations | Functions

stm32f10x_gpio.h File Reference

This file contains all the functions prototypes for the GPIO firmware library. More...

#include "stm32f10x.h"

Go to the source code of this file.

Data Structures

struct | GPIO_InitTypeDef
GPIO Init structure definition. More...

Defines

#define | GPIO_ETH_MediaInterface_MII ((u32)0x00000000)
#define | GPIO_ETH_MediaInterface_RMII ((u32)0x00000001)
#define | GPIO_FullRemap_TIM1 ((uint32_t)0x001600C0)
#define | GPIO_FullRemap_TIM2 ((uint32_t)0x00180300)
#define | GPIO_FullRemap_TIM3 ((uint32_t)0x001A0C00)
#define | GPIO_FullRemap_USART3 ((uint32_t)0x00140030)
#define | GPIO_PartialRemap1_TIM2 ((uint32_t)0x00180100)
#define | GPIO_PartialRemap2_TIM2 ((uint32_t)0x00180200)
#define | GPIO_PartialRemap_TIM1 ((uint32_t)0x00160040)
#define | GPIO_PartialRemap_TIM3 ((uint32_t)0x001A0800)
#define | GPIO_PartialRemap_USART3 ((uint32_t)0x00140010)
#define | GPIO_Pin_0 ((uint16_t)0x0001)
#define | GPIO_Pin_1 ((uint16_t)0x0002)
#define | GPIO_Pin_10 ((uint16_t)0x0400)
#define | GPIO_Pin_11 ((uint16_t)0x0800)
#define | GPIO_Pin_12 ((uint16_t)0x1000)
#define | GPIO_Pin_13 ((uint16_t)0x2000)
#define | GPIO_Pin_14 ((uint16_t)0x4000)
#define | GPIO_Pin_15 ((uint16_t)0x8000)
#define | GPIO_Pin_2 ((uint16_t)0x0004)
#define | GPIO_Pin_3 ((uint16_t)0x0008)
#define | GPIO_Pin_4 ((uint16_t)0x0010)
#define | GPIO_Pin_5 ((uint16_t)0x0020)
#define | GPIO_Pin_6 ((uint16_t)0x0040)
#define | GPIO_Pin_7 ((uint16_t)0x0080)
#define | GPIO_Pin_8 ((uint16_t)0x0100)
#define | GPIO_Pin_9 ((uint16_t)0x0200)
#define | GPIO_Pin_All ((uint16_t)0xFFFF)
#define | GPIO_PinSource0 ((uint8_t)0x00)
#define | GPIO_PinSource1 ((uint8_t)0x01)
#define | GPIO_PinSource10 ((uint8_t)0x0A)
#define | GPIO_PinSource11 ((uint8_t)0x0B)
#define | GPIO_PinSource12 ((uint8_t)0x0C)
#define | GPIO_PinSource13 ((uint8_t)0x0D)
#define | GPIO_PinSource14 ((uint8_t)0x0E)
#define | GPIO_PinSource15 ((uint8_t)0x0F)
#define | GPIO_PinSource2 ((uint8_t)0x02)
#define | GPIO_PinSource3 ((uint8_t)0x03)
#define | GPIO_PinSource4 ((uint8_t)0x04)
#define | GPIO_PinSource5 ((uint8_t)0x05)
#define | GPIO_PinSource6 ((uint8_t)0x06)
#define | GPIO_PinSource7 ((uint8_t)0x07)
#define | GPIO_PinSource8 ((uint8_t)0x08)
#define | GPIO_PinSource9 ((uint8_t)0x09)
#define | GPIO_PortSourceGPIOA ((uint8_t)0x00)
#define | GPIO_PortSourceGPIOB ((uint8_t)0x01)
#define | GPIO_PortSourceGPIOC ((uint8_t)0x02)
#define | GPIO_PortSourceGPIOD ((uint8_t)0x03)
#define | GPIO_PortSourceGPIOE ((uint8_t)0x04)
#define | GPIO_PortSourceGPIOF ((uint8_t)0x05)
#define | GPIO_PortSourceGPIOG ((uint8_t)0x06)
#define | GPIO_Remap1_CAN1 ((uint32_t)0x001D4000)
#define | GPIO_Remap2_CAN1 ((uint32_t)0x001D6000)
#define | GPIO_Remap_ADC1_ETRGINJ ((uint32_t)0x00200002)
#define | GPIO_Remap_ADC1_ETRGREG ((uint32_t)0x00200004)
#define | GPIO_Remap_ADC2_ETRGINJ ((uint32_t)0x00200008)
#define | GPIO_Remap_ADC2_ETRGREG ((uint32_t)0x00200010)
#define | GPIO_Remap_CAN2 ((uint32_t)0x00200040)
#define | GPIO_Remap_CEC ((uint32_t)0x80000008)
#define | GPIO_Remap_ETH ((uint32_t)0x00200020)
#define | GPIO_Remap_FSMC_NADV ((uint32_t)0x80000400)
#define | GPIO_Remap_I2C1 ((uint32_t)0x00000002)
#define | GPIO_Remap_MISC ((uint32_t)0x80002000)
#define | GPIO_Remap_PD01 ((uint32_t)0x00008000)
#define | GPIO_Remap_PTP_PPS ((uint32_t)0x00204000)
#define | GPIO_Remap_SPI1 ((uint32_t)0x00000001)
#define | GPIO_Remap_SPI3 ((uint32_t)0x00201100)
#define | GPIO_Remap_SWJ_Disable ((uint32_t)0x00300400)
#define | GPIO_Remap_SWJ_JTAGDisable ((uint32_t)0x00300200)
#define | GPIO_Remap_SWJ_NoJTRST ((uint32_t)0x00300100)
#define | GPIO_Remap_TIM10 ((uint32_t)0x80000040)
#define | GPIO_Remap_TIM11 ((uint32_t)0x80000080)
#define | GPIO_Remap_TIM12 ((uint32_t)0x80001000)
#define | GPIO_Remap_TIM13 ((uint32_t)0x80000100)
#define | GPIO_Remap_TIM14 ((uint32_t)0x80000200)
#define | GPIO_Remap_TIM15 ((uint32_t)0x80000001)
#define | GPIO_Remap_TIM16 ((uint32_t)0x80000002)
#define | GPIO_Remap_TIM17 ((uint32_t)0x80000004)
#define | GPIO_Remap_TIM1_DMA ((uint32_t)0x80000010)
#define | GPIO_Remap_TIM2ITR1_PTP_SOF ((uint32_t)0x00202000)
#define | GPIO_Remap_TIM4 ((uint32_t)0x00001000)
#define | GPIO_Remap_TIM5CH4_LSI ((uint32_t)0x00200001)
#define | GPIO_Remap_TIM67_DAC_DMA ((uint32_t)0x80000800)
#define | GPIO_Remap_TIM9 ((uint32_t)0x80000020)
#define | GPIO_Remap_USART1 ((uint32_t)0x00000004)
#define | GPIO_Remap_USART2 ((uint32_t)0x00000008)
#define | IS_GET_GPIO_PIN(PIN)
#define | IS_GPIO_ALL_PERIPH(PERIPH)
#define | IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))
#define | IS_GPIO_ETH_MEDIA_INTERFACE(INTERFACE)
#define | IS_GPIO_EVENTOUT_PORT_SOURCE(PORTSOURCE)
#define | IS_GPIO_EXTI_PORT_SOURCE(PORTSOURCE)
#define | IS_GPIO_MODE(MODE)
#define | IS_GPIO_PIN(PIN) ((((PIN) & (uint16_t)0x00) == 0x00) && ((PIN) != (uint16_t)0x00))
#define | IS_GPIO_PIN_SOURCE(PINSOURCE)
#define | IS_GPIO_REMAP(REMAP)
#define | IS_GPIO_SPEED(SPEED)

Enumerations

enum | BitAction { Bit_RESET = 0, Bit_SET }

Bit_SET and Bit_RESET enumeration.

More...
enum GPIOMode_TypeDef {
GPIO_Mode_AIN = 0x0, GPIO_Mode_IN_FLOATING = 0x04, GPIO_Mode_IPD = 0x28, GPIO_Mode_IPU = 0x48,
GPIO_Mode_Out_OD = 0x14, GPIO_Mode_Out_PP = 0x10, GPIO_Mode_AF_OD = 0x1C, GPIO_Mode_AF_PP = 0x18
}

Configuration Mode enumeration.

More...
enum | GPIOSpeed_TypeDef { GPIO_Speed_10MHz = 1, GPIO_Speed_2MHz, GPIO_Speed_50MHz }

Output Maximum frequency selection.

More...

Functions

void | GPIO_AFIODeInit (void)
Deinitializes the Alternate Functions (remap, event control and EXTI configuration) registers to their default reset values.
void | GPIO_DeInit (GPIO_TypeDef *GPIOx)
Deinitializes the GPIOx peripheral registers to their default reset values.
void | GPIO_ETH_MediaInterfaceConfig (uint32_t GPIO_ETH_MediaInterface)
Selects the Ethernet media interface.
void | GPIO_EventOutputCmd (FunctionalState NewState)
Enables or disables the Event Output.
void | GPIO_EventOutputConfig (uint8_t GPIO_PortSource, uint8_t GPIO_PinSource)
Selects the GPIO pin used as Event output.
void | GPIO_EXTILineConfig (uint8_t GPIO_PortSource, uint8_t GPIO_PinSource)
Selects the GPIO pin used as EXTI Line.
void | GPIO_Init (GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct)
Initializes the GPIOx peripheral according to the specified parameters in the GPIO_InitStruct.
void | GPIO_PinLockConfig (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Locks GPIO Pins configuration registers.
void | GPIO_PinRemapConfig (uint32_t GPIO_Remap, FunctionalState NewState)
Changes the mapping of the specified pin.
uint16_t | GPIO_ReadInputData (GPIO_TypeDef *GPIOx)
Reads the specified GPIO input data port.
uint8_t | GPIO_ReadInputDataBit (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Reads the specified input port pin.
uint16_t | GPIO_ReadOutputData (GPIO_TypeDef *GPIOx)
Reads the specified GPIO output data port.
uint8_t | GPIO_ReadOutputDataBit (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Reads the specified output data port bit.
void | GPIO_ResetBits (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Clears the selected data port bits.
void | GPIO_SetBits (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Sets the selected data port bits.
void | GPIO_StructInit (GPIO_InitTypeDef *GPIO_InitStruct)
Fills each GPIO_InitStruct member with its default value.
void | GPIO_Write (GPIO_TypeDef *GPIOx, uint16_t PortVal)
Writes data to the specified GPIO data port.
void | GPIO_WriteBit (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
Sets or clears the selected data port bit.

Detailed Description

This file contains all the functions prototypes for the GPIO firmware library.

Author:
MCD Application Team
Version:
V3.5.0
Date:
11-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm32f10x_gpio.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_i2c.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Libraries
  • STM32F10x_StdPeriph_Driver
  • src
Defines | Functions

stm32f10x_i2c.c File Reference

This file provides all the I2C firmware functions. More...

#include "stm32f10x_i2c.h"
#include "stm32f10x_rcc.h"

Go to the source code of this file.

Defines

#define | CCR_CCR_Set ((uint16_t)0x0FFF)
#define | CCR_FS_Set ((uint16_t)0x8000)
#define | CR1_ACK_Reset ((uint16_t)0xFBFF)
#define | CR1_ACK_Set ((uint16_t)0x0400)
#define | CR1_CLEAR_Mask ((uint16_t)0xFBF5)
#define | CR1_ENARP_Reset ((uint16_t)0xFFEF)
#define | CR1_ENARP_Set ((uint16_t)0x0010)
#define | CR1_ENGC_Reset ((uint16_t)0xFFBF)
#define | CR1_ENGC_Set ((uint16_t)0x0040)
#define | CR1_ENPEC_Reset ((uint16_t)0xFFDF)
#define | CR1_ENPEC_Set ((uint16_t)0x0020)
#define | CR1_NOSTRETCH_Reset ((uint16_t)0xFF7F)
#define | CR1_NOSTRETCH_Set ((uint16_t)0x0080)
#define | CR1_PE_Reset ((uint16_t)0xFFFE)
#define | CR1_PE_Set ((uint16_t)0x0001)
#define | CR1_PEC_Reset ((uint16_t)0xEFFF)
#define | CR1_PEC_Set ((uint16_t)0x1000)
#define | CR1_START_Reset ((uint16_t)0xFEFF)
#define | CR1_START_Set ((uint16_t)0x0100)
#define | CR1_STOP_Reset ((uint16_t)0xFDFF)
#define | CR1_STOP_Set ((uint16_t)0x0200)
#define | CR1_SWRST_Reset ((uint16_t)0x7FFF)
#define | CR1_SWRST_Set ((uint16_t)0x8000)
#define | CR2_DMAEN_Reset ((uint16_t)0xF7FF)
#define | CR2_DMAEN_Set ((uint16_t)0x0800)
#define | CR2_FREQ_Reset ((uint16_t)0xFFC0)
#define | CR2_LAST_Reset ((uint16_t)0xEFFF)
#define | CR2_LAST_Set ((uint16_t)0x1000)
#define | FLAG_Mask ((uint32_t)0x00FFFFFF)
#define | ITEN_Mask ((uint32_t)0x07000000)
#define | OAR1_ADD0_Reset ((uint16_t)0xFFFE)
#define | OAR1_ADD0_Set ((uint16_t)0x0001)
#define | OAR2_ADD2_Reset ((uint16_t)0xFF01)
#define | OAR2_ENDUAL_Reset ((uint16_t)0xFFFE)
#define | OAR2_ENDUAL_Set ((uint16_t)0x0001)

Functions

void | I2C_AcknowledgeConfig (I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C acknowledge feature.
void | I2C_ARPCmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C ARP.
void | I2C_CalculatePEC (I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the PEC value calculation of the transferred bytes.
ErrorStatus | I2C_CheckEvent (I2C_TypeDef *I2Cx, uint32_t I2C_EVENT)
I2C State Monitoring Functions.
void | I2C_ClearFlag (I2C_TypeDef *I2Cx, uint32_t I2C_FLAG)
Clears the I2Cx's pending flags.
void | I2C_ClearITPendingBit (I2C_TypeDef *I2Cx, uint32_t I2C_IT)
Clears the I2Cx’s interrupt pending bits.
void | I2C_Cmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C peripheral.
void | I2C_DeInit (I2C_TypeDef *I2Cx)
Deinitializes the I2Cx peripheral registers to their default reset values.
void | I2C_DMACmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C DMA requests.
void | I2C_DMALastTransferCmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
Specifies if the next DMA transfer will be the last one.
void | I2C_DualAddressCmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C dual addressing mode.
void | I2C_FastModeDutyCycleConfig (I2C_TypeDef *I2Cx, uint16_t I2C_DutyCycle)
Selects the specified I2C fast mode duty cycle.
void | I2C_GeneralCallCmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C general call feature.
void | I2C_GenerateSTART (I2C_TypeDef *I2Cx, FunctionalState NewState)
Generates I2Cx communication START condition.
void | I2C_GenerateSTOP (I2C_TypeDef *I2Cx, FunctionalState NewState)
Generates I2Cx communication STOP condition.
FlagStatus | I2C_GetFlagStatus (I2C_TypeDef *I2Cx, uint32_t I2C_FLAG)
3) Flag-based state monitoring
ITStatus | I2C_GetITStatus (I2C_TypeDef *I2Cx, uint32_t I2C_IT)
Checks whether the specified I2C interrupt has occurred or not.
uint32_t | I2C_GetLastEvent (I2C_TypeDef *I2Cx)
2) Advanced state monitoring
uint8_t | I2C_GetPEC (I2C_TypeDef *I2Cx)
Returns the PEC value for the specified I2C.
void | I2C_Init (I2C_TypeDef *I2Cx, I2C_InitTypeDef *I2C_InitStruct)
Initializes the I2Cx peripheral according to the specified parameters in the I2C_InitStruct.
void | I2C_ITConfig (I2C_TypeDef *I2Cx, uint16_t I2C_IT, FunctionalState NewState)
Enables or disables the specified I2C interrupts.
void | I2C_NACKPositionConfig (I2C_TypeDef *I2Cx, uint16_t I2C_NACKPosition)
Selects the specified I2C NACK position in master receiver mode.
void | I2C_OwnAddress2Config (I2C_TypeDef *I2Cx, uint8_t Address)
Configures the specified I2C own address2.
void | I2C_PECPositionConfig (I2C_TypeDef *I2Cx, uint16_t I2C_PECPosition)
Selects the specified I2C PEC position.
uint16_t | I2C_ReadRegister (I2C_TypeDef *I2Cx, uint8_t I2C_Register)
Reads the specified I2C register and returns its value.
uint8_t | I2C_ReceiveData (I2C_TypeDef *I2Cx)
Returns the most recent received data by the I2Cx peripheral.
void | I2C_Send7bitAddress (I2C_TypeDef *I2Cx, uint8_t Address, uint8_t I2C_Direction)
Transmits the address byte to select the slave device.
void | I2C_SendData (I2C_TypeDef *I2Cx, uint8_t Data)
Sends a data byte through the I2Cx peripheral.
void | I2C_SMBusAlertConfig (I2C_TypeDef *I2Cx, uint16_t I2C_SMBusAlert)
Drives the SMBusAlert pin high or low for the specified I2C.
void | I2C_SoftwareResetCmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C software reset.
void | I2C_StretchClockCmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C Clock stretching.
void | I2C_StructInit (I2C_InitTypeDef *I2C_InitStruct)
Fills each I2C_InitStruct member with its default value.
void | I2C_TransmitPEC (I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C PEC transfer.

Detailed Description

This file provides all the I2C firmware functions.

Author:
MCD Application Team
Version:
V3.5.0
Date:
11-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm32f10x_i2c.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_i2c.h File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Libraries
  • STM32F10x_StdPeriph_Driver
  • inc
Data Structures | Defines | Functions

stm32f10x_i2c.h File Reference

This file contains all the functions prototypes for the I2C firmware library. More...

#include "stm32f10x.h"

Go to the source code of this file.

Data Structures

struct | I2C_InitTypeDef
I2C Init structure definition. More...

Defines

#define | I2C_Ack_Disable ((uint16_t)0x0000)
#define | I2C_Ack_Enable ((uint16_t)0x0400)
#define | I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000)
#define | I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000)
#define | I2C_Direction_Receiver ((uint8_t)0x01)
#define | I2C_Direction_Transmitter ((uint8_t)0x00)
#define | I2C_DutyCycle_16_9 ((uint16_t)0x4000)
#define | I2C_DutyCycle_2 ((uint16_t)0xBFFF)
#define | I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040)
Communication events.
#define | I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084)
#define | I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080)
#define | I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008)
#define | I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001)
Communication start.
#define | I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002)
#define | I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082)
Address Acknowledge.
#define | I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400)
#define | I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040)
Communication events.
#define | I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084)
#define | I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080)
#define | I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000)
#define | I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002)
Communication start events.
#define | I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000)
#define | I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010)
#define | I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082)
#define | I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080)
#define | I2C_FLAG_ADD10 ((uint32_t)0x10000008)
#define | I2C_FLAG_ADDR ((uint32_t)0x10000002)
#define | I2C_FLAG_AF ((uint32_t)0x10000400)
#define | I2C_FLAG_ARLO ((uint32_t)0x10000200)
#define | I2C_FLAG_BERR ((uint32_t)0x10000100)
#define | I2C_FLAG_BTF ((uint32_t)0x10000004)
#define | I2C_FLAG_BUSY ((uint32_t)0x00020000)
#define | I2C_FLAG_DUALF ((uint32_t)0x00800000)
SR2 register flags.
#define | I2C_FLAG_GENCALL ((uint32_t)0x00100000)
#define | I2C_FLAG_MSL ((uint32_t)0x00010000)
#define | I2C_FLAG_OVR ((uint32_t)0x10000800)
#define | I2C_FLAG_PECERR ((uint32_t)0x10001000)
#define | I2C_FLAG_RXNE ((uint32_t)0x10000040)
#define | I2C_FLAG_SB ((uint32_t)0x10000001)
#define | I2C_FLAG_SMBALERT ((uint32_t)0x10008000)
SR1 register flags.
#define | I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000)
#define | I2C_FLAG_SMBHOST ((uint32_t)0x00400000)
#define | I2C_FLAG_STOPF ((uint32_t)0x10000010)
#define | I2C_FLAG_TIMEOUT ((uint32_t)0x10004000)
#define | I2C_FLAG_TRA ((uint32_t)0x00040000)
#define | I2C_FLAG_TXE ((uint32_t)0x10000080)
#define | I2C_IT_ADD10 ((uint32_t)0x02000008)
#define | I2C_IT_ADDR ((uint32_t)0x02000002)
#define | I2C_IT_AF ((uint32_t)0x01000400)
#define | I2C_IT_ARLO ((uint32_t)0x01000200)
#define | I2C_IT_BERR ((uint32_t)0x01000100)
#define | I2C_IT_BTF ((uint32_t)0x02000004)
#define | I2C_IT_BUF ((uint16_t)0x0400)
#define | I2C_IT_ERR ((uint16_t)0x0100)
#define | I2C_IT_EVT ((uint16_t)0x0200)
#define | I2C_IT_OVR ((uint32_t)0x01000800)
#define | I2C_IT_PECERR ((uint32_t)0x01001000)
#define | I2C_IT_RXNE ((uint32_t)0x06000040)
#define | I2C_IT_SB ((uint32_t)0x02000001)
#define | I2C_IT_SMBALERT ((uint32_t)0x01008000)
#define | I2C_IT_STOPF ((uint32_t)0x02000010)
#define | I2C_IT_TIMEOUT ((uint32_t)0x01004000)
#define | I2C_IT_TXE ((uint32_t)0x06000080)
#define | I2C_Mode_I2C ((uint16_t)0x0000)
#define | I2C_Mode_SMBusDevice ((uint16_t)0x0002)
#define | I2C_Mode_SMBusHost ((uint16_t)0x000A)
#define | I2C_NACKPosition_Current ((uint16_t)0xF7FF)
#define | I2C_NACKPosition_Next ((uint16_t)0x0800)
#define | I2C_PECPosition_Current ((uint16_t)0xF7FF)
#define | I2C_PECPosition_Next ((uint16_t)0x0800)
#define | I2C_Register_CCR ((uint8_t)0x1C)
#define | I2C_Register_CR1 ((uint8_t)0x00)
#define | I2C_Register_CR2 ((uint8_t)0x04)
#define | I2C_Register_DR ((uint8_t)0x10)
#define | I2C_Register_OAR1 ((uint8_t)0x08)
#define | I2C_Register_OAR2 ((uint8_t)0x0C)
#define | I2C_Register_SR1 ((uint8_t)0x14)
#define | I2C_Register_SR2 ((uint8_t)0x18)
#define | I2C_Register_TRISE ((uint8_t)0x20)
#define | I2C_SMBusAlert_High ((uint16_t)0xDFFF)
#define | I2C_SMBusAlert_Low ((uint16_t)0x2000)
#define | IS_I2C_ACK_STATE(STATE)
#define | IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS)
#define | IS_I2C_ALL_PERIPH(PERIPH)
#define | IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00))
#define | IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00))
#define | IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000))
#define | IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00))
#define | IS_I2C_DIRECTION(DIRECTION)
#define | IS_I2C_DUTY_CYCLE(CYCLE)
#define | IS_I2C_EVENT(EVENT)
#define | IS_I2C_GET_FLAG(FLAG)
#define | IS_I2C_GET_IT(IT)
#define | IS_I2C_MODE(MODE)
#define | IS_I2C_NACK_POSITION(POSITION)
#define | IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF)
#define | IS_I2C_PEC_POSITION(POSITION)
#define | IS_I2C_REGISTER(REGISTER)
#define | IS_I2C_SMBUS_ALERT(ALERT)

Functions

void | I2C_AcknowledgeConfig (I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C acknowledge feature.
void | I2C_ARPCmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C ARP.
void | I2C_CalculatePEC (I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the PEC value calculation of the transferred bytes.
ErrorStatus | I2C_CheckEvent (I2C_TypeDef *I2Cx, uint32_t I2C_EVENT)
I2C State Monitoring Functions.
void | I2C_ClearFlag (I2C_TypeDef *I2Cx, uint32_t I2C_FLAG)
Clears the I2Cx's pending flags.
void | I2C_ClearITPendingBit (I2C_TypeDef *I2Cx, uint32_t I2C_IT)
Clears the I2Cx’s interrupt pending bits.
void | I2C_Cmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C peripheral.
void | I2C_DeInit (I2C_TypeDef *I2Cx)
Deinitializes the I2Cx peripheral registers to their default reset values.
void | I2C_DMACmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C DMA requests.
void | I2C_DMALastTransferCmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
Specifies if the next DMA transfer will be the last one.
void | I2C_DualAddressCmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C dual addressing mode.
void | I2C_FastModeDutyCycleConfig (I2C_TypeDef *I2Cx, uint16_t I2C_DutyCycle)
Selects the specified I2C fast mode duty cycle.
void | I2C_GeneralCallCmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C general call feature.
void | I2C_GenerateSTART (I2C_TypeDef *I2Cx, FunctionalState NewState)
Generates I2Cx communication START condition.
void | I2C_GenerateSTOP (I2C_TypeDef *I2Cx, FunctionalState NewState)
Generates I2Cx communication STOP condition.
FlagStatus | I2C_GetFlagStatus (I2C_TypeDef *I2Cx, uint32_t I2C_FLAG)
3) Flag-based state monitoring
ITStatus | I2C_GetITStatus (I2C_TypeDef *I2Cx, uint32_t I2C_IT)
Checks whether the specified I2C interrupt has occurred or not.
uint32_t | I2C_GetLastEvent (I2C_TypeDef *I2Cx)
2) Advanced state monitoring
uint8_t | I2C_GetPEC (I2C_TypeDef *I2Cx)
Returns the PEC value for the specified I2C.
void | I2C_Init (I2C_TypeDef *I2Cx, I2C_InitTypeDef *I2C_InitStruct)
Initializes the I2Cx peripheral according to the specified parameters in the I2C_InitStruct.
void | I2C_ITConfig (I2C_TypeDef *I2Cx, uint16_t I2C_IT, FunctionalState NewState)
Enables or disables the specified I2C interrupts.
void | I2C_NACKPositionConfig (I2C_TypeDef *I2Cx, uint16_t I2C_NACKPosition)
Selects the specified I2C NACK position in master receiver mode.
void | I2C_OwnAddress2Config (I2C_TypeDef *I2Cx, uint8_t Address)
Configures the specified I2C own address2.
void | I2C_PECPositionConfig (I2C_TypeDef *I2Cx, uint16_t I2C_PECPosition)
Selects the specified I2C PEC position.
uint16_t | I2C_ReadRegister (I2C_TypeDef *I2Cx, uint8_t I2C_Register)
Reads the specified I2C register and returns its value.
uint8_t | I2C_ReceiveData (I2C_TypeDef *I2Cx)
Returns the most recent received data by the I2Cx peripheral.
void | I2C_Send7bitAddress (I2C_TypeDef *I2Cx, uint8_t Address, uint8_t I2C_Direction)
Transmits the address byte to select the slave device.
void | I2C_SendData (I2C_TypeDef *I2Cx, uint8_t Data)
Sends a data byte through the I2Cx peripheral.
void | I2C_SMBusAlertConfig (I2C_TypeDef *I2Cx, uint16_t I2C_SMBusAlert)
Drives the SMBusAlert pin high or low for the specified I2C.
void | I2C_SoftwareResetCmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C software reset.
void | I2C_StretchClockCmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C Clock stretching.
void | I2C_StructInit (I2C_InitTypeDef *I2C_InitStruct)
Fills each I2C_InitStruct member with its default value.
void | I2C_TransmitPEC (I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C PEC transfer.

Detailed Description

This file contains all the functions prototypes for the I2C firmware library.

Author:
MCD Application Team
Version:
V3.5.0
Date:
11-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm32f10x_i2c.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_ip_dbg.c File Reference

  • File List
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  • Project
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  • RunTime_Check
Functions | Variables

stm32f10x_ip_dbg.c File Reference

This file provides all peripherals pointers initialization. More...

#include "stm32f10x_ip_dbg.h"

Go to the source code of this file.

Functions

void | debug (void)
This function initialize peripherals pointers.

Variables

ADC_TypeDef * ADC1_DBG
ADC_TypeDef * ADC2_DBG
ADC_TypeDef * ADC3_DBG
AFIO_TypeDef * AFIO_DBG
BKP_TypeDef * BKP_DBG
CAN_TypeDef * CAN1_DBG
CEC_TypeDef * CEC_DBG
CRC_TypeDef * CRC_DBG
DAC_TypeDef * DAC_DBG
DBGMCU_TypeDef * DBGMCU_DBG
DMA_Channel_TypeDef * DMA1_Channel1_DBG
DMA_Channel_TypeDef * DMA1_Channel2_DBG
DMA_Channel_TypeDef * DMA1_Channel3_DBG
DMA_Channel_TypeDef * DMA1_Channel4_DBG
DMA_Channel_TypeDef * DMA1_Channel5_DBG
DMA_Channel_TypeDef * DMA1_Channel6_DBG
DMA_Channel_TypeDef * DMA1_Channel7_DBG
DMA_TypeDef * DMA1_DBG
DMA_Channel_TypeDef * DMA2_Channel1_DBG
DMA_Channel_TypeDef * DMA2_Channel2_DBG
DMA_Channel_TypeDef * DMA2_Channel3_DBG
DMA_Channel_TypeDef * DMA2_Channel4_DBG
DMA_Channel_TypeDef * DMA2_Channel5_DBG
DMA_TypeDef * DMA2_DBG
EXTI_TypeDef * EXTI_DBG
FLASH_TypeDef * FLASH_DBG
FSMC_Bank1_TypeDef * FSMC_Bank1_DBG
FSMC_Bank1E_TypeDef * FSMC_Bank1E_DBG
FSMC_Bank2_TypeDef * FSMC_Bank2_DBG
FSMC_Bank3_TypeDef * FSMC_Bank3_DBG
FSMC_Bank4_TypeDef * FSMC_Bank4_DBG
GPIO_TypeDef * GPIOA_DBG
GPIO_TypeDef * GPIOB_DBG
GPIO_TypeDef * GPIOC_DBG
GPIO_TypeDef * GPIOD_DBG
GPIO_TypeDef * GPIOE_DBG
GPIO_TypeDef * GPIOF_DBG
GPIO_TypeDef * GPIOG_DBG
I2C_TypeDef * I2C1_DBG
I2C_TypeDef * I2C2_DBG
IWDG_TypeDef * IWDG_DBG
NVIC_Type * | NVIC_DBG
OB_TypeDef * OB_DBG
PWR_TypeDef * PWR_DBG
RCC_TypeDef * RCC_DBG
RTC_TypeDef * RTC_DBG
SCB_Type * | SCB_DBG
SDIO_TypeDef * SDIO_DBG
SPI_TypeDef * SPI1_DBG
SPI_TypeDef * SPI2_DBG
SPI_TypeDef * SPI3_DBG
SysTick_Type * | SysTick_DBG
TIM_TypeDef * TIM15_DBG
TIM_TypeDef * TIM16_DBG
TIM_TypeDef * TIM17_DBG
TIM_TypeDef * TIM1_DBG
TIM_TypeDef * TIM2_DBG
TIM_TypeDef * TIM3_DBG
TIM_TypeDef * TIM4_DBG
TIM_TypeDef * TIM5_DBG
TIM_TypeDef * TIM6_DBG
TIM_TypeDef * TIM7_DBG
TIM_TypeDef * TIM8_DBG
USART_TypeDef * UART4_DBG
USART_TypeDef * UART5_DBG
USART_TypeDef * USART1_DBG
USART_TypeDef * USART2_DBG
USART_TypeDef * USART3_DBG
WWDG_TypeDef * WWDG_DBG

Detailed Description

This file provides all peripherals pointers initialization.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm32f10x_ip_dbg.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_ip_dbg.h File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • Lib_DEBUG
  • RunTime_Check
Functions

stm32f10x_ip_dbg.h File Reference

This file contains the headers of the library peripherals Debug. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void debug (void)
This function initialize peripherals pointers.

Detailed Description

This file contains the headers of the library peripherals Debug.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm32f10x_ip_dbg.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • ADC
  • 3ADCs_DMA
Functions | Variables

STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"

Go to the source code of this file.

Functions

void | ADC1_2_IRQHandler (void)
This function handles ADC1 and ADC2 global interrupts requests.
void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

__IO uint16_t | ADC2ConvertedValue

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • ADC
  • ADC1_DMA
Functions

STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • ADC
  • AnalogWatchdog
Functions

STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"
#include "stm32_eval.h"

Go to the source code of this file.

Functions

void | ADC1_2_IRQHandler (void)
This function handles ADC1 and ADC2 global interrupts requests.
void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • ADC
  • ExtLinesTrigger
Functions | Variables

STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"

Go to the source code of this file.

Functions

void | ADC1_2_IRQHandler (void)
This function handles ADC1 and ADC2 global interrupts requests.
void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

__IO uint16_t | ADC_InjectedConvertedValueTab [32]
uint32_t | Index = 0

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • ADC
  • RegSimul_DualMode
Functions

STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • ADC
  • TIMTrigger_AutoInjection
Functions | Variables

STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"

Go to the source code of this file.

Functions

void | ADC1_2_IRQHandler (void)
This function handles ADC1 and ADC2 global interrupts requests.
void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

__IO uint16_t | ADC_InjectedConvertedValueTab [32]
__IO uint32_t | Index

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • BKP
  • Backup_Data
Functions

STM32F10x_StdPeriph_Examples/BKP/Backup_Data/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/BKP/Backup_Data/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • BKP
  • Tamper
Functions

STM32F10x_StdPeriph_Examples/BKP/Tamper/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"
#include "main.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | TAMPER_IRQHandler (void)
This function handles Tamper interrupt request.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/BKP/Tamper/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • CAN
  • DualCAN
Functions | Variables

STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | CAN1_RX0_IRQHandler (void)
This function handles CAN1 RX0 Handler.
void | CAN2_RX0_IRQHandler (void)
This function handles CAN2 RX0 Handler.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | LED_Display (uint8_t Ledstatus)
Turn ON/OFF the dedicate led.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSVC exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

CanRxMsg RxMessage

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • CAN
  • LoopBack
Functions | Variables

STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSVC exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.
void | USB_LP_CAN1_RX0_IRQHandler (void)
This function handles CAN1 Handler.

Variables

__IO uint32_t | ret

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • CAN
  • Networking
Functions | Variables

STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | LED_Display (uint8_t Ledstatus)
Turn ON/OFF the dedicate led.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSVC exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.
void | USB_LP_CAN1_RX0_IRQHandler (void)
This function handles CAN1 Handler.

Variables

uint8_t | KeyNumber
CanRxMsg RxMessage

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • CEC
  • DataExchangeInterrupt
Functions | Variables

STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"
#include "stm32_eval.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | CEC_IRQHandler (void)
This function handles CEC global interrupt request.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | EXTI9_5_IRQHandler (void)
This function handles EXTI Lines 9 to 5 interrupts requests.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSVC exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

uint8_t | ByteNumber
uint8_t | HeaderBlockValueToSend = 0
uint8_t | InitiatorAddress = 0
uint8_t | rcv_inc = 0
uint8_t | ReceiveBuffer [10]
__IO uint8_t | ReceivedFrame = 0
uint8_t | RecepErrorCode = 0
uint8_t | send_inc = 0
uint8_t | TransErrorCode = 0
uint8_t | TransmitBuffer [10]

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • CortexM3
  • BitBand
Functions

STM32F10x_StdPeriph_Examples/CortexM3/BitBand/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/CortexM3/BitBand/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • CortexM3
  • Mode_Privilege
Functions

STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • CortexM3
  • MPU
Functions

STM32F10x_StdPeriph_Examples/CortexM3/MPU/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"
#include "stm32_eval.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/CortexM3/MPU/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • CRC
  • CRC_Calculation
Functions

STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • DAC
  • DualModeDMA_SineWave
Functions

STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • DAC
  • OneChannel_NoiseWave
Functions

STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • DAC
  • OneChannelDMA_Escalator
Functions

STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • DAC
  • TwoChannels_TriangleWave
Functions

STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • DMA
  • ADC_TIM1
Functions

STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • DMA
  • FLASH_RAM
Functions | Variables

STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | DMA1_Channel6_IRQHandler (void)
This function handles DMA1 Channel 6 interrupt request.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

__IO uint16_t | CurrDataCounterEnd

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • DMA
  • FSMC
Functions

STM32F10x_StdPeriph_Examples/DMA/FSMC/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/DMA/FSMC/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • DMA
  • I2C_RAM
Functions

STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • DMA
  • SPI_RAM
Functions

STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

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  • EXTI
  • EXTI_Config
Functions

STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"
#include "stm32_eval.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | EXTI0_IRQHandler (void)
This function handles External line 0 interrupt request.
void | EXTI9_5_IRQHandler (void)
This function handles External lines 9 to 5 interrupt request.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
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  • FLASH
  • Dual_Boot
Functions

STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"
#include "main.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

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  • Program
Functions

STM32F10x_StdPeriph_Examples/FLASH/Program/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/FLASH/Program/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • FLASH
  • Write_Protection
Functions

STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

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  • Project
  • STM32F10x_StdPeriph_Examples
  • FSMC
  • NAND
Functions

STM32F10x_StdPeriph_Examples/FSMC/NAND/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/FSMC/NAND/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • FSMC
  • NOR
Functions

STM32F10x_StdPeriph_Examples/FSMC/NOR/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/FSMC/NOR/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

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  • Project
  • STM32F10x_StdPeriph_Examples
  • FSMC
  • NOR_CodeExecute
  • binary
Functions

STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • FSMC
  • NOR_CodeExecute
Functions

STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • FSMC
  • OneNAND
Functions

STM32F10x_StdPeriph_Examples/FSMC/OneNAND/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/FSMC/OneNAND/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • FSMC
  • SRAM
Functions

STM32F10x_StdPeriph_Examples/FSMC/SRAM/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/FSMC/SRAM/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • FSMC
  • SRAM_DataMemory
Functions

STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • GPIO
  • IOToggle
Functions

STM32F10x_StdPeriph_Examples/GPIO/IOToggle/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/GPIO/IOToggle/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • GPIO
  • JTAG_Remap
Functions

STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • I2C
  • EEPROM
Functions

STM32F10x_StdPeriph_Examples/I2C/EEPROM/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/I2C/EEPROM/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • I2C
  • I2C_TSENSOR
Functions | Variables

STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"
#include "stm32_eval_i2c_tsensor.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | I2C1_ER_IRQHandler (void)
This function handles I2C2 Error interrupt request.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

__IO uint8_t | SMbusAlertOccurred

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • I2C
  • IOExpander
Functions

STM32F10x_StdPeriph_Examples/I2C/IOExpander/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"
#include "main.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | EXTI15_10_IRQHandler (void)
This function handles External lines 15 to 10 interrupt request.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSVC exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/I2C/IOExpander/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • I2S
  • Interrupt
Functions | Variables

STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SPI2_IRQHandler (void)
This function handles SPI2 global interrupt request.
void | SPI3_IRQHandler (void)
This function handles SPI3 global interrupt request.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

uint16_t | I2S2_Buffer_Rx [32]
const uint16_t | I2S3_Buffer_Tx [32]
__IO uint32_t | RxIdx
__IO uint32_t | TxIdx

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • I2S
  • SPI_I2S_Switch
Functions

STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • IWDG
  • IWDG_Reset
Functions | Variables

STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"
#include "stm32_eval.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | EXTI9_5_IRQHandler (void)
This function handles External lines 9 to 5 interrupt request.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | TIM5_IRQHandler (void)
This function handles TIM5 global interrupt request.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

__IO uint32_t | Capture = 0
__IO uint16_t | CaptureNumber = 0
__IO uint16_t | IC1ReadValue1 = 0
__IO uint16_t | IC1ReadValue2 = 0
uint32_t | LsiFreq
__IO uint32_t | TimingDelay

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • Lib_DEBUG
  • RunTime_Check
Functions

STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • NVIC
  • DMA_WFIMode
Functions | Variables

STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"
#include "stm32_eval.h"

Go to the source code of this file.

Functions

uint8_t | Buffercmp16 (uint16_t *pBuffer1, uint16_t *pBuffer2, uint16_t BufferLength)
Compares two buffers.
void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | DMA1_Channel5_IRQHandler (void)
This function handles DMA1 Channel 5 interrupt request.
void | DMA1_Channel6_IRQHandler (void)
This function handles DMA1 Channel 6 interrupt request.
void | DMA_Configuration (void)
Configures the used DMA Channel.
void | EXTI9_5_IRQHandler (void)
This function handles External lines 9 to 5 interrupt request.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

uint16_t | DST_Buffer [10]
__IO uint32_t | LowPowerMode
uint16_t | SRC_Buffer [10] = {0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39}
uint8_t | TestStatus = 0

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • NVIC
  • IRQ_Mask
Functions | Variables

STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"
#include "stm32_eval.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | EXTI0_IRQHandler (void)
This function handles EXTI Lines 0 interrupt request.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | TIM2_IRQHandler (void)
This function handles TIM2 global interrupt request.
void | TIM3_IRQHandler (void)
This function handles TIM3 global interrupt request.
void | TIM4_IRQHandler (void)
This function handles TIM4 global interrupt request.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

__IO uint32_t | index = 0

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • NVIC
  • IRQ_Priority
Functions | Variables

STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"
#include "stm32_eval.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | EXTI0_IRQHandler (void)
This function handles External interrupt Line 0 request.
void | EXTI9_5_IRQHandler (void)
This function handles External lines 9 to 5 interrupt request.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

uint8_t | PreemptionOccured
uint8_t | PreemptionPriorityValue

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • NVIC
  • VectorTable_Relocation
Functions

STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"
#include "main.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • PWR
  • PVD
Functions

STM32F10x_StdPeriph_Examples/PWR/PVD/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"
#include "stm32_eval.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | PVD_IRQHandler (void)
This function handles the PVD Output interrupt request.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/PWR/PVD/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • PWR
  • STANDBY
Functions

STM32F10x_StdPeriph_Examples/PWR/STANDBY/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"
#include "stm32_eval.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | EXTI9_5_IRQHandler (void)
This function handles External lines 9 to 5 interrupt request.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/PWR/STANDBY/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • PWR
  • STOP
Functions | Variables

STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"
#include "stm32_eval.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | EXTI9_5_IRQHandler (void)
This function handles External lines 9 to 5 interrupt request.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | RTCAlarm_IRQHandler (void)
This function handles RTC Alarm interrupt request.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

__IO uint32_t | TimingDelay = 0

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • RCC
  • RCC_ClockConfig
Functions

STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"
#include "main.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | RCC_IRQHandler (void)
This function handles RCC interrupt request.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • RTC
  • Calendar
Functions | Variables

STM32F10x_StdPeriph_Examples/RTC/Calendar/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"
#include "stm32_eval.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | RTC_IRQHandler (void)
This function handles RTC global interrupt request.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

__IO uint32_t | TimeDisplay

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/RTC/Calendar/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • RTC
  • LSI_Calib
Functions | Variables

STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"
#include "main.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | RTC_IRQHandler (void)
This function handles RTC global interrupt request.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | TIM5_IRQHandler (void)
This function handles TIM5 global interrupt request.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

uint16_t | tmpCC4 [2] = {0, 0}

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • SDIO
  • uSDCard
Functions

STM32F10x_StdPeriph_Examples/SDIO/uSDCard/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"
#include "stm32_eval_sdio_sd.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SDIO_IRQHandler (void)
This function handles SDIO global interrupt request.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/SDIO/uSDCard/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • SPI
  • CRC
Functions

STM32F10x_StdPeriph_Examples/SPI/CRC/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/SPI/CRC/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • SPI
  • DMA
Functions

STM32F10x_StdPeriph_Examples/SPI/DMA/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/SPI/DMA/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • SPI
  • FullDuplex_SoftNSS
Functions

STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • SPI
  • Simplex_Interrupt
Defines | Functions | Variables

STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"
#include "platform_config.h"

Go to the source code of this file.

Defines

#define | BufferSize 32

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SPI1_IRQHandler (void)
This function handles SPI1 or SPI3 global interrupt request.
void | SPI2_IRQHandler (void)
This function handles SPI2 global interrupt request.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

__IO uint8_t | RxIdx
uint8_t | SPI_MASTER_Buffer_Tx [BufferSize]
uint8_t | SPI_SLAVE_Buffer_Rx [BufferSize]
__IO uint8_t | TxIdx

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • SPI
  • SPI_FLASH
Functions

STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • SysTick
  • TimeBase
Functions

STM32F10x_StdPeriph_Examples/SysTick/TimeBase/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"
#include "main.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/SysTick/TimeBase/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

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  • TIM
  • 6Steps
Functions | Variables

STM32F10x_StdPeriph_Examples/TIM/6Steps/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | TIM1_TRG_COM_IRQHandler (void)
This function handles TIM1 Trigger and commutation interrupts requests.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

__IO uint32_t | step = 1

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/TIM/6Steps/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

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  • 7PWM_Output
Functions

STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

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Functions

STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

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  • ComplementarySignals
Functions

STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

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  • DMA
Functions

STM32F10x_StdPeriph_Examples/TIM/DMA/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/TIM/DMA/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

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  • DMABurst
Functions

STM32F10x_StdPeriph_Examples/TIM/DMABurst/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/TIM/DMABurst/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

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  • TIM
  • ExtTrigger_Synchro
Functions

STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

  • File List
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  • STM32F10x_StdPeriph_Examples
  • TIM
  • InputCapture
Functions | Variables

STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | TIM3_IRQHandler (void)
This function handles TIM3 global interrupt request.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

__IO uint32_t | Capture = 0
__IO uint16_t | CaptureNumber = 0
__IO uint16_t | IC3ReadValue1 = 0
__IO uint16_t | IC3ReadValue2 = 0
__IO uint32_t | TIM3Freq = 0

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

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  • OCActive
Functions

STM32F10x_StdPeriph_Examples/TIM/OCActive/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/TIM/OCActive/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

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  • OCInactive
Functions

STM32F10x_StdPeriph_Examples/TIM/OCInactive/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | TIM2_IRQHandler (void)
This function handles TIM2 global interrupt request.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/TIM/OCInactive/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

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  • STM32F10x_StdPeriph_Examples
  • TIM
  • OCToggle
Functions | Variables

STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | TIM3_IRQHandler (void)
This function handles TIM3 global interrupt request.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

uint16_t | capture = 0
__IO uint16_t | CCR1_Val
__IO uint16_t | CCR2_Val
__IO uint16_t | CCR3_Val
__IO uint16_t | CCR4_Val

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

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  • OnePulse
Functions

STM32F10x_StdPeriph_Examples/TIM/OnePulse/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/TIM/OnePulse/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • TIM
  • Parallel_Synchro
Functions

STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • TIM
  • PWM_Input
Functions | Variables

STM32F10x_StdPeriph_Examples/TIM/PWM_Input/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | TIM3_IRQHandler (void)
This function handles TIM3 global interrupt request.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

__IO uint16_t | DutyCycle = 0
__IO uint32_t | Frequency = 0
__IO uint16_t | IC2Value = 0

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/TIM/PWM_Input/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • TIM
  • PWM_Output
Functions

STM32F10x_StdPeriph_Examples/TIM/PWM_Output/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/TIM/PWM_Output/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • TIM
  • TIM10_PWMOutput
Functions

STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • TIM
  • TIM15_ComplementarySignals
Functions

STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • TIM
  • TIM1_Synchro
Functions

STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • TIM
  • TIM9_OCToggle
Functions | Variables

STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | TIM1_BRK_TIM9_IRQHandler (void)
This function handles TIM1 Break and TIM9 interrupts request.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

uint16_t | capture = 0
__IO uint16_t | CCR1Val
__IO uint16_t | CCR2Val

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • TIM
  • TimeBase
Functions | Variables

STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | TIM2_IRQHandler (void)
This function handles TIM2 global interrupt request.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

uint16_t | capture = 0
__IO uint16_t | CCR1_Val
__IO uint16_t | CCR2_Val
__IO uint16_t | CCR3_Val
__IO uint16_t | CCR4_Val

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • USART
  • DMA_Interrupt
Functions | Variables

STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.
void | USART2_IRQHandler (void)
This function handles USART2 global interrupt request.
void | USART3_IRQHandler (void)
This function handles USART3 global interrupt request.

Variables

uint8_t | NbrOfDataToRead
uint8_t | RxBuffer2 []
uint8_t | RxCounter = 0

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • USART
  • DMA_Polling
Functions

STM32F10x_StdPeriph_Examples/USART/DMA_Polling/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/USART/DMA_Polling/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • USART
  • HalfDuplex
Functions

STM32F10x_StdPeriph_Examples/USART/HalfDuplex/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/USART/HalfDuplex/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • USART
  • HyperTerminal_HwFlowControl
Functions

STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • USART
  • HyperTerminal_Interrupt
Defines | Functions | Variables

STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"
#include "stm32_eval.h"

Go to the source code of this file.

Defines

#define | countof(a) (sizeof(a) / sizeof(*(a)))
#define | RxBufferSize 0x20
#define | TxBufferSize (countof(TxBuffer) - 1)
#define | USARTx_IRQHandler USART1_IRQHandler

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.
void | USARTx_IRQHandler (void)
This function handles USARTx global interrupt request.

Variables

uint8_t | NbrOfDataToRead = RxBufferSize
uint8_t | NbrOfDataToTransfer = TxBufferSize
uint8_t | RxBuffer [RxBufferSize]
uint16_t | RxCounter = 0
uint8_t | TxBuffer []
uint8_t | TxCounter = 0

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

  • File List
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Functions | Variables

STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"
#include "platform_config.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.
void | USARTy_IRQHandler (void)
This function handles USARTy global interrupt request.
void | USARTz_IRQHandler (void)
This function handles USARTz global interrupt request.

Variables

uint8_t | NbrOfDataToRead1
uint8_t | NbrOfDataToRead2
uint8_t | NbrOfDataToTransfer1
uint8_t | NbrOfDataToTransfer2
uint8_t | RxBuffer1 []
uint8_t | RxBuffer2 []
__IO uint8_t | RxCounter1
__IO uint8_t | RxCounter2
uint8_t | TxBuffer1 []
uint8_t | TxBuffer2 []
__IO uint8_t | TxCounter1
__IO uint8_t | TxCounter2

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
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  • USART
  • IrDA
  • Receive
Functions

STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

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  • Project
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  • USART
  • IrDA
  • Transmit
Functions

STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
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Functions

STM32F10x_StdPeriph_Examples/USART/MultiProcessor/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"
#include "platform_config.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | EXTI0_IRQHandler (void)
This function handles External interrupt Line 0 request.
void | EXTI9_5_IRQHandler (void)
This function handles External lines 9 to 5 interrupt request.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/USART/MultiProcessor/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

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Functions

STM32F10x_StdPeriph_Examples/USART/Polling/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/USART/Polling/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

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  • Printf
Functions

STM32F10x_StdPeriph_Examples/USART/Printf/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/USART/Printf/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • USART
  • Smartcard
Functions | Variables

STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"
#include "platform_config.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | EXTI15_10_IRQHandler (void)
This function handles External lines 15 to 10 interrupt request.
void | EXTI9_5_IRQHandler (void)
This function handles External lines 9 to 5 interrupt request.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SC_USART_IRQHandler (void)
This function handles SC_USART global interrupt request.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

__IO uint32_t | CardInserted

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • USART
  • Synchronous
Functions

STM32F10x_StdPeriph_Examples/USART/Synchronous/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/USART/Synchronous/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

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  • WWDG_Reset
Functions | Variables

STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"
#include "stm32_eval.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | EXTI9_5_IRQHandler (void)
This function handles External lines 9 to 5 interrupt request.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Variables

__IO uint32_t | TimingDelay

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c File Reference

  • File List
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Functions

STM32F10x_StdPeriph_Template/stm32f10x_it.c File Reference

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine. More...

#include "stm32f10x_it.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSVC exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Template/stm32f10x_it.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

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  • Project
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  • 3ADCs_DMA
Functions

STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | ADC1_2_IRQHandler (void)
This function handles ADC1 and ADC2 global interrupts requests.
void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

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  • ADC1_DMA
Functions

STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

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  • Project
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  • ADC
  • AnalogWatchdog
Functions

STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | ADC1_2_IRQHandler (void)
This function handles ADC1 and ADC2 global interrupts requests.
void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • ADC
  • ExtLinesTrigger
Functions

STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | ADC1_2_IRQHandler (void)
This function handles ADC1 and ADC2 global interrupts requests.
void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • ADC
  • RegSimul_DualMode
Functions

STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

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  • STM32F10x_StdPeriph_Lib_V3.5.0
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  • ADC
  • TIMTrigger_AutoInjection
Functions

STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | ADC1_2_IRQHandler (void)
This function handles ADC1 and ADC2 global interrupts requests.
void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

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  • BKP
  • Backup_Data
Functions

STM32F10x_StdPeriph_Examples/BKP/Backup_Data/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/BKP/Backup_Data/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

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  • STM32F10x_StdPeriph_Lib_V3.5.0
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  • BKP
  • Tamper
Functions

STM32F10x_StdPeriph_Examples/BKP/Tamper/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | TAMPER_IRQHandler (void)
This function handles Tamper interrupt request.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/BKP/Tamper/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

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  • Project
  • STM32F10x_StdPeriph_Examples
  • CAN
  • DualCAN
Functions

STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | CAN1_RX0_IRQHandler (void)
This function handles CAN1 RX0 Handler.
void | CAN2_RX0_IRQHandler (void)
This function handles CAN2 RX0 Handler.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

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  • STM32F10x_StdPeriph_Examples
  • CAN
  • LoopBack
Functions

STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.
void | USB_LP_CAN1_RX0_IRQHandler (void)
This function handles CAN1 Handler.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

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  • CAN
  • Networking
Functions

STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.
void | USB_LP_CAN1_RX0_IRQHandler (void)
This function handles CAN1 Handler.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • CEC
  • DataExchangeInterrupt
Functions

STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | CEC_IRQHandler (void)
This function handles CEC global interrupt request.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | EXTI9_5_IRQHandler (void)
This function handles EXTI Lines 9 to 5 interrupts requests.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • CortexM3
  • BitBand
Functions

STM32F10x_StdPeriph_Examples/CortexM3/BitBand/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/CortexM3/BitBand/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • CortexM3
  • Mode_Privilege
Functions

STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
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  • CortexM3
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Functions

STM32F10x_StdPeriph_Examples/CortexM3/MPU/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/CortexM3/MPU/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • CRC
  • CRC_Calculation
Functions

STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • DAC
  • DualModeDMA_SineWave
Functions

STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

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  • DAC
  • OneChannel_NoiseWave
Functions

STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • DAC
  • OneChannelDMA_Escalator
Functions

STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • DAC
  • TwoChannels_TriangleWave
Functions

STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • DMA
  • ADC_TIM1
Functions

STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • DMA
  • FLASH_RAM
Functions

STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | DMA1_Channel6_IRQHandler (void)
This function handles DMA1 Channel 6 interrupt request.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • DMA
  • FSMC
Functions

STM32F10x_StdPeriph_Examples/DMA/FSMC/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/DMA/FSMC/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • DMA
  • I2C_RAM
Functions

STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • DMA
  • SPI_RAM
Functions

STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • EXTI
  • EXTI_Config
Functions

STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | EXTI0_IRQHandler (void)
This function handles External line 0 interrupt request.
void | EXTI9_5_IRQHandler (void)
This function handles EXTI Lines 9 to 5 interrupts requests.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

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  • Project
  • STM32F10x_StdPeriph_Examples
  • FLASH
  • Dual_Boot
Functions

STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • FLASH
  • Program
Functions

STM32F10x_StdPeriph_Examples/FLASH/Program/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/FLASH/Program/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • FLASH
  • Write_Protection
Functions

STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • FSMC
  • NAND
Functions

STM32F10x_StdPeriph_Examples/FSMC/NAND/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/FSMC/NAND/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

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Functions

STM32F10x_StdPeriph_Examples/FSMC/NOR/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/FSMC/NOR/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

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  • binary
Functions

STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

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Functions

STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

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  • Project
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Functions

STM32F10x_StdPeriph_Examples/FSMC/OneNAND/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/FSMC/OneNAND/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

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  • Project
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  • SRAM
Functions

STM32F10x_StdPeriph_Examples/FSMC/SRAM/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/FSMC/SRAM/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

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  • SRAM_DataMemory
Functions

STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • GPIO
  • IOToggle
Functions

STM32F10x_StdPeriph_Examples/GPIO/IOToggle/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/GPIO/IOToggle/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • GPIO
  • JTAG_Remap
Functions

STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

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  • Project
  • STM32F10x_StdPeriph_Examples
  • I2C
  • EEPROM
Functions

STM32F10x_StdPeriph_Examples/I2C/EEPROM/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/I2C/EEPROM/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

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  • I2C_TSENSOR
Functions

STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

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  • STM32F10x_StdPeriph_Lib_V3.5.0
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  • IOExpander
Functions

STM32F10x_StdPeriph_Examples/I2C/IOExpander/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | EXTI15_10_IRQHandler (void)
This function handles External lines 15 to 10 interrupt request.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/I2C/IOExpander/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • I2S
  • Interrupt
Functions

STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SPI2_IRQHandler (void)
This function handles SPI2 global interrupt request.
void | SPI3_IRQHandler (void)
This function handles SPI3 global interrupt request.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • I2S
  • SPI_I2S_Switch
Functions

STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • IWDG
  • IWDG_Reset
Functions

STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | EXTI9_5_IRQHandler (void)
This function handles EXTI Lines 9 to 5 interrupts requests.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | TIM5_IRQHandler (void)
This function handles TIM5 global interrupt request.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • Lib_DEBUG
  • RunTime_Check
Functions

STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • NVIC
  • DMA_WFIMode
Functions

STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | DMA1_Channel5_IRQHandler (void)
This function handles DMA1 Channel 5 interrupt request.
void | DMA1_Channel6_IRQHandler (void)
This function handles DMA1 Channel 6 interrupt request.
void | EXTI9_5_IRQHandler (void)
This function handles EXTI Lines 9 to 5 interrupts requests.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
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  • NVIC
  • IRQ_Mask
Functions

STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | EXTI0_IRQHandler (void)
This function handles External line 0 interrupt request.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | TIM2_IRQHandler (void)
This function handles TIM2 global interrupt request.
void | TIM3_IRQHandler (void)
This function handles TIM3 global interrupt request.
void | TIM4_IRQHandler (void)
This function handles TIM4 global interrupt request.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • NVIC
  • IRQ_Priority
Functions

STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | EXTI0_IRQHandler (void)
This function handles External line 0 interrupt request.
void | EXTI9_5_IRQHandler (void)
This function handles EXTI Lines 9 to 5 interrupts requests.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • NVIC
  • VectorTable_Relocation
Functions

STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • PWR
  • PVD
Functions

STM32F10x_StdPeriph_Examples/PWR/PVD/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | PVD_IRQHandler (void)
This function handles the PVD Output interrupt request.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/PWR/PVD/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • PWR
  • STANDBY
Functions

STM32F10x_StdPeriph_Examples/PWR/STANDBY/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | EXTI9_5_IRQHandler (void)
This function handles EXTI Lines 9 to 5 interrupts requests.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/PWR/STANDBY/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • PWR
  • STOP
Functions

STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | EXTI9_5_IRQHandler (void)
This function handles EXTI Lines 9 to 5 interrupts requests.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | RTCAlarm_IRQHandler (void)
This function handles RTC Alarm interrupt request.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • RCC
  • RCC_ClockConfig
Functions

STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | RCC_IRQHandler (void)
This function handles RCC interrupt request.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • RTC
  • Calendar
Functions

STM32F10x_StdPeriph_Examples/RTC/Calendar/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | RTC_IRQHandler (void)
This function handles RTC global interrupt request.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/RTC/Calendar/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • RTC
  • LSI_Calib
Functions

STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | RTC_IRQHandler (void)
This function handles RTC global interrupt request.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | TIM5_IRQHandler (void)
This function handles TIM5 global interrupt request.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • SDIO
  • uSDCard
Functions

STM32F10x_StdPeriph_Examples/SDIO/uSDCard/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SDIO_IRQHandler (void)
This function handles SDIO global interrupt request.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/SDIO/uSDCard/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • SPI
  • CRC
Functions

STM32F10x_StdPeriph_Examples/SPI/CRC/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/SPI/CRC/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

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  • DMA
Functions

STM32F10x_StdPeriph_Examples/SPI/DMA/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/SPI/DMA/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

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  • FullDuplex_SoftNSS
Functions

STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

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  • Simplex_Interrupt
Functions

STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SPI1_IRQHandler (void)
This function handles SPI1 or SPI3 global interrupt request.
void | SPI2_IRQHandler (void)
This function handles SPI2 global interrupt request.
void | SPI3_IRQHandler (void)
This function handles SPI3 global interrupt request.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

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  • SPI_FLASH
Functions

STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

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  • Project
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  • TimeBase
Functions

STM32F10x_StdPeriph_Examples/SysTick/TimeBase/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/SysTick/TimeBase/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

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  • 6Steps
Functions

STM32F10x_StdPeriph_Examples/TIM/6Steps/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | TIM1_TRG_COM_IRQHandler (void)
This function handles TIM1 Trigger and commutation interrupts requests.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/TIM/6Steps/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

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  • TIM
  • 7PWM_Output
Functions

STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

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  • Cascade_Synchro
Functions

STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

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  • ComplementarySignals
Functions

STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

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  • Project
  • STM32F10x_StdPeriph_Examples
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  • DMA
Functions

STM32F10x_StdPeriph_Examples/TIM/DMA/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/TIM/DMA/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

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  • TIM
  • DMABurst
Functions

STM32F10x_StdPeriph_Examples/TIM/DMABurst/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/TIM/DMABurst/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • TIM
  • ExtTrigger_Synchro
Functions

STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • TIM
  • InputCapture
Functions

STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | TIM3_IRQHandler (void)
This function handles TIM3 global interrupt request.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

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  • OCActive
Functions

STM32F10x_StdPeriph_Examples/TIM/OCActive/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/TIM/OCActive/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

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  • OCInactive
Functions

STM32F10x_StdPeriph_Examples/TIM/OCInactive/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | TIM2_IRQHandler (void)
This function handles TIM2 global interrupt request.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/TIM/OCInactive/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

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  • OCToggle
Functions

STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | TIM3_IRQHandler (void)
This function handles TIM3 global interrupt request.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • TIM
  • OnePulse
Functions

STM32F10x_StdPeriph_Examples/TIM/OnePulse/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/TIM/OnePulse/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

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  • Project
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  • Parallel_Synchro
Functions

STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

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  • PWM_Input
Functions

STM32F10x_StdPeriph_Examples/TIM/PWM_Input/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | TIM3_IRQHandler (void)
This function handles TIM3 global interrupt request.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/TIM/PWM_Input/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • TIM
  • PWM_Output
Functions

STM32F10x_StdPeriph_Examples/TIM/PWM_Output/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/TIM/PWM_Output/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • TIM
  • TIM10_PWMOutput
Functions

STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
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  • TIM15_ComplementarySignals
Functions

STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

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  • TIM1_Synchro
Functions

STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

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  • TIM9_OCToggle
Functions

STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | TIM3_IRQHandler (void)
This function handles TIM3 global interrupt request.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

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  • STM32F10x_StdPeriph_Examples
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  • TimeBase
Functions

STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | TIM2_IRQHandler (void)
This function handles TIM2 global interrupt request.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • USART
  • DMA_Interrupt
Functions

STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.
void | USART2_IRQHandler (void)
This function handles USART2 global interrupt request.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

  • File List
  • Globals
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  • DMA_Polling
Functions

STM32F10x_StdPeriph_Examples/USART/DMA_Polling/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/USART/DMA_Polling/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

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Functions

STM32F10x_StdPeriph_Examples/USART/HalfDuplex/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/USART/HalfDuplex/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

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Functions

STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

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Functions

STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.
void | USART1_IRQHandler (void)
void | USART2_IRQHandler (void)
This function handles USART2 global interrupt request.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.h.

Function Documentation

void USART1_IRQHandler ( void )


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

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Functions

STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.
void | USART1_IRQHandler (void)
void | USART2_IRQHandler (void)
This function handles USART2 global interrupt request.
void | USART3_IRQHandler (void)
This function handles USART3 global interrupt request.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.h.

Function Documentation

void USART1_IRQHandler ( void )


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

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  • Receive
Functions

STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

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  • Transmit
Functions

STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

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  • MultiProcessor
Functions

STM32F10x_StdPeriph_Examples/USART/MultiProcessor/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | EXTI0_IRQHandler (void)
This function handles External line 0 interrupt request.
void | EXTI9_5_IRQHandler (void)
This function handles EXTI Lines 9 to 5 interrupts requests.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/USART/MultiProcessor/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

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  • Project
  • STM32F10x_StdPeriph_Examples
  • USART
  • Polling
Functions

STM32F10x_StdPeriph_Examples/USART/Polling/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/USART/Polling/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

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  • Printf
Functions

STM32F10x_StdPeriph_Examples/USART/Printf/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/USART/Printf/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

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  • Smartcard
Functions

STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | EXTI15_10_IRQHandler (void)
This function handles External lines 15 to 10 interrupt request.
void | EXTI9_5_IRQHandler (void)
This function handles EXTI Lines 9 to 5 interrupts requests.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.
void | USART3_IRQHandler (void)
This function handles USART3 global interrupt request.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

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  • USART
  • Synchronous
Functions

STM32F10x_StdPeriph_Examples/USART/Synchronous/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/USART/Synchronous/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

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  • STM32F10x_StdPeriph_Lib_V3.5.0
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  • WWDG_Reset
Functions

STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | EXTI9_5_IRQHandler (void)
This function handles EXTI Lines 9 to 5 interrupts requests.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h File Reference

  • File List
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  • STM32F10x_StdPeriph_Template
Functions

STM32F10x_StdPeriph_Template/stm32f10x_it.h File Reference

This file contains the headers of the interrupt handlers. More...

#include "stm32f10x.h"

Go to the source code of this file.

Functions

void | BusFault_Handler (void)
This function handles Bus Fault exception.
void | DebugMon_Handler (void)
This function handles Debug Monitor exception.
void | HardFault_Handler (void)
This function handles Hard Fault exception.
void | MemManage_Handler (void)
This function handles Memory Manage exception.
void | NMI_Handler (void)
This function handles NMI exception.
void | PendSV_Handler (void)
This function handles PendSV_Handler exception.
void | SVC_Handler (void)
This function handles SVCall exception.
void | SysTick_Handler (void)
This function handles SysTick Handler.
void | UsageFault_Handler (void)
This function handles Usage Fault exception.

Detailed Description

This file contains the headers of the interrupt handlers.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file STM32F10x_StdPeriph_Template/stm32f10x_it.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_iwdg.c File Reference

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Defines | Functions

stm32f10x_iwdg.c File Reference

This file provides all the IWDG firmware functions. More...

#include "stm32f10x_iwdg.h"

Go to the source code of this file.

Defines

#define | KR_KEY_Enable ((uint16_t)0xCCCC)
#define | KR_KEY_Reload ((uint16_t)0xAAAA)

Functions

void | IWDG_Enable (void)
Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled).
FlagStatus | IWDG_GetFlagStatus (uint16_t IWDG_FLAG)
Checks whether the specified IWDG flag is set or not.
void | IWDG_ReloadCounter (void)
Reloads IWDG counter with value defined in the reload register (write access to IWDG_PR and IWDG_RLR registers disabled).
void | IWDG_SetPrescaler (uint8_t IWDG_Prescaler)
Sets IWDG Prescaler value.
void | IWDG_SetReload (uint16_t Reload)
Sets IWDG Reload value.
void | IWDG_WriteAccessCmd (uint16_t IWDG_WriteAccess)
Enables or disables write access to IWDG_PR and IWDG_RLR registers.

Detailed Description

This file provides all the IWDG firmware functions.

Author:
MCD Application Team
Version:
V3.5.0
Date:
11-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm32f10x_iwdg.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_iwdg.h File Reference

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  • STM32F10x_StdPeriph_Lib_V3.5.0
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  • inc
Defines | Functions

stm32f10x_iwdg.h File Reference

This file contains all the functions prototypes for the IWDG firmware library. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU))
#define | IS_IWDG_PRESCALER(PRESCALER)
#define | IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)
#define | IS_IWDG_WRITE_ACCESS(ACCESS)
#define | IWDG_FLAG_PVU ((uint16_t)0x0001)
#define | IWDG_FLAG_RVU ((uint16_t)0x0002)
#define | IWDG_Prescaler_128 ((uint8_t)0x05)
#define | IWDG_Prescaler_16 ((uint8_t)0x02)
#define | IWDG_Prescaler_256 ((uint8_t)0x06)
#define | IWDG_Prescaler_32 ((uint8_t)0x03)
#define | IWDG_Prescaler_4 ((uint8_t)0x00)
#define | IWDG_Prescaler_64 ((uint8_t)0x04)
#define | IWDG_Prescaler_8 ((uint8_t)0x01)
#define | IWDG_WriteAccess_Disable ((uint16_t)0x0000)
#define | IWDG_WriteAccess_Enable ((uint16_t)0x5555)

Functions

void | IWDG_Enable (void)
Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled).
FlagStatus | IWDG_GetFlagStatus (uint16_t IWDG_FLAG)
Checks whether the specified IWDG flag is set or not.
void | IWDG_ReloadCounter (void)
Reloads IWDG counter with value defined in the reload register (write access to IWDG_PR and IWDG_RLR registers disabled).
void | IWDG_SetPrescaler (uint8_t IWDG_Prescaler)
Sets IWDG Prescaler value.
void | IWDG_SetReload (uint16_t Reload)
Sets IWDG Reload value.
void | IWDG_WriteAccessCmd (uint16_t IWDG_WriteAccess)
Enables or disables write access to IWDG_PR and IWDG_RLR registers.

Detailed Description

This file contains all the functions prototypes for the IWDG firmware library.

Author:
MCD Application Team
Version:
V3.5.0
Date:
11-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm32f10x_iwdg.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_pwr.c File Reference

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  • STM32F10x_StdPeriph_Lib_V3.5.0
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  • src
Defines | Functions

stm32f10x_pwr.c File Reference

This file provides all the PWR firmware functions. More...

#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"

Go to the source code of this file.

Defines

#define | CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))
#define | CR_DS_MASK ((uint32_t)0xFFFFFFFC)
#define | CR_OFFSET (PWR_OFFSET + 0x00)
#define | CR_PLS_MASK ((uint32_t)0xFFFFFF1F)
#define | CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))
#define | CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))
#define | CSR_OFFSET (PWR_OFFSET + 0x04)
#define | DBP_BitNumber 0x08
#define | EWUP_BitNumber 0x08
#define | PVDE_BitNumber 0x04
#define | PWR_OFFSET (PWR_BASE - PERIPH_BASE)

Functions

void | PWR_BackupAccessCmd (FunctionalState NewState)
Enables or disables access to the RTC and backup registers.
void | PWR_ClearFlag (uint32_t PWR_FLAG)
Clears the PWR's pending flags.
void | PWR_DeInit (void)
Deinitializes the PWR peripheral registers to their default reset values.
void | PWR_EnterSTANDBYMode (void)
Enters STANDBY mode.
void | PWR_EnterSTOPMode (uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
Enters STOP mode.
FlagStatus | PWR_GetFlagStatus (uint32_t PWR_FLAG)
Checks whether the specified PWR flag is set or not.
void | PWR_PVDCmd (FunctionalState NewState)
Enables or disables the Power Voltage Detector(PVD).
void | PWR_PVDLevelConfig (uint32_t PWR_PVDLevel)
Configures the voltage threshold detected by the Power Voltage Detector(PVD).
void | PWR_WakeUpPinCmd (FunctionalState NewState)
Enables or disables the WakeUp Pin functionality.

Detailed Description

This file provides all the PWR firmware functions.

Author:
MCD Application Team
Version:
V3.5.0
Date:
11-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm32f10x_pwr.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_pwr.h File Reference

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  • inc
Defines | Functions

stm32f10x_pwr.h File Reference

This file contains all the functions prototypes for the PWR firmware library. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB))
#define | IS_PWR_GET_FLAG(FLAG)
#define | IS_PWR_PVD_LEVEL(LEVEL)
#define | IS_PWR_REGULATOR(REGULATOR)
#define | IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE))
#define | PWR_FLAG_PVDO ((uint32_t)0x00000004)
#define | PWR_FLAG_SB ((uint32_t)0x00000002)
#define | PWR_FLAG_WU ((uint32_t)0x00000001)
#define | PWR_PVDLevel_2V2 ((uint32_t)0x00000000)
#define | PWR_PVDLevel_2V3 ((uint32_t)0x00000020)
#define | PWR_PVDLevel_2V4 ((uint32_t)0x00000040)
#define | PWR_PVDLevel_2V5 ((uint32_t)0x00000060)
#define | PWR_PVDLevel_2V6 ((uint32_t)0x00000080)
#define | PWR_PVDLevel_2V7 ((uint32_t)0x000000A0)
#define | PWR_PVDLevel_2V8 ((uint32_t)0x000000C0)
#define | PWR_PVDLevel_2V9 ((uint32_t)0x000000E0)
#define | PWR_Regulator_LowPower ((uint32_t)0x00000001)
#define | PWR_Regulator_ON ((uint32_t)0x00000000)
#define | PWR_STOPEntry_WFE ((uint8_t)0x02)
#define | PWR_STOPEntry_WFI ((uint8_t)0x01)

Functions

void | PWR_BackupAccessCmd (FunctionalState NewState)
Enables or disables access to the RTC and backup registers.
void | PWR_ClearFlag (uint32_t PWR_FLAG)
Clears the PWR's pending flags.
void | PWR_DeInit (void)
Deinitializes the PWR peripheral registers to their default reset values.
void | PWR_EnterSTANDBYMode (void)
Enters STANDBY mode.
void | PWR_EnterSTOPMode (uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
Enters STOP mode.
FlagStatus | PWR_GetFlagStatus (uint32_t PWR_FLAG)
Checks whether the specified PWR flag is set or not.
void | PWR_PVDCmd (FunctionalState NewState)
Enables or disables the Power Voltage Detector(PVD).
void | PWR_PVDLevelConfig (uint32_t PWR_PVDLevel)
Configures the voltage threshold detected by the Power Voltage Detector(PVD).
void | PWR_WakeUpPinCmd (FunctionalState NewState)
Enables or disables the WakeUp Pin functionality.

Detailed Description

This file contains all the functions prototypes for the PWR firmware library.

Author:
MCD Application Team
Version:
V3.5.0
Date:
11-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm32f10x_pwr.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_rcc.c File Reference

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  • src
Defines | Functions | Variables

stm32f10x_rcc.c File Reference

This file provides all the RCC firmware functions. More...

#include "stm32f10x_rcc.h"

Go to the source code of this file.

Defines

#define | BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET)
#define | BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))
#define | BDCR_OFFSET (RCC_OFFSET + 0x20)
#define | BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))
#define | BDRST_BitNumber 0x10
#define | CFGR_ADCPRE_Reset_Mask ((uint32_t)0xFFFF3FFF)
#define | CFGR_ADCPRE_Set_Mask ((uint32_t)0x0000C000)
#define | CFGR_BYTE4_ADDRESS ((uint32_t)0x40021007)
#define | CFGR_HPRE_Reset_Mask ((uint32_t)0xFFFFFF0F)
#define | CFGR_HPRE_Set_Mask ((uint32_t)0x000000F0)
#define | CFGR_OFFSET (RCC_OFFSET + 0x04)
#define | CFGR_PLL_Mask ((uint32_t)0xFFC0FFFF)
#define | CFGR_PLLMull_Mask ((uint32_t)0x003C0000)
#define | CFGR_PLLSRC_Mask ((uint32_t)0x00010000)
#define | CFGR_PLLXTPRE_Mask ((uint32_t)0x00020000)
#define | CFGR_PPRE1_Reset_Mask ((uint32_t)0xFFFFF8FF)
#define | CFGR_PPRE1_Set_Mask ((uint32_t)0x00000700)
#define | CFGR_PPRE2_Reset_Mask ((uint32_t)0xFFFFC7FF)
#define | CFGR_PPRE2_Set_Mask ((uint32_t)0x00003800)
#define | CFGR_SW_Mask ((uint32_t)0xFFFFFFFC)
#define | CFGR_SWS_Mask ((uint32_t)0x0000000C)
#define | CFGR_USBPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (USBPRE_BitNumber * 4))
#define | CIR_BYTE2_ADDRESS ((uint32_t)0x40021009)
#define | CIR_BYTE3_ADDRESS ((uint32_t)0x4002100A)
#define | CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))
#define | CR_HSEBYP_Reset ((uint32_t)0xFFFBFFFF)
#define | CR_HSEBYP_Set ((uint32_t)0x00040000)
#define | CR_HSEON_Reset ((uint32_t)0xFFFEFFFF)
#define | CR_HSEON_Set ((uint32_t)0x00010000)
#define | CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))
#define | CR_HSITRIM_Mask ((uint32_t)0xFFFFFF07)
#define | CR_OFFSET (RCC_OFFSET + 0x00)
#define | CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))
#define | CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))
#define | CSR_OFFSET (RCC_OFFSET + 0x24)
#define | CSR_RMVF_Set ((uint32_t)0x01000000)
#define | CSSON_BitNumber 0x13
#define | FLAG_Mask ((uint8_t)0x1F)
#define | HSION_BitNumber 0x00
#define | LSION_BitNumber 0x00
#define | PLLON_BitNumber 0x18
#define | RCC_OFFSET (RCC_BASE - PERIPH_BASE)
#define | RTCEN_BitNumber 0x0F
#define | USBPRE_BitNumber 0x16

Functions

void | RCC_ADCCLKConfig (uint32_t RCC_PCLK2)
Configures the ADC clock (ADCCLK).
void | RCC_AdjustHSICalibrationValue (uint8_t HSICalibrationValue)
Adjusts the Internal High Speed oscillator (HSI) calibration value.
void | RCC_AHBPeriphClockCmd (uint32_t RCC_AHBPeriph, FunctionalState NewState)
Enables or disables the AHB peripheral clock.
void | RCC_APB1PeriphClockCmd (uint32_t RCC_APB1Periph, FunctionalState NewState)
Enables or disables the Low Speed APB (APB1) peripheral clock.
void | RCC_APB1PeriphResetCmd (uint32_t RCC_APB1Periph, FunctionalState NewState)
Forces or releases Low Speed APB (APB1) peripheral reset.
void | RCC_APB2PeriphClockCmd (uint32_t RCC_APB2Periph, FunctionalState NewState)
Enables or disables the High Speed APB (APB2) peripheral clock.
void | RCC_APB2PeriphResetCmd (uint32_t RCC_APB2Periph, FunctionalState NewState)
Forces or releases High Speed APB (APB2) peripheral reset.
void | RCC_BackupResetCmd (FunctionalState NewState)
Forces or releases the Backup domain reset.
void | RCC_ClearFlag (void)
Clears the RCC reset flags.
void | RCC_ClearITPendingBit (uint8_t RCC_IT)
Clears the RCC's interrupt pending bits.
void | RCC_ClockSecuritySystemCmd (FunctionalState NewState)
Enables or disables the Clock Security System.
void | RCC_DeInit (void)
Resets the RCC clock configuration to the default reset state.
void | RCC_GetClocksFreq (RCC_ClocksTypeDef *RCC_Clocks)
Returns the frequencies of different on chip clocks.
FlagStatus | RCC_GetFlagStatus (uint8_t RCC_FLAG)
Checks whether the specified RCC flag is set or not.
ITStatus | RCC_GetITStatus (uint8_t RCC_IT)
Checks whether the specified RCC interrupt has occurred or not.
uint8_t | RCC_GetSYSCLKSource (void)
Returns the clock source used as system clock.
void | RCC_HCLKConfig (uint32_t RCC_SYSCLK)
Configures the AHB clock (HCLK).
void | RCC_HSEConfig (uint32_t RCC_HSE)
Configures the External High Speed oscillator (HSE).
void | RCC_HSICmd (FunctionalState NewState)
Enables or disables the Internal High Speed oscillator (HSI).
void | RCC_ITConfig (uint8_t RCC_IT, FunctionalState NewState)
Enables or disables the specified RCC interrupts.
void | RCC_LSEConfig (uint8_t RCC_LSE)
Configures the External Low Speed oscillator (LSE).
void | RCC_LSICmd (FunctionalState NewState)
Enables or disables the Internal Low Speed oscillator (LSI).
void | RCC_MCOConfig (uint8_t RCC_MCO)
Selects the clock source to output on MCO pin.
void | RCC_PCLK1Config (uint32_t RCC_HCLK)
Configures the Low Speed APB clock (PCLK1).
void | RCC_PCLK2Config (uint32_t RCC_HCLK)
Configures the High Speed APB clock (PCLK2).
void | RCC_PLLCmd (FunctionalState NewState)
Enables or disables the PLL.
void | RCC_PLLConfig (uint32_t RCC_PLLSource, uint32_t RCC_PLLMul)
Configures the PLL clock source and multiplication factor.
void | RCC_RTCCLKCmd (FunctionalState NewState)
Enables or disables the RTC clock.
void | RCC_RTCCLKConfig (uint32_t RCC_RTCCLKSource)
Configures the RTC clock (RTCCLK).
void | RCC_SYSCLKConfig (uint32_t RCC_SYSCLKSource)
Configures the system clock (SYSCLK).
void | RCC_USBCLKConfig (uint32_t RCC_USBCLKSource)
Configures the USB clock (USBCLK).
ErrorStatus | RCC_WaitForHSEStartUp (void)
Waits for HSE start-up.

Variables

static __I uint8_t | ADCPrescTable [4] = {2, 4, 6, 8}
static __I uint8_t | APBAHBPrescTable [16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}

Detailed Description

This file provides all the RCC firmware functions.

Author:
MCD Application Team
Version:
V3.5.0
Date:
11-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm32f10x_rcc.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_rcc.h File Reference

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Data Structures | Defines | Functions

stm32f10x_rcc.h File Reference

This file contains all the functions prototypes for the RCC firmware library. More...

#include "stm32f10x.h"

Go to the source code of this file.

Data Structures

struct | RCC_ClocksTypeDef

Defines

#define | IS_RCC_ADCCLK(ADCCLK)
#define | IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFAA8) == 0x00) && ((PERIPH) != 0x00))
#define | IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x81013600) == 0x00) && ((PERIPH) != 0x00))
#define | IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFC00002) == 0x00) && ((PERIPH) != 0x00))
#define | IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
#define | IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x60) == 0x00) && ((IT) != 0x00))
#define | IS_RCC_FLAG(FLAG)
#define | IS_RCC_GET_IT(IT)
#define | IS_RCC_HCLK(HCLK)
#define | IS_RCC_HSE(HSE)
#define | IS_RCC_IT(IT) ((((IT) & (uint8_t)0xE0) == 0x00) && ((IT) != 0x00))
#define | IS_RCC_LSE(LSE)
#define | IS_RCC_MCO(MCO)
#define | IS_RCC_PCLK(PCLK)
#define | IS_RCC_PLL_MUL(MUL)
#define | IS_RCC_PLL_SOURCE(SOURCE)
#define | IS_RCC_RTCCLK_SOURCE(SOURCE)
#define | IS_RCC_SYSCLK_SOURCE(SOURCE)
#define | IS_RCC_USBCLK_SOURCE(SOURCE)
#define | RCC_AHBPeriph_CRC ((uint32_t)0x00000040)
#define | RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001)
#define | RCC_AHBPeriph_DMA2 ((uint32_t)0x00000002)
#define | RCC_AHBPeriph_FLITF ((uint32_t)0x00000010)
#define | RCC_AHBPeriph_FSMC ((uint32_t)0x00000100)
#define | RCC_AHBPeriph_SDIO ((uint32_t)0x00000400)
#define | RCC_AHBPeriph_SRAM ((uint32_t)0x00000004)
#define | RCC_APB1Periph_BKP ((uint32_t)0x08000000)
#define | RCC_APB1Periph_CAN1 ((uint32_t)0x02000000)
#define | RCC_APB1Periph_CAN2 ((uint32_t)0x04000000)
#define | RCC_APB1Periph_CEC ((uint32_t)0x40000000)
#define | RCC_APB1Periph_DAC ((uint32_t)0x20000000)
#define | RCC_APB1Periph_I2C1 ((uint32_t)0x00200000)
#define | RCC_APB1Periph_I2C2 ((uint32_t)0x00400000)
#define | RCC_APB1Periph_PWR ((uint32_t)0x10000000)
#define | RCC_APB1Periph_SPI2 ((uint32_t)0x00004000)
#define | RCC_APB1Periph_SPI3 ((uint32_t)0x00008000)
#define | RCC_APB1Periph_TIM12 ((uint32_t)0x00000040)
#define | RCC_APB1Periph_TIM13 ((uint32_t)0x00000080)
#define | RCC_APB1Periph_TIM14 ((uint32_t)0x00000100)
#define | RCC_APB1Periph_TIM2 ((uint32_t)0x00000001)
#define | RCC_APB1Periph_TIM3 ((uint32_t)0x00000002)
#define | RCC_APB1Periph_TIM4 ((uint32_t)0x00000004)
#define | RCC_APB1Periph_TIM5 ((uint32_t)0x00000008)
#define | RCC_APB1Periph_TIM6 ((uint32_t)0x00000010)
#define | RCC_APB1Periph_TIM7 ((uint32_t)0x00000020)
#define | RCC_APB1Periph_UART4 ((uint32_t)0x00080000)
#define | RCC_APB1Periph_UART5 ((uint32_t)0x00100000)
#define | RCC_APB1Periph_USART2 ((uint32_t)0x00020000)
#define | RCC_APB1Periph_USART3 ((uint32_t)0x00040000)
#define | RCC_APB1Periph_USB ((uint32_t)0x00800000)
#define | RCC_APB1Periph_WWDG ((uint32_t)0x00000800)
#define | RCC_APB2Periph_ADC1 ((uint32_t)0x00000200)
#define | RCC_APB2Periph_ADC2 ((uint32_t)0x00000400)
#define | RCC_APB2Periph_ADC3 ((uint32_t)0x00008000)
#define | RCC_APB2Periph_AFIO ((uint32_t)0x00000001)
#define | RCC_APB2Periph_GPIOA ((uint32_t)0x00000004)
#define | RCC_APB2Periph_GPIOB ((uint32_t)0x00000008)
#define | RCC_APB2Periph_GPIOC ((uint32_t)0x00000010)
#define | RCC_APB2Periph_GPIOD ((uint32_t)0x00000020)
#define | RCC_APB2Periph_GPIOE ((uint32_t)0x00000040)
#define | RCC_APB2Periph_GPIOF ((uint32_t)0x00000080)
#define | RCC_APB2Periph_GPIOG ((uint32_t)0x00000100)
#define | RCC_APB2Periph_SPI1 ((uint32_t)0x00001000)
#define | RCC_APB2Periph_TIM1 ((uint32_t)0x00000800)
#define | RCC_APB2Periph_TIM10 ((uint32_t)0x00100000)
#define | RCC_APB2Periph_TIM11 ((uint32_t)0x00200000)
#define | RCC_APB2Periph_TIM15 ((uint32_t)0x00010000)
#define | RCC_APB2Periph_TIM16 ((uint32_t)0x00020000)
#define | RCC_APB2Periph_TIM17 ((uint32_t)0x00040000)
#define | RCC_APB2Periph_TIM8 ((uint32_t)0x00002000)
#define | RCC_APB2Periph_TIM9 ((uint32_t)0x00080000)
#define | RCC_APB2Periph_USART1 ((uint32_t)0x00004000)
#define | RCC_FLAG_HSERDY ((uint8_t)0x31)
#define | RCC_FLAG_HSIRDY ((uint8_t)0x21)
#define | RCC_FLAG_IWDGRST ((uint8_t)0x7D)
#define | RCC_FLAG_LPWRRST ((uint8_t)0x7F)
#define | RCC_FLAG_LSERDY ((uint8_t)0x41)
#define | RCC_FLAG_LSIRDY ((uint8_t)0x61)
#define | RCC_FLAG_PINRST ((uint8_t)0x7A)
#define | RCC_FLAG_PLLRDY ((uint8_t)0x39)
#define | RCC_FLAG_PORRST ((uint8_t)0x7B)
#define | RCC_FLAG_SFTRST ((uint8_t)0x7C)
#define | RCC_FLAG_WWDGRST ((uint8_t)0x7E)
#define | RCC_HCLK_Div1 ((uint32_t)0x00000000)
#define | RCC_HCLK_Div16 ((uint32_t)0x00000700)
#define | RCC_HCLK_Div2 ((uint32_t)0x00000400)
#define | RCC_HCLK_Div4 ((uint32_t)0x00000500)
#define | RCC_HCLK_Div8 ((uint32_t)0x00000600)
#define | RCC_HSE_Bypass ((uint32_t)0x00040000)
#define | RCC_HSE_OFF ((uint32_t)0x00000000)
#define | RCC_HSE_ON ((uint32_t)0x00010000)
#define | RCC_IT_CSS ((uint8_t)0x80)
#define | RCC_IT_HSERDY ((uint8_t)0x08)
#define | RCC_IT_HSIRDY ((uint8_t)0x04)
#define | RCC_IT_LSERDY ((uint8_t)0x02)
#define | RCC_IT_LSIRDY ((uint8_t)0x01)
#define | RCC_IT_PLLRDY ((uint8_t)0x10)
#define | RCC_LSE_Bypass ((uint8_t)0x04)
#define | RCC_LSE_OFF ((uint8_t)0x00)
#define | RCC_LSE_ON ((uint8_t)0x01)
#define | RCC_MCO_HSE ((uint8_t)0x06)
#define | RCC_MCO_HSI ((uint8_t)0x05)
#define | RCC_MCO_NoClock ((uint8_t)0x00)
#define | RCC_MCO_PLLCLK_Div2 ((uint8_t)0x07)
#define | RCC_MCO_SYSCLK ((uint8_t)0x04)
#define | RCC_PCLK2_Div2 ((uint32_t)0x00000000)
#define | RCC_PCLK2_Div4 ((uint32_t)0x00004000)
#define | RCC_PCLK2_Div6 ((uint32_t)0x00008000)
#define | RCC_PCLK2_Div8 ((uint32_t)0x0000C000)
#define | RCC_PLLMul_10 ((uint32_t)0x00200000)
#define | RCC_PLLMul_11 ((uint32_t)0x00240000)
#define | RCC_PLLMul_12 ((uint32_t)0x00280000)
#define | RCC_PLLMul_13 ((uint32_t)0x002C0000)
#define | RCC_PLLMul_14 ((uint32_t)0x00300000)
#define | RCC_PLLMul_15 ((uint32_t)0x00340000)
#define | RCC_PLLMul_16 ((uint32_t)0x00380000)
#define | RCC_PLLMul_2 ((uint32_t)0x00000000)
#define | RCC_PLLMul_3 ((uint32_t)0x00040000)
#define | RCC_PLLMul_4 ((uint32_t)0x00080000)
#define | RCC_PLLMul_5 ((uint32_t)0x000C0000)
#define | RCC_PLLMul_6 ((uint32_t)0x00100000)
#define | RCC_PLLMul_7 ((uint32_t)0x00140000)
#define | RCC_PLLMul_8 ((uint32_t)0x00180000)
#define | RCC_PLLMul_9 ((uint32_t)0x001C0000)
#define | RCC_PLLSource_HSE_Div1 ((uint32_t)0x00010000)
#define | RCC_PLLSource_HSE_Div2 ((uint32_t)0x00030000)
#define | RCC_PLLSource_HSI_Div2 ((uint32_t)0x00000000)
#define | RCC_RTCCLKSource_HSE_Div128 ((uint32_t)0x00000300)
#define | RCC_RTCCLKSource_LSE ((uint32_t)0x00000100)
#define | RCC_RTCCLKSource_LSI ((uint32_t)0x00000200)
#define | RCC_SYSCLK_Div1 ((uint32_t)0x00000000)
#define | RCC_SYSCLK_Div128 ((uint32_t)0x000000D0)
#define | RCC_SYSCLK_Div16 ((uint32_t)0x000000B0)
#define | RCC_SYSCLK_Div2 ((uint32_t)0x00000080)
#define | RCC_SYSCLK_Div256 ((uint32_t)0x000000E0)
#define | RCC_SYSCLK_Div4 ((uint32_t)0x00000090)
#define | RCC_SYSCLK_Div512 ((uint32_t)0x000000F0)
#define | RCC_SYSCLK_Div64 ((uint32_t)0x000000C0)
#define | RCC_SYSCLK_Div8 ((uint32_t)0x000000A0)
#define | RCC_SYSCLKSource_HSE ((uint32_t)0x00000001)
#define | RCC_SYSCLKSource_HSI ((uint32_t)0x00000000)
#define | RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002)
#define | RCC_USBCLKSource_PLLCLK_1Div5 ((uint8_t)0x00)
#define | RCC_USBCLKSource_PLLCLK_Div1 ((uint8_t)0x01)

Functions

void | RCC_ADCCLKConfig (uint32_t RCC_PCLK2)
Configures the ADC clock (ADCCLK).
void | RCC_AdjustHSICalibrationValue (uint8_t HSICalibrationValue)
Adjusts the Internal High Speed oscillator (HSI) calibration value.
void | RCC_AHBPeriphClockCmd (uint32_t RCC_AHBPeriph, FunctionalState NewState)
Enables or disables the AHB peripheral clock.
void | RCC_APB1PeriphClockCmd (uint32_t RCC_APB1Periph, FunctionalState NewState)
Enables or disables the Low Speed APB (APB1) peripheral clock.
void | RCC_APB1PeriphResetCmd (uint32_t RCC_APB1Periph, FunctionalState NewState)
Forces or releases Low Speed APB (APB1) peripheral reset.
void | RCC_APB2PeriphClockCmd (uint32_t RCC_APB2Periph, FunctionalState NewState)
Enables or disables the High Speed APB (APB2) peripheral clock.
void | RCC_APB2PeriphResetCmd (uint32_t RCC_APB2Periph, FunctionalState NewState)
Forces or releases High Speed APB (APB2) peripheral reset.
void | RCC_BackupResetCmd (FunctionalState NewState)
Forces or releases the Backup domain reset.
void | RCC_ClearFlag (void)
Clears the RCC reset flags.
void | RCC_ClearITPendingBit (uint8_t RCC_IT)
Clears the RCC's interrupt pending bits.
void | RCC_ClockSecuritySystemCmd (FunctionalState NewState)
Enables or disables the Clock Security System.
void | RCC_DeInit (void)
Resets the RCC clock configuration to the default reset state.
void | RCC_GetClocksFreq (RCC_ClocksTypeDef *RCC_Clocks)
Returns the frequencies of different on chip clocks.
FlagStatus | RCC_GetFlagStatus (uint8_t RCC_FLAG)
Checks whether the specified RCC flag is set or not.
ITStatus | RCC_GetITStatus (uint8_t RCC_IT)
Checks whether the specified RCC interrupt has occurred or not.
uint8_t | RCC_GetSYSCLKSource (void)
Returns the clock source used as system clock.
void | RCC_HCLKConfig (uint32_t RCC_SYSCLK)
Configures the AHB clock (HCLK).
void | RCC_HSEConfig (uint32_t RCC_HSE)
Configures the External High Speed oscillator (HSE).
void | RCC_HSICmd (FunctionalState NewState)
Enables or disables the Internal High Speed oscillator (HSI).
void | RCC_ITConfig (uint8_t RCC_IT, FunctionalState NewState)
Enables or disables the specified RCC interrupts.
void | RCC_LSEConfig (uint8_t RCC_LSE)
Configures the External Low Speed oscillator (LSE).
void | RCC_LSICmd (FunctionalState NewState)
Enables or disables the Internal Low Speed oscillator (LSI).
void | RCC_MCOConfig (uint8_t RCC_MCO)
Selects the clock source to output on MCO pin.
void | RCC_PCLK1Config (uint32_t RCC_HCLK)
Configures the Low Speed APB clock (PCLK1).
void | RCC_PCLK2Config (uint32_t RCC_HCLK)
Configures the High Speed APB clock (PCLK2).
void | RCC_PLLCmd (FunctionalState NewState)
Enables or disables the PLL.
void | RCC_PLLConfig (uint32_t RCC_PLLSource, uint32_t RCC_PLLMul)
Configures the PLL clock source and multiplication factor.
void | RCC_RTCCLKCmd (FunctionalState NewState)
Enables or disables the RTC clock.
void | RCC_RTCCLKConfig (uint32_t RCC_RTCCLKSource)
Configures the RTC clock (RTCCLK).
void | RCC_SYSCLKConfig (uint32_t RCC_SYSCLKSource)
Configures the system clock (SYSCLK).
void | RCC_USBCLKConfig (uint32_t RCC_USBCLKSource)
Configures the USB clock (USBCLK).
ErrorStatus | RCC_WaitForHSEStartUp (void)
Waits for HSE start-up.

Detailed Description

This file contains all the functions prototypes for the RCC firmware library.

Author:
MCD Application Team
Version:
V3.5.0
Date:
11-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm32f10x_rcc.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_rtc.c File Reference

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  • src
Defines | Functions

stm32f10x_rtc.c File Reference

This file provides all the RTC firmware functions. More...

#include "stm32f10x_rtc.h"

Go to the source code of this file.

Defines

#define | PRLH_MSB_MASK ((uint32_t)0x000F0000)
#define | RTC_LSB_MASK ((uint32_t)0x0000FFFF)

Functions

void | RTC_ClearFlag (uint16_t RTC_FLAG)
Clears the RTC's pending flags.
void | RTC_ClearITPendingBit (uint16_t RTC_IT)
Clears the RTC's interrupt pending bits.
void | RTC_EnterConfigMode (void)
Enters the RTC configuration mode.
void | RTC_ExitConfigMode (void)
Exits from the RTC configuration mode.
uint32_t | RTC_GetCounter (void)
Gets the RTC counter value.
uint32_t | RTC_GetDivider (void)
Gets the RTC divider value.
FlagStatus | RTC_GetFlagStatus (uint16_t RTC_FLAG)
Checks whether the specified RTC flag is set or not.
ITStatus | RTC_GetITStatus (uint16_t RTC_IT)
Checks whether the specified RTC interrupt has occurred or not.
void | RTC_ITConfig (uint16_t RTC_IT, FunctionalState NewState)
Enables or disables the specified RTC interrupts.
void | RTC_SetAlarm (uint32_t AlarmValue)
Sets the RTC alarm value.
void | RTC_SetCounter (uint32_t CounterValue)
Sets the RTC counter value.
void | RTC_SetPrescaler (uint32_t PrescalerValue)
Sets the RTC prescaler value.
void | RTC_WaitForLastTask (void)
Waits until last write operation on RTC registers has finished.
void | RTC_WaitForSynchro (void)
Waits until the RTC registers (RTC_CNT, RTC_ALR and RTC_PRL) are synchronized with RTC APB clock.

Detailed Description

This file provides all the RTC firmware functions.

Author:
MCD Application Team
Version:
V3.5.0
Date:
11-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm32f10x_rtc.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_rtc.h File Reference

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  • STM32F10x_StdPeriph_Lib_V3.5.0
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  • inc
Defines | Functions

stm32f10x_rtc.h File Reference

This file contains all the functions prototypes for the RTC firmware library. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | IS_RTC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFFF0) == 0x00) && ((FLAG) != 0x00))
#define | IS_RTC_GET_FLAG(FLAG)
#define | IS_RTC_GET_IT(IT)
#define | IS_RTC_IT(IT) ((((IT) & (uint16_t)0xFFF8) == 0x00) && ((IT) != 0x00))
#define | IS_RTC_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFFFF)
#define | RTC_FLAG_ALR ((uint16_t)0x0002)
#define | RTC_FLAG_OW ((uint16_t)0x0004)
#define | RTC_FLAG_RSF ((uint16_t)0x0008)
#define | RTC_FLAG_RTOFF ((uint16_t)0x0020)
#define | RTC_FLAG_SEC ((uint16_t)0x0001)
#define | RTC_IT_ALR ((uint16_t)0x0002)
#define | RTC_IT_OW ((uint16_t)0x0004)
#define | RTC_IT_SEC ((uint16_t)0x0001)

Functions

void | RTC_ClearFlag (uint16_t RTC_FLAG)
Clears the RTC's pending flags.
void | RTC_ClearITPendingBit (uint16_t RTC_IT)
Clears the RTC's interrupt pending bits.
void | RTC_EnterConfigMode (void)
Enters the RTC configuration mode.
void | RTC_ExitConfigMode (void)
Exits from the RTC configuration mode.
uint32_t | RTC_GetCounter (void)
Gets the RTC counter value.
uint32_t | RTC_GetDivider (void)
Gets the RTC divider value.
FlagStatus | RTC_GetFlagStatus (uint16_t RTC_FLAG)
Checks whether the specified RTC flag is set or not.
ITStatus | RTC_GetITStatus (uint16_t RTC_IT)
Checks whether the specified RTC interrupt has occurred or not.
void | RTC_ITConfig (uint16_t RTC_IT, FunctionalState NewState)
Enables or disables the specified RTC interrupts.
void | RTC_SetAlarm (uint32_t AlarmValue)
Sets the RTC alarm value.
void | RTC_SetCounter (uint32_t CounterValue)
Sets the RTC counter value.
void | RTC_SetPrescaler (uint32_t PrescalerValue)
Sets the RTC prescaler value.
void | RTC_WaitForLastTask (void)
Waits until last write operation on RTC registers has finished.
void | RTC_WaitForSynchro (void)
Waits until the RTC registers (RTC_CNT, RTC_ALR and RTC_PRL) are synchronized with RTC APB clock.

Detailed Description

This file contains all the functions prototypes for the RTC firmware library.

Author:
MCD Application Team
Version:
V3.5.0
Date:
11-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm32f10x_rtc.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_sdio.c File Reference

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Defines | Functions

stm32f10x_sdio.c File Reference

This file provides all the SDIO firmware functions. More...

#include "stm32f10x_sdio.h"
#include "stm32f10x_rcc.h"

Go to the source code of this file.

Defines

#define | ATACMD_BitNumber 0x0E
#define | CLKCR_CLEAR_MASK ((uint32_t)0xFFFF8100)
#define | CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4))
#define | CLKCR_OFFSET (SDIO_OFFSET + 0x04)
#define | CLKEN_BitNumber 0x08
#define | CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4))
#define | CMD_CLEAR_MASK ((uint32_t)0xFFFFF800)
#define | CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4))
#define | CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4))
#define | CMD_OFFSET (SDIO_OFFSET + 0x0C)
#define | CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4))
#define | DCTRL_CLEAR_MASK ((uint32_t)0xFFFFFF08)
#define | DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4))
#define | DCTRL_OFFSET (SDIO_OFFSET + 0x2C)
#define | DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4))
#define | DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4))
#define | DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4))
#define | DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4))
#define | DMAEN_BitNumber 0x03
#define | ENCMDCOMPL_BitNumber 0x0C
#define | NIEN_BitNumber 0x0D
#define | PWR_PWRCTRL_MASK ((uint32_t)0xFFFFFFFC)
#define | RWMOD_BitNumber 0x0A
#define | RWSTART_BitNumber 0x08
#define | RWSTOP_BitNumber 0x09
#define | SDIO_OFFSET (SDIO_BASE - PERIPH_BASE)
#define | SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14))
#define | SDIOEN_BitNumber 0x0B
#define | SDIOSUSPEND_BitNumber 0x0B

Functions

void | SDIO_CEATAITCmd (FunctionalState NewState)
Enables or disables the CE-ATA interrupt.
void | SDIO_ClearFlag (uint32_t SDIO_FLAG)
Clears the SDIO's pending flags.
void | SDIO_ClearITPendingBit (uint32_t SDIO_IT)
Clears the SDIO's interrupt pending bits.
void | SDIO_ClockCmd (FunctionalState NewState)
Enables or disables the SDIO Clock.
void | SDIO_CmdStructInit (SDIO_CmdInitTypeDef *SDIO_CmdInitStruct)
Fills each SDIO_CmdInitStruct member with its default value.
void | SDIO_CommandCompletionCmd (FunctionalState NewState)
Enables or disables the command completion signal.
void | SDIO_DataConfig (SDIO_DataInitTypeDef *SDIO_DataInitStruct)
Initializes the SDIO data path according to the specified parameters in the SDIO_DataInitStruct.
void | SDIO_DataStructInit (SDIO_DataInitTypeDef *SDIO_DataInitStruct)
Fills each SDIO_DataInitStruct member with its default value.
void | SDIO_DeInit (void)
Deinitializes the SDIO peripheral registers to their default reset values.
void | SDIO_DMACmd (FunctionalState NewState)
Enables or disables the SDIO DMA request.
uint8_t | SDIO_GetCommandResponse (void)
Returns command index of last command for which response received.
uint32_t | SDIO_GetDataCounter (void)
Returns number of remaining data bytes to be transferred.
uint32_t | SDIO_GetFIFOCount (void)
Returns the number of words left to be written to or read from FIFO.
FlagStatus | SDIO_GetFlagStatus (uint32_t SDIO_FLAG)
Checks whether the specified SDIO flag is set or not.
ITStatus | SDIO_GetITStatus (uint32_t SDIO_IT)
Checks whether the specified SDIO interrupt has occurred or not.
uint32_t | SDIO_GetPowerState (void)
Gets the power status of the controller.
uint32_t | SDIO_GetResponse (uint32_t SDIO_RESP)
Returns response received from the card for the last command.
void | SDIO_Init (SDIO_InitTypeDef *SDIO_InitStruct)
Initializes the SDIO peripheral according to the specified parameters in the SDIO_InitStruct.
void | SDIO_ITConfig (uint32_t SDIO_IT, FunctionalState NewState)
Enables or disables the SDIO interrupts.
uint32_t | SDIO_ReadData (void)
Read one data word from Rx FIFO.
void | SDIO_SendCEATACmd (FunctionalState NewState)
Sends CE-ATA command (CMD61).
void | SDIO_SendCommand (SDIO_CmdInitTypeDef *SDIO_CmdInitStruct)
Initializes the SDIO Command according to the specified parameters in the SDIO_CmdInitStruct and send the command.
void | SDIO_SendSDIOSuspendCmd (FunctionalState NewState)
Enables or disables the SD I/O Mode suspend command sending.
void | SDIO_SetPowerState (uint32_t SDIO_PowerState)
Sets the power status of the controller.
void | SDIO_SetSDIOOperation (FunctionalState NewState)
Enables or disables the SD I/O Mode Operation.
void | SDIO_SetSDIOReadWaitMode (uint32_t SDIO_ReadWaitMode)
Sets one of the two options of inserting read wait interval.
void | SDIO_StartSDIOReadWait (FunctionalState NewState)
Starts the SD I/O Read Wait operation.
void | SDIO_StopSDIOReadWait (FunctionalState NewState)
Stops the SD I/O Read Wait operation.
void | SDIO_StructInit (SDIO_InitTypeDef *SDIO_InitStruct)
Fills each SDIO_InitStruct member with its default value.
void | SDIO_WriteData (uint32_t Data)
Write one data word to Tx FIFO.

Detailed Description

This file provides all the SDIO firmware functions.

Author:
MCD Application Team
Version:
V3.5.0
Date:
11-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm32f10x_sdio.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_sdio.h File Reference

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  • STM32F10x_StdPeriph_Lib_V3.5.0
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  • inc
Data Structures | Defines | Functions

stm32f10x_sdio.h File Reference

This file contains all the functions prototypes for the SDIO firmware library. More...

#include "stm32f10x.h"

Go to the source code of this file.

Data Structures

struct | SDIO_CmdInitTypeDef
struct | SDIO_DataInitTypeDef
struct | SDIO_InitTypeDef

Defines

#define | IS_SDIO_BLOCK_SIZE(SIZE)
#define | IS_SDIO_BUS_WIDE(WIDE)
#define | IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00))
#define | IS_SDIO_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00))
#define | IS_SDIO_CLOCK_BYPASS(BYPASS)
#define | IS_SDIO_CLOCK_EDGE(EDGE)
#define | IS_SDIO_CLOCK_POWER_SAVE(SAVE)
#define | IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40)
#define | IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_Enable) || ((CPSM) == SDIO_CPSM_Disable))
#define | IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)
#define | IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_Enable) || ((DPSM) == SDIO_DPSM_Disable))
#define | IS_SDIO_FLAG(FLAG)
#define | IS_SDIO_GET_IT(IT)
#define | IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL)
#define | IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00))
#define | IS_SDIO_POWER_STATE(STATE) (((STATE) == SDIO_PowerState_OFF) || ((STATE) == SDIO_PowerState_ON))
#define | IS_SDIO_READWAIT_MODE(MODE)
#define | IS_SDIO_RESP(RESP)
#define | IS_SDIO_RESPONSE(RESPONSE)
#define | IS_SDIO_TRANSFER_DIR(DIR)
#define | IS_SDIO_TRANSFER_MODE(MODE)
#define | IS_SDIO_WAIT(WAIT)
#define | SDIO_BusWide_1b ((uint32_t)0x00000000)
#define | SDIO_BusWide_4b ((uint32_t)0x00000800)
#define | SDIO_BusWide_8b ((uint32_t)0x00001000)
#define | SDIO_ClockBypass_Disable ((uint32_t)0x00000000)
#define | SDIO_ClockBypass_Enable ((uint32_t)0x00000400)
#define | SDIO_ClockEdge_Falling ((uint32_t)0x00002000)
#define | SDIO_ClockEdge_Rising ((uint32_t)0x00000000)
#define | SDIO_ClockPowerSave_Disable ((uint32_t)0x00000000)
#define | SDIO_ClockPowerSave_Enable ((uint32_t)0x00000200)
#define | SDIO_CPSM_Disable ((uint32_t)0x00000000)
#define | SDIO_CPSM_Enable ((uint32_t)0x00000400)
#define | SDIO_DataBlockSize_1024b ((uint32_t)0x000000A0)
#define | SDIO_DataBlockSize_128b ((uint32_t)0x00000070)
#define | SDIO_DataBlockSize_16384b ((uint32_t)0x000000E0)
#define | SDIO_DataBlockSize_16b ((uint32_t)0x00000040)
#define | SDIO_DataBlockSize_1b ((uint32_t)0x00000000)
#define | SDIO_DataBlockSize_2048b ((uint32_t)0x000000B0)
#define | SDIO_DataBlockSize_256b ((uint32_t)0x00000080)
#define | SDIO_DataBlockSize_2b ((uint32_t)0x00000010)
#define | SDIO_DataBlockSize_32b ((uint32_t)0x00000050)
#define | SDIO_DataBlockSize_4096b ((uint32_t)0x000000C0)
#define | SDIO_DataBlockSize_4b ((uint32_t)0x00000020)
#define | SDIO_DataBlockSize_512b ((uint32_t)0x00000090)
#define | SDIO_DataBlockSize_64b ((uint32_t)0x00000060)
#define | SDIO_DataBlockSize_8192b ((uint32_t)0x000000D0)
#define | SDIO_DataBlockSize_8b ((uint32_t)0x00000030)
#define | SDIO_DPSM_Disable ((uint32_t)0x00000000)
#define | SDIO_DPSM_Enable ((uint32_t)0x00000001)
#define | SDIO_FLAG_CCRCFAIL ((uint32_t)0x00000001)
#define | SDIO_FLAG_CEATAEND ((uint32_t)0x00800000)
#define | SDIO_FLAG_CMDACT ((uint32_t)0x00000800)
#define | SDIO_FLAG_CMDREND ((uint32_t)0x00000040)
#define | SDIO_FLAG_CMDSENT ((uint32_t)0x00000080)
#define | SDIO_FLAG_CTIMEOUT ((uint32_t)0x00000004)
#define | SDIO_FLAG_DATAEND ((uint32_t)0x00000100)
#define | SDIO_FLAG_DBCKEND ((uint32_t)0x00000400)
#define | SDIO_FLAG_DCRCFAIL ((uint32_t)0x00000002)
#define | SDIO_FLAG_DTIMEOUT ((uint32_t)0x00000008)
#define | SDIO_FLAG_RXACT ((uint32_t)0x00002000)
#define | SDIO_FLAG_RXDAVL ((uint32_t)0x00200000)
#define | SDIO_FLAG_RXFIFOE ((uint32_t)0x00080000)
#define | SDIO_FLAG_RXFIFOF ((uint32_t)0x00020000)
#define | SDIO_FLAG_RXFIFOHF ((uint32_t)0x00008000)
#define | SDIO_FLAG_RXOVERR ((uint32_t)0x00000020)
#define | SDIO_FLAG_SDIOIT ((uint32_t)0x00400000)
#define | SDIO_FLAG_STBITERR ((uint32_t)0x00000200)
#define | SDIO_FLAG_TXACT ((uint32_t)0x00001000)
#define | SDIO_FLAG_TXDAVL ((uint32_t)0x00100000)
#define | SDIO_FLAG_TXFIFOE ((uint32_t)0x00040000)
#define | SDIO_FLAG_TXFIFOF ((uint32_t)0x00010000)
#define | SDIO_FLAG_TXFIFOHE ((uint32_t)0x00004000)
#define | SDIO_FLAG_TXUNDERR ((uint32_t)0x00000010)
#define | SDIO_HardwareFlowControl_Disable ((uint32_t)0x00000000)
#define | SDIO_HardwareFlowControl_Enable ((uint32_t)0x00004000)
#define | SDIO_IT_CCRCFAIL ((uint32_t)0x00000001)
#define | SDIO_IT_CEATAEND ((uint32_t)0x00800000)
#define | SDIO_IT_CMDACT ((uint32_t)0x00000800)
#define | SDIO_IT_CMDREND ((uint32_t)0x00000040)
#define | SDIO_IT_CMDSENT ((uint32_t)0x00000080)
#define | SDIO_IT_CTIMEOUT ((uint32_t)0x00000004)
#define | SDIO_IT_DATAEND ((uint32_t)0x00000100)
#define | SDIO_IT_DBCKEND ((uint32_t)0x00000400)
#define | SDIO_IT_DCRCFAIL ((uint32_t)0x00000002)
#define | SDIO_IT_DTIMEOUT ((uint32_t)0x00000008)
#define | SDIO_IT_RXACT ((uint32_t)0x00002000)
#define | SDIO_IT_RXDAVL ((uint32_t)0x00200000)
#define | SDIO_IT_RXFIFOE ((uint32_t)0x00080000)
#define | SDIO_IT_RXFIFOF ((uint32_t)0x00020000)
#define | SDIO_IT_RXFIFOHF ((uint32_t)0x00008000)
#define | SDIO_IT_RXOVERR ((uint32_t)0x00000020)
#define | SDIO_IT_SDIOIT ((uint32_t)0x00400000)
#define | SDIO_IT_STBITERR ((uint32_t)0x00000200)
#define | SDIO_IT_TXACT ((uint32_t)0x00001000)
#define | SDIO_IT_TXDAVL ((uint32_t)0x00100000)
#define | SDIO_IT_TXFIFOE ((uint32_t)0x00040000)
#define | SDIO_IT_TXFIFOF ((uint32_t)0x00010000)
#define | SDIO_IT_TXFIFOHE ((uint32_t)0x00004000)
#define | SDIO_IT_TXUNDERR ((uint32_t)0x00000010)
#define | SDIO_PowerState_OFF ((uint32_t)0x00000000)
#define | SDIO_PowerState_ON ((uint32_t)0x00000003)
#define | SDIO_ReadWaitMode_CLK ((uint32_t)0x00000001)
#define | SDIO_ReadWaitMode_DATA2 ((uint32_t)0x00000000)
#define | SDIO_RESP1 ((uint32_t)0x00000000)
#define | SDIO_RESP2 ((uint32_t)0x00000004)
#define | SDIO_RESP3 ((uint32_t)0x00000008)
#define | SDIO_RESP4 ((uint32_t)0x0000000C)
#define | SDIO_Response_Long ((uint32_t)0x000000C0)
#define | SDIO_Response_No ((uint32_t)0x00000000)
#define | SDIO_Response_Short ((uint32_t)0x00000040)
#define | SDIO_TransferDir_ToCard ((uint32_t)0x00000000)
#define | SDIO_TransferDir_ToSDIO ((uint32_t)0x00000002)
#define | SDIO_TransferMode_Block ((uint32_t)0x00000000)
#define | SDIO_TransferMode_Stream ((uint32_t)0x00000004)
#define | SDIO_Wait_IT ((uint32_t)0x00000100)
#define | SDIO_Wait_No ((uint32_t)0x00000000)
#define | SDIO_Wait_Pend ((uint32_t)0x00000200)

Functions

void | SDIO_CEATAITCmd (FunctionalState NewState)
Enables or disables the CE-ATA interrupt.
void | SDIO_ClearFlag (uint32_t SDIO_FLAG)
Clears the SDIO's pending flags.
void | SDIO_ClearITPendingBit (uint32_t SDIO_IT)
Clears the SDIO's interrupt pending bits.
void | SDIO_ClockCmd (FunctionalState NewState)
Enables or disables the SDIO Clock.
void | SDIO_CmdStructInit (SDIO_CmdInitTypeDef *SDIO_CmdInitStruct)
Fills each SDIO_CmdInitStruct member with its default value.
void | SDIO_CommandCompletionCmd (FunctionalState NewState)
Enables or disables the command completion signal.
void | SDIO_DataConfig (SDIO_DataInitTypeDef *SDIO_DataInitStruct)
Initializes the SDIO data path according to the specified parameters in the SDIO_DataInitStruct.
void | SDIO_DataStructInit (SDIO_DataInitTypeDef *SDIO_DataInitStruct)
Fills each SDIO_DataInitStruct member with its default value.
void | SDIO_DeInit (void)
Deinitializes the SDIO peripheral registers to their default reset values.
void | SDIO_DMACmd (FunctionalState NewState)
Enables or disables the SDIO DMA request.
uint8_t | SDIO_GetCommandResponse (void)
Returns command index of last command for which response received.
uint32_t | SDIO_GetDataCounter (void)
Returns number of remaining data bytes to be transferred.
uint32_t | SDIO_GetFIFOCount (void)
Returns the number of words left to be written to or read from FIFO.
FlagStatus | SDIO_GetFlagStatus (uint32_t SDIO_FLAG)
Checks whether the specified SDIO flag is set or not.
ITStatus | SDIO_GetITStatus (uint32_t SDIO_IT)
Checks whether the specified SDIO interrupt has occurred or not.
uint32_t | SDIO_GetPowerState (void)
Gets the power status of the controller.
uint32_t | SDIO_GetResponse (uint32_t SDIO_RESP)
Returns response received from the card for the last command.
void | SDIO_Init (SDIO_InitTypeDef *SDIO_InitStruct)
Initializes the SDIO peripheral according to the specified parameters in the SDIO_InitStruct.
void | SDIO_ITConfig (uint32_t SDIO_IT, FunctionalState NewState)
Enables or disables the SDIO interrupts.
uint32_t | SDIO_ReadData (void)
Read one data word from Rx FIFO.
void | SDIO_SendCEATACmd (FunctionalState NewState)
Sends CE-ATA command (CMD61).
void | SDIO_SendCommand (SDIO_CmdInitTypeDef *SDIO_CmdInitStruct)
Initializes the SDIO Command according to the specified parameters in the SDIO_CmdInitStruct and send the command.
void | SDIO_SendSDIOSuspendCmd (FunctionalState NewState)
Enables or disables the SD I/O Mode suspend command sending.
void | SDIO_SetPowerState (uint32_t SDIO_PowerState)
Sets the power status of the controller.
void | SDIO_SetSDIOOperation (FunctionalState NewState)
Enables or disables the SD I/O Mode Operation.
void | SDIO_SetSDIOReadWaitMode (uint32_t SDIO_ReadWaitMode)
Sets one of the two options of inserting read wait interval.
void | SDIO_StartSDIOReadWait (FunctionalState NewState)
Starts the SD I/O Read Wait operation.
void | SDIO_StopSDIOReadWait (FunctionalState NewState)
Stops the SD I/O Read Wait operation.
void | SDIO_StructInit (SDIO_InitTypeDef *SDIO_InitStruct)
Fills each SDIO_InitStruct member with its default value.
void | SDIO_WriteData (uint32_t Data)
Write one data word to Tx FIFO.

Detailed Description

This file contains all the functions prototypes for the SDIO firmware library.

Author:
MCD Application Team
Version:
V3.5.0
Date:
11-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm32f10x_sdio.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_spi.c File Reference

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Libraries
  • STM32F10x_StdPeriph_Driver
  • src
Defines | Functions

stm32f10x_spi.c File Reference

This file provides all the SPI firmware functions. More...

#include "stm32f10x_spi.h"
#include "stm32f10x_rcc.h"

Go to the source code of this file.

Defines

#define | CR1_CLEAR_Mask ((uint16_t)0x3040)
#define | CR1_CRCEN_Reset ((uint16_t)0xDFFF)
#define | CR1_CRCEN_Set ((uint16_t)0x2000)
#define | CR1_CRCNext_Set ((uint16_t)0x1000)
#define | CR1_SPE_Reset ((uint16_t)0xFFBF)
#define | CR1_SPE_Set ((uint16_t)0x0040)
#define | CR2_SSOE_Reset ((uint16_t)0xFFFB)
#define | CR2_SSOE_Set ((uint16_t)0x0004)
#define | I2S2_CLOCK_SRC ((uint32_t)(0x00020000))
#define | I2S3_CLOCK_SRC ((uint32_t)(0x00040000))
#define | I2S_DIV_MASK ((uint32_t)(0x000000F0))
#define | I2S_Mode_Select ((uint16_t)0x0800)
#define | I2S_MUL_MASK ((uint32_t)(0x0000F000))
#define | I2SCFGR_CLEAR_Mask ((uint16_t)0xF040)
#define | I2SCFGR_I2SE_Reset ((uint16_t)0xFBFF)
#define | I2SCFGR_I2SE_Set ((uint16_t)0x0400)
#define | SPI_Mode_Select ((uint16_t)0xF7FF)

Functions

void | I2S_Cmd (SPI_TypeDef *SPIx, FunctionalState NewState)
Enables or disables the specified SPI peripheral (in I2S mode).
void | I2S_Init (SPI_TypeDef *SPIx, I2S_InitTypeDef *I2S_InitStruct)
Initializes the SPIx peripheral according to the specified parameters in the I2S_InitStruct.
void | I2S_StructInit (I2S_InitTypeDef *I2S_InitStruct)
Fills each I2S_InitStruct member with its default value.
void | SPI_BiDirectionalLineConfig (SPI_TypeDef *SPIx, uint16_t SPI_Direction)
Selects the data transfer direction in bi-directional mode for the specified SPI.
void | SPI_CalculateCRC (SPI_TypeDef *SPIx, FunctionalState NewState)
Enables or disables the CRC value calculation of the transferred bytes.
void | SPI_Cmd (SPI_TypeDef *SPIx, FunctionalState NewState)
Enables or disables the specified SPI peripheral.
void | SPI_DataSizeConfig (SPI_TypeDef *SPIx, uint16_t SPI_DataSize)
Configures the data size for the selected SPI.
uint16_t | SPI_GetCRC (SPI_TypeDef *SPIx, uint8_t SPI_CRC)
Returns the transmit or the receive CRC register value for the specified SPI.
uint16_t | SPI_GetCRCPolynomial (SPI_TypeDef *SPIx)
Returns the CRC Polynomial register value for the specified SPI.
void | SPI_I2S_ClearFlag (SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG)
Clears the SPIx CRC Error (CRCERR) flag.
void | SPI_I2S_ClearITPendingBit (SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT)
Clears the SPIx CRC Error (CRCERR) interrupt pending bit.
void | SPI_I2S_DeInit (SPI_TypeDef *SPIx)
Deinitializes the SPIx peripheral registers to their default reset values (Affects also the I2Ss).
void | SPI_I2S_DMACmd (SPI_TypeDef *SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState)
Enables or disables the SPIx/I2Sx DMA interface.
FlagStatus | SPI_I2S_GetFlagStatus (SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG)
Checks whether the specified SPI/I2S flag is set or not.
ITStatus | SPI_I2S_GetITStatus (SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT)
Checks whether the specified SPI/I2S interrupt has occurred or not.
void | SPI_I2S_ITConfig (SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState)
Enables or disables the specified SPI/I2S interrupts.
uint16_t | SPI_I2S_ReceiveData (SPI_TypeDef *SPIx)
Returns the most recent received data by the SPIx/I2Sx peripheral.
void | SPI_I2S_SendData (SPI_TypeDef *SPIx, uint16_t Data)
Transmits a Data through the SPIx/I2Sx peripheral.
void | SPI_Init (SPI_TypeDef *SPIx, SPI_InitTypeDef *SPI_InitStruct)
Initializes the SPIx peripheral according to the specified parameters in the SPI_InitStruct.
void | SPI_NSSInternalSoftwareConfig (SPI_TypeDef *SPIx, uint16_t SPI_NSSInternalSoft)
Configures internally by software the NSS pin for the selected SPI.
void | SPI_SSOutputCmd (SPI_TypeDef *SPIx, FunctionalState NewState)
Enables or disables the SS output for the selected SPI.
void | SPI_StructInit (SPI_InitTypeDef *SPI_InitStruct)
Fills each SPI_InitStruct member with its default value.
void | SPI_TransmitCRC (SPI_TypeDef *SPIx)
Transmit the SPIx CRC value.

Detailed Description

This file provides all the SPI firmware functions.

Author:
MCD Application Team
Version:
V3.5.0
Date:
11-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm32f10x_spi.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_spi.h File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Libraries
  • STM32F10x_StdPeriph_Driver
  • inc
Data Structures | Defines | Functions

stm32f10x_spi.h File Reference

This file contains all the functions prototypes for the SPI firmware library. More...

#include "stm32f10x.h"

Go to the source code of this file.

Data Structures

struct | I2S_InitTypeDef
I2S Init structure definition. More...
struct | SPI_InitTypeDef
SPI Init structure definition. More...

Defines

#define | I2S_AudioFreq_11k ((uint32_t)11025)
#define | I2S_AudioFreq_16k ((uint32_t)16000)
#define | I2S_AudioFreq_192k ((uint32_t)192000)
#define | I2S_AudioFreq_22k ((uint32_t)22050)
#define | I2S_AudioFreq_32k ((uint32_t)32000)
#define | I2S_AudioFreq_44k ((uint32_t)44100)
#define | I2S_AudioFreq_48k ((uint32_t)48000)
#define | I2S_AudioFreq_8k ((uint32_t)8000)
#define | I2S_AudioFreq_96k ((uint32_t)96000)
#define | I2S_AudioFreq_Default ((uint32_t)2)
#define | I2S_CPOL_High ((uint16_t)0x0008)
#define | I2S_CPOL_Low ((uint16_t)0x0000)
#define | I2S_DataFormat_16b ((uint16_t)0x0000)
#define | I2S_DataFormat_16bextended ((uint16_t)0x0001)
#define | I2S_DataFormat_24b ((uint16_t)0x0003)
#define | I2S_DataFormat_32b ((uint16_t)0x0005)
#define | I2S_FLAG_CHSIDE ((uint16_t)0x0004)
#define | I2S_FLAG_UDR ((uint16_t)0x0008)
#define | I2S_IT_UDR ((uint8_t)0x53)
#define | I2S_MCLKOutput_Disable ((uint16_t)0x0000)
#define | I2S_MCLKOutput_Enable ((uint16_t)0x0200)
#define | I2S_Mode_MasterRx ((uint16_t)0x0300)
#define | I2S_Mode_MasterTx ((uint16_t)0x0200)
#define | I2S_Mode_SlaveRx ((uint16_t)0x0100)
#define | I2S_Mode_SlaveTx ((uint16_t)0x0000)
#define | I2S_Standard_LSB ((uint16_t)0x0020)
#define | I2S_Standard_MSB ((uint16_t)0x0010)
#define | I2S_Standard_PCMLong ((uint16_t)0x00B0)
#define | I2S_Standard_PCMShort ((uint16_t)0x0030)
#define | I2S_Standard_Phillips ((uint16_t)0x0000)
#define | IS_I2S_AUDIO_FREQ(FREQ)
#define | IS_I2S_CPOL(CPOL)
#define | IS_I2S_DATA_FORMAT(FORMAT)
#define | IS_I2S_MCLK_OUTPUT(OUTPUT)
#define | IS_I2S_MODE(MODE)
#define | IS_I2S_STANDARD(STANDARD)
#define | IS_SPI_23_PERIPH(PERIPH)
#define | IS_SPI_ALL_PERIPH(PERIPH)
#define | IS_SPI_BAUDRATE_PRESCALER(PRESCALER)
#define | IS_SPI_CPHA(CPHA)
#define | IS_SPI_CPOL(CPOL)
#define | IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx))
#define | IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1)
#define | IS_SPI_DATASIZE(DATASIZE)
#define | IS_SPI_DIRECTION(DIRECTION)
#define | IS_SPI_DIRECTION_MODE(MODE)
#define | IS_SPI_FIRST_BIT(BIT)
#define | IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR))
#define | IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR))
#define | IS_SPI_I2S_CONFIG_IT(IT)
#define | IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00))
#define | IS_SPI_I2S_GET_FLAG(FLAG)
#define | IS_SPI_I2S_GET_IT(IT)
#define | IS_SPI_MODE(MODE)
#define | IS_SPI_NSS(NSS)
#define | IS_SPI_NSS_INTERNAL(INTERNAL)
#define | SPI_BaudRatePrescaler_128 ((uint16_t)0x0030)
#define | SPI_BaudRatePrescaler_16 ((uint16_t)0x0018)
#define | SPI_BaudRatePrescaler_2 ((uint16_t)0x0000)
#define | SPI_BaudRatePrescaler_256 ((uint16_t)0x0038)
#define | SPI_BaudRatePrescaler_32 ((uint16_t)0x0020)
#define | SPI_BaudRatePrescaler_4 ((uint16_t)0x0008)
#define | SPI_BaudRatePrescaler_64 ((uint16_t)0x0028)
#define | SPI_BaudRatePrescaler_8 ((uint16_t)0x0010)
#define | SPI_CPHA_1Edge ((uint16_t)0x0000)
#define | SPI_CPHA_2Edge ((uint16_t)0x0001)
#define | SPI_CPOL_High ((uint16_t)0x0002)
#define | SPI_CPOL_Low ((uint16_t)0x0000)
#define | SPI_CRC_Rx ((uint8_t)0x01)
#define | SPI_CRC_Tx ((uint8_t)0x00)
#define | SPI_DataSize_16b ((uint16_t)0x0800)
#define | SPI_DataSize_8b ((uint16_t)0x0000)
#define | SPI_Direction_1Line_Rx ((uint16_t)0x8000)
#define | SPI_Direction_1Line_Tx ((uint16_t)0xC000)
#define | SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)
#define | SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400)
#define | SPI_Direction_Rx ((uint16_t)0xBFFF)
#define | SPI_Direction_Tx ((uint16_t)0x4000)
#define | SPI_FirstBit_LSB ((uint16_t)0x0080)
#define | SPI_FirstBit_MSB ((uint16_t)0x0000)
#define | SPI_FLAG_CRCERR ((uint16_t)0x0010)
#define | SPI_FLAG_MODF ((uint16_t)0x0020)
#define | SPI_I2S_DMAReq_Rx ((uint16_t)0x0001)
#define | SPI_I2S_DMAReq_Tx ((uint16_t)0x0002)
#define | SPI_I2S_FLAG_BSY ((uint16_t)0x0080)
#define | SPI_I2S_FLAG_OVR ((uint16_t)0x0040)
#define | SPI_I2S_FLAG_RXNE ((uint16_t)0x0001)
#define | SPI_I2S_FLAG_TXE ((uint16_t)0x0002)
#define | SPI_I2S_IT_ERR ((uint8_t)0x50)
#define | SPI_I2S_IT_OVR ((uint8_t)0x56)
#define | SPI_I2S_IT_RXNE ((uint8_t)0x60)
#define | SPI_I2S_IT_TXE ((uint8_t)0x71)
#define | SPI_IT_CRCERR ((uint8_t)0x54)
#define | SPI_IT_MODF ((uint8_t)0x55)
#define | SPI_Mode_Master ((uint16_t)0x0104)
#define | SPI_Mode_Slave ((uint16_t)0x0000)
#define | SPI_NSS_Hard ((uint16_t)0x0000)
#define | SPI_NSS_Soft ((uint16_t)0x0200)
#define | SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF)
#define | SPI_NSSInternalSoft_Set ((uint16_t)0x0100)

Functions

void | I2S_Cmd (SPI_TypeDef *SPIx, FunctionalState NewState)
Enables or disables the specified SPI peripheral (in I2S mode).
void | I2S_Init (SPI_TypeDef *SPIx, I2S_InitTypeDef *I2S_InitStruct)
Initializes the SPIx peripheral according to the specified parameters in the I2S_InitStruct.
void | I2S_StructInit (I2S_InitTypeDef *I2S_InitStruct)
Fills each I2S_InitStruct member with its default value.
void | SPI_BiDirectionalLineConfig (SPI_TypeDef *SPIx, uint16_t SPI_Direction)
Selects the data transfer direction in bi-directional mode for the specified SPI.
void | SPI_CalculateCRC (SPI_TypeDef *SPIx, FunctionalState NewState)
Enables or disables the CRC value calculation of the transferred bytes.
void | SPI_Cmd (SPI_TypeDef *SPIx, FunctionalState NewState)
Enables or disables the specified SPI peripheral.
void | SPI_DataSizeConfig (SPI_TypeDef *SPIx, uint16_t SPI_DataSize)
Configures the data size for the selected SPI.
uint16_t | SPI_GetCRC (SPI_TypeDef *SPIx, uint8_t SPI_CRC)
Returns the transmit or the receive CRC register value for the specified SPI.
uint16_t | SPI_GetCRCPolynomial (SPI_TypeDef *SPIx)
Returns the CRC Polynomial register value for the specified SPI.
void | SPI_I2S_ClearFlag (SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG)
Clears the SPIx CRC Error (CRCERR) flag.
void | SPI_I2S_ClearITPendingBit (SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT)
Clears the SPIx CRC Error (CRCERR) interrupt pending bit.
void | SPI_I2S_DeInit (SPI_TypeDef *SPIx)
Deinitializes the SPIx peripheral registers to their default reset values (Affects also the I2Ss).
void | SPI_I2S_DMACmd (SPI_TypeDef *SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState)
Enables or disables the SPIx/I2Sx DMA interface.
FlagStatus | SPI_I2S_GetFlagStatus (SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG)
Checks whether the specified SPI/I2S flag is set or not.
ITStatus | SPI_I2S_GetITStatus (SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT)
Checks whether the specified SPI/I2S interrupt has occurred or not.
void | SPI_I2S_ITConfig (SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState)
Enables or disables the specified SPI/I2S interrupts.
uint16_t | SPI_I2S_ReceiveData (SPI_TypeDef *SPIx)
Returns the most recent received data by the SPIx/I2Sx peripheral.
void | SPI_I2S_SendData (SPI_TypeDef *SPIx, uint16_t Data)
Transmits a Data through the SPIx/I2Sx peripheral.
void | SPI_Init (SPI_TypeDef *SPIx, SPI_InitTypeDef *SPI_InitStruct)
Initializes the SPIx peripheral according to the specified parameters in the SPI_InitStruct.
void | SPI_NSSInternalSoftwareConfig (SPI_TypeDef *SPIx, uint16_t SPI_NSSInternalSoft)
Configures internally by software the NSS pin for the selected SPI.
void | SPI_SSOutputCmd (SPI_TypeDef *SPIx, FunctionalState NewState)
Enables or disables the SS output for the selected SPI.
void | SPI_StructInit (SPI_InitTypeDef *SPI_InitStruct)
Fills each SPI_InitStruct member with its default value.
void | SPI_TransmitCRC (SPI_TypeDef *SPIx)
Transmit the SPIx CRC value.

Detailed Description

This file contains all the functions prototypes for the SPI firmware library.

Author:
MCD Application Team
Version:
V3.5.0
Date:
11-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm32f10x_spi.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_tim.c File Reference

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  • STM32F10x_StdPeriph_Lib_V3.5.0
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Defines | Functions

stm32f10x_tim.c File Reference

This file provides all the TIM firmware functions. More...

#include "stm32f10x_tim.h"
#include "stm32f10x_rcc.h"

Go to the source code of this file.

Defines

#define | CCER_CCE_Set ((uint16_t)0x0001)
#define | CCER_CCNE_Set ((uint16_t)0x0004)
#define | CCMR_Offset ((uint16_t)0x0018)
#define | SMCR_ETR_Mask ((uint16_t)0x00FF)

Functions

static void | TI1_Config (TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, uint16_t TIM_ICFilter)
Configure the TI1 as Input.
static void | TI2_Config (TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, uint16_t TIM_ICFilter)
Configure the TI2 as Input.
static void | TI3_Config (TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, uint16_t TIM_ICFilter)
Configure the TI3 as Input.
static void | TI4_Config (TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, uint16_t TIM_ICFilter)
Configure the TI4 as Input.
void | TIM_ARRPreloadConfig (TIM_TypeDef *TIMx, FunctionalState NewState)
Enables or disables TIMx peripheral Preload register on ARR.
void | TIM_BDTRConfig (TIM_TypeDef *TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)
Configures the: Break feature, dead time, Lock level, the OSSI, the OSSR State and the AOE(automatic output enable).
void | TIM_BDTRStructInit (TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)
Fills each TIM_BDTRInitStruct member with its default value.
void | TIM_CCPreloadControl (TIM_TypeDef *TIMx, FunctionalState NewState)
Sets or Resets the TIM peripheral Capture Compare Preload Control bit.
void | TIM_CCxCmd (TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx)
Enables or disables the TIM Capture Compare Channel x.
void | TIM_CCxNCmd (TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN)
Enables or disables the TIM Capture Compare Channel xN.
void | TIM_ClearFlag (TIM_TypeDef *TIMx, uint16_t TIM_FLAG)
Clears the TIMx's pending flags.
void | TIM_ClearITPendingBit (TIM_TypeDef *TIMx, uint16_t TIM_IT)
Clears the TIMx's interrupt pending bits.
void | TIM_ClearOC1Ref (TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
Clears or safeguards the OCREF1 signal on an external event.
void | TIM_ClearOC2Ref (TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
Clears or safeguards the OCREF2 signal on an external event.
void | TIM_ClearOC3Ref (TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
Clears or safeguards the OCREF3 signal on an external event.
void | TIM_ClearOC4Ref (TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
Clears or safeguards the OCREF4 signal on an external event.
void | TIM_Cmd (TIM_TypeDef *TIMx, FunctionalState NewState)
Enables or disables the specified TIM peripheral.
void | TIM_CounterModeConfig (TIM_TypeDef *TIMx, uint16_t TIM_CounterMode)
Specifies the TIMx Counter Mode to be used.
void | TIM_CtrlPWMOutputs (TIM_TypeDef *TIMx, FunctionalState NewState)
Enables or disables the TIM peripheral Main Outputs.
void | TIM_DeInit (TIM_TypeDef *TIMx)
Deinitializes the TIMx peripheral registers to their default reset values.
void | TIM_DMACmd (TIM_TypeDef *TIMx, uint16_t TIM_DMASource, FunctionalState NewState)
Enables or disables the TIMx's DMA Requests.
void | TIM_DMAConfig (TIM_TypeDef *TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)
Configures the TIMx's DMA interface.
void | TIM_EncoderInterfaceConfig (TIM_TypeDef *TIMx, uint16_t TIM_EncoderMode, uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity)
Configures the TIMx Encoder Interface.
void | TIM_ETRClockMode1Config (TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
Configures the External clock Mode1.
void | TIM_ETRClockMode2Config (TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
Configures the External clock Mode2.
void | TIM_ETRConfig (TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
Configures the TIMx External Trigger (ETR).
void | TIM_ForcedOC1Config (TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
Forces the TIMx output 1 waveform to active or inactive level.
void | TIM_ForcedOC2Config (TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
Forces the TIMx output 2 waveform to active or inactive level.
void | TIM_ForcedOC3Config (TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
Forces the TIMx output 3 waveform to active or inactive level.
void | TIM_ForcedOC4Config (TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
Forces the TIMx output 4 waveform to active or inactive level.
void | TIM_GenerateEvent (TIM_TypeDef *TIMx, uint16_t TIM_EventSource)
Configures the TIMx event to be generate by software.
uint16_t | TIM_GetCapture1 (TIM_TypeDef *TIMx)
Gets the TIMx Input Capture 1 value.
uint16_t | TIM_GetCapture2 (TIM_TypeDef *TIMx)
Gets the TIMx Input Capture 2 value.
uint16_t | TIM_GetCapture3 (TIM_TypeDef *TIMx)
Gets the TIMx Input Capture 3 value.
uint16_t | TIM_GetCapture4 (TIM_TypeDef *TIMx)
Gets the TIMx Input Capture 4 value.
uint16_t | TIM_GetCounter (TIM_TypeDef *TIMx)
Gets the TIMx Counter value.
FlagStatus | TIM_GetFlagStatus (TIM_TypeDef *TIMx, uint16_t TIM_FLAG)
Checks whether the specified TIM flag is set or not.
ITStatus | TIM_GetITStatus (TIM_TypeDef *TIMx, uint16_t TIM_IT)
Checks whether the TIM interrupt has occurred or not.
uint16_t | TIM_GetPrescaler (TIM_TypeDef *TIMx)
Gets the TIMx Prescaler value.
void | TIM_ICInit (TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct)
Initializes the TIM peripheral according to the specified parameters in the TIM_ICInitStruct.
void | TIM_ICStructInit (TIM_ICInitTypeDef *TIM_ICInitStruct)
Fills each TIM_ICInitStruct member with its default value.
void | TIM_InternalClockConfig (TIM_TypeDef *TIMx)
Configures the TIMx internal Clock.
void | TIM_ITConfig (TIM_TypeDef *TIMx, uint16_t TIM_IT, FunctionalState NewState)
Enables or disables the specified TIM interrupts.
void | TIM_ITRxExternalClockConfig (TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource)
Configures the TIMx Internal Trigger as External Clock.
void | TIM_OC1FastConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
Configures the TIMx Output Compare 1 Fast feature.
void | TIM_OC1Init (TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
Initializes the TIMx Channel1 according to the specified parameters in the TIM_OCInitStruct.
void | TIM_OC1NPolarityConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity)
Configures the TIMx Channel 1N polarity.
void | TIM_OC1PolarityConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
Configures the TIMx channel 1 polarity.
void | TIM_OC1PreloadConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
Enables or disables the TIMx peripheral Preload register on CCR1.
void | TIM_OC2FastConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
Configures the TIMx Output Compare 2 Fast feature.
void | TIM_OC2Init (TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
Initializes the TIMx Channel2 according to the specified parameters in the TIM_OCInitStruct.
void | TIM_OC2NPolarityConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity)
Configures the TIMx Channel 2N polarity.
void | TIM_OC2PolarityConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
Configures the TIMx channel 2 polarity.
void | TIM_OC2PreloadConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
Enables or disables the TIMx peripheral Preload register on CCR2.
void | TIM_OC3FastConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
Configures the TIMx Output Compare 3 Fast feature.
void | TIM_OC3Init (TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
Initializes the TIMx Channel3 according to the specified parameters in the TIM_OCInitStruct.
void | TIM_OC3NPolarityConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity)
Configures the TIMx Channel 3N polarity.
void | TIM_OC3PolarityConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
Configures the TIMx channel 3 polarity.
void | TIM_OC3PreloadConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
Enables or disables the TIMx peripheral Preload register on CCR3.
void | TIM_OC4FastConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
Configures the TIMx Output Compare 4 Fast feature.
void | TIM_OC4Init (TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
Initializes the TIMx Channel4 according to the specified parameters in the TIM_OCInitStruct.
void | TIM_OC4PolarityConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
Configures the TIMx channel 4 polarity.
void | TIM_OC4PreloadConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
Enables or disables the TIMx peripheral Preload register on CCR4.
void | TIM_OCStructInit (TIM_OCInitTypeDef *TIM_OCInitStruct)
Fills each TIM_OCInitStruct member with its default value.
void | TIM_PrescalerConfig (TIM_TypeDef *TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)
Configures the TIMx Prescaler.
void | TIM_PWMIConfig (TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct)
Configures the TIM peripheral according to the specified parameters in the TIM_ICInitStruct to measure an external PWM signal.
void | TIM_SelectCCDMA (TIM_TypeDef *TIMx, FunctionalState NewState)
Selects the TIMx peripheral Capture Compare DMA source.
void | TIM_SelectCOM (TIM_TypeDef *TIMx, FunctionalState NewState)
Selects the TIM peripheral Commutation event.
void | TIM_SelectHallSensor (TIM_TypeDef *TIMx, FunctionalState NewState)
Enables or disables the TIMx's Hall sensor interface.
void | TIM_SelectInputTrigger (TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource)
Selects the Input Trigger source.
void | TIM_SelectMasterSlaveMode (TIM_TypeDef *TIMx, uint16_t TIM_MasterSlaveMode)
Sets or Resets the TIMx Master/Slave Mode.
void | TIM_SelectOCxM (TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode)
Selects the TIM Output Compare Mode.
void | TIM_SelectOnePulseMode (TIM_TypeDef *TIMx, uint16_t TIM_OPMode)
Selects the TIMx's One Pulse Mode.
void | TIM_SelectOutputTrigger (TIM_TypeDef *TIMx, uint16_t TIM_TRGOSource)
Selects the TIMx Trigger Output Mode.
void | TIM_SelectSlaveMode (TIM_TypeDef *TIMx, uint16_t TIM_SlaveMode)
Selects the TIMx Slave Mode.
void | TIM_SetAutoreload (TIM_TypeDef *TIMx, uint16_t Autoreload)
Sets the TIMx Autoreload Register value.
void | TIM_SetClockDivision (TIM_TypeDef *TIMx, uint16_t TIM_CKD)
Sets the TIMx Clock Division value.
void | TIM_SetCompare1 (TIM_TypeDef *TIMx, uint16_t Compare1)
Sets the TIMx Capture Compare1 Register value.
void | TIM_SetCompare2 (TIM_TypeDef *TIMx, uint16_t Compare2)
Sets the TIMx Capture Compare2 Register value.
void | TIM_SetCompare3 (TIM_TypeDef *TIMx, uint16_t Compare3)
Sets the TIMx Capture Compare3 Register value.
void | TIM_SetCompare4 (TIM_TypeDef *TIMx, uint16_t Compare4)
Sets the TIMx Capture Compare4 Register value.
void | TIM_SetCounter (TIM_TypeDef *TIMx, uint16_t Counter)
Sets the TIMx Counter Register value.
void | TIM_SetIC1Prescaler (TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
Sets the TIMx Input Capture 1 prescaler.
void | TIM_SetIC2Prescaler (TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
Sets the TIMx Input Capture 2 prescaler.
void | TIM_SetIC3Prescaler (TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
Sets the TIMx Input Capture 3 prescaler.
void | TIM_SetIC4Prescaler (TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
Sets the TIMx Input Capture 4 prescaler.
void | TIM_TimeBaseInit (TIM_TypeDef *TIMx, TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct)
Initializes the TIMx Time Base Unit peripheral according to the specified parameters in the TIM_TimeBaseInitStruct.
void | TIM_TimeBaseStructInit (TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct)
Fills each TIM_TimeBaseInitStruct member with its default value.
void | TIM_TIxExternalClockConfig (TIM_TypeDef *TIMx, uint16_t TIM_TIxExternalCLKSource, uint16_t TIM_ICPolarity, uint16_t ICFilter)
Configures the TIMx Trigger as External Clock.
void | TIM_UpdateDisableConfig (TIM_TypeDef *TIMx, FunctionalState NewState)
Enables or Disables the TIMx Update event.
void | TIM_UpdateRequestConfig (TIM_TypeDef *TIMx, uint16_t TIM_UpdateSource)
Configures the TIMx Update Request Interrupt source.

Detailed Description

This file provides all the TIM firmware functions.

Author:
MCD Application Team
Version:
V3.5.0
Date:
11-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm32f10x_tim.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_tim.h File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Libraries
  • STM32F10x_StdPeriph_Driver
  • inc
Data Structures | Defines | Functions

stm32f10x_tim.h File Reference

This file contains all the functions prototypes for the TIM firmware library. More...

#include "stm32f10x.h"

Go to the source code of this file.

Data Structures

struct | TIM_BDTRInitTypeDef
BDTR structure definition. More...
struct | TIM_ICInitTypeDef
TIM Input Capture Init structure definition. More...
struct | TIM_OCInitTypeDef
TIM Output Compare Init structure definition. More...
struct | TIM_TimeBaseInitTypeDef
TIM Time Base Init structure definition. More...

Defines

#define | IS_TIM_ALL_PERIPH(PERIPH)
#define | IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE)
#define | IS_TIM_BREAK_POLARITY(POLARITY)
#define | IS_TIM_BREAK_STATE(STATE)
#define | IS_TIM_CCX(CCX)
#define | IS_TIM_CCXN(CCXN)
#define | IS_TIM_CHANNEL(CHANNEL)
#define | IS_TIM_CKD_DIV(DIV)
#define | IS_TIM_CLEAR_FLAG(TIM_FLAG) ((((TIM_FLAG) & (uint16_t)0xE100) == 0x0000) && ((TIM_FLAG) != 0x0000))
#define | IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL)
#define | IS_TIM_COUNTER_MODE(MODE)
#define | IS_TIM_DMA_BASE(BASE)
#define | IS_TIM_DMA_LENGTH(LENGTH)
#define | IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000))
#define | IS_TIM_ENCODER_MODE(MODE)
#define | IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000))
#define | IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF)
#define | IS_TIM_EXT_POLARITY(POLARITY)
#define | IS_TIM_EXT_PRESCALER(PRESCALER)
#define | IS_TIM_FORCED_ACTION(ACTION)
#define | IS_TIM_GET_FLAG(FLAG)
#define | IS_TIM_GET_IT(IT)
#define | IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
#define | IS_TIM_IC_POLARITY(POLARITY)
#define | IS_TIM_IC_POLARITY_LITE(POLARITY)
#define | IS_TIM_IC_PRESCALER(PRESCALER)
#define | IS_TIM_IC_SELECTION(SELECTION)
#define | IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION)
#define | IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000))
#define | IS_TIM_LIST1_PERIPH(PERIPH)
#define | IS_TIM_LIST2_PERIPH(PERIPH)
#define | IS_TIM_LIST3_PERIPH(PERIPH)
#define | IS_TIM_LIST4_PERIPH(PERIPH)
#define | IS_TIM_LIST5_PERIPH(PERIPH)
#define | IS_TIM_LIST6_PERIPH(PERIPH)
#define | IS_TIM_LIST7_PERIPH(PERIPH)
#define | IS_TIM_LIST8_PERIPH(PERIPH)
#define | IS_TIM_LIST9_PERIPH(PERIPH)
#define | IS_TIM_LOCK_LEVEL(LEVEL)
#define | IS_TIM_MSM_STATE(STATE)
#define | IS_TIM_OC_MODE(MODE)
#define | IS_TIM_OC_POLARITY(POLARITY)
#define | IS_TIM_OCCLEAR_STATE(STATE)
#define | IS_TIM_OCFAST_STATE(STATE)
#define | IS_TIM_OCIDLE_STATE(STATE)
#define | IS_TIM_OCM(MODE)
#define | IS_TIM_OCN_POLARITY(POLARITY)
#define | IS_TIM_OCNIDLE_STATE(STATE)
#define | IS_TIM_OCPRELOAD_STATE(STATE)
#define | IS_TIM_OPM_MODE(MODE)
#define | IS_TIM_OSSI_STATE(STATE)
#define | IS_TIM_OSSR_STATE(STATE)
#define | IS_TIM_OUTPUT_STATE(STATE)
#define | IS_TIM_OUTPUTN_STATE(STATE)
#define | IS_TIM_PRESCALER_RELOAD(RELOAD)
#define | IS_TIM_PWMI_CHANNEL(CHANNEL)
#define | IS_TIM_SLAVE_MODE(MODE)
#define | IS_TIM_TIXCLK_SOURCE(SOURCE)
#define | IS_TIM_TRGO_SOURCE(SOURCE)
#define | IS_TIM_TRIGGER_SELECTION(SELECTION)
#define | IS_TIM_UPDATE_SOURCE(SOURCE)
#define | TIM_AutomaticOutput_Disable ((uint16_t)0x0000)
#define | TIM_AutomaticOutput_Enable ((uint16_t)0x4000)
#define | TIM_Break_Disable ((uint16_t)0x0000)
#define | TIM_Break_Enable ((uint16_t)0x1000)
#define | TIM_BreakPolarity_High ((uint16_t)0x2000)
#define | TIM_BreakPolarity_Low ((uint16_t)0x0000)
#define | TIM_CCx_Disable ((uint16_t)0x0000)
#define | TIM_CCx_Enable ((uint16_t)0x0001)
#define | TIM_CCxN_Disable ((uint16_t)0x0000)
#define | TIM_CCxN_Enable ((uint16_t)0x0004)
#define | TIM_Channel_1 ((uint16_t)0x0000)
#define | TIM_Channel_2 ((uint16_t)0x0004)
#define | TIM_Channel_3 ((uint16_t)0x0008)
#define | TIM_Channel_4 ((uint16_t)0x000C)
#define | TIM_CKD_DIV1 ((uint16_t)0x0000)
#define | TIM_CKD_DIV2 ((uint16_t)0x0100)
#define | TIM_CKD_DIV4 ((uint16_t)0x0200)
#define | TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020)
#define | TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040)
#define | TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060)
#define | TIM_CounterMode_Down ((uint16_t)0x0010)
#define | TIM_CounterMode_Up ((uint16_t)0x0000)
#define | TIM_DMA_CC1 ((uint16_t)0x0200)
#define | TIM_DMA_CC2 ((uint16_t)0x0400)
#define | TIM_DMA_CC3 ((uint16_t)0x0800)
#define | TIM_DMA_CC4 ((uint16_t)0x1000)
#define | TIM_DMA_COM ((uint16_t)0x2000)
#define | TIM_DMA_Trigger ((uint16_t)0x4000)
#define | TIM_DMA_Update ((uint16_t)0x0100)
#define | TIM_DMABase_ARR ((uint16_t)0x000B)
#define | TIM_DMABase_BDTR ((uint16_t)0x0011)
#define | TIM_DMABase_CCER ((uint16_t)0x0008)
#define | TIM_DMABase_CCMR1 ((uint16_t)0x0006)
#define | TIM_DMABase_CCMR2 ((uint16_t)0x0007)
#define | TIM_DMABase_CCR1 ((uint16_t)0x000D)
#define | TIM_DMABase_CCR2 ((uint16_t)0x000E)
#define | TIM_DMABase_CCR3 ((uint16_t)0x000F)
#define | TIM_DMABase_CCR4 ((uint16_t)0x0010)
#define | TIM_DMABase_CNT ((uint16_t)0x0009)
#define | TIM_DMABase_CR1 ((uint16_t)0x0000)
#define | TIM_DMABase_CR2 ((uint16_t)0x0001)
#define | TIM_DMABase_DCR ((uint16_t)0x0012)
#define | TIM_DMABase_DIER ((uint16_t)0x0003)
#define | TIM_DMABase_EGR ((uint16_t)0x0005)
#define | TIM_DMABase_PSC ((uint16_t)0x000A)
#define | TIM_DMABase_RCR ((uint16_t)0x000C)
#define | TIM_DMABase_SMCR ((uint16_t)0x0002)
#define | TIM_DMABase_SR ((uint16_t)0x0004)
#define | TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers
#define | TIM_DMABurstLength_10Transfers ((uint16_t)0x0900)
#define | TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers
#define | TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00)
#define | TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers
#define | TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00)
#define | TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers
#define | TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00)
#define | TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers
#define | TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00)
#define | TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers
#define | TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00)
#define | TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers
#define | TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00)
#define | TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers
#define | TIM_DMABurstLength_17Transfers ((uint16_t)0x1000)
#define | TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers
#define | TIM_DMABurstLength_18Transfers ((uint16_t)0x1100)
#define | TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer
#define | TIM_DMABurstLength_1Transfer ((uint16_t)0x0000)
#define | TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers
#define | TIM_DMABurstLength_2Transfers ((uint16_t)0x0100)
#define | TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers
#define | TIM_DMABurstLength_3Transfers ((uint16_t)0x0200)
#define | TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers
#define | TIM_DMABurstLength_4Transfers ((uint16_t)0x0300)
#define | TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers
#define | TIM_DMABurstLength_5Transfers ((uint16_t)0x0400)
#define | TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers
#define | TIM_DMABurstLength_6Transfers ((uint16_t)0x0500)
#define | TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers
#define | TIM_DMABurstLength_7Transfers ((uint16_t)0x0600)
#define | TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers
#define | TIM_DMABurstLength_8Transfers ((uint16_t)0x0700)
#define | TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers
#define | TIM_DMABurstLength_9Transfers ((uint16_t)0x0800)
#define | TIM_EncoderMode_TI1 ((uint16_t)0x0001)
#define | TIM_EncoderMode_TI12 ((uint16_t)0x0003)
#define | TIM_EncoderMode_TI2 ((uint16_t)0x0002)
#define | TIM_EventSource_Break ((uint16_t)0x0080)
#define | TIM_EventSource_CC1 ((uint16_t)0x0002)
#define | TIM_EventSource_CC2 ((uint16_t)0x0004)
#define | TIM_EventSource_CC3 ((uint16_t)0x0008)
#define | TIM_EventSource_CC4 ((uint16_t)0x0010)
#define | TIM_EventSource_COM ((uint16_t)0x0020)
#define | TIM_EventSource_Trigger ((uint16_t)0x0040)
#define | TIM_EventSource_Update ((uint16_t)0x0001)
#define | TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000)
#define | TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000)
#define | TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000)
#define | TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000)
#define | TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000)
#define | TIM_ExtTRGPSC_OFF ((uint16_t)0x0000)
#define | TIM_FLAG_Break ((uint16_t)0x0080)
#define | TIM_FLAG_CC1 ((uint16_t)0x0002)
#define | TIM_FLAG_CC1OF ((uint16_t)0x0200)
#define | TIM_FLAG_CC2 ((uint16_t)0x0004)
#define | TIM_FLAG_CC2OF ((uint16_t)0x0400)
#define | TIM_FLAG_CC3 ((uint16_t)0x0008)
#define | TIM_FLAG_CC3OF ((uint16_t)0x0800)
#define | TIM_FLAG_CC4 ((uint16_t)0x0010)
#define | TIM_FLAG_CC4OF ((uint16_t)0x1000)
#define | TIM_FLAG_COM ((uint16_t)0x0020)
#define | TIM_FLAG_Trigger ((uint16_t)0x0040)
#define | TIM_FLAG_Update ((uint16_t)0x0001)
#define | TIM_ForcedAction_Active ((uint16_t)0x0050)
#define | TIM_ForcedAction_InActive ((uint16_t)0x0040)
#define | TIM_ICPolarity_BothEdge ((uint16_t)0x000A)
#define | TIM_ICPolarity_Falling ((uint16_t)0x0002)
#define | TIM_ICPolarity_Rising ((uint16_t)0x0000)
#define | TIM_ICPSC_DIV1 ((uint16_t)0x0000)
#define | TIM_ICPSC_DIV2 ((uint16_t)0x0004)
#define | TIM_ICPSC_DIV4 ((uint16_t)0x0008)
#define | TIM_ICPSC_DIV8 ((uint16_t)0x000C)
#define | TIM_ICSelection_DirectTI ((uint16_t)0x0001)
#define | TIM_ICSelection_IndirectTI ((uint16_t)0x0002)
#define | TIM_ICSelection_TRC ((uint16_t)0x0003)
#define | TIM_IT_Break ((uint16_t)0x0080)
#define | TIM_IT_CC1 ((uint16_t)0x0002)
#define | TIM_IT_CC2 ((uint16_t)0x0004)
#define | TIM_IT_CC3 ((uint16_t)0x0008)
#define | TIM_IT_CC4 ((uint16_t)0x0010)
#define | TIM_IT_COM ((uint16_t)0x0020)
#define | TIM_IT_Trigger ((uint16_t)0x0040)
#define | TIM_IT_Update ((uint16_t)0x0001)
#define | TIM_LOCKLevel_1 ((uint16_t)0x0100)
#define | TIM_LOCKLevel_2 ((uint16_t)0x0200)
#define | TIM_LOCKLevel_3 ((uint16_t)0x0300)
#define | TIM_LOCKLevel_OFF ((uint16_t)0x0000)
#define | TIM_MasterSlaveMode_Disable ((uint16_t)0x0000)
#define | TIM_MasterSlaveMode_Enable ((uint16_t)0x0080)
#define | TIM_OCClear_Disable ((uint16_t)0x0000)
#define | TIM_OCClear_Enable ((uint16_t)0x0080)
#define | TIM_OCFast_Disable ((uint16_t)0x0000)
#define | TIM_OCFast_Enable ((uint16_t)0x0004)
#define | TIM_OCIdleState_Reset ((uint16_t)0x0000)
#define | TIM_OCIdleState_Set ((uint16_t)0x0100)
#define | TIM_OCMode_Active ((uint16_t)0x0010)
#define | TIM_OCMode_Inactive ((uint16_t)0x0020)
#define | TIM_OCMode_PWM1 ((uint16_t)0x0060)
#define | TIM_OCMode_PWM2 ((uint16_t)0x0070)
#define | TIM_OCMode_Timing ((uint16_t)0x0000)
#define | TIM_OCMode_Toggle ((uint16_t)0x0030)
#define | TIM_OCNIdleState_Reset ((uint16_t)0x0000)
#define | TIM_OCNIdleState_Set ((uint16_t)0x0200)
#define | TIM_OCNPolarity_High ((uint16_t)0x0000)
#define | TIM_OCNPolarity_Low ((uint16_t)0x0008)
#define | TIM_OCPolarity_High ((uint16_t)0x0000)
#define | TIM_OCPolarity_Low ((uint16_t)0x0002)
#define | TIM_OCPreload_Disable ((uint16_t)0x0000)
#define | TIM_OCPreload_Enable ((uint16_t)0x0008)
#define | TIM_OPMode_Repetitive ((uint16_t)0x0000)
#define | TIM_OPMode_Single ((uint16_t)0x0008)
#define | TIM_OSSIState_Disable ((uint16_t)0x0000)
#define | TIM_OSSIState_Enable ((uint16_t)0x0400)
#define | TIM_OSSRState_Disable ((uint16_t)0x0000)
#define | TIM_OSSRState_Enable ((uint16_t)0x0800)
#define | TIM_OutputNState_Disable ((uint16_t)0x0000)
#define | TIM_OutputNState_Enable ((uint16_t)0x0004)
#define | TIM_OutputState_Disable ((uint16_t)0x0000)
#define | TIM_OutputState_Enable ((uint16_t)0x0001)
#define | TIM_PSCReloadMode_Immediate ((uint16_t)0x0001)
#define | TIM_PSCReloadMode_Update ((uint16_t)0x0000)
#define | TIM_SlaveMode_External1 ((uint16_t)0x0007)
#define | TIM_SlaveMode_Gated ((uint16_t)0x0005)
#define | TIM_SlaveMode_Reset ((uint16_t)0x0004)
#define | TIM_SlaveMode_Trigger ((uint16_t)0x0006)
#define | TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050)
#define | TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040)
#define | TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060)
#define | TIM_TRGOSource_Enable ((uint16_t)0x0010)
#define | TIM_TRGOSource_OC1 ((uint16_t)0x0030)
#define | TIM_TRGOSource_OC1Ref ((uint16_t)0x0040)
#define | TIM_TRGOSource_OC2Ref ((uint16_t)0x0050)
#define | TIM_TRGOSource_OC3Ref ((uint16_t)0x0060)
#define | TIM_TRGOSource_OC4Ref ((uint16_t)0x0070)
#define | TIM_TRGOSource_Reset ((uint16_t)0x0000)
#define | TIM_TRGOSource_Update ((uint16_t)0x0020)
#define | TIM_TS_ETRF ((uint16_t)0x0070)
#define | TIM_TS_ITR0 ((uint16_t)0x0000)
#define | TIM_TS_ITR1 ((uint16_t)0x0010)
#define | TIM_TS_ITR2 ((uint16_t)0x0020)
#define | TIM_TS_ITR3 ((uint16_t)0x0030)
#define | TIM_TS_TI1F_ED ((uint16_t)0x0040)
#define | TIM_TS_TI1FP1 ((uint16_t)0x0050)
#define | TIM_TS_TI2FP2 ((uint16_t)0x0060)
#define | TIM_UpdateSource_Global ((uint16_t)0x0000)
#define | TIM_UpdateSource_Regular ((uint16_t)0x0001)

Functions

void | TIM_ARRPreloadConfig (TIM_TypeDef *TIMx, FunctionalState NewState)
Enables or disables TIMx peripheral Preload register on ARR.
void | TIM_BDTRConfig (TIM_TypeDef *TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)
Configures the: Break feature, dead time, Lock level, the OSSI, the OSSR State and the AOE(automatic output enable).
void | TIM_BDTRStructInit (TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)
Fills each TIM_BDTRInitStruct member with its default value.
void | TIM_CCPreloadControl (TIM_TypeDef *TIMx, FunctionalState NewState)
Sets or Resets the TIM peripheral Capture Compare Preload Control bit.
void | TIM_CCxCmd (TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx)
Enables or disables the TIM Capture Compare Channel x.
void | TIM_CCxNCmd (TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN)
Enables or disables the TIM Capture Compare Channel xN.
void | TIM_ClearFlag (TIM_TypeDef *TIMx, uint16_t TIM_FLAG)
Clears the TIMx's pending flags.
void | TIM_ClearITPendingBit (TIM_TypeDef *TIMx, uint16_t TIM_IT)
Clears the TIMx's interrupt pending bits.
void | TIM_ClearOC1Ref (TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
Clears or safeguards the OCREF1 signal on an external event.
void | TIM_ClearOC2Ref (TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
Clears or safeguards the OCREF2 signal on an external event.
void | TIM_ClearOC3Ref (TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
Clears or safeguards the OCREF3 signal on an external event.
void | TIM_ClearOC4Ref (TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
Clears or safeguards the OCREF4 signal on an external event.
void | TIM_Cmd (TIM_TypeDef *TIMx, FunctionalState NewState)
Enables or disables the specified TIM peripheral.
void | TIM_CounterModeConfig (TIM_TypeDef *TIMx, uint16_t TIM_CounterMode)
Specifies the TIMx Counter Mode to be used.
void | TIM_CtrlPWMOutputs (TIM_TypeDef *TIMx, FunctionalState NewState)
Enables or disables the TIM peripheral Main Outputs.
void | TIM_DeInit (TIM_TypeDef *TIMx)
Deinitializes the TIMx peripheral registers to their default reset values.
void | TIM_DMACmd (TIM_TypeDef *TIMx, uint16_t TIM_DMASource, FunctionalState NewState)
Enables or disables the TIMx's DMA Requests.
void | TIM_DMAConfig (TIM_TypeDef *TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)
Configures the TIMx's DMA interface.
void | TIM_EncoderInterfaceConfig (TIM_TypeDef *TIMx, uint16_t TIM_EncoderMode, uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity)
Configures the TIMx Encoder Interface.
void | TIM_ETRClockMode1Config (TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
Configures the External clock Mode1.
void | TIM_ETRClockMode2Config (TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
Configures the External clock Mode2.
void | TIM_ETRConfig (TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
Configures the TIMx External Trigger (ETR).
void | TIM_ForcedOC1Config (TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
Forces the TIMx output 1 waveform to active or inactive level.
void | TIM_ForcedOC2Config (TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
Forces the TIMx output 2 waveform to active or inactive level.
void | TIM_ForcedOC3Config (TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
Forces the TIMx output 3 waveform to active or inactive level.
void | TIM_ForcedOC4Config (TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
Forces the TIMx output 4 waveform to active or inactive level.
void | TIM_GenerateEvent (TIM_TypeDef *TIMx, uint16_t TIM_EventSource)
Configures the TIMx event to be generate by software.
uint16_t | TIM_GetCapture1 (TIM_TypeDef *TIMx)
Gets the TIMx Input Capture 1 value.
uint16_t | TIM_GetCapture2 (TIM_TypeDef *TIMx)
Gets the TIMx Input Capture 2 value.
uint16_t | TIM_GetCapture3 (TIM_TypeDef *TIMx)
Gets the TIMx Input Capture 3 value.
uint16_t | TIM_GetCapture4 (TIM_TypeDef *TIMx)
Gets the TIMx Input Capture 4 value.
uint16_t | TIM_GetCounter (TIM_TypeDef *TIMx)
Gets the TIMx Counter value.
FlagStatus | TIM_GetFlagStatus (TIM_TypeDef *TIMx, uint16_t TIM_FLAG)
Checks whether the specified TIM flag is set or not.
ITStatus | TIM_GetITStatus (TIM_TypeDef *TIMx, uint16_t TIM_IT)
Checks whether the TIM interrupt has occurred or not.
uint16_t | TIM_GetPrescaler (TIM_TypeDef *TIMx)
Gets the TIMx Prescaler value.
void | TIM_ICInit (TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct)
Initializes the TIM peripheral according to the specified parameters in the TIM_ICInitStruct.
void | TIM_ICStructInit (TIM_ICInitTypeDef *TIM_ICInitStruct)
Fills each TIM_ICInitStruct member with its default value.
void | TIM_InternalClockConfig (TIM_TypeDef *TIMx)
Configures the TIMx internal Clock.
void | TIM_ITConfig (TIM_TypeDef *TIMx, uint16_t TIM_IT, FunctionalState NewState)
Enables or disables the specified TIM interrupts.
void | TIM_ITRxExternalClockConfig (TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource)
Configures the TIMx Internal Trigger as External Clock.
void | TIM_OC1FastConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
Configures the TIMx Output Compare 1 Fast feature.
void | TIM_OC1Init (TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
Initializes the TIMx Channel1 according to the specified parameters in the TIM_OCInitStruct.
void | TIM_OC1NPolarityConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity)
Configures the TIMx Channel 1N polarity.
void | TIM_OC1PolarityConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
Configures the TIMx channel 1 polarity.
void | TIM_OC1PreloadConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
Enables or disables the TIMx peripheral Preload register on CCR1.
void | TIM_OC2FastConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
Configures the TIMx Output Compare 2 Fast feature.
void | TIM_OC2Init (TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
Initializes the TIMx Channel2 according to the specified parameters in the TIM_OCInitStruct.
void | TIM_OC2NPolarityConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity)
Configures the TIMx Channel 2N polarity.
void | TIM_OC2PolarityConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
Configures the TIMx channel 2 polarity.
void | TIM_OC2PreloadConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
Enables or disables the TIMx peripheral Preload register on CCR2.
void | TIM_OC3FastConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
Configures the TIMx Output Compare 3 Fast feature.
void | TIM_OC3Init (TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
Initializes the TIMx Channel3 according to the specified parameters in the TIM_OCInitStruct.
void | TIM_OC3NPolarityConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity)
Configures the TIMx Channel 3N polarity.
void | TIM_OC3PolarityConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
Configures the TIMx channel 3 polarity.
void | TIM_OC3PreloadConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
Enables or disables the TIMx peripheral Preload register on CCR3.
void | TIM_OC4FastConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
Configures the TIMx Output Compare 4 Fast feature.
void | TIM_OC4Init (TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
Initializes the TIMx Channel4 according to the specified parameters in the TIM_OCInitStruct.
void | TIM_OC4PolarityConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
Configures the TIMx channel 4 polarity.
void | TIM_OC4PreloadConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
Enables or disables the TIMx peripheral Preload register on CCR4.
void | TIM_OCStructInit (TIM_OCInitTypeDef *TIM_OCInitStruct)
Fills each TIM_OCInitStruct member with its default value.
void | TIM_PrescalerConfig (TIM_TypeDef *TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)
Configures the TIMx Prescaler.
void | TIM_PWMIConfig (TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct)
Configures the TIM peripheral according to the specified parameters in the TIM_ICInitStruct to measure an external PWM signal.
void | TIM_SelectCCDMA (TIM_TypeDef *TIMx, FunctionalState NewState)
Selects the TIMx peripheral Capture Compare DMA source.
void | TIM_SelectCOM (TIM_TypeDef *TIMx, FunctionalState NewState)
Selects the TIM peripheral Commutation event.
void | TIM_SelectHallSensor (TIM_TypeDef *TIMx, FunctionalState NewState)
Enables or disables the TIMx's Hall sensor interface.
void | TIM_SelectInputTrigger (TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource)
Selects the Input Trigger source.
void | TIM_SelectMasterSlaveMode (TIM_TypeDef *TIMx, uint16_t TIM_MasterSlaveMode)
Sets or Resets the TIMx Master/Slave Mode.
void | TIM_SelectOCxM (TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode)
Selects the TIM Output Compare Mode.
void | TIM_SelectOnePulseMode (TIM_TypeDef *TIMx, uint16_t TIM_OPMode)
Selects the TIMx's One Pulse Mode.
void | TIM_SelectOutputTrigger (TIM_TypeDef *TIMx, uint16_t TIM_TRGOSource)
Selects the TIMx Trigger Output Mode.
void | TIM_SelectSlaveMode (TIM_TypeDef *TIMx, uint16_t TIM_SlaveMode)
Selects the TIMx Slave Mode.
void | TIM_SetAutoreload (TIM_TypeDef *TIMx, uint16_t Autoreload)
Sets the TIMx Autoreload Register value.
void | TIM_SetClockDivision (TIM_TypeDef *TIMx, uint16_t TIM_CKD)
Sets the TIMx Clock Division value.
void | TIM_SetCompare1 (TIM_TypeDef *TIMx, uint16_t Compare1)
Sets the TIMx Capture Compare1 Register value.
void | TIM_SetCompare2 (TIM_TypeDef *TIMx, uint16_t Compare2)
Sets the TIMx Capture Compare2 Register value.
void | TIM_SetCompare3 (TIM_TypeDef *TIMx, uint16_t Compare3)
Sets the TIMx Capture Compare3 Register value.
void | TIM_SetCompare4 (TIM_TypeDef *TIMx, uint16_t Compare4)
Sets the TIMx Capture Compare4 Register value.
void | TIM_SetCounter (TIM_TypeDef *TIMx, uint16_t Counter)
Sets the TIMx Counter Register value.
void | TIM_SetIC1Prescaler (TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
Sets the TIMx Input Capture 1 prescaler.
void | TIM_SetIC2Prescaler (TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
Sets the TIMx Input Capture 2 prescaler.
void | TIM_SetIC3Prescaler (TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
Sets the TIMx Input Capture 3 prescaler.
void | TIM_SetIC4Prescaler (TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
Sets the TIMx Input Capture 4 prescaler.
void | TIM_TimeBaseInit (TIM_TypeDef *TIMx, TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct)
Initializes the TIMx Time Base Unit peripheral according to the specified parameters in the TIM_TimeBaseInitStruct.
void | TIM_TimeBaseStructInit (TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct)
Fills each TIM_TimeBaseInitStruct member with its default value.
void | TIM_TIxExternalClockConfig (TIM_TypeDef *TIMx, uint16_t TIM_TIxExternalCLKSource, uint16_t TIM_ICPolarity, uint16_t ICFilter)
Configures the TIMx Trigger as External Clock.
void | TIM_UpdateDisableConfig (TIM_TypeDef *TIMx, FunctionalState NewState)
Enables or Disables the TIMx Update event.
void | TIM_UpdateRequestConfig (TIM_TypeDef *TIMx, uint16_t TIM_UpdateSource)
Configures the TIMx Update Request Interrupt source.

Detailed Description

This file contains all the functions prototypes for the TIM firmware library.

Author:
MCD Application Team
Version:
V3.5.0
Date:
11-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm32f10x_tim.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_usart.c File Reference

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Defines | Functions

stm32f10x_usart.c File Reference

This file provides all the USART firmware functions. More...

#include "stm32f10x_usart.h"
#include "stm32f10x_rcc.h"

Go to the source code of this file.

Defines

#define | CR1_CLEAR_Mask ((uint16_t)0xE9F3)
#define | CR1_OVER8_Reset ((u16)0x7FFF)
#define | CR1_OVER8_Set ((u16)0x8000)
#define | CR1_RWU_Reset ((uint16_t)0xFFFD)
#define | CR1_RWU_Set ((uint16_t)0x0002)
#define | CR1_SBK_Set ((uint16_t)0x0001)
#define | CR1_UE_Reset ((uint16_t)0xDFFF)
#define | CR1_UE_Set ((uint16_t)0x2000)
#define | CR1_WAKE_Mask ((uint16_t)0xF7FF)
#define | CR2_Address_Mask ((uint16_t)0xFFF0)
#define | CR2_CLOCK_CLEAR_Mask ((uint16_t)0xF0FF)
#define | CR2_LBDL_Mask ((uint16_t)0xFFDF)
#define | CR2_LINEN_Reset ((uint16_t)0xBFFF)
#define | CR2_LINEN_Set ((uint16_t)0x4000)
#define | CR2_STOP_CLEAR_Mask ((uint16_t)0xCFFF)
#define | CR3_CLEAR_Mask ((uint16_t)0xFCFF)
#define | CR3_HDSEL_Reset ((uint16_t)0xFFF7)
#define | CR3_HDSEL_Set ((uint16_t)0x0008)
#define | CR3_IREN_Reset ((uint16_t)0xFFFD)
#define | CR3_IREN_Set ((uint16_t)0x0002)
#define | CR3_IRLP_Mask ((uint16_t)0xFFFB)
#define | CR3_NACK_Reset ((uint16_t)0xFFEF)
#define | CR3_NACK_Set ((uint16_t)0x0010)
#define | CR3_ONEBITE_Reset ((u16)0xF7FF)
#define | CR3_ONEBITE_Set ((u16)0x0800)
#define | CR3_SCEN_Reset ((uint16_t)0xFFDF)
#define | CR3_SCEN_Set ((uint16_t)0x0020)
#define | GTPR_LSB_Mask ((uint16_t)0x00FF)
#define | GTPR_MSB_Mask ((uint16_t)0xFF00)
#define | IT_Mask ((uint16_t)0x001F)

Functions

void | USART_ClearFlag (USART_TypeDef *USARTx, uint16_t USART_FLAG)
Clears the USARTx's pending flags.
void | USART_ClearITPendingBit (USART_TypeDef *USARTx, uint16_t USART_IT)
Clears the USARTx's interrupt pending bits.
void | USART_ClockInit (USART_TypeDef *USARTx, USART_ClockInitTypeDef *USART_ClockInitStruct)
Initializes the USARTx peripheral Clock according to the specified parameters in the USART_ClockInitStruct .
void | USART_ClockStructInit (USART_ClockInitTypeDef *USART_ClockInitStruct)
Fills each USART_ClockInitStruct member with its default value.
void | USART_Cmd (USART_TypeDef *USARTx, FunctionalState NewState)
Enables or disables the specified USART peripheral.
void | USART_DeInit (USART_TypeDef *USARTx)
Deinitializes the USARTx peripheral registers to their default reset values.
void | USART_DMACmd (USART_TypeDef *USARTx, uint16_t USART_DMAReq, FunctionalState NewState)
Enables or disables the USART’s DMA interface.
FlagStatus | USART_GetFlagStatus (USART_TypeDef *USARTx, uint16_t USART_FLAG)
Checks whether the specified USART flag is set or not.
ITStatus | USART_GetITStatus (USART_TypeDef *USARTx, uint16_t USART_IT)
Checks whether the specified USART interrupt has occurred or not.
void | USART_HalfDuplexCmd (USART_TypeDef *USARTx, FunctionalState NewState)
Enables or disables the USART’s Half Duplex communication.
void | USART_Init (USART_TypeDef *USARTx, USART_InitTypeDef *USART_InitStruct)
Initializes the USARTx peripheral according to the specified parameters in the USART_InitStruct .
void | USART_IrDACmd (USART_TypeDef *USARTx, FunctionalState NewState)
Enables or disables the USART's IrDA interface.
void | USART_IrDAConfig (USART_TypeDef *USARTx, uint16_t USART_IrDAMode)
Configures the USART's IrDA interface.
void | USART_ITConfig (USART_TypeDef *USARTx, uint16_t USART_IT, FunctionalState NewState)
Enables or disables the specified USART interrupts.
void | USART_LINBreakDetectLengthConfig (USART_TypeDef *USARTx, uint16_t USART_LINBreakDetectLength)
Sets the USART LIN Break detection length.
void | USART_LINCmd (USART_TypeDef *USARTx, FunctionalState NewState)
Enables or disables the USART’s LIN mode.
void | USART_OneBitMethodCmd (USART_TypeDef *USARTx, FunctionalState NewState)
Enables or disables the USART's one bit sampling method.
void | USART_OverSampling8Cmd (USART_TypeDef *USARTx, FunctionalState NewState)
Enables or disables the USART's 8x oversampling mode.
uint16_t | USART_ReceiveData (USART_TypeDef *USARTx)
Returns the most recent received data by the USARTx peripheral.
void | USART_ReceiverWakeUpCmd (USART_TypeDef *USARTx, FunctionalState NewState)
Determines if the USART is in mute mode or not.
void | USART_SendBreak (USART_TypeDef *USARTx)
Transmits break characters.
void | USART_SendData (USART_TypeDef *USARTx, uint16_t Data)
Transmits single data through the USARTx peripheral.
void | USART_SetAddress (USART_TypeDef *USARTx, uint8_t USART_Address)
Sets the address of the USART node.
void | USART_SetGuardTime (USART_TypeDef *USARTx, uint8_t USART_GuardTime)
Sets the specified USART guard time.
void | USART_SetPrescaler (USART_TypeDef *USARTx, uint8_t USART_Prescaler)
Sets the system clock prescaler.
void | USART_SmartCardCmd (USART_TypeDef *USARTx, FunctionalState NewState)
Enables or disables the USART’s Smart Card mode.
void | USART_SmartCardNACKCmd (USART_TypeDef *USARTx, FunctionalState NewState)
Enables or disables NACK transmission.
void | USART_StructInit (USART_InitTypeDef *USART_InitStruct)
Fills each USART_InitStruct member with its default value.
void | USART_WakeUpConfig (USART_TypeDef *USARTx, uint16_t USART_WakeUp)
Selects the USART WakeUp method.

Detailed Description

This file provides all the USART firmware functions.

Author:
MCD Application Team
Version:
V3.5.0
Date:
11-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm32f10x_usart.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_usart.h File Reference

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  • STM32F10x_StdPeriph_Lib_V3.5.0
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Data Structures | Defines | Functions

stm32f10x_usart.h File Reference

This file contains all the functions prototypes for the USART firmware library. More...

#include "stm32f10x.h"

Go to the source code of this file.

Data Structures

struct | USART_ClockInitTypeDef
USART Clock Init Structure definition. More...
struct | USART_InitTypeDef
USART Init Structure definition. More...

Defines

#define | IS_USART_1234_PERIPH(PERIPH)
#define | IS_USART_123_PERIPH(PERIPH)
#define | IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF)
#define | IS_USART_ALL_PERIPH(PERIPH)
#define | IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x0044AA21))
#define | IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00))
#define | IS_USART_CLEAR_IT(IT)
#define | IS_USART_CLOCK(CLOCK)
#define | IS_USART_CONFIG_IT(IT)
#define | IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge))
#define | IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High))
#define | IS_USART_DATA(DATA) ((DATA) <= 0x1FF)
#define | IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00))
#define | IS_USART_FLAG(FLAG)
#define | IS_USART_GET_IT(IT)
#define | IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)
#define | IS_USART_IRDA_MODE(MODE)
#define | IS_USART_LASTBIT(LASTBIT)
#define | IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH)
#define | IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00))
#define | IS_USART_PARITY(PARITY)
#define | IS_USART_PERIPH_FLAG(PERIPH, USART_FLAG)
#define | IS_USART_STOPBITS(STOPBITS)
#define | IS_USART_WAKEUP(WAKEUP)
#define | IS_USART_WORD_LENGTH(LENGTH)
#define | USART_Clock_Disable ((uint16_t)0x0000)
#define | USART_Clock_Enable ((uint16_t)0x0800)
#define | USART_CPHA_1Edge ((uint16_t)0x0000)
#define | USART_CPHA_2Edge ((uint16_t)0x0200)
#define | USART_CPOL_High ((uint16_t)0x0400)
#define | USART_CPOL_Low ((uint16_t)0x0000)
#define | USART_DMAReq_Rx ((uint16_t)0x0040)
#define | USART_DMAReq_Tx ((uint16_t)0x0080)
#define | USART_FLAG_CTS ((uint16_t)0x0200)
#define | USART_FLAG_FE ((uint16_t)0x0002)
#define | USART_FLAG_IDLE ((uint16_t)0x0010)
#define | USART_FLAG_LBD ((uint16_t)0x0100)
#define | USART_FLAG_NE ((uint16_t)0x0004)
#define | USART_FLAG_ORE ((uint16_t)0x0008)
#define | USART_FLAG_PE ((uint16_t)0x0001)
#define | USART_FLAG_RXNE ((uint16_t)0x0020)
#define | USART_FLAG_TC ((uint16_t)0x0040)
#define | USART_FLAG_TXE ((uint16_t)0x0080)
#define | USART_HardwareFlowControl_CTS ((uint16_t)0x0200)
#define | USART_HardwareFlowControl_None ((uint16_t)0x0000)
#define | USART_HardwareFlowControl_RTS ((uint16_t)0x0100)
#define | USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300)
#define | USART_IrDAMode_LowPower ((uint16_t)0x0004)
#define | USART_IrDAMode_Normal ((uint16_t)0x0000)
#define | USART_IT_CTS ((uint16_t)0x096A)
#define | USART_IT_ERR ((uint16_t)0x0060)
#define | USART_IT_FE ((uint16_t)0x0160)
#define | USART_IT_IDLE ((uint16_t)0x0424)
#define | USART_IT_LBD ((uint16_t)0x0846)
#define | USART_IT_NE ((uint16_t)0x0260)
#define | USART_IT_ORE ((uint16_t)0x0360)
#define | USART_IT_PE ((uint16_t)0x0028)
#define | USART_IT_RXNE ((uint16_t)0x0525)
#define | USART_IT_TC ((uint16_t)0x0626)
#define | USART_IT_TXE ((uint16_t)0x0727)
#define | USART_LastBit_Disable ((uint16_t)0x0000)
#define | USART_LastBit_Enable ((uint16_t)0x0100)
#define | USART_LINBreakDetectLength_10b ((uint16_t)0x0000)
#define | USART_LINBreakDetectLength_11b ((uint16_t)0x0020)
#define | USART_Mode_Rx ((uint16_t)0x0004)
#define | USART_Mode_Tx ((uint16_t)0x0008)
#define | USART_Parity_Even ((uint16_t)0x0400)
#define | USART_Parity_No ((uint16_t)0x0000)
#define | USART_Parity_Odd ((uint16_t)0x0600)
#define | USART_StopBits_0_5 ((uint16_t)0x1000)
#define | USART_StopBits_1 ((uint16_t)0x0000)
#define | USART_StopBits_1_5 ((uint16_t)0x3000)
#define | USART_StopBits_2 ((uint16_t)0x2000)
#define | USART_WakeUp_AddressMark ((uint16_t)0x0800)
#define | USART_WakeUp_IdleLine ((uint16_t)0x0000)
#define | USART_WordLength_8b ((uint16_t)0x0000)
#define | USART_WordLength_9b ((uint16_t)0x1000)

Functions

void | USART_ClearFlag (USART_TypeDef *USARTx, uint16_t USART_FLAG)
Clears the USARTx's pending flags.
void | USART_ClearITPendingBit (USART_TypeDef *USARTx, uint16_t USART_IT)
Clears the USARTx's interrupt pending bits.
void | USART_ClockInit (USART_TypeDef *USARTx, USART_ClockInitTypeDef *USART_ClockInitStruct)
Initializes the USARTx peripheral Clock according to the specified parameters in the USART_ClockInitStruct .
void | USART_ClockStructInit (USART_ClockInitTypeDef *USART_ClockInitStruct)
Fills each USART_ClockInitStruct member with its default value.
void | USART_Cmd (USART_TypeDef *USARTx, FunctionalState NewState)
Enables or disables the specified USART peripheral.
void | USART_DeInit (USART_TypeDef *USARTx)
Deinitializes the USARTx peripheral registers to their default reset values.
void | USART_DMACmd (USART_TypeDef *USARTx, uint16_t USART_DMAReq, FunctionalState NewState)
Enables or disables the USART’s DMA interface.
FlagStatus | USART_GetFlagStatus (USART_TypeDef *USARTx, uint16_t USART_FLAG)
Checks whether the specified USART flag is set or not.
ITStatus | USART_GetITStatus (USART_TypeDef *USARTx, uint16_t USART_IT)
Checks whether the specified USART interrupt has occurred or not.
void | USART_HalfDuplexCmd (USART_TypeDef *USARTx, FunctionalState NewState)
Enables or disables the USART’s Half Duplex communication.
void | USART_Init (USART_TypeDef *USARTx, USART_InitTypeDef *USART_InitStruct)
Initializes the USARTx peripheral according to the specified parameters in the USART_InitStruct .
void | USART_IrDACmd (USART_TypeDef *USARTx, FunctionalState NewState)
Enables or disables the USART's IrDA interface.
void | USART_IrDAConfig (USART_TypeDef *USARTx, uint16_t USART_IrDAMode)
Configures the USART's IrDA interface.
void | USART_ITConfig (USART_TypeDef *USARTx, uint16_t USART_IT, FunctionalState NewState)
Enables or disables the specified USART interrupts.
void | USART_LINBreakDetectLengthConfig (USART_TypeDef *USARTx, uint16_t USART_LINBreakDetectLength)
Sets the USART LIN Break detection length.
void | USART_LINCmd (USART_TypeDef *USARTx, FunctionalState NewState)
Enables or disables the USART’s LIN mode.
void | USART_OneBitMethodCmd (USART_TypeDef *USARTx, FunctionalState NewState)
Enables or disables the USART's one bit sampling method.
void | USART_OverSampling8Cmd (USART_TypeDef *USARTx, FunctionalState NewState)
Enables or disables the USART's 8x oversampling mode.
uint16_t | USART_ReceiveData (USART_TypeDef *USARTx)
Returns the most recent received data by the USARTx peripheral.
void | USART_ReceiverWakeUpCmd (USART_TypeDef *USARTx, FunctionalState NewState)
Determines if the USART is in mute mode or not.
void | USART_SendBreak (USART_TypeDef *USARTx)
Transmits break characters.
void | USART_SendData (USART_TypeDef *USARTx, uint16_t Data)
Transmits single data through the USARTx peripheral.
void | USART_SetAddress (USART_TypeDef *USARTx, uint8_t USART_Address)
Sets the address of the USART node.
void | USART_SetGuardTime (USART_TypeDef *USARTx, uint8_t USART_GuardTime)
Sets the specified USART guard time.
void | USART_SetPrescaler (USART_TypeDef *USARTx, uint8_t USART_Prescaler)
Sets the system clock prescaler.
void | USART_SmartCardCmd (USART_TypeDef *USARTx, FunctionalState NewState)
Enables or disables the USART’s Smart Card mode.
void | USART_SmartCardNACKCmd (USART_TypeDef *USARTx, FunctionalState NewState)
Enables or disables NACK transmission.
void | USART_StructInit (USART_InitTypeDef *USART_InitStruct)
Fills each USART_InitStruct member with its default value.
void | USART_WakeUpConfig (USART_TypeDef *USARTx, uint16_t USART_WakeUp)
Selects the USART WakeUp method.

Detailed Description

This file contains all the functions prototypes for the USART firmware library.

Author:
MCD Application Team
Version:
V3.5.0
Date:
11-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm32f10x_usart.h.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_wwdg.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Libraries
  • STM32F10x_StdPeriph_Driver
  • src
Defines | Functions

stm32f10x_wwdg.c File Reference

This file provides all the WWDG firmware functions. More...

#include "stm32f10x_wwdg.h"
#include "stm32f10x_rcc.h"

Go to the source code of this file.

Defines

#define | BIT_Mask ((uint8_t)0x7F)
#define | CFR_EWI_BB (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4))
#define | CFR_OFFSET (WWDG_OFFSET + 0x04)
#define | CFR_W_Mask ((uint32_t)0xFFFFFF80)
#define | CFR_WDGTB_Mask ((uint32_t)0xFFFFFE7F)
#define | CR_WDGA_Set ((uint32_t)0x00000080)
#define | EWI_BitNumber 0x09
#define | WWDG_OFFSET (WWDG_BASE - PERIPH_BASE)

Functions

void | WWDG_ClearFlag (void)
Clears Early Wakeup interrupt flag.
void | WWDG_DeInit (void)
Deinitializes the WWDG peripheral registers to their default reset values.
void | WWDG_Enable (uint8_t Counter)
Enables WWDG and load the counter value.
void | WWDG_EnableIT (void)
Enables the WWDG Early Wakeup interrupt(EWI).
FlagStatus | WWDG_GetFlagStatus (void)
Checks whether the Early Wakeup interrupt flag is set or not.
void | WWDG_SetCounter (uint8_t Counter)
Sets the WWDG counter value.
void | WWDG_SetPrescaler (uint32_t WWDG_Prescaler)
Sets the WWDG Prescaler.
void | WWDG_SetWindowValue (uint8_t WindowValue)
Sets the WWDG window value.

Detailed Description

This file provides all the WWDG firmware functions.

Author:
MCD Application Team
Version:
V3.5.0
Date:
11-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm32f10x_wwdg.c.


STM32F10x Standard Peripherals Firmware Library: stm32f10x_wwdg.h File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Libraries
  • STM32F10x_StdPeriph_Driver
  • inc
Defines | Functions

stm32f10x_wwdg.h File Reference

This file contains all the functions prototypes for the WWDG firmware library. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F))
#define | IS_WWDG_PRESCALER(PRESCALER)
#define | IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F)
#define | WWDG_Prescaler_1 ((uint32_t)0x00000000)
#define | WWDG_Prescaler_2 ((uint32_t)0x00000080)
#define | WWDG_Prescaler_4 ((uint32_t)0x00000100)
#define | WWDG_Prescaler_8 ((uint32_t)0x00000180)

Functions

void | WWDG_ClearFlag (void)
Clears Early Wakeup interrupt flag.
void | WWDG_DeInit (void)
Deinitializes the WWDG peripheral registers to their default reset values.
void | WWDG_Enable (uint8_t Counter)
Enables WWDG and load the counter value.
void | WWDG_EnableIT (void)
Enables the WWDG Early Wakeup interrupt(EWI).
FlagStatus | WWDG_GetFlagStatus (void)
Checks whether the Early Wakeup interrupt flag is set or not.
void | WWDG_SetCounter (uint8_t Counter)
Sets the WWDG counter value.
void | WWDG_SetPrescaler (uint32_t WWDG_Prescaler)
Sets the WWDG Prescaler.
void | WWDG_SetWindowValue (uint8_t WindowValue)
Sets the WWDG window value.

Detailed Description

This file contains all the functions prototypes for the WWDG firmware library.

Author:
MCD Application Team
Version:
V3.5.0
Date:
11-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm32f10x_wwdg.h.


STM32F10x Standard Peripherals Firmware Library: stm32l152_eval.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • STM32L152_EVAL
Functions | Variables

stm32l152_eval.c File Reference

This file provides:

  • set of firmware functions to manage Leds, push-button and COM ports
  • low level initialization functions for SD card (on SPI) and temperature sensor (LM75) available on STM32L152-EVAL evaluation board RevB from STMicroelectronics.
More...

#include "stm32l152_eval.h"
#include "stm32l1xx_spi.h"
#include "stm32l1xx_i2c.h"

Go to the source code of this file.

Functions

void | LM75_LowLevel_DeInit (void)
DeInitializes the LM75_I2C.
void | LM75_LowLevel_Init (void)
Initializes the LM75_I2C.
void | SD_LowLevel_DeInit (void)
DeInitializes the SPI interface.
void | SD_LowLevel_Init (void)
Initializes the SD Card and put it into StandBy State (Ready for data transfer).
void | sEE_LowLevel_DeInit (void)
DeInitializes peripherals used by the I2C EEPROM driver.
void | sEE_LowLevel_DMAConfig (uint32_t pBuffer, uint32_t BufferSize, uint32_t Direction)
Initializes DMA channel used by the I2C EEPROM driver.
void | sEE_LowLevel_Init (void)
Initializes peripherals used by the I2C EEPROM driver.
void | STM_EVAL_COMInit (COM_TypeDef COM, USART_InitTypeDef *USART_InitStruct)
Configures COM port.
void | STM_EVAL_LEDInit (Led_TypeDef Led)
Configures LED GPIO.
void | STM_EVAL_LEDOff (Led_TypeDef Led)
Turns selected LED Off.
void | STM_EVAL_LEDOn (Led_TypeDef Led)
Turns selected LED On.
void | STM_EVAL_LEDToggle (Led_TypeDef Led)
Toggles the selected LED.
uint32_t | STM_EVAL_PBGetState (Button_TypeDef Button)
Returns the selected Button state.
void | STM_EVAL_PBInit (Button_TypeDef Button, ButtonMode_TypeDef Button_Mode)
Configures Button GPIO and EXTI Line.

Variables

const uint32_t | BUTTON_CLK [BUTTONn]
const uint16_t | BUTTON_EXTI_LINE [BUTTONn]
const uint16_t | BUTTON_IRQn [BUTTONn]
const uint16_t | BUTTON_PIN [BUTTONn]
const uint16_t | BUTTON_PIN_SOURCE [BUTTONn]
GPIO_TypeDef * | BUTTON_PORT [BUTTONn]
const uint16_t | BUTTON_PORT_SOURCE [BUTTONn]
const uint16_t | COM_RX_AF [COMn] = {EVAL_COM1_RX_AF, EVAL_COM2_RX_AF}
const uint16_t | COM_RX_PIN [COMn] = {EVAL_COM1_RX_PIN, EVAL_COM2_RX_PIN}
const uint16_t | COM_RX_PIN_SOURCE [COMn] = {EVAL_COM1_RX_SOURCE, EVAL_COM2_RX_SOURCE}
GPIO_TypeDef * | COM_RX_PORT [COMn] = {EVAL_COM1_RX_GPIO_PORT, EVAL_COM2_RX_GPIO_PORT}
const uint32_t | COM_RX_PORT_CLK [COMn] = {EVAL_COM1_RX_GPIO_CLK, EVAL_COM2_RX_GPIO_CLK}
const uint16_t | COM_TX_AF [COMn] = {EVAL_COM1_TX_AF, EVAL_COM2_TX_AF}
const uint16_t | COM_TX_PIN [COMn] = {EVAL_COM1_TX_PIN, EVAL_COM2_TX_PIN}
const uint16_t | COM_TX_PIN_SOURCE [COMn] = {EVAL_COM1_TX_SOURCE, EVAL_COM2_TX_SOURCE}
GPIO_TypeDef * | COM_TX_PORT [COMn] = {EVAL_COM1_TX_GPIO_PORT, EVAL_COM2_TX_GPIO_PORT}
const uint32_t | COM_TX_PORT_CLK [COMn] = {EVAL_COM1_TX_GPIO_CLK, EVAL_COM2_TX_GPIO_CLK}
USART_TypeDef * | COM_USART [COMn] = {EVAL_COM1, EVAL_COM2}
const uint32_t | COM_USART_CLK [COMn] = {EVAL_COM1_CLK, EVAL_COM2_CLK}
const uint32_t | GPIO_CLK [LEDn]
const uint16_t | GPIO_PIN [LEDn]
GPIO_TypeDef * | GPIO_PORT [LEDn]
DMA_InitTypeDef sEEDMA_InitStructure

Detailed Description

This file provides:

  • set of firmware functions to manage Leds, push-button and COM ports
  • low level initialization functions for SD card (on SPI) and temperature sensor (LM75) available on STM32L152-EVAL evaluation board RevB from STMicroelectronics.
Author:
MCD Application Team
Version:
V4.5.0
Date:
07-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm32l152_eval.c.


STM32F10x Standard Peripherals Firmware Library: stm32l152_eval.h File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • STM32L152_EVAL
Defines | Functions

stm32l152_eval.h File Reference

This file contains definitions for STM32L152_EVAL's Leds, push-buttons and COM ports hardware resources. More...

#include "stm32_eval.h"

Go to the source code of this file.

Defines

#define | BUTTONn 6
#define | COMn 2
#define | DOWN_BUTTON_EXTI_IRQn EXTI15_10_IRQn
#define | DOWN_BUTTON_EXTI_LINE EXTI_Line10
#define | DOWN_BUTTON_EXTI_PIN_SOURCE EXTI_PinSource10
#define | DOWN_BUTTON_EXTI_PORT_SOURCE EXTI_PortSourceGPIOE
#define | DOWN_BUTTON_GPIO_CLK RCC_AHBPeriph_GPIOE
#define | DOWN_BUTTON_GPIO_PORT GPIOE
#define | DOWN_BUTTON_PIN GPIO_Pin_10
Joystick Down push-button.
#define | EVAL_COM1 USART2
Definition for COM port1, connected to USART2.
#define | EVAL_COM1_CLK RCC_APB1Periph_USART2
#define | EVAL_COM1_CTS_AF GPIO_AF_USART2
#define | EVAL_COM1_CTS_GPIO_CLK RCC_AHBPeriph_GPIOD
#define | EVAL_COM1_CTS_GPIO_PORT GPIOD
#define | EVAL_COM1_CTS_PIN GPIO_Pin_3
#define | EVAL_COM1_CTS_SOURCE GPIO_PinSource3
#define | EVAL_COM1_IRQn USART2_IRQn
#define | EVAL_COM1_RTS_AF GPIO_AF_USART2
#define | EVAL_COM1_RTS_GPIO_CLK RCC_AHBPeriph_GPIOD
#define | EVAL_COM1_RTS_GPIO_PORT GPIOD
#define | EVAL_COM1_RTS_PIN GPIO_Pin_4
#define | EVAL_COM1_RTS_SOURCE GPIO_PinSource4
#define | EVAL_COM1_RX_AF GPIO_AF_USART2
#define | EVAL_COM1_RX_GPIO_CLK RCC_AHBPeriph_GPIOD
#define | EVAL_COM1_RX_GPIO_PORT GPIOD
#define | EVAL_COM1_RX_PIN GPIO_Pin_6
#define | EVAL_COM1_RX_SOURCE GPIO_PinSource6
#define | EVAL_COM1_TX_AF GPIO_AF_USART2
#define | EVAL_COM1_TX_GPIO_CLK RCC_AHBPeriph_GPIOD
#define | EVAL_COM1_TX_GPIO_PORT GPIOD
#define | EVAL_COM1_TX_PIN GPIO_Pin_5
#define | EVAL_COM1_TX_SOURCE GPIO_PinSource5
#define | EVAL_COM2 USART3
Definition for COM port2, connected to USART3.
#define | EVAL_COM2_CLK RCC_APB1Periph_USART3
#define | EVAL_COM2_IRQn USART3_IRQn
#define | EVAL_COM2_RX_AF GPIO_AF_USART3
#define | EVAL_COM2_RX_GPIO_CLK RCC_AHBPeriph_GPIOC
#define | EVAL_COM2_RX_GPIO_PORT GPIOC
#define | EVAL_COM2_RX_PIN GPIO_Pin_11
#define | EVAL_COM2_RX_SOURCE GPIO_PinSource11
#define | EVAL_COM2_TX_AF GPIO_AF_USART3
#define | EVAL_COM2_TX_GPIO_CLK RCC_AHBPeriph_GPIOC
#define | EVAL_COM2_TX_GPIO_PORT GPIOC
#define | EVAL_COM2_TX_PIN GPIO_Pin_10
#define | EVAL_COM2_TX_SOURCE GPIO_PinSource10
#define | KEY_BUTTON_EXTI_IRQn EXTI0_IRQn
#define | KEY_BUTTON_EXTI_LINE EXTI_Line0
#define | KEY_BUTTON_EXTI_PIN_SOURCE EXTI_PinSource0
#define | KEY_BUTTON_EXTI_PORT_SOURCE EXTI_PortSourceGPIOA
#define | KEY_BUTTON_GPIO_CLK RCC_AHBPeriph_GPIOA
#define | KEY_BUTTON_GPIO_PORT GPIOA
#define | KEY_BUTTON_PIN GPIO_Pin_0
Key push-button.
#define | LED1_GPIO_CLK RCC_AHBPeriph_GPIOD
#define | LED1_GPIO_PORT GPIOD
#define | LED1_PIN GPIO_Pin_0
#define | LED2_GPIO_CLK RCC_AHBPeriph_GPIOD
#define | LED2_GPIO_PORT GPIOD
#define | LED2_PIN GPIO_Pin_1
#define | LED3_GPIO_CLK RCC_AHBPeriph_GPIOD
#define | LED3_GPIO_PORT GPIOD
#define | LED3_PIN GPIO_Pin_4
#define | LED4_GPIO_CLK RCC_AHBPeriph_GPIOD
#define | LED4_GPIO_PORT GPIOD
#define | LED4_PIN GPIO_Pin_5
#define | LEDn 4
#define | LEFT_BUTTON_EXTI_IRQn EXTI15_10_IRQn
#define | LEFT_BUTTON_EXTI_LINE EXTI_Line12
#define | LEFT_BUTTON_EXTI_PIN_SOURCE EXTI_PinSource12
#define | LEFT_BUTTON_EXTI_PORT_SOURCE EXTI_PortSourceGPIOE
#define | LEFT_BUTTON_GPIO_CLK RCC_AHBPeriph_GPIOE
#define | LEFT_BUTTON_GPIO_PORT GPIOE
#define | LEFT_BUTTON_PIN GPIO_Pin_12
Joystick Left push-button.
#define | LM75_DMA_CLK RCC_AHBPeriph_DMA1
#define | LM75_DMA_RX_CHANNEL DMA1_Channel7
#define | LM75_DMA_RX_TCFLAG DMA1_FLAG_TC7
#define | LM75_DMA_TX_CHANNEL DMA1_Channel6
#define | LM75_DMA_TX_TCFLAG DMA1_FLAG_TC6
#define | LM75_I2C I2C1
LM75 Temperature Sensor I2C Interface pins.
#define | LM75_I2C_CLK RCC_APB1Periph_I2C1
#define | LM75_I2C_DR ((uint32_t)0x40005410)
#define | LM75_I2C_SCL_AF GPIO_AF_I2C1
#define | LM75_I2C_SCL_GPIO_CLK RCC_AHBPeriph_GPIOB
#define | LM75_I2C_SCL_GPIO_PORT GPIOB
#define | LM75_I2C_SCL_PIN GPIO_Pin_6
#define | LM75_I2C_SCL_SOURCE GPIO_PinSource6
#define | LM75_I2C_SDA_AF GPIO_AF_I2C1
#define | LM75_I2C_SDA_GPIO_CLK RCC_AHBPeriph_GPIOB
#define | LM75_I2C_SDA_GPIO_PORT GPIOB
#define | LM75_I2C_SDA_PIN GPIO_Pin_7
#define | LM75_I2C_SDA_SOURCE GPIO_PinSource7
#define | LM75_I2C_SMBUSALERT_AF GPIO_AF_I2C1
#define | LM75_I2C_SMBUSALERT_GPIO_CLK RCC_AHBPeriph_GPIOB
#define | LM75_I2C_SMBUSALERT_GPIO_PORT GPIOB
#define | LM75_I2C_SMBUSALERT_PIN GPIO_Pin_5
#define | LM75_I2C_SMBUSALERT_SOURCE GPIO_PinSource5
#define | RIGHT_BUTTON_EXTI_IRQn EXTI15_10_IRQn
#define | RIGHT_BUTTON_EXTI_LINE EXTI_Line11
#define | RIGHT_BUTTON_EXTI_PIN_SOURCE EXTI_PinSource11
#define | RIGHT_BUTTON_EXTI_PORT_SOURCE EXTI_PortSourceGPIOE
#define | RIGHT_BUTTON_GPIO_CLK RCC_AHBPeriph_GPIOE
#define | RIGHT_BUTTON_GPIO_PORT GPIOE
#define | RIGHT_BUTTON_PIN GPIO_Pin_11
Joystick Right push-button.
#define | SD_CS_GPIO_CLK RCC_AHBPeriph_GPIOD
#define | SD_CS_GPIO_PORT GPIOD
#define | SD_CS_PIN GPIO_Pin_7
#define | SD_DETECT_EXTI_IRQn EXTI9_5_IRQn
#define | SD_DETECT_EXTI_LINE EXTI_Line6
#define | SD_DETECT_EXTI_PIN_SOURCE EXTI_PinSource6
#define | SD_DETECT_EXTI_PORT_SOURCE EXTI_PortSourceGPIOE
#define | SD_DETECT_GPIO_CLK RCC_AHBPeriph_GPIOE
#define | SD_DETECT_GPIO_PORT GPIOE
#define | SD_DETECT_PIN GPIO_Pin_6
#define | SD_SPI SPI2
SD Card SPI Interface.
#define | SD_SPI_CLK RCC_APB1Periph_SPI2
#define | SD_SPI_MISO_AF GPIO_AF_SPI2
#define | SD_SPI_MISO_GPIO_CLK RCC_AHBPeriph_GPIOB
#define | SD_SPI_MISO_GPIO_PORT GPIOB
#define | SD_SPI_MISO_PIN GPIO_Pin_14
#define | SD_SPI_MISO_SOURCE GPIO_PinSource14
#define | SD_SPI_MOSI_AF GPIO_AF_SPI2
#define | SD_SPI_MOSI_GPIO_CLK RCC_AHBPeriph_GPIOB
#define | SD_SPI_MOSI_GPIO_PORT GPIOB
#define | SD_SPI_MOSI_PIN GPIO_Pin_15
#define | SD_SPI_MOSI_SOURCE GPIO_PinSource15
#define | SD_SPI_SCK_AF GPIO_AF_SPI2
#define | SD_SPI_SCK_GPIO_CLK RCC_AHBPeriph_GPIOB
#define | SD_SPI_SCK_GPIO_PORT GPIOB
#define | SD_SPI_SCK_PIN GPIO_Pin_13
#define | SD_SPI_SCK_SOURCE GPIO_PinSource13
#define | sEE_DIRECTION_RX 1
#define | sEE_DIRECTION_TX 0
#define | sEE_I2C I2C1
I2C EEPROM Interface pins.
#define | sEE_I2C_CLK RCC_APB1Periph_I2C1
#define | sEE_I2C_DMA DMA1
#define | sEE_I2C_DMA_CHANNEL_RX DMA1_Channel7
#define | sEE_I2C_DMA_CHANNEL_TX DMA1_Channel6
#define | sEE_I2C_DMA_CLK RCC_AHBPeriph_DMA1
#define | sEE_I2C_DMA_FLAG_RX_GL DMA1_IT_GL7
#define | sEE_I2C_DMA_FLAG_RX_TC DMA1_IT_TC7
#define | sEE_I2C_DMA_FLAG_TX_GL DMA1_IT_GL6
#define | sEE_I2C_DMA_FLAG_TX_TC DMA1_IT_TC6
#define | sEE_I2C_DMA_PREPRIO 0
#define | sEE_I2C_DMA_RX_IRQHandler DMA1_Channel7_IRQHandler
#define | sEE_I2C_DMA_RX_IRQn DMA1_Channel7_IRQn
#define | sEE_I2C_DMA_SUBPRIO 0
#define | sEE_I2C_DMA_TX_IRQHandler DMA1_Channel6_IRQHandler
#define | sEE_I2C_DMA_TX_IRQn DMA1_Channel6_IRQn
#define | sEE_I2C_DR_Address ((uint32_t)0x40005410)
#define | sEE_I2C_SCL_AF GPIO_AF_I2C1
#define | sEE_I2C_SCL_GPIO_CLK RCC_AHBPeriph_GPIOB
#define | sEE_I2C_SCL_GPIO_PORT GPIOB
#define | sEE_I2C_SCL_PIN GPIO_Pin_6
#define | sEE_I2C_SCL_SOURCE GPIO_PinSource6
#define | sEE_I2C_SDA_AF GPIO_AF_I2C1
#define | sEE_I2C_SDA_GPIO_CLK RCC_AHBPeriph_GPIOB
#define | sEE_I2C_SDA_GPIO_PORT GPIOB
#define | sEE_I2C_SDA_PIN GPIO_Pin_7
#define | sEE_I2C_SDA_SOURCE GPIO_PinSource7
#define | sEE_M24C64_32
#define | sEE_TIME_CONST 24
#define | sEE_USE_DMA
#define | SEL_BUTTON_EXTI_IRQn EXTI9_5_IRQn
#define | SEL_BUTTON_EXTI_LINE EXTI_Line8
#define | SEL_BUTTON_EXTI_PIN_SOURCE EXTI_PinSource8
#define | SEL_BUTTON_EXTI_PORT_SOURCE EXTI_PortSourceGPIOE
#define | SEL_BUTTON_GPIO_CLK RCC_AHBPeriph_GPIOE
#define | SEL_BUTTON_GPIO_PORT GPIOE
#define | SEL_BUTTON_PIN GPIO_Pin_8
Joystick Sel push-button.
#define | UP_BUTTON_EXTI_IRQn EXTI9_5_IRQn
#define | UP_BUTTON_EXTI_LINE EXTI_Line9
#define | UP_BUTTON_EXTI_PIN_SOURCE EXTI_PinSource9
#define | UP_BUTTON_EXTI_PORT_SOURCE EXTI_PortSourceGPIOE
#define | UP_BUTTON_GPIO_CLK RCC_AHBPeriph_GPIOE
#define | UP_BUTTON_GPIO_PORT GPIOE
#define | UP_BUTTON_PIN GPIO_Pin_9
Joystick Up push-button.

Functions

void | LM75_LowLevel_DeInit (void)
DeInitializes the LM75_I2C.
void | LM75_LowLevel_Init (void)
Initializes the LM75_I2C.
void | SD_LowLevel_DeInit (void)
DeInitializes the SD/SD communication.
void | SD_LowLevel_Init (void)
Initializes the SD_SPI and CS pins.
void | sEE_LowLevel_DeInit (void)
DeInitializes peripherals used by the I2C EEPROM driver.
void | sEE_LowLevel_DMAConfig (uint32_t pBuffer, uint32_t BufferSize, uint32_t Direction)
Initializes DMA channel used by the I2C EEPROM driver.
void | sEE_LowLevel_Init (void)
Initializes peripherals used by the I2C EEPROM driver.
void | STM_EVAL_COMInit (COM_TypeDef COM, USART_InitTypeDef *USART_InitStruct)
Configures COM port.
void | STM_EVAL_LEDInit (Led_TypeDef Led)
Configures LED GPIO.
void | STM_EVAL_LEDOff (Led_TypeDef Led)
Turns selected LED Off.
void | STM_EVAL_LEDOn (Led_TypeDef Led)
Turns selected LED On.
void | STM_EVAL_LEDToggle (Led_TypeDef Led)
Toggles the selected LED.
uint32_t | STM_EVAL_PBGetState (Button_TypeDef Button)
Returns the selected Button state.
void | STM_EVAL_PBInit (Button_TypeDef Button, ButtonMode_TypeDef Button_Mode)
Configures Button GPIO and EXTI Line.

Detailed Description

This file contains definitions for STM32L152_EVAL's Leds, push-buttons and COM ports hardware resources.

Author:
MCD Application Team
Version:
V4.5.0
Date:
07-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm32l152_eval.h.


STM32F10x Standard Peripherals Firmware Library: stm32l152_eval_glass_lcd.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • STM32L152_EVAL
Functions | Variables

stm32l152_eval_glass_lcd.c File Reference

This file includes the LCD Glass driver for Pacific Display (LCD_PD878, PD878-DP-FH-W-LV-6-RH) Module of STM32L152-EVAL board RevB. More...

#include "stm32l152_eval_glass_lcd.h"

Go to the source code of this file.

Functions

static void | Convert (uint8_t *c, Point_Typedef point, Apostrophe_Typedef apostrophe)
Converts an ascii char to an LCD digit.
static void | delay (__IO uint32_t nCount)
Inserts a delay time.
void | LCD_GLASS_Clear (void)
This function Clear the whole LCD RAM.
void | LCD_GLASS_ClearChar (uint8_t position)
This function Clear a char in the LCD RAM.
void | LCD_GLASS_DisplayChar (uint8_t *ch, Point_Typedef point, Apostrophe_Typedef apostrophe, uint8_t position)
This function writes a char in the LCD RAM.
void | LCD_GLASS_DisplayString (uint8_t *ptr)
This function writes a char in the LCD RAM.
void | LCD_GLASS_Init (void)
Configures the LCD GLASS relative GPIO port IOs and LCD peripheral.
void | LCD_GLASS_ScrollString (uint8_t *ptr, uint16_t nScroll, uint16_t ScrollSpeed)
Display a string in scrolling mode.
void | LCD_GLASS_WriteChar (uint8_t *ch, Point_Typedef point, Apostrophe_Typedef apostrophe, uint8_t position)
This function writes a char in the LCD RAM.
static void | LCD_GPIOConfig (void)
Configures the LCD Segments and Coms GPIOs.

Variables

uint8_t | digit [4]
LETTERS AND NUMBERS MAPPING DEFINITION.
__I uint16_t | LetterMap [26]
__I uint16_t | mask [4] = {0xF000, 0x0F00, 0x00F0, 0x000F}
__I uint16_t | NumberMap [10]
__I uint8_t | shift [4] = {0x0C, 0x08, 0x04, 0x00}

Detailed Description

This file includes the LCD Glass driver for Pacific Display (LCD_PD878, PD878-DP-FH-W-LV-6-RH) Module of STM32L152-EVAL board RevB.

Author:
MCD Application Team
Version:
V4.5.0
Date:
07-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm32l152_eval_glass_lcd.c.


STM32F10x Standard Peripherals Firmware Library: stm32l152_eval_glass_lcd.h File Reference

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
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  • STM32L152_EVAL
Enumerations | Functions

stm32l152_eval_glass_lcd.h File Reference

Header file for stm32l152_eval_glass_lcd.c module. More...

#include "stm32l1xx.h"

Go to the source code of this file.

Enumerations

enum | Apostrophe_Typedef { APOSTROPHE_OFF = 0, APOSTROPHE_ON = 1 }
enum | Point_Typedef { POINT_OFF = 0, POINT_ON = 1 }

Functions

void | LCD_GLASS_Clear (void)
This function Clear the whole LCD RAM.
void | LCD_GLASS_ClearChar (uint8_t position)
This function Clear a char in the LCD RAM.
void | LCD_GLASS_DisplayChar (uint8_t *ch, Point_Typedef point, Apostrophe_Typedef apostrophe, uint8_t position)
This function writes a char in the LCD RAM.
void | LCD_GLASS_DisplayString (uint8_t *ptr)
This function writes a char in the LCD RAM.
void | LCD_GLASS_Init (void)
Configures the LCD GLASS relative GPIO port IOs and LCD peripheral.
void | LCD_GLASS_ScrollString (uint8_t *ptr, uint16_t nScroll, uint16_t ScrollSpeed)
Display a string in scrolling mode.
void | LCD_GLASS_WriteChar (uint8_t *ch, Point_Typedef point, Apostrophe_Typedef apostrophe, uint8_t position)
This function writes a char in the LCD RAM.

Detailed Description

Header file for stm32l152_eval_glass_lcd.c module.

Author:
MCD Application Team
Version:
V4.5.0
Date:
07-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm32l152_eval_glass_lcd.h.


STM32F10x Standard Peripherals Firmware Library: stm32l152_eval_i2c_ee.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • STM32L152_EVAL
Functions | Variables

stm32l152_eval_i2c_ee.c File Reference

This file provides a set of functions needed to manage an I2C M24CXX EEPROM memory. More...

#include "stm32l152_eval_i2c_ee.h"

Go to the source code of this file.

Functions

void | sEE_DeInit (void)
DeInitializes peripherals used by the I2C EEPROM driver.
void | sEE_I2C_DMA_RX_IRQHandler (void)
This function handles the DMA Rx Channel interrupt Handler.
void | sEE_I2C_DMA_TX_IRQHandler (void)
This function handles the DMA Tx Channel interrupt Handler.
void | sEE_Init (void)
Initializes peripherals used by the I2C EEPROM driver.
uint32_t | sEE_ReadBuffer (uint8_t *pBuffer, uint16_t ReadAddr, uint16_t *NumByteToRead)
Reads a block of data from the EEPROM.
uint32_t | sEE_WaitEepromStandbyState (void)
Wait for EEPROM Standby state.
void | sEE_WriteBuffer (uint8_t *pBuffer, uint16_t WriteAddr, uint16_t NumByteToWrite)
Writes buffer of data to the I2C EEPROM.
uint32_t | sEE_WritePage (uint8_t *pBuffer, uint16_t WriteAddr, uint8_t *NumByteToWrite)
Writes more than one byte to the EEPROM with a single WRITE cycle.

Variables

__IO uint16_t | sEEAddress = 0
__IO uint8_t | sEEDataNum
__IO uint16_t * | sEEDataReadPointer
__IO uint8_t * | sEEDataWritePointer
__IO uint32_t | sEETimeout = sEE_LONG_TIMEOUT

Detailed Description

This file provides a set of functions needed to manage an I2C M24CXX EEPROM memory.

Author:
MCD Application Team
Version:
V4.5.0
Date:
07-March-2011 =================================================================== Notes:
  • This driver is intended for STM32L1xx families devices only.
  • There is no I2C EEPROM memory available in STM32L152-EVAL board, to use this driver you have to build your own hardware. ===================================================================

It implements a high level communication layer for read and write from/to this memory. The needed STM32 hardware resources (I2C and GPIO) are defined in stm32l152_eval.h file, and the initialization is performed in sEE_LowLevel_Init() function declared in stm32l152_eval.c file. You can easily tailor this driver to any other development board, by just adapting the defines for hardware resources and sEE_LowLevel_Init() function.

Note:
In this driver, basic read and write functions (sEE_ReadBuffer() and sEE_WritePage()) use the DMA to perform the data transfer to/from EEPROM memory (except when number of requested data is equal to 1). Thus, after calling these two functions, user application may perform other tasks while DMA is transferring data. The application should then monitor the variable holding the number of data in order to determine when the transfer is completed (variable decremented to 0). Stopping transfer tasks are performed into DMA interrupt handlers (which are integrated into this driver).

+-----------------------------------------------------------------+ | Pin assignment | +---------------------------------------+-----------+-------------+ | STM32 I2C Pins | sEE | Pin | +---------------------------------------+-----------+-------------+ | . | E0(GND) | 1 (0V) | | . | E1(GND) | 2 (0V) | | . | E2(GND) | 3 (0V) | | . | E0(VSS) | 4 (0V) | | sEE_I2C_SDA_PIN/ SDA | SDA | 5 | | sEE_I2C_SCL_PIN/ SCL | SCL | 6 | | . | /WC(VDD)| 7 (3.3V) | | . | VDD | 8 (3.3V) | +---------------------------------------+-----------+-------------+

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm32l152_eval_i2c_ee.c.


STM32F10x Standard Peripherals Firmware Library: stm32l152_eval_i2c_ee.h File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • STM32L152_EVAL
Defines | Functions

stm32l152_eval_i2c_ee.h File Reference

This file contains all the functions prototypes for the stm32l152_eval_i2c_ee firmware driver. More...

#include "stm32_eval.h"

Go to the source code of this file.

Defines

#define | I2C_SLAVE_ADDRESS7 0xA0
#define | I2C_SPEED 200000
#define | sEE_FAIL 1
#define | sEE_FLAG_TIMEOUT ((uint32_t)0x1000)
#define | sEE_LONG_TIMEOUT ((uint32_t)(10 * sEE_FLAG_TIMEOUT))
#define | sEE_M24C64_32
#define | sEE_MAX_TRIALS_NUMBER 300
#define | sEE_OK 0
#define | sEE_STATE_BUSY 1
#define | sEE_STATE_ERROR 2
#define | sEE_STATE_READY 0

Functions

void | sEE_DeInit (void)
DeInitializes peripherals used by the I2C EEPROM driver.
void | sEE_Init (void)
Initializes peripherals used by the I2C EEPROM driver.
uint32_t | sEE_ReadBuffer (uint8_t *pBuffer, uint16_t ReadAddr, uint16_t *NumByteToRead)
Reads a block of data from the EEPROM.
uint32_t | sEE_TIMEOUT_UserCallback (void)
Example of timeout situation management.
uint32_t | sEE_WaitEepromStandbyState (void)
Wait for EEPROM Standby state.
void | sEE_WriteBuffer (uint8_t *pBuffer, uint16_t WriteAddr, uint16_t NumByteToWrite)
Writes buffer of data to the I2C EEPROM.
uint32_t | sEE_WritePage (uint8_t *pBuffer, uint16_t WriteAddr, uint8_t *NumByteToWrite)
Writes more than one byte to the EEPROM with a single WRITE cycle.

Detailed Description

This file contains all the functions prototypes for the stm32l152_eval_i2c_ee firmware driver.

Author:
MCD Application Team
Version:
V4.5.0
Date:
07-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm32l152_eval_i2c_ee.h.


STM32F10x Standard Peripherals Firmware Library: stm32l152_eval_lcd.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • STM32L152_EVAL
Defines | Functions | Variables

stm32l152_eval_lcd.c File Reference

This file includes the LCD driver for AM-240320L8TNQW00H (LCD_ILI9320), AM-240320LDTNQW00H (LCD_SPFD5408B) Liquid Crystal Display Module of STM32L152-EVAL board RevB. More...

#include "stm32l152_eval_lcd.h"
#include "../Common/fonts.c"

Go to the source code of this file.

Defines

#define | ABS(X) ((X) > 0 ? (X) : -(X))
#define | LCD_ILI9320 0x9320
#define | LCD_READ_REG 0x03
#define | LCD_SPFD5408 0x5408
#define | LCD_WRITE_REG 0x02
#define | MAX_POLY_CORNERS 200
#define | POLY_X(Z) ((int32_t)((Points + Z)->Y))
#define | POLY_Y(Z) ((int32_t)((Points + Z)->X))
#define | READ_STATUS 0x01
#define | SET_INDEX 0x00
#define | START_BYTE 0x70

Functions

static void | delay (__IO uint32_t nCount)
Inserts a delay time.
static void | delay (__IO uint32_t nCount)
Inserts a delay time.
void | LCD_Clear (uint16_t Color)
Clears the hole LCD.
void | LCD_ClearLine (uint8_t Line)
Clears the selected line.
void | LCD_ClosedPolyLine (pPoint Points, uint16_t PointCount)
Displays a closed polyline (between many points).
void | LCD_ClosedPolyLineRelative (pPoint Points, uint16_t PointCount)
Displays a closed relative polyline (between many points).
void | LCD_CtrlLinesConfig (void)
Configures LCD control lines in Output Push-Pull mode.
void | LCD_CtrlLinesWrite (GPIO_TypeDef *GPIOx, uint16_t CtrlPins, BitAction BitVal)
Sets or reset LCD control lines.
void | LCD_DisplayChar (uint8_t Line, uint16_t Column, uint8_t Ascii)
Displays one character (16dots width, 24dots height).
void | LCD_DisplayOff (void)
Disables the Display.
void | LCD_DisplayOn (void)
Enables the Display.
void | LCD_DisplayStringLine (uint8_t Line, uint8_t *ptr)
Displays a maximum of 20 char on the LCD.
void | LCD_DrawChar (uint8_t Xpos, uint16_t Ypos, const uint16_t *c)
Draws a character on LCD.
void | LCD_DrawCircle (uint8_t Xpos, uint16_t Ypos, uint16_t Radius)
Displays a circle.
void | LCD_DrawFullCircle (uint16_t Xpos, uint16_t Ypos, uint16_t Radius)
Displays a full circle.
void | LCD_DrawFullRect (uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height)
Displays a full rectangle.
void | LCD_DrawLine (uint8_t Xpos, uint16_t Ypos, uint16_t Length, uint8_t Direction)
Displays a line.
void | LCD_DrawMonoPict (const uint32_t *Pict)
Displays a monocolor picture.
void | LCD_DrawRect (uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width)
Displays a rectangle.
void | LCD_DrawUniLine (uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2)
Displays an uni line (between two points).
void | LCD_FillPolyLine (pPoint Points, uint16_t PointCount)
Displays a full polyline (between many points).
void | LCD_GetColors (__IO uint16_t *_TextColor, __IO uint16_t *_BackColor)
Gets the LCD Text and Background colors.
sFONT * | LCD_GetFont (void)
Gets the Text Font.
void | LCD_nCS_StartByte (uint8_t Start_Byte)
Reset LCD control line(/CS) and Send Start-Byte.
void | LCD_PolyLine (pPoint Points, uint16_t PointCount)
Displays an polyline (between many points).
void | LCD_PolyLineRelative (pPoint Points, uint16_t PointCount)
Displays a relative polyline (between many points).
static void | LCD_PolyLineRelativeClosed (pPoint Points, uint16_t PointCount, uint16_t Closed)
Displays an relative polyline (between many points).
void | LCD_PowerOn (void)
Power on the LCD.
uint16_t | LCD_ReadReg (uint8_t LCD_Reg)
Reads the selected LCD Register.
void | LCD_SetBackColor (__IO uint16_t Color)
Sets the Background color.
void | LCD_SetColors (__IO uint16_t _TextColor, __IO uint16_t _BackColor)
Sets the LCD Text and Background colors.
void | LCD_SetCursor (uint8_t Xpos, uint16_t Ypos)
Sets the cursor position.
void | LCD_SetDisplayWindow (uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width)
Sets a display window.
void | LCD_SetFont (sFONT *fonts)
Sets the Text Font.
void | LCD_SetTextColor (__IO uint16_t Color)
Sets the Text color.
void | LCD_Setup (void)
Setups the LCD.
void | LCD_SPIConfig (void)
Configures the LCD_SPI interface.
void | LCD_WindowModeDisable (void)
Disables LCD Window mode.
void | LCD_WriteRAM (uint16_t RGB_Code)
Writes to the LCD RAM.
void | LCD_WriteRAM_Prepare (void)
Prepare to write to the LCD RAM.
void | LCD_WriteRAMWord (uint16_t RGB_Code)
Writes 1 word to the LCD RAM.
void | LCD_WriteReg (uint8_t LCD_Reg, uint16_t LCD_RegValue)
Writes to the selected LCD ILI9320 register.
void | LCD_WriteRegIndex (uint8_t LCD_Reg)
Writes index to select the LCD register.
static void | PutPixel (int16_t x, int16_t y)
Displays a pixel.
void | STM32L152_LCD_DeInit (void)
DeInitializes the LCD.
void | STM32L152_LCD_Init (void)
Initializes the LCD.

Variables

static __IO uint16_t | BackColor = 0xFFFF
static sFONT * | LCD_Currentfonts
static __IO uint32_t | LCDType = LCD_SPFD5408
static __IO uint16_t | TextColor = 0x0000

Detailed Description

This file includes the LCD driver for AM-240320L8TNQW00H (LCD_ILI9320), AM-240320LDTNQW00H (LCD_SPFD5408B) Liquid Crystal Display Module of STM32L152-EVAL board RevB.

Author:
MCD Application Team
Version:
V4.5.0
Date:
07-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm32l152_eval_lcd.c.


STM32F10x Standard Peripherals Firmware Library: stm32l152_eval_lcd.h File Reference

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
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  • STM32L152_EVAL
Data Structures | Defines | Typedefs | Functions

stm32l152_eval_lcd.h File Reference

This file contains all the functions prototypes for the stm32l152_eval_lcd firmware driver. More...

#include "stm32l1xx.h"
#include "../Common/fonts.h"

Go to the source code of this file.

Data Structures

struct | Point

Defines

#define | _delay_ delay
Uncomment the line below if you want to use LCD_DrawBMP function to display a bitmap picture on the LCD.
#define | ASSEMBLE_RGB(R, G, B) ((((R)& 0xF8) << 8) | (((G) & 0xFC) << 3) | (((B) & 0xF8) >> 3))
#define | LCD_COLOR_BLACK 0x0000
#define | LCD_COLOR_BLUE 0x001F
#define | LCD_COLOR_BLUE2 0x051F
#define | LCD_COLOR_CYAN 0x7FFF
#define | LCD_COLOR_GREEN 0x07E0
#define | LCD_COLOR_GREY 0xF7DE
#define | LCD_COLOR_MAGENTA 0xF81F
#define | LCD_COLOR_RED 0xF800
#define | LCD_COLOR_WHITE 0xFFFF
LCD color.
#define | LCD_COLOR_YELLOW 0xFFE0
#define | LCD_DEFAULT_FONT Font16x24
LCD default font.
#define | LCD_DIR_HORIZONTAL 0x0000
LCD Direction.
#define | LCD_DIR_VERTICAL 0x0001
#define | LCD_LINE_0 LINE(0)
LCD Lines depending on the chosen fonts.
#define | LCD_LINE_1 LINE(1)
#define | LCD_LINE_10 LINE(10)
#define | LCD_LINE_11 LINE(11)
#define | LCD_LINE_12 LINE(12)
#define | LCD_LINE_13 LINE(13)
#define | LCD_LINE_14 LINE(14)
#define | LCD_LINE_15 LINE(15)
#define | LCD_LINE_16 LINE(16)
#define | LCD_LINE_17 LINE(17)
#define | LCD_LINE_18 LINE(18)
#define | LCD_LINE_19 LINE(19)
#define | LCD_LINE_2 LINE(2)
#define | LCD_LINE_20 LINE(20)
#define | LCD_LINE_21 LINE(21)
#define | LCD_LINE_22 LINE(22)
#define | LCD_LINE_23 LINE(23)
#define | LCD_LINE_24 LINE(24)
#define | LCD_LINE_25 LINE(25)
#define | LCD_LINE_26 LINE(26)
#define | LCD_LINE_27 LINE(27)
#define | LCD_LINE_28 LINE(28)
#define | LCD_LINE_29 LINE(29)
#define | LCD_LINE_3 LINE(3)
#define | LCD_LINE_4 LINE(4)
#define | LCD_LINE_5 LINE(5)
#define | LCD_LINE_6 LINE(6)
#define | LCD_LINE_7 LINE(7)
#define | LCD_LINE_8 LINE(8)
#define | LCD_LINE_9 LINE(9)
#define | LCD_NCS_GPIO_CLK RCC_AHBPeriph_GPIOH
#define | LCD_NCS_GPIO_PORT GPIOH
#define | LCD_NCS_PIN GPIO_Pin_2
LCD Control pins.
#define | LCD_PIXEL_HEIGHT 0x00F0
#define | LCD_PIXEL_WIDTH 0x0140
LCD Size (Width and Height)
#define | LCD_REG_0 0x00
LCD Registers.
#define | LCD_REG_1 0x01
#define | LCD_REG_10 0x0A
#define | LCD_REG_106 0x6A
#define | LCD_REG_118 0x76
#define | LCD_REG_12 0x0C
#define | LCD_REG_128 0x80
#define | LCD_REG_129 0x81
#define | LCD_REG_13 0x0D
#define | LCD_REG_130 0x82
#define | LCD_REG_131 0x83
#define | LCD_REG_132 0x84
#define | LCD_REG_133 0x85
#define | LCD_REG_134 0x86
#define | LCD_REG_135 0x87
#define | LCD_REG_136 0x88
#define | LCD_REG_137 0x89
#define | LCD_REG_139 0x8B
#define | LCD_REG_14 0x0E
#define | LCD_REG_140 0x8C
#define | LCD_REG_141 0x8D
#define | LCD_REG_143 0x8F
#define | LCD_REG_144 0x90
#define | LCD_REG_145 0x91
#define | LCD_REG_146 0x92
#define | LCD_REG_147 0x93
#define | LCD_REG_148 0x94
#define | LCD_REG_149 0x95
#define | LCD_REG_15 0x0F
#define | LCD_REG_150 0x96
#define | LCD_REG_151 0x97
#define | LCD_REG_152 0x98
#define | LCD_REG_153 0x99
#define | LCD_REG_154 0x9A
#define | LCD_REG_157 0x9D
#define | LCD_REG_16 0x10
#define | LCD_REG_17 0x11
#define | LCD_REG_18 0x12
#define | LCD_REG_19 0x13
#define | LCD_REG_192 0xC0
#define | LCD_REG_193 0xC1
#define | LCD_REG_2 0x02
#define | LCD_REG_20 0x14
#define | LCD_REG_21 0x15
#define | LCD_REG_22 0x16
#define | LCD_REG_227 0xE3
#define | LCD_REG_229 0xE5
#define | LCD_REG_23 0x17
#define | LCD_REG_231 0xE7
#define | LCD_REG_239 0xEF
#define | LCD_REG_24 0x18
#define | LCD_REG_25 0x19
#define | LCD_REG_26 0x1A
#define | LCD_REG_27 0x1B
#define | LCD_REG_28 0x1C
#define | LCD_REG_29 0x1D
#define | LCD_REG_3 0x03
#define | LCD_REG_30 0x1E
#define | LCD_REG_31 0x1F
#define | LCD_REG_32 0x20
#define | LCD_REG_33 0x21
#define | LCD_REG_34 0x22
#define | LCD_REG_36 0x24
#define | LCD_REG_37 0x25
#define | LCD_REG_4 0x04
#define | LCD_REG_40 0x28
#define | LCD_REG_41 0x29
#define | LCD_REG_43 0x2B
#define | LCD_REG_45 0x2D
#define | LCD_REG_48 0x30
#define | LCD_REG_49 0x31
#define | LCD_REG_5 0x05
#define | LCD_REG_50 0x32
#define | LCD_REG_51 0x33
#define | LCD_REG_52 0x34
#define | LCD_REG_53 0x35
#define | LCD_REG_54 0x36
#define | LCD_REG_55 0x37
#define | LCD_REG_56 0x38
#define | LCD_REG_57 0x39
#define | LCD_REG_59 0x3B
#define | LCD_REG_6 0x06
#define | LCD_REG_60 0x3C
#define | LCD_REG_61 0x3D
#define | LCD_REG_62 0x3E
#define | LCD_REG_63 0x3F
#define | LCD_REG_64 0x40
#define | LCD_REG_65 0x41
#define | LCD_REG_66 0x42
#define | LCD_REG_67 0x43
#define | LCD_REG_68 0x44
#define | LCD_REG_69 0x45
#define | LCD_REG_7 0x07
#define | LCD_REG_70 0x46
#define | LCD_REG_71 0x47
#define | LCD_REG_72 0x48
#define | LCD_REG_73 0x49
#define | LCD_REG_74 0x4A
#define | LCD_REG_75 0x4B
#define | LCD_REG_76 0x4C
#define | LCD_REG_77 0x4D
#define | LCD_REG_78 0x4E
#define | LCD_REG_79 0x4F
#define | LCD_REG_8 0x08
#define | LCD_REG_80 0x50
#define | LCD_REG_81 0x51
#define | LCD_REG_82 0x52
#define | LCD_REG_83 0x53
#define | LCD_REG_9 0x09
#define | LCD_REG_96 0x60
#define | LCD_REG_97 0x61
#define | LCD_SPI SPI1
#define | LCD_SPI_CLK RCC_APB2Periph_SPI1
#define | LCD_SPI_MISO_AF GPIO_AF_SPI1
#define | LCD_SPI_MISO_GPIO_CLK RCC_AHBPeriph_GPIOE
#define | LCD_SPI_MISO_GPIO_PORT GPIOE
#define | LCD_SPI_MISO_PIN GPIO_Pin_14
#define | LCD_SPI_MISO_SOURCE GPIO_PinSource14
#define | LCD_SPI_MOSI_AF GPIO_AF_SPI1
#define | LCD_SPI_MOSI_GPIO_CLK RCC_AHBPeriph_GPIOE
#define | LCD_SPI_MOSI_GPIO_PORT GPIOE
#define | LCD_SPI_MOSI_PIN GPIO_Pin_15
#define | LCD_SPI_MOSI_SOURCE GPIO_PinSource15
#define | LCD_SPI_SCK_AF GPIO_AF_SPI1
#define | LCD_SPI_SCK_GPIO_CLK RCC_AHBPeriph_GPIOE
#define | LCD_SPI_SCK_GPIO_PORT GPIOE
#define | LCD_SPI_SCK_PIN GPIO_Pin_13
LCD SPI Interface pins.
#define | LCD_SPI_SCK_SOURCE GPIO_PinSource13

Typedefs

typedef struct Point * | pPoint

Functions

void | LCD_Clear (uint16_t Color)
Clears the hole LCD.
void | LCD_ClearLine (uint8_t Line)
Clears the selected line.
void | LCD_ClosedPolyLine (pPoint Points, uint16_t PointCount)
Displays a closed polyline (between many points).
void | LCD_ClosedPolyLineRelative (pPoint Points, uint16_t PointCount)
Displays a closed relative polyline (between many points).
void | LCD_CtrlLinesConfig (void)
Configures LCD control lines in Output Push-Pull mode.
void | LCD_CtrlLinesWrite (GPIO_TypeDef *GPIOx, uint16_t CtrlPins, BitAction BitVal)
Sets or reset LCD control lines.
void | LCD_DisplayChar (uint8_t Line, uint16_t Column, uint8_t Ascii)
Displays one character (16dots width, 24dots height).
void | LCD_DisplayOff (void)
Disables the Display.
void | LCD_DisplayOn (void)
Enables the Display.
void | LCD_DisplayStringLine (uint8_t Line, uint8_t *ptr)
Displays a maximum of 20 char on the LCD.
void | LCD_DrawBMP (uint32_t BmpAddress)
void | LCD_DrawChar (uint8_t Xpos, uint16_t Ypos, const uint16_t *c)
Draws a character on LCD.
void | LCD_DrawCircle (uint8_t Xpos, uint16_t Ypos, uint16_t Radius)
Displays a circle.
void | LCD_DrawFullCircle (uint16_t Xpos, uint16_t Ypos, uint16_t Radius)
Displays a full circle.
void | LCD_DrawFullRect (uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height)
Displays a full rectangle.
void | LCD_DrawLine (uint8_t Xpos, uint16_t Ypos, uint16_t Length, uint8_t Direction)
Displays a line.
void | LCD_DrawMonoPict (const uint32_t *Pict)
Displays a monocolor picture.
void | LCD_DrawRect (uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width)
Displays a rectangle.
void | LCD_DrawUniLine (uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2)
Displays an uni line (between two points).
void | LCD_FillPolyLine (pPoint Points, uint16_t PointCount)
Displays a full polyline (between many points).
void | LCD_GetColors (__IO uint16_t *_TextColor, __IO uint16_t *_BackColor)
Gets the LCD Text and Background colors.
sFONT * | LCD_GetFont (void)
Gets the Text Font.
void | LCD_nCS_StartByte (uint8_t Start_Byte)
Reset LCD control line(/CS) and Send Start-Byte.
void | LCD_PolyLine (pPoint Points, uint16_t PointCount)
Displays an polyline (between many points).
void | LCD_PolyLineRelative (pPoint Points, uint16_t PointCount)
Displays a relative polyline (between many points).
void | LCD_PowerOn (void)
Power on the LCD.
uint16_t | LCD_ReadReg (uint8_t LCD_Reg)
Reads the selected LCD Register.
void | LCD_SetBackColor (__IO uint16_t Color)
Sets the Background color.
void | LCD_SetColors (__IO uint16_t _TextColor, __IO uint16_t _BackColor)
Sets the LCD Text and Background colors.
void | LCD_SetCursor (uint8_t Xpos, uint16_t Ypos)
Sets the cursor position.
void | LCD_SetDisplayWindow (uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width)
Sets a display window.
void | LCD_SetFont (sFONT *fonts)
Sets the Text Font.
void | LCD_SetTextColor (__IO uint16_t Color)
Sets the Text color.
void | LCD_Setup (void)
Setups the LCD.
void | LCD_SPIConfig (void)
Configures the LCD_SPI interface.
void | LCD_WindowModeDisable (void)
Disables LCD Window mode.
void | LCD_WriteRAM (uint16_t RGB_Code)
Writes to the LCD RAM.
void | LCD_WriteRAM_Prepare (void)
Prepare to write to the LCD RAM.
void | LCD_WriteRAMWord (uint16_t RGB_Code)
Writes 1 word to the LCD RAM.
void | LCD_WriteReg (uint8_t LCD_Reg, uint16_t LCD_RegValue)
Writes to the selected LCD register.
void | LCD_WriteRegIndex (uint8_t LCD_Reg)
Writes index to select the LCD register.
void | STM32L152_LCD_DeInit (void)
DeInitializes the LCD.
void | STM32L152_LCD_Init (void)
Initializes the LCD.

Detailed Description

This file contains all the functions prototypes for the stm32l152_eval_lcd firmware driver.

Author:
MCD Application Team
Version:
V4.5.0
Date:
07-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file stm32l152_eval_lcd.h.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Libraries
  • CMSIS
  • CM3
  • DeviceSupport
  • ST
  • STM32F10x
Defines | Functions | Variables

Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.c File Reference

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClockTo72 (void)
Setup the external memory controller.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = SYSCLK_FREQ_72MHz


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • ADC
  • 3ADCs_DMA
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_56MHz 56000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClockTo56 (void)
Setup the external memory controller.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = SYSCLK_FREQ_56MHz

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • ADC
  • ADC1_DMA
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_56MHz 56000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • ADC
  • AnalogWatchdog
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_56MHz 56000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • ADC
  • ExtLinesTrigger
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_56MHz 56000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • ADC
  • RegSimul_DualMode
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_56MHz 56000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • ADC
  • TIMTrigger_AutoInjection
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_56MHz 56000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • BKP
  • Backup_Data
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/BKP/Backup_Data/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/BKP/Backup_Data/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • BKP
  • Tamper
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/BKP/Tamper/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/BKP/Tamper/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • CAN
  • DualCAN
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/CAN/DualCAN/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/CAN/DualCAN/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • CAN
  • LoopBack
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/CAN/LoopBack/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/CAN/LoopBack/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • CAN
  • Networking
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/CAN/Networking/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/CAN/Networking/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • CEC
  • DataExchangeInterrupt
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • CortexM3
  • BitBand
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/CortexM3/BitBand/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/CortexM3/BitBand/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • CortexM3
  • Mode_Privilege
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • CortexM3
  • MPU
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/CortexM3/MPU/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/CortexM3/MPU/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • CRC
  • CRC_Calculation
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • DAC
  • DualModeDMA_SineWave
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • DAC
  • OneChannel_NoiseWave
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • DAC
  • OneChannelDMA_Escalator
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • DAC
  • TwoChannels_TriangleWave
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • DMA
  • ADC_TIM1
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • DMA
  • FLASH_RAM
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • DMA
  • FSMC
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/DMA/FSMC/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/DMA/FSMC/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • DMA
  • I2C_RAM
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • DMA
  • SPI_RAM
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • EXTI
  • EXTI_Config
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • FLASH
  • Dual_Boot
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
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  • STM32F10x_StdPeriph_Examples
  • FLASH
  • Program
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/FLASH/Program/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/FLASH/Program/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • FLASH
  • Write_Protection
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • FSMC
  • NAND
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/FSMC/NAND/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/FSMC/NAND/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • FSMC
  • NOR
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/FSMC/NOR/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/FSMC/NOR/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • FSMC
  • NOR_CodeExecute
  • binary
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • FSMC
  • NOR_CodeExecute
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • FSMC
  • OneNAND
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/FSMC/OneNAND/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/FSMC/OneNAND/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • FSMC
  • SRAM
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • FSMC
  • SRAM_DataMemory
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • GPIO
  • IOToggle
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/GPIO/IOToggle/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/GPIO/IOToggle/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • GPIO
  • JTAG_Remap
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • I2C
  • EEPROM
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/I2C/EEPROM/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/I2C/EEPROM/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • I2C
  • I2C_TSENSOR
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • I2C
  • IOExpander
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/I2C/IOExpander/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/I2C/IOExpander/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • I2S
  • Interrupt
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/I2S/Interrupt/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/I2S/Interrupt/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • I2S
  • SPI_I2S_Switch
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • IWDG
  • IWDG_Reset
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • Lib_DEBUG
  • RunTime_Check
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • NVIC
  • DMA_WFIMode
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • NVIC
  • IRQ_Mask
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • NVIC
  • IRQ_Priority
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • NVIC
  • VectorTable_Relocation
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x3000

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • PWR
  • PVD
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/PWR/PVD/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/PWR/PVD/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • PWR
  • STANDBY
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/PWR/STANDBY/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/PWR/STANDBY/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • PWR
  • STOP
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/PWR/STOP/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/PWR/STOP/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • RCC
  • RCC_ClockConfig
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • RTC
  • Calendar
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/RTC/Calendar/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/RTC/Calendar/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • RTC
  • LSI_Calib
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • SDIO
  • uSDCard
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/SDIO/uSDCard/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/SDIO/uSDCard/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • SPI
  • CRC
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/SPI/CRC/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/SPI/CRC/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • SPI
  • DMA
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/SPI/DMA/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/SPI/DMA/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • SPI
  • FullDuplex_SoftNSS
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • SPI
  • Simplex_Interrupt
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • SPI
  • SPI_FLASH
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • SysTick
  • TimeBase
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/SysTick/TimeBase/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/SysTick/TimeBase/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • TIM
  • 6Steps
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/TIM/6Steps/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/TIM/6Steps/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • TIM
  • 7PWM_Output
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • TIM
  • Cascade_Synchro
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • TIM
  • ComplementarySignals
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • TIM
  • DMA
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/TIM/DMA/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/TIM/DMA/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
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  • DMABurst
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/TIM/DMABurst/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/TIM/DMABurst/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
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  • ExtTrigger_Synchro
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • TIM
  • InputCapture
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/TIM/InputCapture/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/TIM/InputCapture/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • TIM
  • OCActive
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/TIM/OCActive/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/TIM/OCActive/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • TIM
  • OCInactive
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/TIM/OCInactive/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/TIM/OCInactive/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • TIM
  • OCToggle
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/TIM/OCToggle/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/TIM/OCToggle/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • TIM
  • OnePulse
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/TIM/OnePulse/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/TIM/OnePulse/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • TIM
  • Parallel_Synchro
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • TIM
  • PWM_Input
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Input/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Input/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • TIM
  • PWM_Output
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Output/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Output/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • TIM
  • TIM10_PWMOutput
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • TIM
  • TIM15_ComplementarySignals
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • TIM
  • TIM1_Synchro
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • TIM
  • TIM9_OCToggle
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • TIM
  • TimeBase
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/TIM/TimeBase/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/TIM/TimeBase/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • USART
  • DMA_Interrupt
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • USART
  • DMA_Polling
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/USART/DMA_Polling/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/USART/DMA_Polling/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • USART
  • HalfDuplex
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/USART/HalfDuplex/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/USART/HalfDuplex/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • USART
  • HyperTerminal_HwFlowControl
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • USART
  • HyperTerminal_Interrupt
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • USART
  • Interrupt
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/USART/Interrupt/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/USART/Interrupt/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • USART
  • IrDA
  • Receive
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • USART
  • IrDA
  • Transmit
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • USART
  • MultiProcessor
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/USART/MultiProcessor/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/USART/MultiProcessor/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
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  • USART
  • Polling
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/USART/Polling/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/USART/Polling/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
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  • Printf
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/USART/Printf/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/USART/Printf/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
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  • USART
  • Smartcard
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/USART/Smartcard/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/USART/Smartcard/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • USART
  • Synchronous
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/USART/Synchronous/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/USART/Synchronous/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
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  • WWDG
  • WWDG_Reset
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/system_stm32f10x.c File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. More...

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
08-April-2011 1. This file provides two functions and one global variable to be called from user application:
  • SystemInit(): Setups the system clock (System clock source, PLL Multiplier factors, AHB/APBx prescalers and Flash settings). This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f10x_xx.s" file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file Project/STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/system_stm32f10x.c.


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c File Reference

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  • STM32F10x_StdPeriph_Lib_V3.5.0
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  • STM32F10x_StdPeriph_Template
Defines | Functions | Variables

Project/STM32F10x_StdPeriph_Template/system_stm32f10x.c File Reference

#include "stm32f10x.h"

Go to the source code of this file.

Defines

#define | SYSCLK_FREQ_72MHz 72000000
#define | VECT_TAB_OFFSET 0x0

Functions

static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
static void | SetSysClock (void)
Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

__I uint8_t | AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
uint32_t | SystemCoreClock = HSI_VALUE


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.h File Reference

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Libraries
  • CMSIS
  • CM3
  • DeviceSupport
  • ST
  • STM32F10x
Functions | Variables

system_stm32f10x.h File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer System Header File. More...

Go to the source code of this file.

Functions

void | SystemCoreClockUpdate (void)
Update SystemCoreClock variable according to Clock Register Values.
void | SystemInit (void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemCoreClock variable.

Variables

uint32_t | SystemCoreClock

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer System Header File.

Author:
MCD Application Team
Version:
V3.5.0
Date:
11-March-2011
Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2011 STMicroelectronics

Definition in file system_stm32f10x.h.


STM32F10x Standard Peripherals Firmware Library: Globals

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  • All
  • Functions
  • Variables
  • Typedefs
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- _ -

  • __CAN1_USED__ : STM32F10x_StdPeriph_Examples/CAN/LoopBack/main.c , STM32F10x_StdPeriph_Examples/CAN/Networking/main.c
  • __MPU_PRESENT : stm32f10x.h
  • __NVIC_PRIO_BITS : stm32f10x.h
  • __STM32F10X_STDPERIPH_VERSION : stm32f10x.h
  • __STM32F10X_STDPERIPH_VERSION_MAIN : stm32f10x.h
  • __STM32F10X_STDPERIPH_VERSION_RC : stm32f10x.h
  • __STM32F10X_STDPERIPH_VERSION_SUB1 : stm32f10x.h
  • __STM32F10X_STDPERIPH_VERSION_SUB2 : stm32f10x.h
  • __Vendor_SysTickConfig : stm32f10x.h
  • _delay_ : stm3210c_eval_ioe.h , stm32l152_eval_lcd.h , stm3210b_eval_lcd.h , stm3210e_eval_lcd.h , stm32100b_eval_lcd.h , stm32100e_eval_ioe.h , stm32100e_eval_lcd.h , stm3210c_eval_lcd.h


STM32F10x Standard Peripherals Firmware Library: accesspermission.c Source File

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  • Project
  • STM32F10x_StdPeriph_Examples
  • CortexM3
  • MPU

accesspermission.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    CortexM3/MPU/accesspermission.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Access rights configuration using Cortex-M3 MPU regions.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022
00023 /* Includes ------------------------------------------------------------------*/
00024 #include "main.h"
00025
00026 /** @addtogroup STM32F10x_StdPeriph_Examples
00027   * @{
00028   */
00029
00030 /** @addtogroup CortexM3_MPU
00031   * @{
00032   */
00033
00034 /* Private typedef -----------------------------------------------------------*/
00035 /* Private define ------------------------------------------------------------*/
00036 #define ARRAY_ADDRESS_START    (0x20002000UL)
00037 #define ARRAY_SIZE             (0x09UL << 0UL)
00038 #define ARRAY_REGION_NUMBER    (0x03UL << MPU_RNR_REGION_Pos)
00039
00040 /* Private macro -------------------------------------------------------------*/
00041 /* Private variables ---------------------------------------------------------*/
00042
00043 #if defined ( __CC_ARM   )
00044 uint8_t privilegedreadonlyarray[32] __attribute__((at(0x20002000)));
00045
00046 #elif defined ( __ICCARM__ )
00047 #pragma location=0x20002000
00048 __no_init uint8_t privilegedreadonlyarray[32];
00049
00050 #elif defined   (  __GNUC__  )
00051 uint8_t privilegedreadonlyarray[32] __attribute__((section(".ROarraySection")));
00052
00053 #elif defined   (  __TASKING__  )
00054 uint8_t privilegedreadonlyarray[32] __at(0x20002000);
00055 #endif
00056
00057 /* Private functions ---------------------------------------------------------*/
00058 /**
00059   * @brief  This function configure the access right using Cortex-M3 MPU regions.
00060   * @param  None
00061   * @retval None
00062   */
00063 void accesspermission(void)
00064 {
00065  uint8_t a;
00066
00067   /* Configure region for privilegedreadonlyarray as REGION NÝ3, 32byte and R
00068      only in privileged mode */
00069   MPU->RNR  = ARRAY_REGION_NUMBER;
00070   MPU->RBAR |= ARRAY_ADDRESS_START;
00071   MPU->RASR |= ARRAY_SIZE | portMPU_REGION_PRIVILEGED_READ_ONLY;
00072
00073   /* Read from privilegedreadonlyarray. This will not generate error */
00074   a = privilegedreadonlyarray[0];
00075
00076   /* Uncomment the following line to write to privilegedreadonlyarray. This will
00077      generate error */
00078   //privilegedreadonlyarray[0] = 'e';
00079
00080 }
00081
00082 /**
00083   * @}
00084   */
00085
00086 /**
00087   * @}
00088   */
00089
00090 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: Data Structures

  • Data Structures
  • Data Structure Index
  • Data Fields

Data Structures

Here are the data structures with brief descriptions:
_tFont |
ADC_InitTypeDef | ADC Init structure definition
ADC_TypeDef | Analog to Digital Converter
AFIO_TypeDef | Alternate Function I/O
BKP_TypeDef | Backup Registers
CAN_FIFOMailBox_TypeDef | Controller Area Network FIFOMailBox
CAN_FilterInitTypeDef | CAN filter init structure definition
CAN_FilterRegister_TypeDef | Controller Area Network FilterRegister
CAN_InitTypeDef | CAN init structure definition
CAN_TxMailBox_TypeDef | Controller Area Network TxMailBox
CAN_TypeDef | Controller Area Network
CanRxMsg | CAN Rx message structure definition
CanTxMsg | CAN Tx message structure definition
CEC_InitTypeDef | CEC Init structure definition
CEC_TypeDef | Consumer Electronics Control (CEC)
CRC_TypeDef | CRC calculation unit
DAC_InitTypeDef | DAC Init structure definition
DAC_TypeDef | Digital to Analog Converter
DBGMCU_TypeDef | Debug MCU
DMA_Channel_TypeDef | DMA Controller
DMA_InitTypeDef | DMA Init structure definition
DMA_TypeDef |
ETH_TypeDef | Ethernet MAC
EXTI_InitTypeDef | EXTI Init Structure definition
EXTI_TypeDef | External Interrupt/Event Controller
FLASH_TypeDef | FLASH Registers
FSMC_Bank1_TypeDef | Flexible Static Memory Controller
FSMC_Bank1E_TypeDef | Flexible Static Memory Controller Bank1E
FSMC_Bank2_TypeDef | Flexible Static Memory Controller Bank2
FSMC_Bank3_TypeDef | Flexible Static Memory Controller Bank3
FSMC_Bank4_TypeDef | Flexible Static Memory Controller Bank4
FSMC_NAND_PCCARDTimingInitTypeDef | Timing parameters For FSMC NAND and PCCARD Banks
FSMC_NANDInitTypeDef | FSMC NAND Init structure definition
FSMC_NORSRAMInitTypeDef | FSMC NOR/SRAM Init structure definition
FSMC_NORSRAMTimingInitTypeDef | Timing parameters For NOR/SRAM Banks
FSMC_PCCARDInitTypeDef | FSMC PCCARD Init structure definition
GPIO_InitTypeDef | GPIO Init structure definition
GPIO_TypeDef | General Purpose I/O
HDMI_CEC_Map |
HDMI_CEC_Message | CEC Init Structure definition
I2C_InitTypeDef | I2C Init structure definition
I2C_TypeDef | Inter Integrated Circuit Interface
I2S_InitTypeDef | I2S Init structure definition
IWDG_TypeDef | Independent WATCHDOG
LCD_TypeDef |
NAND_ADDRESS |
NAND_IDTypeDef |
NOR_IDTypeDef |
NVIC_InitTypeDef | NVIC Init Structure definition
OB_TypeDef | Option Bytes Registers
OneNAND_ADDRESS |
OneNAND_IDTypeDef |
Point |
PWR_TypeDef | Power Control
RCC_ClocksTypeDef |
RCC_TypeDef | Reset and Clock Control
RTC_TypeDef | Real-Time Clock
SC_ATR |
SD_CardInfo | SD Card information
SD_CardStatus | SD Card Status
SD_CID | Card Identification Data: CID Register
SD_CSD | Card Specific Data: CSD Register
SDIO_CmdInitTypeDef |
SDIO_DataInitTypeDef |
SDIO_InitTypeDef |
SDIO_TypeDef | SD host Interface
SPI_InitTypeDef | SPI Init structure definition
SPI_TypeDef | Serial Peripheral Interface
TIM_BDTRInitTypeDef | BDTR structure definition
TIM_ICInitTypeDef | TIM Input Capture Init structure definition
TIM_OCInitTypeDef | TIM Output Compare Init structure definition
TIM_TimeBaseInitTypeDef | TIM Time Base Init structure definition
TIM_TypeDef | TIM
TS_STATE | Touch Screen Information structure
USART_ClockInitTypeDef | USART Clock Init Structure definition
USART_InitTypeDef | USART Init Structure definition
USART_TypeDef | Universal Synchronous Asynchronous Receiver Transmitter
WWDG_TypeDef | Window WATCHDOG


STM32F10x Standard Peripherals Firmware Library: main.h Source File

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • BKP
  • Tamper

BKP/Tamper/main.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    BKP/Tamper/main.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Header for main.c module
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __MAIN_H
00024 #define __MAIN_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028 #include "stm32_eval.h"
00029
00030 /* Exported types ------------------------------------------------------------*/
00031 /* Exported constants --------------------------------------------------------*/
00032 /* Exported macro ------------------------------------------------------------*/
00033 /* Exported functions ------------------------------------------------------- */
00034 uint32_t IsBackupRegReset(void);
00035
00036 #endif /* __MAIN_H */
00037
00038 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: platform_config.h Source File

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • CAN
  • Networking

CAN/Networking/platform_config.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    CAN/Networking/platform_config.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Evaluation board specific configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __PLATFORM_CONFIG_H
00024 #define __PLATFORM_CONFIG_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32_eval.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Uncomment the line corresponding to the STMicroelectronics evaluation board
00032    used to run the example */
00033 #if !defined (USE_STM3210B_EVAL) &&  !defined (USE_STM3210E_EVAL) &&  !defined (USE_STM3210C_EVAL)
00034  //#define USE_STM3210B_EVAL
00035  //#define USE_STM3210E_EVAL
00036  #define USE_STM3210C_EVAL
00037 #endif
00038
00039 /* Define the STM32F10x hardware depending on the used evaluation board */
00040 #ifdef USE_STM3210B_EVAL
00041   #define RCC_APB2Periph_GPIO_CAN1    RCC_APB2Periph_GPIOD
00042   #define GPIO_Remapping_CAN1         GPIO_Remap2_CAN1
00043   #define GPIO_CAN1                   GPIOD
00044   #define GPIO_Pin_CAN1_RX            GPIO_Pin_0
00045   #define GPIO_Pin_CAN1_TX            GPIO_Pin_1
00046
00047 #elif defined USE_STM3210E_EVAL
00048   #define RCC_APB2Periph_GPIO_CAN1    RCC_APB2Periph_GPIOB
00049   #define GPIO_Remapping_CAN1         GPIO_Remap1_CAN1
00050   #define GPIO_CAN1                   GPIOB
00051   #define GPIO_Pin_CAN1_RX            GPIO_Pin_8
00052   #define GPIO_Pin_CAN1_TX            GPIO_Pin_9
00053
00054 #elif defined USE_STM3210C_EVAL
00055   #define RCC_APB2Periph_GPIO_CAN1    RCC_APB2Periph_GPIOD
00056   #define GPIO_Remapping_CAN1         GPIO_Remap2_CAN1
00057   #define GPIO_CAN1                   GPIOD
00058   #define GPIO_Pin_CAN1_RX            GPIO_Pin_0
00059   #define GPIO_Pin_CAN1_TX            GPIO_Pin_1
00060
00061   #define RCC_APB2Periph_GPIO_CAN2    RCC_APB2Periph_GPIOB
00062   #define GPIO_Remapping_CAN2         GPIO_Remap_CAN2
00063   #define GPIO_CAN2                   GPIOB
00064   #define GPIO_Pin_CAN2_RX            GPIO_Pin_5
00065   #define GPIO_Pin_CAN2_TX            GPIO_Pin_6
00066 #endif /* USE_STM3210B_EVAL */
00067
00068 /* Exported macro ------------------------------------------------------------*/
00069 /* Exported functions ------------------------------------------------------- */
00070
00071 #endif /* __PLATFORM_CONFIG_H */
00072
00073 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: Data Structure Index

  • Data Structures
  • Data Structure Index
  • Data Fields

Data Structure Index

A | B | C | D | E | F | G | H | I | L | N | O | P | R | S | T | U | W | _
A
CAN_FIFOMailBox_TypeDef CanTxMsg DBGMCU_TypeDef EXTI_TypeDef FSMC_Bank4_TypeDef GPIO_InitTypeDef I2C_TypeDef NAND_ADDRESS OneNAND_ADDRESS RCC_ClocksTypeDef SD_CardStatus SDIO_TypeDef TIM_OCInitTypeDef USART_InitTypeDef
ADC_InitTypeDef CAN_FilterInitTypeDef CEC_InitTypeDef DMA_Channel_TypeDef
F
FSMC_NAND_PCCARDTimingInitTypeDef GPIO_TypeDef I2S_InitTypeDef NAND_IDTypeDef OneNAND_IDTypeDef RCC_TypeDef SD_CID SPI_InitTypeDef TIM_TimeBaseInitTypeDef USART_TypeDef
ADC_TypeDef CAN_FilterRegister_TypeDef CEC_TypeDef DMA_InitTypeDef FLASH_TypeDef FSMC_NANDInitTypeDef
H
IWDG_TypeDef NOR_IDTypeDef
P
RTC_TypeDef SD_CSD SPI_TypeDef TIM_TypeDef
W
AFIO_TypeDef CAN_InitTypeDef CRC_TypeDef DMA_TypeDef FSMC_Bank1_TypeDef FSMC_NORSRAMInitTypeDef HDMI_CEC_Map
L
NVIC_InitTypeDef Point
S
SDIO_CmdInitTypeDef
T
TS_STATE WWDG_TypeDef
B
CAN_TxMailBox_TypeDef
D
E
FSMC_Bank1E_TypeDef FSMC_NORSRAMTimingInitTypeDef HDMI_CEC_Message LCD_TypeDef
O
PWR_TypeDef SC_ATR SDIO_DataInitTypeDef TIM_BDTRInitTypeDef
U
_
BKP_TypeDef CAN_TypeDef DAC_InitTypeDef ETH_TypeDef FSMC_Bank2_TypeDef FSMC_PCCARDInitTypeDef
I
N
OB_TypeDef
R
SD_CardInfo SDIO_InitTypeDef TIM_ICInitTypeDef USART_ClockInitTypeDef _tFont
C
CanRxMsg DAC_TypeDef EXTI_InitTypeDef FSMC_Bank3_TypeDef
G
I2C_InitTypeDef


STM32F10x Standard Peripherals Firmware Library: Complete list of DMA examples.txt File Reference

  • File List
  • Globals

Complete list of DMA examples.txt File Reference

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: main.h Source File

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • CortexM3
  • MPU

CortexM3/MPU/main.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    CortexM3/MPU/main.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Header for main.c module
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __MAIN_H
00024 #define __MAIN_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Public macro --------------------------------------------------------------*/
00033 /* Public define -------------------------------------------------------------*/
00034 #define RAM_ADDRESS_START                        (0x20000000UL)
00035 #define RAM_SIZE                                 (0x19UL << 0UL)
00036 #define PERIPH_ADDRESS_START                     (0x40000000)
00037 #define PERIPH_SIZE                              (0x39UL << 0UL)
00038 #define FLASH_ADDRESS_START                      (0x08000000)
00039 #define FLASH_SIZE                               (0x27UL << 0UL)
00040 #define portMPU_REGION_READ_WRITE                (0x03UL << MPU_RASR_AP_Pos)
00041 #define portMPU_REGION_PRIVILEGED_READ_ONLY      (0x05UL << MPU_RASR_AP_Pos)
00042 #define portMPU_REGION_READ_ONLY                 (0x06UL << MPU_RASR_AP_Pos)
00043 #define portMPU_REGION_PRIVILEGED_READ_WRITE     (0x01UL << MPU_RASR_AP_Pos)
00044 #define RAM_REGION_NUMBER                        (0x00UL << MPU_RNR_REGION_Pos)
00045 #define FLASH_REGION_NUMBER                      (0x01UL << MPU_RNR_REGION_Pos)
00046 #define PERIPH_REGION_NUMBER                     (0x02UL << MPU_RNR_REGION_Pos)
00047
00048 /* Exported functions ------------------------------------------------------- */
00049 void accesspermission(void);
00050
00051 #endif /* __MAIN_H */
00052
00053 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • ADC
  • AnalogWatchdog

AnalogWatchdog Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/main.c [code]

Main program body.

file | STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • RTC
  • LSI_Calib

LSI_Calib Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/main.c [code]

Main program body.

file | RTC/LSI_Calib/main.h [code]

Header file for main.c.

file | STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • NVIC
  • DMA_WFIMode

DMA_WFIMode Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/main.c [code]

Main program body.

file | STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • TIM
  • TIM10_PWMOutput

TIM10_PWMOutput Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/main.c [code]

Main program body.

file | STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • STM32100E_EVAL

STM32100E_EVAL Directory Reference

Files

file | stm32100e_eval.c [code]

This file provides

  • set of firmware functions to manage Leds, push-button and COM ports
  • low level initialization functions for SD card (on SDIO), SPI serial flash (sFLASH) and temperature sensor (LM75) available on STM32100E-EVAL evaluation board from STMicroelectronics.

file | stm32100e_eval.h [code]

This file contains definitions for STM32100E_EVAL's Leds, push-buttons COM ports, sFLASH (on SPI) and Temperature Sensor LM75 (on I2C) hardware resources.

file | stm32100e_eval_cec.c [code]

This file provides all the STM32100E-EVAL HDMI-CEC firmware functions.

file | stm32100e_eval_cec.h [code]

This file contains all the functions prototypes for the stm32100e_eval_cec firmware driver.

file | stm32100e_eval_fsmc_onenand.c [code]

This file provides a set of functions needed to drive the KFG1216U2A/B-DIB6 OneNAND memory mounted on STM32100E-EVAL board.

file | stm32100e_eval_fsmc_onenand.h [code]

This file contains all the functions prototypes for the stm32100e_eval_fsmc_onenand firmware driver.

file | stm32100e_eval_fsmc_sram.c [code]

This file provides a set of functions needed to drive the IS61WV102416BLL SRAM memory mounted on STM32100E-EVAL board.

file | stm32100e_eval_fsmc_sram.h [code]

This file contains all the functions prototypes for the stm32100e_eval_fsmc_sram firmware driver.

file | stm32100e_eval_ioe.c [code]

This file includes the IO Expander driver for STMPE811 IO Expander devices.

file | stm32100e_eval_ioe.h [code]

This file contains all the functions prototypes for the IO Expander firmware driver.

file | stm32100e_eval_lcd.c [code]

This file includes the LCD driver for AM-240320L8TNQW00H (LCD_ILI9320), AM240320D5TOQW01H (LCD_ILI9325) and AM-240320LDTNQW00H (LCD_SPFD5408B) Liquid Crystal Display Module of STM32100E-EVAL board.

file | stm32100e_eval_lcd.h [code]

This file contains all the functions prototypes for the stm32100e_eval_lcd firmware driver.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/MPU/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • CortexM3
  • MPU

MPU Directory Reference

Files

file | accesspermission.c [code]

Access rights configuration using Cortex-M3 MPU regions.

file | STM32F10x_StdPeriph_Examples/CortexM3/MPU/main.c [code]

Main program body.

file | CortexM3/MPU/main.h [code]

Header for main.c module.

file | STM32F10x_StdPeriph_Examples/CortexM3/MPU/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/CortexM3/MPU/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/CortexM3/MPU/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/CortexM3/MPU/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RTC/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • RTC

RTC Directory Reference

Directories

directory | Calendar
directory | LSI_Calib


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • SPI

SPI Directory Reference

Directories

directory | CRC
directory | DMA
directory | FullDuplex_SoftNSS
directory | Simplex_Interrupt
directory | SPI_FLASH


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • I2C
  • I2C_TSENSOR

I2C_TSENSOR Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/main.c [code]

Main program body.

file | STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • TIM

TIM Directory Reference

Directories

directory | 6Steps
directory | 7PWM_Output
directory | Cascade_Synchro
directory | ComplementarySignals
directory | DMA
directory | DMABurst
directory | ExtTrigger_Synchro
directory | InputCapture
directory | OCActive
directory | OCInactive
directory | OCToggle
directory | OnePulse
directory | Parallel_Synchro
directory | PWM_Input
directory | PWM_Output
directory | TIM10_PWMOutput
directory | TIM15_ComplementarySignals
directory | TIM1_Synchro
directory | TIM9_OCToggle
directory | TimeBase


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • DAC

DAC Directory Reference

Directories

directory | DualModeDMA_SineWave
directory | OneChannel_NoiseWave
directory | OneChannelDMA_Escalator
directory | TwoChannels_TriangleWave


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • USART
  • HyperTerminal_Interrupt

HyperTerminal_Interrupt Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/main.c [code]

Main program body.

file | STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/6Steps/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • TIM
  • 6Steps

6Steps Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/TIM/6Steps/main.c [code]

Main program body.

file | STM32F10x_StdPeriph_Examples/TIM/6Steps/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/TIM/6Steps/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/TIM/6Steps/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/TIM/6Steps/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/IWDG/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • IWDG

IWDG Directory Reference

Directories

directory IWDG_Reset


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCToggle/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • TIM
  • OCToggle

OCToggle Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/TIM/OCToggle/main.c [code]

Main program body.

file | STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/TIM/OCToggle/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • ADC

ADC Directory Reference

Directories

directory | 3ADCs_DMA
directory | ADC1_DMA
directory | AnalogWatchdog
directory | ExtLinesTrigger
directory | RegSimul_DualMode
directory | TIMTrigger_AutoInjection


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/WWDG/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • WWDG

WWDG Directory Reference

Directories

directory WWDG_Reset


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OnePulse/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • TIM
  • OnePulse

OnePulse Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/TIM/OnePulse/main.c [code]

Main program body.

file | STM32F10x_StdPeriph_Examples/TIM/OnePulse/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/TIM/OnePulse/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/TIM/OnePulse/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/TIM/OnePulse/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • CAN

CAN Directory Reference

Directories

directory | DualCAN
directory | LoopBack
directory | Networking


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/DMA/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • SPI
  • DMA

DMA Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/SPI/DMA/main.c [code]

Main program body.

file | SPI/DMA/platform_config.h [code]

Evaluation board specific configuration file.

file | STM32F10x_StdPeriph_Examples/SPI/DMA/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/SPI/DMA/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/SPI/DMA/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/SPI/DMA/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Template

STM32F10x_StdPeriph_Template Directory Reference

Files

file | STM32F10x_StdPeriph_Template/main.c [code]

Main program body.

file | STM32F10x_StdPeriph_Template/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Template/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Template/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Template/system_stm32f10x.c [code]


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • SPI
  • Simplex_Interrupt

Simplex_Interrupt Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/main.c [code]

Main program body.

file | SPI/Simplex_Interrupt/platform_config.h [code]

Evaluation board specific configuration file.

file | STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • TIM
  • ExtTrigger_Synchro

ExtTrigger_Synchro Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/main.c [code]

Main program body.

file | STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • ADC
  • ExtLinesTrigger

ExtLinesTrigger Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/main.c [code]

Main program body.

file | STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • PWR

PWR Directory Reference

Directories

directory | PVD
directory | STANDBY
directory | STOP


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RTC/Calendar/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • RTC
  • Calendar

Calendar Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/RTC/Calendar/main.c [code]

Main program body.

file | STM32F10x_StdPeriph_Examples/RTC/Calendar/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/RTC/Calendar/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/RTC/Calendar/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/RTC/Calendar/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • USART

USART Directory Reference

Directories

directory | DMA_Interrupt
directory | DMA_Polling
directory | HalfDuplex
directory | HyperTerminal_HwFlowControl
directory | HyperTerminal_Interrupt
directory | Interrupt
directory | IrDA
directory | MultiProcessor
directory | Polling
directory | Printf
directory | Smartcard
directory | Synchronous


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples

STM32F10x_StdPeriph_Examples Directory Reference

Directories

directory | ADC
directory | BKP
directory | CAN
directory | CEC
directory | CortexM3
directory | CRC
directory | DAC
directory | DMA
directory | EXTI
directory | FLASH
directory | FSMC
directory | GPIO
directory | I2C
directory | I2S
directory | IWDG
directory | Lib_DEBUG
directory | NVIC
directory | PWR
directory | RCC
directory | RTC
directory | SDIO
directory | SPI
directory | SysTick
directory | TIM
directory | USART
directory | WWDG


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Program/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • FLASH
  • Program

Program Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/FLASH/Program/main.c [code]

Main program body.

file | STM32F10x_StdPeriph_Examples/FLASH/Program/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/FLASH/Program/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/FLASH/Program/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/FLASH/Program/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • TIM
  • TIM15_ComplementarySignals

TIM15_ComplementarySignals Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/main.c [code]

Main program body.

file | STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • DAC
  • OneChannel_NoiseWave

OneChannel_NoiseWave Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/main.c [code]

Main program body.

file | STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/BKP/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • BKP

BKP Directory Reference

Directories

directory | Backup_Data
directory | Tamper


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCActive/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • TIM
  • OCActive

OCActive Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/TIM/OCActive/main.c [code]

Main program body.

file | STM32F10x_StdPeriph_Examples/TIM/OCActive/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/TIM/OCActive/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/TIM/OCActive/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/TIM/OCActive/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • SPI
  • SPI_FLASH

SPI_FLASH Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/main.c [code]

Main program body.

file | STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100B_EVAL/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • STM32100B_EVAL

STM32100B_EVAL Directory Reference

Files

file | stm32100b_eval.c [code]

This file provides

  • set of firmware functions to manage Leds, push-button and COM ports
  • low level initialization functions for SD card (on SPI), SPI serial flash (sFLASH) and temperature sensor (LM75) available on STM32100B-EVAL evaluation board from STMicroelectronics.

file | stm32100b_eval.h [code]

This file contains definitions for STM32100B_EVAL's Leds, push-buttons COM ports, SD Card on SPI, sFLASH on SPI and Temperature Sensor LM75 on I2C hardware resources.

file | stm32100b_eval_cec.c [code]

This file provides all the STM32100B-EVAL HDMI-CEC firmware functions.

file | stm32100b_eval_cec.h [code]

This file contains all the functions prototypes for the stm32100b_eval_cec firmware driver.

file | stm32100b_eval_lcd.c [code]

This file includes the LCD driver for AM-240320LTNQW00H (LCD_HX8312), AM-240320L8TNQW00H (LCD_ILI9320), AM-240320LDTNQW00H (LCD_SPFD5408B) Liquid Crystal Display Module of STM32100B-EVAL board.

file | stm32100b_eval_lcd.h [code]

This file contains all the functions prototypes for the stm32100b_eval_lcd firmware driver.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Input/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • TIM
  • PWM_Input

PWM_Input Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/TIM/PWM_Input/main.c [code]

Main program body.

file | STM32F10x_StdPeriph_Examples/TIM/PWM_Input/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/TIM/PWM_Input/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/TIM/PWM_Input/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Input/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/IOExpander/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • I2C
  • IOExpander

IOExpander Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/I2C/IOExpander/main.c [code]

Main program body.

file | I2C/IOExpander/main.h [code]

Header for main.c module.

file | STM32F10x_StdPeriph_Examples/I2C/IOExpander/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/I2C/IOExpander/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/I2C/IOExpander/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/I2C/IOExpander/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2S/Interrupt/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • I2S
  • Interrupt

Interrupt Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/I2S/Interrupt/main.c [code]

Main program body.

file | STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/I2S/Interrupt/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • FSMC
  • SRAM

SRAM Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/FSMC/SRAM/main.c [code]

Main program body.

file | STM32F10x_StdPeriph_Examples/FSMC/SRAM/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/FSMC/SRAM/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/FSMC/SRAM/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Libraries
  • CMSIS
  • CM3
  • DeviceSupport
  • ST

ST Directory Reference

Directories

directory STM32F10x


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities

Utilities Directory Reference

Directories

directory STM32_EVAL


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/IrDA/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • USART
  • IrDA

IrDA Directory Reference

Directories

directory | Receive
directory | Transmit


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210C_EVAL/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • STM3210C_EVAL

STM3210C_EVAL Directory Reference

Files

file | stm3210c_eval.c [code]

This file provides

  • set of firmware functions to manage Leds, push-button and COM ports
  • low level initialization functions for SD card (on SPI) and I2C serial EEPROM (sEE) available on STM3210C-EVAL evaluation board from STMicroelectronics.

file | stm3210c_eval.h [code]

This file contains definitions for STM3210C_EVAL's Leds, push-buttons COM ports, SD Card on SPI and sEE on I2C hardware resources.

file | stm3210c_eval_ioe.c [code]

This file includes the IO Expander driver for STMPE811 IO Expander devices.

file | stm3210c_eval_ioe.h [code]

This file contains all the functions prototypes for the IO Expander firmware driver.

file | stm3210c_eval_lcd.c [code]

This file includes the LCD driver for AM-240320L8TNQW00H (LCD_ILI9320) Liquid Crystal Display Module of STM3210C-EVAL board.

file | stm3210c_eval_lcd.h [code]

This file contains all the functions prototypes for the lcd firmware driver.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • TIM
  • ComplementarySignals

ComplementarySignals Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/main.c [code]

Main program body.

file | STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TimeBase/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • TIM
  • TimeBase

TimeBase Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/TIM/TimeBase/main.c [code]

Main program body.

file | STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/TIM/TimeBase/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • Common

Common Directory Reference

Files

file | fonts.c [code]

This file provides text fonts for STM32xx-EVAL's LCD driver.

file | fonts.h [code]

Header for fonts.c.

file | stm32_eval_i2c_ee.c [code]

This file provides a set of functions needed to manage the I2C M24CXX EEPROM memory mounted on STM32xx-EVAL board (refer to stm32_eval.h to know about the boards supporting this memory).

file | stm32_eval_i2c_ee.h [code]

This file contains all the functions prototypes for the stm32_eval_i2c_ee firmware driver.

file | stm32_eval_i2c_tsensor.c [code]

This file provides a set of functions needed to manage the I2C LM75 temperature sensor mounted on STM32xx-EVAL board (refer to stm32_eval.h to know about the boards supporting this sensor). It implements a high level communication layer for read and write from/to this sensor. The needed STM32 hardware resources (I2C and GPIO) are defined in stm32xx_eval.h file, and the initialization is performed in LM75_LowLevel_Init() function declared in stm32xx_eval.c file.

file | stm32_eval_i2c_tsensor.h [code]

This file contains all the functions prototypes for the stm32_eval_i2c_tsensor firmware driver.

file | stm32_eval_sdio_sd.c [code]

This file provides a set of functions needed to manage the SDIO SD Card memory mounted on STM32xx-EVAL board (refer to stm32_eval.h to know about the boards supporting this memory).

file | stm32_eval_sdio_sd.h [code]

This file contains all the functions prototypes for the SD Card stm32_eval_sdio_sd driver firmware library.

file | stm32_eval_spi_flash.c [code]

This file provides a set of functions needed to manage the SPI M25Pxxx FLASH memory mounted on STM32xx-EVAL board (refer to stm32_eval.h to know about the boards supporting this memory). It implements a high level communication layer for read and write from/to this memory. The needed STM32 hardware resources (SPI and GPIO) are defined in stm32xx_eval.h file, and the initialization is performed in sFLASH_LowLevel_Init() function declared in stm32xx_eval.c file. You can easily tailor this driver to any other development board, by just adapting the defines for hardware resources and sFLASH_LowLevel_Init() function.

file | stm32_eval_spi_flash.h [code]

This file contains all the functions prototypes for the stm32_eval_spi_flash firmware driver.

file | stm32_eval_spi_sd.c [code]

This file provides a set of functions needed to manage the SPI SD Card memory mounted on STM32xx-EVAL board (refer to stm32_eval.h to know about the boards supporting this memory). It implements a high level communication layer for read and write from/to this memory. The needed STM32 hardware resources (SPI and GPIO) are defined in stm32xx_eval.h file, and the initialization is performed in SD_LowLevel_Init() function declared in stm32xx_eval.c file. You can easily tailor this driver to any other development board, by just adapting the defines for hardware resources and SD_LowLevel_Init() function.

file | stm32_eval_spi_sd.h [code]

This file contains all the functions prototypes for the stm32_eval_spi_sd firmware driver.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • TIM
  • Cascade_Synchro

Cascade_Synchro Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/main.c [code]

Main program body.

file | STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/CRC/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • SPI
  • CRC

CRC Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/SPI/CRC/main.c [code]

Main program body.

file | STM32F10x_StdPeriph_Examples/SPI/CRC/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/SPI/CRC/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/SPI/CRC/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/SPI/CRC/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • DAC
  • TwoChannels_TriangleWave

TwoChannels_TriangleWave Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/main.c [code]

Main program body.

file | STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/EXTI/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • EXTI

EXTI Directory Reference

Directories

directory EXTI_Config


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • STM3210E_EVAL

STM3210E_EVAL Directory Reference

Files

file | stm3210e_eval.c [code]

This file provides

  • set of firmware functions to manage Leds, push-button and COM ports
  • low level initialization functions for SD card (on SDIO), SPI serial flash (sFLASH) and temperature sensor (LM75) available on STM3210E-EVAL evaluation board from STMicroelectronics.

file | stm3210e_eval.h [code]

This file contains definitions for STM3210E_EVAL's Leds, push-buttons COM ports, sFLASH (on SPI) and Temperature Sensor LM75 (on I2C) hardware resources.

file | stm3210e_eval_fsmc_nand.c [code]

This file provides a set of functions needed to drive the NAND512W3A2 memory mounted on STM3210E-EVAL board.

file | stm3210e_eval_fsmc_nand.h [code]

This file contains all the functions prototypes for the stm3210e_eval_fsmc_nand firmware driver.

file | stm3210e_eval_fsmc_nor.c [code]

This file provides a set of functions needed to drive the M29W128FL, M29W128GL and S29GL128P NOR memories mounted on STM3210E-EVAL board.

file | stm3210e_eval_fsmc_nor.h [code]

This file contains all the functions prototypes for the stm3210e_eval_fsmc_nor firmware driver.

file | stm3210e_eval_fsmc_sram.c [code]

This file provides a set of functions needed to drive the IS61WV51216BLL SRAM memory mounted on STM3210E-EVAL board.

file | stm3210e_eval_fsmc_sram.h [code]

This file contains all the functions prototypes for the stm3210e_eval_fsmc_sram firmware driver.

file | stm3210e_eval_lcd.c [code]

This file includes the LCD driver for AM-240320L8TNQW00H (LCD_ILI9320) and AM-240320LDTNQW00H (LCD_SPFD5408B) Liquid Crystal Display Module of STM3210E-EVAL board.

file | stm3210e_eval_lcd.h [code]

This file contains all the functions prototypes for the stm3210e_eval_lcd firmware driver.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • FSMC
  • NOR_CodeExecute
  • binary

binary Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/main.c [code]

Main program body.

file | STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Libraries
  • CMSIS
  • CM3

CM3 Directory Reference

Directories

directory DeviceSupport


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • DAC
  • OneChannelDMA_Escalator

OneChannelDMA_Escalator Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/main.c [code]

Main program body.

file | STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/DMA/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • TIM
  • DMA

DMA Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/TIM/DMA/main.c [code]

Main program body.

file | STM32F10x_StdPeriph_Examples/TIM/DMA/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/TIM/DMA/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/TIM/DMA/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/TIM/DMA/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project

Project Directory Reference

Directories

directory | STM32F10x_StdPeriph_Examples
directory | STM32F10x_StdPeriph_Template


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/BKP/Backup_Data/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • BKP
  • Backup_Data

Backup_Data Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/BKP/Backup_Data/main.c [code]

Main program body.

file | STM32F10x_StdPeriph_Examples/BKP/Backup_Data/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/BKP/Backup_Data/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/BKP/Backup_Data/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/BKP/Backup_Data/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • FSMC
  • NOR

NOR Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/FSMC/NOR/main.c [code]

Main program body.

file | STM32F10x_StdPeriph_Examples/FSMC/NOR/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/FSMC/NOR/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/FSMC/NOR/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/FSMC/NOR/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210B_EVAL/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • STM3210B_EVAL

STM3210B_EVAL Directory Reference

Files

file | stm3210b_eval.c [code]

This file provides

  • set of firmware functions to manage Leds, push-button and COM ports
  • low level initialization functions for SD card (on SPI), SPI serial flash (sFLASH) and temperature sensor (LM75) available on STM3210B-EVAL evaluation board from STMicroelectronics.

file | stm3210b_eval.h [code]

This file contains definitions for STM3210B_EVAL's Leds, push-buttons COM ports, SD Card (on SPI), sFLASH (on SPI) and Temperature sensor LM75 (on I2C) hardware resources.

file | stm3210b_eval_lcd.c [code]

This file includes the LCD driver for AM-240320LTNQW00H (LCD_HX8312), AM-240320L8TNQW00H (LCD_ILI9320), AM-240320LDTNQW00H (LCD_SPFD5408B) Liquid Crystal Display Module of STM3210B-EVAL board.

file | stm3210b_eval_lcd.h [code]

This file contains all the functions prototypes for the stm3210b_eval_lcd firmware driver.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SDIO/uSDCard/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • SDIO
  • uSDCard

uSDCard Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/SDIO/uSDCard/main.c [code]

Main program body.

file | STM32F10x_StdPeriph_Examples/SDIO/uSDCard/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/SDIO/uSDCard/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/SDIO/uSDCard/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/SDIO/uSDCard/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32L152_EVAL/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • STM32L152_EVAL

STM32L152_EVAL Directory Reference

Files

file | stm32l152_eval.c [code]

This file provides:

  • set of firmware functions to manage Leds, push-button and COM ports
  • low level initialization functions for SD card (on SPI) and temperature sensor (LM75) available on STM32L152-EVAL evaluation board RevB from STMicroelectronics.

file | stm32l152_eval.h [code]

This file contains definitions for STM32L152_EVAL's Leds, push-buttons and COM ports hardware resources.

file | stm32l152_eval_glass_lcd.c [code]

This file includes the LCD Glass driver for Pacific Display (LCD_PD878, PD878-DP-FH-W-LV-6-RH) Module of STM32L152-EVAL board RevB.

file | stm32l152_eval_glass_lcd.h [code]

Header file for stm32l152_eval_glass_lcd.c module.

file | stm32l152_eval_i2c_ee.c [code]

This file provides a set of functions needed to manage an I2C M24CXX EEPROM memory.

file | stm32l152_eval_i2c_ee.h [code]

This file contains all the functions prototypes for the stm32l152_eval_i2c_ee firmware driver.

file | stm32l152_eval_lcd.c [code]

This file includes the LCD driver for AM-240320L8TNQW00H (LCD_ILI9320), AM-240320LDTNQW00H (LCD_SPFD5408B) Liquid Crystal Display Module of STM32L152-EVAL board RevB.

file | stm32l152_eval_lcd.h [code]

This file contains all the functions prototypes for the stm32l152_eval_lcd firmware driver.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • DMA
  • ADC_TIM1

ADC_TIM1 Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/main.c [code]

Main program body.

file | STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCInactive/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • TIM
  • OCInactive

OCInactive Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/TIM/OCInactive/main.c [code]

Main program body.

file | STM32F10x_StdPeriph_Examples/TIM/OCInactive/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/TIM/OCInactive/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/TIM/OCInactive/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/TIM/OCInactive/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RCC/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • RCC

RCC Directory Reference

Directories

directory RCC_ClockConfig


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/STOP/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • PWR
  • STOP

STOP Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/PWR/STOP/main.c [code]

Main program body.

file | STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/PWR/STOP/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • ADC
  • 3ADCs_DMA

3ADCs_DMA Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c [code]

Main program body.

file | STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Libraries

Libraries Directory Reference

Directories

directory | CMSIS
directory | STM32F10x_StdPeriph_Driver


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • TIM
  • TIM1_Synchro

TIM1_Synchro Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/main.c [code]

Main program body.

file | STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Output/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • TIM
  • PWM_Output

PWM_Output Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/TIM/PWM_Output/main.c [code]

Main program body.

file | STM32F10x_StdPeriph_Examples/TIM/PWM_Output/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/TIM/PWM_Output/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/TIM/PWM_Output/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Output/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • TIM
  • Parallel_Synchro

Parallel_Synchro Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/main.c [code]

Main program body.

file | STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/OneNAND/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • FSMC
  • OneNAND

OneNAND Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/FSMC/OneNAND/main.c [code]

Main program body.

file | STM32F10x_StdPeriph_Examples/FSMC/OneNAND/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/FSMC/OneNAND/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/FSMC/OneNAND/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/FSMC/OneNAND/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • CRC
  • CRC_Calculation

CRC_Calculation Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/main.c [code]

Main program body.

file | STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/GPIO/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • GPIO

GPIO Directory Reference

Directories

directory | IOToggle
directory | JTAG_Remap


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/DMA_Polling/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • USART
  • DMA_Polling

DMA_Polling Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/USART/DMA_Polling/main.c [code]

Main program body.

file | USART/DMA_Polling/platform_config.h [code]

Evaluation board specific configuration file.

file | STM32F10x_StdPeriph_Examples/USART/DMA_Polling/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/USART/DMA_Polling/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/USART/DMA_Polling/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/USART/DMA_Polling/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • DMA
  • FLASH_RAM

FLASH_RAM Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/main.c [code]

Main program body.

file | STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HalfDuplex/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • USART
  • HalfDuplex

HalfDuplex Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/USART/HalfDuplex/main.c [code]

Main program body.

file | USART/HalfDuplex/platform_config.h [code]

Evaluation board specific configuration file.

file | STM32F10x_StdPeriph_Examples/USART/HalfDuplex/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/USART/HalfDuplex/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/USART/HalfDuplex/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/USART/HalfDuplex/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Smartcard/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • USART
  • Smartcard

Smartcard Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/USART/Smartcard/main.c [code]

Main program body.

file | USART/Smartcard/platform_config.h [code]

Evaluation board specific configuration file.

file | STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/USART/Smartcard/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • FLASH

FLASH Directory Reference

Directories

directory | Dual_Boot
directory | Program
directory | Write_Protection


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/BitBand/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • CortexM3
  • BitBand

BitBand Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/CortexM3/BitBand/main.c [code]

Main program body.

file | STM32F10x_StdPeriph_Examples/CortexM3/BitBand/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/CortexM3/BitBand/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/CortexM3/BitBand/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/CortexM3/BitBand/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Libraries
  • STM32F10x_StdPeriph_Driver
  • src

src Directory Reference

Files

file | misc.c [code]

This file provides all the miscellaneous firmware functions (add-on to CMSIS functions).

file | stm32f10x_adc.c [code]

This file provides all the ADC firmware functions.

file | stm32f10x_bkp.c [code]

This file provides all the BKP firmware functions.

file | stm32f10x_can.c [code]

This file provides all the CAN firmware functions.

file | stm32f10x_cec.c [code]

This file provides all the CEC firmware functions.

file | stm32f10x_crc.c [code]

This file provides all the CRC firmware functions.

file | stm32f10x_dac.c [code]

This file provides all the DAC firmware functions.

file | stm32f10x_dbgmcu.c [code]

This file provides all the DBGMCU firmware functions.

file | stm32f10x_dma.c [code]

This file provides all the DMA firmware functions.

file | stm32f10x_exti.c [code]

This file provides all the EXTI firmware functions.

file | stm32f10x_flash.c [code]

This file provides all the FLASH firmware functions.

file | stm32f10x_fsmc.c [code]

This file provides all the FSMC firmware functions.

file | stm32f10x_gpio.c [code]

This file provides all the GPIO firmware functions.

file | stm32f10x_i2c.c [code]

This file provides all the I2C firmware functions.

file | stm32f10x_iwdg.c [code]

This file provides all the IWDG firmware functions.

file | stm32f10x_pwr.c [code]

This file provides all the PWR firmware functions.

file | stm32f10x_rcc.c [code]

This file provides all the RCC firmware functions.

file | stm32f10x_rtc.c [code]

This file provides all the RTC firmware functions.

file | stm32f10x_sdio.c [code]

This file provides all the SDIO firmware functions.

file | stm32f10x_spi.c [code]

This file provides all the SPI firmware functions.

file | stm32f10x_tim.c [code]

This file provides all the TIM firmware functions.

file | stm32f10x_usart.c [code]

This file provides all the USART firmware functions.

file | stm32f10x_wwdg.c [code]

This file provides all the WWDG firmware functions.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • NVIC
  • VectorTable_Relocation

VectorTable_Relocation Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/main.c [code]

Main program body.

file | NVIC/VectorTable_Relocation/main.h [code]

Header for main.c module.

file | STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/DualCAN/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • CAN
  • DualCAN

DualCAN Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/CAN/DualCAN/main.c [code]

Main program body.

file | STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/CAN/DualCAN/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • ADC
  • TIMTrigger_AutoInjection

TIMTrigger_AutoInjection Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/main.c [code]

Main program body.

file | STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • DMA
  • SPI_RAM

SPI_RAM Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/main.c [code]

Main program body.

file | DMA/SPI_RAM/platform_config.h [code]

Evaluation board specific configuration file.

file | STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • WWDG
  • WWDG_Reset

WWDG_Reset Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/main.c [code]

Main program body.

file | STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • USART
  • HyperTerminal_HwFlowControl

HyperTerminal_HwFlowControl Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/main.c [code]

Main program body.

file | USART/HyperTerminal_HwFlowControl/platform_config.h [code]

Evaluation board specific configuration file.

file | STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Libraries
  • CMSIS

CMSIS Directory Reference

Directories

directory CM3


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • TIM
  • 7PWM_Output

7PWM_Output Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/main.c [code]

Main program body.

file | STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/Lib_DEBUG/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • Lib_DEBUG

Lib_DEBUG Directory Reference

Directories

directory RunTime_Check


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Interrupt/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • USART
  • Interrupt

Interrupt Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c [code]

Main program body.

file | USART/Interrupt/platform_config.h [code]

Evaluation board specific configuration file.

file | STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/USART/Interrupt/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Libraries
  • STM32F10x_StdPeriph_Driver
  • inc

inc Directory Reference

Files

file | misc.h [code]

This file contains all the functions prototypes for the miscellaneous firmware library functions (add-on to CMSIS functions).

file | stm32f10x_adc.h [code]

This file contains all the functions prototypes for the ADC firmware library.

file | stm32f10x_bkp.h [code]

This file contains all the functions prototypes for the BKP firmware library.

file | stm32f10x_can.h [code]

This file contains all the functions prototypes for the CAN firmware library.

file | stm32f10x_cec.h [code]

This file contains all the functions prototypes for the CEC firmware library.

file | stm32f10x_crc.h [code]

This file contains all the functions prototypes for the CRC firmware library.

file | stm32f10x_dac.h [code]

This file contains all the functions prototypes for the DAC firmware library.

file | stm32f10x_dbgmcu.h [code]

This file contains all the functions prototypes for the DBGMCU firmware library.

file | stm32f10x_dma.h [code]

This file contains all the functions prototypes for the DMA firmware library.

file | stm32f10x_exti.h [code]

This file contains all the functions prototypes for the EXTI firmware library.

file | stm32f10x_flash.h [code]

This file contains all the functions prototypes for the FLASH firmware library.

file | stm32f10x_fsmc.h [code]

This file contains all the functions prototypes for the FSMC firmware library.

file | stm32f10x_gpio.h [code]

This file contains all the functions prototypes for the GPIO firmware library.

file | stm32f10x_i2c.h [code]

This file contains all the functions prototypes for the I2C firmware library.

file | stm32f10x_iwdg.h [code]

This file contains all the functions prototypes for the IWDG firmware library.

file | stm32f10x_pwr.h [code]

This file contains all the functions prototypes for the PWR firmware library.

file | stm32f10x_rcc.h [code]

This file contains all the functions prototypes for the RCC firmware library.

file | stm32f10x_rtc.h [code]

This file contains all the functions prototypes for the RTC firmware library.

file | stm32f10x_sdio.h [code]

This file contains all the functions prototypes for the SDIO firmware library.

file | stm32f10x_spi.h [code]

This file contains all the functions prototypes for the SPI firmware library.

file | stm32f10x_tim.h [code]

This file contains all the functions prototypes for the TIM firmware library.

file | stm32f10x_usart.h [code]

This file contains all the functions prototypes for the USART firmware library.

file | stm32f10x_wwdg.h [code]

This file contains all the functions prototypes for the WWDG firmware library.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • FSMC
  • NOR_CodeExecute

NOR_CodeExecute Directory Reference

Directories

directory | binary

Files

file | STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/main.c [code]

Main program body.

file | STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • EXTI
  • EXTI_Config

EXTI_Config Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/main.c [code]

Main program body.

file | STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • ADC
  • ADC1_DMA

ADC1_DMA Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/main.c [code]

Main program body.

file | STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • RCC
  • RCC_ClockConfig

RCC_ClockConfig Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/main.c [code]

Main program body.

file | RCC/RCC_ClockConfig/main.h [code]

Header for main.c module.

file | STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CEC/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • CEC

CEC Directory Reference

Directories

directory DataExchangeInterrupt


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • TIM
  • TIM9_OCToggle

TIM9_OCToggle Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/main.c [code]

Main program body.

file | STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • CortexM3
  • Mode_Privilege

Mode_Privilege Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/main.c [code]

Main program body.

file | STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • USART
  • IrDA
  • Transmit

Transmit Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/main.c [code]

Main program body.

file | USART/IrDA/Transmit/platform_config.h [code]

Evaluation board specific configuration file.

file | STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NAND/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • FSMC
  • NAND

NAND Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/FSMC/NAND/main.c [code]

Main program body.

file | STM32F10x_StdPeriph_Examples/FSMC/NAND/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/FSMC/NAND/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/FSMC/NAND/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/FSMC/NAND/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • SPI
  • FullDuplex_SoftNSS

FullDuplex_SoftNSS Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/main.c [code]

Main program body.

file | SPI/FullDuplex_SoftNSS/platform_config.h [code]

Evaluation board specific configuration file.

file | STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Libraries
  • CMSIS
  • CM3
  • DeviceSupport
  • ST
  • STM32F10x

STM32F10x Directory Reference

Files

file | stm32f10x.h [code]

CMSIS Cortex-M3 Device Peripheral Access Layer Header File. This file contains all the peripheral register's definitions, bits definitions and memory mapping for STM32F10x Connectivity line, High density, High density value line, Medium density, Medium density Value line, Low density, Low density Value line and XL-density devices.

file | Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.c [code]
file | system_stm32f10x.h [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Header File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • NVIC

NVIC Directory Reference

Directories

directory | DMA_WFIMode
directory | IRQ_Mask
directory | IRQ_Priority
directory | VectorTable_Relocation


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/FSMC/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • DMA
  • FSMC

FSMC Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/DMA/FSMC/main.c [code]

Main program body.

file | STM32F10x_StdPeriph_Examples/DMA/FSMC/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/DMA/FSMC/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/DMA/FSMC/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/DMA/FSMC/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Printf/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • USART
  • Printf

Printf Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/USART/Printf/main.c [code]

Main program body.

file | STM32F10x_StdPeriph_Examples/USART/Printf/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/USART/Printf/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/USART/Printf/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/USART/Printf/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • DAC
  • DualModeDMA_SineWave

DualModeDMA_SineWave Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/main.c [code]

Main program body.

file | STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • NVIC
  • IRQ_Mask

IRQ_Mask Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/main.c [code]

Main program body.

file | STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/BKP/Tamper/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • BKP
  • Tamper

Tamper Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/BKP/Tamper/main.c [code]

Main program body.

file | BKP/Tamper/main.h [code]

Header for main.c module.

file | STM32F10x_StdPeriph_Examples/BKP/Tamper/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/BKP/Tamper/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/BKP/Tamper/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/BKP/Tamper/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • FLASH
  • Write_Protection

Write_Protection Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/main.c [code]

Main program body.

file | STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • GPIO
  • JTAG_Remap

JTAG_Remap Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/main.c [code]

Main program body.

file | STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • CEC
  • DataExchangeInterrupt

DataExchangeInterrupt Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/main.c [code]

Main program body.

file | STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Synchronous/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • USART
  • Synchronous

Synchronous Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/USART/Synchronous/main.c [code]

Main program body.

file | USART/Synchronous/platform_config.h [code]

Evaluation board specific configuration file.

file | STM32F10x_StdPeriph_Examples/USART/Synchronous/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/USART/Synchronous/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/USART/Synchronous/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/USART/Synchronous/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/InputCapture/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • TIM
  • InputCapture

InputCapture Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/TIM/InputCapture/main.c [code]

Main program body.

file | STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/TIM/InputCapture/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • USART
  • DMA_Interrupt

DMA_Interrupt Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/main.c [code]

Main program body.

file | USART/DMA_Interrupt/platform_config.h [code]

Evaluation board specific configuration file.

file | STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/Networking/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • CAN
  • Networking

Networking Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/CAN/Networking/main.c [code]

Main program body.

file | CAN/Networking/platform_config.h [code]

Evaluation board specific configuration file.

file | STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/CAN/Networking/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CRC/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • CRC

CRC Directory Reference

Directories

directory CRC_Calculation


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • FSMC

FSMC Directory Reference

Directories

directory | NAND
directory | NOR
directory | NOR_CodeExecute
directory | OneNAND
directory | SRAM
directory | SRAM_DataMemory


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/GPIO/IOToggle/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • GPIO
  • IOToggle

IOToggle Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/GPIO/IOToggle/main.c [code]

Main program body.

file | STM32F10x_StdPeriph_Examples/GPIO/IOToggle/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/GPIO/IOToggle/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/GPIO/IOToggle/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/GPIO/IOToggle/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Libraries
  • CMSIS
  • CM3
  • DeviceSupport

DeviceSupport Directory Reference

Directories

directory ST


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SysTick/TimeBase/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • SysTick
  • TimeBase

TimeBase Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/SysTick/TimeBase/main.c [code]

Main program body.

file | SysTick/TimeBase/main.h [code]

Header for main.c module.

file | STM32F10x_StdPeriph_Examples/SysTick/TimeBase/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/SysTick/TimeBase/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/SysTick/TimeBase/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/SysTick/TimeBase/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • FSMC
  • SRAM_DataMemory

SRAM_DataMemory Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/main.c [code]

Main program body.

file | STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0

STM32F10x_StdPeriph_Lib_V3.5.0 Directory Reference

Directories

directory | Libraries
directory | Project
directory | Utilities


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/MultiProcessor/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • USART
  • MultiProcessor

MultiProcessor Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/USART/MultiProcessor/main.c [code]

Main program body.

file | USART/MultiProcessor/platform_config.h [code]

Evaluation board specific configuration file.

file | STM32F10x_StdPeriph_Examples/USART/MultiProcessor/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/USART/MultiProcessor/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/USART/MultiProcessor/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/USART/MultiProcessor/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/EEPROM/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • I2C
  • EEPROM

EEPROM Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/I2C/EEPROM/main.c [code]

Main program body.

file | STM32F10x_StdPeriph_Examples/I2C/EEPROM/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/I2C/EEPROM/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/I2C/EEPROM/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/I2C/EEPROM/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Polling/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • USART
  • Polling

Polling Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/USART/Polling/main.c [code]

Main program body.

file | USART/Polling/platform_config.h [code]

Evaluation board specific configuration file.

file | STM32F10x_StdPeriph_Examples/USART/Polling/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/USART/Polling/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/USART/Polling/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/USART/Polling/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/STANDBY/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • PWR
  • STANDBY

STANDBY Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/PWR/STANDBY/main.c [code]

Main program body.

file | STM32F10x_StdPeriph_Examples/PWR/STANDBY/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/PWR/STANDBY/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/PWR/STANDBY/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/PWR/STANDBY/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • CortexM3

CortexM3 Directory Reference

Directories

directory | BitBand
directory | Mode_Privilege
directory | MPU


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • USART
  • IrDA
  • Receive

Receive Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/main.c [code]

Main program body.

file | USART/IrDA/Receive/platform_config.h [code]

Evaluation board specific configuration file.

file | STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/DMABurst/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • TIM
  • DMABurst

DMABurst Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/TIM/DMABurst/main.c [code]

Main program body.

file | STM32F10x_StdPeriph_Examples/TIM/DMABurst/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/TIM/DMABurst/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/TIM/DMABurst/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/TIM/DMABurst/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SysTick/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • SysTick

SysTick Directory Reference

Directories

directory TimeBase


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • FLASH
  • Dual_Boot

Dual_Boot Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/main.c [code]

Main program body.

file | FLASH/Dual_Boot/main.h [code]

Header for main.c module.

file | STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/LoopBack/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • CAN
  • LoopBack

LoopBack Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/CAN/LoopBack/main.c [code]

Main program body.

file | STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/CAN/LoopBack/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • DMA
  • I2C_RAM

I2C_RAM Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/main.c [code]

Main program body.

file | STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2S/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • I2S

I2S Directory Reference

Directories

directory | Interrupt
directory | SPI_I2S_Switch


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • I2S
  • SPI_I2S_Switch

SPI_I2S_Switch Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/main.c [code]

Main program body.

file | STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL

STM32_EVAL Directory Reference

Directories

directory | Common
directory | STM32100B_EVAL
directory | STM32100E_EVAL
directory | STM3210B_EVAL
directory | STM3210C_EVAL
directory | STM3210E_EVAL
directory | STM32L152_EVAL

Files

file | stm32_eval.c [code]

STM32xx-EVAL abstraction layer. This file should be added to the main application to use the provided functions that manage Leds, push-buttons, COM ports and low level HW resources initialization of the different modules available on STM32 evaluation boards from STMicroelectronics.

file | stm32_eval.h [code]

Header file for stm32_eval.c module.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SDIO/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • SDIO

SDIO Directory Reference

Directories

directory uSDCard


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • IWDG
  • IWDG_Reset

IWDG_Reset Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/main.c [code]

Main program body.

file | STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • ADC
  • RegSimul_DualMode

RegSimul_DualMode Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/main.c [code]

Main program body.

file | STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • DMA

DMA Directory Reference

Directories

directory | ADC_TIM1
directory | FLASH_RAM
directory | FSMC
directory | I2C_RAM
directory | SPI_RAM


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • Lib_DEBUG
  • RunTime_Check

RunTime_Check Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/main.c [code]

Main program body.

file | STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/stm32f10x_conf.h [code]

Library configuration file.

file | stm32f10x_ip_dbg.c [code]

This file provides all peripherals pointers initialization.

file | stm32f10x_ip_dbg.h [code]

This file contains the headers of the library peripherals Debug.

file | STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • I2C

I2C Directory Reference

Directories

directory | EEPROM
directory | I2C_TSENSOR
directory | IOExpander


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Libraries
  • STM32F10x_StdPeriph_Driver

STM32F10x_StdPeriph_Driver Directory Reference

Directories

directory | inc
directory | src


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/PVD/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • PWR
  • PVD

PVD Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/PWR/PVD/main.c [code]

Main program body.

file | STM32F10x_StdPeriph_Examples/PWR/PVD/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/PWR/PVD/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/PWR/PVD/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/PWR/PVD/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: C:/PWA2007/IntroPack/__Deliveries/Libraries/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/ Directory Reference

  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • NVIC
  • IRQ_Priority

IRQ_Priority Directory Reference

Files

file | STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/main.c [code]

Main program body.

file | STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_conf.h [code]

Library configuration file.

file | STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_it.c [code]

Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine.

file | STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_it.h [code]

This file contains the headers of the interrupt handlers.

file | Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/system_stm32f10x.c [code]

CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.


STM32F10x Standard Peripherals Firmware Library: Directories

Directories

This directory hierarchy is sorted roughly, but not completely, alphabetically:
  • STM32F10x_StdPeriph_Lib_V3.5.0
    • Libraries
      • CMSIS
        • CM3
          • DeviceSupport
            • ST
              • STM32F10x
      • STM32F10x_StdPeriph_Driver
        • inc
        • src
    • Project
      • STM32F10x_StdPeriph_Examples
        • ADC
          • 3ADCs_DMA
          • ADC1_DMA
          • AnalogWatchdog
          • ExtLinesTrigger
          • RegSimul_DualMode
          • TIMTrigger_AutoInjection
        • BKP
          • Backup_Data
          • Tamper
        • CAN
          • DualCAN
          • LoopBack
          • Networking
        • CEC
          • DataExchangeInterrupt
        • CortexM3
          • BitBand
          • Mode_Privilege
          • MPU
        • CRC
          • CRC_Calculation
        • DAC
          • DualModeDMA_SineWave
          • OneChannel_NoiseWave
          • OneChannelDMA_Escalator
          • TwoChannels_TriangleWave
        • DMA
          • ADC_TIM1
          • FLASH_RAM
          • FSMC
          • I2C_RAM
          • SPI_RAM
        • EXTI
          • EXTI_Config
        • FLASH
          • Dual_Boot
          • Program
          • Write_Protection
        • FSMC
          • NAND
          • NOR
          • NOR_CodeExecute
            • binary
          • OneNAND
          • SRAM
          • SRAM_DataMemory
        • GPIO
          • IOToggle
          • JTAG_Remap
        • I2C
          • EEPROM
          • I2C_TSENSOR
          • IOExpander
        • I2S
          • Interrupt
          • SPI_I2S_Switch
        • IWDG
          • IWDG_Reset
        • Lib_DEBUG
          • RunTime_Check
        • NVIC
          • DMA_WFIMode
          • IRQ_Mask
          • IRQ_Priority
          • VectorTable_Relocation
        • PWR
          • PVD
          • STANDBY
          • STOP
        • RCC
          • RCC_ClockConfig
        • RTC
          • Calendar
          • LSI_Calib
        • SDIO
          • uSDCard
        • SPI
          • CRC
          • DMA
          • FullDuplex_SoftNSS
          • Simplex_Interrupt
          • SPI_FLASH
        • SysTick
          • TimeBase
        • TIM
          • 6Steps
          • 7PWM_Output
          • Cascade_Synchro
          • ComplementarySignals
          • DMA
          • DMABurst
          • ExtTrigger_Synchro
          • InputCapture
          • OCActive
          • OCInactive
          • OCToggle
          • OnePulse
          • Parallel_Synchro
          • PWM_Input
          • PWM_Output
          • TIM10_PWMOutput
          • TIM15_ComplementarySignals
          • TIM1_Synchro
          • TIM9_OCToggle
          • TimeBase
        • USART
          • DMA_Interrupt
          • DMA_Polling
          • HalfDuplex
          • HyperTerminal_HwFlowControl
          • HyperTerminal_Interrupt
          • Interrupt
          • IrDA
            • Receive
            • Transmit
          • MultiProcessor
          • Polling
          • Printf
          • Smartcard
          • Synchronous
        • WWDG
          • WWDG_Reset
      • STM32F10x_StdPeriph_Template
    • Utilities
      • STM32_EVAL
        • Common
        • STM32100B_EVAL
        • STM32100E_EVAL
        • STM3210B_EVAL
        • STM3210C_EVAL
        • STM3210E_EVAL
        • STM32L152_EVAL


STM32F10x Standard Peripherals Firmware Library: platform_config.h Source File

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • DMA
  • SPI_RAM

DMA/SPI_RAM/platform_config.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    DMA/SPI_RAM/platform_config.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Evaluation board specific configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __PLATFORM_CONFIG_H
00024 #define __PLATFORM_CONFIG_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027
00028 /* Exported types ------------------------------------------------------------*/
00029 /* Exported constants --------------------------------------------------------*/
00030 /* Uncomment the line corresponding to the STMicroelectronics evaluation board
00031    used to run the example */
00032 #if !defined (USE_STM32100E_EVAL) && !defined (USE_STM32100B_EVAL) && !defined (USE_STM3210B_EVAL) &&  !defined (USE_STM3210E_EVAL) &&  !defined (USE_STM3210C_EVAL)
00033  //#define USE_STM32100B_EVAL
00034  //#define USE_STM3210B_EVAL
00035  //#define USE_STM3210E_EVAL
00036  //#define USE_STM32100E_EVAL
00037  #define USE_STM3210C_EVAL
00038 #endif
00039
00040 /* Define the STM32F10x hardware depending on the used evaluation board */
00041 #if defined (USE_STM3210B_EVAL) || defined (USE_STM3210E_EVAL) || defined(USE_STM32100B_EVAL) || defined (USE_STM32100E_EVAL)
00042   #define SPI_MASTER                   SPI1
00043   #define SPI_MASTER_CLK               RCC_APB2Periph_SPI1
00044   #define SPI_MASTER_GPIO              GPIOA
00045   #define SPI_MASTER_GPIO_CLK          RCC_APB2Periph_GPIOA
00046   #define SPI_MASTER_PIN_SCK           GPIO_Pin_5
00047   #define SPI_MASTER_PIN_MISO          GPIO_Pin_6
00048   #define SPI_MASTER_PIN_MOSI          GPIO_Pin_7
00049   #define SPI_MASTER_DMA               DMA1
00050   #define SPI_MASTER_DMA_CLK           RCC_AHBPeriph_DMA1
00051   #define SPI_MASTER_Rx_DMA_Channel    DMA1_Channel2
00052   #define SPI_MASTER_Rx_DMA_FLAG       DMA1_FLAG_TC2
00053   #define SPI_MASTER_Tx_DMA_Channel    DMA1_Channel3
00054   #define SPI_MASTER_Tx_DMA_FLAG       DMA1_FLAG_TC3
00055   #define SPI_MASTER_DR_Base           0x4001300C
00056
00057   #define SPI_SLAVE                    SPI2
00058   #define SPI_SLAVE_CLK                RCC_APB1Periph_SPI2
00059   #define SPI_SLAVE_GPIO               GPIOB
00060   #define SPI_SLAVE_GPIO_CLK           RCC_APB2Periph_GPIOB
00061   #define SPI_SLAVE_PIN_SCK            GPIO_Pin_13
00062   #define SPI_SLAVE_PIN_MISO           GPIO_Pin_14
00063   #define SPI_SLAVE_PIN_MOSI           GPIO_Pin_15
00064   #define SPI_SLAVE_DMA                DMA1
00065   #define SPI_SLAVE_DMA_CLK            RCC_AHBPeriph_DMA1
00066   #define SPI_SLAVE_Rx_DMA_Channel     DMA1_Channel4
00067   #define SPI_SLAVE_Rx_DMA_FLAG        DMA1_FLAG_TC4
00068   #define SPI_SLAVE_Tx_DMA_Channel     DMA1_Channel5
00069   #define SPI_SLAVE_Tx_DMA_FLAG        DMA1_FLAG_TC5
00070   #define SPI_SLAVE_DR_Base            0x4000380C
00071
00072 #elif defined (USE_STM3210C_EVAL)
00073   #define SPI_MASTER                   SPI3   /* SPI pins are remapped by software */
00074   #define SPI_MASTER_CLK               RCC_APB1Periph_SPI3
00075   #define SPI_MASTER_GPIO              GPIOC
00076   #define SPI_MASTER_GPIO_CLK          RCC_APB2Periph_GPIOC
00077   #define SPI_MASTER_PIN_SCK           GPIO_Pin_10
00078   #define SPI_MASTER_PIN_MISO          GPIO_Pin_11
00079   #define SPI_MASTER_PIN_MOSI          GPIO_Pin_12
00080   #define SPI_MASTER_DMA               DMA2
00081   #define SPI_MASTER_DMA_CLK           RCC_AHBPeriph_DMA2
00082   #define SPI_MASTER_Rx_DMA_Channel    DMA2_Channel1
00083   #define SPI_MASTER_Rx_DMA_FLAG       DMA2_FLAG_TC1
00084   #define SPI_MASTER_Tx_DMA_Channel    DMA2_Channel2
00085   #define SPI_MASTER_Tx_DMA_FLAG       DMA2_FLAG_TC2
00086   #define SPI_MASTER_DR_Base           0x40003C0C
00087
00088   #define SPI_SLAVE                    SPI2
00089   #define SPI_SLAVE_CLK                RCC_APB1Periph_SPI2
00090   #define SPI_SLAVE_GPIO               GPIOB
00091   #define SPI_SLAVE_GPIO_CLK           RCC_APB2Periph_GPIOB
00092   #define SPI_SLAVE_PIN_SCK            GPIO_Pin_13
00093   #define SPI_SLAVE_PIN_MISO           GPIO_Pin_14
00094   #define SPI_SLAVE_PIN_MOSI           GPIO_Pin_15
00095   #define SPI_SLAVE_DMA                DMA1
00096   #define SPI_SLAVE_DMA_CLK            RCC_AHBPeriph_DMA1
00097   #define SPI_SLAVE_Rx_DMA_Channel     DMA1_Channel4
00098   #define SPI_SLAVE_Rx_DMA_FLAG        DMA1_FLAG_TC4
00099   #define SPI_SLAVE_Tx_DMA_Channel     DMA1_Channel5
00100   #define SPI_SLAVE_Tx_DMA_FLAG        DMA1_FLAG_TC5
00101   #define SPI_SLAVE_DR_Base            0x4000380C
00102
00103 #endif
00104
00105 /* Exported macro ------------------------------------------------------------*/
00106 /* Exported functions ------------------------------------------------------- */
00107
00108 #endif /* __PLATFORM_CONFIG_H */
00109
00110 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: DMA_EXAMPLES

  • STM32F10x Standard Peripheral's Examples

DMA_EXAMPLES

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    DMA/readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   STM32F10x Standard Peripherals DMA Examples List.
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************

In addition to these examples, there are other examples using the DMA peripheral:

  • Complet List of DMA Examples
    • 3 ADCs DMA example
    • ADC1 DMA example
    • ADC external lines trigger example
    • ADC regular simultaneous dual mode example
    • ADC TIM trigger and auto-injection example
    • DAC dual mode sine wave example
    • DAC one channel DMA escalator example
    • I2C and M24CXX EEPROM communication example
    • I2C and LM75 Temperature Sensor communication example
    • I2C and STMPE811 IO Expander communication example
    • DMA in WFI mode example
    • SDIO_Example
    • SPI DMA example
    • TIM DMA example
    • USART DMA Interrupt example
    • USART DMA Polling example
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: File List

  • File List
  • Globals

File List

Here is a list of all files with brief descriptions:
accesspermission.c [code] | Access rights configuration using Cortex-M3 MPU regions
fonts.c [code] | This file provides text fonts for STM32xx-EVAL's LCD driver
fonts.h [code] | Header for fonts.c
STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/BKP/Backup_Data/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/BKP/Tamper/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/CAN/DualCAN/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/CAN/LoopBack/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/CAN/Networking/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/CortexM3/BitBand/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/CortexM3/MPU/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/DMA/FSMC/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/FLASH/Program/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/FSMC/NAND/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/FSMC/NOR/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/FSMC/OneNAND/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/FSMC/SRAM/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/GPIO/IOToggle/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/I2C/EEPROM/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/I2C/IOExpander/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/I2S/Interrupt/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/PWR/PVD/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/PWR/STANDBY/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/PWR/STOP/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/RTC/Calendar/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/SDIO/uSDCard/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/SPI/CRC/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/SPI/DMA/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/SysTick/TimeBase/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/TIM/6Steps/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/TIM/DMA/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/TIM/DMABurst/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/TIM/InputCapture/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/TIM/OCActive/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/TIM/OCInactive/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/TIM/OCToggle/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/TIM/OnePulse/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/TIM/PWM_Input/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/TIM/PWM_Output/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/TIM/TimeBase/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/USART/DMA_Polling/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/USART/HalfDuplex/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/USART/MultiProcessor/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/USART/Polling/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/USART/Printf/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/USART/Smartcard/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/USART/Synchronous/main.c [code] | Main program body
STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/main.c [code] | Main program body
STM32F10x_StdPeriph_Template/main.c [code] | Main program body
BKP/Tamper/main.h [code] | Header for main.c module
CortexM3/MPU/main.h [code] | Header for main.c module
FLASH/Dual_Boot/main.h [code] | Header for main.c module
I2C/IOExpander/main.h [code] | Header for main.c module
NVIC/VectorTable_Relocation/main.h [code] | Header for main.c module
RCC/RCC_ClockConfig/main.h [code] | Header for main.c module
RTC/LSI_Calib/main.h [code] | Header file for main.c
SysTick/TimeBase/main.h [code] | Header for main.c module
misc.c [code] | This file provides all the miscellaneous firmware functions (add-on to CMSIS functions)
misc.h [code] | This file contains all the functions prototypes for the miscellaneous firmware library functions (add-on to CMSIS functions)
CAN/Networking/platform_config.h [code] | Evaluation board specific configuration file
DMA/SPI_RAM/platform_config.h [code] | Evaluation board specific configuration file
SPI/DMA/platform_config.h [code] | Evaluation board specific configuration file
SPI/FullDuplex_SoftNSS/platform_config.h [code] | Evaluation board specific configuration file
SPI/Simplex_Interrupt/platform_config.h [code] | Evaluation board specific configuration file
USART/DMA_Interrupt/platform_config.h [code] | Evaluation board specific configuration file
USART/DMA_Polling/platform_config.h [code] | Evaluation board specific configuration file
USART/HalfDuplex/platform_config.h [code] | Evaluation board specific configuration file
USART/HyperTerminal_HwFlowControl/platform_config.h [code] | Evaluation board specific configuration file
USART/Interrupt/platform_config.h [code] | Evaluation board specific configuration file
USART/IrDA/Receive/platform_config.h [code] | Evaluation board specific configuration file
USART/IrDA/Transmit/platform_config.h [code] | Evaluation board specific configuration file
USART/MultiProcessor/platform_config.h [code] | Evaluation board specific configuration file
USART/Polling/platform_config.h [code] | Evaluation board specific configuration file
USART/Smartcard/platform_config.h [code] | Evaluation board specific configuration file
USART/Synchronous/platform_config.h [code] | Evaluation board specific configuration file
stm32100b_eval.c [code] This file provides

  • set of firmware functions to manage Leds, push-button and COM ports
  • low level initialization functions for SD card (on SPI), SPI serial flash (sFLASH) and temperature sensor (LM75) available on STM32100B-EVAL evaluation board from STMicroelectronics
stm32100b_eval.h [code] | This file contains definitions for STM32100B_EVAL's Leds, push-buttons COM ports, SD Card on SPI, sFLASH on SPI and Temperature Sensor LM75 on I2C hardware resources
stm32100b_eval_cec.c [code] | This file provides all the STM32100B-EVAL HDMI-CEC firmware functions
stm32100b_eval_cec.h [code] | This file contains all the functions prototypes for the stm32100b_eval_cec firmware driver
stm32100b_eval_lcd.c [code] | This file includes the LCD driver for AM-240320LTNQW00H (LCD_HX8312), AM-240320L8TNQW00H (LCD_ILI9320), AM-240320LDTNQW00H (LCD_SPFD5408B) Liquid Crystal Display Module of STM32100B-EVAL board
stm32100b_eval_lcd.h [code] | This file contains all the functions prototypes for the stm32100b_eval_lcd firmware driver
stm32100e_eval.c [code] This file provides

  • set of firmware functions to manage Leds, push-button and COM ports
  • low level initialization functions for SD card (on SDIO), SPI serial flash (sFLASH) and temperature sensor (LM75) available on STM32100E-EVAL evaluation board from STMicroelectronics
stm32100e_eval.h [code] | This file contains definitions for STM32100E_EVAL's Leds, push-buttons COM ports, sFLASH (on SPI) and Temperature Sensor LM75 (on I2C) hardware resources
stm32100e_eval_cec.c [code] | This file provides all the STM32100E-EVAL HDMI-CEC firmware functions
stm32100e_eval_cec.h [code] | This file contains all the functions prototypes for the stm32100e_eval_cec firmware driver
stm32100e_eval_fsmc_onenand.c [code] | This file provides a set of functions needed to drive the KFG1216U2A/B-DIB6 OneNAND memory mounted on STM32100E-EVAL board
stm32100e_eval_fsmc_onenand.h [code] | This file contains all the functions prototypes for the stm32100e_eval_fsmc_onenand firmware driver
stm32100e_eval_fsmc_sram.c [code] | This file provides a set of functions needed to drive the IS61WV102416BLL SRAM memory mounted on STM32100E-EVAL board
stm32100e_eval_fsmc_sram.h [code] | This file contains all the functions prototypes for the stm32100e_eval_fsmc_sram firmware driver
stm32100e_eval_ioe.c [code] | This file includes the IO Expander driver for STMPE811 IO Expander devices
stm32100e_eval_ioe.h [code] | This file contains all the functions prototypes for the IO Expander firmware driver
stm32100e_eval_lcd.c [code] | This file includes the LCD driver for AM-240320L8TNQW00H (LCD_ILI9320), AM240320D5TOQW01H (LCD_ILI9325) and AM-240320LDTNQW00H (LCD_SPFD5408B) Liquid Crystal Display Module of STM32100E-EVAL board
stm32100e_eval_lcd.h [code] | This file contains all the functions prototypes for the stm32100e_eval_lcd firmware driver
stm3210b_eval.c [code] This file provides

  • set of firmware functions to manage Leds, push-button and COM ports
  • low level initialization functions for SD card (on SPI), SPI serial flash (sFLASH) and temperature sensor (LM75) available on STM3210B-EVAL evaluation board from STMicroelectronics
stm3210b_eval.h [code] | This file contains definitions for STM3210B_EVAL's Leds, push-buttons COM ports, SD Card (on SPI), sFLASH (on SPI) and Temperature sensor LM75 (on I2C) hardware resources
stm3210b_eval_lcd.c [code] | This file includes the LCD driver for AM-240320LTNQW00H (LCD_HX8312), AM-240320L8TNQW00H (LCD_ILI9320), AM-240320LDTNQW00H (LCD_SPFD5408B) Liquid Crystal Display Module of STM3210B-EVAL board
stm3210b_eval_lcd.h [code] | This file contains all the functions prototypes for the stm3210b_eval_lcd firmware driver
stm3210c_eval.c [code] This file provides

  • set of firmware functions to manage Leds, push-button and COM ports
  • low level initialization functions for SD card (on SPI) and I2C serial EEPROM (sEE) available on STM3210C-EVAL evaluation board from STMicroelectronics
stm3210c_eval.h [code] | This file contains definitions for STM3210C_EVAL's Leds, push-buttons COM ports, SD Card on SPI and sEE on I2C hardware resources
stm3210c_eval_ioe.c [code] | This file includes the IO Expander driver for STMPE811 IO Expander devices
stm3210c_eval_ioe.h [code] | This file contains all the functions prototypes for the IO Expander firmware driver
stm3210c_eval_lcd.c [code] | This file includes the LCD driver for AM-240320L8TNQW00H (LCD_ILI9320) Liquid Crystal Display Module of STM3210C-EVAL board
stm3210c_eval_lcd.h [code] | This file contains all the functions prototypes for the lcd firmware driver
stm3210e_eval.c [code] This file provides

  • set of firmware functions to manage Leds, push-button and COM ports
  • low level initialization functions for SD card (on SDIO), SPI serial flash (sFLASH) and temperature sensor (LM75) available on STM3210E-EVAL evaluation board from STMicroelectronics
stm3210e_eval.h [code] | This file contains definitions for STM3210E_EVAL's Leds, push-buttons COM ports, sFLASH (on SPI) and Temperature Sensor LM75 (on I2C) hardware resources
stm3210e_eval_fsmc_nand.c [code] | This file provides a set of functions needed to drive the NAND512W3A2 memory mounted on STM3210E-EVAL board
stm3210e_eval_fsmc_nand.h [code] | This file contains all the functions prototypes for the stm3210e_eval_fsmc_nand firmware driver
stm3210e_eval_fsmc_nor.c [code] | This file provides a set of functions needed to drive the M29W128FL, M29W128GL and S29GL128P NOR memories mounted on STM3210E-EVAL board
stm3210e_eval_fsmc_nor.h [code] | This file contains all the functions prototypes for the stm3210e_eval_fsmc_nor firmware driver
stm3210e_eval_fsmc_sram.c [code] | This file provides a set of functions needed to drive the IS61WV51216BLL SRAM memory mounted on STM3210E-EVAL board
stm3210e_eval_fsmc_sram.h [code] | This file contains all the functions prototypes for the stm3210e_eval_fsmc_sram firmware driver
stm3210e_eval_lcd.c [code] | This file includes the LCD driver for AM-240320L8TNQW00H (LCD_ILI9320) and AM-240320LDTNQW00H (LCD_SPFD5408B) Liquid Crystal Display Module of STM3210E-EVAL board
stm3210e_eval_lcd.h [code] | This file contains all the functions prototypes for the stm3210e_eval_lcd firmware driver
stm32_eval.c [code] | STM32xx-EVAL abstraction layer. This file should be added to the main application to use the provided functions that manage Leds, push-buttons, COM ports and low level HW resources initialization of the different modules available on STM32 evaluation boards from STMicroelectronics
stm32_eval.h [code] | Header file for stm32_eval.c module
stm32_eval_i2c_ee.c [code] | This file provides a set of functions needed to manage the I2C M24CXX EEPROM memory mounted on STM32xx-EVAL board (refer to stm32_eval.h to know about the boards supporting this memory)
stm32_eval_i2c_ee.h [code] | This file contains all the functions prototypes for the stm32_eval_i2c_ee firmware driver
stm32_eval_i2c_tsensor.c [code] | This file provides a set of functions needed to manage the I2C LM75 temperature sensor mounted on STM32xx-EVAL board (refer to stm32_eval.h to know about the boards supporting this sensor). It implements a high level communication layer for read and write from/to this sensor. The needed STM32 hardware resources (I2C and GPIO) are defined in stm32xx_eval.h file, and the initialization is performed in LM75_LowLevel_Init() function declared in stm32xx_eval.c file
stm32_eval_i2c_tsensor.h [code] | This file contains all the functions prototypes for the stm32_eval_i2c_tsensor firmware driver
stm32_eval_sdio_sd.c [code] | This file provides a set of functions needed to manage the SDIO SD Card memory mounted on STM32xx-EVAL board (refer to stm32_eval.h to know about the boards supporting this memory)
stm32_eval_sdio_sd.h [code] | This file contains all the functions prototypes for the SD Card stm32_eval_sdio_sd driver firmware library
stm32_eval_spi_flash.c [code] | This file provides a set of functions needed to manage the SPI M25Pxxx FLASH memory mounted on STM32xx-EVAL board (refer to stm32_eval.h to know about the boards supporting this memory). It implements a high level communication layer for read and write from/to this memory. The needed STM32 hardware resources (SPI and GPIO) are defined in stm32xx_eval.h file, and the initialization is performed in sFLASH_LowLevel_Init() function declared in stm32xx_eval.c file. You can easily tailor this driver to any other development board, by just adapting the defines for hardware resources and sFLASH_LowLevel_Init() function
stm32_eval_spi_flash.h [code] | This file contains all the functions prototypes for the stm32_eval_spi_flash firmware driver
stm32_eval_spi_sd.c [code] | This file provides a set of functions needed to manage the SPI SD Card memory mounted on STM32xx-EVAL board (refer to stm32_eval.h to know about the boards supporting this memory). It implements a high level communication layer for read and write from/to this memory. The needed STM32 hardware resources (SPI and GPIO) are defined in stm32xx_eval.h file, and the initialization is performed in SD_LowLevel_Init() function declared in stm32xx_eval.c file. You can easily tailor this driver to any other development board, by just adapting the defines for hardware resources and SD_LowLevel_Init() function
stm32_eval_spi_sd.h [code] | This file contains all the functions prototypes for the stm32_eval_spi_sd firmware driver
stm32f10x.h [code] | CMSIS Cortex-M3 Device Peripheral Access Layer Header File. This file contains all the peripheral register's definitions, bits definitions and memory mapping for STM32F10x Connectivity line, High density, High density value line, Medium density, Medium density Value line, Low density, Low density Value line and XL-density devices
stm32f10x_adc.c [code] | This file provides all the ADC firmware functions
stm32f10x_adc.h [code] | This file contains all the functions prototypes for the ADC firmware library
stm32f10x_bkp.c [code] | This file provides all the BKP firmware functions
stm32f10x_bkp.h [code] | This file contains all the functions prototypes for the BKP firmware library
stm32f10x_can.c [code] | This file provides all the CAN firmware functions
stm32f10x_can.h [code] | This file contains all the functions prototypes for the CAN firmware library
stm32f10x_cec.c [code] | This file provides all the CEC firmware functions
stm32f10x_cec.h [code] | This file contains all the functions prototypes for the CEC firmware library
STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/BKP/Backup_Data/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/BKP/Tamper/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/CortexM3/BitBand/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/CortexM3/MPU/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/DMA/FSMC/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/FLASH/Program/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/FSMC/NAND/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/FSMC/NOR/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/FSMC/OneNAND/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/FSMC/SRAM/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/GPIO/IOToggle/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/I2C/EEPROM/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/I2C/IOExpander/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/PWR/PVD/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/PWR/STANDBY/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/RTC/Calendar/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/SDIO/uSDCard/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/SPI/CRC/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/SPI/DMA/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/SysTick/TimeBase/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/TIM/6Steps/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/TIM/DMA/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/TIM/DMABurst/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/TIM/OCActive/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/TIM/OCInactive/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/TIM/OnePulse/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/TIM/PWM_Input/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/TIM/PWM_Output/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/USART/DMA_Polling/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/USART/HalfDuplex/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/USART/MultiProcessor/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/USART/Polling/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/USART/Printf/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/USART/Synchronous/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_conf.h [code] | Library configuration file
STM32F10x_StdPeriph_Template/stm32f10x_conf.h [code] | Library configuration file
stm32f10x_crc.c [code] | This file provides all the CRC firmware functions
stm32f10x_crc.h [code] | This file contains all the functions prototypes for the CRC firmware library
stm32f10x_dac.c [code] | This file provides all the DAC firmware functions
stm32f10x_dac.h [code] | This file contains all the functions prototypes for the DAC firmware library
stm32f10x_dbgmcu.c [code] | This file provides all the DBGMCU firmware functions
stm32f10x_dbgmcu.h [code] | This file contains all the functions prototypes for the DBGMCU firmware library
stm32f10x_dma.c [code] | This file provides all the DMA firmware functions
stm32f10x_dma.h [code] | This file contains all the functions prototypes for the DMA firmware library
stm32f10x_exti.c [code] | This file provides all the EXTI firmware functions
stm32f10x_exti.h [code] | This file contains all the functions prototypes for the EXTI firmware library
stm32f10x_flash.c [code] | This file provides all the FLASH firmware functions
stm32f10x_flash.h [code] | This file contains all the functions prototypes for the FLASH firmware library
stm32f10x_fsmc.c [code] | This file provides all the FSMC firmware functions
stm32f10x_fsmc.h [code] | This file contains all the functions prototypes for the FSMC firmware library
stm32f10x_gpio.c [code] | This file provides all the GPIO firmware functions
stm32f10x_gpio.h [code] | This file contains all the functions prototypes for the GPIO firmware library
stm32f10x_i2c.c [code] | This file provides all the I2C firmware functions
stm32f10x_i2c.h [code] | This file contains all the functions prototypes for the I2C firmware library
stm32f10x_ip_dbg.c [code] | This file provides all peripherals pointers initialization
stm32f10x_ip_dbg.h [code] | This file contains the headers of the library peripherals Debug
STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/BKP/Backup_Data/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/BKP/Tamper/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/CortexM3/BitBand/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/CortexM3/MPU/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/DMA/FSMC/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/FLASH/Program/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/FSMC/NAND/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/FSMC/NOR/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/FSMC/OneNAND/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/FSMC/SRAM/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/GPIO/IOToggle/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/I2C/EEPROM/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/I2C/IOExpander/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/PWR/PVD/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/PWR/STANDBY/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/RTC/Calendar/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/SDIO/uSDCard/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/SPI/CRC/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/SPI/DMA/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/SysTick/TimeBase/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/TIM/6Steps/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/TIM/DMA/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/TIM/DMABurst/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/TIM/OCActive/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/TIM/OCInactive/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/TIM/OnePulse/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/TIM/PWM_Input/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/TIM/PWM_Output/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/USART/DMA_Polling/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/USART/HalfDuplex/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/USART/MultiProcessor/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/USART/Polling/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/USART/Printf/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/USART/Synchronous/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Template/stm32f10x_it.c [code] | Main Interrupt Service Routines. This file provides template for all exceptions handler and peripherals interrupt service routine
STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/BKP/Backup_Data/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/BKP/Tamper/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/CortexM3/BitBand/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/CortexM3/MPU/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/DMA/FSMC/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/FLASH/Program/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/FSMC/NAND/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/FSMC/NOR/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/FSMC/OneNAND/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/FSMC/SRAM/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/GPIO/IOToggle/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/I2C/EEPROM/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/I2C/IOExpander/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/PWR/PVD/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/PWR/STANDBY/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/RTC/Calendar/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/SDIO/uSDCard/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/SPI/CRC/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/SPI/DMA/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/SysTick/TimeBase/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/TIM/6Steps/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/TIM/DMA/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/TIM/DMABurst/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/TIM/OCActive/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/TIM/OCInactive/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/TIM/OnePulse/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/TIM/PWM_Input/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/TIM/PWM_Output/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/USART/DMA_Polling/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/USART/HalfDuplex/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/USART/MultiProcessor/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/USART/Polling/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/USART/Printf/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/USART/Synchronous/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
STM32F10x_StdPeriph_Template/stm32f10x_it.h [code] | This file contains the headers of the interrupt handlers
stm32f10x_iwdg.c [code] | This file provides all the IWDG firmware functions
stm32f10x_iwdg.h [code] | This file contains all the functions prototypes for the IWDG firmware library
stm32f10x_pwr.c [code] | This file provides all the PWR firmware functions
stm32f10x_pwr.h [code] | This file contains all the functions prototypes for the PWR firmware library
stm32f10x_rcc.c [code] | This file provides all the RCC firmware functions
stm32f10x_rcc.h [code] | This file contains all the functions prototypes for the RCC firmware library
stm32f10x_rtc.c [code] | This file provides all the RTC firmware functions
stm32f10x_rtc.h [code] | This file contains all the functions prototypes for the RTC firmware library
stm32f10x_sdio.c [code] | This file provides all the SDIO firmware functions
stm32f10x_sdio.h [code] | This file contains all the functions prototypes for the SDIO firmware library
stm32f10x_spi.c [code] | This file provides all the SPI firmware functions
stm32f10x_spi.h [code] | This file contains all the functions prototypes for the SPI firmware library
stm32f10x_tim.c [code] | This file provides all the TIM firmware functions
stm32f10x_tim.h [code] | This file contains all the functions prototypes for the TIM firmware library
stm32f10x_usart.c [code] | This file provides all the USART firmware functions
stm32f10x_usart.h [code] | This file contains all the functions prototypes for the USART firmware library
stm32f10x_wwdg.c [code] | This file provides all the WWDG firmware functions
stm32f10x_wwdg.h [code] | This file contains all the functions prototypes for the WWDG firmware library
stm32l152_eval.c [code] This file provides:

  • set of firmware functions to manage Leds, push-button and COM ports
  • low level initialization functions for SD card (on SPI) and temperature sensor (LM75) available on STM32L152-EVAL evaluation board RevB from STMicroelectronics
stm32l152_eval.h [code] | This file contains definitions for STM32L152_EVAL's Leds, push-buttons and COM ports hardware resources
stm32l152_eval_glass_lcd.c [code] | This file includes the LCD Glass driver for Pacific Display (LCD_PD878, PD878-DP-FH-W-LV-6-RH) Module of STM32L152-EVAL board RevB
stm32l152_eval_glass_lcd.h [code] | Header file for stm32l152_eval_glass_lcd.c module
stm32l152_eval_i2c_ee.c [code] | This file provides a set of functions needed to manage an I2C M24CXX EEPROM memory
stm32l152_eval_i2c_ee.h [code] | This file contains all the functions prototypes for the stm32l152_eval_i2c_ee firmware driver
stm32l152_eval_lcd.c [code] | This file includes the LCD driver for AM-240320L8TNQW00H (LCD_ILI9320), AM-240320LDTNQW00H (LCD_SPFD5408B) Liquid Crystal Display Module of STM32L152-EVAL board RevB
stm32l152_eval_lcd.h [code] | This file contains all the functions prototypes for the stm32l152_eval_lcd firmware driver
Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.c [code]
Project/STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/BKP/Backup_Data/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/BKP/Tamper/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/CAN/DualCAN/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/CAN/LoopBack/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/CAN/Networking/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/CortexM3/BitBand/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/CortexM3/MPU/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/DMA/FSMC/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/FLASH/Program/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/FSMC/NAND/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/FSMC/NOR/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/FSMC/OneNAND/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/GPIO/IOToggle/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/I2C/EEPROM/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/I2C/IOExpander/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/I2S/Interrupt/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/PWR/PVD/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/PWR/STANDBY/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/PWR/STOP/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/RTC/Calendar/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/SDIO/uSDCard/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/SPI/CRC/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/SPI/DMA/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/SysTick/TimeBase/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/TIM/6Steps/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/TIM/DMA/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/TIM/DMABurst/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/TIM/InputCapture/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/TIM/OCActive/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/TIM/OCInactive/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/TIM/OCToggle/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/TIM/OnePulse/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Input/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Output/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/TIM/TimeBase/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/USART/DMA_Polling/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/USART/HalfDuplex/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/USART/Interrupt/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/USART/MultiProcessor/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/USART/Polling/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/USART/Printf/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/USART/Smartcard/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/USART/Synchronous/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/system_stm32f10x.c [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
Project/STM32F10x_StdPeriph_Template/system_stm32f10x.c [code]
system_stm32f10x.h [code] | CMSIS Cortex-M3 Device Peripheral Access Layer System Header File


STM32F10x Standard Peripherals Firmware Library: main.h Source File

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • FLASH
  • Dual_Boot

FLASH/Dual_Boot/main.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    FLASH/Dual_Boot/main.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Header for main.c module
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __MAIN_H
00024 #define __MAIN_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028 #include "stm32_eval.h"
00029 #include "stm3210e_eval_lcd.h"
00030
00031 /* Exported types ------------------------------------------------------------*/
00032 /* Exported constants --------------------------------------------------------*/
00033 /* Exported macro ------------------------------------------------------------*/
00034 /* Exported functions ------------------------------------------------------- */
00035 void TimingDelay_Decrement(void);
00036
00037 #endif /* __MAIN_H */
00038
00039 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: fonts.c Source File

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • Common

fonts.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    fonts.c
00004   * @author  MCD Application Team
00005   * @version V4.5.0
00006   * @date    07-March-2011
00007   * @brief   This file provides text fonts for STM32xx-EVAL's LCD driver.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "fonts.h"
00024
00025 /** @addtogroup Utilities
00026   * @{
00027   */
00028
00029 /** @addtogroup STM32_EVAL
00030   * @{
00031   */
00032
00033 /** @addtogroup Common
00034   * @{
00035   */
00036
00037 /** @addtogroup FONTS
00038   * @brief      This file includes the Fonts driver of STM32-EVAL boards.
00039   * @{
00040   */
00041
00042 /** @defgroup FONTS_Private_Types
00043   * @{
00044   */
00045 /**
00046   * @}
00047   */
00048
00049
00050 /** @defgroup FONTS_Private_Defines
00051   * @{
00052   */
00053 /**
00054   * @}
00055   */
00056
00057
00058 /** @defgroup FONTS_Private_Macros
00059   * @{
00060   */
00061 /**
00062   * @}
00063   */
00064
00065
00066 /** @defgroup FONTS_Private_Variables
00067   * @{
00068   */
00069 const uint16_t ASCII16x24_Table [] = {
00070 /**
00071   * @brief        Space ' '
00072   */
00073          0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00074          0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00075          0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00076 /**
00077   * @brief        '!'
00078   */
00079          0x0000, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,
00080          0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0000, 0x0000,
00081          0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00082 /**
00083   * @brief        '"'
00084   */
00085          0x0000, 0x0000, 0x00CC, 0x00CC, 0x00CC, 0x00CC, 0x00CC, 0x00CC,
00086          0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00087          0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00088 /**
00089   * @brief        '#'
00090   */
00091          0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0C60, 0x0C60,
00092          0x0C60, 0x0630, 0x0630, 0x1FFE, 0x1FFE, 0x0630, 0x0738, 0x0318,
00093          0x1FFE, 0x1FFE, 0x0318, 0x0318, 0x018C, 0x018C, 0x018C, 0x0000,
00094 /**
00095   * @brief        '$'
00096   */
00097          0x0000, 0x0080, 0x03E0, 0x0FF8, 0x0E9C, 0x1C8C, 0x188C, 0x008C,
00098          0x0098, 0x01F8, 0x07E0, 0x0E80, 0x1C80, 0x188C, 0x188C, 0x189C,
00099          0x0CB8, 0x0FF0, 0x03E0, 0x0080, 0x0080, 0x0000, 0x0000, 0x0000,
00100 /**
00101   * @brief        '%'
00102   */
00103          0x0000, 0x0000, 0x0000, 0x180E, 0x0C1B, 0x0C11, 0x0611, 0x0611,
00104          0x0311, 0x0311, 0x019B, 0x018E, 0x38C0, 0x6CC0, 0x4460, 0x4460,
00105          0x4430, 0x4430, 0x4418, 0x6C18, 0x380C, 0x0000, 0x0000, 0x0000,
00106 /**
00107   * @brief        '&'
00108   */
00109          0x0000, 0x01E0, 0x03F0, 0x0738, 0x0618, 0x0618, 0x0330, 0x01F0,
00110          0x00F0, 0x00F8, 0x319C, 0x330E, 0x1E06, 0x1C06, 0x1C06, 0x3F06,
00111          0x73FC, 0x21F0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00112 /**
00113   * @brief        '''
00114   */
00115          0x0000, 0x0000, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C,
00116          0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00117          0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00118 /**
00119   * @brief        '('
00120   */
00121          0x0000, 0x0200, 0x0300, 0x0180, 0x00C0, 0x00C0, 0x0060, 0x0060,
00122          0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030,
00123          0x0060, 0x0060, 0x00C0, 0x00C0, 0x0180, 0x0300, 0x0200, 0x0000,
00124 /**
00125   * @brief        ')'
00126   */
00127          0x0000, 0x0020, 0x0060, 0x00C0, 0x0180, 0x0180, 0x0300, 0x0300,
00128          0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600,
00129          0x0300, 0x0300, 0x0180, 0x0180, 0x00C0, 0x0060, 0x0020, 0x0000,
00130 /**
00131   * @brief        '*'
00132   */
00133          0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x00C0, 0x00C0,
00134          0x06D8, 0x07F8, 0x01E0, 0x0330, 0x0738, 0x0000, 0x0000, 0x0000,
00135          0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00136 /**
00137   * @brief        '+'
00138   */
00139          0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0180, 0x0180,
00140          0x0180, 0x0180, 0x0180, 0x3FFC, 0x3FFC, 0x0180, 0x0180, 0x0180,
00141          0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00142 /**
00143   * @brief        ','
00144   */
00145          0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00146          0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00147          0x0000, 0x0180, 0x0180, 0x0100, 0x0100, 0x0080, 0x0000, 0x0000,
00148 /**
00149   * @brief        '-'
00150   */
00151          0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00152          0x0000, 0x0000, 0x0000, 0x0000, 0x07E0, 0x07E0, 0x0000, 0x0000,
00153          0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00154 /**
00155   * @brief        '.'
00156   */
00157          0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00158          0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00159          0x0000, 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00160 /**
00161   * @brief        '/'
00162   */
00163          0x0000, 0x0C00, 0x0C00, 0x0600, 0x0600, 0x0600, 0x0300, 0x0300,
00164          0x0300, 0x0380, 0x0180, 0x0180, 0x0180, 0x00C0, 0x00C0, 0x00C0,
00165          0x0060, 0x0060, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00166 /**
00167   * @brief        '0'
00168   */
00169          0x0000, 0x03E0, 0x07F0, 0x0E38, 0x0C18, 0x180C, 0x180C, 0x180C,
00170          0x180C, 0x180C, 0x180C, 0x180C, 0x180C, 0x180C, 0x0C18, 0x0E38,
00171          0x07F0, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00172 /**
00173   * @brief        '1'
00174   */
00175          0x0000, 0x0100, 0x0180, 0x01C0, 0x01F0, 0x0198, 0x0188, 0x0180,
00176          0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,
00177          0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00178 /**
00179   * @brief        '2'
00180   */
00181          0x0000, 0x03E0, 0x0FF8, 0x0C18, 0x180C, 0x180C, 0x1800, 0x1800,
00182          0x0C00, 0x0600, 0x0300, 0x0180, 0x00C0, 0x0060, 0x0030, 0x0018,
00183          0x1FFC, 0x1FFC, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00184 /**
00185   * @brief        '3'
00186   */
00187          0x0000, 0x01E0, 0x07F8, 0x0E18, 0x0C0C, 0x0C0C, 0x0C00, 0x0600,
00188          0x03C0, 0x07C0, 0x0C00, 0x1800, 0x1800, 0x180C, 0x180C, 0x0C18,
00189          0x07F8, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00190 /**
00191   * @brief        '4'
00192   */
00193          0x0000, 0x0C00, 0x0E00, 0x0F00, 0x0F00, 0x0D80, 0x0CC0, 0x0C60,
00194          0x0C60, 0x0C30, 0x0C18, 0x0C0C, 0x3FFC, 0x3FFC, 0x0C00, 0x0C00,
00195          0x0C00, 0x0C00, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00196 /**
00197   * @brief        '5'
00198   */
00199          0x0000, 0x0FF8, 0x0FF8, 0x0018, 0x0018, 0x000C, 0x03EC, 0x07FC,
00200          0x0E1C, 0x1C00, 0x1800, 0x1800, 0x1800, 0x180C, 0x0C1C, 0x0E18,
00201          0x07F8, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00202 /**
00203   * @brief        '6'
00204   */
00205          0x0000, 0x07C0, 0x0FF0, 0x1C38, 0x1818, 0x0018, 0x000C, 0x03CC,
00206          0x0FEC, 0x0E3C, 0x1C1C, 0x180C, 0x180C, 0x180C, 0x1C18, 0x0E38,
00207          0x07F0, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00208 /**
00209   * @brief        '7'
00210   */
00211          0x0000, 0x1FFC, 0x1FFC, 0x0C00, 0x0600, 0x0600, 0x0300, 0x0380,
00212          0x0180, 0x01C0, 0x00C0, 0x00E0, 0x0060, 0x0060, 0x0070, 0x0030,
00213          0x0030, 0x0030, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00214 /**
00215   * @brief        '8'
00216   */
00217          0x0000, 0x03E0, 0x07F0, 0x0E38, 0x0C18, 0x0C18, 0x0C18, 0x0638,
00218          0x07F0, 0x07F0, 0x0C18, 0x180C, 0x180C, 0x180C, 0x180C, 0x0C38,
00219          0x0FF8, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00220 /**
00221   * @brief        '9'
00222   */
00223          0x0000, 0x03E0, 0x07F0, 0x0E38, 0x0C1C, 0x180C, 0x180C, 0x180C,
00224          0x1C1C, 0x1E38, 0x1BF8, 0x19E0, 0x1800, 0x0C00, 0x0C00, 0x0E1C,
00225          0x07F8, 0x01F0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00226 /**
00227   * @brief        ':'
00228   */
00229          0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0180, 0x0180,
00230          0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00231          0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00232 /**
00233   * @brief        ';'
00234   */
00235          0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0180, 0x0180,
00236          0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00237          0x0180, 0x0180, 0x0100, 0x0100, 0x0080, 0x0000, 0x0000, 0x0000,
00238 /**
00239   * @brief        '<'
00240   */
00241          0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00242          0x1000, 0x1C00, 0x0F80, 0x03E0, 0x00F8, 0x0018, 0x00F8, 0x03E0,
00243          0x0F80, 0x1C00, 0x1000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00244 /**
00245   * @brief        '='
00246   */
00247          0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00248          0x1FF8, 0x0000, 0x0000, 0x0000, 0x1FF8, 0x0000, 0x0000, 0x0000,
00249          0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00250 /**
00251   * @brief        '>'
00252   */
00253          0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00254          0x0008, 0x0038, 0x01F0, 0x07C0, 0x1F00, 0x1800, 0x1F00, 0x07C0,
00255          0x01F0, 0x0038, 0x0008, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00256 /**
00257   * @brief        '?'
00258   */
00259          0x0000, 0x03E0, 0x0FF8, 0x0C18, 0x180C, 0x180C, 0x1800, 0x0C00,
00260          0x0600, 0x0300, 0x0180, 0x00C0, 0x00C0, 0x00C0, 0x0000, 0x0000,
00261          0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00262 /**
00263   * @brief        '@'
00264   */
00265          0x0000, 0x0000, 0x07E0, 0x1818, 0x2004, 0x29C2, 0x4A22, 0x4411,
00266          0x4409, 0x4409, 0x4409, 0x2209, 0x1311, 0x0CE2, 0x4002, 0x2004,
00267          0x1818, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00268 /**
00269   * @brief        'A'
00270   */
00271          0x0000, 0x0380, 0x0380, 0x06C0, 0x06C0, 0x06C0, 0x0C60, 0x0C60,
00272          0x1830, 0x1830, 0x1830, 0x3FF8, 0x3FF8, 0x701C, 0x600C, 0x600C,
00273          0xC006, 0xC006, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00274 /**
00275   * @brief        'B'
00276   */
00277          0x0000, 0x03FC, 0x0FFC, 0x0C0C, 0x180C, 0x180C, 0x180C, 0x0C0C,
00278          0x07FC, 0x0FFC, 0x180C, 0x300C, 0x300C, 0x300C, 0x300C, 0x180C,
00279          0x1FFC, 0x07FC, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00280 /**
00281   * @brief        'C'
00282   */
00283          0x0000, 0x07C0, 0x1FF0, 0x3838, 0x301C, 0x700C, 0x6006, 0x0006,
00284          0x0006, 0x0006, 0x0006, 0x0006, 0x0006, 0x6006, 0x700C, 0x301C,
00285          0x1FF0, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00286 /**
00287   * @brief        'D'
00288   */
00289          0x0000, 0x03FE, 0x0FFE, 0x0E06, 0x1806, 0x1806, 0x3006, 0x3006,
00290          0x3006, 0x3006, 0x3006, 0x3006, 0x3006, 0x1806, 0x1806, 0x0E06,
00291          0x0FFE, 0x03FE, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00292 /**
00293   * @brief        'E'
00294   */
00295          0x0000, 0x3FFC, 0x3FFC, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C,
00296          0x1FFC, 0x1FFC, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C,
00297          0x3FFC, 0x3FFC, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00298 /**
00299   * @brief        'F'
00300   */
00301          0x0000, 0x3FF8, 0x3FF8, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018,
00302          0x1FF8, 0x1FF8, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018,
00303          0x0018, 0x0018, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00304 /**
00305   * @brief        'G'
00306   */
00307          0x0000, 0x0FE0, 0x3FF8, 0x783C, 0x600E, 0xE006, 0xC007, 0x0003,
00308          0x0003, 0xFE03, 0xFE03, 0xC003, 0xC007, 0xC006, 0xC00E, 0xF03C,
00309          0x3FF8, 0x0FE0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00310 /**
00311   * @brief        'H'
00312   */
00313          0x0000, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C,
00314          0x3FFC, 0x3FFC, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C,
00315          0x300C, 0x300C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00316 /**
00317   * @brief        'I'
00318   */
00319          0x0000, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,
00320          0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,
00321          0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00322 /**
00323   * @brief        'J'
00324   */
00325          0x0000, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600,
00326          0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0618, 0x0618, 0x0738,
00327          0x03F0, 0x01E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00328 /**
00329   * @brief        'K'
00330   */
00331          0x0000, 0x3006, 0x1806, 0x0C06, 0x0606, 0x0306, 0x0186, 0x00C6,
00332          0x0066, 0x0076, 0x00DE, 0x018E, 0x0306, 0x0606, 0x0C06, 0x1806,
00333          0x3006, 0x6006, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00334 /**
00335   * @brief        'L'
00336   */
00337          0x0000, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018,
00338          0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018,
00339          0x1FF8, 0x1FF8, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00340 /**
00341   * @brief        'M'
00342   */
00343          0x0000, 0xE00E, 0xF01E, 0xF01E, 0xF01E, 0xD836, 0xD836, 0xD836,
00344          0xD836, 0xCC66, 0xCC66, 0xCC66, 0xC6C6, 0xC6C6, 0xC6C6, 0xC6C6,
00345          0xC386, 0xC386, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00346 /**
00347   * @brief        'N'
00348   */
00349          0x0000, 0x300C, 0x301C, 0x303C, 0x303C, 0x306C, 0x306C, 0x30CC,
00350          0x30CC, 0x318C, 0x330C, 0x330C, 0x360C, 0x360C, 0x3C0C, 0x3C0C,
00351          0x380C, 0x300C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00352 /**
00353   * @brief        'O'
00354   */
00355          0x0000, 0x07E0, 0x1FF8, 0x381C, 0x700E, 0x6006, 0xC003, 0xC003,
00356          0xC003, 0xC003, 0xC003, 0xC003, 0xC003, 0x6006, 0x700E, 0x381C,
00357          0x1FF8, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00358 /**
00359   * @brief        'P'
00360   */
00361          0x0000, 0x0FFC, 0x1FFC, 0x380C, 0x300C, 0x300C, 0x300C, 0x300C,
00362          0x180C, 0x1FFC, 0x07FC, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C,
00363          0x000C, 0x000C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00364 /**
00365   * @brief        'Q'
00366   */
00367          0x0000, 0x07E0, 0x1FF8, 0x381C, 0x700E, 0x6006, 0xE003, 0xC003,
00368          0xC003, 0xC003, 0xC003, 0xC003, 0xE007, 0x6306, 0x3F0E, 0x3C1C,
00369          0x3FF8, 0xF7E0, 0xC000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00370 /**
00371   * @brief        'R'
00372   */
00373          0x0000, 0x0FFE, 0x1FFE, 0x3806, 0x3006, 0x3006, 0x3006, 0x3806,
00374          0x1FFE, 0x07FE, 0x0306, 0x0606, 0x0C06, 0x1806, 0x1806, 0x3006,
00375          0x3006, 0x6006, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00376 /**
00377   * @brief        'S'
00378   */
00379          0x0000, 0x03E0, 0x0FF8, 0x0C1C, 0x180C, 0x180C, 0x000C, 0x001C,
00380          0x03F8, 0x0FE0, 0x1E00, 0x3800, 0x3006, 0x3006, 0x300E, 0x1C1C,
00381          0x0FF8, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00382 /**
00383   * @brief        'T'
00384   */
00385          0x0000, 0x7FFE, 0x7FFE, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,
00386          0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,
00387          0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00388 /**
00389   * @brief        'U'
00390   */
00391          0x0000, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C,
00392          0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x1818,
00393          0x1FF8, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00394 /**
00395   * @brief        'V'
00396   */
00397          0x0000, 0x6003, 0x3006, 0x3006, 0x3006, 0x180C, 0x180C, 0x180C,
00398          0x0C18, 0x0C18, 0x0E38, 0x0630, 0x0630, 0x0770, 0x0360, 0x0360,
00399          0x01C0, 0x01C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00400 /**
00401   * @brief        'W'
00402   */
00403          0x0000, 0x6003, 0x61C3, 0x61C3, 0x61C3, 0x3366, 0x3366, 0x3366,
00404          0x3366, 0x3366, 0x3366, 0x1B6C, 0x1B6C, 0x1B6C, 0x1A2C, 0x1E3C,
00405          0x0E38, 0x0E38, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00406 /**
00407   * @brief        'X'
00408   */
00409          0x0000, 0xE00F, 0x700C, 0x3018, 0x1830, 0x0C70, 0x0E60, 0x07C0,
00410          0x0380, 0x0380, 0x03C0, 0x06E0, 0x0C70, 0x1C30, 0x1818, 0x300C,
00411          0x600E, 0xE007, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00412 /**
00413   * @brief        'Y'
00414   */
00415          0x0000, 0xC003, 0x6006, 0x300C, 0x381C, 0x1838, 0x0C30, 0x0660,
00416          0x07E0, 0x03C0, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,
00417          0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00418 /**
00419   * @brief        'Z'
00420   */
00421          0x0000, 0x7FFC, 0x7FFC, 0x6000, 0x3000, 0x1800, 0x0C00, 0x0600,
00422          0x0300, 0x0180, 0x00C0, 0x0060, 0x0030, 0x0018, 0x000C, 0x0006,
00423          0x7FFE, 0x7FFE, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00424 /**
00425   * @brief        '['
00426   */
00427          0x0000, 0x03E0, 0x03E0, 0x0060, 0x0060, 0x0060, 0x0060, 0x0060,
00428          0x0060, 0x0060, 0x0060, 0x0060, 0x0060, 0x0060, 0x0060, 0x0060,
00429          0x0060, 0x0060, 0x0060, 0x0060, 0x0060, 0x03E0, 0x03E0, 0x0000,
00430 /**
00431   * @brief        '\'
00432   */
00433          0x0000, 0x0030, 0x0030, 0x0060, 0x0060, 0x0060, 0x00C0, 0x00C0,
00434          0x00C0, 0x01C0, 0x0180, 0x0180, 0x0180, 0x0300, 0x0300, 0x0300,
00435          0x0600, 0x0600, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00436 /**
00437   * @brief        ']'
00438   */
00439          0x0000, 0x03E0, 0x03E0, 0x0300, 0x0300, 0x0300, 0x0300, 0x0300,
00440          0x0300, 0x0300, 0x0300, 0x0300, 0x0300, 0x0300, 0x0300, 0x0300,
00441          0x0300, 0x0300, 0x0300, 0x0300, 0x0300, 0x03E0, 0x03E0, 0x0000,
00442 /**
00443   * @brief        '^'
00444   */
00445          0x0000, 0x0000, 0x01C0, 0x01C0, 0x0360, 0x0360, 0x0360, 0x0630,
00446          0x0630, 0x0C18, 0x0C18, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00447          0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00448 /**
00449   * @brief        '_'
00450   */
00451          0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00452          0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00453          0x0000, 0xFFFF, 0xFFFF, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00454 /**
00455   * @brief        '''
00456   */
00457          0x0000, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x0000,
00458          0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00459          0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00460 /**
00461   * @brief        'a'
00462   */
00463          0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03F0, 0x07F8,
00464          0x0C1C, 0x0C0C, 0x0F00, 0x0FF0, 0x0CF8, 0x0C0C, 0x0C0C, 0x0F1C,
00465          0x0FF8, 0x18F0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00466 /**
00467   * @brief        'b'
00468   */
00469          0x0000, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x03D8, 0x0FF8,
00470          0x0C38, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x0C38,
00471          0x0FF8, 0x03D8, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00472 /**
00473   * @brief        'c'
00474   */
00475          0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03C0, 0x07F0,
00476          0x0E30, 0x0C18, 0x0018, 0x0018, 0x0018, 0x0018, 0x0C18, 0x0E30,
00477          0x07F0, 0x03C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00478 /**
00479   * @brief        'd'
00480   */
00481          0x0000, 0x1800, 0x1800, 0x1800, 0x1800, 0x1800, 0x1BC0, 0x1FF0,
00482          0x1C30, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1C30,
00483          0x1FF0, 0x1BC0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00484 /**
00485   * @brief        'e'
00486   */
00487          0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03C0, 0x0FF0,
00488          0x0C30, 0x1818, 0x1FF8, 0x1FF8, 0x0018, 0x0018, 0x1838, 0x1C30,
00489          0x0FF0, 0x07C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00490 /**
00491   * @brief        'f'
00492   */
00493          0x0000, 0x0F80, 0x0FC0, 0x00C0, 0x00C0, 0x00C0, 0x07F0, 0x07F0,
00494          0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,
00495          0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00496 /**
00497   * @brief        'g'
00498   */
00499          0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0DE0, 0x0FF8,
00500          0x0E18, 0x0C0C, 0x0C0C, 0x0C0C, 0x0C0C, 0x0C0C, 0x0C0C, 0x0E18,
00501          0x0FF8, 0x0DE0, 0x0C00, 0x0C0C, 0x061C, 0x07F8, 0x01F0, 0x0000,
00502 /**
00503   * @brief        'h'
00504   */
00505          0x0000, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x07D8, 0x0FF8,
00506          0x1C38, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818,
00507          0x1818, 0x1818, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00508 /**
00509   * @brief        'i'
00510   */
00511          0x0000, 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x00C0, 0x00C0,
00512          0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,
00513          0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00514 /**
00515   * @brief        'j'
00516   */
00517          0x0000, 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x00C0, 0x00C0,
00518          0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,
00519          0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00F8, 0x0078, 0x0000,
00520 /**
00521   * @brief        'k'
00522   */
00523          0x0000, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x0C0C, 0x060C,
00524          0x030C, 0x018C, 0x00CC, 0x006C, 0x00FC, 0x019C, 0x038C, 0x030C,
00525          0x060C, 0x0C0C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00526 /**
00527   * @brief        'l'
00528   */
00529          0x0000, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,
00530          0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,
00531          0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00532 /**
00533   * @brief        'm'
00534   */
00535          0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x3C7C, 0x7EFF,
00536          0xE3C7, 0xC183, 0xC183, 0xC183, 0xC183, 0xC183, 0xC183, 0xC183,
00537          0xC183, 0xC183, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00538 /**
00539   * @brief        'n'
00540   */
00541          0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0798, 0x0FF8,
00542          0x1C38, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818,
00543          0x1818, 0x1818, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00544 /**
00545   * @brief        'o'
00546   */
00547          0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03C0, 0x0FF0,
00548          0x0C30, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x0C30,
00549          0x0FF0, 0x03C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00550 /**
00551   * @brief        'p'
00552   */
00553          0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03D8, 0x0FF8,
00554          0x0C38, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x0C38,
00555          0x0FF8, 0x03D8, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0000,
00556 /**
00557   * @brief        'q'
00558   */
00559          0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1BC0, 0x1FF0,
00560          0x1C30, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1C30,
00561          0x1FF0, 0x1BC0, 0x1800, 0x1800, 0x1800, 0x1800, 0x1800, 0x0000,
00562 /**
00563   * @brief        'r'
00564   */
00565          0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x07B0, 0x03F0,
00566          0x0070, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030,
00567          0x0030, 0x0030, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00568 /**
00569   * @brief        's'
00570   */
00571          0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03E0, 0x03F0,
00572          0x0E38, 0x0C18, 0x0038, 0x03F0, 0x07C0, 0x0C00, 0x0C18, 0x0E38,
00573          0x07F0, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00574 /**
00575   * @brief        't'
00576   */
00577          0x0000, 0x0000, 0x0080, 0x00C0, 0x00C0, 0x00C0, 0x07F0, 0x07F0,
00578          0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,
00579          0x07C0, 0x0780, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00580 /**
00581   * @brief        'u'
00582   */
00583          0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1818, 0x1818,
00584          0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1C38,
00585          0x1FF0, 0x19E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00586 /**
00587   * @brief        'v'
00588   */
00589          0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x180C, 0x0C18,
00590          0x0C18, 0x0C18, 0x0630, 0x0630, 0x0630, 0x0360, 0x0360, 0x0360,
00591          0x01C0, 0x01C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00592 /**
00593   * @brief        'w'
00594   */
00595          0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x41C1, 0x41C1,
00596          0x61C3, 0x6363, 0x6363, 0x6363, 0x3636, 0x3636, 0x3636, 0x1C1C,
00597          0x1C1C, 0x1C1C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00598 /**
00599   * @brief        'x'
00600   */
00601          0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x381C, 0x1C38,
00602          0x0C30, 0x0660, 0x0360, 0x0360, 0x0360, 0x0360, 0x0660, 0x0C30,
00603          0x1C38, 0x381C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00604 /**
00605   * @brief        'y'
00606   */
00607          0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x3018, 0x1830,
00608          0x1830, 0x1870, 0x0C60, 0x0C60, 0x0CE0, 0x06C0, 0x06C0, 0x0380,
00609          0x0380, 0x0380, 0x0180, 0x0180, 0x01C0, 0x00F0, 0x0070, 0x0000,
00610 /**
00611   * @brief        'z'
00612   */
00613          0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1FFC, 0x1FFC,
00614          0x0C00, 0x0600, 0x0300, 0x0180, 0x00C0, 0x0060, 0x0030, 0x0018,
00615          0x1FFC, 0x1FFC, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00616 /**
00617   * @brief        '{'
00618   */
00619          0x0000, 0x0300, 0x0180, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,
00620          0x00C0, 0x0060, 0x0060, 0x0030, 0x0060, 0x0040, 0x00C0, 0x00C0,
00621          0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x0180, 0x0300, 0x0000, 0x0000,
00622 /**
00623   * @brief        '|'
00624   */
00625          0x0000, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,
00626          0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,
00627          0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0000,
00628 /**
00629   * @brief        '}'
00630   */
00631          0x0000, 0x0060, 0x00C0, 0x01C0, 0x0180, 0x0180, 0x0180, 0x0180,
00632          0x0180, 0x0300, 0x0300, 0x0600, 0x0300, 0x0100, 0x0180, 0x0180,
00633          0x0180, 0x0180, 0x0180, 0x0180, 0x00C0, 0x0060, 0x0000, 0x0000,
00634 /**
00635   * @brief        '~'
00636   */
00637          0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00638          0x10F0, 0x1FF8, 0x0F08, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
00639          0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000};
00640
00641 const uint16_t ASCII12x12_Table [] = {
00642     0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
00643     0x0000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x0000,0x2000,0x0000,0x0000,
00644     0x0000,0x5000,0x5000,0x5000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
00645     0x0000,0x0900,0x0900,0x1200,0x7f00,0x1200,0x7f00,0x1200,0x2400,0x2400,0x0000,0x0000,
00646     0x1000,0x3800,0x5400,0x5000,0x5000,0x3800,0x1400,0x5400,0x5400,0x3800,0x1000,0x0000,
00647     0x0000,0x3080,0x4900,0x4900,0x4a00,0x32c0,0x0520,0x0920,0x0920,0x10c0,0x0000,0x0000,
00648     0x0000,0x0c00,0x1200,0x1200,0x1400,0x1800,0x2500,0x2300,0x2300,0x1d80,0x0000,0x0000,
00649     0x0000,0x4000,0x4000,0x4000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
00650     0x0000,0x0800,0x1000,0x1000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x1000,0x1000,
00651     0x0000,0x4000,0x2000,0x2000,0x1000,0x1000,0x1000,0x1000,0x1000,0x1000,0x2000,0x2000,
00652     0x0000,0x2000,0x7000,0x2000,0x5000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
00653     0x0000,0x0000,0x0000,0x0800,0x0800,0x7f00,0x0800,0x0800,0x0000,0x0000,0x0000,0x0000,
00654     0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x2000,0x2000,0x4000,
00655     0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x7000,0x0000,0x0000,0x0000,0x0000,0x0000,
00656     0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x2000,0x0000,0x0000,
00657     0x0000,0x1000,0x1000,0x1000,0x2000,0x2000,0x2000,0x2000,0x4000,0x4000,0x0000,0x0000,
00658     0x0000,0x1000,0x2800,0x4400,0x4400,0x4400,0x4400,0x4400,0x2800,0x1000,0x0000,0x0000,
00659     0x0000,0x1000,0x3000,0x5000,0x1000,0x1000,0x1000,0x1000,0x1000,0x1000,0x0000,0x0000,
00660     0x0000,0x3000,0x4800,0x4400,0x0400,0x0800,0x1000,0x2000,0x4000,0x7c00,0x0000,0x0000,
00661     0x0000,0x3000,0x4800,0x0400,0x0800,0x1000,0x0800,0x4400,0x4800,0x3000,0x0000,0x0000,
00662     0x0000,0x0800,0x1800,0x1800,0x2800,0x2800,0x4800,0x7c00,0x0800,0x0800,0x0000,0x0000,
00663     0x0000,0x3c00,0x2000,0x4000,0x7000,0x4800,0x0400,0x4400,0x4800,0x3000,0x0000,0x0000,
00664     0x0000,0x1800,0x2400,0x4000,0x5000,0x6800,0x4400,0x4400,0x2800,0x1000,0x0000,0x0000,
00665     0x0000,0x7c00,0x0400,0x0800,0x1000,0x1000,0x1000,0x2000,0x2000,0x2000,0x0000,0x0000,
00666     0x0000,0x1000,0x2800,0x4400,0x2800,0x1000,0x2800,0x4400,0x2800,0x1000,0x0000,0x0000,
00667     0x0000,0x1000,0x2800,0x4400,0x4400,0x2c00,0x1400,0x0400,0x4800,0x3000,0x0000,0x0000,
00668     0x0000,0x0000,0x0000,0x2000,0x0000,0x0000,0x0000,0x0000,0x0000,0x2000,0x0000,0x0000,
00669     0x0000,0x0000,0x0000,0x2000,0x0000,0x0000,0x0000,0x0000,0x0000,0x2000,0x2000,0x4000,
00670     0x0000,0x0000,0x0400,0x0800,0x3000,0x4000,0x3000,0x0800,0x0400,0x0000,0x0000,0x0000,
00671     0x0000,0x0000,0x0000,0x7c00,0x0000,0x0000,0x7c00,0x0000,0x0000,0x0000,0x0000,0x0000,
00672     0x0000,0x0000,0x4000,0x2000,0x1800,0x0400,0x1800,0x2000,0x4000,0x0000,0x0000,0x0000,
00673     0x0000,0x3800,0x6400,0x4400,0x0400,0x0800,0x1000,0x1000,0x0000,0x1000,0x0000,0x0000,
00674     0x0000,0x0f80,0x1040,0x2ea0,0x51a0,0x5120,0x5120,0x5120,0x5320,0x4dc0,0x2020,0x1040,
00675     0x0000,0x0800,0x1400,0x1400,0x1400,0x2200,0x3e00,0x2200,0x4100,0x4100,0x0000,0x0000,
00676     0x0000,0x3c00,0x2200,0x2200,0x2200,0x3c00,0x2200,0x2200,0x2200,0x3c00,0x0000,0x0000,
00677     0x0000,0x0e00,0x1100,0x2100,0x2000,0x2000,0x2000,0x2100,0x1100,0x0e00,0x0000,0x0000,
00678     0x0000,0x3c00,0x2200,0x2100,0x2100,0x2100,0x2100,0x2100,0x2200,0x3c00,0x0000,0x0000,
00679     0x0000,0x3e00,0x2000,0x2000,0x2000,0x3e00,0x2000,0x2000,0x2000,0x3e00,0x0000,0x0000,
00680     0x0000,0x3e00,0x2000,0x2000,0x2000,0x3c00,0x2000,0x2000,0x2000,0x2000,0x0000,0x0000,
00681     0x0000,0x0e00,0x1100,0x2100,0x2000,0x2700,0x2100,0x2100,0x1100,0x0e00,0x0000,0x0000,
00682     0x0000,0x2100,0x2100,0x2100,0x2100,0x3f00,0x2100,0x2100,0x2100,0x2100,0x0000,0x0000,
00683     0x0000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x0000,0x0000,
00684     0x0000,0x0800,0x0800,0x0800,0x0800,0x0800,0x0800,0x4800,0x4800,0x3000,0x0000,0x0000,
00685     0x0000,0x2200,0x2400,0x2800,0x2800,0x3800,0x2800,0x2400,0x2400,0x2200,0x0000,0x0000,
00686     0x0000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x3e00,0x0000,0x0000,
00687     0x0000,0x2080,0x3180,0x3180,0x3180,0x2a80,0x2a80,0x2a80,0x2a80,0x2480,0x0000,0x0000,
00688     0x0000,0x2100,0x3100,0x3100,0x2900,0x2900,0x2500,0x2300,0x2300,0x2100,0x0000,0x0000,
00689     0x0000,0x0c00,0x1200,0x2100,0x2100,0x2100,0x2100,0x2100,0x1200,0x0c00,0x0000,0x0000,
00690     0x0000,0x3c00,0x2200,0x2200,0x2200,0x3c00,0x2000,0x2000,0x2000,0x2000,0x0000,0x0000,
00691     0x0000,0x0c00,0x1200,0x2100,0x2100,0x2100,0x2100,0x2100,0x1600,0x0d00,0x0100,0x0000,
00692     0x0000,0x3e00,0x2100,0x2100,0x2100,0x3e00,0x2400,0x2200,0x2100,0x2080,0x0000,0x0000,
00693     0x0000,0x1c00,0x2200,0x2200,0x2000,0x1c00,0x0200,0x2200,0x2200,0x1c00,0x0000,0x0000,
00694     0x0000,0x3e00,0x0800,0x0800,0x0800,0x0800,0x0800,0x0800,0x0800,0x0800,0x0000,0x0000,
00695     0x0000,0x2100,0x2100,0x2100,0x2100,0x2100,0x2100,0x2100,0x1200,0x0c00,0x0000,0x0000,
00696     0x0000,0x4100,0x4100,0x2200,0x2200,0x2200,0x1400,0x1400,0x1400,0x0800,0x0000,0x0000,
00697     0x0000,0x4440,0x4a40,0x2a40,0x2a80,0x2a80,0x2a80,0x2a80,0x2a80,0x1100,0x0000,0x0000,
00698     0x0000,0x4100,0x2200,0x1400,0x1400,0x0800,0x1400,0x1400,0x2200,0x4100,0x0000,0x0000,
00699     0x0000,0x4100,0x2200,0x2200,0x1400,0x0800,0x0800,0x0800,0x0800,0x0800,0x0000,0x0000,
00700     0x0000,0x7e00,0x0200,0x0400,0x0800,0x1000,0x1000,0x2000,0x4000,0x7e00,0x0000,0x0000,
00701     0x0000,0x3000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,
00702     0x0000,0x4000,0x4000,0x2000,0x2000,0x2000,0x2000,0x2000,0x1000,0x1000,0x0000,0x0000,
00703     0x0000,0x6000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,
00704     0x0000,0x1000,0x2800,0x2800,0x2800,0x4400,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
00705     0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x7e00,
00706     0x4000,0x2000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
00707     0x0000,0x0000,0x0000,0x3800,0x4400,0x0400,0x3c00,0x4400,0x4400,0x3c00,0x0000,0x0000,
00708     0x0000,0x4000,0x4000,0x5800,0x6400,0x4400,0x4400,0x4400,0x6400,0x5800,0x0000,0x0000,
00709     0x0000,0x0000,0x0000,0x3000,0x4800,0x4000,0x4000,0x4000,0x4800,0x3000,0x0000,0x0000,
00710     0x0000,0x0400,0x0400,0x3400,0x4c00,0x4400,0x4400,0x4400,0x4c00,0x3400,0x0000,0x0000,
00711     0x0000,0x0000,0x0000,0x3800,0x4400,0x4400,0x7c00,0x4000,0x4400,0x3800,0x0000,0x0000,
00712     0x0000,0x6000,0x4000,0xe000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x0000,0x0000,
00713     0x0000,0x0000,0x0000,0x3400,0x4c00,0x4400,0x4400,0x4400,0x4c00,0x3400,0x0400,0x4400,
00714     0x0000,0x4000,0x4000,0x5800,0x6400,0x4400,0x4400,0x4400,0x4400,0x4400,0x0000,0x0000,
00715     0x0000,0x4000,0x0000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x0000,0x0000,
00716     0x0000,0x4000,0x0000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,
00717     0x0000,0x4000,0x4000,0x4800,0x5000,0x6000,0x5000,0x5000,0x4800,0x4800,0x0000,0x0000,
00718     0x0000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x0000,0x0000,
00719     0x0000,0x0000,0x0000,0x5200,0x6d00,0x4900,0x4900,0x4900,0x4900,0x4900,0x0000,0x0000,
00720     0x0000,0x0000,0x0000,0x5800,0x6400,0x4400,0x4400,0x4400,0x4400,0x4400,0x0000,0x0000,
00721     0x0000,0x0000,0x0000,0x3800,0x4400,0x4400,0x4400,0x4400,0x4400,0x3800,0x0000,0x0000,
00722     0x0000,0x0000,0x0000,0x5800,0x6400,0x4400,0x4400,0x4400,0x6400,0x5800,0x4000,0x4000,
00723     0x0000,0x0000,0x0000,0x3400,0x4c00,0x4400,0x4400,0x4400,0x4c00,0x3400,0x0400,0x0400,
00724     0x0000,0x0000,0x0000,0x5000,0x6000,0x4000,0x4000,0x4000,0x4000,0x4000,0x0000,0x0000,
00725     0x0000,0x0000,0x0000,0x3000,0x4800,0x4000,0x3000,0x0800,0x4800,0x3000,0x0000,0x0000,
00726     0x0000,0x4000,0x4000,0xe000,0x4000,0x4000,0x4000,0x4000,0x4000,0x6000,0x0000,0x0000,
00727     0x0000,0x0000,0x0000,0x4400,0x4400,0x4400,0x4400,0x4400,0x4c00,0x3400,0x0000,0x0000,
00728     0x0000,0x0000,0x0000,0x4400,0x4400,0x2800,0x2800,0x2800,0x2800,0x1000,0x0000,0x0000,
00729     0x0000,0x0000,0x0000,0x4900,0x4900,0x5500,0x5500,0x5500,0x5500,0x2200,0x0000,0x0000,
00730     0x0000,0x0000,0x0000,0x4400,0x2800,0x2800,0x1000,0x2800,0x2800,0x4400,0x0000,0x0000,
00731     0x0000,0x0000,0x0000,0x4400,0x4400,0x2800,0x2800,0x2800,0x1000,0x1000,0x1000,0x1000,
00732     0x0000,0x0000,0x0000,0x7800,0x0800,0x1000,0x2000,0x2000,0x4000,0x7800,0x0000,0x0000,
00733     0x0000,0x1000,0x2000,0x2000,0x2000,0x2000,0x4000,0x2000,0x2000,0x2000,0x2000,0x2000,
00734     0x0000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,
00735     0x0000,0x4000,0x2000,0x2000,0x2000,0x2000,0x1000,0x2000,0x2000,0x2000,0x2000,0x2000,
00736     0x0000,0x0000,0x0000,0x0000,0x7400,0x5800,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
00737     0x0000,0x0000,0x7000,0x5000,0x5000,0x5000,0x5000,0x5000,0x5000,0x7000,0x0000,0x0000};
00738
00739 const uint16_t ASCII8x12_Table [] = {
00740     0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
00741     0x00,0x00,0x00,0x10,0x10,0x10,0x10,0x10,0x10,0x00,0x10,0x00,
00742     0x00,0x00,0x00,0x28,0x28,0x28,0x00,0x00,0x00,0x00,0x00,0x00,
00743     0x00,0x00,0x00,0x14,0x14,0x3e,0x14,0x28,0x7c,0x28,0x28,0x00,
00744     0x00,0x00,0x10,0x38,0x54,0x50,0x38,0x14,0x14,0x54,0x38,0x10,
00745     0x00,0x00,0x00,0x44,0xa8,0xa8,0x50,0x14,0x1a,0x2a,0x24,0x00,
00746     0x00,0x00,0x00,0x20,0x50,0x50,0x20,0xe8,0x98,0x98,0x60,0x00,
00747     0x00,0x00,0x00,0x80,0x80,0x80,0x00,0x00,0x00,0x00,0x00,0x00,
00748     0x00,0x00,0x00,0x40,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,
00749     0x00,0x00,0x00,0x80,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,
00750     0x00,0x00,0x00,0x40,0xe0,0x40,0xa0,0x00,0x00,0x00,0x00,0x00,
00751     0x00,0x00,0x00,0x00,0x00,0x20,0x20,0xf8,0x20,0x20,0x00,0x00,
00752     0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x40,
00753     0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xc0,0x00,0x00,0x00,
00754     0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x00,
00755     0x00,0x00,0x00,0x20,0x20,0x20,0x40,0x40,0x80,0x80,0x80,0x00,
00756     0x00,0x00,0x00,0x60,0x90,0x90,0x90,0x90,0x90,0x90,0x60,0x00,
00757     0x00,0x00,0x00,0x20,0x60,0xa0,0x20,0x20,0x20,0x20,0x20,0x00,
00758     0x00,0x00,0x00,0x60,0x90,0x10,0x10,0x20,0x40,0x80,0xf0,0x00,
00759     0x00,0x00,0x00,0x60,0x90,0x10,0x60,0x10,0x10,0x90,0x60,0x00,
00760     0x00,0x00,0x00,0x10,0x30,0x50,0x50,0x90,0xf8,0x10,0x10,0x00,
00761     0x00,0x00,0x00,0x70,0x40,0x80,0xe0,0x10,0x10,0x90,0x60,0x00,
00762     0x00,0x00,0x00,0x60,0x90,0x80,0xa0,0xd0,0x90,0x90,0x60,0x00,
00763     0x00,0x00,0x00,0xf0,0x10,0x20,0x20,0x20,0x40,0x40,0x40,0x00,
00764     0x00,0x00,0x00,0x60,0x90,0x90,0x60,0x90,0x90,0x90,0x60,0x00,
00765     0x00,0x00,0x00,0x60,0x90,0x90,0xb0,0x50,0x10,0x90,0x60,0x00,
00766     0x00,0x00,0x00,0x00,0x00,0x40,0x00,0x00,0x00,0x00,0x40,0x00,
00767     0x00,0x00,0x00,0x00,0x00,0x40,0x00,0x00,0x00,0x00,0x40,0x40,
00768     0x00,0x00,0x00,0x00,0x00,0x10,0x60,0x80,0x60,0x10,0x00,0x00,
00769     0x00,0x00,0x00,0x00,0x00,0x00,0xf0,0x00,0xf0,0x00,0x00,0x00,
00770     0x00,0x00,0x00,0x00,0x00,0x80,0x60,0x10,0x60,0x80,0x00,0x00,
00771     0x00,0x00,0x00,0x60,0x90,0x10,0x20,0x40,0x40,0x00,0x40,0x00,
00772     0x00,0x00,0x00,0x1c,0x22,0x5b,0xa5,0xa5,0xa5,0xa5,0x9e,0x41,
00773     0x00,0x00,0x00,0x20,0x50,0x50,0x50,0x50,0x70,0x88,0x88,0x00,
00774     0x00,0x00,0x00,0xf0,0x88,0x88,0xf0,0x88,0x88,0x88,0xf0,0x00,
00775     0x00,0x00,0x00,0x38,0x44,0x84,0x80,0x80,0x84,0x44,0x38,0x00,
00776     0x00,0x00,0x00,0xe0,0x90,0x88,0x88,0x88,0x88,0x90,0xe0,0x00,
00777     0x00,0x00,0x00,0xf8,0x80,0x80,0xf8,0x80,0x80,0x80,0xf8,0x00,
00778     0x00,0x00,0x00,0x78,0x40,0x40,0x70,0x40,0x40,0x40,0x40,0x00,
00779     0x00,0x00,0x00,0x38,0x44,0x84,0x80,0x9c,0x84,0x44,0x38,0x00,
00780     0x00,0x00,0x00,0x88,0x88,0x88,0xf8,0x88,0x88,0x88,0x88,0x00,
00781     0x00,0x00,0x00,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x00,
00782     0x00,0x00,0x00,0x10,0x10,0x10,0x10,0x10,0x90,0x90,0x60,0x00,
00783     0x00,0x00,0x00,0x88,0x90,0xa0,0xe0,0xa0,0x90,0x90,0x88,0x00,
00784     0x00,0x00,0x00,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0xf0,0x00,
00785     0x00,0x00,0x00,0x82,0xc6,0xc6,0xaa,0xaa,0xaa,0xaa,0x92,0x00,
00786     0x00,0x00,0x00,0x84,0xc4,0xa4,0xa4,0x94,0x94,0x8c,0x84,0x00,
00787     0x00,0x00,0x00,0x30,0x48,0x84,0x84,0x84,0x84,0x48,0x30,0x00,
00788     0x00,0x00,0x00,0xf0,0x88,0x88,0x88,0xf0,0x80,0x80,0x80,0x00,
00789     0x00,0x00,0x00,0x30,0x48,0x84,0x84,0x84,0x84,0x58,0x34,0x04,
00790     0x00,0x00,0x00,0x78,0x44,0x44,0x78,0x50,0x48,0x44,0x42,0x00,
00791     0x00,0x00,0x00,0x70,0x88,0x80,0x70,0x08,0x88,0x88,0x70,0x00,
00792     0x00,0x00,0x00,0xf8,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x00,
00793     0x00,0x00,0x00,0x84,0x84,0x84,0x84,0x84,0x84,0x48,0x30,0x00,
00794     0x00,0x00,0x00,0x88,0x88,0x50,0x50,0x50,0x50,0x50,0x20,0x00,
00795     0x00,0x00,0x00,0x92,0xaa,0xaa,0xaa,0xaa,0xaa,0xaa,0x44,0x00,
00796     0x00,0x00,0x00,0x84,0x48,0x48,0x30,0x30,0x48,0x48,0x84,0x00,
00797     0x00,0x00,0x00,0x88,0x50,0x50,0x20,0x20,0x20,0x20,0x20,0x00,
00798     0x00,0x00,0x00,0xf8,0x08,0x10,0x20,0x20,0x40,0x80,0xf8,0x00,
00799     0x00,0x00,0x00,0xc0,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,
00800     0x00,0x00,0x00,0x80,0x80,0x40,0x40,0x40,0x40,0x20,0x20,0x00,
00801     0x00,0x00,0x00,0xc0,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,
00802     0x00,0x00,0x00,0x40,0xa0,0xa0,0xa0,0x00,0x00,0x00,0x00,0x00,
00803     0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xf8,
00804     0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
00805     0x00,0x00,0x00,0x00,0x00,0xe0,0x10,0x70,0x90,0x90,0x70,0x00,
00806     0x00,0x00,0x00,0x80,0x80,0xa0,0xd0,0x90,0x90,0xd0,0xa0,0x00,
00807     0x00,0x00,0x00,0x00,0x00,0x60,0x90,0x80,0x80,0x90,0x60,0x00,
00808     0x00,0x00,0x00,0x10,0x10,0x50,0xb0,0x90,0x90,0xb0,0x50,0x00,
00809     0x00,0x00,0x00,0x00,0x00,0x60,0x90,0xf0,0x80,0x90,0x60,0x00,
00810     0x00,0x00,0x00,0xc0,0x80,0xc0,0x80,0x80,0x80,0x80,0x80,0x00,
00811     0x00,0x00,0x00,0x00,0x00,0x50,0xb0,0x90,0x90,0xb0,0x50,0x10,
00812     0x00,0x00,0x00,0x80,0x80,0xa0,0xd0,0x90,0x90,0x90,0x90,0x00,
00813     0x00,0x00,0x00,0x80,0x00,0x80,0x80,0x80,0x80,0x80,0x80,0x00,
00814     0x00,0x00,0x00,0x80,0x00,0x80,0x80,0x80,0x80,0x80,0x80,0x80,
00815     0x00,0x00,0x00,0x80,0x80,0x90,0xa0,0xc0,0xa0,0x90,0x90,0x00,
00816     0x00,0x00,0x00,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x00,
00817     0x00,0x00,0x00,0x00,0x00,0xa6,0xda,0x92,0x92,0x92,0x92,0x00,
00818     0x00,0x00,0x00,0x00,0x00,0xa0,0xd0,0x90,0x90,0x90,0x90,0x00,
00819     0x00,0x00,0x00,0x00,0x00,0x60,0x90,0x90,0x90,0x90,0x60,0x00,
00820     0x00,0x00,0x00,0x00,0x00,0xa0,0xd0,0x90,0x90,0xd0,0xa0,0x80,
00821     0x00,0x00,0x00,0x00,0x00,0x50,0xb0,0x90,0x90,0xb0,0x50,0x10,
00822     0x00,0x00,0x00,0x00,0x00,0xa0,0xc0,0x80,0x80,0x80,0x80,0x00,
00823     0x00,0x00,0x00,0x00,0x00,0xe0,0x90,0x40,0x20,0x90,0x60,0x00,
00824     0x00,0x00,0x00,0x80,0x80,0xc0,0x80,0x80,0x80,0x80,0xc0,0x00,
00825     0x00,0x00,0x00,0x00,0x00,0x90,0x90,0x90,0x90,0xb0,0x50,0x00,
00826     0x00,0x00,0x00,0x00,0x00,0x88,0x88,0x50,0x50,0x50,0x20,0x00,
00827     0x00,0x00,0x00,0x00,0x00,0x92,0xaa,0xaa,0xaa,0xaa,0x44,0x00,
00828     0x00,0x00,0x00,0x00,0x00,0x88,0x50,0x20,0x20,0x50,0x88,0x00,
00829     0x00,0x00,0x00,0x00,0x00,0x88,0x50,0x50,0x50,0x20,0x20,0x20,
00830     0x00,0x00,0x00,0x00,0x00,0xf0,0x10,0x20,0x40,0x80,0xf0,0x00,
00831     0x00,0x00,0x00,0xc0,0x80,0x80,0x80,0x00,0x80,0x80,0x80,0x80,
00832     0x00,0x00,0x00,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,
00833     0x00,0x00,0x00,0xc0,0x40,0x40,0x40,0x20,0x40,0x40,0x40,0x40,
00834     0x00,0x00,0x00,0x00,0x00,0x00,0xe8,0xb0,0x00,0x00,0x00,0x00,
00835     0x00,0x00,0x00,0x00,0xe0,0xa0,0xa0,0xa0,0xa0,0xa0,0xe0,0x00};
00836
00837 const uint16_t ASCII8x8_Table [] = {
00838     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
00839     0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x40,
00840     0xa0, 0xa0, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00,
00841     0x00, 0x24, 0x24, 0xfe, 0x48, 0xfc, 0x48, 0x48,
00842     0x38, 0x54, 0x50, 0x38, 0x14, 0x14, 0x54, 0x38,
00843     0x44, 0xa8, 0xa8, 0x50, 0x14, 0x1a, 0x2a, 0x24,
00844     0x10, 0x28, 0x28, 0x10, 0x74, 0x4c, 0x4c, 0x30,
00845     0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00,
00846     0x08, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x08,
00847     0x10, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x10,
00848     0x00, 0x00, 0x24, 0x18, 0x3c, 0x18, 0x24, 0x00,
00849     0x00, 0x00, 0x10, 0x10, 0x7c, 0x10, 0x10, 0x00,
00850     0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x08, 0x10,
00851     0x00, 0x00, 0x00, 0x00, 0x3c, 0x00, 0x00, 0x00,
00852     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x18,
00853     0x08, 0x08, 0x08, 0x10, 0x10, 0x20, 0x20, 0x20,
00854     0x18, 0x24, 0x24, 0x24, 0x24, 0x24, 0x24, 0x18,
00855     0x08, 0x18, 0x28, 0x08, 0x08, 0x08, 0x08, 0x08,
00856     0x38, 0x44, 0x00, 0x04, 0x08, 0x10, 0x20, 0x7c,
00857     0x18, 0x24, 0x04, 0x18, 0x04, 0x04, 0x24, 0x18,
00858     0x04, 0x0c, 0x14, 0x24, 0x44, 0x7e, 0x04, 0x04,
00859     0x3c, 0x20, 0x20, 0x38, 0x04, 0x04, 0x24, 0x18,
00860     0x18, 0x24, 0x20, 0x38, 0x24, 0x24, 0x24, 0x18,
00861     0x3c, 0x04, 0x08, 0x08, 0x08, 0x10, 0x10, 0x10,
00862     0x18, 0x24, 0x24, 0x18, 0x24, 0x24, 0x24, 0x18,
00863     0x18, 0x24, 0x24, 0x24, 0x1c, 0x04, 0x24, 0x18,
00864     0x00, 0x00, 0x10, 0x00, 0x00, 0x10, 0x00, 0x00,
00865     0x00, 0x00, 0x08, 0x00, 0x00, 0x08, 0x10, 0x00,
00866     0x00, 0x00, 0x04, 0x18, 0x20, 0x18, 0x04, 0x00,
00867     0x00, 0x00, 0x00, 0x3c, 0x00, 0x3c, 0x00, 0x00,
00868     0x00, 0x00, 0x20, 0x18, 0x04, 0x18, 0x20, 0x00,
00869     0x18, 0x24, 0x04, 0x08, 0x10, 0x10, 0x00, 0x10,
00870     0x3c, 0x42, 0x99, 0xa5, 0xa5, 0x9d, 0x42, 0x38,
00871     0x38, 0x44, 0x44, 0x44, 0x7c, 0x44, 0x44, 0x44,
00872     0x78, 0x44, 0x44, 0x78, 0x44, 0x44, 0x44, 0x78,
00873     0x1c, 0x22, 0x42, 0x40, 0x40, 0x42, 0x22, 0x1c,
00874     0x70, 0x48, 0x44, 0x44, 0x44, 0x44, 0x48, 0x70,
00875     0x7c, 0x40, 0x40, 0x7c, 0x40, 0x40, 0x40, 0x7c,
00876     0x3c, 0x20, 0x20, 0x38, 0x20, 0x20, 0x20, 0x20,
00877     0x1c, 0x22, 0x42, 0x40, 0x4e, 0x42, 0x22, 0x1c,
00878     0x44, 0x44, 0x44, 0x7c, 0x44, 0x44, 0x44, 0x44,
00879     0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
00880     0x04, 0x04, 0x04, 0x04, 0x04, 0x24, 0x24, 0x18,
00881     0x44, 0x48, 0x50, 0x70, 0x50, 0x48, 0x48, 0x44,
00882     0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x3c,
00883     0x82, 0xc6, 0xc6, 0xaa, 0xaa, 0xaa, 0xaa, 0x92,
00884     0x42, 0x62, 0x52, 0x52, 0x4a, 0x4a, 0x46, 0x42,
00885     0x18, 0x24, 0x42, 0x42, 0x42, 0x42, 0x24, 0x18,
00886     0x78, 0x44, 0x44, 0x44, 0x78, 0x40, 0x40, 0x40,
00887     0x18, 0x24, 0x42, 0x42, 0x42, 0x42, 0x2c, 0x1a,
00888     0x78, 0x44, 0x44, 0x78, 0x50, 0x48, 0x44, 0x42,
00889     0x38, 0x44, 0x40, 0x38, 0x04, 0x44, 0x44, 0x38,
00890     0x7c, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
00891     0x42, 0x42, 0x42, 0x42, 0x42, 0x42, 0x24, 0x18,
00892     0x44, 0x44, 0x28, 0x28, 0x28, 0x28, 0x28, 0x10,
00893     0x92, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x44,
00894     0x42, 0x24, 0x24, 0x18, 0x18, 0x24, 0x24, 0x42,
00895     0x44, 0x28, 0x28, 0x10, 0x10, 0x10, 0x10, 0x10,
00896     0x7c, 0x04, 0x08, 0x10, 0x10, 0x20, 0x40, 0x7c,
00897     0x1c, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x1c,
00898     0x10, 0x10, 0x08, 0x08, 0x08, 0x08, 0x04, 0x04,
00899     0x1c, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x1c,
00900     0x10, 0x28, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00,
00901     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
00902     0x20, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00,
00903     0x00, 0x00, 0x18, 0x04, 0x1c, 0x24, 0x24, 0x1c,
00904     0x20, 0x20, 0x28, 0x34, 0x24, 0x24, 0x34, 0x28,
00905     0x00, 0x00, 0x18, 0x24, 0x20, 0x20, 0x24, 0x18,
00906     0x04, 0x04, 0x14, 0x2c, 0x24, 0x24, 0x2c, 0x14,
00907     0x00, 0x00, 0x18, 0x24, 0x3c, 0x20, 0x24, 0x18,
00908     0x00, 0x18, 0x10, 0x10, 0x18, 0x10, 0x10, 0x10,
00909     0x00, 0x18, 0x24, 0x24, 0x18, 0x04, 0x24, 0x18,
00910     0x20, 0x20, 0x28, 0x34, 0x24, 0x24, 0x24, 0x24,
00911     0x10, 0x00, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
00912     0x08, 0x00, 0x08, 0x08, 0x08, 0x08, 0x28, 0x10,
00913     0x20, 0x20, 0x24, 0x28, 0x30, 0x28, 0x24, 0x24,
00914     0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
00915     0x00, 0x00, 0xa6, 0xda, 0x92, 0x92, 0x92, 0x92,
00916     0x00, 0x00, 0x28, 0x34, 0x24, 0x24, 0x24, 0x24,
00917     0x00, 0x00, 0x18, 0x24, 0x24, 0x24, 0x24, 0x18,
00918     0x00, 0x28, 0x34, 0x24, 0x38, 0x20, 0x20, 0x20,
00919     0x00, 0x14, 0x2c, 0x24, 0x1c, 0x04, 0x04, 0x04,
00920     0x00, 0x00, 0x2c, 0x30, 0x20, 0x20, 0x20, 0x20,
00921     0x00, 0x00, 0x18, 0x24, 0x10, 0x08, 0x24, 0x18,
00922     0x00, 0x10, 0x38, 0x10, 0x10, 0x10, 0x10, 0x18,
00923     0x00, 0x00, 0x24, 0x24, 0x24, 0x24, 0x2c, 0x14,
00924     0x00, 0x00, 0x44, 0x44, 0x28, 0x28, 0x28, 0x10,
00925     0x00, 0x00, 0x92, 0xaa, 0xaa, 0xaa, 0xaa, 0x44,
00926     0x00, 0x00, 0x44, 0x28, 0x10, 0x10, 0x28, 0x44,
00927     0x00, 0x28, 0x28, 0x28, 0x10, 0x10, 0x10, 0x10,
00928     0x00, 0x00, 0x3c, 0x04, 0x08, 0x10, 0x20, 0x3c,
00929     0x00, 0x08, 0x10, 0x10, 0x20, 0x10, 0x10, 0x08,
00930     0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
00931     0x00, 0x10, 0x08, 0x08, 0x04, 0x08, 0x08, 0x10,
00932     0x00, 0x00, 0x00, 0x60, 0x92, 0x0c, 0x00, 0x00,
00933     0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
00934
00935
00936 sFONT Font16x24 = {
00937   ASCII16x24_Table,
00938   16, /* Width */
00939   24, /* Height */
00940 };
00941
00942 sFONT Font12x12 = {
00943   ASCII12x12_Table,
00944   12, /* Width */
00945   12, /* Height */
00946 };
00947
00948 sFONT Font8x12 = {
00949   ASCII8x12_Table,
00950   8, /* Width */
00951   12, /* Height */
00952 };
00953
00954
00955 sFONT Font8x8 = {
00956   ASCII8x8_Table,
00957   8, /* Width */
00958   8, /* Height */
00959 };
00960
00961 /**
00962   * @}
00963   */
00964
00965
00966 /** @defgroup FONTS_Private_Function_Prototypes
00967   * @{
00968   */
00969 /**
00970   * @}
00971   */
00972
00973
00974 /** @defgroup FONTS_Private_Functions
00975   * @{
00976   */
00977
00978 /**
00979   * @}
00980   */
00981
00982 /**
00983   * @}
00984   */
00985
00986 /**
00987   * @}
00988   */
00989
00990 /**
00991   * @}
00992   */
00993
00994 /**
00995   * @}
00996   */
00997 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: fonts.h Source File

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fonts.h

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00001 /**
00002   ******************************************************************************
00003   * @file    fonts.h
00004   * @author  MCD Application Team
00005   * @version V4.5.0
00006   * @date    07-March-2011
00007   * @brief   Header for fonts.c
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __FONTS_H
00024 #define __FONTS_H
00025
00026 #ifdef __cplusplus
00027  extern "C" {
00028 #endif
00029
00030 /* Includes ------------------------------------------------------------------*/
00031 #include <stdint.h>
00032
00033 /** @addtogroup Utilities
00034   * @{
00035   */
00036
00037 /** @addtogroup STM32_EVAL
00038   * @{
00039   */
00040
00041 /** @addtogroup Common
00042   * @{
00043   */
00044
00045 /** @addtogroup FONTS
00046   * @{
00047   */
00048
00049 /** @defgroup FONTS_Exported_Types
00050   * @{
00051   */
00052 typedef struct _tFont
00053 {
00054   const uint16_t *table;
00055   uint16_t Width;
00056   uint16_t Height;
00057
00058 } sFONT;
00059
00060 extern sFONT Font16x24;
00061 extern sFONT Font12x12;
00062 extern sFONT Font8x12;
00063 extern sFONT Font8x8;
00064
00065 /**
00066   * @}
00067   */
00068
00069 /** @defgroup FONTS_Exported_Constants
00070   * @{
00071   */
00072 #define LINE(x) ((x) * (((sFONT *)LCD_GetFont())->Height))
00073
00074 /**
00075   * @}
00076   */
00077
00078 /** @defgroup FONTS_Exported_Macros
00079   * @{
00080   */
00081 /**
00082   * @}
00083   */
00084
00085 /** @defgroup FONTS_Exported_Functions
00086   * @{
00087   */
00088 /**
00089   * @}
00090   */
00091
00092 #ifdef __cplusplus
00093 }
00094 #endif
00095
00096 #endif /* __FONTS_H */
00097
00098 /**
00099   * @}
00100   */
00101
00102 /**
00103   * @}
00104   */
00105
00106 /**
00107   * @}
00108   */
00109
00110 /**
00111   * @}
00112   */
00113
00114 /**
00115   * @}
00116   */
00117
00118 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


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  • JOFR1 : ADC_TypeDef
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  • KEYR : FLASH_TypeDef
  • KR : IWDG_TypeDef


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  • LCD_RAM : LCD_TypeDef
  • LCD_REG : LCD_TypeDef
  • LCKR : GPIO_TypeDef
  • LogicalAddress : HDMI_CEC_Map
  • LTR : ADC_TypeDef


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  • MACA0HR : ETH_TypeDef
  • MACA0LR : ETH_TypeDef
  • MACA1HR : ETH_TypeDef
  • MACA1LR : ETH_TypeDef
  • MACA2HR : ETH_TypeDef
  • MACA2LR : ETH_TypeDef
  • MACA3HR : ETH_TypeDef
  • MACA3LR : ETH_TypeDef
  • MACCR : ETH_TypeDef
  • MACFCR : ETH_TypeDef
  • MACFFR : ETH_TypeDef
  • MACHTHR : ETH_TypeDef
  • MACHTLR : ETH_TypeDef
  • MACIMR : ETH_TypeDef
  • MACMIIAR : ETH_TypeDef
  • MACMIIDR : ETH_TypeDef
  • MACPMTCSR : ETH_TypeDef
  • MACRWUFFR : ETH_TypeDef
  • MACSR : ETH_TypeDef
  • MACVLANTR : ETH_TypeDef
  • Maker_ID : NAND_IDTypeDef
  • ManDeflECC : SD_CSD
  • ManufactDate : SD_CID
  • Manufacturer_Code : NOR_IDTypeDef
  • Manufacturer_ID : OneNAND_IDTypeDef
  • ManufacturerID : SD_CID
  • MAPR : AFIO_TypeDef
  • MAPR2 : AFIO_TypeDef
  • MASK : SDIO_TypeDef
  • MaxBusClkFrec : SD_CSD
  • MaxRdCurrentVDDMax : SD_CSD
  • MaxRdCurrentVDDMin : SD_CSD
  • MaxWrBlockLen : SD_CSD
  • MaxWrCurrentVDDMax : SD_CSD
  • MaxWrCurrentVDDMin : SD_CSD
  • MCR : CAN_TypeDef
  • MMCCR : ETH_TypeDef
  • MMCRFAECR : ETH_TypeDef
  • MMCRFCECR : ETH_TypeDef
  • MMCRGUFCR : ETH_TypeDef
  • MMCRIMR : ETH_TypeDef
  • MMCRIR : ETH_TypeDef
  • MMCTGFCR : ETH_TypeDef
  • MMCTGFMSCCR : ETH_TypeDef
  • MMCTGFSCCR : ETH_TypeDef
  • MMCTIMR : ETH_TypeDef
  • MMCTIR : ETH_TypeDef
  • MSR : CAN_TypeDef


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Here is a list of all struct and union fields with links to the structures/unions they belong to:

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  • NSAC : SD_CSD
  • NVIC_IRQChannel : NVIC_InitTypeDef
  • NVIC_IRQChannelCmd : NVIC_InitTypeDef
  • NVIC_IRQChannelPreemptionPriority : NVIC_InitTypeDef
  • NVIC_IRQChannelSubPriority : NVIC_InitTypeDef


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Here is a list of all struct and union fields with links to the structures/unions they belong to:

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  • OAR : CEC_TypeDef
  • OAR1 : I2C_TypeDef
  • OAR2 : I2C_TypeDef
  • OBR : FLASH_TypeDef
  • ODR : GPIO_TypeDef
  • OEM_AppliID : SD_CID
  • Opcode : HDMI_CEC_Message
  • Operande : HDMI_CEC_Message
  • OPTKEYR : FLASH_TypeDef


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  • Z : TS_STATE
  • Zone : NAND_ADDRESS


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  • BDCR : RCC_TypeDef
  • BDTR : TIM_TypeDef
  • Block : NAND_ADDRESS , OneNAND_ADDRESS
  • BRR : GPIO_TypeDef , USART_TypeDef
  • BSRR : GPIO_TypeDef
  • BTCR : FSMC_Bank1_TypeDef
  • BTR : CAN_TypeDef
  • BWTR : FSMC_Bank1E_TypeDef


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  • CAN_ABOM : CAN_InitTypeDef
  • CAN_AWUM : CAN_InitTypeDef
  • CAN_BS1 : CAN_InitTypeDef
  • CAN_BS2 : CAN_InitTypeDef
  • CAN_FilterActivation : CAN_FilterInitTypeDef
  • CAN_FilterFIFOAssignment : CAN_FilterInitTypeDef
  • CAN_FilterIdHigh : CAN_FilterInitTypeDef
  • CAN_FilterIdLow : CAN_FilterInitTypeDef
  • CAN_FilterMaskIdHigh : CAN_FilterInitTypeDef
  • CAN_FilterMaskIdLow : CAN_FilterInitTypeDef
  • CAN_FilterMode : CAN_FilterInitTypeDef
  • CAN_FilterNumber : CAN_FilterInitTypeDef
  • CAN_FilterScale : CAN_FilterInitTypeDef
  • CAN_Mode : CAN_InitTypeDef
  • CAN_NART : CAN_InitTypeDef
  • CAN_Prescaler : CAN_InitTypeDef
  • CAN_RFLM : CAN_InitTypeDef
  • CAN_SJW : CAN_InitTypeDef
  • CAN_TTCM : CAN_InitTypeDef
  • CAN_TXFP : CAN_InitTypeDef
  • CardBlockSize : SD_CardInfo
  • CardCapacity : SD_CardInfo
  • CardComdClasses : SD_CSD
  • CardType : SD_CardInfo
  • CCER : TIM_TypeDef
  • CCMR1 : TIM_TypeDef
  • CCMR2 : TIM_TypeDef
  • CCR : DMA_Channel_TypeDef , I2C_TypeDef
  • CCR1 : TIM_TypeDef
  • CCR2 : TIM_TypeDef
  • CCR3 : TIM_TypeDef
  • CCR4 : TIM_TypeDef
  • CEC_BitPeriodMode : CEC_InitTypeDef
  • CEC_BitTimingMode : CEC_InitTypeDef
  • CFGR : CEC_TypeDef , RCC_TypeDef
  • CFR : WWDG_TypeDef
  • CID_CRC : SD_CID
  • CIR : RCC_TypeDef
  • CLKCR : SDIO_TypeDef
  • CMAR : DMA_Channel_TypeDef
  • CMD : SDIO_TypeDef
  • CNDTR : DMA_Channel_TypeDef
  • CNT : TIM_TypeDef
  • CNTH : RTC_TypeDef
  • CNTL : RTC_TypeDef
  • ContentProtectAppli : SD_CSD
  • CopyFlag : SD_CSD
  • CPAR : DMA_Channel_TypeDef
  • CR : BKP_TypeDef , RCC_TypeDef , WWDG_TypeDef , CRC_TypeDef , DBGMCU_TypeDef , FLASH_TypeDef , PWR_TypeDef , DAC_TypeDef
  • CR1 : ADC_TypeDef , SPI_TypeDef , TIM_TypeDef , USART_TypeDef , I2C_TypeDef
  • CR2 : ADC_TypeDef , SPI_TypeDef , USART_TypeDef , I2C_TypeDef , TIM_TypeDef
  • CR3 : USART_TypeDef
  • CRCPR : SPI_TypeDef
  • CRH : GPIO_TypeDef , RTC_TypeDef
  • CRL : GPIO_TypeDef , RTC_TypeDef
  • CSD_CRC : SD_CSD
  • CSDStruct : SD_CSD
  • CSR : PWR_TypeDef , RCC_TypeDef , BKP_TypeDef , CEC_TypeDef


STM32F10x Standard Peripherals Firmware Library: Data Fields

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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- d -

  • DAC_LFSRUnmask_TriangleAmplitude : DAC_InitTypeDef
  • DAC_OutputBuffer : DAC_InitTypeDef
  • DAC_Trigger : DAC_InitTypeDef
  • DAC_WaveGeneration : DAC_InitTypeDef
  • DAT_BUS_WIDTH : SD_CardStatus
  • Data : CanTxMsg , CanRxMsg
  • Data0 : OB_TypeDef
  • Data1 : OB_TypeDef
  • DCOUNT : SDIO_TypeDef
  • DCR : TIM_TypeDef
  • DCTRL : SDIO_TypeDef
  • Device_Code1 : NOR_IDTypeDef
  • Device_Code2 : NOR_IDTypeDef
  • Device_Code3 : NOR_IDTypeDef
  • Device_ID : OneNAND_IDTypeDef , NAND_IDTypeDef
  • DeviceSize : SD_CSD
  • DeviceSizeMul : SD_CSD
  • DeviceType : HDMI_CEC_Map
  • DHR12L1 : DAC_TypeDef
  • DHR12L2 : DAC_TypeDef
  • DHR12LD : DAC_TypeDef
  • DHR12R1 : DAC_TypeDef
  • DHR12R2 : DAC_TypeDef
  • DHR12RD : DAC_TypeDef
  • DHR8R1 : DAC_TypeDef
  • DHR8R2 : DAC_TypeDef
  • DHR8RD : DAC_TypeDef
  • DIER : TIM_TypeDef
  • DIVH : RTC_TypeDef
  • DIVL : RTC_TypeDef
  • DLC : CanTxMsg , CanRxMsg
  • DLEN : SDIO_TypeDef
  • DMA_BufferSize : DMA_InitTypeDef
  • DMA_DIR : DMA_InitTypeDef
  • DMA_M2M : DMA_InitTypeDef
  • DMA_MemoryBaseAddr : DMA_InitTypeDef
  • DMA_MemoryDataSize : DMA_InitTypeDef
  • DMA_MemoryInc : DMA_InitTypeDef
  • DMA_Mode : DMA_InitTypeDef
  • DMA_PeripheralBaseAddr : DMA_InitTypeDef
  • DMA_PeripheralDataSize : DMA_InitTypeDef
  • DMA_PeripheralInc : DMA_InitTypeDef
  • DMA_Priority : DMA_InitTypeDef
  • DMABMR : ETH_TypeDef
  • DMACHRBAR : ETH_TypeDef
  • DMACHRDR : ETH_TypeDef
  • DMACHTBAR : ETH_TypeDef
  • DMACHTDR : ETH_TypeDef
  • DMAIER : ETH_TypeDef
  • DMAMFBOCR : ETH_TypeDef
  • DMAOMR : ETH_TypeDef
  • DMAR : TIM_TypeDef
  • DMARDLAR : ETH_TypeDef
  • DMARPDR : ETH_TypeDef
  • DMASR : ETH_TypeDef
  • DMATDLAR : ETH_TypeDef
  • DMATPDR : ETH_TypeDef
  • DOR1 : DAC_TypeDef
  • DOR2 : DAC_TypeDef
  • DR : CRC_TypeDef , I2C_TypeDef , SPI_TypeDef , USART_TypeDef , ADC_TypeDef
  • DR1 : BKP_TypeDef
  • DR10 : BKP_TypeDef
  • DR11 : BKP_TypeDef
  • DR12 : BKP_TypeDef
  • DR13 : BKP_TypeDef
  • DR14 : BKP_TypeDef
  • DR15 : BKP_TypeDef
  • DR16 : BKP_TypeDef
  • DR17 : BKP_TypeDef
  • DR18 : BKP_TypeDef
  • DR19 : BKP_TypeDef
  • DR2 : BKP_TypeDef
  • DR20 : BKP_TypeDef
  • DR21 : BKP_TypeDef
  • DR22 : BKP_TypeDef
  • DR23 : BKP_TypeDef
  • DR24 : BKP_TypeDef
  • DR25 : BKP_TypeDef
  • DR26 : BKP_TypeDef
  • DR27 : BKP_TypeDef
  • DR28 : BKP_TypeDef
  • DR29 : BKP_TypeDef
  • DR3 : BKP_TypeDef
  • DR30 : BKP_TypeDef
  • DR31 : BKP_TypeDef
  • DR32 : BKP_TypeDef
  • DR33 : BKP_TypeDef
  • DR34 : BKP_TypeDef
  • DR35 : BKP_TypeDef
  • DR36 : BKP_TypeDef
  • DR37 : BKP_TypeDef
  • DR38 : BKP_TypeDef
  • DR39 : BKP_TypeDef
  • DR4 : BKP_TypeDef
  • DR40 : BKP_TypeDef
  • DR41 : BKP_TypeDef
  • DR42 : BKP_TypeDef
  • DR5 : BKP_TypeDef
  • DR6 : BKP_TypeDef
  • DR7 : BKP_TypeDef
  • DR8 : BKP_TypeDef
  • DR9 : BKP_TypeDef
  • DSRImpl : SD_CSD
  • DTIMER : SDIO_TypeDef


STM32F10x Standard Peripherals Firmware Library: Data Fields

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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- e -

  • ECC : SD_CSD
  • ECCR2 : FSMC_Bank2_TypeDef
  • ECCR3 : FSMC_Bank3_TypeDef
  • EGR : TIM_TypeDef
  • EMR : EXTI_TypeDef
  • ERASE_OFFSET : SD_CardStatus
  • ERASE_SIZE : SD_CardStatus
  • ERASE_TIMEOUT : SD_CardStatus
  • EraseGrMul : SD_CSD
  • EraseGrSize : SD_CSD
  • ESR : CAN_TypeDef , CEC_TypeDef
  • EVCR : AFIO_TypeDef
  • EXTI_Line : EXTI_InitTypeDef
  • EXTI_LineCmd : EXTI_InitTypeDef
  • EXTI_Mode : EXTI_InitTypeDef
  • EXTI_Trigger : EXTI_InitTypeDef
  • EXTICR : AFIO_TypeDef
  • ExtId : CanTxMsg , CanRxMsg


STM32F10x Standard Peripherals Firmware Library: Data Fields

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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- f -

  • FA1R : CAN_TypeDef
  • FFA1R : CAN_TypeDef
  • FIFO : SDIO_TypeDef
  • FIFOCNT : SDIO_TypeDef
  • FileFormat : SD_CSD
  • FileFormatGrouop : SD_CSD
  • FM1R : CAN_TypeDef
  • FMI : CanRxMsg
  • FMR : CAN_TypeDef
  • Fourth_ID : NAND_IDTypeDef
  • FR1 : CAN_FilterRegister_TypeDef
  • FR2 : CAN_FilterRegister_TypeDef
  • FS1R : CAN_TypeDef
  • FSMC_AccessMode : FSMC_NORSRAMTimingInitTypeDef
  • FSMC_AddressHoldTime : FSMC_NORSRAMTimingInitTypeDef
  • FSMC_AddressSetupTime : FSMC_NORSRAMTimingInitTypeDef
  • FSMC_AsynchronousWait : FSMC_NORSRAMInitTypeDef
  • FSMC_AttributeSpaceTimingStruct : FSMC_NANDInitTypeDef , FSMC_PCCARDInitTypeDef
  • FSMC_Bank : FSMC_NORSRAMInitTypeDef , FSMC_NANDInitTypeDef
  • FSMC_BurstAccessMode : FSMC_NORSRAMInitTypeDef
  • FSMC_BusTurnAroundDuration : FSMC_NORSRAMTimingInitTypeDef
  • FSMC_CLKDivision : FSMC_NORSRAMTimingInitTypeDef
  • FSMC_CommonSpaceTimingStruct : FSMC_NANDInitTypeDef , FSMC_PCCARDInitTypeDef
  • FSMC_DataAddressMux : FSMC_NORSRAMInitTypeDef
  • FSMC_DataLatency : FSMC_NORSRAMTimingInitTypeDef
  • FSMC_DataSetupTime : FSMC_NORSRAMTimingInitTypeDef
  • FSMC_ECC : FSMC_NANDInitTypeDef
  • FSMC_ECCPageSize : FSMC_NANDInitTypeDef
  • FSMC_ExtendedMode : FSMC_NORSRAMInitTypeDef
  • FSMC_HiZSetupTime : FSMC_NAND_PCCARDTimingInitTypeDef
  • FSMC_HoldSetupTime : FSMC_NAND_PCCARDTimingInitTypeDef
  • FSMC_IOSpaceTimingStruct : FSMC_PCCARDInitTypeDef
  • FSMC_MemoryDataWidth : FSMC_NORSRAMInitTypeDef , FSMC_NANDInitTypeDef
  • FSMC_MemoryType : FSMC_NORSRAMInitTypeDef
  • FSMC_ReadWriteTimingStruct : FSMC_NORSRAMInitTypeDef
  • FSMC_SetupTime : FSMC_NAND_PCCARDTimingInitTypeDef
  • FSMC_TARSetupTime : FSMC_PCCARDInitTypeDef , FSMC_NANDInitTypeDef
  • FSMC_TCLRSetupTime : FSMC_PCCARDInitTypeDef , FSMC_NANDInitTypeDef
  • FSMC_Waitfeature : FSMC_PCCARDInitTypeDef , FSMC_NANDInitTypeDef
  • FSMC_WaitSetupTime : FSMC_NAND_PCCARDTimingInitTypeDef
  • FSMC_WaitSignal : FSMC_NORSRAMInitTypeDef
  • FSMC_WaitSignalActive : FSMC_NORSRAMInitTypeDef
  • FSMC_WaitSignalPolarity : FSMC_NORSRAMInitTypeDef
  • FSMC_WrapMode : FSMC_NORSRAMInitTypeDef
  • FSMC_WriteBurst : FSMC_NORSRAMInitTypeDef
  • FSMC_WriteOperation : FSMC_NORSRAMInitTypeDef
  • FSMC_WriteTimingStruct : FSMC_NORSRAMInitTypeDef
  • FTSR : EXTI_TypeDef


STM32F10x Standard Peripherals Firmware Library: Data Fields

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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- g -

  • GPIO_Mode : GPIO_InitTypeDef
  • GPIO_Pin : GPIO_InitTypeDef
  • GPIO_Speed : GPIO_InitTypeDef
  • GTPR : USART_TypeDef


STM32F10x Standard Peripherals Firmware Library: Data Fields

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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- h -

  • H : SC_ATR
  • HCLK_Frequency : RCC_ClocksTypeDef
  • Header : HDMI_CEC_Message
  • Height : _tFont
  • Hlenght : SC_ATR
  • HTR : ADC_TypeDef


STM32F10x Standard Peripherals Firmware Library: Data Fields

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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- i -

  • I2C_Ack : I2C_InitTypeDef
  • I2C_AcknowledgedAddress : I2C_InitTypeDef
  • I2C_ClockSpeed : I2C_InitTypeDef
  • I2C_DutyCycle : I2C_InitTypeDef
  • I2C_Mode : I2C_InitTypeDef
  • I2C_OwnAddress1 : I2C_InitTypeDef
  • I2S_AudioFreq : I2S_InitTypeDef
  • I2S_CPOL : I2S_InitTypeDef
  • I2S_DataFormat : I2S_InitTypeDef
  • I2S_MCLKOutput : I2S_InitTypeDef
  • I2S_Mode : I2S_InitTypeDef
  • I2S_Standard : I2S_InitTypeDef
  • I2SCFGR : SPI_TypeDef
  • I2SPR : SPI_TypeDef
  • ICR : SDIO_TypeDef
  • IDCODE : DBGMCU_TypeDef
  • IDE : CanTxMsg , CanRxMsg
  • IDR : GPIO_TypeDef , CRC_TypeDef
  • IER : CAN_TypeDef
  • IFCR : DMA_TypeDef
  • IMR : EXTI_TypeDef
  • ISR : DMA_TypeDef


STM32F10x Standard Peripherals Firmware Library: Data Fields

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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- p -

  • Page : OneNAND_ADDRESS , NAND_ADDRESS
  • PartBlockRead : SD_CSD
  • PATT2 : FSMC_Bank2_TypeDef
  • PATT3 : FSMC_Bank3_TypeDef
  • PATT4 : FSMC_Bank4_TypeDef
  • PCLK1_Frequency : RCC_ClocksTypeDef
  • PCLK2_Frequency : RCC_ClocksTypeDef
  • PCR2 : FSMC_Bank2_TypeDef
  • PCR3 : FSMC_Bank3_TypeDef
  • PCR4 : FSMC_Bank4_TypeDef
  • PERFORMANCE_MOVE : SD_CardStatus
  • PermWrProtect : SD_CSD
  • PhysicalAddress_A : HDMI_CEC_Map
  • PhysicalAddress_B : HDMI_CEC_Map
  • PhysicalAddress_C : HDMI_CEC_Map
  • PhysicalAddress_D : HDMI_CEC_Map
  • PIO4 : FSMC_Bank4_TypeDef
  • PMEM2 : FSMC_Bank2_TypeDef
  • PMEM3 : FSMC_Bank3_TypeDef
  • PMEM4 : FSMC_Bank4_TypeDef
  • POWER : SDIO_TypeDef
  • PR : EXTI_TypeDef , IWDG_TypeDef
  • PRES : CEC_TypeDef
  • PRLH : RTC_TypeDef
  • PRLL : RTC_TypeDef
  • ProdName1 : SD_CID
  • ProdName2 : SD_CID
  • ProdRev : SD_CID
  • ProdSN : SD_CID
  • PSC : TIM_TypeDef
  • PTPSSIR : ETH_TypeDef
  • PTPTSAR : ETH_TypeDef
  • PTPTSCR : ETH_TypeDef
  • PTPTSHR : ETH_TypeDef
  • PTPTSHUR : ETH_TypeDef
  • PTPTSLR : ETH_TypeDef
  • PTPTSLUR : ETH_TypeDef
  • PTPTTHR : ETH_TypeDef
  • PTPTTLR : ETH_TypeDef


STM32F10x Standard Peripherals Firmware Library: Data Fields

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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- r -

  • RCA : SD_CardInfo
  • RCR : TIM_TypeDef
  • RdBlockLen : SD_CSD
  • RdBlockMisalign : SD_CSD
  • RDHR : CAN_FIFOMailBox_TypeDef
  • RDLR : CAN_FIFOMailBox_TypeDef
  • RDP : OB_TypeDef
  • RDTR : CAN_FIFOMailBox_TypeDef
  • RESERVED : FLASH_TypeDef
  • RESERVED0 : AFIO_TypeDef , I2C_TypeDef , RTC_TypeDef , SDIO_TypeDef , BKP_TypeDef , SPI_TypeDef , TIM_TypeDef , CAN_TypeDef , USART_TypeDef , CRC_TypeDef , ETH_TypeDef , FSMC_Bank2_TypeDef , FSMC_Bank3_TypeDef
  • RESERVED1 : SPI_TypeDef , TIM_TypeDef , USART_TypeDef
  • Reserved1 : SD_CSD , SD_CID
  • RESERVED1 : BKP_TypeDef , CAN_TypeDef , CRC_TypeDef , ETH_TypeDef , I2C_TypeDef , RTC_TypeDef , SDIO_TypeDef
  • RESERVED10 : BKP_TypeDef , TIM_TypeDef
  • RESERVED11 : BKP_TypeDef , TIM_TypeDef
  • RESERVED12 : BKP_TypeDef , TIM_TypeDef
  • RESERVED13 : BKP_TypeDef , TIM_TypeDef
  • RESERVED14 : BKP_TypeDef , TIM_TypeDef
  • RESERVED15 : BKP_TypeDef , TIM_TypeDef
  • RESERVED16 : BKP_TypeDef , TIM_TypeDef
  • RESERVED17 : BKP_TypeDef , TIM_TypeDef
  • RESERVED18 : BKP_TypeDef , TIM_TypeDef
  • RESERVED19 : BKP_TypeDef , TIM_TypeDef
  • RESERVED2 : USART_TypeDef
  • Reserved2 : SD_CSD , SD_CID
  • RESERVED2 : BKP_TypeDef , CAN_TypeDef , ETH_TypeDef , I2C_TypeDef , RTC_TypeDef , SPI_TypeDef , TIM_TypeDef
  • RESERVED20 : BKP_TypeDef
  • RESERVED21 : BKP_TypeDef
  • RESERVED22 : BKP_TypeDef
  • RESERVED23 : BKP_TypeDef
  • RESERVED24 : BKP_TypeDef
  • RESERVED25 : BKP_TypeDef
  • RESERVED26 : BKP_TypeDef
  • RESERVED27 : BKP_TypeDef
  • RESERVED28 : BKP_TypeDef
  • RESERVED29 : BKP_TypeDef
  • Reserved3 : SD_CSD
  • RESERVED3 : BKP_TypeDef , CAN_TypeDef , ETH_TypeDef , I2C_TypeDef , RTC_TypeDef , SPI_TypeDef , TIM_TypeDef , USART_TypeDef
  • RESERVED30 : BKP_TypeDef
  • RESERVED31 : BKP_TypeDef
  • RESERVED32 : BKP_TypeDef
  • RESERVED33 : BKP_TypeDef
  • RESERVED34 : BKP_TypeDef
  • RESERVED35 : BKP_TypeDef
  • RESERVED36 : BKP_TypeDef
  • RESERVED37 : BKP_TypeDef
  • RESERVED38 : BKP_TypeDef
  • RESERVED39 : BKP_TypeDef
  • Reserved4 : SD_CSD
  • RESERVED4 : CAN_TypeDef , ETH_TypeDef , I2C_TypeDef , RTC_TypeDef , SPI_TypeDef , TIM_TypeDef , USART_TypeDef , BKP_TypeDef
  • RESERVED40 : BKP_TypeDef
  • RESERVED41 : BKP_TypeDef
  • RESERVED42 : BKP_TypeDef
  • RESERVED43 : BKP_TypeDef
  • RESERVED44 : BKP_TypeDef
  • RESERVED45 : BKP_TypeDef
  • RESERVED5 : CAN_TypeDef , ETH_TypeDef , TIM_TypeDef , BKP_TypeDef , SPI_TypeDef , RTC_TypeDef , I2C_TypeDef , USART_TypeDef
  • RESERVED6 : USART_TypeDef , I2C_TypeDef , BKP_TypeDef , ETH_TypeDef , SPI_TypeDef , RTC_TypeDef , TIM_TypeDef
  • RESERVED7 : SPI_TypeDef , ETH_TypeDef , TIM_TypeDef , BKP_TypeDef , RTC_TypeDef , I2C_TypeDef
  • RESERVED8 : I2C_TypeDef , SPI_TypeDef , ETH_TypeDef , BKP_TypeDef , TIM_TypeDef , RTC_TypeDef
  • RESERVED9 : ETH_TypeDef , BKP_TypeDef , RTC_TypeDef , TIM_TypeDef
  • RESP1 : SDIO_TypeDef
  • RESP2 : SDIO_TypeDef
  • RESP3 : SDIO_TypeDef
  • RESP4 : SDIO_TypeDef
  • RESPCMD : SDIO_TypeDef
  • RF0R : CAN_TypeDef
  • RF1R : CAN_TypeDef
  • RIR : CAN_FIFOMailBox_TypeDef
  • RLR : IWDG_TypeDef
  • RTCCR : BKP_TypeDef
  • RTR : CanTxMsg , CanRxMsg
  • RTSR : EXTI_TypeDef
  • RXCRCR : SPI_TypeDef
  • RXD : CEC_TypeDef
  • RxMessageLength : HDMI_CEC_Message


STM32F10x Standard Peripherals Firmware Library: Data Fields

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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- s -

  • SD_CARD_TYPE : SD_CardStatus
  • SD_cid : SD_CardInfo
  • SD_csd : SD_CardInfo
  • SDIO_Argument : SDIO_CmdInitTypeDef
  • SDIO_BusWide : SDIO_InitTypeDef
  • SDIO_ClockBypass : SDIO_InitTypeDef
  • SDIO_ClockDiv : SDIO_InitTypeDef
  • SDIO_ClockEdge : SDIO_InitTypeDef
  • SDIO_ClockPowerSave : SDIO_InitTypeDef
  • SDIO_CmdIndex : SDIO_CmdInitTypeDef
  • SDIO_CPSM : SDIO_CmdInitTypeDef
  • SDIO_DataBlockSize : SDIO_DataInitTypeDef
  • SDIO_DataLength : SDIO_DataInitTypeDef
  • SDIO_DataTimeOut : SDIO_DataInitTypeDef
  • SDIO_DPSM : SDIO_DataInitTypeDef
  • SDIO_HardwareFlowControl : SDIO_InitTypeDef
  • SDIO_Response : SDIO_CmdInitTypeDef
  • SDIO_TransferDir : SDIO_DataInitTypeDef
  • SDIO_TransferMode : SDIO_DataInitTypeDef
  • SDIO_Wait : SDIO_CmdInitTypeDef
  • SECURED_MODE : SD_CardStatus
  • sFIFOMailBox : CAN_TypeDef
  • sFilterRegister : CAN_TypeDef
  • SIZE_OF_PROTECTED_AREA : SD_CardStatus
  • SMCR : TIM_TypeDef
  • SMPR1 : ADC_TypeDef
  • SMPR2 : ADC_TypeDef
  • SPEED_CLASS : SD_CardStatus
  • SPI_BaudRatePrescaler : SPI_InitTypeDef
  • SPI_CPHA : SPI_InitTypeDef
  • SPI_CPOL : SPI_InitTypeDef
  • SPI_CRCPolynomial : SPI_InitTypeDef
  • SPI_DataSize : SPI_InitTypeDef
  • SPI_Direction : SPI_InitTypeDef
  • SPI_FirstBit : SPI_InitTypeDef
  • SPI_Mode : SPI_InitTypeDef
  • SPI_NSS : SPI_InitTypeDef
  • SQR1 : ADC_TypeDef
  • SQR2 : ADC_TypeDef
  • SQR3 : ADC_TypeDef
  • SR : SPI_TypeDef , USART_TypeDef , IWDG_TypeDef , FLASH_TypeDef , ADC_TypeDef , WWDG_TypeDef , TIM_TypeDef
  • SR1 : I2C_TypeDef
  • SR2 : I2C_TypeDef , FSMC_Bank2_TypeDef
  • SR3 : FSMC_Bank3_TypeDef
  • SR4 : FSMC_Bank4_TypeDef
  • STA : SDIO_TypeDef
  • StdId : CanTxMsg , CanRxMsg
  • sTxMailBox : CAN_TypeDef
  • SWIER : EXTI_TypeDef
  • SWTRIGR : DAC_TypeDef
  • SYSCLK_Frequency : RCC_ClocksTypeDef
  • SysSpecVersion : SD_CSD


STM32F10x Standard Peripherals Firmware Library: Data Fields

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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- t -

  • T : SC_ATR
  • T0 : SC_ATR
  • TAAC : SD_CSD
  • table : _tFont
  • TDHR : CAN_TxMailBox_TypeDef
  • TDLR : CAN_TxMailBox_TypeDef
  • TDTR : CAN_TxMailBox_TypeDef
  • TempWrProtect : SD_CSD
  • Third_ID : NAND_IDTypeDef
  • TIM_AutomaticOutput : TIM_BDTRInitTypeDef
  • TIM_Break : TIM_BDTRInitTypeDef
  • TIM_BreakPolarity : TIM_BDTRInitTypeDef
  • TIM_Channel : TIM_ICInitTypeDef
  • TIM_ClockDivision : TIM_TimeBaseInitTypeDef
  • TIM_CounterMode : TIM_TimeBaseInitTypeDef
  • TIM_DeadTime : TIM_BDTRInitTypeDef
  • TIM_ICFilter : TIM_ICInitTypeDef
  • TIM_ICPolarity : TIM_ICInitTypeDef
  • TIM_ICPrescaler : TIM_ICInitTypeDef
  • TIM_ICSelection : TIM_ICInitTypeDef
  • TIM_LOCKLevel : TIM_BDTRInitTypeDef
  • TIM_OCIdleState : TIM_OCInitTypeDef
  • TIM_OCMode : TIM_OCInitTypeDef
  • TIM_OCNIdleState : TIM_OCInitTypeDef
  • TIM_OCNPolarity : TIM_OCInitTypeDef
  • TIM_OCPolarity : TIM_OCInitTypeDef
  • TIM_OSSIState : TIM_BDTRInitTypeDef
  • TIM_OSSRState : TIM_BDTRInitTypeDef
  • TIM_OutputNState : TIM_OCInitTypeDef
  • TIM_OutputState : TIM_OCInitTypeDef
  • TIM_Period : TIM_TimeBaseInitTypeDef
  • TIM_Prescaler : TIM_TimeBaseInitTypeDef
  • TIM_Pulse : TIM_OCInitTypeDef
  • TIM_RepetitionCounter : TIM_TimeBaseInitTypeDef
  • TIR : CAN_TxMailBox_TypeDef
  • Tlenght : SC_ATR
  • TouchDetected : TS_STATE
  • TRISE : I2C_TypeDef
  • TS : SC_ATR
  • TSR : CAN_TypeDef
  • TXCRCR : SPI_TypeDef
  • TXD : CEC_TypeDef
  • TxMessageLength : HDMI_CEC_Message


STM32F10x Standard Peripherals Firmware Library: Data Fields

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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- u -

  • USART_BaudRate : USART_InitTypeDef
  • USART_Clock : USART_ClockInitTypeDef
  • USART_CPHA : USART_ClockInitTypeDef
  • USART_CPOL : USART_ClockInitTypeDef
  • USART_HardwareFlowControl : USART_InitTypeDef
  • USART_LastBit : USART_ClockInitTypeDef
  • USART_Mode : USART_InitTypeDef
  • USART_Parity : USART_InitTypeDef
  • USART_StopBits : USART_InitTypeDef
  • USART_WordLength : USART_InitTypeDef
  • USER : OB_TypeDef


STM32F10x Standard Peripherals Firmware Library: Data Fields

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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- w -

  • Width : _tFont
  • WrBlockMisalign : SD_CSD
  • WriteBlockPaPartial : SD_CSD
  • WRP0 : OB_TypeDef
  • WRP1 : OB_TypeDef
  • WRP2 : OB_TypeDef
  • WRP3 : OB_TypeDef
  • WRPR : FLASH_TypeDef
  • WrProtectGrEnable : SD_CSD
  • WrProtectGrSize : SD_CSD
  • WrSpeedFact : SD_CSD


STM32F10x Standard Peripherals Firmware Library: Data Fields

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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- x -

  • X : Point , TS_STATE


STM32F10x Standard Peripherals Firmware Library: Data Fields

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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- y -

  • Y : Point , TS_STATE


STM32F10x Standard Peripherals Firmware Library: Data Fields - Variables

  • Data Structures
  • Data Structure Index
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- a -

  • ACR : FLASH_TypeDef
  • ADC_ContinuousConvMode : ADC_InitTypeDef
  • ADC_DataAlign : ADC_InitTypeDef
  • ADC_ExternalTrigConv : ADC_InitTypeDef
  • ADC_Mode : ADC_InitTypeDef
  • ADC_NbrOfChannel : ADC_InitTypeDef
  • ADC_ScanConvMode : ADC_InitTypeDef
  • ADCCLK_Frequency : RCC_ClocksTypeDef
  • AHBENR : RCC_TypeDef
  • ALRH : RTC_TypeDef
  • ALRL : RTC_TypeDef
  • APB1ENR : RCC_TypeDef
  • APB1RSTR : RCC_TypeDef
  • APB2ENR : RCC_TypeDef
  • APB2RSTR : RCC_TypeDef
  • AR : FLASH_TypeDef
  • ARG : SDIO_TypeDef
  • ARR : TIM_TypeDef
  • AU_SIZE : SD_CardStatus


STM32F10x Standard Peripherals Firmware Library: Data Fields - Variables

  • Data Structures
  • Data Structure Index
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- j -

  • JDR1 : ADC_TypeDef
  • JDR2 : ADC_TypeDef
  • JDR3 : ADC_TypeDef
  • JDR4 : ADC_TypeDef
  • JOFR1 : ADC_TypeDef
  • JOFR2 : ADC_TypeDef
  • JOFR3 : ADC_TypeDef
  • JOFR4 : ADC_TypeDef
  • JSQR : ADC_TypeDef


STM32F10x Standard Peripherals Firmware Library: Data Fields - Variables

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- k -

  • KEYR : FLASH_TypeDef
  • KR : IWDG_TypeDef


STM32F10x Standard Peripherals Firmware Library: Data Fields - Variables

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- l -

  • LCD_RAM : LCD_TypeDef
  • LCD_REG : LCD_TypeDef
  • LCKR : GPIO_TypeDef
  • LogicalAddress : HDMI_CEC_Map
  • LTR : ADC_TypeDef


STM32F10x Standard Peripherals Firmware Library: Data Fields - Variables

  • Data Structures
  • Data Structure Index
  • Data Fields
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  • Variables
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- m -

  • MACA0HR : ETH_TypeDef
  • MACA0LR : ETH_TypeDef
  • MACA1HR : ETH_TypeDef
  • MACA1LR : ETH_TypeDef
  • MACA2HR : ETH_TypeDef
  • MACA2LR : ETH_TypeDef
  • MACA3HR : ETH_TypeDef
  • MACA3LR : ETH_TypeDef
  • MACCR : ETH_TypeDef
  • MACFCR : ETH_TypeDef
  • MACFFR : ETH_TypeDef
  • MACHTHR : ETH_TypeDef
  • MACHTLR : ETH_TypeDef
  • MACIMR : ETH_TypeDef
  • MACMIIAR : ETH_TypeDef
  • MACMIIDR : ETH_TypeDef
  • MACPMTCSR : ETH_TypeDef
  • MACRWUFFR : ETH_TypeDef
  • MACSR : ETH_TypeDef
  • MACVLANTR : ETH_TypeDef
  • Maker_ID : NAND_IDTypeDef
  • ManDeflECC : SD_CSD
  • ManufactDate : SD_CID
  • Manufacturer_Code : NOR_IDTypeDef
  • Manufacturer_ID : OneNAND_IDTypeDef
  • ManufacturerID : SD_CID
  • MAPR : AFIO_TypeDef
  • MAPR2 : AFIO_TypeDef
  • MASK : SDIO_TypeDef
  • MaxBusClkFrec : SD_CSD
  • MaxRdCurrentVDDMax : SD_CSD
  • MaxRdCurrentVDDMin : SD_CSD
  • MaxWrBlockLen : SD_CSD
  • MaxWrCurrentVDDMax : SD_CSD
  • MaxWrCurrentVDDMin : SD_CSD
  • MCR : CAN_TypeDef
  • MMCCR : ETH_TypeDef
  • MMCRFAECR : ETH_TypeDef
  • MMCRFCECR : ETH_TypeDef
  • MMCRGUFCR : ETH_TypeDef
  • MMCRIMR : ETH_TypeDef
  • MMCRIR : ETH_TypeDef
  • MMCTGFCR : ETH_TypeDef
  • MMCTGFMSCCR : ETH_TypeDef
  • MMCTGFSCCR : ETH_TypeDef
  • MMCTIMR : ETH_TypeDef
  • MMCTIR : ETH_TypeDef
  • MSR : CAN_TypeDef


STM32F10x Standard Peripherals Firmware Library: Data Fields - Variables

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- n -

  • NSAC : SD_CSD
  • NVIC_IRQChannel : NVIC_InitTypeDef
  • NVIC_IRQChannelCmd : NVIC_InitTypeDef
  • NVIC_IRQChannelPreemptionPriority : NVIC_InitTypeDef
  • NVIC_IRQChannelSubPriority : NVIC_InitTypeDef


STM32F10x Standard Peripherals Firmware Library: Data Fields - Variables

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- o -

  • OAR : CEC_TypeDef
  • OAR1 : I2C_TypeDef
  • OAR2 : I2C_TypeDef
  • OBR : FLASH_TypeDef
  • ODR : GPIO_TypeDef
  • OEM_AppliID : SD_CID
  • Opcode : HDMI_CEC_Message
  • Operande : HDMI_CEC_Message
  • OPTKEYR : FLASH_TypeDef


STM32F10x Standard Peripherals Firmware Library: Data Fields - Variables

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- z -

  • Z : TS_STATE
  • Zone : NAND_ADDRESS


STM32F10x Standard Peripherals Firmware Library: Data Fields - Variables

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- b -

  • BDCR : RCC_TypeDef
  • BDTR : TIM_TypeDef
  • Block : NAND_ADDRESS , OneNAND_ADDRESS
  • BRR : GPIO_TypeDef , USART_TypeDef
  • BSRR : GPIO_TypeDef
  • BTCR : FSMC_Bank1_TypeDef
  • BTR : CAN_TypeDef
  • BWTR : FSMC_Bank1E_TypeDef


STM32F10x Standard Peripherals Firmware Library: Data Fields - Variables

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- c -

  • CAN_ABOM : CAN_InitTypeDef
  • CAN_AWUM : CAN_InitTypeDef
  • CAN_BS1 : CAN_InitTypeDef
  • CAN_BS2 : CAN_InitTypeDef
  • CAN_FilterActivation : CAN_FilterInitTypeDef
  • CAN_FilterFIFOAssignment : CAN_FilterInitTypeDef
  • CAN_FilterIdHigh : CAN_FilterInitTypeDef
  • CAN_FilterIdLow : CAN_FilterInitTypeDef
  • CAN_FilterMaskIdHigh : CAN_FilterInitTypeDef
  • CAN_FilterMaskIdLow : CAN_FilterInitTypeDef
  • CAN_FilterMode : CAN_FilterInitTypeDef
  • CAN_FilterNumber : CAN_FilterInitTypeDef
  • CAN_FilterScale : CAN_FilterInitTypeDef
  • CAN_Mode : CAN_InitTypeDef
  • CAN_NART : CAN_InitTypeDef
  • CAN_Prescaler : CAN_InitTypeDef
  • CAN_RFLM : CAN_InitTypeDef
  • CAN_SJW : CAN_InitTypeDef
  • CAN_TTCM : CAN_InitTypeDef
  • CAN_TXFP : CAN_InitTypeDef
  • CardBlockSize : SD_CardInfo
  • CardCapacity : SD_CardInfo
  • CardComdClasses : SD_CSD
  • CardType : SD_CardInfo
  • CCER : TIM_TypeDef
  • CCMR1 : TIM_TypeDef
  • CCMR2 : TIM_TypeDef
  • CCR : DMA_Channel_TypeDef , I2C_TypeDef
  • CCR1 : TIM_TypeDef
  • CCR2 : TIM_TypeDef
  • CCR3 : TIM_TypeDef
  • CCR4 : TIM_TypeDef
  • CEC_BitPeriodMode : CEC_InitTypeDef
  • CEC_BitTimingMode : CEC_InitTypeDef
  • CFGR : CEC_TypeDef , RCC_TypeDef
  • CFR : WWDG_TypeDef
  • CID_CRC : SD_CID
  • CIR : RCC_TypeDef
  • CLKCR : SDIO_TypeDef
  • CMAR : DMA_Channel_TypeDef
  • CMD : SDIO_TypeDef
  • CNDTR : DMA_Channel_TypeDef
  • CNT : TIM_TypeDef
  • CNTH : RTC_TypeDef
  • CNTL : RTC_TypeDef
  • ContentProtectAppli : SD_CSD
  • CopyFlag : SD_CSD
  • CPAR : DMA_Channel_TypeDef
  • CR : BKP_TypeDef , RCC_TypeDef , WWDG_TypeDef , CRC_TypeDef , DBGMCU_TypeDef , FLASH_TypeDef , PWR_TypeDef , DAC_TypeDef
  • CR1 : ADC_TypeDef , SPI_TypeDef , TIM_TypeDef , USART_TypeDef , I2C_TypeDef
  • CR2 : ADC_TypeDef , SPI_TypeDef , USART_TypeDef , I2C_TypeDef , TIM_TypeDef
  • CR3 : USART_TypeDef
  • CRCPR : SPI_TypeDef
  • CRH : GPIO_TypeDef , RTC_TypeDef
  • CRL : GPIO_TypeDef , RTC_TypeDef
  • CSD_CRC : SD_CSD
  • CSDStruct : SD_CSD
  • CSR : PWR_TypeDef , RCC_TypeDef , BKP_TypeDef , CEC_TypeDef


STM32F10x Standard Peripherals Firmware Library: Data Fields - Variables

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- d -

  • DAC_LFSRUnmask_TriangleAmplitude : DAC_InitTypeDef
  • DAC_OutputBuffer : DAC_InitTypeDef
  • DAC_Trigger : DAC_InitTypeDef
  • DAC_WaveGeneration : DAC_InitTypeDef
  • DAT_BUS_WIDTH : SD_CardStatus
  • Data : CanTxMsg , CanRxMsg
  • Data0 : OB_TypeDef
  • Data1 : OB_TypeDef
  • DCOUNT : SDIO_TypeDef
  • DCR : TIM_TypeDef
  • DCTRL : SDIO_TypeDef
  • Device_Code1 : NOR_IDTypeDef
  • Device_Code2 : NOR_IDTypeDef
  • Device_Code3 : NOR_IDTypeDef
  • Device_ID : OneNAND_IDTypeDef , NAND_IDTypeDef
  • DeviceSize : SD_CSD
  • DeviceSizeMul : SD_CSD
  • DeviceType : HDMI_CEC_Map
  • DHR12L1 : DAC_TypeDef
  • DHR12L2 : DAC_TypeDef
  • DHR12LD : DAC_TypeDef
  • DHR12R1 : DAC_TypeDef
  • DHR12R2 : DAC_TypeDef
  • DHR12RD : DAC_TypeDef
  • DHR8R1 : DAC_TypeDef
  • DHR8R2 : DAC_TypeDef
  • DHR8RD : DAC_TypeDef
  • DIER : TIM_TypeDef
  • DIVH : RTC_TypeDef
  • DIVL : RTC_TypeDef
  • DLC : CanTxMsg , CanRxMsg
  • DLEN : SDIO_TypeDef
  • DMA_BufferSize : DMA_InitTypeDef
  • DMA_DIR : DMA_InitTypeDef
  • DMA_M2M : DMA_InitTypeDef
  • DMA_MemoryBaseAddr : DMA_InitTypeDef
  • DMA_MemoryDataSize : DMA_InitTypeDef
  • DMA_MemoryInc : DMA_InitTypeDef
  • DMA_Mode : DMA_InitTypeDef
  • DMA_PeripheralBaseAddr : DMA_InitTypeDef
  • DMA_PeripheralDataSize : DMA_InitTypeDef
  • DMA_PeripheralInc : DMA_InitTypeDef
  • DMA_Priority : DMA_InitTypeDef
  • DMABMR : ETH_TypeDef
  • DMACHRBAR : ETH_TypeDef
  • DMACHRDR : ETH_TypeDef
  • DMACHTBAR : ETH_TypeDef
  • DMACHTDR : ETH_TypeDef
  • DMAIER : ETH_TypeDef
  • DMAMFBOCR : ETH_TypeDef
  • DMAOMR : ETH_TypeDef
  • DMAR : TIM_TypeDef
  • DMARDLAR : ETH_TypeDef
  • DMARPDR : ETH_TypeDef
  • DMASR : ETH_TypeDef
  • DMATDLAR : ETH_TypeDef
  • DMATPDR : ETH_TypeDef
  • DOR1 : DAC_TypeDef
  • DOR2 : DAC_TypeDef
  • DR : CRC_TypeDef , I2C_TypeDef , SPI_TypeDef , USART_TypeDef , ADC_TypeDef
  • DR1 : BKP_TypeDef
  • DR10 : BKP_TypeDef
  • DR11 : BKP_TypeDef
  • DR12 : BKP_TypeDef
  • DR13 : BKP_TypeDef
  • DR14 : BKP_TypeDef
  • DR15 : BKP_TypeDef
  • DR16 : BKP_TypeDef
  • DR17 : BKP_TypeDef
  • DR18 : BKP_TypeDef
  • DR19 : BKP_TypeDef
  • DR2 : BKP_TypeDef
  • DR20 : BKP_TypeDef
  • DR21 : BKP_TypeDef
  • DR22 : BKP_TypeDef
  • DR23 : BKP_TypeDef
  • DR24 : BKP_TypeDef
  • DR25 : BKP_TypeDef
  • DR26 : BKP_TypeDef
  • DR27 : BKP_TypeDef
  • DR28 : BKP_TypeDef
  • DR29 : BKP_TypeDef
  • DR3 : BKP_TypeDef
  • DR30 : BKP_TypeDef
  • DR31 : BKP_TypeDef
  • DR32 : BKP_TypeDef
  • DR33 : BKP_TypeDef
  • DR34 : BKP_TypeDef
  • DR35 : BKP_TypeDef
  • DR36 : BKP_TypeDef
  • DR37 : BKP_TypeDef
  • DR38 : BKP_TypeDef
  • DR39 : BKP_TypeDef
  • DR4 : BKP_TypeDef
  • DR40 : BKP_TypeDef
  • DR41 : BKP_TypeDef
  • DR42 : BKP_TypeDef
  • DR5 : BKP_TypeDef
  • DR6 : BKP_TypeDef
  • DR7 : BKP_TypeDef
  • DR8 : BKP_TypeDef
  • DR9 : BKP_TypeDef
  • DSRImpl : SD_CSD
  • DTIMER : SDIO_TypeDef


STM32F10x Standard Peripherals Firmware Library: Data Fields - Variables

  • Data Structures
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- e -

  • ECC : SD_CSD
  • ECCR2 : FSMC_Bank2_TypeDef
  • ECCR3 : FSMC_Bank3_TypeDef
  • EGR : TIM_TypeDef
  • EMR : EXTI_TypeDef
  • ERASE_OFFSET : SD_CardStatus
  • ERASE_SIZE : SD_CardStatus
  • ERASE_TIMEOUT : SD_CardStatus
  • EraseGrMul : SD_CSD
  • EraseGrSize : SD_CSD
  • ESR : CAN_TypeDef , CEC_TypeDef
  • EVCR : AFIO_TypeDef
  • EXTI_Line : EXTI_InitTypeDef
  • EXTI_LineCmd : EXTI_InitTypeDef
  • EXTI_Mode : EXTI_InitTypeDef
  • EXTI_Trigger : EXTI_InitTypeDef
  • EXTICR : AFIO_TypeDef
  • ExtId : CanTxMsg , CanRxMsg


STM32F10x Standard Peripherals Firmware Library: Data Fields - Variables

  • Data Structures
  • Data Structure Index
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  • Variables
  • a
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- f -

  • FA1R : CAN_TypeDef
  • FFA1R : CAN_TypeDef
  • FIFO : SDIO_TypeDef
  • FIFOCNT : SDIO_TypeDef
  • FileFormat : SD_CSD
  • FileFormatGrouop : SD_CSD
  • FM1R : CAN_TypeDef
  • FMI : CanRxMsg
  • FMR : CAN_TypeDef
  • Fourth_ID : NAND_IDTypeDef
  • FR1 : CAN_FilterRegister_TypeDef
  • FR2 : CAN_FilterRegister_TypeDef
  • FS1R : CAN_TypeDef
  • FSMC_AccessMode : FSMC_NORSRAMTimingInitTypeDef
  • FSMC_AddressHoldTime : FSMC_NORSRAMTimingInitTypeDef
  • FSMC_AddressSetupTime : FSMC_NORSRAMTimingInitTypeDef
  • FSMC_AsynchronousWait : FSMC_NORSRAMInitTypeDef
  • FSMC_AttributeSpaceTimingStruct : FSMC_NANDInitTypeDef , FSMC_PCCARDInitTypeDef
  • FSMC_Bank : FSMC_NORSRAMInitTypeDef , FSMC_NANDInitTypeDef
  • FSMC_BurstAccessMode : FSMC_NORSRAMInitTypeDef
  • FSMC_BusTurnAroundDuration : FSMC_NORSRAMTimingInitTypeDef
  • FSMC_CLKDivision : FSMC_NORSRAMTimingInitTypeDef
  • FSMC_CommonSpaceTimingStruct : FSMC_NANDInitTypeDef , FSMC_PCCARDInitTypeDef
  • FSMC_DataAddressMux : FSMC_NORSRAMInitTypeDef
  • FSMC_DataLatency : FSMC_NORSRAMTimingInitTypeDef
  • FSMC_DataSetupTime : FSMC_NORSRAMTimingInitTypeDef
  • FSMC_ECC : FSMC_NANDInitTypeDef
  • FSMC_ECCPageSize : FSMC_NANDInitTypeDef
  • FSMC_ExtendedMode : FSMC_NORSRAMInitTypeDef
  • FSMC_HiZSetupTime : FSMC_NAND_PCCARDTimingInitTypeDef
  • FSMC_HoldSetupTime : FSMC_NAND_PCCARDTimingInitTypeDef
  • FSMC_IOSpaceTimingStruct : FSMC_PCCARDInitTypeDef
  • FSMC_MemoryDataWidth : FSMC_NORSRAMInitTypeDef , FSMC_NANDInitTypeDef
  • FSMC_MemoryType : FSMC_NORSRAMInitTypeDef
  • FSMC_ReadWriteTimingStruct : FSMC_NORSRAMInitTypeDef
  • FSMC_SetupTime : FSMC_NAND_PCCARDTimingInitTypeDef
  • FSMC_TARSetupTime : FSMC_PCCARDInitTypeDef , FSMC_NANDInitTypeDef
  • FSMC_TCLRSetupTime : FSMC_PCCARDInitTypeDef , FSMC_NANDInitTypeDef
  • FSMC_Waitfeature : FSMC_PCCARDInitTypeDef , FSMC_NANDInitTypeDef
  • FSMC_WaitSetupTime : FSMC_NAND_PCCARDTimingInitTypeDef
  • FSMC_WaitSignal : FSMC_NORSRAMInitTypeDef
  • FSMC_WaitSignalActive : FSMC_NORSRAMInitTypeDef
  • FSMC_WaitSignalPolarity : FSMC_NORSRAMInitTypeDef
  • FSMC_WrapMode : FSMC_NORSRAMInitTypeDef
  • FSMC_WriteBurst : FSMC_NORSRAMInitTypeDef
  • FSMC_WriteOperation : FSMC_NORSRAMInitTypeDef
  • FSMC_WriteTimingStruct : FSMC_NORSRAMInitTypeDef
  • FTSR : EXTI_TypeDef


STM32F10x Standard Peripherals Firmware Library: Data Fields - Variables

  • Data Structures
  • Data Structure Index
  • Data Fields
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  • Variables
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- g -

  • GPIO_Mode : GPIO_InitTypeDef
  • GPIO_Pin : GPIO_InitTypeDef
  • GPIO_Speed : GPIO_InitTypeDef
  • GTPR : USART_TypeDef


STM32F10x Standard Peripherals Firmware Library: Data Fields - Variables

  • Data Structures
  • Data Structure Index
  • Data Fields
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  • Variables
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- h -

  • H : SC_ATR
  • HCLK_Frequency : RCC_ClocksTypeDef
  • Header : HDMI_CEC_Message
  • Height : _tFont
  • Hlenght : SC_ATR
  • HTR : ADC_TypeDef


STM32F10x Standard Peripherals Firmware Library: Data Fields - Variables

  • Data Structures
  • Data Structure Index
  • Data Fields
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  • Variables
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- i -

  • I2C_Ack : I2C_InitTypeDef
  • I2C_AcknowledgedAddress : I2C_InitTypeDef
  • I2C_ClockSpeed : I2C_InitTypeDef
  • I2C_DutyCycle : I2C_InitTypeDef
  • I2C_Mode : I2C_InitTypeDef
  • I2C_OwnAddress1 : I2C_InitTypeDef
  • I2S_AudioFreq : I2S_InitTypeDef
  • I2S_CPOL : I2S_InitTypeDef
  • I2S_DataFormat : I2S_InitTypeDef
  • I2S_MCLKOutput : I2S_InitTypeDef
  • I2S_Mode : I2S_InitTypeDef
  • I2S_Standard : I2S_InitTypeDef
  • I2SCFGR : SPI_TypeDef
  • I2SPR : SPI_TypeDef
  • ICR : SDIO_TypeDef
  • IDCODE : DBGMCU_TypeDef
  • IDE : CanTxMsg , CanRxMsg
  • IDR : GPIO_TypeDef , CRC_TypeDef
  • IER : CAN_TypeDef
  • IFCR : DMA_TypeDef
  • IMR : EXTI_TypeDef
  • ISR : DMA_TypeDef


STM32F10x Standard Peripherals Firmware Library: Data Fields - Variables

  • Data Structures
  • Data Structure Index
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- p -

  • Page : OneNAND_ADDRESS , NAND_ADDRESS
  • PartBlockRead : SD_CSD
  • PATT2 : FSMC_Bank2_TypeDef
  • PATT3 : FSMC_Bank3_TypeDef
  • PATT4 : FSMC_Bank4_TypeDef
  • PCLK1_Frequency : RCC_ClocksTypeDef
  • PCLK2_Frequency : RCC_ClocksTypeDef
  • PCR2 : FSMC_Bank2_TypeDef
  • PCR3 : FSMC_Bank3_TypeDef
  • PCR4 : FSMC_Bank4_TypeDef
  • PERFORMANCE_MOVE : SD_CardStatus
  • PermWrProtect : SD_CSD
  • PhysicalAddress_A : HDMI_CEC_Map
  • PhysicalAddress_B : HDMI_CEC_Map
  • PhysicalAddress_C : HDMI_CEC_Map
  • PhysicalAddress_D : HDMI_CEC_Map
  • PIO4 : FSMC_Bank4_TypeDef
  • PMEM2 : FSMC_Bank2_TypeDef
  • PMEM3 : FSMC_Bank3_TypeDef
  • PMEM4 : FSMC_Bank4_TypeDef
  • POWER : SDIO_TypeDef
  • PR : EXTI_TypeDef , IWDG_TypeDef
  • PRES : CEC_TypeDef
  • PRLH : RTC_TypeDef
  • PRLL : RTC_TypeDef
  • ProdName1 : SD_CID
  • ProdName2 : SD_CID
  • ProdRev : SD_CID
  • ProdSN : SD_CID
  • PSC : TIM_TypeDef
  • PTPSSIR : ETH_TypeDef
  • PTPTSAR : ETH_TypeDef
  • PTPTSCR : ETH_TypeDef
  • PTPTSHR : ETH_TypeDef
  • PTPTSHUR : ETH_TypeDef
  • PTPTSLR : ETH_TypeDef
  • PTPTSLUR : ETH_TypeDef
  • PTPTTHR : ETH_TypeDef
  • PTPTTLR : ETH_TypeDef


STM32F10x Standard Peripherals Firmware Library: Data Fields - Variables

  • Data Structures
  • Data Structure Index
  • Data Fields
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  • Variables
  • a
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- r -

  • RCA : SD_CardInfo
  • RCR : TIM_TypeDef
  • RdBlockLen : SD_CSD
  • RdBlockMisalign : SD_CSD
  • RDHR : CAN_FIFOMailBox_TypeDef
  • RDLR : CAN_FIFOMailBox_TypeDef
  • RDP : OB_TypeDef
  • RDTR : CAN_FIFOMailBox_TypeDef
  • RESERVED : FLASH_TypeDef
  • RESERVED0 : AFIO_TypeDef , I2C_TypeDef , RTC_TypeDef , SDIO_TypeDef , BKP_TypeDef , SPI_TypeDef , TIM_TypeDef , CAN_TypeDef , USART_TypeDef , CRC_TypeDef , ETH_TypeDef , FSMC_Bank2_TypeDef , FSMC_Bank3_TypeDef
  • RESERVED1 : SPI_TypeDef , TIM_TypeDef , USART_TypeDef
  • Reserved1 : SD_CSD , SD_CID
  • RESERVED1 : BKP_TypeDef , CAN_TypeDef , CRC_TypeDef , ETH_TypeDef , I2C_TypeDef , RTC_TypeDef , SDIO_TypeDef
  • RESERVED10 : BKP_TypeDef , TIM_TypeDef
  • RESERVED11 : BKP_TypeDef , TIM_TypeDef
  • RESERVED12 : BKP_TypeDef , TIM_TypeDef
  • RESERVED13 : BKP_TypeDef , TIM_TypeDef
  • RESERVED14 : BKP_TypeDef , TIM_TypeDef
  • RESERVED15 : BKP_TypeDef , TIM_TypeDef
  • RESERVED16 : BKP_TypeDef , TIM_TypeDef
  • RESERVED17 : BKP_TypeDef , TIM_TypeDef
  • RESERVED18 : BKP_TypeDef , TIM_TypeDef
  • RESERVED19 : BKP_TypeDef , TIM_TypeDef
  • RESERVED2 : USART_TypeDef
  • Reserved2 : SD_CSD , SD_CID
  • RESERVED2 : BKP_TypeDef , CAN_TypeDef , ETH_TypeDef , I2C_TypeDef , RTC_TypeDef , SPI_TypeDef , TIM_TypeDef
  • RESERVED20 : BKP_TypeDef
  • RESERVED21 : BKP_TypeDef
  • RESERVED22 : BKP_TypeDef
  • RESERVED23 : BKP_TypeDef
  • RESERVED24 : BKP_TypeDef
  • RESERVED25 : BKP_TypeDef
  • RESERVED26 : BKP_TypeDef
  • RESERVED27 : BKP_TypeDef
  • RESERVED28 : BKP_TypeDef
  • RESERVED29 : BKP_TypeDef
  • Reserved3 : SD_CSD
  • RESERVED3 : BKP_TypeDef , CAN_TypeDef , ETH_TypeDef , I2C_TypeDef , RTC_TypeDef , SPI_TypeDef , TIM_TypeDef , USART_TypeDef
  • RESERVED30 : BKP_TypeDef
  • RESERVED31 : BKP_TypeDef
  • RESERVED32 : BKP_TypeDef
  • RESERVED33 : BKP_TypeDef
  • RESERVED34 : BKP_TypeDef
  • RESERVED35 : BKP_TypeDef
  • RESERVED36 : BKP_TypeDef
  • RESERVED37 : BKP_TypeDef
  • RESERVED38 : BKP_TypeDef
  • RESERVED39 : BKP_TypeDef
  • Reserved4 : SD_CSD
  • RESERVED4 : CAN_TypeDef , ETH_TypeDef , I2C_TypeDef , RTC_TypeDef , SPI_TypeDef , TIM_TypeDef , USART_TypeDef , BKP_TypeDef
  • RESERVED40 : BKP_TypeDef
  • RESERVED41 : BKP_TypeDef
  • RESERVED42 : BKP_TypeDef
  • RESERVED43 : BKP_TypeDef
  • RESERVED44 : BKP_TypeDef
  • RESERVED45 : BKP_TypeDef
  • RESERVED5 : CAN_TypeDef , ETH_TypeDef , TIM_TypeDef , BKP_TypeDef , SPI_TypeDef , RTC_TypeDef , I2C_TypeDef , USART_TypeDef
  • RESERVED6 : USART_TypeDef , I2C_TypeDef , BKP_TypeDef , ETH_TypeDef , SPI_TypeDef , RTC_TypeDef , TIM_TypeDef
  • RESERVED7 : SPI_TypeDef , ETH_TypeDef , TIM_TypeDef , BKP_TypeDef , RTC_TypeDef , I2C_TypeDef
  • RESERVED8 : I2C_TypeDef , SPI_TypeDef , ETH_TypeDef , BKP_TypeDef , TIM_TypeDef , RTC_TypeDef
  • RESERVED9 : ETH_TypeDef , BKP_TypeDef , RTC_TypeDef , TIM_TypeDef
  • RESP1 : SDIO_TypeDef
  • RESP2 : SDIO_TypeDef
  • RESP3 : SDIO_TypeDef
  • RESP4 : SDIO_TypeDef
  • RESPCMD : SDIO_TypeDef
  • RF0R : CAN_TypeDef
  • RF1R : CAN_TypeDef
  • RIR : CAN_FIFOMailBox_TypeDef
  • RLR : IWDG_TypeDef
  • RTCCR : BKP_TypeDef
  • RTR : CanTxMsg , CanRxMsg
  • RTSR : EXTI_TypeDef
  • RXCRCR : SPI_TypeDef
  • RXD : CEC_TypeDef
  • RxMessageLength : HDMI_CEC_Message


STM32F10x Standard Peripherals Firmware Library: Data Fields - Variables

  • Data Structures
  • Data Structure Index
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- s -

  • SD_CARD_TYPE : SD_CardStatus
  • SD_cid : SD_CardInfo
  • SD_csd : SD_CardInfo
  • SDIO_Argument : SDIO_CmdInitTypeDef
  • SDIO_BusWide : SDIO_InitTypeDef
  • SDIO_ClockBypass : SDIO_InitTypeDef
  • SDIO_ClockDiv : SDIO_InitTypeDef
  • SDIO_ClockEdge : SDIO_InitTypeDef
  • SDIO_ClockPowerSave : SDIO_InitTypeDef
  • SDIO_CmdIndex : SDIO_CmdInitTypeDef
  • SDIO_CPSM : SDIO_CmdInitTypeDef
  • SDIO_DataBlockSize : SDIO_DataInitTypeDef
  • SDIO_DataLength : SDIO_DataInitTypeDef
  • SDIO_DataTimeOut : SDIO_DataInitTypeDef
  • SDIO_DPSM : SDIO_DataInitTypeDef
  • SDIO_HardwareFlowControl : SDIO_InitTypeDef
  • SDIO_Response : SDIO_CmdInitTypeDef
  • SDIO_TransferDir : SDIO_DataInitTypeDef
  • SDIO_TransferMode : SDIO_DataInitTypeDef
  • SDIO_Wait : SDIO_CmdInitTypeDef
  • SECURED_MODE : SD_CardStatus
  • sFIFOMailBox : CAN_TypeDef
  • sFilterRegister : CAN_TypeDef
  • SIZE_OF_PROTECTED_AREA : SD_CardStatus
  • SMCR : TIM_TypeDef
  • SMPR1 : ADC_TypeDef
  • SMPR2 : ADC_TypeDef
  • SPEED_CLASS : SD_CardStatus
  • SPI_BaudRatePrescaler : SPI_InitTypeDef
  • SPI_CPHA : SPI_InitTypeDef
  • SPI_CPOL : SPI_InitTypeDef
  • SPI_CRCPolynomial : SPI_InitTypeDef
  • SPI_DataSize : SPI_InitTypeDef
  • SPI_Direction : SPI_InitTypeDef
  • SPI_FirstBit : SPI_InitTypeDef
  • SPI_Mode : SPI_InitTypeDef
  • SPI_NSS : SPI_InitTypeDef
  • SQR1 : ADC_TypeDef
  • SQR2 : ADC_TypeDef
  • SQR3 : ADC_TypeDef
  • SR : SPI_TypeDef , USART_TypeDef , IWDG_TypeDef , FLASH_TypeDef , ADC_TypeDef , WWDG_TypeDef , TIM_TypeDef
  • SR1 : I2C_TypeDef
  • SR2 : I2C_TypeDef , FSMC_Bank2_TypeDef
  • SR3 : FSMC_Bank3_TypeDef
  • SR4 : FSMC_Bank4_TypeDef
  • STA : SDIO_TypeDef
  • StdId : CanTxMsg , CanRxMsg
  • sTxMailBox : CAN_TypeDef
  • SWIER : EXTI_TypeDef
  • SWTRIGR : DAC_TypeDef
  • SYSCLK_Frequency : RCC_ClocksTypeDef
  • SysSpecVersion : SD_CSD


STM32F10x Standard Peripherals Firmware Library: Data Fields - Variables

  • Data Structures
  • Data Structure Index
  • Data Fields
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  • a
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- t -

  • T : SC_ATR
  • T0 : SC_ATR
  • TAAC : SD_CSD
  • table : _tFont
  • TDHR : CAN_TxMailBox_TypeDef
  • TDLR : CAN_TxMailBox_TypeDef
  • TDTR : CAN_TxMailBox_TypeDef
  • TempWrProtect : SD_CSD
  • Third_ID : NAND_IDTypeDef
  • TIM_AutomaticOutput : TIM_BDTRInitTypeDef
  • TIM_Break : TIM_BDTRInitTypeDef
  • TIM_BreakPolarity : TIM_BDTRInitTypeDef
  • TIM_Channel : TIM_ICInitTypeDef
  • TIM_ClockDivision : TIM_TimeBaseInitTypeDef
  • TIM_CounterMode : TIM_TimeBaseInitTypeDef
  • TIM_DeadTime : TIM_BDTRInitTypeDef
  • TIM_ICFilter : TIM_ICInitTypeDef
  • TIM_ICPolarity : TIM_ICInitTypeDef
  • TIM_ICPrescaler : TIM_ICInitTypeDef
  • TIM_ICSelection : TIM_ICInitTypeDef
  • TIM_LOCKLevel : TIM_BDTRInitTypeDef
  • TIM_OCIdleState : TIM_OCInitTypeDef
  • TIM_OCMode : TIM_OCInitTypeDef
  • TIM_OCNIdleState : TIM_OCInitTypeDef
  • TIM_OCNPolarity : TIM_OCInitTypeDef
  • TIM_OCPolarity : TIM_OCInitTypeDef
  • TIM_OSSIState : TIM_BDTRInitTypeDef
  • TIM_OSSRState : TIM_BDTRInitTypeDef
  • TIM_OutputNState : TIM_OCInitTypeDef
  • TIM_OutputState : TIM_OCInitTypeDef
  • TIM_Period : TIM_TimeBaseInitTypeDef
  • TIM_Prescaler : TIM_TimeBaseInitTypeDef
  • TIM_Pulse : TIM_OCInitTypeDef
  • TIM_RepetitionCounter : TIM_TimeBaseInitTypeDef
  • TIR : CAN_TxMailBox_TypeDef
  • Tlenght : SC_ATR
  • TouchDetected : TS_STATE
  • TRISE : I2C_TypeDef
  • TS : SC_ATR
  • TSR : CAN_TypeDef
  • TXCRCR : SPI_TypeDef
  • TXD : CEC_TypeDef
  • TxMessageLength : HDMI_CEC_Message


STM32F10x Standard Peripherals Firmware Library: Data Fields - Variables

  • Data Structures
  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
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- u -

  • USART_BaudRate : USART_InitTypeDef
  • USART_Clock : USART_ClockInitTypeDef
  • USART_CPHA : USART_ClockInitTypeDef
  • USART_CPOL : USART_ClockInitTypeDef
  • USART_HardwareFlowControl : USART_InitTypeDef
  • USART_LastBit : USART_ClockInitTypeDef
  • USART_Mode : USART_InitTypeDef
  • USART_Parity : USART_InitTypeDef
  • USART_StopBits : USART_InitTypeDef
  • USART_WordLength : USART_InitTypeDef
  • USER : OB_TypeDef


STM32F10x Standard Peripherals Firmware Library: Data Fields - Variables

  • Data Structures
  • Data Structure Index
  • Data Fields
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  • Variables
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  • x
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- w -

  • Width : _tFont
  • WrBlockMisalign : SD_CSD
  • WriteBlockPaPartial : SD_CSD
  • WRP0 : OB_TypeDef
  • WRP1 : OB_TypeDef
  • WRP2 : OB_TypeDef
  • WRP3 : OB_TypeDef
  • WRPR : FLASH_TypeDef
  • WrProtectGrEnable : SD_CSD
  • WrProtectGrSize : SD_CSD
  • WrSpeedFact : SD_CSD


STM32F10x Standard Peripherals Firmware Library: Data Fields - Variables

  • Data Structures
  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
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  • x
  • y
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- x -

  • X : Point , TS_STATE


STM32F10x Standard Peripherals Firmware Library: Data Fields - Variables

  • Data Structures
  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
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  • x
  • y
  • z

- y -

  • Y : Point , TS_STATE


STM32F10x Standard Peripherals Firmware Library: fwlib_drivers.txt File Reference

  • File List
  • Globals

fwlib_drivers.txt File Reference

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: fwlib_examples.txt File Reference

  • File List
  • Globals

fwlib_examples.txt File Reference

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: STM32F10x Standard Peripheral's Examples

STM32F10x Standard Peripheral's Examples

  • ADC
    • 3 ADCs DMA example
    • ADC1 DMA example
    • ADC analog watchdog example
    • ADC external lines trigger example
    • ADC regular simultaneous dual mode example
    • ADC TIM trigger and auto-injection example
  • BKP
    • Backup Data example
    • BKP Tamper example
  • CAN
    • Dual CAN example
    • CAN LoopBack example
    • CAN Networking example
  • CEC
    • CEC Data Exchange using Interrupt example
  • CortexM3
    • CortexM3 BitBand example
    • CortexM3 Mode Privilege example
    • CortexM3 MPU example
  • CRC
    • CRC Calculation example
  • DAC
    • DAC dual mode sine wave example
    • DAC one channel noise wave example
    • DAC one channel DMA escalator example
    • DAC two channels triangle wave example
  • DMA
    • DMA_EXAMPLES
    • DMA ADC1 TIM1 example
    • DMA FLASH to RAM example
    • DMA FSMC example
    • DMA I2C to RAM example
    • DMA SPI to RAM example
  • EXTI
    • EXTI configuration example
  • FLASH
    • FLASH Program example
    • XL-Density devices FLASH Dual Boot capability example
    • FLASH Write Protection example
  • FSMC
    • FSMC NAND example
    • FSMC NOR example
    • FSMC NOR CodeExecute example
    • FSMC NOR CodeExecute example binary directory
    • FSMC OneNAND example
    • FSMC SRAM example
    • FSMC SRAM DataMemory example
  • GPIO
    • GPIO IO Toggle example
    • GPIO JTAG Remap example
  • I2C
    • I2C and M24CXX EEPROM communication example
    • I2C and LM75 Temperature Sensor communication example
    • I2C and STMPE811 IO Expander communication example
  • I2S
    • I2S Interrupt example
    • SPI_I2S_Switch example
  • IWDG
    • IWDG Reset example
  • Lib_DEBUG
    • Lib_DEBUG Run Time Checking example
  • NVIC
    • DMA in WFI mode example
    • NVIC IRQ Mask example
    • NVIC IRQ Priority example
    • NVIC VectorTable Relocation example
  • PWR
    • PWR PVD example
    • PWR STANDBY example
    • PWR STOP example
  • RCC
    • RCC Clock configuration example
  • RTC
    • RTC Calendar example
    • RTC LSI_Calib example
  • SDIO
    • SDIO Micro SD Card example
  • SPI
    • SPI CRC example
    • SPI DMA example
    • SPI Full Duplex Software NSS example
    • SPI SPI_FLASH example
    • SPI Simplex Interrupt example
  • Systick
    • SysTick Time Base example
  • TIM
    • TIM 6 Steps example
    • TIM 7 PWM Output example
    • TIM Cascade Synchro example
    • TIM Complementary Signals example
    • TIM DMA example
    • TIM1 DMA Burst transfer example
    • TIM External Trigger Synchro example
    • TIM Input Capture example
    • TIM OC Active example
    • TIM OC Inactive example
    • TIM OC Toggle example
    • TIM One Pulse example
    • TIM Parallel Synchro example
    • TIM PWM Input example
    • TIM PWM Output example
    • TIM1 Synchro example
    • TIM15 Complementary Signals example
    • TIM9 OC Toggle example
    • TIM10 PWM Output example
    • TIM Time Base example
  • USART
    • USART DMA Interrupt example
    • USART DMA Polling example
    • USART Half Duplex example
    • USART Hyperterminal Hardware Flow Control example
    • USART Hyperterminal interrupt example
    • USART Interrupts example
    • USART IrDA Receive example
    • USART IrDA Transmit example
    • USART Multi Processor example
    • USART Polling example
    • USART Printf example
    • USART Smartcard example
    • USART Synchronous example
  • WWDG
    • WWDG Reset example


STM32F10x Standard Peripherals Firmware Library: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
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  • n
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  • r
  • s
  • t
  • u
  • v
  • w
  • y
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- j -

  • j : STM32F10x_StdPeriph_Examples/FSMC/NAND/main.c , STM32F10x_StdPeriph_Examples/FSMC/OneNAND/main.c
  • JDR_Offset : stm32f10x_adc.c
  • JOY_CENTER : stm32_eval.h
  • JOY_DOWN : stm3210c_eval_ioe.h , stm32_eval.h
  • JOY_IO_DOWN : stm3210c_eval_ioe.h
  • JOY_IO_LEFT : stm3210c_eval_ioe.h
  • JOY_IO_NONE : stm3210c_eval_ioe.h
  • JOY_IO_PINS : stm3210c_eval_ioe.h
  • JOY_IO_RIGHT : stm3210c_eval_ioe.h
  • JOY_IO_SEL : stm3210c_eval_ioe.h
  • JOY_IO_UP : stm3210c_eval_ioe.h
  • JOY_LEFT : stm3210c_eval_ioe.h , stm32_eval.h
  • JOY_NONE : stm3210c_eval_ioe.h , stm32_eval.h
  • JOY_RIGHT : stm3210c_eval_ioe.h , stm32_eval.h
  • JOY_SEL : stm3210c_eval_ioe.h , stm32_eval.h
  • JOY_State_TypeDef : stm32_eval.h
  • JOY_UP : stm3210c_eval_ioe.h , stm32_eval.h
  • JOYState_TypeDef : stm3210c_eval_ioe.h , stm32_eval.h
  • JSQR_JL_Reset : stm32f10x_adc.c
  • JSQR_JL_Set : stm32f10x_adc.c
  • JSQR_JSQ_Set : stm32f10x_adc.c
  • Jump_To_Application : STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/main.c
  • JumpAddress : STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/main.c


STM32F10x Standard Peripherals Firmware Library: Globals

  • File List
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- k -

  • k : STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/main.c
  • KEY_BUTTON_EXTI_IRQn : stm32100b_eval.h , stm3210b_eval.h , stm3210c_eval.h , stm32100e_eval.h , stm3210e_eval.h , stm32l152_eval.h
  • KEY_BUTTON_EXTI_LINE : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210c_eval.h , stm3210e_eval.h , stm32l152_eval.h
  • KEY_BUTTON_EXTI_PIN_SOURCE : stm3210b_eval.h , stm3210c_eval.h , stm3210e_eval.h , stm32l152_eval.h , stm32100b_eval.h , stm32100e_eval.h
  • KEY_BUTTON_EXTI_PORT_SOURCE : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210c_eval.h , stm3210e_eval.h , stm32l152_eval.h
  • KEY_BUTTON_GPIO_CLK : stm32l152_eval.h , stm32100e_eval.h , stm32100b_eval.h , stm3210b_eval.h , stm3210c_eval.h , stm3210e_eval.h
  • KEY_BUTTON_GPIO_PORT : stm32l152_eval.h , stm3210c_eval.h , stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210e_eval.h
  • KEY_BUTTON_PIN : stm32100b_eval.h , stm32l152_eval.h , stm3210b_eval.h , stm3210e_eval.h , stm32100e_eval.h , stm3210c_eval.h
  • KEY_NOT_PRESSED : STM32F10x_StdPeriph_Examples/CAN/Networking/main.c
  • KEY_PRESSED : STM32F10x_StdPeriph_Examples/CAN/Networking/main.c
  • KeyNumber : STM32F10x_StdPeriph_Examples/CAN/Networking/main.c , STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_it.c
  • KR_KEY_Enable : stm32f10x_iwdg.c
  • KR_KEY_Reload : stm32f10x_iwdg.c


STM32F10x Standard Peripherals Firmware Library: Globals

  • File List
  • Globals
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  • Functions
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  • h
  • i
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  • s
  • t
  • u
  • v
  • w
  • y
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- l -

  • LCD : stm32100e_eval_lcd.c , stm3210e_eval_lcd.c
  • LCD_BASE : stm3210e_eval_lcd.c , stm32100e_eval_lcd.c
  • LCD_Clear() : stm32100e_eval_lcd.h , stm32l152_eval_lcd.h , stm3210b_eval_lcd.c , stm32100b_eval_lcd.c , stm3210b_eval_lcd.h , stm3210c_eval_lcd.c , stm32100b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.c , stm32100e_eval_lcd.c , stm3210e_eval_lcd.h , stm32l152_eval_lcd.c
  • LCD_ClearLine() : stm32100b_eval_lcd.c , stm32100b_eval_lcd.h , stm32100e_eval_lcd.c , stm32100e_eval_lcd.h , stm3210b_eval_lcd.c , stm3210b_eval_lcd.h , stm3210c_eval_lcd.c , stm3210c_eval_lcd.h , stm3210e_eval_lcd.c , stm3210e_eval_lcd.h , stm32l152_eval_lcd.c , stm32l152_eval_lcd.h
  • LCD_ClosedPolyLine() : stm32100e_eval_lcd.h , stm3210b_eval_lcd.c , stm3210b_eval_lcd.h , stm3210c_eval_lcd.c , stm3210c_eval_lcd.h , stm3210e_eval_lcd.c , stm3210e_eval_lcd.h , stm32l152_eval_lcd.c , stm32l152_eval_lcd.h , stm32100b_eval_lcd.c , stm32100b_eval_lcd.h , stm32100e_eval_lcd.c
  • LCD_ClosedPolyLineRelative() : stm32100b_eval_lcd.c , stm32100b_eval_lcd.h , stm32100e_eval_lcd.c , stm32100e_eval_lcd.h , stm3210b_eval_lcd.c , stm3210b_eval_lcd.h , stm3210c_eval_lcd.c , stm3210c_eval_lcd.h , stm3210e_eval_lcd.c , stm3210e_eval_lcd.h , stm32l152_eval_lcd.c , stm32l152_eval_lcd.h
  • LCD_COLOR_BLACK : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_COLOR_BLUE : stm32l152_eval_lcd.h , stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h
  • LCD_COLOR_BLUE2 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_COLOR_CYAN : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_COLOR_GREEN : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_COLOR_GREY : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_COLOR_MAGENTA : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_COLOR_RED : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_COLOR_WHITE : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_COLOR_YELLOW : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_CtrlLinesConfig() : stm32100b_eval_lcd.c , stm32100b_eval_lcd.h , stm32100e_eval_lcd.c , stm32100e_eval_lcd.h , stm3210b_eval_lcd.c , stm3210b_eval_lcd.h , stm3210c_eval_lcd.c , stm3210c_eval_lcd.h , stm3210e_eval_lcd.c , stm3210e_eval_lcd.h , stm32l152_eval_lcd.c , stm32l152_eval_lcd.h
  • LCD_CtrlLinesWrite() : stm3210b_eval_lcd.h , stm3210c_eval_lcd.c , stm3210c_eval_lcd.h , stm32l152_eval_lcd.c , stm32l152_eval_lcd.h , stm32100b_eval_lcd.c , stm32100b_eval_lcd.h , stm3210b_eval_lcd.c
  • LCD_Currentfonts : stm32100b_eval_lcd.c , stm32100e_eval_lcd.c , stm3210b_eval_lcd.c , stm3210c_eval_lcd.c , stm3210e_eval_lcd.c , stm32l152_eval_lcd.c
  • LCD_DEFAULT_FONT : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_DeInit() : stm32100b_eval_lcd.c , stm32100b_eval_lcd.h , stm32100e_eval_lcd.c , stm32100e_eval_lcd.h , stm3210b_eval_lcd.c , stm3210b_eval_lcd.h , stm3210c_eval_lcd.c , stm3210c_eval_lcd.h , stm3210e_eval_lcd.c , stm3210e_eval_lcd.h
  • LCD_DIR_HORIZONTAL : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_DIR_VERTICAL : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_DisplayChar() : stm32100b_eval_lcd.c , stm32100b_eval_lcd.h , stm32100e_eval_lcd.c , stm32100e_eval_lcd.h , stm3210b_eval_lcd.c , stm3210b_eval_lcd.h , stm3210c_eval_lcd.c , stm3210c_eval_lcd.h , stm3210e_eval_lcd.c , stm3210e_eval_lcd.h , stm32l152_eval_lcd.c , stm32l152_eval_lcd.h
  • LCD_DisplayOff() : stm32100b_eval_lcd.c , stm32100b_eval_lcd.h , stm32100e_eval_lcd.c , stm32100e_eval_lcd.h , stm3210b_eval_lcd.c , stm3210b_eval_lcd.h , stm3210c_eval_lcd.c , stm3210c_eval_lcd.h , stm3210e_eval_lcd.c , stm3210e_eval_lcd.h , stm32l152_eval_lcd.c , stm32l152_eval_lcd.h
  • LCD_DisplayOn() : stm32100b_eval_lcd.c , stm32100b_eval_lcd.h , stm32100e_eval_lcd.c , stm32100e_eval_lcd.h , stm3210b_eval_lcd.c , stm3210b_eval_lcd.h , stm3210c_eval_lcd.c , stm3210c_eval_lcd.h , stm3210e_eval_lcd.c , stm3210e_eval_lcd.h , stm32l152_eval_lcd.c , stm32l152_eval_lcd.h
  • LCD_DisplayStringLine() : stm32100b_eval_lcd.c , stm32100b_eval_lcd.h , stm32100e_eval_lcd.c , stm32100e_eval_lcd.h , stm3210b_eval_lcd.c , stm3210b_eval_lcd.h , stm3210c_eval_lcd.c , stm3210c_eval_lcd.h , stm3210e_eval_lcd.c , stm3210e_eval_lcd.h , stm32l152_eval_lcd.c , stm32l152_eval_lcd.h
  • LCD_DrawBMP() : stm32100b_eval_lcd.h , stm3210b_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_DrawChar() : stm32100b_eval_lcd.c , stm32100b_eval_lcd.h , stm32100e_eval_lcd.c , stm32100e_eval_lcd.h , stm3210b_eval_lcd.c , stm3210b_eval_lcd.h , stm3210c_eval_lcd.c , stm3210c_eval_lcd.h , stm3210e_eval_lcd.c , stm3210e_eval_lcd.h , stm32l152_eval_lcd.c , stm32l152_eval_lcd.h
  • LCD_DrawCircle() : stm32100b_eval_lcd.c , stm32100b_eval_lcd.h , stm32100e_eval_lcd.c , stm32100e_eval_lcd.h , stm3210b_eval_lcd.c , stm3210b_eval_lcd.h , stm3210c_eval_lcd.c , stm3210c_eval_lcd.h , stm3210e_eval_lcd.c , stm3210e_eval_lcd.h , stm32l152_eval_lcd.c , stm32l152_eval_lcd.h
  • LCD_DrawFullCircle() : stm32100b_eval_lcd.c , stm32100b_eval_lcd.h , stm32100e_eval_lcd.c , stm32100e_eval_lcd.h , stm3210b_eval_lcd.c , stm3210b_eval_lcd.h , stm3210c_eval_lcd.c , stm3210c_eval_lcd.h , stm3210e_eval_lcd.c , stm3210e_eval_lcd.h , stm32l152_eval_lcd.c , stm32l152_eval_lcd.h
  • LCD_DrawFullRect() : stm32100e_eval_lcd.c , stm32100e_eval_lcd.h , stm3210b_eval_lcd.c , stm3210b_eval_lcd.h , stm3210c_eval_lcd.c , stm3210c_eval_lcd.h , stm3210e_eval_lcd.c , stm3210e_eval_lcd.h , stm32l152_eval_lcd.c , stm32l152_eval_lcd.h , stm32100b_eval_lcd.c , stm32100b_eval_lcd.h
  • LCD_DrawLine() : stm32100b_eval_lcd.c , stm32100b_eval_lcd.h , stm32100e_eval_lcd.c , stm32100e_eval_lcd.h , stm3210b_eval_lcd.c , stm3210b_eval_lcd.h , stm3210c_eval_lcd.c , stm3210c_eval_lcd.h , stm3210e_eval_lcd.c , stm3210e_eval_lcd.h , stm32l152_eval_lcd.c , stm32l152_eval_lcd.h
  • LCD_DrawMonoPict() : stm32100b_eval_lcd.c , stm32100b_eval_lcd.h , stm32100e_eval_lcd.c , stm32100e_eval_lcd.h , stm3210b_eval_lcd.c , stm3210b_eval_lcd.h , stm3210c_eval_lcd.c , stm3210c_eval_lcd.h , stm3210e_eval_lcd.c , stm3210e_eval_lcd.h , stm32l152_eval_lcd.c , stm32l152_eval_lcd.h
  • LCD_DrawRect() : stm32100b_eval_lcd.c , stm32100b_eval_lcd.h , stm32100e_eval_lcd.c , stm32100e_eval_lcd.h , stm3210b_eval_lcd.c , stm3210b_eval_lcd.h , stm3210c_eval_lcd.c , stm3210c_eval_lcd.h , stm3210e_eval_lcd.c , stm3210e_eval_lcd.h , stm32l152_eval_lcd.c , stm32l152_eval_lcd.h
  • LCD_DrawUniLine() : stm32100b_eval_lcd.c , stm32100b_eval_lcd.h , stm32100e_eval_lcd.c , stm32100e_eval_lcd.h , stm3210b_eval_lcd.c , stm3210b_eval_lcd.h , stm3210c_eval_lcd.c , stm3210c_eval_lcd.h , stm3210e_eval_lcd.c , stm3210e_eval_lcd.h , stm32l152_eval_lcd.c , stm32l152_eval_lcd.h
  • LCD_FillPolyLine() : stm32100b_eval_lcd.c , stm32100b_eval_lcd.h , stm32100e_eval_lcd.c , stm32100e_eval_lcd.h , stm3210b_eval_lcd.c , stm3210b_eval_lcd.h , stm3210c_eval_lcd.c , stm3210c_eval_lcd.h , stm3210e_eval_lcd.c , stm3210e_eval_lcd.h , stm32l152_eval_lcd.c , stm32l152_eval_lcd.h
  • LCD_FSMCConfig() : stm32100e_eval_lcd.c , stm32100e_eval_lcd.h , stm3210e_eval_lcd.c , stm3210e_eval_lcd.h
  • LCD_GetColors() : stm32100b_eval_lcd.c , stm32100b_eval_lcd.h , stm32100e_eval_lcd.c , stm32100e_eval_lcd.h , stm3210b_eval_lcd.c , stm3210b_eval_lcd.h , stm3210c_eval_lcd.c , stm3210c_eval_lcd.h , stm3210e_eval_lcd.c , stm3210e_eval_lcd.h , stm32l152_eval_lcd.c , stm32l152_eval_lcd.h
  • LCD_GetFont() : stm32100b_eval_lcd.c , stm32100b_eval_lcd.h , stm32100e_eval_lcd.c , stm32100e_eval_lcd.h , stm3210b_eval_lcd.c , stm3210b_eval_lcd.h , stm3210c_eval_lcd.c , stm3210c_eval_lcd.h , stm3210e_eval_lcd.c , stm3210e_eval_lcd.h , stm32l152_eval_lcd.c , stm32l152_eval_lcd.h
  • LCD_GLASS_Clear() : stm32l152_eval_glass_lcd.c , stm32l152_eval_glass_lcd.h
  • LCD_GLASS_ClearChar() : stm32l152_eval_glass_lcd.c , stm32l152_eval_glass_lcd.h
  • LCD_GLASS_DisplayChar() : stm32l152_eval_glass_lcd.c , stm32l152_eval_glass_lcd.h
  • LCD_GLASS_DisplayString() : stm32l152_eval_glass_lcd.c , stm32l152_eval_glass_lcd.h
  • LCD_GLASS_Init() : stm32l152_eval_glass_lcd.c , stm32l152_eval_glass_lcd.h
  • LCD_GLASS_ScrollString() : stm32l152_eval_glass_lcd.c , stm32l152_eval_glass_lcd.h
  • LCD_GLASS_WriteChar() : stm32l152_eval_glass_lcd.c , stm32l152_eval_glass_lcd.h
  • LCD_GPIOConfig() : stm32l152_eval_glass_lcd.c
  • LCD_HX8312 : stm32100b_eval_lcd.c , stm3210b_eval_lcd.c
  • LCD_ILI9320 : stm32100b_eval_lcd.c , stm3210b_eval_lcd.c , stm32l152_eval_lcd.c
  • LCD_LINE_0 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_LINE_1 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_LINE_10 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_LINE_11 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_LINE_12 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_LINE_13 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_LINE_14 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_LINE_15 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_LINE_16 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_LINE_17 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_LINE_18 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_LINE_19 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_LINE_2 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_LINE_20 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_LINE_21 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_LINE_22 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_LINE_23 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_LINE_24 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_LINE_25 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_LINE_26 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_LINE_27 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_LINE_28 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_LINE_29 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_LINE_3 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_LINE_4 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_LINE_5 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_LINE_6 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_LINE_7 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_LINE_8 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_LINE_9 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_NCS_GPIO_CLK : stm32100b_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_NCS_GPIO_PORT : stm32100b_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_NCS_PIN : stm32100b_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_nCS_StartByte() : stm32100b_eval_lcd.c , stm32100b_eval_lcd.h , stm3210b_eval_lcd.c , stm3210b_eval_lcd.h , stm3210c_eval_lcd.c , stm3210c_eval_lcd.h , stm32l152_eval_lcd.c , stm32l152_eval_lcd.h
  • LCD_NWR_GPIO_CLK : stm32100b_eval_lcd.h , stm3210b_eval_lcd.h
  • LCD_NWR_GPIO_PORT : stm32100b_eval_lcd.h , stm3210b_eval_lcd.h
  • LCD_NWR_PIN : stm32100b_eval_lcd.h , stm3210b_eval_lcd.h
  • LCD_PIXEL_HEIGHT : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_PIXEL_WIDTH : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_PolyLine() : stm32100b_eval_lcd.c , stm32100b_eval_lcd.h , stm32100e_eval_lcd.c , stm32100e_eval_lcd.h , stm3210b_eval_lcd.c , stm3210b_eval_lcd.h , stm3210c_eval_lcd.c , stm3210c_eval_lcd.h , stm3210e_eval_lcd.c , stm3210e_eval_lcd.h , stm32l152_eval_lcd.c , stm32l152_eval_lcd.h
  • LCD_PolyLineRelative() : stm32100b_eval_lcd.c , stm32100b_eval_lcd.h , stm32100e_eval_lcd.c , stm32100e_eval_lcd.h , stm3210b_eval_lcd.c , stm3210b_eval_lcd.h , stm3210c_eval_lcd.c , stm3210c_eval_lcd.h , stm3210e_eval_lcd.c , stm3210e_eval_lcd.h , stm32l152_eval_lcd.c , stm32l152_eval_lcd.h
  • LCD_PolyLineRelativeClosed() : stm32100b_eval_lcd.c , stm32100e_eval_lcd.c , stm3210b_eval_lcd.c , stm3210c_eval_lcd.c , stm3210e_eval_lcd.c , stm32l152_eval_lcd.c
  • LCD_PowerOn() : stm32100b_eval_lcd.c , stm32100b_eval_lcd.h , stm32100e_eval_lcd.c , stm32100e_eval_lcd.h , stm3210b_eval_lcd.c , stm3210b_eval_lcd.h , stm3210c_eval_lcd.c , stm3210c_eval_lcd.h , stm3210e_eval_lcd.c , stm3210e_eval_lcd.h , stm32l152_eval_lcd.c , stm32l152_eval_lcd.h
  • LCD_READ_REG : stm32100b_eval_lcd.c , stm3210b_eval_lcd.c , stm3210c_eval_lcd.c , stm32l152_eval_lcd.c
  • LCD_ReadRAM() : stm32100e_eval_lcd.c , stm32100e_eval_lcd.h , stm3210e_eval_lcd.c , stm3210e_eval_lcd.h
  • LCD_ReadReg() : stm32100b_eval_lcd.c , stm32100b_eval_lcd.h , stm32100e_eval_lcd.c , stm32100e_eval_lcd.h , stm3210b_eval_lcd.c , stm3210b_eval_lcd.h , stm3210c_eval_lcd.c , stm3210c_eval_lcd.h , stm3210e_eval_lcd.c , stm3210e_eval_lcd.h , stm32l152_eval_lcd.c , stm32l152_eval_lcd.h
  • LCD_REG_0 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_1 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_10 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_106 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_118 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_12 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_128 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_129 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_13 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_130 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_131 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_132 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_133 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_134 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_135 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_136 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_137 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_139 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_14 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_140 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_141 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_143 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_144 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_145 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_146 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_147 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_148 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_149 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_15 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_150 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_151 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_152 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_153 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_154 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_157 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_16 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_17 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_18 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_19 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_192 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_193 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_2 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_20 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_21 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_22 : stm32l152_eval_lcd.h , stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h
  • LCD_REG_227 : stm32100b_eval_lcd.h , stm3210b_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_229 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_23 : stm3210b_eval_lcd.h , stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_231 : stm32100b_eval_lcd.h , stm3210b_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_239 : stm3210b_eval_lcd.h , stm32100b_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_24 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_25 : stm32100b_eval_lcd.h , stm3210e_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_26 : stm3210b_eval_lcd.h , stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_27 : stm3210e_eval_lcd.h , stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_28 : stm3210b_eval_lcd.h , stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_29 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_3 : stm3210b_eval_lcd.h , stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_30 : stm3210e_eval_lcd.h , stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_31 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_32 : stm32100b_eval_lcd.h , stm3210e_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_33 : stm3210b_eval_lcd.h , stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_34 : stm3210e_eval_lcd.h , stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_36 : stm3210b_eval_lcd.h , stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_37 : stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h , stm32100b_eval_lcd.h
  • LCD_REG_4 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_40 : stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm32l152_eval_lcd.h , stm3210e_eval_lcd.h , stm32100b_eval_lcd.h
  • LCD_REG_41 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_43 : stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm32l152_eval_lcd.h , stm32100b_eval_lcd.h , stm3210e_eval_lcd.h
  • LCD_REG_45 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h , stm3210b_eval_lcd.h
  • LCD_REG_48 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm32l152_eval_lcd.h , stm3210e_eval_lcd.h
  • LCD_REG_49 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h , stm3210b_eval_lcd.h
  • LCD_REG_5 : stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h , stm32100b_eval_lcd.h
  • LCD_REG_50 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h , stm3210b_eval_lcd.h
  • LCD_REG_51 : stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm32l152_eval_lcd.h , stm3210e_eval_lcd.h , stm32100b_eval_lcd.h
  • LCD_REG_52 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_53 : stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm32l152_eval_lcd.h , stm32100b_eval_lcd.h , stm3210e_eval_lcd.h
  • LCD_REG_54 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h , stm3210b_eval_lcd.h
  • LCD_REG_55 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm32l152_eval_lcd.h , stm3210e_eval_lcd.h
  • LCD_REG_56 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h , stm3210b_eval_lcd.h
  • LCD_REG_57 : stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h , stm32100b_eval_lcd.h
  • LCD_REG_58 : stm32100e_eval_lcd.h , stm3210e_eval_lcd.h
  • LCD_REG_59 : stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm32l152_eval_lcd.h , stm32100b_eval_lcd.h , stm3210e_eval_lcd.h
  • LCD_REG_6 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h , stm3210b_eval_lcd.h
  • LCD_REG_60 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm32l152_eval_lcd.h , stm3210e_eval_lcd.h
  • LCD_REG_61 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h , stm3210b_eval_lcd.h
  • LCD_REG_62 : stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h , stm32100b_eval_lcd.h
  • LCD_REG_63 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h , stm3210b_eval_lcd.h
  • LCD_REG_64 : stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm32l152_eval_lcd.h , stm3210e_eval_lcd.h , stm32100b_eval_lcd.h
  • LCD_REG_65 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_66 : stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm32l152_eval_lcd.h , stm32100b_eval_lcd.h , stm3210e_eval_lcd.h
  • LCD_REG_67 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h , stm3210b_eval_lcd.h
  • LCD_REG_68 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm32l152_eval_lcd.h , stm3210e_eval_lcd.h
  • LCD_REG_69 : stm3210b_eval_lcd.h , stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_7 : stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h , stm32100b_eval_lcd.h
  • LCD_REG_70 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h , stm3210b_eval_lcd.h
  • LCD_REG_71 : stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm32l152_eval_lcd.h , stm3210e_eval_lcd.h , stm32100b_eval_lcd.h
  • LCD_REG_72 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_73 : stm32l152_eval_lcd.h , stm3210e_eval_lcd.h , stm32100e_eval_lcd.h , stm3210c_eval_lcd.h , stm3210b_eval_lcd.h , stm32100b_eval_lcd.h
  • LCD_REG_74 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm32l152_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm3210b_eval_lcd.h
  • LCD_REG_75 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm32l152_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h
  • LCD_REG_76 : stm32l152_eval_lcd.h , stm3210b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210c_eval_lcd.h , stm32100b_eval_lcd.h , stm3210e_eval_lcd.h
  • LCD_REG_77 : stm3210e_eval_lcd.h , stm3210c_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm32l152_eval_lcd.h , stm32100b_eval_lcd.h
  • LCD_REG_78 : stm32100e_eval_lcd.h , stm3210c_eval_lcd.h , stm32l152_eval_lcd.h , stm3210e_eval_lcd.h , stm32100b_eval_lcd.h , stm3210b_eval_lcd.h
  • LCD_REG_79 : stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm32l152_eval_lcd.h , stm3210e_eval_lcd.h
  • LCD_REG_8 : stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm32100e_eval_lcd.h , stm32100b_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_80 : stm3210e_eval_lcd.h , stm32100e_eval_lcd.h , stm3210c_eval_lcd.h , stm32l152_eval_lcd.h , stm3210b_eval_lcd.h , stm32100b_eval_lcd.h
  • LCD_REG_81 : stm32100e_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h , stm32100b_eval_lcd.h , stm3210b_eval_lcd.h
  • LCD_REG_82 : stm32100b_eval_lcd.h , stm3210c_eval_lcd.h , stm32100e_eval_lcd.h , stm32l152_eval_lcd.h , stm3210b_eval_lcd.h , stm3210e_eval_lcd.h
  • LCD_REG_83 : stm3210e_eval_lcd.h , stm32l152_eval_lcd.h , stm3210b_eval_lcd.h , stm32100e_eval_lcd.h , stm32100b_eval_lcd.h , stm3210c_eval_lcd.h
  • LCD_REG_9 : stm3210e_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm32l152_eval_lcd.h , stm32100b_eval_lcd.h
  • LCD_REG_96 : stm3210c_eval_lcd.h , stm32l152_eval_lcd.h , stm3210e_eval_lcd.h , stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h
  • LCD_REG_97 : stm3210c_eval_lcd.h , stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm32l152_eval_lcd.h , stm3210b_eval_lcd.h , stm3210e_eval_lcd.h
  • LCD_RS_GPIO_CLK : stm3210b_eval_lcd.h , stm32100b_eval_lcd.h
  • LCD_RS_GPIO_PORT : stm32100b_eval_lcd.h , stm3210b_eval_lcd.h
  • LCD_RS_PIN : stm3210b_eval_lcd.h , stm32100b_eval_lcd.h
  • LCD_RSNWR_GPIO_CLK : stm32_eval.h
  • LCD_SetBackColor() : stm32l152_eval_lcd.c , stm32100b_eval_lcd.c , stm32100e_eval_lcd.c , stm3210b_eval_lcd.c , stm3210e_eval_lcd.c , stm3210e_eval_lcd.h , stm32100b_eval_lcd.h , stm3210c_eval_lcd.c , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm32l152_eval_lcd.h , stm3210c_eval_lcd.h
  • LCD_SetColors() : stm32100b_eval_lcd.c , stm3210b_eval_lcd.c , stm3210c_eval_lcd.c , stm3210e_eval_lcd.c , stm32100b_eval_lcd.h , stm3210b_eval_lcd.h , stm32100e_eval_lcd.c , stm32l152_eval_lcd.c , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h , stm3210c_eval_lcd.h , stm32100e_eval_lcd.h
  • LCD_SetCursor() : stm3210b_eval_lcd.h , stm3210c_eval_lcd.c , stm32100b_eval_lcd.c , stm32100b_eval_lcd.h , stm32100e_eval_lcd.c , stm3210b_eval_lcd.c , stm3210e_eval_lcd.c , stm32l152_eval_lcd.c , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h , stm3210c_eval_lcd.h , stm32100e_eval_lcd.h
  • LCD_SetDisplayWindow() : stm32100b_eval_lcd.c , stm3210b_eval_lcd.c , stm3210b_eval_lcd.h , stm3210c_eval_lcd.c , stm3210e_eval_lcd.c , stm3210e_eval_lcd.h , stm32100e_eval_lcd.c , stm32l152_eval_lcd.c , stm32100b_eval_lcd.h , stm32l152_eval_lcd.h , stm3210c_eval_lcd.h , stm32100e_eval_lcd.h
  • LCD_SetFont() : stm32l152_eval_lcd.c , stm32100b_eval_lcd.c , stm32100e_eval_lcd.c , stm3210b_eval_lcd.c , stm3210e_eval_lcd.c , stm3210e_eval_lcd.h , stm32100b_eval_lcd.h , stm3210b_eval_lcd.h , stm32l152_eval_lcd.h , stm3210c_eval_lcd.c , stm3210c_eval_lcd.h , stm32100e_eval_lcd.h
  • LCD_SetTextColor() : stm32100e_eval_lcd.c , stm32100b_eval_lcd.c , stm3210b_eval_lcd.c , stm3210c_eval_lcd.c , stm3210e_eval_lcd.c , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.c , stm32l152_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm32100b_eval_lcd.h
  • LCD_Setup() : stm3210b_eval_lcd.c , stm32100b_eval_lcd.h , stm32100b_eval_lcd.c , stm3210c_eval_lcd.c , stm32l152_eval_lcd.c , stm32l152_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h
  • LCD_SPFD5408 : stm32100b_eval_lcd.c , stm32l152_eval_lcd.c , stm3210b_eval_lcd.c
  • LCD_SPI : stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm32l152_eval_lcd.h , stm32100b_eval_lcd.h
  • LCD_SPI_CLK : stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm32l152_eval_lcd.h , stm32100b_eval_lcd.h
  • LCD_SPI_GPIO_CLK : stm32_eval.h
  • LCD_SPI_GPIO_PORT : stm32_eval.h
  • LCD_SPI_MISO_AF : stm32l152_eval_lcd.h
  • LCD_SPI_MISO_GPIO_CLK : stm32100b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210b_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_SPI_MISO_GPIO_PORT : stm32100b_eval_lcd.h , stm3210c_eval_lcd.h , stm32l152_eval_lcd.h , stm3210b_eval_lcd.h
  • LCD_SPI_MISO_PIN : stm3210c_eval_lcd.h , stm32l152_eval_lcd.h , stm32100b_eval_lcd.h , stm3210b_eval_lcd.h
  • LCD_SPI_MISO_SOURCE : stm32l152_eval_lcd.h
  • LCD_SPI_MOSI_AF : stm32l152_eval_lcd.h
  • LCD_SPI_MOSI_GPIO_CLK : stm32100b_eval_lcd.h , stm3210c_eval_lcd.h , stm32l152_eval_lcd.h , stm3210b_eval_lcd.h
  • LCD_SPI_MOSI_GPIO_PORT : stm32100b_eval_lcd.h , stm3210c_eval_lcd.h , stm32l152_eval_lcd.h , stm3210b_eval_lcd.h
  • LCD_SPI_MOSI_PIN : stm32100b_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_SPI_MOSI_SOURCE : stm32l152_eval_lcd.h
  • LCD_SPI_SCK_AF : stm32l152_eval_lcd.h
  • LCD_SPI_SCK_GPIO_CLK : stm32100b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210b_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_SPI_SCK_GPIO_PORT : stm32100b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210b_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_SPI_SCK_PIN : stm32100b_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_SPI_SCK_SOURCE : stm32l152_eval_lcd.h
  • LCD_SPIConfig() : stm32100b_eval_lcd.h , stm3210b_eval_lcd.c , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm32l152_eval_lcd.h , stm3210c_eval_lcd.c , stm32l152_eval_lcd.c , stm32100b_eval_lcd.c
  • LCD_WindowModeDisable() : stm32l152_eval_lcd.h , stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm32l152_eval_lcd.c , stm3210b_eval_lcd.c , stm3210e_eval_lcd.h , stm3210b_eval_lcd.h , stm32100b_eval_lcd.c , stm32100e_eval_lcd.c , stm3210e_eval_lcd.c , stm3210c_eval_lcd.h , stm3210c_eval_lcd.c
  • LCD_WRITE_REG : stm3210c_eval_lcd.c , stm3210b_eval_lcd.c , stm32100b_eval_lcd.c , stm32l152_eval_lcd.c
  • LCD_WriteBMP() : stm32100e_eval_lcd.h , stm3210e_eval_lcd.c , stm3210e_eval_lcd.h , stm32100e_eval_lcd.c
  • LCD_WriteRAM() : stm32100b_eval_lcd.h , stm3210e_eval_lcd.h , stm3210b_eval_lcd.h , stm32l152_eval_lcd.c , stm32100e_eval_lcd.c , stm32100b_eval_lcd.c , stm3210c_eval_lcd.c , stm3210b_eval_lcd.c , stm32100e_eval_lcd.h , stm3210e_eval_lcd.c , stm3210c_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_WriteRAM_Prepare() : stm32l152_eval_lcd.h , stm3210e_eval_lcd.h , stm3210c_eval_lcd.c , stm32100b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.c , stm32l152_eval_lcd.c , stm3210b_eval_lcd.c , stm3210b_eval_lcd.h , stm32100b_eval_lcd.c , stm32100e_eval_lcd.h , stm32100e_eval_lcd.c
  • LCD_WriteRAMWord() : stm32l152_eval_lcd.c , stm3210c_eval_lcd.c , stm3210b_eval_lcd.h , stm32100b_eval_lcd.h , stm3210c_eval_lcd.h , stm32l152_eval_lcd.h , stm32100b_eval_lcd.c , stm3210b_eval_lcd.c
  • LCD_WriteReg() : stm32l152_eval_lcd.c , stm32100b_eval_lcd.c , stm3210e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.c , stm32100b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210b_eval_lcd.c , stm3210e_eval_lcd.c , stm32100e_eval_lcd.h , stm32l152_eval_lcd.h , stm32100e_eval_lcd.c
  • LCD_WriteRegHX8312() : stm32100b_eval_lcd.c , stm3210b_eval_lcd.c
  • LCD_WriteRegILI9320() : stm32100b_eval_lcd.c , stm3210b_eval_lcd.c
  • LCD_WriteRegIndex() : stm32l152_eval_lcd.c , stm3210b_eval_lcd.h , stm3210c_eval_lcd.c , stm32100b_eval_lcd.h , stm32100b_eval_lcd.c , stm3210b_eval_lcd.c , stm3210c_eval_lcd.h , stm32l152_eval_lcd.h
  • LCDType : stm32l152_eval_lcd.c , stm32100b_eval_lcd.c , stm3210b_eval_lcd.c
  • LED1 : stm32_eval.h
  • LED1_GPIO_CLK : stm3210e_eval.h , stm3210c_eval.h , stm3210b_eval.h , stm32100b_eval.h , stm32l152_eval.h , stm32100e_eval.h
  • LED1_GPIO_PORT : stm32100e_eval.h , stm3210b_eval.h , stm3210e_eval.h , stm32100b_eval.h , stm3210c_eval.h , stm32l152_eval.h
  • LED1_PIN : stm3210b_eval.h , stm32100b_eval.h , stm3210e_eval.h , stm3210c_eval.h , stm32100e_eval.h , stm32l152_eval.h
  • LED2 : stm32_eval.h
  • LED2_GPIO_CLK : stm3210e_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm32100b_eval.h , stm32l152_eval.h , stm3210c_eval.h
  • LED2_GPIO_PORT : stm3210b_eval.h , stm3210e_eval.h , stm32100b_eval.h , stm3210c_eval.h , stm32l152_eval.h , stm32100e_eval.h
  • LED2_PIN : stm3210c_eval.h , stm32l152_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210e_eval.h , stm32100b_eval.h
  • LED3 : stm32_eval.h
  • LED3_GPIO_CLK : stm3210c_eval.h , stm3210b_eval.h , stm32100b_eval.h , stm32l152_eval.h , stm3210e_eval.h , stm32100e_eval.h
  • LED3_GPIO_PORT : stm32100e_eval.h , stm32l152_eval.h , stm32100b_eval.h , stm3210e_eval.h , stm3210b_eval.h , stm3210c_eval.h
  • LED3_PIN : stm32100e_eval.h , stm3210b_eval.h , stm32l152_eval.h , stm3210c_eval.h , stm3210e_eval.h , stm32100b_eval.h
  • LED4 : stm32_eval.h
  • LED4_GPIO_CLK : stm3210b_eval.h , stm3210c_eval.h , stm32l152_eval.h , stm3210e_eval.h , stm32100b_eval.h , stm32100e_eval.h
  • LED4_GPIO_PORT : stm3210b_eval.h , stm32l152_eval.h , stm32100b_eval.h , stm3210c_eval.h , stm32100e_eval.h , stm3210e_eval.h
  • LED4_PIN : stm32l152_eval.h , stm3210e_eval.h , stm32100b_eval.h , stm3210b_eval.h , stm3210c_eval.h , stm32100e_eval.h
  • LED_Display() : STM32F10x_StdPeriph_Examples/CAN/DualCAN/main.c , STM32F10x_StdPeriph_Examples/CAN/Networking/main.c
  • Led_TypeDef : stm32_eval.h
  • LEDn : stm3210e_eval.h , stm32100b_eval.h , stm3210c_eval.h , stm32l152_eval.h , stm3210b_eval.h , stm32100e_eval.h
  • LEFT_BUTTON_EXTI_IRQn : stm32100e_eval.h , stm3210b_eval.h , stm3210e_eval.h , stm32l152_eval.h , stm32100b_eval.h
  • LEFT_BUTTON_EXTI_LINE : stm32100e_eval.h , stm32l152_eval.h , stm3210b_eval.h , stm3210e_eval.h , stm32100b_eval.h
  • LEFT_BUTTON_EXTI_PIN_SOURCE : stm3210b_eval.h , stm32100e_eval.h , stm32100b_eval.h , stm32l152_eval.h , stm3210e_eval.h
  • LEFT_BUTTON_EXTI_PORT_SOURCE : stm3210b_eval.h , stm32100e_eval.h , stm3210e_eval.h , stm32100b_eval.h , stm32l152_eval.h
  • LEFT_BUTTON_GPIO_CLK : stm32100b_eval.h , stm3210e_eval.h , stm3210b_eval.h , stm32l152_eval.h , stm32100e_eval.h
  • LEFT_BUTTON_GPIO_PORT : stm32100e_eval.h , stm32l152_eval.h , stm3210e_eval.h , stm3210b_eval.h , stm32100b_eval.h
  • LEFT_BUTTON_PIN : stm32100b_eval.h , stm32l152_eval.h , stm3210b_eval.h , stm32100e_eval.h , stm3210e_eval.h
  • LetterMap : stm32l152_eval_glass_lcd.c
  • LINE : fonts.h
  • Line0 : stm32_eval.h
  • Line1 : stm32_eval.h
  • Line2 : stm32_eval.h
  • Line3 : stm32_eval.h
  • Line4 : stm32_eval.h
  • Line5 : stm32_eval.h
  • Line6 : stm32_eval.h
  • Line7 : stm32_eval.h
  • Line8 : stm32_eval.h
  • Line9 : stm32_eval.h
  • LM75_ADDR : stm32_eval_i2c_tsensor.h
  • LM75_DeInit() : stm32_eval_i2c_tsensor.h , stm32_eval_i2c_tsensor.c
  • LM75_DMA_CLK : stm3210b_eval.h , stm32100b_eval.h , stm32l152_eval.h , stm32100e_eval.h , stm3210e_eval.h
  • LM75_DMA_Config() : stm32_eval_i2c_tsensor.c
  • LM75_DMA_RX : stm32_eval_i2c_tsensor.h
  • LM75_DMA_RX_CHANNEL : stm3210b_eval.h , stm3210e_eval.h , stm32100b_eval.h , stm32100e_eval.h , stm32l152_eval.h
  • LM75_DMA_RX_TCFLAG : stm3210e_eval.h , stm32100e_eval.h , stm32100b_eval.h , stm3210b_eval.h , stm32l152_eval.h
  • LM75_DMA_TX : stm32_eval_i2c_tsensor.h
  • LM75_DMA_TX_CHANNEL : stm3210e_eval.h , stm32l152_eval.h , stm32100b_eval.h , stm3210b_eval.h , stm32100e_eval.h
  • LM75_DMA_TX_TCFLAG : stm32100b_eval.h , stm32100e_eval.h , stm3210e_eval.h , stm32l152_eval.h , stm3210b_eval.h
  • LM75_DMADirection_TypeDef : stm32_eval_i2c_tsensor.h
  • LM75_FAIL : stm32_eval_i2c_tsensor.h
  • LM75_FLAG_TIMEOUT : stm32_eval_i2c_tsensor.h
  • LM75_GetStatus() : stm32_eval_i2c_tsensor.c , stm32_eval_i2c_tsensor.h
  • LM75_I2C : stm3210e_eval.h , stm32100e_eval.h , stm32100b_eval.h , stm32l152_eval.h , stm3210b_eval.h
  • LM75_I2C_CLK : stm3210e_eval.h , stm3210b_eval.h , stm32l152_eval.h , stm32100b_eval.h , stm32100e_eval.h
  • LM75_I2C_DR : stm32l152_eval.h , stm3210b_eval.h , stm32100b_eval.h , stm3210e_eval.h , stm32100e_eval.h
  • LM75_I2C_SCL_AF : stm32l152_eval.h
  • LM75_I2C_SCL_GPIO_CLK : stm32l152_eval.h , stm32100b_eval.h , stm32100e_eval.h , stm3210e_eval.h , stm3210b_eval.h
  • LM75_I2C_SCL_GPIO_PORT : stm32100e_eval.h , stm32l152_eval.h , stm3210b_eval.h , stm3210e_eval.h , stm32100b_eval.h
  • LM75_I2C_SCL_PIN : stm3210e_eval.h , stm32100b_eval.h , stm3210b_eval.h , stm32l152_eval.h , stm32100e_eval.h
  • LM75_I2C_SCL_SOURCE : stm32l152_eval.h
  • LM75_I2C_SDA_AF : stm32l152_eval.h
  • LM75_I2C_SDA_GPIO_CLK : stm32l152_eval.h , stm32100b_eval.h , stm32100e_eval.h , stm3210e_eval.h , stm3210b_eval.h
  • LM75_I2C_SDA_GPIO_PORT : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm32l152_eval.h , stm3210e_eval.h
  • LM75_I2C_SDA_PIN : stm32l152_eval.h , stm32100b_eval.h , stm3210e_eval.h , stm3210b_eval.h , stm32100e_eval.h
  • LM75_I2C_SDA_SOURCE : stm32l152_eval.h
  • LM75_I2C_SMBUSALERT_AF : stm32l152_eval.h
  • LM75_I2C_SMBUSALERT_GPIO_CLK : stm3210e_eval.h , stm3210b_eval.h , stm32l152_eval.h , stm32100e_eval.h , stm32100b_eval.h
  • LM75_I2C_SMBUSALERT_GPIO_PORT : stm3210e_eval.h , stm32100b_eval.h , stm32100e_eval.h , stm32l152_eval.h , stm3210b_eval.h
  • LM75_I2C_SMBUSALERT_PIN : stm32l152_eval.h , stm3210b_eval.h , stm32100b_eval.h , stm32100e_eval.h , stm3210e_eval.h
  • LM75_I2C_SMBUSALERT_SOURCE : stm32l152_eval.h
  • LM75_I2C_SPEED : stm32_eval_i2c_tsensor.h
  • LM75_Init() : stm32_eval_i2c_tsensor.h , stm32_eval_i2c_tsensor.c
  • LM75_LONG_TIMEOUT : stm32_eval_i2c_tsensor.h
  • LM75_LowLevel_DeInit() : stm32100b_eval.h , stm3210b_eval.c , stm3210b_eval.h , stm32l152_eval.c , stm32100b_eval.c , stm3210e_eval.c , stm32100e_eval.h , stm3210e_eval.h , stm32l152_eval.h , stm32100e_eval.c
  • LM75_LowLevel_Init() : stm32l152_eval.c , stm32100b_eval.h , stm32100e_eval.h , stm32l152_eval.h , stm3210e_eval.c , stm3210b_eval.c , stm32100e_eval.c , stm32100b_eval.c , stm3210b_eval.h , stm3210e_eval.h
  • LM75_OK : stm32_eval_i2c_tsensor.h
  • LM75_ReadConfReg() : stm32_eval_i2c_tsensor.h , stm32_eval_i2c_tsensor.c
  • LM75_ReadReg() : stm32_eval_i2c_tsensor.c , stm32_eval_i2c_tsensor.h
  • LM75_ReadTemp() : stm32_eval_i2c_tsensor.h , stm32_eval_i2c_tsensor.c
  • LM75_REG_CONF : stm32_eval_i2c_tsensor.h
  • LM75_REG_TEMP : stm32_eval_i2c_tsensor.h
  • LM75_REG_THYS : stm32_eval_i2c_tsensor.h
  • LM75_REG_TOS : stm32_eval_i2c_tsensor.h
  • LM75_SD_RESET : stm32_eval_i2c_tsensor.c
  • LM75_SD_SET : stm32_eval_i2c_tsensor.c
  • LM75_ShutDown() : stm32_eval_i2c_tsensor.h , stm32_eval_i2c_tsensor.c
  • LM75_Status_TypDef : stm32_eval_i2c_tsensor.h
  • LM75_Timeout : stm32_eval_i2c_tsensor.c
  • LM75_TIMEOUT_UserCallback : stm32_eval_i2c_tsensor.h
  • LM75_WriteConfReg() : stm32_eval_i2c_tsensor.h , stm32_eval_i2c_tsensor.c
  • LM75_WriteReg() : stm32_eval_i2c_tsensor.c , stm32_eval_i2c_tsensor.h
  • LogicalAddressAllocation() : stm32100e_eval_cec.c , stm32100b_eval_cec.c
  • LowPowerMode : STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/main.c
  • LSB_MASK : stm32f10x_gpio.c
  • LSI_TIM_MEASURE : STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/main.c
  • LsiFreq : STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/main.c , STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/main.c
  • LSION_BitNumber : stm32f10x_rcc.c


STM32F10x Standard Peripherals Firmware Library: Globals

  • File List
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  • f
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- m -

  • Magenta : stm32_eval.h
  • main() : STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c , STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/main.c , STM32F10x_StdPeriph_Examples/BKP/Backup_Data/main.c , STM32F10x_StdPeriph_Examples/CortexM3/MPU/main.c , STM32F10x_StdPeriph_Examples/FSMC/NOR/main.c , STM32F10x_StdPeriph_Examples/TIM/6Steps/main.c , STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/main.c , STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/main.c , STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/main.c , STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/main.c , STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/main.c , STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/main.c , STM32F10x_StdPeriph_Examples/TIM/DMA/main.c , STM32F10x_StdPeriph_Examples/TIM/DMABurst/main.c , STM32F10x_StdPeriph_Examples/FSMC/OneNAND/main.c , STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/main.c , STM32F10x_StdPeriph_Examples/TIM/InputCapture/main.c , STM32F10x_StdPeriph_Examples/BKP/Tamper/main.c , STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/main.c , STM32F10x_StdPeriph_Examples/FSMC/SRAM/main.c , STM32F10x_StdPeriph_Examples/TIM/OCActive/main.c , STM32F10x_StdPeriph_Examples/TIM/OCInactive/main.c , STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/main.c , STM32F10x_StdPeriph_Examples/TIM/OCToggle/main.c , STM32F10x_StdPeriph_Examples/TIM/OnePulse/main.c , STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/main.c , STM32F10x_StdPeriph_Examples/GPIO/IOToggle/main.c , STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/main.c , STM32F10x_StdPeriph_Examples/TIM/PWM_Input/main.c , STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/main.c , STM32F10x_StdPeriph_Examples/TIM/PWM_Output/main.c , STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/main.c , STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/main.c , STM32F10x_StdPeriph_Examples/CAN/DualCAN/main.c , STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/main.c , STM32F10x_StdPeriph_Examples/I2C/EEPROM/main.c , STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/main.c , STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/main.c , STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/main.c , STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/main.c , STM32F10x_StdPeriph_Examples/TIM/TimeBase/main.c , STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/main.c , STM32F10x_StdPeriph_Examples/I2C/IOExpander/main.c , STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/main.c , STM32F10x_StdPeriph_Examples/USART/DMA_Polling/main.c , STM32F10x_StdPeriph_Examples/I2S/Interrupt/main.c , STM32F10x_StdPeriph_Examples/USART/HalfDuplex/main.c , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/main.c , STM32F10x_StdPeriph_Examples/CAN/LoopBack/main.c , STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/main.c , STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/main.c , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/main.c , STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c , STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/main.c , STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/main.c , STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/main.c , STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/main.c , STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/main.c , STM32F10x_StdPeriph_Examples/USART/MultiProcessor/main.c , STM32F10x_StdPeriph_Examples/USART/Polling/main.c , STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/main.c , STM32F10x_StdPeriph_Examples/USART/Printf/main.c , STM32F10x_StdPeriph_Examples/USART/Smartcard/main.c , STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/main.c , STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/main.c , STM32F10x_StdPeriph_Examples/CAN/Networking/main.c , STM32F10x_StdPeriph_Examples/DMA/FSMC/main.c , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/main.c , STM32F10x_StdPeriph_Examples/USART/Synchronous/main.c , STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/main.c , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/main.c , STM32F10x_StdPeriph_Template/main.c , STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/main.c , STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/main.c , STM32F10x_StdPeriph_Examples/PWR/PVD/main.c , STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/main.c , STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/main.c , STM32F10x_StdPeriph_Examples/PWR/STANDBY/main.c , STM32F10x_StdPeriph_Examples/PWR/STOP/main.c , STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/main.c , STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/main.c , STM32F10x_StdPeriph_Examples/RTC/Calendar/main.c , STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/main.c , STM32F10x_StdPeriph_Examples/CortexM3/BitBand/main.c , STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/main.c , STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/main.c , STM32F10x_StdPeriph_Examples/SDIO/uSDCard/main.c , STM32F10x_StdPeriph_Examples/FLASH/Program/main.c , STM32F10x_StdPeriph_Examples/SPI/CRC/main.c , STM32F10x_StdPeriph_Examples/SPI/DMA/main.c , STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/main.c , STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/main.c , STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/main.c , STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/main.c , STM32F10x_StdPeriph_Examples/FSMC/NAND/main.c , STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/main.c , STM32F10x_StdPeriph_Examples/SysTick/TimeBase/main.c
  • MAPR_MII_RMII_SEL_BB : stm32f10x_gpio.c
  • MAPR_OFFSET : stm32f10x_gpio.c
  • mask : stm32l152_eval_glass_lcd.c
  • MAX_POLY_CORNERS : stm32100b_eval_lcd.c , stm32100e_eval_lcd.c , stm3210b_eval_lcd.c , stm3210c_eval_lcd.c , stm3210e_eval_lcd.c , stm32l152_eval_lcd.c
  • MCR_DBF : stm32f10x_can.c
  • MemManage_Handler() : STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SPI/DMA/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/DMA/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SPI/CRC/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/CRC/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SDIO/uSDCard/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/OnePulse/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/RTC/Calendar/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/PWR/STANDBY/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/PWR/PVD/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/PWR/PVD/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/PWM_Input/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/PWM_Input/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2C/IOExpander/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2C/IOExpander/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2C/EEPROM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/GPIO/IOToggle/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/SRAM/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/SRAM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CortexM3/BitBand/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/OneNAND/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CortexM3/BitBand/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/NOR/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/NAND/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FLASH/Program/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CortexM3/MPU/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CortexM3/MPU/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/DMA_Polling/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Synchronous/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Polling/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/MultiProcessor/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/MultiProcessor/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/FSMC/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/FSMC/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/BKP/Tamper/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/BKP/Tamper/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/BKP/Backup_Data/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/BKP/Backup_Data/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SDIO/uSDCard/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/6Steps/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/PWR/STANDBY/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/PWM_Output/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/HalfDuplex/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2C/EEPROM/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/GPIO/IOToggle/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/OneNAND/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Printf/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/NOR/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FLASH/Program/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/stm32f10x_it.h , STM32F10x_StdPeriph_Template/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/stm32f10x_it.c , STM32F10x_StdPeriph_Template/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Synchronous/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Printf/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/NAND/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Polling/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/DMA_Polling/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/HalfDuplex/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/DMA/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/DMABurst/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/OCActive/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/OCActive/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/OCInactive/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/RTC/Calendar/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/6Steps/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/OnePulse/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/PWM_Output/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SysTick/TimeBase/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SysTick/TimeBase/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/OCInactive/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/DMABurst/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/DMA/stm32f10x_it.c
  • MemoryManagement_IRQn : stm32f10x.h
  • MemoryProgramStatus : STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/main.c , STM32F10x_StdPeriph_Examples/FLASH/Program/main.c
  • MEMS_INT1_PIN : stm3210c_eval_ioe.h
  • MEMS_INT2_PIN : stm3210c_eval_ioe.h
  • MESSAGE1 : STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/main.c
  • MESSAGE10 : STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/main.c
  • MESSAGE11 : STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/main.c
  • MESSAGE12 : STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/main.c
  • MESSAGE2 : STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/main.c , STM32F10x_StdPeriph_Examples/I2C/IOExpander/main.c
  • MESSAGE3 : STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/main.c , STM32F10x_StdPeriph_Examples/I2C/IOExpander/main.c
  • MESSAGE5 : STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/main.c
  • MESSAGE6 : STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/main.c
  • MESSAGE7 : STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/main.c
  • MESSAGE8 : STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/main.c
  • MESSAGE9 : STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/main.c
  • MII_INT_PIN : stm3210c_eval_ioe.h
  • MII_RMII_SEL_BitNumber : stm32f10x_gpio.c
  • Mode_EXTI : stm32_eval.h
  • Mode_GPIO : stm32_eval.h
  • MODIFY_REG : stm32f10x.h
  • MPU_SETUP() : STM32F10x_StdPeriph_Examples/CortexM3/MPU/main.c
  • MSPValue : STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/main.c
  • MULTI_BUFFER_SIZE : STM32F10x_StdPeriph_Examples/SDIO/uSDCard/main.c
  • MY_DEVICE_ADDRESS : STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_conf.h
  • MyKey : STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/main.c
  • MyLogicalAddress : stm32100e_eval_cec.c , stm32100b_eval_cec.c
  • MyPhysicalAddress : stm32100e_eval_cec.c , stm32100b_eval_cec.c


STM32F10x Standard Peripherals Firmware Library: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- n -

  • NAND_AddressIncrement() : stm3210e_eval_fsmc_nand.c , stm3210e_eval_fsmc_nand.h
  • NAND_BLOCK_SIZE : stm3210e_eval_fsmc_nand.h
  • NAND_BUSY : stm3210e_eval_fsmc_nand.h
  • NAND_CMD_AREA_A : stm3210e_eval_fsmc_nand.h
  • NAND_CMD_AREA_B : stm3210e_eval_fsmc_nand.h
  • NAND_CMD_AREA_C : stm3210e_eval_fsmc_nand.h
  • NAND_CMD_ERASE0 : stm3210e_eval_fsmc_nand.h
  • NAND_CMD_ERASE1 : stm3210e_eval_fsmc_nand.h
  • NAND_CMD_LOCK_STATUS : stm3210e_eval_fsmc_nand.h
  • NAND_CMD_READID : stm3210e_eval_fsmc_nand.h
  • NAND_CMD_RESET : stm3210e_eval_fsmc_nand.h
  • NAND_CMD_STATUS : stm3210e_eval_fsmc_nand.h
  • NAND_CMD_WRITE0 : stm3210e_eval_fsmc_nand.h
  • NAND_CMD_WRITE_TRUE1 : stm3210e_eval_fsmc_nand.h
  • NAND_EraseBlock() : stm3210e_eval_fsmc_nand.c , stm3210e_eval_fsmc_nand.h
  • NAND_ERROR : stm3210e_eval_fsmc_nand.h
  • NAND_GetStatus() : stm3210e_eval_fsmc_nand.c , stm3210e_eval_fsmc_nand.h
  • NAND_ID : STM32F10x_StdPeriph_Examples/FSMC/NAND/main.c
  • NAND_Init() : stm3210e_eval_fsmc_nand.c , stm3210e_eval_fsmc_nand.h
  • NAND_INVALID_ADDRESS : stm3210e_eval_fsmc_nand.h
  • NAND_MAX_ZONE : stm3210e_eval_fsmc_nand.h
  • NAND_PAGE_SIZE : stm3210e_eval_fsmc_nand.h
  • NAND_ReadID() : stm3210e_eval_fsmc_nand.c , stm3210e_eval_fsmc_nand.h
  • NAND_ReadSmallPage() : stm3210e_eval_fsmc_nand.c , stm3210e_eval_fsmc_nand.h
  • NAND_ReadSpareArea() : stm3210e_eval_fsmc_nand.h , stm3210e_eval_fsmc_nand.c
  • NAND_ReadStatus() : stm3210e_eval_fsmc_nand.c , stm3210e_eval_fsmc_nand.h
  • NAND_READY : stm3210e_eval_fsmc_nand.h
  • NAND_Reset() : stm3210e_eval_fsmc_nand.c , stm3210e_eval_fsmc_nand.h
  • NAND_SPARE_AREA_SIZE : stm3210e_eval_fsmc_nand.h
  • NAND_ST_DeviceID : STM32F10x_StdPeriph_Examples/FSMC/NAND/main.c
  • NAND_ST_MakerID : STM32F10x_StdPeriph_Examples/FSMC/NAND/main.c
  • NAND_TIMEOUT_ERROR : stm3210e_eval_fsmc_nand.h
  • NAND_VALID_ADDRESS : stm3210e_eval_fsmc_nand.h
  • NAND_WriteSmallPage() : stm3210e_eval_fsmc_nand.c , stm3210e_eval_fsmc_nand.h
  • NAND_WriteSpareArea() : stm3210e_eval_fsmc_nand.c , stm3210e_eval_fsmc_nand.h
  • NAND_ZONE_SIZE : stm3210e_eval_fsmc_nand.h
  • NbrOfDataToRead : STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/main.c , STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.c
  • NbrOfDataToRead1 : STM32F10x_StdPeriph_Examples/USART/HalfDuplex/main.c , STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c , STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Synchronous/main.c
  • NbrOfDataToRead2 : STM32F10x_StdPeriph_Examples/USART/HalfDuplex/main.c , STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c , STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Synchronous/main.c
  • NbrOfDataToTransfer : STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/main.c , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.c
  • NbrOfDataToTransfer1 : STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c , STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.c
  • NbrOfDataToTransfer2 : STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c
  • NbrOfPage : STM32F10x_StdPeriph_Examples/FLASH/Program/main.c , STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/main.c
  • NIEN_BitNumber : stm32f10x_sdio.c
  • NMI_Handler() : STM32F10x_StdPeriph_Examples/FSMC/NOR/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Synchronous/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Synchronous/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/NOR/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/stm32f10x_it.c , STM32F10x_StdPeriph_Template/stm32f10x_it.c , STM32F10x_StdPeriph_Template/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/OneNAND/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/OneNAND/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/SRAM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/SRAM/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/GPIO/IOToggle/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/GPIO/IOToggle/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2C/EEPROM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2C/EEPROM/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2C/IOExpander/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2C/IOExpander/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/BKP/Backup_Data/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/BKP/Backup_Data/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/BKP/Tamper/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/BKP/Tamper/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/PWR/PVD/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/PWR/PVD/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/PWR/STANDBY/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/PWR/STANDBY/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/RTC/Calendar/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/RTC/Calendar/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SDIO/uSDCard/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SDIO/uSDCard/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SPI/CRC/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SPI/CRC/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/DMA/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SPI/DMA/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CortexM3/BitBand/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CortexM3/BitBand/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SysTick/TimeBase/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SysTick/TimeBase/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CortexM3/MPU/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/6Steps/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/6Steps/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CortexM3/MPU/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/DMA/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/DMA/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/DMABurst/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/DMABurst/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/OCActive/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/OCActive/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/OCInactive/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/OCInactive/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/OnePulse/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/OnePulse/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/PWM_Input/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/PWM_Input/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/PWM_Output/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/PWM_Output/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/FSMC/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/FSMC/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/DMA_Polling/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/DMA_Polling/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/HalfDuplex/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/HalfDuplex/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FLASH/Program/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FLASH/Program/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/MultiProcessor/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/MultiProcessor/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Polling/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Polling/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/NAND/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Printf/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Printf/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/NAND/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_it.h
  • NonMaskableInt_IRQn : stm32f10x.h
  • NOR_EraseBlock() : stm3210e_eval_fsmc_nor.c , stm3210e_eval_fsmc_nor.h
  • NOR_EraseChip() : stm3210e_eval_fsmc_nor.c , stm3210e_eval_fsmc_nor.h
  • NOR_ERROR : stm3210e_eval_fsmc_nor.h
  • NOR_GetStatus() : stm3210e_eval_fsmc_nor.c , stm3210e_eval_fsmc_nor.h
  • NOR_ID : STM32F10x_StdPeriph_Examples/FSMC/NOR/main.c
  • NOR_Init() : stm3210e_eval_fsmc_nor.c , stm3210e_eval_fsmc_nor.h
  • NOR_ONGOING : stm3210e_eval_fsmc_nor.h
  • NOR_ProgramBuffer() : stm3210e_eval_fsmc_nor.c , stm3210e_eval_fsmc_nor.h
  • NOR_ReadBuffer() : stm3210e_eval_fsmc_nor.c , stm3210e_eval_fsmc_nor.h
  • NOR_ReadHalfWord() : stm3210e_eval_fsmc_nor.h , stm3210e_eval_fsmc_nor.c
  • NOR_ReadID() : stm3210e_eval_fsmc_nor.c , stm3210e_eval_fsmc_nor.h
  • NOR_Reset() : stm3210e_eval_fsmc_nor.h , stm3210e_eval_fsmc_nor.c
  • NOR_ReturnToReadMode() : stm3210e_eval_fsmc_nor.c , stm3210e_eval_fsmc_nor.h
  • NOR_Status : stm3210e_eval_fsmc_nor.h
  • NOR_SUCCESS : stm3210e_eval_fsmc_nor.h
  • NOR_TIMEOUT : stm3210e_eval_fsmc_nor.h
  • NOR_WRITE : stm3210e_eval_fsmc_nor.c
  • NOR_WriteBuffer() : stm3210e_eval_fsmc_nor.c , stm3210e_eval_fsmc_nor.h
  • NOR_WriteHalfWord() : stm3210e_eval_fsmc_nor.c , stm3210e_eval_fsmc_nor.h
  • NULL : stm32_eval_sdio_sd.c
  • NUMBER_OF_BLOCKS : STM32F10x_StdPeriph_Examples/SDIO/uSDCard/main.c
  • NumberMap : stm32l152_eval_glass_lcd.c
  • NumDataRead : STM32F10x_StdPeriph_Examples/I2C/EEPROM/main.c
  • NVIC_Config() : STM32F10x_StdPeriph_Examples/CAN/DualCAN/main.c , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/main.c , STM32F10x_StdPeriph_Examples/CAN/Networking/main.c
  • NVIC_Configuration() : STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c , STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/main.c , STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/main.c , STM32F10x_StdPeriph_Examples/BKP/Tamper/main.c , STM32F10x_StdPeriph_Examples/CAN/LoopBack/main.c , STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/main.c , STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/main.c , STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/main.c , STM32F10x_StdPeriph_Examples/I2S/Interrupt/main.c , STM32F10x_StdPeriph_Examples/PWR/STOP/main.c , STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/main.c , STM32F10x_StdPeriph_Examples/RTC/Calendar/main.c , STM32F10x_StdPeriph_Examples/SDIO/uSDCard/main.c , STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/main.c , STM32F10x_StdPeriph_Examples/TIM/6Steps/main.c , STM32F10x_StdPeriph_Examples/TIM/OCInactive/main.c , STM32F10x_StdPeriph_Examples/TIM/OCToggle/main.c , STM32F10x_StdPeriph_Examples/TIM/PWM_Input/main.c , STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/main.c , STM32F10x_StdPeriph_Examples/TIM/TimeBase/main.c , STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/main.c , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/main.c , STM32F10x_StdPeriph_Examples/USART/Smartcard/main.c , STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c , STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/main.c , STM32F10x_StdPeriph_Examples/TIM/InputCapture/main.c , STM32F10x_StdPeriph_Examples/PWR/PVD/main.c , STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/main.c
  • NVIC_DBG : stm32f10x_ip_dbg.c
  • NVIC_IABR_ACTIVE : stm32f10x.h
  • NVIC_IABR_ACTIVE_0 : stm32f10x.h
  • NVIC_IABR_ACTIVE_1 : stm32f10x.h
  • NVIC_IABR_ACTIVE_10 : stm32f10x.h
  • NVIC_IABR_ACTIVE_11 : stm32f10x.h
  • NVIC_IABR_ACTIVE_12 : stm32f10x.h
  • NVIC_IABR_ACTIVE_13 : stm32f10x.h
  • NVIC_IABR_ACTIVE_14 : stm32f10x.h
  • NVIC_IABR_ACTIVE_15 : stm32f10x.h
  • NVIC_IABR_ACTIVE_16 : stm32f10x.h
  • NVIC_IABR_ACTIVE_17 : stm32f10x.h
  • NVIC_IABR_ACTIVE_18 : stm32f10x.h
  • NVIC_IABR_ACTIVE_19 : stm32f10x.h
  • NVIC_IABR_ACTIVE_2 : stm32f10x.h
  • NVIC_IABR_ACTIVE_20 : stm32f10x.h
  • NVIC_IABR_ACTIVE_21 : stm32f10x.h
  • NVIC_IABR_ACTIVE_22 : stm32f10x.h
  • NVIC_IABR_ACTIVE_23 : stm32f10x.h
  • NVIC_IABR_ACTIVE_24 : stm32f10x.h
  • NVIC_IABR_ACTIVE_25 : stm32f10x.h
  • NVIC_IABR_ACTIVE_26 : stm32f10x.h
  • NVIC_IABR_ACTIVE_27 : stm32f10x.h
  • NVIC_IABR_ACTIVE_28 : stm32f10x.h
  • NVIC_IABR_ACTIVE_29 : stm32f10x.h
  • NVIC_IABR_ACTIVE_3 : stm32f10x.h
  • NVIC_IABR_ACTIVE_30 : stm32f10x.h
  • NVIC_IABR_ACTIVE_31 : stm32f10x.h
  • NVIC_IABR_ACTIVE_4 : stm32f10x.h
  • NVIC_IABR_ACTIVE_5 : stm32f10x.h
  • NVIC_IABR_ACTIVE_6 : stm32f10x.h
  • NVIC_IABR_ACTIVE_7 : stm32f10x.h
  • NVIC_IABR_ACTIVE_8 : stm32f10x.h
  • NVIC_IABR_ACTIVE_9 : stm32f10x.h
  • NVIC_ICER_CLRENA : stm32f10x.h
  • NVIC_ICER_CLRENA_0 : stm32f10x.h
  • NVIC_ICER_CLRENA_1 : stm32f10x.h
  • NVIC_ICER_CLRENA_10 : stm32f10x.h
  • NVIC_ICER_CLRENA_11 : stm32f10x.h
  • NVIC_ICER_CLRENA_12 : stm32f10x.h
  • NVIC_ICER_CLRENA_13 : stm32f10x.h
  • NVIC_ICER_CLRENA_14 : stm32f10x.h
  • NVIC_ICER_CLRENA_15 : stm32f10x.h
  • NVIC_ICER_CLRENA_16 : stm32f10x.h
  • NVIC_ICER_CLRENA_17 : stm32f10x.h
  • NVIC_ICER_CLRENA_18 : stm32f10x.h
  • NVIC_ICER_CLRENA_19 : stm32f10x.h
  • NVIC_ICER_CLRENA_2 : stm32f10x.h
  • NVIC_ICER_CLRENA_20 : stm32f10x.h
  • NVIC_ICER_CLRENA_21 : stm32f10x.h
  • NVIC_ICER_CLRENA_22 : stm32f10x.h
  • NVIC_ICER_CLRENA_23 : stm32f10x.h
  • NVIC_ICER_CLRENA_24 : stm32f10x.h
  • NVIC_ICER_CLRENA_25 : stm32f10x.h
  • NVIC_ICER_CLRENA_26 : stm32f10x.h
  • NVIC_ICER_CLRENA_27 : stm32f10x.h
  • NVIC_ICER_CLRENA_28 : stm32f10x.h
  • NVIC_ICER_CLRENA_29 : stm32f10x.h
  • NVIC_ICER_CLRENA_3 : stm32f10x.h
  • NVIC_ICER_CLRENA_30 : stm32f10x.h
  • NVIC_ICER_CLRENA_31 : stm32f10x.h
  • NVIC_ICER_CLRENA_4 : stm32f10x.h
  • NVIC_ICER_CLRENA_5 : stm32f10x.h
  • NVIC_ICER_CLRENA_6 : stm32f10x.h
  • NVIC_ICER_CLRENA_7 : stm32f10x.h
  • NVIC_ICER_CLRENA_8 : stm32f10x.h
  • NVIC_ICER_CLRENA_9 : stm32f10x.h
  • NVIC_ICPR_CLRPEND : stm32f10x.h
  • NVIC_ICPR_CLRPEND_0 : stm32f10x.h
  • NVIC_ICPR_CLRPEND_1 : stm32f10x.h
  • NVIC_ICPR_CLRPEND_10 : stm32f10x.h
  • NVIC_ICPR_CLRPEND_11 : stm32f10x.h
  • NVIC_ICPR_CLRPEND_12 : stm32f10x.h
  • NVIC_ICPR_CLRPEND_13 : stm32f10x.h
  • NVIC_ICPR_CLRPEND_14 : stm32f10x.h
  • NVIC_ICPR_CLRPEND_15 : stm32f10x.h
  • NVIC_ICPR_CLRPEND_16 : stm32f10x.h
  • NVIC_ICPR_CLRPEND_17 : stm32f10x.h
  • NVIC_ICPR_CLRPEND_18 : stm32f10x.h
  • NVIC_ICPR_CLRPEND_19 : stm32f10x.h
  • NVIC_ICPR_CLRPEND_2 : stm32f10x.h
  • NVIC_ICPR_CLRPEND_20 : stm32f10x.h
  • NVIC_ICPR_CLRPEND_21 : stm32f10x.h
  • NVIC_ICPR_CLRPEND_22 : stm32f10x.h
  • NVIC_ICPR_CLRPEND_23 : stm32f10x.h
  • NVIC_ICPR_CLRPEND_24 : stm32f10x.h
  • NVIC_ICPR_CLRPEND_25 : stm32f10x.h
  • NVIC_ICPR_CLRPEND_26 : stm32f10x.h
  • NVIC_ICPR_CLRPEND_27 : stm32f10x.h
  • NVIC_ICPR_CLRPEND_28 : stm32f10x.h
  • NVIC_ICPR_CLRPEND_29 : stm32f10x.h
  • NVIC_ICPR_CLRPEND_3 : stm32f10x.h
  • NVIC_ICPR_CLRPEND_30 : stm32f10x.h
  • NVIC_ICPR_CLRPEND_31 : stm32f10x.h
  • NVIC_ICPR_CLRPEND_4 : stm32f10x.h
  • NVIC_ICPR_CLRPEND_5 : stm32f10x.h
  • NVIC_ICPR_CLRPEND_6 : stm32f10x.h
  • NVIC_ICPR_CLRPEND_7 : stm32f10x.h
  • NVIC_ICPR_CLRPEND_8 : stm32f10x.h
  • NVIC_ICPR_CLRPEND_9 : stm32f10x.h
  • NVIC_Init() : misc.h , misc.c
  • NVIC_InitStructure : STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/main.c , STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/main.c
  • NVIC_IPR0_PRI_0 : stm32f10x.h
  • NVIC_IPR0_PRI_1 : stm32f10x.h
  • NVIC_IPR0_PRI_2 : stm32f10x.h
  • NVIC_IPR0_PRI_3 : stm32f10x.h
  • NVIC_IPR1_PRI_4 : stm32f10x.h
  • NVIC_IPR1_PRI_5 : stm32f10x.h
  • NVIC_IPR1_PRI_6 : stm32f10x.h
  • NVIC_IPR1_PRI_7 : stm32f10x.h
  • NVIC_IPR2_PRI_10 : stm32f10x.h
  • NVIC_IPR2_PRI_11 : stm32f10x.h
  • NVIC_IPR2_PRI_8 : stm32f10x.h
  • NVIC_IPR2_PRI_9 : stm32f10x.h
  • NVIC_IPR3_PRI_12 : stm32f10x.h
  • NVIC_IPR3_PRI_13 : stm32f10x.h
  • NVIC_IPR3_PRI_14 : stm32f10x.h
  • NVIC_IPR3_PRI_15 : stm32f10x.h
  • NVIC_IPR4_PRI_16 : stm32f10x.h
  • NVIC_IPR4_PRI_17 : stm32f10x.h
  • NVIC_IPR4_PRI_18 : stm32f10x.h
  • NVIC_IPR4_PRI_19 : stm32f10x.h
  • NVIC_IPR5_PRI_20 : stm32f10x.h
  • NVIC_IPR5_PRI_21 : stm32f10x.h
  • NVIC_IPR5_PRI_22 : stm32f10x.h
  • NVIC_IPR5_PRI_23 : stm32f10x.h
  • NVIC_IPR6_PRI_24 : stm32f10x.h
  • NVIC_IPR6_PRI_25 : stm32f10x.h
  • NVIC_IPR6_PRI_26 : stm32f10x.h
  • NVIC_IPR6_PRI_27 : stm32f10x.h
  • NVIC_IPR7_PRI_28 : stm32f10x.h
  • NVIC_IPR7_PRI_29 : stm32f10x.h
  • NVIC_IPR7_PRI_30 : stm32f10x.h
  • NVIC_IPR7_PRI_31 : stm32f10x.h
  • NVIC_ISER_SETENA : stm32f10x.h
  • NVIC_ISER_SETENA_0 : stm32f10x.h
  • NVIC_ISER_SETENA_1 : stm32f10x.h
  • NVIC_ISER_SETENA_10 : stm32f10x.h
  • NVIC_ISER_SETENA_11 : stm32f10x.h
  • NVIC_ISER_SETENA_12 : stm32f10x.h
  • NVIC_ISER_SETENA_13 : stm32f10x.h
  • NVIC_ISER_SETENA_14 : stm32f10x.h
  • NVIC_ISER_SETENA_15 : stm32f10x.h
  • NVIC_ISER_SETENA_16 : stm32f10x.h
  • NVIC_ISER_SETENA_17 : stm32f10x.h
  • NVIC_ISER_SETENA_18 : stm32f10x.h
  • NVIC_ISER_SETENA_19 : stm32f10x.h
  • NVIC_ISER_SETENA_2 : stm32f10x.h
  • NVIC_ISER_SETENA_20 : stm32f10x.h
  • NVIC_ISER_SETENA_21 : stm32f10x.h
  • NVIC_ISER_SETENA_22 : stm32f10x.h
  • NVIC_ISER_SETENA_23 : stm32f10x.h
  • NVIC_ISER_SETENA_24 : stm32f10x.h
  • NVIC_ISER_SETENA_25 : stm32f10x.h
  • NVIC_ISER_SETENA_26 : stm32f10x.h
  • NVIC_ISER_SETENA_27 : stm32f10x.h
  • NVIC_ISER_SETENA_28 : stm32f10x.h
  • NVIC_ISER_SETENA_29 : stm32f10x.h
  • NVIC_ISER_SETENA_3 : stm32f10x.h
  • NVIC_ISER_SETENA_30 : stm32f10x.h
  • NVIC_ISER_SETENA_31 : stm32f10x.h
  • NVIC_ISER_SETENA_4 : stm32f10x.h
  • NVIC_ISER_SETENA_5 : stm32f10x.h
  • NVIC_ISER_SETENA_6 : stm32f10x.h
  • NVIC_ISER_SETENA_7 : stm32f10x.h
  • NVIC_ISER_SETENA_8 : stm32f10x.h
  • NVIC_ISER_SETENA_9 : stm32f10x.h
  • NVIC_ISPR_SETPEND : stm32f10x.h
  • NVIC_ISPR_SETPEND_0 : stm32f10x.h
  • NVIC_ISPR_SETPEND_1 : stm32f10x.h
  • NVIC_ISPR_SETPEND_10 : stm32f10x.h
  • NVIC_ISPR_SETPEND_11 : stm32f10x.h
  • NVIC_ISPR_SETPEND_12 : stm32f10x.h
  • NVIC_ISPR_SETPEND_13 : stm32f10x.h
  • NVIC_ISPR_SETPEND_14 : stm32f10x.h
  • NVIC_ISPR_SETPEND_15 : stm32f10x.h
  • NVIC_ISPR_SETPEND_16 : stm32f10x.h
  • NVIC_ISPR_SETPEND_17 : stm32f10x.h
  • NVIC_ISPR_SETPEND_18 : stm32f10x.h
  • NVIC_ISPR_SETPEND_19 : stm32f10x.h
  • NVIC_ISPR_SETPEND_2 : stm32f10x.h
  • NVIC_ISPR_SETPEND_20 : stm32f10x.h
  • NVIC_ISPR_SETPEND_21 : stm32f10x.h
  • NVIC_ISPR_SETPEND_22 : stm32f10x.h
  • NVIC_ISPR_SETPEND_23 : stm32f10x.h
  • NVIC_ISPR_SETPEND_24 : stm32f10x.h
  • NVIC_ISPR_SETPEND_25 : stm32f10x.h
  • NVIC_ISPR_SETPEND_26 : stm32f10x.h
  • NVIC_ISPR_SETPEND_27 : stm32f10x.h
  • NVIC_ISPR_SETPEND_28 : stm32f10x.h
  • NVIC_ISPR_SETPEND_29 : stm32f10x.h
  • NVIC_ISPR_SETPEND_3 : stm32f10x.h
  • NVIC_ISPR_SETPEND_30 : stm32f10x.h
  • NVIC_ISPR_SETPEND_31 : stm32f10x.h
  • NVIC_ISPR_SETPEND_4 : stm32f10x.h
  • NVIC_ISPR_SETPEND_5 : stm32f10x.h
  • NVIC_ISPR_SETPEND_6 : stm32f10x.h
  • NVIC_ISPR_SETPEND_7 : stm32f10x.h
  • NVIC_ISPR_SETPEND_8 : stm32f10x.h
  • NVIC_ISPR_SETPEND_9 : stm32f10x.h
  • NVIC_LP_SEVONPEND : misc.h
  • NVIC_LP_SLEEPDEEP : misc.h
  • NVIC_LP_SLEEPONEXIT : misc.h
  • NVIC_PriorityGroup_0 : misc.h
  • NVIC_PriorityGroup_1 : misc.h
  • NVIC_PriorityGroup_2 : misc.h
  • NVIC_PriorityGroup_3 : misc.h
  • NVIC_PriorityGroup_4 : misc.h
  • NVIC_PriorityGroupConfig() : misc.h , misc.c
  • NVIC_SetVectorTable() : misc.c , misc.h
  • NVIC_SystemLPConfig() : misc.c , misc.h
  • NVIC_VectTab_FLASH : misc.h
  • NVIC_VectTab_RAM : misc.h


STM32F10x Standard Peripherals Firmware Library: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- o -

  • OAR1_ADD0_Reset : stm32f10x_i2c.c
  • OAR1_ADD0_Set : stm32f10x_i2c.c
  • OAR2_ADD2_Reset : stm32f10x_i2c.c
  • OAR2_ENDUAL_Reset : stm32f10x_i2c.c
  • OAR2_ENDUAL_Set : stm32f10x_i2c.c
  • OB : stm32f10x.h
  • OB_BASE : stm32f10x.h
  • OB_DBG : stm32f10x_ip_dbg.c
  • OB_IWDG_HW : stm32f10x_flash.h
  • OB_IWDG_SW : stm32f10x_flash.h
  • OB_STDBY_NoRST : stm32f10x_flash.h
  • OB_STDBY_RST : stm32f10x_flash.h
  • OB_STOP_NoRST : stm32f10x_flash.h
  • OB_STOP_RST : stm32f10x_flash.h
  • OB_USER_BFB2 : stm32f10x_flash.c
  • OneNAND_AsynchronousRead() : stm32100e_eval_fsmc_onenand.c , stm32100e_eval_fsmc_onenand.h
  • ONENAND_BOOTPARTITION_ADDR : stm32100e_eval_fsmc_onenand.c
  • OneNAND_BUFFER_SIZE : STM32F10x_StdPeriph_Examples/FSMC/OneNAND/main.c
  • OneNAND_CMD_ERASE : stm32100e_eval_fsmc_onenand.h
  • OneNAND_CMD_LOAD : stm32100e_eval_fsmc_onenand.h
  • OneNAND_CMD_PROGRAM : stm32100e_eval_fsmc_onenand.h
  • OneNAND_CMD_READ_ID : stm32100e_eval_fsmc_onenand.h
  • OneNAND_CMD_RESET : stm32100e_eval_fsmc_onenand.h
  • OneNAND_CMD_UNLOCK : stm32100e_eval_fsmc_onenand.h
  • OneNAND_DATA_RAM_0_0_ADD : stm32100e_eval_fsmc_onenand.h
  • OneNAND_DATA_RAM_0_0_REG : stm32100e_eval_fsmc_onenand.h
  • OneNAND_DATA_RAM_0_1_ADD : stm32100e_eval_fsmc_onenand.h
  • OneNAND_DATA_RAM_0_1_REG : stm32100e_eval_fsmc_onenand.h
  • OneNAND_DATA_RAM_0_2_ADD : stm32100e_eval_fsmc_onenand.h
  • OneNAND_DATA_RAM_0_2_REG : stm32100e_eval_fsmc_onenand.h
  • OneNAND_DATA_RAM_0_3_ADD : stm32100e_eval_fsmc_onenand.h
  • OneNAND_DATA_RAM_0_3_REG : stm32100e_eval_fsmc_onenand.h
  • OneNAND_DATA_RAM_1_0_ADD : stm32100e_eval_fsmc_onenand.h
  • OneNAND_DATA_RAM_1_0_REG : stm32100e_eval_fsmc_onenand.h
  • OneNAND_DATA_RAM_1_1_ADD : stm32100e_eval_fsmc_onenand.h
  • OneNAND_DATA_RAM_1_1_REG : stm32100e_eval_fsmc_onenand.h
  • OneNAND_DATA_RAM_1_2_ADD : stm32100e_eval_fsmc_onenand.h
  • OneNAND_DATA_RAM_1_2_REG : stm32100e_eval_fsmc_onenand.h
  • OneNAND_DATA_RAM_1_3_ADD : stm32100e_eval_fsmc_onenand.h
  • OneNAND_DATA_RAM_1_3_REG : stm32100e_eval_fsmc_onenand.h
  • OneNAND_EraseBlock() : stm32100e_eval_fsmc_onenand.c , stm32100e_eval_fsmc_onenand.h
  • OneNAND_ERROR : stm32100e_eval_fsmc_onenand.h
  • OneNAND_ID : STM32F10x_StdPeriph_Examples/FSMC/OneNAND/main.c
  • OneNAND_Init() : stm32100e_eval_fsmc_onenand.c , stm32100e_eval_fsmc_onenand.h
  • OneNAND_NUMBER_OF_PAGE_PER_BLOCK : STM32F10x_StdPeriph_Examples/FSMC/OneNAND/main.c
  • OneNAND_ONGOING : stm32100e_eval_fsmc_onenand.h
  • OneNAND_ReadControllerStatus() : stm32100e_eval_fsmc_onenand.c , stm32100e_eval_fsmc_onenand.h
  • OneNAND_ReadID() : stm32100e_eval_fsmc_onenand.c , stm32100e_eval_fsmc_onenand.h
  • OneNAND_ReadStatus() : stm32100e_eval_fsmc_onenand.h , stm32100e_eval_fsmc_onenand.c
  • OneNAND_REG_AMOUNTOFBUFFERS : stm32100e_eval_fsmc_onenand.h
  • OneNAND_REG_BOOTBUFFERSIZE : stm32100e_eval_fsmc_onenand.h
  • OneNAND_REG_COMMAND : stm32100e_eval_fsmc_onenand.h
  • OneNAND_REG_CONTROLSTATUS : stm32100e_eval_fsmc_onenand.h
  • OneNAND_REG_DATABUFFERSIZE : stm32100e_eval_fsmc_onenand.h
  • OneNAND_REG_DEVICEID : stm32100e_eval_fsmc_onenand.h
  • OneNAND_REG_INTERRUPT : stm32100e_eval_fsmc_onenand.h
  • OneNAND_REG_MANUFACTERID : stm32100e_eval_fsmc_onenand.h
  • OneNAND_REG_STARTADDRESINT8_T : stm32100e_eval_fsmc_onenand.h
  • OneNAND_REG_STARTADDRESS1 : stm32100e_eval_fsmc_onenand.h
  • OneNAND_REG_STARTADDRESS3 : stm32100e_eval_fsmc_onenand.h
  • OneNAND_REG_STARTADDRESS4 : stm32100e_eval_fsmc_onenand.h
  • OneNAND_REG_STARTBLOCKADDRESS : stm32100e_eval_fsmc_onenand.h
  • OneNAND_REG_STARTBUFFER : stm32100e_eval_fsmc_onenand.h
  • OneNAND_REG_SYSTEMCONFIGURATION : stm32100e_eval_fsmc_onenand.h
  • OneNAND_REG_TECHNOLOGY : stm32100e_eval_fsmc_onenand.h
  • OneNAND_REG_WRITEPROTECTIONSTATUS : stm32100e_eval_fsmc_onenand.h
  • OneNAND_Reset() : stm32100e_eval_fsmc_onenand.c , stm32100e_eval_fsmc_onenand.h
  • OneNAND_SAMSUNG_DEVICE_ID : STM32F10x_StdPeriph_Examples/FSMC/OneNAND/main.c
  • OneNAND_SAMSUNG_MANUFACTURER_ID : STM32F10x_StdPeriph_Examples/FSMC/OneNAND/main.c
  • OneNAND_Status : stm32100e_eval_fsmc_onenand.h
  • OneNAND_SUCCESS : stm32100e_eval_fsmc_onenand.h
  • OneNAND_SynchronousRead() : stm32100e_eval_fsmc_onenand.c , stm32100e_eval_fsmc_onenand.h
  • OneNAND_TIMEOUT : stm32100e_eval_fsmc_onenand.h
  • OneNAND_UnlockBlock() : stm32100e_eval_fsmc_onenand.c , stm32100e_eval_fsmc_onenand.h
  • OneNAND_WRITE : stm32100e_eval_fsmc_onenand.c
  • OneNAND_WRITE_BLOCK_NUMBER : STM32F10x_StdPeriph_Examples/FSMC/OneNAND/main.c
  • OneNAND_WRITE_PAGE_NUMBER : STM32F10x_StdPeriph_Examples/FSMC/OneNAND/main.c
  • OneNAND_WriteBuffer() : stm32100e_eval_fsmc_onenand.h , stm32100e_eval_fsmc_onenand.c
  • OperationComplete : STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/main.c


STM32F10x Standard Peripherals Firmware Library: Globals

  • File List
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- a -

  • AbortReason : stm32100b_eval_cec.c , stm32100e_eval_cec.c
  • ABS : stm32100e_eval_lcd.c , stm32l152_eval_lcd.c , stm3210b_eval_lcd.c , stm32100b_eval_lcd.c , stm3210c_eval_lcd.c , stm3210e_eval_lcd.c
  • ACCESS_PERMISSION : STM32F10x_StdPeriph_Examples/CortexM3/MPU/main.c
  • accesspermission() : accesspermission.c , CortexM3/MPU/main.h
  • ACR_HLFCYA_Mask : stm32f10x_flash.c
  • ACR_LATENCY_Mask : stm32f10x_flash.c
  • ACR_PRFTBE_Mask : stm32f10x_flash.c
  • ACR_PRFTBS_Mask : stm32f10x_flash.c
  • ADC1 : stm32f10x.h
  • ADC1_2_IRQHandler() : STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_it.h
  • ADC1_BASE : stm32f10x.h
  • ADC1_DBG : stm32f10x_ip_dbg.c
  • ADC1_DR_Address : STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/main.c , STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c , STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/main.c , STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/main.c , STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/main.c , STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/main.c
  • ADC1ConvertedValue : STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c
  • ADC2 : stm32f10x.h
  • ADC2_BASE : stm32f10x.h
  • ADC2_DBG : stm32f10x_ip_dbg.c
  • ADC2ConvertedValue : STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_it.c
  • ADC3 : stm32f10x.h
  • ADC3_BASE : stm32f10x.h
  • ADC3_DBG : stm32f10x_ip_dbg.c
  • ADC3_DR_Address : STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c
  • ADC3ConvertedValue : STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c
  • ADC_AnalogWatchdog_AllInjecEnable : stm32f10x_adc.h
  • ADC_AnalogWatchdog_AllRegAllInjecEnable : stm32f10x_adc.h
  • ADC_AnalogWatchdog_AllRegEnable : stm32f10x_adc.h
  • ADC_AnalogWatchdog_None : stm32f10x_adc.h
  • ADC_AnalogWatchdog_SingleInjecEnable : stm32f10x_adc.h
  • ADC_AnalogWatchdog_SingleRegEnable : stm32f10x_adc.h
  • ADC_AnalogWatchdog_SingleRegOrInjecEnable : stm32f10x_adc.h
  • ADC_AnalogWatchdogCmd() : stm32f10x_adc.h , stm32f10x_adc.c
  • ADC_AnalogWatchdogSingleChannelConfig() : stm32f10x_adc.h , stm32f10x_adc.c
  • ADC_AnalogWatchdogThresholdsConfig() : stm32f10x_adc.h , stm32f10x_adc.c
  • ADC_AutoInjectedConvCmd() : stm32f10x_adc.h , stm32f10x_adc.c
  • ADC_Channel_0 : stm32f10x_adc.h
  • ADC_Channel_1 : stm32f10x_adc.h
  • ADC_Channel_10 : stm32f10x_adc.h
  • ADC_Channel_11 : stm32f10x_adc.h
  • ADC_Channel_12 : stm32f10x_adc.h
  • ADC_Channel_13 : stm32f10x_adc.h
  • ADC_Channel_14 : stm32f10x_adc.h
  • ADC_Channel_15 : stm32f10x_adc.h
  • ADC_Channel_16 : stm32f10x_adc.h
  • ADC_Channel_17 : stm32f10x_adc.h
  • ADC_Channel_2 : stm32f10x_adc.h
  • ADC_Channel_3 : stm32f10x_adc.h
  • ADC_Channel_4 : stm32f10x_adc.h
  • ADC_Channel_5 : stm32f10x_adc.h
  • ADC_Channel_6 : stm32f10x_adc.h
  • ADC_Channel_7 : stm32f10x_adc.h
  • ADC_Channel_8 : stm32f10x_adc.h
  • ADC_Channel_9 : stm32f10x_adc.h
  • ADC_Channel_TempSensor : stm32f10x_adc.h
  • ADC_Channel_Vrefint : stm32f10x_adc.h
  • ADC_ClearFlag() : stm32f10x_adc.h , stm32f10x_adc.c
  • ADC_ClearITPendingBit() : stm32f10x_adc.h , stm32f10x_adc.c
  • ADC_Cmd() : stm32f10x_adc.h , stm32f10x_adc.c
  • ADC_CR1_AWDCH : stm32f10x.h
  • ADC_CR1_AWDCH_0 : stm32f10x.h
  • ADC_CR1_AWDCH_1 : stm32f10x.h
  • ADC_CR1_AWDCH_2 : stm32f10x.h
  • ADC_CR1_AWDCH_3 : stm32f10x.h
  • ADC_CR1_AWDCH_4 : stm32f10x.h
  • ADC_CR1_AWDEN : stm32f10x.h
  • ADC_CR1_AWDIE : stm32f10x.h
  • ADC_CR1_AWDSGL : stm32f10x.h
  • ADC_CR1_DISCEN : stm32f10x.h
  • ADC_CR1_DISCNUM : stm32f10x.h
  • ADC_CR1_DISCNUM_0 : stm32f10x.h
  • ADC_CR1_DISCNUM_1 : stm32f10x.h
  • ADC_CR1_DISCNUM_2 : stm32f10x.h
  • ADC_CR1_DUALMOD : stm32f10x.h
  • ADC_CR1_DUALMOD_0 : stm32f10x.h
  • ADC_CR1_DUALMOD_1 : stm32f10x.h
  • ADC_CR1_DUALMOD_2 : stm32f10x.h
  • ADC_CR1_DUALMOD_3 : stm32f10x.h
  • ADC_CR1_EOCIE : stm32f10x.h
  • ADC_CR1_JAUTO : stm32f10x.h
  • ADC_CR1_JAWDEN : stm32f10x.h
  • ADC_CR1_JDISCEN : stm32f10x.h
  • ADC_CR1_JEOCIE : stm32f10x.h
  • ADC_CR1_SCAN : stm32f10x.h
  • ADC_CR2_ADON : stm32f10x.h
  • ADC_CR2_ALIGN : stm32f10x.h
  • ADC_CR2_CAL : stm32f10x.h
  • ADC_CR2_CONT : stm32f10x.h
  • ADC_CR2_DMA : stm32f10x.h
  • ADC_CR2_EXTSEL : stm32f10x.h
  • ADC_CR2_EXTSEL_0 : stm32f10x.h
  • ADC_CR2_EXTSEL_1 : stm32f10x.h
  • ADC_CR2_EXTSEL_2 : stm32f10x.h
  • ADC_CR2_EXTTRIG : stm32f10x.h
  • ADC_CR2_JEXTSEL : stm32f10x.h
  • ADC_CR2_JEXTSEL_0 : stm32f10x.h
  • ADC_CR2_JEXTSEL_1 : stm32f10x.h
  • ADC_CR2_JEXTSEL_2 : stm32f10x.h
  • ADC_CR2_JEXTTRIG : stm32f10x.h
  • ADC_CR2_JSWSTART : stm32f10x.h
  • ADC_CR2_RSTCAL : stm32f10x.h
  • ADC_CR2_SWSTART : stm32f10x.h
  • ADC_CR2_TSVREFE : stm32f10x.h
  • ADC_DataAlign_Left : stm32f10x_adc.h
  • ADC_DataAlign_Right : stm32f10x_adc.h
  • ADC_DeInit() : stm32f10x_adc.h , stm32f10x_adc.c
  • ADC_DiscModeChannelCountConfig() : stm32f10x_adc.h , stm32f10x_adc.c
  • ADC_DiscModeCmd() : stm32f10x_adc.h , stm32f10x_adc.c
  • ADC_DMACmd() : stm32f10x_adc.h , stm32f10x_adc.c
  • ADC_DR_ADC2DATA : stm32f10x.h
  • ADC_DR_DATA : stm32f10x.h
  • ADC_DualConvertedValueTab : STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/main.c
  • ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO : stm32f10x_adc.h
  • ADC_ExternalTrigConv_None : stm32f10x_adc.h
  • ADC_ExternalTrigConv_T1_CC1 : stm32f10x_adc.h
  • ADC_ExternalTrigConv_T1_CC2 : stm32f10x_adc.h
  • ADC_ExternalTrigConv_T1_CC3 : stm32f10x_adc.h
  • ADC_ExternalTrigConv_T2_CC2 : stm32f10x_adc.h
  • ADC_ExternalTrigConv_T2_CC3 : stm32f10x_adc.h
  • ADC_ExternalTrigConv_T3_CC1 : stm32f10x_adc.h
  • ADC_ExternalTrigConv_T3_TRGO : stm32f10x_adc.h
  • ADC_ExternalTrigConv_T4_CC4 : stm32f10x_adc.h
  • ADC_ExternalTrigConv_T5_CC1 : stm32f10x_adc.h
  • ADC_ExternalTrigConv_T5_CC3 : stm32f10x_adc.h
  • ADC_ExternalTrigConv_T8_CC1 : stm32f10x_adc.h
  • ADC_ExternalTrigConv_T8_TRGO : stm32f10x_adc.h
  • ADC_ExternalTrigConvCmd() : stm32f10x_adc.h , stm32f10x_adc.c
  • ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 : stm32f10x_adc.h
  • ADC_ExternalTrigInjecConv_None : stm32f10x_adc.h
  • ADC_ExternalTrigInjecConv_T1_CC4 : stm32f10x_adc.h
  • ADC_ExternalTrigInjecConv_T1_TRGO : stm32f10x_adc.h
  • ADC_ExternalTrigInjecConv_T2_CC1 : stm32f10x_adc.h
  • ADC_ExternalTrigInjecConv_T2_TRGO : stm32f10x_adc.h
  • ADC_ExternalTrigInjecConv_T3_CC4 : stm32f10x_adc.h
  • ADC_ExternalTrigInjecConv_T4_CC3 : stm32f10x_adc.h
  • ADC_ExternalTrigInjecConv_T4_TRGO : stm32f10x_adc.h
  • ADC_ExternalTrigInjecConv_T5_CC4 : stm32f10x_adc.h
  • ADC_ExternalTrigInjecConv_T5_TRGO : stm32f10x_adc.h
  • ADC_ExternalTrigInjecConv_T8_CC2 : stm32f10x_adc.h
  • ADC_ExternalTrigInjecConv_T8_CC4 : stm32f10x_adc.h
  • ADC_ExternalTrigInjectedConvCmd() : stm32f10x_adc.h , stm32f10x_adc.c
  • ADC_ExternalTrigInjectedConvConfig() : stm32f10x_adc.h , stm32f10x_adc.c
  • ADC_FLAG_AWD : stm32f10x_adc.h
  • ADC_FLAG_EOC : stm32f10x_adc.h
  • ADC_FLAG_JEOC : stm32f10x_adc.h
  • ADC_FLAG_JSTRT : stm32f10x_adc.h
  • ADC_FLAG_STRT : stm32f10x_adc.h
  • ADC_GetCalibrationStatus() : stm32f10x_adc.h , stm32f10x_adc.c
  • ADC_GetConversionValue() : stm32f10x_adc.h , stm32f10x_adc.c
  • ADC_GetDualModeConversionValue() : stm32f10x_adc.h , stm32f10x_adc.c
  • ADC_GetFlagStatus() : stm32f10x_adc.h , stm32f10x_adc.c
  • ADC_GetInjectedConversionValue() : stm32f10x_adc.h , stm32f10x_adc.c
  • ADC_GetITStatus() : stm32f10x_adc.h , stm32f10x_adc.c
  • ADC_GetResetCalibrationStatus() : stm32f10x_adc.h , stm32f10x_adc.c
  • ADC_GetSoftwareStartConvStatus() : stm32f10x_adc.h , stm32f10x_adc.c
  • ADC_GetSoftwareStartInjectedConvCmdStatus() : stm32f10x_adc.h , stm32f10x_adc.c
  • ADC_HTR_HT : stm32f10x.h
  • ADC_Init() : stm32f10x_adc.h , stm32f10x_adc.c
  • ADC_InitStructure : STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c , STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/main.c , STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/main.c , STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/main.c , STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/main.c , STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/main.c , STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/main.c
  • ADC_InjectedChannel_1 : stm32f10x_adc.h
  • ADC_InjectedChannel_2 : stm32f10x_adc.h
  • ADC_InjectedChannel_3 : stm32f10x_adc.h
  • ADC_InjectedChannel_4 : stm32f10x_adc.h
  • ADC_InjectedChannelConfig() : stm32f10x_adc.h , stm32f10x_adc.c
  • ADC_InjectedConvertedValueTab : STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/main.c , STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/main.c , STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_it.c
  • ADC_InjectedDiscModeCmd() : stm32f10x_adc.h , stm32f10x_adc.c
  • ADC_InjectedSequencerLengthConfig() : stm32f10x_adc.h , stm32f10x_adc.c
  • ADC_IT_AWD : stm32f10x_adc.h
  • ADC_IT_EOC : stm32f10x_adc.h
  • ADC_IT_JEOC : stm32f10x_adc.h
  • ADC_ITConfig() : stm32f10x_adc.h , stm32f10x_adc.c
  • ADC_JDR1_JDATA : stm32f10x.h
  • ADC_JDR2_JDATA : stm32f10x.h
  • ADC_JDR3_JDATA : stm32f10x.h
  • ADC_JDR4_JDATA : stm32f10x.h
  • ADC_JOFR1_JOFFSET1 : stm32f10x.h
  • ADC_JOFR2_JOFFSET2 : stm32f10x.h
  • ADC_JOFR3_JOFFSET3 : stm32f10x.h
  • ADC_JOFR4_JOFFSET4 : stm32f10x.h
  • ADC_JSQR_JL : stm32f10x.h
  • ADC_JSQR_JL_0 : stm32f10x.h
  • ADC_JSQR_JL_1 : stm32f10x.h
  • ADC_JSQR_JSQ1 : stm32f10x.h
  • ADC_JSQR_JSQ1_0 : stm32f10x.h
  • ADC_JSQR_JSQ1_1 : stm32f10x.h
  • ADC_JSQR_JSQ1_2 : stm32f10x.h
  • ADC_JSQR_JSQ1_3 : stm32f10x.h
  • ADC_JSQR_JSQ1_4 : stm32f10x.h
  • ADC_JSQR_JSQ2 : stm32f10x.h
  • ADC_JSQR_JSQ2_0 : stm32f10x.h
  • ADC_JSQR_JSQ2_1 : stm32f10x.h
  • ADC_JSQR_JSQ2_2 : stm32f10x.h
  • ADC_JSQR_JSQ2_3 : stm32f10x.h
  • ADC_JSQR_JSQ2_4 : stm32f10x.h
  • ADC_JSQR_JSQ3 : stm32f10x.h
  • ADC_JSQR_JSQ3_0 : stm32f10x.h
  • ADC_JSQR_JSQ3_1 : stm32f10x.h
  • ADC_JSQR_JSQ3_2 : stm32f10x.h
  • ADC_JSQR_JSQ3_3 : stm32f10x.h
  • ADC_JSQR_JSQ3_4 : stm32f10x.h
  • ADC_JSQR_JSQ4 : stm32f10x.h
  • ADC_JSQR_JSQ4_0 : stm32f10x.h
  • ADC_JSQR_JSQ4_1 : stm32f10x.h
  • ADC_JSQR_JSQ4_2 : stm32f10x.h
  • ADC_JSQR_JSQ4_3 : stm32f10x.h
  • ADC_JSQR_JSQ4_4 : stm32f10x.h
  • ADC_LTR_LT : stm32f10x.h
  • ADC_Mode_AlterTrig : stm32f10x_adc.h
  • ADC_Mode_FastInterl : stm32f10x_adc.h
  • ADC_Mode_Independent : stm32f10x_adc.h
  • ADC_Mode_InjecSimult : stm32f10x_adc.h
  • ADC_Mode_InjecSimult_FastInterl : stm32f10x_adc.h
  • ADC_Mode_InjecSimult_SlowInterl : stm32f10x_adc.h
  • ADC_Mode_RegInjecSimult : stm32f10x_adc.h
  • ADC_Mode_RegSimult : stm32f10x_adc.h
  • ADC_Mode_RegSimult_AlterTrig : stm32f10x_adc.h
  • ADC_Mode_SlowInterl : stm32f10x_adc.h
  • ADC_RegularChannelConfig() : stm32f10x_adc.h , stm32f10x_adc.c
  • ADC_RegularConvertedValueTab : STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/main.c , STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/main.c
  • ADC_ResetCalibration() : stm32f10x_adc.h , stm32f10x_adc.c
  • ADC_SampleTime_13Cycles5 : stm32f10x_adc.h
  • ADC_SampleTime_1Cycles5 : stm32f10x_adc.h
  • ADC_SampleTime_239Cycles5 : stm32f10x_adc.h
  • ADC_SampleTime_28Cycles5 : stm32f10x_adc.h
  • ADC_SampleTime_41Cycles5 : stm32f10x_adc.h
  • ADC_SampleTime_55Cycles5 : stm32f10x_adc.h
  • ADC_SampleTime_71Cycles5 : stm32f10x_adc.h
  • ADC_SampleTime_7Cycles5 : stm32f10x_adc.h
  • ADC_SetInjectedOffset() : stm32f10x_adc.h , stm32f10x_adc.c
  • ADC_SMPR1_SMP10 : stm32f10x.h
  • ADC_SMPR1_SMP10_0 : stm32f10x.h
  • ADC_SMPR1_SMP10_1 : stm32f10x.h
  • ADC_SMPR1_SMP10_2 : stm32f10x.h
  • ADC_SMPR1_SMP11 : stm32f10x.h
  • ADC_SMPR1_SMP11_0 : stm32f10x.h
  • ADC_SMPR1_SMP11_1 : stm32f10x.h
  • ADC_SMPR1_SMP11_2 : stm32f10x.h
  • ADC_SMPR1_SMP12 : stm32f10x.h
  • ADC_SMPR1_SMP12_0 : stm32f10x.h
  • ADC_SMPR1_SMP12_1 : stm32f10x.h
  • ADC_SMPR1_SMP12_2 : stm32f10x.h
  • ADC_SMPR1_SMP13 : stm32f10x.h
  • ADC_SMPR1_SMP13_0 : stm32f10x.h
  • ADC_SMPR1_SMP13_1 : stm32f10x.h
  • ADC_SMPR1_SMP13_2 : stm32f10x.h
  • ADC_SMPR1_SMP14 : stm32f10x.h
  • ADC_SMPR1_SMP14_0 : stm32f10x.h
  • ADC_SMPR1_SMP14_1 : stm32f10x.h
  • ADC_SMPR1_SMP14_2 : stm32f10x.h
  • ADC_SMPR1_SMP15 : stm32f10x.h
  • ADC_SMPR1_SMP15_0 : stm32f10x.h
  • ADC_SMPR1_SMP15_1 : stm32f10x.h
  • ADC_SMPR1_SMP15_2 : stm32f10x.h
  • ADC_SMPR1_SMP16 : stm32f10x.h
  • ADC_SMPR1_SMP16_0 : stm32f10x.h
  • ADC_SMPR1_SMP16_1 : stm32f10x.h
  • ADC_SMPR1_SMP16_2 : stm32f10x.h
  • ADC_SMPR1_SMP17 : stm32f10x.h
  • ADC_SMPR1_SMP17_0 : stm32f10x.h
  • ADC_SMPR1_SMP17_1 : stm32f10x.h
  • ADC_SMPR1_SMP17_2 : stm32f10x.h
  • ADC_SMPR2_SMP0 : stm32f10x.h
  • ADC_SMPR2_SMP0_0 : stm32f10x.h
  • ADC_SMPR2_SMP0_1 : stm32f10x.h
  • ADC_SMPR2_SMP0_2 : stm32f10x.h
  • ADC_SMPR2_SMP1 : stm32f10x.h
  • ADC_SMPR2_SMP1_0 : stm32f10x.h
  • ADC_SMPR2_SMP1_1 : stm32f10x.h
  • ADC_SMPR2_SMP1_2 : stm32f10x.h
  • ADC_SMPR2_SMP2 : stm32f10x.h
  • ADC_SMPR2_SMP2_0 : stm32f10x.h
  • ADC_SMPR2_SMP2_1 : stm32f10x.h
  • ADC_SMPR2_SMP2_2 : stm32f10x.h
  • ADC_SMPR2_SMP3 : stm32f10x.h
  • ADC_SMPR2_SMP3_0 : stm32f10x.h
  • ADC_SMPR2_SMP3_1 : stm32f10x.h
  • ADC_SMPR2_SMP3_2 : stm32f10x.h
  • ADC_SMPR2_SMP4 : stm32f10x.h
  • ADC_SMPR2_SMP4_0 : stm32f10x.h
  • ADC_SMPR2_SMP4_1 : stm32f10x.h
  • ADC_SMPR2_SMP4_2 : stm32f10x.h
  • ADC_SMPR2_SMP5 : stm32f10x.h
  • ADC_SMPR2_SMP5_0 : stm32f10x.h
  • ADC_SMPR2_SMP5_1 : stm32f10x.h
  • ADC_SMPR2_SMP5_2 : stm32f10x.h
  • ADC_SMPR2_SMP6 : stm32f10x.h
  • ADC_SMPR2_SMP6_0 : stm32f10x.h
  • ADC_SMPR2_SMP6_1 : stm32f10x.h
  • ADC_SMPR2_SMP6_2 : stm32f10x.h
  • ADC_SMPR2_SMP7 : stm32f10x.h
  • ADC_SMPR2_SMP7_0 : stm32f10x.h
  • ADC_SMPR2_SMP7_1 : stm32f10x.h
  • ADC_SMPR2_SMP7_2 : stm32f10x.h
  • ADC_SMPR2_SMP8 : stm32f10x.h
  • ADC_SMPR2_SMP8_0 : stm32f10x.h
  • ADC_SMPR2_SMP8_1 : stm32f10x.h
  • ADC_SMPR2_SMP8_2 : stm32f10x.h
  • ADC_SMPR2_SMP9 : stm32f10x.h
  • ADC_SMPR2_SMP9_0 : stm32f10x.h
  • ADC_SMPR2_SMP9_1 : stm32f10x.h
  • ADC_SMPR2_SMP9_2 : stm32f10x.h
  • ADC_SoftwareStartConvCmd() : stm32f10x_adc.h , stm32f10x_adc.c
  • ADC_SoftwareStartInjectedConvCmd() : stm32f10x_adc.h , stm32f10x_adc.c
  • ADC_SQR1_L : stm32f10x.h
  • ADC_SQR1_L_0 : stm32f10x.h
  • ADC_SQR1_L_1 : stm32f10x.h
  • ADC_SQR1_L_2 : stm32f10x.h
  • ADC_SQR1_L_3 : stm32f10x.h
  • ADC_SQR1_SQ13 : stm32f10x.h
  • ADC_SQR1_SQ13_0 : stm32f10x.h
  • ADC_SQR1_SQ13_1 : stm32f10x.h
  • ADC_SQR1_SQ13_2 : stm32f10x.h
  • ADC_SQR1_SQ13_3 : stm32f10x.h
  • ADC_SQR1_SQ13_4 : stm32f10x.h
  • ADC_SQR1_SQ14 : stm32f10x.h
  • ADC_SQR1_SQ14_0 : stm32f10x.h
  • ADC_SQR1_SQ14_1 : stm32f10x.h
  • ADC_SQR1_SQ14_2 : stm32f10x.h
  • ADC_SQR1_SQ14_3 : stm32f10x.h
  • ADC_SQR1_SQ14_4 : stm32f10x.h
  • ADC_SQR1_SQ15 : stm32f10x.h
  • ADC_SQR1_SQ15_0 : stm32f10x.h
  • ADC_SQR1_SQ15_1 : stm32f10x.h
  • ADC_SQR1_SQ15_2 : stm32f10x.h
  • ADC_SQR1_SQ15_3 : stm32f10x.h
  • ADC_SQR1_SQ15_4 : stm32f10x.h
  • ADC_SQR1_SQ16 : stm32f10x.h
  • ADC_SQR1_SQ16_0 : stm32f10x.h
  • ADC_SQR1_SQ16_1 : stm32f10x.h
  • ADC_SQR1_SQ16_2 : stm32f10x.h
  • ADC_SQR1_SQ16_3 : stm32f10x.h
  • ADC_SQR1_SQ16_4 : stm32f10x.h
  • ADC_SQR2_SQ10 : stm32f10x.h
  • ADC_SQR2_SQ10_0 : stm32f10x.h
  • ADC_SQR2_SQ10_1 : stm32f10x.h
  • ADC_SQR2_SQ10_2 : stm32f10x.h
  • ADC_SQR2_SQ10_3 : stm32f10x.h
  • ADC_SQR2_SQ10_4 : stm32f10x.h
  • ADC_SQR2_SQ11 : stm32f10x.h
  • ADC_SQR2_SQ11_0 : stm32f10x.h
  • ADC_SQR2_SQ11_1 : stm32f10x.h
  • ADC_SQR2_SQ11_2 : stm32f10x.h
  • ADC_SQR2_SQ11_3 : stm32f10x.h
  • ADC_SQR2_SQ11_4 : stm32f10x.h
  • ADC_SQR2_SQ12 : stm32f10x.h
  • ADC_SQR2_SQ12_0 : stm32f10x.h
  • ADC_SQR2_SQ12_1 : stm32f10x.h
  • ADC_SQR2_SQ12_2 : stm32f10x.h
  • ADC_SQR2_SQ12_3 : stm32f10x.h
  • ADC_SQR2_SQ12_4 : stm32f10x.h
  • ADC_SQR2_SQ7 : stm32f10x.h
  • ADC_SQR2_SQ7_0 : stm32f10x.h
  • ADC_SQR2_SQ7_1 : stm32f10x.h
  • ADC_SQR2_SQ7_2 : stm32f10x.h
  • ADC_SQR2_SQ7_3 : stm32f10x.h
  • ADC_SQR2_SQ7_4 : stm32f10x.h
  • ADC_SQR2_SQ8 : stm32f10x.h
  • ADC_SQR2_SQ8_0 : stm32f10x.h
  • ADC_SQR2_SQ8_1 : stm32f10x.h
  • ADC_SQR2_SQ8_2 : stm32f10x.h
  • ADC_SQR2_SQ8_3 : stm32f10x.h
  • ADC_SQR2_SQ8_4 : stm32f10x.h
  • ADC_SQR2_SQ9 : stm32f10x.h
  • ADC_SQR2_SQ9_0 : stm32f10x.h
  • ADC_SQR2_SQ9_1 : stm32f10x.h
  • ADC_SQR2_SQ9_2 : stm32f10x.h
  • ADC_SQR2_SQ9_3 : stm32f10x.h
  • ADC_SQR2_SQ9_4 : stm32f10x.h
  • ADC_SQR3_SQ1 : stm32f10x.h
  • ADC_SQR3_SQ1_0 : stm32f10x.h
  • ADC_SQR3_SQ1_1 : stm32f10x.h
  • ADC_SQR3_SQ1_2 : stm32f10x.h
  • ADC_SQR3_SQ1_3 : stm32f10x.h
  • ADC_SQR3_SQ1_4 : stm32f10x.h
  • ADC_SQR3_SQ2 : stm32f10x.h
  • ADC_SQR3_SQ2_0 : stm32f10x.h
  • ADC_SQR3_SQ2_1 : stm32f10x.h
  • ADC_SQR3_SQ2_2 : stm32f10x.h
  • ADC_SQR3_SQ2_3 : stm32f10x.h
  • ADC_SQR3_SQ2_4 : stm32f10x.h
  • ADC_SQR3_SQ3 : stm32f10x.h
  • ADC_SQR3_SQ3_0 : stm32f10x.h
  • ADC_SQR3_SQ3_1 : stm32f10x.h
  • ADC_SQR3_SQ3_2 : stm32f10x.h
  • ADC_SQR3_SQ3_3 : stm32f10x.h
  • ADC_SQR3_SQ3_4 : stm32f10x.h
  • ADC_SQR3_SQ4 : stm32f10x.h
  • ADC_SQR3_SQ4_0 : stm32f10x.h
  • ADC_SQR3_SQ4_1 : stm32f10x.h
  • ADC_SQR3_SQ4_2 : stm32f10x.h
  • ADC_SQR3_SQ4_3 : stm32f10x.h
  • ADC_SQR3_SQ4_4 : stm32f10x.h
  • ADC_SQR3_SQ5 : stm32f10x.h
  • ADC_SQR3_SQ5_0 : stm32f10x.h
  • ADC_SQR3_SQ5_1 : stm32f10x.h
  • ADC_SQR3_SQ5_2 : stm32f10x.h
  • ADC_SQR3_SQ5_3 : stm32f10x.h
  • ADC_SQR3_SQ5_4 : stm32f10x.h
  • ADC_SQR3_SQ6 : stm32f10x.h
  • ADC_SQR3_SQ6_0 : stm32f10x.h
  • ADC_SQR3_SQ6_1 : stm32f10x.h
  • ADC_SQR3_SQ6_2 : stm32f10x.h
  • ADC_SQR3_SQ6_3 : stm32f10x.h
  • ADC_SQR3_SQ6_4 : stm32f10x.h
  • ADC_SR_AWD : stm32f10x.h
  • ADC_SR_EOC : stm32f10x.h
  • ADC_SR_JEOC : stm32f10x.h
  • ADC_SR_JSTRT : stm32f10x.h
  • ADC_SR_STRT : stm32f10x.h
  • ADC_StartCalibration() : stm32f10x_adc.c , stm32f10x_adc.h
  • ADC_StructInit() : stm32f10x_adc.h , stm32f10x_adc.c
  • ADC_TempSensorVrefintCmd() : stm32f10x_adc.c , stm32f10x_adc.h
  • ADCConvertedValue : STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/main.c
  • ADCPrescTable : stm32f10x_rcc.c
  • ADDR_1st_CYCLE : stm3210e_eval_fsmc_nand.h
  • ADDR_2nd_CYCLE : stm3210e_eval_fsmc_nand.h
  • ADDR_3rd_CYCLE : stm3210e_eval_fsmc_nand.h
  • ADDR_4th_CYCLE : stm3210e_eval_fsmc_nand.h
  • ADDR_AREA : stm3210e_eval_fsmc_nand.h
  • ADDR_SHIFT : stm3210e_eval_fsmc_nor.c
  • Address : STM32F10x_StdPeriph_Examples/FLASH/Program/main.c , STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/main.c , STM32F10x_StdPeriph_Examples/FSMC/OneNAND/main.c
  • AFIO : stm32f10x.h
  • AFIO_BASE : stm32f10x.h
  • AFIO_DBG : stm32f10x_ip_dbg.c
  • AFIO_EVCR_EVOE : stm32f10x.h
  • AFIO_EVCR_PIN : stm32f10x.h
  • AFIO_EVCR_PIN_0 : stm32f10x.h
  • AFIO_EVCR_PIN_1 : stm32f10x.h
  • AFIO_EVCR_PIN_2 : stm32f10x.h
  • AFIO_EVCR_PIN_3 : stm32f10x.h
  • AFIO_EVCR_PIN_PX0 : stm32f10x.h
  • AFIO_EVCR_PIN_PX1 : stm32f10x.h
  • AFIO_EVCR_PIN_PX10 : stm32f10x.h
  • AFIO_EVCR_PIN_PX11 : stm32f10x.h
  • AFIO_EVCR_PIN_PX12 : stm32f10x.h
  • AFIO_EVCR_PIN_PX13 : stm32f10x.h
  • AFIO_EVCR_PIN_PX14 : stm32f10x.h
  • AFIO_EVCR_PIN_PX15 : stm32f10x.h
  • AFIO_EVCR_PIN_PX2 : stm32f10x.h
  • AFIO_EVCR_PIN_PX3 : stm32f10x.h
  • AFIO_EVCR_PIN_PX4 : stm32f10x.h
  • AFIO_EVCR_PIN_PX5 : stm32f10x.h
  • AFIO_EVCR_PIN_PX6 : stm32f10x.h
  • AFIO_EVCR_PIN_PX7 : stm32f10x.h
  • AFIO_EVCR_PIN_PX8 : stm32f10x.h
  • AFIO_EVCR_PIN_PX9 : stm32f10x.h
  • AFIO_EVCR_PORT : stm32f10x.h
  • AFIO_EVCR_PORT_0 : stm32f10x.h
  • AFIO_EVCR_PORT_1 : stm32f10x.h
  • AFIO_EVCR_PORT_2 : stm32f10x.h
  • AFIO_EVCR_PORT_PA : stm32f10x.h
  • AFIO_EVCR_PORT_PB : stm32f10x.h
  • AFIO_EVCR_PORT_PC : stm32f10x.h
  • AFIO_EVCR_PORT_PD : stm32f10x.h
  • AFIO_EVCR_PORT_PE : stm32f10x.h
  • AFIO_EXTICR1_EXTI0 : stm32f10x.h
  • AFIO_EXTICR1_EXTI0_PA : stm32f10x.h
  • AFIO_EXTICR1_EXTI0_PB : stm32f10x.h
  • AFIO_EXTICR1_EXTI0_PC : stm32f10x.h
  • AFIO_EXTICR1_EXTI0_PD : stm32f10x.h
  • AFIO_EXTICR1_EXTI0_PE : stm32f10x.h
  • AFIO_EXTICR1_EXTI0_PF : stm32f10x.h
  • AFIO_EXTICR1_EXTI0_PG : stm32f10x.h
  • AFIO_EXTICR1_EXTI1 : stm32f10x.h
  • AFIO_EXTICR1_EXTI1_PA : stm32f10x.h
  • AFIO_EXTICR1_EXTI1_PB : stm32f10x.h
  • AFIO_EXTICR1_EXTI1_PC : stm32f10x.h
  • AFIO_EXTICR1_EXTI1_PD : stm32f10x.h
  • AFIO_EXTICR1_EXTI1_PE : stm32f10x.h
  • AFIO_EXTICR1_EXTI1_PF : stm32f10x.h
  • AFIO_EXTICR1_EXTI1_PG : stm32f10x.h
  • AFIO_EXTICR1_EXTI2 : stm32f10x.h
  • AFIO_EXTICR1_EXTI2_PA : stm32f10x.h
  • AFIO_EXTICR1_EXTI2_PB : stm32f10x.h
  • AFIO_EXTICR1_EXTI2_PC : stm32f10x.h
  • AFIO_EXTICR1_EXTI2_PD : stm32f10x.h
  • AFIO_EXTICR1_EXTI2_PE : stm32f10x.h
  • AFIO_EXTICR1_EXTI2_PF : stm32f10x.h
  • AFIO_EXTICR1_EXTI2_PG : stm32f10x.h
  • AFIO_EXTICR1_EXTI3 : stm32f10x.h
  • AFIO_EXTICR1_EXTI3_PA : stm32f10x.h
  • AFIO_EXTICR1_EXTI3_PB : stm32f10x.h
  • AFIO_EXTICR1_EXTI3_PC : stm32f10x.h
  • AFIO_EXTICR1_EXTI3_PD : stm32f10x.h
  • AFIO_EXTICR1_EXTI3_PE : stm32f10x.h
  • AFIO_EXTICR1_EXTI3_PF : stm32f10x.h
  • AFIO_EXTICR1_EXTI3_PG : stm32f10x.h
  • AFIO_EXTICR2_EXTI4 : stm32f10x.h
  • AFIO_EXTICR2_EXTI4_PA : stm32f10x.h
  • AFIO_EXTICR2_EXTI4_PB : stm32f10x.h
  • AFIO_EXTICR2_EXTI4_PC : stm32f10x.h
  • AFIO_EXTICR2_EXTI4_PD : stm32f10x.h
  • AFIO_EXTICR2_EXTI4_PE : stm32f10x.h
  • AFIO_EXTICR2_EXTI4_PF : stm32f10x.h
  • AFIO_EXTICR2_EXTI4_PG : stm32f10x.h
  • AFIO_EXTICR2_EXTI5 : stm32f10x.h
  • AFIO_EXTICR2_EXTI5_PA : stm32f10x.h
  • AFIO_EXTICR2_EXTI5_PB : stm32f10x.h
  • AFIO_EXTICR2_EXTI5_PC : stm32f10x.h
  • AFIO_EXTICR2_EXTI5_PD : stm32f10x.h
  • AFIO_EXTICR2_EXTI5_PE : stm32f10x.h
  • AFIO_EXTICR2_EXTI5_PF : stm32f10x.h
  • AFIO_EXTICR2_EXTI5_PG : stm32f10x.h
  • AFIO_EXTICR2_EXTI6 : stm32f10x.h
  • AFIO_EXTICR2_EXTI6_PA : stm32f10x.h
  • AFIO_EXTICR2_EXTI6_PB : stm32f10x.h
  • AFIO_EXTICR2_EXTI6_PC : stm32f10x.h
  • AFIO_EXTICR2_EXTI6_PD : stm32f10x.h
  • AFIO_EXTICR2_EXTI6_PE : stm32f10x.h
  • AFIO_EXTICR2_EXTI6_PF : stm32f10x.h
  • AFIO_EXTICR2_EXTI6_PG : stm32f10x.h
  • AFIO_EXTICR2_EXTI7 : stm32f10x.h
  • AFIO_EXTICR2_EXTI7_PA : stm32f10x.h
  • AFIO_EXTICR2_EXTI7_PB : stm32f10x.h
  • AFIO_EXTICR2_EXTI7_PC : stm32f10x.h
  • AFIO_EXTICR2_EXTI7_PD : stm32f10x.h
  • AFIO_EXTICR2_EXTI7_PE : stm32f10x.h
  • AFIO_EXTICR2_EXTI7_PF : stm32f10x.h
  • AFIO_EXTICR2_EXTI7_PG : stm32f10x.h
  • AFIO_EXTICR3_EXTI10 : stm32f10x.h
  • AFIO_EXTICR3_EXTI10_PA : stm32f10x.h
  • AFIO_EXTICR3_EXTI10_PB : stm32f10x.h
  • AFIO_EXTICR3_EXTI10_PC : stm32f10x.h
  • AFIO_EXTICR3_EXTI10_PD : stm32f10x.h
  • AFIO_EXTICR3_EXTI10_PE : stm32f10x.h
  • AFIO_EXTICR3_EXTI10_PF : stm32f10x.h
  • AFIO_EXTICR3_EXTI10_PG : stm32f10x.h
  • AFIO_EXTICR3_EXTI11 : stm32f10x.h
  • AFIO_EXTICR3_EXTI11_PA : stm32f10x.h
  • AFIO_EXTICR3_EXTI11_PB : stm32f10x.h
  • AFIO_EXTICR3_EXTI11_PC : stm32f10x.h
  • AFIO_EXTICR3_EXTI11_PD : stm32f10x.h
  • AFIO_EXTICR3_EXTI11_PE : stm32f10x.h
  • AFIO_EXTICR3_EXTI11_PF : stm32f10x.h
  • AFIO_EXTICR3_EXTI11_PG : stm32f10x.h
  • AFIO_EXTICR3_EXTI8 : stm32f10x.h
  • AFIO_EXTICR3_EXTI8_PA : stm32f10x.h
  • AFIO_EXTICR3_EXTI8_PB : stm32f10x.h
  • AFIO_EXTICR3_EXTI8_PC : stm32f10x.h
  • AFIO_EXTICR3_EXTI8_PD : stm32f10x.h
  • AFIO_EXTICR3_EXTI8_PE : stm32f10x.h
  • AFIO_EXTICR3_EXTI8_PF : stm32f10x.h
  • AFIO_EXTICR3_EXTI8_PG : stm32f10x.h
  • AFIO_EXTICR3_EXTI9 : stm32f10x.h
  • AFIO_EXTICR3_EXTI9_PA : stm32f10x.h
  • AFIO_EXTICR3_EXTI9_PB : stm32f10x.h
  • AFIO_EXTICR3_EXTI9_PC : stm32f10x.h
  • AFIO_EXTICR3_EXTI9_PD : stm32f10x.h
  • AFIO_EXTICR3_EXTI9_PE : stm32f10x.h
  • AFIO_EXTICR3_EXTI9_PF : stm32f10x.h
  • AFIO_EXTICR3_EXTI9_PG : stm32f10x.h
  • AFIO_EXTICR4_EXTI12 : stm32f10x.h
  • AFIO_EXTICR4_EXTI12_PA : stm32f10x.h
  • AFIO_EXTICR4_EXTI12_PB : stm32f10x.h
  • AFIO_EXTICR4_EXTI12_PC : stm32f10x.h
  • AFIO_EXTICR4_EXTI12_PD : stm32f10x.h
  • AFIO_EXTICR4_EXTI12_PE : stm32f10x.h
  • AFIO_EXTICR4_EXTI12_PF : stm32f10x.h
  • AFIO_EXTICR4_EXTI12_PG : stm32f10x.h
  • AFIO_EXTICR4_EXTI13 : stm32f10x.h
  • AFIO_EXTICR4_EXTI13_PA : stm32f10x.h
  • AFIO_EXTICR4_EXTI13_PB : stm32f10x.h
  • AFIO_EXTICR4_EXTI13_PC : stm32f10x.h
  • AFIO_EXTICR4_EXTI13_PD : stm32f10x.h
  • AFIO_EXTICR4_EXTI13_PE : stm32f10x.h
  • AFIO_EXTICR4_EXTI13_PF : stm32f10x.h
  • AFIO_EXTICR4_EXTI13_PG : stm32f10x.h
  • AFIO_EXTICR4_EXTI14 : stm32f10x.h
  • AFIO_EXTICR4_EXTI14_PA : stm32f10x.h
  • AFIO_EXTICR4_EXTI14_PB : stm32f10x.h
  • AFIO_EXTICR4_EXTI14_PC : stm32f10x.h
  • AFIO_EXTICR4_EXTI14_PD : stm32f10x.h
  • AFIO_EXTICR4_EXTI14_PE : stm32f10x.h
  • AFIO_EXTICR4_EXTI14_PF : stm32f10x.h
  • AFIO_EXTICR4_EXTI14_PG : stm32f10x.h
  • AFIO_EXTICR4_EXTI15 : stm32f10x.h
  • AFIO_EXTICR4_EXTI15_PA : stm32f10x.h
  • AFIO_EXTICR4_EXTI15_PB : stm32f10x.h
  • AFIO_EXTICR4_EXTI15_PC : stm32f10x.h
  • AFIO_EXTICR4_EXTI15_PD : stm32f10x.h
  • AFIO_EXTICR4_EXTI15_PE : stm32f10x.h
  • AFIO_EXTICR4_EXTI15_PF : stm32f10x.h
  • AFIO_EXTICR4_EXTI15_PG : stm32f10x.h
  • AFIO_MAPR_ADC1_ETRGINJ_REMAP : stm32f10x.h
  • AFIO_MAPR_ADC1_ETRGREG_REMAP : stm32f10x.h
  • AFIO_MAPR_ADC2_ETRGINJ_REMAP : stm32f10x.h
  • AFIO_MAPR_ADC2_ETRGREG_REMAP : stm32f10x.h
  • AFIO_MAPR_CAN_REMAP : stm32f10x.h
  • AFIO_MAPR_CAN_REMAP_0 : stm32f10x.h
  • AFIO_MAPR_CAN_REMAP_1 : stm32f10x.h
  • AFIO_MAPR_CAN_REMAP_REMAP1 : stm32f10x.h
  • AFIO_MAPR_CAN_REMAP_REMAP2 : stm32f10x.h
  • AFIO_MAPR_CAN_REMAP_REMAP3 : stm32f10x.h
  • AFIO_MAPR_I2C1_REMAP : stm32f10x.h
  • AFIO_MAPR_PD01_REMAP : stm32f10x.h
  • AFIO_MAPR_SPI1_REMAP : stm32f10x.h
  • AFIO_MAPR_SWJ_CFG : stm32f10x.h
  • AFIO_MAPR_SWJ_CFG_0 : stm32f10x.h
  • AFIO_MAPR_SWJ_CFG_1 : stm32f10x.h
  • AFIO_MAPR_SWJ_CFG_2 : stm32f10x.h
  • AFIO_MAPR_SWJ_CFG_DISABLE : stm32f10x.h
  • AFIO_MAPR_SWJ_CFG_JTAGDISABLE : stm32f10x.h
  • AFIO_MAPR_SWJ_CFG_NOJNTRST : stm32f10x.h
  • AFIO_MAPR_SWJ_CFG_RESET : stm32f10x.h
  • AFIO_MAPR_TIM1_REMAP : stm32f10x.h
  • AFIO_MAPR_TIM1_REMAP_0 : stm32f10x.h
  • AFIO_MAPR_TIM1_REMAP_1 : stm32f10x.h
  • AFIO_MAPR_TIM1_REMAP_FULLREMAP : stm32f10x.h
  • AFIO_MAPR_TIM1_REMAP_NOREMAP : stm32f10x.h
  • AFIO_MAPR_TIM1_REMAP_PARTIALREMAP : stm32f10x.h
  • AFIO_MAPR_TIM2_REMAP : stm32f10x.h
  • AFIO_MAPR_TIM2_REMAP_0 : stm32f10x.h
  • AFIO_MAPR_TIM2_REMAP_1 : stm32f10x.h
  • AFIO_MAPR_TIM2_REMAP_FULLREMAP : stm32f10x.h
  • AFIO_MAPR_TIM2_REMAP_NOREMAP : stm32f10x.h
  • AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 : stm32f10x.h
  • AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 : stm32f10x.h
  • AFIO_MAPR_TIM3_REMAP : stm32f10x.h
  • AFIO_MAPR_TIM3_REMAP_0 : stm32f10x.h
  • AFIO_MAPR_TIM3_REMAP_1 : stm32f10x.h
  • AFIO_MAPR_TIM3_REMAP_FULLREMAP : stm32f10x.h
  • AFIO_MAPR_TIM3_REMAP_NOREMAP : stm32f10x.h
  • AFIO_MAPR_TIM3_REMAP_PARTIALREMAP : stm32f10x.h
  • AFIO_MAPR_TIM4_REMAP : stm32f10x.h
  • AFIO_MAPR_TIM5CH4_IREMAP : stm32f10x.h
  • AFIO_MAPR_USART1_REMAP : stm32f10x.h
  • AFIO_MAPR_USART2_REMAP : stm32f10x.h
  • AFIO_MAPR_USART3_REMAP : stm32f10x.h
  • AFIO_MAPR_USART3_REMAP_0 : stm32f10x.h
  • AFIO_MAPR_USART3_REMAP_1 : stm32f10x.h
  • AFIO_MAPR_USART3_REMAP_FULLREMAP : stm32f10x.h
  • AFIO_MAPR_USART3_REMAP_NOREMAP : stm32f10x.h
  • AFIO_MAPR_USART3_REMAP_PARTIALREMAP : stm32f10x.h
  • AFIO_OFFSET : stm32f10x_gpio.c
  • AHBPERIPH_BASE : stm32f10x.h
  • AHBPrescTable : Project/STM32F10x_StdPeriph_Examples/TIM/OCActive/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/TimeBase/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/CAN/LoopBack/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/FSMC/NAND/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/FSMC/NOR/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/DMA/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/PWR/STANDBY/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/CAN/DualCAN/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/DMA_Polling/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/GPIO/IOToggle/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/PWR/PVD/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/SysTick/TimeBase/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/Smartcard/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/MultiProcessor/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/Printf/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/DMABurst/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/I2C/IOExpander/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/I2C/EEPROM/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/BKP/Backup_Data/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/DMA/FSMC/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/HalfDuplex/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/InputCapture/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/OCToggle/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/OCInactive/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/OnePulse/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Input/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/FSMC/OneNAND/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/CAN/Networking/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/CortexM3/MPU/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/I2S/Interrupt/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/Interrupt/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Output/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/6Steps/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/Polling/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/FLASH/Program/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/Synchronous/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/CortexM3/BitBand/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/BKP/Tamper/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/SPI/DMA/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/SPI/CRC/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/system_stm32f10x.c , Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/RTC/Calendar/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Template/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/PWR/STOP/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/SDIO/uSDCard/system_stm32f10x.c
  • AIRCR_VECTKEY_MASK : misc.c
  • ALL_IT : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • APB1PERIPH_BASE : stm32f10x.h
  • APB2PERIPH_BASE : stm32f10x.h
  • APBAHBPrescTable : stm32f10x_rcc.c
  • APOSTROPHE_OFF : stm32l152_eval_glass_lcd.h
  • APOSTROPHE_ON : stm32l152_eval_glass_lcd.h
  • Apostrophe_Typedef : stm32l152_eval_glass_lcd.h
  • ApplicationAddress : STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/main.c
  • ARRAY_ADDRESS_START : accesspermission.c
  • ARRAY_REGION_NUMBER : accesspermission.c
  • ARRAY_SIZE : accesspermission.c
  • ASCII12x12_Table : fonts.c
  • ASCII16x24_Table : fonts.c
  • ASCII8x12_Table : fonts.c
  • ASCII8x8_Table : fonts.c
  • ASSEMBLE_RGB : stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm32l152_eval_lcd.h , stm3210e_eval_lcd.h , stm32100b_eval_lcd.h , stm32100e_eval_lcd.h
  • assert_failed() : STM32F10x_StdPeriph_Examples/I2C/EEPROM/stm32f10x_conf.h
  • assert_param : STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/USART/HalfDuplex/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/TIM/OCActive/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/FSMC/SRAM/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/I2C/EEPROM/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/BKP/Tamper/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/PWR/PVD/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/FSMC/NOR/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/TIM/PWM_Input/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/DMA/FSMC/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/CortexM3/MPU/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/USART/Synchronous/stm32f10x_conf.h , STM32F10x_StdPeriph_Template/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/BKP/Backup_Data/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/SysTick/TimeBase/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/SPI/DMA/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/CortexM3/BitBand/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/TIM/OCInactive/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/SPI/CRC/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/USART/MultiProcessor/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/USART/DMA_Polling/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/USART/Polling/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/TIM/OnePulse/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/TIM/DMA/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/TIM/PWM_Output/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/FSMC/NAND/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/TIM/DMABurst/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/GPIO/IOToggle/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/SDIO/uSDCard/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/TIM/6Steps/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/PWR/STANDBY/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/USART/Printf/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/FSMC/OneNAND/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/FLASH/Program/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/RTC/Calendar/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/I2C/IOExpander/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_conf.h
  • ATACMD_BitNumber : stm32f10x_sdio.c
  • ATRDecodeStatus : STM32F10x_StdPeriph_Examples/USART/Smartcard/main.c
  • AUDIO_RESET_PIN : stm3210c_eval_ioe.h


STM32F10x Standard Peripherals Firmware Library: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • j
  • k
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w
  • y
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- b -

  • BackColor : stm32100b_eval_lcd.c , stm32100e_eval_lcd.c , stm3210c_eval_lcd.c , stm3210e_eval_lcd.c , stm3210b_eval_lcd.c , stm32l152_eval_lcd.c
  • Bank1_NOR2_ADDR : stm3210e_eval_fsmc_nor.c
  • BANK1_ONENAND1_ADDR : stm32100e_eval_fsmc_onenand.c
  • Bank1_SRAM3_ADDR : STM32F10x_StdPeriph_Examples/DMA/FSMC/main.c , stm32100e_eval_fsmc_sram.c , stm3210e_eval_fsmc_sram.c
  • BANK1_START_ADDRESS : STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/main.c
  • BANK1_WRITE_END_ADDR : STM32F10x_StdPeriph_Examples/FLASH/Program/main.c , STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/main.c
  • BANK1_WRITE_START_ADDR : STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/main.c , STM32F10x_StdPeriph_Examples/FLASH/Program/main.c
  • Bank2_NAND_ADDR : stm3210e_eval_fsmc_nand.c
  • BANK2_START_ADDRESS : STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/main.c
  • Bank_NAND_ADDR : stm3210e_eval_fsmc_nand.c
  • BCR_FACCEN_Set : stm32f10x_fsmc.c
  • BCR_MBKEN_Reset : stm32f10x_fsmc.c
  • BCR_MBKEN_Set : stm32f10x_fsmc.c
  • BDCR_ADDRESS : stm32f10x_rcc.c
  • BDCR_BDRST_BB : stm32f10x_rcc.c
  • BDCR_OFFSET : stm32f10x_rcc.c
  • BDCR_RTCEN_BB : stm32f10x_rcc.c
  • BDRST_BitNumber : stm32f10x_rcc.c
  • BIT_Mask : stm32f10x_wwdg.c
  • Bit_RESET : stm32f10x_gpio.h
  • Bit_SET : stm32f10x_gpio.h
  • BitAction : stm32f10x_gpio.h
  • BitReset : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • BitSet : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • BKP : stm32f10x.h
  • BKP_BASE : stm32f10x.h
  • BKP_ClearFlag() : stm32f10x_bkp.h , stm32f10x_bkp.c
  • BKP_ClearITPendingBit() : stm32f10x_bkp.h , stm32f10x_bkp.c
  • BKP_CR_TPAL : stm32f10x.h
  • BKP_CR_TPE : stm32f10x.h
  • BKP_CSR_CTE : stm32f10x.h
  • BKP_CSR_CTI : stm32f10x.h
  • BKP_CSR_TEF : stm32f10x.h
  • BKP_CSR_TIF : stm32f10x.h
  • BKP_CSR_TPIE : stm32f10x.h
  • BKP_DBG : stm32f10x_ip_dbg.c
  • BKP_DeInit() : stm32f10x_bkp.h , stm32f10x_bkp.c
  • BKP_DR1 : stm32f10x_bkp.h
  • BKP_DR10 : stm32f10x_bkp.h
  • BKP_DR10_D : stm32f10x.h
  • BKP_DR11 : stm32f10x_bkp.h
  • BKP_DR11_D : stm32f10x.h
  • BKP_DR12 : stm32f10x_bkp.h
  • BKP_DR12_D : stm32f10x.h
  • BKP_DR13 : stm32f10x_bkp.h
  • BKP_DR13_D : stm32f10x.h
  • BKP_DR14 : stm32f10x_bkp.h
  • BKP_DR14_D : stm32f10x.h
  • BKP_DR15 : stm32f10x_bkp.h
  • BKP_DR15_D : stm32f10x.h
  • BKP_DR16 : stm32f10x_bkp.h
  • BKP_DR16_D : stm32f10x.h
  • BKP_DR17 : stm32f10x_bkp.h
  • BKP_DR17_D : stm32f10x.h
  • BKP_DR18 : stm32f10x_bkp.h
  • BKP_DR18_D : stm32f10x.h
  • BKP_DR19 : stm32f10x_bkp.h
  • BKP_DR19_D : stm32f10x.h
  • BKP_DR1_D : stm32f10x.h
  • BKP_DR2 : stm32f10x_bkp.h
  • BKP_DR20 : stm32f10x_bkp.h
  • BKP_DR20_D : stm32f10x.h
  • BKP_DR21 : stm32f10x_bkp.h
  • BKP_DR21_D : stm32f10x.h
  • BKP_DR22 : stm32f10x_bkp.h
  • BKP_DR22_D : stm32f10x.h
  • BKP_DR23 : stm32f10x_bkp.h
  • BKP_DR23_D : stm32f10x.h
  • BKP_DR24 : stm32f10x_bkp.h
  • BKP_DR24_D : stm32f10x.h
  • BKP_DR25 : stm32f10x_bkp.h
  • BKP_DR25_D : stm32f10x.h
  • BKP_DR26 : stm32f10x_bkp.h
  • BKP_DR26_D : stm32f10x.h
  • BKP_DR27 : stm32f10x_bkp.h
  • BKP_DR27_D : stm32f10x.h
  • BKP_DR28 : stm32f10x_bkp.h
  • BKP_DR28_D : stm32f10x.h
  • BKP_DR29 : stm32f10x_bkp.h
  • BKP_DR29_D : stm32f10x.h
  • BKP_DR2_D : stm32f10x.h
  • BKP_DR3 : stm32f10x_bkp.h
  • BKP_DR30 : stm32f10x_bkp.h
  • BKP_DR30_D : stm32f10x.h
  • BKP_DR31 : stm32f10x_bkp.h
  • BKP_DR31_D : stm32f10x.h
  • BKP_DR32 : stm32f10x_bkp.h
  • BKP_DR32_D : stm32f10x.h
  • BKP_DR33 : stm32f10x_bkp.h
  • BKP_DR33_D : stm32f10x.h
  • BKP_DR34 : stm32f10x_bkp.h
  • BKP_DR34_D : stm32f10x.h
  • BKP_DR35 : stm32f10x_bkp.h
  • BKP_DR35_D : stm32f10x.h
  • BKP_DR36 : stm32f10x_bkp.h
  • BKP_DR36_D : stm32f10x.h
  • BKP_DR37 : stm32f10x_bkp.h
  • BKP_DR37_D : stm32f10x.h
  • BKP_DR38 : stm32f10x_bkp.h
  • BKP_DR38_D : stm32f10x.h
  • BKP_DR39 : stm32f10x_bkp.h
  • BKP_DR39_D : stm32f10x.h
  • BKP_DR3_D : stm32f10x.h
  • BKP_DR4 : stm32f10x_bkp.h
  • BKP_DR40 : stm32f10x_bkp.h
  • BKP_DR40_D : stm32f10x.h
  • BKP_DR41 : stm32f10x_bkp.h
  • BKP_DR41_D : stm32f10x.h
  • BKP_DR42 : stm32f10x_bkp.h
  • BKP_DR42_D : stm32f10x.h
  • BKP_DR4_D : stm32f10x.h
  • BKP_DR5 : stm32f10x_bkp.h
  • BKP_DR5_D : stm32f10x.h
  • BKP_DR6 : stm32f10x_bkp.h
  • BKP_DR6_D : stm32f10x.h
  • BKP_DR7 : stm32f10x_bkp.h
  • BKP_DR7_D : stm32f10x.h
  • BKP_DR8 : stm32f10x_bkp.h
  • BKP_DR8_D : stm32f10x.h
  • BKP_DR9 : stm32f10x_bkp.h
  • BKP_DR9_D : stm32f10x.h
  • BKP_DR_NUMBER : STM32F10x_StdPeriph_Examples/BKP/Backup_Data/main.c , STM32F10x_StdPeriph_Examples/BKP/Tamper/main.c
  • BKP_GetFlagStatus() : stm32f10x_bkp.h , stm32f10x_bkp.c
  • BKP_GetITStatus() : stm32f10x_bkp.h , stm32f10x_bkp.c
  • BKP_ITConfig() : stm32f10x_bkp.h , stm32f10x_bkp.c
  • BKP_OFFSET : stm32f10x_bkp.c
  • BKP_ReadBackupRegister() : stm32f10x_bkp.h , stm32f10x_bkp.c
  • BKP_RTCCR_ASOE : stm32f10x.h
  • BKP_RTCCR_ASOS : stm32f10x.h
  • BKP_RTCCR_CAL : stm32f10x.h
  • BKP_RTCCR_CCO : stm32f10x.h
  • BKP_RTCOutputConfig() : stm32f10x_bkp.h , stm32f10x_bkp.c
  • BKP_RTCOutputSource_Alarm : stm32f10x_bkp.h
  • BKP_RTCOutputSource_CalibClock : stm32f10x_bkp.h
  • BKP_RTCOutputSource_None : stm32f10x_bkp.h
  • BKP_RTCOutputSource_Second : stm32f10x_bkp.h
  • BKP_SetRTCCalibrationValue() : stm32f10x_bkp.h , stm32f10x_bkp.c
  • BKP_TamperPinCmd() : stm32f10x_bkp.h , stm32f10x_bkp.c
  • BKP_TamperPinLevel_High : stm32f10x_bkp.h
  • BKP_TamperPinLevel_Low : stm32f10x_bkp.h
  • BKP_TamperPinLevelConfig() : stm32f10x_bkp.h , stm32f10x_bkp.c
  • BKP_WriteBackupRegister() : stm32f10x_bkp.h , stm32f10x_bkp.c
  • BKPDataReg : STM32F10x_StdPeriph_Examples/BKP/Backup_Data/main.c , STM32F10x_StdPeriph_Examples/BKP/Tamper/main.c
  • Black : stm32_eval.h
  • BLOCK_SIZE : STM32F10x_StdPeriph_Examples/SDIO/uSDCard/main.c
  • BlockErase_Timeout : stm3210e_eval_fsmc_nor.c
  • Blue : stm32_eval.h
  • Blue2 : stm32_eval.h
  • Buffer_Block_Rx : STM32F10x_StdPeriph_Examples/SDIO/uSDCard/main.c
  • Buffer_Block_Tx : STM32F10x_StdPeriph_Examples/SDIO/uSDCard/main.c
  • Buffer_MultiBlock_Rx : STM32F10x_StdPeriph_Examples/SDIO/uSDCard/main.c
  • Buffer_MultiBlock_Tx : STM32F10x_StdPeriph_Examples/SDIO/uSDCard/main.c
  • BUFFER_SIZE : STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/main.c , STM32F10x_StdPeriph_Examples/FSMC/NAND/main.c , STM32F10x_StdPeriph_Examples/FSMC/NOR/main.c , STM32F10x_StdPeriph_Examples/FSMC/SRAM/main.c
  • BUFFER_SIZE1 : STM32F10x_StdPeriph_Examples/I2C/EEPROM/main.c
  • BUFFER_SIZE2 : STM32F10x_StdPeriph_Examples/I2C/EEPROM/main.c
  • Buffercmp() : STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/main.c , STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/main.c , STM32F10x_StdPeriph_Examples/DMA/FSMC/main.c , STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/main.c , STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/main.c , STM32F10x_StdPeriph_Examples/I2C/EEPROM/main.c , STM32F10x_StdPeriph_Examples/I2S/Interrupt/main.c , STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/main.c , STM32F10x_StdPeriph_Examples/SDIO/uSDCard/main.c , STM32F10x_StdPeriph_Examples/SPI/CRC/main.c , STM32F10x_StdPeriph_Examples/SPI/DMA/main.c , STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/main.c , STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/main.c , STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/main.c , STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/main.c , STM32F10x_StdPeriph_Examples/USART/DMA_Polling/main.c , STM32F10x_StdPeriph_Examples/USART/HalfDuplex/main.c , STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c , STM32F10x_StdPeriph_Examples/USART/Polling/main.c , STM32F10x_StdPeriph_Examples/USART/Synchronous/main.c
  • Buffercmp16() : STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/main.c
  • Buffercmp24bits() : STM32F10x_StdPeriph_Examples/I2S/Interrupt/main.c
  • BufferCount : stm32100b_eval_cec.c , stm32100e_eval_cec.c
  • BufferPointer : stm32100b_eval_cec.c , stm32100e_eval_cec.c
  • BufferSize : STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/main.c , STM32F10x_StdPeriph_Examples/DMA/FSMC/main.c , STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/main.c , STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/main.c , STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/main.c , STM32F10x_StdPeriph_Examples/SPI/CRC/main.c , STM32F10x_StdPeriph_Examples/SPI/DMA/main.c , STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/main.c , STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/main.c , STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/main.c
  • BusFault_Handler() : STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Synchronous/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CortexM3/MPU/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CortexM3/BitBand/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/FSMC/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/FSMC/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/BKP/Tamper/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FLASH/Program/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/DMABurst/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/NAND/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/NOR/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/NOR/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SDIO/uSDCard/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/6Steps/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/OneNAND/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/SRAM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/SRAM/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/6Steps/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/OneNAND/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/HalfDuplex/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/HalfDuplex/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2C/EEPROM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2C/EEPROM/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/DMA_Polling/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/DMA_Polling/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SysTick/TimeBase/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/MultiProcessor/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/MultiProcessor/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/DMABurst/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SPI/CRC/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/PWR/PVD/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Printf/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Printf/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_it.c , STM32F10x_StdPeriph_Template/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/RTC/Calendar/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SDIO/uSDCard/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/CRC/stm32f10x_it.h , STM32F10x_StdPeriph_Template/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Polling/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SPI/DMA/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/PWR/PVD/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/PWR/STANDBY/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/PWR/STANDBY/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/RTC/Calendar/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Synchronous/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/DMA/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SysTick/TimeBase/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/DMA/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/DMA/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/OnePulse/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/PWM_Input/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2C/IOExpander/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2C/IOExpander/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CortexM3/MPU/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CortexM3/BitBand/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/OCActive/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/PWM_Output/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/BKP/Tamper/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/BKP/Backup_Data/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/BKP/Backup_Data/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FLASH/Program/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/NAND/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Polling/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/GPIO/IOToggle/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/GPIO/IOToggle/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/OCActive/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/PWM_Input/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/PWM_Output/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/OCInactive/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/OCInactive/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/OnePulse/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_it.c
  • BusFault_IRQn : stm32f10x.h
  • BUTTON_CLK : stm3210c_eval.c , stm32l152_eval.c , stm32100e_eval.c , stm3210b_eval.c , stm3210e_eval.c , stm32100b_eval.c
  • Button_DOWN : stm32_eval.h
  • BUTTON_DOWN : stm32_eval.h
  • BUTTON_EXTI_LINE : stm32l152_eval.c , stm3210e_eval.c , stm3210b_eval.c , stm32100e_eval.c , stm3210c_eval.c , stm32100b_eval.c
  • BUTTON_IRQn : stm32100b_eval.c , stm3210b_eval.c , stm32l152_eval.c , stm3210e_eval.c , stm32100e_eval.c , stm3210c_eval.c
  • Button_KEY : stm32_eval.h
  • BUTTON_KEY : stm32_eval.h
  • Button_LEFT : stm32_eval.h
  • BUTTON_LEFT : stm32_eval.h
  • BUTTON_MODE_EXTI : stm32_eval.h
  • BUTTON_MODE_GPIO : stm32_eval.h
  • Button_Mode_TypeDef : stm32_eval.h
  • BUTTON_PIN : stm3210c_eval.c , stm32100b_eval.c , stm3210e_eval.c , stm32l152_eval.c , stm3210b_eval.c , stm32100e_eval.c
  • BUTTON_PIN_SOURCE : stm3210b_eval.c , stm3210e_eval.c , stm3210c_eval.c , stm32l152_eval.c , stm32100b_eval.c , stm32100e_eval.c
  • BUTTON_PORT : stm32100b_eval.c , stm32100e_eval.c , stm32l152_eval.c , stm3210e_eval.c , stm3210b_eval.c , stm3210c_eval.c
  • BUTTON_PORT_SOURCE : stm32100b_eval.c , stm32l152_eval.c , stm32100e_eval.c , stm3210e_eval.c , stm3210c_eval.c , stm3210b_eval.c
  • BUTTON_RIGHT : stm32_eval.h
  • Button_RIGHT : stm32_eval.h
  • BUTTON_SEL : stm32_eval.h
  • Button_SEL : stm32_eval.h
  • BUTTON_TAMPER : stm32_eval.h
  • Button_TAMPER : stm32_eval.h
  • Button_TypeDef : stm32_eval.h
  • Button_UP : stm32_eval.h
  • BUTTON_UP : stm32_eval.h
  • BUTTON_WAKEUP : stm32_eval.h
  • Button_WAKEUP : stm32_eval.h
  • ButtonMode_TypeDef : stm32_eval.h
  • BUTTONn : stm3210e_eval.h , stm32l152_eval.h , stm3210b_eval.h , stm32100b_eval.h , stm3210c_eval.h , stm32100e_eval.h
  • ByteNumber : STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/main.c , STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.c


STM32F10x Standard Peripherals Firmware Library: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
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  • c
  • d
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  • f
  • g
  • h
  • i
  • j
  • k
  • l
  • m
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- c -

  • CAN1 : stm32f10x.h
  • CAN1_BASE : stm32f10x.h
  • CAN1_DBG : stm32f10x_ip_dbg.c
  • CAN1_RX0_IRQHandler() : STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_it.h
  • CAN2 : stm32f10x.h
  • CAN2_BASE : stm32f10x.h
  • CAN2_RX0_IRQHandler() : STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_it.h
  • CAN_BAUDRATE : STM32F10x_StdPeriph_Examples/CAN/DualCAN/main.c
  • CAN_BS1_10tq : stm32f10x_can.h
  • CAN_BS1_11tq : stm32f10x_can.h
  • CAN_BS1_12tq : stm32f10x_can.h
  • CAN_BS1_13tq : stm32f10x_can.h
  • CAN_BS1_14tq : stm32f10x_can.h
  • CAN_BS1_15tq : stm32f10x_can.h
  • CAN_BS1_16tq : stm32f10x_can.h
  • CAN_BS1_1tq : stm32f10x_can.h
  • CAN_BS1_2tq : stm32f10x_can.h
  • CAN_BS1_3tq : stm32f10x_can.h
  • CAN_BS1_4tq : stm32f10x_can.h
  • CAN_BS1_5tq : stm32f10x_can.h
  • CAN_BS1_6tq : stm32f10x_can.h
  • CAN_BS1_7tq : stm32f10x_can.h
  • CAN_BS1_8tq : stm32f10x_can.h
  • CAN_BS1_9tq : stm32f10x_can.h
  • CAN_BS2_1tq : stm32f10x_can.h
  • CAN_BS2_2tq : stm32f10x_can.h
  • CAN_BS2_3tq : stm32f10x_can.h
  • CAN_BS2_4tq : stm32f10x_can.h
  • CAN_BS2_5tq : stm32f10x_can.h
  • CAN_BS2_6tq : stm32f10x_can.h
  • CAN_BS2_7tq : stm32f10x_can.h
  • CAN_BS2_8tq : stm32f10x_can.h
  • CAN_BTR_BRP : stm32f10x.h
  • CAN_BTR_LBKM : stm32f10x.h
  • CAN_BTR_SILM : stm32f10x.h
  • CAN_BTR_SJW : stm32f10x.h
  • CAN_BTR_TS1 : stm32f10x.h
  • CAN_BTR_TS2 : stm32f10x.h
  • CAN_CancelTransmit() : stm32f10x_can.h , stm32f10x_can.c
  • CAN_ClearFlag() : stm32f10x_can.h , stm32f10x_can.c
  • CAN_ClearITPendingBit() : stm32f10x_can.h , stm32f10x_can.c
  • CAN_Config() : STM32F10x_StdPeriph_Examples/CAN/DualCAN/main.c , STM32F10x_StdPeriph_Examples/CAN/Networking/main.c
  • CAN_DBGFreeze() : stm32f10x_can.h , stm32f10x_can.c
  • CAN_DeInit() : stm32f10x_can.h , stm32f10x_can.c
  • CAN_ErrorCode_ACKErr : stm32f10x_can.h
  • CAN_ErrorCode_BitDominantErr : stm32f10x_can.h
  • CAN_ErrorCode_BitRecessiveErr : stm32f10x_can.h
  • CAN_ErrorCode_CRCErr : stm32f10x_can.h
  • CAN_ErrorCode_FormErr : stm32f10x_can.h
  • CAN_ErrorCode_NoErr : stm32f10x_can.h
  • CAN_ErrorCode_SoftwareSetErr : stm32f10x_can.h
  • CAN_ErrorCode_StuffErr : stm32f10x_can.h
  • CAN_ESR_BOFF : stm32f10x.h
  • CAN_ESR_EPVF : stm32f10x.h
  • CAN_ESR_EWGF : stm32f10x.h
  • CAN_ESR_LEC : stm32f10x.h
  • CAN_ESR_LEC_0 : stm32f10x.h
  • CAN_ESR_LEC_1 : stm32f10x.h
  • CAN_ESR_LEC_2 : stm32f10x.h
  • CAN_ESR_REC : stm32f10x.h
  • CAN_ESR_TEC : stm32f10x.h
  • CAN_F0R1_FB0 : stm32f10x.h
  • CAN_F0R1_FB1 : stm32f10x.h
  • CAN_F0R1_FB10 : stm32f10x.h
  • CAN_F0R1_FB11 : stm32f10x.h
  • CAN_F0R1_FB12 : stm32f10x.h
  • CAN_F0R1_FB13 : stm32f10x.h
  • CAN_F0R1_FB14 : stm32f10x.h
  • CAN_F0R1_FB15 : stm32f10x.h
  • CAN_F0R1_FB16 : stm32f10x.h
  • CAN_F0R1_FB17 : stm32f10x.h
  • CAN_F0R1_FB18 : stm32f10x.h
  • CAN_F0R1_FB19 : stm32f10x.h
  • CAN_F0R1_FB2 : stm32f10x.h
  • CAN_F0R1_FB20 : stm32f10x.h
  • CAN_F0R1_FB21 : stm32f10x.h
  • CAN_F0R1_FB22 : stm32f10x.h
  • CAN_F0R1_FB23 : stm32f10x.h
  • CAN_F0R1_FB24 : stm32f10x.h
  • CAN_F0R1_FB25 : stm32f10x.h
  • CAN_F0R1_FB26 : stm32f10x.h
  • CAN_F0R1_FB27 : stm32f10x.h
  • CAN_F0R1_FB28 : stm32f10x.h
  • CAN_F0R1_FB29 : stm32f10x.h
  • CAN_F0R1_FB3 : stm32f10x.h
  • CAN_F0R1_FB30 : stm32f10x.h
  • CAN_F0R1_FB31 : stm32f10x.h
  • CAN_F0R1_FB4 : stm32f10x.h
  • CAN_F0R1_FB5 : stm32f10x.h
  • CAN_F0R1_FB6 : stm32f10x.h
  • CAN_F0R1_FB7 : stm32f10x.h
  • CAN_F0R1_FB8 : stm32f10x.h
  • CAN_F0R1_FB9 : stm32f10x.h
  • CAN_F0R2_FB0 : stm32f10x.h
  • CAN_F0R2_FB1 : stm32f10x.h
  • CAN_F0R2_FB10 : stm32f10x.h
  • CAN_F0R2_FB11 : stm32f10x.h
  • CAN_F0R2_FB12 : stm32f10x.h
  • CAN_F0R2_FB13 : stm32f10x.h
  • CAN_F0R2_FB14 : stm32f10x.h
  • CAN_F0R2_FB15 : stm32f10x.h
  • CAN_F0R2_FB16 : stm32f10x.h
  • CAN_F0R2_FB17 : stm32f10x.h
  • CAN_F0R2_FB18 : stm32f10x.h
  • CAN_F0R2_FB19 : stm32f10x.h
  • CAN_F0R2_FB2 : stm32f10x.h
  • CAN_F0R2_FB20 : stm32f10x.h
  • CAN_F0R2_FB21 : stm32f10x.h
  • CAN_F0R2_FB22 : stm32f10x.h
  • CAN_F0R2_FB23 : stm32f10x.h
  • CAN_F0R2_FB24 : stm32f10x.h
  • CAN_F0R2_FB25 : stm32f10x.h
  • CAN_F0R2_FB26 : stm32f10x.h
  • CAN_F0R2_FB27 : stm32f10x.h
  • CAN_F0R2_FB28 : stm32f10x.h
  • CAN_F0R2_FB29 : stm32f10x.h
  • CAN_F0R2_FB3 : stm32f10x.h
  • CAN_F0R2_FB30 : stm32f10x.h
  • CAN_F0R2_FB31 : stm32f10x.h
  • CAN_F0R2_FB4 : stm32f10x.h
  • CAN_F0R2_FB5 : stm32f10x.h
  • CAN_F0R2_FB6 : stm32f10x.h
  • CAN_F0R2_FB7 : stm32f10x.h
  • CAN_F0R2_FB8 : stm32f10x.h
  • CAN_F0R2_FB9 : stm32f10x.h
  • CAN_F10R1_FB0 : stm32f10x.h
  • CAN_F10R1_FB1 : stm32f10x.h
  • CAN_F10R1_FB10 : stm32f10x.h
  • CAN_F10R1_FB11 : stm32f10x.h
  • CAN_F10R1_FB12 : stm32f10x.h
  • CAN_F10R1_FB13 : stm32f10x.h
  • CAN_F10R1_FB14 : stm32f10x.h
  • CAN_F10R1_FB15 : stm32f10x.h
  • CAN_F10R1_FB16 : stm32f10x.h
  • CAN_F10R1_FB17 : stm32f10x.h
  • CAN_F10R1_FB18 : stm32f10x.h
  • CAN_F10R1_FB19 : stm32f10x.h
  • CAN_F10R1_FB2 : stm32f10x.h
  • CAN_F10R1_FB20 : stm32f10x.h
  • CAN_F10R1_FB21 : stm32f10x.h
  • CAN_F10R1_FB22 : stm32f10x.h
  • CAN_F10R1_FB23 : stm32f10x.h
  • CAN_F10R1_FB24 : stm32f10x.h
  • CAN_F10R1_FB25 : stm32f10x.h
  • CAN_F10R1_FB26 : stm32f10x.h
  • CAN_F10R1_FB27 : stm32f10x.h
  • CAN_F10R1_FB28 : stm32f10x.h
  • CAN_F10R1_FB29 : stm32f10x.h
  • CAN_F10R1_FB3 : stm32f10x.h
  • CAN_F10R1_FB30 : stm32f10x.h
  • CAN_F10R1_FB31 : stm32f10x.h
  • CAN_F10R1_FB4 : stm32f10x.h
  • CAN_F10R1_FB5 : stm32f10x.h
  • CAN_F10R1_FB6 : stm32f10x.h
  • CAN_F10R1_FB7 : stm32f10x.h
  • CAN_F10R1_FB8 : stm32f10x.h
  • CAN_F10R1_FB9 : stm32f10x.h
  • CAN_F10R2_FB0 : stm32f10x.h
  • CAN_F10R2_FB1 : stm32f10x.h
  • CAN_F10R2_FB10 : stm32f10x.h
  • CAN_F10R2_FB11 : stm32f10x.h
  • CAN_F10R2_FB12 : stm32f10x.h
  • CAN_F10R2_FB13 : stm32f10x.h
  • CAN_F10R2_FB14 : stm32f10x.h
  • CAN_F10R2_FB15 : stm32f10x.h
  • CAN_F10R2_FB16 : stm32f10x.h
  • CAN_F10R2_FB17 : stm32f10x.h
  • CAN_F10R2_FB18 : stm32f10x.h
  • CAN_F10R2_FB19 : stm32f10x.h
  • CAN_F10R2_FB2 : stm32f10x.h
  • CAN_F10R2_FB20 : stm32f10x.h
  • CAN_F10R2_FB21 : stm32f10x.h
  • CAN_F10R2_FB22 : stm32f10x.h
  • CAN_F10R2_FB23 : stm32f10x.h
  • CAN_F10R2_FB24 : stm32f10x.h
  • CAN_F10R2_FB25 : stm32f10x.h
  • CAN_F10R2_FB26 : stm32f10x.h
  • CAN_F10R2_FB27 : stm32f10x.h
  • CAN_F10R2_FB28 : stm32f10x.h
  • CAN_F10R2_FB29 : stm32f10x.h
  • CAN_F10R2_FB3 : stm32f10x.h
  • CAN_F10R2_FB30 : stm32f10x.h
  • CAN_F10R2_FB31 : stm32f10x.h
  • CAN_F10R2_FB4 : stm32f10x.h
  • CAN_F10R2_FB5 : stm32f10x.h
  • CAN_F10R2_FB6 : stm32f10x.h
  • CAN_F10R2_FB7 : stm32f10x.h
  • CAN_F10R2_FB8 : stm32f10x.h
  • CAN_F10R2_FB9 : stm32f10x.h
  • CAN_F11R1_FB0 : stm32f10x.h
  • CAN_F11R1_FB1 : stm32f10x.h
  • CAN_F11R1_FB10 : stm32f10x.h
  • CAN_F11R1_FB11 : stm32f10x.h
  • CAN_F11R1_FB12 : stm32f10x.h
  • CAN_F11R1_FB13 : stm32f10x.h
  • CAN_F11R1_FB14 : stm32f10x.h
  • CAN_F11R1_FB15 : stm32f10x.h
  • CAN_F11R1_FB16 : stm32f10x.h
  • CAN_F11R1_FB17 : stm32f10x.h
  • CAN_F11R1_FB18 : stm32f10x.h
  • CAN_F11R1_FB19 : stm32f10x.h
  • CAN_F11R1_FB2 : stm32f10x.h
  • CAN_F11R1_FB20 : stm32f10x.h
  • CAN_F11R1_FB21 : stm32f10x.h
  • CAN_F11R1_FB22 : stm32f10x.h
  • CAN_F11R1_FB23 : stm32f10x.h
  • CAN_F11R1_FB24 : stm32f10x.h
  • CAN_F11R1_FB25 : stm32f10x.h
  • CAN_F11R1_FB26 : stm32f10x.h
  • CAN_F11R1_FB27 : stm32f10x.h
  • CAN_F11R1_FB28 : stm32f10x.h
  • CAN_F11R1_FB29 : stm32f10x.h
  • CAN_F11R1_FB3 : stm32f10x.h
  • CAN_F11R1_FB30 : stm32f10x.h
  • CAN_F11R1_FB31 : stm32f10x.h
  • CAN_F11R1_FB4 : stm32f10x.h
  • CAN_F11R1_FB5 : stm32f10x.h
  • CAN_F11R1_FB6 : stm32f10x.h
  • CAN_F11R1_FB7 : stm32f10x.h
  • CAN_F11R1_FB8 : stm32f10x.h
  • CAN_F11R1_FB9 : stm32f10x.h
  • CAN_F11R2_FB0 : stm32f10x.h
  • CAN_F11R2_FB1 : stm32f10x.h
  • CAN_F11R2_FB10 : stm32f10x.h
  • CAN_F11R2_FB11 : stm32f10x.h
  • CAN_F11R2_FB12 : stm32f10x.h
  • CAN_F11R2_FB13 : stm32f10x.h
  • CAN_F11R2_FB14 : stm32f10x.h
  • CAN_F11R2_FB15 : stm32f10x.h
  • CAN_F11R2_FB16 : stm32f10x.h
  • CAN_F11R2_FB17 : stm32f10x.h
  • CAN_F11R2_FB18 : stm32f10x.h
  • CAN_F11R2_FB19 : stm32f10x.h
  • CAN_F11R2_FB2 : stm32f10x.h
  • CAN_F11R2_FB20 : stm32f10x.h
  • CAN_F11R2_FB21 : stm32f10x.h
  • CAN_F11R2_FB22 : stm32f10x.h
  • CAN_F11R2_FB23 : stm32f10x.h
  • CAN_F11R2_FB24 : stm32f10x.h
  • CAN_F11R2_FB25 : stm32f10x.h
  • CAN_F11R2_FB26 : stm32f10x.h
  • CAN_F11R2_FB27 : stm32f10x.h
  • CAN_F11R2_FB28 : stm32f10x.h
  • CAN_F11R2_FB29 : stm32f10x.h
  • CAN_F11R2_FB3 : stm32f10x.h
  • CAN_F11R2_FB30 : stm32f10x.h
  • CAN_F11R2_FB31 : stm32f10x.h
  • CAN_F11R2_FB4 : stm32f10x.h
  • CAN_F11R2_FB5 : stm32f10x.h
  • CAN_F11R2_FB6 : stm32f10x.h
  • CAN_F11R2_FB7 : stm32f10x.h
  • CAN_F11R2_FB8 : stm32f10x.h
  • CAN_F11R2_FB9 : stm32f10x.h
  • CAN_F12R1_FB0 : stm32f10x.h
  • CAN_F12R1_FB1 : stm32f10x.h
  • CAN_F12R1_FB10 : stm32f10x.h
  • CAN_F12R1_FB11 : stm32f10x.h
  • CAN_F12R1_FB12 : stm32f10x.h
  • CAN_F12R1_FB13 : stm32f10x.h
  • CAN_F12R1_FB14 : stm32f10x.h
  • CAN_F12R1_FB15 : stm32f10x.h
  • CAN_F12R1_FB16 : stm32f10x.h
  • CAN_F12R1_FB17 : stm32f10x.h
  • CAN_F12R1_FB18 : stm32f10x.h
  • CAN_F12R1_FB19 : stm32f10x.h
  • CAN_F12R1_FB2 : stm32f10x.h
  • CAN_F12R1_FB20 : stm32f10x.h
  • CAN_F12R1_FB21 : stm32f10x.h
  • CAN_F12R1_FB22 : stm32f10x.h
  • CAN_F12R1_FB23 : stm32f10x.h
  • CAN_F12R1_FB24 : stm32f10x.h
  • CAN_F12R1_FB25 : stm32f10x.h
  • CAN_F12R1_FB26 : stm32f10x.h
  • CAN_F12R1_FB27 : stm32f10x.h
  • CAN_F12R1_FB28 : stm32f10x.h
  • CAN_F12R1_FB29 : stm32f10x.h
  • CAN_F12R1_FB3 : stm32f10x.h
  • CAN_F12R1_FB30 : stm32f10x.h
  • CAN_F12R1_FB31 : stm32f10x.h
  • CAN_F12R1_FB4 : stm32f10x.h
  • CAN_F12R1_FB5 : stm32f10x.h
  • CAN_F12R1_FB6 : stm32f10x.h
  • CAN_F12R1_FB7 : stm32f10x.h
  • CAN_F12R1_FB8 : stm32f10x.h
  • CAN_F12R1_FB9 : stm32f10x.h
  • CAN_F12R2_FB0 : stm32f10x.h
  • CAN_F12R2_FB1 : stm32f10x.h
  • CAN_F12R2_FB10 : stm32f10x.h
  • CAN_F12R2_FB11 : stm32f10x.h
  • CAN_F12R2_FB12 : stm32f10x.h
  • CAN_F12R2_FB13 : stm32f10x.h
  • CAN_F12R2_FB14 : stm32f10x.h
  • CAN_F12R2_FB15 : stm32f10x.h
  • CAN_F12R2_FB16 : stm32f10x.h
  • CAN_F12R2_FB17 : stm32f10x.h
  • CAN_F12R2_FB18 : stm32f10x.h
  • CAN_F12R2_FB19 : stm32f10x.h
  • CAN_F12R2_FB2 : stm32f10x.h
  • CAN_F12R2_FB20 : stm32f10x.h
  • CAN_F12R2_FB21 : stm32f10x.h
  • CAN_F12R2_FB22 : stm32f10x.h
  • CAN_F12R2_FB23 : stm32f10x.h
  • CAN_F12R2_FB24 : stm32f10x.h
  • CAN_F12R2_FB25 : stm32f10x.h
  • CAN_F12R2_FB26 : stm32f10x.h
  • CAN_F12R2_FB27 : stm32f10x.h
  • CAN_F12R2_FB28 : stm32f10x.h
  • CAN_F12R2_FB29 : stm32f10x.h
  • CAN_F12R2_FB3 : stm32f10x.h
  • CAN_F12R2_FB30 : stm32f10x.h
  • CAN_F12R2_FB31 : stm32f10x.h
  • CAN_F12R2_FB4 : stm32f10x.h
  • CAN_F12R2_FB5 : stm32f10x.h
  • CAN_F12R2_FB6 : stm32f10x.h
  • CAN_F12R2_FB7 : stm32f10x.h
  • CAN_F12R2_FB8 : stm32f10x.h
  • CAN_F12R2_FB9 : stm32f10x.h
  • CAN_F13R1_FB0 : stm32f10x.h
  • CAN_F13R1_FB1 : stm32f10x.h
  • CAN_F13R1_FB10 : stm32f10x.h
  • CAN_F13R1_FB11 : stm32f10x.h
  • CAN_F13R1_FB12 : stm32f10x.h
  • CAN_F13R1_FB13 : stm32f10x.h
  • CAN_F13R1_FB14 : stm32f10x.h
  • CAN_F13R1_FB15 : stm32f10x.h
  • CAN_F13R1_FB16 : stm32f10x.h
  • CAN_F13R1_FB17 : stm32f10x.h
  • CAN_F13R1_FB18 : stm32f10x.h
  • CAN_F13R1_FB19 : stm32f10x.h
  • CAN_F13R1_FB2 : stm32f10x.h
  • CAN_F13R1_FB20 : stm32f10x.h
  • CAN_F13R1_FB21 : stm32f10x.h
  • CAN_F13R1_FB22 : stm32f10x.h
  • CAN_F13R1_FB23 : stm32f10x.h
  • CAN_F13R1_FB24 : stm32f10x.h
  • CAN_F13R1_FB25 : stm32f10x.h
  • CAN_F13R1_FB26 : stm32f10x.h
  • CAN_F13R1_FB27 : stm32f10x.h
  • CAN_F13R1_FB28 : stm32f10x.h
  • CAN_F13R1_FB29 : stm32f10x.h
  • CAN_F13R1_FB3 : stm32f10x.h
  • CAN_F13R1_FB30 : stm32f10x.h
  • CAN_F13R1_FB31 : stm32f10x.h
  • CAN_F13R1_FB4 : stm32f10x.h
  • CAN_F13R1_FB5 : stm32f10x.h
  • CAN_F13R1_FB6 : stm32f10x.h
  • CAN_F13R1_FB7 : stm32f10x.h
  • CAN_F13R1_FB8 : stm32f10x.h
  • CAN_F13R1_FB9 : stm32f10x.h
  • CAN_F13R2_FB0 : stm32f10x.h
  • CAN_F13R2_FB1 : stm32f10x.h
  • CAN_F13R2_FB10 : stm32f10x.h
  • CAN_F13R2_FB11 : stm32f10x.h
  • CAN_F13R2_FB12 : stm32f10x.h
  • CAN_F13R2_FB13 : stm32f10x.h
  • CAN_F13R2_FB14 : stm32f10x.h
  • CAN_F13R2_FB15 : stm32f10x.h
  • CAN_F13R2_FB16 : stm32f10x.h
  • CAN_F13R2_FB17 : stm32f10x.h
  • CAN_F13R2_FB18 : stm32f10x.h
  • CAN_F13R2_FB19 : stm32f10x.h
  • CAN_F13R2_FB2 : stm32f10x.h
  • CAN_F13R2_FB20 : stm32f10x.h
  • CAN_F13R2_FB21 : stm32f10x.h
  • CAN_F13R2_FB22 : stm32f10x.h
  • CAN_F13R2_FB23 : stm32f10x.h
  • CAN_F13R2_FB24 : stm32f10x.h
  • CAN_F13R2_FB25 : stm32f10x.h
  • CAN_F13R2_FB26 : stm32f10x.h
  • CAN_F13R2_FB27 : stm32f10x.h
  • CAN_F13R2_FB28 : stm32f10x.h
  • CAN_F13R2_FB29 : stm32f10x.h
  • CAN_F13R2_FB3 : stm32f10x.h
  • CAN_F13R2_FB30 : stm32f10x.h
  • CAN_F13R2_FB31 : stm32f10x.h
  • CAN_F13R2_FB4 : stm32f10x.h
  • CAN_F13R2_FB5 : stm32f10x.h
  • CAN_F13R2_FB6 : stm32f10x.h
  • CAN_F13R2_FB7 : stm32f10x.h
  • CAN_F13R2_FB8 : stm32f10x.h
  • CAN_F13R2_FB9 : stm32f10x.h
  • CAN_F1R1_FB0 : stm32f10x.h
  • CAN_F1R1_FB1 : stm32f10x.h
  • CAN_F1R1_FB10 : stm32f10x.h
  • CAN_F1R1_FB11 : stm32f10x.h
  • CAN_F1R1_FB12 : stm32f10x.h
  • CAN_F1R1_FB13 : stm32f10x.h
  • CAN_F1R1_FB14 : stm32f10x.h
  • CAN_F1R1_FB15 : stm32f10x.h
  • CAN_F1R1_FB16 : stm32f10x.h
  • CAN_F1R1_FB17 : stm32f10x.h
  • CAN_F1R1_FB18 : stm32f10x.h
  • CAN_F1R1_FB19 : stm32f10x.h
  • CAN_F1R1_FB2 : stm32f10x.h
  • CAN_F1R1_FB20 : stm32f10x.h
  • CAN_F1R1_FB21 : stm32f10x.h
  • CAN_F1R1_FB22 : stm32f10x.h
  • CAN_F1R1_FB23 : stm32f10x.h
  • CAN_F1R1_FB24 : stm32f10x.h
  • CAN_F1R1_FB25 : stm32f10x.h
  • CAN_F1R1_FB26 : stm32f10x.h
  • CAN_F1R1_FB27 : stm32f10x.h
  • CAN_F1R1_FB28 : stm32f10x.h
  • CAN_F1R1_FB29 : stm32f10x.h
  • CAN_F1R1_FB3 : stm32f10x.h
  • CAN_F1R1_FB30 : stm32f10x.h
  • CAN_F1R1_FB31 : stm32f10x.h
  • CAN_F1R1_FB4 : stm32f10x.h
  • CAN_F1R1_FB5 : stm32f10x.h
  • CAN_F1R1_FB6 : stm32f10x.h
  • CAN_F1R1_FB7 : stm32f10x.h
  • CAN_F1R1_FB8 : stm32f10x.h
  • CAN_F1R1_FB9 : stm32f10x.h
  • CAN_F1R2_FB0 : stm32f10x.h
  • CAN_F1R2_FB1 : stm32f10x.h
  • CAN_F1R2_FB10 : stm32f10x.h
  • CAN_F1R2_FB11 : stm32f10x.h
  • CAN_F1R2_FB12 : stm32f10x.h
  • CAN_F1R2_FB13 : stm32f10x.h
  • CAN_F1R2_FB14 : stm32f10x.h
  • CAN_F1R2_FB15 : stm32f10x.h
  • CAN_F1R2_FB16 : stm32f10x.h
  • CAN_F1R2_FB17 : stm32f10x.h
  • CAN_F1R2_FB18 : stm32f10x.h
  • CAN_F1R2_FB19 : stm32f10x.h
  • CAN_F1R2_FB2 : stm32f10x.h
  • CAN_F1R2_FB20 : stm32f10x.h
  • CAN_F1R2_FB21 : stm32f10x.h
  • CAN_F1R2_FB22 : stm32f10x.h
  • CAN_F1R2_FB23 : stm32f10x.h
  • CAN_F1R2_FB24 : stm32f10x.h
  • CAN_F1R2_FB25 : stm32f10x.h
  • CAN_F1R2_FB26 : stm32f10x.h
  • CAN_F1R2_FB27 : stm32f10x.h
  • CAN_F1R2_FB28 : stm32f10x.h
  • CAN_F1R2_FB29 : stm32f10x.h
  • CAN_F1R2_FB3 : stm32f10x.h
  • CAN_F1R2_FB30 : stm32f10x.h
  • CAN_F1R2_FB31 : stm32f10x.h
  • CAN_F1R2_FB4 : stm32f10x.h
  • CAN_F1R2_FB5 : stm32f10x.h
  • CAN_F1R2_FB6 : stm32f10x.h
  • CAN_F1R2_FB7 : stm32f10x.h
  • CAN_F1R2_FB8 : stm32f10x.h
  • CAN_F1R2_FB9 : stm32f10x.h
  • CAN_F2R1_FB0 : stm32f10x.h
  • CAN_F2R1_FB1 : stm32f10x.h
  • CAN_F2R1_FB10 : stm32f10x.h
  • CAN_F2R1_FB11 : stm32f10x.h
  • CAN_F2R1_FB12 : stm32f10x.h
  • CAN_F2R1_FB13 : stm32f10x.h
  • CAN_F2R1_FB14 : stm32f10x.h
  • CAN_F2R1_FB15 : stm32f10x.h
  • CAN_F2R1_FB16 : stm32f10x.h
  • CAN_F2R1_FB17 : stm32f10x.h
  • CAN_F2R1_FB18 : stm32f10x.h
  • CAN_F2R1_FB19 : stm32f10x.h
  • CAN_F2R1_FB2 : stm32f10x.h
  • CAN_F2R1_FB20 : stm32f10x.h
  • CAN_F2R1_FB21 : stm32f10x.h
  • CAN_F2R1_FB22 : stm32f10x.h
  • CAN_F2R1_FB23 : stm32f10x.h
  • CAN_F2R1_FB24 : stm32f10x.h
  • CAN_F2R1_FB25 : stm32f10x.h
  • CAN_F2R1_FB26 : stm32f10x.h
  • CAN_F2R1_FB27 : stm32f10x.h
  • CAN_F2R1_FB28 : stm32f10x.h
  • CAN_F2R1_FB29 : stm32f10x.h
  • CAN_F2R1_FB3 : stm32f10x.h
  • CAN_F2R1_FB30 : stm32f10x.h
  • CAN_F2R1_FB31 : stm32f10x.h
  • CAN_F2R1_FB4 : stm32f10x.h
  • CAN_F2R1_FB5 : stm32f10x.h
  • CAN_F2R1_FB6 : stm32f10x.h
  • CAN_F2R1_FB7 : stm32f10x.h
  • CAN_F2R1_FB8 : stm32f10x.h
  • CAN_F2R1_FB9 : stm32f10x.h
  • CAN_F2R2_FB0 : stm32f10x.h
  • CAN_F2R2_FB1 : stm32f10x.h
  • CAN_F2R2_FB10 : stm32f10x.h
  • CAN_F2R2_FB11 : stm32f10x.h
  • CAN_F2R2_FB12 : stm32f10x.h
  • CAN_F2R2_FB13 : stm32f10x.h
  • CAN_F2R2_FB14 : stm32f10x.h
  • CAN_F2R2_FB15 : stm32f10x.h
  • CAN_F2R2_FB16 : stm32f10x.h
  • CAN_F2R2_FB17 : stm32f10x.h
  • CAN_F2R2_FB18 : stm32f10x.h
  • CAN_F2R2_FB19 : stm32f10x.h
  • CAN_F2R2_FB2 : stm32f10x.h
  • CAN_F2R2_FB20 : stm32f10x.h
  • CAN_F2R2_FB21 : stm32f10x.h
  • CAN_F2R2_FB22 : stm32f10x.h
  • CAN_F2R2_FB23 : stm32f10x.h
  • CAN_F2R2_FB24 : stm32f10x.h
  • CAN_F2R2_FB25 : stm32f10x.h
  • CAN_F2R2_FB26 : stm32f10x.h
  • CAN_F2R2_FB27 : stm32f10x.h
  • CAN_F2R2_FB28 : stm32f10x.h
  • CAN_F2R2_FB29 : stm32f10x.h
  • CAN_F2R2_FB3 : stm32f10x.h
  • CAN_F2R2_FB30 : stm32f10x.h
  • CAN_F2R2_FB31 : stm32f10x.h
  • CAN_F2R2_FB4 : stm32f10x.h
  • CAN_F2R2_FB5 : stm32f10x.h
  • CAN_F2R2_FB6 : stm32f10x.h
  • CAN_F2R2_FB7 : stm32f10x.h
  • CAN_F2R2_FB8 : stm32f10x.h
  • CAN_F2R2_FB9 : stm32f10x.h
  • CAN_F3R1_FB0 : stm32f10x.h
  • CAN_F3R1_FB1 : stm32f10x.h
  • CAN_F3R1_FB10 : stm32f10x.h
  • CAN_F3R1_FB11 : stm32f10x.h
  • CAN_F3R1_FB12 : stm32f10x.h
  • CAN_F3R1_FB13 : stm32f10x.h
  • CAN_F3R1_FB14 : stm32f10x.h
  • CAN_F3R1_FB15 : stm32f10x.h
  • CAN_F3R1_FB16 : stm32f10x.h
  • CAN_F3R1_FB17 : stm32f10x.h
  • CAN_F3R1_FB18 : stm32f10x.h
  • CAN_F3R1_FB19 : stm32f10x.h
  • CAN_F3R1_FB2 : stm32f10x.h
  • CAN_F3R1_FB20 : stm32f10x.h
  • CAN_F3R1_FB21 : stm32f10x.h
  • CAN_F3R1_FB22 : stm32f10x.h
  • CAN_F3R1_FB23 : stm32f10x.h
  • CAN_F3R1_FB24 : stm32f10x.h
  • CAN_F3R1_FB25 : stm32f10x.h
  • CAN_F3R1_FB26 : stm32f10x.h
  • CAN_F3R1_FB27 : stm32f10x.h
  • CAN_F3R1_FB28 : stm32f10x.h
  • CAN_F3R1_FB29 : stm32f10x.h
  • CAN_F3R1_FB3 : stm32f10x.h
  • CAN_F3R1_FB30 : stm32f10x.h
  • CAN_F3R1_FB31 : stm32f10x.h
  • CAN_F3R1_FB4 : stm32f10x.h
  • CAN_F3R1_FB5 : stm32f10x.h
  • CAN_F3R1_FB6 : stm32f10x.h
  • CAN_F3R1_FB7 : stm32f10x.h
  • CAN_F3R1_FB8 : stm32f10x.h
  • CAN_F3R1_FB9 : stm32f10x.h
  • CAN_F3R2_FB0 : stm32f10x.h
  • CAN_F3R2_FB1 : stm32f10x.h
  • CAN_F3R2_FB10 : stm32f10x.h
  • CAN_F3R2_FB11 : stm32f10x.h
  • CAN_F3R2_FB12 : stm32f10x.h
  • CAN_F3R2_FB13 : stm32f10x.h
  • CAN_F3R2_FB14 : stm32f10x.h
  • CAN_F3R2_FB15 : stm32f10x.h
  • CAN_F3R2_FB16 : stm32f10x.h
  • CAN_F3R2_FB17 : stm32f10x.h
  • CAN_F3R2_FB18 : stm32f10x.h
  • CAN_F3R2_FB19 : stm32f10x.h
  • CAN_F3R2_FB2 : stm32f10x.h
  • CAN_F3R2_FB20 : stm32f10x.h
  • CAN_F3R2_FB21 : stm32f10x.h
  • CAN_F3R2_FB22 : stm32f10x.h
  • CAN_F3R2_FB23 : stm32f10x.h
  • CAN_F3R2_FB24 : stm32f10x.h
  • CAN_F3R2_FB25 : stm32f10x.h
  • CAN_F3R2_FB26 : stm32f10x.h
  • CAN_F3R2_FB27 : stm32f10x.h
  • CAN_F3R2_FB28 : stm32f10x.h
  • CAN_F3R2_FB29 : stm32f10x.h
  • CAN_F3R2_FB3 : stm32f10x.h
  • CAN_F3R2_FB30 : stm32f10x.h
  • CAN_F3R2_FB31 : stm32f10x.h
  • CAN_F3R2_FB4 : stm32f10x.h
  • CAN_F3R2_FB5 : stm32f10x.h
  • CAN_F3R2_FB6 : stm32f10x.h
  • CAN_F3R2_FB7 : stm32f10x.h
  • CAN_F3R2_FB8 : stm32f10x.h
  • CAN_F3R2_FB9 : stm32f10x.h
  • CAN_F4R1_FB0 : stm32f10x.h
  • CAN_F4R1_FB1 : stm32f10x.h
  • CAN_F4R1_FB10 : stm32f10x.h
  • CAN_F4R1_FB11 : stm32f10x.h
  • CAN_F4R1_FB12 : stm32f10x.h
  • CAN_F4R1_FB13 : stm32f10x.h
  • CAN_F4R1_FB14 : stm32f10x.h
  • CAN_F4R1_FB15 : stm32f10x.h
  • CAN_F4R1_FB16 : stm32f10x.h
  • CAN_F4R1_FB17 : stm32f10x.h
  • CAN_F4R1_FB18 : stm32f10x.h
  • CAN_F4R1_FB19 : stm32f10x.h
  • CAN_F4R1_FB2 : stm32f10x.h
  • CAN_F4R1_FB20 : stm32f10x.h
  • CAN_F4R1_FB21 : stm32f10x.h
  • CAN_F4R1_FB22 : stm32f10x.h
  • CAN_F4R1_FB23 : stm32f10x.h
  • CAN_F4R1_FB24 : stm32f10x.h
  • CAN_F4R1_FB25 : stm32f10x.h
  • CAN_F4R1_FB26 : stm32f10x.h
  • CAN_F4R1_FB27 : stm32f10x.h
  • CAN_F4R1_FB28 : stm32f10x.h
  • CAN_F4R1_FB29 : stm32f10x.h
  • CAN_F4R1_FB3 : stm32f10x.h
  • CAN_F4R1_FB30 : stm32f10x.h
  • CAN_F4R1_FB31 : stm32f10x.h
  • CAN_F4R1_FB4 : stm32f10x.h
  • CAN_F4R1_FB5 : stm32f10x.h
  • CAN_F4R1_FB6 : stm32f10x.h
  • CAN_F4R1_FB7 : stm32f10x.h
  • CAN_F4R1_FB8 : stm32f10x.h
  • CAN_F4R1_FB9 : stm32f10x.h
  • CAN_F4R2_FB0 : stm32f10x.h
  • CAN_F4R2_FB1 : stm32f10x.h
  • CAN_F4R2_FB10 : stm32f10x.h
  • CAN_F4R2_FB11 : stm32f10x.h
  • CAN_F4R2_FB12 : stm32f10x.h
  • CAN_F4R2_FB13 : stm32f10x.h
  • CAN_F4R2_FB14 : stm32f10x.h
  • CAN_F4R2_FB15 : stm32f10x.h
  • CAN_F4R2_FB16 : stm32f10x.h
  • CAN_F4R2_FB17 : stm32f10x.h
  • CAN_F4R2_FB18 : stm32f10x.h
  • CAN_F4R2_FB19 : stm32f10x.h
  • CAN_F4R2_FB2 : stm32f10x.h
  • CAN_F4R2_FB20 : stm32f10x.h
  • CAN_F4R2_FB21 : stm32f10x.h
  • CAN_F4R2_FB22 : stm32f10x.h
  • CAN_F4R2_FB23 : stm32f10x.h
  • CAN_F4R2_FB24 : stm32f10x.h
  • CAN_F4R2_FB25 : stm32f10x.h
  • CAN_F4R2_FB26 : stm32f10x.h
  • CAN_F4R2_FB27 : stm32f10x.h
  • CAN_F4R2_FB28 : stm32f10x.h
  • CAN_F4R2_FB29 : stm32f10x.h
  • CAN_F4R2_FB3 : stm32f10x.h
  • CAN_F4R2_FB30 : stm32f10x.h
  • CAN_F4R2_FB31 : stm32f10x.h
  • CAN_F4R2_FB4 : stm32f10x.h
  • CAN_F4R2_FB5 : stm32f10x.h
  • CAN_F4R2_FB6 : stm32f10x.h
  • CAN_F4R2_FB7 : stm32f10x.h
  • CAN_F4R2_FB8 : stm32f10x.h
  • CAN_F4R2_FB9 : stm32f10x.h
  • CAN_F5R1_FB0 : stm32f10x.h
  • CAN_F5R1_FB1 : stm32f10x.h
  • CAN_F5R1_FB10 : stm32f10x.h
  • CAN_F5R1_FB11 : stm32f10x.h
  • CAN_F5R1_FB12 : stm32f10x.h
  • CAN_F5R1_FB13 : stm32f10x.h
  • CAN_F5R1_FB14 : stm32f10x.h
  • CAN_F5R1_FB15 : stm32f10x.h
  • CAN_F5R1_FB16 : stm32f10x.h
  • CAN_F5R1_FB17 : stm32f10x.h
  • CAN_F5R1_FB18 : stm32f10x.h
  • CAN_F5R1_FB19 : stm32f10x.h
  • CAN_F5R1_FB2 : stm32f10x.h
  • CAN_F5R1_FB20 : stm32f10x.h
  • CAN_F5R1_FB21 : stm32f10x.h
  • CAN_F5R1_FB22 : stm32f10x.h
  • CAN_F5R1_FB23 : stm32f10x.h
  • CAN_F5R1_FB24 : stm32f10x.h
  • CAN_F5R1_FB25 : stm32f10x.h
  • CAN_F5R1_FB26 : stm32f10x.h
  • CAN_F5R1_FB27 : stm32f10x.h
  • CAN_F5R1_FB28 : stm32f10x.h
  • CAN_F5R1_FB29 : stm32f10x.h
  • CAN_F5R1_FB3 : stm32f10x.h
  • CAN_F5R1_FB30 : stm32f10x.h
  • CAN_F5R1_FB31 : stm32f10x.h
  • CAN_F5R1_FB4 : stm32f10x.h
  • CAN_F5R1_FB5 : stm32f10x.h
  • CAN_F5R1_FB6 : stm32f10x.h
  • CAN_F5R1_FB7 : stm32f10x.h
  • CAN_F5R1_FB8 : stm32f10x.h
  • CAN_F5R1_FB9 : stm32f10x.h
  • CAN_F5R2_FB0 : stm32f10x.h
  • CAN_F5R2_FB1 : stm32f10x.h
  • CAN_F5R2_FB10 : stm32f10x.h
  • CAN_F5R2_FB11 : stm32f10x.h
  • CAN_F5R2_FB12 : stm32f10x.h
  • CAN_F5R2_FB13 : stm32f10x.h
  • CAN_F5R2_FB14 : stm32f10x.h
  • CAN_F5R2_FB15 : stm32f10x.h
  • CAN_F5R2_FB16 : stm32f10x.h
  • CAN_F5R2_FB17 : stm32f10x.h
  • CAN_F5R2_FB18 : stm32f10x.h
  • CAN_F5R2_FB19 : stm32f10x.h
  • CAN_F5R2_FB2 : stm32f10x.h
  • CAN_F5R2_FB20 : stm32f10x.h
  • CAN_F5R2_FB21 : stm32f10x.h
  • CAN_F5R2_FB22 : stm32f10x.h
  • CAN_F5R2_FB23 : stm32f10x.h
  • CAN_F5R2_FB24 : stm32f10x.h
  • CAN_F5R2_FB25 : stm32f10x.h
  • CAN_F5R2_FB26 : stm32f10x.h
  • CAN_F5R2_FB27 : stm32f10x.h
  • CAN_F5R2_FB28 : stm32f10x.h
  • CAN_F5R2_FB29 : stm32f10x.h
  • CAN_F5R2_FB3 : stm32f10x.h
  • CAN_F5R2_FB30 : stm32f10x.h
  • CAN_F5R2_FB31 : stm32f10x.h
  • CAN_F5R2_FB4 : stm32f10x.h
  • CAN_F5R2_FB5 : stm32f10x.h
  • CAN_F5R2_FB6 : stm32f10x.h
  • CAN_F5R2_FB7 : stm32f10x.h
  • CAN_F5R2_FB8 : stm32f10x.h
  • CAN_F5R2_FB9 : stm32f10x.h
  • CAN_F6R1_FB0 : stm32f10x.h
  • CAN_F6R1_FB1 : stm32f10x.h
  • CAN_F6R1_FB10 : stm32f10x.h
  • CAN_F6R1_FB11 : stm32f10x.h
  • CAN_F6R1_FB12 : stm32f10x.h
  • CAN_F6R1_FB13 : stm32f10x.h
  • CAN_F6R1_FB14 : stm32f10x.h
  • CAN_F6R1_FB15 : stm32f10x.h
  • CAN_F6R1_FB16 : stm32f10x.h
  • CAN_F6R1_FB17 : stm32f10x.h
  • CAN_F6R1_FB18 : stm32f10x.h
  • CAN_F6R1_FB19 : stm32f10x.h
  • CAN_F6R1_FB2 : stm32f10x.h
  • CAN_F6R1_FB20 : stm32f10x.h
  • CAN_F6R1_FB21 : stm32f10x.h
  • CAN_F6R1_FB22 : stm32f10x.h
  • CAN_F6R1_FB23 : stm32f10x.h
  • CAN_F6R1_FB24 : stm32f10x.h
  • CAN_F6R1_FB25 : stm32f10x.h
  • CAN_F6R1_FB26 : stm32f10x.h
  • CAN_F6R1_FB27 : stm32f10x.h
  • CAN_F6R1_FB28 : stm32f10x.h
  • CAN_F6R1_FB29 : stm32f10x.h
  • CAN_F6R1_FB3 : stm32f10x.h
  • CAN_F6R1_FB30 : stm32f10x.h
  • CAN_F6R1_FB31 : stm32f10x.h
  • CAN_F6R1_FB4 : stm32f10x.h
  • CAN_F6R1_FB5 : stm32f10x.h
  • CAN_F6R1_FB6 : stm32f10x.h
  • CAN_F6R1_FB7 : stm32f10x.h
  • CAN_F6R1_FB8 : stm32f10x.h
  • CAN_F6R1_FB9 : stm32f10x.h
  • CAN_F6R2_FB0 : stm32f10x.h
  • CAN_F6R2_FB1 : stm32f10x.h
  • CAN_F6R2_FB10 : stm32f10x.h
  • CAN_F6R2_FB11 : stm32f10x.h
  • CAN_F6R2_FB12 : stm32f10x.h
  • CAN_F6R2_FB13 : stm32f10x.h
  • CAN_F6R2_FB14 : stm32f10x.h
  • CAN_F6R2_FB15 : stm32f10x.h
  • CAN_F6R2_FB16 : stm32f10x.h
  • CAN_F6R2_FB17 : stm32f10x.h
  • CAN_F6R2_FB18 : stm32f10x.h
  • CAN_F6R2_FB19 : stm32f10x.h
  • CAN_F6R2_FB2 : stm32f10x.h
  • CAN_F6R2_FB20 : stm32f10x.h
  • CAN_F6R2_FB21 : stm32f10x.h
  • CAN_F6R2_FB22 : stm32f10x.h
  • CAN_F6R2_FB23 : stm32f10x.h
  • CAN_F6R2_FB24 : stm32f10x.h
  • CAN_F6R2_FB25 : stm32f10x.h
  • CAN_F6R2_FB26 : stm32f10x.h
  • CAN_F6R2_FB27 : stm32f10x.h
  • CAN_F6R2_FB28 : stm32f10x.h
  • CAN_F6R2_FB29 : stm32f10x.h
  • CAN_F6R2_FB3 : stm32f10x.h
  • CAN_F6R2_FB30 : stm32f10x.h
  • CAN_F6R2_FB31 : stm32f10x.h
  • CAN_F6R2_FB4 : stm32f10x.h
  • CAN_F6R2_FB5 : stm32f10x.h
  • CAN_F6R2_FB6 : stm32f10x.h
  • CAN_F6R2_FB7 : stm32f10x.h
  • CAN_F6R2_FB8 : stm32f10x.h
  • CAN_F6R2_FB9 : stm32f10x.h
  • CAN_F7R1_FB0 : stm32f10x.h
  • CAN_F7R1_FB1 : stm32f10x.h
  • CAN_F7R1_FB10 : stm32f10x.h
  • CAN_F7R1_FB11 : stm32f10x.h
  • CAN_F7R1_FB12 : stm32f10x.h
  • CAN_F7R1_FB13 : stm32f10x.h
  • CAN_F7R1_FB14 : stm32f10x.h
  • CAN_F7R1_FB15 : stm32f10x.h
  • CAN_F7R1_FB16 : stm32f10x.h
  • CAN_F7R1_FB17 : stm32f10x.h
  • CAN_F7R1_FB18 : stm32f10x.h
  • CAN_F7R1_FB19 : stm32f10x.h
  • CAN_F7R1_FB2 : stm32f10x.h
  • CAN_F7R1_FB20 : stm32f10x.h
  • CAN_F7R1_FB21 : stm32f10x.h
  • CAN_F7R1_FB22 : stm32f10x.h
  • CAN_F7R1_FB23 : stm32f10x.h
  • CAN_F7R1_FB24 : stm32f10x.h
  • CAN_F7R1_FB25 : stm32f10x.h
  • CAN_F7R1_FB26 : stm32f10x.h
  • CAN_F7R1_FB27 : stm32f10x.h
  • CAN_F7R1_FB28 : stm32f10x.h
  • CAN_F7R1_FB29 : stm32f10x.h
  • CAN_F7R1_FB3 : stm32f10x.h
  • CAN_F7R1_FB30 : stm32f10x.h
  • CAN_F7R1_FB31 : stm32f10x.h
  • CAN_F7R1_FB4 : stm32f10x.h
  • CAN_F7R1_FB5 : stm32f10x.h
  • CAN_F7R1_FB6 : stm32f10x.h
  • CAN_F7R1_FB7 : stm32f10x.h
  • CAN_F7R1_FB8 : stm32f10x.h
  • CAN_F7R1_FB9 : stm32f10x.h
  • CAN_F7R2_FB0 : stm32f10x.h
  • CAN_F7R2_FB1 : stm32f10x.h
  • CAN_F7R2_FB10 : stm32f10x.h
  • CAN_F7R2_FB11 : stm32f10x.h
  • CAN_F7R2_FB12 : stm32f10x.h
  • CAN_F7R2_FB13 : stm32f10x.h
  • CAN_F7R2_FB14 : stm32f10x.h
  • CAN_F7R2_FB15 : stm32f10x.h
  • CAN_F7R2_FB16 : stm32f10x.h
  • CAN_F7R2_FB17 : stm32f10x.h
  • CAN_F7R2_FB18 : stm32f10x.h
  • CAN_F7R2_FB19 : stm32f10x.h
  • CAN_F7R2_FB2 : stm32f10x.h
  • CAN_F7R2_FB20 : stm32f10x.h
  • CAN_F7R2_FB21 : stm32f10x.h
  • CAN_F7R2_FB22 : stm32f10x.h
  • CAN_F7R2_FB23 : stm32f10x.h
  • CAN_F7R2_FB24 : stm32f10x.h
  • CAN_F7R2_FB25 : stm32f10x.h
  • CAN_F7R2_FB26 : stm32f10x.h
  • CAN_F7R2_FB27 : stm32f10x.h
  • CAN_F7R2_FB28 : stm32f10x.h
  • CAN_F7R2_FB29 : stm32f10x.h
  • CAN_F7R2_FB3 : stm32f10x.h
  • CAN_F7R2_FB30 : stm32f10x.h
  • CAN_F7R2_FB31 : stm32f10x.h
  • CAN_F7R2_FB4 : stm32f10x.h
  • CAN_F7R2_FB5 : stm32f10x.h
  • CAN_F7R2_FB6 : stm32f10x.h
  • CAN_F7R2_FB7 : stm32f10x.h
  • CAN_F7R2_FB8 : stm32f10x.h
  • CAN_F7R2_FB9 : stm32f10x.h
  • CAN_F8R1_FB0 : stm32f10x.h
  • CAN_F8R1_FB1 : stm32f10x.h
  • CAN_F8R1_FB10 : stm32f10x.h
  • CAN_F8R1_FB11 : stm32f10x.h
  • CAN_F8R1_FB12 : stm32f10x.h
  • CAN_F8R1_FB13 : stm32f10x.h
  • CAN_F8R1_FB14 : stm32f10x.h
  • CAN_F8R1_FB15 : stm32f10x.h
  • CAN_F8R1_FB16 : stm32f10x.h
  • CAN_F8R1_FB17 : stm32f10x.h
  • CAN_F8R1_FB18 : stm32f10x.h
  • CAN_F8R1_FB19 : stm32f10x.h
  • CAN_F8R1_FB2 : stm32f10x.h
  • CAN_F8R1_FB20 : stm32f10x.h
  • CAN_F8R1_FB21 : stm32f10x.h
  • CAN_F8R1_FB22 : stm32f10x.h
  • CAN_F8R1_FB23 : stm32f10x.h
  • CAN_F8R1_FB24 : stm32f10x.h
  • CAN_F8R1_FB25 : stm32f10x.h
  • CAN_F8R1_FB26 : stm32f10x.h
  • CAN_F8R1_FB27 : stm32f10x.h
  • CAN_F8R1_FB28 : stm32f10x.h
  • CAN_F8R1_FB29 : stm32f10x.h
  • CAN_F8R1_FB3 : stm32f10x.h
  • CAN_F8R1_FB30 : stm32f10x.h
  • CAN_F8R1_FB31 : stm32f10x.h
  • CAN_F8R1_FB4 : stm32f10x.h
  • CAN_F8R1_FB5 : stm32f10x.h
  • CAN_F8R1_FB6 : stm32f10x.h
  • CAN_F8R1_FB7 : stm32f10x.h
  • CAN_F8R1_FB8 : stm32f10x.h
  • CAN_F8R1_FB9 : stm32f10x.h
  • CAN_F8R2_FB0 : stm32f10x.h
  • CAN_F8R2_FB1 : stm32f10x.h
  • CAN_F8R2_FB10 : stm32f10x.h
  • CAN_F8R2_FB11 : stm32f10x.h
  • CAN_F8R2_FB12 : stm32f10x.h
  • CAN_F8R2_FB13 : stm32f10x.h
  • CAN_F8R2_FB14 : stm32f10x.h
  • CAN_F8R2_FB15 : stm32f10x.h
  • CAN_F8R2_FB16 : stm32f10x.h
  • CAN_F8R2_FB17 : stm32f10x.h
  • CAN_F8R2_FB18 : stm32f10x.h
  • CAN_F8R2_FB19 : stm32f10x.h
  • CAN_F8R2_FB2 : stm32f10x.h
  • CAN_F8R2_FB20 : stm32f10x.h
  • CAN_F8R2_FB21 : stm32f10x.h
  • CAN_F8R2_FB22 : stm32f10x.h
  • CAN_F8R2_FB23 : stm32f10x.h
  • CAN_F8R2_FB24 : stm32f10x.h
  • CAN_F8R2_FB25 : stm32f10x.h
  • CAN_F8R2_FB26 : stm32f10x.h
  • CAN_F8R2_FB27 : stm32f10x.h
  • CAN_F8R2_FB28 : stm32f10x.h
  • CAN_F8R2_FB29 : stm32f10x.h
  • CAN_F8R2_FB3 : stm32f10x.h
  • CAN_F8R2_FB30 : stm32f10x.h
  • CAN_F8R2_FB31 : stm32f10x.h
  • CAN_F8R2_FB4 : stm32f10x.h
  • CAN_F8R2_FB5 : stm32f10x.h
  • CAN_F8R2_FB6 : stm32f10x.h
  • CAN_F8R2_FB7 : stm32f10x.h
  • CAN_F8R2_FB8 : stm32f10x.h
  • CAN_F8R2_FB9 : stm32f10x.h
  • CAN_F9R1_FB0 : stm32f10x.h
  • CAN_F9R1_FB1 : stm32f10x.h
  • CAN_F9R1_FB10 : stm32f10x.h
  • CAN_F9R1_FB11 : stm32f10x.h
  • CAN_F9R1_FB12 : stm32f10x.h
  • CAN_F9R1_FB13 : stm32f10x.h
  • CAN_F9R1_FB14 : stm32f10x.h
  • CAN_F9R1_FB15 : stm32f10x.h
  • CAN_F9R1_FB16 : stm32f10x.h
  • CAN_F9R1_FB17 : stm32f10x.h
  • CAN_F9R1_FB18 : stm32f10x.h
  • CAN_F9R1_FB19 : stm32f10x.h
  • CAN_F9R1_FB2 : stm32f10x.h
  • CAN_F9R1_FB20 : stm32f10x.h
  • CAN_F9R1_FB21 : stm32f10x.h
  • CAN_F9R1_FB22 : stm32f10x.h
  • CAN_F9R1_FB23 : stm32f10x.h
  • CAN_F9R1_FB24 : stm32f10x.h
  • CAN_F9R1_FB25 : stm32f10x.h
  • CAN_F9R1_FB26 : stm32f10x.h
  • CAN_F9R1_FB27 : stm32f10x.h
  • CAN_F9R1_FB28 : stm32f10x.h
  • CAN_F9R1_FB29 : stm32f10x.h
  • CAN_F9R1_FB3 : stm32f10x.h
  • CAN_F9R1_FB30 : stm32f10x.h
  • CAN_F9R1_FB31 : stm32f10x.h
  • CAN_F9R1_FB4 : stm32f10x.h
  • CAN_F9R1_FB5 : stm32f10x.h
  • CAN_F9R1_FB6 : stm32f10x.h
  • CAN_F9R1_FB7 : stm32f10x.h
  • CAN_F9R1_FB8 : stm32f10x.h
  • CAN_F9R1_FB9 : stm32f10x.h
  • CAN_F9R2_FB0 : stm32f10x.h
  • CAN_F9R2_FB1 : stm32f10x.h
  • CAN_F9R2_FB10 : stm32f10x.h
  • CAN_F9R2_FB11 : stm32f10x.h
  • CAN_F9R2_FB12 : stm32f10x.h
  • CAN_F9R2_FB13 : stm32f10x.h
  • CAN_F9R2_FB14 : stm32f10x.h
  • CAN_F9R2_FB15 : stm32f10x.h
  • CAN_F9R2_FB16 : stm32f10x.h
  • CAN_F9R2_FB17 : stm32f10x.h
  • CAN_F9R2_FB18 : stm32f10x.h
  • CAN_F9R2_FB19 : stm32f10x.h
  • CAN_F9R2_FB2 : stm32f10x.h
  • CAN_F9R2_FB20 : stm32f10x.h
  • CAN_F9R2_FB21 : stm32f10x.h
  • CAN_F9R2_FB22 : stm32f10x.h
  • CAN_F9R2_FB23 : stm32f10x.h
  • CAN_F9R2_FB24 : stm32f10x.h
  • CAN_F9R2_FB25 : stm32f10x.h
  • CAN_F9R2_FB26 : stm32f10x.h
  • CAN_F9R2_FB27 : stm32f10x.h
  • CAN_F9R2_FB28 : stm32f10x.h
  • CAN_F9R2_FB29 : stm32f10x.h
  • CAN_F9R2_FB3 : stm32f10x.h
  • CAN_F9R2_FB30 : stm32f10x.h
  • CAN_F9R2_FB31 : stm32f10x.h
  • CAN_F9R2_FB4 : stm32f10x.h
  • CAN_F9R2_FB5 : stm32f10x.h
  • CAN_F9R2_FB6 : stm32f10x.h
  • CAN_F9R2_FB7 : stm32f10x.h
  • CAN_F9R2_FB8 : stm32f10x.h
  • CAN_F9R2_FB9 : stm32f10x.h
  • CAN_FA1R_FACT : stm32f10x.h
  • CAN_FA1R_FACT0 : stm32f10x.h
  • CAN_FA1R_FACT1 : stm32f10x.h
  • CAN_FA1R_FACT10 : stm32f10x.h
  • CAN_FA1R_FACT11 : stm32f10x.h
  • CAN_FA1R_FACT12 : stm32f10x.h
  • CAN_FA1R_FACT13 : stm32f10x.h
  • CAN_FA1R_FACT2 : stm32f10x.h
  • CAN_FA1R_FACT3 : stm32f10x.h
  • CAN_FA1R_FACT4 : stm32f10x.h
  • CAN_FA1R_FACT5 : stm32f10x.h
  • CAN_FA1R_FACT6 : stm32f10x.h
  • CAN_FA1R_FACT7 : stm32f10x.h
  • CAN_FA1R_FACT8 : stm32f10x.h
  • CAN_FA1R_FACT9 : stm32f10x.h
  • CAN_FFA1R_FFA : stm32f10x.h
  • CAN_FFA1R_FFA0 : stm32f10x.h
  • CAN_FFA1R_FFA1 : stm32f10x.h
  • CAN_FFA1R_FFA10 : stm32f10x.h
  • CAN_FFA1R_FFA11 : stm32f10x.h
  • CAN_FFA1R_FFA12 : stm32f10x.h
  • CAN_FFA1R_FFA13 : stm32f10x.h
  • CAN_FFA1R_FFA2 : stm32f10x.h
  • CAN_FFA1R_FFA3 : stm32f10x.h
  • CAN_FFA1R_FFA4 : stm32f10x.h
  • CAN_FFA1R_FFA5 : stm32f10x.h
  • CAN_FFA1R_FFA6 : stm32f10x.h
  • CAN_FFA1R_FFA7 : stm32f10x.h
  • CAN_FFA1R_FFA8 : stm32f10x.h
  • CAN_FFA1R_FFA9 : stm32f10x.h
  • CAN_FIFO0 : stm32f10x_can.h
  • CAN_FIFO1 : stm32f10x_can.h
  • CAN_FIFORelease() : stm32f10x_can.c , stm32f10x_can.h
  • CAN_Filter_FIFO0 : stm32f10x_can.h
  • CAN_Filter_FIFO1 : stm32f10x_can.h
  • CAN_FilterFIFO0 : stm32f10x_can.h
  • CAN_FilterFIFO1 : stm32f10x_can.h
  • CAN_FilterInit() : stm32f10x_can.h , stm32f10x_can.c
  • CAN_FilterInitStructure : STM32F10x_StdPeriph_Examples/CAN/Networking/main.c , STM32F10x_StdPeriph_Examples/CAN/DualCAN/main.c
  • CAN_FilterMode_IdList : stm32f10x_can.h
  • CAN_FilterMode_IdMask : stm32f10x_can.h
  • CAN_FilterScale_16bit : stm32f10x_can.h
  • CAN_FilterScale_32bit : stm32f10x_can.h
  • CAN_FLAG_BOF : stm32f10x_can.h
  • CAN_FLAG_EPV : stm32f10x_can.h
  • CAN_FLAG_EWG : stm32f10x_can.h
  • CAN_FLAG_FF0 : stm32f10x_can.h
  • CAN_FLAG_FF1 : stm32f10x_can.h
  • CAN_FLAG_FMP0 : stm32f10x_can.h
  • CAN_FLAG_FMP1 : stm32f10x_can.h
  • CAN_FLAG_FOV0 : stm32f10x_can.h
  • CAN_FLAG_FOV1 : stm32f10x_can.h
  • CAN_FLAG_LEC : stm32f10x_can.h
  • CAN_FLAG_RQCP0 : stm32f10x_can.h
  • CAN_FLAG_RQCP1 : stm32f10x_can.h
  • CAN_FLAG_RQCP2 : stm32f10x_can.h
  • CAN_FLAG_SLAK : stm32f10x_can.h
  • CAN_FLAG_WKU : stm32f10x_can.h
  • CAN_FLAGS_ESR : stm32f10x_can.c
  • CAN_FLAGS_MSR : stm32f10x_can.c
  • CAN_FLAGS_RF0R : stm32f10x_can.c
  • CAN_FLAGS_RF1R : stm32f10x_can.c
  • CAN_FLAGS_TSR : stm32f10x_can.c
  • CAN_FM1R_FBM : stm32f10x.h
  • CAN_FM1R_FBM0 : stm32f10x.h
  • CAN_FM1R_FBM1 : stm32f10x.h
  • CAN_FM1R_FBM10 : stm32f10x.h
  • CAN_FM1R_FBM11 : stm32f10x.h
  • CAN_FM1R_FBM12 : stm32f10x.h
  • CAN_FM1R_FBM13 : stm32f10x.h
  • CAN_FM1R_FBM2 : stm32f10x.h
  • CAN_FM1R_FBM3 : stm32f10x.h
  • CAN_FM1R_FBM4 : stm32f10x.h
  • CAN_FM1R_FBM5 : stm32f10x.h
  • CAN_FM1R_FBM6 : stm32f10x.h
  • CAN_FM1R_FBM7 : stm32f10x.h
  • CAN_FM1R_FBM8 : stm32f10x.h
  • CAN_FM1R_FBM9 : stm32f10x.h
  • CAN_FMR_FINIT : stm32f10x.h
  • CAN_FS1R_FSC : stm32f10x.h
  • CAN_FS1R_FSC0 : stm32f10x.h
  • CAN_FS1R_FSC1 : stm32f10x.h
  • CAN_FS1R_FSC10 : stm32f10x.h
  • CAN_FS1R_FSC11 : stm32f10x.h
  • CAN_FS1R_FSC12 : stm32f10x.h
  • CAN_FS1R_FSC13 : stm32f10x.h
  • CAN_FS1R_FSC2 : stm32f10x.h
  • CAN_FS1R_FSC3 : stm32f10x.h
  • CAN_FS1R_FSC4 : stm32f10x.h
  • CAN_FS1R_FSC5 : stm32f10x.h
  • CAN_FS1R_FSC6 : stm32f10x.h
  • CAN_FS1R_FSC7 : stm32f10x.h
  • CAN_FS1R_FSC8 : stm32f10x.h
  • CAN_FS1R_FSC9 : stm32f10x.h
  • CAN_GetFlagStatus() : stm32f10x_can.c , stm32f10x_can.h
  • CAN_GetITStatus() : stm32f10x_can.h , stm32f10x_can.c
  • CAN_GetLastErrorCode() : stm32f10x_can.c , stm32f10x_can.h
  • CAN_GetLSBTransmitErrorCounter() : stm32f10x_can.h , stm32f10x_can.c
  • CAN_GetReceiveErrorCounter() : stm32f10x_can.c , stm32f10x_can.h
  • CAN_ID_EXT : stm32f10x_can.h
  • CAN_Id_Extended : stm32f10x_can.h
  • CAN_Id_Standard : stm32f10x_can.h
  • CAN_ID_STD : stm32f10x_can.h
  • CAN_IER_BOFIE : stm32f10x.h
  • CAN_IER_EPVIE : stm32f10x.h
  • CAN_IER_ERRIE : stm32f10x.h
  • CAN_IER_EWGIE : stm32f10x.h
  • CAN_IER_FFIE0 : stm32f10x.h
  • CAN_IER_FFIE1 : stm32f10x.h
  • CAN_IER_FMPIE0 : stm32f10x.h
  • CAN_IER_FMPIE1 : stm32f10x.h
  • CAN_IER_FOVIE0 : stm32f10x.h
  • CAN_IER_FOVIE1 : stm32f10x.h
  • CAN_IER_LECIE : stm32f10x.h
  • CAN_IER_SLKIE : stm32f10x.h
  • CAN_IER_TMEIE : stm32f10x.h
  • CAN_IER_WKUIE : stm32f10x.h
  • CAN_Init() : stm32f10x_can.h , stm32f10x_can.c
  • CAN_InitStatus_Failed : stm32f10x_can.h
  • CAN_InitStatus_Success : stm32f10x_can.h
  • CAN_InitStructure : STM32F10x_StdPeriph_Examples/CAN/Networking/main.c , STM32F10x_StdPeriph_Examples/CAN/DualCAN/main.c
  • CAN_Interrupt() : STM32F10x_StdPeriph_Examples/CAN/LoopBack/main.c
  • CAN_IT_BOF : stm32f10x_can.h
  • CAN_IT_EPV : stm32f10x_can.h
  • CAN_IT_ERR : stm32f10x_can.h
  • CAN_IT_EWG : stm32f10x_can.h
  • CAN_IT_FF0 : stm32f10x_can.h
  • CAN_IT_FF1 : stm32f10x_can.h
  • CAN_IT_FMP0 : stm32f10x_can.h
  • CAN_IT_FMP1 : stm32f10x_can.h
  • CAN_IT_FOV0 : stm32f10x_can.h
  • CAN_IT_FOV1 : stm32f10x_can.h
  • CAN_IT_LEC : stm32f10x_can.h
  • CAN_IT_RQCP0 : stm32f10x_can.h
  • CAN_IT_RQCP1 : stm32f10x_can.h
  • CAN_IT_RQCP2 : stm32f10x_can.h
  • CAN_IT_SLK : stm32f10x_can.h
  • CAN_IT_TME : stm32f10x_can.h
  • CAN_IT_WKU : stm32f10x_can.h
  • CAN_ITConfig() : stm32f10x_can.c , stm32f10x_can.h
  • CAN_MCR_ABOM : stm32f10x.h
  • CAN_MCR_AWUM : stm32f10x.h
  • CAN_MCR_INRQ : stm32f10x.h
  • CAN_MCR_NART : stm32f10x.h
  • CAN_MCR_RESET : stm32f10x.h
  • CAN_MCR_RFLM : stm32f10x.h
  • CAN_MCR_SLEEP : stm32f10x.h
  • CAN_MCR_TTCM : stm32f10x.h
  • CAN_MCR_TXFP : stm32f10x.h
  • CAN_MessagePending() : stm32f10x_can.h , stm32f10x_can.c
  • CAN_Mode_LoopBack : stm32f10x_can.h
  • CAN_MODE_MASK : stm32f10x_can.c
  • CAN_Mode_Normal : stm32f10x_can.h
  • CAN_Mode_Silent : stm32f10x_can.h
  • CAN_Mode_Silent_LoopBack : stm32f10x_can.h
  • CAN_ModeStatus_Failed : stm32f10x_can.h
  • CAN_ModeStatus_Success : stm32f10x_can.h
  • CAN_MSR_ERRI : stm32f10x.h
  • CAN_MSR_INAK : stm32f10x.h
  • CAN_MSR_RX : stm32f10x.h
  • CAN_MSR_RXM : stm32f10x.h
  • CAN_MSR_SAMP : stm32f10x.h
  • CAN_MSR_SLAK : stm32f10x.h
  • CAN_MSR_SLAKI : stm32f10x.h
  • CAN_MSR_TXM : stm32f10x.h
  • CAN_MSR_WKUI : stm32f10x.h
  • CAN_NO_MB : stm32f10x_can.h
  • CAN_OperatingMode_Initialization : stm32f10x_can.h
  • CAN_OperatingMode_Normal : stm32f10x_can.h
  • CAN_OperatingMode_Sleep : stm32f10x_can.h
  • CAN_OperatingModeRequest() : stm32f10x_can.h , stm32f10x_can.c
  • CAN_Polling() : STM32F10x_StdPeriph_Examples/CAN/LoopBack/main.c
  • CAN_RDH0R_DATA4 : stm32f10x.h
  • CAN_RDH0R_DATA5 : stm32f10x.h
  • CAN_RDH0R_DATA6 : stm32f10x.h
  • CAN_RDH0R_DATA7 : stm32f10x.h
  • CAN_RDH1R_DATA4 : stm32f10x.h
  • CAN_RDH1R_DATA5 : stm32f10x.h
  • CAN_RDH1R_DATA6 : stm32f10x.h
  • CAN_RDH1R_DATA7 : stm32f10x.h
  • CAN_RDL0R_DATA0 : stm32f10x.h
  • CAN_RDL0R_DATA1 : stm32f10x.h
  • CAN_RDL0R_DATA2 : stm32f10x.h
  • CAN_RDL0R_DATA3 : stm32f10x.h
  • CAN_RDL1R_DATA0 : stm32f10x.h
  • CAN_RDL1R_DATA1 : stm32f10x.h
  • CAN_RDL1R_DATA2 : stm32f10x.h
  • CAN_RDL1R_DATA3 : stm32f10x.h
  • CAN_RDT0R_DLC : stm32f10x.h
  • CAN_RDT0R_FMI : stm32f10x.h
  • CAN_RDT0R_TIME : stm32f10x.h
  • CAN_RDT1R_DLC : stm32f10x.h
  • CAN_RDT1R_FMI : stm32f10x.h
  • CAN_RDT1R_TIME : stm32f10x.h
  • CAN_Receive() : stm32f10x_can.c , stm32f10x_can.h
  • CAN_RF0R_FMP0 : stm32f10x.h
  • CAN_RF0R_FOVR0 : stm32f10x.h
  • CAN_RF0R_FULL0 : stm32f10x.h
  • CAN_RF0R_RFOM0 : stm32f10x.h
  • CAN_RF1R_FMP1 : stm32f10x.h
  • CAN_RF1R_FOVR1 : stm32f10x.h
  • CAN_RF1R_FULL1 : stm32f10x.h
  • CAN_RF1R_RFOM1 : stm32f10x.h
  • CAN_RI0R_EXID : stm32f10x.h
  • CAN_RI0R_IDE : stm32f10x.h
  • CAN_RI0R_RTR : stm32f10x.h
  • CAN_RI0R_STID : stm32f10x.h
  • CAN_RI1R_EXID : stm32f10x.h
  • CAN_RI1R_IDE : stm32f10x.h
  • CAN_RI1R_RTR : stm32f10x.h
  • CAN_RI1R_STID : stm32f10x.h
  • CAN_RTR_DATA : stm32f10x_can.h
  • CAN_RTR_Data : stm32f10x_can.h
  • CAN_RTR_REMOTE : stm32f10x_can.h
  • CAN_RTR_Remote : stm32f10x_can.h
  • CAN_SJW_1tq : stm32f10x_can.h
  • CAN_SJW_2tq : stm32f10x_can.h
  • CAN_SJW_3tq : stm32f10x_can.h
  • CAN_SJW_4tq : stm32f10x_can.h
  • CAN_SlaveStartBank() : stm32f10x_can.c , stm32f10x_can.h
  • CAN_Sleep() : stm32f10x_can.c , stm32f10x_can.h
  • CAN_Sleep_Failed : stm32f10x_can.h
  • CAN_Sleep_Ok : stm32f10x_can.h
  • CAN_StructInit() : stm32f10x_can.c , stm32f10x_can.h
  • CAN_TDH0R_DATA4 : stm32f10x.h
  • CAN_TDH0R_DATA5 : stm32f10x.h
  • CAN_TDH0R_DATA6 : stm32f10x.h
  • CAN_TDH0R_DATA7 : stm32f10x.h
  • CAN_TDH1R_DATA4 : stm32f10x.h
  • CAN_TDH1R_DATA5 : stm32f10x.h
  • CAN_TDH1R_DATA6 : stm32f10x.h
  • CAN_TDH1R_DATA7 : stm32f10x.h
  • CAN_TDH2R_DATA4 : stm32f10x.h
  • CAN_TDH2R_DATA5 : stm32f10x.h
  • CAN_TDH2R_DATA6 : stm32f10x.h
  • CAN_TDH2R_DATA7 : stm32f10x.h
  • CAN_TDL0R_DATA0 : stm32f10x.h
  • CAN_TDL0R_DATA1 : stm32f10x.h
  • CAN_TDL0R_DATA2 : stm32f10x.h
  • CAN_TDL0R_DATA3 : stm32f10x.h
  • CAN_TDL1R_DATA0 : stm32f10x.h
  • CAN_TDL1R_DATA1 : stm32f10x.h
  • CAN_TDL1R_DATA2 : stm32f10x.h
  • CAN_TDL1R_DATA3 : stm32f10x.h
  • CAN_TDL2R_DATA0 : stm32f10x.h
  • CAN_TDL2R_DATA1 : stm32f10x.h
  • CAN_TDL2R_DATA2 : stm32f10x.h
  • CAN_TDL2R_DATA3 : stm32f10x.h
  • CAN_TDT0R_DLC : stm32f10x.h
  • CAN_TDT0R_TGT : stm32f10x.h
  • CAN_TDT0R_TIME : stm32f10x.h
  • CAN_TDT1R_DLC : stm32f10x.h
  • CAN_TDT1R_TGT : stm32f10x.h
  • CAN_TDT1R_TIME : stm32f10x.h
  • CAN_TDT2R_DLC : stm32f10x.h
  • CAN_TDT2R_TGT : stm32f10x.h
  • CAN_TDT2R_TIME : stm32f10x.h
  • CAN_TI0R_EXID : stm32f10x.h
  • CAN_TI0R_IDE : stm32f10x.h
  • CAN_TI0R_RTR : stm32f10x.h
  • CAN_TI0R_STID : stm32f10x.h
  • CAN_TI0R_TXRQ : stm32f10x.h
  • CAN_TI1R_EXID : stm32f10x.h
  • CAN_TI1R_IDE : stm32f10x.h
  • CAN_TI1R_RTR : stm32f10x.h
  • CAN_TI1R_STID : stm32f10x.h
  • CAN_TI1R_TXRQ : stm32f10x.h
  • CAN_TI2R_EXID : stm32f10x.h
  • CAN_TI2R_IDE : stm32f10x.h
  • CAN_TI2R_RTR : stm32f10x.h
  • CAN_TI2R_STID : stm32f10x.h
  • CAN_TI2R_TXRQ : stm32f10x.h
  • CAN_Transmit() : stm32f10x_can.c , stm32f10x_can.h
  • CAN_TransmitStatus() : stm32f10x_can.c , stm32f10x_can.h
  • CAN_TSR_ABRQ0 : stm32f10x.h
  • CAN_TSR_ABRQ1 : stm32f10x.h
  • CAN_TSR_ABRQ2 : stm32f10x.h
  • CAN_TSR_ALST0 : stm32f10x.h
  • CAN_TSR_ALST1 : stm32f10x.h
  • CAN_TSR_ALST2 : stm32f10x.h
  • CAN_TSR_CODE : stm32f10x.h
  • CAN_TSR_LOW : stm32f10x.h
  • CAN_TSR_LOW0 : stm32f10x.h
  • CAN_TSR_LOW1 : stm32f10x.h
  • CAN_TSR_LOW2 : stm32f10x.h
  • CAN_TSR_RQCP0 : stm32f10x.h
  • CAN_TSR_RQCP1 : stm32f10x.h
  • CAN_TSR_RQCP2 : stm32f10x.h
  • CAN_TSR_TERR0 : stm32f10x.h
  • CAN_TSR_TERR1 : stm32f10x.h
  • CAN_TSR_TERR2 : stm32f10x.h
  • CAN_TSR_TME : stm32f10x.h
  • CAN_TSR_TME0 : stm32f10x.h
  • CAN_TSR_TME1 : stm32f10x.h
  • CAN_TSR_TME2 : stm32f10x.h
  • CAN_TSR_TXOK0 : stm32f10x.h
  • CAN_TSR_TXOK1 : stm32f10x.h
  • CAN_TSR_TXOK2 : stm32f10x.h
  • CAN_TTComModeCmd() : stm32f10x_can.c , stm32f10x_can.h
  • CAN_TXMAILBOX_0 : stm32f10x_can.c
  • CAN_TXMAILBOX_1 : stm32f10x_can.c
  • CAN_TXMAILBOX_2 : stm32f10x_can.c
  • CAN_TxStatus_Failed : stm32f10x_can.h
  • CAN_TxStatus_NoMailBox : stm32f10x_can.h
  • CAN_TxStatus_Ok : stm32f10x_can.h
  • CAN_TxStatus_Pending : stm32f10x_can.h
  • CAN_WakeUp() : stm32f10x_can.h , stm32f10x_can.c
  • CAN_WakeUp_Failed : stm32f10x_can.h
  • CAN_WakeUp_Ok : stm32f10x_can.h
  • CANINITFAILED : stm32f10x_can.h
  • CANINITOK : stm32f10x_can.h
  • CANSLEEPFAILED : stm32f10x_can.h
  • CANSLEEPOK : stm32f10x_can.h
  • CANTXFAILE : stm32f10x_can.h
  • CANTXOK : stm32f10x_can.h
  • CANTXPENDING : stm32f10x_can.h
  • CANWAKEUPFAILED : stm32f10x_can.h
  • CANWAKEUPOK : stm32f10x_can.h
  • CANx : STM32F10x_StdPeriph_Examples/CAN/Networking/main.c , STM32F10x_StdPeriph_Examples/CAN/LoopBack/main.c
  • capture : STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_it.c
  • Capture : STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_it.c
  • capture : STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_it.c
  • CaptureNumber : STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/main.c , STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_it.c
  • CardInserted : STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Smartcard/main.c
  • CardProtocol : STM32F10x_StdPeriph_Examples/USART/Smartcard/main.c
  • CardType : stm32_eval_sdio_sd.c
  • CCER_CCE_Set : stm32f10x_tim.c
  • CCER_CCNE_Set : stm32f10x_tim.c
  • CCMR_Offset : stm32f10x_tim.c
  • CCR1_Val : STM32F10x_StdPeriph_Examples/TIM/6Steps/main.c , STM32F10x_StdPeriph_Examples/TIM/OCInactive/main.c , STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/main.c , STM32F10x_StdPeriph_Examples/TIM/TimeBase/main.c , STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/OCToggle/main.c , STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/PWM_Output/main.c , STM32F10x_StdPeriph_Examples/TIM/OCActive/main.c
  • CCR1Val : STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/main.c , STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/main.c
  • CCR2_Val : STM32F10x_StdPeriph_Examples/TIM/OCInactive/main.c , STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/TimeBase/main.c , STM32F10x_StdPeriph_Examples/TIM/6Steps/main.c , STM32F10x_StdPeriph_Examples/TIM/OCActive/main.c , STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/OCToggle/main.c , STM32F10x_StdPeriph_Examples/TIM/PWM_Output/main.c
  • CCR2Val : STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/main.c , STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_it.c
  • CCR3_Val : STM32F10x_StdPeriph_Examples/TIM/TimeBase/main.c , STM32F10x_StdPeriph_Examples/TIM/PWM_Output/main.c , STM32F10x_StdPeriph_Examples/TIM/6Steps/main.c , STM32F10x_StdPeriph_Examples/TIM/OCActive/main.c , STM32F10x_StdPeriph_Examples/TIM/OCInactive/main.c , STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/OCToggle/main.c
  • CCR4_Val : STM32F10x_StdPeriph_Examples/TIM/6Steps/main.c , STM32F10x_StdPeriph_Examples/TIM/OCInactive/main.c , STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/PWM_Output/main.c , STM32F10x_StdPeriph_Examples/TIM/TimeBase/main.c , STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/OCActive/main.c , STM32F10x_StdPeriph_Examples/TIM/OCToggle/main.c
  • CCR_CCR_Set : stm32f10x_i2c.c
  • CCR_CLEAR_Mask : stm32f10x_dma.c
  • CCR_FS_Set : stm32f10x_i2c.c
  • CEC : stm32f10x.h
  • CEC_BASE : stm32f10x.h
  • CEC_BitPeriodFlexibleMode : stm32f10x_cec.h
  • CEC_BitPeriodStdMode : stm32f10x_cec.h
  • CEC_BitTimingErrFreeMode : stm32f10x_cec.h
  • CEC_BitTimingStdMode : stm32f10x_cec.h
  • CEC_CFGR_BPEM : stm32f10x.h
  • CEC_CFGR_BTEM : stm32f10x.h
  • CEC_CFGR_IE : stm32f10x.h
  • CEC_CFGR_PE : stm32f10x.h
  • CEC_ClearFlag() : stm32f10x_cec.h , stm32f10x_cec.c
  • CEC_ClearITPendingBit() : stm32f10x_cec.c , stm32f10x_cec.h
  • CEC_Cmd() : stm32f10x_cec.h , stm32f10x_cec.c
  • CEC_CSR_RBTF : stm32f10x.h
  • CEC_CSR_REOM : stm32f10x.h
  • CEC_CSR_RERR : stm32f10x.h
  • CEC_CSR_RSOM : stm32f10x.h
  • CEC_CSR_TBTRF : stm32f10x.h
  • CEC_CSR_TEOM : stm32f10x.h
  • CEC_CSR_TERR : stm32f10x.h
  • CEC_CSR_TSOM : stm32f10x.h
  • CEC_DBG : stm32f10x_ip_dbg.c
  • CEC_DeInit() : stm32f10x_cec.h , stm32f10x_cec.c
  • CEC_DEVICE1 : STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_conf.h
  • CEC_EndOfMessageCmd() : stm32f10x_cec.c , stm32f10x_cec.h
  • CEC_ESR_ACKE : stm32f10x.h
  • CEC_ESR_BPE : stm32f10x.h
  • CEC_ESR_BTE : stm32f10x.h
  • CEC_ESR_LINE : stm32f10x.h
  • CEC_ESR_RBTFE : stm32f10x.h
  • CEC_ESR_SBE : stm32f10x.h
  • CEC_ESR_TBTFE : stm32f10x.h
  • CEC_FLAG_ACKE : stm32f10x_cec.h
  • CEC_FLAG_BPE : stm32f10x_cec.h
  • CEC_FLAG_BTE : stm32f10x_cec.h
  • CEC_FLAG_LINE : stm32f10x_cec.h
  • CEC_FLAG_RBTF : stm32f10x_cec.h
  • CEC_FLAG_RBTFE : stm32f10x_cec.h
  • CEC_FLAG_REOM : stm32f10x_cec.h
  • CEC_FLAG_RERR : stm32f10x_cec.h
  • CEC_FLAG_RSOM : stm32f10x_cec.h
  • CEC_FLAG_SBE : stm32f10x_cec.h
  • CEC_FLAG_TBTFE : stm32f10x_cec.h
  • CEC_FLAG_TBTRF : stm32f10x_cec.h
  • CEC_FLAG_TEOM : stm32f10x_cec.h
  • CEC_FLAG_TERR : stm32f10x_cec.h
  • CEC_GetFlagStatus() : stm32f10x_cec.h , stm32f10x_cec.c
  • CEC_GetITStatus() : stm32f10x_cec.h , stm32f10x_cec.c
  • CEC_Init() : stm32f10x_cec.h , stm32f10x_cec.c
  • CEC_InitStructure : STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/main.c
  • CEC_IRQHandler() : STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.c
  • CEC_IT_RBTF : stm32f10x_cec.h
  • CEC_IT_RERR : stm32f10x_cec.h
  • CEC_IT_TBTRF : stm32f10x_cec.h
  • CEC_IT_TERR : stm32f10x_cec.h
  • CEC_ITConfig() : stm32f10x_cec.c , stm32f10x_cec.h
  • CEC_OAR_OA : stm32f10x.h
  • CEC_OAR_OA_0 : stm32f10x.h
  • CEC_OAR_OA_1 : stm32f10x.h
  • CEC_OAR_OA_2 : stm32f10x.h
  • CEC_OAR_OA_3 : stm32f10x.h
  • CEC_OFFSET : stm32f10x_cec.c
  • CEC_OwnAddressConfig() : stm32f10x_cec.h , stm32f10x_cec.c
  • CEC_PRES_PRES : stm32f10x.h
  • CEC_ReceiveDataByte() : stm32f10x_cec.c , stm32f10x_cec.h
  • CEC_RXD_RXD : stm32f10x.h
  • CEC_SendDataByte() : stm32f10x_cec.h , stm32f10x_cec.c
  • CEC_SetPrescaler() : stm32f10x_cec.c , stm32f10x_cec.h
  • CEC_StartOfMessage() : stm32f10x_cec.c , stm32f10x_cec.h
  • CEC_TXD_TXD : stm32f10x.h
  • CECDevicesNumber : stm32100e_eval_cec.c , stm32100b_eval_cec.c
  • CFGR_ADCPRE_Reset_Mask : stm32f10x_rcc.c
  • CFGR_ADCPRE_Set_Mask : stm32f10x_rcc.c
  • CFGR_BYTE4_ADDRESS : stm32f10x_rcc.c
  • CFGR_CLEAR_Mask : stm32f10x_cec.c
  • CFGR_HPRE_Reset_Mask : stm32f10x_rcc.c
  • CFGR_HPRE_Set_Mask : stm32f10x_rcc.c
  • CFGR_IE_BB : stm32f10x_cec.c
  • CFGR_OFFSET : stm32f10x_rcc.c , stm32f10x_cec.c
  • CFGR_PE_BB : stm32f10x_cec.c
  • CFGR_PLL_Mask : stm32f10x_rcc.c
  • CFGR_PLLMull_Mask : stm32f10x_rcc.c
  • CFGR_PLLSRC_Mask : stm32f10x_rcc.c
  • CFGR_PLLXTPRE_Mask : stm32f10x_rcc.c
  • CFGR_PPRE1_Reset_Mask : stm32f10x_rcc.c
  • CFGR_PPRE1_Set_Mask : stm32f10x_rcc.c
  • CFGR_PPRE2_Reset_Mask : stm32f10x_rcc.c
  • CFGR_PPRE2_Set_Mask : stm32f10x_rcc.c
  • CFGR_SW_Mask : stm32f10x_rcc.c
  • CFGR_SWS_Mask : stm32f10x_rcc.c
  • CFGR_USBPRE_BB : stm32f10x_rcc.c
  • CFR_EWI_BB : stm32f10x_wwdg.c
  • CFR_OFFSET : stm32f10x_wwdg.c
  • CFR_W_Mask : stm32f10x_wwdg.c
  • CFR_WDGTB_Mask : stm32f10x_wwdg.c
  • Channel1Pulse : STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/main.c , STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/main.c
  • Channel2Pulse : STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/main.c , STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/main.c
  • Channel3Pulse : STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/main.c , STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/main.c
  • Channel4Pulse : STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/main.c
  • CheckBackupReg() : STM32F10x_StdPeriph_Examples/BKP/Tamper/main.c , STM32F10x_StdPeriph_Examples/BKP/Backup_Data/main.c
  • CheckITStatus() : stm32f10x_can.c
  • ChipErase_Timeout : stm3210e_eval_fsmc_nor.c
  • CID_Tab : stm32_eval_sdio_sd.c
  • CIR_BYTE2_ADDRESS : stm32f10x_rcc.c
  • CIR_BYTE3_ADDRESS : stm32f10x_rcc.c
  • CLEAR_BIT : stm32f10x.h
  • CLEAR_REG : stm32f10x.h
  • CLKCR_CLEAR_MASK : stm32f10x_sdio.c
  • CLKCR_CLKEN_BB : stm32f10x_sdio.c
  • CLKCR_OFFSET : stm32f10x_sdio.c
  • CLKEN_BitNumber : stm32f10x_sdio.c
  • ClockSpeed : STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/main.c
  • CMD_AREA : stm3210e_eval_fsmc_nand.h
  • CMD_ATACMD_BB : stm32f10x_sdio.c
  • CMD_CLEAR_MASK : stm32f10x_sdio.c
  • CMD_ENCMDCOMPL_BB : stm32f10x_sdio.c
  • CMD_NIEN_BB : stm32f10x_sdio.c
  • CMD_OFFSET : stm32f10x_sdio.c
  • CMD_SDIOSUSPEND_BB : stm32f10x_sdio.c
  • CmdError() : stm32_eval_sdio_sd.c
  • CmdResp1Error() : stm32_eval_sdio_sd.c
  • CmdResp2Error() : stm32_eval_sdio_sd.c
  • CmdResp3Error() : stm32_eval_sdio_sd.c
  • CmdResp6Error() : stm32_eval_sdio_sd.c
  • CmdResp7Error() : stm32_eval_sdio_sd.c
  • COM1 : stm32_eval.h
  • COM2 : stm32_eval.h
  • COM_RX_AF : stm32l152_eval.c
  • COM_RX_PIN : stm32100b_eval.c , stm3210c_eval.c , stm32l152_eval.c , stm3210e_eval.c , stm3210b_eval.c , stm32100e_eval.c
  • COM_RX_PIN_SOURCE : stm32l152_eval.c
  • COM_RX_PORT : stm32l152_eval.c , stm3210b_eval.c , stm3210e_eval.c , stm32100b_eval.c , stm3210c_eval.c , stm32100e_eval.c
  • COM_RX_PORT_CLK : stm3210c_eval.c , stm32100b_eval.c , stm32100e_eval.c , stm3210e_eval.c , stm3210b_eval.c , stm32l152_eval.c
  • COM_TX_AF : stm32l152_eval.c
  • COM_TX_PIN : stm32l152_eval.c , stm3210c_eval.c , stm3210b_eval.c , stm32100b_eval.c , stm32100e_eval.c , stm3210e_eval.c
  • COM_TX_PIN_SOURCE : stm32l152_eval.c
  • COM_TX_PORT : stm3210b_eval.c , stm32100b_eval.c , stm32100e_eval.c , stm32l152_eval.c , stm3210e_eval.c , stm3210c_eval.c
  • COM_TX_PORT_CLK : stm32100b_eval.c , stm3210c_eval.c , stm32l152_eval.c , stm3210e_eval.c , stm32100e_eval.c , stm3210b_eval.c
  • COM_TypeDef : stm32_eval.h
  • COM_USART : stm3210c_eval.c , stm32100b_eval.c , stm32100e_eval.c , stm3210e_eval.c , stm32l152_eval.c , stm3210b_eval.c
  • COM_USART_CLK : stm3210e_eval.c , stm3210c_eval.c , stm32100e_eval.c , stm32100b_eval.c , stm3210b_eval.c , stm32l152_eval.c
  • COMn : stm32100b_eval.h , stm32l152_eval.h , stm32100e_eval.h , stm3210c_eval.h , stm3210e_eval.h , stm3210b_eval.h
  • Convert() : stm32l152_eval_glass_lcd.c
  • convert_from_bytes_to_power_of_two() : stm32_eval_sdio_sd.c
  • Counter : STM32F10x_StdPeriph_Examples/USART/Smartcard/main.c
  • countof : STM32F10x_StdPeriph_Examples/USART/Polling/main.c , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/main.c , STM32F10x_StdPeriph_Examples/USART/HalfDuplex/main.c , STM32F10x_StdPeriph_Examples/I2C/EEPROM/main.c , STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/main.c , STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/main.c , STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c , STM32F10x_StdPeriph_Examples/USART/DMA_Polling/main.c , STM32F10x_StdPeriph_Examples/USART/Synchronous/main.c
  • CR1_ACK_Reset : stm32f10x_i2c.c
  • CR1_ACK_Set : stm32f10x_i2c.c
  • CR1_AWDCH_Reset : stm32f10x_adc.c
  • CR1_AWDMode_Reset : stm32f10x_adc.c
  • CR1_CLEAR_Mask : stm32f10x_usart.c , stm32f10x_spi.c , stm32f10x_adc.c , stm32f10x_i2c.c
  • CR1_CRCEN_Reset : stm32f10x_spi.c
  • CR1_CRCEN_Set : stm32f10x_spi.c
  • CR1_CRCNext_Set : stm32f10x_spi.c
  • CR1_DISCEN_Reset : stm32f10x_adc.c
  • CR1_DISCEN_Set : stm32f10x_adc.c
  • CR1_DISCNUM_Reset : stm32f10x_adc.c
  • CR1_ENARP_Reset : stm32f10x_i2c.c
  • CR1_ENARP_Set : stm32f10x_i2c.c
  • CR1_ENGC_Reset : stm32f10x_i2c.c
  • CR1_ENGC_Set : stm32f10x_i2c.c
  • CR1_ENPEC_Reset : stm32f10x_i2c.c
  • CR1_ENPEC_Set : stm32f10x_i2c.c
  • CR1_JAUTO_Reset : stm32f10x_adc.c
  • CR1_JAUTO_Set : stm32f10x_adc.c
  • CR1_JDISCEN_Reset : stm32f10x_adc.c
  • CR1_JDISCEN_Set : stm32f10x_adc.c
  • CR1_NOSTRETCH_Reset : stm32f10x_i2c.c
  • CR1_NOSTRETCH_Set : stm32f10x_i2c.c
  • CR1_OVER8_Reset : stm32f10x_usart.c
  • CR1_OVER8_Set : stm32f10x_usart.c
  • CR1_PE_Reset : stm32f10x_i2c.c
  • CR1_PE_Set : stm32f10x_i2c.c
  • CR1_PEC_Reset : stm32f10x_i2c.c
  • CR1_PEC_Set : stm32f10x_i2c.c
  • CR1_RWU_Reset : stm32f10x_usart.c
  • CR1_RWU_Set : stm32f10x_usart.c
  • CR1_SBK_Set : stm32f10x_usart.c
  • CR1_SPE_Reset : stm32f10x_spi.c
  • CR1_SPE_Set : stm32f10x_spi.c
  • CR1_START_Reset : stm32f10x_i2c.c
  • CR1_START_Set : stm32f10x_i2c.c
  • CR1_STOP_Reset : stm32f10x_i2c.c
  • CR1_STOP_Set : stm32f10x_i2c.c
  • CR1_SWRST_Reset : stm32f10x_i2c.c
  • CR1_SWRST_Set : stm32f10x_i2c.c
  • CR1_UE_Reset : stm32f10x_usart.c
  • CR1_UE_Set : stm32f10x_usart.c
  • CR1_WAKE_Mask : stm32f10x_usart.c
  • CR2_Address_Mask : stm32f10x_usart.c
  • CR2_ADON_Reset : stm32f10x_adc.c
  • CR2_ADON_Set : stm32f10x_adc.c
  • CR2_CAL_Set : stm32f10x_adc.c
  • CR2_CLEAR_Mask : stm32f10x_adc.c
  • CR2_CLOCK_CLEAR_Mask : stm32f10x_usart.c
  • CR2_DMA_Reset : stm32f10x_adc.c
  • CR2_DMA_Set : stm32f10x_adc.c
  • CR2_DMAEN_Reset : stm32f10x_i2c.c
  • CR2_DMAEN_Set : stm32f10x_i2c.c
  • CR2_EXTTRIG_Reset : stm32f10x_adc.c
  • CR2_EXTTRIG_Set : stm32f10x_adc.c
  • CR2_EXTTRIG_SWSTART_Reset : stm32f10x_adc.c
  • CR2_EXTTRIG_SWSTART_Set : stm32f10x_adc.c
  • CR2_FREQ_Reset : stm32f10x_i2c.c
  • CR2_JEXTSEL_Reset : stm32f10x_adc.c
  • CR2_JEXTTRIG_JSWSTART_Reset : stm32f10x_adc.c
  • CR2_JEXTTRIG_JSWSTART_Set : stm32f10x_adc.c
  • CR2_JEXTTRIG_Reset : stm32f10x_adc.c
  • CR2_JEXTTRIG_Set : stm32f10x_adc.c
  • CR2_JSWSTART_Set : stm32f10x_adc.c
  • CR2_LAST_Reset : stm32f10x_i2c.c
  • CR2_LAST_Set : stm32f10x_i2c.c
  • CR2_LBDL_Mask : stm32f10x_usart.c
  • CR2_LINEN_Reset : stm32f10x_usart.c
  • CR2_LINEN_Set : stm32f10x_usart.c
  • CR2_RSTCAL_Set : stm32f10x_adc.c
  • CR2_SSOE_Reset : stm32f10x_spi.c
  • CR2_SSOE_Set : stm32f10x_spi.c
  • CR2_STOP_CLEAR_Mask : stm32f10x_usart.c
  • CR2_SWSTART_Set : stm32f10x_adc.c
  • CR2_TSVREFE_Reset : stm32f10x_adc.c
  • CR2_TSVREFE_Set : stm32f10x_adc.c
  • CR3_CLEAR_Mask : stm32f10x_usart.c
  • CR3_HDSEL_Reset : stm32f10x_usart.c
  • CR3_HDSEL_Set : stm32f10x_usart.c
  • CR3_IREN_Reset : stm32f10x_usart.c
  • CR3_IREN_Set : stm32f10x_usart.c
  • CR3_IRLP_Mask : stm32f10x_usart.c
  • CR3_NACK_Reset : stm32f10x_usart.c
  • CR3_NACK_Set : stm32f10x_usart.c
  • CR3_ONEBITE_Reset : stm32f10x_usart.c
  • CR3_ONEBITE_Set : stm32f10x_usart.c
  • CR3_SCEN_Reset : stm32f10x_usart.c
  • CR3_SCEN_Set : stm32f10x_usart.c
  • CR_CLEAR_MASK : stm32f10x_dac.c
  • CR_CSSON_BB : stm32f10x_rcc.c
  • CR_DBP_BB : stm32f10x_pwr.c
  • CR_DS_MASK : stm32f10x_pwr.c
  • CR_HSEBYP_Reset : stm32f10x_rcc.c
  • CR_HSEBYP_Set : stm32f10x_rcc.c
  • CR_HSEON_Reset : stm32f10x_rcc.c
  • CR_HSEON_Set : stm32f10x_rcc.c
  • CR_HSION_BB : stm32f10x_rcc.c
  • CR_HSITRIM_Mask : stm32f10x_rcc.c
  • CR_LOCK_Set : stm32f10x_flash.c
  • CR_MER_Reset : stm32f10x_flash.c
  • CR_MER_Set : stm32f10x_flash.c
  • CR_OFFSET : stm32f10x_bkp.c , stm32f10x_rcc.c , stm32f10x_pwr.c
  • CR_OPTER_Reset : stm32f10x_flash.c
  • CR_OPTER_Set : stm32f10x_flash.c
  • CR_OPTPG_Reset : stm32f10x_flash.c
  • CR_OPTPG_Set : stm32f10x_flash.c
  • CR_PER_Reset : stm32f10x_flash.c
  • CR_PER_Set : stm32f10x_flash.c
  • CR_PG_Reset : stm32f10x_flash.c
  • CR_PG_Set : stm32f10x_flash.c
  • CR_PLLON_BB : stm32f10x_rcc.c
  • CR_PLS_MASK : stm32f10x_pwr.c
  • CR_PVDE_BB : stm32f10x_pwr.c
  • CR_STRT_Set : stm32f10x_flash.c
  • CR_TPAL_BB : stm32f10x_bkp.c
  • CR_TPE_BB : stm32f10x_bkp.c
  • CR_WDGA_Set : stm32f10x_wwdg.c
  • CRC : stm32f10x.h
  • CRC1Value : STM32F10x_StdPeriph_Examples/SPI/CRC/main.c
  • CRC2Value : STM32F10x_StdPeriph_Examples/SPI/CRC/main.c
  • CRC_BASE : stm32f10x.h
  • CRC_CalcBlockCRC() : stm32f10x_crc.c , stm32f10x_crc.h
  • CRC_CalcCRC() : stm32f10x_crc.c , stm32f10x_crc.h
  • CRC_CR_RESET : stm32f10x.h
  • CRC_DBG : stm32f10x_ip_dbg.c
  • CRC_DR_DR : stm32f10x.h
  • CRC_GetCRC() : stm32f10x_crc.c , stm32f10x_crc.h
  • CRC_GetIDRegister() : stm32f10x_crc.c , stm32f10x_crc.h
  • CRC_IDR_IDR : stm32f10x.h
  • CRC_ResetDR() : stm32f10x_crc.c , stm32f10x_crc.h
  • CRC_SetIDRegister() : stm32f10x_crc.h , stm32f10x_crc.c
  • CRCPolynomial : STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/main.c
  • CRCValue : STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/main.c
  • CSD_Tab : stm32_eval_sdio_sd.c
  • CSR_EWUP_BB : stm32f10x_pwr.c
  • CSR_LSION_BB : stm32f10x_rcc.c
  • CSR_OFFSET : stm32f10x_cec.c , stm32f10x_rcc.c , stm32f10x_bkp.c , stm32f10x_pwr.c
  • CSR_RMVF_Set : stm32f10x_rcc.c
  • CSR_TEF_BB : stm32f10x_bkp.c
  • CSR_TEOM_BB : stm32f10x_cec.c
  • CSR_TIF_BB : stm32f10x_bkp.c
  • CSR_TPIE_BB : stm32f10x_bkp.c
  • CSR_TSOM_BB : stm32f10x_cec.c
  • CSSON_BitNumber : stm32f10x_rcc.c
  • CurrDataCounterBegin : STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/main.c
  • CurrDataCounterEnd : STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/main.c
  • CurrentStack : STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/main.c
  • Cyan : stm32_eval.h


STM32F10x Standard Peripherals Firmware Library: Globals

  • File List
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  • Variables
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- d -

  • DAC : stm32f10x.h
  • DAC_Align_12b_L : stm32f10x_dac.h
  • DAC_Align_12b_R : stm32f10x_dac.h
  • DAC_Align_8b_R : stm32f10x_dac.h
  • DAC_BASE : stm32f10x.h
  • DAC_Channel_1 : stm32f10x_dac.h
  • DAC_Channel_2 : stm32f10x_dac.h
  • DAC_Cmd() : stm32f10x_dac.h , stm32f10x_dac.c
  • DAC_CR_BOFF1 : stm32f10x.h
  • DAC_CR_BOFF2 : stm32f10x.h
  • DAC_CR_DMAEN1 : stm32f10x.h
  • DAC_CR_DMAEN2 : stm32f10x.h
  • DAC_CR_EN1 : stm32f10x.h
  • DAC_CR_EN2 : stm32f10x.h
  • DAC_CR_MAMP1 : stm32f10x.h
  • DAC_CR_MAMP1_0 : stm32f10x.h
  • DAC_CR_MAMP1_1 : stm32f10x.h
  • DAC_CR_MAMP1_2 : stm32f10x.h
  • DAC_CR_MAMP1_3 : stm32f10x.h
  • DAC_CR_MAMP2 : stm32f10x.h
  • DAC_CR_MAMP2_0 : stm32f10x.h
  • DAC_CR_MAMP2_1 : stm32f10x.h
  • DAC_CR_MAMP2_2 : stm32f10x.h
  • DAC_CR_MAMP2_3 : stm32f10x.h
  • DAC_CR_TEN1 : stm32f10x.h
  • DAC_CR_TEN2 : stm32f10x.h
  • DAC_CR_TSEL1 : stm32f10x.h
  • DAC_CR_TSEL1_0 : stm32f10x.h
  • DAC_CR_TSEL1_1 : stm32f10x.h
  • DAC_CR_TSEL1_2 : stm32f10x.h
  • DAC_CR_TSEL2 : stm32f10x.h
  • DAC_CR_TSEL2_0 : stm32f10x.h
  • DAC_CR_TSEL2_1 : stm32f10x.h
  • DAC_CR_TSEL2_2 : stm32f10x.h
  • DAC_CR_WAVE1 : stm32f10x.h
  • DAC_CR_WAVE1_0 : stm32f10x.h
  • DAC_CR_WAVE1_1 : stm32f10x.h
  • DAC_CR_WAVE2 : stm32f10x.h
  • DAC_CR_WAVE2_0 : stm32f10x.h
  • DAC_CR_WAVE2_1 : stm32f10x.h
  • DAC_DBG : stm32f10x_ip_dbg.c
  • DAC_DeInit() : stm32f10x_dac.h , stm32f10x_dac.c
  • DAC_DHR12L1_DACC1DHR : stm32f10x.h
  • DAC_DHR12L2_DACC2DHR : stm32f10x.h
  • DAC_DHR12LD_DACC1DHR : stm32f10x.h
  • DAC_DHR12LD_DACC2DHR : stm32f10x.h
  • DAC_DHR12R1_DACC1DHR : stm32f10x.h
  • DAC_DHR12R2_DACC2DHR : stm32f10x.h
  • DAC_DHR12RD_Address : STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/main.c
  • DAC_DHR12RD_DACC1DHR : stm32f10x.h
  • DAC_DHR12RD_DACC2DHR : stm32f10x.h
  • DAC_DHR8R1_Address : STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/main.c
  • DAC_DHR8R1_DACC1DHR : stm32f10x.h
  • DAC_DHR8R2_DACC2DHR : stm32f10x.h
  • DAC_DHR8RD_DACC1DHR : stm32f10x.h
  • DAC_DHR8RD_DACC2DHR : stm32f10x.h
  • DAC_DMACmd() : stm32f10x_dac.h , stm32f10x_dac.c
  • DAC_DOR1_DACC1DOR : stm32f10x.h
  • DAC_DOR2_DACC2DOR : stm32f10x.h
  • DAC_DualSoftwareTriggerCmd() : stm32f10x_dac.c , stm32f10x_dac.h
  • DAC_GetDataOutputValue() : stm32f10x_dac.h , stm32f10x_dac.c
  • DAC_Init() : stm32f10x_dac.h , stm32f10x_dac.c
  • DAC_InitStructure : STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/main.c , STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/main.c , STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/main.c , STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/main.c
  • DAC_LFSRUnmask_Bit0 : stm32f10x_dac.h
  • DAC_LFSRUnmask_Bits10_0 : stm32f10x_dac.h
  • DAC_LFSRUnmask_Bits11_0 : stm32f10x_dac.h
  • DAC_LFSRUnmask_Bits1_0 : stm32f10x_dac.h
  • DAC_LFSRUnmask_Bits2_0 : stm32f10x_dac.h
  • DAC_LFSRUnmask_Bits3_0 : stm32f10x_dac.h
  • DAC_LFSRUnmask_Bits4_0 : stm32f10x_dac.h
  • DAC_LFSRUnmask_Bits5_0 : stm32f10x_dac.h
  • DAC_LFSRUnmask_Bits6_0 : stm32f10x_dac.h
  • DAC_LFSRUnmask_Bits7_0 : stm32f10x_dac.h
  • DAC_LFSRUnmask_Bits8_0 : stm32f10x_dac.h
  • DAC_LFSRUnmask_Bits9_0 : stm32f10x_dac.h
  • DAC_OutputBuffer_Disable : stm32f10x_dac.h
  • DAC_OutputBuffer_Enable : stm32f10x_dac.h
  • DAC_SetChannel1Data() : stm32f10x_dac.h , stm32f10x_dac.c
  • DAC_SetChannel2Data() : stm32f10x_dac.h , stm32f10x_dac.c
  • DAC_SetDualChannelData() : stm32f10x_dac.h , stm32f10x_dac.c
  • DAC_SoftwareTriggerCmd() : stm32f10x_dac.h , stm32f10x_dac.c
  • DAC_SR_DMAUDR1 : stm32f10x.h
  • DAC_SR_DMAUDR2 : stm32f10x.h
  • DAC_StructInit() : stm32f10x_dac.h , stm32f10x_dac.c
  • DAC_SWTRIGR_SWTRIG1 : stm32f10x.h
  • DAC_SWTRIGR_SWTRIG2 : stm32f10x.h
  • DAC_TriangleAmplitude_1 : stm32f10x_dac.h
  • DAC_TriangleAmplitude_1023 : stm32f10x_dac.h
  • DAC_TriangleAmplitude_127 : stm32f10x_dac.h
  • DAC_TriangleAmplitude_15 : stm32f10x_dac.h
  • DAC_TriangleAmplitude_2047 : stm32f10x_dac.h
  • DAC_TriangleAmplitude_255 : stm32f10x_dac.h
  • DAC_TriangleAmplitude_3 : stm32f10x_dac.h
  • DAC_TriangleAmplitude_31 : stm32f10x_dac.h
  • DAC_TriangleAmplitude_4095 : stm32f10x_dac.h
  • DAC_TriangleAmplitude_511 : stm32f10x_dac.h
  • DAC_TriangleAmplitude_63 : stm32f10x_dac.h
  • DAC_TriangleAmplitude_7 : stm32f10x_dac.h
  • DAC_Trigger_Ext_IT9 : stm32f10x_dac.h
  • DAC_Trigger_None : stm32f10x_dac.h
  • DAC_Trigger_Software : stm32f10x_dac.h
  • DAC_Trigger_T15_TRGO : stm32f10x_dac.h
  • DAC_Trigger_T2_TRGO : stm32f10x_dac.h
  • DAC_Trigger_T3_TRGO : stm32f10x_dac.h
  • DAC_Trigger_T4_TRGO : stm32f10x_dac.h
  • DAC_Trigger_T5_TRGO : stm32f10x_dac.h
  • DAC_Trigger_T6_TRGO : stm32f10x_dac.h
  • DAC_Trigger_T7_TRGO : stm32f10x_dac.h
  • DAC_Trigger_T8_TRGO : stm32f10x_dac.h
  • DAC_Wave_Noise : stm32f10x_dac.h
  • DAC_Wave_Triangle : stm32f10x_dac.h
  • DAC_WaveGeneration_Noise : stm32f10x_dac.h
  • DAC_WaveGeneration_None : stm32f10x_dac.h
  • DAC_WaveGeneration_Triangle : stm32f10x_dac.h
  • DAC_WaveGenerationCmd() : stm32f10x_dac.h , stm32f10x_dac.c
  • Data : STM32F10x_StdPeriph_Examples/FLASH/Program/main.c , STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/main.c
  • DATA_AREA : stm3210e_eval_fsmc_nand.h
  • DataBuffer : STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/main.c
  • DBGAFR_LOCATION_MASK : stm32f10x_gpio.c
  • DBGAFR_NUMBITS_MASK : stm32f10x_gpio.c
  • DBGAFR_POSITION_MASK : stm32f10x_gpio.c
  • DBGAFR_SWJCFG_MASK : stm32f10x_gpio.c
  • DBGMCU : stm32f10x.h
  • DBGMCU_BASE : stm32f10x.h
  • DBGMCU_CAN1_STOP : stm32f10x_dbgmcu.h
  • DBGMCU_CAN2_STOP : stm32f10x_dbgmcu.h
  • DBGMCU_Config() : stm32f10x_dbgmcu.h , stm32f10x_dbgmcu.c
  • DBGMCU_CR_DBG_CAN1_STOP : stm32f10x.h
  • DBGMCU_CR_DBG_CAN2_STOP : stm32f10x.h
  • DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT : stm32f10x.h
  • DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT : stm32f10x.h
  • DBGMCU_CR_DBG_IWDG_STOP : stm32f10x.h
  • DBGMCU_CR_DBG_SLEEP : stm32f10x.h
  • DBGMCU_CR_DBG_STANDBY : stm32f10x.h
  • DBGMCU_CR_DBG_STOP : stm32f10x.h
  • DBGMCU_CR_DBG_TIM10_STOP : stm32f10x.h
  • DBGMCU_CR_DBG_TIM11_STOP : stm32f10x.h
  • DBGMCU_CR_DBG_TIM12_STOP : stm32f10x.h
  • DBGMCU_CR_DBG_TIM13_STOP : stm32f10x.h
  • DBGMCU_CR_DBG_TIM14_STOP : stm32f10x.h
  • DBGMCU_CR_DBG_TIM15_STOP : stm32f10x.h
  • DBGMCU_CR_DBG_TIM16_STOP : stm32f10x.h
  • DBGMCU_CR_DBG_TIM17_STOP : stm32f10x.h
  • DBGMCU_CR_DBG_TIM1_STOP : stm32f10x.h
  • DBGMCU_CR_DBG_TIM2_STOP : stm32f10x.h
  • DBGMCU_CR_DBG_TIM3_STOP : stm32f10x.h
  • DBGMCU_CR_DBG_TIM4_STOP : stm32f10x.h
  • DBGMCU_CR_DBG_TIM5_STOP : stm32f10x.h
  • DBGMCU_CR_DBG_TIM6_STOP : stm32f10x.h
  • DBGMCU_CR_DBG_TIM7_STOP : stm32f10x.h
  • DBGMCU_CR_DBG_TIM8_STOP : stm32f10x.h
  • DBGMCU_CR_DBG_TIM9_STOP : stm32f10x.h
  • DBGMCU_CR_DBG_WWDG_STOP : stm32f10x.h
  • DBGMCU_CR_TRACE_IOEN : stm32f10x.h
  • DBGMCU_CR_TRACE_MODE : stm32f10x.h
  • DBGMCU_CR_TRACE_MODE_0 : stm32f10x.h
  • DBGMCU_CR_TRACE_MODE_1 : stm32f10x.h
  • DBGMCU_DBG : stm32f10x_ip_dbg.c
  • DBGMCU_GetDEVID() : stm32f10x_dbgmcu.h , stm32f10x_dbgmcu.c
  • DBGMCU_GetREVID() : stm32f10x_dbgmcu.h , stm32f10x_dbgmcu.c
  • DBGMCU_I2C1_SMBUS_TIMEOUT : stm32f10x_dbgmcu.h
  • DBGMCU_I2C2_SMBUS_TIMEOUT : stm32f10x_dbgmcu.h
  • DBGMCU_IDCODE_DEV_ID : stm32f10x.h
  • DBGMCU_IDCODE_REV_ID : stm32f10x.h
  • DBGMCU_IDCODE_REV_ID_0 : stm32f10x.h
  • DBGMCU_IDCODE_REV_ID_1 : stm32f10x.h
  • DBGMCU_IDCODE_REV_ID_10 : stm32f10x.h
  • DBGMCU_IDCODE_REV_ID_11 : stm32f10x.h
  • DBGMCU_IDCODE_REV_ID_12 : stm32f10x.h
  • DBGMCU_IDCODE_REV_ID_13 : stm32f10x.h
  • DBGMCU_IDCODE_REV_ID_14 : stm32f10x.h
  • DBGMCU_IDCODE_REV_ID_15 : stm32f10x.h
  • DBGMCU_IDCODE_REV_ID_2 : stm32f10x.h
  • DBGMCU_IDCODE_REV_ID_3 : stm32f10x.h
  • DBGMCU_IDCODE_REV_ID_4 : stm32f10x.h
  • DBGMCU_IDCODE_REV_ID_5 : stm32f10x.h
  • DBGMCU_IDCODE_REV_ID_6 : stm32f10x.h
  • DBGMCU_IDCODE_REV_ID_7 : stm32f10x.h
  • DBGMCU_IDCODE_REV_ID_8 : stm32f10x.h
  • DBGMCU_IDCODE_REV_ID_9 : stm32f10x.h
  • DBGMCU_IWDG_STOP : stm32f10x_dbgmcu.h
  • DBGMCU_SLEEP : stm32f10x_dbgmcu.h
  • DBGMCU_STANDBY : stm32f10x_dbgmcu.h
  • DBGMCU_STOP : stm32f10x_dbgmcu.h
  • DBGMCU_TIM10_STOP : stm32f10x_dbgmcu.h
  • DBGMCU_TIM11_STOP : stm32f10x_dbgmcu.h
  • DBGMCU_TIM12_STOP : stm32f10x_dbgmcu.h
  • DBGMCU_TIM13_STOP : stm32f10x_dbgmcu.h
  • DBGMCU_TIM14_STOP : stm32f10x_dbgmcu.h
  • DBGMCU_TIM15_STOP : stm32f10x_dbgmcu.h
  • DBGMCU_TIM16_STOP : stm32f10x_dbgmcu.h
  • DBGMCU_TIM17_STOP : stm32f10x_dbgmcu.h
  • DBGMCU_TIM1_STOP : stm32f10x_dbgmcu.h
  • DBGMCU_TIM2_STOP : stm32f10x_dbgmcu.h
  • DBGMCU_TIM3_STOP : stm32f10x_dbgmcu.h
  • DBGMCU_TIM4_STOP : stm32f10x_dbgmcu.h
  • DBGMCU_TIM5_STOP : stm32f10x_dbgmcu.h
  • DBGMCU_TIM6_STOP : stm32f10x_dbgmcu.h
  • DBGMCU_TIM7_STOP : stm32f10x_dbgmcu.h
  • DBGMCU_TIM8_STOP : stm32f10x_dbgmcu.h
  • DBGMCU_TIM9_STOP : stm32f10x_dbgmcu.h
  • DBGMCU_WWDG_STOP : stm32f10x_dbgmcu.h
  • DBP_BitNumber : stm32f10x_pwr.c
  • DCTRL_CLEAR_MASK : stm32f10x_sdio.c
  • DCTRL_DMAEN_BB : stm32f10x_sdio.c
  • DCTRL_OFFSET : stm32f10x_sdio.c
  • DCTRL_RWMOD_BB : stm32f10x_sdio.c
  • DCTRL_RWSTART_BB : stm32f10x_sdio.c
  • DCTRL_RWSTOP_BB : stm32f10x_sdio.c
  • DCTRL_SDIOEN_BB : stm32f10x_sdio.c
  • debug() : stm32f10x_ip_dbg.c , stm32f10x_ip_dbg.h
  • DebugMon_Handler() : STM32F10x_StdPeriph_Examples/CortexM3/BitBand/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CortexM3/BitBand/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CortexM3/MPU/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CortexM3/MPU/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/FSMC/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/FSMC/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FLASH/Program/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FLASH/Program/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/NAND/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/NAND/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/NOR/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/NOR/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/OneNAND/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/OneNAND/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/SRAM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/SRAM/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/GPIO/IOToggle/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/GPIO/IOToggle/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2C/EEPROM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2C/EEPROM/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2C/IOExpander/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2C/IOExpander/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/PWR/PVD/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/PWR/PVD/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/PWR/STANDBY/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/PWR/STANDBY/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/RTC/Calendar/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/RTC/Calendar/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SDIO/uSDCard/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SDIO/uSDCard/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/CRC/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SPI/CRC/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/DMA/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SPI/DMA/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SysTick/TimeBase/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SysTick/TimeBase/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/6Steps/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/6Steps/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/DMA/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/DMA/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/DMABurst/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/DMABurst/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/OCActive/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/OCActive/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/OCInactive/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/OCInactive/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/OnePulse/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/OnePulse/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/PWM_Input/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/PWM_Input/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/PWM_Output/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/PWM_Output/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/DMA_Polling/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/DMA_Polling/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/HalfDuplex/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/HalfDuplex/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/MultiProcessor/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/MultiProcessor/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Polling/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Polling/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Printf/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Printf/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Synchronous/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Synchronous/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_it.h , STM32F10x_StdPeriph_Template/stm32f10x_it.c , STM32F10x_StdPeriph_Template/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/BKP/Backup_Data/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/BKP/Backup_Data/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/BKP/Tamper/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/BKP/Tamper/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.h
  • DebugMonitor_IRQn : stm32f10x.h
  • Delay() : STM32F10x_StdPeriph_Examples/CAN/DualCAN/main.c , STM32F10x_StdPeriph_Examples/CAN/Networking/main.c , STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/main.c , STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/main.c , STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/main.c , STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/main.c , STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/main.c , STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/main.c , STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/main.c , STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/main.c , STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/main.c , STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/main.c , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/main.c , STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/main.c , STM32F10x_StdPeriph_Examples/PWR/STOP/main.c , STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/main.c , STM32F10x_StdPeriph_Examples/SysTick/TimeBase/main.c , STM32F10x_StdPeriph_Examples/USART/MultiProcessor/main.c , STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/main.c
  • delay() : stm32100b_eval_lcd.c , stm32100e_eval_ioe.c , stm32100e_eval_lcd.c , stm3210b_eval_lcd.c , stm3210c_eval_ioe.c , stm3210c_eval_lcd.c , stm3210e_eval_lcd.c , stm32l152_eval_glass_lcd.c , stm32l152_eval_lcd.c
  • DELAY_COUNT : STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/main.c
  • DeviceCount : stm32100b_eval_cec.c , stm32100e_eval_cec.c
  • DeviceType : stm32100b_eval_cec.c , stm32100e_eval_cec.c
  • DHR12R1_OFFSET : stm32f10x_dac.c
  • DHR12R2_OFFSET : stm32f10x_dac.c
  • DHR12RD_OFFSET : stm32f10x_dac.c
  • digit : stm32l152_eval_glass_lcd.c
  • Direction_IN : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • Direction_OUT : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • DISABLE : stm32f10x.h
  • DMA1 : stm32f10x.h
  • DMA1_BASE : stm32f10x.h
  • DMA1_Channel1 : stm32f10x.h
  • DMA1_Channel1_BASE : stm32f10x.h
  • DMA1_Channel1_DBG : stm32f10x_ip_dbg.c
  • DMA1_Channel1_IRQn : stm32f10x.h
  • DMA1_Channel1_IT_Mask : stm32f10x_dma.c
  • DMA1_Channel2 : stm32f10x.h
  • DMA1_Channel2_BASE : stm32f10x.h
  • DMA1_Channel2_DBG : stm32f10x_ip_dbg.c
  • DMA1_Channel2_IRQn : stm32f10x.h
  • DMA1_Channel2_IT_Mask : stm32f10x_dma.c
  • DMA1_Channel3 : stm32f10x.h
  • DMA1_Channel3_BASE : stm32f10x.h
  • DMA1_Channel3_DBG : stm32f10x_ip_dbg.c
  • DMA1_Channel3_IRQn : stm32f10x.h
  • DMA1_Channel3_IT_Mask : stm32f10x_dma.c
  • DMA1_Channel4 : stm32f10x.h
  • DMA1_Channel4_BASE : stm32f10x.h
  • DMA1_Channel4_DBG : stm32f10x_ip_dbg.c
  • DMA1_Channel4_IRQn : stm32f10x.h
  • DMA1_Channel4_IT_Mask : stm32f10x_dma.c
  • DMA1_Channel5 : stm32f10x.h
  • DMA1_Channel5_BASE : stm32f10x.h
  • DMA1_Channel5_DBG : stm32f10x_ip_dbg.c
  • DMA1_Channel5_IRQHandler() : STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_it.c
  • DMA1_Channel5_IRQn : stm32f10x.h
  • DMA1_Channel5_IT_Mask : stm32f10x_dma.c
  • DMA1_Channel6 : stm32f10x.h
  • DMA1_Channel6_BASE : stm32f10x.h
  • DMA1_Channel6_DBG : stm32f10x_ip_dbg.c
  • DMA1_Channel6_IRQHandler() : STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_it.h
  • DMA1_Channel6_IRQn : stm32f10x.h
  • DMA1_Channel6_IT_Mask : stm32f10x_dma.c
  • DMA1_Channel7 : stm32f10x.h
  • DMA1_Channel7_BASE : stm32f10x.h
  • DMA1_Channel7_DBG : stm32f10x_ip_dbg.c
  • DMA1_Channel7_IRQn : stm32f10x.h
  • DMA1_Channel7_IT_Mask : stm32f10x_dma.c
  • DMA1_DBG : stm32f10x_ip_dbg.c
  • DMA1_FLAG_GL1 : stm32f10x_dma.h
  • DMA1_FLAG_GL2 : stm32f10x_dma.h
  • DMA1_FLAG_GL3 : stm32f10x_dma.h
  • DMA1_FLAG_GL4 : stm32f10x_dma.h
  • DMA1_FLAG_GL5 : stm32f10x_dma.h
  • DMA1_FLAG_GL6 : stm32f10x_dma.h
  • DMA1_FLAG_GL7 : stm32f10x_dma.h
  • DMA1_FLAG_HT1 : stm32f10x_dma.h
  • DMA1_FLAG_HT2 : stm32f10x_dma.h
  • DMA1_FLAG_HT3 : stm32f10x_dma.h
  • DMA1_FLAG_HT4 : stm32f10x_dma.h
  • DMA1_FLAG_HT5 : stm32f10x_dma.h
  • DMA1_FLAG_HT6 : stm32f10x_dma.h
  • DMA1_FLAG_HT7 : stm32f10x_dma.h
  • DMA1_FLAG_TC1 : stm32f10x_dma.h
  • DMA1_FLAG_TC2 : stm32f10x_dma.h
  • DMA1_FLAG_TC3 : stm32f10x_dma.h
  • DMA1_FLAG_TC4 : stm32f10x_dma.h
  • DMA1_FLAG_TC5 : stm32f10x_dma.h
  • DMA1_FLAG_TC6 : stm32f10x_dma.h
  • DMA1_FLAG_TC7 : stm32f10x_dma.h
  • DMA1_FLAG_TE1 : stm32f10x_dma.h
  • DMA1_FLAG_TE2 : stm32f10x_dma.h
  • DMA1_FLAG_TE3 : stm32f10x_dma.h
  • DMA1_FLAG_TE4 : stm32f10x_dma.h
  • DMA1_FLAG_TE5 : stm32f10x_dma.h
  • DMA1_FLAG_TE6 : stm32f10x_dma.h
  • DMA1_FLAG_TE7 : stm32f10x_dma.h
  • DMA1_IT_GL1 : stm32f10x_dma.h
  • DMA1_IT_GL2 : stm32f10x_dma.h
  • DMA1_IT_GL3 : stm32f10x_dma.h
  • DMA1_IT_GL4 : stm32f10x_dma.h
  • DMA1_IT_GL5 : stm32f10x_dma.h
  • DMA1_IT_GL6 : stm32f10x_dma.h
  • DMA1_IT_GL7 : stm32f10x_dma.h
  • DMA1_IT_HT1 : stm32f10x_dma.h
  • DMA1_IT_HT2 : stm32f10x_dma.h
  • DMA1_IT_HT3 : stm32f10x_dma.h
  • DMA1_IT_HT4 : stm32f10x_dma.h
  • DMA1_IT_HT5 : stm32f10x_dma.h
  • DMA1_IT_HT6 : stm32f10x_dma.h
  • DMA1_IT_HT7 : stm32f10x_dma.h
  • DMA1_IT_TC1 : stm32f10x_dma.h
  • DMA1_IT_TC2 : stm32f10x_dma.h
  • DMA1_IT_TC3 : stm32f10x_dma.h
  • DMA1_IT_TC4 : stm32f10x_dma.h
  • DMA1_IT_TC5 : stm32f10x_dma.h
  • DMA1_IT_TC6 : stm32f10x_dma.h
  • DMA1_IT_TC7 : stm32f10x_dma.h
  • DMA1_IT_TE1 : stm32f10x_dma.h
  • DMA1_IT_TE2 : stm32f10x_dma.h
  • DMA1_IT_TE3 : stm32f10x_dma.h
  • DMA1_IT_TE4 : stm32f10x_dma.h
  • DMA1_IT_TE5 : stm32f10x_dma.h
  • DMA1_IT_TE6 : stm32f10x_dma.h
  • DMA1_IT_TE7 : stm32f10x_dma.h
  • DMA2 : stm32f10x.h
  • DMA2_BASE : stm32f10x.h
  • DMA2_Channel1 : stm32f10x.h
  • DMA2_Channel1_BASE : stm32f10x.h
  • DMA2_Channel1_DBG : stm32f10x_ip_dbg.c
  • DMA2_Channel1_IT_Mask : stm32f10x_dma.c
  • DMA2_Channel2 : stm32f10x.h
  • DMA2_Channel2_BASE : stm32f10x.h
  • DMA2_Channel2_DBG : stm32f10x_ip_dbg.c
  • DMA2_Channel2_IT_Mask : stm32f10x_dma.c
  • DMA2_Channel3 : stm32f10x.h
  • DMA2_Channel3_BASE : stm32f10x.h
  • DMA2_Channel3_DBG : stm32f10x_ip_dbg.c
  • DMA2_Channel3_IT_Mask : stm32f10x_dma.c
  • DMA2_Channel4 : stm32f10x.h
  • DMA2_Channel4_BASE : stm32f10x.h
  • DMA2_Channel4_DBG : stm32f10x_ip_dbg.c
  • DMA2_Channel4_IT_Mask : stm32f10x_dma.c
  • DMA2_Channel5 : stm32f10x.h
  • DMA2_Channel5_BASE : stm32f10x.h
  • DMA2_Channel5_DBG : stm32f10x_ip_dbg.c
  • DMA2_Channel5_IT_Mask : stm32f10x_dma.c
  • DMA2_DBG : stm32f10x_ip_dbg.c
  • DMA2_FLAG_GL1 : stm32f10x_dma.h
  • DMA2_FLAG_GL2 : stm32f10x_dma.h
  • DMA2_FLAG_GL3 : stm32f10x_dma.h
  • DMA2_FLAG_GL4 : stm32f10x_dma.h
  • DMA2_FLAG_GL5 : stm32f10x_dma.h
  • DMA2_FLAG_HT1 : stm32f10x_dma.h
  • DMA2_FLAG_HT2 : stm32f10x_dma.h
  • DMA2_FLAG_HT3 : stm32f10x_dma.h
  • DMA2_FLAG_HT4 : stm32f10x_dma.h
  • DMA2_FLAG_HT5 : stm32f10x_dma.h
  • DMA2_FLAG_TC1 : stm32f10x_dma.h
  • DMA2_FLAG_TC2 : stm32f10x_dma.h
  • DMA2_FLAG_TC3 : stm32f10x_dma.h
  • DMA2_FLAG_TC4 : stm32f10x_dma.h
  • DMA2_FLAG_TC5 : stm32f10x_dma.h
  • DMA2_FLAG_TE1 : stm32f10x_dma.h
  • DMA2_FLAG_TE2 : stm32f10x_dma.h
  • DMA2_FLAG_TE3 : stm32f10x_dma.h
  • DMA2_FLAG_TE4 : stm32f10x_dma.h
  • DMA2_FLAG_TE5 : stm32f10x_dma.h
  • DMA2_IT_GL1 : stm32f10x_dma.h
  • DMA2_IT_GL2 : stm32f10x_dma.h
  • DMA2_IT_GL3 : stm32f10x_dma.h
  • DMA2_IT_GL4 : stm32f10x_dma.h
  • DMA2_IT_GL5 : stm32f10x_dma.h
  • DMA2_IT_HT1 : stm32f10x_dma.h
  • DMA2_IT_HT2 : stm32f10x_dma.h
  • DMA2_IT_HT3 : stm32f10x_dma.h
  • DMA2_IT_HT4 : stm32f10x_dma.h
  • DMA2_IT_HT5 : stm32f10x_dma.h
  • DMA2_IT_TC1 : stm32f10x_dma.h
  • DMA2_IT_TC2 : stm32f10x_dma.h
  • DMA2_IT_TC3 : stm32f10x_dma.h
  • DMA2_IT_TC4 : stm32f10x_dma.h
  • DMA2_IT_TC5 : stm32f10x_dma.h
  • DMA2_IT_TE1 : stm32f10x_dma.h
  • DMA2_IT_TE2 : stm32f10x_dma.h
  • DMA2_IT_TE3 : stm32f10x_dma.h
  • DMA2_IT_TE4 : stm32f10x_dma.h
  • DMA2_IT_TE5 : stm32f10x_dma.h
  • DMA_CCR1_CIRC : stm32f10x.h
  • DMA_CCR1_DIR : stm32f10x.h
  • DMA_CCR1_EN : stm32f10x.h
  • DMA_CCR1_HTIE : stm32f10x.h
  • DMA_CCR1_MEM2MEM : stm32f10x.h
  • DMA_CCR1_MINC : stm32f10x.h
  • DMA_CCR1_MSIZE : stm32f10x.h
  • DMA_CCR1_MSIZE_0 : stm32f10x.h
  • DMA_CCR1_MSIZE_1 : stm32f10x.h
  • DMA_CCR1_PINC : stm32f10x.h
  • DMA_CCR1_PL : stm32f10x.h
  • DMA_CCR1_PL_0 : stm32f10x.h
  • DMA_CCR1_PL_1 : stm32f10x.h
  • DMA_CCR1_PSIZE : stm32f10x.h
  • DMA_CCR1_PSIZE_0 : stm32f10x.h
  • DMA_CCR1_PSIZE_1 : stm32f10x.h
  • DMA_CCR1_TCIE : stm32f10x.h
  • DMA_CCR1_TEIE : stm32f10x.h
  • DMA_CCR2_CIRC : stm32f10x.h
  • DMA_CCR2_DIR : stm32f10x.h
  • DMA_CCR2_EN : stm32f10x.h
  • DMA_CCR2_HTIE : stm32f10x.h
  • DMA_CCR2_MEM2MEM : stm32f10x.h
  • DMA_CCR2_MINC : stm32f10x.h
  • DMA_CCR2_MSIZE : stm32f10x.h
  • DMA_CCR2_MSIZE_0 : stm32f10x.h
  • DMA_CCR2_MSIZE_1 : stm32f10x.h
  • DMA_CCR2_PINC : stm32f10x.h
  • DMA_CCR2_PL : stm32f10x.h
  • DMA_CCR2_PL_0 : stm32f10x.h
  • DMA_CCR2_PL_1 : stm32f10x.h
  • DMA_CCR2_PSIZE : stm32f10x.h
  • DMA_CCR2_PSIZE_0 : stm32f10x.h
  • DMA_CCR2_PSIZE_1 : stm32f10x.h
  • DMA_CCR2_TCIE : stm32f10x.h
  • DMA_CCR2_TEIE : stm32f10x.h
  • DMA_CCR3_CIRC : stm32f10x.h
  • DMA_CCR3_DIR : stm32f10x.h
  • DMA_CCR3_EN : stm32f10x.h
  • DMA_CCR3_HTIE : stm32f10x.h
  • DMA_CCR3_MEM2MEM : stm32f10x.h
  • DMA_CCR3_MINC : stm32f10x.h
  • DMA_CCR3_MSIZE : stm32f10x.h
  • DMA_CCR3_MSIZE_0 : stm32f10x.h
  • DMA_CCR3_MSIZE_1 : stm32f10x.h
  • DMA_CCR3_PINC : stm32f10x.h
  • DMA_CCR3_PL : stm32f10x.h
  • DMA_CCR3_PL_0 : stm32f10x.h
  • DMA_CCR3_PL_1 : stm32f10x.h
  • DMA_CCR3_PSIZE : stm32f10x.h
  • DMA_CCR3_PSIZE_0 : stm32f10x.h
  • DMA_CCR3_PSIZE_1 : stm32f10x.h
  • DMA_CCR3_TCIE : stm32f10x.h
  • DMA_CCR3_TEIE : stm32f10x.h
  • DMA_CCR4_CIRC : stm32f10x.h
  • DMA_CCR4_DIR : stm32f10x.h
  • DMA_CCR4_EN : stm32f10x.h
  • DMA_CCR4_HTIE : stm32f10x.h
  • DMA_CCR4_MEM2MEM : stm32f10x.h
  • DMA_CCR4_MINC : stm32f10x.h
  • DMA_CCR4_MSIZE : stm32f10x.h
  • DMA_CCR4_MSIZE_0 : stm32f10x.h
  • DMA_CCR4_MSIZE_1 : stm32f10x.h
  • DMA_CCR4_PINC : stm32f10x.h
  • DMA_CCR4_PL : stm32f10x.h
  • DMA_CCR4_PL_0 : stm32f10x.h
  • DMA_CCR4_PL_1 : stm32f10x.h
  • DMA_CCR4_PSIZE : stm32f10x.h
  • DMA_CCR4_PSIZE_0 : stm32f10x.h
  • DMA_CCR4_PSIZE_1 : stm32f10x.h
  • DMA_CCR4_TCIE : stm32f10x.h
  • DMA_CCR4_TEIE : stm32f10x.h
  • DMA_CCR5_CIRC : stm32f10x.h
  • DMA_CCR5_DIR : stm32f10x.h
  • DMA_CCR5_EN : stm32f10x.h
  • DMA_CCR5_HTIE : stm32f10x.h
  • DMA_CCR5_MEM2MEM : stm32f10x.h
  • DMA_CCR5_MINC : stm32f10x.h
  • DMA_CCR5_MSIZE : stm32f10x.h
  • DMA_CCR5_MSIZE_0 : stm32f10x.h
  • DMA_CCR5_MSIZE_1 : stm32f10x.h
  • DMA_CCR5_PINC : stm32f10x.h
  • DMA_CCR5_PL : stm32f10x.h
  • DMA_CCR5_PL_0 : stm32f10x.h
  • DMA_CCR5_PL_1 : stm32f10x.h
  • DMA_CCR5_PSIZE : stm32f10x.h
  • DMA_CCR5_PSIZE_0 : stm32f10x.h
  • DMA_CCR5_PSIZE_1 : stm32f10x.h
  • DMA_CCR5_TCIE : stm32f10x.h
  • DMA_CCR5_TEIE : stm32f10x.h
  • DMA_CCR6_CIRC : stm32f10x.h
  • DMA_CCR6_DIR : stm32f10x.h
  • DMA_CCR6_EN : stm32f10x.h
  • DMA_CCR6_HTIE : stm32f10x.h
  • DMA_CCR6_MEM2MEM : stm32f10x.h
  • DMA_CCR6_MINC : stm32f10x.h
  • DMA_CCR6_MSIZE : stm32f10x.h
  • DMA_CCR6_MSIZE_0 : stm32f10x.h
  • DMA_CCR6_MSIZE_1 : stm32f10x.h
  • DMA_CCR6_PINC : stm32f10x.h
  • DMA_CCR6_PL : stm32f10x.h
  • DMA_CCR6_PL_0 : stm32f10x.h
  • DMA_CCR6_PL_1 : stm32f10x.h
  • DMA_CCR6_PSIZE : stm32f10x.h
  • DMA_CCR6_PSIZE_0 : stm32f10x.h
  • DMA_CCR6_PSIZE_1 : stm32f10x.h
  • DMA_CCR6_TCIE : stm32f10x.h
  • DMA_CCR6_TEIE : stm32f10x.h
  • DMA_CCR7_CIRC : stm32f10x.h
  • DMA_CCR7_DIR : stm32f10x.h
  • DMA_CCR7_EN : stm32f10x.h
  • DMA_CCR7_HTIE : stm32f10x.h
  • DMA_CCR7_MEM2MEM : stm32f10x.h
  • DMA_CCR7_MINC : stm32f10x.h
  • DMA_CCR7_MSIZE : stm32f10x.h
  • DMA_CCR7_MSIZE_0 : stm32f10x.h
  • DMA_CCR7_MSIZE_1 : stm32f10x.h
  • DMA_CCR7_PINC : stm32f10x.h
  • DMA_CCR7_PL : stm32f10x.h
  • DMA_CCR7_PL_0 : stm32f10x.h
  • DMA_CCR7_PL_1 : stm32f10x.h
  • DMA_CCR7_PSIZE : stm32f10x.h
  • DMA_CCR7_PSIZE_0 : stm32f10x.h
  • DMA_CCR7_PSIZE_1 : stm32f10x.h
  • DMA_CCR7_TCIE : stm32f10x.h
  • DMA_CCR7_TEIE : stm32f10x.h
  • DMA_ClearFlag() : stm32f10x_dma.c , stm32f10x_dma.h
  • DMA_ClearITPendingBit() : stm32f10x_dma.h , stm32f10x_dma.c
  • DMA_CMAR1_MA : stm32f10x.h
  • DMA_CMAR2_MA : stm32f10x.h
  • DMA_CMAR3_MA : stm32f10x.h
  • DMA_CMAR4_MA : stm32f10x.h
  • DMA_CMAR5_MA : stm32f10x.h
  • DMA_CMAR6_MA : stm32f10x.h
  • DMA_CMAR7_MA : stm32f10x.h
  • DMA_Cmd() : stm32f10x_dma.c , stm32f10x_dma.h
  • DMA_CNDTR1_NDT : stm32f10x.h
  • DMA_CNDTR2_NDT : stm32f10x.h
  • DMA_CNDTR3_NDT : stm32f10x.h
  • DMA_CNDTR4_NDT : stm32f10x.h
  • DMA_CNDTR5_NDT : stm32f10x.h
  • DMA_CNDTR6_NDT : stm32f10x.h
  • DMA_CNDTR7_NDT : stm32f10x.h
  • DMA_Configuration() : STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/main.c , STM32F10x_StdPeriph_Examples/USART/DMA_Polling/main.c , STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/main.c , STM32F10x_StdPeriph_Examples/TIM/DMA/main.c
  • DMA_CPAR1_PA : stm32f10x.h
  • DMA_CPAR2_PA : stm32f10x.h
  • DMA_CPAR3_PA : stm32f10x.h
  • DMA_CPAR4_PA : stm32f10x.h
  • DMA_CPAR5_PA : stm32f10x.h
  • DMA_CPAR6_PA : stm32f10x.h
  • DMA_CPAR7_PA : stm32f10x.h
  • DMA_DeInit() : stm32f10x_dma.c , stm32f10x_dma.h
  • DMA_DIR_PeripheralDST : stm32f10x_dma.h
  • DMA_DIR_PeripheralSRC : stm32f10x_dma.h
  • DMA_GetCurrDataCounter() : stm32f10x_dma.h , stm32f10x_dma.c
  • DMA_GetFlagStatus() : stm32f10x_dma.h , stm32f10x_dma.c
  • DMA_GetITStatus() : stm32f10x_dma.h , stm32f10x_dma.c
  • DMA_IFCR_CGIF1 : stm32f10x.h
  • DMA_IFCR_CGIF2 : stm32f10x.h
  • DMA_IFCR_CGIF3 : stm32f10x.h
  • DMA_IFCR_CGIF4 : stm32f10x.h
  • DMA_IFCR_CGIF5 : stm32f10x.h
  • DMA_IFCR_CGIF6 : stm32f10x.h
  • DMA_IFCR_CGIF7 : stm32f10x.h
  • DMA_IFCR_CHTIF1 : stm32f10x.h
  • DMA_IFCR_CHTIF2 : stm32f10x.h
  • DMA_IFCR_CHTIF3 : stm32f10x.h
  • DMA_IFCR_CHTIF4 : stm32f10x.h
  • DMA_IFCR_CHTIF5 : stm32f10x.h
  • DMA_IFCR_CHTIF6 : stm32f10x.h
  • DMA_IFCR_CHTIF7 : stm32f10x.h
  • DMA_IFCR_CTCIF1 : stm32f10x.h
  • DMA_IFCR_CTCIF2 : stm32f10x.h
  • DMA_IFCR_CTCIF3 : stm32f10x.h
  • DMA_IFCR_CTCIF4 : stm32f10x.h
  • DMA_IFCR_CTCIF5 : stm32f10x.h
  • DMA_IFCR_CTCIF6 : stm32f10x.h
  • DMA_IFCR_CTCIF7 : stm32f10x.h
  • DMA_IFCR_CTEIF1 : stm32f10x.h
  • DMA_IFCR_CTEIF2 : stm32f10x.h
  • DMA_IFCR_CTEIF3 : stm32f10x.h
  • DMA_IFCR_CTEIF4 : stm32f10x.h
  • DMA_IFCR_CTEIF5 : stm32f10x.h
  • DMA_IFCR_CTEIF6 : stm32f10x.h
  • DMA_IFCR_CTEIF7 : stm32f10x.h
  • DMA_Init() : stm32f10x_dma.c , stm32f10x_dma.h
  • DMA_InitStructure : STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/main.c , STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/main.c , STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/main.c , STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/main.c , STM32F10x_StdPeriph_Examples/DMA/FSMC/main.c , STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/main.c , STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/main.c , STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/main.c , STM32F10x_StdPeriph_Examples/TIM/DMABurst/main.c , STM32F10x_StdPeriph_Examples/SPI/DMA/main.c , STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/main.c , STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/main.c , STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/main.c , STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/main.c , STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c
  • DMA_ISR_GIF1 : stm32f10x.h
  • DMA_ISR_GIF2 : stm32f10x.h
  • DMA_ISR_GIF3 : stm32f10x.h
  • DMA_ISR_GIF4 : stm32f10x.h
  • DMA_ISR_GIF5 : stm32f10x.h
  • DMA_ISR_GIF6 : stm32f10x.h
  • DMA_ISR_GIF7 : stm32f10x.h
  • DMA_ISR_HTIF1 : stm32f10x.h
  • DMA_ISR_HTIF2 : stm32f10x.h
  • DMA_ISR_HTIF3 : stm32f10x.h
  • DMA_ISR_HTIF4 : stm32f10x.h
  • DMA_ISR_HTIF5 : stm32f10x.h
  • DMA_ISR_HTIF6 : stm32f10x.h
  • DMA_ISR_HTIF7 : stm32f10x.h
  • DMA_ISR_TCIF1 : stm32f10x.h
  • DMA_ISR_TCIF2 : stm32f10x.h
  • DMA_ISR_TCIF3 : stm32f10x.h
  • DMA_ISR_TCIF4 : stm32f10x.h
  • DMA_ISR_TCIF5 : stm32f10x.h
  • DMA_ISR_TCIF6 : stm32f10x.h
  • DMA_ISR_TCIF7 : stm32f10x.h
  • DMA_ISR_TEIF1 : stm32f10x.h
  • DMA_ISR_TEIF2 : stm32f10x.h
  • DMA_ISR_TEIF3 : stm32f10x.h
  • DMA_ISR_TEIF4 : stm32f10x.h
  • DMA_ISR_TEIF5 : stm32f10x.h
  • DMA_ISR_TEIF6 : stm32f10x.h
  • DMA_ISR_TEIF7 : stm32f10x.h
  • DMA_IT_HT : stm32f10x_dma.h
  • DMA_IT_TC : stm32f10x_dma.h
  • DMA_IT_TE : stm32f10x_dma.h
  • DMA_ITConfig() : stm32f10x_dma.h , stm32f10x_dma.c
  • DMA_M2M_Disable : stm32f10x_dma.h
  • DMA_M2M_Enable : stm32f10x_dma.h
  • DMA_MemoryDataSize_Byte : stm32f10x_dma.h
  • DMA_MemoryDataSize_HalfWord : stm32f10x_dma.h
  • DMA_MemoryDataSize_Word : stm32f10x_dma.h
  • DMA_MemoryInc_Disable : stm32f10x_dma.h
  • DMA_MemoryInc_Enable : stm32f10x_dma.h
  • DMA_Mode_Circular : stm32f10x_dma.h
  • DMA_Mode_Normal : stm32f10x_dma.h
  • DMA_PeripheralDataSize_Byte : stm32f10x_dma.h
  • DMA_PeripheralDataSize_HalfWord : stm32f10x_dma.h
  • DMA_PeripheralDataSize_Word : stm32f10x_dma.h
  • DMA_PeripheralInc_Disable : stm32f10x_dma.h
  • DMA_PeripheralInc_Enable : stm32f10x_dma.h
  • DMA_Priority_High : stm32f10x_dma.h
  • DMA_Priority_Low : stm32f10x_dma.h
  • DMA_Priority_Medium : stm32f10x_dma.h
  • DMA_Priority_VeryHigh : stm32f10x_dma.h
  • DMA_SetCurrDataCounter() : stm32f10x_dma.c , stm32f10x_dma.h
  • DMA_StructInit() : stm32f10x_dma.h , stm32f10x_dma.c
  • DMAEN_BitNumber : stm32f10x_sdio.c
  • DOR_OFFSET : stm32f10x_dac.c
  • DOWN_BUTTON_EXTI_IRQn : stm32l152_eval.h , stm3210e_eval.h , stm32100e_eval.h , stm32100b_eval.h , stm3210b_eval.h
  • DOWN_BUTTON_EXTI_LINE : stm32l152_eval.h , stm32100b_eval.h , stm3210b_eval.h , stm3210e_eval.h , stm32100e_eval.h
  • DOWN_BUTTON_EXTI_PIN_SOURCE : stm32l152_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210e_eval.h , stm32100b_eval.h
  • DOWN_BUTTON_EXTI_PORT_SOURCE : stm32100e_eval.h , stm3210e_eval.h , stm32100b_eval.h , stm3210b_eval.h , stm32l152_eval.h
  • DOWN_BUTTON_GPIO_CLK : stm32100e_eval.h , stm3210e_eval.h , stm3210b_eval.h , stm32l152_eval.h , stm32100b_eval.h
  • DOWN_BUTTON_GPIO_PORT : stm3210b_eval.h , stm32100b_eval.h , stm3210e_eval.h , stm32100e_eval.h , stm32l152_eval.h
  • DOWN_BUTTON_PIN : stm32l152_eval.h , stm32100e_eval.h , stm3210e_eval.h , stm3210b_eval.h , stm32100b_eval.h
  • DR_ADDRESS : stm32f10x_adc.c
  • DST_Buffer : STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/main.c , STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Smartcard/main.c , STM32F10x_StdPeriph_Examples/DMA/FSMC/main.c , STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/main.c
  • DUAL_SWTRIG_RESET : stm32f10x_dac.c
  • DUAL_SWTRIG_SET : stm32f10x_dac.c
  • DualSine12bit : STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/main.c
  • DutyCycle : STM32F10x_StdPeriph_Examples/TIM/PWM_Input/stm32f10x_it.c
  • DYMMY_BYTE : STM32F10x_StdPeriph_Examples/USART/Synchronous/main.c


STM32F10x Standard Peripherals Firmware Library: Globals

  • File List
  • Globals
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  • Functions
  • Variables
  • Typedefs
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- e -

  • eBuffercmp() : STM32F10x_StdPeriph_Examples/SDIO/uSDCard/main.c
  • EDGE_FALLING : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • EDGE_RISING : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • ENABLE : stm32f10x.h
  • ENABLE_LCD_MSG_DISPLAY : STM32F10x_StdPeriph_Examples/I2C/EEPROM/main.c
  • ENCMDCOMPL_BitNumber : stm32f10x_sdio.c
  • EraseCounter : STM32F10x_StdPeriph_Examples/FLASH/Program/main.c , STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/main.c
  • EraseStatus : STM32F10x_StdPeriph_Examples/SDIO/uSDCard/main.c
  • EraseTimeout : stm32f10x_flash.c
  • ERROR : stm32f10x.h
  • ErrorStatus : stm32f10x.h
  • Escalator8bit : STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/main.c
  • ETH : stm32f10x.h
  • ETH_BASE : stm32f10x.h
  • ETH_DMA_BASE : stm32f10x.h
  • ETH_MAC_BASE : stm32f10x.h
  • ETH_MMC_BASE : stm32f10x.h
  • ETH_PTP_BASE : stm32f10x.h
  • EVAL_COM1 : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210c_eval.h , stm3210e_eval.h , stm32l152_eval.h
  • EVAL_COM1_CLK : stm3210e_eval.h , stm32l152_eval.h , stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210c_eval.h
  • EVAL_COM1_CTS_AF : stm32l152_eval.h
  • EVAL_COM1_CTS_GPIO_CLK : stm32l152_eval.h
  • EVAL_COM1_CTS_GPIO_PORT : stm32l152_eval.h
  • EVAL_COM1_CTS_PIN : stm32l152_eval.h
  • EVAL_COM1_CTS_SOURCE : stm32l152_eval.h
  • EVAL_COM1_IRQn : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210c_eval.h , stm3210e_eval.h , stm32l152_eval.h
  • EVAL_COM1_RTS_AF : stm32l152_eval.h
  • EVAL_COM1_RTS_GPIO_CLK : stm32l152_eval.h
  • EVAL_COM1_RTS_GPIO_PORT : stm32l152_eval.h
  • EVAL_COM1_RTS_PIN : stm32l152_eval.h
  • EVAL_COM1_RTS_SOURCE : stm32l152_eval.h
  • EVAL_COM1_RX_AF : stm32l152_eval.h
  • EVAL_COM1_RX_GPIO_CLK : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210c_eval.h , stm3210e_eval.h , stm32l152_eval.h
  • EVAL_COM1_RX_GPIO_PORT : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210c_eval.h , stm3210e_eval.h , stm32l152_eval.h
  • EVAL_COM1_RX_PIN : stm32100e_eval.h , stm3210b_eval.h , stm3210c_eval.h , stm3210e_eval.h , stm32l152_eval.h , stm32100b_eval.h
  • EVAL_COM1_RX_SOURCE : stm32l152_eval.h
  • EVAL_COM1_TX_AF : stm32l152_eval.h
  • EVAL_COM1_TX_GPIO_CLK : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210c_eval.h , stm3210e_eval.h , stm32l152_eval.h
  • EVAL_COM1_TX_GPIO_PORT : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210c_eval.h , stm3210e_eval.h , stm32l152_eval.h
  • EVAL_COM1_TX_PIN : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210c_eval.h , stm3210e_eval.h , stm32l152_eval.h
  • EVAL_COM1_TX_SOURCE : stm32l152_eval.h
  • EVAL_COM2 : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210e_eval.h , stm32l152_eval.h
  • EVAL_COM2_CLK : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210e_eval.h , stm32l152_eval.h
  • EVAL_COM2_IRQn : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210e_eval.h , stm32l152_eval.h
  • EVAL_COM2_RX_AF : stm32l152_eval.h
  • EVAL_COM2_RX_GPIO_CLK : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210e_eval.h , stm32l152_eval.h
  • EVAL_COM2_RX_GPIO_PORT : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210e_eval.h , stm32l152_eval.h
  • EVAL_COM2_RX_PIN : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210e_eval.h , stm32l152_eval.h
  • EVAL_COM2_RX_SOURCE : stm32l152_eval.h
  • EVAL_COM2_TX_AF : stm32l152_eval.h
  • EVAL_COM2_TX_GPIO_CLK : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210e_eval.h , stm32l152_eval.h
  • EVAL_COM2_TX_GPIO_PORT : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210e_eval.h , stm32l152_eval.h
  • EVAL_COM2_TX_PIN : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210e_eval.h , stm32l152_eval.h
  • EVAL_COM2_TX_SOURCE : stm32l152_eval.h
  • EVCR_EVOE_BB : stm32f10x_gpio.c
  • EVCR_OFFSET : stm32f10x_gpio.c
  • EVCR_PORTPINCONFIG_MASK : stm32f10x_gpio.c
  • EVOE_BitNumber : stm32f10x_gpio.c
  • EWI_BitNumber : stm32f10x_wwdg.c
  • EWUP_BitNumber : stm32f10x_pwr.c
  • EXTI : stm32f10x.h
  • EXTI0_Config() : STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/main.c
  • EXTI0_IRQHandler() : STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/MultiProcessor/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/MultiProcessor/stm32f10x_it.h
  • EXTI0_IRQn : stm32f10x.h
  • EXTI15_10_IRQHandler() : STM32F10x_StdPeriph_Examples/I2C/IOExpander/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2C/IOExpander/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_it.h
  • EXTI1_IRQn : stm32f10x.h
  • EXTI2_IRQn : stm32f10x.h
  • EXTI3_IRQn : stm32f10x.h
  • EXTI4_IRQn : stm32f10x.h
  • EXTI9_5_Config() : STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/main.c
  • EXTI9_5_IRQHandler() : STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/PWR/STANDBY/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/PWR/STANDBY/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/MultiProcessor/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/MultiProcessor/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_it.h
  • EXTI_BASE : stm32f10x.h
  • EXTI_ClearFlag() : stm32f10x_exti.c , stm32f10x_exti.h
  • EXTI_ClearITPendingBit() : stm32f10x_exti.h , stm32f10x_exti.c
  • EXTI_Configuration() : STM32F10x_StdPeriph_Examples/PWR/PVD/main.c , STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/main.c , STM32F10x_StdPeriph_Examples/PWR/STOP/main.c , STM32F10x_StdPeriph_Examples/USART/Smartcard/main.c
  • EXTI_DBG : stm32f10x_ip_dbg.c
  • EXTI_DeInit() : stm32f10x_exti.h , stm32f10x_exti.c
  • EXTI_EMR_MR0 : stm32f10x.h
  • EXTI_EMR_MR1 : stm32f10x.h
  • EXTI_EMR_MR10 : stm32f10x.h
  • EXTI_EMR_MR11 : stm32f10x.h
  • EXTI_EMR_MR12 : stm32f10x.h
  • EXTI_EMR_MR13 : stm32f10x.h
  • EXTI_EMR_MR14 : stm32f10x.h
  • EXTI_EMR_MR15 : stm32f10x.h
  • EXTI_EMR_MR16 : stm32f10x.h
  • EXTI_EMR_MR17 : stm32f10x.h
  • EXTI_EMR_MR18 : stm32f10x.h
  • EXTI_EMR_MR19 : stm32f10x.h
  • EXTI_EMR_MR2 : stm32f10x.h
  • EXTI_EMR_MR3 : stm32f10x.h
  • EXTI_EMR_MR4 : stm32f10x.h
  • EXTI_EMR_MR5 : stm32f10x.h
  • EXTI_EMR_MR6 : stm32f10x.h
  • EXTI_EMR_MR7 : stm32f10x.h
  • EXTI_EMR_MR8 : stm32f10x.h
  • EXTI_EMR_MR9 : stm32f10x.h
  • EXTI_FTSR_TR0 : stm32f10x.h
  • EXTI_FTSR_TR1 : stm32f10x.h
  • EXTI_FTSR_TR10 : stm32f10x.h
  • EXTI_FTSR_TR11 : stm32f10x.h
  • EXTI_FTSR_TR12 : stm32f10x.h
  • EXTI_FTSR_TR13 : stm32f10x.h
  • EXTI_FTSR_TR14 : stm32f10x.h
  • EXTI_FTSR_TR15 : stm32f10x.h
  • EXTI_FTSR_TR16 : stm32f10x.h
  • EXTI_FTSR_TR17 : stm32f10x.h
  • EXTI_FTSR_TR18 : stm32f10x.h
  • EXTI_FTSR_TR19 : stm32f10x.h
  • EXTI_FTSR_TR2 : stm32f10x.h
  • EXTI_FTSR_TR3 : stm32f10x.h
  • EXTI_FTSR_TR4 : stm32f10x.h
  • EXTI_FTSR_TR5 : stm32f10x.h
  • EXTI_FTSR_TR6 : stm32f10x.h
  • EXTI_FTSR_TR7 : stm32f10x.h
  • EXTI_FTSR_TR8 : stm32f10x.h
  • EXTI_FTSR_TR9 : stm32f10x.h
  • EXTI_GenerateSWInterrupt() : stm32f10x_exti.h , stm32f10x_exti.c
  • EXTI_GetFlagStatus() : stm32f10x_exti.c , stm32f10x_exti.h
  • EXTI_GetITStatus() : stm32f10x_exti.c , stm32f10x_exti.h
  • EXTI_IMR_MR0 : stm32f10x.h
  • EXTI_IMR_MR1 : stm32f10x.h
  • EXTI_IMR_MR10 : stm32f10x.h
  • EXTI_IMR_MR11 : stm32f10x.h
  • EXTI_IMR_MR12 : stm32f10x.h
  • EXTI_IMR_MR13 : stm32f10x.h
  • EXTI_IMR_MR14 : stm32f10x.h
  • EXTI_IMR_MR15 : stm32f10x.h
  • EXTI_IMR_MR16 : stm32f10x.h
  • EXTI_IMR_MR17 : stm32f10x.h
  • EXTI_IMR_MR18 : stm32f10x.h
  • EXTI_IMR_MR19 : stm32f10x.h
  • EXTI_IMR_MR2 : stm32f10x.h
  • EXTI_IMR_MR3 : stm32f10x.h
  • EXTI_IMR_MR4 : stm32f10x.h
  • EXTI_IMR_MR5 : stm32f10x.h
  • EXTI_IMR_MR6 : stm32f10x.h
  • EXTI_IMR_MR7 : stm32f10x.h
  • EXTI_IMR_MR8 : stm32f10x.h
  • EXTI_IMR_MR9 : stm32f10x.h
  • EXTI_Init() : stm32f10x_exti.c , stm32f10x_exti.h
  • EXTI_InitStructure : STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/main.c
  • EXTI_Line0 : stm32f10x_exti.h
  • EXTI_Line1 : stm32f10x_exti.h
  • EXTI_Line10 : stm32f10x_exti.h
  • EXTI_Line11 : stm32f10x_exti.h
  • EXTI_Line12 : stm32f10x_exti.h
  • EXTI_Line13 : stm32f10x_exti.h
  • EXTI_Line14 : stm32f10x_exti.h
  • EXTI_Line15 : stm32f10x_exti.h
  • EXTI_Line16 : stm32f10x_exti.h
  • EXTI_Line17 : stm32f10x_exti.h
  • EXTI_Line18 : stm32f10x_exti.h
  • EXTI_Line19 : stm32f10x_exti.h
  • EXTI_Line2 : stm32f10x_exti.h
  • EXTI_Line3 : stm32f10x_exti.h
  • EXTI_Line4 : stm32f10x_exti.h
  • EXTI_Line5 : stm32f10x_exti.h
  • EXTI_Line6 : stm32f10x_exti.h
  • EXTI_Line7 : stm32f10x_exti.h
  • EXTI_Line8 : stm32f10x_exti.h
  • EXTI_Line9 : stm32f10x_exti.h
  • EXTI_LINENONE : stm32f10x_exti.c
  • EXTI_Mode_Event : stm32f10x_exti.h
  • EXTI_Mode_Interrupt : stm32f10x_exti.h
  • EXTI_PR_PR0 : stm32f10x.h
  • EXTI_PR_PR1 : stm32f10x.h
  • EXTI_PR_PR10 : stm32f10x.h
  • EXTI_PR_PR11 : stm32f10x.h
  • EXTI_PR_PR12 : stm32f10x.h
  • EXTI_PR_PR13 : stm32f10x.h
  • EXTI_PR_PR14 : stm32f10x.h
  • EXTI_PR_PR15 : stm32f10x.h
  • EXTI_PR_PR16 : stm32f10x.h
  • EXTI_PR_PR17 : stm32f10x.h
  • EXTI_PR_PR18 : stm32f10x.h
  • EXTI_PR_PR19 : stm32f10x.h
  • EXTI_PR_PR2 : stm32f10x.h
  • EXTI_PR_PR3 : stm32f10x.h
  • EXTI_PR_PR4 : stm32f10x.h
  • EXTI_PR_PR5 : stm32f10x.h
  • EXTI_PR_PR6 : stm32f10x.h
  • EXTI_PR_PR7 : stm32f10x.h
  • EXTI_PR_PR8 : stm32f10x.h
  • EXTI_PR_PR9 : stm32f10x.h
  • EXTI_RTSR_TR0 : stm32f10x.h
  • EXTI_RTSR_TR1 : stm32f10x.h
  • EXTI_RTSR_TR10 : stm32f10x.h
  • EXTI_RTSR_TR11 : stm32f10x.h
  • EXTI_RTSR_TR12 : stm32f10x.h
  • EXTI_RTSR_TR13 : stm32f10x.h
  • EXTI_RTSR_TR14 : stm32f10x.h
  • EXTI_RTSR_TR15 : stm32f10x.h
  • EXTI_RTSR_TR16 : stm32f10x.h
  • EXTI_RTSR_TR17 : stm32f10x.h
  • EXTI_RTSR_TR18 : stm32f10x.h
  • EXTI_RTSR_TR19 : stm32f10x.h
  • EXTI_RTSR_TR2 : stm32f10x.h
  • EXTI_RTSR_TR3 : stm32f10x.h
  • EXTI_RTSR_TR4 : stm32f10x.h
  • EXTI_RTSR_TR5 : stm32f10x.h
  • EXTI_RTSR_TR6 : stm32f10x.h
  • EXTI_RTSR_TR7 : stm32f10x.h
  • EXTI_RTSR_TR8 : stm32f10x.h
  • EXTI_RTSR_TR9 : stm32f10x.h
  • EXTI_StructInit() : stm32f10x_exti.h , stm32f10x_exti.c
  • EXTI_SWIER_SWIER0 : stm32f10x.h
  • EXTI_SWIER_SWIER1 : stm32f10x.h
  • EXTI_SWIER_SWIER10 : stm32f10x.h
  • EXTI_SWIER_SWIER11 : stm32f10x.h
  • EXTI_SWIER_SWIER12 : stm32f10x.h
  • EXTI_SWIER_SWIER13 : stm32f10x.h
  • EXTI_SWIER_SWIER14 : stm32f10x.h
  • EXTI_SWIER_SWIER15 : stm32f10x.h
  • EXTI_SWIER_SWIER16 : stm32f10x.h
  • EXTI_SWIER_SWIER17 : stm32f10x.h
  • EXTI_SWIER_SWIER18 : stm32f10x.h
  • EXTI_SWIER_SWIER19 : stm32f10x.h
  • EXTI_SWIER_SWIER2 : stm32f10x.h
  • EXTI_SWIER_SWIER3 : stm32f10x.h
  • EXTI_SWIER_SWIER4 : stm32f10x.h
  • EXTI_SWIER_SWIER5 : stm32f10x.h
  • EXTI_SWIER_SWIER6 : stm32f10x.h
  • EXTI_SWIER_SWIER7 : stm32f10x.h
  • EXTI_SWIER_SWIER8 : stm32f10x.h
  • EXTI_SWIER_SWIER9 : stm32f10x.h
  • EXTI_Trigger_Falling : stm32f10x_exti.h
  • EXTI_Trigger_Rising : stm32f10x_exti.h
  • EXTI_Trigger_Rising_Falling : stm32f10x_exti.h
  • EXTIMode_TypeDef : stm32f10x_exti.h
  • EXTITrigger_TypeDef : stm32f10x_exti.h


STM32F10x Standard Peripherals Firmware Library: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
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  • a
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  • f
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  • h
  • i
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  • l
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- f -

  • FAILED : STM32F10x_StdPeriph_Examples/CAN/LoopBack/main.c , STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/main.c , STM32F10x_StdPeriph_Examples/DMA/FSMC/main.c , STM32F10x_StdPeriph_Examples/FLASH/Program/main.c , STM32F10x_StdPeriph_Examples/SPI/DMA/main.c , STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/main.c , STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/main.c , STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/main.c , STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/main.c , STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/main.c , STM32F10x_StdPeriph_Examples/I2C/EEPROM/main.c , STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/main.c , STM32F10x_StdPeriph_Examples/USART/DMA_Polling/main.c , STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/main.c , STM32F10x_StdPeriph_Examples/USART/HalfDuplex/main.c , STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c , STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/main.c , STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/main.c , STM32F10x_StdPeriph_Examples/I2S/Interrupt/main.c , STM32F10x_StdPeriph_Examples/USART/Polling/main.c , STM32F10x_StdPeriph_Examples/USART/Smartcard/main.c , STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/main.c , STM32F10x_StdPeriph_Examples/USART/Synchronous/main.c , STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/main.c , STM32F10x_StdPeriph_Examples/SDIO/uSDCard/main.c , STM32F10x_StdPeriph_Examples/SPI/CRC/main.c
  • FeatureOpcode : stm32100b_eval_cec.c , stm32100e_eval_cec.c
  • Fill_Buffer() : STM32F10x_StdPeriph_Examples/SDIO/uSDCard/main.c , STM32F10x_StdPeriph_Examples/FSMC/NAND/main.c , STM32F10x_StdPeriph_Examples/FSMC/NOR/main.c , STM32F10x_StdPeriph_Examples/FSMC/SRAM/main.c
  • Fill_hBuffer() : STM32F10x_StdPeriph_Examples/FSMC/OneNAND/main.c
  • FindSCR() : stm32_eval_sdio_sd.c
  • FLAG_Mask : stm32f10x_cec.c , stm32f10x_dma.c , stm32f10x_i2c.c , stm32f10x_rcc.c
  • FlagStatus : stm32f10x.h
  • FLASH : stm32f10x.h
  • FLASH_ACR_HLFCYA : stm32f10x.h
  • FLASH_ACR_LATENCY : stm32f10x.h
  • FLASH_ACR_LATENCY_0 : stm32f10x.h
  • FLASH_ACR_LATENCY_1 : stm32f10x.h
  • FLASH_ACR_LATENCY_2 : stm32f10x.h
  • FLASH_ACR_PRFTBE : stm32f10x.h
  • FLASH_ACR_PRFTBS : stm32f10x.h
  • FLASH_ADDRESS_START : CortexM3/MPU/main.h
  • FLASH_AR_FAR : stm32f10x.h
  • FLASH_BANK1_END_ADDRESS : stm32f10x_flash.c
  • FLASH_BASE : stm32f10x.h
  • FLASH_BUSY : stm32f10x_flash.h
  • FLASH_ClearFlag() : stm32f10x_flash.h , stm32f10x_flash.c
  • FLASH_COMPLETE : stm32f10x_flash.h
  • FLASH_CR_EOPIE : stm32f10x.h
  • FLASH_CR_ERRIE : stm32f10x.h
  • FLASH_CR_LOCK : stm32f10x.h
  • FLASH_CR_MER : stm32f10x.h
  • FLASH_CR_OPTER : stm32f10x.h
  • FLASH_CR_OPTPG : stm32f10x.h
  • FLASH_CR_OPTWRE : stm32f10x.h
  • FLASH_CR_PER : stm32f10x.h
  • FLASH_CR_PG : stm32f10x.h
  • FLASH_CR_STRT : stm32f10x.h
  • FLASH_Data0_Data0 : stm32f10x.h
  • FLASH_Data0_nData0 : stm32f10x.h
  • FLASH_Data1_Data1 : stm32f10x.h
  • FLASH_Data1_nData1 : stm32f10x.h
  • FLASH_DBG : stm32f10x_ip_dbg.c
  • FLASH_EnableWriteProtection() : stm32f10x_flash.h , stm32f10x_flash.c
  • FLASH_EraseAllBank1Pages() : stm32f10x_flash.h , stm32f10x_flash.c
  • FLASH_EraseAllPages() : stm32f10x_flash.h , stm32f10x_flash.c
  • FLASH_EraseOptionBytes() : stm32f10x_flash.h , stm32f10x_flash.c
  • FLASH_ErasePage() : stm32f10x_flash.h , stm32f10x_flash.c
  • FLASH_ERROR_PG : stm32f10x_flash.h
  • FLASH_ERROR_WRP : stm32f10x_flash.h
  • FLASH_FLAG_BANK1_BSY : stm32f10x_flash.h
  • FLASH_FLAG_BANK1_EOP : stm32f10x_flash.h
  • FLASH_FLAG_BANK1_PGERR : stm32f10x_flash.h
  • FLASH_FLAG_BANK1_WRPRTERR : stm32f10x_flash.h
  • FLASH_FLAG_BSY : stm32f10x_flash.h
  • FLASH_FLAG_EOP : stm32f10x_flash.h
  • FLASH_FLAG_OPTERR : stm32f10x_flash.h
  • FLASH_FLAG_PGERR : stm32f10x_flash.h
  • FLASH_FLAG_WRPRTERR : stm32f10x_flash.h
  • FLASH_GetBank1Status() : stm32f10x_flash.h , stm32f10x_flash.c
  • FLASH_GetFlagStatus() : stm32f10x_flash.h , stm32f10x_flash.c
  • FLASH_GetPrefetchBufferStatus() : stm32f10x_flash.h , stm32f10x_flash.c
  • FLASH_GetReadOutProtectionStatus() : stm32f10x_flash.h , stm32f10x_flash.c
  • FLASH_GetStatus() : stm32f10x_flash.h , stm32f10x_flash.c
  • FLASH_GetUserOptionByte() : stm32f10x_flash.h , stm32f10x_flash.c
  • FLASH_GetWriteProtectionOptionByte() : stm32f10x_flash.h , stm32f10x_flash.c
  • FLASH_HalfCycleAccess_Disable : stm32f10x_flash.h
  • FLASH_HalfCycleAccess_Enable : stm32f10x_flash.h
  • FLASH_HalfCycleAccessCmd() : stm32f10x_flash.h , stm32f10x_flash.c
  • FLASH_IRQn : stm32f10x.h
  • FLASH_IT_BANK1_EOP : stm32f10x_flash.h
  • FLASH_IT_BANK1_ERROR : stm32f10x_flash.h
  • FLASH_IT_EOP : stm32f10x_flash.h
  • FLASH_IT_ERROR : stm32f10x_flash.h
  • FLASH_ITConfig() : stm32f10x_flash.h , stm32f10x_flash.c
  • FLASH_KEY1 : stm32f10x_flash.c
  • FLASH_KEY2 : stm32f10x_flash.c
  • FLASH_KEYR_FKEYR : stm32f10x.h
  • FLASH_Latency_0 : stm32f10x_flash.h
  • FLASH_Latency_1 : stm32f10x_flash.h
  • FLASH_Latency_2 : stm32f10x_flash.h
  • FLASH_Lock() : stm32f10x_flash.h , stm32f10x_flash.c
  • FLASH_LockBank1() : stm32f10x_flash.h , stm32f10x_flash.c
  • FLASH_OBR_BFB2 : stm32f10x.h
  • FLASH_OBR_nRST_STDBY : stm32f10x.h
  • FLASH_OBR_nRST_STOP : stm32f10x.h
  • FLASH_OBR_OPTERR : stm32f10x.h
  • FLASH_OBR_RDPRT : stm32f10x.h
  • FLASH_OBR_USER : stm32f10x.h
  • FLASH_OBR_WDG_SW : stm32f10x.h
  • FLASH_OPTKEYR_OPTKEYR : stm32f10x.h
  • FLASH_PAGE_SIZE : STM32F10x_StdPeriph_Examples/FLASH/Program/main.c , STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/main.c
  • FLASH_PAGES_TO_BE_PROTECTED : STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/main.c
  • FLASH_PrefetchBuffer_Disable : stm32f10x_flash.h
  • FLASH_PrefetchBuffer_Enable : stm32f10x_flash.h
  • FLASH_PrefetchBufferCmd() : stm32f10x_flash.h , stm32f10x_flash.c
  • FLASH_ProgramHalfWord() : stm32f10x_flash.h , stm32f10x_flash.c
  • FLASH_ProgramOptionByteData() : stm32f10x_flash.h , stm32f10x_flash.c
  • FLASH_ProgramWord() : stm32f10x_flash.h , stm32f10x_flash.c
  • FLASH_R_BASE : stm32f10x.h
  • FLASH_RDP_nRDP : stm32f10x.h
  • FLASH_RDP_RDP : stm32f10x.h
  • FLASH_ReadAddress : STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/main.c
  • FLASH_ReadOutProtection() : stm32f10x_flash.h , stm32f10x_flash.c
  • FLASH_REGION_NUMBER : CortexM3/MPU/main.h
  • FLASH_SectorToErase : STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/main.c
  • FLASH_SetLatency() : stm32f10x_flash.h , stm32f10x_flash.c
  • FLASH_SIZE : CortexM3/MPU/main.h
  • FLASH_SR_BSY : stm32f10x.h
  • FLASH_SR_EOP : stm32f10x.h
  • FLASH_SR_PGERR : stm32f10x.h
  • FLASH_SR_WRPRTERR : stm32f10x.h
  • FLASH_Status : stm32f10x_flash.h
  • FLASH_TIMEOUT : stm32f10x_flash.h
  • FLASH_Unlock() : stm32f10x_flash.h , stm32f10x_flash.c
  • FLASH_UnlockBank1() : stm32f10x_flash.h , stm32f10x_flash.c
  • FLASH_USER_nUSER : stm32f10x.h
  • FLASH_USER_USER : stm32f10x.h
  • FLASH_UserOptionByteConfig() : stm32f10x_flash.h , stm32f10x_flash.c
  • FLASH_WaitForLastBank1Operation() : stm32f10x_flash.h , stm32f10x_flash.c
  • FLASH_WaitForLastOperation() : stm32f10x_flash.h , stm32f10x_flash.c
  • FLASH_WriteAddress : STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/main.c
  • FLASH_WRP0_nWRP0 : stm32f10x.h
  • FLASH_WRP0_WRP0 : stm32f10x.h
  • FLASH_WRP1_nWRP1 : stm32f10x.h
  • FLASH_WRP1_WRP1 : stm32f10x.h
  • FLASH_WRP2_nWRP2 : stm32f10x.h
  • FLASH_WRP2_WRP2 : stm32f10x.h
  • FLASH_WRP3_nWRP3 : stm32f10x.h
  • FLASH_WRP3_WRP3 : stm32f10x.h
  • FLASH_WRPR_WRP : stm32f10x.h
  • FLASH_WRProt_AllPages : stm32f10x_flash.h
  • FLASH_WRProt_Pages0to1 : stm32f10x_flash.h
  • FLASH_WRProt_Pages0to3 : stm32f10x_flash.h
  • FLASH_WRProt_Pages100to103 : stm32f10x_flash.h
  • FLASH_WRProt_Pages104to107 : stm32f10x_flash.h
  • FLASH_WRProt_Pages108to111 : stm32f10x_flash.h
  • FLASH_WRProt_Pages10to11 : stm32f10x_flash.h
  • FLASH_WRProt_Pages112to115 : stm32f10x_flash.h
  • FLASH_WRProt_Pages116to119 : stm32f10x_flash.h
  • FLASH_WRProt_Pages120to123 : stm32f10x_flash.h
  • FLASH_WRProt_Pages124to127 : stm32f10x_flash.h
  • FLASH_WRProt_Pages12to13 : stm32f10x_flash.h
  • FLASH_WRProt_Pages12to15 : stm32f10x_flash.h
  • FLASH_WRProt_Pages14to15 : stm32f10x_flash.h
  • FLASH_WRProt_Pages16to17 : stm32f10x_flash.h
  • FLASH_WRProt_Pages16to19 : stm32f10x_flash.h
  • FLASH_WRProt_Pages18to19 : stm32f10x_flash.h
  • FLASH_WRProt_Pages20to21 : stm32f10x_flash.h
  • FLASH_WRProt_Pages20to23 : stm32f10x_flash.h
  • FLASH_WRProt_Pages22to23 : stm32f10x_flash.h
  • FLASH_WRProt_Pages24to25 : stm32f10x_flash.h
  • FLASH_WRProt_Pages24to27 : stm32f10x_flash.h
  • FLASH_WRProt_Pages26to27 : stm32f10x_flash.h
  • FLASH_WRProt_Pages28to29 : stm32f10x_flash.h
  • FLASH_WRProt_Pages28to31 : stm32f10x_flash.h
  • FLASH_WRProt_Pages2to3 : stm32f10x_flash.h
  • FLASH_WRProt_Pages30to31 : stm32f10x_flash.h
  • FLASH_WRProt_Pages32to33 : stm32f10x_flash.h
  • FLASH_WRProt_Pages32to35 : stm32f10x_flash.h
  • FLASH_WRProt_Pages34to35 : stm32f10x_flash.h
  • FLASH_WRProt_Pages36to37 : stm32f10x_flash.h
  • FLASH_WRProt_Pages36to39 : stm32f10x_flash.h
  • FLASH_WRProt_Pages38to39 : stm32f10x_flash.h
  • FLASH_WRProt_Pages40to41 : stm32f10x_flash.h
  • FLASH_WRProt_Pages40to43 : stm32f10x_flash.h
  • FLASH_WRProt_Pages42to43 : stm32f10x_flash.h
  • FLASH_WRProt_Pages44to45 : stm32f10x_flash.h
  • FLASH_WRProt_Pages44to47 : stm32f10x_flash.h
  • FLASH_WRProt_Pages46to47 : stm32f10x_flash.h
  • FLASH_WRProt_Pages48to49 : stm32f10x_flash.h
  • FLASH_WRProt_Pages48to51 : stm32f10x_flash.h
  • FLASH_WRProt_Pages4to5 : stm32f10x_flash.h
  • FLASH_WRProt_Pages4to7 : stm32f10x_flash.h
  • FLASH_WRProt_Pages50to51 : stm32f10x_flash.h
  • FLASH_WRProt_Pages52to53 : stm32f10x_flash.h
  • FLASH_WRProt_Pages52to55 : stm32f10x_flash.h
  • FLASH_WRProt_Pages54to55 : stm32f10x_flash.h
  • FLASH_WRProt_Pages56to57 : stm32f10x_flash.h
  • FLASH_WRProt_Pages56to59 : stm32f10x_flash.h
  • FLASH_WRProt_Pages58to59 : stm32f10x_flash.h
  • FLASH_WRProt_Pages60to61 : stm32f10x_flash.h
  • FLASH_WRProt_Pages60to63 : stm32f10x_flash.h
  • FLASH_WRProt_Pages62to127 : stm32f10x_flash.h
  • FLASH_WRProt_Pages62to255 : stm32f10x_flash.h
  • FLASH_WRProt_Pages62to511 : stm32f10x_flash.h
  • FLASH_WRProt_Pages64to67 : stm32f10x_flash.h
  • FLASH_WRProt_Pages68to71 : stm32f10x_flash.h
  • FLASH_WRProt_Pages6to7 : stm32f10x_flash.h
  • FLASH_WRProt_Pages72to75 : stm32f10x_flash.h
  • FLASH_WRProt_Pages76to79 : stm32f10x_flash.h
  • FLASH_WRProt_Pages80to83 : stm32f10x_flash.h
  • FLASH_WRProt_Pages84to87 : stm32f10x_flash.h
  • FLASH_WRProt_Pages88to91 : stm32f10x_flash.h
  • FLASH_WRProt_Pages8to11 : stm32f10x_flash.h
  • FLASH_WRProt_Pages8to9 : stm32f10x_flash.h
  • FLASH_WRProt_Pages92to95 : stm32f10x_flash.h
  • FLASH_WRProt_Pages96to99 : stm32f10x_flash.h
  • FlashID : STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/main.c
  • FLASHStatus : STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/main.c , STM32F10x_StdPeriph_Examples/FLASH/Program/main.c
  • FMR_FINIT : stm32f10x_can.c
  • FOLLOWER : STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_conf.h
  • Font12x12 : fonts.c , fonts.h
  • Font16x24 : fonts.c , fonts.h
  • Font8x12 : fonts.c , fonts.h
  • Font8x8 : fonts.c , fonts.h
  • Frequency : STM32F10x_StdPeriph_Examples/TIM/PWM_Input/stm32f10x_it.c
  • FSMC_AccessMode_A : stm32f10x_fsmc.h
  • FSMC_AccessMode_B : stm32f10x_fsmc.h
  • FSMC_AccessMode_C : stm32f10x_fsmc.h
  • FSMC_AccessMode_D : stm32f10x_fsmc.h
  • FSMC_AsynchronousWait_Disable : stm32f10x_fsmc.h
  • FSMC_AsynchronousWait_Enable : stm32f10x_fsmc.h
  • FSMC_Bank1 : stm32f10x.h
  • FSMC_Bank1_DBG : stm32f10x_ip_dbg.c
  • FSMC_Bank1_NORSRAM1 : stm32f10x_fsmc.h
  • FSMC_Bank1_NORSRAM2 : stm32f10x_fsmc.h
  • FSMC_Bank1_NORSRAM3 : stm32f10x_fsmc.h
  • FSMC_Bank1_NORSRAM4 : stm32f10x_fsmc.h
  • FSMC_Bank1_R_BASE : stm32f10x.h
  • FSMC_Bank1E : stm32f10x.h
  • FSMC_Bank1E_DBG : stm32f10x_ip_dbg.c
  • FSMC_Bank1E_R_BASE : stm32f10x.h
  • FSMC_Bank2 : stm32f10x.h
  • FSMC_Bank2_DBG : stm32f10x_ip_dbg.c
  • FSMC_Bank2_NAND : stm32f10x_fsmc.h
  • FSMC_Bank2_R_BASE : stm32f10x.h
  • FSMC_Bank3 : stm32f10x.h
  • FSMC_Bank3_DBG : stm32f10x_ip_dbg.c
  • FSMC_Bank3_NAND : stm32f10x_fsmc.h
  • FSMC_Bank3_R_BASE : stm32f10x.h
  • FSMC_Bank4 : stm32f10x.h
  • FSMC_Bank4_DBG : stm32f10x_ip_dbg.c
  • FSMC_Bank4_PCCARD : stm32f10x_fsmc.h
  • FSMC_Bank4_R_BASE : stm32f10x.h
  • FSMC_Bank_NAND : stm3210e_eval_fsmc_nand.c
  • FSMC_BCR1_ASYNCWAIT : stm32f10x.h
  • FSMC_BCR1_BURSTEN : stm32f10x.h
  • FSMC_BCR1_CBURSTRW : stm32f10x.h
  • FSMC_BCR1_EXTMOD : stm32f10x.h
  • FSMC_BCR1_FACCEN : stm32f10x.h
  • FSMC_BCR1_MBKEN : stm32f10x.h
  • FSMC_BCR1_MTYP : stm32f10x.h
  • FSMC_BCR1_MTYP_0 : stm32f10x.h
  • FSMC_BCR1_MTYP_1 : stm32f10x.h
  • FSMC_BCR1_MUXEN : stm32f10x.h
  • FSMC_BCR1_MWID : stm32f10x.h
  • FSMC_BCR1_MWID_0 : stm32f10x.h
  • FSMC_BCR1_MWID_1 : stm32f10x.h
  • FSMC_BCR1_WAITCFG : stm32f10x.h
  • FSMC_BCR1_WAITEN : stm32f10x.h
  • FSMC_BCR1_WAITPOL : stm32f10x.h
  • FSMC_BCR1_WRAPMOD : stm32f10x.h
  • FSMC_BCR1_WREN : stm32f10x.h
  • FSMC_BCR2_ASYNCWAIT : stm32f10x.h
  • FSMC_BCR2_BURSTEN : stm32f10x.h
  • FSMC_BCR2_CBURSTRW : stm32f10x.h
  • FSMC_BCR2_EXTMOD : stm32f10x.h
  • FSMC_BCR2_FACCEN : stm32f10x.h
  • FSMC_BCR2_MBKEN : stm32f10x.h
  • FSMC_BCR2_MTYP : stm32f10x.h
  • FSMC_BCR2_MTYP_0 : stm32f10x.h
  • FSMC_BCR2_MTYP_1 : stm32f10x.h
  • FSMC_BCR2_MUXEN : stm32f10x.h
  • FSMC_BCR2_MWID : stm32f10x.h
  • FSMC_BCR2_MWID_0 : stm32f10x.h
  • FSMC_BCR2_MWID_1 : stm32f10x.h
  • FSMC_BCR2_WAITCFG : stm32f10x.h
  • FSMC_BCR2_WAITEN : stm32f10x.h
  • FSMC_BCR2_WAITPOL : stm32f10x.h
  • FSMC_BCR2_WRAPMOD : stm32f10x.h
  • FSMC_BCR2_WREN : stm32f10x.h
  • FSMC_BCR3_ASYNCWAIT : stm32f10x.h
  • FSMC_BCR3_BURSTEN : stm32f10x.h
  • FSMC_BCR3_CBURSTRW : stm32f10x.h
  • FSMC_BCR3_EXTMOD : stm32f10x.h
  • FSMC_BCR3_FACCEN : stm32f10x.h
  • FSMC_BCR3_MBKEN : stm32f10x.h
  • FSMC_BCR3_MTYP : stm32f10x.h
  • FSMC_BCR3_MTYP_0 : stm32f10x.h
  • FSMC_BCR3_MTYP_1 : stm32f10x.h
  • FSMC_BCR3_MUXEN : stm32f10x.h
  • FSMC_BCR3_MWID : stm32f10x.h
  • FSMC_BCR3_MWID_0 : stm32f10x.h
  • FSMC_BCR3_MWID_1 : stm32f10x.h
  • FSMC_BCR3_WAITCFG : stm32f10x.h
  • FSMC_BCR3_WAITEN : stm32f10x.h
  • FSMC_BCR3_WAITPOL : stm32f10x.h
  • FSMC_BCR3_WRAPMOD : stm32f10x.h
  • FSMC_BCR3_WREN : stm32f10x.h
  • FSMC_BCR4_ASYNCWAIT : stm32f10x.h
  • FSMC_BCR4_BURSTEN : stm32f10x.h
  • FSMC_BCR4_CBURSTRW : stm32f10x.h
  • FSMC_BCR4_EXTMOD : stm32f10x.h
  • FSMC_BCR4_FACCEN : stm32f10x.h
  • FSMC_BCR4_MBKEN : stm32f10x.h
  • FSMC_BCR4_MTYP : stm32f10x.h
  • FSMC_BCR4_MTYP_0 : stm32f10x.h
  • FSMC_BCR4_MTYP_1 : stm32f10x.h
  • FSMC_BCR4_MUXEN : stm32f10x.h
  • FSMC_BCR4_MWID : stm32f10x.h
  • FSMC_BCR4_MWID_0 : stm32f10x.h
  • FSMC_BCR4_MWID_1 : stm32f10x.h
  • FSMC_BCR4_WAITCFG : stm32f10x.h
  • FSMC_BCR4_WAITEN : stm32f10x.h
  • FSMC_BCR4_WAITPOL : stm32f10x.h
  • FSMC_BCR4_WRAPMOD : stm32f10x.h
  • FSMC_BCR4_WREN : stm32f10x.h
  • FSMC_BTR1_ACCMOD : stm32f10x.h
  • FSMC_BTR1_ACCMOD_0 : stm32f10x.h
  • FSMC_BTR1_ACCMOD_1 : stm32f10x.h
  • FSMC_BTR1_ADDHLD : stm32f10x.h
  • FSMC_BTR1_ADDHLD_0 : stm32f10x.h
  • FSMC_BTR1_ADDHLD_1 : stm32f10x.h
  • FSMC_BTR1_ADDHLD_2 : stm32f10x.h
  • FSMC_BTR1_ADDHLD_3 : stm32f10x.h
  • FSMC_BTR1_ADDSET : stm32f10x.h
  • FSMC_BTR1_ADDSET_0 : stm32f10x.h
  • FSMC_BTR1_ADDSET_1 : stm32f10x.h
  • FSMC_BTR1_ADDSET_2 : stm32f10x.h
  • FSMC_BTR1_ADDSET_3 : stm32f10x.h
  • FSMC_BTR1_BUSTURN : stm32f10x.h
  • FSMC_BTR1_BUSTURN_0 : stm32f10x.h
  • FSMC_BTR1_BUSTURN_1 : stm32f10x.h
  • FSMC_BTR1_BUSTURN_2 : stm32f10x.h
  • FSMC_BTR1_BUSTURN_3 : stm32f10x.h
  • FSMC_BTR1_CLKDIV : stm32f10x.h
  • FSMC_BTR1_CLKDIV_0 : stm32f10x.h
  • FSMC_BTR1_CLKDIV_1 : stm32f10x.h
  • FSMC_BTR1_CLKDIV_2 : stm32f10x.h
  • FSMC_BTR1_CLKDIV_3 : stm32f10x.h
  • FSMC_BTR1_DATAST : stm32f10x.h
  • FSMC_BTR1_DATAST_0 : stm32f10x.h
  • FSMC_BTR1_DATAST_1 : stm32f10x.h
  • FSMC_BTR1_DATAST_2 : stm32f10x.h
  • FSMC_BTR1_DATAST_3 : stm32f10x.h
  • FSMC_BTR1_DATLAT : stm32f10x.h
  • FSMC_BTR1_DATLAT_0 : stm32f10x.h
  • FSMC_BTR1_DATLAT_1 : stm32f10x.h
  • FSMC_BTR1_DATLAT_2 : stm32f10x.h
  • FSMC_BTR1_DATLAT_3 : stm32f10x.h
  • FSMC_BTR2_ACCMOD : stm32f10x.h
  • FSMC_BTR2_ACCMOD_0 : stm32f10x.h
  • FSMC_BTR2_ACCMOD_1 : stm32f10x.h
  • FSMC_BTR2_ADDHLD : stm32f10x.h
  • FSMC_BTR2_ADDHLD_0 : stm32f10x.h
  • FSMC_BTR2_ADDHLD_1 : stm32f10x.h
  • FSMC_BTR2_ADDHLD_2 : stm32f10x.h
  • FSMC_BTR2_ADDHLD_3 : stm32f10x.h
  • FSMC_BTR2_ADDSET : stm32f10x.h
  • FSMC_BTR2_ADDSET_0 : stm32f10x.h
  • FSMC_BTR2_ADDSET_1 : stm32f10x.h
  • FSMC_BTR2_ADDSET_2 : stm32f10x.h
  • FSMC_BTR2_ADDSET_3 : stm32f10x.h
  • FSMC_BTR2_BUSTURN : stm32f10x.h
  • FSMC_BTR2_BUSTURN_0 : stm32f10x.h
  • FSMC_BTR2_BUSTURN_1 : stm32f10x.h
  • FSMC_BTR2_BUSTURN_2 : stm32f10x.h
  • FSMC_BTR2_BUSTURN_3 : stm32f10x.h
  • FSMC_BTR2_CLKDIV : stm32f10x.h
  • FSMC_BTR2_CLKDIV_0 : stm32f10x.h
  • FSMC_BTR2_CLKDIV_1 : stm32f10x.h
  • FSMC_BTR2_CLKDIV_2 : stm32f10x.h
  • FSMC_BTR2_CLKDIV_3 : stm32f10x.h
  • FSMC_BTR2_DATAST : stm32f10x.h
  • FSMC_BTR2_DATAST_0 : stm32f10x.h
  • FSMC_BTR2_DATAST_1 : stm32f10x.h
  • FSMC_BTR2_DATAST_2 : stm32f10x.h
  • FSMC_BTR2_DATAST_3 : stm32f10x.h
  • FSMC_BTR2_DATLAT : stm32f10x.h
  • FSMC_BTR2_DATLAT_0 : stm32f10x.h
  • FSMC_BTR2_DATLAT_1 : stm32f10x.h
  • FSMC_BTR2_DATLAT_2 : stm32f10x.h
  • FSMC_BTR2_DATLAT_3 : stm32f10x.h
  • FSMC_BTR3_ACCMOD : stm32f10x.h
  • FSMC_BTR3_ACCMOD_0 : stm32f10x.h
  • FSMC_BTR3_ACCMOD_1 : stm32f10x.h
  • FSMC_BTR3_ADDHLD : stm32f10x.h
  • FSMC_BTR3_ADDHLD_0 : stm32f10x.h
  • FSMC_BTR3_ADDHLD_1 : stm32f10x.h
  • FSMC_BTR3_ADDHLD_2 : stm32f10x.h
  • FSMC_BTR3_ADDHLD_3 : stm32f10x.h
  • FSMC_BTR3_ADDSET : stm32f10x.h
  • FSMC_BTR3_ADDSET_0 : stm32f10x.h
  • FSMC_BTR3_ADDSET_1 : stm32f10x.h
  • FSMC_BTR3_ADDSET_2 : stm32f10x.h
  • FSMC_BTR3_ADDSET_3 : stm32f10x.h
  • FSMC_BTR3_BUSTURN : stm32f10x.h
  • FSMC_BTR3_BUSTURN_0 : stm32f10x.h
  • FSMC_BTR3_BUSTURN_1 : stm32f10x.h
  • FSMC_BTR3_BUSTURN_2 : stm32f10x.h
  • FSMC_BTR3_BUSTURN_3 : stm32f10x.h
  • FSMC_BTR3_CLKDIV : stm32f10x.h
  • FSMC_BTR3_CLKDIV_0 : stm32f10x.h
  • FSMC_BTR3_CLKDIV_1 : stm32f10x.h
  • FSMC_BTR3_CLKDIV_2 : stm32f10x.h
  • FSMC_BTR3_CLKDIV_3 : stm32f10x.h
  • FSMC_BTR3_DATAST : stm32f10x.h
  • FSMC_BTR3_DATAST_0 : stm32f10x.h
  • FSMC_BTR3_DATAST_1 : stm32f10x.h
  • FSMC_BTR3_DATAST_2 : stm32f10x.h
  • FSMC_BTR3_DATAST_3 : stm32f10x.h
  • FSMC_BTR3_DATLAT : stm32f10x.h
  • FSMC_BTR3_DATLAT_0 : stm32f10x.h
  • FSMC_BTR3_DATLAT_1 : stm32f10x.h
  • FSMC_BTR3_DATLAT_2 : stm32f10x.h
  • FSMC_BTR3_DATLAT_3 : stm32f10x.h
  • FSMC_BTR4_ACCMOD : stm32f10x.h
  • FSMC_BTR4_ACCMOD_0 : stm32f10x.h
  • FSMC_BTR4_ACCMOD_1 : stm32f10x.h
  • FSMC_BTR4_ADDHLD : stm32f10x.h
  • FSMC_BTR4_ADDHLD_0 : stm32f10x.h
  • FSMC_BTR4_ADDHLD_1 : stm32f10x.h
  • FSMC_BTR4_ADDHLD_2 : stm32f10x.h
  • FSMC_BTR4_ADDHLD_3 : stm32f10x.h
  • FSMC_BTR4_ADDSET : stm32f10x.h
  • FSMC_BTR4_ADDSET_0 : stm32f10x.h
  • FSMC_BTR4_ADDSET_1 : stm32f10x.h
  • FSMC_BTR4_ADDSET_2 : stm32f10x.h
  • FSMC_BTR4_ADDSET_3 : stm32f10x.h
  • FSMC_BTR4_BUSTURN : stm32f10x.h
  • FSMC_BTR4_BUSTURN_0 : stm32f10x.h
  • FSMC_BTR4_BUSTURN_1 : stm32f10x.h
  • FSMC_BTR4_BUSTURN_2 : stm32f10x.h
  • FSMC_BTR4_BUSTURN_3 : stm32f10x.h
  • FSMC_BTR4_CLKDIV : stm32f10x.h
  • FSMC_BTR4_CLKDIV_0 : stm32f10x.h
  • FSMC_BTR4_CLKDIV_1 : stm32f10x.h
  • FSMC_BTR4_CLKDIV_2 : stm32f10x.h
  • FSMC_BTR4_CLKDIV_3 : stm32f10x.h
  • FSMC_BTR4_DATAST : stm32f10x.h
  • FSMC_BTR4_DATAST_0 : stm32f10x.h
  • FSMC_BTR4_DATAST_1 : stm32f10x.h
  • FSMC_BTR4_DATAST_2 : stm32f10x.h
  • FSMC_BTR4_DATAST_3 : stm32f10x.h
  • FSMC_BTR4_DATLAT : stm32f10x.h
  • FSMC_BTR4_DATLAT_0 : stm32f10x.h
  • FSMC_BTR4_DATLAT_1 : stm32f10x.h
  • FSMC_BTR4_DATLAT_2 : stm32f10x.h
  • FSMC_BTR4_DATLAT_3 : stm32f10x.h
  • FSMC_BurstAccessMode_Disable : stm32f10x_fsmc.h
  • FSMC_BurstAccessMode_Enable : stm32f10x_fsmc.h
  • FSMC_BWTR1_ACCMOD : stm32f10x.h
  • FSMC_BWTR1_ACCMOD_0 : stm32f10x.h
  • FSMC_BWTR1_ACCMOD_1 : stm32f10x.h
  • FSMC_BWTR1_ADDHLD : stm32f10x.h
  • FSMC_BWTR1_ADDHLD_0 : stm32f10x.h
  • FSMC_BWTR1_ADDHLD_1 : stm32f10x.h
  • FSMC_BWTR1_ADDHLD_2 : stm32f10x.h
  • FSMC_BWTR1_ADDHLD_3 : stm32f10x.h
  • FSMC_BWTR1_ADDSET : stm32f10x.h
  • FSMC_BWTR1_ADDSET_0 : stm32f10x.h
  • FSMC_BWTR1_ADDSET_1 : stm32f10x.h
  • FSMC_BWTR1_ADDSET_2 : stm32f10x.h
  • FSMC_BWTR1_ADDSET_3 : stm32f10x.h
  • FSMC_BWTR1_CLKDIV : stm32f10x.h
  • FSMC_BWTR1_CLKDIV_0 : stm32f10x.h
  • FSMC_BWTR1_CLKDIV_1 : stm32f10x.h
  • FSMC_BWTR1_CLKDIV_2 : stm32f10x.h
  • FSMC_BWTR1_CLKDIV_3 : stm32f10x.h
  • FSMC_BWTR1_DATAST : stm32f10x.h
  • FSMC_BWTR1_DATAST_0 : stm32f10x.h
  • FSMC_BWTR1_DATAST_1 : stm32f10x.h
  • FSMC_BWTR1_DATAST_2 : stm32f10x.h
  • FSMC_BWTR1_DATAST_3 : stm32f10x.h
  • FSMC_BWTR1_DATLAT : stm32f10x.h
  • FSMC_BWTR1_DATLAT_0 : stm32f10x.h
  • FSMC_BWTR1_DATLAT_1 : stm32f10x.h
  • FSMC_BWTR1_DATLAT_2 : stm32f10x.h
  • FSMC_BWTR1_DATLAT_3 : stm32f10x.h
  • FSMC_BWTR2_ACCMOD : stm32f10x.h
  • FSMC_BWTR2_ACCMOD_0 : stm32f10x.h
  • FSMC_BWTR2_ACCMOD_1 : stm32f10x.h
  • FSMC_BWTR2_ADDHLD : stm32f10x.h
  • FSMC_BWTR2_ADDHLD_0 : stm32f10x.h
  • FSMC_BWTR2_ADDHLD_1 : stm32f10x.h
  • FSMC_BWTR2_ADDHLD_2 : stm32f10x.h
  • FSMC_BWTR2_ADDHLD_3 : stm32f10x.h
  • FSMC_BWTR2_ADDSET : stm32f10x.h
  • FSMC_BWTR2_ADDSET_0 : stm32f10x.h
  • FSMC_BWTR2_ADDSET_1 : stm32f10x.h
  • FSMC_BWTR2_ADDSET_2 : stm32f10x.h
  • FSMC_BWTR2_ADDSET_3 : stm32f10x.h
  • FSMC_BWTR2_CLKDIV : stm32f10x.h
  • FSMC_BWTR2_CLKDIV_0 : stm32f10x.h
  • FSMC_BWTR2_CLKDIV_1 : stm32f10x.h
  • FSMC_BWTR2_CLKDIV_2 : stm32f10x.h
  • FSMC_BWTR2_CLKDIV_3 : stm32f10x.h
  • FSMC_BWTR2_DATAST : stm32f10x.h
  • FSMC_BWTR2_DATAST_0 : stm32f10x.h
  • FSMC_BWTR2_DATAST_1 : stm32f10x.h
  • FSMC_BWTR2_DATAST_2 : stm32f10x.h
  • FSMC_BWTR2_DATAST_3 : stm32f10x.h
  • FSMC_BWTR2_DATLAT : stm32f10x.h
  • FSMC_BWTR2_DATLAT_0 : stm32f10x.h
  • FSMC_BWTR2_DATLAT_1 : stm32f10x.h
  • FSMC_BWTR2_DATLAT_2 : stm32f10x.h
  • FSMC_BWTR2_DATLAT_3 : stm32f10x.h
  • FSMC_BWTR3_ACCMOD : stm32f10x.h
  • FSMC_BWTR3_ACCMOD_0 : stm32f10x.h
  • FSMC_BWTR3_ACCMOD_1 : stm32f10x.h
  • FSMC_BWTR3_ADDHLD : stm32f10x.h
  • FSMC_BWTR3_ADDHLD_0 : stm32f10x.h
  • FSMC_BWTR3_ADDHLD_1 : stm32f10x.h
  • FSMC_BWTR3_ADDHLD_2 : stm32f10x.h
  • FSMC_BWTR3_ADDHLD_3 : stm32f10x.h
  • FSMC_BWTR3_ADDSET : stm32f10x.h
  • FSMC_BWTR3_ADDSET_0 : stm32f10x.h
  • FSMC_BWTR3_ADDSET_1 : stm32f10x.h
  • FSMC_BWTR3_ADDSET_2 : stm32f10x.h
  • FSMC_BWTR3_ADDSET_3 : stm32f10x.h
  • FSMC_BWTR3_CLKDIV : stm32f10x.h
  • FSMC_BWTR3_CLKDIV_0 : stm32f10x.h
  • FSMC_BWTR3_CLKDIV_1 : stm32f10x.h
  • FSMC_BWTR3_CLKDIV_2 : stm32f10x.h
  • FSMC_BWTR3_CLKDIV_3 : stm32f10x.h
  • FSMC_BWTR3_DATAST : stm32f10x.h
  • FSMC_BWTR3_DATAST_0 : stm32f10x.h
  • FSMC_BWTR3_DATAST_1 : stm32f10x.h
  • FSMC_BWTR3_DATAST_2 : stm32f10x.h
  • FSMC_BWTR3_DATAST_3 : stm32f10x.h
  • FSMC_BWTR3_DATLAT : stm32f10x.h
  • FSMC_BWTR3_DATLAT_0 : stm32f10x.h
  • FSMC_BWTR3_DATLAT_1 : stm32f10x.h
  • FSMC_BWTR3_DATLAT_2 : stm32f10x.h
  • FSMC_BWTR3_DATLAT_3 : stm32f10x.h
  • FSMC_BWTR4_ACCMOD : stm32f10x.h
  • FSMC_BWTR4_ACCMOD_0 : stm32f10x.h
  • FSMC_BWTR4_ACCMOD_1 : stm32f10x.h
  • FSMC_BWTR4_ADDHLD : stm32f10x.h
  • FSMC_BWTR4_ADDHLD_0 : stm32f10x.h
  • FSMC_BWTR4_ADDHLD_1 : stm32f10x.h
  • FSMC_BWTR4_ADDHLD_2 : stm32f10x.h
  • FSMC_BWTR4_ADDHLD_3 : stm32f10x.h
  • FSMC_BWTR4_ADDSET : stm32f10x.h
  • FSMC_BWTR4_ADDSET_0 : stm32f10x.h
  • FSMC_BWTR4_ADDSET_1 : stm32f10x.h
  • FSMC_BWTR4_ADDSET_2 : stm32f10x.h
  • FSMC_BWTR4_ADDSET_3 : stm32f10x.h
  • FSMC_BWTR4_CLKDIV : stm32f10x.h
  • FSMC_BWTR4_CLKDIV_0 : stm32f10x.h
  • FSMC_BWTR4_CLKDIV_1 : stm32f10x.h
  • FSMC_BWTR4_CLKDIV_2 : stm32f10x.h
  • FSMC_BWTR4_CLKDIV_3 : stm32f10x.h
  • FSMC_BWTR4_DATAST : stm32f10x.h
  • FSMC_BWTR4_DATAST_0 : stm32f10x.h
  • FSMC_BWTR4_DATAST_1 : stm32f10x.h
  • FSMC_BWTR4_DATAST_2 : stm32f10x.h
  • FSMC_BWTR4_DATAST_3 : stm32f10x.h
  • FSMC_BWTR4_DATLAT : stm32f10x.h
  • FSMC_BWTR4_DATLAT_0 : stm32f10x.h
  • FSMC_BWTR4_DATLAT_1 : stm32f10x.h
  • FSMC_BWTR4_DATLAT_2 : stm32f10x.h
  • FSMC_BWTR4_DATLAT_3 : stm32f10x.h
  • FSMC_ClearFlag() : stm32f10x_fsmc.c , stm32f10x_fsmc.h
  • FSMC_ClearITPendingBit() : stm32f10x_fsmc.h , stm32f10x_fsmc.c
  • FSMC_DataAddressMux_Disable : stm32f10x_fsmc.h
  • FSMC_DataAddressMux_Enable : stm32f10x_fsmc.h
  • FSMC_ECC_Disable : stm32f10x_fsmc.h
  • FSMC_ECC_Enable : stm32f10x_fsmc.h
  • FSMC_ECCPageSize_1024Bytes : stm32f10x_fsmc.h
  • FSMC_ECCPageSize_2048Bytes : stm32f10x_fsmc.h
  • FSMC_ECCPageSize_256Bytes : stm32f10x_fsmc.h
  • FSMC_ECCPageSize_4096Bytes : stm32f10x_fsmc.h
  • FSMC_ECCPageSize_512Bytes : stm32f10x_fsmc.h
  • FSMC_ECCPageSize_8192Bytes : stm32f10x_fsmc.h
  • FSMC_ECCR2_ECC2 : stm32f10x.h
  • FSMC_ECCR3_ECC3 : stm32f10x.h
  • FSMC_ExtendedMode_Disable : stm32f10x_fsmc.h
  • FSMC_ExtendedMode_Enable : stm32f10x_fsmc.h
  • FSMC_FLAG_FallingEdge : stm32f10x_fsmc.h
  • FSMC_FLAG_FEMPT : stm32f10x_fsmc.h
  • FSMC_FLAG_Level : stm32f10x_fsmc.h
  • FSMC_FLAG_RisingEdge : stm32f10x_fsmc.h
  • FSMC_GetECC() : stm32f10x_fsmc.h , stm32f10x_fsmc.c
  • FSMC_GetFlagStatus() : stm32f10x_fsmc.c , stm32f10x_fsmc.h
  • FSMC_GetITStatus() : stm32f10x_fsmc.h , stm32f10x_fsmc.c
  • FSMC_IT_FallingEdge : stm32f10x_fsmc.h
  • FSMC_IT_Level : stm32f10x_fsmc.h
  • FSMC_IT_RisingEdge : stm32f10x_fsmc.h
  • FSMC_ITConfig() : stm32f10x_fsmc.h , stm32f10x_fsmc.c
  • FSMC_MemoryDataWidth_16b : stm32f10x_fsmc.h
  • FSMC_MemoryDataWidth_8b : stm32f10x_fsmc.h
  • FSMC_MemoryType_NOR : stm32f10x_fsmc.h
  • FSMC_MemoryType_PSRAM : stm32f10x_fsmc.h
  • FSMC_MemoryType_SRAM : stm32f10x_fsmc.h
  • FSMC_NANDCmd() : stm32f10x_fsmc.h , stm32f10x_fsmc.c
  • FSMC_NANDDeInit() : stm32f10x_fsmc.c , stm32f10x_fsmc.h
  • FSMC_NANDECCCmd() : stm32f10x_fsmc.h , stm32f10x_fsmc.c
  • FSMC_NANDInit() : stm32f10x_fsmc.h , stm32f10x_fsmc.c
  • FSMC_NANDStructInit() : stm32f10x_fsmc.h , stm32f10x_fsmc.c
  • FSMC_NORSRAMCmd() : stm32f10x_fsmc.c , stm32f10x_fsmc.h
  • FSMC_NORSRAMDeInit() : stm32f10x_fsmc.h , stm32f10x_fsmc.c
  • FSMC_NORSRAMInit() : stm32f10x_fsmc.c , stm32f10x_fsmc.h
  • FSMC_NORSRAMStructInit() : stm32f10x_fsmc.h , stm32f10x_fsmc.c
  • FSMC_PATT2_ATTHIZ2 : stm32f10x.h
  • FSMC_PATT2_ATTHIZ2_0 : stm32f10x.h
  • FSMC_PATT2_ATTHIZ2_1 : stm32f10x.h
  • FSMC_PATT2_ATTHIZ2_2 : stm32f10x.h
  • FSMC_PATT2_ATTHIZ2_3 : stm32f10x.h
  • FSMC_PATT2_ATTHIZ2_4 : stm32f10x.h
  • FSMC_PATT2_ATTHIZ2_5 : stm32f10x.h
  • FSMC_PATT2_ATTHIZ2_6 : stm32f10x.h
  • FSMC_PATT2_ATTHIZ2_7 : stm32f10x.h
  • FSMC_PATT2_ATTHOLD2 : stm32f10x.h
  • FSMC_PATT2_ATTHOLD2_0 : stm32f10x.h
  • FSMC_PATT2_ATTHOLD2_1 : stm32f10x.h
  • FSMC_PATT2_ATTHOLD2_2 : stm32f10x.h
  • FSMC_PATT2_ATTHOLD2_3 : stm32f10x.h
  • FSMC_PATT2_ATTHOLD2_4 : stm32f10x.h
  • FSMC_PATT2_ATTHOLD2_5 : stm32f10x.h
  • FSMC_PATT2_ATTHOLD2_6 : stm32f10x.h
  • FSMC_PATT2_ATTHOLD2_7 : stm32f10x.h
  • FSMC_PATT2_ATTSET2 : stm32f10x.h
  • FSMC_PATT2_ATTSET2_0 : stm32f10x.h
  • FSMC_PATT2_ATTSET2_1 : stm32f10x.h
  • FSMC_PATT2_ATTSET2_2 : stm32f10x.h
  • FSMC_PATT2_ATTSET2_3 : stm32f10x.h
  • FSMC_PATT2_ATTSET2_4 : stm32f10x.h
  • FSMC_PATT2_ATTSET2_5 : stm32f10x.h
  • FSMC_PATT2_ATTSET2_6 : stm32f10x.h
  • FSMC_PATT2_ATTSET2_7 : stm32f10x.h
  • FSMC_PATT2_ATTWAIT2 : stm32f10x.h
  • FSMC_PATT2_ATTWAIT2_0 : stm32f10x.h
  • FSMC_PATT2_ATTWAIT2_1 : stm32f10x.h
  • FSMC_PATT2_ATTWAIT2_2 : stm32f10x.h
  • FSMC_PATT2_ATTWAIT2_3 : stm32f10x.h
  • FSMC_PATT2_ATTWAIT2_4 : stm32f10x.h
  • FSMC_PATT2_ATTWAIT2_5 : stm32f10x.h
  • FSMC_PATT2_ATTWAIT2_6 : stm32f10x.h
  • FSMC_PATT2_ATTWAIT2_7 : stm32f10x.h
  • FSMC_PATT3_ATTHIZ3 : stm32f10x.h
  • FSMC_PATT3_ATTHIZ3_0 : stm32f10x.h
  • FSMC_PATT3_ATTHIZ3_1 : stm32f10x.h
  • FSMC_PATT3_ATTHIZ3_2 : stm32f10x.h
  • FSMC_PATT3_ATTHIZ3_3 : stm32f10x.h
  • FSMC_PATT3_ATTHIZ3_4 : stm32f10x.h
  • FSMC_PATT3_ATTHIZ3_5 : stm32f10x.h
  • FSMC_PATT3_ATTHIZ3_6 : stm32f10x.h
  • FSMC_PATT3_ATTHIZ3_7 : stm32f10x.h
  • FSMC_PATT3_ATTHOLD3 : stm32f10x.h
  • FSMC_PATT3_ATTHOLD3_0 : stm32f10x.h
  • FSMC_PATT3_ATTHOLD3_1 : stm32f10x.h
  • FSMC_PATT3_ATTHOLD3_2 : stm32f10x.h
  • FSMC_PATT3_ATTHOLD3_3 : stm32f10x.h
  • FSMC_PATT3_ATTHOLD3_4 : stm32f10x.h
  • FSMC_PATT3_ATTHOLD3_5 : stm32f10x.h
  • FSMC_PATT3_ATTHOLD3_6 : stm32f10x.h
  • FSMC_PATT3_ATTHOLD3_7 : stm32f10x.h
  • FSMC_PATT3_ATTSET3 : stm32f10x.h
  • FSMC_PATT3_ATTSET3_0 : stm32f10x.h
  • FSMC_PATT3_ATTSET3_1 : stm32f10x.h
  • FSMC_PATT3_ATTSET3_2 : stm32f10x.h
  • FSMC_PATT3_ATTSET3_3 : stm32f10x.h
  • FSMC_PATT3_ATTSET3_4 : stm32f10x.h
  • FSMC_PATT3_ATTSET3_5 : stm32f10x.h
  • FSMC_PATT3_ATTSET3_6 : stm32f10x.h
  • FSMC_PATT3_ATTSET3_7 : stm32f10x.h
  • FSMC_PATT3_ATTWAIT3 : stm32f10x.h
  • FSMC_PATT3_ATTWAIT3_0 : stm32f10x.h
  • FSMC_PATT3_ATTWAIT3_1 : stm32f10x.h
  • FSMC_PATT3_ATTWAIT3_2 : stm32f10x.h
  • FSMC_PATT3_ATTWAIT3_3 : stm32f10x.h
  • FSMC_PATT3_ATTWAIT3_4 : stm32f10x.h
  • FSMC_PATT3_ATTWAIT3_5 : stm32f10x.h
  • FSMC_PATT3_ATTWAIT3_6 : stm32f10x.h
  • FSMC_PATT3_ATTWAIT3_7 : stm32f10x.h
  • FSMC_PATT4_ATTHIZ4 : stm32f10x.h
  • FSMC_PATT4_ATTHIZ4_0 : stm32f10x.h
  • FSMC_PATT4_ATTHIZ4_1 : stm32f10x.h
  • FSMC_PATT4_ATTHIZ4_2 : stm32f10x.h
  • FSMC_PATT4_ATTHIZ4_3 : stm32f10x.h
  • FSMC_PATT4_ATTHIZ4_4 : stm32f10x.h
  • FSMC_PATT4_ATTHIZ4_5 : stm32f10x.h
  • FSMC_PATT4_ATTHIZ4_6 : stm32f10x.h
  • FSMC_PATT4_ATTHIZ4_7 : stm32f10x.h
  • FSMC_PATT4_ATTHOLD4 : stm32f10x.h
  • FSMC_PATT4_ATTHOLD4_0 : stm32f10x.h
  • FSMC_PATT4_ATTHOLD4_1 : stm32f10x.h
  • FSMC_PATT4_ATTHOLD4_2 : stm32f10x.h
  • FSMC_PATT4_ATTHOLD4_3 : stm32f10x.h
  • FSMC_PATT4_ATTHOLD4_4 : stm32f10x.h
  • FSMC_PATT4_ATTHOLD4_5 : stm32f10x.h
  • FSMC_PATT4_ATTHOLD4_6 : stm32f10x.h
  • FSMC_PATT4_ATTHOLD4_7 : stm32f10x.h
  • FSMC_PATT4_ATTSET4 : stm32f10x.h
  • FSMC_PATT4_ATTSET4_0 : stm32f10x.h
  • FSMC_PATT4_ATTSET4_1 : stm32f10x.h
  • FSMC_PATT4_ATTSET4_2 : stm32f10x.h
  • FSMC_PATT4_ATTSET4_3 : stm32f10x.h
  • FSMC_PATT4_ATTSET4_4 : stm32f10x.h
  • FSMC_PATT4_ATTSET4_5 : stm32f10x.h
  • FSMC_PATT4_ATTSET4_6 : stm32f10x.h
  • FSMC_PATT4_ATTSET4_7 : stm32f10x.h
  • FSMC_PATT4_ATTWAIT4 : stm32f10x.h
  • FSMC_PATT4_ATTWAIT4_0 : stm32f10x.h
  • FSMC_PATT4_ATTWAIT4_1 : stm32f10x.h
  • FSMC_PATT4_ATTWAIT4_2 : stm32f10x.h
  • FSMC_PATT4_ATTWAIT4_3 : stm32f10x.h
  • FSMC_PATT4_ATTWAIT4_4 : stm32f10x.h
  • FSMC_PATT4_ATTWAIT4_5 : stm32f10x.h
  • FSMC_PATT4_ATTWAIT4_6 : stm32f10x.h
  • FSMC_PATT4_ATTWAIT4_7 : stm32f10x.h
  • FSMC_PCCARDCmd() : stm32f10x_fsmc.c , stm32f10x_fsmc.h
  • FSMC_PCCARDDeInit() : stm32f10x_fsmc.h , stm32f10x_fsmc.c
  • FSMC_PCCARDInit() : stm32f10x_fsmc.h , stm32f10x_fsmc.c
  • FSMC_PCCARDStructInit() : stm32f10x_fsmc.h , stm32f10x_fsmc.c
  • FSMC_PCR2_ECCEN : stm32f10x.h
  • FSMC_PCR2_ECCPS : stm32f10x.h
  • FSMC_PCR2_ECCPS_0 : stm32f10x.h
  • FSMC_PCR2_ECCPS_1 : stm32f10x.h
  • FSMC_PCR2_ECCPS_2 : stm32f10x.h
  • FSMC_PCR2_PBKEN : stm32f10x.h
  • FSMC_PCR2_PTYP : stm32f10x.h
  • FSMC_PCR2_PWAITEN : stm32f10x.h
  • FSMC_PCR2_PWID : stm32f10x.h
  • FSMC_PCR2_PWID_0 : stm32f10x.h
  • FSMC_PCR2_PWID_1 : stm32f10x.h
  • FSMC_PCR2_TAR : stm32f10x.h
  • FSMC_PCR2_TAR_0 : stm32f10x.h
  • FSMC_PCR2_TAR_1 : stm32f10x.h
  • FSMC_PCR2_TAR_2 : stm32f10x.h
  • FSMC_PCR2_TAR_3 : stm32f10x.h
  • FSMC_PCR2_TCLR : stm32f10x.h
  • FSMC_PCR2_TCLR_0 : stm32f10x.h
  • FSMC_PCR2_TCLR_1 : stm32f10x.h
  • FSMC_PCR2_TCLR_2 : stm32f10x.h
  • FSMC_PCR2_TCLR_3 : stm32f10x.h
  • FSMC_PCR3_ECCEN : stm32f10x.h
  • FSMC_PCR3_ECCPS : stm32f10x.h
  • FSMC_PCR3_ECCPS_0 : stm32f10x.h
  • FSMC_PCR3_ECCPS_1 : stm32f10x.h
  • FSMC_PCR3_ECCPS_2 : stm32f10x.h
  • FSMC_PCR3_PBKEN : stm32f10x.h
  • FSMC_PCR3_PTYP : stm32f10x.h
  • FSMC_PCR3_PWAITEN : stm32f10x.h
  • FSMC_PCR3_PWID : stm32f10x.h
  • FSMC_PCR3_PWID_0 : stm32f10x.h
  • FSMC_PCR3_PWID_1 : stm32f10x.h
  • FSMC_PCR3_TAR : stm32f10x.h
  • FSMC_PCR3_TAR_0 : stm32f10x.h
  • FSMC_PCR3_TAR_1 : stm32f10x.h
  • FSMC_PCR3_TAR_2 : stm32f10x.h
  • FSMC_PCR3_TAR_3 : stm32f10x.h
  • FSMC_PCR3_TCLR : stm32f10x.h
  • FSMC_PCR3_TCLR_0 : stm32f10x.h
  • FSMC_PCR3_TCLR_1 : stm32f10x.h
  • FSMC_PCR3_TCLR_2 : stm32f10x.h
  • FSMC_PCR3_TCLR_3 : stm32f10x.h
  • FSMC_PCR4_ECCEN : stm32f10x.h
  • FSMC_PCR4_ECCPS : stm32f10x.h
  • FSMC_PCR4_ECCPS_0 : stm32f10x.h
  • FSMC_PCR4_ECCPS_1 : stm32f10x.h
  • FSMC_PCR4_ECCPS_2 : stm32f10x.h
  • FSMC_PCR4_PBKEN : stm32f10x.h
  • FSMC_PCR4_PTYP : stm32f10x.h
  • FSMC_PCR4_PWAITEN : stm32f10x.h
  • FSMC_PCR4_PWID : stm32f10x.h
  • FSMC_PCR4_PWID_0 : stm32f10x.h
  • FSMC_PCR4_PWID_1 : stm32f10x.h
  • FSMC_PCR4_TAR : stm32f10x.h
  • FSMC_PCR4_TAR_0 : stm32f10x.h
  • FSMC_PCR4_TAR_1 : stm32f10x.h
  • FSMC_PCR4_TAR_2 : stm32f10x.h
  • FSMC_PCR4_TAR_3 : stm32f10x.h
  • FSMC_PCR4_TCLR : stm32f10x.h
  • FSMC_PCR4_TCLR_0 : stm32f10x.h
  • FSMC_PCR4_TCLR_1 : stm32f10x.h
  • FSMC_PCR4_TCLR_2 : stm32f10x.h
  • FSMC_PCR4_TCLR_3 : stm32f10x.h
  • FSMC_PIO4_IOHIZ4 : stm32f10x.h
  • FSMC_PIO4_IOHIZ4_0 : stm32f10x.h
  • FSMC_PIO4_IOHIZ4_1 : stm32f10x.h
  • FSMC_PIO4_IOHIZ4_2 : stm32f10x.h
  • FSMC_PIO4_IOHIZ4_3 : stm32f10x.h
  • FSMC_PIO4_IOHIZ4_4 : stm32f10x.h
  • FSMC_PIO4_IOHIZ4_5 : stm32f10x.h
  • FSMC_PIO4_IOHIZ4_6 : stm32f10x.h
  • FSMC_PIO4_IOHIZ4_7 : stm32f10x.h
  • FSMC_PIO4_IOHOLD4 : stm32f10x.h
  • FSMC_PIO4_IOHOLD4_0 : stm32f10x.h
  • FSMC_PIO4_IOHOLD4_1 : stm32f10x.h
  • FSMC_PIO4_IOHOLD4_2 : stm32f10x.h
  • FSMC_PIO4_IOHOLD4_3 : stm32f10x.h
  • FSMC_PIO4_IOHOLD4_4 : stm32f10x.h
  • FSMC_PIO4_IOHOLD4_5 : stm32f10x.h
  • FSMC_PIO4_IOHOLD4_6 : stm32f10x.h
  • FSMC_PIO4_IOHOLD4_7 : stm32f10x.h
  • FSMC_PIO4_IOSET4 : stm32f10x.h
  • FSMC_PIO4_IOSET4_0 : stm32f10x.h
  • FSMC_PIO4_IOSET4_1 : stm32f10x.h
  • FSMC_PIO4_IOSET4_2 : stm32f10x.h
  • FSMC_PIO4_IOSET4_3 : stm32f10x.h
  • FSMC_PIO4_IOSET4_4 : stm32f10x.h
  • FSMC_PIO4_IOSET4_5 : stm32f10x.h
  • FSMC_PIO4_IOSET4_6 : stm32f10x.h
  • FSMC_PIO4_IOSET4_7 : stm32f10x.h
  • FSMC_PIO4_IOWAIT4 : stm32f10x.h
  • FSMC_PIO4_IOWAIT4_0 : stm32f10x.h
  • FSMC_PIO4_IOWAIT4_1 : stm32f10x.h
  • FSMC_PIO4_IOWAIT4_2 : stm32f10x.h
  • FSMC_PIO4_IOWAIT4_3 : stm32f10x.h
  • FSMC_PIO4_IOWAIT4_4 : stm32f10x.h
  • FSMC_PIO4_IOWAIT4_5 : stm32f10x.h
  • FSMC_PIO4_IOWAIT4_6 : stm32f10x.h
  • FSMC_PIO4_IOWAIT4_7 : stm32f10x.h
  • FSMC_PMEM2_MEMHIZ2 : stm32f10x.h
  • FSMC_PMEM2_MEMHIZ2_0 : stm32f10x.h
  • FSMC_PMEM2_MEMHIZ2_1 : stm32f10x.h
  • FSMC_PMEM2_MEMHIZ2_2 : stm32f10x.h
  • FSMC_PMEM2_MEMHIZ2_3 : stm32f10x.h
  • FSMC_PMEM2_MEMHIZ2_4 : stm32f10x.h
  • FSMC_PMEM2_MEMHIZ2_5 : stm32f10x.h
  • FSMC_PMEM2_MEMHIZ2_6 : stm32f10x.h
  • FSMC_PMEM2_MEMHIZ2_7 : stm32f10x.h
  • FSMC_PMEM2_MEMHOLD2 : stm32f10x.h
  • FSMC_PMEM2_MEMHOLD2_0 : stm32f10x.h
  • FSMC_PMEM2_MEMHOLD2_1 : stm32f10x.h
  • FSMC_PMEM2_MEMHOLD2_2 : stm32f10x.h
  • FSMC_PMEM2_MEMHOLD2_3 : stm32f10x.h
  • FSMC_PMEM2_MEMHOLD2_4 : stm32f10x.h
  • FSMC_PMEM2_MEMHOLD2_5 : stm32f10x.h
  • FSMC_PMEM2_MEMHOLD2_6 : stm32f10x.h
  • FSMC_PMEM2_MEMHOLD2_7 : stm32f10x.h
  • FSMC_PMEM2_MEMSET2 : stm32f10x.h
  • FSMC_PMEM2_MEMSET2_0 : stm32f10x.h
  • FSMC_PMEM2_MEMSET2_1 : stm32f10x.h
  • FSMC_PMEM2_MEMSET2_2 : stm32f10x.h
  • FSMC_PMEM2_MEMSET2_3 : stm32f10x.h
  • FSMC_PMEM2_MEMSET2_4 : stm32f10x.h
  • FSMC_PMEM2_MEMSET2_5 : stm32f10x.h
  • FSMC_PMEM2_MEMSET2_6 : stm32f10x.h
  • FSMC_PMEM2_MEMSET2_7 : stm32f10x.h
  • FSMC_PMEM2_MEMWAIT2 : stm32f10x.h
  • FSMC_PMEM2_MEMWAIT2_0 : stm32f10x.h
  • FSMC_PMEM2_MEMWAIT2_1 : stm32f10x.h
  • FSMC_PMEM2_MEMWAIT2_2 : stm32f10x.h
  • FSMC_PMEM2_MEMWAIT2_3 : stm32f10x.h
  • FSMC_PMEM2_MEMWAIT2_4 : stm32f10x.h
  • FSMC_PMEM2_MEMWAIT2_5 : stm32f10x.h
  • FSMC_PMEM2_MEMWAIT2_6 : stm32f10x.h
  • FSMC_PMEM2_MEMWAIT2_7 : stm32f10x.h
  • FSMC_PMEM3_MEMHIZ3 : stm32f10x.h
  • FSMC_PMEM3_MEMHIZ3_0 : stm32f10x.h
  • FSMC_PMEM3_MEMHIZ3_1 : stm32f10x.h
  • FSMC_PMEM3_MEMHIZ3_2 : stm32f10x.h
  • FSMC_PMEM3_MEMHIZ3_3 : stm32f10x.h
  • FSMC_PMEM3_MEMHIZ3_4 : stm32f10x.h
  • FSMC_PMEM3_MEMHIZ3_5 : stm32f10x.h
  • FSMC_PMEM3_MEMHIZ3_6 : stm32f10x.h
  • FSMC_PMEM3_MEMHIZ3_7 : stm32f10x.h
  • FSMC_PMEM3_MEMHOLD3 : stm32f10x.h
  • FSMC_PMEM3_MEMHOLD3_0 : stm32f10x.h
  • FSMC_PMEM3_MEMHOLD3_1 : stm32f10x.h
  • FSMC_PMEM3_MEMHOLD3_2 : stm32f10x.h
  • FSMC_PMEM3_MEMHOLD3_3 : stm32f10x.h
  • FSMC_PMEM3_MEMHOLD3_4 : stm32f10x.h
  • FSMC_PMEM3_MEMHOLD3_5 : stm32f10x.h
  • FSMC_PMEM3_MEMHOLD3_6 : stm32f10x.h
  • FSMC_PMEM3_MEMHOLD3_7 : stm32f10x.h
  • FSMC_PMEM3_MEMSET3 : stm32f10x.h
  • FSMC_PMEM3_MEMSET3_0 : stm32f10x.h
  • FSMC_PMEM3_MEMSET3_1 : stm32f10x.h
  • FSMC_PMEM3_MEMSET3_2 : stm32f10x.h
  • FSMC_PMEM3_MEMSET3_3 : stm32f10x.h
  • FSMC_PMEM3_MEMSET3_4 : stm32f10x.h
  • FSMC_PMEM3_MEMSET3_5 : stm32f10x.h
  • FSMC_PMEM3_MEMSET3_6 : stm32f10x.h
  • FSMC_PMEM3_MEMSET3_7 : stm32f10x.h
  • FSMC_PMEM3_MEMWAIT3 : stm32f10x.h
  • FSMC_PMEM3_MEMWAIT3_0 : stm32f10x.h
  • FSMC_PMEM3_MEMWAIT3_1 : stm32f10x.h
  • FSMC_PMEM3_MEMWAIT3_2 : stm32f10x.h
  • FSMC_PMEM3_MEMWAIT3_3 : stm32f10x.h
  • FSMC_PMEM3_MEMWAIT3_4 : stm32f10x.h
  • FSMC_PMEM3_MEMWAIT3_5 : stm32f10x.h
  • FSMC_PMEM3_MEMWAIT3_6 : stm32f10x.h
  • FSMC_PMEM3_MEMWAIT3_7 : stm32f10x.h
  • FSMC_PMEM4_MEMHIZ4 : stm32f10x.h
  • FSMC_PMEM4_MEMHIZ4_0 : stm32f10x.h
  • FSMC_PMEM4_MEMHIZ4_1 : stm32f10x.h
  • FSMC_PMEM4_MEMHIZ4_2 : stm32f10x.h
  • FSMC_PMEM4_MEMHIZ4_3 : stm32f10x.h
  • FSMC_PMEM4_MEMHIZ4_4 : stm32f10x.h
  • FSMC_PMEM4_MEMHIZ4_5 : stm32f10x.h
  • FSMC_PMEM4_MEMHIZ4_6 : stm32f10x.h
  • FSMC_PMEM4_MEMHIZ4_7 : stm32f10x.h
  • FSMC_PMEM4_MEMHOLD4 : stm32f10x.h
  • FSMC_PMEM4_MEMHOLD4_0 : stm32f10x.h
  • FSMC_PMEM4_MEMHOLD4_1 : stm32f10x.h
  • FSMC_PMEM4_MEMHOLD4_2 : stm32f10x.h
  • FSMC_PMEM4_MEMHOLD4_3 : stm32f10x.h
  • FSMC_PMEM4_MEMHOLD4_4 : stm32f10x.h
  • FSMC_PMEM4_MEMHOLD4_5 : stm32f10x.h
  • FSMC_PMEM4_MEMHOLD4_6 : stm32f10x.h
  • FSMC_PMEM4_MEMHOLD4_7 : stm32f10x.h
  • FSMC_PMEM4_MEMSET4 : stm32f10x.h
  • FSMC_PMEM4_MEMSET4_0 : stm32f10x.h
  • FSMC_PMEM4_MEMSET4_1 : stm32f10x.h
  • FSMC_PMEM4_MEMSET4_2 : stm32f10x.h
  • FSMC_PMEM4_MEMSET4_3 : stm32f10x.h
  • FSMC_PMEM4_MEMSET4_4 : stm32f10x.h
  • FSMC_PMEM4_MEMSET4_5 : stm32f10x.h
  • FSMC_PMEM4_MEMSET4_6 : stm32f10x.h
  • FSMC_PMEM4_MEMSET4_7 : stm32f10x.h
  • FSMC_PMEM4_MEMWAIT4 : stm32f10x.h
  • FSMC_PMEM4_MEMWAIT4_0 : stm32f10x.h
  • FSMC_PMEM4_MEMWAIT4_1 : stm32f10x.h
  • FSMC_PMEM4_MEMWAIT4_2 : stm32f10x.h
  • FSMC_PMEM4_MEMWAIT4_3 : stm32f10x.h
  • FSMC_PMEM4_MEMWAIT4_4 : stm32f10x.h
  • FSMC_PMEM4_MEMWAIT4_5 : stm32f10x.h
  • FSMC_PMEM4_MEMWAIT4_6 : stm32f10x.h
  • FSMC_PMEM4_MEMWAIT4_7 : stm32f10x.h
  • FSMC_R_BASE : stm32f10x.h
  • FSMC_SR2_FEMPT : stm32f10x.h
  • FSMC_SR2_IFEN : stm32f10x.h
  • FSMC_SR2_IFS : stm32f10x.h
  • FSMC_SR2_ILEN : stm32f10x.h
  • FSMC_SR2_ILS : stm32f10x.h
  • FSMC_SR2_IREN : stm32f10x.h
  • FSMC_SR2_IRS : stm32f10x.h
  • FSMC_SR3_FEMPT : stm32f10x.h
  • FSMC_SR3_IFEN : stm32f10x.h
  • FSMC_SR3_IFS : stm32f10x.h
  • FSMC_SR3_ILEN : stm32f10x.h
  • FSMC_SR3_ILS : stm32f10x.h
  • FSMC_SR3_IREN : stm32f10x.h
  • FSMC_SR3_IRS : stm32f10x.h
  • FSMC_SR4_FEMPT : stm32f10x.h
  • FSMC_SR4_IFEN : stm32f10x.h
  • FSMC_SR4_IFS : stm32f10x.h
  • FSMC_SR4_ILEN : stm32f10x.h
  • FSMC_SR4_ILS : stm32f10x.h
  • FSMC_SR4_IREN : stm32f10x.h
  • FSMC_SR4_IRS : stm32f10x.h
  • FSMC_Waitfeature_Disable : stm32f10x_fsmc.h
  • FSMC_Waitfeature_Enable : stm32f10x_fsmc.h
  • FSMC_WaitSignal_Disable : stm32f10x_fsmc.h
  • FSMC_WaitSignal_Enable : stm32f10x_fsmc.h
  • FSMC_WaitSignalActive_BeforeWaitState : stm32f10x_fsmc.h
  • FSMC_WaitSignalActive_DuringWaitState : stm32f10x_fsmc.h
  • FSMC_WaitSignalPolarity_High : stm32f10x_fsmc.h
  • FSMC_WaitSignalPolarity_Low : stm32f10x_fsmc.h
  • FSMC_WrapMode_Disable : stm32f10x_fsmc.h
  • FSMC_WrapMode_Enable : stm32f10x_fsmc.h
  • FSMC_WriteBurst_Disable : stm32f10x_fsmc.h
  • FSMC_WriteBurst_Enable : stm32f10x_fsmc.h
  • FSMC_WriteOperation_Disable : stm32f10x_fsmc.h
  • FSMC_WriteOperation_Enable : stm32f10x_fsmc.h
  • FunctionalState : stm32f10x.h


STM32F10x Standard Peripherals Firmware Library: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
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  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • j
  • k
  • l
  • m
  • n
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  • t
  • u
  • v
  • w
  • y
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- g -

  • GetVar_OperationComplete() : STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/main.c , RTC/LSI_Calib/main.h
  • GPIO_AFIODeInit() : stm32f10x_gpio.c , stm32f10x_gpio.h
  • GPIO_BRR_BR0 : stm32f10x.h
  • GPIO_BRR_BR1 : stm32f10x.h
  • GPIO_BRR_BR10 : stm32f10x.h
  • GPIO_BRR_BR11 : stm32f10x.h
  • GPIO_BRR_BR12 : stm32f10x.h
  • GPIO_BRR_BR13 : stm32f10x.h
  • GPIO_BRR_BR14 : stm32f10x.h
  • GPIO_BRR_BR15 : stm32f10x.h
  • GPIO_BRR_BR2 : stm32f10x.h
  • GPIO_BRR_BR3 : stm32f10x.h
  • GPIO_BRR_BR4 : stm32f10x.h
  • GPIO_BRR_BR5 : stm32f10x.h
  • GPIO_BRR_BR6 : stm32f10x.h
  • GPIO_BRR_BR7 : stm32f10x.h
  • GPIO_BRR_BR8 : stm32f10x.h
  • GPIO_BRR_BR9 : stm32f10x.h
  • GPIO_BSRR_BR0 : stm32f10x.h
  • GPIO_BSRR_BR1 : stm32f10x.h
  • GPIO_BSRR_BR10 : stm32f10x.h
  • GPIO_BSRR_BR11 : stm32f10x.h
  • GPIO_BSRR_BR12 : stm32f10x.h
  • GPIO_BSRR_BR13 : stm32f10x.h
  • GPIO_BSRR_BR14 : stm32f10x.h
  • GPIO_BSRR_BR15 : stm32f10x.h
  • GPIO_BSRR_BR2 : stm32f10x.h
  • GPIO_BSRR_BR3 : stm32f10x.h
  • GPIO_BSRR_BR4 : stm32f10x.h
  • GPIO_BSRR_BR5 : stm32f10x.h
  • GPIO_BSRR_BR6 : stm32f10x.h
  • GPIO_BSRR_BR7 : stm32f10x.h
  • GPIO_BSRR_BR8 : stm32f10x.h
  • GPIO_BSRR_BR9 : stm32f10x.h
  • GPIO_BSRR_BS0 : stm32f10x.h
  • GPIO_BSRR_BS1 : stm32f10x.h
  • GPIO_BSRR_BS10 : stm32f10x.h
  • GPIO_BSRR_BS11 : stm32f10x.h
  • GPIO_BSRR_BS12 : stm32f10x.h
  • GPIO_BSRR_BS13 : stm32f10x.h
  • GPIO_BSRR_BS14 : stm32f10x.h
  • GPIO_BSRR_BS15 : stm32f10x.h
  • GPIO_BSRR_BS2 : stm32f10x.h
  • GPIO_BSRR_BS3 : stm32f10x.h
  • GPIO_BSRR_BS4 : stm32f10x.h
  • GPIO_BSRR_BS5 : stm32f10x.h
  • GPIO_BSRR_BS6 : stm32f10x.h
  • GPIO_BSRR_BS7 : stm32f10x.h
  • GPIO_BSRR_BS8 : stm32f10x.h
  • GPIO_BSRR_BS9 : stm32f10x.h
  • GPIO_CAN : STM32F10x_StdPeriph_Examples/CAN/Networking/main.c
  • GPIO_CAN1 : CAN/Networking/platform_config.h
  • GPIO_CAN2 : CAN/Networking/platform_config.h
  • GPIO_CLK : stm32100b_eval.c , stm32100e_eval.c , stm3210b_eval.c , stm3210c_eval.c , stm3210e_eval.c , stm32l152_eval.c
  • GPIO_Configuration() : STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/main.c , STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/main.c , STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/main.c , STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/main.c , STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/main.c , STM32F10x_StdPeriph_Examples/BKP/Tamper/main.c , STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/main.c , STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/main.c , STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/main.c , STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/main.c , STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/main.c , STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/main.c , STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/main.c , STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/main.c , STM32F10x_StdPeriph_Examples/I2S/Interrupt/main.c , STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/main.c , STM32F10x_StdPeriph_Examples/SPI/CRC/main.c , STM32F10x_StdPeriph_Examples/SPI/DMA/main.c , STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/main.c , STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/main.c , STM32F10x_StdPeriph_Examples/TIM/6Steps/main.c , STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/main.c , STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/main.c , STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/main.c , STM32F10x_StdPeriph_Examples/TIM/DMA/main.c , STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/main.c , STM32F10x_StdPeriph_Examples/TIM/InputCapture/main.c , STM32F10x_StdPeriph_Examples/TIM/OCActive/main.c , STM32F10x_StdPeriph_Examples/TIM/OCInactive/main.c , STM32F10x_StdPeriph_Examples/TIM/OCToggle/main.c , STM32F10x_StdPeriph_Examples/TIM/OnePulse/main.c , STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/main.c , STM32F10x_StdPeriph_Examples/TIM/PWM_Input/main.c , STM32F10x_StdPeriph_Examples/TIM/PWM_Output/main.c , STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/main.c , STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/main.c , STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/main.c , STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/main.c , STM32F10x_StdPeriph_Examples/TIM/TimeBase/main.c , STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/main.c , STM32F10x_StdPeriph_Examples/USART/DMA_Polling/main.c , STM32F10x_StdPeriph_Examples/USART/HalfDuplex/main.c , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/main.c , STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c , STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/main.c , STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/main.c , STM32F10x_StdPeriph_Examples/USART/MultiProcessor/main.c , STM32F10x_StdPeriph_Examples/USART/Polling/main.c , STM32F10x_StdPeriph_Examples/USART/Smartcard/main.c , STM32F10x_StdPeriph_Examples/USART/Synchronous/main.c , STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c
  • GPIO_CRH_CNF : stm32f10x.h
  • GPIO_CRH_CNF10 : stm32f10x.h
  • GPIO_CRH_CNF10_0 : stm32f10x.h
  • GPIO_CRH_CNF10_1 : stm32f10x.h
  • GPIO_CRH_CNF11 : stm32f10x.h
  • GPIO_CRH_CNF11_0 : stm32f10x.h
  • GPIO_CRH_CNF11_1 : stm32f10x.h
  • GPIO_CRH_CNF12 : stm32f10x.h
  • GPIO_CRH_CNF12_0 : stm32f10x.h
  • GPIO_CRH_CNF12_1 : stm32f10x.h
  • GPIO_CRH_CNF13 : stm32f10x.h
  • GPIO_CRH_CNF13_0 : stm32f10x.h
  • GPIO_CRH_CNF13_1 : stm32f10x.h
  • GPIO_CRH_CNF14 : stm32f10x.h
  • GPIO_CRH_CNF14_0 : stm32f10x.h
  • GPIO_CRH_CNF14_1 : stm32f10x.h
  • GPIO_CRH_CNF15 : stm32f10x.h
  • GPIO_CRH_CNF15_0 : stm32f10x.h
  • GPIO_CRH_CNF15_1 : stm32f10x.h
  • GPIO_CRH_CNF8 : stm32f10x.h
  • GPIO_CRH_CNF8_0 : stm32f10x.h
  • GPIO_CRH_CNF8_1 : stm32f10x.h
  • GPIO_CRH_CNF9 : stm32f10x.h
  • GPIO_CRH_CNF9_0 : stm32f10x.h
  • GPIO_CRH_CNF9_1 : stm32f10x.h
  • GPIO_CRH_MODE : stm32f10x.h
  • GPIO_CRH_MODE10 : stm32f10x.h
  • GPIO_CRH_MODE10_0 : stm32f10x.h
  • GPIO_CRH_MODE10_1 : stm32f10x.h
  • GPIO_CRH_MODE11 : stm32f10x.h
  • GPIO_CRH_MODE11_0 : stm32f10x.h
  • GPIO_CRH_MODE11_1 : stm32f10x.h
  • GPIO_CRH_MODE12 : stm32f10x.h
  • GPIO_CRH_MODE12_0 : stm32f10x.h
  • GPIO_CRH_MODE12_1 : stm32f10x.h
  • GPIO_CRH_MODE13 : stm32f10x.h
  • GPIO_CRH_MODE13_0 : stm32f10x.h
  • GPIO_CRH_MODE13_1 : stm32f10x.h
  • GPIO_CRH_MODE14 : stm32f10x.h
  • GPIO_CRH_MODE14_0 : stm32f10x.h
  • GPIO_CRH_MODE14_1 : stm32f10x.h
  • GPIO_CRH_MODE15 : stm32f10x.h
  • GPIO_CRH_MODE15_0 : stm32f10x.h
  • GPIO_CRH_MODE15_1 : stm32f10x.h
  • GPIO_CRH_MODE8 : stm32f10x.h
  • GPIO_CRH_MODE8_0 : stm32f10x.h
  • GPIO_CRH_MODE8_1 : stm32f10x.h
  • GPIO_CRH_MODE9 : stm32f10x.h
  • GPIO_CRH_MODE9_0 : stm32f10x.h
  • GPIO_CRH_MODE9_1 : stm32f10x.h
  • GPIO_CRL_CNF : stm32f10x.h
  • GPIO_CRL_CNF0 : stm32f10x.h
  • GPIO_CRL_CNF0_0 : stm32f10x.h
  • GPIO_CRL_CNF0_1 : stm32f10x.h
  • GPIO_CRL_CNF1 : stm32f10x.h
  • GPIO_CRL_CNF1_0 : stm32f10x.h
  • GPIO_CRL_CNF1_1 : stm32f10x.h
  • GPIO_CRL_CNF2 : stm32f10x.h
  • GPIO_CRL_CNF2_0 : stm32f10x.h
  • GPIO_CRL_CNF2_1 : stm32f10x.h
  • GPIO_CRL_CNF3 : stm32f10x.h
  • GPIO_CRL_CNF3_0 : stm32f10x.h
  • GPIO_CRL_CNF3_1 : stm32f10x.h
  • GPIO_CRL_CNF4 : stm32f10x.h
  • GPIO_CRL_CNF4_0 : stm32f10x.h
  • GPIO_CRL_CNF4_1 : stm32f10x.h
  • GPIO_CRL_CNF5 : stm32f10x.h
  • GPIO_CRL_CNF5_0 : stm32f10x.h
  • GPIO_CRL_CNF5_1 : stm32f10x.h
  • GPIO_CRL_CNF6 : stm32f10x.h
  • GPIO_CRL_CNF6_0 : stm32f10x.h
  • GPIO_CRL_CNF6_1 : stm32f10x.h
  • GPIO_CRL_CNF7 : stm32f10x.h
  • GPIO_CRL_CNF7_0 : stm32f10x.h
  • GPIO_CRL_CNF7_1 : stm32f10x.h
  • GPIO_CRL_MODE : stm32f10x.h
  • GPIO_CRL_MODE0 : stm32f10x.h
  • GPIO_CRL_MODE0_0 : stm32f10x.h
  • GPIO_CRL_MODE0_1 : stm32f10x.h
  • GPIO_CRL_MODE1 : stm32f10x.h
  • GPIO_CRL_MODE1_0 : stm32f10x.h
  • GPIO_CRL_MODE1_1 : stm32f10x.h
  • GPIO_CRL_MODE2 : stm32f10x.h
  • GPIO_CRL_MODE2_0 : stm32f10x.h
  • GPIO_CRL_MODE2_1 : stm32f10x.h
  • GPIO_CRL_MODE3 : stm32f10x.h
  • GPIO_CRL_MODE3_0 : stm32f10x.h
  • GPIO_CRL_MODE3_1 : stm32f10x.h
  • GPIO_CRL_MODE4 : stm32f10x.h
  • GPIO_CRL_MODE4_0 : stm32f10x.h
  • GPIO_CRL_MODE4_1 : stm32f10x.h
  • GPIO_CRL_MODE5 : stm32f10x.h
  • GPIO_CRL_MODE5_0 : stm32f10x.h
  • GPIO_CRL_MODE5_1 : stm32f10x.h
  • GPIO_CRL_MODE6 : stm32f10x.h
  • GPIO_CRL_MODE6_0 : stm32f10x.h
  • GPIO_CRL_MODE6_1 : stm32f10x.h
  • GPIO_CRL_MODE7 : stm32f10x.h
  • GPIO_CRL_MODE7_0 : stm32f10x.h
  • GPIO_CRL_MODE7_1 : stm32f10x.h
  • GPIO_CTSPin : USART/HyperTerminal_HwFlowControl/platform_config.h
  • GPIO_DeInit() : stm32f10x_gpio.h , stm32f10x_gpio.c
  • GPIO_ETH_MediaInterface_MII : stm32f10x_gpio.h
  • GPIO_ETH_MediaInterface_RMII : stm32f10x_gpio.h
  • GPIO_ETH_MediaInterfaceConfig() : stm32f10x_gpio.h , stm32f10x_gpio.c
  • GPIO_EventOutputCmd() : stm32f10x_gpio.h , stm32f10x_gpio.c
  • GPIO_EventOutputConfig() : stm32f10x_gpio.h , stm32f10x_gpio.c
  • GPIO_EXTILineConfig() : stm32f10x_gpio.h , stm32f10x_gpio.c
  • GPIO_FullRemap_TIM1 : stm32f10x_gpio.h
  • GPIO_FullRemap_TIM2 : stm32f10x_gpio.h
  • GPIO_FullRemap_TIM3 : stm32f10x_gpio.h
  • GPIO_FullRemap_USART3 : stm32f10x_gpio.h
  • GPIO_IDR_IDR0 : stm32f10x.h
  • GPIO_IDR_IDR1 : stm32f10x.h
  • GPIO_IDR_IDR10 : stm32f10x.h
  • GPIO_IDR_IDR11 : stm32f10x.h
  • GPIO_IDR_IDR12 : stm32f10x.h
  • GPIO_IDR_IDR13 : stm32f10x.h
  • GPIO_IDR_IDR14 : stm32f10x.h
  • GPIO_IDR_IDR15 : stm32f10x.h
  • GPIO_IDR_IDR2 : stm32f10x.h
  • GPIO_IDR_IDR3 : stm32f10x.h
  • GPIO_IDR_IDR4 : stm32f10x.h
  • GPIO_IDR_IDR5 : stm32f10x.h
  • GPIO_IDR_IDR6 : stm32f10x.h
  • GPIO_IDR_IDR7 : stm32f10x.h
  • GPIO_IDR_IDR8 : stm32f10x.h
  • GPIO_IDR_IDR9 : stm32f10x.h
  • GPIO_Init() : stm32f10x_gpio.h , stm32f10x_gpio.c
  • GPIO_InitStructure : STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/main.c , STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/main.c , STM32F10x_StdPeriph_Examples/GPIO/IOToggle/main.c , STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/main.c , STM32F10x_StdPeriph_Examples/SPI/DMA/main.c , STM32F10x_StdPeriph_Examples/TIM/DMABurst/main.c
  • GPIO_LCKR_LCK0 : stm32f10x.h
  • GPIO_LCKR_LCK1 : stm32f10x.h
  • GPIO_LCKR_LCK10 : stm32f10x.h
  • GPIO_LCKR_LCK11 : stm32f10x.h
  • GPIO_LCKR_LCK12 : stm32f10x.h
  • GPIO_LCKR_LCK13 : stm32f10x.h
  • GPIO_LCKR_LCK14 : stm32f10x.h
  • GPIO_LCKR_LCK15 : stm32f10x.h
  • GPIO_LCKR_LCK2 : stm32f10x.h
  • GPIO_LCKR_LCK3 : stm32f10x.h
  • GPIO_LCKR_LCK4 : stm32f10x.h
  • GPIO_LCKR_LCK5 : stm32f10x.h
  • GPIO_LCKR_LCK6 : stm32f10x.h
  • GPIO_LCKR_LCK7 : stm32f10x.h
  • GPIO_LCKR_LCK8 : stm32f10x.h
  • GPIO_LCKR_LCK9 : stm32f10x.h
  • GPIO_LCKR_LCKK : stm32f10x.h
  • GPIO_Mode_AF_OD : stm32f10x_gpio.h
  • GPIO_Mode_AF_PP : stm32f10x_gpio.h
  • GPIO_Mode_AIN : stm32f10x_gpio.h
  • GPIO_Mode_IN_FLOATING : stm32f10x_gpio.h
  • GPIO_Mode_IPD : stm32f10x_gpio.h
  • GPIO_Mode_IPU : stm32f10x_gpio.h
  • GPIO_Mode_Out_OD : stm32f10x_gpio.h
  • GPIO_Mode_Out_PP : stm32f10x_gpio.h
  • GPIO_ODR_ODR0 : stm32f10x.h
  • GPIO_ODR_ODR1 : stm32f10x.h
  • GPIO_ODR_ODR10 : stm32f10x.h
  • GPIO_ODR_ODR11 : stm32f10x.h
  • GPIO_ODR_ODR12 : stm32f10x.h
  • GPIO_ODR_ODR13 : stm32f10x.h
  • GPIO_ODR_ODR14 : stm32f10x.h
  • GPIO_ODR_ODR15 : stm32f10x.h
  • GPIO_ODR_ODR2 : stm32f10x.h
  • GPIO_ODR_ODR3 : stm32f10x.h
  • GPIO_ODR_ODR4 : stm32f10x.h
  • GPIO_ODR_ODR5 : stm32f10x.h
  • GPIO_ODR_ODR6 : stm32f10x.h
  • GPIO_ODR_ODR7 : stm32f10x.h
  • GPIO_ODR_ODR8 : stm32f10x.h
  • GPIO_ODR_ODR9 : stm32f10x.h
  • GPIO_PartialRemap1_TIM2 : stm32f10x_gpio.h
  • GPIO_PartialRemap2_TIM2 : stm32f10x_gpio.h
  • GPIO_PartialRemap_TIM1 : stm32f10x_gpio.h
  • GPIO_PartialRemap_TIM3 : stm32f10x_gpio.h
  • GPIO_PartialRemap_USART3 : stm32f10x_gpio.h
  • GPIO_PIN : stm32100b_eval.c , stm32100e_eval.c , stm3210b_eval.c , stm3210c_eval.c , stm3210e_eval.c , stm32l152_eval.c
  • GPIO_Pin_0 : stm32f10x_gpio.h
  • GPIO_Pin_1 : stm32f10x_gpio.h
  • GPIO_Pin_10 : stm32f10x_gpio.h
  • GPIO_Pin_11 : stm32f10x_gpio.h
  • GPIO_Pin_12 : stm32f10x_gpio.h
  • GPIO_Pin_13 : stm32f10x_gpio.h
  • GPIO_Pin_14 : stm32f10x_gpio.h
  • GPIO_Pin_15 : stm32f10x_gpio.h
  • GPIO_Pin_2 : stm32f10x_gpio.h
  • GPIO_Pin_3 : stm32f10x_gpio.h
  • GPIO_Pin_4 : stm32f10x_gpio.h
  • GPIO_Pin_5 : stm32f10x_gpio.h
  • GPIO_Pin_6 : stm32f10x_gpio.h
  • GPIO_Pin_7 : stm32f10x_gpio.h
  • GPIO_Pin_8 : stm32f10x_gpio.h
  • GPIO_Pin_9 : stm32f10x_gpio.h
  • GPIO_Pin_All : stm32f10x_gpio.h
  • GPIO_Pin_CAN1_RX : CAN/Networking/platform_config.h
  • GPIO_Pin_CAN1_TX : CAN/Networking/platform_config.h
  • GPIO_Pin_CAN2_RX : CAN/Networking/platform_config.h
  • GPIO_Pin_CAN2_TX : CAN/Networking/platform_config.h
  • GPIO_Pin_CAN_RX : STM32F10x_StdPeriph_Examples/CAN/Networking/main.c
  • GPIO_Pin_CAN_TX : STM32F10x_StdPeriph_Examples/CAN/Networking/main.c
  • GPIO_PinLockConfig() : stm32f10x_gpio.h , stm32f10x_gpio.c
  • GPIO_PinRemapConfig() : stm32f10x_gpio.h , stm32f10x_gpio.c
  • GPIO_PinSource0 : stm32f10x_gpio.h
  • GPIO_PinSource1 : stm32f10x_gpio.h
  • GPIO_PinSource10 : stm32f10x_gpio.h
  • GPIO_PinSource11 : stm32f10x_gpio.h
  • GPIO_PinSource12 : stm32f10x_gpio.h
  • GPIO_PinSource13 : stm32f10x_gpio.h
  • GPIO_PinSource14 : stm32f10x_gpio.h
  • GPIO_PinSource15 : stm32f10x_gpio.h
  • GPIO_PinSource2 : stm32f10x_gpio.h
  • GPIO_PinSource3 : stm32f10x_gpio.h
  • GPIO_PinSource4 : stm32f10x_gpio.h
  • GPIO_PinSource5 : stm32f10x_gpio.h
  • GPIO_PinSource6 : stm32f10x_gpio.h
  • GPIO_PinSource7 : stm32f10x_gpio.h
  • GPIO_PinSource8 : stm32f10x_gpio.h
  • GPIO_PinSource9 : stm32f10x_gpio.h
  • GPIO_PORT : stm3210b_eval.c , stm3210c_eval.c , stm3210e_eval.c , stm32l152_eval.c , stm32100e_eval.c , stm32100b_eval.c
  • GPIO_PortSourceGPIOA : stm32f10x_gpio.h
  • GPIO_PortSourceGPIOB : stm32f10x_gpio.h
  • GPIO_PortSourceGPIOC : stm32f10x_gpio.h
  • GPIO_PortSourceGPIOD : stm32f10x_gpio.h
  • GPIO_PortSourceGPIOE : stm32f10x_gpio.h
  • GPIO_PortSourceGPIOF : stm32f10x_gpio.h
  • GPIO_PortSourceGPIOG : stm32f10x_gpio.h
  • GPIO_ReadInputData() : stm32f10x_gpio.c , stm32f10x_gpio.h
  • GPIO_ReadInputDataBit() : stm32f10x_gpio.c , stm32f10x_gpio.h
  • GPIO_ReadOutputData() : stm32f10x_gpio.c , stm32f10x_gpio.h
  • GPIO_ReadOutputDataBit() : stm32f10x_gpio.c , stm32f10x_gpio.h
  • GPIO_Remap1_CAN1 : stm32f10x_gpio.h
  • GPIO_Remap2_CAN1 : stm32f10x_gpio.h
  • GPIO_Remap_ADC1_ETRGINJ : stm32f10x_gpio.h
  • GPIO_Remap_ADC1_ETRGREG : stm32f10x_gpio.h
  • GPIO_Remap_ADC2_ETRGINJ : stm32f10x_gpio.h
  • GPIO_Remap_ADC2_ETRGREG : stm32f10x_gpio.h
  • GPIO_Remap_CAN2 : stm32f10x_gpio.h
  • GPIO_Remap_CEC : stm32f10x_gpio.h
  • GPIO_Remap_ETH : stm32f10x_gpio.h
  • GPIO_Remap_FSMC_NADV : stm32f10x_gpio.h
  • GPIO_Remap_I2C1 : stm32f10x_gpio.h
  • GPIO_Remap_MISC : stm32f10x_gpio.h
  • GPIO_Remap_PD01 : stm32f10x_gpio.h
  • GPIO_Remap_PTP_PPS : stm32f10x_gpio.h
  • GPIO_Remap_SPI1 : stm32f10x_gpio.h
  • GPIO_Remap_SPI3 : stm32f10x_gpio.h
  • GPIO_Remap_SWJ_Disable : stm32f10x_gpio.h
  • GPIO_Remap_SWJ_JTAGDisable : stm32f10x_gpio.h
  • GPIO_Remap_SWJ_NoJTRST : stm32f10x_gpio.h
  • GPIO_Remap_TIM10 : stm32f10x_gpio.h
  • GPIO_Remap_TIM11 : stm32f10x_gpio.h
  • GPIO_Remap_TIM12 : stm32f10x_gpio.h
  • GPIO_Remap_TIM13 : stm32f10x_gpio.h
  • GPIO_Remap_TIM14 : stm32f10x_gpio.h
  • GPIO_Remap_TIM15 : stm32f10x_gpio.h
  • GPIO_Remap_TIM16 : stm32f10x_gpio.h
  • GPIO_Remap_TIM17 : stm32f10x_gpio.h
  • GPIO_Remap_TIM1_DMA : stm32f10x_gpio.h
  • GPIO_Remap_TIM2ITR1_PTP_SOF : stm32f10x_gpio.h
  • GPIO_Remap_TIM4 : stm32f10x_gpio.h
  • GPIO_Remap_TIM5CH4_LSI : stm32f10x_gpio.h
  • GPIO_Remap_TIM67_DAC_DMA : stm32f10x_gpio.h
  • GPIO_Remap_TIM9 : stm32f10x_gpio.h
  • GPIO_Remap_USART1 : stm32f10x_gpio.h
  • GPIO_Remap_USART2 : stm32f10x_gpio.h
  • GPIO_Remapping_CAN : STM32F10x_StdPeriph_Examples/CAN/Networking/main.c
  • GPIO_Remapping_CAN1 : CAN/Networking/platform_config.h
  • GPIO_Remapping_CAN2 : CAN/Networking/platform_config.h
  • GPIO_ResetBits() : stm32f10x_gpio.h , stm32f10x_gpio.c
  • GPIO_RTSPin : USART/HyperTerminal_HwFlowControl/platform_config.h
  • GPIO_RxPin : USART/HyperTerminal_HwFlowControl/platform_config.h
  • GPIO_SetBits() : stm32f10x_gpio.h , stm32f10x_gpio.c
  • GPIO_Speed_10MHz : stm32f10x_gpio.h
  • GPIO_Speed_2MHz : stm32f10x_gpio.h
  • GPIO_Speed_50MHz : stm32f10x_gpio.h
  • GPIO_StructInit() : stm32f10x_gpio.c , stm32f10x_gpio.h
  • GPIO_TxPin : USART/HyperTerminal_HwFlowControl/platform_config.h
  • GPIO_Write() : stm32f10x_gpio.c , stm32f10x_gpio.h
  • GPIO_WriteBit() : stm32f10x_gpio.h , stm32f10x_gpio.c
  • GPIOA : stm32f10x.h
  • GPIOA_BASE : stm32f10x.h
  • GPIOA_DBG : stm32f10x_ip_dbg.c
  • GPIOB : stm32f10x.h
  • GPIOB_BASE : stm32f10x.h
  • GPIOB_DBG : stm32f10x_ip_dbg.c
  • GPIOC : stm32f10x.h
  • GPIOC_BASE : stm32f10x.h
  • GPIOC_DBG : stm32f10x_ip_dbg.c
  • GPIOD : stm32f10x.h
  • GPIOD_BASE : stm32f10x.h
  • GPIOD_DBG : stm32f10x_ip_dbg.c
  • GPIOE : stm32f10x.h
  • GPIOE_BASE : stm32f10x.h
  • GPIOE_DBG : stm32f10x_ip_dbg.c
  • GPIOF : stm32f10x.h
  • GPIOF_BASE : stm32f10x.h
  • GPIOF_DBG : stm32f10x_ip_dbg.c
  • GPIOG : stm32f10x.h
  • GPIOG_BASE : stm32f10x.h
  • GPIOG_DBG : stm32f10x_ip_dbg.c
  • GPIOMode_TypeDef : stm32f10x_gpio.h
  • GPIOSpeed_TypeDef : stm32f10x_gpio.h
  • GPIOx : USART/HyperTerminal_HwFlowControl/platform_config.h
  • Green : stm32_eval.h
  • Grey : stm32_eval.h
  • GTPR_LSB_Mask : stm32f10x_usart.c
  • GTPR_MSB_Mask : stm32f10x_usart.c


STM32F10x Standard Peripherals Firmware Library: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- h -

  • HardFault_Handler() : STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/BKP/Tamper/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/DMA/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/OneNAND/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/DMA/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/DMABurst/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/OneNAND/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/DMABurst/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/SRAM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/SRAM/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/OCActive/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/OCActive/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/OCInactive/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/OCInactive/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/GPIO/IOToggle/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/OnePulse/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/GPIO/IOToggle/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/OnePulse/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/PWM_Input/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/PWM_Input/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/PWM_Output/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2C/EEPROM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/PWM_Output/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2C/EEPROM/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2C/IOExpander/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2C/IOExpander/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/DMA_Polling/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/DMA_Polling/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/HalfDuplex/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/HalfDuplex/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/FSMC/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/MultiProcessor/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/MultiProcessor/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Polling/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/FSMC/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Polling/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Printf/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Printf/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Synchronous/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Synchronous/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_it.h , STM32F10x_StdPeriph_Template/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f10x_it.c , STM32F10x_StdPeriph_Template/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/PWR/PVD/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CortexM3/BitBand/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/PWR/PVD/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/PWR/STANDBY/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/PWR/STANDBY/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/BKP/Backup_Data/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CortexM3/BitBand/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/RTC/Calendar/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/RTC/Calendar/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FLASH/Program/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SDIO/uSDCard/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/BKP/Backup_Data/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FLASH/Program/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SDIO/uSDCard/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/CRC/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SPI/CRC/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/DMA/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CortexM3/MPU/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/DMA/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/NAND/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/BKP/Tamper/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CortexM3/MPU/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/NAND/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/NOR/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SysTick/TimeBase/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/NOR/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SysTick/TimeBase/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/6Steps/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/6Steps/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/stm32f10x_it.c
  • HDMI_CEC_AUDIOSYSTEM : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_BIT_PERIOD : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_BIT_TIMING : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_BLOCK_ACKNOWLEDGE : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_CANNOTPROVIDE_SOURCE : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_CheckConnectedDevices() : stm32100b_eval_cec.c , stm32100b_eval_cec.h , stm32100e_eval_cec.c , stm32100e_eval_cec.h
  • HDMI_CEC_CommandCallBack() : stm32100b_eval_cec.c , stm32100b_eval_cec.h , stm32100e_eval_cec.c , stm32100e_eval_cec.h
  • HDMI_CEC_DEVICE_UNREGISTRED : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_DeviceMap : stm32100b_eval_cec.c , stm32100e_eval_cec.c
  • HDMI_CEC_Error : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_Follower_String : stm32100b_eval_cec.c , stm32100e_eval_cec.c
  • HDMI_CEC_GetErrorStatus() : stm32100b_eval_cec.c , stm32100b_eval_cec.h , stm32100e_eval_cec.c , stm32100e_eval_cec.h
  • HDMI_CEC_HPD_GPIO_CLK : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_HPD_GPIO_PORT : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_HPD_HIGH : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_HPD_LOW : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_HPD_PIN : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_I2C : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_I2C_CLK : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_I2C_CLOCK_SPEED : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_I2C_GPIO_CLK : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_I2C_GPIO_PORT : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_I2C_SCL_PIN : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_I2C_SDA_PIN : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_I2C_SLAVE_ADDRESS7 : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_Init() : stm32100b_eval_cec.c , stm32100b_eval_cec.h , stm32100e_eval_cec.c , stm32100e_eval_cec.h
  • HDMI_CEC_INVALID_OPERAND : stm32100e_eval_cec.h , stm32100b_eval_cec.h
  • HDMI_CEC_LINE : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_LINE_GPIO_CLK : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_LINE_GPIO_PORT : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_LINE_PIN : stm32100e_eval_cec.h , stm32100b_eval_cec.h
  • HDMI_CEC_MapStruct : stm32100b_eval_cec.c , stm32100e_eval_cec.c
  • HDMI_CEC_NOT_CORRECT_MODETORESPOND : stm32100e_eval_cec.h , stm32100b_eval_cec.h
  • HDMI_CEC_OK : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_OPCODE_ABORT : stm32100e_eval_cec.h , stm32100b_eval_cec.h
  • HDMI_CEC_OPCODE_ACTIVE_SOURCE : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_OPCODE_CEC_VERSION : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_OPCODE_CLEAR_ANALOGUE_TIMER : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_OPCODE_CLEAR_DIGITAL_TIMER : stm32100e_eval_cec.h , stm32100b_eval_cec.h
  • HDMI_CEC_OPCODE_CLEAR_EXTERNAL_TIMER : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_OPCODE_DECK_CONTROL : stm32100e_eval_cec.h , stm32100b_eval_cec.h
  • HDMI_CEC_OPCODE_DECK_STATUS : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_OPCODE_DEVICE_VENDOR_ID : stm32100e_eval_cec.h , stm32100b_eval_cec.h
  • HDMI_CEC_OPCODE_FEATURE_ABORT : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_OPCODE_GET_CEC_VERSION : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_OPCODE_GET_MENU_LANGUAGE : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_OPCODE_GIVE_AUDIO_STATUS : stm32100e_eval_cec.h , stm32100b_eval_cec.h
  • HDMI_CEC_OPCODE_GIVE_DECK_STATUS : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_OPCODE_GIVE_DEVICE_POWER_STATUS : stm32100e_eval_cec.h , stm32100b_eval_cec.h
  • HDMI_CEC_OPCODE_GIVE_DEVICE_VENDOR_ID : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_OPCODE_GIVE_OSD_NAME : stm32100e_eval_cec.h , stm32100b_eval_cec.h
  • HDMI_CEC_OPCODE_GIVE_PHYSICAL_ADDRESS : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_OPCODE_GIVE_SYSTEM_AUDIO_MODE_STATUS : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_OPCODE_GIVE_TUNER_DEVICE_STATUS : stm32100e_eval_cec.h , stm32100b_eval_cec.h
  • HDMI_CEC_OPCODE_IMAGE_VIEW_ON : stm32100e_eval_cec.h , stm32100b_eval_cec.h
  • HDMI_CEC_OPCODE_INACTIVE_SOURCE : stm32100e_eval_cec.h , stm32100b_eval_cec.h
  • HDMI_CEC_OPCODE_MENU_REQUEST : stm32100e_eval_cec.h , stm32100b_eval_cec.h
  • HDMI_CEC_OPCODE_MENU_STATUS : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_OPCODE_PLAY : stm32100e_eval_cec.h , stm32100b_eval_cec.h
  • HDMI_CEC_OPCODE_RECORD_OFF : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_OPCODE_RECORD_ON : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_OPCODE_RECORD_STATUS : stm32100e_eval_cec.h , stm32100b_eval_cec.h
  • HDMI_CEC_OPCODE_RECORD_TV_SCREEN : stm32100e_eval_cec.h , stm32100b_eval_cec.h
  • HDMI_CEC_OPCODE_REPORT_AUDIO_STATUS : stm32100e_eval_cec.h , stm32100b_eval_cec.h
  • HDMI_CEC_OPCODE_REPORT_PHYSICAL_ADDRESS : stm32100e_eval_cec.h , stm32100b_eval_cec.h
  • HDMI_CEC_OPCODE_REPORT_POWER_STATUS : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_OPCODE_REQUEST_ACTIVE_SOURCE : stm32100e_eval_cec.h , stm32100b_eval_cec.h
  • HDMI_CEC_OPCODE_ROUTING_CHANGE : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_OPCODE_ROUTING_INFORMATION : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_OPCODE_SELECT_ANALOGUE_SERVICE : stm32100e_eval_cec.h , stm32100b_eval_cec.h
  • HDMI_CEC_OPCODE_SELECT_DIGITAL_SERVICE : stm32100e_eval_cec.h , stm32100b_eval_cec.h
  • HDMI_CEC_OPCODE_SET_ANALOGUE_TIMER : stm32100e_eval_cec.h , stm32100b_eval_cec.h
  • HDMI_CEC_OPCODE_SET_AUDIO_RATE : stm32100e_eval_cec.h , stm32100b_eval_cec.h
  • HDMI_CEC_OPCODE_SET_DIGITAL_TIMER : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_OPCODE_SET_EXTERNAL_TIMER : stm32100e_eval_cec.h , stm32100b_eval_cec.h
  • HDMI_CEC_OPCODE_SET_MENU_LANGUAGE : stm32100e_eval_cec.h , stm32100b_eval_cec.h
  • HDMI_CEC_OPCODE_SET_OSD_NAME : stm32100e_eval_cec.h , stm32100b_eval_cec.h
  • HDMI_CEC_OPCODE_SET_OSD_STRING : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_OPCODE_SET_STREAM_PATH : stm32100e_eval_cec.h , stm32100b_eval_cec.h
  • HDMI_CEC_OPCODE_SET_SYSTEM_AUDIO_MODE : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_OPCODE_SET_TIMER_PROGRAM_TITLE : stm32100e_eval_cec.h , stm32100b_eval_cec.h
  • HDMI_CEC_OPCODE_STANDBY : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_OPCODE_SYSTEM_AUDIO_MODE_REQUEST : stm32100e_eval_cec.h , stm32100b_eval_cec.h
  • HDMI_CEC_OPCODE_SYSTEM_AUDIO_MODE_STATUS : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_OPCODE_TEXT_VIEW_ON : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_OPCODE_TIMER_CLEARED_STATUS : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_OPCODE_TIMER_STATUS : stm32100e_eval_cec.h , stm32100b_eval_cec.h
  • HDMI_CEC_OPCODE_TUNER_DEVICE_STATUS : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_OPCODE_TUNER_STEP_DECREMENT : stm32100e_eval_cec.h , stm32100b_eval_cec.h
  • HDMI_CEC_OPCODE_TUNER_STEP_INCREMENT : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_OPCODE_USER_CONTROL_PRESSED : stm32100e_eval_cec.h , stm32100b_eval_cec.h
  • HDMI_CEC_OPCODE_USER_CONTROL_RELEASED : stm32100e_eval_cec.h , stm32100b_eval_cec.h
  • HDMI_CEC_OPCODE_VENDOR_COMMAND : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_OPCODE_VENDOR_COMMAND_WITH_ID : stm32100e_eval_cec.h , stm32100b_eval_cec.h
  • HDMI_CEC_OPCODE_VENDOR_REMOTE_BUTTON_DOWN : stm32100e_eval_cec.h , stm32100b_eval_cec.h
  • HDMI_CEC_OPCODE_VENDOR_REMOTE_BUTTON_UP : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_PLAYBACK : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_ProcessIRQSrc() : stm32100e_eval_cec.c , stm32100b_eval_cec.h , stm32100e_eval_cec.h , stm32100b_eval_cec.c
  • HDMI_CEC_RECORDING : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_REFUSED : stm32100e_eval_cec.h , stm32100b_eval_cec.h
  • HDMI_CEC_ReportPhysicalAddress() : stm32100b_eval_cec.h , stm32100e_eval_cec.h , stm32100b_eval_cec.c , stm32100e_eval_cec.c
  • HDMI_CEC_ROOT : stm32100e_eval_cec.h , stm32100b_eval_cec.h
  • HDMI_CEC_RX_BLOCK_FINISHED : stm32100e_eval_cec.h , stm32100b_eval_cec.h
  • HDMI_CEC_RX_MessageStructPrivate : stm32100b_eval_cec.c , stm32100e_eval_cec.c
  • HDMI_CEC_START_BIT : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_TIMEOUT : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_TIMEOUT_VALUE : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_TransmitMessage() : stm32100e_eval_cec.h , stm32100e_eval_cec.c , stm32100b_eval_cec.h , stm32100b_eval_cec.c
  • HDMI_CEC_TUNER : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_TV : stm32100e_eval_cec.h , stm32100b_eval_cec.h
  • HDMI_CEC_TX_BLOCK_FINISHED : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_TX_MESSAGE_LENGTH_MAX : stm32100e_eval_cec.h , stm32100b_eval_cec.h
  • HDMI_CEC_TX_MessageStructPrivate : stm32100e_eval_cec.c , stm32100b_eval_cec.c
  • HDMI_CEC_TX_MessageStructure : stm32100e_eval_cec.c , stm32100b_eval_cec.c
  • HDMI_CEC_UNRECOGNIZED_OPCODE : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_VERSION : stm32100e_eval_cec.h , stm32100b_eval_cec.h
  • HeaderBlockValueToSend : STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.c
  • HIST_LENGHT : STM32F10x_StdPeriph_Examples/USART/Smartcard/main.c
  • Horizontal : stm32_eval.h
  • HSE_STARTUP_TIMEOUT : stm32f10x.h
  • HSE_Value : stm32f10x.h
  • HSE_VALUE : stm32f10x.h
  • HSEStartUp_TimeOut : stm32f10x.h
  • HSEStartUpStatus : STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/main.c , STM32F10x_StdPeriph_Examples/I2S/Interrupt/main.c , STM32F10x_StdPeriph_Examples/PWR/STOP/main.c , STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/main.c
  • HSI_VALUE : stm32f10x.h
  • HSI_Value : stm32f10x.h
  • HSION_BitNumber : stm32f10x_rcc.c


STM32F10x Standard Peripherals Firmware Library: Globals

  • File List
  • Globals
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- i -

  • I2C1 : stm32f10x.h
  • I2C1_BASE : stm32f10x.h
  • I2C1_Buffer_Tx : STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/main.c
  • I2C1_DBG : stm32f10x_ip_dbg.c
  • I2C1_DR_Address : STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/main.c
  • I2C1_ER_IRQHandler() : STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/stm32f10x_it.c
  • I2C1_SLAVE_ADDRESS7 : STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/main.c
  • I2C2 : stm32f10x.h
  • I2C2_BASE : stm32f10x.h
  • I2C2_Buffer_Rx : STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/main.c
  • I2C2_DBG : stm32f10x_ip_dbg.c
  • I2C2_DR_Address : STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/main.c
  • I2C2_SLAVE_ADDRESS7 : STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/main.c
  • I2C_Ack_Disable : stm32f10x_i2c.h
  • I2C_Ack_Enable : stm32f10x_i2c.h
  • I2C_AcknowledgeConfig() : stm32f10x_i2c.h , stm32f10x_i2c.c
  • I2C_AcknowledgedAddress_10bit : stm32f10x_i2c.h
  • I2C_AcknowledgedAddress_7bit : stm32f10x_i2c.h
  • I2C_ARPCmd() : stm32f10x_i2c.h , stm32f10x_i2c.c
  • I2C_CalculatePEC() : stm32f10x_i2c.h , stm32f10x_i2c.c
  • I2C_CCR_CCR : stm32f10x.h
  • I2C_CCR_DUTY : stm32f10x.h
  • I2C_CCR_FS : stm32f10x.h
  • I2C_CheckEvent() : stm32f10x_i2c.h , stm32f10x_i2c.c
  • I2C_ClearFlag() : stm32f10x_i2c.h , stm32f10x_i2c.c
  • I2C_ClearITPendingBit() : stm32f10x_i2c.c , stm32f10x_i2c.h
  • I2C_Cmd() : stm32f10x_i2c.h , stm32f10x_i2c.c
  • I2C_CR1_ACK : stm32f10x.h
  • I2C_CR1_ALERT : stm32f10x.h
  • I2C_CR1_ENARP : stm32f10x.h
  • I2C_CR1_ENGC : stm32f10x.h
  • I2C_CR1_ENPEC : stm32f10x.h
  • I2C_CR1_NOSTRETCH : stm32f10x.h
  • I2C_CR1_PE : stm32f10x.h
  • I2C_CR1_PEC : stm32f10x.h
  • I2C_CR1_POS : stm32f10x.h
  • I2C_CR1_SMBTYPE : stm32f10x.h
  • I2C_CR1_SMBUS : stm32f10x.h
  • I2C_CR1_START : stm32f10x.h
  • I2C_CR1_STOP : stm32f10x.h
  • I2C_CR1_SWRST : stm32f10x.h
  • I2C_CR2_DMAEN : stm32f10x.h
  • I2C_CR2_FREQ : stm32f10x.h
  • I2C_CR2_FREQ_0 : stm32f10x.h
  • I2C_CR2_FREQ_1 : stm32f10x.h
  • I2C_CR2_FREQ_2 : stm32f10x.h
  • I2C_CR2_FREQ_3 : stm32f10x.h
  • I2C_CR2_FREQ_4 : stm32f10x.h
  • I2C_CR2_FREQ_5 : stm32f10x.h
  • I2C_CR2_ITBUFEN : stm32f10x.h
  • I2C_CR2_ITERREN : stm32f10x.h
  • I2C_CR2_ITEVTEN : stm32f10x.h
  • I2C_CR2_LAST : stm32f10x.h
  • I2C_DeInit() : stm32f10x_i2c.h , stm32f10x_i2c.c
  • I2C_Direction_Receiver : stm32f10x_i2c.h
  • I2C_Direction_Transmitter : stm32f10x_i2c.h
  • I2C_DMACmd() : stm32f10x_i2c.h , stm32f10x_i2c.c
  • I2C_DMALastTransferCmd() : stm32f10x_i2c.h , stm32f10x_i2c.c
  • I2C_DR_DR : stm32f10x.h
  • I2C_DualAddressCmd() : stm32f10x_i2c.h , stm32f10x_i2c.c
  • I2C_DutyCycle_16_9 : stm32f10x_i2c.h
  • I2C_DutyCycle_2 : stm32f10x_i2c.h
  • I2C_EVENT_MASTER_BYTE_RECEIVED : stm32f10x_i2c.h
  • I2C_EVENT_MASTER_BYTE_TRANSMITTED : stm32f10x_i2c.h
  • I2C_EVENT_MASTER_BYTE_TRANSMITTING : stm32f10x_i2c.h
  • I2C_EVENT_MASTER_MODE_ADDRESS10 : stm32f10x_i2c.h
  • I2C_EVENT_MASTER_MODE_SELECT : stm32f10x_i2c.h
  • I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED : stm32f10x_i2c.h
  • I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED : stm32f10x_i2c.h
  • I2C_EVENT_SLAVE_ACK_FAILURE : stm32f10x_i2c.h
  • I2C_EVENT_SLAVE_BYTE_RECEIVED : stm32f10x_i2c.h
  • I2C_EVENT_SLAVE_BYTE_TRANSMITTED : stm32f10x_i2c.h
  • I2C_EVENT_SLAVE_BYTE_TRANSMITTING : stm32f10x_i2c.h
  • I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED : stm32f10x_i2c.h
  • I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED : stm32f10x_i2c.h
  • I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED : stm32f10x_i2c.h
  • I2C_EVENT_SLAVE_STOP_DETECTED : stm32f10x_i2c.h
  • I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED : stm32f10x_i2c.h
  • I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED : stm32f10x_i2c.h
  • I2C_FastModeDutyCycleConfig() : stm32f10x_i2c.h , stm32f10x_i2c.c
  • I2C_FLAG_ADD10 : stm32f10x_i2c.h
  • I2C_FLAG_ADDR : stm32f10x_i2c.h
  • I2C_FLAG_AF : stm32f10x_i2c.h
  • I2C_FLAG_ARLO : stm32f10x_i2c.h
  • I2C_FLAG_BERR : stm32f10x_i2c.h
  • I2C_FLAG_BTF : stm32f10x_i2c.h
  • I2C_FLAG_BUSY : stm32f10x_i2c.h
  • I2C_FLAG_DUALF : stm32f10x_i2c.h
  • I2C_FLAG_GENCALL : stm32f10x_i2c.h
  • I2C_FLAG_MSL : stm32f10x_i2c.h
  • I2C_FLAG_OVR : stm32f10x_i2c.h
  • I2C_FLAG_PECERR : stm32f10x_i2c.h
  • I2C_FLAG_RXNE : stm32f10x_i2c.h
  • I2C_FLAG_SB : stm32f10x_i2c.h
  • I2C_FLAG_SMBALERT : stm32f10x_i2c.h
  • I2C_FLAG_SMBDEFAULT : stm32f10x_i2c.h
  • I2C_FLAG_SMBHOST : stm32f10x_i2c.h
  • I2C_FLAG_STOPF : stm32f10x_i2c.h
  • I2C_FLAG_TIMEOUT : stm32f10x_i2c.h
  • I2C_FLAG_TRA : stm32f10x_i2c.h
  • I2C_FLAG_TXE : stm32f10x_i2c.h
  • I2C_GeneralCallCmd() : stm32f10x_i2c.h , stm32f10x_i2c.c
  • I2C_GenerateSTART() : stm32f10x_i2c.h , stm32f10x_i2c.c
  • I2C_GenerateSTOP() : stm32f10x_i2c.h , stm32f10x_i2c.c
  • I2C_GetFlagStatus() : stm32f10x_i2c.h , stm32f10x_i2c.c
  • I2C_GetITStatus() : stm32f10x_i2c.h , stm32f10x_i2c.c
  • I2C_GetLastEvent() : stm32f10x_i2c.h , stm32f10x_i2c.c
  • I2C_GetPEC() : stm32f10x_i2c.h , stm32f10x_i2c.c
  • I2C_Init() : stm32f10x_i2c.h , stm32f10x_i2c.c
  • I2C_InitStructure : STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/main.c
  • I2C_IT_ADD10 : stm32f10x_i2c.h
  • I2C_IT_ADDR : stm32f10x_i2c.h
  • I2C_IT_AF : stm32f10x_i2c.h
  • I2C_IT_ARLO : stm32f10x_i2c.h
  • I2C_IT_BERR : stm32f10x_i2c.h
  • I2C_IT_BTF : stm32f10x_i2c.h
  • I2C_IT_BUF : stm32f10x_i2c.h
  • I2C_IT_ERR : stm32f10x_i2c.h
  • I2C_IT_EVT : stm32f10x_i2c.h
  • I2C_IT_OVR : stm32f10x_i2c.h
  • I2C_IT_PECERR : stm32f10x_i2c.h
  • I2C_IT_RXNE : stm32f10x_i2c.h
  • I2C_IT_SB : stm32f10x_i2c.h
  • I2C_IT_SMBALERT : stm32f10x_i2c.h
  • I2C_IT_STOPF : stm32f10x_i2c.h
  • I2C_IT_TIMEOUT : stm32f10x_i2c.h
  • I2C_IT_TXE : stm32f10x_i2c.h
  • I2C_ITConfig() : stm32f10x_i2c.h , stm32f10x_i2c.c
  • I2C_Mode_I2C : stm32f10x_i2c.h
  • I2C_Mode_SMBusDevice : stm32f10x_i2c.h
  • I2C_Mode_SMBusHost : stm32f10x_i2c.h
  • I2C_NACKPosition_Current : stm32f10x_i2c.h
  • I2C_NACKPosition_Next : stm32f10x_i2c.h
  • I2C_NACKPositionConfig() : stm32f10x_i2c.h , stm32f10x_i2c.c
  • I2C_OAR1_ADD0 : stm32f10x.h
  • I2C_OAR1_ADD1 : stm32f10x.h
  • I2C_OAR1_ADD1_7 : stm32f10x.h
  • I2C_OAR1_ADD2 : stm32f10x.h
  • I2C_OAR1_ADD3 : stm32f10x.h
  • I2C_OAR1_ADD4 : stm32f10x.h
  • I2C_OAR1_ADD5 : stm32f10x.h
  • I2C_OAR1_ADD6 : stm32f10x.h
  • I2C_OAR1_ADD7 : stm32f10x.h
  • I2C_OAR1_ADD8 : stm32f10x.h
  • I2C_OAR1_ADD8_9 : stm32f10x.h
  • I2C_OAR1_ADD9 : stm32f10x.h
  • I2C_OAR1_ADDMODE : stm32f10x.h
  • I2C_OAR2_ADD2 : stm32f10x.h
  • I2C_OAR2_ENDUAL : stm32f10x.h
  • I2C_OwnAddress2Config() : stm32f10x_i2c.h , stm32f10x_i2c.c
  • I2C_PECPosition_Current : stm32f10x_i2c.h
  • I2C_PECPosition_Next : stm32f10x_i2c.h
  • I2C_PECPositionConfig() : stm32f10x_i2c.h , stm32f10x_i2c.c
  • I2C_ReadDataBuffer() : stm32100e_eval_ioe.c , stm32100e_eval_ioe.h , stm3210c_eval_ioe.c , stm3210c_eval_ioe.h
  • I2C_ReadDeviceRegister() : stm32100e_eval_ioe.c , stm32100e_eval_ioe.h , stm3210c_eval_ioe.c , stm3210c_eval_ioe.h
  • I2C_ReadRegister() : stm32f10x_i2c.h , stm32f10x_i2c.c
  • I2C_ReceiveData() : stm32f10x_i2c.h , stm32f10x_i2c.c
  • I2C_Register_CCR : stm32f10x_i2c.h
  • I2C_Register_CR1 : stm32f10x_i2c.h
  • I2C_Register_CR2 : stm32f10x_i2c.h
  • I2C_Register_DR : stm32f10x_i2c.h
  • I2C_Register_OAR1 : stm32f10x_i2c.h
  • I2C_Register_OAR2 : stm32f10x_i2c.h
  • I2C_Register_SR1 : stm32f10x_i2c.h
  • I2C_Register_SR2 : stm32f10x_i2c.h
  • I2C_Register_TRISE : stm32f10x_i2c.h
  • I2C_Send7bitAddress() : stm32f10x_i2c.h , stm32f10x_i2c.c
  • I2C_SendData() : stm32f10x_i2c.h , stm32f10x_i2c.c
  • I2C_SLAVE_ADDRESS7 : stm32_eval_i2c_ee.h , stm32l152_eval_i2c_ee.h
  • I2C_SMBusAlert_High : stm32f10x_i2c.h
  • I2C_SMBusAlert_Low : stm32f10x_i2c.h
  • I2C_SMBusAlertConfig() : stm32f10x_i2c.h , stm32f10x_i2c.c
  • I2C_SoftwareResetCmd() : stm32f10x_i2c.h , stm32f10x_i2c.c
  • I2C_SPEED : stm32_eval_i2c_ee.h , stm32l152_eval_i2c_ee.h
  • I2C_SR1_ADD10 : stm32f10x.h
  • I2C_SR1_ADDR : stm32f10x.h
  • I2C_SR1_AF : stm32f10x.h
  • I2C_SR1_ARLO : stm32f10x.h
  • I2C_SR1_BERR : stm32f10x.h
  • I2C_SR1_BTF : stm32f10x.h
  • I2C_SR1_OVR : stm32f10x.h
  • I2C_SR1_PECERR : stm32f10x.h
  • I2C_SR1_RXNE : stm32f10x.h
  • I2C_SR1_SB : stm32f10x.h
  • I2C_SR1_SMBALERT : stm32f10x.h
  • I2C_SR1_STOPF : stm32f10x.h
  • I2C_SR1_TIMEOUT : stm32f10x.h
  • I2C_SR1_TXE : stm32f10x.h
  • I2C_SR2_BUSY : stm32f10x.h
  • I2C_SR2_DUALF : stm32f10x.h
  • I2C_SR2_GENCALL : stm32f10x.h
  • I2C_SR2_MSL : stm32f10x.h
  • I2C_SR2_PEC : stm32f10x.h
  • I2C_SR2_SMBDEFAULT : stm32f10x.h
  • I2C_SR2_SMBHOST : stm32f10x.h
  • I2C_SR2_TRA : stm32f10x.h
  • I2C_StretchClockCmd() : stm32f10x_i2c.h , stm32f10x_i2c.c
  • I2C_StructInit() : stm32f10x_i2c.h , stm32f10x_i2c.c
  • I2C_TIMEOUT : stm32_eval_i2c_tsensor.h
  • I2C_TransmitPEC() : stm32f10x_i2c.h , stm32f10x_i2c.c
  • I2C_TRISE_TRISE : stm32f10x.h
  • I2C_WriteDeviceRegister() : stm32100e_eval_ioe.c , stm32100e_eval_ioe.h , stm3210c_eval_ioe.c , stm3210c_eval_ioe.h
  • I2S2_Buffer_Rx : STM32F10x_StdPeriph_Examples/I2S/Interrupt/main.c , STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/main.c
  • I2S2_CLOCK_SRC : stm32f10x_spi.c
  • I2S3_Buffer_Tx : STM32F10x_StdPeriph_Examples/I2S/Interrupt/main.c , STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/main.c
  • I2S3_CLOCK_SRC : stm32f10x_spi.c
  • I2S_AudioFreq_11k : stm32f10x_spi.h
  • I2S_AudioFreq_16k : stm32f10x_spi.h
  • I2S_AudioFreq_192k : stm32f10x_spi.h
  • I2S_AudioFreq_22k : stm32f10x_spi.h
  • I2S_AudioFreq_32k : stm32f10x_spi.h
  • I2S_AudioFreq_44k : stm32f10x_spi.h
  • I2S_AudioFreq_48k : stm32f10x_spi.h
  • I2S_AudioFreq_8k : stm32f10x_spi.h
  • I2S_AudioFreq_96k : stm32f10x_spi.h
  • I2S_AudioFreq_Default : stm32f10x_spi.h
  • I2S_Cmd() : stm32f10x_spi.h , stm32f10x_spi.c
  • I2S_CPOL_High : stm32f10x_spi.h
  • I2S_CPOL_Low : stm32f10x_spi.h
  • I2S_DataFormat_16b : stm32f10x_spi.h
  • I2S_DataFormat_16bextended : stm32f10x_spi.h
  • I2S_DataFormat_24b : stm32f10x_spi.h
  • I2S_DataFormat_32b : stm32f10x_spi.h
  • I2S_DIV_MASK : stm32f10x_spi.c
  • I2S_FLAG_CHSIDE : stm32f10x_spi.h
  • I2S_FLAG_UDR : stm32f10x_spi.h
  • I2S_Init() : stm32f10x_spi.h , stm32f10x_spi.c
  • I2S_InitStructure : STM32F10x_StdPeriph_Examples/I2S/Interrupt/main.c , STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/main.c
  • I2S_IT_UDR : stm32f10x_spi.h
  • I2S_MCLKOutput_Disable : stm32f10x_spi.h
  • I2S_MCLKOutput_Enable : stm32f10x_spi.h
  • I2S_Mode_MasterRx : stm32f10x_spi.h
  • I2S_Mode_MasterTx : stm32f10x_spi.h
  • I2S_Mode_Select : stm32f10x_spi.c
  • I2S_Mode_SlaveRx : stm32f10x_spi.h
  • I2S_Mode_SlaveTx : stm32f10x_spi.h
  • I2S_MUL_MASK : stm32f10x_spi.c
  • I2S_Standard_LSB : stm32f10x_spi.h
  • I2S_Standard_MSB : stm32f10x_spi.h
  • I2S_Standard_PCMLong : stm32f10x_spi.h
  • I2S_Standard_PCMShort : stm32f10x_spi.h
  • I2S_Standard_Phillips : stm32f10x_spi.h
  • I2S_StructInit() : stm32f10x_spi.h , stm32f10x_spi.c
  • I2SCFGR_CLEAR_Mask : stm32f10x_spi.c
  • I2SCFGR_I2SE_Reset : stm32f10x_spi.c
  • I2SCFGR_I2SE_Set : stm32f10x_spi.c
  • IC1ReadValue1 : STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_it.c
  • IC1ReadValue2 : STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_it.c
  • IC2Value : STM32F10x_StdPeriph_Examples/TIM/PWM_Input/stm32f10x_it.c
  • IC3ReadValue1 : STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_it.c
  • IC3ReadValue2 : STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_it.c
  • IDCODE_DEVID_MASK : stm32f10x_dbgmcu.c
  • Idx : STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/main.c , STM32F10x_StdPeriph_Examples/DMA/FSMC/main.c
  • IE_BitNumber : stm32f10x_cec.c
  • INAK_TIMEOUT : stm32f10x_can.c
  • IncrementVar_OperationComplete() : STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/main.c , RTC/LSI_Calib/main.h
  • index : STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/main.c , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/main.c , STM32F10x_StdPeriph_Examples/USART/Polling/main.c , STM32F10x_StdPeriph_Examples/USART/Smartcard/main.c
  • Index : STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/main.c , STM32F10x_StdPeriph_Examples/FSMC/NOR/main.c , STM32F10x_StdPeriph_Examples/FSMC/SRAM/main.c , STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/main.c , STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/main.c
  • Init_RxMes() : STM32F10x_StdPeriph_Examples/CAN/DualCAN/main.c , STM32F10x_StdPeriph_Examples/CAN/Networking/main.c
  • InitiatorAddress : STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.c
  • IO1_IN_ALL_PINS : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IO1_OUT_ALL_PINS : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IO2_IN_ALL_PINS : stm3210c_eval_ioe.h
  • IO2_OUT_ALL_PINS : stm3210c_eval_ioe.h
  • IO_IT_0 : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IO_IT_1 : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IO_IT_2 : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IO_IT_3 : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IO_IT_4 : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IO_IT_5 : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IO_IT_6 : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IO_IT_7 : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IO_Pin_0 : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IO_Pin_1 : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IO_Pin_2 : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IO_Pin_3 : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IO_Pin_4 : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IO_Pin_5 : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IO_Pin_6 : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IO_Pin_7 : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IO_Pin_ALL : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE1_NOT_OPERATIONAL : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE2_NOT_OPERATIONAL : stm3210c_eval_ioe.h
  • IOE_1_ADDR : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_2_ADDR : stm3210c_eval_ioe.h
  • IOE_ADC_FCT : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_BitValue_TypeDef : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_ClearGITPending() : stm32100e_eval_ioe.c , stm32100e_eval_ioe.h , stm3210c_eval_ioe.c , stm3210c_eval_ioe.h
  • IOE_ClearIOITPending() : stm32100e_eval_ioe.c , stm32100e_eval_ioe.h , stm3210c_eval_ioe.c , stm3210c_eval_ioe.h
  • IOE_Config() : stm32100e_eval_ioe.c , stm32100e_eval_ioe.h , stm3210c_eval_ioe.c , stm3210c_eval_ioe.h
  • IOE_DMA : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_DMA_CLK : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_DMA_Config() : stm32100e_eval_ioe.c , stm3210c_eval_ioe.c
  • IOE_DMA_RX : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_DMA_RX_CHANNEL : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_DMA_RX_TCFLAG : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_DMA_TX : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_DMA_TX_CHANNEL : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_DMA_TX_TCFLAG : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_DMADirection_TypeDef : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_EXTI_Config() : stm32100e_eval_ioe.c , stm3210c_eval_ioe.c
  • IOE_FAILURE : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_FnctCmd() : stm32100e_eval_ioe.c , stm32100e_eval_ioe.h , stm3210c_eval_ioe.c , stm3210c_eval_ioe.h
  • IOE_GetGITStatus() : stm32100e_eval_ioe.c , stm32100e_eval_ioe.h , stm3210c_eval_ioe.c , stm3210c_eval_ioe.h
  • IOE_GetIOITStatus() : stm32100e_eval_ioe.c , stm32100e_eval_ioe.h , stm3210c_eval_ioe.c , stm3210c_eval_ioe.h
  • IOE_GIT_ADC : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_GIT_EN : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_GIT_FE : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_GIT_FF : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_GIT_FOV : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_GIT_FTH : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_GIT_GPIO : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_GIT_TEMP : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_GIT_TOUCH : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_GITCmd() : stm32100e_eval_ioe.c , stm32100e_eval_ioe.h , stm3210c_eval_ioe.c , stm3210c_eval_ioe.h
  • IOE_GITConfig() : stm32100e_eval_ioe.c , stm32100e_eval_ioe.h , stm3210c_eval_ioe.c , stm3210c_eval_ioe.h
  • IOE_GPIO_Config() : stm32100e_eval_ioe.c , stm3210c_eval_ioe.c
  • IOE_I2C : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_I2C_CLK : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_I2C_Config() : stm32100e_eval_ioe.c , stm3210c_eval_ioe.c
  • IOE_I2C_DR : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_I2C_SCL_GPIO_CLK : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_I2C_SCL_GPIO_PORT : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_I2C_SCL_PIN : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_I2C_SDA_GPIO_CLK : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_I2C_SDA_GPIO_PORT : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_I2C_SDA_PIN : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_I2C_SPEED : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_INMEMS_IT : stm3210c_eval_ioe.h
  • IOE_INTERRUPT_MODE : I2C/IOExpander/main.h
  • IOE_IO_FCT : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_IOAFConfig() : stm32100e_eval_ioe.c , stm32100e_eval_ioe.h , stm3210c_eval_ioe.c , stm3210c_eval_ioe.h
  • IOE_IOEdgeConfig() : stm32100e_eval_ioe.c , stm32100e_eval_ioe.h , stm3210c_eval_ioe.c , stm3210c_eval_ioe.h
  • IOE_IOITConfig() : stm32100e_eval_ioe.c , stm32100e_eval_ioe.h , stm3210c_eval_ioe.c , stm3210c_eval_ioe.h
  • IOE_IOPinConfig() : stm32100e_eval_ioe.c , stm32100e_eval_ioe.h , stm3210c_eval_ioe.c , stm3210c_eval_ioe.h
  • IOE_IsOperational() : stm32100e_eval_ioe.c , stm32100e_eval_ioe.h , stm3210c_eval_ioe.c , stm3210c_eval_ioe.h
  • IOE_IT_EXTI_IRQn : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_IT_EXTI_LINE : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_IT_EXTI_PIN_SOURCE : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_IT_EXTI_PORT_SOURCE : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_IT_GPIO_CLK : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_IT_GPIO_PORT : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_IT_PIN : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_ITConfig() : stm32100e_eval_ioe.c , stm32100e_eval_ioe.h , stm3210c_eval_ioe.c , stm3210c_eval_ioe.h
  • IOE_ITOutConfig() : stm32100e_eval_ioe.c , stm32100e_eval_ioe.h , stm3210c_eval_ioe.c , stm3210c_eval_ioe.h
  • IOE_ITSRC_INMEMS : stm3210c_eval_ioe.h
  • IOE_ITSRC_JOYSTICK : stm3210c_eval_ioe.h
  • IOE_ITSRC_TEMPSENS : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_ITSRC_TSC : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_JOY_IT : stm3210c_eval_ioe.h
  • IOE_JoyStickGetState() : stm3210c_eval_ioe.c , stm3210c_eval_ioe.h
  • IOE_OK : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_ReadID() : stm32100e_eval_ioe.c , stm32100e_eval_ioe.h , stm3210c_eval_ioe.c , stm3210c_eval_ioe.h
  • IOE_ReadIOPin() : stm32100e_eval_ioe.c , stm32100e_eval_ioe.h , stm3210c_eval_ioe.c , stm3210c_eval_ioe.h
  • IOE_REG_ADC_CAPT : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_REG_ADC_CTRL1 : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_REG_ADC_CTRL2 : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_REG_ADC_DATA_CH0 : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_REG_ADC_DATA_CH1 : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_REG_ADC_DATA_CH2 : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_REG_ADC_DATA_CH3 : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_REG_ADC_DATA_CH4 : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_REG_ADC_DATA_CH5 : stm3210c_eval_ioe.h , stm32100e_eval_ioe.h
  • IOE_REG_ADC_DATA_CH6 : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_REG_ADC_DATA_CH7 : stm3210c_eval_ioe.h , stm32100e_eval_ioe.h
  • IOE_REG_ADC_INT_EN : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_REG_ADC_INT_STA : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_REG_CHP_ID : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_REG_FIFO_SIZE : stm3210c_eval_ioe.h , stm32100e_eval_ioe.h
  • IOE_REG_FIFO_STA : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_REG_FIFO_TH : stm3210c_eval_ioe.h , stm32100e_eval_ioe.h
  • IOE_REG_GPIO_AF : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_REG_GPIO_CLR_PIN : stm3210c_eval_ioe.h , stm32100e_eval_ioe.h
  • IOE_REG_GPIO_DIR : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_REG_GPIO_ED : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_REG_GPIO_FE : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_REG_GPIO_INT_EN : stm3210c_eval_ioe.h , stm32100e_eval_ioe.h
  • IOE_REG_GPIO_INT_STA : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_REG_GPIO_MP_STA : stm3210c_eval_ioe.h , stm32100e_eval_ioe.h
  • IOE_REG_GPIO_RE : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_REG_GPIO_SET_PIN : stm3210c_eval_ioe.h , stm32100e_eval_ioe.h
  • IOE_REG_ID_VER : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_REG_INT_CTRL : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_REG_INT_EN : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_REG_INT_STA : stm3210c_eval_ioe.h , stm32100e_eval_ioe.h
  • IOE_REG_SPI_CFG : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_REG_SYS_CTRL1 : stm3210c_eval_ioe.h , stm32100e_eval_ioe.h
  • IOE_REG_SYS_CTRL2 : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_REG_TEMP_CTRL : stm3210c_eval_ioe.h , stm32100e_eval_ioe.h
  • IOE_REG_TEMP_DATA : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_REG_TEMP_TH : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_REG_TSC_CFG : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_REG_TSC_CTRL : stm3210c_eval_ioe.h , stm32100e_eval_ioe.h
  • IOE_REG_TSC_DATA : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_REG_TSC_DATA_X : stm3210c_eval_ioe.h , stm32100e_eval_ioe.h
  • IOE_REG_TSC_DATA_XYZ : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_REG_TSC_DATA_Y : stm3210c_eval_ioe.h , stm32100e_eval_ioe.h
  • IOE_REG_TSC_DATA_Z : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_REG_TSC_FRACT_XYZ : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_REG_TSC_I_DRIVE : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_REG_TSC_SHIELD : stm3210c_eval_ioe.h , stm32100e_eval_ioe.h
  • IOE_REG_WDM_BL_X : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_REG_WDM_BL_Y : stm3210c_eval_ioe.h , stm32100e_eval_ioe.h
  • IOE_REG_WDM_TR_X : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_REG_WDM_TR_Y : stm3210c_eval_ioe.h , stm32100e_eval_ioe.h
  • IOE_Reset() : stm32100e_eval_ioe.c , stm32100e_eval_ioe.h , stm3210c_eval_ioe.c , stm3210c_eval_ioe.h
  • IOE_Status_TypDef : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_TempSens_Config() : stm32100e_eval_ioe.h , stm3210c_eval_ioe.c , stm3210c_eval_ioe.h , stm32100e_eval_ioe.c
  • IOE_TEMPSENS_FCT : stm3210c_eval_ioe.h , stm32100e_eval_ioe.h
  • IOE_TempSens_GetData() : stm32100e_eval_ioe.c , stm32100e_eval_ioe.h , stm3210c_eval_ioe.h , stm3210c_eval_ioe.c
  • IOE_TIMEOUT : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_TimeOut : stm32100e_eval_ioe.c , stm3210c_eval_ioe.c
  • IOE_TimeoutUserCallback : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_TS_Config() : stm32100e_eval_ioe.h , stm3210c_eval_ioe.c , stm3210c_eval_ioe.h , stm32100e_eval_ioe.c
  • IOE_TS_FCT : stm3210c_eval_ioe.h , stm32100e_eval_ioe.h
  • IOE_TS_GetState() : stm32100e_eval_ioe.c , stm32100e_eval_ioe.h , stm3210c_eval_ioe.h , stm3210c_eval_ioe.c
  • IOE_TS_IT : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_TS_Read_X() : stm32100e_eval_ioe.c , stm3210c_eval_ioe.c
  • IOE_TS_Read_Y() : stm32100e_eval_ioe.c , stm3210c_eval_ioe.c
  • IOE_TS_Read_Z() : stm3210c_eval_ioe.c , stm32100e_eval_ioe.c
  • IOE_WriteIOPin() : stm3210c_eval_ioe.c , stm32100e_eval_ioe.c , stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IRQn : stm32f10x.h
  • IRQn_Type : stm32f10x.h
  • IS_ADC_ALL_PERIPH : stm32f10x_adc.h
  • IS_ADC_ANALOG_WATCHDOG : stm32f10x_adc.h
  • IS_ADC_CHANNEL : stm32f10x_adc.h
  • IS_ADC_CLEAR_FLAG : stm32f10x_adc.h
  • IS_ADC_DATA_ALIGN : stm32f10x_adc.h
  • IS_ADC_DMA_PERIPH : stm32f10x_adc.h
  • IS_ADC_EXT_INJEC_TRIG : stm32f10x_adc.h
  • IS_ADC_EXT_TRIG : stm32f10x_adc.h
  • IS_ADC_GET_FLAG : stm32f10x_adc.h
  • IS_ADC_GET_IT : stm32f10x_adc.h
  • IS_ADC_INJECTED_CHANNEL : stm32f10x_adc.h
  • IS_ADC_INJECTED_LENGTH : stm32f10x_adc.h
  • IS_ADC_INJECTED_RANK : stm32f10x_adc.h
  • IS_ADC_IT : stm32f10x_adc.h
  • IS_ADC_MODE : stm32f10x_adc.h
  • IS_ADC_OFFSET : stm32f10x_adc.h
  • IS_ADC_REGULAR_DISC_NUMBER : stm32f10x_adc.h
  • IS_ADC_REGULAR_LENGTH : stm32f10x_adc.h
  • IS_ADC_REGULAR_RANK : stm32f10x_adc.h
  • IS_ADC_SAMPLE_TIME : stm32f10x_adc.h
  • IS_ADC_THRESHOLD : stm32f10x_adc.h
  • IS_BKP_CALIBRATION_VALUE : stm32f10x_bkp.h
  • IS_BKP_DR : stm32f10x_bkp.h
  • IS_BKP_RTC_OUTPUT_SOURCE : stm32f10x_bkp.h
  • IS_BKP_TAMPER_PIN_LEVEL : stm32f10x_bkp.h
  • IS_CAN_ALL_PERIPH : stm32f10x_can.h
  • IS_CAN_BANKNUMBER : stm32f10x_can.h
  • IS_CAN_BS1 : stm32f10x_can.h
  • IS_CAN_BS2 : stm32f10x_can.h
  • IS_CAN_CLEAR_FLAG : stm32f10x_can.h
  • IS_CAN_CLEAR_IT : stm32f10x_can.h
  • IS_CAN_DLC : stm32f10x_can.h
  • IS_CAN_EXTID : stm32f10x_can.h
  • IS_CAN_FIFO : stm32f10x_can.h
  • IS_CAN_FILTER_FIFO : stm32f10x_can.h
  • IS_CAN_FILTER_MODE : stm32f10x_can.h
  • IS_CAN_FILTER_NUMBER : stm32f10x_can.h
  • IS_CAN_FILTER_SCALE : stm32f10x_can.h
  • IS_CAN_GET_FLAG : stm32f10x_can.h
  • IS_CAN_IDTYPE : stm32f10x_can.h
  • IS_CAN_IT : stm32f10x_can.h
  • IS_CAN_MODE : stm32f10x_can.h
  • IS_CAN_OPERATING_MODE : stm32f10x_can.h
  • IS_CAN_PRESCALER : stm32f10x_can.h
  • IS_CAN_RTR : stm32f10x_can.h
  • IS_CAN_SJW : stm32f10x_can.h
  • IS_CAN_STDID : stm32f10x_can.h
  • IS_CAN_TRANSMITMAILBOX : stm32f10x_can.h
  • IS_CEC_ADDRESS : stm32f10x_cec.h
  • IS_CEC_BIT_PERIOD_ERROR_MODE : stm32f10x_cec.h
  • IS_CEC_BIT_TIMING_ERROR_MODE : stm32f10x_cec.h
  • IS_CEC_CLEAR_FLAG : stm32f10x_cec.h
  • IS_CEC_GET_FLAG : stm32f10x_cec.h
  • IS_CEC_GET_IT : stm32f10x_cec.h
  • IS_CEC_PRESCALER : stm32f10x_cec.h
  • IS_DAC_ALIGN : stm32f10x_dac.h
  • IS_DAC_CHANNEL : stm32f10x_dac.h
  • IS_DAC_DATA : stm32f10x_dac.h
  • IS_DAC_GENERATE_WAVE : stm32f10x_dac.h
  • IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE : stm32f10x_dac.h
  • IS_DAC_OUTPUT_BUFFER_STATE : stm32f10x_dac.h
  • IS_DAC_TRIGGER : stm32f10x_dac.h
  • IS_DAC_WAVE : stm32f10x_dac.h
  • IS_DBGMCU_PERIPH : stm32f10x_dbgmcu.h
  • IS_DMA_ALL_PERIPH : stm32f10x_dma.h
  • IS_DMA_BUFFER_SIZE : stm32f10x_dma.h
  • IS_DMA_CLEAR_FLAG : stm32f10x_dma.h
  • IS_DMA_CLEAR_IT : stm32f10x_dma.h
  • IS_DMA_CONFIG_IT : stm32f10x_dma.h
  • IS_DMA_DIR : stm32f10x_dma.h
  • IS_DMA_GET_FLAG : stm32f10x_dma.h
  • IS_DMA_GET_IT : stm32f10x_dma.h
  • IS_DMA_M2M_STATE : stm32f10x_dma.h
  • IS_DMA_MEMORY_DATA_SIZE : stm32f10x_dma.h
  • IS_DMA_MEMORY_INC_STATE : stm32f10x_dma.h
  • IS_DMA_MODE : stm32f10x_dma.h
  • IS_DMA_PERIPHERAL_DATA_SIZE : stm32f10x_dma.h
  • IS_DMA_PERIPHERAL_INC_STATE : stm32f10x_dma.h
  • IS_DMA_PRIORITY : stm32f10x_dma.h
  • IS_EXTI_LINE : stm32f10x_exti.h
  • IS_EXTI_MODE : stm32f10x_exti.h
  • IS_EXTI_TRIGGER : stm32f10x_exti.h
  • IS_FLASH_ADDRESS : stm32f10x_flash.h
  • IS_FLASH_CLEAR_FLAG : stm32f10x_flash.h
  • IS_FLASH_GET_FLAG : stm32f10x_flash.h
  • IS_FLASH_HALFCYCLEACCESS_STATE : stm32f10x_flash.h
  • IS_FLASH_IT : stm32f10x_flash.h
  • IS_FLASH_LATENCY : stm32f10x_flash.h
  • IS_FLASH_PREFETCHBUFFER_STATE : stm32f10x_flash.h
  • IS_FLASH_WRPROT_PAGE : stm32f10x_flash.h
  • IS_FSMC_ACCESS_MODE : stm32f10x_fsmc.h
  • IS_FSMC_ADDRESS_HOLD_TIME : stm32f10x_fsmc.h
  • IS_FSMC_ADDRESS_SETUP_TIME : stm32f10x_fsmc.h
  • IS_FSMC_ASYNWAIT : stm32f10x_fsmc.h
  • IS_FSMC_BURSTMODE : stm32f10x_fsmc.h
  • IS_FSMC_CLEAR_FLAG : stm32f10x_fsmc.h
  • IS_FSMC_CLK_DIV : stm32f10x_fsmc.h
  • IS_FSMC_DATA_LATENCY : stm32f10x_fsmc.h
  • IS_FSMC_DATASETUP_TIME : stm32f10x_fsmc.h
  • IS_FSMC_ECC_STATE : stm32f10x_fsmc.h
  • IS_FSMC_ECCPAGE_SIZE : stm32f10x_fsmc.h
  • IS_FSMC_EXTENDED_MODE : stm32f10x_fsmc.h
  • IS_FSMC_GET_FLAG : stm32f10x_fsmc.h
  • IS_FSMC_GET_IT : stm32f10x_fsmc.h
  • IS_FSMC_GETFLAG_BANK : stm32f10x_fsmc.h
  • IS_FSMC_HIZ_TIME : stm32f10x_fsmc.h
  • IS_FSMC_HOLD_TIME : stm32f10x_fsmc.h
  • IS_FSMC_IT : stm32f10x_fsmc.h
  • IS_FSMC_IT_BANK : stm32f10x_fsmc.h
  • IS_FSMC_MEMORY : stm32f10x_fsmc.h
  • IS_FSMC_MEMORY_WIDTH : stm32f10x_fsmc.h
  • IS_FSMC_MUX : stm32f10x_fsmc.h
  • IS_FSMC_NAND_BANK : stm32f10x_fsmc.h
  • IS_FSMC_NORSRAM_BANK : stm32f10x_fsmc.h
  • IS_FSMC_SETUP_TIME : stm32f10x_fsmc.h
  • IS_FSMC_TAR_TIME : stm32f10x_fsmc.h
  • IS_FSMC_TCLR_TIME : stm32f10x_fsmc.h
  • IS_FSMC_TURNAROUND_TIME : stm32f10x_fsmc.h
  • IS_FSMC_WAIT_FEATURE : stm32f10x_fsmc.h
  • IS_FSMC_WAIT_POLARITY : stm32f10x_fsmc.h
  • IS_FSMC_WAIT_SIGNAL_ACTIVE : stm32f10x_fsmc.h
  • IS_FSMC_WAIT_TIME : stm32f10x_fsmc.h
  • IS_FSMC_WAITE_SIGNAL : stm32f10x_fsmc.h
  • IS_FSMC_WRAP_MODE : stm32f10x_fsmc.h
  • IS_FSMC_WRITE_BURST : stm32f10x_fsmc.h
  • IS_FSMC_WRITE_OPERATION : stm32f10x_fsmc.h
  • IS_FUNCTIONAL_STATE : stm32f10x.h
  • IS_GET_EXTI_LINE : stm32f10x_exti.h
  • IS_GET_GPIO_PIN : stm32f10x_gpio.h
  • IS_GPIO_ALL_PERIPH : stm32f10x_gpio.h
  • IS_GPIO_BIT_ACTION : stm32f10x_gpio.h
  • IS_GPIO_ETH_MEDIA_INTERFACE : stm32f10x_gpio.h
  • IS_GPIO_EVENTOUT_PORT_SOURCE : stm32f10x_gpio.h
  • IS_GPIO_EXTI_PORT_SOURCE : stm32f10x_gpio.h
  • IS_GPIO_MODE : stm32f10x_gpio.h
  • IS_GPIO_PIN : stm32f10x_gpio.h
  • IS_GPIO_PIN_SOURCE : stm32f10x_gpio.h
  • IS_GPIO_REMAP : stm32f10x_gpio.h
  • IS_GPIO_SPEED : stm32f10x_gpio.h
  • IS_I2C_ACK_STATE : stm32f10x_i2c.h
  • IS_I2C_ACKNOWLEDGE_ADDRESS : stm32f10x_i2c.h
  • IS_I2C_ALL_PERIPH : stm32f10x_i2c.h
  • IS_I2C_CLEAR_FLAG : stm32f10x_i2c.h
  • IS_I2C_CLEAR_IT : stm32f10x_i2c.h
  • IS_I2C_CLOCK_SPEED : stm32f10x_i2c.h
  • IS_I2C_CONFIG_IT : stm32f10x_i2c.h
  • IS_I2C_DIRECTION : stm32f10x_i2c.h
  • IS_I2C_DUTY_CYCLE : stm32f10x_i2c.h
  • IS_I2C_EVENT : stm32f10x_i2c.h
  • IS_I2C_GET_FLAG : stm32f10x_i2c.h
  • IS_I2C_GET_IT : stm32f10x_i2c.h
  • IS_I2C_MODE : stm32f10x_i2c.h
  • IS_I2C_NACK_POSITION : stm32f10x_i2c.h
  • IS_I2C_OWN_ADDRESS1 : stm32f10x_i2c.h
  • IS_I2C_PEC_POSITION : stm32f10x_i2c.h
  • IS_I2C_REGISTER : stm32f10x_i2c.h
  • IS_I2C_SMBUS_ALERT : stm32f10x_i2c.h
  • IS_I2S_AUDIO_FREQ : stm32f10x_spi.h
  • IS_I2S_CPOL : stm32f10x_spi.h
  • IS_I2S_DATA_FORMAT : stm32f10x_spi.h
  • IS_I2S_MCLK_OUTPUT : stm32f10x_spi.h
  • IS_I2S_MODE : stm32f10x_spi.h
  • IS_I2S_STANDARD : stm32f10x_spi.h
  • IS_IWDG_FLAG : stm32f10x_iwdg.h
  • IS_IWDG_PRESCALER : stm32f10x_iwdg.h
  • IS_IWDG_RELOAD : stm32f10x_iwdg.h
  • IS_IWDG_WRITE_ACCESS : stm32f10x_iwdg.h
  • IS_NVIC_LP : misc.h
  • IS_NVIC_OFFSET : misc.h
  • IS_NVIC_PREEMPTION_PRIORITY : misc.h
  • IS_NVIC_PRIORITY_GROUP : misc.h
  • IS_NVIC_SUB_PRIORITY : misc.h
  • IS_NVIC_VECTTAB : misc.h
  • IS_OB_DATA_ADDRESS : stm32f10x_flash.h
  • IS_OB_IWDG_SOURCE : stm32f10x_flash.h
  • IS_OB_STDBY_SOURCE : stm32f10x_flash.h
  • IS_OB_STOP_SOURCE : stm32f10x_flash.h
  • IS_PWR_CLEAR_FLAG : stm32f10x_pwr.h
  • IS_PWR_GET_FLAG : stm32f10x_pwr.h
  • IS_PWR_PVD_LEVEL : stm32f10x_pwr.h
  • IS_PWR_REGULATOR : stm32f10x_pwr.h
  • IS_PWR_STOP_ENTRY : stm32f10x_pwr.h
  • IS_RCC_ADCCLK : stm32f10x_rcc.h
  • IS_RCC_AHB_PERIPH : stm32f10x_rcc.h
  • IS_RCC_APB1_PERIPH : stm32f10x_rcc.h
  • IS_RCC_APB2_PERIPH : stm32f10x_rcc.h
  • IS_RCC_CALIBRATION_VALUE : stm32f10x_rcc.h
  • IS_RCC_CLEAR_IT : stm32f10x_rcc.h
  • IS_RCC_FLAG : stm32f10x_rcc.h
  • IS_RCC_GET_IT : stm32f10x_rcc.h
  • IS_RCC_HCLK : stm32f10x_rcc.h
  • IS_RCC_HSE : stm32f10x_rcc.h
  • IS_RCC_IT : stm32f10x_rcc.h
  • IS_RCC_LSE : stm32f10x_rcc.h
  • IS_RCC_MCO : stm32f10x_rcc.h
  • IS_RCC_PCLK : stm32f10x_rcc.h
  • IS_RCC_PLL_MUL : stm32f10x_rcc.h
  • IS_RCC_PLL_SOURCE : stm32f10x_rcc.h
  • IS_RCC_RTCCLK_SOURCE : stm32f10x_rcc.h
  • IS_RCC_SYSCLK_SOURCE : stm32f10x_rcc.h
  • IS_RCC_USBCLK_SOURCE : stm32f10x_rcc.h
  • IS_RTC_CLEAR_FLAG : stm32f10x_rtc.h
  • IS_RTC_GET_FLAG : stm32f10x_rtc.h
  • IS_RTC_GET_IT : stm32f10x_rtc.h
  • IS_RTC_IT : stm32f10x_rtc.h
  • IS_RTC_PRESCALER : stm32f10x_rtc.h
  • IS_SDIO_BLOCK_SIZE : stm32f10x_sdio.h
  • IS_SDIO_BUS_WIDE : stm32f10x_sdio.h
  • IS_SDIO_CLEAR_FLAG : stm32f10x_sdio.h
  • IS_SDIO_CLEAR_IT : stm32f10x_sdio.h
  • IS_SDIO_CLOCK_BYPASS : stm32f10x_sdio.h
  • IS_SDIO_CLOCK_EDGE : stm32f10x_sdio.h
  • IS_SDIO_CLOCK_POWER_SAVE : stm32f10x_sdio.h
  • IS_SDIO_CMD_INDEX : stm32f10x_sdio.h
  • IS_SDIO_CPSM : stm32f10x_sdio.h
  • IS_SDIO_DATA_LENGTH : stm32f10x_sdio.h
  • IS_SDIO_DPSM : stm32f10x_sdio.h
  • IS_SDIO_FLAG : stm32f10x_sdio.h
  • IS_SDIO_GET_IT : stm32f10x_sdio.h
  • IS_SDIO_HARDWARE_FLOW_CONTROL : stm32f10x_sdio.h
  • IS_SDIO_IT : stm32f10x_sdio.h
  • IS_SDIO_POWER_STATE : stm32f10x_sdio.h
  • IS_SDIO_READWAIT_MODE : stm32f10x_sdio.h
  • IS_SDIO_RESP : stm32f10x_sdio.h
  • IS_SDIO_RESPONSE : stm32f10x_sdio.h
  • IS_SDIO_TRANSFER_DIR : stm32f10x_sdio.h
  • IS_SDIO_TRANSFER_MODE : stm32f10x_sdio.h
  • IS_SDIO_WAIT : stm32f10x_sdio.h
  • IS_SPI_23_PERIPH : stm32f10x_spi.h
  • IS_SPI_ALL_PERIPH : stm32f10x_spi.h
  • IS_SPI_BAUDRATE_PRESCALER : stm32f10x_spi.h
  • IS_SPI_CPHA : stm32f10x_spi.h
  • IS_SPI_CPOL : stm32f10x_spi.h
  • IS_SPI_CRC : stm32f10x_spi.h
  • IS_SPI_CRC_POLYNOMIAL : stm32f10x_spi.h
  • IS_SPI_DATASIZE : stm32f10x_spi.h
  • IS_SPI_DIRECTION : stm32f10x_spi.h
  • IS_SPI_DIRECTION_MODE : stm32f10x_spi.h
  • IS_SPI_FIRST_BIT : stm32f10x_spi.h
  • IS_SPI_I2S_CLEAR_FLAG : stm32f10x_spi.h
  • IS_SPI_I2S_CLEAR_IT : stm32f10x_spi.h
  • IS_SPI_I2S_CONFIG_IT : stm32f10x_spi.h
  • IS_SPI_I2S_DMAREQ : stm32f10x_spi.h
  • IS_SPI_I2S_GET_FLAG : stm32f10x_spi.h
  • IS_SPI_I2S_GET_IT : stm32f10x_spi.h
  • IS_SPI_MODE : stm32f10x_spi.h
  • IS_SPI_NSS : stm32f10x_spi.h
  • IS_SPI_NSS_INTERNAL : stm32f10x_spi.h
  • IS_SYSTICK_CLK_SOURCE : misc.h
  • IS_TIM_ALL_PERIPH : stm32f10x_tim.h
  • IS_TIM_AUTOMATIC_OUTPUT_STATE : stm32f10x_tim.h
  • IS_TIM_BREAK_POLARITY : stm32f10x_tim.h
  • IS_TIM_BREAK_STATE : stm32f10x_tim.h
  • IS_TIM_CCX : stm32f10x_tim.h
  • IS_TIM_CCXN : stm32f10x_tim.h
  • IS_TIM_CHANNEL : stm32f10x_tim.h
  • IS_TIM_CKD_DIV : stm32f10x_tim.h
  • IS_TIM_CLEAR_FLAG : stm32f10x_tim.h
  • IS_TIM_COMPLEMENTARY_CHANNEL : stm32f10x_tim.h
  • IS_TIM_COUNTER_MODE : stm32f10x_tim.h
  • IS_TIM_DMA_BASE : stm32f10x_tim.h
  • IS_TIM_DMA_LENGTH : stm32f10x_tim.h
  • IS_TIM_DMA_SOURCE : stm32f10x_tim.h
  • IS_TIM_ENCODER_MODE : stm32f10x_tim.h
  • IS_TIM_EVENT_SOURCE : stm32f10x_tim.h
  • IS_TIM_EXT_FILTER : stm32f10x_tim.h
  • IS_TIM_EXT_POLARITY : stm32f10x_tim.h
  • IS_TIM_EXT_PRESCALER : stm32f10x_tim.h
  • IS_TIM_FORCED_ACTION : stm32f10x_tim.h
  • IS_TIM_GET_FLAG : stm32f10x_tim.h
  • IS_TIM_GET_IT : stm32f10x_tim.h
  • IS_TIM_IC_FILTER : stm32f10x_tim.h
  • IS_TIM_IC_POLARITY : stm32f10x_tim.h
  • IS_TIM_IC_POLARITY_LITE : stm32f10x_tim.h
  • IS_TIM_IC_PRESCALER : stm32f10x_tim.h
  • IS_TIM_IC_SELECTION : stm32f10x_tim.h
  • IS_TIM_INTERNAL_TRIGGER_SELECTION : stm32f10x_tim.h
  • IS_TIM_IT : stm32f10x_tim.h
  • IS_TIM_LIST1_PERIPH : stm32f10x_tim.h
  • IS_TIM_LIST2_PERIPH : stm32f10x_tim.h
  • IS_TIM_LIST3_PERIPH : stm32f10x_tim.h
  • IS_TIM_LIST4_PERIPH : stm32f10x_tim.h
  • IS_TIM_LIST5_PERIPH : stm32f10x_tim.h
  • IS_TIM_LIST6_PERIPH : stm32f10x_tim.h
  • IS_TIM_LIST7_PERIPH : stm32f10x_tim.h
  • IS_TIM_LIST8_PERIPH : stm32f10x_tim.h
  • IS_TIM_LIST9_PERIPH : stm32f10x_tim.h
  • IS_TIM_LOCK_LEVEL : stm32f10x_tim.h
  • IS_TIM_MSM_STATE : stm32f10x_tim.h
  • IS_TIM_OC_MODE : stm32f10x_tim.h
  • IS_TIM_OC_POLARITY : stm32f10x_tim.h
  • IS_TIM_OCCLEAR_STATE : stm32f10x_tim.h
  • IS_TIM_OCFAST_STATE : stm32f10x_tim.h
  • IS_TIM_OCIDLE_STATE : stm32f10x_tim.h
  • IS_TIM_OCM : stm32f10x_tim.h
  • IS_TIM_OCN_POLARITY : stm32f10x_tim.h
  • IS_TIM_OCNIDLE_STATE : stm32f10x_tim.h
  • IS_TIM_OCPRELOAD_STATE : stm32f10x_tim.h
  • IS_TIM_OPM_MODE : stm32f10x_tim.h
  • IS_TIM_OSSI_STATE : stm32f10x_tim.h
  • IS_TIM_OSSR_STATE : stm32f10x_tim.h
  • IS_TIM_OUTPUT_STATE : stm32f10x_tim.h
  • IS_TIM_OUTPUTN_STATE : stm32f10x_tim.h
  • IS_TIM_PRESCALER_RELOAD : stm32f10x_tim.h
  • IS_TIM_PWMI_CHANNEL : stm32f10x_tim.h
  • IS_TIM_SLAVE_MODE : stm32f10x_tim.h
  • IS_TIM_TIXCLK_SOURCE : stm32f10x_tim.h
  • IS_TIM_TRGO_SOURCE : stm32f10x_tim.h
  • IS_TIM_TRIGGER_SELECTION : stm32f10x_tim.h
  • IS_TIM_UPDATE_SOURCE : stm32f10x_tim.h
  • IS_USART_1234_PERIPH : stm32f10x_usart.h
  • IS_USART_123_PERIPH : stm32f10x_usart.h
  • IS_USART_ADDRESS : stm32f10x_usart.h
  • IS_USART_ALL_PERIPH : stm32f10x_usart.h
  • IS_USART_BAUDRATE : stm32f10x_usart.h
  • IS_USART_CLEAR_FLAG : stm32f10x_usart.h
  • IS_USART_CLEAR_IT : stm32f10x_usart.h
  • IS_USART_CLOCK : stm32f10x_usart.h
  • IS_USART_CONFIG_IT : stm32f10x_usart.h
  • IS_USART_CPHA : stm32f10x_usart.h
  • IS_USART_CPOL : stm32f10x_usart.h
  • IS_USART_DATA : stm32f10x_usart.h
  • IS_USART_DMAREQ : stm32f10x_usart.h
  • IS_USART_FLAG : stm32f10x_usart.h
  • IS_USART_GET_IT : stm32f10x_usart.h
  • IS_USART_HARDWARE_FLOW_CONTROL : stm32f10x_usart.h
  • IS_USART_IRDA_MODE : stm32f10x_usart.h
  • IS_USART_LASTBIT : stm32f10x_usart.h
  • IS_USART_LIN_BREAK_DETECT_LENGTH : stm32f10x_usart.h
  • IS_USART_MODE : stm32f10x_usart.h
  • IS_USART_PARITY : stm32f10x_usart.h
  • IS_USART_PERIPH_FLAG : stm32f10x_usart.h
  • IS_USART_STOPBITS : stm32f10x_usart.h
  • IS_USART_WAKEUP : stm32f10x_usart.h
  • IS_USART_WORD_LENGTH : stm32f10x_usart.h
  • IS_WWDG_COUNTER : stm32f10x_wwdg.h
  • IS_WWDG_PRESCALER : stm32f10x_wwdg.h
  • IS_WWDG_WINDOW_VALUE : stm32f10x_wwdg.h
  • IsBackupRegReset() : STM32F10x_StdPeriph_Examples/BKP/Tamper/main.c , BKP/Tamper/main.h
  • IsCardProgramming() : stm32_eval_sdio_sd.c
  • IT_Mask : stm32f10x_usart.c
  • ITEN_Mask : stm32f10x_i2c.c
  • ITStatus : stm32f10x.h
  • IWDG : stm32f10x.h
  • IWDG_BASE : stm32f10x.h
  • IWDG_DBG : stm32f10x_ip_dbg.c
  • IWDG_Enable() : stm32f10x_iwdg.c , stm32f10x_iwdg.h
  • IWDG_FLAG_PVU : stm32f10x_iwdg.h
  • IWDG_FLAG_RVU : stm32f10x_iwdg.h
  • IWDG_GetFlagStatus() : stm32f10x_iwdg.c , stm32f10x_iwdg.h
  • IWDG_KR_KEY : stm32f10x.h
  • IWDG_PR_PR : stm32f10x.h
  • IWDG_PR_PR_0 : stm32f10x.h
  • IWDG_PR_PR_1 : stm32f10x.h
  • IWDG_PR_PR_2 : stm32f10x.h
  • IWDG_Prescaler_128 : stm32f10x_iwdg.h
  • IWDG_Prescaler_16 : stm32f10x_iwdg.h
  • IWDG_Prescaler_256 : stm32f10x_iwdg.h
  • IWDG_Prescaler_32 : stm32f10x_iwdg.h
  • IWDG_Prescaler_4 : stm32f10x_iwdg.h
  • IWDG_Prescaler_64 : stm32f10x_iwdg.h
  • IWDG_Prescaler_8 : stm32f10x_iwdg.h
  • IWDG_ReloadCounter() : stm32f10x_iwdg.h , stm32f10x_iwdg.c
  • IWDG_RLR_RL : stm32f10x.h
  • IWDG_SetPrescaler() : stm32f10x_iwdg.c , stm32f10x_iwdg.h
  • IWDG_SetReload() : stm32f10x_iwdg.h , stm32f10x_iwdg.c
  • IWDG_SR_PVU : stm32f10x.h
  • IWDG_SR_RVU : stm32f10x.h
  • IWDG_WriteAccess_Disable : stm32f10x_iwdg.h
  • IWDG_WriteAccess_Enable : stm32f10x_iwdg.h
  • IWDG_WriteAccessCmd() : stm32f10x_iwdg.h , stm32f10x_iwdg.c


STM32F10x Standard Peripherals Firmware Library: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- p -

  • PageIndex : STM32F10x_StdPeriph_Examples/FSMC/OneNAND/main.c
  • PageNumber : STM32F10x_StdPeriph_Examples/FSMC/NAND/main.c
  • PARAM_ERROR : stm3210c_eval_ioe.h , stm32100e_eval_ioe.h
  • PASSED : STM32F10x_StdPeriph_Examples/DMA/FSMC/main.c , STM32F10x_StdPeriph_Examples/I2S/Interrupt/main.c , STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/main.c , STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/main.c , STM32F10x_StdPeriph_Examples/SDIO/uSDCard/main.c , STM32F10x_StdPeriph_Examples/SPI/CRC/main.c , STM32F10x_StdPeriph_Examples/CAN/LoopBack/main.c , STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/main.c , STM32F10x_StdPeriph_Examples/SPI/DMA/main.c , STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/main.c , STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/main.c , STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/main.c , STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/main.c , STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/main.c , STM32F10x_StdPeriph_Examples/FLASH/Program/main.c , STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/main.c , STM32F10x_StdPeriph_Examples/USART/DMA_Polling/main.c , STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/main.c , STM32F10x_StdPeriph_Examples/USART/HalfDuplex/main.c , STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c , STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/main.c , STM32F10x_StdPeriph_Examples/I2C/EEPROM/main.c , STM32F10x_StdPeriph_Examples/USART/Polling/main.c , STM32F10x_StdPeriph_Examples/USART/Smartcard/main.c , STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/main.c , STM32F10x_StdPeriph_Examples/USART/Synchronous/main.c
  • PCR_ECCEN_Reset : stm32f10x_fsmc.c
  • PCR_ECCEN_Set : stm32f10x_fsmc.c
  • PCR_MemoryType_NAND : stm32f10x_fsmc.c
  • PCR_PBKEN_Reset : stm32f10x_fsmc.c
  • PCR_PBKEN_Set : stm32f10x_fsmc.c
  • PE_BitNumber : stm32f10x_cec.c
  • PendSV_Handler() : STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CortexM3/MPU/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CortexM3/MPU/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/PWR/PVD/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/PWR/PVD/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/PWR/STANDBY/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/PWR/STANDBY/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/RTC/Calendar/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/RTC/Calendar/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SDIO/uSDCard/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SDIO/uSDCard/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/CRC/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SPI/CRC/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/DMA/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/DMA/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SysTick/TimeBase/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SysTick/TimeBase/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/6Steps/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/FSMC/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/6Steps/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/FSMC/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/DMA/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/DMA/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/DMABurst/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/DMABurst/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/OCActive/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/OCActive/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/OCInactive/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/OCInactive/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FLASH/Program/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/OnePulse/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FLASH/Program/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/OnePulse/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/stm32f10x_it.c , STM32F10x_StdPeriph_Template/stm32f10x_it.h , STM32F10x_StdPeriph_Template/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Synchronous/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Printf/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Printf/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Polling/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Polling/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/MultiProcessor/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/MultiProcessor/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/PWM_Input/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/HalfDuplex/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/HalfDuplex/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/DMA_Polling/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/DMA_Polling/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/PWM_Input/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/PWM_Output/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/NAND/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/PWM_Output/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/NAND/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/NOR/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/BKP/Backup_Data/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/NOR/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/BKP/Backup_Data/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/BKP/Tamper/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/OneNAND/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/BKP/Tamper/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/OneNAND/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/SRAM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/SRAM/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/GPIO/IOToggle/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/GPIO/IOToggle/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Synchronous/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2C/EEPROM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2C/EEPROM/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2C/IOExpander/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2C/IOExpander/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CortexM3/BitBand/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CortexM3/BitBand/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_it.c
  • PendSV_IRQn : stm32f10x.h
  • PeriodValue : STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/main.c
  • PERIPH_ADDRESS_START : CortexM3/MPU/main.h
  • PERIPH_BASE : stm32f10x.h
  • PERIPH_BB_BASE : stm32f10x.h
  • PERIPH_REGION_NUMBER : CortexM3/MPU/main.h
  • PERIPH_SIZE : CortexM3/MPU/main.h
  • pFunction : STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/main.c
  • PhysicalAddressDiscovery() : stm32100b_eval_cec.c , stm32100e_eval_cec.c
  • PLLON_BitNumber : stm32f10x_rcc.c
  • POINT_OFF : stm32l152_eval_glass_lcd.h
  • POINT_ON : stm32l152_eval_glass_lcd.h
  • Point_Typedef : stm32l152_eval_glass_lcd.h
  • Polarity_High : stm3210c_eval_ioe.h , stm32100e_eval_ioe.h
  • Polarity_Low : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • POLY_X : stm3210b_eval_lcd.c , stm3210c_eval_lcd.c , stm3210e_eval_lcd.c , stm32l152_eval_lcd.c , stm32100e_eval_lcd.c , stm32100b_eval_lcd.c
  • POLY_Y : stm32100e_eval_lcd.c , stm3210b_eval_lcd.c , stm3210c_eval_lcd.c , stm3210e_eval_lcd.c , stm32l152_eval_lcd.c , stm32100b_eval_lcd.c
  • portMPU_REGION_PRIVILEGED_READ_ONLY : CortexM3/MPU/main.h
  • portMPU_REGION_PRIVILEGED_READ_WRITE : CortexM3/MPU/main.h
  • portMPU_REGION_READ_ONLY : CortexM3/MPU/main.h
  • portMPU_REGION_READ_WRITE : CortexM3/MPU/main.h
  • pPoint : stm32100b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210b_eval_lcd.h , stm32100e_eval_lcd.h , stm32l152_eval_lcd.h , stm3210e_eval_lcd.h
  • PreemptionOccured : STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/main.c
  • PreemptionPriorityValue : STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/main.c , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_it.c
  • PrescalerValue : STM32F10x_StdPeriph_Examples/TIM/OCInactive/main.c , STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/main.c , STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/main.c , STM32F10x_StdPeriph_Examples/TIM/PWM_Output/main.c , STM32F10x_StdPeriph_Examples/TIM/OnePulse/main.c , STM32F10x_StdPeriph_Examples/TIM/OCActive/main.c , STM32F10x_StdPeriph_Examples/TIM/TimeBase/main.c , STM32F10x_StdPeriph_Examples/TIM/OCToggle/main.c
  • PRLH_MSB_MASK : stm32f10x_rtc.c
  • Program_Timeout : stm3210e_eval_fsmc_nor.c
  • ProgramTimeout : stm32f10x_flash.c
  • ProtectedPages : STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/main.c
  • PSPMemAlloc : STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/main.c
  • PSPValue : STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/main.c
  • PUTCHAR_PROTOTYPE : STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/main.c , STM32F10x_StdPeriph_Examples/RTC/Calendar/main.c , STM32F10x_StdPeriph_Template/main.c , STM32F10x_StdPeriph_Examples/USART/Printf/main.c
  • PutPixel() : stm3210b_eval_lcd.c , stm3210c_eval_lcd.c , stm32100b_eval_lcd.c , stm3210e_eval_lcd.c , stm32l152_eval_lcd.c , stm32100e_eval_lcd.c
  • PVD_IRQHandler() : STM32F10x_StdPeriph_Examples/PWR/PVD/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/PWR/PVD/stm32f10x_it.c
  • PVD_IRQn : stm32f10x.h
  • PVDE_BitNumber : stm32f10x_pwr.c
  • PWR : stm32f10x.h
  • PWR_BackupAccessCmd() : stm32f10x_pwr.h , stm32f10x_pwr.c
  • PWR_BASE : stm32f10x.h
  • PWR_ClearFlag() : stm32f10x_pwr.h , stm32f10x_pwr.c
  • PWR_CR_CSBF : stm32f10x.h
  • PWR_CR_CWUF : stm32f10x.h
  • PWR_CR_DBP : stm32f10x.h
  • PWR_CR_LPDS : stm32f10x.h
  • PWR_CR_PDDS : stm32f10x.h
  • PWR_CR_PLS : stm32f10x.h
  • PWR_CR_PLS_0 : stm32f10x.h
  • PWR_CR_PLS_1 : stm32f10x.h
  • PWR_CR_PLS_2 : stm32f10x.h
  • PWR_CR_PLS_2V2 : stm32f10x.h
  • PWR_CR_PLS_2V3 : stm32f10x.h
  • PWR_CR_PLS_2V4 : stm32f10x.h
  • PWR_CR_PLS_2V5 : stm32f10x.h
  • PWR_CR_PLS_2V6 : stm32f10x.h
  • PWR_CR_PLS_2V7 : stm32f10x.h
  • PWR_CR_PLS_2V8 : stm32f10x.h
  • PWR_CR_PLS_2V9 : stm32f10x.h
  • PWR_CR_PVDE : stm32f10x.h
  • PWR_CSR_EWUP : stm32f10x.h
  • PWR_CSR_PVDO : stm32f10x.h
  • PWR_CSR_SBF : stm32f10x.h
  • PWR_CSR_WUF : stm32f10x.h
  • PWR_DBG : stm32f10x_ip_dbg.c
  • PWR_DeInit() : stm32f10x_pwr.h , stm32f10x_pwr.c
  • PWR_EnterSTANDBYMode() : stm32f10x_pwr.h , stm32f10x_pwr.c
  • PWR_EnterSTOPMode() : stm32f10x_pwr.c , stm32f10x_pwr.h
  • PWR_FLAG_PVDO : stm32f10x_pwr.h
  • PWR_FLAG_SB : stm32f10x_pwr.h
  • PWR_FLAG_WU : stm32f10x_pwr.h
  • PWR_GetFlagStatus() : stm32f10x_pwr.h , stm32f10x_pwr.c
  • PWR_OFFSET : stm32f10x_pwr.c
  • PWR_PVDCmd() : stm32f10x_pwr.h , stm32f10x_pwr.c
  • PWR_PVDLevel_2V2 : stm32f10x_pwr.h
  • PWR_PVDLevel_2V3 : stm32f10x_pwr.h
  • PWR_PVDLevel_2V4 : stm32f10x_pwr.h
  • PWR_PVDLevel_2V5 : stm32f10x_pwr.h
  • PWR_PVDLevel_2V6 : stm32f10x_pwr.h
  • PWR_PVDLevel_2V7 : stm32f10x_pwr.h
  • PWR_PVDLevel_2V8 : stm32f10x_pwr.h
  • PWR_PVDLevel_2V9 : stm32f10x_pwr.h
  • PWR_PVDLevelConfig() : stm32f10x_pwr.h , stm32f10x_pwr.c
  • PWR_PWRCTRL_MASK : stm32f10x_sdio.c
  • PWR_Regulator_LowPower : stm32f10x_pwr.h
  • PWR_Regulator_ON : stm32f10x_pwr.h
  • PWR_STOPEntry_WFE : stm32f10x_pwr.h
  • PWR_STOPEntry_WFI : stm32f10x_pwr.h
  • PWR_WakeUpPinCmd() : stm32f10x_pwr.h , stm32f10x_pwr.c


STM32F10x Standard Peripherals Firmware Library: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
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  • f
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  • h
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  • k
  • l
  • m
  • n
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  • s
  • t
  • u
  • v
  • w
  • y
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- r -

  • R0 : stm32_eval.h
  • R1 : stm32_eval.h
  • R10 : stm32_eval.h
  • R106 : stm32_eval.h
  • R118 : stm32_eval.h
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  • R140 : stm32_eval.h
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  • R144 : stm32_eval.h
  • R145 : stm32_eval.h
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  • R157 : stm32_eval.h
  • R16 : stm32_eval.h
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  • R18 : stm32_eval.h
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  • R192 : stm32_eval.h
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  • R2 : stm32_eval.h
  • R20 : stm32_eval.h
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  • R227 : stm32_eval.h
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  • R231 : stm32_eval.h
  • R239 : stm32_eval.h
  • R24 : stm32_eval.h
  • R25 : stm32_eval.h
  • R26 : stm32_eval.h
  • R27 : stm32_eval.h
  • R28 : stm32_eval.h
  • R29 : stm32_eval.h
  • R3 : stm32_eval.h
  • R30 : stm32_eval.h
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  • R32 : stm32_eval.h
  • R33 : stm32_eval.h
  • R34 : stm32_eval.h
  • R36 : stm32_eval.h
  • R37 : stm32_eval.h
  • R4 : stm32_eval.h
  • R40 : stm32_eval.h
  • R41 : stm32_eval.h
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  • R45 : stm32_eval.h
  • R48 : stm32_eval.h
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  • R5 : stm32_eval.h
  • R50 : stm32_eval.h
  • R51 : stm32_eval.h
  • R52 : stm32_eval.h
  • R53 : stm32_eval.h
  • R54 : stm32_eval.h
  • R55 : stm32_eval.h
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  • R59 : stm32_eval.h
  • R6 : stm32_eval.h
  • R60 : stm32_eval.h
  • R61 : stm32_eval.h
  • R62 : stm32_eval.h
  • R63 : stm32_eval.h
  • R64 : stm32_eval.h
  • R65 : stm32_eval.h
  • R66 : stm32_eval.h
  • R67 : stm32_eval.h
  • R68 : stm32_eval.h
  • R69 : stm32_eval.h
  • R7 : stm32_eval.h
  • R70 : stm32_eval.h
  • R71 : stm32_eval.h
  • R72 : stm32_eval.h
  • R73 : stm32_eval.h
  • R74 : stm32_eval.h
  • R75 : stm32_eval.h
  • R76 : stm32_eval.h
  • R77 : stm32_eval.h
  • R78 : stm32_eval.h
  • R79 : stm32_eval.h
  • R8 : stm32_eval.h
  • R80 : stm32_eval.h
  • R81 : stm32_eval.h
  • R82 : stm32_eval.h
  • R83 : stm32_eval.h
  • R9 : stm32_eval.h
  • R96 : stm32_eval.h
  • R97 : stm32_eval.h
  • RAM_ADDRESS_START : CortexM3/MPU/main.h
  • RAM_BASE : STM32F10x_StdPeriph_Examples/CortexM3/BitBand/main.c
  • RAM_BB_BASE : STM32F10x_StdPeriph_Examples/CortexM3/BitBand/main.c
  • RAM_REGION_NUMBER : CortexM3/MPU/main.h
  • RAM_SIZE : CortexM3/MPU/main.h
  • RCA : stm32_eval_sdio_sd.c
  • RCC : stm32f10x.h
  • RCC_ADCCLKConfig() : stm32f10x_rcc.h , stm32f10x_rcc.c
  • RCC_AdjustHSICalibrationValue() : stm32f10x_rcc.h , stm32f10x_rcc.c
  • RCC_AHBENR_CRCEN : stm32f10x.h
  • RCC_AHBENR_DMA1EN : stm32f10x.h
  • RCC_AHBENR_FLITFEN : stm32f10x.h
  • RCC_AHBENR_SRAMEN : stm32f10x.h
  • RCC_AHBPeriph_CRC : stm32f10x_rcc.h
  • RCC_AHBPeriph_DMA1 : stm32f10x_rcc.h
  • RCC_AHBPeriph_DMA2 : stm32f10x_rcc.h
  • RCC_AHBPeriph_FLITF : stm32f10x_rcc.h
  • RCC_AHBPeriph_FSMC : stm32f10x_rcc.h
  • RCC_AHBPeriph_SDIO : stm32f10x_rcc.h
  • RCC_AHBPeriph_SRAM : stm32f10x_rcc.h
  • RCC_AHBPeriphClockCmd() : stm32f10x_rcc.h , stm32f10x_rcc.c
  • RCC_APB1ENR_BKPEN : stm32f10x.h
  • RCC_APB1ENR_CAN1EN : stm32f10x.h
  • RCC_APB1ENR_I2C1EN : stm32f10x.h
  • RCC_APB1ENR_I2C2EN : stm32f10x.h
  • RCC_APB1ENR_PWREN : stm32f10x.h
  • RCC_APB1ENR_SPI2EN : stm32f10x.h
  • RCC_APB1ENR_TIM2EN : stm32f10x.h
  • RCC_APB1ENR_TIM3EN : stm32f10x.h
  • RCC_APB1ENR_TIM4EN : stm32f10x.h
  • RCC_APB1ENR_USART2EN : stm32f10x.h
  • RCC_APB1ENR_USART3EN : stm32f10x.h
  • RCC_APB1ENR_WWDGEN : stm32f10x.h
  • RCC_APB1Periph_BKP : stm32f10x_rcc.h
  • RCC_APB1Periph_CAN1 : stm32f10x_rcc.h
  • RCC_APB1Periph_CAN2 : stm32f10x_rcc.h
  • RCC_APB1Periph_CEC : stm32f10x_rcc.h
  • RCC_APB1Periph_DAC : stm32f10x_rcc.h
  • RCC_APB1Periph_I2C1 : stm32f10x_rcc.h
  • RCC_APB1Periph_I2C2 : stm32f10x_rcc.h
  • RCC_APB1Periph_PWR : stm32f10x_rcc.h
  • RCC_APB1Periph_SPI2 : stm32f10x_rcc.h
  • RCC_APB1Periph_SPI3 : stm32f10x_rcc.h
  • RCC_APB1Periph_TIM12 : stm32f10x_rcc.h
  • RCC_APB1Periph_TIM13 : stm32f10x_rcc.h
  • RCC_APB1Periph_TIM14 : stm32f10x_rcc.h
  • RCC_APB1Periph_TIM2 : stm32f10x_rcc.h
  • RCC_APB1Periph_TIM3 : stm32f10x_rcc.h
  • RCC_APB1Periph_TIM4 : stm32f10x_rcc.h
  • RCC_APB1Periph_TIM5 : stm32f10x_rcc.h
  • RCC_APB1Periph_TIM6 : stm32f10x_rcc.h
  • RCC_APB1Periph_TIM7 : stm32f10x_rcc.h
  • RCC_APB1Periph_UART4 : stm32f10x_rcc.h
  • RCC_APB1Periph_UART5 : stm32f10x_rcc.h
  • RCC_APB1Periph_USART2 : stm32f10x_rcc.h
  • RCC_APB1Periph_USART3 : stm32f10x_rcc.h
  • RCC_APB1Periph_USB : stm32f10x_rcc.h
  • RCC_APB1Periph_WWDG : stm32f10x_rcc.h
  • RCC_APB1PeriphClockCmd() : stm32f10x_rcc.h , stm32f10x_rcc.c
  • RCC_APB1PeriphResetCmd() : stm32f10x_rcc.h , stm32f10x_rcc.c
  • RCC_APB1RSTR_BKPRST : stm32f10x.h
  • RCC_APB1RSTR_CAN1RST : stm32f10x.h
  • RCC_APB1RSTR_I2C1RST : stm32f10x.h
  • RCC_APB1RSTR_I2C2RST : stm32f10x.h
  • RCC_APB1RSTR_PWRRST : stm32f10x.h
  • RCC_APB1RSTR_SPI2RST : stm32f10x.h
  • RCC_APB1RSTR_TIM2RST : stm32f10x.h
  • RCC_APB1RSTR_TIM3RST : stm32f10x.h
  • RCC_APB1RSTR_TIM4RST : stm32f10x.h
  • RCC_APB1RSTR_USART2RST : stm32f10x.h
  • RCC_APB1RSTR_USART3RST : stm32f10x.h
  • RCC_APB1RSTR_WWDGRST : stm32f10x.h
  • RCC_APB2ENR_ADC1EN : stm32f10x.h
  • RCC_APB2ENR_ADC2EN : stm32f10x.h
  • RCC_APB2ENR_AFIOEN : stm32f10x.h
  • RCC_APB2ENR_IOPAEN : stm32f10x.h
  • RCC_APB2ENR_IOPBEN : stm32f10x.h
  • RCC_APB2ENR_IOPCEN : stm32f10x.h
  • RCC_APB2ENR_IOPDEN : stm32f10x.h
  • RCC_APB2ENR_IOPEEN : stm32f10x.h
  • RCC_APB2ENR_SPI1EN : stm32f10x.h
  • RCC_APB2ENR_TIM1EN : stm32f10x.h
  • RCC_APB2ENR_USART1EN : stm32f10x.h
  • RCC_APB2Periph_ADC1 : stm32f10x_rcc.h
  • RCC_APB2Periph_ADC2 : stm32f10x_rcc.h
  • RCC_APB2Periph_ADC3 : stm32f10x_rcc.h
  • RCC_APB2Periph_AFIO : stm32f10x_rcc.h
  • RCC_APB2Periph_GPIO_CAN1 : CAN/Networking/platform_config.h
  • RCC_APB2Periph_GPIO_CAN2 : CAN/Networking/platform_config.h
  • RCC_APB2Periph_GPIOA : stm32f10x_rcc.h
  • RCC_APB2Periph_GPIOB : stm32f10x_rcc.h
  • RCC_APB2Periph_GPIOC : stm32f10x_rcc.h
  • RCC_APB2Periph_GPIOD : stm32f10x_rcc.h
  • RCC_APB2Periph_GPIOE : stm32f10x_rcc.h
  • RCC_APB2Periph_GPIOF : stm32f10x_rcc.h
  • RCC_APB2Periph_GPIOG : stm32f10x_rcc.h
  • RCC_APB2Periph_GPIOx : USART/HyperTerminal_HwFlowControl/platform_config.h
  • RCC_APB2Periph_SPI1 : stm32f10x_rcc.h
  • RCC_APB2Periph_TIM1 : stm32f10x_rcc.h
  • RCC_APB2Periph_TIM10 : stm32f10x_rcc.h
  • RCC_APB2Periph_TIM11 : stm32f10x_rcc.h
  • RCC_APB2Periph_TIM15 : stm32f10x_rcc.h
  • RCC_APB2Periph_TIM16 : stm32f10x_rcc.h
  • RCC_APB2Periph_TIM17 : stm32f10x_rcc.h
  • RCC_APB2Periph_TIM8 : stm32f10x_rcc.h
  • RCC_APB2Periph_TIM9 : stm32f10x_rcc.h
  • RCC_APB2Periph_USART1 : stm32f10x_rcc.h
  • RCC_APB2PeriphClockCmd() : stm32f10x_rcc.h , stm32f10x_rcc.c
  • RCC_APB2PeriphResetCmd() : stm32f10x_rcc.h , stm32f10x_rcc.c
  • RCC_APB2RSTR_ADC1RST : stm32f10x.h
  • RCC_APB2RSTR_ADC2RST : stm32f10x.h
  • RCC_APB2RSTR_AFIORST : stm32f10x.h
  • RCC_APB2RSTR_IOPARST : stm32f10x.h
  • RCC_APB2RSTR_IOPBRST : stm32f10x.h
  • RCC_APB2RSTR_IOPCRST : stm32f10x.h
  • RCC_APB2RSTR_IOPDRST : stm32f10x.h
  • RCC_APB2RSTR_IOPERST : stm32f10x.h
  • RCC_APB2RSTR_SPI1RST : stm32f10x.h
  • RCC_APB2RSTR_TIM1RST : stm32f10x.h
  • RCC_APB2RSTR_USART1RST : stm32f10x.h
  • RCC_BackupResetCmd() : stm32f10x_rcc.h , stm32f10x_rcc.c
  • RCC_BASE : stm32f10x.h
  • RCC_BDCR_BDRST : stm32f10x.h
  • RCC_BDCR_LSEBYP : stm32f10x.h
  • RCC_BDCR_LSEON : stm32f10x.h
  • RCC_BDCR_LSERDY : stm32f10x.h
  • RCC_BDCR_RTCEN : stm32f10x.h
  • RCC_BDCR_RTCSEL : stm32f10x.h
  • RCC_BDCR_RTCSEL_0 : stm32f10x.h
  • RCC_BDCR_RTCSEL_1 : stm32f10x.h
  • RCC_BDCR_RTCSEL_HSE : stm32f10x.h
  • RCC_BDCR_RTCSEL_LSE : stm32f10x.h
  • RCC_BDCR_RTCSEL_LSI : stm32f10x.h
  • RCC_BDCR_RTCSEL_NOCLOCK : stm32f10x.h
  • RCC_CFGR_ADCPRE : stm32f10x.h
  • RCC_CFGR_ADCPRE_0 : stm32f10x.h
  • RCC_CFGR_ADCPRE_1 : stm32f10x.h
  • RCC_CFGR_ADCPRE_DIV2 : stm32f10x.h
  • RCC_CFGR_ADCPRE_DIV4 : stm32f10x.h
  • RCC_CFGR_ADCPRE_DIV6 : stm32f10x.h
  • RCC_CFGR_ADCPRE_DIV8 : stm32f10x.h
  • RCC_CFGR_HPRE : stm32f10x.h
  • RCC_CFGR_HPRE_0 : stm32f10x.h
  • RCC_CFGR_HPRE_1 : stm32f10x.h
  • RCC_CFGR_HPRE_2 : stm32f10x.h
  • RCC_CFGR_HPRE_3 : stm32f10x.h
  • RCC_CFGR_HPRE_DIV1 : stm32f10x.h
  • RCC_CFGR_HPRE_DIV128 : stm32f10x.h
  • RCC_CFGR_HPRE_DIV16 : stm32f10x.h
  • RCC_CFGR_HPRE_DIV2 : stm32f10x.h
  • RCC_CFGR_HPRE_DIV256 : stm32f10x.h
  • RCC_CFGR_HPRE_DIV4 : stm32f10x.h
  • RCC_CFGR_HPRE_DIV512 : stm32f10x.h
  • RCC_CFGR_HPRE_DIV64 : stm32f10x.h
  • RCC_CFGR_HPRE_DIV8 : stm32f10x.h
  • RCC_CFGR_MCO : stm32f10x.h
  • RCC_CFGR_MCO_0 : stm32f10x.h
  • RCC_CFGR_MCO_1 : stm32f10x.h
  • RCC_CFGR_MCO_2 : stm32f10x.h
  • RCC_CFGR_MCO_HSE : stm32f10x.h
  • RCC_CFGR_MCO_HSI : stm32f10x.h
  • RCC_CFGR_MCO_NOCLOCK : stm32f10x.h
  • RCC_CFGR_MCO_PLL : stm32f10x.h
  • RCC_CFGR_MCO_SYSCLK : stm32f10x.h
  • RCC_CFGR_PLLMULL : stm32f10x.h
  • RCC_CFGR_PLLMULL10 : stm32f10x.h
  • RCC_CFGR_PLLMULL11 : stm32f10x.h
  • RCC_CFGR_PLLMULL12 : stm32f10x.h
  • RCC_CFGR_PLLMULL13 : stm32f10x.h
  • RCC_CFGR_PLLMULL14 : stm32f10x.h
  • RCC_CFGR_PLLMULL15 : stm32f10x.h
  • RCC_CFGR_PLLMULL16 : stm32f10x.h
  • RCC_CFGR_PLLMULL2 : stm32f10x.h
  • RCC_CFGR_PLLMULL3 : stm32f10x.h
  • RCC_CFGR_PLLMULL4 : stm32f10x.h
  • RCC_CFGR_PLLMULL5 : stm32f10x.h
  • RCC_CFGR_PLLMULL6 : stm32f10x.h
  • RCC_CFGR_PLLMULL7 : stm32f10x.h
  • RCC_CFGR_PLLMULL8 : stm32f10x.h
  • RCC_CFGR_PLLMULL9 : stm32f10x.h
  • RCC_CFGR_PLLMULL_0 : stm32f10x.h
  • RCC_CFGR_PLLMULL_1 : stm32f10x.h
  • RCC_CFGR_PLLMULL_2 : stm32f10x.h
  • RCC_CFGR_PLLMULL_3 : stm32f10x.h
  • RCC_CFGR_PLLSRC : stm32f10x.h
  • RCC_CFGR_PLLSRC_HSE : stm32f10x.h
  • RCC_CFGR_PLLSRC_HSI_Div2 : stm32f10x.h
  • RCC_CFGR_PLLXTPRE : stm32f10x.h
  • RCC_CFGR_PLLXTPRE_HSE : stm32f10x.h
  • RCC_CFGR_PLLXTPRE_HSE_Div2 : stm32f10x.h
  • RCC_CFGR_PPRE1 : stm32f10x.h
  • RCC_CFGR_PPRE1_0 : stm32f10x.h
  • RCC_CFGR_PPRE1_1 : stm32f10x.h
  • RCC_CFGR_PPRE1_2 : stm32f10x.h
  • RCC_CFGR_PPRE1_DIV1 : stm32f10x.h
  • RCC_CFGR_PPRE1_DIV16 : stm32f10x.h
  • RCC_CFGR_PPRE1_DIV2 : stm32f10x.h
  • RCC_CFGR_PPRE1_DIV4 : stm32f10x.h
  • RCC_CFGR_PPRE1_DIV8 : stm32f10x.h
  • RCC_CFGR_PPRE2 : stm32f10x.h
  • RCC_CFGR_PPRE2_0 : stm32f10x.h
  • RCC_CFGR_PPRE2_1 : stm32f10x.h
  • RCC_CFGR_PPRE2_2 : stm32f10x.h
  • RCC_CFGR_PPRE2_DIV1 : stm32f10x.h
  • RCC_CFGR_PPRE2_DIV16 : stm32f10x.h
  • RCC_CFGR_PPRE2_DIV2 : stm32f10x.h
  • RCC_CFGR_PPRE2_DIV4 : stm32f10x.h
  • RCC_CFGR_PPRE2_DIV8 : stm32f10x.h
  • RCC_CFGR_SW : stm32f10x.h
  • RCC_CFGR_SW_0 : stm32f10x.h
  • RCC_CFGR_SW_1 : stm32f10x.h
  • RCC_CFGR_SW_HSE : stm32f10x.h
  • RCC_CFGR_SW_HSI : stm32f10x.h
  • RCC_CFGR_SW_PLL : stm32f10x.h
  • RCC_CFGR_SWS : stm32f10x.h
  • RCC_CFGR_SWS_0 : stm32f10x.h
  • RCC_CFGR_SWS_1 : stm32f10x.h
  • RCC_CFGR_SWS_HSE : stm32f10x.h
  • RCC_CFGR_SWS_HSI : stm32f10x.h
  • RCC_CFGR_SWS_PLL : stm32f10x.h
  • RCC_CFGR_USBPRE : stm32f10x.h
  • RCC_CIR_CSSC : stm32f10x.h
  • RCC_CIR_CSSF : stm32f10x.h
  • RCC_CIR_HSERDYC : stm32f10x.h
  • RCC_CIR_HSERDYF : stm32f10x.h
  • RCC_CIR_HSERDYIE : stm32f10x.h
  • RCC_CIR_HSIRDYC : stm32f10x.h
  • RCC_CIR_HSIRDYF : stm32f10x.h
  • RCC_CIR_HSIRDYIE : stm32f10x.h
  • RCC_CIR_LSERDYC : stm32f10x.h
  • RCC_CIR_LSERDYF : stm32f10x.h
  • RCC_CIR_LSERDYIE : stm32f10x.h
  • RCC_CIR_LSIRDYC : stm32f10x.h
  • RCC_CIR_LSIRDYF : stm32f10x.h
  • RCC_CIR_LSIRDYIE : stm32f10x.h
  • RCC_CIR_PLLRDYC : stm32f10x.h
  • RCC_CIR_PLLRDYF : stm32f10x.h
  • RCC_CIR_PLLRDYIE : stm32f10x.h
  • RCC_ClearFlag() : stm32f10x_rcc.h , stm32f10x_rcc.c
  • RCC_ClearITPendingBit() : stm32f10x_rcc.h , stm32f10x_rcc.c
  • RCC_ClockFreq : STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/main.c
  • RCC_Clocks : STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/main.c , STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/main.c
  • RCC_ClockSecuritySystemCmd() : stm32f10x_rcc.h , stm32f10x_rcc.c
  • RCC_Configuration() : STM32F10x_StdPeriph_Examples/FSMC/NOR/main.c , STM32F10x_StdPeriph_Examples/USART/DMA_Polling/main.c , STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/main.c , STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/main.c , STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/main.c , STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/main.c , STM32F10x_StdPeriph_Examples/TIM/OCActive/main.c , STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/main.c , STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/main.c , STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c , STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/main.c , STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/main.c , STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/main.c , STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/main.c , STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/main.c , STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/main.c , STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/main.c , STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/main.c , STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/main.c , STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/main.c , STM32F10x_StdPeriph_Examples/DMA/FSMC/main.c , STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/main.c , STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/main.c , STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/main.c , STM32F10x_StdPeriph_Examples/I2S/Interrupt/main.c , STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/main.c , STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/main.c , STM32F10x_StdPeriph_Examples/SPI/CRC/main.c , STM32F10x_StdPeriph_Examples/SPI/DMA/main.c , STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/main.c , STM32F10x_StdPeriph_Examples/TIM/6Steps/main.c , STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/main.c , STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/main.c , STM32F10x_StdPeriph_Examples/TIM/DMA/main.c , STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/main.c , STM32F10x_StdPeriph_Examples/TIM/InputCapture/main.c , STM32F10x_StdPeriph_Examples/TIM/OCInactive/main.c , STM32F10x_StdPeriph_Examples/TIM/OCToggle/main.c , STM32F10x_StdPeriph_Examples/TIM/OnePulse/main.c , STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/main.c , STM32F10x_StdPeriph_Examples/TIM/PWM_Input/main.c , STM32F10x_StdPeriph_Examples/TIM/PWM_Output/main.c , STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/main.c , STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/main.c , STM32F10x_StdPeriph_Examples/TIM/TimeBase/main.c , STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/main.c , STM32F10x_StdPeriph_Examples/USART/HalfDuplex/main.c , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/main.c , STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c , STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/main.c , STM32F10x_StdPeriph_Examples/USART/MultiProcessor/main.c , STM32F10x_StdPeriph_Examples/USART/Polling/main.c , STM32F10x_StdPeriph_Examples/USART/Smartcard/main.c , STM32F10x_StdPeriph_Examples/USART/Synchronous/main.c
  • RCC_CR_CSSON : stm32f10x.h
  • RCC_CR_HSEBYP : stm32f10x.h
  • RCC_CR_HSEON : stm32f10x.h
  • RCC_CR_HSERDY : stm32f10x.h
  • RCC_CR_HSICAL : stm32f10x.h
  • RCC_CR_HSION : stm32f10x.h
  • RCC_CR_HSIRDY : stm32f10x.h
  • RCC_CR_HSITRIM : stm32f10x.h
  • RCC_CR_PLLON : stm32f10x.h
  • RCC_CR_PLLRDY : stm32f10x.h
  • RCC_CSR_IWDGRSTF : stm32f10x.h
  • RCC_CSR_LPWRRSTF : stm32f10x.h
  • RCC_CSR_LSION : stm32f10x.h
  • RCC_CSR_LSIRDY : stm32f10x.h
  • RCC_CSR_PINRSTF : stm32f10x.h
  • RCC_CSR_PORRSTF : stm32f10x.h
  • RCC_CSR_RMVF : stm32f10x.h
  • RCC_CSR_SFTRSTF : stm32f10x.h
  • RCC_CSR_WWDGRSTF : stm32f10x.h
  • RCC_DBG : stm32f10x_ip_dbg.c
  • RCC_DeInit() : stm32f10x_rcc.h , stm32f10x_rcc.c
  • RCC_FLAG_HSERDY : stm32f10x_rcc.h
  • RCC_FLAG_HSIRDY : stm32f10x_rcc.h
  • RCC_FLAG_IWDGRST : stm32f10x_rcc.h
  • RCC_FLAG_LPWRRST : stm32f10x_rcc.h
  • RCC_FLAG_LSERDY : stm32f10x_rcc.h
  • RCC_FLAG_LSIRDY : stm32f10x_rcc.h
  • RCC_FLAG_PINRST : stm32f10x_rcc.h
  • RCC_FLAG_PLLRDY : stm32f10x_rcc.h
  • RCC_FLAG_PORRST : stm32f10x_rcc.h
  • RCC_FLAG_SFTRST : stm32f10x_rcc.h
  • RCC_FLAG_WWDGRST : stm32f10x_rcc.h
  • RCC_GetClocksFreq() : stm32f10x_rcc.c , stm32f10x_rcc.h
  • RCC_GetFlagStatus() : stm32f10x_rcc.h , stm32f10x_rcc.c
  • RCC_GetITStatus() : stm32f10x_rcc.c , stm32f10x_rcc.h
  • RCC_GetSYSCLKSource() : stm32f10x_rcc.h , stm32f10x_rcc.c
  • RCC_HCLK_Div1 : stm32f10x_rcc.h
  • RCC_HCLK_Div16 : stm32f10x_rcc.h
  • RCC_HCLK_Div2 : stm32f10x_rcc.h
  • RCC_HCLK_Div4 : stm32f10x_rcc.h
  • RCC_HCLK_Div8 : stm32f10x_rcc.h
  • RCC_HCLKConfig() : stm32f10x_rcc.h , stm32f10x_rcc.c
  • RCC_HSE_Bypass : stm32f10x_rcc.h
  • RCC_HSE_OFF : stm32f10x_rcc.h
  • RCC_HSE_ON : stm32f10x_rcc.h
  • RCC_HSEConfig() : stm32f10x_rcc.h , stm32f10x_rcc.c
  • RCC_HSICmd() : stm32f10x_rcc.c , stm32f10x_rcc.h
  • RCC_IRQHandler() : STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/stm32f10x_it.h
  • RCC_IRQn : stm32f10x.h
  • RCC_IT_CSS : stm32f10x_rcc.h
  • RCC_IT_HSERDY : stm32f10x_rcc.h
  • RCC_IT_HSIRDY : stm32f10x_rcc.h
  • RCC_IT_LSERDY : stm32f10x_rcc.h
  • RCC_IT_LSIRDY : stm32f10x_rcc.h
  • RCC_IT_PLLRDY : stm32f10x_rcc.h
  • RCC_ITConfig() : stm32f10x_rcc.h , stm32f10x_rcc.c
  • RCC_LSE_Bypass : stm32f10x_rcc.h
  • RCC_LSE_OFF : stm32f10x_rcc.h
  • RCC_LSE_ON : stm32f10x_rcc.h
  • RCC_LSEConfig() : stm32f10x_rcc.c , stm32f10x_rcc.h
  • RCC_LSICmd() : stm32f10x_rcc.h , stm32f10x_rcc.c
  • RCC_MCO_HSE : stm32f10x_rcc.h
  • RCC_MCO_HSI : stm32f10x_rcc.h
  • RCC_MCO_NoClock : stm32f10x_rcc.h
  • RCC_MCO_PLLCLK_Div2 : stm32f10x_rcc.h
  • RCC_MCO_SYSCLK : stm32f10x_rcc.h
  • RCC_MCOConfig() : stm32f10x_rcc.c , stm32f10x_rcc.h
  • RCC_OFFSET : stm32f10x_rcc.c
  • RCC_PCLK1Config() : stm32f10x_rcc.c , stm32f10x_rcc.h
  • RCC_PCLK2_Div2 : stm32f10x_rcc.h
  • RCC_PCLK2_Div4 : stm32f10x_rcc.h
  • RCC_PCLK2_Div6 : stm32f10x_rcc.h
  • RCC_PCLK2_Div8 : stm32f10x_rcc.h
  • RCC_PCLK2Config() : stm32f10x_rcc.c , stm32f10x_rcc.h
  • RCC_PLLCmd() : stm32f10x_rcc.h , stm32f10x_rcc.c
  • RCC_PLLConfig() : stm32f10x_rcc.h , stm32f10x_rcc.c
  • RCC_PLLMul_10 : stm32f10x_rcc.h
  • RCC_PLLMul_11 : stm32f10x_rcc.h
  • RCC_PLLMul_12 : stm32f10x_rcc.h
  • RCC_PLLMul_13 : stm32f10x_rcc.h
  • RCC_PLLMul_14 : stm32f10x_rcc.h
  • RCC_PLLMul_15 : stm32f10x_rcc.h
  • RCC_PLLMul_16 : stm32f10x_rcc.h
  • RCC_PLLMul_2 : stm32f10x_rcc.h
  • RCC_PLLMul_3 : stm32f10x_rcc.h
  • RCC_PLLMul_4 : stm32f10x_rcc.h
  • RCC_PLLMul_5 : stm32f10x_rcc.h
  • RCC_PLLMul_6 : stm32f10x_rcc.h
  • RCC_PLLMul_7 : stm32f10x_rcc.h
  • RCC_PLLMul_8 : stm32f10x_rcc.h
  • RCC_PLLMul_9 : stm32f10x_rcc.h
  • RCC_PLLSource_HSE_Div1 : stm32f10x_rcc.h
  • RCC_PLLSource_HSE_Div2 : stm32f10x_rcc.h
  • RCC_PLLSource_HSI_Div2 : stm32f10x_rcc.h
  • RCC_RTCCLKCmd() : stm32f10x_rcc.h , stm32f10x_rcc.c
  • RCC_RTCCLKConfig() : stm32f10x_rcc.h , stm32f10x_rcc.c
  • RCC_RTCCLKSource_HSE_Div128 : stm32f10x_rcc.h
  • RCC_RTCCLKSource_LSE : stm32f10x_rcc.h
  • RCC_RTCCLKSource_LSI : stm32f10x_rcc.h
  • RCC_SYSCLK_Div1 : stm32f10x_rcc.h
  • RCC_SYSCLK_Div128 : stm32f10x_rcc.h
  • RCC_SYSCLK_Div16 : stm32f10x_rcc.h
  • RCC_SYSCLK_Div2 : stm32f10x_rcc.h
  • RCC_SYSCLK_Div256 : stm32f10x_rcc.h
  • RCC_SYSCLK_Div4 : stm32f10x_rcc.h
  • RCC_SYSCLK_Div512 : stm32f10x_rcc.h
  • RCC_SYSCLK_Div64 : stm32f10x_rcc.h
  • RCC_SYSCLK_Div8 : stm32f10x_rcc.h
  • RCC_SYSCLKConfig() : stm32f10x_rcc.h , stm32f10x_rcc.c
  • RCC_SYSCLKSource_HSE : stm32f10x_rcc.h
  • RCC_SYSCLKSource_HSI : stm32f10x_rcc.h
  • RCC_SYSCLKSource_PLLCLK : stm32f10x_rcc.h
  • RCC_USBCLKConfig() : stm32f10x_rcc.c , stm32f10x_rcc.h
  • RCC_USBCLKSource_PLLCLK_1Div5 : stm32f10x_rcc.h
  • RCC_USBCLKSource_PLLCLK_Div1 : stm32f10x_rcc.h
  • RCC_WaitForHSEStartUp() : stm32f10x_rcc.h , stm32f10x_rcc.c
  • rcv_inc : STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.c
  • RDP_Key : stm32f10x_flash.c
  • RDPRT_Mask : stm32f10x_flash.c
  • READ_BIT : stm32f10x.h
  • READ_REG : stm32f10x.h
  • READ_STATUS : stm32100b_eval_lcd.c , stm3210b_eval_lcd.c , stm32l152_eval_lcd.c , stm3210c_eval_lcd.c
  • ReadKey() : STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/main.c
  • ReceiveBuffer : STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/main.c
  • ReceivedData : STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/main.c
  • ReceivedFrame : STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/main.c , stm32100e_eval_cec.c , stm32100b_eval_cec.c , STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.c
  • ReceiveStatus : stm32100b_eval_cec.c , stm32100e_eval_cec.c
  • RecepErrorCode : STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.c , stm32100e_eval_cec.c , stm32100b_eval_cec.c
  • Red : stm32_eval.h
  • RESET : stm32f10x.h
  • ret : STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CAN/LoopBack/main.c
  • RIGHT_BUTTON_EXTI_IRQn : stm32100e_eval.h , stm3210e_eval.h , stm3210b_eval.h , stm32l152_eval.h , stm32100b_eval.h
  • RIGHT_BUTTON_EXTI_LINE : stm3210b_eval.h , stm3210e_eval.h , stm32100e_eval.h , stm32100b_eval.h , stm32l152_eval.h
  • RIGHT_BUTTON_EXTI_PIN_SOURCE : stm32100e_eval.h , stm32l152_eval.h , stm32100b_eval.h , stm3210e_eval.h , stm3210b_eval.h
  • RIGHT_BUTTON_EXTI_PORT_SOURCE : stm32100b_eval.h , stm3210b_eval.h , stm32l152_eval.h , stm32100e_eval.h , stm3210e_eval.h
  • RIGHT_BUTTON_GPIO_CLK : stm3210e_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm32100b_eval.h , stm32l152_eval.h
  • RIGHT_BUTTON_GPIO_PORT : stm3210e_eval.h , stm32100b_eval.h , stm32100e_eval.h , stm32l152_eval.h , stm3210b_eval.h
  • RIGHT_BUTTON_PIN : stm32100e_eval.h , stm3210b_eval.h , stm32100b_eval.h , stm32l152_eval.h , stm3210e_eval.h
  • ROW_ADDRESS : stm3210e_eval_fsmc_nand.c
  • RTC : stm32f10x.h
  • RTC_ALRH_RTC_ALR : stm32f10x.h
  • RTC_ALRL_RTC_ALR : stm32f10x.h
  • RTC_BASE : stm32f10x.h
  • RTC_ClearFlag() : stm32f10x_rtc.c , stm32f10x_rtc.h
  • RTC_ClearITPendingBit() : stm32f10x_rtc.c , stm32f10x_rtc.h
  • RTC_CNTH_RTC_CNT : stm32f10x.h
  • RTC_CNTL_RTC_CNT : stm32f10x.h
  • RTC_Configuration() : STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/main.c , STM32F10x_StdPeriph_Examples/PWR/STOP/main.c , STM32F10x_StdPeriph_Examples/PWR/STANDBY/main.c , STM32F10x_StdPeriph_Examples/RTC/Calendar/main.c
  • RTC_CRH_ALRIE : stm32f10x.h
  • RTC_CRH_OWIE : stm32f10x.h
  • RTC_CRH_SECIE : stm32f10x.h
  • RTC_CRL_ALRF : stm32f10x.h
  • RTC_CRL_CNF : stm32f10x.h
  • RTC_CRL_OWF : stm32f10x.h
  • RTC_CRL_RSF : stm32f10x.h
  • RTC_CRL_RTOFF : stm32f10x.h
  • RTC_CRL_SECF : stm32f10x.h
  • RTC_DBG : stm32f10x_ip_dbg.c
  • RTC_DIVH_RTC_DIV : stm32f10x.h
  • RTC_DIVL_RTC_DIV : stm32f10x.h
  • RTC_EnterConfigMode() : stm32f10x_rtc.c , stm32f10x_rtc.h
  • RTC_ExitConfigMode() : stm32f10x_rtc.h , stm32f10x_rtc.c
  • RTC_FLAG_ALR : stm32f10x_rtc.h
  • RTC_FLAG_OW : stm32f10x_rtc.h
  • RTC_FLAG_RSF : stm32f10x_rtc.h
  • RTC_FLAG_RTOFF : stm32f10x_rtc.h
  • RTC_FLAG_SEC : stm32f10x_rtc.h
  • RTC_GetCounter() : stm32f10x_rtc.c , stm32f10x_rtc.h
  • RTC_GetDivider() : stm32f10x_rtc.c , stm32f10x_rtc.h
  • RTC_GetFlagStatus() : stm32f10x_rtc.c , stm32f10x_rtc.h
  • RTC_GetITStatus() : stm32f10x_rtc.h , stm32f10x_rtc.c
  • RTC_IRQHandler() : STM32F10x_StdPeriph_Examples/RTC/Calendar/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/RTC/Calendar/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_it.h
  • RTC_IRQn : stm32f10x.h
  • RTC_IT_ALR : stm32f10x_rtc.h
  • RTC_IT_OW : stm32f10x_rtc.h
  • RTC_IT_SEC : stm32f10x_rtc.h
  • RTC_ITConfig() : stm32f10x_rtc.h , stm32f10x_rtc.c
  • RTC_LSB_MASK : stm32f10x_rtc.c
  • RTC_PRLH_PRL : stm32f10x.h
  • RTC_PRLL_PRL : stm32f10x.h
  • RTC_SetAlarm() : stm32f10x_rtc.h , stm32f10x_rtc.c
  • RTC_SetCounter() : stm32f10x_rtc.h , stm32f10x_rtc.c
  • RTC_SetPrescaler() : stm32f10x_rtc.c , stm32f10x_rtc.h
  • RTC_WaitForLastTask() : stm32f10x_rtc.c , stm32f10x_rtc.h
  • RTC_WaitForSynchro() : stm32f10x_rtc.h , stm32f10x_rtc.c
  • RTCAlarm_IRQHandler() : STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_it.c
  • RTCClockOutput_Enable : STM32F10x_StdPeriph_Examples/RTC/Calendar/main.c , STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/main.c
  • RTCCR_CAL_MASK : stm32f10x_bkp.c
  • RTCCR_MASK : stm32f10x_bkp.c
  • RTCEN_BitNumber : stm32f10x_rcc.c
  • RWMOD_BitNumber : stm32f10x_sdio.c
  • RWSTART_BitNumber : stm32f10x_sdio.c
  • RWSTOP_BitNumber : stm32f10x_sdio.c
  • Rx1_Buffer : STM32F10x_StdPeriph_Examples/I2C/EEPROM/main.c
  • Rx2_Buffer : STM32F10x_StdPeriph_Examples/I2C/EEPROM/main.c
  • Rx_Buffer : STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/main.c
  • Rx_Idx : STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/main.c
  • RxBuffer : STM32F10x_StdPeriph_Examples/FSMC/NOR/main.c , STM32F10x_StdPeriph_Examples/FSMC/SRAM/main.c , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Polling/main.c , STM32F10x_StdPeriph_Examples/FSMC/NAND/main.c , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/main.c
  • RxBuffer1 : STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/DMA_Polling/main.c , STM32F10x_StdPeriph_Examples/USART/Synchronous/main.c , STM32F10x_StdPeriph_Examples/USART/HalfDuplex/main.c , STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/main.c , STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c
  • RxBuffer2 : STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Synchronous/main.c , STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/main.c , STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c , STM32F10x_StdPeriph_Examples/USART/HalfDuplex/main.c , STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/DMA_Polling/main.c
  • RxBuffer_A : STM32F10x_StdPeriph_Examples/FSMC/OneNAND/main.c
  • RxBuffer_S : STM32F10x_StdPeriph_Examples/FSMC/OneNAND/main.c
  • RxBufferSize : STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/main.c
  • RxBufferSize1 : STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c
  • RxBufferSize2 : STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c
  • RxCounter : STM32F10x_StdPeriph_Examples/USART/Polling/main.c , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/main.c , stm32100e_eval_cec.c , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.c , stm32100b_eval_cec.c , STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_it.c
  • RxCounter1 : STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/HalfDuplex/main.c , STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c , STM32F10x_StdPeriph_Examples/USART/Synchronous/main.c
  • RxCounter2 : STM32F10x_StdPeriph_Examples/USART/HalfDuplex/main.c , STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Synchronous/main.c , STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c
  • RxIdx : STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/main.c , STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/main.c , STM32F10x_StdPeriph_Examples/SPI/CRC/main.c , STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/main.c , STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2S/Interrupt/main.c
  • RxMessage : STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_it.c


STM32F10x Standard Peripherals Firmware Library: Globals

  • File List
  • Globals
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  • Variables
  • Typedefs
  • Enumerations
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  • f
  • g
  • h
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- s -

  • s16 : stm32f10x.h
  • s32 : stm32f10x.h
  • s8 : stm32f10x.h
  • sc16 : stm32f10x.h
  • sc32 : stm32f10x.h
  • sc8 : stm32f10x.h
  • SC_A2R : STM32F10x_StdPeriph_Examples/USART/Smartcard/main.c
  • SC_decode_Answer2reset() : STM32F10x_StdPeriph_Examples/USART/Smartcard/main.c
  • SC_Receive_Timeout : STM32F10x_StdPeriph_Examples/USART/Smartcard/main.c
  • SC_USART_IRQHandler() : STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_it.c
  • SCB_AFSR_IMPDEF : stm32f10x.h
  • SCB_AIRCR_ENDIANESS : stm32f10x.h
  • SCB_AIRCR_PRIGROUP : stm32f10x.h
  • SCB_AIRCR_PRIGROUP0 : stm32f10x.h
  • SCB_AIRCR_PRIGROUP1 : stm32f10x.h
  • SCB_AIRCR_PRIGROUP2 : stm32f10x.h
  • SCB_AIRCR_PRIGROUP3 : stm32f10x.h
  • SCB_AIRCR_PRIGROUP4 : stm32f10x.h
  • SCB_AIRCR_PRIGROUP5 : stm32f10x.h
  • SCB_AIRCR_PRIGROUP6 : stm32f10x.h
  • SCB_AIRCR_PRIGROUP7 : stm32f10x.h
  • SCB_AIRCR_PRIGROUP_0 : stm32f10x.h
  • SCB_AIRCR_PRIGROUP_1 : stm32f10x.h
  • SCB_AIRCR_PRIGROUP_2 : stm32f10x.h
  • SCB_AIRCR_SYSRESETREQ : stm32f10x.h
  • SCB_AIRCR_VECTCLRACTIVE : stm32f10x.h
  • SCB_AIRCR_VECTKEY : stm32f10x.h
  • SCB_AIRCR_VECTRESET : stm32f10x.h
  • SCB_BFAR_ADDRESS : stm32f10x.h
  • SCB_CCR_BFHFNMIGN : stm32f10x.h
  • SCB_CCR_DIV_0_TRP : stm32f10x.h
  • SCB_CCR_NONBASETHRDENA : stm32f10x.h
  • SCB_CCR_STKALIGN : stm32f10x.h
  • SCB_CCR_UNALIGN_TRP : stm32f10x.h
  • SCB_CCR_USERSETMPEND : stm32f10x.h
  • SCB_CFSR_BFARVALID : stm32f10x.h
  • SCB_CFSR_DACCVIOL : stm32f10x.h
  • SCB_CFSR_DIVBYZERO : stm32f10x.h
  • SCB_CFSR_IACCVIOL : stm32f10x.h
  • SCB_CFSR_IBUSERR : stm32f10x.h
  • SCB_CFSR_IMPRECISERR : stm32f10x.h
  • SCB_CFSR_INVPC : stm32f10x.h
  • SCB_CFSR_INVSTATE : stm32f10x.h
  • SCB_CFSR_MMARVALID : stm32f10x.h
  • SCB_CFSR_MSTKERR : stm32f10x.h
  • SCB_CFSR_MUNSTKERR : stm32f10x.h
  • SCB_CFSR_NOCP : stm32f10x.h
  • SCB_CFSR_PRECISERR : stm32f10x.h
  • SCB_CFSR_STKERR : stm32f10x.h
  • SCB_CFSR_UNALIGNED : stm32f10x.h
  • SCB_CFSR_UNDEFINSTR : stm32f10x.h
  • SCB_CFSR_UNSTKERR : stm32f10x.h
  • SCB_CPUID_Constant : stm32f10x.h
  • SCB_CPUID_IMPLEMENTER : stm32f10x.h
  • SCB_CPUID_PARTNO : stm32f10x.h
  • SCB_CPUID_REVISION : stm32f10x.h
  • SCB_CPUID_VARIANT : stm32f10x.h
  • SCB_DBG : stm32f10x_ip_dbg.c
  • SCB_DFSR_BKPT : stm32f10x.h
  • SCB_DFSR_DWTTRAP : stm32f10x.h
  • SCB_DFSR_EXTERNAL : stm32f10x.h
  • SCB_DFSR_HALTED : stm32f10x.h
  • SCB_DFSR_VCATCH : stm32f10x.h
  • SCB_HFSR_DEBUGEVT : stm32f10x.h
  • SCB_HFSR_FORCED : stm32f10x.h
  • SCB_HFSR_VECTTBL : stm32f10x.h
  • SCB_ICSR_ISRPENDING : stm32f10x.h
  • SCB_ICSR_ISRPREEMPT : stm32f10x.h
  • SCB_ICSR_NMIPENDSET : stm32f10x.h
  • SCB_ICSR_PENDSTCLR : stm32f10x.h
  • SCB_ICSR_PENDSTSET : stm32f10x.h
  • SCB_ICSR_PENDSVCLR : stm32f10x.h
  • SCB_ICSR_PENDSVSET : stm32f10x.h
  • SCB_ICSR_RETTOBASE : stm32f10x.h
  • SCB_ICSR_VECTACTIVE : stm32f10x.h
  • SCB_ICSR_VECTPENDING : stm32f10x.h
  • SCB_MMFAR_ADDRESS : stm32f10x.h
  • SCB_SCR_SEVONPEND : stm32f10x.h
  • SCB_SCR_SLEEPDEEP : stm32f10x.h
  • SCB_SCR_SLEEPONEXIT : stm32f10x.h
  • SCB_SHCSR_BUSFAULTACT : stm32f10x.h
  • SCB_SHCSR_BUSFAULTENA : stm32f10x.h
  • SCB_SHCSR_BUSFAULTPENDED : stm32f10x.h
  • SCB_SHCSR_MEMFAULTACT : stm32f10x.h
  • SCB_SHCSR_MEMFAULTENA : stm32f10x.h
  • SCB_SHCSR_MEMFAULTPENDED : stm32f10x.h
  • SCB_SHCSR_MONITORACT : stm32f10x.h
  • SCB_SHCSR_PENDSVACT : stm32f10x.h
  • SCB_SHCSR_SVCALLACT : stm32f10x.h
  • SCB_SHCSR_SVCALLPENDED : stm32f10x.h
  • SCB_SHCSR_SYSTICKACT : stm32f10x.h
  • SCB_SHCSR_USGFAULTACT : stm32f10x.h
  • SCB_SHCSR_USGFAULTENA : stm32f10x.h
  • SCB_SHCSR_USGFAULTPENDED : stm32f10x.h
  • SCB_SHPR_PRI_N : stm32f10x.h
  • SCB_SHPR_PRI_N1 : stm32f10x.h
  • SCB_SHPR_PRI_N2 : stm32f10x.h
  • SCB_SHPR_PRI_N3 : stm32f10x.h
  • SCB_VTOR_TBLBASE : stm32f10x.h
  • SCB_VTOR_TBLOFF : stm32f10x.h
  • SD_0TO7BITS : stm32_eval_sdio_sd.c
  • SD_16TO23BITS : stm32_eval_sdio_sd.c
  • SD_24TO31BITS : stm32_eval_sdio_sd.c
  • SD_8TO15BITS : stm32_eval_sdio_sd.c
  • SD_ADDR_MISALIGNED : stm32_eval_sdio_sd.h
  • SD_ADDR_OUT_OF_RANGE : stm32_eval_sdio_sd.h
  • SD_ADDRESS_ERROR : stm32_eval_spi_sd.h
  • SD_AKE_SEQ_ERROR : stm32_eval_sdio_sd.h
  • SD_ALLZERO : stm32_eval_sdio_sd.c
  • SD_BAD_ERASE_PARAM : stm32_eval_sdio_sd.h
  • SD_BLOCK_LEN_ERR : stm32_eval_sdio_sd.h
  • SD_BLOCK_SIZE : stm32_eval_spi_sd.h
  • SD_CARD_DISCONNECTED : stm32_eval_sdio_sd.h
  • SD_CARD_ECC_DISABLED : stm32_eval_sdio_sd.h
  • SD_CARD_ECC_FAILED : stm32_eval_sdio_sd.h
  • SD_CARD_ERROR : stm32_eval_sdio_sd.h
  • SD_CARD_IDENTIFICATION : stm32_eval_sdio_sd.h
  • SD_CARD_LOCKED : stm32_eval_sdio_sd.c
  • SD_CARD_PROGRAMMING : stm32_eval_sdio_sd.h
  • SD_CARD_READY : stm32_eval_sdio_sd.h
  • SD_CARD_RECEIVING : stm32_eval_sdio_sd.h
  • SD_CARD_SENDING : stm32_eval_sdio_sd.h
  • SD_CARD_STANDBY : stm32_eval_sdio_sd.h
  • SD_CARD_TRANSFER : stm32_eval_sdio_sd.h
  • SD_CC_ERROR : stm32_eval_sdio_sd.h
  • SD_CCCC_ERASE : stm32_eval_sdio_sd.c
  • SD_CCCC_LOCK_UNLOCK : stm32_eval_sdio_sd.c
  • SD_CCCC_WRITE_PROT : stm32_eval_sdio_sd.c
  • SD_CHECK_PATTERN : stm32_eval_sdio_sd.c
  • SD_CID_CSD_OVERWRITE : stm32_eval_sdio_sd.h
  • SD_CMD_ALL_SEND_CID : stm32_eval_sdio_sd.h
  • SD_CMD_APP_CMD : stm32_eval_sdio_sd.h
  • SD_CMD_APP_SD_SET_BUSWIDTH : stm32_eval_sdio_sd.h
  • SD_CMD_CLR_WRITE_PROT : stm32_eval_sdio_sd.h , stm32_eval_spi_sd.h
  • SD_CMD_CRC_FAIL : stm32_eval_sdio_sd.h
  • SD_CMD_ERASE : stm32_eval_sdio_sd.h , stm32_eval_spi_sd.h
  • SD_CMD_ERASE_GRP_END : stm32_eval_sdio_sd.h , stm32_eval_spi_sd.h
  • SD_CMD_ERASE_GRP_START : stm32_eval_sdio_sd.h , stm32_eval_spi_sd.h
  • SD_CMD_FAST_IO : stm32_eval_sdio_sd.h
  • SD_CMD_GEN_CMD : stm32_eval_sdio_sd.h
  • SD_CMD_GO_IDLE_STATE : stm32_eval_sdio_sd.h , stm32_eval_spi_sd.h
  • SD_CMD_GO_INACTIVE_STATE : stm32_eval_sdio_sd.h
  • SD_CMD_GO_IRQ_STATE : stm32_eval_sdio_sd.h
  • SD_CMD_HS_BUSTEST_READ : stm32_eval_sdio_sd.h
  • SD_CMD_HS_BUSTEST_WRITE : stm32_eval_sdio_sd.h
  • SD_CMD_HS_SEND_EXT_CSD : stm32_eval_sdio_sd.h
  • SD_CMD_HS_SWITCH : stm32_eval_sdio_sd.h
  • SD_CMD_LOCK_UNLOCK : stm32_eval_sdio_sd.h
  • SD_CMD_NO_CMD : stm32_eval_sdio_sd.h
  • SD_CMD_OUT_OF_RANGE : stm32_eval_sdio_sd.h
  • SD_CMD_PROG_CID : stm32_eval_sdio_sd.h
  • SD_CMD_PROG_CSD : stm32_eval_sdio_sd.h , stm32_eval_spi_sd.h
  • SD_CMD_READ_DAT_UNTIL_STOP : stm32_eval_sdio_sd.h
  • SD_CMD_READ_MULT_BLOCK : stm32_eval_sdio_sd.h , stm32_eval_spi_sd.h
  • SD_CMD_READ_SINGLE_BLOCK : stm32_eval_sdio_sd.h , stm32_eval_spi_sd.h
  • SD_CMD_RSP_TIMEOUT : stm32_eval_sdio_sd.h
  • SD_CMD_SD_APP_CHANGE_SECURE_AREA : stm32_eval_sdio_sd.h
  • SD_CMD_SD_APP_GET_CER_RES1 : stm32_eval_sdio_sd.h
  • SD_CMD_SD_APP_GET_CER_RN2 : stm32_eval_sdio_sd.h
  • SD_CMD_SD_APP_GET_MID : stm32_eval_sdio_sd.h
  • SD_CMD_SD_APP_GET_MKB : stm32_eval_sdio_sd.h
  • SD_CMD_SD_APP_OP_COND : stm32_eval_sdio_sd.h
  • SD_CMD_SD_APP_SECURE_ERASE : stm32_eval_sdio_sd.h
  • SD_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK : stm32_eval_sdio_sd.h
  • SD_CMD_SD_APP_SECURE_WRITE_MKB : stm32_eval_sdio_sd.h
  • SD_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK : stm32_eval_sdio_sd.h
  • SD_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS : stm32_eval_sdio_sd.h
  • SD_CMD_SD_APP_SEND_SCR : stm32_eval_sdio_sd.h
  • SD_CMD_SD_APP_SET_CER_RES2 : stm32_eval_sdio_sd.h
  • SD_CMD_SD_APP_SET_CER_RN1 : stm32_eval_sdio_sd.h
  • SD_CMD_SD_APP_SET_CLR_CARD_DETECT : stm32_eval_sdio_sd.h
  • SD_CMD_SD_APP_STAUS : stm32_eval_sdio_sd.h
  • SD_CMD_SD_ERASE_GRP_END : stm32_eval_sdio_sd.h , stm32_eval_spi_sd.h
  • SD_CMD_SD_ERASE_GRP_START : stm32_eval_sdio_sd.h , stm32_eval_spi_sd.h
  • SD_CMD_SDIO_RW_DIRECT : stm32_eval_sdio_sd.h
  • SD_CMD_SDIO_RW_EXTENDED : stm32_eval_sdio_sd.h
  • SD_CMD_SDIO_SEN_OP_COND : stm32_eval_sdio_sd.h
  • SD_CMD_SEL_DESEL_CARD : stm32_eval_sdio_sd.h
  • SD_CMD_SEND_CID : stm32_eval_sdio_sd.h , stm32_eval_spi_sd.h
  • SD_CMD_SEND_CSD : stm32_eval_sdio_sd.h , stm32_eval_spi_sd.h
  • SD_CMD_SEND_OP_COND : stm32_eval_sdio_sd.h , stm32_eval_spi_sd.h
  • SD_CMD_SEND_STATUS : stm32_eval_sdio_sd.h , stm32_eval_spi_sd.h
  • SD_CMD_SEND_WRITE_PROT : stm32_eval_sdio_sd.h , stm32_eval_spi_sd.h
  • SD_CMD_SET_BLOCK_COUNT : stm32_eval_sdio_sd.h , stm32_eval_spi_sd.h
  • SD_CMD_SET_BLOCKLEN : stm32_eval_sdio_sd.h , stm32_eval_spi_sd.h
  • SD_CMD_SET_DSR : stm32_eval_sdio_sd.h
  • SD_CMD_SET_REL_ADDR : stm32_eval_sdio_sd.h
  • SD_CMD_SET_WRITE_PROT : stm32_eval_sdio_sd.h , stm32_eval_spi_sd.h
  • SD_CMD_STOP_TRANSMISSION : stm32_eval_sdio_sd.h , stm32_eval_spi_sd.h
  • SD_CMD_UNTAG_ERASE_GROUP : stm32_eval_spi_sd.h
  • SD_CMD_UNTAG_SECTOR : stm32_eval_spi_sd.h
  • SD_CMD_WRITE_DAT_UNTIL_STOP : stm32_eval_sdio_sd.h
  • SD_CMD_WRITE_MULT_BLOCK : stm32_eval_sdio_sd.h , stm32_eval_spi_sd.h
  • SD_CMD_WRITE_SINGLE_BLOCK : stm32_eval_sdio_sd.h , stm32_eval_spi_sd.h
  • SD_COM_CRC_ERROR : stm32_eval_spi_sd.h
  • SD_COM_CRC_FAILED : stm32_eval_sdio_sd.h
  • SD_CS_GPIO_CLK : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210c_eval.h , stm32l152_eval.h
  • SD_CS_GPIO_PORT : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210c_eval.h , stm32l152_eval.h
  • SD_CS_HIGH : stm32_eval_spi_sd.h
  • SD_CS_LOW : stm32_eval_spi_sd.h
  • SD_CS_PIN : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210c_eval.h , stm32l152_eval.h
  • SD_DATA_CRC_ERROR : stm32_eval_spi_sd.h
  • SD_DATA_CRC_FAIL : stm32_eval_sdio_sd.h
  • SD_DATA_OK : stm32_eval_spi_sd.h
  • SD_DATA_OTHER_ERROR : stm32_eval_spi_sd.h
  • SD_DATA_TIMEOUT : stm32_eval_sdio_sd.h
  • SD_DATA_WRITE_ERROR : stm32_eval_spi_sd.h
  • SD_DATATIMEOUT : stm32_eval_sdio_sd.c
  • SD_DeInit() : stm32_eval_sdio_sd.c , stm32_eval_sdio_sd.h , stm32_eval_spi_sd.c , stm32_eval_spi_sd.h
  • SD_Detect() : stm32_eval_sdio_sd.c , stm32_eval_sdio_sd.h , stm32_eval_spi_sd.c , stm32_eval_spi_sd.h
  • SD_DETECT_EXTI_IRQn : stm32l152_eval.h
  • SD_DETECT_EXTI_LINE : stm32l152_eval.h
  • SD_DETECT_EXTI_PIN_SOURCE : stm32l152_eval.h
  • SD_DETECT_EXTI_PORT_SOURCE : stm32l152_eval.h
  • SD_DETECT_GPIO_CLK : stm3210b_eval.h , stm3210c_eval.h , stm3210e_eval.h , stm32l152_eval.h , stm32100b_eval.h , stm32100e_eval.h
  • SD_DETECT_GPIO_PORT : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210c_eval.h , stm3210e_eval.h , stm32l152_eval.h
  • SD_DETECT_PIN : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210c_eval.h , stm3210e_eval.h , stm32l152_eval.h
  • SD_DMA_MODE : stm32_eval_sdio_sd.h
  • SD_DMAEndOfTransferStatus() : stm3210e_eval.c , stm3210e_eval.h
  • SD_DUMMY_BYTE : stm32_eval_spi_sd.h
  • SD_EnableWideBusOperation() : stm32_eval_sdio_sd.c , stm32_eval_sdio_sd.h
  • SD_Erase() : stm32_eval_sdio_sd.c , stm32_eval_sdio_sd.h
  • SD_ERASE_RESET : stm32_eval_sdio_sd.h , stm32_eval_spi_sd.h
  • SD_ERASE_SEQ_ERR : stm32_eval_sdio_sd.h
  • SD_ERASE_SEQUENCE_ERROR : stm32_eval_spi_sd.h
  • SD_EraseTest() : STM32F10x_StdPeriph_Examples/SDIO/uSDCard/main.c
  • SD_Error : stm32_eval_sdio_sd.h , stm32_eval_spi_sd.h
  • SD_ERROR : stm32_eval_sdio_sd.h
  • SD_GENERAL_UNKNOWN_ERROR : stm32_eval_sdio_sd.h
  • SD_GetCardInfo() : stm32_eval_sdio_sd.c , stm32_eval_sdio_sd.h , stm32_eval_spi_sd.c , stm32_eval_spi_sd.h
  • SD_GetCardStatus() : stm32_eval_sdio_sd.c , stm32_eval_sdio_sd.h
  • SD_GetCIDRegister() : stm32_eval_spi_sd.c , stm32_eval_spi_sd.h
  • SD_GetCSDRegister() : stm32_eval_spi_sd.c , stm32_eval_spi_sd.h
  • SD_GetDataResponse() : stm32_eval_spi_sd.c , stm32_eval_spi_sd.h
  • SD_GetResponse() : stm32_eval_spi_sd.c , stm32_eval_spi_sd.h
  • SD_GetState() : stm32_eval_sdio_sd.c , stm32_eval_sdio_sd.h
  • SD_GetStatus() : stm32_eval_sdio_sd.c , stm32_eval_sdio_sd.h , stm32_eval_spi_sd.c , stm32_eval_spi_sd.h
  • SD_GetTransferState() : stm32_eval_sdio_sd.c , stm32_eval_sdio_sd.h
  • SD_GoIdleState() : stm32_eval_spi_sd.c , stm32_eval_spi_sd.h
  • SD_HALFFIFO : stm32_eval_sdio_sd.c
  • SD_HALFFIFOBYTES : stm32_eval_sdio_sd.c
  • SD_HIGH_CAPACITY : stm32_eval_sdio_sd.c
  • SD_ILLEGAL_CMD : stm32_eval_sdio_sd.h
  • SD_ILLEGAL_COMMAND : stm32_eval_spi_sd.h
  • SD_IN_IDLE_STATE : stm32_eval_spi_sd.h
  • SD_Init() : stm32_eval_sdio_sd.c , stm32_eval_sdio_sd.h , stm32_eval_spi_sd.c , stm32_eval_spi_sd.h
  • SD_InitializeCards() : stm32_eval_sdio_sd.c , stm32_eval_sdio_sd.h
  • SD_INTERNAL_ERROR : stm32_eval_sdio_sd.h
  • SD_INVALID_PARAMETER : stm32_eval_sdio_sd.h
  • SD_INVALID_VOLTRANGE : stm32_eval_sdio_sd.h
  • SD_LOCK_UNLOCK_FAILED : stm32_eval_sdio_sd.h
  • SD_LowLevel_DeInit() : stm32100b_eval.c , stm32100b_eval.h , stm32100e_eval.c , stm32100e_eval.h , stm3210b_eval.c , stm3210b_eval.h , stm3210c_eval.c , stm3210c_eval.h , stm3210e_eval.c , stm3210e_eval.h , stm32l152_eval.c , stm32l152_eval.h
  • SD_LowLevel_DMA_RxConfig() : stm3210e_eval.c , stm3210e_eval.h
  • SD_LowLevel_DMA_TxConfig() : stm3210e_eval.c , stm3210e_eval.h
  • SD_LowLevel_Init() : stm32100b_eval.c , stm32100b_eval.h , stm32100e_eval.c , stm32100e_eval.h , stm3210b_eval.c , stm3210b_eval.h , stm3210c_eval.c , stm3210c_eval.h , stm3210e_eval.c , stm3210e_eval.h , stm32l152_eval.c , stm32l152_eval.h
  • SD_MAX_DATA_LENGTH : stm32_eval_sdio_sd.c
  • SD_MAX_VOLT_TRIAL : stm32_eval_sdio_sd.c
  • SD_MultiBlockTest() : STM32F10x_StdPeriph_Examples/SDIO/uSDCard/main.c
  • SD_NOT_CONFIGURED : stm32_eval_sdio_sd.h
  • SD_NOT_PRESENT : stm32_eval_sdio_sd.h , stm32_eval_spi_sd.h
  • SD_OCR_ADDR_MISALIGNED : stm32_eval_sdio_sd.c
  • SD_OCR_ADDR_OUT_OF_RANGE : stm32_eval_sdio_sd.c
  • SD_OCR_AKE_SEQ_ERROR : stm32_eval_sdio_sd.c
  • SD_OCR_BAD_ERASE_PARAM : stm32_eval_sdio_sd.c
  • SD_OCR_BLOCK_LEN_ERR : stm32_eval_sdio_sd.c
  • SD_OCR_CARD_ECC_DISABLED : stm32_eval_sdio_sd.c
  • SD_OCR_CARD_ECC_FAILED : stm32_eval_sdio_sd.c
  • SD_OCR_CC_ERROR : stm32_eval_sdio_sd.c
  • SD_OCR_CID_CSD_OVERWRIETE : stm32_eval_sdio_sd.c
  • SD_OCR_COM_CRC_FAILED : stm32_eval_sdio_sd.c
  • SD_OCR_ERASE_RESET : stm32_eval_sdio_sd.c
  • SD_OCR_ERASE_SEQ_ERR : stm32_eval_sdio_sd.c
  • SD_OCR_ERRORBITS : stm32_eval_sdio_sd.c
  • SD_OCR_GENERAL_UNKNOWN_ERROR : stm32_eval_sdio_sd.c
  • SD_OCR_ILLEGAL_CMD : stm32_eval_sdio_sd.c
  • SD_OCR_LOCK_UNLOCK_FAILED : stm32_eval_sdio_sd.c
  • SD_OCR_STREAM_READ_UNDERRUN : stm32_eval_sdio_sd.c
  • SD_OCR_STREAM_WRITE_OVERRUN : stm32_eval_sdio_sd.c
  • SD_OCR_WP_ERASE_SKIP : stm32_eval_sdio_sd.c
  • SD_OCR_WRITE_PROT_VIOLATION : stm32_eval_sdio_sd.c
  • SD_OK : stm32_eval_sdio_sd.h
  • SD_OPERATION_BLOCK : STM32F10x_StdPeriph_Examples/SDIO/uSDCard/main.c
  • SD_OPERATION_END : STM32F10x_StdPeriph_Examples/SDIO/uSDCard/main.c
  • SD_OPERATION_ERASE : STM32F10x_StdPeriph_Examples/SDIO/uSDCard/main.c
  • SD_OPERATION_MULTI_BLOCK : STM32F10x_StdPeriph_Examples/SDIO/uSDCard/main.c
  • SD_PARAMETER_ERROR : stm32_eval_spi_sd.h
  • SD_PowerOFF() : stm32_eval_sdio_sd.c , stm32_eval_sdio_sd.h
  • SD_PowerON() : stm32_eval_sdio_sd.c , stm32_eval_sdio_sd.h
  • SD_PRESENT : stm32_eval_sdio_sd.h , stm32_eval_spi_sd.h
  • SD_ProcessIRQSrc() : stm32_eval_sdio_sd.c , stm32_eval_sdio_sd.h
  • SD_R6_COM_CRC_FAILED : stm32_eval_sdio_sd.c
  • SD_R6_GENERAL_UNKNOWN_ERROR : stm32_eval_sdio_sd.c
  • SD_R6_ILLEGAL_CMD : stm32_eval_sdio_sd.c
  • SD_ReadBlock() : stm32_eval_sdio_sd.c , stm32_eval_sdio_sd.h , stm32_eval_spi_sd.c , stm32_eval_spi_sd.h
  • SD_ReadByte() : stm32_eval_spi_sd.c , stm32_eval_spi_sd.h
  • SD_ReadMultiBlocks() : stm32_eval_sdio_sd.c , stm32_eval_sdio_sd.h , stm32_eval_spi_sd.c , stm32_eval_spi_sd.h
  • SD_REQUEST_NOT_APPLICABLE : stm32_eval_sdio_sd.h
  • SD_REQUEST_PENDING : stm32_eval_sdio_sd.h
  • SD_RESPONSE_FAILURE : stm32_eval_spi_sd.h
  • SD_RESPONSE_NO_ERROR : stm32_eval_spi_sd.h
  • SD_RX_OVERRUN : stm32_eval_sdio_sd.h
  • SD_SDIO_DISABLED : stm32_eval_sdio_sd.h
  • SD_SDIO_FUNCTION_BUSY : stm32_eval_sdio_sd.h
  • SD_SDIO_FUNCTION_FAILED : stm32_eval_sdio_sd.h
  • SD_SDIO_UNKNOWN_FUNCTION : stm32_eval_sdio_sd.h
  • SD_SelectDeselect() : stm32_eval_sdio_sd.c , stm32_eval_sdio_sd.h
  • SD_SendCmd() : stm32_eval_spi_sd.c , stm32_eval_spi_sd.h
  • SD_SendSDStatus() : stm32_eval_sdio_sd.c , stm32_eval_sdio_sd.h
  • SD_SendStatus() : stm32_eval_sdio_sd.c , stm32_eval_sdio_sd.h
  • SD_SINGLE_BUS_SUPPORT : stm32_eval_sdio_sd.c
  • SD_SingleBlockTest() : STM32F10x_StdPeriph_Examples/SDIO/uSDCard/main.c
  • SD_SPI : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210c_eval.h , stm32l152_eval.h
  • SD_SPI_CLK : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210c_eval.h , stm32l152_eval.h
  • SD_SPI_MISO_AF : stm32l152_eval.h
  • SD_SPI_MISO_GPIO_CLK : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210c_eval.h , stm32l152_eval.h
  • SD_SPI_MISO_GPIO_PORT : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210c_eval.h , stm32l152_eval.h
  • SD_SPI_MISO_PIN : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210c_eval.h , stm32l152_eval.h
  • SD_SPI_MISO_SOURCE : stm32l152_eval.h
  • SD_SPI_MOSI_AF : stm32l152_eval.h
  • SD_SPI_MOSI_GPIO_CLK : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210c_eval.h , stm32l152_eval.h
  • SD_SPI_MOSI_GPIO_PORT : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210c_eval.h , stm32l152_eval.h
  • SD_SPI_MOSI_PIN : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210c_eval.h , stm32l152_eval.h
  • SD_SPI_MOSI_SOURCE : stm32l152_eval.h
  • SD_SPI_SCK_AF : stm32l152_eval.h
  • SD_SPI_SCK_GPIO_CLK : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210c_eval.h , stm32l152_eval.h
  • SD_SPI_SCK_GPIO_PORT : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210c_eval.h , stm32l152_eval.h
  • SD_SPI_SCK_PIN : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210c_eval.h , stm32l152_eval.h
  • SD_SPI_SCK_SOURCE : stm32l152_eval.h
  • SD_START_BIT_ERR : stm32_eval_sdio_sd.h
  • SD_START_DATA_MULTIPLE_BLOCK_READ : stm32_eval_spi_sd.h
  • SD_START_DATA_MULTIPLE_BLOCK_WRITE : stm32_eval_spi_sd.h
  • SD_START_DATA_SINGLE_BLOCK_READ : stm32_eval_spi_sd.h
  • SD_START_DATA_SINGLE_BLOCK_WRITE : stm32_eval_spi_sd.h
  • SD_STD_CAPACITY : stm32_eval_sdio_sd.c
  • SD_STOP_DATA_MULTIPLE_BLOCK_WRITE : stm32_eval_spi_sd.h
  • SD_StopTransfer() : stm32_eval_sdio_sd.c , stm32_eval_sdio_sd.h
  • SD_STREAM_READ_UNDERRUN : stm32_eval_sdio_sd.h
  • SD_STREAM_WRITE_OVERRUN : stm32_eval_sdio_sd.h
  • SD_SWITCH_ERROR : stm32_eval_sdio_sd.h
  • SD_TRANSFER_BUSY : stm32_eval_sdio_sd.h
  • SD_TRANSFER_ERROR : stm32_eval_sdio_sd.h
  • SD_TRANSFER_OK : stm32_eval_sdio_sd.h
  • SD_TX_UNDERRUN : stm32_eval_sdio_sd.h
  • SD_UNSUPPORTED_FEATURE : stm32_eval_sdio_sd.h
  • SD_UNSUPPORTED_HW : stm32_eval_sdio_sd.h
  • SD_VOLTAGE_WINDOW_SD : stm32_eval_sdio_sd.c
  • SD_WaitReadOperation() : stm32_eval_sdio_sd.c , stm32_eval_sdio_sd.h
  • SD_WaitWriteOperation() : stm32_eval_sdio_sd.h , stm32_eval_sdio_sd.c
  • SD_WIDE_BUS_SUPPORT : stm32_eval_sdio_sd.c
  • SD_WP_ERASE_SKIP : stm32_eval_sdio_sd.h
  • SD_WRITE_PROT_VIOLATION : stm32_eval_sdio_sd.h
  • SD_WriteBlock() : stm32_eval_sdio_sd.c , stm32_eval_sdio_sd.h , stm32_eval_spi_sd.c , stm32_eval_spi_sd.h
  • SD_WriteByte() : stm32_eval_spi_sd.c , stm32_eval_spi_sd.h
  • SD_WriteMultiBlocks() : stm32_eval_sdio_sd.c , stm32_eval_sdio_sd.h , stm32_eval_spi_sd.c , stm32_eval_spi_sd.h
  • SDCardInfo : stm32_eval_sdio_sd.c
  • SDCardOperation : STM32F10x_StdPeriph_Examples/SDIO/uSDCard/main.c
  • SDCardState : stm32_eval_sdio_sd.h
  • SDEnWideBus() : stm32_eval_sdio_sd.c
  • SDIO : stm32f10x.h
  • SDIO_ARG_CMDARG : stm32f10x.h
  • SDIO_BASE : stm32f10x.h
  • SDIO_BusWide_1b : stm32f10x_sdio.h
  • SDIO_BusWide_4b : stm32f10x_sdio.h
  • SDIO_BusWide_8b : stm32f10x_sdio.h
  • SDIO_CEATAITCmd() : stm32f10x_sdio.h , stm32f10x_sdio.c
  • SDIO_ClearFlag() : stm32f10x_sdio.h , stm32f10x_sdio.c
  • SDIO_ClearITPendingBit() : stm32f10x_sdio.h , stm32f10x_sdio.c
  • SDIO_CLKCR_BYPASS : stm32f10x.h
  • SDIO_CLKCR_CLKDIV : stm32f10x.h
  • SDIO_CLKCR_CLKEN : stm32f10x.h
  • SDIO_CLKCR_HWFC_EN : stm32f10x.h
  • SDIO_CLKCR_NEGEDGE : stm32f10x.h
  • SDIO_CLKCR_PWRSAV : stm32f10x.h
  • SDIO_CLKCR_WIDBUS : stm32f10x.h
  • SDIO_CLKCR_WIDBUS_0 : stm32f10x.h
  • SDIO_CLKCR_WIDBUS_1 : stm32f10x.h
  • SDIO_ClockBypass_Disable : stm32f10x_sdio.h
  • SDIO_ClockBypass_Enable : stm32f10x_sdio.h
  • SDIO_ClockCmd() : stm32f10x_sdio.h , stm32f10x_sdio.c
  • SDIO_ClockEdge_Falling : stm32f10x_sdio.h
  • SDIO_ClockEdge_Rising : stm32f10x_sdio.h
  • SDIO_ClockPowerSave_Disable : stm32f10x_sdio.h
  • SDIO_ClockPowerSave_Enable : stm32f10x_sdio.h
  • SDIO_CMD0TIMEOUT : stm32_eval_sdio_sd.c
  • SDIO_CMD_CEATACMD : stm32f10x.h
  • SDIO_CMD_CMDINDEX : stm32f10x.h
  • SDIO_CMD_CPSMEN : stm32f10x.h
  • SDIO_CMD_ENCMDCOMPL : stm32f10x.h
  • SDIO_CMD_NIEN : stm32f10x.h
  • SDIO_CMD_SDIOSUSPEND : stm32f10x.h
  • SDIO_CMD_WAITINT : stm32f10x.h
  • SDIO_CMD_WAITPEND : stm32f10x.h
  • SDIO_CMD_WAITRESP : stm32f10x.h
  • SDIO_CMD_WAITRESP_0 : stm32f10x.h
  • SDIO_CMD_WAITRESP_1 : stm32f10x.h
  • SDIO_CmdInitStructure : stm32_eval_sdio_sd.c
  • SDIO_CmdStructInit() : stm32f10x_sdio.h , stm32f10x_sdio.c
  • SDIO_CommandCompletionCmd() : stm32f10x_sdio.h , stm32f10x_sdio.c
  • SDIO_CPSM_Disable : stm32f10x_sdio.h
  • SDIO_CPSM_Enable : stm32f10x_sdio.h
  • SDIO_DataBlockSize_1024b : stm32f10x_sdio.h
  • SDIO_DataBlockSize_128b : stm32f10x_sdio.h
  • SDIO_DataBlockSize_16384b : stm32f10x_sdio.h
  • SDIO_DataBlockSize_16b : stm32f10x_sdio.h
  • SDIO_DataBlockSize_1b : stm32f10x_sdio.h
  • SDIO_DataBlockSize_2048b : stm32f10x_sdio.h
  • SDIO_DataBlockSize_256b : stm32f10x_sdio.h
  • SDIO_DataBlockSize_2b : stm32f10x_sdio.h
  • SDIO_DataBlockSize_32b : stm32f10x_sdio.h
  • SDIO_DataBlockSize_4096b : stm32f10x_sdio.h
  • SDIO_DataBlockSize_4b : stm32f10x_sdio.h
  • SDIO_DataBlockSize_512b : stm32f10x_sdio.h
  • SDIO_DataBlockSize_64b : stm32f10x_sdio.h
  • SDIO_DataBlockSize_8192b : stm32f10x_sdio.h
  • SDIO_DataBlockSize_8b : stm32f10x_sdio.h
  • SDIO_DataConfig() : stm32f10x_sdio.h , stm32f10x_sdio.c
  • SDIO_DataInitStructure : stm32_eval_sdio_sd.c
  • SDIO_DataStructInit() : stm32f10x_sdio.h , stm32f10x_sdio.c
  • SDIO_DBG : stm32f10x_ip_dbg.c
  • SDIO_DCOUNT_DATACOUNT : stm32f10x.h
  • SDIO_DCTRL_DBLOCKSIZE : stm32f10x.h
  • SDIO_DCTRL_DBLOCKSIZE_0 : stm32f10x.h
  • SDIO_DCTRL_DBLOCKSIZE_1 : stm32f10x.h
  • SDIO_DCTRL_DBLOCKSIZE_2 : stm32f10x.h
  • SDIO_DCTRL_DBLOCKSIZE_3 : stm32f10x.h
  • SDIO_DCTRL_DMAEN : stm32f10x.h
  • SDIO_DCTRL_DTDIR : stm32f10x.h
  • SDIO_DCTRL_DTEN : stm32f10x.h
  • SDIO_DCTRL_DTMODE : stm32f10x.h
  • SDIO_DCTRL_RWMOD : stm32f10x.h
  • SDIO_DCTRL_RWSTART : stm32f10x.h
  • SDIO_DCTRL_RWSTOP : stm32f10x.h
  • SDIO_DCTRL_SDIOEN : stm32f10x.h
  • SDIO_DeInit() : stm32f10x_sdio.h , stm32f10x_sdio.c
  • SDIO_DLEN_DATALENGTH : stm32f10x.h
  • SDIO_DMACmd() : stm32f10x_sdio.h , stm32f10x_sdio.c
  • SDIO_DPSM_Disable : stm32f10x_sdio.h
  • SDIO_DPSM_Enable : stm32f10x_sdio.h
  • SDIO_DTIMER_DATATIME : stm32f10x.h
  • SDIO_FIFO_ADDRESS : stm3210e_eval.h
  • SDIO_FIFO_FIFODATA : stm32f10x.h
  • SDIO_FIFOCNT_FIFOCOUNT : stm32f10x.h
  • SDIO_FLAG_CCRCFAIL : stm32f10x_sdio.h
  • SDIO_FLAG_CEATAEND : stm32f10x_sdio.h
  • SDIO_FLAG_CMDACT : stm32f10x_sdio.h
  • SDIO_FLAG_CMDREND : stm32f10x_sdio.h
  • SDIO_FLAG_CMDSENT : stm32f10x_sdio.h
  • SDIO_FLAG_CTIMEOUT : stm32f10x_sdio.h
  • SDIO_FLAG_DATAEND : stm32f10x_sdio.h
  • SDIO_FLAG_DBCKEND : stm32f10x_sdio.h
  • SDIO_FLAG_DCRCFAIL : stm32f10x_sdio.h
  • SDIO_FLAG_DTIMEOUT : stm32f10x_sdio.h
  • SDIO_FLAG_RXACT : stm32f10x_sdio.h
  • SDIO_FLAG_RXDAVL : stm32f10x_sdio.h
  • SDIO_FLAG_RXFIFOE : stm32f10x_sdio.h
  • SDIO_FLAG_RXFIFOF : stm32f10x_sdio.h
  • SDIO_FLAG_RXFIFOHF : stm32f10x_sdio.h
  • SDIO_FLAG_RXOVERR : stm32f10x_sdio.h
  • SDIO_FLAG_SDIOIT : stm32f10x_sdio.h
  • SDIO_FLAG_STBITERR : stm32f10x_sdio.h
  • SDIO_FLAG_TXACT : stm32f10x_sdio.h
  • SDIO_FLAG_TXDAVL : stm32f10x_sdio.h
  • SDIO_FLAG_TXFIFOE : stm32f10x_sdio.h
  • SDIO_FLAG_TXFIFOF : stm32f10x_sdio.h
  • SDIO_FLAG_TXFIFOHE : stm32f10x_sdio.h
  • SDIO_FLAG_TXUNDERR : stm32f10x_sdio.h
  • SDIO_GetCommandResponse() : stm32f10x_sdio.h , stm32f10x_sdio.c
  • SDIO_GetDataCounter() : stm32f10x_sdio.h , stm32f10x_sdio.c
  • SDIO_GetFIFOCount() : stm32f10x_sdio.h , stm32f10x_sdio.c
  • SDIO_GetFlagStatus() : stm32f10x_sdio.h , stm32f10x_sdio.c
  • SDIO_GetITStatus() : stm32f10x_sdio.h , stm32f10x_sdio.c
  • SDIO_GetPowerState() : stm32f10x_sdio.h , stm32f10x_sdio.c
  • SDIO_GetResponse() : stm32f10x_sdio.h , stm32f10x_sdio.c
  • SDIO_HardwareFlowControl_Disable : stm32f10x_sdio.h
  • SDIO_HardwareFlowControl_Enable : stm32f10x_sdio.h
  • SDIO_HIGH_CAPACITY_MMC_CARD : stm32_eval_sdio_sd.h
  • SDIO_HIGH_CAPACITY_SD_CARD : stm32_eval_sdio_sd.h
  • SDIO_HIGH_SPEED_MULTIMEDIA_CARD : stm32_eval_sdio_sd.h
  • SDIO_ICR_CCRCFAILC : stm32f10x.h
  • SDIO_ICR_CEATAENDC : stm32f10x.h
  • SDIO_ICR_CMDRENDC : stm32f10x.h
  • SDIO_ICR_CMDSENTC : stm32f10x.h
  • SDIO_ICR_CTIMEOUTC : stm32f10x.h
  • SDIO_ICR_DATAENDC : stm32f10x.h
  • SDIO_ICR_DBCKENDC : stm32f10x.h
  • SDIO_ICR_DCRCFAILC : stm32f10x.h
  • SDIO_ICR_DTIMEOUTC : stm32f10x.h
  • SDIO_ICR_RXOVERRC : stm32f10x.h
  • SDIO_ICR_SDIOITC : stm32f10x.h
  • SDIO_ICR_STBITERRC : stm32f10x.h
  • SDIO_ICR_TXUNDERRC : stm32f10x.h
  • SDIO_Init() : stm32f10x_sdio.h , stm32f10x_sdio.c
  • SDIO_INIT_CLK_DIV : stm3210e_eval.h
  • SDIO_InitStructure : stm32_eval_sdio_sd.c
  • SDIO_IRQHandler() : STM32F10x_StdPeriph_Examples/SDIO/uSDCard/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SDIO/uSDCard/stm32f10x_it.h
  • SDIO_IT_CCRCFAIL : stm32f10x_sdio.h
  • SDIO_IT_CEATAEND : stm32f10x_sdio.h
  • SDIO_IT_CMDACT : stm32f10x_sdio.h
  • SDIO_IT_CMDREND : stm32f10x_sdio.h
  • SDIO_IT_CMDSENT : stm32f10x_sdio.h
  • SDIO_IT_CTIMEOUT : stm32f10x_sdio.h
  • SDIO_IT_DATAEND : stm32f10x_sdio.h
  • SDIO_IT_DBCKEND : stm32f10x_sdio.h
  • SDIO_IT_DCRCFAIL : stm32f10x_sdio.h
  • SDIO_IT_DTIMEOUT : stm32f10x_sdio.h
  • SDIO_IT_RXACT : stm32f10x_sdio.h
  • SDIO_IT_RXDAVL : stm32f10x_sdio.h
  • SDIO_IT_RXFIFOE : stm32f10x_sdio.h
  • SDIO_IT_RXFIFOF : stm32f10x_sdio.h
  • SDIO_IT_RXFIFOHF : stm32f10x_sdio.h
  • SDIO_IT_RXOVERR : stm32f10x_sdio.h
  • SDIO_IT_SDIOIT : stm32f10x_sdio.h
  • SDIO_IT_STBITERR : stm32f10x_sdio.h
  • SDIO_IT_TXACT : stm32f10x_sdio.h
  • SDIO_IT_TXDAVL : stm32f10x_sdio.h
  • SDIO_IT_TXFIFOE : stm32f10x_sdio.h
  • SDIO_IT_TXFIFOF : stm32f10x_sdio.h
  • SDIO_IT_TXFIFOHE : stm32f10x_sdio.h
  • SDIO_IT_TXUNDERR : stm32f10x_sdio.h
  • SDIO_ITConfig() : stm32f10x_sdio.h , stm32f10x_sdio.c
  • SDIO_MASK_CCRCFAILIE : stm32f10x.h
  • SDIO_MASK_CEATAENDIE : stm32f10x.h
  • SDIO_MASK_CMDACTIE : stm32f10x.h
  • SDIO_MASK_CMDRENDIE : stm32f10x.h
  • SDIO_MASK_CMDSENTIE : stm32f10x.h
  • SDIO_MASK_CTIMEOUTIE : stm32f10x.h
  • SDIO_MASK_DATAENDIE : stm32f10x.h
  • SDIO_MASK_DBCKENDIE : stm32f10x.h
  • SDIO_MASK_DCRCFAILIE : stm32f10x.h
  • SDIO_MASK_DTIMEOUTIE : stm32f10x.h
  • SDIO_MASK_RXACTIE : stm32f10x.h
  • SDIO_MASK_RXDAVLIE : stm32f10x.h
  • SDIO_MASK_RXFIFOEIE : stm32f10x.h
  • SDIO_MASK_RXFIFOFIE : stm32f10x.h
  • SDIO_MASK_RXFIFOHFIE : stm32f10x.h
  • SDIO_MASK_RXOVERRIE : stm32f10x.h
  • SDIO_MASK_SDIOITIE : stm32f10x.h
  • SDIO_MASK_STBITERRIE : stm32f10x.h
  • SDIO_MASK_TXACTIE : stm32f10x.h
  • SDIO_MASK_TXDAVLIE : stm32f10x.h
  • SDIO_MASK_TXFIFOEIE : stm32f10x.h
  • SDIO_MASK_TXFIFOFIE : stm32f10x.h
  • SDIO_MASK_TXFIFOHEIE : stm32f10x.h
  • SDIO_MASK_TXUNDERRIE : stm32f10x.h
  • SDIO_MULTIMEDIA_CARD : stm32_eval_sdio_sd.h
  • SDIO_OFFSET : stm32f10x_sdio.c
  • SDIO_POWER_PWRCTRL : stm32f10x.h
  • SDIO_POWER_PWRCTRL_0 : stm32f10x.h
  • SDIO_POWER_PWRCTRL_1 : stm32f10x.h
  • SDIO_PowerState_OFF : stm32f10x_sdio.h
  • SDIO_PowerState_ON : stm32f10x_sdio.h
  • SDIO_ReadData() : stm32f10x_sdio.h , stm32f10x_sdio.c
  • SDIO_ReadWaitMode_CLK : stm32f10x_sdio.h
  • SDIO_ReadWaitMode_DATA2 : stm32f10x_sdio.h
  • SDIO_RESP0_CARDSTATUS0 : stm32f10x.h
  • SDIO_RESP1 : stm32f10x_sdio.h
  • SDIO_RESP1_CARDSTATUS1 : stm32f10x.h
  • SDIO_RESP2 : stm32f10x_sdio.h
  • SDIO_RESP2_CARDSTATUS2 : stm32f10x.h
  • SDIO_RESP3 : stm32f10x_sdio.h
  • SDIO_RESP3_CARDSTATUS3 : stm32f10x.h
  • SDIO_RESP4 : stm32f10x_sdio.h
  • SDIO_RESP4_CARDSTATUS4 : stm32f10x.h
  • SDIO_RESP_ADDR : stm32f10x_sdio.c
  • SDIO_RESPCMD_RESPCMD : stm32f10x.h
  • SDIO_Response_Long : stm32f10x_sdio.h
  • SDIO_Response_No : stm32f10x_sdio.h
  • SDIO_Response_Short : stm32f10x_sdio.h
  • SDIO_SECURE_DIGITAL_IO_CARD : stm32_eval_sdio_sd.h
  • SDIO_SECURE_DIGITAL_IO_COMBO_CARD : stm32_eval_sdio_sd.h
  • SDIO_SEND_IF_COND : stm32_eval_sdio_sd.c
  • SDIO_SendCEATACmd() : stm32f10x_sdio.h , stm32f10x_sdio.c
  • SDIO_SendCommand() : stm32f10x_sdio.h , stm32f10x_sdio.c
  • SDIO_SendSDIOSuspendCmd() : stm32f10x_sdio.h , stm32f10x_sdio.c
  • SDIO_SetPowerState() : stm32f10x_sdio.h , stm32f10x_sdio.c
  • SDIO_SetSDIOOperation() : stm32f10x_sdio.h , stm32f10x_sdio.c
  • SDIO_SetSDIOReadWaitMode() : stm32f10x_sdio.h , stm32f10x_sdio.c
  • SDIO_STA_CCRCFAIL : stm32f10x.h
  • SDIO_STA_CEATAEND : stm32f10x.h
  • SDIO_STA_CMDACT : stm32f10x.h
  • SDIO_STA_CMDREND : stm32f10x.h
  • SDIO_STA_CMDSENT : stm32f10x.h
  • SDIO_STA_CTIMEOUT : stm32f10x.h
  • SDIO_STA_DATAEND : stm32f10x.h
  • SDIO_STA_DBCKEND : stm32f10x.h
  • SDIO_STA_DCRCFAIL : stm32f10x.h
  • SDIO_STA_DTIMEOUT : stm32f10x.h
  • SDIO_STA_RXACT : stm32f10x.h
  • SDIO_STA_RXDAVL : stm32f10x.h
  • SDIO_STA_RXFIFOE : stm32f10x.h
  • SDIO_STA_RXFIFOF : stm32f10x.h
  • SDIO_STA_RXFIFOHF : stm32f10x.h
  • SDIO_STA_RXOVERR : stm32f10x.h
  • SDIO_STA_SDIOIT : stm32f10x.h
  • SDIO_STA_STBITERR : stm32f10x.h
  • SDIO_STA_TXACT : stm32f10x.h
  • SDIO_STA_TXDAVL : stm32f10x.h
  • SDIO_STA_TXFIFOE : stm32f10x.h
  • SDIO_STA_TXFIFOF : stm32f10x.h
  • SDIO_STA_TXFIFOHE : stm32f10x.h
  • SDIO_STA_TXUNDERR : stm32f10x.h
  • SDIO_StartSDIOReadWait() : stm32f10x_sdio.h , stm32f10x_sdio.c
  • SDIO_STATIC_FLAGS : stm32_eval_sdio_sd.c
  • SDIO_STD_CAPACITY_SD_CARD_V1_1 : stm32_eval_sdio_sd.h
  • SDIO_STD_CAPACITY_SD_CARD_V2_0 : stm32_eval_sdio_sd.h
  • SDIO_StopSDIOReadWait() : stm32f10x_sdio.h , stm32f10x_sdio.c
  • SDIO_StructInit() : stm32f10x_sdio.h , stm32f10x_sdio.c
  • SDIO_TRANSFER_CLK_DIV : stm3210e_eval.h
  • SDIO_TransferDir_ToCard : stm32f10x_sdio.h
  • SDIO_TransferDir_ToSDIO : stm32f10x_sdio.h
  • SDIO_TransferMode_Block : stm32f10x_sdio.h
  • SDIO_TransferMode_Stream : stm32f10x_sdio.h
  • SDIO_Wait_IT : stm32f10x_sdio.h
  • SDIO_Wait_No : stm32f10x_sdio.h
  • SDIO_Wait_Pend : stm32f10x_sdio.h
  • SDIO_WriteData() : stm32f10x_sdio.h , stm32f10x_sdio.c
  • SDIOEN_BitNumber : stm32f10x_sdio.c
  • SDIOSUSPEND_BitNumber : stm32f10x_sdio.c
  • SDSTATUS_Tab : stm32_eval_sdio_sd.c
  • SDTransferState : stm32_eval_sdio_sd.h
  • sEE_DeInit() : stm32_eval_i2c_ee.c , stm32_eval_i2c_ee.h , stm32l152_eval_i2c_ee.c , stm32l152_eval_i2c_ee.h
  • sEE_DIRECTION_RX : stm32100e_eval.h , stm3210c_eval.h , stm32l152_eval.h
  • sEE_DIRECTION_TX : stm32100e_eval.h , stm3210c_eval.h , stm32l152_eval.h
  • sEE_EnterCriticalSection_UserCallback() : stm32_eval_i2c_ee.c , stm32_eval_i2c_ee.h
  • sEE_ExitCriticalSection_UserCallback() : stm32_eval_i2c_ee.c , stm32_eval_i2c_ee.h
  • sEE_FAIL : stm32_eval_i2c_ee.h , stm32l152_eval_i2c_ee.h
  • sEE_FLAG_TIMEOUT : stm32_eval_i2c_ee.h , stm32l152_eval_i2c_ee.h
  • sEE_HW_ADDRESS : stm32_eval_i2c_ee.h
  • sEE_I2C : stm32100e_eval.h , stm3210c_eval.h , stm32l152_eval.h
  • sEE_I2C_CLK : stm32100e_eval.h , stm3210c_eval.h , stm32l152_eval.h
  • sEE_I2C_DMA : stm32100e_eval.h , stm3210c_eval.h , stm32l152_eval.h
  • sEE_I2C_DMA_CHANNEL_RX : stm32100e_eval.h , stm3210c_eval.h , stm32l152_eval.h
  • sEE_I2C_DMA_CHANNEL_TX : stm32100e_eval.h , stm3210c_eval.h , stm32l152_eval.h
  • sEE_I2C_DMA_CLK : stm32100e_eval.h , stm3210c_eval.h , stm32l152_eval.h
  • sEE_I2C_DMA_FLAG_RX_GL : stm32100e_eval.h , stm3210c_eval.h , stm32l152_eval.h
  • sEE_I2C_DMA_FLAG_RX_TC : stm32100e_eval.h , stm3210c_eval.h , stm32l152_eval.h
  • sEE_I2C_DMA_FLAG_TX_GL : stm32100e_eval.h , stm3210c_eval.h , stm32l152_eval.h
  • sEE_I2C_DMA_FLAG_TX_TC : stm32100e_eval.h , stm3210c_eval.h , stm32l152_eval.h
  • sEE_I2C_DMA_PREPRIO : stm32100e_eval.h , stm3210c_eval.h , stm32l152_eval.h
  • sEE_I2C_DMA_RX_IRQHandler : stm32100e_eval.h , stm3210c_eval.h , stm32l152_eval.h , stm32_eval_i2c_ee.c , stm32l152_eval_i2c_ee.c
  • sEE_I2C_DMA_RX_IRQn : stm32100e_eval.h , stm3210c_eval.h , stm32l152_eval.h
  • sEE_I2C_DMA_SUBPRIO : stm32100e_eval.h , stm3210c_eval.h , stm32l152_eval.h
  • sEE_I2C_DMA_TX_IRQHandler : stm32100e_eval.h , stm3210c_eval.h , stm32l152_eval.h , stm32_eval_i2c_ee.c , stm32l152_eval_i2c_ee.c
  • sEE_I2C_DMA_TX_IRQn : stm32100e_eval.h , stm3210c_eval.h , stm32l152_eval.h
  • sEE_I2C_DR_Address : stm32100e_eval.h , stm3210c_eval.h , stm32l152_eval.h
  • sEE_I2C_SCL_AF : stm32l152_eval.h
  • sEE_I2C_SCL_GPIO_CLK : stm32100e_eval.h , stm3210c_eval.h , stm32l152_eval.h
  • sEE_I2C_SCL_GPIO_PORT : stm32100e_eval.h , stm3210c_eval.h , stm32l152_eval.h
  • sEE_I2C_SCL_PIN : stm32100e_eval.h , stm3210c_eval.h , stm32l152_eval.h
  • sEE_I2C_SCL_SOURCE : stm32l152_eval.h
  • sEE_I2C_SDA_AF : stm32l152_eval.h
  • sEE_I2C_SDA_GPIO_CLK : stm32100e_eval.h , stm3210c_eval.h , stm32l152_eval.h
  • sEE_I2C_SDA_GPIO_PORT : stm32100e_eval.h , stm3210c_eval.h , stm32l152_eval.h
  • sEE_I2C_SDA_PIN : stm32100e_eval.h , stm3210c_eval.h , stm32l152_eval.h
  • sEE_I2C_SDA_SOURCE : stm32l152_eval.h
  • sEE_Init() : stm32_eval_i2c_ee.c , stm32_eval_i2c_ee.h , stm32l152_eval_i2c_ee.c , stm32l152_eval_i2c_ee.h
  • sEE_LONG_TIMEOUT : stm32_eval_i2c_ee.h , stm32l152_eval_i2c_ee.h
  • sEE_LowLevel_DeInit() : stm32100e_eval.c , stm32100e_eval.h , stm3210c_eval.c , stm3210c_eval.h , stm32l152_eval.c , stm32l152_eval.h
  • sEE_LowLevel_DMAConfig() : stm32100e_eval.c , stm32100e_eval.h , stm3210c_eval.c , stm3210c_eval.h , stm32l152_eval.c , stm32l152_eval.h
  • sEE_LowLevel_Init() : stm32100e_eval.c , stm32100e_eval.h , stm3210c_eval.c , stm3210c_eval.h , stm32l152_eval.c , stm32l152_eval.h
  • sEE_M24C64_32 : stm32_eval_i2c_ee.h , stm32100e_eval.h , stm3210c_eval.h , stm32l152_eval.h , stm32l152_eval_i2c_ee.h
  • sEE_MAX_TRIALS_NUMBER : stm32_eval_i2c_ee.h , stm32l152_eval_i2c_ee.h
  • sEE_OK : stm32_eval_i2c_ee.h , stm32l152_eval_i2c_ee.h
  • sEE_PAGESIZE : stm32_eval_i2c_ee.h
  • sEE_READ_ADDRESS1 : STM32F10x_StdPeriph_Examples/I2C/EEPROM/main.c
  • sEE_READ_ADDRESS2 : STM32F10x_StdPeriph_Examples/I2C/EEPROM/main.c
  • sEE_ReadBuffer() : stm32_eval_i2c_ee.c , stm32_eval_i2c_ee.h , stm32l152_eval_i2c_ee.c , stm32l152_eval_i2c_ee.h
  • sEE_STATE_BUSY : stm32_eval_i2c_ee.h , stm32l152_eval_i2c_ee.h
  • sEE_STATE_ERROR : stm32_eval_i2c_ee.h , stm32l152_eval_i2c_ee.h
  • sEE_STATE_READY : stm32_eval_i2c_ee.h , stm32l152_eval_i2c_ee.h
  • sEE_TIME_CONST : stm32100e_eval.h , stm3210c_eval.h , stm32l152_eval.h
  • sEE_TIMEOUT_UserCallback() : STM32F10x_StdPeriph_Examples/I2C/EEPROM/main.c , stm32_eval_i2c_ee.h , stm32l152_eval_i2c_ee.h
  • sEE_USE_DMA : stm32100e_eval.h , stm3210c_eval.h , stm32l152_eval.h
  • sEE_WaitEepromStandbyState() : stm32_eval_i2c_ee.c , stm32_eval_i2c_ee.h , stm32l152_eval_i2c_ee.c , stm32l152_eval_i2c_ee.h
  • sEE_WRITE_ADDRESS1 : STM32F10x_StdPeriph_Examples/I2C/EEPROM/main.c
  • sEE_WRITE_ADDRESS2 : STM32F10x_StdPeriph_Examples/I2C/EEPROM/main.c
  • sEE_WriteBuffer() : stm32_eval_i2c_ee.c , stm32_eval_i2c_ee.h , stm32l152_eval_i2c_ee.c , stm32l152_eval_i2c_ee.h
  • sEE_WritePage() : stm32_eval_i2c_ee.c , stm32_eval_i2c_ee.h , stm32l152_eval_i2c_ee.c , stm32l152_eval_i2c_ee.h
  • sEEAddress : stm32_eval_i2c_ee.c , stm32l152_eval_i2c_ee.c
  • sEEDataNum : stm32_eval_i2c_ee.c , stm32l152_eval_i2c_ee.c
  • sEEDataReadPointer : stm32_eval_i2c_ee.c , stm32l152_eval_i2c_ee.c
  • sEEDataWritePointer : stm32_eval_i2c_ee.c , stm32l152_eval_i2c_ee.c
  • sEEDMA_InitStructure : stm32100e_eval.c , stm3210c_eval.c , stm32l152_eval.c
  • sEETimeout : stm32_eval_i2c_ee.c , stm32l152_eval_i2c_ee.c
  • SEL_BUTTON_EXTI_IRQn : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210e_eval.h , stm32l152_eval.h
  • SEL_BUTTON_EXTI_LINE : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210e_eval.h , stm32l152_eval.h
  • SEL_BUTTON_EXTI_PIN_SOURCE : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210e_eval.h , stm32l152_eval.h
  • SEL_BUTTON_EXTI_PORT_SOURCE : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210e_eval.h , stm32l152_eval.h
  • SEL_BUTTON_GPIO_CLK : stm3210e_eval.h , stm32l152_eval.h , stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h
  • SEL_BUTTON_GPIO_PORT : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210e_eval.h , stm32l152_eval.h
  • SEL_BUTTON_PIN : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210e_eval.h , stm32l152_eval.h
  • send_inc : STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.c
  • SendFrame : stm32100b_eval_cec.c , stm32100e_eval_cec.c
  • SendStatus : stm32100b_eval_cec.c , stm32100e_eval_cec.c
  • SET : stm32f10x.h
  • SET_BIT : stm32f10x.h
  • SET_INDEX : stm32100b_eval_lcd.c , stm3210b_eval_lcd.c , stm3210c_eval_lcd.c , stm32l152_eval_lcd.c
  • SetSysClock() : Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/system_stm32f10x.c , STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/main.c
  • SetSysClockTo24() : STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/main.c
  • SetSysClockTo36() : STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/main.c
  • SetSysClockTo48() : STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/main.c
  • SetSysClockTo56() : Project/STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/system_stm32f10x.c , STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/main.c
  • SetSysClockTo72() : Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.c , STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/main.c
  • SetSysClockToHSE() : STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/main.c
  • SETUP_LENGHT : STM32F10x_StdPeriph_Examples/USART/Smartcard/main.c
  • SetVar_PeriodValue() : STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/main.c , RTC/LSI_Calib/main.h
  • sFLASH_CMD_BE : stm32_eval_spi_flash.h
  • sFLASH_CMD_RDID : stm32_eval_spi_flash.h
  • sFLASH_CMD_RDSR : stm32_eval_spi_flash.h
  • sFLASH_CMD_READ : stm32_eval_spi_flash.h
  • sFLASH_CMD_SE : stm32_eval_spi_flash.h
  • sFLASH_CMD_WREN : stm32_eval_spi_flash.h
  • sFLASH_CMD_WRITE : stm32_eval_spi_flash.h
  • sFLASH_CMD_WRSR : stm32_eval_spi_flash.h
  • sFLASH_CS_GPIO_CLK : stm3210b_eval.h , stm32100b_eval.h , stm32100e_eval.h , stm3210e_eval.h
  • sFLASH_CS_GPIO_PORT : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210e_eval.h
  • sFLASH_CS_HIGH : stm32_eval_spi_flash.h
  • sFLASH_CS_LOW : stm32_eval_spi_flash.h
  • sFLASH_CS_PIN : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210e_eval.h
  • sFLASH_DeInit() : stm32_eval_spi_flash.c , stm32_eval_spi_flash.h
  • sFLASH_DUMMY_BYTE : stm32_eval_spi_flash.h
  • sFLASH_EraseBulk() : stm32_eval_spi_flash.h , stm32_eval_spi_flash.c
  • sFLASH_EraseSector() : stm32_eval_spi_flash.c , stm32_eval_spi_flash.h
  • sFLASH_ID : STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/main.c
  • sFLASH_Init() : stm32_eval_spi_flash.c , stm32_eval_spi_flash.h
  • sFLASH_LowLevel_DeInit() : stm32100e_eval.c , stm32100b_eval.c , stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.c , stm3210b_eval.h , stm3210e_eval.h , stm3210e_eval.c
  • sFLASH_LowLevel_Init() : stm32100b_eval.c , stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.c , stm3210b_eval.h , stm3210e_eval.c , stm3210e_eval.h , stm32100e_eval.c
  • sFLASH_M25P128_ID : stm32_eval_spi_flash.h
  • sFLASH_M25P64_ID : stm32_eval_spi_flash.h
  • sFLASH_ReadBuffer() : stm32_eval_spi_flash.h , stm32_eval_spi_flash.c
  • sFLASH_ReadByte() : stm32_eval_spi_flash.c , stm32_eval_spi_flash.h
  • sFLASH_ReadID() : stm32_eval_spi_flash.h , stm32_eval_spi_flash.c
  • sFLASH_SendByte() : stm32_eval_spi_flash.c , stm32_eval_spi_flash.h
  • sFLASH_SendHalfWord() : stm32_eval_spi_flash.h , stm32_eval_spi_flash.c
  • sFLASH_SPI : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210e_eval.h
  • sFLASH_SPI_CLK : stm32100b_eval.h , stm32100e_eval.h , stm3210e_eval.h , stm3210b_eval.h
  • sFLASH_SPI_MISO_GPIO_CLK : stm32100b_eval.h , stm32100e_eval.h , stm3210e_eval.h , stm3210b_eval.h
  • sFLASH_SPI_MISO_GPIO_PORT : stm32100b_eval.h , stm32100e_eval.h , stm3210e_eval.h , stm3210b_eval.h
  • sFLASH_SPI_MISO_PIN : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210e_eval.h
  • sFLASH_SPI_MOSI_GPIO_CLK : stm32100b_eval.h , stm32100e_eval.h , stm3210e_eval.h , stm3210b_eval.h
  • sFLASH_SPI_MOSI_GPIO_PORT : stm32100b_eval.h , stm32100e_eval.h , stm3210e_eval.h , stm3210b_eval.h
  • sFLASH_SPI_MOSI_PIN : stm32100b_eval.h , stm32100e_eval.h , stm3210e_eval.h , stm3210b_eval.h
  • sFLASH_SPI_PAGESIZE : stm32_eval_spi_flash.h
  • sFLASH_SPI_SCK_GPIO_CLK : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210e_eval.h
  • sFLASH_SPI_SCK_GPIO_PORT : stm32100b_eval.h , stm3210b_eval.h , stm3210e_eval.h , stm32100e_eval.h
  • sFLASH_SPI_SCK_PIN : stm32100b_eval.h , stm3210b_eval.h , stm3210e_eval.h , stm32100e_eval.h
  • sFLASH_StartReadSequence() : stm32_eval_spi_flash.c , stm32_eval_spi_flash.h
  • sFLASH_WaitForWriteEnd() : stm32_eval_spi_flash.c , stm32_eval_spi_flash.h
  • sFLASH_WIP_FLAG : stm32_eval_spi_flash.h
  • sFLASH_WriteBuffer() : stm32_eval_spi_flash.c , stm32_eval_spi_flash.h
  • sFLASH_WriteEnable() : stm32_eval_spi_flash.c , stm32_eval_spi_flash.h
  • sFLASH_WritePage() : stm32_eval_spi_flash.h , stm32_eval_spi_flash.c
  • sFONT : fonts.h
  • shift : stm32l152_eval_glass_lcd.c
  • Sine12bit : STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/main.c
  • SLAK_TIMEOUT : stm32f10x_can.c
  • SMbusAlertOccurred : STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/main.c , STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/stm32f10x_it.c
  • SMCR_ETR_Mask : stm32f10x_tim.c
  • SMPR1_SMP_Set : stm32f10x_adc.c
  • SMPR2_SMP_Set : stm32f10x_adc.c
  • SP_MAIN : STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/main.c
  • SP_PROCESS : STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/main.c
  • SP_PROCESS_SIZE : STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/main.c
  • SPI1 : stm32f10x.h
  • SPI1_BASE : stm32f10x.h
  • SPI1_Buffer_Rx : STM32F10x_StdPeriph_Examples/SPI/CRC/main.c
  • SPI1_Buffer_Tx : STM32F10x_StdPeriph_Examples/SPI/CRC/main.c
  • SPI1_DBG : stm32f10x_ip_dbg.c
  • SPI1_IRQHandler() : STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.h
  • SPI2 : stm32f10x.h
  • SPI2_BASE : stm32f10x.h
  • SPI2_Buffer_Rx : STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/main.c , STM32F10x_StdPeriph_Examples/SPI/CRC/main.c
  • SPI2_Buffer_Tx : STM32F10x_StdPeriph_Examples/SPI/CRC/main.c
  • SPI2_DBG : stm32f10x_ip_dbg.c
  • SPI2_IRQHandler() : STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.h
  • SPI3 : stm32f10x.h
  • SPI3_BASE : stm32f10x.h
  • SPI3_Buffer_Tx : STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/main.c
  • SPI3_DBG : stm32f10x_ip_dbg.c
  • SPI3_IRQHandler() : STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_it.h
  • SPI_BaudRatePrescaler_128 : stm32f10x_spi.h
  • SPI_BaudRatePrescaler_16 : stm32f10x_spi.h
  • SPI_BaudRatePrescaler_2 : stm32f10x_spi.h
  • SPI_BaudRatePrescaler_256 : stm32f10x_spi.h
  • SPI_BaudRatePrescaler_32 : stm32f10x_spi.h
  • SPI_BaudRatePrescaler_4 : stm32f10x_spi.h
  • SPI_BaudRatePrescaler_64 : stm32f10x_spi.h
  • SPI_BaudRatePrescaler_8 : stm32f10x_spi.h
  • SPI_BiDirectionalLineConfig() : stm32f10x_spi.h , stm32f10x_spi.c
  • SPI_CalculateCRC() : stm32f10x_spi.c , stm32f10x_spi.h
  • SPI_Cmd() : stm32f10x_spi.h , stm32f10x_spi.c
  • SPI_Configuration() : STM32F10x_StdPeriph_Examples/USART/Synchronous/main.c
  • SPI_CPHA_1Edge : stm32f10x_spi.h
  • SPI_CPHA_2Edge : stm32f10x_spi.h
  • SPI_CPOL_High : stm32f10x_spi.h
  • SPI_CPOL_Low : stm32f10x_spi.h
  • SPI_CR1_BIDIMODE : stm32f10x.h
  • SPI_CR1_BIDIOE : stm32f10x.h
  • SPI_CR1_BR : stm32f10x.h
  • SPI_CR1_BR_0 : stm32f10x.h
  • SPI_CR1_BR_1 : stm32f10x.h
  • SPI_CR1_BR_2 : stm32f10x.h
  • SPI_CR1_CPHA : stm32f10x.h
  • SPI_CR1_CPOL : stm32f10x.h
  • SPI_CR1_CRCEN : stm32f10x.h
  • SPI_CR1_CRCNEXT : stm32f10x.h
  • SPI_CR1_DFF : stm32f10x.h
  • SPI_CR1_LSBFIRST : stm32f10x.h
  • SPI_CR1_MSTR : stm32f10x.h
  • SPI_CR1_RXONLY : stm32f10x.h
  • SPI_CR1_SPE : stm32f10x.h
  • SPI_CR1_SSI : stm32f10x.h
  • SPI_CR1_SSM : stm32f10x.h
  • SPI_CR2_ERRIE : stm32f10x.h
  • SPI_CR2_RXDMAEN : stm32f10x.h
  • SPI_CR2_RXNEIE : stm32f10x.h
  • SPI_CR2_SSOE : stm32f10x.h
  • SPI_CR2_TXDMAEN : stm32f10x.h
  • SPI_CR2_TXEIE : stm32f10x.h
  • SPI_CRC_Rx : stm32f10x_spi.h
  • SPI_CRC_Tx : stm32f10x_spi.h
  • SPI_CRCPR_CRCPOLY : stm32f10x.h
  • SPI_DataSize_16b : stm32f10x_spi.h
  • SPI_DataSize_8b : stm32f10x_spi.h
  • SPI_DataSizeConfig() : stm32f10x_spi.h , stm32f10x_spi.c
  • SPI_Direction_1Line_Rx : stm32f10x_spi.h
  • SPI_Direction_1Line_Tx : stm32f10x_spi.h
  • SPI_Direction_2Lines_FullDuplex : stm32f10x_spi.h
  • SPI_Direction_2Lines_RxOnly : stm32f10x_spi.h
  • SPI_Direction_Rx : stm32f10x_spi.h
  • SPI_Direction_Tx : stm32f10x_spi.h
  • SPI_DR_DR : stm32f10x.h
  • SPI_FirstBit_LSB : stm32f10x_spi.h
  • SPI_FirstBit_MSB : stm32f10x_spi.h
  • SPI_FLAG_CRCERR : stm32f10x_spi.h
  • SPI_FLAG_MODF : stm32f10x_spi.h
  • SPI_GetCRC() : stm32f10x_spi.h , stm32f10x_spi.c
  • SPI_GetCRCPolynomial() : stm32f10x_spi.c , stm32f10x_spi.h
  • SPI_I2S_ClearFlag() : stm32f10x_spi.h , stm32f10x_spi.c
  • SPI_I2S_ClearITPendingBit() : stm32f10x_spi.c , stm32f10x_spi.h
  • SPI_I2S_DeInit() : stm32f10x_spi.h , stm32f10x_spi.c
  • SPI_I2S_DMACmd() : stm32f10x_spi.h , stm32f10x_spi.c
  • SPI_I2S_DMAReq_Rx : stm32f10x_spi.h
  • SPI_I2S_DMAReq_Tx : stm32f10x_spi.h
  • SPI_I2S_FLAG_BSY : stm32f10x_spi.h
  • SPI_I2S_FLAG_OVR : stm32f10x_spi.h
  • SPI_I2S_FLAG_RXNE : stm32f10x_spi.h
  • SPI_I2S_FLAG_TXE : stm32f10x_spi.h
  • SPI_I2S_GetFlagStatus() : stm32f10x_spi.c , stm32f10x_spi.h
  • SPI_I2S_GetITStatus() : stm32f10x_spi.h , stm32f10x_spi.c
  • SPI_I2S_IT_ERR : stm32f10x_spi.h
  • SPI_I2S_IT_OVR : stm32f10x_spi.h
  • SPI_I2S_IT_RXNE : stm32f10x_spi.h
  • SPI_I2S_IT_TXE : stm32f10x_spi.h
  • SPI_I2S_ITConfig() : stm32f10x_spi.h , stm32f10x_spi.c
  • SPI_I2S_ReceiveData() : stm32f10x_spi.h , stm32f10x_spi.c
  • SPI_I2S_SendData() : stm32f10x_spi.c , stm32f10x_spi.h
  • SPI_I2SCFGR_CHLEN : stm32f10x.h
  • SPI_I2SCFGR_CKPOL : stm32f10x.h
  • SPI_I2SCFGR_DATLEN : stm32f10x.h
  • SPI_I2SCFGR_DATLEN_0 : stm32f10x.h
  • SPI_I2SCFGR_DATLEN_1 : stm32f10x.h
  • SPI_I2SCFGR_I2SCFG : stm32f10x.h
  • SPI_I2SCFGR_I2SCFG_0 : stm32f10x.h
  • SPI_I2SCFGR_I2SCFG_1 : stm32f10x.h
  • SPI_I2SCFGR_I2SE : stm32f10x.h
  • SPI_I2SCFGR_I2SMOD : stm32f10x.h
  • SPI_I2SCFGR_I2SSTD : stm32f10x.h
  • SPI_I2SCFGR_I2SSTD_0 : stm32f10x.h
  • SPI_I2SCFGR_I2SSTD_1 : stm32f10x.h
  • SPI_I2SCFGR_PCMSYNC : stm32f10x.h
  • SPI_I2SPR_I2SDIV : stm32f10x.h
  • SPI_I2SPR_MCKOE : stm32f10x.h
  • SPI_I2SPR_ODD : stm32f10x.h
  • SPI_Init() : stm32f10x_spi.h , stm32f10x_spi.c
  • SPI_InitStructure : STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/main.c , STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/main.c , STM32F10x_StdPeriph_Examples/SPI/CRC/main.c , STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/main.c , STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/main.c , STM32F10x_StdPeriph_Examples/SPI/DMA/main.c
  • SPI_IT_CRCERR : stm32f10x_spi.h
  • SPI_IT_MODF : stm32f10x_spi.h
  • SPI_MASTER_Buffer_Rx : STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/main.c
  • SPI_MASTER_Buffer_Tx : STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/main.c , STM32F10x_StdPeriph_Examples/SPI/DMA/main.c , STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/main.c
  • SPI_MASTERCRCValue : STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/main.c
  • SPI_Mode_Master : stm32f10x_spi.h
  • SPI_Mode_Select : stm32f10x_spi.c
  • SPI_Mode_Slave : stm32f10x_spi.h
  • SPI_NSS_Hard : stm32f10x_spi.h
  • SPI_NSS_Soft : stm32f10x_spi.h
  • SPI_NSSInternalSoft_Reset : stm32f10x_spi.h
  • SPI_NSSInternalSoft_Set : stm32f10x_spi.h
  • SPI_NSSInternalSoftwareConfig() : stm32f10x_spi.h , stm32f10x_spi.c
  • SPI_RXCRCR_RXCRC : stm32f10x.h
  • SPI_SLAVE_Buffer_Rx : STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/main.c , STM32F10x_StdPeriph_Examples/SPI/DMA/main.c , STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/main.c , STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.c
  • SPI_SLAVE_Buffer_Tx : STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/main.c
  • SPI_SLAVECRCValue : STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/main.c
  • SPI_SR_BSY : stm32f10x.h
  • SPI_SR_CHSIDE : stm32f10x.h
  • SPI_SR_CRCERR : stm32f10x.h
  • SPI_SR_MODF : stm32f10x.h
  • SPI_SR_OVR : stm32f10x.h
  • SPI_SR_RXNE : stm32f10x.h
  • SPI_SR_TXE : stm32f10x.h
  • SPI_SR_UDR : stm32f10x.h
  • SPI_SSOutputCmd() : stm32f10x_spi.h , stm32f10x_spi.c
  • SPI_StructInit() : stm32f10x_spi.h , stm32f10x_spi.c
  • SPI_TransmitCRC() : stm32f10x_spi.h , stm32f10x_spi.c
  • SPI_TXCRCR_TXCRC : stm32f10x.h
  • SPIy_Buffer_Rx : STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/main.c
  • SPIy_Buffer_Tx : STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/main.c
  • SPIz_Buffer_Rx : STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/main.c
  • SPIz_Buffer_Tx : STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/main.c
  • SQR1_CLEAR_Mask : stm32f10x_adc.c
  • SQR1_SQ_Set : stm32f10x_adc.c
  • SQR2_SQ_Set : stm32f10x_adc.c
  • SQR3_SQ_Set : stm32f10x_adc.c
  • SRAM_BASE : stm32f10x.h
  • SRAM_BB_BASE : stm32f10x.h
  • SRAM_Init() : stm32100e_eval_fsmc_sram.c , stm32100e_eval_fsmc_sram.h , stm3210e_eval_fsmc_sram.c , stm3210e_eval_fsmc_sram.h
  • SRAM_ReadBuffer() : stm32100e_eval_fsmc_sram.h , stm3210e_eval_fsmc_sram.c , stm3210e_eval_fsmc_sram.h , stm32100e_eval_fsmc_sram.c
  • SRAM_WriteBuffer() : stm32100e_eval_fsmc_sram.h , stm3210e_eval_fsmc_sram.c , stm3210e_eval_fsmc_sram.h , stm32100e_eval_fsmc_sram.c
  • SRC_Buffer : STM32F10x_StdPeriph_Examples/TIM/DMA/main.c , STM32F10x_StdPeriph_Examples/TIM/DMABurst/main.c , STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_it.c
  • SRC_Const_Buffer : STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/main.c , STM32F10x_StdPeriph_Examples/DMA/FSMC/main.c
  • START_BYTE : stm32100b_eval_lcd.c , stm3210b_eval_lcd.c , stm3210c_eval_lcd.c , stm32l152_eval_lcd.c
  • status : STM32F10x_StdPeriph_Examples/FSMC/NAND/main.c
  • Status : STM32F10x_StdPeriph_Examples/FSMC/OneNAND/main.c , STM32F10x_StdPeriph_Examples/SDIO/uSDCard/main.c
  • step : STM32F10x_StdPeriph_Examples/TIM/6Steps/stm32f10x_it.c
  • STM32100B_LCD_Init() : stm32100b_eval_lcd.c , stm32100b_eval_lcd.h
  • STM32100E_LCD_Init() : stm32100e_eval_lcd.c , stm32100e_eval_lcd.h
  • STM3210B_LCD_Init() : stm3210b_eval_lcd.c , stm3210b_eval_lcd.h
  • STM3210C_LCD_Init() : stm3210c_eval_lcd.h , stm3210c_eval_lcd.c
  • STM3210E_LCD_Init() : stm3210e_eval_lcd.c , stm3210e_eval_lcd.h
  • STM32L152_LCD_DeInit() : stm32l152_eval_lcd.c , stm32l152_eval_lcd.h
  • STM32L152_LCD_Init() : stm32l152_eval_lcd.h , stm32l152_eval_lcd.c
  • STM_EVAL_COMInit() : stm3210e_eval.h , stm3210b_eval.h , stm32100b_eval.c , stm32100e_eval.c , stm3210c_eval.c , stm3210c_eval.h , stm3210e_eval.c , stm32l152_eval.c , stm32100e_eval.h , stm3210b_eval.c , stm32100b_eval.h , stm32l152_eval.h
  • STM_EVAL_LEDInit() : stm3210e_eval.h , stm32100b_eval.h , stm3210b_eval.c , stm3210c_eval.c , stm32100e_eval.c , stm32l152_eval.c , stm32l152_eval.h , stm32100b_eval.c , stm32100e_eval.h , stm3210c_eval.h , stm3210e_eval.c , stm3210b_eval.h
  • STM_EVAL_LEDOff() : stm3210c_eval.h , stm32100b_eval.h , stm3210b_eval.h , stm3210b_eval.c , stm32100b_eval.c , stm32100e_eval.c , stm3210c_eval.c , stm3210e_eval.c , stm32l152_eval.c , stm32100e_eval.h , stm32l152_eval.h , stm3210e_eval.h
  • STM_EVAL_LEDOn() : stm3210b_eval.h , stm3210e_eval.h , stm32100b_eval.h , stm3210b_eval.c , stm32100e_eval.c , stm32100e_eval.h , stm3210c_eval.c , stm32l152_eval.c , stm32100b_eval.c , stm3210c_eval.h , stm3210e_eval.c , stm32l152_eval.h
  • STM_EVAL_LEDToggle() : stm3210e_eval.h , stm3210b_eval.h , stm32l152_eval.h , stm32100b_eval.c , stm32100e_eval.c , stm3210c_eval.c , stm3210c_eval.h , stm3210e_eval.c , stm32l152_eval.c , stm32100e_eval.h , stm3210b_eval.c , stm32100b_eval.h
  • STM_EVAL_PBGetState() : stm32100b_eval.h , stm32100e_eval.h , stm3210e_eval.h , stm32100b_eval.c , stm32100e_eval.c , stm3210b_eval.c , stm3210c_eval.c , stm32l152_eval.c , stm32l152_eval.h , stm3210c_eval.h , stm3210e_eval.c , stm3210b_eval.h
  • STM_EVAL_PBInit() : stm32100b_eval.h , stm3210b_eval.h , stm3210e_eval.c , stm32100b_eval.c , stm32100e_eval.c , stm3210c_eval.c , stm32l152_eval.c , stm32100e_eval.h , stm3210b_eval.c , stm3210c_eval.h , stm32l152_eval.h , stm3210e_eval.h
  • STMPE811_ID : stm3210c_eval_ioe.h , stm32100e_eval_ioe.h
  • StopCondition : stm32_eval_sdio_sd.c
  • SUCCESS : stm32f10x.h
  • SVC_Handler() : STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2C/EEPROM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/GPIO/IOToggle/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2C/IOExpander/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2C/EEPROM/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/SRAM/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/NOR/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/NOR/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/FSMC/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CortexM3/MPU/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CortexM3/MPU/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/BKP/Backup_Data/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/BKP/Backup_Data/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/DMA/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SPI/CRC/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/PWR/STANDBY/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/PWR/PVD/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2C/IOExpander/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/SRAM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/FSMC/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/BKP/Tamper/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/BKP/Tamper/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CortexM3/BitBand/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FLASH/Program/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/NAND/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/OneNAND/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/GPIO/IOToggle/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/PWR/PVD/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/RTC/Calendar/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SDIO/uSDCard/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SDIO/uSDCard/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/DMA/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/RTC/Calendar/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SysTick/TimeBase/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/DMABurst/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SPI/DMA/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/OCInactive/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/OCInactive/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/OnePulse/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/PWM_Input/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/PWM_Output/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SysTick/TimeBase/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Polling/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/DMA_Polling/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/HalfDuplex/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/stm32f10x_it.c , STM32F10x_StdPeriph_Template/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Polling/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Printf/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Synchronous/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_it.c , STM32F10x_StdPeriph_Template/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Printf/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Synchronous/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/MultiProcessor/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/OnePulse/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/DMA_Polling/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/MultiProcessor/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/HalfDuplex/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/PWM_Input/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/PWR/STANDBY/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/PWM_Output/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/DMABurst/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/OCActive/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CortexM3/BitBand/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/OCActive/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/DMA/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/6Steps/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/6Steps/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FLASH/Program/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/CRC/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/NAND/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/OneNAND/stm32f10x_it.h
  • SVCall_IRQn : stm32f10x.h
  • SYSCLK_FREQ_24MHz : RCC/RCC_ClockConfig/main.h
  • SYSCLK_FREQ_56MHz : Project/STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/system_stm32f10x.c
  • SYSCLK_FREQ_72MHz : Project/STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/DMA/FSMC/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/I2S/Interrupt/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/FSMC/NAND/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/FLASH/Program/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/CAN/LoopBack/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/Smartcard/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/TimeBase/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/Synchronous/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/Polling/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/RTC/Calendar/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/Interrupt/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/DMA_Polling/system_stm32f10x.c , RCC/RCC_ClockConfig/main.h , Project/STM32F10x_StdPeriph_Examples/USART/HalfDuplex/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/SPI/DMA/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/PWR/STOP/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Input/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/SDIO/uSDCard/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/SysTick/TimeBase/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/OCInactive/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/DMA/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/OCActive/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/6Steps/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/InputCapture/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/PWR/STANDBY/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/DMABurst/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/OnePulse/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/CortexM3/BitBand/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/CortexM3/MPU/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/CAN/DualCAN/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/BKP/Backup_Data/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/CAN/Networking/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/FSMC/OneNAND/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/PWR/PVD/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/SPI/CRC/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/OCToggle/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Output/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/MultiProcessor/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Template/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/system_stm32f10x.c , Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/GPIO/IOToggle/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/BKP/Tamper/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/Printf/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/I2C/IOExpander/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/I2C/EEPROM/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/FSMC/NOR/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/system_stm32f10x.c
  • SYSCLKConfig_STOP() : STM32F10x_StdPeriph_Examples/PWR/STOP/main.c
  • SystemCoreClock : Project/STM32F10x_StdPeriph_Examples/TIM/6Steps/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/SPI/DMA/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/RTC/Calendar/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/PWR/STOP/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/PWR/STANDBY/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/PWR/PVD/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/FSMC/NAND/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/I2C/IOExpander/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/OCToggle/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Output/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/FLASH/Program/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/DMA/FSMC/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/CortexM3/MPU/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/CortexM3/BitBand/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/CAN/LoopBack/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/BKP/Backup_Data/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/CAN/Networking/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/BKP/Tamper/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/MultiProcessor/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/system_stm32f10x.c , system_stm32f10x.h , Project/STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/I2S/Interrupt/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/Synchronous/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/Polling/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/SDIO/uSDCard/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Template/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/FSMC/NOR/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/I2C/EEPROM/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/DMABurst/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/DMA/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Input/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/FSMC/OneNAND/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/InputCapture/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/Interrupt/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/HalfDuplex/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/TimeBase/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/OCInactive/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/GPIO/IOToggle/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/system_stm32f10x.c , Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/CAN/DualCAN/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/SPI/CRC/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/DMA_Polling/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/Smartcard/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/Printf/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/OnePulse/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/OCActive/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/SysTick/TimeBase/system_stm32f10x.c
  • SystemCoreClockUpdate() : system_stm32f10x.h , Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.c
  • SystemInit() : Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.c , system_stm32f10x.h
  • SysTick_CALIB_NOREF : stm32f10x.h
  • SysTick_CALIB_SKEW : stm32f10x.h
  • SysTick_CALIB_TENMS : stm32f10x.h
  • SysTick_CLKSource_HCLK : misc.h
  • SysTick_CLKSource_HCLK_Div8 : misc.h
  • SysTick_CLKSourceConfig() : misc.c , misc.h
  • SysTick_Configuration() : STM32F10x_StdPeriph_Examples/PWR/STOP/main.c , STM32F10x_StdPeriph_Examples/PWR/STANDBY/main.c , STM32F10x_StdPeriph_Examples/TIM/6Steps/main.c
  • SysTick_CTRL_CLKSOURCE : stm32f10x.h
  • SysTick_CTRL_COUNTFLAG : stm32f10x.h
  • SysTick_CTRL_ENABLE : stm32f10x.h
  • SysTick_CTRL_TICKINT : stm32f10x.h
  • SysTick_DBG : stm32f10x_ip_dbg.c
  • SysTick_Handler() : STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/DMABurst/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/NAND/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SPI/DMA/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CortexM3/MPU/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/6Steps/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/DMA_Polling/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/PWM_Output/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/PWR/PVD/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/OCInactive/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/MultiProcessor/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/OneNAND/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SPI/CRC/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FLASH/Program/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Printf/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/MultiProcessor/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/PWR/STANDBY/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/PWM_Input/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/HalfDuplex/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/OCInactive/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/OneNAND/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Printf/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/PWR/STANDBY/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2C/IOExpander/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/OCActive/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/BKP/Backup_Data/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/HalfDuplex/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/OCActive/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SysTick/TimeBase/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SysTick/TimeBase/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/NAND/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CortexM3/BitBand/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/CRC/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/DMA/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/BKP/Tamper/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CortexM3/BitBand/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/6Steps/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/SRAM/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Polling/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/stm32f10x_it.c , STM32F10x_StdPeriph_Template/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/OnePulse/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/PWM_Input/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/DMA/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/GPIO/IOToggle/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FLASH/Program/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/SRAM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SDIO/uSDCard/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/OnePulse/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Polling/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/RTC/Calendar/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/DMA/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/GPIO/IOToggle/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/NOR/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Synchronous/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/PWM_Output/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2C/EEPROM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/BKP/Backup_Data/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/RTC/Calendar/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2C/EEPROM/stm32f10x_it.h , STM32F10x_StdPeriph_Template/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SDIO/uSDCard/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/FSMC/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/DMA_Polling/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/DMABurst/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CortexM3/MPU/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Synchronous/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/NOR/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/FSMC/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/PWR/PVD/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/BKP/Tamper/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_it.c
  • SysTick_IRQn : stm32f10x.h
  • SysTick_LOAD_RELOAD : stm32f10x.h
  • SysTick_VAL_CURRENT : stm32f10x.h


STM32F10x Standard Peripherals Firmware Library: Globals

  • File List
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  • Variables
  • Typedefs
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  • f
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  • h
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- t -

  • T0_PROTOCOL : STM32F10x_StdPeriph_Examples/USART/Smartcard/main.c
  • Tab : STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/main.c
  • TabAddr : STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/main.c
  • TAMPER_BUTTON_EXTI_IRQn : stm32100b_eval.h , stm3210e_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210c_eval.h
  • TAMPER_BUTTON_EXTI_LINE : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210c_eval.h , stm3210e_eval.h
  • TAMPER_BUTTON_EXTI_PIN_SOURCE : stm3210b_eval.h , stm3210c_eval.h , stm3210e_eval.h , stm32100b_eval.h , stm32100e_eval.h
  • TAMPER_BUTTON_EXTI_PORT_SOURCE : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210c_eval.h , stm3210e_eval.h
  • TAMPER_BUTTON_GPIO_CLK : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210c_eval.h , stm3210e_eval.h
  • TAMPER_BUTTON_GPIO_PORT : stm3210c_eval.h , stm3210e_eval.h , stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h
  • TAMPER_BUTTON_PIN : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210c_eval.h , stm3210e_eval.h
  • TAMPER_IRQHandler() : STM32F10x_StdPeriph_Examples/BKP/Tamper/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/BKP/Tamper/stm32f10x_it.h
  • TAMPER_IRQn : stm32f10x.h
  • TEF_BitNumber : stm32f10x_bkp.c
  • TempCelsiusDisplay : STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/main.c
  • TEMPERATURE_THYS : STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/main.c
  • TEMPERATURE_TOS : STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/main.c
  • TempFahrenheitDisplay : STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/main.c
  • TempValue : STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/main.c
  • TempValueCelsius : STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/main.c
  • TempValueFahrenheit : STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/main.c
  • TEOM_BitNumber : stm32f10x_cec.c
  • TestRx : STM32F10x_StdPeriph_Examples/CAN/LoopBack/main.c
  • TestStatus : STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/main.c , STM32F10x_StdPeriph_Examples/SDIO/uSDCard/main.c , STM32F10x_StdPeriph_Examples/SPI/CRC/main.c , STM32F10x_StdPeriph_Examples/SPI/DMA/main.c , STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/main.c , STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/main.c , STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/main.c , STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/main.c , STM32F10x_StdPeriph_Examples/USART/DMA_Polling/main.c , STM32F10x_StdPeriph_Examples/USART/HalfDuplex/main.c , STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c , STM32F10x_StdPeriph_Examples/USART/Polling/main.c , STM32F10x_StdPeriph_Examples/USART/Smartcard/main.c , STM32F10x_StdPeriph_Examples/USART/Synchronous/main.c , STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CAN/LoopBack/main.c , STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/main.c , STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/main.c , STM32F10x_StdPeriph_Examples/DMA/FSMC/main.c , STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/main.c , STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/main.c , STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/main.c , STM32F10x_StdPeriph_Examples/FLASH/Program/main.c , STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/main.c , STM32F10x_StdPeriph_Examples/I2C/EEPROM/main.c , STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/main.c , STM32F10x_StdPeriph_Examples/I2S/Interrupt/main.c
  • TextColor : stm32100b_eval_lcd.c , stm32100e_eval_lcd.c , stm3210b_eval_lcd.c , stm3210c_eval_lcd.c , stm3210e_eval_lcd.c , stm32l152_eval_lcd.c
  • THREAD_MODE_PRIVILEGED : STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/main.c
  • THREAD_MODE_UNPRIVILEGED : STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/main.c
  • ThreadMode : STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/main.c
  • TI1_Config() : stm32f10x_tim.c
  • TI2_Config() : stm32f10x_tim.c
  • TI3_Config() : stm32f10x_tim.c
  • TI4_Config() : stm32f10x_tim.c
  • TIF_BitNumber : stm32f10x_bkp.c
  • TIM1 : stm32f10x.h
  • TIM10 : stm32f10x.h
  • TIM10_BASE : stm32f10x.h
  • TIM11 : stm32f10x.h
  • TIM11_BASE : stm32f10x.h
  • TIM12 : stm32f10x.h
  • TIM12_BASE : stm32f10x.h
  • TIM13 : stm32f10x.h
  • TIM13_BASE : stm32f10x.h
  • TIM14 : stm32f10x.h
  • TIM14_BASE : stm32f10x.h
  • TIM15 : stm32f10x.h
  • TIM15_BASE : stm32f10x.h
  • TIM15_DBG : stm32f10x_ip_dbg.c
  • TIM16 : stm32f10x.h
  • TIM16_BASE : stm32f10x.h
  • TIM16_DBG : stm32f10x_ip_dbg.c
  • TIM17 : stm32f10x.h
  • TIM17_BASE : stm32f10x.h
  • TIM17_DBG : stm32f10x_ip_dbg.c
  • TIM1_BASE : stm32f10x.h
  • TIM1_BRK_TIM9_IRQHandler() : STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_it.c
  • TIM1_CCR1_Address : STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/main.c
  • TIM1_CCR3_Address : STM32F10x_StdPeriph_Examples/TIM/DMA/main.c
  • TIM1_DBG : stm32f10x_ip_dbg.c
  • TIM1_DMAR_ADDRESS : STM32F10x_StdPeriph_Examples/TIM/DMABurst/main.c
  • TIM1_TRG_COM_IRQHandler() : STM32F10x_StdPeriph_Examples/TIM/6Steps/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/6Steps/stm32f10x_it.h
  • TIM2 : stm32f10x.h
  • TIM2_BASE : stm32f10x.h
  • TIM2_DBG : stm32f10x_ip_dbg.c
  • TIM2_IRQHandler() : STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/OCInactive/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/OCInactive/stm32f10x_it.h
  • TIM3 : stm32f10x.h
  • TIM3_BASE : stm32f10x.h
  • TIM3_DBG : stm32f10x_ip_dbg.c
  • TIM3_IRQHandler() : STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/PWM_Input/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/PWM_Input/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_it.h
  • TIM3Freq : STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_it.c
  • TIM4 : stm32f10x.h
  • TIM4_BASE : stm32f10x.h
  • TIM4_DBG : stm32f10x_ip_dbg.c
  • TIM4_IRQHandler() : STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_it.h
  • TIM5 : stm32f10x.h
  • TIM5_BASE : stm32f10x.h
  • TIM5_ConfigForLSI() : STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/main.c
  • TIM5_DBG : stm32f10x_ip_dbg.c
  • TIM5_IRQHandler() : STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_it.h
  • TIM6 : stm32f10x.h
  • TIM6_BASE : stm32f10x.h
  • TIM6_DBG : stm32f10x_ip_dbg.c
  • TIM7 : stm32f10x.h
  • TIM7_BASE : stm32f10x.h
  • TIM7_DBG : stm32f10x_ip_dbg.c
  • TIM8 : stm32f10x.h
  • TIM8_BASE : stm32f10x.h
  • TIM8_DBG : stm32f10x_ip_dbg.c
  • TIM9 : stm32f10x.h
  • TIM9_BASE : stm32f10x.h
  • TIM_ARR_ARR : stm32f10x.h
  • TIM_ARRPreloadConfig() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_AutomaticOutput_Disable : stm32f10x_tim.h
  • TIM_AutomaticOutput_Enable : stm32f10x_tim.h
  • TIM_BDTR_AOE : stm32f10x.h
  • TIM_BDTR_BKE : stm32f10x.h
  • TIM_BDTR_BKP : stm32f10x.h
  • TIM_BDTR_DTG : stm32f10x.h
  • TIM_BDTR_DTG_0 : stm32f10x.h
  • TIM_BDTR_DTG_1 : stm32f10x.h
  • TIM_BDTR_DTG_2 : stm32f10x.h
  • TIM_BDTR_DTG_3 : stm32f10x.h
  • TIM_BDTR_DTG_4 : stm32f10x.h
  • TIM_BDTR_DTG_5 : stm32f10x.h
  • TIM_BDTR_DTG_6 : stm32f10x.h
  • TIM_BDTR_DTG_7 : stm32f10x.h
  • TIM_BDTR_LOCK : stm32f10x.h
  • TIM_BDTR_LOCK_0 : stm32f10x.h
  • TIM_BDTR_LOCK_1 : stm32f10x.h
  • TIM_BDTR_MOE : stm32f10x.h
  • TIM_BDTR_OSSI : stm32f10x.h
  • TIM_BDTR_OSSR : stm32f10x.h
  • TIM_BDTRConfig() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_BDTRInitStructure : STM32F10x_StdPeriph_Examples/TIM/6Steps/main.c , STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/main.c , STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/main.c , STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/main.c
  • TIM_BDTRStructInit() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_Break_Disable : stm32f10x_tim.h
  • TIM_Break_Enable : stm32f10x_tim.h
  • TIM_BreakPolarity_High : stm32f10x_tim.h
  • TIM_BreakPolarity_Low : stm32f10x_tim.h
  • TIM_CCER_CC1E : stm32f10x.h
  • TIM_CCER_CC1NE : stm32f10x.h
  • TIM_CCER_CC1NP : stm32f10x.h
  • TIM_CCER_CC1P : stm32f10x.h
  • TIM_CCER_CC2E : stm32f10x.h
  • TIM_CCER_CC2NE : stm32f10x.h
  • TIM_CCER_CC2NP : stm32f10x.h
  • TIM_CCER_CC2P : stm32f10x.h
  • TIM_CCER_CC3E : stm32f10x.h
  • TIM_CCER_CC3NE : stm32f10x.h
  • TIM_CCER_CC3NP : stm32f10x.h
  • TIM_CCER_CC3P : stm32f10x.h
  • TIM_CCER_CC4E : stm32f10x.h
  • TIM_CCER_CC4NP : stm32f10x.h
  • TIM_CCER_CC4P : stm32f10x.h
  • TIM_CCMR1_CC1S : stm32f10x.h
  • TIM_CCMR1_CC1S_0 : stm32f10x.h
  • TIM_CCMR1_CC1S_1 : stm32f10x.h
  • TIM_CCMR1_CC2S : stm32f10x.h
  • TIM_CCMR1_CC2S_0 : stm32f10x.h
  • TIM_CCMR1_CC2S_1 : stm32f10x.h
  • TIM_CCMR1_IC1F : stm32f10x.h
  • TIM_CCMR1_IC1F_0 : stm32f10x.h
  • TIM_CCMR1_IC1F_1 : stm32f10x.h
  • TIM_CCMR1_IC1F_2 : stm32f10x.h
  • TIM_CCMR1_IC1F_3 : stm32f10x.h
  • TIM_CCMR1_IC1PSC : stm32f10x.h
  • TIM_CCMR1_IC1PSC_0 : stm32f10x.h
  • TIM_CCMR1_IC1PSC_1 : stm32f10x.h
  • TIM_CCMR1_IC2F : stm32f10x.h
  • TIM_CCMR1_IC2F_0 : stm32f10x.h
  • TIM_CCMR1_IC2F_1 : stm32f10x.h
  • TIM_CCMR1_IC2F_2 : stm32f10x.h
  • TIM_CCMR1_IC2F_3 : stm32f10x.h
  • TIM_CCMR1_IC2PSC : stm32f10x.h
  • TIM_CCMR1_IC2PSC_0 : stm32f10x.h
  • TIM_CCMR1_IC2PSC_1 : stm32f10x.h
  • TIM_CCMR1_OC1CE : stm32f10x.h
  • TIM_CCMR1_OC1FE : stm32f10x.h
  • TIM_CCMR1_OC1M : stm32f10x.h
  • TIM_CCMR1_OC1M_0 : stm32f10x.h
  • TIM_CCMR1_OC1M_1 : stm32f10x.h
  • TIM_CCMR1_OC1M_2 : stm32f10x.h
  • TIM_CCMR1_OC1PE : stm32f10x.h
  • TIM_CCMR1_OC2CE : stm32f10x.h
  • TIM_CCMR1_OC2FE : stm32f10x.h
  • TIM_CCMR1_OC2M : stm32f10x.h
  • TIM_CCMR1_OC2M_0 : stm32f10x.h
  • TIM_CCMR1_OC2M_1 : stm32f10x.h
  • TIM_CCMR1_OC2M_2 : stm32f10x.h
  • TIM_CCMR1_OC2PE : stm32f10x.h
  • TIM_CCMR2_CC3S : stm32f10x.h
  • TIM_CCMR2_CC3S_0 : stm32f10x.h
  • TIM_CCMR2_CC3S_1 : stm32f10x.h
  • TIM_CCMR2_CC4S : stm32f10x.h
  • TIM_CCMR2_CC4S_0 : stm32f10x.h
  • TIM_CCMR2_CC4S_1 : stm32f10x.h
  • TIM_CCMR2_IC3F : stm32f10x.h
  • TIM_CCMR2_IC3F_0 : stm32f10x.h
  • TIM_CCMR2_IC3F_1 : stm32f10x.h
  • TIM_CCMR2_IC3F_2 : stm32f10x.h
  • TIM_CCMR2_IC3F_3 : stm32f10x.h
  • TIM_CCMR2_IC3PSC : stm32f10x.h
  • TIM_CCMR2_IC3PSC_0 : stm32f10x.h
  • TIM_CCMR2_IC3PSC_1 : stm32f10x.h
  • TIM_CCMR2_IC4F : stm32f10x.h
  • TIM_CCMR2_IC4F_0 : stm32f10x.h
  • TIM_CCMR2_IC4F_1 : stm32f10x.h
  • TIM_CCMR2_IC4F_2 : stm32f10x.h
  • TIM_CCMR2_IC4F_3 : stm32f10x.h
  • TIM_CCMR2_IC4PSC : stm32f10x.h
  • TIM_CCMR2_IC4PSC_0 : stm32f10x.h
  • TIM_CCMR2_IC4PSC_1 : stm32f10x.h
  • TIM_CCMR2_OC3CE : stm32f10x.h
  • TIM_CCMR2_OC3FE : stm32f10x.h
  • TIM_CCMR2_OC3M : stm32f10x.h
  • TIM_CCMR2_OC3M_0 : stm32f10x.h
  • TIM_CCMR2_OC3M_1 : stm32f10x.h
  • TIM_CCMR2_OC3M_2 : stm32f10x.h
  • TIM_CCMR2_OC3PE : stm32f10x.h
  • TIM_CCMR2_OC4CE : stm32f10x.h
  • TIM_CCMR2_OC4FE : stm32f10x.h
  • TIM_CCMR2_OC4M : stm32f10x.h
  • TIM_CCMR2_OC4M_0 : stm32f10x.h
  • TIM_CCMR2_OC4M_1 : stm32f10x.h
  • TIM_CCMR2_OC4M_2 : stm32f10x.h
  • TIM_CCMR2_OC4PE : stm32f10x.h
  • TIM_CCPreloadControl() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_CCR1_CCR1 : stm32f10x.h
  • TIM_CCR2_CCR2 : stm32f10x.h
  • TIM_CCR3_CCR3 : stm32f10x.h
  • TIM_CCR4_CCR4 : stm32f10x.h
  • TIM_CCx_Disable : stm32f10x_tim.h
  • TIM_CCx_Enable : stm32f10x_tim.h
  • TIM_CCxCmd() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_CCxN_Disable : stm32f10x_tim.h
  • TIM_CCxN_Enable : stm32f10x_tim.h
  • TIM_CCxNCmd() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_Channel_1 : stm32f10x_tim.h
  • TIM_Channel_2 : stm32f10x_tim.h
  • TIM_Channel_3 : stm32f10x_tim.h
  • TIM_Channel_4 : stm32f10x_tim.h
  • TIM_CKD_DIV1 : stm32f10x_tim.h
  • TIM_CKD_DIV2 : stm32f10x_tim.h
  • TIM_CKD_DIV4 : stm32f10x_tim.h
  • TIM_ClearFlag() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_ClearITPendingBit() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_ClearOC1Ref() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_ClearOC2Ref() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_ClearOC3Ref() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_ClearOC4Ref() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_Cmd() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_CNT_CNT : stm32f10x.h
  • TIM_Config() : STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/main.c
  • TIM_CounterMode_CenterAligned1 : stm32f10x_tim.h
  • TIM_CounterMode_CenterAligned2 : stm32f10x_tim.h
  • TIM_CounterMode_CenterAligned3 : stm32f10x_tim.h
  • TIM_CounterMode_Down : stm32f10x_tim.h
  • TIM_CounterMode_Up : stm32f10x_tim.h
  • TIM_CounterModeConfig() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_CR1_ARPE : stm32f10x.h
  • TIM_CR1_CEN : stm32f10x.h
  • TIM_CR1_CKD : stm32f10x.h
  • TIM_CR1_CKD_0 : stm32f10x.h
  • TIM_CR1_CKD_1 : stm32f10x.h
  • TIM_CR1_CMS : stm32f10x.h
  • TIM_CR1_CMS_0 : stm32f10x.h
  • TIM_CR1_CMS_1 : stm32f10x.h
  • TIM_CR1_DIR : stm32f10x.h
  • TIM_CR1_OPM : stm32f10x.h
  • TIM_CR1_UDIS : stm32f10x.h
  • TIM_CR1_URS : stm32f10x.h
  • TIM_CR2_CCDS : stm32f10x.h
  • TIM_CR2_CCPC : stm32f10x.h
  • TIM_CR2_CCUS : stm32f10x.h
  • TIM_CR2_MMS : stm32f10x.h
  • TIM_CR2_MMS_0 : stm32f10x.h
  • TIM_CR2_MMS_1 : stm32f10x.h
  • TIM_CR2_MMS_2 : stm32f10x.h
  • TIM_CR2_OIS1 : stm32f10x.h
  • TIM_CR2_OIS1N : stm32f10x.h
  • TIM_CR2_OIS2 : stm32f10x.h
  • TIM_CR2_OIS2N : stm32f10x.h
  • TIM_CR2_OIS3 : stm32f10x.h
  • TIM_CR2_OIS3N : stm32f10x.h
  • TIM_CR2_OIS4 : stm32f10x.h
  • TIM_CR2_TI1S : stm32f10x.h
  • TIM_CtrlPWMOutputs() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_DCR_DBA : stm32f10x.h
  • TIM_DCR_DBA_0 : stm32f10x.h
  • TIM_DCR_DBA_1 : stm32f10x.h
  • TIM_DCR_DBA_2 : stm32f10x.h
  • TIM_DCR_DBA_3 : stm32f10x.h
  • TIM_DCR_DBA_4 : stm32f10x.h
  • TIM_DCR_DBL : stm32f10x.h
  • TIM_DCR_DBL_0 : stm32f10x.h
  • TIM_DCR_DBL_1 : stm32f10x.h
  • TIM_DCR_DBL_2 : stm32f10x.h
  • TIM_DCR_DBL_3 : stm32f10x.h
  • TIM_DCR_DBL_4 : stm32f10x.h
  • TIM_DeInit() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_DIER_BIE : stm32f10x.h
  • TIM_DIER_CC1DE : stm32f10x.h
  • TIM_DIER_CC1IE : stm32f10x.h
  • TIM_DIER_CC2DE : stm32f10x.h
  • TIM_DIER_CC2IE : stm32f10x.h
  • TIM_DIER_CC3DE : stm32f10x.h
  • TIM_DIER_CC3IE : stm32f10x.h
  • TIM_DIER_CC4DE : stm32f10x.h
  • TIM_DIER_CC4IE : stm32f10x.h
  • TIM_DIER_COMDE : stm32f10x.h
  • TIM_DIER_COMIE : stm32f10x.h
  • TIM_DIER_TDE : stm32f10x.h
  • TIM_DIER_TIE : stm32f10x.h
  • TIM_DIER_UDE : stm32f10x.h
  • TIM_DIER_UIE : stm32f10x.h
  • TIM_DMA_CC1 : stm32f10x_tim.h
  • TIM_DMA_CC2 : stm32f10x_tim.h
  • TIM_DMA_CC3 : stm32f10x_tim.h
  • TIM_DMA_CC4 : stm32f10x_tim.h
  • TIM_DMA_COM : stm32f10x_tim.h
  • TIM_DMA_Trigger : stm32f10x_tim.h
  • TIM_DMA_Update : stm32f10x_tim.h
  • TIM_DMABase_ARR : stm32f10x_tim.h
  • TIM_DMABase_BDTR : stm32f10x_tim.h
  • TIM_DMABase_CCER : stm32f10x_tim.h
  • TIM_DMABase_CCMR1 : stm32f10x_tim.h
  • TIM_DMABase_CCMR2 : stm32f10x_tim.h
  • TIM_DMABase_CCR1 : stm32f10x_tim.h
  • TIM_DMABase_CCR2 : stm32f10x_tim.h
  • TIM_DMABase_CCR3 : stm32f10x_tim.h
  • TIM_DMABase_CCR4 : stm32f10x_tim.h
  • TIM_DMABase_CNT : stm32f10x_tim.h
  • TIM_DMABase_CR1 : stm32f10x_tim.h
  • TIM_DMABase_CR2 : stm32f10x_tim.h
  • TIM_DMABase_DCR : stm32f10x_tim.h
  • TIM_DMABase_DIER : stm32f10x_tim.h
  • TIM_DMABase_EGR : stm32f10x_tim.h
  • TIM_DMABase_PSC : stm32f10x_tim.h
  • TIM_DMABase_RCR : stm32f10x_tim.h
  • TIM_DMABase_SMCR : stm32f10x_tim.h
  • TIM_DMABase_SR : stm32f10x_tim.h
  • TIM_DMABurstLength_10Bytes : stm32f10x_tim.h
  • TIM_DMABurstLength_10Transfers : stm32f10x_tim.h
  • TIM_DMABurstLength_11Bytes : stm32f10x_tim.h
  • TIM_DMABurstLength_11Transfers : stm32f10x_tim.h
  • TIM_DMABurstLength_12Bytes : stm32f10x_tim.h
  • TIM_DMABurstLength_12Transfers : stm32f10x_tim.h
  • TIM_DMABurstLength_13Bytes : stm32f10x_tim.h
  • TIM_DMABurstLength_13Transfers : stm32f10x_tim.h
  • TIM_DMABurstLength_14Bytes : stm32f10x_tim.h
  • TIM_DMABurstLength_14Transfers : stm32f10x_tim.h
  • TIM_DMABurstLength_15Bytes : stm32f10x_tim.h
  • TIM_DMABurstLength_15Transfers : stm32f10x_tim.h
  • TIM_DMABurstLength_16Bytes : stm32f10x_tim.h
  • TIM_DMABurstLength_16Transfers : stm32f10x_tim.h
  • TIM_DMABurstLength_17Bytes : stm32f10x_tim.h
  • TIM_DMABurstLength_17Transfers : stm32f10x_tim.h
  • TIM_DMABurstLength_18Bytes : stm32f10x_tim.h
  • TIM_DMABurstLength_18Transfers : stm32f10x_tim.h
  • TIM_DMABurstLength_1Byte : stm32f10x_tim.h
  • TIM_DMABurstLength_1Transfer : stm32f10x_tim.h
  • TIM_DMABurstLength_2Bytes : stm32f10x_tim.h
  • TIM_DMABurstLength_2Transfers : stm32f10x_tim.h
  • TIM_DMABurstLength_3Bytes : stm32f10x_tim.h
  • TIM_DMABurstLength_3Transfers : stm32f10x_tim.h
  • TIM_DMABurstLength_4Bytes : stm32f10x_tim.h
  • TIM_DMABurstLength_4Transfers : stm32f10x_tim.h
  • TIM_DMABurstLength_5Bytes : stm32f10x_tim.h
  • TIM_DMABurstLength_5Transfers : stm32f10x_tim.h
  • TIM_DMABurstLength_6Bytes : stm32f10x_tim.h
  • TIM_DMABurstLength_6Transfers : stm32f10x_tim.h
  • TIM_DMABurstLength_7Bytes : stm32f10x_tim.h
  • TIM_DMABurstLength_7Transfers : stm32f10x_tim.h
  • TIM_DMABurstLength_8Bytes : stm32f10x_tim.h
  • TIM_DMABurstLength_8Transfers : stm32f10x_tim.h
  • TIM_DMABurstLength_9Bytes : stm32f10x_tim.h
  • TIM_DMABurstLength_9Transfers : stm32f10x_tim.h
  • TIM_DMACmd() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_DMAConfig() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_DMAR_DMAB : stm32f10x.h
  • TIM_EGR_BG : stm32f10x.h
  • TIM_EGR_CC1G : stm32f10x.h
  • TIM_EGR_CC2G : stm32f10x.h
  • TIM_EGR_CC3G : stm32f10x.h
  • TIM_EGR_CC4G : stm32f10x.h
  • TIM_EGR_COMG : stm32f10x.h
  • TIM_EGR_TG : stm32f10x.h
  • TIM_EGR_UG : stm32f10x.h
  • TIM_EncoderInterfaceConfig() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_EncoderMode_TI1 : stm32f10x_tim.h
  • TIM_EncoderMode_TI12 : stm32f10x_tim.h
  • TIM_EncoderMode_TI2 : stm32f10x_tim.h
  • TIM_ETRClockMode1Config() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_ETRClockMode2Config() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_ETRConfig() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_EventSource_Break : stm32f10x_tim.h
  • TIM_EventSource_CC1 : stm32f10x_tim.h
  • TIM_EventSource_CC2 : stm32f10x_tim.h
  • TIM_EventSource_CC3 : stm32f10x_tim.h
  • TIM_EventSource_CC4 : stm32f10x_tim.h
  • TIM_EventSource_COM : stm32f10x_tim.h
  • TIM_EventSource_Trigger : stm32f10x_tim.h
  • TIM_EventSource_Update : stm32f10x_tim.h
  • TIM_ExtTRGPolarity_Inverted : stm32f10x_tim.h
  • TIM_ExtTRGPolarity_NonInverted : stm32f10x_tim.h
  • TIM_ExtTRGPSC_DIV2 : stm32f10x_tim.h
  • TIM_ExtTRGPSC_DIV4 : stm32f10x_tim.h
  • TIM_ExtTRGPSC_DIV8 : stm32f10x_tim.h
  • TIM_ExtTRGPSC_OFF : stm32f10x_tim.h
  • TIM_FLAG_Break : stm32f10x_tim.h
  • TIM_FLAG_CC1 : stm32f10x_tim.h
  • TIM_FLAG_CC1OF : stm32f10x_tim.h
  • TIM_FLAG_CC2 : stm32f10x_tim.h
  • TIM_FLAG_CC2OF : stm32f10x_tim.h
  • TIM_FLAG_CC3 : stm32f10x_tim.h
  • TIM_FLAG_CC3OF : stm32f10x_tim.h
  • TIM_FLAG_CC4 : stm32f10x_tim.h
  • TIM_FLAG_CC4OF : stm32f10x_tim.h
  • TIM_FLAG_COM : stm32f10x_tim.h
  • TIM_FLAG_Trigger : stm32f10x_tim.h
  • TIM_FLAG_Update : stm32f10x_tim.h
  • TIM_ForcedAction_Active : stm32f10x_tim.h
  • TIM_ForcedAction_InActive : stm32f10x_tim.h
  • TIM_ForcedOC1Config() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_ForcedOC2Config() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_ForcedOC3Config() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_ForcedOC4Config() : stm32f10x_tim.c , stm32f10x_tim.h
  • TIM_GenerateEvent() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_GetCapture1() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_GetCapture2() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_GetCapture3() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_GetCapture4() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_GetCounter() : stm32f10x_tim.c , stm32f10x_tim.h
  • TIM_GetFlagStatus() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_GetITStatus() : stm32f10x_tim.c , stm32f10x_tim.h
  • TIM_GetPrescaler() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_ICInit() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_ICInitStructure : STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/main.c , STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/main.c , STM32F10x_StdPeriph_Examples/TIM/OnePulse/main.c , STM32F10x_StdPeriph_Examples/TIM/PWM_Input/main.c , STM32F10x_StdPeriph_Examples/TIM/InputCapture/main.c
  • TIM_ICPolarity_BothEdge : stm32f10x_tim.h
  • TIM_ICPolarity_Falling : stm32f10x_tim.h
  • TIM_ICPolarity_Rising : stm32f10x_tim.h
  • TIM_ICPSC_DIV1 : stm32f10x_tim.h
  • TIM_ICPSC_DIV2 : stm32f10x_tim.h
  • TIM_ICPSC_DIV4 : stm32f10x_tim.h
  • TIM_ICPSC_DIV8 : stm32f10x_tim.h
  • TIM_ICSelection_DirectTI : stm32f10x_tim.h
  • TIM_ICSelection_IndirectTI : stm32f10x_tim.h
  • TIM_ICSelection_TRC : stm32f10x_tim.h
  • TIM_ICStructInit() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_InternalClockConfig() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_IT_Break : stm32f10x_tim.h
  • TIM_IT_CC1 : stm32f10x_tim.h
  • TIM_IT_CC2 : stm32f10x_tim.h
  • TIM_IT_CC3 : stm32f10x_tim.h
  • TIM_IT_CC4 : stm32f10x_tim.h
  • TIM_IT_COM : stm32f10x_tim.h
  • TIM_IT_Trigger : stm32f10x_tim.h
  • TIM_IT_Update : stm32f10x_tim.h
  • TIM_ITConfig() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_ITRxExternalClockConfig() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_LOCKLevel_1 : stm32f10x_tim.h
  • TIM_LOCKLevel_2 : stm32f10x_tim.h
  • TIM_LOCKLevel_3 : stm32f10x_tim.h
  • TIM_LOCKLevel_OFF : stm32f10x_tim.h
  • TIM_MasterSlaveMode_Disable : stm32f10x_tim.h
  • TIM_MasterSlaveMode_Enable : stm32f10x_tim.h
  • TIM_OC1FastConfig() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_OC1Init() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_OC1NPolarityConfig() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_OC1PolarityConfig() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_OC1PreloadConfig() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_OC2FastConfig() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_OC2Init() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_OC2NPolarityConfig() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_OC2PolarityConfig() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_OC2PreloadConfig() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_OC3FastConfig() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_OC3Init() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_OC3NPolarityConfig() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_OC3PolarityConfig() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_OC3PreloadConfig() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_OC4FastConfig() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_OC4Init() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_OC4PolarityConfig() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_OC4PreloadConfig() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_OCClear_Disable : stm32f10x_tim.h
  • TIM_OCClear_Enable : stm32f10x_tim.h
  • TIM_OCFast_Disable : stm32f10x_tim.h
  • TIM_OCFast_Enable : stm32f10x_tim.h
  • TIM_OCIdleState_Reset : stm32f10x_tim.h
  • TIM_OCIdleState_Set : stm32f10x_tim.h
  • TIM_OCInitStructure : STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/main.c , STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/main.c , STM32F10x_StdPeriph_Examples/TIM/6Steps/main.c , STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/main.c , STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/main.c , STM32F10x_StdPeriph_Examples/TIM/DMA/main.c , STM32F10x_StdPeriph_Examples/TIM/DMABurst/main.c , STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/main.c , STM32F10x_StdPeriph_Examples/TIM/OCInactive/main.c , STM32F10x_StdPeriph_Examples/TIM/OCToggle/main.c , STM32F10x_StdPeriph_Examples/TIM/OnePulse/main.c , STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/main.c , STM32F10x_StdPeriph_Examples/TIM/PWM_Output/main.c , STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/main.c , STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/main.c , STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/main.c , STM32F10x_StdPeriph_Examples/TIM/TimeBase/main.c , STM32F10x_StdPeriph_Examples/TIM/OCActive/main.c , STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/main.c , STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/main.c
  • TIM_OCMode_Active : stm32f10x_tim.h
  • TIM_OCMode_Inactive : stm32f10x_tim.h
  • TIM_OCMode_PWM1 : stm32f10x_tim.h
  • TIM_OCMode_PWM2 : stm32f10x_tim.h
  • TIM_OCMode_Timing : stm32f10x_tim.h
  • TIM_OCMode_Toggle : stm32f10x_tim.h
  • TIM_OCNIdleState_Reset : stm32f10x_tim.h
  • TIM_OCNIdleState_Set : stm32f10x_tim.h
  • TIM_OCNPolarity_High : stm32f10x_tim.h
  • TIM_OCNPolarity_Low : stm32f10x_tim.h
  • TIM_OCPolarity_High : stm32f10x_tim.h
  • TIM_OCPolarity_Low : stm32f10x_tim.h
  • TIM_OCPreload_Disable : stm32f10x_tim.h
  • TIM_OCPreload_Enable : stm32f10x_tim.h
  • TIM_OCStructInit() : stm32f10x_tim.c , stm32f10x_tim.h
  • TIM_OPMode_Repetitive : stm32f10x_tim.h
  • TIM_OPMode_Single : stm32f10x_tim.h
  • TIM_OSSIState_Disable : stm32f10x_tim.h
  • TIM_OSSIState_Enable : stm32f10x_tim.h
  • TIM_OSSRState_Disable : stm32f10x_tim.h
  • TIM_OSSRState_Enable : stm32f10x_tim.h
  • TIM_OutputNState_Disable : stm32f10x_tim.h
  • TIM_OutputNState_Enable : stm32f10x_tim.h
  • TIM_OutputState_Disable : stm32f10x_tim.h
  • TIM_OutputState_Enable : stm32f10x_tim.h
  • TIM_PrescalerConfig() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_PSC_PSC : stm32f10x.h
  • TIM_PSCReloadMode_Immediate : stm32f10x_tim.h
  • TIM_PSCReloadMode_Update : stm32f10x_tim.h
  • TIM_PWMIConfig() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_RCR_REP : stm32f10x.h
  • TIM_SelectCCDMA() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_SelectCOM() : stm32f10x_tim.c , stm32f10x_tim.h
  • TIM_SelectHallSensor() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_SelectInputTrigger() : stm32f10x_tim.c , stm32f10x_tim.h
  • TIM_SelectMasterSlaveMode() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_SelectOCxM() : stm32f10x_tim.c , stm32f10x_tim.h
  • TIM_SelectOnePulseMode() : stm32f10x_tim.c , stm32f10x_tim.h
  • TIM_SelectOutputTrigger() : stm32f10x_tim.c , stm32f10x_tim.h
  • TIM_SelectSlaveMode() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_SetAutoreload() : stm32f10x_tim.c , stm32f10x_tim.h
  • TIM_SetClockDivision() : stm32f10x_tim.c , stm32f10x_tim.h
  • TIM_SetCompare1() : stm32f10x_tim.c , stm32f10x_tim.h
  • TIM_SetCompare2() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_SetCompare3() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_SetCompare4() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_SetCounter() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_SetIC1Prescaler() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_SetIC2Prescaler() : stm32f10x_tim.c , stm32f10x_tim.h
  • TIM_SetIC3Prescaler() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_SetIC4Prescaler() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_SlaveMode_External1 : stm32f10x_tim.h
  • TIM_SlaveMode_Gated : stm32f10x_tim.h
  • TIM_SlaveMode_Reset : stm32f10x_tim.h
  • TIM_SlaveMode_Trigger : stm32f10x_tim.h
  • TIM_SMCR_ECE : stm32f10x.h
  • TIM_SMCR_ETF : stm32f10x.h
  • TIM_SMCR_ETF_0 : stm32f10x.h
  • TIM_SMCR_ETF_1 : stm32f10x.h
  • TIM_SMCR_ETF_2 : stm32f10x.h
  • TIM_SMCR_ETF_3 : stm32f10x.h
  • TIM_SMCR_ETP : stm32f10x.h
  • TIM_SMCR_ETPS : stm32f10x.h
  • TIM_SMCR_ETPS_0 : stm32f10x.h
  • TIM_SMCR_ETPS_1 : stm32f10x.h
  • TIM_SMCR_MSM : stm32f10x.h
  • TIM_SMCR_SMS : stm32f10x.h
  • TIM_SMCR_SMS_0 : stm32f10x.h
  • TIM_SMCR_SMS_1 : stm32f10x.h
  • TIM_SMCR_SMS_2 : stm32f10x.h
  • TIM_SMCR_TS : stm32f10x.h
  • TIM_SMCR_TS_0 : stm32f10x.h
  • TIM_SMCR_TS_1 : stm32f10x.h
  • TIM_SMCR_TS_2 : stm32f10x.h
  • TIM_SR_BIF : stm32f10x.h
  • TIM_SR_CC1IF : stm32f10x.h
  • TIM_SR_CC1OF : stm32f10x.h
  • TIM_SR_CC2IF : stm32f10x.h
  • TIM_SR_CC2OF : stm32f10x.h
  • TIM_SR_CC3IF : stm32f10x.h
  • TIM_SR_CC3OF : stm32f10x.h
  • TIM_SR_CC4IF : stm32f10x.h
  • TIM_SR_CC4OF : stm32f10x.h
  • TIM_SR_COMIF : stm32f10x.h
  • TIM_SR_TIF : stm32f10x.h
  • TIM_SR_UIF : stm32f10x.h
  • TIM_TimeBaseInit() : stm32f10x_tim.c , stm32f10x_tim.h
  • TIM_TimeBaseStructInit() : stm32f10x_tim.c , stm32f10x_tim.h
  • TIM_TimeBaseStructure : STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/main.c , STM32F10x_StdPeriph_Examples/TIM/OCActive/main.c , STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/main.c , STM32F10x_StdPeriph_Examples/TIM/OnePulse/main.c , STM32F10x_StdPeriph_Examples/TIM/6Steps/main.c , STM32F10x_StdPeriph_Examples/TIM/DMA/main.c , STM32F10x_StdPeriph_Examples/TIM/OCInactive/main.c , STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/main.c , STM32F10x_StdPeriph_Examples/TIM/PWM_Output/main.c , STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/main.c , STM32F10x_StdPeriph_Examples/TIM/TimeBase/main.c , STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/main.c , STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/main.c , STM32F10x_StdPeriph_Examples/TIM/DMABurst/main.c , STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/main.c , STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/main.c , STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/main.c , STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/main.c , STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/main.c , STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/main.c , STM32F10x_StdPeriph_Examples/TIM/OCToggle/main.c , STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/main.c , STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/main.c
  • TIM_TIxExternalCLK1Source_TI1 : stm32f10x_tim.h
  • TIM_TIxExternalCLK1Source_TI1ED : stm32f10x_tim.h
  • TIM_TIxExternalCLK1Source_TI2 : stm32f10x_tim.h
  • TIM_TIxExternalClockConfig() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_TRGOSource_Enable : stm32f10x_tim.h
  • TIM_TRGOSource_OC1 : stm32f10x_tim.h
  • TIM_TRGOSource_OC1Ref : stm32f10x_tim.h
  • TIM_TRGOSource_OC2Ref : stm32f10x_tim.h
  • TIM_TRGOSource_OC3Ref : stm32f10x_tim.h
  • TIM_TRGOSource_OC4Ref : stm32f10x_tim.h
  • TIM_TRGOSource_Reset : stm32f10x_tim.h
  • TIM_TRGOSource_Update : stm32f10x_tim.h
  • TIM_TS_ETRF : stm32f10x_tim.h
  • TIM_TS_ITR0 : stm32f10x_tim.h
  • TIM_TS_ITR1 : stm32f10x_tim.h
  • TIM_TS_ITR2 : stm32f10x_tim.h
  • TIM_TS_ITR3 : stm32f10x_tim.h
  • TIM_TS_TI1F_ED : stm32f10x_tim.h
  • TIM_TS_TI1FP1 : stm32f10x_tim.h
  • TIM_TS_TI2FP2 : stm32f10x_tim.h
  • TIM_UpdateDisableConfig() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_UpdateRequestConfig() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_UpdateSource_Global : stm32f10x_tim.h
  • TIM_UpdateSource_Regular : stm32f10x_tim.h
  • Time_Adjust() : STM32F10x_StdPeriph_Examples/RTC/Calendar/main.c
  • Time_Display() : STM32F10x_StdPeriph_Examples/RTC/Calendar/main.c
  • Time_Regulate() : STM32F10x_StdPeriph_Examples/RTC/Calendar/main.c
  • Time_Show() : STM32F10x_StdPeriph_Examples/RTC/Calendar/main.c
  • TimeDisplay : STM32F10x_StdPeriph_Examples/RTC/Calendar/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/RTC/Calendar/main.c
  • TIMEOUT_MAX : stm32100e_eval_ioe.c , stm3210c_eval_ioe.c
  • TimerPeriod : STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/main.c , STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/main.c , STM32F10x_StdPeriph_Examples/TIM/DMA/main.c
  • TimingDelay : STM32F10x_StdPeriph_Examples/SysTick/TimeBase/main.c , STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/main.c , STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/main.c , STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/main.c , STM32F10x_StdPeriph_Examples/PWR/STOP/main.c , STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/main.c
  • TimingDelay_Decrement() : NVIC/VectorTable_Relocation/main.h , STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/main.c , FLASH/Dual_Boot/main.h , STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/main.c , STM32F10x_StdPeriph_Examples/SysTick/TimeBase/main.c , SysTick/TimeBase/main.h
  • TMIDxR_TXRQ : stm32f10x_can.c
  • tmpCC4 : STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_it.c
  • TOUCH_IO_ALL : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • TOUCH_XD : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • TOUCH_XU : stm3210c_eval_ioe.h , stm32100e_eval_ioe.h
  • TOUCH_YD : stm3210c_eval_ioe.h , stm32100e_eval_ioe.h
  • TOUCH_YU : stm3210c_eval_ioe.h , stm32100e_eval_ioe.h
  • TPAL_BitNumber : stm32f10x_bkp.c
  • TPE_BitNumber : stm32f10x_bkp.c
  • TPIE_BitNumber : stm32f10x_bkp.c
  • TransErrorCode : stm32100b_eval_cec.c , stm32100e_eval_cec.c , STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.c
  • TransferEnd : stm32_eval_sdio_sd.c
  • TransferError : stm32_eval_sdio_sd.c
  • TransferStatus : STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/main.c , STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/main.c , STM32F10x_StdPeriph_Examples/USART/Polling/main.c , STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/main.c , STM32F10x_StdPeriph_Examples/SPI/DMA/main.c , STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/main.c , STM32F10x_StdPeriph_Examples/DMA/FSMC/main.c
  • TransferStatus1 : STM32F10x_StdPeriph_Examples/USART/HalfDuplex/main.c , STM32F10x_StdPeriph_Examples/I2S/Interrupt/main.c , STM32F10x_StdPeriph_Examples/SPI/CRC/main.c , STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/main.c , STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/main.c , STM32F10x_StdPeriph_Examples/SDIO/uSDCard/main.c , STM32F10x_StdPeriph_Examples/I2C/EEPROM/main.c , STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/main.c , STM32F10x_StdPeriph_Examples/USART/Synchronous/main.c , STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/main.c , STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/main.c , STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c , STM32F10x_StdPeriph_Examples/USART/DMA_Polling/main.c
  • TransferStatus2 : STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c , STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/main.c , STM32F10x_StdPeriph_Examples/I2C/EEPROM/main.c , STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/main.c , STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/main.c , STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/main.c , STM32F10x_StdPeriph_Examples/SPI/CRC/main.c , STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/main.c , STM32F10x_StdPeriph_Examples/USART/HalfDuplex/main.c , STM32F10x_StdPeriph_Examples/I2S/Interrupt/main.c , STM32F10x_StdPeriph_Examples/USART/DMA_Polling/main.c , STM32F10x_StdPeriph_Examples/SDIO/uSDCard/main.c , STM32F10x_StdPeriph_Examples/USART/Synchronous/main.c
  • TransferStatus3 : STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/main.c , STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/main.c
  • TransferStatus4 : STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/main.c
  • TransmitBuffer : STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/main.c , STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.c
  • TS_CONVERSION_DELAY : stm3210c_eval_ioe.c
  • TS_State : stm3210c_eval_ioe.c , stm32100e_eval_ioe.c
  • TSOM_BitNumber : stm32f10x_cec.c
  • Tx1_Buffer : STM32F10x_StdPeriph_Examples/I2C/EEPROM/main.c
  • Tx2_Buffer : STM32F10x_StdPeriph_Examples/I2C/EEPROM/main.c
  • Tx_Buffer : STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/main.c
  • Tx_Idx : STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/main.c
  • TxBuffer : STM32F10x_StdPeriph_Examples/USART/Polling/main.c , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/main.c , STM32F10x_StdPeriph_Examples/FSMC/NAND/main.c , STM32F10x_StdPeriph_Examples/FSMC/NOR/main.c , STM32F10x_StdPeriph_Examples/FSMC/OneNAND/main.c , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/SRAM/main.c
  • TxBuffer1 : STM32F10x_StdPeriph_Examples/USART/Synchronous/main.c , STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c , STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/main.c , STM32F10x_StdPeriph_Examples/USART/DMA_Polling/main.c , STM32F10x_StdPeriph_Examples/USART/HalfDuplex/main.c , STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.c
  • TxBuffer2 : STM32F10x_StdPeriph_Examples/USART/DMA_Polling/main.c , STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c , STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/main.c , STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Synchronous/main.c , STM32F10x_StdPeriph_Examples/USART/HalfDuplex/main.c
  • TxBufferSize : STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/main.c , STM32F10x_StdPeriph_Examples/USART/Polling/main.c , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.c
  • TxBufferSize1 : STM32F10x_StdPeriph_Examples/USART/DMA_Polling/main.c , STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/main.c , STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c , STM32F10x_StdPeriph_Examples/USART/Synchronous/main.c , STM32F10x_StdPeriph_Examples/USART/HalfDuplex/main.c
  • TxBufferSize2 : STM32F10x_StdPeriph_Examples/USART/Synchronous/main.c , STM32F10x_StdPeriph_Examples/USART/HalfDuplex/main.c , STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c , STM32F10x_StdPeriph_Examples/USART/DMA_Polling/main.c , STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/main.c
  • TxCounter : STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.c , stm32100b_eval_cec.c , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/main.c , stm32100e_eval_cec.c , STM32F10x_StdPeriph_Examples/USART/Polling/main.c
  • TxCounter1 : STM32F10x_StdPeriph_Examples/USART/HalfDuplex/main.c , STM32F10x_StdPeriph_Examples/USART/Synchronous/main.c , STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c , STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.c
  • TxCounter2 : STM32F10x_StdPeriph_Examples/USART/Synchronous/main.c , STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c , STM32F10x_StdPeriph_Examples/USART/HalfDuplex/main.c , STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.c
  • TxIdx : STM32F10x_StdPeriph_Examples/I2S/Interrupt/main.c , STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/main.c , STM32F10x_StdPeriph_Examples/SPI/DMA/main.c , STM32F10x_StdPeriph_Examples/SPI/CRC/main.c , STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/main.c , STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/main.c
  • TxMessage : STM32F10x_StdPeriph_Examples/CAN/DualCAN/main.c , STM32F10x_StdPeriph_Examples/CAN/Networking/main.c
  • Type_Edge : stm3210c_eval_ioe.h , stm32100e_eval_ioe.h
  • Type_Level : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h


STM32F10x Standard Peripherals Firmware Library: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- u -

  • u16 : stm32f10x.h
  • u32 : stm32f10x.h
  • u8 : stm32f10x.h
  • UART4 : stm32f10x.h
  • UART4_BASE : stm32f10x.h
  • UART4_DBG : stm32f10x_ip_dbg.c
  • UART5 : stm32f10x.h
  • UART5_BASE : stm32f10x.h
  • UART5_DBG : stm32f10x_ip_dbg.c
  • uc16 : stm32f10x.h
  • uc32 : stm32f10x.h
  • uc8 : stm32f10x.h
  • UP_BUTTON_EXTI_IRQn : stm3210e_eval.h , stm32l152_eval.h , stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h
  • UP_BUTTON_EXTI_LINE : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210e_eval.h , stm32l152_eval.h
  • UP_BUTTON_EXTI_PIN_SOURCE : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210e_eval.h , stm32l152_eval.h
  • UP_BUTTON_EXTI_PORT_SOURCE : stm32l152_eval.h , stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210e_eval.h
  • UP_BUTTON_GPIO_CLK : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210e_eval.h , stm32l152_eval.h
  • UP_BUTTON_GPIO_PORT : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210e_eval.h , stm32l152_eval.h
  • UP_BUTTON_PIN : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210e_eval.h , stm32l152_eval.h
  • UsageFault_Handler() : STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2C/IOExpander/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2C/IOExpander/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CortexM3/BitBand/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CortexM3/BitBand/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/PWR/PVD/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/PWR/PVD/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/PWR/STANDBY/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/PWR/STANDBY/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CortexM3/MPU/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CortexM3/MPU/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/RTC/Calendar/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/RTC/Calendar/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SDIO/uSDCard/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SDIO/uSDCard/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SPI/CRC/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SPI/CRC/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/DMA/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SPI/DMA/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SysTick/TimeBase/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SysTick/TimeBase/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/6Steps/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/6Steps/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/DMA/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/DMA/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/DMABurst/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/DMABurst/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/FSMC/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/FSMC/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/OCActive/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/OCActive/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/OCInactive/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/OCInactive/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/OnePulse/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/OnePulse/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/PWM_Input/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/PWM_Input/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/PWM_Output/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/PWM_Output/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FLASH/Program/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FLASH/Program/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/NAND/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/NAND/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/DMA_Polling/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/DMA_Polling/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/NOR/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/HalfDuplex/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/HalfDuplex/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/NOR/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/OneNAND/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/MultiProcessor/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/MultiProcessor/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/OneNAND/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Polling/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Polling/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/SRAM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Printf/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Printf/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/SRAM/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Synchronous/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Synchronous/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/BKP/Backup_Data/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/GPIO/IOToggle/stm32f10x_it.c , STM32F10x_StdPeriph_Template/stm32f10x_it.c , STM32F10x_StdPeriph_Template/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/GPIO/IOToggle/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/BKP/Backup_Data/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/BKP/Tamper/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2C/EEPROM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2C/EEPROM/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/BKP/Tamper/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/stm32f10x_it.h
  • UsageFault_IRQn : stm32f10x.h
  • USART1 : stm32f10x.h
  • USART1_BASE : stm32f10x.h
  • USART1_DBG : stm32f10x_ip_dbg.c
  • USART1_IRQHandler() : STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.h
  • USART2 : stm32f10x.h
  • USART2_BASE : stm32f10x.h
  • USART2_DBG : stm32f10x_ip_dbg.c
  • USART2_IRQHandler() : STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.h
  • USART3 : stm32f10x.h
  • USART3_BASE : stm32f10x.h
  • USART3_DBG : stm32f10x_ip_dbg.c
  • USART3_IRQHandler() : STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_it.h
  • USART_BRR_DIV_Fraction : stm32f10x.h
  • USART_BRR_DIV_Mantissa : stm32f10x.h
  • USART_ClearFlag() : stm32f10x_usart.h , stm32f10x_usart.c
  • USART_ClearITPendingBit() : stm32f10x_usart.h , stm32f10x_usart.c
  • USART_Clock_Disable : stm32f10x_usart.h
  • USART_Clock_Enable : stm32f10x_usart.h
  • USART_ClockInit() : stm32f10x_usart.h , stm32f10x_usart.c
  • USART_ClockInitStructure : STM32F10x_StdPeriph_Examples/USART/Smartcard/main.c , STM32F10x_StdPeriph_Examples/USART/Synchronous/main.c
  • USART_ClockStructInit() : stm32f10x_usart.h , stm32f10x_usart.c
  • USART_Cmd() : stm32f10x_usart.h , stm32f10x_usart.c
  • USART_CPHA_1Edge : stm32f10x_usart.h
  • USART_CPHA_2Edge : stm32f10x_usart.h
  • USART_CPOL_High : stm32f10x_usart.h
  • USART_CPOL_Low : stm32f10x_usart.h
  • USART_CR1_IDLEIE : stm32f10x.h
  • USART_CR1_M : stm32f10x.h
  • USART_CR1_OVER8 : stm32f10x.h
  • USART_CR1_PCE : stm32f10x.h
  • USART_CR1_PEIE : stm32f10x.h
  • USART_CR1_PS : stm32f10x.h
  • USART_CR1_RE : stm32f10x.h
  • USART_CR1_RWU : stm32f10x.h
  • USART_CR1_RXNEIE : stm32f10x.h
  • USART_CR1_SBK : stm32f10x.h
  • USART_CR1_TCIE : stm32f10x.h
  • USART_CR1_TE : stm32f10x.h
  • USART_CR1_TXEIE : stm32f10x.h
  • USART_CR1_UE : stm32f10x.h
  • USART_CR1_WAKE : stm32f10x.h
  • USART_CR2_ADD : stm32f10x.h
  • USART_CR2_CLKEN : stm32f10x.h
  • USART_CR2_CPHA : stm32f10x.h
  • USART_CR2_CPOL : stm32f10x.h
  • USART_CR2_LBCL : stm32f10x.h
  • USART_CR2_LBDIE : stm32f10x.h
  • USART_CR2_LBDL : stm32f10x.h
  • USART_CR2_LINEN : stm32f10x.h
  • USART_CR2_STOP : stm32f10x.h
  • USART_CR2_STOP_0 : stm32f10x.h
  • USART_CR2_STOP_1 : stm32f10x.h
  • USART_CR3_CTSE : stm32f10x.h
  • USART_CR3_CTSIE : stm32f10x.h
  • USART_CR3_DMAR : stm32f10x.h
  • USART_CR3_DMAT : stm32f10x.h
  • USART_CR3_EIE : stm32f10x.h
  • USART_CR3_HDSEL : stm32f10x.h
  • USART_CR3_IREN : stm32f10x.h
  • USART_CR3_IRLP : stm32f10x.h
  • USART_CR3_NACK : stm32f10x.h
  • USART_CR3_ONEBIT : stm32f10x.h
  • USART_CR3_RTSE : stm32f10x.h
  • USART_CR3_SCEN : stm32f10x.h
  • USART_DeInit() : stm32f10x_usart.h , stm32f10x_usart.c
  • USART_DMACmd() : stm32f10x_usart.h , stm32f10x_usart.c
  • USART_DMAReq_Rx : stm32f10x_usart.h
  • USART_DMAReq_Tx : stm32f10x_usart.h
  • USART_DR_DR : stm32f10x.h
  • USART_FLAG_CTS : stm32f10x_usart.h
  • USART_FLAG_FE : stm32f10x_usart.h
  • USART_FLAG_IDLE : stm32f10x_usart.h
  • USART_FLAG_LBD : stm32f10x_usart.h
  • USART_FLAG_NE : stm32f10x_usart.h
  • USART_FLAG_ORE : stm32f10x_usart.h
  • USART_FLAG_PE : stm32f10x_usart.h
  • USART_FLAG_RXNE : stm32f10x_usart.h
  • USART_FLAG_TC : stm32f10x_usart.h
  • USART_FLAG_TXE : stm32f10x_usart.h
  • USART_GetFlagStatus() : stm32f10x_usart.h , stm32f10x_usart.c
  • USART_GetITStatus() : stm32f10x_usart.h , stm32f10x_usart.c
  • USART_GTPR_GT : stm32f10x.h
  • USART_GTPR_PSC : stm32f10x.h
  • USART_GTPR_PSC_0 : stm32f10x.h
  • USART_GTPR_PSC_1 : stm32f10x.h
  • USART_GTPR_PSC_2 : stm32f10x.h
  • USART_GTPR_PSC_3 : stm32f10x.h
  • USART_GTPR_PSC_4 : stm32f10x.h
  • USART_GTPR_PSC_5 : stm32f10x.h
  • USART_GTPR_PSC_6 : stm32f10x.h
  • USART_GTPR_PSC_7 : stm32f10x.h
  • USART_HalfDuplexCmd() : stm32f10x_usart.h , stm32f10x_usart.c
  • USART_HardwareFlowControl_CTS : stm32f10x_usart.h
  • USART_HardwareFlowControl_None : stm32f10x_usart.h
  • USART_HardwareFlowControl_RTS : stm32f10x_usart.h
  • USART_HardwareFlowControl_RTS_CTS : stm32f10x_usart.h
  • USART_Init() : stm32f10x_usart.h , stm32f10x_usart.c
  • USART_InitStructure : STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/main.c , STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/main.c , STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/main.c , STM32F10x_StdPeriph_Examples/RTC/Calendar/main.c , STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/main.c , STM32F10x_StdPeriph_Examples/USART/DMA_Polling/main.c , STM32F10x_StdPeriph_Examples/USART/HalfDuplex/main.c , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/main.c , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/main.c , STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c , STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/main.c , STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/main.c , STM32F10x_StdPeriph_Examples/USART/MultiProcessor/main.c , STM32F10x_StdPeriph_Examples/USART/Polling/main.c , STM32F10x_StdPeriph_Examples/USART/Printf/main.c , STM32F10x_StdPeriph_Examples/USART/Smartcard/main.c , STM32F10x_StdPeriph_Examples/USART/Synchronous/main.c , STM32F10x_StdPeriph_Template/main.c
  • USART_IrDACmd() : stm32f10x_usart.h , stm32f10x_usart.c
  • USART_IrDAConfig() : stm32f10x_usart.h , stm32f10x_usart.c
  • USART_IrDAMode_LowPower : stm32f10x_usart.h
  • USART_IrDAMode_Normal : stm32f10x_usart.h
  • USART_IT_CTS : stm32f10x_usart.h
  • USART_IT_ERR : stm32f10x_usart.h
  • USART_IT_FE : stm32f10x_usart.h
  • USART_IT_IDLE : stm32f10x_usart.h
  • USART_IT_LBD : stm32f10x_usart.h
  • USART_IT_NE : stm32f10x_usart.h
  • USART_IT_ORE : stm32f10x_usart.h
  • USART_IT_PE : stm32f10x_usart.h
  • USART_IT_RXNE : stm32f10x_usart.h
  • USART_IT_TC : stm32f10x_usart.h
  • USART_IT_TXE : stm32f10x_usart.h
  • USART_ITConfig() : stm32f10x_usart.h , stm32f10x_usart.c
  • USART_LastBit_Disable : stm32f10x_usart.h
  • USART_LastBit_Enable : stm32f10x_usart.h
  • USART_LINBreakDetectLength_10b : stm32f10x_usart.h
  • USART_LINBreakDetectLength_11b : stm32f10x_usart.h
  • USART_LINBreakDetectLengthConfig() : stm32f10x_usart.h , stm32f10x_usart.c
  • USART_LINCmd() : stm32f10x_usart.h , stm32f10x_usart.c
  • USART_Mode_Rx : stm32f10x_usart.h
  • USART_Mode_Tx : stm32f10x_usart.h
  • USART_OneBitMethodCmd() : stm32f10x_usart.h , stm32f10x_usart.c
  • USART_OverSampling8Cmd() : stm32f10x_usart.h , stm32f10x_usart.c
  • USART_Parity_Even : stm32f10x_usart.h
  • USART_Parity_No : stm32f10x_usart.h
  • USART_Parity_Odd : stm32f10x_usart.h
  • USART_ReceiveData() : stm32f10x_usart.h , stm32f10x_usart.c
  • USART_ReceiverWakeUpCmd() : stm32f10x_usart.h , stm32f10x_usart.c
  • USART_Scanf() : STM32F10x_StdPeriph_Examples/RTC/Calendar/main.c
  • USART_SendBreak() : stm32f10x_usart.h , stm32f10x_usart.c
  • USART_SendData() : stm32f10x_usart.h , stm32f10x_usart.c
  • USART_SetAddress() : stm32f10x_usart.h , stm32f10x_usart.c
  • USART_SetGuardTime() : stm32f10x_usart.h , stm32f10x_usart.c
  • USART_SetPrescaler() : stm32f10x_usart.h , stm32f10x_usart.c
  • USART_SmartCardCmd() : stm32f10x_usart.h , stm32f10x_usart.c
  • USART_SmartCardNACKCmd() : stm32f10x_usart.h , stm32f10x_usart.c
  • USART_SR_CTS : stm32f10x.h
  • USART_SR_FE : stm32f10x.h
  • USART_SR_IDLE : stm32f10x.h
  • USART_SR_LBD : stm32f10x.h
  • USART_SR_NE : stm32f10x.h
  • USART_SR_ORE : stm32f10x.h
  • USART_SR_PE : stm32f10x.h
  • USART_SR_RXNE : stm32f10x.h
  • USART_SR_TC : stm32f10x.h
  • USART_SR_TXE : stm32f10x.h
  • USART_StopBits_0_5 : stm32f10x_usart.h
  • USART_StopBits_1 : stm32f10x_usart.h
  • USART_StopBits_1_5 : stm32f10x_usart.h
  • USART_StopBits_2 : stm32f10x_usart.h
  • USART_StructInit() : stm32f10x_usart.h , stm32f10x_usart.c
  • USART_WakeUp_AddressMark : stm32f10x_usart.h
  • USART_WakeUp_IdleLine : stm32f10x_usart.h
  • USART_WakeUpConfig() : stm32f10x_usart.h , stm32f10x_usart.c
  • USART_WordLength_8b : stm32f10x_usart.h
  • USART_WordLength_9b : stm32f10x_usart.h
  • USARTx_IRQHandler : STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.c
  • USARTx_IRQn : STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/main.c
  • USARTy : USART/Interrupt/platform_config.h
  • USARTy_CLK : USART/Interrupt/platform_config.h
  • USARTy_DMA1_Channel : STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/main.c
  • USARTy_DMA1_IRQn : STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/main.c
  • USARTy_DR_Address : STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/main.c
  • USARTy_GPIO : USART/Interrupt/platform_config.h
  • USARTy_GPIO_CLK : USART/Interrupt/platform_config.h
  • USARTy_IRQHandler : USART/Interrupt/platform_config.h , STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.c
  • USARTy_IRQn : USART/Interrupt/platform_config.h
  • USARTy_RxPin : USART/Interrupt/platform_config.h
  • USARTy_TxPin : USART/Interrupt/platform_config.h
  • USARTz : USART/Interrupt/platform_config.h
  • USARTz_CLK : USART/Interrupt/platform_config.h
  • USARTz_GPIO : USART/Interrupt/platform_config.h
  • USARTz_GPIO_CLK : USART/Interrupt/platform_config.h
  • USARTz_IRQHandler : USART/Interrupt/platform_config.h , STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.c
  • USARTz_IRQn : USART/Interrupt/platform_config.h
  • USARTz_RxPin : USART/Interrupt/platform_config.h
  • USARTz_TxPin : USART/Interrupt/platform_config.h
  • USB_ADDR0_RX_ADDR0_RX : stm32f10x.h
  • USB_ADDR0_TX_ADDR0_TX : stm32f10x.h
  • USB_ADDR1_RX_ADDR1_RX : stm32f10x.h
  • USB_ADDR1_TX_ADDR1_TX : stm32f10x.h
  • USB_ADDR2_RX_ADDR2_RX : stm32f10x.h
  • USB_ADDR2_TX_ADDR2_TX : stm32f10x.h
  • USB_ADDR3_RX_ADDR3_RX : stm32f10x.h
  • USB_ADDR3_TX_ADDR3_TX : stm32f10x.h
  • USB_ADDR4_RX_ADDR4_RX : stm32f10x.h
  • USB_ADDR4_TX_ADDR4_TX : stm32f10x.h
  • USB_ADDR5_RX_ADDR5_RX : stm32f10x.h
  • USB_ADDR5_TX_ADDR5_TX : stm32f10x.h
  • USB_ADDR6_RX_ADDR6_RX : stm32f10x.h
  • USB_ADDR6_TX_ADDR6_TX : stm32f10x.h
  • USB_ADDR7_RX_ADDR7_RX : stm32f10x.h
  • USB_ADDR7_TX_ADDR7_TX : stm32f10x.h
  • USB_BTABLE_BTABLE : stm32f10x.h
  • USB_CNTR_CTRM : stm32f10x.h
  • USB_CNTR_ERRM : stm32f10x.h
  • USB_CNTR_ESOFM : stm32f10x.h
  • USB_CNTR_FRES : stm32f10x.h
  • USB_CNTR_FSUSP : stm32f10x.h
  • USB_CNTR_LP_MODE : stm32f10x.h
  • USB_CNTR_PDWN : stm32f10x.h
  • USB_CNTR_PMAOVRM : stm32f10x.h
  • USB_CNTR_RESETM : stm32f10x.h
  • USB_CNTR_RESUME : stm32f10x.h
  • USB_CNTR_SOFM : stm32f10x.h
  • USB_CNTR_SUSPM : stm32f10x.h
  • USB_CNTR_WKUPM : stm32f10x.h
  • USB_COUNT0_RX_0_BLSIZE_0 : stm32f10x.h
  • USB_COUNT0_RX_0_COUNT0_RX_0 : stm32f10x.h
  • USB_COUNT0_RX_0_NUM_BLOCK_0 : stm32f10x.h
  • USB_COUNT0_RX_0_NUM_BLOCK_0_0 : stm32f10x.h
  • USB_COUNT0_RX_0_NUM_BLOCK_0_1 : stm32f10x.h
  • USB_COUNT0_RX_0_NUM_BLOCK_0_2 : stm32f10x.h
  • USB_COUNT0_RX_0_NUM_BLOCK_0_3 : stm32f10x.h
  • USB_COUNT0_RX_0_NUM_BLOCK_0_4 : stm32f10x.h
  • USB_COUNT0_RX_1_BLSIZE_1 : stm32f10x.h
  • USB_COUNT0_RX_1_COUNT0_RX_1 : stm32f10x.h
  • USB_COUNT0_RX_1_NUM_BLOCK_1 : stm32f10x.h
  • USB_COUNT0_RX_1_NUM_BLOCK_1_0 : stm32f10x.h
  • USB_COUNT0_RX_1_NUM_BLOCK_1_1 : stm32f10x.h
  • USB_COUNT0_RX_1_NUM_BLOCK_1_2 : stm32f10x.h
  • USB_COUNT0_RX_1_NUM_BLOCK_1_3 : stm32f10x.h
  • USB_COUNT0_RX_1_NUM_BLOCK_1_4 : stm32f10x.h
  • USB_COUNT0_RX_BLSIZE : stm32f10x.h
  • USB_COUNT0_RX_COUNT0_RX : stm32f10x.h
  • USB_COUNT0_RX_NUM_BLOCK : stm32f10x.h
  • USB_COUNT0_RX_NUM_BLOCK_0 : stm32f10x.h
  • USB_COUNT0_RX_NUM_BLOCK_1 : stm32f10x.h
  • USB_COUNT0_RX_NUM_BLOCK_2 : stm32f10x.h
  • USB_COUNT0_RX_NUM_BLOCK_3 : stm32f10x.h
  • USB_COUNT0_RX_NUM_BLOCK_4 : stm32f10x.h
  • USB_COUNT0_TX_0_COUNT0_TX_0 : stm32f10x.h
  • USB_COUNT0_TX_1_COUNT0_TX_1 : stm32f10x.h
  • USB_COUNT0_TX_COUNT0_TX : stm32f10x.h
  • USB_COUNT1_RX_0_BLSIZE_0 : stm32f10x.h
  • USB_COUNT1_RX_0_COUNT1_RX_0 : stm32f10x.h
  • USB_COUNT1_RX_0_NUM_BLOCK_0 : stm32f10x.h
  • USB_COUNT1_RX_0_NUM_BLOCK_0_0 : stm32f10x.h
  • USB_COUNT1_RX_0_NUM_BLOCK_0_1 : stm32f10x.h
  • USB_COUNT1_RX_0_NUM_BLOCK_0_2 : stm32f10x.h
  • USB_COUNT1_RX_0_NUM_BLOCK_0_3 : stm32f10x.h
  • USB_COUNT1_RX_0_NUM_BLOCK_0_4 : stm32f10x.h
  • USB_COUNT1_RX_1_BLSIZE_1 : stm32f10x.h
  • USB_COUNT1_RX_1_COUNT1_RX_1 : stm32f10x.h
  • USB_COUNT1_RX_1_NUM_BLOCK_1 : stm32f10x.h
  • USB_COUNT1_RX_1_NUM_BLOCK_1_0 : stm32f10x.h
  • USB_COUNT1_RX_1_NUM_BLOCK_1_1 : stm32f10x.h
  • USB_COUNT1_RX_1_NUM_BLOCK_1_2 : stm32f10x.h
  • USB_COUNT1_RX_1_NUM_BLOCK_1_3 : stm32f10x.h
  • USB_COUNT1_RX_1_NUM_BLOCK_1_4 : stm32f10x.h
  • USB_COUNT1_RX_BLSIZE : stm32f10x.h
  • USB_COUNT1_RX_COUNT1_RX : stm32f10x.h
  • USB_COUNT1_RX_NUM_BLOCK : stm32f10x.h
  • USB_COUNT1_RX_NUM_BLOCK_0 : stm32f10x.h
  • USB_COUNT1_RX_NUM_BLOCK_1 : stm32f10x.h
  • USB_COUNT1_RX_NUM_BLOCK_2 : stm32f10x.h
  • USB_COUNT1_RX_NUM_BLOCK_3 : stm32f10x.h
  • USB_COUNT1_RX_NUM_BLOCK_4 : stm32f10x.h
  • USB_COUNT1_TX_0_COUNT1_TX_0 : stm32f10x.h
  • USB_COUNT1_TX_1_COUNT1_TX_1 : stm32f10x.h
  • USB_COUNT1_TX_COUNT1_TX : stm32f10x.h
  • USB_COUNT2_RX_0_BLSIZE_0 : stm32f10x.h
  • USB_COUNT2_RX_0_COUNT2_RX_0 : stm32f10x.h
  • USB_COUNT2_RX_0_NUM_BLOCK_0 : stm32f10x.h
  • USB_COUNT2_RX_0_NUM_BLOCK_0_0 : stm32f10x.h
  • USB_COUNT2_RX_0_NUM_BLOCK_0_1 : stm32f10x.h
  • USB_COUNT2_RX_0_NUM_BLOCK_0_2 : stm32f10x.h
  • USB_COUNT2_RX_0_NUM_BLOCK_0_3 : stm32f10x.h
  • USB_COUNT2_RX_0_NUM_BLOCK_0_4 : stm32f10x.h
  • USB_COUNT2_RX_1_BLSIZE_1 : stm32f10x.h
  • USB_COUNT2_RX_1_COUNT2_RX_1 : stm32f10x.h
  • USB_COUNT2_RX_1_NUM_BLOCK_1 : stm32f10x.h
  • USB_COUNT2_RX_1_NUM_BLOCK_1_0 : stm32f10x.h
  • USB_COUNT2_RX_1_NUM_BLOCK_1_1 : stm32f10x.h
  • USB_COUNT2_RX_1_NUM_BLOCK_1_2 : stm32f10x.h
  • USB_COUNT2_RX_1_NUM_BLOCK_1_3 : stm32f10x.h
  • USB_COUNT2_RX_1_NUM_BLOCK_1_4 : stm32f10x.h
  • USB_COUNT2_RX_BLSIZE : stm32f10x.h
  • USB_COUNT2_RX_COUNT2_RX : stm32f10x.h
  • USB_COUNT2_RX_NUM_BLOCK : stm32f10x.h
  • USB_COUNT2_RX_NUM_BLOCK_0 : stm32f10x.h
  • USB_COUNT2_RX_NUM_BLOCK_1 : stm32f10x.h
  • USB_COUNT2_RX_NUM_BLOCK_2 : stm32f10x.h
  • USB_COUNT2_RX_NUM_BLOCK_3 : stm32f10x.h
  • USB_COUNT2_RX_NUM_BLOCK_4 : stm32f10x.h
  • USB_COUNT2_TX_0_COUNT2_TX_0 : stm32f10x.h
  • USB_COUNT2_TX_1_COUNT2_TX_1 : stm32f10x.h
  • USB_COUNT2_TX_COUNT2_TX : stm32f10x.h
  • USB_COUNT3_RX_0_BLSIZE_0 : stm32f10x.h
  • USB_COUNT3_RX_0_COUNT3_RX_0 : stm32f10x.h
  • USB_COUNT3_RX_0_NUM_BLOCK_0 : stm32f10x.h
  • USB_COUNT3_RX_0_NUM_BLOCK_0_0 : stm32f10x.h
  • USB_COUNT3_RX_0_NUM_BLOCK_0_1 : stm32f10x.h
  • USB_COUNT3_RX_0_NUM_BLOCK_0_2 : stm32f10x.h
  • USB_COUNT3_RX_0_NUM_BLOCK_0_3 : stm32f10x.h
  • USB_COUNT3_RX_0_NUM_BLOCK_0_4 : stm32f10x.h
  • USB_COUNT3_RX_1_BLSIZE_1 : stm32f10x.h
  • USB_COUNT3_RX_1_COUNT3_RX_1 : stm32f10x.h
  • USB_COUNT3_RX_1_NUM_BLOCK_1 : stm32f10x.h
  • USB_COUNT3_RX_1_NUM_BLOCK_1_0 : stm32f10x.h
  • USB_COUNT3_RX_1_NUM_BLOCK_1_1 : stm32f10x.h
  • USB_COUNT3_RX_1_NUM_BLOCK_1_2 : stm32f10x.h
  • USB_COUNT3_RX_1_NUM_BLOCK_1_3 : stm32f10x.h
  • USB_COUNT3_RX_1_NUM_BLOCK_1_4 : stm32f10x.h
  • USB_COUNT3_RX_BLSIZE : stm32f10x.h
  • USB_COUNT3_RX_COUNT3_RX : stm32f10x.h
  • USB_COUNT3_RX_NUM_BLOCK : stm32f10x.h
  • USB_COUNT3_RX_NUM_BLOCK_0 : stm32f10x.h
  • USB_COUNT3_RX_NUM_BLOCK_1 : stm32f10x.h
  • USB_COUNT3_RX_NUM_BLOCK_2 : stm32f10x.h
  • USB_COUNT3_RX_NUM_BLOCK_3 : stm32f10x.h
  • USB_COUNT3_RX_NUM_BLOCK_4 : stm32f10x.h
  • USB_COUNT3_TX_0_COUNT3_TX_0 : stm32f10x.h
  • USB_COUNT3_TX_1_COUNT3_TX_1 : stm32f10x.h
  • USB_COUNT3_TX_COUNT3_TX : stm32f10x.h
  • USB_COUNT4_RX_0_BLSIZE_0 : stm32f10x.h
  • USB_COUNT4_RX_0_COUNT4_RX_0 : stm32f10x.h
  • USB_COUNT4_RX_0_NUM_BLOCK_0 : stm32f10x.h
  • USB_COUNT4_RX_0_NUM_BLOCK_0_0 : stm32f10x.h
  • USB_COUNT4_RX_0_NUM_BLOCK_0_1 : stm32f10x.h
  • USB_COUNT4_RX_0_NUM_BLOCK_0_2 : stm32f10x.h
  • USB_COUNT4_RX_0_NUM_BLOCK_0_3 : stm32f10x.h
  • USB_COUNT4_RX_0_NUM_BLOCK_0_4 : stm32f10x.h
  • USB_COUNT4_RX_1_BLSIZE_1 : stm32f10x.h
  • USB_COUNT4_RX_1_COUNT4_RX_1 : stm32f10x.h
  • USB_COUNT4_RX_1_NUM_BLOCK_1 : stm32f10x.h
  • USB_COUNT4_RX_1_NUM_BLOCK_1_0 : stm32f10x.h
  • USB_COUNT4_RX_1_NUM_BLOCK_1_1 : stm32f10x.h
  • USB_COUNT4_RX_1_NUM_BLOCK_1_2 : stm32f10x.h
  • USB_COUNT4_RX_1_NUM_BLOCK_1_3 : stm32f10x.h
  • USB_COUNT4_RX_1_NUM_BLOCK_1_4 : stm32f10x.h
  • USB_COUNT4_RX_BLSIZE : stm32f10x.h
  • USB_COUNT4_RX_COUNT4_RX : stm32f10x.h
  • USB_COUNT4_RX_NUM_BLOCK : stm32f10x.h
  • USB_COUNT4_RX_NUM_BLOCK_0 : stm32f10x.h
  • USB_COUNT4_RX_NUM_BLOCK_1 : stm32f10x.h
  • USB_COUNT4_RX_NUM_BLOCK_2 : stm32f10x.h
  • USB_COUNT4_RX_NUM_BLOCK_3 : stm32f10x.h
  • USB_COUNT4_RX_NUM_BLOCK_4 : stm32f10x.h
  • USB_COUNT4_TX_0_COUNT4_TX_0 : stm32f10x.h
  • USB_COUNT4_TX_1_COUNT4_TX_1 : stm32f10x.h
  • USB_COUNT4_TX_COUNT4_TX : stm32f10x.h
  • USB_COUNT5_RX_0_BLSIZE_0 : stm32f10x.h
  • USB_COUNT5_RX_0_COUNT5_RX_0 : stm32f10x.h
  • USB_COUNT5_RX_0_NUM_BLOCK_0 : stm32f10x.h
  • USB_COUNT5_RX_0_NUM_BLOCK_0_0 : stm32f10x.h
  • USB_COUNT5_RX_0_NUM_BLOCK_0_1 : stm32f10x.h
  • USB_COUNT5_RX_0_NUM_BLOCK_0_2 : stm32f10x.h
  • USB_COUNT5_RX_0_NUM_BLOCK_0_3 : stm32f10x.h
  • USB_COUNT5_RX_0_NUM_BLOCK_0_4 : stm32f10x.h
  • USB_COUNT5_RX_1_BLSIZE_1 : stm32f10x.h
  • USB_COUNT5_RX_1_COUNT5_RX_1 : stm32f10x.h
  • USB_COUNT5_RX_1_NUM_BLOCK_1 : stm32f10x.h
  • USB_COUNT5_RX_1_NUM_BLOCK_1_0 : stm32f10x.h
  • USB_COUNT5_RX_1_NUM_BLOCK_1_1 : stm32f10x.h
  • USB_COUNT5_RX_1_NUM_BLOCK_1_2 : stm32f10x.h
  • USB_COUNT5_RX_1_NUM_BLOCK_1_3 : stm32f10x.h
  • USB_COUNT5_RX_1_NUM_BLOCK_1_4 : stm32f10x.h
  • USB_COUNT5_RX_BLSIZE : stm32f10x.h
  • USB_COUNT5_RX_COUNT5_RX : stm32f10x.h
  • USB_COUNT5_RX_NUM_BLOCK : stm32f10x.h
  • USB_COUNT5_RX_NUM_BLOCK_0 : stm32f10x.h
  • USB_COUNT5_RX_NUM_BLOCK_1 : stm32f10x.h
  • USB_COUNT5_RX_NUM_BLOCK_2 : stm32f10x.h
  • USB_COUNT5_RX_NUM_BLOCK_3 : stm32f10x.h
  • USB_COUNT5_RX_NUM_BLOCK_4 : stm32f10x.h
  • USB_COUNT5_TX_0_COUNT5_TX_0 : stm32f10x.h
  • USB_COUNT5_TX_1_COUNT5_TX_1 : stm32f10x.h
  • USB_COUNT5_TX_COUNT5_TX : stm32f10x.h
  • USB_COUNT6_RX_0_BLSIZE_0 : stm32f10x.h
  • USB_COUNT6_RX_0_COUNT6_RX_0 : stm32f10x.h
  • USB_COUNT6_RX_0_NUM_BLOCK_0 : stm32f10x.h
  • USB_COUNT6_RX_0_NUM_BLOCK_0_0 : stm32f10x.h
  • USB_COUNT6_RX_0_NUM_BLOCK_0_1 : stm32f10x.h
  • USB_COUNT6_RX_0_NUM_BLOCK_0_2 : stm32f10x.h
  • USB_COUNT6_RX_0_NUM_BLOCK_0_3 : stm32f10x.h
  • USB_COUNT6_RX_0_NUM_BLOCK_0_4 : stm32f10x.h
  • USB_COUNT6_RX_1_BLSIZE_1 : stm32f10x.h
  • USB_COUNT6_RX_1_COUNT6_RX_1 : stm32f10x.h
  • USB_COUNT6_RX_1_NUM_BLOCK_1 : stm32f10x.h
  • USB_COUNT6_RX_1_NUM_BLOCK_1_0 : stm32f10x.h
  • USB_COUNT6_RX_1_NUM_BLOCK_1_1 : stm32f10x.h
  • USB_COUNT6_RX_1_NUM_BLOCK_1_2 : stm32f10x.h
  • USB_COUNT6_RX_1_NUM_BLOCK_1_3 : stm32f10x.h
  • USB_COUNT6_RX_1_NUM_BLOCK_1_4 : stm32f10x.h
  • USB_COUNT6_RX_BLSIZE : stm32f10x.h
  • USB_COUNT6_RX_COUNT6_RX : stm32f10x.h
  • USB_COUNT6_RX_NUM_BLOCK : stm32f10x.h
  • USB_COUNT6_RX_NUM_BLOCK_0 : stm32f10x.h
  • USB_COUNT6_RX_NUM_BLOCK_1 : stm32f10x.h
  • USB_COUNT6_RX_NUM_BLOCK_2 : stm32f10x.h
  • USB_COUNT6_RX_NUM_BLOCK_3 : stm32f10x.h
  • USB_COUNT6_RX_NUM_BLOCK_4 : stm32f10x.h
  • USB_COUNT6_TX_0_COUNT6_TX_0 : stm32f10x.h
  • USB_COUNT6_TX_1_COUNT6_TX_1 : stm32f10x.h
  • USB_COUNT6_TX_COUNT6_TX : stm32f10x.h
  • USB_COUNT7_RX_0_BLSIZE_0 : stm32f10x.h
  • USB_COUNT7_RX_0_COUNT7_RX_0 : stm32f10x.h
  • USB_COUNT7_RX_0_NUM_BLOCK_0 : stm32f10x.h
  • USB_COUNT7_RX_0_NUM_BLOCK_0_0 : stm32f10x.h
  • USB_COUNT7_RX_0_NUM_BLOCK_0_1 : stm32f10x.h
  • USB_COUNT7_RX_0_NUM_BLOCK_0_2 : stm32f10x.h
  • USB_COUNT7_RX_0_NUM_BLOCK_0_3 : stm32f10x.h
  • USB_COUNT7_RX_0_NUM_BLOCK_0_4 : stm32f10x.h
  • USB_COUNT7_RX_1_BLSIZE_1 : stm32f10x.h
  • USB_COUNT7_RX_1_COUNT7_RX_1 : stm32f10x.h
  • USB_COUNT7_RX_1_NUM_BLOCK_1 : stm32f10x.h
  • USB_COUNT7_RX_1_NUM_BLOCK_1_0 : stm32f10x.h
  • USB_COUNT7_RX_1_NUM_BLOCK_1_1 : stm32f10x.h
  • USB_COUNT7_RX_1_NUM_BLOCK_1_2 : stm32f10x.h
  • USB_COUNT7_RX_1_NUM_BLOCK_1_3 : stm32f10x.h
  • USB_COUNT7_RX_1_NUM_BLOCK_1_4 : stm32f10x.h
  • USB_COUNT7_RX_BLSIZE : stm32f10x.h
  • USB_COUNT7_RX_COUNT7_RX : stm32f10x.h
  • USB_COUNT7_RX_NUM_BLOCK : stm32f10x.h
  • USB_COUNT7_RX_NUM_BLOCK_0 : stm32f10x.h
  • USB_COUNT7_RX_NUM_BLOCK_1 : stm32f10x.h
  • USB_COUNT7_RX_NUM_BLOCK_2 : stm32f10x.h
  • USB_COUNT7_RX_NUM_BLOCK_3 : stm32f10x.h
  • USB_COUNT7_RX_NUM_BLOCK_4 : stm32f10x.h
  • USB_COUNT7_TX_0_COUNT7_TX_0 : stm32f10x.h
  • USB_COUNT7_TX_1_COUNT7_TX_1 : stm32f10x.h
  • USB_COUNT7_TX_COUNT7_TX : stm32f10x.h
  • USB_DADDR_ADD : stm32f10x.h
  • USB_DADDR_ADD0 : stm32f10x.h
  • USB_DADDR_ADD1 : stm32f10x.h
  • USB_DADDR_ADD2 : stm32f10x.h
  • USB_DADDR_ADD3 : stm32f10x.h
  • USB_DADDR_ADD4 : stm32f10x.h
  • USB_DADDR_ADD5 : stm32f10x.h
  • USB_DADDR_ADD6 : stm32f10x.h
  • USB_DADDR_EF : stm32f10x.h
  • USB_EP0R_CTR_RX : stm32f10x.h
  • USB_EP0R_CTR_TX : stm32f10x.h
  • USB_EP0R_DTOG_RX : stm32f10x.h
  • USB_EP0R_DTOG_TX : stm32f10x.h
  • USB_EP0R_EA : stm32f10x.h
  • USB_EP0R_EP_KIND : stm32f10x.h
  • USB_EP0R_EP_TYPE : stm32f10x.h
  • USB_EP0R_EP_TYPE_0 : stm32f10x.h
  • USB_EP0R_EP_TYPE_1 : stm32f10x.h
  • USB_EP0R_SETUP : stm32f10x.h
  • USB_EP0R_STAT_RX : stm32f10x.h
  • USB_EP0R_STAT_RX_0 : stm32f10x.h
  • USB_EP0R_STAT_RX_1 : stm32f10x.h
  • USB_EP0R_STAT_TX : stm32f10x.h
  • USB_EP0R_STAT_TX_0 : stm32f10x.h
  • USB_EP0R_STAT_TX_1 : stm32f10x.h
  • USB_EP1R_CTR_RX : stm32f10x.h
  • USB_EP1R_CTR_TX : stm32f10x.h
  • USB_EP1R_DTOG_RX : stm32f10x.h
  • USB_EP1R_DTOG_TX : stm32f10x.h
  • USB_EP1R_EA : stm32f10x.h
  • USB_EP1R_EP_KIND : stm32f10x.h
  • USB_EP1R_EP_TYPE : stm32f10x.h
  • USB_EP1R_EP_TYPE_0 : stm32f10x.h
  • USB_EP1R_EP_TYPE_1 : stm32f10x.h
  • USB_EP1R_SETUP : stm32f10x.h
  • USB_EP1R_STAT_RX : stm32f10x.h
  • USB_EP1R_STAT_RX_0 : stm32f10x.h
  • USB_EP1R_STAT_RX_1 : stm32f10x.h
  • USB_EP1R_STAT_TX : stm32f10x.h
  • USB_EP1R_STAT_TX_0 : stm32f10x.h
  • USB_EP1R_STAT_TX_1 : stm32f10x.h
  • USB_EP2R_CTR_RX : stm32f10x.h
  • USB_EP2R_CTR_TX : stm32f10x.h
  • USB_EP2R_DTOG_RX : stm32f10x.h
  • USB_EP2R_DTOG_TX : stm32f10x.h
  • USB_EP2R_EA : stm32f10x.h
  • USB_EP2R_EP_KIND : stm32f10x.h
  • USB_EP2R_EP_TYPE : stm32f10x.h
  • USB_EP2R_EP_TYPE_0 : stm32f10x.h
  • USB_EP2R_EP_TYPE_1 : stm32f10x.h
  • USB_EP2R_SETUP : stm32f10x.h
  • USB_EP2R_STAT_RX : stm32f10x.h
  • USB_EP2R_STAT_RX_0 : stm32f10x.h
  • USB_EP2R_STAT_RX_1 : stm32f10x.h
  • USB_EP2R_STAT_TX : stm32f10x.h
  • USB_EP2R_STAT_TX_0 : stm32f10x.h
  • USB_EP2R_STAT_TX_1 : stm32f10x.h
  • USB_EP3R_CTR_RX : stm32f10x.h
  • USB_EP3R_CTR_TX : stm32f10x.h
  • USB_EP3R_DTOG_RX : stm32f10x.h
  • USB_EP3R_DTOG_TX : stm32f10x.h
  • USB_EP3R_EA : stm32f10x.h
  • USB_EP3R_EP_KIND : stm32f10x.h
  • USB_EP3R_EP_TYPE : stm32f10x.h
  • USB_EP3R_EP_TYPE_0 : stm32f10x.h
  • USB_EP3R_EP_TYPE_1 : stm32f10x.h
  • USB_EP3R_SETUP : stm32f10x.h
  • USB_EP3R_STAT_RX : stm32f10x.h
  • USB_EP3R_STAT_RX_0 : stm32f10x.h
  • USB_EP3R_STAT_RX_1 : stm32f10x.h
  • USB_EP3R_STAT_TX : stm32f10x.h
  • USB_EP3R_STAT_TX_0 : stm32f10x.h
  • USB_EP3R_STAT_TX_1 : stm32f10x.h
  • USB_EP4R_CTR_RX : stm32f10x.h
  • USB_EP4R_CTR_TX : stm32f10x.h
  • USB_EP4R_DTOG_RX : stm32f10x.h
  • USB_EP4R_DTOG_TX : stm32f10x.h
  • USB_EP4R_EA : stm32f10x.h
  • USB_EP4R_EP_KIND : stm32f10x.h
  • USB_EP4R_EP_TYPE : stm32f10x.h
  • USB_EP4R_EP_TYPE_0 : stm32f10x.h
  • USB_EP4R_EP_TYPE_1 : stm32f10x.h
  • USB_EP4R_SETUP : stm32f10x.h
  • USB_EP4R_STAT_RX : stm32f10x.h
  • USB_EP4R_STAT_RX_0 : stm32f10x.h
  • USB_EP4R_STAT_RX_1 : stm32f10x.h
  • USB_EP4R_STAT_TX : stm32f10x.h
  • USB_EP4R_STAT_TX_0 : stm32f10x.h
  • USB_EP4R_STAT_TX_1 : stm32f10x.h
  • USB_EP5R_CTR_RX : stm32f10x.h
  • USB_EP5R_CTR_TX : stm32f10x.h
  • USB_EP5R_DTOG_RX : stm32f10x.h
  • USB_EP5R_DTOG_TX : stm32f10x.h
  • USB_EP5R_EA : stm32f10x.h
  • USB_EP5R_EP_KIND : stm32f10x.h
  • USB_EP5R_EP_TYPE : stm32f10x.h
  • USB_EP5R_EP_TYPE_0 : stm32f10x.h
  • USB_EP5R_EP_TYPE_1 : stm32f10x.h
  • USB_EP5R_SETUP : stm32f10x.h
  • USB_EP5R_STAT_RX : stm32f10x.h
  • USB_EP5R_STAT_RX_0 : stm32f10x.h
  • USB_EP5R_STAT_RX_1 : stm32f10x.h
  • USB_EP5R_STAT_TX : stm32f10x.h
  • USB_EP5R_STAT_TX_0 : stm32f10x.h
  • USB_EP5R_STAT_TX_1 : stm32f10x.h
  • USB_EP6R_CTR_RX : stm32f10x.h
  • USB_EP6R_CTR_TX : stm32f10x.h
  • USB_EP6R_DTOG_RX : stm32f10x.h
  • USB_EP6R_DTOG_TX : stm32f10x.h
  • USB_EP6R_EA : stm32f10x.h
  • USB_EP6R_EP_KIND : stm32f10x.h
  • USB_EP6R_EP_TYPE : stm32f10x.h
  • USB_EP6R_EP_TYPE_0 : stm32f10x.h
  • USB_EP6R_EP_TYPE_1 : stm32f10x.h
  • USB_EP6R_SETUP : stm32f10x.h
  • USB_EP6R_STAT_RX : stm32f10x.h
  • USB_EP6R_STAT_RX_0 : stm32f10x.h
  • USB_EP6R_STAT_RX_1 : stm32f10x.h
  • USB_EP6R_STAT_TX : stm32f10x.h
  • USB_EP6R_STAT_TX_0 : stm32f10x.h
  • USB_EP6R_STAT_TX_1 : stm32f10x.h
  • USB_EP7R_CTR_RX : stm32f10x.h
  • USB_EP7R_CTR_TX : stm32f10x.h
  • USB_EP7R_DTOG_RX : stm32f10x.h
  • USB_EP7R_DTOG_TX : stm32f10x.h
  • USB_EP7R_EA : stm32f10x.h
  • USB_EP7R_EP_KIND : stm32f10x.h
  • USB_EP7R_EP_TYPE : stm32f10x.h
  • USB_EP7R_EP_TYPE_0 : stm32f10x.h
  • USB_EP7R_EP_TYPE_1 : stm32f10x.h
  • USB_EP7R_SETUP : stm32f10x.h
  • USB_EP7R_STAT_RX : stm32f10x.h
  • USB_EP7R_STAT_RX_0 : stm32f10x.h
  • USB_EP7R_STAT_RX_1 : stm32f10x.h
  • USB_EP7R_STAT_TX : stm32f10x.h
  • USB_EP7R_STAT_TX_0 : stm32f10x.h
  • USB_EP7R_STAT_TX_1 : stm32f10x.h
  • USB_FNR_FN : stm32f10x.h
  • USB_FNR_LCK : stm32f10x.h
  • USB_FNR_LSOF : stm32f10x.h
  • USB_FNR_RXDM : stm32f10x.h
  • USB_FNR_RXDP : stm32f10x.h
  • USB_ISTR_CTR : stm32f10x.h
  • USB_ISTR_DIR : stm32f10x.h
  • USB_ISTR_EP_ID : stm32f10x.h
  • USB_ISTR_ERR : stm32f10x.h
  • USB_ISTR_ESOF : stm32f10x.h
  • USB_ISTR_PMAOVR : stm32f10x.h
  • USB_ISTR_RESET : stm32f10x.h
  • USB_ISTR_SOF : stm32f10x.h
  • USB_ISTR_SUSP : stm32f10x.h
  • USB_ISTR_WKUP : stm32f10x.h
  • USB_LP_CAN1_RX0_IRQHandler() : STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_it.c
  • USBPRE_BitNumber : stm32f10x_rcc.c
  • USE_DEFAULT_CRITICAL_CALLBACK : stm32_eval_i2c_ee.h
  • USE_FULL_ASSERT : STM32F10x_StdPeriph_Examples/I2C/EEPROM/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/stm32f10x_conf.h
  • USE_STM32100E_EVAL : USART/IrDA/Transmit/platform_config.h , USART/Interrupt/platform_config.h
  • USE_STM3210C_EVAL : USART/Smartcard/platform_config.h , CAN/Networking/platform_config.h , SPI/Simplex_Interrupt/platform_config.h , USART/Polling/platform_config.h , USART/DMA_Interrupt/platform_config.h , USART/IrDA/Receive/platform_config.h , USART/HalfDuplex/platform_config.h , USART/MultiProcessor/platform_config.h , DMA/SPI_RAM/platform_config.h , SPI/DMA/platform_config.h , SPI/FullDuplex_SoftNSS/platform_config.h , USART/DMA_Polling/platform_config.h
  • USE_STM3210E_EVAL : USART/Synchronous/platform_config.h , USART/HyperTerminal_HwFlowControl/platform_config.h


STM32F10x Standard Peripherals Firmware Library: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • j
  • k
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w
  • y
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- v -

  • Var : STM32F10x_StdPeriph_Examples/CortexM3/BitBand/main.c
  • Var_GetBit_BB : STM32F10x_StdPeriph_Examples/CortexM3/BitBand/main.c
  • Var_ResetBit_BB : STM32F10x_StdPeriph_Examples/CortexM3/BitBand/main.c
  • Var_SetBit_BB : STM32F10x_StdPeriph_Examples/CortexM3/BitBand/main.c
  • VarAddr : STM32F10x_StdPeriph_Examples/CortexM3/BitBand/main.c
  • VarBitValue : STM32F10x_StdPeriph_Examples/CortexM3/BitBand/main.c
  • VBAT_DIV_PIN : stm3210c_eval_ioe.h
  • VECT_TAB_OFFSET : Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/BKP/Tamper/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/SDIO/uSDCard/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/SPI/CRC/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/SPI/DMA/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Template/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/Synchronous/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/Smartcard/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/Printf/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/Polling/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/MultiProcessor/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/CAN/DualCAN/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/HalfDuplex/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/DMA_Polling/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/TimeBase/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Output/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Input/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/OnePulse/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/OCToggle/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/OCActive/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/InputCapture/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/DMABurst/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/DMA/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/SysTick/TimeBase/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/6Steps/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/CAN/LoopBack/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/FLASH/Program/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/RTC/Calendar/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/PWR/STOP/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/PWR/STANDBY/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/PWR/PVD/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/I2S/Interrupt/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/I2C/IOExpander/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/I2C/EEPROM/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/GPIO/IOToggle/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/FSMC/OneNAND/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/OCInactive/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/CAN/Networking/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/FSMC/NAND/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/FSMC/NOR/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/CortexM3/BitBand/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/DMA/FSMC/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/Interrupt/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/CortexM3/MPU/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/BKP/Backup_Data/system_stm32f10x.c
  • Vertical : stm32_eval.h
  • vs16 : stm32f10x.h
  • vs32 : stm32f10x.h
  • vs8 : stm32f10x.h
  • vsc16 : stm32f10x.h
  • vsc32 : stm32f10x.h
  • vsc8 : stm32f10x.h
  • vu16 : stm32f10x.h
  • vu32 : stm32f10x.h
  • vu8 : stm32f10x.h
  • vuc16 : stm32f10x.h
  • vuc32 : stm32f10x.h
  • vuc8 : stm32f10x.h


STM32F10x Standard Peripherals Firmware Library: Globals

  • File List
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- w -

  • WAKEUP_BUTTON_EXTI_IRQn : stm32100b_eval.h , stm32100e_eval.h , stm3210c_eval.h , stm3210e_eval.h , stm3210b_eval.h
  • WAKEUP_BUTTON_EXTI_LINE : stm3210b_eval.h , stm3210c_eval.h , stm3210e_eval.h , stm32100b_eval.h , stm32100e_eval.h
  • WAKEUP_BUTTON_EXTI_PIN_SOURCE : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210c_eval.h , stm3210e_eval.h
  • WAKEUP_BUTTON_EXTI_PORT_SOURCE : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210c_eval.h , stm3210e_eval.h
  • WAKEUP_BUTTON_GPIO_CLK : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210c_eval.h , stm3210e_eval.h
  • WAKEUP_BUTTON_GPIO_PORT : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210c_eval.h , stm3210e_eval.h
  • WAKEUP_BUTTON_PIN : stm32100e_eval.h , stm3210b_eval.h , stm3210c_eval.h , stm3210e_eval.h , stm32100b_eval.h
  • White : stm32_eval.h
  • WRITE_PROTECTION_DISABLE : STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/main.c
  • WRITE_READ_ADDR : STM32F10x_StdPeriph_Examples/FSMC/NOR/main.c , STM32F10x_StdPeriph_Examples/FSMC/SRAM/main.c
  • WRITE_REG : stm32f10x.h
  • WriteReadAddr : STM32F10x_StdPeriph_Examples/FSMC/NAND/main.c
  • WriteReadStatus : STM32F10x_StdPeriph_Examples/FSMC/NAND/main.c , STM32F10x_StdPeriph_Examples/FSMC/NOR/main.c , STM32F10x_StdPeriph_Examples/FSMC/SRAM/main.c
  • WriteToBackupReg() : STM32F10x_StdPeriph_Examples/BKP/Backup_Data/main.c , STM32F10x_StdPeriph_Examples/BKP/Tamper/main.c
  • WRP0_Mask : stm32f10x_flash.c
  • WRP1_Mask : stm32f10x_flash.c
  • WRP2_Mask : stm32f10x_flash.c
  • WRP3_Mask : stm32f10x_flash.c
  • WRPR_Value : STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/main.c
  • WWDG : stm32f10x.h
  • WWDG_BASE : stm32f10x.h
  • WWDG_CFR_EWI : stm32f10x.h
  • WWDG_CFR_W : stm32f10x.h
  • WWDG_CFR_W0 : stm32f10x.h
  • WWDG_CFR_W1 : stm32f10x.h
  • WWDG_CFR_W2 : stm32f10x.h
  • WWDG_CFR_W3 : stm32f10x.h
  • WWDG_CFR_W4 : stm32f10x.h
  • WWDG_CFR_W5 : stm32f10x.h
  • WWDG_CFR_W6 : stm32f10x.h
  • WWDG_CFR_WDGTB : stm32f10x.h
  • WWDG_CFR_WDGTB0 : stm32f10x.h
  • WWDG_CFR_WDGTB1 : stm32f10x.h
  • WWDG_ClearFlag() : stm32f10x_wwdg.h , stm32f10x_wwdg.c
  • WWDG_CR_T : stm32f10x.h
  • WWDG_CR_T0 : stm32f10x.h
  • WWDG_CR_T1 : stm32f10x.h
  • WWDG_CR_T2 : stm32f10x.h
  • WWDG_CR_T3 : stm32f10x.h
  • WWDG_CR_T4 : stm32f10x.h
  • WWDG_CR_T5 : stm32f10x.h
  • WWDG_CR_T6 : stm32f10x.h
  • WWDG_CR_WDGA : stm32f10x.h
  • WWDG_DBG : stm32f10x_ip_dbg.c
  • WWDG_DeInit() : stm32f10x_wwdg.h , stm32f10x_wwdg.c
  • WWDG_Enable() : stm32f10x_wwdg.c , stm32f10x_wwdg.h
  • WWDG_EnableIT() : stm32f10x_wwdg.h , stm32f10x_wwdg.c
  • WWDG_GetFlagStatus() : stm32f10x_wwdg.h , stm32f10x_wwdg.c
  • WWDG_IRQn : stm32f10x.h
  • WWDG_OFFSET : stm32f10x_wwdg.c
  • WWDG_Prescaler_1 : stm32f10x_wwdg.h
  • WWDG_Prescaler_2 : stm32f10x_wwdg.h
  • WWDG_Prescaler_4 : stm32f10x_wwdg.h
  • WWDG_Prescaler_8 : stm32f10x_wwdg.h
  • WWDG_SetCounter() : stm32f10x_wwdg.h , stm32f10x_wwdg.c
  • WWDG_SetPrescaler() : stm32f10x_wwdg.c , stm32f10x_wwdg.h
  • WWDG_SetWindowValue() : stm32f10x_wwdg.c , stm32f10x_wwdg.h
  • WWDG_SR_EWIF : stm32f10x.h


STM32F10x Standard Peripherals Firmware Library: Globals

  • File List
  • Globals
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  • Functions
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  • o
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  • y
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- y -

  • Yellow : stm32_eval.h


STM32F10x Standard Peripherals Firmware Library: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
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  • d
  • e
  • f
  • g
  • h
  • i
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- _ -

  • __CAN1_USED__ : STM32F10x_StdPeriph_Examples/CAN/LoopBack/main.c , STM32F10x_StdPeriph_Examples/CAN/Networking/main.c
  • __MPU_PRESENT : stm32f10x.h
  • __NVIC_PRIO_BITS : stm32f10x.h
  • __STM32F10X_STDPERIPH_VERSION : stm32f10x.h
  • __STM32F10X_STDPERIPH_VERSION_MAIN : stm32f10x.h
  • __STM32F10X_STDPERIPH_VERSION_RC : stm32f10x.h
  • __STM32F10X_STDPERIPH_VERSION_SUB1 : stm32f10x.h
  • __STM32F10X_STDPERIPH_VERSION_SUB2 : stm32f10x.h
  • __Vendor_SysTickConfig : stm32f10x.h
  • _delay_ : stm3210c_eval_ioe.h , stm32l152_eval_lcd.h , stm3210b_eval_lcd.h , stm3210e_eval_lcd.h , stm32100b_eval_lcd.h , stm32100e_eval_ioe.h , stm32100e_eval_lcd.h , stm3210c_eval_lcd.h


STM32F10x Standard Peripherals Firmware Library: Globals

  • File List
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  • Functions
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  • Typedefs
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- j -

  • JDR_Offset : stm32f10x_adc.c
  • JOY_CENTER : stm32_eval.h
  • JOY_IO_DOWN : stm3210c_eval_ioe.h
  • JOY_IO_LEFT : stm3210c_eval_ioe.h
  • JOY_IO_NONE : stm3210c_eval_ioe.h
  • JOY_IO_PINS : stm3210c_eval_ioe.h
  • JOY_IO_RIGHT : stm3210c_eval_ioe.h
  • JOY_IO_SEL : stm3210c_eval_ioe.h
  • JOY_IO_UP : stm3210c_eval_ioe.h
  • JOY_State_TypeDef : stm32_eval.h
  • JSQR_JL_Reset : stm32f10x_adc.c
  • JSQR_JL_Set : stm32f10x_adc.c
  • JSQR_JSQ_Set : stm32f10x_adc.c


STM32F10x Standard Peripherals Firmware Library: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • j
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- k -

  • KEY_BUTTON_EXTI_IRQn : stm32100b_eval.h , stm32100e_eval.h , stm3210c_eval.h , stm3210e_eval.h , stm3210b_eval.h , stm32l152_eval.h
  • KEY_BUTTON_EXTI_LINE : stm32100e_eval.h , stm3210b_eval.h , stm3210c_eval.h , stm3210e_eval.h , stm32l152_eval.h , stm32100b_eval.h
  • KEY_BUTTON_EXTI_PIN_SOURCE : stm3210c_eval.h , stm3210e_eval.h , stm32l152_eval.h , stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h
  • KEY_BUTTON_EXTI_PORT_SOURCE : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210c_eval.h , stm3210e_eval.h , stm32l152_eval.h
  • KEY_BUTTON_GPIO_CLK : stm3210b_eval.h , stm32100b_eval.h , stm32100e_eval.h , stm3210c_eval.h , stm3210e_eval.h , stm32l152_eval.h
  • KEY_BUTTON_GPIO_PORT : stm32100e_eval.h , stm3210b_eval.h , stm3210c_eval.h , stm32l152_eval.h , stm32100b_eval.h , stm3210e_eval.h
  • KEY_BUTTON_PIN : stm32l152_eval.h , stm3210c_eval.h , stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210e_eval.h
  • KEY_NOT_PRESSED : STM32F10x_StdPeriph_Examples/CAN/Networking/main.c
  • KEY_PRESSED : STM32F10x_StdPeriph_Examples/CAN/Networking/main.c
  • KR_KEY_Enable : stm32f10x_iwdg.c
  • KR_KEY_Reload : stm32f10x_iwdg.c


STM32F10x Standard Peripherals Firmware Library: Globals

  • File List
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- l -

  • LCD : stm32100e_eval_lcd.c , stm3210e_eval_lcd.c
  • LCD_BASE : stm3210e_eval_lcd.c , stm32100e_eval_lcd.c
  • LCD_COLOR_BLACK : stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32100b_eval_lcd.h , stm32l152_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h
  • LCD_COLOR_BLUE : stm32l152_eval_lcd.h , stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h
  • LCD_COLOR_BLUE2 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_COLOR_CYAN : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_COLOR_GREEN : stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h , stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h
  • LCD_COLOR_GREY : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_COLOR_MAGENTA : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_COLOR_RED : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_COLOR_WHITE : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_COLOR_YELLOW : stm32l152_eval_lcd.h , stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h
  • LCD_DEFAULT_FONT : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_DIR_HORIZONTAL : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_DIR_VERTICAL : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_HX8312 : stm32100b_eval_lcd.c , stm3210b_eval_lcd.c
  • LCD_ILI9320 : stm32100b_eval_lcd.c , stm3210b_eval_lcd.c , stm32l152_eval_lcd.c
  • LCD_LINE_0 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_LINE_1 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_LINE_10 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_LINE_11 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_LINE_12 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_LINE_13 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_LINE_14 : stm3210e_eval_lcd.h , stm32l152_eval_lcd.h , stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h
  • LCD_LINE_15 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_LINE_16 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_LINE_17 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_LINE_18 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_LINE_19 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_LINE_2 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_LINE_20 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_LINE_21 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_LINE_22 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_LINE_23 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_LINE_24 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_LINE_25 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_LINE_26 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_LINE_27 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_LINE_28 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_LINE_29 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_LINE_3 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_LINE_4 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_LINE_5 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_LINE_6 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_LINE_7 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_LINE_8 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_LINE_9 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_NCS_GPIO_CLK : stm32100b_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_NCS_GPIO_PORT : stm32100b_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_NCS_PIN : stm32100b_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_NWR_GPIO_CLK : stm32100b_eval_lcd.h , stm3210b_eval_lcd.h
  • LCD_NWR_GPIO_PORT : stm32100b_eval_lcd.h , stm3210b_eval_lcd.h
  • LCD_NWR_PIN : stm32100b_eval_lcd.h , stm3210b_eval_lcd.h
  • LCD_PIXEL_HEIGHT : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_PIXEL_WIDTH : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_READ_REG : stm32100b_eval_lcd.c , stm3210b_eval_lcd.c , stm3210c_eval_lcd.c , stm32l152_eval_lcd.c
  • LCD_REG_0 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_1 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_10 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_106 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_118 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_12 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_128 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_129 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_13 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_130 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_131 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_132 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_133 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_134 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_135 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_136 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_137 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_139 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_14 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_140 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_141 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_143 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_144 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_145 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_146 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_147 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_148 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_149 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_15 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_150 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_151 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_152 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_153 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_154 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_157 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_16 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_17 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_18 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_19 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_192 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_193 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_2 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_20 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_21 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_22 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_227 : stm32100b_eval_lcd.h , stm3210b_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_229 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_23 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_231 : stm32100b_eval_lcd.h , stm3210b_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_239 : stm32100b_eval_lcd.h , stm3210b_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_24 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_25 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_26 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_27 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_28 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_29 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_3 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_30 : stm3210e_eval_lcd.h , stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_31 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_32 : stm32100b_eval_lcd.h , stm3210e_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_33 : stm3210b_eval_lcd.h , stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_34 : stm3210e_eval_lcd.h , stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_36 : stm3210b_eval_lcd.h , stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_37 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_4 : stm3210b_eval_lcd.h , stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_40 : stm3210e_eval_lcd.h , stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_41 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_43 : stm32100b_eval_lcd.h , stm3210e_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_45 : stm3210b_eval_lcd.h , stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_48 : stm3210e_eval_lcd.h , stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_49 : stm3210b_eval_lcd.h , stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_5 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_50 : stm3210b_eval_lcd.h , stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_51 : stm3210e_eval_lcd.h , stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_52 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_53 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm32l152_eval_lcd.h , stm3210e_eval_lcd.h
  • LCD_REG_54 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h , stm3210b_eval_lcd.h
  • LCD_REG_55 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm32l152_eval_lcd.h , stm3210e_eval_lcd.h
  • LCD_REG_56 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h , stm3210b_eval_lcd.h
  • LCD_REG_57 : stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h , stm32100b_eval_lcd.h
  • LCD_REG_58 : stm32100e_eval_lcd.h , stm3210e_eval_lcd.h
  • LCD_REG_59 : stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm32l152_eval_lcd.h , stm3210e_eval_lcd.h , stm32100b_eval_lcd.h
  • LCD_REG_6 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h , stm3210b_eval_lcd.h
  • LCD_REG_60 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm32l152_eval_lcd.h , stm3210e_eval_lcd.h
  • LCD_REG_61 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h , stm3210b_eval_lcd.h
  • LCD_REG_62 : stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h , stm32100b_eval_lcd.h
  • LCD_REG_63 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h , stm3210b_eval_lcd.h
  • LCD_REG_64 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm32l152_eval_lcd.h , stm3210e_eval_lcd.h
  • LCD_REG_65 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_66 : stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm32l152_eval_lcd.h , stm3210e_eval_lcd.h , stm32100b_eval_lcd.h
  • LCD_REG_67 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h , stm3210b_eval_lcd.h
  • LCD_REG_68 : stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_69 : stm3210e_eval_lcd.h , stm3210b_eval_lcd.h , stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210c_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_7 : stm3210e_eval_lcd.h , stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_70 : stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm32l152_eval_lcd.h , stm32100b_eval_lcd.h , stm3210e_eval_lcd.h , stm32100e_eval_lcd.h
  • LCD_REG_71 : stm3210b_eval_lcd.h , stm3210e_eval_lcd.h , stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm32l152_eval_lcd.h , stm3210c_eval_lcd.h
  • LCD_REG_72 : stm3210b_eval_lcd.h , stm32100e_eval_lcd.h , stm32l152_eval_lcd.h , stm32100b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h
  • LCD_REG_73 : stm3210e_eval_lcd.h , stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210c_eval_lcd.h , stm32l152_eval_lcd.h , stm3210b_eval_lcd.h
  • LCD_REG_74 : stm32100b_eval_lcd.h , stm3210b_eval_lcd.h , stm32l152_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32100e_eval_lcd.h
  • LCD_REG_75 : stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm32l152_eval_lcd.h , stm3210b_eval_lcd.h
  • LCD_REG_76 : stm32l152_eval_lcd.h , stm3210e_eval_lcd.h , stm3210b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210c_eval_lcd.h , stm32100b_eval_lcd.h
  • LCD_REG_77 : stm3210e_eval_lcd.h , stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_78 : stm3210e_eval_lcd.h , stm3210b_eval_lcd.h , stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210c_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_79 : stm3210c_eval_lcd.h , stm3210b_eval_lcd.h , stm3210e_eval_lcd.h , stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_8 : stm3210e_eval_lcd.h , stm32l152_eval_lcd.h , stm3210b_eval_lcd.h , stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210c_eval_lcd.h
  • LCD_REG_80 : stm3210b_eval_lcd.h , stm3210e_eval_lcd.h , stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210c_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_81 : stm32100e_eval_lcd.h , stm32100b_eval_lcd.h , stm3210b_eval_lcd.h , stm32l152_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h
  • LCD_REG_82 : stm3210b_eval_lcd.h , stm3210e_eval_lcd.h , stm32100b_eval_lcd.h , stm3210c_eval_lcd.h , stm32100e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_83 : stm3210b_eval_lcd.h , stm32100b_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h , stm32100e_eval_lcd.h , stm3210c_eval_lcd.h
  • LCD_REG_9 : stm3210e_eval_lcd.h , stm32100b_eval_lcd.h , stm3210c_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_REG_96 : stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210e_eval_lcd.h , stm32100b_eval_lcd.h , stm32l152_eval_lcd.h , stm3210c_eval_lcd.h
  • LCD_REG_97 : stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_RS_GPIO_CLK : stm32100b_eval_lcd.h , stm3210b_eval_lcd.h
  • LCD_RS_GPIO_PORT : stm32100b_eval_lcd.h , stm3210b_eval_lcd.h
  • LCD_RS_PIN : stm32100b_eval_lcd.h , stm3210b_eval_lcd.h
  • LCD_RSNWR_GPIO_CLK : stm32_eval.h
  • LCD_SPFD5408 : stm3210b_eval_lcd.c , stm32100b_eval_lcd.c , stm32l152_eval_lcd.c
  • LCD_SPI : stm3210c_eval_lcd.h , stm32l152_eval_lcd.h , stm32100b_eval_lcd.h , stm3210b_eval_lcd.h
  • LCD_SPI_CLK : stm32100b_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_SPI_GPIO_CLK : stm32_eval.h
  • LCD_SPI_GPIO_PORT : stm32_eval.h
  • LCD_SPI_MISO_AF : stm32l152_eval_lcd.h
  • LCD_SPI_MISO_GPIO_CLK : stm32100b_eval_lcd.h , stm3210b_eval_lcd.h , stm32l152_eval_lcd.h , stm3210c_eval_lcd.h
  • LCD_SPI_MISO_GPIO_PORT : stm32l152_eval_lcd.h , stm3210b_eval_lcd.h , stm32100b_eval_lcd.h , stm3210c_eval_lcd.h
  • LCD_SPI_MISO_PIN : stm32100b_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_SPI_MISO_SOURCE : stm32l152_eval_lcd.h
  • LCD_SPI_MOSI_AF : stm32l152_eval_lcd.h
  • LCD_SPI_MOSI_GPIO_CLK : stm32l152_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm32100b_eval_lcd.h
  • LCD_SPI_MOSI_GPIO_PORT : stm3210b_eval_lcd.h , stm32l152_eval_lcd.h , stm32100b_eval_lcd.h , stm3210c_eval_lcd.h
  • LCD_SPI_MOSI_PIN : stm3210b_eval_lcd.h , stm32100b_eval_lcd.h , stm3210c_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_SPI_MOSI_SOURCE : stm32l152_eval_lcd.h
  • LCD_SPI_SCK_AF : stm32l152_eval_lcd.h
  • LCD_SPI_SCK_GPIO_CLK : stm32100b_eval_lcd.h , stm32l152_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h
  • LCD_SPI_SCK_GPIO_PORT : stm3210b_eval_lcd.h , stm32l152_eval_lcd.h , stm32100b_eval_lcd.h , stm3210c_eval_lcd.h
  • LCD_SPI_SCK_PIN : stm3210c_eval_lcd.h , stm3210b_eval_lcd.h , stm32100b_eval_lcd.h , stm32l152_eval_lcd.h
  • LCD_SPI_SCK_SOURCE : stm32l152_eval_lcd.h
  • LCD_WRITE_REG : stm3210b_eval_lcd.c , stm32100b_eval_lcd.c , stm3210c_eval_lcd.c , stm32l152_eval_lcd.c
  • LED1_GPIO_CLK : stm32100e_eval.h , stm32l152_eval.h , stm3210c_eval.h , stm3210e_eval.h , stm32100b_eval.h , stm3210b_eval.h
  • LED1_GPIO_PORT : stm3210c_eval.h , stm32100b_eval.h , stm32l152_eval.h , stm3210b_eval.h , stm3210e_eval.h , stm32100e_eval.h
  • LED1_PIN : stm32100e_eval.h , stm3210c_eval.h , stm32l152_eval.h , stm32100b_eval.h , stm3210e_eval.h , stm3210b_eval.h
  • LED2_GPIO_CLK : stm3210c_eval.h , stm3210b_eval.h , stm3210e_eval.h , stm32100e_eval.h , stm32100b_eval.h , stm32l152_eval.h
  • LED2_GPIO_PORT : stm32l152_eval.h , stm32100e_eval.h , stm3210c_eval.h , stm3210b_eval.h , stm32100b_eval.h , stm3210e_eval.h
  • LED2_PIN : stm3210c_eval.h , stm32100e_eval.h , stm3210e_eval.h , stm32100b_eval.h , stm3210b_eval.h , stm32l152_eval.h
  • LED3_GPIO_CLK : stm32100e_eval.h , stm3210e_eval.h , stm3210b_eval.h , stm32100b_eval.h , stm3210c_eval.h , stm32l152_eval.h
  • LED3_GPIO_PORT : stm32100b_eval.h , stm3210e_eval.h , stm3210b_eval.h , stm32l152_eval.h , stm3210c_eval.h , stm32100e_eval.h
  • LED3_PIN : stm3210e_eval.h , stm32l152_eval.h , stm3210b_eval.h , stm3210c_eval.h , stm32100e_eval.h , stm32100b_eval.h
  • LED4_GPIO_CLK : stm32l152_eval.h , stm3210b_eval.h , stm32100e_eval.h , stm3210e_eval.h , stm32100b_eval.h , stm3210c_eval.h
  • LED4_GPIO_PORT : stm32l152_eval.h , stm32100e_eval.h , stm3210e_eval.h , stm3210b_eval.h , stm32100b_eval.h , stm3210c_eval.h
  • LED4_PIN : stm3210c_eval.h , stm3210b_eval.h , stm32100b_eval.h , stm32l152_eval.h , stm3210e_eval.h , stm32100e_eval.h
  • LEDn : stm3210b_eval.h , stm3210c_eval.h , stm3210e_eval.h , stm32100b_eval.h , stm32l152_eval.h , stm32100e_eval.h
  • LEFT_BUTTON_EXTI_IRQn : stm32100b_eval.h , stm3210b_eval.h , stm32l152_eval.h , stm3210e_eval.h , stm32100e_eval.h
  • LEFT_BUTTON_EXTI_LINE : stm32l152_eval.h , stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210e_eval.h
  • LEFT_BUTTON_EXTI_PIN_SOURCE : stm3210e_eval.h , stm3210b_eval.h , stm32l152_eval.h , stm32100b_eval.h , stm32100e_eval.h
  • LEFT_BUTTON_EXTI_PORT_SOURCE : stm3210b_eval.h , stm32l152_eval.h , stm32100b_eval.h , stm3210e_eval.h , stm32100e_eval.h
  • LEFT_BUTTON_GPIO_CLK : stm3210e_eval.h , stm32l152_eval.h , stm3210b_eval.h , stm32100b_eval.h , stm32100e_eval.h
  • LEFT_BUTTON_GPIO_PORT : stm32l152_eval.h , stm3210b_eval.h , stm3210e_eval.h , stm32100e_eval.h , stm32100b_eval.h
  • LEFT_BUTTON_PIN : stm32100e_eval.h , stm3210e_eval.h , stm32100b_eval.h , stm32l152_eval.h , stm3210b_eval.h
  • LINE : fonts.h
  • Line0 : stm32_eval.h
  • Line1 : stm32_eval.h
  • Line2 : stm32_eval.h
  • Line3 : stm32_eval.h
  • Line4 : stm32_eval.h
  • Line5 : stm32_eval.h
  • Line6 : stm32_eval.h
  • Line7 : stm32_eval.h
  • Line8 : stm32_eval.h
  • Line9 : stm32_eval.h
  • LM75_ADDR : stm32_eval_i2c_tsensor.h
  • LM75_DMA_CLK : stm32100b_eval.h , stm3210e_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm32l152_eval.h
  • LM75_DMA_RX_CHANNEL : stm32l152_eval.h , stm3210b_eval.h , stm32100e_eval.h , stm32100b_eval.h , stm3210e_eval.h
  • LM75_DMA_RX_TCFLAG : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm32l152_eval.h , stm3210e_eval.h
  • LM75_DMA_TX_CHANNEL : stm3210e_eval.h , stm32100e_eval.h , stm32100b_eval.h , stm3210b_eval.h , stm32l152_eval.h
  • LM75_DMA_TX_TCFLAG : stm32100e_eval.h , stm32100b_eval.h , stm3210b_eval.h , stm32l152_eval.h , stm3210e_eval.h
  • LM75_FLAG_TIMEOUT : stm32_eval_i2c_tsensor.h
  • LM75_I2C : stm3210b_eval.h , stm32100e_eval.h , stm3210e_eval.h , stm32100b_eval.h , stm32l152_eval.h
  • LM75_I2C_CLK : stm3210e_eval.h , stm32100e_eval.h , stm32l152_eval.h , stm3210b_eval.h , stm32100b_eval.h
  • LM75_I2C_DR : stm32100b_eval.h , stm3210b_eval.h , stm32100e_eval.h , stm3210e_eval.h , stm32l152_eval.h
  • LM75_I2C_SCL_AF : stm32l152_eval.h
  • LM75_I2C_SCL_GPIO_CLK : stm32l152_eval.h , stm32100e_eval.h , stm32100b_eval.h , stm3210b_eval.h , stm3210e_eval.h
  • LM75_I2C_SCL_GPIO_PORT : stm32l152_eval.h , stm3210e_eval.h , stm3210b_eval.h , stm32100b_eval.h , stm32100e_eval.h
  • LM75_I2C_SCL_PIN : stm3210b_eval.h , stm32l152_eval.h , stm32100e_eval.h , stm3210e_eval.h , stm32100b_eval.h
  • LM75_I2C_SCL_SOURCE : stm32l152_eval.h
  • LM75_I2C_SDA_AF : stm32l152_eval.h
  • LM75_I2C_SDA_GPIO_CLK : stm3210b_eval.h , stm32100b_eval.h , stm32l152_eval.h , stm32100e_eval.h , stm3210e_eval.h
  • LM75_I2C_SDA_GPIO_PORT : stm3210b_eval.h , stm32100b_eval.h , stm3210e_eval.h , stm32100e_eval.h , stm32l152_eval.h
  • LM75_I2C_SDA_PIN : stm3210b_eval.h , stm32l152_eval.h , stm32100b_eval.h , stm32100e_eval.h , stm3210e_eval.h
  • LM75_I2C_SDA_SOURCE : stm32l152_eval.h
  • LM75_I2C_SMBUSALERT_AF : stm32l152_eval.h
  • LM75_I2C_SMBUSALERT_GPIO_CLK : stm3210e_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm32100b_eval.h , stm32l152_eval.h
  • LM75_I2C_SMBUSALERT_GPIO_PORT : stm3210b_eval.h , stm32100b_eval.h , stm32100e_eval.h , stm32l152_eval.h , stm3210e_eval.h
  • LM75_I2C_SMBUSALERT_PIN : stm32100b_eval.h , stm32l152_eval.h , stm32100e_eval.h , stm3210e_eval.h , stm3210b_eval.h
  • LM75_I2C_SMBUSALERT_SOURCE : stm32l152_eval.h
  • LM75_I2C_SPEED : stm32_eval_i2c_tsensor.h
  • LM75_LONG_TIMEOUT : stm32_eval_i2c_tsensor.h
  • LM75_REG_CONF : stm32_eval_i2c_tsensor.h
  • LM75_REG_TEMP : stm32_eval_i2c_tsensor.h
  • LM75_REG_THYS : stm32_eval_i2c_tsensor.h
  • LM75_REG_TOS : stm32_eval_i2c_tsensor.h
  • LM75_SD_RESET : stm32_eval_i2c_tsensor.c
  • LM75_SD_SET : stm32_eval_i2c_tsensor.c
  • LM75_TIMEOUT_UserCallback : stm32_eval_i2c_tsensor.h
  • LSB_MASK : stm32f10x_gpio.c
  • LSI_TIM_MEASURE : STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/main.c
  • LSION_BitNumber : stm32f10x_rcc.c


STM32F10x Standard Peripherals Firmware Library: Globals

  • File List
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- m -

  • Magenta : stm32_eval.h
  • MAPR_MII_RMII_SEL_BB : stm32f10x_gpio.c
  • MAPR_OFFSET : stm32f10x_gpio.c
  • MAX_POLY_CORNERS : stm32100b_eval_lcd.c , stm3210e_eval_lcd.c , stm32l152_eval_lcd.c , stm32100e_eval_lcd.c , stm3210b_eval_lcd.c , stm3210c_eval_lcd.c
  • MCR_DBF : stm32f10x_can.c
  • MEMS_INT1_PIN : stm3210c_eval_ioe.h
  • MEMS_INT2_PIN : stm3210c_eval_ioe.h
  • MESSAGE1 : STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/main.c
  • MESSAGE10 : STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/main.c
  • MESSAGE11 : STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/main.c
  • MESSAGE12 : STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/main.c
  • MESSAGE2 : STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/main.c , STM32F10x_StdPeriph_Examples/I2C/IOExpander/main.c
  • MESSAGE3 : STM32F10x_StdPeriph_Examples/I2C/IOExpander/main.c , STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/main.c
  • MESSAGE5 : STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/main.c
  • MESSAGE6 : STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/main.c
  • MESSAGE7 : STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/main.c
  • MESSAGE8 : STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/main.c
  • MESSAGE9 : STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/main.c
  • MII_INT_PIN : stm3210c_eval_ioe.h
  • MII_RMII_SEL_BitNumber : stm32f10x_gpio.c
  • Mode_EXTI : stm32_eval.h
  • Mode_GPIO : stm32_eval.h
  • MODIFY_REG : stm32f10x.h
  • MULTI_BUFFER_SIZE : STM32F10x_StdPeriph_Examples/SDIO/uSDCard/main.c
  • MY_DEVICE_ADDRESS : STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_conf.h


STM32F10x Standard Peripherals Firmware Library: Globals

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- n -

  • NAND_BLOCK_SIZE : stm3210e_eval_fsmc_nand.h
  • NAND_BUSY : stm3210e_eval_fsmc_nand.h
  • NAND_CMD_AREA_A : stm3210e_eval_fsmc_nand.h
  • NAND_CMD_AREA_B : stm3210e_eval_fsmc_nand.h
  • NAND_CMD_AREA_C : stm3210e_eval_fsmc_nand.h
  • NAND_CMD_ERASE0 : stm3210e_eval_fsmc_nand.h
  • NAND_CMD_ERASE1 : stm3210e_eval_fsmc_nand.h
  • NAND_CMD_LOCK_STATUS : stm3210e_eval_fsmc_nand.h
  • NAND_CMD_READID : stm3210e_eval_fsmc_nand.h
  • NAND_CMD_RESET : stm3210e_eval_fsmc_nand.h
  • NAND_CMD_STATUS : stm3210e_eval_fsmc_nand.h
  • NAND_CMD_WRITE0 : stm3210e_eval_fsmc_nand.h
  • NAND_CMD_WRITE_TRUE1 : stm3210e_eval_fsmc_nand.h
  • NAND_ERROR : stm3210e_eval_fsmc_nand.h
  • NAND_INVALID_ADDRESS : stm3210e_eval_fsmc_nand.h
  • NAND_MAX_ZONE : stm3210e_eval_fsmc_nand.h
  • NAND_PAGE_SIZE : stm3210e_eval_fsmc_nand.h
  • NAND_READY : stm3210e_eval_fsmc_nand.h
  • NAND_SPARE_AREA_SIZE : stm3210e_eval_fsmc_nand.h
  • NAND_ST_DeviceID : STM32F10x_StdPeriph_Examples/FSMC/NAND/main.c
  • NAND_ST_MakerID : STM32F10x_StdPeriph_Examples/FSMC/NAND/main.c
  • NAND_TIMEOUT_ERROR : stm3210e_eval_fsmc_nand.h
  • NAND_VALID_ADDRESS : stm3210e_eval_fsmc_nand.h
  • NAND_ZONE_SIZE : stm3210e_eval_fsmc_nand.h
  • NIEN_BitNumber : stm32f10x_sdio.c
  • NOR_WRITE : stm3210e_eval_fsmc_nor.c
  • NULL : stm32_eval_sdio_sd.c
  • NUMBER_OF_BLOCKS : STM32F10x_StdPeriph_Examples/SDIO/uSDCard/main.c
  • NVIC_IABR_ACTIVE : stm32f10x.h
  • NVIC_IABR_ACTIVE_0 : stm32f10x.h
  • NVIC_IABR_ACTIVE_1 : stm32f10x.h
  • NVIC_IABR_ACTIVE_10 : stm32f10x.h
  • NVIC_IABR_ACTIVE_11 : stm32f10x.h
  • NVIC_IABR_ACTIVE_12 : stm32f10x.h
  • NVIC_IABR_ACTIVE_13 : stm32f10x.h
  • NVIC_IABR_ACTIVE_14 : stm32f10x.h
  • NVIC_IABR_ACTIVE_15 : stm32f10x.h
  • NVIC_IABR_ACTIVE_16 : stm32f10x.h
  • NVIC_IABR_ACTIVE_17 : stm32f10x.h
  • NVIC_IABR_ACTIVE_18 : stm32f10x.h
  • NVIC_IABR_ACTIVE_19 : stm32f10x.h
  • NVIC_IABR_ACTIVE_2 : stm32f10x.h
  • NVIC_IABR_ACTIVE_20 : stm32f10x.h
  • NVIC_IABR_ACTIVE_21 : stm32f10x.h
  • NVIC_IABR_ACTIVE_22 : stm32f10x.h
  • NVIC_IABR_ACTIVE_23 : stm32f10x.h
  • NVIC_IABR_ACTIVE_24 : stm32f10x.h
  • NVIC_IABR_ACTIVE_25 : stm32f10x.h
  • NVIC_IABR_ACTIVE_26 : stm32f10x.h
  • NVIC_IABR_ACTIVE_27 : stm32f10x.h
  • NVIC_IABR_ACTIVE_28 : stm32f10x.h
  • NVIC_IABR_ACTIVE_29 : stm32f10x.h
  • NVIC_IABR_ACTIVE_3 : stm32f10x.h
  • NVIC_IABR_ACTIVE_30 : stm32f10x.h
  • NVIC_IABR_ACTIVE_31 : stm32f10x.h
  • NVIC_IABR_ACTIVE_4 : stm32f10x.h
  • NVIC_IABR_ACTIVE_5 : stm32f10x.h
  • NVIC_IABR_ACTIVE_6 : stm32f10x.h
  • NVIC_IABR_ACTIVE_7 : stm32f10x.h
  • NVIC_IABR_ACTIVE_8 : stm32f10x.h
  • NVIC_IABR_ACTIVE_9 : stm32f10x.h
  • NVIC_ICER_CLRENA : stm32f10x.h
  • NVIC_ICER_CLRENA_0 : stm32f10x.h
  • NVIC_ICER_CLRENA_1 : stm32f10x.h
  • NVIC_ICER_CLRENA_10 : stm32f10x.h
  • NVIC_ICER_CLRENA_11 : stm32f10x.h
  • NVIC_ICER_CLRENA_12 : stm32f10x.h
  • NVIC_ICER_CLRENA_13 : stm32f10x.h
  • NVIC_ICER_CLRENA_14 : stm32f10x.h
  • NVIC_ICER_CLRENA_15 : stm32f10x.h
  • NVIC_ICER_CLRENA_16 : stm32f10x.h
  • NVIC_ICER_CLRENA_17 : stm32f10x.h
  • NVIC_ICER_CLRENA_18 : stm32f10x.h
  • NVIC_ICER_CLRENA_19 : stm32f10x.h
  • NVIC_ICER_CLRENA_2 : stm32f10x.h
  • NVIC_ICER_CLRENA_20 : stm32f10x.h
  • NVIC_ICER_CLRENA_21 : stm32f10x.h
  • NVIC_ICER_CLRENA_22 : stm32f10x.h
  • NVIC_ICER_CLRENA_23 : stm32f10x.h
  • NVIC_ICER_CLRENA_24 : stm32f10x.h
  • NVIC_ICER_CLRENA_25 : stm32f10x.h
  • NVIC_ICER_CLRENA_26 : stm32f10x.h
  • NVIC_ICER_CLRENA_27 : stm32f10x.h
  • NVIC_ICER_CLRENA_28 : stm32f10x.h
  • NVIC_ICER_CLRENA_29 : stm32f10x.h
  • NVIC_ICER_CLRENA_3 : stm32f10x.h
  • NVIC_ICER_CLRENA_30 : stm32f10x.h
  • NVIC_ICER_CLRENA_31 : stm32f10x.h
  • NVIC_ICER_CLRENA_4 : stm32f10x.h
  • NVIC_ICER_CLRENA_5 : stm32f10x.h
  • NVIC_ICER_CLRENA_6 : stm32f10x.h
  • NVIC_ICER_CLRENA_7 : stm32f10x.h
  • NVIC_ICER_CLRENA_8 : stm32f10x.h
  • NVIC_ICER_CLRENA_9 : stm32f10x.h
  • NVIC_ICPR_CLRPEND : stm32f10x.h
  • NVIC_ICPR_CLRPEND_0 : stm32f10x.h
  • NVIC_ICPR_CLRPEND_1 : stm32f10x.h
  • NVIC_ICPR_CLRPEND_10 : stm32f10x.h
  • NVIC_ICPR_CLRPEND_11 : stm32f10x.h
  • NVIC_ICPR_CLRPEND_12 : stm32f10x.h
  • NVIC_ICPR_CLRPEND_13 : stm32f10x.h
  • NVIC_ICPR_CLRPEND_14 : stm32f10x.h
  • NVIC_ICPR_CLRPEND_15 : stm32f10x.h
  • NVIC_ICPR_CLRPEND_16 : stm32f10x.h
  • NVIC_ICPR_CLRPEND_17 : stm32f10x.h
  • NVIC_ICPR_CLRPEND_18 : stm32f10x.h
  • NVIC_ICPR_CLRPEND_19 : stm32f10x.h
  • NVIC_ICPR_CLRPEND_2 : stm32f10x.h
  • NVIC_ICPR_CLRPEND_20 : stm32f10x.h
  • NVIC_ICPR_CLRPEND_21 : stm32f10x.h
  • NVIC_ICPR_CLRPEND_22 : stm32f10x.h
  • NVIC_ICPR_CLRPEND_23 : stm32f10x.h
  • NVIC_ICPR_CLRPEND_24 : stm32f10x.h
  • NVIC_ICPR_CLRPEND_25 : stm32f10x.h
  • NVIC_ICPR_CLRPEND_26 : stm32f10x.h
  • NVIC_ICPR_CLRPEND_27 : stm32f10x.h
  • NVIC_ICPR_CLRPEND_28 : stm32f10x.h
  • NVIC_ICPR_CLRPEND_29 : stm32f10x.h
  • NVIC_ICPR_CLRPEND_3 : stm32f10x.h
  • NVIC_ICPR_CLRPEND_30 : stm32f10x.h
  • NVIC_ICPR_CLRPEND_31 : stm32f10x.h
  • NVIC_ICPR_CLRPEND_4 : stm32f10x.h
  • NVIC_ICPR_CLRPEND_5 : stm32f10x.h
  • NVIC_ICPR_CLRPEND_6 : stm32f10x.h
  • NVIC_ICPR_CLRPEND_7 : stm32f10x.h
  • NVIC_ICPR_CLRPEND_8 : stm32f10x.h
  • NVIC_ICPR_CLRPEND_9 : stm32f10x.h
  • NVIC_IPR0_PRI_0 : stm32f10x.h
  • NVIC_IPR0_PRI_1 : stm32f10x.h
  • NVIC_IPR0_PRI_2 : stm32f10x.h
  • NVIC_IPR0_PRI_3 : stm32f10x.h
  • NVIC_IPR1_PRI_4 : stm32f10x.h
  • NVIC_IPR1_PRI_5 : stm32f10x.h
  • NVIC_IPR1_PRI_6 : stm32f10x.h
  • NVIC_IPR1_PRI_7 : stm32f10x.h
  • NVIC_IPR2_PRI_10 : stm32f10x.h
  • NVIC_IPR2_PRI_11 : stm32f10x.h
  • NVIC_IPR2_PRI_8 : stm32f10x.h
  • NVIC_IPR2_PRI_9 : stm32f10x.h
  • NVIC_IPR3_PRI_12 : stm32f10x.h
  • NVIC_IPR3_PRI_13 : stm32f10x.h
  • NVIC_IPR3_PRI_14 : stm32f10x.h
  • NVIC_IPR3_PRI_15 : stm32f10x.h
  • NVIC_IPR4_PRI_16 : stm32f10x.h
  • NVIC_IPR4_PRI_17 : stm32f10x.h
  • NVIC_IPR4_PRI_18 : stm32f10x.h
  • NVIC_IPR4_PRI_19 : stm32f10x.h
  • NVIC_IPR5_PRI_20 : stm32f10x.h
  • NVIC_IPR5_PRI_21 : stm32f10x.h
  • NVIC_IPR5_PRI_22 : stm32f10x.h
  • NVIC_IPR5_PRI_23 : stm32f10x.h
  • NVIC_IPR6_PRI_24 : stm32f10x.h
  • NVIC_IPR6_PRI_25 : stm32f10x.h
  • NVIC_IPR6_PRI_26 : stm32f10x.h
  • NVIC_IPR6_PRI_27 : stm32f10x.h
  • NVIC_IPR7_PRI_28 : stm32f10x.h
  • NVIC_IPR7_PRI_29 : stm32f10x.h
  • NVIC_IPR7_PRI_30 : stm32f10x.h
  • NVIC_IPR7_PRI_31 : stm32f10x.h
  • NVIC_ISER_SETENA : stm32f10x.h
  • NVIC_ISER_SETENA_0 : stm32f10x.h
  • NVIC_ISER_SETENA_1 : stm32f10x.h
  • NVIC_ISER_SETENA_10 : stm32f10x.h
  • NVIC_ISER_SETENA_11 : stm32f10x.h
  • NVIC_ISER_SETENA_12 : stm32f10x.h
  • NVIC_ISER_SETENA_13 : stm32f10x.h
  • NVIC_ISER_SETENA_14 : stm32f10x.h
  • NVIC_ISER_SETENA_15 : stm32f10x.h
  • NVIC_ISER_SETENA_16 : stm32f10x.h
  • NVIC_ISER_SETENA_17 : stm32f10x.h
  • NVIC_ISER_SETENA_18 : stm32f10x.h
  • NVIC_ISER_SETENA_19 : stm32f10x.h
  • NVIC_ISER_SETENA_2 : stm32f10x.h
  • NVIC_ISER_SETENA_20 : stm32f10x.h
  • NVIC_ISER_SETENA_21 : stm32f10x.h
  • NVIC_ISER_SETENA_22 : stm32f10x.h
  • NVIC_ISER_SETENA_23 : stm32f10x.h
  • NVIC_ISER_SETENA_24 : stm32f10x.h
  • NVIC_ISER_SETENA_25 : stm32f10x.h
  • NVIC_ISER_SETENA_26 : stm32f10x.h
  • NVIC_ISER_SETENA_27 : stm32f10x.h
  • NVIC_ISER_SETENA_28 : stm32f10x.h
  • NVIC_ISER_SETENA_29 : stm32f10x.h
  • NVIC_ISER_SETENA_3 : stm32f10x.h
  • NVIC_ISER_SETENA_30 : stm32f10x.h
  • NVIC_ISER_SETENA_31 : stm32f10x.h
  • NVIC_ISER_SETENA_4 : stm32f10x.h
  • NVIC_ISER_SETENA_5 : stm32f10x.h
  • NVIC_ISER_SETENA_6 : stm32f10x.h
  • NVIC_ISER_SETENA_7 : stm32f10x.h
  • NVIC_ISER_SETENA_8 : stm32f10x.h
  • NVIC_ISER_SETENA_9 : stm32f10x.h
  • NVIC_ISPR_SETPEND : stm32f10x.h
  • NVIC_ISPR_SETPEND_0 : stm32f10x.h
  • NVIC_ISPR_SETPEND_1 : stm32f10x.h
  • NVIC_ISPR_SETPEND_10 : stm32f10x.h
  • NVIC_ISPR_SETPEND_11 : stm32f10x.h
  • NVIC_ISPR_SETPEND_12 : stm32f10x.h
  • NVIC_ISPR_SETPEND_13 : stm32f10x.h
  • NVIC_ISPR_SETPEND_14 : stm32f10x.h
  • NVIC_ISPR_SETPEND_15 : stm32f10x.h
  • NVIC_ISPR_SETPEND_16 : stm32f10x.h
  • NVIC_ISPR_SETPEND_17 : stm32f10x.h
  • NVIC_ISPR_SETPEND_18 : stm32f10x.h
  • NVIC_ISPR_SETPEND_19 : stm32f10x.h
  • NVIC_ISPR_SETPEND_2 : stm32f10x.h
  • NVIC_ISPR_SETPEND_20 : stm32f10x.h
  • NVIC_ISPR_SETPEND_21 : stm32f10x.h
  • NVIC_ISPR_SETPEND_22 : stm32f10x.h
  • NVIC_ISPR_SETPEND_23 : stm32f10x.h
  • NVIC_ISPR_SETPEND_24 : stm32f10x.h
  • NVIC_ISPR_SETPEND_25 : stm32f10x.h
  • NVIC_ISPR_SETPEND_26 : stm32f10x.h
  • NVIC_ISPR_SETPEND_27 : stm32f10x.h
  • NVIC_ISPR_SETPEND_28 : stm32f10x.h
  • NVIC_ISPR_SETPEND_29 : stm32f10x.h
  • NVIC_ISPR_SETPEND_3 : stm32f10x.h
  • NVIC_ISPR_SETPEND_30 : stm32f10x.h
  • NVIC_ISPR_SETPEND_31 : stm32f10x.h
  • NVIC_ISPR_SETPEND_4 : stm32f10x.h
  • NVIC_ISPR_SETPEND_5 : stm32f10x.h
  • NVIC_ISPR_SETPEND_6 : stm32f10x.h
  • NVIC_ISPR_SETPEND_7 : stm32f10x.h
  • NVIC_ISPR_SETPEND_8 : stm32f10x.h
  • NVIC_ISPR_SETPEND_9 : stm32f10x.h
  • NVIC_LP_SEVONPEND : misc.h
  • NVIC_LP_SLEEPDEEP : misc.h
  • NVIC_LP_SLEEPONEXIT : misc.h
  • NVIC_PriorityGroup_0 : misc.h
  • NVIC_PriorityGroup_1 : misc.h
  • NVIC_PriorityGroup_2 : misc.h
  • NVIC_PriorityGroup_3 : misc.h
  • NVIC_PriorityGroup_4 : misc.h
  • NVIC_VectTab_FLASH : misc.h
  • NVIC_VectTab_RAM : misc.h


STM32F10x Standard Peripherals Firmware Library: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
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- o -

  • OAR1_ADD0_Reset : stm32f10x_i2c.c
  • OAR1_ADD0_Set : stm32f10x_i2c.c
  • OAR2_ADD2_Reset : stm32f10x_i2c.c
  • OAR2_ENDUAL_Reset : stm32f10x_i2c.c
  • OAR2_ENDUAL_Set : stm32f10x_i2c.c
  • OB : stm32f10x.h
  • OB_BASE : stm32f10x.h
  • OB_IWDG_HW : stm32f10x_flash.h
  • OB_IWDG_SW : stm32f10x_flash.h
  • OB_STDBY_NoRST : stm32f10x_flash.h
  • OB_STDBY_RST : stm32f10x_flash.h
  • OB_STOP_NoRST : stm32f10x_flash.h
  • OB_STOP_RST : stm32f10x_flash.h
  • OB_USER_BFB2 : stm32f10x_flash.c
  • ONENAND_BOOTPARTITION_ADDR : stm32100e_eval_fsmc_onenand.c
  • OneNAND_BUFFER_SIZE : STM32F10x_StdPeriph_Examples/FSMC/OneNAND/main.c
  • OneNAND_CMD_ERASE : stm32100e_eval_fsmc_onenand.h
  • OneNAND_CMD_LOAD : stm32100e_eval_fsmc_onenand.h
  • OneNAND_CMD_PROGRAM : stm32100e_eval_fsmc_onenand.h
  • OneNAND_CMD_READ_ID : stm32100e_eval_fsmc_onenand.h
  • OneNAND_CMD_RESET : stm32100e_eval_fsmc_onenand.h
  • OneNAND_CMD_UNLOCK : stm32100e_eval_fsmc_onenand.h
  • OneNAND_DATA_RAM_0_0_ADD : stm32100e_eval_fsmc_onenand.h
  • OneNAND_DATA_RAM_0_0_REG : stm32100e_eval_fsmc_onenand.h
  • OneNAND_DATA_RAM_0_1_ADD : stm32100e_eval_fsmc_onenand.h
  • OneNAND_DATA_RAM_0_1_REG : stm32100e_eval_fsmc_onenand.h
  • OneNAND_DATA_RAM_0_2_ADD : stm32100e_eval_fsmc_onenand.h
  • OneNAND_DATA_RAM_0_2_REG : stm32100e_eval_fsmc_onenand.h
  • OneNAND_DATA_RAM_0_3_ADD : stm32100e_eval_fsmc_onenand.h
  • OneNAND_DATA_RAM_0_3_REG : stm32100e_eval_fsmc_onenand.h
  • OneNAND_DATA_RAM_1_0_ADD : stm32100e_eval_fsmc_onenand.h
  • OneNAND_DATA_RAM_1_0_REG : stm32100e_eval_fsmc_onenand.h
  • OneNAND_DATA_RAM_1_1_ADD : stm32100e_eval_fsmc_onenand.h
  • OneNAND_DATA_RAM_1_1_REG : stm32100e_eval_fsmc_onenand.h
  • OneNAND_DATA_RAM_1_2_ADD : stm32100e_eval_fsmc_onenand.h
  • OneNAND_DATA_RAM_1_2_REG : stm32100e_eval_fsmc_onenand.h
  • OneNAND_DATA_RAM_1_3_ADD : stm32100e_eval_fsmc_onenand.h
  • OneNAND_DATA_RAM_1_3_REG : stm32100e_eval_fsmc_onenand.h
  • OneNAND_NUMBER_OF_PAGE_PER_BLOCK : STM32F10x_StdPeriph_Examples/FSMC/OneNAND/main.c
  • OneNAND_REG_AMOUNTOFBUFFERS : stm32100e_eval_fsmc_onenand.h
  • OneNAND_REG_BOOTBUFFERSIZE : stm32100e_eval_fsmc_onenand.h
  • OneNAND_REG_COMMAND : stm32100e_eval_fsmc_onenand.h
  • OneNAND_REG_CONTROLSTATUS : stm32100e_eval_fsmc_onenand.h
  • OneNAND_REG_DATABUFFERSIZE : stm32100e_eval_fsmc_onenand.h
  • OneNAND_REG_DEVICEID : stm32100e_eval_fsmc_onenand.h
  • OneNAND_REG_INTERRUPT : stm32100e_eval_fsmc_onenand.h
  • OneNAND_REG_MANUFACTERID : stm32100e_eval_fsmc_onenand.h
  • OneNAND_REG_STARTADDRESINT8_T : stm32100e_eval_fsmc_onenand.h
  • OneNAND_REG_STARTADDRESS1 : stm32100e_eval_fsmc_onenand.h
  • OneNAND_REG_STARTADDRESS3 : stm32100e_eval_fsmc_onenand.h
  • OneNAND_REG_STARTADDRESS4 : stm32100e_eval_fsmc_onenand.h
  • OneNAND_REG_STARTBLOCKADDRESS : stm32100e_eval_fsmc_onenand.h
  • OneNAND_REG_STARTBUFFER : stm32100e_eval_fsmc_onenand.h
  • OneNAND_REG_SYSTEMCONFIGURATION : stm32100e_eval_fsmc_onenand.h
  • OneNAND_REG_TECHNOLOGY : stm32100e_eval_fsmc_onenand.h
  • OneNAND_REG_WRITEPROTECTIONSTATUS : stm32100e_eval_fsmc_onenand.h
  • OneNAND_SAMSUNG_DEVICE_ID : STM32F10x_StdPeriph_Examples/FSMC/OneNAND/main.c
  • OneNAND_SAMSUNG_MANUFACTURER_ID : STM32F10x_StdPeriph_Examples/FSMC/OneNAND/main.c
  • OneNAND_WRITE : stm32100e_eval_fsmc_onenand.c
  • OneNAND_WRITE_BLOCK_NUMBER : STM32F10x_StdPeriph_Examples/FSMC/OneNAND/main.c
  • OneNAND_WRITE_PAGE_NUMBER : STM32F10x_StdPeriph_Examples/FSMC/OneNAND/main.c


STM32F10x Standard Peripherals Firmware Library: Globals

  • File List
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- a -

  • ABS : stm32100b_eval_lcd.c , stm32100e_eval_lcd.c , stm3210c_eval_lcd.c , stm3210e_eval_lcd.c , stm3210b_eval_lcd.c , stm32l152_eval_lcd.c
  • ACCESS_PERMISSION : STM32F10x_StdPeriph_Examples/CortexM3/MPU/main.c
  • ACR_HLFCYA_Mask : stm32f10x_flash.c
  • ACR_LATENCY_Mask : stm32f10x_flash.c
  • ACR_PRFTBE_Mask : stm32f10x_flash.c
  • ACR_PRFTBS_Mask : stm32f10x_flash.c
  • ADC1 : stm32f10x.h
  • ADC1_BASE : stm32f10x.h
  • ADC1_DR_Address : STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/main.c , STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/main.c , STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/main.c , STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/main.c , STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c , STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/main.c
  • ADC2 : stm32f10x.h
  • ADC2_BASE : stm32f10x.h
  • ADC3 : stm32f10x.h
  • ADC3_BASE : stm32f10x.h
  • ADC3_DR_Address : STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c
  • ADC_AnalogWatchdog_AllInjecEnable : stm32f10x_adc.h
  • ADC_AnalogWatchdog_AllRegAllInjecEnable : stm32f10x_adc.h
  • ADC_AnalogWatchdog_AllRegEnable : stm32f10x_adc.h
  • ADC_AnalogWatchdog_None : stm32f10x_adc.h
  • ADC_AnalogWatchdog_SingleInjecEnable : stm32f10x_adc.h
  • ADC_AnalogWatchdog_SingleRegEnable : stm32f10x_adc.h
  • ADC_AnalogWatchdog_SingleRegOrInjecEnable : stm32f10x_adc.h
  • ADC_Channel_0 : stm32f10x_adc.h
  • ADC_Channel_1 : stm32f10x_adc.h
  • ADC_Channel_10 : stm32f10x_adc.h
  • ADC_Channel_11 : stm32f10x_adc.h
  • ADC_Channel_12 : stm32f10x_adc.h
  • ADC_Channel_13 : stm32f10x_adc.h
  • ADC_Channel_14 : stm32f10x_adc.h
  • ADC_Channel_15 : stm32f10x_adc.h
  • ADC_Channel_16 : stm32f10x_adc.h
  • ADC_Channel_17 : stm32f10x_adc.h
  • ADC_Channel_2 : stm32f10x_adc.h
  • ADC_Channel_3 : stm32f10x_adc.h
  • ADC_Channel_4 : stm32f10x_adc.h
  • ADC_Channel_5 : stm32f10x_adc.h
  • ADC_Channel_6 : stm32f10x_adc.h
  • ADC_Channel_7 : stm32f10x_adc.h
  • ADC_Channel_8 : stm32f10x_adc.h
  • ADC_Channel_9 : stm32f10x_adc.h
  • ADC_Channel_TempSensor : stm32f10x_adc.h
  • ADC_Channel_Vrefint : stm32f10x_adc.h
  • ADC_CR1_AWDCH : stm32f10x.h
  • ADC_CR1_AWDCH_0 : stm32f10x.h
  • ADC_CR1_AWDCH_1 : stm32f10x.h
  • ADC_CR1_AWDCH_2 : stm32f10x.h
  • ADC_CR1_AWDCH_3 : stm32f10x.h
  • ADC_CR1_AWDCH_4 : stm32f10x.h
  • ADC_CR1_AWDEN : stm32f10x.h
  • ADC_CR1_AWDIE : stm32f10x.h
  • ADC_CR1_AWDSGL : stm32f10x.h
  • ADC_CR1_DISCEN : stm32f10x.h
  • ADC_CR1_DISCNUM : stm32f10x.h
  • ADC_CR1_DISCNUM_0 : stm32f10x.h
  • ADC_CR1_DISCNUM_1 : stm32f10x.h
  • ADC_CR1_DISCNUM_2 : stm32f10x.h
  • ADC_CR1_DUALMOD : stm32f10x.h
  • ADC_CR1_DUALMOD_0 : stm32f10x.h
  • ADC_CR1_DUALMOD_1 : stm32f10x.h
  • ADC_CR1_DUALMOD_2 : stm32f10x.h
  • ADC_CR1_DUALMOD_3 : stm32f10x.h
  • ADC_CR1_EOCIE : stm32f10x.h
  • ADC_CR1_JAUTO : stm32f10x.h
  • ADC_CR1_JAWDEN : stm32f10x.h
  • ADC_CR1_JDISCEN : stm32f10x.h
  • ADC_CR1_JEOCIE : stm32f10x.h
  • ADC_CR1_SCAN : stm32f10x.h
  • ADC_CR2_ADON : stm32f10x.h
  • ADC_CR2_ALIGN : stm32f10x.h
  • ADC_CR2_CAL : stm32f10x.h
  • ADC_CR2_CONT : stm32f10x.h
  • ADC_CR2_DMA : stm32f10x.h
  • ADC_CR2_EXTSEL : stm32f10x.h
  • ADC_CR2_EXTSEL_0 : stm32f10x.h
  • ADC_CR2_EXTSEL_1 : stm32f10x.h
  • ADC_CR2_EXTSEL_2 : stm32f10x.h
  • ADC_CR2_EXTTRIG : stm32f10x.h
  • ADC_CR2_JEXTSEL : stm32f10x.h
  • ADC_CR2_JEXTSEL_0 : stm32f10x.h
  • ADC_CR2_JEXTSEL_1 : stm32f10x.h
  • ADC_CR2_JEXTSEL_2 : stm32f10x.h
  • ADC_CR2_JEXTTRIG : stm32f10x.h
  • ADC_CR2_JSWSTART : stm32f10x.h
  • ADC_CR2_RSTCAL : stm32f10x.h
  • ADC_CR2_SWSTART : stm32f10x.h
  • ADC_CR2_TSVREFE : stm32f10x.h
  • ADC_DataAlign_Left : stm32f10x_adc.h
  • ADC_DataAlign_Right : stm32f10x_adc.h
  • ADC_DR_ADC2DATA : stm32f10x.h
  • ADC_DR_DATA : stm32f10x.h
  • ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO : stm32f10x_adc.h
  • ADC_ExternalTrigConv_None : stm32f10x_adc.h
  • ADC_ExternalTrigConv_T1_CC1 : stm32f10x_adc.h
  • ADC_ExternalTrigConv_T1_CC2 : stm32f10x_adc.h
  • ADC_ExternalTrigConv_T1_CC3 : stm32f10x_adc.h
  • ADC_ExternalTrigConv_T2_CC2 : stm32f10x_adc.h
  • ADC_ExternalTrigConv_T2_CC3 : stm32f10x_adc.h
  • ADC_ExternalTrigConv_T3_CC1 : stm32f10x_adc.h
  • ADC_ExternalTrigConv_T3_TRGO : stm32f10x_adc.h
  • ADC_ExternalTrigConv_T4_CC4 : stm32f10x_adc.h
  • ADC_ExternalTrigConv_T5_CC1 : stm32f10x_adc.h
  • ADC_ExternalTrigConv_T5_CC3 : stm32f10x_adc.h
  • ADC_ExternalTrigConv_T8_CC1 : stm32f10x_adc.h
  • ADC_ExternalTrigConv_T8_TRGO : stm32f10x_adc.h
  • ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 : stm32f10x_adc.h
  • ADC_ExternalTrigInjecConv_None : stm32f10x_adc.h
  • ADC_ExternalTrigInjecConv_T1_CC4 : stm32f10x_adc.h
  • ADC_ExternalTrigInjecConv_T1_TRGO : stm32f10x_adc.h
  • ADC_ExternalTrigInjecConv_T2_CC1 : stm32f10x_adc.h
  • ADC_ExternalTrigInjecConv_T2_TRGO : stm32f10x_adc.h
  • ADC_ExternalTrigInjecConv_T3_CC4 : stm32f10x_adc.h
  • ADC_ExternalTrigInjecConv_T4_CC3 : stm32f10x_adc.h
  • ADC_ExternalTrigInjecConv_T4_TRGO : stm32f10x_adc.h
  • ADC_ExternalTrigInjecConv_T5_CC4 : stm32f10x_adc.h
  • ADC_ExternalTrigInjecConv_T5_TRGO : stm32f10x_adc.h
  • ADC_ExternalTrigInjecConv_T8_CC2 : stm32f10x_adc.h
  • ADC_ExternalTrigInjecConv_T8_CC4 : stm32f10x_adc.h
  • ADC_FLAG_AWD : stm32f10x_adc.h
  • ADC_FLAG_EOC : stm32f10x_adc.h
  • ADC_FLAG_JEOC : stm32f10x_adc.h
  • ADC_FLAG_JSTRT : stm32f10x_adc.h
  • ADC_FLAG_STRT : stm32f10x_adc.h
  • ADC_HTR_HT : stm32f10x.h
  • ADC_InjectedChannel_1 : stm32f10x_adc.h
  • ADC_InjectedChannel_2 : stm32f10x_adc.h
  • ADC_InjectedChannel_3 : stm32f10x_adc.h
  • ADC_InjectedChannel_4 : stm32f10x_adc.h
  • ADC_IT_AWD : stm32f10x_adc.h
  • ADC_IT_EOC : stm32f10x_adc.h
  • ADC_IT_JEOC : stm32f10x_adc.h
  • ADC_JDR1_JDATA : stm32f10x.h
  • ADC_JDR2_JDATA : stm32f10x.h
  • ADC_JDR3_JDATA : stm32f10x.h
  • ADC_JDR4_JDATA : stm32f10x.h
  • ADC_JOFR1_JOFFSET1 : stm32f10x.h
  • ADC_JOFR2_JOFFSET2 : stm32f10x.h
  • ADC_JOFR3_JOFFSET3 : stm32f10x.h
  • ADC_JOFR4_JOFFSET4 : stm32f10x.h
  • ADC_JSQR_JL : stm32f10x.h
  • ADC_JSQR_JL_0 : stm32f10x.h
  • ADC_JSQR_JL_1 : stm32f10x.h
  • ADC_JSQR_JSQ1 : stm32f10x.h
  • ADC_JSQR_JSQ1_0 : stm32f10x.h
  • ADC_JSQR_JSQ1_1 : stm32f10x.h
  • ADC_JSQR_JSQ1_2 : stm32f10x.h
  • ADC_JSQR_JSQ1_3 : stm32f10x.h
  • ADC_JSQR_JSQ1_4 : stm32f10x.h
  • ADC_JSQR_JSQ2 : stm32f10x.h
  • ADC_JSQR_JSQ2_0 : stm32f10x.h
  • ADC_JSQR_JSQ2_1 : stm32f10x.h
  • ADC_JSQR_JSQ2_2 : stm32f10x.h
  • ADC_JSQR_JSQ2_3 : stm32f10x.h
  • ADC_JSQR_JSQ2_4 : stm32f10x.h
  • ADC_JSQR_JSQ3 : stm32f10x.h
  • ADC_JSQR_JSQ3_0 : stm32f10x.h
  • ADC_JSQR_JSQ3_1 : stm32f10x.h
  • ADC_JSQR_JSQ3_2 : stm32f10x.h
  • ADC_JSQR_JSQ3_3 : stm32f10x.h
  • ADC_JSQR_JSQ3_4 : stm32f10x.h
  • ADC_JSQR_JSQ4 : stm32f10x.h
  • ADC_JSQR_JSQ4_0 : stm32f10x.h
  • ADC_JSQR_JSQ4_1 : stm32f10x.h
  • ADC_JSQR_JSQ4_2 : stm32f10x.h
  • ADC_JSQR_JSQ4_3 : stm32f10x.h
  • ADC_JSQR_JSQ4_4 : stm32f10x.h
  • ADC_LTR_LT : stm32f10x.h
  • ADC_Mode_AlterTrig : stm32f10x_adc.h
  • ADC_Mode_FastInterl : stm32f10x_adc.h
  • ADC_Mode_Independent : stm32f10x_adc.h
  • ADC_Mode_InjecSimult : stm32f10x_adc.h
  • ADC_Mode_InjecSimult_FastInterl : stm32f10x_adc.h
  • ADC_Mode_InjecSimult_SlowInterl : stm32f10x_adc.h
  • ADC_Mode_RegInjecSimult : stm32f10x_adc.h
  • ADC_Mode_RegSimult : stm32f10x_adc.h
  • ADC_Mode_RegSimult_AlterTrig : stm32f10x_adc.h
  • ADC_Mode_SlowInterl : stm32f10x_adc.h
  • ADC_SampleTime_13Cycles5 : stm32f10x_adc.h
  • ADC_SampleTime_1Cycles5 : stm32f10x_adc.h
  • ADC_SampleTime_239Cycles5 : stm32f10x_adc.h
  • ADC_SampleTime_28Cycles5 : stm32f10x_adc.h
  • ADC_SampleTime_41Cycles5 : stm32f10x_adc.h
  • ADC_SampleTime_55Cycles5 : stm32f10x_adc.h
  • ADC_SampleTime_71Cycles5 : stm32f10x_adc.h
  • ADC_SampleTime_7Cycles5 : stm32f10x_adc.h
  • ADC_SMPR1_SMP10 : stm32f10x.h
  • ADC_SMPR1_SMP10_0 : stm32f10x.h
  • ADC_SMPR1_SMP10_1 : stm32f10x.h
  • ADC_SMPR1_SMP10_2 : stm32f10x.h
  • ADC_SMPR1_SMP11 : stm32f10x.h
  • ADC_SMPR1_SMP11_0 : stm32f10x.h
  • ADC_SMPR1_SMP11_1 : stm32f10x.h
  • ADC_SMPR1_SMP11_2 : stm32f10x.h
  • ADC_SMPR1_SMP12 : stm32f10x.h
  • ADC_SMPR1_SMP12_0 : stm32f10x.h
  • ADC_SMPR1_SMP12_1 : stm32f10x.h
  • ADC_SMPR1_SMP12_2 : stm32f10x.h
  • ADC_SMPR1_SMP13 : stm32f10x.h
  • ADC_SMPR1_SMP13_0 : stm32f10x.h
  • ADC_SMPR1_SMP13_1 : stm32f10x.h
  • ADC_SMPR1_SMP13_2 : stm32f10x.h
  • ADC_SMPR1_SMP14 : stm32f10x.h
  • ADC_SMPR1_SMP14_0 : stm32f10x.h
  • ADC_SMPR1_SMP14_1 : stm32f10x.h
  • ADC_SMPR1_SMP14_2 : stm32f10x.h
  • ADC_SMPR1_SMP15 : stm32f10x.h
  • ADC_SMPR1_SMP15_0 : stm32f10x.h
  • ADC_SMPR1_SMP15_1 : stm32f10x.h
  • ADC_SMPR1_SMP15_2 : stm32f10x.h
  • ADC_SMPR1_SMP16 : stm32f10x.h
  • ADC_SMPR1_SMP16_0 : stm32f10x.h
  • ADC_SMPR1_SMP16_1 : stm32f10x.h
  • ADC_SMPR1_SMP16_2 : stm32f10x.h
  • ADC_SMPR1_SMP17 : stm32f10x.h
  • ADC_SMPR1_SMP17_0 : stm32f10x.h
  • ADC_SMPR1_SMP17_1 : stm32f10x.h
  • ADC_SMPR1_SMP17_2 : stm32f10x.h
  • ADC_SMPR2_SMP0 : stm32f10x.h
  • ADC_SMPR2_SMP0_0 : stm32f10x.h
  • ADC_SMPR2_SMP0_1 : stm32f10x.h
  • ADC_SMPR2_SMP0_2 : stm32f10x.h
  • ADC_SMPR2_SMP1 : stm32f10x.h
  • ADC_SMPR2_SMP1_0 : stm32f10x.h
  • ADC_SMPR2_SMP1_1 : stm32f10x.h
  • ADC_SMPR2_SMP1_2 : stm32f10x.h
  • ADC_SMPR2_SMP2 : stm32f10x.h
  • ADC_SMPR2_SMP2_0 : stm32f10x.h
  • ADC_SMPR2_SMP2_1 : stm32f10x.h
  • ADC_SMPR2_SMP2_2 : stm32f10x.h
  • ADC_SMPR2_SMP3 : stm32f10x.h
  • ADC_SMPR2_SMP3_0 : stm32f10x.h
  • ADC_SMPR2_SMP3_1 : stm32f10x.h
  • ADC_SMPR2_SMP3_2 : stm32f10x.h
  • ADC_SMPR2_SMP4 : stm32f10x.h
  • ADC_SMPR2_SMP4_0 : stm32f10x.h
  • ADC_SMPR2_SMP4_1 : stm32f10x.h
  • ADC_SMPR2_SMP4_2 : stm32f10x.h
  • ADC_SMPR2_SMP5 : stm32f10x.h
  • ADC_SMPR2_SMP5_0 : stm32f10x.h
  • ADC_SMPR2_SMP5_1 : stm32f10x.h
  • ADC_SMPR2_SMP5_2 : stm32f10x.h
  • ADC_SMPR2_SMP6 : stm32f10x.h
  • ADC_SMPR2_SMP6_0 : stm32f10x.h
  • ADC_SMPR2_SMP6_1 : stm32f10x.h
  • ADC_SMPR2_SMP6_2 : stm32f10x.h
  • ADC_SMPR2_SMP7 : stm32f10x.h
  • ADC_SMPR2_SMP7_0 : stm32f10x.h
  • ADC_SMPR2_SMP7_1 : stm32f10x.h
  • ADC_SMPR2_SMP7_2 : stm32f10x.h
  • ADC_SMPR2_SMP8 : stm32f10x.h
  • ADC_SMPR2_SMP8_0 : stm32f10x.h
  • ADC_SMPR2_SMP8_1 : stm32f10x.h
  • ADC_SMPR2_SMP8_2 : stm32f10x.h
  • ADC_SMPR2_SMP9 : stm32f10x.h
  • ADC_SMPR2_SMP9_0 : stm32f10x.h
  • ADC_SMPR2_SMP9_1 : stm32f10x.h
  • ADC_SMPR2_SMP9_2 : stm32f10x.h
  • ADC_SQR1_L : stm32f10x.h
  • ADC_SQR1_L_0 : stm32f10x.h
  • ADC_SQR1_L_1 : stm32f10x.h
  • ADC_SQR1_L_2 : stm32f10x.h
  • ADC_SQR1_L_3 : stm32f10x.h
  • ADC_SQR1_SQ13 : stm32f10x.h
  • ADC_SQR1_SQ13_0 : stm32f10x.h
  • ADC_SQR1_SQ13_1 : stm32f10x.h
  • ADC_SQR1_SQ13_2 : stm32f10x.h
  • ADC_SQR1_SQ13_3 : stm32f10x.h
  • ADC_SQR1_SQ13_4 : stm32f10x.h
  • ADC_SQR1_SQ14 : stm32f10x.h
  • ADC_SQR1_SQ14_0 : stm32f10x.h
  • ADC_SQR1_SQ14_1 : stm32f10x.h
  • ADC_SQR1_SQ14_2 : stm32f10x.h
  • ADC_SQR1_SQ14_3 : stm32f10x.h
  • ADC_SQR1_SQ14_4 : stm32f10x.h
  • ADC_SQR1_SQ15 : stm32f10x.h
  • ADC_SQR1_SQ15_0 : stm32f10x.h
  • ADC_SQR1_SQ15_1 : stm32f10x.h
  • ADC_SQR1_SQ15_2 : stm32f10x.h
  • ADC_SQR1_SQ15_3 : stm32f10x.h
  • ADC_SQR1_SQ15_4 : stm32f10x.h
  • ADC_SQR1_SQ16 : stm32f10x.h
  • ADC_SQR1_SQ16_0 : stm32f10x.h
  • ADC_SQR1_SQ16_1 : stm32f10x.h
  • ADC_SQR1_SQ16_2 : stm32f10x.h
  • ADC_SQR1_SQ16_3 : stm32f10x.h
  • ADC_SQR1_SQ16_4 : stm32f10x.h
  • ADC_SQR2_SQ10 : stm32f10x.h
  • ADC_SQR2_SQ10_0 : stm32f10x.h
  • ADC_SQR2_SQ10_1 : stm32f10x.h
  • ADC_SQR2_SQ10_2 : stm32f10x.h
  • ADC_SQR2_SQ10_3 : stm32f10x.h
  • ADC_SQR2_SQ10_4 : stm32f10x.h
  • ADC_SQR2_SQ11 : stm32f10x.h
  • ADC_SQR2_SQ11_0 : stm32f10x.h
  • ADC_SQR2_SQ11_1 : stm32f10x.h
  • ADC_SQR2_SQ11_2 : stm32f10x.h
  • ADC_SQR2_SQ11_3 : stm32f10x.h
  • ADC_SQR2_SQ11_4 : stm32f10x.h
  • ADC_SQR2_SQ12 : stm32f10x.h
  • ADC_SQR2_SQ12_0 : stm32f10x.h
  • ADC_SQR2_SQ12_1 : stm32f10x.h
  • ADC_SQR2_SQ12_2 : stm32f10x.h
  • ADC_SQR2_SQ12_3 : stm32f10x.h
  • ADC_SQR2_SQ12_4 : stm32f10x.h
  • ADC_SQR2_SQ7 : stm32f10x.h
  • ADC_SQR2_SQ7_0 : stm32f10x.h
  • ADC_SQR2_SQ7_1 : stm32f10x.h
  • ADC_SQR2_SQ7_2 : stm32f10x.h
  • ADC_SQR2_SQ7_3 : stm32f10x.h
  • ADC_SQR2_SQ7_4 : stm32f10x.h
  • ADC_SQR2_SQ8 : stm32f10x.h
  • ADC_SQR2_SQ8_0 : stm32f10x.h
  • ADC_SQR2_SQ8_1 : stm32f10x.h
  • ADC_SQR2_SQ8_2 : stm32f10x.h
  • ADC_SQR2_SQ8_3 : stm32f10x.h
  • ADC_SQR2_SQ8_4 : stm32f10x.h
  • ADC_SQR2_SQ9 : stm32f10x.h
  • ADC_SQR2_SQ9_0 : stm32f10x.h
  • ADC_SQR2_SQ9_1 : stm32f10x.h
  • ADC_SQR2_SQ9_2 : stm32f10x.h
  • ADC_SQR2_SQ9_3 : stm32f10x.h
  • ADC_SQR2_SQ9_4 : stm32f10x.h
  • ADC_SQR3_SQ1 : stm32f10x.h
  • ADC_SQR3_SQ1_0 : stm32f10x.h
  • ADC_SQR3_SQ1_1 : stm32f10x.h
  • ADC_SQR3_SQ1_2 : stm32f10x.h
  • ADC_SQR3_SQ1_3 : stm32f10x.h
  • ADC_SQR3_SQ1_4 : stm32f10x.h
  • ADC_SQR3_SQ2 : stm32f10x.h
  • ADC_SQR3_SQ2_0 : stm32f10x.h
  • ADC_SQR3_SQ2_1 : stm32f10x.h
  • ADC_SQR3_SQ2_2 : stm32f10x.h
  • ADC_SQR3_SQ2_3 : stm32f10x.h
  • ADC_SQR3_SQ2_4 : stm32f10x.h
  • ADC_SQR3_SQ3 : stm32f10x.h
  • ADC_SQR3_SQ3_0 : stm32f10x.h
  • ADC_SQR3_SQ3_1 : stm32f10x.h
  • ADC_SQR3_SQ3_2 : stm32f10x.h
  • ADC_SQR3_SQ3_3 : stm32f10x.h
  • ADC_SQR3_SQ3_4 : stm32f10x.h
  • ADC_SQR3_SQ4 : stm32f10x.h
  • ADC_SQR3_SQ4_0 : stm32f10x.h
  • ADC_SQR3_SQ4_1 : stm32f10x.h
  • ADC_SQR3_SQ4_2 : stm32f10x.h
  • ADC_SQR3_SQ4_3 : stm32f10x.h
  • ADC_SQR3_SQ4_4 : stm32f10x.h
  • ADC_SQR3_SQ5 : stm32f10x.h
  • ADC_SQR3_SQ5_0 : stm32f10x.h
  • ADC_SQR3_SQ5_1 : stm32f10x.h
  • ADC_SQR3_SQ5_2 : stm32f10x.h
  • ADC_SQR3_SQ5_3 : stm32f10x.h
  • ADC_SQR3_SQ5_4 : stm32f10x.h
  • ADC_SQR3_SQ6 : stm32f10x.h
  • ADC_SQR3_SQ6_0 : stm32f10x.h
  • ADC_SQR3_SQ6_1 : stm32f10x.h
  • ADC_SQR3_SQ6_2 : stm32f10x.h
  • ADC_SQR3_SQ6_3 : stm32f10x.h
  • ADC_SQR3_SQ6_4 : stm32f10x.h
  • ADC_SR_AWD : stm32f10x.h
  • ADC_SR_EOC : stm32f10x.h
  • ADC_SR_JEOC : stm32f10x.h
  • ADC_SR_JSTRT : stm32f10x.h
  • ADC_SR_STRT : stm32f10x.h
  • ADDR_1st_CYCLE : stm3210e_eval_fsmc_nand.h
  • ADDR_2nd_CYCLE : stm3210e_eval_fsmc_nand.h
  • ADDR_3rd_CYCLE : stm3210e_eval_fsmc_nand.h
  • ADDR_4th_CYCLE : stm3210e_eval_fsmc_nand.h
  • ADDR_AREA : stm3210e_eval_fsmc_nand.h
  • ADDR_SHIFT : stm3210e_eval_fsmc_nor.c
  • AFIO : stm32f10x.h
  • AFIO_BASE : stm32f10x.h
  • AFIO_EVCR_EVOE : stm32f10x.h
  • AFIO_EVCR_PIN : stm32f10x.h
  • AFIO_EVCR_PIN_0 : stm32f10x.h
  • AFIO_EVCR_PIN_1 : stm32f10x.h
  • AFIO_EVCR_PIN_2 : stm32f10x.h
  • AFIO_EVCR_PIN_3 : stm32f10x.h
  • AFIO_EVCR_PIN_PX0 : stm32f10x.h
  • AFIO_EVCR_PIN_PX1 : stm32f10x.h
  • AFIO_EVCR_PIN_PX10 : stm32f10x.h
  • AFIO_EVCR_PIN_PX11 : stm32f10x.h
  • AFIO_EVCR_PIN_PX12 : stm32f10x.h
  • AFIO_EVCR_PIN_PX13 : stm32f10x.h
  • AFIO_EVCR_PIN_PX14 : stm32f10x.h
  • AFIO_EVCR_PIN_PX15 : stm32f10x.h
  • AFIO_EVCR_PIN_PX2 : stm32f10x.h
  • AFIO_EVCR_PIN_PX3 : stm32f10x.h
  • AFIO_EVCR_PIN_PX4 : stm32f10x.h
  • AFIO_EVCR_PIN_PX5 : stm32f10x.h
  • AFIO_EVCR_PIN_PX6 : stm32f10x.h
  • AFIO_EVCR_PIN_PX7 : stm32f10x.h
  • AFIO_EVCR_PIN_PX8 : stm32f10x.h
  • AFIO_EVCR_PIN_PX9 : stm32f10x.h
  • AFIO_EVCR_PORT : stm32f10x.h
  • AFIO_EVCR_PORT_0 : stm32f10x.h
  • AFIO_EVCR_PORT_1 : stm32f10x.h
  • AFIO_EVCR_PORT_2 : stm32f10x.h
  • AFIO_EVCR_PORT_PA : stm32f10x.h
  • AFIO_EVCR_PORT_PB : stm32f10x.h
  • AFIO_EVCR_PORT_PC : stm32f10x.h
  • AFIO_EVCR_PORT_PD : stm32f10x.h
  • AFIO_EVCR_PORT_PE : stm32f10x.h
  • AFIO_EXTICR1_EXTI0 : stm32f10x.h
  • AFIO_EXTICR1_EXTI0_PA : stm32f10x.h
  • AFIO_EXTICR1_EXTI0_PB : stm32f10x.h
  • AFIO_EXTICR1_EXTI0_PC : stm32f10x.h
  • AFIO_EXTICR1_EXTI0_PD : stm32f10x.h
  • AFIO_EXTICR1_EXTI0_PE : stm32f10x.h
  • AFIO_EXTICR1_EXTI0_PF : stm32f10x.h
  • AFIO_EXTICR1_EXTI0_PG : stm32f10x.h
  • AFIO_EXTICR1_EXTI1 : stm32f10x.h
  • AFIO_EXTICR1_EXTI1_PA : stm32f10x.h
  • AFIO_EXTICR1_EXTI1_PB : stm32f10x.h
  • AFIO_EXTICR1_EXTI1_PC : stm32f10x.h
  • AFIO_EXTICR1_EXTI1_PD : stm32f10x.h
  • AFIO_EXTICR1_EXTI1_PE : stm32f10x.h
  • AFIO_EXTICR1_EXTI1_PF : stm32f10x.h
  • AFIO_EXTICR1_EXTI1_PG : stm32f10x.h
  • AFIO_EXTICR1_EXTI2 : stm32f10x.h
  • AFIO_EXTICR1_EXTI2_PA : stm32f10x.h
  • AFIO_EXTICR1_EXTI2_PB : stm32f10x.h
  • AFIO_EXTICR1_EXTI2_PC : stm32f10x.h
  • AFIO_EXTICR1_EXTI2_PD : stm32f10x.h
  • AFIO_EXTICR1_EXTI2_PE : stm32f10x.h
  • AFIO_EXTICR1_EXTI2_PF : stm32f10x.h
  • AFIO_EXTICR1_EXTI2_PG : stm32f10x.h
  • AFIO_EXTICR1_EXTI3 : stm32f10x.h
  • AFIO_EXTICR1_EXTI3_PA : stm32f10x.h
  • AFIO_EXTICR1_EXTI3_PB : stm32f10x.h
  • AFIO_EXTICR1_EXTI3_PC : stm32f10x.h
  • AFIO_EXTICR1_EXTI3_PD : stm32f10x.h
  • AFIO_EXTICR1_EXTI3_PE : stm32f10x.h
  • AFIO_EXTICR1_EXTI3_PF : stm32f10x.h
  • AFIO_EXTICR1_EXTI3_PG : stm32f10x.h
  • AFIO_EXTICR2_EXTI4 : stm32f10x.h
  • AFIO_EXTICR2_EXTI4_PA : stm32f10x.h
  • AFIO_EXTICR2_EXTI4_PB : stm32f10x.h
  • AFIO_EXTICR2_EXTI4_PC : stm32f10x.h
  • AFIO_EXTICR2_EXTI4_PD : stm32f10x.h
  • AFIO_EXTICR2_EXTI4_PE : stm32f10x.h
  • AFIO_EXTICR2_EXTI4_PF : stm32f10x.h
  • AFIO_EXTICR2_EXTI4_PG : stm32f10x.h
  • AFIO_EXTICR2_EXTI5 : stm32f10x.h
  • AFIO_EXTICR2_EXTI5_PA : stm32f10x.h
  • AFIO_EXTICR2_EXTI5_PB : stm32f10x.h
  • AFIO_EXTICR2_EXTI5_PC : stm32f10x.h
  • AFIO_EXTICR2_EXTI5_PD : stm32f10x.h
  • AFIO_EXTICR2_EXTI5_PE : stm32f10x.h
  • AFIO_EXTICR2_EXTI5_PF : stm32f10x.h
  • AFIO_EXTICR2_EXTI5_PG : stm32f10x.h
  • AFIO_EXTICR2_EXTI6 : stm32f10x.h
  • AFIO_EXTICR2_EXTI6_PA : stm32f10x.h
  • AFIO_EXTICR2_EXTI6_PB : stm32f10x.h
  • AFIO_EXTICR2_EXTI6_PC : stm32f10x.h
  • AFIO_EXTICR2_EXTI6_PD : stm32f10x.h
  • AFIO_EXTICR2_EXTI6_PE : stm32f10x.h
  • AFIO_EXTICR2_EXTI6_PF : stm32f10x.h
  • AFIO_EXTICR2_EXTI6_PG : stm32f10x.h
  • AFIO_EXTICR2_EXTI7 : stm32f10x.h
  • AFIO_EXTICR2_EXTI7_PA : stm32f10x.h
  • AFIO_EXTICR2_EXTI7_PB : stm32f10x.h
  • AFIO_EXTICR2_EXTI7_PC : stm32f10x.h
  • AFIO_EXTICR2_EXTI7_PD : stm32f10x.h
  • AFIO_EXTICR2_EXTI7_PE : stm32f10x.h
  • AFIO_EXTICR2_EXTI7_PF : stm32f10x.h
  • AFIO_EXTICR2_EXTI7_PG : stm32f10x.h
  • AFIO_EXTICR3_EXTI10 : stm32f10x.h
  • AFIO_EXTICR3_EXTI10_PA : stm32f10x.h
  • AFIO_EXTICR3_EXTI10_PB : stm32f10x.h
  • AFIO_EXTICR3_EXTI10_PC : stm32f10x.h
  • AFIO_EXTICR3_EXTI10_PD : stm32f10x.h
  • AFIO_EXTICR3_EXTI10_PE : stm32f10x.h
  • AFIO_EXTICR3_EXTI10_PF : stm32f10x.h
  • AFIO_EXTICR3_EXTI10_PG : stm32f10x.h
  • AFIO_EXTICR3_EXTI11 : stm32f10x.h
  • AFIO_EXTICR3_EXTI11_PA : stm32f10x.h
  • AFIO_EXTICR3_EXTI11_PB : stm32f10x.h
  • AFIO_EXTICR3_EXTI11_PC : stm32f10x.h
  • AFIO_EXTICR3_EXTI11_PD : stm32f10x.h
  • AFIO_EXTICR3_EXTI11_PE : stm32f10x.h
  • AFIO_EXTICR3_EXTI11_PF : stm32f10x.h
  • AFIO_EXTICR3_EXTI11_PG : stm32f10x.h
  • AFIO_EXTICR3_EXTI8 : stm32f10x.h
  • AFIO_EXTICR3_EXTI8_PA : stm32f10x.h
  • AFIO_EXTICR3_EXTI8_PB : stm32f10x.h
  • AFIO_EXTICR3_EXTI8_PC : stm32f10x.h
  • AFIO_EXTICR3_EXTI8_PD : stm32f10x.h
  • AFIO_EXTICR3_EXTI8_PE : stm32f10x.h
  • AFIO_EXTICR3_EXTI8_PF : stm32f10x.h
  • AFIO_EXTICR3_EXTI8_PG : stm32f10x.h
  • AFIO_EXTICR3_EXTI9 : stm32f10x.h
  • AFIO_EXTICR3_EXTI9_PA : stm32f10x.h
  • AFIO_EXTICR3_EXTI9_PB : stm32f10x.h
  • AFIO_EXTICR3_EXTI9_PC : stm32f10x.h
  • AFIO_EXTICR3_EXTI9_PD : stm32f10x.h
  • AFIO_EXTICR3_EXTI9_PE : stm32f10x.h
  • AFIO_EXTICR3_EXTI9_PF : stm32f10x.h
  • AFIO_EXTICR3_EXTI9_PG : stm32f10x.h
  • AFIO_EXTICR4_EXTI12 : stm32f10x.h
  • AFIO_EXTICR4_EXTI12_PA : stm32f10x.h
  • AFIO_EXTICR4_EXTI12_PB : stm32f10x.h
  • AFIO_EXTICR4_EXTI12_PC : stm32f10x.h
  • AFIO_EXTICR4_EXTI12_PD : stm32f10x.h
  • AFIO_EXTICR4_EXTI12_PE : stm32f10x.h
  • AFIO_EXTICR4_EXTI12_PF : stm32f10x.h
  • AFIO_EXTICR4_EXTI12_PG : stm32f10x.h
  • AFIO_EXTICR4_EXTI13 : stm32f10x.h
  • AFIO_EXTICR4_EXTI13_PA : stm32f10x.h
  • AFIO_EXTICR4_EXTI13_PB : stm32f10x.h
  • AFIO_EXTICR4_EXTI13_PC : stm32f10x.h
  • AFIO_EXTICR4_EXTI13_PD : stm32f10x.h
  • AFIO_EXTICR4_EXTI13_PE : stm32f10x.h
  • AFIO_EXTICR4_EXTI13_PF : stm32f10x.h
  • AFIO_EXTICR4_EXTI13_PG : stm32f10x.h
  • AFIO_EXTICR4_EXTI14 : stm32f10x.h
  • AFIO_EXTICR4_EXTI14_PA : stm32f10x.h
  • AFIO_EXTICR4_EXTI14_PB : stm32f10x.h
  • AFIO_EXTICR4_EXTI14_PC : stm32f10x.h
  • AFIO_EXTICR4_EXTI14_PD : stm32f10x.h
  • AFIO_EXTICR4_EXTI14_PE : stm32f10x.h
  • AFIO_EXTICR4_EXTI14_PF : stm32f10x.h
  • AFIO_EXTICR4_EXTI14_PG : stm32f10x.h
  • AFIO_EXTICR4_EXTI15 : stm32f10x.h
  • AFIO_EXTICR4_EXTI15_PA : stm32f10x.h
  • AFIO_EXTICR4_EXTI15_PB : stm32f10x.h
  • AFIO_EXTICR4_EXTI15_PC : stm32f10x.h
  • AFIO_EXTICR4_EXTI15_PD : stm32f10x.h
  • AFIO_EXTICR4_EXTI15_PE : stm32f10x.h
  • AFIO_EXTICR4_EXTI15_PF : stm32f10x.h
  • AFIO_EXTICR4_EXTI15_PG : stm32f10x.h
  • AFIO_MAPR_ADC1_ETRGINJ_REMAP : stm32f10x.h
  • AFIO_MAPR_ADC1_ETRGREG_REMAP : stm32f10x.h
  • AFIO_MAPR_ADC2_ETRGINJ_REMAP : stm32f10x.h
  • AFIO_MAPR_ADC2_ETRGREG_REMAP : stm32f10x.h
  • AFIO_MAPR_CAN_REMAP : stm32f10x.h
  • AFIO_MAPR_CAN_REMAP_0 : stm32f10x.h
  • AFIO_MAPR_CAN_REMAP_1 : stm32f10x.h
  • AFIO_MAPR_CAN_REMAP_REMAP1 : stm32f10x.h
  • AFIO_MAPR_CAN_REMAP_REMAP2 : stm32f10x.h
  • AFIO_MAPR_CAN_REMAP_REMAP3 : stm32f10x.h
  • AFIO_MAPR_I2C1_REMAP : stm32f10x.h
  • AFIO_MAPR_PD01_REMAP : stm32f10x.h
  • AFIO_MAPR_SPI1_REMAP : stm32f10x.h
  • AFIO_MAPR_SWJ_CFG : stm32f10x.h
  • AFIO_MAPR_SWJ_CFG_0 : stm32f10x.h
  • AFIO_MAPR_SWJ_CFG_1 : stm32f10x.h
  • AFIO_MAPR_SWJ_CFG_2 : stm32f10x.h
  • AFIO_MAPR_SWJ_CFG_DISABLE : stm32f10x.h
  • AFIO_MAPR_SWJ_CFG_JTAGDISABLE : stm32f10x.h
  • AFIO_MAPR_SWJ_CFG_NOJNTRST : stm32f10x.h
  • AFIO_MAPR_SWJ_CFG_RESET : stm32f10x.h
  • AFIO_MAPR_TIM1_REMAP : stm32f10x.h
  • AFIO_MAPR_TIM1_REMAP_0 : stm32f10x.h
  • AFIO_MAPR_TIM1_REMAP_1 : stm32f10x.h
  • AFIO_MAPR_TIM1_REMAP_FULLREMAP : stm32f10x.h
  • AFIO_MAPR_TIM1_REMAP_NOREMAP : stm32f10x.h
  • AFIO_MAPR_TIM1_REMAP_PARTIALREMAP : stm32f10x.h
  • AFIO_MAPR_TIM2_REMAP : stm32f10x.h
  • AFIO_MAPR_TIM2_REMAP_0 : stm32f10x.h
  • AFIO_MAPR_TIM2_REMAP_1 : stm32f10x.h
  • AFIO_MAPR_TIM2_REMAP_FULLREMAP : stm32f10x.h
  • AFIO_MAPR_TIM2_REMAP_NOREMAP : stm32f10x.h
  • AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 : stm32f10x.h
  • AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 : stm32f10x.h
  • AFIO_MAPR_TIM3_REMAP : stm32f10x.h
  • AFIO_MAPR_TIM3_REMAP_0 : stm32f10x.h
  • AFIO_MAPR_TIM3_REMAP_1 : stm32f10x.h
  • AFIO_MAPR_TIM3_REMAP_FULLREMAP : stm32f10x.h
  • AFIO_MAPR_TIM3_REMAP_NOREMAP : stm32f10x.h
  • AFIO_MAPR_TIM3_REMAP_PARTIALREMAP : stm32f10x.h
  • AFIO_MAPR_TIM4_REMAP : stm32f10x.h
  • AFIO_MAPR_TIM5CH4_IREMAP : stm32f10x.h
  • AFIO_MAPR_USART1_REMAP : stm32f10x.h
  • AFIO_MAPR_USART2_REMAP : stm32f10x.h
  • AFIO_MAPR_USART3_REMAP : stm32f10x.h
  • AFIO_MAPR_USART3_REMAP_0 : stm32f10x.h
  • AFIO_MAPR_USART3_REMAP_1 : stm32f10x.h
  • AFIO_MAPR_USART3_REMAP_FULLREMAP : stm32f10x.h
  • AFIO_MAPR_USART3_REMAP_NOREMAP : stm32f10x.h
  • AFIO_MAPR_USART3_REMAP_PARTIALREMAP : stm32f10x.h
  • AFIO_OFFSET : stm32f10x_gpio.c
  • AHBPERIPH_BASE : stm32f10x.h
  • AIRCR_VECTKEY_MASK : misc.c
  • ALL_IT : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • APB1PERIPH_BASE : stm32f10x.h
  • APB2PERIPH_BASE : stm32f10x.h
  • ApplicationAddress : STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/main.c
  • ARRAY_ADDRESS_START : accesspermission.c
  • ARRAY_REGION_NUMBER : accesspermission.c
  • ARRAY_SIZE : accesspermission.c
  • ASSEMBLE_RGB : stm32100e_eval_lcd.h , stm3210c_eval_lcd.h , stm32100b_eval_lcd.h , stm32l152_eval_lcd.h , stm3210b_eval_lcd.h , stm3210e_eval_lcd.h
  • assert_param : STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/DMA/FSMC/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/USART/DMA_Polling/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/USART/MultiProcessor/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/SysTick/TimeBase/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/CortexM3/BitBand/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/USART/Polling/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/CortexM3/MPU/stm32f10x_conf.h , STM32F10x_StdPeriph_Template/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/TIM/6Steps/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/TIM/DMABurst/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/SDIO/uSDCard/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/USART/Printf/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/FSMC/NOR/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/TIM/DMA/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/PWR/PVD/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/FSMC/OneNAND/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/TIM/OCInactive/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/I2C/IOExpander/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/RTC/Calendar/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/BKP/Backup_Data/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/SPI/DMA/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/SPI/CRC/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/USART/HalfDuplex/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/FLASH/Program/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/TIM/OCActive/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/TIM/OnePulse/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/I2C/EEPROM/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/TIM/PWM_Input/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/PWR/STANDBY/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/USART/Synchronous/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/BKP/Tamper/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/FSMC/NAND/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/TIM/PWM_Output/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/GPIO/IOToggle/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/FSMC/SRAM/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/stm32f10x_conf.h
  • ATACMD_BitNumber : stm32f10x_sdio.c
  • AUDIO_RESET_PIN : stm3210c_eval_ioe.h


STM32F10x Standard Peripherals Firmware Library: Globals

  • File List
  • Globals
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- b -

  • Bank1_NOR2_ADDR : stm3210e_eval_fsmc_nor.c
  • BANK1_ONENAND1_ADDR : stm32100e_eval_fsmc_onenand.c
  • Bank1_SRAM3_ADDR : stm32100e_eval_fsmc_sram.c , stm3210e_eval_fsmc_sram.c , STM32F10x_StdPeriph_Examples/DMA/FSMC/main.c
  • BANK1_START_ADDRESS : STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/main.c
  • BANK1_WRITE_END_ADDR : STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/main.c , STM32F10x_StdPeriph_Examples/FLASH/Program/main.c
  • BANK1_WRITE_START_ADDR : STM32F10x_StdPeriph_Examples/FLASH/Program/main.c , STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/main.c
  • Bank2_NAND_ADDR : stm3210e_eval_fsmc_nand.c
  • BANK2_START_ADDRESS : STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/main.c
  • Bank_NAND_ADDR : stm3210e_eval_fsmc_nand.c
  • BCR_FACCEN_Set : stm32f10x_fsmc.c
  • BCR_MBKEN_Reset : stm32f10x_fsmc.c
  • BCR_MBKEN_Set : stm32f10x_fsmc.c
  • BDCR_ADDRESS : stm32f10x_rcc.c
  • BDCR_BDRST_BB : stm32f10x_rcc.c
  • BDCR_OFFSET : stm32f10x_rcc.c
  • BDCR_RTCEN_BB : stm32f10x_rcc.c
  • BDRST_BitNumber : stm32f10x_rcc.c
  • BIT_Mask : stm32f10x_wwdg.c
  • BKP : stm32f10x.h
  • BKP_BASE : stm32f10x.h
  • BKP_CR_TPAL : stm32f10x.h
  • BKP_CR_TPE : stm32f10x.h
  • BKP_CSR_CTE : stm32f10x.h
  • BKP_CSR_CTI : stm32f10x.h
  • BKP_CSR_TEF : stm32f10x.h
  • BKP_CSR_TIF : stm32f10x.h
  • BKP_CSR_TPIE : stm32f10x.h
  • BKP_DR1 : stm32f10x_bkp.h
  • BKP_DR10 : stm32f10x_bkp.h
  • BKP_DR10_D : stm32f10x.h
  • BKP_DR11 : stm32f10x_bkp.h
  • BKP_DR11_D : stm32f10x.h
  • BKP_DR12 : stm32f10x_bkp.h
  • BKP_DR12_D : stm32f10x.h
  • BKP_DR13 : stm32f10x_bkp.h
  • BKP_DR13_D : stm32f10x.h
  • BKP_DR14 : stm32f10x_bkp.h
  • BKP_DR14_D : stm32f10x.h
  • BKP_DR15 : stm32f10x_bkp.h
  • BKP_DR15_D : stm32f10x.h
  • BKP_DR16 : stm32f10x_bkp.h
  • BKP_DR16_D : stm32f10x.h
  • BKP_DR17 : stm32f10x_bkp.h
  • BKP_DR17_D : stm32f10x.h
  • BKP_DR18 : stm32f10x_bkp.h
  • BKP_DR18_D : stm32f10x.h
  • BKP_DR19 : stm32f10x_bkp.h
  • BKP_DR19_D : stm32f10x.h
  • BKP_DR1_D : stm32f10x.h
  • BKP_DR2 : stm32f10x_bkp.h
  • BKP_DR20 : stm32f10x_bkp.h
  • BKP_DR20_D : stm32f10x.h
  • BKP_DR21 : stm32f10x_bkp.h
  • BKP_DR21_D : stm32f10x.h
  • BKP_DR22 : stm32f10x_bkp.h
  • BKP_DR22_D : stm32f10x.h
  • BKP_DR23 : stm32f10x_bkp.h
  • BKP_DR23_D : stm32f10x.h
  • BKP_DR24 : stm32f10x_bkp.h
  • BKP_DR24_D : stm32f10x.h
  • BKP_DR25 : stm32f10x_bkp.h
  • BKP_DR25_D : stm32f10x.h
  • BKP_DR26 : stm32f10x_bkp.h
  • BKP_DR26_D : stm32f10x.h
  • BKP_DR27 : stm32f10x_bkp.h
  • BKP_DR27_D : stm32f10x.h
  • BKP_DR28 : stm32f10x_bkp.h
  • BKP_DR28_D : stm32f10x.h
  • BKP_DR29 : stm32f10x_bkp.h
  • BKP_DR29_D : stm32f10x.h
  • BKP_DR2_D : stm32f10x.h
  • BKP_DR3 : stm32f10x_bkp.h
  • BKP_DR30 : stm32f10x_bkp.h
  • BKP_DR30_D : stm32f10x.h
  • BKP_DR31 : stm32f10x_bkp.h
  • BKP_DR31_D : stm32f10x.h
  • BKP_DR32 : stm32f10x_bkp.h
  • BKP_DR32_D : stm32f10x.h
  • BKP_DR33 : stm32f10x_bkp.h
  • BKP_DR33_D : stm32f10x.h
  • BKP_DR34 : stm32f10x_bkp.h
  • BKP_DR34_D : stm32f10x.h
  • BKP_DR35 : stm32f10x_bkp.h
  • BKP_DR35_D : stm32f10x.h
  • BKP_DR36 : stm32f10x_bkp.h
  • BKP_DR36_D : stm32f10x.h
  • BKP_DR37 : stm32f10x_bkp.h
  • BKP_DR37_D : stm32f10x.h
  • BKP_DR38 : stm32f10x_bkp.h
  • BKP_DR38_D : stm32f10x.h
  • BKP_DR39 : stm32f10x_bkp.h
  • BKP_DR39_D : stm32f10x.h
  • BKP_DR3_D : stm32f10x.h
  • BKP_DR4 : stm32f10x_bkp.h
  • BKP_DR40 : stm32f10x_bkp.h
  • BKP_DR40_D : stm32f10x.h
  • BKP_DR41 : stm32f10x_bkp.h
  • BKP_DR41_D : stm32f10x.h
  • BKP_DR42 : stm32f10x_bkp.h
  • BKP_DR42_D : stm32f10x.h
  • BKP_DR4_D : stm32f10x.h
  • BKP_DR5 : stm32f10x_bkp.h
  • BKP_DR5_D : stm32f10x.h
  • BKP_DR6 : stm32f10x_bkp.h
  • BKP_DR6_D : stm32f10x.h
  • BKP_DR7 : stm32f10x_bkp.h
  • BKP_DR7_D : stm32f10x.h
  • BKP_DR8 : stm32f10x_bkp.h
  • BKP_DR8_D : stm32f10x.h
  • BKP_DR9 : stm32f10x_bkp.h
  • BKP_DR9_D : stm32f10x.h
  • BKP_DR_NUMBER : STM32F10x_StdPeriph_Examples/BKP/Tamper/main.c , STM32F10x_StdPeriph_Examples/BKP/Backup_Data/main.c
  • BKP_OFFSET : stm32f10x_bkp.c
  • BKP_RTCCR_ASOE : stm32f10x.h
  • BKP_RTCCR_ASOS : stm32f10x.h
  • BKP_RTCCR_CAL : stm32f10x.h
  • BKP_RTCCR_CCO : stm32f10x.h
  • BKP_RTCOutputSource_Alarm : stm32f10x_bkp.h
  • BKP_RTCOutputSource_CalibClock : stm32f10x_bkp.h
  • BKP_RTCOutputSource_None : stm32f10x_bkp.h
  • BKP_RTCOutputSource_Second : stm32f10x_bkp.h
  • BKP_TamperPinLevel_High : stm32f10x_bkp.h
  • BKP_TamperPinLevel_Low : stm32f10x_bkp.h
  • Black : stm32_eval.h
  • BLOCK_SIZE : STM32F10x_StdPeriph_Examples/SDIO/uSDCard/main.c
  • BlockErase_Timeout : stm3210e_eval_fsmc_nor.c
  • Blue : stm32_eval.h
  • Blue2 : stm32_eval.h
  • BUFFER_SIZE : STM32F10x_StdPeriph_Examples/FSMC/NOR/main.c , STM32F10x_StdPeriph_Examples/FSMC/NAND/main.c , STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/main.c , STM32F10x_StdPeriph_Examples/FSMC/SRAM/main.c
  • BUFFER_SIZE1 : STM32F10x_StdPeriph_Examples/I2C/EEPROM/main.c
  • BUFFER_SIZE2 : STM32F10x_StdPeriph_Examples/I2C/EEPROM/main.c
  • BufferSize : STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/main.c , STM32F10x_StdPeriph_Examples/SPI/DMA/main.c , STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/main.c , STM32F10x_StdPeriph_Examples/SPI/CRC/main.c , STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/main.c , STM32F10x_StdPeriph_Examples/DMA/FSMC/main.c , STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/main.c , STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/main.c , STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/main.c , STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/main.c
  • Button_DOWN : stm32_eval.h
  • Button_KEY : stm32_eval.h
  • Button_LEFT : stm32_eval.h
  • Button_Mode_TypeDef : stm32_eval.h
  • Button_RIGHT : stm32_eval.h
  • Button_SEL : stm32_eval.h
  • Button_TAMPER : stm32_eval.h
  • Button_UP : stm32_eval.h
  • Button_WAKEUP : stm32_eval.h
  • BUTTONn : stm3210b_eval.h , stm3210e_eval.h , stm32100b_eval.h , stm32100e_eval.h , stm32l152_eval.h , stm3210c_eval.h


STM32F10x Standard Peripherals Firmware Library: Globals

  • File List
  • Globals
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- c -

  • CAN1 : stm32f10x.h
  • CAN1_BASE : stm32f10x.h
  • CAN2 : stm32f10x.h
  • CAN2_BASE : stm32f10x.h
  • CAN_BAUDRATE : STM32F10x_StdPeriph_Examples/CAN/DualCAN/main.c
  • CAN_BS1_10tq : stm32f10x_can.h
  • CAN_BS1_11tq : stm32f10x_can.h
  • CAN_BS1_12tq : stm32f10x_can.h
  • CAN_BS1_13tq : stm32f10x_can.h
  • CAN_BS1_14tq : stm32f10x_can.h
  • CAN_BS1_15tq : stm32f10x_can.h
  • CAN_BS1_16tq : stm32f10x_can.h
  • CAN_BS1_1tq : stm32f10x_can.h
  • CAN_BS1_2tq : stm32f10x_can.h
  • CAN_BS1_3tq : stm32f10x_can.h
  • CAN_BS1_4tq : stm32f10x_can.h
  • CAN_BS1_5tq : stm32f10x_can.h
  • CAN_BS1_6tq : stm32f10x_can.h
  • CAN_BS1_7tq : stm32f10x_can.h
  • CAN_BS1_8tq : stm32f10x_can.h
  • CAN_BS1_9tq : stm32f10x_can.h
  • CAN_BS2_1tq : stm32f10x_can.h
  • CAN_BS2_2tq : stm32f10x_can.h
  • CAN_BS2_3tq : stm32f10x_can.h
  • CAN_BS2_4tq : stm32f10x_can.h
  • CAN_BS2_5tq : stm32f10x_can.h
  • CAN_BS2_6tq : stm32f10x_can.h
  • CAN_BS2_7tq : stm32f10x_can.h
  • CAN_BS2_8tq : stm32f10x_can.h
  • CAN_BTR_BRP : stm32f10x.h
  • CAN_BTR_LBKM : stm32f10x.h
  • CAN_BTR_SILM : stm32f10x.h
  • CAN_BTR_SJW : stm32f10x.h
  • CAN_BTR_TS1 : stm32f10x.h
  • CAN_BTR_TS2 : stm32f10x.h
  • CAN_ErrorCode_ACKErr : stm32f10x_can.h
  • CAN_ErrorCode_BitDominantErr : stm32f10x_can.h
  • CAN_ErrorCode_BitRecessiveErr : stm32f10x_can.h
  • CAN_ErrorCode_CRCErr : stm32f10x_can.h
  • CAN_ErrorCode_FormErr : stm32f10x_can.h
  • CAN_ErrorCode_NoErr : stm32f10x_can.h
  • CAN_ErrorCode_SoftwareSetErr : stm32f10x_can.h
  • CAN_ErrorCode_StuffErr : stm32f10x_can.h
  • CAN_ESR_BOFF : stm32f10x.h
  • CAN_ESR_EPVF : stm32f10x.h
  • CAN_ESR_EWGF : stm32f10x.h
  • CAN_ESR_LEC : stm32f10x.h
  • CAN_ESR_LEC_0 : stm32f10x.h
  • CAN_ESR_LEC_1 : stm32f10x.h
  • CAN_ESR_LEC_2 : stm32f10x.h
  • CAN_ESR_REC : stm32f10x.h
  • CAN_ESR_TEC : stm32f10x.h
  • CAN_F0R1_FB0 : stm32f10x.h
  • CAN_F0R1_FB1 : stm32f10x.h
  • CAN_F0R1_FB10 : stm32f10x.h
  • CAN_F0R1_FB11 : stm32f10x.h
  • CAN_F0R1_FB12 : stm32f10x.h
  • CAN_F0R1_FB13 : stm32f10x.h
  • CAN_F0R1_FB14 : stm32f10x.h
  • CAN_F0R1_FB15 : stm32f10x.h
  • CAN_F0R1_FB16 : stm32f10x.h
  • CAN_F0R1_FB17 : stm32f10x.h
  • CAN_F0R1_FB18 : stm32f10x.h
  • CAN_F0R1_FB19 : stm32f10x.h
  • CAN_F0R1_FB2 : stm32f10x.h
  • CAN_F0R1_FB20 : stm32f10x.h
  • CAN_F0R1_FB21 : stm32f10x.h
  • CAN_F0R1_FB22 : stm32f10x.h
  • CAN_F0R1_FB23 : stm32f10x.h
  • CAN_F0R1_FB24 : stm32f10x.h
  • CAN_F0R1_FB25 : stm32f10x.h
  • CAN_F0R1_FB26 : stm32f10x.h
  • CAN_F0R1_FB27 : stm32f10x.h
  • CAN_F0R1_FB28 : stm32f10x.h
  • CAN_F0R1_FB29 : stm32f10x.h
  • CAN_F0R1_FB3 : stm32f10x.h
  • CAN_F0R1_FB30 : stm32f10x.h
  • CAN_F0R1_FB31 : stm32f10x.h
  • CAN_F0R1_FB4 : stm32f10x.h
  • CAN_F0R1_FB5 : stm32f10x.h
  • CAN_F0R1_FB6 : stm32f10x.h
  • CAN_F0R1_FB7 : stm32f10x.h
  • CAN_F0R1_FB8 : stm32f10x.h
  • CAN_F0R1_FB9 : stm32f10x.h
  • CAN_F0R2_FB0 : stm32f10x.h
  • CAN_F0R2_FB1 : stm32f10x.h
  • CAN_F0R2_FB10 : stm32f10x.h
  • CAN_F0R2_FB11 : stm32f10x.h
  • CAN_F0R2_FB12 : stm32f10x.h
  • CAN_F0R2_FB13 : stm32f10x.h
  • CAN_F0R2_FB14 : stm32f10x.h
  • CAN_F0R2_FB15 : stm32f10x.h
  • CAN_F0R2_FB16 : stm32f10x.h
  • CAN_F0R2_FB17 : stm32f10x.h
  • CAN_F0R2_FB18 : stm32f10x.h
  • CAN_F0R2_FB19 : stm32f10x.h
  • CAN_F0R2_FB2 : stm32f10x.h
  • CAN_F0R2_FB20 : stm32f10x.h
  • CAN_F0R2_FB21 : stm32f10x.h
  • CAN_F0R2_FB22 : stm32f10x.h
  • CAN_F0R2_FB23 : stm32f10x.h
  • CAN_F0R2_FB24 : stm32f10x.h
  • CAN_F0R2_FB25 : stm32f10x.h
  • CAN_F0R2_FB26 : stm32f10x.h
  • CAN_F0R2_FB27 : stm32f10x.h
  • CAN_F0R2_FB28 : stm32f10x.h
  • CAN_F0R2_FB29 : stm32f10x.h
  • CAN_F0R2_FB3 : stm32f10x.h
  • CAN_F0R2_FB30 : stm32f10x.h
  • CAN_F0R2_FB31 : stm32f10x.h
  • CAN_F0R2_FB4 : stm32f10x.h
  • CAN_F0R2_FB5 : stm32f10x.h
  • CAN_F0R2_FB6 : stm32f10x.h
  • CAN_F0R2_FB7 : stm32f10x.h
  • CAN_F0R2_FB8 : stm32f10x.h
  • CAN_F0R2_FB9 : stm32f10x.h
  • CAN_F10R1_FB0 : stm32f10x.h
  • CAN_F10R1_FB1 : stm32f10x.h
  • CAN_F10R1_FB10 : stm32f10x.h
  • CAN_F10R1_FB11 : stm32f10x.h
  • CAN_F10R1_FB12 : stm32f10x.h
  • CAN_F10R1_FB13 : stm32f10x.h
  • CAN_F10R1_FB14 : stm32f10x.h
  • CAN_F10R1_FB15 : stm32f10x.h
  • CAN_F10R1_FB16 : stm32f10x.h
  • CAN_F10R1_FB17 : stm32f10x.h
  • CAN_F10R1_FB18 : stm32f10x.h
  • CAN_F10R1_FB19 : stm32f10x.h
  • CAN_F10R1_FB2 : stm32f10x.h
  • CAN_F10R1_FB20 : stm32f10x.h
  • CAN_F10R1_FB21 : stm32f10x.h
  • CAN_F10R1_FB22 : stm32f10x.h
  • CAN_F10R1_FB23 : stm32f10x.h
  • CAN_F10R1_FB24 : stm32f10x.h
  • CAN_F10R1_FB25 : stm32f10x.h
  • CAN_F10R1_FB26 : stm32f10x.h
  • CAN_F10R1_FB27 : stm32f10x.h
  • CAN_F10R1_FB28 : stm32f10x.h
  • CAN_F10R1_FB29 : stm32f10x.h
  • CAN_F10R1_FB3 : stm32f10x.h
  • CAN_F10R1_FB30 : stm32f10x.h
  • CAN_F10R1_FB31 : stm32f10x.h
  • CAN_F10R1_FB4 : stm32f10x.h
  • CAN_F10R1_FB5 : stm32f10x.h
  • CAN_F10R1_FB6 : stm32f10x.h
  • CAN_F10R1_FB7 : stm32f10x.h
  • CAN_F10R1_FB8 : stm32f10x.h
  • CAN_F10R1_FB9 : stm32f10x.h
  • CAN_F10R2_FB0 : stm32f10x.h
  • CAN_F10R2_FB1 : stm32f10x.h
  • CAN_F10R2_FB10 : stm32f10x.h
  • CAN_F10R2_FB11 : stm32f10x.h
  • CAN_F10R2_FB12 : stm32f10x.h
  • CAN_F10R2_FB13 : stm32f10x.h
  • CAN_F10R2_FB14 : stm32f10x.h
  • CAN_F10R2_FB15 : stm32f10x.h
  • CAN_F10R2_FB16 : stm32f10x.h
  • CAN_F10R2_FB17 : stm32f10x.h
  • CAN_F10R2_FB18 : stm32f10x.h
  • CAN_F10R2_FB19 : stm32f10x.h
  • CAN_F10R2_FB2 : stm32f10x.h
  • CAN_F10R2_FB20 : stm32f10x.h
  • CAN_F10R2_FB21 : stm32f10x.h
  • CAN_F10R2_FB22 : stm32f10x.h
  • CAN_F10R2_FB23 : stm32f10x.h
  • CAN_F10R2_FB24 : stm32f10x.h
  • CAN_F10R2_FB25 : stm32f10x.h
  • CAN_F10R2_FB26 : stm32f10x.h
  • CAN_F10R2_FB27 : stm32f10x.h
  • CAN_F10R2_FB28 : stm32f10x.h
  • CAN_F10R2_FB29 : stm32f10x.h
  • CAN_F10R2_FB3 : stm32f10x.h
  • CAN_F10R2_FB30 : stm32f10x.h
  • CAN_F10R2_FB31 : stm32f10x.h
  • CAN_F10R2_FB4 : stm32f10x.h
  • CAN_F10R2_FB5 : stm32f10x.h
  • CAN_F10R2_FB6 : stm32f10x.h
  • CAN_F10R2_FB7 : stm32f10x.h
  • CAN_F10R2_FB8 : stm32f10x.h
  • CAN_F10R2_FB9 : stm32f10x.h
  • CAN_F11R1_FB0 : stm32f10x.h
  • CAN_F11R1_FB1 : stm32f10x.h
  • CAN_F11R1_FB10 : stm32f10x.h
  • CAN_F11R1_FB11 : stm32f10x.h
  • CAN_F11R1_FB12 : stm32f10x.h
  • CAN_F11R1_FB13 : stm32f10x.h
  • CAN_F11R1_FB14 : stm32f10x.h
  • CAN_F11R1_FB15 : stm32f10x.h
  • CAN_F11R1_FB16 : stm32f10x.h
  • CAN_F11R1_FB17 : stm32f10x.h
  • CAN_F11R1_FB18 : stm32f10x.h
  • CAN_F11R1_FB19 : stm32f10x.h
  • CAN_F11R1_FB2 : stm32f10x.h
  • CAN_F11R1_FB20 : stm32f10x.h
  • CAN_F11R1_FB21 : stm32f10x.h
  • CAN_F11R1_FB22 : stm32f10x.h
  • CAN_F11R1_FB23 : stm32f10x.h
  • CAN_F11R1_FB24 : stm32f10x.h
  • CAN_F11R1_FB25 : stm32f10x.h
  • CAN_F11R1_FB26 : stm32f10x.h
  • CAN_F11R1_FB27 : stm32f10x.h
  • CAN_F11R1_FB28 : stm32f10x.h
  • CAN_F11R1_FB29 : stm32f10x.h
  • CAN_F11R1_FB3 : stm32f10x.h
  • CAN_F11R1_FB30 : stm32f10x.h
  • CAN_F11R1_FB31 : stm32f10x.h
  • CAN_F11R1_FB4 : stm32f10x.h
  • CAN_F11R1_FB5 : stm32f10x.h
  • CAN_F11R1_FB6 : stm32f10x.h
  • CAN_F11R1_FB7 : stm32f10x.h
  • CAN_F11R1_FB8 : stm32f10x.h
  • CAN_F11R1_FB9 : stm32f10x.h
  • CAN_F11R2_FB0 : stm32f10x.h
  • CAN_F11R2_FB1 : stm32f10x.h
  • CAN_F11R2_FB10 : stm32f10x.h
  • CAN_F11R2_FB11 : stm32f10x.h
  • CAN_F11R2_FB12 : stm32f10x.h
  • CAN_F11R2_FB13 : stm32f10x.h
  • CAN_F11R2_FB14 : stm32f10x.h
  • CAN_F11R2_FB15 : stm32f10x.h
  • CAN_F11R2_FB16 : stm32f10x.h
  • CAN_F11R2_FB17 : stm32f10x.h
  • CAN_F11R2_FB18 : stm32f10x.h
  • CAN_F11R2_FB19 : stm32f10x.h
  • CAN_F11R2_FB2 : stm32f10x.h
  • CAN_F11R2_FB20 : stm32f10x.h
  • CAN_F11R2_FB21 : stm32f10x.h
  • CAN_F11R2_FB22 : stm32f10x.h
  • CAN_F11R2_FB23 : stm32f10x.h
  • CAN_F11R2_FB24 : stm32f10x.h
  • CAN_F11R2_FB25 : stm32f10x.h
  • CAN_F11R2_FB26 : stm32f10x.h
  • CAN_F11R2_FB27 : stm32f10x.h
  • CAN_F11R2_FB28 : stm32f10x.h
  • CAN_F11R2_FB29 : stm32f10x.h
  • CAN_F11R2_FB3 : stm32f10x.h
  • CAN_F11R2_FB30 : stm32f10x.h
  • CAN_F11R2_FB31 : stm32f10x.h
  • CAN_F11R2_FB4 : stm32f10x.h
  • CAN_F11R2_FB5 : stm32f10x.h
  • CAN_F11R2_FB6 : stm32f10x.h
  • CAN_F11R2_FB7 : stm32f10x.h
  • CAN_F11R2_FB8 : stm32f10x.h
  • CAN_F11R2_FB9 : stm32f10x.h
  • CAN_F12R1_FB0 : stm32f10x.h
  • CAN_F12R1_FB1 : stm32f10x.h
  • CAN_F12R1_FB10 : stm32f10x.h
  • CAN_F12R1_FB11 : stm32f10x.h
  • CAN_F12R1_FB12 : stm32f10x.h
  • CAN_F12R1_FB13 : stm32f10x.h
  • CAN_F12R1_FB14 : stm32f10x.h
  • CAN_F12R1_FB15 : stm32f10x.h
  • CAN_F12R1_FB16 : stm32f10x.h
  • CAN_F12R1_FB17 : stm32f10x.h
  • CAN_F12R1_FB18 : stm32f10x.h
  • CAN_F12R1_FB19 : stm32f10x.h
  • CAN_F12R1_FB2 : stm32f10x.h
  • CAN_F12R1_FB20 : stm32f10x.h
  • CAN_F12R1_FB21 : stm32f10x.h
  • CAN_F12R1_FB22 : stm32f10x.h
  • CAN_F12R1_FB23 : stm32f10x.h
  • CAN_F12R1_FB24 : stm32f10x.h
  • CAN_F12R1_FB25 : stm32f10x.h
  • CAN_F12R1_FB26 : stm32f10x.h
  • CAN_F12R1_FB27 : stm32f10x.h
  • CAN_F12R1_FB28 : stm32f10x.h
  • CAN_F12R1_FB29 : stm32f10x.h
  • CAN_F12R1_FB3 : stm32f10x.h
  • CAN_F12R1_FB30 : stm32f10x.h
  • CAN_F12R1_FB31 : stm32f10x.h
  • CAN_F12R1_FB4 : stm32f10x.h
  • CAN_F12R1_FB5 : stm32f10x.h
  • CAN_F12R1_FB6 : stm32f10x.h
  • CAN_F12R1_FB7 : stm32f10x.h
  • CAN_F12R1_FB8 : stm32f10x.h
  • CAN_F12R1_FB9 : stm32f10x.h
  • CAN_F12R2_FB0 : stm32f10x.h
  • CAN_F12R2_FB1 : stm32f10x.h
  • CAN_F12R2_FB10 : stm32f10x.h
  • CAN_F12R2_FB11 : stm32f10x.h
  • CAN_F12R2_FB12 : stm32f10x.h
  • CAN_F12R2_FB13 : stm32f10x.h
  • CAN_F12R2_FB14 : stm32f10x.h
  • CAN_F12R2_FB15 : stm32f10x.h
  • CAN_F12R2_FB16 : stm32f10x.h
  • CAN_F12R2_FB17 : stm32f10x.h
  • CAN_F12R2_FB18 : stm32f10x.h
  • CAN_F12R2_FB19 : stm32f10x.h
  • CAN_F12R2_FB2 : stm32f10x.h
  • CAN_F12R2_FB20 : stm32f10x.h
  • CAN_F12R2_FB21 : stm32f10x.h
  • CAN_F12R2_FB22 : stm32f10x.h
  • CAN_F12R2_FB23 : stm32f10x.h
  • CAN_F12R2_FB24 : stm32f10x.h
  • CAN_F12R2_FB25 : stm32f10x.h
  • CAN_F12R2_FB26 : stm32f10x.h
  • CAN_F12R2_FB27 : stm32f10x.h
  • CAN_F12R2_FB28 : stm32f10x.h
  • CAN_F12R2_FB29 : stm32f10x.h
  • CAN_F12R2_FB3 : stm32f10x.h
  • CAN_F12R2_FB30 : stm32f10x.h
  • CAN_F12R2_FB31 : stm32f10x.h
  • CAN_F12R2_FB4 : stm32f10x.h
  • CAN_F12R2_FB5 : stm32f10x.h
  • CAN_F12R2_FB6 : stm32f10x.h
  • CAN_F12R2_FB7 : stm32f10x.h
  • CAN_F12R2_FB8 : stm32f10x.h
  • CAN_F12R2_FB9 : stm32f10x.h
  • CAN_F13R1_FB0 : stm32f10x.h
  • CAN_F13R1_FB1 : stm32f10x.h
  • CAN_F13R1_FB10 : stm32f10x.h
  • CAN_F13R1_FB11 : stm32f10x.h
  • CAN_F13R1_FB12 : stm32f10x.h
  • CAN_F13R1_FB13 : stm32f10x.h
  • CAN_F13R1_FB14 : stm32f10x.h
  • CAN_F13R1_FB15 : stm32f10x.h
  • CAN_F13R1_FB16 : stm32f10x.h
  • CAN_F13R1_FB17 : stm32f10x.h
  • CAN_F13R1_FB18 : stm32f10x.h
  • CAN_F13R1_FB19 : stm32f10x.h
  • CAN_F13R1_FB2 : stm32f10x.h
  • CAN_F13R1_FB20 : stm32f10x.h
  • CAN_F13R1_FB21 : stm32f10x.h
  • CAN_F13R1_FB22 : stm32f10x.h
  • CAN_F13R1_FB23 : stm32f10x.h
  • CAN_F13R1_FB24 : stm32f10x.h
  • CAN_F13R1_FB25 : stm32f10x.h
  • CAN_F13R1_FB26 : stm32f10x.h
  • CAN_F13R1_FB27 : stm32f10x.h
  • CAN_F13R1_FB28 : stm32f10x.h
  • CAN_F13R1_FB29 : stm32f10x.h
  • CAN_F13R1_FB3 : stm32f10x.h
  • CAN_F13R1_FB30 : stm32f10x.h
  • CAN_F13R1_FB31 : stm32f10x.h
  • CAN_F13R1_FB4 : stm32f10x.h
  • CAN_F13R1_FB5 : stm32f10x.h
  • CAN_F13R1_FB6 : stm32f10x.h
  • CAN_F13R1_FB7 : stm32f10x.h
  • CAN_F13R1_FB8 : stm32f10x.h
  • CAN_F13R1_FB9 : stm32f10x.h
  • CAN_F13R2_FB0 : stm32f10x.h
  • CAN_F13R2_FB1 : stm32f10x.h
  • CAN_F13R2_FB10 : stm32f10x.h
  • CAN_F13R2_FB11 : stm32f10x.h
  • CAN_F13R2_FB12 : stm32f10x.h
  • CAN_F13R2_FB13 : stm32f10x.h
  • CAN_F13R2_FB14 : stm32f10x.h
  • CAN_F13R2_FB15 : stm32f10x.h
  • CAN_F13R2_FB16 : stm32f10x.h
  • CAN_F13R2_FB17 : stm32f10x.h
  • CAN_F13R2_FB18 : stm32f10x.h
  • CAN_F13R2_FB19 : stm32f10x.h
  • CAN_F13R2_FB2 : stm32f10x.h
  • CAN_F13R2_FB20 : stm32f10x.h
  • CAN_F13R2_FB21 : stm32f10x.h
  • CAN_F13R2_FB22 : stm32f10x.h
  • CAN_F13R2_FB23 : stm32f10x.h
  • CAN_F13R2_FB24 : stm32f10x.h
  • CAN_F13R2_FB25 : stm32f10x.h
  • CAN_F13R2_FB26 : stm32f10x.h
  • CAN_F13R2_FB27 : stm32f10x.h
  • CAN_F13R2_FB28 : stm32f10x.h
  • CAN_F13R2_FB29 : stm32f10x.h
  • CAN_F13R2_FB3 : stm32f10x.h
  • CAN_F13R2_FB30 : stm32f10x.h
  • CAN_F13R2_FB31 : stm32f10x.h
  • CAN_F13R2_FB4 : stm32f10x.h
  • CAN_F13R2_FB5 : stm32f10x.h
  • CAN_F13R2_FB6 : stm32f10x.h
  • CAN_F13R2_FB7 : stm32f10x.h
  • CAN_F13R2_FB8 : stm32f10x.h
  • CAN_F13R2_FB9 : stm32f10x.h
  • CAN_F1R1_FB0 : stm32f10x.h
  • CAN_F1R1_FB1 : stm32f10x.h
  • CAN_F1R1_FB10 : stm32f10x.h
  • CAN_F1R1_FB11 : stm32f10x.h
  • CAN_F1R1_FB12 : stm32f10x.h
  • CAN_F1R1_FB13 : stm32f10x.h
  • CAN_F1R1_FB14 : stm32f10x.h
  • CAN_F1R1_FB15 : stm32f10x.h
  • CAN_F1R1_FB16 : stm32f10x.h
  • CAN_F1R1_FB17 : stm32f10x.h
  • CAN_F1R1_FB18 : stm32f10x.h
  • CAN_F1R1_FB19 : stm32f10x.h
  • CAN_F1R1_FB2 : stm32f10x.h
  • CAN_F1R1_FB20 : stm32f10x.h
  • CAN_F1R1_FB21 : stm32f10x.h
  • CAN_F1R1_FB22 : stm32f10x.h
  • CAN_F1R1_FB23 : stm32f10x.h
  • CAN_F1R1_FB24 : stm32f10x.h
  • CAN_F1R1_FB25 : stm32f10x.h
  • CAN_F1R1_FB26 : stm32f10x.h
  • CAN_F1R1_FB27 : stm32f10x.h
  • CAN_F1R1_FB28 : stm32f10x.h
  • CAN_F1R1_FB29 : stm32f10x.h
  • CAN_F1R1_FB3 : stm32f10x.h
  • CAN_F1R1_FB30 : stm32f10x.h
  • CAN_F1R1_FB31 : stm32f10x.h
  • CAN_F1R1_FB4 : stm32f10x.h
  • CAN_F1R1_FB5 : stm32f10x.h
  • CAN_F1R1_FB6 : stm32f10x.h
  • CAN_F1R1_FB7 : stm32f10x.h
  • CAN_F1R1_FB8 : stm32f10x.h
  • CAN_F1R1_FB9 : stm32f10x.h
  • CAN_F1R2_FB0 : stm32f10x.h
  • CAN_F1R2_FB1 : stm32f10x.h
  • CAN_F1R2_FB10 : stm32f10x.h
  • CAN_F1R2_FB11 : stm32f10x.h
  • CAN_F1R2_FB12 : stm32f10x.h
  • CAN_F1R2_FB13 : stm32f10x.h
  • CAN_F1R2_FB14 : stm32f10x.h
  • CAN_F1R2_FB15 : stm32f10x.h
  • CAN_F1R2_FB16 : stm32f10x.h
  • CAN_F1R2_FB17 : stm32f10x.h
  • CAN_F1R2_FB18 : stm32f10x.h
  • CAN_F1R2_FB19 : stm32f10x.h
  • CAN_F1R2_FB2 : stm32f10x.h
  • CAN_F1R2_FB20 : stm32f10x.h
  • CAN_F1R2_FB21 : stm32f10x.h
  • CAN_F1R2_FB22 : stm32f10x.h
  • CAN_F1R2_FB23 : stm32f10x.h
  • CAN_F1R2_FB24 : stm32f10x.h
  • CAN_F1R2_FB25 : stm32f10x.h
  • CAN_F1R2_FB26 : stm32f10x.h
  • CAN_F1R2_FB27 : stm32f10x.h
  • CAN_F1R2_FB28 : stm32f10x.h
  • CAN_F1R2_FB29 : stm32f10x.h
  • CAN_F1R2_FB3 : stm32f10x.h
  • CAN_F1R2_FB30 : stm32f10x.h
  • CAN_F1R2_FB31 : stm32f10x.h
  • CAN_F1R2_FB4 : stm32f10x.h
  • CAN_F1R2_FB5 : stm32f10x.h
  • CAN_F1R2_FB6 : stm32f10x.h
  • CAN_F1R2_FB7 : stm32f10x.h
  • CAN_F1R2_FB8 : stm32f10x.h
  • CAN_F1R2_FB9 : stm32f10x.h
  • CAN_F2R1_FB0 : stm32f10x.h
  • CAN_F2R1_FB1 : stm32f10x.h
  • CAN_F2R1_FB10 : stm32f10x.h
  • CAN_F2R1_FB11 : stm32f10x.h
  • CAN_F2R1_FB12 : stm32f10x.h
  • CAN_F2R1_FB13 : stm32f10x.h
  • CAN_F2R1_FB14 : stm32f10x.h
  • CAN_F2R1_FB15 : stm32f10x.h
  • CAN_F2R1_FB16 : stm32f10x.h
  • CAN_F2R1_FB17 : stm32f10x.h
  • CAN_F2R1_FB18 : stm32f10x.h
  • CAN_F2R1_FB19 : stm32f10x.h
  • CAN_F2R1_FB2 : stm32f10x.h
  • CAN_F2R1_FB20 : stm32f10x.h
  • CAN_F2R1_FB21 : stm32f10x.h
  • CAN_F2R1_FB22 : stm32f10x.h
  • CAN_F2R1_FB23 : stm32f10x.h
  • CAN_F2R1_FB24 : stm32f10x.h
  • CAN_F2R1_FB25 : stm32f10x.h
  • CAN_F2R1_FB26 : stm32f10x.h
  • CAN_F2R1_FB27 : stm32f10x.h
  • CAN_F2R1_FB28 : stm32f10x.h
  • CAN_F2R1_FB29 : stm32f10x.h
  • CAN_F2R1_FB3 : stm32f10x.h
  • CAN_F2R1_FB30 : stm32f10x.h
  • CAN_F2R1_FB31 : stm32f10x.h
  • CAN_F2R1_FB4 : stm32f10x.h
  • CAN_F2R1_FB5 : stm32f10x.h
  • CAN_F2R1_FB6 : stm32f10x.h
  • CAN_F2R1_FB7 : stm32f10x.h
  • CAN_F2R1_FB8 : stm32f10x.h
  • CAN_F2R1_FB9 : stm32f10x.h
  • CAN_F2R2_FB0 : stm32f10x.h
  • CAN_F2R2_FB1 : stm32f10x.h
  • CAN_F2R2_FB10 : stm32f10x.h
  • CAN_F2R2_FB11 : stm32f10x.h
  • CAN_F2R2_FB12 : stm32f10x.h
  • CAN_F2R2_FB13 : stm32f10x.h
  • CAN_F2R2_FB14 : stm32f10x.h
  • CAN_F2R2_FB15 : stm32f10x.h
  • CAN_F2R2_FB16 : stm32f10x.h
  • CAN_F2R2_FB17 : stm32f10x.h
  • CAN_F2R2_FB18 : stm32f10x.h
  • CAN_F2R2_FB19 : stm32f10x.h
  • CAN_F2R2_FB2 : stm32f10x.h
  • CAN_F2R2_FB20 : stm32f10x.h
  • CAN_F2R2_FB21 : stm32f10x.h
  • CAN_F2R2_FB22 : stm32f10x.h
  • CAN_F2R2_FB23 : stm32f10x.h
  • CAN_F2R2_FB24 : stm32f10x.h
  • CAN_F2R2_FB25 : stm32f10x.h
  • CAN_F2R2_FB26 : stm32f10x.h
  • CAN_F2R2_FB27 : stm32f10x.h
  • CAN_F2R2_FB28 : stm32f10x.h
  • CAN_F2R2_FB29 : stm32f10x.h
  • CAN_F2R2_FB3 : stm32f10x.h
  • CAN_F2R2_FB30 : stm32f10x.h
  • CAN_F2R2_FB31 : stm32f10x.h
  • CAN_F2R2_FB4 : stm32f10x.h
  • CAN_F2R2_FB5 : stm32f10x.h
  • CAN_F2R2_FB6 : stm32f10x.h
  • CAN_F2R2_FB7 : stm32f10x.h
  • CAN_F2R2_FB8 : stm32f10x.h
  • CAN_F2R2_FB9 : stm32f10x.h
  • CAN_F3R1_FB0 : stm32f10x.h
  • CAN_F3R1_FB1 : stm32f10x.h
  • CAN_F3R1_FB10 : stm32f10x.h
  • CAN_F3R1_FB11 : stm32f10x.h
  • CAN_F3R1_FB12 : stm32f10x.h
  • CAN_F3R1_FB13 : stm32f10x.h
  • CAN_F3R1_FB14 : stm32f10x.h
  • CAN_F3R1_FB15 : stm32f10x.h
  • CAN_F3R1_FB16 : stm32f10x.h
  • CAN_F3R1_FB17 : stm32f10x.h
  • CAN_F3R1_FB18 : stm32f10x.h
  • CAN_F3R1_FB19 : stm32f10x.h
  • CAN_F3R1_FB2 : stm32f10x.h
  • CAN_F3R1_FB20 : stm32f10x.h
  • CAN_F3R1_FB21 : stm32f10x.h
  • CAN_F3R1_FB22 : stm32f10x.h
  • CAN_F3R1_FB23 : stm32f10x.h
  • CAN_F3R1_FB24 : stm32f10x.h
  • CAN_F3R1_FB25 : stm32f10x.h
  • CAN_F3R1_FB26 : stm32f10x.h
  • CAN_F3R1_FB27 : stm32f10x.h
  • CAN_F3R1_FB28 : stm32f10x.h
  • CAN_F3R1_FB29 : stm32f10x.h
  • CAN_F3R1_FB3 : stm32f10x.h
  • CAN_F3R1_FB30 : stm32f10x.h
  • CAN_F3R1_FB31 : stm32f10x.h
  • CAN_F3R1_FB4 : stm32f10x.h
  • CAN_F3R1_FB5 : stm32f10x.h
  • CAN_F3R1_FB6 : stm32f10x.h
  • CAN_F3R1_FB7 : stm32f10x.h
  • CAN_F3R1_FB8 : stm32f10x.h
  • CAN_F3R1_FB9 : stm32f10x.h
  • CAN_F3R2_FB0 : stm32f10x.h
  • CAN_F3R2_FB1 : stm32f10x.h
  • CAN_F3R2_FB10 : stm32f10x.h
  • CAN_F3R2_FB11 : stm32f10x.h
  • CAN_F3R2_FB12 : stm32f10x.h
  • CAN_F3R2_FB13 : stm32f10x.h
  • CAN_F3R2_FB14 : stm32f10x.h
  • CAN_F3R2_FB15 : stm32f10x.h
  • CAN_F3R2_FB16 : stm32f10x.h
  • CAN_F3R2_FB17 : stm32f10x.h
  • CAN_F3R2_FB18 : stm32f10x.h
  • CAN_F3R2_FB19 : stm32f10x.h
  • CAN_F3R2_FB2 : stm32f10x.h
  • CAN_F3R2_FB20 : stm32f10x.h
  • CAN_F3R2_FB21 : stm32f10x.h
  • CAN_F3R2_FB22 : stm32f10x.h
  • CAN_F3R2_FB23 : stm32f10x.h
  • CAN_F3R2_FB24 : stm32f10x.h
  • CAN_F3R2_FB25 : stm32f10x.h
  • CAN_F3R2_FB26 : stm32f10x.h
  • CAN_F3R2_FB27 : stm32f10x.h
  • CAN_F3R2_FB28 : stm32f10x.h
  • CAN_F3R2_FB29 : stm32f10x.h
  • CAN_F3R2_FB3 : stm32f10x.h
  • CAN_F3R2_FB30 : stm32f10x.h
  • CAN_F3R2_FB31 : stm32f10x.h
  • CAN_F3R2_FB4 : stm32f10x.h
  • CAN_F3R2_FB5 : stm32f10x.h
  • CAN_F3R2_FB6 : stm32f10x.h
  • CAN_F3R2_FB7 : stm32f10x.h
  • CAN_F3R2_FB8 : stm32f10x.h
  • CAN_F3R2_FB9 : stm32f10x.h
  • CAN_F4R1_FB0 : stm32f10x.h
  • CAN_F4R1_FB1 : stm32f10x.h
  • CAN_F4R1_FB10 : stm32f10x.h
  • CAN_F4R1_FB11 : stm32f10x.h
  • CAN_F4R1_FB12 : stm32f10x.h
  • CAN_F4R1_FB13 : stm32f10x.h
  • CAN_F4R1_FB14 : stm32f10x.h
  • CAN_F4R1_FB15 : stm32f10x.h
  • CAN_F4R1_FB16 : stm32f10x.h
  • CAN_F4R1_FB17 : stm32f10x.h
  • CAN_F4R1_FB18 : stm32f10x.h
  • CAN_F4R1_FB19 : stm32f10x.h
  • CAN_F4R1_FB2 : stm32f10x.h
  • CAN_F4R1_FB20 : stm32f10x.h
  • CAN_F4R1_FB21 : stm32f10x.h
  • CAN_F4R1_FB22 : stm32f10x.h
  • CAN_F4R1_FB23 : stm32f10x.h
  • CAN_F4R1_FB24 : stm32f10x.h
  • CAN_F4R1_FB25 : stm32f10x.h
  • CAN_F4R1_FB26 : stm32f10x.h
  • CAN_F4R1_FB27 : stm32f10x.h
  • CAN_F4R1_FB28 : stm32f10x.h
  • CAN_F4R1_FB29 : stm32f10x.h
  • CAN_F4R1_FB3 : stm32f10x.h
  • CAN_F4R1_FB30 : stm32f10x.h
  • CAN_F4R1_FB31 : stm32f10x.h
  • CAN_F4R1_FB4 : stm32f10x.h
  • CAN_F4R1_FB5 : stm32f10x.h
  • CAN_F4R1_FB6 : stm32f10x.h
  • CAN_F4R1_FB7 : stm32f10x.h
  • CAN_F4R1_FB8 : stm32f10x.h
  • CAN_F4R1_FB9 : stm32f10x.h
  • CAN_F4R2_FB0 : stm32f10x.h
  • CAN_F4R2_FB1 : stm32f10x.h
  • CAN_F4R2_FB10 : stm32f10x.h
  • CAN_F4R2_FB11 : stm32f10x.h
  • CAN_F4R2_FB12 : stm32f10x.h
  • CAN_F4R2_FB13 : stm32f10x.h
  • CAN_F4R2_FB14 : stm32f10x.h
  • CAN_F4R2_FB15 : stm32f10x.h
  • CAN_F4R2_FB16 : stm32f10x.h
  • CAN_F4R2_FB17 : stm32f10x.h
  • CAN_F4R2_FB18 : stm32f10x.h
  • CAN_F4R2_FB19 : stm32f10x.h
  • CAN_F4R2_FB2 : stm32f10x.h
  • CAN_F4R2_FB20 : stm32f10x.h
  • CAN_F4R2_FB21 : stm32f10x.h
  • CAN_F4R2_FB22 : stm32f10x.h
  • CAN_F4R2_FB23 : stm32f10x.h
  • CAN_F4R2_FB24 : stm32f10x.h
  • CAN_F4R2_FB25 : stm32f10x.h
  • CAN_F4R2_FB26 : stm32f10x.h
  • CAN_F4R2_FB27 : stm32f10x.h
  • CAN_F4R2_FB28 : stm32f10x.h
  • CAN_F4R2_FB29 : stm32f10x.h
  • CAN_F4R2_FB3 : stm32f10x.h
  • CAN_F4R2_FB30 : stm32f10x.h
  • CAN_F4R2_FB31 : stm32f10x.h
  • CAN_F4R2_FB4 : stm32f10x.h
  • CAN_F4R2_FB5 : stm32f10x.h
  • CAN_F4R2_FB6 : stm32f10x.h
  • CAN_F4R2_FB7 : stm32f10x.h
  • CAN_F4R2_FB8 : stm32f10x.h
  • CAN_F4R2_FB9 : stm32f10x.h
  • CAN_F5R1_FB0 : stm32f10x.h
  • CAN_F5R1_FB1 : stm32f10x.h
  • CAN_F5R1_FB10 : stm32f10x.h
  • CAN_F5R1_FB11 : stm32f10x.h
  • CAN_F5R1_FB12 : stm32f10x.h
  • CAN_F5R1_FB13 : stm32f10x.h
  • CAN_F5R1_FB14 : stm32f10x.h
  • CAN_F5R1_FB15 : stm32f10x.h
  • CAN_F5R1_FB16 : stm32f10x.h
  • CAN_F5R1_FB17 : stm32f10x.h
  • CAN_F5R1_FB18 : stm32f10x.h
  • CAN_F5R1_FB19 : stm32f10x.h
  • CAN_F5R1_FB2 : stm32f10x.h
  • CAN_F5R1_FB20 : stm32f10x.h
  • CAN_F5R1_FB21 : stm32f10x.h
  • CAN_F5R1_FB22 : stm32f10x.h
  • CAN_F5R1_FB23 : stm32f10x.h
  • CAN_F5R1_FB24 : stm32f10x.h
  • CAN_F5R1_FB25 : stm32f10x.h
  • CAN_F5R1_FB26 : stm32f10x.h
  • CAN_F5R1_FB27 : stm32f10x.h
  • CAN_F5R1_FB28 : stm32f10x.h
  • CAN_F5R1_FB29 : stm32f10x.h
  • CAN_F5R1_FB3 : stm32f10x.h
  • CAN_F5R1_FB30 : stm32f10x.h
  • CAN_F5R1_FB31 : stm32f10x.h
  • CAN_F5R1_FB4 : stm32f10x.h
  • CAN_F5R1_FB5 : stm32f10x.h
  • CAN_F5R1_FB6 : stm32f10x.h
  • CAN_F5R1_FB7 : stm32f10x.h
  • CAN_F5R1_FB8 : stm32f10x.h
  • CAN_F5R1_FB9 : stm32f10x.h
  • CAN_F5R2_FB0 : stm32f10x.h
  • CAN_F5R2_FB1 : stm32f10x.h
  • CAN_F5R2_FB10 : stm32f10x.h
  • CAN_F5R2_FB11 : stm32f10x.h
  • CAN_F5R2_FB12 : stm32f10x.h
  • CAN_F5R2_FB13 : stm32f10x.h
  • CAN_F5R2_FB14 : stm32f10x.h
  • CAN_F5R2_FB15 : stm32f10x.h
  • CAN_F5R2_FB16 : stm32f10x.h
  • CAN_F5R2_FB17 : stm32f10x.h
  • CAN_F5R2_FB18 : stm32f10x.h
  • CAN_F5R2_FB19 : stm32f10x.h
  • CAN_F5R2_FB2 : stm32f10x.h
  • CAN_F5R2_FB20 : stm32f10x.h
  • CAN_F5R2_FB21 : stm32f10x.h
  • CAN_F5R2_FB22 : stm32f10x.h
  • CAN_F5R2_FB23 : stm32f10x.h
  • CAN_F5R2_FB24 : stm32f10x.h
  • CAN_F5R2_FB25 : stm32f10x.h
  • CAN_F5R2_FB26 : stm32f10x.h
  • CAN_F5R2_FB27 : stm32f10x.h
  • CAN_F5R2_FB28 : stm32f10x.h
  • CAN_F5R2_FB29 : stm32f10x.h
  • CAN_F5R2_FB3 : stm32f10x.h
  • CAN_F5R2_FB30 : stm32f10x.h
  • CAN_F5R2_FB31 : stm32f10x.h
  • CAN_F5R2_FB4 : stm32f10x.h
  • CAN_F5R2_FB5 : stm32f10x.h
  • CAN_F5R2_FB6 : stm32f10x.h
  • CAN_F5R2_FB7 : stm32f10x.h
  • CAN_F5R2_FB8 : stm32f10x.h
  • CAN_F5R2_FB9 : stm32f10x.h
  • CAN_F6R1_FB0 : stm32f10x.h
  • CAN_F6R1_FB1 : stm32f10x.h
  • CAN_F6R1_FB10 : stm32f10x.h
  • CAN_F6R1_FB11 : stm32f10x.h
  • CAN_F6R1_FB12 : stm32f10x.h
  • CAN_F6R1_FB13 : stm32f10x.h
  • CAN_F6R1_FB14 : stm32f10x.h
  • CAN_F6R1_FB15 : stm32f10x.h
  • CAN_F6R1_FB16 : stm32f10x.h
  • CAN_F6R1_FB17 : stm32f10x.h
  • CAN_F6R1_FB18 : stm32f10x.h
  • CAN_F6R1_FB19 : stm32f10x.h
  • CAN_F6R1_FB2 : stm32f10x.h
  • CAN_F6R1_FB20 : stm32f10x.h
  • CAN_F6R1_FB21 : stm32f10x.h
  • CAN_F6R1_FB22 : stm32f10x.h
  • CAN_F6R1_FB23 : stm32f10x.h
  • CAN_F6R1_FB24 : stm32f10x.h
  • CAN_F6R1_FB25 : stm32f10x.h
  • CAN_F6R1_FB26 : stm32f10x.h
  • CAN_F6R1_FB27 : stm32f10x.h
  • CAN_F6R1_FB28 : stm32f10x.h
  • CAN_F6R1_FB29 : stm32f10x.h
  • CAN_F6R1_FB3 : stm32f10x.h
  • CAN_F6R1_FB30 : stm32f10x.h
  • CAN_F6R1_FB31 : stm32f10x.h
  • CAN_F6R1_FB4 : stm32f10x.h
  • CAN_F6R1_FB5 : stm32f10x.h
  • CAN_F6R1_FB6 : stm32f10x.h
  • CAN_F6R1_FB7 : stm32f10x.h
  • CAN_F6R1_FB8 : stm32f10x.h
  • CAN_F6R1_FB9 : stm32f10x.h
  • CAN_F6R2_FB0 : stm32f10x.h
  • CAN_F6R2_FB1 : stm32f10x.h
  • CAN_F6R2_FB10 : stm32f10x.h
  • CAN_F6R2_FB11 : stm32f10x.h
  • CAN_F6R2_FB12 : stm32f10x.h
  • CAN_F6R2_FB13 : stm32f10x.h
  • CAN_F6R2_FB14 : stm32f10x.h
  • CAN_F6R2_FB15 : stm32f10x.h
  • CAN_F6R2_FB16 : stm32f10x.h
  • CAN_F6R2_FB17 : stm32f10x.h
  • CAN_F6R2_FB18 : stm32f10x.h
  • CAN_F6R2_FB19 : stm32f10x.h
  • CAN_F6R2_FB2 : stm32f10x.h
  • CAN_F6R2_FB20 : stm32f10x.h
  • CAN_F6R2_FB21 : stm32f10x.h
  • CAN_F6R2_FB22 : stm32f10x.h
  • CAN_F6R2_FB23 : stm32f10x.h
  • CAN_F6R2_FB24 : stm32f10x.h
  • CAN_F6R2_FB25 : stm32f10x.h
  • CAN_F6R2_FB26 : stm32f10x.h
  • CAN_F6R2_FB27 : stm32f10x.h
  • CAN_F6R2_FB28 : stm32f10x.h
  • CAN_F6R2_FB29 : stm32f10x.h
  • CAN_F6R2_FB3 : stm32f10x.h
  • CAN_F6R2_FB30 : stm32f10x.h
  • CAN_F6R2_FB31 : stm32f10x.h
  • CAN_F6R2_FB4 : stm32f10x.h
  • CAN_F6R2_FB5 : stm32f10x.h
  • CAN_F6R2_FB6 : stm32f10x.h
  • CAN_F6R2_FB7 : stm32f10x.h
  • CAN_F6R2_FB8 : stm32f10x.h
  • CAN_F6R2_FB9 : stm32f10x.h
  • CAN_F7R1_FB0 : stm32f10x.h
  • CAN_F7R1_FB1 : stm32f10x.h
  • CAN_F7R1_FB10 : stm32f10x.h
  • CAN_F7R1_FB11 : stm32f10x.h
  • CAN_F7R1_FB12 : stm32f10x.h
  • CAN_F7R1_FB13 : stm32f10x.h
  • CAN_F7R1_FB14 : stm32f10x.h
  • CAN_F7R1_FB15 : stm32f10x.h
  • CAN_F7R1_FB16 : stm32f10x.h
  • CAN_F7R1_FB17 : stm32f10x.h
  • CAN_F7R1_FB18 : stm32f10x.h
  • CAN_F7R1_FB19 : stm32f10x.h
  • CAN_F7R1_FB2 : stm32f10x.h
  • CAN_F7R1_FB20 : stm32f10x.h
  • CAN_F7R1_FB21 : stm32f10x.h
  • CAN_F7R1_FB22 : stm32f10x.h
  • CAN_F7R1_FB23 : stm32f10x.h
  • CAN_F7R1_FB24 : stm32f10x.h
  • CAN_F7R1_FB25 : stm32f10x.h
  • CAN_F7R1_FB26 : stm32f10x.h
  • CAN_F7R1_FB27 : stm32f10x.h
  • CAN_F7R1_FB28 : stm32f10x.h
  • CAN_F7R1_FB29 : stm32f10x.h
  • CAN_F7R1_FB3 : stm32f10x.h
  • CAN_F7R1_FB30 : stm32f10x.h
  • CAN_F7R1_FB31 : stm32f10x.h
  • CAN_F7R1_FB4 : stm32f10x.h
  • CAN_F7R1_FB5 : stm32f10x.h
  • CAN_F7R1_FB6 : stm32f10x.h
  • CAN_F7R1_FB7 : stm32f10x.h
  • CAN_F7R1_FB8 : stm32f10x.h
  • CAN_F7R1_FB9 : stm32f10x.h
  • CAN_F7R2_FB0 : stm32f10x.h
  • CAN_F7R2_FB1 : stm32f10x.h
  • CAN_F7R2_FB10 : stm32f10x.h
  • CAN_F7R2_FB11 : stm32f10x.h
  • CAN_F7R2_FB12 : stm32f10x.h
  • CAN_F7R2_FB13 : stm32f10x.h
  • CAN_F7R2_FB14 : stm32f10x.h
  • CAN_F7R2_FB15 : stm32f10x.h
  • CAN_F7R2_FB16 : stm32f10x.h
  • CAN_F7R2_FB17 : stm32f10x.h
  • CAN_F7R2_FB18 : stm32f10x.h
  • CAN_F7R2_FB19 : stm32f10x.h
  • CAN_F7R2_FB2 : stm32f10x.h
  • CAN_F7R2_FB20 : stm32f10x.h
  • CAN_F7R2_FB21 : stm32f10x.h
  • CAN_F7R2_FB22 : stm32f10x.h
  • CAN_F7R2_FB23 : stm32f10x.h
  • CAN_F7R2_FB24 : stm32f10x.h
  • CAN_F7R2_FB25 : stm32f10x.h
  • CAN_F7R2_FB26 : stm32f10x.h
  • CAN_F7R2_FB27 : stm32f10x.h
  • CAN_F7R2_FB28 : stm32f10x.h
  • CAN_F7R2_FB29 : stm32f10x.h
  • CAN_F7R2_FB3 : stm32f10x.h
  • CAN_F7R2_FB30 : stm32f10x.h
  • CAN_F7R2_FB31 : stm32f10x.h
  • CAN_F7R2_FB4 : stm32f10x.h
  • CAN_F7R2_FB5 : stm32f10x.h
  • CAN_F7R2_FB6 : stm32f10x.h
  • CAN_F7R2_FB7 : stm32f10x.h
  • CAN_F7R2_FB8 : stm32f10x.h
  • CAN_F7R2_FB9 : stm32f10x.h
  • CAN_F8R1_FB0 : stm32f10x.h
  • CAN_F8R1_FB1 : stm32f10x.h
  • CAN_F8R1_FB10 : stm32f10x.h
  • CAN_F8R1_FB11 : stm32f10x.h
  • CAN_F8R1_FB12 : stm32f10x.h
  • CAN_F8R1_FB13 : stm32f10x.h
  • CAN_F8R1_FB14 : stm32f10x.h
  • CAN_F8R1_FB15 : stm32f10x.h
  • CAN_F8R1_FB16 : stm32f10x.h
  • CAN_F8R1_FB17 : stm32f10x.h
  • CAN_F8R1_FB18 : stm32f10x.h
  • CAN_F8R1_FB19 : stm32f10x.h
  • CAN_F8R1_FB2 : stm32f10x.h
  • CAN_F8R1_FB20 : stm32f10x.h
  • CAN_F8R1_FB21 : stm32f10x.h
  • CAN_F8R1_FB22 : stm32f10x.h
  • CAN_F8R1_FB23 : stm32f10x.h
  • CAN_F8R1_FB24 : stm32f10x.h
  • CAN_F8R1_FB25 : stm32f10x.h
  • CAN_F8R1_FB26 : stm32f10x.h
  • CAN_F8R1_FB27 : stm32f10x.h
  • CAN_F8R1_FB28 : stm32f10x.h
  • CAN_F8R1_FB29 : stm32f10x.h
  • CAN_F8R1_FB3 : stm32f10x.h
  • CAN_F8R1_FB30 : stm32f10x.h
  • CAN_F8R1_FB31 : stm32f10x.h
  • CAN_F8R1_FB4 : stm32f10x.h
  • CAN_F8R1_FB5 : stm32f10x.h
  • CAN_F8R1_FB6 : stm32f10x.h
  • CAN_F8R1_FB7 : stm32f10x.h
  • CAN_F8R1_FB8 : stm32f10x.h
  • CAN_F8R1_FB9 : stm32f10x.h
  • CAN_F8R2_FB0 : stm32f10x.h
  • CAN_F8R2_FB1 : stm32f10x.h
  • CAN_F8R2_FB10 : stm32f10x.h
  • CAN_F8R2_FB11 : stm32f10x.h
  • CAN_F8R2_FB12 : stm32f10x.h
  • CAN_F8R2_FB13 : stm32f10x.h
  • CAN_F8R2_FB14 : stm32f10x.h
  • CAN_F8R2_FB15 : stm32f10x.h
  • CAN_F8R2_FB16 : stm32f10x.h
  • CAN_F8R2_FB17 : stm32f10x.h
  • CAN_F8R2_FB18 : stm32f10x.h
  • CAN_F8R2_FB19 : stm32f10x.h
  • CAN_F8R2_FB2 : stm32f10x.h
  • CAN_F8R2_FB20 : stm32f10x.h
  • CAN_F8R2_FB21 : stm32f10x.h
  • CAN_F8R2_FB22 : stm32f10x.h
  • CAN_F8R2_FB23 : stm32f10x.h
  • CAN_F8R2_FB24 : stm32f10x.h
  • CAN_F8R2_FB25 : stm32f10x.h
  • CAN_F8R2_FB26 : stm32f10x.h
  • CAN_F8R2_FB27 : stm32f10x.h
  • CAN_F8R2_FB28 : stm32f10x.h
  • CAN_F8R2_FB29 : stm32f10x.h
  • CAN_F8R2_FB3 : stm32f10x.h
  • CAN_F8R2_FB30 : stm32f10x.h
  • CAN_F8R2_FB31 : stm32f10x.h
  • CAN_F8R2_FB4 : stm32f10x.h
  • CAN_F8R2_FB5 : stm32f10x.h
  • CAN_F8R2_FB6 : stm32f10x.h
  • CAN_F8R2_FB7 : stm32f10x.h
  • CAN_F8R2_FB8 : stm32f10x.h
  • CAN_F8R2_FB9 : stm32f10x.h
  • CAN_F9R1_FB0 : stm32f10x.h
  • CAN_F9R1_FB1 : stm32f10x.h
  • CAN_F9R1_FB10 : stm32f10x.h
  • CAN_F9R1_FB11 : stm32f10x.h
  • CAN_F9R1_FB12 : stm32f10x.h
  • CAN_F9R1_FB13 : stm32f10x.h
  • CAN_F9R1_FB14 : stm32f10x.h
  • CAN_F9R1_FB15 : stm32f10x.h
  • CAN_F9R1_FB16 : stm32f10x.h
  • CAN_F9R1_FB17 : stm32f10x.h
  • CAN_F9R1_FB18 : stm32f10x.h
  • CAN_F9R1_FB19 : stm32f10x.h
  • CAN_F9R1_FB2 : stm32f10x.h
  • CAN_F9R1_FB20 : stm32f10x.h
  • CAN_F9R1_FB21 : stm32f10x.h
  • CAN_F9R1_FB22 : stm32f10x.h
  • CAN_F9R1_FB23 : stm32f10x.h
  • CAN_F9R1_FB24 : stm32f10x.h
  • CAN_F9R1_FB25 : stm32f10x.h
  • CAN_F9R1_FB26 : stm32f10x.h
  • CAN_F9R1_FB27 : stm32f10x.h
  • CAN_F9R1_FB28 : stm32f10x.h
  • CAN_F9R1_FB29 : stm32f10x.h
  • CAN_F9R1_FB3 : stm32f10x.h
  • CAN_F9R1_FB30 : stm32f10x.h
  • CAN_F9R1_FB31 : stm32f10x.h
  • CAN_F9R1_FB4 : stm32f10x.h
  • CAN_F9R1_FB5 : stm32f10x.h
  • CAN_F9R1_FB6 : stm32f10x.h
  • CAN_F9R1_FB7 : stm32f10x.h
  • CAN_F9R1_FB8 : stm32f10x.h
  • CAN_F9R1_FB9 : stm32f10x.h
  • CAN_F9R2_FB0 : stm32f10x.h
  • CAN_F9R2_FB1 : stm32f10x.h
  • CAN_F9R2_FB10 : stm32f10x.h
  • CAN_F9R2_FB11 : stm32f10x.h
  • CAN_F9R2_FB12 : stm32f10x.h
  • CAN_F9R2_FB13 : stm32f10x.h
  • CAN_F9R2_FB14 : stm32f10x.h
  • CAN_F9R2_FB15 : stm32f10x.h
  • CAN_F9R2_FB16 : stm32f10x.h
  • CAN_F9R2_FB17 : stm32f10x.h
  • CAN_F9R2_FB18 : stm32f10x.h
  • CAN_F9R2_FB19 : stm32f10x.h
  • CAN_F9R2_FB2 : stm32f10x.h
  • CAN_F9R2_FB20 : stm32f10x.h
  • CAN_F9R2_FB21 : stm32f10x.h
  • CAN_F9R2_FB22 : stm32f10x.h
  • CAN_F9R2_FB23 : stm32f10x.h
  • CAN_F9R2_FB24 : stm32f10x.h
  • CAN_F9R2_FB25 : stm32f10x.h
  • CAN_F9R2_FB26 : stm32f10x.h
  • CAN_F9R2_FB27 : stm32f10x.h
  • CAN_F9R2_FB28 : stm32f10x.h
  • CAN_F9R2_FB29 : stm32f10x.h
  • CAN_F9R2_FB3 : stm32f10x.h
  • CAN_F9R2_FB30 : stm32f10x.h
  • CAN_F9R2_FB31 : stm32f10x.h
  • CAN_F9R2_FB4 : stm32f10x.h
  • CAN_F9R2_FB5 : stm32f10x.h
  • CAN_F9R2_FB6 : stm32f10x.h
  • CAN_F9R2_FB7 : stm32f10x.h
  • CAN_F9R2_FB8 : stm32f10x.h
  • CAN_F9R2_FB9 : stm32f10x.h
  • CAN_FA1R_FACT : stm32f10x.h
  • CAN_FA1R_FACT0 : stm32f10x.h
  • CAN_FA1R_FACT1 : stm32f10x.h
  • CAN_FA1R_FACT10 : stm32f10x.h
  • CAN_FA1R_FACT11 : stm32f10x.h
  • CAN_FA1R_FACT12 : stm32f10x.h
  • CAN_FA1R_FACT13 : stm32f10x.h
  • CAN_FA1R_FACT2 : stm32f10x.h
  • CAN_FA1R_FACT3 : stm32f10x.h
  • CAN_FA1R_FACT4 : stm32f10x.h
  • CAN_FA1R_FACT5 : stm32f10x.h
  • CAN_FA1R_FACT6 : stm32f10x.h
  • CAN_FA1R_FACT7 : stm32f10x.h
  • CAN_FA1R_FACT8 : stm32f10x.h
  • CAN_FA1R_FACT9 : stm32f10x.h
  • CAN_FFA1R_FFA : stm32f10x.h
  • CAN_FFA1R_FFA0 : stm32f10x.h
  • CAN_FFA1R_FFA1 : stm32f10x.h
  • CAN_FFA1R_FFA10 : stm32f10x.h
  • CAN_FFA1R_FFA11 : stm32f10x.h
  • CAN_FFA1R_FFA12 : stm32f10x.h
  • CAN_FFA1R_FFA13 : stm32f10x.h
  • CAN_FFA1R_FFA2 : stm32f10x.h
  • CAN_FFA1R_FFA3 : stm32f10x.h
  • CAN_FFA1R_FFA4 : stm32f10x.h
  • CAN_FFA1R_FFA5 : stm32f10x.h
  • CAN_FFA1R_FFA6 : stm32f10x.h
  • CAN_FFA1R_FFA7 : stm32f10x.h
  • CAN_FFA1R_FFA8 : stm32f10x.h
  • CAN_FFA1R_FFA9 : stm32f10x.h
  • CAN_FIFO0 : stm32f10x_can.h
  • CAN_FIFO1 : stm32f10x_can.h
  • CAN_Filter_FIFO0 : stm32f10x_can.h
  • CAN_Filter_FIFO1 : stm32f10x_can.h
  • CAN_FilterFIFO0 : stm32f10x_can.h
  • CAN_FilterFIFO1 : stm32f10x_can.h
  • CAN_FilterMode_IdList : stm32f10x_can.h
  • CAN_FilterMode_IdMask : stm32f10x_can.h
  • CAN_FilterScale_16bit : stm32f10x_can.h
  • CAN_FilterScale_32bit : stm32f10x_can.h
  • CAN_FLAG_BOF : stm32f10x_can.h
  • CAN_FLAG_EPV : stm32f10x_can.h
  • CAN_FLAG_EWG : stm32f10x_can.h
  • CAN_FLAG_FF0 : stm32f10x_can.h
  • CAN_FLAG_FF1 : stm32f10x_can.h
  • CAN_FLAG_FMP0 : stm32f10x_can.h
  • CAN_FLAG_FMP1 : stm32f10x_can.h
  • CAN_FLAG_FOV0 : stm32f10x_can.h
  • CAN_FLAG_FOV1 : stm32f10x_can.h
  • CAN_FLAG_LEC : stm32f10x_can.h
  • CAN_FLAG_RQCP0 : stm32f10x_can.h
  • CAN_FLAG_RQCP1 : stm32f10x_can.h
  • CAN_FLAG_RQCP2 : stm32f10x_can.h
  • CAN_FLAG_SLAK : stm32f10x_can.h
  • CAN_FLAG_WKU : stm32f10x_can.h
  • CAN_FLAGS_ESR : stm32f10x_can.c
  • CAN_FLAGS_MSR : stm32f10x_can.c
  • CAN_FLAGS_RF0R : stm32f10x_can.c
  • CAN_FLAGS_RF1R : stm32f10x_can.c
  • CAN_FLAGS_TSR : stm32f10x_can.c
  • CAN_FM1R_FBM : stm32f10x.h
  • CAN_FM1R_FBM0 : stm32f10x.h
  • CAN_FM1R_FBM1 : stm32f10x.h
  • CAN_FM1R_FBM10 : stm32f10x.h
  • CAN_FM1R_FBM11 : stm32f10x.h
  • CAN_FM1R_FBM12 : stm32f10x.h
  • CAN_FM1R_FBM13 : stm32f10x.h
  • CAN_FM1R_FBM2 : stm32f10x.h
  • CAN_FM1R_FBM3 : stm32f10x.h
  • CAN_FM1R_FBM4 : stm32f10x.h
  • CAN_FM1R_FBM5 : stm32f10x.h
  • CAN_FM1R_FBM6 : stm32f10x.h
  • CAN_FM1R_FBM7 : stm32f10x.h
  • CAN_FM1R_FBM8 : stm32f10x.h
  • CAN_FM1R_FBM9 : stm32f10x.h
  • CAN_FMR_FINIT : stm32f10x.h
  • CAN_FS1R_FSC : stm32f10x.h
  • CAN_FS1R_FSC0 : stm32f10x.h
  • CAN_FS1R_FSC1 : stm32f10x.h
  • CAN_FS1R_FSC10 : stm32f10x.h
  • CAN_FS1R_FSC11 : stm32f10x.h
  • CAN_FS1R_FSC12 : stm32f10x.h
  • CAN_FS1R_FSC13 : stm32f10x.h
  • CAN_FS1R_FSC2 : stm32f10x.h
  • CAN_FS1R_FSC3 : stm32f10x.h
  • CAN_FS1R_FSC4 : stm32f10x.h
  • CAN_FS1R_FSC5 : stm32f10x.h
  • CAN_FS1R_FSC6 : stm32f10x.h
  • CAN_FS1R_FSC7 : stm32f10x.h
  • CAN_FS1R_FSC8 : stm32f10x.h
  • CAN_FS1R_FSC9 : stm32f10x.h
  • CAN_ID_EXT : stm32f10x_can.h
  • CAN_Id_Extended : stm32f10x_can.h
  • CAN_Id_Standard : stm32f10x_can.h
  • CAN_ID_STD : stm32f10x_can.h
  • CAN_IER_BOFIE : stm32f10x.h
  • CAN_IER_EPVIE : stm32f10x.h
  • CAN_IER_ERRIE : stm32f10x.h
  • CAN_IER_EWGIE : stm32f10x.h
  • CAN_IER_FFIE0 : stm32f10x.h
  • CAN_IER_FFIE1 : stm32f10x.h
  • CAN_IER_FMPIE0 : stm32f10x.h
  • CAN_IER_FMPIE1 : stm32f10x.h
  • CAN_IER_FOVIE0 : stm32f10x.h
  • CAN_IER_FOVIE1 : stm32f10x.h
  • CAN_IER_LECIE : stm32f10x.h
  • CAN_IER_SLKIE : stm32f10x.h
  • CAN_IER_TMEIE : stm32f10x.h
  • CAN_IER_WKUIE : stm32f10x.h
  • CAN_InitStatus_Failed : stm32f10x_can.h
  • CAN_InitStatus_Success : stm32f10x_can.h
  • CAN_IT_BOF : stm32f10x_can.h
  • CAN_IT_EPV : stm32f10x_can.h
  • CAN_IT_ERR : stm32f10x_can.h
  • CAN_IT_EWG : stm32f10x_can.h
  • CAN_IT_FF0 : stm32f10x_can.h
  • CAN_IT_FF1 : stm32f10x_can.h
  • CAN_IT_FMP0 : stm32f10x_can.h
  • CAN_IT_FMP1 : stm32f10x_can.h
  • CAN_IT_FOV0 : stm32f10x_can.h
  • CAN_IT_FOV1 : stm32f10x_can.h
  • CAN_IT_LEC : stm32f10x_can.h
  • CAN_IT_RQCP0 : stm32f10x_can.h
  • CAN_IT_RQCP1 : stm32f10x_can.h
  • CAN_IT_RQCP2 : stm32f10x_can.h
  • CAN_IT_SLK : stm32f10x_can.h
  • CAN_IT_TME : stm32f10x_can.h
  • CAN_IT_WKU : stm32f10x_can.h
  • CAN_MCR_ABOM : stm32f10x.h
  • CAN_MCR_AWUM : stm32f10x.h
  • CAN_MCR_INRQ : stm32f10x.h
  • CAN_MCR_NART : stm32f10x.h
  • CAN_MCR_RESET : stm32f10x.h
  • CAN_MCR_RFLM : stm32f10x.h
  • CAN_MCR_SLEEP : stm32f10x.h
  • CAN_MCR_TTCM : stm32f10x.h
  • CAN_MCR_TXFP : stm32f10x.h
  • CAN_Mode_LoopBack : stm32f10x_can.h
  • CAN_MODE_MASK : stm32f10x_can.c
  • CAN_Mode_Normal : stm32f10x_can.h
  • CAN_Mode_Silent : stm32f10x_can.h
  • CAN_Mode_Silent_LoopBack : stm32f10x_can.h
  • CAN_ModeStatus_Failed : stm32f10x_can.h
  • CAN_ModeStatus_Success : stm32f10x_can.h
  • CAN_MSR_ERRI : stm32f10x.h
  • CAN_MSR_INAK : stm32f10x.h
  • CAN_MSR_RX : stm32f10x.h
  • CAN_MSR_RXM : stm32f10x.h
  • CAN_MSR_SAMP : stm32f10x.h
  • CAN_MSR_SLAK : stm32f10x.h
  • CAN_MSR_SLAKI : stm32f10x.h
  • CAN_MSR_TXM : stm32f10x.h
  • CAN_MSR_WKUI : stm32f10x.h
  • CAN_NO_MB : stm32f10x_can.h
  • CAN_OperatingMode_Initialization : stm32f10x_can.h
  • CAN_OperatingMode_Normal : stm32f10x_can.h
  • CAN_OperatingMode_Sleep : stm32f10x_can.h
  • CAN_RDH0R_DATA4 : stm32f10x.h
  • CAN_RDH0R_DATA5 : stm32f10x.h
  • CAN_RDH0R_DATA6 : stm32f10x.h
  • CAN_RDH0R_DATA7 : stm32f10x.h
  • CAN_RDH1R_DATA4 : stm32f10x.h
  • CAN_RDH1R_DATA5 : stm32f10x.h
  • CAN_RDH1R_DATA6 : stm32f10x.h
  • CAN_RDH1R_DATA7 : stm32f10x.h
  • CAN_RDL0R_DATA0 : stm32f10x.h
  • CAN_RDL0R_DATA1 : stm32f10x.h
  • CAN_RDL0R_DATA2 : stm32f10x.h
  • CAN_RDL0R_DATA3 : stm32f10x.h
  • CAN_RDL1R_DATA0 : stm32f10x.h
  • CAN_RDL1R_DATA1 : stm32f10x.h
  • CAN_RDL1R_DATA2 : stm32f10x.h
  • CAN_RDL1R_DATA3 : stm32f10x.h
  • CAN_RDT0R_DLC : stm32f10x.h
  • CAN_RDT0R_FMI : stm32f10x.h
  • CAN_RDT0R_TIME : stm32f10x.h
  • CAN_RDT1R_DLC : stm32f10x.h
  • CAN_RDT1R_FMI : stm32f10x.h
  • CAN_RDT1R_TIME : stm32f10x.h
  • CAN_RF0R_FMP0 : stm32f10x.h
  • CAN_RF0R_FOVR0 : stm32f10x.h
  • CAN_RF0R_FULL0 : stm32f10x.h
  • CAN_RF0R_RFOM0 : stm32f10x.h
  • CAN_RF1R_FMP1 : stm32f10x.h
  • CAN_RF1R_FOVR1 : stm32f10x.h
  • CAN_RF1R_FULL1 : stm32f10x.h
  • CAN_RF1R_RFOM1 : stm32f10x.h
  • CAN_RI0R_EXID : stm32f10x.h
  • CAN_RI0R_IDE : stm32f10x.h
  • CAN_RI0R_RTR : stm32f10x.h
  • CAN_RI0R_STID : stm32f10x.h
  • CAN_RI1R_EXID : stm32f10x.h
  • CAN_RI1R_IDE : stm32f10x.h
  • CAN_RI1R_RTR : stm32f10x.h
  • CAN_RI1R_STID : stm32f10x.h
  • CAN_RTR_Data : stm32f10x_can.h
  • CAN_RTR_DATA : stm32f10x_can.h
  • CAN_RTR_Remote : stm32f10x_can.h
  • CAN_RTR_REMOTE : stm32f10x_can.h
  • CAN_SJW_1tq : stm32f10x_can.h
  • CAN_SJW_2tq : stm32f10x_can.h
  • CAN_SJW_3tq : stm32f10x_can.h
  • CAN_SJW_4tq : stm32f10x_can.h
  • CAN_Sleep_Failed : stm32f10x_can.h
  • CAN_Sleep_Ok : stm32f10x_can.h
  • CAN_TDH0R_DATA4 : stm32f10x.h
  • CAN_TDH0R_DATA5 : stm32f10x.h
  • CAN_TDH0R_DATA6 : stm32f10x.h
  • CAN_TDH0R_DATA7 : stm32f10x.h
  • CAN_TDH1R_DATA4 : stm32f10x.h
  • CAN_TDH1R_DATA5 : stm32f10x.h
  • CAN_TDH1R_DATA6 : stm32f10x.h
  • CAN_TDH1R_DATA7 : stm32f10x.h
  • CAN_TDH2R_DATA4 : stm32f10x.h
  • CAN_TDH2R_DATA5 : stm32f10x.h
  • CAN_TDH2R_DATA6 : stm32f10x.h
  • CAN_TDH2R_DATA7 : stm32f10x.h
  • CAN_TDL0R_DATA0 : stm32f10x.h
  • CAN_TDL0R_DATA1 : stm32f10x.h
  • CAN_TDL0R_DATA2 : stm32f10x.h
  • CAN_TDL0R_DATA3 : stm32f10x.h
  • CAN_TDL1R_DATA0 : stm32f10x.h
  • CAN_TDL1R_DATA1 : stm32f10x.h
  • CAN_TDL1R_DATA2 : stm32f10x.h
  • CAN_TDL1R_DATA3 : stm32f10x.h
  • CAN_TDL2R_DATA0 : stm32f10x.h
  • CAN_TDL2R_DATA1 : stm32f10x.h
  • CAN_TDL2R_DATA2 : stm32f10x.h
  • CAN_TDL2R_DATA3 : stm32f10x.h
  • CAN_TDT0R_DLC : stm32f10x.h
  • CAN_TDT0R_TGT : stm32f10x.h
  • CAN_TDT0R_TIME : stm32f10x.h
  • CAN_TDT1R_DLC : stm32f10x.h
  • CAN_TDT1R_TGT : stm32f10x.h
  • CAN_TDT1R_TIME : stm32f10x.h
  • CAN_TDT2R_DLC : stm32f10x.h
  • CAN_TDT2R_TGT : stm32f10x.h
  • CAN_TDT2R_TIME : stm32f10x.h
  • CAN_TI0R_EXID : stm32f10x.h
  • CAN_TI0R_IDE : stm32f10x.h
  • CAN_TI0R_RTR : stm32f10x.h
  • CAN_TI0R_STID : stm32f10x.h
  • CAN_TI0R_TXRQ : stm32f10x.h
  • CAN_TI1R_EXID : stm32f10x.h
  • CAN_TI1R_IDE : stm32f10x.h
  • CAN_TI1R_RTR : stm32f10x.h
  • CAN_TI1R_STID : stm32f10x.h
  • CAN_TI1R_TXRQ : stm32f10x.h
  • CAN_TI2R_EXID : stm32f10x.h
  • CAN_TI2R_IDE : stm32f10x.h
  • CAN_TI2R_RTR : stm32f10x.h
  • CAN_TI2R_STID : stm32f10x.h
  • CAN_TI2R_TXRQ : stm32f10x.h
  • CAN_TSR_ABRQ0 : stm32f10x.h
  • CAN_TSR_ABRQ1 : stm32f10x.h
  • CAN_TSR_ABRQ2 : stm32f10x.h
  • CAN_TSR_ALST0 : stm32f10x.h
  • CAN_TSR_ALST1 : stm32f10x.h
  • CAN_TSR_ALST2 : stm32f10x.h
  • CAN_TSR_CODE : stm32f10x.h
  • CAN_TSR_LOW : stm32f10x.h
  • CAN_TSR_LOW0 : stm32f10x.h
  • CAN_TSR_LOW1 : stm32f10x.h
  • CAN_TSR_LOW2 : stm32f10x.h
  • CAN_TSR_RQCP0 : stm32f10x.h
  • CAN_TSR_RQCP1 : stm32f10x.h
  • CAN_TSR_RQCP2 : stm32f10x.h
  • CAN_TSR_TERR0 : stm32f10x.h
  • CAN_TSR_TERR1 : stm32f10x.h
  • CAN_TSR_TERR2 : stm32f10x.h
  • CAN_TSR_TME : stm32f10x.h
  • CAN_TSR_TME0 : stm32f10x.h
  • CAN_TSR_TME1 : stm32f10x.h
  • CAN_TSR_TME2 : stm32f10x.h
  • CAN_TSR_TXOK0 : stm32f10x.h
  • CAN_TSR_TXOK1 : stm32f10x.h
  • CAN_TSR_TXOK2 : stm32f10x.h
  • CAN_TXMAILBOX_0 : stm32f10x_can.c
  • CAN_TXMAILBOX_1 : stm32f10x_can.c
  • CAN_TXMAILBOX_2 : stm32f10x_can.c
  • CAN_TxStatus_Failed : stm32f10x_can.h
  • CAN_TxStatus_NoMailBox : stm32f10x_can.h
  • CAN_TxStatus_Ok : stm32f10x_can.h
  • CAN_TxStatus_Pending : stm32f10x_can.h
  • CAN_WakeUp_Failed : stm32f10x_can.h
  • CAN_WakeUp_Ok : stm32f10x_can.h
  • CANINITFAILED : stm32f10x_can.h
  • CANINITOK : stm32f10x_can.h
  • CANSLEEPFAILED : stm32f10x_can.h
  • CANSLEEPOK : stm32f10x_can.h
  • CANTXFAILE : stm32f10x_can.h
  • CANTXOK : stm32f10x_can.h
  • CANTXPENDING : stm32f10x_can.h
  • CANWAKEUPFAILED : stm32f10x_can.h
  • CANWAKEUPOK : stm32f10x_can.h
  • CANx : STM32F10x_StdPeriph_Examples/CAN/Networking/main.c , STM32F10x_StdPeriph_Examples/CAN/LoopBack/main.c
  • CCER_CCE_Set : stm32f10x_tim.c
  • CCER_CCNE_Set : stm32f10x_tim.c
  • CCMR_Offset : stm32f10x_tim.c
  • CCR_CCR_Set : stm32f10x_i2c.c
  • CCR_CLEAR_Mask : stm32f10x_dma.c
  • CCR_FS_Set : stm32f10x_i2c.c
  • CEC : stm32f10x.h
  • CEC_BASE : stm32f10x.h
  • CEC_BitPeriodFlexibleMode : stm32f10x_cec.h
  • CEC_BitPeriodStdMode : stm32f10x_cec.h
  • CEC_BitTimingErrFreeMode : stm32f10x_cec.h
  • CEC_BitTimingStdMode : stm32f10x_cec.h
  • CEC_CFGR_BPEM : stm32f10x.h
  • CEC_CFGR_BTEM : stm32f10x.h
  • CEC_CFGR_IE : stm32f10x.h
  • CEC_CFGR_PE : stm32f10x.h
  • CEC_CSR_RBTF : stm32f10x.h
  • CEC_CSR_REOM : stm32f10x.h
  • CEC_CSR_RERR : stm32f10x.h
  • CEC_CSR_RSOM : stm32f10x.h
  • CEC_CSR_TBTRF : stm32f10x.h
  • CEC_CSR_TEOM : stm32f10x.h
  • CEC_CSR_TERR : stm32f10x.h
  • CEC_CSR_TSOM : stm32f10x.h
  • CEC_DEVICE1 : STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_conf.h
  • CEC_ESR_ACKE : stm32f10x.h
  • CEC_ESR_BPE : stm32f10x.h
  • CEC_ESR_BTE : stm32f10x.h
  • CEC_ESR_LINE : stm32f10x.h
  • CEC_ESR_RBTFE : stm32f10x.h
  • CEC_ESR_SBE : stm32f10x.h
  • CEC_ESR_TBTFE : stm32f10x.h
  • CEC_FLAG_ACKE : stm32f10x_cec.h
  • CEC_FLAG_BPE : stm32f10x_cec.h
  • CEC_FLAG_BTE : stm32f10x_cec.h
  • CEC_FLAG_LINE : stm32f10x_cec.h
  • CEC_FLAG_RBTF : stm32f10x_cec.h
  • CEC_FLAG_RBTFE : stm32f10x_cec.h
  • CEC_FLAG_REOM : stm32f10x_cec.h
  • CEC_FLAG_RERR : stm32f10x_cec.h
  • CEC_FLAG_RSOM : stm32f10x_cec.h
  • CEC_FLAG_SBE : stm32f10x_cec.h
  • CEC_FLAG_TBTFE : stm32f10x_cec.h
  • CEC_FLAG_TBTRF : stm32f10x_cec.h
  • CEC_FLAG_TEOM : stm32f10x_cec.h
  • CEC_FLAG_TERR : stm32f10x_cec.h
  • CEC_IT_RBTF : stm32f10x_cec.h
  • CEC_IT_RERR : stm32f10x_cec.h
  • CEC_IT_TBTRF : stm32f10x_cec.h
  • CEC_IT_TERR : stm32f10x_cec.h
  • CEC_OAR_OA : stm32f10x.h
  • CEC_OAR_OA_0 : stm32f10x.h
  • CEC_OAR_OA_1 : stm32f10x.h
  • CEC_OAR_OA_2 : stm32f10x.h
  • CEC_OAR_OA_3 : stm32f10x.h
  • CEC_OFFSET : stm32f10x_cec.c
  • CEC_PRES_PRES : stm32f10x.h
  • CEC_RXD_RXD : stm32f10x.h
  • CEC_TXD_TXD : stm32f10x.h
  • CFGR_ADCPRE_Reset_Mask : stm32f10x_rcc.c
  • CFGR_ADCPRE_Set_Mask : stm32f10x_rcc.c
  • CFGR_BYTE4_ADDRESS : stm32f10x_rcc.c
  • CFGR_CLEAR_Mask : stm32f10x_cec.c
  • CFGR_HPRE_Reset_Mask : stm32f10x_rcc.c
  • CFGR_HPRE_Set_Mask : stm32f10x_rcc.c
  • CFGR_IE_BB : stm32f10x_cec.c
  • CFGR_OFFSET : stm32f10x_cec.c , stm32f10x_rcc.c
  • CFGR_PE_BB : stm32f10x_cec.c
  • CFGR_PLL_Mask : stm32f10x_rcc.c
  • CFGR_PLLMull_Mask : stm32f10x_rcc.c
  • CFGR_PLLSRC_Mask : stm32f10x_rcc.c
  • CFGR_PLLXTPRE_Mask : stm32f10x_rcc.c
  • CFGR_PPRE1_Reset_Mask : stm32f10x_rcc.c
  • CFGR_PPRE1_Set_Mask : stm32f10x_rcc.c
  • CFGR_PPRE2_Reset_Mask : stm32f10x_rcc.c
  • CFGR_PPRE2_Set_Mask : stm32f10x_rcc.c
  • CFGR_SW_Mask : stm32f10x_rcc.c
  • CFGR_SWS_Mask : stm32f10x_rcc.c
  • CFGR_USBPRE_BB : stm32f10x_rcc.c
  • CFR_EWI_BB : stm32f10x_wwdg.c
  • CFR_OFFSET : stm32f10x_wwdg.c
  • CFR_W_Mask : stm32f10x_wwdg.c
  • CFR_WDGTB_Mask : stm32f10x_wwdg.c
  • ChipErase_Timeout : stm3210e_eval_fsmc_nor.c
  • CIR_BYTE2_ADDRESS : stm32f10x_rcc.c
  • CIR_BYTE3_ADDRESS : stm32f10x_rcc.c
  • CLEAR_BIT : stm32f10x.h
  • CLEAR_REG : stm32f10x.h
  • CLKCR_CLEAR_MASK : stm32f10x_sdio.c
  • CLKCR_CLKEN_BB : stm32f10x_sdio.c
  • CLKCR_OFFSET : stm32f10x_sdio.c
  • CLKEN_BitNumber : stm32f10x_sdio.c
  • ClockSpeed : STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/main.c
  • CMD_AREA : stm3210e_eval_fsmc_nand.h
  • CMD_ATACMD_BB : stm32f10x_sdio.c
  • CMD_CLEAR_MASK : stm32f10x_sdio.c
  • CMD_ENCMDCOMPL_BB : stm32f10x_sdio.c
  • CMD_NIEN_BB : stm32f10x_sdio.c
  • CMD_OFFSET : stm32f10x_sdio.c
  • CMD_SDIOSUSPEND_BB : stm32f10x_sdio.c
  • COMn : stm3210e_eval.h , stm32l152_eval.h , stm3210c_eval.h , stm3210b_eval.h , stm32100e_eval.h , stm32100b_eval.h
  • countof : STM32F10x_StdPeriph_Examples/I2C/EEPROM/main.c , STM32F10x_StdPeriph_Examples/USART/HalfDuplex/main.c , STM32F10x_StdPeriph_Examples/USART/Polling/main.c , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/main.c , STM32F10x_StdPeriph_Examples/USART/DMA_Polling/main.c , STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/main.c , STM32F10x_StdPeriph_Examples/USART/Synchronous/main.c , STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/main.c
  • CR1_ACK_Reset : stm32f10x_i2c.c
  • CR1_ACK_Set : stm32f10x_i2c.c
  • CR1_AWDCH_Reset : stm32f10x_adc.c
  • CR1_AWDMode_Reset : stm32f10x_adc.c
  • CR1_CLEAR_Mask : stm32f10x_usart.c , stm32f10x_spi.c , stm32f10x_i2c.c , stm32f10x_adc.c
  • CR1_CRCEN_Reset : stm32f10x_spi.c
  • CR1_CRCEN_Set : stm32f10x_spi.c
  • CR1_CRCNext_Set : stm32f10x_spi.c
  • CR1_DISCEN_Reset : stm32f10x_adc.c
  • CR1_DISCEN_Set : stm32f10x_adc.c
  • CR1_DISCNUM_Reset : stm32f10x_adc.c
  • CR1_ENARP_Reset : stm32f10x_i2c.c
  • CR1_ENARP_Set : stm32f10x_i2c.c
  • CR1_ENGC_Reset : stm32f10x_i2c.c
  • CR1_ENGC_Set : stm32f10x_i2c.c
  • CR1_ENPEC_Reset : stm32f10x_i2c.c
  • CR1_ENPEC_Set : stm32f10x_i2c.c
  • CR1_JAUTO_Reset : stm32f10x_adc.c
  • CR1_JAUTO_Set : stm32f10x_adc.c
  • CR1_JDISCEN_Reset : stm32f10x_adc.c
  • CR1_JDISCEN_Set : stm32f10x_adc.c
  • CR1_NOSTRETCH_Reset : stm32f10x_i2c.c
  • CR1_NOSTRETCH_Set : stm32f10x_i2c.c
  • CR1_OVER8_Reset : stm32f10x_usart.c
  • CR1_OVER8_Set : stm32f10x_usart.c
  • CR1_PE_Reset : stm32f10x_i2c.c
  • CR1_PE_Set : stm32f10x_i2c.c
  • CR1_PEC_Reset : stm32f10x_i2c.c
  • CR1_PEC_Set : stm32f10x_i2c.c
  • CR1_RWU_Reset : stm32f10x_usart.c
  • CR1_RWU_Set : stm32f10x_usart.c
  • CR1_SBK_Set : stm32f10x_usart.c
  • CR1_SPE_Reset : stm32f10x_spi.c
  • CR1_SPE_Set : stm32f10x_spi.c
  • CR1_START_Reset : stm32f10x_i2c.c
  • CR1_START_Set : stm32f10x_i2c.c
  • CR1_STOP_Reset : stm32f10x_i2c.c
  • CR1_STOP_Set : stm32f10x_i2c.c
  • CR1_SWRST_Reset : stm32f10x_i2c.c
  • CR1_SWRST_Set : stm32f10x_i2c.c
  • CR1_UE_Reset : stm32f10x_usart.c
  • CR1_UE_Set : stm32f10x_usart.c
  • CR1_WAKE_Mask : stm32f10x_usart.c
  • CR2_Address_Mask : stm32f10x_usart.c
  • CR2_ADON_Reset : stm32f10x_adc.c
  • CR2_ADON_Set : stm32f10x_adc.c
  • CR2_CAL_Set : stm32f10x_adc.c
  • CR2_CLEAR_Mask : stm32f10x_adc.c
  • CR2_CLOCK_CLEAR_Mask : stm32f10x_usart.c
  • CR2_DMA_Reset : stm32f10x_adc.c
  • CR2_DMA_Set : stm32f10x_adc.c
  • CR2_DMAEN_Reset : stm32f10x_i2c.c
  • CR2_DMAEN_Set : stm32f10x_i2c.c
  • CR2_EXTTRIG_Reset : stm32f10x_adc.c
  • CR2_EXTTRIG_Set : stm32f10x_adc.c
  • CR2_EXTTRIG_SWSTART_Reset : stm32f10x_adc.c
  • CR2_EXTTRIG_SWSTART_Set : stm32f10x_adc.c
  • CR2_FREQ_Reset : stm32f10x_i2c.c
  • CR2_JEXTSEL_Reset : stm32f10x_adc.c
  • CR2_JEXTTRIG_JSWSTART_Reset : stm32f10x_adc.c
  • CR2_JEXTTRIG_JSWSTART_Set : stm32f10x_adc.c
  • CR2_JEXTTRIG_Reset : stm32f10x_adc.c
  • CR2_JEXTTRIG_Set : stm32f10x_adc.c
  • CR2_JSWSTART_Set : stm32f10x_adc.c
  • CR2_LAST_Reset : stm32f10x_i2c.c
  • CR2_LAST_Set : stm32f10x_i2c.c
  • CR2_LBDL_Mask : stm32f10x_usart.c
  • CR2_LINEN_Reset : stm32f10x_usart.c
  • CR2_LINEN_Set : stm32f10x_usart.c
  • CR2_RSTCAL_Set : stm32f10x_adc.c
  • CR2_SSOE_Reset : stm32f10x_spi.c
  • CR2_SSOE_Set : stm32f10x_spi.c
  • CR2_STOP_CLEAR_Mask : stm32f10x_usart.c
  • CR2_SWSTART_Set : stm32f10x_adc.c
  • CR2_TSVREFE_Reset : stm32f10x_adc.c
  • CR2_TSVREFE_Set : stm32f10x_adc.c
  • CR3_CLEAR_Mask : stm32f10x_usart.c
  • CR3_HDSEL_Reset : stm32f10x_usart.c
  • CR3_HDSEL_Set : stm32f10x_usart.c
  • CR3_IREN_Reset : stm32f10x_usart.c
  • CR3_IREN_Set : stm32f10x_usart.c
  • CR3_IRLP_Mask : stm32f10x_usart.c
  • CR3_NACK_Reset : stm32f10x_usart.c
  • CR3_NACK_Set : stm32f10x_usart.c
  • CR3_ONEBITE_Reset : stm32f10x_usart.c
  • CR3_ONEBITE_Set : stm32f10x_usart.c
  • CR3_SCEN_Reset : stm32f10x_usart.c
  • CR3_SCEN_Set : stm32f10x_usart.c
  • CR_CLEAR_MASK : stm32f10x_dac.c
  • CR_CSSON_BB : stm32f10x_rcc.c
  • CR_DBP_BB : stm32f10x_pwr.c
  • CR_DS_MASK : stm32f10x_pwr.c
  • CR_HSEBYP_Reset : stm32f10x_rcc.c
  • CR_HSEBYP_Set : stm32f10x_rcc.c
  • CR_HSEON_Reset : stm32f10x_rcc.c
  • CR_HSEON_Set : stm32f10x_rcc.c
  • CR_HSION_BB : stm32f10x_rcc.c
  • CR_HSITRIM_Mask : stm32f10x_rcc.c
  • CR_LOCK_Set : stm32f10x_flash.c
  • CR_MER_Reset : stm32f10x_flash.c
  • CR_MER_Set : stm32f10x_flash.c
  • CR_OFFSET : stm32f10x_rcc.c , stm32f10x_bkp.c , stm32f10x_pwr.c
  • CR_OPTER_Reset : stm32f10x_flash.c
  • CR_OPTER_Set : stm32f10x_flash.c
  • CR_OPTPG_Reset : stm32f10x_flash.c
  • CR_OPTPG_Set : stm32f10x_flash.c
  • CR_PER_Reset : stm32f10x_flash.c
  • CR_PER_Set : stm32f10x_flash.c
  • CR_PG_Reset : stm32f10x_flash.c
  • CR_PG_Set : stm32f10x_flash.c
  • CR_PLLON_BB : stm32f10x_rcc.c
  • CR_PLS_MASK : stm32f10x_pwr.c
  • CR_PVDE_BB : stm32f10x_pwr.c
  • CR_STRT_Set : stm32f10x_flash.c
  • CR_TPAL_BB : stm32f10x_bkp.c
  • CR_TPE_BB : stm32f10x_bkp.c
  • CR_WDGA_Set : stm32f10x_wwdg.c
  • CRC : stm32f10x.h
  • CRC_BASE : stm32f10x.h
  • CRC_CR_RESET : stm32f10x.h
  • CRC_DR_DR : stm32f10x.h
  • CRC_IDR_IDR : stm32f10x.h
  • CRCPolynomial : STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/main.c
  • CSR_EWUP_BB : stm32f10x_pwr.c
  • CSR_LSION_BB : stm32f10x_rcc.c
  • CSR_OFFSET : stm32f10x_pwr.c , stm32f10x_rcc.c , stm32f10x_bkp.c , stm32f10x_cec.c
  • CSR_RMVF_Set : stm32f10x_rcc.c
  • CSR_TEF_BB : stm32f10x_bkp.c
  • CSR_TEOM_BB : stm32f10x_cec.c
  • CSR_TIF_BB : stm32f10x_bkp.c
  • CSR_TPIE_BB : stm32f10x_bkp.c
  • CSR_TSOM_BB : stm32f10x_cec.c
  • CSSON_BitNumber : stm32f10x_rcc.c
  • Cyan : stm32_eval.h


STM32F10x Standard Peripherals Firmware Library: Globals

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- d -

  • DAC : stm32f10x.h
  • DAC_Align_12b_L : stm32f10x_dac.h
  • DAC_Align_12b_R : stm32f10x_dac.h
  • DAC_Align_8b_R : stm32f10x_dac.h
  • DAC_BASE : stm32f10x.h
  • DAC_Channel_1 : stm32f10x_dac.h
  • DAC_Channel_2 : stm32f10x_dac.h
  • DAC_CR_BOFF1 : stm32f10x.h
  • DAC_CR_BOFF2 : stm32f10x.h
  • DAC_CR_DMAEN1 : stm32f10x.h
  • DAC_CR_DMAEN2 : stm32f10x.h
  • DAC_CR_EN1 : stm32f10x.h
  • DAC_CR_EN2 : stm32f10x.h
  • DAC_CR_MAMP1 : stm32f10x.h
  • DAC_CR_MAMP1_0 : stm32f10x.h
  • DAC_CR_MAMP1_1 : stm32f10x.h
  • DAC_CR_MAMP1_2 : stm32f10x.h
  • DAC_CR_MAMP1_3 : stm32f10x.h
  • DAC_CR_MAMP2 : stm32f10x.h
  • DAC_CR_MAMP2_0 : stm32f10x.h
  • DAC_CR_MAMP2_1 : stm32f10x.h
  • DAC_CR_MAMP2_2 : stm32f10x.h
  • DAC_CR_MAMP2_3 : stm32f10x.h
  • DAC_CR_TEN1 : stm32f10x.h
  • DAC_CR_TEN2 : stm32f10x.h
  • DAC_CR_TSEL1 : stm32f10x.h
  • DAC_CR_TSEL1_0 : stm32f10x.h
  • DAC_CR_TSEL1_1 : stm32f10x.h
  • DAC_CR_TSEL1_2 : stm32f10x.h
  • DAC_CR_TSEL2 : stm32f10x.h
  • DAC_CR_TSEL2_0 : stm32f10x.h
  • DAC_CR_TSEL2_1 : stm32f10x.h
  • DAC_CR_TSEL2_2 : stm32f10x.h
  • DAC_CR_WAVE1 : stm32f10x.h
  • DAC_CR_WAVE1_0 : stm32f10x.h
  • DAC_CR_WAVE1_1 : stm32f10x.h
  • DAC_CR_WAVE2 : stm32f10x.h
  • DAC_CR_WAVE2_0 : stm32f10x.h
  • DAC_CR_WAVE2_1 : stm32f10x.h
  • DAC_DHR12L1_DACC1DHR : stm32f10x.h
  • DAC_DHR12L2_DACC2DHR : stm32f10x.h
  • DAC_DHR12LD_DACC1DHR : stm32f10x.h
  • DAC_DHR12LD_DACC2DHR : stm32f10x.h
  • DAC_DHR12R1_DACC1DHR : stm32f10x.h
  • DAC_DHR12R2_DACC2DHR : stm32f10x.h
  • DAC_DHR12RD_Address : STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/main.c
  • DAC_DHR12RD_DACC1DHR : stm32f10x.h
  • DAC_DHR12RD_DACC2DHR : stm32f10x.h
  • DAC_DHR8R1_Address : STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/main.c
  • DAC_DHR8R1_DACC1DHR : stm32f10x.h
  • DAC_DHR8R2_DACC2DHR : stm32f10x.h
  • DAC_DHR8RD_DACC1DHR : stm32f10x.h
  • DAC_DHR8RD_DACC2DHR : stm32f10x.h
  • DAC_DOR1_DACC1DOR : stm32f10x.h
  • DAC_DOR2_DACC2DOR : stm32f10x.h
  • DAC_LFSRUnmask_Bit0 : stm32f10x_dac.h
  • DAC_LFSRUnmask_Bits10_0 : stm32f10x_dac.h
  • DAC_LFSRUnmask_Bits11_0 : stm32f10x_dac.h
  • DAC_LFSRUnmask_Bits1_0 : stm32f10x_dac.h
  • DAC_LFSRUnmask_Bits2_0 : stm32f10x_dac.h
  • DAC_LFSRUnmask_Bits3_0 : stm32f10x_dac.h
  • DAC_LFSRUnmask_Bits4_0 : stm32f10x_dac.h
  • DAC_LFSRUnmask_Bits5_0 : stm32f10x_dac.h
  • DAC_LFSRUnmask_Bits6_0 : stm32f10x_dac.h
  • DAC_LFSRUnmask_Bits7_0 : stm32f10x_dac.h
  • DAC_LFSRUnmask_Bits8_0 : stm32f10x_dac.h
  • DAC_LFSRUnmask_Bits9_0 : stm32f10x_dac.h
  • DAC_OutputBuffer_Disable : stm32f10x_dac.h
  • DAC_OutputBuffer_Enable : stm32f10x_dac.h
  • DAC_SR_DMAUDR1 : stm32f10x.h
  • DAC_SR_DMAUDR2 : stm32f10x.h
  • DAC_SWTRIGR_SWTRIG1 : stm32f10x.h
  • DAC_SWTRIGR_SWTRIG2 : stm32f10x.h
  • DAC_TriangleAmplitude_1 : stm32f10x_dac.h
  • DAC_TriangleAmplitude_1023 : stm32f10x_dac.h
  • DAC_TriangleAmplitude_127 : stm32f10x_dac.h
  • DAC_TriangleAmplitude_15 : stm32f10x_dac.h
  • DAC_TriangleAmplitude_2047 : stm32f10x_dac.h
  • DAC_TriangleAmplitude_255 : stm32f10x_dac.h
  • DAC_TriangleAmplitude_3 : stm32f10x_dac.h
  • DAC_TriangleAmplitude_31 : stm32f10x_dac.h
  • DAC_TriangleAmplitude_4095 : stm32f10x_dac.h
  • DAC_TriangleAmplitude_511 : stm32f10x_dac.h
  • DAC_TriangleAmplitude_63 : stm32f10x_dac.h
  • DAC_TriangleAmplitude_7 : stm32f10x_dac.h
  • DAC_Trigger_Ext_IT9 : stm32f10x_dac.h
  • DAC_Trigger_None : stm32f10x_dac.h
  • DAC_Trigger_Software : stm32f10x_dac.h
  • DAC_Trigger_T15_TRGO : stm32f10x_dac.h
  • DAC_Trigger_T2_TRGO : stm32f10x_dac.h
  • DAC_Trigger_T3_TRGO : stm32f10x_dac.h
  • DAC_Trigger_T4_TRGO : stm32f10x_dac.h
  • DAC_Trigger_T5_TRGO : stm32f10x_dac.h
  • DAC_Trigger_T6_TRGO : stm32f10x_dac.h
  • DAC_Trigger_T7_TRGO : stm32f10x_dac.h
  • DAC_Trigger_T8_TRGO : stm32f10x_dac.h
  • DAC_Wave_Noise : stm32f10x_dac.h
  • DAC_Wave_Triangle : stm32f10x_dac.h
  • DAC_WaveGeneration_Noise : stm32f10x_dac.h
  • DAC_WaveGeneration_None : stm32f10x_dac.h
  • DAC_WaveGeneration_Triangle : stm32f10x_dac.h
  • DATA_AREA : stm3210e_eval_fsmc_nand.h
  • DBGAFR_LOCATION_MASK : stm32f10x_gpio.c
  • DBGAFR_NUMBITS_MASK : stm32f10x_gpio.c
  • DBGAFR_POSITION_MASK : stm32f10x_gpio.c
  • DBGAFR_SWJCFG_MASK : stm32f10x_gpio.c
  • DBGMCU : stm32f10x.h
  • DBGMCU_BASE : stm32f10x.h
  • DBGMCU_CAN1_STOP : stm32f10x_dbgmcu.h
  • DBGMCU_CAN2_STOP : stm32f10x_dbgmcu.h
  • DBGMCU_CR_DBG_CAN1_STOP : stm32f10x.h
  • DBGMCU_CR_DBG_CAN2_STOP : stm32f10x.h
  • DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT : stm32f10x.h
  • DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT : stm32f10x.h
  • DBGMCU_CR_DBG_IWDG_STOP : stm32f10x.h
  • DBGMCU_CR_DBG_SLEEP : stm32f10x.h
  • DBGMCU_CR_DBG_STANDBY : stm32f10x.h
  • DBGMCU_CR_DBG_STOP : stm32f10x.h
  • DBGMCU_CR_DBG_TIM10_STOP : stm32f10x.h
  • DBGMCU_CR_DBG_TIM11_STOP : stm32f10x.h
  • DBGMCU_CR_DBG_TIM12_STOP : stm32f10x.h
  • DBGMCU_CR_DBG_TIM13_STOP : stm32f10x.h
  • DBGMCU_CR_DBG_TIM14_STOP : stm32f10x.h
  • DBGMCU_CR_DBG_TIM15_STOP : stm32f10x.h
  • DBGMCU_CR_DBG_TIM16_STOP : stm32f10x.h
  • DBGMCU_CR_DBG_TIM17_STOP : stm32f10x.h
  • DBGMCU_CR_DBG_TIM1_STOP : stm32f10x.h
  • DBGMCU_CR_DBG_TIM2_STOP : stm32f10x.h
  • DBGMCU_CR_DBG_TIM3_STOP : stm32f10x.h
  • DBGMCU_CR_DBG_TIM4_STOP : stm32f10x.h
  • DBGMCU_CR_DBG_TIM5_STOP : stm32f10x.h
  • DBGMCU_CR_DBG_TIM6_STOP : stm32f10x.h
  • DBGMCU_CR_DBG_TIM7_STOP : stm32f10x.h
  • DBGMCU_CR_DBG_TIM8_STOP : stm32f10x.h
  • DBGMCU_CR_DBG_TIM9_STOP : stm32f10x.h
  • DBGMCU_CR_DBG_WWDG_STOP : stm32f10x.h
  • DBGMCU_CR_TRACE_IOEN : stm32f10x.h
  • DBGMCU_CR_TRACE_MODE : stm32f10x.h
  • DBGMCU_CR_TRACE_MODE_0 : stm32f10x.h
  • DBGMCU_CR_TRACE_MODE_1 : stm32f10x.h
  • DBGMCU_I2C1_SMBUS_TIMEOUT : stm32f10x_dbgmcu.h
  • DBGMCU_I2C2_SMBUS_TIMEOUT : stm32f10x_dbgmcu.h
  • DBGMCU_IDCODE_DEV_ID : stm32f10x.h
  • DBGMCU_IDCODE_REV_ID : stm32f10x.h
  • DBGMCU_IDCODE_REV_ID_0 : stm32f10x.h
  • DBGMCU_IDCODE_REV_ID_1 : stm32f10x.h
  • DBGMCU_IDCODE_REV_ID_10 : stm32f10x.h
  • DBGMCU_IDCODE_REV_ID_11 : stm32f10x.h
  • DBGMCU_IDCODE_REV_ID_12 : stm32f10x.h
  • DBGMCU_IDCODE_REV_ID_13 : stm32f10x.h
  • DBGMCU_IDCODE_REV_ID_14 : stm32f10x.h
  • DBGMCU_IDCODE_REV_ID_15 : stm32f10x.h
  • DBGMCU_IDCODE_REV_ID_2 : stm32f10x.h
  • DBGMCU_IDCODE_REV_ID_3 : stm32f10x.h
  • DBGMCU_IDCODE_REV_ID_4 : stm32f10x.h
  • DBGMCU_IDCODE_REV_ID_5 : stm32f10x.h
  • DBGMCU_IDCODE_REV_ID_6 : stm32f10x.h
  • DBGMCU_IDCODE_REV_ID_7 : stm32f10x.h
  • DBGMCU_IDCODE_REV_ID_8 : stm32f10x.h
  • DBGMCU_IDCODE_REV_ID_9 : stm32f10x.h
  • DBGMCU_IWDG_STOP : stm32f10x_dbgmcu.h
  • DBGMCU_SLEEP : stm32f10x_dbgmcu.h
  • DBGMCU_STANDBY : stm32f10x_dbgmcu.h
  • DBGMCU_STOP : stm32f10x_dbgmcu.h
  • DBGMCU_TIM10_STOP : stm32f10x_dbgmcu.h
  • DBGMCU_TIM11_STOP : stm32f10x_dbgmcu.h
  • DBGMCU_TIM12_STOP : stm32f10x_dbgmcu.h
  • DBGMCU_TIM13_STOP : stm32f10x_dbgmcu.h
  • DBGMCU_TIM14_STOP : stm32f10x_dbgmcu.h
  • DBGMCU_TIM15_STOP : stm32f10x_dbgmcu.h
  • DBGMCU_TIM16_STOP : stm32f10x_dbgmcu.h
  • DBGMCU_TIM17_STOP : stm32f10x_dbgmcu.h
  • DBGMCU_TIM1_STOP : stm32f10x_dbgmcu.h
  • DBGMCU_TIM2_STOP : stm32f10x_dbgmcu.h
  • DBGMCU_TIM3_STOP : stm32f10x_dbgmcu.h
  • DBGMCU_TIM4_STOP : stm32f10x_dbgmcu.h
  • DBGMCU_TIM5_STOP : stm32f10x_dbgmcu.h
  • DBGMCU_TIM6_STOP : stm32f10x_dbgmcu.h
  • DBGMCU_TIM7_STOP : stm32f10x_dbgmcu.h
  • DBGMCU_TIM8_STOP : stm32f10x_dbgmcu.h
  • DBGMCU_TIM9_STOP : stm32f10x_dbgmcu.h
  • DBGMCU_WWDG_STOP : stm32f10x_dbgmcu.h
  • DBP_BitNumber : stm32f10x_pwr.c
  • DCTRL_CLEAR_MASK : stm32f10x_sdio.c
  • DCTRL_DMAEN_BB : stm32f10x_sdio.c
  • DCTRL_OFFSET : stm32f10x_sdio.c
  • DCTRL_RWMOD_BB : stm32f10x_sdio.c
  • DCTRL_RWSTART_BB : stm32f10x_sdio.c
  • DCTRL_RWSTOP_BB : stm32f10x_sdio.c
  • DCTRL_SDIOEN_BB : stm32f10x_sdio.c
  • DELAY_COUNT : STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/main.c
  • DHR12R1_OFFSET : stm32f10x_dac.c
  • DHR12R2_OFFSET : stm32f10x_dac.c
  • DHR12RD_OFFSET : stm32f10x_dac.c
  • Direction_IN : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • Direction_OUT : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • DMA1 : stm32f10x.h
  • DMA1_BASE : stm32f10x.h
  • DMA1_Channel1 : stm32f10x.h
  • DMA1_Channel1_BASE : stm32f10x.h
  • DMA1_Channel1_IT_Mask : stm32f10x_dma.c
  • DMA1_Channel2 : stm32f10x.h
  • DMA1_Channel2_BASE : stm32f10x.h
  • DMA1_Channel2_IT_Mask : stm32f10x_dma.c
  • DMA1_Channel3 : stm32f10x.h
  • DMA1_Channel3_BASE : stm32f10x.h
  • DMA1_Channel3_IT_Mask : stm32f10x_dma.c
  • DMA1_Channel4 : stm32f10x.h
  • DMA1_Channel4_BASE : stm32f10x.h
  • DMA1_Channel4_IT_Mask : stm32f10x_dma.c
  • DMA1_Channel5 : stm32f10x.h
  • DMA1_Channel5_BASE : stm32f10x.h
  • DMA1_Channel5_IT_Mask : stm32f10x_dma.c
  • DMA1_Channel6 : stm32f10x.h
  • DMA1_Channel6_BASE : stm32f10x.h
  • DMA1_Channel6_IT_Mask : stm32f10x_dma.c
  • DMA1_Channel7 : stm32f10x.h
  • DMA1_Channel7_BASE : stm32f10x.h
  • DMA1_Channel7_IT_Mask : stm32f10x_dma.c
  • DMA1_FLAG_GL1 : stm32f10x_dma.h
  • DMA1_FLAG_GL2 : stm32f10x_dma.h
  • DMA1_FLAG_GL3 : stm32f10x_dma.h
  • DMA1_FLAG_GL4 : stm32f10x_dma.h
  • DMA1_FLAG_GL5 : stm32f10x_dma.h
  • DMA1_FLAG_GL6 : stm32f10x_dma.h
  • DMA1_FLAG_GL7 : stm32f10x_dma.h
  • DMA1_FLAG_HT1 : stm32f10x_dma.h
  • DMA1_FLAG_HT2 : stm32f10x_dma.h
  • DMA1_FLAG_HT3 : stm32f10x_dma.h
  • DMA1_FLAG_HT4 : stm32f10x_dma.h
  • DMA1_FLAG_HT5 : stm32f10x_dma.h
  • DMA1_FLAG_HT6 : stm32f10x_dma.h
  • DMA1_FLAG_HT7 : stm32f10x_dma.h
  • DMA1_FLAG_TC1 : stm32f10x_dma.h
  • DMA1_FLAG_TC2 : stm32f10x_dma.h
  • DMA1_FLAG_TC3 : stm32f10x_dma.h
  • DMA1_FLAG_TC4 : stm32f10x_dma.h
  • DMA1_FLAG_TC5 : stm32f10x_dma.h
  • DMA1_FLAG_TC6 : stm32f10x_dma.h
  • DMA1_FLAG_TC7 : stm32f10x_dma.h
  • DMA1_FLAG_TE1 : stm32f10x_dma.h
  • DMA1_FLAG_TE2 : stm32f10x_dma.h
  • DMA1_FLAG_TE3 : stm32f10x_dma.h
  • DMA1_FLAG_TE4 : stm32f10x_dma.h
  • DMA1_FLAG_TE5 : stm32f10x_dma.h
  • DMA1_FLAG_TE6 : stm32f10x_dma.h
  • DMA1_FLAG_TE7 : stm32f10x_dma.h
  • DMA1_IT_GL1 : stm32f10x_dma.h
  • DMA1_IT_GL2 : stm32f10x_dma.h
  • DMA1_IT_GL3 : stm32f10x_dma.h
  • DMA1_IT_GL4 : stm32f10x_dma.h
  • DMA1_IT_GL5 : stm32f10x_dma.h
  • DMA1_IT_GL6 : stm32f10x_dma.h
  • DMA1_IT_GL7 : stm32f10x_dma.h
  • DMA1_IT_HT1 : stm32f10x_dma.h
  • DMA1_IT_HT2 : stm32f10x_dma.h
  • DMA1_IT_HT3 : stm32f10x_dma.h
  • DMA1_IT_HT4 : stm32f10x_dma.h
  • DMA1_IT_HT5 : stm32f10x_dma.h
  • DMA1_IT_HT6 : stm32f10x_dma.h
  • DMA1_IT_HT7 : stm32f10x_dma.h
  • DMA1_IT_TC1 : stm32f10x_dma.h
  • DMA1_IT_TC2 : stm32f10x_dma.h
  • DMA1_IT_TC3 : stm32f10x_dma.h
  • DMA1_IT_TC4 : stm32f10x_dma.h
  • DMA1_IT_TC5 : stm32f10x_dma.h
  • DMA1_IT_TC6 : stm32f10x_dma.h
  • DMA1_IT_TC7 : stm32f10x_dma.h
  • DMA1_IT_TE1 : stm32f10x_dma.h
  • DMA1_IT_TE2 : stm32f10x_dma.h
  • DMA1_IT_TE3 : stm32f10x_dma.h
  • DMA1_IT_TE4 : stm32f10x_dma.h
  • DMA1_IT_TE5 : stm32f10x_dma.h
  • DMA1_IT_TE6 : stm32f10x_dma.h
  • DMA1_IT_TE7 : stm32f10x_dma.h
  • DMA2 : stm32f10x.h
  • DMA2_BASE : stm32f10x.h
  • DMA2_Channel1 : stm32f10x.h
  • DMA2_Channel1_BASE : stm32f10x.h
  • DMA2_Channel1_IT_Mask : stm32f10x_dma.c
  • DMA2_Channel2 : stm32f10x.h
  • DMA2_Channel2_BASE : stm32f10x.h
  • DMA2_Channel2_IT_Mask : stm32f10x_dma.c
  • DMA2_Channel3 : stm32f10x.h
  • DMA2_Channel3_BASE : stm32f10x.h
  • DMA2_Channel3_IT_Mask : stm32f10x_dma.c
  • DMA2_Channel4 : stm32f10x.h
  • DMA2_Channel4_BASE : stm32f10x.h
  • DMA2_Channel4_IT_Mask : stm32f10x_dma.c
  • DMA2_Channel5 : stm32f10x.h
  • DMA2_Channel5_BASE : stm32f10x.h
  • DMA2_Channel5_IT_Mask : stm32f10x_dma.c
  • DMA2_FLAG_GL1 : stm32f10x_dma.h
  • DMA2_FLAG_GL2 : stm32f10x_dma.h
  • DMA2_FLAG_GL3 : stm32f10x_dma.h
  • DMA2_FLAG_GL4 : stm32f10x_dma.h
  • DMA2_FLAG_GL5 : stm32f10x_dma.h
  • DMA2_FLAG_HT1 : stm32f10x_dma.h
  • DMA2_FLAG_HT2 : stm32f10x_dma.h
  • DMA2_FLAG_HT3 : stm32f10x_dma.h
  • DMA2_FLAG_HT4 : stm32f10x_dma.h
  • DMA2_FLAG_HT5 : stm32f10x_dma.h
  • DMA2_FLAG_TC1 : stm32f10x_dma.h
  • DMA2_FLAG_TC2 : stm32f10x_dma.h
  • DMA2_FLAG_TC3 : stm32f10x_dma.h
  • DMA2_FLAG_TC4 : stm32f10x_dma.h
  • DMA2_FLAG_TC5 : stm32f10x_dma.h
  • DMA2_FLAG_TE1 : stm32f10x_dma.h
  • DMA2_FLAG_TE2 : stm32f10x_dma.h
  • DMA2_FLAG_TE3 : stm32f10x_dma.h
  • DMA2_FLAG_TE4 : stm32f10x_dma.h
  • DMA2_FLAG_TE5 : stm32f10x_dma.h
  • DMA2_IT_GL1 : stm32f10x_dma.h
  • DMA2_IT_GL2 : stm32f10x_dma.h
  • DMA2_IT_GL3 : stm32f10x_dma.h
  • DMA2_IT_GL4 : stm32f10x_dma.h
  • DMA2_IT_GL5 : stm32f10x_dma.h
  • DMA2_IT_HT1 : stm32f10x_dma.h
  • DMA2_IT_HT2 : stm32f10x_dma.h
  • DMA2_IT_HT3 : stm32f10x_dma.h
  • DMA2_IT_HT4 : stm32f10x_dma.h
  • DMA2_IT_HT5 : stm32f10x_dma.h
  • DMA2_IT_TC1 : stm32f10x_dma.h
  • DMA2_IT_TC2 : stm32f10x_dma.h
  • DMA2_IT_TC3 : stm32f10x_dma.h
  • DMA2_IT_TC4 : stm32f10x_dma.h
  • DMA2_IT_TC5 : stm32f10x_dma.h
  • DMA2_IT_TE1 : stm32f10x_dma.h
  • DMA2_IT_TE2 : stm32f10x_dma.h
  • DMA2_IT_TE3 : stm32f10x_dma.h
  • DMA2_IT_TE4 : stm32f10x_dma.h
  • DMA2_IT_TE5 : stm32f10x_dma.h
  • DMA_CCR1_CIRC : stm32f10x.h
  • DMA_CCR1_DIR : stm32f10x.h
  • DMA_CCR1_EN : stm32f10x.h
  • DMA_CCR1_HTIE : stm32f10x.h
  • DMA_CCR1_MEM2MEM : stm32f10x.h
  • DMA_CCR1_MINC : stm32f10x.h
  • DMA_CCR1_MSIZE : stm32f10x.h
  • DMA_CCR1_MSIZE_0 : stm32f10x.h
  • DMA_CCR1_MSIZE_1 : stm32f10x.h
  • DMA_CCR1_PINC : stm32f10x.h
  • DMA_CCR1_PL : stm32f10x.h
  • DMA_CCR1_PL_0 : stm32f10x.h
  • DMA_CCR1_PL_1 : stm32f10x.h
  • DMA_CCR1_PSIZE : stm32f10x.h
  • DMA_CCR1_PSIZE_0 : stm32f10x.h
  • DMA_CCR1_PSIZE_1 : stm32f10x.h
  • DMA_CCR1_TCIE : stm32f10x.h
  • DMA_CCR1_TEIE : stm32f10x.h
  • DMA_CCR2_CIRC : stm32f10x.h
  • DMA_CCR2_DIR : stm32f10x.h
  • DMA_CCR2_EN : stm32f10x.h
  • DMA_CCR2_HTIE : stm32f10x.h
  • DMA_CCR2_MEM2MEM : stm32f10x.h
  • DMA_CCR2_MINC : stm32f10x.h
  • DMA_CCR2_MSIZE : stm32f10x.h
  • DMA_CCR2_MSIZE_0 : stm32f10x.h
  • DMA_CCR2_MSIZE_1 : stm32f10x.h
  • DMA_CCR2_PINC : stm32f10x.h
  • DMA_CCR2_PL : stm32f10x.h
  • DMA_CCR2_PL_0 : stm32f10x.h
  • DMA_CCR2_PL_1 : stm32f10x.h
  • DMA_CCR2_PSIZE : stm32f10x.h
  • DMA_CCR2_PSIZE_0 : stm32f10x.h
  • DMA_CCR2_PSIZE_1 : stm32f10x.h
  • DMA_CCR2_TCIE : stm32f10x.h
  • DMA_CCR2_TEIE : stm32f10x.h
  • DMA_CCR3_CIRC : stm32f10x.h
  • DMA_CCR3_DIR : stm32f10x.h
  • DMA_CCR3_EN : stm32f10x.h
  • DMA_CCR3_HTIE : stm32f10x.h
  • DMA_CCR3_MEM2MEM : stm32f10x.h
  • DMA_CCR3_MINC : stm32f10x.h
  • DMA_CCR3_MSIZE : stm32f10x.h
  • DMA_CCR3_MSIZE_0 : stm32f10x.h
  • DMA_CCR3_MSIZE_1 : stm32f10x.h
  • DMA_CCR3_PINC : stm32f10x.h
  • DMA_CCR3_PL : stm32f10x.h
  • DMA_CCR3_PL_0 : stm32f10x.h
  • DMA_CCR3_PL_1 : stm32f10x.h
  • DMA_CCR3_PSIZE : stm32f10x.h
  • DMA_CCR3_PSIZE_0 : stm32f10x.h
  • DMA_CCR3_PSIZE_1 : stm32f10x.h
  • DMA_CCR3_TCIE : stm32f10x.h
  • DMA_CCR3_TEIE : stm32f10x.h
  • DMA_CCR4_CIRC : stm32f10x.h
  • DMA_CCR4_DIR : stm32f10x.h
  • DMA_CCR4_EN : stm32f10x.h
  • DMA_CCR4_HTIE : stm32f10x.h
  • DMA_CCR4_MEM2MEM : stm32f10x.h
  • DMA_CCR4_MINC : stm32f10x.h
  • DMA_CCR4_MSIZE : stm32f10x.h
  • DMA_CCR4_MSIZE_0 : stm32f10x.h
  • DMA_CCR4_MSIZE_1 : stm32f10x.h
  • DMA_CCR4_PINC : stm32f10x.h
  • DMA_CCR4_PL : stm32f10x.h
  • DMA_CCR4_PL_0 : stm32f10x.h
  • DMA_CCR4_PL_1 : stm32f10x.h
  • DMA_CCR4_PSIZE : stm32f10x.h
  • DMA_CCR4_PSIZE_0 : stm32f10x.h
  • DMA_CCR4_PSIZE_1 : stm32f10x.h
  • DMA_CCR4_TCIE : stm32f10x.h
  • DMA_CCR4_TEIE : stm32f10x.h
  • DMA_CCR5_CIRC : stm32f10x.h
  • DMA_CCR5_DIR : stm32f10x.h
  • DMA_CCR5_EN : stm32f10x.h
  • DMA_CCR5_HTIE : stm32f10x.h
  • DMA_CCR5_MEM2MEM : stm32f10x.h
  • DMA_CCR5_MINC : stm32f10x.h
  • DMA_CCR5_MSIZE : stm32f10x.h
  • DMA_CCR5_MSIZE_0 : stm32f10x.h
  • DMA_CCR5_MSIZE_1 : stm32f10x.h
  • DMA_CCR5_PINC : stm32f10x.h
  • DMA_CCR5_PL : stm32f10x.h
  • DMA_CCR5_PL_0 : stm32f10x.h
  • DMA_CCR5_PL_1 : stm32f10x.h
  • DMA_CCR5_PSIZE : stm32f10x.h
  • DMA_CCR5_PSIZE_0 : stm32f10x.h
  • DMA_CCR5_PSIZE_1 : stm32f10x.h
  • DMA_CCR5_TCIE : stm32f10x.h
  • DMA_CCR5_TEIE : stm32f10x.h
  • DMA_CCR6_CIRC : stm32f10x.h
  • DMA_CCR6_DIR : stm32f10x.h
  • DMA_CCR6_EN : stm32f10x.h
  • DMA_CCR6_HTIE : stm32f10x.h
  • DMA_CCR6_MEM2MEM : stm32f10x.h
  • DMA_CCR6_MINC : stm32f10x.h
  • DMA_CCR6_MSIZE : stm32f10x.h
  • DMA_CCR6_MSIZE_0 : stm32f10x.h
  • DMA_CCR6_MSIZE_1 : stm32f10x.h
  • DMA_CCR6_PINC : stm32f10x.h
  • DMA_CCR6_PL : stm32f10x.h
  • DMA_CCR6_PL_0 : stm32f10x.h
  • DMA_CCR6_PL_1 : stm32f10x.h
  • DMA_CCR6_PSIZE : stm32f10x.h
  • DMA_CCR6_PSIZE_0 : stm32f10x.h
  • DMA_CCR6_PSIZE_1 : stm32f10x.h
  • DMA_CCR6_TCIE : stm32f10x.h
  • DMA_CCR6_TEIE : stm32f10x.h
  • DMA_CCR7_CIRC : stm32f10x.h
  • DMA_CCR7_DIR : stm32f10x.h
  • DMA_CCR7_EN : stm32f10x.h
  • DMA_CCR7_HTIE : stm32f10x.h
  • DMA_CCR7_MEM2MEM : stm32f10x.h
  • DMA_CCR7_MINC : stm32f10x.h
  • DMA_CCR7_MSIZE : stm32f10x.h
  • DMA_CCR7_MSIZE_0 : stm32f10x.h
  • DMA_CCR7_MSIZE_1 : stm32f10x.h
  • DMA_CCR7_PINC : stm32f10x.h
  • DMA_CCR7_PL : stm32f10x.h
  • DMA_CCR7_PL_0 : stm32f10x.h
  • DMA_CCR7_PL_1 : stm32f10x.h
  • DMA_CCR7_PSIZE : stm32f10x.h
  • DMA_CCR7_PSIZE_0 : stm32f10x.h
  • DMA_CCR7_PSIZE_1 : stm32f10x.h
  • DMA_CCR7_TCIE : stm32f10x.h
  • DMA_CCR7_TEIE : stm32f10x.h
  • DMA_CMAR1_MA : stm32f10x.h
  • DMA_CMAR2_MA : stm32f10x.h
  • DMA_CMAR3_MA : stm32f10x.h
  • DMA_CMAR4_MA : stm32f10x.h
  • DMA_CMAR5_MA : stm32f10x.h
  • DMA_CMAR6_MA : stm32f10x.h
  • DMA_CMAR7_MA : stm32f10x.h
  • DMA_CNDTR1_NDT : stm32f10x.h
  • DMA_CNDTR2_NDT : stm32f10x.h
  • DMA_CNDTR3_NDT : stm32f10x.h
  • DMA_CNDTR4_NDT : stm32f10x.h
  • DMA_CNDTR5_NDT : stm32f10x.h
  • DMA_CNDTR6_NDT : stm32f10x.h
  • DMA_CNDTR7_NDT : stm32f10x.h
  • DMA_CPAR1_PA : stm32f10x.h
  • DMA_CPAR2_PA : stm32f10x.h
  • DMA_CPAR3_PA : stm32f10x.h
  • DMA_CPAR4_PA : stm32f10x.h
  • DMA_CPAR5_PA : stm32f10x.h
  • DMA_CPAR6_PA : stm32f10x.h
  • DMA_CPAR7_PA : stm32f10x.h
  • DMA_DIR_PeripheralDST : stm32f10x_dma.h
  • DMA_DIR_PeripheralSRC : stm32f10x_dma.h
  • DMA_IFCR_CGIF1 : stm32f10x.h
  • DMA_IFCR_CGIF2 : stm32f10x.h
  • DMA_IFCR_CGIF3 : stm32f10x.h
  • DMA_IFCR_CGIF4 : stm32f10x.h
  • DMA_IFCR_CGIF5 : stm32f10x.h
  • DMA_IFCR_CGIF6 : stm32f10x.h
  • DMA_IFCR_CGIF7 : stm32f10x.h
  • DMA_IFCR_CHTIF1 : stm32f10x.h
  • DMA_IFCR_CHTIF2 : stm32f10x.h
  • DMA_IFCR_CHTIF3 : stm32f10x.h
  • DMA_IFCR_CHTIF4 : stm32f10x.h
  • DMA_IFCR_CHTIF5 : stm32f10x.h
  • DMA_IFCR_CHTIF6 : stm32f10x.h
  • DMA_IFCR_CHTIF7 : stm32f10x.h
  • DMA_IFCR_CTCIF1 : stm32f10x.h
  • DMA_IFCR_CTCIF2 : stm32f10x.h
  • DMA_IFCR_CTCIF3 : stm32f10x.h
  • DMA_IFCR_CTCIF4 : stm32f10x.h
  • DMA_IFCR_CTCIF5 : stm32f10x.h
  • DMA_IFCR_CTCIF6 : stm32f10x.h
  • DMA_IFCR_CTCIF7 : stm32f10x.h
  • DMA_IFCR_CTEIF1 : stm32f10x.h
  • DMA_IFCR_CTEIF2 : stm32f10x.h
  • DMA_IFCR_CTEIF3 : stm32f10x.h
  • DMA_IFCR_CTEIF4 : stm32f10x.h
  • DMA_IFCR_CTEIF5 : stm32f10x.h
  • DMA_IFCR_CTEIF6 : stm32f10x.h
  • DMA_IFCR_CTEIF7 : stm32f10x.h
  • DMA_ISR_GIF1 : stm32f10x.h
  • DMA_ISR_GIF2 : stm32f10x.h
  • DMA_ISR_GIF3 : stm32f10x.h
  • DMA_ISR_GIF4 : stm32f10x.h
  • DMA_ISR_GIF5 : stm32f10x.h
  • DMA_ISR_GIF6 : stm32f10x.h
  • DMA_ISR_GIF7 : stm32f10x.h
  • DMA_ISR_HTIF1 : stm32f10x.h
  • DMA_ISR_HTIF2 : stm32f10x.h
  • DMA_ISR_HTIF3 : stm32f10x.h
  • DMA_ISR_HTIF4 : stm32f10x.h
  • DMA_ISR_HTIF5 : stm32f10x.h
  • DMA_ISR_HTIF6 : stm32f10x.h
  • DMA_ISR_HTIF7 : stm32f10x.h
  • DMA_ISR_TCIF1 : stm32f10x.h
  • DMA_ISR_TCIF2 : stm32f10x.h
  • DMA_ISR_TCIF3 : stm32f10x.h
  • DMA_ISR_TCIF4 : stm32f10x.h
  • DMA_ISR_TCIF5 : stm32f10x.h
  • DMA_ISR_TCIF6 : stm32f10x.h
  • DMA_ISR_TCIF7 : stm32f10x.h
  • DMA_ISR_TEIF1 : stm32f10x.h
  • DMA_ISR_TEIF2 : stm32f10x.h
  • DMA_ISR_TEIF3 : stm32f10x.h
  • DMA_ISR_TEIF4 : stm32f10x.h
  • DMA_ISR_TEIF5 : stm32f10x.h
  • DMA_ISR_TEIF6 : stm32f10x.h
  • DMA_ISR_TEIF7 : stm32f10x.h
  • DMA_IT_HT : stm32f10x_dma.h
  • DMA_IT_TC : stm32f10x_dma.h
  • DMA_IT_TE : stm32f10x_dma.h
  • DMA_M2M_Disable : stm32f10x_dma.h
  • DMA_M2M_Enable : stm32f10x_dma.h
  • DMA_MemoryDataSize_Byte : stm32f10x_dma.h
  • DMA_MemoryDataSize_HalfWord : stm32f10x_dma.h
  • DMA_MemoryDataSize_Word : stm32f10x_dma.h
  • DMA_MemoryInc_Disable : stm32f10x_dma.h
  • DMA_MemoryInc_Enable : stm32f10x_dma.h
  • DMA_Mode_Circular : stm32f10x_dma.h
  • DMA_Mode_Normal : stm32f10x_dma.h
  • DMA_PeripheralDataSize_Byte : stm32f10x_dma.h
  • DMA_PeripheralDataSize_HalfWord : stm32f10x_dma.h
  • DMA_PeripheralDataSize_Word : stm32f10x_dma.h
  • DMA_PeripheralInc_Disable : stm32f10x_dma.h
  • DMA_PeripheralInc_Enable : stm32f10x_dma.h
  • DMA_Priority_High : stm32f10x_dma.h
  • DMA_Priority_Low : stm32f10x_dma.h
  • DMA_Priority_Medium : stm32f10x_dma.h
  • DMA_Priority_VeryHigh : stm32f10x_dma.h
  • DMAEN_BitNumber : stm32f10x_sdio.c
  • DOR_OFFSET : stm32f10x_dac.c
  • DOWN_BUTTON_EXTI_IRQn : stm3210e_eval.h , stm32100e_eval.h , stm32l152_eval.h , stm3210b_eval.h , stm32100b_eval.h
  • DOWN_BUTTON_EXTI_LINE : stm32100e_eval.h , stm32100b_eval.h , stm3210e_eval.h , stm3210b_eval.h , stm32l152_eval.h
  • DOWN_BUTTON_EXTI_PIN_SOURCE : stm32100e_eval.h , stm3210b_eval.h , stm32100b_eval.h , stm3210e_eval.h , stm32l152_eval.h
  • DOWN_BUTTON_EXTI_PORT_SOURCE : stm3210e_eval.h , stm3210b_eval.h , stm32100b_eval.h , stm32100e_eval.h , stm32l152_eval.h
  • DOWN_BUTTON_GPIO_CLK : stm32100b_eval.h , stm32l152_eval.h , stm3210b_eval.h , stm32100e_eval.h , stm3210e_eval.h
  • DOWN_BUTTON_GPIO_PORT : stm32100e_eval.h , stm32100b_eval.h , stm3210e_eval.h , stm3210b_eval.h , stm32l152_eval.h
  • DOWN_BUTTON_PIN : stm32100e_eval.h , stm3210e_eval.h , stm32l152_eval.h , stm3210b_eval.h , stm32100b_eval.h
  • DR_ADDRESS : stm32f10x_adc.c
  • DUAL_SWTRIG_RESET : stm32f10x_dac.c
  • DUAL_SWTRIG_SET : stm32f10x_dac.c
  • DYMMY_BYTE : STM32F10x_StdPeriph_Examples/USART/Synchronous/main.c


STM32F10x Standard Peripherals Firmware Library: Globals

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- e -

  • EDGE_FALLING : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • EDGE_RISING : stm3210c_eval_ioe.h , stm32100e_eval_ioe.h
  • ENABLE_LCD_MSG_DISPLAY : STM32F10x_StdPeriph_Examples/I2C/EEPROM/main.c
  • ENCMDCOMPL_BitNumber : stm32f10x_sdio.c
  • EraseTimeout : stm32f10x_flash.c
  • ETH : stm32f10x.h
  • ETH_BASE : stm32f10x.h
  • ETH_DMA_BASE : stm32f10x.h
  • ETH_MAC_BASE : stm32f10x.h
  • ETH_MMC_BASE : stm32f10x.h
  • ETH_PTP_BASE : stm32f10x.h
  • EVAL_COM1 : stm3210b_eval.h , stm3210c_eval.h , stm3210e_eval.h , stm32l152_eval.h , stm32100b_eval.h , stm32100e_eval.h
  • EVAL_COM1_CLK : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210c_eval.h , stm3210e_eval.h , stm32l152_eval.h
  • EVAL_COM1_CTS_AF : stm32l152_eval.h
  • EVAL_COM1_CTS_GPIO_CLK : stm32l152_eval.h
  • EVAL_COM1_CTS_GPIO_PORT : stm32l152_eval.h
  • EVAL_COM1_CTS_PIN : stm32l152_eval.h
  • EVAL_COM1_CTS_SOURCE : stm32l152_eval.h
  • EVAL_COM1_IRQn : stm32100e_eval.h , stm3210b_eval.h , stm3210c_eval.h , stm3210e_eval.h , stm32l152_eval.h , stm32100b_eval.h
  • EVAL_COM1_RTS_AF : stm32l152_eval.h
  • EVAL_COM1_RTS_GPIO_CLK : stm32l152_eval.h
  • EVAL_COM1_RTS_GPIO_PORT : stm32l152_eval.h
  • EVAL_COM1_RTS_PIN : stm32l152_eval.h
  • EVAL_COM1_RTS_SOURCE : stm32l152_eval.h
  • EVAL_COM1_RX_AF : stm32l152_eval.h
  • EVAL_COM1_RX_GPIO_CLK : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210c_eval.h , stm3210e_eval.h , stm32l152_eval.h
  • EVAL_COM1_RX_GPIO_PORT : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210c_eval.h , stm3210e_eval.h , stm32l152_eval.h
  • EVAL_COM1_RX_PIN : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210c_eval.h , stm3210e_eval.h , stm32l152_eval.h
  • EVAL_COM1_RX_SOURCE : stm32l152_eval.h
  • EVAL_COM1_TX_AF : stm32l152_eval.h
  • EVAL_COM1_TX_GPIO_CLK : stm32100e_eval.h , stm3210b_eval.h , stm3210c_eval.h , stm3210e_eval.h , stm32l152_eval.h , stm32100b_eval.h
  • EVAL_COM1_TX_GPIO_PORT : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210c_eval.h , stm3210e_eval.h , stm32l152_eval.h
  • EVAL_COM1_TX_PIN : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210c_eval.h , stm3210e_eval.h , stm32l152_eval.h
  • EVAL_COM1_TX_SOURCE : stm32l152_eval.h
  • EVAL_COM2 : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210e_eval.h , stm32l152_eval.h
  • EVAL_COM2_CLK : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210e_eval.h , stm32l152_eval.h
  • EVAL_COM2_IRQn : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210e_eval.h , stm32l152_eval.h
  • EVAL_COM2_RX_AF : stm32l152_eval.h
  • EVAL_COM2_RX_GPIO_CLK : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210e_eval.h , stm32l152_eval.h
  • EVAL_COM2_RX_GPIO_PORT : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210e_eval.h , stm32l152_eval.h
  • EVAL_COM2_RX_PIN : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210e_eval.h , stm32l152_eval.h
  • EVAL_COM2_RX_SOURCE : stm32l152_eval.h
  • EVAL_COM2_TX_AF : stm32l152_eval.h
  • EVAL_COM2_TX_GPIO_CLK : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210e_eval.h , stm32l152_eval.h
  • EVAL_COM2_TX_GPIO_PORT : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210e_eval.h , stm32l152_eval.h
  • EVAL_COM2_TX_PIN : stm3210e_eval.h , stm32l152_eval.h , stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h
  • EVAL_COM2_TX_SOURCE : stm32l152_eval.h
  • EVCR_EVOE_BB : stm32f10x_gpio.c
  • EVCR_OFFSET : stm32f10x_gpio.c
  • EVCR_PORTPINCONFIG_MASK : stm32f10x_gpio.c
  • EVOE_BitNumber : stm32f10x_gpio.c
  • EWI_BitNumber : stm32f10x_wwdg.c
  • EWUP_BitNumber : stm32f10x_pwr.c
  • EXTI : stm32f10x.h
  • EXTI_BASE : stm32f10x.h
  • EXTI_EMR_MR0 : stm32f10x.h
  • EXTI_EMR_MR1 : stm32f10x.h
  • EXTI_EMR_MR10 : stm32f10x.h
  • EXTI_EMR_MR11 : stm32f10x.h
  • EXTI_EMR_MR12 : stm32f10x.h
  • EXTI_EMR_MR13 : stm32f10x.h
  • EXTI_EMR_MR14 : stm32f10x.h
  • EXTI_EMR_MR15 : stm32f10x.h
  • EXTI_EMR_MR16 : stm32f10x.h
  • EXTI_EMR_MR17 : stm32f10x.h
  • EXTI_EMR_MR18 : stm32f10x.h
  • EXTI_EMR_MR19 : stm32f10x.h
  • EXTI_EMR_MR2 : stm32f10x.h
  • EXTI_EMR_MR3 : stm32f10x.h
  • EXTI_EMR_MR4 : stm32f10x.h
  • EXTI_EMR_MR5 : stm32f10x.h
  • EXTI_EMR_MR6 : stm32f10x.h
  • EXTI_EMR_MR7 : stm32f10x.h
  • EXTI_EMR_MR8 : stm32f10x.h
  • EXTI_EMR_MR9 : stm32f10x.h
  • EXTI_FTSR_TR0 : stm32f10x.h
  • EXTI_FTSR_TR1 : stm32f10x.h
  • EXTI_FTSR_TR10 : stm32f10x.h
  • EXTI_FTSR_TR11 : stm32f10x.h
  • EXTI_FTSR_TR12 : stm32f10x.h
  • EXTI_FTSR_TR13 : stm32f10x.h
  • EXTI_FTSR_TR14 : stm32f10x.h
  • EXTI_FTSR_TR15 : stm32f10x.h
  • EXTI_FTSR_TR16 : stm32f10x.h
  • EXTI_FTSR_TR17 : stm32f10x.h
  • EXTI_FTSR_TR18 : stm32f10x.h
  • EXTI_FTSR_TR19 : stm32f10x.h
  • EXTI_FTSR_TR2 : stm32f10x.h
  • EXTI_FTSR_TR3 : stm32f10x.h
  • EXTI_FTSR_TR4 : stm32f10x.h
  • EXTI_FTSR_TR5 : stm32f10x.h
  • EXTI_FTSR_TR6 : stm32f10x.h
  • EXTI_FTSR_TR7 : stm32f10x.h
  • EXTI_FTSR_TR8 : stm32f10x.h
  • EXTI_FTSR_TR9 : stm32f10x.h
  • EXTI_IMR_MR0 : stm32f10x.h
  • EXTI_IMR_MR1 : stm32f10x.h
  • EXTI_IMR_MR10 : stm32f10x.h
  • EXTI_IMR_MR11 : stm32f10x.h
  • EXTI_IMR_MR12 : stm32f10x.h
  • EXTI_IMR_MR13 : stm32f10x.h
  • EXTI_IMR_MR14 : stm32f10x.h
  • EXTI_IMR_MR15 : stm32f10x.h
  • EXTI_IMR_MR16 : stm32f10x.h
  • EXTI_IMR_MR17 : stm32f10x.h
  • EXTI_IMR_MR18 : stm32f10x.h
  • EXTI_IMR_MR19 : stm32f10x.h
  • EXTI_IMR_MR2 : stm32f10x.h
  • EXTI_IMR_MR3 : stm32f10x.h
  • EXTI_IMR_MR4 : stm32f10x.h
  • EXTI_IMR_MR5 : stm32f10x.h
  • EXTI_IMR_MR6 : stm32f10x.h
  • EXTI_IMR_MR7 : stm32f10x.h
  • EXTI_IMR_MR8 : stm32f10x.h
  • EXTI_IMR_MR9 : stm32f10x.h
  • EXTI_Line0 : stm32f10x_exti.h
  • EXTI_Line1 : stm32f10x_exti.h
  • EXTI_Line10 : stm32f10x_exti.h
  • EXTI_Line11 : stm32f10x_exti.h
  • EXTI_Line12 : stm32f10x_exti.h
  • EXTI_Line13 : stm32f10x_exti.h
  • EXTI_Line14 : stm32f10x_exti.h
  • EXTI_Line15 : stm32f10x_exti.h
  • EXTI_Line16 : stm32f10x_exti.h
  • EXTI_Line17 : stm32f10x_exti.h
  • EXTI_Line18 : stm32f10x_exti.h
  • EXTI_Line19 : stm32f10x_exti.h
  • EXTI_Line2 : stm32f10x_exti.h
  • EXTI_Line3 : stm32f10x_exti.h
  • EXTI_Line4 : stm32f10x_exti.h
  • EXTI_Line5 : stm32f10x_exti.h
  • EXTI_Line6 : stm32f10x_exti.h
  • EXTI_Line7 : stm32f10x_exti.h
  • EXTI_Line8 : stm32f10x_exti.h
  • EXTI_Line9 : stm32f10x_exti.h
  • EXTI_LINENONE : stm32f10x_exti.c
  • EXTI_PR_PR0 : stm32f10x.h
  • EXTI_PR_PR1 : stm32f10x.h
  • EXTI_PR_PR10 : stm32f10x.h
  • EXTI_PR_PR11 : stm32f10x.h
  • EXTI_PR_PR12 : stm32f10x.h
  • EXTI_PR_PR13 : stm32f10x.h
  • EXTI_PR_PR14 : stm32f10x.h
  • EXTI_PR_PR15 : stm32f10x.h
  • EXTI_PR_PR16 : stm32f10x.h
  • EXTI_PR_PR17 : stm32f10x.h
  • EXTI_PR_PR18 : stm32f10x.h
  • EXTI_PR_PR19 : stm32f10x.h
  • EXTI_PR_PR2 : stm32f10x.h
  • EXTI_PR_PR3 : stm32f10x.h
  • EXTI_PR_PR4 : stm32f10x.h
  • EXTI_PR_PR5 : stm32f10x.h
  • EXTI_PR_PR6 : stm32f10x.h
  • EXTI_PR_PR7 : stm32f10x.h
  • EXTI_PR_PR8 : stm32f10x.h
  • EXTI_PR_PR9 : stm32f10x.h
  • EXTI_RTSR_TR0 : stm32f10x.h
  • EXTI_RTSR_TR1 : stm32f10x.h
  • EXTI_RTSR_TR10 : stm32f10x.h
  • EXTI_RTSR_TR11 : stm32f10x.h
  • EXTI_RTSR_TR12 : stm32f10x.h
  • EXTI_RTSR_TR13 : stm32f10x.h
  • EXTI_RTSR_TR14 : stm32f10x.h
  • EXTI_RTSR_TR15 : stm32f10x.h
  • EXTI_RTSR_TR16 : stm32f10x.h
  • EXTI_RTSR_TR17 : stm32f10x.h
  • EXTI_RTSR_TR18 : stm32f10x.h
  • EXTI_RTSR_TR19 : stm32f10x.h
  • EXTI_RTSR_TR2 : stm32f10x.h
  • EXTI_RTSR_TR3 : stm32f10x.h
  • EXTI_RTSR_TR4 : stm32f10x.h
  • EXTI_RTSR_TR5 : stm32f10x.h
  • EXTI_RTSR_TR6 : stm32f10x.h
  • EXTI_RTSR_TR7 : stm32f10x.h
  • EXTI_RTSR_TR8 : stm32f10x.h
  • EXTI_RTSR_TR9 : stm32f10x.h
  • EXTI_SWIER_SWIER0 : stm32f10x.h
  • EXTI_SWIER_SWIER1 : stm32f10x.h
  • EXTI_SWIER_SWIER10 : stm32f10x.h
  • EXTI_SWIER_SWIER11 : stm32f10x.h
  • EXTI_SWIER_SWIER12 : stm32f10x.h
  • EXTI_SWIER_SWIER13 : stm32f10x.h
  • EXTI_SWIER_SWIER14 : stm32f10x.h
  • EXTI_SWIER_SWIER15 : stm32f10x.h
  • EXTI_SWIER_SWIER16 : stm32f10x.h
  • EXTI_SWIER_SWIER17 : stm32f10x.h
  • EXTI_SWIER_SWIER18 : stm32f10x.h
  • EXTI_SWIER_SWIER19 : stm32f10x.h
  • EXTI_SWIER_SWIER2 : stm32f10x.h
  • EXTI_SWIER_SWIER3 : stm32f10x.h
  • EXTI_SWIER_SWIER4 : stm32f10x.h
  • EXTI_SWIER_SWIER5 : stm32f10x.h
  • EXTI_SWIER_SWIER6 : stm32f10x.h
  • EXTI_SWIER_SWIER7 : stm32f10x.h
  • EXTI_SWIER_SWIER8 : stm32f10x.h
  • EXTI_SWIER_SWIER9 : stm32f10x.h


STM32F10x Standard Peripherals Firmware Library: Globals

  • File List
  • Globals
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  • Functions
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- f -

  • FLAG_Mask : stm32f10x_cec.c , stm32f10x_dma.c , stm32f10x_rcc.c , stm32f10x_i2c.c
  • FLASH : stm32f10x.h
  • FLASH_ACR_HLFCYA : stm32f10x.h
  • FLASH_ACR_LATENCY : stm32f10x.h
  • FLASH_ACR_LATENCY_0 : stm32f10x.h
  • FLASH_ACR_LATENCY_1 : stm32f10x.h
  • FLASH_ACR_LATENCY_2 : stm32f10x.h
  • FLASH_ACR_PRFTBE : stm32f10x.h
  • FLASH_ACR_PRFTBS : stm32f10x.h
  • FLASH_ADDRESS_START : CortexM3/MPU/main.h
  • FLASH_AR_FAR : stm32f10x.h
  • FLASH_BANK1_END_ADDRESS : stm32f10x_flash.c
  • FLASH_BASE : stm32f10x.h
  • FLASH_CR_EOPIE : stm32f10x.h
  • FLASH_CR_ERRIE : stm32f10x.h
  • FLASH_CR_LOCK : stm32f10x.h
  • FLASH_CR_MER : stm32f10x.h
  • FLASH_CR_OPTER : stm32f10x.h
  • FLASH_CR_OPTPG : stm32f10x.h
  • FLASH_CR_OPTWRE : stm32f10x.h
  • FLASH_CR_PER : stm32f10x.h
  • FLASH_CR_PG : stm32f10x.h
  • FLASH_CR_STRT : stm32f10x.h
  • FLASH_Data0_Data0 : stm32f10x.h
  • FLASH_Data0_nData0 : stm32f10x.h
  • FLASH_Data1_Data1 : stm32f10x.h
  • FLASH_Data1_nData1 : stm32f10x.h
  • FLASH_FLAG_BANK1_BSY : stm32f10x_flash.h
  • FLASH_FLAG_BANK1_EOP : stm32f10x_flash.h
  • FLASH_FLAG_BANK1_PGERR : stm32f10x_flash.h
  • FLASH_FLAG_BANK1_WRPRTERR : stm32f10x_flash.h
  • FLASH_FLAG_BSY : stm32f10x_flash.h
  • FLASH_FLAG_EOP : stm32f10x_flash.h
  • FLASH_FLAG_OPTERR : stm32f10x_flash.h
  • FLASH_FLAG_PGERR : stm32f10x_flash.h
  • FLASH_FLAG_WRPRTERR : stm32f10x_flash.h
  • FLASH_HalfCycleAccess_Disable : stm32f10x_flash.h
  • FLASH_HalfCycleAccess_Enable : stm32f10x_flash.h
  • FLASH_IT_BANK1_EOP : stm32f10x_flash.h
  • FLASH_IT_BANK1_ERROR : stm32f10x_flash.h
  • FLASH_IT_EOP : stm32f10x_flash.h
  • FLASH_IT_ERROR : stm32f10x_flash.h
  • FLASH_KEY1 : stm32f10x_flash.c
  • FLASH_KEY2 : stm32f10x_flash.c
  • FLASH_KEYR_FKEYR : stm32f10x.h
  • FLASH_Latency_0 : stm32f10x_flash.h
  • FLASH_Latency_1 : stm32f10x_flash.h
  • FLASH_Latency_2 : stm32f10x_flash.h
  • FLASH_OBR_BFB2 : stm32f10x.h
  • FLASH_OBR_nRST_STDBY : stm32f10x.h
  • FLASH_OBR_nRST_STOP : stm32f10x.h
  • FLASH_OBR_OPTERR : stm32f10x.h
  • FLASH_OBR_RDPRT : stm32f10x.h
  • FLASH_OBR_USER : stm32f10x.h
  • FLASH_OBR_WDG_SW : stm32f10x.h
  • FLASH_OPTKEYR_OPTKEYR : stm32f10x.h
  • FLASH_PAGE_SIZE : STM32F10x_StdPeriph_Examples/FLASH/Program/main.c , STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/main.c
  • FLASH_PAGES_TO_BE_PROTECTED : STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/main.c
  • FLASH_PrefetchBuffer_Disable : stm32f10x_flash.h
  • FLASH_PrefetchBuffer_Enable : stm32f10x_flash.h
  • FLASH_R_BASE : stm32f10x.h
  • FLASH_RDP_nRDP : stm32f10x.h
  • FLASH_RDP_RDP : stm32f10x.h
  • FLASH_ReadAddress : STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/main.c
  • FLASH_REGION_NUMBER : CortexM3/MPU/main.h
  • FLASH_SectorToErase : STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/main.c
  • FLASH_SIZE : CortexM3/MPU/main.h
  • FLASH_SR_BSY : stm32f10x.h
  • FLASH_SR_EOP : stm32f10x.h
  • FLASH_SR_PGERR : stm32f10x.h
  • FLASH_SR_WRPRTERR : stm32f10x.h
  • FLASH_USER_nUSER : stm32f10x.h
  • FLASH_USER_USER : stm32f10x.h
  • FLASH_WriteAddress : STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/main.c
  • FLASH_WRP0_nWRP0 : stm32f10x.h
  • FLASH_WRP0_WRP0 : stm32f10x.h
  • FLASH_WRP1_nWRP1 : stm32f10x.h
  • FLASH_WRP1_WRP1 : stm32f10x.h
  • FLASH_WRP2_nWRP2 : stm32f10x.h
  • FLASH_WRP2_WRP2 : stm32f10x.h
  • FLASH_WRP3_nWRP3 : stm32f10x.h
  • FLASH_WRP3_WRP3 : stm32f10x.h
  • FLASH_WRPR_WRP : stm32f10x.h
  • FLASH_WRProt_AllPages : stm32f10x_flash.h
  • FLASH_WRProt_Pages0to1 : stm32f10x_flash.h
  • FLASH_WRProt_Pages0to3 : stm32f10x_flash.h
  • FLASH_WRProt_Pages100to103 : stm32f10x_flash.h
  • FLASH_WRProt_Pages104to107 : stm32f10x_flash.h
  • FLASH_WRProt_Pages108to111 : stm32f10x_flash.h
  • FLASH_WRProt_Pages10to11 : stm32f10x_flash.h
  • FLASH_WRProt_Pages112to115 : stm32f10x_flash.h
  • FLASH_WRProt_Pages116to119 : stm32f10x_flash.h
  • FLASH_WRProt_Pages120to123 : stm32f10x_flash.h
  • FLASH_WRProt_Pages124to127 : stm32f10x_flash.h
  • FLASH_WRProt_Pages12to13 : stm32f10x_flash.h
  • FLASH_WRProt_Pages12to15 : stm32f10x_flash.h
  • FLASH_WRProt_Pages14to15 : stm32f10x_flash.h
  • FLASH_WRProt_Pages16to17 : stm32f10x_flash.h
  • FLASH_WRProt_Pages16to19 : stm32f10x_flash.h
  • FLASH_WRProt_Pages18to19 : stm32f10x_flash.h
  • FLASH_WRProt_Pages20to21 : stm32f10x_flash.h
  • FLASH_WRProt_Pages20to23 : stm32f10x_flash.h
  • FLASH_WRProt_Pages22to23 : stm32f10x_flash.h
  • FLASH_WRProt_Pages24to25 : stm32f10x_flash.h
  • FLASH_WRProt_Pages24to27 : stm32f10x_flash.h
  • FLASH_WRProt_Pages26to27 : stm32f10x_flash.h
  • FLASH_WRProt_Pages28to29 : stm32f10x_flash.h
  • FLASH_WRProt_Pages28to31 : stm32f10x_flash.h
  • FLASH_WRProt_Pages2to3 : stm32f10x_flash.h
  • FLASH_WRProt_Pages30to31 : stm32f10x_flash.h
  • FLASH_WRProt_Pages32to33 : stm32f10x_flash.h
  • FLASH_WRProt_Pages32to35 : stm32f10x_flash.h
  • FLASH_WRProt_Pages34to35 : stm32f10x_flash.h
  • FLASH_WRProt_Pages36to37 : stm32f10x_flash.h
  • FLASH_WRProt_Pages36to39 : stm32f10x_flash.h
  • FLASH_WRProt_Pages38to39 : stm32f10x_flash.h
  • FLASH_WRProt_Pages40to41 : stm32f10x_flash.h
  • FLASH_WRProt_Pages40to43 : stm32f10x_flash.h
  • FLASH_WRProt_Pages42to43 : stm32f10x_flash.h
  • FLASH_WRProt_Pages44to45 : stm32f10x_flash.h
  • FLASH_WRProt_Pages44to47 : stm32f10x_flash.h
  • FLASH_WRProt_Pages46to47 : stm32f10x_flash.h
  • FLASH_WRProt_Pages48to49 : stm32f10x_flash.h
  • FLASH_WRProt_Pages48to51 : stm32f10x_flash.h
  • FLASH_WRProt_Pages4to5 : stm32f10x_flash.h
  • FLASH_WRProt_Pages4to7 : stm32f10x_flash.h
  • FLASH_WRProt_Pages50to51 : stm32f10x_flash.h
  • FLASH_WRProt_Pages52to53 : stm32f10x_flash.h
  • FLASH_WRProt_Pages52to55 : stm32f10x_flash.h
  • FLASH_WRProt_Pages54to55 : stm32f10x_flash.h
  • FLASH_WRProt_Pages56to57 : stm32f10x_flash.h
  • FLASH_WRProt_Pages56to59 : stm32f10x_flash.h
  • FLASH_WRProt_Pages58to59 : stm32f10x_flash.h
  • FLASH_WRProt_Pages60to61 : stm32f10x_flash.h
  • FLASH_WRProt_Pages60to63 : stm32f10x_flash.h
  • FLASH_WRProt_Pages62to127 : stm32f10x_flash.h
  • FLASH_WRProt_Pages62to255 : stm32f10x_flash.h
  • FLASH_WRProt_Pages62to511 : stm32f10x_flash.h
  • FLASH_WRProt_Pages64to67 : stm32f10x_flash.h
  • FLASH_WRProt_Pages68to71 : stm32f10x_flash.h
  • FLASH_WRProt_Pages6to7 : stm32f10x_flash.h
  • FLASH_WRProt_Pages72to75 : stm32f10x_flash.h
  • FLASH_WRProt_Pages76to79 : stm32f10x_flash.h
  • FLASH_WRProt_Pages80to83 : stm32f10x_flash.h
  • FLASH_WRProt_Pages84to87 : stm32f10x_flash.h
  • FLASH_WRProt_Pages88to91 : stm32f10x_flash.h
  • FLASH_WRProt_Pages8to11 : stm32f10x_flash.h
  • FLASH_WRProt_Pages8to9 : stm32f10x_flash.h
  • FLASH_WRProt_Pages92to95 : stm32f10x_flash.h
  • FLASH_WRProt_Pages96to99 : stm32f10x_flash.h
  • FMR_FINIT : stm32f10x_can.c
  • FOLLOWER : STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_conf.h
  • FSMC_AccessMode_A : stm32f10x_fsmc.h
  • FSMC_AccessMode_B : stm32f10x_fsmc.h
  • FSMC_AccessMode_C : stm32f10x_fsmc.h
  • FSMC_AccessMode_D : stm32f10x_fsmc.h
  • FSMC_AsynchronousWait_Disable : stm32f10x_fsmc.h
  • FSMC_AsynchronousWait_Enable : stm32f10x_fsmc.h
  • FSMC_Bank1 : stm32f10x.h
  • FSMC_Bank1_NORSRAM1 : stm32f10x_fsmc.h
  • FSMC_Bank1_NORSRAM2 : stm32f10x_fsmc.h
  • FSMC_Bank1_NORSRAM3 : stm32f10x_fsmc.h
  • FSMC_Bank1_NORSRAM4 : stm32f10x_fsmc.h
  • FSMC_Bank1_R_BASE : stm32f10x.h
  • FSMC_Bank1E : stm32f10x.h
  • FSMC_Bank1E_R_BASE : stm32f10x.h
  • FSMC_Bank2 : stm32f10x.h
  • FSMC_Bank2_NAND : stm32f10x_fsmc.h
  • FSMC_Bank2_R_BASE : stm32f10x.h
  • FSMC_Bank3 : stm32f10x.h
  • FSMC_Bank3_NAND : stm32f10x_fsmc.h
  • FSMC_Bank3_R_BASE : stm32f10x.h
  • FSMC_Bank4 : stm32f10x.h
  • FSMC_Bank4_PCCARD : stm32f10x_fsmc.h
  • FSMC_Bank4_R_BASE : stm32f10x.h
  • FSMC_Bank_NAND : stm3210e_eval_fsmc_nand.c
  • FSMC_BCR1_ASYNCWAIT : stm32f10x.h
  • FSMC_BCR1_BURSTEN : stm32f10x.h
  • FSMC_BCR1_CBURSTRW : stm32f10x.h
  • FSMC_BCR1_EXTMOD : stm32f10x.h
  • FSMC_BCR1_FACCEN : stm32f10x.h
  • FSMC_BCR1_MBKEN : stm32f10x.h
  • FSMC_BCR1_MTYP : stm32f10x.h
  • FSMC_BCR1_MTYP_0 : stm32f10x.h
  • FSMC_BCR1_MTYP_1 : stm32f10x.h
  • FSMC_BCR1_MUXEN : stm32f10x.h
  • FSMC_BCR1_MWID : stm32f10x.h
  • FSMC_BCR1_MWID_0 : stm32f10x.h
  • FSMC_BCR1_MWID_1 : stm32f10x.h
  • FSMC_BCR1_WAITCFG : stm32f10x.h
  • FSMC_BCR1_WAITEN : stm32f10x.h
  • FSMC_BCR1_WAITPOL : stm32f10x.h
  • FSMC_BCR1_WRAPMOD : stm32f10x.h
  • FSMC_BCR1_WREN : stm32f10x.h
  • FSMC_BCR2_ASYNCWAIT : stm32f10x.h
  • FSMC_BCR2_BURSTEN : stm32f10x.h
  • FSMC_BCR2_CBURSTRW : stm32f10x.h
  • FSMC_BCR2_EXTMOD : stm32f10x.h
  • FSMC_BCR2_FACCEN : stm32f10x.h
  • FSMC_BCR2_MBKEN : stm32f10x.h
  • FSMC_BCR2_MTYP : stm32f10x.h
  • FSMC_BCR2_MTYP_0 : stm32f10x.h
  • FSMC_BCR2_MTYP_1 : stm32f10x.h
  • FSMC_BCR2_MUXEN : stm32f10x.h
  • FSMC_BCR2_MWID : stm32f10x.h
  • FSMC_BCR2_MWID_0 : stm32f10x.h
  • FSMC_BCR2_MWID_1 : stm32f10x.h
  • FSMC_BCR2_WAITCFG : stm32f10x.h
  • FSMC_BCR2_WAITEN : stm32f10x.h
  • FSMC_BCR2_WAITPOL : stm32f10x.h
  • FSMC_BCR2_WRAPMOD : stm32f10x.h
  • FSMC_BCR2_WREN : stm32f10x.h
  • FSMC_BCR3_ASYNCWAIT : stm32f10x.h
  • FSMC_BCR3_BURSTEN : stm32f10x.h
  • FSMC_BCR3_CBURSTRW : stm32f10x.h
  • FSMC_BCR3_EXTMOD : stm32f10x.h
  • FSMC_BCR3_FACCEN : stm32f10x.h
  • FSMC_BCR3_MBKEN : stm32f10x.h
  • FSMC_BCR3_MTYP : stm32f10x.h
  • FSMC_BCR3_MTYP_0 : stm32f10x.h
  • FSMC_BCR3_MTYP_1 : stm32f10x.h
  • FSMC_BCR3_MUXEN : stm32f10x.h
  • FSMC_BCR3_MWID : stm32f10x.h
  • FSMC_BCR3_MWID_0 : stm32f10x.h
  • FSMC_BCR3_MWID_1 : stm32f10x.h
  • FSMC_BCR3_WAITCFG : stm32f10x.h
  • FSMC_BCR3_WAITEN : stm32f10x.h
  • FSMC_BCR3_WAITPOL : stm32f10x.h
  • FSMC_BCR3_WRAPMOD : stm32f10x.h
  • FSMC_BCR3_WREN : stm32f10x.h
  • FSMC_BCR4_ASYNCWAIT : stm32f10x.h
  • FSMC_BCR4_BURSTEN : stm32f10x.h
  • FSMC_BCR4_CBURSTRW : stm32f10x.h
  • FSMC_BCR4_EXTMOD : stm32f10x.h
  • FSMC_BCR4_FACCEN : stm32f10x.h
  • FSMC_BCR4_MBKEN : stm32f10x.h
  • FSMC_BCR4_MTYP : stm32f10x.h
  • FSMC_BCR4_MTYP_0 : stm32f10x.h
  • FSMC_BCR4_MTYP_1 : stm32f10x.h
  • FSMC_BCR4_MUXEN : stm32f10x.h
  • FSMC_BCR4_MWID : stm32f10x.h
  • FSMC_BCR4_MWID_0 : stm32f10x.h
  • FSMC_BCR4_MWID_1 : stm32f10x.h
  • FSMC_BCR4_WAITCFG : stm32f10x.h
  • FSMC_BCR4_WAITEN : stm32f10x.h
  • FSMC_BCR4_WAITPOL : stm32f10x.h
  • FSMC_BCR4_WRAPMOD : stm32f10x.h
  • FSMC_BCR4_WREN : stm32f10x.h
  • FSMC_BTR1_ACCMOD : stm32f10x.h
  • FSMC_BTR1_ACCMOD_0 : stm32f10x.h
  • FSMC_BTR1_ACCMOD_1 : stm32f10x.h
  • FSMC_BTR1_ADDHLD : stm32f10x.h
  • FSMC_BTR1_ADDHLD_0 : stm32f10x.h
  • FSMC_BTR1_ADDHLD_1 : stm32f10x.h
  • FSMC_BTR1_ADDHLD_2 : stm32f10x.h
  • FSMC_BTR1_ADDHLD_3 : stm32f10x.h
  • FSMC_BTR1_ADDSET : stm32f10x.h
  • FSMC_BTR1_ADDSET_0 : stm32f10x.h
  • FSMC_BTR1_ADDSET_1 : stm32f10x.h
  • FSMC_BTR1_ADDSET_2 : stm32f10x.h
  • FSMC_BTR1_ADDSET_3 : stm32f10x.h
  • FSMC_BTR1_BUSTURN : stm32f10x.h
  • FSMC_BTR1_BUSTURN_0 : stm32f10x.h
  • FSMC_BTR1_BUSTURN_1 : stm32f10x.h
  • FSMC_BTR1_BUSTURN_2 : stm32f10x.h
  • FSMC_BTR1_BUSTURN_3 : stm32f10x.h
  • FSMC_BTR1_CLKDIV : stm32f10x.h
  • FSMC_BTR1_CLKDIV_0 : stm32f10x.h
  • FSMC_BTR1_CLKDIV_1 : stm32f10x.h
  • FSMC_BTR1_CLKDIV_2 : stm32f10x.h
  • FSMC_BTR1_CLKDIV_3 : stm32f10x.h
  • FSMC_BTR1_DATAST : stm32f10x.h
  • FSMC_BTR1_DATAST_0 : stm32f10x.h
  • FSMC_BTR1_DATAST_1 : stm32f10x.h
  • FSMC_BTR1_DATAST_2 : stm32f10x.h
  • FSMC_BTR1_DATAST_3 : stm32f10x.h
  • FSMC_BTR1_DATLAT : stm32f10x.h
  • FSMC_BTR1_DATLAT_0 : stm32f10x.h
  • FSMC_BTR1_DATLAT_1 : stm32f10x.h
  • FSMC_BTR1_DATLAT_2 : stm32f10x.h
  • FSMC_BTR1_DATLAT_3 : stm32f10x.h
  • FSMC_BTR2_ACCMOD : stm32f10x.h
  • FSMC_BTR2_ACCMOD_0 : stm32f10x.h
  • FSMC_BTR2_ACCMOD_1 : stm32f10x.h
  • FSMC_BTR2_ADDHLD : stm32f10x.h
  • FSMC_BTR2_ADDHLD_0 : stm32f10x.h
  • FSMC_BTR2_ADDHLD_1 : stm32f10x.h
  • FSMC_BTR2_ADDHLD_2 : stm32f10x.h
  • FSMC_BTR2_ADDHLD_3 : stm32f10x.h
  • FSMC_BTR2_ADDSET : stm32f10x.h
  • FSMC_BTR2_ADDSET_0 : stm32f10x.h
  • FSMC_BTR2_ADDSET_1 : stm32f10x.h
  • FSMC_BTR2_ADDSET_2 : stm32f10x.h
  • FSMC_BTR2_ADDSET_3 : stm32f10x.h
  • FSMC_BTR2_BUSTURN : stm32f10x.h
  • FSMC_BTR2_BUSTURN_0 : stm32f10x.h
  • FSMC_BTR2_BUSTURN_1 : stm32f10x.h
  • FSMC_BTR2_BUSTURN_2 : stm32f10x.h
  • FSMC_BTR2_BUSTURN_3 : stm32f10x.h
  • FSMC_BTR2_CLKDIV : stm32f10x.h
  • FSMC_BTR2_CLKDIV_0 : stm32f10x.h
  • FSMC_BTR2_CLKDIV_1 : stm32f10x.h
  • FSMC_BTR2_CLKDIV_2 : stm32f10x.h
  • FSMC_BTR2_CLKDIV_3 : stm32f10x.h
  • FSMC_BTR2_DATAST : stm32f10x.h
  • FSMC_BTR2_DATAST_0 : stm32f10x.h
  • FSMC_BTR2_DATAST_1 : stm32f10x.h
  • FSMC_BTR2_DATAST_2 : stm32f10x.h
  • FSMC_BTR2_DATAST_3 : stm32f10x.h
  • FSMC_BTR2_DATLAT : stm32f10x.h
  • FSMC_BTR2_DATLAT_0 : stm32f10x.h
  • FSMC_BTR2_DATLAT_1 : stm32f10x.h
  • FSMC_BTR2_DATLAT_2 : stm32f10x.h
  • FSMC_BTR2_DATLAT_3 : stm32f10x.h
  • FSMC_BTR3_ACCMOD : stm32f10x.h
  • FSMC_BTR3_ACCMOD_0 : stm32f10x.h
  • FSMC_BTR3_ACCMOD_1 : stm32f10x.h
  • FSMC_BTR3_ADDHLD : stm32f10x.h
  • FSMC_BTR3_ADDHLD_0 : stm32f10x.h
  • FSMC_BTR3_ADDHLD_1 : stm32f10x.h
  • FSMC_BTR3_ADDHLD_2 : stm32f10x.h
  • FSMC_BTR3_ADDHLD_3 : stm32f10x.h
  • FSMC_BTR3_ADDSET : stm32f10x.h
  • FSMC_BTR3_ADDSET_0 : stm32f10x.h
  • FSMC_BTR3_ADDSET_1 : stm32f10x.h
  • FSMC_BTR3_ADDSET_2 : stm32f10x.h
  • FSMC_BTR3_ADDSET_3 : stm32f10x.h
  • FSMC_BTR3_BUSTURN : stm32f10x.h
  • FSMC_BTR3_BUSTURN_0 : stm32f10x.h
  • FSMC_BTR3_BUSTURN_1 : stm32f10x.h
  • FSMC_BTR3_BUSTURN_2 : stm32f10x.h
  • FSMC_BTR3_BUSTURN_3 : stm32f10x.h
  • FSMC_BTR3_CLKDIV : stm32f10x.h
  • FSMC_BTR3_CLKDIV_0 : stm32f10x.h
  • FSMC_BTR3_CLKDIV_1 : stm32f10x.h
  • FSMC_BTR3_CLKDIV_2 : stm32f10x.h
  • FSMC_BTR3_CLKDIV_3 : stm32f10x.h
  • FSMC_BTR3_DATAST : stm32f10x.h
  • FSMC_BTR3_DATAST_0 : stm32f10x.h
  • FSMC_BTR3_DATAST_1 : stm32f10x.h
  • FSMC_BTR3_DATAST_2 : stm32f10x.h
  • FSMC_BTR3_DATAST_3 : stm32f10x.h
  • FSMC_BTR3_DATLAT : stm32f10x.h
  • FSMC_BTR3_DATLAT_0 : stm32f10x.h
  • FSMC_BTR3_DATLAT_1 : stm32f10x.h
  • FSMC_BTR3_DATLAT_2 : stm32f10x.h
  • FSMC_BTR3_DATLAT_3 : stm32f10x.h
  • FSMC_BTR4_ACCMOD : stm32f10x.h
  • FSMC_BTR4_ACCMOD_0 : stm32f10x.h
  • FSMC_BTR4_ACCMOD_1 : stm32f10x.h
  • FSMC_BTR4_ADDHLD : stm32f10x.h
  • FSMC_BTR4_ADDHLD_0 : stm32f10x.h
  • FSMC_BTR4_ADDHLD_1 : stm32f10x.h
  • FSMC_BTR4_ADDHLD_2 : stm32f10x.h
  • FSMC_BTR4_ADDHLD_3 : stm32f10x.h
  • FSMC_BTR4_ADDSET : stm32f10x.h
  • FSMC_BTR4_ADDSET_0 : stm32f10x.h
  • FSMC_BTR4_ADDSET_1 : stm32f10x.h
  • FSMC_BTR4_ADDSET_2 : stm32f10x.h
  • FSMC_BTR4_ADDSET_3 : stm32f10x.h
  • FSMC_BTR4_BUSTURN : stm32f10x.h
  • FSMC_BTR4_BUSTURN_0 : stm32f10x.h
  • FSMC_BTR4_BUSTURN_1 : stm32f10x.h
  • FSMC_BTR4_BUSTURN_2 : stm32f10x.h
  • FSMC_BTR4_BUSTURN_3 : stm32f10x.h
  • FSMC_BTR4_CLKDIV : stm32f10x.h
  • FSMC_BTR4_CLKDIV_0 : stm32f10x.h
  • FSMC_BTR4_CLKDIV_1 : stm32f10x.h
  • FSMC_BTR4_CLKDIV_2 : stm32f10x.h
  • FSMC_BTR4_CLKDIV_3 : stm32f10x.h
  • FSMC_BTR4_DATAST : stm32f10x.h
  • FSMC_BTR4_DATAST_0 : stm32f10x.h
  • FSMC_BTR4_DATAST_1 : stm32f10x.h
  • FSMC_BTR4_DATAST_2 : stm32f10x.h
  • FSMC_BTR4_DATAST_3 : stm32f10x.h
  • FSMC_BTR4_DATLAT : stm32f10x.h
  • FSMC_BTR4_DATLAT_0 : stm32f10x.h
  • FSMC_BTR4_DATLAT_1 : stm32f10x.h
  • FSMC_BTR4_DATLAT_2 : stm32f10x.h
  • FSMC_BTR4_DATLAT_3 : stm32f10x.h
  • FSMC_BurstAccessMode_Disable : stm32f10x_fsmc.h
  • FSMC_BurstAccessMode_Enable : stm32f10x_fsmc.h
  • FSMC_BWTR1_ACCMOD : stm32f10x.h
  • FSMC_BWTR1_ACCMOD_0 : stm32f10x.h
  • FSMC_BWTR1_ACCMOD_1 : stm32f10x.h
  • FSMC_BWTR1_ADDHLD : stm32f10x.h
  • FSMC_BWTR1_ADDHLD_0 : stm32f10x.h
  • FSMC_BWTR1_ADDHLD_1 : stm32f10x.h
  • FSMC_BWTR1_ADDHLD_2 : stm32f10x.h
  • FSMC_BWTR1_ADDHLD_3 : stm32f10x.h
  • FSMC_BWTR1_ADDSET : stm32f10x.h
  • FSMC_BWTR1_ADDSET_0 : stm32f10x.h
  • FSMC_BWTR1_ADDSET_1 : stm32f10x.h
  • FSMC_BWTR1_ADDSET_2 : stm32f10x.h
  • FSMC_BWTR1_ADDSET_3 : stm32f10x.h
  • FSMC_BWTR1_CLKDIV : stm32f10x.h
  • FSMC_BWTR1_CLKDIV_0 : stm32f10x.h
  • FSMC_BWTR1_CLKDIV_1 : stm32f10x.h
  • FSMC_BWTR1_CLKDIV_2 : stm32f10x.h
  • FSMC_BWTR1_CLKDIV_3 : stm32f10x.h
  • FSMC_BWTR1_DATAST : stm32f10x.h
  • FSMC_BWTR1_DATAST_0 : stm32f10x.h
  • FSMC_BWTR1_DATAST_1 : stm32f10x.h
  • FSMC_BWTR1_DATAST_2 : stm32f10x.h
  • FSMC_BWTR1_DATAST_3 : stm32f10x.h
  • FSMC_BWTR1_DATLAT : stm32f10x.h
  • FSMC_BWTR1_DATLAT_0 : stm32f10x.h
  • FSMC_BWTR1_DATLAT_1 : stm32f10x.h
  • FSMC_BWTR1_DATLAT_2 : stm32f10x.h
  • FSMC_BWTR1_DATLAT_3 : stm32f10x.h
  • FSMC_BWTR2_ACCMOD : stm32f10x.h
  • FSMC_BWTR2_ACCMOD_0 : stm32f10x.h
  • FSMC_BWTR2_ACCMOD_1 : stm32f10x.h
  • FSMC_BWTR2_ADDHLD : stm32f10x.h
  • FSMC_BWTR2_ADDHLD_0 : stm32f10x.h
  • FSMC_BWTR2_ADDHLD_1 : stm32f10x.h
  • FSMC_BWTR2_ADDHLD_2 : stm32f10x.h
  • FSMC_BWTR2_ADDHLD_3 : stm32f10x.h
  • FSMC_BWTR2_ADDSET : stm32f10x.h
  • FSMC_BWTR2_ADDSET_0 : stm32f10x.h
  • FSMC_BWTR2_ADDSET_1 : stm32f10x.h
  • FSMC_BWTR2_ADDSET_2 : stm32f10x.h
  • FSMC_BWTR2_ADDSET_3 : stm32f10x.h
  • FSMC_BWTR2_CLKDIV : stm32f10x.h
  • FSMC_BWTR2_CLKDIV_0 : stm32f10x.h
  • FSMC_BWTR2_CLKDIV_1 : stm32f10x.h
  • FSMC_BWTR2_CLKDIV_2 : stm32f10x.h
  • FSMC_BWTR2_CLKDIV_3 : stm32f10x.h
  • FSMC_BWTR2_DATAST : stm32f10x.h
  • FSMC_BWTR2_DATAST_0 : stm32f10x.h
  • FSMC_BWTR2_DATAST_1 : stm32f10x.h
  • FSMC_BWTR2_DATAST_2 : stm32f10x.h
  • FSMC_BWTR2_DATAST_3 : stm32f10x.h
  • FSMC_BWTR2_DATLAT : stm32f10x.h
  • FSMC_BWTR2_DATLAT_0 : stm32f10x.h
  • FSMC_BWTR2_DATLAT_1 : stm32f10x.h
  • FSMC_BWTR2_DATLAT_2 : stm32f10x.h
  • FSMC_BWTR2_DATLAT_3 : stm32f10x.h
  • FSMC_BWTR3_ACCMOD : stm32f10x.h
  • FSMC_BWTR3_ACCMOD_0 : stm32f10x.h
  • FSMC_BWTR3_ACCMOD_1 : stm32f10x.h
  • FSMC_BWTR3_ADDHLD : stm32f10x.h
  • FSMC_BWTR3_ADDHLD_0 : stm32f10x.h
  • FSMC_BWTR3_ADDHLD_1 : stm32f10x.h
  • FSMC_BWTR3_ADDHLD_2 : stm32f10x.h
  • FSMC_BWTR3_ADDHLD_3 : stm32f10x.h
  • FSMC_BWTR3_ADDSET : stm32f10x.h
  • FSMC_BWTR3_ADDSET_0 : stm32f10x.h
  • FSMC_BWTR3_ADDSET_1 : stm32f10x.h
  • FSMC_BWTR3_ADDSET_2 : stm32f10x.h
  • FSMC_BWTR3_ADDSET_3 : stm32f10x.h
  • FSMC_BWTR3_CLKDIV : stm32f10x.h
  • FSMC_BWTR3_CLKDIV_0 : stm32f10x.h
  • FSMC_BWTR3_CLKDIV_1 : stm32f10x.h
  • FSMC_BWTR3_CLKDIV_2 : stm32f10x.h
  • FSMC_BWTR3_CLKDIV_3 : stm32f10x.h
  • FSMC_BWTR3_DATAST : stm32f10x.h
  • FSMC_BWTR3_DATAST_0 : stm32f10x.h
  • FSMC_BWTR3_DATAST_1 : stm32f10x.h
  • FSMC_BWTR3_DATAST_2 : stm32f10x.h
  • FSMC_BWTR3_DATAST_3 : stm32f10x.h
  • FSMC_BWTR3_DATLAT : stm32f10x.h
  • FSMC_BWTR3_DATLAT_0 : stm32f10x.h
  • FSMC_BWTR3_DATLAT_1 : stm32f10x.h
  • FSMC_BWTR3_DATLAT_2 : stm32f10x.h
  • FSMC_BWTR3_DATLAT_3 : stm32f10x.h
  • FSMC_BWTR4_ACCMOD : stm32f10x.h
  • FSMC_BWTR4_ACCMOD_0 : stm32f10x.h
  • FSMC_BWTR4_ACCMOD_1 : stm32f10x.h
  • FSMC_BWTR4_ADDHLD : stm32f10x.h
  • FSMC_BWTR4_ADDHLD_0 : stm32f10x.h
  • FSMC_BWTR4_ADDHLD_1 : stm32f10x.h
  • FSMC_BWTR4_ADDHLD_2 : stm32f10x.h
  • FSMC_BWTR4_ADDHLD_3 : stm32f10x.h
  • FSMC_BWTR4_ADDSET : stm32f10x.h
  • FSMC_BWTR4_ADDSET_0 : stm32f10x.h
  • FSMC_BWTR4_ADDSET_1 : stm32f10x.h
  • FSMC_BWTR4_ADDSET_2 : stm32f10x.h
  • FSMC_BWTR4_ADDSET_3 : stm32f10x.h
  • FSMC_BWTR4_CLKDIV : stm32f10x.h
  • FSMC_BWTR4_CLKDIV_0 : stm32f10x.h
  • FSMC_BWTR4_CLKDIV_1 : stm32f10x.h
  • FSMC_BWTR4_CLKDIV_2 : stm32f10x.h
  • FSMC_BWTR4_CLKDIV_3 : stm32f10x.h
  • FSMC_BWTR4_DATAST : stm32f10x.h
  • FSMC_BWTR4_DATAST_0 : stm32f10x.h
  • FSMC_BWTR4_DATAST_1 : stm32f10x.h
  • FSMC_BWTR4_DATAST_2 : stm32f10x.h
  • FSMC_BWTR4_DATAST_3 : stm32f10x.h
  • FSMC_BWTR4_DATLAT : stm32f10x.h
  • FSMC_BWTR4_DATLAT_0 : stm32f10x.h
  • FSMC_BWTR4_DATLAT_1 : stm32f10x.h
  • FSMC_BWTR4_DATLAT_2 : stm32f10x.h
  • FSMC_BWTR4_DATLAT_3 : stm32f10x.h
  • FSMC_DataAddressMux_Disable : stm32f10x_fsmc.h
  • FSMC_DataAddressMux_Enable : stm32f10x_fsmc.h
  • FSMC_ECC_Disable : stm32f10x_fsmc.h
  • FSMC_ECC_Enable : stm32f10x_fsmc.h
  • FSMC_ECCPageSize_1024Bytes : stm32f10x_fsmc.h
  • FSMC_ECCPageSize_2048Bytes : stm32f10x_fsmc.h
  • FSMC_ECCPageSize_256Bytes : stm32f10x_fsmc.h
  • FSMC_ECCPageSize_4096Bytes : stm32f10x_fsmc.h
  • FSMC_ECCPageSize_512Bytes : stm32f10x_fsmc.h
  • FSMC_ECCPageSize_8192Bytes : stm32f10x_fsmc.h
  • FSMC_ECCR2_ECC2 : stm32f10x.h
  • FSMC_ECCR3_ECC3 : stm32f10x.h
  • FSMC_ExtendedMode_Disable : stm32f10x_fsmc.h
  • FSMC_ExtendedMode_Enable : stm32f10x_fsmc.h
  • FSMC_FLAG_FallingEdge : stm32f10x_fsmc.h
  • FSMC_FLAG_FEMPT : stm32f10x_fsmc.h
  • FSMC_FLAG_Level : stm32f10x_fsmc.h
  • FSMC_FLAG_RisingEdge : stm32f10x_fsmc.h
  • FSMC_IT_FallingEdge : stm32f10x_fsmc.h
  • FSMC_IT_Level : stm32f10x_fsmc.h
  • FSMC_IT_RisingEdge : stm32f10x_fsmc.h
  • FSMC_MemoryDataWidth_16b : stm32f10x_fsmc.h
  • FSMC_MemoryDataWidth_8b : stm32f10x_fsmc.h
  • FSMC_MemoryType_NOR : stm32f10x_fsmc.h
  • FSMC_MemoryType_PSRAM : stm32f10x_fsmc.h
  • FSMC_MemoryType_SRAM : stm32f10x_fsmc.h
  • FSMC_PATT2_ATTHIZ2 : stm32f10x.h
  • FSMC_PATT2_ATTHIZ2_0 : stm32f10x.h
  • FSMC_PATT2_ATTHIZ2_1 : stm32f10x.h
  • FSMC_PATT2_ATTHIZ2_2 : stm32f10x.h
  • FSMC_PATT2_ATTHIZ2_3 : stm32f10x.h
  • FSMC_PATT2_ATTHIZ2_4 : stm32f10x.h
  • FSMC_PATT2_ATTHIZ2_5 : stm32f10x.h
  • FSMC_PATT2_ATTHIZ2_6 : stm32f10x.h
  • FSMC_PATT2_ATTHIZ2_7 : stm32f10x.h
  • FSMC_PATT2_ATTHOLD2 : stm32f10x.h
  • FSMC_PATT2_ATTHOLD2_0 : stm32f10x.h
  • FSMC_PATT2_ATTHOLD2_1 : stm32f10x.h
  • FSMC_PATT2_ATTHOLD2_2 : stm32f10x.h
  • FSMC_PATT2_ATTHOLD2_3 : stm32f10x.h
  • FSMC_PATT2_ATTHOLD2_4 : stm32f10x.h
  • FSMC_PATT2_ATTHOLD2_5 : stm32f10x.h
  • FSMC_PATT2_ATTHOLD2_6 : stm32f10x.h
  • FSMC_PATT2_ATTHOLD2_7 : stm32f10x.h
  • FSMC_PATT2_ATTSET2 : stm32f10x.h
  • FSMC_PATT2_ATTSET2_0 : stm32f10x.h
  • FSMC_PATT2_ATTSET2_1 : stm32f10x.h
  • FSMC_PATT2_ATTSET2_2 : stm32f10x.h
  • FSMC_PATT2_ATTSET2_3 : stm32f10x.h
  • FSMC_PATT2_ATTSET2_4 : stm32f10x.h
  • FSMC_PATT2_ATTSET2_5 : stm32f10x.h
  • FSMC_PATT2_ATTSET2_6 : stm32f10x.h
  • FSMC_PATT2_ATTSET2_7 : stm32f10x.h
  • FSMC_PATT2_ATTWAIT2 : stm32f10x.h
  • FSMC_PATT2_ATTWAIT2_0 : stm32f10x.h
  • FSMC_PATT2_ATTWAIT2_1 : stm32f10x.h
  • FSMC_PATT2_ATTWAIT2_2 : stm32f10x.h
  • FSMC_PATT2_ATTWAIT2_3 : stm32f10x.h
  • FSMC_PATT2_ATTWAIT2_4 : stm32f10x.h
  • FSMC_PATT2_ATTWAIT2_5 : stm32f10x.h
  • FSMC_PATT2_ATTWAIT2_6 : stm32f10x.h
  • FSMC_PATT2_ATTWAIT2_7 : stm32f10x.h
  • FSMC_PATT3_ATTHIZ3 : stm32f10x.h
  • FSMC_PATT3_ATTHIZ3_0 : stm32f10x.h
  • FSMC_PATT3_ATTHIZ3_1 : stm32f10x.h
  • FSMC_PATT3_ATTHIZ3_2 : stm32f10x.h
  • FSMC_PATT3_ATTHIZ3_3 : stm32f10x.h
  • FSMC_PATT3_ATTHIZ3_4 : stm32f10x.h
  • FSMC_PATT3_ATTHIZ3_5 : stm32f10x.h
  • FSMC_PATT3_ATTHIZ3_6 : stm32f10x.h
  • FSMC_PATT3_ATTHIZ3_7 : stm32f10x.h
  • FSMC_PATT3_ATTHOLD3 : stm32f10x.h
  • FSMC_PATT3_ATTHOLD3_0 : stm32f10x.h
  • FSMC_PATT3_ATTHOLD3_1 : stm32f10x.h
  • FSMC_PATT3_ATTHOLD3_2 : stm32f10x.h
  • FSMC_PATT3_ATTHOLD3_3 : stm32f10x.h
  • FSMC_PATT3_ATTHOLD3_4 : stm32f10x.h
  • FSMC_PATT3_ATTHOLD3_5 : stm32f10x.h
  • FSMC_PATT3_ATTHOLD3_6 : stm32f10x.h
  • FSMC_PATT3_ATTHOLD3_7 : stm32f10x.h
  • FSMC_PATT3_ATTSET3 : stm32f10x.h
  • FSMC_PATT3_ATTSET3_0 : stm32f10x.h
  • FSMC_PATT3_ATTSET3_1 : stm32f10x.h
  • FSMC_PATT3_ATTSET3_2 : stm32f10x.h
  • FSMC_PATT3_ATTSET3_3 : stm32f10x.h
  • FSMC_PATT3_ATTSET3_4 : stm32f10x.h
  • FSMC_PATT3_ATTSET3_5 : stm32f10x.h
  • FSMC_PATT3_ATTSET3_6 : stm32f10x.h
  • FSMC_PATT3_ATTSET3_7 : stm32f10x.h
  • FSMC_PATT3_ATTWAIT3 : stm32f10x.h
  • FSMC_PATT3_ATTWAIT3_0 : stm32f10x.h
  • FSMC_PATT3_ATTWAIT3_1 : stm32f10x.h
  • FSMC_PATT3_ATTWAIT3_2 : stm32f10x.h
  • FSMC_PATT3_ATTWAIT3_3 : stm32f10x.h
  • FSMC_PATT3_ATTWAIT3_4 : stm32f10x.h
  • FSMC_PATT3_ATTWAIT3_5 : stm32f10x.h
  • FSMC_PATT3_ATTWAIT3_6 : stm32f10x.h
  • FSMC_PATT3_ATTWAIT3_7 : stm32f10x.h
  • FSMC_PATT4_ATTHIZ4 : stm32f10x.h
  • FSMC_PATT4_ATTHIZ4_0 : stm32f10x.h
  • FSMC_PATT4_ATTHIZ4_1 : stm32f10x.h
  • FSMC_PATT4_ATTHIZ4_2 : stm32f10x.h
  • FSMC_PATT4_ATTHIZ4_3 : stm32f10x.h
  • FSMC_PATT4_ATTHIZ4_4 : stm32f10x.h
  • FSMC_PATT4_ATTHIZ4_5 : stm32f10x.h
  • FSMC_PATT4_ATTHIZ4_6 : stm32f10x.h
  • FSMC_PATT4_ATTHIZ4_7 : stm32f10x.h
  • FSMC_PATT4_ATTHOLD4 : stm32f10x.h
  • FSMC_PATT4_ATTHOLD4_0 : stm32f10x.h
  • FSMC_PATT4_ATTHOLD4_1 : stm32f10x.h
  • FSMC_PATT4_ATTHOLD4_2 : stm32f10x.h
  • FSMC_PATT4_ATTHOLD4_3 : stm32f10x.h
  • FSMC_PATT4_ATTHOLD4_4 : stm32f10x.h
  • FSMC_PATT4_ATTHOLD4_5 : stm32f10x.h
  • FSMC_PATT4_ATTHOLD4_6 : stm32f10x.h
  • FSMC_PATT4_ATTHOLD4_7 : stm32f10x.h
  • FSMC_PATT4_ATTSET4 : stm32f10x.h
  • FSMC_PATT4_ATTSET4_0 : stm32f10x.h
  • FSMC_PATT4_ATTSET4_1 : stm32f10x.h
  • FSMC_PATT4_ATTSET4_2 : stm32f10x.h
  • FSMC_PATT4_ATTSET4_3 : stm32f10x.h
  • FSMC_PATT4_ATTSET4_4 : stm32f10x.h
  • FSMC_PATT4_ATTSET4_5 : stm32f10x.h
  • FSMC_PATT4_ATTSET4_6 : stm32f10x.h
  • FSMC_PATT4_ATTSET4_7 : stm32f10x.h
  • FSMC_PATT4_ATTWAIT4 : stm32f10x.h
  • FSMC_PATT4_ATTWAIT4_0 : stm32f10x.h
  • FSMC_PATT4_ATTWAIT4_1 : stm32f10x.h
  • FSMC_PATT4_ATTWAIT4_2 : stm32f10x.h
  • FSMC_PATT4_ATTWAIT4_3 : stm32f10x.h
  • FSMC_PATT4_ATTWAIT4_4 : stm32f10x.h
  • FSMC_PATT4_ATTWAIT4_5 : stm32f10x.h
  • FSMC_PATT4_ATTWAIT4_6 : stm32f10x.h
  • FSMC_PATT4_ATTWAIT4_7 : stm32f10x.h
  • FSMC_PCR2_ECCEN : stm32f10x.h
  • FSMC_PCR2_ECCPS : stm32f10x.h
  • FSMC_PCR2_ECCPS_0 : stm32f10x.h
  • FSMC_PCR2_ECCPS_1 : stm32f10x.h
  • FSMC_PCR2_ECCPS_2 : stm32f10x.h
  • FSMC_PCR2_PBKEN : stm32f10x.h
  • FSMC_PCR2_PTYP : stm32f10x.h
  • FSMC_PCR2_PWAITEN : stm32f10x.h
  • FSMC_PCR2_PWID : stm32f10x.h
  • FSMC_PCR2_PWID_0 : stm32f10x.h
  • FSMC_PCR2_PWID_1 : stm32f10x.h
  • FSMC_PCR2_TAR : stm32f10x.h
  • FSMC_PCR2_TAR_0 : stm32f10x.h
  • FSMC_PCR2_TAR_1 : stm32f10x.h
  • FSMC_PCR2_TAR_2 : stm32f10x.h
  • FSMC_PCR2_TAR_3 : stm32f10x.h
  • FSMC_PCR2_TCLR : stm32f10x.h
  • FSMC_PCR2_TCLR_0 : stm32f10x.h
  • FSMC_PCR2_TCLR_1 : stm32f10x.h
  • FSMC_PCR2_TCLR_2 : stm32f10x.h
  • FSMC_PCR2_TCLR_3 : stm32f10x.h
  • FSMC_PCR3_ECCEN : stm32f10x.h
  • FSMC_PCR3_ECCPS : stm32f10x.h
  • FSMC_PCR3_ECCPS_0 : stm32f10x.h
  • FSMC_PCR3_ECCPS_1 : stm32f10x.h
  • FSMC_PCR3_ECCPS_2 : stm32f10x.h
  • FSMC_PCR3_PBKEN : stm32f10x.h
  • FSMC_PCR3_PTYP : stm32f10x.h
  • FSMC_PCR3_PWAITEN : stm32f10x.h
  • FSMC_PCR3_PWID : stm32f10x.h
  • FSMC_PCR3_PWID_0 : stm32f10x.h
  • FSMC_PCR3_PWID_1 : stm32f10x.h
  • FSMC_PCR3_TAR : stm32f10x.h
  • FSMC_PCR3_TAR_0 : stm32f10x.h
  • FSMC_PCR3_TAR_1 : stm32f10x.h
  • FSMC_PCR3_TAR_2 : stm32f10x.h
  • FSMC_PCR3_TAR_3 : stm32f10x.h
  • FSMC_PCR3_TCLR : stm32f10x.h
  • FSMC_PCR3_TCLR_0 : stm32f10x.h
  • FSMC_PCR3_TCLR_1 : stm32f10x.h
  • FSMC_PCR3_TCLR_2 : stm32f10x.h
  • FSMC_PCR3_TCLR_3 : stm32f10x.h
  • FSMC_PCR4_ECCEN : stm32f10x.h
  • FSMC_PCR4_ECCPS : stm32f10x.h
  • FSMC_PCR4_ECCPS_0 : stm32f10x.h
  • FSMC_PCR4_ECCPS_1 : stm32f10x.h
  • FSMC_PCR4_ECCPS_2 : stm32f10x.h
  • FSMC_PCR4_PBKEN : stm32f10x.h
  • FSMC_PCR4_PTYP : stm32f10x.h
  • FSMC_PCR4_PWAITEN : stm32f10x.h
  • FSMC_PCR4_PWID : stm32f10x.h
  • FSMC_PCR4_PWID_0 : stm32f10x.h
  • FSMC_PCR4_PWID_1 : stm32f10x.h
  • FSMC_PCR4_TAR : stm32f10x.h
  • FSMC_PCR4_TAR_0 : stm32f10x.h
  • FSMC_PCR4_TAR_1 : stm32f10x.h
  • FSMC_PCR4_TAR_2 : stm32f10x.h
  • FSMC_PCR4_TAR_3 : stm32f10x.h
  • FSMC_PCR4_TCLR : stm32f10x.h
  • FSMC_PCR4_TCLR_0 : stm32f10x.h
  • FSMC_PCR4_TCLR_1 : stm32f10x.h
  • FSMC_PCR4_TCLR_2 : stm32f10x.h
  • FSMC_PCR4_TCLR_3 : stm32f10x.h
  • FSMC_PIO4_IOHIZ4 : stm32f10x.h
  • FSMC_PIO4_IOHIZ4_0 : stm32f10x.h
  • FSMC_PIO4_IOHIZ4_1 : stm32f10x.h
  • FSMC_PIO4_IOHIZ4_2 : stm32f10x.h
  • FSMC_PIO4_IOHIZ4_3 : stm32f10x.h
  • FSMC_PIO4_IOHIZ4_4 : stm32f10x.h
  • FSMC_PIO4_IOHIZ4_5 : stm32f10x.h
  • FSMC_PIO4_IOHIZ4_6 : stm32f10x.h
  • FSMC_PIO4_IOHIZ4_7 : stm32f10x.h
  • FSMC_PIO4_IOHOLD4 : stm32f10x.h
  • FSMC_PIO4_IOHOLD4_0 : stm32f10x.h
  • FSMC_PIO4_IOHOLD4_1 : stm32f10x.h
  • FSMC_PIO4_IOHOLD4_2 : stm32f10x.h
  • FSMC_PIO4_IOHOLD4_3 : stm32f10x.h
  • FSMC_PIO4_IOHOLD4_4 : stm32f10x.h
  • FSMC_PIO4_IOHOLD4_5 : stm32f10x.h
  • FSMC_PIO4_IOHOLD4_6 : stm32f10x.h
  • FSMC_PIO4_IOHOLD4_7 : stm32f10x.h
  • FSMC_PIO4_IOSET4 : stm32f10x.h
  • FSMC_PIO4_IOSET4_0 : stm32f10x.h
  • FSMC_PIO4_IOSET4_1 : stm32f10x.h
  • FSMC_PIO4_IOSET4_2 : stm32f10x.h
  • FSMC_PIO4_IOSET4_3 : stm32f10x.h
  • FSMC_PIO4_IOSET4_4 : stm32f10x.h
  • FSMC_PIO4_IOSET4_5 : stm32f10x.h
  • FSMC_PIO4_IOSET4_6 : stm32f10x.h
  • FSMC_PIO4_IOSET4_7 : stm32f10x.h
  • FSMC_PIO4_IOWAIT4 : stm32f10x.h
  • FSMC_PIO4_IOWAIT4_0 : stm32f10x.h
  • FSMC_PIO4_IOWAIT4_1 : stm32f10x.h
  • FSMC_PIO4_IOWAIT4_2 : stm32f10x.h
  • FSMC_PIO4_IOWAIT4_3 : stm32f10x.h
  • FSMC_PIO4_IOWAIT4_4 : stm32f10x.h
  • FSMC_PIO4_IOWAIT4_5 : stm32f10x.h
  • FSMC_PIO4_IOWAIT4_6 : stm32f10x.h
  • FSMC_PIO4_IOWAIT4_7 : stm32f10x.h
  • FSMC_PMEM2_MEMHIZ2 : stm32f10x.h
  • FSMC_PMEM2_MEMHIZ2_0 : stm32f10x.h
  • FSMC_PMEM2_MEMHIZ2_1 : stm32f10x.h
  • FSMC_PMEM2_MEMHIZ2_2 : stm32f10x.h
  • FSMC_PMEM2_MEMHIZ2_3 : stm32f10x.h
  • FSMC_PMEM2_MEMHIZ2_4 : stm32f10x.h
  • FSMC_PMEM2_MEMHIZ2_5 : stm32f10x.h
  • FSMC_PMEM2_MEMHIZ2_6 : stm32f10x.h
  • FSMC_PMEM2_MEMHIZ2_7 : stm32f10x.h
  • FSMC_PMEM2_MEMHOLD2 : stm32f10x.h
  • FSMC_PMEM2_MEMHOLD2_0 : stm32f10x.h
  • FSMC_PMEM2_MEMHOLD2_1 : stm32f10x.h
  • FSMC_PMEM2_MEMHOLD2_2 : stm32f10x.h
  • FSMC_PMEM2_MEMHOLD2_3 : stm32f10x.h
  • FSMC_PMEM2_MEMHOLD2_4 : stm32f10x.h
  • FSMC_PMEM2_MEMHOLD2_5 : stm32f10x.h
  • FSMC_PMEM2_MEMHOLD2_6 : stm32f10x.h
  • FSMC_PMEM2_MEMHOLD2_7 : stm32f10x.h
  • FSMC_PMEM2_MEMSET2 : stm32f10x.h
  • FSMC_PMEM2_MEMSET2_0 : stm32f10x.h
  • FSMC_PMEM2_MEMSET2_1 : stm32f10x.h
  • FSMC_PMEM2_MEMSET2_2 : stm32f10x.h
  • FSMC_PMEM2_MEMSET2_3 : stm32f10x.h
  • FSMC_PMEM2_MEMSET2_4 : stm32f10x.h
  • FSMC_PMEM2_MEMSET2_5 : stm32f10x.h
  • FSMC_PMEM2_MEMSET2_6 : stm32f10x.h
  • FSMC_PMEM2_MEMSET2_7 : stm32f10x.h
  • FSMC_PMEM2_MEMWAIT2 : stm32f10x.h
  • FSMC_PMEM2_MEMWAIT2_0 : stm32f10x.h
  • FSMC_PMEM2_MEMWAIT2_1 : stm32f10x.h
  • FSMC_PMEM2_MEMWAIT2_2 : stm32f10x.h
  • FSMC_PMEM2_MEMWAIT2_3 : stm32f10x.h
  • FSMC_PMEM2_MEMWAIT2_4 : stm32f10x.h
  • FSMC_PMEM2_MEMWAIT2_5 : stm32f10x.h
  • FSMC_PMEM2_MEMWAIT2_6 : stm32f10x.h
  • FSMC_PMEM2_MEMWAIT2_7 : stm32f10x.h
  • FSMC_PMEM3_MEMHIZ3 : stm32f10x.h
  • FSMC_PMEM3_MEMHIZ3_0 : stm32f10x.h
  • FSMC_PMEM3_MEMHIZ3_1 : stm32f10x.h
  • FSMC_PMEM3_MEMHIZ3_2 : stm32f10x.h
  • FSMC_PMEM3_MEMHIZ3_3 : stm32f10x.h
  • FSMC_PMEM3_MEMHIZ3_4 : stm32f10x.h
  • FSMC_PMEM3_MEMHIZ3_5 : stm32f10x.h
  • FSMC_PMEM3_MEMHIZ3_6 : stm32f10x.h
  • FSMC_PMEM3_MEMHIZ3_7 : stm32f10x.h
  • FSMC_PMEM3_MEMHOLD3 : stm32f10x.h
  • FSMC_PMEM3_MEMHOLD3_0 : stm32f10x.h
  • FSMC_PMEM3_MEMHOLD3_1 : stm32f10x.h
  • FSMC_PMEM3_MEMHOLD3_2 : stm32f10x.h
  • FSMC_PMEM3_MEMHOLD3_3 : stm32f10x.h
  • FSMC_PMEM3_MEMHOLD3_4 : stm32f10x.h
  • FSMC_PMEM3_MEMHOLD3_5 : stm32f10x.h
  • FSMC_PMEM3_MEMHOLD3_6 : stm32f10x.h
  • FSMC_PMEM3_MEMHOLD3_7 : stm32f10x.h
  • FSMC_PMEM3_MEMSET3 : stm32f10x.h
  • FSMC_PMEM3_MEMSET3_0 : stm32f10x.h
  • FSMC_PMEM3_MEMSET3_1 : stm32f10x.h
  • FSMC_PMEM3_MEMSET3_2 : stm32f10x.h
  • FSMC_PMEM3_MEMSET3_3 : stm32f10x.h
  • FSMC_PMEM3_MEMSET3_4 : stm32f10x.h
  • FSMC_PMEM3_MEMSET3_5 : stm32f10x.h
  • FSMC_PMEM3_MEMSET3_6 : stm32f10x.h
  • FSMC_PMEM3_MEMSET3_7 : stm32f10x.h
  • FSMC_PMEM3_MEMWAIT3 : stm32f10x.h
  • FSMC_PMEM3_MEMWAIT3_0 : stm32f10x.h
  • FSMC_PMEM3_MEMWAIT3_1 : stm32f10x.h
  • FSMC_PMEM3_MEMWAIT3_2 : stm32f10x.h
  • FSMC_PMEM3_MEMWAIT3_3 : stm32f10x.h
  • FSMC_PMEM3_MEMWAIT3_4 : stm32f10x.h
  • FSMC_PMEM3_MEMWAIT3_5 : stm32f10x.h
  • FSMC_PMEM3_MEMWAIT3_6 : stm32f10x.h
  • FSMC_PMEM3_MEMWAIT3_7 : stm32f10x.h
  • FSMC_PMEM4_MEMHIZ4 : stm32f10x.h
  • FSMC_PMEM4_MEMHIZ4_0 : stm32f10x.h
  • FSMC_PMEM4_MEMHIZ4_1 : stm32f10x.h
  • FSMC_PMEM4_MEMHIZ4_2 : stm32f10x.h
  • FSMC_PMEM4_MEMHIZ4_3 : stm32f10x.h
  • FSMC_PMEM4_MEMHIZ4_4 : stm32f10x.h
  • FSMC_PMEM4_MEMHIZ4_5 : stm32f10x.h
  • FSMC_PMEM4_MEMHIZ4_6 : stm32f10x.h
  • FSMC_PMEM4_MEMHIZ4_7 : stm32f10x.h
  • FSMC_PMEM4_MEMHOLD4 : stm32f10x.h
  • FSMC_PMEM4_MEMHOLD4_0 : stm32f10x.h
  • FSMC_PMEM4_MEMHOLD4_1 : stm32f10x.h
  • FSMC_PMEM4_MEMHOLD4_2 : stm32f10x.h
  • FSMC_PMEM4_MEMHOLD4_3 : stm32f10x.h
  • FSMC_PMEM4_MEMHOLD4_4 : stm32f10x.h
  • FSMC_PMEM4_MEMHOLD4_5 : stm32f10x.h
  • FSMC_PMEM4_MEMHOLD4_6 : stm32f10x.h
  • FSMC_PMEM4_MEMHOLD4_7 : stm32f10x.h
  • FSMC_PMEM4_MEMSET4 : stm32f10x.h
  • FSMC_PMEM4_MEMSET4_0 : stm32f10x.h
  • FSMC_PMEM4_MEMSET4_1 : stm32f10x.h
  • FSMC_PMEM4_MEMSET4_2 : stm32f10x.h
  • FSMC_PMEM4_MEMSET4_3 : stm32f10x.h
  • FSMC_PMEM4_MEMSET4_4 : stm32f10x.h
  • FSMC_PMEM4_MEMSET4_5 : stm32f10x.h
  • FSMC_PMEM4_MEMSET4_6 : stm32f10x.h
  • FSMC_PMEM4_MEMSET4_7 : stm32f10x.h
  • FSMC_PMEM4_MEMWAIT4 : stm32f10x.h
  • FSMC_PMEM4_MEMWAIT4_0 : stm32f10x.h
  • FSMC_PMEM4_MEMWAIT4_1 : stm32f10x.h
  • FSMC_PMEM4_MEMWAIT4_2 : stm32f10x.h
  • FSMC_PMEM4_MEMWAIT4_3 : stm32f10x.h
  • FSMC_PMEM4_MEMWAIT4_4 : stm32f10x.h
  • FSMC_PMEM4_MEMWAIT4_5 : stm32f10x.h
  • FSMC_PMEM4_MEMWAIT4_6 : stm32f10x.h
  • FSMC_PMEM4_MEMWAIT4_7 : stm32f10x.h
  • FSMC_R_BASE : stm32f10x.h
  • FSMC_SR2_FEMPT : stm32f10x.h
  • FSMC_SR2_IFEN : stm32f10x.h
  • FSMC_SR2_IFS : stm32f10x.h
  • FSMC_SR2_ILEN : stm32f10x.h
  • FSMC_SR2_ILS : stm32f10x.h
  • FSMC_SR2_IREN : stm32f10x.h
  • FSMC_SR2_IRS : stm32f10x.h
  • FSMC_SR3_FEMPT : stm32f10x.h
  • FSMC_SR3_IFEN : stm32f10x.h
  • FSMC_SR3_IFS : stm32f10x.h
  • FSMC_SR3_ILEN : stm32f10x.h
  • FSMC_SR3_ILS : stm32f10x.h
  • FSMC_SR3_IREN : stm32f10x.h
  • FSMC_SR3_IRS : stm32f10x.h
  • FSMC_SR4_FEMPT : stm32f10x.h
  • FSMC_SR4_IFEN : stm32f10x.h
  • FSMC_SR4_IFS : stm32f10x.h
  • FSMC_SR4_ILEN : stm32f10x.h
  • FSMC_SR4_ILS : stm32f10x.h
  • FSMC_SR4_IREN : stm32f10x.h
  • FSMC_SR4_IRS : stm32f10x.h
  • FSMC_Waitfeature_Disable : stm32f10x_fsmc.h
  • FSMC_Waitfeature_Enable : stm32f10x_fsmc.h
  • FSMC_WaitSignal_Disable : stm32f10x_fsmc.h
  • FSMC_WaitSignal_Enable : stm32f10x_fsmc.h
  • FSMC_WaitSignalActive_BeforeWaitState : stm32f10x_fsmc.h
  • FSMC_WaitSignalActive_DuringWaitState : stm32f10x_fsmc.h
  • FSMC_WaitSignalPolarity_High : stm32f10x_fsmc.h
  • FSMC_WaitSignalPolarity_Low : stm32f10x_fsmc.h
  • FSMC_WrapMode_Disable : stm32f10x_fsmc.h
  • FSMC_WrapMode_Enable : stm32f10x_fsmc.h
  • FSMC_WriteBurst_Disable : stm32f10x_fsmc.h
  • FSMC_WriteBurst_Enable : stm32f10x_fsmc.h
  • FSMC_WriteOperation_Disable : stm32f10x_fsmc.h
  • FSMC_WriteOperation_Enable : stm32f10x_fsmc.h


STM32F10x Standard Peripherals Firmware Library: Globals

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- g -

  • GPIO_BRR_BR0 : stm32f10x.h
  • GPIO_BRR_BR1 : stm32f10x.h
  • GPIO_BRR_BR10 : stm32f10x.h
  • GPIO_BRR_BR11 : stm32f10x.h
  • GPIO_BRR_BR12 : stm32f10x.h
  • GPIO_BRR_BR13 : stm32f10x.h
  • GPIO_BRR_BR14 : stm32f10x.h
  • GPIO_BRR_BR15 : stm32f10x.h
  • GPIO_BRR_BR2 : stm32f10x.h
  • GPIO_BRR_BR3 : stm32f10x.h
  • GPIO_BRR_BR4 : stm32f10x.h
  • GPIO_BRR_BR5 : stm32f10x.h
  • GPIO_BRR_BR6 : stm32f10x.h
  • GPIO_BRR_BR7 : stm32f10x.h
  • GPIO_BRR_BR8 : stm32f10x.h
  • GPIO_BRR_BR9 : stm32f10x.h
  • GPIO_BSRR_BR0 : stm32f10x.h
  • GPIO_BSRR_BR1 : stm32f10x.h
  • GPIO_BSRR_BR10 : stm32f10x.h
  • GPIO_BSRR_BR11 : stm32f10x.h
  • GPIO_BSRR_BR12 : stm32f10x.h
  • GPIO_BSRR_BR13 : stm32f10x.h
  • GPIO_BSRR_BR14 : stm32f10x.h
  • GPIO_BSRR_BR15 : stm32f10x.h
  • GPIO_BSRR_BR2 : stm32f10x.h
  • GPIO_BSRR_BR3 : stm32f10x.h
  • GPIO_BSRR_BR4 : stm32f10x.h
  • GPIO_BSRR_BR5 : stm32f10x.h
  • GPIO_BSRR_BR6 : stm32f10x.h
  • GPIO_BSRR_BR7 : stm32f10x.h
  • GPIO_BSRR_BR8 : stm32f10x.h
  • GPIO_BSRR_BR9 : stm32f10x.h
  • GPIO_BSRR_BS0 : stm32f10x.h
  • GPIO_BSRR_BS1 : stm32f10x.h
  • GPIO_BSRR_BS10 : stm32f10x.h
  • GPIO_BSRR_BS11 : stm32f10x.h
  • GPIO_BSRR_BS12 : stm32f10x.h
  • GPIO_BSRR_BS13 : stm32f10x.h
  • GPIO_BSRR_BS14 : stm32f10x.h
  • GPIO_BSRR_BS15 : stm32f10x.h
  • GPIO_BSRR_BS2 : stm32f10x.h
  • GPIO_BSRR_BS3 : stm32f10x.h
  • GPIO_BSRR_BS4 : stm32f10x.h
  • GPIO_BSRR_BS5 : stm32f10x.h
  • GPIO_BSRR_BS6 : stm32f10x.h
  • GPIO_BSRR_BS7 : stm32f10x.h
  • GPIO_BSRR_BS8 : stm32f10x.h
  • GPIO_BSRR_BS9 : stm32f10x.h
  • GPIO_CAN : STM32F10x_StdPeriph_Examples/CAN/Networking/main.c
  • GPIO_CAN1 : CAN/Networking/platform_config.h
  • GPIO_CAN2 : CAN/Networking/platform_config.h
  • GPIO_CRH_CNF : stm32f10x.h
  • GPIO_CRH_CNF10 : stm32f10x.h
  • GPIO_CRH_CNF10_0 : stm32f10x.h
  • GPIO_CRH_CNF10_1 : stm32f10x.h
  • GPIO_CRH_CNF11 : stm32f10x.h
  • GPIO_CRH_CNF11_0 : stm32f10x.h
  • GPIO_CRH_CNF11_1 : stm32f10x.h
  • GPIO_CRH_CNF12 : stm32f10x.h
  • GPIO_CRH_CNF12_0 : stm32f10x.h
  • GPIO_CRH_CNF12_1 : stm32f10x.h
  • GPIO_CRH_CNF13 : stm32f10x.h
  • GPIO_CRH_CNF13_0 : stm32f10x.h
  • GPIO_CRH_CNF13_1 : stm32f10x.h
  • GPIO_CRH_CNF14 : stm32f10x.h
  • GPIO_CRH_CNF14_0 : stm32f10x.h
  • GPIO_CRH_CNF14_1 : stm32f10x.h
  • GPIO_CRH_CNF15 : stm32f10x.h
  • GPIO_CRH_CNF15_0 : stm32f10x.h
  • GPIO_CRH_CNF15_1 : stm32f10x.h
  • GPIO_CRH_CNF8 : stm32f10x.h
  • GPIO_CRH_CNF8_0 : stm32f10x.h
  • GPIO_CRH_CNF8_1 : stm32f10x.h
  • GPIO_CRH_CNF9 : stm32f10x.h
  • GPIO_CRH_CNF9_0 : stm32f10x.h
  • GPIO_CRH_CNF9_1 : stm32f10x.h
  • GPIO_CRH_MODE : stm32f10x.h
  • GPIO_CRH_MODE10 : stm32f10x.h
  • GPIO_CRH_MODE10_0 : stm32f10x.h
  • GPIO_CRH_MODE10_1 : stm32f10x.h
  • GPIO_CRH_MODE11 : stm32f10x.h
  • GPIO_CRH_MODE11_0 : stm32f10x.h
  • GPIO_CRH_MODE11_1 : stm32f10x.h
  • GPIO_CRH_MODE12 : stm32f10x.h
  • GPIO_CRH_MODE12_0 : stm32f10x.h
  • GPIO_CRH_MODE12_1 : stm32f10x.h
  • GPIO_CRH_MODE13 : stm32f10x.h
  • GPIO_CRH_MODE13_0 : stm32f10x.h
  • GPIO_CRH_MODE13_1 : stm32f10x.h
  • GPIO_CRH_MODE14 : stm32f10x.h
  • GPIO_CRH_MODE14_0 : stm32f10x.h
  • GPIO_CRH_MODE14_1 : stm32f10x.h
  • GPIO_CRH_MODE15 : stm32f10x.h
  • GPIO_CRH_MODE15_0 : stm32f10x.h
  • GPIO_CRH_MODE15_1 : stm32f10x.h
  • GPIO_CRH_MODE8 : stm32f10x.h
  • GPIO_CRH_MODE8_0 : stm32f10x.h
  • GPIO_CRH_MODE8_1 : stm32f10x.h
  • GPIO_CRH_MODE9 : stm32f10x.h
  • GPIO_CRH_MODE9_0 : stm32f10x.h
  • GPIO_CRH_MODE9_1 : stm32f10x.h
  • GPIO_CRL_CNF : stm32f10x.h
  • GPIO_CRL_CNF0 : stm32f10x.h
  • GPIO_CRL_CNF0_0 : stm32f10x.h
  • GPIO_CRL_CNF0_1 : stm32f10x.h
  • GPIO_CRL_CNF1 : stm32f10x.h
  • GPIO_CRL_CNF1_0 : stm32f10x.h
  • GPIO_CRL_CNF1_1 : stm32f10x.h
  • GPIO_CRL_CNF2 : stm32f10x.h
  • GPIO_CRL_CNF2_0 : stm32f10x.h
  • GPIO_CRL_CNF2_1 : stm32f10x.h
  • GPIO_CRL_CNF3 : stm32f10x.h
  • GPIO_CRL_CNF3_0 : stm32f10x.h
  • GPIO_CRL_CNF3_1 : stm32f10x.h
  • GPIO_CRL_CNF4 : stm32f10x.h
  • GPIO_CRL_CNF4_0 : stm32f10x.h
  • GPIO_CRL_CNF4_1 : stm32f10x.h
  • GPIO_CRL_CNF5 : stm32f10x.h
  • GPIO_CRL_CNF5_0 : stm32f10x.h
  • GPIO_CRL_CNF5_1 : stm32f10x.h
  • GPIO_CRL_CNF6 : stm32f10x.h
  • GPIO_CRL_CNF6_0 : stm32f10x.h
  • GPIO_CRL_CNF6_1 : stm32f10x.h
  • GPIO_CRL_CNF7 : stm32f10x.h
  • GPIO_CRL_CNF7_0 : stm32f10x.h
  • GPIO_CRL_CNF7_1 : stm32f10x.h
  • GPIO_CRL_MODE : stm32f10x.h
  • GPIO_CRL_MODE0 : stm32f10x.h
  • GPIO_CRL_MODE0_0 : stm32f10x.h
  • GPIO_CRL_MODE0_1 : stm32f10x.h
  • GPIO_CRL_MODE1 : stm32f10x.h
  • GPIO_CRL_MODE1_0 : stm32f10x.h
  • GPIO_CRL_MODE1_1 : stm32f10x.h
  • GPIO_CRL_MODE2 : stm32f10x.h
  • GPIO_CRL_MODE2_0 : stm32f10x.h
  • GPIO_CRL_MODE2_1 : stm32f10x.h
  • GPIO_CRL_MODE3 : stm32f10x.h
  • GPIO_CRL_MODE3_0 : stm32f10x.h
  • GPIO_CRL_MODE3_1 : stm32f10x.h
  • GPIO_CRL_MODE4 : stm32f10x.h
  • GPIO_CRL_MODE4_0 : stm32f10x.h
  • GPIO_CRL_MODE4_1 : stm32f10x.h
  • GPIO_CRL_MODE5 : stm32f10x.h
  • GPIO_CRL_MODE5_0 : stm32f10x.h
  • GPIO_CRL_MODE5_1 : stm32f10x.h
  • GPIO_CRL_MODE6 : stm32f10x.h
  • GPIO_CRL_MODE6_0 : stm32f10x.h
  • GPIO_CRL_MODE6_1 : stm32f10x.h
  • GPIO_CRL_MODE7 : stm32f10x.h
  • GPIO_CRL_MODE7_0 : stm32f10x.h
  • GPIO_CRL_MODE7_1 : stm32f10x.h
  • GPIO_CTSPin : USART/HyperTerminal_HwFlowControl/platform_config.h
  • GPIO_ETH_MediaInterface_MII : stm32f10x_gpio.h
  • GPIO_ETH_MediaInterface_RMII : stm32f10x_gpio.h
  • GPIO_FullRemap_TIM1 : stm32f10x_gpio.h
  • GPIO_FullRemap_TIM2 : stm32f10x_gpio.h
  • GPIO_FullRemap_TIM3 : stm32f10x_gpio.h
  • GPIO_FullRemap_USART3 : stm32f10x_gpio.h
  • GPIO_IDR_IDR0 : stm32f10x.h
  • GPIO_IDR_IDR1 : stm32f10x.h
  • GPIO_IDR_IDR10 : stm32f10x.h
  • GPIO_IDR_IDR11 : stm32f10x.h
  • GPIO_IDR_IDR12 : stm32f10x.h
  • GPIO_IDR_IDR13 : stm32f10x.h
  • GPIO_IDR_IDR14 : stm32f10x.h
  • GPIO_IDR_IDR15 : stm32f10x.h
  • GPIO_IDR_IDR2 : stm32f10x.h
  • GPIO_IDR_IDR3 : stm32f10x.h
  • GPIO_IDR_IDR4 : stm32f10x.h
  • GPIO_IDR_IDR5 : stm32f10x.h
  • GPIO_IDR_IDR6 : stm32f10x.h
  • GPIO_IDR_IDR7 : stm32f10x.h
  • GPIO_IDR_IDR8 : stm32f10x.h
  • GPIO_IDR_IDR9 : stm32f10x.h
  • GPIO_LCKR_LCK0 : stm32f10x.h
  • GPIO_LCKR_LCK1 : stm32f10x.h
  • GPIO_LCKR_LCK10 : stm32f10x.h
  • GPIO_LCKR_LCK11 : stm32f10x.h
  • GPIO_LCKR_LCK12 : stm32f10x.h
  • GPIO_LCKR_LCK13 : stm32f10x.h
  • GPIO_LCKR_LCK14 : stm32f10x.h
  • GPIO_LCKR_LCK15 : stm32f10x.h
  • GPIO_LCKR_LCK2 : stm32f10x.h
  • GPIO_LCKR_LCK3 : stm32f10x.h
  • GPIO_LCKR_LCK4 : stm32f10x.h
  • GPIO_LCKR_LCK5 : stm32f10x.h
  • GPIO_LCKR_LCK6 : stm32f10x.h
  • GPIO_LCKR_LCK7 : stm32f10x.h
  • GPIO_LCKR_LCK8 : stm32f10x.h
  • GPIO_LCKR_LCK9 : stm32f10x.h
  • GPIO_LCKR_LCKK : stm32f10x.h
  • GPIO_ODR_ODR0 : stm32f10x.h
  • GPIO_ODR_ODR1 : stm32f10x.h
  • GPIO_ODR_ODR10 : stm32f10x.h
  • GPIO_ODR_ODR11 : stm32f10x.h
  • GPIO_ODR_ODR12 : stm32f10x.h
  • GPIO_ODR_ODR13 : stm32f10x.h
  • GPIO_ODR_ODR14 : stm32f10x.h
  • GPIO_ODR_ODR15 : stm32f10x.h
  • GPIO_ODR_ODR2 : stm32f10x.h
  • GPIO_ODR_ODR3 : stm32f10x.h
  • GPIO_ODR_ODR4 : stm32f10x.h
  • GPIO_ODR_ODR5 : stm32f10x.h
  • GPIO_ODR_ODR6 : stm32f10x.h
  • GPIO_ODR_ODR7 : stm32f10x.h
  • GPIO_ODR_ODR8 : stm32f10x.h
  • GPIO_ODR_ODR9 : stm32f10x.h
  • GPIO_PartialRemap1_TIM2 : stm32f10x_gpio.h
  • GPIO_PartialRemap2_TIM2 : stm32f10x_gpio.h
  • GPIO_PartialRemap_TIM1 : stm32f10x_gpio.h
  • GPIO_PartialRemap_TIM3 : stm32f10x_gpio.h
  • GPIO_PartialRemap_USART3 : stm32f10x_gpio.h
  • GPIO_Pin_0 : stm32f10x_gpio.h
  • GPIO_Pin_1 : stm32f10x_gpio.h
  • GPIO_Pin_10 : stm32f10x_gpio.h
  • GPIO_Pin_11 : stm32f10x_gpio.h
  • GPIO_Pin_12 : stm32f10x_gpio.h
  • GPIO_Pin_13 : stm32f10x_gpio.h
  • GPIO_Pin_14 : stm32f10x_gpio.h
  • GPIO_Pin_15 : stm32f10x_gpio.h
  • GPIO_Pin_2 : stm32f10x_gpio.h
  • GPIO_Pin_3 : stm32f10x_gpio.h
  • GPIO_Pin_4 : stm32f10x_gpio.h
  • GPIO_Pin_5 : stm32f10x_gpio.h
  • GPIO_Pin_6 : stm32f10x_gpio.h
  • GPIO_Pin_7 : stm32f10x_gpio.h
  • GPIO_Pin_8 : stm32f10x_gpio.h
  • GPIO_Pin_9 : stm32f10x_gpio.h
  • GPIO_Pin_All : stm32f10x_gpio.h
  • GPIO_Pin_CAN1_RX : CAN/Networking/platform_config.h
  • GPIO_Pin_CAN1_TX : CAN/Networking/platform_config.h
  • GPIO_Pin_CAN2_RX : CAN/Networking/platform_config.h
  • GPIO_Pin_CAN2_TX : CAN/Networking/platform_config.h
  • GPIO_Pin_CAN_RX : STM32F10x_StdPeriph_Examples/CAN/Networking/main.c
  • GPIO_Pin_CAN_TX : STM32F10x_StdPeriph_Examples/CAN/Networking/main.c
  • GPIO_PinSource0 : stm32f10x_gpio.h
  • GPIO_PinSource1 : stm32f10x_gpio.h
  • GPIO_PinSource10 : stm32f10x_gpio.h
  • GPIO_PinSource11 : stm32f10x_gpio.h
  • GPIO_PinSource12 : stm32f10x_gpio.h
  • GPIO_PinSource13 : stm32f10x_gpio.h
  • GPIO_PinSource14 : stm32f10x_gpio.h
  • GPIO_PinSource15 : stm32f10x_gpio.h
  • GPIO_PinSource2 : stm32f10x_gpio.h
  • GPIO_PinSource3 : stm32f10x_gpio.h
  • GPIO_PinSource4 : stm32f10x_gpio.h
  • GPIO_PinSource5 : stm32f10x_gpio.h
  • GPIO_PinSource6 : stm32f10x_gpio.h
  • GPIO_PinSource7 : stm32f10x_gpio.h
  • GPIO_PinSource8 : stm32f10x_gpio.h
  • GPIO_PinSource9 : stm32f10x_gpio.h
  • GPIO_PortSourceGPIOA : stm32f10x_gpio.h
  • GPIO_PortSourceGPIOB : stm32f10x_gpio.h
  • GPIO_PortSourceGPIOC : stm32f10x_gpio.h
  • GPIO_PortSourceGPIOD : stm32f10x_gpio.h
  • GPIO_PortSourceGPIOE : stm32f10x_gpio.h
  • GPIO_PortSourceGPIOF : stm32f10x_gpio.h
  • GPIO_PortSourceGPIOG : stm32f10x_gpio.h
  • GPIO_Remap1_CAN1 : stm32f10x_gpio.h
  • GPIO_Remap2_CAN1 : stm32f10x_gpio.h
  • GPIO_Remap_ADC1_ETRGINJ : stm32f10x_gpio.h
  • GPIO_Remap_ADC1_ETRGREG : stm32f10x_gpio.h
  • GPIO_Remap_ADC2_ETRGINJ : stm32f10x_gpio.h
  • GPIO_Remap_ADC2_ETRGREG : stm32f10x_gpio.h
  • GPIO_Remap_CAN2 : stm32f10x_gpio.h
  • GPIO_Remap_CEC : stm32f10x_gpio.h
  • GPIO_Remap_ETH : stm32f10x_gpio.h
  • GPIO_Remap_FSMC_NADV : stm32f10x_gpio.h
  • GPIO_Remap_I2C1 : stm32f10x_gpio.h
  • GPIO_Remap_MISC : stm32f10x_gpio.h
  • GPIO_Remap_PD01 : stm32f10x_gpio.h
  • GPIO_Remap_PTP_PPS : stm32f10x_gpio.h
  • GPIO_Remap_SPI1 : stm32f10x_gpio.h
  • GPIO_Remap_SPI3 : stm32f10x_gpio.h
  • GPIO_Remap_SWJ_Disable : stm32f10x_gpio.h
  • GPIO_Remap_SWJ_JTAGDisable : stm32f10x_gpio.h
  • GPIO_Remap_SWJ_NoJTRST : stm32f10x_gpio.h
  • GPIO_Remap_TIM10 : stm32f10x_gpio.h
  • GPIO_Remap_TIM11 : stm32f10x_gpio.h
  • GPIO_Remap_TIM12 : stm32f10x_gpio.h
  • GPIO_Remap_TIM13 : stm32f10x_gpio.h
  • GPIO_Remap_TIM14 : stm32f10x_gpio.h
  • GPIO_Remap_TIM15 : stm32f10x_gpio.h
  • GPIO_Remap_TIM16 : stm32f10x_gpio.h
  • GPIO_Remap_TIM17 : stm32f10x_gpio.h
  • GPIO_Remap_TIM1_DMA : stm32f10x_gpio.h
  • GPIO_Remap_TIM2ITR1_PTP_SOF : stm32f10x_gpio.h
  • GPIO_Remap_TIM4 : stm32f10x_gpio.h
  • GPIO_Remap_TIM5CH4_LSI : stm32f10x_gpio.h
  • GPIO_Remap_TIM67_DAC_DMA : stm32f10x_gpio.h
  • GPIO_Remap_TIM9 : stm32f10x_gpio.h
  • GPIO_Remap_USART1 : stm32f10x_gpio.h
  • GPIO_Remap_USART2 : stm32f10x_gpio.h
  • GPIO_Remapping_CAN : STM32F10x_StdPeriph_Examples/CAN/Networking/main.c
  • GPIO_Remapping_CAN1 : CAN/Networking/platform_config.h
  • GPIO_Remapping_CAN2 : CAN/Networking/platform_config.h
  • GPIO_RTSPin : USART/HyperTerminal_HwFlowControl/platform_config.h
  • GPIO_RxPin : USART/HyperTerminal_HwFlowControl/platform_config.h
  • GPIO_TxPin : USART/HyperTerminal_HwFlowControl/platform_config.h
  • GPIOA : stm32f10x.h
  • GPIOA_BASE : stm32f10x.h
  • GPIOB : stm32f10x.h
  • GPIOB_BASE : stm32f10x.h
  • GPIOC : stm32f10x.h
  • GPIOC_BASE : stm32f10x.h
  • GPIOD : stm32f10x.h
  • GPIOD_BASE : stm32f10x.h
  • GPIOE : stm32f10x.h
  • GPIOE_BASE : stm32f10x.h
  • GPIOF : stm32f10x.h
  • GPIOF_BASE : stm32f10x.h
  • GPIOG : stm32f10x.h
  • GPIOG_BASE : stm32f10x.h
  • GPIOx : USART/HyperTerminal_HwFlowControl/platform_config.h
  • Green : stm32_eval.h
  • Grey : stm32_eval.h
  • GTPR_LSB_Mask : stm32f10x_usart.c
  • GTPR_MSB_Mask : stm32f10x_usart.c


STM32F10x Standard Peripherals Firmware Library: Globals

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- h -

  • HDMI_CEC_AUDIOSYSTEM : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_CANNOTPROVIDE_SOURCE : stm32100e_eval_cec.h , stm32100b_eval_cec.h
  • HDMI_CEC_HPD_GPIO_CLK : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_HPD_GPIO_PORT : stm32100e_eval_cec.h , stm32100b_eval_cec.h
  • HDMI_CEC_HPD_HIGH : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_HPD_LOW : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_HPD_PIN : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_I2C : stm32100e_eval_cec.h , stm32100b_eval_cec.h
  • HDMI_CEC_I2C_CLK : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_I2C_CLOCK_SPEED : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_I2C_GPIO_CLK : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_I2C_GPIO_PORT : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_I2C_SCL_PIN : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_I2C_SDA_PIN : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_I2C_SLAVE_ADDRESS7 : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_INVALID_OPERAND : stm32100e_eval_cec.h , stm32100b_eval_cec.h
  • HDMI_CEC_LINE_GPIO_CLK : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_LINE_GPIO_PORT : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_LINE_PIN : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_NOT_CORRECT_MODETORESPOND : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_OPCODE_ABORT : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_OPCODE_ACTIVE_SOURCE : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_OPCODE_CEC_VERSION : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_OPCODE_CLEAR_ANALOGUE_TIMER : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_OPCODE_CLEAR_DIGITAL_TIMER : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_OPCODE_CLEAR_EXTERNAL_TIMER : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_OPCODE_DECK_CONTROL : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_OPCODE_DECK_STATUS : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_OPCODE_DEVICE_VENDOR_ID : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_OPCODE_FEATURE_ABORT : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_OPCODE_GET_CEC_VERSION : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_OPCODE_GET_MENU_LANGUAGE : stm32100e_eval_cec.h , stm32100b_eval_cec.h
  • HDMI_CEC_OPCODE_GIVE_AUDIO_STATUS : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_OPCODE_GIVE_DECK_STATUS : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_OPCODE_GIVE_DEVICE_POWER_STATUS : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_OPCODE_GIVE_DEVICE_VENDOR_ID : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_OPCODE_GIVE_OSD_NAME : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_OPCODE_GIVE_PHYSICAL_ADDRESS : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_OPCODE_GIVE_SYSTEM_AUDIO_MODE_STATUS : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_OPCODE_GIVE_TUNER_DEVICE_STATUS : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_OPCODE_IMAGE_VIEW_ON : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_OPCODE_INACTIVE_SOURCE : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_OPCODE_MENU_REQUEST : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_OPCODE_MENU_STATUS : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_OPCODE_PLAY : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_OPCODE_RECORD_OFF : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_OPCODE_RECORD_ON : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_OPCODE_RECORD_STATUS : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_OPCODE_RECORD_TV_SCREEN : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_OPCODE_REPORT_AUDIO_STATUS : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_OPCODE_REPORT_PHYSICAL_ADDRESS : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_OPCODE_REPORT_POWER_STATUS : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_OPCODE_REQUEST_ACTIVE_SOURCE : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_OPCODE_ROUTING_CHANGE : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_OPCODE_ROUTING_INFORMATION : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_OPCODE_SELECT_ANALOGUE_SERVICE : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_OPCODE_SELECT_DIGITAL_SERVICE : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_OPCODE_SET_ANALOGUE_TIMER : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_OPCODE_SET_AUDIO_RATE : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_OPCODE_SET_DIGITAL_TIMER : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_OPCODE_SET_EXTERNAL_TIMER : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_OPCODE_SET_MENU_LANGUAGE : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_OPCODE_SET_OSD_NAME : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_OPCODE_SET_OSD_STRING : stm32100e_eval_cec.h , stm32100b_eval_cec.h
  • HDMI_CEC_OPCODE_SET_STREAM_PATH : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_OPCODE_SET_SYSTEM_AUDIO_MODE : stm32100e_eval_cec.h , stm32100b_eval_cec.h
  • HDMI_CEC_OPCODE_SET_TIMER_PROGRAM_TITLE : stm32100e_eval_cec.h , stm32100b_eval_cec.h
  • HDMI_CEC_OPCODE_STANDBY : stm32100e_eval_cec.h , stm32100b_eval_cec.h
  • HDMI_CEC_OPCODE_SYSTEM_AUDIO_MODE_REQUEST : stm32100e_eval_cec.h , stm32100b_eval_cec.h
  • HDMI_CEC_OPCODE_SYSTEM_AUDIO_MODE_STATUS : stm32100e_eval_cec.h , stm32100b_eval_cec.h
  • HDMI_CEC_OPCODE_TEXT_VIEW_ON : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_OPCODE_TIMER_CLEARED_STATUS : stm32100e_eval_cec.h , stm32100b_eval_cec.h
  • HDMI_CEC_OPCODE_TIMER_STATUS : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_OPCODE_TUNER_DEVICE_STATUS : stm32100e_eval_cec.h , stm32100b_eval_cec.h
  • HDMI_CEC_OPCODE_TUNER_STEP_DECREMENT : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_OPCODE_TUNER_STEP_INCREMENT : stm32100e_eval_cec.h , stm32100b_eval_cec.h
  • HDMI_CEC_OPCODE_USER_CONTROL_PRESSED : stm32100e_eval_cec.h , stm32100b_eval_cec.h
  • HDMI_CEC_OPCODE_USER_CONTROL_RELEASED : stm32100e_eval_cec.h , stm32100b_eval_cec.h
  • HDMI_CEC_OPCODE_VENDOR_COMMAND : stm32100e_eval_cec.h , stm32100b_eval_cec.h
  • HDMI_CEC_OPCODE_VENDOR_COMMAND_WITH_ID : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_OPCODE_VENDOR_REMOTE_BUTTON_DOWN : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_OPCODE_VENDOR_REMOTE_BUTTON_UP : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_PLAYBACK : stm32100e_eval_cec.h , stm32100b_eval_cec.h
  • HDMI_CEC_RECORDING : stm32100e_eval_cec.h , stm32100b_eval_cec.h
  • HDMI_CEC_REFUSED : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_ROOT : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_TIMEOUT_VALUE : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_TUNER : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_TV : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_TX_MESSAGE_LENGTH_MAX : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_UNRECOGNIZED_OPCODE : stm32100e_eval_cec.h , stm32100b_eval_cec.h
  • HDMI_CEC_VERSION : stm32100e_eval_cec.h , stm32100b_eval_cec.h
  • HIST_LENGHT : STM32F10x_StdPeriph_Examples/USART/Smartcard/main.c
  • Horizontal : stm32_eval.h
  • HSE_STARTUP_TIMEOUT : stm32f10x.h
  • HSE_Value : stm32f10x.h
  • HSE_VALUE : stm32f10x.h
  • HSEStartUp_TimeOut : stm32f10x.h
  • HSI_Value : stm32f10x.h
  • HSI_VALUE : stm32f10x.h
  • HSION_BitNumber : stm32f10x_rcc.c


STM32F10x Standard Peripherals Firmware Library: Globals

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- i -

  • I2C1 : stm32f10x.h
  • I2C1_BASE : stm32f10x.h
  • I2C1_DR_Address : STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/main.c
  • I2C1_SLAVE_ADDRESS7 : STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/main.c
  • I2C2 : stm32f10x.h
  • I2C2_BASE : stm32f10x.h
  • I2C2_DR_Address : STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/main.c
  • I2C2_SLAVE_ADDRESS7 : STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/main.c
  • I2C_Ack_Disable : stm32f10x_i2c.h
  • I2C_Ack_Enable : stm32f10x_i2c.h
  • I2C_AcknowledgedAddress_10bit : stm32f10x_i2c.h
  • I2C_AcknowledgedAddress_7bit : stm32f10x_i2c.h
  • I2C_CCR_CCR : stm32f10x.h
  • I2C_CCR_DUTY : stm32f10x.h
  • I2C_CCR_FS : stm32f10x.h
  • I2C_CR1_ACK : stm32f10x.h
  • I2C_CR1_ALERT : stm32f10x.h
  • I2C_CR1_ENARP : stm32f10x.h
  • I2C_CR1_ENGC : stm32f10x.h
  • I2C_CR1_ENPEC : stm32f10x.h
  • I2C_CR1_NOSTRETCH : stm32f10x.h
  • I2C_CR1_PE : stm32f10x.h
  • I2C_CR1_PEC : stm32f10x.h
  • I2C_CR1_POS : stm32f10x.h
  • I2C_CR1_SMBTYPE : stm32f10x.h
  • I2C_CR1_SMBUS : stm32f10x.h
  • I2C_CR1_START : stm32f10x.h
  • I2C_CR1_STOP : stm32f10x.h
  • I2C_CR1_SWRST : stm32f10x.h
  • I2C_CR2_DMAEN : stm32f10x.h
  • I2C_CR2_FREQ : stm32f10x.h
  • I2C_CR2_FREQ_0 : stm32f10x.h
  • I2C_CR2_FREQ_1 : stm32f10x.h
  • I2C_CR2_FREQ_2 : stm32f10x.h
  • I2C_CR2_FREQ_3 : stm32f10x.h
  • I2C_CR2_FREQ_4 : stm32f10x.h
  • I2C_CR2_FREQ_5 : stm32f10x.h
  • I2C_CR2_ITBUFEN : stm32f10x.h
  • I2C_CR2_ITERREN : stm32f10x.h
  • I2C_CR2_ITEVTEN : stm32f10x.h
  • I2C_CR2_LAST : stm32f10x.h
  • I2C_Direction_Receiver : stm32f10x_i2c.h
  • I2C_Direction_Transmitter : stm32f10x_i2c.h
  • I2C_DR_DR : stm32f10x.h
  • I2C_DutyCycle_16_9 : stm32f10x_i2c.h
  • I2C_DutyCycle_2 : stm32f10x_i2c.h
  • I2C_EVENT_MASTER_BYTE_RECEIVED : stm32f10x_i2c.h
  • I2C_EVENT_MASTER_BYTE_TRANSMITTED : stm32f10x_i2c.h
  • I2C_EVENT_MASTER_BYTE_TRANSMITTING : stm32f10x_i2c.h
  • I2C_EVENT_MASTER_MODE_ADDRESS10 : stm32f10x_i2c.h
  • I2C_EVENT_MASTER_MODE_SELECT : stm32f10x_i2c.h
  • I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED : stm32f10x_i2c.h
  • I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED : stm32f10x_i2c.h
  • I2C_EVENT_SLAVE_ACK_FAILURE : stm32f10x_i2c.h
  • I2C_EVENT_SLAVE_BYTE_RECEIVED : stm32f10x_i2c.h
  • I2C_EVENT_SLAVE_BYTE_TRANSMITTED : stm32f10x_i2c.h
  • I2C_EVENT_SLAVE_BYTE_TRANSMITTING : stm32f10x_i2c.h
  • I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED : stm32f10x_i2c.h
  • I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED : stm32f10x_i2c.h
  • I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED : stm32f10x_i2c.h
  • I2C_EVENT_SLAVE_STOP_DETECTED : stm32f10x_i2c.h
  • I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED : stm32f10x_i2c.h
  • I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED : stm32f10x_i2c.h
  • I2C_FLAG_ADD10 : stm32f10x_i2c.h
  • I2C_FLAG_ADDR : stm32f10x_i2c.h
  • I2C_FLAG_AF : stm32f10x_i2c.h
  • I2C_FLAG_ARLO : stm32f10x_i2c.h
  • I2C_FLAG_BERR : stm32f10x_i2c.h
  • I2C_FLAG_BTF : stm32f10x_i2c.h
  • I2C_FLAG_BUSY : stm32f10x_i2c.h
  • I2C_FLAG_DUALF : stm32f10x_i2c.h
  • I2C_FLAG_GENCALL : stm32f10x_i2c.h
  • I2C_FLAG_MSL : stm32f10x_i2c.h
  • I2C_FLAG_OVR : stm32f10x_i2c.h
  • I2C_FLAG_PECERR : stm32f10x_i2c.h
  • I2C_FLAG_RXNE : stm32f10x_i2c.h
  • I2C_FLAG_SB : stm32f10x_i2c.h
  • I2C_FLAG_SMBALERT : stm32f10x_i2c.h
  • I2C_FLAG_SMBDEFAULT : stm32f10x_i2c.h
  • I2C_FLAG_SMBHOST : stm32f10x_i2c.h
  • I2C_FLAG_STOPF : stm32f10x_i2c.h
  • I2C_FLAG_TIMEOUT : stm32f10x_i2c.h
  • I2C_FLAG_TRA : stm32f10x_i2c.h
  • I2C_FLAG_TXE : stm32f10x_i2c.h
  • I2C_IT_ADD10 : stm32f10x_i2c.h
  • I2C_IT_ADDR : stm32f10x_i2c.h
  • I2C_IT_AF : stm32f10x_i2c.h
  • I2C_IT_ARLO : stm32f10x_i2c.h
  • I2C_IT_BERR : stm32f10x_i2c.h
  • I2C_IT_BTF : stm32f10x_i2c.h
  • I2C_IT_BUF : stm32f10x_i2c.h
  • I2C_IT_ERR : stm32f10x_i2c.h
  • I2C_IT_EVT : stm32f10x_i2c.h
  • I2C_IT_OVR : stm32f10x_i2c.h
  • I2C_IT_PECERR : stm32f10x_i2c.h
  • I2C_IT_RXNE : stm32f10x_i2c.h
  • I2C_IT_SB : stm32f10x_i2c.h
  • I2C_IT_SMBALERT : stm32f10x_i2c.h
  • I2C_IT_STOPF : stm32f10x_i2c.h
  • I2C_IT_TIMEOUT : stm32f10x_i2c.h
  • I2C_IT_TXE : stm32f10x_i2c.h
  • I2C_Mode_I2C : stm32f10x_i2c.h
  • I2C_Mode_SMBusDevice : stm32f10x_i2c.h
  • I2C_Mode_SMBusHost : stm32f10x_i2c.h
  • I2C_NACKPosition_Current : stm32f10x_i2c.h
  • I2C_NACKPosition_Next : stm32f10x_i2c.h
  • I2C_OAR1_ADD0 : stm32f10x.h
  • I2C_OAR1_ADD1 : stm32f10x.h
  • I2C_OAR1_ADD1_7 : stm32f10x.h
  • I2C_OAR1_ADD2 : stm32f10x.h
  • I2C_OAR1_ADD3 : stm32f10x.h
  • I2C_OAR1_ADD4 : stm32f10x.h
  • I2C_OAR1_ADD5 : stm32f10x.h
  • I2C_OAR1_ADD6 : stm32f10x.h
  • I2C_OAR1_ADD7 : stm32f10x.h
  • I2C_OAR1_ADD8 : stm32f10x.h
  • I2C_OAR1_ADD8_9 : stm32f10x.h
  • I2C_OAR1_ADD9 : stm32f10x.h
  • I2C_OAR1_ADDMODE : stm32f10x.h
  • I2C_OAR2_ADD2 : stm32f10x.h
  • I2C_OAR2_ENDUAL : stm32f10x.h
  • I2C_PECPosition_Current : stm32f10x_i2c.h
  • I2C_PECPosition_Next : stm32f10x_i2c.h
  • I2C_Register_CCR : stm32f10x_i2c.h
  • I2C_Register_CR1 : stm32f10x_i2c.h
  • I2C_Register_CR2 : stm32f10x_i2c.h
  • I2C_Register_DR : stm32f10x_i2c.h
  • I2C_Register_OAR1 : stm32f10x_i2c.h
  • I2C_Register_OAR2 : stm32f10x_i2c.h
  • I2C_Register_SR1 : stm32f10x_i2c.h
  • I2C_Register_SR2 : stm32f10x_i2c.h
  • I2C_Register_TRISE : stm32f10x_i2c.h
  • I2C_SLAVE_ADDRESS7 : stm32_eval_i2c_ee.h , stm32l152_eval_i2c_ee.h
  • I2C_SMBusAlert_High : stm32f10x_i2c.h
  • I2C_SMBusAlert_Low : stm32f10x_i2c.h
  • I2C_SPEED : stm32_eval_i2c_ee.h , stm32l152_eval_i2c_ee.h
  • I2C_SR1_ADD10 : stm32f10x.h
  • I2C_SR1_ADDR : stm32f10x.h
  • I2C_SR1_AF : stm32f10x.h
  • I2C_SR1_ARLO : stm32f10x.h
  • I2C_SR1_BERR : stm32f10x.h
  • I2C_SR1_BTF : stm32f10x.h
  • I2C_SR1_OVR : stm32f10x.h
  • I2C_SR1_PECERR : stm32f10x.h
  • I2C_SR1_RXNE : stm32f10x.h
  • I2C_SR1_SB : stm32f10x.h
  • I2C_SR1_SMBALERT : stm32f10x.h
  • I2C_SR1_STOPF : stm32f10x.h
  • I2C_SR1_TIMEOUT : stm32f10x.h
  • I2C_SR1_TXE : stm32f10x.h
  • I2C_SR2_BUSY : stm32f10x.h
  • I2C_SR2_DUALF : stm32f10x.h
  • I2C_SR2_GENCALL : stm32f10x.h
  • I2C_SR2_MSL : stm32f10x.h
  • I2C_SR2_PEC : stm32f10x.h
  • I2C_SR2_SMBDEFAULT : stm32f10x.h
  • I2C_SR2_SMBHOST : stm32f10x.h
  • I2C_SR2_TRA : stm32f10x.h
  • I2C_TIMEOUT : stm32_eval_i2c_tsensor.h
  • I2C_TRISE_TRISE : stm32f10x.h
  • I2S2_CLOCK_SRC : stm32f10x_spi.c
  • I2S3_CLOCK_SRC : stm32f10x_spi.c
  • I2S_AudioFreq_11k : stm32f10x_spi.h
  • I2S_AudioFreq_16k : stm32f10x_spi.h
  • I2S_AudioFreq_192k : stm32f10x_spi.h
  • I2S_AudioFreq_22k : stm32f10x_spi.h
  • I2S_AudioFreq_32k : stm32f10x_spi.h
  • I2S_AudioFreq_44k : stm32f10x_spi.h
  • I2S_AudioFreq_48k : stm32f10x_spi.h
  • I2S_AudioFreq_8k : stm32f10x_spi.h
  • I2S_AudioFreq_96k : stm32f10x_spi.h
  • I2S_AudioFreq_Default : stm32f10x_spi.h
  • I2S_CPOL_High : stm32f10x_spi.h
  • I2S_CPOL_Low : stm32f10x_spi.h
  • I2S_DataFormat_16b : stm32f10x_spi.h
  • I2S_DataFormat_16bextended : stm32f10x_spi.h
  • I2S_DataFormat_24b : stm32f10x_spi.h
  • I2S_DataFormat_32b : stm32f10x_spi.h
  • I2S_DIV_MASK : stm32f10x_spi.c
  • I2S_FLAG_CHSIDE : stm32f10x_spi.h
  • I2S_FLAG_UDR : stm32f10x_spi.h
  • I2S_IT_UDR : stm32f10x_spi.h
  • I2S_MCLKOutput_Disable : stm32f10x_spi.h
  • I2S_MCLKOutput_Enable : stm32f10x_spi.h
  • I2S_Mode_MasterRx : stm32f10x_spi.h
  • I2S_Mode_MasterTx : stm32f10x_spi.h
  • I2S_Mode_Select : stm32f10x_spi.c
  • I2S_Mode_SlaveRx : stm32f10x_spi.h
  • I2S_Mode_SlaveTx : stm32f10x_spi.h
  • I2S_MUL_MASK : stm32f10x_spi.c
  • I2S_Standard_LSB : stm32f10x_spi.h
  • I2S_Standard_MSB : stm32f10x_spi.h
  • I2S_Standard_PCMLong : stm32f10x_spi.h
  • I2S_Standard_PCMShort : stm32f10x_spi.h
  • I2S_Standard_Phillips : stm32f10x_spi.h
  • I2SCFGR_CLEAR_Mask : stm32f10x_spi.c
  • I2SCFGR_I2SE_Reset : stm32f10x_spi.c
  • I2SCFGR_I2SE_Set : stm32f10x_spi.c
  • IDCODE_DEVID_MASK : stm32f10x_dbgmcu.c
  • IE_BitNumber : stm32f10x_cec.c
  • INAK_TIMEOUT : stm32f10x_can.c
  • IO1_IN_ALL_PINS : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IO1_OUT_ALL_PINS : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IO2_IN_ALL_PINS : stm3210c_eval_ioe.h
  • IO2_OUT_ALL_PINS : stm3210c_eval_ioe.h
  • IO_IT_0 : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IO_IT_1 : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IO_IT_2 : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IO_IT_3 : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IO_IT_4 : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IO_IT_5 : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IO_IT_6 : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IO_IT_7 : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IO_Pin_0 : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IO_Pin_1 : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IO_Pin_2 : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IO_Pin_3 : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IO_Pin_4 : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IO_Pin_5 : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IO_Pin_6 : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IO_Pin_7 : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IO_Pin_ALL : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_1_ADDR : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_2_ADDR : stm3210c_eval_ioe.h
  • IOE_ADC_FCT : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_DMA : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_DMA_CLK : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_DMA_RX_CHANNEL : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_DMA_RX_TCFLAG : stm3210c_eval_ioe.h , stm32100e_eval_ioe.h
  • IOE_DMA_TX_CHANNEL : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_DMA_TX_TCFLAG : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_GIT_ADC : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_GIT_EN : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_GIT_FE : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_GIT_FF : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_GIT_FOV : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_GIT_FTH : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_GIT_GPIO : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_GIT_TEMP : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_GIT_TOUCH : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_I2C : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_I2C_CLK : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_I2C_DR : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_I2C_SCL_GPIO_CLK : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_I2C_SCL_GPIO_PORT : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_I2C_SCL_PIN : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_I2C_SDA_GPIO_CLK : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_I2C_SDA_GPIO_PORT : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_I2C_SDA_PIN : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_I2C_SPEED : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_INMEMS_IT : stm3210c_eval_ioe.h
  • IOE_INTERRUPT_MODE : I2C/IOExpander/main.h
  • IOE_IO_FCT : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_IT_EXTI_IRQn : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_IT_EXTI_LINE : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_IT_EXTI_PIN_SOURCE : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_IT_EXTI_PORT_SOURCE : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_IT_GPIO_CLK : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_IT_GPIO_PORT : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_IT_PIN : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_ITSRC_INMEMS : stm3210c_eval_ioe.h
  • IOE_ITSRC_JOYSTICK : stm3210c_eval_ioe.h
  • IOE_ITSRC_TEMPSENS : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_ITSRC_TSC : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_JOY_IT : stm3210c_eval_ioe.h
  • IOE_REG_ADC_CAPT : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_REG_ADC_CTRL1 : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_REG_ADC_CTRL2 : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_REG_ADC_DATA_CH0 : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_REG_ADC_DATA_CH1 : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_REG_ADC_DATA_CH2 : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_REG_ADC_DATA_CH3 : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_REG_ADC_DATA_CH4 : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_REG_ADC_DATA_CH5 : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_REG_ADC_DATA_CH6 : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_REG_ADC_DATA_CH7 : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_REG_ADC_INT_EN : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_REG_ADC_INT_STA : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_REG_CHP_ID : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_REG_FIFO_SIZE : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_REG_FIFO_STA : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_REG_FIFO_TH : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_REG_GPIO_AF : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_REG_GPIO_CLR_PIN : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_REG_GPIO_DIR : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_REG_GPIO_ED : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_REG_GPIO_FE : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_REG_GPIO_INT_EN : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_REG_GPIO_INT_STA : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_REG_GPIO_MP_STA : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_REG_GPIO_RE : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_REG_GPIO_SET_PIN : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_REG_ID_VER : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_REG_INT_CTRL : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_REG_INT_EN : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_REG_INT_STA : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_REG_SPI_CFG : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_REG_SYS_CTRL1 : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_REG_SYS_CTRL2 : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_REG_TEMP_CTRL : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_REG_TEMP_DATA : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_REG_TEMP_TH : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_REG_TSC_CFG : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_REG_TSC_CTRL : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_REG_TSC_DATA : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_REG_TSC_DATA_X : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_REG_TSC_DATA_XYZ : stm3210c_eval_ioe.h , stm32100e_eval_ioe.h
  • IOE_REG_TSC_DATA_Y : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_REG_TSC_DATA_Z : stm3210c_eval_ioe.h , stm32100e_eval_ioe.h
  • IOE_REG_TSC_FRACT_XYZ : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_REG_TSC_I_DRIVE : stm3210c_eval_ioe.h , stm32100e_eval_ioe.h
  • IOE_REG_TSC_SHIELD : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_REG_WDM_BL_X : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_REG_WDM_BL_Y : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_REG_WDM_TR_X : stm3210c_eval_ioe.h , stm32100e_eval_ioe.h
  • IOE_REG_WDM_TR_Y : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_TEMPSENS_FCT : stm3210c_eval_ioe.h , stm32100e_eval_ioe.h
  • IOE_TimeoutUserCallback : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_TS_FCT : stm3210c_eval_ioe.h , stm32100e_eval_ioe.h
  • IOE_TS_IT : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IS_ADC_ALL_PERIPH : stm32f10x_adc.h
  • IS_ADC_ANALOG_WATCHDOG : stm32f10x_adc.h
  • IS_ADC_CHANNEL : stm32f10x_adc.h
  • IS_ADC_CLEAR_FLAG : stm32f10x_adc.h
  • IS_ADC_DATA_ALIGN : stm32f10x_adc.h
  • IS_ADC_DMA_PERIPH : stm32f10x_adc.h
  • IS_ADC_EXT_INJEC_TRIG : stm32f10x_adc.h
  • IS_ADC_EXT_TRIG : stm32f10x_adc.h
  • IS_ADC_GET_FLAG : stm32f10x_adc.h
  • IS_ADC_GET_IT : stm32f10x_adc.h
  • IS_ADC_INJECTED_CHANNEL : stm32f10x_adc.h
  • IS_ADC_INJECTED_LENGTH : stm32f10x_adc.h
  • IS_ADC_INJECTED_RANK : stm32f10x_adc.h
  • IS_ADC_IT : stm32f10x_adc.h
  • IS_ADC_MODE : stm32f10x_adc.h
  • IS_ADC_OFFSET : stm32f10x_adc.h
  • IS_ADC_REGULAR_DISC_NUMBER : stm32f10x_adc.h
  • IS_ADC_REGULAR_LENGTH : stm32f10x_adc.h
  • IS_ADC_REGULAR_RANK : stm32f10x_adc.h
  • IS_ADC_SAMPLE_TIME : stm32f10x_adc.h
  • IS_ADC_THRESHOLD : stm32f10x_adc.h
  • IS_BKP_CALIBRATION_VALUE : stm32f10x_bkp.h
  • IS_BKP_DR : stm32f10x_bkp.h
  • IS_BKP_RTC_OUTPUT_SOURCE : stm32f10x_bkp.h
  • IS_BKP_TAMPER_PIN_LEVEL : stm32f10x_bkp.h
  • IS_CAN_ALL_PERIPH : stm32f10x_can.h
  • IS_CAN_BANKNUMBER : stm32f10x_can.h
  • IS_CAN_BS1 : stm32f10x_can.h
  • IS_CAN_BS2 : stm32f10x_can.h
  • IS_CAN_CLEAR_FLAG : stm32f10x_can.h
  • IS_CAN_CLEAR_IT : stm32f10x_can.h
  • IS_CAN_DLC : stm32f10x_can.h
  • IS_CAN_EXTID : stm32f10x_can.h
  • IS_CAN_FIFO : stm32f10x_can.h
  • IS_CAN_FILTER_FIFO : stm32f10x_can.h
  • IS_CAN_FILTER_MODE : stm32f10x_can.h
  • IS_CAN_FILTER_NUMBER : stm32f10x_can.h
  • IS_CAN_FILTER_SCALE : stm32f10x_can.h
  • IS_CAN_GET_FLAG : stm32f10x_can.h
  • IS_CAN_IDTYPE : stm32f10x_can.h
  • IS_CAN_IT : stm32f10x_can.h
  • IS_CAN_MODE : stm32f10x_can.h
  • IS_CAN_OPERATING_MODE : stm32f10x_can.h
  • IS_CAN_PRESCALER : stm32f10x_can.h
  • IS_CAN_RTR : stm32f10x_can.h
  • IS_CAN_SJW : stm32f10x_can.h
  • IS_CAN_STDID : stm32f10x_can.h
  • IS_CAN_TRANSMITMAILBOX : stm32f10x_can.h
  • IS_CEC_ADDRESS : stm32f10x_cec.h
  • IS_CEC_BIT_PERIOD_ERROR_MODE : stm32f10x_cec.h
  • IS_CEC_BIT_TIMING_ERROR_MODE : stm32f10x_cec.h
  • IS_CEC_CLEAR_FLAG : stm32f10x_cec.h
  • IS_CEC_GET_FLAG : stm32f10x_cec.h
  • IS_CEC_GET_IT : stm32f10x_cec.h
  • IS_CEC_PRESCALER : stm32f10x_cec.h
  • IS_DAC_ALIGN : stm32f10x_dac.h
  • IS_DAC_CHANNEL : stm32f10x_dac.h
  • IS_DAC_DATA : stm32f10x_dac.h
  • IS_DAC_GENERATE_WAVE : stm32f10x_dac.h
  • IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE : stm32f10x_dac.h
  • IS_DAC_OUTPUT_BUFFER_STATE : stm32f10x_dac.h
  • IS_DAC_TRIGGER : stm32f10x_dac.h
  • IS_DAC_WAVE : stm32f10x_dac.h
  • IS_DBGMCU_PERIPH : stm32f10x_dbgmcu.h
  • IS_DMA_ALL_PERIPH : stm32f10x_dma.h
  • IS_DMA_BUFFER_SIZE : stm32f10x_dma.h
  • IS_DMA_CLEAR_FLAG : stm32f10x_dma.h
  • IS_DMA_CLEAR_IT : stm32f10x_dma.h
  • IS_DMA_CONFIG_IT : stm32f10x_dma.h
  • IS_DMA_DIR : stm32f10x_dma.h
  • IS_DMA_GET_FLAG : stm32f10x_dma.h
  • IS_DMA_GET_IT : stm32f10x_dma.h
  • IS_DMA_M2M_STATE : stm32f10x_dma.h
  • IS_DMA_MEMORY_DATA_SIZE : stm32f10x_dma.h
  • IS_DMA_MEMORY_INC_STATE : stm32f10x_dma.h
  • IS_DMA_MODE : stm32f10x_dma.h
  • IS_DMA_PERIPHERAL_DATA_SIZE : stm32f10x_dma.h
  • IS_DMA_PERIPHERAL_INC_STATE : stm32f10x_dma.h
  • IS_DMA_PRIORITY : stm32f10x_dma.h
  • IS_EXTI_LINE : stm32f10x_exti.h
  • IS_EXTI_MODE : stm32f10x_exti.h
  • IS_EXTI_TRIGGER : stm32f10x_exti.h
  • IS_FLASH_ADDRESS : stm32f10x_flash.h
  • IS_FLASH_CLEAR_FLAG : stm32f10x_flash.h
  • IS_FLASH_GET_FLAG : stm32f10x_flash.h
  • IS_FLASH_HALFCYCLEACCESS_STATE : stm32f10x_flash.h
  • IS_FLASH_IT : stm32f10x_flash.h
  • IS_FLASH_LATENCY : stm32f10x_flash.h
  • IS_FLASH_PREFETCHBUFFER_STATE : stm32f10x_flash.h
  • IS_FLASH_WRPROT_PAGE : stm32f10x_flash.h
  • IS_FSMC_ACCESS_MODE : stm32f10x_fsmc.h
  • IS_FSMC_ADDRESS_HOLD_TIME : stm32f10x_fsmc.h
  • IS_FSMC_ADDRESS_SETUP_TIME : stm32f10x_fsmc.h
  • IS_FSMC_ASYNWAIT : stm32f10x_fsmc.h
  • IS_FSMC_BURSTMODE : stm32f10x_fsmc.h
  • IS_FSMC_CLEAR_FLAG : stm32f10x_fsmc.h
  • IS_FSMC_CLK_DIV : stm32f10x_fsmc.h
  • IS_FSMC_DATA_LATENCY : stm32f10x_fsmc.h
  • IS_FSMC_DATASETUP_TIME : stm32f10x_fsmc.h
  • IS_FSMC_ECC_STATE : stm32f10x_fsmc.h
  • IS_FSMC_ECCPAGE_SIZE : stm32f10x_fsmc.h
  • IS_FSMC_EXTENDED_MODE : stm32f10x_fsmc.h
  • IS_FSMC_GET_FLAG : stm32f10x_fsmc.h
  • IS_FSMC_GET_IT : stm32f10x_fsmc.h
  • IS_FSMC_GETFLAG_BANK : stm32f10x_fsmc.h
  • IS_FSMC_HIZ_TIME : stm32f10x_fsmc.h
  • IS_FSMC_HOLD_TIME : stm32f10x_fsmc.h
  • IS_FSMC_IT : stm32f10x_fsmc.h
  • IS_FSMC_IT_BANK : stm32f10x_fsmc.h
  • IS_FSMC_MEMORY : stm32f10x_fsmc.h
  • IS_FSMC_MEMORY_WIDTH : stm32f10x_fsmc.h
  • IS_FSMC_MUX : stm32f10x_fsmc.h
  • IS_FSMC_NAND_BANK : stm32f10x_fsmc.h
  • IS_FSMC_NORSRAM_BANK : stm32f10x_fsmc.h
  • IS_FSMC_SETUP_TIME : stm32f10x_fsmc.h
  • IS_FSMC_TAR_TIME : stm32f10x_fsmc.h
  • IS_FSMC_TCLR_TIME : stm32f10x_fsmc.h
  • IS_FSMC_TURNAROUND_TIME : stm32f10x_fsmc.h
  • IS_FSMC_WAIT_FEATURE : stm32f10x_fsmc.h
  • IS_FSMC_WAIT_POLARITY : stm32f10x_fsmc.h
  • IS_FSMC_WAIT_SIGNAL_ACTIVE : stm32f10x_fsmc.h
  • IS_FSMC_WAIT_TIME : stm32f10x_fsmc.h
  • IS_FSMC_WAITE_SIGNAL : stm32f10x_fsmc.h
  • IS_FSMC_WRAP_MODE : stm32f10x_fsmc.h
  • IS_FSMC_WRITE_BURST : stm32f10x_fsmc.h
  • IS_FSMC_WRITE_OPERATION : stm32f10x_fsmc.h
  • IS_FUNCTIONAL_STATE : stm32f10x.h
  • IS_GET_EXTI_LINE : stm32f10x_exti.h
  • IS_GET_GPIO_PIN : stm32f10x_gpio.h
  • IS_GPIO_ALL_PERIPH : stm32f10x_gpio.h
  • IS_GPIO_BIT_ACTION : stm32f10x_gpio.h
  • IS_GPIO_ETH_MEDIA_INTERFACE : stm32f10x_gpio.h
  • IS_GPIO_EVENTOUT_PORT_SOURCE : stm32f10x_gpio.h
  • IS_GPIO_EXTI_PORT_SOURCE : stm32f10x_gpio.h
  • IS_GPIO_MODE : stm32f10x_gpio.h
  • IS_GPIO_PIN : stm32f10x_gpio.h
  • IS_GPIO_PIN_SOURCE : stm32f10x_gpio.h
  • IS_GPIO_REMAP : stm32f10x_gpio.h
  • IS_GPIO_SPEED : stm32f10x_gpio.h
  • IS_I2C_ACK_STATE : stm32f10x_i2c.h
  • IS_I2C_ACKNOWLEDGE_ADDRESS : stm32f10x_i2c.h
  • IS_I2C_ALL_PERIPH : stm32f10x_i2c.h
  • IS_I2C_CLEAR_FLAG : stm32f10x_i2c.h
  • IS_I2C_CLEAR_IT : stm32f10x_i2c.h
  • IS_I2C_CLOCK_SPEED : stm32f10x_i2c.h
  • IS_I2C_CONFIG_IT : stm32f10x_i2c.h
  • IS_I2C_DIRECTION : stm32f10x_i2c.h
  • IS_I2C_DUTY_CYCLE : stm32f10x_i2c.h
  • IS_I2C_EVENT : stm32f10x_i2c.h
  • IS_I2C_GET_FLAG : stm32f10x_i2c.h
  • IS_I2C_GET_IT : stm32f10x_i2c.h
  • IS_I2C_MODE : stm32f10x_i2c.h
  • IS_I2C_NACK_POSITION : stm32f10x_i2c.h
  • IS_I2C_OWN_ADDRESS1 : stm32f10x_i2c.h
  • IS_I2C_PEC_POSITION : stm32f10x_i2c.h
  • IS_I2C_REGISTER : stm32f10x_i2c.h
  • IS_I2C_SMBUS_ALERT : stm32f10x_i2c.h
  • IS_I2S_AUDIO_FREQ : stm32f10x_spi.h
  • IS_I2S_CPOL : stm32f10x_spi.h
  • IS_I2S_DATA_FORMAT : stm32f10x_spi.h
  • IS_I2S_MCLK_OUTPUT : stm32f10x_spi.h
  • IS_I2S_MODE : stm32f10x_spi.h
  • IS_I2S_STANDARD : stm32f10x_spi.h
  • IS_IWDG_FLAG : stm32f10x_iwdg.h
  • IS_IWDG_PRESCALER : stm32f10x_iwdg.h
  • IS_IWDG_RELOAD : stm32f10x_iwdg.h
  • IS_IWDG_WRITE_ACCESS : stm32f10x_iwdg.h
  • IS_NVIC_LP : misc.h
  • IS_NVIC_OFFSET : misc.h
  • IS_NVIC_PREEMPTION_PRIORITY : misc.h
  • IS_NVIC_PRIORITY_GROUP : misc.h
  • IS_NVIC_SUB_PRIORITY : misc.h
  • IS_NVIC_VECTTAB : misc.h
  • IS_OB_DATA_ADDRESS : stm32f10x_flash.h
  • IS_OB_IWDG_SOURCE : stm32f10x_flash.h
  • IS_OB_STDBY_SOURCE : stm32f10x_flash.h
  • IS_OB_STOP_SOURCE : stm32f10x_flash.h
  • IS_PWR_CLEAR_FLAG : stm32f10x_pwr.h
  • IS_PWR_GET_FLAG : stm32f10x_pwr.h
  • IS_PWR_PVD_LEVEL : stm32f10x_pwr.h
  • IS_PWR_REGULATOR : stm32f10x_pwr.h
  • IS_PWR_STOP_ENTRY : stm32f10x_pwr.h
  • IS_RCC_ADCCLK : stm32f10x_rcc.h
  • IS_RCC_AHB_PERIPH : stm32f10x_rcc.h
  • IS_RCC_APB1_PERIPH : stm32f10x_rcc.h
  • IS_RCC_APB2_PERIPH : stm32f10x_rcc.h
  • IS_RCC_CALIBRATION_VALUE : stm32f10x_rcc.h
  • IS_RCC_CLEAR_IT : stm32f10x_rcc.h
  • IS_RCC_FLAG : stm32f10x_rcc.h
  • IS_RCC_GET_IT : stm32f10x_rcc.h
  • IS_RCC_HCLK : stm32f10x_rcc.h
  • IS_RCC_HSE : stm32f10x_rcc.h
  • IS_RCC_IT : stm32f10x_rcc.h
  • IS_RCC_LSE : stm32f10x_rcc.h
  • IS_RCC_MCO : stm32f10x_rcc.h
  • IS_RCC_PCLK : stm32f10x_rcc.h
  • IS_RCC_PLL_MUL : stm32f10x_rcc.h
  • IS_RCC_PLL_SOURCE : stm32f10x_rcc.h
  • IS_RCC_RTCCLK_SOURCE : stm32f10x_rcc.h
  • IS_RCC_SYSCLK_SOURCE : stm32f10x_rcc.h
  • IS_RCC_USBCLK_SOURCE : stm32f10x_rcc.h
  • IS_RTC_CLEAR_FLAG : stm32f10x_rtc.h
  • IS_RTC_GET_FLAG : stm32f10x_rtc.h
  • IS_RTC_GET_IT : stm32f10x_rtc.h
  • IS_RTC_IT : stm32f10x_rtc.h
  • IS_RTC_PRESCALER : stm32f10x_rtc.h
  • IS_SDIO_BLOCK_SIZE : stm32f10x_sdio.h
  • IS_SDIO_BUS_WIDE : stm32f10x_sdio.h
  • IS_SDIO_CLEAR_FLAG : stm32f10x_sdio.h
  • IS_SDIO_CLEAR_IT : stm32f10x_sdio.h
  • IS_SDIO_CLOCK_BYPASS : stm32f10x_sdio.h
  • IS_SDIO_CLOCK_EDGE : stm32f10x_sdio.h
  • IS_SDIO_CLOCK_POWER_SAVE : stm32f10x_sdio.h
  • IS_SDIO_CMD_INDEX : stm32f10x_sdio.h
  • IS_SDIO_CPSM : stm32f10x_sdio.h
  • IS_SDIO_DATA_LENGTH : stm32f10x_sdio.h
  • IS_SDIO_DPSM : stm32f10x_sdio.h
  • IS_SDIO_FLAG : stm32f10x_sdio.h
  • IS_SDIO_GET_IT : stm32f10x_sdio.h
  • IS_SDIO_HARDWARE_FLOW_CONTROL : stm32f10x_sdio.h
  • IS_SDIO_IT : stm32f10x_sdio.h
  • IS_SDIO_POWER_STATE : stm32f10x_sdio.h
  • IS_SDIO_READWAIT_MODE : stm32f10x_sdio.h
  • IS_SDIO_RESP : stm32f10x_sdio.h
  • IS_SDIO_RESPONSE : stm32f10x_sdio.h
  • IS_SDIO_TRANSFER_DIR : stm32f10x_sdio.h
  • IS_SDIO_TRANSFER_MODE : stm32f10x_sdio.h
  • IS_SDIO_WAIT : stm32f10x_sdio.h
  • IS_SPI_23_PERIPH : stm32f10x_spi.h
  • IS_SPI_ALL_PERIPH : stm32f10x_spi.h
  • IS_SPI_BAUDRATE_PRESCALER : stm32f10x_spi.h
  • IS_SPI_CPHA : stm32f10x_spi.h
  • IS_SPI_CPOL : stm32f10x_spi.h
  • IS_SPI_CRC : stm32f10x_spi.h
  • IS_SPI_CRC_POLYNOMIAL : stm32f10x_spi.h
  • IS_SPI_DATASIZE : stm32f10x_spi.h
  • IS_SPI_DIRECTION : stm32f10x_spi.h
  • IS_SPI_DIRECTION_MODE : stm32f10x_spi.h
  • IS_SPI_FIRST_BIT : stm32f10x_spi.h
  • IS_SPI_I2S_CLEAR_FLAG : stm32f10x_spi.h
  • IS_SPI_I2S_CLEAR_IT : stm32f10x_spi.h
  • IS_SPI_I2S_CONFIG_IT : stm32f10x_spi.h
  • IS_SPI_I2S_DMAREQ : stm32f10x_spi.h
  • IS_SPI_I2S_GET_FLAG : stm32f10x_spi.h
  • IS_SPI_I2S_GET_IT : stm32f10x_spi.h
  • IS_SPI_MODE : stm32f10x_spi.h
  • IS_SPI_NSS : stm32f10x_spi.h
  • IS_SPI_NSS_INTERNAL : stm32f10x_spi.h
  • IS_SYSTICK_CLK_SOURCE : misc.h
  • IS_TIM_ALL_PERIPH : stm32f10x_tim.h
  • IS_TIM_AUTOMATIC_OUTPUT_STATE : stm32f10x_tim.h
  • IS_TIM_BREAK_POLARITY : stm32f10x_tim.h
  • IS_TIM_BREAK_STATE : stm32f10x_tim.h
  • IS_TIM_CCX : stm32f10x_tim.h
  • IS_TIM_CCXN : stm32f10x_tim.h
  • IS_TIM_CHANNEL : stm32f10x_tim.h
  • IS_TIM_CKD_DIV : stm32f10x_tim.h
  • IS_TIM_CLEAR_FLAG : stm32f10x_tim.h
  • IS_TIM_COMPLEMENTARY_CHANNEL : stm32f10x_tim.h
  • IS_TIM_COUNTER_MODE : stm32f10x_tim.h
  • IS_TIM_DMA_BASE : stm32f10x_tim.h
  • IS_TIM_DMA_LENGTH : stm32f10x_tim.h
  • IS_TIM_DMA_SOURCE : stm32f10x_tim.h
  • IS_TIM_ENCODER_MODE : stm32f10x_tim.h
  • IS_TIM_EVENT_SOURCE : stm32f10x_tim.h
  • IS_TIM_EXT_FILTER : stm32f10x_tim.h
  • IS_TIM_EXT_POLARITY : stm32f10x_tim.h
  • IS_TIM_EXT_PRESCALER : stm32f10x_tim.h
  • IS_TIM_FORCED_ACTION : stm32f10x_tim.h
  • IS_TIM_GET_FLAG : stm32f10x_tim.h
  • IS_TIM_GET_IT : stm32f10x_tim.h
  • IS_TIM_IC_FILTER : stm32f10x_tim.h
  • IS_TIM_IC_POLARITY : stm32f10x_tim.h
  • IS_TIM_IC_POLARITY_LITE : stm32f10x_tim.h
  • IS_TIM_IC_PRESCALER : stm32f10x_tim.h
  • IS_TIM_IC_SELECTION : stm32f10x_tim.h
  • IS_TIM_INTERNAL_TRIGGER_SELECTION : stm32f10x_tim.h
  • IS_TIM_IT : stm32f10x_tim.h
  • IS_TIM_LIST1_PERIPH : stm32f10x_tim.h
  • IS_TIM_LIST2_PERIPH : stm32f10x_tim.h
  • IS_TIM_LIST3_PERIPH : stm32f10x_tim.h
  • IS_TIM_LIST4_PERIPH : stm32f10x_tim.h
  • IS_TIM_LIST5_PERIPH : stm32f10x_tim.h
  • IS_TIM_LIST6_PERIPH : stm32f10x_tim.h
  • IS_TIM_LIST7_PERIPH : stm32f10x_tim.h
  • IS_TIM_LIST8_PERIPH : stm32f10x_tim.h
  • IS_TIM_LIST9_PERIPH : stm32f10x_tim.h
  • IS_TIM_LOCK_LEVEL : stm32f10x_tim.h
  • IS_TIM_MSM_STATE : stm32f10x_tim.h
  • IS_TIM_OC_MODE : stm32f10x_tim.h
  • IS_TIM_OC_POLARITY : stm32f10x_tim.h
  • IS_TIM_OCCLEAR_STATE : stm32f10x_tim.h
  • IS_TIM_OCFAST_STATE : stm32f10x_tim.h
  • IS_TIM_OCIDLE_STATE : stm32f10x_tim.h
  • IS_TIM_OCM : stm32f10x_tim.h
  • IS_TIM_OCN_POLARITY : stm32f10x_tim.h
  • IS_TIM_OCNIDLE_STATE : stm32f10x_tim.h
  • IS_TIM_OCPRELOAD_STATE : stm32f10x_tim.h
  • IS_TIM_OPM_MODE : stm32f10x_tim.h
  • IS_TIM_OSSI_STATE : stm32f10x_tim.h
  • IS_TIM_OSSR_STATE : stm32f10x_tim.h
  • IS_TIM_OUTPUT_STATE : stm32f10x_tim.h
  • IS_TIM_OUTPUTN_STATE : stm32f10x_tim.h
  • IS_TIM_PRESCALER_RELOAD : stm32f10x_tim.h
  • IS_TIM_PWMI_CHANNEL : stm32f10x_tim.h
  • IS_TIM_SLAVE_MODE : stm32f10x_tim.h
  • IS_TIM_TIXCLK_SOURCE : stm32f10x_tim.h
  • IS_TIM_TRGO_SOURCE : stm32f10x_tim.h
  • IS_TIM_TRIGGER_SELECTION : stm32f10x_tim.h
  • IS_TIM_UPDATE_SOURCE : stm32f10x_tim.h
  • IS_USART_1234_PERIPH : stm32f10x_usart.h
  • IS_USART_123_PERIPH : stm32f10x_usart.h
  • IS_USART_ADDRESS : stm32f10x_usart.h
  • IS_USART_ALL_PERIPH : stm32f10x_usart.h
  • IS_USART_BAUDRATE : stm32f10x_usart.h
  • IS_USART_CLEAR_FLAG : stm32f10x_usart.h
  • IS_USART_CLEAR_IT : stm32f10x_usart.h
  • IS_USART_CLOCK : stm32f10x_usart.h
  • IS_USART_CONFIG_IT : stm32f10x_usart.h
  • IS_USART_CPHA : stm32f10x_usart.h
  • IS_USART_CPOL : stm32f10x_usart.h
  • IS_USART_DATA : stm32f10x_usart.h
  • IS_USART_DMAREQ : stm32f10x_usart.h
  • IS_USART_FLAG : stm32f10x_usart.h
  • IS_USART_GET_IT : stm32f10x_usart.h
  • IS_USART_HARDWARE_FLOW_CONTROL : stm32f10x_usart.h
  • IS_USART_IRDA_MODE : stm32f10x_usart.h
  • IS_USART_LASTBIT : stm32f10x_usart.h
  • IS_USART_LIN_BREAK_DETECT_LENGTH : stm32f10x_usart.h
  • IS_USART_MODE : stm32f10x_usart.h
  • IS_USART_PARITY : stm32f10x_usart.h
  • IS_USART_PERIPH_FLAG : stm32f10x_usart.h
  • IS_USART_STOPBITS : stm32f10x_usart.h
  • IS_USART_WAKEUP : stm32f10x_usart.h
  • IS_USART_WORD_LENGTH : stm32f10x_usart.h
  • IS_WWDG_COUNTER : stm32f10x_wwdg.h
  • IS_WWDG_PRESCALER : stm32f10x_wwdg.h
  • IS_WWDG_WINDOW_VALUE : stm32f10x_wwdg.h
  • IT_Mask : stm32f10x_usart.c
  • ITEN_Mask : stm32f10x_i2c.c
  • IWDG : stm32f10x.h
  • IWDG_BASE : stm32f10x.h
  • IWDG_FLAG_PVU : stm32f10x_iwdg.h
  • IWDG_FLAG_RVU : stm32f10x_iwdg.h
  • IWDG_KR_KEY : stm32f10x.h
  • IWDG_PR_PR : stm32f10x.h
  • IWDG_PR_PR_0 : stm32f10x.h
  • IWDG_PR_PR_1 : stm32f10x.h
  • IWDG_PR_PR_2 : stm32f10x.h
  • IWDG_Prescaler_128 : stm32f10x_iwdg.h
  • IWDG_Prescaler_16 : stm32f10x_iwdg.h
  • IWDG_Prescaler_256 : stm32f10x_iwdg.h
  • IWDG_Prescaler_32 : stm32f10x_iwdg.h
  • IWDG_Prescaler_4 : stm32f10x_iwdg.h
  • IWDG_Prescaler_64 : stm32f10x_iwdg.h
  • IWDG_Prescaler_8 : stm32f10x_iwdg.h
  • IWDG_RLR_RL : stm32f10x.h
  • IWDG_SR_PVU : stm32f10x.h
  • IWDG_SR_RVU : stm32f10x.h
  • IWDG_WriteAccess_Disable : stm32f10x_iwdg.h
  • IWDG_WriteAccess_Enable : stm32f10x_iwdg.h


STM32F10x Standard Peripherals Firmware Library: Globals

  • File List
  • Globals
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- p -

  • PCR_ECCEN_Reset : stm32f10x_fsmc.c
  • PCR_ECCEN_Set : stm32f10x_fsmc.c
  • PCR_MemoryType_NAND : stm32f10x_fsmc.c
  • PCR_PBKEN_Reset : stm32f10x_fsmc.c
  • PCR_PBKEN_Set : stm32f10x_fsmc.c
  • PE_BitNumber : stm32f10x_cec.c
  • PERIPH_ADDRESS_START : CortexM3/MPU/main.h
  • PERIPH_BASE : stm32f10x.h
  • PERIPH_BB_BASE : stm32f10x.h
  • PERIPH_REGION_NUMBER : CortexM3/MPU/main.h
  • PERIPH_SIZE : CortexM3/MPU/main.h
  • PLLON_BitNumber : stm32f10x_rcc.c
  • Polarity_High : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • Polarity_Low : stm3210c_eval_ioe.h , stm32100e_eval_ioe.h
  • POLY_X : stm32100b_eval_lcd.c , stm32100e_eval_lcd.c , stm3210b_eval_lcd.c , stm3210c_eval_lcd.c , stm3210e_eval_lcd.c , stm32l152_eval_lcd.c
  • POLY_Y : stm32100b_eval_lcd.c , stm32100e_eval_lcd.c , stm3210b_eval_lcd.c , stm3210c_eval_lcd.c , stm3210e_eval_lcd.c , stm32l152_eval_lcd.c
  • portMPU_REGION_PRIVILEGED_READ_ONLY : CortexM3/MPU/main.h
  • portMPU_REGION_PRIVILEGED_READ_WRITE : CortexM3/MPU/main.h
  • portMPU_REGION_READ_ONLY : CortexM3/MPU/main.h
  • portMPU_REGION_READ_WRITE : CortexM3/MPU/main.h
  • PRLH_MSB_MASK : stm32f10x_rtc.c
  • Program_Timeout : stm3210e_eval_fsmc_nor.c
  • ProgramTimeout : stm32f10x_flash.c
  • PUTCHAR_PROTOTYPE : STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/main.c , STM32F10x_StdPeriph_Examples/RTC/Calendar/main.c , STM32F10x_StdPeriph_Examples/USART/Printf/main.c , STM32F10x_StdPeriph_Template/main.c
  • PVDE_BitNumber : stm32f10x_pwr.c
  • PWR : stm32f10x.h
  • PWR_BASE : stm32f10x.h
  • PWR_CR_CSBF : stm32f10x.h
  • PWR_CR_CWUF : stm32f10x.h
  • PWR_CR_DBP : stm32f10x.h
  • PWR_CR_LPDS : stm32f10x.h
  • PWR_CR_PDDS : stm32f10x.h
  • PWR_CR_PLS : stm32f10x.h
  • PWR_CR_PLS_0 : stm32f10x.h
  • PWR_CR_PLS_1 : stm32f10x.h
  • PWR_CR_PLS_2 : stm32f10x.h
  • PWR_CR_PLS_2V2 : stm32f10x.h
  • PWR_CR_PLS_2V3 : stm32f10x.h
  • PWR_CR_PLS_2V4 : stm32f10x.h
  • PWR_CR_PLS_2V5 : stm32f10x.h
  • PWR_CR_PLS_2V6 : stm32f10x.h
  • PWR_CR_PLS_2V7 : stm32f10x.h
  • PWR_CR_PLS_2V8 : stm32f10x.h
  • PWR_CR_PLS_2V9 : stm32f10x.h
  • PWR_CR_PVDE : stm32f10x.h
  • PWR_CSR_EWUP : stm32f10x.h
  • PWR_CSR_PVDO : stm32f10x.h
  • PWR_CSR_SBF : stm32f10x.h
  • PWR_CSR_WUF : stm32f10x.h
  • PWR_FLAG_PVDO : stm32f10x_pwr.h
  • PWR_FLAG_SB : stm32f10x_pwr.h
  • PWR_FLAG_WU : stm32f10x_pwr.h
  • PWR_OFFSET : stm32f10x_pwr.c
  • PWR_PVDLevel_2V2 : stm32f10x_pwr.h
  • PWR_PVDLevel_2V3 : stm32f10x_pwr.h
  • PWR_PVDLevel_2V4 : stm32f10x_pwr.h
  • PWR_PVDLevel_2V5 : stm32f10x_pwr.h
  • PWR_PVDLevel_2V6 : stm32f10x_pwr.h
  • PWR_PVDLevel_2V7 : stm32f10x_pwr.h
  • PWR_PVDLevel_2V8 : stm32f10x_pwr.h
  • PWR_PVDLevel_2V9 : stm32f10x_pwr.h
  • PWR_PWRCTRL_MASK : stm32f10x_sdio.c
  • PWR_Regulator_LowPower : stm32f10x_pwr.h
  • PWR_Regulator_ON : stm32f10x_pwr.h
  • PWR_STOPEntry_WFE : stm32f10x_pwr.h
  • PWR_STOPEntry_WFI : stm32f10x_pwr.h


STM32F10x Standard Peripherals Firmware Library: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
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  • Enumerations
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  • R64 : stm32_eval.h
  • R65 : stm32_eval.h
  • R66 : stm32_eval.h
  • R67 : stm32_eval.h
  • R68 : stm32_eval.h
  • R69 : stm32_eval.h
  • R7 : stm32_eval.h
  • R70 : stm32_eval.h
  • R71 : stm32_eval.h
  • R72 : stm32_eval.h
  • R73 : stm32_eval.h
  • R74 : stm32_eval.h
  • R75 : stm32_eval.h
  • R76 : stm32_eval.h
  • R77 : stm32_eval.h
  • R78 : stm32_eval.h
  • R79 : stm32_eval.h
  • R8 : stm32_eval.h
  • R80 : stm32_eval.h
  • R81 : stm32_eval.h
  • R82 : stm32_eval.h
  • R83 : stm32_eval.h
  • R9 : stm32_eval.h
  • R96 : stm32_eval.h
  • R97 : stm32_eval.h
  • RAM_ADDRESS_START : CortexM3/MPU/main.h
  • RAM_BASE : STM32F10x_StdPeriph_Examples/CortexM3/BitBand/main.c
  • RAM_BB_BASE : STM32F10x_StdPeriph_Examples/CortexM3/BitBand/main.c
  • RAM_REGION_NUMBER : CortexM3/MPU/main.h
  • RAM_SIZE : CortexM3/MPU/main.h
  • RCC : stm32f10x.h
  • RCC_AHBENR_CRCEN : stm32f10x.h
  • RCC_AHBENR_DMA1EN : stm32f10x.h
  • RCC_AHBENR_FLITFEN : stm32f10x.h
  • RCC_AHBENR_SRAMEN : stm32f10x.h
  • RCC_AHBPeriph_CRC : stm32f10x_rcc.h
  • RCC_AHBPeriph_DMA1 : stm32f10x_rcc.h
  • RCC_AHBPeriph_DMA2 : stm32f10x_rcc.h
  • RCC_AHBPeriph_FLITF : stm32f10x_rcc.h
  • RCC_AHBPeriph_FSMC : stm32f10x_rcc.h
  • RCC_AHBPeriph_SDIO : stm32f10x_rcc.h
  • RCC_AHBPeriph_SRAM : stm32f10x_rcc.h
  • RCC_APB1ENR_BKPEN : stm32f10x.h
  • RCC_APB1ENR_CAN1EN : stm32f10x.h
  • RCC_APB1ENR_I2C1EN : stm32f10x.h
  • RCC_APB1ENR_I2C2EN : stm32f10x.h
  • RCC_APB1ENR_PWREN : stm32f10x.h
  • RCC_APB1ENR_SPI2EN : stm32f10x.h
  • RCC_APB1ENR_TIM2EN : stm32f10x.h
  • RCC_APB1ENR_TIM3EN : stm32f10x.h
  • RCC_APB1ENR_TIM4EN : stm32f10x.h
  • RCC_APB1ENR_USART2EN : stm32f10x.h
  • RCC_APB1ENR_USART3EN : stm32f10x.h
  • RCC_APB1ENR_WWDGEN : stm32f10x.h
  • RCC_APB1Periph_BKP : stm32f10x_rcc.h
  • RCC_APB1Periph_CAN1 : stm32f10x_rcc.h
  • RCC_APB1Periph_CAN2 : stm32f10x_rcc.h
  • RCC_APB1Periph_CEC : stm32f10x_rcc.h
  • RCC_APB1Periph_DAC : stm32f10x_rcc.h
  • RCC_APB1Periph_I2C1 : stm32f10x_rcc.h
  • RCC_APB1Periph_I2C2 : stm32f10x_rcc.h
  • RCC_APB1Periph_PWR : stm32f10x_rcc.h
  • RCC_APB1Periph_SPI2 : stm32f10x_rcc.h
  • RCC_APB1Periph_SPI3 : stm32f10x_rcc.h
  • RCC_APB1Periph_TIM12 : stm32f10x_rcc.h
  • RCC_APB1Periph_TIM13 : stm32f10x_rcc.h
  • RCC_APB1Periph_TIM14 : stm32f10x_rcc.h
  • RCC_APB1Periph_TIM2 : stm32f10x_rcc.h
  • RCC_APB1Periph_TIM3 : stm32f10x_rcc.h
  • RCC_APB1Periph_TIM4 : stm32f10x_rcc.h
  • RCC_APB1Periph_TIM5 : stm32f10x_rcc.h
  • RCC_APB1Periph_TIM6 : stm32f10x_rcc.h
  • RCC_APB1Periph_TIM7 : stm32f10x_rcc.h
  • RCC_APB1Periph_UART4 : stm32f10x_rcc.h
  • RCC_APB1Periph_UART5 : stm32f10x_rcc.h
  • RCC_APB1Periph_USART2 : stm32f10x_rcc.h
  • RCC_APB1Periph_USART3 : stm32f10x_rcc.h
  • RCC_APB1Periph_USB : stm32f10x_rcc.h
  • RCC_APB1Periph_WWDG : stm32f10x_rcc.h
  • RCC_APB1RSTR_BKPRST : stm32f10x.h
  • RCC_APB1RSTR_CAN1RST : stm32f10x.h
  • RCC_APB1RSTR_I2C1RST : stm32f10x.h
  • RCC_APB1RSTR_I2C2RST : stm32f10x.h
  • RCC_APB1RSTR_PWRRST : stm32f10x.h
  • RCC_APB1RSTR_SPI2RST : stm32f10x.h
  • RCC_APB1RSTR_TIM2RST : stm32f10x.h
  • RCC_APB1RSTR_TIM3RST : stm32f10x.h
  • RCC_APB1RSTR_TIM4RST : stm32f10x.h
  • RCC_APB1RSTR_USART2RST : stm32f10x.h
  • RCC_APB1RSTR_USART3RST : stm32f10x.h
  • RCC_APB1RSTR_WWDGRST : stm32f10x.h
  • RCC_APB2ENR_ADC1EN : stm32f10x.h
  • RCC_APB2ENR_ADC2EN : stm32f10x.h
  • RCC_APB2ENR_AFIOEN : stm32f10x.h
  • RCC_APB2ENR_IOPAEN : stm32f10x.h
  • RCC_APB2ENR_IOPBEN : stm32f10x.h
  • RCC_APB2ENR_IOPCEN : stm32f10x.h
  • RCC_APB2ENR_IOPDEN : stm32f10x.h
  • RCC_APB2ENR_IOPEEN : stm32f10x.h
  • RCC_APB2ENR_SPI1EN : stm32f10x.h
  • RCC_APB2ENR_TIM1EN : stm32f10x.h
  • RCC_APB2ENR_USART1EN : stm32f10x.h
  • RCC_APB2Periph_ADC1 : stm32f10x_rcc.h
  • RCC_APB2Periph_ADC2 : stm32f10x_rcc.h
  • RCC_APB2Periph_ADC3 : stm32f10x_rcc.h
  • RCC_APB2Periph_AFIO : stm32f10x_rcc.h
  • RCC_APB2Periph_GPIO_CAN1 : CAN/Networking/platform_config.h
  • RCC_APB2Periph_GPIO_CAN2 : CAN/Networking/platform_config.h
  • RCC_APB2Periph_GPIOA : stm32f10x_rcc.h
  • RCC_APB2Periph_GPIOB : stm32f10x_rcc.h
  • RCC_APB2Periph_GPIOC : stm32f10x_rcc.h
  • RCC_APB2Periph_GPIOD : stm32f10x_rcc.h
  • RCC_APB2Periph_GPIOE : stm32f10x_rcc.h
  • RCC_APB2Periph_GPIOF : stm32f10x_rcc.h
  • RCC_APB2Periph_GPIOG : stm32f10x_rcc.h
  • RCC_APB2Periph_GPIOx : USART/HyperTerminal_HwFlowControl/platform_config.h
  • RCC_APB2Periph_SPI1 : stm32f10x_rcc.h
  • RCC_APB2Periph_TIM1 : stm32f10x_rcc.h
  • RCC_APB2Periph_TIM10 : stm32f10x_rcc.h
  • RCC_APB2Periph_TIM11 : stm32f10x_rcc.h
  • RCC_APB2Periph_TIM15 : stm32f10x_rcc.h
  • RCC_APB2Periph_TIM16 : stm32f10x_rcc.h
  • RCC_APB2Periph_TIM17 : stm32f10x_rcc.h
  • RCC_APB2Periph_TIM8 : stm32f10x_rcc.h
  • RCC_APB2Periph_TIM9 : stm32f10x_rcc.h
  • RCC_APB2Periph_USART1 : stm32f10x_rcc.h
  • RCC_APB2RSTR_ADC1RST : stm32f10x.h
  • RCC_APB2RSTR_ADC2RST : stm32f10x.h
  • RCC_APB2RSTR_AFIORST : stm32f10x.h
  • RCC_APB2RSTR_IOPARST : stm32f10x.h
  • RCC_APB2RSTR_IOPBRST : stm32f10x.h
  • RCC_APB2RSTR_IOPCRST : stm32f10x.h
  • RCC_APB2RSTR_IOPDRST : stm32f10x.h
  • RCC_APB2RSTR_IOPERST : stm32f10x.h
  • RCC_APB2RSTR_SPI1RST : stm32f10x.h
  • RCC_APB2RSTR_TIM1RST : stm32f10x.h
  • RCC_APB2RSTR_USART1RST : stm32f10x.h
  • RCC_BASE : stm32f10x.h
  • RCC_BDCR_BDRST : stm32f10x.h
  • RCC_BDCR_LSEBYP : stm32f10x.h
  • RCC_BDCR_LSEON : stm32f10x.h
  • RCC_BDCR_LSERDY : stm32f10x.h
  • RCC_BDCR_RTCEN : stm32f10x.h
  • RCC_BDCR_RTCSEL : stm32f10x.h
  • RCC_BDCR_RTCSEL_0 : stm32f10x.h
  • RCC_BDCR_RTCSEL_1 : stm32f10x.h
  • RCC_BDCR_RTCSEL_HSE : stm32f10x.h
  • RCC_BDCR_RTCSEL_LSE : stm32f10x.h
  • RCC_BDCR_RTCSEL_LSI : stm32f10x.h
  • RCC_BDCR_RTCSEL_NOCLOCK : stm32f10x.h
  • RCC_CFGR_ADCPRE : stm32f10x.h
  • RCC_CFGR_ADCPRE_0 : stm32f10x.h
  • RCC_CFGR_ADCPRE_1 : stm32f10x.h
  • RCC_CFGR_ADCPRE_DIV2 : stm32f10x.h
  • RCC_CFGR_ADCPRE_DIV4 : stm32f10x.h
  • RCC_CFGR_ADCPRE_DIV6 : stm32f10x.h
  • RCC_CFGR_ADCPRE_DIV8 : stm32f10x.h
  • RCC_CFGR_HPRE : stm32f10x.h
  • RCC_CFGR_HPRE_0 : stm32f10x.h
  • RCC_CFGR_HPRE_1 : stm32f10x.h
  • RCC_CFGR_HPRE_2 : stm32f10x.h
  • RCC_CFGR_HPRE_3 : stm32f10x.h
  • RCC_CFGR_HPRE_DIV1 : stm32f10x.h
  • RCC_CFGR_HPRE_DIV128 : stm32f10x.h
  • RCC_CFGR_HPRE_DIV16 : stm32f10x.h
  • RCC_CFGR_HPRE_DIV2 : stm32f10x.h
  • RCC_CFGR_HPRE_DIV256 : stm32f10x.h
  • RCC_CFGR_HPRE_DIV4 : stm32f10x.h
  • RCC_CFGR_HPRE_DIV512 : stm32f10x.h
  • RCC_CFGR_HPRE_DIV64 : stm32f10x.h
  • RCC_CFGR_HPRE_DIV8 : stm32f10x.h
  • RCC_CFGR_MCO : stm32f10x.h
  • RCC_CFGR_MCO_0 : stm32f10x.h
  • RCC_CFGR_MCO_1 : stm32f10x.h
  • RCC_CFGR_MCO_2 : stm32f10x.h
  • RCC_CFGR_MCO_HSE : stm32f10x.h
  • RCC_CFGR_MCO_HSI : stm32f10x.h
  • RCC_CFGR_MCO_NOCLOCK : stm32f10x.h
  • RCC_CFGR_MCO_PLL : stm32f10x.h
  • RCC_CFGR_MCO_SYSCLK : stm32f10x.h
  • RCC_CFGR_PLLMULL : stm32f10x.h
  • RCC_CFGR_PLLMULL10 : stm32f10x.h
  • RCC_CFGR_PLLMULL11 : stm32f10x.h
  • RCC_CFGR_PLLMULL12 : stm32f10x.h
  • RCC_CFGR_PLLMULL13 : stm32f10x.h
  • RCC_CFGR_PLLMULL14 : stm32f10x.h
  • RCC_CFGR_PLLMULL15 : stm32f10x.h
  • RCC_CFGR_PLLMULL16 : stm32f10x.h
  • RCC_CFGR_PLLMULL2 : stm32f10x.h
  • RCC_CFGR_PLLMULL3 : stm32f10x.h
  • RCC_CFGR_PLLMULL4 : stm32f10x.h
  • RCC_CFGR_PLLMULL5 : stm32f10x.h
  • RCC_CFGR_PLLMULL6 : stm32f10x.h
  • RCC_CFGR_PLLMULL7 : stm32f10x.h
  • RCC_CFGR_PLLMULL8 : stm32f10x.h
  • RCC_CFGR_PLLMULL9 : stm32f10x.h
  • RCC_CFGR_PLLMULL_0 : stm32f10x.h
  • RCC_CFGR_PLLMULL_1 : stm32f10x.h
  • RCC_CFGR_PLLMULL_2 : stm32f10x.h
  • RCC_CFGR_PLLMULL_3 : stm32f10x.h
  • RCC_CFGR_PLLSRC : stm32f10x.h
  • RCC_CFGR_PLLSRC_HSE : stm32f10x.h
  • RCC_CFGR_PLLSRC_HSI_Div2 : stm32f10x.h
  • RCC_CFGR_PLLXTPRE : stm32f10x.h
  • RCC_CFGR_PLLXTPRE_HSE : stm32f10x.h
  • RCC_CFGR_PLLXTPRE_HSE_Div2 : stm32f10x.h
  • RCC_CFGR_PPRE1 : stm32f10x.h
  • RCC_CFGR_PPRE1_0 : stm32f10x.h
  • RCC_CFGR_PPRE1_1 : stm32f10x.h
  • RCC_CFGR_PPRE1_2 : stm32f10x.h
  • RCC_CFGR_PPRE1_DIV1 : stm32f10x.h
  • RCC_CFGR_PPRE1_DIV16 : stm32f10x.h
  • RCC_CFGR_PPRE1_DIV2 : stm32f10x.h
  • RCC_CFGR_PPRE1_DIV4 : stm32f10x.h
  • RCC_CFGR_PPRE1_DIV8 : stm32f10x.h
  • RCC_CFGR_PPRE2 : stm32f10x.h
  • RCC_CFGR_PPRE2_0 : stm32f10x.h
  • RCC_CFGR_PPRE2_1 : stm32f10x.h
  • RCC_CFGR_PPRE2_2 : stm32f10x.h
  • RCC_CFGR_PPRE2_DIV1 : stm32f10x.h
  • RCC_CFGR_PPRE2_DIV16 : stm32f10x.h
  • RCC_CFGR_PPRE2_DIV2 : stm32f10x.h
  • RCC_CFGR_PPRE2_DIV4 : stm32f10x.h
  • RCC_CFGR_PPRE2_DIV8 : stm32f10x.h
  • RCC_CFGR_SW : stm32f10x.h
  • RCC_CFGR_SW_0 : stm32f10x.h
  • RCC_CFGR_SW_1 : stm32f10x.h
  • RCC_CFGR_SW_HSE : stm32f10x.h
  • RCC_CFGR_SW_HSI : stm32f10x.h
  • RCC_CFGR_SW_PLL : stm32f10x.h
  • RCC_CFGR_SWS : stm32f10x.h
  • RCC_CFGR_SWS_0 : stm32f10x.h
  • RCC_CFGR_SWS_1 : stm32f10x.h
  • RCC_CFGR_SWS_HSE : stm32f10x.h
  • RCC_CFGR_SWS_HSI : stm32f10x.h
  • RCC_CFGR_SWS_PLL : stm32f10x.h
  • RCC_CFGR_USBPRE : stm32f10x.h
  • RCC_CIR_CSSC : stm32f10x.h
  • RCC_CIR_CSSF : stm32f10x.h
  • RCC_CIR_HSERDYC : stm32f10x.h
  • RCC_CIR_HSERDYF : stm32f10x.h
  • RCC_CIR_HSERDYIE : stm32f10x.h
  • RCC_CIR_HSIRDYC : stm32f10x.h
  • RCC_CIR_HSIRDYF : stm32f10x.h
  • RCC_CIR_HSIRDYIE : stm32f10x.h
  • RCC_CIR_LSERDYC : stm32f10x.h
  • RCC_CIR_LSERDYF : stm32f10x.h
  • RCC_CIR_LSERDYIE : stm32f10x.h
  • RCC_CIR_LSIRDYC : stm32f10x.h
  • RCC_CIR_LSIRDYF : stm32f10x.h
  • RCC_CIR_LSIRDYIE : stm32f10x.h
  • RCC_CIR_PLLRDYC : stm32f10x.h
  • RCC_CIR_PLLRDYF : stm32f10x.h
  • RCC_CIR_PLLRDYIE : stm32f10x.h
  • RCC_CR_CSSON : stm32f10x.h
  • RCC_CR_HSEBYP : stm32f10x.h
  • RCC_CR_HSEON : stm32f10x.h
  • RCC_CR_HSERDY : stm32f10x.h
  • RCC_CR_HSICAL : stm32f10x.h
  • RCC_CR_HSION : stm32f10x.h
  • RCC_CR_HSIRDY : stm32f10x.h
  • RCC_CR_HSITRIM : stm32f10x.h
  • RCC_CR_PLLON : stm32f10x.h
  • RCC_CR_PLLRDY : stm32f10x.h
  • RCC_CSR_IWDGRSTF : stm32f10x.h
  • RCC_CSR_LPWRRSTF : stm32f10x.h
  • RCC_CSR_LSION : stm32f10x.h
  • RCC_CSR_LSIRDY : stm32f10x.h
  • RCC_CSR_PINRSTF : stm32f10x.h
  • RCC_CSR_PORRSTF : stm32f10x.h
  • RCC_CSR_RMVF : stm32f10x.h
  • RCC_CSR_SFTRSTF : stm32f10x.h
  • RCC_CSR_WWDGRSTF : stm32f10x.h
  • RCC_FLAG_HSERDY : stm32f10x_rcc.h
  • RCC_FLAG_HSIRDY : stm32f10x_rcc.h
  • RCC_FLAG_IWDGRST : stm32f10x_rcc.h
  • RCC_FLAG_LPWRRST : stm32f10x_rcc.h
  • RCC_FLAG_LSERDY : stm32f10x_rcc.h
  • RCC_FLAG_LSIRDY : stm32f10x_rcc.h
  • RCC_FLAG_PINRST : stm32f10x_rcc.h
  • RCC_FLAG_PLLRDY : stm32f10x_rcc.h
  • RCC_FLAG_PORRST : stm32f10x_rcc.h
  • RCC_FLAG_SFTRST : stm32f10x_rcc.h
  • RCC_FLAG_WWDGRST : stm32f10x_rcc.h
  • RCC_HCLK_Div1 : stm32f10x_rcc.h
  • RCC_HCLK_Div16 : stm32f10x_rcc.h
  • RCC_HCLK_Div2 : stm32f10x_rcc.h
  • RCC_HCLK_Div4 : stm32f10x_rcc.h
  • RCC_HCLK_Div8 : stm32f10x_rcc.h
  • RCC_HSE_Bypass : stm32f10x_rcc.h
  • RCC_HSE_OFF : stm32f10x_rcc.h
  • RCC_HSE_ON : stm32f10x_rcc.h
  • RCC_IT_CSS : stm32f10x_rcc.h
  • RCC_IT_HSERDY : stm32f10x_rcc.h
  • RCC_IT_HSIRDY : stm32f10x_rcc.h
  • RCC_IT_LSERDY : stm32f10x_rcc.h
  • RCC_IT_LSIRDY : stm32f10x_rcc.h
  • RCC_IT_PLLRDY : stm32f10x_rcc.h
  • RCC_LSE_Bypass : stm32f10x_rcc.h
  • RCC_LSE_OFF : stm32f10x_rcc.h
  • RCC_LSE_ON : stm32f10x_rcc.h
  • RCC_MCO_HSE : stm32f10x_rcc.h
  • RCC_MCO_HSI : stm32f10x_rcc.h
  • RCC_MCO_NoClock : stm32f10x_rcc.h
  • RCC_MCO_PLLCLK_Div2 : stm32f10x_rcc.h
  • RCC_MCO_SYSCLK : stm32f10x_rcc.h
  • RCC_OFFSET : stm32f10x_rcc.c
  • RCC_PCLK2_Div2 : stm32f10x_rcc.h
  • RCC_PCLK2_Div4 : stm32f10x_rcc.h
  • RCC_PCLK2_Div6 : stm32f10x_rcc.h
  • RCC_PCLK2_Div8 : stm32f10x_rcc.h
  • RCC_PLLMul_10 : stm32f10x_rcc.h
  • RCC_PLLMul_11 : stm32f10x_rcc.h
  • RCC_PLLMul_12 : stm32f10x_rcc.h
  • RCC_PLLMul_13 : stm32f10x_rcc.h
  • RCC_PLLMul_14 : stm32f10x_rcc.h
  • RCC_PLLMul_15 : stm32f10x_rcc.h
  • RCC_PLLMul_16 : stm32f10x_rcc.h
  • RCC_PLLMul_2 : stm32f10x_rcc.h
  • RCC_PLLMul_3 : stm32f10x_rcc.h
  • RCC_PLLMul_4 : stm32f10x_rcc.h
  • RCC_PLLMul_5 : stm32f10x_rcc.h
  • RCC_PLLMul_6 : stm32f10x_rcc.h
  • RCC_PLLMul_7 : stm32f10x_rcc.h
  • RCC_PLLMul_8 : stm32f10x_rcc.h
  • RCC_PLLMul_9 : stm32f10x_rcc.h
  • RCC_PLLSource_HSE_Div1 : stm32f10x_rcc.h
  • RCC_PLLSource_HSE_Div2 : stm32f10x_rcc.h
  • RCC_PLLSource_HSI_Div2 : stm32f10x_rcc.h
  • RCC_RTCCLKSource_HSE_Div128 : stm32f10x_rcc.h
  • RCC_RTCCLKSource_LSE : stm32f10x_rcc.h
  • RCC_RTCCLKSource_LSI : stm32f10x_rcc.h
  • RCC_SYSCLK_Div1 : stm32f10x_rcc.h
  • RCC_SYSCLK_Div128 : stm32f10x_rcc.h
  • RCC_SYSCLK_Div16 : stm32f10x_rcc.h
  • RCC_SYSCLK_Div2 : stm32f10x_rcc.h
  • RCC_SYSCLK_Div256 : stm32f10x_rcc.h
  • RCC_SYSCLK_Div4 : stm32f10x_rcc.h
  • RCC_SYSCLK_Div512 : stm32f10x_rcc.h
  • RCC_SYSCLK_Div64 : stm32f10x_rcc.h
  • RCC_SYSCLK_Div8 : stm32f10x_rcc.h
  • RCC_SYSCLKSource_HSE : stm32f10x_rcc.h
  • RCC_SYSCLKSource_HSI : stm32f10x_rcc.h
  • RCC_SYSCLKSource_PLLCLK : stm32f10x_rcc.h
  • RCC_USBCLKSource_PLLCLK_1Div5 : stm32f10x_rcc.h
  • RCC_USBCLKSource_PLLCLK_Div1 : stm32f10x_rcc.h
  • RDP_Key : stm32f10x_flash.c
  • RDPRT_Mask : stm32f10x_flash.c
  • READ_BIT : stm32f10x.h
  • READ_REG : stm32f10x.h
  • READ_STATUS : stm32l152_eval_lcd.c , stm3210c_eval_lcd.c , stm32100b_eval_lcd.c , stm3210b_eval_lcd.c
  • Red : stm32_eval.h
  • RIGHT_BUTTON_EXTI_IRQn : stm32100e_eval.h , stm3210b_eval.h , stm32l152_eval.h , stm3210e_eval.h , stm32100b_eval.h
  • RIGHT_BUTTON_EXTI_LINE : stm32l152_eval.h , stm3210b_eval.h , stm32100b_eval.h , stm3210e_eval.h , stm32100e_eval.h
  • RIGHT_BUTTON_EXTI_PIN_SOURCE : stm3210e_eval.h , stm32100b_eval.h , stm32l152_eval.h , stm32100e_eval.h , stm3210b_eval.h
  • RIGHT_BUTTON_EXTI_PORT_SOURCE : stm3210b_eval.h , stm32100b_eval.h , stm3210e_eval.h , stm32100e_eval.h , stm32l152_eval.h
  • RIGHT_BUTTON_GPIO_CLK : stm32100e_eval.h , stm3210e_eval.h , stm32100b_eval.h , stm32l152_eval.h , stm3210b_eval.h
  • RIGHT_BUTTON_GPIO_PORT : stm32l152_eval.h , stm3210b_eval.h , stm32100b_eval.h , stm32100e_eval.h , stm3210e_eval.h
  • RIGHT_BUTTON_PIN : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210e_eval.h , stm32l152_eval.h
  • ROW_ADDRESS : stm3210e_eval_fsmc_nand.c
  • RTC : stm32f10x.h
  • RTC_ALRH_RTC_ALR : stm32f10x.h
  • RTC_ALRL_RTC_ALR : stm32f10x.h
  • RTC_BASE : stm32f10x.h
  • RTC_CNTH_RTC_CNT : stm32f10x.h
  • RTC_CNTL_RTC_CNT : stm32f10x.h
  • RTC_CRH_ALRIE : stm32f10x.h
  • RTC_CRH_OWIE : stm32f10x.h
  • RTC_CRH_SECIE : stm32f10x.h
  • RTC_CRL_ALRF : stm32f10x.h
  • RTC_CRL_CNF : stm32f10x.h
  • RTC_CRL_OWF : stm32f10x.h
  • RTC_CRL_RSF : stm32f10x.h
  • RTC_CRL_RTOFF : stm32f10x.h
  • RTC_CRL_SECF : stm32f10x.h
  • RTC_DIVH_RTC_DIV : stm32f10x.h
  • RTC_DIVL_RTC_DIV : stm32f10x.h
  • RTC_FLAG_ALR : stm32f10x_rtc.h
  • RTC_FLAG_OW : stm32f10x_rtc.h
  • RTC_FLAG_RSF : stm32f10x_rtc.h
  • RTC_FLAG_RTOFF : stm32f10x_rtc.h
  • RTC_FLAG_SEC : stm32f10x_rtc.h
  • RTC_IT_ALR : stm32f10x_rtc.h
  • RTC_IT_OW : stm32f10x_rtc.h
  • RTC_IT_SEC : stm32f10x_rtc.h
  • RTC_LSB_MASK : stm32f10x_rtc.c
  • RTC_PRLH_PRL : stm32f10x.h
  • RTC_PRLL_PRL : stm32f10x.h
  • RTCClockOutput_Enable : STM32F10x_StdPeriph_Examples/RTC/Calendar/main.c , STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/main.c
  • RTCCR_CAL_MASK : stm32f10x_bkp.c
  • RTCCR_MASK : stm32f10x_bkp.c
  • RTCEN_BitNumber : stm32f10x_rcc.c
  • RWMOD_BitNumber : stm32f10x_sdio.c
  • RWSTART_BitNumber : stm32f10x_sdio.c
  • RWSTOP_BitNumber : stm32f10x_sdio.c
  • RxBufferSize : STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/main.c , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.c
  • RxBufferSize1 : STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c
  • RxBufferSize2 : STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c


STM32F10x Standard Peripherals Firmware Library: Globals

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- s -

  • SC_Receive_Timeout : STM32F10x_StdPeriph_Examples/USART/Smartcard/main.c
  • SCB_AFSR_IMPDEF : stm32f10x.h
  • SCB_AIRCR_ENDIANESS : stm32f10x.h
  • SCB_AIRCR_PRIGROUP : stm32f10x.h
  • SCB_AIRCR_PRIGROUP0 : stm32f10x.h
  • SCB_AIRCR_PRIGROUP1 : stm32f10x.h
  • SCB_AIRCR_PRIGROUP2 : stm32f10x.h
  • SCB_AIRCR_PRIGROUP3 : stm32f10x.h
  • SCB_AIRCR_PRIGROUP4 : stm32f10x.h
  • SCB_AIRCR_PRIGROUP5 : stm32f10x.h
  • SCB_AIRCR_PRIGROUP6 : stm32f10x.h
  • SCB_AIRCR_PRIGROUP7 : stm32f10x.h
  • SCB_AIRCR_PRIGROUP_0 : stm32f10x.h
  • SCB_AIRCR_PRIGROUP_1 : stm32f10x.h
  • SCB_AIRCR_PRIGROUP_2 : stm32f10x.h
  • SCB_AIRCR_SYSRESETREQ : stm32f10x.h
  • SCB_AIRCR_VECTCLRACTIVE : stm32f10x.h
  • SCB_AIRCR_VECTKEY : stm32f10x.h
  • SCB_AIRCR_VECTRESET : stm32f10x.h
  • SCB_BFAR_ADDRESS : stm32f10x.h
  • SCB_CCR_BFHFNMIGN : stm32f10x.h
  • SCB_CCR_DIV_0_TRP : stm32f10x.h
  • SCB_CCR_NONBASETHRDENA : stm32f10x.h
  • SCB_CCR_STKALIGN : stm32f10x.h
  • SCB_CCR_UNALIGN_TRP : stm32f10x.h
  • SCB_CCR_USERSETMPEND : stm32f10x.h
  • SCB_CFSR_BFARVALID : stm32f10x.h
  • SCB_CFSR_DACCVIOL : stm32f10x.h
  • SCB_CFSR_DIVBYZERO : stm32f10x.h
  • SCB_CFSR_IACCVIOL : stm32f10x.h
  • SCB_CFSR_IBUSERR : stm32f10x.h
  • SCB_CFSR_IMPRECISERR : stm32f10x.h
  • SCB_CFSR_INVPC : stm32f10x.h
  • SCB_CFSR_INVSTATE : stm32f10x.h
  • SCB_CFSR_MMARVALID : stm32f10x.h
  • SCB_CFSR_MSTKERR : stm32f10x.h
  • SCB_CFSR_MUNSTKERR : stm32f10x.h
  • SCB_CFSR_NOCP : stm32f10x.h
  • SCB_CFSR_PRECISERR : stm32f10x.h
  • SCB_CFSR_STKERR : stm32f10x.h
  • SCB_CFSR_UNALIGNED : stm32f10x.h
  • SCB_CFSR_UNDEFINSTR : stm32f10x.h
  • SCB_CFSR_UNSTKERR : stm32f10x.h
  • SCB_CPUID_Constant : stm32f10x.h
  • SCB_CPUID_IMPLEMENTER : stm32f10x.h
  • SCB_CPUID_PARTNO : stm32f10x.h
  • SCB_CPUID_REVISION : stm32f10x.h
  • SCB_CPUID_VARIANT : stm32f10x.h
  • SCB_DFSR_BKPT : stm32f10x.h
  • SCB_DFSR_DWTTRAP : stm32f10x.h
  • SCB_DFSR_EXTERNAL : stm32f10x.h
  • SCB_DFSR_HALTED : stm32f10x.h
  • SCB_DFSR_VCATCH : stm32f10x.h
  • SCB_HFSR_DEBUGEVT : stm32f10x.h
  • SCB_HFSR_FORCED : stm32f10x.h
  • SCB_HFSR_VECTTBL : stm32f10x.h
  • SCB_ICSR_ISRPENDING : stm32f10x.h
  • SCB_ICSR_ISRPREEMPT : stm32f10x.h
  • SCB_ICSR_NMIPENDSET : stm32f10x.h
  • SCB_ICSR_PENDSTCLR : stm32f10x.h
  • SCB_ICSR_PENDSTSET : stm32f10x.h
  • SCB_ICSR_PENDSVCLR : stm32f10x.h
  • SCB_ICSR_PENDSVSET : stm32f10x.h
  • SCB_ICSR_RETTOBASE : stm32f10x.h
  • SCB_ICSR_VECTACTIVE : stm32f10x.h
  • SCB_ICSR_VECTPENDING : stm32f10x.h
  • SCB_MMFAR_ADDRESS : stm32f10x.h
  • SCB_SCR_SEVONPEND : stm32f10x.h
  • SCB_SCR_SLEEPDEEP : stm32f10x.h
  • SCB_SCR_SLEEPONEXIT : stm32f10x.h
  • SCB_SHCSR_BUSFAULTACT : stm32f10x.h
  • SCB_SHCSR_BUSFAULTENA : stm32f10x.h
  • SCB_SHCSR_BUSFAULTPENDED : stm32f10x.h
  • SCB_SHCSR_MEMFAULTACT : stm32f10x.h
  • SCB_SHCSR_MEMFAULTENA : stm32f10x.h
  • SCB_SHCSR_MEMFAULTPENDED : stm32f10x.h
  • SCB_SHCSR_MONITORACT : stm32f10x.h
  • SCB_SHCSR_PENDSVACT : stm32f10x.h
  • SCB_SHCSR_SVCALLACT : stm32f10x.h
  • SCB_SHCSR_SVCALLPENDED : stm32f10x.h
  • SCB_SHCSR_SYSTICKACT : stm32f10x.h
  • SCB_SHCSR_USGFAULTACT : stm32f10x.h
  • SCB_SHCSR_USGFAULTENA : stm32f10x.h
  • SCB_SHCSR_USGFAULTPENDED : stm32f10x.h
  • SCB_SHPR_PRI_N : stm32f10x.h
  • SCB_SHPR_PRI_N1 : stm32f10x.h
  • SCB_SHPR_PRI_N2 : stm32f10x.h
  • SCB_SHPR_PRI_N3 : stm32f10x.h
  • SCB_VTOR_TBLBASE : stm32f10x.h
  • SCB_VTOR_TBLOFF : stm32f10x.h
  • SD_0TO7BITS : stm32_eval_sdio_sd.c
  • SD_16TO23BITS : stm32_eval_sdio_sd.c
  • SD_24TO31BITS : stm32_eval_sdio_sd.c
  • SD_8TO15BITS : stm32_eval_sdio_sd.c
  • SD_ALLZERO : stm32_eval_sdio_sd.c
  • SD_BLOCK_SIZE : stm32_eval_spi_sd.h
  • SD_CARD_LOCKED : stm32_eval_sdio_sd.c
  • SD_CCCC_ERASE : stm32_eval_sdio_sd.c
  • SD_CCCC_LOCK_UNLOCK : stm32_eval_sdio_sd.c
  • SD_CCCC_WRITE_PROT : stm32_eval_sdio_sd.c
  • SD_CHECK_PATTERN : stm32_eval_sdio_sd.c
  • SD_CMD_ALL_SEND_CID : stm32_eval_sdio_sd.h
  • SD_CMD_APP_CMD : stm32_eval_sdio_sd.h
  • SD_CMD_APP_SD_SET_BUSWIDTH : stm32_eval_sdio_sd.h
  • SD_CMD_CLR_WRITE_PROT : stm32_eval_sdio_sd.h , stm32_eval_spi_sd.h
  • SD_CMD_ERASE : stm32_eval_sdio_sd.h , stm32_eval_spi_sd.h
  • SD_CMD_ERASE_GRP_END : stm32_eval_sdio_sd.h , stm32_eval_spi_sd.h
  • SD_CMD_ERASE_GRP_START : stm32_eval_sdio_sd.h , stm32_eval_spi_sd.h
  • SD_CMD_FAST_IO : stm32_eval_sdio_sd.h
  • SD_CMD_GEN_CMD : stm32_eval_sdio_sd.h
  • SD_CMD_GO_IDLE_STATE : stm32_eval_sdio_sd.h , stm32_eval_spi_sd.h
  • SD_CMD_GO_INACTIVE_STATE : stm32_eval_sdio_sd.h
  • SD_CMD_GO_IRQ_STATE : stm32_eval_sdio_sd.h
  • SD_CMD_HS_BUSTEST_READ : stm32_eval_sdio_sd.h
  • SD_CMD_HS_BUSTEST_WRITE : stm32_eval_sdio_sd.h
  • SD_CMD_HS_SEND_EXT_CSD : stm32_eval_sdio_sd.h
  • SD_CMD_HS_SWITCH : stm32_eval_sdio_sd.h
  • SD_CMD_LOCK_UNLOCK : stm32_eval_sdio_sd.h
  • SD_CMD_NO_CMD : stm32_eval_sdio_sd.h
  • SD_CMD_PROG_CID : stm32_eval_sdio_sd.h
  • SD_CMD_PROG_CSD : stm32_eval_sdio_sd.h , stm32_eval_spi_sd.h
  • SD_CMD_READ_DAT_UNTIL_STOP : stm32_eval_sdio_sd.h
  • SD_CMD_READ_MULT_BLOCK : stm32_eval_sdio_sd.h , stm32_eval_spi_sd.h
  • SD_CMD_READ_SINGLE_BLOCK : stm32_eval_sdio_sd.h , stm32_eval_spi_sd.h
  • SD_CMD_SD_APP_CHANGE_SECURE_AREA : stm32_eval_sdio_sd.h
  • SD_CMD_SD_APP_GET_CER_RES1 : stm32_eval_sdio_sd.h
  • SD_CMD_SD_APP_GET_CER_RN2 : stm32_eval_sdio_sd.h
  • SD_CMD_SD_APP_GET_MID : stm32_eval_sdio_sd.h
  • SD_CMD_SD_APP_GET_MKB : stm32_eval_sdio_sd.h
  • SD_CMD_SD_APP_OP_COND : stm32_eval_sdio_sd.h
  • SD_CMD_SD_APP_SECURE_ERASE : stm32_eval_sdio_sd.h
  • SD_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK : stm32_eval_sdio_sd.h
  • SD_CMD_SD_APP_SECURE_WRITE_MKB : stm32_eval_sdio_sd.h
  • SD_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK : stm32_eval_sdio_sd.h
  • SD_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS : stm32_eval_sdio_sd.h
  • SD_CMD_SD_APP_SEND_SCR : stm32_eval_sdio_sd.h
  • SD_CMD_SD_APP_SET_CER_RES2 : stm32_eval_sdio_sd.h
  • SD_CMD_SD_APP_SET_CER_RN1 : stm32_eval_sdio_sd.h
  • SD_CMD_SD_APP_SET_CLR_CARD_DETECT : stm32_eval_sdio_sd.h
  • SD_CMD_SD_APP_STAUS : stm32_eval_sdio_sd.h
  • SD_CMD_SD_ERASE_GRP_END : stm32_eval_sdio_sd.h , stm32_eval_spi_sd.h
  • SD_CMD_SD_ERASE_GRP_START : stm32_eval_sdio_sd.h , stm32_eval_spi_sd.h
  • SD_CMD_SDIO_RW_DIRECT : stm32_eval_sdio_sd.h
  • SD_CMD_SDIO_RW_EXTENDED : stm32_eval_sdio_sd.h
  • SD_CMD_SDIO_SEN_OP_COND : stm32_eval_sdio_sd.h
  • SD_CMD_SEL_DESEL_CARD : stm32_eval_sdio_sd.h
  • SD_CMD_SEND_CID : stm32_eval_sdio_sd.h , stm32_eval_spi_sd.h
  • SD_CMD_SEND_CSD : stm32_eval_sdio_sd.h , stm32_eval_spi_sd.h
  • SD_CMD_SEND_OP_COND : stm32_eval_sdio_sd.h , stm32_eval_spi_sd.h
  • SD_CMD_SEND_STATUS : stm32_eval_sdio_sd.h , stm32_eval_spi_sd.h
  • SD_CMD_SEND_WRITE_PROT : stm32_eval_sdio_sd.h , stm32_eval_spi_sd.h
  • SD_CMD_SET_BLOCK_COUNT : stm32_eval_sdio_sd.h , stm32_eval_spi_sd.h
  • SD_CMD_SET_BLOCKLEN : stm32_eval_sdio_sd.h , stm32_eval_spi_sd.h
  • SD_CMD_SET_DSR : stm32_eval_sdio_sd.h
  • SD_CMD_SET_REL_ADDR : stm32_eval_sdio_sd.h
  • SD_CMD_SET_WRITE_PROT : stm32_eval_sdio_sd.h , stm32_eval_spi_sd.h
  • SD_CMD_STOP_TRANSMISSION : stm32_eval_sdio_sd.h , stm32_eval_spi_sd.h
  • SD_CMD_UNTAG_ERASE_GROUP : stm32_eval_spi_sd.h
  • SD_CMD_UNTAG_SECTOR : stm32_eval_spi_sd.h
  • SD_CMD_WRITE_DAT_UNTIL_STOP : stm32_eval_sdio_sd.h
  • SD_CMD_WRITE_MULT_BLOCK : stm32_eval_sdio_sd.h , stm32_eval_spi_sd.h
  • SD_CMD_WRITE_SINGLE_BLOCK : stm32_eval_sdio_sd.h , stm32_eval_spi_sd.h
  • SD_CS_GPIO_CLK : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210c_eval.h , stm32l152_eval.h
  • SD_CS_GPIO_PORT : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210c_eval.h , stm32l152_eval.h
  • SD_CS_HIGH : stm32_eval_spi_sd.h
  • SD_CS_LOW : stm32_eval_spi_sd.h
  • SD_CS_PIN : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210c_eval.h , stm32l152_eval.h
  • SD_DATATIMEOUT : stm32_eval_sdio_sd.c
  • SD_DETECT_EXTI_IRQn : stm32l152_eval.h
  • SD_DETECT_EXTI_LINE : stm32l152_eval.h
  • SD_DETECT_EXTI_PIN_SOURCE : stm32l152_eval.h
  • SD_DETECT_EXTI_PORT_SOURCE : stm32l152_eval.h
  • SD_DETECT_GPIO_CLK : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210c_eval.h , stm3210e_eval.h , stm32l152_eval.h
  • SD_DETECT_GPIO_PORT : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210c_eval.h , stm3210e_eval.h , stm32l152_eval.h
  • SD_DETECT_PIN : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210c_eval.h , stm3210e_eval.h , stm32l152_eval.h
  • SD_DMA_MODE : stm32_eval_sdio_sd.h
  • SD_DUMMY_BYTE : stm32_eval_spi_sd.h
  • SD_HALFFIFO : stm32_eval_sdio_sd.c
  • SD_HALFFIFOBYTES : stm32_eval_sdio_sd.c
  • SD_HIGH_CAPACITY : stm32_eval_sdio_sd.c
  • SD_MAX_DATA_LENGTH : stm32_eval_sdio_sd.c
  • SD_MAX_VOLT_TRIAL : stm32_eval_sdio_sd.c
  • SD_NOT_PRESENT : stm32_eval_sdio_sd.h , stm32_eval_spi_sd.h
  • SD_OCR_ADDR_MISALIGNED : stm32_eval_sdio_sd.c
  • SD_OCR_ADDR_OUT_OF_RANGE : stm32_eval_sdio_sd.c
  • SD_OCR_AKE_SEQ_ERROR : stm32_eval_sdio_sd.c
  • SD_OCR_BAD_ERASE_PARAM : stm32_eval_sdio_sd.c
  • SD_OCR_BLOCK_LEN_ERR : stm32_eval_sdio_sd.c
  • SD_OCR_CARD_ECC_DISABLED : stm32_eval_sdio_sd.c
  • SD_OCR_CARD_ECC_FAILED : stm32_eval_sdio_sd.c
  • SD_OCR_CC_ERROR : stm32_eval_sdio_sd.c
  • SD_OCR_CID_CSD_OVERWRIETE : stm32_eval_sdio_sd.c
  • SD_OCR_COM_CRC_FAILED : stm32_eval_sdio_sd.c
  • SD_OCR_ERASE_RESET : stm32_eval_sdio_sd.c
  • SD_OCR_ERASE_SEQ_ERR : stm32_eval_sdio_sd.c
  • SD_OCR_ERRORBITS : stm32_eval_sdio_sd.c
  • SD_OCR_GENERAL_UNKNOWN_ERROR : stm32_eval_sdio_sd.c
  • SD_OCR_ILLEGAL_CMD : stm32_eval_sdio_sd.c
  • SD_OCR_LOCK_UNLOCK_FAILED : stm32_eval_sdio_sd.c
  • SD_OCR_STREAM_READ_UNDERRUN : stm32_eval_sdio_sd.c
  • SD_OCR_STREAM_WRITE_OVERRUN : stm32_eval_sdio_sd.c
  • SD_OCR_WP_ERASE_SKIP : stm32_eval_sdio_sd.c
  • SD_OCR_WRITE_PROT_VIOLATION : stm32_eval_sdio_sd.c
  • SD_OPERATION_BLOCK : STM32F10x_StdPeriph_Examples/SDIO/uSDCard/main.c
  • SD_OPERATION_END : STM32F10x_StdPeriph_Examples/SDIO/uSDCard/main.c
  • SD_OPERATION_ERASE : STM32F10x_StdPeriph_Examples/SDIO/uSDCard/main.c
  • SD_OPERATION_MULTI_BLOCK : STM32F10x_StdPeriph_Examples/SDIO/uSDCard/main.c
  • SD_PRESENT : stm32_eval_sdio_sd.h , stm32_eval_spi_sd.h
  • SD_R6_COM_CRC_FAILED : stm32_eval_sdio_sd.c
  • SD_R6_GENERAL_UNKNOWN_ERROR : stm32_eval_sdio_sd.c
  • SD_R6_ILLEGAL_CMD : stm32_eval_sdio_sd.c
  • SD_SINGLE_BUS_SUPPORT : stm32_eval_sdio_sd.c
  • SD_SPI : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210c_eval.h , stm32l152_eval.h
  • SD_SPI_CLK : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210c_eval.h , stm32l152_eval.h
  • SD_SPI_MISO_AF : stm32l152_eval.h
  • SD_SPI_MISO_GPIO_CLK : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210c_eval.h , stm32l152_eval.h
  • SD_SPI_MISO_GPIO_PORT : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210c_eval.h , stm32l152_eval.h
  • SD_SPI_MISO_PIN : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210c_eval.h , stm32l152_eval.h
  • SD_SPI_MISO_SOURCE : stm32l152_eval.h
  • SD_SPI_MOSI_AF : stm32l152_eval.h
  • SD_SPI_MOSI_GPIO_CLK : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210c_eval.h , stm32l152_eval.h
  • SD_SPI_MOSI_GPIO_PORT : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210c_eval.h , stm32l152_eval.h
  • SD_SPI_MOSI_PIN : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210c_eval.h , stm32l152_eval.h
  • SD_SPI_MOSI_SOURCE : stm32l152_eval.h
  • SD_SPI_SCK_AF : stm32l152_eval.h
  • SD_SPI_SCK_GPIO_CLK : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210c_eval.h , stm32l152_eval.h
  • SD_SPI_SCK_GPIO_PORT : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210c_eval.h , stm32l152_eval.h
  • SD_SPI_SCK_PIN : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210c_eval.h , stm32l152_eval.h
  • SD_SPI_SCK_SOURCE : stm32l152_eval.h
  • SD_START_DATA_MULTIPLE_BLOCK_READ : stm32_eval_spi_sd.h
  • SD_START_DATA_MULTIPLE_BLOCK_WRITE : stm32_eval_spi_sd.h
  • SD_START_DATA_SINGLE_BLOCK_READ : stm32_eval_spi_sd.h
  • SD_START_DATA_SINGLE_BLOCK_WRITE : stm32_eval_spi_sd.h
  • SD_STD_CAPACITY : stm32_eval_sdio_sd.c
  • SD_STOP_DATA_MULTIPLE_BLOCK_WRITE : stm32_eval_spi_sd.h
  • SD_VOLTAGE_WINDOW_SD : stm32_eval_sdio_sd.c
  • SD_WIDE_BUS_SUPPORT : stm32_eval_sdio_sd.c
  • SDIO : stm32f10x.h
  • SDIO_ARG_CMDARG : stm32f10x.h
  • SDIO_BASE : stm32f10x.h
  • SDIO_BusWide_1b : stm32f10x_sdio.h
  • SDIO_BusWide_4b : stm32f10x_sdio.h
  • SDIO_BusWide_8b : stm32f10x_sdio.h
  • SDIO_CLKCR_BYPASS : stm32f10x.h
  • SDIO_CLKCR_CLKDIV : stm32f10x.h
  • SDIO_CLKCR_CLKEN : stm32f10x.h
  • SDIO_CLKCR_HWFC_EN : stm32f10x.h
  • SDIO_CLKCR_NEGEDGE : stm32f10x.h
  • SDIO_CLKCR_PWRSAV : stm32f10x.h
  • SDIO_CLKCR_WIDBUS : stm32f10x.h
  • SDIO_CLKCR_WIDBUS_0 : stm32f10x.h
  • SDIO_CLKCR_WIDBUS_1 : stm32f10x.h
  • SDIO_ClockBypass_Disable : stm32f10x_sdio.h
  • SDIO_ClockBypass_Enable : stm32f10x_sdio.h
  • SDIO_ClockEdge_Falling : stm32f10x_sdio.h
  • SDIO_ClockEdge_Rising : stm32f10x_sdio.h
  • SDIO_ClockPowerSave_Disable : stm32f10x_sdio.h
  • SDIO_ClockPowerSave_Enable : stm32f10x_sdio.h
  • SDIO_CMD0TIMEOUT : stm32_eval_sdio_sd.c
  • SDIO_CMD_CEATACMD : stm32f10x.h
  • SDIO_CMD_CMDINDEX : stm32f10x.h
  • SDIO_CMD_CPSMEN : stm32f10x.h
  • SDIO_CMD_ENCMDCOMPL : stm32f10x.h
  • SDIO_CMD_NIEN : stm32f10x.h
  • SDIO_CMD_SDIOSUSPEND : stm32f10x.h
  • SDIO_CMD_WAITINT : stm32f10x.h
  • SDIO_CMD_WAITPEND : stm32f10x.h
  • SDIO_CMD_WAITRESP : stm32f10x.h
  • SDIO_CMD_WAITRESP_0 : stm32f10x.h
  • SDIO_CMD_WAITRESP_1 : stm32f10x.h
  • SDIO_CPSM_Disable : stm32f10x_sdio.h
  • SDIO_CPSM_Enable : stm32f10x_sdio.h
  • SDIO_DataBlockSize_1024b : stm32f10x_sdio.h
  • SDIO_DataBlockSize_128b : stm32f10x_sdio.h
  • SDIO_DataBlockSize_16384b : stm32f10x_sdio.h
  • SDIO_DataBlockSize_16b : stm32f10x_sdio.h
  • SDIO_DataBlockSize_1b : stm32f10x_sdio.h
  • SDIO_DataBlockSize_2048b : stm32f10x_sdio.h
  • SDIO_DataBlockSize_256b : stm32f10x_sdio.h
  • SDIO_DataBlockSize_2b : stm32f10x_sdio.h
  • SDIO_DataBlockSize_32b : stm32f10x_sdio.h
  • SDIO_DataBlockSize_4096b : stm32f10x_sdio.h
  • SDIO_DataBlockSize_4b : stm32f10x_sdio.h
  • SDIO_DataBlockSize_512b : stm32f10x_sdio.h
  • SDIO_DataBlockSize_64b : stm32f10x_sdio.h
  • SDIO_DataBlockSize_8192b : stm32f10x_sdio.h
  • SDIO_DataBlockSize_8b : stm32f10x_sdio.h
  • SDIO_DCOUNT_DATACOUNT : stm32f10x.h
  • SDIO_DCTRL_DBLOCKSIZE : stm32f10x.h
  • SDIO_DCTRL_DBLOCKSIZE_0 : stm32f10x.h
  • SDIO_DCTRL_DBLOCKSIZE_1 : stm32f10x.h
  • SDIO_DCTRL_DBLOCKSIZE_2 : stm32f10x.h
  • SDIO_DCTRL_DBLOCKSIZE_3 : stm32f10x.h
  • SDIO_DCTRL_DMAEN : stm32f10x.h
  • SDIO_DCTRL_DTDIR : stm32f10x.h
  • SDIO_DCTRL_DTEN : stm32f10x.h
  • SDIO_DCTRL_DTMODE : stm32f10x.h
  • SDIO_DCTRL_RWMOD : stm32f10x.h
  • SDIO_DCTRL_RWSTART : stm32f10x.h
  • SDIO_DCTRL_RWSTOP : stm32f10x.h
  • SDIO_DCTRL_SDIOEN : stm32f10x.h
  • SDIO_DLEN_DATALENGTH : stm32f10x.h
  • SDIO_DPSM_Disable : stm32f10x_sdio.h
  • SDIO_DPSM_Enable : stm32f10x_sdio.h
  • SDIO_DTIMER_DATATIME : stm32f10x.h
  • SDIO_FIFO_ADDRESS : stm3210e_eval.h
  • SDIO_FIFO_FIFODATA : stm32f10x.h
  • SDIO_FIFOCNT_FIFOCOUNT : stm32f10x.h
  • SDIO_FLAG_CCRCFAIL : stm32f10x_sdio.h
  • SDIO_FLAG_CEATAEND : stm32f10x_sdio.h
  • SDIO_FLAG_CMDACT : stm32f10x_sdio.h
  • SDIO_FLAG_CMDREND : stm32f10x_sdio.h
  • SDIO_FLAG_CMDSENT : stm32f10x_sdio.h
  • SDIO_FLAG_CTIMEOUT : stm32f10x_sdio.h
  • SDIO_FLAG_DATAEND : stm32f10x_sdio.h
  • SDIO_FLAG_DBCKEND : stm32f10x_sdio.h
  • SDIO_FLAG_DCRCFAIL : stm32f10x_sdio.h
  • SDIO_FLAG_DTIMEOUT : stm32f10x_sdio.h
  • SDIO_FLAG_RXACT : stm32f10x_sdio.h
  • SDIO_FLAG_RXDAVL : stm32f10x_sdio.h
  • SDIO_FLAG_RXFIFOE : stm32f10x_sdio.h
  • SDIO_FLAG_RXFIFOF : stm32f10x_sdio.h
  • SDIO_FLAG_RXFIFOHF : stm32f10x_sdio.h
  • SDIO_FLAG_RXOVERR : stm32f10x_sdio.h
  • SDIO_FLAG_SDIOIT : stm32f10x_sdio.h
  • SDIO_FLAG_STBITERR : stm32f10x_sdio.h
  • SDIO_FLAG_TXACT : stm32f10x_sdio.h
  • SDIO_FLAG_TXDAVL : stm32f10x_sdio.h
  • SDIO_FLAG_TXFIFOE : stm32f10x_sdio.h
  • SDIO_FLAG_TXFIFOF : stm32f10x_sdio.h
  • SDIO_FLAG_TXFIFOHE : stm32f10x_sdio.h
  • SDIO_FLAG_TXUNDERR : stm32f10x_sdio.h
  • SDIO_HardwareFlowControl_Disable : stm32f10x_sdio.h
  • SDIO_HardwareFlowControl_Enable : stm32f10x_sdio.h
  • SDIO_HIGH_CAPACITY_MMC_CARD : stm32_eval_sdio_sd.h
  • SDIO_HIGH_CAPACITY_SD_CARD : stm32_eval_sdio_sd.h
  • SDIO_HIGH_SPEED_MULTIMEDIA_CARD : stm32_eval_sdio_sd.h
  • SDIO_ICR_CCRCFAILC : stm32f10x.h
  • SDIO_ICR_CEATAENDC : stm32f10x.h
  • SDIO_ICR_CMDRENDC : stm32f10x.h
  • SDIO_ICR_CMDSENTC : stm32f10x.h
  • SDIO_ICR_CTIMEOUTC : stm32f10x.h
  • SDIO_ICR_DATAENDC : stm32f10x.h
  • SDIO_ICR_DBCKENDC : stm32f10x.h
  • SDIO_ICR_DCRCFAILC : stm32f10x.h
  • SDIO_ICR_DTIMEOUTC : stm32f10x.h
  • SDIO_ICR_RXOVERRC : stm32f10x.h
  • SDIO_ICR_SDIOITC : stm32f10x.h
  • SDIO_ICR_STBITERRC : stm32f10x.h
  • SDIO_ICR_TXUNDERRC : stm32f10x.h
  • SDIO_INIT_CLK_DIV : stm3210e_eval.h
  • SDIO_IT_CCRCFAIL : stm32f10x_sdio.h
  • SDIO_IT_CEATAEND : stm32f10x_sdio.h
  • SDIO_IT_CMDACT : stm32f10x_sdio.h
  • SDIO_IT_CMDREND : stm32f10x_sdio.h
  • SDIO_IT_CMDSENT : stm32f10x_sdio.h
  • SDIO_IT_CTIMEOUT : stm32f10x_sdio.h
  • SDIO_IT_DATAEND : stm32f10x_sdio.h
  • SDIO_IT_DBCKEND : stm32f10x_sdio.h
  • SDIO_IT_DCRCFAIL : stm32f10x_sdio.h
  • SDIO_IT_DTIMEOUT : stm32f10x_sdio.h
  • SDIO_IT_RXACT : stm32f10x_sdio.h
  • SDIO_IT_RXDAVL : stm32f10x_sdio.h
  • SDIO_IT_RXFIFOE : stm32f10x_sdio.h
  • SDIO_IT_RXFIFOF : stm32f10x_sdio.h
  • SDIO_IT_RXFIFOHF : stm32f10x_sdio.h
  • SDIO_IT_RXOVERR : stm32f10x_sdio.h
  • SDIO_IT_SDIOIT : stm32f10x_sdio.h
  • SDIO_IT_STBITERR : stm32f10x_sdio.h
  • SDIO_IT_TXACT : stm32f10x_sdio.h
  • SDIO_IT_TXDAVL : stm32f10x_sdio.h
  • SDIO_IT_TXFIFOE : stm32f10x_sdio.h
  • SDIO_IT_TXFIFOF : stm32f10x_sdio.h
  • SDIO_IT_TXFIFOHE : stm32f10x_sdio.h
  • SDIO_IT_TXUNDERR : stm32f10x_sdio.h
  • SDIO_MASK_CCRCFAILIE : stm32f10x.h
  • SDIO_MASK_CEATAENDIE : stm32f10x.h
  • SDIO_MASK_CMDACTIE : stm32f10x.h
  • SDIO_MASK_CMDRENDIE : stm32f10x.h
  • SDIO_MASK_CMDSENTIE : stm32f10x.h
  • SDIO_MASK_CTIMEOUTIE : stm32f10x.h
  • SDIO_MASK_DATAENDIE : stm32f10x.h
  • SDIO_MASK_DBCKENDIE : stm32f10x.h
  • SDIO_MASK_DCRCFAILIE : stm32f10x.h
  • SDIO_MASK_DTIMEOUTIE : stm32f10x.h
  • SDIO_MASK_RXACTIE : stm32f10x.h
  • SDIO_MASK_RXDAVLIE : stm32f10x.h
  • SDIO_MASK_RXFIFOEIE : stm32f10x.h
  • SDIO_MASK_RXFIFOFIE : stm32f10x.h
  • SDIO_MASK_RXFIFOHFIE : stm32f10x.h
  • SDIO_MASK_RXOVERRIE : stm32f10x.h
  • SDIO_MASK_SDIOITIE : stm32f10x.h
  • SDIO_MASK_STBITERRIE : stm32f10x.h
  • SDIO_MASK_TXACTIE : stm32f10x.h
  • SDIO_MASK_TXDAVLIE : stm32f10x.h
  • SDIO_MASK_TXFIFOEIE : stm32f10x.h
  • SDIO_MASK_TXFIFOFIE : stm32f10x.h
  • SDIO_MASK_TXFIFOHEIE : stm32f10x.h
  • SDIO_MASK_TXUNDERRIE : stm32f10x.h
  • SDIO_MULTIMEDIA_CARD : stm32_eval_sdio_sd.h
  • SDIO_OFFSET : stm32f10x_sdio.c
  • SDIO_POWER_PWRCTRL : stm32f10x.h
  • SDIO_POWER_PWRCTRL_0 : stm32f10x.h
  • SDIO_POWER_PWRCTRL_1 : stm32f10x.h
  • SDIO_PowerState_OFF : stm32f10x_sdio.h
  • SDIO_PowerState_ON : stm32f10x_sdio.h
  • SDIO_ReadWaitMode_CLK : stm32f10x_sdio.h
  • SDIO_ReadWaitMode_DATA2 : stm32f10x_sdio.h
  • SDIO_RESP0_CARDSTATUS0 : stm32f10x.h
  • SDIO_RESP1 : stm32f10x_sdio.h
  • SDIO_RESP1_CARDSTATUS1 : stm32f10x.h
  • SDIO_RESP2 : stm32f10x_sdio.h
  • SDIO_RESP2_CARDSTATUS2 : stm32f10x.h
  • SDIO_RESP3 : stm32f10x_sdio.h
  • SDIO_RESP3_CARDSTATUS3 : stm32f10x.h
  • SDIO_RESP4 : stm32f10x_sdio.h
  • SDIO_RESP4_CARDSTATUS4 : stm32f10x.h
  • SDIO_RESP_ADDR : stm32f10x_sdio.c
  • SDIO_RESPCMD_RESPCMD : stm32f10x.h
  • SDIO_Response_Long : stm32f10x_sdio.h
  • SDIO_Response_No : stm32f10x_sdio.h
  • SDIO_Response_Short : stm32f10x_sdio.h
  • SDIO_SECURE_DIGITAL_IO_CARD : stm32_eval_sdio_sd.h
  • SDIO_SECURE_DIGITAL_IO_COMBO_CARD : stm32_eval_sdio_sd.h
  • SDIO_SEND_IF_COND : stm32_eval_sdio_sd.c
  • SDIO_STA_CCRCFAIL : stm32f10x.h
  • SDIO_STA_CEATAEND : stm32f10x.h
  • SDIO_STA_CMDACT : stm32f10x.h
  • SDIO_STA_CMDREND : stm32f10x.h
  • SDIO_STA_CMDSENT : stm32f10x.h
  • SDIO_STA_CTIMEOUT : stm32f10x.h
  • SDIO_STA_DATAEND : stm32f10x.h
  • SDIO_STA_DBCKEND : stm32f10x.h
  • SDIO_STA_DCRCFAIL : stm32f10x.h
  • SDIO_STA_DTIMEOUT : stm32f10x.h
  • SDIO_STA_RXACT : stm32f10x.h
  • SDIO_STA_RXDAVL : stm32f10x.h
  • SDIO_STA_RXFIFOE : stm32f10x.h
  • SDIO_STA_RXFIFOF : stm32f10x.h
  • SDIO_STA_RXFIFOHF : stm32f10x.h
  • SDIO_STA_RXOVERR : stm32f10x.h
  • SDIO_STA_SDIOIT : stm32f10x.h
  • SDIO_STA_STBITERR : stm32f10x.h
  • SDIO_STA_TXACT : stm32f10x.h
  • SDIO_STA_TXDAVL : stm32f10x.h
  • SDIO_STA_TXFIFOE : stm32f10x.h
  • SDIO_STA_TXFIFOF : stm32f10x.h
  • SDIO_STA_TXFIFOHE : stm32f10x.h
  • SDIO_STA_TXUNDERR : stm32f10x.h
  • SDIO_STATIC_FLAGS : stm32_eval_sdio_sd.c
  • SDIO_STD_CAPACITY_SD_CARD_V1_1 : stm32_eval_sdio_sd.h
  • SDIO_STD_CAPACITY_SD_CARD_V2_0 : stm32_eval_sdio_sd.h
  • SDIO_TRANSFER_CLK_DIV : stm3210e_eval.h
  • SDIO_TransferDir_ToCard : stm32f10x_sdio.h
  • SDIO_TransferDir_ToSDIO : stm32f10x_sdio.h
  • SDIO_TransferMode_Block : stm32f10x_sdio.h
  • SDIO_TransferMode_Stream : stm32f10x_sdio.h
  • SDIO_Wait_IT : stm32f10x_sdio.h
  • SDIO_Wait_No : stm32f10x_sdio.h
  • SDIO_Wait_Pend : stm32f10x_sdio.h
  • SDIOEN_BitNumber : stm32f10x_sdio.c
  • SDIOSUSPEND_BitNumber : stm32f10x_sdio.c
  • sEE_DIRECTION_RX : stm32100e_eval.h , stm3210c_eval.h , stm32l152_eval.h
  • sEE_DIRECTION_TX : stm32100e_eval.h , stm3210c_eval.h , stm32l152_eval.h
  • sEE_FAIL : stm32_eval_i2c_ee.h , stm32l152_eval_i2c_ee.h
  • sEE_FLAG_TIMEOUT : stm32_eval_i2c_ee.h , stm32l152_eval_i2c_ee.h
  • sEE_HW_ADDRESS : stm32_eval_i2c_ee.h
  • sEE_I2C : stm32100e_eval.h , stm3210c_eval.h , stm32l152_eval.h
  • sEE_I2C_CLK : stm3210c_eval.h , stm32l152_eval.h , stm32100e_eval.h
  • sEE_I2C_DMA : stm32100e_eval.h , stm32l152_eval.h , stm3210c_eval.h
  • sEE_I2C_DMA_CHANNEL_RX : stm32100e_eval.h , stm3210c_eval.h , stm32l152_eval.h
  • sEE_I2C_DMA_CHANNEL_TX : stm32100e_eval.h , stm3210c_eval.h , stm32l152_eval.h
  • sEE_I2C_DMA_CLK : stm3210c_eval.h , stm32l152_eval.h , stm32100e_eval.h
  • sEE_I2C_DMA_FLAG_RX_GL : stm32100e_eval.h , stm32l152_eval.h , stm3210c_eval.h
  • sEE_I2C_DMA_FLAG_RX_TC : stm32100e_eval.h , stm3210c_eval.h , stm32l152_eval.h
  • sEE_I2C_DMA_FLAG_TX_GL : stm32100e_eval.h , stm3210c_eval.h , stm32l152_eval.h
  • sEE_I2C_DMA_FLAG_TX_TC : stm32100e_eval.h , stm3210c_eval.h , stm32l152_eval.h
  • sEE_I2C_DMA_PREPRIO : stm32100e_eval.h , stm32l152_eval.h , stm3210c_eval.h
  • sEE_I2C_DMA_RX_IRQHandler : stm32100e_eval.h , stm3210c_eval.h , stm32l152_eval.h
  • sEE_I2C_DMA_RX_IRQn : stm32100e_eval.h , stm3210c_eval.h , stm32l152_eval.h
  • sEE_I2C_DMA_SUBPRIO : stm3210c_eval.h , stm32l152_eval.h , stm32100e_eval.h
  • sEE_I2C_DMA_TX_IRQHandler : stm32100e_eval.h , stm3210c_eval.h , stm32l152_eval.h
  • sEE_I2C_DMA_TX_IRQn : stm32100e_eval.h , stm3210c_eval.h , stm32l152_eval.h
  • sEE_I2C_DR_Address : stm32100e_eval.h , stm3210c_eval.h , stm32l152_eval.h
  • sEE_I2C_SCL_AF : stm32l152_eval.h
  • sEE_I2C_SCL_GPIO_CLK : stm32100e_eval.h , stm3210c_eval.h , stm32l152_eval.h
  • sEE_I2C_SCL_GPIO_PORT : stm3210c_eval.h , stm32l152_eval.h , stm32100e_eval.h
  • sEE_I2C_SCL_PIN : stm32100e_eval.h , stm3210c_eval.h , stm32l152_eval.h
  • sEE_I2C_SCL_SOURCE : stm32l152_eval.h
  • sEE_I2C_SDA_AF : stm32l152_eval.h
  • sEE_I2C_SDA_GPIO_CLK : stm3210c_eval.h , stm32l152_eval.h , stm32100e_eval.h
  • sEE_I2C_SDA_GPIO_PORT : stm32100e_eval.h , stm32l152_eval.h , stm3210c_eval.h
  • sEE_I2C_SDA_PIN : stm32100e_eval.h , stm3210c_eval.h , stm32l152_eval.h
  • sEE_I2C_SDA_SOURCE : stm32l152_eval.h
  • sEE_LONG_TIMEOUT : stm32_eval_i2c_ee.h , stm32l152_eval_i2c_ee.h
  • sEE_M24C64_32 : stm32_eval_i2c_ee.h , stm32100e_eval.h , stm3210c_eval.h , stm32l152_eval.h , stm32l152_eval_i2c_ee.h
  • sEE_MAX_TRIALS_NUMBER : stm32_eval_i2c_ee.h , stm32l152_eval_i2c_ee.h
  • sEE_OK : stm32_eval_i2c_ee.h , stm32l152_eval_i2c_ee.h
  • sEE_PAGESIZE : stm32_eval_i2c_ee.h
  • sEE_READ_ADDRESS1 : STM32F10x_StdPeriph_Examples/I2C/EEPROM/main.c
  • sEE_READ_ADDRESS2 : STM32F10x_StdPeriph_Examples/I2C/EEPROM/main.c
  • sEE_STATE_BUSY : stm32l152_eval_i2c_ee.h , stm32_eval_i2c_ee.h
  • sEE_STATE_ERROR : stm32_eval_i2c_ee.h , stm32l152_eval_i2c_ee.h
  • sEE_STATE_READY : stm32_eval_i2c_ee.h , stm32l152_eval_i2c_ee.h
  • sEE_TIME_CONST : stm32100e_eval.h , stm3210c_eval.h , stm32l152_eval.h
  • sEE_USE_DMA : stm32100e_eval.h , stm3210c_eval.h , stm32l152_eval.h
  • sEE_WRITE_ADDRESS1 : STM32F10x_StdPeriph_Examples/I2C/EEPROM/main.c
  • sEE_WRITE_ADDRESS2 : STM32F10x_StdPeriph_Examples/I2C/EEPROM/main.c
  • SEL_BUTTON_EXTI_IRQn : stm32100b_eval.h , stm32100e_eval.h , stm3210e_eval.h , stm32l152_eval.h , stm3210b_eval.h
  • SEL_BUTTON_EXTI_LINE : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210e_eval.h , stm32l152_eval.h
  • SEL_BUTTON_EXTI_PIN_SOURCE : stm3210b_eval.h , stm32100e_eval.h , stm3210e_eval.h , stm32100b_eval.h , stm32l152_eval.h
  • SEL_BUTTON_EXTI_PORT_SOURCE : stm3210b_eval.h , stm32100b_eval.h , stm32l152_eval.h , stm3210e_eval.h , stm32100e_eval.h
  • SEL_BUTTON_GPIO_CLK : stm32l152_eval.h , stm32100e_eval.h , stm32100b_eval.h , stm3210e_eval.h , stm3210b_eval.h
  • SEL_BUTTON_GPIO_PORT : stm32100b_eval.h , stm32l152_eval.h , stm3210b_eval.h , stm32100e_eval.h , stm3210e_eval.h
  • SEL_BUTTON_PIN : stm32100b_eval.h , stm3210e_eval.h , stm32100e_eval.h , stm32l152_eval.h , stm3210b_eval.h
  • SET_BIT : stm32f10x.h
  • SET_INDEX : stm32100b_eval_lcd.c , stm3210b_eval_lcd.c , stm32l152_eval_lcd.c , stm3210c_eval_lcd.c
  • SETUP_LENGHT : STM32F10x_StdPeriph_Examples/USART/Smartcard/main.c
  • sFLASH_CMD_BE : stm32_eval_spi_flash.h
  • sFLASH_CMD_RDID : stm32_eval_spi_flash.h
  • sFLASH_CMD_RDSR : stm32_eval_spi_flash.h
  • sFLASH_CMD_READ : stm32_eval_spi_flash.h
  • sFLASH_CMD_SE : stm32_eval_spi_flash.h
  • sFLASH_CMD_WREN : stm32_eval_spi_flash.h
  • sFLASH_CMD_WRITE : stm32_eval_spi_flash.h
  • sFLASH_CMD_WRSR : stm32_eval_spi_flash.h
  • sFLASH_CS_GPIO_CLK : stm32100b_eval.h , stm3210b_eval.h , stm3210e_eval.h , stm32100e_eval.h
  • sFLASH_CS_GPIO_PORT : stm3210e_eval.h , stm32100b_eval.h , stm3210b_eval.h , stm32100e_eval.h
  • sFLASH_CS_HIGH : stm32_eval_spi_flash.h
  • sFLASH_CS_LOW : stm32_eval_spi_flash.h
  • sFLASH_CS_PIN : stm3210e_eval.h , stm3210b_eval.h , stm32100b_eval.h , stm32100e_eval.h
  • sFLASH_DUMMY_BYTE : stm32_eval_spi_flash.h
  • sFLASH_ID : STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/main.c
  • sFLASH_M25P128_ID : stm32_eval_spi_flash.h
  • sFLASH_M25P64_ID : stm32_eval_spi_flash.h
  • sFLASH_SPI : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210e_eval.h
  • sFLASH_SPI_CLK : stm32100e_eval.h , stm3210b_eval.h , stm32100b_eval.h , stm3210e_eval.h
  • sFLASH_SPI_MISO_GPIO_CLK : stm32100e_eval.h , stm32100b_eval.h , stm3210b_eval.h , stm3210e_eval.h
  • sFLASH_SPI_MISO_GPIO_PORT : stm3210b_eval.h , stm32100b_eval.h , stm3210e_eval.h , stm32100e_eval.h
  • sFLASH_SPI_MISO_PIN : stm3210b_eval.h , stm32100b_eval.h , stm32100e_eval.h , stm3210e_eval.h
  • sFLASH_SPI_MOSI_GPIO_CLK : stm32100e_eval.h , stm3210b_eval.h , stm32100b_eval.h , stm3210e_eval.h
  • sFLASH_SPI_MOSI_GPIO_PORT : stm32100b_eval.h , stm3210b_eval.h , stm32100e_eval.h , stm3210e_eval.h
  • sFLASH_SPI_MOSI_PIN : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210e_eval.h
  • sFLASH_SPI_PAGESIZE : stm32_eval_spi_flash.h
  • sFLASH_SPI_SCK_GPIO_CLK : stm32100e_eval.h , stm32100b_eval.h , stm3210e_eval.h , stm3210b_eval.h
  • sFLASH_SPI_SCK_GPIO_PORT : stm32100b_eval.h , stm32100e_eval.h , stm3210e_eval.h , stm3210b_eval.h
  • sFLASH_SPI_SCK_PIN : stm32100e_eval.h , stm3210e_eval.h , stm3210b_eval.h , stm32100b_eval.h
  • sFLASH_WIP_FLAG : stm32_eval_spi_flash.h
  • SLAK_TIMEOUT : stm32f10x_can.c
  • SMCR_ETR_Mask : stm32f10x_tim.c
  • SMPR1_SMP_Set : stm32f10x_adc.c
  • SMPR2_SMP_Set : stm32f10x_adc.c
  • SP_MAIN : STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/main.c
  • SP_PROCESS : STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/main.c
  • SP_PROCESS_SIZE : STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/main.c
  • SPI1 : stm32f10x.h
  • SPI1_BASE : stm32f10x.h
  • SPI2 : stm32f10x.h
  • SPI2_BASE : stm32f10x.h
  • SPI3 : stm32f10x.h
  • SPI3_BASE : stm32f10x.h
  • SPI_BaudRatePrescaler_128 : stm32f10x_spi.h
  • SPI_BaudRatePrescaler_16 : stm32f10x_spi.h
  • SPI_BaudRatePrescaler_2 : stm32f10x_spi.h
  • SPI_BaudRatePrescaler_256 : stm32f10x_spi.h
  • SPI_BaudRatePrescaler_32 : stm32f10x_spi.h
  • SPI_BaudRatePrescaler_4 : stm32f10x_spi.h
  • SPI_BaudRatePrescaler_64 : stm32f10x_spi.h
  • SPI_BaudRatePrescaler_8 : stm32f10x_spi.h
  • SPI_CPHA_1Edge : stm32f10x_spi.h
  • SPI_CPHA_2Edge : stm32f10x_spi.h
  • SPI_CPOL_High : stm32f10x_spi.h
  • SPI_CPOL_Low : stm32f10x_spi.h
  • SPI_CR1_BIDIMODE : stm32f10x.h
  • SPI_CR1_BIDIOE : stm32f10x.h
  • SPI_CR1_BR : stm32f10x.h
  • SPI_CR1_BR_0 : stm32f10x.h
  • SPI_CR1_BR_1 : stm32f10x.h
  • SPI_CR1_BR_2 : stm32f10x.h
  • SPI_CR1_CPHA : stm32f10x.h
  • SPI_CR1_CPOL : stm32f10x.h
  • SPI_CR1_CRCEN : stm32f10x.h
  • SPI_CR1_CRCNEXT : stm32f10x.h
  • SPI_CR1_DFF : stm32f10x.h
  • SPI_CR1_LSBFIRST : stm32f10x.h
  • SPI_CR1_MSTR : stm32f10x.h
  • SPI_CR1_RXONLY : stm32f10x.h
  • SPI_CR1_SPE : stm32f10x.h
  • SPI_CR1_SSI : stm32f10x.h
  • SPI_CR1_SSM : stm32f10x.h
  • SPI_CR2_ERRIE : stm32f10x.h
  • SPI_CR2_RXDMAEN : stm32f10x.h
  • SPI_CR2_RXNEIE : stm32f10x.h
  • SPI_CR2_SSOE : stm32f10x.h
  • SPI_CR2_TXDMAEN : stm32f10x.h
  • SPI_CR2_TXEIE : stm32f10x.h
  • SPI_CRC_Rx : stm32f10x_spi.h
  • SPI_CRC_Tx : stm32f10x_spi.h
  • SPI_CRCPR_CRCPOLY : stm32f10x.h
  • SPI_DataSize_16b : stm32f10x_spi.h
  • SPI_DataSize_8b : stm32f10x_spi.h
  • SPI_Direction_1Line_Rx : stm32f10x_spi.h
  • SPI_Direction_1Line_Tx : stm32f10x_spi.h
  • SPI_Direction_2Lines_FullDuplex : stm32f10x_spi.h
  • SPI_Direction_2Lines_RxOnly : stm32f10x_spi.h
  • SPI_Direction_Rx : stm32f10x_spi.h
  • SPI_Direction_Tx : stm32f10x_spi.h
  • SPI_DR_DR : stm32f10x.h
  • SPI_FirstBit_LSB : stm32f10x_spi.h
  • SPI_FirstBit_MSB : stm32f10x_spi.h
  • SPI_FLAG_CRCERR : stm32f10x_spi.h
  • SPI_FLAG_MODF : stm32f10x_spi.h
  • SPI_I2S_DMAReq_Rx : stm32f10x_spi.h
  • SPI_I2S_DMAReq_Tx : stm32f10x_spi.h
  • SPI_I2S_FLAG_BSY : stm32f10x_spi.h
  • SPI_I2S_FLAG_OVR : stm32f10x_spi.h
  • SPI_I2S_FLAG_RXNE : stm32f10x_spi.h
  • SPI_I2S_FLAG_TXE : stm32f10x_spi.h
  • SPI_I2S_IT_ERR : stm32f10x_spi.h
  • SPI_I2S_IT_OVR : stm32f10x_spi.h
  • SPI_I2S_IT_RXNE : stm32f10x_spi.h
  • SPI_I2S_IT_TXE : stm32f10x_spi.h
  • SPI_I2SCFGR_CHLEN : stm32f10x.h
  • SPI_I2SCFGR_CKPOL : stm32f10x.h
  • SPI_I2SCFGR_DATLEN : stm32f10x.h
  • SPI_I2SCFGR_DATLEN_0 : stm32f10x.h
  • SPI_I2SCFGR_DATLEN_1 : stm32f10x.h
  • SPI_I2SCFGR_I2SCFG : stm32f10x.h
  • SPI_I2SCFGR_I2SCFG_0 : stm32f10x.h
  • SPI_I2SCFGR_I2SCFG_1 : stm32f10x.h
  • SPI_I2SCFGR_I2SE : stm32f10x.h
  • SPI_I2SCFGR_I2SMOD : stm32f10x.h
  • SPI_I2SCFGR_I2SSTD : stm32f10x.h
  • SPI_I2SCFGR_I2SSTD_0 : stm32f10x.h
  • SPI_I2SCFGR_I2SSTD_1 : stm32f10x.h
  • SPI_I2SCFGR_PCMSYNC : stm32f10x.h
  • SPI_I2SPR_I2SDIV : stm32f10x.h
  • SPI_I2SPR_MCKOE : stm32f10x.h
  • SPI_I2SPR_ODD : stm32f10x.h
  • SPI_IT_CRCERR : stm32f10x_spi.h
  • SPI_IT_MODF : stm32f10x_spi.h
  • SPI_Mode_Master : stm32f10x_spi.h
  • SPI_Mode_Select : stm32f10x_spi.c
  • SPI_Mode_Slave : stm32f10x_spi.h
  • SPI_NSS_Hard : stm32f10x_spi.h
  • SPI_NSS_Soft : stm32f10x_spi.h
  • SPI_NSSInternalSoft_Reset : stm32f10x_spi.h
  • SPI_NSSInternalSoft_Set : stm32f10x_spi.h
  • SPI_RXCRCR_RXCRC : stm32f10x.h
  • SPI_SR_BSY : stm32f10x.h
  • SPI_SR_CHSIDE : stm32f10x.h
  • SPI_SR_CRCERR : stm32f10x.h
  • SPI_SR_MODF : stm32f10x.h
  • SPI_SR_OVR : stm32f10x.h
  • SPI_SR_RXNE : stm32f10x.h
  • SPI_SR_TXE : stm32f10x.h
  • SPI_SR_UDR : stm32f10x.h
  • SPI_TXCRCR_TXCRC : stm32f10x.h
  • SQR1_CLEAR_Mask : stm32f10x_adc.c
  • SQR1_SQ_Set : stm32f10x_adc.c
  • SQR2_SQ_Set : stm32f10x_adc.c
  • SQR3_SQ_Set : stm32f10x_adc.c
  • SRAM_BASE : stm32f10x.h
  • SRAM_BB_BASE : stm32f10x.h
  • START_BYTE : stm32l152_eval_lcd.c , stm3210c_eval_lcd.c , stm32100b_eval_lcd.c , stm3210b_eval_lcd.c
  • STMPE811_ID : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • SYSCLK_FREQ_24MHz : RCC/RCC_ClockConfig/main.h
  • SYSCLK_FREQ_56MHz : Project/STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/system_stm32f10x.c
  • SYSCLK_FREQ_72MHz : Project/STM32F10x_StdPeriph_Examples/USART/Printf/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/SysTick/TimeBase/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Input/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/DMABurst/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/DMA_Polling/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/RTC/Calendar/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/CortexM3/BitBand/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/OCToggle/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/FSMC/NOR/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/FLASH/Program/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/OCActive/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Output/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/CAN/LoopBack/system_stm32f10x.c , Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/PWR/STANDBY/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/CAN/DualCAN/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/Interrupt/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/I2C/IOExpander/system_stm32f10x.c , RCC/RCC_ClockConfig/main.h , Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Template/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/GPIO/IOToggle/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/CAN/Networking/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/DMA/FSMC/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/SDIO/uSDCard/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/6Steps/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/TimeBase/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/FSMC/OneNAND/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/HalfDuplex/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/CortexM3/MPU/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/PWR/STOP/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/SPI/CRC/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/InputCapture/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/OnePulse/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/Smartcard/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/I2C/EEPROM/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/PWR/PVD/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/FSMC/NAND/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/MultiProcessor/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/BKP/Tamper/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/Synchronous/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/Polling/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/SPI/DMA/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/DMA/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/I2S/Interrupt/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/BKP/Backup_Data/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/OCInactive/system_stm32f10x.c
  • SysTick_CALIB_NOREF : stm32f10x.h
  • SysTick_CALIB_SKEW : stm32f10x.h
  • SysTick_CALIB_TENMS : stm32f10x.h
  • SysTick_CLKSource_HCLK : misc.h
  • SysTick_CLKSource_HCLK_Div8 : misc.h
  • SysTick_CTRL_CLKSOURCE : stm32f10x.h
  • SysTick_CTRL_COUNTFLAG : stm32f10x.h
  • SysTick_CTRL_ENABLE : stm32f10x.h
  • SysTick_CTRL_TICKINT : stm32f10x.h
  • SysTick_LOAD_RELOAD : stm32f10x.h
  • SysTick_VAL_CURRENT : stm32f10x.h


STM32F10x Standard Peripherals Firmware Library: Globals

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- t -

  • T0_PROTOCOL : STM32F10x_StdPeriph_Examples/USART/Smartcard/main.c
  • TAMPER_BUTTON_EXTI_IRQn : stm32100b_eval.h , stm3210b_eval.h , stm3210c_eval.h , stm32100e_eval.h , stm3210e_eval.h
  • TAMPER_BUTTON_EXTI_LINE : stm32100e_eval.h , stm3210b_eval.h , stm3210c_eval.h , stm3210e_eval.h , stm32100b_eval.h
  • TAMPER_BUTTON_EXTI_PIN_SOURCE : stm3210e_eval.h , stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210c_eval.h
  • TAMPER_BUTTON_EXTI_PORT_SOURCE : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210c_eval.h , stm3210e_eval.h
  • TAMPER_BUTTON_GPIO_CLK : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210c_eval.h , stm3210e_eval.h
  • TAMPER_BUTTON_GPIO_PORT : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210c_eval.h , stm3210e_eval.h
  • TAMPER_BUTTON_PIN : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210c_eval.h , stm3210e_eval.h
  • TEF_BitNumber : stm32f10x_bkp.c
  • TEMPERATURE_THYS : STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/main.c
  • TEMPERATURE_TOS : STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/main.c
  • TEOM_BitNumber : stm32f10x_cec.c
  • THREAD_MODE_PRIVILEGED : STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/main.c
  • THREAD_MODE_UNPRIVILEGED : STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/main.c
  • TIF_BitNumber : stm32f10x_bkp.c
  • TIM1 : stm32f10x.h
  • TIM10 : stm32f10x.h
  • TIM10_BASE : stm32f10x.h
  • TIM11 : stm32f10x.h
  • TIM11_BASE : stm32f10x.h
  • TIM12 : stm32f10x.h
  • TIM12_BASE : stm32f10x.h
  • TIM13 : stm32f10x.h
  • TIM13_BASE : stm32f10x.h
  • TIM14 : stm32f10x.h
  • TIM14_BASE : stm32f10x.h
  • TIM15 : stm32f10x.h
  • TIM15_BASE : stm32f10x.h
  • TIM16 : stm32f10x.h
  • TIM16_BASE : stm32f10x.h
  • TIM17 : stm32f10x.h
  • TIM17_BASE : stm32f10x.h
  • TIM1_BASE : stm32f10x.h
  • TIM1_CCR1_Address : STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/main.c
  • TIM1_CCR3_Address : STM32F10x_StdPeriph_Examples/TIM/DMA/main.c
  • TIM1_DMAR_ADDRESS : STM32F10x_StdPeriph_Examples/TIM/DMABurst/main.c
  • TIM2 : stm32f10x.h
  • TIM2_BASE : stm32f10x.h
  • TIM3 : stm32f10x.h
  • TIM3_BASE : stm32f10x.h
  • TIM4 : stm32f10x.h
  • TIM4_BASE : stm32f10x.h
  • TIM5 : stm32f10x.h
  • TIM5_BASE : stm32f10x.h
  • TIM6 : stm32f10x.h
  • TIM6_BASE : stm32f10x.h
  • TIM7 : stm32f10x.h
  • TIM7_BASE : stm32f10x.h
  • TIM8 : stm32f10x.h
  • TIM8_BASE : stm32f10x.h
  • TIM9 : stm32f10x.h
  • TIM9_BASE : stm32f10x.h
  • TIM_ARR_ARR : stm32f10x.h
  • TIM_AutomaticOutput_Disable : stm32f10x_tim.h
  • TIM_AutomaticOutput_Enable : stm32f10x_tim.h
  • TIM_BDTR_AOE : stm32f10x.h
  • TIM_BDTR_BKE : stm32f10x.h
  • TIM_BDTR_BKP : stm32f10x.h
  • TIM_BDTR_DTG : stm32f10x.h
  • TIM_BDTR_DTG_0 : stm32f10x.h
  • TIM_BDTR_DTG_1 : stm32f10x.h
  • TIM_BDTR_DTG_2 : stm32f10x.h
  • TIM_BDTR_DTG_3 : stm32f10x.h
  • TIM_BDTR_DTG_4 : stm32f10x.h
  • TIM_BDTR_DTG_5 : stm32f10x.h
  • TIM_BDTR_DTG_6 : stm32f10x.h
  • TIM_BDTR_DTG_7 : stm32f10x.h
  • TIM_BDTR_LOCK : stm32f10x.h
  • TIM_BDTR_LOCK_0 : stm32f10x.h
  • TIM_BDTR_LOCK_1 : stm32f10x.h
  • TIM_BDTR_MOE : stm32f10x.h
  • TIM_BDTR_OSSI : stm32f10x.h
  • TIM_BDTR_OSSR : stm32f10x.h
  • TIM_Break_Disable : stm32f10x_tim.h
  • TIM_Break_Enable : stm32f10x_tim.h
  • TIM_BreakPolarity_High : stm32f10x_tim.h
  • TIM_BreakPolarity_Low : stm32f10x_tim.h
  • TIM_CCER_CC1E : stm32f10x.h
  • TIM_CCER_CC1NE : stm32f10x.h
  • TIM_CCER_CC1NP : stm32f10x.h
  • TIM_CCER_CC1P : stm32f10x.h
  • TIM_CCER_CC2E : stm32f10x.h
  • TIM_CCER_CC2NE : stm32f10x.h
  • TIM_CCER_CC2NP : stm32f10x.h
  • TIM_CCER_CC2P : stm32f10x.h
  • TIM_CCER_CC3E : stm32f10x.h
  • TIM_CCER_CC3NE : stm32f10x.h
  • TIM_CCER_CC3NP : stm32f10x.h
  • TIM_CCER_CC3P : stm32f10x.h
  • TIM_CCER_CC4E : stm32f10x.h
  • TIM_CCER_CC4NP : stm32f10x.h
  • TIM_CCER_CC4P : stm32f10x.h
  • TIM_CCMR1_CC1S : stm32f10x.h
  • TIM_CCMR1_CC1S_0 : stm32f10x.h
  • TIM_CCMR1_CC1S_1 : stm32f10x.h
  • TIM_CCMR1_CC2S : stm32f10x.h
  • TIM_CCMR1_CC2S_0 : stm32f10x.h
  • TIM_CCMR1_CC2S_1 : stm32f10x.h
  • TIM_CCMR1_IC1F : stm32f10x.h
  • TIM_CCMR1_IC1F_0 : stm32f10x.h
  • TIM_CCMR1_IC1F_1 : stm32f10x.h
  • TIM_CCMR1_IC1F_2 : stm32f10x.h
  • TIM_CCMR1_IC1F_3 : stm32f10x.h
  • TIM_CCMR1_IC1PSC : stm32f10x.h
  • TIM_CCMR1_IC1PSC_0 : stm32f10x.h
  • TIM_CCMR1_IC1PSC_1 : stm32f10x.h
  • TIM_CCMR1_IC2F : stm32f10x.h
  • TIM_CCMR1_IC2F_0 : stm32f10x.h
  • TIM_CCMR1_IC2F_1 : stm32f10x.h
  • TIM_CCMR1_IC2F_2 : stm32f10x.h
  • TIM_CCMR1_IC2F_3 : stm32f10x.h
  • TIM_CCMR1_IC2PSC : stm32f10x.h
  • TIM_CCMR1_IC2PSC_0 : stm32f10x.h
  • TIM_CCMR1_IC2PSC_1 : stm32f10x.h
  • TIM_CCMR1_OC1CE : stm32f10x.h
  • TIM_CCMR1_OC1FE : stm32f10x.h
  • TIM_CCMR1_OC1M : stm32f10x.h
  • TIM_CCMR1_OC1M_0 : stm32f10x.h
  • TIM_CCMR1_OC1M_1 : stm32f10x.h
  • TIM_CCMR1_OC1M_2 : stm32f10x.h
  • TIM_CCMR1_OC1PE : stm32f10x.h
  • TIM_CCMR1_OC2CE : stm32f10x.h
  • TIM_CCMR1_OC2FE : stm32f10x.h
  • TIM_CCMR1_OC2M : stm32f10x.h
  • TIM_CCMR1_OC2M_0 : stm32f10x.h
  • TIM_CCMR1_OC2M_1 : stm32f10x.h
  • TIM_CCMR1_OC2M_2 : stm32f10x.h
  • TIM_CCMR1_OC2PE : stm32f10x.h
  • TIM_CCMR2_CC3S : stm32f10x.h
  • TIM_CCMR2_CC3S_0 : stm32f10x.h
  • TIM_CCMR2_CC3S_1 : stm32f10x.h
  • TIM_CCMR2_CC4S : stm32f10x.h
  • TIM_CCMR2_CC4S_0 : stm32f10x.h
  • TIM_CCMR2_CC4S_1 : stm32f10x.h
  • TIM_CCMR2_IC3F : stm32f10x.h
  • TIM_CCMR2_IC3F_0 : stm32f10x.h
  • TIM_CCMR2_IC3F_1 : stm32f10x.h
  • TIM_CCMR2_IC3F_2 : stm32f10x.h
  • TIM_CCMR2_IC3F_3 : stm32f10x.h
  • TIM_CCMR2_IC3PSC : stm32f10x.h
  • TIM_CCMR2_IC3PSC_0 : stm32f10x.h
  • TIM_CCMR2_IC3PSC_1 : stm32f10x.h
  • TIM_CCMR2_IC4F : stm32f10x.h
  • TIM_CCMR2_IC4F_0 : stm32f10x.h
  • TIM_CCMR2_IC4F_1 : stm32f10x.h
  • TIM_CCMR2_IC4F_2 : stm32f10x.h
  • TIM_CCMR2_IC4F_3 : stm32f10x.h
  • TIM_CCMR2_IC4PSC : stm32f10x.h
  • TIM_CCMR2_IC4PSC_0 : stm32f10x.h
  • TIM_CCMR2_IC4PSC_1 : stm32f10x.h
  • TIM_CCMR2_OC3CE : stm32f10x.h
  • TIM_CCMR2_OC3FE : stm32f10x.h
  • TIM_CCMR2_OC3M : stm32f10x.h
  • TIM_CCMR2_OC3M_0 : stm32f10x.h
  • TIM_CCMR2_OC3M_1 : stm32f10x.h
  • TIM_CCMR2_OC3M_2 : stm32f10x.h
  • TIM_CCMR2_OC3PE : stm32f10x.h
  • TIM_CCMR2_OC4CE : stm32f10x.h
  • TIM_CCMR2_OC4FE : stm32f10x.h
  • TIM_CCMR2_OC4M : stm32f10x.h
  • TIM_CCMR2_OC4M_0 : stm32f10x.h
  • TIM_CCMR2_OC4M_1 : stm32f10x.h
  • TIM_CCMR2_OC4M_2 : stm32f10x.h
  • TIM_CCMR2_OC4PE : stm32f10x.h
  • TIM_CCR1_CCR1 : stm32f10x.h
  • TIM_CCR2_CCR2 : stm32f10x.h
  • TIM_CCR3_CCR3 : stm32f10x.h
  • TIM_CCR4_CCR4 : stm32f10x.h
  • TIM_CCx_Disable : stm32f10x_tim.h
  • TIM_CCx_Enable : stm32f10x_tim.h
  • TIM_CCxN_Disable : stm32f10x_tim.h
  • TIM_CCxN_Enable : stm32f10x_tim.h
  • TIM_Channel_1 : stm32f10x_tim.h
  • TIM_Channel_2 : stm32f10x_tim.h
  • TIM_Channel_3 : stm32f10x_tim.h
  • TIM_Channel_4 : stm32f10x_tim.h
  • TIM_CKD_DIV1 : stm32f10x_tim.h
  • TIM_CKD_DIV2 : stm32f10x_tim.h
  • TIM_CKD_DIV4 : stm32f10x_tim.h
  • TIM_CNT_CNT : stm32f10x.h
  • TIM_CounterMode_CenterAligned1 : stm32f10x_tim.h
  • TIM_CounterMode_CenterAligned2 : stm32f10x_tim.h
  • TIM_CounterMode_CenterAligned3 : stm32f10x_tim.h
  • TIM_CounterMode_Down : stm32f10x_tim.h
  • TIM_CounterMode_Up : stm32f10x_tim.h
  • TIM_CR1_ARPE : stm32f10x.h
  • TIM_CR1_CEN : stm32f10x.h
  • TIM_CR1_CKD : stm32f10x.h
  • TIM_CR1_CKD_0 : stm32f10x.h
  • TIM_CR1_CKD_1 : stm32f10x.h
  • TIM_CR1_CMS : stm32f10x.h
  • TIM_CR1_CMS_0 : stm32f10x.h
  • TIM_CR1_CMS_1 : stm32f10x.h
  • TIM_CR1_DIR : stm32f10x.h
  • TIM_CR1_OPM : stm32f10x.h
  • TIM_CR1_UDIS : stm32f10x.h
  • TIM_CR1_URS : stm32f10x.h
  • TIM_CR2_CCDS : stm32f10x.h
  • TIM_CR2_CCPC : stm32f10x.h
  • TIM_CR2_CCUS : stm32f10x.h
  • TIM_CR2_MMS : stm32f10x.h
  • TIM_CR2_MMS_0 : stm32f10x.h
  • TIM_CR2_MMS_1 : stm32f10x.h
  • TIM_CR2_MMS_2 : stm32f10x.h
  • TIM_CR2_OIS1 : stm32f10x.h
  • TIM_CR2_OIS1N : stm32f10x.h
  • TIM_CR2_OIS2 : stm32f10x.h
  • TIM_CR2_OIS2N : stm32f10x.h
  • TIM_CR2_OIS3 : stm32f10x.h
  • TIM_CR2_OIS3N : stm32f10x.h
  • TIM_CR2_OIS4 : stm32f10x.h
  • TIM_CR2_TI1S : stm32f10x.h
  • TIM_DCR_DBA : stm32f10x.h
  • TIM_DCR_DBA_0 : stm32f10x.h
  • TIM_DCR_DBA_1 : stm32f10x.h
  • TIM_DCR_DBA_2 : stm32f10x.h
  • TIM_DCR_DBA_3 : stm32f10x.h
  • TIM_DCR_DBA_4 : stm32f10x.h
  • TIM_DCR_DBL : stm32f10x.h
  • TIM_DCR_DBL_0 : stm32f10x.h
  • TIM_DCR_DBL_1 : stm32f10x.h
  • TIM_DCR_DBL_2 : stm32f10x.h
  • TIM_DCR_DBL_3 : stm32f10x.h
  • TIM_DCR_DBL_4 : stm32f10x.h
  • TIM_DIER_BIE : stm32f10x.h
  • TIM_DIER_CC1DE : stm32f10x.h
  • TIM_DIER_CC1IE : stm32f10x.h
  • TIM_DIER_CC2DE : stm32f10x.h
  • TIM_DIER_CC2IE : stm32f10x.h
  • TIM_DIER_CC3DE : stm32f10x.h
  • TIM_DIER_CC3IE : stm32f10x.h
  • TIM_DIER_CC4DE : stm32f10x.h
  • TIM_DIER_CC4IE : stm32f10x.h
  • TIM_DIER_COMDE : stm32f10x.h
  • TIM_DIER_COMIE : stm32f10x.h
  • TIM_DIER_TDE : stm32f10x.h
  • TIM_DIER_TIE : stm32f10x.h
  • TIM_DIER_UDE : stm32f10x.h
  • TIM_DIER_UIE : stm32f10x.h
  • TIM_DMA_CC1 : stm32f10x_tim.h
  • TIM_DMA_CC2 : stm32f10x_tim.h
  • TIM_DMA_CC3 : stm32f10x_tim.h
  • TIM_DMA_CC4 : stm32f10x_tim.h
  • TIM_DMA_COM : stm32f10x_tim.h
  • TIM_DMA_Trigger : stm32f10x_tim.h
  • TIM_DMA_Update : stm32f10x_tim.h
  • TIM_DMABase_ARR : stm32f10x_tim.h
  • TIM_DMABase_BDTR : stm32f10x_tim.h
  • TIM_DMABase_CCER : stm32f10x_tim.h
  • TIM_DMABase_CCMR1 : stm32f10x_tim.h
  • TIM_DMABase_CCMR2 : stm32f10x_tim.h
  • TIM_DMABase_CCR1 : stm32f10x_tim.h
  • TIM_DMABase_CCR2 : stm32f10x_tim.h
  • TIM_DMABase_CCR3 : stm32f10x_tim.h
  • TIM_DMABase_CCR4 : stm32f10x_tim.h
  • TIM_DMABase_CNT : stm32f10x_tim.h
  • TIM_DMABase_CR1 : stm32f10x_tim.h
  • TIM_DMABase_CR2 : stm32f10x_tim.h
  • TIM_DMABase_DCR : stm32f10x_tim.h
  • TIM_DMABase_DIER : stm32f10x_tim.h
  • TIM_DMABase_EGR : stm32f10x_tim.h
  • TIM_DMABase_PSC : stm32f10x_tim.h
  • TIM_DMABase_RCR : stm32f10x_tim.h
  • TIM_DMABase_SMCR : stm32f10x_tim.h
  • TIM_DMABase_SR : stm32f10x_tim.h
  • TIM_DMABurstLength_10Bytes : stm32f10x_tim.h
  • TIM_DMABurstLength_10Transfers : stm32f10x_tim.h
  • TIM_DMABurstLength_11Bytes : stm32f10x_tim.h
  • TIM_DMABurstLength_11Transfers : stm32f10x_tim.h
  • TIM_DMABurstLength_12Bytes : stm32f10x_tim.h
  • TIM_DMABurstLength_12Transfers : stm32f10x_tim.h
  • TIM_DMABurstLength_13Bytes : stm32f10x_tim.h
  • TIM_DMABurstLength_13Transfers : stm32f10x_tim.h
  • TIM_DMABurstLength_14Bytes : stm32f10x_tim.h
  • TIM_DMABurstLength_14Transfers : stm32f10x_tim.h
  • TIM_DMABurstLength_15Bytes : stm32f10x_tim.h
  • TIM_DMABurstLength_15Transfers : stm32f10x_tim.h
  • TIM_DMABurstLength_16Bytes : stm32f10x_tim.h
  • TIM_DMABurstLength_16Transfers : stm32f10x_tim.h
  • TIM_DMABurstLength_17Bytes : stm32f10x_tim.h
  • TIM_DMABurstLength_17Transfers : stm32f10x_tim.h
  • TIM_DMABurstLength_18Bytes : stm32f10x_tim.h
  • TIM_DMABurstLength_18Transfers : stm32f10x_tim.h
  • TIM_DMABurstLength_1Byte : stm32f10x_tim.h
  • TIM_DMABurstLength_1Transfer : stm32f10x_tim.h
  • TIM_DMABurstLength_2Bytes : stm32f10x_tim.h
  • TIM_DMABurstLength_2Transfers : stm32f10x_tim.h
  • TIM_DMABurstLength_3Bytes : stm32f10x_tim.h
  • TIM_DMABurstLength_3Transfers : stm32f10x_tim.h
  • TIM_DMABurstLength_4Bytes : stm32f10x_tim.h
  • TIM_DMABurstLength_4Transfers : stm32f10x_tim.h
  • TIM_DMABurstLength_5Bytes : stm32f10x_tim.h
  • TIM_DMABurstLength_5Transfers : stm32f10x_tim.h
  • TIM_DMABurstLength_6Bytes : stm32f10x_tim.h
  • TIM_DMABurstLength_6Transfers : stm32f10x_tim.h
  • TIM_DMABurstLength_7Bytes : stm32f10x_tim.h
  • TIM_DMABurstLength_7Transfers : stm32f10x_tim.h
  • TIM_DMABurstLength_8Bytes : stm32f10x_tim.h
  • TIM_DMABurstLength_8Transfers : stm32f10x_tim.h
  • TIM_DMABurstLength_9Bytes : stm32f10x_tim.h
  • TIM_DMABurstLength_9Transfers : stm32f10x_tim.h
  • TIM_DMAR_DMAB : stm32f10x.h
  • TIM_EGR_BG : stm32f10x.h
  • TIM_EGR_CC1G : stm32f10x.h
  • TIM_EGR_CC2G : stm32f10x.h
  • TIM_EGR_CC3G : stm32f10x.h
  • TIM_EGR_CC4G : stm32f10x.h
  • TIM_EGR_COMG : stm32f10x.h
  • TIM_EGR_TG : stm32f10x.h
  • TIM_EGR_UG : stm32f10x.h
  • TIM_EncoderMode_TI1 : stm32f10x_tim.h
  • TIM_EncoderMode_TI12 : stm32f10x_tim.h
  • TIM_EncoderMode_TI2 : stm32f10x_tim.h
  • TIM_EventSource_Break : stm32f10x_tim.h
  • TIM_EventSource_CC1 : stm32f10x_tim.h
  • TIM_EventSource_CC2 : stm32f10x_tim.h
  • TIM_EventSource_CC3 : stm32f10x_tim.h
  • TIM_EventSource_CC4 : stm32f10x_tim.h
  • TIM_EventSource_COM : stm32f10x_tim.h
  • TIM_EventSource_Trigger : stm32f10x_tim.h
  • TIM_EventSource_Update : stm32f10x_tim.h
  • TIM_ExtTRGPolarity_Inverted : stm32f10x_tim.h
  • TIM_ExtTRGPolarity_NonInverted : stm32f10x_tim.h
  • TIM_ExtTRGPSC_DIV2 : stm32f10x_tim.h
  • TIM_ExtTRGPSC_DIV4 : stm32f10x_tim.h
  • TIM_ExtTRGPSC_DIV8 : stm32f10x_tim.h
  • TIM_ExtTRGPSC_OFF : stm32f10x_tim.h
  • TIM_FLAG_Break : stm32f10x_tim.h
  • TIM_FLAG_CC1 : stm32f10x_tim.h
  • TIM_FLAG_CC1OF : stm32f10x_tim.h
  • TIM_FLAG_CC2 : stm32f10x_tim.h
  • TIM_FLAG_CC2OF : stm32f10x_tim.h
  • TIM_FLAG_CC3 : stm32f10x_tim.h
  • TIM_FLAG_CC3OF : stm32f10x_tim.h
  • TIM_FLAG_CC4 : stm32f10x_tim.h
  • TIM_FLAG_CC4OF : stm32f10x_tim.h
  • TIM_FLAG_COM : stm32f10x_tim.h
  • TIM_FLAG_Trigger : stm32f10x_tim.h
  • TIM_FLAG_Update : stm32f10x_tim.h
  • TIM_ForcedAction_Active : stm32f10x_tim.h
  • TIM_ForcedAction_InActive : stm32f10x_tim.h
  • TIM_ICPolarity_BothEdge : stm32f10x_tim.h
  • TIM_ICPolarity_Falling : stm32f10x_tim.h
  • TIM_ICPolarity_Rising : stm32f10x_tim.h
  • TIM_ICPSC_DIV1 : stm32f10x_tim.h
  • TIM_ICPSC_DIV2 : stm32f10x_tim.h
  • TIM_ICPSC_DIV4 : stm32f10x_tim.h
  • TIM_ICPSC_DIV8 : stm32f10x_tim.h
  • TIM_ICSelection_DirectTI : stm32f10x_tim.h
  • TIM_ICSelection_IndirectTI : stm32f10x_tim.h
  • TIM_ICSelection_TRC : stm32f10x_tim.h
  • TIM_IT_Break : stm32f10x_tim.h
  • TIM_IT_CC1 : stm32f10x_tim.h
  • TIM_IT_CC2 : stm32f10x_tim.h
  • TIM_IT_CC3 : stm32f10x_tim.h
  • TIM_IT_CC4 : stm32f10x_tim.h
  • TIM_IT_COM : stm32f10x_tim.h
  • TIM_IT_Trigger : stm32f10x_tim.h
  • TIM_IT_Update : stm32f10x_tim.h
  • TIM_LOCKLevel_1 : stm32f10x_tim.h
  • TIM_LOCKLevel_2 : stm32f10x_tim.h
  • TIM_LOCKLevel_3 : stm32f10x_tim.h
  • TIM_LOCKLevel_OFF : stm32f10x_tim.h
  • TIM_MasterSlaveMode_Disable : stm32f10x_tim.h
  • TIM_MasterSlaveMode_Enable : stm32f10x_tim.h
  • TIM_OCClear_Disable : stm32f10x_tim.h
  • TIM_OCClear_Enable : stm32f10x_tim.h
  • TIM_OCFast_Disable : stm32f10x_tim.h
  • TIM_OCFast_Enable : stm32f10x_tim.h
  • TIM_OCIdleState_Reset : stm32f10x_tim.h
  • TIM_OCIdleState_Set : stm32f10x_tim.h
  • TIM_OCMode_Active : stm32f10x_tim.h
  • TIM_OCMode_Inactive : stm32f10x_tim.h
  • TIM_OCMode_PWM1 : stm32f10x_tim.h
  • TIM_OCMode_PWM2 : stm32f10x_tim.h
  • TIM_OCMode_Timing : stm32f10x_tim.h
  • TIM_OCMode_Toggle : stm32f10x_tim.h
  • TIM_OCNIdleState_Reset : stm32f10x_tim.h
  • TIM_OCNIdleState_Set : stm32f10x_tim.h
  • TIM_OCNPolarity_High : stm32f10x_tim.h
  • TIM_OCNPolarity_Low : stm32f10x_tim.h
  • TIM_OCPolarity_High : stm32f10x_tim.h
  • TIM_OCPolarity_Low : stm32f10x_tim.h
  • TIM_OCPreload_Disable : stm32f10x_tim.h
  • TIM_OCPreload_Enable : stm32f10x_tim.h
  • TIM_OPMode_Repetitive : stm32f10x_tim.h
  • TIM_OPMode_Single : stm32f10x_tim.h
  • TIM_OSSIState_Disable : stm32f10x_tim.h
  • TIM_OSSIState_Enable : stm32f10x_tim.h
  • TIM_OSSRState_Disable : stm32f10x_tim.h
  • TIM_OSSRState_Enable : stm32f10x_tim.h
  • TIM_OutputNState_Disable : stm32f10x_tim.h
  • TIM_OutputNState_Enable : stm32f10x_tim.h
  • TIM_OutputState_Disable : stm32f10x_tim.h
  • TIM_OutputState_Enable : stm32f10x_tim.h
  • TIM_PSC_PSC : stm32f10x.h
  • TIM_PSCReloadMode_Immediate : stm32f10x_tim.h
  • TIM_PSCReloadMode_Update : stm32f10x_tim.h
  • TIM_RCR_REP : stm32f10x.h
  • TIM_SlaveMode_External1 : stm32f10x_tim.h
  • TIM_SlaveMode_Gated : stm32f10x_tim.h
  • TIM_SlaveMode_Reset : stm32f10x_tim.h
  • TIM_SlaveMode_Trigger : stm32f10x_tim.h
  • TIM_SMCR_ECE : stm32f10x.h
  • TIM_SMCR_ETF : stm32f10x.h
  • TIM_SMCR_ETF_0 : stm32f10x.h
  • TIM_SMCR_ETF_1 : stm32f10x.h
  • TIM_SMCR_ETF_2 : stm32f10x.h
  • TIM_SMCR_ETF_3 : stm32f10x.h
  • TIM_SMCR_ETP : stm32f10x.h
  • TIM_SMCR_ETPS : stm32f10x.h
  • TIM_SMCR_ETPS_0 : stm32f10x.h
  • TIM_SMCR_ETPS_1 : stm32f10x.h
  • TIM_SMCR_MSM : stm32f10x.h
  • TIM_SMCR_SMS : stm32f10x.h
  • TIM_SMCR_SMS_0 : stm32f10x.h
  • TIM_SMCR_SMS_1 : stm32f10x.h
  • TIM_SMCR_SMS_2 : stm32f10x.h
  • TIM_SMCR_TS : stm32f10x.h
  • TIM_SMCR_TS_0 : stm32f10x.h
  • TIM_SMCR_TS_1 : stm32f10x.h
  • TIM_SMCR_TS_2 : stm32f10x.h
  • TIM_SR_BIF : stm32f10x.h
  • TIM_SR_CC1IF : stm32f10x.h
  • TIM_SR_CC1OF : stm32f10x.h
  • TIM_SR_CC2IF : stm32f10x.h
  • TIM_SR_CC2OF : stm32f10x.h
  • TIM_SR_CC3IF : stm32f10x.h
  • TIM_SR_CC3OF : stm32f10x.h
  • TIM_SR_CC4IF : stm32f10x.h
  • TIM_SR_CC4OF : stm32f10x.h
  • TIM_SR_COMIF : stm32f10x.h
  • TIM_SR_TIF : stm32f10x.h
  • TIM_SR_UIF : stm32f10x.h
  • TIM_TIxExternalCLK1Source_TI1 : stm32f10x_tim.h
  • TIM_TIxExternalCLK1Source_TI1ED : stm32f10x_tim.h
  • TIM_TIxExternalCLK1Source_TI2 : stm32f10x_tim.h
  • TIM_TRGOSource_Enable : stm32f10x_tim.h
  • TIM_TRGOSource_OC1 : stm32f10x_tim.h
  • TIM_TRGOSource_OC1Ref : stm32f10x_tim.h
  • TIM_TRGOSource_OC2Ref : stm32f10x_tim.h
  • TIM_TRGOSource_OC3Ref : stm32f10x_tim.h
  • TIM_TRGOSource_OC4Ref : stm32f10x_tim.h
  • TIM_TRGOSource_Reset : stm32f10x_tim.h
  • TIM_TRGOSource_Update : stm32f10x_tim.h
  • TIM_TS_ETRF : stm32f10x_tim.h
  • TIM_TS_ITR0 : stm32f10x_tim.h
  • TIM_TS_ITR1 : stm32f10x_tim.h
  • TIM_TS_ITR2 : stm32f10x_tim.h
  • TIM_TS_ITR3 : stm32f10x_tim.h
  • TIM_TS_TI1F_ED : stm32f10x_tim.h
  • TIM_TS_TI1FP1 : stm32f10x_tim.h
  • TIM_TS_TI2FP2 : stm32f10x_tim.h
  • TIM_UpdateSource_Global : stm32f10x_tim.h
  • TIM_UpdateSource_Regular : stm32f10x_tim.h
  • TIMEOUT_MAX : stm32100e_eval_ioe.c , stm3210c_eval_ioe.c
  • TMIDxR_TXRQ : stm32f10x_can.c
  • TOUCH_IO_ALL : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • TOUCH_XD : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • TOUCH_XU : stm3210c_eval_ioe.h , stm32100e_eval_ioe.h
  • TOUCH_YD : stm3210c_eval_ioe.h , stm32100e_eval_ioe.h
  • TOUCH_YU : stm3210c_eval_ioe.h , stm32100e_eval_ioe.h
  • TPAL_BitNumber : stm32f10x_bkp.c
  • TPE_BitNumber : stm32f10x_bkp.c
  • TPIE_BitNumber : stm32f10x_bkp.c
  • TS_CONVERSION_DELAY : stm3210c_eval_ioe.c
  • TSOM_BitNumber : stm32f10x_cec.c
  • TxBufferSize : STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/main.c , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Polling/main.c
  • TxBufferSize1 : STM32F10x_StdPeriph_Examples/USART/Synchronous/main.c , STM32F10x_StdPeriph_Examples/USART/HalfDuplex/main.c , STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c , STM32F10x_StdPeriph_Examples/USART/DMA_Polling/main.c , STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/main.c
  • TxBufferSize2 : STM32F10x_StdPeriph_Examples/USART/DMA_Polling/main.c , STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/main.c , STM32F10x_StdPeriph_Examples/USART/Synchronous/main.c , STM32F10x_StdPeriph_Examples/USART/HalfDuplex/main.c , STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c
  • Type_Edge : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • Type_Level : stm3210c_eval_ioe.h , stm32100e_eval_ioe.h


STM32F10x Standard Peripherals Firmware Library: Globals

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- u -

  • UART4 : stm32f10x.h
  • UART4_BASE : stm32f10x.h
  • UART5 : stm32f10x.h
  • UART5_BASE : stm32f10x.h
  • UP_BUTTON_EXTI_IRQn : stm3210e_eval.h , stm32l152_eval.h , stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h
  • UP_BUTTON_EXTI_LINE : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210e_eval.h , stm32l152_eval.h
  • UP_BUTTON_EXTI_PIN_SOURCE : stm32100e_eval.h , stm3210b_eval.h , stm3210e_eval.h , stm32l152_eval.h , stm32100b_eval.h
  • UP_BUTTON_EXTI_PORT_SOURCE : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210e_eval.h , stm32l152_eval.h
  • UP_BUTTON_GPIO_CLK : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210e_eval.h , stm32l152_eval.h
  • UP_BUTTON_GPIO_PORT : stm3210b_eval.h , stm3210e_eval.h , stm32l152_eval.h , stm32100b_eval.h , stm32100e_eval.h
  • UP_BUTTON_PIN : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210e_eval.h , stm32l152_eval.h
  • USART1 : stm32f10x.h
  • USART1_BASE : stm32f10x.h
  • USART2 : stm32f10x.h
  • USART2_BASE : stm32f10x.h
  • USART3 : stm32f10x.h
  • USART3_BASE : stm32f10x.h
  • USART_BRR_DIV_Fraction : stm32f10x.h
  • USART_BRR_DIV_Mantissa : stm32f10x.h
  • USART_Clock_Disable : stm32f10x_usart.h
  • USART_Clock_Enable : stm32f10x_usart.h
  • USART_CPHA_1Edge : stm32f10x_usart.h
  • USART_CPHA_2Edge : stm32f10x_usart.h
  • USART_CPOL_High : stm32f10x_usart.h
  • USART_CPOL_Low : stm32f10x_usart.h
  • USART_CR1_IDLEIE : stm32f10x.h
  • USART_CR1_M : stm32f10x.h
  • USART_CR1_OVER8 : stm32f10x.h
  • USART_CR1_PCE : stm32f10x.h
  • USART_CR1_PEIE : stm32f10x.h
  • USART_CR1_PS : stm32f10x.h
  • USART_CR1_RE : stm32f10x.h
  • USART_CR1_RWU : stm32f10x.h
  • USART_CR1_RXNEIE : stm32f10x.h
  • USART_CR1_SBK : stm32f10x.h
  • USART_CR1_TCIE : stm32f10x.h
  • USART_CR1_TE : stm32f10x.h
  • USART_CR1_TXEIE : stm32f10x.h
  • USART_CR1_UE : stm32f10x.h
  • USART_CR1_WAKE : stm32f10x.h
  • USART_CR2_ADD : stm32f10x.h
  • USART_CR2_CLKEN : stm32f10x.h
  • USART_CR2_CPHA : stm32f10x.h
  • USART_CR2_CPOL : stm32f10x.h
  • USART_CR2_LBCL : stm32f10x.h
  • USART_CR2_LBDIE : stm32f10x.h
  • USART_CR2_LBDL : stm32f10x.h
  • USART_CR2_LINEN : stm32f10x.h
  • USART_CR2_STOP : stm32f10x.h
  • USART_CR2_STOP_0 : stm32f10x.h
  • USART_CR2_STOP_1 : stm32f10x.h
  • USART_CR3_CTSE : stm32f10x.h
  • USART_CR3_CTSIE : stm32f10x.h
  • USART_CR3_DMAR : stm32f10x.h
  • USART_CR3_DMAT : stm32f10x.h
  • USART_CR3_EIE : stm32f10x.h
  • USART_CR3_HDSEL : stm32f10x.h
  • USART_CR3_IREN : stm32f10x.h
  • USART_CR3_IRLP : stm32f10x.h
  • USART_CR3_NACK : stm32f10x.h
  • USART_CR3_ONEBIT : stm32f10x.h
  • USART_CR3_RTSE : stm32f10x.h
  • USART_CR3_SCEN : stm32f10x.h
  • USART_DMAReq_Rx : stm32f10x_usart.h
  • USART_DMAReq_Tx : stm32f10x_usart.h
  • USART_DR_DR : stm32f10x.h
  • USART_FLAG_CTS : stm32f10x_usart.h
  • USART_FLAG_FE : stm32f10x_usart.h
  • USART_FLAG_IDLE : stm32f10x_usart.h
  • USART_FLAG_LBD : stm32f10x_usart.h
  • USART_FLAG_NE : stm32f10x_usart.h
  • USART_FLAG_ORE : stm32f10x_usart.h
  • USART_FLAG_PE : stm32f10x_usart.h
  • USART_FLAG_RXNE : stm32f10x_usart.h
  • USART_FLAG_TC : stm32f10x_usart.h
  • USART_FLAG_TXE : stm32f10x_usart.h
  • USART_GTPR_GT : stm32f10x.h
  • USART_GTPR_PSC : stm32f10x.h
  • USART_GTPR_PSC_0 : stm32f10x.h
  • USART_GTPR_PSC_1 : stm32f10x.h
  • USART_GTPR_PSC_2 : stm32f10x.h
  • USART_GTPR_PSC_3 : stm32f10x.h
  • USART_GTPR_PSC_4 : stm32f10x.h
  • USART_GTPR_PSC_5 : stm32f10x.h
  • USART_GTPR_PSC_6 : stm32f10x.h
  • USART_GTPR_PSC_7 : stm32f10x.h
  • USART_HardwareFlowControl_CTS : stm32f10x_usart.h
  • USART_HardwareFlowControl_None : stm32f10x_usart.h
  • USART_HardwareFlowControl_RTS : stm32f10x_usart.h
  • USART_HardwareFlowControl_RTS_CTS : stm32f10x_usart.h
  • USART_IrDAMode_LowPower : stm32f10x_usart.h
  • USART_IrDAMode_Normal : stm32f10x_usart.h
  • USART_IT_CTS : stm32f10x_usart.h
  • USART_IT_ERR : stm32f10x_usart.h
  • USART_IT_FE : stm32f10x_usart.h
  • USART_IT_IDLE : stm32f10x_usart.h
  • USART_IT_LBD : stm32f10x_usart.h
  • USART_IT_NE : stm32f10x_usart.h
  • USART_IT_ORE : stm32f10x_usart.h
  • USART_IT_PE : stm32f10x_usart.h
  • USART_IT_RXNE : stm32f10x_usart.h
  • USART_IT_TC : stm32f10x_usart.h
  • USART_IT_TXE : stm32f10x_usart.h
  • USART_LastBit_Disable : stm32f10x_usart.h
  • USART_LastBit_Enable : stm32f10x_usart.h
  • USART_LINBreakDetectLength_10b : stm32f10x_usart.h
  • USART_LINBreakDetectLength_11b : stm32f10x_usart.h
  • USART_Mode_Rx : stm32f10x_usart.h
  • USART_Mode_Tx : stm32f10x_usart.h
  • USART_Parity_Even : stm32f10x_usart.h
  • USART_Parity_No : stm32f10x_usart.h
  • USART_Parity_Odd : stm32f10x_usart.h
  • USART_SR_CTS : stm32f10x.h
  • USART_SR_FE : stm32f10x.h
  • USART_SR_IDLE : stm32f10x.h
  • USART_SR_LBD : stm32f10x.h
  • USART_SR_NE : stm32f10x.h
  • USART_SR_ORE : stm32f10x.h
  • USART_SR_PE : stm32f10x.h
  • USART_SR_RXNE : stm32f10x.h
  • USART_SR_TC : stm32f10x.h
  • USART_SR_TXE : stm32f10x.h
  • USART_StopBits_0_5 : stm32f10x_usart.h
  • USART_StopBits_1 : stm32f10x_usart.h
  • USART_StopBits_1_5 : stm32f10x_usart.h
  • USART_StopBits_2 : stm32f10x_usart.h
  • USART_WakeUp_AddressMark : stm32f10x_usart.h
  • USART_WakeUp_IdleLine : stm32f10x_usart.h
  • USART_WordLength_8b : stm32f10x_usart.h
  • USART_WordLength_9b : stm32f10x_usart.h
  • USARTx_IRQHandler : STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.c
  • USARTx_IRQn : STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/main.c
  • USARTy : USART/Interrupt/platform_config.h
  • USARTy_CLK : USART/Interrupt/platform_config.h
  • USARTy_DMA1_Channel : STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/main.c
  • USARTy_DMA1_IRQn : STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/main.c
  • USARTy_DR_Address : STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/main.c
  • USARTy_GPIO : USART/Interrupt/platform_config.h
  • USARTy_GPIO_CLK : USART/Interrupt/platform_config.h
  • USARTy_IRQHandler : USART/Interrupt/platform_config.h
  • USARTy_IRQn : USART/Interrupt/platform_config.h
  • USARTy_RxPin : USART/Interrupt/platform_config.h
  • USARTy_TxPin : USART/Interrupt/platform_config.h
  • USARTz : USART/Interrupt/platform_config.h
  • USARTz_CLK : USART/Interrupt/platform_config.h
  • USARTz_GPIO : USART/Interrupt/platform_config.h
  • USARTz_GPIO_CLK : USART/Interrupt/platform_config.h
  • USARTz_IRQHandler : USART/Interrupt/platform_config.h
  • USARTz_IRQn : USART/Interrupt/platform_config.h
  • USARTz_RxPin : USART/Interrupt/platform_config.h
  • USARTz_TxPin : USART/Interrupt/platform_config.h
  • USB_ADDR0_RX_ADDR0_RX : stm32f10x.h
  • USB_ADDR0_TX_ADDR0_TX : stm32f10x.h
  • USB_ADDR1_RX_ADDR1_RX : stm32f10x.h
  • USB_ADDR1_TX_ADDR1_TX : stm32f10x.h
  • USB_ADDR2_RX_ADDR2_RX : stm32f10x.h
  • USB_ADDR2_TX_ADDR2_TX : stm32f10x.h
  • USB_ADDR3_RX_ADDR3_RX : stm32f10x.h
  • USB_ADDR3_TX_ADDR3_TX : stm32f10x.h
  • USB_ADDR4_RX_ADDR4_RX : stm32f10x.h
  • USB_ADDR4_TX_ADDR4_TX : stm32f10x.h
  • USB_ADDR5_RX_ADDR5_RX : stm32f10x.h
  • USB_ADDR5_TX_ADDR5_TX : stm32f10x.h
  • USB_ADDR6_RX_ADDR6_RX : stm32f10x.h
  • USB_ADDR6_TX_ADDR6_TX : stm32f10x.h
  • USB_ADDR7_RX_ADDR7_RX : stm32f10x.h
  • USB_ADDR7_TX_ADDR7_TX : stm32f10x.h
  • USB_BTABLE_BTABLE : stm32f10x.h
  • USB_CNTR_CTRM : stm32f10x.h
  • USB_CNTR_ERRM : stm32f10x.h
  • USB_CNTR_ESOFM : stm32f10x.h
  • USB_CNTR_FRES : stm32f10x.h
  • USB_CNTR_FSUSP : stm32f10x.h
  • USB_CNTR_LP_MODE : stm32f10x.h
  • USB_CNTR_PDWN : stm32f10x.h
  • USB_CNTR_PMAOVRM : stm32f10x.h
  • USB_CNTR_RESETM : stm32f10x.h
  • USB_CNTR_RESUME : stm32f10x.h
  • USB_CNTR_SOFM : stm32f10x.h
  • USB_CNTR_SUSPM : stm32f10x.h
  • USB_CNTR_WKUPM : stm32f10x.h
  • USB_COUNT0_RX_0_BLSIZE_0 : stm32f10x.h
  • USB_COUNT0_RX_0_COUNT0_RX_0 : stm32f10x.h
  • USB_COUNT0_RX_0_NUM_BLOCK_0 : stm32f10x.h
  • USB_COUNT0_RX_0_NUM_BLOCK_0_0 : stm32f10x.h
  • USB_COUNT0_RX_0_NUM_BLOCK_0_1 : stm32f10x.h
  • USB_COUNT0_RX_0_NUM_BLOCK_0_2 : stm32f10x.h
  • USB_COUNT0_RX_0_NUM_BLOCK_0_3 : stm32f10x.h
  • USB_COUNT0_RX_0_NUM_BLOCK_0_4 : stm32f10x.h
  • USB_COUNT0_RX_1_BLSIZE_1 : stm32f10x.h
  • USB_COUNT0_RX_1_COUNT0_RX_1 : stm32f10x.h
  • USB_COUNT0_RX_1_NUM_BLOCK_1 : stm32f10x.h
  • USB_COUNT0_RX_1_NUM_BLOCK_1_0 : stm32f10x.h
  • USB_COUNT0_RX_1_NUM_BLOCK_1_1 : stm32f10x.h
  • USB_COUNT0_RX_1_NUM_BLOCK_1_2 : stm32f10x.h
  • USB_COUNT0_RX_1_NUM_BLOCK_1_3 : stm32f10x.h
  • USB_COUNT0_RX_1_NUM_BLOCK_1_4 : stm32f10x.h
  • USB_COUNT0_RX_BLSIZE : stm32f10x.h
  • USB_COUNT0_RX_COUNT0_RX : stm32f10x.h
  • USB_COUNT0_RX_NUM_BLOCK : stm32f10x.h
  • USB_COUNT0_RX_NUM_BLOCK_0 : stm32f10x.h
  • USB_COUNT0_RX_NUM_BLOCK_1 : stm32f10x.h
  • USB_COUNT0_RX_NUM_BLOCK_2 : stm32f10x.h
  • USB_COUNT0_RX_NUM_BLOCK_3 : stm32f10x.h
  • USB_COUNT0_RX_NUM_BLOCK_4 : stm32f10x.h
  • USB_COUNT0_TX_0_COUNT0_TX_0 : stm32f10x.h
  • USB_COUNT0_TX_1_COUNT0_TX_1 : stm32f10x.h
  • USB_COUNT0_TX_COUNT0_TX : stm32f10x.h
  • USB_COUNT1_RX_0_BLSIZE_0 : stm32f10x.h
  • USB_COUNT1_RX_0_COUNT1_RX_0 : stm32f10x.h
  • USB_COUNT1_RX_0_NUM_BLOCK_0 : stm32f10x.h
  • USB_COUNT1_RX_0_NUM_BLOCK_0_0 : stm32f10x.h
  • USB_COUNT1_RX_0_NUM_BLOCK_0_1 : stm32f10x.h
  • USB_COUNT1_RX_0_NUM_BLOCK_0_2 : stm32f10x.h
  • USB_COUNT1_RX_0_NUM_BLOCK_0_3 : stm32f10x.h
  • USB_COUNT1_RX_0_NUM_BLOCK_0_4 : stm32f10x.h
  • USB_COUNT1_RX_1_BLSIZE_1 : stm32f10x.h
  • USB_COUNT1_RX_1_COUNT1_RX_1 : stm32f10x.h
  • USB_COUNT1_RX_1_NUM_BLOCK_1 : stm32f10x.h
  • USB_COUNT1_RX_1_NUM_BLOCK_1_0 : stm32f10x.h
  • USB_COUNT1_RX_1_NUM_BLOCK_1_1 : stm32f10x.h
  • USB_COUNT1_RX_1_NUM_BLOCK_1_2 : stm32f10x.h
  • USB_COUNT1_RX_1_NUM_BLOCK_1_3 : stm32f10x.h
  • USB_COUNT1_RX_1_NUM_BLOCK_1_4 : stm32f10x.h
  • USB_COUNT1_RX_BLSIZE : stm32f10x.h
  • USB_COUNT1_RX_COUNT1_RX : stm32f10x.h
  • USB_COUNT1_RX_NUM_BLOCK : stm32f10x.h
  • USB_COUNT1_RX_NUM_BLOCK_0 : stm32f10x.h
  • USB_COUNT1_RX_NUM_BLOCK_1 : stm32f10x.h
  • USB_COUNT1_RX_NUM_BLOCK_2 : stm32f10x.h
  • USB_COUNT1_RX_NUM_BLOCK_3 : stm32f10x.h
  • USB_COUNT1_RX_NUM_BLOCK_4 : stm32f10x.h
  • USB_COUNT1_TX_0_COUNT1_TX_0 : stm32f10x.h
  • USB_COUNT1_TX_1_COUNT1_TX_1 : stm32f10x.h
  • USB_COUNT1_TX_COUNT1_TX : stm32f10x.h
  • USB_COUNT2_RX_0_BLSIZE_0 : stm32f10x.h
  • USB_COUNT2_RX_0_COUNT2_RX_0 : stm32f10x.h
  • USB_COUNT2_RX_0_NUM_BLOCK_0 : stm32f10x.h
  • USB_COUNT2_RX_0_NUM_BLOCK_0_0 : stm32f10x.h
  • USB_COUNT2_RX_0_NUM_BLOCK_0_1 : stm32f10x.h
  • USB_COUNT2_RX_0_NUM_BLOCK_0_2 : stm32f10x.h
  • USB_COUNT2_RX_0_NUM_BLOCK_0_3 : stm32f10x.h
  • USB_COUNT2_RX_0_NUM_BLOCK_0_4 : stm32f10x.h
  • USB_COUNT2_RX_1_BLSIZE_1 : stm32f10x.h
  • USB_COUNT2_RX_1_COUNT2_RX_1 : stm32f10x.h
  • USB_COUNT2_RX_1_NUM_BLOCK_1 : stm32f10x.h
  • USB_COUNT2_RX_1_NUM_BLOCK_1_0 : stm32f10x.h
  • USB_COUNT2_RX_1_NUM_BLOCK_1_1 : stm32f10x.h
  • USB_COUNT2_RX_1_NUM_BLOCK_1_2 : stm32f10x.h
  • USB_COUNT2_RX_1_NUM_BLOCK_1_3 : stm32f10x.h
  • USB_COUNT2_RX_1_NUM_BLOCK_1_4 : stm32f10x.h
  • USB_COUNT2_RX_BLSIZE : stm32f10x.h
  • USB_COUNT2_RX_COUNT2_RX : stm32f10x.h
  • USB_COUNT2_RX_NUM_BLOCK : stm32f10x.h
  • USB_COUNT2_RX_NUM_BLOCK_0 : stm32f10x.h
  • USB_COUNT2_RX_NUM_BLOCK_1 : stm32f10x.h
  • USB_COUNT2_RX_NUM_BLOCK_2 : stm32f10x.h
  • USB_COUNT2_RX_NUM_BLOCK_3 : stm32f10x.h
  • USB_COUNT2_RX_NUM_BLOCK_4 : stm32f10x.h
  • USB_COUNT2_TX_0_COUNT2_TX_0 : stm32f10x.h
  • USB_COUNT2_TX_1_COUNT2_TX_1 : stm32f10x.h
  • USB_COUNT2_TX_COUNT2_TX : stm32f10x.h
  • USB_COUNT3_RX_0_BLSIZE_0 : stm32f10x.h
  • USB_COUNT3_RX_0_COUNT3_RX_0 : stm32f10x.h
  • USB_COUNT3_RX_0_NUM_BLOCK_0 : stm32f10x.h
  • USB_COUNT3_RX_0_NUM_BLOCK_0_0 : stm32f10x.h
  • USB_COUNT3_RX_0_NUM_BLOCK_0_1 : stm32f10x.h
  • USB_COUNT3_RX_0_NUM_BLOCK_0_2 : stm32f10x.h
  • USB_COUNT3_RX_0_NUM_BLOCK_0_3 : stm32f10x.h
  • USB_COUNT3_RX_0_NUM_BLOCK_0_4 : stm32f10x.h
  • USB_COUNT3_RX_1_BLSIZE_1 : stm32f10x.h
  • USB_COUNT3_RX_1_COUNT3_RX_1 : stm32f10x.h
  • USB_COUNT3_RX_1_NUM_BLOCK_1 : stm32f10x.h
  • USB_COUNT3_RX_1_NUM_BLOCK_1_0 : stm32f10x.h
  • USB_COUNT3_RX_1_NUM_BLOCK_1_1 : stm32f10x.h
  • USB_COUNT3_RX_1_NUM_BLOCK_1_2 : stm32f10x.h
  • USB_COUNT3_RX_1_NUM_BLOCK_1_3 : stm32f10x.h
  • USB_COUNT3_RX_1_NUM_BLOCK_1_4 : stm32f10x.h
  • USB_COUNT3_RX_BLSIZE : stm32f10x.h
  • USB_COUNT3_RX_COUNT3_RX : stm32f10x.h
  • USB_COUNT3_RX_NUM_BLOCK : stm32f10x.h
  • USB_COUNT3_RX_NUM_BLOCK_0 : stm32f10x.h
  • USB_COUNT3_RX_NUM_BLOCK_1 : stm32f10x.h
  • USB_COUNT3_RX_NUM_BLOCK_2 : stm32f10x.h
  • USB_COUNT3_RX_NUM_BLOCK_3 : stm32f10x.h
  • USB_COUNT3_RX_NUM_BLOCK_4 : stm32f10x.h
  • USB_COUNT3_TX_0_COUNT3_TX_0 : stm32f10x.h
  • USB_COUNT3_TX_1_COUNT3_TX_1 : stm32f10x.h
  • USB_COUNT3_TX_COUNT3_TX : stm32f10x.h
  • USB_COUNT4_RX_0_BLSIZE_0 : stm32f10x.h
  • USB_COUNT4_RX_0_COUNT4_RX_0 : stm32f10x.h
  • USB_COUNT4_RX_0_NUM_BLOCK_0 : stm32f10x.h
  • USB_COUNT4_RX_0_NUM_BLOCK_0_0 : stm32f10x.h
  • USB_COUNT4_RX_0_NUM_BLOCK_0_1 : stm32f10x.h
  • USB_COUNT4_RX_0_NUM_BLOCK_0_2 : stm32f10x.h
  • USB_COUNT4_RX_0_NUM_BLOCK_0_3 : stm32f10x.h
  • USB_COUNT4_RX_0_NUM_BLOCK_0_4 : stm32f10x.h
  • USB_COUNT4_RX_1_BLSIZE_1 : stm32f10x.h
  • USB_COUNT4_RX_1_COUNT4_RX_1 : stm32f10x.h
  • USB_COUNT4_RX_1_NUM_BLOCK_1 : stm32f10x.h
  • USB_COUNT4_RX_1_NUM_BLOCK_1_0 : stm32f10x.h
  • USB_COUNT4_RX_1_NUM_BLOCK_1_1 : stm32f10x.h
  • USB_COUNT4_RX_1_NUM_BLOCK_1_2 : stm32f10x.h
  • USB_COUNT4_RX_1_NUM_BLOCK_1_3 : stm32f10x.h
  • USB_COUNT4_RX_1_NUM_BLOCK_1_4 : stm32f10x.h
  • USB_COUNT4_RX_BLSIZE : stm32f10x.h
  • USB_COUNT4_RX_COUNT4_RX : stm32f10x.h
  • USB_COUNT4_RX_NUM_BLOCK : stm32f10x.h
  • USB_COUNT4_RX_NUM_BLOCK_0 : stm32f10x.h
  • USB_COUNT4_RX_NUM_BLOCK_1 : stm32f10x.h
  • USB_COUNT4_RX_NUM_BLOCK_2 : stm32f10x.h
  • USB_COUNT4_RX_NUM_BLOCK_3 : stm32f10x.h
  • USB_COUNT4_RX_NUM_BLOCK_4 : stm32f10x.h
  • USB_COUNT4_TX_0_COUNT4_TX_0 : stm32f10x.h
  • USB_COUNT4_TX_1_COUNT4_TX_1 : stm32f10x.h
  • USB_COUNT4_TX_COUNT4_TX : stm32f10x.h
  • USB_COUNT5_RX_0_BLSIZE_0 : stm32f10x.h
  • USB_COUNT5_RX_0_COUNT5_RX_0 : stm32f10x.h
  • USB_COUNT5_RX_0_NUM_BLOCK_0 : stm32f10x.h
  • USB_COUNT5_RX_0_NUM_BLOCK_0_0 : stm32f10x.h
  • USB_COUNT5_RX_0_NUM_BLOCK_0_1 : stm32f10x.h
  • USB_COUNT5_RX_0_NUM_BLOCK_0_2 : stm32f10x.h
  • USB_COUNT5_RX_0_NUM_BLOCK_0_3 : stm32f10x.h
  • USB_COUNT5_RX_0_NUM_BLOCK_0_4 : stm32f10x.h
  • USB_COUNT5_RX_1_BLSIZE_1 : stm32f10x.h
  • USB_COUNT5_RX_1_COUNT5_RX_1 : stm32f10x.h
  • USB_COUNT5_RX_1_NUM_BLOCK_1 : stm32f10x.h
  • USB_COUNT5_RX_1_NUM_BLOCK_1_0 : stm32f10x.h
  • USB_COUNT5_RX_1_NUM_BLOCK_1_1 : stm32f10x.h
  • USB_COUNT5_RX_1_NUM_BLOCK_1_2 : stm32f10x.h
  • USB_COUNT5_RX_1_NUM_BLOCK_1_3 : stm32f10x.h
  • USB_COUNT5_RX_1_NUM_BLOCK_1_4 : stm32f10x.h
  • USB_COUNT5_RX_BLSIZE : stm32f10x.h
  • USB_COUNT5_RX_COUNT5_RX : stm32f10x.h
  • USB_COUNT5_RX_NUM_BLOCK : stm32f10x.h
  • USB_COUNT5_RX_NUM_BLOCK_0 : stm32f10x.h
  • USB_COUNT5_RX_NUM_BLOCK_1 : stm32f10x.h
  • USB_COUNT5_RX_NUM_BLOCK_2 : stm32f10x.h
  • USB_COUNT5_RX_NUM_BLOCK_3 : stm32f10x.h
  • USB_COUNT5_RX_NUM_BLOCK_4 : stm32f10x.h
  • USB_COUNT5_TX_0_COUNT5_TX_0 : stm32f10x.h
  • USB_COUNT5_TX_1_COUNT5_TX_1 : stm32f10x.h
  • USB_COUNT5_TX_COUNT5_TX : stm32f10x.h
  • USB_COUNT6_RX_0_BLSIZE_0 : stm32f10x.h
  • USB_COUNT6_RX_0_COUNT6_RX_0 : stm32f10x.h
  • USB_COUNT6_RX_0_NUM_BLOCK_0 : stm32f10x.h
  • USB_COUNT6_RX_0_NUM_BLOCK_0_0 : stm32f10x.h
  • USB_COUNT6_RX_0_NUM_BLOCK_0_1 : stm32f10x.h
  • USB_COUNT6_RX_0_NUM_BLOCK_0_2 : stm32f10x.h
  • USB_COUNT6_RX_0_NUM_BLOCK_0_3 : stm32f10x.h
  • USB_COUNT6_RX_0_NUM_BLOCK_0_4 : stm32f10x.h
  • USB_COUNT6_RX_1_BLSIZE_1 : stm32f10x.h
  • USB_COUNT6_RX_1_COUNT6_RX_1 : stm32f10x.h
  • USB_COUNT6_RX_1_NUM_BLOCK_1 : stm32f10x.h
  • USB_COUNT6_RX_1_NUM_BLOCK_1_0 : stm32f10x.h
  • USB_COUNT6_RX_1_NUM_BLOCK_1_1 : stm32f10x.h
  • USB_COUNT6_RX_1_NUM_BLOCK_1_2 : stm32f10x.h
  • USB_COUNT6_RX_1_NUM_BLOCK_1_3 : stm32f10x.h
  • USB_COUNT6_RX_1_NUM_BLOCK_1_4 : stm32f10x.h
  • USB_COUNT6_RX_BLSIZE : stm32f10x.h
  • USB_COUNT6_RX_COUNT6_RX : stm32f10x.h
  • USB_COUNT6_RX_NUM_BLOCK : stm32f10x.h
  • USB_COUNT6_RX_NUM_BLOCK_0 : stm32f10x.h
  • USB_COUNT6_RX_NUM_BLOCK_1 : stm32f10x.h
  • USB_COUNT6_RX_NUM_BLOCK_2 : stm32f10x.h
  • USB_COUNT6_RX_NUM_BLOCK_3 : stm32f10x.h
  • USB_COUNT6_RX_NUM_BLOCK_4 : stm32f10x.h
  • USB_COUNT6_TX_0_COUNT6_TX_0 : stm32f10x.h
  • USB_COUNT6_TX_1_COUNT6_TX_1 : stm32f10x.h
  • USB_COUNT6_TX_COUNT6_TX : stm32f10x.h
  • USB_COUNT7_RX_0_BLSIZE_0 : stm32f10x.h
  • USB_COUNT7_RX_0_COUNT7_RX_0 : stm32f10x.h
  • USB_COUNT7_RX_0_NUM_BLOCK_0 : stm32f10x.h
  • USB_COUNT7_RX_0_NUM_BLOCK_0_0 : stm32f10x.h
  • USB_COUNT7_RX_0_NUM_BLOCK_0_1 : stm32f10x.h
  • USB_COUNT7_RX_0_NUM_BLOCK_0_2 : stm32f10x.h
  • USB_COUNT7_RX_0_NUM_BLOCK_0_3 : stm32f10x.h
  • USB_COUNT7_RX_0_NUM_BLOCK_0_4 : stm32f10x.h
  • USB_COUNT7_RX_1_BLSIZE_1 : stm32f10x.h
  • USB_COUNT7_RX_1_COUNT7_RX_1 : stm32f10x.h
  • USB_COUNT7_RX_1_NUM_BLOCK_1 : stm32f10x.h
  • USB_COUNT7_RX_1_NUM_BLOCK_1_0 : stm32f10x.h
  • USB_COUNT7_RX_1_NUM_BLOCK_1_1 : stm32f10x.h
  • USB_COUNT7_RX_1_NUM_BLOCK_1_2 : stm32f10x.h
  • USB_COUNT7_RX_1_NUM_BLOCK_1_3 : stm32f10x.h
  • USB_COUNT7_RX_1_NUM_BLOCK_1_4 : stm32f10x.h
  • USB_COUNT7_RX_BLSIZE : stm32f10x.h
  • USB_COUNT7_RX_COUNT7_RX : stm32f10x.h
  • USB_COUNT7_RX_NUM_BLOCK : stm32f10x.h
  • USB_COUNT7_RX_NUM_BLOCK_0 : stm32f10x.h
  • USB_COUNT7_RX_NUM_BLOCK_1 : stm32f10x.h
  • USB_COUNT7_RX_NUM_BLOCK_2 : stm32f10x.h
  • USB_COUNT7_RX_NUM_BLOCK_3 : stm32f10x.h
  • USB_COUNT7_RX_NUM_BLOCK_4 : stm32f10x.h
  • USB_COUNT7_TX_0_COUNT7_TX_0 : stm32f10x.h
  • USB_COUNT7_TX_1_COUNT7_TX_1 : stm32f10x.h
  • USB_COUNT7_TX_COUNT7_TX : stm32f10x.h
  • USB_DADDR_ADD : stm32f10x.h
  • USB_DADDR_ADD0 : stm32f10x.h
  • USB_DADDR_ADD1 : stm32f10x.h
  • USB_DADDR_ADD2 : stm32f10x.h
  • USB_DADDR_ADD3 : stm32f10x.h
  • USB_DADDR_ADD4 : stm32f10x.h
  • USB_DADDR_ADD5 : stm32f10x.h
  • USB_DADDR_ADD6 : stm32f10x.h
  • USB_DADDR_EF : stm32f10x.h
  • USB_EP0R_CTR_RX : stm32f10x.h
  • USB_EP0R_CTR_TX : stm32f10x.h
  • USB_EP0R_DTOG_RX : stm32f10x.h
  • USB_EP0R_DTOG_TX : stm32f10x.h
  • USB_EP0R_EA : stm32f10x.h
  • USB_EP0R_EP_KIND : stm32f10x.h
  • USB_EP0R_EP_TYPE : stm32f10x.h
  • USB_EP0R_EP_TYPE_0 : stm32f10x.h
  • USB_EP0R_EP_TYPE_1 : stm32f10x.h
  • USB_EP0R_SETUP : stm32f10x.h
  • USB_EP0R_STAT_RX : stm32f10x.h
  • USB_EP0R_STAT_RX_0 : stm32f10x.h
  • USB_EP0R_STAT_RX_1 : stm32f10x.h
  • USB_EP0R_STAT_TX : stm32f10x.h
  • USB_EP0R_STAT_TX_0 : stm32f10x.h
  • USB_EP0R_STAT_TX_1 : stm32f10x.h
  • USB_EP1R_CTR_RX : stm32f10x.h
  • USB_EP1R_CTR_TX : stm32f10x.h
  • USB_EP1R_DTOG_RX : stm32f10x.h
  • USB_EP1R_DTOG_TX : stm32f10x.h
  • USB_EP1R_EA : stm32f10x.h
  • USB_EP1R_EP_KIND : stm32f10x.h
  • USB_EP1R_EP_TYPE : stm32f10x.h
  • USB_EP1R_EP_TYPE_0 : stm32f10x.h
  • USB_EP1R_EP_TYPE_1 : stm32f10x.h
  • USB_EP1R_SETUP : stm32f10x.h
  • USB_EP1R_STAT_RX : stm32f10x.h
  • USB_EP1R_STAT_RX_0 : stm32f10x.h
  • USB_EP1R_STAT_RX_1 : stm32f10x.h
  • USB_EP1R_STAT_TX : stm32f10x.h
  • USB_EP1R_STAT_TX_0 : stm32f10x.h
  • USB_EP1R_STAT_TX_1 : stm32f10x.h
  • USB_EP2R_CTR_RX : stm32f10x.h
  • USB_EP2R_CTR_TX : stm32f10x.h
  • USB_EP2R_DTOG_RX : stm32f10x.h
  • USB_EP2R_DTOG_TX : stm32f10x.h
  • USB_EP2R_EA : stm32f10x.h
  • USB_EP2R_EP_KIND : stm32f10x.h
  • USB_EP2R_EP_TYPE : stm32f10x.h
  • USB_EP2R_EP_TYPE_0 : stm32f10x.h
  • USB_EP2R_EP_TYPE_1 : stm32f10x.h
  • USB_EP2R_SETUP : stm32f10x.h
  • USB_EP2R_STAT_RX : stm32f10x.h
  • USB_EP2R_STAT_RX_0 : stm32f10x.h
  • USB_EP2R_STAT_RX_1 : stm32f10x.h
  • USB_EP2R_STAT_TX : stm32f10x.h
  • USB_EP2R_STAT_TX_0 : stm32f10x.h
  • USB_EP2R_STAT_TX_1 : stm32f10x.h
  • USB_EP3R_CTR_RX : stm32f10x.h
  • USB_EP3R_CTR_TX : stm32f10x.h
  • USB_EP3R_DTOG_RX : stm32f10x.h
  • USB_EP3R_DTOG_TX : stm32f10x.h
  • USB_EP3R_EA : stm32f10x.h
  • USB_EP3R_EP_KIND : stm32f10x.h
  • USB_EP3R_EP_TYPE : stm32f10x.h
  • USB_EP3R_EP_TYPE_0 : stm32f10x.h
  • USB_EP3R_EP_TYPE_1 : stm32f10x.h
  • USB_EP3R_SETUP : stm32f10x.h
  • USB_EP3R_STAT_RX : stm32f10x.h
  • USB_EP3R_STAT_RX_0 : stm32f10x.h
  • USB_EP3R_STAT_RX_1 : stm32f10x.h
  • USB_EP3R_STAT_TX : stm32f10x.h
  • USB_EP3R_STAT_TX_0 : stm32f10x.h
  • USB_EP3R_STAT_TX_1 : stm32f10x.h
  • USB_EP4R_CTR_RX : stm32f10x.h
  • USB_EP4R_CTR_TX : stm32f10x.h
  • USB_EP4R_DTOG_RX : stm32f10x.h
  • USB_EP4R_DTOG_TX : stm32f10x.h
  • USB_EP4R_EA : stm32f10x.h
  • USB_EP4R_EP_KIND : stm32f10x.h
  • USB_EP4R_EP_TYPE : stm32f10x.h
  • USB_EP4R_EP_TYPE_0 : stm32f10x.h
  • USB_EP4R_EP_TYPE_1 : stm32f10x.h
  • USB_EP4R_SETUP : stm32f10x.h
  • USB_EP4R_STAT_RX : stm32f10x.h
  • USB_EP4R_STAT_RX_0 : stm32f10x.h
  • USB_EP4R_STAT_RX_1 : stm32f10x.h
  • USB_EP4R_STAT_TX : stm32f10x.h
  • USB_EP4R_STAT_TX_0 : stm32f10x.h
  • USB_EP4R_STAT_TX_1 : stm32f10x.h
  • USB_EP5R_CTR_RX : stm32f10x.h
  • USB_EP5R_CTR_TX : stm32f10x.h
  • USB_EP5R_DTOG_RX : stm32f10x.h
  • USB_EP5R_DTOG_TX : stm32f10x.h
  • USB_EP5R_EA : stm32f10x.h
  • USB_EP5R_EP_KIND : stm32f10x.h
  • USB_EP5R_EP_TYPE : stm32f10x.h
  • USB_EP5R_EP_TYPE_0 : stm32f10x.h
  • USB_EP5R_EP_TYPE_1 : stm32f10x.h
  • USB_EP5R_SETUP : stm32f10x.h
  • USB_EP5R_STAT_RX : stm32f10x.h
  • USB_EP5R_STAT_RX_0 : stm32f10x.h
  • USB_EP5R_STAT_RX_1 : stm32f10x.h
  • USB_EP5R_STAT_TX : stm32f10x.h
  • USB_EP5R_STAT_TX_0 : stm32f10x.h
  • USB_EP5R_STAT_TX_1 : stm32f10x.h
  • USB_EP6R_CTR_RX : stm32f10x.h
  • USB_EP6R_CTR_TX : stm32f10x.h
  • USB_EP6R_DTOG_RX : stm32f10x.h
  • USB_EP6R_DTOG_TX : stm32f10x.h
  • USB_EP6R_EA : stm32f10x.h
  • USB_EP6R_EP_KIND : stm32f10x.h
  • USB_EP6R_EP_TYPE : stm32f10x.h
  • USB_EP6R_EP_TYPE_0 : stm32f10x.h
  • USB_EP6R_EP_TYPE_1 : stm32f10x.h
  • USB_EP6R_SETUP : stm32f10x.h
  • USB_EP6R_STAT_RX : stm32f10x.h
  • USB_EP6R_STAT_RX_0 : stm32f10x.h
  • USB_EP6R_STAT_RX_1 : stm32f10x.h
  • USB_EP6R_STAT_TX : stm32f10x.h
  • USB_EP6R_STAT_TX_0 : stm32f10x.h
  • USB_EP6R_STAT_TX_1 : stm32f10x.h
  • USB_EP7R_CTR_RX : stm32f10x.h
  • USB_EP7R_CTR_TX : stm32f10x.h
  • USB_EP7R_DTOG_RX : stm32f10x.h
  • USB_EP7R_DTOG_TX : stm32f10x.h
  • USB_EP7R_EA : stm32f10x.h
  • USB_EP7R_EP_KIND : stm32f10x.h
  • USB_EP7R_EP_TYPE : stm32f10x.h
  • USB_EP7R_EP_TYPE_0 : stm32f10x.h
  • USB_EP7R_EP_TYPE_1 : stm32f10x.h
  • USB_EP7R_SETUP : stm32f10x.h
  • USB_EP7R_STAT_RX : stm32f10x.h
  • USB_EP7R_STAT_RX_0 : stm32f10x.h
  • USB_EP7R_STAT_RX_1 : stm32f10x.h
  • USB_EP7R_STAT_TX : stm32f10x.h
  • USB_EP7R_STAT_TX_0 : stm32f10x.h
  • USB_EP7R_STAT_TX_1 : stm32f10x.h
  • USB_FNR_FN : stm32f10x.h
  • USB_FNR_LCK : stm32f10x.h
  • USB_FNR_LSOF : stm32f10x.h
  • USB_FNR_RXDM : stm32f10x.h
  • USB_FNR_RXDP : stm32f10x.h
  • USB_ISTR_CTR : stm32f10x.h
  • USB_ISTR_DIR : stm32f10x.h
  • USB_ISTR_EP_ID : stm32f10x.h
  • USB_ISTR_ERR : stm32f10x.h
  • USB_ISTR_ESOF : stm32f10x.h
  • USB_ISTR_PMAOVR : stm32f10x.h
  • USB_ISTR_RESET : stm32f10x.h
  • USB_ISTR_SOF : stm32f10x.h
  • USB_ISTR_SUSP : stm32f10x.h
  • USB_ISTR_WKUP : stm32f10x.h
  • USBPRE_BitNumber : stm32f10x_rcc.c
  • USE_DEFAULT_CRITICAL_CALLBACK : stm32_eval_i2c_ee.h
  • USE_FULL_ASSERT : STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/stm32f10x_conf.h , STM32F10x_StdPeriph_Examples/I2C/EEPROM/stm32f10x_conf.h
  • USE_STM32100E_EVAL : USART/IrDA/Transmit/platform_config.h , USART/Interrupt/platform_config.h
  • USE_STM3210C_EVAL : USART/IrDA/Receive/platform_config.h , USART/DMA_Polling/platform_config.h , DMA/SPI_RAM/platform_config.h , USART/HalfDuplex/platform_config.h , USART/MultiProcessor/platform_config.h , USART/Smartcard/platform_config.h , USART/DMA_Interrupt/platform_config.h , SPI/DMA/platform_config.h , SPI/Simplex_Interrupt/platform_config.h , SPI/FullDuplex_SoftNSS/platform_config.h , CAN/Networking/platform_config.h , USART/Polling/platform_config.h
  • USE_STM3210E_EVAL : USART/Synchronous/platform_config.h , USART/HyperTerminal_HwFlowControl/platform_config.h


STM32F10x Standard Peripherals Firmware Library: Globals

  • File List
  • Globals
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  • Functions
  • Variables
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  • Enumerations
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- v -

  • Var_GetBit_BB : STM32F10x_StdPeriph_Examples/CortexM3/BitBand/main.c
  • Var_ResetBit_BB : STM32F10x_StdPeriph_Examples/CortexM3/BitBand/main.c
  • Var_SetBit_BB : STM32F10x_StdPeriph_Examples/CortexM3/BitBand/main.c
  • VBAT_DIV_PIN : stm3210c_eval_ioe.h
  • VECT_TAB_OFFSET : Project/STM32F10x_StdPeriph_Examples/USART/Synchronous/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/Smartcard/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/Printf/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/Polling/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/MultiProcessor/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/Interrupt/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/HalfDuplex/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/DMA_Polling/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/TimeBase/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Output/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Input/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/OnePulse/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/OCToggle/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/OCInactive/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/OCActive/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/InputCapture/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/DMABurst/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/DMA/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/6Steps/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/SysTick/TimeBase/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/SPI/DMA/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/SPI/CRC/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/SDIO/uSDCard/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/RTC/Calendar/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/PWR/STOP/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/PWR/STANDBY/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/PWR/PVD/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/I2S/Interrupt/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/I2C/IOExpander/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/I2C/EEPROM/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/GPIO/IOToggle/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/FSMC/OneNAND/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/FSMC/NOR/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/FSMC/NAND/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/FLASH/Program/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/DMA/FSMC/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/CortexM3/MPU/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/CortexM3/BitBand/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/CAN/Networking/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/CAN/LoopBack/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/CAN/DualCAN/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/BKP/Tamper/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/BKP/Backup_Data/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/system_stm32f10x.c , Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Template/system_stm32f10x.c
  • Vertical : stm32_eval.h


STM32F10x Standard Peripherals Firmware Library: Globals

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- w -

  • WAKEUP_BUTTON_EXTI_IRQn : stm32100b_eval.h , stm32100e_eval.h , stm3210c_eval.h , stm3210e_eval.h , stm3210b_eval.h
  • WAKEUP_BUTTON_EXTI_LINE : stm3210b_eval.h , stm3210c_eval.h , stm3210e_eval.h , stm32100b_eval.h , stm32100e_eval.h
  • WAKEUP_BUTTON_EXTI_PIN_SOURCE : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210c_eval.h , stm3210e_eval.h
  • WAKEUP_BUTTON_EXTI_PORT_SOURCE : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210c_eval.h , stm3210e_eval.h
  • WAKEUP_BUTTON_GPIO_CLK : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210c_eval.h , stm3210e_eval.h
  • WAKEUP_BUTTON_GPIO_PORT : stm32100b_eval.h , stm32100e_eval.h , stm3210b_eval.h , stm3210c_eval.h , stm3210e_eval.h
  • WAKEUP_BUTTON_PIN : stm32100e_eval.h , stm3210b_eval.h , stm3210c_eval.h , stm3210e_eval.h , stm32100b_eval.h
  • White : stm32_eval.h
  • WRITE_PROTECTION_DISABLE : STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/main.c
  • WRITE_READ_ADDR : STM32F10x_StdPeriph_Examples/FSMC/NOR/main.c , STM32F10x_StdPeriph_Examples/FSMC/SRAM/main.c
  • WRITE_REG : stm32f10x.h
  • WRP0_Mask : stm32f10x_flash.c
  • WRP1_Mask : stm32f10x_flash.c
  • WRP2_Mask : stm32f10x_flash.c
  • WRP3_Mask : stm32f10x_flash.c
  • WWDG : stm32f10x.h
  • WWDG_BASE : stm32f10x.h
  • WWDG_CFR_EWI : stm32f10x.h
  • WWDG_CFR_W : stm32f10x.h
  • WWDG_CFR_W0 : stm32f10x.h
  • WWDG_CFR_W1 : stm32f10x.h
  • WWDG_CFR_W2 : stm32f10x.h
  • WWDG_CFR_W3 : stm32f10x.h
  • WWDG_CFR_W4 : stm32f10x.h
  • WWDG_CFR_W5 : stm32f10x.h
  • WWDG_CFR_W6 : stm32f10x.h
  • WWDG_CFR_WDGTB : stm32f10x.h
  • WWDG_CFR_WDGTB0 : stm32f10x.h
  • WWDG_CFR_WDGTB1 : stm32f10x.h
  • WWDG_CR_T : stm32f10x.h
  • WWDG_CR_T0 : stm32f10x.h
  • WWDG_CR_T1 : stm32f10x.h
  • WWDG_CR_T2 : stm32f10x.h
  • WWDG_CR_T3 : stm32f10x.h
  • WWDG_CR_T4 : stm32f10x.h
  • WWDG_CR_T5 : stm32f10x.h
  • WWDG_CR_T6 : stm32f10x.h
  • WWDG_CR_WDGA : stm32f10x.h
  • WWDG_OFFSET : stm32f10x_wwdg.c
  • WWDG_Prescaler_1 : stm32f10x_wwdg.h
  • WWDG_Prescaler_2 : stm32f10x_wwdg.h
  • WWDG_Prescaler_4 : stm32f10x_wwdg.h
  • WWDG_Prescaler_8 : stm32f10x_wwdg.h
  • WWDG_SR_EWIF : stm32f10x.h


STM32F10x Standard Peripherals Firmware Library: Globals

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- y -

  • Yellow : stm32_eval.h


STM32F10x Standard Peripherals Firmware Library: Globals

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- a -

  • Apostrophe_Typedef : stm32l152_eval_glass_lcd.h

- b -

  • BitAction : stm32f10x_gpio.h
  • Button_TypeDef : stm32_eval.h
  • ButtonMode_TypeDef : stm32_eval.h

- c -

  • COM_TypeDef : stm32_eval.h

- e -

  • ErrorStatus : stm32f10x.h
  • EXTIMode_TypeDef : stm32f10x_exti.h
  • EXTITrigger_TypeDef : stm32f10x_exti.h

- f -

  • FlagStatus : stm32f10x.h
  • FLASH_Status : stm32f10x_flash.h
  • FunctionalState : stm32f10x.h

- g -

  • GPIOMode_TypeDef : stm32f10x_gpio.h
  • GPIOSpeed_TypeDef : stm32f10x_gpio.h

- h -

  • HDMI_CEC_Error : stm32100b_eval_cec.h , stm32100e_eval_cec.h

- i -

  • IOE_BitValue_TypeDef : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_DMADirection_TypeDef : stm3210c_eval_ioe.h , stm32100e_eval_ioe.h
  • IOE_Status_TypDef : stm3210c_eval_ioe.h , stm32100e_eval_ioe.h
  • IRQn : stm32f10x.h

- j -

  • JOYState_TypeDef : stm3210c_eval_ioe.h , stm32_eval.h

- l -

  • Led_TypeDef : stm32_eval.h
  • LM75_DMADirection_TypeDef : stm32_eval_i2c_tsensor.h
  • LM75_Status_TypDef : stm32_eval_i2c_tsensor.h

- n -

  • NOR_Status : stm3210e_eval_fsmc_nor.h

- o -

  • OneNAND_Status : stm32100e_eval_fsmc_onenand.h

- p -

  • Point_Typedef : stm32l152_eval_glass_lcd.h

- s -

  • SD_Error : stm32_eval_sdio_sd.h , stm32_eval_spi_sd.h
  • SDCardState : stm32_eval_sdio_sd.h
  • SDTransferState : stm32_eval_sdio_sd.h

- t -

  • TestStatus : STM32F10x_StdPeriph_Examples/CAN/LoopBack/main.c , STM32F10x_StdPeriph_Examples/USART/Synchronous/main.c , STM32F10x_StdPeriph_Examples/USART/Smartcard/main.c , STM32F10x_StdPeriph_Examples/USART/Polling/main.c , STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c , STM32F10x_StdPeriph_Examples/USART/HalfDuplex/main.c , STM32F10x_StdPeriph_Examples/USART/DMA_Polling/main.c , STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/main.c , STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/main.c , STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/main.c , STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/main.c , STM32F10x_StdPeriph_Examples/SPI/DMA/main.c , STM32F10x_StdPeriph_Examples/SPI/CRC/main.c , STM32F10x_StdPeriph_Examples/SDIO/uSDCard/main.c , STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/main.c , STM32F10x_StdPeriph_Examples/I2S/Interrupt/main.c , STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/main.c , STM32F10x_StdPeriph_Examples/I2C/EEPROM/main.c , STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/main.c , STM32F10x_StdPeriph_Examples/FLASH/Program/main.c , STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/main.c , STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/main.c , STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/main.c , STM32F10x_StdPeriph_Examples/DMA/FSMC/main.c , STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/main.c , STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/main.c


STM32F10x Standard Peripherals Firmware Library: Globals

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- a -

  • APOSTROPHE_OFF : stm32l152_eval_glass_lcd.h
  • APOSTROPHE_ON : stm32l152_eval_glass_lcd.h


STM32F10x Standard Peripherals Firmware Library: Globals

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- j -

  • JOY_DOWN : stm3210c_eval_ioe.h , stm32_eval.h
  • JOY_LEFT : stm32_eval.h , stm3210c_eval_ioe.h
  • JOY_NONE : stm3210c_eval_ioe.h , stm32_eval.h
  • JOY_RIGHT : stm32_eval.h , stm3210c_eval_ioe.h
  • JOY_SEL : stm32_eval.h , stm3210c_eval_ioe.h
  • JOY_UP : stm3210c_eval_ioe.h , stm32_eval.h


STM32F10x Standard Peripherals Firmware Library: Globals

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- l -

  • LED1 : stm32_eval.h
  • LED2 : stm32_eval.h
  • LED3 : stm32_eval.h
  • LED4 : stm32_eval.h
  • LM75_DMA_RX : stm32_eval_i2c_tsensor.h
  • LM75_DMA_TX : stm32_eval_i2c_tsensor.h
  • LM75_FAIL : stm32_eval_i2c_tsensor.h
  • LM75_OK : stm32_eval_i2c_tsensor.h


STM32F10x Standard Peripherals Firmware Library: Globals

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- m -

  • MemoryManagement_IRQn : stm32f10x.h


STM32F10x Standard Peripherals Firmware Library: Globals

  • File List
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- n -

  • NonMaskableInt_IRQn : stm32f10x.h
  • NOR_ERROR : stm3210e_eval_fsmc_nor.h
  • NOR_ONGOING : stm3210e_eval_fsmc_nor.h
  • NOR_SUCCESS : stm3210e_eval_fsmc_nor.h
  • NOR_TIMEOUT : stm3210e_eval_fsmc_nor.h


STM32F10x Standard Peripherals Firmware Library: Globals

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- o -

  • OneNAND_ERROR : stm32100e_eval_fsmc_onenand.h
  • OneNAND_ONGOING : stm32100e_eval_fsmc_onenand.h
  • OneNAND_SUCCESS : stm32100e_eval_fsmc_onenand.h
  • OneNAND_TIMEOUT : stm32100e_eval_fsmc_onenand.h


STM32F10x Standard Peripherals Firmware Library: Globals

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- b -

  • Bit_RESET : stm32f10x_gpio.h
  • Bit_SET : stm32f10x_gpio.h
  • BitReset : stm3210c_eval_ioe.h , stm32100e_eval_ioe.h
  • BitSet : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • BusFault_IRQn : stm32f10x.h
  • BUTTON_DOWN : stm32_eval.h
  • BUTTON_KEY : stm32_eval.h
  • BUTTON_LEFT : stm32_eval.h
  • BUTTON_MODE_EXTI : stm32_eval.h
  • BUTTON_MODE_GPIO : stm32_eval.h
  • BUTTON_RIGHT : stm32_eval.h
  • BUTTON_SEL : stm32_eval.h
  • BUTTON_TAMPER : stm32_eval.h
  • BUTTON_UP : stm32_eval.h
  • BUTTON_WAKEUP : stm32_eval.h


STM32F10x Standard Peripherals Firmware Library: Globals

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- c -

  • COM1 : stm32_eval.h
  • COM2 : stm32_eval.h


STM32F10x Standard Peripherals Firmware Library: Globals

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- d -

  • DebugMonitor_IRQn : stm32f10x.h
  • DISABLE : stm32f10x.h
  • DMA1_Channel1_IRQn : stm32f10x.h
  • DMA1_Channel2_IRQn : stm32f10x.h
  • DMA1_Channel3_IRQn : stm32f10x.h
  • DMA1_Channel4_IRQn : stm32f10x.h
  • DMA1_Channel5_IRQn : stm32f10x.h
  • DMA1_Channel6_IRQn : stm32f10x.h
  • DMA1_Channel7_IRQn : stm32f10x.h


STM32F10x Standard Peripherals Firmware Library: Globals

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- e -

  • ENABLE : stm32f10x.h
  • ERROR : stm32f10x.h
  • EXTI0_IRQn : stm32f10x.h
  • EXTI1_IRQn : stm32f10x.h
  • EXTI2_IRQn : stm32f10x.h
  • EXTI3_IRQn : stm32f10x.h
  • EXTI4_IRQn : stm32f10x.h
  • EXTI_Mode_Event : stm32f10x_exti.h
  • EXTI_Mode_Interrupt : stm32f10x_exti.h
  • EXTI_Trigger_Falling : stm32f10x_exti.h
  • EXTI_Trigger_Rising : stm32f10x_exti.h
  • EXTI_Trigger_Rising_Falling : stm32f10x_exti.h


STM32F10x Standard Peripherals Firmware Library: Globals

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- f -

  • FAILED : STM32F10x_StdPeriph_Examples/CAN/LoopBack/main.c , STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/main.c , STM32F10x_StdPeriph_Examples/DMA/FSMC/main.c , STM32F10x_StdPeriph_Examples/FLASH/Program/main.c , STM32F10x_StdPeriph_Examples/SPI/DMA/main.c , STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/main.c , STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/main.c , STM32F10x_StdPeriph_Examples/USART/Synchronous/main.c , STM32F10x_StdPeriph_Examples/USART/Smartcard/main.c , STM32F10x_StdPeriph_Examples/USART/Polling/main.c , STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c , STM32F10x_StdPeriph_Examples/USART/HalfDuplex/main.c , STM32F10x_StdPeriph_Examples/USART/DMA_Polling/main.c , STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/main.c , STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/main.c , STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/main.c , STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/main.c , STM32F10x_StdPeriph_Examples/I2C/EEPROM/main.c , STM32F10x_StdPeriph_Examples/SPI/CRC/main.c , STM32F10x_StdPeriph_Examples/SDIO/uSDCard/main.c , STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/main.c , STM32F10x_StdPeriph_Examples/I2S/Interrupt/main.c , STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/main.c , STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/main.c , STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/main.c , STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/main.c
  • FLASH_BUSY : stm32f10x_flash.h
  • FLASH_COMPLETE : stm32f10x_flash.h
  • FLASH_ERROR_PG : stm32f10x_flash.h
  • FLASH_ERROR_WRP : stm32f10x_flash.h
  • FLASH_IRQn : stm32f10x.h
  • FLASH_TIMEOUT : stm32f10x_flash.h


STM32F10x Standard Peripherals Firmware Library: Globals

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- g -

  • GPIO_Mode_AF_OD : stm32f10x_gpio.h
  • GPIO_Mode_AF_PP : stm32f10x_gpio.h
  • GPIO_Mode_AIN : stm32f10x_gpio.h
  • GPIO_Mode_IN_FLOATING : stm32f10x_gpio.h
  • GPIO_Mode_IPD : stm32f10x_gpio.h
  • GPIO_Mode_IPU : stm32f10x_gpio.h
  • GPIO_Mode_Out_OD : stm32f10x_gpio.h
  • GPIO_Mode_Out_PP : stm32f10x_gpio.h
  • GPIO_Speed_10MHz : stm32f10x_gpio.h
  • GPIO_Speed_2MHz : stm32f10x_gpio.h
  • GPIO_Speed_50MHz : stm32f10x_gpio.h


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- h -

  • HDMI_CEC_BIT_PERIOD : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_BIT_TIMING : stm32100e_eval_cec.h , stm32100b_eval_cec.h
  • HDMI_CEC_BLOCK_ACKNOWLEDGE : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_DEVICE_UNREGISTRED : stm32100e_eval_cec.h , stm32100b_eval_cec.h
  • HDMI_CEC_LINE : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_OK : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_RX_BLOCK_FINISHED : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_START_BIT : stm32100b_eval_cec.h , stm32100e_eval_cec.h
  • HDMI_CEC_TIMEOUT : stm32100e_eval_cec.h , stm32100b_eval_cec.h
  • HDMI_CEC_TX_BLOCK_FINISHED : stm32100e_eval_cec.h , stm32100b_eval_cec.h


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- i -

  • IOE1_NOT_OPERATIONAL : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE2_NOT_OPERATIONAL : stm3210c_eval_ioe.h
  • IOE_DMA_RX : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_DMA_TX : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_FAILURE : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_OK : stm3210c_eval_ioe.h , stm32100e_eval_ioe.h
  • IOE_TIMEOUT : stm3210c_eval_ioe.h , stm32100e_eval_ioe.h


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- p -

  • PARAM_ERROR : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • PASSED : STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/main.c , STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/main.c , STM32F10x_StdPeriph_Examples/SDIO/uSDCard/main.c , STM32F10x_StdPeriph_Examples/USART/Synchronous/main.c , STM32F10x_StdPeriph_Examples/USART/Smartcard/main.c , STM32F10x_StdPeriph_Examples/USART/Polling/main.c , STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c , STM32F10x_StdPeriph_Examples/USART/HalfDuplex/main.c , STM32F10x_StdPeriph_Examples/USART/DMA_Polling/main.c , STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/main.c , STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/main.c , STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/main.c , STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/main.c , STM32F10x_StdPeriph_Examples/SPI/CRC/main.c , STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/main.c , STM32F10x_StdPeriph_Examples/SPI/DMA/main.c , STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/main.c , STM32F10x_StdPeriph_Examples/I2S/Interrupt/main.c , STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/main.c , STM32F10x_StdPeriph_Examples/I2C/EEPROM/main.c , STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/main.c , STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/main.c , STM32F10x_StdPeriph_Examples/FLASH/Program/main.c , STM32F10x_StdPeriph_Examples/CAN/LoopBack/main.c , STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/main.c , STM32F10x_StdPeriph_Examples/DMA/FSMC/main.c
  • PendSV_IRQn : stm32f10x.h
  • POINT_OFF : stm32l152_eval_glass_lcd.h
  • POINT_ON : stm32l152_eval_glass_lcd.h
  • PVD_IRQn : stm32f10x.h


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- r -

  • RCC_IRQn : stm32f10x.h
  • RESET : stm32f10x.h
  • RTC_IRQn : stm32f10x.h


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- s -

  • SD_ADDR_MISALIGNED : stm32_eval_sdio_sd.h
  • SD_ADDR_OUT_OF_RANGE : stm32_eval_sdio_sd.h
  • SD_ADDRESS_ERROR : stm32_eval_spi_sd.h
  • SD_AKE_SEQ_ERROR : stm32_eval_sdio_sd.h
  • SD_BAD_ERASE_PARAM : stm32_eval_sdio_sd.h
  • SD_BLOCK_LEN_ERR : stm32_eval_sdio_sd.h
  • SD_CARD_DISCONNECTED : stm32_eval_sdio_sd.h
  • SD_CARD_ECC_DISABLED : stm32_eval_sdio_sd.h
  • SD_CARD_ECC_FAILED : stm32_eval_sdio_sd.h
  • SD_CARD_ERROR : stm32_eval_sdio_sd.h
  • SD_CARD_IDENTIFICATION : stm32_eval_sdio_sd.h
  • SD_CARD_PROGRAMMING : stm32_eval_sdio_sd.h
  • SD_CARD_READY : stm32_eval_sdio_sd.h
  • SD_CARD_RECEIVING : stm32_eval_sdio_sd.h
  • SD_CARD_SENDING : stm32_eval_sdio_sd.h
  • SD_CARD_STANDBY : stm32_eval_sdio_sd.h
  • SD_CARD_TRANSFER : stm32_eval_sdio_sd.h
  • SD_CC_ERROR : stm32_eval_sdio_sd.h
  • SD_CID_CSD_OVERWRITE : stm32_eval_sdio_sd.h
  • SD_CMD_CRC_FAIL : stm32_eval_sdio_sd.h
  • SD_CMD_OUT_OF_RANGE : stm32_eval_sdio_sd.h
  • SD_CMD_RSP_TIMEOUT : stm32_eval_sdio_sd.h
  • SD_COM_CRC_ERROR : stm32_eval_spi_sd.h
  • SD_COM_CRC_FAILED : stm32_eval_sdio_sd.h
  • SD_DATA_CRC_ERROR : stm32_eval_spi_sd.h
  • SD_DATA_CRC_FAIL : stm32_eval_sdio_sd.h
  • SD_DATA_OK : stm32_eval_spi_sd.h
  • SD_DATA_OTHER_ERROR : stm32_eval_spi_sd.h
  • SD_DATA_TIMEOUT : stm32_eval_sdio_sd.h
  • SD_DATA_WRITE_ERROR : stm32_eval_spi_sd.h
  • SD_ERASE_RESET : stm32_eval_spi_sd.h , stm32_eval_sdio_sd.h
  • SD_ERASE_SEQ_ERR : stm32_eval_sdio_sd.h
  • SD_ERASE_SEQUENCE_ERROR : stm32_eval_spi_sd.h
  • SD_ERROR : stm32_eval_sdio_sd.h
  • SD_GENERAL_UNKNOWN_ERROR : stm32_eval_sdio_sd.h
  • SD_ILLEGAL_CMD : stm32_eval_sdio_sd.h
  • SD_ILLEGAL_COMMAND : stm32_eval_spi_sd.h
  • SD_IN_IDLE_STATE : stm32_eval_spi_sd.h
  • SD_INTERNAL_ERROR : stm32_eval_sdio_sd.h
  • SD_INVALID_PARAMETER : stm32_eval_sdio_sd.h
  • SD_INVALID_VOLTRANGE : stm32_eval_sdio_sd.h
  • SD_LOCK_UNLOCK_FAILED : stm32_eval_sdio_sd.h
  • SD_NOT_CONFIGURED : stm32_eval_sdio_sd.h
  • SD_OK : stm32_eval_sdio_sd.h
  • SD_PARAMETER_ERROR : stm32_eval_spi_sd.h
  • SD_REQUEST_NOT_APPLICABLE : stm32_eval_sdio_sd.h
  • SD_REQUEST_PENDING : stm32_eval_sdio_sd.h
  • SD_RESPONSE_FAILURE : stm32_eval_spi_sd.h
  • SD_RESPONSE_NO_ERROR : stm32_eval_spi_sd.h
  • SD_RX_OVERRUN : stm32_eval_sdio_sd.h
  • SD_SDIO_DISABLED : stm32_eval_sdio_sd.h
  • SD_SDIO_FUNCTION_BUSY : stm32_eval_sdio_sd.h
  • SD_SDIO_FUNCTION_FAILED : stm32_eval_sdio_sd.h
  • SD_SDIO_UNKNOWN_FUNCTION : stm32_eval_sdio_sd.h
  • SD_START_BIT_ERR : stm32_eval_sdio_sd.h
  • SD_STREAM_READ_UNDERRUN : stm32_eval_sdio_sd.h
  • SD_STREAM_WRITE_OVERRUN : stm32_eval_sdio_sd.h
  • SD_SWITCH_ERROR : stm32_eval_sdio_sd.h
  • SD_TRANSFER_BUSY : stm32_eval_sdio_sd.h
  • SD_TRANSFER_ERROR : stm32_eval_sdio_sd.h
  • SD_TRANSFER_OK : stm32_eval_sdio_sd.h
  • SD_TX_UNDERRUN : stm32_eval_sdio_sd.h
  • SD_UNSUPPORTED_FEATURE : stm32_eval_sdio_sd.h
  • SD_UNSUPPORTED_HW : stm32_eval_sdio_sd.h
  • SD_WP_ERASE_SKIP : stm32_eval_sdio_sd.h
  • SD_WRITE_PROT_VIOLATION : stm32_eval_sdio_sd.h
  • SET : stm32f10x.h
  • SUCCESS : stm32f10x.h
  • SVCall_IRQn : stm32f10x.h
  • SysTick_IRQn : stm32f10x.h


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- t -

  • TAMPER_IRQn : stm32f10x.h


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- u -

  • UsageFault_IRQn : stm32f10x.h


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- w -

  • WWDG_IRQn : stm32f10x.h


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- a -

  • accesspermission() : accesspermission.c , CortexM3/MPU/main.h
  • ADC1_2_IRQHandler() : STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_it.c
  • ADC_AnalogWatchdogCmd() : stm32f10x_adc.h , stm32f10x_adc.c
  • ADC_AnalogWatchdogSingleChannelConfig() : stm32f10x_adc.h , stm32f10x_adc.c
  • ADC_AnalogWatchdogThresholdsConfig() : stm32f10x_adc.c , stm32f10x_adc.h
  • ADC_AutoInjectedConvCmd() : stm32f10x_adc.h , stm32f10x_adc.c
  • ADC_ClearFlag() : stm32f10x_adc.h , stm32f10x_adc.c
  • ADC_ClearITPendingBit() : stm32f10x_adc.h , stm32f10x_adc.c
  • ADC_Cmd() : stm32f10x_adc.h , stm32f10x_adc.c
  • ADC_DeInit() : stm32f10x_adc.h , stm32f10x_adc.c
  • ADC_DiscModeChannelCountConfig() : stm32f10x_adc.h , stm32f10x_adc.c
  • ADC_DiscModeCmd() : stm32f10x_adc.h , stm32f10x_adc.c
  • ADC_DMACmd() : stm32f10x_adc.c , stm32f10x_adc.h
  • ADC_ExternalTrigConvCmd() : stm32f10x_adc.h , stm32f10x_adc.c
  • ADC_ExternalTrigInjectedConvCmd() : stm32f10x_adc.h , stm32f10x_adc.c
  • ADC_ExternalTrigInjectedConvConfig() : stm32f10x_adc.h , stm32f10x_adc.c
  • ADC_GetCalibrationStatus() : stm32f10x_adc.h , stm32f10x_adc.c
  • ADC_GetConversionValue() : stm32f10x_adc.h , stm32f10x_adc.c
  • ADC_GetDualModeConversionValue() : stm32f10x_adc.h , stm32f10x_adc.c
  • ADC_GetFlagStatus() : stm32f10x_adc.h , stm32f10x_adc.c
  • ADC_GetInjectedConversionValue() : stm32f10x_adc.h , stm32f10x_adc.c
  • ADC_GetITStatus() : stm32f10x_adc.h , stm32f10x_adc.c
  • ADC_GetResetCalibrationStatus() : stm32f10x_adc.h , stm32f10x_adc.c
  • ADC_GetSoftwareStartConvStatus() : stm32f10x_adc.h , stm32f10x_adc.c
  • ADC_GetSoftwareStartInjectedConvCmdStatus() : stm32f10x_adc.h , stm32f10x_adc.c
  • ADC_Init() : stm32f10x_adc.h , stm32f10x_adc.c
  • ADC_InjectedChannelConfig() : stm32f10x_adc.h , stm32f10x_adc.c
  • ADC_InjectedDiscModeCmd() : stm32f10x_adc.h , stm32f10x_adc.c
  • ADC_InjectedSequencerLengthConfig() : stm32f10x_adc.c , stm32f10x_adc.h
  • ADC_ITConfig() : stm32f10x_adc.h , stm32f10x_adc.c
  • ADC_RegularChannelConfig() : stm32f10x_adc.c , stm32f10x_adc.h
  • ADC_ResetCalibration() : stm32f10x_adc.h , stm32f10x_adc.c
  • ADC_SetInjectedOffset() : stm32f10x_adc.c , stm32f10x_adc.h
  • ADC_SoftwareStartConvCmd() : stm32f10x_adc.c , stm32f10x_adc.h
  • ADC_SoftwareStartInjectedConvCmd() : stm32f10x_adc.c , stm32f10x_adc.h
  • ADC_StartCalibration() : stm32f10x_adc.c , stm32f10x_adc.h
  • ADC_StructInit() : stm32f10x_adc.c , stm32f10x_adc.h
  • ADC_TempSensorVrefintCmd() : stm32f10x_adc.c , stm32f10x_adc.h
  • assert_failed() : STM32F10x_StdPeriph_Examples/I2C/EEPROM/stm32f10x_conf.h


STM32F10x Standard Peripherals Firmware Library: Globals

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- l -

  • LCD_Clear() : stm32100b_eval_lcd.c , stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.c , stm3210b_eval_lcd.c , stm3210e_eval_lcd.h , stm32l152_eval_lcd.c , stm32100e_eval_lcd.c , stm3210b_eval_lcd.h , stm32l152_eval_lcd.h , stm3210c_eval_lcd.c
  • LCD_ClearLine() : stm32100e_eval_lcd.h , stm3210b_eval_lcd.c , stm3210b_eval_lcd.h , stm3210c_eval_lcd.c , stm3210c_eval_lcd.h , stm3210e_eval_lcd.c , stm3210e_eval_lcd.h , stm32l152_eval_lcd.c , stm32l152_eval_lcd.h , stm32100b_eval_lcd.c , stm32100b_eval_lcd.h , stm32100e_eval_lcd.c
  • LCD_ClosedPolyLine() : stm3210c_eval_lcd.h , stm3210e_eval_lcd.c , stm3210e_eval_lcd.h , stm32l152_eval_lcd.c , stm32l152_eval_lcd.h , stm32100b_eval_lcd.c , stm32100b_eval_lcd.h , stm32100e_eval_lcd.c , stm32100e_eval_lcd.h , stm3210b_eval_lcd.c , stm3210b_eval_lcd.h , stm3210c_eval_lcd.c
  • LCD_ClosedPolyLineRelative() : stm32100b_eval_lcd.c , stm32100b_eval_lcd.h , stm32100e_eval_lcd.c , stm32100e_eval_lcd.h , stm3210b_eval_lcd.c , stm3210b_eval_lcd.h , stm3210c_eval_lcd.c , stm3210c_eval_lcd.h , stm3210e_eval_lcd.c , stm3210e_eval_lcd.h , stm32l152_eval_lcd.c , stm32l152_eval_lcd.h
  • LCD_CtrlLinesConfig() : stm32100b_eval_lcd.c , stm32100b_eval_lcd.h , stm32100e_eval_lcd.c , stm32100e_eval_lcd.h , stm3210b_eval_lcd.c , stm3210b_eval_lcd.h , stm3210c_eval_lcd.c , stm3210c_eval_lcd.h , stm3210e_eval_lcd.c , stm3210e_eval_lcd.h , stm32l152_eval_lcd.c , stm32l152_eval_lcd.h
  • LCD_CtrlLinesWrite() : stm3210b_eval_lcd.h , stm3210c_eval_lcd.c , stm3210c_eval_lcd.h , stm32l152_eval_lcd.c , stm32l152_eval_lcd.h , stm32100b_eval_lcd.c , stm32100b_eval_lcd.h , stm3210b_eval_lcd.c
  • LCD_DeInit() : stm32100b_eval_lcd.c , stm32100b_eval_lcd.h , stm32100e_eval_lcd.c , stm32100e_eval_lcd.h , stm3210b_eval_lcd.c , stm3210b_eval_lcd.h , stm3210c_eval_lcd.c , stm3210c_eval_lcd.h , stm3210e_eval_lcd.c , stm3210e_eval_lcd.h
  • LCD_DisplayChar() : stm32100b_eval_lcd.c , stm32100b_eval_lcd.h , stm32100e_eval_lcd.c , stm32100e_eval_lcd.h , stm3210b_eval_lcd.c , stm3210b_eval_lcd.h , stm3210c_eval_lcd.c , stm3210c_eval_lcd.h , stm3210e_eval_lcd.c , stm3210e_eval_lcd.h , stm32l152_eval_lcd.c , stm32l152_eval_lcd.h
  • LCD_DisplayOff() : stm32100b_eval_lcd.c , stm32100b_eval_lcd.h , stm32100e_eval_lcd.c , stm32100e_eval_lcd.h , stm3210b_eval_lcd.c , stm3210b_eval_lcd.h , stm3210c_eval_lcd.c , stm3210c_eval_lcd.h , stm3210e_eval_lcd.c , stm3210e_eval_lcd.h , stm32l152_eval_lcd.c , stm32l152_eval_lcd.h
  • LCD_DisplayOn() : stm32100b_eval_lcd.c , stm32100b_eval_lcd.h , stm32100e_eval_lcd.c , stm32100e_eval_lcd.h , stm3210b_eval_lcd.c , stm3210b_eval_lcd.h , stm3210c_eval_lcd.c , stm3210c_eval_lcd.h , stm3210e_eval_lcd.c , stm3210e_eval_lcd.h , stm32l152_eval_lcd.c , stm32l152_eval_lcd.h
  • LCD_DisplayStringLine() : stm32100b_eval_lcd.c , stm32100b_eval_lcd.h , stm32100e_eval_lcd.c , stm32100e_eval_lcd.h , stm3210b_eval_lcd.c , stm3210b_eval_lcd.h , stm3210c_eval_lcd.c , stm3210c_eval_lcd.h , stm3210e_eval_lcd.c , stm3210e_eval_lcd.h , stm32l152_eval_lcd.c , stm32l152_eval_lcd.h
  • LCD_DrawBMP() : stm3210b_eval_lcd.h , stm32l152_eval_lcd.h , stm32100b_eval_lcd.h
  • LCD_DrawChar() : stm32100b_eval_lcd.c , stm32100b_eval_lcd.h , stm32100e_eval_lcd.c , stm32100e_eval_lcd.h , stm3210b_eval_lcd.c , stm3210b_eval_lcd.h , stm3210c_eval_lcd.c , stm3210c_eval_lcd.h , stm3210e_eval_lcd.c , stm3210e_eval_lcd.h , stm32l152_eval_lcd.c , stm32l152_eval_lcd.h
  • LCD_DrawCircle() : stm32100b_eval_lcd.c , stm32100b_eval_lcd.h , stm32100e_eval_lcd.c , stm32100e_eval_lcd.h , stm3210b_eval_lcd.c , stm3210b_eval_lcd.h , stm3210c_eval_lcd.c , stm3210c_eval_lcd.h , stm3210e_eval_lcd.c , stm3210e_eval_lcd.h , stm32l152_eval_lcd.c , stm32l152_eval_lcd.h
  • LCD_DrawFullCircle() : stm32100b_eval_lcd.c , stm32100b_eval_lcd.h , stm32100e_eval_lcd.c , stm32100e_eval_lcd.h , stm3210b_eval_lcd.c , stm3210b_eval_lcd.h , stm3210c_eval_lcd.c , stm3210c_eval_lcd.h , stm3210e_eval_lcd.c , stm3210e_eval_lcd.h , stm32l152_eval_lcd.c , stm32l152_eval_lcd.h
  • LCD_DrawFullRect() : stm32100b_eval_lcd.c , stm32100b_eval_lcd.h , stm32100e_eval_lcd.c , stm32100e_eval_lcd.h , stm3210b_eval_lcd.c , stm3210b_eval_lcd.h , stm3210c_eval_lcd.c , stm3210c_eval_lcd.h , stm3210e_eval_lcd.c , stm3210e_eval_lcd.h , stm32l152_eval_lcd.c , stm32l152_eval_lcd.h
  • LCD_DrawLine() : stm32100b_eval_lcd.c , stm32100b_eval_lcd.h , stm32100e_eval_lcd.c , stm32100e_eval_lcd.h , stm3210b_eval_lcd.c , stm3210b_eval_lcd.h , stm3210c_eval_lcd.c , stm3210c_eval_lcd.h , stm3210e_eval_lcd.c , stm3210e_eval_lcd.h , stm32l152_eval_lcd.c , stm32l152_eval_lcd.h
  • LCD_DrawMonoPict() : stm32100b_eval_lcd.c , stm32100b_eval_lcd.h , stm32100e_eval_lcd.c , stm32100e_eval_lcd.h , stm3210b_eval_lcd.c , stm3210b_eval_lcd.h , stm3210c_eval_lcd.c , stm3210c_eval_lcd.h , stm3210e_eval_lcd.c , stm3210e_eval_lcd.h , stm32l152_eval_lcd.c , stm32l152_eval_lcd.h
  • LCD_DrawRect() : stm32100b_eval_lcd.c , stm32100b_eval_lcd.h , stm32100e_eval_lcd.c , stm32100e_eval_lcd.h , stm3210b_eval_lcd.c , stm3210b_eval_lcd.h , stm3210c_eval_lcd.c , stm3210c_eval_lcd.h , stm3210e_eval_lcd.c , stm3210e_eval_lcd.h , stm32l152_eval_lcd.c , stm32l152_eval_lcd.h
  • LCD_DrawUniLine() : stm32100b_eval_lcd.c , stm32100b_eval_lcd.h , stm32100e_eval_lcd.c , stm32100e_eval_lcd.h , stm3210b_eval_lcd.c , stm3210b_eval_lcd.h , stm3210c_eval_lcd.c , stm3210c_eval_lcd.h , stm3210e_eval_lcd.c , stm3210e_eval_lcd.h , stm32l152_eval_lcd.c , stm32l152_eval_lcd.h
  • LCD_FillPolyLine() : stm32100b_eval_lcd.c , stm32100b_eval_lcd.h , stm32100e_eval_lcd.c , stm32100e_eval_lcd.h , stm3210b_eval_lcd.c , stm3210b_eval_lcd.h , stm3210c_eval_lcd.c , stm3210c_eval_lcd.h , stm3210e_eval_lcd.c , stm3210e_eval_lcd.h , stm32l152_eval_lcd.c , stm32l152_eval_lcd.h
  • LCD_FSMCConfig() : stm32100e_eval_lcd.c , stm32100e_eval_lcd.h , stm3210e_eval_lcd.c , stm3210e_eval_lcd.h
  • LCD_GetColors() : stm32100b_eval_lcd.c , stm32100b_eval_lcd.h , stm32100e_eval_lcd.c , stm32100e_eval_lcd.h , stm3210b_eval_lcd.c , stm3210b_eval_lcd.h , stm3210c_eval_lcd.c , stm3210c_eval_lcd.h , stm3210e_eval_lcd.c , stm3210e_eval_lcd.h , stm32l152_eval_lcd.c , stm32l152_eval_lcd.h
  • LCD_GetFont() : stm32100e_eval_lcd.c , stm32100e_eval_lcd.h , stm3210b_eval_lcd.c , stm3210b_eval_lcd.h , stm3210c_eval_lcd.c , stm3210c_eval_lcd.h , stm3210e_eval_lcd.c , stm3210e_eval_lcd.h , stm32l152_eval_lcd.c , stm32l152_eval_lcd.h , stm32100b_eval_lcd.c , stm32100b_eval_lcd.h
  • LCD_GLASS_Clear() : stm32l152_eval_glass_lcd.c , stm32l152_eval_glass_lcd.h
  • LCD_GLASS_ClearChar() : stm32l152_eval_glass_lcd.c , stm32l152_eval_glass_lcd.h
  • LCD_GLASS_DisplayChar() : stm32l152_eval_glass_lcd.c , stm32l152_eval_glass_lcd.h
  • LCD_GLASS_DisplayString() : stm32l152_eval_glass_lcd.c , stm32l152_eval_glass_lcd.h
  • LCD_GLASS_Init() : stm32l152_eval_glass_lcd.c , stm32l152_eval_glass_lcd.h
  • LCD_GLASS_ScrollString() : stm32l152_eval_glass_lcd.c , stm32l152_eval_glass_lcd.h
  • LCD_GLASS_WriteChar() : stm32l152_eval_glass_lcd.h , stm32l152_eval_glass_lcd.c
  • LCD_GPIOConfig() : stm32l152_eval_glass_lcd.c
  • LCD_nCS_StartByte() : stm3210b_eval_lcd.c , stm32100b_eval_lcd.c , stm32100b_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.c , stm3210c_eval_lcd.h , stm32l152_eval_lcd.h , stm32l152_eval_lcd.c
  • LCD_PolyLine() : stm3210c_eval_lcd.c , stm32100b_eval_lcd.c , stm32100b_eval_lcd.h , stm32100e_eval_lcd.c , stm32100e_eval_lcd.h , stm3210b_eval_lcd.c , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h , stm3210e_eval_lcd.c , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h , stm32l152_eval_lcd.c
  • LCD_PolyLineRelative() : stm32100b_eval_lcd.c , stm32100b_eval_lcd.h , stm32100e_eval_lcd.h , stm3210b_eval_lcd.c , stm3210b_eval_lcd.h , stm3210c_eval_lcd.c , stm3210c_eval_lcd.h , stm3210e_eval_lcd.c , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h , stm32l152_eval_lcd.c , stm32100e_eval_lcd.c
  • LCD_PolyLineRelativeClosed() : stm32100b_eval_lcd.c , stm32100e_eval_lcd.c , stm3210c_eval_lcd.c , stm3210e_eval_lcd.c , stm32l152_eval_lcd.c , stm3210b_eval_lcd.c
  • LCD_PowerOn() : stm32100b_eval_lcd.h , stm32100e_eval_lcd.c , stm32100e_eval_lcd.h , stm3210b_eval_lcd.c , stm3210b_eval_lcd.h , stm3210c_eval_lcd.c , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.c , stm32l152_eval_lcd.h , stm3210e_eval_lcd.c , stm32100b_eval_lcd.c
  • LCD_ReadRAM() : stm32100e_eval_lcd.h , stm3210e_eval_lcd.c , stm3210e_eval_lcd.h , stm32100e_eval_lcd.c
  • LCD_ReadReg() : stm32100b_eval_lcd.h , stm32100e_eval_lcd.c , stm32100e_eval_lcd.h , stm3210b_eval_lcd.c , stm3210b_eval_lcd.h , stm3210c_eval_lcd.c , stm3210c_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.c , stm32l152_eval_lcd.h , stm3210e_eval_lcd.c , stm32100b_eval_lcd.c
  • LCD_SetBackColor() : stm32100b_eval_lcd.h , stm32100e_eval_lcd.c , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.c , stm3210c_eval_lcd.h , stm3210e_eval_lcd.c , stm3210e_eval_lcd.h , stm32l152_eval_lcd.c , stm32l152_eval_lcd.h , stm32100b_eval_lcd.c , stm3210b_eval_lcd.c
  • LCD_SetColors() : stm32100b_eval_lcd.h , stm32100e_eval_lcd.c , stm32100e_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.c , stm3210c_eval_lcd.h , stm3210b_eval_lcd.c , stm3210e_eval_lcd.h , stm32l152_eval_lcd.c , stm32l152_eval_lcd.h , stm3210e_eval_lcd.c , stm32100b_eval_lcd.c
  • LCD_SetCursor() : stm3210e_eval_lcd.h , stm32100b_eval_lcd.c , stm32100e_eval_lcd.h , stm3210b_eval_lcd.c , stm3210c_eval_lcd.h , stm32100b_eval_lcd.h , stm3210b_eval_lcd.h , stm32100e_eval_lcd.c , stm3210c_eval_lcd.c , stm32l152_eval_lcd.c , stm32l152_eval_lcd.h , stm3210e_eval_lcd.c
  • LCD_SetDisplayWindow() : stm32l152_eval_lcd.c , stm3210b_eval_lcd.c , stm3210e_eval_lcd.c , stm32100b_eval_lcd.c , stm3210c_eval_lcd.h , stm3210c_eval_lcd.c , stm32100b_eval_lcd.h , stm32100e_eval_lcd.c , stm3210b_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.h , stm32100e_eval_lcd.h
  • LCD_SetFont() : stm3210e_eval_lcd.c , stm3210b_eval_lcd.c , stm3210c_eval_lcd.h , stm32100b_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.c , stm3210e_eval_lcd.h , stm32100e_eval_lcd.c , stm32100e_eval_lcd.h , stm32100b_eval_lcd.c , stm32l152_eval_lcd.c , stm32l152_eval_lcd.h
  • LCD_SetTextColor() : stm32100e_eval_lcd.c , stm3210c_eval_lcd.c , stm3210b_eval_lcd.c , stm3210e_eval_lcd.c , stm32100b_eval_lcd.c , stm32100e_eval_lcd.h , stm32100b_eval_lcd.h , stm3210b_eval_lcd.h , stm3210e_eval_lcd.h , stm32l152_eval_lcd.c , stm32l152_eval_lcd.h , stm3210c_eval_lcd.h
  • LCD_Setup() : stm32100b_eval_lcd.c , stm3210b_eval_lcd.c , stm3210c_eval_lcd.c , stm3210b_eval_lcd.h , stm32100b_eval_lcd.h , stm3210c_eval_lcd.h , stm32l152_eval_lcd.h , stm32l152_eval_lcd.c
  • LCD_SPIConfig() : stm32100b_eval_lcd.h , stm3210c_eval_lcd.h , stm32l152_eval_lcd.c , stm32l152_eval_lcd.h , stm3210c_eval_lcd.c , stm32100b_eval_lcd.c , stm3210b_eval_lcd.h , stm3210b_eval_lcd.c
  • LCD_WindowModeDisable() : stm32100e_eval_lcd.h , stm3210c_eval_lcd.h , stm32100b_eval_lcd.h , stm3210b_eval_lcd.h , stm3210e_eval_lcd.h , stm3210c_eval_lcd.c , stm3210b_eval_lcd.c , stm32l152_eval_lcd.h , stm32l152_eval_lcd.c , stm32100b_eval_lcd.c , stm32100e_eval_lcd.c , stm3210e_eval_lcd.c
  • LCD_WriteBMP() : stm32100e_eval_lcd.c , stm3210e_eval_lcd.h , stm32100e_eval_lcd.h , stm3210e_eval_lcd.c
  • LCD_WriteRAM() : stm3210c_eval_lcd.c , stm32100e_eval_lcd.c , stm32100e_eval_lcd.h , stm3210e_eval_lcd.h , stm32100b_eval_lcd.h , stm3210b_eval_lcd.c , stm32l152_eval_lcd.c , stm3210c_eval_lcd.h , stm32l152_eval_lcd.h , stm3210e_eval_lcd.c , stm3210b_eval_lcd.h , stm32100b_eval_lcd.c
  • LCD_WriteRAM_Prepare() : stm32l152_eval_lcd.h , stm32l152_eval_lcd.c , stm3210e_eval_lcd.c , stm32100e_eval_lcd.h , stm3210c_eval_lcd.c , stm3210c_eval_lcd.h , stm3210b_eval_lcd.c , stm32100b_eval_lcd.c , stm32100e_eval_lcd.c , stm32100b_eval_lcd.h , stm3210b_eval_lcd.h , stm3210e_eval_lcd.h
  • LCD_WriteRAMWord() : stm32l152_eval_lcd.c , stm3210c_eval_lcd.c , stm3210b_eval_lcd.c , stm32100b_eval_lcd.c , stm32100b_eval_lcd.h , stm32l152_eval_lcd.h , stm3210b_eval_lcd.h , stm3210c_eval_lcd.h
  • LCD_WriteReg() : stm3210c_eval_lcd.h , stm32100e_eval_lcd.c , stm32100b_eval_lcd.c , stm32100e_eval_lcd.h , stm3210b_eval_lcd.c , stm3210e_eval_lcd.c , stm32100b_eval_lcd.h , stm32l152_eval_lcd.h , stm3210e_eval_lcd.h , stm3210c_eval_lcd.c , stm3210b_eval_lcd.h , stm32l152_eval_lcd.c
  • LCD_WriteRegHX8312() : stm32100b_eval_lcd.c , stm3210b_eval_lcd.c
  • LCD_WriteRegILI9320() : stm3210b_eval_lcd.c , stm32100b_eval_lcd.c
  • LCD_WriteRegIndex() : stm3210b_eval_lcd.c , stm3210c_eval_lcd.c , stm3210b_eval_lcd.h , stm32l152_eval_lcd.h , stm32l152_eval_lcd.c , stm3210c_eval_lcd.h , stm32100b_eval_lcd.h , stm32100b_eval_lcd.c
  • LED_Display() : STM32F10x_StdPeriph_Examples/CAN/DualCAN/main.c , STM32F10x_StdPeriph_Examples/CAN/Networking/main.c
  • LM75_DeInit() : stm32_eval_i2c_tsensor.h , stm32_eval_i2c_tsensor.c
  • LM75_DMA_Config() : stm32_eval_i2c_tsensor.c
  • LM75_GetStatus() : stm32_eval_i2c_tsensor.h , stm32_eval_i2c_tsensor.c
  • LM75_Init() : stm32_eval_i2c_tsensor.h , stm32_eval_i2c_tsensor.c
  • LM75_LowLevel_DeInit() : stm3210e_eval.h , stm3210b_eval.c , stm32100e_eval.h , stm32100e_eval.c , stm32100b_eval.h , stm32l152_eval.c , stm3210e_eval.c , stm32l152_eval.h , stm3210b_eval.h , stm32100b_eval.c
  • LM75_LowLevel_Init() : stm3210e_eval.h , stm32100b_eval.h , stm3210b_eval.c , stm32l152_eval.h , stm32100b_eval.c , stm3210b_eval.h , stm32100e_eval.c , stm3210e_eval.c , stm32100e_eval.h , stm32l152_eval.c
  • LM75_ReadConfReg() : stm32_eval_i2c_tsensor.c , stm32_eval_i2c_tsensor.h
  • LM75_ReadReg() : stm32_eval_i2c_tsensor.c , stm32_eval_i2c_tsensor.h
  • LM75_ReadTemp() : stm32_eval_i2c_tsensor.h , stm32_eval_i2c_tsensor.c
  • LM75_ShutDown() : stm32_eval_i2c_tsensor.c , stm32_eval_i2c_tsensor.h
  • LM75_WriteConfReg() : stm32_eval_i2c_tsensor.h , stm32_eval_i2c_tsensor.c
  • LM75_WriteReg() : stm32_eval_i2c_tsensor.h , stm32_eval_i2c_tsensor.c
  • LogicalAddressAllocation() : stm32100b_eval_cec.c , stm32100e_eval_cec.c


STM32F10x Standard Peripherals Firmware Library: Globals

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- m -

  • main() : STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c , STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/main.c , STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/main.c , STM32F10x_StdPeriph_Examples/BKP/Tamper/main.c , STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/main.c , STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/main.c , STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/main.c , STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/main.c , STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/main.c , STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/main.c , STM32F10x_StdPeriph_Examples/TIM/DMA/main.c , STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/main.c , STM32F10x_StdPeriph_Examples/FSMC/OneNAND/main.c , STM32F10x_StdPeriph_Examples/TIM/DMABurst/main.c , STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/main.c , STM32F10x_StdPeriph_Examples/FSMC/SRAM/main.c , STM32F10x_StdPeriph_Examples/TIM/InputCapture/main.c , STM32F10x_StdPeriph_Examples/TIM/OCActive/main.c , STM32F10x_StdPeriph_Examples/CAN/DualCAN/main.c , STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/main.c , STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/main.c , STM32F10x_StdPeriph_Examples/TIM/OCInactive/main.c , STM32F10x_StdPeriph_Examples/TIM/OCToggle/main.c , STM32F10x_StdPeriph_Examples/GPIO/IOToggle/main.c , STM32F10x_StdPeriph_Examples/TIM/OnePulse/main.c , STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/main.c , STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/main.c , STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/main.c , STM32F10x_StdPeriph_Examples/TIM/PWM_Input/main.c , STM32F10x_StdPeriph_Examples/TIM/PWM_Output/main.c , STM32F10x_StdPeriph_Examples/I2C/EEPROM/main.c , STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/main.c , STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/main.c , STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/main.c , STM32F10x_StdPeriph_Examples/CAN/LoopBack/main.c , STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/main.c , STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/main.c , STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/main.c , STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/main.c , STM32F10x_StdPeriph_Examples/I2C/IOExpander/main.c , STM32F10x_StdPeriph_Examples/TIM/TimeBase/main.c , STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/main.c , STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/main.c , STM32F10x_StdPeriph_Examples/I2S/Interrupt/main.c , STM32F10x_StdPeriph_Examples/USART/DMA_Polling/main.c , STM32F10x_StdPeriph_Examples/USART/HalfDuplex/main.c , STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/main.c , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/main.c , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/main.c , STM32F10x_StdPeriph_Examples/CAN/Networking/main.c , STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/main.c , STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/main.c , STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c , STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/main.c , STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/main.c , STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/main.c , STM32F10x_StdPeriph_Examples/USART/MultiProcessor/main.c , STM32F10x_StdPeriph_Examples/DMA/FSMC/main.c , STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/main.c , STM32F10x_StdPeriph_Examples/USART/Polling/main.c , STM32F10x_StdPeriph_Examples/USART/Printf/main.c , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/main.c , STM32F10x_StdPeriph_Examples/USART/Smartcard/main.c , STM32F10x_StdPeriph_Examples/USART/Synchronous/main.c , STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/main.c , STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/main.c , STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/main.c , STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/main.c , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/main.c , STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/main.c , STM32F10x_StdPeriph_Template/main.c , STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/main.c , STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/main.c , STM32F10x_StdPeriph_Examples/PWR/PVD/main.c , STM32F10x_StdPeriph_Examples/PWR/STANDBY/main.c , STM32F10x_StdPeriph_Examples/CortexM3/BitBand/main.c , STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/main.c , STM32F10x_StdPeriph_Examples/PWR/STOP/main.c , STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/main.c , STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/main.c , STM32F10x_StdPeriph_Examples/RTC/Calendar/main.c , STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/main.c , STM32F10x_StdPeriph_Examples/BKP/Backup_Data/main.c , STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/main.c , STM32F10x_StdPeriph_Examples/FLASH/Program/main.c , STM32F10x_StdPeriph_Examples/SDIO/uSDCard/main.c , STM32F10x_StdPeriph_Examples/SPI/CRC/main.c , STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/main.c , STM32F10x_StdPeriph_Examples/SPI/DMA/main.c , STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/main.c , STM32F10x_StdPeriph_Examples/CortexM3/MPU/main.c , STM32F10x_StdPeriph_Examples/FSMC/NAND/main.c , STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/main.c , STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/main.c , STM32F10x_StdPeriph_Examples/FSMC/NOR/main.c , STM32F10x_StdPeriph_Examples/SysTick/TimeBase/main.c , STM32F10x_StdPeriph_Examples/TIM/6Steps/main.c
  • MemManage_Handler() : STM32F10x_StdPeriph_Examples/PWR/PVD/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2C/IOExpander/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2C/IOExpander/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2C/EEPROM/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2C/EEPROM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/GPIO/IOToggle/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/GPIO/IOToggle/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/SRAM/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/SRAM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/OneNAND/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/DMA/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/NOR/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/NOR/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/NAND/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/NAND/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FLASH/Program/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FLASH/Program/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/FSMC/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/FSMC/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CortexM3/MPU/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CortexM3/MPU/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CortexM3/BitBand/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CortexM3/BitBand/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/BKP/Tamper/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/BKP/Tamper/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/BKP/Backup_Data/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/BKP/Backup_Data/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/OCActive/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/OCActive/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/OnePulse/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/PWM_Output/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/PWM_Output/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/OneNAND/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/HalfDuplex/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/HalfDuplex/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Polling/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Printf/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_it.h , STM32F10x_StdPeriph_Template/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/MultiProcessor/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/RTC/Calendar/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/RTC/Calendar/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SDIO/uSDCard/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SDIO/uSDCard/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/CRC/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/DMA/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SysTick/TimeBase/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/6Steps/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/OCInactive/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/OnePulse/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/PWM_Input/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/DMA_Polling/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Polling/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Printf/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Synchronous/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Synchronous/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/CRC/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/6Steps/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/DMABurst/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/OCInactive/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/PWM_Input/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/DMA_Polling/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/MultiProcessor/stm32f10x_it.h , STM32F10x_StdPeriph_Template/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/PWR/STANDBY/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SysTick/TimeBase/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/DMABurst/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/PWR/STANDBY/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SPI/DMA/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/DMA/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/PWR/PVD/stm32f10x_it.h
  • MPU_SETUP() : STM32F10x_StdPeriph_Examples/CortexM3/MPU/main.c


STM32F10x Standard Peripherals Firmware Library: Globals

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- n -

  • NAND_AddressIncrement() : stm3210e_eval_fsmc_nand.c , stm3210e_eval_fsmc_nand.h
  • NAND_EraseBlock() : stm3210e_eval_fsmc_nand.h , stm3210e_eval_fsmc_nand.c
  • NAND_GetStatus() : stm3210e_eval_fsmc_nand.c , stm3210e_eval_fsmc_nand.h
  • NAND_Init() : stm3210e_eval_fsmc_nand.h , stm3210e_eval_fsmc_nand.c
  • NAND_ReadID() : stm3210e_eval_fsmc_nand.c , stm3210e_eval_fsmc_nand.h
  • NAND_ReadSmallPage() : stm3210e_eval_fsmc_nand.c , stm3210e_eval_fsmc_nand.h
  • NAND_ReadSpareArea() : stm3210e_eval_fsmc_nand.c , stm3210e_eval_fsmc_nand.h
  • NAND_ReadStatus() : stm3210e_eval_fsmc_nand.h , stm3210e_eval_fsmc_nand.c
  • NAND_Reset() : stm3210e_eval_fsmc_nand.c , stm3210e_eval_fsmc_nand.h
  • NAND_WriteSmallPage() : stm3210e_eval_fsmc_nand.c , stm3210e_eval_fsmc_nand.h
  • NAND_WriteSpareArea() : stm3210e_eval_fsmc_nand.c , stm3210e_eval_fsmc_nand.h
  • NMI_Handler() : STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/RTC/Calendar/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/RTC/Calendar/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SDIO/uSDCard/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/FSMC/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SDIO/uSDCard/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/CRC/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/FSMC/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/CRC/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/DMA/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SPI/DMA/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/BKP/Backup_Data/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/BKP/Backup_Data/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SysTick/TimeBase/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SysTick/TimeBase/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/6Steps/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/BKP/Tamper/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/6Steps/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f10x_it.c , STM32F10x_StdPeriph_Template/stm32f10x_it.h , STM32F10x_StdPeriph_Template/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Synchronous/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Synchronous/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/BKP/Tamper/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Printf/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Polling/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Polling/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/MultiProcessor/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/MultiProcessor/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/HalfDuplex/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/DMA_Polling/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/DMA_Polling/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FLASH/Program/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/PWM_Output/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/PWM_Input/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/PWM_Input/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/OnePulse/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/OnePulse/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/OCInactive/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/OCInactive/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/OCActive/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/OCActive/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/DMA/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FLASH/Program/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/DMA/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/DMABurst/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/DMABurst/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/NAND/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/NAND/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/NOR/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/NOR/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/PWM_Output/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/OneNAND/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/OneNAND/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/SRAM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/SRAM/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/PWR/STANDBY/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/PWR/STANDBY/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/PWR/PVD/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/PWR/PVD/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CortexM3/BitBand/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Printf/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2C/IOExpander/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2C/EEPROM/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2C/EEPROM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/GPIO/IOToggle/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CortexM3/BitBand/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/GPIO/IOToggle/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/HalfDuplex/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CortexM3/MPU/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CortexM3/MPU/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2C/IOExpander/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/stm32f10x_it.c
  • NOR_EraseBlock() : stm3210e_eval_fsmc_nor.h , stm3210e_eval_fsmc_nor.c
  • NOR_EraseChip() : stm3210e_eval_fsmc_nor.h , stm3210e_eval_fsmc_nor.c
  • NOR_GetStatus() : stm3210e_eval_fsmc_nor.c , stm3210e_eval_fsmc_nor.h
  • NOR_Init() : stm3210e_eval_fsmc_nor.h , stm3210e_eval_fsmc_nor.c
  • NOR_ProgramBuffer() : stm3210e_eval_fsmc_nor.h , stm3210e_eval_fsmc_nor.c
  • NOR_ReadBuffer() : stm3210e_eval_fsmc_nor.h , stm3210e_eval_fsmc_nor.c
  • NOR_ReadHalfWord() : stm3210e_eval_fsmc_nor.h , stm3210e_eval_fsmc_nor.c
  • NOR_ReadID() : stm3210e_eval_fsmc_nor.c , stm3210e_eval_fsmc_nor.h
  • NOR_Reset() : stm3210e_eval_fsmc_nor.c , stm3210e_eval_fsmc_nor.h
  • NOR_ReturnToReadMode() : stm3210e_eval_fsmc_nor.c , stm3210e_eval_fsmc_nor.h
  • NOR_WriteBuffer() : stm3210e_eval_fsmc_nor.c , stm3210e_eval_fsmc_nor.h
  • NOR_WriteHalfWord() : stm3210e_eval_fsmc_nor.h , stm3210e_eval_fsmc_nor.c
  • NVIC_Config() : STM32F10x_StdPeriph_Examples/CAN/Networking/main.c , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/main.c , STM32F10x_StdPeriph_Examples/CAN/DualCAN/main.c
  • NVIC_Configuration() : STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/main.c , STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/main.c , STM32F10x_StdPeriph_Examples/SDIO/uSDCard/main.c , STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/main.c , STM32F10x_StdPeriph_Examples/BKP/Tamper/main.c , STM32F10x_StdPeriph_Examples/TIM/OCInactive/main.c , STM32F10x_StdPeriph_Examples/CAN/LoopBack/main.c , STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c , STM32F10x_StdPeriph_Examples/TIM/PWM_Input/main.c , STM32F10x_StdPeriph_Examples/RTC/Calendar/main.c , STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/main.c , STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/main.c , STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/main.c , STM32F10x_StdPeriph_Examples/PWR/STOP/main.c , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/main.c , STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/main.c , STM32F10x_StdPeriph_Examples/TIM/InputCapture/main.c , STM32F10x_StdPeriph_Examples/USART/Smartcard/main.c , STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/main.c , STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/main.c , STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/main.c , STM32F10x_StdPeriph_Examples/TIM/TimeBase/main.c , STM32F10x_StdPeriph_Examples/PWR/PVD/main.c , STM32F10x_StdPeriph_Examples/TIM/6Steps/main.c , STM32F10x_StdPeriph_Examples/TIM/OCToggle/main.c , STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/main.c , STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c , STM32F10x_StdPeriph_Examples/I2S/Interrupt/main.c
  • NVIC_Init() : misc.c , misc.h
  • NVIC_PriorityGroupConfig() : misc.h , misc.c
  • NVIC_SetVectorTable() : misc.c , misc.h
  • NVIC_SystemLPConfig() : misc.c , misc.h


STM32F10x Standard Peripherals Firmware Library: Globals

  • File List
  • Globals
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- o -

  • OneNAND_AsynchronousRead() : stm32100e_eval_fsmc_onenand.c , stm32100e_eval_fsmc_onenand.h
  • OneNAND_EraseBlock() : stm32100e_eval_fsmc_onenand.h , stm32100e_eval_fsmc_onenand.c
  • OneNAND_Init() : stm32100e_eval_fsmc_onenand.c , stm32100e_eval_fsmc_onenand.h
  • OneNAND_ReadControllerStatus() : stm32100e_eval_fsmc_onenand.h , stm32100e_eval_fsmc_onenand.c
  • OneNAND_ReadID() : stm32100e_eval_fsmc_onenand.c , stm32100e_eval_fsmc_onenand.h
  • OneNAND_ReadStatus() : stm32100e_eval_fsmc_onenand.c , stm32100e_eval_fsmc_onenand.h
  • OneNAND_Reset() : stm32100e_eval_fsmc_onenand.c , stm32100e_eval_fsmc_onenand.h
  • OneNAND_SynchronousRead() : stm32100e_eval_fsmc_onenand.c , stm32100e_eval_fsmc_onenand.h
  • OneNAND_UnlockBlock() : stm32100e_eval_fsmc_onenand.h , stm32100e_eval_fsmc_onenand.c
  • OneNAND_WriteBuffer() : stm32100e_eval_fsmc_onenand.h , stm32100e_eval_fsmc_onenand.c


STM32F10x Standard Peripherals Firmware Library: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
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- b -

  • BKP_ClearFlag() : stm32f10x_bkp.h , stm32f10x_bkp.c
  • BKP_ClearITPendingBit() : stm32f10x_bkp.c , stm32f10x_bkp.h
  • BKP_DeInit() : stm32f10x_bkp.h , stm32f10x_bkp.c
  • BKP_GetFlagStatus() : stm32f10x_bkp.c , stm32f10x_bkp.h
  • BKP_GetITStatus() : stm32f10x_bkp.h , stm32f10x_bkp.c
  • BKP_ITConfig() : stm32f10x_bkp.h , stm32f10x_bkp.c
  • BKP_ReadBackupRegister() : stm32f10x_bkp.h , stm32f10x_bkp.c
  • BKP_RTCOutputConfig() : stm32f10x_bkp.c , stm32f10x_bkp.h
  • BKP_SetRTCCalibrationValue() : stm32f10x_bkp.h , stm32f10x_bkp.c
  • BKP_TamperPinCmd() : stm32f10x_bkp.h , stm32f10x_bkp.c
  • BKP_TamperPinLevelConfig() : stm32f10x_bkp.h , stm32f10x_bkp.c
  • BKP_WriteBackupRegister() : stm32f10x_bkp.h , stm32f10x_bkp.c
  • Buffercmp() : STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/main.c , STM32F10x_StdPeriph_Examples/SDIO/uSDCard/main.c , STM32F10x_StdPeriph_Examples/SPI/CRC/main.c , STM32F10x_StdPeriph_Examples/SPI/DMA/main.c , STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/main.c , STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/main.c , STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/main.c , STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/main.c , STM32F10x_StdPeriph_Examples/USART/DMA_Polling/main.c , STM32F10x_StdPeriph_Examples/USART/HalfDuplex/main.c , STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c , STM32F10x_StdPeriph_Examples/USART/Polling/main.c , STM32F10x_StdPeriph_Examples/USART/Synchronous/main.c , STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/main.c , STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/main.c , STM32F10x_StdPeriph_Examples/DMA/FSMC/main.c , STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/main.c , STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/main.c , STM32F10x_StdPeriph_Examples/I2C/EEPROM/main.c , STM32F10x_StdPeriph_Examples/I2S/Interrupt/main.c
  • Buffercmp16() : STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/main.c
  • Buffercmp24bits() : STM32F10x_StdPeriph_Examples/I2S/Interrupt/main.c
  • BusFault_Handler() : STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/OnePulse/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/OnePulse/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/OCInactive/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/OCInactive/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/OCActive/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/OCActive/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/DMABurst/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/DMABurst/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/DMA/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/DMA/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/6Steps/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/6Steps/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SysTick/TimeBase/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SysTick/TimeBase/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SPI/DMA/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/DMA/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SPI/CRC/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/CRC/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SDIO/uSDCard/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SDIO/uSDCard/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/RTC/Calendar/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/RTC/Calendar/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/PWR/STANDBY/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/PWR/STANDBY/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/PWR/PVD/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/PWR/PVD/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2C/IOExpander/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2C/IOExpander/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2C/EEPROM/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2C/EEPROM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/GPIO/IOToggle/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/GPIO/IOToggle/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/SRAM/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/SRAM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/OneNAND/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/OneNAND/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/NOR/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/NOR/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/NAND/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/NAND/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FLASH/Program/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FLASH/Program/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/FSMC/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/FSMC/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CortexM3/MPU/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CortexM3/MPU/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CortexM3/BitBand/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CortexM3/BitBand/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/BKP/Tamper/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/BKP/Tamper/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/BKP/Backup_Data/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/BKP/Backup_Data/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Printf/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/stm32f10x_it.c , STM32F10x_StdPeriph_Template/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/DMA_Polling/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/MultiProcessor/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Synchronous/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Printf/stm32f10x_it.c , STM32F10x_StdPeriph_Template/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Polling/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/MultiProcessor/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Synchronous/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Polling/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/DMA_Polling/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/HalfDuplex/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/PWM_Output/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/HalfDuplex/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/PWM_Output/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/PWM_Input/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/PWM_Input/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/stm32f10x_it.h


STM32F10x Standard Peripherals Firmware Library: Globals

  • File List
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- c -

  • CAN1_RX0_IRQHandler() : STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_it.h
  • CAN2_RX0_IRQHandler() : STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_it.c
  • CAN_CancelTransmit() : stm32f10x_can.h , stm32f10x_can.c
  • CAN_ClearFlag() : stm32f10x_can.c , stm32f10x_can.h
  • CAN_ClearITPendingBit() : stm32f10x_can.h , stm32f10x_can.c
  • CAN_Config() : STM32F10x_StdPeriph_Examples/CAN/DualCAN/main.c , STM32F10x_StdPeriph_Examples/CAN/Networking/main.c
  • CAN_DBGFreeze() : stm32f10x_can.h , stm32f10x_can.c
  • CAN_DeInit() : stm32f10x_can.c , stm32f10x_can.h
  • CAN_FIFORelease() : stm32f10x_can.h , stm32f10x_can.c
  • CAN_FilterInit() : stm32f10x_can.h , stm32f10x_can.c
  • CAN_GetFlagStatus() : stm32f10x_can.h , stm32f10x_can.c
  • CAN_GetITStatus() : stm32f10x_can.h , stm32f10x_can.c
  • CAN_GetLastErrorCode() : stm32f10x_can.h , stm32f10x_can.c
  • CAN_GetLSBTransmitErrorCounter() : stm32f10x_can.h , stm32f10x_can.c
  • CAN_GetReceiveErrorCounter() : stm32f10x_can.h , stm32f10x_can.c
  • CAN_Init() : stm32f10x_can.c , stm32f10x_can.h
  • CAN_Interrupt() : STM32F10x_StdPeriph_Examples/CAN/LoopBack/main.c
  • CAN_ITConfig() : stm32f10x_can.h , stm32f10x_can.c
  • CAN_MessagePending() : stm32f10x_can.h , stm32f10x_can.c
  • CAN_OperatingModeRequest() : stm32f10x_can.h , stm32f10x_can.c
  • CAN_Polling() : STM32F10x_StdPeriph_Examples/CAN/LoopBack/main.c
  • CAN_Receive() : stm32f10x_can.h , stm32f10x_can.c
  • CAN_SlaveStartBank() : stm32f10x_can.h , stm32f10x_can.c
  • CAN_Sleep() : stm32f10x_can.h , stm32f10x_can.c
  • CAN_StructInit() : stm32f10x_can.h , stm32f10x_can.c
  • CAN_Transmit() : stm32f10x_can.h , stm32f10x_can.c
  • CAN_TransmitStatus() : stm32f10x_can.h , stm32f10x_can.c
  • CAN_TTComModeCmd() : stm32f10x_can.h , stm32f10x_can.c
  • CAN_WakeUp() : stm32f10x_can.h , stm32f10x_can.c
  • CEC_ClearFlag() : stm32f10x_cec.h , stm32f10x_cec.c
  • CEC_ClearITPendingBit() : stm32f10x_cec.h , stm32f10x_cec.c
  • CEC_Cmd() : stm32f10x_cec.h , stm32f10x_cec.c
  • CEC_DeInit() : stm32f10x_cec.c , stm32f10x_cec.h
  • CEC_EndOfMessageCmd() : stm32f10x_cec.h , stm32f10x_cec.c
  • CEC_GetFlagStatus() : stm32f10x_cec.h , stm32f10x_cec.c
  • CEC_GetITStatus() : stm32f10x_cec.h , stm32f10x_cec.c
  • CEC_Init() : stm32f10x_cec.c , stm32f10x_cec.h
  • CEC_IRQHandler() : STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.h
  • CEC_ITConfig() : stm32f10x_cec.h , stm32f10x_cec.c
  • CEC_OwnAddressConfig() : stm32f10x_cec.c , stm32f10x_cec.h
  • CEC_ReceiveDataByte() : stm32f10x_cec.c , stm32f10x_cec.h
  • CEC_SendDataByte() : stm32f10x_cec.c , stm32f10x_cec.h
  • CEC_SetPrescaler() : stm32f10x_cec.c , stm32f10x_cec.h
  • CEC_StartOfMessage() : stm32f10x_cec.h , stm32f10x_cec.c
  • CheckBackupReg() : STM32F10x_StdPeriph_Examples/BKP/Tamper/main.c , STM32F10x_StdPeriph_Examples/BKP/Backup_Data/main.c
  • CheckITStatus() : stm32f10x_can.c
  • CmdError() : stm32_eval_sdio_sd.c
  • CmdResp1Error() : stm32_eval_sdio_sd.c
  • CmdResp2Error() : stm32_eval_sdio_sd.c
  • CmdResp3Error() : stm32_eval_sdio_sd.c
  • CmdResp6Error() : stm32_eval_sdio_sd.c
  • CmdResp7Error() : stm32_eval_sdio_sd.c
  • Convert() : stm32l152_eval_glass_lcd.c
  • convert_from_bytes_to_power_of_two() : stm32_eval_sdio_sd.c
  • CRC_CalcBlockCRC() : stm32f10x_crc.h , stm32f10x_crc.c
  • CRC_CalcCRC() : stm32f10x_crc.h , stm32f10x_crc.c
  • CRC_GetCRC() : stm32f10x_crc.h , stm32f10x_crc.c
  • CRC_GetIDRegister() : stm32f10x_crc.h , stm32f10x_crc.c
  • CRC_ResetDR() : stm32f10x_crc.c , stm32f10x_crc.h
  • CRC_SetIDRegister() : stm32f10x_crc.c , stm32f10x_crc.h


STM32F10x Standard Peripherals Firmware Library: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
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  • r
  • s
  • t
  • u
  • w

- d -

  • DAC_Cmd() : stm32f10x_dac.h , stm32f10x_dac.c
  • DAC_DeInit() : stm32f10x_dac.c , stm32f10x_dac.h
  • DAC_DMACmd() : stm32f10x_dac.h , stm32f10x_dac.c
  • DAC_DualSoftwareTriggerCmd() : stm32f10x_dac.c , stm32f10x_dac.h
  • DAC_GetDataOutputValue() : stm32f10x_dac.h , stm32f10x_dac.c
  • DAC_Init() : stm32f10x_dac.h , stm32f10x_dac.c
  • DAC_SetChannel1Data() : stm32f10x_dac.h , stm32f10x_dac.c
  • DAC_SetChannel2Data() : stm32f10x_dac.c , stm32f10x_dac.h
  • DAC_SetDualChannelData() : stm32f10x_dac.h , stm32f10x_dac.c
  • DAC_SoftwareTriggerCmd() : stm32f10x_dac.h , stm32f10x_dac.c
  • DAC_StructInit() : stm32f10x_dac.h , stm32f10x_dac.c
  • DAC_WaveGenerationCmd() : stm32f10x_dac.h , stm32f10x_dac.c
  • DBGMCU_Config() : stm32f10x_dbgmcu.h , stm32f10x_dbgmcu.c
  • DBGMCU_GetDEVID() : stm32f10x_dbgmcu.h , stm32f10x_dbgmcu.c
  • DBGMCU_GetREVID() : stm32f10x_dbgmcu.h , stm32f10x_dbgmcu.c
  • debug() : stm32f10x_ip_dbg.h , stm32f10x_ip_dbg.c
  • DebugMon_Handler() : STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/PWR/PVD/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/PWR/PVD/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/PWR/STANDBY/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/PWR/STANDBY/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/RTC/Calendar/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/RTC/Calendar/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SDIO/uSDCard/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/stm32f10x_it.h , STM32F10x_StdPeriph_Template/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SDIO/uSDCard/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/CRC/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Synchronous/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Synchronous/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Printf/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Printf/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Polling/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/MultiProcessor/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/MultiProcessor/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/CRC/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/DMA/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/HalfDuplex/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/HalfDuplex/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/DMA_Polling/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/DMA/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/PWM_Output/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/PWM_Output/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/PWM_Input/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/OnePulse/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/OnePulse/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/OCInactive/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/OCActive/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/OCActive/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/DMABurst/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/DMA/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/DMA/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/6Steps/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/6Steps/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SysTick/TimeBase/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/FSMC/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SysTick/TimeBase/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/FSMC/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/DMABurst/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FLASH/Program/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FLASH/Program/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/OCInactive/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/BKP/Backup_Data/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/NAND/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/BKP/Backup_Data/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/NAND/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2C/IOExpander/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2C/IOExpander/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/PWM_Input/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2C/EEPROM/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2C/EEPROM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Polling/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/GPIO/IOToggle/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/GPIO/IOToggle/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/SRAM/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/SRAM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/DMA_Polling/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/OneNAND/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/NOR/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/BKP/Tamper/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/NOR/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/BKP/Tamper/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/OneNAND/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_it.h , STM32F10x_StdPeriph_Template/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CortexM3/BitBand/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CortexM3/BitBand/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CortexM3/MPU/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CortexM3/MPU/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/stm32f10x_it.c
  • Delay() : STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/main.c
  • delay() : stm32100b_eval_lcd.c , stm32l152_eval_lcd.c , stm32100e_eval_ioe.c , stm3210c_eval_lcd.c
  • Delay() : STM32F10x_StdPeriph_Examples/USART/MultiProcessor/main.c , STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/main.c , STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/main.c , STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/main.c , STM32F10x_StdPeriph_Examples/CAN/DualCAN/main.c , STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/main.c , STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/main.c , STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/main.c , STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/main.c , STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/main.c
  • delay() : stm32100e_eval_lcd.c , stm32l152_eval_glass_lcd.c
  • Delay() : STM32F10x_StdPeriph_Examples/SysTick/TimeBase/main.c , STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/main.c
  • delay() : stm3210e_eval_lcd.c , stm3210b_eval_lcd.c
  • Delay() : STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/main.c , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/main.c , STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/main.c , STM32F10x_StdPeriph_Examples/CAN/Networking/main.c , STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/main.c , STM32F10x_StdPeriph_Examples/PWR/STOP/main.c
  • delay() : stm3210c_eval_ioe.c
  • DMA1_Channel5_IRQHandler() : STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_it.c
  • DMA1_Channel6_IRQHandler() : STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_it.c
  • DMA_ClearFlag() : stm32f10x_dma.h , stm32f10x_dma.c
  • DMA_ClearITPendingBit() : stm32f10x_dma.c , stm32f10x_dma.h
  • DMA_Cmd() : stm32f10x_dma.c , stm32f10x_dma.h
  • DMA_Configuration() : STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/main.c , STM32F10x_StdPeriph_Examples/USART/DMA_Polling/main.c , STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/main.c , STM32F10x_StdPeriph_Examples/TIM/DMA/main.c
  • DMA_DeInit() : stm32f10x_dma.c , stm32f10x_dma.h
  • DMA_GetCurrDataCounter() : stm32f10x_dma.c , stm32f10x_dma.h
  • DMA_GetFlagStatus() : stm32f10x_dma.c , stm32f10x_dma.h
  • DMA_GetITStatus() : stm32f10x_dma.h , stm32f10x_dma.c
  • DMA_Init() : stm32f10x_dma.h , stm32f10x_dma.c
  • DMA_ITConfig() : stm32f10x_dma.c , stm32f10x_dma.h
  • DMA_SetCurrDataCounter() : stm32f10x_dma.h , stm32f10x_dma.c
  • DMA_StructInit() : stm32f10x_dma.c , stm32f10x_dma.h


STM32F10x Standard Peripherals Firmware Library: Globals

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- e -

  • eBuffercmp() : STM32F10x_StdPeriph_Examples/SDIO/uSDCard/main.c
  • EXTI0_Config() : STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/main.c
  • EXTI0_IRQHandler() : STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/MultiProcessor/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/MultiProcessor/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_it.c
  • EXTI15_10_IRQHandler() : STM32F10x_StdPeriph_Examples/I2C/IOExpander/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2C/IOExpander/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_it.h
  • EXTI9_5_Config() : STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/main.c
  • EXTI9_5_IRQHandler() : STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/MultiProcessor/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/PWR/STANDBY/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/PWR/STANDBY/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/MultiProcessor/stm32f10x_it.c
  • EXTI_ClearFlag() : stm32f10x_exti.h , stm32f10x_exti.c
  • EXTI_ClearITPendingBit() : stm32f10x_exti.h , stm32f10x_exti.c
  • EXTI_Configuration() : STM32F10x_StdPeriph_Examples/PWR/STOP/main.c , STM32F10x_StdPeriph_Examples/USART/Smartcard/main.c , STM32F10x_StdPeriph_Examples/PWR/PVD/main.c , STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/main.c
  • EXTI_DeInit() : stm32f10x_exti.h , stm32f10x_exti.c
  • EXTI_GenerateSWInterrupt() : stm32f10x_exti.h , stm32f10x_exti.c
  • EXTI_GetFlagStatus() : stm32f10x_exti.h , stm32f10x_exti.c
  • EXTI_GetITStatus() : stm32f10x_exti.c , stm32f10x_exti.h
  • EXTI_Init() : stm32f10x_exti.c , stm32f10x_exti.h
  • EXTI_StructInit() : stm32f10x_exti.c , stm32f10x_exti.h


STM32F10x Standard Peripherals Firmware Library: Globals

  • File List
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- f -

  • Fill_Buffer() : STM32F10x_StdPeriph_Examples/FSMC/NAND/main.c , STM32F10x_StdPeriph_Examples/FSMC/NOR/main.c , STM32F10x_StdPeriph_Examples/SDIO/uSDCard/main.c , STM32F10x_StdPeriph_Examples/FSMC/SRAM/main.c
  • Fill_hBuffer() : STM32F10x_StdPeriph_Examples/FSMC/OneNAND/main.c
  • FindSCR() : stm32_eval_sdio_sd.c
  • FLASH_ClearFlag() : stm32f10x_flash.c , stm32f10x_flash.h
  • FLASH_EnableWriteProtection() : stm32f10x_flash.h , stm32f10x_flash.c
  • FLASH_EraseAllBank1Pages() : stm32f10x_flash.h , stm32f10x_flash.c
  • FLASH_EraseAllPages() : stm32f10x_flash.h , stm32f10x_flash.c
  • FLASH_EraseOptionBytes() : stm32f10x_flash.c , stm32f10x_flash.h
  • FLASH_ErasePage() : stm32f10x_flash.h , stm32f10x_flash.c
  • FLASH_GetBank1Status() : stm32f10x_flash.h , stm32f10x_flash.c
  • FLASH_GetFlagStatus() : stm32f10x_flash.h , stm32f10x_flash.c
  • FLASH_GetPrefetchBufferStatus() : stm32f10x_flash.h , stm32f10x_flash.c
  • FLASH_GetReadOutProtectionStatus() : stm32f10x_flash.h , stm32f10x_flash.c
  • FLASH_GetStatus() : stm32f10x_flash.h , stm32f10x_flash.c
  • FLASH_GetUserOptionByte() : stm32f10x_flash.h , stm32f10x_flash.c
  • FLASH_GetWriteProtectionOptionByte() : stm32f10x_flash.c , stm32f10x_flash.h
  • FLASH_HalfCycleAccessCmd() : stm32f10x_flash.h , stm32f10x_flash.c
  • FLASH_ITConfig() : stm32f10x_flash.h , stm32f10x_flash.c
  • FLASH_Lock() : stm32f10x_flash.h , stm32f10x_flash.c
  • FLASH_LockBank1() : stm32f10x_flash.h , stm32f10x_flash.c
  • FLASH_PrefetchBufferCmd() : stm32f10x_flash.h , stm32f10x_flash.c
  • FLASH_ProgramHalfWord() : stm32f10x_flash.h , stm32f10x_flash.c
  • FLASH_ProgramOptionByteData() : stm32f10x_flash.h , stm32f10x_flash.c
  • FLASH_ProgramWord() : stm32f10x_flash.h , stm32f10x_flash.c
  • FLASH_ReadOutProtection() : stm32f10x_flash.h , stm32f10x_flash.c
  • FLASH_SetLatency() : stm32f10x_flash.h , stm32f10x_flash.c
  • FLASH_Unlock() : stm32f10x_flash.h , stm32f10x_flash.c
  • FLASH_UnlockBank1() : stm32f10x_flash.h , stm32f10x_flash.c
  • FLASH_UserOptionByteConfig() : stm32f10x_flash.h , stm32f10x_flash.c
  • FLASH_WaitForLastBank1Operation() : stm32f10x_flash.h , stm32f10x_flash.c
  • FLASH_WaitForLastOperation() : stm32f10x_flash.h , stm32f10x_flash.c
  • FSMC_ClearFlag() : stm32f10x_fsmc.c , stm32f10x_fsmc.h
  • FSMC_ClearITPendingBit() : stm32f10x_fsmc.h , stm32f10x_fsmc.c
  • FSMC_GetECC() : stm32f10x_fsmc.c , stm32f10x_fsmc.h
  • FSMC_GetFlagStatus() : stm32f10x_fsmc.h , stm32f10x_fsmc.c
  • FSMC_GetITStatus() : stm32f10x_fsmc.h , stm32f10x_fsmc.c
  • FSMC_ITConfig() : stm32f10x_fsmc.c , stm32f10x_fsmc.h
  • FSMC_NANDCmd() : stm32f10x_fsmc.c , stm32f10x_fsmc.h
  • FSMC_NANDDeInit() : stm32f10x_fsmc.h , stm32f10x_fsmc.c
  • FSMC_NANDECCCmd() : stm32f10x_fsmc.c , stm32f10x_fsmc.h
  • FSMC_NANDInit() : stm32f10x_fsmc.h , stm32f10x_fsmc.c
  • FSMC_NANDStructInit() : stm32f10x_fsmc.c , stm32f10x_fsmc.h
  • FSMC_NORSRAMCmd() : stm32f10x_fsmc.h , stm32f10x_fsmc.c
  • FSMC_NORSRAMDeInit() : stm32f10x_fsmc.h , stm32f10x_fsmc.c
  • FSMC_NORSRAMInit() : stm32f10x_fsmc.c , stm32f10x_fsmc.h
  • FSMC_NORSRAMStructInit() : stm32f10x_fsmc.c , stm32f10x_fsmc.h
  • FSMC_PCCARDCmd() : stm32f10x_fsmc.h , stm32f10x_fsmc.c
  • FSMC_PCCARDDeInit() : stm32f10x_fsmc.h , stm32f10x_fsmc.c
  • FSMC_PCCARDInit() : stm32f10x_fsmc.h , stm32f10x_fsmc.c
  • FSMC_PCCARDStructInit() : stm32f10x_fsmc.c , stm32f10x_fsmc.h


STM32F10x Standard Peripherals Firmware Library: Globals

  • File List
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- g -

  • GetVar_OperationComplete() : STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/main.c , RTC/LSI_Calib/main.h
  • GPIO_AFIODeInit() : stm32f10x_gpio.c , stm32f10x_gpio.h
  • GPIO_Configuration() : STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/main.c , STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/main.c , STM32F10x_StdPeriph_Examples/TIM/InputCapture/main.c , STM32F10x_StdPeriph_Examples/TIM/OCActive/main.c , STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/main.c , STM32F10x_StdPeriph_Examples/TIM/OCInactive/main.c , STM32F10x_StdPeriph_Examples/TIM/OCToggle/main.c , STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/main.c , STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/main.c , STM32F10x_StdPeriph_Examples/TIM/OnePulse/main.c , STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/main.c , STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/main.c , STM32F10x_StdPeriph_Examples/TIM/PWM_Input/main.c , STM32F10x_StdPeriph_Examples/TIM/PWM_Output/main.c , STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c , STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/main.c , STM32F10x_StdPeriph_Examples/I2S/Interrupt/main.c , STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/main.c , STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/main.c , STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/main.c , STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/main.c , STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/main.c , STM32F10x_StdPeriph_Examples/BKP/Tamper/main.c , STM32F10x_StdPeriph_Examples/SPI/CRC/main.c , STM32F10x_StdPeriph_Examples/TIM/TimeBase/main.c , STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/main.c , STM32F10x_StdPeriph_Examples/SPI/DMA/main.c , STM32F10x_StdPeriph_Examples/USART/DMA_Polling/main.c , STM32F10x_StdPeriph_Examples/USART/HalfDuplex/main.c , STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/main.c , STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/main.c , STM32F10x_StdPeriph_Examples/USART/Synchronous/main.c , STM32F10x_StdPeriph_Examples/USART/Smartcard/main.c , STM32F10x_StdPeriph_Examples/USART/Polling/main.c , STM32F10x_StdPeriph_Examples/USART/MultiProcessor/main.c , STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/main.c , STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/main.c , STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/main.c , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/main.c , STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c , STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/main.c , STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/main.c , STM32F10x_StdPeriph_Examples/TIM/6Steps/main.c , STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/main.c , STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/main.c , STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/main.c , STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/main.c , STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/main.c , STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/main.c , STM32F10x_StdPeriph_Examples/TIM/DMA/main.c , STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/main.c
  • GPIO_DeInit() : stm32f10x_gpio.h , stm32f10x_gpio.c
  • GPIO_ETH_MediaInterfaceConfig() : stm32f10x_gpio.h , stm32f10x_gpio.c
  • GPIO_EventOutputCmd() : stm32f10x_gpio.h , stm32f10x_gpio.c
  • GPIO_EventOutputConfig() : stm32f10x_gpio.h , stm32f10x_gpio.c
  • GPIO_EXTILineConfig() : stm32f10x_gpio.h , stm32f10x_gpio.c
  • GPIO_Init() : stm32f10x_gpio.h , stm32f10x_gpio.c
  • GPIO_PinLockConfig() : stm32f10x_gpio.h , stm32f10x_gpio.c
  • GPIO_PinRemapConfig() : stm32f10x_gpio.c , stm32f10x_gpio.h
  • GPIO_ReadInputData() : stm32f10x_gpio.h , stm32f10x_gpio.c
  • GPIO_ReadInputDataBit() : stm32f10x_gpio.c , stm32f10x_gpio.h
  • GPIO_ReadOutputData() : stm32f10x_gpio.h , stm32f10x_gpio.c
  • GPIO_ReadOutputDataBit() : stm32f10x_gpio.c , stm32f10x_gpio.h
  • GPIO_ResetBits() : stm32f10x_gpio.h , stm32f10x_gpio.c
  • GPIO_SetBits() : stm32f10x_gpio.c , stm32f10x_gpio.h
  • GPIO_StructInit() : stm32f10x_gpio.h , stm32f10x_gpio.c
  • GPIO_Write() : stm32f10x_gpio.h , stm32f10x_gpio.c
  • GPIO_WriteBit() : stm32f10x_gpio.h , stm32f10x_gpio.c


STM32F10x Standard Peripherals Firmware Library: Globals

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- h -

  • HardFault_Handler() : STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/BKP/Tamper/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/DMA/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/OneNAND/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/DMA/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/DMABurst/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/OneNAND/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/DMABurst/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/SRAM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/SRAM/stm32f10x_it.h , STM32F10x_StdPeriph_Template/stm32f10x_it.h , STM32F10x_StdPeriph_Template/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Synchronous/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Synchronous/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Printf/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Printf/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Polling/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Polling/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/MultiProcessor/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/MultiProcessor/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/HalfDuplex/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/HalfDuplex/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/DMA_Polling/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/DMA_Polling/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/PWM_Output/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/PWM_Output/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/PWM_Input/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/PWM_Input/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/OnePulse/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/OnePulse/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/OCInactive/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/OCActive/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/OCActive/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/OCInactive/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/GPIO/IOToggle/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/GPIO/IOToggle/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/6Steps/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/6Steps/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SysTick/TimeBase/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SysTick/TimeBase/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SPI/DMA/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/DMA/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SPI/CRC/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/CRC/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SDIO/uSDCard/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SDIO/uSDCard/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/RTC/Calendar/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/RTC/Calendar/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/PWR/STANDBY/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/PWR/STANDBY/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/PWR/PVD/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/PWR/PVD/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2C/IOExpander/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2C/IOExpander/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2C/EEPROM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2C/EEPROM/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/FSMC/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/NOR/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/NOR/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/NAND/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/NAND/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FLASH/Program/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FLASH/Program/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/FSMC/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CortexM3/BitBand/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/BKP/Backup_Data/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CortexM3/BitBand/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/BKP/Backup_Data/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CortexM3/MPU/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/BKP/Tamper/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CortexM3/MPU/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/stm32f10x_it.c
  • HDMI_CEC_CheckConnectedDevices() : stm32100e_eval_cec.c , stm32100b_eval_cec.h , stm32100e_eval_cec.h , stm32100b_eval_cec.c
  • HDMI_CEC_CommandCallBack() : stm32100b_eval_cec.h , stm32100b_eval_cec.c , stm32100e_eval_cec.h , stm32100e_eval_cec.c
  • HDMI_CEC_GetErrorStatus() : stm32100b_eval_cec.h , stm32100e_eval_cec.c , stm32100e_eval_cec.h , stm32100b_eval_cec.c
  • HDMI_CEC_Init() : stm32100b_eval_cec.h , stm32100b_eval_cec.c , stm32100e_eval_cec.h , stm32100e_eval_cec.c
  • HDMI_CEC_ProcessIRQSrc() : stm32100b_eval_cec.c , stm32100e_eval_cec.h , stm32100b_eval_cec.h , stm32100e_eval_cec.c
  • HDMI_CEC_ReportPhysicalAddress() : stm32100e_eval_cec.c , stm32100b_eval_cec.h , stm32100b_eval_cec.c , stm32100e_eval_cec.h
  • HDMI_CEC_TransmitMessage() : stm32100b_eval_cec.c , stm32100e_eval_cec.c , stm32100b_eval_cec.h , stm32100e_eval_cec.h


STM32F10x Standard Peripherals Firmware Library: Globals

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- i -

  • I2C1_ER_IRQHandler() : STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/stm32f10x_it.c
  • I2C_AcknowledgeConfig() : stm32f10x_i2c.h , stm32f10x_i2c.c
  • I2C_ARPCmd() : stm32f10x_i2c.h , stm32f10x_i2c.c
  • I2C_CalculatePEC() : stm32f10x_i2c.h , stm32f10x_i2c.c
  • I2C_CheckEvent() : stm32f10x_i2c.h , stm32f10x_i2c.c
  • I2C_ClearFlag() : stm32f10x_i2c.h , stm32f10x_i2c.c
  • I2C_ClearITPendingBit() : stm32f10x_i2c.h , stm32f10x_i2c.c
  • I2C_Cmd() : stm32f10x_i2c.h , stm32f10x_i2c.c
  • I2C_DeInit() : stm32f10x_i2c.h , stm32f10x_i2c.c
  • I2C_DMACmd() : stm32f10x_i2c.h , stm32f10x_i2c.c
  • I2C_DMALastTransferCmd() : stm32f10x_i2c.h , stm32f10x_i2c.c
  • I2C_DualAddressCmd() : stm32f10x_i2c.h , stm32f10x_i2c.c
  • I2C_FastModeDutyCycleConfig() : stm32f10x_i2c.h , stm32f10x_i2c.c
  • I2C_GeneralCallCmd() : stm32f10x_i2c.h , stm32f10x_i2c.c
  • I2C_GenerateSTART() : stm32f10x_i2c.h , stm32f10x_i2c.c
  • I2C_GenerateSTOP() : stm32f10x_i2c.h , stm32f10x_i2c.c
  • I2C_GetFlagStatus() : stm32f10x_i2c.h , stm32f10x_i2c.c
  • I2C_GetITStatus() : stm32f10x_i2c.h , stm32f10x_i2c.c
  • I2C_GetLastEvent() : stm32f10x_i2c.h , stm32f10x_i2c.c
  • I2C_GetPEC() : stm32f10x_i2c.h , stm32f10x_i2c.c
  • I2C_Init() : stm32f10x_i2c.h , stm32f10x_i2c.c
  • I2C_ITConfig() : stm32f10x_i2c.h , stm32f10x_i2c.c
  • I2C_NACKPositionConfig() : stm32f10x_i2c.h , stm32f10x_i2c.c
  • I2C_OwnAddress2Config() : stm32f10x_i2c.h , stm32f10x_i2c.c
  • I2C_PECPositionConfig() : stm32f10x_i2c.h , stm32f10x_i2c.c
  • I2C_ReadDataBuffer() : stm32100e_eval_ioe.c , stm32100e_eval_ioe.h , stm3210c_eval_ioe.c , stm3210c_eval_ioe.h
  • I2C_ReadDeviceRegister() : stm32100e_eval_ioe.c , stm32100e_eval_ioe.h , stm3210c_eval_ioe.c , stm3210c_eval_ioe.h
  • I2C_ReadRegister() : stm32f10x_i2c.h , stm32f10x_i2c.c
  • I2C_ReceiveData() : stm32f10x_i2c.h , stm32f10x_i2c.c
  • I2C_Send7bitAddress() : stm32f10x_i2c.h , stm32f10x_i2c.c
  • I2C_SendData() : stm32f10x_i2c.h , stm32f10x_i2c.c
  • I2C_SMBusAlertConfig() : stm32f10x_i2c.h , stm32f10x_i2c.c
  • I2C_SoftwareResetCmd() : stm32f10x_i2c.h , stm32f10x_i2c.c
  • I2C_StretchClockCmd() : stm32f10x_i2c.h , stm32f10x_i2c.c
  • I2C_StructInit() : stm32f10x_i2c.h , stm32f10x_i2c.c
  • I2C_TransmitPEC() : stm32f10x_i2c.h , stm32f10x_i2c.c
  • I2C_WriteDeviceRegister() : stm32100e_eval_ioe.c , stm32100e_eval_ioe.h , stm3210c_eval_ioe.c , stm3210c_eval_ioe.h
  • I2S_Cmd() : stm32f10x_spi.h , stm32f10x_spi.c
  • I2S_Init() : stm32f10x_spi.h , stm32f10x_spi.c
  • I2S_StructInit() : stm32f10x_spi.h , stm32f10x_spi.c
  • IncrementVar_OperationComplete() : STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/main.c , RTC/LSI_Calib/main.h
  • Init_RxMes() : STM32F10x_StdPeriph_Examples/CAN/DualCAN/main.c , STM32F10x_StdPeriph_Examples/CAN/Networking/main.c
  • IOE_ClearGITPending() : stm32100e_eval_ioe.c , stm32100e_eval_ioe.h , stm3210c_eval_ioe.c , stm3210c_eval_ioe.h
  • IOE_ClearIOITPending() : stm32100e_eval_ioe.c , stm32100e_eval_ioe.h , stm3210c_eval_ioe.c , stm3210c_eval_ioe.h
  • IOE_Config() : stm32100e_eval_ioe.c , stm32100e_eval_ioe.h , stm3210c_eval_ioe.c , stm3210c_eval_ioe.h
  • IOE_DMA_Config() : stm32100e_eval_ioe.c , stm3210c_eval_ioe.c
  • IOE_EXTI_Config() : stm32100e_eval_ioe.c , stm3210c_eval_ioe.c
  • IOE_FnctCmd() : stm32100e_eval_ioe.c , stm32100e_eval_ioe.h , stm3210c_eval_ioe.c , stm3210c_eval_ioe.h
  • IOE_GetGITStatus() : stm32100e_eval_ioe.h , stm32100e_eval_ioe.c , stm3210c_eval_ioe.c , stm3210c_eval_ioe.h
  • IOE_GetIOITStatus() : stm32100e_eval_ioe.c , stm32100e_eval_ioe.h , stm3210c_eval_ioe.c , stm3210c_eval_ioe.h
  • IOE_GITCmd() : stm32100e_eval_ioe.h , stm32100e_eval_ioe.c , stm3210c_eval_ioe.c , stm3210c_eval_ioe.h
  • IOE_GITConfig() : stm32100e_eval_ioe.h , stm32100e_eval_ioe.c , stm3210c_eval_ioe.c , stm3210c_eval_ioe.h
  • IOE_GPIO_Config() : stm3210c_eval_ioe.c , stm32100e_eval_ioe.c
  • IOE_I2C_Config() : stm32100e_eval_ioe.c , stm3210c_eval_ioe.c
  • IOE_IOAFConfig() : stm32100e_eval_ioe.c , stm32100e_eval_ioe.h , stm3210c_eval_ioe.c , stm3210c_eval_ioe.h
  • IOE_IOEdgeConfig() : stm32100e_eval_ioe.c , stm3210c_eval_ioe.c , stm3210c_eval_ioe.h , stm32100e_eval_ioe.h
  • IOE_IOITConfig() : stm32100e_eval_ioe.c , stm3210c_eval_ioe.c , stm3210c_eval_ioe.h , stm32100e_eval_ioe.h
  • IOE_IOPinConfig() : stm32100e_eval_ioe.c , stm3210c_eval_ioe.c , stm3210c_eval_ioe.h , stm32100e_eval_ioe.h
  • IOE_IsOperational() : stm3210c_eval_ioe.c , stm3210c_eval_ioe.h , stm32100e_eval_ioe.c , stm32100e_eval_ioe.h
  • IOE_ITConfig() : stm32100e_eval_ioe.c , stm3210c_eval_ioe.c , stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_ITOutConfig() : stm32100e_eval_ioe.c , stm3210c_eval_ioe.c , stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_JoyStickGetState() : stm3210c_eval_ioe.h , stm3210c_eval_ioe.c
  • IOE_ReadID() : stm32100e_eval_ioe.c , stm32100e_eval_ioe.h , stm3210c_eval_ioe.c , stm3210c_eval_ioe.h
  • IOE_ReadIOPin() : stm3210c_eval_ioe.c , stm32100e_eval_ioe.c , stm3210c_eval_ioe.h , stm32100e_eval_ioe.h
  • IOE_Reset() : stm3210c_eval_ioe.c , stm32100e_eval_ioe.c , stm32100e_eval_ioe.h , stm3210c_eval_ioe.h
  • IOE_TempSens_Config() : stm3210c_eval_ioe.h , stm32100e_eval_ioe.c , stm3210c_eval_ioe.c , stm32100e_eval_ioe.h
  • IOE_TempSens_GetData() : stm32100e_eval_ioe.c , stm32100e_eval_ioe.h , stm3210c_eval_ioe.h , stm3210c_eval_ioe.c
  • IOE_TS_Config() : stm32100e_eval_ioe.h , stm3210c_eval_ioe.c , stm32100e_eval_ioe.c , stm3210c_eval_ioe.h
  • IOE_TS_GetState() : stm32100e_eval_ioe.c , stm3210c_eval_ioe.h , stm3210c_eval_ioe.c , stm32100e_eval_ioe.h
  • IOE_TS_Read_X() : stm32100e_eval_ioe.c , stm3210c_eval_ioe.c
  • IOE_TS_Read_Y() : stm3210c_eval_ioe.c , stm32100e_eval_ioe.c
  • IOE_TS_Read_Z() : stm3210c_eval_ioe.c , stm32100e_eval_ioe.c
  • IOE_WriteIOPin() : stm32100e_eval_ioe.h , stm3210c_eval_ioe.h , stm32100e_eval_ioe.c , stm3210c_eval_ioe.c
  • IsBackupRegReset() : STM32F10x_StdPeriph_Examples/BKP/Tamper/main.c , BKP/Tamper/main.h
  • IsCardProgramming() : stm32_eval_sdio_sd.c
  • IWDG_Enable() : stm32f10x_iwdg.c , stm32f10x_iwdg.h
  • IWDG_GetFlagStatus() : stm32f10x_iwdg.c , stm32f10x_iwdg.h
  • IWDG_ReloadCounter() : stm32f10x_iwdg.h , stm32f10x_iwdg.c
  • IWDG_SetPrescaler() : stm32f10x_iwdg.h , stm32f10x_iwdg.c
  • IWDG_SetReload() : stm32f10x_iwdg.h , stm32f10x_iwdg.c
  • IWDG_WriteAccessCmd() : stm32f10x_iwdg.c , stm32f10x_iwdg.h


STM32F10x Standard Peripherals Firmware Library: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
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  • d
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  • f
  • g
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- p -

  • PendSV_Handler() : STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/BKP/Tamper/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/DMA/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/OneNAND/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/DMA/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/DMABurst/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/OneNAND/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/DMABurst/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/SRAM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/SRAM/stm32f10x_it.h , STM32F10x_StdPeriph_Template/stm32f10x_it.h , STM32F10x_StdPeriph_Template/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Synchronous/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Synchronous/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Printf/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Printf/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Polling/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Polling/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/MultiProcessor/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/MultiProcessor/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/HalfDuplex/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/HalfDuplex/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/DMA_Polling/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/DMA_Polling/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/PWM_Output/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/PWM_Output/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/PWM_Input/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/PWM_Input/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/OnePulse/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/OnePulse/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/OCInactive/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/OCActive/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/OCActive/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/OCInactive/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/GPIO/IOToggle/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/GPIO/IOToggle/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/6Steps/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/6Steps/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SysTick/TimeBase/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SysTick/TimeBase/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SPI/DMA/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/DMA/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SPI/CRC/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/CRC/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SDIO/uSDCard/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SDIO/uSDCard/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/RTC/Calendar/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/RTC/Calendar/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/PWR/STANDBY/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/PWR/STANDBY/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/PWR/PVD/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/PWR/PVD/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2C/IOExpander/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2C/IOExpander/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2C/EEPROM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2C/EEPROM/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/FSMC/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/NOR/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/NOR/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/NAND/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/NAND/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FLASH/Program/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FLASH/Program/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/FSMC/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CortexM3/BitBand/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/BKP/Backup_Data/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CortexM3/BitBand/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/BKP/Backup_Data/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CortexM3/MPU/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/BKP/Tamper/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CortexM3/MPU/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/stm32f10x_it.c
  • PhysicalAddressDiscovery() : stm32100e_eval_cec.c , stm32100b_eval_cec.c
  • PutPixel() : stm3210e_eval_lcd.c , stm32l152_eval_lcd.c , stm3210c_eval_lcd.c , stm32100e_eval_lcd.c , stm32100b_eval_lcd.c , stm3210b_eval_lcd.c
  • PVD_IRQHandler() : STM32F10x_StdPeriph_Examples/PWR/PVD/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/PWR/PVD/stm32f10x_it.c
  • PWR_BackupAccessCmd() : stm32f10x_pwr.h , stm32f10x_pwr.c
  • PWR_ClearFlag() : stm32f10x_pwr.c , stm32f10x_pwr.h
  • PWR_DeInit() : stm32f10x_pwr.c , stm32f10x_pwr.h
  • PWR_EnterSTANDBYMode() : stm32f10x_pwr.c , stm32f10x_pwr.h
  • PWR_EnterSTOPMode() : stm32f10x_pwr.h , stm32f10x_pwr.c
  • PWR_GetFlagStatus() : stm32f10x_pwr.c , stm32f10x_pwr.h
  • PWR_PVDCmd() : stm32f10x_pwr.h , stm32f10x_pwr.c
  • PWR_PVDLevelConfig() : stm32f10x_pwr.h , stm32f10x_pwr.c
  • PWR_WakeUpPinCmd() : stm32f10x_pwr.c , stm32f10x_pwr.h


STM32F10x Standard Peripherals Firmware Library: Globals

  • File List
  • Globals
  • All
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  • Typedefs
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- r -

  • RCC_ADCCLKConfig() : stm32f10x_rcc.h , stm32f10x_rcc.c
  • RCC_AdjustHSICalibrationValue() : stm32f10x_rcc.c , stm32f10x_rcc.h
  • RCC_AHBPeriphClockCmd() : stm32f10x_rcc.h , stm32f10x_rcc.c
  • RCC_APB1PeriphClockCmd() : stm32f10x_rcc.c , stm32f10x_rcc.h
  • RCC_APB1PeriphResetCmd() : stm32f10x_rcc.h , stm32f10x_rcc.c
  • RCC_APB2PeriphClockCmd() : stm32f10x_rcc.h , stm32f10x_rcc.c
  • RCC_APB2PeriphResetCmd() : stm32f10x_rcc.h , stm32f10x_rcc.c
  • RCC_BackupResetCmd() : stm32f10x_rcc.c , stm32f10x_rcc.h
  • RCC_ClearFlag() : stm32f10x_rcc.h , stm32f10x_rcc.c
  • RCC_ClearITPendingBit() : stm32f10x_rcc.h , stm32f10x_rcc.c
  • RCC_ClockSecuritySystemCmd() : stm32f10x_rcc.h , stm32f10x_rcc.c
  • RCC_Configuration() : STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/main.c , STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/main.c , STM32F10x_StdPeriph_Examples/TIM/TimeBase/main.c , STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/main.c , STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/main.c , STM32F10x_StdPeriph_Examples/USART/DMA_Polling/main.c , STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/main.c , STM32F10x_StdPeriph_Examples/USART/HalfDuplex/main.c , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/main.c , STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/main.c , STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c , STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/main.c , STM32F10x_StdPeriph_Examples/DMA/FSMC/main.c , STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/main.c , STM32F10x_StdPeriph_Examples/USART/MultiProcessor/main.c , STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/main.c , STM32F10x_StdPeriph_Examples/USART/Polling/main.c , STM32F10x_StdPeriph_Examples/USART/Smartcard/main.c , STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/main.c , STM32F10x_StdPeriph_Examples/USART/Synchronous/main.c , STM32F10x_StdPeriph_Examples/FSMC/NOR/main.c , STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/main.c , STM32F10x_StdPeriph_Examples/I2S/Interrupt/main.c , STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/main.c , STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/main.c , STM32F10x_StdPeriph_Examples/SPI/CRC/main.c , STM32F10x_StdPeriph_Examples/SPI/DMA/main.c , STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c , STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/main.c , STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/main.c , STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/main.c , STM32F10x_StdPeriph_Examples/TIM/6Steps/main.c , STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/main.c , STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/main.c , STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/main.c , STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/main.c , STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/main.c , STM32F10x_StdPeriph_Examples/TIM/DMA/main.c , STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/main.c , STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/main.c , STM32F10x_StdPeriph_Examples/TIM/InputCapture/main.c , STM32F10x_StdPeriph_Examples/TIM/OCActive/main.c , STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/main.c , STM32F10x_StdPeriph_Examples/TIM/OCInactive/main.c , STM32F10x_StdPeriph_Examples/TIM/OCToggle/main.c , STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/main.c , STM32F10x_StdPeriph_Examples/TIM/OnePulse/main.c , STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/main.c , STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/main.c , STM32F10x_StdPeriph_Examples/TIM/PWM_Input/main.c , STM32F10x_StdPeriph_Examples/TIM/PWM_Output/main.c , STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/main.c , STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/main.c , STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/main.c
  • RCC_DeInit() : stm32f10x_rcc.h , stm32f10x_rcc.c
  • RCC_GetClocksFreq() : stm32f10x_rcc.h , stm32f10x_rcc.c
  • RCC_GetFlagStatus() : stm32f10x_rcc.h , stm32f10x_rcc.c
  • RCC_GetITStatus() : stm32f10x_rcc.h , stm32f10x_rcc.c
  • RCC_GetSYSCLKSource() : stm32f10x_rcc.h , stm32f10x_rcc.c
  • RCC_HCLKConfig() : stm32f10x_rcc.c , stm32f10x_rcc.h
  • RCC_HSEConfig() : stm32f10x_rcc.h , stm32f10x_rcc.c
  • RCC_HSICmd() : stm32f10x_rcc.c , stm32f10x_rcc.h
  • RCC_IRQHandler() : STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/stm32f10x_it.h
  • RCC_ITConfig() : stm32f10x_rcc.c , stm32f10x_rcc.h
  • RCC_LSEConfig() : stm32f10x_rcc.h , stm32f10x_rcc.c
  • RCC_LSICmd() : stm32f10x_rcc.c , stm32f10x_rcc.h
  • RCC_MCOConfig() : stm32f10x_rcc.h , stm32f10x_rcc.c
  • RCC_PCLK1Config() : stm32f10x_rcc.h , stm32f10x_rcc.c
  • RCC_PCLK2Config() : stm32f10x_rcc.h , stm32f10x_rcc.c
  • RCC_PLLCmd() : stm32f10x_rcc.h , stm32f10x_rcc.c
  • RCC_PLLConfig() : stm32f10x_rcc.c , stm32f10x_rcc.h
  • RCC_RTCCLKCmd() : stm32f10x_rcc.h , stm32f10x_rcc.c
  • RCC_RTCCLKConfig() : stm32f10x_rcc.c , stm32f10x_rcc.h
  • RCC_SYSCLKConfig() : stm32f10x_rcc.c , stm32f10x_rcc.h
  • RCC_USBCLKConfig() : stm32f10x_rcc.c , stm32f10x_rcc.h
  • RCC_WaitForHSEStartUp() : stm32f10x_rcc.h , stm32f10x_rcc.c
  • ReadKey() : STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/main.c
  • RTC_ClearFlag() : stm32f10x_rtc.h , stm32f10x_rtc.c
  • RTC_ClearITPendingBit() : stm32f10x_rtc.h , stm32f10x_rtc.c
  • RTC_Configuration() : STM32F10x_StdPeriph_Examples/RTC/Calendar/main.c , STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/main.c , STM32F10x_StdPeriph_Examples/PWR/STANDBY/main.c , STM32F10x_StdPeriph_Examples/PWR/STOP/main.c
  • RTC_EnterConfigMode() : stm32f10x_rtc.h , stm32f10x_rtc.c
  • RTC_ExitConfigMode() : stm32f10x_rtc.h , stm32f10x_rtc.c
  • RTC_GetCounter() : stm32f10x_rtc.c , stm32f10x_rtc.h
  • RTC_GetDivider() : stm32f10x_rtc.c , stm32f10x_rtc.h
  • RTC_GetFlagStatus() : stm32f10x_rtc.c , stm32f10x_rtc.h
  • RTC_GetITStatus() : stm32f10x_rtc.h , stm32f10x_rtc.c
  • RTC_IRQHandler() : STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/RTC/Calendar/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/RTC/Calendar/stm32f10x_it.c
  • RTC_ITConfig() : stm32f10x_rtc.c , stm32f10x_rtc.h
  • RTC_SetAlarm() : stm32f10x_rtc.h , stm32f10x_rtc.c
  • RTC_SetCounter() : stm32f10x_rtc.h , stm32f10x_rtc.c
  • RTC_SetPrescaler() : stm32f10x_rtc.c , stm32f10x_rtc.h
  • RTC_WaitForLastTask() : stm32f10x_rtc.c , stm32f10x_rtc.h
  • RTC_WaitForSynchro() : stm32f10x_rtc.c , stm32f10x_rtc.h
  • RTCAlarm_IRQHandler() : STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_it.h


STM32F10x Standard Peripherals Firmware Library: Globals

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- s -

  • SC_decode_Answer2reset() : STM32F10x_StdPeriph_Examples/USART/Smartcard/main.c
  • SC_USART_IRQHandler() : STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_it.c
  • SD_DeInit() : stm32_eval_sdio_sd.h , stm32_eval_spi_sd.c , stm32_eval_sdio_sd.c , stm32_eval_spi_sd.h
  • SD_Detect() : stm32_eval_sdio_sd.h , stm32_eval_spi_sd.c , stm32_eval_spi_sd.h , stm32_eval_sdio_sd.c
  • SD_DMAEndOfTransferStatus() : stm3210e_eval.c , stm3210e_eval.h
  • SD_EnableWideBusOperation() : stm32_eval_sdio_sd.c , stm32_eval_sdio_sd.h
  • SD_Erase() : stm32_eval_sdio_sd.h , stm32_eval_sdio_sd.c
  • SD_EraseTest() : STM32F10x_StdPeriph_Examples/SDIO/uSDCard/main.c
  • SD_GetCardInfo() : stm32_eval_sdio_sd.c , stm32_eval_sdio_sd.h , stm32_eval_spi_sd.c , stm32_eval_spi_sd.h
  • SD_GetCardStatus() : stm32_eval_sdio_sd.c , stm32_eval_sdio_sd.h
  • SD_GetCIDRegister() : stm32_eval_spi_sd.c , stm32_eval_spi_sd.h
  • SD_GetCSDRegister() : stm32_eval_spi_sd.c , stm32_eval_spi_sd.h
  • SD_GetDataResponse() : stm32_eval_spi_sd.c , stm32_eval_spi_sd.h
  • SD_GetResponse() : stm32_eval_spi_sd.c , stm32_eval_spi_sd.h
  • SD_GetState() : stm32_eval_sdio_sd.c , stm32_eval_sdio_sd.h
  • SD_GetStatus() : stm32_eval_sdio_sd.c , stm32_eval_sdio_sd.h , stm32_eval_spi_sd.c , stm32_eval_spi_sd.h
  • SD_GetTransferState() : stm32_eval_sdio_sd.c , stm32_eval_sdio_sd.h
  • SD_GoIdleState() : stm32_eval_spi_sd.c , stm32_eval_spi_sd.h
  • SD_Init() : stm32_eval_sdio_sd.c , stm32_eval_sdio_sd.h , stm32_eval_spi_sd.c , stm32_eval_spi_sd.h
  • SD_InitializeCards() : stm32_eval_sdio_sd.c , stm32_eval_sdio_sd.h
  • SD_LowLevel_DeInit() : stm32100b_eval.c , stm32100b_eval.h , stm32100e_eval.c , stm32100e_eval.h , stm3210b_eval.c , stm3210b_eval.h , stm3210c_eval.c , stm3210c_eval.h , stm3210e_eval.c , stm3210e_eval.h , stm32l152_eval.c , stm32l152_eval.h
  • SD_LowLevel_DMA_RxConfig() : stm3210e_eval.c , stm3210e_eval.h
  • SD_LowLevel_DMA_TxConfig() : stm3210e_eval.c , stm3210e_eval.h
  • SD_LowLevel_Init() : stm32100b_eval.c , stm32100b_eval.h , stm32100e_eval.c , stm32100e_eval.h , stm3210b_eval.c , stm3210b_eval.h , stm3210c_eval.c , stm3210c_eval.h , stm3210e_eval.c , stm3210e_eval.h , stm32l152_eval.c , stm32l152_eval.h
  • SD_MultiBlockTest() : STM32F10x_StdPeriph_Examples/SDIO/uSDCard/main.c
  • SD_PowerOFF() : stm32_eval_sdio_sd.c , stm32_eval_sdio_sd.h
  • SD_PowerON() : stm32_eval_sdio_sd.c , stm32_eval_sdio_sd.h
  • SD_ProcessIRQSrc() : stm32_eval_sdio_sd.c , stm32_eval_sdio_sd.h
  • SD_ReadBlock() : stm32_eval_sdio_sd.c , stm32_eval_sdio_sd.h , stm32_eval_spi_sd.c , stm32_eval_spi_sd.h
  • SD_ReadByte() : stm32_eval_spi_sd.c , stm32_eval_spi_sd.h
  • SD_ReadMultiBlocks() : stm32_eval_sdio_sd.c , stm32_eval_sdio_sd.h , stm32_eval_spi_sd.c , stm32_eval_spi_sd.h
  • SD_SelectDeselect() : stm32_eval_sdio_sd.c , stm32_eval_sdio_sd.h
  • SD_SendCmd() : stm32_eval_spi_sd.c , stm32_eval_spi_sd.h
  • SD_SendSDStatus() : stm32_eval_sdio_sd.c , stm32_eval_sdio_sd.h
  • SD_SendStatus() : stm32_eval_sdio_sd.c , stm32_eval_sdio_sd.h
  • SD_SingleBlockTest() : STM32F10x_StdPeriph_Examples/SDIO/uSDCard/main.c
  • SD_StopTransfer() : stm32_eval_sdio_sd.c , stm32_eval_sdio_sd.h
  • SD_WaitReadOperation() : stm32_eval_sdio_sd.c , stm32_eval_sdio_sd.h
  • SD_WaitWriteOperation() : stm32_eval_sdio_sd.c , stm32_eval_sdio_sd.h
  • SD_WriteBlock() : stm32_eval_sdio_sd.c , stm32_eval_sdio_sd.h , stm32_eval_spi_sd.c , stm32_eval_spi_sd.h
  • SD_WriteByte() : stm32_eval_spi_sd.c , stm32_eval_spi_sd.h
  • SD_WriteMultiBlocks() : stm32_eval_sdio_sd.c , stm32_eval_sdio_sd.h , stm32_eval_spi_sd.c , stm32_eval_spi_sd.h
  • SDEnWideBus() : stm32_eval_sdio_sd.c
  • SDIO_CEATAITCmd() : stm32f10x_sdio.h , stm32f10x_sdio.c
  • SDIO_ClearFlag() : stm32f10x_sdio.h , stm32f10x_sdio.c
  • SDIO_ClearITPendingBit() : stm32f10x_sdio.h , stm32f10x_sdio.c
  • SDIO_ClockCmd() : stm32f10x_sdio.h , stm32f10x_sdio.c
  • SDIO_CmdStructInit() : stm32f10x_sdio.c , stm32f10x_sdio.h
  • SDIO_CommandCompletionCmd() : stm32f10x_sdio.h , stm32f10x_sdio.c
  • SDIO_DataConfig() : stm32f10x_sdio.h , stm32f10x_sdio.c
  • SDIO_DataStructInit() : stm32f10x_sdio.h , stm32f10x_sdio.c
  • SDIO_DeInit() : stm32f10x_sdio.h , stm32f10x_sdio.c
  • SDIO_DMACmd() : stm32f10x_sdio.h , stm32f10x_sdio.c
  • SDIO_GetCommandResponse() : stm32f10x_sdio.h , stm32f10x_sdio.c
  • SDIO_GetDataCounter() : stm32f10x_sdio.h , stm32f10x_sdio.c
  • SDIO_GetFIFOCount() : stm32f10x_sdio.h , stm32f10x_sdio.c
  • SDIO_GetFlagStatus() : stm32f10x_sdio.h , stm32f10x_sdio.c
  • SDIO_GetITStatus() : stm32f10x_sdio.h , stm32f10x_sdio.c
  • SDIO_GetPowerState() : stm32f10x_sdio.h , stm32f10x_sdio.c
  • SDIO_GetResponse() : stm32f10x_sdio.h , stm32f10x_sdio.c
  • SDIO_Init() : stm32f10x_sdio.h , stm32f10x_sdio.c
  • SDIO_IRQHandler() : STM32F10x_StdPeriph_Examples/SDIO/uSDCard/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SDIO/uSDCard/stm32f10x_it.h
  • SDIO_ITConfig() : stm32f10x_sdio.h , stm32f10x_sdio.c
  • SDIO_ReadData() : stm32f10x_sdio.h , stm32f10x_sdio.c
  • SDIO_SendCEATACmd() : stm32f10x_sdio.h , stm32f10x_sdio.c
  • SDIO_SendCommand() : stm32f10x_sdio.h , stm32f10x_sdio.c
  • SDIO_SendSDIOSuspendCmd() : stm32f10x_sdio.h , stm32f10x_sdio.c
  • SDIO_SetPowerState() : stm32f10x_sdio.h , stm32f10x_sdio.c
  • SDIO_SetSDIOOperation() : stm32f10x_sdio.h , stm32f10x_sdio.c
  • SDIO_SetSDIOReadWaitMode() : stm32f10x_sdio.h , stm32f10x_sdio.c
  • SDIO_StartSDIOReadWait() : stm32f10x_sdio.h , stm32f10x_sdio.c
  • SDIO_StopSDIOReadWait() : stm32f10x_sdio.h , stm32f10x_sdio.c
  • SDIO_StructInit() : stm32f10x_sdio.h , stm32f10x_sdio.c
  • SDIO_WriteData() : stm32f10x_sdio.h , stm32f10x_sdio.c
  • sEE_DeInit() : stm32_eval_i2c_ee.c , stm32_eval_i2c_ee.h , stm32l152_eval_i2c_ee.c , stm32l152_eval_i2c_ee.h
  • sEE_EnterCriticalSection_UserCallback() : stm32_eval_i2c_ee.c , stm32_eval_i2c_ee.h
  • sEE_ExitCriticalSection_UserCallback() : stm32_eval_i2c_ee.c , stm32_eval_i2c_ee.h
  • sEE_I2C_DMA_RX_IRQHandler() : stm32_eval_i2c_ee.c , stm32l152_eval_i2c_ee.c
  • sEE_I2C_DMA_TX_IRQHandler() : stm32_eval_i2c_ee.c , stm32l152_eval_i2c_ee.c
  • sEE_Init() : stm32_eval_i2c_ee.c , stm32_eval_i2c_ee.h , stm32l152_eval_i2c_ee.c , stm32l152_eval_i2c_ee.h
  • sEE_LowLevel_DeInit() : stm32100e_eval.c , stm32100e_eval.h , stm3210c_eval.c , stm3210c_eval.h , stm32l152_eval.c , stm32l152_eval.h
  • sEE_LowLevel_DMAConfig() : stm32100e_eval.c , stm32100e_eval.h , stm3210c_eval.c , stm3210c_eval.h , stm32l152_eval.c , stm32l152_eval.h
  • sEE_LowLevel_Init() : stm32100e_eval.c , stm32100e_eval.h , stm3210c_eval.c , stm3210c_eval.h , stm32l152_eval.c , stm32l152_eval.h
  • sEE_ReadBuffer() : stm32_eval_i2c_ee.c , stm32_eval_i2c_ee.h , stm32l152_eval_i2c_ee.c , stm32l152_eval_i2c_ee.h
  • sEE_TIMEOUT_UserCallback() : STM32F10x_StdPeriph_Examples/I2C/EEPROM/main.c , stm32_eval_i2c_ee.h , stm32l152_eval_i2c_ee.h
  • sEE_WaitEepromStandbyState() : stm32_eval_i2c_ee.c , stm32_eval_i2c_ee.h , stm32l152_eval_i2c_ee.c , stm32l152_eval_i2c_ee.h
  • sEE_WriteBuffer() : stm32_eval_i2c_ee.c , stm32_eval_i2c_ee.h , stm32l152_eval_i2c_ee.c , stm32l152_eval_i2c_ee.h
  • sEE_WritePage() : stm32_eval_i2c_ee.c , stm32_eval_i2c_ee.h , stm32l152_eval_i2c_ee.c , stm32l152_eval_i2c_ee.h
  • SetSysClock() : Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/system_stm32f10x.c , STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/main.c
  • SetSysClockTo24() : STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/main.c
  • SetSysClockTo36() : STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/main.c
  • SetSysClockTo48() : STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/main.c
  • SetSysClockTo56() : Project/STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/system_stm32f10x.c , STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/main.c
  • SetSysClockTo72() : Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.c , STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/main.c
  • SetSysClockToHSE() : STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/main.c
  • SetVar_PeriodValue() : STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/main.c , RTC/LSI_Calib/main.h
  • sFLASH_DeInit() : stm32_eval_spi_flash.c , stm32_eval_spi_flash.h
  • sFLASH_EraseBulk() : stm32_eval_spi_flash.c , stm32_eval_spi_flash.h
  • sFLASH_EraseSector() : stm32_eval_spi_flash.c , stm32_eval_spi_flash.h
  • sFLASH_Init() : stm32_eval_spi_flash.c , stm32_eval_spi_flash.h
  • sFLASH_LowLevel_DeInit() : stm32100b_eval.h , stm32100e_eval.c , stm32100e_eval.h , stm3210b_eval.c , stm3210b_eval.h , stm3210e_eval.c , stm3210e_eval.h , stm32100b_eval.c
  • sFLASH_LowLevel_Init() : stm32100b_eval.c , stm32100b_eval.h , stm32100e_eval.c , stm32100e_eval.h , stm3210b_eval.c , stm3210b_eval.h , stm3210e_eval.c , stm3210e_eval.h
  • sFLASH_ReadBuffer() : stm32_eval_spi_flash.c , stm32_eval_spi_flash.h
  • sFLASH_ReadByte() : stm32_eval_spi_flash.c , stm32_eval_spi_flash.h
  • sFLASH_ReadID() : stm32_eval_spi_flash.c , stm32_eval_spi_flash.h
  • sFLASH_SendByte() : stm32_eval_spi_flash.c , stm32_eval_spi_flash.h
  • sFLASH_SendHalfWord() : stm32_eval_spi_flash.c , stm32_eval_spi_flash.h
  • sFLASH_StartReadSequence() : stm32_eval_spi_flash.c , stm32_eval_spi_flash.h
  • sFLASH_WaitForWriteEnd() : stm32_eval_spi_flash.c , stm32_eval_spi_flash.h
  • sFLASH_WriteBuffer() : stm32_eval_spi_flash.c , stm32_eval_spi_flash.h
  • sFLASH_WriteEnable() : stm32_eval_spi_flash.c , stm32_eval_spi_flash.h
  • sFLASH_WritePage() : stm32_eval_spi_flash.c , stm32_eval_spi_flash.h
  • SPI1_IRQHandler() : STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.h
  • SPI2_IRQHandler() : STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.h
  • SPI3_IRQHandler() : STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.h
  • SPI_BiDirectionalLineConfig() : stm32f10x_spi.h , stm32f10x_spi.c
  • SPI_CalculateCRC() : stm32f10x_spi.h , stm32f10x_spi.c
  • SPI_Cmd() : stm32f10x_spi.h , stm32f10x_spi.c
  • SPI_Configuration() : STM32F10x_StdPeriph_Examples/USART/Synchronous/main.c
  • SPI_DataSizeConfig() : stm32f10x_spi.h , stm32f10x_spi.c
  • SPI_GetCRC() : stm32f10x_spi.h , stm32f10x_spi.c
  • SPI_GetCRCPolynomial() : stm32f10x_spi.h , stm32f10x_spi.c
  • SPI_I2S_ClearFlag() : stm32f10x_spi.h , stm32f10x_spi.c
  • SPI_I2S_ClearITPendingBit() : stm32f10x_spi.h , stm32f10x_spi.c
  • SPI_I2S_DeInit() : stm32f10x_spi.h , stm32f10x_spi.c
  • SPI_I2S_DMACmd() : stm32f10x_spi.h , stm32f10x_spi.c
  • SPI_I2S_GetFlagStatus() : stm32f10x_spi.h , stm32f10x_spi.c
  • SPI_I2S_GetITStatus() : stm32f10x_spi.h , stm32f10x_spi.c
  • SPI_I2S_ITConfig() : stm32f10x_spi.h , stm32f10x_spi.c
  • SPI_I2S_ReceiveData() : stm32f10x_spi.h , stm32f10x_spi.c
  • SPI_I2S_SendData() : stm32f10x_spi.h , stm32f10x_spi.c
  • SPI_Init() : stm32f10x_spi.h , stm32f10x_spi.c
  • SPI_NSSInternalSoftwareConfig() : stm32f10x_spi.h , stm32f10x_spi.c
  • SPI_SSOutputCmd() : stm32f10x_spi.h , stm32f10x_spi.c
  • SPI_StructInit() : stm32f10x_spi.h , stm32f10x_spi.c
  • SPI_TransmitCRC() : stm32f10x_spi.h , stm32f10x_spi.c
  • SRAM_Init() : stm32100e_eval_fsmc_sram.c , stm32100e_eval_fsmc_sram.h , stm3210e_eval_fsmc_sram.c , stm3210e_eval_fsmc_sram.h
  • SRAM_ReadBuffer() : stm32100e_eval_fsmc_sram.c , stm32100e_eval_fsmc_sram.h , stm3210e_eval_fsmc_sram.c , stm3210e_eval_fsmc_sram.h
  • SRAM_WriteBuffer() : stm32100e_eval_fsmc_sram.c , stm32100e_eval_fsmc_sram.h , stm3210e_eval_fsmc_sram.c , stm3210e_eval_fsmc_sram.h
  • STM32100B_LCD_Init() : stm32100b_eval_lcd.c , stm32100b_eval_lcd.h
  • STM32100E_LCD_Init() : stm32100e_eval_lcd.c , stm32100e_eval_lcd.h
  • STM3210B_LCD_Init() : stm3210b_eval_lcd.c , stm3210b_eval_lcd.h
  • STM3210C_LCD_Init() : stm3210c_eval_lcd.c , stm3210c_eval_lcd.h
  • STM3210E_LCD_Init() : stm3210e_eval_lcd.c , stm3210e_eval_lcd.h
  • STM32L152_LCD_DeInit() : stm32l152_eval_lcd.c , stm32l152_eval_lcd.h
  • STM32L152_LCD_Init() : stm32l152_eval_lcd.c , stm32l152_eval_lcd.h
  • STM_EVAL_COMInit() : stm32100b_eval.c , stm32100b_eval.h , stm32100e_eval.c , stm32100e_eval.h , stm3210b_eval.c , stm3210b_eval.h , stm3210c_eval.c , stm3210c_eval.h , stm3210e_eval.c , stm3210e_eval.h , stm32l152_eval.c , stm32l152_eval.h
  • STM_EVAL_LEDInit() : stm32100b_eval.c , stm32100b_eval.h , stm32100e_eval.c , stm32100e_eval.h , stm3210b_eval.c , stm3210b_eval.h , stm3210c_eval.c , stm3210c_eval.h , stm3210e_eval.c , stm3210e_eval.h , stm32l152_eval.c , stm32l152_eval.h
  • STM_EVAL_LEDOff() : stm32100b_eval.c , stm32100b_eval.h , stm32100e_eval.c , stm32100e_eval.h , stm3210b_eval.c , stm3210b_eval.h , stm3210c_eval.c , stm3210c_eval.h , stm3210e_eval.c , stm3210e_eval.h , stm32l152_eval.c , stm32l152_eval.h
  • STM_EVAL_LEDOn() : stm32100b_eval.c , stm32100b_eval.h , stm32100e_eval.c , stm32100e_eval.h , stm3210b_eval.c , stm3210b_eval.h , stm3210c_eval.c , stm3210c_eval.h , stm3210e_eval.c , stm3210e_eval.h , stm32l152_eval.c , stm32l152_eval.h
  • STM_EVAL_LEDToggle() : stm32100b_eval.c , stm32100b_eval.h , stm32100e_eval.c , stm32100e_eval.h , stm3210b_eval.c , stm3210b_eval.h , stm3210c_eval.c , stm3210c_eval.h , stm3210e_eval.c , stm3210e_eval.h , stm32l152_eval.c , stm32l152_eval.h
  • STM_EVAL_PBGetState() : stm3210b_eval.c , stm32100b_eval.c , stm32100b_eval.h , stm32100e_eval.c , stm32100e_eval.h , stm3210b_eval.h , stm3210c_eval.c , stm3210c_eval.h , stm3210e_eval.c , stm3210e_eval.h , stm32l152_eval.c , stm32l152_eval.h
  • STM_EVAL_PBInit() : stm3210e_eval.c , stm3210b_eval.c , stm32100b_eval.c , stm32100b_eval.h , stm32100e_eval.c , stm32100e_eval.h , stm3210b_eval.h , stm3210c_eval.c , stm3210c_eval.h , stm3210e_eval.h , stm32l152_eval.c , stm32l152_eval.h
  • SVC_Handler() : STM32F10x_StdPeriph_Examples/TIM/OCActive/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/NOR/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/OneNAND/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/OneNAND/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/SRAM/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/GPIO/IOToggle/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2C/EEPROM/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2C/IOExpander/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2C/IOExpander/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/DMA/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/DMABurst/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SysTick/TimeBase/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/PWR/PVD/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/PWR/PVD/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/6Steps/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/PWR/STANDBY/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/RTC/Calendar/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/RTC/Calendar/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/DMA/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SDIO/uSDCard/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SDIO/uSDCard/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/CRC/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/DMA/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SysTick/TimeBase/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/CRC/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/6Steps/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/DMA/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/DMABurst/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/OCActive/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/OCInactive/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/OCInactive/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/PWR/STANDBY/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/PWM_Input/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/PWM_Output/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Polling/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/DMA_Polling/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/HalfDuplex/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/MultiProcessor/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Printf/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Synchronous/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_it.h , STM32F10x_StdPeriph_Template/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2C/EEPROM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/GPIO/IOToggle/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/SRAM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/NOR/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/NAND/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FLASH/Program/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/FSMC/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CortexM3/MPU/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CortexM3/BitBand/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/BKP/Backup_Data/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Printf/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/MultiProcessor/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Polling/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_it.c , STM32F10x_StdPeriph_Template/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Synchronous/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/NAND/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FLASH/Program/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CortexM3/BitBand/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/BKP/Tamper/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/BKP/Backup_Data/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/BKP/Tamper/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/HalfDuplex/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/DMA_Polling/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CortexM3/MPU/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/OnePulse/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/FSMC/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/PWM_Output/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/OnePulse/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/PWM_Input/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/stm32f10x_it.c
  • SYSCLKConfig_STOP() : STM32F10x_StdPeriph_Examples/PWR/STOP/main.c
  • SystemCoreClockUpdate() : Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.c , system_stm32f10x.h
  • SystemInit() : Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.c , system_stm32f10x.h
  • SysTick_CLKSourceConfig() : misc.h , misc.c
  • SysTick_Configuration() : STM32F10x_StdPeriph_Examples/PWR/STANDBY/main.c , STM32F10x_StdPeriph_Examples/PWR/STOP/main.c , STM32F10x_StdPeriph_Examples/TIM/6Steps/main.c
  • SysTick_Handler() : STM32F10x_StdPeriph_Examples/FSMC/SRAM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/OneNAND/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/OCActive/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/FSMC/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Polling/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/DMABurst/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/DMA_Polling/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/SRAM/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/BKP/Tamper/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/DMA_Polling/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/GPIO/IOToggle/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Template/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FLASH/Program/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/NOR/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/DMABurst/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Synchronous/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/NAND/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/DMA/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CortexM3/MPU/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CortexM3/BitBand/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CortexM3/BitBand/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/PWM_Input/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/PWM_Input/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/DMA/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/stm32f10x_it.c , STM32F10x_StdPeriph_Template/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/OCInactive/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/PWR/PVD/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Polling/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/FSMC/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SDIO/uSDCard/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Printf/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/PWR/PVD/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/OnePulse/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2C/IOExpander/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SysTick/TimeBase/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/RTC/Calendar/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/PWM_Output/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/6Steps/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/MultiProcessor/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/NAND/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/6Steps/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/NOR/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SDIO/uSDCard/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CortexM3/MPU/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SPI/CRC/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/RTC/Calendar/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/PWM_Output/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/OCActive/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/DMA/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/OnePulse/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/BKP/Backup_Data/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/BKP/Tamper/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/PWR/STANDBY/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FLASH/Program/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/OneNAND/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SysTick/TimeBase/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/GPIO/IOToggle/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/DMA/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/HalfDuplex/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/PWR/STANDBY/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2C/EEPROM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Printf/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SPI/CRC/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/BKP/Backup_Data/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/OCInactive/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Synchronous/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/HalfDuplex/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/MultiProcessor/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2C/EEPROM/stm32f10x_it.h


STM32F10x Standard Peripherals Firmware Library: Globals

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  • TAMPER_IRQHandler() : STM32F10x_StdPeriph_Examples/BKP/Tamper/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/BKP/Tamper/stm32f10x_it.h
  • TI1_Config() : stm32f10x_tim.c
  • TI2_Config() : stm32f10x_tim.c
  • TI3_Config() : stm32f10x_tim.c
  • TI4_Config() : stm32f10x_tim.c
  • TIM1_BRK_TIM9_IRQHandler() : STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_it.c
  • TIM1_TRG_COM_IRQHandler() : STM32F10x_StdPeriph_Examples/TIM/6Steps/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/6Steps/stm32f10x_it.h
  • TIM2_IRQHandler() : STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/OCInactive/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/OCInactive/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_it.h
  • TIM3_IRQHandler() : STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/PWM_Input/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/PWM_Input/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_it.h
  • TIM4_IRQHandler() : STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_it.h
  • TIM5_ConfigForLSI() : STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/main.c
  • TIM5_IRQHandler() : STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_it.h
  • TIM_ARRPreloadConfig() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_BDTRConfig() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_BDTRStructInit() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_CCPreloadControl() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_CCxCmd() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_CCxNCmd() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_ClearFlag() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_ClearITPendingBit() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_ClearOC1Ref() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_ClearOC2Ref() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_ClearOC3Ref() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_ClearOC4Ref() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_Cmd() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_Config() : STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/main.c
  • TIM_CounterModeConfig() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_CtrlPWMOutputs() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_DeInit() : stm32f10x_tim.c , stm32f10x_tim.h
  • TIM_DMACmd() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_DMAConfig() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_EncoderInterfaceConfig() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_ETRClockMode1Config() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_ETRClockMode2Config() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_ETRConfig() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_ForcedOC1Config() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_ForcedOC2Config() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_ForcedOC3Config() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_ForcedOC4Config() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_GenerateEvent() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_GetCapture1() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_GetCapture2() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_GetCapture3() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_GetCapture4() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_GetCounter() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_GetFlagStatus() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_GetITStatus() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_GetPrescaler() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_ICInit() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_ICStructInit() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_InternalClockConfig() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_ITConfig() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_ITRxExternalClockConfig() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_OC1FastConfig() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_OC1Init() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_OC1NPolarityConfig() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_OC1PolarityConfig() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_OC1PreloadConfig() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_OC2FastConfig() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_OC2Init() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_OC2NPolarityConfig() : stm32f10x_tim.c , stm32f10x_tim.h
  • TIM_OC2PolarityConfig() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_OC2PreloadConfig() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_OC3FastConfig() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_OC3Init() : stm32f10x_tim.c , stm32f10x_tim.h
  • TIM_OC3NPolarityConfig() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_OC3PolarityConfig() : stm32f10x_tim.c , stm32f10x_tim.h
  • TIM_OC3PreloadConfig() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_OC4FastConfig() : stm32f10x_tim.c , stm32f10x_tim.h
  • TIM_OC4Init() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_OC4PolarityConfig() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_OC4PreloadConfig() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_OCStructInit() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_PrescalerConfig() : stm32f10x_tim.c , stm32f10x_tim.h
  • TIM_PWMIConfig() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_SelectCCDMA() : stm32f10x_tim.c , stm32f10x_tim.h
  • TIM_SelectCOM() : stm32f10x_tim.c , stm32f10x_tim.h
  • TIM_SelectHallSensor() : stm32f10x_tim.c , stm32f10x_tim.h
  • TIM_SelectInputTrigger() : stm32f10x_tim.c , stm32f10x_tim.h
  • TIM_SelectMasterSlaveMode() : stm32f10x_tim.c , stm32f10x_tim.h
  • TIM_SelectOCxM() : stm32f10x_tim.c , stm32f10x_tim.h
  • TIM_SelectOnePulseMode() : stm32f10x_tim.c , stm32f10x_tim.h
  • TIM_SelectOutputTrigger() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_SelectSlaveMode() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_SetAutoreload() : stm32f10x_tim.c , stm32f10x_tim.h
  • TIM_SetClockDivision() : stm32f10x_tim.c , stm32f10x_tim.h
  • TIM_SetCompare1() : stm32f10x_tim.c , stm32f10x_tim.h
  • TIM_SetCompare2() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_SetCompare3() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_SetCompare4() : stm32f10x_tim.c , stm32f10x_tim.h
  • TIM_SetCounter() : stm32f10x_tim.c , stm32f10x_tim.h
  • TIM_SetIC1Prescaler() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_SetIC2Prescaler() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_SetIC3Prescaler() : stm32f10x_tim.c , stm32f10x_tim.h
  • TIM_SetIC4Prescaler() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_TimeBaseInit() : stm32f10x_tim.c , stm32f10x_tim.h
  • TIM_TimeBaseStructInit() : stm32f10x_tim.c , stm32f10x_tim.h
  • TIM_TIxExternalClockConfig() : stm32f10x_tim.h , stm32f10x_tim.c
  • TIM_UpdateDisableConfig() : stm32f10x_tim.c , stm32f10x_tim.h
  • TIM_UpdateRequestConfig() : stm32f10x_tim.c , stm32f10x_tim.h
  • Time_Adjust() : STM32F10x_StdPeriph_Examples/RTC/Calendar/main.c
  • Time_Display() : STM32F10x_StdPeriph_Examples/RTC/Calendar/main.c
  • Time_Regulate() : STM32F10x_StdPeriph_Examples/RTC/Calendar/main.c
  • Time_Show() : STM32F10x_StdPeriph_Examples/RTC/Calendar/main.c
  • TimingDelay_Decrement() : STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/main.c , NVIC/VectorTable_Relocation/main.h , SysTick/TimeBase/main.h , STM32F10x_StdPeriph_Examples/SysTick/TimeBase/main.c , FLASH/Dual_Boot/main.h , STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/main.c


STM32F10x Standard Peripherals Firmware Library: Globals

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- u -

  • UsageFault_Handler() : STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/BKP/Tamper/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/DMA/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/OneNAND/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/DMA/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/DMABurst/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/OneNAND/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/DMABurst/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/SRAM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/SRAM/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/OCActive/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/OCActive/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/OCInactive/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/OCInactive/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/GPIO/IOToggle/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/OnePulse/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/GPIO/IOToggle/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/OnePulse/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/PWM_Input/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/PWM_Input/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/PWM_Output/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2C/EEPROM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/PWM_Output/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2C/EEPROM/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2C/IOExpander/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/stm32f10x_it.c , STM32F10x_StdPeriph_Template/stm32f10x_it.h , STM32F10x_StdPeriph_Template/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Synchronous/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Synchronous/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Printf/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Printf/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Polling/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Polling/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/MultiProcessor/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/MultiProcessor/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/HalfDuplex/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/HalfDuplex/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/DMA_Polling/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2C/IOExpander/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/DMA_Polling/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/FSMC/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/FSMC/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/PWR/PVD/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CortexM3/BitBand/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/6Steps/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/TIM/6Steps/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SysTick/TimeBase/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SysTick/TimeBase/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SPI/DMA/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/DMA/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SPI/CRC/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SPI/CRC/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SDIO/uSDCard/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/SDIO/uSDCard/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/RTC/Calendar/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/RTC/Calendar/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/PWR/PVD/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/PWR/STANDBY/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/PWR/STANDBY/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/BKP/Backup_Data/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CortexM3/BitBand/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FLASH/Program/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/BKP/Backup_Data/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FLASH/Program/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CortexM3/MPU/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/NAND/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/BKP/Tamper/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CortexM3/MPU/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/NAND/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/NOR/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/NOR/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/stm32f10x_it.c
  • USART1_IRQHandler() : STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.h
  • USART2_IRQHandler() : STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.h
  • USART3_IRQHandler() : STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.h
  • USART_ClearFlag() : stm32f10x_usart.c , stm32f10x_usart.h
  • USART_ClearITPendingBit() : stm32f10x_usart.c , stm32f10x_usart.h
  • USART_ClockInit() : stm32f10x_usart.h , stm32f10x_usart.c
  • USART_ClockStructInit() : stm32f10x_usart.h , stm32f10x_usart.c
  • USART_Cmd() : stm32f10x_usart.h , stm32f10x_usart.c
  • USART_DeInit() : stm32f10x_usart.c , stm32f10x_usart.h
  • USART_DMACmd() : stm32f10x_usart.c , stm32f10x_usart.h
  • USART_GetFlagStatus() : stm32f10x_usart.c , stm32f10x_usart.h
  • USART_GetITStatus() : stm32f10x_usart.c , stm32f10x_usart.h
  • USART_HalfDuplexCmd() : stm32f10x_usart.h , stm32f10x_usart.c
  • USART_Init() : stm32f10x_usart.h , stm32f10x_usart.c
  • USART_IrDACmd() : stm32f10x_usart.h , stm32f10x_usart.c
  • USART_IrDAConfig() : stm32f10x_usart.c , stm32f10x_usart.h
  • USART_ITConfig() : stm32f10x_usart.h , stm32f10x_usart.c
  • USART_LINBreakDetectLengthConfig() : stm32f10x_usart.h , stm32f10x_usart.c
  • USART_LINCmd() : stm32f10x_usart.c , stm32f10x_usart.h
  • USART_OneBitMethodCmd() : stm32f10x_usart.h , stm32f10x_usart.c
  • USART_OverSampling8Cmd() : stm32f10x_usart.c , stm32f10x_usart.h
  • USART_ReceiveData() : stm32f10x_usart.h , stm32f10x_usart.c
  • USART_ReceiverWakeUpCmd() : stm32f10x_usart.c , stm32f10x_usart.h
  • USART_Scanf() : STM32F10x_StdPeriph_Examples/RTC/Calendar/main.c
  • USART_SendBreak() : stm32f10x_usart.c , stm32f10x_usart.h
  • USART_SendData() : stm32f10x_usart.c , stm32f10x_usart.h
  • USART_SetAddress() : stm32f10x_usart.h , stm32f10x_usart.c
  • USART_SetGuardTime() : stm32f10x_usart.c , stm32f10x_usart.h
  • USART_SetPrescaler() : stm32f10x_usart.c , stm32f10x_usart.h
  • USART_SmartCardCmd() : stm32f10x_usart.h , stm32f10x_usart.c
  • USART_SmartCardNACKCmd() : stm32f10x_usart.c , stm32f10x_usart.h
  • USART_StructInit() : stm32f10x_usart.h , stm32f10x_usart.c
  • USART_WakeUpConfig() : stm32f10x_usart.c , stm32f10x_usart.h
  • USARTx_IRQHandler() : STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.c
  • USARTy_IRQHandler() : STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.c
  • USARTz_IRQHandler() : STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.c
  • USB_LP_CAN1_RX0_IRQHandler() : STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_it.h , STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_it.h


STM32F10x Standard Peripherals Firmware Library: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • w

- w -

  • WriteToBackupReg() : STM32F10x_StdPeriph_Examples/BKP/Backup_Data/main.c , STM32F10x_StdPeriph_Examples/BKP/Tamper/main.c
  • WWDG_ClearFlag() : stm32f10x_wwdg.c , stm32f10x_wwdg.h
  • WWDG_DeInit() : stm32f10x_wwdg.h , stm32f10x_wwdg.c
  • WWDG_Enable() : stm32f10x_wwdg.c , stm32f10x_wwdg.h
  • WWDG_EnableIT() : stm32f10x_wwdg.h , stm32f10x_wwdg.c
  • WWDG_GetFlagStatus() : stm32f10x_wwdg.h , stm32f10x_wwdg.c
  • WWDG_SetCounter() : stm32f10x_wwdg.h , stm32f10x_wwdg.c
  • WWDG_SetPrescaler() : stm32f10x_wwdg.c , stm32f10x_wwdg.h
  • WWDG_SetWindowValue() : stm32f10x_wwdg.c , stm32f10x_wwdg.h


STM32F10x Standard Peripherals Firmware Library: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • i
  • p
  • s
  • u
  • v

- i -

  • IRQn_Type : stm32f10x.h
  • ITStatus : stm32f10x.h

- p -

  • pFunction : STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/main.c
  • pPoint : stm32l152_eval_lcd.h , stm3210e_eval_lcd.h , stm3210c_eval_lcd.h , stm3210b_eval_lcd.h , stm32100e_eval_lcd.h , stm32100b_eval_lcd.h

- s -

  • s16 : stm32f10x.h
  • s32 : stm32f10x.h
  • s8 : stm32f10x.h
  • sc16 : stm32f10x.h
  • sc32 : stm32f10x.h
  • sc8 : stm32f10x.h
  • sFONT : fonts.h

- u -

  • u16 : stm32f10x.h
  • u32 : stm32f10x.h
  • u8 : stm32f10x.h
  • uc16 : stm32f10x.h
  • uc32 : stm32f10x.h
  • uc8 : stm32f10x.h

- v -

  • vs16 : stm32f10x.h
  • vs32 : stm32f10x.h
  • vs8 : stm32f10x.h
  • vsc16 : stm32f10x.h
  • vsc32 : stm32f10x.h
  • vsc8 : stm32f10x.h
  • vu16 : stm32f10x.h
  • vu32 : stm32f10x.h
  • vu8 : stm32f10x.h
  • vuc16 : stm32f10x.h
  • vuc32 : stm32f10x.h
  • vuc8 : stm32f10x.h


STM32F10x Standard Peripherals Firmware Library: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • j
  • k
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w

- a -

  • AbortReason : stm32100b_eval_cec.c , stm32100e_eval_cec.c
  • ADC1_DBG : stm32f10x_ip_dbg.c
  • ADC1ConvertedValue : STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c
  • ADC2_DBG : stm32f10x_ip_dbg.c
  • ADC2ConvertedValue : STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_it.c
  • ADC3_DBG : stm32f10x_ip_dbg.c
  • ADC3ConvertedValue : STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c
  • ADC_DualConvertedValueTab : STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/main.c
  • ADC_InitStructure : STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/main.c , STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c , STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/main.c , STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/main.c , STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/main.c , STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/main.c , STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/main.c
  • ADC_InjectedConvertedValueTab : STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/main.c , STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/main.c , STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_it.c
  • ADC_RegularConvertedValueTab : STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/main.c , STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/main.c
  • ADCConvertedValue : STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/main.c
  • ADCPrescTable : stm32f10x_rcc.c
  • Address : STM32F10x_StdPeriph_Examples/FLASH/Program/main.c , STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/main.c , STM32F10x_StdPeriph_Examples/FSMC/OneNAND/main.c
  • AFIO_DBG : stm32f10x_ip_dbg.c
  • AHBPrescTable : Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Input/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/TimeBase/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/OnePulse/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/OCToggle/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/OCInactive/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/OCActive/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/InputCapture/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/DMABurst/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/6Steps/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/SysTick/TimeBase/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/SPI/DMA/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/SPI/CRC/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/SDIO/uSDCard/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/RTC/Calendar/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/PWR/PVD/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/I2S/Interrupt/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/I2C/IOExpander/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/I2C/EEPROM/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/GPIO/IOToggle/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/FSMC/OneNAND/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/FSMC/NOR/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/FSMC/NAND/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/FLASH/Program/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/DMA/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/CortexM3/MPU/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/CortexM3/BitBand/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/PWR/STOP/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/CAN/LoopBack/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/CAN/DualCAN/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/BKP/Tamper/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Template/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/Interrupt/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/system_stm32f10x.c , Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/DMA/FSMC/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/Polling/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/HalfDuplex/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/Synchronous/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/Smartcard/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/PWR/STANDBY/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/BKP/Backup_Data/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/Printf/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/CAN/Networking/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/MultiProcessor/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/DMA_Polling/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Output/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/system_stm32f10x.c
  • APBAHBPrescTable : stm32f10x_rcc.c
  • ASCII12x12_Table : fonts.c
  • ASCII16x24_Table : fonts.c
  • ASCII8x12_Table : fonts.c
  • ASCII8x8_Table : fonts.c
  • ATRDecodeStatus : STM32F10x_StdPeriph_Examples/USART/Smartcard/main.c


STM32F10x Standard Peripherals Firmware Library: Globals

  • File List
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  • Functions
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- j -

  • j : STM32F10x_StdPeriph_Examples/FSMC/NAND/main.c , STM32F10x_StdPeriph_Examples/FSMC/OneNAND/main.c
  • Jump_To_Application : STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/main.c
  • JumpAddress : STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/main.c


STM32F10x Standard Peripherals Firmware Library: Globals

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- k -

  • k : STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/main.c
  • KeyNumber : STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CAN/Networking/main.c


STM32F10x Standard Peripherals Firmware Library: Globals

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- l -

  • LCD_Currentfonts : stm32100b_eval_lcd.c , stm32100e_eval_lcd.c , stm3210c_eval_lcd.c , stm3210e_eval_lcd.c , stm3210b_eval_lcd.c , stm32l152_eval_lcd.c
  • LCDType : stm3210b_eval_lcd.c , stm32l152_eval_lcd.c , stm32100b_eval_lcd.c
  • LetterMap : stm32l152_eval_glass_lcd.c
  • LM75_Timeout : stm32_eval_i2c_tsensor.c
  • LowPowerMode : STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/main.c , STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_it.c
  • LsiFreq : STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/main.c , STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/main.c


STM32F10x Standard Peripherals Firmware Library: Globals

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- m -

  • mask : stm32l152_eval_glass_lcd.c
  • MemoryProgramStatus : STM32F10x_StdPeriph_Examples/FLASH/Program/main.c , STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/main.c
  • MSPValue : STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/main.c
  • MyKey : STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/main.c
  • MyLogicalAddress : stm32100e_eval_cec.c , stm32100b_eval_cec.c
  • MyPhysicalAddress : stm32100e_eval_cec.c , stm32100b_eval_cec.c


STM32F10x Standard Peripherals Firmware Library: Globals

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- n -

  • NAND_ID : STM32F10x_StdPeriph_Examples/FSMC/NAND/main.c
  • NbrOfDataToRead : STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/main.c , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_it.c
  • NbrOfDataToRead1 : STM32F10x_StdPeriph_Examples/USART/Synchronous/main.c , STM32F10x_StdPeriph_Examples/USART/HalfDuplex/main.c , STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c , STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.c
  • NbrOfDataToRead2 : STM32F10x_StdPeriph_Examples/USART/HalfDuplex/main.c , STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c , STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Synchronous/main.c
  • NbrOfDataToTransfer : STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/main.c , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.c
  • NbrOfDataToTransfer1 : STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c
  • NbrOfDataToTransfer2 : STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c , STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.c
  • NbrOfPage : STM32F10x_StdPeriph_Examples/FLASH/Program/main.c , STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/main.c
  • NOR_ID : STM32F10x_StdPeriph_Examples/FSMC/NOR/main.c
  • NumberMap : stm32l152_eval_glass_lcd.c
  • NumDataRead : STM32F10x_StdPeriph_Examples/I2C/EEPROM/main.c
  • NVIC_DBG : stm32f10x_ip_dbg.c
  • NVIC_InitStructure : STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/main.c , STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/main.c


STM32F10x Standard Peripherals Firmware Library: Globals

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- o -

  • OB_DBG : stm32f10x_ip_dbg.c
  • OneNAND_ID : STM32F10x_StdPeriph_Examples/FSMC/OneNAND/main.c
  • OperationComplete : STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/main.c


STM32F10x Standard Peripherals Firmware Library: Globals

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- b -

  • BackColor : stm32100b_eval_lcd.c , stm32100e_eval_lcd.c , stm3210c_eval_lcd.c , stm3210e_eval_lcd.c , stm3210b_eval_lcd.c , stm32l152_eval_lcd.c
  • BKP_DBG : stm32f10x_ip_dbg.c
  • BKPDataReg : STM32F10x_StdPeriph_Examples/BKP/Backup_Data/main.c , STM32F10x_StdPeriph_Examples/BKP/Tamper/main.c
  • Buffer_Block_Rx : STM32F10x_StdPeriph_Examples/SDIO/uSDCard/main.c
  • Buffer_Block_Tx : STM32F10x_StdPeriph_Examples/SDIO/uSDCard/main.c
  • Buffer_MultiBlock_Rx : STM32F10x_StdPeriph_Examples/SDIO/uSDCard/main.c
  • Buffer_MultiBlock_Tx : STM32F10x_StdPeriph_Examples/SDIO/uSDCard/main.c
  • BufferCount : stm32100b_eval_cec.c , stm32100e_eval_cec.c
  • BufferPointer : stm32100b_eval_cec.c , stm32100e_eval_cec.c
  • BUTTON_CLK : stm32100b_eval.c , stm32100e_eval.c , stm3210b_eval.c , stm3210c_eval.c , stm3210e_eval.c , stm32l152_eval.c
  • BUTTON_EXTI_LINE : stm32100b_eval.c , stm32100e_eval.c , stm3210b_eval.c , stm3210c_eval.c , stm3210e_eval.c , stm32l152_eval.c
  • BUTTON_IRQn : stm3210b_eval.c , stm3210c_eval.c , stm3210e_eval.c , stm32l152_eval.c , stm32100b_eval.c , stm32100e_eval.c
  • BUTTON_PIN : stm32100b_eval.c , stm32100e_eval.c , stm3210b_eval.c , stm3210e_eval.c , stm32l152_eval.c , stm3210c_eval.c
  • BUTTON_PIN_SOURCE : stm32100e_eval.c , stm3210c_eval.c , stm32100b_eval.c , stm3210b_eval.c , stm3210e_eval.c , stm32l152_eval.c
  • BUTTON_PORT : stm3210b_eval.c , stm3210e_eval.c , stm3210c_eval.c , stm32100b_eval.c , stm32l152_eval.c , stm32100e_eval.c
  • BUTTON_PORT_SOURCE : stm3210c_eval.c , stm3210e_eval.c , stm32100b_eval.c , stm3210b_eval.c , stm32l152_eval.c , stm32100e_eval.c
  • ByteNumber : STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/main.c


STM32F10x Standard Peripherals Firmware Library: Globals

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- c -

  • CAN1_DBG : stm32f10x_ip_dbg.c
  • CAN_FilterInitStructure : STM32F10x_StdPeriph_Examples/CAN/DualCAN/main.c , STM32F10x_StdPeriph_Examples/CAN/Networking/main.c
  • CAN_InitStructure : STM32F10x_StdPeriph_Examples/CAN/DualCAN/main.c , STM32F10x_StdPeriph_Examples/CAN/Networking/main.c
  • capture : STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_it.c
  • Capture : STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_it.c
  • capture : STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_it.c
  • CaptureNumber : STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/main.c , STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_it.c
  • CardInserted : STM32F10x_StdPeriph_Examples/USART/Smartcard/main.c , STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_it.c
  • CardProtocol : STM32F10x_StdPeriph_Examples/USART/Smartcard/main.c
  • CardType : stm32_eval_sdio_sd.c
  • CCR1_Val : STM32F10x_StdPeriph_Examples/TIM/6Steps/main.c , STM32F10x_StdPeriph_Examples/TIM/OCActive/main.c , STM32F10x_StdPeriph_Examples/TIM/OCInactive/main.c , STM32F10x_StdPeriph_Examples/TIM/OCToggle/main.c , STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/PWM_Output/main.c , STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/main.c , STM32F10x_StdPeriph_Examples/TIM/TimeBase/main.c , STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_it.c
  • CCR1Val : STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/main.c , STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/main.c , STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_it.c
  • CCR2_Val : STM32F10x_StdPeriph_Examples/TIM/OCInactive/main.c , STM32F10x_StdPeriph_Examples/TIM/OCToggle/main.c , STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/PWM_Output/main.c , STM32F10x_StdPeriph_Examples/TIM/TimeBase/main.c , STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/6Steps/main.c , STM32F10x_StdPeriph_Examples/TIM/OCActive/main.c
  • CCR2Val : STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/main.c , STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_it.c
  • CCR3_Val : STM32F10x_StdPeriph_Examples/TIM/6Steps/main.c , STM32F10x_StdPeriph_Examples/TIM/OCActive/main.c , STM32F10x_StdPeriph_Examples/TIM/OCInactive/main.c , STM32F10x_StdPeriph_Examples/TIM/OCToggle/main.c , STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/PWM_Output/main.c , STM32F10x_StdPeriph_Examples/TIM/TimeBase/main.c , STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_it.c
  • CCR4_Val : STM32F10x_StdPeriph_Examples/TIM/6Steps/main.c , STM32F10x_StdPeriph_Examples/TIM/OCActive/main.c , STM32F10x_StdPeriph_Examples/TIM/OCInactive/main.c , STM32F10x_StdPeriph_Examples/TIM/OCToggle/main.c , STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/TIM/PWM_Output/main.c , STM32F10x_StdPeriph_Examples/TIM/TimeBase/main.c , STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_it.c
  • CEC_DBG : stm32f10x_ip_dbg.c
  • CEC_InitStructure : STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/main.c
  • CECDevicesNumber : stm32100b_eval_cec.c , stm32100e_eval_cec.c
  • Channel1Pulse : STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/main.c , STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/main.c
  • Channel2Pulse : STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/main.c , STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/main.c
  • Channel3Pulse : STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/main.c , STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/main.c
  • Channel4Pulse : STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/main.c
  • CID_Tab : stm32_eval_sdio_sd.c
  • COM_RX_AF : stm32l152_eval.c
  • COM_RX_PIN : stm32100b_eval.c , stm32100e_eval.c , stm3210c_eval.c , stm3210e_eval.c , stm32l152_eval.c , stm3210b_eval.c
  • COM_RX_PIN_SOURCE : stm32l152_eval.c
  • COM_RX_PORT : stm32100b_eval.c , stm32100e_eval.c , stm3210b_eval.c , stm3210e_eval.c , stm32l152_eval.c , stm3210c_eval.c
  • COM_RX_PORT_CLK : stm32100b_eval.c , stm32100e_eval.c , stm3210b_eval.c , stm3210c_eval.c , stm3210e_eval.c , stm32l152_eval.c
  • COM_TX_AF : stm32l152_eval.c
  • COM_TX_PIN : stm3210e_eval.c , stm32100e_eval.c , stm32100b_eval.c , stm3210c_eval.c , stm3210b_eval.c , stm32l152_eval.c
  • COM_TX_PIN_SOURCE : stm32l152_eval.c
  • COM_TX_PORT : stm3210c_eval.c , stm3210b_eval.c , stm32100b_eval.c , stm32100e_eval.c , stm3210e_eval.c , stm32l152_eval.c
  • COM_TX_PORT_CLK : stm3210e_eval.c , stm3210c_eval.c , stm3210b_eval.c , stm32l152_eval.c , stm32100e_eval.c , stm32100b_eval.c
  • COM_USART : stm32l152_eval.c , stm3210c_eval.c , stm32100b_eval.c , stm3210b_eval.c , stm32100e_eval.c , stm3210e_eval.c
  • COM_USART_CLK : stm32l152_eval.c , stm3210c_eval.c , stm32100e_eval.c , stm3210b_eval.c , stm32100b_eval.c , stm3210e_eval.c
  • Counter : STM32F10x_StdPeriph_Examples/USART/Smartcard/main.c
  • CRC1Value : STM32F10x_StdPeriph_Examples/SPI/CRC/main.c
  • CRC2Value : STM32F10x_StdPeriph_Examples/SPI/CRC/main.c
  • CRC_DBG : stm32f10x_ip_dbg.c
  • CRCValue : STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/main.c
  • CSD_Tab : stm32_eval_sdio_sd.c
  • CurrDataCounterBegin : STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/main.c
  • CurrDataCounterEnd : STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/main.c , STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/stm32f10x_it.c
  • CurrentStack : STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/main.c


STM32F10x Standard Peripherals Firmware Library: Globals

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  • DAC_DBG : stm32f10x_ip_dbg.c
  • DAC_InitStructure : STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/main.c , STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/main.c , STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/main.c , STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/main.c
  • Data : STM32F10x_StdPeriph_Examples/FLASH/Program/main.c , STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/main.c
  • DataBuffer : STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/main.c
  • DBGMCU_DBG : stm32f10x_ip_dbg.c
  • DeviceCount : stm32100b_eval_cec.c , stm32100e_eval_cec.c
  • DeviceType : stm32100b_eval_cec.c , stm32100e_eval_cec.c
  • digit : stm32l152_eval_glass_lcd.c
  • DMA1_Channel1_DBG : stm32f10x_ip_dbg.c
  • DMA1_Channel2_DBG : stm32f10x_ip_dbg.c
  • DMA1_Channel3_DBG : stm32f10x_ip_dbg.c
  • DMA1_Channel4_DBG : stm32f10x_ip_dbg.c
  • DMA1_Channel5_DBG : stm32f10x_ip_dbg.c
  • DMA1_Channel6_DBG : stm32f10x_ip_dbg.c
  • DMA1_Channel7_DBG : stm32f10x_ip_dbg.c
  • DMA1_DBG : stm32f10x_ip_dbg.c
  • DMA2_Channel1_DBG : stm32f10x_ip_dbg.c
  • DMA2_Channel2_DBG : stm32f10x_ip_dbg.c
  • DMA2_Channel3_DBG : stm32f10x_ip_dbg.c
  • DMA2_Channel4_DBG : stm32f10x_ip_dbg.c
  • DMA2_Channel5_DBG : stm32f10x_ip_dbg.c
  • DMA2_DBG : stm32f10x_ip_dbg.c
  • DMA_InitStructure : STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c , STM32F10x_StdPeriph_Examples/TIM/DMABurst/main.c , STM32F10x_StdPeriph_Examples/SPI/DMA/main.c , STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/main.c , STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/main.c , STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/main.c , STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/main.c , STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/main.c , STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/main.c , STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/main.c , STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/main.c , STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/main.c , STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/main.c , STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/main.c , STM32F10x_StdPeriph_Examples/DMA/FSMC/main.c
  • DST_Buffer : STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/main.c , STM32F10x_StdPeriph_Examples/USART/Smartcard/main.c , STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/DMA/FSMC/main.c , STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/main.c
  • DualSine12bit : STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/main.c
  • DutyCycle : STM32F10x_StdPeriph_Examples/TIM/PWM_Input/stm32f10x_it.c


STM32F10x Standard Peripherals Firmware Library: Globals

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- e -

  • EraseCounter : STM32F10x_StdPeriph_Examples/FLASH/Program/main.c , STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/main.c
  • EraseStatus : STM32F10x_StdPeriph_Examples/SDIO/uSDCard/main.c
  • Escalator8bit : STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/main.c
  • EXTI_DBG : stm32f10x_ip_dbg.c
  • EXTI_InitStructure : STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/main.c


STM32F10x Standard Peripherals Firmware Library: Globals

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- f -

  • FeatureOpcode : stm32100b_eval_cec.c , stm32100e_eval_cec.c
  • FLASH_DBG : stm32f10x_ip_dbg.c
  • FlashID : STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/main.c
  • FLASHStatus : STM32F10x_StdPeriph_Examples/FLASH/Program/main.c , STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/main.c
  • Font12x12 : fonts.h , fonts.c
  • Font16x24 : fonts.c , fonts.h
  • Font8x12 : fonts.c , fonts.h
  • Font8x8 : fonts.c , fonts.h
  • Frequency : STM32F10x_StdPeriph_Examples/TIM/PWM_Input/stm32f10x_it.c
  • FSMC_Bank1_DBG : stm32f10x_ip_dbg.c
  • FSMC_Bank1E_DBG : stm32f10x_ip_dbg.c
  • FSMC_Bank2_DBG : stm32f10x_ip_dbg.c
  • FSMC_Bank3_DBG : stm32f10x_ip_dbg.c
  • FSMC_Bank4_DBG : stm32f10x_ip_dbg.c


STM32F10x Standard Peripherals Firmware Library: Globals

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- g -

  • GPIO_CLK : stm32100b_eval.c , stm32100e_eval.c , stm3210c_eval.c , stm3210e_eval.c , stm3210b_eval.c , stm32l152_eval.c
  • GPIO_InitStructure : STM32F10x_StdPeriph_Examples/GPIO/IOToggle/main.c , STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/main.c , STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/main.c , STM32F10x_StdPeriph_Examples/SPI/DMA/main.c , STM32F10x_StdPeriph_Examples/TIM/DMABurst/main.c , STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/main.c
  • GPIO_PIN : stm3210c_eval.c , stm3210e_eval.c , stm32l152_eval.c , stm32100b_eval.c , stm32100e_eval.c , stm3210b_eval.c
  • GPIO_PORT : stm3210e_eval.c , stm32100b_eval.c , stm32100e_eval.c , stm3210b_eval.c , stm3210c_eval.c , stm32l152_eval.c
  • GPIOA_DBG : stm32f10x_ip_dbg.c
  • GPIOB_DBG : stm32f10x_ip_dbg.c
  • GPIOC_DBG : stm32f10x_ip_dbg.c
  • GPIOD_DBG : stm32f10x_ip_dbg.c
  • GPIOE_DBG : stm32f10x_ip_dbg.c
  • GPIOF_DBG : stm32f10x_ip_dbg.c
  • GPIOG_DBG : stm32f10x_ip_dbg.c


STM32F10x Standard Peripherals Firmware Library: Globals

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- h -

  • HDMI_CEC_DeviceMap : stm32100b_eval_cec.c , stm32100e_eval_cec.c
  • HDMI_CEC_Follower_String : stm32100e_eval_cec.c , stm32100b_eval_cec.c
  • HDMI_CEC_MapStruct : stm32100b_eval_cec.c , stm32100e_eval_cec.c
  • HDMI_CEC_RX_MessageStructPrivate : stm32100e_eval_cec.c , stm32100b_eval_cec.c
  • HDMI_CEC_TX_MessageStructPrivate : stm32100b_eval_cec.c , stm32100e_eval_cec.c
  • HDMI_CEC_TX_MessageStructure : stm32100b_eval_cec.c , stm32100e_eval_cec.c
  • HeaderBlockValueToSend : STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.c
  • HSEStartUpStatus : STM32F10x_StdPeriph_Examples/PWR/STOP/main.c , STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/main.c , STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/main.c , STM32F10x_StdPeriph_Examples/I2S/Interrupt/main.c


STM32F10x Standard Peripherals Firmware Library: Globals

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- i -

  • I2C1_Buffer_Tx : STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/main.c
  • I2C1_DBG : stm32f10x_ip_dbg.c
  • I2C2_Buffer_Rx : STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/main.c
  • I2C2_DBG : stm32f10x_ip_dbg.c
  • I2C_InitStructure : STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/main.c
  • I2S2_Buffer_Rx : STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/main.c , STM32F10x_StdPeriph_Examples/I2S/Interrupt/main.c , STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_it.c
  • I2S3_Buffer_Tx : STM32F10x_StdPeriph_Examples/I2S/Interrupt/main.c , STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/main.c
  • I2S_InitStructure : STM32F10x_StdPeriph_Examples/I2S/Interrupt/main.c , STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/main.c
  • IC1ReadValue1 : STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_it.c
  • IC1ReadValue2 : STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_it.c
  • IC2Value : STM32F10x_StdPeriph_Examples/TIM/PWM_Input/stm32f10x_it.c
  • IC3ReadValue1 : STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_it.c
  • IC3ReadValue2 : STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_it.c
  • Idx : STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/main.c , STM32F10x_StdPeriph_Examples/DMA/FSMC/main.c
  • Index : STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/main.c
  • index : STM32F10x_StdPeriph_Examples/USART/Smartcard/main.c , STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/main.c
  • Index : STM32F10x_StdPeriph_Examples/FSMC/SRAM/main.c
  • index : STM32F10x_StdPeriph_Examples/USART/Polling/main.c
  • Index : STM32F10x_StdPeriph_Examples/FSMC/NOR/main.c
  • index : STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_it.c
  • Index : STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/main.c
  • index : STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/main.c
  • Index : STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/main.c , STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_it.c
  • InitiatorAddress : STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.c
  • IOE_TimeOut : stm32100e_eval_ioe.c , stm3210c_eval_ioe.c
  • IWDG_DBG : stm32f10x_ip_dbg.c


STM32F10x Standard Peripherals Firmware Library: Globals

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- p -

  • PageIndex : STM32F10x_StdPeriph_Examples/FSMC/OneNAND/main.c
  • PageNumber : STM32F10x_StdPeriph_Examples/FSMC/NAND/main.c
  • PeriodValue : STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/main.c
  • PreemptionOccured : STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/main.c , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_it.c
  • PreemptionPriorityValue : STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/main.c , STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_it.c
  • PrescalerValue : STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/main.c , STM32F10x_StdPeriph_Examples/TIM/OCActive/main.c , STM32F10x_StdPeriph_Examples/TIM/OnePulse/main.c , STM32F10x_StdPeriph_Examples/TIM/OCInactive/main.c , STM32F10x_StdPeriph_Examples/TIM/OCToggle/main.c , STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/main.c , STM32F10x_StdPeriph_Examples/TIM/TimeBase/main.c , STM32F10x_StdPeriph_Examples/TIM/PWM_Output/main.c
  • ProtectedPages : STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/main.c
  • PSPMemAlloc : STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/main.c
  • PSPValue : STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/main.c
  • PWR_DBG : stm32f10x_ip_dbg.c


STM32F10x Standard Peripherals Firmware Library: Globals

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- r -

  • RCA : stm32_eval_sdio_sd.c
  • RCC_ClockFreq : STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/main.c
  • RCC_Clocks : STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/main.c , STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/main.c
  • RCC_DBG : stm32f10x_ip_dbg.c
  • rcv_inc : STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.c
  • ReceiveBuffer : STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/main.c
  • ReceivedData : STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/main.c
  • ReceivedFrame : STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/main.c , STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.c , stm32100b_eval_cec.c , stm32100e_eval_cec.c
  • ReceiveStatus : stm32100b_eval_cec.c , stm32100e_eval_cec.c
  • RecepErrorCode : STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.c , stm32100b_eval_cec.c , stm32100e_eval_cec.c
  • ret : STM32F10x_StdPeriph_Examples/CAN/LoopBack/main.c , STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_it.c
  • RTC_DBG : stm32f10x_ip_dbg.c
  • Rx1_Buffer : STM32F10x_StdPeriph_Examples/I2C/EEPROM/main.c
  • Rx2_Buffer : STM32F10x_StdPeriph_Examples/I2C/EEPROM/main.c
  • Rx_Buffer : STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/main.c
  • Rx_Idx : STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/main.c
  • RxBuffer : STM32F10x_StdPeriph_Examples/FSMC/NAND/main.c , STM32F10x_StdPeriph_Examples/FSMC/NOR/main.c , STM32F10x_StdPeriph_Examples/FSMC/SRAM/main.c , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/main.c , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Polling/main.c
  • RxBuffer1 : STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/main.c , STM32F10x_StdPeriph_Examples/USART/DMA_Polling/main.c , STM32F10x_StdPeriph_Examples/USART/HalfDuplex/main.c , STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c , STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Synchronous/main.c
  • RxBuffer2 : STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/main.c , STM32F10x_StdPeriph_Examples/USART/DMA_Polling/main.c , STM32F10x_StdPeriph_Examples/USART/HalfDuplex/main.c , STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c , STM32F10x_StdPeriph_Examples/USART/Synchronous/main.c , STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.c
  • RxBuffer_A : STM32F10x_StdPeriph_Examples/FSMC/OneNAND/main.c
  • RxBuffer_S : STM32F10x_StdPeriph_Examples/FSMC/OneNAND/main.c
  • RxCounter : STM32F10x_StdPeriph_Examples/USART/Polling/main.c , stm32100e_eval_cec.c , STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/main.c , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.c , stm32100b_eval_cec.c
  • RxCounter1 : STM32F10x_StdPeriph_Examples/USART/HalfDuplex/main.c , STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c , STM32F10x_StdPeriph_Examples/USART/Synchronous/main.c
  • RxCounter2 : STM32F10x_StdPeriph_Examples/USART/Synchronous/main.c , STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c , STM32F10x_StdPeriph_Examples/USART/HalfDuplex/main.c
  • RxIdx : STM32F10x_StdPeriph_Examples/I2S/Interrupt/main.c , STM32F10x_StdPeriph_Examples/SPI/CRC/main.c , STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/main.c , STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/main.c , STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/main.c , STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_it.c
  • RxMessage : STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_it.c


STM32F10x Standard Peripherals Firmware Library: Globals

  • File List
  • Globals
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- s -

  • SC_A2R : STM32F10x_StdPeriph_Examples/USART/Smartcard/main.c
  • SCB_DBG : stm32f10x_ip_dbg.c
  • SDCardInfo : stm32_eval_sdio_sd.c
  • SDCardOperation : STM32F10x_StdPeriph_Examples/SDIO/uSDCard/main.c
  • SDIO_CmdInitStructure : stm32_eval_sdio_sd.c
  • SDIO_DataInitStructure : stm32_eval_sdio_sd.c
  • SDIO_DBG : stm32f10x_ip_dbg.c
  • SDIO_InitStructure : stm32_eval_sdio_sd.c
  • SDSTATUS_Tab : stm32_eval_sdio_sd.c
  • sEEAddress : stm32_eval_i2c_ee.c , stm32l152_eval_i2c_ee.c
  • sEEDataNum : stm32_eval_i2c_ee.c , stm32l152_eval_i2c_ee.c
  • sEEDataReadPointer : stm32_eval_i2c_ee.c , stm32l152_eval_i2c_ee.c
  • sEEDataWritePointer : stm32_eval_i2c_ee.c , stm32l152_eval_i2c_ee.c
  • sEEDMA_InitStructure : stm32100e_eval.c , stm3210c_eval.c , stm32l152_eval.c
  • sEETimeout : stm32_eval_i2c_ee.c , stm32l152_eval_i2c_ee.c
  • send_inc : STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.c
  • SendFrame : stm32100b_eval_cec.c , stm32100e_eval_cec.c
  • SendStatus : stm32100b_eval_cec.c , stm32100e_eval_cec.c
  • shift : stm32l152_eval_glass_lcd.c
  • Sine12bit : STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/main.c
  • SMbusAlertOccurred : STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/main.c , STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/stm32f10x_it.c
  • SPI1_Buffer_Rx : STM32F10x_StdPeriph_Examples/SPI/CRC/main.c
  • SPI1_Buffer_Tx : STM32F10x_StdPeriph_Examples/SPI/CRC/main.c
  • SPI1_DBG : stm32f10x_ip_dbg.c
  • SPI2_Buffer_Rx : STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/main.c , STM32F10x_StdPeriph_Examples/SPI/CRC/main.c
  • SPI2_Buffer_Tx : STM32F10x_StdPeriph_Examples/SPI/CRC/main.c
  • SPI2_DBG : stm32f10x_ip_dbg.c
  • SPI3_Buffer_Tx : STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/main.c
  • SPI3_DBG : stm32f10x_ip_dbg.c
  • SPI_InitStructure : STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/main.c , STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/main.c , STM32F10x_StdPeriph_Examples/SPI/CRC/main.c , STM32F10x_StdPeriph_Examples/SPI/DMA/main.c , STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/main.c , STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/main.c
  • SPI_MASTER_Buffer_Rx : STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/main.c
  • SPI_MASTER_Buffer_Tx : STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/main.c , STM32F10x_StdPeriph_Examples/SPI/DMA/main.c , STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/main.c , STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.c
  • SPI_MASTERCRCValue : STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/main.c
  • SPI_SLAVE_Buffer_Rx : STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/main.c , STM32F10x_StdPeriph_Examples/SPI/DMA/main.c , STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/main.c , STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.c
  • SPI_SLAVE_Buffer_Tx : STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/main.c
  • SPI_SLAVECRCValue : STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/main.c
  • SPIy_Buffer_Rx : STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/main.c
  • SPIy_Buffer_Tx : STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/main.c
  • SPIz_Buffer_Rx : STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/main.c
  • SPIz_Buffer_Tx : STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/main.c
  • SRC_Buffer : STM32F10x_StdPeriph_Examples/TIM/DMA/main.c , STM32F10x_StdPeriph_Examples/TIM/DMABurst/main.c , STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_it.c
  • SRC_Const_Buffer : STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/main.c , STM32F10x_StdPeriph_Examples/DMA/FSMC/main.c
  • status : STM32F10x_StdPeriph_Examples/FSMC/NAND/main.c
  • Status : STM32F10x_StdPeriph_Examples/FSMC/OneNAND/main.c , STM32F10x_StdPeriph_Examples/SDIO/uSDCard/main.c
  • step : STM32F10x_StdPeriph_Examples/TIM/6Steps/stm32f10x_it.c
  • StopCondition : stm32_eval_sdio_sd.c
  • SystemCoreClock : Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/DMA/FSMC/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/CortexM3/MPU/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/CortexM3/BitBand/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/CAN/Networking/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/CAN/LoopBack/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/CAN/DualCAN/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/BKP/Tamper/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/BKP/Backup_Data/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/FLASH/Program/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/system_stm32f10x.c , system_stm32f10x.h , Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/Synchronous/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/FSMC/OneNAND/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Output/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/DMABurst/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/Polling/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/SysTick/TimeBase/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/TimeBase/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/I2C/IOExpander/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/OCInactive/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/OCActive/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/OCToggle/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/Smartcard/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Input/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/Printf/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/Interrupt/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/HalfDuplex/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Template/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/SPI/CRC/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/MultiProcessor/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/DMA_Polling/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/FSMC/NOR/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/I2S/Interrupt/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/InputCapture/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/PWR/PVD/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/PWR/STOP/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/OnePulse/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/SDIO/uSDCard/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/SPI/DMA/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/6Steps/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/GPIO/IOToggle/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/I2C/EEPROM/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/PWR/STANDBY/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/FSMC/NAND/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/TIM/DMA/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/RTC/Calendar/system_stm32f10x.c , Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM/system_stm32f10x.c
  • SysTick_DBG : stm32f10x_ip_dbg.c


STM32F10x Standard Peripherals Firmware Library: Globals

  • File List
  • Globals
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- t -

  • Tab : STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/main.c
  • TabAddr : STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/main.c
  • TempCelsiusDisplay : STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/main.c
  • TempFahrenheitDisplay : STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/main.c
  • TempValue : STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/main.c
  • TempValueCelsius : STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/main.c
  • TempValueFahrenheit : STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/main.c
  • TestRx : STM32F10x_StdPeriph_Examples/CAN/LoopBack/main.c
  • TestStatus : STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_it.c
  • TextColor : stm32100b_eval_lcd.c , stm32100e_eval_lcd.c , stm3210b_eval_lcd.c , stm3210c_eval_lcd.c , stm3210e_eval_lcd.c , stm32l152_eval_lcd.c
  • ThreadMode : STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/main.c
  • TIM15_DBG : stm32f10x_ip_dbg.c
  • TIM16_DBG : stm32f10x_ip_dbg.c
  • TIM17_DBG : stm32f10x_ip_dbg.c
  • TIM1_DBG : stm32f10x_ip_dbg.c
  • TIM2_DBG : stm32f10x_ip_dbg.c
  • TIM3_DBG : stm32f10x_ip_dbg.c
  • TIM3Freq : STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_it.c
  • TIM4_DBG : stm32f10x_ip_dbg.c
  • TIM5_DBG : stm32f10x_ip_dbg.c
  • TIM6_DBG : stm32f10x_ip_dbg.c
  • TIM7_DBG : stm32f10x_ip_dbg.c
  • TIM8_DBG : stm32f10x_ip_dbg.c
  • TIM_BDTRInitStructure : STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/main.c , STM32F10x_StdPeriph_Examples/TIM/6Steps/main.c , STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/main.c , STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/main.c
  • TIM_ICInitStructure : STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/main.c , STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/main.c , STM32F10x_StdPeriph_Examples/TIM/InputCapture/main.c , STM32F10x_StdPeriph_Examples/TIM/OnePulse/main.c , STM32F10x_StdPeriph_Examples/TIM/PWM_Input/main.c
  • TIM_OCInitStructure : STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/main.c , STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/main.c , STM32F10x_StdPeriph_Examples/TIM/6Steps/main.c , STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/main.c , STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/main.c , STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/main.c , STM32F10x_StdPeriph_Examples/TIM/DMA/main.c , STM32F10x_StdPeriph_Examples/TIM/DMABurst/main.c , STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/main.c , STM32F10x_StdPeriph_Examples/TIM/OCActive/main.c , STM32F10x_StdPeriph_Examples/TIM/OCInactive/main.c , STM32F10x_StdPeriph_Examples/TIM/OCToggle/main.c , STM32F10x_StdPeriph_Examples/TIM/OnePulse/main.c , STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/main.c , STM32F10x_StdPeriph_Examples/TIM/PWM_Output/main.c , STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/main.c , STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/main.c , STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/main.c , STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/main.c , STM32F10x_StdPeriph_Examples/TIM/TimeBase/main.c
  • TIM_TimeBaseStructure : STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/main.c , STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/main.c , STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/main.c , STM32F10x_StdPeriph_Examples/TIM/DMA/main.c , STM32F10x_StdPeriph_Examples/TIM/DMABurst/main.c , STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/main.c , STM32F10x_StdPeriph_Examples/TIM/OCActive/main.c , STM32F10x_StdPeriph_Examples/TIM/OCInactive/main.c , STM32F10x_StdPeriph_Examples/TIM/OCToggle/main.c , STM32F10x_StdPeriph_Examples/TIM/OnePulse/main.c , STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/main.c , STM32F10x_StdPeriph_Examples/TIM/PWM_Output/main.c , STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/main.c , STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/main.c , STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/main.c , STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/main.c , STM32F10x_StdPeriph_Examples/TIM/TimeBase/main.c , STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/main.c , STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/main.c , STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/main.c , STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/main.c , STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/main.c , STM32F10x_StdPeriph_Examples/TIM/6Steps/main.c
  • TimeDisplay : STM32F10x_StdPeriph_Examples/RTC/Calendar/main.c , STM32F10x_StdPeriph_Examples/RTC/Calendar/stm32f10x_it.c
  • TimerPeriod : STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/main.c , STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/main.c , STM32F10x_StdPeriph_Examples/TIM/DMA/main.c
  • TimingDelay : STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/main.c , STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/main.c , STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/main.c , STM32F10x_StdPeriph_Examples/PWR/STOP/main.c , STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SysTick/TimeBase/main.c , STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/main.c , STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_it.c
  • tmpCC4 : STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_it.c
  • TransErrorCode : STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.c , stm32100b_eval_cec.c , stm32100e_eval_cec.c
  • TransferEnd : stm32_eval_sdio_sd.c
  • TransferError : stm32_eval_sdio_sd.c
  • TransferStatus : STM32F10x_StdPeriph_Examples/DMA/FSMC/main.c , STM32F10x_StdPeriph_Examples/USART/Polling/main.c , STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/main.c , STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/main.c , STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/main.c , STM32F10x_StdPeriph_Examples/SPI/DMA/main.c , STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/main.c
  • TransferStatus1 : STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c , STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/main.c , STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/main.c , STM32F10x_StdPeriph_Examples/I2C/EEPROM/main.c , STM32F10x_StdPeriph_Examples/I2S/Interrupt/main.c , STM32F10x_StdPeriph_Examples/SDIO/uSDCard/main.c , STM32F10x_StdPeriph_Examples/SPI/CRC/main.c , STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/main.c , STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/main.c , STM32F10x_StdPeriph_Examples/USART/DMA_Polling/main.c , STM32F10x_StdPeriph_Examples/USART/HalfDuplex/main.c , STM32F10x_StdPeriph_Examples/USART/Synchronous/main.c , STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/main.c
  • TransferStatus2 : STM32F10x_StdPeriph_Examples/SDIO/uSDCard/main.c , STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/main.c , STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/main.c , STM32F10x_StdPeriph_Examples/USART/DMA_Polling/main.c , STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c , STM32F10x_StdPeriph_Examples/USART/Synchronous/main.c , STM32F10x_StdPeriph_Examples/SPI/CRC/main.c , STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/main.c , STM32F10x_StdPeriph_Examples/I2S/Interrupt/main.c , STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/main.c , STM32F10x_StdPeriph_Examples/USART/HalfDuplex/main.c , STM32F10x_StdPeriph_Examples/I2C/EEPROM/main.c , STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/main.c
  • TransferStatus3 : STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/main.c , STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/main.c
  • TransferStatus4 : STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/main.c
  • TransmitBuffer : STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/main.c
  • TS_State : stm3210c_eval_ioe.c , stm32100e_eval_ioe.c
  • Tx1_Buffer : STM32F10x_StdPeriph_Examples/I2C/EEPROM/main.c
  • Tx2_Buffer : STM32F10x_StdPeriph_Examples/I2C/EEPROM/main.c
  • Tx_Buffer : STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/main.c
  • Tx_Idx : STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/main.c
  • TxBuffer : STM32F10x_StdPeriph_Examples/USART/Polling/main.c , STM32F10x_StdPeriph_Examples/FSMC/SRAM/main.c , STM32F10x_StdPeriph_Examples/FSMC/OneNAND/main.c , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/main.c , STM32F10x_StdPeriph_Examples/FSMC/NAND/main.c , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/FSMC/NOR/main.c
  • TxBuffer1 : STM32F10x_StdPeriph_Examples/USART/Synchronous/main.c , STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c , STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/main.c , STM32F10x_StdPeriph_Examples/USART/HalfDuplex/main.c , STM32F10x_StdPeriph_Examples/USART/DMA_Polling/main.c
  • TxBuffer2 : STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/main.c , STM32F10x_StdPeriph_Examples/USART/HalfDuplex/main.c , STM32F10x_StdPeriph_Examples/USART/Synchronous/main.c , STM32F10x_StdPeriph_Examples/USART/DMA_Polling/main.c , STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c , STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.c
  • TxCounter : stm32100e_eval_cec.c , STM32F10x_StdPeriph_Examples/USART/Polling/main.c , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/main.c , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.c , stm32100b_eval_cec.c
  • TxCounter1 : STM32F10x_StdPeriph_Examples/USART/HalfDuplex/main.c , STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c , STM32F10x_StdPeriph_Examples/USART/Synchronous/main.c , STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.c
  • TxCounter2 : STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/USART/HalfDuplex/main.c , STM32F10x_StdPeriph_Examples/USART/Synchronous/main.c , STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c
  • TxIdx : STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/main.c , STM32F10x_StdPeriph_Examples/SPI/CRC/main.c , STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/SPI/DMA/main.c , STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/main.c , STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_it.c , STM32F10x_StdPeriph_Examples/I2S/Interrupt/main.c , STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/main.c
  • TxMessage : STM32F10x_StdPeriph_Examples/CAN/Networking/main.c , STM32F10x_StdPeriph_Examples/CAN/DualCAN/main.c


STM32F10x Standard Peripherals Firmware Library: Globals

  • File List
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- u -

  • UART4_DBG : stm32f10x_ip_dbg.c
  • UART5_DBG : stm32f10x_ip_dbg.c
  • USART1_DBG : stm32f10x_ip_dbg.c
  • USART2_DBG : stm32f10x_ip_dbg.c
  • USART3_DBG : stm32f10x_ip_dbg.c
  • USART_ClockInitStructure : STM32F10x_StdPeriph_Examples/USART/Smartcard/main.c , STM32F10x_StdPeriph_Examples/USART/Synchronous/main.c
  • USART_InitStructure : STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/main.c , STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/main.c , STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/main.c , STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/main.c , STM32F10x_StdPeriph_Examples/USART/HalfDuplex/main.c , STM32F10x_StdPeriph_Examples/USART/DMA_Polling/main.c , STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/main.c , STM32F10x_StdPeriph_Examples/RTC/Calendar/main.c , STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/main.c , STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/main.c , STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/main.c , STM32F10x_StdPeriph_Examples/USART/Polling/main.c , STM32F10x_StdPeriph_Examples/USART/Synchronous/main.c , STM32F10x_StdPeriph_Examples/USART/Smartcard/main.c , STM32F10x_StdPeriph_Template/main.c , STM32F10x_StdPeriph_Examples/USART/MultiProcessor/main.c , STM32F10x_StdPeriph_Examples/USART/Printf/main.c


STM32F10x Standard Peripherals Firmware Library: Globals

  • File List
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- v -

  • Var : STM32F10x_StdPeriph_Examples/CortexM3/BitBand/main.c
  • VarAddr : STM32F10x_StdPeriph_Examples/CortexM3/BitBand/main.c
  • VarBitValue : STM32F10x_StdPeriph_Examples/CortexM3/BitBand/main.c


STM32F10x Standard Peripherals Firmware Library: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
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  • WriteReadAddr : STM32F10x_StdPeriph_Examples/FSMC/NAND/main.c
  • WriteReadStatus : STM32F10x_StdPeriph_Examples/FSMC/NAND/main.c , STM32F10x_StdPeriph_Examples/FSMC/SRAM/main.c , STM32F10x_StdPeriph_Examples/FSMC/NOR/main.c
  • WRPR_Value : STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/main.c
  • WWDG_DBG : stm32f10x_ip_dbg.c


STM32F10x Standard Peripherals Firmware Library: ADC

Modules

ADC

STM32F10x_StdPeriph_Driver

ADC driver modules. More...

Modules

ADC_Exported_Types
ADC_Exported_Constants
ADC_Exported_Macros
ADC_Exported_Functions
ADC_Private_TypesDefinitions
ADC_Private_Defines
ADC_Private_Macros
ADC_Private_Variables
ADC_Private_FunctionPrototypes
ADC_Private_Functions

Detailed Description

ADC driver modules.


STM32F10x Standard Peripherals Firmware Library: ADC_Exported_Types

Data Structures

ADC_Exported_Types

ADC

Data Structures

struct ADC_InitTypeDef
ADC Init structure definition. More...


STM32F10x Standard Peripherals Firmware Library: BKP

Modules

BKP

STM32F10x_StdPeriph_Driver

BKP driver modules. More...

Modules

BKP_Exported_Types
BKP_Exported_Constants
BKP_Exported_Macros
BKP_Exported_Functions
BKP_Private_TypesDefinitions
BKP_Private_Defines
BKP_Private_Macros
BKP_Private_Variables
BKP_Private_FunctionPrototypes
BKP_Private_Functions

Detailed Description

BKP driver modules.


STM32F10x Standard Peripherals Firmware Library: BKP_Exported_Constants

Modules

BKP_Exported_Constants

BKP

Modules

Tamper_Pin_active_level
RTC_output_source_to_output_on_the_Tamper_pin
Data_Backup_Register


STM32F10x Standard Peripherals Firmware Library: CAN

Modules

CAN

STM32F10x_StdPeriph_Driver

CAN driver modules. More...

Modules

CAN_Exported_Types
CAN_Exported_Constants
CAN_Exported_Macros
CAN_Exported_Functions
CAN_Private_TypesDefinitions
CAN_Private_Defines
CAN_Private_Macros
CAN_Private_Variables
CAN_Private_FunctionPrototypes
CAN_Private_Functions

Detailed Description

CAN driver modules.


STM32F10x Standard Peripherals Firmware Library: CAN_Exported_Constants

Modules

CAN_Exported_Constants

CAN

Modules

CAN_sleep_constants
CAN_Mode
CAN_Operating_Mode
CAN_Mode_Status
CAN_synchronisation_jump_width
CAN_time_quantum_in_bit_segment_1
CAN_time_quantum_in_bit_segment_2
CAN_clock_prescaler
CAN_filter_number
CAN_filter_mode
CAN_filter_scale
CAN_filter_FIFO
Start_bank_filter_for_slave_CAN
CAN_Tx
CAN_identifier_type
CAN_remote_transmission_request
CAN_transmit_constants
CAN_receive_FIFO_number_constants
CAN_wake_up_constants
CAN_Error_Code_constants
CAN_flags
CAN_interrupts
CAN_Legacy


STM32F10x Standard Peripherals Firmware Library: CEC

Modules

CEC

STM32F10x_StdPeriph_Driver

CEC driver modules. More...

Modules

CEC_Exported_Types
CEC_Exported_Constants
CEC_Exported_Macros
CEC_Exported_Functions
CEC_Private_TypesDefinitions
CEC_Private_Defines
CEC_Private_Macros
CEC_Private_Variables
CEC_Private_FunctionPrototypes
CEC_Private_Functions

Detailed Description

CEC driver modules.


STM32F10x Standard Peripherals Firmware Library: CEC_Exported_Constants

Modules

CEC_Exported_Constants

CEC

Modules

CEC_BitTiming_Mode
CEC_BitPeriod_Mode
CEC_interrupts_definition
CEC_Own_Address
CEC_Prescaler
CEC_flags_definition


STM32F10x Standard Peripherals Firmware Library: CEC_Exported_Types

Data Structures

CEC_Exported_Types

CEC

Data Structures

struct CEC_InitTypeDef
CEC Init structure definition. More...


STM32F10x Standard Peripherals Firmware Library: CMSIS

Modules

CMSIS

Modules

Stm32f10x
Stm32f10x_system


STM32F10x Standard Peripherals Firmware Library: Common

Modules

Common

STM32_EVAL

Modules

FONTS

This file includes the Fonts driver of STM32-EVAL boards.

STM32_EVAL_I2C_EE

This file includes the I2C EEPROM driver of STM32-EVAL boards.

STM32_EVAL_I2C_TSENSOR

This file includes the LM75 Temperature Sensor driver of STM32-EVAL boards.

STM32_EVAL_SDIO_SD

This file provides all the SD Card driver firmware functions.

STM32_EVAL_SPI_FLASH

This file includes the M25Pxxx SPI FLASH driver of STM32-EVAL boards.

STM32_EVAL_SPI_SD

This file includes the SD card driver of STM32-EVAL boards.


STM32F10x Standard Peripherals Firmware Library: CRC

Modules

CRC

STM32F10x_StdPeriph_Driver

CRC driver modules. More...

Modules

CRC_Exported_Types
CRC_Exported_Constants
CRC_Exported_Macros
CRC_Exported_Functions
CRC_Private_TypesDefinitions
CRC_Private_Defines
CRC_Private_Macros
CRC_Private_Variables
CRC_Private_FunctionPrototypes
CRC_Private_Functions

Detailed Description

CRC driver modules.


STM32F10x Standard Peripherals Firmware Library: DAC

Modules

DAC

STM32F10x_StdPeriph_Driver

DAC driver modules. More...

Modules

DAC_Exported_Types
DAC_Exported_Constants
DAC_Exported_Macros
DAC_Exported_Functions
DAC_Private_TypesDefinitions
DAC_Private_Defines
DAC_Private_Macros
DAC_Private_Variables
DAC_Private_FunctionPrototypes
DAC_Private_Functions

Detailed Description

DAC driver modules.


STM32F10x Standard Peripherals Firmware Library: DAC_Exported_Constants

Modules

DAC_Exported_Constants

DAC

Modules

DAC_trigger_selection
DAC_wave_generation
DAC_lfsrunmask_triangleamplitude
DAC_output_buffer
DAC_Channel_selection
DAC_data_alignment
DAC_data


STM32F10x Standard Peripherals Firmware Library: DAC_Exported_Types

Data Structures

DAC_Exported_Types

DAC

Data Structures

struct DAC_InitTypeDef
DAC Init structure definition. More...


STM32F10x Standard Peripherals Firmware Library: DBGMCU

Modules

DBGMCU

STM32F10x_StdPeriph_Driver

DBGMCU driver modules. More...

Modules

DBGMCU_Exported_Types
DBGMCU_Exported_Constants
DBGMCU_Exported_Macros
DBGMCU_Exported_Functions
DBGMCU_Private_TypesDefinitions
DBGMCU_Private_Defines
DBGMCU_Private_Macros
DBGMCU_Private_Variables
DBGMCU_Private_FunctionPrototypes
DBGMCU_Private_Functions

Detailed Description

DBGMCU driver modules.


STM32F10x Standard Peripherals Firmware Library: DMA

Modules

DMA

STM32F10x_StdPeriph_Driver

DMA driver modules. More...

Modules

DMA_Exported_Types
DMA_Exported_Constants
DMA_Exported_Macros
DMA_Exported_Functions
DMA_Private_TypesDefinitions
DMA_Private_Defines
DMA_Private_Macros
DMA_Private_Variables
DMA_Private_FunctionPrototypes
DMA_Private_Functions

Detailed Description

DMA driver modules.


STM32F10x Standard Peripherals Firmware Library: DMA_Exported_Types

Data Structures

DMA_Exported_Types

DMA

Data Structures

struct DMA_InitTypeDef
DMA Init structure definition. More...


STM32F10x Standard Peripherals Firmware Library: Exported_constants

Modules

Exported_constants

Stm32f10x

Modules

Peripheral_Registers_Bits_Definition


STM32F10x Standard Peripherals Firmware Library: EXTI

Modules

EXTI

STM32F10x_StdPeriph_Driver

EXTI driver modules. More...

Modules

EXTI_Exported_Types
EXTI_Exported_Constants
EXTI_Exported_Macros
EXTI_Exported_Functions
EXTI_Private_TypesDefinitions
EXTI_Private_Defines
EXTI_Private_Macros
EXTI_Private_Variables
EXTI_Private_FunctionPrototypes
EXTI_Private_Functions

Detailed Description

EXTI driver modules.


STM32F10x Standard Peripherals Firmware Library: EXTI_Exported_Constants

Modules

EXTI_Exported_Constants

EXTI

Modules

EXTI_Lines


STM32F10x Standard Peripherals Firmware Library: FLASH

Modules

FLASH

STM32F10x_StdPeriph_Driver

FLASH driver modules. More...

Modules

FLASH_Exported_Types
FLASH_Exported_Constants
FLASH_Exported_Macros
FLASH_Exported_Functions
FLASH_Private_TypesDefinitions
FLASH_Private_Defines
FLASH_Private_Macros
FLASH_Private_Variables
FLASH_Private_FunctionPrototypes
FLASH_Private_Functions

Detailed Description

FLASH driver modules.


STM32F10x Standard Peripherals Firmware Library: FLASH_Exported_Constants

Modules

FLASH_Exported_Constants

FLASH

Modules

Flash_Latency
Half_Cycle_Enable_Disable
Prefetch_Buffer_Enable_Disable
Option_Bytes_Write_Protection
Option_Bytes_IWatchdog
Option_Bytes_nRST_STOP
Option_Bytes_nRST_STDBY
FLASH_Interrupts
FLASH_Flags


STM32F10x Standard Peripherals Firmware Library: FONTS

Modules

FONTS

Common

This file includes the Fonts driver of STM32-EVAL boards. More...

Modules

FONTS_Private_Types
FONTS_Private_Defines
FONTS_Private_Macros
FONTS_Private_Variables
FONTS_Private_Function_Prototypes
FONTS_Private_Functions
FONTS_Exported_Types
FONTS_Exported_Constants
FONTS_Exported_Macros
FONTS_Exported_Functions

Detailed Description

This file includes the Fonts driver of STM32-EVAL boards.


STM32F10x Standard Peripherals Firmware Library: FSMC

Modules

FSMC

STM32F10x_StdPeriph_Driver

FSMC driver modules. More...

Modules

FSMC_Exported_Types
FSMC_Exported_Constants
FSMC_Exported_Macros
FSMC_Exported_Functions
FSMC_Private_TypesDefinitions
FSMC_Private_Defines
FSMC_Private_Macros
FSMC_Private_Variables
FSMC_Private_FunctionPrototypes
FSMC_Private_Functions

Detailed Description

FSMC driver modules.


STM32F10x Standard Peripherals Firmware Library: FSMC_Exported_Types

Data Structures

FSMC_Exported_Types

FSMC

Data Structures

struct | FSMC_NAND_PCCARDTimingInitTypeDef
Timing parameters For FSMC NAND and PCCARD Banks. More...
struct | FSMC_NANDInitTypeDef
FSMC NAND Init structure definition. More...
struct | FSMC_NORSRAMInitTypeDef
FSMC NOR/SRAM Init structure definition. More...
struct | FSMC_NORSRAMTimingInitTypeDef
Timing parameters For NOR/SRAM Banks. More...
struct | FSMC_PCCARDInitTypeDef
FSMC PCCARD Init structure definition. More...


STM32F10x Standard Peripherals Firmware Library: GPIO

Modules

GPIO

STM32F10x_StdPeriph_Driver

GPIO driver modules. More...

Modules

GPIO_Exported_Types
GPIO_Exported_Constants
GPIO_Exported_Macros
GPIO_Exported_Functions
GPIO_Private_TypesDefinitions
GPIO_Private_Defines
GPIO_Private_Macros
GPIO_Private_Variables
GPIO_Private_FunctionPrototypes
GPIO_Private_Functions

Detailed Description

GPIO driver modules.


STM32F10x Standard Peripherals Firmware Library: GPIO_Exported_Constants

Modules

GPIO_Exported_Constants

GPIO

Modules

GPIO_pins_define
GPIO_Remap_define
GPIO_Port_Sources
GPIO_Pin_sources
Ethernet_Media_Interface


STM32F10x Standard Peripherals Firmware Library: I2C

Modules

I2C

STM32F10x_StdPeriph_Driver

I2C driver modules. More...

Modules

I2C_Exported_Types
I2C_Exported_Constants
I2C_Exported_Macros
I2C_Exported_Functions
I2C_Private_TypesDefinitions
I2C_Private_Defines
I2C_Private_Macros
I2C_Private_Variables
I2C_Private_FunctionPrototypes
I2C_Private_Functions

Detailed Description

I2C driver modules.


STM32F10x Standard Peripherals Firmware Library: I2C_Exported_Types

Data Structures

I2C_Exported_Types

I2C

Data Structures

struct I2C_InitTypeDef
I2C Init structure definition. More...


STM32F10x Standard Peripherals Firmware Library: IWDG

Modules

IWDG

STM32F10x_StdPeriph_Driver

IWDG driver modules. More...

Modules

IWDG_Exported_Types
IWDG_Exported_Constants
IWDG_Exported_Macros
IWDG_Exported_Functions
IWDG_Private_TypesDefinitions
IWDG_Private_Defines
IWDG_Private_Macros
IWDG_Private_Variables
IWDG_Private_FunctionPrototypes
IWDG_Private_Functions

Detailed Description

IWDG driver modules.


STM32F10x Standard Peripherals Firmware Library: IWDG_Exported_Constants

Modules

IWDG_Exported_Constants

IWDG

Modules

IWDG_WriteAccess
IWDG_prescaler
IWDG_Flag


STM32F10x Standard Peripherals Firmware Library: MISC

Modules

MISC

STM32F10x_StdPeriph_Driver

MISC driver modules. More...

Modules

MISC_Exported_Types
NVIC_Priority_Table
MISC_Exported_Constants
MISC_Exported_Macros
MISC_Exported_Functions
MISC_Private_TypesDefinitions
MISC_Private_Defines
MISC_Private_Macros
MISC_Private_Variables
MISC_Private_FunctionPrototypes
MISC_Private_Functions

Detailed Description

MISC driver modules.


STM32F10x Standard Peripherals Firmware Library: MISC_Exported_Constants

Modules

MISC_Exported_Constants

MISC

Modules

Vector_Table_Base
System_Low_Power
Preemption_Priority_Group
SysTick_clock_source


STM32F10x Standard Peripherals Firmware Library: MISC_Exported_Types

Data Structures

MISC_Exported_Types

MISC

Data Structures

struct NVIC_InitTypeDef
NVIC Init Structure definition. More...


STM32F10x Standard Peripherals Firmware Library: NAND_PCCARD_Controller

Modules

NAND_PCCARD_Controller

FSMC_Exported_Constants

Modules

FSMC_Wait_feature
FSMC_ECC
FSMC_ECC_Page_Size
FSMC_TCLR_Setup_Time
FSMC_TAR_Setup_Time
FSMC_Setup_Time
FSMC_Wait_Setup_Time
FSMC_Hold_Setup_Time
FSMC_HiZ_Setup_Time
FSMC_Interrupt_sources
FSMC_Flags


STM32F10x Standard Peripherals Firmware Library: NOR_SRAM_Controller

Modules

NOR_SRAM_Controller

FSMC_Exported_Constants

Modules

FSMC_Data_Address_Bus_Multiplexing
FSMC_Memory_Type
FSMC_Data_Width
FSMC_Burst_Access_Mode
FSMC_AsynchronousWait
FSMC_Wait_Signal_Polarity
FSMC_Wrap_Mode
FSMC_Wait_Timing
FSMC_Write_Operation
FSMC_Wait_Signal
FSMC_Extended_Mode
FSMC_Write_Burst
FSMC_Address_Setup_Time
FSMC_Address_Hold_Time
FSMC_Data_Setup_Time
FSMC_Bus_Turn_around_Duration
FSMC_CLK_Division
FSMC_Data_Latency
FSMC_Access_Mode


STM32F10x Standard Peripherals Firmware Library: Peripheral_registers_structures

Data Structures

Peripheral_registers_structures

Stm32f10x

Data Structures

struct | ADC_TypeDef
Analog to Digital Converter. More...
struct | AFIO_TypeDef
Alternate Function I/O. More...
struct | BKP_TypeDef
Backup Registers. More...
struct | CAN_FIFOMailBox_TypeDef
Controller Area Network FIFOMailBox. More...
struct | CAN_FilterRegister_TypeDef
Controller Area Network FilterRegister. More...
struct | CAN_TxMailBox_TypeDef
Controller Area Network TxMailBox. More...
struct | CAN_TypeDef
Controller Area Network. More...
struct | CEC_TypeDef
Consumer Electronics Control (CEC) More...
struct | CRC_TypeDef
CRC calculation unit. More...
struct | DAC_TypeDef
Digital to Analog Converter. More...
struct | DBGMCU_TypeDef
Debug MCU. More...
struct | DMA_Channel_TypeDef
DMA Controller. More...
struct | DMA_TypeDef
struct | ETH_TypeDef
Ethernet MAC. More...
struct | EXTI_TypeDef
External Interrupt/Event Controller. More...
struct | FLASH_TypeDef
FLASH Registers. More...
struct | FSMC_Bank1_TypeDef
Flexible Static Memory Controller. More...
struct | FSMC_Bank1E_TypeDef
Flexible Static Memory Controller Bank1E. More...
struct | FSMC_Bank2_TypeDef
Flexible Static Memory Controller Bank2. More...
struct | FSMC_Bank3_TypeDef
Flexible Static Memory Controller Bank3. More...
struct | FSMC_Bank4_TypeDef
Flexible Static Memory Controller Bank4. More...
struct | GPIO_TypeDef
General Purpose I/O. More...
struct | I2C_TypeDef
Inter Integrated Circuit Interface. More...
struct | IWDG_TypeDef
Independent WATCHDOG. More...
struct | OB_TypeDef
Option Bytes Registers. More...
struct | PWR_TypeDef
Power Control. More...
struct | RCC_TypeDef
Reset and Clock Control. More...
struct | RTC_TypeDef
Real-Time Clock. More...
struct | SDIO_TypeDef
SD host Interface. More...
struct | SPI_TypeDef
Serial Peripheral Interface. More...
struct | TIM_TypeDef
TIM. More...
struct | USART_TypeDef
Universal Synchronous Asynchronous Receiver Transmitter. More...
struct | WWDG_TypeDef
Window WATCHDOG. More...


STM32F10x Standard Peripherals Firmware Library: PWR

Modules

PWR

STM32F10x_StdPeriph_Driver

PWR driver modules. More...

Modules

PWR_Exported_Types
PWR_Exported_Constants
PWR_Exported_Macros
PWR_Exported_Functions
PWR_Private_TypesDefinitions
PWR_Private_Defines
PWR_Private_Macros
PWR_Private_Variables
PWR_Private_FunctionPrototypes
PWR_Private_Functions

Detailed Description

PWR driver modules.


STM32F10x Standard Peripherals Firmware Library: PWR_Exported_Constants

Modules

PWR_Exported_Constants

PWR

Modules

PVD_detection_level
Regulator_state_is_STOP_mode
STOP_mode_entry
PWR_Flag


STM32F10x Standard Peripherals Firmware Library: RCC

Modules

RCC

STM32F10x_StdPeriph_Driver

RCC driver modules. More...

Modules

RCC_Exported_Types
RCC_Exported_Constants
RCC_Exported_Macros
RCC_Exported_Functions
RCC_Private_TypesDefinitions
RCC_Private_Defines
RCC_Private_Macros
RCC_Private_Variables
RCC_Private_FunctionPrototypes
RCC_Private_Functions

Detailed Description

RCC driver modules.


STM32F10x Standard Peripherals Firmware Library: RCC_Exported_Constants

Modules

RCC_Exported_Constants

RCC

Modules

HSE_configuration
PLL_entry_clock_source
PLL_multiplication_factor
PREDIV1_division_factor
PREDIV1_clock_source
System_clock_source
AHB_clock_source
APB1_APB2_clock_source
RCC_Interrupt_source
USB_Device_clock_source
ADC_clock_source
LSE_configuration
RTC_clock_source
AHB_peripheral
APB2_peripheral
APB1_peripheral
Clock_source_to_output_on_MCO_pin
RCC_Flag


STM32F10x Standard Peripherals Firmware Library: RCC_Exported_Types

Data Structures

RCC_Exported_Types

RCC

Data Structures

struct RCC_ClocksTypeDef


STM32F10x Standard Peripherals Firmware Library: RTC

Modules

RTC

STM32F10x_StdPeriph_Driver

RTC driver modules. More...

Modules

RTC_Exported_Types
RTC_Exported_Constants
RTC_Exported_Macros
RTC_Exported_Functions
RTC_Private_TypesDefinitions
RTC_Private_Defines
RTC_Private_Macros
RTC_Private_Variables
RTC_Private_FunctionPrototypes
RTC_Private_Functions

Detailed Description

RTC driver modules.


STM32F10x Standard Peripherals Firmware Library: RTC_Exported_Constants

Modules

RTC_Exported_Constants

RTC

Modules

RTC_interrupts_define
RTC_interrupts_flags


STM32F10x Standard Peripherals Firmware Library: SDIO

Modules

SDIO

STM32F10x_StdPeriph_Driver

SDIO driver modules. More...

Modules

SDIO_Exported_Types
SDIO_Exported_Constants
SDIO_Exported_Macros
SDIO_Exported_Functions
SDIO_Private_TypesDefinitions
SDIO_Private_Defines
SDIO_Private_Macros
SDIO_Private_Variables
SDIO_Private_FunctionPrototypes
SDIO_Private_Functions

Detailed Description

SDIO driver modules.


STM32F10x Standard Peripherals Firmware Library: SDIO_Exported_Constants

Modules

SDIO_Exported_Constants

SDIO

Modules

SDIO_Clock_Edge
SDIO_Clock_Bypass
SDIO_Clock_Power_Save
SDIO_Bus_Wide
SDIO_Hardware_Flow_Control
SDIO_Power_State
SDIO_Interrupt_sources
SDIO_Command_Index
SDIO_Response_Type
SDIO_Wait_Interrupt_State
SDIO_CPSM_State
SDIO_Response_Registers
SDIO_Data_Length
SDIO_Data_Block_Size
SDIO_Transfer_Direction
SDIO_Transfer_Type
SDIO_DPSM_State
SDIO_Flags
SDIO_Read_Wait_Mode


STM32F10x Standard Peripherals Firmware Library: SDIO_Exported_Types

Data Structures

SDIO_Exported_Types

SDIO

Data Structures

struct | SDIO_CmdInitTypeDef
struct | SDIO_DataInitTypeDef
struct | SDIO_InitTypeDef


STM32F10x Standard Peripherals Firmware Library: SPI

Modules

SPI

STM32F10x_StdPeriph_Driver

SPI driver modules. More...

Modules

SPI_Exported_Types
SPI_Exported_Constants
SPI_Exported_Macros
SPI_Exported_Functions
SPI_Private_TypesDefinitions
SPI_Private_Defines
SPI_Private_Macros
SPI_Private_Variables
SPI_Private_FunctionPrototypes
SPI_Private_Functions

Detailed Description

SPI driver modules.


STM32F10x Standard Peripherals Firmware Library: SPI_Exported_Types

Data Structures

SPI_Exported_Types

SPI

Data Structures

struct | I2S_InitTypeDef
I2S Init structure definition. More...
struct | SPI_InitTypeDef
SPI Init structure definition. More...


STM32F10x Standard Peripherals Firmware Library: STM32_EVAL

Modules

STM32_EVAL

Utilities

This file provides firmware functions to manage Leds, push-buttons, COM ports and low level HW resources initialization of the different modules available on STM32 Evaluation Boards from STMicroelectronics. More...

Modules

STM32_EVAL_Abstraction_Layer
Common
STM32100B_EVAL
STM32100E_EVAL
STM3210B_EVAL
STM3210C_EVAL
STM3210E_EVAL
STM32L152_EVAL

Detailed Description

This file provides firmware functions to manage Leds, push-buttons, COM ports and low level HW resources initialization of the different modules available on STM32 Evaluation Boards from STMicroelectronics.


STM32F10x Standard Peripherals Firmware Library: STM32_EVAL_Abstraction_Layer

Modules

STM32_EVAL_Abstraction_Layer

STM32_EVAL

Modules

STM32_EVAL_Private_TypesDefinitions
STM32_EVAL_Private_Defines
STM32_EVAL_Private_Macros
STM32_EVAL_Private_Variables
STM32_EVAL_Private_FunctionPrototypes
STM32_EVAL_Private_Functions
STM32_EVAL_HARDWARE_RESOURCES
STM32_EVAL_Exported_Types
STM32_EVAL_Exported_Constants
STM32_EVAL_Exported_Macros
STM32_EVAL_Exported_Functions


STM32F10x Standard Peripherals Firmware Library: STM32_EVAL_I2C_EE

Modules

STM32_EVAL_I2C_EE

Common

This file includes the I2C EEPROM driver of STM32-EVAL boards. More...

Modules

STM32_EVAL_I2C_EE_Private_Types
STM32_EVAL_I2C_EE_Private_Defines
STM32_EVAL_I2C_EE_Private_Macros
STM32_EVAL_I2C_EE_Private_Variables
STM32_EVAL_I2C_EE_Private_Function_Prototypes
STM32_EVAL_I2C_EE_Private_Functions
STM32_EVAL_I2C_EE_Exported_Types
STM32_EVAL_I2C_EE_Exported_Constants
STM32_EVAL_I2C_EE_Exported_Macros
STM32_EVAL_I2C_EE_Exported_Functions

Detailed Description

This file includes the I2C EEPROM driver of STM32-EVAL boards.


STM32F10x Standard Peripherals Firmware Library: STM32_EVAL_I2C_TSENSOR

Modules

STM32_EVAL_I2C_TSENSOR

Common

This file includes the LM75 Temperature Sensor driver of STM32-EVAL boards. More...

Modules

STM32_EVAL_I2C_TSENSOR_Private_Types
STM32_EVAL_I2C_TSENSOR_Private_Defines
STM32_EVAL_I2C_TSENSOR_Private_Macros
STM32_EVAL_I2C_TSENSOR_Private_Variables
STM32_EVAL_I2C_TSENSOR_Private_Function_Prototypes
STM32_EVAL_I2C_TSENSOR_Private_Functions
STM32_EVAL_I2C_TSENSOR_Exported_Types
STM32_EVAL_I2C_TSENSOR_Exported_Constants
STM32_EVAL_I2C_TSENSOR_Exported_Macros
STM32_EVAL_I2C_TSENSOR_Exported_Functions

Detailed Description

This file includes the LM75 Temperature Sensor driver of STM32-EVAL boards.


STM32F10x Standard Peripherals Firmware Library: STM32_EVAL_SDIO_SD

Modules

STM32_EVAL_SDIO_SD

Common

This file provides all the SD Card driver firmware functions. More...

Modules

STM32_EVAL_SDIO_SD_Private_Types
STM32_EVAL_SDIO_SD_Private_Defines
STM32_EVAL_SDIO_SD_Private_Macros
STM32_EVAL_SDIO_SD_Private_Variables
STM32_EVAL_SDIO_SD_Private_Function_Prototypes
STM32_EVAL_SDIO_SD_Private_Functions
STM32_EVAL_SDIO_SD_Exported_Types
STM32_EVAL_SDIO_SD_Exported_Constants
STM32_EVAL_SDIO_SD_Exported_Macros
STM32_EVAL_SDIO_SD_Exported_Functions

Detailed Description

This file provides all the SD Card driver firmware functions.


STM32F10x Standard Peripherals Firmware Library: STM32_EVAL_SPI_FLASH

Modules

STM32_EVAL_SPI_FLASH

Common

This file includes the M25Pxxx SPI FLASH driver of STM32-EVAL boards. More...

Modules

STM32_EVAL_SPI_FLASH_Private_Types
STM32_EVAL_SPI_FLASH_Private_Defines
STM32_EVAL_SPI_FLASH_Private_Macros
STM32_EVAL_SPI_FLASH_Private_Variables
STM32_EVAL_SPI_FLASH_Private_Function_Prototypes
STM32_EVAL_SPI_FLASH_Private_Functions
STM32_EVAL_SPI_FLASH_Exported_Types
STM32_EVAL_SPI_FLASH_Exported_Constants
STM32_EVAL_SPI_FLASH_Exported_Macros
STM32_EVAL_SPI_FLASH_Exported_Functions

Detailed Description

This file includes the M25Pxxx SPI FLASH driver of STM32-EVAL boards.


STM32F10x Standard Peripherals Firmware Library: STM32_EVAL_SPI_SD

Modules

STM32_EVAL_SPI_SD

Common

This file includes the SD card driver of STM32-EVAL boards. More...

Modules

STM32_EVAL_SPI_SD_Private_Types
STM32_EVAL_SPI_SD_Private_Defines
STM32_EVAL_SPI_SD_Private_Macros
STM32_EVAL_SPI_SD_Private_Variables
STM32_EVAL_SPI_SD_Private_Function_Prototypes
STM32_EVAL_SPI_SD_Private_Functions
STM32_EVAL_SPI_SD_Exported_Types
STM32_EVAL_SPI_SD_Exported_Constants
STM32_EVAL_SPI_SD_Exported_Macros
STM32_EVAL_SPI_SD_Exported_Functions

Detailed Description

This file includes the SD card driver of STM32-EVAL boards.


STM32F10x Standard Peripherals Firmware Library: Stm32f10x

Modules

Stm32f10x

CMSIS

Modules

Library_configuration_section
Configuration_section_for_CMSIS
Exported_types
Peripheral_registers_structures
Peripheral_memory_map
Peripheral_declaration
Exported_constants
Exported_macro


STM32F10x Standard Peripherals Firmware Library: STM32F10x_StdPeriph_Driver

Modules

STM32F10x_StdPeriph_Driver

Modules

MISC

MISC driver modules.

ADC

ADC driver modules.

BKP

BKP driver modules.

CAN

CAN driver modules.

CEC

CEC driver modules.

CRC

CRC driver modules.

DAC

DAC driver modules.

DBGMCU

DBGMCU driver modules.

DMA

DMA driver modules.

EXTI

EXTI driver modules.

FLASH

FLASH driver modules.

FSMC

FSMC driver modules.

GPIO

GPIO driver modules.

I2C

I2C driver modules.

IWDG

IWDG driver modules.

PWR

PWR driver modules.

RCC

RCC driver modules.

RTC

RTC driver modules.

SDIO

SDIO driver modules.

SPI

SPI driver modules.

TIM

TIM driver modules.

USART

USART driver modules.

WWDG

WWDG driver modules.


STM32F10x Standard Peripherals Firmware Library: STM32F10x_StdPeriph_Examples

Modules

STM32F10x_StdPeriph_Examples

Modules

ADC_3ADCs_DMA
ADC_ADC1_DMA
ADC_AnalogWatchdog
ADC_ExtLinesTrigger
ADC_RegSimul_DualMode
ADC_TIMTrigger_AutoInjection
BKP_Backup_Data
BKP_Tamper
CAN_DualCAN
CAN_LoopBack
CAN_Networking
CEC_DataExchangeInterrupt
CortexM3_BitBand
CortexM3_Mode_Privilege
CortexM3_MPU
CRC_Calculation
DAC_DualModeDMA_SineWave
DAC_OneChannel_NoiseWave
DAC_OneChannelDMA_Escalator
DAC_TwoChannels_TriangleWave
DMA_ADC_TIM1
DMA_FLASH_RAM
DMA_FSMC
DMA_I2C_RAM
DMA_SPI_RAM
EXTI_Config
Dual_Boot
FLASH_Program
FLASH_Write_Protection
FSMC_NAND
FSMC_NOR
FSMC_NOR_CodeExecute_binary
FSMC_NOR_CodeExecute
FSMC_OneNAND
FSMC_SRAM
FSMC_SRAM_DataMemory
GPIO_IOToggle
GPIO_JTAG_Remap
I2C_EEPROM
I2C_TSENSOR
I2C_IOExpander
I2S_Interrupt
I2S_SPI_I2S_Switch
IWDG_Reset
Lib_DEBUG_RunTime_Check
NVIC_DMA_WFIMode
IRQ_Mask
IRQ_Priority
NVIC_VectorTable_Relocation
PWR_PVD
PWR_STANDBY
PWR_STOP
RCC_ClockConfig
RTC_Calendar
RTC_LSI_Calib
SDIO_uSDCard
SPI_CRC
SPI_DMA
SPI_FullDuplex_SoftNSS
SPI_Simplex_Interrupt
SPI_FLASH
SysTick_TimeBase
TIM_6Steps
TIM_7PWM_Output
TIM_Cascade_Synchro
TIM_ComplementarySignals
TIM_DMA
TIM_DMABurst
TIM_ExtTrigger_Synchro
TIM_Input_Capture
TIM_OCActive
TIM_OCInactive
TIM_OCToggle
TIM_OnePulse
TIM_Parallel_Synchro
TIM_PWM_Input
TIM_PWM_Output
TIM10_PWMOutput
TIM15_ComplementarySignals
TIM_TIM1_Synchro
TIM9_OCToggle
TIM_TimeBase
USART_DMA_Interrupt
USART_DMA_Polling
USART_HalfDuplex
USART_HyperTerminal_HwFlowControl
USART_HyperTerminal_Interrupt
USART_Interrupt
USART_IrDA_Receive
USART_IrDA_Transmit
USART_MultiProcessor
USART_Polling
USART_Printf
USART_Smartcard
USART_Synchronous
WWDG_Reset


STM32F10x Standard Peripherals Firmware Library: Stm32f10x_system

Modules

Stm32f10x_system

CMSIS

Modules

STM32F10x_System_Private_Includes
STM32F10x_System_Private_TypesDefinitions
STM32F10x_System_Private_Defines
STM32F10x_System_Private_Macros
STM32F10x_System_Private_Variables
STM32F10x_System_Private_FunctionPrototypes
STM32F10x_System_Private_Functions
STM32F10x_System_Includes

Define to prevent recursive inclusion.

STM32F10x_System_Exported_types
STM32F10x_System_Exported_Constants
STM32F10x_System_Exported_Macros
STM32F10x_System_Exported_Functions


STM32F10x Standard Peripherals Firmware Library: STM32L152_EVAL

Modules

STM32L152_EVAL

STM32_EVAL

Modules

STM32L152_EVAL_LOW_LEVEL

This file provides firmware functions to manage Leds, push-buttons, COM ports, SD card on SPI and temperature sensor (LM75) available on STM32L152-EVAL evaluation board from STMicroelectronics.

STM32L152_EVAL_GLASS_LCD

This file includes the LCD Glass driver for Pacific Display (LCD_PD878, PD878-DP-FH-W-LV-6-RH) Module of STM32L152-EVAL board.

STM32L152_EVAL_LCD

This file includes the LCD driver for AM-240320L8TNQW00H (LCD_ILI9320), AM-240320LDTNQW00H (LCD_SPFD5408B) Liquid Crystal Display Module of STM32L152-EVAL board.

STM32L152_EVAL_I2C_EE

This file includes the I2C EEPROM driver of STM32L152-EVAL board.


STM32F10x Standard Peripherals Firmware Library: STM32L152_EVAL_GLASS_LCD

Modules

STM32L152_EVAL_GLASS_LCD

STM32L152_EVAL

This file includes the LCD Glass driver for Pacific Display (LCD_PD878, PD878-DP-FH-W-LV-6-RH) Module of STM32L152-EVAL board. More...

Modules

STM32L152_EVAL_GLASS_LCD_Private_Types
STM32L152_EVAL_GLASS_LCD_Private_Defines
STM32L152_EVAL_GLASS_LCD_Private_Macros
STM32L152_EVAL_GLASS_LCD_Private_Variables
STM32L152_EVAL_LCD_Private_Function_Prototypes
STM32L152_EVAL_LCD_Private_Functions
STM32L152_EVAL_GLASS_LCD_Exported_Types
STM32L152_EVAL_GLASS_LCD_Exported_Constants
STM32L152_EVAL_GLASS_LCD_Exported_Macros
STM32L152_EVAL_GLASS_LCD_Exported_Functions

Detailed Description

This file includes the LCD Glass driver for Pacific Display (LCD_PD878, PD878-DP-FH-W-LV-6-RH) Module of STM32L152-EVAL board.


STM32F10x Standard Peripherals Firmware Library: STM32L152_EVAL_I2C_EE

Modules

STM32L152_EVAL_I2C_EE

STM32L152_EVAL

This file includes the I2C EEPROM driver of STM32L152-EVAL board. More...

Modules

STM32L152_EVAL_I2C_EE_Private_Types
STM32L152_EVAL_I2C_EE_Private_Defines
STM32L152_EVAL_I2C_EE_Private_Macros
STM32L152_EVAL_I2C_EE_Private_Variables
STM32L152_EVAL_I2C_EE_Private_Function_Prototypes
STM32L152_EVAL_I2C_EE_Private_Functions
STM32L152_EVAL_I2C_EE_Exported_Types
STM32L152_EVAL_I2C_EE_Exported_Constants
STM32L152_EVAL_I2C_EE_Exported_Macros
STM32L152_EVAL_I2C_EE_Exported_Functions

Detailed Description

This file includes the I2C EEPROM driver of STM32L152-EVAL board.


STM32F10x Standard Peripherals Firmware Library: STM32L152_EVAL_LCD

Modules

STM32L152_EVAL_LCD

STM32L152_EVAL

This file includes the LCD driver for AM-240320L8TNQW00H (LCD_ILI9320), AM-240320LDTNQW00H (LCD_SPFD5408B) Liquid Crystal Display Module of STM32L152-EVAL board. More...

Modules

STM32L152_EVAL_LCD_Private_Types
STM32L152_EVAL_LCD_Private_Defines
STM32L152_EVAL_LCD_Private_Macros
STM32L152_EVAL_LCD_Private_Variables
STM32L152_EVAL_LCD_Private_Function_Prototypes
STM32L152_EVAL_LCD_Private_Functions
STM32L152_EVAL_LCD_Exported_Types
STM32L152_EVAL_LCD_Exported_Constants
STM32L152_EVAL_LCD_Exported_Macros
STM32L152_EVAL_LCD_Exported_Functions

Detailed Description

This file includes the LCD driver for AM-240320L8TNQW00H (LCD_ILI9320), AM-240320LDTNQW00H (LCD_SPFD5408B) Liquid Crystal Display Module of STM32L152-EVAL board.


STM32F10x Standard Peripherals Firmware Library: STM32L152_EVAL_LOW_LEVEL

Modules

STM32L152_EVAL_LOW_LEVEL

STM32L152_EVAL

This file provides firmware functions to manage Leds, push-buttons, COM ports, SD card on SPI and temperature sensor (LM75) available on STM32L152-EVAL evaluation board from STMicroelectronics. More...

Modules

STM32L152_EVAL_LOW_LEVEL_Private_TypesDefinitions
STM32L152_EVAL_LOW_LEVEL_Private_Defines
STM32L152_EVAL_LOW_LEVEL_Private_Macros
STM32L152_EVAL_LOW_LEVEL_Private_Variables
STM32L152_EVAL_LOW_LEVEL_Private_FunctionPrototypes
STM32L152_EVAL_LOW_LEVEL_Private_Functions
STM32L152_EVAL_LOW_LEVEL_Exported_Types
STM32L152_EVAL_LOW_LEVEL_Exported_Constants
STM32L152_EVAL_LOW_LEVEL_Exported_Macros
STM32L152_EVAL_LOW_LEVEL_Exported_Functions

Detailed Description

This file provides firmware functions to manage Leds, push-buttons, COM ports, SD card on SPI and temperature sensor (LM75) available on STM32L152-EVAL evaluation board from STMicroelectronics.


STM32F10x Standard Peripherals Firmware Library: STM32L152_EVAL_LOW_LEVEL_Exported_Constants

Modules

STM32L152_EVAL_LOW_LEVEL_Exported_Constants

STM32L152_EVAL_LOW_LEVEL

Modules

STM32L152_EVAL_LOW_LEVEL_LED
STM32L152_EVAL_LOW_LEVEL_BUTTON
STM32L152_EVAL_LOW_LEVEL_COM
STM32L152_EVAL_LOW_LEVEL_SD_FLASH
STM32L152_EVAL_LOW_LEVEL_TSENSOR_I2C
STM32L152_EVAL_LOW_LEVEL_I2C_EE


STM32F10x Standard Peripherals Firmware Library: STM3210B_EVAL

Modules

STM3210B_EVAL

STM32_EVAL

Modules

STM3210B_EVAL_LOW_LEVEL

This file provides firmware functions to manage Leds, push-buttons, COM ports, SD card on SPI, serial flash (sFLASH), serial EEPROM (sEE) and temperature sensor (LM75) available on STM3210B-EVAL evaluation board from STMicroelectronics.

STM3210B_EVAL_LCD

file includes the LCD driver for AM-240320LTNQW00H (LCD_HX8312), AM-240320L8TNQW00H (LCD_ILI9320), AM-240320LDTNQW00H (LCD_SPFD5408B) Liquid Crystal Display Module of STM3210B-EVAL board.


STM32F10x Standard Peripherals Firmware Library: STM3210B_EVAL_LCD

Modules

STM3210B_EVAL_LCD

STM3210B_EVAL

file includes the LCD driver for AM-240320LTNQW00H (LCD_HX8312), AM-240320L8TNQW00H (LCD_ILI9320), AM-240320LDTNQW00H (LCD_SPFD5408B) Liquid Crystal Display Module of STM3210B-EVAL board. More...

Modules

STM3210B_EVAL_LCD_Private_Types
STM3210B_EVAL_LCD_Private_Defines
STM3210B_EVAL_LCD_Private_Macros
STM3210B_EVAL_LCD_Private_Variables
STM3210B_EVAL_LCD_Private_Function_Prototypes
STM3210B_EVAL_LCD_Private_Functions
STM3210B_EVAL_LCD_Exported_Types
STM3210B_EVAL_LCD_Exported_Constants
STM3210B_EVAL_LCD_Exported_Macros
STM3210B_EVAL_LCD_Exported_Functions

Detailed Description

file includes the LCD driver for AM-240320LTNQW00H (LCD_HX8312), AM-240320L8TNQW00H (LCD_ILI9320), AM-240320LDTNQW00H (LCD_SPFD5408B) Liquid Crystal Display Module of STM3210B-EVAL board.


STM32F10x Standard Peripherals Firmware Library: STM3210B_EVAL_LOW_LEVEL

Modules

STM3210B_EVAL_LOW_LEVEL

STM3210B_EVAL

This file provides firmware functions to manage Leds, push-buttons, COM ports, SD card on SPI, serial flash (sFLASH), serial EEPROM (sEE) and temperature sensor (LM75) available on STM3210B-EVAL evaluation board from STMicroelectronics. More...

Modules

STM3210B_EVAL_LOW_LEVEL_Private_TypesDefinitions
STM3210B_EVAL_LOW_LEVEL_Private_Defines
STM3210B_EVAL_LOW_LEVEL_Private_Macros
STM3210B_EVAL_LOW_LEVEL_Private_Variables
STM3210B_EVAL_LOW_LEVEL_Private_FunctionPrototypes
STM3210B_EVAL_LOW_LEVEL_Private_Functions
STM3210B_EVAL_LOW_LEVEL_Exported_Types
STM3210B_EVAL_LOW_LEVEL_Exported_Constants
STM3210B_EVAL_LOW_LEVEL_Exported_Macros
STM3210B_EVAL_LOW_LEVEL_Exported_Functions

Detailed Description

This file provides firmware functions to manage Leds, push-buttons, COM ports, SD card on SPI, serial flash (sFLASH), serial EEPROM (sEE) and temperature sensor (LM75) available on STM3210B-EVAL evaluation board from STMicroelectronics.


STM32F10x Standard Peripherals Firmware Library: STM3210B_EVAL_LOW_LEVEL_Exported_Constants

Modules

STM3210B_EVAL_LOW_LEVEL_Exported_Constants

STM3210B_EVAL_LOW_LEVEL

Modules

STM3210B_EVAL_LOW_LEVEL_LED
STM3210B_EVAL_LOW_LEVEL_BUTTON
STM3210B_EVAL_LOW_LEVEL_COM
STM3210B_EVAL_LOW_LEVEL_SD_SPI
STM3210B_EVAL_LOW_LEVEL_M25P_FLASH_SPI
STM3210B_EVAL_LOW_LEVEL_TSENSOR_I2C


STM32F10x Standard Peripherals Firmware Library: STM3210C_EVAL

Modules

STM3210C_EVAL

STM32_EVAL

Modules

STM3210C_EVAL_LOW_LEVEL

This file provides firmware functions to manage Leds, push-buttons, COM ports, SD card on SPI and EEPROM (sEE) available on STM3210C-EVAL evaluation board from STMicroelectronics.

STM3210C_EVAL_IOE

This file includes the IO Expander driver for STMPE811 IO Expander devices.

STM3210C_EVAL_LCD

This file includes the LCD driver for AM-240320L8TNQW00H (LCD_ILI9320) Liquid Crystal Display Module of STM3210C-EVAL board.


STM32F10x Standard Peripherals Firmware Library: STM3210C_EVAL_IOE

Modules

STM3210C_EVAL_IOE

STM3210C_EVAL

This file includes the IO Expander driver for STMPE811 IO Expander devices. More...

Modules

STM3210C_EVAL_IOE_Private_TypesDefinitions
STM3210C_EVAL_IOE_Private_Defines
STM3210C_EVAL_IOE_Private_Macros
STM3210C_EVAL_IOE_Private_Variables
STM3210C_EVAL_IOE_Private_FunctionPrototypes
STM3210C_EVAL_IOE_Private_Functions
STM3210C_EVAL_IOE_Exported_Types
STM3210C_EVAL_IOE_Exported_Constants
STM3210C_EVAL_IOE_Exported_Macros
STM3210C_EVAL_IOE_Exported_Functions

Detailed Description

This file includes the IO Expander driver for STMPE811 IO Expander devices.


STM32F10x Standard Peripherals Firmware Library: STM3210C_EVAL_LCD

Modules

STM3210C_EVAL_LCD

STM3210C_EVAL

This file includes the LCD driver for AM-240320L8TNQW00H (LCD_ILI9320) Liquid Crystal Display Module of STM3210C-EVAL board. More...

Modules

STM3210C_EVAL_LCD_Private_TypesDefinitions
STM3210C_EVAL_LCD_Private_Defines
STM3210C_EVAL_LCD_Private_Macros
STM3210C_EVAL_LCD_Private_Variables
STM3210C_EVAL_LCD_Private_FunctionPrototypes
STM3210C_EVAL_LCD_Private_Functions
STM3210C_EVAL_LCD_Exported_Types
STM3210C_EVAL_LCD_Exported_Constants
STM3210C_EVAL_LCD_Exported_Macros
STM3210C_EVAL_LCD_Exported_Functions

Detailed Description

This file includes the LCD driver for AM-240320L8TNQW00H (LCD_ILI9320) Liquid Crystal Display Module of STM3210C-EVAL board.


STM32F10x Standard Peripherals Firmware Library: STM3210C_EVAL_LOW_LEVEL

Modules

STM3210C_EVAL_LOW_LEVEL

STM3210C_EVAL

This file provides firmware functions to manage Leds, push-buttons, COM ports, SD card on SPI and EEPROM (sEE) available on STM3210C-EVAL evaluation board from STMicroelectronics. More...

Modules

STM3210C_EVAL_LOW_LEVEL_Private_TypesDefinitions
STM3210C_EVAL_LOW_LEVEL_Private_Defines
STM3210C_EVAL_LOW_LEVEL_Private_Macros
STM3210C_EVAL_LOW_LEVEL_Private_Variables
STM3210C_EVAL_LOW_LEVEL_Private_FunctionPrototypes
STM3210C_EVAL_LOW_LEVEL_Private_Functions
STM3210C_EVAL_LOW_LEVEL_Exported_Types
STM3210C_EVAL_LOW_LEVEL_Exported_Constants
STM3210C_EVAL_LOW_LEVEL_Exported_Macros
STM3210C_EVAL_LOW_LEVEL_Exported_Functions

Detailed Description

This file provides firmware functions to manage Leds, push-buttons, COM ports, SD card on SPI and EEPROM (sEE) available on STM3210C-EVAL evaluation board from STMicroelectronics.


STM32F10x Standard Peripherals Firmware Library: STM3210C_EVAL_LOW_LEVEL_Exported_Constants

Modules

STM3210C_EVAL_LOW_LEVEL_Exported_Constants

STM3210C_EVAL_LOW_LEVEL

Modules

STM3210C_EVAL_LOW_LEVEL_LED
STM3210C_EVAL_LOW_LEVEL_BUTTON
STM3210C_EVAL_LOW_LEVEL_COM
STM3210B_EVAL_SD_SPI
STM3210C_EVAL_LOW_LEVEL_I2C_EE


STM32F10x Standard Peripherals Firmware Library: STM3210E_EVAL

Modules

STM3210E_EVAL

STM32_EVAL

Modules

STM3210E_EVAL_LOW_LEVEL

This file provides firmware functions to manage Leds, push-buttons, COM ports, SD card on SDIO, serial flash (sFLASH), serial EEPROM (sEE) and temperature sensor (LM75) available on STM3210E-EVAL evaluation board from STMicroelectronics.

STM3210E_EVAL_LCD

This file includes the LCD driver for AM-240320L8TNQW00H (LCD_ILI9320) and AM-240320LDTNQW00H (LCD_SPFD5408B) Liquid Crystal Display Module of STM3210E-EVAL board.

STM3210E_EVAL_FSMC_NAND

This file provides a set of functions needed to drive the NAND512W3A2 memory mounted on STM3210E-EVAL board.

STM3210E_EVAL_FSMC_NOR

This file provides a set of functions needed to drive the M29W128FL, M29W128GL and S29GL128P NOR memories mounted on STM3210E-EVAL board.

STM3210E_EVAL_FSMC_SRAM

This file provides a set of functions needed to drive the IS61WV51216BLL SRAM memory mounted on STM3210E-EVAL board.


STM32F10x Standard Peripherals Firmware Library: STM3210E_EVAL_FSMC_NAND

Modules

STM3210E_EVAL_FSMC_NAND

STM3210E_EVAL

This file provides a set of functions needed to drive the NAND512W3A2 memory mounted on STM3210E-EVAL board. More...

Modules

STM3210E_EVAL_FSMC_NAND_Private_Types
STM3210E_EVAL_FSMC_NAND_Private_Defines
STM3210E_EVAL_FSMC_NAND_Private_Macros
STM3210E_EVAL_FSMC_NAND_Private_Variables
STM3210E_EVAL_FSMC_NAND_Private_Function_Prototypes
STM3210E_EVAL_FSMC_NAND_Private_Functions
STM3210E_EVAL_FSMC_NAND_Exported_Types
STM3210E_EVAL_FSMC_NAND_Exported_Constants
STM3210E_EVAL_FSMC_NAND_Exported_Macros
STM3210E_EVAL_FSMC_NAND_Exported_Functions

Detailed Description

This file provides a set of functions needed to drive the NAND512W3A2 memory mounted on STM3210E-EVAL board.


STM32F10x Standard Peripherals Firmware Library: STM3210E_EVAL_FSMC_NAND_Exported_Types

Data Structures

STM3210E_EVAL_FSMC_NAND_Exported_Types

STM3210E_EVAL_FSMC_NAND

Data Structures

struct | NAND_ADDRESS
struct | NAND_IDTypeDef


STM32F10x Standard Peripherals Firmware Library: STM3210E_EVAL_FSMC_NOR

Modules

STM3210E_EVAL_FSMC_NOR

STM3210E_EVAL

This file provides a set of functions needed to drive the M29W128FL, M29W128GL and S29GL128P NOR memories mounted on STM3210E-EVAL board. More...

Modules

STM3210E_EVAL_FSMC_NOR_Private_Types
STM3210E_EVAL_FSMC_NOR_Private_Defines
STM3210E_EVAL_FSMC_NOR_Private_Macros
STM3210E_EVAL_FSMC_NOR_Private_Variables
STM3210E_EVAL_FSMC_NOR_Private_Functions
STM3210E_EVAL_FSMC_NOR_Exported_Types
STM3210E_EVAL_FSMC_NOR_Exported_Constants
STM3210E_EVAL_FSMC_NOR_Exported_Macros
STM3210E_EVAL_FSMC_NOR_Exported_Functions

Detailed Description

This file provides a set of functions needed to drive the M29W128FL, M29W128GL and S29GL128P NOR memories mounted on STM3210E-EVAL board.


STM32F10x Standard Peripherals Firmware Library: STM3210E_EVAL_FSMC_SRAM

Modules

STM3210E_EVAL_FSMC_SRAM

STM3210E_EVAL

This file provides a set of functions needed to drive the IS61WV51216BLL SRAM memory mounted on STM3210E-EVAL board. More...

Modules

STM3210E_EVAL_FSMC_SRAM_Private_Types
STM3210E_EVAL_FSMC_SRAM_Private_Defines
STM3210E_EVAL_FSMC_SRAM_Private_Macros
STM3210E_EVAL_FSMC_SRAM_Private_Variables
STM3210E_EVAL_FSMC_SRAM_Private_Function_Prototypes
STM3210E_EVAL_FSMC_SRAM_Private_Functions
STM3210E_EVAL_FSMC_SRAM_Exported_Types
STM3210E_EVAL_FSMC_SRAM_Exported_Constants
STM3210E_EVAL_FSMC_SRAM_Exported_Macros
STM3210E_EVAL_FSMC_SRAM_Exported_Functions

Detailed Description

This file provides a set of functions needed to drive the IS61WV51216BLL SRAM memory mounted on STM3210E-EVAL board.


STM32F10x Standard Peripherals Firmware Library: STM3210E_EVAL_LCD

Modules

STM3210E_EVAL_LCD

STM3210E_EVAL

This file includes the LCD driver for AM-240320L8TNQW00H (LCD_ILI9320) and AM-240320LDTNQW00H (LCD_SPFD5408B) Liquid Crystal Display Module of STM3210E-EVAL board. More...

Modules

STM3210E_EVAL_LCD_Private_TypesDefinitions
STM3210E_EVAL_LCD_Private_Defines
STM3210E_EVAL_LCD_Private_Macros
STM3210E_EVAL_LCD_Private_Variables
STM3210E_EVAL_LCD_Private_FunctionPrototypes
STM3210E_EVAL_LCD_Private_Functions
STM3210E_EVAL_LCD_Exported_Types
STM3210E_EVAL_LCD_Exported_Constants
STM3210E_EVAL_LCD_Exported_Macros
STM3210E_EVAL_LCD_Exported_Functions

Detailed Description

This file includes the LCD driver for AM-240320L8TNQW00H (LCD_ILI9320) and AM-240320LDTNQW00H (LCD_SPFD5408B) Liquid Crystal Display Module of STM3210E-EVAL board.


STM32F10x Standard Peripherals Firmware Library: STM3210E_EVAL_LCD_Private_TypesDefinitions

Data Structures

STM3210E_EVAL_LCD_Private_TypesDefinitions

STM3210E_EVAL_LCD

Data Structures

struct LCD_TypeDef


STM32F10x Standard Peripherals Firmware Library: STM3210E_EVAL_LOW_LEVEL

Modules

STM3210E_EVAL_LOW_LEVEL

STM3210E_EVAL

This file provides firmware functions to manage Leds, push-buttons, COM ports, SD card on SDIO, serial flash (sFLASH), serial EEPROM (sEE) and temperature sensor (LM75) available on STM3210E-EVAL evaluation board from STMicroelectronics. More...

Modules

STM3210E_EVAL_LOW_LEVEL_Private_TypesDefinitions
STM3210E_EVAL_LOW_LEVEL_Private_Defines
STM3210E_EVAL_LOW_LEVEL_Private_Macros
STM3210E_EVAL_LOW_LEVEL_Private_Variables
STM3210E_EVAL_LOW_LEVEL_Private_FunctionPrototypes
STM3210E_EVAL_LOW_LEVEL_Private_Functions
STM3210E_EVAL_LOW_LEVEL_Exported_Types
STM3210E_EVAL_LOW_LEVEL_Exported_Constants
STM3210E_EVAL_LOW_LEVEL_Exported_Macros
STM3210E_EVAL_LOW_LEVEL_Exported_Functions

Detailed Description

This file provides firmware functions to manage Leds, push-buttons, COM ports, SD card on SDIO, serial flash (sFLASH), serial EEPROM (sEE) and temperature sensor (LM75) available on STM3210E-EVAL evaluation board from STMicroelectronics.


STM32F10x Standard Peripherals Firmware Library: STM3210E_EVAL_LOW_LEVEL_Exported_Constants

Modules

STM3210E_EVAL_LOW_LEVEL_Exported_Constants

STM3210E_EVAL_LOW_LEVEL

Modules

STM3210E_EVAL_LOW_LEVEL_LED
STM3210E_EVAL_LOW_LEVEL_BUTTON
STM3210E_EVAL_LOW_LEVEL_COM
STM3210E_EVAL_LOW_LEVEL_SD_FLASH
STM3210E_EVAL_LOW_LEVEL_M25P_FLASH_SPI
STM3210E_EVAL_LOW_LEVEL_TSENSOR_I2C


STM32F10x Standard Peripherals Firmware Library: STM32100B_EVAL

Modules

STM32100B_EVAL

STM32_EVAL

Modules

STM32100B_EVAL_LOW_LEVEL

This file provides firmware functions to manage Leds, push-buttons, COM ports, SD card on SPI, serial flash (sFLASH) and temperature sensor (LM75) available on STM32100B-EVAL evaluation board from STMicroelectronics.

STM32100B_EVAL_CEC

This file includes the CEC Stack driver for HDMI-CEC Module of STM32100B-EVAL board.

STM32100B_EVAL_LCD

This file includes the LCD driver for AM-240320LTNQW00H (LCD_HX8312), AM-240320L8TNQW00H (LCD_ILI9320), AM-240320LDTNQW00H (LCD_SPFD5408B) Liquid Crystal Display Module of STM32100B-EVAL board.


STM32F10x Standard Peripherals Firmware Library: STM32100B_EVAL_CEC

Modules

STM32100B_EVAL_CEC

STM32100B_EVAL

This file includes the CEC Stack driver for HDMI-CEC Module of STM32100B-EVAL board. More...

Modules

STM32100B_EVAL_CEC_Private_Types
STM32100B_EVAL_CEC_Private_Defines
STM32100B_EVAL_CEC_Private_Macros
STM32100B_EVAL_CEC_Private_Variables
STM32100B_EVAL_CEC_Private_Function_Prototypes
STM32100B_EVAL_CEC_Private_Functions
STM32100B_EVAL_CEC_Exported_Types
STM32100B_EVAL_CEC_Exported_Constants
STM32100B_EVAL_CEC_Exported_Macros
STM32100B_EVAL_CEC_Exported_Functions

Detailed Description

This file includes the CEC Stack driver for HDMI-CEC Module of STM32100B-EVAL board.


STM32F10x Standard Peripherals Firmware Library: STM32100B_EVAL_LCD

Modules

STM32100B_EVAL_LCD

STM32100B_EVAL

This file includes the LCD driver for AM-240320LTNQW00H (LCD_HX8312), AM-240320L8TNQW00H (LCD_ILI9320), AM-240320LDTNQW00H (LCD_SPFD5408B) Liquid Crystal Display Module of STM32100B-EVAL board. More...

Modules

STM32100B_EVAL_LCD_Private_Types
STM32100B_EVAL_LCD_Private_Defines
STM32100B_EVAL_LCD_Private_Macros
STM32100B_EVAL_LCD_Private_Variables
STM32100B_EVAL_LCD_Private_Function_Prototypes
STM32100B_EVAL_LCD_Private_Functions
STM32100B_EVAL_LCD_Exported_Types
STM32100B_EVAL_LCD_Exported_Constants
STM32100B_EVAL_LCD_Exported_Macros
STM32100B_EVAL_LCD_Exported_Functions

Detailed Description

This file includes the LCD driver for AM-240320LTNQW00H (LCD_HX8312), AM-240320L8TNQW00H (LCD_ILI9320), AM-240320LDTNQW00H (LCD_SPFD5408B) Liquid Crystal Display Module of STM32100B-EVAL board.


STM32F10x Standard Peripherals Firmware Library: STM32100B_EVAL_LOW_LEVEL

Modules

STM32100B_EVAL_LOW_LEVEL

STM32100B_EVAL

This file provides firmware functions to manage Leds, push-buttons, COM ports, SD card on SPI, serial flash (sFLASH) and temperature sensor (LM75) available on STM32100B-EVAL evaluation board from STMicroelectronics. More...

Modules

STM32100B_EVAL_LOW_LEVEL_Private_TypesDefinitions
STM32100B_EVAL_LOW_LEVEL_Private_Defines
STM32100B_EVAL_LOW_LEVEL_Private_Macros
STM32100B_EVAL_LOW_LEVEL_Private_Variables
STM32100B_EVAL_LOW_LEVEL_Private_FunctionPrototypes
STM32100B_EVAL_LOW_LEVEL_Private_Functions
STM32100B_EVAL_LOW_LEVEL_Exported_Types
STM32100B_EVAL_LOW_LEVEL_Exported_Constants
STM32100B_EVAL_LOW_LEVEL_Exported_Macros
STM32100B_EVAL_LOW_LEVEL_Exported_Functions

Detailed Description

This file provides firmware functions to manage Leds, push-buttons, COM ports, SD card on SPI, serial flash (sFLASH) and temperature sensor (LM75) available on STM32100B-EVAL evaluation board from STMicroelectronics.


STM32F10x Standard Peripherals Firmware Library: STM32100B_EVAL_LOW_LEVEL_Exported_Constants

Modules

STM32100B_EVAL_LOW_LEVEL_Exported_Constants

STM32100B_EVAL_LOW_LEVEL

Modules

STM32100B_EVAL_LOW_LEVEL_LED
STM32100B_EVAL_LOW_LEVEL_BUTTON
STM32100B_EVAL_LOW_LEVEL_COM
STM32100B_EVAL_LOW_LEVEL_SD_SPI
STM32100B_EVAL_LOW_LEVEL_M25P_FLASH_SPI
STM32100B_EVAL_LOW_LEVEL_TSENSOR_I2C


STM32F10x Standard Peripherals Firmware Library: STM32100E_EVAL

Modules

STM32100E_EVAL

STM32_EVAL

Modules

STM32100E_EVAL_LOW_LEVEL

This file provides firmware functions to manage Leds, push-buttons, COM ports, SD card on SDIO, serial flash (sFLASH), serial EEPROM (sEE) and temperature sensor (LM75) available on STM32100E-EVAL evaluation board from STMicroelectronics.

STM32100E_EVAL_CEC

This file includes the CEC Stack driver for HDMI-CEC Module of STM32100E-EVAL board.

STM32100E_EVAL_IOE

This file includes the IO Expander driver for STMPE811 IO Expander devices.

STM32100E_EVAL_LCD

This file includes the LCD driver for AM-240320L8TNQW00H (LCD_ILI9320), AM240320D5TOQW01H (LCD_ILI9325) and AM-240320LDTNQW00H (LCD_SPFD5408B) Liquid Crystal Display Module of STM32100E-EVAL board.

STM32100E_EVAL_FSMC_ONENAND

This file provides a set of functions needed to drive the KFG1216x2A-xxB5 OneNAND memory mounted on STM32100E-EVAL board.

STM32100E_EVAL_FSMC_SRAM

This file provides a set of functions needed to drive the IS61WV102416BLL SRAM memory mounted on STM32100E-EVAL board.


STM32F10x Standard Peripherals Firmware Library: STM32100E_EVAL_CEC

Modules

STM32100E_EVAL_CEC

STM32100E_EVAL

This file includes the CEC Stack driver for HDMI-CEC Module of STM32100E-EVAL board. More...

Modules

STM32100E_EVAL_CEC_Private_Types
STM32100E_EVAL_CEC_Private_Defines
STM32100E_EVAL_CEC_Private_Macros
STM32100E_EVAL_CEC_Private_Variables
STM32100E_EVAL_CEC_Private_Function_Prototypes
STM32100E_EVAL_CEC_Private_Functions
STM32100E_EVAL_CEC_Exported_Types
STM32100E_EVAL_CEC_Exported_Constants
STM32100E_EVAL_CEC_Exported_Macros
STM32100E_EVAL_CEC_Exported_Functions

Detailed Description

This file includes the CEC Stack driver for HDMI-CEC Module of STM32100E-EVAL board.


STM32F10x Standard Peripherals Firmware Library: STM32100E_EVAL_FSMC_ONENAND

Modules

STM32100E_EVAL_FSMC_ONENAND

STM32100E_EVAL

This file provides a set of functions needed to drive the KFG1216x2A-xxB5 OneNAND memory mounted on STM32100E-EVAL board. More...

Modules

STM32100E_EVAL_FSMC_ONENAND_Private_Types
STM32100E_EVAL_FSMC_ONENAND_Private_Defines
STM32100E_EVAL_FSMC_ONENAND_Private_Macros
STM32100E_EVAL_FSMC_ONENAND_Private_Variables
STM32100E_EVAL_FSMC_ONENAND_Private_Function_Prototypes
STM32100E_EVAL_FSMC_ONENAND_Private_Functions
STM32100E_EVAL_FSMC_ONENAND_Exported_Types
STM32100E_EVAL_FSMC_ONENAND_Exported_Constants
STM32100E_EVAL_FSMC_ONENAND_Exported_Macros
STM32100E_EVAL_FSMC_ONENAND_Exported_Functions

Detailed Description

This file provides a set of functions needed to drive the KFG1216x2A-xxB5 OneNAND memory mounted on STM32100E-EVAL board.


STM32F10x Standard Peripherals Firmware Library: STM32100E_EVAL_FSMC_SRAM

Modules

STM32100E_EVAL_FSMC_SRAM

STM32100E_EVAL

This file provides a set of functions needed to drive the IS61WV102416BLL SRAM memory mounted on STM32100E-EVAL board. More...

Modules

STM32100E_EVAL_FSMC_SRAM_Private_Types
STM32100E_EVAL_FSMC_SRAM_Private_Defines
STM32100E_EVAL_FSMC_SRAM_Private_Macros
STM32100E_EVAL_FSMC_SRAM_Private_Variables
STM32100E_EVAL_FSMC_SRAM_Private_Function_Prototypes
STM32100E_EVAL_FSMC_SRAM_Private_Functions
STM32100E_EVAL_FSMC_SRAM_Exported_Types
STM32100E_EVAL_FSMC_SRAM_Exported_Constants
STM32100E_EVAL_FSMC_SRAM_Exported_Macros
STM32100E_EVAL_FSMC_SRAM_Exported_Functions

Detailed Description

This file provides a set of functions needed to drive the IS61WV102416BLL SRAM memory mounted on STM32100E-EVAL board.


STM32F10x Standard Peripherals Firmware Library: STM32100E_EVAL_IOE

Modules

STM32100E_EVAL_IOE

STM32100E_EVAL

This file includes the IO Expander driver for STMPE811 IO Expander devices. More...

Modules

STM32100E_EVAL_IOE_Private_TypesDefinitions
STM32100E_EVAL_IOE_Private_Defines
STM32100E_EVAL_IOE_Private_Macros
STM32100E_EVAL_IOE_Private_Variables
STM32100E_EVAL_IOE_Private_FunctionPrototypes
STM32100E_EVAL_IOE_Private_Functions
STM32100E_EVAL_IOE_Exported_Types
STM32100E_EVAL_IOE_Exported_Constants
STM32100E_EVAL_IOE_Exported_Macros
STM32100E_EVAL_IOE_Exported_Functions

Detailed Description

This file includes the IO Expander driver for STMPE811 IO Expander devices.


STM32F10x Standard Peripherals Firmware Library: STM32100E_EVAL_LCD

Modules

STM32100E_EVAL_LCD

STM32100E_EVAL

This file includes the LCD driver for AM-240320L8TNQW00H (LCD_ILI9320), AM240320D5TOQW01H (LCD_ILI9325) and AM-240320LDTNQW00H (LCD_SPFD5408B) Liquid Crystal Display Module of STM32100E-EVAL board. More...

Modules

STM32100E_EVAL_LCD_Private_TypesDefinitions
STM32100E_EVAL_LCD_Private_Defines
STM32100E_EVAL_LCD_Private_Macros
STM32100E_EVAL_LCD_Private_Variables
STM32100E_EVAL_LCD_Private_FunctionPrototypes
STM32100E_EVAL_LCD_Private_Functions
STM32100E_EVAL_LCD_Exported_Types
STM32100E_EVAL_LCD_Exported_Constants
STM32100E_EVAL_LCD_Exported_Macros
STM32100E_EVAL_LCD_Exported_Functions

Detailed Description

This file includes the LCD driver for AM-240320L8TNQW00H (LCD_ILI9320), AM240320D5TOQW01H (LCD_ILI9325) and AM-240320LDTNQW00H (LCD_SPFD5408B) Liquid Crystal Display Module of STM32100E-EVAL board.


STM32F10x Standard Peripherals Firmware Library: STM32100E_EVAL_LCD_Private_TypesDefinitions

Data Structures

STM32100E_EVAL_LCD_Private_TypesDefinitions

STM32100E_EVAL_LCD

Data Structures

struct LCD_TypeDef


STM32F10x Standard Peripherals Firmware Library: STM32100E_EVAL_LOW_LEVEL

Modules

STM32100E_EVAL_LOW_LEVEL

STM32100E_EVAL

This file provides firmware functions to manage Leds, push-buttons, COM ports, SD card on SDIO, serial flash (sFLASH), serial EEPROM (sEE) and temperature sensor (LM75) available on STM32100E-EVAL evaluation board from STMicroelectronics. More...

Modules

STM32100E_EVAL_LOW_LEVEL_Private_TypesDefinitions
STM32100E_EVAL_LOW_LEVEL_Private_Defines
STM32100E_EVAL_LOW_LEVEL_Private_Macros
STM32100E_EVAL_LOW_LEVEL_Private_Variables
STM32100E_EVAL_LOW_LEVEL_Private_FunctionPrototypes
STM32100E_EVAL_LOW_LEVEL_Private_Functions
STM32100E_EVAL_LOW_LEVEL_Exported_Types
STM32100E_EVAL_LOW_LEVEL_Exported_Constants
STM32100E_EVAL_LOW_LEVEL_Exported_Macros
STM32100E_EVAL_LOW_LEVEL_Exported_Functions

Detailed Description

This file provides firmware functions to manage Leds, push-buttons, COM ports, SD card on SDIO, serial flash (sFLASH), serial EEPROM (sEE) and temperature sensor (LM75) available on STM32100E-EVAL evaluation board from STMicroelectronics.


STM32F10x Standard Peripherals Firmware Library: STM32100E_EVAL_LOW_LEVEL_Exported_Constants

Modules

STM32100E_EVAL_LOW_LEVEL_Exported_Constants

STM32100E_EVAL_LOW_LEVEL

Modules

STM32100E_EVAL_LOW_LEVEL_LED
STM32100E_EVAL_LOW_LEVEL_BUTTON
STM32100E_EVAL_LOW_LEVEL_COM
STM32100E_EVAL_LOW_LEVEL_SD_FLASH
STM3210C_EVAL_LOW_LEVEL_I2C_EE
STM32100E_EVAL_LOW_LEVEL_M25P_FLASH_SPI
STM32100E_EVAL_LOW_LEVEL_TSENSOR_I2C


STM32F10x Standard Peripherals Firmware Library: TIM

Modules

TIM

STM32F10x_StdPeriph_Driver

TIM driver modules. More...

Modules

TIM_Exported_Types
TIM_Exported_Macros
TIM_Exported_Functions
TIM_Private_TypesDefinitions
TIM_Private_Defines
TIM_Private_Macros
TIM_Private_Variables
TIM_Private_FunctionPrototypes
TIM_Private_Functions

Detailed Description

TIM driver modules.


STM32F10x Standard Peripherals Firmware Library: TIM_Exported_Types

Data Structures | Modules

TIM_Exported_Types

TIM

Data Structures

struct | TIM_BDTRInitTypeDef
BDTR structure definition. More...
struct | TIM_ICInitTypeDef
TIM Input Capture Init structure definition. More...
struct | TIM_OCInitTypeDef
TIM Output Compare Init structure definition. More...
struct | TIM_TimeBaseInitTypeDef
TIM Time Base Init structure definition. More...

Modules

TIM_Exported_constants
TIM_Output_Compare_and_PWM_modes
TIM_One_Pulse_Mode
TIM_Channel
TIM_Clock_Division_CKD
TIM_Counter_Mode
TIM_Output_Compare_Polarity
TIM_Output_Compare_N_Polarity
TIM_Output_Compare_state
TIM_Output_Compare_N_state
TIM_Capture_Compare_state
TIM_Capture_Compare_N_state
Break_Input_enable_disable
Break_Polarity
TIM_AOE_Bit_Set_Reset
Lock_level
OSSI_Off_State_Selection_for_Idle_mode_state
OSSR_Off_State_Selection_for_Run_mode_state
TIM_Output_Compare_Idle_State
TIM_Output_Compare_N_Idle_State
TIM_Input_Capture_Polarity
TIM_Input_Capture_Selection
TIM_Input_Capture_Prescaler
TIM_interrupt_sources
TIM_DMA_Base_address
TIM_DMA_Burst_Length
TIM_DMA_sources
TIM_External_Trigger_Prescaler
TIM_Internal_Trigger_Selection
TIM_TIx_External_Clock_Source
TIM_External_Trigger_Polarity
TIM_Prescaler_Reload_Mode
TIM_Forced_Action
TIM_Encoder_Mode
TIM_Event_Source
TIM_Update_Source
TIM_Output_Compare_Preload_State
TIM_Output_Compare_Fast_State
TIM_Output_Compare_Clear_State
TIM_Trigger_Output_Source
TIM_Slave_Mode
TIM_Master_Slave_Mode
TIM_Flags
TIM_Input_Capture_Filer_Value
TIM_External_Trigger_Filter
TIM_Legacy


STM32F10x Standard Peripherals Firmware Library: USART

Modules

USART

STM32F10x_StdPeriph_Driver

USART driver modules. More...

Modules

USART_Exported_Types
USART_Exported_Constants
USART_Exported_Macros
USART_Exported_Functions
USART_Private_TypesDefinitions
USART_Private_Defines
USART_Private_Macros
USART_Private_Variables
USART_Private_FunctionPrototypes
USART_Private_Functions

Detailed Description

USART driver modules.


STM32F10x Standard Peripherals Firmware Library: USART_Exported_Types

Data Structures

USART_Exported_Types

USART

Data Structures

struct | USART_ClockInitTypeDef
USART Clock Init Structure definition. More...
struct | USART_InitTypeDef
USART Init Structure definition. More...


STM32F10x Standard Peripherals Firmware Library: Utilities

Modules

Utilities

Modules

STM32_EVAL

This file provides firmware functions to manage Leds, push-buttons, COM ports and low level HW resources initialization of the different modules available on STM32 Evaluation Boards from STMicroelectronics.


STM32F10x Standard Peripherals Firmware Library: WWDG

Modules

WWDG

STM32F10x_StdPeriph_Driver

WWDG driver modules. More...

Modules

WWDG_Exported_Types
WWDG_Exported_Constants
WWDG_Exported_Macros
WWDG_Exported_Functions
WWDG_Private_TypesDefinitions
WWDG_Private_Defines
WWDG_Private_Macros
WWDG_Private_Variables
WWDG_Private_FunctionPrototypes
WWDG_Private_Functions

Detailed Description

WWDG driver modules.


STM32F10x Standard Peripherals Firmware Library: WWDG_Exported_Constants

Modules

WWDG_Exported_Constants

WWDG

Modules

WWDG_Prescaler


STM32F10x Standard Peripherals Firmware Library: hitop_project_template.txt File Reference

  • File List
  • Globals

hitop_project_template.txt File Reference

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: HiTop Project Template

  • STM32F10x Standard Peripherals Project Template

HiTop Project Template

  • STM32100E-EVAL
    • HiTOP Project Template for STM32F10x High-density Value line devices
  • STM32100B-EVAL
    • HiTOP Project Template for STM32F10x Medium-density Value line devices
  • STM3210B-EVAL
    • HiTOP Project Template for STM32F10x Medium-density devices
  • STM3210C-EVAL
    • HiTOP Project Template for STM32F10x Connectivity line devices
  • STM3210E-EVAL
    • HiTOP Project Template for STM32F10x High-density devices
  • STM3210E-EVAL_XL
    • HiTOP Project Template for STM32F10x XL-density devices


STM32F10x Standard Peripherals Firmware Library: main.h Source File

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • I2C
  • IOExpander

I2C/IOExpander/main.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    I2C/IOExpander/main.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Header for main.c module
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __MAIN_H
00024 #define __MAIN_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027
00028 #if !(defined USE_STM32100E_EVAL) && !(defined USE_STM3210C_EVAL)
00029  #error "Please select STM3210C_EVAL or STM32100E_EVAL board For this example"
00030 #endif
00031
00032 #include "stm32f10x.h"
00033 #include "stm32_eval.h"
00034 #include <stdio.h>
00035
00036 #ifdef USE_STM3210C_EVAL
00037  #include "stm3210c_eval_lcd.h"
00038  #include "stm3210c_eval_ioe.h"
00039
00040 #elif defined USE_STM32100E_EVAL
00041  #include "stm32100e_eval_lcd.h"
00042  #include "stm32100e_eval_ioe.h"
00043 #endif
00044
00045 /* Exported types ------------------------------------------------------------*/
00046 /* Exported constants --------------------------------------------------------*/
00047
00048 // #define IOE_POLLING_MODE
00049 #define IOE_INTERRUPT_MODE
00050
00051 /* Exported macro ------------------------------------------------------------*/
00052 /* Exported functions ------------------------------------------------------- */
00053
00054
00055 #endif /* __MAIN_H */
00056
00057 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10xxx FWLib V2.0.3 legacy

Back to main page

STM32F10xxx FWLib V2.0.3 legacy

Copyright 2011 STMicroelectronics

Legacy

The STM32F10xxx FWLib V2.0.3 and all related firmware packages are archived, for legacy purpose, in a single zipped file available for download from STMicroelectronics website from this link.

In addition to this archive file, a library patch STM32F10xFWLib_V2.0.3_Patch1.zip is also provided. This patch fixes all FWLib V2.0.3 limitations.

For complete documentation on STM32 (CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Libraries
  • CMSIS
  • CM3
  • DeviceSupport
  • ST
  • STM32F10x

Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    11-March-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *         and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *         and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *         and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *         and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *         and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *         and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Library: Supported devices and toolchains

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STM32F10x Standard Peripherals Library

Supported devices and toolchains

Copyright 2011 STMicroelectronics

STM32F10x devices peripherals Overview

The following table presents the available peripherals set for each STM32 devices.
Glossary
  • Low density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
 | Low-density | Medium-density | High-density XL-density | Connectivity Line | Value line(*)
ADC | X | X | X | X | X
CAN | X | X | X | X | NA
CEC | NA | NA | NA | NA | X
CRC | X | X | X | X | X
DAC | NA | NA | X | X | X
DBGMCU | X | X | X | X | X
DMA | X | X | X | X | X
Ethernet | NA | NA | NA | X | NA
EXTI | X | X | X | X | X
FLASH | X | X | X | X | X
FSMC | NA | NA | X | NA | X
GPIO | X | X | X | X | X
I2C | X | X | X | X | X
IWDG | X | X | X | X | X
PWR | X | X | X | X | X
RCC | X | X | X | X | X
RTC | X | X | X | X | X
SDIO | NA | NA | X | NA | NA
SPI | X | X | X | X | X
TIM | X | X | X | X | X
USART | X | X | X | X | X
USB FS Device | X | X | X | NA | NA
USB OTG FS | NA | NA | NA | X | NA
WWDG | X | X | X | X | X
(*) Value line: STM32F100xx High-, Medium- and Low-density devices.

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Supported STM32F10x devices

The Standard Peripherals Library supports all STM32F10x family products: Connectivity line, XL-density, High-density, High-density Value line, Medium-density, Medium-density Value line, Low-density and Low-density Value line devices. By using this library it becomes straightforward to move the application firmware from one STM32F10x device to another.

User has only to select which device he will use by controlling preprocessor define declared in stm32f10x.h file ( No selected device by default) then the library will be configured accordingly:

stm32f10x.h

...

                          /* Uncomment the line below according to the target     STM32 device used in your
application
*/

#if !defined (STM32F10X_LD_VL)

                          !defined (STM32F10X_LD)

                          && !defined (STM32F10X_MD_VL)

                          && !defined (STM32F10X_MD) &&     !defined (STM32F10X_HD)

                          && !defined (STM32F10X_HD_VL)

                          && !defined (STM32F10X_CL)

  /* #define STM32F10X_LD_VL */   /*!< STM32 Low density Value line devices */

  /* #define STM32F10X_LD */      /*!< STM32 Low density devices */

  /* #define STM32F10X_MD_VL */   /*!< STM32 Medium density Value line devices */

  /* #define STM32F10X_MD */      /*!< STM32 Medium density devices */
  /* #define STM32F10X_HD_VL */   /*!< STM32 High density Value line devices */
  /* #define STM32F10X_HD */      /*!< STM32 High density devices */

  /* #define STM32F10X_XL */      /*!< STM32 XL density devices */

  /* #define STM32F10X_CL */      /*!< STM32 Connectivity line devices */
#endif

#if!defined
(STM32F10X_LD) && !defined (STM32F10X_LD_VL)&& !defined
(STM32F10X_MD) && !defined(STM32F10X_MD_VL) && !defined
(STM32F10X_HD) &&!defined (STM32F10X_HD_VL) && !defined
(STM32F10X_XL) && !defined (STM32F10X_CL)
#error
"Please select first the target STM32F10x device used in your
application (in stm32f10x.h file)"
#endif

/*  Tip: To avoid modifying this file each time you need to switch between these
        devices, you can define the device in your toolchain compiler preprocessor.

 - Low density Value line devices are STM32F100xx microcontrollers where the Flash

   memory density ranges between 16 and 32 Kbytes.

 - Low density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers
   where the Flash memory density ranges between 16 and 32 Kbytes.

 - Medium density Value line devices are STM32F100xx microcontrollers where the Flash

   memory density ranges between 64 and 128 Kbytes.

 - Medium density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers
   where the Flash memory density ranges between 64 and 128 Kbytes.

 - High density Value line devices are STM32F100xx microcontrollers wherethe Flash memory
   density ranges between 256 and 512 Kbytes.
 - High density devices are STM32F101xx and STM32F103xx microcontrollers where
   the Flash memory density ranges between 256 and 512 Kbytes.
 - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
   the Flash memory density ranges between 512 and 1024 Kbytes.
 - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
  */

...

This define will control the declaration of the following part of the Standard Peripherals library:

IRQ channel definition

Peripheral memory mapping and physical registers address definition

Peripheral pointer declaration and driver header file inclusion

Product miscellaneous configuration: external quartz (HSE) value…

Peripheral with Features w/ different/incompatible implementation across the family

Note : This define doesn’t apply to peripheral drivers, these drivers are always supporting features of the family’s superset.

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Supported toolchains

The Standard Peripherals Library supports the following toolchains:

RealView Microcontroller Development Kit MDK-ARM
Embedded Workbench for ARM EWARM

Raisonance Integrated Development Environment RIDE7

Hitex Development Tools HiTOP

Atolic T rueSTUDIO

Refer to Release_Notes_for_STM32F10x_StdPeriph_Template for further details about the version of each supported toolchain.

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STM32F10x Standard Peripherals Library: Peripheral’s examples

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STM32F10x Standard Peripherals Library: Peripheral’s examples

Copyright 2011 STMicroelectronics

The STM32F10x Standard Peripherals library provides a rich set of examples covering the main features of each peripheral. All the examples are independent from the software toolchain. These examples run on STMicroelectronics STM32100E-EVAL (High-density Value line), STM32100B-EVAL (Medium-density Value line), STM3210C-EVAL (Connectivity line), STM3210E-EVAL (High-density and XL-density) and STM3210B-EVAL (Medium-density) evaluation boards and can be easily tailored to any other supported device and development board. Only source files are provided for each example and user can tailor the provided project template to run the selected example with his preferred toolchain.

Contents

  1. STM32F10x StdPeriph_Lib Examples
  2. What do I need to start successfully with Examples?
  3. How to proceed?

STM32F10x StdPeriph_Lib Examples

Acronym:

  • All : STM32F10x Low-density, Low-density value line, Medium-density, Medium-density value line, High-density, High-density Value line, XL-density and Connectivity line devices.
  • Max frequency: 24MHz on value line devices and 72MHz on other devices.
  • EVAL board : STM32100E-EVAL, STM32100B-EVAL, STM3210B-EVAL, STM3210E-EVAL or STM3210C-EVAL boards.

The package contains the following examples:

ADC - BKP - CAN - CEC - CortexM3 - CRC - DAC - DMA - EXTI - FLASH - FSMC - GPIO - I2C - I2S - IWDG - Lib_DEBUG - NVIC - PWR - RCC - RTC - SDIO - SPI - SysTick - TIM - USART - WWDG

IP/Module | Example
 | Name | Brief Description
ADC | 3 ADCs DMA | This example describes how to use the 3 ADCs in independent conversions. Two of them; ADC1 and ADC3 are transferring continuously converted data using DMA while ADC2 converted data are stored using End of conversion interrupt.
 | ADC1 DMA | This example describes how to use the ADC1 and DMA to transfer continuously converted data from ADC1 to memory.
 | ADC analog watchdog | This example describes how to use the ADC analog watchdog to guard continuously an ADC channel.
 | ADC external lines trigger | This example describes how to trigger ADC regular and injected groups channels conversion using two external line events. Discontinuous mode is enabled for regular group channel conversion and configured to convert one regular channel on each external trigger.
 | ADC regular simultaneous dual mode | This example describes how to use ADC1 and ADC2 in regular simultaneous dual mode. ADC1 is configured to convert channel14 and channel17 regular channels continuously. ADC2 is configured to convert channel11 and channel12 regular channels continuously. The connection between internal Vref and channel17 is enabled for ADC1.
 | ADC TIM trigger and auto-injection | This example describes how to convert ADC regular group channels continuously using TIM1 external trigger and injected group channels using the auto-injected feature.
BKP | Backup Data | This example shows how to store user data in the Backup data registers. As the Backup (BKP) domain still powered by VBAT when VDD is switched off, its contents are not lost if a battery is connected to VBAT pin.
 | BKP Tamper | This example shows how to write/read data to/from Backup data registers and demonstrates the Tamper detection feature.
CAN | LoopBack | This example provides a description of how to set a communication with the CAN in loopback mode.
 | Networking (Ex: Normal) | This example shows how to configure the CAN peripheral to send and receive CAN frames in normal mode. The sent frames are used to control Leds by pressing key push button.
 | Dual CAN | This example shows how to configure the CAN1 and CAN2 peripherals to send and receive CAN frames in normal mode. The sent frames are used to control Leds by pressing KEY or Tamper push buttons.
CEC | CEC Data Exchange using Interrupt | This example shows how to configure the HDMI-CEC peripheral and how to create CEC network providing a high level communication between three different devices using CEC protocol messages.
CortexM3 | Bit Banding | This example shows how to use CortexM3 Bit-Band access to perform atomic read-modify-write and read operations on a variable in SRAM.
 | MPU | This example presents the MPU features on STM32F10x XL-density devices and it can be easily ported to any other STM32 device supporting MPU.
 | Mode Privilege | This example shows how to modify CortexM3 Thread mode privilege access and stack. CortexM3 Thread mode is entered on Reset, and can be entered as a result of an exception return.
CRC | CRC Calculation | This example shows how to use CRC (cyclic redundancy check) calculation unit to get a CRC code of a given buffer of data word (32-bit), based on a fixed generator polynomial (0x4C11DB7).
DAC | DAC dual mode sine wave | This example describes how to use DAC dual channel mode with DMA to generate sine waves on both DAC channels outputs.
 | DAC one channel noise wave | This example describes how to use one DAC channel to generate a signal with noise waves on DAC Channel1 output.
 | DAC one channel DMA escalator | This example describes how to use one DAC channel mode with DMA to generate an escalator signal on DAC channel1 output.
 | DAC two channels triangle wave | This example describes how to use two DAC channels to generate two different signals with triangle waves on each DAC Channel output.
DMA | ADC1 TIM1 | This example provides a description of how to use a DMA channel to transfer continuously a data from a peripheral (ADC1) to another peripheral (TIM1) supporting DMA transfer.
 | FLASH to RAM | This example provides a description of how to use a DMA channel to transfer a word data buffer from FLASH memory to embedded SRAM memory.
 | FSMC | This example provides a description of how to use two DMA channels to transfer a word data buffer from Flash memory to external SRAM memory and to recuperate the written data from external SRAM to be stored in internal SRAM.
 | I2C to RAM | This example provides a description of how to use two DMA channels to transfer a data buffer from memory to I2C2 through I2C1.
 | SPI to RAM | This example provides a description of how to use four DMA channels to transfer a data buffer from memory to SPI_SLAVE through SPI_MASTER and a second data buffer from memory to SPI_MASTER through SPI_SLAVE in full-duplex mode. SPI_MASTER and SPI_SLAVE can be SPI1 and SPI2 or SPI3 and SPI2, depending on the STMicroelectronics EVAL board you are using.
EXTI | EXTI configuration | This example shows how to configure external interrupt lines. In this example, 2 EXTI lines (EXTI0 and EXTI8 or EXTI9) are configured to generate an interrupt on each rising or falling edge. In the interrupt routine a led connected to a specific GPIO pin is toggled.
FLASH | Program | This example provides a description of how to program the STM32F10x FLASH.
 | XL-Density devices FLASH Dual Boot capability | This example demonstrates the dual Flash boot capability of XL-Density devices: boot from Flash memory Bank1 or Bank2.
 | Write Protection | This example provides a description of how to enable and disable the write protection for the STM32F10x FLASH.
FSMC | NAND | This example provides a basic example of how to use the FSMC firmware library and an associate driver to perform erase/read/write operations on the NAND512W3A2 memory mounted on STM3210E-EVAL board.
 | NOR | This example provides a basic example of how to use the FSMC firmware library and an associate driver to perform erase/read/write operations on the M29W128FL, M29W128GL or S29GL128P NOR memories mounted on the STM3210E-EVAL board.
 | NOR_CodeExecute | This directory contains a set of sources files that describes how to build an application to be loaded into the NOR memory mounted on STM3210E-EVAL board then execute it from internal Flash.
 | One-NAND | This example shows how to configure the FSMC to drive the OneNAND memory mounted on STM32100E-EVAL board. In this example a basic example of how to use the FSMC firmware library and an associate driver to perform read/write operations on the KFG1216U2A/B-DIB6 OneNAND memory.
 | SRAM | This example provides a basic example of how to use the FSMC firmware library and an associate driver to perform read/write operations on the IS61WV51216BLL SRAM memory mounted on STM3210E-EVAL board.
 | SRAM DataMemory | This example shows how to use the external SRAM mounted on STM3210E-EVAL or STM32100E-EVAL board as program data memory and internal SRAM for Stack.
GPIO | IO Toggle | GPIO ports are connected on APB2 bus, using BSRRH and BSRRL registers 2 cycles are required to set a pin and another cycle to reset it. So GPIO pins can toggle at AHB clock divided by 4.
 | JTAG Remap | This example provides a short description of how to use the JTAG IOs as standard GPIOs and gives a configuration sequence.
I2C | I2C and M24CXX EEPROM communication | This example provides a basic example of how to use the I2C firmware library and an associate I2C EEPROM driver to communicate with an I2C EEPROM device (here the example is interfacing with M24CXX EEPROMs where XX={01, 02, 04, 08, 16, 32, 64}. I2C peripheral is configured in Master transmitter during write operation and in Master receiver during read operation from I2C EEPROM.
 | I2C and LM75 Temperature Sensor communication | This example provides a description of how to use the I2C to communicate with an STLM75 (or a compatible device) I2C temperature sensor is mounted on the evaluation board and used to get instantaneous external temperature (-55°C to +125°C).
 | I2C and STMPE811 IO Expander communication | This firmware provides an example of configuring and using the IO Expander STMPE811 in order to control input Joystick IOs, output IOs and the Touch Screen feature.
I2S | Interrupt | This example provides a description of how to set a communication between two SPIs in I2S mode using interrupts and performing a transfer from Master to Slave.
 | SPI_I2S_Switch | This example provides a description of how to set a communication between two SPIs in I2S mode, and how to switch between SPI and I2S modes, performing a transfer from Master to Slave in I2S modes then a transfer from master to slave in SPI mode and finally a transfer from Slave to Master in I2S mode.
IWDG | IWDG Reset | This example shows how to update at regular period the IWDG reload counter and how to simulate a software fault generating an MCU IWDG reset on expiry of a programmed time period.
LIB_DEBUG | Run Time Checking | This example demonstrates how to declare dynamic peripherals pointers used for Debug mode. To use Debug mode you have to add the stm32f10x_ip_dbg.c file to your application. This creates a pointer to the peripheral structure in SRAM. Debugging consequently becomes easier and all register settings can be obtained by dumping a peripheral variable.
NVIC | DMA in WFI mode | This example shows how to enter the system to WFI mode with DMA transfer enabled and wake-up from this mode by the DMA End of Transfer interrupt.
 | IRQ Mask | This example demonstrates the use of the Nested Vectored Interrupt Controller (NVIC) IRQ Channels configuration and how to mask/activate different IRQs.
 | IRQ Priority | This example demonstrates the use of the Nested Vectored Interrupt Controller (NVIC).
 | VectorTable Relocation | This example describes how to set the CortexM3 vector table in a specific address other than default using the NVIC_SetVectorTable function from the misc.h/.c driver.
PWR | STANDBY | This example shows how to enter the system to STANDBY mode and wake-up from this mode using: external RESET, RTC Alarm or WKUP pin.
 | STOP | This example shows how to enter the system to STOP mode and wake-up using EXTI Line interrupts. The EXTI Line sources are PB.09/PG.08 and RTC Alarm.
 | PVD | This example shows how to configure the programmable voltage detector using an external interrupt line. In this example, EXTI line 16 is configured to generate an interrupt on each rising or falling edge of the PVD output signal (which indicates that the Vdd voltage is below the PVD threshold).
RCC | Clock configuration | This example shows how to configure the System clock (SYSCLK) to have different frequencies: 24MHz, 36MHz, 48MHz, 56MHz and 72MHz (common frequencies that covers the major of the applications).
RTC | Calendar | This example demonstrates and explains how to use the RTC peripheral. As an application example, it demonstrates how to setup the RTC peripheral, in terms of prescaler and interrupts, to be used to keep time and to generate Second interrupt.
 | LSI_Calib | This example demonstrates and explains how to use the LSI clock source auto calibration to get a precise RTC clock.
SDIO | Micro SD Card | This example provides a basic example of how to use the SDIO firmware library and an associate driver to perform read/write operations on the SD Card memory (SD Card V1.0, V1.1, V2.0 and SDHC (High Capacity) protocol) that could be mounted on the STM3210E-EVAL board.
SPI | CRC | This example provides a description of how to set a communication between two SPIs in full-duplex mode and performs a transfer from Master to Slave and Slave to Master followed by CRC transmission.
 | DMA | This example provides a description of how to set a communication between the two SPIs in simplex mode and performs a transfer from SPI_MASTER in polling mode to the SPI_SLAVE in DMA receive mode.
 | Full Duplex Software NSS | This example provides a description of how to set a communication between SPIy and SPIz in full-duplex mode and performs a transfer from Master to Slave and then Slave to Master in the same application with software NSS management. SPIy and SPIz can be SPI1 and SPI2 or SPI3 and SPI2, depending on the STMicroelectronics EVAL board you are using.
 | SPI_FLASH | This example provides a basic example of how to use the SPI firmware library and an associate SPI FLASH driver to communicate with an M25P64 or M25P128 FLASH.
 | Simplex Interrupt | This example provides a description of how to set a communication between two SPIs in simplex mode and performs a data buffer transfer from SPI_MASTER to SPI_SLAVE using TxE interrupt for master and RxNE interrupt for slave. SPI_MASTER and SPI_SLAVE can be SPI1 and SPI2 or SPI3 and SPI2, depending on the STMicroelectronics EVAL board you are using.
SysTick | Time Base | This example shows how to configure the SysTick to generate a time base equal to 1 ms. The system clock is set to 24 MHz on Value line devices and to 72 MHz on other devices, the SysTick is clocked by the AHB clock (HCLK).
TIM | 6 Steps | This example shows how to configure the TIM1 peripheral to generate 6 Steps. The STM32F10x TIM1 peripheral offers the possibility to program in advance the configuration for the next TIM1 outputs behavior (step) and change the configuration of all the channels at the same time. This operation is possible when the COM (commutation) event is used.
 | 7 PWM Output | This example shows how to configure the TIM1 peripheral to generate 7 PWM signals with 4 different duty cycles (50%, 37.5%, 25% and 12.5%).
 | Cascade Synchro | This example shows how to synchronize TIM peripherals in cascade mode.
 | Complementary Signals | This example shows how to configure the TIM1 peripheral to generate three complementary TIM1 signals, to insert a defined dead time value, to use the break feature and to lock the desired parameters.
 | DMA | This example provides a description of how to use DMA with TIM1 Update request to transfer Data from memory to TIM1 Capture Compare Register3.
 | DMA Burst | This example shows how to update the TIM1 channel1 period and the duty cycle using the TIM1 DMA burst feature.
 | External Trigger Synchro | This example shows how to synchronize TIM peripherals in cascade mode with an external trigger.
 | Input Capture | This example shows how to use the TIM peripheral to measure the frequency of an external signal.
 | OC Active | This example shows how to configure the TIM peripheral to generate four different signals with four different delays.
 | OC Inactive | This example shows how to configure the TIM peripheral in Output Compare Inactive mode with the corresponding Interrupt requests for each channel.
 | OC Toggle | This example shows how to configure the TIM3 peripheral to generate four different signals with four different frequencies.
 | One Pulse | This example shows how to use the TIM peripheral to generate a One pulse Mode after a Rising edge of an external signal is received in Timer Input pin.
 | Parallel Synchro | This example shows how to synchronize TIM peripherals in parallel mode.
 | PWM Input | This example shows how to use the TIM peripheral to measure the frequency and duty cycle of an external signal.
 | PWM Output | This example shows how to configure the TIM peripheral in PWM (Pulse Width Modulation) mode.
 | TIM1 Synchro | This example shows how to synchronize TIM1 and Timers (TIM3 and TIM4) in parallel mode.
 | TIM10 PWM Output | This example shows how to configure the TIM10 peripheral in PWM (Pulse Width Modulation) mode.
 | TIM15 Complementary Signals | This example shows how to configure the TIM15 peripheral to generate one complementary TIM15 signal, to insert a defined dead time value, to use the break feature and to lock the desired parameters.
 | TIM9 OC Toggle | This example shows how to configure the TIM9 peripheral to generate two different signals with two different frequencies.
 | Time Base | This example shows how to configure the TIM peripheral in Output Compare Timing mode with the corresponding Interrupt requests for each channel in order to generate 4 different time bases.
USART | DMA Interrupt | This example provides a basic communication between USARTy and USARTz using DMA capability, flags and interrupts. USARTy and USARTz can be USART1 and USART2 or USART2 and USART3, depending on the STMicroelectronics EVAL board you are using.
 | DMA Polling | This example provides a basic communication between USARTy and USARTz using DMA capability. USARTy and USARTz can be USART1 and USART2 or USART2 and USART3, depending on the STMicroelectronics EVAL board you are using.
 | Half Duplex | This example provides a basic communication between USARTy and USARTz in Half-Duplex mode using flags. USARTy and USARTz can be USART1 and USART2 or USART2 and USART3, depending on the STMicroelectronics EVAL board you are using.
 | Hyperterminal Hardware Flow Control | This example provides a description of how to use the USART with hardware flow control and communicate with the HyperTerminal.
 | Hyperterminal interrupt | This example provides a description of how to use the EVAL_COM1 Transmit and Receive interrupts to communicate with the HyperTerminal.
 | Interrupt | This example provides a basic communication between USARTy and USARTz using interrupts. USARTy and USARTz can be USART1 and USART2 or USART2 and USART3, depending on the STMicroelectronics EVAL board you are using.
 | IrDA Receive | This example provides a basic communication USARTy IrDA receive mode. Four leds are used to show which byte is received. USARTy can be USART3 or USART2 depending on the STMicroelectronics EVAL board you are using.
 | IrDA Transmit | This example provides a basic communication USARTy IrDA transmit mode. Five pins, configured in input floating mode, are used to select the byte to be send at each pin state change. USARTy can be USART3 or USART2 depending on the STMicroelectronics EVAL board you are using.
 | Multi Processor | This example provides a description of how to use the USART in multi-processor mode. USARTy and USARTz can be USART1 and USART2 or USART2 and USART3 respectively, depending on the STMicroelectronics EVAL board you are using.
 | Polling | This example provides a basic communication between USARTy and USARTz using flags. USARTy and USARTz can be USART1 and USART2 or USART2 and USART3, depending on the STMicroelectronics EVAL board you are using.
 | Printf | This example shows how to retarget the C library printf function to the USART. This implementation output the printf message on the HyperTerminal using USARTx. USARTx can be USART1 or USART2 depending on the EVAL board you are using.
 | Smartcard | This example provides a description of how to use the USART in Smartcard mode. The example gives only the possibility to read the ATR and decode it into predefined buffer.
 | Synchronous | This example provides a basic communication between USARTy (Synchronous mode) and SPIy using flags. USARTy and SPIy can be USART1 and SPI1 or USART2 and SPI3, depending on the STMicroelectronics EVAL board you are using.
WWDG | WWDG Reset | This example shows how to update at regular period the WWDG counter and how to simulate a software fault generating an MCU WWDG reset on expiry of a programmed time period.

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What do I need to start successfully with Examples?

Evaluation Board: STMicroelectronics STM32100E-EVAL (High-density Value line), STM32100B-EVAL (Medium-density Value line), STM3210C-EVAL (Connectivity line), STM3210E-EVAL (High-density and XL-density) and STM3210B-EVAL (Medium-density) evaluation boards or any other compatible hardware. To use your own specific hardware, you need simply to adapt the examples hardware configuration to your platform.

Tool chain:

Use your preferred toolchain. MDK-ARM (Keil), EWARM (IAR) , RIDE (Raisonance), HiTOP (Hitex) or TrueSTUDIO (Atollic)

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How to proceed?

Copy the files main.c , main.h (if exists), stm32f10x_it.c, platform_config.h (if exists), stm32f10x_it.h, stm32f10x_conf.h and any other source files from the specified example to your toolchain folder under Project\STM32F10x_StdPeriph_Template. This project folder contains already all toolchain files needed for creating projects for STM32F10x microcontrollers.

Open your preferred toolchain and Set active the project related to the used STM32F10x device and hardware platform:

STM32100E-EVAL: to configure the project for STM32F10x High-density Value line devices
STM32100B-EVAL: to configure the project for STM32F10x Medium-density Value line devices

STM3210C-EVAL: to configure the project for STM32F10x Connectivity line devices

STM3210B-EVAL: to configure the project for STM32F10x Medium-density devices

STM3210E-EVAL: to configure the project for STM32F10x High-density devices

STM32F10X_XL: to configure the project for STM32F10x XL-density devices

Finally compile, load and run the example

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STM32F10x Standard Peripherals Library: Peripheral’s Drivers Description

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STM32F10x Standard Peripherals Library

Peripheral’s Drivers Description

Copyright 2011 STMicroelectronics

STM32F10x Standard Peripheral's Library Architecture

The following figure provides a global view of the STM32F10x Standard Peripherals Library usage and interaction with other firmware conponents.

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Description of the STM32F10x Standard Peripheral's Drivers files

The Standard Peripherals library file inclusions relationship is shown in the following figure:

Each peripheral has a source code file stm32f10x_ppp.c and a header file stm32f10x_ppp.h. The stm32f10x_ppp.c file contains all the firmware functions required to use the PPP peripheral.
A single memory mapping file, stm32f10x.h, is supplied for all peripherals. It contains all the register declarations and bits definition. This is the only file that needs to be included in the user application to interface with the library.
The stm32f10x_conf.h file is used to specify the set of parameters to interface with the library drivers before running any application.

The table bellow lists and describes the different files used by the Standard Peripherals library:

File name | Description
stm32f10x_conf.h | Peripheral’s drivers configuration file The user can enable or disable peripheral header file inclusion by using the template This file can also be used to enable or disable the Library run-time failure detection before compiling the firmware library drivers, through the preprocessor define USE_FULL_ASSERT
stm32f10x_ppp.h | Header file of PPP peripheral This file includes the PPP peripheral function and variable definitions used within these functions.
stm32f10x_ppp.c | Driver source code file of PPP peripheral written in C language
stm32f10x_it.h | Header file including all interrupt handlers prototypes
stm32f10x_it.c | Template source file containing the interrupt service routine (ISR) for CortexM3 exceptions. User can add additional ISR(s) for the used peripheral(s) (for the available peripheral interrupt handler's name, please refer to the startup file startup_stm32f10x_xx.s).

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Description of the STM32F10x CMSIS files

The table below lists and describes the different STM32F10x CMSIS files:

File name

Description

stm32f10x.h

CMSIS Cortex-M3 STM32F10xxx device peripheral access layer header file.

The file is the unique include file that the application programmer is using in the C source code, usually in main.c. This file contains:

  • configuration section that allows to select:

- the device used in the target application

- to use or not the peripheral’s drivers in application code (i.e. code will be based on direct
access to peripheral’s registers rather than drivers API) , this option is controlled by the
#define USE_STDPERIPH_DRIVER
- to change few application-specific parameters such as the HSE crystal frequency

  • data structures and the address mapping for all peripherals
  • peripheral's registers declarations and bits definition
  • macros to access peripheral’s registers hardware

system.stm32f10x.h

CMSIS Cortex-M3 STM32F10xxx device peripheral access layer system header file.

system.stm32f10x.c

CMSIS Cortex-M3 STM32F10xxx device peripheral access layer system source file.

startup_stm32f10x_cl.s

Connectivity line devices startup file.

startup_stm32f10x_xl.s

XL-density devices startup file.

startup_stm32f10x_hd.s

High-density devices startup file.

startup_stm32f10x_hd_vl.s

High-density Value line devices startup file.

startup_stm32f10x_md.s

Medium density devices startup file.

startup_stm32f10x_md_vl.s | Medium density Value line devices startup file.

startup_stm32f10x_ld.s

Low-density devices startup file.

startup_stm32f10x_ld_vl.s | Low-density Value line devices startup file.

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For more details please refer to CMSIS documentation .


STM32F10x Standard Peripherals Drivers MISRA-C 2004 Compliance

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STM32F10x Standard Peripherals Drivers MISRA-C 2004 Compliance

Copyright 2011 STMicroelectronics

TheC programming language is growing in importance and use for embeddedsystems, but when it comes to developing code for safety-criticalsystems, the language has many drawbacks. There are severalunspecified, implementation-defined, and undefined aspects of the Clanguage that make it unsuited for use when developing safety-critical systems.
The Motor Industry Software Reliability Association’s Guidelines for the use of the C language in critical systems MISRA-C 2004 [1] describe a subset of C, suited for use when developing safety-critical systems.
The STM32F10x Standard Peripherals Drivers ( STM32F10x_StdPeriph_Driver ) has been developed to be MISRA-C 2004 compliant .

The following section details how the StdPeriph_Driver complies with MISRA-C 2004 (as described in section 4.4 Claiming compliance of the standard [1]):

  • A compliance matrix has been completed which shows how compliance has been enforced.
  • All the STM32F10x_StdPeriph_Driver C code is compliant with the rules of MISRA-C 2004 or subject documented deviations.
  • Alist of all instances of rules not being followed is being maintained,and for each instance there is an appropriately signed-off deviation.
  • All issues listed in the section "4.2 The programming language and coding context of the standard" [1], that has to be checked during the phase of the firmwaredevelopment process, have been addressed during the development of the STM32F10x Standard Peripherals Drivers and appropriate measures have been taken.

Contents

  1. STM32F10x Standard Peripherals Drivers Compliance
  2. How to check your code for MISRA-C 2004 Compliance?

STM32F10x Standard Peripherals Drivers Compliance

The STM32F10x Standard Peripherals Drivers ( STM32F10x_StdPeriph_Driver )has been checked for MISRA-C 2004 compliance using the IAR C/C++Compiler for ARM. MISRA compliancy applies only to STM32F10x Standard Peripherals Drivers source file, examples and project files are not MISRA compliant.

For the checking tool two options are available:

  • The compiler: IAR C/C++ Compiler for ARM V5.50
  • Manual Checking (code review)

The following table lists the MISRA-C 2004 rules that are violated frequently in the code.

MISRA-C 2004 Rule No | Required/Advisory | Summary | Reason
1.1 | Required | Compiler is configured to allow extensions - all code shall conform to ISO 9899 standard C, with no extensions permitted | IAR compiler extensions are enabled. This was allowed to support new CMSIS types.
5.1 | Required | Identifiers (internal and external) shall not rely on significance of more than 31 characters | Some long parameters names are defined for code readability.
5.4 | Required | Enumerated type mixed with another type - the use of a tag shall agree with its declaration. |
8.1 | Required | Noprototype seen - functions shall always have prototype declarations and the prototype shall be visible at both the function definition | This rule is violated as there is no functions prototypes for __WFI and __WFE macros in the CMSIS layer.
10.1 | Required | The value of an expression of integer type shall not be implicitly converted to a different underlying type. | Complexity
10.6 | Required | A 'U' suffix shall be applied to all constants of 'unsigned' type | The "stdint.h" defined types are used to be CMSIS compliant.
11.2 | Required | Conversionsshall not be performed between a pointer to object and any type otherthan an integral type, another pointer to object type or a pointer to void. | Needed when addressing memory mapped registers
11.3 | Advisory | A cast should not be performed between a pointer type and an integral type. | Needed when addressing memory mapped registers
16.7 | Advisory | Apointer parameter in a function prototype should be declared as pointer to const if the pointer is not used to modify the addressed object. |
19.1 | Advisory | #include statements in a file shall only be preceded by other preprocessor directives or comments | This rule was violated to be inline with the CMSIS architecture.

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How to check your code for MISRA-C 2004 Compliance?

Thedefault IAR project template provided with the STM32F10x StandardPeripherals Library is already pre-configured for MISRA-C 2004 Compliance. Then, user has to enable the MISRA-C 2004 checker if needed.

Toenable the IAR MISRA-C 2004 Checker, go to Project->Options (ALT+F7)and then in "General Options" Category select the "MISRA-C:2004" tab andcheck the "Enable MISRA-C" box. With the default EWARM template project, all violated rules described above are unchecked.

To check your code for MISRA-C 2004 compliance using the IAR MISRA-C Checker, please follow the following steps

Enable the IAR MISRA-C 2004 Checker

Inside the core_cm3.h file add the following directive " #pragma system_include " to prevent the MISRA-C checker to check this file.

Uncomment the "USE_FULL_ASSERT" inside the stm32f10x_conf.h file

Note: Only the STM32F10x Standard Peripherals Drivers are MISRA-C 2004 Compliant.

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[1]MISRA-C 2004 Guidelines for the use of the C language in critical systems, Motor Industry Software Reliability Association, October 2004

Forcomplete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Library: Overview

Copyright 2011 STMicroelectronics

The STM32F10x Standard Peripherals library covers 3 abstraction levels, and includes:

A complete register address mapping with all bits, bit fields and registers declared in C. This avoids a cumbersome task and more important, it brings the benefits of a bug free reference mapping file, speeding up the early project phase.

A collection of routines and data structures which covers all peripheral functions (drivers with common API). It can directly be used as a reference framework, since it also includes macros for supporting core-related intrinsic features and common constants and data types definition.

A set of examples covering all available peripherals with template projects for the most common development toolchains. With the appropriate hardware evaluation board, this allows to get started with a brand new micro within few hours.

Each driver consists of a set of functions covering all peripheral functionalities. The development of each driver is driven by a common API (application programming interface) which standardizes the driver structure, the functions and the parameter names.
The driver source code is developed in ‘Strict ANSI-C’ (relaxed ANSI-C for projects and example files). It is fully documented and is MISRA-C 2004 compliant. Writing the whole library in ‘Strict ANSI-C’ makes it independent from the software toolchain. Only the start-up files depend on the toolchain.

The Standard Peripherals Library implements run-time failure detection by checking the input values for all library functions. Such dynamic checking contributes towards enhancing the robustness of the software. Run-time detection is suitable for user application development and debugging. It adds an overhead which can be removed from the final application code to minimize code size and execution speed. For more details refer to Section Run-time checking.

Since the Standard Peripherals Library is generic and covers all peripheral functionalities, the size and/or execution speed of the application code may not be optimized. For many applications, the library may be used as is. However, for applications having tough constraints in terms of code size and/or execution speed, the library drivers should be used as a reference on how to configure the peripheral and tailor them to specific application requirements.

Note: The performance of application code, in terms of size and/or speed, depends also from the C compiler optimization settings. To help make the application code smaller, faster or balanced between size and speed you should consider fine-tuning the optimizations according to your application needs. For more information please refer to your C compiler documentation.

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STM32F10x Standard Peripherals Library: Package description

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STM32F10x Standard Peripherals Library: Package description

Copyright 2011 STMicroelectronics

Package description

The STM32F10x Standard Peripherals library is supplied in one single zip file. The extraction of the zip file generates one folder, STM32F10x_StdPeriph_Lib_VX.Y.Z, which contains the following subfolders:

_htmresc folder
This Folder contains all package html page resources.

Libraries folder
This folder contains all CMSIS files and STM32F10x Standard Peripheral's Drivers.

CMSIS subfolder
This folder contains the STM32F10xxx CMSIS files: device peripheral access layer and core peripheral access layer

STM32F10x_StdPeriph_Driver subfolder
This folder contains all the subdirectories and files that make up the core of the library:

inc sub-folder contains the Peripheral's Drivers header files. They do not need to be modified by the user:

misc.h: all the functions prototypes for the miscellaneous firmware library functions.

stm32f10x_ppp.h (one header file per peripheral): Function prototypes, data structures and enumeration.

src sub-folder contains the Peripheral's Drivers source files. They do not need to be modified by the user:

misc.c: all the miscellaneous firmware functions (add-on to CMSIS functions)..

stm32f10x_ppp.c (one source file per peripheral): Function bodies of each peripheral.

All STM32F10x Standard Peripheral's drivers are coded in Strict ANSI-C and are independent from the software toolchain.

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Project folder
This folder contains template projects and STM32F10x Standard Peripheral's examples

STM32F10x_StdPeriph_Examples subfolder , complete list of available examples

This folder contains, for each peripheral sub-folder, the minimum set of files needed to run a typical example on how to use this peripheral:
readme.txt: brief text file describing the example and how to make it work.
stm32f10x_conf.h: header file allowing to enable/disable the peripheral's drivers header files inclusion.
stm32f10x_it.c: source file containing the interrupt handlers (the function bodies may be emptied if not used).
stm32f10x_it.h: header file including all interrupt handler prototypes.
main.c: example of code.
platform_config.h: (if exists) STMicroelectronics Evaluation board specific configuration file.
 system_stm32f10x.c: this file provide functions to setup the STM32 system: Configures the System clock frequency, AHB/APBx
prescalers and Flash settings.

STM32F10x_StdPeriph_Template subfolder

This folder contains standard template projects for EWARM, MDK-ARM, RIDE, HiTO and TrueSTUDIO toolchains that compile the needed

STM32F10x Standard Peripheral's drivers plus all the user-modifiable files that are necessary to create a new project:
stm32f10x_conf.h: configuration header file.
stm32f10x_it.c: source file containing the interrupt handlers (the function bodies are empty in this template).
stm32f10x_it.h: header file including all interrupt handlers prototypes.
main.c: main program body.
 system_stm32f10x.c: this file provide functions to setup the STM32 system: Configures the System clock frequency, AHB/APBx
prescalers and Flash settings.

EWARM, MDK-ARM, RIDE, HiTOP subfolders: contains respectively the template project for EWARM, MDK-ARM, RIDE, HiTOP

and TrueSTUDIO toolchains (for more details, refer to readme file provided within the template project).

Two workspaces are provided for each project template:

- STM32100E-EVAL: to configure the project for STM32 High-density Value line devices
- STM32100B-EVAL: to configure the project for STM32 Medium-density Value line devices

- STM3210C-EVAL: to configure the project for STM32 Connectivity line devices

- STM3210E-EVAL: to configure the project for STM32 High-density devices

- STM3210B-EVAL: to configure the project for STM32 Medium-density devices

- STM32F10X_XL: to configure the project for STM32 XL-density devices

Utilities folder

STM32_EVAL Implement an abstraction layer to interact with the Human Interface resources; buttons, LEDs, LCD and COM ports (USARTs) available on STMicroelectronics STM32100E-EVAL (High-density Value line), STM32100B-EVAL (Medium-density Value line), STMicroelectronics STM3210C-EVAL (Connectivity line), STM3210E-EVAL (High-density and XL-density) and STM3210B-EVAL (Medium-density) evaluation boards. The stm32_eval.c driver provides a common API to interact with buttons, LEDs and COM ports, while these resources hardware definitions is made in the header file of each evaluation board (stm3210x_eval.h). A common API is provided to manage the LCD across the supported boards, with a separate driver for each board stm3210x_eval_lcd.c.

Common: contains common part for all STM32 EVAL board containing: Leds, push-buttons, COM ports, serial I2C EEPROM memory

(sEE), serial SPI FLASH memory (sFLASH), Temperature sensor (LM75), SD Card memories on SPI and SDIO interfaces.

STM32100E_EVAL: contains LEDs, buttons and COM ports hardware definition file, LCD driver, IO Expander, FSMC SRAM driver,

FSMC OneNAND driver and HDMI CEC driver for this board.
STM32100B_EVAL: contains LEDs, buttons and COM ports hardware definition file, LCD driver and HDMI CEC driver for this board.

STM3210C_EVAL: contains LEDs, buttons and COM ports hardware definition file, IO Expander and LCD driver for this board.
STM3210E_EVAL: contains LEDs, buttons and COM ports hardware definition file, LCD driver, FSMC SRAM driver, FSMC NOR driver
and FSMC NAND driver for this board.
STM3210B_EVAL: contains LEDs, buttons and COM ports hardware definition file and LCD driver for this board.

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STM32F10x Standard Peripherals Library: Coding rules and conventions

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STM32F10x Standard Peripherals Library: Coding rules and conventions

Copyright 2011 STMicroelectronics

The STM32F10x Standard Peripherals Library uses rules and conventions described in the sections below.

Acronyms

The Table below describes the acronyms used in the firmware library.

Acronym | Peripheral/unit
ADC | Analog/digital converter
BKP | Backup registers
CAN | Controller area network
CEC | Consumer Electronics Control
CRC | CRC calculation unit
DAC | Digital to analog converter
DBGMCU | Debug MCU
DMA | DMA controller
EXTI | External interrupt/event controller
FSMC | Flexible static memory controller
FLASH | Flash memory
GPIO | General purpose I/O
I2C | Inter-integrated circuit
I2S | Inter-integrated sound
IWDG | Independent watchdog
NVIC | Nested vectored interrupt controller
PWR | Power controller
RCC | Reset and clock controller
RTC | Reset and clock controller
SDIO | SDIO interface
SPI | Serial peripheral interface
SysTick | System tick timer
TIM | Advanced-control, general-purpose or basic timer
USART | Universal synchronous asynchronous receiver transmitter
WWDG | Window watchdog

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Naming conventions

The STM32F10x Standard Peripherals Library uses the following naming conventions:

  • PPP refers to any peripheral acronym, for example ADC.
  • System and source/header file names are preceded by the prefix ‘stm32f10x_’.
  • Constants used in one file are defined within this file. A constant used in more than one file is defined in a header file. All constants are written in upper case.
  • Registers are considered as constants. Their names are in upper case. In most cases, the same acronyms as in the STM32F10x reference manual document are used.
  • Names of peripheral’s functions are preceded by the corresponding peripheral acronym in upper case followed by an underscore. The first letter in each word is in upper case, for example USART_SendData. Only one underscore is allowed in a function name to separate the peripheral acronym from the rest of the function name.
  • Functions used to initialize the PPP peripheral according to parameters specified in PPP_InitTypeDef are named PPP_Init, for example TIM_Init.
  • Functions used to reset the PPP peripheral registers to their default values are named PPP_DeInit, for example TIM_DeInit.
  • Functions used to fill the PPP_InitTypeDef structure with the reset values of each member are named PPP_StructInit, for example USART_StructInit.
  • Functions used to enable or disable the specified PPP peripheral are named PPP_Cmd, for example USART_Cmd.
  • Functions used to enable or disable an interrupt source of the specified PPP peripheral are named PPP_ITConfig, for example RCC_ITConfig.
  • Functions used to enable or disable the DMA interface of the specified PPP peripheral are named PPP_DMAConfig, for example TIM_DMAConfig.
  • Functions used to configure a peripheral function always end with the string ‘Config’, for example GPIO_PinRemapConfig.
  • Functions used to check whether the specified PPP flag is set or reset are named PPP_GetFlagStatus, for example I2C_GetFlagStatus.
  • Functions used to clear a PPP flag are named PPP_ClearFlag, for example I2C_ClearFlag.
  • Functions used to check whether the specified PPP interrupt has occurred or not are named PPP_GetITStatus, for example I2C_GetITStatus.
  • Functions used to clear a PPP interrupt pending bit are named PPP_ClearITPendingBit, for example I2C_ClearITPendingBit.

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Coding rules

This section describes the coding rules used in the Standard Peripherals library.

Variable types

Specific variable types are already defined with a fixed type and size. These types are defined in the file stm32f10x.h

typedef enum
{
  FALSE = 0,
  TRUE = !FALSE
}
bool;

typedef enum {
  RESET = 0,
  SET = !RESET
}
FlagStatus, ITStatus, BitStatus;

typedef enum {
  DISABLE = 0,
  ENABLE = !DISABLE
}
FunctionalState;

typedef enum {
  ERROR = 0,
  SUCCESS = !ERROR
}
ErrorStatus;

Peripheral’s registers

Peripheral’s registers are accessed through a pointer of structure. Each peripheral has its own structure and pointer. All the structures and declarations are defined in the stm32f10x.h file.

Registers structure
The example below illustrates the Serial Peripheral Interface (SPI) registers structure declaration:

/**
  * @brief Serial Peripheral Interface
  */

typedef struct
{
  __IO uint16_t CR1;
  uint16_t  RESERVED0;
  __IO uint16_t CR2;
  uint16_t  RESERVED1;
  __IO uint16_t SR;
  uint16_t  RESERVED2;
  __IO uint16_t DR;
  uint16_t  RESERVED3;
  __IO uint16_t CRCPR;
  uint16_t  RESERVED4;
  __IO uint16_t RXCRCR;
  uint16_t  RESERVED5;
  __IO uint16_t TXCRCR;
  uint16_t  RESERVED6;
  __IO uint16_t I2SCFGR;
  uint16_t  RESERVED7;
  __IO uint16_t I2SPR;
  uint16_t  RESERVED8;
} SPI_TypeDef;

Register names are the register acronyms written in upper case for each peripheral.
RESERVED indicates a reserved field (i being an integer that indexes the reserved field).

Peripheral declaration
The following example shows the declaration of the SPI peripheral:

#define PERIPH_BASE ((u32)0x40000000)
#define APB1PERIPH_BASE PERIPH_BASE
#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
...
/* SPI2 Base Address definition*/
#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)

The peripheral registers are accessed as follows:

SPI1->CR1 = 0x0001;

Each peripheral has several dedicated registers which contain different flags. Registers are defined within a dedicated structure for each peripheral. Flags are defined as acronyms written in upper case and preceded by ‘PPP_FLAG_’. Flag definition is adapted to each peripheral case and defined in stm32f10x_ppp.h file.

Registers bits
All the peripheral registers bits are defined as constants in the stm32f10x.h file. They are defined as acronyms written in upper-case into the form:

PPP_<register_name>_<bit_name>

Example:

#define SPI_CR2_RXDMAEN                     ((uint8_t)0x01)  /*!<Rx Buffer DMA Enable */
#define SPI_CR2_TXDMAEN                     ((uint8_t)0x02)  /*!<Tx Buffer DMA Enable */
#define SPI_CR2_SSOE                        ((uint8_t)0x04)  /*!<SS Output Enable */
#define SPI_CR2_ERRIE                       ((uint8_t)0x20)  /*!<Error Interrupt Enable */
#define SPI_CR2_RXNEIE                     ((uint8_t)0x40)  /*!<RX buffer Not Empty Interrupt Enable */
#define SPI_CR2_TXEIE                       ((uint8_t)0x80)  /*!<Tx buffer Empty Interrupt Enable */

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Bit-Banding

The Cortex-M3 memory map includes two bit-band memory regions. These regions map each word in an alias region of memory to a bit in a bit-band region of memory. Writing to a word in the alias region has the same effect as a read-modify-write operation on the targeted bit in the bit-band region.

All the STM32F10x peripheral registers are mapped in a bit-band region. This feature is consequently intensively used in functions which perform single bit set/reset in order to reduce and optimize code size.

  1. Mapping formula

The mapping formula shows how to link each word in the alias region to a corresponding target bit in the bit-band region. The mapping formula is given below:

bit_word_offset = (byte_offset x 32) + (bit_number + 4)
bit_word_addr = bit_band_base + bit_word_offse t

where:

  • bit_word_offset is the position of the target bit in the bit-band memory region
  • bit_word_addr is the address of the word in the alias memory region that maps to the targeted bit.
  • bit_band_base is the starting address of the alias region
  • byte_offset is the number of the byte in the bit-band region that contains the targeted bit
  • bit_number is the bit position (0-7) of the targeted bit.

  2. Example of implementation

The following example shows how to map the PLLON[24] bit of RCC_CR register in the alias region:

/* Peripheral base address in the bit-band region */
#define PERIPH_BASE ((u32)0x40000000)
/* Peripheral address in the alias region */
#define PERIPH_BB_BASE ((u32)0x42000000)
/* ----- RCC registers bit address in the alias region ------ */
#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
/* --- CR Register ---*/
/* Alias word address of PLLON bit */
#define CR_OFFSET (RCC_OFFSET + 0x00)
#define PLLON_BitNumber 0x18
#define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32
(PLLON_BitNumber * 4))
To code a function which enables/disables the PLL, the usual method is the following:
...
#define CR_PLLON_Set ((u32)0x01000000)
#define CR_PLLON_Reset ((u32)0xFEFFFFFF)
...
void RCC_PLLCmd(FunctionalState NewState)
{
if (NewState != DISABLE)
{ /* Enable PLL */
RCC->CR |= CR_PLLON_Set;
}
else
{ /* Disable PLL */
RCC->CR &= CR_PLLON_Reset;
}
}
Using bit-band access this function will be coded as follows:
void RCC_PLLCmd(FunctionalState NewState)
{
*(vu32 *) CR_PLLON_BB = (u32)NewState;
}

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Run-time checking

The firmware library implements run-time failure detection by checking the input values of all library functions. The run-time checking is achieved by using an assert_param macro. This macro is used in all library functions which have at least an input parameter. It allows the user to check that the input value lies within the defined parameter values.

EXTI_Init function example

stm32f10x_exti.c
void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct)
{
  /* Check the parameters */
  assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode));
  assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger));
  assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line));
  assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd));
...
}

stm32f10x_exti.h
#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))
#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \
                                  ((TRIGGER) == EXTI_Trigger_Falling) || \
                                  ((TRIGGER) == EXTI_Trigger_Rising_Falling))

#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFFF00000) == 0x00) && ((LINE) != (uint16_t)0x00))

If the expression passed to the assert_param macro is false, the assert_failed function is called, otherwise nothing happens.

Two implementation of assert_failed function are provided, depending on USE_FULL_ASSERT define (declared in stm32f10x_conf.h file).

  • "#define USE_FULL_ASSERT 1 " line is uncommented, if the expression passed to the assert_param macro is false, the assert_failed function will have as input the name of the source file and the source line number of the call that failed.
  • "#define FULL_ASSERT 1" line is commented, if the expression passed to the assert_param macro is true, the assert_failed function will have takes no does not returns the name of the source file and the source line number of the call that failed.

The assert_param macro is implemented in stm32f10x_conf.h as follows:

#ifdef  USE_FULL_ASSERT
/**
  * @brief  The assert_param macro is used for function's parameters check.
  * @param expr: If expr is false, it calls assert_failed function
  *   which reports the name of the source file and the source
  *   line number of the call that failed.
  *   If expr is true, it returns no value.
  * @retval : None
  */
  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
   void assert_failed(uint8_t* file, uint32_t line);
#else
   #define assert_param(expr) ((void)0)
#endif /* USE_FULL_ASSERT */

The assert_failed function is implemented in the main.c file or in any other user C files and can be modified by the user in order to take action when an error occurs.

#ifdef  USE_FULL_ASSERT
/**
  * @brief  Reports the name of the source file and the source line number
  *         where the assert_param error has occurred.
  * @param file: pointer to the source file name
  * @param line: assert_param error line source number
  * @retval : None
  */
void assert_failed(uint8_t* file, uint32_t line)
{
  /* User can add his own implementation to report the file name and line number,
     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */

  /* Infinite loop */
  while (1)
  {
  }
}
#endif

It is recommended to use run-time checking during application code development and debugging, and to remove it from the final application to improve code size and speed (because of the overhead it introduces).
However if the user wants to keep this functionality in his final application, he can re-use the assert_param macro defined within the library to test the parameter values before calling the library functions.

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For complete documentation on STM32 (CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Library: How to use the Library

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STM32F10x Standard Peripherals Library

How to use the Library

Copyright 2011 STMicroelectronics

How to use the Standard Peripherals Library

Create a project and setup all your toolchain's start-up files (or use the template project provided within the Library, under
Project\STM32F10x_StdPeriph_Template)

Select the corresponding startup file depending of the used device:

- startup_stm32f10x_ld_vl.s: for STM32 Low density Value line devices

- startup_stm32f10x_ld.s: for STM32 Low density devices

- startup_stm32f10x_md_vl.s: for STM32 Medium density Value line devices

- startup_stm32f10x_md.s: for STM32 Medium density devices

- startup_stm32f10x_hd_vl.s: for STM32 High density Value line devices
- startup_stm32f10x_hd.s: for STM32 High density devices

- startup_stm32f10x_xl.s: for STM32 XL density devices

- startup_stm32f10x_cl.s: for STM32 Connectivity line devices

The Library entry point is stm32f10x.h (under Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x), user has to include it in the application main and configure it:

Select the target product family to be used, comment/uncomment the right define:

 #if
!defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)
&& !defined (STM32F10X_MD) && !defined
(STM32F10X_MD_VL) && !defined (STM32F10X_HD) &&
!defined (STM32F10X_XL) && !defined (STM32F10X_CL)
/* #define STM32F10X_LD */          /*!< STM32F10X_LD: STM32 Low density devices */
/* #define STM32F10X_LD_VL */    /*!< STM32F10X_LD_VL: STM32 Low density Value Line devices */
/* #define STM32F10X_MD */         /*!< STM32F10X_MD: STM32 Medium density devices */
/* #define STM32F10X_MD_VL */   /*!< STM32F10X_MD_VL: STM32 Medium density Value Line devices */

/* #define STM32F10X_HD_VL */
 /*!< STM32F10X_HD: STM32 High density Value line devices */
/* #define STM32F10X_HD */
 /*!< STM32F10X_HD: STM32 High density devices */
/* #define STM32F10X_XL  */
     /*!< STM32F10X_CL: STM32 XL-density devices */
/* #define STM32F10X_CL */
/*!< STM32F10X_CL: STM32 Connectivity line devices */
#endif

Then user has the choice to use or not the Peripheral’s Drivers

- Case1: application code based on Standard Peripheral’s drivers API (files under Libraries\STM32F10x_StdPeriph_Driver)

- Uncomment #define USE_PERIPH_LIBRARY (default)

- In stm32f10x_conf.h file, select the peripherals to include their header file

- Use Peripheral’s drivers API to build the application; refer to next section for more information.

- In addition to the Peripheral’s drivers you can reuse/adapt the rich set of examples available within the Library to speed

your development, this allow you to started within few hours. Refer to the complete list of available examples

- Case2: application code based on Peripheral’s registers direct access

- Comment #define USE_PERIPH_LIBRARY

- Use Peripheral’s registers structure and bits definition available within stm32f10x.h to build the application

Add the system_stm32f10x.c (under Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x) file in your application, this file provide functions to setup the STM32 system: configure the PLL, system clock and initialize the Embedded Flash Interface. This file provides multiple choice for the system clock frequency, you can selected the frequency needed for your application from the list below (common frequencies that covers the major of the applications):

#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
/* #define SYSCLK_FREQ_HSE HSE_Value */
#define SYSCLK_FREQ_24MHz 24000000
#else
/* #define SYSCLK_FREQ_HSE HSE_Value */
/* #define SYSCLK_FREQ_24MHz 24000000 */
/* #define SYSCLK_FREQ_36MHz 36000000 */
/* #define SYSCLK_FREQ_48MHz 48000000 */
/* #define SYSCLK_FREQ_56MHz 56000000 */
#define SYSCLK_FREQ_72MHz 72000000
#endif

Note: The System clock configuration functions provided within this file assume that:

- For Low-density Value line, Low-density, Medium-density Value line, Medium-density, High-density Value line and High-density devices

an external 8MHz crystal is used to drive the System clock.

- For Connectivity line devices an external 25MHz crystal is used to drive the System clock.

If you are using different crystal you have to change the value of the define HSE_VALUE in stm32f10x.h file and adapt those functions

accordingly.

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Peripheral initialization and configuration

This section describes step-by-step how to initialize and configure a peripheral using the Peripheral’s Drivers. The peripheral will be referred to as PPP.

  1. In the main application file, declare a PPP_InitTypeDef structure, for example: PPP_InitTypeDef PPP_InitStructure;

The PPP_InitStructure is a working variable located in data memory area. It allows initializing one or more PPP instances.

  2. Fill the PPP_InitStructure variable with the allowed values of the structure member.

There are two ways of doing this:

  • Configuring the whole structure by following the procedure described below:

PPP_InitStructure.member1 = val1;
PPP_InitStructure.member2 = val2;
PPP_InitStructure.memberN = valN; /* where N is the number of the structure
    members */

The previous initialization step can be merged in one single line to optimize the code size:

PPP_InitTypeDef PPP_InitStructure = { val1, val2,.., valN}

  • Configuring only a few members of the structure: in this case the user should modify the PPP_InitStructure variable that has been already filled by a call to the PPP_StructInit(..) function. This ensures that the other members of the PPP_InitStructure variable are initialized to the appropriate values (in most cases their default values).

PPP_StructInit(&PPP_InitStructure);
PP_InitStructure.memberX = valX;
PPP_InitStructure.memberY = valY; /*where X and Y are the members the user
    wants to configure*/

  3. Initialize the PPP peripheral by calling the PPP_Init(..) function.

PPP_Init(PPP, &PPP_InitStructure);

  4. At this stage the PPP peripheral is initialized and can be enabled by making a call to PPP_Cmd(..) function.

PPP_Cmd(PPP, ENABLE);

The PPP peripheral can then be used through a set of dedicated functions. These functions are specific to the peripheral.

Note:

  1. Before configuring a peripheral, its clock must be enabled by calling one of the following functions:

RCC_AHBPeriphClockCmd(RCC_AHBPeriph_PPPx, ENABLE);

RCC_APB2PeriphClockCmd(RCC_APB2Periph_PPPx, ENABLE);

RCC_APB1PeriphClockCmd(RCC_APB1Periph_PPPx, ENABLE);

  2. PPP_DeInit(..) function can be used to set all PPP peripheral registers to their default values:

PPP_DeInit(PPP);

  3. To modify the peripheral settings after configuring the peripheral, the user can proceed as follows:

PPP_InitStucture.memberX = valX;
PPP_InitStructure.memberY = valY; /* where X and Y are the only members that user wants to modify*/
PPP_Init(PPP, &PPP_InitStructure);

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STM32F10x Standard Peripherals Library: Limitation

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STM32F10x Standard Peripherals Library: Limitations

Copyright 2011 STMicroelectronics

Limitations

No known limitation in this version.

For complete documentation on STM32 (CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: main_page.txt File Reference

  • File List
  • Globals

main_page.txt File Reference

STM32F10x Standard Peripherals Library: Footer

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STM32F10x Standard Peripherals Firmware Library: note.txt File Reference

  • File List
  • Globals

note.txt File Reference

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STM32F10x Standard Peripherals Firmware Library: MDK-ARM Project Template

  • STM32F10x Standard Peripherals Project Template

MDK-ARM Project Template

  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
  * @file    readme.txt
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   This sub directory contains all the user modifiable files needed
  *          to create a new project linked with the STM32F10x Standard Peripheral
  *          Library and working with RealView MDK-ARM toolchain (Version 4.12 and later).
  ******************************************************************************
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
  * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
  * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
  * CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
  * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  ******************************************************************************
Directory contents
  • Project.Uv2/.Opt: A pre-configured project file with the provided library structure that produces an executable image with MDK-ARM

Enabling "Options for Target 'Output' Browser Information" is useful for quick source files navigation but may slow the compilation time.

Note:
the Note for MDK-ARM file contains the needed steps to follow when using the default startup file provided by MDK-ARM when creating new projects.
How to use it ?
  • Open the Project.uvproj project
  • In the build toolbar select the project config:
    • STM32100B-EVAL: to configure the project for STM32 Medium-density Value line devices
      Note:
      The needed define symbols for this config are already declared in the preprocessor section: USE_STDPERIPH_DRIVER, STM32F10X_MD_VL, USE_STM32100B_EVAL
    • STM3210C-EVAL: to configure the project for STM32 Connectivity line devices
      Note:
      The needed define symbols for this config are already declared in the preprocessor section: USE_STDPERIPH_DRIVER, STM32F10X_CL, USE_STM3210C_EVAL
    • STM3210B-EVAL: to configure the project for STM32 Medium-density devices
      Note:
      The needed define symbols for this config are already declared in the preprocessor section: USE_STDPERIPH_DRIVER, STM32F10X_MD, USE_STM3210B_EVAL
    • STM3210E-EVAL: to configure the project for STM32 High-density devices
      Note:
      The needed define symbols for this config are already declared in the preprocessor section: USE_STDPERIPH_DRIVER, STM32F10X_HD, USE_STM3210E_EVAL
    • STM3210E-EVAL_XL: to configure the project for STM32 XL-density devices
      Note:
      The needed define symbols for this config are already declared in the preprocessor section: USE_STDPERIPH_DRIVER, STM32F10X_XL, USE_STM3210E_EVAL
    • STM32100E-EVAL: to configure the project for STM32 High-density Value line devices
      Note:
      The needed define symbols for this config are already declared in the preprocessor section: USE_STDPERIPH_DRIVER, STM32F10X_HD_VL, USE_STM32100E_EVAL
  • Rebuild all files: Project->Rebuild all target files
  • Load project image: Debug->Start/Stop Debug Session
  • Run program: Debug->Run (F5)
Note:
  • Low-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
  • Medium-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  • High-density Value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 512 and 1024 Kbytes.
  • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

© COPYRIGHT 2011 STMicroelectronics

STM32F10x Standard Peripherals Library: Footer

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STM32F10x Standard Peripherals Firmware Library: misc.c Source File

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Libraries
  • STM32F10x_StdPeriph_Driver
  • src

misc.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    misc.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    11-March-2011
00007   * @brief   This file provides all the miscellaneous firmware functions (add-on
00008   *          to CMSIS functions).
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00013   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00014   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00015   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00016   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00017   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00018   *
00019   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00020   ******************************************************************************
00021   */
00022
00023 /* Includes ------------------------------------------------------------------*/
00024 #include "misc.h"
00025
00026 /** @addtogroup STM32F10x_StdPeriph_Driver
00027   * @{
00028   */
00029
00030 /** @defgroup MISC
00031   * @brief MISC driver modules
00032   * @{
00033   */
00034
00035 /** @defgroup MISC_Private_TypesDefinitions
00036   * @{
00037   */
00038
00039 /**
00040   * @}
00041   */
00042
00043 /** @defgroup MISC_Private_Defines
00044   * @{
00045   */
00046
00047 #define AIRCR_VECTKEY_MASK    ((uint32_t)0x05FA0000)
00048 /**
00049   * @}
00050   */
00051
00052 /** @defgroup MISC_Private_Macros
00053   * @{
00054   */
00055
00056 /**
00057   * @}
00058   */
00059
00060 /** @defgroup MISC_Private_Variables
00061   * @{
00062   */
00063
00064 /**
00065   * @}
00066   */
00067
00068 /** @defgroup MISC_Private_FunctionPrototypes
00069   * @{
00070   */
00071
00072 /**
00073   * @}
00074   */
00075
00076 /** @defgroup MISC_Private_Functions
00077   * @{
00078   */
00079
00080 /**
00081   * @brief  Configures the priority grouping: pre-emption priority and subpriority.
00082   * @param  NVIC_PriorityGroup: specifies the priority grouping bits length.
00083   *   This parameter can be one of the following values:
00084   *     @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority
00085   *                                4 bits for subpriority
00086   *     @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority
00087   *                                3 bits for subpriority
00088   *     @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority
00089   *                                2 bits for subpriority
00090   *     @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority
00091   *                                1 bits for subpriority
00092   *     @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority
00093   *                                0 bits for subpriority
00094   * @retval None
00095   */
00096 void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
00097 {
00098   /* Check the parameters */
00099   assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));
00100
00101   /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */
00102   SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;
00103 }
00104
00105 /**
00106   * @brief  Initializes the NVIC peripheral according to the specified
00107   *         parameters in the NVIC_InitStruct.
00108   * @param  NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains
00109   *         the configuration information for the specified NVIC peripheral.
00110   * @retval None
00111   */
00112 void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)
00113 {
00114   uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F;
00115
00116   /* Check the parameters */
00117   assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));
00118   assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority));
00119   assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));
00120
00121   if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
00122   {
00123     /* Compute the Corresponding IRQ Priority --------------------------------*/
00124     tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08;
00125     tmppre = (0x4 - tmppriority);
00126     tmpsub = tmpsub >> tmppriority;
00127
00128     tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;
00129     tmppriority |=  NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub;
00130     tmppriority = tmppriority << 0x04;
00131
00132     NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority;
00133
00134     /* Enable the Selected IRQ Channels --------------------------------------*/
00135     NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
00136       (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
00137   }
00138   else
00139   {
00140     /* Disable the Selected IRQ Channels -------------------------------------*/
00141     NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
00142       (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
00143   }
00144 }
00145
00146 /**
00147   * @brief  Sets the vector table location and Offset.
00148   * @param  NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory.
00149   *   This parameter can be one of the following values:
00150   *     @arg NVIC_VectTab_RAM
00151   *     @arg NVIC_VectTab_FLASH
00152   * @param  Offset: Vector Table base offset field. This value must be a multiple
00153   *         of 0x200.
00154   * @retval None
00155   */
00156 void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)
00157 {
00158   /* Check the parameters */
00159   assert_param(IS_NVIC_VECTTAB(NVIC_VectTab));
00160   assert_param(IS_NVIC_OFFSET(Offset));
00161
00162   SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);
00163 }
00164
00165 /**
00166   * @brief  Selects the condition for the system to enter low power mode.
00167   * @param  LowPowerMode: Specifies the new mode for the system to enter low power mode.
00168   *   This parameter can be one of the following values:
00169   *     @arg NVIC_LP_SEVONPEND
00170   *     @arg NVIC_LP_SLEEPDEEP
00171   *     @arg NVIC_LP_SLEEPONEXIT
00172   * @param  NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE.
00173   * @retval None
00174   */
00175 void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState)
00176 {
00177   /* Check the parameters */
00178   assert_param(IS_NVIC_LP(LowPowerMode));
00179   assert_param(IS_FUNCTIONAL_STATE(NewState));
00180
00181   if (NewState != DISABLE)
00182   {
00183     SCB->SCR |= LowPowerMode;
00184   }
00185   else
00186   {
00187     SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);
00188   }
00189 }
00190
00191 /**
00192   * @brief  Configures the SysTick clock source.
00193   * @param  SysTick_CLKSource: specifies the SysTick clock source.
00194   *   This parameter can be one of the following values:
00195   *     @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source.
00196   *     @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source.
00197   * @retval None
00198   */
00199 void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)
00200 {
00201   /* Check the parameters */
00202   assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));
00203   if (SysTick_CLKSource == SysTick_CLKSource_HCLK)
00204   {
00205     SysTick->CTRL |= SysTick_CLKSource_HCLK;
00206   }
00207   else
00208   {
00209     SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;
00210   }
00211 }
00212
00213 /**
00214   * @}
00215   */
00216
00217 /**
00218   * @}
00219   */
00220
00221 /**
00222   * @}
00223   */
00224
00225 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: misc.h Source File

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Libraries
  • STM32F10x_StdPeriph_Driver
  • inc

misc.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    misc.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    11-March-2011
00007   * @brief   This file contains all the functions prototypes for the miscellaneous
00008   *          firmware library functions (add-on to CMSIS functions).
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00013   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00014   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00015   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00016   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00017   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00018   *
00019   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00020   ******************************************************************************
00021   */
00022
00023 /* Define to prevent recursive inclusion -------------------------------------*/
00024 #ifndef __MISC_H
00025 #define __MISC_H
00026
00027 #ifdef __cplusplus
00028  extern "C" {
00029 #endif
00030
00031 /* Includes ------------------------------------------------------------------*/
00032 #include "stm32f10x.h"
00033
00034 /** @addtogroup STM32F10x_StdPeriph_Driver
00035   * @{
00036   */
00037
00038 /** @addtogroup MISC
00039   * @{
00040   */
00041
00042 /** @defgroup MISC_Exported_Types
00043   * @{
00044   */
00045
00046 /**
00047   * @brief  NVIC Init Structure definition
00048   */
00049
00050 typedef struct
00051 {
00052   uint8_t NVIC_IRQChannel;                    /*!< Specifies the IRQ channel to be enabled or disabled.
00053                                                    This parameter can be a value of @ref IRQn_Type
00054                                                    (For the complete STM32 Devices IRQ Channels list, please
00055                                                     refer to stm32f10x.h file) */
00056
00057   uint8_t NVIC_IRQChannelPreemptionPriority;  /*!< Specifies the pre-emption priority for the IRQ channel
00058                                                    specified in NVIC_IRQChannel. This parameter can be a value
00059                                                    between 0 and 15 as described in the table @ref NVIC_Priority_Table */
00060
00061   uint8_t NVIC_IRQChannelSubPriority;         /*!< Specifies the subpriority level for the IRQ channel specified
00062                                                    in NVIC_IRQChannel. This parameter can be a value
00063                                                    between 0 and 15 as described in the table @ref NVIC_Priority_Table */
00064
00065   FunctionalState NVIC_IRQChannelCmd;         /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel
00066                                                    will be enabled or disabled.
00067                                                    This parameter can be set either to ENABLE or DISABLE */
00068 } NVIC_InitTypeDef;
00069
00070 /**
00071   * @}
00072   */
00073
00074 /** @defgroup NVIC_Priority_Table
00075   * @{
00076   */
00077
00078 /**
00079 @code
00080  The table below gives the allowed values of the pre-emption priority and subpriority according
00081  to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function
00082   ============================================================================================================================
00083     NVIC_PriorityGroup   | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority  | Description
00084   ============================================================================================================================
00085    NVIC_PriorityGroup_0  |                0                  |            0-15             |   0 bits for pre-emption priority
00086                          |                                   |                             |   4 bits for subpriority
00087   ----------------------------------------------------------------------------------------------------------------------------
00088    NVIC_PriorityGroup_1  |                0-1                |            0-7              |   1 bits for pre-emption priority
00089                          |                                   |                             |   3 bits for subpriority
00090   ----------------------------------------------------------------------------------------------------------------------------
00091    NVIC_PriorityGroup_2  |                0-3                |            0-3              |   2 bits for pre-emption priority
00092                          |                                   |                             |   2 bits for subpriority
00093   ----------------------------------------------------------------------------------------------------------------------------
00094    NVIC_PriorityGroup_3  |                0-7                |            0-1              |   3 bits for pre-emption priority
00095                          |                                   |                             |   1 bits for subpriority
00096   ----------------------------------------------------------------------------------------------------------------------------
00097    NVIC_PriorityGroup_4  |                0-15               |            0                |   4 bits for pre-emption priority
00098                          |                                   |                             |   0 bits for subpriority
00099   ============================================================================================================================
00100 @endcode
00101 */
00102
00103 /**
00104   * @}
00105   */
00106
00107 /** @defgroup MISC_Exported_Constants
00108   * @{
00109   */
00110
00111 /** @defgroup Vector_Table_Base
00112   * @{
00113   */
00114
00115 #define NVIC_VectTab_RAM             ((uint32_t)0x20000000)
00116 #define NVIC_VectTab_FLASH           ((uint32_t)0x08000000)
00117 #define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \
00118                                   ((VECTTAB) == NVIC_VectTab_FLASH))
00119 /**
00120   * @}
00121   */
00122
00123 /** @defgroup System_Low_Power
00124   * @{
00125   */
00126
00127 #define NVIC_LP_SEVONPEND            ((uint8_t)0x10)
00128 #define NVIC_LP_SLEEPDEEP            ((uint8_t)0x04)
00129 #define NVIC_LP_SLEEPONEXIT          ((uint8_t)0x02)
00130 #define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \
00131                         ((LP) == NVIC_LP_SLEEPDEEP) || \
00132                         ((LP) == NVIC_LP_SLEEPONEXIT))
00133 /**
00134   * @}
00135   */
00136
00137 /** @defgroup Preemption_Priority_Group
00138   * @{
00139   */
00140
00141 #define NVIC_PriorityGroup_0         ((uint32_t)0x700) /*!< 0 bits for pre-emption priority
00142                                                             4 bits for subpriority */
00143 #define NVIC_PriorityGroup_1         ((uint32_t)0x600) /*!< 1 bits for pre-emption priority
00144                                                             3 bits for subpriority */
00145 #define NVIC_PriorityGroup_2         ((uint32_t)0x500) /*!< 2 bits for pre-emption priority
00146                                                             2 bits for subpriority */
00147 #define NVIC_PriorityGroup_3         ((uint32_t)0x400) /*!< 3 bits for pre-emption priority
00148                                                             1 bits for subpriority */
00149 #define NVIC_PriorityGroup_4         ((uint32_t)0x300) /*!< 4 bits for pre-emption priority
00150                                                             0 bits for subpriority */
00151
00152 #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \
00153                                        ((GROUP) == NVIC_PriorityGroup_1) || \
00154                                        ((GROUP) == NVIC_PriorityGroup_2) || \
00155                                        ((GROUP) == NVIC_PriorityGroup_3) || \
00156                                        ((GROUP) == NVIC_PriorityGroup_4))
00157
00158 #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10)
00159
00160 #define IS_NVIC_SUB_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10)
00161
00162 #define IS_NVIC_OFFSET(OFFSET)  ((OFFSET) < 0x000FFFFF)
00163
00164 /**
00165   * @}
00166   */
00167
00168 /** @defgroup SysTick_clock_source
00169   * @{
00170   */
00171
00172 #define SysTick_CLKSource_HCLK_Div8    ((uint32_t)0xFFFFFFFB)
00173 #define SysTick_CLKSource_HCLK         ((uint32_t)0x00000004)
00174 #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \
00175                                        ((SOURCE) == SysTick_CLKSource_HCLK_Div8))
00176 /**
00177   * @}
00178   */
00179
00180 /**
00181   * @}
00182   */
00183
00184 /** @defgroup MISC_Exported_Macros
00185   * @{
00186   */
00187
00188 /**
00189   * @}
00190   */
00191
00192 /** @defgroup MISC_Exported_Functions
00193   * @{
00194   */
00195
00196 void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
00197 void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
00198 void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);
00199 void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);
00200 void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);
00201
00202 #ifdef __cplusplus
00203 }
00204 #endif
00205
00206 #endif /* __MISC_H */
00207
00208 /**
00209   * @}
00210   */
00211
00212 /**
00213   * @}
00214   */
00215
00216 /**
00217   * @}
00218   */
00219
00220 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: Modules

Modules

Here is a list of all modules:
  • CMSIS
    • Stm32f10x
      • Library_configuration_section
      • Configuration_section_for_CMSIS
      • Exported_types
      • Peripheral_registers_structures
      • Peripheral_memory_map
      • Peripheral_declaration
      • Exported_constants
        • Peripheral_Registers_Bits_Definition
      • Exported_macro
    • Stm32f10x_system
      • STM32F10x_System_Private_Includes
      • STM32F10x_System_Private_TypesDefinitions
      • STM32F10x_System_Private_Defines
      • STM32F10x_System_Private_Macros
      • STM32F10x_System_Private_Variables
      • STM32F10x_System_Private_FunctionPrototypes
      • STM32F10x_System_Private_Functions
      • STM32F10x_System_Includes
      • STM32F10x_System_Exported_types
      • STM32F10x_System_Exported_Constants
      • STM32F10x_System_Exported_Macros
      • STM32F10x_System_Exported_Functions
  • STM32F10x_StdPeriph_Driver
    • MISC
      • MISC_Exported_Types
      • NVIC_Priority_Table
      • MISC_Exported_Constants
        • Vector_Table_Base
        • System_Low_Power
        • Preemption_Priority_Group
        • SysTick_clock_source
      • MISC_Exported_Macros
      • MISC_Exported_Functions
      • MISC_Private_TypesDefinitions
      • MISC_Private_Defines
      • MISC_Private_Macros
      • MISC_Private_Variables
      • MISC_Private_FunctionPrototypes
      • MISC_Private_Functions
    • ADC
      • ADC_Exported_Types
      • ADC_Exported_Constants
        • ADC_mode
        • ADC_external_trigger_sources_for_regular_channels_conversion
        • ADC_data_align
        • ADC_channels
        • ADC_sampling_time
        • ADC_external_trigger_sources_for_injected_channels_conversion
        • ADC_injected_channel_selection
        • ADC_analog_watchdog_selection
        • ADC_interrupts_definition
        • ADC_flags_definition
        • ADC_thresholds
        • ADC_injected_offset
        • ADC_injected_length
        • ADC_injected_rank
        • ADC_regular_length
        • ADC_regular_rank
        • ADC_regular_discontinuous_mode_number
      • ADC_Exported_Macros
      • ADC_Exported_Functions
      • ADC_Private_TypesDefinitions
      • ADC_Private_Defines
      • ADC_Private_Macros
      • ADC_Private_Variables
      • ADC_Private_FunctionPrototypes
      • ADC_Private_Functions
    • BKP
      • BKP_Exported_Types
      • BKP_Exported_Constants
        • Tamper_Pin_active_level
        • RTC_output_source_to_output_on_the_Tamper_pin
        • Data_Backup_Register
      • BKP_Exported_Macros
      • BKP_Exported_Functions
      • BKP_Private_TypesDefinitions
      • BKP_Private_Defines
      • BKP_Private_Macros
      • BKP_Private_Variables
      • BKP_Private_FunctionPrototypes
      • BKP_Private_Functions
    • CAN
      • CAN_Exported_Types
      • CAN_Exported_Constants
        • CAN_sleep_constants
        • CAN_Mode
        • CAN_Operating_Mode
        • CAN_Mode_Status
        • CAN_synchronisation_jump_width
        • CAN_time_quantum_in_bit_segment_1
        • CAN_time_quantum_in_bit_segment_2
        • CAN_clock_prescaler
        • CAN_filter_number
        • CAN_filter_mode
        • CAN_filter_scale
        • CAN_filter_FIFO
        • Start_bank_filter_for_slave_CAN
        • CAN_Tx
        • CAN_identifier_type
        • CAN_remote_transmission_request
        • CAN_transmit_constants
        • CAN_receive_FIFO_number_constants
        • CAN_wake_up_constants
        • CAN_Error_Code_constants
        • CAN_flags
        • CAN_interrupts
        • CAN_Legacy
      • CAN_Exported_Macros
      • CAN_Exported_Functions
      • CAN_Private_TypesDefinitions
      • CAN_Private_Defines
      • CAN_Private_Macros
      • CAN_Private_Variables
      • CAN_Private_FunctionPrototypes
      • CAN_Private_Functions
    • CEC
      • CEC_Exported_Types
      • CEC_Exported_Constants
        • CEC_BitTiming_Mode
        • CEC_BitPeriod_Mode
        • CEC_interrupts_definition
        • CEC_Own_Address
        • CEC_Prescaler
        • CEC_flags_definition
      • CEC_Exported_Macros
      • CEC_Exported_Functions
      • CEC_Private_TypesDefinitions
      • CEC_Private_Defines
      • CEC_Private_Macros
      • CEC_Private_Variables
      • CEC_Private_FunctionPrototypes
      • CEC_Private_Functions
    • CRC
      • CRC_Exported_Types
      • CRC_Exported_Constants
      • CRC_Exported_Macros
      • CRC_Exported_Functions
      • CRC_Private_TypesDefinitions
      • CRC_Private_Defines
      • CRC_Private_Macros
      • CRC_Private_Variables
      • CRC_Private_FunctionPrototypes
      • CRC_Private_Functions
    • DAC
      • DAC_Exported_Types
      • DAC_Exported_Constants
        • DAC_trigger_selection
        • DAC_wave_generation
        • DAC_lfsrunmask_triangleamplitude
        • DAC_output_buffer
        • DAC_Channel_selection
        • DAC_data_alignment
        • DAC_data
      • DAC_Exported_Macros
      • DAC_Exported_Functions
      • DAC_Private_TypesDefinitions
      • DAC_Private_Defines
      • DAC_Private_Macros
      • DAC_Private_Variables
      • DAC_Private_FunctionPrototypes
      • DAC_Private_Functions
    • DBGMCU
      • DBGMCU_Exported_Types
      • DBGMCU_Exported_Constants
      • DBGMCU_Exported_Macros
      • DBGMCU_Exported_Functions
      • DBGMCU_Private_TypesDefinitions
      • DBGMCU_Private_Defines
      • DBGMCU_Private_Macros
      • DBGMCU_Private_Variables
      • DBGMCU_Private_FunctionPrototypes
      • DBGMCU_Private_Functions
    • DMA
      • DMA_Exported_Types
      • DMA_Exported_Constants
        • DMA_data_transfer_direction
        • DMA_peripheral_incremented_mode
        • DMA_memory_incremented_mode
        • DMA_peripheral_data_size
        • DMA_memory_data_size
        • DMA_circular_normal_mode
        • DMA_priority_level
        • DMA_memory_to_memory
        • DMA_interrupts_definition
        • DMA_flags_definition
        • DMA_Buffer_Size
      • DMA_Exported_Macros
      • DMA_Exported_Functions
      • DMA_Private_TypesDefinitions
      • DMA_Private_Defines
      • DMA_Private_Macros
      • DMA_Private_Variables
      • DMA_Private_FunctionPrototypes
      • DMA_Private_Functions
    • EXTI
      • EXTI_Exported_Types
      • EXTI_Exported_Constants
        • EXTI_Lines
      • EXTI_Exported_Macros
      • EXTI_Exported_Functions
      • EXTI_Private_TypesDefinitions
      • EXTI_Private_Defines
      • EXTI_Private_Macros
      • EXTI_Private_Variables
      • EXTI_Private_FunctionPrototypes
      • EXTI_Private_Functions
    • FLASH
      • FLASH_Exported_Types
      • FLASH_Exported_Constants
        • Flash_Latency
        • Half_Cycle_Enable_Disable
        • Prefetch_Buffer_Enable_Disable
        • Option_Bytes_Write_Protection
        • Option_Bytes_IWatchdog
        • Option_Bytes_nRST_STOP
        • Option_Bytes_nRST_STDBY
        • FLASH_Interrupts
        • FLASH_Flags
      • FLASH_Exported_Macros
      • FLASH_Exported_Functions
      • FLASH_Private_TypesDefinitions
      • FLASH_Private_Defines
      • FLASH_Private_Macros
      • FLASH_Private_Variables
      • FLASH_Private_FunctionPrototypes
      • FLASH_Private_Functions
    • FSMC
      • FSMC_Exported_Types
      • FSMC_Exported_Constants
        • FSMC_NORSRAM_Bank
        • FSMC_NAND_Bank
        • FSMC_PCCARD_Bank
        • NOR_SRAM_Controller
          • FSMC_Data_Address_Bus_Multiplexing
          • FSMC_Memory_Type
          • FSMC_Data_Width
          • FSMC_Burst_Access_Mode
          • FSMC_AsynchronousWait
          • FSMC_Wait_Signal_Polarity
          • FSMC_Wrap_Mode
          • FSMC_Wait_Timing
          • FSMC_Write_Operation
          • FSMC_Wait_Signal
          • FSMC_Extended_Mode
          • FSMC_Write_Burst
          • FSMC_Address_Setup_Time
          • FSMC_Address_Hold_Time
          • FSMC_Data_Setup_Time
          • FSMC_Bus_Turn_around_Duration
          • FSMC_CLK_Division
          • FSMC_Data_Latency
          • FSMC_Access_Mode
        • NAND_PCCARD_Controller
          • FSMC_Wait_feature
          • FSMC_ECC
          • FSMC_ECC_Page_Size
          • FSMC_TCLR_Setup_Time
          • FSMC_TAR_Setup_Time
          • FSMC_Setup_Time
          • FSMC_Wait_Setup_Time
          • FSMC_Hold_Setup_Time
          • FSMC_HiZ_Setup_Time
          • FSMC_Interrupt_sources
          • FSMC_Flags
      • FSMC_Exported_Macros
      • FSMC_Exported_Functions
      • FSMC_Private_TypesDefinitions
      • FSMC_Private_Defines
      • FSMC_Private_Macros
      • FSMC_Private_Variables
      • FSMC_Private_FunctionPrototypes
      • FSMC_Private_Functions
    • GPIO
      • GPIO_Exported_Types
      • GPIO_Exported_Constants
        • GPIO_pins_define
        • GPIO_Remap_define
        • GPIO_Port_Sources
        • GPIO_Pin_sources
        • Ethernet_Media_Interface
      • GPIO_Exported_Macros
      • GPIO_Exported_Functions
      • GPIO_Private_TypesDefinitions
      • GPIO_Private_Defines
      • GPIO_Private_Macros
      • GPIO_Private_Variables
      • GPIO_Private_FunctionPrototypes
      • GPIO_Private_Functions
    • I2C
      • I2C_Exported_Types
      • I2C_Exported_Constants
        • I2C_mode
        • I2C_duty_cycle_in_fast_mode
        • I2C_acknowledgement
        • I2C_transfer_direction
        • I2C_acknowledged_address
        • I2C_registers
        • I2C_SMBus_alert_pin_level
        • I2C_PEC_position
        • I2C_NCAK_position
        • I2C_interrupts_definition
        • I2C_flags_definition
        • I2C_Events
        • I2C_own_address1
        • I2C_clock_speed
      • I2C_Exported_Macros
      • I2C_Exported_Functions
      • I2C_Private_TypesDefinitions
      • I2C_Private_Defines
      • I2C_Private_Macros
      • I2C_Private_Variables
      • I2C_Private_FunctionPrototypes
      • I2C_Private_Functions
    • IWDG
      • IWDG_Exported_Types
      • IWDG_Exported_Constants
        • IWDG_WriteAccess
        • IWDG_prescaler
        • IWDG_Flag
      • IWDG_Exported_Macros
      • IWDG_Exported_Functions
      • IWDG_Private_TypesDefinitions
      • IWDG_Private_Defines
      • IWDG_Private_Macros
      • IWDG_Private_Variables
      • IWDG_Private_FunctionPrototypes
      • IWDG_Private_Functions
    • PWR
      • PWR_Exported_Types
      • PWR_Exported_Constants
        • PVD_detection_level
        • Regulator_state_is_STOP_mode
        • STOP_mode_entry
        • PWR_Flag
      • PWR_Exported_Macros
      • PWR_Exported_Functions
      • PWR_Private_TypesDefinitions
      • PWR_Private_Defines
      • PWR_Private_Macros
      • PWR_Private_Variables
      • PWR_Private_FunctionPrototypes
      • PWR_Private_Functions
    • RCC
      • RCC_Exported_Types
      • RCC_Exported_Constants
        • HSE_configuration
        • PLL_entry_clock_source
        • PLL_multiplication_factor
        • PREDIV1_division_factor
        • PREDIV1_clock_source
        • System_clock_source
        • AHB_clock_source
        • APB1_APB2_clock_source
        • RCC_Interrupt_source
        • USB_Device_clock_source
        • ADC_clock_source
        • LSE_configuration
        • RTC_clock_source
        • AHB_peripheral
        • APB2_peripheral
        • APB1_peripheral
        • Clock_source_to_output_on_MCO_pin
        • RCC_Flag
      • RCC_Exported_Macros
      • RCC_Exported_Functions
      • RCC_Private_TypesDefinitions
      • RCC_Private_Defines
      • RCC_Private_Macros
      • RCC_Private_Variables
      • RCC_Private_FunctionPrototypes
      • RCC_Private_Functions
    • RTC
      • RTC_Exported_Types
      • RTC_Exported_Constants
        • RTC_interrupts_define
        • RTC_interrupts_flags
      • RTC_Exported_Macros
      • RTC_Exported_Functions
      • RTC_Private_TypesDefinitions
      • RTC_Private_Defines
      • RTC_Private_Macros
      • RTC_Private_Variables
      • RTC_Private_FunctionPrototypes
      • RTC_Private_Functions
    • SDIO
      • SDIO_Exported_Types
      • SDIO_Exported_Constants
        • SDIO_Clock_Edge
        • SDIO_Clock_Bypass
        • SDIO_Clock_Power_Save
        • SDIO_Bus_Wide
        • SDIO_Hardware_Flow_Control
        • SDIO_Power_State
        • SDIO_Interrupt_sources
        • SDIO_Command_Index
        • SDIO_Response_Type
        • SDIO_Wait_Interrupt_State
        • SDIO_CPSM_State
        • SDIO_Response_Registers
        • SDIO_Data_Length
        • SDIO_Data_Block_Size
        • SDIO_Transfer_Direction
        • SDIO_Transfer_Type
        • SDIO_DPSM_State
        • SDIO_Flags
        • SDIO_Read_Wait_Mode
      • SDIO_Exported_Macros
      • SDIO_Exported_Functions
      • SDIO_Private_TypesDefinitions
      • SDIO_Private_Defines
      • SDIO_Private_Macros
      • SDIO_Private_Variables
      • SDIO_Private_FunctionPrototypes
      • SDIO_Private_Functions
    • SPI
      • SPI_Exported_Types
      • SPI_Exported_Constants
        • SPI_data_direction
        • SPI_mode
        • SPI_data_size
        • SPI_Clock_Polarity
        • SPI_Clock_Phase
        • SPI_Slave_Select_management
        • SPI_BaudRate_Prescaler
        • SPI_MSB_LSB_transmission
        • I2S_Mode
        • I2S_Standard
        • I2S_Data_Format
        • I2S_MCLK_Output
        • I2S_Audio_Frequency
        • I2S_Clock_Polarity
        • SPI_I2S_DMA_transfer_requests
        • SPI_NSS_internal_software_management
        • SPI_CRC_Transmit_Receive
        • SPI_direction_transmit_receive
        • SPI_I2S_interrupts_definition
        • SPI_I2S_flags_definition
        • SPI_CRC_polynomial
      • SPI_Exported_Macros
      • SPI_Exported_Functions
      • SPI_Private_TypesDefinitions
      • SPI_Private_Defines
      • SPI_Private_Macros
      • SPI_Private_Variables
      • SPI_Private_FunctionPrototypes
      • SPI_Private_Functions
    • TIM
      • TIM_Exported_Types
        • TIM_Exported_constants
        • TIM_Output_Compare_and_PWM_modes
        • TIM_One_Pulse_Mode
        • TIM_Channel
        • TIM_Clock_Division_CKD
        • TIM_Counter_Mode
        • TIM_Output_Compare_Polarity
        • TIM_Output_Compare_N_Polarity
        • TIM_Output_Compare_state
        • TIM_Output_Compare_N_state
        • TIM_Capture_Compare_state
        • TIM_Capture_Compare_N_state
        • Break_Input_enable_disable
        • Break_Polarity
        • TIM_AOE_Bit_Set_Reset
        • Lock_level
        • OSSI_Off_State_Selection_for_Idle_mode_state
        • OSSR_Off_State_Selection_for_Run_mode_state
        • TIM_Output_Compare_Idle_State
        • TIM_Output_Compare_N_Idle_State
        • TIM_Input_Capture_Polarity
        • TIM_Input_Capture_Selection
        • TIM_Input_Capture_Prescaler
        • TIM_interrupt_sources
        • TIM_DMA_Base_address
        • TIM_DMA_Burst_Length
        • TIM_DMA_sources
        • TIM_External_Trigger_Prescaler
        • TIM_Internal_Trigger_Selection
        • TIM_TIx_External_Clock_Source
        • TIM_External_Trigger_Polarity
        • TIM_Prescaler_Reload_Mode
        • TIM_Forced_Action
        • TIM_Encoder_Mode
        • TIM_Event_Source
        • TIM_Update_Source
        • TIM_Output_Compare_Preload_State
        • TIM_Output_Compare_Fast_State
        • TIM_Output_Compare_Clear_State
        • TIM_Trigger_Output_Source
        • TIM_Slave_Mode
        • TIM_Master_Slave_Mode
        • TIM_Flags
        • TIM_Input_Capture_Filer_Value
        • TIM_External_Trigger_Filter
        • TIM_Legacy
      • TIM_Exported_Macros
      • TIM_Exported_Functions
      • TIM_Private_TypesDefinitions
      • TIM_Private_Defines
      • TIM_Private_Macros
      • TIM_Private_Variables
      • TIM_Private_FunctionPrototypes
      • TIM_Private_Functions
    • USART
      • USART_Exported_Types
      • USART_Exported_Constants
        • USART_Word_Length
        • USART_Stop_Bits
        • USART_Parity
        • USART_Mode
        • USART_Hardware_Flow_Control
        • USART_Clock
        • USART_Clock_Polarity
        • USART_Clock_Phase
        • USART_Last_Bit
        • USART_Interrupt_definition
        • USART_DMA_Requests
        • USART_WakeUp_methods
        • USART_LIN_Break_Detection_Length
        • USART_IrDA_Low_Power
        • USART_Flags
      • USART_Exported_Macros
      • USART_Exported_Functions
      • USART_Private_TypesDefinitions
      • USART_Private_Defines
      • USART_Private_Macros
      • USART_Private_Variables
      • USART_Private_FunctionPrototypes
      • USART_Private_Functions
    • WWDG
      • WWDG_Exported_Types
      • WWDG_Exported_Constants
        • WWDG_Prescaler
      • WWDG_Exported_Macros
      • WWDG_Exported_Functions
      • WWDG_Private_TypesDefinitions
      • WWDG_Private_Defines
      • WWDG_Private_Macros
      • WWDG_Private_Variables
      • WWDG_Private_FunctionPrototypes
      • WWDG_Private_Functions
  • STM32F10x_StdPeriph_Examples
    • ADC_3ADCs_DMA
    • ADC_ADC1_DMA
    • ADC_AnalogWatchdog
    • ADC_ExtLinesTrigger
    • ADC_RegSimul_DualMode
    • ADC_TIMTrigger_AutoInjection
    • BKP_Backup_Data
    • BKP_Tamper
    • CAN_DualCAN
    • CAN_LoopBack
    • CAN_Networking
    • CEC_DataExchangeInterrupt
    • CortexM3_BitBand
    • CortexM3_Mode_Privilege
    • CortexM3_MPU
    • CRC_Calculation
    • DAC_DualModeDMA_SineWave
    • DAC_OneChannel_NoiseWave
    • DAC_OneChannelDMA_Escalator
    • DAC_TwoChannels_TriangleWave
    • DMA_ADC_TIM1
    • DMA_FLASH_RAM
    • DMA_FSMC
    • DMA_I2C_RAM
    • DMA_SPI_RAM
    • EXTI_Config
    • Dual_Boot
    • FLASH_Program
    • FLASH_Write_Protection
    • FSMC_NAND
    • FSMC_NOR
    • FSMC_NOR_CodeExecute_binary
    • FSMC_NOR_CodeExecute
    • FSMC_OneNAND
    • FSMC_SRAM
    • FSMC_SRAM_DataMemory
    • GPIO_IOToggle
    • GPIO_JTAG_Remap
    • I2C_EEPROM
    • I2C_TSENSOR
    • I2C_IOExpander
    • I2S_Interrupt
    • I2S_SPI_I2S_Switch
    • IWDG_Reset
    • Lib_DEBUG_RunTime_Check
    • NVIC_DMA_WFIMode
    • IRQ_Mask
    • IRQ_Priority
    • NVIC_VectorTable_Relocation
    • PWR_PVD
    • PWR_STANDBY
    • PWR_STOP
    • RCC_ClockConfig
    • RTC_Calendar
    • RTC_LSI_Calib
    • SDIO_uSDCard
    • SPI_CRC
    • SPI_DMA
    • SPI_FullDuplex_SoftNSS
    • SPI_Simplex_Interrupt
    • SPI_FLASH
    • SysTick_TimeBase
    • TIM_6Steps
    • TIM_7PWM_Output
    • TIM_Cascade_Synchro
    • TIM_ComplementarySignals
    • TIM_DMA
    • TIM_DMABurst
    • TIM_ExtTrigger_Synchro
    • TIM_Input_Capture
    • TIM_OCActive
    • TIM_OCInactive
    • TIM_OCToggle
    • TIM_OnePulse
    • TIM_Parallel_Synchro
    • TIM_PWM_Input
    • TIM_PWM_Output
    • TIM10_PWMOutput
    • TIM15_ComplementarySignals
    • TIM_TIM1_Synchro
    • TIM9_OCToggle
    • TIM_TimeBase
    • USART_DMA_Interrupt
    • USART_DMA_Polling
    • USART_HalfDuplex
    • USART_HyperTerminal_HwFlowControl
    • USART_HyperTerminal_Interrupt
    • USART_Interrupt
    • USART_IrDA_Receive
    • USART_IrDA_Transmit
    • USART_MultiProcessor
    • USART_Polling
    • USART_Printf
    • USART_Smartcard
    • USART_Synchronous
    • WWDG_Reset
  • STM32F10x_StdPeriph_Template
  • Utilities
    • STM32_EVAL
      • STM32_EVAL_Abstraction_Layer
        • STM32_EVAL_Private_TypesDefinitions
        • STM32_EVAL_Private_Defines
        • STM32_EVAL_Private_Macros
        • STM32_EVAL_Private_Variables
        • STM32_EVAL_Private_FunctionPrototypes
        • STM32_EVAL_Private_Functions
        • STM32_EVAL_HARDWARE_RESOURCES
        • STM32_EVAL_Exported_Types
        • STM32_EVAL_Exported_Constants
        • STM32_EVAL_Exported_Macros
        • STM32_EVAL_Exported_Functions
      • Common
        • FONTS
          • FONTS_Private_Types
          • FONTS_Private_Defines
          • FONTS_Private_Macros
          • FONTS_Private_Variables
          • FONTS_Private_Function_Prototypes
          • FONTS_Private_Functions
          • FONTS_Exported_Types
          • FONTS_Exported_Constants
          • FONTS_Exported_Macros
          • FONTS_Exported_Functions
        • STM32_EVAL_I2C_EE
          • STM32_EVAL_I2C_EE_Private_Types
          • STM32_EVAL_I2C_EE_Private_Defines
          • STM32_EVAL_I2C_EE_Private_Macros
          • STM32_EVAL_I2C_EE_Private_Variables
          • STM32_EVAL_I2C_EE_Private_Function_Prototypes
          • STM32_EVAL_I2C_EE_Private_Functions
          • STM32_EVAL_I2C_EE_Exported_Types
          • STM32_EVAL_I2C_EE_Exported_Constants
          • STM32_EVAL_I2C_EE_Exported_Macros
          • STM32_EVAL_I2C_EE_Exported_Functions
        • STM32_EVAL_I2C_TSENSOR
          • STM32_EVAL_I2C_TSENSOR_Private_Types
          • STM32_EVAL_I2C_TSENSOR_Private_Defines
          • STM32_EVAL_I2C_TSENSOR_Private_Macros
          • STM32_EVAL_I2C_TSENSOR_Private_Variables
          • STM32_EVAL_I2C_TSENSOR_Private_Function_Prototypes
          • STM32_EVAL_I2C_TSENSOR_Private_Functions
          • STM32_EVAL_I2C_TSENSOR_Exported_Types
          • STM32_EVAL_I2C_TSENSOR_Exported_Constants
          • STM32_EVAL_I2C_TSENSOR_Exported_Macros
          • STM32_EVAL_I2C_TSENSOR_Exported_Functions
        • STM32_EVAL_SDIO_SD
          • STM32_EVAL_SDIO_SD_Private_Types
          • STM32_EVAL_SDIO_SD_Private_Defines
          • STM32_EVAL_SDIO_SD_Private_Macros
          • STM32_EVAL_SDIO_SD_Private_Variables
          • STM32_EVAL_SDIO_SD_Private_Function_Prototypes
          • STM32_EVAL_SDIO_SD_Private_Functions
          • STM32_EVAL_SDIO_SD_Exported_Types
          • STM32_EVAL_SDIO_SD_Exported_Constants
          • STM32_EVAL_SDIO_SD_Exported_Macros
          • STM32_EVAL_SDIO_SD_Exported_Functions
        • STM32_EVAL_SPI_FLASH
          • STM32_EVAL_SPI_FLASH_Private_Types
          • STM32_EVAL_SPI_FLASH_Private_Defines
          • STM32_EVAL_SPI_FLASH_Private_Macros
          • STM32_EVAL_SPI_FLASH_Private_Variables
          • STM32_EVAL_SPI_FLASH_Private_Function_Prototypes
          • STM32_EVAL_SPI_FLASH_Private_Functions
          • STM32_EVAL_SPI_FLASH_Exported_Types
          • STM32_EVAL_SPI_FLASH_Exported_Constants
          • STM32_EVAL_SPI_FLASH_Exported_Macros
          • STM32_EVAL_SPI_FLASH_Exported_Functions
        • STM32_EVAL_SPI_SD
          • STM32_EVAL_SPI_SD_Private_Types
          • STM32_EVAL_SPI_SD_Private_Defines
          • STM32_EVAL_SPI_SD_Private_Macros
          • STM32_EVAL_SPI_SD_Private_Variables
          • STM32_EVAL_SPI_SD_Private_Function_Prototypes
          • STM32_EVAL_SPI_SD_Private_Functions
          • STM32_EVAL_SPI_SD_Exported_Types
          • STM32_EVAL_SPI_SD_Exported_Constants
          • STM32_EVAL_SPI_SD_Exported_Macros
          • STM32_EVAL_SPI_SD_Exported_Functions
      • STM32100B_EVAL
        • STM32100B_EVAL_LOW_LEVEL
          • STM32100B_EVAL_LOW_LEVEL_Private_TypesDefinitions
          • STM32100B_EVAL_LOW_LEVEL_Private_Defines
          • STM32100B_EVAL_LOW_LEVEL_Private_Macros
          • STM32100B_EVAL_LOW_LEVEL_Private_Variables
          • STM32100B_EVAL_LOW_LEVEL_Private_FunctionPrototypes
          • STM32100B_EVAL_LOW_LEVEL_Private_Functions
          • STM32100B_EVAL_LOW_LEVEL_Exported_Types
          • STM32100B_EVAL_LOW_LEVEL_Exported_Constants
            • STM32100B_EVAL_LOW_LEVEL_LED
            • STM32100B_EVAL_LOW_LEVEL_BUTTON
            • STM32100B_EVAL_LOW_LEVEL_COM
            • STM32100B_EVAL_LOW_LEVEL_SD_SPI
            • STM32100B_EVAL_LOW_LEVEL_M25P_FLASH_SPI
            • STM32100B_EVAL_LOW_LEVEL_TSENSOR_I2C
          • STM32100B_EVAL_LOW_LEVEL_Exported_Macros
          • STM32100B_EVAL_LOW_LEVEL_Exported_Functions
        • STM32100B_EVAL_CEC
          • STM32100B_EVAL_CEC_Private_Types
          • STM32100B_EVAL_CEC_Private_Defines
          • STM32100B_EVAL_CEC_Private_Macros
          • STM32100B_EVAL_CEC_Private_Variables
          • STM32100B_EVAL_CEC_Private_Function_Prototypes
          • STM32100B_EVAL_CEC_Private_Functions
          • STM32100B_EVAL_CEC_Exported_Types
          • STM32100B_EVAL_CEC_Exported_Constants
          • STM32100B_EVAL_CEC_Exported_Macros
          • STM32100B_EVAL_CEC_Exported_Functions
        • STM32100B_EVAL_LCD
          • STM32100B_EVAL_LCD_Private_Types
          • STM32100B_EVAL_LCD_Private_Defines
          • STM32100B_EVAL_LCD_Private_Macros
          • STM32100B_EVAL_LCD_Private_Variables
          • STM32100B_EVAL_LCD_Private_Function_Prototypes
          • STM32100B_EVAL_LCD_Private_Functions
          • STM32100B_EVAL_LCD_Exported_Types
          • STM32100B_EVAL_LCD_Exported_Constants
          • STM32100B_EVAL_LCD_Exported_Macros
          • STM32100B_EVAL_LCD_Exported_Functions
      • STM32100E_EVAL
        • STM32100E_EVAL_LOW_LEVEL
          • STM32100E_EVAL_LOW_LEVEL_Private_TypesDefinitions
          • STM32100E_EVAL_LOW_LEVEL_Private_Defines
          • STM32100E_EVAL_LOW_LEVEL_Private_Macros
          • STM32100E_EVAL_LOW_LEVEL_Private_Variables
          • STM32100E_EVAL_LOW_LEVEL_Private_FunctionPrototypes
          • STM32100E_EVAL_LOW_LEVEL_Private_Functions
          • STM32100E_EVAL_LOW_LEVEL_Exported_Types
          • STM32100E_EVAL_LOW_LEVEL_Exported_Constants
            • STM32100E_EVAL_LOW_LEVEL_LED
            • STM32100E_EVAL_LOW_LEVEL_BUTTON
            • STM32100E_EVAL_LOW_LEVEL_COM
            • STM32100E_EVAL_LOW_LEVEL_SD_FLASH
            • STM3210C_EVAL_LOW_LEVEL_I2C_EE
            • STM32100E_EVAL_LOW_LEVEL_M25P_FLASH_SPI
            • STM32100E_EVAL_LOW_LEVEL_TSENSOR_I2C
          • STM32100E_EVAL_LOW_LEVEL_Exported_Macros
          • STM32100E_EVAL_LOW_LEVEL_Exported_Functions
        • STM32100E_EVAL_CEC
          • STM32100E_EVAL_CEC_Private_Types
          • STM32100E_EVAL_CEC_Private_Defines
          • STM32100E_EVAL_CEC_Private_Macros
          • STM32100E_EVAL_CEC_Private_Variables
          • STM32100E_EVAL_CEC_Private_Function_Prototypes
          • STM32100E_EVAL_CEC_Private_Functions
          • STM32100E_EVAL_CEC_Exported_Types
          • STM32100E_EVAL_CEC_Exported_Constants
          • STM32100E_EVAL_CEC_Exported_Macros
          • STM32100E_EVAL_CEC_Exported_Functions
        • STM32100E_EVAL_IOE
          • STM32100E_EVAL_IOE_Private_TypesDefinitions
          • STM32100E_EVAL_IOE_Private_Defines
          • STM32100E_EVAL_IOE_Private_Macros
          • STM32100E_EVAL_IOE_Private_Variables
          • STM32100E_EVAL_IOE_Private_FunctionPrototypes
          • STM32100E_EVAL_IOE_Private_Functions
          • STM32100E_EVAL_IOE_Exported_Types
          • STM32100E_EVAL_IOE_Exported_Constants
          • STM32100E_EVAL_IOE_Exported_Macros
          • STM32100E_EVAL_IOE_Exported_Functions
        • STM32100E_EVAL_LCD
          • STM32100E_EVAL_LCD_Private_TypesDefinitions
          • STM32100E_EVAL_LCD_Private_Defines
          • STM32100E_EVAL_LCD_Private_Macros
          • STM32100E_EVAL_LCD_Private_Variables
          • STM32100E_EVAL_LCD_Private_FunctionPrototypes
          • STM32100E_EVAL_LCD_Private_Functions
          • STM32100E_EVAL_LCD_Exported_Types
          • STM32100E_EVAL_LCD_Exported_Constants
          • STM32100E_EVAL_LCD_Exported_Macros
          • STM32100E_EVAL_LCD_Exported_Functions
        • STM32100E_EVAL_FSMC_ONENAND
          • STM32100E_EVAL_FSMC_ONENAND_Private_Types
          • STM32100E_EVAL_FSMC_ONENAND_Private_Defines
          • STM32100E_EVAL_FSMC_ONENAND_Private_Macros
          • STM32100E_EVAL_FSMC_ONENAND_Private_Variables
          • STM32100E_EVAL_FSMC_ONENAND_Private_Function_Prototypes
          • STM32100E_EVAL_FSMC_ONENAND_Private_Functions
          • STM32100E_EVAL_FSMC_ONENAND_Exported_Types
          • STM32100E_EVAL_FSMC_ONENAND_Exported_Constants
          • STM32100E_EVAL_FSMC_ONENAND_Exported_Macros
          • STM32100E_EVAL_FSMC_ONENAND_Exported_Functions
        • STM32100E_EVAL_FSMC_SRAM
          • STM32100E_EVAL_FSMC_SRAM_Private_Types
          • STM32100E_EVAL_FSMC_SRAM_Private_Defines
          • STM32100E_EVAL_FSMC_SRAM_Private_Macros
          • STM32100E_EVAL_FSMC_SRAM_Private_Variables
          • STM32100E_EVAL_FSMC_SRAM_Private_Function_Prototypes
          • STM32100E_EVAL_FSMC_SRAM_Private_Functions
          • STM32100E_EVAL_FSMC_SRAM_Exported_Types
          • STM32100E_EVAL_FSMC_SRAM_Exported_Constants
          • STM32100E_EVAL_FSMC_SRAM_Exported_Macros
          • STM32100E_EVAL_FSMC_SRAM_Exported_Functions
      • STM3210B_EVAL
        • STM3210B_EVAL_LOW_LEVEL
          • STM3210B_EVAL_LOW_LEVEL_Private_TypesDefinitions
          • STM3210B_EVAL_LOW_LEVEL_Private_Defines
          • STM3210B_EVAL_LOW_LEVEL_Private_Macros
          • STM3210B_EVAL_LOW_LEVEL_Private_Variables
          • STM3210B_EVAL_LOW_LEVEL_Private_FunctionPrototypes
          • STM3210B_EVAL_LOW_LEVEL_Private_Functions
          • STM3210B_EVAL_LOW_LEVEL_Exported_Types
          • STM3210B_EVAL_LOW_LEVEL_Exported_Constants
            • STM3210B_EVAL_LOW_LEVEL_LED
            • STM3210B_EVAL_LOW_LEVEL_BUTTON
            • STM3210B_EVAL_LOW_LEVEL_COM
            • STM3210B_EVAL_LOW_LEVEL_SD_SPI
            • STM3210B_EVAL_LOW_LEVEL_M25P_FLASH_SPI
            • STM3210B_EVAL_LOW_LEVEL_TSENSOR_I2C
          • STM3210B_EVAL_LOW_LEVEL_Exported_Macros
          • STM3210B_EVAL_LOW_LEVEL_Exported_Functions
        • STM3210B_EVAL_LCD
          • STM3210B_EVAL_LCD_Private_Types
          • STM3210B_EVAL_LCD_Private_Defines
          • STM3210B_EVAL_LCD_Private_Macros
          • STM3210B_EVAL_LCD_Private_Variables
          • STM3210B_EVAL_LCD_Private_Function_Prototypes
          • STM3210B_EVAL_LCD_Private_Functions
          • STM3210B_EVAL_LCD_Exported_Types
          • STM3210B_EVAL_LCD_Exported_Constants
          • STM3210B_EVAL_LCD_Exported_Macros
          • STM3210B_EVAL_LCD_Exported_Functions
      • STM3210C_EVAL
        • STM3210C_EVAL_LOW_LEVEL
          • STM3210C_EVAL_LOW_LEVEL_Private_TypesDefinitions
          • STM3210C_EVAL_LOW_LEVEL_Private_Defines
          • STM3210C_EVAL_LOW_LEVEL_Private_Macros
          • STM3210C_EVAL_LOW_LEVEL_Private_Variables
          • STM3210C_EVAL_LOW_LEVEL_Private_FunctionPrototypes
          • STM3210C_EVAL_LOW_LEVEL_Private_Functions
          • STM3210C_EVAL_LOW_LEVEL_Exported_Types
          • STM3210C_EVAL_LOW_LEVEL_Exported_Constants
            • STM3210C_EVAL_LOW_LEVEL_LED
            • STM3210C_EVAL_LOW_LEVEL_BUTTON
            • STM3210C_EVAL_LOW_LEVEL_COM
            • STM3210B_EVAL_SD_SPI
            • STM3210C_EVAL_LOW_LEVEL_I2C_EE
          • STM3210C_EVAL_LOW_LEVEL_Exported_Macros
          • STM3210C_EVAL_LOW_LEVEL_Exported_Functions
        • STM3210C_EVAL_IOE
          • STM3210C_EVAL_IOE_Private_TypesDefinitions
          • STM3210C_EVAL_IOE_Private_Defines
          • STM3210C_EVAL_IOE_Private_Macros
          • STM3210C_EVAL_IOE_Private_Variables
          • STM3210C_EVAL_IOE_Private_FunctionPrototypes
          • STM3210C_EVAL_IOE_Private_Functions
          • STM3210C_EVAL_IOE_Exported_Types
          • STM3210C_EVAL_IOE_Exported_Constants
          • STM3210C_EVAL_IOE_Exported_Macros
          • STM3210C_EVAL_IOE_Exported_Functions
        • STM3210C_EVAL_LCD
          • STM3210C_EVAL_LCD_Private_TypesDefinitions
          • STM3210C_EVAL_LCD_Private_Defines
          • STM3210C_EVAL_LCD_Private_Macros
          • STM3210C_EVAL_LCD_Private_Variables
          • STM3210C_EVAL_LCD_Private_FunctionPrototypes
          • STM3210C_EVAL_LCD_Private_Functions
          • STM3210C_EVAL_LCD_Exported_Types
          • STM3210C_EVAL_LCD_Exported_Constants
          • STM3210C_EVAL_LCD_Exported_Macros
          • STM3210C_EVAL_LCD_Exported_Functions
      • STM3210E_EVAL
        • STM3210E_EVAL_LOW_LEVEL
          • STM3210E_EVAL_LOW_LEVEL_Private_TypesDefinitions
          • STM3210E_EVAL_LOW_LEVEL_Private_Defines
          • STM3210E_EVAL_LOW_LEVEL_Private_Macros
          • STM3210E_EVAL_LOW_LEVEL_Private_Variables
          • STM3210E_EVAL_LOW_LEVEL_Private_FunctionPrototypes
          • STM3210E_EVAL_LOW_LEVEL_Private_Functions
          • STM3210E_EVAL_LOW_LEVEL_Exported_Types
          • STM3210E_EVAL_LOW_LEVEL_Exported_Constants
            • STM3210E_EVAL_LOW_LEVEL_LED
            • STM3210E_EVAL_LOW_LEVEL_BUTTON
            • STM3210E_EVAL_LOW_LEVEL_COM
            • STM3210E_EVAL_LOW_LEVEL_SD_FLASH
            • STM3210E_EVAL_LOW_LEVEL_M25P_FLASH_SPI
            • STM3210E_EVAL_LOW_LEVEL_TSENSOR_I2C
          • STM3210E_EVAL_LOW_LEVEL_Exported_Macros
          • STM3210E_EVAL_LOW_LEVEL_Exported_Functions
        • STM3210E_EVAL_LCD
          • STM3210E_EVAL_LCD_Private_TypesDefinitions
          • STM3210E_EVAL_LCD_Private_Defines
          • STM3210E_EVAL_LCD_Private_Macros
          • STM3210E_EVAL_LCD_Private_Variables
          • STM3210E_EVAL_LCD_Private_FunctionPrototypes
          • STM3210E_EVAL_LCD_Private_Functions
          • STM3210E_EVAL_LCD_Exported_Types
          • STM3210E_EVAL_LCD_Exported_Constants
          • STM3210E_EVAL_LCD_Exported_Macros
          • STM3210E_EVAL_LCD_Exported_Functions
        • STM3210E_EVAL_FSMC_NAND
          • STM3210E_EVAL_FSMC_NAND_Private_Types
          • STM3210E_EVAL_FSMC_NAND_Private_Defines
          • STM3210E_EVAL_FSMC_NAND_Private_Macros
          • STM3210E_EVAL_FSMC_NAND_Private_Variables
          • STM3210E_EVAL_FSMC_NAND_Private_Function_Prototypes
          • STM3210E_EVAL_FSMC_NAND_Private_Functions
          • STM3210E_EVAL_FSMC_NAND_Exported_Types
          • STM3210E_EVAL_FSMC_NAND_Exported_Constants
          • STM3210E_EVAL_FSMC_NAND_Exported_Macros
          • STM3210E_EVAL_FSMC_NAND_Exported_Functions
        • STM3210E_EVAL_FSMC_NOR
          • STM3210E_EVAL_FSMC_NOR_Private_Types
          • STM3210E_EVAL_FSMC_NOR_Private_Defines
          • STM3210E_EVAL_FSMC_NOR_Private_Macros
          • STM3210E_EVAL_FSMC_NOR_Private_Variables
          • STM3210E_EVAL_FSMC_NOR_Private_Functions
          • STM3210E_EVAL_FSMC_NOR_Exported_Types
          • STM3210E_EVAL_FSMC_NOR_Exported_Constants
          • STM3210E_EVAL_FSMC_NOR_Exported_Macros
          • STM3210E_EVAL_FSMC_NOR_Exported_Functions
        • STM3210E_EVAL_FSMC_SRAM
          • STM3210E_EVAL_FSMC_SRAM_Private_Types
          • STM3210E_EVAL_FSMC_SRAM_Private_Defines
          • STM3210E_EVAL_FSMC_SRAM_Private_Macros
          • STM3210E_EVAL_FSMC_SRAM_Private_Variables
          • STM3210E_EVAL_FSMC_SRAM_Private_Function_Prototypes
          • STM3210E_EVAL_FSMC_SRAM_Private_Functions
          • STM3210E_EVAL_FSMC_SRAM_Exported_Types
          • STM3210E_EVAL_FSMC_SRAM_Exported_Constants
          • STM3210E_EVAL_FSMC_SRAM_Exported_Macros
          • STM3210E_EVAL_FSMC_SRAM_Exported_Functions
      • STM32L152_EVAL
        • STM32L152_EVAL_LOW_LEVEL
          • STM32L152_EVAL_LOW_LEVEL_Private_TypesDefinitions
          • STM32L152_EVAL_LOW_LEVEL_Private_Defines
          • STM32L152_EVAL_LOW_LEVEL_Private_Macros
          • STM32L152_EVAL_LOW_LEVEL_Private_Variables
          • STM32L152_EVAL_LOW_LEVEL_Private_FunctionPrototypes
          • STM32L152_EVAL_LOW_LEVEL_Private_Functions
          • STM32L152_EVAL_LOW_LEVEL_Exported_Types
          • STM32L152_EVAL_LOW_LEVEL_Exported_Constants
            • STM32L152_EVAL_LOW_LEVEL_LED
            • STM32L152_EVAL_LOW_LEVEL_BUTTON
            • STM32L152_EVAL_LOW_LEVEL_COM
            • STM32L152_EVAL_LOW_LEVEL_SD_FLASH
            • STM32L152_EVAL_LOW_LEVEL_TSENSOR_I2C
            • STM32L152_EVAL_LOW_LEVEL_I2C_EE
          • STM32L152_EVAL_LOW_LEVEL_Exported_Macros
          • STM32L152_EVAL_LOW_LEVEL_Exported_Functions
        • STM32L152_EVAL_GLASS_LCD
          • STM32L152_EVAL_GLASS_LCD_Private_Types
          • STM32L152_EVAL_GLASS_LCD_Private_Defines
          • STM32L152_EVAL_GLASS_LCD_Private_Macros
          • STM32L152_EVAL_GLASS_LCD_Private_Variables
          • STM32L152_EVAL_LCD_Private_Function_Prototypes
          • STM32L152_EVAL_LCD_Private_Functions
          • STM32L152_EVAL_GLASS_LCD_Exported_Types
          • STM32L152_EVAL_GLASS_LCD_Exported_Constants
          • STM32L152_EVAL_GLASS_LCD_Exported_Macros
          • STM32L152_EVAL_GLASS_LCD_Exported_Functions
        • STM32L152_EVAL_LCD
          • STM32L152_EVAL_LCD_Private_Types
          • STM32L152_EVAL_LCD_Private_Defines
          • STM32L152_EVAL_LCD_Private_Macros
          • STM32L152_EVAL_LCD_Private_Variables
          • STM32L152_EVAL_LCD_Private_Function_Prototypes
          • STM32L152_EVAL_LCD_Private_Functions
          • STM32L152_EVAL_LCD_Exported_Types
          • STM32L152_EVAL_LCD_Exported_Constants
          • STM32L152_EVAL_LCD_Exported_Macros
          • STM32L152_EVAL_LCD_Exported_Functions
        • STM32L152_EVAL_I2C_EE
          • STM32L152_EVAL_I2C_EE_Private_Types
          • STM32L152_EVAL_I2C_EE_Private_Defines
          • STM32L152_EVAL_I2C_EE_Private_Macros
          • STM32L152_EVAL_I2C_EE_Private_Variables
          • STM32L152_EVAL_I2C_EE_Private_Function_Prototypes
          • STM32L152_EVAL_I2C_EE_Private_Functions
          • STM32L152_EVAL_I2C_EE_Exported_Types
          • STM32L152_EVAL_I2C_EE_Exported_Constants
          • STM32L152_EVAL_I2C_EE_Exported_Macros
          • STM32L152_EVAL_I2C_EE_Exported_Functions


STM32F10x Standard Peripherals Firmware Library: main.h Source File

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  • VectorTable_Relocation

NVIC/VectorTable_Relocation/main.h

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00001 /**
00002   ******************************************************************************
00003   * @file    NVIC/VectorTable_Relocation/main.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Header for main.c module
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __MAIN_H
00024 #define __MAIN_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028 #include "stm32_eval.h"
00029
00030 /* Exported types ------------------------------------------------------------*/
00031 /* Exported constants --------------------------------------------------------*/
00032 /* Exported macro ------------------------------------------------------------*/
00033 /* Exported functions ------------------------------------------------------- */
00034 void TimingDelay_Decrement(void);
00035
00036 #endif /* __MAIN_H */
00037
00038 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: Related Pages

Related Pages

Here is a list of all related documentation pages:
  • STM32F10x Standard Peripheral's Drivers
  • STM32F10x Standard Peripheral's Examples
  • STM32F10x Standard Peripherals Project Template
  • STMicroelectronics STM32 Evaluation Boards Drivers


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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  • ADC
  • ADC1_DMA

Project/STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    ADC/ADC1_DMA/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114  #define SYSCLK_FREQ_56MHz  56000000
00115 /* #define SYSCLK_FREQ_72MHz  72000000 */
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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Project/STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    ADC/AnalogWatchdog/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114  #define SYSCLK_FREQ_56MHz  56000000
00115 /* #define SYSCLK_FREQ_72MHz  72000000 */
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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Project/STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    ADC/ExtLinesTrigger/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114  #define SYSCLK_FREQ_56MHz  56000000
00115 /* #define SYSCLK_FREQ_72MHz  72000000 */
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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Project/STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    ADC/RegSimul_DualMode/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 #define SYSCLK_FREQ_56MHz  56000000
00115 /* #define SYSCLK_FREQ_72MHz  72000000 */
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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Project/STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    ADC/TIMTrigger_AutoInjection/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114  #define SYSCLK_FREQ_56MHz  56000000
00115 /* #define SYSCLK_FREQ_72MHz  72000000*/
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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Project/STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    ADC/3ADCs_DMA/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114  #define SYSCLK_FREQ_56MHz  56000000
00115 /* #define SYSCLK_FREQ_72MHz  72000000 */
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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Project/STM32F10x_StdPeriph_Examples/BKP/Backup_Data/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    BKP/Backup_Data/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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Project/STM32F10x_StdPeriph_Examples/BKP/Tamper/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    BKP/Tamper/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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Project/STM32F10x_StdPeriph_Examples/CAN/DualCAN/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    CAN/DualCAN/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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Project/STM32F10x_StdPeriph_Examples/CAN/LoopBack/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    CAN/LoopBack/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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Project/STM32F10x_StdPeriph_Examples/CAN/Networking/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    CAN/Networking/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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Project/STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    CEC/DataExchangeInterrupt/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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Project/STM32F10x_StdPeriph_Examples/CortexM3/BitBand/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    CortexM3/BitBand/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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Project/STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    CortexM3/Mode_Privilege/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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Project/STM32F10x_StdPeriph_Examples/CortexM3/MPU/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    CortexM3/MPU/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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Project/STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    CRC/CRC_Calculation/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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Project/STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    DAC/DualModeDMA_SineWave/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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Project/STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    DAC/OneChannel_NoiseWave/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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Project/STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    DAC/OneChannelDMA_Escalator/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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Project/STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    DAC/TwoChannels_TriangleWave/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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  • ADC_TIM1

Project/STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    DMA/ADC_TIM1/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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Project/STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    DMA/FLASH_RAM/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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Project/STM32F10x_StdPeriph_Examples/DMA/FSMC/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    DMA/FSMC/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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Project/STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    DMA/I2C_RAM/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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Project/STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    DMA/SPI_RAM/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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  • EXTI_Config

Project/STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    EXTI/EXTI_Config/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    FLASH/Dual_Boot/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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Project/STM32F10x_StdPeriph_Examples/FLASH/Program/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    FLASH/Program/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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Project/STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    FLASH/Write_Protection/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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Project/STM32F10x_StdPeriph_Examples/FSMC/NAND/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    FSMC/NAND/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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Project/STM32F10x_StdPeriph_Examples/FSMC/NOR/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    FSMC/NOR/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    FSMC/NOR_CodeExecute/binary/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    FSMC/NOR_CodeExecute/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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Project/STM32F10x_StdPeriph_Examples/FSMC/OneNAND/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    FSMC/OneNAND/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    FSMC/SRAM/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    FSMC/SRAM_DataMemory/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122  #define DATA_IN_ExtSRAM
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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Project/STM32F10x_StdPeriph_Examples/GPIO/IOToggle/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    GPIO/IOToggle/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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Project/STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    GPIO/JTAG_Remap/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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Project/STM32F10x_StdPeriph_Examples/I2C/EEPROM/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    I2C/EEPROM/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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Project/STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    I2C/I2C_TSENSOR/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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Project/STM32F10x_StdPeriph_Examples/I2C/IOExpander/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    I2C/IOExpander/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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Project/STM32F10x_StdPeriph_Examples/I2S/Interrupt/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    I2S/Interrupt/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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Project/STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    I2S/SPI_I2S_Switch/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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Project/STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    IWDG/IWDG_Reset/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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Project/STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    Lib_DEBUG/RunTime_Check/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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Project/STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    NVIC/DMA_WFIMode/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    NVIC/IRQ_Mask/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    NVIC/IRQ_Priority/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    NVIC/VectorTable_Relocation/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x3000 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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Project/STM32F10x_StdPeriph_Examples/PWR/PVD/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    PWR/PVD/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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Project/STM32F10x_StdPeriph_Examples/PWR/STANDBY/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    PWR/STANDBY/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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Project/STM32F10x_StdPeriph_Examples/PWR/STOP/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    PWR/STOP/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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Project/STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    RCC/RCC_ClockConfig/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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Project/STM32F10x_StdPeriph_Examples/RTC/Calendar/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    RTC/Calendar/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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Project/STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    RTC/LSI_Calib/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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Project/STM32F10x_StdPeriph_Examples/SDIO/uSDCard/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    SDIO/uSDCard/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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Project/STM32F10x_StdPeriph_Examples/SPI/CRC/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    SPI/CRC/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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Project/STM32F10x_StdPeriph_Examples/SPI/DMA/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    SPI/DMA/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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Project/STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    SPI/FullDuplex_SoftNSS/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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  • Simplex_Interrupt

Project/STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    SPI/Simplex_Interrupt/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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Project/STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    SPI/SPI_FLASH/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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  • TimeBase

Project/STM32F10x_StdPeriph_Examples/SysTick/TimeBase/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    SysTick/TimeBase/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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  • Cascade_Synchro

Project/STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    TIM/Cascade_Synchro/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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  • ComplementarySignals

Project/STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    TIM/ComplementarySignals/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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Project/STM32F10x_StdPeriph_Examples/TIM/DMA/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    TIM/DMA/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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  • DMABurst

Project/STM32F10x_StdPeriph_Examples/TIM/DMABurst/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    TIM/DMABurst/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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Project/STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    TIM/ExtTrigger_Synchro/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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Project/STM32F10x_StdPeriph_Examples/TIM/InputCapture/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    TIM/InputCapture/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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Project/STM32F10x_StdPeriph_Examples/TIM/OCActive/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    TIM/OCActive/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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Project/STM32F10x_StdPeriph_Examples/TIM/OCInactive/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    TIM/OCInactive/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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  • OCToggle

Project/STM32F10x_StdPeriph_Examples/TIM/OCToggle/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    TIM/OCToggle/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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Project/STM32F10x_StdPeriph_Examples/TIM/OnePulse/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    TIM/OnePulse/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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Project/STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    TIM/Parallel_Synchro/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Input/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    TIM/PWM_Input/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Output/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    TIM/PWM_Output/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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Project/STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    TIM/TIM1_Synchro/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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Project/STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    TIM/TIM9_OCToggle/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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Project/STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    TIM/TIM10_PWMOutput/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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Project/STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    TIM/TIM15_ComplementarySignals/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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Project/STM32F10x_StdPeriph_Examples/TIM/TimeBase/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    TIM/TimeBase/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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Project/STM32F10x_StdPeriph_Examples/TIM/6Steps/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    TIM/6Steps/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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Project/STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    TIM/7PWM_Output/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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Project/STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    USART/DMA_Interrupt/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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Project/STM32F10x_StdPeriph_Examples/USART/DMA_Polling/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    USART/DMA_Polling/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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Project/STM32F10x_StdPeriph_Examples/USART/HalfDuplex/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    USART/HalfDuplex/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    USART/HyperTerminal_HwFlowControl/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    USART/HyperTerminal_Interrupt/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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Project/STM32F10x_StdPeriph_Examples/USART/Interrupt/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    USART/Interrupt/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    USART/IrDA/Receive/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    USART/IrDA/Transmit/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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Project/STM32F10x_StdPeriph_Examples/USART/MultiProcessor/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    USART/MultiProcessor/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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Project/STM32F10x_StdPeriph_Examples/USART/Polling/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    USART/Polling/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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Project/STM32F10x_StdPeriph_Examples/USART/Printf/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    USART/Printf/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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Project/STM32F10x_StdPeriph_Examples/USART/Smartcard/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    USART/Smartcard/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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  • Synchronous

Project/STM32F10x_StdPeriph_Examples/USART/Synchronous/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    USART/Synchronous/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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  • WWDG_Reset

Project/STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    WWDG/WWDG_Reset/system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *          and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *          and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *          and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *          and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *          and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *          and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.c Source File

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Project/STM32F10x_StdPeriph_Template/system_stm32f10x.c

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00001 /**
00002   ******************************************************************************
00003   * @file    system_stm32f10x.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   *
00009   * 1.  This file provides two functions and one global variable to be called from
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings).
00013   *                      This function is called at startup just after reset and
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f10x_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick
00019   *                                  timer or configure other parameters.
00020   *
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00030   *    function will do nothing and HSI still used as system clock source. User can
00031   *    add some code to deal with this issue inside the SetSysClock() function.
00032   *
00033   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
00034   *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
00035   *    When HSE is used as system clock source, directly or through PLL, and you
00036   *    are using different crystal you have to adapt the HSE value to your own
00037   *    configuration.
00038   *
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /** @addtogroup CMSIS
00054   * @{
00055   */
00056
00057 /** @addtogroup stm32f10x_system
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32F10x_System_Private_Includes
00062   * @{
00063   */
00064
00065 #include "stm32f10x.h"
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup STM32F10x_System_Private_Defines
00080   * @{
00081   */
00082
00083 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
00084    frequency (after reset the HSI is used as SYSCLK source)
00085
00086    IMPORTANT NOTE:
00087    ==============
00088    1. After each device reset the HSI is used as System clock source.
00089
00090    2. Please make sure that the selected System clock doesn't exceed your device's
00091       maximum frequency.
00092
00093    3. If none of the define below is enabled, the HSI is used as System clock
00094     source.
00095
00096    4. The System clock configuration functions provided within this file assume that:
00097         - For Low, Medium and High density Value line devices an external 8MHz
00098           crystal is used to drive the System clock.
00099         - For Low, Medium and High density devices an external 8MHz crystal is
00100           used to drive the System clock.
00101         - For Connectivity line devices an external 25MHz crystal is used to drive
00102           the System clock.
00103      If you are using different crystal you have to adapt those functions accordingly.
00104     */
00105
00106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00107 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00108  #define SYSCLK_FREQ_24MHz  24000000
00109 #else
00110 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
00111 /* #define SYSCLK_FREQ_24MHz  24000000 */
00112 /* #define SYSCLK_FREQ_36MHz  36000000 */
00113 /* #define SYSCLK_FREQ_48MHz  48000000 */
00114 /* #define SYSCLK_FREQ_56MHz  56000000 */
00115 #define SYSCLK_FREQ_72MHz  72000000
00116 #endif
00117
00118 /*!< Uncomment the following line if you need to use external SRAM mounted
00119      on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
00120      STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
00121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00122 /* #define DATA_IN_ExtSRAM */
00123 #endif
00124
00125 /*!< Uncomment the following line if you need to relocate your vector Table in
00126      Internal SRAM. */
00127 /* #define VECT_TAB_SRAM */
00128 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
00129                                   This value must be a multiple of 0x200. */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @addtogroup STM32F10x_System_Private_Macros
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup STM32F10x_System_Private_Variables
00145   * @{
00146   */
00147
00148 /*******************************************************************************
00149 *  Clock Definitions
00150 *******************************************************************************/
00151 #ifdef SYSCLK_FREQ_HSE
00152   uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
00153 #elif defined SYSCLK_FREQ_24MHz
00154   uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
00155 #elif defined SYSCLK_FREQ_36MHz
00156   uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
00157 #elif defined SYSCLK_FREQ_48MHz
00158   uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
00159 #elif defined SYSCLK_FREQ_56MHz
00160   uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
00161 #elif defined SYSCLK_FREQ_72MHz
00162   uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
00163 #else /*!< HSI Selected as System Clock source */
00164   uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
00165 #endif
00166
00167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
00173   * @{
00174   */
00175
00176 static void SetSysClock(void);
00177
00178 #ifdef SYSCLK_FREQ_HSE
00179   static void SetSysClockToHSE(void);
00180 #elif defined SYSCLK_FREQ_24MHz
00181   static void SetSysClockTo24(void);
00182 #elif defined SYSCLK_FREQ_36MHz
00183   static void SetSysClockTo36(void);
00184 #elif defined SYSCLK_FREQ_48MHz
00185   static void SetSysClockTo48(void);
00186 #elif defined SYSCLK_FREQ_56MHz
00187   static void SetSysClockTo56(void);
00188 #elif defined SYSCLK_FREQ_72MHz
00189   static void SetSysClockTo72(void);
00190 #endif
00191
00192 #ifdef DATA_IN_ExtSRAM
00193   static void SystemInit_ExtMemCtl(void);
00194 #endif /* DATA_IN_ExtSRAM */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @addtogroup STM32F10x_System_Private_Functions
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Setup the microcontroller system
00206   *         Initialize the Embedded Flash Interface, the PLL and update the
00207   *         SystemCoreClock variable.
00208   * @note   This function should be used only after reset.
00209   * @param  None
00210   * @retval None
00211   */
00212 void SystemInit (void)
00213 {
00214   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00215   /* Set HSION bit */
00216   RCC->CR |= (uint32_t)0x00000001;
00217
00218   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00219 #ifndef STM32F10X_CL
00220   RCC->CFGR &= (uint32_t)0xF8FF0000;
00221 #else
00222   RCC->CFGR &= (uint32_t)0xF0FF0000;
00223 #endif /* STM32F10X_CL */
00224
00225   /* Reset HSEON, CSSON and PLLON bits */
00226   RCC->CR &= (uint32_t)0xFEF6FFFF;
00227
00228   /* Reset HSEBYP bit */
00229   RCC->CR &= (uint32_t)0xFFFBFFFF;
00230
00231   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00232   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00233
00234 #ifdef STM32F10X_CL
00235   /* Reset PLL2ON and PLL3ON bits */
00236   RCC->CR &= (uint32_t)0xEBFFFFFF;
00237
00238   /* Disable all interrupts and clear pending bits  */
00239   RCC->CIR = 0x00FF0000;
00240
00241   /* Reset CFGR2 register */
00242   RCC->CFGR2 = 0x00000000;
00243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00244   /* Disable all interrupts and clear pending bits  */
00245   RCC->CIR = 0x009F0000;
00246
00247   /* Reset CFGR2 register */
00248   RCC->CFGR2 = 0x00000000;
00249 #else
00250   /* Disable all interrupts and clear pending bits  */
00251   RCC->CIR = 0x009F0000;
00252 #endif /* STM32F10X_CL */
00253
00254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
00255   #ifdef DATA_IN_ExtSRAM
00256     SystemInit_ExtMemCtl();
00257   #endif /* DATA_IN_ExtSRAM */
00258 #endif
00259
00260   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00261   /* Configure the Flash Latency cycles and enable prefetch buffer */
00262   SetSysClock();
00263
00264 #ifdef VECT_TAB_SRAM
00265   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00266 #else
00267   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00268 #endif
00269 }
00270
00271 /**
00272   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00273   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00274   *         be used by the user application to setup the SysTick timer or configure
00275   *         other parameters.
00276   *
00277   * @note   Each time the core clock (HCLK) changes, this function must be called
00278   *         to update SystemCoreClock variable value. Otherwise, any configuration
00279   *         based on this variable will be incorrect.
00280   *
00281   * @note   - The system frequency computed by this function is not the real
00282   *           frequency in the chip. It is calculated based on the predefined
00283   *           constant and the selected clock source:
00284   *
00285   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00286   *
00287   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00288   *
00289   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00290   *             or HSI_VALUE(*) multiplied by the PLL factors.
00291   *
00292   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00293   *             8 MHz) but the real value may vary depending on the variations
00294   *             in voltage and temperature.
00295   *
00296   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00297   *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
00298   *              that HSE_VALUE is same as the real frequency of the crystal used.
00299   *              Otherwise, this function may have wrong result.
00300   *
00301   *         - The result of this function could be not correct when using fractional
00302   *           value for HSE crystal.
00303   * @param  None
00304   * @retval None
00305   */
00306 void SystemCoreClockUpdate (void)
00307 {
00308   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00309
00310 #ifdef  STM32F10X_CL
00311   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00312 #endif /* STM32F10X_CL */
00313
00314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00315   uint32_t prediv1factor = 0;
00316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
00317
00318   /* Get SYSCLK source -------------------------------------------------------*/
00319   tmp = RCC->CFGR & RCC_CFGR_SWS;
00320
00321   switch (tmp)
00322   {
00323     case 0x00:  /* HSI used as system clock */
00324       SystemCoreClock = HSI_VALUE;
00325       break;
00326     case 0x04:  /* HSE used as system clock */
00327       SystemCoreClock = HSE_VALUE;
00328       break;
00329     case 0x08:  /* PLL used as system clock */
00330
00331       /* Get PLL clock source and multiplication factor ----------------------*/
00332       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00333       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00334
00335 #ifndef STM32F10X_CL
00336       pllmull = ( pllmull >> 18) + 2;
00337
00338       if (pllsource == 0x00)
00339       {
00340         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00341         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00342       }
00343       else
00344       {
00345  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
00346        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00347        /* HSE oscillator clock selected as PREDIV1 clock entry */
00348        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00349  #else
00350         /* HSE selected as PLL clock entry */
00351         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00352         {/* HSE oscillator clock divided by 2 */
00353           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00354         }
00355         else
00356         {
00357           SystemCoreClock = HSE_VALUE * pllmull;
00358         }
00359  #endif
00360       }
00361 #else
00362       pllmull = pllmull >> 18;
00363
00364       if (pllmull != 0x0D)
00365       {
00366          pllmull += 2;
00367       }
00368       else
00369       { /* PLL multiplication factor = PLL input clock * 6.5 */
00370         pllmull = 13 / 2;
00371       }
00372
00373       if (pllsource == 0x00)
00374       {
00375         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00376         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00377       }
00378       else
00379       {/* PREDIV1 selected as PLL clock entry */
00380
00381         /* Get PREDIV1 clock source and division factor */
00382         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00383         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00384
00385         if (prediv1source == 0)
00386         {
00387           /* HSE oscillator clock selected as PREDIV1 clock entry */
00388           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
00389         }
00390         else
00391         {/* PLL2 clock selected as PREDIV1 clock entry */
00392
00393           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00394           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00395           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
00396           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00397         }
00398       }
00399 #endif /* STM32F10X_CL */
00400       break;
00401
00402     default:
00403       SystemCoreClock = HSI_VALUE;
00404       break;
00405   }
00406
00407   /* Compute HCLK clock frequency ----------------*/
00408   /* Get HCLK prescaler */
00409   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00410   /* HCLK clock frequency */
00411   SystemCoreClock >>= tmp;
00412 }
00413
00414 /**
00415   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
00416   * @param  None
00417   * @retval None
00418   */
00419 static void SetSysClock(void)
00420 {
00421 #ifdef SYSCLK_FREQ_HSE
00422   SetSysClockToHSE();
00423 #elif defined SYSCLK_FREQ_24MHz
00424   SetSysClockTo24();
00425 #elif defined SYSCLK_FREQ_36MHz
00426   SetSysClockTo36();
00427 #elif defined SYSCLK_FREQ_48MHz
00428   SetSysClockTo48();
00429 #elif defined SYSCLK_FREQ_56MHz
00430   SetSysClockTo56();
00431 #elif defined SYSCLK_FREQ_72MHz
00432   SetSysClockTo72();
00433 #endif
00434
00435  /* If none of the define above is enabled, the HSI is used as System clock
00436     source (default after reset) */
00437 }
00438
00439 /**
00440   * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
00441   *          before jump to __main
00442   * @param  None
00443   * @retval None
00444   */
00445 #ifdef DATA_IN_ExtSRAM
00446 /**
00447   * @brief  Setup the external memory controller.
00448   *         Called in startup_stm32f10x_xx.s/.c before jump to main.
00449   *           This function configures the external SRAM mounted on STM3210E-EVAL
00450   *         board (STM32 High density devices). This SRAM will be used as program
00451   *         data memory (including heap and stack).
00452   * @param  None
00453   * @retval None
00454   */
00455 void SystemInit_ExtMemCtl(void)
00456 {
00457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
00458   required, then adjust the Register Addresses */
00459
00460   /* Enable FSMC clock */
00461   RCC->AHBENR = 0x00000114;
00462
00463   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00464   RCC->APB2ENR = 0x000001E0;
00465
00466 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00467 /*----------------  SRAM Address lines configuration -------------------------*/
00468 /*----------------  NOE and NWE configuration --------------------------------*/
00469 /*----------------  NE3 configuration ----------------------------------------*/
00470 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00471
00472   GPIOD->CRL = 0x44BB44BB;
00473   GPIOD->CRH = 0xBBBBBBBB;
00474
00475   GPIOE->CRL = 0xB44444BB;
00476   GPIOE->CRH = 0xBBBBBBBB;
00477
00478   GPIOF->CRL = 0x44BBBBBB;
00479   GPIOF->CRH = 0xBBBB4444;
00480
00481   GPIOG->CRL = 0x44BBBBBB;
00482   GPIOG->CRH = 0x44444B44;
00483
00484 /*----------------  FSMC Configuration ---------------------------------------*/
00485 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00486
00487   FSMC_Bank1->BTCR[4] = 0x00001011;
00488   FSMC_Bank1->BTCR[5] = 0x00000200;
00489 }
00490 #endif /* DATA_IN_ExtSRAM */
00491
00492 #ifdef SYSCLK_FREQ_HSE
00493 /**
00494   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00495   *         and PCLK1 prescalers.
00496   * @note   This function should be used only after reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 static void SetSysClockToHSE(void)
00501 {
00502   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00503
00504   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00505   /* Enable HSE */
00506   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00507
00508   /* Wait till HSE is ready and if Time out is reached exit */
00509   do
00510   {
00511     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00512     StartUpCounter++;
00513   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00514
00515   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00516   {
00517     HSEStatus = (uint32_t)0x01;
00518   }
00519   else
00520   {
00521     HSEStatus = (uint32_t)0x00;
00522   }
00523
00524   if (HSEStatus == (uint32_t)0x01)
00525   {
00526
00527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00528     /* Enable Prefetch Buffer */
00529     FLASH->ACR |= FLASH_ACR_PRFTBE;
00530
00531     /* Flash 0 wait state */
00532     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00533
00534 #ifndef STM32F10X_CL
00535     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00536 #else
00537     if (HSE_VALUE <= 24000000)
00538         {
00539       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00540         }
00541         else
00542         {
00543       FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00544         }
00545 #endif /* STM32F10X_CL */
00546 #endif
00547
00548     /* HCLK = SYSCLK */
00549     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00550
00551     /* PCLK2 = HCLK */
00552     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00553
00554     /* PCLK1 = HCLK */
00555     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00556
00557     /* Select HSE as system clock source */
00558     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00559     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
00560
00561     /* Wait till HSE is used as system clock source */
00562     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
00563     {
00564     }
00565   }
00566   else
00567   { /* If HSE fails to start-up, the application will have wrong clock
00568          configuration. User can add here some code to deal with this error */
00569   }
00570 }
00571 #elif defined SYSCLK_FREQ_24MHz
00572 /**
00573   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00574   *         and PCLK1 prescalers.
00575   * @note   This function should be used only after reset.
00576   * @param  None
00577   * @retval None
00578   */
00579 static void SetSysClockTo24(void)
00580 {
00581   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00582
00583   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00584   /* Enable HSE */
00585   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00586
00587   /* Wait till HSE is ready and if Time out is reached exit */
00588   do
00589   {
00590     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00591     StartUpCounter++;
00592   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00593
00594   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00595   {
00596     HSEStatus = (uint32_t)0x01;
00597   }
00598   else
00599   {
00600     HSEStatus = (uint32_t)0x00;
00601   }
00602
00603   if (HSEStatus == (uint32_t)0x01)
00604   {
00605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00606     /* Enable Prefetch Buffer */
00607     FLASH->ACR |= FLASH_ACR_PRFTBE;
00608
00609     /* Flash 0 wait state */
00610     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00611     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
00612 #endif
00613
00614     /* HCLK = SYSCLK */
00615     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00616
00617     /* PCLK2 = HCLK */
00618     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00619
00620     /* PCLK1 = HCLK */
00621     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00622
00623 #ifdef STM32F10X_CL
00624     /* Configure PLLs ------------------------------------------------------*/
00625     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
00626     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00627     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00628                             RCC_CFGR_PLLMULL6);
00629
00630     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00631     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00632     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00633                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00634     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00635                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00636
00637     /* Enable PLL2 */
00638     RCC->CR |= RCC_CR_PLL2ON;
00639     /* Wait till PLL2 is ready */
00640     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00641     {
00642     }
00643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00644     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00645     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00646     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
00647 #else
00648     /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
00649     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00650     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
00651 #endif /* STM32F10X_CL */
00652
00653     /* Enable PLL */
00654     RCC->CR |= RCC_CR_PLLON;
00655
00656     /* Wait till PLL is ready */
00657     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00658     {
00659     }
00660
00661     /* Select PLL as system clock source */
00662     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00663     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00664
00665     /* Wait till PLL is used as system clock source */
00666     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00667     {
00668     }
00669   }
00670   else
00671   { /* If HSE fails to start-up, the application will have wrong clock
00672          configuration. User can add here some code to deal with this error */
00673   }
00674 }
00675 #elif defined SYSCLK_FREQ_36MHz
00676 /**
00677   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00678   *         and PCLK1 prescalers.
00679   * @note   This function should be used only after reset.
00680   * @param  None
00681   * @retval None
00682   */
00683 static void SetSysClockTo36(void)
00684 {
00685   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00686
00687   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00688   /* Enable HSE */
00689   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00690
00691   /* Wait till HSE is ready and if Time out is reached exit */
00692   do
00693   {
00694     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00695     StartUpCounter++;
00696   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00697
00698   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00699   {
00700     HSEStatus = (uint32_t)0x01;
00701   }
00702   else
00703   {
00704     HSEStatus = (uint32_t)0x00;
00705   }
00706
00707   if (HSEStatus == (uint32_t)0x01)
00708   {
00709     /* Enable Prefetch Buffer */
00710     FLASH->ACR |= FLASH_ACR_PRFTBE;
00711
00712     /* Flash 1 wait state */
00713     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00714     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00715
00716     /* HCLK = SYSCLK */
00717     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00718
00719     /* PCLK2 = HCLK */
00720     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00721
00722     /* PCLK1 = HCLK */
00723     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00724
00725 #ifdef STM32F10X_CL
00726     /* Configure PLLs ------------------------------------------------------*/
00727
00728     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
00729     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00730     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00731                             RCC_CFGR_PLLMULL9);
00732
00733         /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00734     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
00735
00736     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00737                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00738     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00739                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
00740
00741     /* Enable PLL2 */
00742     RCC->CR |= RCC_CR_PLL2ON;
00743     /* Wait till PLL2 is ready */
00744     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00745     {
00746     }
00747
00748 #else
00749     /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
00750     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00751     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
00752 #endif /* STM32F10X_CL */
00753
00754     /* Enable PLL */
00755     RCC->CR |= RCC_CR_PLLON;
00756
00757     /* Wait till PLL is ready */
00758     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00759     {
00760     }
00761
00762     /* Select PLL as system clock source */
00763     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00764     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00765
00766     /* Wait till PLL is used as system clock source */
00767     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00768     {
00769     }
00770   }
00771   else
00772   { /* If HSE fails to start-up, the application will have wrong clock
00773          configuration. User can add here some code to deal with this error */
00774   }
00775 }
00776 #elif defined SYSCLK_FREQ_48MHz
00777 /**
00778   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00779   *         and PCLK1 prescalers.
00780   * @note   This function should be used only after reset.
00781   * @param  None
00782   * @retval None
00783   */
00784 static void SetSysClockTo48(void)
00785 {
00786   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00787
00788   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00789   /* Enable HSE */
00790   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00791
00792   /* Wait till HSE is ready and if Time out is reached exit */
00793   do
00794   {
00795     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00796     StartUpCounter++;
00797   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00798
00799   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00800   {
00801     HSEStatus = (uint32_t)0x01;
00802   }
00803   else
00804   {
00805     HSEStatus = (uint32_t)0x00;
00806   }
00807
00808   if (HSEStatus == (uint32_t)0x01)
00809   {
00810     /* Enable Prefetch Buffer */
00811     FLASH->ACR |= FLASH_ACR_PRFTBE;
00812
00813     /* Flash 1 wait state */
00814     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00815     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
00816
00817     /* HCLK = SYSCLK */
00818     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00819
00820     /* PCLK2 = HCLK */
00821     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00822
00823     /* PCLK1 = HCLK */
00824     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00825
00826 #ifdef STM32F10X_CL
00827     /* Configure PLLs ------------------------------------------------------*/
00828     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00829     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00830
00831     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00832                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00833     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00834                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00835
00836     /* Enable PLL2 */
00837     RCC->CR |= RCC_CR_PLL2ON;
00838     /* Wait till PLL2 is ready */
00839     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00840     {
00841     }
00842
00843
00844     /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
00845     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00846     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00847                             RCC_CFGR_PLLMULL6);
00848 #else
00849     /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
00850     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00851     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
00852 #endif /* STM32F10X_CL */
00853
00854     /* Enable PLL */
00855     RCC->CR |= RCC_CR_PLLON;
00856
00857     /* Wait till PLL is ready */
00858     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00859     {
00860     }
00861
00862     /* Select PLL as system clock source */
00863     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00864     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00865
00866     /* Wait till PLL is used as system clock source */
00867     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00868     {
00869     }
00870   }
00871   else
00872   { /* If HSE fails to start-up, the application will have wrong clock
00873          configuration. User can add here some code to deal with this error */
00874   }
00875 }
00876
00877 #elif defined SYSCLK_FREQ_56MHz
00878 /**
00879   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00880   *         and PCLK1 prescalers.
00881   * @note   This function should be used only after reset.
00882   * @param  None
00883   * @retval None
00884   */
00885 static void SetSysClockTo56(void)
00886 {
00887   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00888
00889   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00890   /* Enable HSE */
00891   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00892
00893   /* Wait till HSE is ready and if Time out is reached exit */
00894   do
00895   {
00896     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00897     StartUpCounter++;
00898   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00899
00900   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00901   {
00902     HSEStatus = (uint32_t)0x01;
00903   }
00904   else
00905   {
00906     HSEStatus = (uint32_t)0x00;
00907   }
00908
00909   if (HSEStatus == (uint32_t)0x01)
00910   {
00911     /* Enable Prefetch Buffer */
00912     FLASH->ACR |= FLASH_ACR_PRFTBE;
00913
00914     /* Flash 2 wait state */
00915     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
00916     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00917
00918     /* HCLK = SYSCLK */
00919     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00920
00921     /* PCLK2 = HCLK */
00922     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00923
00924     /* PCLK1 = HCLK */
00925     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00926
00927 #ifdef STM32F10X_CL
00928     /* Configure PLLs ------------------------------------------------------*/
00929     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00930     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
00931
00932     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00933                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
00934     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
00935                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
00936
00937     /* Enable PLL2 */
00938     RCC->CR |= RCC_CR_PLL2ON;
00939     /* Wait till PLL2 is ready */
00940     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
00941     {
00942     }
00943
00944
00945     /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
00946     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
00947     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
00948                             RCC_CFGR_PLLMULL7);
00949 #else
00950     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
00951     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00952     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
00953
00954 #endif /* STM32F10X_CL */
00955
00956     /* Enable PLL */
00957     RCC->CR |= RCC_CR_PLLON;
00958
00959     /* Wait till PLL is ready */
00960     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00961     {
00962     }
00963
00964     /* Select PLL as system clock source */
00965     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00966     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00967
00968     /* Wait till PLL is used as system clock source */
00969     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
00970     {
00971     }
00972   }
00973   else
00974   { /* If HSE fails to start-up, the application will have wrong clock
00975          configuration. User can add here some code to deal with this error */
00976   }
00977 }
00978
00979 #elif defined SYSCLK_FREQ_72MHz
00980 /**
00981   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00982   *         and PCLK1 prescalers.
00983   * @note   This function should be used only after reset.
00984   * @param  None
00985   * @retval None
00986   */
00987 static void SetSysClockTo72(void)
00988 {
00989   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00990
00991   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
00992   /* Enable HSE */
00993   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00994
00995   /* Wait till HSE is ready and if Time out is reached exit */
00996   do
00997   {
00998     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00999     StartUpCounter++;
01000   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
01001
01002   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
01003   {
01004     HSEStatus = (uint32_t)0x01;
01005   }
01006   else
01007   {
01008     HSEStatus = (uint32_t)0x00;
01009   }
01010
01011   if (HSEStatus == (uint32_t)0x01)
01012   {
01013     /* Enable Prefetch Buffer */
01014     FLASH->ACR |= FLASH_ACR_PRFTBE;
01015
01016     /* Flash 2 wait state */
01017     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
01018     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
01019
01020
01021     /* HCLK = SYSCLK */
01022     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
01023
01024     /* PCLK2 = HCLK */
01025     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
01026
01027     /* PCLK1 = HCLK */
01028     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
01029
01030 #ifdef STM32F10X_CL
01031     /* Configure PLLs ------------------------------------------------------*/
01032     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
01033     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
01034
01035     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
01036                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
01037     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
01038                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
01039
01040     /* Enable PLL2 */
01041     RCC->CR |= RCC_CR_PLL2ON;
01042     /* Wait till PLL2 is ready */
01043     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
01044     {
01045     }
01046
01047
01048     /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
01049     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
01050     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
01051                             RCC_CFGR_PLLMULL9);
01052 #else
01053     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
01054     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
01055                                         RCC_CFGR_PLLMULL));
01056     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
01057 #endif /* STM32F10X_CL */
01058
01059     /* Enable PLL */
01060     RCC->CR |= RCC_CR_PLLON;
01061
01062     /* Wait till PLL is ready */
01063     while((RCC->CR & RCC_CR_PLLRDY) == 0)
01064     {
01065     }
01066
01067     /* Select PLL as system clock source */
01068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
01069     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
01070
01071     /* Wait till PLL is used as system clock source */
01072     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
01073     {
01074     }
01075   }
01076   else
01077   { /* If HSE fails to start-up, the application will have wrong clock
01078          configuration. User can add here some code to deal with this error */
01079   }
01080 }
01081 #endif
01082
01083 /**
01084   * @}
01085   */
01086
01087 /**
01088   * @}
01089   */
01090
01091 /**
01092   * @}
01093   */
01094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: project_template.txt File Reference

  • File List
  • Globals

project_template.txt File Reference

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: STM32F10x Standard Peripherals Project Template

STM32F10x Standard Peripherals Project Template

  • EWARM
    • EWARM Project Template
  • HiTOP
    • HiTop Project Template
  • RIDE
    • RIDE Project Template
  • MDK-ARM
    • MDK-ARM Project Template
  • TrueSTUDIO
    • TrueSTUDIO Project Template


STM32F10x Standard Peripherals Firmware Library: main.h Source File

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • RCC
  • RCC_ClockConfig

RCC/RCC_ClockConfig/main.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    RCC/RCC_ClockConfig/main.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Header for main.c module
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __MAIN_H
00024 #define __MAIN_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028 #include "stm32_eval.h"
00029
00030 /* Exported types ------------------------------------------------------------*/
00031 /* Exported constants --------------------------------------------------------*/
00032 /* Uncomment the line corresponding to the desired System clock (SYSCLK)
00033    frequency (after reset the HSI is used as SYSCLK source) */
00034 //#define SYSCLK_HSE
00035 #define SYSCLK_FREQ_24MHz
00036
00037 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00038   //#define SYSCLK_FREQ_36MHz
00039   //#define SYSCLK_FREQ_48MHz
00040   //#define SYSCLK_FREQ_56MHz
00041   #define SYSCLK_FREQ_72MHz
00042 #endif
00043
00044 /* Exported macro ------------------------------------------------------------*/
00045 /* Exported functions ------------------------------------------------------- */
00046
00047 #endif /* __MAIN_H */
00048
00049 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


Release Notes for STM32F10x Standard Peripherals Library

Release Notes for STM32F10x Standard Peripherals Library (StdPeriph_Lib)

Copyright 2011 STMicroelectronics

Contents

  1. STM32F10x Standard Peripherals Library update History
  2. License

STM32F10x Standard Peripherals Library update History

V3.5.0 / 08-April-2011

Main Changes

  • Specific system_stm32f10x.c file provided for each example
  • HTML file containing the examples list, with main features, provided in the root folder (allow search on key word/feature)
  • Template projects updated to save configuration time and easy the examples use
  • Refreshed example list vs. previous version:
    • Add two new Examples: MPU and TIM DMA Burst
    • xWDG examples enhanced, ex. accurate IWDG timeout thanks to LSI freq measure w/ Timer
    • NVIC and SysTick examples enhanced to provide more details how to use them w/ CMSIS layer

Contents

  • ARM CM3 CMSIS V1.30 (release notes)
  • STM32F10x CMSIS V3.5.0 (release notes)
  • STM32F10x_StdPeriph_Driver V3.5.0 (release notes)
  • STM32F10x_StdPeriph_Examples V3.5.0 (release notes)
  • STM32F10x_StdPeriph_Template V3.5.0 (release notes)
  • STM32_EVAL V4.5.0 (release notes)

Development Toolchains and Compilers

  • IAR Embedded Workbench for ARM (EWARM) toolchain V5.50.5
  • Hitex IDE/Debugger (HiTOP) toolchain V5.40.0051
  • RealView Microcontroller Development Kit (MDK-ARM) toolchain V4.13
  • Raisonance IDE RIDE7 (RIDE) toolchain (RIDE7 IDE:7.30.10, RKitARM for RIDE7:1.30.10)
  • Atollic TrueSTUDIO STM32 (TrueSTUDIO) toolchain V1.4.0

3.4.0 - 10/15/2010

  1. General
  • Add support for STM32F10x High-density Value line devices.
  • Add 3 examples: FSMC OneNAND, I2C TSENSOR (Temperature Sensro) and I2C IOExpander.
  • Utilities STM32 EVAL drivers enhancements:
    • I2C EEPROM, Temperature Sensor and IO Expander drivers updated to use the DMA for read/write transfer and add more robustness.
    • SD Card (SDIO) driver updated to add more robustness.
  2. Libraries
  • CMSIS
    • See Release Notes for STM32F10x CMSIS
  • STM32F10x_StdPeriph_Drive r
    • See Release Notes for STM32F10x_StdPeriph_Driver
  3. Project
  • STM32F10x_StdPeriph_Examples
    • See Release Notes for STM32F10x_StdPeriph_Examples
  • STM32F10x_StdPeriph_Template
    • See Release Notes for STM32F10x_StdPeriph_Template
  4. Utilities
  • STM32_EVAL
    • See Release Notes_for_STM32_EVAL

3.3.0 - 04/16/2010

  1. General
  • Add support for STM32F10x XL-density devices.
  • Add template project for TrueSTUDIO toolchain.
  2. Libraries
  • CMSIS
    • See Release Notes for STM32F10x CMSIS
  • STM32F10x_StdPeriph_Drive r
    • See Release Notes for STM32F10x_StdPeriph_Driver
  3. Project
  • STM32F10x_StdPeriph_Examples
    • See Release Notes for STM32F10x_StdPeriph_Examples
  • STM32F10x_StdPeriph_Template
    • See Release Notes for STM32F10x_StdPeriph_Template
  4. Utilities
  • STM32_EVAL
    • See Release Notes_for_STM32_EVAL

3.2.0 - 03/01/2010

  1. General
  • Add support for STM32 Low-density Value line (STM32F100x4/6) and Medium-density Value line (STM32F100x8/B) devices.
  • New CMSIS V1.30 release
  2. Libraries
  • CMSIS
    • See Release Notes for STM32F10x CMSIS
  • STM32F10x_StdPeriph_Drive r
    • See Release Notes for STM32F10x_StdPeriph_Driver
  3. Project
  • STM32F10x_StdPeriph_Examples
    • See Release Notes for STM32F10x_StdPeriph_Examples
  • STM32F10x_StdPeriph_Template
    • See Release Notes for STM32F10x_StdPeriph_Template
  4. Utilities
  • STM32_EVAL
    • See Release Notes for STM32F10x_StdPeriph_Utilities

V3.1.2 - 09/28/2009

  1. General
  • Add support for Hitex Development Tools HiTOP.
  2. Libraries
  • CMSIS
    • system_stm32f10x.c: SetSysClockTo56() function, change the flash latency to 2 instead of 1
  • STM32F10x_StdPeriph_Drive r
    • stm32f10x_tim.c: in TIM_OCxInit() functions, add new instruction to set the CCxS bits (x= 1, 2, 3, 4) to 0, i.e. the channel CCx is configured as output. In the previous version these functions was assuming that the CCxS bits are reset; if a channel was previously configured in input, a call to this function doesn't allow using it in output mode. This is resolved with this modification.
    • stm32f10x_spi.h: I2S_InitTypeDef structure, change the type of I2S_AudioFreq field to uint32_t instead of uint16_t. This modification is needed to support I2S 96KHz frequency (available in Connectivity Line devices).
    • stm32f10x_flash.c: FLASH_EraseOptionBytes() function, add note to clarify this function behavior.
  3. Project
  • STM32F10x_StdPeriph_Examples
    • I2C\EEPROM example
      • i2c_ee.c: I2C_EE_BufferRead() function, the following line was removed

/* Clear EV6 by setting again the PE bit */
       I2C_Cmd(I2C_EE, ENABLE);

    • RCC example
      • main.c: SetSysClockTo56() function, change the flash latency to 2 instead of 1
  • Template
    • Add template projects for HiTOP toolchain to support Medium-density (Template\HiTOP\STM3210B-EVAL), High-density (Template\HiTOP\STM3210E-EVAL) and Connectivity line (Template\HiTOP\STM3210C-EVAL) devices.

V3.1.0 - 06/19/2009

  1. General
  • Update to support the additional peripherals and features embedded in the STM32F10x Connectivity Line devices.
  • Doxygen documentation enhanced to give more detail about driver function’s parameters: description, allowed values and required preconditions. This is mainly relevant for peripheral initialization structure’s members (PPP_InitTypeDef).
  • C++ support
  2. Libraries
  • CMSIS
    • stm32f10x.h
      • Add new define STM32F10X_CL to configure the library for Connectivity Line devices (default configuration)
      • Interrupt Number Definition (IRQn)
      • Add definition for Connectivity Line devices peripheral’s interrupts
      • For STM32 Low Density Devices, the SPI2_IRQn was removed since there is no SPI2 in these devices.
      • Add register's definitions, bits definitions and memory mapping for new peripherals (Ethernet and CAN2)
      • RCC, DBGMCU, EXTI, CAN, GPIO and AFIO bits definitions updated
      • AFIO_MAPR_SPI1 _REMAP define declaration corrected to AFIO_MAPR_SPI1_REMAP
      • Tailor HSE_Value to the to the selected device
    • system_stm32f10x.c
      • Clock configuration functions updated to support Connectivity line devices
      • Change SetSysClockTo20 function to SetSysClockTo24
    • startup
      • Add new startup files startup_stm32f10x_cl.s for Connectivity Line devices
      • For STM32 Low Density Devices, the SPI2_IRQHandler was removed since there is no SPI2 in these devices.
      • Use CMSIS Core Peripheral Access Layer V1.20
  • STM32F10x_StdPeriph_Driver
    • CAN: update to support CAN2 peripheral, with no impact on the API
      • Add new instance CAN2
      • Filter number updated
      • Add new function CAN_SlaveStartBank
    • RCC: update to support Connectivity Line devices, with no impact on the API
      • RCC_DeInit and RCC_GetSYSCLKSource functions updated
      • Function’s parameters list updated
      • Add new functions
        • RCC_PREDIV1Config, RCC_PREDIV2Config
        • RCC_PLL2Config, RCC_PLL2Cmd
        • RCC_PLL3Config, RCC_PLL3Cmd
        • RCC_OTGFSCLKConfig
        • RCC_I2S2CLKConfig, RCC_I2S3CLKConfig
        • RCC_AHBPeriphResetCmd
        • RCC_APB2Periph_ALL and RCC_APB1Periph_ALL parameters removed
    • GPIO
      • Update GPIO_PinRemapConfig function with 4 new AF remap
      • Add new function GPIO_ETH_MediaInterfaceConfig
    • EXTI
      • Add new internal EXTI Line 19 connected to ETH wakeup
    • DBGMCU
      • Add new define DBGMCU_CAN2_STOP
    • DAC
      • Add new define DAC_Trigger_T3_TRGO (to be used instead of DAC_Trigger_T8_TRGO, since TIM8 not available in Connectivity Line devices)
    • SPI/I2S
      • I2S_Init function updated to support new clock scheme implemented in Connectivity Line devices
      • Update I2S_AudioFreq defines to support frequency up to 96 KHz
    • FLASH
      • Update FLASH_EnableWriteProtection function header and parameter list to support Connectivity Line devices
  3. Project
    • STM32F10x_StdPeriph_Examples
      • Almost examples updated to run on Connectivity Line devices and STMicroelectronics STM3210C-EVAL evaluation board. Refer to the readme file provided within each example for more information on how to use the example with a specific board.
      • TIM: add new example TIM_Input_Capture
      • I2C: M24C08_EEPROM example renamed to EEPROM
    • Template
      • Template projects for EWARMv5, RIDE and RVMDK updated to support Connectivity Line devices and STMicroelectronics STM3210C-EVAL evaluation board.
  4. Utilities
  • Implement a new abstraction layer to interact with the Human Interface resources; buttons, LEDs, LCD and COM ports (USARTs) available on STMicroelectronics STM3210C-EVAL (Connectivity line), STM3210E-EVAL (High-Density) and STM3210B-EVAL (Medium-Density) evaluation boards. The stm32_eval.c driver provides a common API to interact with buttons, LEDs and COM ports, while these resources hardware definitions is made in the header file of each evaluation board (stm3210x_eval.h). A common API is provided to manage the LCD across the supported boards, with a separate driver for each board stm3210x_eval_lcd.c.

V3.0.0 - 04/06/2009

  1. General
  • STM3210x FW Library renamed to STM32F10x Standard Peripherals Library (StdPeriph_Lib)
  • STM32F10x Standard Peripherals Library is full CMSIS compliant
  • STM32F10x Standard Peripherals Library Structure is updated.
  • STM32F10x Standard Peripherals Package Architecture is enhanced
  • STM32F10x Standard Peripherals Library User Manual with *.chm format
  2. library
  • CAN driver updated
    • CAN driver was updated to support STM32F10xxx connectivity line products.
    • CAN peripheral was renamed as CAN1. All occurrences related to CAN were also renamed as CAN1 in the different drivers.
  • I2C driver
    • I2C event assert macro missing in stm32f10x_i2c.h file.
  • DBGMCU
    • Wrong defines in stm32f10x_dbgmcu.h: DBGMCU_TIM5_STOP, DBGMCU_TIM6_STOP, DBGMCU_TIM7_STOP and DBGMCU_TIM8_STOP defines values are wrong.

  • FSMC
    • Remove the FSMC AddressLowMapping configuration
  3. examples
  • FSMC NOR driver Timings are updated.
  • Add CAN "Normal" example
  • TIM "6Steps" example wave forms updated
  • NVIC "CM3_LPModes" and "System_Handlers" examples removed

For more details, please refer to AN2953 "How to migrate from the STM32F10xxx firmware library V2.0.3 to the STM32F10xxx standard peripheral library V3.0.0".

V2.0.3 - 09/22/2008

  1. General
  • stm32f10xfwlib_contents_html file updated:
    • Description of firmware library package content
    • Easy-to-use firmware library examples: add description of how to use the project template to run the selected example
  2. library
  • stm32f10x_map.h: add all STM32 Hardware registers bits definitions
  • stm32f10x_conf.h: add a define for HSEStartUp_TimeOut
  • stm32f10x_fsmc.h/.c:
    • FSMC_MemoryType_CRAM is changed to FSMC_MemoryType_PSRAM
    • FSMC_AsyncWait member removed from FSMC_NORSRAMInitTypeDef structure
    • FSMC_BusTurnAroundDuration parameter removed in case of write configuration
  • stm32f10x_rcc.h/.c:
    • RCC_FLAG_HSIRDY define value changed to 0x21.
    • StartUpCounterand HSEStatus variables are now local for RCC_WaitForHSEStartUp function.
  • stm32f10x_i2c.h/.c:
    • Add new event: EV8: I2C_EVENT_MASTER_BYTE_TRANSMITTING
  • stm32f10x_tim.c:
    • "=" operator changed to "|=" inside TIM_SelectOCxM function
  • stm32f10x_can.c: Definitions names changed
  3. examples
  • I2C Interrupt example
    • Example updated according to I2C driver update
  • I2C M24C08_EEPROM example
    • i2c_ee.c file: add a loop on I2C_FLAG_BUSY in I2C_EE_PageWrite and
    • I2C_EE_BufferRead functions
    • i2c_ee.c file: add STOP condition in I2C_EE_WaitEepromStandbyState function
  • SDIO example
    • Example updated to support SD Card V2.0 and SD High Capacity cards.
  • USART Polling example
    • USART TC flag check changed by USART TXE flag check

V2.0.2 - 07/11/2008

  1. library
  • stm32f10x_spi.c /.h
    • SPI_I2S_ClearFlag function: some flags are removed from the possible flags parameters list. This function can clear only CRCERR flag.
    • SPI_I2S_ClearITPendingBit function: some pending bits are removed from the possible pending bits parameters list. This function can clear only CRCERR pending bit.
  • stm32f10x_i2c.c /.h
    • I2C_ClearFlag function: some flags are removed from the possible flags parameters list. This function can clear only SMBALER, TIMEOUT, PECERR, OVR, AF, ARLO and BERR flags. The passed parameter can be any combination of above flags.
  • I2C_GetITStatus function checks on interrupt pending bit and the interrupt enable bit.
  • I2C_ClearITPendingBit function: some pending bits are removed from the possible pending bits parameters list. This function can clear only SMBALER, TIMEOUT, PECERR, OVR, AF, ARLO and BERR pending bits. The passed parameter can be any combination of above pending bits.
  • stm32f10x_usart.c /.h
    • USART_ClearFlag function: some flags are removed from the possible flags parameters list. This function can clear only CTS, LBD, TC and RXNE flags.
    • USART_GetITStatus function: IS_USART_IT macro is changed to IS_USART_GET_IT
    • USART_ClearITPendingBit function: some pending bits are removed from the possible pending bits parameters list. This function can clear only CTS, LBD, TC and RXNE pending bits.
  • stm32f10x_tim.c
    • remove IS_TIM_PERIPH_FLAG(TIMx, TIM_FLAG) macro from TIM_ClearFlag function.
  • stm32f10x_wwdg.c
    • use register direct access in the WWDG_GetFlagStatus function instead of bit banding access.
  • stm32f10x_gpio.c
    • GPIO_Init function update.
  2. examples
  • I2C Interrupt example
    • The example is changed to provide a description of how to manage data transfer from master transmitter to slave receiver and from slave transmitter to master receiver using interrupts.
    • add main.h file.
  • I2C 10bitAddress example
    • Updated according to the I2C driver update.
  • I2C DualAddress example
    • Updated according to the I2C driver update.
  • I2C SMBus example
    • Updated according to the I2C driver update
  • USART DMA_Interrupt example
    • Updated according to the USART driver update.
  • USART Smartcard example
    • Updated according to the USART driver update.
  • DAC Examples
    • GPIO_Configuration function updated: Once the DAC channel is enabled, the corresponding GPIO pin is automatically connected to the DAC converter. In order to avoid parasitic consumption, the GPIO pin should be configured in analog.
  • RTC LSI_Calib example
    • Example Update: add main.h file.

V2.0.1 - 06/13/2008

  • Remove the Firmware License Agreement file.
  • Update the source files's header to remove reference to the License.

V2.0 - 05/23/2008

  1. General
  • The FWLib V2.0 is an update of the V1.0 to support the extra peripherals and features embedded in the STM32 High-density devices.
  • Add Firmware License Agreement file.
  • For more details about the Firmware Library, please refer to the User. manual "UM0427 ARM«-based 32-bit MCU STM32F101xx and STM32F103xx Firmware Library" available for download from the ST microcontrollers website: www.st.com/stm32.
  • Glossary
    • Medium-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 32 and 128 Kbytes.
    • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
  2. library
  • Add driver for new peripherals: FSMC, SDIO and DAC.
  • stm32f10x_spi.c /.h
    • driver update to support new I2S functionality.
  • Add driver for DBGMCU and CRC modules
  • stm32f10x_dma.c /.h
    • driver update to support DMA2 channels.
  • stm32f10x_adc.c /.h
    • driver update to support ADC3.
  • stm32f10x_usart.c /.h
    • driver update to support UART4 and UART5.
    • new USART_ClockInitTypeDef structure derived from USART_InitTypeDef one (for USART synchronous parameters).
  • Timer peripherals driver
    • stm32f10x_tim1.c /.h and stm32f10x_tim.c /.h drivers merged in one single driver: stm32f10x_tim.c /.h
    • update to support new timer peripherals: TIM5, TIM6, TIM7 and TIM8.
    • add new macro for function parameters test.
    • TIM_TimeBaseInit, TIM_PrescalerConfig and TIM_GenerateEvent functions updated.
    • TIM_TIxExternalClockConfig, TIM_ETRClockMode1Config, TIM_ETRClockMode2Config, TIM_ETRConfig, TIM_SetIC1Prescaler, TIM_SetIC2Prescaler, TIM_SetIC3Prescaler and TIM_SetIC4Prescaler functions prototype update.
  • stm32f10x_gpio.c /.h
    • driver update to support GPIOF and GPIOG.
  • stm32f10x_lib.c /.h, stm32f10x_map.h, stm32f10x_conf.h
    • update to add new peripherals register declarations and header files inclusion.
  • stm32f10x_nvic.c /.h
  • stm32f10x_itc.c /.h
  • stm32f10x_vector.c /.s
    • update to support the new peripherals interrupt vector.
  • stm32f10x_rcc.c /.h
    • driver update to support new peripherals clock & reset enable/disable.
    • HSE Oscillator start up timeout increased to 0x01FF.
    • RCC_DeInit function update.
  • stm32f10x_bkp.c /.h
    • driver update to support the new 32 backup registers.
  • stm32f10x_map.h
  • stm32f10x_can.c
    • CAN register numbering update
  • stm32f10x_flash.h
    • update macro "IS_FLASH_ADDRESS" to support memory size up to 512KB.
  • stm32f10x_flash.c
    • FLASH_EnableWriteProtection function: update "FLASH_Pages" paramter values description.
  • stm32f10x_exti.c
    • EXTI_Init function update.
  • stm32f10x_type.h
    • 'S32_MIN' type corrected to "#define S32_MIN ((s32)-2147483648)".
  • stm32f10x_ppp.h
    • in all macros, put the passed parameter between parenthesis.
  • stm32f10x_can.c
    • extended ID coded in 29-bit long.
    • CAN initialization acknowledge error fixed.
  • stm32f10x_usart.c
    • change "&=" instead of "=" in USART_ClearITPendingBit and USART_ClearFlag functions.
  • stm32f10x_adc.c
    • replace "&=" by "=" in ADC_ClearITPendingBit and ADC_ClearFlag functions.
  • stm32f10x_i2c.c
    • replace "&=" by "=" in I2C_ClearITPendingBit and I2C_ClearFlag functions.
  • stm32f10x_tim.c
    • replace "&=" by "=" in TIM_ClearITPendingBit and TIM_ClearFlag functions.
  3. project
  • stm32f10x_it.c
    • update file description.
  • Add template projects for EWARM v5 and HiTOP toolchains.
  4. examples
  • FWLib V1.0 examples ported to run on STMicroelectronics STM3210E-EVAL evaluation board (in addition to STM3210B-EVAL)
  • Add new examples for FSMC, SDIO, DAC and I2S (run only on High-density devices).
  • Add new examples for ADC, DMA and RTC peripherals.
  • Add new example for CRC module.
  • Examples folder renamed, use of short name instead of examplex (x: 1 2 ...).

V1.0 - 10/08/2007

  1. library
  • Add template project with RIDE toolchain.
  • In all stm32f10x_ppp.c and stm32f10x_conf.h files: change "assert" macro name to "assert_param".
    • Note: If you are using the FW Library V0.3 in your application and you want to migrate to V1.0, you have to update your applications ôstm32f10x_conf.h file with the latest one (provided with V1.0).
  • stm32f10x_conf.h
    • Remove '#undef assert'
    • Change '#define DEBUG' by '#define DEBUG 1'
  • stm32f10x_type.h
    • Add new types: sc32, sc16, sc8, vsc32, vsc16 and vsc8
  • stm32f10x_it.c
    • Add basic fault exception handling: in "HardFaultException", "MemManageException", "BusFaultException" and "UsageFaultException" ISR the following code was added:

/* Go to infinite loop when exception occurs */
while (1)
{
}

  • stm32f10x_rcc.c
    • "RCC_WaitForHSEStartUp()" function updated to resolve issue with high GNU compiler optimization.
  • stm32f10x_gpio.h
  • '#define GPIO_Remap1_CAN ((u32)0x001D2000)' changed to '#define GPIO_Remap1_CAN ((u32)0x001D4000)'.
  • stm32f10x_rtc.c/.h
    • "RTC_GetPrescaler" function removed.
  • stm32f10x_bkp.c/.h
  • add "BKP_RTCOutputConfig()" function to allow to select the RTC output source(Calib clock, RTC Alarm or RTC Second) to output on Tamper pin and remove "BKP_RTCCalibrationClockOutputCmd()" function.
  • stm32f10x_can.h
    • CAN synchronization jump width defines updated
    • '#define CAN_SJW_0tq' ==> '#define CAN_SJW_1tq'
    • '#define CAN_SJW_1tq' ==> '#define CAN_SJW_2tq'
    • '#define CAN_SJW_2tq' ==> '#define CAN_SJW_3tq'
    • '#define CAN_SJW_3tq' ==> '#define CAN_SJW_4tq'
  • stm32f10x_tim1.c/.h
    • "TIM1_OCxNPolarityConfig(u16 TIM1_OCPolarity)" function: change parameter name to 'TIM1_OCNPolarity'
    • change 'TIM1_ICSelection_TRGI' by 'TIM1_ICSelection_TRC'
  • stm32f10x_tim.c/.h
    • change 'TIM_ICSelection_TRGI' by 'TIM_ICSelection_TRC'
  2. examples
  • ADC examples 3 & 4 updated
  • DEBUG example
  • Example modified to support RIDE specific printf function implementation
  • I2C example5
    • i2c_ee.c: add the following function prototypes: "void GPIO_Configuration(void)" add "void I2C_Configuration(void)"
  • Add GPIO pin toggle example.
  • BKP, CAN, DMA, NVIC and I2C examples readme files updated.
  • Use decimal (instead of hexadecimal) values constants in TIM, TIM1 and IWDG examples.
  • USART
    • example 12
      • USART3 ISR updated
      • Timeout define "SC_Receive_Timeout" updated to 0x4000
    • example 7
      • Example modified to support RIDE specific printf function implementation
  • RTC example
    • Example modified to support RIDE specific printf function implementation
    • Change "BKP_RTCCalibrationClockOutputCmd()" function by "RTC_ClockOutput()"
    • LSI removed as RTC clock source
  • IWDG example
    • LSI frequency value changed from 32 KHz to 40 KHz
  • Update the STM32F10x evaluation board name from STM32F10x-EVAL to STM3210B-EVAL

V0.3 - 05/21/2007

  • Created.

License

The enclosed firmware and all the related documentation are not covered by a License Agreement, if you need such License you can contact your local STMicroelectronics office.

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

For complete documentation on STM32(CORTEX M3) 32-Bit Microcontrollers visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: main.h Source File

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • RTC
  • LSI_Calib

RTC/LSI_Calib/main.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file RTC/LSI_Calib/main.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief  Header file for main.c.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __MAIN_H
00024 #define __MAIN_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028 #include "stm32_eval.h"
00029
00030
00031 /* Exported types ------------------------------------------------------------*/
00032 /* Exported constants --------------------------------------------------------*/
00033 /* Exported macro ------------------------------------------------------------*/
00034 /* Exported functions ------------------------------------------------------- */
00035 uint32_t IncrementVar_OperationComplete(void);
00036 uint32_t GetVar_OperationComplete(void);
00037 void SetVar_PeriodValue(uint32_t Value);
00038
00039 #endif /* __MAIN_H*/
00040
00041 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: platform_config.h Source File

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • SPI
  • DMA

SPI/DMA/platform_config.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    SPI/DMA/platform_config.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Evaluation board specific configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __PLATFORM_CONFIG_H
00024 #define __PLATFORM_CONFIG_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027
00028 /* Exported types ------------------------------------------------------------*/
00029 /* Exported constants --------------------------------------------------------*/
00030 /* Uncomment the line corresponding to the STMicroelectronics evaluation board
00031    used to run the example */
00032 #if !defined (USE_STM3210B_EVAL) &&  !defined (USE_STM3210E_EVAL) &&  !defined (USE_STM3210C_EVAL)&&  !defined (USE_STM32100E_EVAL)
00033  //#define USE_STM3210B_EVAL
00034  //#define USE_STM3210E_EVAL
00035  //#define USE_STM32100E_EVAL
00036  #define USE_STM3210C_EVAL
00037 #endif
00038
00039 /* Define the STM32F10x hardware depending on the used evaluation board */
00040 #if defined (USE_STM3210B_EVAL) || defined (USE_STM3210E_EVAL) || defined (USE_STM32100E_EVAL)
00041   #define SPI_MASTER                   SPI1
00042   #define SPI_MASTER_CLK               RCC_APB2Periph_SPI1
00043   #define SPI_MASTER_GPIO              GPIOA
00044   #define SPI_MASTER_GPIO_CLK          RCC_APB2Periph_GPIOA
00045   #define SPI_MASTER_PIN_NSS           GPIO_Pin_4
00046   #define SPI_MASTER_PIN_SCK           GPIO_Pin_5
00047   #define SPI_MASTER_PIN_MISO          GPIO_Pin_6
00048   #define SPI_MASTER_PIN_MOSI          GPIO_Pin_7
00049
00050   #define SPI_SLAVE                    SPI2
00051   #define SPI_SLAVE_CLK                RCC_APB1Periph_SPI2
00052   #define SPI_SLAVE_GPIO               GPIOB
00053   #define SPI_SLAVE_GPIO_CLK           RCC_APB2Periph_GPIOB
00054   #define SPI_SLAVE_PIN_NSS            GPIO_Pin_12
00055   #define SPI_SLAVE_PIN_SCK            GPIO_Pin_13
00056   #define SPI_SLAVE_PIN_MISO           GPIO_Pin_14
00057   #define SPI_SLAVE_PIN_MOSI           GPIO_Pin_15
00058   #define SPI_SLAVE_DMA                DMA1
00059   #define SPI_SLAVE_DMA_CLK            RCC_AHBPeriph_DMA1
00060   #define SPI_SLAVE_Rx_DMA_Channel     DMA1_Channel4
00061   #define SPI_SLAVE_Rx_DMA_FLAG        DMA1_FLAG_TC4
00062   #define SPI_SLAVE_Tx_DMA_Channel     DMA1_Channel5
00063   #define SPI_SLAVE_Tx_DMA_FLAG        DMA1_FLAG_TC5
00064   #define SPI_SLAVE_DR_Base            0x4000380C
00065
00066 #elif defined (USE_STM3210C_EVAL)
00067   #define SPI_MASTER                   SPI3   /* SPI pins are remapped by software */
00068   #define SPI_MASTER_CLK               RCC_APB1Periph_SPI3
00069   #define SPI_MASTER_GPIO              GPIOC
00070   #define SPI_MASTER_GPIO_NSS          GPIOA
00071   #define SPI_MASTER_GPIO_CLK          (RCC_APB2Periph_GPIOC | RCC_APB2Periph_GPIOA)
00072   #define SPI_MASTER_PIN_NSS           GPIO_Pin_4
00073   #define SPI_MASTER_PIN_SCK           GPIO_Pin_10
00074   #define SPI_MASTER_PIN_MISO          GPIO_Pin_11
00075   #define SPI_MASTER_PIN_MOSI          GPIO_Pin_12
00076
00077   #define SPI_SLAVE                    SPI2
00078   #define SPI_SLAVE_CLK                RCC_APB1Periph_SPI2
00079   #define SPI_SLAVE_GPIO               GPIOB
00080   #define SPI_SLAVE_GPIO_CLK           RCC_APB2Periph_GPIOB
00081   #define SPI_SLAVE_PIN_NSS            GPIO_Pin_12
00082   #define SPI_SLAVE_PIN_SCK            GPIO_Pin_13
00083   #define SPI_SLAVE_PIN_MISO           GPIO_Pin_14
00084   #define SPI_SLAVE_PIN_MOSI           GPIO_Pin_15
00085   #define SPI_SLAVE_DMA                DMA1
00086   #define SPI_SLAVE_DMA_CLK            RCC_AHBPeriph_DMA1
00087   #define SPI_SLAVE_Rx_DMA_Channel     DMA1_Channel4
00088   #define SPI_SLAVE_Rx_DMA_FLAG        DMA1_FLAG_TC4
00089   #define SPI_SLAVE_DR_Base            0x4000380C
00090
00091 #endif
00092
00093 /* Exported macro ------------------------------------------------------------*/
00094 /* Exported functions ------------------------------------------------------- */
00095
00096 #endif /* __PLATFORM_CONFIG_H */
00097
00098 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: platform_config.h Source File

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  • FullDuplex_SoftNSS

SPI/FullDuplex_SoftNSS/platform_config.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    SPI/FullDuplex_SoftNSS/platform_config.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Evaluation board specific configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __PLATFORM_CONFIG_H
00024 #define __PLATFORM_CONFIG_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027
00028 /* Exported types ------------------------------------------------------------*/
00029 /* Exported constants --------------------------------------------------------*/
00030 /* Uncomment the line corresponding to the STMicroelectronics evaluation board
00031    used to run the example */
00032 #if !defined (USE_STM32100B_EVAL) && !defined (USE_STM3210B_EVAL) &&  !defined (USE_STM3210E_EVAL) &&  !defined (USE_STM3210C_EVAL) &&  !defined (USE_STM32100E_EVAL)
00033  //#define USE_STM32100B_EVAL
00034  //#define USE_STM3210B_EVAL
00035  //#define USE_STM3210E_EVAL
00036  //#define USE_STM32100E_EVAL
00037  #define USE_STM3210C_EVAL
00038 #endif
00039
00040 /* Define the STM32F10x hardware depending on the used evaluation board */
00041 #if defined (USE_STM3210B_EVAL) || defined (USE_STM3210E_EVAL) || defined(USE_STM32100B_EVAL) || defined (USE_STM32100E_EVAL)
00042   #define SPIy                   SPI1
00043   #define SPIy_CLK               RCC_APB2Periph_SPI1
00044   #define SPIy_GPIO              GPIOA
00045   #define SPIy_GPIO_CLK          RCC_APB2Periph_GPIOA
00046   #define SPIy_PIN_SCK           GPIO_Pin_5
00047   #define SPIy_PIN_MISO          GPIO_Pin_6
00048   #define SPIy_PIN_MOSI          GPIO_Pin_7
00049
00050   #define SPIz                    SPI2
00051   #define SPIz_CLK                RCC_APB1Periph_SPI2
00052   #define SPIz_GPIO               GPIOB
00053   #define SPIz_GPIO_CLK           RCC_APB2Periph_GPIOB
00054   #define SPIz_PIN_SCK            GPIO_Pin_13
00055   #define SPIz_PIN_MISO           GPIO_Pin_14
00056   #define SPIz_PIN_MOSI           GPIO_Pin_15
00057
00058 #elif defined (USE_STM3210C_EVAL)
00059   #define SPIy                   SPI3   /* SPI pins are remapped by software */
00060   #define SPIy_CLK               RCC_APB1Periph_SPI3
00061   #define SPIy_GPIO              GPIOC
00062   #define SPIy_GPIO_CLK          RCC_APB2Periph_GPIOC
00063   #define SPIy_PIN_SCK           GPIO_Pin_10
00064   #define SPIy_PIN_MISO          GPIO_Pin_11
00065   #define SPIy_PIN_MOSI          GPIO_Pin_12
00066
00067   #define SPIz                    SPI2
00068   #define SPIz_CLK                RCC_APB1Periph_SPI2
00069   #define SPIz_GPIO               GPIOB
00070   #define SPIz_GPIO_CLK           RCC_APB2Periph_GPIOB
00071   #define SPIz_PIN_SCK            GPIO_Pin_13
00072   #define SPIz_PIN_MISO           GPIO_Pin_14
00073   #define SPIz_PIN_MOSI           GPIO_Pin_15
00074
00075 #endif
00076
00077 /* Exported macro ------------------------------------------------------------*/
00078 /* Exported functions ------------------------------------------------------- */
00079
00080 #endif /* __PLATFORM_CONFIG_H */
00081
00082 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: platform_config.h Source File

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  • SPI
  • Simplex_Interrupt

SPI/Simplex_Interrupt/platform_config.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    SPI/Simplex_Interrupt/platform_config.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Evaluation board specific configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __PLATFORM_CONFIG_H
00024 #define __PLATFORM_CONFIG_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027
00028 /* Exported types ------------------------------------------------------------*/
00029 /* Exported constants --------------------------------------------------------*/
00030 /* Uncomment the line corresponding to the STMicroelectronics evaluation board
00031    used to run the example */
00032 #if !defined (USE_STM32100B_EVAL) && !defined (USE_STM3210B_EVAL) &&  !defined (USE_STM3210E_EVAL) &&  !defined (USE_STM3210C_EVAL) &&  !defined (USE_STM32100E_EVAL)
00033  //#define USE_STM32100B_EVAL
00034  //#define USE_STM3210B_EVAL
00035  //#define USE_STM3210E_EVAL
00036  //#define USE_STM32100E_EVAL
00037  #define USE_STM3210C_EVAL
00038 #endif
00039
00040 /* Define the STM32F10x hardware depending on the used evaluation board */
00041 #if defined (USE_STM3210B_EVAL) || defined (USE_STM3210E_EVAL) || defined(USE_STM32100B_EVAL) || defined (USE_STM32100E_EVAL)
00042   #define SPI_MASTER                   SPI1
00043   #define SPI_MASTER_CLK               RCC_APB2Periph_SPI1
00044   #define SPI_MASTER_GPIO              GPIOA
00045   #define SPI_MASTER_GPIO_CLK          RCC_APB2Periph_GPIOA
00046   #define SPI_MASTER_PIN_SCK           GPIO_Pin_5
00047   #define SPI_MASTER_PIN_MISO          GPIO_Pin_6
00048   #define SPI_MASTER_PIN_MOSI          GPIO_Pin_7
00049   #define SPI_MASTER_IRQn              SPI1_IRQn
00050
00051   #define SPI_SLAVE                    SPI2
00052   #define SPI_SLAVE_CLK                RCC_APB1Periph_SPI2
00053   #define SPI_SLAVE_GPIO               GPIOB
00054   #define SPI_SLAVE_GPIO_CLK           RCC_APB2Periph_GPIOB
00055   #define SPI_SLAVE_PIN_SCK            GPIO_Pin_13
00056   #define SPI_SLAVE_PIN_MISO           GPIO_Pin_14
00057   #define SPI_SLAVE_PIN_MOSI           GPIO_Pin_15
00058   #define SPI_SLAVE_IRQn               SPI2_IRQn
00059
00060 #elif defined (USE_STM3210C_EVAL)
00061   #define SPI_MASTER                   SPI3   /* SPI pins are remapped by software */
00062   #define SPI_MASTER_CLK               RCC_APB1Periph_SPI3
00063   #define SPI_MASTER_GPIO              GPIOC
00064   #define SPI_MASTER_GPIO_CLK          RCC_APB2Periph_GPIOC
00065   #define SPI_MASTER_PIN_SCK           GPIO_Pin_10
00066   #define SPI_MASTER_PIN_MISO          GPIO_Pin_11
00067   #define SPI_MASTER_PIN_MOSI          GPIO_Pin_12
00068   #define SPI_MASTER_IRQn              SPI3_IRQn
00069
00070   #define SPI_SLAVE                    SPI2
00071   #define SPI_SLAVE_CLK                RCC_APB1Periph_SPI2
00072   #define SPI_SLAVE_GPIO               GPIOB
00073   #define SPI_SLAVE_GPIO_CLK           RCC_APB2Periph_GPIOB
00074   #define SPI_SLAVE_PIN_SCK            GPIO_Pin_13
00075   #define SPI_SLAVE_PIN_MISO           GPIO_Pin_14
00076   #define SPI_SLAVE_PIN_MOSI           GPIO_Pin_15
00077   #define SPI_SLAVE_IRQn               SPI2_IRQn
00078
00079 #endif
00080
00081 /* Exported macro ------------------------------------------------------------*/
00082 /* Exported functions ------------------------------------------------------- */
00083
00084 #endif /* __PLATFORM_CONFIG_H */
00085
00086 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32_eval.c Source File

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  • Utilities
  • STM32_EVAL

stm32_eval.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32_eval.c
00004   * @author  MCD Application Team
00005   * @version V4.5.0
00006   * @date    07-March-2011
00007   * @brief   STM32xx-EVAL abstraction layer.
00008   *          This file should be added to the main application to use the provided
00009   *          functions that manage Leds, push-buttons, COM ports and low level
00010   *          HW resources initialization of the different modules available on
00011   *          STM32 evaluation boards from STMicroelectronics.
00012   ******************************************************************************
00013   * @attention
00014   *
00015   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00016   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00017   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00018   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00019   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00020   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00021   *
00022   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00023   ******************************************************************************
00024   */
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32_eval.h"
00028
00029 /** @addtogroup Utilities
00030   * @{
00031   */
00032
00033 /** @defgroup STM32_EVAL
00034   * @brief This file provides firmware functions to manage Leds, push-buttons,
00035   *        COM ports and low level HW resources initialization of the different
00036   *        modules available on STM32 Evaluation Boards from STMicroelectronics.
00037   * @{
00038   */
00039
00040 /** @defgroup STM32_EVAL_Abstraction_Layer
00041   * @{
00042   */
00043
00044 #ifdef USE_STM32100B_EVAL
00045  #include "stm32100b_eval/stm32100b_eval.c"
00046 #elif defined USE_STM3210B_EVAL
00047  #include "stm3210b_eval/stm3210b_eval.c"
00048 #elif defined USE_STM3210E_EVAL
00049  #include "stm3210e_eval/stm3210e_eval.c"
00050 #elif defined USE_STM3210C_EVAL
00051  #include "stm3210c_eval/stm3210c_eval.c"
00052 #elif defined USE_STM32L152_EVAL
00053  #include "stm32l152_eval/stm32l152_eval.c"
00054 #elif defined USE_STM32100E_EVAL
00055  #include "stm32100e_eval/stm32100e_eval.c"
00056 #else
00057  #error "Please select first the STM32 EVAL board to be used (in stm32_eval.h)"
00058 #endif
00059
00060 /** @defgroup STM32_EVAL_Private_TypesDefinitions
00061   * @{
00062   */
00063 /**
00064   * @}
00065   */
00066
00067
00068 /** @defgroup STM32_EVAL_Private_Defines
00069   * @{
00070   */
00071 /**
00072   * @}
00073   */
00074
00075
00076 /** @defgroup STM32_EVAL_Private_Macros
00077   * @{
00078   */
00079 /**
00080   * @}
00081   */
00082
00083
00084 /** @defgroup STM32_EVAL_Private_Variables
00085   * @{
00086   */
00087 /**
00088   * @}
00089   */
00090
00091
00092 /** @defgroup STM32_EVAL_Private_FunctionPrototypes
00093   * @{
00094   */
00095 /**
00096   * @}
00097   */
00098
00099
00100 /** @defgroup STM32_EVAL_Private_Functions
00101   * @{
00102   */
00103 /**
00104   * @}
00105   */
00106
00107
00108 /**
00109   * @}
00110   */
00111
00112 /**
00113   * @}
00114   */
00115
00116 /**
00117   * @}
00118   */
00119
00120 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32_eval.h Source File

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  • Utilities
  • STM32_EVAL

stm32_eval.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32_eval.h
00004   * @author  MCD Application Team
00005   * @version V4.5.0
00006   * @date    07-March-2011
00007   * @brief   Header file for stm32_eval.c module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32_EVAL_H
00024 #define __STM32_EVAL_H
00025
00026 #ifdef __cplusplus
00027  extern "C" {
00028 #endif
00029
00030 /* Includes ------------------------------------------------------------------*/
00031
00032 /** @addtogroup Utilities
00033   * @{
00034   */
00035
00036 /** @addtogroup STM32_EVAL
00037   * @{
00038   */
00039
00040 /** @defgroup STM32_EVAL_Abstraction_Layer
00041   * @{
00042   */
00043
00044 /** @defgroup STM32_EVAL_HARDWARE_RESOURCES
00045   * @{
00046   */
00047
00048 /**
00049 @code
00050  The table below gives an overview of the hardware resources supported by each
00051  STM32 EVAL board.
00052      - LCD: TFT Color LCD (Parallel (FSMC) and Serial (SPI))
00053      - IOE: IO Expander on I2C
00054      - sFLASH: serial SPI FLASH (M25Pxxx)
00055      - sEE: serial I2C EEPROM (M24C08, M24C32, M24C64)
00056      - TSENSOR: Temperature Sensor (LM75)
00057      - SD: SD Card memory (SPI and SDIO (SD Card MODE))
00058   =================================================================================================================+
00059     STM32 EVAL     | LED | Buttons  | Com Ports |    LCD    | IOE  | sFLASH | sEE | TSENSOR | SD (SPI) | SD(SDIO)  |
00060   =================================================================================================================+
00061    STM3210B-EVAL   |  4  |    8     |     2     | YES (SPI) | NO   |  YES   | NO  |   YES   |    YES   |    NO     |
00062   -----------------------------------------------------------------------------------------------------------------+
00063    STM3210E-EVAL   |  4  |    8     |     2     | YES (FSMC)| NO   |  YES   | NO  |   YES   |    NO    |    YES    |
00064   -----------------------------------------------------------------------------------------------------------------+
00065    STM3210C-EVAL   |  4  |    3     |     1     | YES (SPI) | YES  |  NO    | YES |   NO    |    YES   |    NO     |
00066   -----------------------------------------------------------------------------------------------------------------+
00067    STM32100B-EVAL  |  4  |    8     |     2     | YES (SPI) | NO   |  YES   | NO  |   YES   |    YES   |    NO     |
00068   -----------------------------------------------------------------------------------------------------------------+
00069    STM32L152-EVAL  |  4  |    8     |     2     | YES (SPI) | NO   |  NO    | NO  |   YES   |    YES   |    NO     |
00070   -----------------------------------------------------------------------------------------------------------------+
00071    STM32100E-EVAL  |  4  |    8     |     2     | YES (FSMC)| YES  |  YES   | YES |   YES   |    YES   |    NO     |
00072   =================================================================================================================+
00073 @endcode
00074 */
00075
00076 /**
00077   * @}
00078   */
00079
00080 /** @defgroup STM32_EVAL_Exported_Types
00081   * @{
00082   */
00083 typedef enum
00084 {
00085   LED1 = 0,
00086   LED2 = 1,
00087   LED3 = 2,
00088   LED4 = 3
00089 } Led_TypeDef;
00090
00091 typedef enum
00092 {
00093   BUTTON_WAKEUP = 0,
00094   BUTTON_TAMPER = 1,
00095   BUTTON_KEY = 2,
00096   BUTTON_RIGHT = 3,
00097   BUTTON_LEFT = 4,
00098   BUTTON_UP = 5,
00099   BUTTON_DOWN = 6,
00100   BUTTON_SEL = 7
00101 } Button_TypeDef;
00102
00103 typedef enum
00104 {
00105   BUTTON_MODE_GPIO = 0,
00106   BUTTON_MODE_EXTI = 1
00107 } ButtonMode_TypeDef;
00108
00109 typedef enum
00110 {
00111   JOY_NONE = 0,
00112   JOY_SEL = 1,
00113   JOY_DOWN = 2,
00114   JOY_LEFT = 3,
00115   JOY_RIGHT = 4,
00116   JOY_UP = 5
00117 } JOYState_TypeDef
00118 ;
00119
00120 typedef enum
00121 {
00122   COM1 = 0,
00123   COM2 = 1
00124 } COM_TypeDef;
00125 /**
00126   * @}
00127   */
00128
00129 /** @defgroup STM32_EVAL_Exported_Constants
00130   * @{
00131   */
00132
00133 /**
00134   * @brief  Uncomment the line corresponding to the STMicroelectronics evaluation
00135   *   board used in your application.
00136   *
00137   *  Tip: To avoid modifying this file each time you need to switch between these
00138   *       boards, you can define the board in your toolchain compiler preprocessor.
00139   */
00140 #if !defined (USE_STM32100B_EVAL) && !defined (USE_STM3210B_EVAL) &&  !defined (USE_STM3210E_EVAL)\
00141    &&  !defined (USE_STM3210C_EVAL) &&  !defined (USE_STM32L152_EVAL) &&  !defined (USE_STM32100E_EVAL)
00142  //#define USE_STM32100B_EVAL
00143  //#define USE_STM3210B_EVAL
00144  //#define USE_STM3210E_EVAL
00145  //#define USE_STM3210C_EVAL
00146  //#define USE_STM32L152_EVAL
00147  //#define USE_STM32100E_EVAL
00148 #endif
00149
00150 #ifdef USE_STM32100B_EVAL
00151  #include "stm32f10x.h"
00152  #include "stm32100b_eval/stm32100b_eval.h"
00153 #elif defined USE_STM3210B_EVAL
00154  #include "stm32f10x.h"
00155  #include "stm3210b_eval/stm3210b_eval.h"
00156 #elif defined USE_STM3210E_EVAL
00157  #include "stm32f10x.h"
00158  #include "stm3210e_eval/stm3210e_eval.h"
00159 #elif defined USE_STM3210C_EVAL
00160  #include "stm32f10x.h"
00161  #include "stm3210c_eval/stm3210c_eval.h"
00162 #elif defined USE_STM32L152_EVAL
00163  #include "stm32l1xx.h"
00164  #include "stm32l152_eval/stm32l152_eval.h"
00165 #elif defined USE_STM32100E_EVAL
00166  #include "stm32f10x.h"
00167  #include "stm32100e_eval/stm32100e_eval.h"
00168 #else
00169  #error "Please select first the STM32 EVAL board to be used (in stm32_eval.h)"
00170 #endif
00171
00172
00173 /**
00174   * @brief  STM32 Button Defines Legacy
00175   */
00176 #define Button_WAKEUP        BUTTON_WAKEUP
00177 #define Button_TAMPER        BUTTON_TAMPER
00178 #define Button_KEY           BUTTON_KEY
00179 #define Button_RIGHT         BUTTON_RIGHT
00180 #define Button_LEFT          BUTTON_LEFT
00181 #define Button_UP            BUTTON_UP
00182 #define Button_DOWN          BUTTON_DOWN
00183 #define Button_SEL           BUTTON_SEL
00184 #define Mode_GPIO            BUTTON_MODE_GPIO
00185 #define Mode_EXTI            BUTTON_MODE_EXTI
00186 #define Button_Mode_TypeDef  ButtonMode_TypeDef
00187 #define JOY_CENTER           JOY_SEL
00188 #define JOY_State_TypeDef    JOYState_TypeDef
00189
00190 /**
00191   * @brief  LCD Defines Legacy
00192   */
00193 #define LCD_RSNWR_GPIO_CLK  LCD_NWR_GPIO_CLK
00194 #define LCD_SPI_GPIO_PORT   LCD_SPI_SCK_GPIO_PORT
00195 #define LCD_SPI_GPIO_CLK    LCD_SPI_SCK_GPIO_CLK
00196 #define R0                  LCD_REG_0
00197 #define R1                  LCD_REG_1
00198 #define R2                  LCD_REG_2
00199 #define R3                  LCD_REG_3
00200 #define R4                  LCD_REG_4
00201 #define R5                  LCD_REG_5
00202 #define R6                  LCD_REG_6
00203 #define R7                  LCD_REG_7
00204 #define R8                  LCD_REG_8
00205 #define R9                  LCD_REG_9
00206 #define R10                 LCD_REG_10
00207 #define R12                 LCD_REG_12
00208 #define R13                 LCD_REG_13
00209 #define R14                 LCD_REG_14
00210 #define R15                 LCD_REG_15
00211 #define R16                 LCD_REG_16
00212 #define R17                 LCD_REG_17
00213 #define R18                 LCD_REG_18
00214 #define R19                 LCD_REG_19
00215 #define R20                 LCD_REG_20
00216 #define R21                 LCD_REG_21
00217 #define R22                 LCD_REG_22
00218 #define R23                 LCD_REG_23
00219 #define R24                 LCD_REG_24
00220 #define R25                 LCD_REG_25
00221 #define R26                 LCD_REG_26
00222 #define R27                 LCD_REG_27
00223 #define R28                 LCD_REG_28
00224 #define R29                 LCD_REG_29
00225 #define R30                 LCD_REG_30
00226 #define R31                 LCD_REG_31
00227 #define R32                 LCD_REG_32
00228 #define R33                 LCD_REG_33
00229 #define R34                 LCD_REG_34
00230 #define R36                 LCD_REG_36
00231 #define R37                 LCD_REG_37
00232 #define R40                 LCD_REG_40
00233 #define R41                 LCD_REG_41
00234 #define R43                 LCD_REG_43
00235 #define R45                 LCD_REG_45
00236 #define R48                 LCD_REG_48
00237 #define R49                 LCD_REG_49
00238 #define R50                 LCD_REG_50
00239 #define R51                 LCD_REG_51
00240 #define R52                 LCD_REG_52
00241 #define R53                 LCD_REG_53
00242 #define R54                 LCD_REG_54
00243 #define R55                 LCD_REG_55
00244 #define R56                 LCD_REG_56
00245 #define R57                 LCD_REG_57
00246 #define R59                 LCD_REG_59
00247 #define R60                 LCD_REG_60
00248 #define R61                 LCD_REG_61
00249 #define R62                 LCD_REG_62
00250 #define R63                 LCD_REG_63
00251 #define R64                 LCD_REG_64
00252 #define R65                 LCD_REG_65
00253 #define R66                 LCD_REG_66
00254 #define R67                 LCD_REG_67
00255 #define R68                 LCD_REG_68
00256 #define R69                 LCD_REG_69
00257 #define R70                 LCD_REG_70
00258 #define R71                 LCD_REG_71
00259 #define R72                 LCD_REG_72
00260 #define R73                 LCD_REG_73
00261 #define R74                 LCD_REG_74
00262 #define R75                 LCD_REG_75
00263 #define R76                 LCD_REG_76
00264 #define R77                 LCD_REG_77
00265 #define R78                 LCD_REG_78
00266 #define R79                 LCD_REG_79
00267 #define R80                 LCD_REG_80
00268 #define R81                 LCD_REG_81
00269 #define R82                 LCD_REG_82
00270 #define R83                 LCD_REG_83
00271 #define R96                 LCD_REG_96
00272 #define R97                 LCD_REG_97
00273 #define R106                LCD_REG_106
00274 #define R118                LCD_REG_118
00275 #define R128                LCD_REG_128
00276 #define R129                LCD_REG_129
00277 #define R130                LCD_REG_130
00278 #define R131                LCD_REG_131
00279 #define R132                LCD_REG_132
00280 #define R133                LCD_REG_133
00281 #define R134                LCD_REG_134
00282 #define R135                LCD_REG_135
00283 #define R136                LCD_REG_136
00284 #define R137                LCD_REG_137
00285 #define R139                LCD_REG_139
00286 #define R140                LCD_REG_140
00287 #define R141                LCD_REG_141
00288 #define R143                LCD_REG_143
00289 #define R144                LCD_REG_144
00290 #define R145                LCD_REG_145
00291 #define R146                LCD_REG_146
00292 #define R147                LCD_REG_147
00293 #define R148                LCD_REG_148
00294 #define R149                LCD_REG_149
00295 #define R150                LCD_REG_150
00296 #define R151                LCD_REG_151
00297 #define R152                LCD_REG_152
00298 #define R153                LCD_REG_153
00299 #define R154                LCD_REG_154
00300 #define R157                LCD_REG_157
00301 #define R192                LCD_REG_192
00302 #define R193                LCD_REG_193
00303 #define R227                LCD_REG_227
00304 #define R229                LCD_REG_229
00305 #define R231                LCD_REG_231
00306 #define R239                LCD_REG_239
00307 #define White               LCD_COLOR_WHITE
00308 #define Black               LCD_COLOR_BLACK
00309 #define Grey                LCD_COLOR_GREY
00310 #define Blue                LCD_COLOR_BLUE
00311 #define Blue2               LCD_COLOR_BLUE2
00312 #define Red                 LCD_COLOR_RED
00313 #define Magenta             LCD_COLOR_MAGENTA
00314 #define Green               LCD_COLOR_GREEN
00315 #define Cyan                LCD_COLOR_CYAN
00316 #define Yellow              LCD_COLOR_YELLOW
00317 #define Line0               LCD_LINE_0
00318 #define Line1               LCD_LINE_1
00319 #define Line2               LCD_LINE_2
00320 #define Line3               LCD_LINE_3
00321 #define Line4               LCD_LINE_4
00322 #define Line5               LCD_LINE_5
00323 #define Line6               LCD_LINE_6
00324 #define Line7               LCD_LINE_7
00325 #define Line8               LCD_LINE_8
00326 #define Line9               LCD_LINE_9
00327 #define Horizontal          LCD_DIR_HORIZONTAL
00328 #define Vertical            LCD_DIR_VERTICAL
00329
00330
00331 /**
00332   * @}
00333   */
00334
00335 /** @defgroup STM32_EVAL_Exported_Macros
00336   * @{
00337   */
00338 /**
00339   * @}
00340   */
00341
00342 /** @defgroup STM32_EVAL_Exported_Functions
00343   * @{
00344   */
00345 /**
00346   * @}
00347   */
00348
00349 #ifdef __cplusplus
00350 }
00351 #endif
00352
00353
00354 #endif /* __STM32_EVAL_H */
00355
00356 /**
00357   * @}
00358   */
00359
00360 /**
00361   * @}
00362   */
00363
00364 /**
00365   * @}
00366   */
00367
00368 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32_eval.txt File Reference

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stm32_eval.txt File Reference

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: stm32_eval_i2c_ee.c Source File

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  • STM32F10x_StdPeriph_Lib_V3.5.0
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stm32_eval_i2c_ee.c

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32_eval_i2c_ee.c
00004   * @author  MCD Application Team
00005   * @version V4.5.0
00006   * @date    07-March-2011
00007   * @brief   This file provides a set of functions needed to manage the I2C M24CXX
00008   *          EEPROM memory mounted on STM32xx-EVAL board (refer to stm32_eval.h
00009   *          to know about the boards supporting this memory).
00010   *
00011   *          ===================================================================
00012   *          Note: This driver is intended for STM32F10x families devices only.
00013   *          ===================================================================
00014   *
00015   *          It implements a high level communication layer for read and write
00016   *          from/to this memory. The needed STM32 hardware resources (I2C and
00017   *          GPIO) are defined in stm32xx_eval.h file, and the initialization is
00018   *          performed in sEE_LowLevel_Init() function declared in stm32xx_eval.c
00019   *          file.
00020   *          You can easily tailor this driver to any other development board,
00021   *          by just adapting the defines for hardware resources and
00022   *          sEE_LowLevel_Init() function.
00023   *
00024   *          @note In this driver, basic read and write functions (sEE_ReadBuffer()
00025   *                and sEE_WritePage()) use the DMA to perform the data transfer
00026   *                to/from EEPROM memory (except when number of requested data is
00027   *                equal to 1). Thus, after calling these two functions, user
00028   *                application may perform other tasks while DMA is transferring
00029   *                data. The application should then monitor the variable holding
00030   *                the number of data in order to determine when the transfer is
00031   *                completed (variable decremented to 0). Stopping transfer tasks
00032   *                are performed into DMA interrupt handlers (which are integrated
00033   *                into this driver).
00034   *
00035   *     +-----------------------------------------------------------------+
00036   *     |                        Pin assignment                           |
00037   *     +---------------------------------------+-----------+-------------+
00038   *     |  STM32 I2C Pins                       |   sEE     |   Pin       |
00039   *     +---------------------------------------+-----------+-------------+
00040   *     | .                                     |   E0(GND) |    1  (0V)  |
00041   *     | .                                     |   E1(GND) |    2  (0V)  |
00042   *     | .                                     |   E2(GND) |    3  (0V)  |
00043   *     | .                                     |   E0(VSS) |    4  (0V)  |
00044   *     | sEE_I2C_SDA_PIN/ SDA                  |   SDA     |    5        |
00045   *     | sEE_I2C_SCL_PIN/ SCL                  |   SCL     |    6        |
00046   *     | .                                     |   /WC(VDD)|    7 (3.3V) |
00047   *     | .                                     |   VDD     |    8 (3.3V) |
00048   *     +---------------------------------------+-----------+-------------+
00049   ******************************************************************************
00050   * @attention
00051   *
00052   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00053   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00054   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00055   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00056   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00057   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00058   *
00059   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00060   ******************************************************************************
00061   */
00062
00063 /* Includes ------------------------------------------------------------------*/
00064 #include "stm32_eval_i2c_ee.h"
00065
00066 /** @addtogroup Utilities
00067   * @{
00068   */
00069
00070 /** @addtogroup STM32_EVAL
00071   * @{
00072   */
00073
00074 /** @addtogroup Common
00075   * @{
00076   */
00077
00078 /** @addtogroup STM32_EVAL_I2C_EE
00079   * @brief      This file includes the I2C EEPROM driver of STM32-EVAL boards.
00080   * @{
00081   */
00082
00083 /** @defgroup STM32_EVAL_I2C_EE_Private_Types
00084   * @{
00085   */
00086 /**
00087   * @}
00088   */
00089
00090
00091 /** @defgroup STM32_EVAL_I2C_EE_Private_Defines
00092   * @{
00093   */
00094 /**
00095   * @}
00096   */
00097
00098
00099 /** @defgroup STM32_EVAL_I2C_EE_Private_Macros
00100   * @{
00101   */
00102 /**
00103   * @}
00104   */
00105
00106
00107 /** @defgroup STM32_EVAL_I2C_EE_Private_Variables
00108   * @{
00109   */
00110 __IO uint16_t  sEEAddress = 0;
00111 __IO uint32_t  sEETimeout = sEE_LONG_TIMEOUT;
00112 __IO uint16_t* sEEDataReadPointer;
00113 __IO uint8_t*  sEEDataWritePointer;
00114 __IO uint8_t   sEEDataNum;
00115 /**
00116   * @}
00117   */
00118
00119
00120 /** @defgroup STM32_EVAL_I2C_EE_Private_Function_Prototypes
00121   * @{
00122   */
00123 /**
00124   * @}
00125   */
00126
00127
00128 /** @defgroup STM32_EVAL_I2C_EE_Private_Functions
00129   * @{
00130   */
00131
00132 /**
00133   * @brief  DeInitializes peripherals used by the I2C EEPROM driver.
00134   * @param  None
00135   * @retval None
00136   */
00137 void sEE_DeInit(void)
00138 {
00139   sEE_LowLevel_DeInit();
00140 }
00141
00142 /**
00143   * @brief  Initializes peripherals used by the I2C EEPROM driver.
00144   * @param  None
00145   * @retval None
00146   */
00147 void sEE_Init(void)
00148 {
00149   I2C_InitTypeDef  I2C_InitStructure;
00150
00151   sEE_LowLevel_Init();
00152
00153   /*!< I2C configuration */
00154   /* sEE_I2C configuration */
00155   I2C_InitStructure.I2C_Mode = I2C_Mode_I2C;
00156   I2C_InitStructure.I2C_DutyCycle = I2C_DutyCycle_2;
00157   I2C_InitStructure.I2C_OwnAddress1 = I2C_SLAVE_ADDRESS7;
00158   I2C_InitStructure.I2C_Ack = I2C_Ack_Enable;
00159   I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
00160   I2C_InitStructure.I2C_ClockSpeed = I2C_SPEED;
00161
00162   /* sEE_I2C Peripheral Enable */
00163   I2C_Cmd(sEE_I2C, ENABLE);
00164   /* Apply sEE_I2C configuration after enabling it */
00165   I2C_Init(sEE_I2C, &I2C_InitStructure);
00166
00167   /* Enable the sEE_I2C peripheral DMA requests */
00168   I2C_DMACmd(sEE_I2C, ENABLE);
00169
00170 #if defined (sEE_M24C64_32)
00171   /*!< Select the EEPROM address according to the state of E0, E1, E2 pins */
00172   sEEAddress = sEE_HW_ADDRESS;
00173 #elif defined (sEE_M24C08)
00174   /*!< depending on the sEE Address selected in the i2c_ee.h file */
00175  #ifdef sEE_Block0_ADDRESS
00176   /*!< Select the sEE Block0 to write on */
00177   sEEAddress = sEE_Block0_ADDRESS;
00178  #endif
00179
00180  #ifdef sEE_Block1_ADDRESS
00181   /*!< Select the sEE Block1 to write on */
00182   sEEAddress = sEE_Block1_ADDRESS;
00183  #endif
00184
00185  #ifdef sEE_Block2_ADDRESS
00186   /*!< Select the sEE Block2 to write on */
00187   sEEAddress = sEE_Block2_ADDRESS;
00188  #endif
00189
00190  #ifdef sEE_Block3_ADDRESS
00191   /*!< Select the sEE Block3 to write on */
00192   sEEAddress = sEE_Block3_ADDRESS;
00193  #endif
00194 #endif /*!< sEE_M24C64_32 */
00195 }
00196
00197 /**
00198   * @brief  Reads a block of data from the EEPROM.
00199   * @param  pBuffer : pointer to the buffer that receives the data read from
00200   *         the EEPROM.
00201   * @param  ReadAddr : EEPROM's internal address to start reading from.
00202   * @param  NumByteToRead : pointer to the variable holding number of bytes to
00203   *         be read from the EEPROM.
00204   *
00205   *        @note The variable pointed by NumByteToRead is reset to 0 when all the
00206   *              data are read from the EEPROM. Application should monitor this
00207   *              variable in order know when the transfer is complete.
00208   *
00209   * @note When number of data to be read is higher than 1, this function just
00210   *       configures the communication and enable the DMA channel to transfer data.
00211   *       Meanwhile, the user application may perform other tasks.
00212   *       When number of data to be read is 1, then the DMA is not used. The byte
00213   *       is read in polling mode.
00214   *
00215   * @retval sEE_OK (0) if operation is correctly performed, else return value
00216   *         different from sEE_OK (0) or the timeout user callback.
00217   */
00218 uint32_t sEE_ReadBuffer(uint8_t* pBuffer, uint16_t ReadAddr, uint16_t* NumByteToRead)
00219 {
00220   /* Set the pointer to the Number of data to be read. This pointer will be used
00221       by the DMA Transfer Completer interrupt Handler in order to reset the
00222       variable to 0. User should check on this variable in order to know if the
00223       DMA transfer has been complete or not. */
00224   sEEDataReadPointer = NumByteToRead;
00225
00226   /*!< While the bus is busy */
00227   sEETimeout = sEE_LONG_TIMEOUT;
00228   while(I2C_GetFlagStatus(sEE_I2C, I2C_FLAG_BUSY))
00229   {
00230     if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
00231   }
00232
00233   /*!< Send START condition */
00234   I2C_GenerateSTART(sEE_I2C, ENABLE);
00235
00236   /*!< Test on EV5 and clear it (cleared by reading SR1 then writing to DR) */
00237   sEETimeout = sEE_FLAG_TIMEOUT;
00238   while(!I2C_CheckEvent(sEE_I2C, I2C_EVENT_MASTER_MODE_SELECT))
00239   {
00240     if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
00241   }
00242
00243   /*!< Send EEPROM address for write */
00244   I2C_Send7bitAddress(sEE_I2C, sEEAddress, I2C_Direction_Transmitter);
00245
00246   /*!< Test on EV6 and clear it */
00247   sEETimeout = sEE_FLAG_TIMEOUT;
00248   while(!I2C_CheckEvent(sEE_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED))
00249   {
00250     if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
00251   }
00252
00253 #ifdef sEE_M24C08
00254
00255   /*!< Send the EEPROM's internal address to read from: Only one byte address */
00256   I2C_SendData(sEE_I2C, ReadAddr);
00257
00258 #elif defined (sEE_M24C64_32)
00259
00260   /*!< Send the EEPROM's internal address to read from: MSB of the address first */
00261   I2C_SendData(sEE_I2C, (uint8_t)((ReadAddr & 0xFF00) >> 8));
00262
00263   /*!< Test on EV8 and clear it */
00264   sEETimeout = sEE_FLAG_TIMEOUT;
00265   while(!I2C_CheckEvent(sEE_I2C, I2C_EVENT_MASTER_BYTE_TRANSMITTED))
00266   {
00267     if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
00268   }
00269
00270   /*!< Send the EEPROM's internal address to read from: LSB of the address */
00271   I2C_SendData(sEE_I2C, (uint8_t)(ReadAddr & 0x00FF));
00272
00273 #endif /*!< sEE_M24C08 */
00274
00275   /*!< Test on EV8 and clear it */
00276   sEETimeout = sEE_FLAG_TIMEOUT;
00277   while(I2C_GetFlagStatus(sEE_I2C, I2C_FLAG_BTF) == RESET)
00278   {
00279     if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
00280   }
00281
00282   /*!< Send STRAT condition a second time */
00283   I2C_GenerateSTART(sEE_I2C, ENABLE);
00284
00285   /*!< Test on EV5 and clear it (cleared by reading SR1 then writing to DR) */
00286   sEETimeout = sEE_FLAG_TIMEOUT;
00287   while(!I2C_CheckEvent(sEE_I2C, I2C_EVENT_MASTER_MODE_SELECT))
00288   {
00289     if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
00290   }
00291
00292   /*!< Send EEPROM address for read */
00293   I2C_Send7bitAddress(sEE_I2C, sEEAddress, I2C_Direction_Receiver);
00294
00295   /* If number of data to be read is 1, then DMA couldn't be used */
00296   /* One Byte Master Reception procedure (POLLING) ---------------------------*/
00297   if ((uint16_t)(*NumByteToRead) < 2)
00298   {
00299     /* Wait on ADDR flag to be set (ADDR is still not cleared at this level */
00300     sEETimeout = sEE_FLAG_TIMEOUT;
00301     while(I2C_GetFlagStatus(sEE_I2C, I2C_FLAG_ADDR) == RESET)
00302     {
00303       if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
00304     }
00305
00306     /*!< Disable Acknowledgement */
00307     I2C_AcknowledgeConfig(sEE_I2C, DISABLE);
00308
00309     /* Call User callback for critical section start (should typically disable interrupts) */
00310     sEE_EnterCriticalSection_UserCallback();
00311
00312     /* Clear ADDR register by reading SR1 then SR2 register (SR1 has already been read) */
00313     (void)sEE_I2C->SR2;
00314
00315     /*!< Send STOP Condition */
00316     I2C_GenerateSTOP(sEE_I2C, ENABLE);
00317
00318     /* Call User callback for critical section end (should typically re-enable interrupts) */
00319     sEE_ExitCriticalSection_UserCallback();
00320
00321     /* Wait for the byte to be received */
00322     sEETimeout = sEE_FLAG_TIMEOUT;
00323     while(I2C_GetFlagStatus(sEE_I2C, I2C_FLAG_RXNE) == RESET)
00324     {
00325       if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
00326     }
00327
00328     /*!< Read the byte received from the EEPROM */
00329     *pBuffer = I2C_ReceiveData(sEE_I2C);
00330
00331     /*!< Decrement the read bytes counter */
00332     (uint16_t)(*NumByteToRead)--;
00333
00334     /* Wait to make sure that STOP control bit has been cleared */
00335     sEETimeout = sEE_FLAG_TIMEOUT;
00336     while(sEE_I2C->CR1 & I2C_CR1_STOP)
00337     {
00338       if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
00339     }
00340
00341     /*!< Re-Enable Acknowledgement to be ready for another reception */
00342     I2C_AcknowledgeConfig(sEE_I2C, ENABLE);
00343   }
00344   else/* More than one Byte Master Reception procedure (DMA) -----------------*/
00345   {
00346     /*!< Test on EV6 and clear it */
00347     sEETimeout = sEE_FLAG_TIMEOUT;
00348     while(!I2C_CheckEvent(sEE_I2C, I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED))
00349     {
00350       if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
00351     }
00352
00353     /* Configure the DMA Rx Channel with the buffer address and the buffer size */
00354     sEE_LowLevel_DMAConfig((uint32_t)pBuffer, (uint16_t)(*NumByteToRead), sEE_DIRECTION_RX);
00355
00356     /* Inform the DMA that the next End Of Transfer Signal will be the last one */
00357     I2C_DMALastTransferCmd(sEE_I2C, ENABLE);
00358
00359     /* Enable the DMA Rx Channel */
00360     DMA_Cmd(sEE_I2C_DMA_CHANNEL_RX, ENABLE);
00361   }
00362
00363   /* If all operations OK, return sEE_OK (0) */
00364   return sEE_OK;
00365 }
00366
00367 /**
00368   * @brief  Writes more than one byte to the EEPROM with a single WRITE cycle.
00369   *
00370   * @note   The number of bytes (combined to write start address) must not
00371   *         cross the EEPROM page boundary. This function can only write into
00372   *         the boundaries of an EEPROM page.
00373   *         This function doesn't check on boundaries condition (in this driver
00374   *         the function sEE_WriteBuffer() which calls sEE_WritePage() is
00375   *         responsible of checking on Page boundaries).
00376   *
00377   * @param  pBuffer : pointer to the buffer containing the data to be written to
00378   *         the EEPROM.
00379   * @param  WriteAddr : EEPROM's internal address to write to.
00380   * @param  NumByteToWrite : pointer to the variable holding number of bytes to
00381   *         be written into the EEPROM.
00382   *
00383   *        @note The variable pointed by NumByteToWrite is reset to 0 when all the
00384   *              data are written to the EEPROM. Application should monitor this
00385   *              variable in order know when the transfer is complete.
00386   *
00387   * @note This function just configure the communication and enable the DMA
00388   *       channel to transfer data. Meanwhile, the user application may perform
00389   *       other tasks in parallel.
00390   *
00391   * @retval sEE_OK (0) if operation is correctly performed, else return value
00392   *         different from sEE_OK (0) or the timeout user callback.
00393   */
00394 uint32_t sEE_WritePage(uint8_t* pBuffer, uint16_t WriteAddr, uint8_t* NumByteToWrite)
00395 {
00396   /* Set the pointer to the Number of data to be written. This pointer will be used
00397       by the DMA Transfer Completer interrupt Handler in order to reset the
00398       variable to 0. User should check on this variable in order to know if the
00399       DMA transfer has been complete or not. */
00400   sEEDataWritePointer = NumByteToWrite;
00401
00402   /*!< While the bus is busy */
00403   sEETimeout = sEE_LONG_TIMEOUT;
00404   while(I2C_GetFlagStatus(sEE_I2C, I2C_FLAG_BUSY))
00405   {
00406     if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
00407   }
00408
00409   /*!< Send START condition */
00410   I2C_GenerateSTART(sEE_I2C, ENABLE);
00411
00412   /*!< Test on EV5 and clear it */
00413   sEETimeout = sEE_FLAG_TIMEOUT;
00414   while(!I2C_CheckEvent(sEE_I2C, I2C_EVENT_MASTER_MODE_SELECT))
00415   {
00416     if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
00417   }
00418
00419   /*!< Send EEPROM address for write */
00420   sEETimeout = sEE_FLAG_TIMEOUT;
00421   I2C_Send7bitAddress(sEE_I2C, sEEAddress, I2C_Direction_Transmitter);
00422
00423   /*!< Test on EV6 and clear it */
00424   sEETimeout = sEE_FLAG_TIMEOUT;
00425   while(!I2C_CheckEvent(sEE_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED))
00426   {
00427     if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
00428   }
00429
00430 #ifdef sEE_M24C08
00431
00432   /*!< Send the EEPROM's internal address to write to : only one byte Address */
00433   I2C_SendData(sEE_I2C, WriteAddr);
00434
00435 #elif defined(sEE_M24C64_32)
00436
00437   /*!< Send the EEPROM's internal address to write to : MSB of the address first */
00438   I2C_SendData(sEE_I2C, (uint8_t)((WriteAddr & 0xFF00) >> 8));
00439
00440   /*!< Test on EV8 and clear it */
00441   sEETimeout = sEE_FLAG_TIMEOUT;
00442   while(!I2C_CheckEvent(sEE_I2C, I2C_EVENT_MASTER_BYTE_TRANSMITTED))
00443   {
00444     if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
00445   }
00446
00447   /*!< Send the EEPROM's internal address to write to : LSB of the address */
00448   I2C_SendData(sEE_I2C, (uint8_t)(WriteAddr & 0x00FF));
00449
00450 #endif /*!< sEE_M24C08 */
00451
00452   /*!< Test on EV8 and clear it */
00453   sEETimeout = sEE_FLAG_TIMEOUT;
00454   while(!I2C_CheckEvent(sEE_I2C, I2C_EVENT_MASTER_BYTE_TRANSMITTED))
00455   {
00456     if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
00457   }
00458
00459   /* Configure the DMA Tx Channel with the buffer address and the buffer size */
00460   sEE_LowLevel_DMAConfig((uint32_t)pBuffer, (uint8_t)(*NumByteToWrite), sEE_DIRECTION_TX);
00461
00462   /* Enable the DMA Tx Channel */
00463   DMA_Cmd(sEE_I2C_DMA_CHANNEL_TX, ENABLE);
00464
00465   /* If all operations OK, return sEE_OK (0) */
00466   return sEE_OK;
00467 }
00468
00469 /**
00470   * @brief  Writes buffer of data to the I2C EEPROM.
00471   * @param  pBuffer : pointer to the buffer  containing the data to be written
00472   *         to the EEPROM.
00473   * @param  WriteAddr : EEPROM's internal address to write to.
00474   * @param  NumByteToWrite : number of bytes to write to the EEPROM.
00475   * @retval None
00476   */
00477 void sEE_WriteBuffer(uint8_t* pBuffer, uint16_t WriteAddr, uint16_t NumByteToWrite)
00478 {
00479   uint8_t NumOfPage = 0, NumOfSingle = 0, count = 0;
00480   uint16_t Addr = 0;
00481
00482   Addr = WriteAddr % sEE_PAGESIZE;
00483   count = sEE_PAGESIZE - Addr;
00484   NumOfPage =  NumByteToWrite / sEE_PAGESIZE;
00485   NumOfSingle = NumByteToWrite % sEE_PAGESIZE;
00486
00487   /*!< If WriteAddr is sEE_PAGESIZE aligned  */
00488   if(Addr == 0)
00489   {
00490     /*!< If NumByteToWrite < sEE_PAGESIZE */
00491     if(NumOfPage == 0)
00492     {
00493       /* Store the number of data to be written */
00494       sEEDataNum = NumOfSingle;
00495       /* Start writing data */
00496       sEE_WritePage(pBuffer, WriteAddr, (uint8_t*)(&sEEDataNum));
00497       /* Wait transfer through DMA to be complete */
00498       sEETimeout = sEE_LONG_TIMEOUT;
00499       while (sEEDataNum > 0)
00500       {
00501         if((sEETimeout--) == 0) {sEE_TIMEOUT_UserCallback(); return;};
00502       }
00503       sEE_WaitEepromStandbyState();
00504     }
00505     /*!< If NumByteToWrite > sEE_PAGESIZE */
00506     else
00507     {
00508       while(NumOfPage--)
00509       {
00510         /* Store the number of data to be written */
00511         sEEDataNum = sEE_PAGESIZE;
00512         sEE_WritePage(pBuffer, WriteAddr, (uint8_t*)(&sEEDataNum));
00513         /* Wait transfer through DMA to be complete */
00514         sEETimeout = sEE_LONG_TIMEOUT;
00515         while (sEEDataNum > 0)
00516         {
00517           if((sEETimeout--) == 0) {sEE_TIMEOUT_UserCallback(); return;};
00518         }
00519         sEE_WaitEepromStandbyState();
00520         WriteAddr +=  sEE_PAGESIZE;
00521         pBuffer += sEE_PAGESIZE;
00522       }
00523
00524       if(NumOfSingle!=0)
00525       {
00526         /* Store the number of data to be written */
00527         sEEDataNum = NumOfSingle;
00528         sEE_WritePage(pBuffer, WriteAddr, (uint8_t*)(&sEEDataNum));
00529         /* Wait transfer through DMA to be complete */
00530         sEETimeout = sEE_LONG_TIMEOUT;
00531         while (sEEDataNum > 0)
00532         {
00533           if((sEETimeout--) == 0) {sEE_TIMEOUT_UserCallback(); return;};
00534         }
00535         sEE_WaitEepromStandbyState();
00536       }
00537     }
00538   }
00539   /*!< If WriteAddr is not sEE_PAGESIZE aligned  */
00540   else
00541   {
00542     /*!< If NumByteToWrite < sEE_PAGESIZE */
00543     if(NumOfPage== 0)
00544     {
00545       /*!< If the number of data to be written is more than the remaining space
00546       in the current page: */
00547       if (NumByteToWrite > count)
00548       {
00549         /* Store the number of data to be written */
00550         sEEDataNum = count;
00551         /*!< Write the data conained in same page */
00552         sEE_WritePage(pBuffer, WriteAddr, (uint8_t*)(&sEEDataNum));
00553         /* Wait transfer through DMA to be complete */
00554         sEETimeout = sEE_LONG_TIMEOUT;
00555         while (sEEDataNum > 0)
00556         {
00557           if((sEETimeout--) == 0) {sEE_TIMEOUT_UserCallback(); return;};
00558         }
00559         sEE_WaitEepromStandbyState();
00560
00561         /* Store the number of data to be written */
00562         sEEDataNum = (NumByteToWrite - count);
00563         /*!< Write the remaining data in the following page */
00564         sEE_WritePage((uint8_t*)(pBuffer + count), (WriteAddr + count), (uint8_t*)(&sEEDataNum));
00565         /* Wait transfer through DMA to be complete */
00566         sEETimeout = sEE_LONG_TIMEOUT;
00567         while (sEEDataNum > 0)
00568         {
00569           if((sEETimeout--) == 0) {sEE_TIMEOUT_UserCallback(); return;};
00570         }
00571         sEE_WaitEepromStandbyState();
00572       }
00573       else
00574       {
00575         /* Store the number of data to be written */
00576         sEEDataNum = NumOfSingle;
00577         sEE_WritePage(pBuffer, WriteAddr, (uint8_t*)(&sEEDataNum));
00578         /* Wait transfer through DMA to be complete */
00579         sEETimeout = sEE_LONG_TIMEOUT;
00580         while (sEEDataNum > 0)
00581         {
00582           if((sEETimeout--) == 0) {sEE_TIMEOUT_UserCallback(); return;};
00583         }
00584         sEE_WaitEepromStandbyState();
00585       }
00586     }
00587     /*!< If NumByteToWrite > sEE_PAGESIZE */
00588     else
00589     {
00590       NumByteToWrite -= count;
00591       NumOfPage =  NumByteToWrite / sEE_PAGESIZE;
00592       NumOfSingle = NumByteToWrite % sEE_PAGESIZE;
00593
00594       if(count != 0)
00595       {
00596         /* Store the number of data to be written */
00597         sEEDataNum = count;
00598         sEE_WritePage(pBuffer, WriteAddr, (uint8_t*)(&sEEDataNum));
00599         /* Wait transfer through DMA to be complete */
00600         sEETimeout = sEE_LONG_TIMEOUT;
00601         while (sEEDataNum > 0)
00602         {
00603           if((sEETimeout--) == 0) {sEE_TIMEOUT_UserCallback(); return;};
00604         }
00605         sEE_WaitEepromStandbyState();
00606         WriteAddr += count;
00607         pBuffer += count;
00608       }
00609
00610       while(NumOfPage--)
00611       {
00612         /* Store the number of data to be written */
00613         sEEDataNum = sEE_PAGESIZE;
00614         sEE_WritePage(pBuffer, WriteAddr, (uint8_t*)(&sEEDataNum));
00615         /* Wait transfer through DMA to be complete */
00616         sEETimeout = sEE_LONG_TIMEOUT;
00617         while (sEEDataNum > 0)
00618         {
00619           if((sEETimeout--) == 0) {sEE_TIMEOUT_UserCallback(); return;};
00620         }
00621         sEE_WaitEepromStandbyState();
00622         WriteAddr +=  sEE_PAGESIZE;
00623         pBuffer += sEE_PAGESIZE;
00624       }
00625       if(NumOfSingle != 0)
00626       {
00627         /* Store the number of data to be written */
00628         sEEDataNum = NumOfSingle;
00629         sEE_WritePage(pBuffer, WriteAddr, (uint8_t*)(&sEEDataNum));
00630         /* Wait transfer through DMA to be complete */
00631         sEETimeout = sEE_LONG_TIMEOUT;
00632         while (sEEDataNum > 0)
00633         {
00634           if((sEETimeout--) == 0) {sEE_TIMEOUT_UserCallback(); return;};
00635         }
00636         sEE_WaitEepromStandbyState();
00637       }
00638     }
00639   }
00640 }
00641
00642 /**
00643   * @brief  Wait for EEPROM Standby state.
00644   *
00645   * @note  This function allows to wait and check that EEPROM has finished the
00646   *        last Write operation. It is mostly used after Write operation: after
00647   *        receiving the buffer to be written, the EEPROM may need additional
00648   *        time to actually perform the write operation. During this time, it
00649   *        doesn't answer to I2C packets addressed to it. Once the write operation
00650   *        is complete the EEPROM responds to its address.
00651   *
00652   * @note  It is not necessary to call this function after sEE_WriteBuffer()
00653   *        function (sEE_WriteBuffer() already calls this function after each
00654   *        write page operation).
00655   *
00656   * @param  None
00657   * @retval sEE_OK (0) if operation is correctly performed, else return value
00658   *         different from sEE_OK (0) or the timeout user callback.
00659   */
00660 uint32_t sEE_WaitEepromStandbyState(void)
00661 {
00662   __IO uint16_t tmpSR1 = 0;
00663   __IO uint32_t sEETrials = 0;
00664
00665   /*!< While the bus is busy */
00666   sEETimeout = sEE_LONG_TIMEOUT;
00667   while(I2C_GetFlagStatus(sEE_I2C, I2C_FLAG_BUSY))
00668   {
00669     if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
00670   }
00671
00672   /* Keep looping till the slave acknowledge his address or maximum number
00673      of trials is reached (this number is defined by sEE_MAX_TRIALS_NUMBER define
00674      in stm32_eval_i2c_ee.h file) */
00675   while (1)
00676   {
00677     /*!< Send START condition */
00678     I2C_GenerateSTART(sEE_I2C, ENABLE);
00679
00680     /*!< Test on EV5 and clear it */
00681     sEETimeout = sEE_FLAG_TIMEOUT;
00682     while(!I2C_CheckEvent(sEE_I2C, I2C_EVENT_MASTER_MODE_SELECT))
00683     {
00684       if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
00685     }
00686
00687     /*!< Send EEPROM address for write */
00688     I2C_Send7bitAddress(sEE_I2C, sEEAddress, I2C_Direction_Transmitter);
00689
00690     /* Wait for ADDR flag to be set (Slave acknowledged his address) */
00691     sEETimeout = sEE_LONG_TIMEOUT;
00692     do
00693     {
00694       /* Get the current value of the SR1 register */
00695       tmpSR1 = sEE_I2C->SR1;
00696
00697       /* Update the timeout value and exit if it reach 0 */
00698       if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
00699     }
00700     /* Keep looping till the Address is acknowledged or the AF flag is
00701        set (address not acknowledged at time) */
00702     while((tmpSR1 & (I2C_SR1_ADDR | I2C_SR1_AF)) == 0);
00703
00704     /* Check if the ADDR flag has been set */
00705     if (tmpSR1 & I2C_SR1_ADDR)
00706     {
00707       /* Clear ADDR Flag by reading SR1 then SR2 registers (SR1 have already
00708          been read) */
00709       (void)sEE_I2C->SR2;
00710
00711       /*!< STOP condition */
00712       I2C_GenerateSTOP(sEE_I2C, ENABLE);
00713
00714       /* Exit the function */
00715       return sEE_OK;
00716     }
00717     else
00718     {
00719       /*!< Clear AF flag */
00720       I2C_ClearFlag(sEE_I2C, I2C_FLAG_AF);
00721     }
00722
00723     /* Check if the maximum allowed numbe of trials has bee reached */
00724     if (sEETrials++ == sEE_MAX_TRIALS_NUMBER)
00725     {
00726       /* If the maximum number of trials has been reached, exit the function */
00727       return sEE_TIMEOUT_UserCallback();
00728     }
00729   }
00730 }
00731
00732 /**
00733   * @brief  This function handles the DMA Tx Channel interrupt Handler.
00734   * @param  None
00735   * @retval None
00736   */
00737 void sEE_I2C_DMA_TX_IRQHandler(void)
00738 {
00739   /* Check if the DMA transfer is complete */
00740   if(DMA_GetFlagStatus(sEE_I2C_DMA_FLAG_TX_TC) != RESET)
00741   {
00742     /* Disable the DMA Tx Channel and Clear all its Flags */
00743     DMA_Cmd(sEE_I2C_DMA_CHANNEL_TX, DISABLE);
00744     DMA_ClearFlag(sEE_I2C_DMA_FLAG_TX_GL);
00745
00746     /*!< Wait till all data have been physically transferred on the bus */
00747     sEETimeout = sEE_LONG_TIMEOUT;
00748     while(!I2C_GetFlagStatus(sEE_I2C, I2C_FLAG_BTF))
00749     {
00750       if((sEETimeout--) == 0) sEE_TIMEOUT_UserCallback();
00751     }
00752
00753     /*!< Send STOP condition */
00754     I2C_GenerateSTOP(sEE_I2C, ENABLE);
00755
00756     /* Perform a read on SR1 and SR2 register to clear eventualaly pending flags */
00757     (void)sEE_I2C->SR1;
00758     (void)sEE_I2C->SR2;
00759
00760     /* Reset the variable holding the number of data to be written */
00761     *sEEDataWritePointer = 0;
00762   }
00763 }
00764
00765 /**
00766   * @brief  This function handles the DMA Rx Channel interrupt Handler.
00767   * @param  None
00768   * @retval None
00769   */
00770 void sEE_I2C_DMA_RX_IRQHandler(void)
00771 {
00772   /* Check if the DMA transfer is complete */
00773   if(DMA_GetFlagStatus(sEE_I2C_DMA_FLAG_RX_TC) != RESET)
00774   {
00775     /*!< Send STOP Condition */
00776     I2C_GenerateSTOP(sEE_I2C, ENABLE);
00777
00778     /* Disable the DMA Rx Channel and Clear all its Flags */
00779     DMA_Cmd(sEE_I2C_DMA_CHANNEL_RX, DISABLE);
00780     DMA_ClearFlag(sEE_I2C_DMA_FLAG_RX_GL);
00781
00782     /* Reset the variable holding the number of data to be read */
00783     *sEEDataReadPointer = 0;
00784   }
00785 }
00786
00787 #ifdef USE_DEFAULT_TIMEOUT_CALLBACK
00788 /**
00789   * @brief  Basic management of the timeout situation.
00790   * @param  None.
00791   * @retval None.
00792   */
00793 uint32_t sEE_TIMEOUT_UserCallback(void)
00794 {
00795   /* Block communication and all processes */
00796   while (1)
00797   {
00798   }
00799 }
00800 #endif /* USE_DEFAULT_TIMEOUT_CALLBACK */
00801
00802 #ifdef USE_DEFAULT_CRITICAL_CALLBACK
00803 /**
00804   * @brief  Start critical section: these callbacks should be typically used
00805   *         to disable interrupts when entering a critical section of I2C communication
00806   *         You may use default callbacks provided into this driver by uncommenting the
00807   *         define USE_DEFAULT_CRITICAL_CALLBACK.
00808   *         Or you can comment that line and implement these callbacks into your
00809   *         application.
00810   * @param  None.
00811   * @retval None.
00812   */
00813 void sEE_EnterCriticalSection_UserCallback(void)
00814 {
00815   __disable_irq();
00816 }
00817
00818 /**
00819   * @brief  Start and End of critical section: these callbacks should be typically used
00820   *         to re-enable interrupts when exiting a critical section of I2C communication
00821   *         You may use default callbacks provided into this driver by uncommenting the
00822   *         define USE_DEFAULT_CRITICAL_CALLBACK.
00823   *         Or you can comment that line and implement these callbacks into your
00824   *         application.
00825   * @param  None.
00826   * @retval None.
00827   */
00828 void sEE_ExitCriticalSection_UserCallback(void)
00829 {
00830   __enable_irq();
00831 }
00832 #endif /* USE_DEFAULT_CRITICAL_CALLBACK */
00833
00834 /**
00835   * @}
00836   */
00837
00838 /**
00839   * @}
00840   */
00841
00842 /**
00843   * @}
00844   */
00845
00846 /**
00847   * @}
00848   */
00849
00850 /**
00851   * @}
00852   */
00853
00854 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32_eval_i2c_ee.h Source File

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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • Common

stm32_eval_i2c_ee.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32_eval_i2c_ee.h
00004   * @author  MCD Application Team
00005   * @version V4.5.0
00006   * @date    07-March-2011
00007   * @brief   This file contains all the functions prototypes for the stm32_eval_i2c_ee
00008   *          firmware driver.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00013   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00014   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00015   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00016   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00017   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00018   *
00019   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00020   ******************************************************************************
00021   */
00022
00023 /* Define to prevent recursive inclusion -------------------------------------*/
00024 #ifndef __STM32_EVAL_I2C_EE_H
00025 #define __STM32_EVAL_I2C_EE_H
00026
00027 #ifdef __cplusplus
00028  extern "C" {
00029 #endif
00030
00031 /* Includes ------------------------------------------------------------------*/
00032 #include "stm32_eval.h"
00033
00034 /** @addtogroup Utilities
00035   * @{
00036   */
00037
00038 /** @addtogroup STM32_EVAL
00039   * @{
00040   */
00041
00042 /** @addtogroup Common
00043   * @{
00044   */
00045
00046 /** @addtogroup STM32_EVAL_I2C_EE
00047   * @{
00048   */
00049
00050 /** @defgroup STM32_EVAL_I2C_EE_Exported_Types
00051   * @{
00052   */
00053
00054 /**
00055   * @}
00056   */
00057
00058 /** @defgroup STM32_EVAL_I2C_EE_Exported_Constants
00059   * @{
00060   */
00061
00062 /* Uncomment this line to use the default start and end of critical section
00063    callbacks (it disables then enabled all interrupts) */
00064 #define USE_DEFAULT_CRITICAL_CALLBACK
00065 /* Start and End of critical section: these callbacks should be typically used
00066    to disable interrupts when entering a critical section of I2C communication
00067    You may use default callbacks provided into this driver by uncommenting the
00068    define USE_DEFAULT_CRITICAL_CALLBACK.
00069    Or you can comment that line and implement these callbacks into your
00070    application */
00071
00072 /* Uncomment the following line to use the default sEE_TIMEOUT_UserCallback()
00073    function implemented in stm32_evel_i2c_ee.c file.
00074    sEE_TIMEOUT_UserCallback() function is called whenever a timeout condition
00075    occure during communication (waiting on an event that doesn't occur, bus
00076    errors, busy devices ...). */
00077 /* #define USE_DEFAULT_TIMEOUT_CALLBACK */
00078
00079 #if !defined (sEE_M24C08) && !defined (sEE_M24C64_32)
00080 /* Use the defines below the choose the EEPROM type */
00081 /* #define sEE_M24C08*/  /* Support the device: M24C08. */
00082 /* note: Could support: M24C01, M24C02, M24C04 and M24C16 if the blocks and
00083    HW address are correctly defined*/
00084 #define sEE_M24C64_32  /* Support the devices: M24C32 and M24C64 */
00085 #endif
00086
00087 #ifdef sEE_M24C64_32
00088 /* For M24C32 and M24C64 devices, E0,E1 and E2 pins are all used for device
00089   address selection (ne need for additional address lines). According to the
00090   Harware connection on the board (on STM3210C-EVAL board E0 = E1 = E2 = 0) */
00091
00092  #define sEE_HW_ADDRESS         0xA0   /* E0 = E1 = E2 = 0 */
00093
00094 #elif defined (sEE_M24C08)
00095 /* The M24C08W contains 4 blocks (128byte each) with the adresses below: E2 = 0
00096    EEPROM Addresses defines */
00097  #define sEE_Block0_ADDRESS     0xA0   /* E2 = 0 */
00098  /*#define sEE_Block1_ADDRESS     0xA2*/ /* E2 = 0 */
00099  /*#define sEE_Block2_ADDRESS     0xA4*/ /* E2 = 0 */
00100  /*#define sEE_Block3_ADDRESS     0xA6*/ /* E2 = 0 */
00101
00102 #endif /* sEE_M24C64_32 */
00103
00104 #define I2C_SPEED               300000
00105 #define I2C_SLAVE_ADDRESS7      0xA0
00106
00107 #if defined (sEE_M24C08)
00108  #define sEE_PAGESIZE           16
00109 #elif defined (sEE_M24C64_32)
00110  #define sEE_PAGESIZE           32
00111 #endif
00112
00113 /* Maximum Timeout values for flags and events waiting loops. These timeouts are
00114    not based on accurate values, they just guarantee that the application will
00115    not remain stuck if the I2C communication is corrupted.
00116    You may modify these timeout values depending on CPU frequency and application
00117    conditions (interrupts routines ...). */
00118 #define sEE_FLAG_TIMEOUT         ((uint32_t)0x1000)
00119 #define sEE_LONG_TIMEOUT         ((uint32_t)(10 * sEE_FLAG_TIMEOUT))
00120
00121 /* Maximum number of trials for sEE_WaitEepromStandbyState() function */
00122 #define sEE_MAX_TRIALS_NUMBER     150
00123
00124 /* Defintions for the state of the DMA transfer */
00125 #define sEE_STATE_READY           0
00126 #define sEE_STATE_BUSY            1
00127 #define sEE_STATE_ERROR           2
00128
00129 #define sEE_OK                    0
00130 #define sEE_FAIL                  1
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @defgroup STM32_EVAL_I2C_EE_Exported_Macros
00137   * @{
00138   */
00139 /**
00140   * @}
00141   */
00142
00143 /** @defgroup STM32_EVAL_I2C_EE_Exported_Functions
00144   * @{
00145   */
00146 void     sEE_DeInit(void);
00147 void     sEE_Init(void);
00148 uint32_t sEE_ReadBuffer(uint8_t* pBuffer, uint16_t ReadAddr, uint16_t* NumByteToRead);
00149 uint32_t sEE_WritePage(uint8_t* pBuffer, uint16_t WriteAddr, uint8_t* NumByteToWrite);
00150 void     sEE_WriteBuffer(uint8_t* pBuffer, uint16_t WriteAddr, uint16_t NumByteToWrite);
00151 uint32_t sEE_WaitEepromStandbyState(void);
00152
00153 /* USER Callbacks: These are functions for which prototypes only are declared in
00154    EEPROM driver and that should be implemented into user applicaiton. */
00155 /* sEE_TIMEOUT_UserCallback() function is called whenever a timeout condition
00156    occure during communication (waiting on an event that doesn't occur, bus
00157    errors, busy devices ...).
00158    You can use the default timeout callback implementation by uncommenting the
00159    define USE_DEFAULT_TIMEOUT_CALLBACK in stm32_evel_i2c_ee.h file.
00160    Typically the user implementation of this callback should reset I2C peripheral
00161    and re-initialize communication or in worst case reset all the application. */
00162 uint32_t sEE_TIMEOUT_UserCallback(void);
00163
00164 /* Start and End of critical section: these callbacks should be typically used
00165    to disable interrupts when entering a critical section of I2C communication
00166    You may use default callbacks provided into this driver by uncommenting the
00167    define USE_DEFAULT_CRITICAL_CALLBACK in stm32_evel_i2c_ee.h file..
00168    Or you can comment that line and implement these callbacks into your
00169    application */
00170 void sEE_EnterCriticalSection_UserCallback(void);
00171 void sEE_ExitCriticalSection_UserCallback(void);
00172
00173
00174 #ifdef __cplusplus
00175 }
00176 #endif
00177
00178 #endif /* __STM32_EVAL_I2C_EE_H */
00179 /**
00180   * @}
00181   */
00182
00183 /**
00184   * @}
00185   */
00186
00187 /**
00188   * @}
00189   */
00190
00191 /**
00192   * @}
00193   */
00194
00195 /**
00196   * @}
00197   */
00198
00199 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
00200
00201


STM32F10x Standard Peripherals Firmware Library: stm32_eval_i2c_tsensor.c Source File

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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • Common

stm32_eval_i2c_tsensor.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32_eval_i2c_tsensor.c
00004   * @author  MCD Application Team
00005   * @version V4.5.0
00006   * @date    07-March-2011
00007   * @brief   This file provides a set of functions needed to manage the I2C LM75
00008   *          temperature sensor mounted on STM32xx-EVAL board (refer to stm32_eval.h
00009   *          to know about the boards supporting this sensor).
00010   *          It implements a high level communication layer for read and write
00011   *          from/to this sensor. The needed STM32 hardware resources (I2C and
00012   *          GPIO) are defined in stm32xx_eval.h file, and the initialization is
00013   *          performed in LM75_LowLevel_Init() function declared in stm32xx_eval.c
00014   *          file.
00015   *
00016   *          Note:
00017   *          -----
00018   *          This driver uses the DMA method to send and receive data on I2C bus,
00019   *          which allows higher efficiency and reliability  of the communication.
00020   *
00021   *          You can easily tailor this driver to any other development board,
00022   *          by just adapting the defines for hardware resources and
00023   *          LM75_LowLevel_Init() function.
00024   *
00025   *     +-----------------------------------------------------------------+
00026   *     |                        Pin assignment                           |
00027   *     +---------------------------------------+-----------+-------------+
00028   *     |  STM32 I2C Pins                       |   STLM75  |   Pin       |
00029   *     +---------------------------------------+-----------+-------------+
00030   *     | LM75_I2C_SDA_PIN/ SDA                 |   SDA     |    1        |
00031   *     | LM75_I2C_SCL_PIN/ SCL                 |   SCL     |    2        |
00032   *     | LM75_I2C_SMBUSALERT_PIN/ SMBUS ALERT  |   OS/INT  |    3        |
00033   *     | .                                     |   GND     |    4  (0V)  |
00034   *     | .                                     |   GND     |    5  (0V)  |
00035   *     | .                                     |   GND     |    6  (0V)  |
00036   *     | .                                     |   GND     |    7  (0V)  |
00037   *     | .                                     |   VDD     |    8  (3.3V)|
00038   *     +---------------------------------------+-----------+-------------+
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00043   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00044   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00045   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00046   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00047   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00048   *
00049   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00050   ******************************************************************************
00051   */
00052
00053 /* Includes ------------------------------------------------------------------*/
00054 #include "stm32_eval_i2c_tsensor.h"
00055
00056 /** @addtogroup Utilities
00057   * @{
00058   */
00059
00060 /** @addtogroup STM32_EVAL
00061   * @{
00062   */
00063
00064 /** @addtogroup Common
00065   * @{
00066   */
00067
00068 /** @addtogroup STM32_EVAL_I2C_TSENSOR
00069   * @brief      This file includes the LM75 Temperature Sensor driver of
00070   *             STM32-EVAL boards.
00071   * @{
00072   */
00073
00074 /** @defgroup STM32_EVAL_I2C_TSENSOR_Private_Types
00075   * @{
00076   */
00077 /**
00078   * @}
00079   */
00080
00081 /** @defgroup STM32_EVAL_I2C_TSENSOR_Private_Defines
00082   * @{
00083   */
00084 #define LM75_SD_SET                0x01 /*!< Set SD bit in the configuration register */
00085 #define LM75_SD_RESET              0xFE /*!< Reset SD bit in the configuration register */
00086 /**
00087   * @}
00088   */
00089
00090 /** @defgroup STM32_EVAL_I2C_TSENSOR_Private_Macros
00091   * @{
00092   */
00093 /**
00094   * @}
00095   */
00096
00097 /** @defgroup STM32_EVAL_I2C_TSENSOR_Private_Variables
00098   * @{
00099   */
00100
00101 __IO uint32_t  LM75_Timeout = LM75_LONG_TIMEOUT;
00102 /**
00103   * @}
00104   */
00105
00106 /** @defgroup STM32_EVAL_I2C_TSENSOR_Private_Function_Prototypes
00107   * @{
00108   */
00109 static void LM75_DMA_Config(LM75_DMADirection_TypeDef Direction, uint8_t* buffer, uint8_t NumData);
00110
00111 /**
00112   * @}
00113   */
00114
00115
00116 /** @defgroup STM32_EVAL_I2C_TSENSOR_Private_Functions
00117   * @{
00118   */
00119
00120 /**
00121   * @brief  DeInitializes the LM75_I2C.
00122   * @param  None
00123   * @retval None
00124   */
00125 void LM75_DeInit(void)
00126 {
00127   LM75_LowLevel_DeInit();
00128 }
00129
00130 /**
00131   * @brief  Initializes the LM75_I2C.
00132   * @param  None
00133   * @retval None
00134   */
00135 void LM75_Init(void)
00136 {
00137   I2C_InitTypeDef   I2C_InitStructure;
00138
00139   LM75_LowLevel_Init();
00140
00141   I2C_DeInit(LM75_I2C);
00142
00143   /*!< LM75_I2C Init */
00144   I2C_InitStructure.I2C_Mode = I2C_Mode_SMBusHost;
00145   I2C_InitStructure.I2C_DutyCycle = I2C_DutyCycle_2;
00146   I2C_InitStructure.I2C_OwnAddress1 = 0x00;
00147   I2C_InitStructure.I2C_Ack = I2C_Ack_Enable;
00148   I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
00149   I2C_InitStructure.I2C_ClockSpeed = LM75_I2C_SPEED;
00150   I2C_Init(LM75_I2C, &I2C_InitStructure);
00151
00152   /*!< Enable SMBus Alert interrupt */
00153   I2C_ITConfig(LM75_I2C, I2C_IT_ERR, ENABLE);
00154
00155   /*!< LM75_I2C Init */
00156   I2C_Cmd(LM75_I2C, ENABLE);
00157 }
00158
00159
00160 /**
00161   * @brief  Configure the DMA Peripheral used to handle communication via I2C.
00162   * @param  None
00163   * @retval None
00164   */
00165
00166 static void LM75_DMA_Config(LM75_DMADirection_TypeDef Direction, uint8_t* buffer, uint8_t NumData)
00167 {
00168   DMA_InitTypeDef DMA_InitStructure;
00169
00170   RCC_AHBPeriphClockCmd(LM75_DMA_CLK, ENABLE);
00171
00172   /* Initialize the DMA_PeripheralBaseAddr member */
00173   DMA_InitStructure.DMA_PeripheralBaseAddr = LM75_I2C_DR;
00174   /* Initialize the DMA_MemoryBaseAddr member */
00175   DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)buffer;
00176    /* Initialize the DMA_PeripheralInc member */
00177   DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
00178   /* Initialize the DMA_MemoryInc member */
00179   DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
00180   /* Initialize the DMA_PeripheralDataSize member */
00181   DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
00182   /* Initialize the DMA_MemoryDataSize member */
00183   DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
00184   /* Initialize the DMA_Mode member */
00185   DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
00186   /* Initialize the DMA_Priority member */
00187   DMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh;
00188   /* Initialize the DMA_M2M member */
00189   DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
00190
00191   /* If using DMA for Reception */
00192   if (Direction == LM75_DMA_RX)
00193   {
00194     /* Initialize the DMA_DIR member */
00195     DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
00196
00197     /* Initialize the DMA_BufferSize member */
00198     DMA_InitStructure.DMA_BufferSize = NumData;
00199
00200     DMA_DeInit(LM75_DMA_RX_CHANNEL);
00201
00202     DMA_Init(LM75_DMA_RX_CHANNEL, &DMA_InitStructure);
00203   }
00204    /* If using DMA for Transmission */
00205   else if (Direction == LM75_DMA_TX)
00206   {
00207     /* Initialize the DMA_DIR member */
00208     DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
00209
00210     /* Initialize the DMA_BufferSize member */
00211     DMA_InitStructure.DMA_BufferSize = NumData;
00212
00213     DMA_DeInit(LM75_DMA_TX_CHANNEL);
00214
00215     DMA_Init(LM75_DMA_TX_CHANNEL, &DMA_InitStructure);
00216   }
00217 }
00218
00219
00220 /**
00221   * @brief  Checks the LM75 status.
00222   * @param  None
00223   * @retval ErrorStatus: LM75 Status (ERROR or SUCCESS).
00224   */
00225 ErrorStatus LM75_GetStatus(void)
00226 {
00227   uint32_t I2C_TimeOut = I2C_TIMEOUT;
00228
00229   /*!< Clear the LM75_I2C AF flag */
00230   I2C_ClearFlag(LM75_I2C, I2C_FLAG_AF);
00231
00232   /*!< Enable LM75_I2C acknowledgement if it is already disabled by other function */
00233   I2C_AcknowledgeConfig(LM75_I2C, ENABLE);
00234
00235   /*---------------------------- Transmission Phase ---------------------------*/
00236
00237   /*!< Send LM75_I2C START condition */
00238   I2C_GenerateSTART(LM75_I2C, ENABLE);
00239
00240   /*!< Test on LM75_I2C EV5 and clear it */
00241   while ((!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_SB)) && I2C_TimeOut)  /*!< EV5 */
00242   {
00243     I2C_TimeOut--;
00244   }
00245   if (I2C_TimeOut == 0)
00246   {
00247     return ERROR;
00248   }
00249
00250   I2C_TimeOut = I2C_TIMEOUT;
00251
00252   /*!< Send STLM75 slave address for write */
00253   I2C_Send7bitAddress(LM75_I2C, LM75_ADDR, I2C_Direction_Transmitter);
00254
00255   while ((!I2C_CheckEvent(LM75_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED)) && I2C_TimeOut)/* EV6 */
00256   {
00257     I2C_TimeOut--;
00258   }
00259
00260   if ((I2C_GetFlagStatus(LM75_I2C, I2C_FLAG_AF) != 0x00) || (I2C_TimeOut == 0))
00261   {
00262     return ERROR;
00263   }
00264   else
00265   {
00266     return SUCCESS;
00267   }
00268 }
00269 /**
00270   * @brief  Read the specified register from the LM75.
00271   * @param  RegName: specifies the LM75 register to be read.
00272   *              This member can be one of the following values:
00273   *                  - LM75_REG_TEMP: temperature register
00274   *                  - LM75_REG_TOS: Over-limit temperature register
00275   *                  - LM75_REG_THYS: Hysteresis temperature register
00276   * @retval LM75 register value.
00277   */
00278 uint16_t LM75_ReadReg(uint8_t RegName)
00279 {
00280   uint8_t LM75_BufferRX[2] ={0,0};
00281   uint16_t tmp = 0;
00282
00283    /* Test on BUSY Flag */
00284   LM75_Timeout = LM75_LONG_TIMEOUT;
00285   while (I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_BUSY))
00286   {
00287     if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
00288   }
00289
00290   /* Configure DMA Peripheral */
00291   LM75_DMA_Config(LM75_DMA_RX, (uint8_t*)LM75_BufferRX, 2);
00292
00293   /* Enable DMA NACK automatic generation */
00294   I2C_DMALastTransferCmd(LM75_I2C, ENABLE);
00295
00296   /* Enable the I2C peripheral */
00297   I2C_GenerateSTART(LM75_I2C, ENABLE);
00298
00299   /* Test on SB Flag */
00300   LM75_Timeout = LM75_FLAG_TIMEOUT;
00301   while (!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_SB))
00302   {
00303     if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
00304   }
00305
00306   /* Send device address for write */
00307   I2C_Send7bitAddress(LM75_I2C, LM75_ADDR, I2C_Direction_Transmitter);
00308
00309   /* Test on ADDR Flag */
00310   LM75_Timeout = LM75_FLAG_TIMEOUT;
00311   while (!I2C_CheckEvent(LM75_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED))
00312   {
00313     if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
00314   }
00315
00316   /* Send the device's internal address to write to */
00317   I2C_SendData(LM75_I2C, RegName);
00318
00319   /* Test on TXE FLag (data sent) */
00320   LM75_Timeout = LM75_FLAG_TIMEOUT;
00321   while ((!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_TXE)) && (!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_BTF)))
00322   {
00323     if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
00324   }
00325
00326   /* Send START condition a second time */
00327   I2C_GenerateSTART(LM75_I2C, ENABLE);
00328
00329   /* Test on SB Flag */
00330   LM75_Timeout = LM75_FLAG_TIMEOUT;
00331   while (!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_SB))
00332   {
00333     if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
00334   }
00335
00336   /* Send LM75 address for read */
00337   I2C_Send7bitAddress(LM75_I2C, LM75_ADDR, I2C_Direction_Receiver);
00338
00339   /* Test on ADDR Flag */
00340   LM75_Timeout = LM75_FLAG_TIMEOUT;
00341   while (!I2C_CheckEvent(LM75_I2C, I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED))
00342   {
00343     if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
00344   }
00345
00346   /* Enable I2C DMA request */
00347   I2C_DMACmd(LM75_I2C,ENABLE);
00348
00349   /* Enable DMA RX Channel */
00350   DMA_Cmd(LM75_DMA_RX_CHANNEL, ENABLE);
00351
00352   /* Wait until DMA Transfer Complete */
00353   LM75_Timeout = LM75_LONG_TIMEOUT;
00354   while (!DMA_GetFlagStatus(LM75_DMA_RX_TCFLAG))
00355   {
00356     if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
00357   }
00358
00359   /* Send STOP Condition */
00360   I2C_GenerateSTOP(LM75_I2C, ENABLE);
00361
00362   /* Disable DMA RX Channel */
00363   DMA_Cmd(LM75_DMA_RX_CHANNEL, DISABLE);
00364
00365   /* Disable I2C DMA request */
00366   I2C_DMACmd(LM75_I2C,DISABLE);
00367
00368   /* Clear DMA RX Transfer Complete Flag */
00369   DMA_ClearFlag(LM75_DMA_RX_TCFLAG);
00370
00371   /*!< Store LM75_I2C received data */
00372   tmp = (uint16_t)(LM75_BufferRX[0] << 8);
00373   tmp |= LM75_BufferRX[1];
00374
00375   /* return a Reg value */
00376   return (uint16_t)tmp;
00377 }
00378
00379 /**
00380   * @brief  Write to the specified register of the LM75.
00381   * @param  RegName: specifies the LM75 register to be written.
00382   *              This member can be one of the following values:
00383   *                  - LM75_REG_TOS: Over-limit temperature register
00384   *                  - LM75_REG_THYS: Hysteresis temperature register
00385   * @param  RegValue: value to be written to LM75 register.
00386   * @retval None
00387   */
00388 uint8_t LM75_WriteReg(uint8_t RegName, uint16_t RegValue)
00389 {
00390   uint8_t LM75_BufferTX[2] ={0,0};
00391   LM75_BufferTX[0] = (uint8_t)(RegValue >> 8);
00392   LM75_BufferTX[1] = (uint8_t)(RegValue);
00393
00394   /* Test on BUSY Flag */
00395   LM75_Timeout = LM75_LONG_TIMEOUT;
00396   while (I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_BUSY))
00397   {
00398     if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
00399   }
00400
00401   /* Configure DMA Peripheral */
00402   LM75_DMA_Config(LM75_DMA_TX, (uint8_t*)LM75_BufferTX, 2);
00403
00404   /* Enable the I2C peripheral */
00405   I2C_GenerateSTART(LM75_I2C, ENABLE);
00406
00407   /* Test on SB Flag */
00408   LM75_Timeout = LM75_FLAG_TIMEOUT;
00409   while (I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_SB) == RESET)
00410   {
00411     if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
00412   }
00413
00414   /* Transmit the slave address and enable writing operation */
00415   I2C_Send7bitAddress(LM75_I2C, LM75_ADDR, I2C_Direction_Transmitter);
00416
00417   /* Test on ADDR Flag */
00418   LM75_Timeout = LM75_FLAG_TIMEOUT;
00419   while (!I2C_CheckEvent(LM75_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED))
00420   {
00421     if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
00422   }
00423
00424   /* Transmit the first address for r/w operations */
00425   I2C_SendData(LM75_I2C, RegName);
00426
00427   /* Test on TXE FLag (data sent) */
00428   LM75_Timeout = LM75_FLAG_TIMEOUT;
00429   while ((!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_TXE)) && (!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_BTF)))
00430   {
00431     if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
00432   }
00433
00434   /* Enable I2C DMA request */
00435   I2C_DMACmd(LM75_I2C,ENABLE);
00436
00437   /* Enable DMA TX Channel */
00438   DMA_Cmd(LM75_DMA_TX_CHANNEL, ENABLE);
00439
00440   /* Wait until DMA Transfer Complete */
00441   LM75_Timeout = LM75_LONG_TIMEOUT;
00442   while (!DMA_GetFlagStatus(LM75_DMA_TX_TCFLAG))
00443   {
00444     if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
00445   }
00446
00447   /* Wait until BTF Flag is set before generating STOP */
00448   LM75_Timeout = LM75_LONG_TIMEOUT;
00449   while (I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_BTF))
00450   {
00451     if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
00452   }
00453
00454   /* Send STOP Condition */
00455   I2C_GenerateSTOP(LM75_I2C, ENABLE);
00456
00457   /* Disable DMA TX Channel */
00458   DMA_Cmd(LM75_DMA_TX_CHANNEL, DISABLE);
00459
00460   /* Disable I2C DMA request */
00461   I2C_DMACmd(LM75_I2C,DISABLE);
00462
00463   /* Clear DMA TX Transfer Complete Flag */
00464   DMA_ClearFlag(LM75_DMA_TX_TCFLAG);
00465
00466   return LM75_OK;
00467 }
00468
00469 /**
00470   * @brief  Read Temperature register of LM75: double temperature value.
00471   * @param  None
00472   * @retval LM75 measured temperature value.
00473   */
00474 uint16_t LM75_ReadTemp(void)
00475 {
00476   uint8_t LM75_BufferRX[2] ={0,0};
00477   uint16_t tmp = 0;
00478
00479   /* Test on BUSY Flag */
00480   LM75_Timeout = LM75_LONG_TIMEOUT;
00481   while (I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_BUSY))
00482   {
00483     if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
00484   }
00485
00486   /* Configure DMA Peripheral */
00487   LM75_DMA_Config(LM75_DMA_RX, (uint8_t*)LM75_BufferRX, 2);
00488
00489   /* Enable DMA NACK automatic generation */
00490   I2C_DMALastTransferCmd(LM75_I2C, ENABLE);
00491
00492   /* Enable the I2C peripheral */
00493   I2C_GenerateSTART(LM75_I2C, ENABLE);
00494
00495   /* Test on SB Flag */
00496   LM75_Timeout = LM75_FLAG_TIMEOUT;
00497   while (!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_SB))
00498   {
00499     if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
00500   }
00501
00502   /* Send device address for write */
00503   I2C_Send7bitAddress(LM75_I2C, LM75_ADDR, I2C_Direction_Transmitter);
00504
00505   /* Test on ADDR Flag */
00506   LM75_Timeout = LM75_FLAG_TIMEOUT;
00507   while (!I2C_CheckEvent(LM75_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED))
00508   {
00509     if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
00510   }
00511
00512   /* Send the device's internal address to write to */
00513   I2C_SendData(LM75_I2C, LM75_REG_TEMP);
00514
00515   /* Test on TXE FLag (data sent) */
00516   LM75_Timeout = LM75_FLAG_TIMEOUT;
00517   while ((!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_TXE)) && (!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_BTF)))
00518   {
00519     if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
00520   }
00521
00522   /* Send START condition a second time */
00523   I2C_GenerateSTART(LM75_I2C, ENABLE);
00524
00525   /* Test on SB Flag */
00526   LM75_Timeout = LM75_FLAG_TIMEOUT;
00527   while (!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_SB))
00528   {
00529     if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
00530   }
00531
00532   /* Send LM75 address for read */
00533   I2C_Send7bitAddress(LM75_I2C, LM75_ADDR, I2C_Direction_Receiver);
00534
00535   /* Test on ADDR Flag */
00536   LM75_Timeout = LM75_FLAG_TIMEOUT;
00537   while (!I2C_CheckEvent(LM75_I2C, I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED))
00538   {
00539     if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
00540   }
00541
00542   /* Enable I2C DMA request */
00543   I2C_DMACmd(LM75_I2C,ENABLE);
00544
00545   /* Enable DMA RX Channel */
00546   DMA_Cmd(LM75_DMA_RX_CHANNEL, ENABLE);
00547
00548   /* Wait until DMA Transfer Complete */
00549   LM75_Timeout = LM75_LONG_TIMEOUT;
00550   while (!DMA_GetFlagStatus(LM75_DMA_RX_TCFLAG))
00551   {
00552     if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
00553   }
00554
00555   /* Send STOP Condition */
00556   I2C_GenerateSTOP(LM75_I2C, ENABLE);
00557
00558   /* Disable DMA RX Channel */
00559   DMA_Cmd(LM75_DMA_RX_CHANNEL, DISABLE);
00560
00561   /* Disable I2C DMA request */
00562   I2C_DMACmd(LM75_I2C,DISABLE);
00563
00564   /* Clear DMA RX Transfer Complete Flag */
00565   DMA_ClearFlag(LM75_DMA_RX_TCFLAG);
00566
00567   /*!< Store LM75_I2C received data */
00568   tmp = (uint16_t)(LM75_BufferRX[0] << 8);
00569   tmp |= LM75_BufferRX[1];
00570
00571   /*!< Return Temperature value */
00572   return (uint16_t)(tmp >> 7);
00573 }
00574
00575 /**
00576   * @brief  Read the configuration register from the LM75.
00577   * @param  None
00578   * @retval LM75 configuration register value.
00579   */
00580 uint8_t LM75_ReadConfReg(void)
00581 {
00582   uint8_t LM75_BufferRX[2] ={0,0};
00583
00584   /* Test on BUSY Flag */
00585   LM75_Timeout = LM75_LONG_TIMEOUT;
00586   while (I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_BUSY))
00587   {
00588     if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
00589   }
00590
00591   /* Configure DMA Peripheral */
00592   LM75_DMA_Config(LM75_DMA_RX, (uint8_t*)LM75_BufferRX, 2);
00593
00594   /* Enable DMA NACK automatic generation */
00595   I2C_DMALastTransferCmd(LM75_I2C, ENABLE);
00596
00597   /* Enable the I2C peripheral */
00598   I2C_GenerateSTART(LM75_I2C, ENABLE);
00599
00600   /* Test on SB Flag */
00601   LM75_Timeout = LM75_FLAG_TIMEOUT;
00602   while (!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_SB))
00603   {
00604     if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
00605   }
00606
00607   /* Send device address for write */
00608   I2C_Send7bitAddress(LM75_I2C, LM75_ADDR, I2C_Direction_Transmitter);
00609
00610   /* Test on ADDR Flag */
00611   LM75_Timeout = LM75_FLAG_TIMEOUT;
00612   while (!I2C_CheckEvent(LM75_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED))
00613   {
00614     if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
00615   }
00616
00617   /* Send the device's internal address to write to */
00618   I2C_SendData(LM75_I2C, LM75_REG_CONF);
00619
00620   /* Test on TXE FLag (data sent) */
00621   LM75_Timeout = LM75_FLAG_TIMEOUT;
00622   while ((!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_TXE)) && (!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_BTF)))
00623   {
00624     if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
00625   }
00626
00627   /* Send START condition a second time */
00628   I2C_GenerateSTART(LM75_I2C, ENABLE);
00629
00630   /* Test on SB Flag */
00631   LM75_Timeout = LM75_FLAG_TIMEOUT;
00632   while (!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_SB))
00633   {
00634     if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
00635   }
00636
00637   /* Send LM75 address for read */
00638   I2C_Send7bitAddress(LM75_I2C, LM75_ADDR, I2C_Direction_Receiver);
00639
00640   /* Test on ADDR Flag */
00641   LM75_Timeout = LM75_FLAG_TIMEOUT;
00642   while (!I2C_CheckEvent(LM75_I2C, I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED))
00643   {
00644     if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
00645   }
00646
00647   /* Enable I2C DMA request */
00648   I2C_DMACmd(LM75_I2C,ENABLE);
00649
00650   /* Enable DMA RX Channel */
00651   DMA_Cmd(LM75_DMA_RX_CHANNEL, ENABLE);
00652
00653   /* Wait until DMA Transfer Complete */
00654   LM75_Timeout = LM75_LONG_TIMEOUT;
00655   while (!DMA_GetFlagStatus(LM75_DMA_RX_TCFLAG))
00656   {
00657     if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
00658   }
00659
00660   /* Send STOP Condition */
00661   I2C_GenerateSTOP(LM75_I2C, ENABLE);
00662
00663   /* Disable DMA RX Channel */
00664   DMA_Cmd(LM75_DMA_RX_CHANNEL, DISABLE);
00665
00666   /* Disable I2C DMA request */
00667   I2C_DMACmd(LM75_I2C,DISABLE);
00668
00669   /* Clear DMA RX Transfer Complete Flag */
00670   DMA_ClearFlag(LM75_DMA_RX_TCFLAG);
00671
00672   /*!< Return Temperature value */
00673   return (uint8_t)LM75_BufferRX[0];
00674 }
00675
00676 /**
00677   * @brief  Write to the configuration register of the LM75.
00678   * @param  RegValue: sepecifies the value to be written to LM75 configuration
00679   *         register.
00680   * @retval None
00681   */
00682 uint8_t LM75_WriteConfReg(uint8_t RegValue)
00683 {
00684   uint8_t LM75_BufferTX = 0;
00685   LM75_BufferTX = (uint8_t)(RegValue);
00686
00687   /* Test on BUSY Flag */
00688   LM75_Timeout = LM75_LONG_TIMEOUT;
00689   while (I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_BUSY))
00690   {
00691     if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
00692   }
00693
00694   /* Configure DMA Peripheral */
00695   LM75_DMA_Config(LM75_DMA_TX, (uint8_t*)(&LM75_BufferTX), 1);
00696
00697   /* Enable the I2C peripheral */
00698   I2C_GenerateSTART(LM75_I2C, ENABLE);
00699
00700   /* Test on SB Flag */
00701   LM75_Timeout = LM75_FLAG_TIMEOUT;
00702   while (I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_SB) == RESET)
00703   {
00704     if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
00705   }
00706
00707   /* Transmit the slave address and enable writing operation */
00708   I2C_Send7bitAddress(LM75_I2C, LM75_ADDR, I2C_Direction_Transmitter);
00709
00710   /* Test on ADDR Flag */
00711   LM75_Timeout = LM75_FLAG_TIMEOUT;
00712   while (!I2C_CheckEvent(LM75_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED))
00713   {
00714     if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
00715   }
00716
00717   /* Transmit the first address for r/w operations */
00718   I2C_SendData(LM75_I2C, LM75_REG_CONF);
00719
00720   /* Test on TXE FLag (data sent) */
00721   LM75_Timeout = LM75_FLAG_TIMEOUT;
00722   while ((!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_TXE)) && (!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_BTF)))
00723   {
00724     if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
00725   }
00726
00727   /* Enable I2C DMA request */
00728   I2C_DMACmd(LM75_I2C,ENABLE);
00729
00730   /* Enable DMA TX Channel */
00731   DMA_Cmd(LM75_DMA_TX_CHANNEL, ENABLE);
00732
00733   /* Wait until DMA Transfer Complete */
00734   LM75_Timeout = LM75_LONG_TIMEOUT;
00735   while (!DMA_GetFlagStatus(LM75_DMA_TX_TCFLAG))
00736   {
00737     if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
00738   }
00739
00740   /* Wait until BTF Flag is set before generating STOP */
00741   LM75_Timeout = LM75_LONG_TIMEOUT;
00742   while ((!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_BTF)))
00743   {
00744     if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
00745   }
00746
00747   /* Send STOP Condition */
00748   I2C_GenerateSTOP(LM75_I2C, ENABLE);
00749
00750   /* Disable DMA TX Channel */
00751   DMA_Cmd(LM75_DMA_TX_CHANNEL, DISABLE);
00752
00753   /* Disable I2C DMA request */
00754   I2C_DMACmd(LM75_I2C,DISABLE);
00755
00756   /* Clear DMA TX Transfer Complete Flag */
00757   DMA_ClearFlag(LM75_DMA_TX_TCFLAG);
00758
00759   return LM75_OK;
00760
00761 }
00762
00763 /**
00764   * @brief  Enables or disables the LM75.
00765   * @param  NewState: specifies the LM75 new status. This parameter can be ENABLE
00766   *         or DISABLE.
00767   * @retval None
00768   */
00769 uint8_t LM75_ShutDown(FunctionalState NewState)
00770 {
00771   uint8_t LM75_BufferRX[2] ={0,0};
00772   uint8_t LM75_BufferTX = 0;
00773   __IO uint8_t RegValue = 0;
00774
00775   /* Test on BUSY Flag */
00776   LM75_Timeout = LM75_LONG_TIMEOUT;
00777   while (I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_BUSY))
00778   {
00779     if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
00780   }
00781
00782   /* Configure DMA Peripheral */
00783   LM75_DMA_Config(LM75_DMA_RX, (uint8_t*)LM75_BufferRX, 2);
00784
00785   /* Enable DMA NACK automatic generation */
00786   I2C_DMALastTransferCmd(LM75_I2C, ENABLE);
00787
00788   /* Enable the I2C peripheral */
00789   I2C_GenerateSTART(LM75_I2C, ENABLE);
00790
00791   /* Test on SB Flag */
00792   LM75_Timeout = LM75_FLAG_TIMEOUT;
00793   while (!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_SB))
00794   {
00795     if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
00796   }
00797
00798   /* Send device address for write */
00799   I2C_Send7bitAddress(LM75_I2C, LM75_ADDR, I2C_Direction_Transmitter);
00800
00801   /* Test on ADDR Flag */
00802   LM75_Timeout = LM75_FLAG_TIMEOUT;
00803   while (!I2C_CheckEvent(LM75_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED))
00804   {
00805     if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
00806   }
00807
00808   /* Send the device's internal address to write to */
00809   I2C_SendData(LM75_I2C, LM75_REG_CONF);
00810
00811   /* Test on TXE FLag (data sent) */
00812   LM75_Timeout = LM75_FLAG_TIMEOUT;
00813   while ((!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_TXE)) && (!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_BTF)))
00814   {
00815     if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
00816   }
00817
00818   /* Send START condition a second time */
00819   I2C_GenerateSTART(LM75_I2C, ENABLE);
00820
00821   /* Test on SB Flag */
00822   LM75_Timeout = LM75_FLAG_TIMEOUT;
00823   while (!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_SB))
00824   {
00825     if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
00826   }
00827
00828   /* Send LM75 address for read */
00829   I2C_Send7bitAddress(LM75_I2C, LM75_ADDR, I2C_Direction_Receiver);
00830
00831   /* Test on ADDR Flag */
00832   LM75_Timeout = LM75_FLAG_TIMEOUT;
00833   while (!I2C_CheckEvent(LM75_I2C, I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED))
00834   {
00835     if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
00836   }
00837
00838   /* Enable I2C DMA request */
00839   I2C_DMACmd(LM75_I2C,ENABLE);
00840
00841   /* Enable DMA RX Channel */
00842   DMA_Cmd(LM75_DMA_RX_CHANNEL, ENABLE);
00843
00844   /* Wait until DMA Transfer Complete */
00845   LM75_Timeout = LM75_LONG_TIMEOUT;
00846   while (!DMA_GetFlagStatus(LM75_DMA_RX_TCFLAG))
00847   {
00848     if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
00849   }
00850
00851   /* Send STOP Condition */
00852   I2C_GenerateSTOP(LM75_I2C, ENABLE);
00853
00854   /* Disable DMA RX Channel */
00855   DMA_Cmd(LM75_DMA_RX_CHANNEL, DISABLE);
00856
00857   /* Disable I2C DMA request */
00858   I2C_DMACmd(LM75_I2C,DISABLE);
00859
00860   /* Clear DMA RX Transfer Complete Flag */
00861   DMA_ClearFlag(LM75_DMA_RX_TCFLAG);
00862
00863   /*!< Get received data */
00864   RegValue = (uint8_t)LM75_BufferRX[0];
00865
00866   /*---------------------------- Transmission Phase ---------------------------*/
00867
00868   /*!< Enable or disable SD bit */
00869   if (NewState != DISABLE)
00870   {
00871     /*!< Enable LM75 */
00872     LM75_BufferTX = RegValue & LM75_SD_RESET;
00873   }
00874   else
00875   {
00876     /*!< Disable LM75 */
00877     LM75_BufferTX = RegValue | LM75_SD_SET;
00878   }
00879
00880   /* Test on BUSY Flag */
00881   LM75_Timeout = LM75_LONG_TIMEOUT;
00882   while (!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_BUSY))
00883   {
00884     if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
00885   }
00886
00887   /* Configure DMA Peripheral */
00888   LM75_DMA_Config(LM75_DMA_TX, (uint8_t*)(&LM75_BufferTX), 1);
00889
00890   /* Enable the I2C peripheral */
00891   I2C_GenerateSTART(LM75_I2C, ENABLE);
00892
00893   /* Test on SB Flag */
00894   LM75_Timeout = LM75_FLAG_TIMEOUT;
00895   while (I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_SB) == RESET)
00896   {
00897     if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
00898   }
00899
00900   /* Transmit the slave address and enable writing operation */
00901   I2C_Send7bitAddress(LM75_I2C, LM75_ADDR, I2C_Direction_Transmitter);
00902
00903   /* Test on ADDR Flag */
00904   LM75_Timeout = LM75_FLAG_TIMEOUT;
00905   while (!I2C_CheckEvent(LM75_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED))
00906   {
00907     if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
00908   }
00909
00910   /* Transmit the first address for r/w operations */
00911   I2C_SendData(LM75_I2C, LM75_REG_CONF);
00912
00913   /* Test on TXE FLag (data sent) */
00914   LM75_Timeout = LM75_FLAG_TIMEOUT;
00915   while ((!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_TXE)) && (!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_BTF)))
00916   {
00917     if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
00918   }
00919
00920   /* Enable I2C DMA request */
00921   I2C_DMACmd(LM75_I2C,ENABLE);
00922
00923   /* Enable DMA TX Channel */
00924   DMA_Cmd(LM75_DMA_TX_CHANNEL, ENABLE);
00925
00926   /* Wait until DMA Transfer Complete */
00927   LM75_Timeout = LM75_LONG_TIMEOUT;
00928   while (!DMA_GetFlagStatus(LM75_DMA_TX_TCFLAG))
00929   {
00930     if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
00931   }
00932
00933   /* Wait until BTF Flag is set before generating STOP */
00934   LM75_Timeout = LM75_LONG_TIMEOUT;
00935   while ((!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_BTF)))
00936   {
00937     if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
00938   }
00939
00940   /* Send STOP Condition */
00941   I2C_GenerateSTOP(LM75_I2C, ENABLE);
00942
00943   /* Disable DMA TX Channel */
00944   DMA_Cmd(LM75_DMA_TX_CHANNEL, DISABLE);
00945
00946   /* Disable I2C DMA request */
00947   I2C_DMACmd(LM75_I2C,DISABLE);
00948
00949   /* Clear DMA TX Transfer Complete Flag */
00950   DMA_ClearFlag(LM75_DMA_TX_TCFLAG);
00951
00952   return LM75_OK;
00953 }
00954
00955 /**
00956   * @}
00957   */
00958
00959
00960 /**
00961   * @}
00962   */
00963
00964
00965 /**
00966   * @}
00967   */
00968
00969 /**
00970   * @}
00971   */
00972
00973 /**
00974   * @}
00975   */
00976
00977 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32_eval_i2c_tsensor.h Source File

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stm32_eval_i2c_tsensor.h

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32_eval_i2c_tsensor.h
00004   * @author  MCD Application Team
00005   * @version V4.5.0
00006   * @date    07-March-2011
00007   * @brief   This file contains all the functions prototypes for the
00008   *          stm32_eval_i2c_tsensor firmware driver.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00013   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00014   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00015   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00016   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00017   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00018   *
00019   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00020   ******************************************************************************
00021   */
00022
00023 /* Define to prevent recursive inclusion -------------------------------------*/
00024 #ifndef __STM32_EVAL_I2C_TSENSOR_H
00025 #define __STM32_EVAL_I2C_TSENSOR_H
00026
00027 #ifdef __cplusplus
00028  extern "C" {
00029 #endif
00030
00031 /* Includes ------------------------------------------------------------------*/
00032 #include "stm32_eval.h"
00033
00034 /** @addtogroup Utilities
00035   * @{
00036   */
00037
00038 /** @addtogroup STM32_EVAL
00039   * @{
00040   */
00041
00042 /** @addtogroup Common
00043   * @{
00044   */
00045
00046 /** @addtogroup STM32_EVAL_I2C_TSENSOR
00047   * @{
00048   */
00049
00050 /** @defgroup STM32_EVAL_I2C_TSENSOR_Exported_Types
00051   * @{
00052   */
00053
00054  /**
00055   * @brief  IOE DMA Direction
00056   */
00057 typedef enum
00058 {
00059   LM75_DMA_TX = 0,
00060   LM75_DMA_RX = 1
00061 }LM75_DMADirection_TypeDef;
00062
00063 /**
00064   * @brief  TSENSOR Status
00065   */
00066 typedef enum
00067 {
00068   LM75_OK = 0,
00069   LM75_FAIL
00070 }LM75_Status_TypDef;
00071
00072 /**
00073   * @}
00074   */
00075
00076 /** @defgroup STM32_EVAL_I2C_TSENSOR_Exported_Constants
00077   * @{
00078   */
00079
00080 /* Uncomment the following line to use Timeout_User_Callback LM75_TimeoutUserCallback().
00081    If This Callback is enabled, it should be implemented by user in main function .
00082    LM75_TimeoutUserCallback() function is called whenever a timeout condition
00083    occure during communication (waiting on an event that doesn't occur, bus
00084    errors, busy devices ...). */
00085 /* #define USE_TIMEOUT_USER_CALLBACK */
00086
00087 /* Maximum Timeout values for flags and events waiting loops. These timeouts are
00088    not based on accurate values, they just guarantee that the application will
00089    not remain stuck if the I2C communication is corrupted.
00090    You may modify these timeout values depending on CPU frequency and application
00091    conditions (interrupts routines ...). */
00092 #define LM75_FLAG_TIMEOUT         ((uint32_t)0x1000)
00093 #define LM75_LONG_TIMEOUT         ((uint32_t)(10 * LM75_FLAG_TIMEOUT))
00094
00095
00096 /**
00097   * @brief  Block Size
00098   */
00099 #define LM75_REG_TEMP       0x00  /*!< Temperature Register of LM75 */
00100 #define LM75_REG_CONF       0x01  /*!< Configuration Register of LM75 */
00101 #define LM75_REG_THYS       0x02  /*!< Temperature Register of LM75 */
00102 #define LM75_REG_TOS        0x03  /*!< Over-temp Shutdown threshold Register of LM75 */
00103 #define I2C_TIMEOUT         ((uint32_t)0x3FFFF) /*!< I2C Time out */
00104 #define LM75_ADDR           0x90   /*!< LM75 address */
00105 #define LM75_I2C_SPEED      100000 /*!< I2C Speed */
00106
00107
00108
00109 /**
00110   * @}
00111   */
00112
00113 /** @defgroup STM32_EVAL_I2C_TSENSOR_Exported_Macros
00114   * @{
00115   */
00116 /**
00117   * @}
00118   */
00119
00120 /** @defgroup STM32_EVAL_I2C_TSENSOR_Exported_Functions
00121   * @{
00122   */
00123 void LM75_DeInit(void);
00124 void LM75_Init(void);
00125 ErrorStatus LM75_GetStatus(void);
00126 uint16_t LM75_ReadTemp(void);
00127 uint16_t LM75_ReadReg(uint8_t RegName);
00128 uint8_t LM75_WriteReg(uint8_t RegName, uint16_t RegValue);
00129 uint8_t LM75_ReadConfReg(void);
00130 uint8_t LM75_WriteConfReg(uint8_t RegValue);
00131 uint8_t LM75_ShutDown(FunctionalState NewState);
00132
00133 /**
00134   * @brief  Timeout user callback function. This function is called when a timeout
00135   *         condition occurs during communication with IO Expander. Only protoype
00136   *         of this function is decalred in IO Expander driver. Its implementation
00137   *         may be done into user application. This function may typically stop
00138   *         current operations and reset the I2C peripheral and IO Expander.
00139   *         To enable this function use uncomment the define USE_TIMEOUT_USER_CALLBACK
00140   *         at the top of this file.
00141   */
00142 #ifdef USE_TIMEOUT_USER_CALLBACK
00143  uint8_t LM75_TIMEOUT_UserCallback(void);
00144 #else
00145  #define LM75_TIMEOUT_UserCallback()  LM75_FAIL
00146 #endif /* USE_TIMEOUT_USER_CALLBACK */
00147
00148 #ifdef __cplusplus
00149 }
00150 #endif
00151
00152 #endif /* __STM32_EVAL_I2C_TSENSOR_H */
00153 /**
00154   * @}
00155   */
00156
00157 /**
00158   * @}
00159   */
00160
00161 /**
00162   * @}
00163   */
00164
00165 /**
00166   * @}
00167   */
00168
00169 /**
00170   * @}
00171   */
00172
00173 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32_eval_sdio_sd.c Source File

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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • Common

stm32_eval_sdio_sd.c

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32_eval_sdio_sd.c
00004   * @author  MCD Application Team
00005   * @version V4.5.0
00006   * @date    07-March-2011
00007   * @brief   This file provides a set of functions needed to manage the SDIO SD
00008   *          Card memory mounted on STM32xx-EVAL board (refer to stm32_eval.h
00009   *          to know about the boards supporting this memory).
00010   *
00011   *
00012   *  @verbatim
00013   *
00014   *          ===================================================================
00015   *                                   How to use this driver
00016   *          ===================================================================
00017   *          It implements a high level communication layer for read and write
00018   *          from/to this memory. The needed STM32 hardware resources (SDIO and
00019   *          GPIO) are defined in stm32xx_eval.h file, and the initialization is
00020   *          performed in SD_LowLevel_Init() function declared in stm32xx_eval.c
00021   *          file.
00022   *          You can easily tailor this driver to any other development board,
00023   *          by just adapting the defines for hardware resources and
00024   *          SD_LowLevel_Init() function.
00025   *
00026   *          A - SD Card Initialization and configuration
00027   *          ============================================
00028   *            - To initialize the SD Card, use the SD_Init() function.  It
00029   *              Initializes the SD Card and put it into StandBy State (Ready
00030   *              for data transfer). This function provide the following operations:
00031   *
00032   *              1 - Apply the SD Card initialization process at 400KHz and check
00033   *                  the SD Card type (Standard Capacity or High Capacity). You
00034   *                  can change or adapt this frequency by adjusting the
00035   *                  "SDIO_INIT_CLK_DIV" define inside the stm32xx_eval.h file.
00036   *                  The SD Card frequency (SDIO_CK) is computed as follows:
00037   *
00038   *                     +---------------------------------------------+
00039   *                     | SDIO_CK = SDIOCLK / (SDIO_INIT_CLK_DIV + 2) |
00040   *                     +---------------------------------------------+
00041   *
00042   *                  In initialization mode and according to the SD Card standard,
00043   *                  make sure that the SDIO_CK frequency don't exceed 400KHz.
00044   *
00045   *              2 - Get the SD CID and CSD data. All these information are
00046   *                  managed by the SDCardInfo structure. This structure provide
00047   *                  also ready computed SD Card capacity and Block size.
00048   *
00049   *              3 - Configure the SD Card Data transfer frequency. By Default,
00050   *                  the card transfer frequency is set to 24MHz. You can change
00051   *                  or adapt this frequency by adjusting the "SDIO_TRANSFER_CLK_DIV"
00052   *                  define inside the stm32xx_eval.h file.
00053   *                  The SD Card frequency (SDIO_CK) is computed as follows:
00054   *
00055   *                     +---------------------------------------------+
00056   *                     | SDIO_CK = SDIOCLK / (SDIO_INIT_CLK_DIV + 2) |
00057   *                     +---------------------------------------------+
00058   *
00059   *                  In transfer mode and according to the SD Card standard,
00060   *                  make sure that the SDIO_CK frequency don't exceed 25MHz
00061   *                  and 50MHz in High-speed mode switch.
00062   *                  To be able to use a frequency higher than 24MHz, you should
00063   *                  use the SDIO peripheral in bypass mode. Refer to the
00064   *                  corresponding reference manual for more details.
00065   *
00066   *              4 -  Select the corresponding SD Card according to the address
00067   *                   read with the step 2.
00068   *
00069   *              5 -  Configure the SD Card in wide bus mode: 4-bits data.
00070   *
00071   *          B - SD Card Read operation
00072   *          ==========================
00073   *           - You can read SD card by using two function: SD_ReadBlock() and
00074   *             SD_ReadMultiBlocks() functions. These functions support only
00075   *             512-byte block length.
00076   *           - The SD_ReadBlock() function read only one block (512-byte). This
00077   *             function can transfer the data using DMA controller or using
00078   *             polling mode. To select between DMA or polling mode refer to
00079   *             "SD_DMA_MODE" or "SD_POLLING_MODE" inside the stm32_eval_sdio_sd.h
00080   *             file and uncomment the corresponding line. By default the SD DMA
00081   *             mode is selected
00082   *           - The SD_ReadMultiBlocks() function read only mutli blocks (multiple
00083   *             of 512-byte).
00084   *           - Any read operation should be followed by two functions to check
00085   *             if the DMA Controller and SD Card status.
00086   *              - SD_ReadWaitOperation(): this function insure that the DMA
00087   *                controller has finished all data transfer.
00088   *              - SD_GetStatus(): to check that the SD Card has finished the
00089   *                data transfer and it is ready for data.
00090   *
00091   *           - The DMA transfer is finished by the SDIO Data End interrupt. User
00092   *             has to call the SD_ProcessIRQ() function inside the SDIO_IRQHandler().
00093   *             Don't forget to enable the SDIO_IRQn interrupt using the NVIC controller.
00094   *
00095   *          C - SD Card Write operation
00096   *          ===========================
00097   *           - You can write SD card by using two function: SD_WriteBlock() and
00098   *             SD_WriteMultiBlocks() functions. These functions support only
00099   *             512-byte block length.
00100   *           - The SD_WriteBlock() function write only one block (512-byte). This
00101   *             function can transfer the data using DMA controller or using
00102   *             polling mode. To select between DMA or polling mode refer to
00103   *             "SD_DMA_MODE" or "SD_POLLING_MODE" inside the stm32_eval_sdio_sd.h
00104   *             file and uncomment the corresponding line. By default the SD DMA
00105   *             mode is selected
00106   *           - The SD_WriteMultiBlocks() function write only mutli blocks (multiple
00107   *             of 512-byte).
00108   *           - Any write operation should be followed by two functions to check
00109   *             if the DMA Controller and SD Card status.
00110   *              - SD_ReadWaitOperation(): this function insure that the DMA
00111   *                controller has finished all data transfer.
00112   *              - SD_GetStatus(): to check that the SD Card has finished the
00113   *                data transfer and it is ready for data.
00114   *
00115   *           - The DMA transfer is finished by the SDIO Data End interrupt. User
00116   *             has to call the SD_ProcessIRQ() function inside the SDIO_IRQHandler().
00117   *             Don't forget to enable the SDIO_IRQn interrupt using the NVIC controller.
00118
00119   *
00120   *          D - SD card status
00121   *          ==================
00122   *           - At any time, you can check the SD Card status and get the SD card
00123   *             state by using the SD_GetStatus() function. This function checks
00124   *             first if the SD card is still connected and then get the internal
00125   *             SD Card transfer state.
00126   *           - You can also get the SD card SD Status register by using the
00127   *             SD_SendSDStatus() function.
00128   *
00129   *          E - Programming Model
00130   *          =====================
00131   *             Status = SD_Init(); // Initialization Step as described in section A
00132   *
00133   *             // SDIO Interrupt ENABLE
00134   *             NVIC_InitStructure.NVIC_IRQChannel = SDIO_IRQn;
00135   *             NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
00136   *             NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
00137   *             NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
00138   *             NVIC_Init(&NVIC_InitStructure);
00139   *
00140   *             // Write operation as described in Section C
00141   *             Status = SD_WriteBlock(buffer, address, 512);
00142   *             Status = SD_WaitWriteOperation();
00143   *             while(SD_GetStatus() != SD_TRANSFER_OK);
00144   *
00145   *             Status = SD_WriteMultiBlocks(buffer, address, 512, NUMBEROFBLOCKS);
00146   *             Status = SD_WaitWriteOperation();
00147   *             while(SD_GetStatus() != SD_TRANSFER_OK);
00148   *
00149   *             // Read operation as described in Section B
00150   *             Status = SD_ReadBlock(buffer, address, 512);
00151   *             Status = SD_WaitReadOperation();
00152   *             while(SD_GetStatus() != SD_TRANSFER_OK);
00153   *
00154   *             Status = SD_ReadMultiBlocks(buffer, address, 512, NUMBEROFBLOCKS);
00155   *             Status = SD_WaitReadOperation();
00156   *             while(SD_GetStatus() != SD_TRANSFER_OK);
00157   *
00158   *
00159   *          STM32 SDIO Pin assignment
00160   *          =========================
00161   *          +-----------------------------------------------------------+
00162   *          |                     Pin assignment                        |
00163   *          +-----------------------------+---------------+-------------+
00164   *          |  STM32 SDIO Pins            |     SD        |    Pin      |
00165   *          +-----------------------------+---------------+-------------+
00166   *          |      SDIO D2                |   D2          |    1        |
00167   *          |      SDIO D3                |   D3          |    2        |
00168   *          |      SDIO CMD               |   CMD         |    3        |
00169   *          |                             |   VCC         |    4 (3.3 V)|
00170   *          |      SDIO CLK               |   CLK         |    5        |
00171   *          |                             |   GND         |    6 (0 V)  |
00172   *          |      SDIO D0                |   D0          |    7        |
00173   *          |      SDIO D1                |   D1          |    8        |
00174   *          +-----------------------------+---------------+-------------+
00175   *
00176   *  @endverbatim
00177   *
00178   ******************************************************************************
00179   * @attention
00180   *
00181   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00182   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00183   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00184   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00185   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00186   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00187   *
00188   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00189   ******************************************************************************
00190   */
00191
00192 /* Includes ------------------------------------------------------------------*/
00193 #include "stm32_eval_sdio_sd.h"
00194
00195 /** @addtogroup Utilities
00196   * @{
00197   */
00198
00199 /** @addtogroup STM32_EVAL
00200   * @{
00201   */
00202
00203 /** @addtogroup Common
00204   * @{
00205   */
00206
00207 /** @addtogroup STM32_EVAL_SDIO_SD
00208   * @brief      This file provides all the SD Card driver firmware functions.
00209   * @{
00210   */
00211
00212 /** @defgroup STM32_EVAL_SDIO_SD_Private_Types
00213   * @{
00214   */
00215 /**
00216   * @}
00217   */
00218
00219
00220 /** @defgroup STM32_EVAL_SDIO_SD_Private_Defines
00221   * @{
00222   */
00223 /**
00224   * @brief  SDIO Static flags, TimeOut, FIFO Address
00225   */
00226 #define NULL 0
00227 #define SDIO_STATIC_FLAGS               ((uint32_t)0x000005FF)
00228 #define SDIO_CMD0TIMEOUT                ((uint32_t)0x00010000)
00229
00230 /**
00231   * @brief  Mask for errors Card Status R1 (OCR Register)
00232   */
00233 #define SD_OCR_ADDR_OUT_OF_RANGE        ((uint32_t)0x80000000)
00234 #define SD_OCR_ADDR_MISALIGNED          ((uint32_t)0x40000000)
00235 #define SD_OCR_BLOCK_LEN_ERR            ((uint32_t)0x20000000)
00236 #define SD_OCR_ERASE_SEQ_ERR            ((uint32_t)0x10000000)
00237 #define SD_OCR_BAD_ERASE_PARAM          ((uint32_t)0x08000000)
00238 #define SD_OCR_WRITE_PROT_VIOLATION     ((uint32_t)0x04000000)
00239 #define SD_OCR_LOCK_UNLOCK_FAILED       ((uint32_t)0x01000000)
00240 #define SD_OCR_COM_CRC_FAILED           ((uint32_t)0x00800000)
00241 #define SD_OCR_ILLEGAL_CMD              ((uint32_t)0x00400000)
00242 #define SD_OCR_CARD_ECC_FAILED          ((uint32_t)0x00200000)
00243 #define SD_OCR_CC_ERROR                 ((uint32_t)0x00100000)
00244 #define SD_OCR_GENERAL_UNKNOWN_ERROR    ((uint32_t)0x00080000)
00245 #define SD_OCR_STREAM_READ_UNDERRUN     ((uint32_t)0x00040000)
00246 #define SD_OCR_STREAM_WRITE_OVERRUN     ((uint32_t)0x00020000)
00247 #define SD_OCR_CID_CSD_OVERWRIETE       ((uint32_t)0x00010000)
00248 #define SD_OCR_WP_ERASE_SKIP            ((uint32_t)0x00008000)
00249 #define SD_OCR_CARD_ECC_DISABLED        ((uint32_t)0x00004000)
00250 #define SD_OCR_ERASE_RESET              ((uint32_t)0x00002000)
00251 #define SD_OCR_AKE_SEQ_ERROR            ((uint32_t)0x00000008)
00252 #define SD_OCR_ERRORBITS                ((uint32_t)0xFDFFE008)
00253
00254 /**
00255   * @brief  Masks for R6 Response
00256   */
00257 #define SD_R6_GENERAL_UNKNOWN_ERROR     ((uint32_t)0x00002000)
00258 #define SD_R6_ILLEGAL_CMD               ((uint32_t)0x00004000)
00259 #define SD_R6_COM_CRC_FAILED            ((uint32_t)0x00008000)
00260
00261 #define SD_VOLTAGE_WINDOW_SD            ((uint32_t)0x80100000)
00262 #define SD_HIGH_CAPACITY                ((uint32_t)0x40000000)
00263 #define SD_STD_CAPACITY                 ((uint32_t)0x00000000)
00264 #define SD_CHECK_PATTERN                ((uint32_t)0x000001AA)
00265
00266 #define SD_MAX_VOLT_TRIAL               ((uint32_t)0x0000FFFF)
00267 #define SD_ALLZERO                      ((uint32_t)0x00000000)
00268
00269 #define SD_WIDE_BUS_SUPPORT             ((uint32_t)0x00040000)
00270 #define SD_SINGLE_BUS_SUPPORT           ((uint32_t)0x00010000)
00271 #define SD_CARD_LOCKED                  ((uint32_t)0x02000000)
00272
00273 #define SD_DATATIMEOUT                  ((uint32_t)0xFFFFFFFF)
00274 #define SD_0TO7BITS                     ((uint32_t)0x000000FF)
00275 #define SD_8TO15BITS                    ((uint32_t)0x0000FF00)
00276 #define SD_16TO23BITS                   ((uint32_t)0x00FF0000)
00277 #define SD_24TO31BITS                   ((uint32_t)0xFF000000)
00278 #define SD_MAX_DATA_LENGTH              ((uint32_t)0x01FFFFFF)
00279
00280 #define SD_HALFFIFO                     ((uint32_t)0x00000008)
00281 #define SD_HALFFIFOBYTES                ((uint32_t)0x00000020)
00282
00283 /**
00284   * @brief  Command Class Supported
00285   */
00286 #define SD_CCCC_LOCK_UNLOCK             ((uint32_t)0x00000080)
00287 #define SD_CCCC_WRITE_PROT              ((uint32_t)0x00000040)
00288 #define SD_CCCC_ERASE                   ((uint32_t)0x00000020)
00289
00290 /**
00291   * @brief  Following commands are SD Card Specific commands.
00292   *         SDIO_APP_CMD should be sent before sending these commands.
00293   */
00294 #define SDIO_SEND_IF_COND               ((uint32_t)0x00000008)
00295
00296 /**
00297   * @}
00298   */
00299
00300
00301 /** @defgroup STM32_EVAL_SDIO_SD_Private_Macros
00302   * @{
00303   */
00304 /**
00305   * @}
00306   */
00307
00308
00309 /** @defgroup STM32_EVAL_SDIO_SD_Private_Variables
00310   * @{
00311   */
00312 static uint32_t CardType =  SDIO_STD_CAPACITY_SD_CARD_V1_1;
00313 static uint32_t CSD_Tab[4], CID_Tab[4], RCA = 0;
00314 static uint8_t SDSTATUS_Tab[16];
00315 __IO uint32_t StopCondition = 0;
00316 __IO SD_Error TransferError = SD_OK;
00317 __IO uint32_t TransferEnd = 0;
00318 SD_CardInfo SDCardInfo;
00319
00320 SDIO_InitTypeDef SDIO_InitStructure;
00321 SDIO_CmdInitTypeDef SDIO_CmdInitStructure;
00322 SDIO_DataInitTypeDef SDIO_DataInitStructure;
00323 /**
00324   * @}
00325   */
00326
00327
00328 /** @defgroup STM32_EVAL_SDIO_SD_Private_Function_Prototypes
00329   * @{
00330   */
00331 static SD_Error CmdError(void);
00332 static SD_Error CmdResp1Error(uint8_t cmd);
00333 static SD_Error CmdResp7Error(void);
00334 static SD_Error CmdResp3Error(void);
00335 static SD_Error CmdResp2Error(void);
00336 static SD_Error CmdResp6Error(uint8_t cmd, uint16_t *prca);
00337 static SD_Error SDEnWideBus(FunctionalState NewState);
00338 static SD_Error IsCardProgramming(uint8_t *pstatus);
00339 static SD_Error FindSCR(uint16_t rca, uint32_t *pscr);
00340 uint8_t convert_from_bytes_to_power_of_two(uint16_t NumberOfBytes);
00341
00342 /**
00343   * @}
00344   */
00345
00346
00347 /** @defgroup STM32_EVAL_SDIO_SD_Private_Functions
00348   * @{
00349   */
00350
00351 /**
00352   * @brief  DeInitializes the SDIO interface.
00353   * @param  None
00354   * @retval None
00355   */
00356 void SD_DeInit(void)
00357 {
00358   SD_LowLevel_DeInit();
00359 }
00360
00361 /**
00362   * @brief  Initializes the SD Card and put it into StandBy State (Ready for data
00363   *         transfer).
00364   * @param  None
00365   * @retval SD_Error: SD Card Error code.
00366   */
00367 SD_Error SD_Init(void)
00368 {
00369   SD_Error errorstatus = SD_OK;
00370
00371   /* SDIO Peripheral Low Level Init */
00372   SD_LowLevel_Init();
00373
00374   SDIO_DeInit();
00375
00376   errorstatus = SD_PowerON();
00377
00378   if (errorstatus != SD_OK)
00379   {
00380     /*!< CMD Response TimeOut (wait for CMDSENT flag) */
00381     return(errorstatus);
00382   }
00383
00384   errorstatus = SD_InitializeCards();
00385
00386   if (errorstatus != SD_OK)
00387   {
00388     /*!< CMD Response TimeOut (wait for CMDSENT flag) */
00389     return(errorstatus);
00390   }
00391
00392   /*!< Configure the SDIO peripheral */
00393   /*!< SDIOCLK = HCLK, SDIO_CK = HCLK/(2 + SDIO_TRANSFER_CLK_DIV) */
00394   /*!< on STM32F2xx devices, SDIOCLK is fixed to 48MHz */
00395   SDIO_InitStructure.SDIO_ClockDiv = SDIO_TRANSFER_CLK_DIV;
00396   SDIO_InitStructure.SDIO_ClockEdge = SDIO_ClockEdge_Rising;
00397   SDIO_InitStructure.SDIO_ClockBypass = SDIO_ClockBypass_Disable;
00398   SDIO_InitStructure.SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable;
00399   SDIO_InitStructure.SDIO_BusWide = SDIO_BusWide_1b;
00400   SDIO_InitStructure.SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable;
00401   SDIO_Init(&SDIO_InitStructure);
00402
00403   if (errorstatus == SD_OK)
00404   {
00405     /*----------------- Read CSD/CID MSD registers ------------------*/
00406     errorstatus = SD_GetCardInfo(&SDCardInfo);
00407   }
00408
00409   if (errorstatus == SD_OK)
00410   {
00411     /*----------------- Select Card --------------------------------*/
00412     errorstatus = SD_SelectDeselect((uint32_t) (SDCardInfo.RCA << 16));
00413   }
00414
00415   if (errorstatus == SD_OK)
00416   {
00417     errorstatus = SD_EnableWideBusOperation(SDIO_BusWide_4b);
00418   }
00419
00420   return(errorstatus);
00421 }
00422
00423 /**
00424   * @brief  Gets the cuurent sd card data transfer status.
00425   * @param  None
00426   * @retval SDTransferState: Data Transfer state.
00427   *   This value can be:
00428   *        - SD_TRANSFER_OK: No data transfer is acting
00429   *        - SD_TRANSFER_BUSY: Data transfer is acting
00430   */
00431 SDTransferState SD_GetStatus(void)
00432 {
00433   SDCardState cardstate =  SD_CARD_TRANSFER;
00434
00435   cardstate = SD_GetState();
00436
00437   if (cardstate == SD_CARD_TRANSFER)
00438   {
00439     return(SD_TRANSFER_OK);
00440   }
00441   else if(cardstate == SD_CARD_ERROR)
00442   {
00443     return (SD_TRANSFER_ERROR);
00444   }
00445   else
00446   {
00447     return(SD_TRANSFER_BUSY);
00448   }
00449 }
00450
00451 /**
00452   * @brief  Returns the current card's state.
00453   * @param  None
00454   * @retval SDCardState: SD Card Error or SD Card Current State.
00455   */
00456 SDCardState SD_GetState(void)
00457 {
00458   uint32_t resp1 = 0;
00459
00460   if(SD_Detect()== SD_PRESENT)
00461   {
00462     if (SD_SendStatus(&resp1) != SD_OK)
00463     {
00464       return SD_CARD_ERROR;
00465     }
00466     else
00467     {
00468       return (SDCardState)((resp1 >> 9) & 0x0F);
00469     }
00470   }
00471   else
00472   {
00473     return SD_CARD_ERROR;
00474   }
00475 }
00476
00477 /**
00478  * @brief  Detect if SD card is correctly plugged in the memory slot.
00479  * @param  None
00480  * @retval Return if SD is detected or not
00481  */
00482 uint8_t SD_Detect(void)
00483 {
00484   __IO uint8_t status = SD_PRESENT;
00485
00486   /*!< Check GPIO to detect SD */
00487   if (GPIO_ReadInputDataBit(SD_DETECT_GPIO_PORT, SD_DETECT_PIN) != Bit_RESET)
00488   {
00489     status = SD_NOT_PRESENT;
00490   }
00491   return status;
00492 }
00493
00494 /**
00495   * @brief  Enquires cards about their operating voltage and configures
00496   *   clock controls.
00497   * @param  None
00498   * @retval SD_Error: SD Card Error code.
00499   */
00500 SD_Error SD_PowerON(void)
00501 {
00502   SD_Error errorstatus = SD_OK;
00503   uint32_t response = 0, count = 0, validvoltage = 0;
00504   uint32_t SDType = SD_STD_CAPACITY;
00505
00506   /*!< Power ON Sequence -----------------------------------------------------*/
00507   /*!< Configure the SDIO peripheral */
00508   /*!< SDIOCLK = HCLK, SDIO_CK = HCLK/(2 + SDIO_INIT_CLK_DIV) */
00509   /*!< on STM32F2xx devices, SDIOCLK is fixed to 48MHz */
00510   /*!< SDIO_CK for initialization should not exceed 400 KHz */
00511   SDIO_InitStructure.SDIO_ClockDiv = SDIO_INIT_CLK_DIV;
00512   SDIO_InitStructure.SDIO_ClockEdge = SDIO_ClockEdge_Rising;
00513   SDIO_InitStructure.SDIO_ClockBypass = SDIO_ClockBypass_Disable;
00514   SDIO_InitStructure.SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable;
00515   SDIO_InitStructure.SDIO_BusWide = SDIO_BusWide_1b;
00516   SDIO_InitStructure.SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable;
00517   SDIO_Init(&SDIO_InitStructure);
00518
00519   /*!< Set Power State to ON */
00520   SDIO_SetPowerState(SDIO_PowerState_ON);
00521
00522   /*!< Enable SDIO Clock */
00523   SDIO_ClockCmd(ENABLE);
00524
00525   /*!< CMD0: GO_IDLE_STATE ---------------------------------------------------*/
00526   /*!< No CMD response required */
00527   SDIO_CmdInitStructure.SDIO_Argument = 0x0;
00528   SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_GO_IDLE_STATE;
00529   SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_No;
00530   SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
00531   SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
00532   SDIO_SendCommand(&SDIO_CmdInitStructure);
00533
00534   errorstatus = CmdError();
00535
00536   if (errorstatus != SD_OK)
00537   {
00538     /*!< CMD Response TimeOut (wait for CMDSENT flag) */
00539     return(errorstatus);
00540   }
00541
00542   /*!< CMD8: SEND_IF_COND ----------------------------------------------------*/
00543   /*!< Send CMD8 to verify SD card interface operating condition */
00544   /*!< Argument: - [31:12]: Reserved (shall be set to '0')
00545                - [11:8]: Supply Voltage (VHS) 0x1 (Range: 2.7-3.6 V)
00546                - [7:0]: Check Pattern (recommended 0xAA) */
00547   /*!< CMD Response: R7 */
00548   SDIO_CmdInitStructure.SDIO_Argument = SD_CHECK_PATTERN;
00549   SDIO_CmdInitStructure.SDIO_CmdIndex = SDIO_SEND_IF_COND;
00550   SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
00551   SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
00552   SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
00553   SDIO_SendCommand(&SDIO_CmdInitStructure);
00554
00555   errorstatus = CmdResp7Error();
00556
00557   if (errorstatus == SD_OK)
00558   {
00559     CardType = SDIO_STD_CAPACITY_SD_CARD_V2_0; /*!< SD Card 2.0 */
00560     SDType = SD_HIGH_CAPACITY;
00561   }
00562   else
00563   {
00564     /*!< CMD55 */
00565     SDIO_CmdInitStructure.SDIO_Argument = 0x00;
00566     SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_CMD;
00567     SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
00568     SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
00569     SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
00570     SDIO_SendCommand(&SDIO_CmdInitStructure);
00571     errorstatus = CmdResp1Error(SD_CMD_APP_CMD);
00572   }
00573   /*!< CMD55 */
00574   SDIO_CmdInitStructure.SDIO_Argument = 0x00;
00575   SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_CMD;
00576   SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
00577   SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
00578   SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
00579   SDIO_SendCommand(&SDIO_CmdInitStructure);
00580   errorstatus = CmdResp1Error(SD_CMD_APP_CMD);
00581
00582   /*!< If errorstatus is Command TimeOut, it is a MMC card */
00583   /*!< If errorstatus is SD_OK it is a SD card: SD card 2.0 (voltage range mismatch)
00584      or SD card 1.x */
00585   if (errorstatus == SD_OK)
00586   {
00587     /*!< SD CARD */
00588     /*!< Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */
00589     while ((!validvoltage) && (count < SD_MAX_VOLT_TRIAL))
00590     {
00591
00592       /*!< SEND CMD55 APP_CMD with RCA as 0 */
00593       SDIO_CmdInitStructure.SDIO_Argument = 0x00;
00594       SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_CMD;
00595       SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
00596       SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
00597       SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
00598       SDIO_SendCommand(&SDIO_CmdInitStructure);
00599
00600       errorstatus = CmdResp1Error(SD_CMD_APP_CMD);
00601
00602       if (errorstatus != SD_OK)
00603       {
00604         return(errorstatus);
00605       }
00606       SDIO_CmdInitStructure.SDIO_Argument = SD_VOLTAGE_WINDOW_SD | SDType;
00607       SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SD_APP_OP_COND;
00608       SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
00609       SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
00610       SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
00611       SDIO_SendCommand(&SDIO_CmdInitStructure);
00612
00613       errorstatus = CmdResp3Error();
00614       if (errorstatus != SD_OK)
00615       {
00616         return(errorstatus);
00617       }
00618
00619       response = SDIO_GetResponse(SDIO_RESP1);
00620       validvoltage = (((response >> 31) == 1) ? 1 : 0);
00621       count++;
00622     }
00623     if (count >= SD_MAX_VOLT_TRIAL)
00624     {
00625       errorstatus = SD_INVALID_VOLTRANGE;
00626       return(errorstatus);
00627     }
00628
00629     if (response &= SD_HIGH_CAPACITY)
00630     {
00631       CardType = SDIO_HIGH_CAPACITY_SD_CARD;
00632     }
00633
00634   }/*!< else MMC Card */
00635
00636   return(errorstatus);
00637 }
00638
00639 /**
00640   * @brief  Turns the SDIO output signals off.
00641   * @param  None
00642   * @retval SD_Error: SD Card Error code.
00643   */
00644 SD_Error SD_PowerOFF(void)
00645 {
00646   SD_Error errorstatus = SD_OK;
00647
00648   /*!< Set Power State to OFF */
00649   SDIO_SetPowerState(SDIO_PowerState_OFF);
00650
00651   return(errorstatus);
00652 }
00653
00654 /**
00655   * @brief  Intialises all cards or single card as the case may be Card(s) come
00656   *         into standby state.
00657   * @param  None
00658   * @retval SD_Error: SD Card Error code.
00659   */
00660 SD_Error SD_InitializeCards(void)
00661 {
00662   SD_Error errorstatus = SD_OK;
00663   uint16_t rca = 0x01;
00664
00665   if (SDIO_GetPowerState() == SDIO_PowerState_OFF)
00666   {
00667     errorstatus = SD_REQUEST_NOT_APPLICABLE;
00668     return(errorstatus);
00669   }
00670
00671   if (SDIO_SECURE_DIGITAL_IO_CARD != CardType)
00672   {
00673     /*!< Send CMD2 ALL_SEND_CID */
00674     SDIO_CmdInitStructure.SDIO_Argument = 0x0;
00675     SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_ALL_SEND_CID;
00676     SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Long;
00677     SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
00678     SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
00679     SDIO_SendCommand(&SDIO_CmdInitStructure);
00680
00681     errorstatus = CmdResp2Error();
00682
00683     if (SD_OK != errorstatus)
00684     {
00685       return(errorstatus);
00686     }
00687
00688     CID_Tab[0] = SDIO_GetResponse(SDIO_RESP1);
00689     CID_Tab[1] = SDIO_GetResponse(SDIO_RESP2);
00690     CID_Tab[2] = SDIO_GetResponse(SDIO_RESP3);
00691     CID_Tab[3] = SDIO_GetResponse(SDIO_RESP4);
00692   }
00693   if ((SDIO_STD_CAPACITY_SD_CARD_V1_1 == CardType) ||  (SDIO_STD_CAPACITY_SD_CARD_V2_0 == CardType) ||  (SDIO_SECURE_DIGITAL_IO_COMBO_CARD == CardType)
00694       ||  (SDIO_HIGH_CAPACITY_SD_CARD == CardType))
00695   {
00696     /*!< Send CMD3 SET_REL_ADDR with argument 0 */
00697     /*!< SD Card publishes its RCA. */
00698     SDIO_CmdInitStructure.SDIO_Argument = 0x00;
00699     SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SET_REL_ADDR;
00700     SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
00701     SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
00702     SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
00703     SDIO_SendCommand(&SDIO_CmdInitStructure);
00704
00705     errorstatus = CmdResp6Error(SD_CMD_SET_REL_ADDR, &rca);
00706
00707     if (SD_OK != errorstatus)
00708     {
00709       return(errorstatus);
00710     }
00711   }
00712
00713   if (SDIO_SECURE_DIGITAL_IO_CARD != CardType)
00714   {
00715     RCA = rca;
00716
00717     /*!< Send CMD9 SEND_CSD with argument as card's RCA */
00718     SDIO_CmdInitStructure.SDIO_Argument = (uint32_t)(rca << 16);
00719     SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SEND_CSD;
00720     SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Long;
00721     SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
00722     SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
00723     SDIO_SendCommand(&SDIO_CmdInitStructure);
00724
00725     errorstatus = CmdResp2Error();
00726
00727     if (SD_OK != errorstatus)
00728     {
00729       return(errorstatus);
00730     }
00731
00732     CSD_Tab[0] = SDIO_GetResponse(SDIO_RESP1);
00733     CSD_Tab[1] = SDIO_GetResponse(SDIO_RESP2);
00734     CSD_Tab[2] = SDIO_GetResponse(SDIO_RESP3);
00735     CSD_Tab[3] = SDIO_GetResponse(SDIO_RESP4);
00736   }
00737
00738   errorstatus = SD_OK; /*!< All cards get intialized */
00739
00740   return(errorstatus);
00741 }
00742
00743 /**
00744   * @brief  Returns information about specific card.
00745   * @param  cardinfo: pointer to a SD_CardInfo structure that contains all SD card
00746   *         information.
00747   * @retval SD_Error: SD Card Error code.
00748   */
00749 SD_Error SD_GetCardInfo(SD_CardInfo *cardinfo)
00750 {
00751   SD_Error errorstatus = SD_OK;
00752   uint8_t tmp = 0;
00753
00754   cardinfo->CardType = (uint8_t)CardType;
00755   cardinfo->RCA = (uint16_t)RCA;
00756
00757   /*!< Byte 0 */
00758   tmp = (uint8_t)((CSD_Tab[0] & 0xFF000000) >> 24);
00759   cardinfo->SD_csd.CSDStruct = (tmp & 0xC0) >> 6;
00760   cardinfo->SD_csd.SysSpecVersion = (tmp & 0x3C) >> 2;
00761   cardinfo->SD_csd.Reserved1 = tmp & 0x03;
00762
00763   /*!< Byte 1 */
00764   tmp = (uint8_t)((CSD_Tab[0] & 0x00FF0000) >> 16);
00765   cardinfo->SD_csd.TAAC = tmp;
00766
00767   /*!< Byte 2 */
00768   tmp = (uint8_t)((CSD_Tab[0] & 0x0000FF00) >> 8);
00769   cardinfo->SD_csd.NSAC = tmp;
00770
00771   /*!< Byte 3 */
00772   tmp = (uint8_t)(CSD_Tab[0] & 0x000000FF);
00773   cardinfo->SD_csd.MaxBusClkFrec = tmp;
00774
00775   /*!< Byte 4 */
00776   tmp = (uint8_t)((CSD_Tab[1] & 0xFF000000) >> 24);
00777   cardinfo->SD_csd.CardComdClasses = tmp << 4;
00778
00779   /*!< Byte 5 */
00780   tmp = (uint8_t)((CSD_Tab[1] & 0x00FF0000) >> 16);
00781   cardinfo->SD_csd.CardComdClasses |= (tmp & 0xF0) >> 4;
00782   cardinfo->SD_csd.RdBlockLen = tmp & 0x0F;
00783
00784   /*!< Byte 6 */
00785   tmp = (uint8_t)((CSD_Tab[1] & 0x0000FF00) >> 8);
00786   cardinfo->SD_csd.PartBlockRead = (tmp & 0x80) >> 7;
00787   cardinfo->SD_csd.WrBlockMisalign = (tmp & 0x40) >> 6;
00788   cardinfo->SD_csd.RdBlockMisalign = (tmp & 0x20) >> 5;
00789   cardinfo->SD_csd.DSRImpl = (tmp & 0x10) >> 4;
00790   cardinfo->SD_csd.Reserved2 = 0; /*!< Reserved */
00791
00792   if ((CardType == SDIO_STD_CAPACITY_SD_CARD_V1_1) || (CardType == SDIO_STD_CAPACITY_SD_CARD_V2_0))
00793   {
00794     cardinfo->SD_csd.DeviceSize = (tmp & 0x03) << 10;
00795
00796     /*!< Byte 7 */
00797     tmp = (uint8_t)(CSD_Tab[1] & 0x000000FF);
00798     cardinfo->SD_csd.DeviceSize |= (tmp) << 2;
00799
00800     /*!< Byte 8 */
00801     tmp = (uint8_t)((CSD_Tab[2] & 0xFF000000) >> 24);
00802     cardinfo->SD_csd.DeviceSize |= (tmp & 0xC0) >> 6;
00803
00804     cardinfo->SD_csd.MaxRdCurrentVDDMin = (tmp & 0x38) >> 3;
00805     cardinfo->SD_csd.MaxRdCurrentVDDMax = (tmp & 0x07);
00806
00807     /*!< Byte 9 */
00808     tmp = (uint8_t)((CSD_Tab[2] & 0x00FF0000) >> 16);
00809     cardinfo->SD_csd.MaxWrCurrentVDDMin = (tmp & 0xE0) >> 5;
00810     cardinfo->SD_csd.MaxWrCurrentVDDMax = (tmp & 0x1C) >> 2;
00811     cardinfo->SD_csd.DeviceSizeMul = (tmp & 0x03) << 1;
00812     /*!< Byte 10 */
00813     tmp = (uint8_t)((CSD_Tab[2] & 0x0000FF00) >> 8);
00814     cardinfo->SD_csd.DeviceSizeMul |= (tmp & 0x80) >> 7;
00815
00816     cardinfo->CardCapacity = (cardinfo->SD_csd.DeviceSize + 1) ;
00817     cardinfo->CardCapacity *= (1 << (cardinfo->SD_csd.DeviceSizeMul + 2));
00818     cardinfo->CardBlockSize = 1 << (cardinfo->SD_csd.RdBlockLen);
00819     cardinfo->CardCapacity *= cardinfo->CardBlockSize;
00820   }
00821   else if (CardType == SDIO_HIGH_CAPACITY_SD_CARD)
00822   {
00823     /*!< Byte 7 */
00824     tmp = (uint8_t)(CSD_Tab[1] & 0x000000FF);
00825     cardinfo->SD_csd.DeviceSize = (tmp & 0x3F) << 16;
00826
00827     /*!< Byte 8 */
00828     tmp = (uint8_t)((CSD_Tab[2] & 0xFF000000) >> 24);
00829
00830     cardinfo->SD_csd.DeviceSize |= (tmp << 8);
00831
00832     /*!< Byte 9 */
00833     tmp = (uint8_t)((CSD_Tab[2] & 0x00FF0000) >> 16);
00834
00835     cardinfo->SD_csd.DeviceSize |= (tmp);
00836
00837     /*!< Byte 10 */
00838     tmp = (uint8_t)((CSD_Tab[2] & 0x0000FF00) >> 8);
00839
00840     cardinfo->CardCapacity = (cardinfo->SD_csd.DeviceSize + 1) * 512 * 1024;
00841     cardinfo->CardBlockSize = 512;
00842   }
00843
00844
00845   cardinfo->SD_csd.EraseGrSize = (tmp & 0x40) >> 6;
00846   cardinfo->SD_csd.EraseGrMul = (tmp & 0x3F) << 1;
00847
00848   /*!< Byte 11 */
00849   tmp = (uint8_t)(CSD_Tab[2] & 0x000000FF);
00850   cardinfo->SD_csd.EraseGrMul |= (tmp & 0x80) >> 7;
00851   cardinfo->SD_csd.WrProtectGrSize = (tmp & 0x7F);
00852
00853   /*!< Byte 12 */
00854   tmp = (uint8_t)((CSD_Tab[3] & 0xFF000000) >> 24);
00855   cardinfo->SD_csd.WrProtectGrEnable = (tmp & 0x80) >> 7;
00856   cardinfo->SD_csd.ManDeflECC = (tmp & 0x60) >> 5;
00857   cardinfo->SD_csd.WrSpeedFact = (tmp & 0x1C) >> 2;
00858   cardinfo->SD_csd.MaxWrBlockLen = (tmp & 0x03) << 2;
00859
00860   /*!< Byte 13 */
00861   tmp = (uint8_t)((CSD_Tab[3] & 0x00FF0000) >> 16);
00862   cardinfo->SD_csd.MaxWrBlockLen |= (tmp & 0xC0) >> 6;
00863   cardinfo->SD_csd.WriteBlockPaPartial = (tmp & 0x20) >> 5;
00864   cardinfo->SD_csd.Reserved3 = 0;
00865   cardinfo->SD_csd.ContentProtectAppli = (tmp & 0x01);
00866
00867   /*!< Byte 14 */
00868   tmp = (uint8_t)((CSD_Tab[3] & 0x0000FF00) >> 8);
00869   cardinfo->SD_csd.FileFormatGrouop = (tmp & 0x80) >> 7;
00870   cardinfo->SD_csd.CopyFlag = (tmp & 0x40) >> 6;
00871   cardinfo->SD_csd.PermWrProtect = (tmp & 0x20) >> 5;
00872   cardinfo->SD_csd.TempWrProtect = (tmp & 0x10) >> 4;
00873   cardinfo->SD_csd.FileFormat = (tmp & 0x0C) >> 2;
00874   cardinfo->SD_csd.ECC = (tmp & 0x03);
00875
00876   /*!< Byte 15 */
00877   tmp = (uint8_t)(CSD_Tab[3] & 0x000000FF);
00878   cardinfo->SD_csd.CSD_CRC = (tmp & 0xFE) >> 1;
00879   cardinfo->SD_csd.Reserved4 = 1;
00880
00881
00882   /*!< Byte 0 */
00883   tmp = (uint8_t)((CID_Tab[0] & 0xFF000000) >> 24);
00884   cardinfo->SD_cid.ManufacturerID = tmp;
00885
00886   /*!< Byte 1 */
00887   tmp = (uint8_t)((CID_Tab[0] & 0x00FF0000) >> 16);
00888   cardinfo->SD_cid.OEM_AppliID = tmp << 8;
00889
00890   /*!< Byte 2 */
00891   tmp = (uint8_t)((CID_Tab[0] & 0x000000FF00) >> 8);
00892   cardinfo->SD_cid.OEM_AppliID |= tmp;
00893
00894   /*!< Byte 3 */
00895   tmp = (uint8_t)(CID_Tab[0] & 0x000000FF);
00896   cardinfo->SD_cid.ProdName1 = tmp << 24;
00897
00898   /*!< Byte 4 */
00899   tmp = (uint8_t)((CID_Tab[1] & 0xFF000000) >> 24);
00900   cardinfo->SD_cid.ProdName1 |= tmp << 16;
00901
00902   /*!< Byte 5 */
00903   tmp = (uint8_t)((CID_Tab[1] & 0x00FF0000) >> 16);
00904   cardinfo->SD_cid.ProdName1 |= tmp << 8;
00905
00906   /*!< Byte 6 */
00907   tmp = (uint8_t)((CID_Tab[1] & 0x0000FF00) >> 8);
00908   cardinfo->SD_cid.ProdName1 |= tmp;
00909
00910   /*!< Byte 7 */
00911   tmp = (uint8_t)(CID_Tab[1] & 0x000000FF);
00912   cardinfo->SD_cid.ProdName2 = tmp;
00913
00914   /*!< Byte 8 */
00915   tmp = (uint8_t)((CID_Tab[2] & 0xFF000000) >> 24);
00916   cardinfo->SD_cid.ProdRev = tmp;
00917
00918   /*!< Byte 9 */
00919   tmp = (uint8_t)((CID_Tab[2] & 0x00FF0000) >> 16);
00920   cardinfo->SD_cid.ProdSN = tmp << 24;
00921
00922   /*!< Byte 10 */
00923   tmp = (uint8_t)((CID_Tab[2] & 0x0000FF00) >> 8);
00924   cardinfo->SD_cid.ProdSN |= tmp << 16;
00925
00926   /*!< Byte 11 */
00927   tmp = (uint8_t)(CID_Tab[2] & 0x000000FF);
00928   cardinfo->SD_cid.ProdSN |= tmp << 8;
00929
00930   /*!< Byte 12 */
00931   tmp = (uint8_t)((CID_Tab[3] & 0xFF000000) >> 24);
00932   cardinfo->SD_cid.ProdSN |= tmp;
00933
00934   /*!< Byte 13 */
00935   tmp = (uint8_t)((CID_Tab[3] & 0x00FF0000) >> 16);
00936   cardinfo->SD_cid.Reserved1 |= (tmp & 0xF0) >> 4;
00937   cardinfo->SD_cid.ManufactDate = (tmp & 0x0F) << 8;
00938
00939   /*!< Byte 14 */
00940   tmp = (uint8_t)((CID_Tab[3] & 0x0000FF00) >> 8);
00941   cardinfo->SD_cid.ManufactDate |= tmp;
00942
00943   /*!< Byte 15 */
00944   tmp = (uint8_t)(CID_Tab[3] & 0x000000FF);
00945   cardinfo->SD_cid.CID_CRC = (tmp & 0xFE) >> 1;
00946   cardinfo->SD_cid.Reserved2 = 1;
00947
00948   return(errorstatus);
00949 }
00950
00951 /**
00952   * @brief  Enables wide bus opeartion for the requeseted card if supported by
00953   *         card.
00954   * @param  WideMode: Specifies the SD card wide bus mode.
00955   *   This parameter can be one of the following values:
00956   *     @arg SDIO_BusWide_8b: 8-bit data transfer (Only for MMC)
00957   *     @arg SDIO_BusWide_4b: 4-bit data transfer
00958   *     @arg SDIO_BusWide_1b: 1-bit data transfer
00959   * @retval SD_Error: SD Card Error code.
00960   */
00961 SD_Error SD_GetCardStatus(SD_CardStatus *cardstatus)
00962 {
00963   SD_Error errorstatus = SD_OK;
00964   uint8_t tmp = 0;
00965
00966   errorstatus = SD_SendSDStatus((uint32_t *)SDSTATUS_Tab);
00967
00968   if (errorstatus  != SD_OK)
00969   {
00970     return(errorstatus);
00971   }
00972
00973   /*!< Byte 0 */
00974   tmp = (uint8_t)((SDSTATUS_Tab[0] & 0xC0) >> 6);
00975   cardstatus->DAT_BUS_WIDTH = tmp;
00976
00977   /*!< Byte 0 */
00978   tmp = (uint8_t)((SDSTATUS_Tab[0] & 0x20) >> 5);
00979   cardstatus->SECURED_MODE = tmp;
00980
00981   /*!< Byte 2 */
00982   tmp = (uint8_t)((SDSTATUS_Tab[2] & 0xFF));
00983   cardstatus->SD_CARD_TYPE = tmp << 8;
00984
00985   /*!< Byte 3 */
00986   tmp = (uint8_t)((SDSTATUS_Tab[3] & 0xFF));
00987   cardstatus->SD_CARD_TYPE |= tmp;
00988
00989   /*!< Byte 4 */
00990   tmp = (uint8_t)(SDSTATUS_Tab[4] & 0xFF);
00991   cardstatus->SIZE_OF_PROTECTED_AREA = tmp << 24;
00992
00993   /*!< Byte 5 */
00994   tmp = (uint8_t)(SDSTATUS_Tab[5] & 0xFF);
00995   cardstatus->SIZE_OF_PROTECTED_AREA |= tmp << 16;
00996
00997   /*!< Byte 6 */
00998   tmp = (uint8_t)(SDSTATUS_Tab[6] & 0xFF);
00999   cardstatus->SIZE_OF_PROTECTED_AREA |= tmp << 8;
01000
01001   /*!< Byte 7 */
01002   tmp = (uint8_t)(SDSTATUS_Tab[7] & 0xFF);
01003   cardstatus->SIZE_OF_PROTECTED_AREA |= tmp;
01004
01005   /*!< Byte 8 */
01006   tmp = (uint8_t)((SDSTATUS_Tab[8] & 0xFF));
01007   cardstatus->SPEED_CLASS = tmp;
01008
01009   /*!< Byte 9 */
01010   tmp = (uint8_t)((SDSTATUS_Tab[9] & 0xFF));
01011   cardstatus->PERFORMANCE_MOVE = tmp;
01012
01013   /*!< Byte 10 */
01014   tmp = (uint8_t)((SDSTATUS_Tab[10] & 0xF0) >> 4);
01015   cardstatus->AU_SIZE = tmp;
01016
01017   /*!< Byte 11 */
01018   tmp = (uint8_t)(SDSTATUS_Tab[11] & 0xFF);
01019   cardstatus->ERASE_SIZE = tmp << 8;
01020
01021   /*!< Byte 12 */
01022   tmp = (uint8_t)(SDSTATUS_Tab[12] & 0xFF);
01023   cardstatus->ERASE_SIZE |= tmp;
01024
01025   /*!< Byte 13 */
01026   tmp = (uint8_t)((SDSTATUS_Tab[13] & 0xFC) >> 2);
01027   cardstatus->ERASE_TIMEOUT = tmp;
01028
01029   /*!< Byte 13 */
01030   tmp = (uint8_t)((SDSTATUS_Tab[13] & 0x3));
01031   cardstatus->ERASE_OFFSET = tmp;
01032
01033   return(errorstatus);
01034 }
01035
01036 /**
01037   * @brief  Enables wide bus opeartion for the requeseted card if supported by
01038   *         card.
01039   * @param  WideMode: Specifies the SD card wide bus mode.
01040   *   This parameter can be one of the following values:
01041   *     @arg SDIO_BusWide_8b: 8-bit data transfer (Only for MMC)
01042   *     @arg SDIO_BusWide_4b: 4-bit data transfer
01043   *     @arg SDIO_BusWide_1b: 1-bit data transfer
01044   * @retval SD_Error: SD Card Error code.
01045   */
01046 SD_Error SD_EnableWideBusOperation(uint32_t WideMode)
01047 {
01048   SD_Error errorstatus = SD_OK;
01049
01050   /*!< MMC Card doesn't support this feature */
01051   if (SDIO_MULTIMEDIA_CARD == CardType)
01052   {
01053     errorstatus = SD_UNSUPPORTED_FEATURE;
01054     return(errorstatus);
01055   }
01056   else if ((SDIO_STD_CAPACITY_SD_CARD_V1_1 == CardType) || (SDIO_STD_CAPACITY_SD_CARD_V2_0 == CardType) || (SDIO_HIGH_CAPACITY_SD_CARD == CardType))
01057   {
01058     if (SDIO_BusWide_8b == WideMode)
01059     {
01060       errorstatus = SD_UNSUPPORTED_FEATURE;
01061       return(errorstatus);
01062     }
01063     else if (SDIO_BusWide_4b == WideMode)
01064     {
01065       errorstatus = SDEnWideBus(ENABLE);
01066
01067       if (SD_OK == errorstatus)
01068       {
01069         /*!< Configure the SDIO peripheral */
01070         SDIO_InitStructure.SDIO_ClockDiv = SDIO_TRANSFER_CLK_DIV;
01071         SDIO_InitStructure.SDIO_ClockEdge = SDIO_ClockEdge_Rising;
01072         SDIO_InitStructure.SDIO_ClockBypass = SDIO_ClockBypass_Disable;
01073         SDIO_InitStructure.SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable;
01074         SDIO_InitStructure.SDIO_BusWide = SDIO_BusWide_4b;
01075         SDIO_InitStructure.SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable;
01076         SDIO_Init(&SDIO_InitStructure);
01077       }
01078     }
01079     else
01080     {
01081       errorstatus = SDEnWideBus(DISABLE);
01082
01083       if (SD_OK == errorstatus)
01084       {
01085         /*!< Configure the SDIO peripheral */
01086         SDIO_InitStructure.SDIO_ClockDiv = SDIO_TRANSFER_CLK_DIV;
01087         SDIO_InitStructure.SDIO_ClockEdge = SDIO_ClockEdge_Rising;
01088         SDIO_InitStructure.SDIO_ClockBypass = SDIO_ClockBypass_Disable;
01089         SDIO_InitStructure.SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable;
01090         SDIO_InitStructure.SDIO_BusWide = SDIO_BusWide_1b;
01091         SDIO_InitStructure.SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable;
01092         SDIO_Init(&SDIO_InitStructure);
01093       }
01094     }
01095   }
01096
01097   return(errorstatus);
01098 }
01099
01100 /**
01101   * @brief  Selects od Deselects the corresponding card.
01102   * @param  addr: Address of the Card to be selected.
01103   * @retval SD_Error: SD Card Error code.
01104   */
01105 SD_Error SD_SelectDeselect(uint32_t addr)
01106 {
01107   SD_Error errorstatus = SD_OK;
01108
01109   /*!< Send CMD7 SDIO_SEL_DESEL_CARD */
01110   SDIO_CmdInitStructure.SDIO_Argument =  addr;
01111   SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SEL_DESEL_CARD;
01112   SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
01113   SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
01114   SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
01115   SDIO_SendCommand(&SDIO_CmdInitStructure);
01116
01117   errorstatus = CmdResp1Error(SD_CMD_SEL_DESEL_CARD);
01118
01119   return(errorstatus);
01120 }
01121
01122 /**
01123   * @brief  Allows to read one block from a specified address in a card. The Data
01124   *         transfer can be managed by DMA mode or Polling mode.
01125   * @note   This operation should be followed by two functions to check if the
01126   *         DMA Controller and SD Card status.
01127   *          - SD_ReadWaitOperation(): this function insure that the DMA
01128   *            controller has finished all data transfer.
01129   *          - SD_GetStatus(): to check that the SD Card has finished the
01130   *            data transfer and it is ready for data.
01131   * @param  readbuff: pointer to the buffer that will contain the received data
01132   * @param  ReadAddr: Address from where data are to be read.
01133   * @param  BlockSize: the SD card Data block size. The Block size should be 512.
01134   * @retval SD_Error: SD Card Error code.
01135   */
01136 SD_Error SD_ReadBlock(uint8_t *readbuff, uint32_t ReadAddr, uint16_t BlockSize)
01137 {
01138   SD_Error errorstatus = SD_OK;
01139 #if defined (SD_POLLING_MODE)
01140   uint32_t count = 0, *tempbuff = (uint32_t *)readbuff;
01141 #endif
01142
01143   TransferError = SD_OK;
01144   TransferEnd = 0;
01145   StopCondition = 0;
01146
01147   SDIO->DCTRL = 0x0;
01148
01149
01150   if (CardType == SDIO_HIGH_CAPACITY_SD_CARD)
01151   {
01152     BlockSize = 512;
01153     ReadAddr /= 512;
01154   }
01155
01156   SDIO_DataInitStructure.SDIO_DataTimeOut = SD_DATATIMEOUT;
01157   SDIO_DataInitStructure.SDIO_DataLength = BlockSize;
01158   SDIO_DataInitStructure.SDIO_DataBlockSize = (uint32_t) 9 << 4;
01159   SDIO_DataInitStructure.SDIO_TransferDir = SDIO_TransferDir_ToSDIO;
01160   SDIO_DataInitStructure.SDIO_TransferMode = SDIO_TransferMode_Block;
01161   SDIO_DataInitStructure.SDIO_DPSM = SDIO_DPSM_Enable;
01162   SDIO_DataConfig(&SDIO_DataInitStructure);
01163
01164   /*!< Send CMD17 READ_SINGLE_BLOCK */
01165   SDIO_CmdInitStructure.SDIO_Argument = (uint32_t)ReadAddr;
01166   SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_READ_SINGLE_BLOCK;
01167   SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
01168   SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
01169   SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
01170   SDIO_SendCommand(&SDIO_CmdInitStructure);
01171
01172   errorstatus = CmdResp1Error(SD_CMD_READ_SINGLE_BLOCK);
01173
01174   if (errorstatus != SD_OK)
01175   {
01176     return(errorstatus);
01177   }
01178
01179 #if defined (SD_POLLING_MODE)
01180   /*!< In case of single block transfer, no need of stop transfer at all.*/
01181   /*!< Polling mode */
01182   while (!(SDIO->STA &(SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR)))
01183   {
01184     if (SDIO_GetFlagStatus(SDIO_FLAG_RXFIFOHF) != RESET)
01185     {
01186       for (count = 0; count < 8; count++)
01187       {
01188         *(tempbuff + count) = SDIO_ReadData();
01189       }
01190       tempbuff += 8;
01191     }
01192   }
01193
01194   if (SDIO_GetFlagStatus(SDIO_FLAG_DTIMEOUT) != RESET)
01195   {
01196     SDIO_ClearFlag(SDIO_FLAG_DTIMEOUT);
01197     errorstatus = SD_DATA_TIMEOUT;
01198     return(errorstatus);
01199   }
01200   else if (SDIO_GetFlagStatus(SDIO_FLAG_DCRCFAIL) != RESET)
01201   {
01202     SDIO_ClearFlag(SDIO_FLAG_DCRCFAIL);
01203     errorstatus = SD_DATA_CRC_FAIL;
01204     return(errorstatus);
01205   }
01206   else if (SDIO_GetFlagStatus(SDIO_FLAG_RXOVERR) != RESET)
01207   {
01208     SDIO_ClearFlag(SDIO_FLAG_RXOVERR);
01209     errorstatus = SD_RX_OVERRUN;
01210     return(errorstatus);
01211   }
01212   else if (SDIO_GetFlagStatus(SDIO_FLAG_STBITERR) != RESET)
01213   {
01214     SDIO_ClearFlag(SDIO_FLAG_STBITERR);
01215     errorstatus = SD_START_BIT_ERR;
01216     return(errorstatus);
01217   }
01218   while (SDIO_GetFlagStatus(SDIO_FLAG_RXDAVL) != RESET)
01219   {
01220     *tempbuff = SDIO_ReadData();
01221     tempbuff++;
01222   }
01223
01224   /*!< Clear all the static flags */
01225   SDIO_ClearFlag(SDIO_STATIC_FLAGS);
01226
01227 #elif defined (SD_DMA_MODE)
01228     SDIO_ITConfig(SDIO_IT_DATAEND, ENABLE);
01229     SDIO_DMACmd(ENABLE);
01230     SD_LowLevel_DMA_RxConfig((uint32_t *)readbuff, BlockSize);
01231 #endif
01232
01233   return(errorstatus);
01234 }
01235
01236 /**
01237   * @brief  Allows to read blocks from a specified address  in a card.  The Data
01238   *         transfer can be managed by DMA mode or Polling mode.
01239   * @note   This operation should be followed by two functions to check if the
01240   *         DMA Controller and SD Card status.
01241   *          - SD_ReadWaitOperation(): this function insure that the DMA
01242   *            controller has finished all data transfer.
01243   *          - SD_GetStatus(): to check that the SD Card has finished the
01244   *            data transfer and it is ready for data.
01245   * @param  readbuff: pointer to the buffer that will contain the received data.
01246   * @param  ReadAddr: Address from where data are to be read.
01247   * @param  BlockSize: the SD card Data block size. The Block size should be 512.
01248   * @param  NumberOfBlocks: number of blocks to be read.
01249   * @retval SD_Error: SD Card Error code.
01250   */
01251 SD_Error SD_ReadMultiBlocks(uint8_t *readbuff, uint32_t ReadAddr, uint16_t BlockSize, uint32_t NumberOfBlocks)
01252 {
01253   SD_Error errorstatus = SD_OK;
01254   TransferError = SD_OK;
01255   TransferEnd = 0;
01256   StopCondition = 1;
01257
01258   SDIO->DCTRL = 0x0;
01259
01260   if (CardType == SDIO_HIGH_CAPACITY_SD_CARD)
01261   {
01262     BlockSize = 512;
01263     ReadAddr /= 512;
01264   }
01265
01266   /*!< Set Block Size for Card */
01267   SDIO_CmdInitStructure.SDIO_Argument = (uint32_t) BlockSize;
01268   SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SET_BLOCKLEN;
01269   SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
01270   SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
01271   SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
01272   SDIO_SendCommand(&SDIO_CmdInitStructure);
01273
01274   errorstatus = CmdResp1Error(SD_CMD_SET_BLOCKLEN);
01275
01276   if (SD_OK != errorstatus)
01277   {
01278     return(errorstatus);
01279   }
01280
01281   SDIO_DataInitStructure.SDIO_DataTimeOut = SD_DATATIMEOUT;
01282   SDIO_DataInitStructure.SDIO_DataLength = NumberOfBlocks * BlockSize;
01283   SDIO_DataInitStructure.SDIO_DataBlockSize = (uint32_t) 9 << 4;
01284   SDIO_DataInitStructure.SDIO_TransferDir = SDIO_TransferDir_ToSDIO;
01285   SDIO_DataInitStructure.SDIO_TransferMode = SDIO_TransferMode_Block;
01286   SDIO_DataInitStructure.SDIO_DPSM = SDIO_DPSM_Enable;
01287   SDIO_DataConfig(&SDIO_DataInitStructure);
01288
01289   /*!< Send CMD18 READ_MULT_BLOCK with argument data address */
01290   SDIO_CmdInitStructure.SDIO_Argument = (uint32_t)ReadAddr;
01291   SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_READ_MULT_BLOCK;
01292   SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
01293   SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
01294   SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
01295   SDIO_SendCommand(&SDIO_CmdInitStructure);
01296
01297   errorstatus = CmdResp1Error(SD_CMD_READ_MULT_BLOCK);
01298
01299   if (errorstatus != SD_OK)
01300   {
01301     return(errorstatus);
01302   }
01303
01304   SDIO_ITConfig(SDIO_IT_DATAEND, ENABLE);
01305   SDIO_DMACmd(ENABLE);
01306   SD_LowLevel_DMA_RxConfig((uint32_t *)readbuff, (NumberOfBlocks * BlockSize));
01307
01308   return(errorstatus);
01309 }
01310
01311 /**
01312   * @brief  This function waits until the SDIO DMA data transfer is finished.
01313   *         This function should be called after SDIO_ReadMultiBlocks() function
01314   *         to insure that all data sent by the card are already transferred by
01315   *         the DMA controller.
01316   * @param  None.
01317   * @retval SD_Error: SD Card Error code.
01318   */
01319 SD_Error SD_WaitReadOperation(void)
01320 {
01321   SD_Error errorstatus = SD_OK;
01322
01323   while ((SD_DMAEndOfTransferStatus() == RESET) && (TransferEnd == 0) && (TransferError == SD_OK))
01324   {}
01325
01326   if (TransferError != SD_OK)
01327   {
01328     return(TransferError);
01329   }
01330
01331   return(errorstatus);
01332 }
01333
01334 /**
01335   * @brief  Allows to write one block starting from a specified address in a card.
01336   *         The Data transfer can be managed by DMA mode or Polling mode.
01337   * @note   This operation should be followed by two functions to check if the
01338   *         DMA Controller and SD Card status.
01339   *          - SD_ReadWaitOperation(): this function insure that the DMA
01340   *            controller has finished all data transfer.
01341   *          - SD_GetStatus(): to check that the SD Card has finished the
01342   *            data transfer and it is ready for data.
01343   * @param  writebuff: pointer to the buffer that contain the data to be transferred.
01344   * @param  WriteAddr: Address from where data are to be read.
01345   * @param  BlockSize: the SD card Data block size. The Block size should be 512.
01346   * @retval SD_Error: SD Card Error code.
01347   */
01348 SD_Error SD_WriteBlock(uint8_t *writebuff, uint32_t WriteAddr, uint16_t BlockSize)
01349 {
01350   SD_Error errorstatus = SD_OK;
01351
01352 #if defined (SD_POLLING_MODE)
01353   uint32_t bytestransferred = 0, count = 0, restwords = 0;
01354   uint32_t *tempbuff = (uint32_t *)writebuff;
01355 #endif
01356
01357   TransferError = SD_OK;
01358   TransferEnd = 0;
01359   StopCondition = 0;
01360
01361   SDIO->DCTRL = 0x0;
01362
01363
01364   if (CardType == SDIO_HIGH_CAPACITY_SD_CARD)
01365   {
01366     BlockSize = 512;
01367     WriteAddr /= 512;
01368   }
01369
01370   /*!< Send CMD24 WRITE_SINGLE_BLOCK */
01371   SDIO_CmdInitStructure.SDIO_Argument = WriteAddr;
01372   SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_WRITE_SINGLE_BLOCK;
01373   SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
01374   SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
01375   SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
01376   SDIO_SendCommand(&SDIO_CmdInitStructure);
01377
01378   errorstatus = CmdResp1Error(SD_CMD_WRITE_SINGLE_BLOCK);
01379
01380   if (errorstatus != SD_OK)
01381   {
01382     return(errorstatus);
01383   }
01384
01385   SDIO_DataInitStructure.SDIO_DataTimeOut = SD_DATATIMEOUT;
01386   SDIO_DataInitStructure.SDIO_DataLength = BlockSize;
01387   SDIO_DataInitStructure.SDIO_DataBlockSize = (uint32_t) 9 << 4;
01388   SDIO_DataInitStructure.SDIO_TransferDir = SDIO_TransferDir_ToCard;
01389   SDIO_DataInitStructure.SDIO_TransferMode = SDIO_TransferMode_Block;
01390   SDIO_DataInitStructure.SDIO_DPSM = SDIO_DPSM_Enable;
01391   SDIO_DataConfig(&SDIO_DataInitStructure);
01392
01393   /*!< In case of single data block transfer no need of stop command at all */
01394 #if defined (SD_POLLING_MODE)
01395   while (!(SDIO->STA & (SDIO_FLAG_DBCKEND | SDIO_FLAG_TXUNDERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_STBITERR)))
01396   {
01397     if (SDIO_GetFlagStatus(SDIO_FLAG_TXFIFOHE) != RESET)
01398     {
01399       if ((512 - bytestransferred) < 32)
01400       {
01401         restwords = ((512 - bytestransferred) % 4 == 0) ? ((512 - bytestransferred) / 4) : (( 512 -  bytestransferred) / 4 + 1);
01402         for (count = 0; count < restwords; count++, tempbuff++, bytestransferred += 4)
01403         {
01404           SDIO_WriteData(*tempbuff);
01405         }
01406       }
01407       else
01408       {
01409         for (count = 0; count < 8; count++)
01410         {
01411           SDIO_WriteData(*(tempbuff + count));
01412         }
01413         tempbuff += 8;
01414         bytestransferred += 32;
01415       }
01416     }
01417   }
01418   if (SDIO_GetFlagStatus(SDIO_FLAG_DTIMEOUT) != RESET)
01419   {
01420     SDIO_ClearFlag(SDIO_FLAG_DTIMEOUT);
01421     errorstatus = SD_DATA_TIMEOUT;
01422     return(errorstatus);
01423   }
01424   else if (SDIO_GetFlagStatus(SDIO_FLAG_DCRCFAIL) != RESET)
01425   {
01426     SDIO_ClearFlag(SDIO_FLAG_DCRCFAIL);
01427     errorstatus = SD_DATA_CRC_FAIL;
01428     return(errorstatus);
01429   }
01430   else if (SDIO_GetFlagStatus(SDIO_FLAG_TXUNDERR) != RESET)
01431   {
01432     SDIO_ClearFlag(SDIO_FLAG_TXUNDERR);
01433     errorstatus = SD_TX_UNDERRUN;
01434     return(errorstatus);
01435   }
01436   else if (SDIO_GetFlagStatus(SDIO_FLAG_STBITERR) != RESET)
01437   {
01438     SDIO_ClearFlag(SDIO_FLAG_STBITERR);
01439     errorstatus = SD_START_BIT_ERR;
01440     return(errorstatus);
01441   }
01442 #elif defined (SD_DMA_MODE)
01443   SDIO_ITConfig(SDIO_IT_DATAEND, ENABLE);
01444   SD_LowLevel_DMA_TxConfig((uint32_t *)writebuff, BlockSize);
01445   SDIO_DMACmd(ENABLE);
01446 #endif
01447
01448   return(errorstatus);
01449 }
01450
01451 /**
01452   * @brief  Allows to write blocks starting from a specified address in a card.
01453   *         The Data transfer can be managed by DMA mode only.
01454   * @note   This operation should be followed by two functions to check if the
01455   *         DMA Controller and SD Card status.
01456   *          - SD_ReadWaitOperation(): this function insure that the DMA
01457   *            controller has finished all data transfer.
01458   *          - SD_GetStatus(): to check that the SD Card has finished the
01459   *            data transfer and it is ready for data.
01460   * @param  WriteAddr: Address from where data are to be read.
01461   * @param  writebuff: pointer to the buffer that contain the data to be transferred.
01462   * @param  BlockSize: the SD card Data block size. The Block size should be 512.
01463   * @param  NumberOfBlocks: number of blocks to be written.
01464   * @retval SD_Error: SD Card Error code.
01465   */
01466 SD_Error SD_WriteMultiBlocks(uint8_t *writebuff, uint32_t WriteAddr, uint16_t BlockSize, uint32_t NumberOfBlocks)
01467 {
01468   SD_Error errorstatus = SD_OK;
01469   __IO uint32_t count = 0;
01470
01471   TransferError = SD_OK;
01472   TransferEnd = 0;
01473   StopCondition = 1;
01474
01475   SDIO->DCTRL = 0x0;
01476
01477   if (CardType == SDIO_HIGH_CAPACITY_SD_CARD)
01478   {
01479     BlockSize = 512;
01480     WriteAddr /= 512;
01481   }
01482
01483   /*!< To improve performance */
01484   SDIO_CmdInitStructure.SDIO_Argument = (uint32_t) (RCA << 16);
01485   SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_CMD;
01486   SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
01487   SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
01488   SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
01489   SDIO_SendCommand(&SDIO_CmdInitStructure);
01490
01491
01492   errorstatus = CmdResp1Error(SD_CMD_APP_CMD);
01493
01494   if (errorstatus != SD_OK)
01495   {
01496     return(errorstatus);
01497   }
01498   /*!< To improve performance */
01499   SDIO_CmdInitStructure.SDIO_Argument = (uint32_t)NumberOfBlocks;
01500   SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SET_BLOCK_COUNT;
01501   SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
01502   SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
01503   SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
01504   SDIO_SendCommand(&SDIO_CmdInitStructure);
01505
01506   errorstatus = CmdResp1Error(SD_CMD_SET_BLOCK_COUNT);
01507
01508   if (errorstatus != SD_OK)
01509   {
01510     return(errorstatus);
01511   }
01512
01513
01514   /*!< Send CMD25 WRITE_MULT_BLOCK with argument data address */
01515   SDIO_CmdInitStructure.SDIO_Argument = (uint32_t)WriteAddr;
01516   SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_WRITE_MULT_BLOCK;
01517   SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
01518   SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
01519   SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
01520   SDIO_SendCommand(&SDIO_CmdInitStructure);
01521
01522   errorstatus = CmdResp1Error(SD_CMD_WRITE_MULT_BLOCK);
01523
01524   if (SD_OK != errorstatus)
01525   {
01526     return(errorstatus);
01527   }
01528
01529   SDIO_DataInitStructure.SDIO_DataTimeOut = SD_DATATIMEOUT;
01530   SDIO_DataInitStructure.SDIO_DataLength = NumberOfBlocks * BlockSize;
01531   SDIO_DataInitStructure.SDIO_DataBlockSize = (uint32_t) 9 << 4;
01532   SDIO_DataInitStructure.SDIO_TransferDir = SDIO_TransferDir_ToCard;
01533   SDIO_DataInitStructure.SDIO_TransferMode = SDIO_TransferMode_Block;
01534   SDIO_DataInitStructure.SDIO_DPSM = SDIO_DPSM_Enable;
01535   SDIO_DataConfig(&SDIO_DataInitStructure);
01536
01537   SDIO_ITConfig(SDIO_IT_DATAEND, ENABLE);
01538   SDIO_DMACmd(ENABLE);
01539   SD_LowLevel_DMA_TxConfig((uint32_t *)writebuff, (NumberOfBlocks * BlockSize));
01540
01541   return(errorstatus);
01542 }
01543
01544 /**
01545   * @brief  This function waits until the SDIO DMA data transfer is finished.
01546   *         This function should be called after SDIO_WriteBlock() and
01547   *         SDIO_WriteMultiBlocks() function to insure that all data sent by the
01548   *         card are already transferred by the DMA controller.
01549   * @param  None.
01550   * @retval SD_Error: SD Card Error code.
01551   */
01552 SD_Error SD_WaitWriteOperation(void)
01553 {
01554   SD_Error errorstatus = SD_OK;
01555
01556   while ((SD_DMAEndOfTransferStatus() == RESET) && (TransferEnd == 0) && (TransferError == SD_OK))
01557   {}
01558
01559   if (TransferError != SD_OK)
01560   {
01561     return(TransferError);
01562   }
01563
01564   /*!< Clear all the static flags */
01565   SDIO_ClearFlag(SDIO_STATIC_FLAGS);
01566
01567   return(errorstatus);
01568 }
01569
01570 /**
01571   * @brief  Gets the cuurent data transfer state.
01572   * @param  None
01573   * @retval SDTransferState: Data Transfer state.
01574   *   This value can be:
01575   *        - SD_TRANSFER_OK: No data transfer is acting
01576   *        - SD_TRANSFER_BUSY: Data transfer is acting
01577   */
01578 SDTransferState SD_GetTransferState(void)
01579 {
01580   if (SDIO->STA & (SDIO_FLAG_TXACT | SDIO_FLAG_RXACT))
01581   {
01582     return(SD_TRANSFER_BUSY);
01583   }
01584   else
01585   {
01586     return(SD_TRANSFER_OK);
01587   }
01588 }
01589
01590 /**
01591   * @brief  Aborts an ongoing data transfer.
01592   * @param  None
01593   * @retval SD_Error: SD Card Error code.
01594   */
01595 SD_Error SD_StopTransfer(void)
01596 {
01597   SD_Error errorstatus = SD_OK;
01598
01599   /*!< Send CMD12 STOP_TRANSMISSION  */
01600   SDIO->ARG = 0x0;
01601   SDIO->CMD = 0x44C;
01602   errorstatus = CmdResp1Error(SD_CMD_STOP_TRANSMISSION);
01603
01604   return(errorstatus);
01605 }
01606
01607 /**
01608   * @brief  Allows to erase memory area specified for the given card.
01609   * @param  startaddr: the start address.
01610   * @param  endaddr: the end address.
01611   * @retval SD_Error: SD Card Error code.
01612   */
01613 SD_Error SD_Erase(uint32_t startaddr, uint32_t endaddr)
01614 {
01615   SD_Error errorstatus = SD_OK;
01616   uint32_t delay = 0;
01617   __IO uint32_t maxdelay = 0;
01618   uint8_t cardstate = 0;
01619
01620   /*!< Check if the card coomnd class supports erase command */
01621   if (((CSD_Tab[1] >> 20) & SD_CCCC_ERASE) == 0)
01622   {
01623     errorstatus = SD_REQUEST_NOT_APPLICABLE;
01624     return(errorstatus);
01625   }
01626
01627   maxdelay = 120000 / ((SDIO->CLKCR & 0xFF) + 2);
01628
01629   if (SDIO_GetResponse(SDIO_RESP1) & SD_CARD_LOCKED)
01630   {
01631     errorstatus = SD_LOCK_UNLOCK_FAILED;
01632     return(errorstatus);
01633   }
01634
01635   if (CardType == SDIO_HIGH_CAPACITY_SD_CARD)
01636   {
01637     startaddr /= 512;
01638     endaddr /= 512;
01639   }
01640
01641   /*!< According to sd-card spec 1.0 ERASE_GROUP_START (CMD32) and erase_group_end(CMD33) */
01642   if ((SDIO_STD_CAPACITY_SD_CARD_V1_1 == CardType) || (SDIO_STD_CAPACITY_SD_CARD_V2_0 == CardType) || (SDIO_HIGH_CAPACITY_SD_CARD == CardType))
01643   {
01644     /*!< Send CMD32 SD_ERASE_GRP_START with argument as addr  */
01645     SDIO_CmdInitStructure.SDIO_Argument = startaddr;
01646     SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SD_ERASE_GRP_START;
01647     SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
01648     SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
01649     SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
01650     SDIO_SendCommand(&SDIO_CmdInitStructure);
01651
01652     errorstatus = CmdResp1Error(SD_CMD_SD_ERASE_GRP_START);
01653     if (errorstatus != SD_OK)
01654     {
01655       return(errorstatus);
01656     }
01657
01658     /*!< Send CMD33 SD_ERASE_GRP_END with argument as addr  */
01659     SDIO_CmdInitStructure.SDIO_Argument = endaddr;
01660     SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SD_ERASE_GRP_END;
01661     SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
01662     SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
01663     SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
01664     SDIO_SendCommand(&SDIO_CmdInitStructure);
01665
01666     errorstatus = CmdResp1Error(SD_CMD_SD_ERASE_GRP_END);
01667     if (errorstatus != SD_OK)
01668     {
01669       return(errorstatus);
01670     }
01671   }
01672
01673   /*!< Send CMD38 ERASE */
01674   SDIO_CmdInitStructure.SDIO_Argument = 0;
01675   SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_ERASE;
01676   SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
01677   SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
01678   SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
01679   SDIO_SendCommand(&SDIO_CmdInitStructure);
01680
01681   errorstatus = CmdResp1Error(SD_CMD_ERASE);
01682
01683   if (errorstatus != SD_OK)
01684   {
01685     return(errorstatus);
01686   }
01687
01688   for (delay = 0; delay < maxdelay; delay++)
01689   {}
01690
01691   /*!< Wait till the card is in programming state */
01692   errorstatus = IsCardProgramming(&cardstate);
01693
01694   while ((errorstatus == SD_OK) && ((SD_CARD_PROGRAMMING == cardstate) || (SD_CARD_RECEIVING == cardstate)))
01695   {
01696     errorstatus = IsCardProgramming(&cardstate);
01697   }
01698
01699   return(errorstatus);
01700 }
01701
01702 /**
01703   * @brief  Returns the current card's status.
01704   * @param  pcardstatus: pointer to the buffer that will contain the SD card
01705   *         status (Card Status register).
01706   * @retval SD_Error: SD Card Error code.
01707   */
01708 SD_Error SD_SendStatus(uint32_t *pcardstatus)
01709 {
01710   SD_Error errorstatus = SD_OK;
01711
01712   SDIO->ARG = (uint32_t) RCA << 16;
01713   SDIO->CMD = 0x44D;
01714
01715   errorstatus = CmdResp1Error(SD_CMD_SEND_STATUS);
01716
01717   if (errorstatus != SD_OK)
01718   {
01719     return(errorstatus);
01720   }
01721
01722   *pcardstatus = SDIO->RESP1;
01723   return(errorstatus);
01724 }
01725
01726 /**
01727   * @brief  Returns the current SD card's status.
01728   * @param  psdstatus: pointer to the buffer that will contain the SD card status
01729   *         (SD Status register).
01730   * @retval SD_Error: SD Card Error code.
01731   */
01732 SD_Error SD_SendSDStatus(uint32_t *psdstatus)
01733 {
01734   SD_Error errorstatus = SD_OK;
01735   uint32_t count = 0;
01736
01737   if (SDIO_GetResponse(SDIO_RESP1) & SD_CARD_LOCKED)
01738   {
01739     errorstatus = SD_LOCK_UNLOCK_FAILED;
01740     return(errorstatus);
01741   }
01742
01743   /*!< Set block size for card if it is not equal to current block size for card. */
01744   SDIO_CmdInitStructure.SDIO_Argument = 64;
01745   SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SET_BLOCKLEN;
01746   SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
01747   SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
01748   SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
01749   SDIO_SendCommand(&SDIO_CmdInitStructure);
01750
01751   errorstatus = CmdResp1Error(SD_CMD_SET_BLOCKLEN);
01752
01753   if (errorstatus != SD_OK)
01754   {
01755     return(errorstatus);
01756   }
01757
01758   /*!< CMD55 */
01759   SDIO_CmdInitStructure.SDIO_Argument = (uint32_t) RCA << 16;
01760   SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_CMD;
01761   SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
01762   SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
01763   SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
01764   SDIO_SendCommand(&SDIO_CmdInitStructure);
01765   errorstatus = CmdResp1Error(SD_CMD_APP_CMD);
01766
01767   if (errorstatus != SD_OK)
01768   {
01769     return(errorstatus);
01770   }
01771
01772   SDIO_DataInitStructure.SDIO_DataTimeOut = SD_DATATIMEOUT;
01773   SDIO_DataInitStructure.SDIO_DataLength = 64;
01774   SDIO_DataInitStructure.SDIO_DataBlockSize = SDIO_DataBlockSize_64b;
01775   SDIO_DataInitStructure.SDIO_TransferDir = SDIO_TransferDir_ToSDIO;
01776   SDIO_DataInitStructure.SDIO_TransferMode = SDIO_TransferMode_Block;
01777   SDIO_DataInitStructure.SDIO_DPSM = SDIO_DPSM_Enable;
01778   SDIO_DataConfig(&SDIO_DataInitStructure);
01779
01780   /*!< Send ACMD13 SD_APP_STAUS  with argument as card's RCA.*/
01781   SDIO_CmdInitStructure.SDIO_Argument = 0;
01782   SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SD_APP_STAUS;
01783   SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
01784   SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
01785   SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
01786   SDIO_SendCommand(&SDIO_CmdInitStructure);
01787   errorstatus = CmdResp1Error(SD_CMD_SD_APP_STAUS);
01788
01789   if (errorstatus != SD_OK)
01790   {
01791     return(errorstatus);
01792   }
01793
01794   while (!(SDIO->STA &(SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR)))
01795   {
01796     if (SDIO_GetFlagStatus(SDIO_FLAG_RXFIFOHF) != RESET)
01797     {
01798       for (count = 0; count < 8; count++)
01799       {
01800         *(psdstatus + count) = SDIO_ReadData();
01801       }
01802       psdstatus += 8;
01803     }
01804   }
01805
01806   if (SDIO_GetFlagStatus(SDIO_FLAG_DTIMEOUT) != RESET)
01807   {
01808     SDIO_ClearFlag(SDIO_FLAG_DTIMEOUT);
01809     errorstatus = SD_DATA_TIMEOUT;
01810     return(errorstatus);
01811   }
01812   else if (SDIO_GetFlagStatus(SDIO_FLAG_DCRCFAIL) != RESET)
01813   {
01814     SDIO_ClearFlag(SDIO_FLAG_DCRCFAIL);
01815     errorstatus = SD_DATA_CRC_FAIL;
01816     return(errorstatus);
01817   }
01818   else if (SDIO_GetFlagStatus(SDIO_FLAG_RXOVERR) != RESET)
01819   {
01820     SDIO_ClearFlag(SDIO_FLAG_RXOVERR);
01821     errorstatus = SD_RX_OVERRUN;
01822     return(errorstatus);
01823   }
01824   else if (SDIO_GetFlagStatus(SDIO_FLAG_STBITERR) != RESET)
01825   {
01826     SDIO_ClearFlag(SDIO_FLAG_STBITERR);
01827     errorstatus = SD_START_BIT_ERR;
01828     return(errorstatus);
01829   }
01830
01831   while (SDIO_GetFlagStatus(SDIO_FLAG_RXDAVL) != RESET)
01832   {
01833     *psdstatus = SDIO_ReadData();
01834     psdstatus++;
01835   }
01836
01837   /*!< Clear all the static status flags*/
01838   SDIO_ClearFlag(SDIO_STATIC_FLAGS);
01839
01840   return(errorstatus);
01841 }
01842
01843 /**
01844   * @brief  Allows to process all the interrupts that are high.
01845   * @param  None
01846   * @retval SD_Error: SD Card Error code.
01847   */
01848 SD_Error SD_ProcessIRQSrc(void)
01849 {
01850   if (StopCondition == 1)
01851   {
01852     SDIO->ARG = 0x0;
01853     SDIO->CMD = 0x44C;
01854     TransferError = CmdResp1Error(SD_CMD_STOP_TRANSMISSION);
01855   }
01856   else
01857   {
01858     TransferError = SD_OK;
01859   }
01860   SDIO_ClearITPendingBit(SDIO_IT_DATAEND);
01861   SDIO_ITConfig(SDIO_IT_DATAEND, DISABLE);
01862   TransferEnd = 1;
01863   return(TransferError);
01864 }
01865
01866 /**
01867   * @brief  Checks for error conditions for CMD0.
01868   * @param  None
01869   * @retval SD_Error: SD Card Error code.
01870   */
01871 static SD_Error CmdError(void)
01872 {
01873   SD_Error errorstatus = SD_OK;
01874   uint32_t timeout;
01875
01876   timeout = SDIO_CMD0TIMEOUT; /*!< 10000 */
01877
01878   while ((timeout > 0) && (SDIO_GetFlagStatus(SDIO_FLAG_CMDSENT) == RESET))
01879   {
01880     timeout--;
01881   }
01882
01883   if (timeout == 0)
01884   {
01885     errorstatus = SD_CMD_RSP_TIMEOUT;
01886     return(errorstatus);
01887   }
01888
01889   /*!< Clear all the static flags */
01890   SDIO_ClearFlag(SDIO_STATIC_FLAGS);
01891
01892   return(errorstatus);
01893 }
01894
01895 /**
01896   * @brief  Checks for error conditions for R7 response.
01897   * @param  None
01898   * @retval SD_Error: SD Card Error code.
01899   */
01900 static SD_Error CmdResp7Error(void)
01901 {
01902   SD_Error errorstatus = SD_OK;
01903   uint32_t status;
01904   uint32_t timeout = SDIO_CMD0TIMEOUT;
01905
01906   status = SDIO->STA;
01907
01908   while (!(status & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) && (timeout > 0))
01909   {
01910     timeout--;
01911     status = SDIO->STA;
01912   }
01913
01914   if ((timeout == 0) || (status & SDIO_FLAG_CTIMEOUT))
01915   {
01916     /*!< Card is not V2.0 complient or card does not support the set voltage range */
01917     errorstatus = SD_CMD_RSP_TIMEOUT;
01918     SDIO_ClearFlag(SDIO_FLAG_CTIMEOUT);
01919     return(errorstatus);
01920   }
01921
01922   if (status & SDIO_FLAG_CMDREND)
01923   {
01924     /*!< Card is SD V2.0 compliant */
01925     errorstatus = SD_OK;
01926     SDIO_ClearFlag(SDIO_FLAG_CMDREND);
01927     return(errorstatus);
01928   }
01929   return(errorstatus);
01930 }
01931
01932 /**
01933   * @brief  Checks for error conditions for R1 response.
01934   * @param  cmd: The sent command index.
01935   * @retval SD_Error: SD Card Error code.
01936   */
01937 static SD_Error CmdResp1Error(uint8_t cmd)
01938 {
01939   while (!(SDIO->STA & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)))
01940   {
01941   }
01942
01943   SDIO->ICR = SDIO_STATIC_FLAGS;
01944
01945   return (SD_Error)(SDIO->RESP1 &  SD_OCR_ERRORBITS);
01946 }
01947
01948 /**
01949   * @brief  Checks for error conditions for R3 (OCR) response.
01950   * @param  None
01951   * @retval SD_Error: SD Card Error code.
01952   */
01953 static SD_Error CmdResp3Error(void)
01954 {
01955   SD_Error errorstatus = SD_OK;
01956   uint32_t status;
01957
01958   status = SDIO->STA;
01959
01960   while (!(status & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)))
01961   {
01962     status = SDIO->STA;
01963   }
01964
01965   if (status & SDIO_FLAG_CTIMEOUT)
01966   {
01967     errorstatus = SD_CMD_RSP_TIMEOUT;
01968     SDIO_ClearFlag(SDIO_FLAG_CTIMEOUT);
01969     return(errorstatus);
01970   }
01971   /*!< Clear all the static flags */
01972   SDIO_ClearFlag(SDIO_STATIC_FLAGS);
01973   return(errorstatus);
01974 }
01975
01976 /**
01977   * @brief  Checks for error conditions for R2 (CID or CSD) response.
01978   * @param  None
01979   * @retval SD_Error: SD Card Error code.
01980   */
01981 static SD_Error CmdResp2Error(void)
01982 {
01983   SD_Error errorstatus = SD_OK;
01984   uint32_t status;
01985
01986   status = SDIO->STA;
01987
01988   while (!(status & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CTIMEOUT | SDIO_FLAG_CMDREND)))
01989   {
01990     status = SDIO->STA;
01991   }
01992
01993   if (status & SDIO_FLAG_CTIMEOUT)
01994   {
01995     errorstatus = SD_CMD_RSP_TIMEOUT;
01996     SDIO_ClearFlag(SDIO_FLAG_CTIMEOUT);
01997     return(errorstatus);
01998   }
01999   else if (status & SDIO_FLAG_CCRCFAIL)
02000   {
02001     errorstatus = SD_CMD_CRC_FAIL;
02002     SDIO_ClearFlag(SDIO_FLAG_CCRCFAIL);
02003     return(errorstatus);
02004   }
02005
02006   /*!< Clear all the static flags */
02007   SDIO_ClearFlag(SDIO_STATIC_FLAGS);
02008
02009   return(errorstatus);
02010 }
02011
02012 /**
02013   * @brief  Checks for error conditions for R6 (RCA) response.
02014   * @param  cmd: The sent command index.
02015   * @param  prca: pointer to the variable that will contain the SD card relative
02016   *         address RCA.
02017   * @retval SD_Error: SD Card Error code.
02018   */
02019 static SD_Error CmdResp6Error(uint8_t cmd, uint16_t *prca)
02020 {
02021   SD_Error errorstatus = SD_OK;
02022   uint32_t status;
02023   uint32_t response_r1;
02024
02025   status = SDIO->STA;
02026
02027   while (!(status & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CTIMEOUT | SDIO_FLAG_CMDREND)))
02028   {
02029     status = SDIO->STA;
02030   }
02031
02032   if (status & SDIO_FLAG_CTIMEOUT)
02033   {
02034     errorstatus = SD_CMD_RSP_TIMEOUT;
02035     SDIO_ClearFlag(SDIO_FLAG_CTIMEOUT);
02036     return(errorstatus);
02037   }
02038   else if (status & SDIO_FLAG_CCRCFAIL)
02039   {
02040     errorstatus = SD_CMD_CRC_FAIL;
02041     SDIO_ClearFlag(SDIO_FLAG_CCRCFAIL);
02042     return(errorstatus);
02043   }
02044
02045   /*!< Check response received is of desired command */
02046   if (SDIO_GetCommandResponse() != cmd)
02047   {
02048     errorstatus = SD_ILLEGAL_CMD;
02049     return(errorstatus);
02050   }
02051
02052   /*!< Clear all the static flags */
02053   SDIO_ClearFlag(SDIO_STATIC_FLAGS);
02054
02055   /*!< We have received response, retrieve it.  */
02056   response_r1 = SDIO_GetResponse(SDIO_RESP1);
02057
02058   if (SD_ALLZERO == (response_r1 & (SD_R6_GENERAL_UNKNOWN_ERROR | SD_R6_ILLEGAL_CMD | SD_R6_COM_CRC_FAILED)))
02059   {
02060     *prca = (uint16_t) (response_r1 >> 16);
02061     return(errorstatus);
02062   }
02063
02064   if (response_r1 & SD_R6_GENERAL_UNKNOWN_ERROR)
02065   {
02066     return(SD_GENERAL_UNKNOWN_ERROR);
02067   }
02068
02069   if (response_r1 & SD_R6_ILLEGAL_CMD)
02070   {
02071     return(SD_ILLEGAL_CMD);
02072   }
02073
02074   if (response_r1 & SD_R6_COM_CRC_FAILED)
02075   {
02076     return(SD_COM_CRC_FAILED);
02077   }
02078
02079   return(errorstatus);
02080 }
02081
02082 /**
02083   * @brief  Enables or disables the SDIO wide bus mode.
02084   * @param  NewState: new state of the SDIO wide bus mode.
02085   *   This parameter can be: ENABLE or DISABLE.
02086   * @retval SD_Error: SD Card Error code.
02087   */
02088 static SD_Error SDEnWideBus(FunctionalState NewState)
02089 {
02090   SD_Error errorstatus = SD_OK;
02091
02092   uint32_t scr[2] = {0, 0};
02093
02094   if (SDIO_GetResponse(SDIO_RESP1) & SD_CARD_LOCKED)
02095   {
02096     errorstatus = SD_LOCK_UNLOCK_FAILED;
02097     return(errorstatus);
02098   }
02099
02100   /*!< Get SCR Register */
02101   errorstatus = FindSCR(RCA, scr);
02102
02103   if (errorstatus != SD_OK)
02104   {
02105     return(errorstatus);
02106   }
02107
02108   /*!< If wide bus operation to be enabled */
02109   if (NewState == ENABLE)
02110   {
02111     /*!< If requested card supports wide bus operation */
02112     if ((scr[1] & SD_WIDE_BUS_SUPPORT) != SD_ALLZERO)
02113     {
02114       /*!< Send CMD55 APP_CMD with argument as card's RCA.*/
02115       SDIO_CmdInitStructure.SDIO_Argument = (uint32_t) RCA << 16;
02116       SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_CMD;
02117       SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
02118       SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
02119       SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
02120       SDIO_SendCommand(&SDIO_CmdInitStructure);
02121
02122       errorstatus = CmdResp1Error(SD_CMD_APP_CMD);
02123
02124       if (errorstatus != SD_OK)
02125       {
02126         return(errorstatus);
02127       }
02128
02129       /*!< Send ACMD6 APP_CMD with argument as 2 for wide bus mode */
02130       SDIO_CmdInitStructure.SDIO_Argument = 0x2;
02131       SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_SD_SET_BUSWIDTH;
02132       SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
02133       SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
02134       SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
02135       SDIO_SendCommand(&SDIO_CmdInitStructure);
02136
02137       errorstatus = CmdResp1Error(SD_CMD_APP_SD_SET_BUSWIDTH);
02138
02139       if (errorstatus != SD_OK)
02140       {
02141         return(errorstatus);
02142       }
02143       return(errorstatus);
02144     }
02145     else
02146     {
02147       errorstatus = SD_REQUEST_NOT_APPLICABLE;
02148       return(errorstatus);
02149     }
02150   }   /*!< If wide bus operation to be disabled */
02151   else
02152   {
02153     /*!< If requested card supports 1 bit mode operation */
02154     if ((scr[1] & SD_SINGLE_BUS_SUPPORT) != SD_ALLZERO)
02155     {
02156       /*!< Send CMD55 APP_CMD with argument as card's RCA.*/
02157       SDIO_CmdInitStructure.SDIO_Argument = (uint32_t) RCA << 16;
02158       SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_CMD;
02159       SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
02160       SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
02161       SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
02162       SDIO_SendCommand(&SDIO_CmdInitStructure);
02163
02164
02165       errorstatus = CmdResp1Error(SD_CMD_APP_CMD);
02166
02167       if (errorstatus != SD_OK)
02168       {
02169         return(errorstatus);
02170       }
02171
02172       /*!< Send ACMD6 APP_CMD with argument as 2 for wide bus mode */
02173       SDIO_CmdInitStructure.SDIO_Argument = 0x00;
02174       SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_SD_SET_BUSWIDTH;
02175       SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
02176       SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
02177       SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
02178       SDIO_SendCommand(&SDIO_CmdInitStructure);
02179
02180       errorstatus = CmdResp1Error(SD_CMD_APP_SD_SET_BUSWIDTH);
02181
02182       if (errorstatus != SD_OK)
02183       {
02184         return(errorstatus);
02185       }
02186
02187       return(errorstatus);
02188     }
02189     else
02190     {
02191       errorstatus = SD_REQUEST_NOT_APPLICABLE;
02192       return(errorstatus);
02193     }
02194   }
02195 }
02196
02197 /**
02198   * @brief  Checks if the SD card is in programming state.
02199   * @param  pstatus: pointer to the variable that will contain the SD card state.
02200   * @retval SD_Error: SD Card Error code.
02201   */
02202 static SD_Error IsCardProgramming(uint8_t *pstatus)
02203 {
02204   SD_Error errorstatus = SD_OK;
02205   __IO uint32_t respR1 = 0, status = 0;
02206
02207   SDIO_CmdInitStructure.SDIO_Argument = (uint32_t) RCA << 16;
02208   SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SEND_STATUS;
02209   SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
02210   SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
02211   SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
02212   SDIO_SendCommand(&SDIO_CmdInitStructure);
02213
02214   status = SDIO->STA;
02215   while (!(status & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)))
02216   {
02217     status = SDIO->STA;
02218   }
02219
02220   if (status & SDIO_FLAG_CTIMEOUT)
02221   {
02222     errorstatus = SD_CMD_RSP_TIMEOUT;
02223     SDIO_ClearFlag(SDIO_FLAG_CTIMEOUT);
02224     return(errorstatus);
02225   }
02226   else if (status & SDIO_FLAG_CCRCFAIL)
02227   {
02228     errorstatus = SD_CMD_CRC_FAIL;
02229     SDIO_ClearFlag(SDIO_FLAG_CCRCFAIL);
02230     return(errorstatus);
02231   }
02232
02233   status = (uint32_t)SDIO_GetCommandResponse();
02234
02235   /*!< Check response received is of desired command */
02236   if (status != SD_CMD_SEND_STATUS)
02237   {
02238     errorstatus = SD_ILLEGAL_CMD;
02239     return(errorstatus);
02240   }
02241
02242   /*!< Clear all the static flags */
02243   SDIO_ClearFlag(SDIO_STATIC_FLAGS);
02244
02245
02246   /*!< We have received response, retrieve it for analysis  */
02247   respR1 = SDIO_GetResponse(SDIO_RESP1);
02248
02249   /*!< Find out card status */
02250   *pstatus = (uint8_t) ((respR1 >> 9) & 0x0000000F);
02251
02252   if ((respR1 & SD_OCR_ERRORBITS) == SD_ALLZERO)
02253   {
02254     return(errorstatus);
02255   }
02256
02257   if (respR1 & SD_OCR_ADDR_OUT_OF_RANGE)
02258   {
02259     return(SD_ADDR_OUT_OF_RANGE);
02260   }
02261
02262   if (respR1 & SD_OCR_ADDR_MISALIGNED)
02263   {
02264     return(SD_ADDR_MISALIGNED);
02265   }
02266
02267   if (respR1 & SD_OCR_BLOCK_LEN_ERR)
02268   {
02269     return(SD_BLOCK_LEN_ERR);
02270   }
02271
02272   if (respR1 & SD_OCR_ERASE_SEQ_ERR)
02273   {
02274     return(SD_ERASE_SEQ_ERR);
02275   }
02276
02277   if (respR1 & SD_OCR_BAD_ERASE_PARAM)
02278   {
02279     return(SD_BAD_ERASE_PARAM);
02280   }
02281
02282   if (respR1 & SD_OCR_WRITE_PROT_VIOLATION)
02283   {
02284     return(SD_WRITE_PROT_VIOLATION);
02285   }
02286
02287   if (respR1 & SD_OCR_LOCK_UNLOCK_FAILED)
02288   {
02289     return(SD_LOCK_UNLOCK_FAILED);
02290   }
02291
02292   if (respR1 & SD_OCR_COM_CRC_FAILED)
02293   {
02294     return(SD_COM_CRC_FAILED);
02295   }
02296
02297   if (respR1 & SD_OCR_ILLEGAL_CMD)
02298   {
02299     return(SD_ILLEGAL_CMD);
02300   }
02301
02302   if (respR1 & SD_OCR_CARD_ECC_FAILED)
02303   {
02304     return(SD_CARD_ECC_FAILED);
02305   }
02306
02307   if (respR1 & SD_OCR_CC_ERROR)
02308   {
02309     return(SD_CC_ERROR);
02310   }
02311
02312   if (respR1 & SD_OCR_GENERAL_UNKNOWN_ERROR)
02313   {
02314     return(SD_GENERAL_UNKNOWN_ERROR);
02315   }
02316
02317   if (respR1 & SD_OCR_STREAM_READ_UNDERRUN)
02318   {
02319     return(SD_STREAM_READ_UNDERRUN);
02320   }
02321
02322   if (respR1 & SD_OCR_STREAM_WRITE_OVERRUN)
02323   {
02324     return(SD_STREAM_WRITE_OVERRUN);
02325   }
02326
02327   if (respR1 & SD_OCR_CID_CSD_OVERWRIETE)
02328   {
02329     return(SD_CID_CSD_OVERWRITE);
02330   }
02331
02332   if (respR1 & SD_OCR_WP_ERASE_SKIP)
02333   {
02334     return(SD_WP_ERASE_SKIP);
02335   }
02336
02337   if (respR1 & SD_OCR_CARD_ECC_DISABLED)
02338   {
02339     return(SD_CARD_ECC_DISABLED);
02340   }
02341
02342   if (respR1 & SD_OCR_ERASE_RESET)
02343   {
02344     return(SD_ERASE_RESET);
02345   }
02346
02347   if (respR1 & SD_OCR_AKE_SEQ_ERROR)
02348   {
02349     return(SD_AKE_SEQ_ERROR);
02350   }
02351
02352   return(errorstatus);
02353 }
02354
02355 /**
02356   * @brief  Find the SD card SCR register value.
02357   * @param  rca: selected card address.
02358   * @param  pscr: pointer to the buffer that will contain the SCR value.
02359   * @retval SD_Error: SD Card Error code.
02360   */
02361 static SD_Error FindSCR(uint16_t rca, uint32_t *pscr)
02362 {
02363   uint32_t index = 0;
02364   SD_Error errorstatus = SD_OK;
02365   uint32_t tempscr[2] = {0, 0};
02366
02367   /*!< Set Block Size To 8 Bytes */
02368   /*!< Send CMD55 APP_CMD with argument as card's RCA */
02369   SDIO_CmdInitStructure.SDIO_Argument = (uint32_t)8;
02370   SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SET_BLOCKLEN;
02371   SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
02372   SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
02373   SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
02374   SDIO_SendCommand(&SDIO_CmdInitStructure);
02375
02376   errorstatus = CmdResp1Error(SD_CMD_SET_BLOCKLEN);
02377
02378   if (errorstatus != SD_OK)
02379   {
02380     return(errorstatus);
02381   }
02382
02383   /*!< Send CMD55 APP_CMD with argument as card's RCA */
02384   SDIO_CmdInitStructure.SDIO_Argument = (uint32_t) RCA << 16;
02385   SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_CMD;
02386   SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
02387   SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
02388   SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
02389   SDIO_SendCommand(&SDIO_CmdInitStructure);
02390
02391   errorstatus = CmdResp1Error(SD_CMD_APP_CMD);
02392
02393   if (errorstatus != SD_OK)
02394   {
02395     return(errorstatus);
02396   }
02397   SDIO_DataInitStructure.SDIO_DataTimeOut = SD_DATATIMEOUT;
02398   SDIO_DataInitStructure.SDIO_DataLength = 8;
02399   SDIO_DataInitStructure.SDIO_DataBlockSize = SDIO_DataBlockSize_8b;
02400   SDIO_DataInitStructure.SDIO_TransferDir = SDIO_TransferDir_ToSDIO;
02401   SDIO_DataInitStructure.SDIO_TransferMode = SDIO_TransferMode_Block;
02402   SDIO_DataInitStructure.SDIO_DPSM = SDIO_DPSM_Enable;
02403   SDIO_DataConfig(&SDIO_DataInitStructure);
02404
02405
02406   /*!< Send ACMD51 SD_APP_SEND_SCR with argument as 0 */
02407   SDIO_CmdInitStructure.SDIO_Argument = 0x0;
02408   SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SD_APP_SEND_SCR;
02409   SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
02410   SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
02411   SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
02412   SDIO_SendCommand(&SDIO_CmdInitStructure);
02413
02414   errorstatus = CmdResp1Error(SD_CMD_SD_APP_SEND_SCR);
02415
02416   if (errorstatus != SD_OK)
02417   {
02418     return(errorstatus);
02419   }
02420
02421   while (!(SDIO->STA & (SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR)))
02422   {
02423     if (SDIO_GetFlagStatus(SDIO_FLAG_RXDAVL) != RESET)
02424     {
02425       *(tempscr + index) = SDIO_ReadData();
02426       index++;
02427     }
02428   }
02429
02430   if (SDIO_GetFlagStatus(SDIO_FLAG_DTIMEOUT) != RESET)
02431   {
02432     SDIO_ClearFlag(SDIO_FLAG_DTIMEOUT);
02433     errorstatus = SD_DATA_TIMEOUT;
02434     return(errorstatus);
02435   }
02436   else if (SDIO_GetFlagStatus(SDIO_FLAG_DCRCFAIL) != RESET)
02437   {
02438     SDIO_ClearFlag(SDIO_FLAG_DCRCFAIL);
02439     errorstatus = SD_DATA_CRC_FAIL;
02440     return(errorstatus);
02441   }
02442   else if (SDIO_GetFlagStatus(SDIO_FLAG_RXOVERR) != RESET)
02443   {
02444     SDIO_ClearFlag(SDIO_FLAG_RXOVERR);
02445     errorstatus = SD_RX_OVERRUN;
02446     return(errorstatus);
02447   }
02448   else if (SDIO_GetFlagStatus(SDIO_FLAG_STBITERR) != RESET)
02449   {
02450     SDIO_ClearFlag(SDIO_FLAG_STBITERR);
02451     errorstatus = SD_START_BIT_ERR;
02452     return(errorstatus);
02453   }
02454
02455   /*!< Clear all the static flags */
02456   SDIO_ClearFlag(SDIO_STATIC_FLAGS);
02457
02458   *(pscr + 1) = ((tempscr[0] & SD_0TO7BITS) << 24) | ((tempscr[0] & SD_8TO15BITS) << 8) | ((tempscr[0] & SD_16TO23BITS) >> 8) | ((tempscr[0] & SD_24TO31BITS) >> 24);
02459
02460   *(pscr) = ((tempscr[1] & SD_0TO7BITS) << 24) | ((tempscr[1] & SD_8TO15BITS) << 8) | ((tempscr[1] & SD_16TO23BITS) >> 8) | ((tempscr[1] & SD_24TO31BITS) >> 24);
02461
02462   return(errorstatus);
02463 }
02464
02465 /**
02466   * @brief  Converts the number of bytes in power of two and returns the power.
02467   * @param  NumberOfBytes: number of bytes.
02468   * @retval None
02469   */
02470 uint8_t convert_from_bytes_to_power_of_two(uint16_t NumberOfBytes)
02471 {
02472   uint8_t count = 0;
02473
02474   while (NumberOfBytes != 1)
02475   {
02476     NumberOfBytes >>= 1;
02477     count++;
02478   }
02479   return(count);
02480 }
02481
02482 /**
02483   * @}
02484   */
02485
02486 /**
02487   * @}
02488   */
02489
02490 /**
02491   * @}
02492   */
02493
02494 /**
02495   * @}
02496   */
02497
02498 /**
02499   * @}
02500   */
02501
02502 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32_eval_sdio_sd.h Source File

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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • Common

stm32_eval_sdio_sd.h

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32_eval_sdio_sd.h
00004   * @author  MCD Application Team
00005   * @version V4.5.0
00006   * @date    07-March-2011
00007   * @brief   This file contains all the functions prototypes for the SD Card
00008   *          stm32_eval_sdio_sd driver firmware library.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00013   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00014   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00015   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00016   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00017   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00018   *
00019   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00020   ******************************************************************************
00021   */
00022
00023 /* Define to prevent recursive inclusion -------------------------------------*/
00024 #ifndef __STM32_EVAL_SDIO_SD_H
00025 #define __STM32_EVAL_SDIO_SD_H
00026
00027 #ifdef __cplusplus
00028  extern "C" {
00029 #endif
00030
00031 /* Includes ------------------------------------------------------------------*/
00032 #include "stm32_eval.h"
00033
00034 /** @addtogroup Utilities
00035   * @{
00036   */
00037
00038 /** @addtogroup STM32_EVAL
00039   * @{
00040   */
00041
00042 /** @addtogroup Common
00043   * @{
00044   */
00045
00046 /** @addtogroup STM32_EVAL_SDIO_SD
00047   * @{
00048   */
00049
00050 /** @defgroup STM32_EVAL_SDIO_SD_Exported_Types
00051   * @{
00052   */
00053 typedef enum
00054 {
00055 /**
00056   * @brief  SDIO specific error defines
00057   */
00058   SD_CMD_CRC_FAIL                    = (1), /*!< Command response received (but CRC check failed) */
00059   SD_DATA_CRC_FAIL                   = (2), /*!< Data bock sent/received (CRC check Failed) */
00060   SD_CMD_RSP_TIMEOUT                 = (3), /*!< Command response timeout */
00061   SD_DATA_TIMEOUT                    = (4), /*!< Data time out */
00062   SD_TX_UNDERRUN                     = (5), /*!< Transmit FIFO under-run */
00063   SD_RX_OVERRUN                      = (6), /*!< Receive FIFO over-run */
00064   SD_START_BIT_ERR                   = (7), /*!< Start bit not detected on all data signals in widE bus mode */
00065   SD_CMD_OUT_OF_RANGE                = (8), /*!< CMD's argument was out of range.*/
00066   SD_ADDR_MISALIGNED                 = (9), /*!< Misaligned address */
00067   SD_BLOCK_LEN_ERR                   = (10), /*!< Transferred block length is not allowed for the card or the number of transferred bytes does not match the block length */
00068   SD_ERASE_SEQ_ERR                   = (11), /*!< An error in the sequence of erase command occurs.*/
00069   SD_BAD_ERASE_PARAM                 = (12), /*!< An Invalid selection for erase groups */
00070   SD_WRITE_PROT_VIOLATION            = (13), /*!< Attempt to program a write protect block */
00071   SD_LOCK_UNLOCK_FAILED              = (14), /*!< Sequence or password error has been detected in unlock command or if there was an attempt to access a locked card */
00072   SD_COM_CRC_FAILED                  = (15), /*!< CRC check of the previous command failed */
00073   SD_ILLEGAL_CMD                     = (16), /*!< Command is not legal for the card state */
00074   SD_CARD_ECC_FAILED                 = (17), /*!< Card internal ECC was applied but failed to correct the data */
00075   SD_CC_ERROR                        = (18), /*!< Internal card controller error */
00076   SD_GENERAL_UNKNOWN_ERROR           = (19), /*!< General or Unknown error */
00077   SD_STREAM_READ_UNDERRUN            = (20), /*!< The card could not sustain data transfer in stream read operation. */
00078   SD_STREAM_WRITE_OVERRUN            = (21), /*!< The card could not sustain data programming in stream mode */
00079   SD_CID_CSD_OVERWRITE               = (22), /*!< CID/CSD overwrite error */
00080   SD_WP_ERASE_SKIP                   = (23), /*!< only partial address space was erased */
00081   SD_CARD_ECC_DISABLED               = (24), /*!< Command has been executed without using internal ECC */
00082   SD_ERASE_RESET                     = (25), /*!< Erase sequence was cleared before executing because an out of erase sequence command was received */
00083   SD_AKE_SEQ_ERROR                   = (26), /*!< Error in sequence of authentication. */
00084   SD_INVALID_VOLTRANGE               = (27),
00085   SD_ADDR_OUT_OF_RANGE               = (28),
00086   SD_SWITCH_ERROR                    = (29),
00087   SD_SDIO_DISABLED                   = (30),
00088   SD_SDIO_FUNCTION_BUSY              = (31),
00089   SD_SDIO_FUNCTION_FAILED            = (32),
00090   SD_SDIO_UNKNOWN_FUNCTION           = (33),
00091
00092 /**
00093   * @brief  Standard error defines
00094   */
00095   SD_INTERNAL_ERROR,
00096   SD_NOT_CONFIGURED,
00097   SD_REQUEST_PENDING,
00098   SD_REQUEST_NOT_APPLICABLE,
00099   SD_INVALID_PARAMETER,
00100   SD_UNSUPPORTED_FEATURE,
00101   SD_UNSUPPORTED_HW,
00102   SD_ERROR,
00103   SD_OK = 0
00104 } SD_Error;
00105
00106 /**
00107   * @brief  SDIO Transfer state
00108   */
00109 typedef enum
00110 {
00111   SD_TRANSFER_OK  = 0,
00112   SD_TRANSFER_BUSY = 1,
00113   SD_TRANSFER_ERROR
00114 } SDTransferState;
00115
00116 /**
00117   * @brief  SD Card States
00118   */
00119 typedef enum
00120 {
00121   SD_CARD_READY                  = ((uint32_t)0x00000001),
00122   SD_CARD_IDENTIFICATION         = ((uint32_t)0x00000002),
00123   SD_CARD_STANDBY                = ((uint32_t)0x00000003),
00124   SD_CARD_TRANSFER               = ((uint32_t)0x00000004),
00125   SD_CARD_SENDING                = ((uint32_t)0x00000005),
00126   SD_CARD_RECEIVING              = ((uint32_t)0x00000006),
00127   SD_CARD_PROGRAMMING            = ((uint32_t)0x00000007),
00128   SD_CARD_DISCONNECTED           = ((uint32_t)0x00000008),
00129   SD_CARD_ERROR                  = ((uint32_t)0x000000FF)
00130 }SDCardState;
00131
00132
00133 /**
00134   * @brief  Card Specific Data: CSD Register
00135   */
00136 typedef struct
00137 {
00138   __IO uint8_t  CSDStruct;            /*!< CSD structure */
00139   __IO uint8_t  SysSpecVersion;       /*!< System specification version */
00140   __IO uint8_t  Reserved1;            /*!< Reserved */
00141   __IO uint8_t  TAAC;                 /*!< Data read access-time 1 */
00142   __IO uint8_t  NSAC;                 /*!< Data read access-time 2 in CLK cycles */
00143   __IO uint8_t  MaxBusClkFrec;        /*!< Max. bus clock frequency */
00144   __IO uint16_t CardComdClasses;      /*!< Card command classes */
00145   __IO uint8_t  RdBlockLen;           /*!< Max. read data block length */
00146   __IO uint8_t  PartBlockRead;        /*!< Partial blocks for read allowed */
00147   __IO uint8_t  WrBlockMisalign;      /*!< Write block misalignment */
00148   __IO uint8_t  RdBlockMisalign;      /*!< Read block misalignment */
00149   __IO uint8_t  DSRImpl;              /*!< DSR implemented */
00150   __IO uint8_t  Reserved2;            /*!< Reserved */
00151   __IO uint32_t DeviceSize;           /*!< Device Size */
00152   __IO uint8_t  MaxRdCurrentVDDMin;   /*!< Max. read current @ VDD min */
00153   __IO uint8_t  MaxRdCurrentVDDMax;   /*!< Max. read current @ VDD max */
00154   __IO uint8_t  MaxWrCurrentVDDMin;   /*!< Max. write current @ VDD min */
00155   __IO uint8_t  MaxWrCurrentVDDMax;   /*!< Max. write current @ VDD max */
00156   __IO uint8_t  DeviceSizeMul;        /*!< Device size multiplier */
00157   __IO uint8_t  EraseGrSize;          /*!< Erase group size */
00158   __IO uint8_t  EraseGrMul;           /*!< Erase group size multiplier */
00159   __IO uint8_t  WrProtectGrSize;      /*!< Write protect group size */
00160   __IO uint8_t  WrProtectGrEnable;    /*!< Write protect group enable */
00161   __IO uint8_t  ManDeflECC;           /*!< Manufacturer default ECC */
00162   __IO uint8_t  WrSpeedFact;          /*!< Write speed factor */
00163   __IO uint8_t  MaxWrBlockLen;        /*!< Max. write data block length */
00164   __IO uint8_t  WriteBlockPaPartial;  /*!< Partial blocks for write allowed */
00165   __IO uint8_t  Reserved3;            /*!< Reserded */
00166   __IO uint8_t  ContentProtectAppli;  /*!< Content protection application */
00167   __IO uint8_t  FileFormatGrouop;     /*!< File format group */
00168   __IO uint8_t  CopyFlag;             /*!< Copy flag (OTP) */
00169   __IO uint8_t  PermWrProtect;        /*!< Permanent write protection */
00170   __IO uint8_t  TempWrProtect;        /*!< Temporary write protection */
00171   __IO uint8_t  FileFormat;           /*!< File Format */
00172   __IO uint8_t  ECC;                  /*!< ECC code */
00173   __IO uint8_t  CSD_CRC;              /*!< CSD CRC */
00174   __IO uint8_t  Reserved4;            /*!< always 1*/
00175 } SD_CSD;
00176
00177 /**
00178   * @brief  Card Identification Data: CID Register
00179   */
00180 typedef struct
00181 {
00182   __IO uint8_t  ManufacturerID;       /*!< ManufacturerID */
00183   __IO uint16_t OEM_AppliID;          /*!< OEM/Application ID */
00184   __IO uint32_t ProdName1;            /*!< Product Name part1 */
00185   __IO uint8_t  ProdName2;            /*!< Product Name part2*/
00186   __IO uint8_t  ProdRev;              /*!< Product Revision */
00187   __IO uint32_t ProdSN;               /*!< Product Serial Number */
00188   __IO uint8_t  Reserved1;            /*!< Reserved1 */
00189   __IO uint16_t ManufactDate;         /*!< Manufacturing Date */
00190   __IO uint8_t  CID_CRC;              /*!< CID CRC */
00191   __IO uint8_t  Reserved2;            /*!< always 1 */
00192 } SD_CID;
00193
00194 /**
00195   * @brief SD Card Status
00196   */
00197 typedef struct
00198 {
00199   __IO uint8_t DAT_BUS_WIDTH;
00200   __IO uint8_t SECURED_MODE;
00201   __IO uint16_t SD_CARD_TYPE;
00202   __IO uint32_t SIZE_OF_PROTECTED_AREA;
00203   __IO uint8_t SPEED_CLASS;
00204   __IO uint8_t PERFORMANCE_MOVE;
00205   __IO uint8_t AU_SIZE;
00206   __IO uint16_t ERASE_SIZE;
00207   __IO uint8_t ERASE_TIMEOUT;
00208   __IO uint8_t ERASE_OFFSET;
00209 } SD_CardStatus;
00210
00211
00212 /**
00213   * @brief SD Card information
00214   */
00215 typedef struct
00216 {
00217   SD_CSD SD_csd;
00218   SD_CID SD_cid;
00219   uint32_t CardCapacity;  /*!< Card Capacity */
00220   uint32_t CardBlockSize; /*!< Card Block Size */
00221   uint16_t RCA;
00222   uint8_t CardType;
00223 } SD_CardInfo;
00224
00225 /**
00226   * @}
00227   */
00228
00229 /** @defgroup STM32_EVAL_SDIO_SD_Exported_Constants
00230   * @{
00231   */
00232
00233 /**
00234   * @brief SDIO Commands  Index
00235   */
00236 #define SD_CMD_GO_IDLE_STATE                       ((uint8_t)0)
00237 #define SD_CMD_SEND_OP_COND                        ((uint8_t)1)
00238 #define SD_CMD_ALL_SEND_CID                        ((uint8_t)2)
00239 #define SD_CMD_SET_REL_ADDR                        ((uint8_t)3) /*!< SDIO_SEND_REL_ADDR for SD Card */
00240 #define SD_CMD_SET_DSR                             ((uint8_t)4)
00241 #define SD_CMD_SDIO_SEN_OP_COND                    ((uint8_t)5)
00242 #define SD_CMD_HS_SWITCH                           ((uint8_t)6)
00243 #define SD_CMD_SEL_DESEL_CARD                      ((uint8_t)7)
00244 #define SD_CMD_HS_SEND_EXT_CSD                     ((uint8_t)8)
00245 #define SD_CMD_SEND_CSD                            ((uint8_t)9)
00246 #define SD_CMD_SEND_CID                            ((uint8_t)10)
00247 #define SD_CMD_READ_DAT_UNTIL_STOP                 ((uint8_t)11) /*!< SD Card doesn't support it */
00248 #define SD_CMD_STOP_TRANSMISSION                   ((uint8_t)12)
00249 #define SD_CMD_SEND_STATUS                         ((uint8_t)13)
00250 #define SD_CMD_HS_BUSTEST_READ                     ((uint8_t)14)
00251 #define SD_CMD_GO_INACTIVE_STATE                   ((uint8_t)15)
00252 #define SD_CMD_SET_BLOCKLEN                        ((uint8_t)16)
00253 #define SD_CMD_READ_SINGLE_BLOCK                   ((uint8_t)17)
00254 #define SD_CMD_READ_MULT_BLOCK                     ((uint8_t)18)
00255 #define SD_CMD_HS_BUSTEST_WRITE                    ((uint8_t)19)
00256 #define SD_CMD_WRITE_DAT_UNTIL_STOP                ((uint8_t)20) /*!< SD Card doesn't support it */
00257 #define SD_CMD_SET_BLOCK_COUNT                     ((uint8_t)23) /*!< SD Card doesn't support it */
00258 #define SD_CMD_WRITE_SINGLE_BLOCK                  ((uint8_t)24)
00259 #define SD_CMD_WRITE_MULT_BLOCK                    ((uint8_t)25)
00260 #define SD_CMD_PROG_CID                            ((uint8_t)26) /*!< reserved for manufacturers */
00261 #define SD_CMD_PROG_CSD                            ((uint8_t)27)
00262 #define SD_CMD_SET_WRITE_PROT                      ((uint8_t)28)
00263 #define SD_CMD_CLR_WRITE_PROT                      ((uint8_t)29)
00264 #define SD_CMD_SEND_WRITE_PROT                     ((uint8_t)30)
00265 #define SD_CMD_SD_ERASE_GRP_START                  ((uint8_t)32) /*!< To set the address of the first write
00266                                                                   block to be erased. (For SD card only) */
00267 #define SD_CMD_SD_ERASE_GRP_END                    ((uint8_t)33) /*!< To set the address of the last write block of the
00268                                                                   continuous range to be erased. (For SD card only) */
00269 #define SD_CMD_ERASE_GRP_START                     ((uint8_t)35) /*!< To set the address of the first write block to be erased.
00270                                                                   (For MMC card only spec 3.31) */
00271
00272 #define SD_CMD_ERASE_GRP_END                       ((uint8_t)36) /*!< To set the address of the last write block of the
00273                                                                   continuous range to be erased. (For MMC card only spec 3.31) */
00274
00275 #define SD_CMD_ERASE                               ((uint8_t)38)
00276 #define SD_CMD_FAST_IO                             ((uint8_t)39) /*!< SD Card doesn't support it */
00277 #define SD_CMD_GO_IRQ_STATE                        ((uint8_t)40) /*!< SD Card doesn't support it */
00278 #define SD_CMD_LOCK_UNLOCK                         ((uint8_t)42)
00279 #define SD_CMD_APP_CMD                             ((uint8_t)55)
00280 #define SD_CMD_GEN_CMD                             ((uint8_t)56)
00281 #define SD_CMD_NO_CMD                              ((uint8_t)64)
00282
00283 /**
00284   * @brief Following commands are SD Card Specific commands.
00285   *        SDIO_APP_CMD should be sent before sending these commands.
00286   */
00287 #define SD_CMD_APP_SD_SET_BUSWIDTH                 ((uint8_t)6)  /*!< For SD Card only */
00288 #define SD_CMD_SD_APP_STAUS                        ((uint8_t)13) /*!< For SD Card only */
00289 #define SD_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS        ((uint8_t)22) /*!< For SD Card only */
00290 #define SD_CMD_SD_APP_OP_COND                      ((uint8_t)41) /*!< For SD Card only */
00291 #define SD_CMD_SD_APP_SET_CLR_CARD_DETECT          ((uint8_t)42) /*!< For SD Card only */
00292 #define SD_CMD_SD_APP_SEND_SCR                     ((uint8_t)51) /*!< For SD Card only */
00293 #define SD_CMD_SDIO_RW_DIRECT                      ((uint8_t)52) /*!< For SD I/O Card only */
00294 #define SD_CMD_SDIO_RW_EXTENDED                    ((uint8_t)53) /*!< For SD I/O Card only */
00295
00296 /**
00297   * @brief Following commands are SD Card Specific security commands.
00298   *        SDIO_APP_CMD should be sent before sending these commands.
00299   */
00300 #define SD_CMD_SD_APP_GET_MKB                      ((uint8_t)43) /*!< For SD Card only */
00301 #define SD_CMD_SD_APP_GET_MID                      ((uint8_t)44) /*!< For SD Card only */
00302 #define SD_CMD_SD_APP_SET_CER_RN1                  ((uint8_t)45) /*!< For SD Card only */
00303 #define SD_CMD_SD_APP_GET_CER_RN2                  ((uint8_t)46) /*!< For SD Card only */
00304 #define SD_CMD_SD_APP_SET_CER_RES2                 ((uint8_t)47) /*!< For SD Card only */
00305 #define SD_CMD_SD_APP_GET_CER_RES1                 ((uint8_t)48) /*!< For SD Card only */
00306 #define SD_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK   ((uint8_t)18) /*!< For SD Card only */
00307 #define SD_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK  ((uint8_t)25) /*!< For SD Card only */
00308 #define SD_CMD_SD_APP_SECURE_ERASE                 ((uint8_t)38) /*!< For SD Card only */
00309 #define SD_CMD_SD_APP_CHANGE_SECURE_AREA           ((uint8_t)49) /*!< For SD Card only */
00310 #define SD_CMD_SD_APP_SECURE_WRITE_MKB             ((uint8_t)48) /*!< For SD Card only */
00311
00312 /* Uncomment the following line to select the SDIO Data transfer mode */
00313 #define SD_DMA_MODE                                ((uint32_t)0x00000000)
00314 /*#define SD_POLLING_MODE                            ((uint32_t)0x00000002)*/
00315
00316 /**
00317   * @brief  SD detection on its memory slot
00318   */
00319 #define SD_PRESENT                                 ((uint8_t)0x01)
00320 #define SD_NOT_PRESENT                             ((uint8_t)0x00)
00321
00322 /**
00323   * @brief Supported SD Memory Cards
00324   */
00325 #define SDIO_STD_CAPACITY_SD_CARD_V1_1             ((uint32_t)0x00000000)
00326 #define SDIO_STD_CAPACITY_SD_CARD_V2_0             ((uint32_t)0x00000001)
00327 #define SDIO_HIGH_CAPACITY_SD_CARD                 ((uint32_t)0x00000002)
00328 #define SDIO_MULTIMEDIA_CARD                       ((uint32_t)0x00000003)
00329 #define SDIO_SECURE_DIGITAL_IO_CARD                ((uint32_t)0x00000004)
00330 #define SDIO_HIGH_SPEED_MULTIMEDIA_CARD            ((uint32_t)0x00000005)
00331 #define SDIO_SECURE_DIGITAL_IO_COMBO_CARD          ((uint32_t)0x00000006)
00332 #define SDIO_HIGH_CAPACITY_MMC_CARD                ((uint32_t)0x00000007)
00333
00334 /**
00335   * @}
00336   */
00337
00338 /** @defgroup STM32_EVAL_SDIO_SD_Exported_Macros
00339   * @{
00340   */
00341 /**
00342   * @}
00343   */
00344
00345 /** @defgroup STM32_EVAL_SDIO_SD_Exported_Functions
00346   * @{
00347   */
00348 void SD_DeInit(void);
00349 SD_Error SD_Init(void);
00350 SDTransferState SD_GetStatus(void);
00351 SDCardState SD_GetState(void);
00352 uint8_t SD_Detect(void);
00353 SD_Error SD_PowerON(void);
00354 SD_Error SD_PowerOFF(void);
00355 SD_Error SD_InitializeCards(void);
00356 SD_Error SD_GetCardInfo(SD_CardInfo *cardinfo);
00357 SD_Error SD_GetCardStatus(SD_CardStatus *cardstatus);
00358 SD_Error SD_EnableWideBusOperation(uint32_t WideMode);
00359 SD_Error SD_SelectDeselect(uint32_t addr);
00360 SD_Error SD_ReadBlock(uint8_t *readbuff, uint32_t ReadAddr, uint16_t BlockSize);
00361 SD_Error SD_ReadMultiBlocks(uint8_t *readbuff, uint32_t ReadAddr, uint16_t BlockSize, uint32_t NumberOfBlocks);
00362 SD_Error SD_WriteBlock(uint8_t *writebuff, uint32_t WriteAddr, uint16_t BlockSize);
00363 SD_Error SD_WriteMultiBlocks(uint8_t *writebuff, uint32_t WriteAddr, uint16_t BlockSize, uint32_t NumberOfBlocks);
00364 SDTransferState SD_GetTransferState(void);
00365 SD_Error SD_StopTransfer(void);
00366 SD_Error SD_Erase(uint32_t startaddr, uint32_t endaddr);
00367 SD_Error SD_SendStatus(uint32_t *pcardstatus);
00368 SD_Error SD_SendSDStatus(uint32_t *psdstatus);
00369 SD_Error SD_ProcessIRQSrc(void);
00370 SD_Error SD_WaitReadOperation(void);
00371 SD_Error SD_WaitWriteOperation(void);
00372 #ifdef __cplusplus
00373 }
00374 #endif
00375
00376 #endif /* __STM32_EVAL_SDIO_SD_H */
00377 /**
00378   * @}
00379   */
00380
00381 /**
00382   * @}
00383   */
00384
00385 /**
00386   * @}
00387   */
00388
00389 /**
00390   * @}
00391   */
00392
00393 /**
00394   * @}
00395   */
00396
00397 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32_eval_spi_flash.c Source File

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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • Common

stm32_eval_spi_flash.c

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32_eval_spi_flash.c
00004   * @author  MCD Application Team
00005   * @version V4.5.0
00006   * @date    07-March-2011
00007   * @brief   This file provides a set of functions needed to manage the SPI M25Pxxx
00008   *          FLASH memory mounted on STM32xx-EVAL board (refer to stm32_eval.h
00009   *          to know about the boards supporting this memory).
00010   *          It implements a high level communication layer for read and write
00011   *          from/to this memory. The needed STM32 hardware resources (SPI and
00012   *          GPIO) are defined in stm32xx_eval.h file, and the initialization is
00013   *          performed in sFLASH_LowLevel_Init() function declared in stm32xx_eval.c
00014   *          file.
00015   *          You can easily tailor this driver to any other development board,
00016   *          by just adapting the defines for hardware resources and
00017   *          sFLASH_LowLevel_Init() function.
00018   *
00019   *          +-----------------------------------------------------------+
00020   *          |                     Pin assignment                        |
00021   *          +-----------------------------+---------------+-------------+
00022   *          |  STM32 SPI Pins             |     sFLASH    |    Pin      |
00023   *          +-----------------------------+---------------+-------------+
00024   *          | sFLASH_CS_PIN               | ChipSelect(/S)|    1        |
00025   *          | sFLASH_SPI_MISO_PIN / MISO  |   DataOut(Q)  |    2        |
00026   *          |                             |   VCC         |    3 (3.3 V)|
00027   *          |                             |   GND         |    4 (0 V)  |
00028   *          | sFLASH_SPI_MOSI_PIN / MOSI  |   DataIn(D)   |    5        |
00029   *          | sFLASH_SPI_SCK_PIN / SCLK   |   Clock(C)    |    6        |
00030   *          |                             |    VCC        |    7 (3.3 V)|
00031   *          |                             |    VCC        |    8 (3.3 V)|
00032   *          +-----------------------------+---------------+-------------+
00033   ******************************************************************************
00034   * @attention
00035   *
00036   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00037   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00038   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00039   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00040   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00041   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00042   *
00043   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00044   ******************************************************************************
00045   */
00046
00047 /* Includes ------------------------------------------------------------------*/
00048 #include "stm32_eval_spi_flash.h"
00049
00050 /** @addtogroup Utilities
00051   * @{
00052   */
00053
00054 /** @addtogroup STM32_EVAL
00055   * @{
00056   */
00057
00058 /** @addtogroup Common
00059   * @{
00060   */
00061
00062 /** @addtogroup STM32_EVAL_SPI_FLASH
00063   * @brief      This file includes the M25Pxxx SPI FLASH driver of STM32-EVAL boards.
00064   * @{
00065   */
00066
00067 /** @defgroup STM32_EVAL_SPI_FLASH_Private_Types
00068   * @{
00069   */
00070 /**
00071   * @}
00072   */
00073
00074
00075 /** @defgroup STM32_EVAL_SPI_FLASH_Private_Defines
00076   * @{
00077   */
00078 /**
00079   * @}
00080   */
00081
00082 /** @defgroup STM32_EVAL_SPI_FLASH_Private_Macros
00083   * @{
00084   */
00085 /**
00086   * @}
00087   */
00088
00089
00090 /** @defgroup STM32_EVAL_SPI_FLASH_Private_Variables
00091   * @{
00092   */
00093 /**
00094   * @}
00095   */
00096
00097
00098 /** @defgroup STM32_EVAL_SPI_FLASH_Private_Function_Prototypes
00099   * @{
00100   */
00101 /**
00102   * @}
00103   */
00104
00105
00106 /** @defgroup STM32_EVAL_SPI_FLASH_Private_Functions
00107   * @{
00108   */
00109
00110 /**
00111   * @brief  DeInitializes the peripherals used by the SPI FLASH driver.
00112   * @param  None
00113   * @retval None
00114   */
00115 void sFLASH_DeInit(void)
00116 {
00117   sFLASH_LowLevel_DeInit();
00118 }
00119
00120 /**
00121   * @brief  Initializes the peripherals used by the SPI FLASH driver.
00122   * @param  None
00123   * @retval None
00124   */
00125 void sFLASH_Init(void)
00126 {
00127   SPI_InitTypeDef  SPI_InitStructure;
00128
00129   sFLASH_LowLevel_Init();
00130
00131   /*!< Deselect the FLASH: Chip Select high */
00132   sFLASH_CS_HIGH();
00133
00134   /*!< SPI configuration */
00135   SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
00136   SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
00137   SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
00138   SPI_InitStructure.SPI_CPOL = SPI_CPOL_High;
00139   SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge;
00140   SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
00141 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00142   SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
00143 #else
00144   SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_4;
00145 #endif
00146
00147   SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
00148   SPI_InitStructure.SPI_CRCPolynomial = 7;
00149   SPI_Init(sFLASH_SPI, &SPI_InitStructure);
00150
00151   /*!< Enable the sFLASH_SPI  */
00152   SPI_Cmd(sFLASH_SPI, ENABLE);
00153 }
00154
00155 /**
00156   * @brief  Erases the specified FLASH sector.
00157   * @param  SectorAddr: address of the sector to erase.
00158   * @retval None
00159   */
00160 void sFLASH_EraseSector(uint32_t SectorAddr)
00161 {
00162   /*!< Send write enable instruction */
00163   sFLASH_WriteEnable();
00164
00165   /*!< Sector Erase */
00166   /*!< Select the FLASH: Chip Select low */
00167   sFLASH_CS_LOW();
00168   /*!< Send Sector Erase instruction */
00169   sFLASH_SendByte(sFLASH_CMD_SE);
00170   /*!< Send SectorAddr high nibble address byte */
00171   sFLASH_SendByte((SectorAddr & 0xFF0000) >> 16);
00172   /*!< Send SectorAddr medium nibble address byte */
00173   sFLASH_SendByte((SectorAddr & 0xFF00) >> 8);
00174   /*!< Send SectorAddr low nibble address byte */
00175   sFLASH_SendByte(SectorAddr & 0xFF);
00176   /*!< Deselect the FLASH: Chip Select high */
00177   sFLASH_CS_HIGH();
00178
00179   /*!< Wait the end of Flash writing */
00180   sFLASH_WaitForWriteEnd();
00181 }
00182
00183 /**
00184   * @brief  Erases the entire FLASH.
00185   * @param  None
00186   * @retval None
00187   */
00188 void sFLASH_EraseBulk(void)
00189 {
00190   /*!< Send write enable instruction */
00191   sFLASH_WriteEnable();
00192
00193   /*!< Bulk Erase */
00194   /*!< Select the FLASH: Chip Select low */
00195   sFLASH_CS_LOW();
00196   /*!< Send Bulk Erase instruction  */
00197   sFLASH_SendByte(sFLASH_CMD_BE);
00198   /*!< Deselect the FLASH: Chip Select high */
00199   sFLASH_CS_HIGH();
00200
00201   /*!< Wait the end of Flash writing */
00202   sFLASH_WaitForWriteEnd();
00203 }
00204
00205 /**
00206   * @brief  Writes more than one byte to the FLASH with a single WRITE cycle
00207   *         (Page WRITE sequence).
00208   * @note   The number of byte can't exceed the FLASH page size.
00209   * @param  pBuffer: pointer to the buffer  containing the data to be written
00210   *         to the FLASH.
00211   * @param  WriteAddr: FLASH's internal address to write to.
00212   * @param  NumByteToWrite: number of bytes to write to the FLASH, must be equal
00213   *         or less than "sFLASH_PAGESIZE" value.
00214   * @retval None
00215   */
00216 void sFLASH_WritePage(uint8_t* pBuffer, uint32_t WriteAddr, uint16_t NumByteToWrite)
00217 {
00218   /*!< Enable the write access to the FLASH */
00219   sFLASH_WriteEnable();
00220
00221   /*!< Select the FLASH: Chip Select low */
00222   sFLASH_CS_LOW();
00223   /*!< Send "Write to Memory " instruction */
00224   sFLASH_SendByte(sFLASH_CMD_WRITE);
00225   /*!< Send WriteAddr high nibble address byte to write to */
00226   sFLASH_SendByte((WriteAddr & 0xFF0000) >> 16);
00227   /*!< Send WriteAddr medium nibble address byte to write to */
00228   sFLASH_SendByte((WriteAddr & 0xFF00) >> 8);
00229   /*!< Send WriteAddr low nibble address byte to write to */
00230   sFLASH_SendByte(WriteAddr & 0xFF);
00231
00232   /*!< while there is data to be written on the FLASH */
00233   while (NumByteToWrite--)
00234   {
00235     /*!< Send the current byte */
00236     sFLASH_SendByte(*pBuffer);
00237     /*!< Point on the next byte to be written */
00238     pBuffer++;
00239   }
00240
00241   /*!< Deselect the FLASH: Chip Select high */
00242   sFLASH_CS_HIGH();
00243
00244   /*!< Wait the end of Flash writing */
00245   sFLASH_WaitForWriteEnd();
00246 }
00247
00248 /**
00249   * @brief  Writes block of data to the FLASH. In this function, the number of
00250   *         WRITE cycles are reduced, using Page WRITE sequence.
00251   * @param  pBuffer: pointer to the buffer  containing the data to be written
00252   *         to the FLASH.
00253   * @param  WriteAddr: FLASH's internal address to write to.
00254   * @param  NumByteToWrite: number of bytes to write to the FLASH.
00255   * @retval None
00256   */
00257 void sFLASH_WriteBuffer(uint8_t* pBuffer, uint32_t WriteAddr, uint16_t NumByteToWrite)
00258 {
00259   uint8_t NumOfPage = 0, NumOfSingle = 0, Addr = 0, count = 0, temp = 0;
00260
00261   Addr = WriteAddr % sFLASH_SPI_PAGESIZE;
00262   count = sFLASH_SPI_PAGESIZE - Addr;
00263   NumOfPage =  NumByteToWrite / sFLASH_SPI_PAGESIZE;
00264   NumOfSingle = NumByteToWrite % sFLASH_SPI_PAGESIZE;
00265
00266   if (Addr == 0) /*!< WriteAddr is sFLASH_PAGESIZE aligned  */
00267   {
00268     if (NumOfPage == 0) /*!< NumByteToWrite < sFLASH_PAGESIZE */
00269     {
00270       sFLASH_WritePage(pBuffer, WriteAddr, NumByteToWrite);
00271     }
00272     else /*!< NumByteToWrite > sFLASH_PAGESIZE */
00273     {
00274       while (NumOfPage--)
00275       {
00276         sFLASH_WritePage(pBuffer, WriteAddr, sFLASH_SPI_PAGESIZE);
00277         WriteAddr +=  sFLASH_SPI_PAGESIZE;
00278         pBuffer += sFLASH_SPI_PAGESIZE;
00279       }
00280
00281       sFLASH_WritePage(pBuffer, WriteAddr, NumOfSingle);
00282     }
00283   }
00284   else /*!< WriteAddr is not sFLASH_PAGESIZE aligned  */
00285   {
00286     if (NumOfPage == 0) /*!< NumByteToWrite < sFLASH_PAGESIZE */
00287     {
00288       if (NumOfSingle > count) /*!< (NumByteToWrite + WriteAddr) > sFLASH_PAGESIZE */
00289       {
00290         temp = NumOfSingle - count;
00291
00292         sFLASH_WritePage(pBuffer, WriteAddr, count);
00293         WriteAddr +=  count;
00294         pBuffer += count;
00295
00296         sFLASH_WritePage(pBuffer, WriteAddr, temp);
00297       }
00298       else
00299       {
00300         sFLASH_WritePage(pBuffer, WriteAddr, NumByteToWrite);
00301       }
00302     }
00303     else /*!< NumByteToWrite > sFLASH_PAGESIZE */
00304     {
00305       NumByteToWrite -= count;
00306       NumOfPage =  NumByteToWrite / sFLASH_SPI_PAGESIZE;
00307       NumOfSingle = NumByteToWrite % sFLASH_SPI_PAGESIZE;
00308
00309       sFLASH_WritePage(pBuffer, WriteAddr, count);
00310       WriteAddr +=  count;
00311       pBuffer += count;
00312
00313       while (NumOfPage--)
00314       {
00315         sFLASH_WritePage(pBuffer, WriteAddr, sFLASH_SPI_PAGESIZE);
00316         WriteAddr +=  sFLASH_SPI_PAGESIZE;
00317         pBuffer += sFLASH_SPI_PAGESIZE;
00318       }
00319
00320       if (NumOfSingle != 0)
00321       {
00322         sFLASH_WritePage(pBuffer, WriteAddr, NumOfSingle);
00323       }
00324     }
00325   }
00326 }
00327
00328 /**
00329   * @brief  Reads a block of data from the FLASH.
00330   * @param  pBuffer: pointer to the buffer that receives the data read from the FLASH.
00331   * @param  ReadAddr: FLASH's internal address to read from.
00332   * @param  NumByteToRead: number of bytes to read from the FLASH.
00333   * @retval None
00334   */
00335 void sFLASH_ReadBuffer(uint8_t* pBuffer, uint32_t ReadAddr, uint16_t NumByteToRead)
00336 {
00337   /*!< Select the FLASH: Chip Select low */
00338   sFLASH_CS_LOW();
00339
00340   /*!< Send "Read from Memory " instruction */
00341   sFLASH_SendByte(sFLASH_CMD_READ);
00342
00343   /*!< Send ReadAddr high nibble address byte to read from */
00344   sFLASH_SendByte((ReadAddr & 0xFF0000) >> 16);
00345   /*!< Send ReadAddr medium nibble address byte to read from */
00346   sFLASH_SendByte((ReadAddr& 0xFF00) >> 8);
00347   /*!< Send ReadAddr low nibble address byte to read from */
00348   sFLASH_SendByte(ReadAddr & 0xFF);
00349
00350   while (NumByteToRead--) /*!< while there is data to be read */
00351   {
00352     /*!< Read a byte from the FLASH */
00353     *pBuffer = sFLASH_SendByte(sFLASH_DUMMY_BYTE);
00354     /*!< Point to the next location where the byte read will be saved */
00355     pBuffer++;
00356   }
00357
00358   /*!< Deselect the FLASH: Chip Select high */
00359   sFLASH_CS_HIGH();
00360 }
00361
00362 /**
00363   * @brief  Reads FLASH identification.
00364   * @param  None
00365   * @retval FLASH identification
00366   */
00367 uint32_t sFLASH_ReadID(void)
00368 {
00369   uint32_t Temp = 0, Temp0 = 0, Temp1 = 0, Temp2 = 0;
00370
00371   /*!< Select the FLASH: Chip Select low */
00372   sFLASH_CS_LOW();
00373
00374   /*!< Send "RDID " instruction */
00375   sFLASH_SendByte(0x9F);
00376
00377   /*!< Read a byte from the FLASH */
00378   Temp0 = sFLASH_SendByte(sFLASH_DUMMY_BYTE);
00379
00380   /*!< Read a byte from the FLASH */
00381   Temp1 = sFLASH_SendByte(sFLASH_DUMMY_BYTE);
00382
00383   /*!< Read a byte from the FLASH */
00384   Temp2 = sFLASH_SendByte(sFLASH_DUMMY_BYTE);
00385
00386   /*!< Deselect the FLASH: Chip Select high */
00387   sFLASH_CS_HIGH();
00388
00389   Temp = (Temp0 << 16) | (Temp1 << 8) | Temp2;
00390
00391   return Temp;
00392 }
00393
00394 /**
00395   * @brief  Initiates a read data byte (READ) sequence from the Flash.
00396   *   This is done by driving the /CS line low to select the device, then the READ
00397   *   instruction is transmitted followed by 3 bytes address. This function exit
00398   *   and keep the /CS line low, so the Flash still being selected. With this
00399   *   technique the whole content of the Flash is read with a single READ instruction.
00400   * @param  ReadAddr: FLASH's internal address to read from.
00401   * @retval None
00402   */
00403 void sFLASH_StartReadSequence(uint32_t ReadAddr)
00404 {
00405   /*!< Select the FLASH: Chip Select low */
00406   sFLASH_CS_LOW();
00407
00408   /*!< Send "Read from Memory " instruction */
00409   sFLASH_SendByte(sFLASH_CMD_READ);
00410
00411   /*!< Send the 24-bit address of the address to read from -------------------*/
00412   /*!< Send ReadAddr high nibble address byte */
00413   sFLASH_SendByte((ReadAddr & 0xFF0000) >> 16);
00414   /*!< Send ReadAddr medium nibble address byte */
00415   sFLASH_SendByte((ReadAddr& 0xFF00) >> 8);
00416   /*!< Send ReadAddr low nibble address byte */
00417   sFLASH_SendByte(ReadAddr & 0xFF);
00418 }
00419
00420 /**
00421   * @brief  Reads a byte from the SPI Flash.
00422   * @note   This function must be used only if the Start_Read_Sequence function
00423   *         has been previously called.
00424   * @param  None
00425   * @retval Byte Read from the SPI Flash.
00426   */
00427 uint8_t sFLASH_ReadByte(void)
00428 {
00429   return (sFLASH_SendByte(sFLASH_DUMMY_BYTE));
00430 }
00431
00432 /**
00433   * @brief  Sends a byte through the SPI interface and return the byte received
00434   *         from the SPI bus.
00435   * @param  byte: byte to send.
00436   * @retval The value of the received byte.
00437   */
00438 uint8_t sFLASH_SendByte(uint8_t byte)
00439 {
00440   /*!< Loop while DR register in not emplty */
00441   while (SPI_I2S_GetFlagStatus(sFLASH_SPI, SPI_I2S_FLAG_TXE) == RESET);
00442
00443   /*!< Send byte through the SPI1 peripheral */
00444   SPI_I2S_SendData(sFLASH_SPI, byte);
00445
00446   /*!< Wait to receive a byte */
00447   while (SPI_I2S_GetFlagStatus(sFLASH_SPI, SPI_I2S_FLAG_RXNE) == RESET);
00448
00449   /*!< Return the byte read from the SPI bus */
00450   return SPI_I2S_ReceiveData(sFLASH_SPI);
00451 }
00452
00453 /**
00454   * @brief  Sends a Half Word through the SPI interface and return the Half Word
00455   *         received from the SPI bus.
00456   * @param  HalfWord: Half Word to send.
00457   * @retval The value of the received Half Word.
00458   */
00459 uint16_t sFLASH_SendHalfWord(uint16_t HalfWord)
00460 {
00461   /*!< Loop while DR register in not emplty */
00462   while (SPI_I2S_GetFlagStatus(sFLASH_SPI, SPI_I2S_FLAG_TXE) == RESET);
00463
00464   /*!< Send Half Word through the sFLASH peripheral */
00465   SPI_I2S_SendData(sFLASH_SPI, HalfWord);
00466
00467   /*!< Wait to receive a Half Word */
00468   while (SPI_I2S_GetFlagStatus(sFLASH_SPI, SPI_I2S_FLAG_RXNE) == RESET);
00469
00470   /*!< Return the Half Word read from the SPI bus */
00471   return SPI_I2S_ReceiveData(sFLASH_SPI);
00472 }
00473
00474 /**
00475   * @brief  Enables the write access to the FLASH.
00476   * @param  None
00477   * @retval None
00478   */
00479 void sFLASH_WriteEnable(void)
00480 {
00481   /*!< Select the FLASH: Chip Select low */
00482   sFLASH_CS_LOW();
00483
00484   /*!< Send "Write Enable" instruction */
00485   sFLASH_SendByte(sFLASH_CMD_WREN);
00486
00487   /*!< Deselect the FLASH: Chip Select high */
00488   sFLASH_CS_HIGH();
00489 }
00490
00491 /**
00492   * @brief  Polls the status of the Write In Progress (WIP) flag in the FLASH's
00493   *         status register and loop until write opertaion has completed.
00494   * @param  None
00495   * @retval None
00496   */
00497 void sFLASH_WaitForWriteEnd(void)
00498 {
00499   uint8_t flashstatus = 0;
00500
00501   /*!< Select the FLASH: Chip Select low */
00502   sFLASH_CS_LOW();
00503
00504   /*!< Send "Read Status Register" instruction */
00505   sFLASH_SendByte(sFLASH_CMD_RDSR);
00506
00507   /*!< Loop as long as the memory is busy with a write cycle */
00508   do
00509   {
00510     /*!< Send a dummy byte to generate the clock needed by the FLASH
00511     and put the value of the status register in FLASH_Status variable */
00512     flashstatus = sFLASH_SendByte(sFLASH_DUMMY_BYTE);
00513
00514   }
00515   while ((flashstatus & sFLASH_WIP_FLAG) == SET); /* Write in progress */
00516
00517   /*!< Deselect the FLASH: Chip Select high */
00518   sFLASH_CS_HIGH();
00519 }
00520
00521 /**
00522   * @}
00523   */
00524
00525 /**
00526   * @}
00527   */
00528
00529 /**
00530   * @}
00531   */
00532
00533 /**
00534   * @}
00535   */
00536
00537 /**
00538   * @}
00539   */
00540
00541 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32_eval_spi_flash.h Source File

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • Common

stm32_eval_spi_flash.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32_eval_spi_flash.h
00004   * @author  MCD Application Team
00005   * @version V4.5.0
00006   * @date    07-March-2011
00007   * @brief   This file contains all the functions prototypes for the stm32_eval_spi_flash
00008   *          firmware driver.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00013   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00014   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00015   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00016   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00017   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00018   *
00019   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00020   ******************************************************************************
00021   */
00022
00023 /* Define to prevent recursive inclusion -------------------------------------*/
00024 #ifndef __STM32_EVAL_SPI_FLASH_H
00025 #define __STM32_EVAL_SPI_FLASH_H
00026
00027 #ifdef __cplusplus
00028  extern "C" {
00029 #endif
00030
00031 /* Includes ------------------------------------------------------------------*/
00032 #include "stm32_eval.h"
00033
00034 /** @addtogroup Utilities
00035   * @{
00036   */
00037
00038 /** @addtogroup STM32_EVAL
00039   * @{
00040   */
00041
00042 /** @addtogroup Common
00043   * @{
00044   */
00045
00046 /** @addtogroup STM32_EVAL_SPI_FLASH
00047   * @{
00048   */
00049
00050 /** @defgroup STM32_EVAL_SPI_FLASH_Exported_Types
00051   * @{
00052   */
00053 /**
00054   * @}
00055   */
00056
00057 /** @defgroup STM32_EVAL_SPI_FLASH_Exported_Constants
00058   * @{
00059   */
00060 /**
00061   * @brief  M25P SPI Flash supported commands
00062   */
00063 #define sFLASH_CMD_WRITE          0x02  /*!< Write to Memory instruction */
00064 #define sFLASH_CMD_WRSR           0x01  /*!< Write Status Register instruction */
00065 #define sFLASH_CMD_WREN           0x06  /*!< Write enable instruction */
00066 #define sFLASH_CMD_READ           0x03  /*!< Read from Memory instruction */
00067 #define sFLASH_CMD_RDSR           0x05  /*!< Read Status Register instruction  */
00068 #define sFLASH_CMD_RDID           0x9F  /*!< Read identification */
00069 #define sFLASH_CMD_SE             0xD8  /*!< Sector Erase instruction */
00070 #define sFLASH_CMD_BE             0xC7  /*!< Bulk Erase instruction */
00071
00072 #define sFLASH_WIP_FLAG           0x01  /*!< Write In Progress (WIP) flag */
00073
00074 #define sFLASH_DUMMY_BYTE         0xA5
00075 #define sFLASH_SPI_PAGESIZE       0x100
00076
00077 #define sFLASH_M25P128_ID         0x202018
00078 #define sFLASH_M25P64_ID          0x202017
00079
00080 /**
00081   * @}
00082   */
00083
00084 /** @defgroup STM32_EVAL_SPI_FLASH_Exported_Macros
00085   * @{
00086   */
00087 /**
00088   * @brief  Select sFLASH: Chip Select pin low
00089   */
00090 #define sFLASH_CS_LOW()       GPIO_ResetBits(sFLASH_CS_GPIO_PORT, sFLASH_CS_PIN)
00091 /**
00092   * @brief  Deselect sFLASH: Chip Select pin high
00093   */
00094 #define sFLASH_CS_HIGH()      GPIO_SetBits(sFLASH_CS_GPIO_PORT, sFLASH_CS_PIN)
00095 /**
00096   * @}
00097   */
00098
00099
00100
00101 /** @defgroup STM32_EVAL_SPI_FLASH_Exported_Functions
00102   * @{
00103   */
00104 /**
00105   * @brief  High layer functions
00106   */
00107 void sFLASH_DeInit(void);
00108 void sFLASH_Init(void);
00109 void sFLASH_EraseSector(uint32_t SectorAddr);
00110 void sFLASH_EraseBulk(void);
00111 void sFLASH_WritePage(uint8_t* pBuffer, uint32_t WriteAddr, uint16_t NumByteToWrite);
00112 void sFLASH_WriteBuffer(uint8_t* pBuffer, uint32_t WriteAddr, uint16_t NumByteToWrite);
00113 void sFLASH_ReadBuffer(uint8_t* pBuffer, uint32_t ReadAddr, uint16_t NumByteToRead);
00114 uint32_t sFLASH_ReadID(void);
00115 void sFLASH_StartReadSequence(uint32_t ReadAddr);
00116
00117 /**
00118   * @brief  Low layer functions
00119   */
00120 uint8_t sFLASH_ReadByte(void);
00121 uint8_t sFLASH_SendByte(uint8_t byte);
00122 uint16_t sFLASH_SendHalfWord(uint16_t HalfWord);
00123 void sFLASH_WriteEnable(void);
00124 void sFLASH_WaitForWriteEnd(void);
00125
00126 #ifdef __cplusplus
00127 }
00128 #endif
00129
00130 #endif /* __STM32_EVAL_SPI_FLASH_H */
00131 /**
00132   * @}
00133   */
00134
00135 /**
00136   * @}
00137   */
00138
00139 /**
00140   * @}
00141   */
00142
00143 /**
00144   * @}
00145   */
00146
00147 /**
00148   * @}
00149   */
00150
00151 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32_eval_spi_sd.c Source File

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • Common

stm32_eval_spi_sd.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32_eval_spi_sd.c
00004   * @author  MCD Application Team
00005   * @version V4.5.0
00006   * @date    07-March-2011
00007   * @brief   This file provides a set of functions needed to manage the SPI SD
00008   *          Card memory mounted on STM32xx-EVAL board (refer to stm32_eval.h
00009   *          to know about the boards supporting this memory).
00010   *          It implements a high level communication layer for read and write
00011   *          from/to this memory. The needed STM32 hardware resources (SPI and
00012   *          GPIO) are defined in stm32xx_eval.h file, and the initialization is
00013   *          performed in SD_LowLevel_Init() function declared in stm32xx_eval.c
00014   *          file.
00015   *          You can easily tailor this driver to any other development board,
00016   *          by just adapting the defines for hardware resources and
00017   *          SD_LowLevel_Init() function.
00018   *
00019   *          +-------------------------------------------------------+
00020   *          |                     Pin assignment                    |
00021   *          +-------------------------+---------------+-------------+
00022   *          |  STM32 SPI Pins         |     SD        |    Pin      |
00023   *          +-------------------------+---------------+-------------+
00024   *          | SD_SPI_CS_PIN           |   ChipSelect  |    1        |
00025   *          | SD_SPI_MOSI_PIN / MOSI  |   DataIn      |    2        |
00026   *          |                         |   GND         |    3 (0 V)  |
00027   *          |                         |   VDD         |    4 (3.3 V)|
00028   *          | SD_SPI_SCK_PIN / SCLK   |   Clock       |    5        |
00029   *          |                         |   GND         |    6 (0 V)  |
00030   *          | SD_SPI_MISO_PIN / MISO  |   DataOut     |    7        |
00031   *          +-------------------------+---------------+-------------+
00032   ******************************************************************************
00033   * @attention
00034   *
00035   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00036   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00037   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00038   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00039   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00040   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00041   *
00042   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00043   ******************************************************************************
00044   */
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32_eval_spi_sd.h"
00048
00049 /** @addtogroup Utilities
00050   * @{
00051   */
00052
00053 /** @addtogroup STM32_EVAL
00054   * @{
00055   */
00056
00057 /** @addtogroup Common
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32_EVAL_SPI_SD
00062   * @brief      This file includes the SD card driver of STM32-EVAL boards.
00063   * @{
00064   */
00065
00066 /** @defgroup STM32_EVAL_SPI_SD_Private_Types
00067   * @{
00068   */
00069 /**
00070   * @}
00071   */
00072
00073
00074 /** @defgroup STM32_EVAL_SPI_SD_Private_Defines
00075   * @{
00076   */
00077 /**
00078   * @}
00079   */
00080
00081 /** @defgroup STM32_EVAL_SPI_SD_Private_Macros
00082   * @{
00083   */
00084 /**
00085   * @}
00086   */
00087
00088
00089 /** @defgroup STM32_EVAL_SPI_SD_Private_Variables
00090   * @{
00091   */
00092 /**
00093   * @}
00094   */
00095
00096
00097 /** @defgroup STM32_EVAL_SPI_SD_Private_Function_Prototypes
00098   * @{
00099   */
00100 /**
00101   * @}
00102   */
00103
00104
00105 /** @defgroup STM32_EVAL_SPI_SD_Private_Functions
00106   * @{
00107   */
00108
00109 /**
00110   * @brief  DeInitializes the SD/SD communication.
00111   * @param  None
00112   * @retval None
00113   */
00114 void SD_DeInit(void)
00115 {
00116   SD_LowLevel_DeInit();
00117 }
00118
00119 /**
00120   * @brief  Initializes the SD/SD communication.
00121   * @param  None
00122   * @retval The SD Response:
00123   *         - SD_RESPONSE_FAILURE: Sequence failed
00124   *         - SD_RESPONSE_NO_ERROR: Sequence succeed
00125   */
00126 SD_Error SD_Init(void)
00127 {
00128   uint32_t i = 0;
00129
00130   /*!< Initialize SD_SPI */
00131   SD_LowLevel_Init();
00132
00133   /*!< SD chip select high */
00134   SD_CS_HIGH();
00135
00136   /*!< Send dummy byte 0xFF, 10 times with CS high */
00137   /*!< Rise CS and MOSI for 80 clocks cycles */
00138   for (i = 0; i <= 9; i++)
00139   {
00140     /*!< Send dummy byte 0xFF */
00141     SD_WriteByte(SD_DUMMY_BYTE);
00142   }
00143   /*------------Put SD in SPI mode--------------*/
00144   /*!< SD initialized and set to SPI mode properly */
00145   return (SD_GoIdleState());
00146 }
00147
00148 /**
00149  * @brief  Detect if SD card is correctly plugged in the memory slot.
00150  * @param  None
00151  * @retval Return if SD is detected or not
00152  */
00153 uint8_t SD_Detect(void)
00154 {
00155   __IO uint8_t status = SD_PRESENT;
00156
00157   /*!< Check GPIO to detect SD */
00158   if (GPIO_ReadInputData(SD_DETECT_GPIO_PORT) & SD_DETECT_PIN)
00159   {
00160     status = SD_NOT_PRESENT;
00161   }
00162   return status;
00163 }
00164
00165 /**
00166   * @brief  Returns information about specific card.
00167   * @param  cardinfo: pointer to a SD_CardInfo structure that contains all SD
00168   *         card information.
00169   * @retval The SD Response:
00170   *         - SD_RESPONSE_FAILURE: Sequence failed
00171   *         - SD_RESPONSE_NO_ERROR: Sequence succeed
00172   */
00173 SD_Error SD_GetCardInfo(SD_CardInfo *cardinfo)
00174 {
00175   SD_Error status = SD_RESPONSE_FAILURE;
00176
00177   status = SD_GetCSDRegister(&(cardinfo->SD_csd));
00178   status = SD_GetCIDRegister(&(cardinfo->SD_cid));
00179   cardinfo->CardCapacity = (cardinfo->SD_csd.DeviceSize + 1) ;
00180   cardinfo->CardCapacity *= (1 << (cardinfo->SD_csd.DeviceSizeMul + 2));
00181   cardinfo->CardBlockSize = 1 << (cardinfo->SD_csd.RdBlockLen);
00182   cardinfo->CardCapacity *= cardinfo->CardBlockSize;
00183
00184   /*!< Returns the reponse */
00185   return status;
00186 }
00187
00188 /**
00189   * @brief  Reads a block of data from the SD.
00190   * @param  pBuffer: pointer to the buffer that receives the data read from the
00191   *                  SD.
00192   * @param  ReadAddr: SD's internal address to read from.
00193   * @param  BlockSize: the SD card Data block size.
00194   * @retval The SD Response:
00195   *         - SD_RESPONSE_FAILURE: Sequence failed
00196   *         - SD_RESPONSE_NO_ERROR: Sequence succeed
00197   */
00198 SD_Error SD_ReadBlock(uint8_t* pBuffer, uint32_t ReadAddr, uint16_t BlockSize)
00199 {
00200   uint32_t i = 0;
00201   SD_Error rvalue = SD_RESPONSE_FAILURE;
00202
00203   /*!< SD chip select low */
00204   SD_CS_LOW();
00205
00206   /*!< Send CMD17 (SD_CMD_READ_SINGLE_BLOCK) to read one block */
00207   SD_SendCmd(SD_CMD_READ_SINGLE_BLOCK, ReadAddr, 0xFF);
00208
00209   /*!< Check if the SD acknowledged the read block command: R1 response (0x00: no errors) */
00210   if (!SD_GetResponse(SD_RESPONSE_NO_ERROR))
00211   {
00212     /*!< Now look for the data token to signify the start of the data */
00213     if (!SD_GetResponse(SD_START_DATA_SINGLE_BLOCK_READ))
00214     {
00215       /*!< Read the SD block data : read NumByteToRead data */
00216       for (i = 0; i < BlockSize; i++)
00217       {
00218         /*!< Save the received data */
00219         *pBuffer = SD_ReadByte();
00220
00221         /*!< Point to the next location where the byte read will be saved */
00222         pBuffer++;
00223       }
00224       /*!< Get CRC bytes (not really needed by us, but required by SD) */
00225       SD_ReadByte();
00226       SD_ReadByte();
00227       /*!< Set response value to success */
00228       rvalue = SD_RESPONSE_NO_ERROR;
00229     }
00230   }
00231   /*!< SD chip select high */
00232   SD_CS_HIGH();
00233
00234   /*!< Send dummy byte: 8 Clock pulses of delay */
00235   SD_WriteByte(SD_DUMMY_BYTE);
00236
00237   /*!< Returns the reponse */
00238   return rvalue;
00239 }
00240
00241 /**
00242   * @brief  Reads multiple block of data from the SD.
00243   * @param  pBuffer: pointer to the buffer that receives the data read from the
00244   *                  SD.
00245   * @param  ReadAddr: SD's internal address to read from.
00246   * @param  BlockSize: the SD card Data block size.
00247   * @param  NumberOfBlocks: number of blocks to be read.
00248   * @retval The SD Response:
00249   *         - SD_RESPONSE_FAILURE: Sequence failed
00250   *         - SD_RESPONSE_NO_ERROR: Sequence succeed
00251   */
00252 SD_Error SD_ReadMultiBlocks(uint8_t* pBuffer, uint32_t ReadAddr, uint16_t BlockSize, uint32_t NumberOfBlocks)
00253 {
00254   uint32_t i = 0, Offset = 0;
00255   SD_Error rvalue = SD_RESPONSE_FAILURE;
00256
00257   /*!< SD chip select low */
00258   SD_CS_LOW();
00259   /*!< Data transfer */
00260   while (NumberOfBlocks--)
00261   {
00262     /*!< Send CMD17 (SD_CMD_READ_SINGLE_BLOCK) to read one block */
00263     SD_SendCmd (SD_CMD_READ_SINGLE_BLOCK, ReadAddr + Offset, 0xFF);
00264     /*!< Check if the SD acknowledged the read block command: R1 response (0x00: no errors) */
00265     if (SD_GetResponse(SD_RESPONSE_NO_ERROR))
00266     {
00267       return  SD_RESPONSE_FAILURE;
00268     }
00269     /*!< Now look for the data token to signify the start of the data */
00270     if (!SD_GetResponse(SD_START_DATA_SINGLE_BLOCK_READ))
00271     {
00272       /*!< Read the SD block data : read NumByteToRead data */
00273       for (i = 0; i < BlockSize; i++)
00274       {
00275         /*!< Read the pointed data */
00276         *pBuffer = SD_ReadByte();
00277         /*!< Point to the next location where the byte read will be saved */
00278         pBuffer++;
00279       }
00280       /*!< Set next read address*/
00281       Offset += 512;
00282       /*!< get CRC bytes (not really needed by us, but required by SD) */
00283       SD_ReadByte();
00284       SD_ReadByte();
00285       /*!< Set response value to success */
00286       rvalue = SD_RESPONSE_NO_ERROR;
00287     }
00288     else
00289     {
00290       /*!< Set response value to failure */
00291       rvalue = SD_RESPONSE_FAILURE;
00292     }
00293   }
00294   /*!< SD chip select high */
00295   SD_CS_HIGH();
00296   /*!< Send dummy byte: 8 Clock pulses of delay */
00297   SD_WriteByte(SD_DUMMY_BYTE);
00298   /*!< Returns the reponse */
00299   return rvalue;
00300 }
00301
00302 /**
00303   * @brief  Writes a block on the SD
00304   * @param  pBuffer: pointer to the buffer containing the data to be written on
00305   *                  the SD.
00306   * @param  WriteAddr: address to write on.
00307   * @param  BlockSize: the SD card Data block size.
00308   * @retval The SD Response:
00309   *         - SD_RESPONSE_FAILURE: Sequence failed
00310   *         - SD_RESPONSE_NO_ERROR: Sequence succeed
00311   */
00312 SD_Error SD_WriteBlock(uint8_t* pBuffer, uint32_t WriteAddr, uint16_t BlockSize)
00313 {
00314   uint32_t i = 0;
00315   SD_Error rvalue = SD_RESPONSE_FAILURE;
00316
00317   /*!< SD chip select low */
00318   SD_CS_LOW();
00319
00320   /*!< Send CMD24 (SD_CMD_WRITE_SINGLE_BLOCK) to write multiple block */
00321   SD_SendCmd(SD_CMD_WRITE_SINGLE_BLOCK, WriteAddr, 0xFF);
00322
00323   /*!< Check if the SD acknowledged the write block command: R1 response (0x00: no errors) */
00324   if (!SD_GetResponse(SD_RESPONSE_NO_ERROR))
00325   {
00326     /*!< Send a dummy byte */
00327     SD_WriteByte(SD_DUMMY_BYTE);
00328
00329     /*!< Send the data token to signify the start of the data */
00330     SD_WriteByte(0xFE);
00331
00332     /*!< Write the block data to SD : write count data by block */
00333     for (i = 0; i < BlockSize; i++)
00334     {
00335       /*!< Send the pointed byte */
00336       SD_WriteByte(*pBuffer);
00337       /*!< Point to the next location where the byte read will be saved */
00338       pBuffer++;
00339     }
00340     /*!< Put CRC bytes (not really needed by us, but required by SD) */
00341     SD_ReadByte();
00342     SD_ReadByte();
00343
00344     /*!< Read data response */
00345     if (SD_GetDataResponse() == SD_DATA_OK)
00346     {
00347       rvalue = SD_RESPONSE_NO_ERROR;
00348     }
00349   }
00350   /*!< SD chip select high */
00351   SD_CS_HIGH();
00352   /*!< Send dummy byte: 8 Clock pulses of delay */
00353   SD_WriteByte(SD_DUMMY_BYTE);
00354
00355   /*!< Returns the reponse */
00356   return rvalue;
00357 }
00358
00359 /**
00360   * @brief  Writes many blocks on the SD
00361   * @param  pBuffer: pointer to the buffer containing the data to be written on
00362   *                  the SD.
00363   * @param  WriteAddr: address to write on.
00364   * @param  BlockSize: the SD card Data block size.
00365   * @param  NumberOfBlocks: number of blocks to be written.
00366   * @retval The SD Response:
00367   *         - SD_RESPONSE_FAILURE: Sequence failed
00368   *         - SD_RESPONSE_NO_ERROR: Sequence succeed
00369   */
00370 SD_Error SD_WriteMultiBlocks(uint8_t* pBuffer, uint32_t WriteAddr, uint16_t BlockSize, uint32_t NumberOfBlocks)
00371 {
00372   uint32_t i = 0, Offset = 0;
00373   SD_Error rvalue = SD_RESPONSE_FAILURE;
00374
00375   /*!< SD chip select low */
00376   SD_CS_LOW();
00377   /*!< Data transfer */
00378   while (NumberOfBlocks--)
00379   {
00380     /*!< Send CMD24 (SD_CMD_WRITE_SINGLE_BLOCK) to write blocks */
00381     SD_SendCmd(SD_CMD_WRITE_SINGLE_BLOCK, WriteAddr + Offset, 0xFF);
00382     /*!< Check if the SD acknowledged the write block command: R1 response (0x00: no errors) */
00383     if (SD_GetResponse(SD_RESPONSE_NO_ERROR))
00384     {
00385       return SD_RESPONSE_FAILURE;
00386     }
00387     /*!< Send dummy byte */
00388     SD_WriteByte(SD_DUMMY_BYTE);
00389     /*!< Send the data token to signify the start of the data */
00390     SD_WriteByte(SD_START_DATA_SINGLE_BLOCK_WRITE);
00391     /*!< Write the block data to SD : write count data by block */
00392     for (i = 0; i < BlockSize; i++)
00393     {
00394       /*!< Send the pointed byte */
00395       SD_WriteByte(*pBuffer);
00396       /*!< Point to the next location where the byte read will be saved */
00397       pBuffer++;
00398     }
00399     /*!< Set next write address */
00400     Offset += 512;
00401     /*!< Put CRC bytes (not really needed by us, but required by SD) */
00402     SD_ReadByte();
00403     SD_ReadByte();
00404     /*!< Read data response */
00405     if (SD_GetDataResponse() == SD_DATA_OK)
00406     {
00407       /*!< Set response value to success */
00408       rvalue = SD_RESPONSE_NO_ERROR;
00409     }
00410     else
00411     {
00412       /*!< Set response value to failure */
00413       rvalue = SD_RESPONSE_FAILURE;
00414     }
00415   }
00416   /*!< SD chip select high */
00417   SD_CS_HIGH();
00418   /*!< Send dummy byte: 8 Clock pulses of delay */
00419   SD_WriteByte(SD_DUMMY_BYTE);
00420   /*!< Returns the reponse */
00421   return rvalue;
00422 }
00423
00424 /**
00425   * @brief  Read the CSD card register.
00426   *         Reading the contents of the CSD register in SPI mode is a simple
00427   *         read-block transaction.
00428   * @param  SD_csd: pointer on an SCD register structure
00429   * @retval The SD Response:
00430   *         - SD_RESPONSE_FAILURE: Sequence failed
00431   *         - SD_RESPONSE_NO_ERROR: Sequence succeed
00432   */
00433 SD_Error SD_GetCSDRegister(SD_CSD* SD_csd)
00434 {
00435   uint32_t i = 0;
00436   SD_Error rvalue = SD_RESPONSE_FAILURE;
00437   uint8_t CSD_Tab[16];
00438
00439   /*!< SD chip select low */
00440   SD_CS_LOW();
00441   /*!< Send CMD9 (CSD register) or CMD10(CSD register) */
00442   SD_SendCmd(SD_CMD_SEND_CSD, 0, 0xFF);
00443   /*!< Wait for response in the R1 format (0x00 is no errors) */
00444   if (!SD_GetResponse(SD_RESPONSE_NO_ERROR))
00445   {
00446     if (!SD_GetResponse(SD_START_DATA_SINGLE_BLOCK_READ))
00447     {
00448       for (i = 0; i < 16; i++)
00449       {
00450         /*!< Store CSD register value on CSD_Tab */
00451         CSD_Tab[i] = SD_ReadByte();
00452       }
00453     }
00454     /*!< Get CRC bytes (not really needed by us, but required by SD) */
00455     SD_WriteByte(SD_DUMMY_BYTE);
00456     SD_WriteByte(SD_DUMMY_BYTE);
00457     /*!< Set response value to success */
00458     rvalue = SD_RESPONSE_NO_ERROR;
00459   }
00460   /*!< SD chip select high */
00461   SD_CS_HIGH();
00462   /*!< Send dummy byte: 8 Clock pulses of delay */
00463   SD_WriteByte(SD_DUMMY_BYTE);
00464
00465   /*!< Byte 0 */
00466   SD_csd->CSDStruct = (CSD_Tab[0] & 0xC0) >> 6;
00467   SD_csd->SysSpecVersion = (CSD_Tab[0] & 0x3C) >> 2;
00468   SD_csd->Reserved1 = CSD_Tab[0] & 0x03;
00469
00470   /*!< Byte 1 */
00471   SD_csd->TAAC = CSD_Tab[1];
00472
00473   /*!< Byte 2 */
00474   SD_csd->NSAC = CSD_Tab[2];
00475
00476   /*!< Byte 3 */
00477   SD_csd->MaxBusClkFrec = CSD_Tab[3];
00478
00479   /*!< Byte 4 */
00480   SD_csd->CardComdClasses = CSD_Tab[4] << 4;
00481
00482   /*!< Byte 5 */
00483   SD_csd->CardComdClasses |= (CSD_Tab[5] & 0xF0) >> 4;
00484   SD_csd->RdBlockLen = CSD_Tab[5] & 0x0F;
00485
00486   /*!< Byte 6 */
00487   SD_csd->PartBlockRead = (CSD_Tab[6] & 0x80) >> 7;
00488   SD_csd->WrBlockMisalign = (CSD_Tab[6] & 0x40) >> 6;
00489   SD_csd->RdBlockMisalign = (CSD_Tab[6] & 0x20) >> 5;
00490   SD_csd->DSRImpl = (CSD_Tab[6] & 0x10) >> 4;
00491   SD_csd->Reserved2 = 0; /*!< Reserved */
00492
00493   SD_csd->DeviceSize = (CSD_Tab[6] & 0x03) << 10;
00494
00495   /*!< Byte 7 */
00496   SD_csd->DeviceSize |= (CSD_Tab[7]) << 2;
00497
00498   /*!< Byte 8 */
00499   SD_csd->DeviceSize |= (CSD_Tab[8] & 0xC0) >> 6;
00500
00501   SD_csd->MaxRdCurrentVDDMin = (CSD_Tab[8] & 0x38) >> 3;
00502   SD_csd->MaxRdCurrentVDDMax = (CSD_Tab[8] & 0x07);
00503
00504   /*!< Byte 9 */
00505   SD_csd->MaxWrCurrentVDDMin = (CSD_Tab[9] & 0xE0) >> 5;
00506   SD_csd->MaxWrCurrentVDDMax = (CSD_Tab[9] & 0x1C) >> 2;
00507   SD_csd->DeviceSizeMul = (CSD_Tab[9] & 0x03) << 1;
00508   /*!< Byte 10 */
00509   SD_csd->DeviceSizeMul |= (CSD_Tab[10] & 0x80) >> 7;
00510
00511   SD_csd->EraseGrSize = (CSD_Tab[10] & 0x40) >> 6;
00512   SD_csd->EraseGrMul = (CSD_Tab[10] & 0x3F) << 1;
00513
00514   /*!< Byte 11 */
00515   SD_csd->EraseGrMul |= (CSD_Tab[11] & 0x80) >> 7;
00516   SD_csd->WrProtectGrSize = (CSD_Tab[11] & 0x7F);
00517
00518   /*!< Byte 12 */
00519   SD_csd->WrProtectGrEnable = (CSD_Tab[12] & 0x80) >> 7;
00520   SD_csd->ManDeflECC = (CSD_Tab[12] & 0x60) >> 5;
00521   SD_csd->WrSpeedFact = (CSD_Tab[12] & 0x1C) >> 2;
00522   SD_csd->MaxWrBlockLen = (CSD_Tab[12] & 0x03) << 2;
00523
00524   /*!< Byte 13 */
00525   SD_csd->MaxWrBlockLen |= (CSD_Tab[13] & 0xC0) >> 6;
00526   SD_csd->WriteBlockPaPartial = (CSD_Tab[13] & 0x20) >> 5;
00527   SD_csd->Reserved3 = 0;
00528   SD_csd->ContentProtectAppli = (CSD_Tab[13] & 0x01);
00529
00530   /*!< Byte 14 */
00531   SD_csd->FileFormatGrouop = (CSD_Tab[14] & 0x80) >> 7;
00532   SD_csd->CopyFlag = (CSD_Tab[14] & 0x40) >> 6;
00533   SD_csd->PermWrProtect = (CSD_Tab[14] & 0x20) >> 5;
00534   SD_csd->TempWrProtect = (CSD_Tab[14] & 0x10) >> 4;
00535   SD_csd->FileFormat = (CSD_Tab[14] & 0x0C) >> 2;
00536   SD_csd->ECC = (CSD_Tab[14] & 0x03);
00537
00538   /*!< Byte 15 */
00539   SD_csd->CSD_CRC = (CSD_Tab[15] & 0xFE) >> 1;
00540   SD_csd->Reserved4 = 1;
00541
00542   /*!< Return the reponse */
00543   return rvalue;
00544 }
00545
00546 /**
00547   * @brief  Read the CID card register.
00548   *         Reading the contents of the CID register in SPI mode is a simple
00549   *         read-block transaction.
00550   * @param  SD_cid: pointer on an CID register structure
00551   * @retval The SD Response:
00552   *         - SD_RESPONSE_FAILURE: Sequence failed
00553   *         - SD_RESPONSE_NO_ERROR: Sequence succeed
00554   */
00555 SD_Error SD_GetCIDRegister(SD_CID* SD_cid)
00556 {
00557   uint32_t i = 0;
00558   SD_Error rvalue = SD_RESPONSE_FAILURE;
00559   uint8_t CID_Tab[16];
00560
00561   /*!< SD chip select low */
00562   SD_CS_LOW();
00563
00564   /*!< Send CMD10 (CID register) */
00565   SD_SendCmd(SD_CMD_SEND_CID, 0, 0xFF);
00566
00567   /*!< Wait for response in the R1 format (0x00 is no errors) */
00568   if (!SD_GetResponse(SD_RESPONSE_NO_ERROR))
00569   {
00570     if (!SD_GetResponse(SD_START_DATA_SINGLE_BLOCK_READ))
00571     {
00572       /*!< Store CID register value on CID_Tab */
00573       for (i = 0; i < 16; i++)
00574       {
00575         CID_Tab[i] = SD_ReadByte();
00576       }
00577     }
00578     /*!< Get CRC bytes (not really needed by us, but required by SD) */
00579     SD_WriteByte(SD_DUMMY_BYTE);
00580     SD_WriteByte(SD_DUMMY_BYTE);
00581     /*!< Set response value to success */
00582     rvalue = SD_RESPONSE_NO_ERROR;
00583   }
00584   /*!< SD chip select high */
00585   SD_CS_HIGH();
00586   /*!< Send dummy byte: 8 Clock pulses of delay */
00587   SD_WriteByte(SD_DUMMY_BYTE);
00588
00589   /*!< Byte 0 */
00590   SD_cid->ManufacturerID = CID_Tab[0];
00591
00592   /*!< Byte 1 */
00593   SD_cid->OEM_AppliID = CID_Tab[1] << 8;
00594
00595   /*!< Byte 2 */
00596   SD_cid->OEM_AppliID |= CID_Tab[2];
00597
00598   /*!< Byte 3 */
00599   SD_cid->ProdName1 = CID_Tab[3] << 24;
00600
00601   /*!< Byte 4 */
00602   SD_cid->ProdName1 |= CID_Tab[4] << 16;
00603
00604   /*!< Byte 5 */
00605   SD_cid->ProdName1 |= CID_Tab[5] << 8;
00606
00607   /*!< Byte 6 */
00608   SD_cid->ProdName1 |= CID_Tab[6];
00609
00610   /*!< Byte 7 */
00611   SD_cid->ProdName2 = CID_Tab[7];
00612
00613   /*!< Byte 8 */
00614   SD_cid->ProdRev = CID_Tab[8];
00615
00616   /*!< Byte 9 */
00617   SD_cid->ProdSN = CID_Tab[9] << 24;
00618
00619   /*!< Byte 10 */
00620   SD_cid->ProdSN |= CID_Tab[10] << 16;
00621
00622   /*!< Byte 11 */
00623   SD_cid->ProdSN |= CID_Tab[11] << 8;
00624
00625   /*!< Byte 12 */
00626   SD_cid->ProdSN |= CID_Tab[12];
00627
00628   /*!< Byte 13 */
00629   SD_cid->Reserved1 |= (CID_Tab[13] & 0xF0) >> 4;
00630   SD_cid->ManufactDate = (CID_Tab[13] & 0x0F) << 8;
00631
00632   /*!< Byte 14 */
00633   SD_cid->ManufactDate |= CID_Tab[14];
00634
00635   /*!< Byte 15 */
00636   SD_cid->CID_CRC = (CID_Tab[15] & 0xFE) >> 1;
00637   SD_cid->Reserved2 = 1;
00638
00639   /*!< Return the reponse */
00640   return rvalue;
00641 }
00642
00643 /**
00644   * @brief  Send 5 bytes command to the SD card.
00645   * @param  Cmd: The user expected command to send to SD card.
00646   * @param  Arg: The command argument.
00647   * @param  Crc: The CRC.
00648   * @retval None
00649   */
00650 void SD_SendCmd(uint8_t Cmd, uint32_t Arg, uint8_t Crc)
00651 {
00652   uint32_t i = 0x00;
00653
00654   uint8_t Frame[6];
00655
00656   Frame[0] = (Cmd | 0x40); /*!< Construct byte 1 */
00657
00658   Frame[1] = (uint8_t)(Arg >> 24); /*!< Construct byte 2 */
00659
00660   Frame[2] = (uint8_t)(Arg >> 16); /*!< Construct byte 3 */
00661
00662   Frame[3] = (uint8_t)(Arg >> 8); /*!< Construct byte 4 */
00663
00664   Frame[4] = (uint8_t)(Arg); /*!< Construct byte 5 */
00665
00666   Frame[5] = (Crc); /*!< Construct CRC: byte 6 */
00667
00668   for (i = 0; i < 6; i++)
00669   {
00670     SD_WriteByte(Frame[i]); /*!< Send the Cmd bytes */
00671   }
00672 }
00673
00674 /**
00675   * @brief  Get SD card data response.
00676   * @param  None
00677   * @retval The SD status: Read data response xxx0<status>1
00678   *         - status 010: Data accecpted
00679   *         - status 101: Data rejected due to a crc error
00680   *         - status 110: Data rejected due to a Write error.
00681   *         - status 111: Data rejected due to other error.
00682   */
00683 uint8_t SD_GetDataResponse(void)
00684 {
00685   uint32_t i = 0;
00686   uint8_t response, rvalue;
00687
00688   while (i <= 64)
00689   {
00690     /*!< Read resonse */
00691     response = SD_ReadByte();
00692     /*!< Mask unused bits */
00693     response &= 0x1F;
00694     switch (response)
00695     {
00696       case SD_DATA_OK:
00697       {
00698         rvalue = SD_DATA_OK;
00699         break;
00700       }
00701       case SD_DATA_CRC_ERROR:
00702         return SD_DATA_CRC_ERROR;
00703       case SD_DATA_WRITE_ERROR:
00704         return SD_DATA_WRITE_ERROR;
00705       default:
00706       {
00707         rvalue = SD_DATA_OTHER_ERROR;
00708         break;
00709       }
00710     }
00711     /*!< Exit loop in case of data ok */
00712     if (rvalue == SD_DATA_OK)
00713       break;
00714     /*!< Increment loop counter */
00715     i++;
00716   }
00717
00718   /*!< Wait null data */
00719   while (SD_ReadByte() == 0);
00720
00721   /*!< Return response */
00722   return response;
00723 }
00724
00725 /**
00726   * @brief  Returns the SD response.
00727   * @param  None
00728   * @retval The SD Response:
00729   *         - SD_RESPONSE_FAILURE: Sequence failed
00730   *         - SD_RESPONSE_NO_ERROR: Sequence succeed
00731   */
00732 SD_Error SD_GetResponse(uint8_t Response)
00733 {
00734   uint32_t Count = 0xFFF;
00735
00736   /*!< Check if response is got or a timeout is happen */
00737   while ((SD_ReadByte() != Response) && Count)
00738   {
00739     Count--;
00740   }
00741   if (Count == 0)
00742   {
00743     /*!< After time out */
00744     return SD_RESPONSE_FAILURE;
00745   }
00746   else
00747   {
00748     /*!< Right response got */
00749     return SD_RESPONSE_NO_ERROR;
00750   }
00751 }
00752
00753 /**
00754   * @brief  Returns the SD status.
00755   * @param  None
00756   * @retval The SD status.
00757   */
00758 uint16_t SD_GetStatus(void)
00759 {
00760   uint16_t Status = 0;
00761
00762   /*!< SD chip select low */
00763   SD_CS_LOW();
00764
00765   /*!< Send CMD13 (SD_SEND_STATUS) to get SD status */
00766   SD_SendCmd(SD_CMD_SEND_STATUS, 0, 0xFF);
00767
00768   Status = SD_ReadByte();
00769   Status |= (uint16_t)(SD_ReadByte() << 8);
00770
00771   /*!< SD chip select high */
00772   SD_CS_HIGH();
00773
00774   /*!< Send dummy byte 0xFF */
00775   SD_WriteByte(SD_DUMMY_BYTE);
00776
00777   return Status;
00778 }
00779
00780 /**
00781   * @brief  Put SD in Idle state.
00782   * @param  None
00783   * @retval The SD Response:
00784   *         - SD_RESPONSE_FAILURE: Sequence failed
00785   *         - SD_RESPONSE_NO_ERROR: Sequence succeed
00786   */
00787 SD_Error SD_GoIdleState(void)
00788 {
00789   /*!< SD chip select low */
00790   SD_CS_LOW();
00791
00792   /*!< Send CMD0 (SD_CMD_GO_IDLE_STATE) to put SD in SPI mode */
00793   SD_SendCmd(SD_CMD_GO_IDLE_STATE, 0, 0x95);
00794
00795   /*!< Wait for In Idle State Response (R1 Format) equal to 0x01 */
00796   if (SD_GetResponse(SD_IN_IDLE_STATE))
00797   {
00798     /*!< No Idle State Response: return response failue */
00799     return SD_RESPONSE_FAILURE;
00800   }
00801   /*----------Activates the card initialization process-----------*/
00802   do
00803   {
00804     /*!< SD chip select high */
00805     SD_CS_HIGH();
00806
00807     /*!< Send Dummy byte 0xFF */
00808     SD_WriteByte(SD_DUMMY_BYTE);
00809
00810     /*!< SD chip select low */
00811     SD_CS_LOW();
00812
00813     /*!< Send CMD1 (Activates the card process) until response equal to 0x0 */
00814     SD_SendCmd(SD_CMD_SEND_OP_COND, 0, 0xFF);
00815     /*!< Wait for no error Response (R1 Format) equal to 0x00 */
00816   }
00817   while (SD_GetResponse(SD_RESPONSE_NO_ERROR));
00818
00819   /*!< SD chip select high */
00820   SD_CS_HIGH();
00821
00822   /*!< Send dummy byte 0xFF */
00823   SD_WriteByte(SD_DUMMY_BYTE);
00824
00825   return SD_RESPONSE_NO_ERROR;
00826 }
00827
00828 /**
00829   * @brief  Write a byte on the SD.
00830   * @param  Data: byte to send.
00831   * @retval None
00832   */
00833 uint8_t SD_WriteByte(uint8_t Data)
00834 {
00835   /*!< Wait until the transmit buffer is empty */
00836   while(SPI_I2S_GetFlagStatus(SD_SPI, SPI_I2S_FLAG_TXE) == RESET)
00837   {
00838   }
00839
00840   /*!< Send the byte */
00841   SPI_I2S_SendData(SD_SPI, Data);
00842
00843   /*!< Wait to receive a byte*/
00844   while(SPI_I2S_GetFlagStatus(SD_SPI, SPI_I2S_FLAG_RXNE) == RESET)
00845   {
00846   }
00847
00848   /*!< Return the byte read from the SPI bus */
00849   return SPI_I2S_ReceiveData(SD_SPI);
00850 }
00851
00852 /**
00853   * @brief  Read a byte from the SD.
00854   * @param  None
00855   * @retval The received byte.
00856   */
00857 uint8_t SD_ReadByte(void)
00858 {
00859   uint8_t Data = 0;
00860
00861   /*!< Wait until the transmit buffer is empty */
00862   while (SPI_I2S_GetFlagStatus(SD_SPI, SPI_I2S_FLAG_TXE) == RESET)
00863   {
00864   }
00865   /*!< Send the byte */
00866   SPI_I2S_SendData(SD_SPI, SD_DUMMY_BYTE);
00867
00868   /*!< Wait until a data is received */
00869   while (SPI_I2S_GetFlagStatus(SD_SPI, SPI_I2S_FLAG_RXNE) == RESET)
00870   {
00871   }
00872   /*!< Get the received data */
00873   Data = SPI_I2S_ReceiveData(SD_SPI);
00874
00875   /*!< Return the shifted data */
00876   return Data;
00877 }
00878
00879 /**
00880   * @}
00881   */
00882
00883
00884 /**
00885   * @}
00886   */
00887
00888
00889 /**
00890   * @}
00891   */
00892
00893 /**
00894   * @}
00895   */
00896
00897 /**
00898   * @}
00899   */
00900
00901 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32_eval_spi_sd.h Source File

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • Common

stm32_eval_spi_sd.h

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32_eval_spi_sd.h
00004   * @author  MCD Application Team
00005   * @version V4.5.0
00006   * @date    07-March-2011
00007   * @brief   This file contains all the functions prototypes for the stm32_eval_spi_sd
00008   *          firmware driver.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00013   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00014   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00015   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00016   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00017   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00018   *
00019   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00020   ******************************************************************************
00021   */
00022
00023 /* Define to prevent recursive inclusion -------------------------------------*/
00024 #ifndef __STM32_EVAL_SPI_SD_H
00025 #define __STM32_EVAL_SPI_SD_H
00026
00027 #ifdef __cplusplus
00028  extern "C" {
00029 #endif
00030
00031 /* Includes ------------------------------------------------------------------*/
00032 #include "stm32_eval.h"
00033
00034 /** @addtogroup Utilities
00035   * @{
00036   */
00037
00038 /** @addtogroup STM32_EVAL
00039   * @{
00040   */
00041
00042 /** @addtogroup Common
00043   * @{
00044   */
00045
00046 /** @addtogroup STM32_EVAL_SPI_SD
00047   * @{
00048   */
00049
00050 /** @defgroup STM32_EVAL_SPI_SD_Exported_Types
00051   * @{
00052   */
00053
00054 typedef enum
00055 {
00056 /**
00057   * @brief  SD reponses and error flags
00058   */
00059   SD_RESPONSE_NO_ERROR      = (0x00),
00060   SD_IN_IDLE_STATE          = (0x01),
00061   SD_ERASE_RESET            = (0x02),
00062   SD_ILLEGAL_COMMAND        = (0x04),
00063   SD_COM_CRC_ERROR          = (0x08),
00064   SD_ERASE_SEQUENCE_ERROR   = (0x10),
00065   SD_ADDRESS_ERROR          = (0x20),
00066   SD_PARAMETER_ERROR        = (0x40),
00067   SD_RESPONSE_FAILURE       = (0xFF),
00068
00069 /**
00070   * @brief  Data response error
00071   */
00072   SD_DATA_OK                = (0x05),
00073   SD_DATA_CRC_ERROR         = (0x0B),
00074   SD_DATA_WRITE_ERROR       = (0x0D),
00075   SD_DATA_OTHER_ERROR       = (0xFF)
00076 } SD_Error;
00077
00078 /**
00079   * @brief  Card Specific Data: CSD Register
00080   */
00081 typedef struct
00082 {
00083   __IO uint8_t  CSDStruct;            /*!< CSD structure */
00084   __IO uint8_t  SysSpecVersion;       /*!< System specification version */
00085   __IO uint8_t  Reserved1;            /*!< Reserved */
00086   __IO uint8_t  TAAC;                 /*!< Data read access-time 1 */
00087   __IO uint8_t  NSAC;                 /*!< Data read access-time 2 in CLK cycles */
00088   __IO uint8_t  MaxBusClkFrec;        /*!< Max. bus clock frequency */
00089   __IO uint16_t CardComdClasses;      /*!< Card command classes */
00090   __IO uint8_t  RdBlockLen;           /*!< Max. read data block length */
00091   __IO uint8_t  PartBlockRead;        /*!< Partial blocks for read allowed */
00092   __IO uint8_t  WrBlockMisalign;      /*!< Write block misalignment */
00093   __IO uint8_t  RdBlockMisalign;      /*!< Read block misalignment */
00094   __IO uint8_t  DSRImpl;              /*!< DSR implemented */
00095   __IO uint8_t  Reserved2;            /*!< Reserved */
00096   __IO uint32_t DeviceSize;           /*!< Device Size */
00097   __IO uint8_t  MaxRdCurrentVDDMin;   /*!< Max. read current @ VDD min */
00098   __IO uint8_t  MaxRdCurrentVDDMax;   /*!< Max. read current @ VDD max */
00099   __IO uint8_t  MaxWrCurrentVDDMin;   /*!< Max. write current @ VDD min */
00100   __IO uint8_t  MaxWrCurrentVDDMax;   /*!< Max. write current @ VDD max */
00101   __IO uint8_t  DeviceSizeMul;        /*!< Device size multiplier */
00102   __IO uint8_t  EraseGrSize;          /*!< Erase group size */
00103   __IO uint8_t  EraseGrMul;           /*!< Erase group size multiplier */
00104   __IO uint8_t  WrProtectGrSize;      /*!< Write protect group size */
00105   __IO uint8_t  WrProtectGrEnable;    /*!< Write protect group enable */
00106   __IO uint8_t  ManDeflECC;           /*!< Manufacturer default ECC */
00107   __IO uint8_t  WrSpeedFact;          /*!< Write speed factor */
00108   __IO uint8_t  MaxWrBlockLen;        /*!< Max. write data block length */
00109   __IO uint8_t  WriteBlockPaPartial;  /*!< Partial blocks for write allowed */
00110   __IO uint8_t  Reserved3;            /*!< Reserded */
00111   __IO uint8_t  ContentProtectAppli;  /*!< Content protection application */
00112   __IO uint8_t  FileFormatGrouop;     /*!< File format group */
00113   __IO uint8_t  CopyFlag;             /*!< Copy flag (OTP) */
00114   __IO uint8_t  PermWrProtect;        /*!< Permanent write protection */
00115   __IO uint8_t  TempWrProtect;        /*!< Temporary write protection */
00116   __IO uint8_t  FileFormat;           /*!< File Format */
00117   __IO uint8_t  ECC;                  /*!< ECC code */
00118   __IO uint8_t  CSD_CRC;              /*!< CSD CRC */
00119   __IO uint8_t  Reserved4;            /*!< always 1*/
00120 } SD_CSD;
00121
00122 /**
00123   * @brief  Card Identification Data: CID Register
00124   */
00125 typedef struct
00126 {
00127   __IO uint8_t  ManufacturerID;       /*!< ManufacturerID */
00128   __IO uint16_t OEM_AppliID;          /*!< OEM/Application ID */
00129   __IO uint32_t ProdName1;            /*!< Product Name part1 */
00130   __IO uint8_t  ProdName2;            /*!< Product Name part2*/
00131   __IO uint8_t  ProdRev;              /*!< Product Revision */
00132   __IO uint32_t ProdSN;               /*!< Product Serial Number */
00133   __IO uint8_t  Reserved1;            /*!< Reserved1 */
00134   __IO uint16_t ManufactDate;         /*!< Manufacturing Date */
00135   __IO uint8_t  CID_CRC;              /*!< CID CRC */
00136   __IO uint8_t  Reserved2;            /*!< always 1 */
00137 } SD_CID;
00138
00139 /**
00140   * @brief SD Card information
00141   */
00142 typedef struct
00143 {
00144   SD_CSD SD_csd;
00145   SD_CID SD_cid;
00146   uint32_t CardCapacity;  /*!< Card Capacity */
00147   uint32_t CardBlockSize; /*!< Card Block Size */
00148 } SD_CardInfo;
00149
00150 /**
00151   * @}
00152   */
00153
00154 /** @defgroup STM32_EVAL_SPI_SD_Exported_Constants
00155   * @{
00156   */
00157
00158 /**
00159   * @brief  Block Size
00160   */
00161 #define SD_BLOCK_SIZE    0x200
00162
00163 /**
00164   * @brief  Dummy byte
00165   */
00166 #define SD_DUMMY_BYTE   0xFF
00167
00168 /**
00169   * @brief  Start Data tokens:
00170   *         Tokens (necessary because at nop/idle (and CS active) only 0xff is
00171   *         on the data/command line)
00172   */
00173 #define SD_START_DATA_SINGLE_BLOCK_READ    0xFE  /*!< Data token start byte, Start Single Block Read */
00174 #define SD_START_DATA_MULTIPLE_BLOCK_READ  0xFE  /*!< Data token start byte, Start Multiple Block Read */
00175 #define SD_START_DATA_SINGLE_BLOCK_WRITE   0xFE  /*!< Data token start byte, Start Single Block Write */
00176 #define SD_START_DATA_MULTIPLE_BLOCK_WRITE 0xFD  /*!< Data token start byte, Start Multiple Block Write */
00177 #define SD_STOP_DATA_MULTIPLE_BLOCK_WRITE  0xFD  /*!< Data toke stop byte, Stop Multiple Block Write */
00178
00179 /**
00180   * @brief  SD detection on its memory slot
00181   */
00182 #define SD_PRESENT        ((uint8_t)0x01)
00183 #define SD_NOT_PRESENT    ((uint8_t)0x00)
00184
00185
00186 /**
00187   * @brief  Commands: CMDxx = CMD-number | 0x40
00188   */
00189 #define SD_CMD_GO_IDLE_STATE          0   /*!< CMD0 = 0x40 */
00190 #define SD_CMD_SEND_OP_COND           1   /*!< CMD1 = 0x41 */
00191 #define SD_CMD_SEND_CSD               9   /*!< CMD9 = 0x49 */
00192 #define SD_CMD_SEND_CID               10  /*!< CMD10 = 0x4A */
00193 #define SD_CMD_STOP_TRANSMISSION      12  /*!< CMD12 = 0x4C */
00194 #define SD_CMD_SEND_STATUS            13  /*!< CMD13 = 0x4D */
00195 #define SD_CMD_SET_BLOCKLEN           16  /*!< CMD16 = 0x50 */
00196 #define SD_CMD_READ_SINGLE_BLOCK      17  /*!< CMD17 = 0x51 */
00197 #define SD_CMD_READ_MULT_BLOCK        18  /*!< CMD18 = 0x52 */
00198 #define SD_CMD_SET_BLOCK_COUNT        23  /*!< CMD23 = 0x57 */
00199 #define SD_CMD_WRITE_SINGLE_BLOCK     24  /*!< CMD24 = 0x58 */
00200 #define SD_CMD_WRITE_MULT_BLOCK       25  /*!< CMD25 = 0x59 */
00201 #define SD_CMD_PROG_CSD               27  /*!< CMD27 = 0x5B */
00202 #define SD_CMD_SET_WRITE_PROT         28  /*!< CMD28 = 0x5C */
00203 #define SD_CMD_CLR_WRITE_PROT         29  /*!< CMD29 = 0x5D */
00204 #define SD_CMD_SEND_WRITE_PROT        30  /*!< CMD30 = 0x5E */
00205 #define SD_CMD_SD_ERASE_GRP_START     32  /*!< CMD32 = 0x60 */
00206 #define SD_CMD_SD_ERASE_GRP_END       33  /*!< CMD33 = 0x61 */
00207 #define SD_CMD_UNTAG_SECTOR           34  /*!< CMD34 = 0x62 */
00208 #define SD_CMD_ERASE_GRP_START        35  /*!< CMD35 = 0x63 */
00209 #define SD_CMD_ERASE_GRP_END          36  /*!< CMD36 = 0x64 */
00210 #define SD_CMD_UNTAG_ERASE_GROUP      37  /*!< CMD37 = 0x65 */
00211 #define SD_CMD_ERASE                  38  /*!< CMD38 = 0x66 */
00212
00213 /**
00214   * @}
00215   */
00216
00217 /** @defgroup STM32_EVAL_SPI_SD_Exported_Macros
00218   * @{
00219   */
00220 /**
00221   * @brief  Select SD Card: ChipSelect pin low
00222   */
00223 #define SD_CS_LOW()     GPIO_ResetBits(SD_CS_GPIO_PORT, SD_CS_PIN)
00224 /**
00225   * @brief  Deselect SD Card: ChipSelect pin high
00226   */
00227 #define SD_CS_HIGH()    GPIO_SetBits(SD_CS_GPIO_PORT, SD_CS_PIN)
00228 /**
00229   * @}
00230   */
00231
00232 /** @defgroup STM32_EVAL_SPI_SD_Exported_Functions
00233   * @{
00234   */
00235 void SD_DeInit(void);
00236 SD_Error SD_Init(void);
00237 uint8_t SD_Detect(void);
00238 SD_Error SD_GetCardInfo(SD_CardInfo *cardinfo);
00239 SD_Error SD_ReadBlock(uint8_t* pBuffer, uint32_t ReadAddr, uint16_t BlockSize);
00240 SD_Error SD_ReadMultiBlocks(uint8_t* pBuffer, uint32_t ReadAddr, uint16_t BlockSize, uint32_t NumberOfBlocks);
00241 SD_Error SD_WriteBlock(uint8_t* pBuffer, uint32_t WriteAddr, uint16_t BlockSize);
00242 SD_Error SD_WriteMultiBlocks(uint8_t* pBuffer, uint32_t WriteAddr, uint16_t BlockSize, uint32_t NumberOfBlocks);
00243 SD_Error SD_GetCSDRegister(SD_CSD* SD_csd);
00244 SD_Error SD_GetCIDRegister(SD_CID* SD_cid);
00245
00246 void SD_SendCmd(uint8_t Cmd, uint32_t Arg, uint8_t Crc);
00247 SD_Error SD_GetResponse(uint8_t Response);
00248 uint8_t SD_GetDataResponse(void);
00249 SD_Error SD_GoIdleState(void);
00250 uint16_t SD_GetStatus(void);
00251
00252 uint8_t SD_WriteByte(uint8_t byte);
00253 uint8_t SD_ReadByte(void);
00254
00255 #ifdef __cplusplus
00256 }
00257 #endif
00258
00259 #endif /* __STM32_EVAL_SPI_SD_H */
00260 /**
00261   * @}
00262   */
00263
00264 /**
00265   * @}
00266   */
00267
00268 /**
00269   * @}
00270   */
00271
00272 /**
00273   * @}
00274   */
00275
00276 /**
00277   * @}
00278   */
00279
00280 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x.h Source File

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Libraries
  • CMSIS
  • CM3
  • DeviceSupport
  • ST
  • STM32F10x

stm32f10x.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32f10x.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    11-March-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
00008   *          This file contains all the peripheral register's definitions, bits
00009   *          definitions and memory mapping for STM32F10x Connectivity line,
00010   *          High density, High density value line, Medium density,
00011   *          Medium density Value line, Low density, Low density Value line
00012   *          and XL-density devices.
00013   *
00014   *          The file is the unique include file that the application programmer
00015   *          is using in the C source code, usually in main.c. This file contains:
00016   *           - Configuration section that allows to select:
00017   *              - The device used in the target application
00018   *              - To use or not the peripheral’s drivers in application code(i.e.
00019   *                code will be based on direct access to peripheral’s registers
00020   *                rather than drivers API), this option is controlled by
00021   *                "#define USE_STDPERIPH_DRIVER"
00022   *              - To change few application-specific parameters such as the HSE
00023   *                crystal frequency
00024   *           - Data structures and the address mapping for all peripherals
00025   *           - Peripheral's registers declarations and bits definition
00026   *           - Macros to access peripheral’s registers hardware
00027   *
00028   ******************************************************************************
00029   * @attention
00030   *
00031   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00032   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00033   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00034   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00035   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00036   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00037   *
00038   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00039   ******************************************************************************
00040   */
00041
00042 /** @addtogroup CMSIS
00043   * @{
00044   */
00045
00046 /** @addtogroup stm32f10x
00047   * @{
00048   */
00049
00050 #ifndef __STM32F10x_H
00051 #define __STM32F10x_H
00052
00053 #ifdef __cplusplus
00054  extern "C" {
00055 #endif
00056
00057 /** @addtogroup Library_configuration_section
00058   * @{
00059   */
00060
00061 /* Uncomment the line below according to the target STM32 device used in your
00062    application
00063   */
00064
00065 #if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL)
00066   /* #define STM32F10X_LD */     /*!< STM32F10X_LD: STM32 Low density devices */
00067   /* #define STM32F10X_LD_VL */  /*!< STM32F10X_LD_VL: STM32 Low density Value Line devices */
00068   /* #define STM32F10X_MD */     /*!< STM32F10X_MD: STM32 Medium density devices */
00069   /* #define STM32F10X_MD_VL */  /*!< STM32F10X_MD_VL: STM32 Medium density Value Line devices */
00070   /* #define STM32F10X_HD */     /*!< STM32F10X_HD: STM32 High density devices */
00071   /* #define STM32F10X_HD_VL */  /*!< STM32F10X_HD_VL: STM32 High density value line devices */
00072   /* #define STM32F10X_XL */     /*!< STM32F10X_XL: STM32 XL-density devices */
00073   /* #define STM32F10X_CL */     /*!< STM32F10X_CL: STM32 Connectivity line devices */
00074 #endif
00075 /*  Tip: To avoid modifying this file each time you need to switch between these
00076         devices, you can define the device in your toolchain compiler preprocessor.
00077
00078  - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers
00079    where the Flash memory density ranges between 16 and 32 Kbytes.
00080  - Low-density value line devices are STM32F100xx microcontrollers where the Flash
00081    memory density ranges between 16 and 32 Kbytes.
00082  - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers
00083    where the Flash memory density ranges between 64 and 128 Kbytes.
00084  - Medium-density value line devices are STM32F100xx microcontrollers where the
00085    Flash memory density ranges between 64 and 128 Kbytes.
00086  - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
00087    the Flash memory density ranges between 256 and 512 Kbytes.
00088  - High-density value line devices are STM32F100xx microcontrollers where the
00089    Flash memory density ranges between 256 and 512 Kbytes.
00090  - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
00091    the Flash memory density ranges between 512 and 1024 Kbytes.
00092  - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
00093   */
00094
00095 #if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL)
00096  #error "Please select first the target STM32F10x device used in your application (in stm32f10x.h file)"
00097 #endif
00098
00099 #if !defined  USE_STDPERIPH_DRIVER
00100 /**
00101  * @brief Comment the line below if you will not use the peripherals drivers.
00102    In this case, these drivers will not be included and the application code will
00103    be based on direct access to peripherals registers
00104    */
00105   /*#define USE_STDPERIPH_DRIVER*/
00106 #endif
00107
00108 /**
00109  * @brief In the following line adjust the value of External High Speed oscillator (HSE)
00110    used in your application
00111
00112    Tip: To avoid modifying this file each time you need to use different HSE, you
00113         can define the HSE value in your toolchain compiler preprocessor.
00114   */
00115 #if !defined  HSE_VALUE
00116  #ifdef STM32F10X_CL
00117   #define HSE_VALUE    ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
00118  #else
00119   #define HSE_VALUE    ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
00120  #endif /* STM32F10X_CL */
00121 #endif /* HSE_VALUE */
00122
00123
00124 /**
00125  * @brief In the following line adjust the External High Speed oscillator (HSE) Startup
00126    Timeout value
00127    */
00128 #define HSE_STARTUP_TIMEOUT   ((uint16_t)0x0500) /*!< Time out for HSE start up */
00129
00130 #define HSI_VALUE    ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/
00131
00132 /**
00133  * @brief STM32F10x Standard Peripheral Library version number
00134    */
00135 #define __STM32F10X_STDPERIPH_VERSION_MAIN   (0x03) /*!< [31:24] main version */
00136 #define __STM32F10X_STDPERIPH_VERSION_SUB1   (0x05) /*!< [23:16] sub1 version */
00137 #define __STM32F10X_STDPERIPH_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */
00138 #define __STM32F10X_STDPERIPH_VERSION_RC     (0x00) /*!< [7:0]  release candidate */
00139 #define __STM32F10X_STDPERIPH_VERSION       ( (__STM32F10X_STDPERIPH_VERSION_MAIN << 24)\
00140                                              |(__STM32F10X_STDPERIPH_VERSION_SUB1 << 16)\
00141                                              |(__STM32F10X_STDPERIPH_VERSION_SUB2 << 8)\
00142                                              |(__STM32F10X_STDPERIPH_VERSION_RC))
00143
00144 /**
00145   * @}
00146   */
00147
00148 /** @addtogroup Configuration_section_for_CMSIS
00149   * @{
00150   */
00151
00152 /**
00153  * @brief Configuration of the Cortex-M3 Processor and Core Peripherals
00154  */
00155 #ifdef STM32F10X_XL
00156  #define __MPU_PRESENT             1 /*!< STM32 XL-density devices provide an MPU */
00157 #else
00158  #define __MPU_PRESENT             0 /*!< Other STM32 devices does not provide an MPU */
00159 #endif /* STM32F10X_XL */
00160 #define __NVIC_PRIO_BITS          4 /*!< STM32 uses 4 Bits for the Priority Levels    */
00161 #define __Vendor_SysTickConfig    0 /*!< Set to 1 if different SysTick Config is used */
00162
00163 /**
00164  * @brief STM32F10x Interrupt Number Definition, according to the selected device
00165  *        in @ref Library_configuration_section
00166  */
00167 typedef enum IRQn
00168 {
00169 /******  Cortex-M3 Processor Exceptions Numbers ***************************************************/
00170   NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                             */
00171   MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M3 Memory Management Interrupt              */
00172   BusFault_IRQn               = -11,    /*!< 5 Cortex-M3 Bus Fault Interrupt                      */
00173   UsageFault_IRQn             = -10,    /*!< 6 Cortex-M3 Usage Fault Interrupt                    */
00174   SVCall_IRQn                 = -5,     /*!< 11 Cortex-M3 SV Call Interrupt                       */
00175   DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M3 Debug Monitor Interrupt                 */
00176   PendSV_IRQn                 = -2,     /*!< 14 Cortex-M3 Pend SV Interrupt                       */
00177   SysTick_IRQn                = -1,     /*!< 15 Cortex-M3 System Tick Interrupt                   */
00178
00179 /******  STM32 specific Interrupt Numbers *********************************************************/
00180   WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                            */
00181   PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt            */
00182   TAMPER_IRQn                 = 2,      /*!< Tamper Interrupt                                     */
00183   RTC_IRQn                    = 3,      /*!< RTC global Interrupt                                 */
00184   FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                               */
00185   RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                 */
00186   EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                 */
00187   EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                 */
00188   EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                 */
00189   EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                 */
00190   EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                 */
00191   DMA1_Channel1_IRQn          = 11,     /*!< DMA1 Channel 1 global Interrupt                      */
00192   DMA1_Channel2_IRQn          = 12,     /*!< DMA1 Channel 2 global Interrupt                      */
00193   DMA1_Channel3_IRQn          = 13,     /*!< DMA1 Channel 3 global Interrupt                      */
00194   DMA1_Channel4_IRQn          = 14,     /*!< DMA1 Channel 4 global Interrupt                      */
00195   DMA1_Channel5_IRQn          = 15,     /*!< DMA1 Channel 5 global Interrupt                      */
00196   DMA1_Channel6_IRQn          = 16,     /*!< DMA1 Channel 6 global Interrupt                      */
00197   DMA1_Channel7_IRQn          = 17,     /*!< DMA1 Channel 7 global Interrupt                      */
00198
00199 #ifdef STM32F10X_LD
00200   ADC1_2_IRQn                 = 18,     /*!< ADC1 and ADC2 global Interrupt                       */
00201   USB_HP_CAN1_TX_IRQn         = 19,     /*!< USB Device High Priority or CAN1 TX Interrupts       */
00202   USB_LP_CAN1_RX0_IRQn        = 20,     /*!< USB Device Low Priority or CAN1 RX0 Interrupts       */
00203   CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                   */
00204   CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                   */
00205   EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
00206   TIM1_BRK_IRQn               = 24,     /*!< TIM1 Break Interrupt                                 */
00207   TIM1_UP_IRQn                = 25,     /*!< TIM1 Update Interrupt                                */
00208   TIM1_TRG_COM_IRQn           = 26,     /*!< TIM1 Trigger and Commutation Interrupt               */
00209   TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                       */
00210   TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                */
00211   TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                */
00212   I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
00213   I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */
00214   SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */
00215   USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */
00216   USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */
00217   EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
00218   RTCAlarm_IRQn               = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */
00219   USBWakeUp_IRQn              = 42      /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
00220 #endif /* STM32F10X_LD */
00221
00222 #ifdef STM32F10X_LD_VL
00223   ADC1_IRQn                   = 18,     /*!< ADC1 global Interrupt                                */
00224   EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
00225   TIM1_BRK_TIM15_IRQn         = 24,     /*!< TIM1 Break and TIM15 Interrupts                      */
00226   TIM1_UP_TIM16_IRQn          = 25,     /*!< TIM1 Update and TIM16 Interrupts                     */
00227   TIM1_TRG_COM_TIM17_IRQn     = 26,     /*!< TIM1 Trigger and Commutation and TIM17 Interrupt     */
00228   TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                       */
00229   TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                */
00230   TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                */
00231   I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
00232   I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */
00233   SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */
00234   USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */
00235   USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */
00236   EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
00237   RTCAlarm_IRQn               = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */
00238   CEC_IRQn                    = 42,     /*!< HDMI-CEC Interrupt                                   */
00239   TIM6_DAC_IRQn               = 54,     /*!< TIM6 and DAC underrun Interrupt                      */
00240   TIM7_IRQn                   = 55      /*!< TIM7 Interrupt                                       */
00241 #endif /* STM32F10X_LD_VL */
00242
00243 #ifdef STM32F10X_MD
00244   ADC1_2_IRQn                 = 18,     /*!< ADC1 and ADC2 global Interrupt                       */
00245   USB_HP_CAN1_TX_IRQn         = 19,     /*!< USB Device High Priority or CAN1 TX Interrupts       */
00246   USB_LP_CAN1_RX0_IRQn        = 20,     /*!< USB Device Low Priority or CAN1 RX0 Interrupts       */
00247   CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                   */
00248   CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                   */
00249   EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
00250   TIM1_BRK_IRQn               = 24,     /*!< TIM1 Break Interrupt                                 */
00251   TIM1_UP_IRQn                = 25,     /*!< TIM1 Update Interrupt                                */
00252   TIM1_TRG_COM_IRQn           = 26,     /*!< TIM1 Trigger and Commutation Interrupt               */
00253   TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                       */
00254   TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                */
00255   TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                */
00256   TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                */
00257   I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
00258   I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */
00259   I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                 */
00260   I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                 */
00261   SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */
00262   SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                */
00263   USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */
00264   USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */
00265   USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                              */
00266   EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
00267   RTCAlarm_IRQn               = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */
00268   USBWakeUp_IRQn              = 42      /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
00269 #endif /* STM32F10X_MD */
00270
00271 #ifdef STM32F10X_MD_VL
00272   ADC1_IRQn                   = 18,     /*!< ADC1 global Interrupt                                */
00273   EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
00274   TIM1_BRK_TIM15_IRQn         = 24,     /*!< TIM1 Break and TIM15 Interrupts                      */
00275   TIM1_UP_TIM16_IRQn          = 25,     /*!< TIM1 Update and TIM16 Interrupts                     */
00276   TIM1_TRG_COM_TIM17_IRQn     = 26,     /*!< TIM1 Trigger and Commutation and TIM17 Interrupt     */
00277   TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                       */
00278   TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                */
00279   TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                */
00280   TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                */
00281   I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
00282   I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */
00283   I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                 */
00284   I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                 */
00285   SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */
00286   SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                */
00287   USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */
00288   USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */
00289   USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                              */
00290   EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
00291   RTCAlarm_IRQn               = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */
00292   CEC_IRQn                    = 42,     /*!< HDMI-CEC Interrupt                                   */
00293   TIM6_DAC_IRQn               = 54,     /*!< TIM6 and DAC underrun Interrupt                      */
00294   TIM7_IRQn                   = 55      /*!< TIM7 Interrupt                                       */
00295 #endif /* STM32F10X_MD_VL */
00296
00297 #ifdef STM32F10X_HD
00298   ADC1_2_IRQn                 = 18,     /*!< ADC1 and ADC2 global Interrupt                       */
00299   USB_HP_CAN1_TX_IRQn         = 19,     /*!< USB Device High Priority or CAN1 TX Interrupts       */
00300   USB_LP_CAN1_RX0_IRQn        = 20,     /*!< USB Device Low Priority or CAN1 RX0 Interrupts       */
00301   CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                   */
00302   CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                   */
00303   EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
00304   TIM1_BRK_IRQn               = 24,     /*!< TIM1 Break Interrupt                                 */
00305   TIM1_UP_IRQn                = 25,     /*!< TIM1 Update Interrupt                                */
00306   TIM1_TRG_COM_IRQn           = 26,     /*!< TIM1 Trigger and Commutation Interrupt               */
00307   TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                       */
00308   TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                */
00309   TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                */
00310   TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                */
00311   I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
00312   I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */
00313   I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                 */
00314   I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                 */
00315   SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */
00316   SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                */
00317   USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */
00318   USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */
00319   USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                              */
00320   EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
00321   RTCAlarm_IRQn               = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */
00322   USBWakeUp_IRQn              = 42,     /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
00323   TIM8_BRK_IRQn               = 43,     /*!< TIM8 Break Interrupt                                 */
00324   TIM8_UP_IRQn                = 44,     /*!< TIM8 Update Interrupt                                */
00325   TIM8_TRG_COM_IRQn           = 45,     /*!< TIM8 Trigger and Commutation Interrupt               */
00326   TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                       */
00327   ADC3_IRQn                   = 47,     /*!< ADC3 global Interrupt                                */
00328   FSMC_IRQn                   = 48,     /*!< FSMC global Interrupt                                */
00329   SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                */
00330   TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                */
00331   SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                */
00332   UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                               */
00333   UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                               */
00334   TIM6_IRQn                   = 54,     /*!< TIM6 global Interrupt                                */
00335   TIM7_IRQn                   = 55,     /*!< TIM7 global Interrupt                                */
00336   DMA2_Channel1_IRQn          = 56,     /*!< DMA2 Channel 1 global Interrupt                      */
00337   DMA2_Channel2_IRQn          = 57,     /*!< DMA2 Channel 2 global Interrupt                      */
00338   DMA2_Channel3_IRQn          = 58,     /*!< DMA2 Channel 3 global Interrupt                      */
00339   DMA2_Channel4_5_IRQn        = 59      /*!< DMA2 Channel 4 and Channel 5 global Interrupt        */
00340 #endif /* STM32F10X_HD */
00341
00342 #ifdef STM32F10X_HD_VL
00343   ADC1_IRQn                   = 18,     /*!< ADC1 global Interrupt                                */
00344   EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
00345   TIM1_BRK_TIM15_IRQn         = 24,     /*!< TIM1 Break and TIM15 Interrupts                      */
00346   TIM1_UP_TIM16_IRQn          = 25,     /*!< TIM1 Update and TIM16 Interrupts                     */
00347   TIM1_TRG_COM_TIM17_IRQn     = 26,     /*!< TIM1 Trigger and Commutation and TIM17 Interrupt     */
00348   TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                       */
00349   TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                */
00350   TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                */
00351   TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                */
00352   I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
00353   I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */
00354   I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                 */
00355   I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                 */
00356   SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */
00357   SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                */
00358   USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */
00359   USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */
00360   USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                              */
00361   EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
00362   RTCAlarm_IRQn               = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */
00363   CEC_IRQn                    = 42,     /*!< HDMI-CEC Interrupt                                   */
00364   TIM12_IRQn                  = 43,     /*!< TIM12 global Interrupt                               */
00365   TIM13_IRQn                  = 44,     /*!< TIM13 global Interrupt                               */
00366   TIM14_IRQn                  = 45,     /*!< TIM14 global Interrupt                               */
00367   TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                */
00368   SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                */
00369   UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                               */
00370   UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                               */
00371   TIM6_DAC_IRQn               = 54,     /*!< TIM6 and DAC underrun Interrupt                      */
00372   TIM7_IRQn                   = 55,     /*!< TIM7 Interrupt                                       */
00373   DMA2_Channel1_IRQn          = 56,     /*!< DMA2 Channel 1 global Interrupt                      */
00374   DMA2_Channel2_IRQn          = 57,     /*!< DMA2 Channel 2 global Interrupt                      */
00375   DMA2_Channel3_IRQn          = 58,     /*!< DMA2 Channel 3 global Interrupt                      */
00376   DMA2_Channel4_5_IRQn        = 59,     /*!< DMA2 Channel 4 and Channel 5 global Interrupt        */
00377   DMA2_Channel5_IRQn          = 60      /*!< DMA2 Channel 5 global Interrupt (DMA2 Channel 5 is
00378                                              mapped at position 60 only if the MISC_REMAP bit in
00379                                              the AFIO_MAPR2 register is set)                      */
00380 #endif /* STM32F10X_HD_VL */
00381
00382 #ifdef STM32F10X_XL
00383   ADC1_2_IRQn                 = 18,     /*!< ADC1 and ADC2 global Interrupt                       */
00384   USB_HP_CAN1_TX_IRQn         = 19,     /*!< USB Device High Priority or CAN1 TX Interrupts       */
00385   USB_LP_CAN1_RX0_IRQn        = 20,     /*!< USB Device Low Priority or CAN1 RX0 Interrupts       */
00386   CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                   */
00387   CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                   */
00388   EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
00389   TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break Interrupt and TIM9 global Interrupt       */
00390   TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global Interrupt     */
00391   TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
00392   TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                       */
00393   TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                */
00394   TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                */
00395   TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                */
00396   I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
00397   I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */
00398   I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                 */
00399   I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                 */
00400   SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */
00401   SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                */
00402   USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */
00403   USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */
00404   USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                              */
00405   EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
00406   RTCAlarm_IRQn               = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */
00407   USBWakeUp_IRQn              = 42,     /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
00408   TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global Interrupt      */
00409   TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global Interrupt     */
00410   TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
00411   TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                       */
00412   ADC3_IRQn                   = 47,     /*!< ADC3 global Interrupt                                */
00413   FSMC_IRQn                   = 48,     /*!< FSMC global Interrupt                                */
00414   SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                */
00415   TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                */
00416   SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                */
00417   UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                               */
00418   UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                               */
00419   TIM6_IRQn                   = 54,     /*!< TIM6 global Interrupt                                */
00420   TIM7_IRQn                   = 55,     /*!< TIM7 global Interrupt                                */
00421   DMA2_Channel1_IRQn          = 56,     /*!< DMA2 Channel 1 global Interrupt                      */
00422   DMA2_Channel2_IRQn          = 57,     /*!< DMA2 Channel 2 global Interrupt                      */
00423   DMA2_Channel3_IRQn          = 58,     /*!< DMA2 Channel 3 global Interrupt                      */
00424   DMA2_Channel4_5_IRQn        = 59      /*!< DMA2 Channel 4 and Channel 5 global Interrupt        */
00425 #endif /* STM32F10X_XL */
00426
00427 #ifdef STM32F10X_CL
00428   ADC1_2_IRQn                 = 18,     /*!< ADC1 and ADC2 global Interrupt                       */
00429   CAN1_TX_IRQn                = 19,     /*!< USB Device High Priority or CAN1 TX Interrupts       */
00430   CAN1_RX0_IRQn               = 20,     /*!< USB Device Low Priority or CAN1 RX0 Interrupts       */
00431   CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                   */
00432   CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                   */
00433   EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
00434   TIM1_BRK_IRQn               = 24,     /*!< TIM1 Break Interrupt                                 */
00435   TIM1_UP_IRQn                = 25,     /*!< TIM1 Update Interrupt                                */
00436   TIM1_TRG_COM_IRQn           = 26,     /*!< TIM1 Trigger and Commutation Interrupt               */
00437   TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                       */
00438   TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                */
00439   TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                */
00440   TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                */
00441   I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
00442   I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */
00443   I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                 */
00444   I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                 */
00445   SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */
00446   SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                */
00447   USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */
00448   USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */
00449   USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                              */
00450   EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
00451   RTCAlarm_IRQn               = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */
00452   OTG_FS_WKUP_IRQn            = 42,     /*!< USB OTG FS WakeUp from suspend through EXTI Line Interrupt */
00453   TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                */
00454   SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                */
00455   UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                               */
00456   UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                               */
00457   TIM6_IRQn                   = 54,     /*!< TIM6 global Interrupt                                */
00458   TIM7_IRQn                   = 55,     /*!< TIM7 global Interrupt                                */
00459   DMA2_Channel1_IRQn          = 56,     /*!< DMA2 Channel 1 global Interrupt                      */
00460   DMA2_Channel2_IRQn          = 57,     /*!< DMA2 Channel 2 global Interrupt                      */
00461   DMA2_Channel3_IRQn          = 58,     /*!< DMA2 Channel 3 global Interrupt                      */
00462   DMA2_Channel4_IRQn          = 59,     /*!< DMA2 Channel 4 global Interrupt                      */
00463   DMA2_Channel5_IRQn          = 60,     /*!< DMA2 Channel 5 global Interrupt                      */
00464   ETH_IRQn                    = 61,     /*!< Ethernet global Interrupt                            */
00465   ETH_WKUP_IRQn               = 62,     /*!< Ethernet Wakeup through EXTI line Interrupt          */
00466   CAN2_TX_IRQn                = 63,     /*!< CAN2 TX Interrupt                                    */
00467   CAN2_RX0_IRQn               = 64,     /*!< CAN2 RX0 Interrupt                                   */
00468   CAN2_RX1_IRQn               = 65,     /*!< CAN2 RX1 Interrupt                                   */
00469   CAN2_SCE_IRQn               = 66,     /*!< CAN2 SCE Interrupt                                   */
00470   OTG_FS_IRQn                 = 67      /*!< USB OTG FS global Interrupt                          */
00471 #endif /* STM32F10X_CL */
00472 } IRQn_Type;
00473
00474 /**
00475   * @}
00476   */
00477
00478 #include "core_cm3.h"
00479 #include "system_stm32f10x.h"
00480 #include <stdint.h>
00481
00482 /** @addtogroup Exported_types
00483   * @{
00484   */
00485
00486 /*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */
00487 typedef int32_t  s32;
00488 typedef int16_t s16;
00489 typedef int8_t  s8;
00490
00491 typedef const int32_t sc32;  /*!< Read Only */
00492 typedef const int16_t sc16;  /*!< Read Only */
00493 typedef const int8_t sc8;   /*!< Read Only */
00494
00495 typedef __IO int32_t  vs32;
00496 typedef __IO int16_t  vs16;
00497 typedef __IO int8_t   vs8;
00498
00499 typedef __I int32_t vsc32;  /*!< Read Only */
00500 typedef __I int16_t vsc16;  /*!< Read Only */
00501 typedef __I int8_t vsc8;   /*!< Read Only */
00502
00503 typedef uint32_t  u32;
00504 typedef uint16_t u16;
00505 typedef uint8_t  u8;
00506
00507 typedef const uint32_t uc32;  /*!< Read Only */
00508 typedef const uint16_t uc16;  /*!< Read Only */
00509 typedef const uint8_t uc8;   /*!< Read Only */
00510
00511 typedef __IO uint32_t  vu32;
00512 typedef __IO uint16_t vu16;
00513 typedef __IO uint8_t  vu8;
00514
00515 typedef __I uint32_t vuc32;  /*!< Read Only */
00516 typedef __I uint16_t vuc16;  /*!< Read Only */
00517 typedef __I uint8_t vuc8;   /*!< Read Only */
00518
00519 typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
00520
00521 typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
00522 #define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
00523
00524 typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
00525
00526 /*!< STM32F10x Standard Peripheral Library old definitions (maintained for legacy purpose) */
00527 #define HSEStartUp_TimeOut   HSE_STARTUP_TIMEOUT
00528 #define HSE_Value            HSE_VALUE
00529 #define HSI_Value            HSI_VALUE
00530 /**
00531   * @}
00532   */
00533
00534 /** @addtogroup Peripheral_registers_structures
00535   * @{
00536   */
00537
00538 /**
00539   * @brief Analog to Digital Converter
00540   */
00541
00542 typedef struct
00543 {
00544   __IO uint32_t SR;
00545   __IO uint32_t CR1;
00546   __IO uint32_t CR2;
00547   __IO uint32_t SMPR1;
00548   __IO uint32_t SMPR2;
00549   __IO uint32_t JOFR1;
00550   __IO uint32_t JOFR2;
00551   __IO uint32_t JOFR3;
00552   __IO uint32_t JOFR4;
00553   __IO uint32_t HTR;
00554   __IO uint32_t LTR;
00555   __IO uint32_t SQR1;
00556   __IO uint32_t SQR2;
00557   __IO uint32_t SQR3;
00558   __IO uint32_t JSQR;
00559   __IO uint32_t JDR1;
00560   __IO uint32_t JDR2;
00561   __IO uint32_t JDR3;
00562   __IO uint32_t JDR4;
00563   __IO uint32_t DR;
00564 } ADC_TypeDef;
00565
00566 /**
00567   * @brief Backup Registers
00568   */
00569
00570 typedef struct
00571 {
00572   uint32_t  RESERVED0;
00573   __IO uint16_t DR1;
00574   uint16_t  RESERVED1;
00575   __IO uint16_t DR2;
00576   uint16_t  RESERVED2;
00577   __IO uint16_t DR3;
00578   uint16_t  RESERVED3;
00579   __IO uint16_t DR4;
00580   uint16_t  RESERVED4;
00581   __IO uint16_t DR5;
00582   uint16_t  RESERVED5;
00583   __IO uint16_t DR6;
00584   uint16_t  RESERVED6;
00585   __IO uint16_t DR7;
00586   uint16_t  RESERVED7;
00587   __IO uint16_t DR8;
00588   uint16_t  RESERVED8;
00589   __IO uint16_t DR9;
00590   uint16_t  RESERVED9;
00591   __IO uint16_t DR10;
00592   uint16_t  RESERVED10;
00593   __IO uint16_t RTCCR;
00594   uint16_t  RESERVED11;
00595   __IO uint16_t CR;
00596   uint16_t  RESERVED12;
00597   __IO uint16_t CSR;
00598   uint16_t  RESERVED13[5];
00599   __IO uint16_t DR11;
00600   uint16_t  RESERVED14;
00601   __IO uint16_t DR12;
00602   uint16_t  RESERVED15;
00603   __IO uint16_t DR13;
00604   uint16_t  RESERVED16;
00605   __IO uint16_t DR14;
00606   uint16_t  RESERVED17;
00607   __IO uint16_t DR15;
00608   uint16_t  RESERVED18;
00609   __IO uint16_t DR16;
00610   uint16_t  RESERVED19;
00611   __IO uint16_t DR17;
00612   uint16_t  RESERVED20;
00613   __IO uint16_t DR18;
00614   uint16_t  RESERVED21;
00615   __IO uint16_t DR19;
00616   uint16_t  RESERVED22;
00617   __IO uint16_t DR20;
00618   uint16_t  RESERVED23;
00619   __IO uint16_t DR21;
00620   uint16_t  RESERVED24;
00621   __IO uint16_t DR22;
00622   uint16_t  RESERVED25;
00623   __IO uint16_t DR23;
00624   uint16_t  RESERVED26;
00625   __IO uint16_t DR24;
00626   uint16_t  RESERVED27;
00627   __IO uint16_t DR25;
00628   uint16_t  RESERVED28;
00629   __IO uint16_t DR26;
00630   uint16_t  RESERVED29;
00631   __IO uint16_t DR27;
00632   uint16_t  RESERVED30;
00633   __IO uint16_t DR28;
00634   uint16_t  RESERVED31;
00635   __IO uint16_t DR29;
00636   uint16_t  RESERVED32;
00637   __IO uint16_t DR30;
00638   uint16_t  RESERVED33;
00639   __IO uint16_t DR31;
00640   uint16_t  RESERVED34;
00641   __IO uint16_t DR32;
00642   uint16_t  RESERVED35;
00643   __IO uint16_t DR33;
00644   uint16_t  RESERVED36;
00645   __IO uint16_t DR34;
00646   uint16_t  RESERVED37;
00647   __IO uint16_t DR35;
00648   uint16_t  RESERVED38;
00649   __IO uint16_t DR36;
00650   uint16_t  RESERVED39;
00651   __IO uint16_t DR37;
00652   uint16_t  RESERVED40;
00653   __IO uint16_t DR38;
00654   uint16_t  RESERVED41;
00655   __IO uint16_t DR39;
00656   uint16_t  RESERVED42;
00657   __IO uint16_t DR40;
00658   uint16_t  RESERVED43;
00659   __IO uint16_t DR41;
00660   uint16_t  RESERVED44;
00661   __IO uint16_t DR42;
00662   uint16_t  RESERVED45;
00663 } BKP_TypeDef;
00664
00665 /**
00666   * @brief Controller Area Network TxMailBox
00667   */
00668
00669 typedef struct
00670 {
00671   __IO uint32_t TIR;
00672   __IO uint32_t TDTR;
00673   __IO uint32_t TDLR;
00674   __IO uint32_t TDHR;
00675 } CAN_TxMailBox_TypeDef;
00676
00677 /**
00678   * @brief Controller Area Network FIFOMailBox
00679   */
00680
00681 typedef struct
00682 {
00683   __IO uint32_t RIR;
00684   __IO uint32_t RDTR;
00685   __IO uint32_t RDLR;
00686   __IO uint32_t RDHR;
00687 } CAN_FIFOMailBox_TypeDef;
00688
00689 /**
00690   * @brief Controller Area Network FilterRegister
00691   */
00692
00693 typedef struct
00694 {
00695   __IO uint32_t FR1;
00696   __IO uint32_t FR2;
00697 } CAN_FilterRegister_TypeDef;
00698
00699 /**
00700   * @brief Controller Area Network
00701   */
00702
00703 typedef struct
00704 {
00705   __IO uint32_t MCR;
00706   __IO uint32_t MSR;
00707   __IO uint32_t TSR;
00708   __IO uint32_t RF0R;
00709   __IO uint32_t RF1R;
00710   __IO uint32_t IER;
00711   __IO uint32_t ESR;
00712   __IO uint32_t BTR;
00713   uint32_t  RESERVED0[88];
00714   CAN_TxMailBox_TypeDef sTxMailBox[3];
00715   CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
00716   uint32_t  RESERVED1[12];
00717   __IO uint32_t FMR;
00718   __IO uint32_t FM1R;
00719   uint32_t  RESERVED2;
00720   __IO uint32_t FS1R;
00721   uint32_t  RESERVED3;
00722   __IO uint32_t FFA1R;
00723   uint32_t  RESERVED4;
00724   __IO uint32_t FA1R;
00725   uint32_t  RESERVED5[8];
00726 #ifndef STM32F10X_CL
00727   CAN_FilterRegister_TypeDef sFilterRegister[14];
00728 #else
00729   CAN_FilterRegister_TypeDef sFilterRegister[28];
00730 #endif /* STM32F10X_CL */
00731 } CAN_TypeDef;
00732
00733 /**
00734   * @brief Consumer Electronics Control (CEC)
00735   */
00736 typedef struct
00737 {
00738   __IO uint32_t CFGR;
00739   __IO uint32_t OAR;
00740   __IO uint32_t PRES;
00741   __IO uint32_t ESR;
00742   __IO uint32_t CSR;
00743   __IO uint32_t TXD;
00744   __IO uint32_t RXD;
00745 } CEC_TypeDef;
00746
00747 /**
00748   * @brief CRC calculation unit
00749   */
00750
00751 typedef struct
00752 {
00753   __IO uint32_t DR;
00754   __IO uint8_t  IDR;
00755   uint8_t   RESERVED0;
00756   uint16_t  RESERVED1;
00757   __IO uint32_t CR;
00758 } CRC_TypeDef;
00759
00760 /**
00761   * @brief Digital to Analog Converter
00762   */
00763
00764 typedef struct
00765 {
00766   __IO uint32_t CR;
00767   __IO uint32_t SWTRIGR;
00768   __IO uint32_t DHR12R1;
00769   __IO uint32_t DHR12L1;
00770   __IO uint32_t DHR8R1;
00771   __IO uint32_t DHR12R2;
00772   __IO uint32_t DHR12L2;
00773   __IO uint32_t DHR8R2;
00774   __IO uint32_t DHR12RD;
00775   __IO uint32_t DHR12LD;
00776   __IO uint32_t DHR8RD;
00777   __IO uint32_t DOR1;
00778   __IO uint32_t DOR2;
00779 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00780   __IO uint32_t SR;
00781 #endif
00782 } DAC_TypeDef;
00783
00784 /**
00785   * @brief Debug MCU
00786   */
00787
00788 typedef struct
00789 {
00790   __IO uint32_t IDCODE;
00791   __IO uint32_t CR;
00792 }DBGMCU_TypeDef;
00793
00794 /**
00795   * @brief DMA Controller
00796   */
00797
00798 typedef struct
00799 {
00800   __IO uint32_t CCR;
00801   __IO uint32_t CNDTR;
00802   __IO uint32_t CPAR;
00803   __IO uint32_t CMAR;
00804 } DMA_Channel_TypeDef;
00805
00806 typedef struct
00807 {
00808   __IO uint32_t ISR;
00809   __IO uint32_t IFCR;
00810 } DMA_TypeDef;
00811
00812 /**
00813   * @brief Ethernet MAC
00814   */
00815
00816 typedef struct
00817 {
00818   __IO uint32_t MACCR;
00819   __IO uint32_t MACFFR;
00820   __IO uint32_t MACHTHR;
00821   __IO uint32_t MACHTLR;
00822   __IO uint32_t MACMIIAR;
00823   __IO uint32_t MACMIIDR;
00824   __IO uint32_t MACFCR;
00825   __IO uint32_t MACVLANTR;             /*    8 */
00826        uint32_t RESERVED0[2];
00827   __IO uint32_t MACRWUFFR;             /*   11 */
00828   __IO uint32_t MACPMTCSR;
00829        uint32_t RESERVED1[2];
00830   __IO uint32_t MACSR;                 /*   15 */
00831   __IO uint32_t MACIMR;
00832   __IO uint32_t MACA0HR;
00833   __IO uint32_t MACA0LR;
00834   __IO uint32_t MACA1HR;
00835   __IO uint32_t MACA1LR;
00836   __IO uint32_t MACA2HR;
00837   __IO uint32_t MACA2LR;
00838   __IO uint32_t MACA3HR;
00839   __IO uint32_t MACA3LR;               /*   24 */
00840        uint32_t RESERVED2[40];
00841   __IO uint32_t MMCCR;                 /*   65 */
00842   __IO uint32_t MMCRIR;
00843   __IO uint32_t MMCTIR;
00844   __IO uint32_t MMCRIMR;
00845   __IO uint32_t MMCTIMR;               /*   69 */
00846        uint32_t RESERVED3[14];
00847   __IO uint32_t MMCTGFSCCR;            /*   84 */
00848   __IO uint32_t MMCTGFMSCCR;
00849        uint32_t RESERVED4[5];
00850   __IO uint32_t MMCTGFCR;
00851        uint32_t RESERVED5[10];
00852   __IO uint32_t MMCRFCECR;
00853   __IO uint32_t MMCRFAECR;
00854        uint32_t RESERVED6[10];
00855   __IO uint32_t MMCRGUFCR;
00856        uint32_t RESERVED7[334];
00857   __IO uint32_t PTPTSCR;
00858   __IO uint32_t PTPSSIR;
00859   __IO uint32_t PTPTSHR;
00860   __IO uint32_t PTPTSLR;
00861   __IO uint32_t PTPTSHUR;
00862   __IO uint32_t PTPTSLUR;
00863   __IO uint32_t PTPTSAR;
00864   __IO uint32_t PTPTTHR;
00865   __IO uint32_t PTPTTLR;
00866        uint32_t RESERVED8[567];
00867   __IO uint32_t DMABMR;
00868   __IO uint32_t DMATPDR;
00869   __IO uint32_t DMARPDR;
00870   __IO uint32_t DMARDLAR;
00871   __IO uint32_t DMATDLAR;
00872   __IO uint32_t DMASR;
00873   __IO uint32_t DMAOMR;
00874   __IO uint32_t DMAIER;
00875   __IO uint32_t DMAMFBOCR;
00876        uint32_t RESERVED9[9];
00877   __IO uint32_t DMACHTDR;
00878   __IO uint32_t DMACHRDR;
00879   __IO uint32_t DMACHTBAR;
00880   __IO uint32_t DMACHRBAR;
00881 } ETH_TypeDef;
00882
00883 /**
00884   * @brief External Interrupt/Event Controller
00885   */
00886
00887 typedef struct
00888 {
00889   __IO uint32_t IMR;
00890   __IO uint32_t EMR;
00891   __IO uint32_t RTSR;
00892   __IO uint32_t FTSR;
00893   __IO uint32_t SWIER;
00894   __IO uint32_t PR;
00895 } EXTI_TypeDef;
00896
00897 /**
00898   * @brief FLASH Registers
00899   */
00900
00901 typedef struct
00902 {
00903   __IO uint32_t ACR;
00904   __IO uint32_t KEYR;
00905   __IO uint32_t OPTKEYR;
00906   __IO uint32_t SR;
00907   __IO uint32_t CR;
00908   __IO uint32_t AR;
00909   __IO uint32_t RESERVED;
00910   __IO uint32_t OBR;
00911   __IO uint32_t WRPR;
00912 #ifdef STM32F10X_XL
00913   uint32_t RESERVED1[8];
00914   __IO uint32_t KEYR2;
00915   uint32_t RESERVED2;
00916   __IO uint32_t SR2;
00917   __IO uint32_t CR2;
00918   __IO uint32_t AR2;
00919 #endif /* STM32F10X_XL */
00920 } FLASH_TypeDef;
00921
00922 /**
00923   * @brief Option Bytes Registers
00924   */
00925
00926 typedef struct
00927 {
00928   __IO uint16_t RDP;
00929   __IO uint16_t USER;
00930   __IO uint16_t Data0;
00931   __IO uint16_t Data1;
00932   __IO uint16_t WRP0;
00933   __IO uint16_t WRP1;
00934   __IO uint16_t WRP2;
00935   __IO uint16_t WRP3;
00936 } OB_TypeDef;
00937
00938 /**
00939   * @brief Flexible Static Memory Controller
00940   */
00941
00942 typedef struct
00943 {
00944   __IO uint32_t BTCR[8];
00945 } FSMC_Bank1_TypeDef;
00946
00947 /**
00948   * @brief Flexible Static Memory Controller Bank1E
00949   */
00950
00951 typedef struct
00952 {
00953   __IO uint32_t BWTR[7];
00954 } FSMC_Bank1E_TypeDef;
00955
00956 /**
00957   * @brief Flexible Static Memory Controller Bank2
00958   */
00959
00960 typedef struct
00961 {
00962   __IO uint32_t PCR2;
00963   __IO uint32_t SR2;
00964   __IO uint32_t PMEM2;
00965   __IO uint32_t PATT2;
00966   uint32_t  RESERVED0;
00967   __IO uint32_t ECCR2;
00968 } FSMC_Bank2_TypeDef;
00969
00970 /**
00971   * @brief Flexible Static Memory Controller Bank3
00972   */
00973
00974 typedef struct
00975 {
00976   __IO uint32_t PCR3;
00977   __IO uint32_t SR3;
00978   __IO uint32_t PMEM3;
00979   __IO uint32_t PATT3;
00980   uint32_t  RESERVED0;
00981   __IO uint32_t ECCR3;
00982 } FSMC_Bank3_TypeDef;
00983
00984 /**
00985   * @brief Flexible Static Memory Controller Bank4
00986   */
00987
00988 typedef struct
00989 {
00990   __IO uint32_t PCR4;
00991   __IO uint32_t SR4;
00992   __IO uint32_t PMEM4;
00993   __IO uint32_t PATT4;
00994   __IO uint32_t PIO4;
00995 } FSMC_Bank4_TypeDef;
00996
00997 /**
00998   * @brief General Purpose I/O
00999   */
01000
01001 typedef struct
01002 {
01003   __IO uint32_t CRL;
01004   __IO uint32_t CRH;
01005   __IO uint32_t IDR;
01006   __IO uint32_t ODR;
01007   __IO uint32_t BSRR;
01008   __IO uint32_t BRR;
01009   __IO uint32_t LCKR;
01010 } GPIO_TypeDef;
01011
01012 /**
01013   * @brief Alternate Function I/O
01014   */
01015
01016 typedef struct
01017 {
01018   __IO uint32_t EVCR;
01019   __IO uint32_t MAPR;
01020   __IO uint32_t EXTICR[4];
01021   uint32_t RESERVED0;
01022   __IO uint32_t MAPR2;
01023 } AFIO_TypeDef;
01024 /**
01025   * @brief Inter Integrated Circuit Interface
01026   */
01027
01028 typedef struct
01029 {
01030   __IO uint16_t CR1;
01031   uint16_t  RESERVED0;
01032   __IO uint16_t CR2;
01033   uint16_t  RESERVED1;
01034   __IO uint16_t OAR1;
01035   uint16_t  RESERVED2;
01036   __IO uint16_t OAR2;
01037   uint16_t  RESERVED3;
01038   __IO uint16_t DR;
01039   uint16_t  RESERVED4;
01040   __IO uint16_t SR1;
01041   uint16_t  RESERVED5;
01042   __IO uint16_t SR2;
01043   uint16_t  RESERVED6;
01044   __IO uint16_t CCR;
01045   uint16_t  RESERVED7;
01046   __IO uint16_t TRISE;
01047   uint16_t  RESERVED8;
01048 } I2C_TypeDef;
01049
01050 /**
01051   * @brief Independent WATCHDOG
01052   */
01053
01054 typedef struct
01055 {
01056   __IO uint32_t KR;
01057   __IO uint32_t PR;
01058   __IO uint32_t RLR;
01059   __IO uint32_t SR;
01060 } IWDG_TypeDef;
01061
01062 /**
01063   * @brief Power Control
01064   */
01065
01066 typedef struct
01067 {
01068   __IO uint32_t CR;
01069   __IO uint32_t CSR;
01070 } PWR_TypeDef;
01071
01072 /**
01073   * @brief Reset and Clock Control
01074   */
01075
01076 typedef struct
01077 {
01078   __IO uint32_t CR;
01079   __IO uint32_t CFGR;
01080   __IO uint32_t CIR;
01081   __IO uint32_t APB2RSTR;
01082   __IO uint32_t APB1RSTR;
01083   __IO uint32_t AHBENR;
01084   __IO uint32_t APB2ENR;
01085   __IO uint32_t APB1ENR;
01086   __IO uint32_t BDCR;
01087   __IO uint32_t CSR;
01088
01089 #ifdef STM32F10X_CL
01090   __IO uint32_t AHBRSTR;
01091   __IO uint32_t CFGR2;
01092 #endif /* STM32F10X_CL */
01093
01094 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
01095   uint32_t RESERVED0;
01096   __IO uint32_t CFGR2;
01097 #endif /* STM32F10X_LD_VL || STM32F10X_MD_VL || STM32F10X_HD_VL */
01098 } RCC_TypeDef;
01099
01100 /**
01101   * @brief Real-Time Clock
01102   */
01103
01104 typedef struct
01105 {
01106   __IO uint16_t CRH;
01107   uint16_t  RESERVED0;
01108   __IO uint16_t CRL;
01109   uint16_t  RESERVED1;
01110   __IO uint16_t PRLH;
01111   uint16_t  RESERVED2;
01112   __IO uint16_t PRLL;
01113   uint16_t  RESERVED3;
01114   __IO uint16_t DIVH;
01115   uint16_t  RESERVED4;
01116   __IO uint16_t DIVL;
01117   uint16_t  RESERVED5;
01118   __IO uint16_t CNTH;
01119   uint16_t  RESERVED6;
01120   __IO uint16_t CNTL;
01121   uint16_t  RESERVED7;
01122   __IO uint16_t ALRH;
01123   uint16_t  RESERVED8;
01124   __IO uint16_t ALRL;
01125   uint16_t  RESERVED9;
01126 } RTC_TypeDef;
01127
01128 /**
01129   * @brief SD host Interface
01130   */
01131
01132 typedef struct
01133 {
01134   __IO uint32_t POWER;
01135   __IO uint32_t CLKCR;
01136   __IO uint32_t ARG;
01137   __IO uint32_t CMD;
01138   __I uint32_t RESPCMD;
01139   __I uint32_t RESP1;
01140   __I uint32_t RESP2;
01141   __I uint32_t RESP3;
01142   __I uint32_t RESP4;
01143   __IO uint32_t DTIMER;
01144   __IO uint32_t DLEN;
01145   __IO uint32_t DCTRL;
01146   __I uint32_t DCOUNT;
01147   __I uint32_t STA;
01148   __IO uint32_t ICR;
01149   __IO uint32_t MASK;
01150   uint32_t  RESERVED0[2];
01151   __I uint32_t FIFOCNT;
01152   uint32_t  RESERVED1[13];
01153   __IO uint32_t FIFO;
01154 } SDIO_TypeDef;
01155
01156 /**
01157   * @brief Serial Peripheral Interface
01158   */
01159
01160 typedef struct
01161 {
01162   __IO uint16_t CR1;
01163   uint16_t  RESERVED0;
01164   __IO uint16_t CR2;
01165   uint16_t  RESERVED1;
01166   __IO uint16_t SR;
01167   uint16_t  RESERVED2;
01168   __IO uint16_t DR;
01169   uint16_t  RESERVED3;
01170   __IO uint16_t CRCPR;
01171   uint16_t  RESERVED4;
01172   __IO uint16_t RXCRCR;
01173   uint16_t  RESERVED5;
01174   __IO uint16_t TXCRCR;
01175   uint16_t  RESERVED6;
01176   __IO uint16_t I2SCFGR;
01177   uint16_t  RESERVED7;
01178   __IO uint16_t I2SPR;
01179   uint16_t  RESERVED8;
01180 } SPI_TypeDef;
01181
01182 /**
01183   * @brief TIM
01184   */
01185
01186 typedef struct
01187 {
01188   __IO uint16_t CR1;
01189   uint16_t  RESERVED0;
01190   __IO uint16_t CR2;
01191   uint16_t  RESERVED1;
01192   __IO uint16_t SMCR;
01193   uint16_t  RESERVED2;
01194   __IO uint16_t DIER;
01195   uint16_t  RESERVED3;
01196   __IO uint16_t SR;
01197   uint16_t  RESERVED4;
01198   __IO uint16_t EGR;
01199   uint16_t  RESERVED5;
01200   __IO uint16_t CCMR1;
01201   uint16_t  RESERVED6;
01202   __IO uint16_t CCMR2;
01203   uint16_t  RESERVED7;
01204   __IO uint16_t CCER;
01205   uint16_t  RESERVED8;
01206   __IO uint16_t CNT;
01207   uint16_t  RESERVED9;
01208   __IO uint16_t PSC;
01209   uint16_t  RESERVED10;
01210   __IO uint16_t ARR;
01211   uint16_t  RESERVED11;
01212   __IO uint16_t RCR;
01213   uint16_t  RESERVED12;
01214   __IO uint16_t CCR1;
01215   uint16_t  RESERVED13;
01216   __IO uint16_t CCR2;
01217   uint16_t  RESERVED14;
01218   __IO uint16_t CCR3;
01219   uint16_t  RESERVED15;
01220   __IO uint16_t CCR4;
01221   uint16_t  RESERVED16;
01222   __IO uint16_t BDTR;
01223   uint16_t  RESERVED17;
01224   __IO uint16_t DCR;
01225   uint16_t  RESERVED18;
01226   __IO uint16_t DMAR;
01227   uint16_t  RESERVED19;
01228 } TIM_TypeDef;
01229
01230 /**
01231   * @brief Universal Synchronous Asynchronous Receiver Transmitter
01232   */
01233
01234 typedef struct
01235 {
01236   __IO uint16_t SR;
01237   uint16_t  RESERVED0;
01238   __IO uint16_t DR;
01239   uint16_t  RESERVED1;
01240   __IO uint16_t BRR;
01241   uint16_t  RESERVED2;
01242   __IO uint16_t CR1;
01243   uint16_t  RESERVED3;
01244   __IO uint16_t CR2;
01245   uint16_t  RESERVED4;
01246   __IO uint16_t CR3;
01247   uint16_t  RESERVED5;
01248   __IO uint16_t GTPR;
01249   uint16_t  RESERVED6;
01250 } USART_TypeDef;
01251
01252 /**
01253   * @brief Window WATCHDOG
01254   */
01255
01256 typedef struct
01257 {
01258   __IO uint32_t CR;
01259   __IO uint32_t CFR;
01260   __IO uint32_t SR;
01261 } WWDG_TypeDef;
01262
01263 /**
01264   * @}
01265   */
01266
01267 /** @addtogroup Peripheral_memory_map
01268   * @{
01269   */
01270
01271
01272 #define FLASH_BASE            ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
01273 #define SRAM_BASE             ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
01274 #define PERIPH_BASE           ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
01275
01276 #define SRAM_BB_BASE          ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
01277 #define PERIPH_BB_BASE        ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
01278
01279 #define FSMC_R_BASE           ((uint32_t)0xA0000000) /*!< FSMC registers base address */
01280
01281 /*!< Peripheral memory map */
01282 #define APB1PERIPH_BASE       PERIPH_BASE
01283 #define APB2PERIPH_BASE       (PERIPH_BASE + 0x10000)
01284 #define AHBPERIPH_BASE        (PERIPH_BASE + 0x20000)
01285
01286 #define TIM2_BASE             (APB1PERIPH_BASE + 0x0000)
01287 #define TIM3_BASE             (APB1PERIPH_BASE + 0x0400)
01288 #define TIM4_BASE             (APB1PERIPH_BASE + 0x0800)
01289 #define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00)
01290 #define TIM6_BASE             (APB1PERIPH_BASE + 0x1000)
01291 #define TIM7_BASE             (APB1PERIPH_BASE + 0x1400)
01292 #define TIM12_BASE            (APB1PERIPH_BASE + 0x1800)
01293 #define TIM13_BASE            (APB1PERIPH_BASE + 0x1C00)
01294 #define TIM14_BASE            (APB1PERIPH_BASE + 0x2000)
01295 #define RTC_BASE              (APB1PERIPH_BASE + 0x2800)
01296 #define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00)
01297 #define IWDG_BASE             (APB1PERIPH_BASE + 0x3000)
01298 #define SPI2_BASE             (APB1PERIPH_BASE + 0x3800)
01299 #define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00)
01300 #define USART2_BASE           (APB1PERIPH_BASE + 0x4400)
01301 #define USART3_BASE           (APB1PERIPH_BASE + 0x4800)
01302 #define UART4_BASE            (APB1PERIPH_BASE + 0x4C00)
01303 #define UART5_BASE            (APB1PERIPH_BASE + 0x5000)
01304 #define I2C1_BASE             (APB1PERIPH_BASE + 0x5400)
01305 #define I2C2_BASE             (APB1PERIPH_BASE + 0x5800)
01306 #define CAN1_BASE             (APB1PERIPH_BASE + 0x6400)
01307 #define CAN2_BASE             (APB1PERIPH_BASE + 0x6800)
01308 #define BKP_BASE              (APB1PERIPH_BASE + 0x6C00)
01309 #define PWR_BASE              (APB1PERIPH_BASE + 0x7000)
01310 #define DAC_BASE              (APB1PERIPH_BASE + 0x7400)
01311 #define CEC_BASE              (APB1PERIPH_BASE + 0x7800)
01312
01313 #define AFIO_BASE             (APB2PERIPH_BASE + 0x0000)
01314 #define EXTI_BASE             (APB2PERIPH_BASE + 0x0400)
01315 #define GPIOA_BASE            (APB2PERIPH_BASE + 0x0800)
01316 #define GPIOB_BASE            (APB2PERIPH_BASE + 0x0C00)
01317 #define GPIOC_BASE            (APB2PERIPH_BASE + 0x1000)
01318 #define GPIOD_BASE            (APB2PERIPH_BASE + 0x1400)
01319 #define GPIOE_BASE            (APB2PERIPH_BASE + 0x1800)
01320 #define GPIOF_BASE            (APB2PERIPH_BASE + 0x1C00)
01321 #define GPIOG_BASE            (APB2PERIPH_BASE + 0x2000)
01322 #define ADC1_BASE             (APB2PERIPH_BASE + 0x2400)
01323 #define ADC2_BASE             (APB2PERIPH_BASE + 0x2800)
01324 #define TIM1_BASE             (APB2PERIPH_BASE + 0x2C00)
01325 #define SPI1_BASE             (APB2PERIPH_BASE + 0x3000)
01326 #define TIM8_BASE             (APB2PERIPH_BASE + 0x3400)
01327 #define USART1_BASE           (APB2PERIPH_BASE + 0x3800)
01328 #define ADC3_BASE             (APB2PERIPH_BASE + 0x3C00)
01329 #define TIM15_BASE            (APB2PERIPH_BASE + 0x4000)
01330 #define TIM16_BASE            (APB2PERIPH_BASE + 0x4400)
01331 #define TIM17_BASE            (APB2PERIPH_BASE + 0x4800)
01332 #define TIM9_BASE             (APB2PERIPH_BASE + 0x4C00)
01333 #define TIM10_BASE            (APB2PERIPH_BASE + 0x5000)
01334 #define TIM11_BASE            (APB2PERIPH_BASE + 0x5400)
01335
01336 #define SDIO_BASE             (PERIPH_BASE + 0x18000)
01337
01338 #define DMA1_BASE             (AHBPERIPH_BASE + 0x0000)
01339 #define DMA1_Channel1_BASE    (AHBPERIPH_BASE + 0x0008)
01340 #define DMA1_Channel2_BASE    (AHBPERIPH_BASE + 0x001C)
01341 #define DMA1_Channel3_BASE    (AHBPERIPH_BASE + 0x0030)
01342 #define DMA1_Channel4_BASE    (AHBPERIPH_BASE + 0x0044)
01343 #define DMA1_Channel5_BASE    (AHBPERIPH_BASE + 0x0058)
01344 #define DMA1_Channel6_BASE    (AHBPERIPH_BASE + 0x006C)
01345 #define DMA1_Channel7_BASE    (AHBPERIPH_BASE + 0x0080)
01346 #define DMA2_BASE             (AHBPERIPH_BASE + 0x0400)
01347 #define DMA2_Channel1_BASE    (AHBPERIPH_BASE + 0x0408)
01348 #define DMA2_Channel2_BASE    (AHBPERIPH_BASE + 0x041C)
01349 #define DMA2_Channel3_BASE    (AHBPERIPH_BASE + 0x0430)
01350 #define DMA2_Channel4_BASE    (AHBPERIPH_BASE + 0x0444)
01351 #define DMA2_Channel5_BASE    (AHBPERIPH_BASE + 0x0458)
01352 #define RCC_BASE              (AHBPERIPH_BASE + 0x1000)
01353 #define CRC_BASE              (AHBPERIPH_BASE + 0x3000)
01354
01355 #define FLASH_R_BASE          (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */
01356 #define OB_BASE               ((uint32_t)0x1FFFF800)    /*!< Flash Option Bytes base address */
01357
01358 #define ETH_BASE              (AHBPERIPH_BASE + 0x8000)
01359 #define ETH_MAC_BASE          (ETH_BASE)
01360 #define ETH_MMC_BASE          (ETH_BASE + 0x0100)
01361 #define ETH_PTP_BASE          (ETH_BASE + 0x0700)
01362 #define ETH_DMA_BASE          (ETH_BASE + 0x1000)
01363
01364 #define FSMC_Bank1_R_BASE     (FSMC_R_BASE + 0x0000) /*!< FSMC Bank1 registers base address */
01365 #define FSMC_Bank1E_R_BASE    (FSMC_R_BASE + 0x0104) /*!< FSMC Bank1E registers base address */
01366 #define FSMC_Bank2_R_BASE     (FSMC_R_BASE + 0x0060) /*!< FSMC Bank2 registers base address */
01367 #define FSMC_Bank3_R_BASE     (FSMC_R_BASE + 0x0080) /*!< FSMC Bank3 registers base address */
01368 #define FSMC_Bank4_R_BASE     (FSMC_R_BASE + 0x00A0) /*!< FSMC Bank4 registers base address */
01369
01370 #define DBGMCU_BASE          ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
01371
01372 /**
01373   * @}
01374   */
01375
01376 /** @addtogroup Peripheral_declaration
01377   * @{
01378   */
01379
01380 #define TIM2                ((TIM_TypeDef *) TIM2_BASE)
01381 #define TIM3                ((TIM_TypeDef *) TIM3_BASE)
01382 #define TIM4                ((TIM_TypeDef *) TIM4_BASE)
01383 #define TIM5                ((TIM_TypeDef *) TIM5_BASE)
01384 #define TIM6                ((TIM_TypeDef *) TIM6_BASE)
01385 #define TIM7                ((TIM_TypeDef *) TIM7_BASE)
01386 #define TIM12               ((TIM_TypeDef *) TIM12_BASE)
01387 #define TIM13               ((TIM_TypeDef *) TIM13_BASE)
01388 #define TIM14               ((TIM_TypeDef *) TIM14_BASE)
01389 #define RTC                 ((RTC_TypeDef *) RTC_BASE)
01390 #define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
01391 #define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
01392 #define SPI2                ((SPI_TypeDef *) SPI2_BASE)
01393 #define SPI3                ((SPI_TypeDef *) SPI3_BASE)
01394 #define USART2              ((USART_TypeDef *) USART2_BASE)
01395 #define USART3              ((USART_TypeDef *) USART3_BASE)
01396 #define UART4               ((USART_TypeDef *) UART4_BASE)
01397 #define UART5               ((USART_TypeDef *) UART5_BASE)
01398 #define I2C1                ((I2C_TypeDef *) I2C1_BASE)
01399 #define I2C2                ((I2C_TypeDef *) I2C2_BASE)
01400 #define CAN1                ((CAN_TypeDef *) CAN1_BASE)
01401 #define CAN2                ((CAN_TypeDef *) CAN2_BASE)
01402 #define BKP                 ((BKP_TypeDef *) BKP_BASE)
01403 #define PWR                 ((PWR_TypeDef *) PWR_BASE)
01404 #define DAC                 ((DAC_TypeDef *) DAC_BASE)
01405 #define CEC                 ((CEC_TypeDef *) CEC_BASE)
01406 #define AFIO                ((AFIO_TypeDef *) AFIO_BASE)
01407 #define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
01408 #define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
01409 #define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
01410 #define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
01411 #define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
01412 #define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
01413 #define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
01414 #define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
01415 #define ADC1                ((ADC_TypeDef *) ADC1_BASE)
01416 #define ADC2                ((ADC_TypeDef *) ADC2_BASE)
01417 #define TIM1                ((TIM_TypeDef *) TIM1_BASE)
01418 #define SPI1                ((SPI_TypeDef *) SPI1_BASE)
01419 #define TIM8                ((TIM_TypeDef *) TIM8_BASE)
01420 #define USART1              ((USART_TypeDef *) USART1_BASE)
01421 #define ADC3                ((ADC_TypeDef *) ADC3_BASE)
01422 #define TIM15               ((TIM_TypeDef *) TIM15_BASE)
01423 #define TIM16               ((TIM_TypeDef *) TIM16_BASE)
01424 #define TIM17               ((TIM_TypeDef *) TIM17_BASE)
01425 #define TIM9                ((TIM_TypeDef *) TIM9_BASE)
01426 #define TIM10               ((TIM_TypeDef *) TIM10_BASE)
01427 #define TIM11               ((TIM_TypeDef *) TIM11_BASE)
01428 #define SDIO                ((SDIO_TypeDef *) SDIO_BASE)
01429 #define DMA1                ((DMA_TypeDef *) DMA1_BASE)
01430 #define DMA2                ((DMA_TypeDef *) DMA2_BASE)
01431 #define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
01432 #define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
01433 #define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
01434 #define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
01435 #define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
01436 #define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
01437 #define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
01438 #define DMA2_Channel1       ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
01439 #define DMA2_Channel2       ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
01440 #define DMA2_Channel3       ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
01441 #define DMA2_Channel4       ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
01442 #define DMA2_Channel5       ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
01443 #define RCC                 ((RCC_TypeDef *) RCC_BASE)
01444 #define CRC                 ((CRC_TypeDef *) CRC_BASE)
01445 #define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
01446 #define OB                  ((OB_TypeDef *) OB_BASE)
01447 #define ETH                 ((ETH_TypeDef *) ETH_BASE)
01448 #define FSMC_Bank1          ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
01449 #define FSMC_Bank1E         ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
01450 #define FSMC_Bank2          ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE)
01451 #define FSMC_Bank3          ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE)
01452 #define FSMC_Bank4          ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
01453 #define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
01454
01455 /**
01456   * @}
01457   */
01458
01459 /** @addtogroup Exported_constants
01460   * @{
01461   */
01462
01463   /** @addtogroup Peripheral_Registers_Bits_Definition
01464   * @{
01465   */
01466
01467 /******************************************************************************/
01468 /*                         Peripheral Registers_Bits_Definition               */
01469 /******************************************************************************/
01470
01471 /******************************************************************************/
01472 /*                                                                            */
01473 /*                          CRC calculation unit                              */
01474 /*                                                                            */
01475 /******************************************************************************/
01476
01477 /*******************  Bit definition for CRC_DR register  *********************/
01478 #define  CRC_DR_DR                           ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
01479
01480
01481 /*******************  Bit definition for CRC_IDR register  ********************/
01482 #define  CRC_IDR_IDR                         ((uint8_t)0xFF)        /*!< General-purpose 8-bit data register bits */
01483
01484
01485 /********************  Bit definition for CRC_CR register  ********************/
01486 #define  CRC_CR_RESET                        ((uint8_t)0x01)        /*!< RESET bit */
01487
01488 /******************************************************************************/
01489 /*                                                                            */
01490 /*                             Power Control                                  */
01491 /*                                                                            */
01492 /******************************************************************************/
01493
01494 /********************  Bit definition for PWR_CR register  ********************/
01495 #define  PWR_CR_LPDS                         ((uint16_t)0x0001)     /*!< Low-Power Deepsleep */
01496 #define  PWR_CR_PDDS                         ((uint16_t)0x0002)     /*!< Power Down Deepsleep */
01497 #define  PWR_CR_CWUF                         ((uint16_t)0x0004)     /*!< Clear Wakeup Flag */
01498 #define  PWR_CR_CSBF                         ((uint16_t)0x0008)     /*!< Clear Standby Flag */
01499 #define  PWR_CR_PVDE                         ((uint16_t)0x0010)     /*!< Power Voltage Detector Enable */
01500
01501 #define  PWR_CR_PLS                          ((uint16_t)0x00E0)     /*!< PLS[2:0] bits (PVD Level Selection) */
01502 #define  PWR_CR_PLS_0                        ((uint16_t)0x0020)     /*!< Bit 0 */
01503 #define  PWR_CR_PLS_1                        ((uint16_t)0x0040)     /*!< Bit 1 */
01504 #define  PWR_CR_PLS_2                        ((uint16_t)0x0080)     /*!< Bit 2 */
01505
01506 /*!< PVD level configuration */
01507 #define  PWR_CR_PLS_2V2                      ((uint16_t)0x0000)     /*!< PVD level 2.2V */
01508 #define  PWR_CR_PLS_2V3                      ((uint16_t)0x0020)     /*!< PVD level 2.3V */
01509 #define  PWR_CR_PLS_2V4                      ((uint16_t)0x0040)     /*!< PVD level 2.4V */
01510 #define  PWR_CR_PLS_2V5                      ((uint16_t)0x0060)     /*!< PVD level 2.5V */
01511 #define  PWR_CR_PLS_2V6                      ((uint16_t)0x0080)     /*!< PVD level 2.6V */
01512 #define  PWR_CR_PLS_2V7                      ((uint16_t)0x00A0)     /*!< PVD level 2.7V */
01513 #define  PWR_CR_PLS_2V8                      ((uint16_t)0x00C0)     /*!< PVD level 2.8V */
01514 #define  PWR_CR_PLS_2V9                      ((uint16_t)0x00E0)     /*!< PVD level 2.9V */
01515
01516 #define  PWR_CR_DBP                          ((uint16_t)0x0100)     /*!< Disable Backup Domain write protection */
01517
01518
01519 /*******************  Bit definition for PWR_CSR register  ********************/
01520 #define  PWR_CSR_WUF                         ((uint16_t)0x0001)     /*!< Wakeup Flag */
01521 #define  PWR_CSR_SBF                         ((uint16_t)0x0002)     /*!< Standby Flag */
01522 #define  PWR_CSR_PVDO                        ((uint16_t)0x0004)     /*!< PVD Output */
01523 #define  PWR_CSR_EWUP                        ((uint16_t)0x0100)     /*!< Enable WKUP pin */
01524
01525 /******************************************************************************/
01526 /*                                                                            */
01527 /*                            Backup registers                                */
01528 /*                                                                            */
01529 /******************************************************************************/
01530
01531 /*******************  Bit definition for BKP_DR1 register  ********************/
01532 #define  BKP_DR1_D                           ((uint16_t)0xFFFF)     /*!< Backup data */
01533
01534 /*******************  Bit definition for BKP_DR2 register  ********************/
01535 #define  BKP_DR2_D                           ((uint16_t)0xFFFF)     /*!< Backup data */
01536
01537 /*******************  Bit definition for BKP_DR3 register  ********************/
01538 #define  BKP_DR3_D                           ((uint16_t)0xFFFF)     /*!< Backup data */
01539
01540 /*******************  Bit definition for BKP_DR4 register  ********************/
01541 #define  BKP_DR4_D                           ((uint16_t)0xFFFF)     /*!< Backup data */
01542
01543 /*******************  Bit definition for BKP_DR5 register  ********************/
01544 #define  BKP_DR5_D                           ((uint16_t)0xFFFF)     /*!< Backup data */
01545
01546 /*******************  Bit definition for BKP_DR6 register  ********************/
01547 #define  BKP_DR6_D                           ((uint16_t)0xFFFF)     /*!< Backup data */
01548
01549 /*******************  Bit definition for BKP_DR7 register  ********************/
01550 #define  BKP_DR7_D                           ((uint16_t)0xFFFF)     /*!< Backup data */
01551
01552 /*******************  Bit definition for BKP_DR8 register  ********************/
01553 #define  BKP_DR8_D                           ((uint16_t)0xFFFF)     /*!< Backup data */
01554
01555 /*******************  Bit definition for BKP_DR9 register  ********************/
01556 #define  BKP_DR9_D                           ((uint16_t)0xFFFF)     /*!< Backup data */
01557
01558 /*******************  Bit definition for BKP_DR10 register  *******************/
01559 #define  BKP_DR10_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
01560
01561 /*******************  Bit definition for BKP_DR11 register  *******************/
01562 #define  BKP_DR11_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
01563
01564 /*******************  Bit definition for BKP_DR12 register  *******************/
01565 #define  BKP_DR12_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
01566
01567 /*******************  Bit definition for BKP_DR13 register  *******************/
01568 #define  BKP_DR13_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
01569
01570 /*******************  Bit definition for BKP_DR14 register  *******************/
01571 #define  BKP_DR14_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
01572
01573 /*******************  Bit definition for BKP_DR15 register  *******************/
01574 #define  BKP_DR15_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
01575
01576 /*******************  Bit definition for BKP_DR16 register  *******************/
01577 #define  BKP_DR16_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
01578
01579 /*******************  Bit definition for BKP_DR17 register  *******************/
01580 #define  BKP_DR17_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
01581
01582 /******************  Bit definition for BKP_DR18 register  ********************/
01583 #define  BKP_DR18_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
01584
01585 /*******************  Bit definition for BKP_DR19 register  *******************/
01586 #define  BKP_DR19_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
01587
01588 /*******************  Bit definition for BKP_DR20 register  *******************/
01589 #define  BKP_DR20_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
01590
01591 /*******************  Bit definition for BKP_DR21 register  *******************/
01592 #define  BKP_DR21_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
01593
01594 /*******************  Bit definition for BKP_DR22 register  *******************/
01595 #define  BKP_DR22_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
01596
01597 /*******************  Bit definition for BKP_DR23 register  *******************/
01598 #define  BKP_DR23_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
01599
01600 /*******************  Bit definition for BKP_DR24 register  *******************/
01601 #define  BKP_DR24_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
01602
01603 /*******************  Bit definition for BKP_DR25 register  *******************/
01604 #define  BKP_DR25_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
01605
01606 /*******************  Bit definition for BKP_DR26 register  *******************/
01607 #define  BKP_DR26_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
01608
01609 /*******************  Bit definition for BKP_DR27 register  *******************/
01610 #define  BKP_DR27_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
01611
01612 /*******************  Bit definition for BKP_DR28 register  *******************/
01613 #define  BKP_DR28_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
01614
01615 /*******************  Bit definition for BKP_DR29 register  *******************/
01616 #define  BKP_DR29_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
01617
01618 /*******************  Bit definition for BKP_DR30 register  *******************/
01619 #define  BKP_DR30_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
01620
01621 /*******************  Bit definition for BKP_DR31 register  *******************/
01622 #define  BKP_DR31_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
01623
01624 /*******************  Bit definition for BKP_DR32 register  *******************/
01625 #define  BKP_DR32_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
01626
01627 /*******************  Bit definition for BKP_DR33 register  *******************/
01628 #define  BKP_DR33_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
01629
01630 /*******************  Bit definition for BKP_DR34 register  *******************/
01631 #define  BKP_DR34_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
01632
01633 /*******************  Bit definition for BKP_DR35 register  *******************/
01634 #define  BKP_DR35_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
01635
01636 /*******************  Bit definition for BKP_DR36 register  *******************/
01637 #define  BKP_DR36_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
01638
01639 /*******************  Bit definition for BKP_DR37 register  *******************/
01640 #define  BKP_DR37_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
01641
01642 /*******************  Bit definition for BKP_DR38 register  *******************/
01643 #define  BKP_DR38_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
01644
01645 /*******************  Bit definition for BKP_DR39 register  *******************/
01646 #define  BKP_DR39_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
01647
01648 /*******************  Bit definition for BKP_DR40 register  *******************/
01649 #define  BKP_DR40_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
01650
01651 /*******************  Bit definition for BKP_DR41 register  *******************/
01652 #define  BKP_DR41_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
01653
01654 /*******************  Bit definition for BKP_DR42 register  *******************/
01655 #define  BKP_DR42_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
01656
01657 /******************  Bit definition for BKP_RTCCR register  *******************/
01658 #define  BKP_RTCCR_CAL                       ((uint16_t)0x007F)     /*!< Calibration value */
01659 #define  BKP_RTCCR_CCO                       ((uint16_t)0x0080)     /*!< Calibration Clock Output */
01660 #define  BKP_RTCCR_ASOE                      ((uint16_t)0x0100)     /*!< Alarm or Second Output Enable */
01661 #define  BKP_RTCCR_ASOS                      ((uint16_t)0x0200)     /*!< Alarm or Second Output Selection */
01662
01663 /********************  Bit definition for BKP_CR register  ********************/
01664 #define  BKP_CR_TPE                          ((uint8_t)0x01)        /*!< TAMPER pin enable */
01665 #define  BKP_CR_TPAL                         ((uint8_t)0x02)        /*!< TAMPER pin active level */
01666
01667 /*******************  Bit definition for BKP_CSR register  ********************/
01668 #define  BKP_CSR_CTE                         ((uint16_t)0x0001)     /*!< Clear Tamper event */
01669 #define  BKP_CSR_CTI                         ((uint16_t)0x0002)     /*!< Clear Tamper Interrupt */
01670 #define  BKP_CSR_TPIE                        ((uint16_t)0x0004)     /*!< TAMPER Pin interrupt enable */
01671 #define  BKP_CSR_TEF                         ((uint16_t)0x0100)     /*!< Tamper Event Flag */
01672 #define  BKP_CSR_TIF                         ((uint16_t)0x0200)     /*!< Tamper Interrupt Flag */
01673
01674 /******************************************************************************/
01675 /*                                                                            */
01676 /*                         Reset and Clock Control                            */
01677 /*                                                                            */
01678 /******************************************************************************/
01679
01680 /********************  Bit definition for RCC_CR register  ********************/
01681 #define  RCC_CR_HSION                        ((uint32_t)0x00000001)        /*!< Internal High Speed clock enable */
01682 #define  RCC_CR_HSIRDY                       ((uint32_t)0x00000002)        /*!< Internal High Speed clock ready flag */
01683 #define  RCC_CR_HSITRIM                      ((uint32_t)0x000000F8)        /*!< Internal High Speed clock trimming */
01684 #define  RCC_CR_HSICAL                       ((uint32_t)0x0000FF00)        /*!< Internal High Speed clock Calibration */
01685 #define  RCC_CR_HSEON                        ((uint32_t)0x00010000)        /*!< External High Speed clock enable */
01686 #define  RCC_CR_HSERDY                       ((uint32_t)0x00020000)        /*!< External High Speed clock ready flag */
01687 #define  RCC_CR_HSEBYP                       ((uint32_t)0x00040000)        /*!< External High Speed clock Bypass */
01688 #define  RCC_CR_CSSON                        ((uint32_t)0x00080000)        /*!< Clock Security System enable */
01689 #define  RCC_CR_PLLON                        ((uint32_t)0x01000000)        /*!< PLL enable */
01690 #define  RCC_CR_PLLRDY                       ((uint32_t)0x02000000)        /*!< PLL clock ready flag */
01691
01692 #ifdef STM32F10X_CL
01693  #define  RCC_CR_PLL2ON                       ((uint32_t)0x04000000)        /*!< PLL2 enable */
01694  #define  RCC_CR_PLL2RDY                      ((uint32_t)0x08000000)        /*!< PLL2 clock ready flag */
01695  #define  RCC_CR_PLL3ON                       ((uint32_t)0x10000000)        /*!< PLL3 enable */
01696  #define  RCC_CR_PLL3RDY                      ((uint32_t)0x20000000)        /*!< PLL3 clock ready flag */
01697 #endif /* STM32F10X_CL */
01698
01699 /*******************  Bit definition for RCC_CFGR register  *******************/
01700 /*!< SW configuration */
01701 #define  RCC_CFGR_SW                         ((uint32_t)0x00000003)        /*!< SW[1:0] bits (System clock Switch) */
01702 #define  RCC_CFGR_SW_0                       ((uint32_t)0x00000001)        /*!< Bit 0 */
01703 #define  RCC_CFGR_SW_1                       ((uint32_t)0x00000002)        /*!< Bit 1 */
01704
01705 #define  RCC_CFGR_SW_HSI                     ((uint32_t)0x00000000)        /*!< HSI selected as system clock */
01706 #define  RCC_CFGR_SW_HSE                     ((uint32_t)0x00000001)        /*!< HSE selected as system clock */
01707 #define  RCC_CFGR_SW_PLL                     ((uint32_t)0x00000002)        /*!< PLL selected as system clock */
01708
01709 /*!< SWS configuration */
01710 #define  RCC_CFGR_SWS                        ((uint32_t)0x0000000C)        /*!< SWS[1:0] bits (System Clock Switch Status) */
01711 #define  RCC_CFGR_SWS_0                      ((uint32_t)0x00000004)        /*!< Bit 0 */
01712 #define  RCC_CFGR_SWS_1                      ((uint32_t)0x00000008)        /*!< Bit 1 */
01713
01714 #define  RCC_CFGR_SWS_HSI                    ((uint32_t)0x00000000)        /*!< HSI oscillator used as system clock */
01715 #define  RCC_CFGR_SWS_HSE                    ((uint32_t)0x00000004)        /*!< HSE oscillator used as system clock */
01716 #define  RCC_CFGR_SWS_PLL                    ((uint32_t)0x00000008)        /*!< PLL used as system clock */
01717
01718 /*!< HPRE configuration */
01719 #define  RCC_CFGR_HPRE                       ((uint32_t)0x000000F0)        /*!< HPRE[3:0] bits (AHB prescaler) */
01720 #define  RCC_CFGR_HPRE_0                     ((uint32_t)0x00000010)        /*!< Bit 0 */
01721 #define  RCC_CFGR_HPRE_1                     ((uint32_t)0x00000020)        /*!< Bit 1 */
01722 #define  RCC_CFGR_HPRE_2                     ((uint32_t)0x00000040)        /*!< Bit 2 */
01723 #define  RCC_CFGR_HPRE_3                     ((uint32_t)0x00000080)        /*!< Bit 3 */
01724
01725 #define  RCC_CFGR_HPRE_DIV1                  ((uint32_t)0x00000000)        /*!< SYSCLK not divided */
01726 #define  RCC_CFGR_HPRE_DIV2                  ((uint32_t)0x00000080)        /*!< SYSCLK divided by 2 */
01727 #define  RCC_CFGR_HPRE_DIV4                  ((uint32_t)0x00000090)        /*!< SYSCLK divided by 4 */
01728 #define  RCC_CFGR_HPRE_DIV8                  ((uint32_t)0x000000A0)        /*!< SYSCLK divided by 8 */
01729 #define  RCC_CFGR_HPRE_DIV16                 ((uint32_t)0x000000B0)        /*!< SYSCLK divided by 16 */
01730 #define  RCC_CFGR_HPRE_DIV64                 ((uint32_t)0x000000C0)        /*!< SYSCLK divided by 64 */
01731 #define  RCC_CFGR_HPRE_DIV128                ((uint32_t)0x000000D0)        /*!< SYSCLK divided by 128 */
01732 #define  RCC_CFGR_HPRE_DIV256                ((uint32_t)0x000000E0)        /*!< SYSCLK divided by 256 */
01733 #define  RCC_CFGR_HPRE_DIV512                ((uint32_t)0x000000F0)        /*!< SYSCLK divided by 512 */
01734
01735 /*!< PPRE1 configuration */
01736 #define  RCC_CFGR_PPRE1                      ((uint32_t)0x00000700)        /*!< PRE1[2:0] bits (APB1 prescaler) */
01737 #define  RCC_CFGR_PPRE1_0                    ((uint32_t)0x00000100)        /*!< Bit 0 */
01738 #define  RCC_CFGR_PPRE1_1                    ((uint32_t)0x00000200)        /*!< Bit 1 */
01739 #define  RCC_CFGR_PPRE1_2                    ((uint32_t)0x00000400)        /*!< Bit 2 */
01740
01741 #define  RCC_CFGR_PPRE1_DIV1                 ((uint32_t)0x00000000)        /*!< HCLK not divided */
01742 #define  RCC_CFGR_PPRE1_DIV2                 ((uint32_t)0x00000400)        /*!< HCLK divided by 2 */
01743 #define  RCC_CFGR_PPRE1_DIV4                 ((uint32_t)0x00000500)        /*!< HCLK divided by 4 */
01744 #define  RCC_CFGR_PPRE1_DIV8                 ((uint32_t)0x00000600)        /*!< HCLK divided by 8 */
01745 #define  RCC_CFGR_PPRE1_DIV16                ((uint32_t)0x00000700)        /*!< HCLK divided by 16 */
01746
01747 /*!< PPRE2 configuration */
01748 #define  RCC_CFGR_PPRE2                      ((uint32_t)0x00003800)        /*!< PRE2[2:0] bits (APB2 prescaler) */
01749 #define  RCC_CFGR_PPRE2_0                    ((uint32_t)0x00000800)        /*!< Bit 0 */
01750 #define  RCC_CFGR_PPRE2_1                    ((uint32_t)0x00001000)        /*!< Bit 1 */
01751 #define  RCC_CFGR_PPRE2_2                    ((uint32_t)0x00002000)        /*!< Bit 2 */
01752
01753 #define  RCC_CFGR_PPRE2_DIV1                 ((uint32_t)0x00000000)        /*!< HCLK not divided */
01754 #define  RCC_CFGR_PPRE2_DIV2                 ((uint32_t)0x00002000)        /*!< HCLK divided by 2 */
01755 #define  RCC_CFGR_PPRE2_DIV4                 ((uint32_t)0x00002800)        /*!< HCLK divided by 4 */
01756 #define  RCC_CFGR_PPRE2_DIV8                 ((uint32_t)0x00003000)        /*!< HCLK divided by 8 */
01757 #define  RCC_CFGR_PPRE2_DIV16                ((uint32_t)0x00003800)        /*!< HCLK divided by 16 */
01758
01759 /*!< ADCPPRE configuration */
01760 #define  RCC_CFGR_ADCPRE                     ((uint32_t)0x0000C000)        /*!< ADCPRE[1:0] bits (ADC prescaler) */
01761 #define  RCC_CFGR_ADCPRE_0                   ((uint32_t)0x00004000)        /*!< Bit 0 */
01762 #define  RCC_CFGR_ADCPRE_1                   ((uint32_t)0x00008000)        /*!< Bit 1 */
01763
01764 #define  RCC_CFGR_ADCPRE_DIV2                ((uint32_t)0x00000000)        /*!< PCLK2 divided by 2 */
01765 #define  RCC_CFGR_ADCPRE_DIV4                ((uint32_t)0x00004000)        /*!< PCLK2 divided by 4 */
01766 #define  RCC_CFGR_ADCPRE_DIV6                ((uint32_t)0x00008000)        /*!< PCLK2 divided by 6 */
01767 #define  RCC_CFGR_ADCPRE_DIV8                ((uint32_t)0x0000C000)        /*!< PCLK2 divided by 8 */
01768
01769 #define  RCC_CFGR_PLLSRC                     ((uint32_t)0x00010000)        /*!< PLL entry clock source */
01770
01771 #define  RCC_CFGR_PLLXTPRE                   ((uint32_t)0x00020000)        /*!< HSE divider for PLL entry */
01772
01773 /*!< PLLMUL configuration */
01774 #define  RCC_CFGR_PLLMULL                    ((uint32_t)0x003C0000)        /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
01775 #define  RCC_CFGR_PLLMULL_0                  ((uint32_t)0x00040000)        /*!< Bit 0 */
01776 #define  RCC_CFGR_PLLMULL_1                  ((uint32_t)0x00080000)        /*!< Bit 1 */
01777 #define  RCC_CFGR_PLLMULL_2                  ((uint32_t)0x00100000)        /*!< Bit 2 */
01778 #define  RCC_CFGR_PLLMULL_3                  ((uint32_t)0x00200000)        /*!< Bit 3 */
01779
01780 #ifdef STM32F10X_CL
01781  #define  RCC_CFGR_PLLSRC_HSI_Div2           ((uint32_t)0x00000000)        /*!< HSI clock divided by 2 selected as PLL entry clock source */
01782  #define  RCC_CFGR_PLLSRC_PREDIV1            ((uint32_t)0x00010000)        /*!< PREDIV1 clock selected as PLL entry clock source */
01783
01784  #define  RCC_CFGR_PLLXTPRE_PREDIV1          ((uint32_t)0x00000000)        /*!< PREDIV1 clock not divided for PLL entry */
01785  #define  RCC_CFGR_PLLXTPRE_PREDIV1_Div2     ((uint32_t)0x00020000)        /*!< PREDIV1 clock divided by 2 for PLL entry */
01786
01787  #define  RCC_CFGR_PLLMULL4                  ((uint32_t)0x00080000)        /*!< PLL input clock * 4 */
01788  #define  RCC_CFGR_PLLMULL5                  ((uint32_t)0x000C0000)        /*!< PLL input clock * 5 */
01789  #define  RCC_CFGR_PLLMULL6                  ((uint32_t)0x00100000)        /*!< PLL input clock * 6 */
01790  #define  RCC_CFGR_PLLMULL7                  ((uint32_t)0x00140000)        /*!< PLL input clock * 7 */
01791  #define  RCC_CFGR_PLLMULL8                  ((uint32_t)0x00180000)        /*!< PLL input clock * 8 */
01792  #define  RCC_CFGR_PLLMULL9                  ((uint32_t)0x001C0000)        /*!< PLL input clock * 9 */
01793  #define  RCC_CFGR_PLLMULL6_5                ((uint32_t)0x00340000)        /*!< PLL input clock * 6.5 */
01794
01795  #define  RCC_CFGR_OTGFSPRE                  ((uint32_t)0x00400000)        /*!< USB OTG FS prescaler */
01796
01797 /*!< MCO configuration */
01798  #define  RCC_CFGR_MCO                       ((uint32_t)0x0F000000)        /*!< MCO[3:0] bits (Microcontroller Clock Output) */
01799  #define  RCC_CFGR_MCO_0                     ((uint32_t)0x01000000)        /*!< Bit 0 */
01800  #define  RCC_CFGR_MCO_1                     ((uint32_t)0x02000000)        /*!< Bit 1 */
01801  #define  RCC_CFGR_MCO_2                     ((uint32_t)0x04000000)        /*!< Bit 2 */
01802  #define  RCC_CFGR_MCO_3                     ((uint32_t)0x08000000)        /*!< Bit 3 */
01803
01804  #define  RCC_CFGR_MCO_NOCLOCK               ((uint32_t)0x00000000)        /*!< No clock */
01805  #define  RCC_CFGR_MCO_SYSCLK                ((uint32_t)0x04000000)        /*!< System clock selected as MCO source */
01806  #define  RCC_CFGR_MCO_HSI                   ((uint32_t)0x05000000)        /*!< HSI clock selected as MCO source */
01807  #define  RCC_CFGR_MCO_HSE                   ((uint32_t)0x06000000)        /*!< HSE clock selected as MCO source */
01808  #define  RCC_CFGR_MCO_PLLCLK_Div2           ((uint32_t)0x07000000)        /*!< PLL clock divided by 2 selected as MCO source */
01809  #define  RCC_CFGR_MCO_PLL2CLK               ((uint32_t)0x08000000)        /*!< PLL2 clock selected as MCO source*/
01810  #define  RCC_CFGR_MCO_PLL3CLK_Div2          ((uint32_t)0x09000000)        /*!< PLL3 clock divided by 2 selected as MCO source*/
01811  #define  RCC_CFGR_MCO_Ext_HSE               ((uint32_t)0x0A000000)        /*!< XT1 external 3-25 MHz oscillator clock selected as MCO source */
01812  #define  RCC_CFGR_MCO_PLL3CLK               ((uint32_t)0x0B000000)        /*!< PLL3 clock selected as MCO source */
01813 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
01814  #define  RCC_CFGR_PLLSRC_HSI_Div2           ((uint32_t)0x00000000)        /*!< HSI clock divided by 2 selected as PLL entry clock source */
01815  #define  RCC_CFGR_PLLSRC_PREDIV1            ((uint32_t)0x00010000)        /*!< PREDIV1 clock selected as PLL entry clock source */
01816
01817  #define  RCC_CFGR_PLLXTPRE_PREDIV1          ((uint32_t)0x00000000)        /*!< PREDIV1 clock not divided for PLL entry */
01818  #define  RCC_CFGR_PLLXTPRE_PREDIV1_Div2     ((uint32_t)0x00020000)        /*!< PREDIV1 clock divided by 2 for PLL entry */
01819
01820  #define  RCC_CFGR_PLLMULL2                  ((uint32_t)0x00000000)        /*!< PLL input clock*2 */
01821  #define  RCC_CFGR_PLLMULL3                  ((uint32_t)0x00040000)        /*!< PLL input clock*3 */
01822  #define  RCC_CFGR_PLLMULL4                  ((uint32_t)0x00080000)        /*!< PLL input clock*4 */
01823  #define  RCC_CFGR_PLLMULL5                  ((uint32_t)0x000C0000)        /*!< PLL input clock*5 */
01824  #define  RCC_CFGR_PLLMULL6                  ((uint32_t)0x00100000)        /*!< PLL input clock*6 */
01825  #define  RCC_CFGR_PLLMULL7                  ((uint32_t)0x00140000)        /*!< PLL input clock*7 */
01826  #define  RCC_CFGR_PLLMULL8                  ((uint32_t)0x00180000)        /*!< PLL input clock*8 */
01827  #define  RCC_CFGR_PLLMULL9                  ((uint32_t)0x001C0000)        /*!< PLL input clock*9 */
01828  #define  RCC_CFGR_PLLMULL10                 ((uint32_t)0x00200000)        /*!< PLL input clock10 */
01829  #define  RCC_CFGR_PLLMULL11                 ((uint32_t)0x00240000)        /*!< PLL input clock*11 */
01830  #define  RCC_CFGR_PLLMULL12                 ((uint32_t)0x00280000)        /*!< PLL input clock*12 */
01831  #define  RCC_CFGR_PLLMULL13                 ((uint32_t)0x002C0000)        /*!< PLL input clock*13 */
01832  #define  RCC_CFGR_PLLMULL14                 ((uint32_t)0x00300000)        /*!< PLL input clock*14 */
01833  #define  RCC_CFGR_PLLMULL15                 ((uint32_t)0x00340000)        /*!< PLL input clock*15 */
01834  #define  RCC_CFGR_PLLMULL16                 ((uint32_t)0x00380000)        /*!< PLL input clock*16 */
01835
01836 /*!< MCO configuration */
01837  #define  RCC_CFGR_MCO                       ((uint32_t)0x07000000)        /*!< MCO[2:0] bits (Microcontroller Clock Output) */
01838  #define  RCC_CFGR_MCO_0                     ((uint32_t)0x01000000)        /*!< Bit 0 */
01839  #define  RCC_CFGR_MCO_1                     ((uint32_t)0x02000000)        /*!< Bit 1 */
01840  #define  RCC_CFGR_MCO_2                     ((uint32_t)0x04000000)        /*!< Bit 2 */
01841
01842  #define  RCC_CFGR_MCO_NOCLOCK               ((uint32_t)0x00000000)        /*!< No clock */
01843  #define  RCC_CFGR_MCO_SYSCLK                ((uint32_t)0x04000000)        /*!< System clock selected as MCO source */
01844  #define  RCC_CFGR_MCO_HSI                   ((uint32_t)0x05000000)        /*!< HSI clock selected as MCO source */
01845  #define  RCC_CFGR_MCO_HSE                   ((uint32_t)0x06000000)        /*!< HSE clock selected as MCO source  */
01846  #define  RCC_CFGR_MCO_PLL                   ((uint32_t)0x07000000)        /*!< PLL clock divided by 2 selected as MCO source */
01847 #else
01848  #define  RCC_CFGR_PLLSRC_HSI_Div2           ((uint32_t)0x00000000)        /*!< HSI clock divided by 2 selected as PLL entry clock source */
01849  #define  RCC_CFGR_PLLSRC_HSE                ((uint32_t)0x00010000)        /*!< HSE clock selected as PLL entry clock source */
01850
01851  #define  RCC_CFGR_PLLXTPRE_HSE              ((uint32_t)0x00000000)        /*!< HSE clock not divided for PLL entry */
01852  #define  RCC_CFGR_PLLXTPRE_HSE_Div2         ((uint32_t)0x00020000)        /*!< HSE clock divided by 2 for PLL entry */
01853
01854  #define  RCC_CFGR_PLLMULL2                  ((uint32_t)0x00000000)        /*!< PLL input clock*2 */
01855  #define  RCC_CFGR_PLLMULL3                  ((uint32_t)0x00040000)        /*!< PLL input clock*3 */
01856  #define  RCC_CFGR_PLLMULL4                  ((uint32_t)0x00080000)        /*!< PLL input clock*4 */
01857  #define  RCC_CFGR_PLLMULL5                  ((uint32_t)0x000C0000)        /*!< PLL input clock*5 */
01858  #define  RCC_CFGR_PLLMULL6                  ((uint32_t)0x00100000)        /*!< PLL input clock*6 */
01859  #define  RCC_CFGR_PLLMULL7                  ((uint32_t)0x00140000)        /*!< PLL input clock*7 */
01860  #define  RCC_CFGR_PLLMULL8                  ((uint32_t)0x00180000)        /*!< PLL input clock*8 */
01861  #define  RCC_CFGR_PLLMULL9                  ((uint32_t)0x001C0000)        /*!< PLL input clock*9 */
01862  #define  RCC_CFGR_PLLMULL10                 ((uint32_t)0x00200000)        /*!< PLL input clock10 */
01863  #define  RCC_CFGR_PLLMULL11                 ((uint32_t)0x00240000)        /*!< PLL input clock*11 */
01864  #define  RCC_CFGR_PLLMULL12                 ((uint32_t)0x00280000)        /*!< PLL input clock*12 */
01865  #define  RCC_CFGR_PLLMULL13                 ((uint32_t)0x002C0000)        /*!< PLL input clock*13 */
01866  #define  RCC_CFGR_PLLMULL14                 ((uint32_t)0x00300000)        /*!< PLL input clock*14 */
01867  #define  RCC_CFGR_PLLMULL15                 ((uint32_t)0x00340000)        /*!< PLL input clock*15 */
01868  #define  RCC_CFGR_PLLMULL16                 ((uint32_t)0x00380000)        /*!< PLL input clock*16 */
01869  #define  RCC_CFGR_USBPRE                    ((uint32_t)0x00400000)        /*!< USB Device prescaler */
01870
01871 /*!< MCO configuration */
01872  #define  RCC_CFGR_MCO                       ((uint32_t)0x07000000)        /*!< MCO[2:0] bits (Microcontroller Clock Output) */
01873  #define  RCC_CFGR_MCO_0                     ((uint32_t)0x01000000)        /*!< Bit 0 */
01874  #define  RCC_CFGR_MCO_1                     ((uint32_t)0x02000000)        /*!< Bit 1 */
01875  #define  RCC_CFGR_MCO_2                     ((uint32_t)0x04000000)        /*!< Bit 2 */
01876
01877  #define  RCC_CFGR_MCO_NOCLOCK               ((uint32_t)0x00000000)        /*!< No clock */
01878  #define  RCC_CFGR_MCO_SYSCLK                ((uint32_t)0x04000000)        /*!< System clock selected as MCO source */
01879  #define  RCC_CFGR_MCO_HSI                   ((uint32_t)0x05000000)        /*!< HSI clock selected as MCO source */
01880  #define  RCC_CFGR_MCO_HSE                   ((uint32_t)0x06000000)        /*!< HSE clock selected as MCO source  */
01881  #define  RCC_CFGR_MCO_PLL                   ((uint32_t)0x07000000)        /*!< PLL clock divided by 2 selected as MCO source */
01882 #endif /* STM32F10X_CL */
01883
01884 /*!<******************  Bit definition for RCC_CIR register  ********************/
01885 #define  RCC_CIR_LSIRDYF                     ((uint32_t)0x00000001)        /*!< LSI Ready Interrupt flag */
01886 #define  RCC_CIR_LSERDYF                     ((uint32_t)0x00000002)        /*!< LSE Ready Interrupt flag */
01887 #define  RCC_CIR_HSIRDYF                     ((uint32_t)0x00000004)        /*!< HSI Ready Interrupt flag */
01888 #define  RCC_CIR_HSERDYF                     ((uint32_t)0x00000008)        /*!< HSE Ready Interrupt flag */
01889 #define  RCC_CIR_PLLRDYF                     ((uint32_t)0x00000010)        /*!< PLL Ready Interrupt flag */
01890 #define  RCC_CIR_CSSF                        ((uint32_t)0x00000080)        /*!< Clock Security System Interrupt flag */
01891 #define  RCC_CIR_LSIRDYIE                    ((uint32_t)0x00000100)        /*!< LSI Ready Interrupt Enable */
01892 #define  RCC_CIR_LSERDYIE                    ((uint32_t)0x00000200)        /*!< LSE Ready Interrupt Enable */
01893 #define  RCC_CIR_HSIRDYIE                    ((uint32_t)0x00000400)        /*!< HSI Ready Interrupt Enable */
01894 #define  RCC_CIR_HSERDYIE                    ((uint32_t)0x00000800)        /*!< HSE Ready Interrupt Enable */
01895 #define  RCC_CIR_PLLRDYIE                    ((uint32_t)0x00001000)        /*!< PLL Ready Interrupt Enable */
01896 #define  RCC_CIR_LSIRDYC                     ((uint32_t)0x00010000)        /*!< LSI Ready Interrupt Clear */
01897 #define  RCC_CIR_LSERDYC                     ((uint32_t)0x00020000)        /*!< LSE Ready Interrupt Clear */
01898 #define  RCC_CIR_HSIRDYC                     ((uint32_t)0x00040000)        /*!< HSI Ready Interrupt Clear */
01899 #define  RCC_CIR_HSERDYC                     ((uint32_t)0x00080000)        /*!< HSE Ready Interrupt Clear */
01900 #define  RCC_CIR_PLLRDYC                     ((uint32_t)0x00100000)        /*!< PLL Ready Interrupt Clear */
01901 #define  RCC_CIR_CSSC                        ((uint32_t)0x00800000)        /*!< Clock Security System Interrupt Clear */
01902
01903 #ifdef STM32F10X_CL
01904  #define  RCC_CIR_PLL2RDYF                    ((uint32_t)0x00000020)        /*!< PLL2 Ready Interrupt flag */
01905  #define  RCC_CIR_PLL3RDYF                    ((uint32_t)0x00000040)        /*!< PLL3 Ready Interrupt flag */
01906  #define  RCC_CIR_PLL2RDYIE                   ((uint32_t)0x00002000)        /*!< PLL2 Ready Interrupt Enable */
01907  #define  RCC_CIR_PLL3RDYIE                   ((uint32_t)0x00004000)        /*!< PLL3 Ready Interrupt Enable */
01908  #define  RCC_CIR_PLL2RDYC                    ((uint32_t)0x00200000)        /*!< PLL2 Ready Interrupt Clear */
01909  #define  RCC_CIR_PLL3RDYC                    ((uint32_t)0x00400000)        /*!< PLL3 Ready Interrupt Clear */
01910 #endif /* STM32F10X_CL */
01911
01912 /*****************  Bit definition for RCC_APB2RSTR register  *****************/
01913 #define  RCC_APB2RSTR_AFIORST                ((uint32_t)0x00000001)        /*!< Alternate Function I/O reset */
01914 #define  RCC_APB2RSTR_IOPARST                ((uint32_t)0x00000004)        /*!< I/O port A reset */
01915 #define  RCC_APB2RSTR_IOPBRST                ((uint32_t)0x00000008)        /*!< I/O port B reset */
01916 #define  RCC_APB2RSTR_IOPCRST                ((uint32_t)0x00000010)        /*!< I/O port C reset */
01917 #define  RCC_APB2RSTR_IOPDRST                ((uint32_t)0x00000020)        /*!< I/O port D reset */
01918 #define  RCC_APB2RSTR_ADC1RST                ((uint32_t)0x00000200)        /*!< ADC 1 interface reset */
01919
01920 #if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL)
01921 #define  RCC_APB2RSTR_ADC2RST                ((uint32_t)0x00000400)        /*!< ADC 2 interface reset */
01922 #endif
01923
01924 #define  RCC_APB2RSTR_TIM1RST                ((uint32_t)0x00000800)        /*!< TIM1 Timer reset */
01925 #define  RCC_APB2RSTR_SPI1RST                ((uint32_t)0x00001000)        /*!< SPI 1 reset */
01926 #define  RCC_APB2RSTR_USART1RST              ((uint32_t)0x00004000)        /*!< USART1 reset */
01927
01928 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
01929 #define  RCC_APB2RSTR_TIM15RST               ((uint32_t)0x00010000)        /*!< TIM15 Timer reset */
01930 #define  RCC_APB2RSTR_TIM16RST               ((uint32_t)0x00020000)        /*!< TIM16 Timer reset */
01931 #define  RCC_APB2RSTR_TIM17RST               ((uint32_t)0x00040000)        /*!< TIM17 Timer reset */
01932 #endif
01933
01934 #if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)
01935  #define  RCC_APB2RSTR_IOPERST               ((uint32_t)0x00000040)        /*!< I/O port E reset */
01936 #endif /* STM32F10X_LD && STM32F10X_LD_VL */
01937
01938 #if defined (STM32F10X_HD) || defined (STM32F10X_XL)
01939  #define  RCC_APB2RSTR_IOPFRST               ((uint32_t)0x00000080)        /*!< I/O port F reset */
01940  #define  RCC_APB2RSTR_IOPGRST               ((uint32_t)0x00000100)        /*!< I/O port G reset */
01941  #define  RCC_APB2RSTR_TIM8RST               ((uint32_t)0x00002000)        /*!< TIM8 Timer reset */
01942  #define  RCC_APB2RSTR_ADC3RST               ((uint32_t)0x00008000)        /*!< ADC3 interface reset */
01943 #endif
01944
01945 #if defined (STM32F10X_HD_VL)
01946  #define  RCC_APB2RSTR_IOPFRST               ((uint32_t)0x00000080)        /*!< I/O port F reset */
01947  #define  RCC_APB2RSTR_IOPGRST               ((uint32_t)0x00000100)        /*!< I/O port G reset */
01948 #endif
01949
01950 #ifdef STM32F10X_XL
01951  #define  RCC_APB2RSTR_TIM9RST               ((uint32_t)0x00080000)         /*!< TIM9 Timer reset */
01952  #define  RCC_APB2RSTR_TIM10RST              ((uint32_t)0x00100000)         /*!< TIM10 Timer reset */
01953  #define  RCC_APB2RSTR_TIM11RST              ((uint32_t)0x00200000)         /*!< TIM11 Timer reset */
01954 #endif /* STM32F10X_XL */
01955
01956 /*****************  Bit definition for RCC_APB1RSTR register  *****************/
01957 #define  RCC_APB1RSTR_TIM2RST                ((uint32_t)0x00000001)        /*!< Timer 2 reset */
01958 #define  RCC_APB1RSTR_TIM3RST                ((uint32_t)0x00000002)        /*!< Timer 3 reset */
01959 #define  RCC_APB1RSTR_WWDGRST                ((uint32_t)0x00000800)        /*!< Window Watchdog reset */
01960 #define  RCC_APB1RSTR_USART2RST              ((uint32_t)0x00020000)        /*!< USART 2 reset */
01961 #define  RCC_APB1RSTR_I2C1RST                ((uint32_t)0x00200000)        /*!< I2C 1 reset */
01962
01963 #if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL)
01964 #define  RCC_APB1RSTR_CAN1RST                ((uint32_t)0x02000000)        /*!< CAN1 reset */
01965 #endif
01966
01967 #define  RCC_APB1RSTR_BKPRST                 ((uint32_t)0x08000000)        /*!< Backup interface reset */
01968 #define  RCC_APB1RSTR_PWRRST                 ((uint32_t)0x10000000)        /*!< Power interface reset */
01969
01970 #if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)
01971  #define  RCC_APB1RSTR_TIM4RST               ((uint32_t)0x00000004)        /*!< Timer 4 reset */
01972  #define  RCC_APB1RSTR_SPI2RST               ((uint32_t)0x00004000)        /*!< SPI 2 reset */
01973  #define  RCC_APB1RSTR_USART3RST             ((uint32_t)0x00040000)        /*!< USART 3 reset */
01974  #define  RCC_APB1RSTR_I2C2RST               ((uint32_t)0x00400000)        /*!< I2C 2 reset */
01975 #endif /* STM32F10X_LD && STM32F10X_LD_VL */
01976
01977 #if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD) || defined  (STM32F10X_XL)
01978  #define  RCC_APB1RSTR_USBRST                ((uint32_t)0x00800000)        /*!< USB Device reset */
01979 #endif
01980
01981 #if defined (STM32F10X_HD) || defined  (STM32F10X_CL) || defined  (STM32F10X_XL)
01982  #define  RCC_APB1RSTR_TIM5RST                ((uint32_t)0x00000008)        /*!< Timer 5 reset */
01983  #define  RCC_APB1RSTR_TIM6RST                ((uint32_t)0x00000010)        /*!< Timer 6 reset */
01984  #define  RCC_APB1RSTR_TIM7RST                ((uint32_t)0x00000020)        /*!< Timer 7 reset */
01985  #define  RCC_APB1RSTR_SPI3RST                ((uint32_t)0x00008000)        /*!< SPI 3 reset */
01986  #define  RCC_APB1RSTR_UART4RST               ((uint32_t)0x00080000)        /*!< UART 4 reset */
01987  #define  RCC_APB1RSTR_UART5RST               ((uint32_t)0x00100000)        /*!< UART 5 reset */
01988  #define  RCC_APB1RSTR_DACRST                 ((uint32_t)0x20000000)        /*!< DAC interface reset */
01989 #endif
01990
01991 #if defined (STM32F10X_LD_VL) || defined  (STM32F10X_MD_VL) || defined  (STM32F10X_HD_VL)
01992  #define  RCC_APB1RSTR_TIM6RST                ((uint32_t)0x00000010)        /*!< Timer 6 reset */
01993  #define  RCC_APB1RSTR_TIM7RST                ((uint32_t)0x00000020)        /*!< Timer 7 reset */
01994  #define  RCC_APB1RSTR_DACRST                 ((uint32_t)0x20000000)        /*!< DAC interface reset */
01995  #define  RCC_APB1RSTR_CECRST                 ((uint32_t)0x40000000)        /*!< CEC interface reset */
01996 #endif
01997
01998 #if defined  (STM32F10X_HD_VL)
01999  #define  RCC_APB1RSTR_TIM5RST                ((uint32_t)0x00000008)        /*!< Timer 5 reset */
02000  #define  RCC_APB1RSTR_TIM12RST               ((uint32_t)0x00000040)        /*!< TIM12 Timer reset */
02001  #define  RCC_APB1RSTR_TIM13RST               ((uint32_t)0x00000080)        /*!< TIM13 Timer reset */
02002  #define  RCC_APB1RSTR_TIM14RST               ((uint32_t)0x00000100)        /*!< TIM14 Timer reset */
02003  #define  RCC_APB1RSTR_SPI3RST                ((uint32_t)0x00008000)        /*!< SPI 3 reset */
02004  #define  RCC_APB1RSTR_UART4RST               ((uint32_t)0x00080000)        /*!< UART 4 reset */
02005  #define  RCC_APB1RSTR_UART5RST               ((uint32_t)0x00100000)        /*!< UART 5 reset */
02006 #endif
02007
02008 #ifdef STM32F10X_CL
02009  #define  RCC_APB1RSTR_CAN2RST                ((uint32_t)0x04000000)        /*!< CAN2 reset */
02010 #endif /* STM32F10X_CL */
02011
02012 #ifdef STM32F10X_XL
02013  #define  RCC_APB1RSTR_TIM12RST               ((uint32_t)0x00000040)         /*!< TIM12 Timer reset */
02014  #define  RCC_APB1RSTR_TIM13RST               ((uint32_t)0x00000080)         /*!< TIM13 Timer reset */
02015  #define  RCC_APB1RSTR_TIM14RST               ((uint32_t)0x00000100)         /*!< TIM14 Timer reset */
02016 #endif /* STM32F10X_XL */
02017
02018 /******************  Bit definition for RCC_AHBENR register  ******************/
02019 #define  RCC_AHBENR_DMA1EN                   ((uint16_t)0x0001)            /*!< DMA1 clock enable */
02020 #define  RCC_AHBENR_SRAMEN                   ((uint16_t)0x0004)            /*!< SRAM interface clock enable */
02021 #define  RCC_AHBENR_FLITFEN                  ((uint16_t)0x0010)            /*!< FLITF clock enable */
02022 #define  RCC_AHBENR_CRCEN                    ((uint16_t)0x0040)            /*!< CRC clock enable */
02023
02024 #if defined (STM32F10X_HD) || defined  (STM32F10X_CL) || defined  (STM32F10X_HD_VL)
02025  #define  RCC_AHBENR_DMA2EN                  ((uint16_t)0x0002)            /*!< DMA2 clock enable */
02026 #endif
02027
02028 #if defined (STM32F10X_HD) || defined (STM32F10X_XL)
02029  #define  RCC_AHBENR_FSMCEN                  ((uint16_t)0x0100)            /*!< FSMC clock enable */
02030  #define  RCC_AHBENR_SDIOEN                  ((uint16_t)0x0400)            /*!< SDIO clock enable */
02031 #endif
02032
02033 #if defined (STM32F10X_HD_VL)
02034  #define  RCC_AHBENR_FSMCEN                  ((uint16_t)0x0100)            /*!< FSMC clock enable */
02035 #endif
02036
02037 #ifdef STM32F10X_CL
02038  #define  RCC_AHBENR_OTGFSEN                 ((uint32_t)0x00001000)         /*!< USB OTG FS clock enable */
02039  #define  RCC_AHBENR_ETHMACEN                ((uint32_t)0x00004000)         /*!< ETHERNET MAC clock enable */
02040  #define  RCC_AHBENR_ETHMACTXEN              ((uint32_t)0x00008000)         /*!< ETHERNET MAC Tx clock enable */
02041  #define  RCC_AHBENR_ETHMACRXEN              ((uint32_t)0x00010000)         /*!< ETHERNET MAC Rx clock enable */
02042 #endif /* STM32F10X_CL */
02043
02044 /******************  Bit definition for RCC_APB2ENR register  *****************/
02045 #define  RCC_APB2ENR_AFIOEN                  ((uint32_t)0x00000001)         /*!< Alternate Function I/O clock enable */
02046 #define  RCC_APB2ENR_IOPAEN                  ((uint32_t)0x00000004)         /*!< I/O port A clock enable */
02047 #define  RCC_APB2ENR_IOPBEN                  ((uint32_t)0x00000008)         /*!< I/O port B clock enable */
02048 #define  RCC_APB2ENR_IOPCEN                  ((uint32_t)0x00000010)         /*!< I/O port C clock enable */
02049 #define  RCC_APB2ENR_IOPDEN                  ((uint32_t)0x00000020)         /*!< I/O port D clock enable */
02050 #define  RCC_APB2ENR_ADC1EN                  ((uint32_t)0x00000200)         /*!< ADC 1 interface clock enable */
02051
02052 #if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL)
02053 #define  RCC_APB2ENR_ADC2EN                  ((uint32_t)0x00000400)         /*!< ADC 2 interface clock enable */
02054 #endif
02055
02056 #define  RCC_APB2ENR_TIM1EN                  ((uint32_t)0x00000800)         /*!< TIM1 Timer clock enable */
02057 #define  RCC_APB2ENR_SPI1EN                  ((uint32_t)0x00001000)         /*!< SPI 1 clock enable */
02058 #define  RCC_APB2ENR_USART1EN                ((uint32_t)0x00004000)         /*!< USART1 clock enable */
02059
02060 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
02061 #define  RCC_APB2ENR_TIM15EN                 ((uint32_t)0x00010000)         /*!< TIM15 Timer clock enable */
02062 #define  RCC_APB2ENR_TIM16EN                 ((uint32_t)0x00020000)         /*!< TIM16 Timer clock enable */
02063 #define  RCC_APB2ENR_TIM17EN                 ((uint32_t)0x00040000)         /*!< TIM17 Timer clock enable */
02064 #endif
02065
02066 #if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)
02067  #define  RCC_APB2ENR_IOPEEN                 ((uint32_t)0x00000040)         /*!< I/O port E clock enable */
02068 #endif /* STM32F10X_LD && STM32F10X_LD_VL */
02069
02070 #if defined (STM32F10X_HD) || defined (STM32F10X_XL)
02071  #define  RCC_APB2ENR_IOPFEN                 ((uint32_t)0x00000080)         /*!< I/O port F clock enable */
02072  #define  RCC_APB2ENR_IOPGEN                 ((uint32_t)0x00000100)         /*!< I/O port G clock enable */
02073  #define  RCC_APB2ENR_TIM8EN                 ((uint32_t)0x00002000)         /*!< TIM8 Timer clock enable */
02074  #define  RCC_APB2ENR_ADC3EN                 ((uint32_t)0x00008000)         /*!< DMA1 clock enable */
02075 #endif
02076
02077 #if defined (STM32F10X_HD_VL)
02078  #define  RCC_APB2ENR_IOPFEN                 ((uint32_t)0x00000080)         /*!< I/O port F clock enable */
02079  #define  RCC_APB2ENR_IOPGEN                 ((uint32_t)0x00000100)         /*!< I/O port G clock enable */
02080 #endif
02081
02082 #ifdef STM32F10X_XL
02083  #define  RCC_APB2ENR_TIM9EN                 ((uint32_t)0x00080000)         /*!< TIM9 Timer clock enable  */
02084  #define  RCC_APB2ENR_TIM10EN                ((uint32_t)0x00100000)         /*!< TIM10 Timer clock enable  */
02085  #define  RCC_APB2ENR_TIM11EN                ((uint32_t)0x00200000)         /*!< TIM11 Timer clock enable */
02086 #endif
02087
02088 /*****************  Bit definition for RCC_APB1ENR register  ******************/
02089 #define  RCC_APB1ENR_TIM2EN                  ((uint32_t)0x00000001)        /*!< Timer 2 clock enabled*/
02090 #define  RCC_APB1ENR_TIM3EN                  ((uint32_t)0x00000002)        /*!< Timer 3 clock enable */
02091 #define  RCC_APB1ENR_WWDGEN                  ((uint32_t)0x00000800)        /*!< Window Watchdog clock enable */
02092 #define  RCC_APB1ENR_USART2EN                ((uint32_t)0x00020000)        /*!< USART 2 clock enable */
02093 #define  RCC_APB1ENR_I2C1EN                  ((uint32_t)0x00200000)        /*!< I2C 1 clock enable */
02094
02095 #if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL)
02096 #define  RCC_APB1ENR_CAN1EN                  ((uint32_t)0x02000000)        /*!< CAN1 clock enable */
02097 #endif
02098
02099 #define  RCC_APB1ENR_BKPEN                   ((uint32_t)0x08000000)        /*!< Backup interface clock enable */
02100 #define  RCC_APB1ENR_PWREN                   ((uint32_t)0x10000000)        /*!< Power interface clock enable */
02101
02102 #if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)
02103  #define  RCC_APB1ENR_TIM4EN                 ((uint32_t)0x00000004)        /*!< Timer 4 clock enable */
02104  #define  RCC_APB1ENR_SPI2EN                 ((uint32_t)0x00004000)        /*!< SPI 2 clock enable */
02105  #define  RCC_APB1ENR_USART3EN               ((uint32_t)0x00040000)        /*!< USART 3 clock enable */
02106  #define  RCC_APB1ENR_I2C2EN                 ((uint32_t)0x00400000)        /*!< I2C 2 clock enable */
02107 #endif /* STM32F10X_LD && STM32F10X_LD_VL */
02108
02109 #if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined  (STM32F10X_LD)
02110  #define  RCC_APB1ENR_USBEN                  ((uint32_t)0x00800000)        /*!< USB Device clock enable */
02111 #endif
02112
02113 #if defined (STM32F10X_HD) || defined  (STM32F10X_CL)
02114  #define  RCC_APB1ENR_TIM5EN                 ((uint32_t)0x00000008)        /*!< Timer 5 clock enable */
02115  #define  RCC_APB1ENR_TIM6EN                 ((uint32_t)0x00000010)        /*!< Timer 6 clock enable */
02116  #define  RCC_APB1ENR_TIM7EN                 ((uint32_t)0x00000020)        /*!< Timer 7 clock enable */
02117  #define  RCC_APB1ENR_SPI3EN                 ((uint32_t)0x00008000)        /*!< SPI 3 clock enable */
02118  #define  RCC_APB1ENR_UART4EN                ((uint32_t)0x00080000)        /*!< UART 4 clock enable */
02119  #define  RCC_APB1ENR_UART5EN                ((uint32_t)0x00100000)        /*!< UART 5 clock enable */
02120  #define  RCC_APB1ENR_DACEN                  ((uint32_t)0x20000000)        /*!< DAC interface clock enable */
02121 #endif
02122
02123 #if defined (STM32F10X_LD_VL) || defined  (STM32F10X_MD_VL) || defined  (STM32F10X_HD_VL)
02124  #define  RCC_APB1ENR_TIM6EN                 ((uint32_t)0x00000010)        /*!< Timer 6 clock enable */
02125  #define  RCC_APB1ENR_TIM7EN                 ((uint32_t)0x00000020)        /*!< Timer 7 clock enable */
02126  #define  RCC_APB1ENR_DACEN                  ((uint32_t)0x20000000)        /*!< DAC interface clock enable */
02127  #define  RCC_APB1ENR_CECEN                  ((uint32_t)0x40000000)        /*!< CEC interface clock enable */
02128 #endif
02129
02130 #ifdef STM32F10X_HD_VL
02131  #define  RCC_APB1ENR_TIM5EN                 ((uint32_t)0x00000008)        /*!< Timer 5 clock enable */
02132  #define  RCC_APB1ENR_TIM12EN                ((uint32_t)0x00000040)         /*!< TIM12 Timer clock enable  */
02133  #define  RCC_APB1ENR_TIM13EN                ((uint32_t)0x00000080)         /*!< TIM13 Timer clock enable  */
02134  #define  RCC_APB1ENR_TIM14EN                ((uint32_t)0x00000100)         /*!< TIM14 Timer clock enable */
02135  #define  RCC_APB1ENR_SPI3EN                 ((uint32_t)0x00008000)        /*!< SPI 3 clock enable */
02136  #define  RCC_APB1ENR_UART4EN                ((uint32_t)0x00080000)        /*!< UART 4 clock enable */
02137  #define  RCC_APB1ENR_UART5EN                ((uint32_t)0x00100000)        /*!< UART 5 clock enable */
02138 #endif /* STM32F10X_HD_VL */
02139
02140 #ifdef STM32F10X_CL
02141  #define  RCC_APB1ENR_CAN2EN                  ((uint32_t)0x04000000)        /*!< CAN2 clock enable */
02142 #endif /* STM32F10X_CL */
02143
02144 #ifdef STM32F10X_XL
02145  #define  RCC_APB1ENR_TIM12EN                ((uint32_t)0x00000040)         /*!< TIM12 Timer clock enable  */
02146  #define  RCC_APB1ENR_TIM13EN                ((uint32_t)0x00000080)         /*!< TIM13 Timer clock enable  */
02147  #define  RCC_APB1ENR_TIM14EN                ((uint32_t)0x00000100)         /*!< TIM14 Timer clock enable */
02148 #endif /* STM32F10X_XL */
02149
02150 /*******************  Bit definition for RCC_BDCR register  *******************/
02151 #define  RCC_BDCR_LSEON                      ((uint32_t)0x00000001)        /*!< External Low Speed oscillator enable */
02152 #define  RCC_BDCR_LSERDY                     ((uint32_t)0x00000002)        /*!< External Low Speed oscillator Ready */
02153 #define  RCC_BDCR_LSEBYP                     ((uint32_t)0x00000004)        /*!< External Low Speed oscillator Bypass */
02154
02155 #define  RCC_BDCR_RTCSEL                     ((uint32_t)0x00000300)        /*!< RTCSEL[1:0] bits (RTC clock source selection) */
02156 #define  RCC_BDCR_RTCSEL_0                   ((uint32_t)0x00000100)        /*!< Bit 0 */
02157 #define  RCC_BDCR_RTCSEL_1                   ((uint32_t)0x00000200)        /*!< Bit 1 */
02158
02159 /*!< RTC congiguration */
02160 #define  RCC_BDCR_RTCSEL_NOCLOCK             ((uint32_t)0x00000000)        /*!< No clock */
02161 #define  RCC_BDCR_RTCSEL_LSE                 ((uint32_t)0x00000100)        /*!< LSE oscillator clock used as RTC clock */
02162 #define  RCC_BDCR_RTCSEL_LSI                 ((uint32_t)0x00000200)        /*!< LSI oscillator clock used as RTC clock */
02163 #define  RCC_BDCR_RTCSEL_HSE                 ((uint32_t)0x00000300)        /*!< HSE oscillator clock divided by 128 used as RTC clock */
02164
02165 #define  RCC_BDCR_RTCEN                      ((uint32_t)0x00008000)        /*!< RTC clock enable */
02166 #define  RCC_BDCR_BDRST                      ((uint32_t)0x00010000)        /*!< Backup domain software reset  */
02167
02168 /*******************  Bit definition for RCC_CSR register  ********************/
02169 #define  RCC_CSR_LSION                       ((uint32_t)0x00000001)        /*!< Internal Low Speed oscillator enable */
02170 #define  RCC_CSR_LSIRDY                      ((uint32_t)0x00000002)        /*!< Internal Low Speed oscillator Ready */
02171 #define  RCC_CSR_RMVF                        ((uint32_t)0x01000000)        /*!< Remove reset flag */
02172 #define  RCC_CSR_PINRSTF                     ((uint32_t)0x04000000)        /*!< PIN reset flag */
02173 #define  RCC_CSR_PORRSTF                     ((uint32_t)0x08000000)        /*!< POR/PDR reset flag */
02174 #define  RCC_CSR_SFTRSTF                     ((uint32_t)0x10000000)        /*!< Software Reset flag */
02175 #define  RCC_CSR_IWDGRSTF                    ((uint32_t)0x20000000)        /*!< Independent Watchdog reset flag */
02176 #define  RCC_CSR_WWDGRSTF                    ((uint32_t)0x40000000)        /*!< Window watchdog reset flag */
02177 #define  RCC_CSR_LPWRRSTF                    ((uint32_t)0x80000000)        /*!< Low-Power reset flag */
02178
02179 #ifdef STM32F10X_CL
02180 /*******************  Bit definition for RCC_AHBRSTR register  ****************/
02181  #define  RCC_AHBRSTR_OTGFSRST               ((uint32_t)0x00001000)         /*!< USB OTG FS reset */
02182  #define  RCC_AHBRSTR_ETHMACRST              ((uint32_t)0x00004000)         /*!< ETHERNET MAC reset */
02183
02184 /*******************  Bit definition for RCC_CFGR2 register  ******************/
02185 /*!< PREDIV1 configuration */
02186  #define  RCC_CFGR2_PREDIV1                  ((uint32_t)0x0000000F)        /*!< PREDIV1[3:0] bits */
02187  #define  RCC_CFGR2_PREDIV1_0                ((uint32_t)0x00000001)        /*!< Bit 0 */
02188  #define  RCC_CFGR2_PREDIV1_1                ((uint32_t)0x00000002)        /*!< Bit 1 */
02189  #define  RCC_CFGR2_PREDIV1_2                ((uint32_t)0x00000004)        /*!< Bit 2 */
02190  #define  RCC_CFGR2_PREDIV1_3                ((uint32_t)0x00000008)        /*!< Bit 3 */
02191
02192  #define  RCC_CFGR2_PREDIV1_DIV1             ((uint32_t)0x00000000)        /*!< PREDIV1 input clock not divided */
02193  #define  RCC_CFGR2_PREDIV1_DIV2             ((uint32_t)0x00000001)        /*!< PREDIV1 input clock divided by 2 */
02194  #define  RCC_CFGR2_PREDIV1_DIV3             ((uint32_t)0x00000002)        /*!< PREDIV1 input clock divided by 3 */
02195  #define  RCC_CFGR2_PREDIV1_DIV4             ((uint32_t)0x00000003)        /*!< PREDIV1 input clock divided by 4 */
02196  #define  RCC_CFGR2_PREDIV1_DIV5             ((uint32_t)0x00000004)        /*!< PREDIV1 input clock divided by 5 */
02197  #define  RCC_CFGR2_PREDIV1_DIV6             ((uint32_t)0x00000005)        /*!< PREDIV1 input clock divided by 6 */
02198  #define  RCC_CFGR2_PREDIV1_DIV7             ((uint32_t)0x00000006)        /*!< PREDIV1 input clock divided by 7 */
02199  #define  RCC_CFGR2_PREDIV1_DIV8             ((uint32_t)0x00000007)        /*!< PREDIV1 input clock divided by 8 */
02200  #define  RCC_CFGR2_PREDIV1_DIV9             ((uint32_t)0x00000008)        /*!< PREDIV1 input clock divided by 9 */
02201  #define  RCC_CFGR2_PREDIV1_DIV10            ((uint32_t)0x00000009)        /*!< PREDIV1 input clock divided by 10 */
02202  #define  RCC_CFGR2_PREDIV1_DIV11            ((uint32_t)0x0000000A)        /*!< PREDIV1 input clock divided by 11 */
02203  #define  RCC_CFGR2_PREDIV1_DIV12            ((uint32_t)0x0000000B)        /*!< PREDIV1 input clock divided by 12 */
02204  #define  RCC_CFGR2_PREDIV1_DIV13            ((uint32_t)0x0000000C)        /*!< PREDIV1 input clock divided by 13 */
02205  #define  RCC_CFGR2_PREDIV1_DIV14            ((uint32_t)0x0000000D)        /*!< PREDIV1 input clock divided by 14 */
02206  #define  RCC_CFGR2_PREDIV1_DIV15            ((uint32_t)0x0000000E)        /*!< PREDIV1 input clock divided by 15 */
02207  #define  RCC_CFGR2_PREDIV1_DIV16            ((uint32_t)0x0000000F)        /*!< PREDIV1 input clock divided by 16 */
02208
02209 /*!< PREDIV2 configuration */
02210  #define  RCC_CFGR2_PREDIV2                  ((uint32_t)0x000000F0)        /*!< PREDIV2[3:0] bits */
02211  #define  RCC_CFGR2_PREDIV2_0                ((uint32_t)0x00000010)        /*!< Bit 0 */
02212  #define  RCC_CFGR2_PREDIV2_1                ((uint32_t)0x00000020)        /*!< Bit 1 */
02213  #define  RCC_CFGR2_PREDIV2_2                ((uint32_t)0x00000040)        /*!< Bit 2 */
02214  #define  RCC_CFGR2_PREDIV2_3                ((uint32_t)0x00000080)        /*!< Bit 3 */
02215
02216  #define  RCC_CFGR2_PREDIV2_DIV1             ((uint32_t)0x00000000)        /*!< PREDIV2 input clock not divided */
02217  #define  RCC_CFGR2_PREDIV2_DIV2             ((uint32_t)0x00000010)        /*!< PREDIV2 input clock divided by 2 */
02218  #define  RCC_CFGR2_PREDIV2_DIV3             ((uint32_t)0x00000020)        /*!< PREDIV2 input clock divided by 3 */
02219  #define  RCC_CFGR2_PREDIV2_DIV4             ((uint32_t)0x00000030)        /*!< PREDIV2 input clock divided by 4 */
02220  #define  RCC_CFGR2_PREDIV2_DIV5             ((uint32_t)0x00000040)        /*!< PREDIV2 input clock divided by 5 */
02221  #define  RCC_CFGR2_PREDIV2_DIV6             ((uint32_t)0x00000050)        /*!< PREDIV2 input clock divided by 6 */
02222  #define  RCC_CFGR2_PREDIV2_DIV7             ((uint32_t)0x00000060)        /*!< PREDIV2 input clock divided by 7 */
02223  #define  RCC_CFGR2_PREDIV2_DIV8             ((uint32_t)0x00000070)        /*!< PREDIV2 input clock divided by 8 */
02224  #define  RCC_CFGR2_PREDIV2_DIV9             ((uint32_t)0x00000080)        /*!< PREDIV2 input clock divided by 9 */
02225  #define  RCC_CFGR2_PREDIV2_DIV10            ((uint32_t)0x00000090)        /*!< PREDIV2 input clock divided by 10 */
02226  #define  RCC_CFGR2_PREDIV2_DIV11            ((uint32_t)0x000000A0)        /*!< PREDIV2 input clock divided by 11 */
02227  #define  RCC_CFGR2_PREDIV2_DIV12            ((uint32_t)0x000000B0)        /*!< PREDIV2 input clock divided by 12 */
02228  #define  RCC_CFGR2_PREDIV2_DIV13            ((uint32_t)0x000000C0)        /*!< PREDIV2 input clock divided by 13 */
02229  #define  RCC_CFGR2_PREDIV2_DIV14            ((uint32_t)0x000000D0)        /*!< PREDIV2 input clock divided by 14 */
02230  #define  RCC_CFGR2_PREDIV2_DIV15            ((uint32_t)0x000000E0)        /*!< PREDIV2 input clock divided by 15 */
02231  #define  RCC_CFGR2_PREDIV2_DIV16            ((uint32_t)0x000000F0)        /*!< PREDIV2 input clock divided by 16 */
02232
02233 /*!< PLL2MUL configuration */
02234  #define  RCC_CFGR2_PLL2MUL                  ((uint32_t)0x00000F00)        /*!< PLL2MUL[3:0] bits */
02235  #define  RCC_CFGR2_PLL2MUL_0                ((uint32_t)0x00000100)        /*!< Bit 0 */
02236  #define  RCC_CFGR2_PLL2MUL_1                ((uint32_t)0x00000200)        /*!< Bit 1 */
02237  #define  RCC_CFGR2_PLL2MUL_2                ((uint32_t)0x00000400)        /*!< Bit 2 */
02238  #define  RCC_CFGR2_PLL2MUL_3                ((uint32_t)0x00000800)        /*!< Bit 3 */
02239
02240  #define  RCC_CFGR2_PLL2MUL8                 ((uint32_t)0x00000600)        /*!< PLL2 input clock * 8 */
02241  #define  RCC_CFGR2_PLL2MUL9                 ((uint32_t)0x00000700)        /*!< PLL2 input clock * 9 */
02242  #define  RCC_CFGR2_PLL2MUL10                ((uint32_t)0x00000800)        /*!< PLL2 input clock * 10 */
02243  #define  RCC_CFGR2_PLL2MUL11                ((uint32_t)0x00000900)        /*!< PLL2 input clock * 11 */
02244  #define  RCC_CFGR2_PLL2MUL12                ((uint32_t)0x00000A00)        /*!< PLL2 input clock * 12 */
02245  #define  RCC_CFGR2_PLL2MUL13                ((uint32_t)0x00000B00)        /*!< PLL2 input clock * 13 */
02246  #define  RCC_CFGR2_PLL2MUL14                ((uint32_t)0x00000C00)        /*!< PLL2 input clock * 14 */
02247  #define  RCC_CFGR2_PLL2MUL16                ((uint32_t)0x00000E00)        /*!< PLL2 input clock * 16 */
02248  #define  RCC_CFGR2_PLL2MUL20                ((uint32_t)0x00000F00)        /*!< PLL2 input clock * 20 */
02249
02250 /*!< PLL3MUL configuration */
02251  #define  RCC_CFGR2_PLL3MUL                  ((uint32_t)0x0000F000)        /*!< PLL3MUL[3:0] bits */
02252  #define  RCC_CFGR2_PLL3MUL_0                ((uint32_t)0x00001000)        /*!< Bit 0 */
02253  #define  RCC_CFGR2_PLL3MUL_1                ((uint32_t)0x00002000)        /*!< Bit 1 */
02254  #define  RCC_CFGR2_PLL3MUL_2                ((uint32_t)0x00004000)        /*!< Bit 2 */
02255  #define  RCC_CFGR2_PLL3MUL_3                ((uint32_t)0x00008000)        /*!< Bit 3 */
02256
02257  #define  RCC_CFGR2_PLL3MUL8                 ((uint32_t)0x00006000)        /*!< PLL3 input clock * 8 */
02258  #define  RCC_CFGR2_PLL3MUL9                 ((uint32_t)0x00007000)        /*!< PLL3 input clock * 9 */
02259  #define  RCC_CFGR2_PLL3MUL10                ((uint32_t)0x00008000)        /*!< PLL3 input clock * 10 */
02260  #define  RCC_CFGR2_PLL3MUL11                ((uint32_t)0x00009000)        /*!< PLL3 input clock * 11 */
02261  #define  RCC_CFGR2_PLL3MUL12                ((uint32_t)0x0000A000)        /*!< PLL3 input clock * 12 */
02262  #define  RCC_CFGR2_PLL3MUL13                ((uint32_t)0x0000B000)        /*!< PLL3 input clock * 13 */
02263  #define  RCC_CFGR2_PLL3MUL14                ((uint32_t)0x0000C000)        /*!< PLL3 input clock * 14 */
02264  #define  RCC_CFGR2_PLL3MUL16                ((uint32_t)0x0000E000)        /*!< PLL3 input clock * 16 */
02265  #define  RCC_CFGR2_PLL3MUL20                ((uint32_t)0x0000F000)        /*!< PLL3 input clock * 20 */
02266
02267  #define  RCC_CFGR2_PREDIV1SRC               ((uint32_t)0x00010000)        /*!< PREDIV1 entry clock source */
02268  #define  RCC_CFGR2_PREDIV1SRC_PLL2          ((uint32_t)0x00010000)        /*!< PLL2 selected as PREDIV1 entry clock source */
02269  #define  RCC_CFGR2_PREDIV1SRC_HSE           ((uint32_t)0x00000000)        /*!< HSE selected as PREDIV1 entry clock source */
02270  #define  RCC_CFGR2_I2S2SRC                  ((uint32_t)0x00020000)        /*!< I2S2 entry clock source */
02271  #define  RCC_CFGR2_I2S3SRC                  ((uint32_t)0x00040000)        /*!< I2S3 clock source */
02272 #endif /* STM32F10X_CL */
02273
02274 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
02275 /*******************  Bit definition for RCC_CFGR2 register  ******************/
02276 /*!< PREDIV1 configuration */
02277  #define  RCC_CFGR2_PREDIV1                  ((uint32_t)0x0000000F)        /*!< PREDIV1[3:0] bits */
02278  #define  RCC_CFGR2_PREDIV1_0                ((uint32_t)0x00000001)        /*!< Bit 0 */
02279  #define  RCC_CFGR2_PREDIV1_1                ((uint32_t)0x00000002)        /*!< Bit 1 */
02280  #define  RCC_CFGR2_PREDIV1_2                ((uint32_t)0x00000004)        /*!< Bit 2 */
02281  #define  RCC_CFGR2_PREDIV1_3                ((uint32_t)0x00000008)        /*!< Bit 3 */
02282
02283  #define  RCC_CFGR2_PREDIV1_DIV1             ((uint32_t)0x00000000)        /*!< PREDIV1 input clock not divided */
02284  #define  RCC_CFGR2_PREDIV1_DIV2             ((uint32_t)0x00000001)        /*!< PREDIV1 input clock divided by 2 */
02285  #define  RCC_CFGR2_PREDIV1_DIV3             ((uint32_t)0x00000002)        /*!< PREDIV1 input clock divided by 3 */
02286  #define  RCC_CFGR2_PREDIV1_DIV4             ((uint32_t)0x00000003)        /*!< PREDIV1 input clock divided by 4 */
02287  #define  RCC_CFGR2_PREDIV1_DIV5             ((uint32_t)0x00000004)        /*!< PREDIV1 input clock divided by 5 */
02288  #define  RCC_CFGR2_PREDIV1_DIV6             ((uint32_t)0x00000005)        /*!< PREDIV1 input clock divided by 6 */
02289  #define  RCC_CFGR2_PREDIV1_DIV7             ((uint32_t)0x00000006)        /*!< PREDIV1 input clock divided by 7 */
02290  #define  RCC_CFGR2_PREDIV1_DIV8             ((uint32_t)0x00000007)        /*!< PREDIV1 input clock divided by 8 */
02291  #define  RCC_CFGR2_PREDIV1_DIV9             ((uint32_t)0x00000008)        /*!< PREDIV1 input clock divided by 9 */
02292  #define  RCC_CFGR2_PREDIV1_DIV10            ((uint32_t)0x00000009)        /*!< PREDIV1 input clock divided by 10 */
02293  #define  RCC_CFGR2_PREDIV1_DIV11            ((uint32_t)0x0000000A)        /*!< PREDIV1 input clock divided by 11 */
02294  #define  RCC_CFGR2_PREDIV1_DIV12            ((uint32_t)0x0000000B)        /*!< PREDIV1 input clock divided by 12 */
02295  #define  RCC_CFGR2_PREDIV1_DIV13            ((uint32_t)0x0000000C)        /*!< PREDIV1 input clock divided by 13 */
02296  #define  RCC_CFGR2_PREDIV1_DIV14            ((uint32_t)0x0000000D)        /*!< PREDIV1 input clock divided by 14 */
02297  #define  RCC_CFGR2_PREDIV1_DIV15            ((uint32_t)0x0000000E)        /*!< PREDIV1 input clock divided by 15 */
02298  #define  RCC_CFGR2_PREDIV1_DIV16            ((uint32_t)0x0000000F)        /*!< PREDIV1 input clock divided by 16 */
02299 #endif
02300
02301 /******************************************************************************/
02302 /*                                                                            */
02303 /*                General Purpose and Alternate Function I/O                  */
02304 /*                                                                            */
02305 /******************************************************************************/
02306
02307 /*******************  Bit definition for GPIO_CRL register  *******************/
02308 #define  GPIO_CRL_MODE                       ((uint32_t)0x33333333)        /*!< Port x mode bits */
02309
02310 #define  GPIO_CRL_MODE0                      ((uint32_t)0x00000003)        /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */
02311 #define  GPIO_CRL_MODE0_0                    ((uint32_t)0x00000001)        /*!< Bit 0 */
02312 #define  GPIO_CRL_MODE0_1                    ((uint32_t)0x00000002)        /*!< Bit 1 */
02313
02314 #define  GPIO_CRL_MODE1                      ((uint32_t)0x00000030)        /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */
02315 #define  GPIO_CRL_MODE1_0                    ((uint32_t)0x00000010)        /*!< Bit 0 */
02316 #define  GPIO_CRL_MODE1_1                    ((uint32_t)0x00000020)        /*!< Bit 1 */
02317
02318 #define  GPIO_CRL_MODE2                      ((uint32_t)0x00000300)        /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */
02319 #define  GPIO_CRL_MODE2_0                    ((uint32_t)0x00000100)        /*!< Bit 0 */
02320 #define  GPIO_CRL_MODE2_1                    ((uint32_t)0x00000200)        /*!< Bit 1 */
02321
02322 #define  GPIO_CRL_MODE3                      ((uint32_t)0x00003000)        /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */
02323 #define  GPIO_CRL_MODE3_0                    ((uint32_t)0x00001000)        /*!< Bit 0 */
02324 #define  GPIO_CRL_MODE3_1                    ((uint32_t)0x00002000)        /*!< Bit 1 */
02325
02326 #define  GPIO_CRL_MODE4                      ((uint32_t)0x00030000)        /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */
02327 #define  GPIO_CRL_MODE4_0                    ((uint32_t)0x00010000)        /*!< Bit 0 */
02328 #define  GPIO_CRL_MODE4_1                    ((uint32_t)0x00020000)        /*!< Bit 1 */
02329
02330 #define  GPIO_CRL_MODE5                      ((uint32_t)0x00300000)        /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */
02331 #define  GPIO_CRL_MODE5_0                    ((uint32_t)0x00100000)        /*!< Bit 0 */
02332 #define  GPIO_CRL_MODE5_1                    ((uint32_t)0x00200000)        /*!< Bit 1 */
02333
02334 #define  GPIO_CRL_MODE6                      ((uint32_t)0x03000000)        /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */
02335 #define  GPIO_CRL_MODE6_0                    ((uint32_t)0x01000000)        /*!< Bit 0 */
02336 #define  GPIO_CRL_MODE6_1                    ((uint32_t)0x02000000)        /*!< Bit 1 */
02337
02338 #define  GPIO_CRL_MODE7                      ((uint32_t)0x30000000)        /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */
02339 #define  GPIO_CRL_MODE7_0                    ((uint32_t)0x10000000)        /*!< Bit 0 */
02340 #define  GPIO_CRL_MODE7_1                    ((uint32_t)0x20000000)        /*!< Bit 1 */
02341
02342 #define  GPIO_CRL_CNF                        ((uint32_t)0xCCCCCCCC)        /*!< Port x configuration bits */
02343
02344 #define  GPIO_CRL_CNF0                       ((uint32_t)0x0000000C)        /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */
02345 #define  GPIO_CRL_CNF0_0                     ((uint32_t)0x00000004)        /*!< Bit 0 */
02346 #define  GPIO_CRL_CNF0_1                     ((uint32_t)0x00000008)        /*!< Bit 1 */
02347
02348 #define  GPIO_CRL_CNF1                       ((uint32_t)0x000000C0)        /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */
02349 #define  GPIO_CRL_CNF1_0                     ((uint32_t)0x00000040)        /*!< Bit 0 */
02350 #define  GPIO_CRL_CNF1_1                     ((uint32_t)0x00000080)        /*!< Bit 1 */
02351
02352 #define  GPIO_CRL_CNF2                       ((uint32_t)0x00000C00)        /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */
02353 #define  GPIO_CRL_CNF2_0                     ((uint32_t)0x00000400)        /*!< Bit 0 */
02354 #define  GPIO_CRL_CNF2_1                     ((uint32_t)0x00000800)        /*!< Bit 1 */
02355
02356 #define  GPIO_CRL_CNF3                       ((uint32_t)0x0000C000)        /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */
02357 #define  GPIO_CRL_CNF3_0                     ((uint32_t)0x00004000)        /*!< Bit 0 */
02358 #define  GPIO_CRL_CNF3_1                     ((uint32_t)0x00008000)        /*!< Bit 1 */
02359
02360 #define  GPIO_CRL_CNF4                       ((uint32_t)0x000C0000)        /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */
02361 #define  GPIO_CRL_CNF4_0                     ((uint32_t)0x00040000)        /*!< Bit 0 */
02362 #define  GPIO_CRL_CNF4_1                     ((uint32_t)0x00080000)        /*!< Bit 1 */
02363
02364 #define  GPIO_CRL_CNF5                       ((uint32_t)0x00C00000)        /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */
02365 #define  GPIO_CRL_CNF5_0                     ((uint32_t)0x00400000)        /*!< Bit 0 */
02366 #define  GPIO_CRL_CNF5_1                     ((uint32_t)0x00800000)        /*!< Bit 1 */
02367
02368 #define  GPIO_CRL_CNF6                       ((uint32_t)0x0C000000)        /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */
02369 #define  GPIO_CRL_CNF6_0                     ((uint32_t)0x04000000)        /*!< Bit 0 */
02370 #define  GPIO_CRL_CNF6_1                     ((uint32_t)0x08000000)        /*!< Bit 1 */
02371
02372 #define  GPIO_CRL_CNF7                       ((uint32_t)0xC0000000)        /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */
02373 #define  GPIO_CRL_CNF7_0                     ((uint32_t)0x40000000)        /*!< Bit 0 */
02374 #define  GPIO_CRL_CNF7_1                     ((uint32_t)0x80000000)        /*!< Bit 1 */
02375
02376 /*******************  Bit definition for GPIO_CRH register  *******************/
02377 #define  GPIO_CRH_MODE                       ((uint32_t)0x33333333)        /*!< Port x mode bits */
02378
02379 #define  GPIO_CRH_MODE8                      ((uint32_t)0x00000003)        /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */
02380 #define  GPIO_CRH_MODE8_0                    ((uint32_t)0x00000001)        /*!< Bit 0 */
02381 #define  GPIO_CRH_MODE8_1                    ((uint32_t)0x00000002)        /*!< Bit 1 */
02382
02383 #define  GPIO_CRH_MODE9                      ((uint32_t)0x00000030)        /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */
02384 #define  GPIO_CRH_MODE9_0                    ((uint32_t)0x00000010)        /*!< Bit 0 */
02385 #define  GPIO_CRH_MODE9_1                    ((uint32_t)0x00000020)        /*!< Bit 1 */
02386
02387 #define  GPIO_CRH_MODE10                     ((uint32_t)0x00000300)        /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */
02388 #define  GPIO_CRH_MODE10_0                   ((uint32_t)0x00000100)        /*!< Bit 0 */
02389 #define  GPIO_CRH_MODE10_1                   ((uint32_t)0x00000200)        /*!< Bit 1 */
02390
02391 #define  GPIO_CRH_MODE11                     ((uint32_t)0x00003000)        /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */
02392 #define  GPIO_CRH_MODE11_0                   ((uint32_t)0x00001000)        /*!< Bit 0 */
02393 #define  GPIO_CRH_MODE11_1                   ((uint32_t)0x00002000)        /*!< Bit 1 */
02394
02395 #define  GPIO_CRH_MODE12                     ((uint32_t)0x00030000)        /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */
02396 #define  GPIO_CRH_MODE12_0                   ((uint32_t)0x00010000)        /*!< Bit 0 */
02397 #define  GPIO_CRH_MODE12_1                   ((uint32_t)0x00020000)        /*!< Bit 1 */
02398
02399 #define  GPIO_CRH_MODE13                     ((uint32_t)0x00300000)        /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */
02400 #define  GPIO_CRH_MODE13_0                   ((uint32_t)0x00100000)        /*!< Bit 0 */
02401 #define  GPIO_CRH_MODE13_1                   ((uint32_t)0x00200000)        /*!< Bit 1 */
02402
02403 #define  GPIO_CRH_MODE14                     ((uint32_t)0x03000000)        /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */
02404 #define  GPIO_CRH_MODE14_0                   ((uint32_t)0x01000000)        /*!< Bit 0 */
02405 #define  GPIO_CRH_MODE14_1                   ((uint32_t)0x02000000)        /*!< Bit 1 */
02406
02407 #define  GPIO_CRH_MODE15                     ((uint32_t)0x30000000)        /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */
02408 #define  GPIO_CRH_MODE15_0                   ((uint32_t)0x10000000)        /*!< Bit 0 */
02409 #define  GPIO_CRH_MODE15_1                   ((uint32_t)0x20000000)        /*!< Bit 1 */
02410
02411 #define  GPIO_CRH_CNF                        ((uint32_t)0xCCCCCCCC)        /*!< Port x configuration bits */
02412
02413 #define  GPIO_CRH_CNF8                       ((uint32_t)0x0000000C)        /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */
02414 #define  GPIO_CRH_CNF8_0                     ((uint32_t)0x00000004)        /*!< Bit 0 */
02415 #define  GPIO_CRH_CNF8_1                     ((uint32_t)0x00000008)        /*!< Bit 1 */
02416
02417 #define  GPIO_CRH_CNF9                       ((uint32_t)0x000000C0)        /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */
02418 #define  GPIO_CRH_CNF9_0                     ((uint32_t)0x00000040)        /*!< Bit 0 */
02419 #define  GPIO_CRH_CNF9_1                     ((uint32_t)0x00000080)        /*!< Bit 1 */
02420
02421 #define  GPIO_CRH_CNF10                      ((uint32_t)0x00000C00)        /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */
02422 #define  GPIO_CRH_CNF10_0                    ((uint32_t)0x00000400)        /*!< Bit 0 */
02423 #define  GPIO_CRH_CNF10_1                    ((uint32_t)0x00000800)        /*!< Bit 1 */
02424
02425 #define  GPIO_CRH_CNF11                      ((uint32_t)0x0000C000)        /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */
02426 #define  GPIO_CRH_CNF11_0                    ((uint32_t)0x00004000)        /*!< Bit 0 */
02427 #define  GPIO_CRH_CNF11_1                    ((uint32_t)0x00008000)        /*!< Bit 1 */
02428
02429 #define  GPIO_CRH_CNF12                      ((uint32_t)0x000C0000)        /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */
02430 #define  GPIO_CRH_CNF12_0                    ((uint32_t)0x00040000)        /*!< Bit 0 */
02431 #define  GPIO_CRH_CNF12_1                    ((uint32_t)0x00080000)        /*!< Bit 1 */
02432
02433 #define  GPIO_CRH_CNF13                      ((uint32_t)0x00C00000)        /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */
02434 #define  GPIO_CRH_CNF13_0                    ((uint32_t)0x00400000)        /*!< Bit 0 */
02435 #define  GPIO_CRH_CNF13_1                    ((uint32_t)0x00800000)        /*!< Bit 1 */
02436
02437 #define  GPIO_CRH_CNF14                      ((uint32_t)0x0C000000)        /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */
02438 #define  GPIO_CRH_CNF14_0                    ((uint32_t)0x04000000)        /*!< Bit 0 */
02439 #define  GPIO_CRH_CNF14_1                    ((uint32_t)0x08000000)        /*!< Bit 1 */
02440
02441 #define  GPIO_CRH_CNF15                      ((uint32_t)0xC0000000)        /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */
02442 #define  GPIO_CRH_CNF15_0                    ((uint32_t)0x40000000)        /*!< Bit 0 */
02443 #define  GPIO_CRH_CNF15_1                    ((uint32_t)0x80000000)        /*!< Bit 1 */
02444
02445 /*!<******************  Bit definition for GPIO_IDR register  *******************/
02446 #define GPIO_IDR_IDR0                        ((uint16_t)0x0001)            /*!< Port input data, bit 0 */
02447 #define GPIO_IDR_IDR1                        ((uint16_t)0x0002)            /*!< Port input data, bit 1 */
02448 #define GPIO_IDR_IDR2                        ((uint16_t)0x0004)            /*!< Port input data, bit 2 */
02449 #define GPIO_IDR_IDR3                        ((uint16_t)0x0008)            /*!< Port input data, bit 3 */
02450 #define GPIO_IDR_IDR4                        ((uint16_t)0x0010)            /*!< Port input data, bit 4 */
02451 #define GPIO_IDR_IDR5                        ((uint16_t)0x0020)            /*!< Port input data, bit 5 */
02452 #define GPIO_IDR_IDR6                        ((uint16_t)0x0040)            /*!< Port input data, bit 6 */
02453 #define GPIO_IDR_IDR7                        ((uint16_t)0x0080)            /*!< Port input data, bit 7 */
02454 #define GPIO_IDR_IDR8                        ((uint16_t)0x0100)            /*!< Port input data, bit 8 */
02455 #define GPIO_IDR_IDR9                        ((uint16_t)0x0200)            /*!< Port input data, bit 9 */
02456 #define GPIO_IDR_IDR10                       ((uint16_t)0x0400)            /*!< Port input data, bit 10 */
02457 #define GPIO_IDR_IDR11                       ((uint16_t)0x0800)            /*!< Port input data, bit 11 */
02458 #define GPIO_IDR_IDR12                       ((uint16_t)0x1000)            /*!< Port input data, bit 12 */
02459 #define GPIO_IDR_IDR13                       ((uint16_t)0x2000)            /*!< Port input data, bit 13 */
02460 #define GPIO_IDR_IDR14                       ((uint16_t)0x4000)            /*!< Port input data, bit 14 */
02461 #define GPIO_IDR_IDR15                       ((uint16_t)0x8000)            /*!< Port input data, bit 15 */
02462
02463 /*******************  Bit definition for GPIO_ODR register  *******************/
02464 #define GPIO_ODR_ODR0                        ((uint16_t)0x0001)            /*!< Port output data, bit 0 */
02465 #define GPIO_ODR_ODR1                        ((uint16_t)0x0002)            /*!< Port output data, bit 1 */
02466 #define GPIO_ODR_ODR2                        ((uint16_t)0x0004)            /*!< Port output data, bit 2 */
02467 #define GPIO_ODR_ODR3                        ((uint16_t)0x0008)            /*!< Port output data, bit 3 */
02468 #define GPIO_ODR_ODR4                        ((uint16_t)0x0010)            /*!< Port output data, bit 4 */
02469 #define GPIO_ODR_ODR5                        ((uint16_t)0x0020)            /*!< Port output data, bit 5 */
02470 #define GPIO_ODR_ODR6                        ((uint16_t)0x0040)            /*!< Port output data, bit 6 */
02471 #define GPIO_ODR_ODR7                        ((uint16_t)0x0080)            /*!< Port output data, bit 7 */
02472 #define GPIO_ODR_ODR8                        ((uint16_t)0x0100)            /*!< Port output data, bit 8 */
02473 #define GPIO_ODR_ODR9                        ((uint16_t)0x0200)            /*!< Port output data, bit 9 */
02474 #define GPIO_ODR_ODR10                       ((uint16_t)0x0400)            /*!< Port output data, bit 10 */
02475 #define GPIO_ODR_ODR11                       ((uint16_t)0x0800)            /*!< Port output data, bit 11 */
02476 #define GPIO_ODR_ODR12                       ((uint16_t)0x1000)            /*!< Port output data, bit 12 */
02477 #define GPIO_ODR_ODR13                       ((uint16_t)0x2000)            /*!< Port output data, bit 13 */
02478 #define GPIO_ODR_ODR14                       ((uint16_t)0x4000)            /*!< Port output data, bit 14 */
02479 #define GPIO_ODR_ODR15                       ((uint16_t)0x8000)            /*!< Port output data, bit 15 */
02480
02481 /******************  Bit definition for GPIO_BSRR register  *******************/
02482 #define GPIO_BSRR_BS0                        ((uint32_t)0x00000001)        /*!< Port x Set bit 0 */
02483 #define GPIO_BSRR_BS1                        ((uint32_t)0x00000002)        /*!< Port x Set bit 1 */
02484 #define GPIO_BSRR_BS2                        ((uint32_t)0x00000004)        /*!< Port x Set bit 2 */
02485 #define GPIO_BSRR_BS3                        ((uint32_t)0x00000008)        /*!< Port x Set bit 3 */
02486 #define GPIO_BSRR_BS4                        ((uint32_t)0x00000010)        /*!< Port x Set bit 4 */
02487 #define GPIO_BSRR_BS5                        ((uint32_t)0x00000020)        /*!< Port x Set bit 5 */
02488 #define GPIO_BSRR_BS6                        ((uint32_t)0x00000040)        /*!< Port x Set bit 6 */
02489 #define GPIO_BSRR_BS7                        ((uint32_t)0x00000080)        /*!< Port x Set bit 7 */
02490 #define GPIO_BSRR_BS8                        ((uint32_t)0x00000100)        /*!< Port x Set bit 8 */
02491 #define GPIO_BSRR_BS9                        ((uint32_t)0x00000200)        /*!< Port x Set bit 9 */
02492 #define GPIO_BSRR_BS10                       ((uint32_t)0x00000400)        /*!< Port x Set bit 10 */
02493 #define GPIO_BSRR_BS11                       ((uint32_t)0x00000800)        /*!< Port x Set bit 11 */
02494 #define GPIO_BSRR_BS12                       ((uint32_t)0x00001000)        /*!< Port x Set bit 12 */
02495 #define GPIO_BSRR_BS13                       ((uint32_t)0x00002000)        /*!< Port x Set bit 13 */
02496 #define GPIO_BSRR_BS14                       ((uint32_t)0x00004000)        /*!< Port x Set bit 14 */
02497 #define GPIO_BSRR_BS15                       ((uint32_t)0x00008000)        /*!< Port x Set bit 15 */
02498
02499 #define GPIO_BSRR_BR0                        ((uint32_t)0x00010000)        /*!< Port x Reset bit 0 */
02500 #define GPIO_BSRR_BR1                        ((uint32_t)0x00020000)        /*!< Port x Reset bit 1 */
02501 #define GPIO_BSRR_BR2                        ((uint32_t)0x00040000)        /*!< Port x Reset bit 2 */
02502 #define GPIO_BSRR_BR3                        ((uint32_t)0x00080000)        /*!< Port x Reset bit 3 */
02503 #define GPIO_BSRR_BR4                        ((uint32_t)0x00100000)        /*!< Port x Reset bit 4 */
02504 #define GPIO_BSRR_BR5                        ((uint32_t)0x00200000)        /*!< Port x Reset bit 5 */
02505 #define GPIO_BSRR_BR6                        ((uint32_t)0x00400000)        /*!< Port x Reset bit 6 */
02506 #define GPIO_BSRR_BR7                        ((uint32_t)0x00800000)        /*!< Port x Reset bit 7 */
02507 #define GPIO_BSRR_BR8                        ((uint32_t)0x01000000)        /*!< Port x Reset bit 8 */
02508 #define GPIO_BSRR_BR9                        ((uint32_t)0x02000000)        /*!< Port x Reset bit 9 */
02509 #define GPIO_BSRR_BR10                       ((uint32_t)0x04000000)        /*!< Port x Reset bit 10 */
02510 #define GPIO_BSRR_BR11                       ((uint32_t)0x08000000)        /*!< Port x Reset bit 11 */
02511 #define GPIO_BSRR_BR12                       ((uint32_t)0x10000000)        /*!< Port x Reset bit 12 */
02512 #define GPIO_BSRR_BR13                       ((uint32_t)0x20000000)        /*!< Port x Reset bit 13 */
02513 #define GPIO_BSRR_BR14                       ((uint32_t)0x40000000)        /*!< Port x Reset bit 14 */
02514 #define GPIO_BSRR_BR15                       ((uint32_t)0x80000000)        /*!< Port x Reset bit 15 */
02515
02516 /*******************  Bit definition for GPIO_BRR register  *******************/
02517 #define GPIO_BRR_BR0                         ((uint16_t)0x0001)            /*!< Port x Reset bit 0 */
02518 #define GPIO_BRR_BR1                         ((uint16_t)0x0002)            /*!< Port x Reset bit 1 */
02519 #define GPIO_BRR_BR2                         ((uint16_t)0x0004)            /*!< Port x Reset bit 2 */
02520 #define GPIO_BRR_BR3                         ((uint16_t)0x0008)            /*!< Port x Reset bit 3 */
02521 #define GPIO_BRR_BR4                         ((uint16_t)0x0010)            /*!< Port x Reset bit 4 */
02522 #define GPIO_BRR_BR5                         ((uint16_t)0x0020)            /*!< Port x Reset bit 5 */
02523 #define GPIO_BRR_BR6                         ((uint16_t)0x0040)            /*!< Port x Reset bit 6 */
02524 #define GPIO_BRR_BR7                         ((uint16_t)0x0080)            /*!< Port x Reset bit 7 */
02525 #define GPIO_BRR_BR8                         ((uint16_t)0x0100)            /*!< Port x Reset bit 8 */
02526 #define GPIO_BRR_BR9                         ((uint16_t)0x0200)            /*!< Port x Reset bit 9 */
02527 #define GPIO_BRR_BR10                        ((uint16_t)0x0400)            /*!< Port x Reset bit 10 */
02528 #define GPIO_BRR_BR11                        ((uint16_t)0x0800)            /*!< Port x Reset bit 11 */
02529 #define GPIO_BRR_BR12                        ((uint16_t)0x1000)            /*!< Port x Reset bit 12 */
02530 #define GPIO_BRR_BR13                        ((uint16_t)0x2000)            /*!< Port x Reset bit 13 */
02531 #define GPIO_BRR_BR14                        ((uint16_t)0x4000)            /*!< Port x Reset bit 14 */
02532 #define GPIO_BRR_BR15                        ((uint16_t)0x8000)            /*!< Port x Reset bit 15 */
02533
02534 /******************  Bit definition for GPIO_LCKR register  *******************/
02535 #define GPIO_LCKR_LCK0                       ((uint32_t)0x00000001)        /*!< Port x Lock bit 0 */
02536 #define GPIO_LCKR_LCK1                       ((uint32_t)0x00000002)        /*!< Port x Lock bit 1 */
02537 #define GPIO_LCKR_LCK2                       ((uint32_t)0x00000004)        /*!< Port x Lock bit 2 */
02538 #define GPIO_LCKR_LCK3                       ((uint32_t)0x00000008)        /*!< Port x Lock bit 3 */
02539 #define GPIO_LCKR_LCK4                       ((uint32_t)0x00000010)        /*!< Port x Lock bit 4 */
02540 #define GPIO_LCKR_LCK5                       ((uint32_t)0x00000020)        /*!< Port x Lock bit 5 */
02541 #define GPIO_LCKR_LCK6                       ((uint32_t)0x00000040)        /*!< Port x Lock bit 6 */
02542 #define GPIO_LCKR_LCK7                       ((uint32_t)0x00000080)        /*!< Port x Lock bit 7 */
02543 #define GPIO_LCKR_LCK8                       ((uint32_t)0x00000100)        /*!< Port x Lock bit 8 */
02544 #define GPIO_LCKR_LCK9                       ((uint32_t)0x00000200)        /*!< Port x Lock bit 9 */
02545 #define GPIO_LCKR_LCK10                      ((uint32_t)0x00000400)        /*!< Port x Lock bit 10 */
02546 #define GPIO_LCKR_LCK11                      ((uint32_t)0x00000800)        /*!< Port x Lock bit 11 */
02547 #define GPIO_LCKR_LCK12                      ((uint32_t)0x00001000)        /*!< Port x Lock bit 12 */
02548 #define GPIO_LCKR_LCK13                      ((uint32_t)0x00002000)        /*!< Port x Lock bit 13 */
02549 #define GPIO_LCKR_LCK14                      ((uint32_t)0x00004000)        /*!< Port x Lock bit 14 */
02550 #define GPIO_LCKR_LCK15                      ((uint32_t)0x00008000)        /*!< Port x Lock bit 15 */
02551 #define GPIO_LCKR_LCKK                       ((uint32_t)0x00010000)        /*!< Lock key */
02552
02553 /*----------------------------------------------------------------------------*/
02554
02555 /******************  Bit definition for AFIO_EVCR register  *******************/
02556 #define AFIO_EVCR_PIN                        ((uint8_t)0x0F)               /*!< PIN[3:0] bits (Pin selection) */
02557 #define AFIO_EVCR_PIN_0                      ((uint8_t)0x01)               /*!< Bit 0 */
02558 #define AFIO_EVCR_PIN_1                      ((uint8_t)0x02)               /*!< Bit 1 */
02559 #define AFIO_EVCR_PIN_2                      ((uint8_t)0x04)               /*!< Bit 2 */
02560 #define AFIO_EVCR_PIN_3                      ((uint8_t)0x08)               /*!< Bit 3 */
02561
02562 /*!< PIN configuration */
02563 #define AFIO_EVCR_PIN_PX0                    ((uint8_t)0x00)               /*!< Pin 0 selected */
02564 #define AFIO_EVCR_PIN_PX1                    ((uint8_t)0x01)               /*!< Pin 1 selected */
02565 #define AFIO_EVCR_PIN_PX2                    ((uint8_t)0x02)               /*!< Pin 2 selected */
02566 #define AFIO_EVCR_PIN_PX3                    ((uint8_t)0x03)               /*!< Pin 3 selected */
02567 #define AFIO_EVCR_PIN_PX4                    ((uint8_t)0x04)               /*!< Pin 4 selected */
02568 #define AFIO_EVCR_PIN_PX5                    ((uint8_t)0x05)               /*!< Pin 5 selected */
02569 #define AFIO_EVCR_PIN_PX6                    ((uint8_t)0x06)               /*!< Pin 6 selected */
02570 #define AFIO_EVCR_PIN_PX7                    ((uint8_t)0x07)               /*!< Pin 7 selected */
02571 #define AFIO_EVCR_PIN_PX8                    ((uint8_t)0x08)               /*!< Pin 8 selected */
02572 #define AFIO_EVCR_PIN_PX9                    ((uint8_t)0x09)               /*!< Pin 9 selected */
02573 #define AFIO_EVCR_PIN_PX10                   ((uint8_t)0x0A)               /*!< Pin 10 selected */
02574 #define AFIO_EVCR_PIN_PX11                   ((uint8_t)0x0B)               /*!< Pin 11 selected */
02575 #define AFIO_EVCR_PIN_PX12                   ((uint8_t)0x0C)               /*!< Pin 12 selected */
02576 #define AFIO_EVCR_PIN_PX13                   ((uint8_t)0x0D)               /*!< Pin 13 selected */
02577 #define AFIO_EVCR_PIN_PX14                   ((uint8_t)0x0E)               /*!< Pin 14 selected */
02578 #define AFIO_EVCR_PIN_PX15                   ((uint8_t)0x0F)               /*!< Pin 15 selected */
02579
02580 #define AFIO_EVCR_PORT                       ((uint8_t)0x70)               /*!< PORT[2:0] bits (Port selection) */
02581 #define AFIO_EVCR_PORT_0                     ((uint8_t)0x10)               /*!< Bit 0 */
02582 #define AFIO_EVCR_PORT_1                     ((uint8_t)0x20)               /*!< Bit 1 */
02583 #define AFIO_EVCR_PORT_2                     ((uint8_t)0x40)               /*!< Bit 2 */
02584
02585 /*!< PORT configuration */
02586 #define AFIO_EVCR_PORT_PA                    ((uint8_t)0x00)               /*!< Port A selected */
02587 #define AFIO_EVCR_PORT_PB                    ((uint8_t)0x10)               /*!< Port B selected */
02588 #define AFIO_EVCR_PORT_PC                    ((uint8_t)0x20)               /*!< Port C selected */
02589 #define AFIO_EVCR_PORT_PD                    ((uint8_t)0x30)               /*!< Port D selected */
02590 #define AFIO_EVCR_PORT_PE                    ((uint8_t)0x40)               /*!< Port E selected */
02591
02592 #define AFIO_EVCR_EVOE                       ((uint8_t)0x80)               /*!< Event Output Enable */
02593
02594 /******************  Bit definition for AFIO_MAPR register  *******************/
02595 #define AFIO_MAPR_SPI1_REMAP                 ((uint32_t)0x00000001)        /*!< SPI1 remapping */
02596 #define AFIO_MAPR_I2C1_REMAP                 ((uint32_t)0x00000002)        /*!< I2C1 remapping */
02597 #define AFIO_MAPR_USART1_REMAP               ((uint32_t)0x00000004)        /*!< USART1 remapping */
02598 #define AFIO_MAPR_USART2_REMAP               ((uint32_t)0x00000008)        /*!< USART2 remapping */
02599
02600 #define AFIO_MAPR_USART3_REMAP               ((uint32_t)0x00000030)        /*!< USART3_REMAP[1:0] bits (USART3 remapping) */
02601 #define AFIO_MAPR_USART3_REMAP_0             ((uint32_t)0x00000010)        /*!< Bit 0 */
02602 #define AFIO_MAPR_USART3_REMAP_1             ((uint32_t)0x00000020)        /*!< Bit 1 */
02603
02604 /* USART3_REMAP configuration */
02605 #define AFIO_MAPR_USART3_REMAP_NOREMAP       ((uint32_t)0x00000000)        /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
02606 #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP  ((uint32_t)0x00000010)        /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */
02607 #define AFIO_MAPR_USART3_REMAP_FULLREMAP     ((uint32_t)0x00000030)        /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */
02608
02609 #define AFIO_MAPR_TIM1_REMAP                 ((uint32_t)0x000000C0)        /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */
02610 #define AFIO_MAPR_TIM1_REMAP_0               ((uint32_t)0x00000040)        /*!< Bit 0 */
02611 #define AFIO_MAPR_TIM1_REMAP_1               ((uint32_t)0x00000080)        /*!< Bit 1 */
02612
02613 /*!< TIM1_REMAP configuration */
02614 #define AFIO_MAPR_TIM1_REMAP_NOREMAP         ((uint32_t)0x00000000)        /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
02615 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP    ((uint32_t)0x00000040)        /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */
02616 #define AFIO_MAPR_TIM1_REMAP_FULLREMAP       ((uint32_t)0x000000C0)        /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */
02617
02618 #define AFIO_MAPR_TIM2_REMAP                 ((uint32_t)0x00000300)        /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */
02619 #define AFIO_MAPR_TIM2_REMAP_0               ((uint32_t)0x00000100)        /*!< Bit 0 */
02620 #define AFIO_MAPR_TIM2_REMAP_1               ((uint32_t)0x00000200)        /*!< Bit 1 */
02621
02622 /*!< TIM2_REMAP configuration */
02623 #define AFIO_MAPR_TIM2_REMAP_NOREMAP         ((uint32_t)0x00000000)        /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
02624 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1   ((uint32_t)0x00000100)        /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */
02625 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2   ((uint32_t)0x00000200)        /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */
02626 #define AFIO_MAPR_TIM2_REMAP_FULLREMAP       ((uint32_t)0x00000300)        /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */
02627
02628 #define AFIO_MAPR_TIM3_REMAP                 ((uint32_t)0x00000C00)        /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */
02629 #define AFIO_MAPR_TIM3_REMAP_0               ((uint32_t)0x00000400)        /*!< Bit 0 */
02630 #define AFIO_MAPR_TIM3_REMAP_1               ((uint32_t)0x00000800)        /*!< Bit 1 */
02631
02632 /*!< TIM3_REMAP configuration */
02633 #define AFIO_MAPR_TIM3_REMAP_NOREMAP         ((uint32_t)0x00000000)        /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
02634 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP    ((uint32_t)0x00000800)        /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */
02635 #define AFIO_MAPR_TIM3_REMAP_FULLREMAP       ((uint32_t)0x00000C00)        /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */
02636
02637 #define AFIO_MAPR_TIM4_REMAP                 ((uint32_t)0x00001000)        /*!< TIM4_REMAP bit (TIM4 remapping) */
02638
02639 #define AFIO_MAPR_CAN_REMAP                  ((uint32_t)0x00006000)        /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */
02640 #define AFIO_MAPR_CAN_REMAP_0                ((uint32_t)0x00002000)        /*!< Bit 0 */
02641 #define AFIO_MAPR_CAN_REMAP_1                ((uint32_t)0x00004000)        /*!< Bit 1 */
02642
02643 /*!< CAN_REMAP configuration */
02644 #define AFIO_MAPR_CAN_REMAP_REMAP1           ((uint32_t)0x00000000)        /*!< CANRX mapped to PA11, CANTX mapped to PA12 */
02645 #define AFIO_MAPR_CAN_REMAP_REMAP2           ((uint32_t)0x00004000)        /*!< CANRX mapped to PB8, CANTX mapped to PB9 */
02646 #define AFIO_MAPR_CAN_REMAP_REMAP3           ((uint32_t)0x00006000)        /*!< CANRX mapped to PD0, CANTX mapped to PD1 */
02647
02648 #define AFIO_MAPR_PD01_REMAP                 ((uint32_t)0x00008000)        /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
02649 #define AFIO_MAPR_TIM5CH4_IREMAP             ((uint32_t)0x00010000)        /*!< TIM5 Channel4 Internal Remap */
02650 #define AFIO_MAPR_ADC1_ETRGINJ_REMAP         ((uint32_t)0x00020000)        /*!< ADC 1 External Trigger Injected Conversion remapping */
02651 #define AFIO_MAPR_ADC1_ETRGREG_REMAP         ((uint32_t)0x00040000)        /*!< ADC 1 External Trigger Regular Conversion remapping */
02652 #define AFIO_MAPR_ADC2_ETRGINJ_REMAP         ((uint32_t)0x00080000)        /*!< ADC 2 External Trigger Injected Conversion remapping */
02653 #define AFIO_MAPR_ADC2_ETRGREG_REMAP         ((uint32_t)0x00100000)        /*!< ADC 2 External Trigger Regular Conversion remapping */
02654
02655 /*!< SWJ_CFG configuration */
02656 #define AFIO_MAPR_SWJ_CFG                    ((uint32_t)0x07000000)        /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */
02657 #define AFIO_MAPR_SWJ_CFG_0                  ((uint32_t)0x01000000)        /*!< Bit 0 */
02658 #define AFIO_MAPR_SWJ_CFG_1                  ((uint32_t)0x02000000)        /*!< Bit 1 */
02659 #define AFIO_MAPR_SWJ_CFG_2                  ((uint32_t)0x04000000)        /*!< Bit 2 */
02660
02661 #define AFIO_MAPR_SWJ_CFG_RESET              ((uint32_t)0x00000000)        /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */
02662 #define AFIO_MAPR_SWJ_CFG_NOJNTRST           ((uint32_t)0x01000000)        /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */
02663 #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE        ((uint32_t)0x02000000)        /*!< JTAG-DP Disabled and SW-DP Enabled */
02664 #define AFIO_MAPR_SWJ_CFG_DISABLE            ((uint32_t)0x04000000)        /*!< JTAG-DP Disabled and SW-DP Disabled */
02665
02666 #ifdef STM32F10X_CL
02667 /*!< ETH_REMAP configuration */
02668  #define AFIO_MAPR_ETH_REMAP                  ((uint32_t)0x00200000)        /*!< SPI3_REMAP bit (Ethernet MAC I/O remapping) */
02669
02670 /*!< CAN2_REMAP configuration */
02671  #define AFIO_MAPR_CAN2_REMAP                 ((uint32_t)0x00400000)        /*!< CAN2_REMAP bit (CAN2 I/O remapping) */
02672
02673 /*!< MII_RMII_SEL configuration */
02674  #define AFIO_MAPR_MII_RMII_SEL               ((uint32_t)0x00800000)        /*!< MII_RMII_SEL bit (Ethernet MII or RMII selection) */
02675
02676 /*!< SPI3_REMAP configuration */
02677  #define AFIO_MAPR_SPI3_REMAP                 ((uint32_t)0x10000000)        /*!< SPI3_REMAP bit (SPI3 remapping) */
02678
02679 /*!< TIM2ITR1_IREMAP configuration */
02680  #define AFIO_MAPR_TIM2ITR1_IREMAP            ((uint32_t)0x20000000)        /*!< TIM2ITR1_IREMAP bit (TIM2 internal trigger 1 remapping) */
02681
02682 /*!< PTP_PPS_REMAP configuration */
02683  #define AFIO_MAPR_PTP_PPS_REMAP              ((uint32_t)0x40000000)        /*!< PTP_PPS_REMAP bit (Ethernet PTP PPS remapping) */
02684 #endif
02685
02686 /*****************  Bit definition for AFIO_EXTICR1 register  *****************/
02687 #define AFIO_EXTICR1_EXTI0                   ((uint16_t)0x000F)            /*!< EXTI 0 configuration */
02688 #define AFIO_EXTICR1_EXTI1                   ((uint16_t)0x00F0)            /*!< EXTI 1 configuration */
02689 #define AFIO_EXTICR1_EXTI2                   ((uint16_t)0x0F00)            /*!< EXTI 2 configuration */
02690 #define AFIO_EXTICR1_EXTI3                   ((uint16_t)0xF000)            /*!< EXTI 3 configuration */
02691
02692 /*!< EXTI0 configuration */
02693 #define AFIO_EXTICR1_EXTI0_PA                ((uint16_t)0x0000)            /*!< PA[0] pin */
02694 #define AFIO_EXTICR1_EXTI0_PB                ((uint16_t)0x0001)            /*!< PB[0] pin */
02695 #define AFIO_EXTICR1_EXTI0_PC                ((uint16_t)0x0002)            /*!< PC[0] pin */
02696 #define AFIO_EXTICR1_EXTI0_PD                ((uint16_t)0x0003)            /*!< PD[0] pin */
02697 #define AFIO_EXTICR1_EXTI0_PE                ((uint16_t)0x0004)            /*!< PE[0] pin */
02698 #define AFIO_EXTICR1_EXTI0_PF                ((uint16_t)0x0005)            /*!< PF[0] pin */
02699 #define AFIO_EXTICR1_EXTI0_PG                ((uint16_t)0x0006)            /*!< PG[0] pin */
02700
02701 /*!< EXTI1 configuration */
02702 #define AFIO_EXTICR1_EXTI1_PA                ((uint16_t)0x0000)            /*!< PA[1] pin */
02703 #define AFIO_EXTICR1_EXTI1_PB                ((uint16_t)0x0010)            /*!< PB[1] pin */
02704 #define AFIO_EXTICR1_EXTI1_PC                ((uint16_t)0x0020)            /*!< PC[1] pin */
02705 #define AFIO_EXTICR1_EXTI1_PD                ((uint16_t)0x0030)            /*!< PD[1] pin */
02706 #define AFIO_EXTICR1_EXTI1_PE                ((uint16_t)0x0040)            /*!< PE[1] pin */
02707 #define AFIO_EXTICR1_EXTI1_PF                ((uint16_t)0x0050)            /*!< PF[1] pin */
02708 #define AFIO_EXTICR1_EXTI1_PG                ((uint16_t)0x0060)            /*!< PG[1] pin */
02709
02710 /*!< EXTI2 configuration */
02711 #define AFIO_EXTICR1_EXTI2_PA                ((uint16_t)0x0000)            /*!< PA[2] pin */
02712 #define AFIO_EXTICR1_EXTI2_PB                ((uint16_t)0x0100)            /*!< PB[2] pin */
02713 #define AFIO_EXTICR1_EXTI2_PC                ((uint16_t)0x0200)            /*!< PC[2] pin */
02714 #define AFIO_EXTICR1_EXTI2_PD                ((uint16_t)0x0300)            /*!< PD[2] pin */
02715 #define AFIO_EXTICR1_EXTI2_PE                ((uint16_t)0x0400)            /*!< PE[2] pin */
02716 #define AFIO_EXTICR1_EXTI2_PF                ((uint16_t)0x0500)            /*!< PF[2] pin */
02717 #define AFIO_EXTICR1_EXTI2_PG                ((uint16_t)0x0600)            /*!< PG[2] pin */
02718
02719 /*!< EXTI3 configuration */
02720 #define AFIO_EXTICR1_EXTI3_PA                ((uint16_t)0x0000)            /*!< PA[3] pin */
02721 #define AFIO_EXTICR1_EXTI3_PB                ((uint16_t)0x1000)            /*!< PB[3] pin */
02722 #define AFIO_EXTICR1_EXTI3_PC                ((uint16_t)0x2000)            /*!< PC[3] pin */
02723 #define AFIO_EXTICR1_EXTI3_PD                ((uint16_t)0x3000)            /*!< PD[3] pin */
02724 #define AFIO_EXTICR1_EXTI3_PE                ((uint16_t)0x4000)            /*!< PE[3] pin */
02725 #define AFIO_EXTICR1_EXTI3_PF                ((uint16_t)0x5000)            /*!< PF[3] pin */
02726 #define AFIO_EXTICR1_EXTI3_PG                ((uint16_t)0x6000)            /*!< PG[3] pin */
02727
02728 /*****************  Bit definition for AFIO_EXTICR2 register  *****************/
02729 #define AFIO_EXTICR2_EXTI4                   ((uint16_t)0x000F)            /*!< EXTI 4 configuration */
02730 #define AFIO_EXTICR2_EXTI5                   ((uint16_t)0x00F0)            /*!< EXTI 5 configuration */
02731 #define AFIO_EXTICR2_EXTI6                   ((uint16_t)0x0F00)            /*!< EXTI 6 configuration */
02732 #define AFIO_EXTICR2_EXTI7                   ((uint16_t)0xF000)            /*!< EXTI 7 configuration */
02733
02734 /*!< EXTI4 configuration */
02735 #define AFIO_EXTICR2_EXTI4_PA                ((uint16_t)0x0000)            /*!< PA[4] pin */
02736 #define AFIO_EXTICR2_EXTI4_PB                ((uint16_t)0x0001)            /*!< PB[4] pin */
02737 #define AFIO_EXTICR2_EXTI4_PC                ((uint16_t)0x0002)            /*!< PC[4] pin */
02738 #define AFIO_EXTICR2_EXTI4_PD                ((uint16_t)0x0003)            /*!< PD[4] pin */
02739 #define AFIO_EXTICR2_EXTI4_PE                ((uint16_t)0x0004)            /*!< PE[4] pin */
02740 #define AFIO_EXTICR2_EXTI4_PF                ((uint16_t)0x0005)            /*!< PF[4] pin */
02741 #define AFIO_EXTICR2_EXTI4_PG                ((uint16_t)0x0006)            /*!< PG[4] pin */
02742
02743 /* EXTI5 configuration */
02744 #define AFIO_EXTICR2_EXTI5_PA                ((uint16_t)0x0000)            /*!< PA[5] pin */
02745 #define AFIO_EXTICR2_EXTI5_PB                ((uint16_t)0x0010)            /*!< PB[5] pin */
02746 #define AFIO_EXTICR2_EXTI5_PC                ((uint16_t)0x0020)            /*!< PC[5] pin */
02747 #define AFIO_EXTICR2_EXTI5_PD                ((uint16_t)0x0030)            /*!< PD[5] pin */
02748 #define AFIO_EXTICR2_EXTI5_PE                ((uint16_t)0x0040)            /*!< PE[5] pin */
02749 #define AFIO_EXTICR2_EXTI5_PF                ((uint16_t)0x0050)            /*!< PF[5] pin */
02750 #define AFIO_EXTICR2_EXTI5_PG                ((uint16_t)0x0060)            /*!< PG[5] pin */
02751
02752 /*!< EXTI6 configuration */
02753 #define AFIO_EXTICR2_EXTI6_PA                ((uint16_t)0x0000)            /*!< PA[6] pin */
02754 #define AFIO_EXTICR2_EXTI6_PB                ((uint16_t)0x0100)            /*!< PB[6] pin */
02755 #define AFIO_EXTICR2_EXTI6_PC                ((uint16_t)0x0200)            /*!< PC[6] pin */
02756 #define AFIO_EXTICR2_EXTI6_PD                ((uint16_t)0x0300)            /*!< PD[6] pin */
02757 #define AFIO_EXTICR2_EXTI6_PE                ((uint16_t)0x0400)            /*!< PE[6] pin */
02758 #define AFIO_EXTICR2_EXTI6_PF                ((uint16_t)0x0500)            /*!< PF[6] pin */
02759 #define AFIO_EXTICR2_EXTI6_PG                ((uint16_t)0x0600)            /*!< PG[6] pin */
02760
02761 /*!< EXTI7 configuration */
02762 #define AFIO_EXTICR2_EXTI7_PA                ((uint16_t)0x0000)            /*!< PA[7] pin */
02763 #define AFIO_EXTICR2_EXTI7_PB                ((uint16_t)0x1000)            /*!< PB[7] pin */
02764 #define AFIO_EXTICR2_EXTI7_PC                ((uint16_t)0x2000)            /*!< PC[7] pin */
02765 #define AFIO_EXTICR2_EXTI7_PD                ((uint16_t)0x3000)            /*!< PD[7] pin */
02766 #define AFIO_EXTICR2_EXTI7_PE                ((uint16_t)0x4000)            /*!< PE[7] pin */
02767 #define AFIO_EXTICR2_EXTI7_PF                ((uint16_t)0x5000)            /*!< PF[7] pin */
02768 #define AFIO_EXTICR2_EXTI7_PG                ((uint16_t)0x6000)            /*!< PG[7] pin */
02769
02770 /*****************  Bit definition for AFIO_EXTICR3 register  *****************/
02771 #define AFIO_EXTICR3_EXTI8                   ((uint16_t)0x000F)            /*!< EXTI 8 configuration */
02772 #define AFIO_EXTICR3_EXTI9                   ((uint16_t)0x00F0)            /*!< EXTI 9 configuration */
02773 #define AFIO_EXTICR3_EXTI10                  ((uint16_t)0x0F00)            /*!< EXTI 10 configuration */
02774 #define AFIO_EXTICR3_EXTI11                  ((uint16_t)0xF000)            /*!< EXTI 11 configuration */
02775
02776 /*!< EXTI8 configuration */
02777 #define AFIO_EXTICR3_EXTI8_PA                ((uint16_t)0x0000)            /*!< PA[8] pin */
02778 #define AFIO_EXTICR3_EXTI8_PB                ((uint16_t)0x0001)            /*!< PB[8] pin */
02779 #define AFIO_EXTICR3_EXTI8_PC                ((uint16_t)0x0002)            /*!< PC[8] pin */
02780 #define AFIO_EXTICR3_EXTI8_PD                ((uint16_t)0x0003)            /*!< PD[8] pin */
02781 #define AFIO_EXTICR3_EXTI8_PE                ((uint16_t)0x0004)            /*!< PE[8] pin */
02782 #define AFIO_EXTICR3_EXTI8_PF                ((uint16_t)0x0005)            /*!< PF[8] pin */
02783 #define AFIO_EXTICR3_EXTI8_PG                ((uint16_t)0x0006)            /*!< PG[8] pin */
02784
02785 /*!< EXTI9 configuration */
02786 #define AFIO_EXTICR3_EXTI9_PA                ((uint16_t)0x0000)            /*!< PA[9] pin */
02787 #define AFIO_EXTICR3_EXTI9_PB                ((uint16_t)0x0010)            /*!< PB[9] pin */
02788 #define AFIO_EXTICR3_EXTI9_PC                ((uint16_t)0x0020)            /*!< PC[9] pin */
02789 #define AFIO_EXTICR3_EXTI9_PD                ((uint16_t)0x0030)            /*!< PD[9] pin */
02790 #define AFIO_EXTICR3_EXTI9_PE                ((uint16_t)0x0040)            /*!< PE[9] pin */
02791 #define AFIO_EXTICR3_EXTI9_PF                ((uint16_t)0x0050)            /*!< PF[9] pin */
02792 #define AFIO_EXTICR3_EXTI9_PG                ((uint16_t)0x0060)            /*!< PG[9] pin */
02793
02794 /*!< EXTI10 configuration */
02795 #define AFIO_EXTICR3_EXTI10_PA               ((uint16_t)0x0000)            /*!< PA[10] pin */
02796 #define AFIO_EXTICR3_EXTI10_PB               ((uint16_t)0x0100)            /*!< PB[10] pin */
02797 #define AFIO_EXTICR3_EXTI10_PC               ((uint16_t)0x0200)            /*!< PC[10] pin */
02798 #define AFIO_EXTICR3_EXTI10_PD               ((uint16_t)0x0300)            /*!< PD[10] pin */
02799 #define AFIO_EXTICR3_EXTI10_PE               ((uint16_t)0x0400)            /*!< PE[10] pin */
02800 #define AFIO_EXTICR3_EXTI10_PF               ((uint16_t)0x0500)            /*!< PF[10] pin */
02801 #define AFIO_EXTICR3_EXTI10_PG               ((uint16_t)0x0600)            /*!< PG[10] pin */
02802
02803 /*!< EXTI11 configuration */
02804 #define AFIO_EXTICR3_EXTI11_PA               ((uint16_t)0x0000)            /*!< PA[11] pin */
02805 #define AFIO_EXTICR3_EXTI11_PB               ((uint16_t)0x1000)            /*!< PB[11] pin */
02806 #define AFIO_EXTICR3_EXTI11_PC               ((uint16_t)0x2000)            /*!< PC[11] pin */
02807 #define AFIO_EXTICR3_EXTI11_PD               ((uint16_t)0x3000)            /*!< PD[11] pin */
02808 #define AFIO_EXTICR3_EXTI11_PE               ((uint16_t)0x4000)            /*!< PE[11] pin */
02809 #define AFIO_EXTICR3_EXTI11_PF               ((uint16_t)0x5000)            /*!< PF[11] pin */
02810 #define AFIO_EXTICR3_EXTI11_PG               ((uint16_t)0x6000)            /*!< PG[11] pin */
02811
02812 /*****************  Bit definition for AFIO_EXTICR4 register  *****************/
02813 #define AFIO_EXTICR4_EXTI12                  ((uint16_t)0x000F)            /*!< EXTI 12 configuration */
02814 #define AFIO_EXTICR4_EXTI13                  ((uint16_t)0x00F0)            /*!< EXTI 13 configuration */
02815 #define AFIO_EXTICR4_EXTI14                  ((uint16_t)0x0F00)            /*!< EXTI 14 configuration */
02816 #define AFIO_EXTICR4_EXTI15                  ((uint16_t)0xF000)            /*!< EXTI 15 configuration */
02817
02818 /* EXTI12 configuration */
02819 #define AFIO_EXTICR4_EXTI12_PA               ((uint16_t)0x0000)            /*!< PA[12] pin */
02820 #define AFIO_EXTICR4_EXTI12_PB               ((uint16_t)0x0001)            /*!< PB[12] pin */
02821 #define AFIO_EXTICR4_EXTI12_PC               ((uint16_t)0x0002)            /*!< PC[12] pin */
02822 #define AFIO_EXTICR4_EXTI12_PD               ((uint16_t)0x0003)            /*!< PD[12] pin */
02823 #define AFIO_EXTICR4_EXTI12_PE               ((uint16_t)0x0004)            /*!< PE[12] pin */
02824 #define AFIO_EXTICR4_EXTI12_PF               ((uint16_t)0x0005)            /*!< PF[12] pin */
02825 #define AFIO_EXTICR4_EXTI12_PG               ((uint16_t)0x0006)            /*!< PG[12] pin */
02826
02827 /* EXTI13 configuration */
02828 #define AFIO_EXTICR4_EXTI13_PA               ((uint16_t)0x0000)            /*!< PA[13] pin */
02829 #define AFIO_EXTICR4_EXTI13_PB               ((uint16_t)0x0010)            /*!< PB[13] pin */
02830 #define AFIO_EXTICR4_EXTI13_PC               ((uint16_t)0x0020)            /*!< PC[13] pin */
02831 #define AFIO_EXTICR4_EXTI13_PD               ((uint16_t)0x0030)            /*!< PD[13] pin */
02832 #define AFIO_EXTICR4_EXTI13_PE               ((uint16_t)0x0040)            /*!< PE[13] pin */
02833 #define AFIO_EXTICR4_EXTI13_PF               ((uint16_t)0x0050)            /*!< PF[13] pin */
02834 #define AFIO_EXTICR4_EXTI13_PG               ((uint16_t)0x0060)            /*!< PG[13] pin */
02835
02836 /*!< EXTI14 configuration */
02837 #define AFIO_EXTICR4_EXTI14_PA               ((uint16_t)0x0000)            /*!< PA[14] pin */
02838 #define AFIO_EXTICR4_EXTI14_PB               ((uint16_t)0x0100)            /*!< PB[14] pin */
02839 #define AFIO_EXTICR4_EXTI14_PC               ((uint16_t)0x0200)            /*!< PC[14] pin */
02840 #define AFIO_EXTICR4_EXTI14_PD               ((uint16_t)0x0300)            /*!< PD[14] pin */
02841 #define AFIO_EXTICR4_EXTI14_PE               ((uint16_t)0x0400)            /*!< PE[14] pin */
02842 #define AFIO_EXTICR4_EXTI14_PF               ((uint16_t)0x0500)            /*!< PF[14] pin */
02843 #define AFIO_EXTICR4_EXTI14_PG               ((uint16_t)0x0600)            /*!< PG[14] pin */
02844
02845 /*!< EXTI15 configuration */
02846 #define AFIO_EXTICR4_EXTI15_PA               ((uint16_t)0x0000)            /*!< PA[15] pin */
02847 #define AFIO_EXTICR4_EXTI15_PB               ((uint16_t)0x1000)            /*!< PB[15] pin */
02848 #define AFIO_EXTICR4_EXTI15_PC               ((uint16_t)0x2000)            /*!< PC[15] pin */
02849 #define AFIO_EXTICR4_EXTI15_PD               ((uint16_t)0x3000)            /*!< PD[15] pin */
02850 #define AFIO_EXTICR4_EXTI15_PE               ((uint16_t)0x4000)            /*!< PE[15] pin */
02851 #define AFIO_EXTICR4_EXTI15_PF               ((uint16_t)0x5000)            /*!< PF[15] pin */
02852 #define AFIO_EXTICR4_EXTI15_PG               ((uint16_t)0x6000)            /*!< PG[15] pin */
02853
02854 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
02855 /******************  Bit definition for AFIO_MAPR2 register  ******************/
02856 #define AFIO_MAPR2_TIM15_REMAP               ((uint32_t)0x00000001)        /*!< TIM15 remapping */
02857 #define AFIO_MAPR2_TIM16_REMAP               ((uint32_t)0x00000002)        /*!< TIM16 remapping */
02858 #define AFIO_MAPR2_TIM17_REMAP               ((uint32_t)0x00000004)        /*!< TIM17 remapping */
02859 #define AFIO_MAPR2_CEC_REMAP                 ((uint32_t)0x00000008)        /*!< CEC remapping */
02860 #define AFIO_MAPR2_TIM1_DMA_REMAP            ((uint32_t)0x00000010)        /*!< TIM1_DMA remapping */
02861 #endif
02862
02863 #ifdef STM32F10X_HD_VL
02864 #define AFIO_MAPR2_TIM13_REMAP               ((uint32_t)0x00000100)        /*!< TIM13 remapping */
02865 #define AFIO_MAPR2_TIM14_REMAP               ((uint32_t)0x00000200)        /*!< TIM14 remapping */
02866 #define AFIO_MAPR2_FSMC_NADV_REMAP           ((uint32_t)0x00000400)        /*!< FSMC NADV remapping */
02867 #define AFIO_MAPR2_TIM67_DAC_DMA_REMAP       ((uint32_t)0x00000800)        /*!< TIM6/TIM7 and DAC DMA remapping */
02868 #define AFIO_MAPR2_TIM12_REMAP               ((uint32_t)0x00001000)        /*!< TIM12 remapping */
02869 #define AFIO_MAPR2_MISC_REMAP                ((uint32_t)0x00002000)        /*!< Miscellaneous remapping */
02870 #endif
02871
02872 #ifdef STM32F10X_XL
02873 /******************  Bit definition for AFIO_MAPR2 register  ******************/
02874 #define AFIO_MAPR2_TIM9_REMAP                ((uint32_t)0x00000020)        /*!< TIM9 remapping */
02875 #define AFIO_MAPR2_TIM10_REMAP               ((uint32_t)0x00000040)        /*!< TIM10 remapping */
02876 #define AFIO_MAPR2_TIM11_REMAP               ((uint32_t)0x00000080)        /*!< TIM11 remapping */
02877 #define AFIO_MAPR2_TIM13_REMAP               ((uint32_t)0x00000100)        /*!< TIM13 remapping */
02878 #define AFIO_MAPR2_TIM14_REMAP               ((uint32_t)0x00000200)        /*!< TIM14 remapping */
02879 #define AFIO_MAPR2_FSMC_NADV_REMAP           ((uint32_t)0x00000400)        /*!< FSMC NADV remapping */
02880 #endif
02881
02882 /******************************************************************************/
02883 /*                                                                            */
02884 /*                               SystemTick                                   */
02885 /*                                                                            */
02886 /******************************************************************************/
02887
02888 /*****************  Bit definition for SysTick_CTRL register  *****************/
02889 #define  SysTick_CTRL_ENABLE                 ((uint32_t)0x00000001)        /*!< Counter enable */
02890 #define  SysTick_CTRL_TICKINT                ((uint32_t)0x00000002)        /*!< Counting down to 0 pends the SysTick handler */
02891 #define  SysTick_CTRL_CLKSOURCE              ((uint32_t)0x00000004)        /*!< Clock source */
02892 #define  SysTick_CTRL_COUNTFLAG              ((uint32_t)0x00010000)        /*!< Count Flag */
02893
02894 /*****************  Bit definition for SysTick_LOAD register  *****************/
02895 #define  SysTick_LOAD_RELOAD                 ((uint32_t)0x00FFFFFF)        /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */
02896
02897 /*****************  Bit definition for SysTick_VAL register  ******************/
02898 #define  SysTick_VAL_CURRENT                 ((uint32_t)0x00FFFFFF)        /*!< Current value at the time the register is accessed */
02899
02900 /*****************  Bit definition for SysTick_CALIB register  ****************/
02901 #define  SysTick_CALIB_TENMS                 ((uint32_t)0x00FFFFFF)        /*!< Reload value to use for 10ms timing */
02902 #define  SysTick_CALIB_SKEW                  ((uint32_t)0x40000000)        /*!< Calibration value is not exactly 10 ms */
02903 #define  SysTick_CALIB_NOREF                 ((uint32_t)0x80000000)        /*!< The reference clock is not provided */
02904
02905 /******************************************************************************/
02906 /*                                                                            */
02907 /*                  Nested Vectored Interrupt Controller                      */
02908 /*                                                                            */
02909 /******************************************************************************/
02910
02911 /******************  Bit definition for NVIC_ISER register  *******************/
02912 #define  NVIC_ISER_SETENA                    ((uint32_t)0xFFFFFFFF)        /*!< Interrupt set enable bits */
02913 #define  NVIC_ISER_SETENA_0                  ((uint32_t)0x00000001)        /*!< bit 0 */
02914 #define  NVIC_ISER_SETENA_1                  ((uint32_t)0x00000002)        /*!< bit 1 */
02915 #define  NVIC_ISER_SETENA_2                  ((uint32_t)0x00000004)        /*!< bit 2 */
02916 #define  NVIC_ISER_SETENA_3                  ((uint32_t)0x00000008)        /*!< bit 3 */
02917 #define  NVIC_ISER_SETENA_4                  ((uint32_t)0x00000010)        /*!< bit 4 */
02918 #define  NVIC_ISER_SETENA_5                  ((uint32_t)0x00000020)        /*!< bit 5 */
02919 #define  NVIC_ISER_SETENA_6                  ((uint32_t)0x00000040)        /*!< bit 6 */
02920 #define  NVIC_ISER_SETENA_7                  ((uint32_t)0x00000080)        /*!< bit 7 */
02921 #define  NVIC_ISER_SETENA_8                  ((uint32_t)0x00000100)        /*!< bit 8 */
02922 #define  NVIC_ISER_SETENA_9                  ((uint32_t)0x00000200)        /*!< bit 9 */
02923 #define  NVIC_ISER_SETENA_10                 ((uint32_t)0x00000400)        /*!< bit 10 */
02924 #define  NVIC_ISER_SETENA_11                 ((uint32_t)0x00000800)        /*!< bit 11 */
02925 #define  NVIC_ISER_SETENA_12                 ((uint32_t)0x00001000)        /*!< bit 12 */
02926 #define  NVIC_ISER_SETENA_13                 ((uint32_t)0x00002000)        /*!< bit 13 */
02927 #define  NVIC_ISER_SETENA_14                 ((uint32_t)0x00004000)        /*!< bit 14 */
02928 #define  NVIC_ISER_SETENA_15                 ((uint32_t)0x00008000)        /*!< bit 15 */
02929 #define  NVIC_ISER_SETENA_16                 ((uint32_t)0x00010000)        /*!< bit 16 */
02930 #define  NVIC_ISER_SETENA_17                 ((uint32_t)0x00020000)        /*!< bit 17 */
02931 #define  NVIC_ISER_SETENA_18                 ((uint32_t)0x00040000)        /*!< bit 18 */
02932 #define  NVIC_ISER_SETENA_19                 ((uint32_t)0x00080000)        /*!< bit 19 */
02933 #define  NVIC_ISER_SETENA_20                 ((uint32_t)0x00100000)        /*!< bit 20 */
02934 #define  NVIC_ISER_SETENA_21                 ((uint32_t)0x00200000)        /*!< bit 21 */
02935 #define  NVIC_ISER_SETENA_22                 ((uint32_t)0x00400000)        /*!< bit 22 */
02936 #define  NVIC_ISER_SETENA_23                 ((uint32_t)0x00800000)        /*!< bit 23 */
02937 #define  NVIC_ISER_SETENA_24                 ((uint32_t)0x01000000)        /*!< bit 24 */
02938 #define  NVIC_ISER_SETENA_25                 ((uint32_t)0x02000000)        /*!< bit 25 */
02939 #define  NVIC_ISER_SETENA_26                 ((uint32_t)0x04000000)        /*!< bit 26 */
02940 #define  NVIC_ISER_SETENA_27                 ((uint32_t)0x08000000)        /*!< bit 27 */
02941 #define  NVIC_ISER_SETENA_28                 ((uint32_t)0x10000000)        /*!< bit 28 */
02942 #define  NVIC_ISER_SETENA_29                 ((uint32_t)0x20000000)        /*!< bit 29 */
02943 #define  NVIC_ISER_SETENA_30                 ((uint32_t)0x40000000)        /*!< bit 30 */
02944 #define  NVIC_ISER_SETENA_31                 ((uint32_t)0x80000000)        /*!< bit 31 */
02945
02946 /******************  Bit definition for NVIC_ICER register  *******************/
02947 #define  NVIC_ICER_CLRENA                   ((uint32_t)0xFFFFFFFF)        /*!< Interrupt clear-enable bits */
02948 #define  NVIC_ICER_CLRENA_0                  ((uint32_t)0x00000001)        /*!< bit 0 */
02949 #define  NVIC_ICER_CLRENA_1                  ((uint32_t)0x00000002)        /*!< bit 1 */
02950 #define  NVIC_ICER_CLRENA_2                  ((uint32_t)0x00000004)        /*!< bit 2 */
02951 #define  NVIC_ICER_CLRENA_3                  ((uint32_t)0x00000008)        /*!< bit 3 */
02952 #define  NVIC_ICER_CLRENA_4                  ((uint32_t)0x00000010)        /*!< bit 4 */
02953 #define  NVIC_ICER_CLRENA_5                  ((uint32_t)0x00000020)        /*!< bit 5 */
02954 #define  NVIC_ICER_CLRENA_6                  ((uint32_t)0x00000040)        /*!< bit 6 */
02955 #define  NVIC_ICER_CLRENA_7                  ((uint32_t)0x00000080)        /*!< bit 7 */
02956 #define  NVIC_ICER_CLRENA_8                  ((uint32_t)0x00000100)        /*!< bit 8 */
02957 #define  NVIC_ICER_CLRENA_9                  ((uint32_t)0x00000200)        /*!< bit 9 */
02958 #define  NVIC_ICER_CLRENA_10                 ((uint32_t)0x00000400)        /*!< bit 10 */
02959 #define  NVIC_ICER_CLRENA_11                 ((uint32_t)0x00000800)        /*!< bit 11 */
02960 #define  NVIC_ICER_CLRENA_12                 ((uint32_t)0x00001000)        /*!< bit 12 */
02961 #define  NVIC_ICER_CLRENA_13                 ((uint32_t)0x00002000)        /*!< bit 13 */
02962 #define  NVIC_ICER_CLRENA_14                 ((uint32_t)0x00004000)        /*!< bit 14 */
02963 #define  NVIC_ICER_CLRENA_15                 ((uint32_t)0x00008000)        /*!< bit 15 */
02964 #define  NVIC_ICER_CLRENA_16                 ((uint32_t)0x00010000)        /*!< bit 16 */
02965 #define  NVIC_ICER_CLRENA_17                 ((uint32_t)0x00020000)        /*!< bit 17 */
02966 #define  NVIC_ICER_CLRENA_18                 ((uint32_t)0x00040000)        /*!< bit 18 */
02967 #define  NVIC_ICER_CLRENA_19                 ((uint32_t)0x00080000)        /*!< bit 19 */
02968 #define  NVIC_ICER_CLRENA_20                 ((uint32_t)0x00100000)        /*!< bit 20 */
02969 #define  NVIC_ICER_CLRENA_21                 ((uint32_t)0x00200000)        /*!< bit 21 */
02970 #define  NVIC_ICER_CLRENA_22                 ((uint32_t)0x00400000)        /*!< bit 22 */
02971 #define  NVIC_ICER_CLRENA_23                 ((uint32_t)0x00800000)        /*!< bit 23 */
02972 #define  NVIC_ICER_CLRENA_24                 ((uint32_t)0x01000000)        /*!< bit 24 */
02973 #define  NVIC_ICER_CLRENA_25                 ((uint32_t)0x02000000)        /*!< bit 25 */
02974 #define  NVIC_ICER_CLRENA_26                 ((uint32_t)0x04000000)        /*!< bit 26 */
02975 #define  NVIC_ICER_CLRENA_27                 ((uint32_t)0x08000000)        /*!< bit 27 */
02976 #define  NVIC_ICER_CLRENA_28                 ((uint32_t)0x10000000)        /*!< bit 28 */
02977 #define  NVIC_ICER_CLRENA_29                 ((uint32_t)0x20000000)        /*!< bit 29 */
02978 #define  NVIC_ICER_CLRENA_30                 ((uint32_t)0x40000000)        /*!< bit 30 */
02979 #define  NVIC_ICER_CLRENA_31                 ((uint32_t)0x80000000)        /*!< bit 31 */
02980
02981 /******************  Bit definition for NVIC_ISPR register  *******************/
02982 #define  NVIC_ISPR_SETPEND                   ((uint32_t)0xFFFFFFFF)        /*!< Interrupt set-pending bits */
02983 #define  NVIC_ISPR_SETPEND_0                 ((uint32_t)0x00000001)        /*!< bit 0 */
02984 #define  NVIC_ISPR_SETPEND_1                 ((uint32_t)0x00000002)        /*!< bit 1 */
02985 #define  NVIC_ISPR_SETPEND_2                 ((uint32_t)0x00000004)        /*!< bit 2 */
02986 #define  NVIC_ISPR_SETPEND_3                 ((uint32_t)0x00000008)        /*!< bit 3 */
02987 #define  NVIC_ISPR_SETPEND_4                 ((uint32_t)0x00000010)        /*!< bit 4 */
02988 #define  NVIC_ISPR_SETPEND_5                 ((uint32_t)0x00000020)        /*!< bit 5 */
02989 #define  NVIC_ISPR_SETPEND_6                 ((uint32_t)0x00000040)        /*!< bit 6 */
02990 #define  NVIC_ISPR_SETPEND_7                 ((uint32_t)0x00000080)        /*!< bit 7 */
02991 #define  NVIC_ISPR_SETPEND_8                 ((uint32_t)0x00000100)        /*!< bit 8 */
02992 #define  NVIC_ISPR_SETPEND_9                 ((uint32_t)0x00000200)        /*!< bit 9 */
02993 #define  NVIC_ISPR_SETPEND_10                ((uint32_t)0x00000400)        /*!< bit 10 */
02994 #define  NVIC_ISPR_SETPEND_11                ((uint32_t)0x00000800)        /*!< bit 11 */
02995 #define  NVIC_ISPR_SETPEND_12                ((uint32_t)0x00001000)        /*!< bit 12 */
02996 #define  NVIC_ISPR_SETPEND_13                ((uint32_t)0x00002000)        /*!< bit 13 */
02997 #define  NVIC_ISPR_SETPEND_14                ((uint32_t)0x00004000)        /*!< bit 14 */
02998 #define  NVIC_ISPR_SETPEND_15                ((uint32_t)0x00008000)        /*!< bit 15 */
02999 #define  NVIC_ISPR_SETPEND_16                ((uint32_t)0x00010000)        /*!< bit 16 */
03000 #define  NVIC_ISPR_SETPEND_17                ((uint32_t)0x00020000)        /*!< bit 17 */
03001 #define  NVIC_ISPR_SETPEND_18                ((uint32_t)0x00040000)        /*!< bit 18 */
03002 #define  NVIC_ISPR_SETPEND_19                ((uint32_t)0x00080000)        /*!< bit 19 */
03003 #define  NVIC_ISPR_SETPEND_20                ((uint32_t)0x00100000)        /*!< bit 20 */
03004 #define  NVIC_ISPR_SETPEND_21                ((uint32_t)0x00200000)        /*!< bit 21 */
03005 #define  NVIC_ISPR_SETPEND_22                ((uint32_t)0x00400000)        /*!< bit 22 */
03006 #define  NVIC_ISPR_SETPEND_23                ((uint32_t)0x00800000)        /*!< bit 23 */
03007 #define  NVIC_ISPR_SETPEND_24                ((uint32_t)0x01000000)        /*!< bit 24 */
03008 #define  NVIC_ISPR_SETPEND_25                ((uint32_t)0x02000000)        /*!< bit 25 */
03009 #define  NVIC_ISPR_SETPEND_26                ((uint32_t)0x04000000)        /*!< bit 26 */
03010 #define  NVIC_ISPR_SETPEND_27                ((uint32_t)0x08000000)        /*!< bit 27 */
03011 #define  NVIC_ISPR_SETPEND_28                ((uint32_t)0x10000000)        /*!< bit 28 */
03012 #define  NVIC_ISPR_SETPEND_29                ((uint32_t)0x20000000)        /*!< bit 29 */
03013 #define  NVIC_ISPR_SETPEND_30                ((uint32_t)0x40000000)        /*!< bit 30 */
03014 #define  NVIC_ISPR_SETPEND_31                ((uint32_t)0x80000000)        /*!< bit 31 */
03015
03016 /******************  Bit definition for NVIC_ICPR register  *******************/
03017 #define  NVIC_ICPR_CLRPEND                   ((uint32_t)0xFFFFFFFF)        /*!< Interrupt clear-pending bits */
03018 #define  NVIC_ICPR_CLRPEND_0                 ((uint32_t)0x00000001)        /*!< bit 0 */
03019 #define  NVIC_ICPR_CLRPEND_1                 ((uint32_t)0x00000002)        /*!< bit 1 */
03020 #define  NVIC_ICPR_CLRPEND_2                 ((uint32_t)0x00000004)        /*!< bit 2 */
03021 #define  NVIC_ICPR_CLRPEND_3                 ((uint32_t)0x00000008)        /*!< bit 3 */
03022 #define  NVIC_ICPR_CLRPEND_4                 ((uint32_t)0x00000010)        /*!< bit 4 */
03023 #define  NVIC_ICPR_CLRPEND_5                 ((uint32_t)0x00000020)        /*!< bit 5 */
03024 #define  NVIC_ICPR_CLRPEND_6                 ((uint32_t)0x00000040)        /*!< bit 6 */
03025 #define  NVIC_ICPR_CLRPEND_7                 ((uint32_t)0x00000080)        /*!< bit 7 */
03026 #define  NVIC_ICPR_CLRPEND_8                 ((uint32_t)0x00000100)        /*!< bit 8 */
03027 #define  NVIC_ICPR_CLRPEND_9                 ((uint32_t)0x00000200)        /*!< bit 9 */
03028 #define  NVIC_ICPR_CLRPEND_10                ((uint32_t)0x00000400)        /*!< bit 10 */
03029 #define  NVIC_ICPR_CLRPEND_11                ((uint32_t)0x00000800)        /*!< bit 11 */
03030 #define  NVIC_ICPR_CLRPEND_12                ((uint32_t)0x00001000)        /*!< bit 12 */
03031 #define  NVIC_ICPR_CLRPEND_13                ((uint32_t)0x00002000)        /*!< bit 13 */
03032 #define  NVIC_ICPR_CLRPEND_14                ((uint32_t)0x00004000)        /*!< bit 14 */
03033 #define  NVIC_ICPR_CLRPEND_15                ((uint32_t)0x00008000)        /*!< bit 15 */
03034 #define  NVIC_ICPR_CLRPEND_16                ((uint32_t)0x00010000)        /*!< bit 16 */
03035 #define  NVIC_ICPR_CLRPEND_17                ((uint32_t)0x00020000)        /*!< bit 17 */
03036 #define  NVIC_ICPR_CLRPEND_18                ((uint32_t)0x00040000)        /*!< bit 18 */
03037 #define  NVIC_ICPR_CLRPEND_19                ((uint32_t)0x00080000)        /*!< bit 19 */
03038 #define  NVIC_ICPR_CLRPEND_20                ((uint32_t)0x00100000)        /*!< bit 20 */
03039 #define  NVIC_ICPR_CLRPEND_21                ((uint32_t)0x00200000)        /*!< bit 21 */
03040 #define  NVIC_ICPR_CLRPEND_22                ((uint32_t)0x00400000)        /*!< bit 22 */
03041 #define  NVIC_ICPR_CLRPEND_23                ((uint32_t)0x00800000)        /*!< bit 23 */
03042 #define  NVIC_ICPR_CLRPEND_24                ((uint32_t)0x01000000)        /*!< bit 24 */
03043 #define  NVIC_ICPR_CLRPEND_25                ((uint32_t)0x02000000)        /*!< bit 25 */
03044 #define  NVIC_ICPR_CLRPEND_26                ((uint32_t)0x04000000)        /*!< bit 26 */
03045 #define  NVIC_ICPR_CLRPEND_27                ((uint32_t)0x08000000)        /*!< bit 27 */
03046 #define  NVIC_ICPR_CLRPEND_28                ((uint32_t)0x10000000)        /*!< bit 28 */
03047 #define  NVIC_ICPR_CLRPEND_29                ((uint32_t)0x20000000)        /*!< bit 29 */
03048 #define  NVIC_ICPR_CLRPEND_30                ((uint32_t)0x40000000)        /*!< bit 30 */
03049 #define  NVIC_ICPR_CLRPEND_31                ((uint32_t)0x80000000)        /*!< bit 31 */
03050
03051 /******************  Bit definition for NVIC_IABR register  *******************/
03052 #define  NVIC_IABR_ACTIVE                    ((uint32_t)0xFFFFFFFF)        /*!< Interrupt active flags */
03053 #define  NVIC_IABR_ACTIVE_0                  ((uint32_t)0x00000001)        /*!< bit 0 */
03054 #define  NVIC_IABR_ACTIVE_1                  ((uint32_t)0x00000002)        /*!< bit 1 */
03055 #define  NVIC_IABR_ACTIVE_2                  ((uint32_t)0x00000004)        /*!< bit 2 */
03056 #define  NVIC_IABR_ACTIVE_3                  ((uint32_t)0x00000008)        /*!< bit 3 */
03057 #define  NVIC_IABR_ACTIVE_4                  ((uint32_t)0x00000010)        /*!< bit 4 */
03058 #define  NVIC_IABR_ACTIVE_5                  ((uint32_t)0x00000020)        /*!< bit 5 */
03059 #define  NVIC_IABR_ACTIVE_6                  ((uint32_t)0x00000040)        /*!< bit 6 */
03060 #define  NVIC_IABR_ACTIVE_7                  ((uint32_t)0x00000080)        /*!< bit 7 */
03061 #define  NVIC_IABR_ACTIVE_8                  ((uint32_t)0x00000100)        /*!< bit 8 */
03062 #define  NVIC_IABR_ACTIVE_9                  ((uint32_t)0x00000200)        /*!< bit 9 */
03063 #define  NVIC_IABR_ACTIVE_10                 ((uint32_t)0x00000400)        /*!< bit 10 */
03064 #define  NVIC_IABR_ACTIVE_11                 ((uint32_t)0x00000800)        /*!< bit 11 */
03065 #define  NVIC_IABR_ACTIVE_12                 ((uint32_t)0x00001000)        /*!< bit 12 */
03066 #define  NVIC_IABR_ACTIVE_13                 ((uint32_t)0x00002000)        /*!< bit 13 */
03067 #define  NVIC_IABR_ACTIVE_14                 ((uint32_t)0x00004000)        /*!< bit 14 */
03068 #define  NVIC_IABR_ACTIVE_15                 ((uint32_t)0x00008000)        /*!< bit 15 */
03069 #define  NVIC_IABR_ACTIVE_16                 ((uint32_t)0x00010000)        /*!< bit 16 */
03070 #define  NVIC_IABR_ACTIVE_17                 ((uint32_t)0x00020000)        /*!< bit 17 */
03071 #define  NVIC_IABR_ACTIVE_18                 ((uint32_t)0x00040000)        /*!< bit 18 */
03072 #define  NVIC_IABR_ACTIVE_19                 ((uint32_t)0x00080000)        /*!< bit 19 */
03073 #define  NVIC_IABR_ACTIVE_20                 ((uint32_t)0x00100000)        /*!< bit 20 */
03074 #define  NVIC_IABR_ACTIVE_21                 ((uint32_t)0x00200000)        /*!< bit 21 */
03075 #define  NVIC_IABR_ACTIVE_22                 ((uint32_t)0x00400000)        /*!< bit 22 */
03076 #define  NVIC_IABR_ACTIVE_23                 ((uint32_t)0x00800000)        /*!< bit 23 */
03077 #define  NVIC_IABR_ACTIVE_24                 ((uint32_t)0x01000000)        /*!< bit 24 */
03078 #define  NVIC_IABR_ACTIVE_25                 ((uint32_t)0x02000000)        /*!< bit 25 */
03079 #define  NVIC_IABR_ACTIVE_26                 ((uint32_t)0x04000000)        /*!< bit 26 */
03080 #define  NVIC_IABR_ACTIVE_27                 ((uint32_t)0x08000000)        /*!< bit 27 */
03081 #define  NVIC_IABR_ACTIVE_28                 ((uint32_t)0x10000000)        /*!< bit 28 */
03082 #define  NVIC_IABR_ACTIVE_29                 ((uint32_t)0x20000000)        /*!< bit 29 */
03083 #define  NVIC_IABR_ACTIVE_30                 ((uint32_t)0x40000000)        /*!< bit 30 */
03084 #define  NVIC_IABR_ACTIVE_31                 ((uint32_t)0x80000000)        /*!< bit 31 */
03085
03086 /******************  Bit definition for NVIC_PRI0 register  *******************/
03087 #define  NVIC_IPR0_PRI_0                     ((uint32_t)0x000000FF)        /*!< Priority of interrupt 0 */
03088 #define  NVIC_IPR0_PRI_1                     ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 1 */
03089 #define  NVIC_IPR0_PRI_2                     ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 2 */
03090 #define  NVIC_IPR0_PRI_3                     ((uint32_t)0xFF000000)        /*!< Priority of interrupt 3 */
03091
03092 /******************  Bit definition for NVIC_PRI1 register  *******************/
03093 #define  NVIC_IPR1_PRI_4                     ((uint32_t)0x000000FF)        /*!< Priority of interrupt 4 */
03094 #define  NVIC_IPR1_PRI_5                     ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 5 */
03095 #define  NVIC_IPR1_PRI_6                     ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 6 */
03096 #define  NVIC_IPR1_PRI_7                     ((uint32_t)0xFF000000)        /*!< Priority of interrupt 7 */
03097
03098 /******************  Bit definition for NVIC_PRI2 register  *******************/
03099 #define  NVIC_IPR2_PRI_8                     ((uint32_t)0x000000FF)        /*!< Priority of interrupt 8 */
03100 #define  NVIC_IPR2_PRI_9                     ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 9 */
03101 #define  NVIC_IPR2_PRI_10                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 10 */
03102 #define  NVIC_IPR2_PRI_11                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 11 */
03103
03104 /******************  Bit definition for NVIC_PRI3 register  *******************/
03105 #define  NVIC_IPR3_PRI_12                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 12 */
03106 #define  NVIC_IPR3_PRI_13                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 13 */
03107 #define  NVIC_IPR3_PRI_14                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 14 */
03108 #define  NVIC_IPR3_PRI_15                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 15 */
03109
03110 /******************  Bit definition for NVIC_PRI4 register  *******************/
03111 #define  NVIC_IPR4_PRI_16                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 16 */
03112 #define  NVIC_IPR4_PRI_17                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 17 */
03113 #define  NVIC_IPR4_PRI_18                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 18 */
03114 #define  NVIC_IPR4_PRI_19                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 19 */
03115
03116 /******************  Bit definition for NVIC_PRI5 register  *******************/
03117 #define  NVIC_IPR5_PRI_20                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 20 */
03118 #define  NVIC_IPR5_PRI_21                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 21 */
03119 #define  NVIC_IPR5_PRI_22                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 22 */
03120 #define  NVIC_IPR5_PRI_23                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 23 */
03121
03122 /******************  Bit definition for NVIC_PRI6 register  *******************/
03123 #define  NVIC_IPR6_PRI_24                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 24 */
03124 #define  NVIC_IPR6_PRI_25                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 25 */
03125 #define  NVIC_IPR6_PRI_26                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 26 */
03126 #define  NVIC_IPR6_PRI_27                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 27 */
03127
03128 /******************  Bit definition for NVIC_PRI7 register  *******************/
03129 #define  NVIC_IPR7_PRI_28                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 28 */
03130 #define  NVIC_IPR7_PRI_29                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 29 */
03131 #define  NVIC_IPR7_PRI_30                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 30 */
03132 #define  NVIC_IPR7_PRI_31                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 31 */
03133
03134 /******************  Bit definition for SCB_CPUID register  *******************/
03135 #define  SCB_CPUID_REVISION                  ((uint32_t)0x0000000F)        /*!< Implementation defined revision number */
03136 #define  SCB_CPUID_PARTNO                    ((uint32_t)0x0000FFF0)        /*!< Number of processor within family */
03137 #define  SCB_CPUID_Constant                  ((uint32_t)0x000F0000)        /*!< Reads as 0x0F */
03138 #define  SCB_CPUID_VARIANT                   ((uint32_t)0x00F00000)        /*!< Implementation defined variant number */
03139 #define  SCB_CPUID_IMPLEMENTER               ((uint32_t)0xFF000000)        /*!< Implementer code. ARM is 0x41 */
03140
03141 /*******************  Bit definition for SCB_ICSR register  *******************/
03142 #define  SCB_ICSR_VECTACTIVE                 ((uint32_t)0x000001FF)        /*!< Active ISR number field */
03143 #define  SCB_ICSR_RETTOBASE                  ((uint32_t)0x00000800)        /*!< All active exceptions minus the IPSR_current_exception yields the empty set */
03144 #define  SCB_ICSR_VECTPENDING                ((uint32_t)0x003FF000)        /*!< Pending ISR number field */
03145 #define  SCB_ICSR_ISRPENDING                 ((uint32_t)0x00400000)        /*!< Interrupt pending flag */
03146 #define  SCB_ICSR_ISRPREEMPT                 ((uint32_t)0x00800000)        /*!< It indicates that a pending interrupt becomes active in the next running cycle */
03147 #define  SCB_ICSR_PENDSTCLR                  ((uint32_t)0x02000000)        /*!< Clear pending SysTick bit */
03148 #define  SCB_ICSR_PENDSTSET                  ((uint32_t)0x04000000)        /*!< Set pending SysTick bit */
03149 #define  SCB_ICSR_PENDSVCLR                  ((uint32_t)0x08000000)        /*!< Clear pending pendSV bit */
03150 #define  SCB_ICSR_PENDSVSET                  ((uint32_t)0x10000000)        /*!< Set pending pendSV bit */
03151 #define  SCB_ICSR_NMIPENDSET                 ((uint32_t)0x80000000)        /*!< Set pending NMI bit */
03152
03153 /*******************  Bit definition for SCB_VTOR register  *******************/
03154 #define  SCB_VTOR_TBLOFF                     ((uint32_t)0x1FFFFF80)        /*!< Vector table base offset field */
03155 #define  SCB_VTOR_TBLBASE                    ((uint32_t)0x20000000)        /*!< Table base in code(0) or RAM(1) */
03156
03157 /*!<*****************  Bit definition for SCB_AIRCR register  *******************/
03158 #define  SCB_AIRCR_VECTRESET                 ((uint32_t)0x00000001)        /*!< System Reset bit */
03159 #define  SCB_AIRCR_VECTCLRACTIVE             ((uint32_t)0x00000002)        /*!< Clear active vector bit */
03160 #define  SCB_AIRCR_SYSRESETREQ               ((uint32_t)0x00000004)        /*!< Requests chip control logic to generate a reset */
03161
03162 #define  SCB_AIRCR_PRIGROUP                  ((uint32_t)0x00000700)        /*!< PRIGROUP[2:0] bits (Priority group) */
03163 #define  SCB_AIRCR_PRIGROUP_0                ((uint32_t)0x00000100)        /*!< Bit 0 */
03164 #define  SCB_AIRCR_PRIGROUP_1                ((uint32_t)0x00000200)        /*!< Bit 1 */
03165 #define  SCB_AIRCR_PRIGROUP_2                ((uint32_t)0x00000400)        /*!< Bit 2  */
03166
03167 /* prority group configuration */
03168 #define  SCB_AIRCR_PRIGROUP0                 ((uint32_t)0x00000000)        /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */
03169 #define  SCB_AIRCR_PRIGROUP1                 ((uint32_t)0x00000100)        /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */
03170 #define  SCB_AIRCR_PRIGROUP2                 ((uint32_t)0x00000200)        /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */
03171 #define  SCB_AIRCR_PRIGROUP3                 ((uint32_t)0x00000300)        /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */
03172 #define  SCB_AIRCR_PRIGROUP4                 ((uint32_t)0x00000400)        /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */
03173 #define  SCB_AIRCR_PRIGROUP5                 ((uint32_t)0x00000500)        /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */
03174 #define  SCB_AIRCR_PRIGROUP6                 ((uint32_t)0x00000600)        /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */
03175 #define  SCB_AIRCR_PRIGROUP7                 ((uint32_t)0x00000700)        /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */
03176
03177 #define  SCB_AIRCR_ENDIANESS                 ((uint32_t)0x00008000)        /*!< Data endianness bit */
03178 #define  SCB_AIRCR_VECTKEY                   ((uint32_t)0xFFFF0000)        /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */
03179
03180 /*******************  Bit definition for SCB_SCR register  ********************/
03181 #define  SCB_SCR_SLEEPONEXIT                 ((uint8_t)0x02)               /*!< Sleep on exit bit */
03182 #define  SCB_SCR_SLEEPDEEP                   ((uint8_t)0x04)               /*!< Sleep deep bit */
03183 #define  SCB_SCR_SEVONPEND                   ((uint8_t)0x10)               /*!< Wake up from WFE */
03184
03185 /********************  Bit definition for SCB_CCR register  *******************/
03186 #define  SCB_CCR_NONBASETHRDENA              ((uint16_t)0x0001)            /*!< Thread mode can be entered from any level in Handler mode by controlled return value */
03187 #define  SCB_CCR_USERSETMPEND                ((uint16_t)0x0002)            /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */
03188 #define  SCB_CCR_UNALIGN_TRP                 ((uint16_t)0x0008)            /*!< Trap for unaligned access */
03189 #define  SCB_CCR_DIV_0_TRP                   ((uint16_t)0x0010)            /*!< Trap on Divide by 0 */
03190 #define  SCB_CCR_BFHFNMIGN                   ((uint16_t)0x0100)            /*!< Handlers running at priority -1 and -2 */
03191 #define  SCB_CCR_STKALIGN                    ((uint16_t)0x0200)            /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */
03192
03193 /*******************  Bit definition for SCB_SHPR register ********************/
03194 #define  SCB_SHPR_PRI_N                      ((uint32_t)0x000000FF)        /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */
03195 #define  SCB_SHPR_PRI_N1                     ((uint32_t)0x0000FF00)        /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */
03196 #define  SCB_SHPR_PRI_N2                     ((uint32_t)0x00FF0000)        /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */
03197 #define  SCB_SHPR_PRI_N3                     ((uint32_t)0xFF000000)        /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */
03198
03199 /******************  Bit definition for SCB_SHCSR register  *******************/
03200 #define  SCB_SHCSR_MEMFAULTACT               ((uint32_t)0x00000001)        /*!< MemManage is active */
03201 #define  SCB_SHCSR_BUSFAULTACT               ((uint32_t)0x00000002)        /*!< BusFault is active */
03202 #define  SCB_SHCSR_USGFAULTACT               ((uint32_t)0x00000008)        /*!< UsageFault is active */
03203 #define  SCB_SHCSR_SVCALLACT                 ((uint32_t)0x00000080)        /*!< SVCall is active */
03204 #define  SCB_SHCSR_MONITORACT                ((uint32_t)0x00000100)        /*!< Monitor is active */
03205 #define  SCB_SHCSR_PENDSVACT                 ((uint32_t)0x00000400)        /*!< PendSV is active */
03206 #define  SCB_SHCSR_SYSTICKACT                ((uint32_t)0x00000800)        /*!< SysTick is active */
03207 #define  SCB_SHCSR_USGFAULTPENDED            ((uint32_t)0x00001000)        /*!< Usage Fault is pended */
03208 #define  SCB_SHCSR_MEMFAULTPENDED            ((uint32_t)0x00002000)        /*!< MemManage is pended */
03209 #define  SCB_SHCSR_BUSFAULTPENDED            ((uint32_t)0x00004000)        /*!< Bus Fault is pended */
03210 #define  SCB_SHCSR_SVCALLPENDED              ((uint32_t)0x00008000)        /*!< SVCall is pended */
03211 #define  SCB_SHCSR_MEMFAULTENA               ((uint32_t)0x00010000)        /*!< MemManage enable */
03212 #define  SCB_SHCSR_BUSFAULTENA               ((uint32_t)0x00020000)        /*!< Bus Fault enable */
03213 #define  SCB_SHCSR_USGFAULTENA               ((uint32_t)0x00040000)        /*!< UsageFault enable */
03214
03215 /*******************  Bit definition for SCB_CFSR register  *******************/
03216 /*!< MFSR */
03217 #define  SCB_CFSR_IACCVIOL                   ((uint32_t)0x00000001)        /*!< Instruction access violation */
03218 #define  SCB_CFSR_DACCVIOL                   ((uint32_t)0x00000002)        /*!< Data access violation */
03219 #define  SCB_CFSR_MUNSTKERR                  ((uint32_t)0x00000008)        /*!< Unstacking error */
03220 #define  SCB_CFSR_MSTKERR                    ((uint32_t)0x00000010)        /*!< Stacking error */
03221 #define  SCB_CFSR_MMARVALID                  ((uint32_t)0x00000080)        /*!< Memory Manage Address Register address valid flag */
03222 /*!< BFSR */
03223 #define  SCB_CFSR_IBUSERR                    ((uint32_t)0x00000100)        /*!< Instruction bus error flag */
03224 #define  SCB_CFSR_PRECISERR                  ((uint32_t)0x00000200)        /*!< Precise data bus error */
03225 #define  SCB_CFSR_IMPRECISERR                ((uint32_t)0x00000400)        /*!< Imprecise data bus error */
03226 #define  SCB_CFSR_UNSTKERR                   ((uint32_t)0x00000800)        /*!< Unstacking error */
03227 #define  SCB_CFSR_STKERR                     ((uint32_t)0x00001000)        /*!< Stacking error */
03228 #define  SCB_CFSR_BFARVALID                  ((uint32_t)0x00008000)        /*!< Bus Fault Address Register address valid flag */
03229 /*!< UFSR */
03230 #define  SCB_CFSR_UNDEFINSTR                 ((uint32_t)0x00010000)        /*!< The processor attempt to execute an undefined instruction */
03231 #define  SCB_CFSR_INVSTATE                   ((uint32_t)0x00020000)        /*!< Invalid combination of EPSR and instruction */
03232 #define  SCB_CFSR_INVPC                      ((uint32_t)0x00040000)        /*!< Attempt to load EXC_RETURN into pc illegally */
03233 #define  SCB_CFSR_NOCP                       ((uint32_t)0x00080000)        /*!< Attempt to use a coprocessor instruction */
03234 #define  SCB_CFSR_UNALIGNED                  ((uint32_t)0x01000000)        /*!< Fault occurs when there is an attempt to make an unaligned memory access */
03235 #define  SCB_CFSR_DIVBYZERO                  ((uint32_t)0x02000000)        /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
03236
03237 /*******************  Bit definition for SCB_HFSR register  *******************/
03238 #define  SCB_HFSR_VECTTBL                    ((uint32_t)0x00000002)        /*!< Fault occurs because of vector table read on exception processing */
03239 #define  SCB_HFSR_FORCED                     ((uint32_t)0x40000000)        /*!< Hard Fault activated when a configurable Fault was received and cannot activate */
03240 #define  SCB_HFSR_DEBUGEVT                   ((uint32_t)0x80000000)        /*!< Fault related to debug */
03241
03242 /*******************  Bit definition for SCB_DFSR register  *******************/
03243 #define  SCB_DFSR_HALTED                     ((uint8_t)0x01)               /*!< Halt request flag */
03244 #define  SCB_DFSR_BKPT                       ((uint8_t)0x02)               /*!< BKPT flag */
03245 #define  SCB_DFSR_DWTTRAP                    ((uint8_t)0x04)               /*!< Data Watchpoint and Trace (DWT) flag */
03246 #define  SCB_DFSR_VCATCH                     ((uint8_t)0x08)               /*!< Vector catch flag */
03247 #define  SCB_DFSR_EXTERNAL                   ((uint8_t)0x10)               /*!< External debug request flag */
03248
03249 /*******************  Bit definition for SCB_MMFAR register  ******************/
03250 #define  SCB_MMFAR_ADDRESS                   ((uint32_t)0xFFFFFFFF)        /*!< Mem Manage fault address field */
03251
03252 /*******************  Bit definition for SCB_BFAR register  *******************/
03253 #define  SCB_BFAR_ADDRESS                    ((uint32_t)0xFFFFFFFF)        /*!< Bus fault address field */
03254
03255 /*******************  Bit definition for SCB_afsr register  *******************/
03256 #define  SCB_AFSR_IMPDEF                     ((uint32_t)0xFFFFFFFF)        /*!< Implementation defined */
03257
03258 /******************************************************************************/
03259 /*                                                                            */
03260 /*                    External Interrupt/Event Controller                     */
03261 /*                                                                            */
03262 /******************************************************************************/
03263
03264 /*******************  Bit definition for EXTI_IMR register  *******************/
03265 #define  EXTI_IMR_MR0                        ((uint32_t)0x00000001)        /*!< Interrupt Mask on line 0 */
03266 #define  EXTI_IMR_MR1                        ((uint32_t)0x00000002)        /*!< Interrupt Mask on line 1 */
03267 #define  EXTI_IMR_MR2                        ((uint32_t)0x00000004)        /*!< Interrupt Mask on line 2 */
03268 #define  EXTI_IMR_MR3                        ((uint32_t)0x00000008)        /*!< Interrupt Mask on line 3 */
03269 #define  EXTI_IMR_MR4                        ((uint32_t)0x00000010)        /*!< Interrupt Mask on line 4 */
03270 #define  EXTI_IMR_MR5                        ((uint32_t)0x00000020)        /*!< Interrupt Mask on line 5 */
03271 #define  EXTI_IMR_MR6                        ((uint32_t)0x00000040)        /*!< Interrupt Mask on line 6 */
03272 #define  EXTI_IMR_MR7                        ((uint32_t)0x00000080)        /*!< Interrupt Mask on line 7 */
03273 #define  EXTI_IMR_MR8                        ((uint32_t)0x00000100)        /*!< Interrupt Mask on line 8 */
03274 #define  EXTI_IMR_MR9                        ((uint32_t)0x00000200)        /*!< Interrupt Mask on line 9 */
03275 #define  EXTI_IMR_MR10                       ((uint32_t)0x00000400)        /*!< Interrupt Mask on line 10 */
03276 #define  EXTI_IMR_MR11                       ((uint32_t)0x00000800)        /*!< Interrupt Mask on line 11 */
03277 #define  EXTI_IMR_MR12                       ((uint32_t)0x00001000)        /*!< Interrupt Mask on line 12 */
03278 #define  EXTI_IMR_MR13                       ((uint32_t)0x00002000)        /*!< Interrupt Mask on line 13 */
03279 #define  EXTI_IMR_MR14                       ((uint32_t)0x00004000)        /*!< Interrupt Mask on line 14 */
03280 #define  EXTI_IMR_MR15                       ((uint32_t)0x00008000)        /*!< Interrupt Mask on line 15 */
03281 #define  EXTI_IMR_MR16                       ((uint32_t)0x00010000)        /*!< Interrupt Mask on line 16 */
03282 #define  EXTI_IMR_MR17                       ((uint32_t)0x00020000)        /*!< Interrupt Mask on line 17 */
03283 #define  EXTI_IMR_MR18                       ((uint32_t)0x00040000)        /*!< Interrupt Mask on line 18 */
03284 #define  EXTI_IMR_MR19                       ((uint32_t)0x00080000)        /*!< Interrupt Mask on line 19 */
03285
03286 /*******************  Bit definition for EXTI_EMR register  *******************/
03287 #define  EXTI_EMR_MR0                        ((uint32_t)0x00000001)        /*!< Event Mask on line 0 */
03288 #define  EXTI_EMR_MR1                        ((uint32_t)0x00000002)        /*!< Event Mask on line 1 */
03289 #define  EXTI_EMR_MR2                        ((uint32_t)0x00000004)        /*!< Event Mask on line 2 */
03290 #define  EXTI_EMR_MR3                        ((uint32_t)0x00000008)        /*!< Event Mask on line 3 */
03291 #define  EXTI_EMR_MR4                        ((uint32_t)0x00000010)        /*!< Event Mask on line 4 */
03292 #define  EXTI_EMR_MR5                        ((uint32_t)0x00000020)        /*!< Event Mask on line 5 */
03293 #define  EXTI_EMR_MR6                        ((uint32_t)0x00000040)        /*!< Event Mask on line 6 */
03294 #define  EXTI_EMR_MR7                        ((uint32_t)0x00000080)        /*!< Event Mask on line 7 */
03295 #define  EXTI_EMR_MR8                        ((uint32_t)0x00000100)        /*!< Event Mask on line 8 */
03296 #define  EXTI_EMR_MR9                        ((uint32_t)0x00000200)        /*!< Event Mask on line 9 */
03297 #define  EXTI_EMR_MR10                       ((uint32_t)0x00000400)        /*!< Event Mask on line 10 */
03298 #define  EXTI_EMR_MR11                       ((uint32_t)0x00000800)        /*!< Event Mask on line 11 */
03299 #define  EXTI_EMR_MR12                       ((uint32_t)0x00001000)        /*!< Event Mask on line 12 */
03300 #define  EXTI_EMR_MR13                       ((uint32_t)0x00002000)        /*!< Event Mask on line 13 */
03301 #define  EXTI_EMR_MR14                       ((uint32_t)0x00004000)        /*!< Event Mask on line 14 */
03302 #define  EXTI_EMR_MR15                       ((uint32_t)0x00008000)        /*!< Event Mask on line 15 */
03303 #define  EXTI_EMR_MR16                       ((uint32_t)0x00010000)        /*!< Event Mask on line 16 */
03304 #define  EXTI_EMR_MR17                       ((uint32_t)0x00020000)        /*!< Event Mask on line 17 */
03305 #define  EXTI_EMR_MR18                       ((uint32_t)0x00040000)        /*!< Event Mask on line 18 */
03306 #define  EXTI_EMR_MR19                       ((uint32_t)0x00080000)        /*!< Event Mask on line 19 */
03307
03308 /******************  Bit definition for EXTI_RTSR register  *******************/
03309 #define  EXTI_RTSR_TR0                       ((uint32_t)0x00000001)        /*!< Rising trigger event configuration bit of line 0 */
03310 #define  EXTI_RTSR_TR1                       ((uint32_t)0x00000002)        /*!< Rising trigger event configuration bit of line 1 */
03311 #define  EXTI_RTSR_TR2                       ((uint32_t)0x00000004)        /*!< Rising trigger event configuration bit of line 2 */
03312 #define  EXTI_RTSR_TR3                       ((uint32_t)0x00000008)        /*!< Rising trigger event configuration bit of line 3 */
03313 #define  EXTI_RTSR_TR4                       ((uint32_t)0x00000010)        /*!< Rising trigger event configuration bit of line 4 */
03314 #define  EXTI_RTSR_TR5                       ((uint32_t)0x00000020)        /*!< Rising trigger event configuration bit of line 5 */
03315 #define  EXTI_RTSR_TR6                       ((uint32_t)0x00000040)        /*!< Rising trigger event configuration bit of line 6 */
03316 #define  EXTI_RTSR_TR7                       ((uint32_t)0x00000080)        /*!< Rising trigger event configuration bit of line 7 */
03317 #define  EXTI_RTSR_TR8                       ((uint32_t)0x00000100)        /*!< Rising trigger event configuration bit of line 8 */
03318 #define  EXTI_RTSR_TR9                       ((uint32_t)0x00000200)        /*!< Rising trigger event configuration bit of line 9 */
03319 #define  EXTI_RTSR_TR10                      ((uint32_t)0x00000400)        /*!< Rising trigger event configuration bit of line 10 */
03320 #define  EXTI_RTSR_TR11                      ((uint32_t)0x00000800)        /*!< Rising trigger event configuration bit of line 11 */
03321 #define  EXTI_RTSR_TR12                      ((uint32_t)0x00001000)        /*!< Rising trigger event configuration bit of line 12 */
03322 #define  EXTI_RTSR_TR13                      ((uint32_t)0x00002000)        /*!< Rising trigger event configuration bit of line 13 */
03323 #define  EXTI_RTSR_TR14                      ((uint32_t)0x00004000)        /*!< Rising trigger event configuration bit of line 14 */
03324 #define  EXTI_RTSR_TR15                      ((uint32_t)0x00008000)        /*!< Rising trigger event configuration bit of line 15 */
03325 #define  EXTI_RTSR_TR16                      ((uint32_t)0x00010000)        /*!< Rising trigger event configuration bit of line 16 */
03326 #define  EXTI_RTSR_TR17                      ((uint32_t)0x00020000)        /*!< Rising trigger event configuration bit of line 17 */
03327 #define  EXTI_RTSR_TR18                      ((uint32_t)0x00040000)        /*!< Rising trigger event configuration bit of line 18 */
03328 #define  EXTI_RTSR_TR19                      ((uint32_t)0x00080000)        /*!< Rising trigger event configuration bit of line 19 */
03329
03330 /******************  Bit definition for EXTI_FTSR register  *******************/
03331 #define  EXTI_FTSR_TR0                       ((uint32_t)0x00000001)        /*!< Falling trigger event configuration bit of line 0 */
03332 #define  EXTI_FTSR_TR1                       ((uint32_t)0x00000002)        /*!< Falling trigger event configuration bit of line 1 */
03333 #define  EXTI_FTSR_TR2                       ((uint32_t)0x00000004)        /*!< Falling trigger event configuration bit of line 2 */
03334 #define  EXTI_FTSR_TR3                       ((uint32_t)0x00000008)        /*!< Falling trigger event configuration bit of line 3 */
03335 #define  EXTI_FTSR_TR4                       ((uint32_t)0x00000010)        /*!< Falling trigger event configuration bit of line 4 */
03336 #define  EXTI_FTSR_TR5                       ((uint32_t)0x00000020)        /*!< Falling trigger event configuration bit of line 5 */
03337 #define  EXTI_FTSR_TR6                       ((uint32_t)0x00000040)        /*!< Falling trigger event configuration bit of line 6 */
03338 #define  EXTI_FTSR_TR7                       ((uint32_t)0x00000080)        /*!< Falling trigger event configuration bit of line 7 */
03339 #define  EXTI_FTSR_TR8                       ((uint32_t)0x00000100)        /*!< Falling trigger event configuration bit of line 8 */
03340 #define  EXTI_FTSR_TR9                       ((uint32_t)0x00000200)        /*!< Falling trigger event configuration bit of line 9 */
03341 #define  EXTI_FTSR_TR10                      ((uint32_t)0x00000400)        /*!< Falling trigger event configuration bit of line 10 */
03342 #define  EXTI_FTSR_TR11                      ((uint32_t)0x00000800)        /*!< Falling trigger event configuration bit of line 11 */
03343 #define  EXTI_FTSR_TR12                      ((uint32_t)0x00001000)        /*!< Falling trigger event configuration bit of line 12 */
03344 #define  EXTI_FTSR_TR13                      ((uint32_t)0x00002000)        /*!< Falling trigger event configuration bit of line 13 */
03345 #define  EXTI_FTSR_TR14                      ((uint32_t)0x00004000)        /*!< Falling trigger event configuration bit of line 14 */
03346 #define  EXTI_FTSR_TR15                      ((uint32_t)0x00008000)        /*!< Falling trigger event configuration bit of line 15 */
03347 #define  EXTI_FTSR_TR16                      ((uint32_t)0x00010000)        /*!< Falling trigger event configuration bit of line 16 */
03348 #define  EXTI_FTSR_TR17                      ((uint32_t)0x00020000)        /*!< Falling trigger event configuration bit of line 17 */
03349 #define  EXTI_FTSR_TR18                      ((uint32_t)0x00040000)        /*!< Falling trigger event configuration bit of line 18 */
03350 #define  EXTI_FTSR_TR19                      ((uint32_t)0x00080000)        /*!< Falling trigger event configuration bit of line 19 */
03351
03352 /******************  Bit definition for EXTI_SWIER register  ******************/
03353 #define  EXTI_SWIER_SWIER0                   ((uint32_t)0x00000001)        /*!< Software Interrupt on line 0 */
03354 #define  EXTI_SWIER_SWIER1                   ((uint32_t)0x00000002)        /*!< Software Interrupt on line 1 */
03355 #define  EXTI_SWIER_SWIER2                   ((uint32_t)0x00000004)        /*!< Software Interrupt on line 2 */
03356 #define  EXTI_SWIER_SWIER3                   ((uint32_t)0x00000008)        /*!< Software Interrupt on line 3 */
03357 #define  EXTI_SWIER_SWIER4                   ((uint32_t)0x00000010)        /*!< Software Interrupt on line 4 */
03358 #define  EXTI_SWIER_SWIER5                   ((uint32_t)0x00000020)        /*!< Software Interrupt on line 5 */
03359 #define  EXTI_SWIER_SWIER6                   ((uint32_t)0x00000040)        /*!< Software Interrupt on line 6 */
03360 #define  EXTI_SWIER_SWIER7                   ((uint32_t)0x00000080)        /*!< Software Interrupt on line 7 */
03361 #define  EXTI_SWIER_SWIER8                   ((uint32_t)0x00000100)        /*!< Software Interrupt on line 8 */
03362 #define  EXTI_SWIER_SWIER9                   ((uint32_t)0x00000200)        /*!< Software Interrupt on line 9 */
03363 #define  EXTI_SWIER_SWIER10                  ((uint32_t)0x00000400)        /*!< Software Interrupt on line 10 */
03364 #define  EXTI_SWIER_SWIER11                  ((uint32_t)0x00000800)        /*!< Software Interrupt on line 11 */
03365 #define  EXTI_SWIER_SWIER12                  ((uint32_t)0x00001000)        /*!< Software Interrupt on line 12 */
03366 #define  EXTI_SWIER_SWIER13                  ((uint32_t)0x00002000)        /*!< Software Interrupt on line 13 */
03367 #define  EXTI_SWIER_SWIER14                  ((uint32_t)0x00004000)        /*!< Software Interrupt on line 14 */
03368 #define  EXTI_SWIER_SWIER15                  ((uint32_t)0x00008000)        /*!< Software Interrupt on line 15 */
03369 #define  EXTI_SWIER_SWIER16                  ((uint32_t)0x00010000)        /*!< Software Interrupt on line 16 */
03370 #define  EXTI_SWIER_SWIER17                  ((uint32_t)0x00020000)        /*!< Software Interrupt on line 17 */
03371 #define  EXTI_SWIER_SWIER18                  ((uint32_t)0x00040000)        /*!< Software Interrupt on line 18 */
03372 #define  EXTI_SWIER_SWIER19                  ((uint32_t)0x00080000)        /*!< Software Interrupt on line 19 */
03373
03374 /*******************  Bit definition for EXTI_PR register  ********************/
03375 #define  EXTI_PR_PR0                         ((uint32_t)0x00000001)        /*!< Pending bit for line 0 */
03376 #define  EXTI_PR_PR1                         ((uint32_t)0x00000002)        /*!< Pending bit for line 1 */
03377 #define  EXTI_PR_PR2                         ((uint32_t)0x00000004)        /*!< Pending bit for line 2 */
03378 #define  EXTI_PR_PR3                         ((uint32_t)0x00000008)        /*!< Pending bit for line 3 */
03379 #define  EXTI_PR_PR4                         ((uint32_t)0x00000010)        /*!< Pending bit for line 4 */
03380 #define  EXTI_PR_PR5                         ((uint32_t)0x00000020)        /*!< Pending bit for line 5 */
03381 #define  EXTI_PR_PR6                         ((uint32_t)0x00000040)        /*!< Pending bit for line 6 */
03382 #define  EXTI_PR_PR7                         ((uint32_t)0x00000080)        /*!< Pending bit for line 7 */
03383 #define  EXTI_PR_PR8                         ((uint32_t)0x00000100)        /*!< Pending bit for line 8 */
03384 #define  EXTI_PR_PR9                         ((uint32_t)0x00000200)        /*!< Pending bit for line 9 */
03385 #define  EXTI_PR_PR10                        ((uint32_t)0x00000400)        /*!< Pending bit for line 10 */
03386 #define  EXTI_PR_PR11                        ((uint32_t)0x00000800)        /*!< Pending bit for line 11 */
03387 #define  EXTI_PR_PR12                        ((uint32_t)0x00001000)        /*!< Pending bit for line 12 */
03388 #define  EXTI_PR_PR13                        ((uint32_t)0x00002000)        /*!< Pending bit for line 13 */
03389 #define  EXTI_PR_PR14                        ((uint32_t)0x00004000)        /*!< Pending bit for line 14 */
03390 #define  EXTI_PR_PR15                        ((uint32_t)0x00008000)        /*!< Pending bit for line 15 */
03391 #define  EXTI_PR_PR16                        ((uint32_t)0x00010000)        /*!< Pending bit for line 16 */
03392 #define  EXTI_PR_PR17                        ((uint32_t)0x00020000)        /*!< Pending bit for line 17 */
03393 #define  EXTI_PR_PR18                        ((uint32_t)0x00040000)        /*!< Pending bit for line 18 */
03394 #define  EXTI_PR_PR19                        ((uint32_t)0x00080000)        /*!< Pending bit for line 19 */
03395
03396 /******************************************************************************/
03397 /*                                                                            */
03398 /*                             DMA Controller                                 */
03399 /*                                                                            */
03400 /******************************************************************************/
03401
03402 /*******************  Bit definition for DMA_ISR register  ********************/
03403 #define  DMA_ISR_GIF1                        ((uint32_t)0x00000001)        /*!< Channel 1 Global interrupt flag */
03404 #define  DMA_ISR_TCIF1                       ((uint32_t)0x00000002)        /*!< Channel 1 Transfer Complete flag */
03405 #define  DMA_ISR_HTIF1                       ((uint32_t)0x00000004)        /*!< Channel 1 Half Transfer flag */
03406 #define  DMA_ISR_TEIF1                       ((uint32_t)0x00000008)        /*!< Channel 1 Transfer Error flag */
03407 #define  DMA_ISR_GIF2                        ((uint32_t)0x00000010)        /*!< Channel 2 Global interrupt flag */
03408 #define  DMA_ISR_TCIF2                       ((uint32_t)0x00000020)        /*!< Channel 2 Transfer Complete flag */
03409 #define  DMA_ISR_HTIF2                       ((uint32_t)0x00000040)        /*!< Channel 2 Half Transfer flag */
03410 #define  DMA_ISR_TEIF2                       ((uint32_t)0x00000080)        /*!< Channel 2 Transfer Error flag */
03411 #define  DMA_ISR_GIF3                        ((uint32_t)0x00000100)        /*!< Channel 3 Global interrupt flag */
03412 #define  DMA_ISR_TCIF3                       ((uint32_t)0x00000200)        /*!< Channel 3 Transfer Complete flag */
03413 #define  DMA_ISR_HTIF3                       ((uint32_t)0x00000400)        /*!< Channel 3 Half Transfer flag */
03414 #define  DMA_ISR_TEIF3                       ((uint32_t)0x00000800)        /*!< Channel 3 Transfer Error flag */
03415 #define  DMA_ISR_GIF4                        ((uint32_t)0x00001000)        /*!< Channel 4 Global interrupt flag */
03416 #define  DMA_ISR_TCIF4                       ((uint32_t)0x00002000)        /*!< Channel 4 Transfer Complete flag */
03417 #define  DMA_ISR_HTIF4                       ((uint32_t)0x00004000)        /*!< Channel 4 Half Transfer flag */
03418 #define  DMA_ISR_TEIF4                       ((uint32_t)0x00008000)        /*!< Channel 4 Transfer Error flag */
03419 #define  DMA_ISR_GIF5                        ((uint32_t)0x00010000)        /*!< Channel 5 Global interrupt flag */
03420 #define  DMA_ISR_TCIF5                       ((uint32_t)0x00020000)        /*!< Channel 5 Transfer Complete flag */
03421 #define  DMA_ISR_HTIF5                       ((uint32_t)0x00040000)        /*!< Channel 5 Half Transfer flag */
03422 #define  DMA_ISR_TEIF5                       ((uint32_t)0x00080000)        /*!< Channel 5 Transfer Error flag */
03423 #define  DMA_ISR_GIF6                        ((uint32_t)0x00100000)        /*!< Channel 6 Global interrupt flag */
03424 #define  DMA_ISR_TCIF6                       ((uint32_t)0x00200000)        /*!< Channel 6 Transfer Complete flag */
03425 #define  DMA_ISR_HTIF6                       ((uint32_t)0x00400000)        /*!< Channel 6 Half Transfer flag */
03426 #define  DMA_ISR_TEIF6                       ((uint32_t)0x00800000)        /*!< Channel 6 Transfer Error flag */
03427 #define  DMA_ISR_GIF7                        ((uint32_t)0x01000000)        /*!< Channel 7 Global interrupt flag */
03428 #define  DMA_ISR_TCIF7                       ((uint32_t)0x02000000)        /*!< Channel 7 Transfer Complete flag */
03429 #define  DMA_ISR_HTIF7                       ((uint32_t)0x04000000)        /*!< Channel 7 Half Transfer flag */
03430 #define  DMA_ISR_TEIF7                       ((uint32_t)0x08000000)        /*!< Channel 7 Transfer Error flag */
03431
03432 /*******************  Bit definition for DMA_IFCR register  *******************/
03433 #define  DMA_IFCR_CGIF1                      ((uint32_t)0x00000001)        /*!< Channel 1 Global interrupt clear */
03434 #define  DMA_IFCR_CTCIF1                     ((uint32_t)0x00000002)        /*!< Channel 1 Transfer Complete clear */
03435 #define  DMA_IFCR_CHTIF1                     ((uint32_t)0x00000004)        /*!< Channel 1 Half Transfer clear */
03436 #define  DMA_IFCR_CTEIF1                     ((uint32_t)0x00000008)        /*!< Channel 1 Transfer Error clear */
03437 #define  DMA_IFCR_CGIF2                      ((uint32_t)0x00000010)        /*!< Channel 2 Global interrupt clear */
03438 #define  DMA_IFCR_CTCIF2                     ((uint32_t)0x00000020)        /*!< Channel 2 Transfer Complete clear */
03439 #define  DMA_IFCR_CHTIF2                     ((uint32_t)0x00000040)        /*!< Channel 2 Half Transfer clear */
03440 #define  DMA_IFCR_CTEIF2                     ((uint32_t)0x00000080)        /*!< Channel 2 Transfer Error clear */
03441 #define  DMA_IFCR_CGIF3                      ((uint32_t)0x00000100)        /*!< Channel 3 Global interrupt clear */
03442 #define  DMA_IFCR_CTCIF3                     ((uint32_t)0x00000200)        /*!< Channel 3 Transfer Complete clear */
03443 #define  DMA_IFCR_CHTIF3                     ((uint32_t)0x00000400)        /*!< Channel 3 Half Transfer clear */
03444 #define  DMA_IFCR_CTEIF3                     ((uint32_t)0x00000800)        /*!< Channel 3 Transfer Error clear */
03445 #define  DMA_IFCR_CGIF4                      ((uint32_t)0x00001000)        /*!< Channel 4 Global interrupt clear */
03446 #define  DMA_IFCR_CTCIF4                     ((uint32_t)0x00002000)        /*!< Channel 4 Transfer Complete clear */
03447 #define  DMA_IFCR_CHTIF4                     ((uint32_t)0x00004000)        /*!< Channel 4 Half Transfer clear */
03448 #define  DMA_IFCR_CTEIF4                     ((uint32_t)0x00008000)        /*!< Channel 4 Transfer Error clear */
03449 #define  DMA_IFCR_CGIF5                      ((uint32_t)0x00010000)        /*!< Channel 5 Global interrupt clear */
03450 #define  DMA_IFCR_CTCIF5                     ((uint32_t)0x00020000)        /*!< Channel 5 Transfer Complete clear */
03451 #define  DMA_IFCR_CHTIF5                     ((uint32_t)0x00040000)        /*!< Channel 5 Half Transfer clear */
03452 #define  DMA_IFCR_CTEIF5                     ((uint32_t)0x00080000)        /*!< Channel 5 Transfer Error clear */
03453 #define  DMA_IFCR_CGIF6                      ((uint32_t)0x00100000)        /*!< Channel 6 Global interrupt clear */
03454 #define  DMA_IFCR_CTCIF6                     ((uint32_t)0x00200000)        /*!< Channel 6 Transfer Complete clear */
03455 #define  DMA_IFCR_CHTIF6                     ((uint32_t)0x00400000)        /*!< Channel 6 Half Transfer clear */
03456 #define  DMA_IFCR_CTEIF6                     ((uint32_t)0x00800000)        /*!< Channel 6 Transfer Error clear */
03457 #define  DMA_IFCR_CGIF7                      ((uint32_t)0x01000000)        /*!< Channel 7 Global interrupt clear */
03458 #define  DMA_IFCR_CTCIF7                     ((uint32_t)0x02000000)        /*!< Channel 7 Transfer Complete clear */
03459 #define  DMA_IFCR_CHTIF7                     ((uint32_t)0x04000000)        /*!< Channel 7 Half Transfer clear */
03460 #define  DMA_IFCR_CTEIF7                     ((uint32_t)0x08000000)        /*!< Channel 7 Transfer Error clear */
03461
03462 /*******************  Bit definition for DMA_CCR1 register  *******************/
03463 #define  DMA_CCR1_EN                         ((uint16_t)0x0001)            /*!< Channel enable*/
03464 #define  DMA_CCR1_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */
03465 #define  DMA_CCR1_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */
03466 #define  DMA_CCR1_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */
03467 #define  DMA_CCR1_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */
03468 #define  DMA_CCR1_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */
03469 #define  DMA_CCR1_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */
03470 #define  DMA_CCR1_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */
03471
03472 #define  DMA_CCR1_PSIZE                      ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */
03473 #define  DMA_CCR1_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */
03474 #define  DMA_CCR1_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */
03475
03476 #define  DMA_CCR1_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */
03477 #define  DMA_CCR1_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */
03478 #define  DMA_CCR1_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */
03479
03480 #define  DMA_CCR1_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits(Channel Priority level) */
03481 #define  DMA_CCR1_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */
03482 #define  DMA_CCR1_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */
03483
03484 #define  DMA_CCR1_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode */
03485
03486 /*******************  Bit definition for DMA_CCR2 register  *******************/
03487 #define  DMA_CCR2_EN                         ((uint16_t)0x0001)            /*!< Channel enable */
03488 #define  DMA_CCR2_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */
03489 #define  DMA_CCR2_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */
03490 #define  DMA_CCR2_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */
03491 #define  DMA_CCR2_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */
03492 #define  DMA_CCR2_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */
03493 #define  DMA_CCR2_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */
03494 #define  DMA_CCR2_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */
03495
03496 #define  DMA_CCR2_PSIZE                      ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */
03497 #define  DMA_CCR2_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */
03498 #define  DMA_CCR2_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */
03499
03500 #define  DMA_CCR2_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */
03501 #define  DMA_CCR2_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */
03502 #define  DMA_CCR2_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */
03503
03504 #define  DMA_CCR2_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits (Channel Priority level) */
03505 #define  DMA_CCR2_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */
03506 #define  DMA_CCR2_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */
03507
03508 #define  DMA_CCR2_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode */
03509
03510 /*******************  Bit definition for DMA_CCR3 register  *******************/
03511 #define  DMA_CCR3_EN                         ((uint16_t)0x0001)            /*!< Channel enable */
03512 #define  DMA_CCR3_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */
03513 #define  DMA_CCR3_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */
03514 #define  DMA_CCR3_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */
03515 #define  DMA_CCR3_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */
03516 #define  DMA_CCR3_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */
03517 #define  DMA_CCR3_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */
03518 #define  DMA_CCR3_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */
03519
03520 #define  DMA_CCR3_PSIZE                      ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */
03521 #define  DMA_CCR3_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */
03522 #define  DMA_CCR3_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */
03523
03524 #define  DMA_CCR3_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */
03525 #define  DMA_CCR3_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */
03526 #define  DMA_CCR3_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */
03527
03528 #define  DMA_CCR3_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits (Channel Priority level) */
03529 #define  DMA_CCR3_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */
03530 #define  DMA_CCR3_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */
03531
03532 #define  DMA_CCR3_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode */
03533
03534 /*!<******************  Bit definition for DMA_CCR4 register  *******************/
03535 #define  DMA_CCR4_EN                         ((uint16_t)0x0001)            /*!< Channel enable */
03536 #define  DMA_CCR4_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */
03537 #define  DMA_CCR4_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */
03538 #define  DMA_CCR4_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */
03539 #define  DMA_CCR4_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */
03540 #define  DMA_CCR4_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */
03541 #define  DMA_CCR4_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */
03542 #define  DMA_CCR4_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */
03543
03544 #define  DMA_CCR4_PSIZE                      ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */
03545 #define  DMA_CCR4_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */
03546 #define  DMA_CCR4_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */
03547
03548 #define  DMA_CCR4_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */
03549 #define  DMA_CCR4_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */
03550 #define  DMA_CCR4_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */
03551
03552 #define  DMA_CCR4_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits (Channel Priority level) */
03553 #define  DMA_CCR4_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */
03554 #define  DMA_CCR4_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */
03555
03556 #define  DMA_CCR4_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode */
03557
03558 /******************  Bit definition for DMA_CCR5 register  *******************/
03559 #define  DMA_CCR5_EN                         ((uint16_t)0x0001)            /*!< Channel enable */
03560 #define  DMA_CCR5_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */
03561 #define  DMA_CCR5_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */
03562 #define  DMA_CCR5_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */
03563 #define  DMA_CCR5_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */
03564 #define  DMA_CCR5_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */
03565 #define  DMA_CCR5_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */
03566 #define  DMA_CCR5_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */
03567
03568 #define  DMA_CCR5_PSIZE                      ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */
03569 #define  DMA_CCR5_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */
03570 #define  DMA_CCR5_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */
03571
03572 #define  DMA_CCR5_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */
03573 #define  DMA_CCR5_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */
03574 #define  DMA_CCR5_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */
03575
03576 #define  DMA_CCR5_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits (Channel Priority level) */
03577 #define  DMA_CCR5_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */
03578 #define  DMA_CCR5_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */
03579
03580 #define  DMA_CCR5_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode enable */
03581
03582 /*******************  Bit definition for DMA_CCR6 register  *******************/
03583 #define  DMA_CCR6_EN                         ((uint16_t)0x0001)            /*!< Channel enable */
03584 #define  DMA_CCR6_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */
03585 #define  DMA_CCR6_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */
03586 #define  DMA_CCR6_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */
03587 #define  DMA_CCR6_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */
03588 #define  DMA_CCR6_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */
03589 #define  DMA_CCR6_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */
03590 #define  DMA_CCR6_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */
03591
03592 #define  DMA_CCR6_PSIZE                      ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */
03593 #define  DMA_CCR6_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */
03594 #define  DMA_CCR6_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */
03595
03596 #define  DMA_CCR6_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */
03597 #define  DMA_CCR6_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */
03598 #define  DMA_CCR6_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */
03599
03600 #define  DMA_CCR6_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits (Channel Priority level) */
03601 #define  DMA_CCR6_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */
03602 #define  DMA_CCR6_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */
03603
03604 #define  DMA_CCR6_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode */
03605
03606 /*******************  Bit definition for DMA_CCR7 register  *******************/
03607 #define  DMA_CCR7_EN                         ((uint16_t)0x0001)            /*!< Channel enable */
03608 #define  DMA_CCR7_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */
03609 #define  DMA_CCR7_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */
03610 #define  DMA_CCR7_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */
03611 #define  DMA_CCR7_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */
03612 #define  DMA_CCR7_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */
03613 #define  DMA_CCR7_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */
03614 #define  DMA_CCR7_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */
03615
03616 #define  DMA_CCR7_PSIZE            ,         ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */
03617 #define  DMA_CCR7_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */
03618 #define  DMA_CCR7_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */
03619
03620 #define  DMA_CCR7_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */
03621 #define  DMA_CCR7_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */
03622 #define  DMA_CCR7_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */
03623
03624 #define  DMA_CCR7_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits (Channel Priority level) */
03625 #define  DMA_CCR7_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */
03626 #define  DMA_CCR7_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */
03627
03628 #define  DMA_CCR7_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode enable */
03629
03630 /******************  Bit definition for DMA_CNDTR1 register  ******************/
03631 #define  DMA_CNDTR1_NDT                      ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */
03632
03633 /******************  Bit definition for DMA_CNDTR2 register  ******************/
03634 #define  DMA_CNDTR2_NDT                      ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */
03635
03636 /******************  Bit definition for DMA_CNDTR3 register  ******************/
03637 #define  DMA_CNDTR3_NDT                      ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */
03638
03639 /******************  Bit definition for DMA_CNDTR4 register  ******************/
03640 #define  DMA_CNDTR4_NDT                      ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */
03641
03642 /******************  Bit definition for DMA_CNDTR5 register  ******************/
03643 #define  DMA_CNDTR5_NDT                      ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */
03644
03645 /******************  Bit definition for DMA_CNDTR6 register  ******************/
03646 #define  DMA_CNDTR6_NDT                      ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */
03647
03648 /******************  Bit definition for DMA_CNDTR7 register  ******************/
03649 #define  DMA_CNDTR7_NDT                      ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */
03650
03651 /******************  Bit definition for DMA_CPAR1 register  *******************/
03652 #define  DMA_CPAR1_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
03653
03654 /******************  Bit definition for DMA_CPAR2 register  *******************/
03655 #define  DMA_CPAR2_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
03656
03657 /******************  Bit definition for DMA_CPAR3 register  *******************/
03658 #define  DMA_CPAR3_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
03659
03660
03661 /******************  Bit definition for DMA_CPAR4 register  *******************/
03662 #define  DMA_CPAR4_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
03663
03664 /******************  Bit definition for DMA_CPAR5 register  *******************/
03665 #define  DMA_CPAR5_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
03666
03667 /******************  Bit definition for DMA_CPAR6 register  *******************/
03668 #define  DMA_CPAR6_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
03669
03670
03671 /******************  Bit definition for DMA_CPAR7 register  *******************/
03672 #define  DMA_CPAR7_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
03673
03674 /******************  Bit definition for DMA_CMAR1 register  *******************/
03675 #define  DMA_CMAR1_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
03676
03677 /******************  Bit definition for DMA_CMAR2 register  *******************/
03678 #define  DMA_CMAR2_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
03679
03680 /******************  Bit definition for DMA_CMAR3 register  *******************/
03681 #define  DMA_CMAR3_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
03682
03683
03684 /******************  Bit definition for DMA_CMAR4 register  *******************/
03685 #define  DMA_CMAR4_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
03686
03687 /******************  Bit definition for DMA_CMAR5 register  *******************/
03688 #define  DMA_CMAR5_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
03689
03690 /******************  Bit definition for DMA_CMAR6 register  *******************/
03691 #define  DMA_CMAR6_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
03692
03693 /******************  Bit definition for DMA_CMAR7 register  *******************/
03694 #define  DMA_CMAR7_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
03695
03696 /******************************************************************************/
03697 /*                                                                            */
03698 /*                        Analog to Digital Converter                         */
03699 /*                                                                            */
03700 /******************************************************************************/
03701
03702 /********************  Bit definition for ADC_SR register  ********************/
03703 #define  ADC_SR_AWD                          ((uint8_t)0x01)               /*!< Analog watchdog flag */
03704 #define  ADC_SR_EOC                          ((uint8_t)0x02)               /*!< End of conversion */
03705 #define  ADC_SR_JEOC                         ((uint8_t)0x04)               /*!< Injected channel end of conversion */
03706 #define  ADC_SR_JSTRT                        ((uint8_t)0x08)               /*!< Injected channel Start flag */
03707 #define  ADC_SR_STRT                         ((uint8_t)0x10)               /*!< Regular channel Start flag */
03708
03709 /*******************  Bit definition for ADC_CR1 register  ********************/
03710 #define  ADC_CR1_AWDCH                       ((uint32_t)0x0000001F)        /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
03711 #define  ADC_CR1_AWDCH_0                     ((uint32_t)0x00000001)        /*!< Bit 0 */
03712 #define  ADC_CR1_AWDCH_1                     ((uint32_t)0x00000002)        /*!< Bit 1 */
03713 #define  ADC_CR1_AWDCH_2                     ((uint32_t)0x00000004)        /*!< Bit 2 */
03714 #define  ADC_CR1_AWDCH_3                     ((uint32_t)0x00000008)        /*!< Bit 3 */
03715 #define  ADC_CR1_AWDCH_4                     ((uint32_t)0x00000010)        /*!< Bit 4 */
03716
03717 #define  ADC_CR1_EOCIE                       ((uint32_t)0x00000020)        /*!< Interrupt enable for EOC */
03718 #define  ADC_CR1_AWDIE                       ((uint32_t)0x00000040)        /*!< Analog Watchdog interrupt enable */
03719 #define  ADC_CR1_JEOCIE                      ((uint32_t)0x00000080)        /*!< Interrupt enable for injected channels */
03720 #define  ADC_CR1_SCAN                        ((uint32_t)0x00000100)        /*!< Scan mode */
03721 #define  ADC_CR1_AWDSGL                      ((uint32_t)0x00000200)        /*!< Enable the watchdog on a single channel in scan mode */
03722 #define  ADC_CR1_JAUTO                       ((uint32_t)0x00000400)        /*!< Automatic injected group conversion */
03723 #define  ADC_CR1_DISCEN                      ((uint32_t)0x00000800)        /*!< Discontinuous mode on regular channels */
03724 #define  ADC_CR1_JDISCEN                     ((uint32_t)0x00001000)        /*!< Discontinuous mode on injected channels */
03725
03726 #define  ADC_CR1_DISCNUM                     ((uint32_t)0x0000E000)        /*!< DISCNUM[2:0] bits (Discontinuous mode channel count) */
03727 #define  ADC_CR1_DISCNUM_0                   ((uint32_t)0x00002000)        /*!< Bit 0 */
03728 #define  ADC_CR1_DISCNUM_1                   ((uint32_t)0x00004000)        /*!< Bit 1 */
03729 #define  ADC_CR1_DISCNUM_2                   ((uint32_t)0x00008000)        /*!< Bit 2 */
03730
03731 #define  ADC_CR1_DUALMOD                     ((uint32_t)0x000F0000)        /*!< DUALMOD[3:0] bits (Dual mode selection) */
03732 #define  ADC_CR1_DUALMOD_0                   ((uint32_t)0x00010000)        /*!< Bit 0 */
03733 #define  ADC_CR1_DUALMOD_1                   ((uint32_t)0x00020000)        /*!< Bit 1 */
03734 #define  ADC_CR1_DUALMOD_2                   ((uint32_t)0x00040000)        /*!< Bit 2 */
03735 #define  ADC_CR1_DUALMOD_3                   ((uint32_t)0x00080000)        /*!< Bit 3 */
03736
03737 #define  ADC_CR1_JAWDEN                      ((uint32_t)0x00400000)        /*!< Analog watchdog enable on injected channels */
03738 #define  ADC_CR1_AWDEN                       ((uint32_t)0x00800000)        /*!< Analog watchdog enable on regular channels */
03739
03740
03741 /*******************  Bit definition for ADC_CR2 register  ********************/
03742 #define  ADC_CR2_ADON                        ((uint32_t)0x00000001)        /*!< A/D Converter ON / OFF */
03743 #define  ADC_CR2_CONT                        ((uint32_t)0x00000002)        /*!< Continuous Conversion */
03744 #define  ADC_CR2_CAL                         ((uint32_t)0x00000004)        /*!< A/D Calibration */
03745 #define  ADC_CR2_RSTCAL                      ((uint32_t)0x00000008)        /*!< Reset Calibration */
03746 #define  ADC_CR2_DMA                         ((uint32_t)0x00000100)        /*!< Direct Memory access mode */
03747 #define  ADC_CR2_ALIGN                       ((uint32_t)0x00000800)        /*!< Data Alignment */
03748
03749 #define  ADC_CR2_JEXTSEL                     ((uint32_t)0x00007000)        /*!< JEXTSEL[2:0] bits (External event select for injected group) */
03750 #define  ADC_CR2_JEXTSEL_0                   ((uint32_t)0x00001000)        /*!< Bit 0 */
03751 #define  ADC_CR2_JEXTSEL_1                   ((uint32_t)0x00002000)        /*!< Bit 1 */
03752 #define  ADC_CR2_JEXTSEL_2                   ((uint32_t)0x00004000)        /*!< Bit 2 */
03753
03754 #define  ADC_CR2_JEXTTRIG                    ((uint32_t)0x00008000)        /*!< External Trigger Conversion mode for injected channels */
03755
03756 #define  ADC_CR2_EXTSEL                      ((uint32_t)0x000E0000)        /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
03757 #define  ADC_CR2_EXTSEL_0                    ((uint32_t)0x00020000)        /*!< Bit 0 */
03758 #define  ADC_CR2_EXTSEL_1                    ((uint32_t)0x00040000)        /*!< Bit 1 */
03759 #define  ADC_CR2_EXTSEL_2                    ((uint32_t)0x00080000)        /*!< Bit 2 */
03760
03761 #define  ADC_CR2_EXTTRIG                     ((uint32_t)0x00100000)        /*!< External Trigger Conversion mode for regular channels */
03762 #define  ADC_CR2_JSWSTART                    ((uint32_t)0x00200000)        /*!< Start Conversion of injected channels */
03763 #define  ADC_CR2_SWSTART                     ((uint32_t)0x00400000)        /*!< Start Conversion of regular channels */
03764 #define  ADC_CR2_TSVREFE                     ((uint32_t)0x00800000)        /*!< Temperature Sensor and VREFINT Enable */
03765
03766 /******************  Bit definition for ADC_SMPR1 register  *******************/
03767 #define  ADC_SMPR1_SMP10                     ((uint32_t)0x00000007)        /*!< SMP10[2:0] bits (Channel 10 Sample time selection) */
03768 #define  ADC_SMPR1_SMP10_0                   ((uint32_t)0x00000001)        /*!< Bit 0 */
03769 #define  ADC_SMPR1_SMP10_1                   ((uint32_t)0x00000002)        /*!< Bit 1 */
03770 #define  ADC_SMPR1_SMP10_2                   ((uint32_t)0x00000004)        /*!< Bit 2 */
03771
03772 #define  ADC_SMPR1_SMP11                     ((uint32_t)0x00000038)        /*!< SMP11[2:0] bits (Channel 11 Sample time selection) */
03773 #define  ADC_SMPR1_SMP11_0                   ((uint32_t)0x00000008)        /*!< Bit 0 */
03774 #define  ADC_SMPR1_SMP11_1                   ((uint32_t)0x00000010)        /*!< Bit 1 */
03775 #define  ADC_SMPR1_SMP11_2                   ((uint32_t)0x00000020)        /*!< Bit 2 */
03776
03777 #define  ADC_SMPR1_SMP12                     ((uint32_t)0x000001C0)        /*!< SMP12[2:0] bits (Channel 12 Sample time selection) */
03778 #define  ADC_SMPR1_SMP12_0                   ((uint32_t)0x00000040)        /*!< Bit 0 */
03779 #define  ADC_SMPR1_SMP12_1                   ((uint32_t)0x00000080)        /*!< Bit 1 */
03780 #define  ADC_SMPR1_SMP12_2                   ((uint32_t)0x00000100)        /*!< Bit 2 */
03781
03782 #define  ADC_SMPR1_SMP13                     ((uint32_t)0x00000E00)        /*!< SMP13[2:0] bits (Channel 13 Sample time selection) */
03783 #define  ADC_SMPR1_SMP13_0                   ((uint32_t)0x00000200)        /*!< Bit 0 */
03784 #define  ADC_SMPR1_SMP13_1                   ((uint32_t)0x00000400)        /*!< Bit 1 */
03785 #define  ADC_SMPR1_SMP13_2                   ((uint32_t)0x00000800)        /*!< Bit 2 */
03786
03787 #define  ADC_SMPR1_SMP14                     ((uint32_t)0x00007000)        /*!< SMP14[2:0] bits (Channel 14 Sample time selection) */
03788 #define  ADC_SMPR1_SMP14_0                   ((uint32_t)0x00001000)        /*!< Bit 0 */
03789 #define  ADC_SMPR1_SMP14_1                   ((uint32_t)0x00002000)        /*!< Bit 1 */
03790 #define  ADC_SMPR1_SMP14_2                   ((uint32_t)0x00004000)        /*!< Bit 2 */
03791
03792 #define  ADC_SMPR1_SMP15                     ((uint32_t)0x00038000)        /*!< SMP15[2:0] bits (Channel 15 Sample time selection) */
03793 #define  ADC_SMPR1_SMP15_0                   ((uint32_t)0x00008000)        /*!< Bit 0 */
03794 #define  ADC_SMPR1_SMP15_1                   ((uint32_t)0x00010000)        /*!< Bit 1 */
03795 #define  ADC_SMPR1_SMP15_2                   ((uint32_t)0x00020000)        /*!< Bit 2 */
03796
03797 #define  ADC_SMPR1_SMP16                     ((uint32_t)0x001C0000)        /*!< SMP16[2:0] bits (Channel 16 Sample time selection) */
03798 #define  ADC_SMPR1_SMP16_0                   ((uint32_t)0x00040000)        /*!< Bit 0 */
03799 #define  ADC_SMPR1_SMP16_1                   ((uint32_t)0x00080000)        /*!< Bit 1 */
03800 #define  ADC_SMPR1_SMP16_2                   ((uint32_t)0x00100000)        /*!< Bit 2 */
03801
03802 #define  ADC_SMPR1_SMP17                     ((uint32_t)0x00E00000)        /*!< SMP17[2:0] bits (Channel 17 Sample time selection) */
03803 #define  ADC_SMPR1_SMP17_0                   ((uint32_t)0x00200000)        /*!< Bit 0 */
03804 #define  ADC_SMPR1_SMP17_1                   ((uint32_t)0x00400000)        /*!< Bit 1 */
03805 #define  ADC_SMPR1_SMP17_2                   ((uint32_t)0x00800000)        /*!< Bit 2 */
03806
03807 /******************  Bit definition for ADC_SMPR2 register  *******************/
03808 #define  ADC_SMPR2_SMP0                      ((uint32_t)0x00000007)        /*!< SMP0[2:0] bits (Channel 0 Sample time selection) */
03809 #define  ADC_SMPR2_SMP0_0                    ((uint32_t)0x00000001)        /*!< Bit 0 */
03810 #define  ADC_SMPR2_SMP0_1                    ((uint32_t)0x00000002)        /*!< Bit 1 */
03811 #define  ADC_SMPR2_SMP0_2                    ((uint32_t)0x00000004)        /*!< Bit 2 */
03812
03813 #define  ADC_SMPR2_SMP1                      ((uint32_t)0x00000038)        /*!< SMP1[2:0] bits (Channel 1 Sample time selection) */
03814 #define  ADC_SMPR2_SMP1_0                    ((uint32_t)0x00000008)        /*!< Bit 0 */
03815 #define  ADC_SMPR2_SMP1_1                    ((uint32_t)0x00000010)        /*!< Bit 1 */
03816 #define  ADC_SMPR2_SMP1_2                    ((uint32_t)0x00000020)        /*!< Bit 2 */
03817
03818 #define  ADC_SMPR2_SMP2                      ((uint32_t)0x000001C0)        /*!< SMP2[2:0] bits (Channel 2 Sample time selection) */
03819 #define  ADC_SMPR2_SMP2_0                    ((uint32_t)0x00000040)        /*!< Bit 0 */
03820 #define  ADC_SMPR2_SMP2_1                    ((uint32_t)0x00000080)        /*!< Bit 1 */
03821 #define  ADC_SMPR2_SMP2_2                    ((uint32_t)0x00000100)        /*!< Bit 2 */
03822
03823 #define  ADC_SMPR2_SMP3                      ((uint32_t)0x00000E00)        /*!< SMP3[2:0] bits (Channel 3 Sample time selection) */
03824 #define  ADC_SMPR2_SMP3_0                    ((uint32_t)0x00000200)        /*!< Bit 0 */
03825 #define  ADC_SMPR2_SMP3_1                    ((uint32_t)0x00000400)        /*!< Bit 1 */
03826 #define  ADC_SMPR2_SMP3_2                    ((uint32_t)0x00000800)        /*!< Bit 2 */
03827
03828 #define  ADC_SMPR2_SMP4                      ((uint32_t)0x00007000)        /*!< SMP4[2:0] bits (Channel 4 Sample time selection) */
03829 #define  ADC_SMPR2_SMP4_0                    ((uint32_t)0x00001000)        /*!< Bit 0 */
03830 #define  ADC_SMPR2_SMP4_1                    ((uint32_t)0x00002000)        /*!< Bit 1 */
03831 #define  ADC_SMPR2_SMP4_2                    ((uint32_t)0x00004000)        /*!< Bit 2 */
03832
03833 #define  ADC_SMPR2_SMP5                      ((uint32_t)0x00038000)        /*!< SMP5[2:0] bits (Channel 5 Sample time selection) */
03834 #define  ADC_SMPR2_SMP5_0                    ((uint32_t)0x00008000)        /*!< Bit 0 */
03835 #define  ADC_SMPR2_SMP5_1                    ((uint32_t)0x00010000)        /*!< Bit 1 */
03836 #define  ADC_SMPR2_SMP5_2                    ((uint32_t)0x00020000)        /*!< Bit 2 */
03837
03838 #define  ADC_SMPR2_SMP6                      ((uint32_t)0x001C0000)        /*!< SMP6[2:0] bits (Channel 6 Sample time selection) */
03839 #define  ADC_SMPR2_SMP6_0                    ((uint32_t)0x00040000)        /*!< Bit 0 */
03840 #define  ADC_SMPR2_SMP6_1                    ((uint32_t)0x00080000)        /*!< Bit 1 */
03841 #define  ADC_SMPR2_SMP6_2                    ((uint32_t)0x00100000)        /*!< Bit 2 */
03842
03843 #define  ADC_SMPR2_SMP7                      ((uint32_t)0x00E00000)        /*!< SMP7[2:0] bits (Channel 7 Sample time selection) */
03844 #define  ADC_SMPR2_SMP7_0                    ((uint32_t)0x00200000)        /*!< Bit 0 */
03845 #define  ADC_SMPR2_SMP7_1                    ((uint32_t)0x00400000)        /*!< Bit 1 */
03846 #define  ADC_SMPR2_SMP7_2                    ((uint32_t)0x00800000)        /*!< Bit 2 */
03847
03848 #define  ADC_SMPR2_SMP8                      ((uint32_t)0x07000000)        /*!< SMP8[2:0] bits (Channel 8 Sample time selection) */
03849 #define  ADC_SMPR2_SMP8_0                    ((uint32_t)0x01000000)        /*!< Bit 0 */
03850 #define  ADC_SMPR2_SMP8_1                    ((uint32_t)0x02000000)        /*!< Bit 1 */
03851 #define  ADC_SMPR2_SMP8_2                    ((uint32_t)0x04000000)        /*!< Bit 2 */
03852
03853 #define  ADC_SMPR2_SMP9                      ((uint32_t)0x38000000)        /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */
03854 #define  ADC_SMPR2_SMP9_0                    ((uint32_t)0x08000000)        /*!< Bit 0 */
03855 #define  ADC_SMPR2_SMP9_1                    ((uint32_t)0x10000000)        /*!< Bit 1 */
03856 #define  ADC_SMPR2_SMP9_2                    ((uint32_t)0x20000000)        /*!< Bit 2 */
03857
03858 /******************  Bit definition for ADC_JOFR1 register  *******************/
03859 #define  ADC_JOFR1_JOFFSET1                  ((uint16_t)0x0FFF)            /*!< Data offset for injected channel 1 */
03860
03861 /******************  Bit definition for ADC_JOFR2 register  *******************/
03862 #define  ADC_JOFR2_JOFFSET2                  ((uint16_t)0x0FFF)            /*!< Data offset for injected channel 2 */
03863
03864 /******************  Bit definition for ADC_JOFR3 register  *******************/
03865 #define  ADC_JOFR3_JOFFSET3                  ((uint16_t)0x0FFF)            /*!< Data offset for injected channel 3 */
03866
03867 /******************  Bit definition for ADC_JOFR4 register  *******************/
03868 #define  ADC_JOFR4_JOFFSET4                  ((uint16_t)0x0FFF)            /*!< Data offset for injected channel 4 */
03869
03870 /*******************  Bit definition for ADC_HTR register  ********************/
03871 #define  ADC_HTR_HT                          ((uint16_t)0x0FFF)            /*!< Analog watchdog high threshold */
03872
03873 /*******************  Bit definition for ADC_LTR register  ********************/
03874 #define  ADC_LTR_LT                          ((uint16_t)0x0FFF)            /*!< Analog watchdog low threshold */
03875
03876 /*******************  Bit definition for ADC_SQR1 register  *******************/
03877 #define  ADC_SQR1_SQ13                       ((uint32_t)0x0000001F)        /*!< SQ13[4:0] bits (13th conversion in regular sequence) */
03878 #define  ADC_SQR1_SQ13_0                     ((uint32_t)0x00000001)        /*!< Bit 0 */
03879 #define  ADC_SQR1_SQ13_1                     ((uint32_t)0x00000002)        /*!< Bit 1 */
03880 #define  ADC_SQR1_SQ13_2                     ((uint32_t)0x00000004)        /*!< Bit 2 */
03881 #define  ADC_SQR1_SQ13_3                     ((uint32_t)0x00000008)        /*!< Bit 3 */
03882 #define  ADC_SQR1_SQ13_4                     ((uint32_t)0x00000010)        /*!< Bit 4 */
03883
03884 #define  ADC_SQR1_SQ14                       ((uint32_t)0x000003E0)        /*!< SQ14[4:0] bits (14th conversion in regular sequence) */
03885 #define  ADC_SQR1_SQ14_0                     ((uint32_t)0x00000020)        /*!< Bit 0 */
03886 #define  ADC_SQR1_SQ14_1                     ((uint32_t)0x00000040)        /*!< Bit 1 */
03887 #define  ADC_SQR1_SQ14_2                     ((uint32_t)0x00000080)        /*!< Bit 2 */
03888 #define  ADC_SQR1_SQ14_3                     ((uint32_t)0x00000100)        /*!< Bit 3 */
03889 #define  ADC_SQR1_SQ14_4                     ((uint32_t)0x00000200)        /*!< Bit 4 */
03890
03891 #define  ADC_SQR1_SQ15                       ((uint32_t)0x00007C00)        /*!< SQ15[4:0] bits (15th conversion in regular sequence) */
03892 #define  ADC_SQR1_SQ15_0                     ((uint32_t)0x00000400)        /*!< Bit 0 */
03893 #define  ADC_SQR1_SQ15_1                     ((uint32_t)0x00000800)        /*!< Bit 1 */
03894 #define  ADC_SQR1_SQ15_2                     ((uint32_t)0x00001000)        /*!< Bit 2 */
03895 #define  ADC_SQR1_SQ15_3                     ((uint32_t)0x00002000)        /*!< Bit 3 */
03896 #define  ADC_SQR1_SQ15_4                     ((uint32_t)0x00004000)        /*!< Bit 4 */
03897
03898 #define  ADC_SQR1_SQ16                       ((uint32_t)0x000F8000)        /*!< SQ16[4:0] bits (16th conversion in regular sequence) */
03899 #define  ADC_SQR1_SQ16_0                     ((uint32_t)0x00008000)        /*!< Bit 0 */
03900 #define  ADC_SQR1_SQ16_1                     ((uint32_t)0x00010000)        /*!< Bit 1 */
03901 #define  ADC_SQR1_SQ16_2                     ((uint32_t)0x00020000)        /*!< Bit 2 */
03902 #define  ADC_SQR1_SQ16_3                     ((uint32_t)0x00040000)        /*!< Bit 3 */
03903 #define  ADC_SQR1_SQ16_4                     ((uint32_t)0x00080000)        /*!< Bit 4 */
03904
03905 #define  ADC_SQR1_L                          ((uint32_t)0x00F00000)        /*!< L[3:0] bits (Regular channel sequence length) */
03906 #define  ADC_SQR1_L_0                        ((uint32_t)0x00100000)        /*!< Bit 0 */
03907 #define  ADC_SQR1_L_1                        ((uint32_t)0x00200000)        /*!< Bit 1 */
03908 #define  ADC_SQR1_L_2                        ((uint32_t)0x00400000)        /*!< Bit 2 */
03909 #define  ADC_SQR1_L_3                        ((uint32_t)0x00800000)        /*!< Bit 3 */
03910
03911 /*******************  Bit definition for ADC_SQR2 register  *******************/
03912 #define  ADC_SQR2_SQ7                        ((uint32_t)0x0000001F)        /*!< SQ7[4:0] bits (7th conversion in regular sequence) */
03913 #define  ADC_SQR2_SQ7_0                      ((uint32_t)0x00000001)        /*!< Bit 0 */
03914 #define  ADC_SQR2_SQ7_1                      ((uint32_t)0x00000002)        /*!< Bit 1 */
03915 #define  ADC_SQR2_SQ7_2                      ((uint32_t)0x00000004)        /*!< Bit 2 */
03916 #define  ADC_SQR2_SQ7_3                      ((uint32_t)0x00000008)        /*!< Bit 3 */
03917 #define  ADC_SQR2_SQ7_4                      ((uint32_t)0x00000010)        /*!< Bit 4 */
03918
03919 #define  ADC_SQR2_SQ8                        ((uint32_t)0x000003E0)        /*!< SQ8[4:0] bits (8th conversion in regular sequence) */
03920 #define  ADC_SQR2_SQ8_0                      ((uint32_t)0x00000020)        /*!< Bit 0 */
03921 #define  ADC_SQR2_SQ8_1                      ((uint32_t)0x00000040)        /*!< Bit 1 */
03922 #define  ADC_SQR2_SQ8_2                      ((uint32_t)0x00000080)        /*!< Bit 2 */
03923 #define  ADC_SQR2_SQ8_3                      ((uint32_t)0x00000100)        /*!< Bit 3 */
03924 #define  ADC_SQR2_SQ8_4                      ((uint32_t)0x00000200)        /*!< Bit 4 */
03925
03926 #define  ADC_SQR2_SQ9                        ((uint32_t)0x00007C00)        /*!< SQ9[4:0] bits (9th conversion in regular sequence) */
03927 #define  ADC_SQR2_SQ9_0                      ((uint32_t)0x00000400)        /*!< Bit 0 */
03928 #define  ADC_SQR2_SQ9_1                      ((uint32_t)0x00000800)        /*!< Bit 1 */
03929 #define  ADC_SQR2_SQ9_2                      ((uint32_t)0x00001000)        /*!< Bit 2 */
03930 #define  ADC_SQR2_SQ9_3                      ((uint32_t)0x00002000)        /*!< Bit 3 */
03931 #define  ADC_SQR2_SQ9_4                      ((uint32_t)0x00004000)        /*!< Bit 4 */
03932
03933 #define  ADC_SQR2_SQ10                       ((uint32_t)0x000F8000)        /*!< SQ10[4:0] bits (10th conversion in regular sequence) */
03934 #define  ADC_SQR2_SQ10_0                     ((uint32_t)0x00008000)        /*!< Bit 0 */
03935 #define  ADC_SQR2_SQ10_1                     ((uint32_t)0x00010000)        /*!< Bit 1 */
03936 #define  ADC_SQR2_SQ10_2                     ((uint32_t)0x00020000)        /*!< Bit 2 */
03937 #define  ADC_SQR2_SQ10_3                     ((uint32_t)0x00040000)        /*!< Bit 3 */
03938 #define  ADC_SQR2_SQ10_4                     ((uint32_t)0x00080000)        /*!< Bit 4 */
03939
03940 #define  ADC_SQR2_SQ11                       ((uint32_t)0x01F00000)        /*!< SQ11[4:0] bits (11th conversion in regular sequence) */
03941 #define  ADC_SQR2_SQ11_0                     ((uint32_t)0x00100000)        /*!< Bit 0 */
03942 #define  ADC_SQR2_SQ11_1                     ((uint32_t)0x00200000)        /*!< Bit 1 */
03943 #define  ADC_SQR2_SQ11_2                     ((uint32_t)0x00400000)        /*!< Bit 2 */
03944 #define  ADC_SQR2_SQ11_3                     ((uint32_t)0x00800000)        /*!< Bit 3 */
03945 #define  ADC_SQR2_SQ11_4                     ((uint32_t)0x01000000)        /*!< Bit 4 */
03946
03947 #define  ADC_SQR2_SQ12                       ((uint32_t)0x3E000000)        /*!< SQ12[4:0] bits (12th conversion in regular sequence) */
03948 #define  ADC_SQR2_SQ12_0                     ((uint32_t)0x02000000)        /*!< Bit 0 */
03949 #define  ADC_SQR2_SQ12_1                     ((uint32_t)0x04000000)        /*!< Bit 1 */
03950 #define  ADC_SQR2_SQ12_2                     ((uint32_t)0x08000000)        /*!< Bit 2 */
03951 #define  ADC_SQR2_SQ12_3                     ((uint32_t)0x10000000)        /*!< Bit 3 */
03952 #define  ADC_SQR2_SQ12_4                     ((uint32_t)0x20000000)        /*!< Bit 4 */
03953
03954 /*******************  Bit definition for ADC_SQR3 register  *******************/
03955 #define  ADC_SQR3_SQ1                        ((uint32_t)0x0000001F)        /*!< SQ1[4:0] bits (1st conversion in regular sequence) */
03956 #define  ADC_SQR3_SQ1_0                      ((uint32_t)0x00000001)        /*!< Bit 0 */
03957 #define  ADC_SQR3_SQ1_1                      ((uint32_t)0x00000002)        /*!< Bit 1 */
03958 #define  ADC_SQR3_SQ1_2                      ((uint32_t)0x00000004)        /*!< Bit 2 */
03959 #define  ADC_SQR3_SQ1_3                      ((uint32_t)0x00000008)        /*!< Bit 3 */
03960 #define  ADC_SQR3_SQ1_4                      ((uint32_t)0x00000010)        /*!< Bit 4 */
03961
03962 #define  ADC_SQR3_SQ2                        ((uint32_t)0x000003E0)        /*!< SQ2[4:0] bits (2nd conversion in regular sequence) */
03963 #define  ADC_SQR3_SQ2_0                      ((uint32_t)0x00000020)        /*!< Bit 0 */
03964 #define  ADC_SQR3_SQ2_1                      ((uint32_t)0x00000040)        /*!< Bit 1 */
03965 #define  ADC_SQR3_SQ2_2                      ((uint32_t)0x00000080)        /*!< Bit 2 */
03966 #define  ADC_SQR3_SQ2_3                      ((uint32_t)0x00000100)        /*!< Bit 3 */
03967 #define  ADC_SQR3_SQ2_4                      ((uint32_t)0x00000200)        /*!< Bit 4 */
03968
03969 #define  ADC_SQR3_SQ3                        ((uint32_t)0x00007C00)        /*!< SQ3[4:0] bits (3rd conversion in regular sequence) */
03970 #define  ADC_SQR3_SQ3_0                      ((uint32_t)0x00000400)        /*!< Bit 0 */
03971 #define  ADC_SQR3_SQ3_1                      ((uint32_t)0x00000800)        /*!< Bit 1 */
03972 #define  ADC_SQR3_SQ3_2                      ((uint32_t)0x00001000)        /*!< Bit 2 */
03973 #define  ADC_SQR3_SQ3_3                      ((uint32_t)0x00002000)        /*!< Bit 3 */
03974 #define  ADC_SQR3_SQ3_4                      ((uint32_t)0x00004000)        /*!< Bit 4 */
03975
03976 #define  ADC_SQR3_SQ4                        ((uint32_t)0x000F8000)        /*!< SQ4[4:0] bits (4th conversion in regular sequence) */
03977 #define  ADC_SQR3_SQ4_0                      ((uint32_t)0x00008000)        /*!< Bit 0 */
03978 #define  ADC_SQR3_SQ4_1                      ((uint32_t)0x00010000)        /*!< Bit 1 */
03979 #define  ADC_SQR3_SQ4_2                      ((uint32_t)0x00020000)        /*!< Bit 2 */
03980 #define  ADC_SQR3_SQ4_3                      ((uint32_t)0x00040000)        /*!< Bit 3 */
03981 #define  ADC_SQR3_SQ4_4                      ((uint32_t)0x00080000)        /*!< Bit 4 */
03982
03983 #define  ADC_SQR3_SQ5                        ((uint32_t)0x01F00000)        /*!< SQ5[4:0] bits (5th conversion in regular sequence) */
03984 #define  ADC_SQR3_SQ5_0                      ((uint32_t)0x00100000)        /*!< Bit 0 */
03985 #define  ADC_SQR3_SQ5_1                      ((uint32_t)0x00200000)        /*!< Bit 1 */
03986 #define  ADC_SQR3_SQ5_2                      ((uint32_t)0x00400000)        /*!< Bit 2 */
03987 #define  ADC_SQR3_SQ5_3                      ((uint32_t)0x00800000)        /*!< Bit 3 */
03988 #define  ADC_SQR3_SQ5_4                      ((uint32_t)0x01000000)        /*!< Bit 4 */
03989
03990 #define  ADC_SQR3_SQ6                        ((uint32_t)0x3E000000)        /*!< SQ6[4:0] bits (6th conversion in regular sequence) */
03991 #define  ADC_SQR3_SQ6_0                      ((uint32_t)0x02000000)        /*!< Bit 0 */
03992 #define  ADC_SQR3_SQ6_1                      ((uint32_t)0x04000000)        /*!< Bit 1 */
03993 #define  ADC_SQR3_SQ6_2                      ((uint32_t)0x08000000)        /*!< Bit 2 */
03994 #define  ADC_SQR3_SQ6_3                      ((uint32_t)0x10000000)        /*!< Bit 3 */
03995 #define  ADC_SQR3_SQ6_4                      ((uint32_t)0x20000000)        /*!< Bit 4 */
03996
03997 /*******************  Bit definition for ADC_JSQR register  *******************/
03998 #define  ADC_JSQR_JSQ1                       ((uint32_t)0x0000001F)        /*!< JSQ1[4:0] bits (1st conversion in injected sequence) */
03999 #define  ADC_JSQR_JSQ1_0                     ((uint32_t)0x00000001)        /*!< Bit 0 */
04000 #define  ADC_JSQR_JSQ1_1                     ((uint32_t)0x00000002)        /*!< Bit 1 */
04001 #define  ADC_JSQR_JSQ1_2                     ((uint32_t)0x00000004)        /*!< Bit 2 */
04002 #define  ADC_JSQR_JSQ1_3                     ((uint32_t)0x00000008)        /*!< Bit 3 */
04003 #define  ADC_JSQR_JSQ1_4                     ((uint32_t)0x00000010)        /*!< Bit 4 */
04004
04005 #define  ADC_JSQR_JSQ2                       ((uint32_t)0x000003E0)        /*!< JSQ2[4:0] bits (2nd conversion in injected sequence) */
04006 #define  ADC_JSQR_JSQ2_0                     ((uint32_t)0x00000020)        /*!< Bit 0 */
04007 #define  ADC_JSQR_JSQ2_1                     ((uint32_t)0x00000040)        /*!< Bit 1 */
04008 #define  ADC_JSQR_JSQ2_2                     ((uint32_t)0x00000080)        /*!< Bit 2 */
04009 #define  ADC_JSQR_JSQ2_3                     ((uint32_t)0x00000100)        /*!< Bit 3 */
04010 #define  ADC_JSQR_JSQ2_4                     ((uint32_t)0x00000200)        /*!< Bit 4 */
04011
04012 #define  ADC_JSQR_JSQ3                       ((uint32_t)0x00007C00)        /*!< JSQ3[4:0] bits (3rd conversion in injected sequence) */
04013 #define  ADC_JSQR_JSQ3_0                     ((uint32_t)0x00000400)        /*!< Bit 0 */
04014 #define  ADC_JSQR_JSQ3_1                     ((uint32_t)0x00000800)        /*!< Bit 1 */
04015 #define  ADC_JSQR_JSQ3_2                     ((uint32_t)0x00001000)        /*!< Bit 2 */
04016 #define  ADC_JSQR_JSQ3_3                     ((uint32_t)0x00002000)        /*!< Bit 3 */
04017 #define  ADC_JSQR_JSQ3_4                     ((uint32_t)0x00004000)        /*!< Bit 4 */
04018
04019 #define  ADC_JSQR_JSQ4                       ((uint32_t)0x000F8000)        /*!< JSQ4[4:0] bits (4th conversion in injected sequence) */
04020 #define  ADC_JSQR_JSQ4_0                     ((uint32_t)0x00008000)        /*!< Bit 0 */
04021 #define  ADC_JSQR_JSQ4_1                     ((uint32_t)0x00010000)        /*!< Bit 1 */
04022 #define  ADC_JSQR_JSQ4_2                     ((uint32_t)0x00020000)        /*!< Bit 2 */
04023 #define  ADC_JSQR_JSQ4_3                     ((uint32_t)0x00040000)        /*!< Bit 3 */
04024 #define  ADC_JSQR_JSQ4_4                     ((uint32_t)0x00080000)        /*!< Bit 4 */
04025
04026 #define  ADC_JSQR_JL                         ((uint32_t)0x00300000)        /*!< JL[1:0] bits (Injected Sequence length) */
04027 #define  ADC_JSQR_JL_0                       ((uint32_t)0x00100000)        /*!< Bit 0 */
04028 #define  ADC_JSQR_JL_1                       ((uint32_t)0x00200000)        /*!< Bit 1 */
04029
04030 /*******************  Bit definition for ADC_JDR1 register  *******************/
04031 #define  ADC_JDR1_JDATA                      ((uint16_t)0xFFFF)            /*!< Injected data */
04032
04033 /*******************  Bit definition for ADC_JDR2 register  *******************/
04034 #define  ADC_JDR2_JDATA                      ((uint16_t)0xFFFF)            /*!< Injected data */
04035
04036 /*******************  Bit definition for ADC_JDR3 register  *******************/
04037 #define  ADC_JDR3_JDATA                      ((uint16_t)0xFFFF)            /*!< Injected data */
04038
04039 /*******************  Bit definition for ADC_JDR4 register  *******************/
04040 #define  ADC_JDR4_JDATA                      ((uint16_t)0xFFFF)            /*!< Injected data */
04041
04042 /********************  Bit definition for ADC_DR register  ********************/
04043 #define  ADC_DR_DATA                         ((uint32_t)0x0000FFFF)        /*!< Regular data */
04044 #define  ADC_DR_ADC2DATA                     ((uint32_t)0xFFFF0000)        /*!< ADC2 data */
04045
04046 /******************************************************************************/
04047 /*                                                                            */
04048 /*                      Digital to Analog Converter                           */
04049 /*                                                                            */
04050 /******************************************************************************/
04051
04052 /********************  Bit definition for DAC_CR register  ********************/
04053 #define  DAC_CR_EN1                          ((uint32_t)0x00000001)        /*!< DAC channel1 enable */
04054 #define  DAC_CR_BOFF1                        ((uint32_t)0x00000002)        /*!< DAC channel1 output buffer disable */
04055 #define  DAC_CR_TEN1                         ((uint32_t)0x00000004)        /*!< DAC channel1 Trigger enable */
04056
04057 #define  DAC_CR_TSEL1                        ((uint32_t)0x00000038)        /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
04058 #define  DAC_CR_TSEL1_0                      ((uint32_t)0x00000008)        /*!< Bit 0 */
04059 #define  DAC_CR_TSEL1_1                      ((uint32_t)0x00000010)        /*!< Bit 1 */
04060 #define  DAC_CR_TSEL1_2                      ((uint32_t)0x00000020)        /*!< Bit 2 */
04061
04062 #define  DAC_CR_WAVE1                        ((uint32_t)0x000000C0)        /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
04063 #define  DAC_CR_WAVE1_0                      ((uint32_t)0x00000040)        /*!< Bit 0 */
04064 #define  DAC_CR_WAVE1_1                      ((uint32_t)0x00000080)        /*!< Bit 1 */
04065
04066 #define  DAC_CR_MAMP1                        ((uint32_t)0x00000F00)        /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
04067 #define  DAC_CR_MAMP1_0                      ((uint32_t)0x00000100)        /*!< Bit 0 */
04068 #define  DAC_CR_MAMP1_1                      ((uint32_t)0x00000200)        /*!< Bit 1 */
04069 #define  DAC_CR_MAMP1_2                      ((uint32_t)0x00000400)        /*!< Bit 2 */
04070 #define  DAC_CR_MAMP1_3                      ((uint32_t)0x00000800)        /*!< Bit 3 */
04071
04072 #define  DAC_CR_DMAEN1                       ((uint32_t)0x00001000)        /*!< DAC channel1 DMA enable */
04073 #define  DAC_CR_EN2                          ((uint32_t)0x00010000)        /*!< DAC channel2 enable */
04074 #define  DAC_CR_BOFF2                        ((uint32_t)0x00020000)        /*!< DAC channel2 output buffer disable */
04075 #define  DAC_CR_TEN2                         ((uint32_t)0x00040000)        /*!< DAC channel2 Trigger enable */
04076
04077 #define  DAC_CR_TSEL2                        ((uint32_t)0x00380000)        /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
04078 #define  DAC_CR_TSEL2_0                      ((uint32_t)0x00080000)        /*!< Bit 0 */
04079 #define  DAC_CR_TSEL2_1                      ((uint32_t)0x00100000)        /*!< Bit 1 */
04080 #define  DAC_CR_TSEL2_2                      ((uint32_t)0x00200000)        /*!< Bit 2 */
04081
04082 #define  DAC_CR_WAVE2                        ((uint32_t)0x00C00000)        /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
04083 #define  DAC_CR_WAVE2_0                      ((uint32_t)0x00400000)        /*!< Bit 0 */
04084 #define  DAC_CR_WAVE2_1                      ((uint32_t)0x00800000)        /*!< Bit 1 */
04085
04086 #define  DAC_CR_MAMP2                        ((uint32_t)0x0F000000)        /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
04087 #define  DAC_CR_MAMP2_0                      ((uint32_t)0x01000000)        /*!< Bit 0 */
04088 #define  DAC_CR_MAMP2_1                      ((uint32_t)0x02000000)        /*!< Bit 1 */
04089 #define  DAC_CR_MAMP2_2                      ((uint32_t)0x04000000)        /*!< Bit 2 */
04090 #define  DAC_CR_MAMP2_3                      ((uint32_t)0x08000000)        /*!< Bit 3 */
04091
04092 #define  DAC_CR_DMAEN2                       ((uint32_t)0x10000000)        /*!< DAC channel2 DMA enabled */
04093
04094 /*****************  Bit definition for DAC_SWTRIGR register  ******************/
04095 #define  DAC_SWTRIGR_SWTRIG1                 ((uint8_t)0x01)               /*!< DAC channel1 software trigger */
04096 #define  DAC_SWTRIGR_SWTRIG2                 ((uint8_t)0x02)               /*!< DAC channel2 software trigger */
04097
04098 /*****************  Bit definition for DAC_DHR12R1 register  ******************/
04099 #define  DAC_DHR12R1_DACC1DHR                ((uint16_t)0x0FFF)            /*!< DAC channel1 12-bit Right aligned data */
04100
04101 /*****************  Bit definition for DAC_DHR12L1 register  ******************/
04102 #define  DAC_DHR12L1_DACC1DHR                ((uint16_t)0xFFF0)            /*!< DAC channel1 12-bit Left aligned data */
04103
04104 /******************  Bit definition for DAC_DHR8R1 register  ******************/
04105 #define  DAC_DHR8R1_DACC1DHR                 ((uint8_t)0xFF)               /*!< DAC channel1 8-bit Right aligned data */
04106
04107 /*****************  Bit definition for DAC_DHR12R2 register  ******************/
04108 #define  DAC_DHR12R2_DACC2DHR                ((uint16_t)0x0FFF)            /*!< DAC channel2 12-bit Right aligned data */
04109
04110 /*****************  Bit definition for DAC_DHR12L2 register  ******************/
04111 #define  DAC_DHR12L2_DACC2DHR                ((uint16_t)0xFFF0)            /*!< DAC channel2 12-bit Left aligned data */
04112
04113 /******************  Bit definition for DAC_DHR8R2 register  ******************/
04114 #define  DAC_DHR8R2_DACC2DHR                 ((uint8_t)0xFF)               /*!< DAC channel2 8-bit Right aligned data */
04115
04116 /*****************  Bit definition for DAC_DHR12RD register  ******************/
04117 #define  DAC_DHR12RD_DACC1DHR                ((uint32_t)0x00000FFF)        /*!< DAC channel1 12-bit Right aligned data */
04118 #define  DAC_DHR12RD_DACC2DHR                ((uint32_t)0x0FFF0000)        /*!< DAC channel2 12-bit Right aligned data */
04119
04120 /*****************  Bit definition for DAC_DHR12LD register  ******************/
04121 #define  DAC_DHR12LD_DACC1DHR                ((uint32_t)0x0000FFF0)        /*!< DAC channel1 12-bit Left aligned data */
04122 #define  DAC_DHR12LD_DACC2DHR                ((uint32_t)0xFFF00000)        /*!< DAC channel2 12-bit Left aligned data */
04123
04124 /******************  Bit definition for DAC_DHR8RD register  ******************/
04125 #define  DAC_DHR8RD_DACC1DHR                 ((uint16_t)0x00FF)            /*!< DAC channel1 8-bit Right aligned data */
04126 #define  DAC_DHR8RD_DACC2DHR                 ((uint16_t)0xFF00)            /*!< DAC channel2 8-bit Right aligned data */
04127
04128 /*******************  Bit definition for DAC_DOR1 register  *******************/
04129 #define  DAC_DOR1_DACC1DOR                   ((uint16_t)0x0FFF)            /*!< DAC channel1 data output */
04130
04131 /*******************  Bit definition for DAC_DOR2 register  *******************/
04132 #define  DAC_DOR2_DACC2DOR                   ((uint16_t)0x0FFF)            /*!< DAC channel2 data output */
04133
04134 /********************  Bit definition for DAC_SR register  ********************/
04135 #define  DAC_SR_DMAUDR1                      ((uint32_t)0x00002000)        /*!< DAC channel1 DMA underrun flag */
04136 #define  DAC_SR_DMAUDR2                      ((uint32_t)0x20000000)        /*!< DAC channel2 DMA underrun flag */
04137
04138 /******************************************************************************/
04139 /*                                                                            */
04140 /*                                    CEC                                     */
04141 /*                                                                            */
04142 /******************************************************************************/
04143 /********************  Bit definition for CEC_CFGR register  ******************/
04144 #define  CEC_CFGR_PE              ((uint16_t)0x0001)     /*!<  Peripheral Enable */
04145 #define  CEC_CFGR_IE              ((uint16_t)0x0002)     /*!<  Interrupt Enable */
04146 #define  CEC_CFGR_BTEM            ((uint16_t)0x0004)     /*!<  Bit Timing Error Mode */
04147 #define  CEC_CFGR_BPEM            ((uint16_t)0x0008)     /*!<  Bit Period Error Mode */
04148
04149 /********************  Bit definition for CEC_OAR register  ******************/
04150 #define  CEC_OAR_OA               ((uint16_t)0x000F)     /*!<  OA[3:0]: Own Address */
04151 #define  CEC_OAR_OA_0             ((uint16_t)0x0001)     /*!<  Bit 0 */
04152 #define  CEC_OAR_OA_1             ((uint16_t)0x0002)     /*!<  Bit 1 */
04153 #define  CEC_OAR_OA_2             ((uint16_t)0x0004)     /*!<  Bit 2 */
04154 #define  CEC_OAR_OA_3             ((uint16_t)0x0008)     /*!<  Bit 3 */
04155
04156 /********************  Bit definition for CEC_PRES register  ******************/
04157 #define  CEC_PRES_PRES            ((uint16_t)0x3FFF)   /*!<  Prescaler Counter Value */
04158
04159 /********************  Bit definition for CEC_ESR register  ******************/
04160 #define  CEC_ESR_BTE              ((uint16_t)0x0001)     /*!<  Bit Timing Error */
04161 #define  CEC_ESR_BPE              ((uint16_t)0x0002)     /*!<  Bit Period Error */
04162 #define  CEC_ESR_RBTFE            ((uint16_t)0x0004)     /*!<  Rx Block Transfer Finished Error */
04163 #define  CEC_ESR_SBE              ((uint16_t)0x0008)     /*!<  Start Bit Error */
04164 #define  CEC_ESR_ACKE             ((uint16_t)0x0010)     /*!<  Block Acknowledge Error */
04165 #define  CEC_ESR_LINE             ((uint16_t)0x0020)     /*!<  Line Error */
04166 #define  CEC_ESR_TBTFE            ((uint16_t)0x0040)     /*!<  Tx Block Transfer Finished Error */
04167
04168 /********************  Bit definition for CEC_CSR register  ******************/
04169 #define  CEC_CSR_TSOM             ((uint16_t)0x0001)     /*!<  Tx Start Of Message */
04170 #define  CEC_CSR_TEOM             ((uint16_t)0x0002)     /*!<  Tx End Of Message */
04171 #define  CEC_CSR_TERR             ((uint16_t)0x0004)     /*!<  Tx Error */
04172 #define  CEC_CSR_TBTRF            ((uint16_t)0x0008)     /*!<  Tx Byte Transfer Request or Block Transfer Finished */
04173 #define  CEC_CSR_RSOM             ((uint16_t)0x0010)     /*!<  Rx Start Of Message */
04174 #define  CEC_CSR_REOM             ((uint16_t)0x0020)     /*!<  Rx End Of Message */
04175 #define  CEC_CSR_RERR             ((uint16_t)0x0040)     /*!<  Rx Error */
04176 #define  CEC_CSR_RBTF             ((uint16_t)0x0080)     /*!<  Rx Block Transfer Finished */
04177
04178 /********************  Bit definition for CEC_TXD register  ******************/
04179 #define  CEC_TXD_TXD              ((uint16_t)0x00FF)     /*!<  Tx Data register */
04180
04181 /********************  Bit definition for CEC_RXD register  ******************/
04182 #define  CEC_RXD_RXD              ((uint16_t)0x00FF)     /*!<  Rx Data register */
04183
04184 /******************************************************************************/
04185 /*                                                                            */
04186 /*                                    TIM                                     */
04187 /*                                                                            */
04188 /******************************************************************************/
04189
04190 /*******************  Bit definition for TIM_CR1 register  ********************/
04191 #define  TIM_CR1_CEN                         ((uint16_t)0x0001)            /*!< Counter enable */
04192 #define  TIM_CR1_UDIS                        ((uint16_t)0x0002)            /*!< Update disable */
04193 #define  TIM_CR1_URS                         ((uint16_t)0x0004)            /*!< Update request source */
04194 #define  TIM_CR1_OPM                         ((uint16_t)0x0008)            /*!< One pulse mode */
04195 #define  TIM_CR1_DIR                         ((uint16_t)0x0010)            /*!< Direction */
04196
04197 #define  TIM_CR1_CMS                         ((uint16_t)0x0060)            /*!< CMS[1:0] bits (Center-aligned mode selection) */
04198 #define  TIM_CR1_CMS_0                       ((uint16_t)0x0020)            /*!< Bit 0 */
04199 #define  TIM_CR1_CMS_1                       ((uint16_t)0x0040)            /*!< Bit 1 */
04200
04201 #define  TIM_CR1_ARPE                        ((uint16_t)0x0080)            /*!< Auto-reload preload enable */
04202
04203 #define  TIM_CR1_CKD                         ((uint16_t)0x0300)            /*!< CKD[1:0] bits (clock division) */
04204 #define  TIM_CR1_CKD_0                       ((uint16_t)0x0100)            /*!< Bit 0 */
04205 #define  TIM_CR1_CKD_1                       ((uint16_t)0x0200)            /*!< Bit 1 */
04206
04207 /*******************  Bit definition for TIM_CR2 register  ********************/
04208 #define  TIM_CR2_CCPC                        ((uint16_t)0x0001)            /*!< Capture/Compare Preloaded Control */
04209 #define  TIM_CR2_CCUS                        ((uint16_t)0x0004)            /*!< Capture/Compare Control Update Selection */
04210 #define  TIM_CR2_CCDS                        ((uint16_t)0x0008)            /*!< Capture/Compare DMA Selection */
04211
04212 #define  TIM_CR2_MMS                         ((uint16_t)0x0070)            /*!< MMS[2:0] bits (Master Mode Selection) */
04213 #define  TIM_CR2_MMS_0                       ((uint16_t)0x0010)            /*!< Bit 0 */
04214 #define  TIM_CR2_MMS_1                       ((uint16_t)0x0020)            /*!< Bit 1 */
04215 #define  TIM_CR2_MMS_2                       ((uint16_t)0x0040)            /*!< Bit 2 */
04216
04217 #define  TIM_CR2_TI1S                        ((uint16_t)0x0080)            /*!< TI1 Selection */
04218 #define  TIM_CR2_OIS1                        ((uint16_t)0x0100)            /*!< Output Idle state 1 (OC1 output) */
04219 #define  TIM_CR2_OIS1N                       ((uint16_t)0x0200)            /*!< Output Idle state 1 (OC1N output) */
04220 #define  TIM_CR2_OIS2                        ((uint16_t)0x0400)            /*!< Output Idle state 2 (OC2 output) */
04221 #define  TIM_CR2_OIS2N                       ((uint16_t)0x0800)            /*!< Output Idle state 2 (OC2N output) */
04222 #define  TIM_CR2_OIS3                        ((uint16_t)0x1000)            /*!< Output Idle state 3 (OC3 output) */
04223 #define  TIM_CR2_OIS3N                       ((uint16_t)0x2000)            /*!< Output Idle state 3 (OC3N output) */
04224 #define  TIM_CR2_OIS4                        ((uint16_t)0x4000)            /*!< Output Idle state 4 (OC4 output) */
04225
04226 /*******************  Bit definition for TIM_SMCR register  *******************/
04227 #define  TIM_SMCR_SMS                        ((uint16_t)0x0007)            /*!< SMS[2:0] bits (Slave mode selection) */
04228 #define  TIM_SMCR_SMS_0                      ((uint16_t)0x0001)            /*!< Bit 0 */
04229 #define  TIM_SMCR_SMS_1                      ((uint16_t)0x0002)            /*!< Bit 1 */
04230 #define  TIM_SMCR_SMS_2                      ((uint16_t)0x0004)            /*!< Bit 2 */
04231
04232 #define  TIM_SMCR_TS                         ((uint16_t)0x0070)            /*!< TS[2:0] bits (Trigger selection) */
04233 #define  TIM_SMCR_TS_0                       ((uint16_t)0x0010)            /*!< Bit 0 */
04234 #define  TIM_SMCR_TS_1                       ((uint16_t)0x0020)            /*!< Bit 1 */
04235 #define  TIM_SMCR_TS_2                       ((uint16_t)0x0040)            /*!< Bit 2 */
04236
04237 #define  TIM_SMCR_MSM                        ((uint16_t)0x0080)            /*!< Master/slave mode */
04238
04239 #define  TIM_SMCR_ETF                        ((uint16_t)0x0F00)            /*!< ETF[3:0] bits (External trigger filter) */
04240 #define  TIM_SMCR_ETF_0                      ((uint16_t)0x0100)            /*!< Bit 0 */
04241 #define  TIM_SMCR_ETF_1                      ((uint16_t)0x0200)            /*!< Bit 1 */
04242 #define  TIM_SMCR_ETF_2                      ((uint16_t)0x0400)            /*!< Bit 2 */
04243 #define  TIM_SMCR_ETF_3                      ((uint16_t)0x0800)            /*!< Bit 3 */
04244
04245 #define  TIM_SMCR_ETPS                       ((uint16_t)0x3000)            /*!< ETPS[1:0] bits (External trigger prescaler) */
04246 #define  TIM_SMCR_ETPS_0                     ((uint16_t)0x1000)            /*!< Bit 0 */
04247 #define  TIM_SMCR_ETPS_1                     ((uint16_t)0x2000)            /*!< Bit 1 */
04248
04249 #define  TIM_SMCR_ECE                        ((uint16_t)0x4000)            /*!< External clock enable */
04250 #define  TIM_SMCR_ETP                        ((uint16_t)0x8000)            /*!< External trigger polarity */
04251
04252 /*******************  Bit definition for TIM_DIER register  *******************/
04253 #define  TIM_DIER_UIE                        ((uint16_t)0x0001)            /*!< Update interrupt enable */
04254 #define  TIM_DIER_CC1IE                      ((uint16_t)0x0002)            /*!< Capture/Compare 1 interrupt enable */
04255 #define  TIM_DIER_CC2IE                      ((uint16_t)0x0004)            /*!< Capture/Compare 2 interrupt enable */
04256 #define  TIM_DIER_CC3IE                      ((uint16_t)0x0008)            /*!< Capture/Compare 3 interrupt enable */
04257 #define  TIM_DIER_CC4IE                      ((uint16_t)0x0010)            /*!< Capture/Compare 4 interrupt enable */
04258 #define  TIM_DIER_COMIE                      ((uint16_t)0x0020)            /*!< COM interrupt enable */
04259 #define  TIM_DIER_TIE                        ((uint16_t)0x0040)            /*!< Trigger interrupt enable */
04260 #define  TIM_DIER_BIE                        ((uint16_t)0x0080)            /*!< Break interrupt enable */
04261 #define  TIM_DIER_UDE                        ((uint16_t)0x0100)            /*!< Update DMA request enable */
04262 #define  TIM_DIER_CC1DE                      ((uint16_t)0x0200)            /*!< Capture/Compare 1 DMA request enable */
04263 #define  TIM_DIER_CC2DE                      ((uint16_t)0x0400)            /*!< Capture/Compare 2 DMA request enable */
04264 #define  TIM_DIER_CC3DE                      ((uint16_t)0x0800)            /*!< Capture/Compare 3 DMA request enable */
04265 #define  TIM_DIER_CC4DE                      ((uint16_t)0x1000)            /*!< Capture/Compare 4 DMA request enable */
04266 #define  TIM_DIER_COMDE                      ((uint16_t)0x2000)            /*!< COM DMA request enable */
04267 #define  TIM_DIER_TDE                        ((uint16_t)0x4000)            /*!< Trigger DMA request enable */
04268
04269 /********************  Bit definition for TIM_SR register  ********************/
04270 #define  TIM_SR_UIF                          ((uint16_t)0x0001)            /*!< Update interrupt Flag */
04271 #define  TIM_SR_CC1IF                        ((uint16_t)0x0002)            /*!< Capture/Compare 1 interrupt Flag */
04272 #define  TIM_SR_CC2IF                        ((uint16_t)0x0004)            /*!< Capture/Compare 2 interrupt Flag */
04273 #define  TIM_SR_CC3IF                        ((uint16_t)0x0008)            /*!< Capture/Compare 3 interrupt Flag */
04274 #define  TIM_SR_CC4IF                        ((uint16_t)0x0010)            /*!< Capture/Compare 4 interrupt Flag */
04275 #define  TIM_SR_COMIF                        ((uint16_t)0x0020)            /*!< COM interrupt Flag */
04276 #define  TIM_SR_TIF                          ((uint16_t)0x0040)            /*!< Trigger interrupt Flag */
04277 #define  TIM_SR_BIF                          ((uint16_t)0x0080)            /*!< Break interrupt Flag */
04278 #define  TIM_SR_CC1OF                        ((uint16_t)0x0200)            /*!< Capture/Compare 1 Overcapture Flag */
04279 #define  TIM_SR_CC2OF                        ((uint16_t)0x0400)            /*!< Capture/Compare 2 Overcapture Flag */
04280 #define  TIM_SR_CC3OF                        ((uint16_t)0x0800)            /*!< Capture/Compare 3 Overcapture Flag */
04281 #define  TIM_SR_CC4OF                        ((uint16_t)0x1000)            /*!< Capture/Compare 4 Overcapture Flag */
04282
04283 /*******************  Bit definition for TIM_EGR register  ********************/
04284 #define  TIM_EGR_UG                          ((uint8_t)0x01)               /*!< Update Generation */
04285 #define  TIM_EGR_CC1G                        ((uint8_t)0x02)               /*!< Capture/Compare 1 Generation */
04286 #define  TIM_EGR_CC2G                        ((uint8_t)0x04)               /*!< Capture/Compare 2 Generation */
04287 #define  TIM_EGR_CC3G                        ((uint8_t)0x08)               /*!< Capture/Compare 3 Generation */
04288 #define  TIM_EGR_CC4G                        ((uint8_t)0x10)               /*!< Capture/Compare 4 Generation */
04289 #define  TIM_EGR_COMG                        ((uint8_t)0x20)               /*!< Capture/Compare Control Update Generation */
04290 #define  TIM_EGR_TG                          ((uint8_t)0x40)               /*!< Trigger Generation */
04291 #define  TIM_EGR_BG                          ((uint8_t)0x80)               /*!< Break Generation */
04292
04293 /******************  Bit definition for TIM_CCMR1 register  *******************/
04294 #define  TIM_CCMR1_CC1S                      ((uint16_t)0x0003)            /*!< CC1S[1:0] bits (Capture/Compare 1 Selection) */
04295 #define  TIM_CCMR1_CC1S_0                    ((uint16_t)0x0001)            /*!< Bit 0 */
04296 #define  TIM_CCMR1_CC1S_1                    ((uint16_t)0x0002)            /*!< Bit 1 */
04297
04298 #define  TIM_CCMR1_OC1FE                     ((uint16_t)0x0004)            /*!< Output Compare 1 Fast enable */
04299 #define  TIM_CCMR1_OC1PE                     ((uint16_t)0x0008)            /*!< Output Compare 1 Preload enable */
04300
04301 #define  TIM_CCMR1_OC1M                      ((uint16_t)0x0070)            /*!< OC1M[2:0] bits (Output Compare 1 Mode) */
04302 #define  TIM_CCMR1_OC1M_0                    ((uint16_t)0x0010)            /*!< Bit 0 */
04303 #define  TIM_CCMR1_OC1M_1                    ((uint16_t)0x0020)            /*!< Bit 1 */
04304 #define  TIM_CCMR1_OC1M_2                    ((uint16_t)0x0040)            /*!< Bit 2 */
04305
04306 #define  TIM_CCMR1_OC1CE                     ((uint16_t)0x0080)            /*!< Output Compare 1Clear Enable */
04307
04308 #define  TIM_CCMR1_CC2S                      ((uint16_t)0x0300)            /*!< CC2S[1:0] bits (Capture/Compare 2 Selection) */
04309 #define  TIM_CCMR1_CC2S_0                    ((uint16_t)0x0100)            /*!< Bit 0 */
04310 #define  TIM_CCMR1_CC2S_1                    ((uint16_t)0x0200)            /*!< Bit 1 */
04311
04312 #define  TIM_CCMR1_OC2FE                     ((uint16_t)0x0400)            /*!< Output Compare 2 Fast enable */
04313 #define  TIM_CCMR1_OC2PE                     ((uint16_t)0x0800)            /*!< Output Compare 2 Preload enable */
04314
04315 #define  TIM_CCMR1_OC2M                      ((uint16_t)0x7000)            /*!< OC2M[2:0] bits (Output Compare 2 Mode) */
04316 #define  TIM_CCMR1_OC2M_0                    ((uint16_t)0x1000)            /*!< Bit 0 */
04317 #define  TIM_CCMR1_OC2M_1                    ((uint16_t)0x2000)            /*!< Bit 1 */
04318 #define  TIM_CCMR1_OC2M_2                    ((uint16_t)0x4000)            /*!< Bit 2 */
04319
04320 #define  TIM_CCMR1_OC2CE                     ((uint16_t)0x8000)            /*!< Output Compare 2 Clear Enable */
04321
04322 /*----------------------------------------------------------------------------*/
04323
04324 #define  TIM_CCMR1_IC1PSC                    ((uint16_t)0x000C)            /*!< IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
04325 #define  TIM_CCMR1_IC1PSC_0                  ((uint16_t)0x0004)            /*!< Bit 0 */
04326 #define  TIM_CCMR1_IC1PSC_1                  ((uint16_t)0x0008)            /*!< Bit 1 */
04327
04328 #define  TIM_CCMR1_IC1F                      ((uint16_t)0x00F0)            /*!< IC1F[3:0] bits (Input Capture 1 Filter) */
04329 #define  TIM_CCMR1_IC1F_0                    ((uint16_t)0x0010)            /*!< Bit 0 */
04330 #define  TIM_CCMR1_IC1F_1                    ((uint16_t)0x0020)            /*!< Bit 1 */
04331 #define  TIM_CCMR1_IC1F_2                    ((uint16_t)0x0040)            /*!< Bit 2 */
04332 #define  TIM_CCMR1_IC1F_3                    ((uint16_t)0x0080)            /*!< Bit 3 */
04333
04334 #define  TIM_CCMR1_IC2PSC                    ((uint16_t)0x0C00)            /*!< IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
04335 #define  TIM_CCMR1_IC2PSC_0                  ((uint16_t)0x0400)            /*!< Bit 0 */
04336 #define  TIM_CCMR1_IC2PSC_1                  ((uint16_t)0x0800)            /*!< Bit 1 */
04337
04338 #define  TIM_CCMR1_IC2F                      ((uint16_t)0xF000)            /*!< IC2F[3:0] bits (Input Capture 2 Filter) */
04339 #define  TIM_CCMR1_IC2F_0                    ((uint16_t)0x1000)            /*!< Bit 0 */
04340 #define  TIM_CCMR1_IC2F_1                    ((uint16_t)0x2000)            /*!< Bit 1 */
04341 #define  TIM_CCMR1_IC2F_2                    ((uint16_t)0x4000)            /*!< Bit 2 */
04342 #define  TIM_CCMR1_IC2F_3                    ((uint16_t)0x8000)            /*!< Bit 3 */
04343
04344 /******************  Bit definition for TIM_CCMR2 register  *******************/
04345 #define  TIM_CCMR2_CC3S                      ((uint16_t)0x0003)            /*!< CC3S[1:0] bits (Capture/Compare 3 Selection) */
04346 #define  TIM_CCMR2_CC3S_0                    ((uint16_t)0x0001)            /*!< Bit 0 */
04347 #define  TIM_CCMR2_CC3S_1                    ((uint16_t)0x0002)            /*!< Bit 1 */
04348
04349 #define  TIM_CCMR2_OC3FE                     ((uint16_t)0x0004)            /*!< Output Compare 3 Fast enable */
04350 #define  TIM_CCMR2_OC3PE                     ((uint16_t)0x0008)            /*!< Output Compare 3 Preload enable */
04351
04352 #define  TIM_CCMR2_OC3M                      ((uint16_t)0x0070)            /*!< OC3M[2:0] bits (Output Compare 3 Mode) */
04353 #define  TIM_CCMR2_OC3M_0                    ((uint16_t)0x0010)            /*!< Bit 0 */
04354 #define  TIM_CCMR2_OC3M_1                    ((uint16_t)0x0020)            /*!< Bit 1 */
04355 #define  TIM_CCMR2_OC3M_2                    ((uint16_t)0x0040)            /*!< Bit 2 */
04356
04357 #define  TIM_CCMR2_OC3CE                     ((uint16_t)0x0080)            /*!< Output Compare 3 Clear Enable */
04358
04359 #define  TIM_CCMR2_CC4S                      ((uint16_t)0x0300)            /*!< CC4S[1:0] bits (Capture/Compare 4 Selection) */
04360 #define  TIM_CCMR2_CC4S_0                    ((uint16_t)0x0100)            /*!< Bit 0 */
04361 #define  TIM_CCMR2_CC4S_1                    ((uint16_t)0x0200)            /*!< Bit 1 */
04362
04363 #define  TIM_CCMR2_OC4FE                     ((uint16_t)0x0400)            /*!< Output Compare 4 Fast enable */
04364 #define  TIM_CCMR2_OC4PE                     ((uint16_t)0x0800)            /*!< Output Compare 4 Preload enable */
04365
04366 #define  TIM_CCMR2_OC4M                      ((uint16_t)0x7000)            /*!< OC4M[2:0] bits (Output Compare 4 Mode) */
04367 #define  TIM_CCMR2_OC4M_0                    ((uint16_t)0x1000)            /*!< Bit 0 */
04368 #define  TIM_CCMR2_OC4M_1                    ((uint16_t)0x2000)            /*!< Bit 1 */
04369 #define  TIM_CCMR2_OC4M_2                    ((uint16_t)0x4000)            /*!< Bit 2 */
04370
04371 #define  TIM_CCMR2_OC4CE                     ((uint16_t)0x8000)            /*!< Output Compare 4 Clear Enable */
04372
04373 /*----------------------------------------------------------------------------*/
04374
04375 #define  TIM_CCMR2_IC3PSC                    ((uint16_t)0x000C)            /*!< IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
04376 #define  TIM_CCMR2_IC3PSC_0                  ((uint16_t)0x0004)            /*!< Bit 0 */
04377 #define  TIM_CCMR2_IC3PSC_1                  ((uint16_t)0x0008)            /*!< Bit 1 */
04378
04379 #define  TIM_CCMR2_IC3F                      ((uint16_t)0x00F0)            /*!< IC3F[3:0] bits (Input Capture 3 Filter) */
04380 #define  TIM_CCMR2_IC3F_0                    ((uint16_t)0x0010)            /*!< Bit 0 */
04381 #define  TIM_CCMR2_IC3F_1                    ((uint16_t)0x0020)            /*!< Bit 1 */
04382 #define  TIM_CCMR2_IC3F_2                    ((uint16_t)0x0040)            /*!< Bit 2 */
04383 #define  TIM_CCMR2_IC3F_3                    ((uint16_t)0x0080)            /*!< Bit 3 */
04384
04385 #define  TIM_CCMR2_IC4PSC                    ((uint16_t)0x0C00)            /*!< IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
04386 #define  TIM_CCMR2_IC4PSC_0                  ((uint16_t)0x0400)            /*!< Bit 0 */
04387 #define  TIM_CCMR2_IC4PSC_1                  ((uint16_t)0x0800)            /*!< Bit 1 */
04388
04389 #define  TIM_CCMR2_IC4F                      ((uint16_t)0xF000)            /*!< IC4F[3:0] bits (Input Capture 4 Filter) */
04390 #define  TIM_CCMR2_IC4F_0                    ((uint16_t)0x1000)            /*!< Bit 0 */
04391 #define  TIM_CCMR2_IC4F_1                    ((uint16_t)0x2000)            /*!< Bit 1 */
04392 #define  TIM_CCMR2_IC4F_2                    ((uint16_t)0x4000)            /*!< Bit 2 */
04393 #define  TIM_CCMR2_IC4F_3                    ((uint16_t)0x8000)            /*!< Bit 3 */
04394
04395 /*******************  Bit definition for TIM_CCER register  *******************/
04396 #define  TIM_CCER_CC1E                       ((uint16_t)0x0001)            /*!< Capture/Compare 1 output enable */
04397 #define  TIM_CCER_CC1P                       ((uint16_t)0x0002)            /*!< Capture/Compare 1 output Polarity */
04398 #define  TIM_CCER_CC1NE                      ((uint16_t)0x0004)            /*!< Capture/Compare 1 Complementary output enable */
04399 #define  TIM_CCER_CC1NP                      ((uint16_t)0x0008)            /*!< Capture/Compare 1 Complementary output Polarity */
04400 #define  TIM_CCER_CC2E                       ((uint16_t)0x0010)            /*!< Capture/Compare 2 output enable */
04401 #define  TIM_CCER_CC2P                       ((uint16_t)0x0020)            /*!< Capture/Compare 2 output Polarity */
04402 #define  TIM_CCER_CC2NE                      ((uint16_t)0x0040)            /*!< Capture/Compare 2 Complementary output enable */
04403 #define  TIM_CCER_CC2NP                      ((uint16_t)0x0080)            /*!< Capture/Compare 2 Complementary output Polarity */
04404 #define  TIM_CCER_CC3E                       ((uint16_t)0x0100)            /*!< Capture/Compare 3 output enable */
04405 #define  TIM_CCER_CC3P                       ((uint16_t)0x0200)            /*!< Capture/Compare 3 output Polarity */
04406 #define  TIM_CCER_CC3NE                      ((uint16_t)0x0400)            /*!< Capture/Compare 3 Complementary output enable */
04407 #define  TIM_CCER_CC3NP                      ((uint16_t)0x0800)            /*!< Capture/Compare 3 Complementary output Polarity */
04408 #define  TIM_CCER_CC4E                       ((uint16_t)0x1000)            /*!< Capture/Compare 4 output enable */
04409 #define  TIM_CCER_CC4P                       ((uint16_t)0x2000)            /*!< Capture/Compare 4 output Polarity */
04410 #define  TIM_CCER_CC4NP                      ((uint16_t)0x8000)            /*!< Capture/Compare 4 Complementary output Polarity */
04411
04412 /*******************  Bit definition for TIM_CNT register  ********************/
04413 #define  TIM_CNT_CNT                         ((uint16_t)0xFFFF)            /*!< Counter Value */
04414
04415 /*******************  Bit definition for TIM_PSC register  ********************/
04416 #define  TIM_PSC_PSC                         ((uint16_t)0xFFFF)            /*!< Prescaler Value */
04417
04418 /*******************  Bit definition for TIM_ARR register  ********************/
04419 #define  TIM_ARR_ARR                         ((uint16_t)0xFFFF)            /*!< actual auto-reload Value */
04420
04421 /*******************  Bit definition for TIM_RCR register  ********************/
04422 #define  TIM_RCR_REP                         ((uint8_t)0xFF)               /*!< Repetition Counter Value */
04423
04424 /*******************  Bit definition for TIM_CCR1 register  *******************/
04425 #define  TIM_CCR1_CCR1                       ((uint16_t)0xFFFF)            /*!< Capture/Compare 1 Value */
04426
04427 /*******************  Bit definition for TIM_CCR2 register  *******************/
04428 #define  TIM_CCR2_CCR2                       ((uint16_t)0xFFFF)            /*!< Capture/Compare 2 Value */
04429
04430 /*******************  Bit definition for TIM_CCR3 register  *******************/
04431 #define  TIM_CCR3_CCR3                       ((uint16_t)0xFFFF)            /*!< Capture/Compare 3 Value */
04432
04433 /*******************  Bit definition for TIM_CCR4 register  *******************/
04434 #define  TIM_CCR4_CCR4                       ((uint16_t)0xFFFF)            /*!< Capture/Compare 4 Value */
04435
04436 /*******************  Bit definition for TIM_BDTR register  *******************/
04437 #define  TIM_BDTR_DTG                        ((uint16_t)0x00FF)            /*!< DTG[0:7] bits (Dead-Time Generator set-up) */
04438 #define  TIM_BDTR_DTG_0                      ((uint16_t)0x0001)            /*!< Bit 0 */
04439 #define  TIM_BDTR_DTG_1                      ((uint16_t)0x0002)            /*!< Bit 1 */
04440 #define  TIM_BDTR_DTG_2                      ((uint16_t)0x0004)            /*!< Bit 2 */
04441 #define  TIM_BDTR_DTG_3                      ((uint16_t)0x0008)            /*!< Bit 3 */
04442 #define  TIM_BDTR_DTG_4                      ((uint16_t)0x0010)            /*!< Bit 4 */
04443 #define  TIM_BDTR_DTG_5                      ((uint16_t)0x0020)            /*!< Bit 5 */
04444 #define  TIM_BDTR_DTG_6                      ((uint16_t)0x0040)            /*!< Bit 6 */
04445 #define  TIM_BDTR_DTG_7                      ((uint16_t)0x0080)            /*!< Bit 7 */
04446
04447 #define  TIM_BDTR_LOCK                       ((uint16_t)0x0300)            /*!< LOCK[1:0] bits (Lock Configuration) */
04448 #define  TIM_BDTR_LOCK_0                     ((uint16_t)0x0100)            /*!< Bit 0 */
04449 #define  TIM_BDTR_LOCK_1                     ((uint16_t)0x0200)            /*!< Bit 1 */
04450
04451 #define  TIM_BDTR_OSSI                       ((uint16_t)0x0400)            /*!< Off-State Selection for Idle mode */
04452 #define  TIM_BDTR_OSSR                       ((uint16_t)0x0800)            /*!< Off-State Selection for Run mode */
04453 #define  TIM_BDTR_BKE                        ((uint16_t)0x1000)            /*!< Break enable */
04454 #define  TIM_BDTR_BKP                        ((uint16_t)0x2000)            /*!< Break Polarity */
04455 #define  TIM_BDTR_AOE                        ((uint16_t)0x4000)            /*!< Automatic Output enable */
04456 #define  TIM_BDTR_MOE                        ((uint16_t)0x8000)            /*!< Main Output enable */
04457
04458 /*******************  Bit definition for TIM_DCR register  ********************/
04459 #define  TIM_DCR_DBA                         ((uint16_t)0x001F)            /*!< DBA[4:0] bits (DMA Base Address) */
04460 #define  TIM_DCR_DBA_0                       ((uint16_t)0x0001)            /*!< Bit 0 */
04461 #define  TIM_DCR_DBA_1                       ((uint16_t)0x0002)            /*!< Bit 1 */
04462 #define  TIM_DCR_DBA_2                       ((uint16_t)0x0004)            /*!< Bit 2 */
04463 #define  TIM_DCR_DBA_3                       ((uint16_t)0x0008)            /*!< Bit 3 */
04464 #define  TIM_DCR_DBA_4                       ((uint16_t)0x0010)            /*!< Bit 4 */
04465
04466 #define  TIM_DCR_DBL                         ((uint16_t)0x1F00)            /*!< DBL[4:0] bits (DMA Burst Length) */
04467 #define  TIM_DCR_DBL_0                       ((uint16_t)0x0100)            /*!< Bit 0 */
04468 #define  TIM_DCR_DBL_1                       ((uint16_t)0x0200)            /*!< Bit 1 */
04469 #define  TIM_DCR_DBL_2                       ((uint16_t)0x0400)            /*!< Bit 2 */
04470 #define  TIM_DCR_DBL_3                       ((uint16_t)0x0800)            /*!< Bit 3 */
04471 #define  TIM_DCR_DBL_4                       ((uint16_t)0x1000)            /*!< Bit 4 */
04472
04473 /*******************  Bit definition for TIM_DMAR register  *******************/
04474 #define  TIM_DMAR_DMAB                       ((uint16_t)0xFFFF)            /*!< DMA register for burst accesses */
04475
04476 /******************************************************************************/
04477 /*                                                                            */
04478 /*                             Real-Time Clock                                */
04479 /*                                                                            */
04480 /******************************************************************************/
04481
04482 /*******************  Bit definition for RTC_CRH register  ********************/
04483 #define  RTC_CRH_SECIE                       ((uint8_t)0x01)               /*!< Second Interrupt Enable */
04484 #define  RTC_CRH_ALRIE                       ((uint8_t)0x02)               /*!< Alarm Interrupt Enable */
04485 #define  RTC_CRH_OWIE                        ((uint8_t)0x04)               /*!< OverfloW Interrupt Enable */
04486
04487 /*******************  Bit definition for RTC_CRL register  ********************/
04488 #define  RTC_CRL_SECF                        ((uint8_t)0x01)               /*!< Second Flag */
04489 #define  RTC_CRL_ALRF                        ((uint8_t)0x02)               /*!< Alarm Flag */
04490 #define  RTC_CRL_OWF                         ((uint8_t)0x04)               /*!< OverfloW Flag */
04491 #define  RTC_CRL_RSF                         ((uint8_t)0x08)               /*!< Registers Synchronized Flag */
04492 #define  RTC_CRL_CNF                         ((uint8_t)0x10)               /*!< Configuration Flag */
04493 #define  RTC_CRL_RTOFF                       ((uint8_t)0x20)               /*!< RTC operation OFF */
04494
04495 /*******************  Bit definition for RTC_PRLH register  *******************/
04496 #define  RTC_PRLH_PRL                        ((uint16_t)0x000F)            /*!< RTC Prescaler Reload Value High */
04497
04498 /*******************  Bit definition for RTC_PRLL register  *******************/
04499 #define  RTC_PRLL_PRL                        ((uint16_t)0xFFFF)            /*!< RTC Prescaler Reload Value Low */
04500
04501 /*******************  Bit definition for RTC_DIVH register  *******************/
04502 #define  RTC_DIVH_RTC_DIV                    ((uint16_t)0x000F)            /*!< RTC Clock Divider High */
04503
04504 /*******************  Bit definition for RTC_DIVL register  *******************/
04505 #define  RTC_DIVL_RTC_DIV                    ((uint16_t)0xFFFF)            /*!< RTC Clock Divider Low */
04506
04507 /*******************  Bit definition for RTC_CNTH register  *******************/
04508 #define  RTC_CNTH_RTC_CNT                    ((uint16_t)0xFFFF)            /*!< RTC Counter High */
04509
04510 /*******************  Bit definition for RTC_CNTL register  *******************/
04511 #define  RTC_CNTL_RTC_CNT                    ((uint16_t)0xFFFF)            /*!< RTC Counter Low */
04512
04513 /*******************  Bit definition for RTC_ALRH register  *******************/
04514 #define  RTC_ALRH_RTC_ALR                    ((uint16_t)0xFFFF)            /*!< RTC Alarm High */
04515
04516 /*******************  Bit definition for RTC_ALRL register  *******************/
04517 #define  RTC_ALRL_RTC_ALR                    ((uint16_t)0xFFFF)            /*!< RTC Alarm Low */
04518
04519 /******************************************************************************/
04520 /*                                                                            */
04521 /*                           Independent WATCHDOG                             */
04522 /*                                                                            */
04523 /******************************************************************************/
04524
04525 /*******************  Bit definition for IWDG_KR register  ********************/
04526 #define  IWDG_KR_KEY                         ((uint16_t)0xFFFF)            /*!< Key value (write only, read 0000h) */
04527
04528 /*******************  Bit definition for IWDG_PR register  ********************/
04529 #define  IWDG_PR_PR                          ((uint8_t)0x07)               /*!< PR[2:0] (Prescaler divider) */
04530 #define  IWDG_PR_PR_0                        ((uint8_t)0x01)               /*!< Bit 0 */
04531 #define  IWDG_PR_PR_1                        ((uint8_t)0x02)               /*!< Bit 1 */
04532 #define  IWDG_PR_PR_2                        ((uint8_t)0x04)               /*!< Bit 2 */
04533
04534 /*******************  Bit definition for IWDG_RLR register  *******************/
04535 #define  IWDG_RLR_RL                         ((uint16_t)0x0FFF)            /*!< Watchdog counter reload value */
04536
04537 /*******************  Bit definition for IWDG_SR register  ********************/
04538 #define  IWDG_SR_PVU                         ((uint8_t)0x01)               /*!< Watchdog prescaler value update */
04539 #define  IWDG_SR_RVU                         ((uint8_t)0x02)               /*!< Watchdog counter reload value update */
04540
04541 /******************************************************************************/
04542 /*                                                                            */
04543 /*                            Window WATCHDOG                                 */
04544 /*                                                                            */
04545 /******************************************************************************/
04546
04547 /*******************  Bit definition for WWDG_CR register  ********************/
04548 #define  WWDG_CR_T                           ((uint8_t)0x7F)               /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
04549 #define  WWDG_CR_T0                          ((uint8_t)0x01)               /*!< Bit 0 */
04550 #define  WWDG_CR_T1                          ((uint8_t)0x02)               /*!< Bit 1 */
04551 #define  WWDG_CR_T2                          ((uint8_t)0x04)               /*!< Bit 2 */
04552 #define  WWDG_CR_T3                          ((uint8_t)0x08)               /*!< Bit 3 */
04553 #define  WWDG_CR_T4                          ((uint8_t)0x10)               /*!< Bit 4 */
04554 #define  WWDG_CR_T5                          ((uint8_t)0x20)               /*!< Bit 5 */
04555 #define  WWDG_CR_T6                          ((uint8_t)0x40)               /*!< Bit 6 */
04556
04557 #define  WWDG_CR_WDGA                        ((uint8_t)0x80)               /*!< Activation bit */
04558
04559 /*******************  Bit definition for WWDG_CFR register  *******************/
04560 #define  WWDG_CFR_W                          ((uint16_t)0x007F)            /*!< W[6:0] bits (7-bit window value) */
04561 #define  WWDG_CFR_W0                         ((uint16_t)0x0001)            /*!< Bit 0 */
04562 #define  WWDG_CFR_W1                         ((uint16_t)0x0002)            /*!< Bit 1 */
04563 #define  WWDG_CFR_W2                         ((uint16_t)0x0004)            /*!< Bit 2 */
04564 #define  WWDG_CFR_W3                         ((uint16_t)0x0008)            /*!< Bit 3 */
04565 #define  WWDG_CFR_W4                         ((uint16_t)0x0010)            /*!< Bit 4 */
04566 #define  WWDG_CFR_W5                         ((uint16_t)0x0020)            /*!< Bit 5 */
04567 #define  WWDG_CFR_W6                         ((uint16_t)0x0040)            /*!< Bit 6 */
04568
04569 #define  WWDG_CFR_WDGTB                      ((uint16_t)0x0180)            /*!< WDGTB[1:0] bits (Timer Base) */
04570 #define  WWDG_CFR_WDGTB0                     ((uint16_t)0x0080)            /*!< Bit 0 */
04571 #define  WWDG_CFR_WDGTB1                     ((uint16_t)0x0100)            /*!< Bit 1 */
04572
04573 #define  WWDG_CFR_EWI                        ((uint16_t)0x0200)            /*!< Early Wakeup Interrupt */
04574
04575 /*******************  Bit definition for WWDG_SR register  ********************/
04576 #define  WWDG_SR_EWIF                        ((uint8_t)0x01)               /*!< Early Wakeup Interrupt Flag */
04577
04578 /******************************************************************************/
04579 /*                                                                            */
04580 /*                       Flexible Static Memory Controller                    */
04581 /*                                                                            */
04582 /******************************************************************************/
04583
04584 /******************  Bit definition for FSMC_BCR1 register  *******************/
04585 #define  FSMC_BCR1_MBKEN                     ((uint32_t)0x00000001)        /*!< Memory bank enable bit */
04586 #define  FSMC_BCR1_MUXEN                     ((uint32_t)0x00000002)        /*!< Address/data multiplexing enable bit */
04587
04588 #define  FSMC_BCR1_MTYP                      ((uint32_t)0x0000000C)        /*!< MTYP[1:0] bits (Memory type) */
04589 #define  FSMC_BCR1_MTYP_0                    ((uint32_t)0x00000004)        /*!< Bit 0 */
04590 #define  FSMC_BCR1_MTYP_1                    ((uint32_t)0x00000008)        /*!< Bit 1 */
04591
04592 #define  FSMC_BCR1_MWID                      ((uint32_t)0x00000030)        /*!< MWID[1:0] bits (Memory data bus width) */
04593 #define  FSMC_BCR1_MWID_0                    ((uint32_t)0x00000010)        /*!< Bit 0 */
04594 #define  FSMC_BCR1_MWID_1                    ((uint32_t)0x00000020)        /*!< Bit 1 */
04595
04596 #define  FSMC_BCR1_FACCEN                    ((uint32_t)0x00000040)        /*!< Flash access enable */
04597 #define  FSMC_BCR1_BURSTEN                   ((uint32_t)0x00000100)        /*!< Burst enable bit */
04598 #define  FSMC_BCR1_WAITPOL                   ((uint32_t)0x00000200)        /*!< Wait signal polarity bit */
04599 #define  FSMC_BCR1_WRAPMOD                   ((uint32_t)0x00000400)        /*!< Wrapped burst mode support */
04600 #define  FSMC_BCR1_WAITCFG                   ((uint32_t)0x00000800)        /*!< Wait timing configuration */
04601 #define  FSMC_BCR1_WREN                      ((uint32_t)0x00001000)        /*!< Write enable bit */
04602 #define  FSMC_BCR1_WAITEN                    ((uint32_t)0x00002000)        /*!< Wait enable bit */
04603 #define  FSMC_BCR1_EXTMOD                    ((uint32_t)0x00004000)        /*!< Extended mode enable */
04604 #define  FSMC_BCR1_ASYNCWAIT                 ((uint32_t)0x00008000)       /*!< Asynchronous wait */
04605 #define  FSMC_BCR1_CBURSTRW                  ((uint32_t)0x00080000)        /*!< Write burst enable */
04606
04607 /******************  Bit definition for FSMC_BCR2 register  *******************/
04608 #define  FSMC_BCR2_MBKEN                     ((uint32_t)0x00000001)        /*!< Memory bank enable bit */
04609 #define  FSMC_BCR2_MUXEN                     ((uint32_t)0x00000002)        /*!< Address/data multiplexing enable bit */
04610
04611 #define  FSMC_BCR2_MTYP                      ((uint32_t)0x0000000C)        /*!< MTYP[1:0] bits (Memory type) */
04612 #define  FSMC_BCR2_MTYP_0                    ((uint32_t)0x00000004)        /*!< Bit 0 */
04613 #define  FSMC_BCR2_MTYP_1                    ((uint32_t)0x00000008)        /*!< Bit 1 */
04614
04615 #define  FSMC_BCR2_MWID                      ((uint32_t)0x00000030)        /*!< MWID[1:0] bits (Memory data bus width) */
04616 #define  FSMC_BCR2_MWID_0                    ((uint32_t)0x00000010)        /*!< Bit 0 */
04617 #define  FSMC_BCR2_MWID_1                    ((uint32_t)0x00000020)        /*!< Bit 1 */
04618
04619 #define  FSMC_BCR2_FACCEN                    ((uint32_t)0x00000040)        /*!< Flash access enable */
04620 #define  FSMC_BCR2_BURSTEN                   ((uint32_t)0x00000100)        /*!< Burst enable bit */
04621 #define  FSMC_BCR2_WAITPOL                   ((uint32_t)0x00000200)        /*!< Wait signal polarity bit */
04622 #define  FSMC_BCR2_WRAPMOD                   ((uint32_t)0x00000400)        /*!< Wrapped burst mode support */
04623 #define  FSMC_BCR2_WAITCFG                   ((uint32_t)0x00000800)        /*!< Wait timing configuration */
04624 #define  FSMC_BCR2_WREN                      ((uint32_t)0x00001000)        /*!< Write enable bit */
04625 #define  FSMC_BCR2_WAITEN                    ((uint32_t)0x00002000)        /*!< Wait enable bit */
04626 #define  FSMC_BCR2_EXTMOD                    ((uint32_t)0x00004000)        /*!< Extended mode enable */
04627 #define  FSMC_BCR2_ASYNCWAIT                 ((uint32_t)0x00008000)       /*!< Asynchronous wait */
04628 #define  FSMC_BCR2_CBURSTRW                  ((uint32_t)0x00080000)        /*!< Write burst enable */
04629
04630 /******************  Bit definition for FSMC_BCR3 register  *******************/
04631 #define  FSMC_BCR3_MBKEN                     ((uint32_t)0x00000001)        /*!< Memory bank enable bit */
04632 #define  FSMC_BCR3_MUXEN                     ((uint32_t)0x00000002)        /*!< Address/data multiplexing enable bit */
04633
04634 #define  FSMC_BCR3_MTYP                      ((uint32_t)0x0000000C)        /*!< MTYP[1:0] bits (Memory type) */
04635 #define  FSMC_BCR3_MTYP_0                    ((uint32_t)0x00000004)        /*!< Bit 0 */
04636 #define  FSMC_BCR3_MTYP_1                    ((uint32_t)0x00000008)        /*!< Bit 1 */
04637
04638 #define  FSMC_BCR3_MWID                      ((uint32_t)0x00000030)        /*!< MWID[1:0] bits (Memory data bus width) */
04639 #define  FSMC_BCR3_MWID_0                    ((uint32_t)0x00000010)        /*!< Bit 0 */
04640 #define  FSMC_BCR3_MWID_1                    ((uint32_t)0x00000020)        /*!< Bit 1 */
04641
04642 #define  FSMC_BCR3_FACCEN                    ((uint32_t)0x00000040)        /*!< Flash access enable */
04643 #define  FSMC_BCR3_BURSTEN                   ((uint32_t)0x00000100)        /*!< Burst enable bit */
04644 #define  FSMC_BCR3_WAITPOL                   ((uint32_t)0x00000200)        /*!< Wait signal polarity bit. */
04645 #define  FSMC_BCR3_WRAPMOD                   ((uint32_t)0x00000400)        /*!< Wrapped burst mode support */
04646 #define  FSMC_BCR3_WAITCFG                   ((uint32_t)0x00000800)        /*!< Wait timing configuration */
04647 #define  FSMC_BCR3_WREN                      ((uint32_t)0x00001000)        /*!< Write enable bit */
04648 #define  FSMC_BCR3_WAITEN                    ((uint32_t)0x00002000)        /*!< Wait enable bit */
04649 #define  FSMC_BCR3_EXTMOD                    ((uint32_t)0x00004000)        /*!< Extended mode enable */
04650 #define  FSMC_BCR3_ASYNCWAIT                 ((uint32_t)0x00008000)       /*!< Asynchronous wait */
04651 #define  FSMC_BCR3_CBURSTRW                  ((uint32_t)0x00080000)        /*!< Write burst enable */
04652
04653 /******************  Bit definition for FSMC_BCR4 register  *******************/
04654 #define  FSMC_BCR4_MBKEN                     ((uint32_t)0x00000001)        /*!< Memory bank enable bit */
04655 #define  FSMC_BCR4_MUXEN                     ((uint32_t)0x00000002)        /*!< Address/data multiplexing enable bit */
04656
04657 #define  FSMC_BCR4_MTYP                      ((uint32_t)0x0000000C)        /*!< MTYP[1:0] bits (Memory type) */
04658 #define  FSMC_BCR4_MTYP_0                    ((uint32_t)0x00000004)        /*!< Bit 0 */
04659 #define  FSMC_BCR4_MTYP_1                    ((uint32_t)0x00000008)        /*!< Bit 1 */
04660
04661 #define  FSMC_BCR4_MWID                      ((uint32_t)0x00000030)        /*!< MWID[1:0] bits (Memory data bus width) */
04662 #define  FSMC_BCR4_MWID_0                    ((uint32_t)0x00000010)        /*!< Bit 0 */
04663 #define  FSMC_BCR4_MWID_1                    ((uint32_t)0x00000020)        /*!< Bit 1 */
04664
04665 #define  FSMC_BCR4_FACCEN                    ((uint32_t)0x00000040)        /*!< Flash access enable */
04666 #define  FSMC_BCR4_BURSTEN                   ((uint32_t)0x00000100)        /*!< Burst enable bit */
04667 #define  FSMC_BCR4_WAITPOL                   ((uint32_t)0x00000200)        /*!< Wait signal polarity bit */
04668 #define  FSMC_BCR4_WRAPMOD                   ((uint32_t)0x00000400)        /*!< Wrapped burst mode support */
04669 #define  FSMC_BCR4_WAITCFG                   ((uint32_t)0x00000800)        /*!< Wait timing configuration */
04670 #define  FSMC_BCR4_WREN                      ((uint32_t)0x00001000)        /*!< Write enable bit */
04671 #define  FSMC_BCR4_WAITEN                    ((uint32_t)0x00002000)        /*!< Wait enable bit */
04672 #define  FSMC_BCR4_EXTMOD                    ((uint32_t)0x00004000)        /*!< Extended mode enable */
04673 #define  FSMC_BCR4_ASYNCWAIT                 ((uint32_t)0x00008000)       /*!< Asynchronous wait */
04674 #define  FSMC_BCR4_CBURSTRW                  ((uint32_t)0x00080000)        /*!< Write burst enable */
04675
04676 /******************  Bit definition for FSMC_BTR1 register  ******************/
04677 #define  FSMC_BTR1_ADDSET                    ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */
04678 #define  FSMC_BTR1_ADDSET_0                  ((uint32_t)0x00000001)        /*!< Bit 0 */
04679 #define  FSMC_BTR1_ADDSET_1                  ((uint32_t)0x00000002)        /*!< Bit 1 */
04680 #define  FSMC_BTR1_ADDSET_2                  ((uint32_t)0x00000004)        /*!< Bit 2 */
04681 #define  FSMC_BTR1_ADDSET_3                  ((uint32_t)0x00000008)        /*!< Bit 3 */
04682
04683 #define  FSMC_BTR1_ADDHLD                    ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
04684 #define  FSMC_BTR1_ADDHLD_0                  ((uint32_t)0x00000010)        /*!< Bit 0 */
04685 #define  FSMC_BTR1_ADDHLD_1                  ((uint32_t)0x00000020)        /*!< Bit 1 */
04686 #define  FSMC_BTR1_ADDHLD_2                  ((uint32_t)0x00000040)        /*!< Bit 2 */
04687 #define  FSMC_BTR1_ADDHLD_3                  ((uint32_t)0x00000080)        /*!< Bit 3 */
04688
04689 #define  FSMC_BTR1_DATAST                    ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */
04690 #define  FSMC_BTR1_DATAST_0                  ((uint32_t)0x00000100)        /*!< Bit 0 */
04691 #define  FSMC_BTR1_DATAST_1                  ((uint32_t)0x00000200)        /*!< Bit 1 */
04692 #define  FSMC_BTR1_DATAST_2                  ((uint32_t)0x00000400)        /*!< Bit 2 */
04693 #define  FSMC_BTR1_DATAST_3                  ((uint32_t)0x00000800)        /*!< Bit 3 */
04694
04695 #define  FSMC_BTR1_BUSTURN                   ((uint32_t)0x000F0000)        /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
04696 #define  FSMC_BTR1_BUSTURN_0                 ((uint32_t)0x00010000)        /*!< Bit 0 */
04697 #define  FSMC_BTR1_BUSTURN_1                 ((uint32_t)0x00020000)        /*!< Bit 1 */
04698 #define  FSMC_BTR1_BUSTURN_2                 ((uint32_t)0x00040000)        /*!< Bit 2 */
04699 #define  FSMC_BTR1_BUSTURN_3                 ((uint32_t)0x00080000)        /*!< Bit 3 */
04700
04701 #define  FSMC_BTR1_CLKDIV                    ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */
04702 #define  FSMC_BTR1_CLKDIV_0                  ((uint32_t)0x00100000)        /*!< Bit 0 */
04703 #define  FSMC_BTR1_CLKDIV_1                  ((uint32_t)0x00200000)        /*!< Bit 1 */
04704 #define  FSMC_BTR1_CLKDIV_2                  ((uint32_t)0x00400000)        /*!< Bit 2 */
04705 #define  FSMC_BTR1_CLKDIV_3                  ((uint32_t)0x00800000)        /*!< Bit 3 */
04706
04707 #define  FSMC_BTR1_DATLAT                    ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */
04708 #define  FSMC_BTR1_DATLAT_0                  ((uint32_t)0x01000000)        /*!< Bit 0 */
04709 #define  FSMC_BTR1_DATLAT_1                  ((uint32_t)0x02000000)        /*!< Bit 1 */
04710 #define  FSMC_BTR1_DATLAT_2                  ((uint32_t)0x04000000)        /*!< Bit 2 */
04711 #define  FSMC_BTR1_DATLAT_3                  ((uint32_t)0x08000000)        /*!< Bit 3 */
04712
04713 #define  FSMC_BTR1_ACCMOD                    ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */
04714 #define  FSMC_BTR1_ACCMOD_0                  ((uint32_t)0x10000000)        /*!< Bit 0 */
04715 #define  FSMC_BTR1_ACCMOD_1                  ((uint32_t)0x20000000)        /*!< Bit 1 */
04716
04717 /******************  Bit definition for FSMC_BTR2 register  *******************/
04718 #define  FSMC_BTR2_ADDSET                    ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */
04719 #define  FSMC_BTR2_ADDSET_0                  ((uint32_t)0x00000001)        /*!< Bit 0 */
04720 #define  FSMC_BTR2_ADDSET_1                  ((uint32_t)0x00000002)        /*!< Bit 1 */
04721 #define  FSMC_BTR2_ADDSET_2                  ((uint32_t)0x00000004)        /*!< Bit 2 */
04722 #define  FSMC_BTR2_ADDSET_3                  ((uint32_t)0x00000008)        /*!< Bit 3 */
04723
04724 #define  FSMC_BTR2_ADDHLD                    ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
04725 #define  FSMC_BTR2_ADDHLD_0                  ((uint32_t)0x00000010)        /*!< Bit 0 */
04726 #define  FSMC_BTR2_ADDHLD_1                  ((uint32_t)0x00000020)        /*!< Bit 1 */
04727 #define  FSMC_BTR2_ADDHLD_2                  ((uint32_t)0x00000040)        /*!< Bit 2 */
04728 #define  FSMC_BTR2_ADDHLD_3                  ((uint32_t)0x00000080)        /*!< Bit 3 */
04729
04730 #define  FSMC_BTR2_DATAST                    ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */
04731 #define  FSMC_BTR2_DATAST_0                  ((uint32_t)0x00000100)        /*!< Bit 0 */
04732 #define  FSMC_BTR2_DATAST_1                  ((uint32_t)0x00000200)        /*!< Bit 1 */
04733 #define  FSMC_BTR2_DATAST_2                  ((uint32_t)0x00000400)        /*!< Bit 2 */
04734 #define  FSMC_BTR2_DATAST_3                  ((uint32_t)0x00000800)        /*!< Bit 3 */
04735
04736 #define  FSMC_BTR2_BUSTURN                   ((uint32_t)0x000F0000)        /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
04737 #define  FSMC_BTR2_BUSTURN_0                 ((uint32_t)0x00010000)        /*!< Bit 0 */
04738 #define  FSMC_BTR2_BUSTURN_1                 ((uint32_t)0x00020000)        /*!< Bit 1 */
04739 #define  FSMC_BTR2_BUSTURN_2                 ((uint32_t)0x00040000)        /*!< Bit 2 */
04740 #define  FSMC_BTR2_BUSTURN_3                 ((uint32_t)0x00080000)        /*!< Bit 3 */
04741
04742 #define  FSMC_BTR2_CLKDIV                    ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */
04743 #define  FSMC_BTR2_CLKDIV_0                  ((uint32_t)0x00100000)        /*!< Bit 0 */
04744 #define  FSMC_BTR2_CLKDIV_1                  ((uint32_t)0x00200000)        /*!< Bit 1 */
04745 #define  FSMC_BTR2_CLKDIV_2                  ((uint32_t)0x00400000)        /*!< Bit 2 */
04746 #define  FSMC_BTR2_CLKDIV_3                  ((uint32_t)0x00800000)        /*!< Bit 3 */
04747
04748 #define  FSMC_BTR2_DATLAT                    ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */
04749 #define  FSMC_BTR2_DATLAT_0                  ((uint32_t)0x01000000)        /*!< Bit 0 */
04750 #define  FSMC_BTR2_DATLAT_1                  ((uint32_t)0x02000000)        /*!< Bit 1 */
04751 #define  FSMC_BTR2_DATLAT_2                  ((uint32_t)0x04000000)        /*!< Bit 2 */
04752 #define  FSMC_BTR2_DATLAT_3                  ((uint32_t)0x08000000)        /*!< Bit 3 */
04753
04754 #define  FSMC_BTR2_ACCMOD                    ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */
04755 #define  FSMC_BTR2_ACCMOD_0                  ((uint32_t)0x10000000)        /*!< Bit 0 */
04756 #define  FSMC_BTR2_ACCMOD_1                  ((uint32_t)0x20000000)        /*!< Bit 1 */
04757
04758 /*******************  Bit definition for FSMC_BTR3 register  *******************/
04759 #define  FSMC_BTR3_ADDSET                    ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */
04760 #define  FSMC_BTR3_ADDSET_0                  ((uint32_t)0x00000001)        /*!< Bit 0 */
04761 #define  FSMC_BTR3_ADDSET_1                  ((uint32_t)0x00000002)        /*!< Bit 1 */
04762 #define  FSMC_BTR3_ADDSET_2                  ((uint32_t)0x00000004)        /*!< Bit 2 */
04763 #define  FSMC_BTR3_ADDSET_3                  ((uint32_t)0x00000008)        /*!< Bit 3 */
04764
04765 #define  FSMC_BTR3_ADDHLD                    ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
04766 #define  FSMC_BTR3_ADDHLD_0                  ((uint32_t)0x00000010)        /*!< Bit 0 */
04767 #define  FSMC_BTR3_ADDHLD_1                  ((uint32_t)0x00000020)        /*!< Bit 1 */
04768 #define  FSMC_BTR3_ADDHLD_2                  ((uint32_t)0x00000040)        /*!< Bit 2 */
04769 #define  FSMC_BTR3_ADDHLD_3                  ((uint32_t)0x00000080)        /*!< Bit 3 */
04770
04771 #define  FSMC_BTR3_DATAST                    ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */
04772 #define  FSMC_BTR3_DATAST_0                  ((uint32_t)0x00000100)        /*!< Bit 0 */
04773 #define  FSMC_BTR3_DATAST_1                  ((uint32_t)0x00000200)        /*!< Bit 1 */
04774 #define  FSMC_BTR3_DATAST_2                  ((uint32_t)0x00000400)        /*!< Bit 2 */
04775 #define  FSMC_BTR3_DATAST_3                  ((uint32_t)0x00000800)        /*!< Bit 3 */
04776
04777 #define  FSMC_BTR3_BUSTURN                   ((uint32_t)0x000F0000)        /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
04778 #define  FSMC_BTR3_BUSTURN_0                 ((uint32_t)0x00010000)        /*!< Bit 0 */
04779 #define  FSMC_BTR3_BUSTURN_1                 ((uint32_t)0x00020000)        /*!< Bit 1 */
04780 #define  FSMC_BTR3_BUSTURN_2                 ((uint32_t)0x00040000)        /*!< Bit 2 */
04781 #define  FSMC_BTR3_BUSTURN_3                 ((uint32_t)0x00080000)        /*!< Bit 3 */
04782
04783 #define  FSMC_BTR3_CLKDIV                    ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */
04784 #define  FSMC_BTR3_CLKDIV_0                  ((uint32_t)0x00100000)        /*!< Bit 0 */
04785 #define  FSMC_BTR3_CLKDIV_1                  ((uint32_t)0x00200000)        /*!< Bit 1 */
04786 #define  FSMC_BTR3_CLKDIV_2                  ((uint32_t)0x00400000)        /*!< Bit 2 */
04787 #define  FSMC_BTR3_CLKDIV_3                  ((uint32_t)0x00800000)        /*!< Bit 3 */
04788
04789 #define  FSMC_BTR3_DATLAT                    ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */
04790 #define  FSMC_BTR3_DATLAT_0                  ((uint32_t)0x01000000)        /*!< Bit 0 */
04791 #define  FSMC_BTR3_DATLAT_1                  ((uint32_t)0x02000000)        /*!< Bit 1 */
04792 #define  FSMC_BTR3_DATLAT_2                  ((uint32_t)0x04000000)        /*!< Bit 2 */
04793 #define  FSMC_BTR3_DATLAT_3                  ((uint32_t)0x08000000)        /*!< Bit 3 */
04794
04795 #define  FSMC_BTR3_ACCMOD                    ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */
04796 #define  FSMC_BTR3_ACCMOD_0                  ((uint32_t)0x10000000)        /*!< Bit 0 */
04797 #define  FSMC_BTR3_ACCMOD_1                  ((uint32_t)0x20000000)        /*!< Bit 1 */
04798
04799 /******************  Bit definition for FSMC_BTR4 register  *******************/
04800 #define  FSMC_BTR4_ADDSET                    ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */
04801 #define  FSMC_BTR4_ADDSET_0                  ((uint32_t)0x00000001)        /*!< Bit 0 */
04802 #define  FSMC_BTR4_ADDSET_1                  ((uint32_t)0x00000002)        /*!< Bit 1 */
04803 #define  FSMC_BTR4_ADDSET_2                  ((uint32_t)0x00000004)        /*!< Bit 2 */
04804 #define  FSMC_BTR4_ADDSET_3                  ((uint32_t)0x00000008)        /*!< Bit 3 */
04805
04806 #define  FSMC_BTR4_ADDHLD                    ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
04807 #define  FSMC_BTR4_ADDHLD_0                  ((uint32_t)0x00000010)        /*!< Bit 0 */
04808 #define  FSMC_BTR4_ADDHLD_1                  ((uint32_t)0x00000020)        /*!< Bit 1 */
04809 #define  FSMC_BTR4_ADDHLD_2                  ((uint32_t)0x00000040)        /*!< Bit 2 */
04810 #define  FSMC_BTR4_ADDHLD_3                  ((uint32_t)0x00000080)        /*!< Bit 3 */
04811
04812 #define  FSMC_BTR4_DATAST                    ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */
04813 #define  FSMC_BTR4_DATAST_0                  ((uint32_t)0x00000100)        /*!< Bit 0 */
04814 #define  FSMC_BTR4_DATAST_1                  ((uint32_t)0x00000200)        /*!< Bit 1 */
04815 #define  FSMC_BTR4_DATAST_2                  ((uint32_t)0x00000400)        /*!< Bit 2 */
04816 #define  FSMC_BTR4_DATAST_3                  ((uint32_t)0x00000800)        /*!< Bit 3 */
04817
04818 #define  FSMC_BTR4_BUSTURN                   ((uint32_t)0x000F0000)        /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
04819 #define  FSMC_BTR4_BUSTURN_0                 ((uint32_t)0x00010000)        /*!< Bit 0 */
04820 #define  FSMC_BTR4_BUSTURN_1                 ((uint32_t)0x00020000)        /*!< Bit 1 */
04821 #define  FSMC_BTR4_BUSTURN_2                 ((uint32_t)0x00040000)        /*!< Bit 2 */
04822 #define  FSMC_BTR4_BUSTURN_3                 ((uint32_t)0x00080000)        /*!< Bit 3 */
04823
04824 #define  FSMC_BTR4_CLKDIV                    ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */
04825 #define  FSMC_BTR4_CLKDIV_0                  ((uint32_t)0x00100000)        /*!< Bit 0 */
04826 #define  FSMC_BTR4_CLKDIV_1                  ((uint32_t)0x00200000)        /*!< Bit 1 */
04827 #define  FSMC_BTR4_CLKDIV_2                  ((uint32_t)0x00400000)        /*!< Bit 2 */
04828 #define  FSMC_BTR4_CLKDIV_3                  ((uint32_t)0x00800000)        /*!< Bit 3 */
04829
04830 #define  FSMC_BTR4_DATLAT                    ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */
04831 #define  FSMC_BTR4_DATLAT_0                  ((uint32_t)0x01000000)        /*!< Bit 0 */
04832 #define  FSMC_BTR4_DATLAT_1                  ((uint32_t)0x02000000)        /*!< Bit 1 */
04833 #define  FSMC_BTR4_DATLAT_2                  ((uint32_t)0x04000000)        /*!< Bit 2 */
04834 #define  FSMC_BTR4_DATLAT_3                  ((uint32_t)0x08000000)        /*!< Bit 3 */
04835
04836 #define  FSMC_BTR4_ACCMOD                    ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */
04837 #define  FSMC_BTR4_ACCMOD_0                  ((uint32_t)0x10000000)        /*!< Bit 0 */
04838 #define  FSMC_BTR4_ACCMOD_1                  ((uint32_t)0x20000000)        /*!< Bit 1 */
04839
04840 /******************  Bit definition for FSMC_BWTR1 register  ******************/
04841 #define  FSMC_BWTR1_ADDSET                   ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */
04842 #define  FSMC_BWTR1_ADDSET_0                 ((uint32_t)0x00000001)        /*!< Bit 0 */
04843 #define  FSMC_BWTR1_ADDSET_1                 ((uint32_t)0x00000002)        /*!< Bit 1 */
04844 #define  FSMC_BWTR1_ADDSET_2                 ((uint32_t)0x00000004)        /*!< Bit 2 */
04845 #define  FSMC_BWTR1_ADDSET_3                 ((uint32_t)0x00000008)        /*!< Bit 3 */
04846
04847 #define  FSMC_BWTR1_ADDHLD                   ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
04848 #define  FSMC_BWTR1_ADDHLD_0                 ((uint32_t)0x00000010)        /*!< Bit 0 */
04849 #define  FSMC_BWTR1_ADDHLD_1                 ((uint32_t)0x00000020)        /*!< Bit 1 */
04850 #define  FSMC_BWTR1_ADDHLD_2                 ((uint32_t)0x00000040)        /*!< Bit 2 */
04851 #define  FSMC_BWTR1_ADDHLD_3                 ((uint32_t)0x00000080)        /*!< Bit 3 */
04852
04853 #define  FSMC_BWTR1_DATAST                   ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */
04854 #define  FSMC_BWTR1_DATAST_0                 ((uint32_t)0x00000100)        /*!< Bit 0 */
04855 #define  FSMC_BWTR1_DATAST_1                 ((uint32_t)0x00000200)        /*!< Bit 1 */
04856 #define  FSMC_BWTR1_DATAST_2                 ((uint32_t)0x00000400)        /*!< Bit 2 */
04857 #define  FSMC_BWTR1_DATAST_3                 ((uint32_t)0x00000800)        /*!< Bit 3 */
04858
04859 #define  FSMC_BWTR1_CLKDIV                   ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */
04860 #define  FSMC_BWTR1_CLKDIV_0                 ((uint32_t)0x00100000)        /*!< Bit 0 */
04861 #define  FSMC_BWTR1_CLKDIV_1                 ((uint32_t)0x00200000)        /*!< Bit 1 */
04862 #define  FSMC_BWTR1_CLKDIV_2                 ((uint32_t)0x00400000)        /*!< Bit 2 */
04863 #define  FSMC_BWTR1_CLKDIV_3                 ((uint32_t)0x00800000)        /*!< Bit 3 */
04864
04865 #define  FSMC_BWTR1_DATLAT                   ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */
04866 #define  FSMC_BWTR1_DATLAT_0                 ((uint32_t)0x01000000)        /*!< Bit 0 */
04867 #define  FSMC_BWTR1_DATLAT_1                 ((uint32_t)0x02000000)        /*!< Bit 1 */
04868 #define  FSMC_BWTR1_DATLAT_2                 ((uint32_t)0x04000000)        /*!< Bit 2 */
04869 #define  FSMC_BWTR1_DATLAT_3                 ((uint32_t)0x08000000)        /*!< Bit 3 */
04870
04871 #define  FSMC_BWTR1_ACCMOD                   ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */
04872 #define  FSMC_BWTR1_ACCMOD_0                 ((uint32_t)0x10000000)        /*!< Bit 0 */
04873 #define  FSMC_BWTR1_ACCMOD_1                 ((uint32_t)0x20000000)        /*!< Bit 1 */
04874
04875 /******************  Bit definition for FSMC_BWTR2 register  ******************/
04876 #define  FSMC_BWTR2_ADDSET                   ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */
04877 #define  FSMC_BWTR2_ADDSET_0                 ((uint32_t)0x00000001)        /*!< Bit 0 */
04878 #define  FSMC_BWTR2_ADDSET_1                 ((uint32_t)0x00000002)        /*!< Bit 1 */
04879 #define  FSMC_BWTR2_ADDSET_2                 ((uint32_t)0x00000004)        /*!< Bit 2 */
04880 #define  FSMC_BWTR2_ADDSET_3                 ((uint32_t)0x00000008)        /*!< Bit 3 */
04881
04882 #define  FSMC_BWTR2_ADDHLD                   ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
04883 #define  FSMC_BWTR2_ADDHLD_0                 ((uint32_t)0x00000010)        /*!< Bit 0 */
04884 #define  FSMC_BWTR2_ADDHLD_1                 ((uint32_t)0x00000020)        /*!< Bit 1 */
04885 #define  FSMC_BWTR2_ADDHLD_2                 ((uint32_t)0x00000040)        /*!< Bit 2 */
04886 #define  FSMC_BWTR2_ADDHLD_3                 ((uint32_t)0x00000080)        /*!< Bit 3 */
04887
04888 #define  FSMC_BWTR2_DATAST                   ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */
04889 #define  FSMC_BWTR2_DATAST_0                 ((uint32_t)0x00000100)        /*!< Bit 0 */
04890 #define  FSMC_BWTR2_DATAST_1                 ((uint32_t)0x00000200)        /*!< Bit 1 */
04891 #define  FSMC_BWTR2_DATAST_2                 ((uint32_t)0x00000400)        /*!< Bit 2 */
04892 #define  FSMC_BWTR2_DATAST_3                 ((uint32_t)0x00000800)        /*!< Bit 3 */
04893
04894 #define  FSMC_BWTR2_CLKDIV                   ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */
04895 #define  FSMC_BWTR2_CLKDIV_0                 ((uint32_t)0x00100000)        /*!< Bit 0 */
04896 #define  FSMC_BWTR2_CLKDIV_1                 ((uint32_t)0x00200000)        /*!< Bit 1*/
04897 #define  FSMC_BWTR2_CLKDIV_2                 ((uint32_t)0x00400000)        /*!< Bit 2 */
04898 #define  FSMC_BWTR2_CLKDIV_3                 ((uint32_t)0x00800000)        /*!< Bit 3 */
04899
04900 #define  FSMC_BWTR2_DATLAT                   ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */
04901 #define  FSMC_BWTR2_DATLAT_0                 ((uint32_t)0x01000000)        /*!< Bit 0 */
04902 #define  FSMC_BWTR2_DATLAT_1                 ((uint32_t)0x02000000)        /*!< Bit 1 */
04903 #define  FSMC_BWTR2_DATLAT_2                 ((uint32_t)0x04000000)        /*!< Bit 2 */
04904 #define  FSMC_BWTR2_DATLAT_3                 ((uint32_t)0x08000000)        /*!< Bit 3 */
04905
04906 #define  FSMC_BWTR2_ACCMOD                   ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */
04907 #define  FSMC_BWTR2_ACCMOD_0                 ((uint32_t)0x10000000)        /*!< Bit 0 */
04908 #define  FSMC_BWTR2_ACCMOD_1                 ((uint32_t)0x20000000)        /*!< Bit 1 */
04909
04910 /******************  Bit definition for FSMC_BWTR3 register  ******************/
04911 #define  FSMC_BWTR3_ADDSET                   ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */
04912 #define  FSMC_BWTR3_ADDSET_0                 ((uint32_t)0x00000001)        /*!< Bit 0 */
04913 #define  FSMC_BWTR3_ADDSET_1                 ((uint32_t)0x00000002)        /*!< Bit 1 */
04914 #define  FSMC_BWTR3_ADDSET_2                 ((uint32_t)0x00000004)        /*!< Bit 2 */
04915 #define  FSMC_BWTR3_ADDSET_3                 ((uint32_t)0x00000008)        /*!< Bit 3 */
04916
04917 #define  FSMC_BWTR3_ADDHLD                   ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
04918 #define  FSMC_BWTR3_ADDHLD_0                 ((uint32_t)0x00000010)        /*!< Bit 0 */
04919 #define  FSMC_BWTR3_ADDHLD_1                 ((uint32_t)0x00000020)        /*!< Bit 1 */
04920 #define  FSMC_BWTR3_ADDHLD_2                 ((uint32_t)0x00000040)        /*!< Bit 2 */
04921 #define  FSMC_BWTR3_ADDHLD_3                 ((uint32_t)0x00000080)        /*!< Bit 3 */
04922
04923 #define  FSMC_BWTR3_DATAST                   ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */
04924 #define  FSMC_BWTR3_DATAST_0                 ((uint32_t)0x00000100)        /*!< Bit 0 */
04925 #define  FSMC_BWTR3_DATAST_1                 ((uint32_t)0x00000200)        /*!< Bit 1 */
04926 #define  FSMC_BWTR3_DATAST_2                 ((uint32_t)0x00000400)        /*!< Bit 2 */
04927 #define  FSMC_BWTR3_DATAST_3                 ((uint32_t)0x00000800)        /*!< Bit 3 */
04928
04929 #define  FSMC_BWTR3_CLKDIV                   ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */
04930 #define  FSMC_BWTR3_CLKDIV_0                 ((uint32_t)0x00100000)        /*!< Bit 0 */
04931 #define  FSMC_BWTR3_CLKDIV_1                 ((uint32_t)0x00200000)        /*!< Bit 1 */
04932 #define  FSMC_BWTR3_CLKDIV_2                 ((uint32_t)0x00400000)        /*!< Bit 2 */
04933 #define  FSMC_BWTR3_CLKDIV_3                 ((uint32_t)0x00800000)        /*!< Bit 3 */
04934
04935 #define  FSMC_BWTR3_DATLAT                   ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */
04936 #define  FSMC_BWTR3_DATLAT_0                 ((uint32_t)0x01000000)        /*!< Bit 0 */
04937 #define  FSMC_BWTR3_DATLAT_1                 ((uint32_t)0x02000000)        /*!< Bit 1 */
04938 #define  FSMC_BWTR3_DATLAT_2                 ((uint32_t)0x04000000)        /*!< Bit 2 */
04939 #define  FSMC_BWTR3_DATLAT_3                 ((uint32_t)0x08000000)        /*!< Bit 3 */
04940
04941 #define  FSMC_BWTR3_ACCMOD                   ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */
04942 #define  FSMC_BWTR3_ACCMOD_0                 ((uint32_t)0x10000000)        /*!< Bit 0 */
04943 #define  FSMC_BWTR3_ACCMOD_1                 ((uint32_t)0x20000000)        /*!< Bit 1 */
04944
04945 /******************  Bit definition for FSMC_BWTR4 register  ******************/
04946 #define  FSMC_BWTR4_ADDSET                   ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */
04947 #define  FSMC_BWTR4_ADDSET_0                 ((uint32_t)0x00000001)        /*!< Bit 0 */
04948 #define  FSMC_BWTR4_ADDSET_1                 ((uint32_t)0x00000002)        /*!< Bit 1 */
04949 #define  FSMC_BWTR4_ADDSET_2                 ((uint32_t)0x00000004)        /*!< Bit 2 */
04950 #define  FSMC_BWTR4_ADDSET_3                 ((uint32_t)0x00000008)        /*!< Bit 3 */
04951
04952 #define  FSMC_BWTR4_ADDHLD                   ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
04953 #define  FSMC_BWTR4_ADDHLD_0                 ((uint32_t)0x00000010)        /*!< Bit 0 */
04954 #define  FSMC_BWTR4_ADDHLD_1                 ((uint32_t)0x00000020)        /*!< Bit 1 */
04955 #define  FSMC_BWTR4_ADDHLD_2                 ((uint32_t)0x00000040)        /*!< Bit 2 */
04956 #define  FSMC_BWTR4_ADDHLD_3                 ((uint32_t)0x00000080)        /*!< Bit 3 */
04957
04958 #define  FSMC_BWTR4_DATAST                   ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */
04959 #define  FSMC_BWTR4_DATAST_0                 ((uint32_t)0x00000100)        /*!< Bit 0 */
04960 #define  FSMC_BWTR4_DATAST_1                 ((uint32_t)0x00000200)        /*!< Bit 1 */
04961 #define  FSMC_BWTR4_DATAST_2                 ((uint32_t)0x00000400)        /*!< Bit 2 */
04962 #define  FSMC_BWTR4_DATAST_3                 ((uint32_t)0x00000800)        /*!< Bit 3 */
04963
04964 #define  FSMC_BWTR4_CLKDIV                   ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */
04965 #define  FSMC_BWTR4_CLKDIV_0                 ((uint32_t)0x00100000)        /*!< Bit 0 */
04966 #define  FSMC_BWTR4_CLKDIV_1                 ((uint32_t)0x00200000)        /*!< Bit 1 */
04967 #define  FSMC_BWTR4_CLKDIV_2                 ((uint32_t)0x00400000)        /*!< Bit 2 */
04968 #define  FSMC_BWTR4_CLKDIV_3                 ((uint32_t)0x00800000)        /*!< Bit 3 */
04969
04970 #define  FSMC_BWTR4_DATLAT                   ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */
04971 #define  FSMC_BWTR4_DATLAT_0                 ((uint32_t)0x01000000)        /*!< Bit 0 */
04972 #define  FSMC_BWTR4_DATLAT_1                 ((uint32_t)0x02000000)        /*!< Bit 1 */
04973 #define  FSMC_BWTR4_DATLAT_2                 ((uint32_t)0x04000000)        /*!< Bit 2 */
04974 #define  FSMC_BWTR4_DATLAT_3                 ((uint32_t)0x08000000)        /*!< Bit 3 */
04975
04976 #define  FSMC_BWTR4_ACCMOD                   ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */
04977 #define  FSMC_BWTR4_ACCMOD_0                 ((uint32_t)0x10000000)        /*!< Bit 0 */
04978 #define  FSMC_BWTR4_ACCMOD_1                 ((uint32_t)0x20000000)        /*!< Bit 1 */
04979
04980 /******************  Bit definition for FSMC_PCR2 register  *******************/
04981 #define  FSMC_PCR2_PWAITEN                   ((uint32_t)0x00000002)        /*!< Wait feature enable bit */
04982 #define  FSMC_PCR2_PBKEN                     ((uint32_t)0x00000004)        /*!< PC Card/NAND Flash memory bank enable bit */
04983 #define  FSMC_PCR2_PTYP                      ((uint32_t)0x00000008)        /*!< Memory type */
04984
04985 #define  FSMC_PCR2_PWID                      ((uint32_t)0x00000030)        /*!< PWID[1:0] bits (NAND Flash databus width) */
04986 #define  FSMC_PCR2_PWID_0                    ((uint32_t)0x00000010)        /*!< Bit 0 */
04987 #define  FSMC_PCR2_PWID_1                    ((uint32_t)0x00000020)        /*!< Bit 1 */
04988
04989 #define  FSMC_PCR2_ECCEN                     ((uint32_t)0x00000040)        /*!< ECC computation logic enable bit */
04990
04991 #define  FSMC_PCR2_TCLR                      ((uint32_t)0x00001E00)        /*!< TCLR[3:0] bits (CLE to RE delay) */
04992 #define  FSMC_PCR2_TCLR_0                    ((uint32_t)0x00000200)        /*!< Bit 0 */
04993 #define  FSMC_PCR2_TCLR_1                    ((uint32_t)0x00000400)        /*!< Bit 1 */
04994 #define  FSMC_PCR2_TCLR_2                    ((uint32_t)0x00000800)        /*!< Bit 2 */
04995 #define  FSMC_PCR2_TCLR_3                    ((uint32_t)0x00001000)        /*!< Bit 3 */
04996
04997 #define  FSMC_PCR2_TAR                       ((uint32_t)0x0001E000)        /*!< TAR[3:0] bits (ALE to RE delay) */
04998 #define  FSMC_PCR2_TAR_0                     ((uint32_t)0x00002000)        /*!< Bit 0 */
04999 #define  FSMC_PCR2_TAR_1                     ((uint32_t)0x00004000)        /*!< Bit 1 */
05000 #define  FSMC_PCR2_TAR_2                     ((uint32_t)0x00008000)        /*!< Bit 2 */
05001 #define  FSMC_PCR2_TAR_3                     ((uint32_t)0x00010000)        /*!< Bit 3 */
05002
05003 #define  FSMC_PCR2_ECCPS                     ((uint32_t)0x000E0000)        /*!< ECCPS[1:0] bits (ECC page size) */
05004 #define  FSMC_PCR2_ECCPS_0                   ((uint32_t)0x00020000)        /*!< Bit 0 */
05005 #define  FSMC_PCR2_ECCPS_1                   ((uint32_t)0x00040000)        /*!< Bit 1 */
05006 #define  FSMC_PCR2_ECCPS_2                   ((uint32_t)0x00080000)        /*!< Bit 2 */
05007
05008 /******************  Bit definition for FSMC_PCR3 register  *******************/
05009 #define  FSMC_PCR3_PWAITEN                   ((uint32_t)0x00000002)        /*!< Wait feature enable bit */
05010 #define  FSMC_PCR3_PBKEN                     ((uint32_t)0x00000004)        /*!< PC Card/NAND Flash memory bank enable bit */
05011 #define  FSMC_PCR3_PTYP                      ((uint32_t)0x00000008)        /*!< Memory type */
05012
05013 #define  FSMC_PCR3_PWID                      ((uint32_t)0x00000030)        /*!< PWID[1:0] bits (NAND Flash databus width) */
05014 #define  FSMC_PCR3_PWID_0                    ((uint32_t)0x00000010)        /*!< Bit 0 */
05015 #define  FSMC_PCR3_PWID_1                    ((uint32_t)0x00000020)        /*!< Bit 1 */
05016
05017 #define  FSMC_PCR3_ECCEN                     ((uint32_t)0x00000040)        /*!< ECC computation logic enable bit */
05018
05019 #define  FSMC_PCR3_TCLR                      ((uint32_t)0x00001E00)        /*!< TCLR[3:0] bits (CLE to RE delay) */
05020 #define  FSMC_PCR3_TCLR_0                    ((uint32_t)0x00000200)        /*!< Bit 0 */
05021 #define  FSMC_PCR3_TCLR_1                    ((uint32_t)0x00000400)        /*!< Bit 1 */
05022 #define  FSMC_PCR3_TCLR_2                    ((uint32_t)0x00000800)        /*!< Bit 2 */
05023 #define  FSMC_PCR3_TCLR_3                    ((uint32_t)0x00001000)        /*!< Bit 3 */
05024
05025 #define  FSMC_PCR3_TAR                       ((uint32_t)0x0001E000)        /*!< TAR[3:0] bits (ALE to RE delay) */
05026 #define  FSMC_PCR3_TAR_0                     ((uint32_t)0x00002000)        /*!< Bit 0 */
05027 #define  FSMC_PCR3_TAR_1                     ((uint32_t)0x00004000)        /*!< Bit 1 */
05028 #define  FSMC_PCR3_TAR_2                     ((uint32_t)0x00008000)        /*!< Bit 2 */
05029 #define  FSMC_PCR3_TAR_3                     ((uint32_t)0x00010000)        /*!< Bit 3 */
05030
05031 #define  FSMC_PCR3_ECCPS                     ((uint32_t)0x000E0000)        /*!< ECCPS[2:0] bits (ECC page size) */
05032 #define  FSMC_PCR3_ECCPS_0                   ((uint32_t)0x00020000)        /*!< Bit 0 */
05033 #define  FSMC_PCR3_ECCPS_1                   ((uint32_t)0x00040000)        /*!< Bit 1 */
05034 #define  FSMC_PCR3_ECCPS_2                   ((uint32_t)0x00080000)        /*!< Bit 2 */
05035
05036 /******************  Bit definition for FSMC_PCR4 register  *******************/
05037 #define  FSMC_PCR4_PWAITEN                   ((uint32_t)0x00000002)        /*!< Wait feature enable bit */
05038 #define  FSMC_PCR4_PBKEN                     ((uint32_t)0x00000004)        /*!< PC Card/NAND Flash memory bank enable bit */
05039 #define  FSMC_PCR4_PTYP                      ((uint32_t)0x00000008)        /*!< Memory type */
05040
05041 #define  FSMC_PCR4_PWID                      ((uint32_t)0x00000030)        /*!< PWID[1:0] bits (NAND Flash databus width) */
05042 #define  FSMC_PCR4_PWID_0                    ((uint32_t)0x00000010)        /*!< Bit 0 */
05043 #define  FSMC_PCR4_PWID_1                    ((uint32_t)0x00000020)        /*!< Bit 1 */
05044
05045 #define  FSMC_PCR4_ECCEN                     ((uint32_t)0x00000040)        /*!< ECC computation logic enable bit */
05046
05047 #define  FSMC_PCR4_TCLR                      ((uint32_t)0x00001E00)        /*!< TCLR[3:0] bits (CLE to RE delay) */
05048 #define  FSMC_PCR4_TCLR_0                    ((uint32_t)0x00000200)        /*!< Bit 0 */
05049 #define  FSMC_PCR4_TCLR_1                    ((uint32_t)0x00000400)        /*!< Bit 1 */
05050 #define  FSMC_PCR4_TCLR_2                    ((uint32_t)0x00000800)        /*!< Bit 2 */
05051 #define  FSMC_PCR4_TCLR_3                    ((uint32_t)0x00001000)        /*!< Bit 3 */
05052
05053 #define  FSMC_PCR4_TAR                       ((uint32_t)0x0001E000)        /*!< TAR[3:0] bits (ALE to RE delay) */
05054 #define  FSMC_PCR4_TAR_0                     ((uint32_t)0x00002000)        /*!< Bit 0 */
05055 #define  FSMC_PCR4_TAR_1                     ((uint32_t)0x00004000)        /*!< Bit 1 */
05056 #define  FSMC_PCR4_TAR_2                     ((uint32_t)0x00008000)        /*!< Bit 2 */
05057 #define  FSMC_PCR4_TAR_3                     ((uint32_t)0x00010000)        /*!< Bit 3 */
05058
05059 #define  FSMC_PCR4_ECCPS                     ((uint32_t)0x000E0000)        /*!< ECCPS[2:0] bits (ECC page size) */
05060 #define  FSMC_PCR4_ECCPS_0                   ((uint32_t)0x00020000)        /*!< Bit 0 */
05061 #define  FSMC_PCR4_ECCPS_1                   ((uint32_t)0x00040000)        /*!< Bit 1 */
05062 #define  FSMC_PCR4_ECCPS_2                   ((uint32_t)0x00080000)        /*!< Bit 2 */
05063
05064 /*******************  Bit definition for FSMC_SR2 register  *******************/
05065 #define  FSMC_SR2_IRS                        ((uint8_t)0x01)               /*!< Interrupt Rising Edge status */
05066 #define  FSMC_SR2_ILS                        ((uint8_t)0x02)               /*!< Interrupt Level status */
05067 #define  FSMC_SR2_IFS                        ((uint8_t)0x04)               /*!< Interrupt Falling Edge status */
05068 #define  FSMC_SR2_IREN                       ((uint8_t)0x08)               /*!< Interrupt Rising Edge detection Enable bit */
05069 #define  FSMC_SR2_ILEN                       ((uint8_t)0x10)               /*!< Interrupt Level detection Enable bit */
05070 #define  FSMC_SR2_IFEN                       ((uint8_t)0x20)               /*!< Interrupt Falling Edge detection Enable bit */
05071 #define  FSMC_SR2_FEMPT                      ((uint8_t)0x40)               /*!< FIFO empty */
05072
05073 /*******************  Bit definition for FSMC_SR3 register  *******************/
05074 #define  FSMC_SR3_IRS                        ((uint8_t)0x01)               /*!< Interrupt Rising Edge status */
05075 #define  FSMC_SR3_ILS                        ((uint8_t)0x02)               /*!< Interrupt Level status */
05076 #define  FSMC_SR3_IFS                        ((uint8_t)0x04)               /*!< Interrupt Falling Edge status */
05077 #define  FSMC_SR3_IREN                       ((uint8_t)0x08)               /*!< Interrupt Rising Edge detection Enable bit */
05078 #define  FSMC_SR3_ILEN                       ((uint8_t)0x10)               /*!< Interrupt Level detection Enable bit */
05079 #define  FSMC_SR3_IFEN                       ((uint8_t)0x20)               /*!< Interrupt Falling Edge detection Enable bit */
05080 #define  FSMC_SR3_FEMPT                      ((uint8_t)0x40)               /*!< FIFO empty */
05081
05082 /*******************  Bit definition for FSMC_SR4 register  *******************/
05083 #define  FSMC_SR4_IRS                        ((uint8_t)0x01)               /*!< Interrupt Rising Edge status */
05084 #define  FSMC_SR4_ILS                        ((uint8_t)0x02)               /*!< Interrupt Level status */
05085 #define  FSMC_SR4_IFS                        ((uint8_t)0x04)               /*!< Interrupt Falling Edge status */
05086 #define  FSMC_SR4_IREN                       ((uint8_t)0x08)               /*!< Interrupt Rising Edge detection Enable bit */
05087 #define  FSMC_SR4_ILEN                       ((uint8_t)0x10)               /*!< Interrupt Level detection Enable bit */
05088 #define  FSMC_SR4_IFEN                       ((uint8_t)0x20)               /*!< Interrupt Falling Edge detection Enable bit */
05089 #define  FSMC_SR4_FEMPT                      ((uint8_t)0x40)               /*!< FIFO empty */
05090
05091 /******************  Bit definition for FSMC_PMEM2 register  ******************/
05092 #define  FSMC_PMEM2_MEMSET2                  ((uint32_t)0x000000FF)        /*!< MEMSET2[7:0] bits (Common memory 2 setup time) */
05093 #define  FSMC_PMEM2_MEMSET2_0                ((uint32_t)0x00000001)        /*!< Bit 0 */
05094 #define  FSMC_PMEM2_MEMSET2_1                ((uint32_t)0x00000002)        /*!< Bit 1 */
05095 #define  FSMC_PMEM2_MEMSET2_2                ((uint32_t)0x00000004)        /*!< Bit 2 */
05096 #define  FSMC_PMEM2_MEMSET2_3                ((uint32_t)0x00000008)        /*!< Bit 3 */
05097 #define  FSMC_PMEM2_MEMSET2_4                ((uint32_t)0x00000010)        /*!< Bit 4 */
05098 #define  FSMC_PMEM2_MEMSET2_5                ((uint32_t)0x00000020)        /*!< Bit 5 */
05099 #define  FSMC_PMEM2_MEMSET2_6                ((uint32_t)0x00000040)        /*!< Bit 6 */
05100 #define  FSMC_PMEM2_MEMSET2_7                ((uint32_t)0x00000080)        /*!< Bit 7 */
05101
05102 #define  FSMC_PMEM2_MEMWAIT2                 ((uint32_t)0x0000FF00)        /*!< MEMWAIT2[7:0] bits (Common memory 2 wait time) */
05103 #define  FSMC_PMEM2_MEMWAIT2_0               ((uint32_t)0x00000100)        /*!< Bit 0 */
05104 #define  FSMC_PMEM2_MEMWAIT2_1               ((uint32_t)0x00000200)        /*!< Bit 1 */
05105 #define  FSMC_PMEM2_MEMWAIT2_2               ((uint32_t)0x00000400)        /*!< Bit 2 */
05106 #define  FSMC_PMEM2_MEMWAIT2_3               ((uint32_t)0x00000800)        /*!< Bit 3 */
05107 #define  FSMC_PMEM2_MEMWAIT2_4               ((uint32_t)0x00001000)        /*!< Bit 4 */
05108 #define  FSMC_PMEM2_MEMWAIT2_5               ((uint32_t)0x00002000)        /*!< Bit 5 */
05109 #define  FSMC_PMEM2_MEMWAIT2_6               ((uint32_t)0x00004000)        /*!< Bit 6 */
05110 #define  FSMC_PMEM2_MEMWAIT2_7               ((uint32_t)0x00008000)        /*!< Bit 7 */
05111
05112 #define  FSMC_PMEM2_MEMHOLD2                 ((uint32_t)0x00FF0000)        /*!< MEMHOLD2[7:0] bits (Common memory 2 hold time) */
05113 #define  FSMC_PMEM2_MEMHOLD2_0               ((uint32_t)0x00010000)        /*!< Bit 0 */
05114 #define  FSMC_PMEM2_MEMHOLD2_1               ((uint32_t)0x00020000)        /*!< Bit 1 */
05115 #define  FSMC_PMEM2_MEMHOLD2_2               ((uint32_t)0x00040000)        /*!< Bit 2 */
05116 #define  FSMC_PMEM2_MEMHOLD2_3               ((uint32_t)0x00080000)        /*!< Bit 3 */
05117 #define  FSMC_PMEM2_MEMHOLD2_4               ((uint32_t)0x00100000)        /*!< Bit 4 */
05118 #define  FSMC_PMEM2_MEMHOLD2_5               ((uint32_t)0x00200000)        /*!< Bit 5 */
05119 #define  FSMC_PMEM2_MEMHOLD2_6               ((uint32_t)0x00400000)        /*!< Bit 6 */
05120 #define  FSMC_PMEM2_MEMHOLD2_7               ((uint32_t)0x00800000)        /*!< Bit 7 */
05121
05122 #define  FSMC_PMEM2_MEMHIZ2                  ((uint32_t)0xFF000000)        /*!< MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
05123 #define  FSMC_PMEM2_MEMHIZ2_0                ((uint32_t)0x01000000)        /*!< Bit 0 */
05124 #define  FSMC_PMEM2_MEMHIZ2_1                ((uint32_t)0x02000000)        /*!< Bit 1 */
05125 #define  FSMC_PMEM2_MEMHIZ2_2                ((uint32_t)0x04000000)        /*!< Bit 2 */
05126 #define  FSMC_PMEM2_MEMHIZ2_3                ((uint32_t)0x08000000)        /*!< Bit 3 */
05127 #define  FSMC_PMEM2_MEMHIZ2_4                ((uint32_t)0x10000000)        /*!< Bit 4 */
05128 #define  FSMC_PMEM2_MEMHIZ2_5                ((uint32_t)0x20000000)        /*!< Bit 5 */
05129 #define  FSMC_PMEM2_MEMHIZ2_6                ((uint32_t)0x40000000)        /*!< Bit 6 */
05130 #define  FSMC_PMEM2_MEMHIZ2_7                ((uint32_t)0x80000000)        /*!< Bit 7 */
05131
05132 /******************  Bit definition for FSMC_PMEM3 register  ******************/
05133 #define  FSMC_PMEM3_MEMSET3                  ((uint32_t)0x000000FF)        /*!< MEMSET3[7:0] bits (Common memory 3 setup time) */
05134 #define  FSMC_PMEM3_MEMSET3_0                ((uint32_t)0x00000001)        /*!< Bit 0 */
05135 #define  FSMC_PMEM3_MEMSET3_1                ((uint32_t)0x00000002)        /*!< Bit 1 */
05136 #define  FSMC_PMEM3_MEMSET3_2                ((uint32_t)0x00000004)        /*!< Bit 2 */
05137 #define  FSMC_PMEM3_MEMSET3_3                ((uint32_t)0x00000008)        /*!< Bit 3 */
05138 #define  FSMC_PMEM3_MEMSET3_4                ((uint32_t)0x00000010)        /*!< Bit 4 */
05139 #define  FSMC_PMEM3_MEMSET3_5                ((uint32_t)0x00000020)        /*!< Bit 5 */
05140 #define  FSMC_PMEM3_MEMSET3_6                ((uint32_t)0x00000040)        /*!< Bit 6 */
05141 #define  FSMC_PMEM3_MEMSET3_7                ((uint32_t)0x00000080)        /*!< Bit 7 */
05142
05143 #define  FSMC_PMEM3_MEMWAIT3                 ((uint32_t)0x0000FF00)        /*!< MEMWAIT3[7:0] bits (Common memory 3 wait time) */
05144 #define  FSMC_PMEM3_MEMWAIT3_0               ((uint32_t)0x00000100)        /*!< Bit 0 */
05145 #define  FSMC_PMEM3_MEMWAIT3_1               ((uint32_t)0x00000200)        /*!< Bit 1 */
05146 #define  FSMC_PMEM3_MEMWAIT3_2               ((uint32_t)0x00000400)        /*!< Bit 2 */
05147 #define  FSMC_PMEM3_MEMWAIT3_3               ((uint32_t)0x00000800)        /*!< Bit 3 */
05148 #define  FSMC_PMEM3_MEMWAIT3_4               ((uint32_t)0x00001000)        /*!< Bit 4 */
05149 #define  FSMC_PMEM3_MEMWAIT3_5               ((uint32_t)0x00002000)        /*!< Bit 5 */
05150 #define  FSMC_PMEM3_MEMWAIT3_6               ((uint32_t)0x00004000)        /*!< Bit 6 */
05151 #define  FSMC_PMEM3_MEMWAIT3_7               ((uint32_t)0x00008000)        /*!< Bit 7 */
05152
05153 #define  FSMC_PMEM3_MEMHOLD3                 ((uint32_t)0x00FF0000)        /*!< MEMHOLD3[7:0] bits (Common memory 3 hold time) */
05154 #define  FSMC_PMEM3_MEMHOLD3_0               ((uint32_t)0x00010000)        /*!< Bit 0 */
05155 #define  FSMC_PMEM3_MEMHOLD3_1               ((uint32_t)0x00020000)        /*!< Bit 1 */
05156 #define  FSMC_PMEM3_MEMHOLD3_2               ((uint32_t)0x00040000)        /*!< Bit 2 */
05157 #define  FSMC_PMEM3_MEMHOLD3_3               ((uint32_t)0x00080000)        /*!< Bit 3 */
05158 #define  FSMC_PMEM3_MEMHOLD3_4               ((uint32_t)0x00100000)        /*!< Bit 4 */
05159 #define  FSMC_PMEM3_MEMHOLD3_5               ((uint32_t)0x00200000)        /*!< Bit 5 */
05160 #define  FSMC_PMEM3_MEMHOLD3_6               ((uint32_t)0x00400000)        /*!< Bit 6 */
05161 #define  FSMC_PMEM3_MEMHOLD3_7               ((uint32_t)0x00800000)        /*!< Bit 7 */
05162
05163 #define  FSMC_PMEM3_MEMHIZ3                  ((uint32_t)0xFF000000)        /*!< MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
05164 #define  FSMC_PMEM3_MEMHIZ3_0                ((uint32_t)0x01000000)        /*!< Bit 0 */
05165 #define  FSMC_PMEM3_MEMHIZ3_1                ((uint32_t)0x02000000)        /*!< Bit 1 */
05166 #define  FSMC_PMEM3_MEMHIZ3_2                ((uint32_t)0x04000000)        /*!< Bit 2 */
05167 #define  FSMC_PMEM3_MEMHIZ3_3                ((uint32_t)0x08000000)        /*!< Bit 3 */
05168 #define  FSMC_PMEM3_MEMHIZ3_4                ((uint32_t)0x10000000)        /*!< Bit 4 */
05169 #define  FSMC_PMEM3_MEMHIZ3_5                ((uint32_t)0x20000000)        /*!< Bit 5 */
05170 #define  FSMC_PMEM3_MEMHIZ3_6                ((uint32_t)0x40000000)        /*!< Bit 6 */
05171 #define  FSMC_PMEM3_MEMHIZ3_7                ((uint32_t)0x80000000)        /*!< Bit 7 */
05172
05173 /******************  Bit definition for FSMC_PMEM4 register  ******************/
05174 #define  FSMC_PMEM4_MEMSET4                  ((uint32_t)0x000000FF)        /*!< MEMSET4[7:0] bits (Common memory 4 setup time) */
05175 #define  FSMC_PMEM4_MEMSET4_0                ((uint32_t)0x00000001)        /*!< Bit 0 */
05176 #define  FSMC_PMEM4_MEMSET4_1                ((uint32_t)0x00000002)        /*!< Bit 1 */
05177 #define  FSMC_PMEM4_MEMSET4_2                ((uint32_t)0x00000004)        /*!< Bit 2 */
05178 #define  FSMC_PMEM4_MEMSET4_3                ((uint32_t)0x00000008)        /*!< Bit 3 */
05179 #define  FSMC_PMEM4_MEMSET4_4                ((uint32_t)0x00000010)        /*!< Bit 4 */
05180 #define  FSMC_PMEM4_MEMSET4_5                ((uint32_t)0x00000020)        /*!< Bit 5 */
05181 #define  FSMC_PMEM4_MEMSET4_6                ((uint32_t)0x00000040)        /*!< Bit 6 */
05182 #define  FSMC_PMEM4_MEMSET4_7                ((uint32_t)0x00000080)        /*!< Bit 7 */
05183
05184 #define  FSMC_PMEM4_MEMWAIT4                 ((uint32_t)0x0000FF00)        /*!< MEMWAIT4[7:0] bits (Common memory 4 wait time) */
05185 #define  FSMC_PMEM4_MEMWAIT4_0               ((uint32_t)0x00000100)        /*!< Bit 0 */
05186 #define  FSMC_PMEM4_MEMWAIT4_1               ((uint32_t)0x00000200)        /*!< Bit 1 */
05187 #define  FSMC_PMEM4_MEMWAIT4_2               ((uint32_t)0x00000400)        /*!< Bit 2 */
05188 #define  FSMC_PMEM4_MEMWAIT4_3               ((uint32_t)0x00000800)        /*!< Bit 3 */
05189 #define  FSMC_PMEM4_MEMWAIT4_4               ((uint32_t)0x00001000)        /*!< Bit 4 */
05190 #define  FSMC_PMEM4_MEMWAIT4_5               ((uint32_t)0x00002000)        /*!< Bit 5 */
05191 #define  FSMC_PMEM4_MEMWAIT4_6               ((uint32_t)0x00004000)        /*!< Bit 6 */
05192 #define  FSMC_PMEM4_MEMWAIT4_7               ((uint32_t)0x00008000)        /*!< Bit 7 */
05193
05194 #define  FSMC_PMEM4_MEMHOLD4                 ((uint32_t)0x00FF0000)        /*!< MEMHOLD4[7:0] bits (Common memory 4 hold time) */
05195 #define  FSMC_PMEM4_MEMHOLD4_0               ((uint32_t)0x00010000)        /*!< Bit 0 */
05196 #define  FSMC_PMEM4_MEMHOLD4_1               ((uint32_t)0x00020000)        /*!< Bit 1 */
05197 #define  FSMC_PMEM4_MEMHOLD4_2               ((uint32_t)0x00040000)        /*!< Bit 2 */
05198 #define  FSMC_PMEM4_MEMHOLD4_3               ((uint32_t)0x00080000)        /*!< Bit 3 */
05199 #define  FSMC_PMEM4_MEMHOLD4_4               ((uint32_t)0x00100000)        /*!< Bit 4 */
05200 #define  FSMC_PMEM4_MEMHOLD4_5               ((uint32_t)0x00200000)        /*!< Bit 5 */
05201 #define  FSMC_PMEM4_MEMHOLD4_6               ((uint32_t)0x00400000)        /*!< Bit 6 */
05202 #define  FSMC_PMEM4_MEMHOLD4_7               ((uint32_t)0x00800000)        /*!< Bit 7 */
05203
05204 #define  FSMC_PMEM4_MEMHIZ4                  ((uint32_t)0xFF000000)        /*!< MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
05205 #define  FSMC_PMEM4_MEMHIZ4_0                ((uint32_t)0x01000000)        /*!< Bit 0 */
05206 #define  FSMC_PMEM4_MEMHIZ4_1                ((uint32_t)0x02000000)        /*!< Bit 1 */
05207 #define  FSMC_PMEM4_MEMHIZ4_2                ((uint32_t)0x04000000)        /*!< Bit 2 */
05208 #define  FSMC_PMEM4_MEMHIZ4_3                ((uint32_t)0x08000000)        /*!< Bit 3 */
05209 #define  FSMC_PMEM4_MEMHIZ4_4                ((uint32_t)0x10000000)        /*!< Bit 4 */
05210 #define  FSMC_PMEM4_MEMHIZ4_5                ((uint32_t)0x20000000)        /*!< Bit 5 */
05211 #define  FSMC_PMEM4_MEMHIZ4_6                ((uint32_t)0x40000000)        /*!< Bit 6 */
05212 #define  FSMC_PMEM4_MEMHIZ4_7                ((uint32_t)0x80000000)        /*!< Bit 7 */
05213
05214 /******************  Bit definition for FSMC_PATT2 register  ******************/
05215 #define  FSMC_PATT2_ATTSET2                  ((uint32_t)0x000000FF)        /*!< ATTSET2[7:0] bits (Attribute memory 2 setup time) */
05216 #define  FSMC_PATT2_ATTSET2_0                ((uint32_t)0x00000001)        /*!< Bit 0 */
05217 #define  FSMC_PATT2_ATTSET2_1                ((uint32_t)0x00000002)        /*!< Bit 1 */
05218 #define  FSMC_PATT2_ATTSET2_2                ((uint32_t)0x00000004)        /*!< Bit 2 */
05219 #define  FSMC_PATT2_ATTSET2_3                ((uint32_t)0x00000008)        /*!< Bit 3 */
05220 #define  FSMC_PATT2_ATTSET2_4                ((uint32_t)0x00000010)        /*!< Bit 4 */
05221 #define  FSMC_PATT2_ATTSET2_5                ((uint32_t)0x00000020)        /*!< Bit 5 */
05222 #define  FSMC_PATT2_ATTSET2_6                ((uint32_t)0x00000040)        /*!< Bit 6 */
05223 #define  FSMC_PATT2_ATTSET2_7                ((uint32_t)0x00000080)        /*!< Bit 7 */
05224
05225 #define  FSMC_PATT2_ATTWAIT2                 ((uint32_t)0x0000FF00)        /*!< ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
05226 #define  FSMC_PATT2_ATTWAIT2_0               ((uint32_t)0x00000100)        /*!< Bit 0 */
05227 #define  FSMC_PATT2_ATTWAIT2_1               ((uint32_t)0x00000200)        /*!< Bit 1 */
05228 #define  FSMC_PATT2_ATTWAIT2_2               ((uint32_t)0x00000400)        /*!< Bit 2 */
05229 #define  FSMC_PATT2_ATTWAIT2_3               ((uint32_t)0x00000800)        /*!< Bit 3 */
05230 #define  FSMC_PATT2_ATTWAIT2_4               ((uint32_t)0x00001000)        /*!< Bit 4 */
05231 #define  FSMC_PATT2_ATTWAIT2_5               ((uint32_t)0x00002000)        /*!< Bit 5 */
05232 #define  FSMC_PATT2_ATTWAIT2_6               ((uint32_t)0x00004000)        /*!< Bit 6 */
05233 #define  FSMC_PATT2_ATTWAIT2_7               ((uint32_t)0x00008000)        /*!< Bit 7 */
05234
05235 #define  FSMC_PATT2_ATTHOLD2                 ((uint32_t)0x00FF0000)        /*!< ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
05236 #define  FSMC_PATT2_ATTHOLD2_0               ((uint32_t)0x00010000)        /*!< Bit 0 */
05237 #define  FSMC_PATT2_ATTHOLD2_1               ((uint32_t)0x00020000)        /*!< Bit 1 */
05238 #define  FSMC_PATT2_ATTHOLD2_2               ((uint32_t)0x00040000)        /*!< Bit 2 */
05239 #define  FSMC_PATT2_ATTHOLD2_3               ((uint32_t)0x00080000)        /*!< Bit 3 */
05240 #define  FSMC_PATT2_ATTHOLD2_4               ((uint32_t)0x00100000)        /*!< Bit 4 */
05241 #define  FSMC_PATT2_ATTHOLD2_5               ((uint32_t)0x00200000)        /*!< Bit 5 */
05242 #define  FSMC_PATT2_ATTHOLD2_6               ((uint32_t)0x00400000)        /*!< Bit 6 */
05243 #define  FSMC_PATT2_ATTHOLD2_7               ((uint32_t)0x00800000)        /*!< Bit 7 */
05244
05245 #define  FSMC_PATT2_ATTHIZ2                  ((uint32_t)0xFF000000)        /*!< ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
05246 #define  FSMC_PATT2_ATTHIZ2_0                ((uint32_t)0x01000000)        /*!< Bit 0 */
05247 #define  FSMC_PATT2_ATTHIZ2_1                ((uint32_t)0x02000000)        /*!< Bit 1 */
05248 #define  FSMC_PATT2_ATTHIZ2_2                ((uint32_t)0x04000000)        /*!< Bit 2 */
05249 #define  FSMC_PATT2_ATTHIZ2_3                ((uint32_t)0x08000000)        /*!< Bit 3 */
05250 #define  FSMC_PATT2_ATTHIZ2_4                ((uint32_t)0x10000000)        /*!< Bit 4 */
05251 #define  FSMC_PATT2_ATTHIZ2_5                ((uint32_t)0x20000000)        /*!< Bit 5 */
05252 #define  FSMC_PATT2_ATTHIZ2_6                ((uint32_t)0x40000000)        /*!< Bit 6 */
05253 #define  FSMC_PATT2_ATTHIZ2_7                ((uint32_t)0x80000000)        /*!< Bit 7 */
05254
05255 /******************  Bit definition for FSMC_PATT3 register  ******************/
05256 #define  FSMC_PATT3_ATTSET3                  ((uint32_t)0x000000FF)        /*!< ATTSET3[7:0] bits (Attribute memory 3 setup time) */
05257 #define  FSMC_PATT3_ATTSET3_0                ((uint32_t)0x00000001)        /*!< Bit 0 */
05258 #define  FSMC_PATT3_ATTSET3_1                ((uint32_t)0x00000002)        /*!< Bit 1 */
05259 #define  FSMC_PATT3_ATTSET3_2                ((uint32_t)0x00000004)        /*!< Bit 2 */
05260 #define  FSMC_PATT3_ATTSET3_3                ((uint32_t)0x00000008)        /*!< Bit 3 */
05261 #define  FSMC_PATT3_ATTSET3_4                ((uint32_t)0x00000010)        /*!< Bit 4 */
05262 #define  FSMC_PATT3_ATTSET3_5                ((uint32_t)0x00000020)        /*!< Bit 5 */
05263 #define  FSMC_PATT3_ATTSET3_6                ((uint32_t)0x00000040)        /*!< Bit 6 */
05264 #define  FSMC_PATT3_ATTSET3_7                ((uint32_t)0x00000080)        /*!< Bit 7 */
05265
05266 #define  FSMC_PATT3_ATTWAIT3                 ((uint32_t)0x0000FF00)        /*!< ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
05267 #define  FSMC_PATT3_ATTWAIT3_0               ((uint32_t)0x00000100)        /*!< Bit 0 */
05268 #define  FSMC_PATT3_ATTWAIT3_1               ((uint32_t)0x00000200)        /*!< Bit 1 */
05269 #define  FSMC_PATT3_ATTWAIT3_2               ((uint32_t)0x00000400)        /*!< Bit 2 */
05270 #define  FSMC_PATT3_ATTWAIT3_3               ((uint32_t)0x00000800)        /*!< Bit 3 */
05271 #define  FSMC_PATT3_ATTWAIT3_4               ((uint32_t)0x00001000)        /*!< Bit 4 */
05272 #define  FSMC_PATT3_ATTWAIT3_5               ((uint32_t)0x00002000)        /*!< Bit 5 */
05273 #define  FSMC_PATT3_ATTWAIT3_6               ((uint32_t)0x00004000)        /*!< Bit 6 */
05274 #define  FSMC_PATT3_ATTWAIT3_7               ((uint32_t)0x00008000)        /*!< Bit 7 */
05275
05276 #define  FSMC_PATT3_ATTHOLD3                 ((uint32_t)0x00FF0000)        /*!< ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
05277 #define  FSMC_PATT3_ATTHOLD3_0               ((uint32_t)0x00010000)        /*!< Bit 0 */
05278 #define  FSMC_PATT3_ATTHOLD3_1               ((uint32_t)0x00020000)        /*!< Bit 1 */
05279 #define  FSMC_PATT3_ATTHOLD3_2               ((uint32_t)0x00040000)        /*!< Bit 2 */
05280 #define  FSMC_PATT3_ATTHOLD3_3               ((uint32_t)0x00080000)        /*!< Bit 3 */
05281 #define  FSMC_PATT3_ATTHOLD3_4               ((uint32_t)0x00100000)        /*!< Bit 4 */
05282 #define  FSMC_PATT3_ATTHOLD3_5               ((uint32_t)0x00200000)        /*!< Bit 5 */
05283 #define  FSMC_PATT3_ATTHOLD3_6               ((uint32_t)0x00400000)        /*!< Bit 6 */
05284 #define  FSMC_PATT3_ATTHOLD3_7               ((uint32_t)0x00800000)        /*!< Bit 7 */
05285
05286 #define  FSMC_PATT3_ATTHIZ3                  ((uint32_t)0xFF000000)        /*!< ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
05287 #define  FSMC_PATT3_ATTHIZ3_0                ((uint32_t)0x01000000)        /*!< Bit 0 */
05288 #define  FSMC_PATT3_ATTHIZ3_1                ((uint32_t)0x02000000)        /*!< Bit 1 */
05289 #define  FSMC_PATT3_ATTHIZ3_2                ((uint32_t)0x04000000)        /*!< Bit 2 */
05290 #define  FSMC_PATT3_ATTHIZ3_3                ((uint32_t)0x08000000)        /*!< Bit 3 */
05291 #define  FSMC_PATT3_ATTHIZ3_4                ((uint32_t)0x10000000)        /*!< Bit 4 */
05292 #define  FSMC_PATT3_ATTHIZ3_5                ((uint32_t)0x20000000)        /*!< Bit 5 */
05293 #define  FSMC_PATT3_ATTHIZ3_6                ((uint32_t)0x40000000)        /*!< Bit 6 */
05294 #define  FSMC_PATT3_ATTHIZ3_7                ((uint32_t)0x80000000)        /*!< Bit 7 */
05295
05296 /******************  Bit definition for FSMC_PATT4 register  ******************/
05297 #define  FSMC_PATT4_ATTSET4                  ((uint32_t)0x000000FF)        /*!< ATTSET4[7:0] bits (Attribute memory 4 setup time) */
05298 #define  FSMC_PATT4_ATTSET4_0                ((uint32_t)0x00000001)        /*!< Bit 0 */
05299 #define  FSMC_PATT4_ATTSET4_1                ((uint32_t)0x00000002)        /*!< Bit 1 */
05300 #define  FSMC_PATT4_ATTSET4_2                ((uint32_t)0x00000004)        /*!< Bit 2 */
05301 #define  FSMC_PATT4_ATTSET4_3                ((uint32_t)0x00000008)        /*!< Bit 3 */
05302 #define  FSMC_PATT4_ATTSET4_4                ((uint32_t)0x00000010)        /*!< Bit 4 */
05303 #define  FSMC_PATT4_ATTSET4_5                ((uint32_t)0x00000020)        /*!< Bit 5 */
05304 #define  FSMC_PATT4_ATTSET4_6                ((uint32_t)0x00000040)        /*!< Bit 6 */
05305 #define  FSMC_PATT4_ATTSET4_7                ((uint32_t)0x00000080)        /*!< Bit 7 */
05306
05307 #define  FSMC_PATT4_ATTWAIT4                 ((uint32_t)0x0000FF00)        /*!< ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
05308 #define  FSMC_PATT4_ATTWAIT4_0               ((uint32_t)0x00000100)        /*!< Bit 0 */
05309 #define  FSMC_PATT4_ATTWAIT4_1               ((uint32_t)0x00000200)        /*!< Bit 1 */
05310 #define  FSMC_PATT4_ATTWAIT4_2               ((uint32_t)0x00000400)        /*!< Bit 2 */
05311 #define  FSMC_PATT4_ATTWAIT4_3               ((uint32_t)0x00000800)        /*!< Bit 3 */
05312 #define  FSMC_PATT4_ATTWAIT4_4               ((uint32_t)0x00001000)        /*!< Bit 4 */
05313 #define  FSMC_PATT4_ATTWAIT4_5               ((uint32_t)0x00002000)        /*!< Bit 5 */
05314 #define  FSMC_PATT4_ATTWAIT4_6               ((uint32_t)0x00004000)        /*!< Bit 6 */
05315 #define  FSMC_PATT4_ATTWAIT4_7               ((uint32_t)0x00008000)        /*!< Bit 7 */
05316
05317 #define  FSMC_PATT4_ATTHOLD4                 ((uint32_t)0x00FF0000)        /*!< ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
05318 #define  FSMC_PATT4_ATTHOLD4_0               ((uint32_t)0x00010000)        /*!< Bit 0 */
05319 #define  FSMC_PATT4_ATTHOLD4_1               ((uint32_t)0x00020000)        /*!< Bit 1 */
05320 #define  FSMC_PATT4_ATTHOLD4_2               ((uint32_t)0x00040000)        /*!< Bit 2 */
05321 #define  FSMC_PATT4_ATTHOLD4_3               ((uint32_t)0x00080000)        /*!< Bit 3 */
05322 #define  FSMC_PATT4_ATTHOLD4_4               ((uint32_t)0x00100000)        /*!< Bit 4 */
05323 #define  FSMC_PATT4_ATTHOLD4_5               ((uint32_t)0x00200000)        /*!< Bit 5 */
05324 #define  FSMC_PATT4_ATTHOLD4_6               ((uint32_t)0x00400000)        /*!< Bit 6 */
05325 #define  FSMC_PATT4_ATTHOLD4_7               ((uint32_t)0x00800000)        /*!< Bit 7 */
05326
05327 #define  FSMC_PATT4_ATTHIZ4                  ((uint32_t)0xFF000000)        /*!< ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
05328 #define  FSMC_PATT4_ATTHIZ4_0                ((uint32_t)0x01000000)        /*!< Bit 0 */
05329 #define  FSMC_PATT4_ATTHIZ4_1                ((uint32_t)0x02000000)        /*!< Bit 1 */
05330 #define  FSMC_PATT4_ATTHIZ4_2                ((uint32_t)0x04000000)        /*!< Bit 2 */
05331 #define  FSMC_PATT4_ATTHIZ4_3                ((uint32_t)0x08000000)        /*!< Bit 3 */
05332 #define  FSMC_PATT4_ATTHIZ4_4                ((uint32_t)0x10000000)        /*!< Bit 4 */
05333 #define  FSMC_PATT4_ATTHIZ4_5                ((uint32_t)0x20000000)        /*!< Bit 5 */
05334 #define  FSMC_PATT4_ATTHIZ4_6                ((uint32_t)0x40000000)        /*!< Bit 6 */
05335 #define  FSMC_PATT4_ATTHIZ4_7                ((uint32_t)0x80000000)        /*!< Bit 7 */
05336
05337 /******************  Bit definition for FSMC_PIO4 register  *******************/
05338 #define  FSMC_PIO4_IOSET4                    ((uint32_t)0x000000FF)        /*!< IOSET4[7:0] bits (I/O 4 setup time) */
05339 #define  FSMC_PIO4_IOSET4_0                  ((uint32_t)0x00000001)        /*!< Bit 0 */
05340 #define  FSMC_PIO4_IOSET4_1                  ((uint32_t)0x00000002)        /*!< Bit 1 */
05341 #define  FSMC_PIO4_IOSET4_2                  ((uint32_t)0x00000004)        /*!< Bit 2 */
05342 #define  FSMC_PIO4_IOSET4_3                  ((uint32_t)0x00000008)        /*!< Bit 3 */
05343 #define  FSMC_PIO4_IOSET4_4                  ((uint32_t)0x00000010)        /*!< Bit 4 */
05344 #define  FSMC_PIO4_IOSET4_5                  ((uint32_t)0x00000020)        /*!< Bit 5 */
05345 #define  FSMC_PIO4_IOSET4_6                  ((uint32_t)0x00000040)        /*!< Bit 6 */
05346 #define  FSMC_PIO4_IOSET4_7                  ((uint32_t)0x00000080)        /*!< Bit 7 */
05347
05348 #define  FSMC_PIO4_IOWAIT4                   ((uint32_t)0x0000FF00)        /*!< IOWAIT4[7:0] bits (I/O 4 wait time) */
05349 #define  FSMC_PIO4_IOWAIT4_0                 ((uint32_t)0x00000100)        /*!< Bit 0 */
05350 #define  FSMC_PIO4_IOWAIT4_1                 ((uint32_t)0x00000200)        /*!< Bit 1 */
05351 #define  FSMC_PIO4_IOWAIT4_2                 ((uint32_t)0x00000400)        /*!< Bit 2 */
05352 #define  FSMC_PIO4_IOWAIT4_3                 ((uint32_t)0x00000800)        /*!< Bit 3 */
05353 #define  FSMC_PIO4_IOWAIT4_4                 ((uint32_t)0x00001000)        /*!< Bit 4 */
05354 #define  FSMC_PIO4_IOWAIT4_5                 ((uint32_t)0x00002000)        /*!< Bit 5 */
05355 #define  FSMC_PIO4_IOWAIT4_6                 ((uint32_t)0x00004000)        /*!< Bit 6 */
05356 #define  FSMC_PIO4_IOWAIT4_7                 ((uint32_t)0x00008000)        /*!< Bit 7 */
05357
05358 #define  FSMC_PIO4_IOHOLD4                   ((uint32_t)0x00FF0000)        /*!< IOHOLD4[7:0] bits (I/O 4 hold time) */
05359 #define  FSMC_PIO4_IOHOLD4_0                 ((uint32_t)0x00010000)        /*!< Bit 0 */
05360 #define  FSMC_PIO4_IOHOLD4_1                 ((uint32_t)0x00020000)        /*!< Bit 1 */
05361 #define  FSMC_PIO4_IOHOLD4_2                 ((uint32_t)0x00040000)        /*!< Bit 2 */
05362 #define  FSMC_PIO4_IOHOLD4_3                 ((uint32_t)0x00080000)        /*!< Bit 3 */
05363 #define  FSMC_PIO4_IOHOLD4_4                 ((uint32_t)0x00100000)        /*!< Bit 4 */
05364 #define  FSMC_PIO4_IOHOLD4_5                 ((uint32_t)0x00200000)        /*!< Bit 5 */
05365 #define  FSMC_PIO4_IOHOLD4_6                 ((uint32_t)0x00400000)        /*!< Bit 6 */
05366 #define  FSMC_PIO4_IOHOLD4_7                 ((uint32_t)0x00800000)        /*!< Bit 7 */
05367
05368 #define  FSMC_PIO4_IOHIZ4                    ((uint32_t)0xFF000000)        /*!< IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
05369 #define  FSMC_PIO4_IOHIZ4_0                  ((uint32_t)0x01000000)        /*!< Bit 0 */
05370 #define  FSMC_PIO4_IOHIZ4_1                  ((uint32_t)0x02000000)        /*!< Bit 1 */
05371 #define  FSMC_PIO4_IOHIZ4_2                  ((uint32_t)0x04000000)        /*!< Bit 2 */
05372 #define  FSMC_PIO4_IOHIZ4_3                  ((uint32_t)0x08000000)        /*!< Bit 3 */
05373 #define  FSMC_PIO4_IOHIZ4_4                  ((uint32_t)0x10000000)        /*!< Bit 4 */
05374 #define  FSMC_PIO4_IOHIZ4_5                  ((uint32_t)0x20000000)        /*!< Bit 5 */
05375 #define  FSMC_PIO4_IOHIZ4_6                  ((uint32_t)0x40000000)        /*!< Bit 6 */
05376 #define  FSMC_PIO4_IOHIZ4_7                  ((uint32_t)0x80000000)        /*!< Bit 7 */
05377
05378 /******************  Bit definition for FSMC_ECCR2 register  ******************/
05379 #define  FSMC_ECCR2_ECC2                     ((uint32_t)0xFFFFFFFF)        /*!< ECC result */
05380
05381 /******************  Bit definition for FSMC_ECCR3 register  ******************/
05382 #define  FSMC_ECCR3_ECC3                     ((uint32_t)0xFFFFFFFF)        /*!< ECC result */
05383
05384 /******************************************************************************/
05385 /*                                                                            */
05386 /*                          SD host Interface                                 */
05387 /*                                                                            */
05388 /******************************************************************************/
05389
05390 /******************  Bit definition for SDIO_POWER register  ******************/
05391 #define  SDIO_POWER_PWRCTRL                  ((uint8_t)0x03)               /*!< PWRCTRL[1:0] bits (Power supply control bits) */
05392 #define  SDIO_POWER_PWRCTRL_0                ((uint8_t)0x01)               /*!< Bit 0 */
05393 #define  SDIO_POWER_PWRCTRL_1                ((uint8_t)0x02)               /*!< Bit 1 */
05394
05395 /******************  Bit definition for SDIO_CLKCR register  ******************/
05396 #define  SDIO_CLKCR_CLKDIV                   ((uint16_t)0x00FF)            /*!< Clock divide factor */
05397 #define  SDIO_CLKCR_CLKEN                    ((uint16_t)0x0100)            /*!< Clock enable bit */
05398 #define  SDIO_CLKCR_PWRSAV                   ((uint16_t)0x0200)            /*!< Power saving configuration bit */
05399 #define  SDIO_CLKCR_BYPASS                   ((uint16_t)0x0400)            /*!< Clock divider bypass enable bit */
05400
05401 #define  SDIO_CLKCR_WIDBUS                   ((uint16_t)0x1800)            /*!< WIDBUS[1:0] bits (Wide bus mode enable bit) */
05402 #define  SDIO_CLKCR_WIDBUS_0                 ((uint16_t)0x0800)            /*!< Bit 0 */
05403 #define  SDIO_CLKCR_WIDBUS_1                 ((uint16_t)0x1000)            /*!< Bit 1 */
05404
05405 #define  SDIO_CLKCR_NEGEDGE                  ((uint16_t)0x2000)            /*!< SDIO_CK dephasing selection bit */
05406 #define  SDIO_CLKCR_HWFC_EN                  ((uint16_t)0x4000)            /*!< HW Flow Control enable */
05407
05408 /*******************  Bit definition for SDIO_ARG register  *******************/
05409 #define  SDIO_ARG_CMDARG                     ((uint32_t)0xFFFFFFFF)            /*!< Command argument */
05410
05411 /*******************  Bit definition for SDIO_CMD register  *******************/
05412 #define  SDIO_CMD_CMDINDEX                   ((uint16_t)0x003F)            /*!< Command Index */
05413
05414 #define  SDIO_CMD_WAITRESP                   ((uint16_t)0x00C0)            /*!< WAITRESP[1:0] bits (Wait for response bits) */
05415 #define  SDIO_CMD_WAITRESP_0                 ((uint16_t)0x0040)            /*!<  Bit 0 */
05416 #define  SDIO_CMD_WAITRESP_1                 ((uint16_t)0x0080)            /*!<  Bit 1 */
05417
05418 #define  SDIO_CMD_WAITINT                    ((uint16_t)0x0100)            /*!< CPSM Waits for Interrupt Request */
05419 #define  SDIO_CMD_WAITPEND                   ((uint16_t)0x0200)            /*!< CPSM Waits for ends of data transfer (CmdPend internal signal) */
05420 #define  SDIO_CMD_CPSMEN                     ((uint16_t)0x0400)            /*!< Command path state machine (CPSM) Enable bit */
05421 #define  SDIO_CMD_SDIOSUSPEND                ((uint16_t)0x0800)            /*!< SD I/O suspend command */
05422 #define  SDIO_CMD_ENCMDCOMPL                 ((uint16_t)0x1000)            /*!< Enable CMD completion */
05423 #define  SDIO_CMD_NIEN                       ((uint16_t)0x2000)            /*!< Not Interrupt Enable */
05424 #define  SDIO_CMD_CEATACMD                   ((uint16_t)0x4000)            /*!< CE-ATA command */
05425
05426 /*****************  Bit definition for SDIO_RESPCMD register  *****************/
05427 #define  SDIO_RESPCMD_RESPCMD                ((uint8_t)0x3F)               /*!< Response command index */
05428
05429 /******************  Bit definition for SDIO_RESP0 register  ******************/
05430 #define  SDIO_RESP0_CARDSTATUS0              ((uint32_t)0xFFFFFFFF)        /*!< Card Status */
05431
05432 /******************  Bit definition for SDIO_RESP1 register  ******************/
05433 #define  SDIO_RESP1_CARDSTATUS1              ((uint32_t)0xFFFFFFFF)        /*!< Card Status */
05434
05435 /******************  Bit definition for SDIO_RESP2 register  ******************/
05436 #define  SDIO_RESP2_CARDSTATUS2              ((uint32_t)0xFFFFFFFF)        /*!< Card Status */
05437
05438 /******************  Bit definition for SDIO_RESP3 register  ******************/
05439 #define  SDIO_RESP3_CARDSTATUS3              ((uint32_t)0xFFFFFFFF)        /*!< Card Status */
05440
05441 /******************  Bit definition for SDIO_RESP4 register  ******************/
05442 #define  SDIO_RESP4_CARDSTATUS4              ((uint32_t)0xFFFFFFFF)        /*!< Card Status */
05443
05444 /******************  Bit definition for SDIO_DTIMER register  *****************/
05445 #define  SDIO_DTIMER_DATATIME                ((uint32_t)0xFFFFFFFF)        /*!< Data timeout period. */
05446
05447 /******************  Bit definition for SDIO_DLEN register  *******************/
05448 #define  SDIO_DLEN_DATALENGTH                ((uint32_t)0x01FFFFFF)        /*!< Data length value */
05449
05450 /******************  Bit definition for SDIO_DCTRL register  ******************/
05451 #define  SDIO_DCTRL_DTEN                     ((uint16_t)0x0001)            /*!< Data transfer enabled bit */
05452 #define  SDIO_DCTRL_DTDIR                    ((uint16_t)0x0002)            /*!< Data transfer direction selection */
05453 #define  SDIO_DCTRL_DTMODE                   ((uint16_t)0x0004)            /*!< Data transfer mode selection */
05454 #define  SDIO_DCTRL_DMAEN                    ((uint16_t)0x0008)            /*!< DMA enabled bit */
05455
05456 #define  SDIO_DCTRL_DBLOCKSIZE               ((uint16_t)0x00F0)            /*!< DBLOCKSIZE[3:0] bits (Data block size) */
05457 #define  SDIO_DCTRL_DBLOCKSIZE_0             ((uint16_t)0x0010)            /*!< Bit 0 */
05458 #define  SDIO_DCTRL_DBLOCKSIZE_1             ((uint16_t)0x0020)            /*!< Bit 1 */
05459 #define  SDIO_DCTRL_DBLOCKSIZE_2             ((uint16_t)0x0040)            /*!< Bit 2 */
05460 #define  SDIO_DCTRL_DBLOCKSIZE_3             ((uint16_t)0x0080)            /*!< Bit 3 */
05461
05462 #define  SDIO_DCTRL_RWSTART                  ((uint16_t)0x0100)            /*!< Read wait start */
05463 #define  SDIO_DCTRL_RWSTOP                   ((uint16_t)0x0200)            /*!< Read wait stop */
05464 #define  SDIO_DCTRL_RWMOD                    ((uint16_t)0x0400)            /*!< Read wait mode */
05465 #define  SDIO_DCTRL_SDIOEN                   ((uint16_t)0x0800)            /*!< SD I/O enable functions */
05466
05467 /******************  Bit definition for SDIO_DCOUNT register  *****************/
05468 #define  SDIO_DCOUNT_DATACOUNT               ((uint32_t)0x01FFFFFF)        /*!< Data count value */
05469
05470 /******************  Bit definition for SDIO_STA register  ********************/
05471 #define  SDIO_STA_CCRCFAIL                   ((uint32_t)0x00000001)        /*!< Command response received (CRC check failed) */
05472 #define  SDIO_STA_DCRCFAIL                   ((uint32_t)0x00000002)        /*!< Data block sent/received (CRC check failed) */
05473 #define  SDIO_STA_CTIMEOUT                   ((uint32_t)0x00000004)        /*!< Command response timeout */
05474 #define  SDIO_STA_DTIMEOUT                   ((uint32_t)0x00000008)        /*!< Data timeout */
05475 #define  SDIO_STA_TXUNDERR                   ((uint32_t)0x00000010)        /*!< Transmit FIFO underrun error */
05476 #define  SDIO_STA_RXOVERR                    ((uint32_t)0x00000020)        /*!< Received FIFO overrun error */
05477 #define  SDIO_STA_CMDREND                    ((uint32_t)0x00000040)        /*!< Command response received (CRC check passed) */
05478 #define  SDIO_STA_CMDSENT                    ((uint32_t)0x00000080)        /*!< Command sent (no response required) */
05479 #define  SDIO_STA_DATAEND                    ((uint32_t)0x00000100)        /*!< Data end (data counter, SDIDCOUNT, is zero) */
05480 #define  SDIO_STA_STBITERR                   ((uint32_t)0x00000200)        /*!< Start bit not detected on all data signals in wide bus mode */
05481 #define  SDIO_STA_DBCKEND                    ((uint32_t)0x00000400)        /*!< Data block sent/received (CRC check passed) */
05482 #define  SDIO_STA_CMDACT                     ((uint32_t)0x00000800)        /*!< Command transfer in progress */
05483 #define  SDIO_STA_TXACT                      ((uint32_t)0x00001000)        /*!< Data transmit in progress */
05484 #define  SDIO_STA_RXACT                      ((uint32_t)0x00002000)        /*!< Data receive in progress */
05485 #define  SDIO_STA_TXFIFOHE                   ((uint32_t)0x00004000)        /*!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
05486 #define  SDIO_STA_RXFIFOHF                   ((uint32_t)0x00008000)        /*!< Receive FIFO Half Full: there are at least 8 words in the FIFO */
05487 #define  SDIO_STA_TXFIFOF                    ((uint32_t)0x00010000)        /*!< Transmit FIFO full */
05488 #define  SDIO_STA_RXFIFOF                    ((uint32_t)0x00020000)        /*!< Receive FIFO full */
05489 #define  SDIO_STA_TXFIFOE                    ((uint32_t)0x00040000)        /*!< Transmit FIFO empty */
05490 #define  SDIO_STA_RXFIFOE                    ((uint32_t)0x00080000)        /*!< Receive FIFO empty */
05491 #define  SDIO_STA_TXDAVL                     ((uint32_t)0x00100000)        /*!< Data available in transmit FIFO */
05492 #define  SDIO_STA_RXDAVL                     ((uint32_t)0x00200000)        /*!< Data available in receive FIFO */
05493 #define  SDIO_STA_SDIOIT                     ((uint32_t)0x00400000)        /*!< SDIO interrupt received */
05494 #define  SDIO_STA_CEATAEND                   ((uint32_t)0x00800000)        /*!< CE-ATA command completion signal received for CMD61 */
05495
05496 /*******************  Bit definition for SDIO_ICR register  *******************/
05497 #define  SDIO_ICR_CCRCFAILC                  ((uint32_t)0x00000001)        /*!< CCRCFAIL flag clear bit */
05498 #define  SDIO_ICR_DCRCFAILC                  ((uint32_t)0x00000002)        /*!< DCRCFAIL flag clear bit */
05499 #define  SDIO_ICR_CTIMEOUTC                  ((uint32_t)0x00000004)        /*!< CTIMEOUT flag clear bit */
05500 #define  SDIO_ICR_DTIMEOUTC                  ((uint32_t)0x00000008)        /*!< DTIMEOUT flag clear bit */
05501 #define  SDIO_ICR_TXUNDERRC                  ((uint32_t)0x00000010)        /*!< TXUNDERR flag clear bit */
05502 #define  SDIO_ICR_RXOVERRC                   ((uint32_t)0x00000020)        /*!< RXOVERR flag clear bit */
05503 #define  SDIO_ICR_CMDRENDC                   ((uint32_t)0x00000040)        /*!< CMDREND flag clear bit */
05504 #define  SDIO_ICR_CMDSENTC                   ((uint32_t)0x00000080)        /*!< CMDSENT flag clear bit */
05505 #define  SDIO_ICR_DATAENDC                   ((uint32_t)0x00000100)        /*!< DATAEND flag clear bit */
05506 #define  SDIO_ICR_STBITERRC                  ((uint32_t)0x00000200)        /*!< STBITERR flag clear bit */
05507 #define  SDIO_ICR_DBCKENDC                   ((uint32_t)0x00000400)        /*!< DBCKEND flag clear bit */
05508 #define  SDIO_ICR_SDIOITC                    ((uint32_t)0x00400000)        /*!< SDIOIT flag clear bit */
05509 #define  SDIO_ICR_CEATAENDC                  ((uint32_t)0x00800000)        /*!< CEATAEND flag clear bit */
05510
05511 /******************  Bit definition for SDIO_MASK register  *******************/
05512 #define  SDIO_MASK_CCRCFAILIE                ((uint32_t)0x00000001)        /*!< Command CRC Fail Interrupt Enable */
05513 #define  SDIO_MASK_DCRCFAILIE                ((uint32_t)0x00000002)        /*!< Data CRC Fail Interrupt Enable */
05514 #define  SDIO_MASK_CTIMEOUTIE                ((uint32_t)0x00000004)        /*!< Command TimeOut Interrupt Enable */
05515 #define  SDIO_MASK_DTIMEOUTIE                ((uint32_t)0x00000008)        /*!< Data TimeOut Interrupt Enable */
05516 #define  SDIO_MASK_TXUNDERRIE                ((uint32_t)0x00000010)        /*!< Tx FIFO UnderRun Error Interrupt Enable */
05517 #define  SDIO_MASK_RXOVERRIE                 ((uint32_t)0x00000020)        /*!< Rx FIFO OverRun Error Interrupt Enable */
05518 #define  SDIO_MASK_CMDRENDIE                 ((uint32_t)0x00000040)        /*!< Command Response Received Interrupt Enable */
05519 #define  SDIO_MASK_CMDSENTIE                 ((uint32_t)0x00000080)        /*!< Command Sent Interrupt Enable */
05520 #define  SDIO_MASK_DATAENDIE                 ((uint32_t)0x00000100)        /*!< Data End Interrupt Enable */
05521 #define  SDIO_MASK_STBITERRIE                ((uint32_t)0x00000200)        /*!< Start Bit Error Interrupt Enable */
05522 #define  SDIO_MASK_DBCKENDIE                 ((uint32_t)0x00000400)        /*!< Data Block End Interrupt Enable */
05523 #define  SDIO_MASK_CMDACTIE                  ((uint32_t)0x00000800)        /*!< Command Acting Interrupt Enable */
05524 #define  SDIO_MASK_TXACTIE                   ((uint32_t)0x00001000)        /*!< Data Transmit Acting Interrupt Enable */
05525 #define  SDIO_MASK_RXACTIE                   ((uint32_t)0x00002000)        /*!< Data receive acting interrupt enabled */
05526 #define  SDIO_MASK_TXFIFOHEIE                ((uint32_t)0x00004000)        /*!< Tx FIFO Half Empty interrupt Enable */
05527 #define  SDIO_MASK_RXFIFOHFIE                ((uint32_t)0x00008000)        /*!< Rx FIFO Half Full interrupt Enable */
05528 #define  SDIO_MASK_TXFIFOFIE                 ((uint32_t)0x00010000)        /*!< Tx FIFO Full interrupt Enable */
05529 #define  SDIO_MASK_RXFIFOFIE                 ((uint32_t)0x00020000)        /*!< Rx FIFO Full interrupt Enable */
05530 #define  SDIO_MASK_TXFIFOEIE                 ((uint32_t)0x00040000)        /*!< Tx FIFO Empty interrupt Enable */
05531 #define  SDIO_MASK_RXFIFOEIE                 ((uint32_t)0x00080000)        /*!< Rx FIFO Empty interrupt Enable */
05532 #define  SDIO_MASK_TXDAVLIE                  ((uint32_t)0x00100000)        /*!< Data available in Tx FIFO interrupt Enable */
05533 #define  SDIO_MASK_RXDAVLIE                  ((uint32_t)0x00200000)        /*!< Data available in Rx FIFO interrupt Enable */
05534 #define  SDIO_MASK_SDIOITIE                  ((uint32_t)0x00400000)        /*!< SDIO Mode Interrupt Received interrupt Enable */
05535 #define  SDIO_MASK_CEATAENDIE                ((uint32_t)0x00800000)        /*!< CE-ATA command completion signal received Interrupt Enable */
05536
05537 /*****************  Bit definition for SDIO_FIFOCNT register  *****************/
05538 #define  SDIO_FIFOCNT_FIFOCOUNT              ((uint32_t)0x00FFFFFF)        /*!< Remaining number of words to be written to or read from the FIFO */
05539
05540 /******************  Bit definition for SDIO_FIFO register  *******************/
05541 #define  SDIO_FIFO_FIFODATA                  ((uint32_t)0xFFFFFFFF)        /*!< Receive and transmit FIFO data */
05542
05543 /******************************************************************************/
05544 /*                                                                            */
05545 /*                                   USB Device FS                            */
05546 /*                                                                            */
05547 /******************************************************************************/
05548
05549 /*!< Endpoint-specific registers */
05550 /*******************  Bit definition for USB_EP0R register  *******************/
05551 #define  USB_EP0R_EA                         ((uint16_t)0x000F)            /*!< Endpoint Address */
05552
05553 #define  USB_EP0R_STAT_TX                    ((uint16_t)0x0030)            /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
05554 #define  USB_EP0R_STAT_TX_0                  ((uint16_t)0x0010)            /*!< Bit 0 */
05555 #define  USB_EP0R_STAT_TX_1                  ((uint16_t)0x0020)            /*!< Bit 1 */
05556
05557 #define  USB_EP0R_DTOG_TX                    ((uint16_t)0x0040)            /*!< Data Toggle, for transmission transfers */
05558 #define  USB_EP0R_CTR_TX                     ((uint16_t)0x0080)            /*!< Correct Transfer for transmission */
05559 #define  USB_EP0R_EP_KIND                    ((uint16_t)0x0100)            /*!< Endpoint Kind */
05560
05561 #define  USB_EP0R_EP_TYPE                    ((uint16_t)0x0600)            /*!< EP_TYPE[1:0] bits (Endpoint type) */
05562 #define  USB_EP0R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!< Bit 0 */
05563 #define  USB_EP0R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!< Bit 1 */
05564
05565 #define  USB_EP0R_SETUP                      ((uint16_t)0x0800)            /*!< Setup transaction completed */
05566
05567 #define  USB_EP0R_STAT_RX                    ((uint16_t)0x3000)            /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
05568 #define  USB_EP0R_STAT_RX_0                  ((uint16_t)0x1000)            /*!< Bit 0 */
05569 #define  USB_EP0R_STAT_RX_1                  ((uint16_t)0x2000)            /*!< Bit 1 */
05570
05571 #define  USB_EP0R_DTOG_RX                    ((uint16_t)0x4000)            /*!< Data Toggle, for reception transfers */
05572 #define  USB_EP0R_CTR_RX                     ((uint16_t)0x8000)            /*!< Correct Transfer for reception */
05573
05574 /*******************  Bit definition for USB_EP1R register  *******************/
05575 #define  USB_EP1R_EA                         ((uint16_t)0x000F)            /*!< Endpoint Address */
05576
05577 #define  USB_EP1R_STAT_TX                    ((uint16_t)0x0030)            /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
05578 #define  USB_EP1R_STAT_TX_0                  ((uint16_t)0x0010)            /*!< Bit 0 */
05579 #define  USB_EP1R_STAT_TX_1                  ((uint16_t)0x0020)            /*!< Bit 1 */
05580
05581 #define  USB_EP1R_DTOG_TX                    ((uint16_t)0x0040)            /*!< Data Toggle, for transmission transfers */
05582 #define  USB_EP1R_CTR_TX                     ((uint16_t)0x0080)            /*!< Correct Transfer for transmission */
05583 #define  USB_EP1R_EP_KIND                    ((uint16_t)0x0100)            /*!< Endpoint Kind */
05584
05585 #define  USB_EP1R_EP_TYPE                    ((uint16_t)0x0600)            /*!< EP_TYPE[1:0] bits (Endpoint type) */
05586 #define  USB_EP1R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!< Bit 0 */
05587 #define  USB_EP1R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!< Bit 1 */
05588
05589 #define  USB_EP1R_SETUP                      ((uint16_t)0x0800)            /*!< Setup transaction completed */
05590
05591 #define  USB_EP1R_STAT_RX                    ((uint16_t)0x3000)            /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
05592 #define  USB_EP1R_STAT_RX_0                  ((uint16_t)0x1000)            /*!< Bit 0 */
05593 #define  USB_EP1R_STAT_RX_1                  ((uint16_t)0x2000)            /*!< Bit 1 */
05594
05595 #define  USB_EP1R_DTOG_RX                    ((uint16_t)0x4000)            /*!< Data Toggle, for reception transfers */
05596 #define  USB_EP1R_CTR_RX                     ((uint16_t)0x8000)            /*!< Correct Transfer for reception */
05597
05598 /*******************  Bit definition for USB_EP2R register  *******************/
05599 #define  USB_EP2R_EA                         ((uint16_t)0x000F)            /*!< Endpoint Address */
05600
05601 #define  USB_EP2R_STAT_TX                    ((uint16_t)0x0030)            /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
05602 #define  USB_EP2R_STAT_TX_0                  ((uint16_t)0x0010)            /*!< Bit 0 */
05603 #define  USB_EP2R_STAT_TX_1                  ((uint16_t)0x0020)            /*!< Bit 1 */
05604
05605 #define  USB_EP2R_DTOG_TX                    ((uint16_t)0x0040)            /*!< Data Toggle, for transmission transfers */
05606 #define  USB_EP2R_CTR_TX                     ((uint16_t)0x0080)            /*!< Correct Transfer for transmission */
05607 #define  USB_EP2R_EP_KIND                    ((uint16_t)0x0100)            /*!< Endpoint Kind */
05608
05609 #define  USB_EP2R_EP_TYPE                    ((uint16_t)0x0600)            /*!< EP_TYPE[1:0] bits (Endpoint type) */
05610 #define  USB_EP2R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!< Bit 0 */
05611 #define  USB_EP2R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!< Bit 1 */
05612
05613 #define  USB_EP2R_SETUP                      ((uint16_t)0x0800)            /*!< Setup transaction completed */
05614
05615 #define  USB_EP2R_STAT_RX                    ((uint16_t)0x3000)            /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
05616 #define  USB_EP2R_STAT_RX_0                  ((uint16_t)0x1000)            /*!< Bit 0 */
05617 #define  USB_EP2R_STAT_RX_1                  ((uint16_t)0x2000)            /*!< Bit 1 */
05618
05619 #define  USB_EP2R_DTOG_RX                    ((uint16_t)0x4000)            /*!< Data Toggle, for reception transfers */
05620 #define  USB_EP2R_CTR_RX                     ((uint16_t)0x8000)            /*!< Correct Transfer for reception */
05621
05622 /*******************  Bit definition for USB_EP3R register  *******************/
05623 #define  USB_EP3R_EA                         ((uint16_t)0x000F)            /*!< Endpoint Address */
05624
05625 #define  USB_EP3R_STAT_TX                    ((uint16_t)0x0030)            /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
05626 #define  USB_EP3R_STAT_TX_0                  ((uint16_t)0x0010)            /*!< Bit 0 */
05627 #define  USB_EP3R_STAT_TX_1                  ((uint16_t)0x0020)            /*!< Bit 1 */
05628
05629 #define  USB_EP3R_DTOG_TX                    ((uint16_t)0x0040)            /*!< Data Toggle, for transmission transfers */
05630 #define  USB_EP3R_CTR_TX                     ((uint16_t)0x0080)            /*!< Correct Transfer for transmission */
05631 #define  USB_EP3R_EP_KIND                    ((uint16_t)0x0100)            /*!< Endpoint Kind */
05632
05633 #define  USB_EP3R_EP_TYPE                    ((uint16_t)0x0600)            /*!< EP_TYPE[1:0] bits (Endpoint type) */
05634 #define  USB_EP3R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!< Bit 0 */
05635 #define  USB_EP3R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!< Bit 1 */
05636
05637 #define  USB_EP3R_SETUP                      ((uint16_t)0x0800)            /*!< Setup transaction completed */
05638
05639 #define  USB_EP3R_STAT_RX                    ((uint16_t)0x3000)            /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
05640 #define  USB_EP3R_STAT_RX_0                  ((uint16_t)0x1000)            /*!< Bit 0 */
05641 #define  USB_EP3R_STAT_RX_1                  ((uint16_t)0x2000)            /*!< Bit 1 */
05642
05643 #define  USB_EP3R_DTOG_RX                    ((uint16_t)0x4000)            /*!< Data Toggle, for reception transfers */
05644 #define  USB_EP3R_CTR_RX                     ((uint16_t)0x8000)            /*!< Correct Transfer for reception */
05645
05646 /*******************  Bit definition for USB_EP4R register  *******************/
05647 #define  USB_EP4R_EA                         ((uint16_t)0x000F)            /*!< Endpoint Address */
05648
05649 #define  USB_EP4R_STAT_TX                    ((uint16_t)0x0030)            /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
05650 #define  USB_EP4R_STAT_TX_0                  ((uint16_t)0x0010)            /*!< Bit 0 */
05651 #define  USB_EP4R_STAT_TX_1                  ((uint16_t)0x0020)            /*!< Bit 1 */
05652
05653 #define  USB_EP4R_DTOG_TX                    ((uint16_t)0x0040)            /*!< Data Toggle, for transmission transfers */
05654 #define  USB_EP4R_CTR_TX                     ((uint16_t)0x0080)            /*!< Correct Transfer for transmission */
05655 #define  USB_EP4R_EP_KIND                    ((uint16_t)0x0100)            /*!< Endpoint Kind */
05656
05657 #define  USB_EP4R_EP_TYPE                    ((uint16_t)0x0600)            /*!< EP_TYPE[1:0] bits (Endpoint type) */
05658 #define  USB_EP4R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!< Bit 0 */
05659 #define  USB_EP4R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!< Bit 1 */
05660
05661 #define  USB_EP4R_SETUP                      ((uint16_t)0x0800)            /*!< Setup transaction completed */
05662
05663 #define  USB_EP4R_STAT_RX                    ((uint16_t)0x3000)            /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
05664 #define  USB_EP4R_STAT_RX_0                  ((uint16_t)0x1000)            /*!< Bit 0 */
05665 #define  USB_EP4R_STAT_RX_1                  ((uint16_t)0x2000)            /*!< Bit 1 */
05666
05667 #define  USB_EP4R_DTOG_RX                    ((uint16_t)0x4000)            /*!< Data Toggle, for reception transfers */
05668 #define  USB_EP4R_CTR_RX                     ((uint16_t)0x8000)            /*!< Correct Transfer for reception */
05669
05670 /*******************  Bit definition for USB_EP5R register  *******************/
05671 #define  USB_EP5R_EA                         ((uint16_t)0x000F)            /*!< Endpoint Address */
05672
05673 #define  USB_EP5R_STAT_TX                    ((uint16_t)0x0030)            /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
05674 #define  USB_EP5R_STAT_TX_0                  ((uint16_t)0x0010)            /*!< Bit 0 */
05675 #define  USB_EP5R_STAT_TX_1                  ((uint16_t)0x0020)            /*!< Bit 1 */
05676
05677 #define  USB_EP5R_DTOG_TX                    ((uint16_t)0x0040)            /*!< Data Toggle, for transmission transfers */
05678 #define  USB_EP5R_CTR_TX                     ((uint16_t)0x0080)            /*!< Correct Transfer for transmission */
05679 #define  USB_EP5R_EP_KIND                    ((uint16_t)0x0100)            /*!< Endpoint Kind */
05680
05681 #define  USB_EP5R_EP_TYPE                    ((uint16_t)0x0600)            /*!< EP_TYPE[1:0] bits (Endpoint type) */
05682 #define  USB_EP5R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!< Bit 0 */
05683 #define  USB_EP5R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!< Bit 1 */
05684
05685 #define  USB_EP5R_SETUP                      ((uint16_t)0x0800)            /*!< Setup transaction completed */
05686
05687 #define  USB_EP5R_STAT_RX                    ((uint16_t)0x3000)            /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
05688 #define  USB_EP5R_STAT_RX_0                  ((uint16_t)0x1000)            /*!< Bit 0 */
05689 #define  USB_EP5R_STAT_RX_1                  ((uint16_t)0x2000)            /*!< Bit 1 */
05690
05691 #define  USB_EP5R_DTOG_RX                    ((uint16_t)0x4000)            /*!< Data Toggle, for reception transfers */
05692 #define  USB_EP5R_CTR_RX                     ((uint16_t)0x8000)            /*!< Correct Transfer for reception */
05693
05694 /*******************  Bit definition for USB_EP6R register  *******************/
05695 #define  USB_EP6R_EA                         ((uint16_t)0x000F)            /*!< Endpoint Address */
05696
05697 #define  USB_EP6R_STAT_TX                    ((uint16_t)0x0030)            /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
05698 #define  USB_EP6R_STAT_TX_0                  ((uint16_t)0x0010)            /*!< Bit 0 */
05699 #define  USB_EP6R_STAT_TX_1                  ((uint16_t)0x0020)            /*!< Bit 1 */
05700
05701 #define  USB_EP6R_DTOG_TX                    ((uint16_t)0x0040)            /*!< Data Toggle, for transmission transfers */
05702 #define  USB_EP6R_CTR_TX                     ((uint16_t)0x0080)            /*!< Correct Transfer for transmission */
05703 #define  USB_EP6R_EP_KIND                    ((uint16_t)0x0100)            /*!< Endpoint Kind */
05704
05705 #define  USB_EP6R_EP_TYPE                    ((uint16_t)0x0600)            /*!< EP_TYPE[1:0] bits (Endpoint type) */
05706 #define  USB_EP6R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!< Bit 0 */
05707 #define  USB_EP6R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!< Bit 1 */
05708
05709 #define  USB_EP6R_SETUP                      ((uint16_t)0x0800)            /*!< Setup transaction completed */
05710
05711 #define  USB_EP6R_STAT_RX                    ((uint16_t)0x3000)            /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
05712 #define  USB_EP6R_STAT_RX_0                  ((uint16_t)0x1000)            /*!< Bit 0 */
05713 #define  USB_EP6R_STAT_RX_1                  ((uint16_t)0x2000)            /*!< Bit 1 */
05714
05715 #define  USB_EP6R_DTOG_RX                    ((uint16_t)0x4000)            /*!< Data Toggle, for reception transfers */
05716 #define  USB_EP6R_CTR_RX                     ((uint16_t)0x8000)            /*!< Correct Transfer for reception */
05717
05718 /*******************  Bit definition for USB_EP7R register  *******************/
05719 #define  USB_EP7R_EA                         ((uint16_t)0x000F)            /*!< Endpoint Address */
05720
05721 #define  USB_EP7R_STAT_TX                    ((uint16_t)0x0030)            /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
05722 #define  USB_EP7R_STAT_TX_0                  ((uint16_t)0x0010)            /*!< Bit 0 */
05723 #define  USB_EP7R_STAT_TX_1                  ((uint16_t)0x0020)            /*!< Bit 1 */
05724
05725 #define  USB_EP7R_DTOG_TX                    ((uint16_t)0x0040)            /*!< Data Toggle, for transmission transfers */
05726 #define  USB_EP7R_CTR_TX                     ((uint16_t)0x0080)            /*!< Correct Transfer for transmission */
05727 #define  USB_EP7R_EP_KIND                    ((uint16_t)0x0100)            /*!< Endpoint Kind */
05728
05729 #define  USB_EP7R_EP_TYPE                    ((uint16_t)0x0600)            /*!< EP_TYPE[1:0] bits (Endpoint type) */
05730 #define  USB_EP7R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!< Bit 0 */
05731 #define  USB_EP7R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!< Bit 1 */
05732
05733 #define  USB_EP7R_SETUP                      ((uint16_t)0x0800)            /*!< Setup transaction completed */
05734
05735 #define  USB_EP7R_STAT_RX                    ((uint16_t)0x3000)            /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
05736 #define  USB_EP7R_STAT_RX_0                  ((uint16_t)0x1000)            /*!< Bit 0 */
05737 #define  USB_EP7R_STAT_RX_1                  ((uint16_t)0x2000)            /*!< Bit 1 */
05738
05739 #define  USB_EP7R_DTOG_RX                    ((uint16_t)0x4000)            /*!< Data Toggle, for reception transfers */
05740 #define  USB_EP7R_CTR_RX                     ((uint16_t)0x8000)            /*!< Correct Transfer for reception */
05741
05742 /*!< Common registers */
05743 /*******************  Bit definition for USB_CNTR register  *******************/
05744 #define  USB_CNTR_FRES                       ((uint16_t)0x0001)            /*!< Force USB Reset */
05745 #define  USB_CNTR_PDWN                       ((uint16_t)0x0002)            /*!< Power down */
05746 #define  USB_CNTR_LP_MODE                    ((uint16_t)0x0004)            /*!< Low-power mode */
05747 #define  USB_CNTR_FSUSP                      ((uint16_t)0x0008)            /*!< Force suspend */
05748 #define  USB_CNTR_RESUME                     ((uint16_t)0x0010)            /*!< Resume request */
05749 #define  USB_CNTR_ESOFM                      ((uint16_t)0x0100)            /*!< Expected Start Of Frame Interrupt Mask */
05750 #define  USB_CNTR_SOFM                       ((uint16_t)0x0200)            /*!< Start Of Frame Interrupt Mask */
05751 #define  USB_CNTR_RESETM                     ((uint16_t)0x0400)            /*!< RESET Interrupt Mask */
05752 #define  USB_CNTR_SUSPM                      ((uint16_t)0x0800)            /*!< Suspend mode Interrupt Mask */
05753 #define  USB_CNTR_WKUPM                      ((uint16_t)0x1000)            /*!< Wakeup Interrupt Mask */
05754 #define  USB_CNTR_ERRM                       ((uint16_t)0x2000)            /*!< Error Interrupt Mask */
05755 #define  USB_CNTR_PMAOVRM                    ((uint16_t)0x4000)            /*!< Packet Memory Area Over / Underrun Interrupt Mask */
05756 #define  USB_CNTR_CTRM                       ((uint16_t)0x8000)            /*!< Correct Transfer Interrupt Mask */
05757
05758 /*******************  Bit definition for USB_ISTR register  *******************/
05759 #define  USB_ISTR_EP_ID                      ((uint16_t)0x000F)            /*!< Endpoint Identifier */
05760 #define  USB_ISTR_DIR                        ((uint16_t)0x0010)            /*!< Direction of transaction */
05761 #define  USB_ISTR_ESOF                       ((uint16_t)0x0100)            /*!< Expected Start Of Frame */
05762 #define  USB_ISTR_SOF                        ((uint16_t)0x0200)            /*!< Start Of Frame */
05763 #define  USB_ISTR_RESET                      ((uint16_t)0x0400)            /*!< USB RESET request */
05764 #define  USB_ISTR_SUSP                       ((uint16_t)0x0800)            /*!< Suspend mode request */
05765 #define  USB_ISTR_WKUP                       ((uint16_t)0x1000)            /*!< Wake up */
05766 #define  USB_ISTR_ERR                        ((uint16_t)0x2000)            /*!< Error */
05767 #define  USB_ISTR_PMAOVR                     ((uint16_t)0x4000)            /*!< Packet Memory Area Over / Underrun */
05768 #define  USB_ISTR_CTR                        ((uint16_t)0x8000)            /*!< Correct Transfer */
05769
05770 /*******************  Bit definition for USB_FNR register  ********************/
05771 #define  USB_FNR_FN                          ((uint16_t)0x07FF)            /*!< Frame Number */
05772 #define  USB_FNR_LSOF                        ((uint16_t)0x1800)            /*!< Lost SOF */
05773 #define  USB_FNR_LCK                         ((uint16_t)0x2000)            /*!< Locked */
05774 #define  USB_FNR_RXDM                        ((uint16_t)0x4000)            /*!< Receive Data - Line Status */
05775 #define  USB_FNR_RXDP                        ((uint16_t)0x8000)            /*!< Receive Data + Line Status */
05776
05777 /******************  Bit definition for USB_DADDR register  *******************/
05778 #define  USB_DADDR_ADD                       ((uint8_t)0x7F)               /*!< ADD[6:0] bits (Device Address) */
05779 #define  USB_DADDR_ADD0                      ((uint8_t)0x01)               /*!< Bit 0 */
05780 #define  USB_DADDR_ADD1                      ((uint8_t)0x02)               /*!< Bit 1 */
05781 #define  USB_DADDR_ADD2                      ((uint8_t)0x04)               /*!< Bit 2 */
05782 #define  USB_DADDR_ADD3                      ((uint8_t)0x08)               /*!< Bit 3 */
05783 #define  USB_DADDR_ADD4                      ((uint8_t)0x10)               /*!< Bit 4 */
05784 #define  USB_DADDR_ADD5                      ((uint8_t)0x20)               /*!< Bit 5 */
05785 #define  USB_DADDR_ADD6                      ((uint8_t)0x40)               /*!< Bit 6 */
05786
05787 #define  USB_DADDR_EF                        ((uint8_t)0x80)               /*!< Enable Function */
05788
05789 /******************  Bit definition for USB_BTABLE register  ******************/
05790 #define  USB_BTABLE_BTABLE                   ((uint16_t)0xFFF8)            /*!< Buffer Table */
05791
05792 /*!< Buffer descriptor table */
05793 /*****************  Bit definition for USB_ADDR0_TX register  *****************/
05794 #define  USB_ADDR0_TX_ADDR0_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 0 */
05795
05796 /*****************  Bit definition for USB_ADDR1_TX register  *****************/
05797 #define  USB_ADDR1_TX_ADDR1_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 1 */
05798
05799 /*****************  Bit definition for USB_ADDR2_TX register  *****************/
05800 #define  USB_ADDR2_TX_ADDR2_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 2 */
05801
05802 /*****************  Bit definition for USB_ADDR3_TX register  *****************/
05803 #define  USB_ADDR3_TX_ADDR3_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 3 */
05804
05805 /*****************  Bit definition for USB_ADDR4_TX register  *****************/
05806 #define  USB_ADDR4_TX_ADDR4_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 4 */
05807
05808 /*****************  Bit definition for USB_ADDR5_TX register  *****************/
05809 #define  USB_ADDR5_TX_ADDR5_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 5 */
05810
05811 /*****************  Bit definition for USB_ADDR6_TX register  *****************/
05812 #define  USB_ADDR6_TX_ADDR6_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 6 */
05813
05814 /*****************  Bit definition for USB_ADDR7_TX register  *****************/
05815 #define  USB_ADDR7_TX_ADDR7_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 7 */
05816
05817 /*----------------------------------------------------------------------------*/
05818
05819 /*****************  Bit definition for USB_COUNT0_TX register  ****************/
05820 #define  USB_COUNT0_TX_COUNT0_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 0 */
05821
05822 /*****************  Bit definition for USB_COUNT1_TX register  ****************/
05823 #define  USB_COUNT1_TX_COUNT1_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 1 */
05824
05825 /*****************  Bit definition for USB_COUNT2_TX register  ****************/
05826 #define  USB_COUNT2_TX_COUNT2_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 2 */
05827
05828 /*****************  Bit definition for USB_COUNT3_TX register  ****************/
05829 #define  USB_COUNT3_TX_COUNT3_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 3 */
05830
05831 /*****************  Bit definition for USB_COUNT4_TX register  ****************/
05832 #define  USB_COUNT4_TX_COUNT4_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 4 */
05833
05834 /*****************  Bit definition for USB_COUNT5_TX register  ****************/
05835 #define  USB_COUNT5_TX_COUNT5_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 5 */
05836
05837 /*****************  Bit definition for USB_COUNT6_TX register  ****************/
05838 #define  USB_COUNT6_TX_COUNT6_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 6 */
05839
05840 /*****************  Bit definition for USB_COUNT7_TX register  ****************/
05841 #define  USB_COUNT7_TX_COUNT7_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 7 */
05842
05843 /*----------------------------------------------------------------------------*/
05844
05845 /****************  Bit definition for USB_COUNT0_TX_0 register  ***************/
05846 #define  USB_COUNT0_TX_0_COUNT0_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 0 (low) */
05847
05848 /****************  Bit definition for USB_COUNT0_TX_1 register  ***************/
05849 #define  USB_COUNT0_TX_1_COUNT0_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 0 (high) */
05850
05851 /****************  Bit definition for USB_COUNT1_TX_0 register  ***************/
05852 #define  USB_COUNT1_TX_0_COUNT1_TX_0          ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 1 (low) */
05853
05854 /****************  Bit definition for USB_COUNT1_TX_1 register  ***************/
05855 #define  USB_COUNT1_TX_1_COUNT1_TX_1          ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 1 (high) */
05856
05857 /****************  Bit definition for USB_COUNT2_TX_0 register  ***************/
05858 #define  USB_COUNT2_TX_0_COUNT2_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 2 (low) */
05859
05860 /****************  Bit definition for USB_COUNT2_TX_1 register  ***************/
05861 #define  USB_COUNT2_TX_1_COUNT2_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 2 (high) */
05862
05863 /****************  Bit definition for USB_COUNT3_TX_0 register  ***************/
05864 #define  USB_COUNT3_TX_0_COUNT3_TX_0         ((uint16_t)0x000003FF)        /*!< Transmission Byte Count 3 (low) */
05865
05866 /****************  Bit definition for USB_COUNT3_TX_1 register  ***************/
05867 #define  USB_COUNT3_TX_1_COUNT3_TX_1         ((uint16_t)0x03FF0000)        /*!< Transmission Byte Count 3 (high) */
05868
05869 /****************  Bit definition for USB_COUNT4_TX_0 register  ***************/
05870 #define  USB_COUNT4_TX_0_COUNT4_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 4 (low) */
05871
05872 /****************  Bit definition for USB_COUNT4_TX_1 register  ***************/
05873 #define  USB_COUNT4_TX_1_COUNT4_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 4 (high) */
05874
05875 /****************  Bit definition for USB_COUNT5_TX_0 register  ***************/
05876 #define  USB_COUNT5_TX_0_COUNT5_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 5 (low) */
05877
05878 /****************  Bit definition for USB_COUNT5_TX_1 register  ***************/
05879 #define  USB_COUNT5_TX_1_COUNT5_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 5 (high) */
05880
05881 /****************  Bit definition for USB_COUNT6_TX_0 register  ***************/
05882 #define  USB_COUNT6_TX_0_COUNT6_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 6 (low) */
05883
05884 /****************  Bit definition for USB_COUNT6_TX_1 register  ***************/
05885 #define  USB_COUNT6_TX_1_COUNT6_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 6 (high) */
05886
05887 /****************  Bit definition for USB_COUNT7_TX_0 register  ***************/
05888 #define  USB_COUNT7_TX_0_COUNT7_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 7 (low) */
05889
05890 /****************  Bit definition for USB_COUNT7_TX_1 register  ***************/
05891 #define  USB_COUNT7_TX_1_COUNT7_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 7 (high) */
05892
05893 /*----------------------------------------------------------------------------*/
05894
05895 /*****************  Bit definition for USB_ADDR0_RX register  *****************/
05896 #define  USB_ADDR0_RX_ADDR0_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 0 */
05897
05898 /*****************  Bit definition for USB_ADDR1_RX register  *****************/
05899 #define  USB_ADDR1_RX_ADDR1_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 1 */
05900
05901 /*****************  Bit definition for USB_ADDR2_RX register  *****************/
05902 #define  USB_ADDR2_RX_ADDR2_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 2 */
05903
05904 /*****************  Bit definition for USB_ADDR3_RX register  *****************/
05905 #define  USB_ADDR3_RX_ADDR3_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 3 */
05906
05907 /*****************  Bit definition for USB_ADDR4_RX register  *****************/
05908 #define  USB_ADDR4_RX_ADDR4_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 4 */
05909
05910 /*****************  Bit definition for USB_ADDR5_RX register  *****************/
05911 #define  USB_ADDR5_RX_ADDR5_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 5 */
05912
05913 /*****************  Bit definition for USB_ADDR6_RX register  *****************/
05914 #define  USB_ADDR6_RX_ADDR6_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 6 */
05915
05916 /*****************  Bit definition for USB_ADDR7_RX register  *****************/
05917 #define  USB_ADDR7_RX_ADDR7_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 7 */
05918
05919 /*----------------------------------------------------------------------------*/
05920
05921 /*****************  Bit definition for USB_COUNT0_RX register  ****************/
05922 #define  USB_COUNT0_RX_COUNT0_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */
05923
05924 #define  USB_COUNT0_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
05925 #define  USB_COUNT0_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */
05926 #define  USB_COUNT0_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */
05927 #define  USB_COUNT0_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */
05928 #define  USB_COUNT0_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */
05929 #define  USB_COUNT0_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */
05930
05931 #define  USB_COUNT0_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */
05932
05933 /*****************  Bit definition for USB_COUNT1_RX register  ****************/
05934 #define  USB_COUNT1_RX_COUNT1_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */
05935
05936 #define  USB_COUNT1_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
05937 #define  USB_COUNT1_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */
05938 #define  USB_COUNT1_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */
05939 #define  USB_COUNT1_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */
05940 #define  USB_COUNT1_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */
05941 #define  USB_COUNT1_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */
05942
05943 #define  USB_COUNT1_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */
05944
05945 /*****************  Bit definition for USB_COUNT2_RX register  ****************/
05946 #define  USB_COUNT2_RX_COUNT2_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */
05947
05948 #define  USB_COUNT2_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
05949 #define  USB_COUNT2_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */
05950 #define  USB_COUNT2_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */
05951 #define  USB_COUNT2_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */
05952 #define  USB_COUNT2_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */
05953 #define  USB_COUNT2_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */
05954
05955 #define  USB_COUNT2_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */
05956
05957 /*****************  Bit definition for USB_COUNT3_RX register  ****************/
05958 #define  USB_COUNT3_RX_COUNT3_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */
05959
05960 #define  USB_COUNT3_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
05961 #define  USB_COUNT3_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */
05962 #define  USB_COUNT3_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */
05963 #define  USB_COUNT3_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */
05964 #define  USB_COUNT3_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */
05965 #define  USB_COUNT3_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */
05966
05967 #define  USB_COUNT3_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */
05968
05969 /*****************  Bit definition for USB_COUNT4_RX register  ****************/
05970 #define  USB_COUNT4_RX_COUNT4_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */
05971
05972 #define  USB_COUNT4_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
05973 #define  USB_COUNT4_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */
05974 #define  USB_COUNT4_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */
05975 #define  USB_COUNT4_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */
05976 #define  USB_COUNT4_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */
05977 #define  USB_COUNT4_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */
05978
05979 #define  USB_COUNT4_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */
05980
05981 /*****************  Bit definition for USB_COUNT5_RX register  ****************/
05982 #define  USB_COUNT5_RX_COUNT5_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */
05983
05984 #define  USB_COUNT5_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
05985 #define  USB_COUNT5_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */
05986 #define  USB_COUNT5_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */
05987 #define  USB_COUNT5_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */
05988 #define  USB_COUNT5_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */
05989 #define  USB_COUNT5_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */
05990
05991 #define  USB_COUNT5_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */
05992
05993 /*****************  Bit definition for USB_COUNT6_RX register  ****************/
05994 #define  USB_COUNT6_RX_COUNT6_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */
05995
05996 #define  USB_COUNT6_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
05997 #define  USB_COUNT6_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */
05998 #define  USB_COUNT6_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */
05999 #define  USB_COUNT6_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */
06000 #define  USB_COUNT6_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */
06001 #define  USB_COUNT6_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */
06002
06003 #define  USB_COUNT6_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */
06004
06005 /*****************  Bit definition for USB_COUNT7_RX register  ****************/
06006 #define  USB_COUNT7_RX_COUNT7_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */
06007
06008 #define  USB_COUNT7_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
06009 #define  USB_COUNT7_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */
06010 #define  USB_COUNT7_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */
06011 #define  USB_COUNT7_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */
06012 #define  USB_COUNT7_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */
06013 #define  USB_COUNT7_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */
06014
06015 #define  USB_COUNT7_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */
06016
06017 /*----------------------------------------------------------------------------*/
06018
06019 /****************  Bit definition for USB_COUNT0_RX_0 register  ***************/
06020 #define  USB_COUNT0_RX_0_COUNT0_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
06021
06022 #define  USB_COUNT0_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
06023 #define  USB_COUNT0_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
06024 #define  USB_COUNT0_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
06025 #define  USB_COUNT0_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
06026 #define  USB_COUNT0_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
06027 #define  USB_COUNT0_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
06028
06029 #define  USB_COUNT0_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
06030
06031 /****************  Bit definition for USB_COUNT0_RX_1 register  ***************/
06032 #define  USB_COUNT0_RX_1_COUNT0_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
06033
06034 #define  USB_COUNT0_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
06035 #define  USB_COUNT0_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 1 */
06036 #define  USB_COUNT0_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
06037 #define  USB_COUNT0_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
06038 #define  USB_COUNT0_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
06039 #define  USB_COUNT0_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
06040
06041 #define  USB_COUNT0_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
06042
06043 /****************  Bit definition for USB_COUNT1_RX_0 register  ***************/
06044 #define  USB_COUNT1_RX_0_COUNT1_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
06045
06046 #define  USB_COUNT1_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
06047 #define  USB_COUNT1_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
06048 #define  USB_COUNT1_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
06049 #define  USB_COUNT1_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
06050 #define  USB_COUNT1_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
06051 #define  USB_COUNT1_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
06052
06053 #define  USB_COUNT1_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
06054
06055 /****************  Bit definition for USB_COUNT1_RX_1 register  ***************/
06056 #define  USB_COUNT1_RX_1_COUNT1_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
06057
06058 #define  USB_COUNT1_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
06059 #define  USB_COUNT1_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
06060 #define  USB_COUNT1_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
06061 #define  USB_COUNT1_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
06062 #define  USB_COUNT1_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
06063 #define  USB_COUNT1_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
06064
06065 #define  USB_COUNT1_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
06066
06067 /****************  Bit definition for USB_COUNT2_RX_0 register  ***************/
06068 #define  USB_COUNT2_RX_0_COUNT2_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
06069
06070 #define  USB_COUNT2_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
06071 #define  USB_COUNT2_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
06072 #define  USB_COUNT2_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
06073 #define  USB_COUNT2_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
06074 #define  USB_COUNT2_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
06075 #define  USB_COUNT2_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
06076
06077 #define  USB_COUNT2_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
06078
06079 /****************  Bit definition for USB_COUNT2_RX_1 register  ***************/
06080 #define  USB_COUNT2_RX_1_COUNT2_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
06081
06082 #define  USB_COUNT2_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
06083 #define  USB_COUNT2_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
06084 #define  USB_COUNT2_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
06085 #define  USB_COUNT2_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
06086 #define  USB_COUNT2_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
06087 #define  USB_COUNT2_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
06088
06089 #define  USB_COUNT2_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
06090
06091 /****************  Bit definition for USB_COUNT3_RX_0 register  ***************/
06092 #define  USB_COUNT3_RX_0_COUNT3_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
06093
06094 #define  USB_COUNT3_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
06095 #define  USB_COUNT3_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
06096 #define  USB_COUNT3_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
06097 #define  USB_COUNT3_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
06098 #define  USB_COUNT3_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
06099 #define  USB_COUNT3_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
06100
06101 #define  USB_COUNT3_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
06102
06103 /****************  Bit definition for USB_COUNT3_RX_1 register  ***************/
06104 #define  USB_COUNT3_RX_1_COUNT3_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
06105
06106 #define  USB_COUNT3_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
06107 #define  USB_COUNT3_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
06108 #define  USB_COUNT3_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
06109 #define  USB_COUNT3_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
06110 #define  USB_COUNT3_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
06111 #define  USB_COUNT3_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
06112
06113 #define  USB_COUNT3_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
06114
06115 /****************  Bit definition for USB_COUNT4_RX_0 register  ***************/
06116 #define  USB_COUNT4_RX_0_COUNT4_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
06117
06118 #define  USB_COUNT4_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
06119 #define  USB_COUNT4_RX_0_NUM_BLOCK_0_0      ((uint32_t)0x00000400)        /*!< Bit 0 */
06120 #define  USB_COUNT4_RX_0_NUM_BLOCK_0_1      ((uint32_t)0x00000800)        /*!< Bit 1 */
06121 #define  USB_COUNT4_RX_0_NUM_BLOCK_0_2      ((uint32_t)0x00001000)        /*!< Bit 2 */
06122 #define  USB_COUNT4_RX_0_NUM_BLOCK_0_3      ((uint32_t)0x00002000)        /*!< Bit 3 */
06123 #define  USB_COUNT4_RX_0_NUM_BLOCK_0_4      ((uint32_t)0x00004000)        /*!< Bit 4 */
06124
06125 #define  USB_COUNT4_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
06126
06127 /****************  Bit definition for USB_COUNT4_RX_1 register  ***************/
06128 #define  USB_COUNT4_RX_1_COUNT4_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
06129
06130 #define  USB_COUNT4_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
06131 #define  USB_COUNT4_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
06132 #define  USB_COUNT4_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
06133 #define  USB_COUNT4_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
06134 #define  USB_COUNT4_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
06135 #define  USB_COUNT4_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
06136
06137 #define  USB_COUNT4_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
06138
06139 /****************  Bit definition for USB_COUNT5_RX_0 register  ***************/
06140 #define  USB_COUNT5_RX_0_COUNT5_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
06141
06142 #define  USB_COUNT5_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
06143 #define  USB_COUNT5_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
06144 #define  USB_COUNT5_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
06145 #define  USB_COUNT5_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
06146 #define  USB_COUNT5_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
06147 #define  USB_COUNT5_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
06148
06149 #define  USB_COUNT5_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
06150
06151 /****************  Bit definition for USB_COUNT5_RX_1 register  ***************/
06152 #define  USB_COUNT5_RX_1_COUNT5_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
06153
06154 #define  USB_COUNT5_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
06155 #define  USB_COUNT5_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
06156 #define  USB_COUNT5_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
06157 #define  USB_COUNT5_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
06158 #define  USB_COUNT5_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
06159 #define  USB_COUNT5_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
06160
06161 #define  USB_COUNT5_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
06162
06163 /***************  Bit definition for USB_COUNT6_RX_0  register  ***************/
06164 #define  USB_COUNT6_RX_0_COUNT6_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
06165
06166 #define  USB_COUNT6_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
06167 #define  USB_COUNT6_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
06168 #define  USB_COUNT6_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
06169 #define  USB_COUNT6_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
06170 #define  USB_COUNT6_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
06171 #define  USB_COUNT6_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
06172
06173 #define  USB_COUNT6_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
06174
06175 /****************  Bit definition for USB_COUNT6_RX_1 register  ***************/
06176 #define  USB_COUNT6_RX_1_COUNT6_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
06177
06178 #define  USB_COUNT6_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
06179 #define  USB_COUNT6_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
06180 #define  USB_COUNT6_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
06181 #define  USB_COUNT6_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
06182 #define  USB_COUNT6_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
06183 #define  USB_COUNT6_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
06184
06185 #define  USB_COUNT6_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
06186
06187 /***************  Bit definition for USB_COUNT7_RX_0 register  ****************/
06188 #define  USB_COUNT7_RX_0_COUNT7_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
06189
06190 #define  USB_COUNT7_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
06191 #define  USB_COUNT7_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
06192 #define  USB_COUNT7_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
06193 #define  USB_COUNT7_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
06194 #define  USB_COUNT7_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
06195 #define  USB_COUNT7_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
06196
06197 #define  USB_COUNT7_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
06198
06199 /***************  Bit definition for USB_COUNT7_RX_1 register  ****************/
06200 #define  USB_COUNT7_RX_1_COUNT7_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
06201
06202 #define  USB_COUNT7_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
06203 #define  USB_COUNT7_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
06204 #define  USB_COUNT7_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
06205 #define  USB_COUNT7_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
06206 #define  USB_COUNT7_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
06207 #define  USB_COUNT7_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
06208
06209 #define  USB_COUNT7_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
06210
06211 /******************************************************************************/
06212 /*                                                                            */
06213 /*                         Controller Area Network                            */
06214 /*                                                                            */
06215 /******************************************************************************/
06216
06217 /*!< CAN control and status registers */
06218 /*******************  Bit definition for CAN_MCR register  ********************/
06219 #define  CAN_MCR_INRQ                        ((uint16_t)0x0001)            /*!< Initialization Request */
06220 #define  CAN_MCR_SLEEP                       ((uint16_t)0x0002)            /*!< Sleep Mode Request */
06221 #define  CAN_MCR_TXFP                        ((uint16_t)0x0004)            /*!< Transmit FIFO Priority */
06222 #define  CAN_MCR_RFLM                        ((uint16_t)0x0008)            /*!< Receive FIFO Locked Mode */
06223 #define  CAN_MCR_NART                        ((uint16_t)0x0010)            /*!< No Automatic Retransmission */
06224 #define  CAN_MCR_AWUM                        ((uint16_t)0x0020)            /*!< Automatic Wakeup Mode */
06225 #define  CAN_MCR_ABOM                        ((uint16_t)0x0040)            /*!< Automatic Bus-Off Management */
06226 #define  CAN_MCR_TTCM                        ((uint16_t)0x0080)            /*!< Time Triggered Communication Mode */
06227 #define  CAN_MCR_RESET                       ((uint16_t)0x8000)            /*!< CAN software master reset */
06228
06229 /*******************  Bit definition for CAN_MSR register  ********************/
06230 #define  CAN_MSR_INAK                        ((uint16_t)0x0001)            /*!< Initialization Acknowledge */
06231 #define  CAN_MSR_SLAK                        ((uint16_t)0x0002)            /*!< Sleep Acknowledge */
06232 #define  CAN_MSR_ERRI                        ((uint16_t)0x0004)            /*!< Error Interrupt */
06233 #define  CAN_MSR_WKUI                        ((uint16_t)0x0008)            /*!< Wakeup Interrupt */
06234 #define  CAN_MSR_SLAKI                       ((uint16_t)0x0010)            /*!< Sleep Acknowledge Interrupt */
06235 #define  CAN_MSR_TXM                         ((uint16_t)0x0100)            /*!< Transmit Mode */
06236 #define  CAN_MSR_RXM                         ((uint16_t)0x0200)            /*!< Receive Mode */
06237 #define  CAN_MSR_SAMP                        ((uint16_t)0x0400)            /*!< Last Sample Point */
06238 #define  CAN_MSR_RX                          ((uint16_t)0x0800)            /*!< CAN Rx Signal */
06239
06240 /*******************  Bit definition for CAN_TSR register  ********************/
06241 #define  CAN_TSR_RQCP0                       ((uint32_t)0x00000001)        /*!< Request Completed Mailbox0 */
06242 #define  CAN_TSR_TXOK0                       ((uint32_t)0x00000002)        /*!< Transmission OK of Mailbox0 */
06243 #define  CAN_TSR_ALST0                       ((uint32_t)0x00000004)        /*!< Arbitration Lost for Mailbox0 */
06244 #define  CAN_TSR_TERR0                       ((uint32_t)0x00000008)        /*!< Transmission Error of Mailbox0 */
06245 #define  CAN_TSR_ABRQ0                       ((uint32_t)0x00000080)        /*!< Abort Request for Mailbox0 */
06246 #define  CAN_TSR_RQCP1                       ((uint32_t)0x00000100)        /*!< Request Completed Mailbox1 */
06247 #define  CAN_TSR_TXOK1                       ((uint32_t)0x00000200)        /*!< Transmission OK of Mailbox1 */
06248 #define  CAN_TSR_ALST1                       ((uint32_t)0x00000400)        /*!< Arbitration Lost for Mailbox1 */
06249 #define  CAN_TSR_TERR1                       ((uint32_t)0x00000800)        /*!< Transmission Error of Mailbox1 */
06250 #define  CAN_TSR_ABRQ1                       ((uint32_t)0x00008000)        /*!< Abort Request for Mailbox 1 */
06251 #define  CAN_TSR_RQCP2                       ((uint32_t)0x00010000)        /*!< Request Completed Mailbox2 */
06252 #define  CAN_TSR_TXOK2                       ((uint32_t)0x00020000)        /*!< Transmission OK of Mailbox 2 */
06253 #define  CAN_TSR_ALST2                       ((uint32_t)0x00040000)        /*!< Arbitration Lost for mailbox 2 */
06254 #define  CAN_TSR_TERR2                       ((uint32_t)0x00080000)        /*!< Transmission Error of Mailbox 2 */
06255 #define  CAN_TSR_ABRQ2                       ((uint32_t)0x00800000)        /*!< Abort Request for Mailbox 2 */
06256 #define  CAN_TSR_CODE                        ((uint32_t)0x03000000)        /*!< Mailbox Code */
06257
06258 #define  CAN_TSR_TME                         ((uint32_t)0x1C000000)        /*!< TME[2:0] bits */
06259 #define  CAN_TSR_TME0                        ((uint32_t)0x04000000)        /*!< Transmit Mailbox 0 Empty */
06260 #define  CAN_TSR_TME1                        ((uint32_t)0x08000000)        /*!< Transmit Mailbox 1 Empty */
06261 #define  CAN_TSR_TME2                        ((uint32_t)0x10000000)        /*!< Transmit Mailbox 2 Empty */
06262
06263 #define  CAN_TSR_LOW                         ((uint32_t)0xE0000000)        /*!< LOW[2:0] bits */
06264 #define  CAN_TSR_LOW0                        ((uint32_t)0x20000000)        /*!< Lowest Priority Flag for Mailbox 0 */
06265 #define  CAN_TSR_LOW1                        ((uint32_t)0x40000000)        /*!< Lowest Priority Flag for Mailbox 1 */
06266 #define  CAN_TSR_LOW2                        ((uint32_t)0x80000000)        /*!< Lowest Priority Flag for Mailbox 2 */
06267
06268 /*******************  Bit definition for CAN_RF0R register  *******************/
06269 #define  CAN_RF0R_FMP0                       ((uint8_t)0x03)               /*!< FIFO 0 Message Pending */
06270 #define  CAN_RF0R_FULL0                      ((uint8_t)0x08)               /*!< FIFO 0 Full */
06271 #define  CAN_RF0R_FOVR0                      ((uint8_t)0x10)               /*!< FIFO 0 Overrun */
06272 #define  CAN_RF0R_RFOM0                      ((uint8_t)0x20)               /*!< Release FIFO 0 Output Mailbox */
06273
06274 /*******************  Bit definition for CAN_RF1R register  *******************/
06275 #define  CAN_RF1R_FMP1                       ((uint8_t)0x03)               /*!< FIFO 1 Message Pending */
06276 #define  CAN_RF1R_FULL1                      ((uint8_t)0x08)               /*!< FIFO 1 Full */
06277 #define  CAN_RF1R_FOVR1                      ((uint8_t)0x10)               /*!< FIFO 1 Overrun */
06278 #define  CAN_RF1R_RFOM1                      ((uint8_t)0x20)               /*!< Release FIFO 1 Output Mailbox */
06279
06280 /********************  Bit definition for CAN_IER register  *******************/
06281 #define  CAN_IER_TMEIE                       ((uint32_t)0x00000001)        /*!< Transmit Mailbox Empty Interrupt Enable */
06282 #define  CAN_IER_FMPIE0                      ((uint32_t)0x00000002)        /*!< FIFO Message Pending Interrupt Enable */
06283 #define  CAN_IER_FFIE0                       ((uint32_t)0x00000004)        /*!< FIFO Full Interrupt Enable */
06284 #define  CAN_IER_FOVIE0                      ((uint32_t)0x00000008)        /*!< FIFO Overrun Interrupt Enable */
06285 #define  CAN_IER_FMPIE1                      ((uint32_t)0x00000010)        /*!< FIFO Message Pending Interrupt Enable */
06286 #define  CAN_IER_FFIE1                       ((uint32_t)0x00000020)        /*!< FIFO Full Interrupt Enable */
06287 #define  CAN_IER_FOVIE1                      ((uint32_t)0x00000040)        /*!< FIFO Overrun Interrupt Enable */
06288 #define  CAN_IER_EWGIE                       ((uint32_t)0x00000100)        /*!< Error Warning Interrupt Enable */
06289 #define  CAN_IER_EPVIE                       ((uint32_t)0x00000200)        /*!< Error Passive Interrupt Enable */
06290 #define  CAN_IER_BOFIE                       ((uint32_t)0x00000400)        /*!< Bus-Off Interrupt Enable */
06291 #define  CAN_IER_LECIE                       ((uint32_t)0x00000800)        /*!< Last Error Code Interrupt Enable */
06292 #define  CAN_IER_ERRIE                       ((uint32_t)0x00008000)        /*!< Error Interrupt Enable */
06293 #define  CAN_IER_WKUIE                       ((uint32_t)0x00010000)        /*!< Wakeup Interrupt Enable */
06294 #define  CAN_IER_SLKIE                       ((uint32_t)0x00020000)        /*!< Sleep Interrupt Enable */
06295
06296 /********************  Bit definition for CAN_ESR register  *******************/
06297 #define  CAN_ESR_EWGF                        ((uint32_t)0x00000001)        /*!< Error Warning Flag */
06298 #define  CAN_ESR_EPVF                        ((uint32_t)0x00000002)        /*!< Error Passive Flag */
06299 #define  CAN_ESR_BOFF                        ((uint32_t)0x00000004)        /*!< Bus-Off Flag */
06300
06301 #define  CAN_ESR_LEC                         ((uint32_t)0x00000070)        /*!< LEC[2:0] bits (Last Error Code) */
06302 #define  CAN_ESR_LEC_0                       ((uint32_t)0x00000010)        /*!< Bit 0 */
06303 #define  CAN_ESR_LEC_1                       ((uint32_t)0x00000020)        /*!< Bit 1 */
06304 #define  CAN_ESR_LEC_2                       ((uint32_t)0x00000040)        /*!< Bit 2 */
06305
06306 #define  CAN_ESR_TEC                         ((uint32_t)0x00FF0000)        /*!< Least significant byte of the 9-bit Transmit Error Counter */
06307 #define  CAN_ESR_REC                         ((uint32_t)0xFF000000)        /*!< Receive Error Counter */
06308
06309 /*******************  Bit definition for CAN_BTR register  ********************/
06310 #define  CAN_BTR_BRP                         ((uint32_t)0x000003FF)        /*!< Baud Rate Prescaler */
06311 #define  CAN_BTR_TS1                         ((uint32_t)0x000F0000)        /*!< Time Segment 1 */
06312 #define  CAN_BTR_TS2                         ((uint32_t)0x00700000)        /*!< Time Segment 2 */
06313 #define  CAN_BTR_SJW                         ((uint32_t)0x03000000)        /*!< Resynchronization Jump Width */
06314 #define  CAN_BTR_LBKM                        ((uint32_t)0x40000000)        /*!< Loop Back Mode (Debug) */
06315 #define  CAN_BTR_SILM                        ((uint32_t)0x80000000)        /*!< Silent Mode */
06316
06317 /*!< Mailbox registers */
06318 /******************  Bit definition for CAN_TI0R register  ********************/
06319 #define  CAN_TI0R_TXRQ                       ((uint32_t)0x00000001)        /*!< Transmit Mailbox Request */
06320 #define  CAN_TI0R_RTR                        ((uint32_t)0x00000002)        /*!< Remote Transmission Request */
06321 #define  CAN_TI0R_IDE                        ((uint32_t)0x00000004)        /*!< Identifier Extension */
06322 #define  CAN_TI0R_EXID                       ((uint32_t)0x001FFFF8)        /*!< Extended Identifier */
06323 #define  CAN_TI0R_STID                       ((uint32_t)0xFFE00000)        /*!< Standard Identifier or Extended Identifier */
06324
06325 /******************  Bit definition for CAN_TDT0R register  *******************/
06326 #define  CAN_TDT0R_DLC                       ((uint32_t)0x0000000F)        /*!< Data Length Code */
06327 #define  CAN_TDT0R_TGT                       ((uint32_t)0x00000100)        /*!< Transmit Global Time */
06328 #define  CAN_TDT0R_TIME                      ((uint32_t)0xFFFF0000)        /*!< Message Time Stamp */
06329
06330 /******************  Bit definition for CAN_TDL0R register  *******************/
06331 #define  CAN_TDL0R_DATA0                     ((uint32_t)0x000000FF)        /*!< Data byte 0 */
06332 #define  CAN_TDL0R_DATA1                     ((uint32_t)0x0000FF00)        /*!< Data byte 1 */
06333 #define  CAN_TDL0R_DATA2                     ((uint32_t)0x00FF0000)        /*!< Data byte 2 */
06334 #define  CAN_TDL0R_DATA3                     ((uint32_t)0xFF000000)        /*!< Data byte 3 */
06335
06336 /******************  Bit definition for CAN_TDH0R register  *******************/
06337 #define  CAN_TDH0R_DATA4                     ((uint32_t)0x000000FF)        /*!< Data byte 4 */
06338 #define  CAN_TDH0R_DATA5                     ((uint32_t)0x0000FF00)        /*!< Data byte 5 */
06339 #define  CAN_TDH0R_DATA6                     ((uint32_t)0x00FF0000)        /*!< Data byte 6 */
06340 #define  CAN_TDH0R_DATA7                     ((uint32_t)0xFF000000)        /*!< Data byte 7 */
06341
06342 /*******************  Bit definition for CAN_TI1R register  *******************/
06343 #define  CAN_TI1R_TXRQ                       ((uint32_t)0x00000001)        /*!< Transmit Mailbox Request */
06344 #define  CAN_TI1R_RTR                        ((uint32_t)0x00000002)        /*!< Remote Transmission Request */
06345 #define  CAN_TI1R_IDE                        ((uint32_t)0x00000004)        /*!< Identifier Extension */
06346 #define  CAN_TI1R_EXID                       ((uint32_t)0x001FFFF8)        /*!< Extended Identifier */
06347 #define  CAN_TI1R_STID                       ((uint32_t)0xFFE00000)        /*!< Standard Identifier or Extended Identifier */
06348
06349 /*******************  Bit definition for CAN_TDT1R register  ******************/
06350 #define  CAN_TDT1R_DLC                       ((uint32_t)0x0000000F)        /*!< Data Length Code */
06351 #define  CAN_TDT1R_TGT                       ((uint32_t)0x00000100)        /*!< Transmit Global Time */
06352 #define  CAN_TDT1R_TIME                      ((uint32_t)0xFFFF0000)        /*!< Message Time Stamp */
06353
06354 /*******************  Bit definition for CAN_TDL1R register  ******************/
06355 #define  CAN_TDL1R_DATA0                     ((uint32_t)0x000000FF)        /*!< Data byte 0 */
06356 #define  CAN_TDL1R_DATA1                     ((uint32_t)0x0000FF00)        /*!< Data byte 1 */
06357 #define  CAN_TDL1R_DATA2                     ((uint32_t)0x00FF0000)        /*!< Data byte 2 */
06358 #define  CAN_TDL1R_DATA3                     ((uint32_t)0xFF000000)        /*!< Data byte 3 */
06359
06360 /*******************  Bit definition for CAN_TDH1R register  ******************/
06361 #define  CAN_TDH1R_DATA4                     ((uint32_t)0x000000FF)        /*!< Data byte 4 */
06362 #define  CAN_TDH1R_DATA5                     ((uint32_t)0x0000FF00)        /*!< Data byte 5 */
06363 #define  CAN_TDH1R_DATA6                     ((uint32_t)0x00FF0000)        /*!< Data byte 6 */
06364 #define  CAN_TDH1R_DATA7                     ((uint32_t)0xFF000000)        /*!< Data byte 7 */
06365
06366 /*******************  Bit definition for CAN_TI2R register  *******************/
06367 #define  CAN_TI2R_TXRQ                       ((uint32_t)0x00000001)        /*!< Transmit Mailbox Request */
06368 #define  CAN_TI2R_RTR                        ((uint32_t)0x00000002)        /*!< Remote Transmission Request */
06369 #define  CAN_TI2R_IDE                        ((uint32_t)0x00000004)        /*!< Identifier Extension */
06370 #define  CAN_TI2R_EXID                       ((uint32_t)0x001FFFF8)        /*!< Extended identifier */
06371 #define  CAN_TI2R_STID                       ((uint32_t)0xFFE00000)        /*!< Standard Identifier or Extended Identifier */
06372
06373 /*******************  Bit definition for CAN_TDT2R register  ******************/
06374 #define  CAN_TDT2R_DLC                       ((uint32_t)0x0000000F)        /*!< Data Length Code */
06375 #define  CAN_TDT2R_TGT                       ((uint32_t)0x00000100)        /*!< Transmit Global Time */
06376 #define  CAN_TDT2R_TIME                      ((uint32_t)0xFFFF0000)        /*!< Message Time Stamp */
06377
06378 /*******************  Bit definition for CAN_TDL2R register  ******************/
06379 #define  CAN_TDL2R_DATA0                     ((uint32_t)0x000000FF)        /*!< Data byte 0 */
06380 #define  CAN_TDL2R_DATA1                     ((uint32_t)0x0000FF00)        /*!< Data byte 1 */
06381 #define  CAN_TDL2R_DATA2                     ((uint32_t)0x00FF0000)        /*!< Data byte 2 */
06382 #define  CAN_TDL2R_DATA3                     ((uint32_t)0xFF000000)        /*!< Data byte 3 */
06383
06384 /*******************  Bit definition for CAN_TDH2R register  ******************/
06385 #define  CAN_TDH2R_DATA4                     ((uint32_t)0x000000FF)        /*!< Data byte 4 */
06386 #define  CAN_TDH2R_DATA5                     ((uint32_t)0x0000FF00)        /*!< Data byte 5 */
06387 #define  CAN_TDH2R_DATA6                     ((uint32_t)0x00FF0000)        /*!< Data byte 6 */
06388 #define  CAN_TDH2R_DATA7                     ((uint32_t)0xFF000000)        /*!< Data byte 7 */
06389
06390 /*******************  Bit definition for CAN_RI0R register  *******************/
06391 #define  CAN_RI0R_RTR                        ((uint32_t)0x00000002)        /*!< Remote Transmission Request */
06392 #define  CAN_RI0R_IDE                        ((uint32_t)0x00000004)        /*!< Identifier Extension */
06393 #define  CAN_RI0R_EXID                       ((uint32_t)0x001FFFF8)        /*!< Extended Identifier */
06394 #define  CAN_RI0R_STID                       ((uint32_t)0xFFE00000)        /*!< Standard Identifier or Extended Identifier */
06395
06396 /*******************  Bit definition for CAN_RDT0R register  ******************/
06397 #define  CAN_RDT0R_DLC                       ((uint32_t)0x0000000F)        /*!< Data Length Code */
06398 #define  CAN_RDT0R_FMI                       ((uint32_t)0x0000FF00)        /*!< Filter Match Index */
06399 #define  CAN_RDT0R_TIME                      ((uint32_t)0xFFFF0000)        /*!< Message Time Stamp */
06400
06401 /*******************  Bit definition for CAN_RDL0R register  ******************/
06402 #define  CAN_RDL0R_DATA0                     ((uint32_t)0x000000FF)        /*!< Data byte 0 */
06403 #define  CAN_RDL0R_DATA1                     ((uint32_t)0x0000FF00)        /*!< Data byte 1 */
06404 #define  CAN_RDL0R_DATA2                     ((uint32_t)0x00FF0000)        /*!< Data byte 2 */
06405 #define  CAN_RDL0R_DATA3                     ((uint32_t)0xFF000000)        /*!< Data byte 3 */
06406
06407 /*******************  Bit definition for CAN_RDH0R register  ******************/
06408 #define  CAN_RDH0R_DATA4                     ((uint32_t)0x000000FF)        /*!< Data byte 4 */
06409 #define  CAN_RDH0R_DATA5                     ((uint32_t)0x0000FF00)        /*!< Data byte 5 */
06410 #define  CAN_RDH0R_DATA6                     ((uint32_t)0x00FF0000)        /*!< Data byte 6 */
06411 #define  CAN_RDH0R_DATA7                     ((uint32_t)0xFF000000)        /*!< Data byte 7 */
06412
06413 /*******************  Bit definition for CAN_RI1R register  *******************/
06414 #define  CAN_RI1R_RTR                        ((uint32_t)0x00000002)        /*!< Remote Transmission Request */
06415 #define  CAN_RI1R_IDE                        ((uint32_t)0x00000004)        /*!< Identifier Extension */
06416 #define  CAN_RI1R_EXID                       ((uint32_t)0x001FFFF8)        /*!< Extended identifier */
06417 #define  CAN_RI1R_STID                       ((uint32_t)0xFFE00000)        /*!< Standard Identifier or Extended Identifier */
06418
06419 /*******************  Bit definition for CAN_RDT1R register  ******************/
06420 #define  CAN_RDT1R_DLC                       ((uint32_t)0x0000000F)        /*!< Data Length Code */
06421 #define  CAN_RDT1R_FMI                       ((uint32_t)0x0000FF00)        /*!< Filter Match Index */
06422 #define  CAN_RDT1R_TIME                      ((uint32_t)0xFFFF0000)        /*!< Message Time Stamp */
06423
06424 /*******************  Bit definition for CAN_RDL1R register  ******************/
06425 #define  CAN_RDL1R_DATA0                     ((uint32_t)0x000000FF)        /*!< Data byte 0 */
06426 #define  CAN_RDL1R_DATA1                     ((uint32_t)0x0000FF00)        /*!< Data byte 1 */
06427 #define  CAN_RDL1R_DATA2                     ((uint32_t)0x00FF0000)        /*!< Data byte 2 */
06428 #define  CAN_RDL1R_DATA3                     ((uint32_t)0xFF000000)        /*!< Data byte 3 */
06429
06430 /*******************  Bit definition for CAN_RDH1R register  ******************/
06431 #define  CAN_RDH1R_DATA4                     ((uint32_t)0x000000FF)        /*!< Data byte 4 */
06432 #define  CAN_RDH1R_DATA5                     ((uint32_t)0x0000FF00)        /*!< Data byte 5 */
06433 #define  CAN_RDH1R_DATA6                     ((uint32_t)0x00FF0000)        /*!< Data byte 6 */
06434 #define  CAN_RDH1R_DATA7                     ((uint32_t)0xFF000000)        /*!< Data byte 7 */
06435
06436 /*!< CAN filter registers */
06437 /*******************  Bit definition for CAN_FMR register  ********************/
06438 #define  CAN_FMR_FINIT                       ((uint8_t)0x01)               /*!< Filter Init Mode */
06439
06440 /*******************  Bit definition for CAN_FM1R register  *******************/
06441 #define  CAN_FM1R_FBM                        ((uint16_t)0x3FFF)            /*!< Filter Mode */
06442 #define  CAN_FM1R_FBM0                       ((uint16_t)0x0001)            /*!< Filter Init Mode bit 0 */
06443 #define  CAN_FM1R_FBM1                       ((uint16_t)0x0002)            /*!< Filter Init Mode bit 1 */
06444 #define  CAN_FM1R_FBM2                       ((uint16_t)0x0004)            /*!< Filter Init Mode bit 2 */
06445 #define  CAN_FM1R_FBM3                       ((uint16_t)0x0008)            /*!< Filter Init Mode bit 3 */
06446 #define  CAN_FM1R_FBM4                       ((uint16_t)0x0010)            /*!< Filter Init Mode bit 4 */
06447 #define  CAN_FM1R_FBM5                       ((uint16_t)0x0020)            /*!< Filter Init Mode bit 5 */
06448 #define  CAN_FM1R_FBM6                       ((uint16_t)0x0040)            /*!< Filter Init Mode bit 6 */
06449 #define  CAN_FM1R_FBM7                       ((uint16_t)0x0080)            /*!< Filter Init Mode bit 7 */
06450 #define  CAN_FM1R_FBM8                       ((uint16_t)0x0100)            /*!< Filter Init Mode bit 8 */
06451 #define  CAN_FM1R_FBM9                       ((uint16_t)0x0200)            /*!< Filter Init Mode bit 9 */
06452 #define  CAN_FM1R_FBM10                      ((uint16_t)0x0400)            /*!< Filter Init Mode bit 10 */
06453 #define  CAN_FM1R_FBM11                      ((uint16_t)0x0800)            /*!< Filter Init Mode bit 11 */
06454 #define  CAN_FM1R_FBM12                      ((uint16_t)0x1000)            /*!< Filter Init Mode bit 12 */
06455 #define  CAN_FM1R_FBM13                      ((uint16_t)0x2000)            /*!< Filter Init Mode bit 13 */
06456
06457 /*******************  Bit definition for CAN_FS1R register  *******************/
06458 #define  CAN_FS1R_FSC                        ((uint16_t)0x3FFF)            /*!< Filter Scale Configuration */
06459 #define  CAN_FS1R_FSC0                       ((uint16_t)0x0001)            /*!< Filter Scale Configuration bit 0 */
06460 #define  CAN_FS1R_FSC1                       ((uint16_t)0x0002)            /*!< Filter Scale Configuration bit 1 */
06461 #define  CAN_FS1R_FSC2                       ((uint16_t)0x0004)            /*!< Filter Scale Configuration bit 2 */
06462 #define  CAN_FS1R_FSC3                       ((uint16_t)0x0008)            /*!< Filter Scale Configuration bit 3 */
06463 #define  CAN_FS1R_FSC4                       ((uint16_t)0x0010)            /*!< Filter Scale Configuration bit 4 */
06464 #define  CAN_FS1R_FSC5                       ((uint16_t)0x0020)            /*!< Filter Scale Configuration bit 5 */
06465 #define  CAN_FS1R_FSC6                       ((uint16_t)0x0040)            /*!< Filter Scale Configuration bit 6 */
06466 #define  CAN_FS1R_FSC7                       ((uint16_t)0x0080)            /*!< Filter Scale Configuration bit 7 */
06467 #define  CAN_FS1R_FSC8                       ((uint16_t)0x0100)            /*!< Filter Scale Configuration bit 8 */
06468 #define  CAN_FS1R_FSC9                       ((uint16_t)0x0200)            /*!< Filter Scale Configuration bit 9 */
06469 #define  CAN_FS1R_FSC10                      ((uint16_t)0x0400)            /*!< Filter Scale Configuration bit 10 */
06470 #define  CAN_FS1R_FSC11                      ((uint16_t)0x0800)            /*!< Filter Scale Configuration bit 11 */
06471 #define  CAN_FS1R_FSC12                      ((uint16_t)0x1000)            /*!< Filter Scale Configuration bit 12 */
06472 #define  CAN_FS1R_FSC13                      ((uint16_t)0x2000)            /*!< Filter Scale Configuration bit 13 */
06473
06474 /******************  Bit definition for CAN_FFA1R register  *******************/
06475 #define  CAN_FFA1R_FFA                       ((uint16_t)0x3FFF)            /*!< Filter FIFO Assignment */
06476 #define  CAN_FFA1R_FFA0                      ((uint16_t)0x0001)            /*!< Filter FIFO Assignment for Filter 0 */
06477 #define  CAN_FFA1R_FFA1                      ((uint16_t)0x0002)            /*!< Filter FIFO Assignment for Filter 1 */
06478 #define  CAN_FFA1R_FFA2                      ((uint16_t)0x0004)            /*!< Filter FIFO Assignment for Filter 2 */
06479 #define  CAN_FFA1R_FFA3                      ((uint16_t)0x0008)            /*!< Filter FIFO Assignment for Filter 3 */
06480 #define  CAN_FFA1R_FFA4                      ((uint16_t)0x0010)            /*!< Filter FIFO Assignment for Filter 4 */
06481 #define  CAN_FFA1R_FFA5                      ((uint16_t)0x0020)            /*!< Filter FIFO Assignment for Filter 5 */
06482 #define  CAN_FFA1R_FFA6                      ((uint16_t)0x0040)            /*!< Filter FIFO Assignment for Filter 6 */
06483 #define  CAN_FFA1R_FFA7                      ((uint16_t)0x0080)            /*!< Filter FIFO Assignment for Filter 7 */
06484 #define  CAN_FFA1R_FFA8                      ((uint16_t)0x0100)            /*!< Filter FIFO Assignment for Filter 8 */
06485 #define  CAN_FFA1R_FFA9                      ((uint16_t)0x0200)            /*!< Filter FIFO Assignment for Filter 9 */
06486 #define  CAN_FFA1R_FFA10                     ((uint16_t)0x0400)            /*!< Filter FIFO Assignment for Filter 10 */
06487 #define  CAN_FFA1R_FFA11                     ((uint16_t)0x0800)            /*!< Filter FIFO Assignment for Filter 11 */
06488 #define  CAN_FFA1R_FFA12                     ((uint16_t)0x1000)            /*!< Filter FIFO Assignment for Filter 12 */
06489 #define  CAN_FFA1R_FFA13                     ((uint16_t)0x2000)            /*!< Filter FIFO Assignment for Filter 13 */
06490
06491 /*******************  Bit definition for CAN_FA1R register  *******************/
06492 #define  CAN_FA1R_FACT                       ((uint16_t)0x3FFF)            /*!< Filter Active */
06493 #define  CAN_FA1R_FACT0                      ((uint16_t)0x0001)            /*!< Filter 0 Active */
06494 #define  CAN_FA1R_FACT1                      ((uint16_t)0x0002)            /*!< Filter 1 Active */
06495 #define  CAN_FA1R_FACT2                      ((uint16_t)0x0004)            /*!< Filter 2 Active */
06496 #define  CAN_FA1R_FACT3                      ((uint16_t)0x0008)            /*!< Filter 3 Active */
06497 #define  CAN_FA1R_FACT4                      ((uint16_t)0x0010)            /*!< Filter 4 Active */
06498 #define  CAN_FA1R_FACT5                      ((uint16_t)0x0020)            /*!< Filter 5 Active */
06499 #define  CAN_FA1R_FACT6                      ((uint16_t)0x0040)            /*!< Filter 6 Active */
06500 #define  CAN_FA1R_FACT7                      ((uint16_t)0x0080)            /*!< Filter 7 Active */
06501 #define  CAN_FA1R_FACT8                      ((uint16_t)0x0100)            /*!< Filter 8 Active */
06502 #define  CAN_FA1R_FACT9                      ((uint16_t)0x0200)            /*!< Filter 9 Active */
06503 #define  CAN_FA1R_FACT10                     ((uint16_t)0x0400)            /*!< Filter 10 Active */
06504 #define  CAN_FA1R_FACT11                     ((uint16_t)0x0800)            /*!< Filter 11 Active */
06505 #define  CAN_FA1R_FACT12                     ((uint16_t)0x1000)            /*!< Filter 12 Active */
06506 #define  CAN_FA1R_FACT13                     ((uint16_t)0x2000)            /*!< Filter 13 Active */
06507
06508 /*******************  Bit definition for CAN_F0R1 register  *******************/
06509 #define  CAN_F0R1_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
06510 #define  CAN_F0R1_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
06511 #define  CAN_F0R1_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
06512 #define  CAN_F0R1_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
06513 #define  CAN_F0R1_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
06514 #define  CAN_F0R1_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
06515 #define  CAN_F0R1_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
06516 #define  CAN_F0R1_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
06517 #define  CAN_F0R1_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
06518 #define  CAN_F0R1_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
06519 #define  CAN_F0R1_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
06520 #define  CAN_F0R1_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
06521 #define  CAN_F0R1_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
06522 #define  CAN_F0R1_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
06523 #define  CAN_F0R1_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
06524 #define  CAN_F0R1_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
06525 #define  CAN_F0R1_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
06526 #define  CAN_F0R1_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
06527 #define  CAN_F0R1_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
06528 #define  CAN_F0R1_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
06529 #define  CAN_F0R1_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
06530 #define  CAN_F0R1_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
06531 #define  CAN_F0R1_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
06532 #define  CAN_F0R1_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
06533 #define  CAN_F0R1_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
06534 #define  CAN_F0R1_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
06535 #define  CAN_F0R1_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
06536 #define  CAN_F0R1_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
06537 #define  CAN_F0R1_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
06538 #define  CAN_F0R1_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
06539 #define  CAN_F0R1_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
06540 #define  CAN_F0R1_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
06541
06542 /*******************  Bit definition for CAN_F1R1 register  *******************/
06543 #define  CAN_F1R1_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
06544 #define  CAN_F1R1_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
06545 #define  CAN_F1R1_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
06546 #define  CAN_F1R1_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
06547 #define  CAN_F1R1_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
06548 #define  CAN_F1R1_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
06549 #define  CAN_F1R1_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
06550 #define  CAN_F1R1_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
06551 #define  CAN_F1R1_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
06552 #define  CAN_F1R1_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
06553 #define  CAN_F1R1_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
06554 #define  CAN_F1R1_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
06555 #define  CAN_F1R1_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
06556 #define  CAN_F1R1_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
06557 #define  CAN_F1R1_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
06558 #define  CAN_F1R1_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
06559 #define  CAN_F1R1_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
06560 #define  CAN_F1R1_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
06561 #define  CAN_F1R1_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
06562 #define  CAN_F1R1_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
06563 #define  CAN_F1R1_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
06564 #define  CAN_F1R1_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
06565 #define  CAN_F1R1_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
06566 #define  CAN_F1R1_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
06567 #define  CAN_F1R1_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
06568 #define  CAN_F1R1_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
06569 #define  CAN_F1R1_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
06570 #define  CAN_F1R1_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
06571 #define  CAN_F1R1_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
06572 #define  CAN_F1R1_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
06573 #define  CAN_F1R1_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
06574 #define  CAN_F1R1_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
06575
06576 /*******************  Bit definition for CAN_F2R1 register  *******************/
06577 #define  CAN_F2R1_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
06578 #define  CAN_F2R1_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
06579 #define  CAN_F2R1_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
06580 #define  CAN_F2R1_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
06581 #define  CAN_F2R1_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
06582 #define  CAN_F2R1_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
06583 #define  CAN_F2R1_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
06584 #define  CAN_F2R1_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
06585 #define  CAN_F2R1_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
06586 #define  CAN_F2R1_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
06587 #define  CAN_F2R1_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
06588 #define  CAN_F2R1_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
06589 #define  CAN_F2R1_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
06590 #define  CAN_F2R1_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
06591 #define  CAN_F2R1_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
06592 #define  CAN_F2R1_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
06593 #define  CAN_F2R1_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
06594 #define  CAN_F2R1_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
06595 #define  CAN_F2R1_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
06596 #define  CAN_F2R1_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
06597 #define  CAN_F2R1_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
06598 #define  CAN_F2R1_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
06599 #define  CAN_F2R1_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
06600 #define  CAN_F2R1_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
06601 #define  CAN_F2R1_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
06602 #define  CAN_F2R1_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
06603 #define  CAN_F2R1_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
06604 #define  CAN_F2R1_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
06605 #define  CAN_F2R1_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
06606 #define  CAN_F2R1_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
06607 #define  CAN_F2R1_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
06608 #define  CAN_F2R1_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
06609
06610 /*******************  Bit definition for CAN_F3R1 register  *******************/
06611 #define  CAN_F3R1_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
06612 #define  CAN_F3R1_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
06613 #define  CAN_F3R1_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
06614 #define  CAN_F3R1_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
06615 #define  CAN_F3R1_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
06616 #define  CAN_F3R1_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
06617 #define  CAN_F3R1_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
06618 #define  CAN_F3R1_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
06619 #define  CAN_F3R1_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
06620 #define  CAN_F3R1_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
06621 #define  CAN_F3R1_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
06622 #define  CAN_F3R1_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
06623 #define  CAN_F3R1_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
06624 #define  CAN_F3R1_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
06625 #define  CAN_F3R1_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
06626 #define  CAN_F3R1_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
06627 #define  CAN_F3R1_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
06628 #define  CAN_F3R1_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
06629 #define  CAN_F3R1_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
06630 #define  CAN_F3R1_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
06631 #define  CAN_F3R1_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
06632 #define  CAN_F3R1_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
06633 #define  CAN_F3R1_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
06634 #define  CAN_F3R1_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
06635 #define  CAN_F3R1_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
06636 #define  CAN_F3R1_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
06637 #define  CAN_F3R1_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
06638 #define  CAN_F3R1_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
06639 #define  CAN_F3R1_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
06640 #define  CAN_F3R1_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
06641 #define  CAN_F3R1_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
06642 #define  CAN_F3R1_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
06643
06644 /*******************  Bit definition for CAN_F4R1 register  *******************/
06645 #define  CAN_F4R1_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
06646 #define  CAN_F4R1_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
06647 #define  CAN_F4R1_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
06648 #define  CAN_F4R1_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
06649 #define  CAN_F4R1_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
06650 #define  CAN_F4R1_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
06651 #define  CAN_F4R1_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
06652 #define  CAN_F4R1_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
06653 #define  CAN_F4R1_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
06654 #define  CAN_F4R1_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
06655 #define  CAN_F4R1_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
06656 #define  CAN_F4R1_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
06657 #define  CAN_F4R1_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
06658 #define  CAN_F4R1_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
06659 #define  CAN_F4R1_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
06660 #define  CAN_F4R1_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
06661 #define  CAN_F4R1_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
06662 #define  CAN_F4R1_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
06663 #define  CAN_F4R1_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
06664 #define  CAN_F4R1_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
06665 #define  CAN_F4R1_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
06666 #define  CAN_F4R1_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
06667 #define  CAN_F4R1_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
06668 #define  CAN_F4R1_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
06669 #define  CAN_F4R1_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
06670 #define  CAN_F4R1_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
06671 #define  CAN_F4R1_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
06672 #define  CAN_F4R1_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
06673 #define  CAN_F4R1_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
06674 #define  CAN_F4R1_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
06675 #define  CAN_F4R1_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
06676 #define  CAN_F4R1_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
06677
06678 /*******************  Bit definition for CAN_F5R1 register  *******************/
06679 #define  CAN_F5R1_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
06680 #define  CAN_F5R1_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
06681 #define  CAN_F5R1_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
06682 #define  CAN_F5R1_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
06683 #define  CAN_F5R1_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
06684 #define  CAN_F5R1_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
06685 #define  CAN_F5R1_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
06686 #define  CAN_F5R1_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
06687 #define  CAN_F5R1_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
06688 #define  CAN_F5R1_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
06689 #define  CAN_F5R1_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
06690 #define  CAN_F5R1_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
06691 #define  CAN_F5R1_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
06692 #define  CAN_F5R1_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
06693 #define  CAN_F5R1_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
06694 #define  CAN_F5R1_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
06695 #define  CAN_F5R1_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
06696 #define  CAN_F5R1_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
06697 #define  CAN_F5R1_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
06698 #define  CAN_F5R1_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
06699 #define  CAN_F5R1_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
06700 #define  CAN_F5R1_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
06701 #define  CAN_F5R1_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
06702 #define  CAN_F5R1_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
06703 #define  CAN_F5R1_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
06704 #define  CAN_F5R1_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
06705 #define  CAN_F5R1_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
06706 #define  CAN_F5R1_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
06707 #define  CAN_F5R1_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
06708 #define  CAN_F5R1_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
06709 #define  CAN_F5R1_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
06710 #define  CAN_F5R1_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
06711
06712 /*******************  Bit definition for CAN_F6R1 register  *******************/
06713 #define  CAN_F6R1_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
06714 #define  CAN_F6R1_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
06715 #define  CAN_F6R1_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
06716 #define  CAN_F6R1_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
06717 #define  CAN_F6R1_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
06718 #define  CAN_F6R1_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
06719 #define  CAN_F6R1_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
06720 #define  CAN_F6R1_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
06721 #define  CAN_F6R1_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
06722 #define  CAN_F6R1_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
06723 #define  CAN_F6R1_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
06724 #define  CAN_F6R1_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
06725 #define  CAN_F6R1_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
06726 #define  CAN_F6R1_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
06727 #define  CAN_F6R1_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
06728 #define  CAN_F6R1_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
06729 #define  CAN_F6R1_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
06730 #define  CAN_F6R1_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
06731 #define  CAN_F6R1_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
06732 #define  CAN_F6R1_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
06733 #define  CAN_F6R1_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
06734 #define  CAN_F6R1_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
06735 #define  CAN_F6R1_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
06736 #define  CAN_F6R1_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
06737 #define  CAN_F6R1_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
06738 #define  CAN_F6R1_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
06739 #define  CAN_F6R1_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
06740 #define  CAN_F6R1_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
06741 #define  CAN_F6R1_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
06742 #define  CAN_F6R1_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
06743 #define  CAN_F6R1_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
06744 #define  CAN_F6R1_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
06745
06746 /*******************  Bit definition for CAN_F7R1 register  *******************/
06747 #define  CAN_F7R1_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
06748 #define  CAN_F7R1_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
06749 #define  CAN_F7R1_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
06750 #define  CAN_F7R1_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
06751 #define  CAN_F7R1_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
06752 #define  CAN_F7R1_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
06753 #define  CAN_F7R1_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
06754 #define  CAN_F7R1_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
06755 #define  CAN_F7R1_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
06756 #define  CAN_F7R1_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
06757 #define  CAN_F7R1_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
06758 #define  CAN_F7R1_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
06759 #define  CAN_F7R1_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
06760 #define  CAN_F7R1_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
06761 #define  CAN_F7R1_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
06762 #define  CAN_F7R1_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
06763 #define  CAN_F7R1_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
06764 #define  CAN_F7R1_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
06765 #define  CAN_F7R1_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
06766 #define  CAN_F7R1_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
06767 #define  CAN_F7R1_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
06768 #define  CAN_F7R1_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
06769 #define  CAN_F7R1_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
06770 #define  CAN_F7R1_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
06771 #define  CAN_F7R1_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
06772 #define  CAN_F7R1_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
06773 #define  CAN_F7R1_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
06774 #define  CAN_F7R1_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
06775 #define  CAN_F7R1_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
06776 #define  CAN_F7R1_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
06777 #define  CAN_F7R1_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
06778 #define  CAN_F7R1_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
06779
06780 /*******************  Bit definition for CAN_F8R1 register  *******************/
06781 #define  CAN_F8R1_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
06782 #define  CAN_F8R1_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
06783 #define  CAN_F8R1_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
06784 #define  CAN_F8R1_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
06785 #define  CAN_F8R1_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
06786 #define  CAN_F8R1_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
06787 #define  CAN_F8R1_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
06788 #define  CAN_F8R1_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
06789 #define  CAN_F8R1_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
06790 #define  CAN_F8R1_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
06791 #define  CAN_F8R1_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
06792 #define  CAN_F8R1_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
06793 #define  CAN_F8R1_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
06794 #define  CAN_F8R1_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
06795 #define  CAN_F8R1_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
06796 #define  CAN_F8R1_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
06797 #define  CAN_F8R1_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
06798 #define  CAN_F8R1_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
06799 #define  CAN_F8R1_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
06800 #define  CAN_F8R1_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
06801 #define  CAN_F8R1_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
06802 #define  CAN_F8R1_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
06803 #define  CAN_F8R1_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
06804 #define  CAN_F8R1_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
06805 #define  CAN_F8R1_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
06806 #define  CAN_F8R1_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
06807 #define  CAN_F8R1_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
06808 #define  CAN_F8R1_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
06809 #define  CAN_F8R1_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
06810 #define  CAN_F8R1_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
06811 #define  CAN_F8R1_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
06812 #define  CAN_F8R1_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
06813
06814 /*******************  Bit definition for CAN_F9R1 register  *******************/
06815 #define  CAN_F9R1_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
06816 #define  CAN_F9R1_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
06817 #define  CAN_F9R1_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
06818 #define  CAN_F9R1_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
06819 #define  CAN_F9R1_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
06820 #define  CAN_F9R1_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
06821 #define  CAN_F9R1_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
06822 #define  CAN_F9R1_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
06823 #define  CAN_F9R1_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
06824 #define  CAN_F9R1_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
06825 #define  CAN_F9R1_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
06826 #define  CAN_F9R1_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
06827 #define  CAN_F9R1_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
06828 #define  CAN_F9R1_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
06829 #define  CAN_F9R1_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
06830 #define  CAN_F9R1_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
06831 #define  CAN_F9R1_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
06832 #define  CAN_F9R1_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
06833 #define  CAN_F9R1_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
06834 #define  CAN_F9R1_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
06835 #define  CAN_F9R1_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
06836 #define  CAN_F9R1_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
06837 #define  CAN_F9R1_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
06838 #define  CAN_F9R1_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
06839 #define  CAN_F9R1_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
06840 #define  CAN_F9R1_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
06841 #define  CAN_F9R1_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
06842 #define  CAN_F9R1_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
06843 #define  CAN_F9R1_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
06844 #define  CAN_F9R1_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
06845 #define  CAN_F9R1_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
06846 #define  CAN_F9R1_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
06847
06848 /*******************  Bit definition for CAN_F10R1 register  ******************/
06849 #define  CAN_F10R1_FB0                       ((uint32_t)0x00000001)        /*!< Filter bit 0 */
06850 #define  CAN_F10R1_FB1                       ((uint32_t)0x00000002)        /*!< Filter bit 1 */
06851 #define  CAN_F10R1_FB2                       ((uint32_t)0x00000004)        /*!< Filter bit 2 */
06852 #define  CAN_F10R1_FB3                       ((uint32_t)0x00000008)        /*!< Filter bit 3 */
06853 #define  CAN_F10R1_FB4                       ((uint32_t)0x00000010)        /*!< Filter bit 4 */
06854 #define  CAN_F10R1_FB5                       ((uint32_t)0x00000020)        /*!< Filter bit 5 */
06855 #define  CAN_F10R1_FB6                       ((uint32_t)0x00000040)        /*!< Filter bit 6 */
06856 #define  CAN_F10R1_FB7                       ((uint32_t)0x00000080)        /*!< Filter bit 7 */
06857 #define  CAN_F10R1_FB8                       ((uint32_t)0x00000100)        /*!< Filter bit 8 */
06858 #define  CAN_F10R1_FB9                       ((uint32_t)0x00000200)        /*!< Filter bit 9 */
06859 #define  CAN_F10R1_FB10                      ((uint32_t)0x00000400)        /*!< Filter bit 10 */
06860 #define  CAN_F10R1_FB11                      ((uint32_t)0x00000800)        /*!< Filter bit 11 */
06861 #define  CAN_F10R1_FB12                      ((uint32_t)0x00001000)        /*!< Filter bit 12 */
06862 #define  CAN_F10R1_FB13                      ((uint32_t)0x00002000)        /*!< Filter bit 13 */
06863 #define  CAN_F10R1_FB14                      ((uint32_t)0x00004000)        /*!< Filter bit 14 */
06864 #define  CAN_F10R1_FB15                      ((uint32_t)0x00008000)        /*!< Filter bit 15 */
06865 #define  CAN_F10R1_FB16                      ((uint32_t)0x00010000)        /*!< Filter bit 16 */
06866 #define  CAN_F10R1_FB17                      ((uint32_t)0x00020000)        /*!< Filter bit 17 */
06867 #define  CAN_F10R1_FB18                      ((uint32_t)0x00040000)        /*!< Filter bit 18 */
06868 #define  CAN_F10R1_FB19                      ((uint32_t)0x00080000)        /*!< Filter bit 19 */
06869 #define  CAN_F10R1_FB20                      ((uint32_t)0x00100000)        /*!< Filter bit 20 */
06870 #define  CAN_F10R1_FB21                      ((uint32_t)0x00200000)        /*!< Filter bit 21 */
06871 #define  CAN_F10R1_FB22                      ((uint32_t)0x00400000)        /*!< Filter bit 22 */
06872 #define  CAN_F10R1_FB23                      ((uint32_t)0x00800000)        /*!< Filter bit 23 */
06873 #define  CAN_F10R1_FB24                      ((uint32_t)0x01000000)        /*!< Filter bit 24 */
06874 #define  CAN_F10R1_FB25                      ((uint32_t)0x02000000)        /*!< Filter bit 25 */
06875 #define  CAN_F10R1_FB26                      ((uint32_t)0x04000000)        /*!< Filter bit 26 */
06876 #define  CAN_F10R1_FB27                      ((uint32_t)0x08000000)        /*!< Filter bit 27 */
06877 #define  CAN_F10R1_FB28                      ((uint32_t)0x10000000)        /*!< Filter bit 28 */
06878 #define  CAN_F10R1_FB29                      ((uint32_t)0x20000000)        /*!< Filter bit 29 */
06879 #define  CAN_F10R1_FB30                      ((uint32_t)0x40000000)        /*!< Filter bit 30 */
06880 #define  CAN_F10R1_FB31                      ((uint32_t)0x80000000)        /*!< Filter bit 31 */
06881
06882 /*******************  Bit definition for CAN_F11R1 register  ******************/
06883 #define  CAN_F11R1_FB0                       ((uint32_t)0x00000001)        /*!< Filter bit 0 */
06884 #define  CAN_F11R1_FB1                       ((uint32_t)0x00000002)        /*!< Filter bit 1 */
06885 #define  CAN_F11R1_FB2                       ((uint32_t)0x00000004)        /*!< Filter bit 2 */
06886 #define  CAN_F11R1_FB3                       ((uint32_t)0x00000008)        /*!< Filter bit 3 */
06887 #define  CAN_F11R1_FB4                       ((uint32_t)0x00000010)        /*!< Filter bit 4 */
06888 #define  CAN_F11R1_FB5                       ((uint32_t)0x00000020)        /*!< Filter bit 5 */
06889 #define  CAN_F11R1_FB6                       ((uint32_t)0x00000040)        /*!< Filter bit 6 */
06890 #define  CAN_F11R1_FB7                       ((uint32_t)0x00000080)        /*!< Filter bit 7 */
06891 #define  CAN_F11R1_FB8                       ((uint32_t)0x00000100)        /*!< Filter bit 8 */
06892 #define  CAN_F11R1_FB9                       ((uint32_t)0x00000200)        /*!< Filter bit 9 */
06893 #define  CAN_F11R1_FB10                      ((uint32_t)0x00000400)        /*!< Filter bit 10 */
06894 #define  CAN_F11R1_FB11                      ((uint32_t)0x00000800)        /*!< Filter bit 11 */
06895 #define  CAN_F11R1_FB12                      ((uint32_t)0x00001000)        /*!< Filter bit 12 */
06896 #define  CAN_F11R1_FB13                      ((uint32_t)0x00002000)        /*!< Filter bit 13 */
06897 #define  CAN_F11R1_FB14                      ((uint32_t)0x00004000)        /*!< Filter bit 14 */
06898 #define  CAN_F11R1_FB15                      ((uint32_t)0x00008000)        /*!< Filter bit 15 */
06899 #define  CAN_F11R1_FB16                      ((uint32_t)0x00010000)        /*!< Filter bit 16 */
06900 #define  CAN_F11R1_FB17                      ((uint32_t)0x00020000)        /*!< Filter bit 17 */
06901 #define  CAN_F11R1_FB18                      ((uint32_t)0x00040000)        /*!< Filter bit 18 */
06902 #define  CAN_F11R1_FB19                      ((uint32_t)0x00080000)        /*!< Filter bit 19 */
06903 #define  CAN_F11R1_FB20                      ((uint32_t)0x00100000)        /*!< Filter bit 20 */
06904 #define  CAN_F11R1_FB21                      ((uint32_t)0x00200000)        /*!< Filter bit 21 */
06905 #define  CAN_F11R1_FB22                      ((uint32_t)0x00400000)        /*!< Filter bit 22 */
06906 #define  CAN_F11R1_FB23                      ((uint32_t)0x00800000)        /*!< Filter bit 23 */
06907 #define  CAN_F11R1_FB24                      ((uint32_t)0x01000000)        /*!< Filter bit 24 */
06908 #define  CAN_F11R1_FB25                      ((uint32_t)0x02000000)        /*!< Filter bit 25 */
06909 #define  CAN_F11R1_FB26                      ((uint32_t)0x04000000)        /*!< Filter bit 26 */
06910 #define  CAN_F11R1_FB27                      ((uint32_t)0x08000000)        /*!< Filter bit 27 */
06911 #define  CAN_F11R1_FB28                      ((uint32_t)0x10000000)        /*!< Filter bit 28 */
06912 #define  CAN_F11R1_FB29                      ((uint32_t)0x20000000)        /*!< Filter bit 29 */
06913 #define  CAN_F11R1_FB30                      ((uint32_t)0x40000000)        /*!< Filter bit 30 */
06914 #define  CAN_F11R1_FB31                      ((uint32_t)0x80000000)        /*!< Filter bit 31 */
06915
06916 /*******************  Bit definition for CAN_F12R1 register  ******************/
06917 #define  CAN_F12R1_FB0                       ((uint32_t)0x00000001)        /*!< Filter bit 0 */
06918 #define  CAN_F12R1_FB1                       ((uint32_t)0x00000002)        /*!< Filter bit 1 */
06919 #define  CAN_F12R1_FB2                       ((uint32_t)0x00000004)        /*!< Filter bit 2 */
06920 #define  CAN_F12R1_FB3                       ((uint32_t)0x00000008)        /*!< Filter bit 3 */
06921 #define  CAN_F12R1_FB4                       ((uint32_t)0x00000010)        /*!< Filter bit 4 */
06922 #define  CAN_F12R1_FB5                       ((uint32_t)0x00000020)        /*!< Filter bit 5 */
06923 #define  CAN_F12R1_FB6                       ((uint32_t)0x00000040)        /*!< Filter bit 6 */
06924 #define  CAN_F12R1_FB7                       ((uint32_t)0x00000080)        /*!< Filter bit 7 */
06925 #define  CAN_F12R1_FB8                       ((uint32_t)0x00000100)        /*!< Filter bit 8 */
06926 #define  CAN_F12R1_FB9                       ((uint32_t)0x00000200)        /*!< Filter bit 9 */
06927 #define  CAN_F12R1_FB10                      ((uint32_t)0x00000400)        /*!< Filter bit 10 */
06928 #define  CAN_F12R1_FB11                      ((uint32_t)0x00000800)        /*!< Filter bit 11 */
06929 #define  CAN_F12R1_FB12                      ((uint32_t)0x00001000)        /*!< Filter bit 12 */
06930 #define  CAN_F12R1_FB13                      ((uint32_t)0x00002000)        /*!< Filter bit 13 */
06931 #define  CAN_F12R1_FB14                      ((uint32_t)0x00004000)        /*!< Filter bit 14 */
06932 #define  CAN_F12R1_FB15                      ((uint32_t)0x00008000)        /*!< Filter bit 15 */
06933 #define  CAN_F12R1_FB16                      ((uint32_t)0x00010000)        /*!< Filter bit 16 */
06934 #define  CAN_F12R1_FB17                      ((uint32_t)0x00020000)        /*!< Filter bit 17 */
06935 #define  CAN_F12R1_FB18                      ((uint32_t)0x00040000)        /*!< Filter bit 18 */
06936 #define  CAN_F12R1_FB19                      ((uint32_t)0x00080000)        /*!< Filter bit 19 */
06937 #define  CAN_F12R1_FB20                      ((uint32_t)0x00100000)        /*!< Filter bit 20 */
06938 #define  CAN_F12R1_FB21                      ((uint32_t)0x00200000)        /*!< Filter bit 21 */
06939 #define  CAN_F12R1_FB22                      ((uint32_t)0x00400000)        /*!< Filter bit 22 */
06940 #define  CAN_F12R1_FB23                      ((uint32_t)0x00800000)        /*!< Filter bit 23 */
06941 #define  CAN_F12R1_FB24                      ((uint32_t)0x01000000)        /*!< Filter bit 24 */
06942 #define  CAN_F12R1_FB25                      ((uint32_t)0x02000000)        /*!< Filter bit 25 */
06943 #define  CAN_F12R1_FB26                      ((uint32_t)0x04000000)        /*!< Filter bit 26 */
06944 #define  CAN_F12R1_FB27                      ((uint32_t)0x08000000)        /*!< Filter bit 27 */
06945 #define  CAN_F12R1_FB28                      ((uint32_t)0x10000000)        /*!< Filter bit 28 */
06946 #define  CAN_F12R1_FB29                      ((uint32_t)0x20000000)        /*!< Filter bit 29 */
06947 #define  CAN_F12R1_FB30                      ((uint32_t)0x40000000)        /*!< Filter bit 30 */
06948 #define  CAN_F12R1_FB31                      ((uint32_t)0x80000000)        /*!< Filter bit 31 */
06949
06950 /*******************  Bit definition for CAN_F13R1 register  ******************/
06951 #define  CAN_F13R1_FB0                       ((uint32_t)0x00000001)        /*!< Filter bit 0 */
06952 #define  CAN_F13R1_FB1                       ((uint32_t)0x00000002)        /*!< Filter bit 1 */
06953 #define  CAN_F13R1_FB2                       ((uint32_t)0x00000004)        /*!< Filter bit 2 */
06954 #define  CAN_F13R1_FB3                       ((uint32_t)0x00000008)        /*!< Filter bit 3 */
06955 #define  CAN_F13R1_FB4                       ((uint32_t)0x00000010)        /*!< Filter bit 4 */
06956 #define  CAN_F13R1_FB5                       ((uint32_t)0x00000020)        /*!< Filter bit 5 */
06957 #define  CAN_F13R1_FB6                       ((uint32_t)0x00000040)        /*!< Filter bit 6 */
06958 #define  CAN_F13R1_FB7                       ((uint32_t)0x00000080)        /*!< Filter bit 7 */
06959 #define  CAN_F13R1_FB8                       ((uint32_t)0x00000100)        /*!< Filter bit 8 */
06960 #define  CAN_F13R1_FB9                       ((uint32_t)0x00000200)        /*!< Filter bit 9 */
06961 #define  CAN_F13R1_FB10                      ((uint32_t)0x00000400)        /*!< Filter bit 10 */
06962 #define  CAN_F13R1_FB11                      ((uint32_t)0x00000800)        /*!< Filter bit 11 */
06963 #define  CAN_F13R1_FB12                      ((uint32_t)0x00001000)        /*!< Filter bit 12 */
06964 #define  CAN_F13R1_FB13                      ((uint32_t)0x00002000)        /*!< Filter bit 13 */
06965 #define  CAN_F13R1_FB14                      ((uint32_t)0x00004000)        /*!< Filter bit 14 */
06966 #define  CAN_F13R1_FB15                      ((uint32_t)0x00008000)        /*!< Filter bit 15 */
06967 #define  CAN_F13R1_FB16                      ((uint32_t)0x00010000)        /*!< Filter bit 16 */
06968 #define  CAN_F13R1_FB17                      ((uint32_t)0x00020000)        /*!< Filter bit 17 */
06969 #define  CAN_F13R1_FB18                      ((uint32_t)0x00040000)        /*!< Filter bit 18 */
06970 #define  CAN_F13R1_FB19                      ((uint32_t)0x00080000)        /*!< Filter bit 19 */
06971 #define  CAN_F13R1_FB20                      ((uint32_t)0x00100000)        /*!< Filter bit 20 */
06972 #define  CAN_F13R1_FB21                      ((uint32_t)0x00200000)        /*!< Filter bit 21 */
06973 #define  CAN_F13R1_FB22                      ((uint32_t)0x00400000)        /*!< Filter bit 22 */
06974 #define  CAN_F13R1_FB23                      ((uint32_t)0x00800000)        /*!< Filter bit 23 */
06975 #define  CAN_F13R1_FB24                      ((uint32_t)0x01000000)        /*!< Filter bit 24 */
06976 #define  CAN_F13R1_FB25                      ((uint32_t)0x02000000)        /*!< Filter bit 25 */
06977 #define  CAN_F13R1_FB26                      ((uint32_t)0x04000000)        /*!< Filter bit 26 */
06978 #define  CAN_F13R1_FB27                      ((uint32_t)0x08000000)        /*!< Filter bit 27 */
06979 #define  CAN_F13R1_FB28                      ((uint32_t)0x10000000)        /*!< Filter bit 28 */
06980 #define  CAN_F13R1_FB29                      ((uint32_t)0x20000000)        /*!< Filter bit 29 */
06981 #define  CAN_F13R1_FB30                      ((uint32_t)0x40000000)        /*!< Filter bit 30 */
06982 #define  CAN_F13R1_FB31                      ((uint32_t)0x80000000)        /*!< Filter bit 31 */
06983
06984 /*******************  Bit definition for CAN_F0R2 register  *******************/
06985 #define  CAN_F0R2_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
06986 #define  CAN_F0R2_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
06987 #define  CAN_F0R2_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
06988 #define  CAN_F0R2_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
06989 #define  CAN_F0R2_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
06990 #define  CAN_F0R2_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
06991 #define  CAN_F0R2_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
06992 #define  CAN_F0R2_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
06993 #define  CAN_F0R2_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
06994 #define  CAN_F0R2_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
06995 #define  CAN_F0R2_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
06996 #define  CAN_F0R2_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
06997 #define  CAN_F0R2_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
06998 #define  CAN_F0R2_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
06999 #define  CAN_F0R2_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
07000 #define  CAN_F0R2_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
07001 #define  CAN_F0R2_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
07002 #define  CAN_F0R2_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
07003 #define  CAN_F0R2_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
07004 #define  CAN_F0R2_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
07005 #define  CAN_F0R2_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
07006 #define  CAN_F0R2_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
07007 #define  CAN_F0R2_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
07008 #define  CAN_F0R2_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
07009 #define  CAN_F0R2_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
07010 #define  CAN_F0R2_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
07011 #define  CAN_F0R2_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
07012 #define  CAN_F0R2_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
07013 #define  CAN_F0R2_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
07014 #define  CAN_F0R2_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
07015 #define  CAN_F0R2_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
07016 #define  CAN_F0R2_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
07017
07018 /*******************  Bit definition for CAN_F1R2 register  *******************/
07019 #define  CAN_F1R2_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
07020 #define  CAN_F1R2_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
07021 #define  CAN_F1R2_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
07022 #define  CAN_F1R2_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
07023 #define  CAN_F1R2_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
07024 #define  CAN_F1R2_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
07025 #define  CAN_F1R2_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
07026 #define  CAN_F1R2_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
07027 #define  CAN_F1R2_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
07028 #define  CAN_F1R2_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
07029 #define  CAN_F1R2_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
07030 #define  CAN_F1R2_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
07031 #define  CAN_F1R2_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
07032 #define  CAN_F1R2_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
07033 #define  CAN_F1R2_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
07034 #define  CAN_F1R2_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
07035 #define  CAN_F1R2_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
07036 #define  CAN_F1R2_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
07037 #define  CAN_F1R2_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
07038 #define  CAN_F1R2_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
07039 #define  CAN_F1R2_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
07040 #define  CAN_F1R2_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
07041 #define  CAN_F1R2_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
07042 #define  CAN_F1R2_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
07043 #define  CAN_F1R2_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
07044 #define  CAN_F1R2_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
07045 #define  CAN_F1R2_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
07046 #define  CAN_F1R2_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
07047 #define  CAN_F1R2_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
07048 #define  CAN_F1R2_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
07049 #define  CAN_F1R2_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
07050 #define  CAN_F1R2_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
07051
07052 /*******************  Bit definition for CAN_F2R2 register  *******************/
07053 #define  CAN_F2R2_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
07054 #define  CAN_F2R2_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
07055 #define  CAN_F2R2_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
07056 #define  CAN_F2R2_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
07057 #define  CAN_F2R2_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
07058 #define  CAN_F2R2_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
07059 #define  CAN_F2R2_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
07060 #define  CAN_F2R2_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
07061 #define  CAN_F2R2_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
07062 #define  CAN_F2R2_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
07063 #define  CAN_F2R2_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
07064 #define  CAN_F2R2_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
07065 #define  CAN_F2R2_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
07066 #define  CAN_F2R2_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
07067 #define  CAN_F2R2_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
07068 #define  CAN_F2R2_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
07069 #define  CAN_F2R2_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
07070 #define  CAN_F2R2_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
07071 #define  CAN_F2R2_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
07072 #define  CAN_F2R2_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
07073 #define  CAN_F2R2_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
07074 #define  CAN_F2R2_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
07075 #define  CAN_F2R2_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
07076 #define  CAN_F2R2_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
07077 #define  CAN_F2R2_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
07078 #define  CAN_F2R2_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
07079 #define  CAN_F2R2_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
07080 #define  CAN_F2R2_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
07081 #define  CAN_F2R2_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
07082 #define  CAN_F2R2_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
07083 #define  CAN_F2R2_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
07084 #define  CAN_F2R2_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
07085
07086 /*******************  Bit definition for CAN_F3R2 register  *******************/
07087 #define  CAN_F3R2_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
07088 #define  CAN_F3R2_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
07089 #define  CAN_F3R2_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
07090 #define  CAN_F3R2_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
07091 #define  CAN_F3R2_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
07092 #define  CAN_F3R2_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
07093 #define  CAN_F3R2_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
07094 #define  CAN_F3R2_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
07095 #define  CAN_F3R2_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
07096 #define  CAN_F3R2_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
07097 #define  CAN_F3R2_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
07098 #define  CAN_F3R2_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
07099 #define  CAN_F3R2_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
07100 #define  CAN_F3R2_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
07101 #define  CAN_F3R2_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
07102 #define  CAN_F3R2_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
07103 #define  CAN_F3R2_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
07104 #define  CAN_F3R2_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
07105 #define  CAN_F3R2_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
07106 #define  CAN_F3R2_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
07107 #define  CAN_F3R2_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
07108 #define  CAN_F3R2_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
07109 #define  CAN_F3R2_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
07110 #define  CAN_F3R2_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
07111 #define  CAN_F3R2_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
07112 #define  CAN_F3R2_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
07113 #define  CAN_F3R2_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
07114 #define  CAN_F3R2_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
07115 #define  CAN_F3R2_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
07116 #define  CAN_F3R2_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
07117 #define  CAN_F3R2_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
07118 #define  CAN_F3R2_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
07119
07120 /*******************  Bit definition for CAN_F4R2 register  *******************/
07121 #define  CAN_F4R2_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
07122 #define  CAN_F4R2_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
07123 #define  CAN_F4R2_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
07124 #define  CAN_F4R2_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
07125 #define  CAN_F4R2_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
07126 #define  CAN_F4R2_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
07127 #define  CAN_F4R2_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
07128 #define  CAN_F4R2_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
07129 #define  CAN_F4R2_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
07130 #define  CAN_F4R2_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
07131 #define  CAN_F4R2_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
07132 #define  CAN_F4R2_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
07133 #define  CAN_F4R2_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
07134 #define  CAN_F4R2_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
07135 #define  CAN_F4R2_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
07136 #define  CAN_F4R2_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
07137 #define  CAN_F4R2_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
07138 #define  CAN_F4R2_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
07139 #define  CAN_F4R2_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
07140 #define  CAN_F4R2_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
07141 #define  CAN_F4R2_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
07142 #define  CAN_F4R2_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
07143 #define  CAN_F4R2_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
07144 #define  CAN_F4R2_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
07145 #define  CAN_F4R2_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
07146 #define  CAN_F4R2_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
07147 #define  CAN_F4R2_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
07148 #define  CAN_F4R2_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
07149 #define  CAN_F4R2_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
07150 #define  CAN_F4R2_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
07151 #define  CAN_F4R2_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
07152 #define  CAN_F4R2_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
07153
07154 /*******************  Bit definition for CAN_F5R2 register  *******************/
07155 #define  CAN_F5R2_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
07156 #define  CAN_F5R2_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
07157 #define  CAN_F5R2_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
07158 #define  CAN_F5R2_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
07159 #define  CAN_F5R2_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
07160 #define  CAN_F5R2_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
07161 #define  CAN_F5R2_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
07162 #define  CAN_F5R2_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
07163 #define  CAN_F5R2_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
07164 #define  CAN_F5R2_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
07165 #define  CAN_F5R2_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
07166 #define  CAN_F5R2_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
07167 #define  CAN_F5R2_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
07168 #define  CAN_F5R2_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
07169 #define  CAN_F5R2_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
07170 #define  CAN_F5R2_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
07171 #define  CAN_F5R2_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
07172 #define  CAN_F5R2_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
07173 #define  CAN_F5R2_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
07174 #define  CAN_F5R2_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
07175 #define  CAN_F5R2_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
07176 #define  CAN_F5R2_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
07177 #define  CAN_F5R2_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
07178 #define  CAN_F5R2_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
07179 #define  CAN_F5R2_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
07180 #define  CAN_F5R2_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
07181 #define  CAN_F5R2_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
07182 #define  CAN_F5R2_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
07183 #define  CAN_F5R2_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
07184 #define  CAN_F5R2_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
07185 #define  CAN_F5R2_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
07186 #define  CAN_F5R2_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
07187
07188 /*******************  Bit definition for CAN_F6R2 register  *******************/
07189 #define  CAN_F6R2_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
07190 #define  CAN_F6R2_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
07191 #define  CAN_F6R2_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
07192 #define  CAN_F6R2_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
07193 #define  CAN_F6R2_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
07194 #define  CAN_F6R2_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
07195 #define  CAN_F6R2_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
07196 #define  CAN_F6R2_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
07197 #define  CAN_F6R2_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
07198 #define  CAN_F6R2_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
07199 #define  CAN_F6R2_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
07200 #define  CAN_F6R2_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
07201 #define  CAN_F6R2_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
07202 #define  CAN_F6R2_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
07203 #define  CAN_F6R2_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
07204 #define  CAN_F6R2_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
07205 #define  CAN_F6R2_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
07206 #define  CAN_F6R2_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
07207 #define  CAN_F6R2_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
07208 #define  CAN_F6R2_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
07209 #define  CAN_F6R2_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
07210 #define  CAN_F6R2_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
07211 #define  CAN_F6R2_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
07212 #define  CAN_F6R2_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
07213 #define  CAN_F6R2_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
07214 #define  CAN_F6R2_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
07215 #define  CAN_F6R2_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
07216 #define  CAN_F6R2_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
07217 #define  CAN_F6R2_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
07218 #define  CAN_F6R2_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
07219 #define  CAN_F6R2_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
07220 #define  CAN_F6R2_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
07221
07222 /*******************  Bit definition for CAN_F7R2 register  *******************/
07223 #define  CAN_F7R2_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
07224 #define  CAN_F7R2_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
07225 #define  CAN_F7R2_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
07226 #define  CAN_F7R2_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
07227 #define  CAN_F7R2_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
07228 #define  CAN_F7R2_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
07229 #define  CAN_F7R2_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
07230 #define  CAN_F7R2_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
07231 #define  CAN_F7R2_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
07232 #define  CAN_F7R2_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
07233 #define  CAN_F7R2_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
07234 #define  CAN_F7R2_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
07235 #define  CAN_F7R2_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
07236 #define  CAN_F7R2_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
07237 #define  CAN_F7R2_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
07238 #define  CAN_F7R2_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
07239 #define  CAN_F7R2_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
07240 #define  CAN_F7R2_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
07241 #define  CAN_F7R2_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
07242 #define  CAN_F7R2_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
07243 #define  CAN_F7R2_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
07244 #define  CAN_F7R2_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
07245 #define  CAN_F7R2_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
07246 #define  CAN_F7R2_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
07247 #define  CAN_F7R2_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
07248 #define  CAN_F7R2_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
07249 #define  CAN_F7R2_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
07250 #define  CAN_F7R2_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
07251 #define  CAN_F7R2_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
07252 #define  CAN_F7R2_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
07253 #define  CAN_F7R2_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
07254 #define  CAN_F7R2_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
07255
07256 /*******************  Bit definition for CAN_F8R2 register  *******************/
07257 #define  CAN_F8R2_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
07258 #define  CAN_F8R2_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
07259 #define  CAN_F8R2_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
07260 #define  CAN_F8R2_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
07261 #define  CAN_F8R2_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
07262 #define  CAN_F8R2_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
07263 #define  CAN_F8R2_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
07264 #define  CAN_F8R2_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
07265 #define  CAN_F8R2_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
07266 #define  CAN_F8R2_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
07267 #define  CAN_F8R2_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
07268 #define  CAN_F8R2_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
07269 #define  CAN_F8R2_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
07270 #define  CAN_F8R2_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
07271 #define  CAN_F8R2_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
07272 #define  CAN_F8R2_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
07273 #define  CAN_F8R2_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
07274 #define  CAN_F8R2_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
07275 #define  CAN_F8R2_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
07276 #define  CAN_F8R2_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
07277 #define  CAN_F8R2_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
07278 #define  CAN_F8R2_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
07279 #define  CAN_F8R2_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
07280 #define  CAN_F8R2_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
07281 #define  CAN_F8R2_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
07282 #define  CAN_F8R2_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
07283 #define  CAN_F8R2_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
07284 #define  CAN_F8R2_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
07285 #define  CAN_F8R2_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
07286 #define  CAN_F8R2_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
07287 #define  CAN_F8R2_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
07288 #define  CAN_F8R2_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
07289
07290 /*******************  Bit definition for CAN_F9R2 register  *******************/
07291 #define  CAN_F9R2_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
07292 #define  CAN_F9R2_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
07293 #define  CAN_F9R2_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
07294 #define  CAN_F9R2_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
07295 #define  CAN_F9R2_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
07296 #define  CAN_F9R2_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
07297 #define  CAN_F9R2_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
07298 #define  CAN_F9R2_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
07299 #define  CAN_F9R2_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
07300 #define  CAN_F9R2_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
07301 #define  CAN_F9R2_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
07302 #define  CAN_F9R2_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
07303 #define  CAN_F9R2_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
07304 #define  CAN_F9R2_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
07305 #define  CAN_F9R2_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
07306 #define  CAN_F9R2_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
07307 #define  CAN_F9R2_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
07308 #define  CAN_F9R2_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
07309 #define  CAN_F9R2_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
07310 #define  CAN_F9R2_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
07311 #define  CAN_F9R2_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
07312 #define  CAN_F9R2_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
07313 #define  CAN_F9R2_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
07314 #define  CAN_F9R2_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
07315 #define  CAN_F9R2_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
07316 #define  CAN_F9R2_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
07317 #define  CAN_F9R2_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
07318 #define  CAN_F9R2_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
07319 #define  CAN_F9R2_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
07320 #define  CAN_F9R2_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
07321 #define  CAN_F9R2_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
07322 #define  CAN_F9R2_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
07323
07324 /*******************  Bit definition for CAN_F10R2 register  ******************/
07325 #define  CAN_F10R2_FB0                       ((uint32_t)0x00000001)        /*!< Filter bit 0 */
07326 #define  CAN_F10R2_FB1                       ((uint32_t)0x00000002)        /*!< Filter bit 1 */
07327 #define  CAN_F10R2_FB2                       ((uint32_t)0x00000004)        /*!< Filter bit 2 */
07328 #define  CAN_F10R2_FB3                       ((uint32_t)0x00000008)        /*!< Filter bit 3 */
07329 #define  CAN_F10R2_FB4                       ((uint32_t)0x00000010)        /*!< Filter bit 4 */
07330 #define  CAN_F10R2_FB5                       ((uint32_t)0x00000020)        /*!< Filter bit 5 */
07331 #define  CAN_F10R2_FB6                       ((uint32_t)0x00000040)        /*!< Filter bit 6 */
07332 #define  CAN_F10R2_FB7                       ((uint32_t)0x00000080)        /*!< Filter bit 7 */
07333 #define  CAN_F10R2_FB8                       ((uint32_t)0x00000100)        /*!< Filter bit 8 */
07334 #define  CAN_F10R2_FB9                       ((uint32_t)0x00000200)        /*!< Filter bit 9 */
07335 #define  CAN_F10R2_FB10                      ((uint32_t)0x00000400)        /*!< Filter bit 10 */
07336 #define  CAN_F10R2_FB11                      ((uint32_t)0x00000800)        /*!< Filter bit 11 */
07337 #define  CAN_F10R2_FB12                      ((uint32_t)0x00001000)        /*!< Filter bit 12 */
07338 #define  CAN_F10R2_FB13                      ((uint32_t)0x00002000)        /*!< Filter bit 13 */
07339 #define  CAN_F10R2_FB14                      ((uint32_t)0x00004000)        /*!< Filter bit 14 */
07340 #define  CAN_F10R2_FB15                      ((uint32_t)0x00008000)        /*!< Filter bit 15 */
07341 #define  CAN_F10R2_FB16                      ((uint32_t)0x00010000)        /*!< Filter bit 16 */
07342 #define  CAN_F10R2_FB17                      ((uint32_t)0x00020000)        /*!< Filter bit 17 */
07343 #define  CAN_F10R2_FB18                      ((uint32_t)0x00040000)        /*!< Filter bit 18 */
07344 #define  CAN_F10R2_FB19                      ((uint32_t)0x00080000)        /*!< Filter bit 19 */
07345 #define  CAN_F10R2_FB20                      ((uint32_t)0x00100000)        /*!< Filter bit 20 */
07346 #define  CAN_F10R2_FB21                      ((uint32_t)0x00200000)        /*!< Filter bit 21 */
07347 #define  CAN_F10R2_FB22                      ((uint32_t)0x00400000)        /*!< Filter bit 22 */
07348 #define  CAN_F10R2_FB23                      ((uint32_t)0x00800000)        /*!< Filter bit 23 */
07349 #define  CAN_F10R2_FB24                      ((uint32_t)0x01000000)        /*!< Filter bit 24 */
07350 #define  CAN_F10R2_FB25                      ((uint32_t)0x02000000)        /*!< Filter bit 25 */
07351 #define  CAN_F10R2_FB26                      ((uint32_t)0x04000000)        /*!< Filter bit 26 */
07352 #define  CAN_F10R2_FB27                      ((uint32_t)0x08000000)        /*!< Filter bit 27 */
07353 #define  CAN_F10R2_FB28                      ((uint32_t)0x10000000)        /*!< Filter bit 28 */
07354 #define  CAN_F10R2_FB29                      ((uint32_t)0x20000000)        /*!< Filter bit 29 */
07355 #define  CAN_F10R2_FB30                      ((uint32_t)0x40000000)        /*!< Filter bit 30 */
07356 #define  CAN_F10R2_FB31                      ((uint32_t)0x80000000)        /*!< Filter bit 31 */
07357
07358 /*******************  Bit definition for CAN_F11R2 register  ******************/
07359 #define  CAN_F11R2_FB0                       ((uint32_t)0x00000001)        /*!< Filter bit 0 */
07360 #define  CAN_F11R2_FB1                       ((uint32_t)0x00000002)        /*!< Filter bit 1 */
07361 #define  CAN_F11R2_FB2                       ((uint32_t)0x00000004)        /*!< Filter bit 2 */
07362 #define  CAN_F11R2_FB3                       ((uint32_t)0x00000008)        /*!< Filter bit 3 */
07363 #define  CAN_F11R2_FB4                       ((uint32_t)0x00000010)        /*!< Filter bit 4 */
07364 #define  CAN_F11R2_FB5                       ((uint32_t)0x00000020)        /*!< Filter bit 5 */
07365 #define  CAN_F11R2_FB6                       ((uint32_t)0x00000040)        /*!< Filter bit 6 */
07366 #define  CAN_F11R2_FB7                       ((uint32_t)0x00000080)        /*!< Filter bit 7 */
07367 #define  CAN_F11R2_FB8                       ((uint32_t)0x00000100)        /*!< Filter bit 8 */
07368 #define  CAN_F11R2_FB9                       ((uint32_t)0x00000200)        /*!< Filter bit 9 */
07369 #define  CAN_F11R2_FB10                      ((uint32_t)0x00000400)        /*!< Filter bit 10 */
07370 #define  CAN_F11R2_FB11                      ((uint32_t)0x00000800)        /*!< Filter bit 11 */
07371 #define  CAN_F11R2_FB12                      ((uint32_t)0x00001000)        /*!< Filter bit 12 */
07372 #define  CAN_F11R2_FB13                      ((uint32_t)0x00002000)        /*!< Filter bit 13 */
07373 #define  CAN_F11R2_FB14                      ((uint32_t)0x00004000)        /*!< Filter bit 14 */
07374 #define  CAN_F11R2_FB15                      ((uint32_t)0x00008000)        /*!< Filter bit 15 */
07375 #define  CAN_F11R2_FB16                      ((uint32_t)0x00010000)        /*!< Filter bit 16 */
07376 #define  CAN_F11R2_FB17                      ((uint32_t)0x00020000)        /*!< Filter bit 17 */
07377 #define  CAN_F11R2_FB18                      ((uint32_t)0x00040000)        /*!< Filter bit 18 */
07378 #define  CAN_F11R2_FB19                      ((uint32_t)0x00080000)        /*!< Filter bit 19 */
07379 #define  CAN_F11R2_FB20                      ((uint32_t)0x00100000)        /*!< Filter bit 20 */
07380 #define  CAN_F11R2_FB21                      ((uint32_t)0x00200000)        /*!< Filter bit 21 */
07381 #define  CAN_F11R2_FB22                      ((uint32_t)0x00400000)        /*!< Filter bit 22 */
07382 #define  CAN_F11R2_FB23                      ((uint32_t)0x00800000)        /*!< Filter bit 23 */
07383 #define  CAN_F11R2_FB24                      ((uint32_t)0x01000000)        /*!< Filter bit 24 */
07384 #define  CAN_F11R2_FB25                      ((uint32_t)0x02000000)        /*!< Filter bit 25 */
07385 #define  CAN_F11R2_FB26                      ((uint32_t)0x04000000)        /*!< Filter bit 26 */
07386 #define  CAN_F11R2_FB27                      ((uint32_t)0x08000000)        /*!< Filter bit 27 */
07387 #define  CAN_F11R2_FB28                      ((uint32_t)0x10000000)        /*!< Filter bit 28 */
07388 #define  CAN_F11R2_FB29                      ((uint32_t)0x20000000)        /*!< Filter bit 29 */
07389 #define  CAN_F11R2_FB30                      ((uint32_t)0x40000000)        /*!< Filter bit 30 */
07390 #define  CAN_F11R2_FB31                      ((uint32_t)0x80000000)        /*!< Filter bit 31 */
07391
07392 /*******************  Bit definition for CAN_F12R2 register  ******************/
07393 #define  CAN_F12R2_FB0                       ((uint32_t)0x00000001)        /*!< Filter bit 0 */
07394 #define  CAN_F12R2_FB1                       ((uint32_t)0x00000002)        /*!< Filter bit 1 */
07395 #define  CAN_F12R2_FB2                       ((uint32_t)0x00000004)        /*!< Filter bit 2 */
07396 #define  CAN_F12R2_FB3                       ((uint32_t)0x00000008)        /*!< Filter bit 3 */
07397 #define  CAN_F12R2_FB4                       ((uint32_t)0x00000010)        /*!< Filter bit 4 */
07398 #define  CAN_F12R2_FB5                       ((uint32_t)0x00000020)        /*!< Filter bit 5 */
07399 #define  CAN_F12R2_FB6                       ((uint32_t)0x00000040)        /*!< Filter bit 6 */
07400 #define  CAN_F12R2_FB7                       ((uint32_t)0x00000080)        /*!< Filter bit 7 */
07401 #define  CAN_F12R2_FB8                       ((uint32_t)0x00000100)        /*!< Filter bit 8 */
07402 #define  CAN_F12R2_FB9                       ((uint32_t)0x00000200)        /*!< Filter bit 9 */
07403 #define  CAN_F12R2_FB10                      ((uint32_t)0x00000400)        /*!< Filter bit 10 */
07404 #define  CAN_F12R2_FB11                      ((uint32_t)0x00000800)        /*!< Filter bit 11 */
07405 #define  CAN_F12R2_FB12                      ((uint32_t)0x00001000)        /*!< Filter bit 12 */
07406 #define  CAN_F12R2_FB13                      ((uint32_t)0x00002000)        /*!< Filter bit 13 */
07407 #define  CAN_F12R2_FB14                      ((uint32_t)0x00004000)        /*!< Filter bit 14 */
07408 #define  CAN_F12R2_FB15                      ((uint32_t)0x00008000)        /*!< Filter bit 15 */
07409 #define  CAN_F12R2_FB16                      ((uint32_t)0x00010000)        /*!< Filter bit 16 */
07410 #define  CAN_F12R2_FB17                      ((uint32_t)0x00020000)        /*!< Filter bit 17 */
07411 #define  CAN_F12R2_FB18                      ((uint32_t)0x00040000)        /*!< Filter bit 18 */
07412 #define  CAN_F12R2_FB19                      ((uint32_t)0x00080000)        /*!< Filter bit 19 */
07413 #define  CAN_F12R2_FB20                      ((uint32_t)0x00100000)        /*!< Filter bit 20 */
07414 #define  CAN_F12R2_FB21                      ((uint32_t)0x00200000)        /*!< Filter bit 21 */
07415 #define  CAN_F12R2_FB22                      ((uint32_t)0x00400000)        /*!< Filter bit 22 */
07416 #define  CAN_F12R2_FB23                      ((uint32_t)0x00800000)        /*!< Filter bit 23 */
07417 #define  CAN_F12R2_FB24                      ((uint32_t)0x01000000)        /*!< Filter bit 24 */
07418 #define  CAN_F12R2_FB25                      ((uint32_t)0x02000000)        /*!< Filter bit 25 */
07419 #define  CAN_F12R2_FB26                      ((uint32_t)0x04000000)        /*!< Filter bit 26 */
07420 #define  CAN_F12R2_FB27                      ((uint32_t)0x08000000)        /*!< Filter bit 27 */
07421 #define  CAN_F12R2_FB28                      ((uint32_t)0x10000000)        /*!< Filter bit 28 */
07422 #define  CAN_F12R2_FB29                      ((uint32_t)0x20000000)        /*!< Filter bit 29 */
07423 #define  CAN_F12R2_FB30                      ((uint32_t)0x40000000)        /*!< Filter bit 30 */
07424 #define  CAN_F12R2_FB31                      ((uint32_t)0x80000000)        /*!< Filter bit 31 */
07425
07426 /*******************  Bit definition for CAN_F13R2 register  ******************/
07427 #define  CAN_F13R2_FB0                       ((uint32_t)0x00000001)        /*!< Filter bit 0 */
07428 #define  CAN_F13R2_FB1                       ((uint32_t)0x00000002)        /*!< Filter bit 1 */
07429 #define  CAN_F13R2_FB2                       ((uint32_t)0x00000004)        /*!< Filter bit 2 */
07430 #define  CAN_F13R2_FB3                       ((uint32_t)0x00000008)        /*!< Filter bit 3 */
07431 #define  CAN_F13R2_FB4                       ((uint32_t)0x00000010)        /*!< Filter bit 4 */
07432 #define  CAN_F13R2_FB5                       ((uint32_t)0x00000020)        /*!< Filter bit 5 */
07433 #define  CAN_F13R2_FB6                       ((uint32_t)0x00000040)        /*!< Filter bit 6 */
07434 #define  CAN_F13R2_FB7                       ((uint32_t)0x00000080)        /*!< Filter bit 7 */
07435 #define  CAN_F13R2_FB8                       ((uint32_t)0x00000100)        /*!< Filter bit 8 */
07436 #define  CAN_F13R2_FB9                       ((uint32_t)0x00000200)        /*!< Filter bit 9 */
07437 #define  CAN_F13R2_FB10                      ((uint32_t)0x00000400)        /*!< Filter bit 10 */
07438 #define  CAN_F13R2_FB11                      ((uint32_t)0x00000800)        /*!< Filter bit 11 */
07439 #define  CAN_F13R2_FB12                      ((uint32_t)0x00001000)        /*!< Filter bit 12 */
07440 #define  CAN_F13R2_FB13                      ((uint32_t)0x00002000)        /*!< Filter bit 13 */
07441 #define  CAN_F13R2_FB14                      ((uint32_t)0x00004000)        /*!< Filter bit 14 */
07442 #define  CAN_F13R2_FB15                      ((uint32_t)0x00008000)        /*!< Filter bit 15 */
07443 #define  CAN_F13R2_FB16                      ((uint32_t)0x00010000)        /*!< Filter bit 16 */
07444 #define  CAN_F13R2_FB17                      ((uint32_t)0x00020000)        /*!< Filter bit 17 */
07445 #define  CAN_F13R2_FB18                      ((uint32_t)0x00040000)        /*!< Filter bit 18 */
07446 #define  CAN_F13R2_FB19                      ((uint32_t)0x00080000)        /*!< Filter bit 19 */
07447 #define  CAN_F13R2_FB20                      ((uint32_t)0x00100000)        /*!< Filter bit 20 */
07448 #define  CAN_F13R2_FB21                      ((uint32_t)0x00200000)        /*!< Filter bit 21 */
07449 #define  CAN_F13R2_FB22                      ((uint32_t)0x00400000)        /*!< Filter bit 22 */
07450 #define  CAN_F13R2_FB23                      ((uint32_t)0x00800000)        /*!< Filter bit 23 */
07451 #define  CAN_F13R2_FB24                      ((uint32_t)0x01000000)        /*!< Filter bit 24 */
07452 #define  CAN_F13R2_FB25                      ((uint32_t)0x02000000)        /*!< Filter bit 25 */
07453 #define  CAN_F13R2_FB26                      ((uint32_t)0x04000000)        /*!< Filter bit 26 */
07454 #define  CAN_F13R2_FB27                      ((uint32_t)0x08000000)        /*!< Filter bit 27 */
07455 #define  CAN_F13R2_FB28                      ((uint32_t)0x10000000)        /*!< Filter bit 28 */
07456 #define  CAN_F13R2_FB29                      ((uint32_t)0x20000000)        /*!< Filter bit 29 */
07457 #define  CAN_F13R2_FB30                      ((uint32_t)0x40000000)        /*!< Filter bit 30 */
07458 #define  CAN_F13R2_FB31                      ((uint32_t)0x80000000)        /*!< Filter bit 31 */
07459
07460 /******************************************************************************/
07461 /*                                                                            */
07462 /*                        Serial Peripheral Interface                         */
07463 /*                                                                            */
07464 /******************************************************************************/
07465
07466 /*******************  Bit definition for SPI_CR1 register  ********************/
07467 #define  SPI_CR1_CPHA                        ((uint16_t)0x0001)            /*!< Clock Phase */
07468 #define  SPI_CR1_CPOL                        ((uint16_t)0x0002)            /*!< Clock Polarity */
07469 #define  SPI_CR1_MSTR                        ((uint16_t)0x0004)            /*!< Master Selection */
07470
07471 #define  SPI_CR1_BR                          ((uint16_t)0x0038)            /*!< BR[2:0] bits (Baud Rate Control) */
07472 #define  SPI_CR1_BR_0                        ((uint16_t)0x0008)            /*!< Bit 0 */
07473 #define  SPI_CR1_BR_1                        ((uint16_t)0x0010)            /*!< Bit 1 */
07474 #define  SPI_CR1_BR_2                        ((uint16_t)0x0020)            /*!< Bit 2 */
07475
07476 #define  SPI_CR1_SPE                         ((uint16_t)0x0040)            /*!< SPI Enable */
07477 #define  SPI_CR1_LSBFIRST                    ((uint16_t)0x0080)            /*!< Frame Format */
07478 #define  SPI_CR1_SSI                         ((uint16_t)0x0100)            /*!< Internal slave select */
07479 #define  SPI_CR1_SSM                         ((uint16_t)0x0200)            /*!< Software slave management */
07480 #define  SPI_CR1_RXONLY                      ((uint16_t)0x0400)            /*!< Receive only */
07481 #define  SPI_CR1_DFF                         ((uint16_t)0x0800)            /*!< Data Frame Format */
07482 #define  SPI_CR1_CRCNEXT                     ((uint16_t)0x1000)            /*!< Transmit CRC next */
07483 #define  SPI_CR1_CRCEN                       ((uint16_t)0x2000)            /*!< Hardware CRC calculation enable */
07484 #define  SPI_CR1_BIDIOE                      ((uint16_t)0x4000)            /*!< Output enable in bidirectional mode */
07485 #define  SPI_CR1_BIDIMODE                    ((uint16_t)0x8000)            /*!< Bidirectional data mode enable */
07486
07487 /*******************  Bit definition for SPI_CR2 register  ********************/
07488 #define  SPI_CR2_RXDMAEN                     ((uint8_t)0x01)               /*!< Rx Buffer DMA Enable */
07489 #define  SPI_CR2_TXDMAEN                     ((uint8_t)0x02)               /*!< Tx Buffer DMA Enable */
07490 #define  SPI_CR2_SSOE                        ((uint8_t)0x04)               /*!< SS Output Enable */
07491 #define  SPI_CR2_ERRIE                       ((uint8_t)0x20)               /*!< Error Interrupt Enable */
07492 #define  SPI_CR2_RXNEIE                      ((uint8_t)0x40)               /*!< RX buffer Not Empty Interrupt Enable */
07493 #define  SPI_CR2_TXEIE                       ((uint8_t)0x80)               /*!< Tx buffer Empty Interrupt Enable */
07494
07495 /********************  Bit definition for SPI_SR register  ********************/
07496 #define  SPI_SR_RXNE                         ((uint8_t)0x01)               /*!< Receive buffer Not Empty */
07497 #define  SPI_SR_TXE                          ((uint8_t)0x02)               /*!< Transmit buffer Empty */
07498 #define  SPI_SR_CHSIDE                       ((uint8_t)0x04)               /*!< Channel side */
07499 #define  SPI_SR_UDR                          ((uint8_t)0x08)               /*!< Underrun flag */
07500 #define  SPI_SR_CRCERR                       ((uint8_t)0x10)               /*!< CRC Error flag */
07501 #define  SPI_SR_MODF                         ((uint8_t)0x20)               /*!< Mode fault */
07502 #define  SPI_SR_OVR                          ((uint8_t)0x40)               /*!< Overrun flag */
07503 #define  SPI_SR_BSY                          ((uint8_t)0x80)               /*!< Busy flag */
07504
07505 /********************  Bit definition for SPI_DR register  ********************/
07506 #define  SPI_DR_DR                           ((uint16_t)0xFFFF)            /*!< Data Register */
07507
07508 /*******************  Bit definition for SPI_CRCPR register  ******************/
07509 #define  SPI_CRCPR_CRCPOLY                   ((uint16_t)0xFFFF)            /*!< CRC polynomial register */
07510
07511 /******************  Bit definition for SPI_RXCRCR register  ******************/
07512 #define  SPI_RXCRCR_RXCRC                    ((uint16_t)0xFFFF)            /*!< Rx CRC Register */
07513
07514 /******************  Bit definition for SPI_TXCRCR register  ******************/
07515 #define  SPI_TXCRCR_TXCRC                    ((uint16_t)0xFFFF)            /*!< Tx CRC Register */
07516
07517 /******************  Bit definition for SPI_I2SCFGR register  *****************/
07518 #define  SPI_I2SCFGR_CHLEN                   ((uint16_t)0x0001)            /*!< Channel length (number of bits per audio channel) */
07519
07520 #define  SPI_I2SCFGR_DATLEN                  ((uint16_t)0x0006)            /*!< DATLEN[1:0] bits (Data length to be transferred) */
07521 #define  SPI_I2SCFGR_DATLEN_0                ((uint16_t)0x0002)            /*!< Bit 0 */
07522 #define  SPI_I2SCFGR_DATLEN_1                ((uint16_t)0x0004)            /*!< Bit 1 */
07523
07524 #define  SPI_I2SCFGR_CKPOL                   ((uint16_t)0x0008)            /*!< steady state clock polarity */
07525
07526 #define  SPI_I2SCFGR_I2SSTD                  ((uint16_t)0x0030)            /*!< I2SSTD[1:0] bits (I2S standard selection) */
07527 #define  SPI_I2SCFGR_I2SSTD_0                ((uint16_t)0x0010)            /*!< Bit 0 */
07528 #define  SPI_I2SCFGR_I2SSTD_1                ((uint16_t)0x0020)            /*!< Bit 1 */
07529
07530 #define  SPI_I2SCFGR_PCMSYNC                 ((uint16_t)0x0080)            /*!< PCM frame synchronization */
07531
07532 #define  SPI_I2SCFGR_I2SCFG                  ((uint16_t)0x0300)            /*!< I2SCFG[1:0] bits (I2S configuration mode) */
07533 #define  SPI_I2SCFGR_I2SCFG_0                ((uint16_t)0x0100)            /*!< Bit 0 */
07534 #define  SPI_I2SCFGR_I2SCFG_1                ((uint16_t)0x0200)            /*!< Bit 1 */
07535
07536 #define  SPI_I2SCFGR_I2SE                    ((uint16_t)0x0400)            /*!< I2S Enable */
07537 #define  SPI_I2SCFGR_I2SMOD                  ((uint16_t)0x0800)            /*!< I2S mode selection */
07538
07539 /******************  Bit definition for SPI_I2SPR register  *******************/
07540 #define  SPI_I2SPR_I2SDIV                    ((uint16_t)0x00FF)            /*!< I2S Linear prescaler */
07541 #define  SPI_I2SPR_ODD                       ((uint16_t)0x0100)            /*!< Odd factor for the prescaler */
07542 #define  SPI_I2SPR_MCKOE                     ((uint16_t)0x0200)            /*!< Master Clock Output Enable */
07543
07544 /******************************************************************************/
07545 /*                                                                            */
07546 /*                      Inter-integrated Circuit Interface                    */
07547 /*                                                                            */
07548 /******************************************************************************/
07549
07550 /*******************  Bit definition for I2C_CR1 register  ********************/
07551 #define  I2C_CR1_PE                          ((uint16_t)0x0001)            /*!< Peripheral Enable */
07552 #define  I2C_CR1_SMBUS                       ((uint16_t)0x0002)            /*!< SMBus Mode */
07553 #define  I2C_CR1_SMBTYPE                     ((uint16_t)0x0008)            /*!< SMBus Type */
07554 #define  I2C_CR1_ENARP                       ((uint16_t)0x0010)            /*!< ARP Enable */
07555 #define  I2C_CR1_ENPEC                       ((uint16_t)0x0020)            /*!< PEC Enable */
07556 #define  I2C_CR1_ENGC                        ((uint16_t)0x0040)            /*!< General Call Enable */
07557 #define  I2C_CR1_NOSTRETCH                   ((uint16_t)0x0080)            /*!< Clock Stretching Disable (Slave mode) */
07558 #define  I2C_CR1_START                       ((uint16_t)0x0100)            /*!< Start Generation */
07559 #define  I2C_CR1_STOP                        ((uint16_t)0x0200)            /*!< Stop Generation */
07560 #define  I2C_CR1_ACK                         ((uint16_t)0x0400)            /*!< Acknowledge Enable */
07561 #define  I2C_CR1_POS                         ((uint16_t)0x0800)            /*!< Acknowledge/PEC Position (for data reception) */
07562 #define  I2C_CR1_PEC                         ((uint16_t)0x1000)            /*!< Packet Error Checking */
07563 #define  I2C_CR1_ALERT                       ((uint16_t)0x2000)            /*!< SMBus Alert */
07564 #define  I2C_CR1_SWRST                       ((uint16_t)0x8000)            /*!< Software Reset */
07565
07566 /*******************  Bit definition for I2C_CR2 register  ********************/
07567 #define  I2C_CR2_FREQ                        ((uint16_t)0x003F)            /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
07568 #define  I2C_CR2_FREQ_0                      ((uint16_t)0x0001)            /*!< Bit 0 */
07569 #define  I2C_CR2_FREQ_1                      ((uint16_t)0x0002)            /*!< Bit 1 */
07570 #define  I2C_CR2_FREQ_2                      ((uint16_t)0x0004)            /*!< Bit 2 */
07571 #define  I2C_CR2_FREQ_3                      ((uint16_t)0x0008)            /*!< Bit 3 */
07572 #define  I2C_CR2_FREQ_4                      ((uint16_t)0x0010)            /*!< Bit 4 */
07573 #define  I2C_CR2_FREQ_5                      ((uint16_t)0x0020)            /*!< Bit 5 */
07574
07575 #define  I2C_CR2_ITERREN                     ((uint16_t)0x0100)            /*!< Error Interrupt Enable */
07576 #define  I2C_CR2_ITEVTEN                     ((uint16_t)0x0200)            /*!< Event Interrupt Enable */
07577 #define  I2C_CR2_ITBUFEN                     ((uint16_t)0x0400)            /*!< Buffer Interrupt Enable */
07578 #define  I2C_CR2_DMAEN                       ((uint16_t)0x0800)            /*!< DMA Requests Enable */
07579 #define  I2C_CR2_LAST                        ((uint16_t)0x1000)            /*!< DMA Last Transfer */
07580
07581 /*******************  Bit definition for I2C_OAR1 register  *******************/
07582 #define  I2C_OAR1_ADD1_7                     ((uint16_t)0x00FE)            /*!< Interface Address */
07583 #define  I2C_OAR1_ADD8_9                     ((uint16_t)0x0300)            /*!< Interface Address */
07584
07585 #define  I2C_OAR1_ADD0                       ((uint16_t)0x0001)            /*!< Bit 0 */
07586 #define  I2C_OAR1_ADD1                       ((uint16_t)0x0002)            /*!< Bit 1 */
07587 #define  I2C_OAR1_ADD2                       ((uint16_t)0x0004)            /*!< Bit 2 */
07588 #define  I2C_OAR1_ADD3                       ((uint16_t)0x0008)            /*!< Bit 3 */
07589 #define  I2C_OAR1_ADD4                       ((uint16_t)0x0010)            /*!< Bit 4 */
07590 #define  I2C_OAR1_ADD5                       ((uint16_t)0x0020)            /*!< Bit 5 */
07591 #define  I2C_OAR1_ADD6                       ((uint16_t)0x0040)            /*!< Bit 6 */
07592 #define  I2C_OAR1_ADD7                       ((uint16_t)0x0080)            /*!< Bit 7 */
07593 #define  I2C_OAR1_ADD8                       ((uint16_t)0x0100)            /*!< Bit 8 */
07594 #define  I2C_OAR1_ADD9                       ((uint16_t)0x0200)            /*!< Bit 9 */
07595
07596 #define  I2C_OAR1_ADDMODE                    ((uint16_t)0x8000)            /*!< Addressing Mode (Slave mode) */
07597
07598 /*******************  Bit definition for I2C_OAR2 register  *******************/
07599 #define  I2C_OAR2_ENDUAL                     ((uint8_t)0x01)               /*!< Dual addressing mode enable */
07600 #define  I2C_OAR2_ADD2                       ((uint8_t)0xFE)               /*!< Interface address */
07601
07602 /********************  Bit definition for I2C_DR register  ********************/
07603 #define  I2C_DR_DR                           ((uint8_t)0xFF)               /*!< 8-bit Data Register */
07604
07605 /*******************  Bit definition for I2C_SR1 register  ********************/
07606 #define  I2C_SR1_SB                          ((uint16_t)0x0001)            /*!< Start Bit (Master mode) */
07607 #define  I2C_SR1_ADDR                        ((uint16_t)0x0002)            /*!< Address sent (master mode)/matched (slave mode) */
07608 #define  I2C_SR1_BTF                         ((uint16_t)0x0004)            /*!< Byte Transfer Finished */
07609 #define  I2C_SR1_ADD10                       ((uint16_t)0x0008)            /*!< 10-bit header sent (Master mode) */
07610 #define  I2C_SR1_STOPF                       ((uint16_t)0x0010)            /*!< Stop detection (Slave mode) */
07611 #define  I2C_SR1_RXNE                        ((uint16_t)0x0040)            /*!< Data Register not Empty (receivers) */
07612 #define  I2C_SR1_TXE                         ((uint16_t)0x0080)            /*!< Data Register Empty (transmitters) */
07613 #define  I2C_SR1_BERR                        ((uint16_t)0x0100)            /*!< Bus Error */
07614 #define  I2C_SR1_ARLO                        ((uint16_t)0x0200)            /*!< Arbitration Lost (master mode) */
07615 #define  I2C_SR1_AF                          ((uint16_t)0x0400)            /*!< Acknowledge Failure */
07616 #define  I2C_SR1_OVR                         ((uint16_t)0x0800)            /*!< Overrun/Underrun */
07617 #define  I2C_SR1_PECERR                      ((uint16_t)0x1000)            /*!< PEC Error in reception */
07618 #define  I2C_SR1_TIMEOUT                     ((uint16_t)0x4000)            /*!< Timeout or Tlow Error */
07619 #define  I2C_SR1_SMBALERT                    ((uint16_t)0x8000)            /*!< SMBus Alert */
07620
07621 /*******************  Bit definition for I2C_SR2 register  ********************/
07622 #define  I2C_SR2_MSL                         ((uint16_t)0x0001)            /*!< Master/Slave */
07623 #define  I2C_SR2_BUSY                        ((uint16_t)0x0002)            /*!< Bus Busy */
07624 #define  I2C_SR2_TRA                         ((uint16_t)0x0004)            /*!< Transmitter/Receiver */
07625 #define  I2C_SR2_GENCALL                     ((uint16_t)0x0010)            /*!< General Call Address (Slave mode) */
07626 #define  I2C_SR2_SMBDEFAULT                  ((uint16_t)0x0020)            /*!< SMBus Device Default Address (Slave mode) */
07627 #define  I2C_SR2_SMBHOST                     ((uint16_t)0x0040)            /*!< SMBus Host Header (Slave mode) */
07628 #define  I2C_SR2_DUALF                       ((uint16_t)0x0080)            /*!< Dual Flag (Slave mode) */
07629 #define  I2C_SR2_PEC                         ((uint16_t)0xFF00)            /*!< Packet Error Checking Register */
07630
07631 /*******************  Bit definition for I2C_CCR register  ********************/
07632 #define  I2C_CCR_CCR                         ((uint16_t)0x0FFF)            /*!< Clock Control Register in Fast/Standard mode (Master mode) */
07633 #define  I2C_CCR_DUTY                        ((uint16_t)0x4000)            /*!< Fast Mode Duty Cycle */
07634 #define  I2C_CCR_FS                          ((uint16_t)0x8000)            /*!< I2C Master Mode Selection */
07635
07636 /******************  Bit definition for I2C_TRISE register  *******************/
07637 #define  I2C_TRISE_TRISE                     ((uint8_t)0x3F)               /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
07638
07639 /******************************************************************************/
07640 /*                                                                            */
07641 /*         Universal Synchronous Asynchronous Receiver Transmitter            */
07642 /*                                                                            */
07643 /******************************************************************************/
07644
07645 /*******************  Bit definition for USART_SR register  *******************/
07646 #define  USART_SR_PE                         ((uint16_t)0x0001)            /*!< Parity Error */
07647 #define  USART_SR_FE                         ((uint16_t)0x0002)            /*!< Framing Error */
07648 #define  USART_SR_NE                         ((uint16_t)0x0004)            /*!< Noise Error Flag */
07649 #define  USART_SR_ORE                        ((uint16_t)0x0008)            /*!< OverRun Error */
07650 #define  USART_SR_IDLE                       ((uint16_t)0x0010)            /*!< IDLE line detected */
07651 #define  USART_SR_RXNE                       ((uint16_t)0x0020)            /*!< Read Data Register Not Empty */
07652 #define  USART_SR_TC                         ((uint16_t)0x0040)            /*!< Transmission Complete */
07653 #define  USART_SR_TXE                        ((uint16_t)0x0080)            /*!< Transmit Data Register Empty */
07654 #define  USART_SR_LBD                        ((uint16_t)0x0100)            /*!< LIN Break Detection Flag */
07655 #define  USART_SR_CTS                        ((uint16_t)0x0200)            /*!< CTS Flag */
07656
07657 /*******************  Bit definition for USART_DR register  *******************/
07658 #define  USART_DR_DR                         ((uint16_t)0x01FF)            /*!< Data value */
07659
07660 /******************  Bit definition for USART_BRR register  *******************/
07661 #define  USART_BRR_DIV_Fraction              ((uint16_t)0x000F)            /*!< Fraction of USARTDIV */
07662 #define  USART_BRR_DIV_Mantissa              ((uint16_t)0xFFF0)            /*!< Mantissa of USARTDIV */
07663
07664 /******************  Bit definition for USART_CR1 register  *******************/
07665 #define  USART_CR1_SBK                       ((uint16_t)0x0001)            /*!< Send Break */
07666 #define  USART_CR1_RWU                       ((uint16_t)0x0002)            /*!< Receiver wakeup */
07667 #define  USART_CR1_RE                        ((uint16_t)0x0004)            /*!< Receiver Enable */
07668 #define  USART_CR1_TE                        ((uint16_t)0x0008)            /*!< Transmitter Enable */
07669 #define  USART_CR1_IDLEIE                    ((uint16_t)0x0010)            /*!< IDLE Interrupt Enable */
07670 #define  USART_CR1_RXNEIE                    ((uint16_t)0x0020)            /*!< RXNE Interrupt Enable */
07671 #define  USART_CR1_TCIE                      ((uint16_t)0x0040)            /*!< Transmission Complete Interrupt Enable */
07672 #define  USART_CR1_TXEIE                     ((uint16_t)0x0080)            /*!< PE Interrupt Enable */
07673 #define  USART_CR1_PEIE                      ((uint16_t)0x0100)            /*!< PE Interrupt Enable */
07674 #define  USART_CR1_PS                        ((uint16_t)0x0200)            /*!< Parity Selection */
07675 #define  USART_CR1_PCE                       ((uint16_t)0x0400)            /*!< Parity Control Enable */
07676 #define  USART_CR1_WAKE                      ((uint16_t)0x0800)            /*!< Wakeup method */
07677 #define  USART_CR1_M                         ((uint16_t)0x1000)            /*!< Word length */
07678 #define  USART_CR1_UE                        ((uint16_t)0x2000)            /*!< USART Enable */
07679 #define  USART_CR1_OVER8                     ((uint16_t)0x8000)            /*!< USART Oversmapling 8-bits */
07680
07681 /******************  Bit definition for USART_CR2 register  *******************/
07682 #define  USART_CR2_ADD                       ((uint16_t)0x000F)            /*!< Address of the USART node */
07683 #define  USART_CR2_LBDL                      ((uint16_t)0x0020)            /*!< LIN Break Detection Length */
07684 #define  USART_CR2_LBDIE                     ((uint16_t)0x0040)            /*!< LIN Break Detection Interrupt Enable */
07685 #define  USART_CR2_LBCL                      ((uint16_t)0x0100)            /*!< Last Bit Clock pulse */
07686 #define  USART_CR2_CPHA                      ((uint16_t)0x0200)            /*!< Clock Phase */
07687 #define  USART_CR2_CPOL                      ((uint16_t)0x0400)            /*!< Clock Polarity */
07688 #define  USART_CR2_CLKEN                     ((uint16_t)0x0800)            /*!< Clock Enable */
07689
07690 #define  USART_CR2_STOP                      ((uint16_t)0x3000)            /*!< STOP[1:0] bits (STOP bits) */
07691 #define  USART_CR2_STOP_0                    ((uint16_t)0x1000)            /*!< Bit 0 */
07692 #define  USART_CR2_STOP_1                    ((uint16_t)0x2000)            /*!< Bit 1 */
07693
07694 #define  USART_CR2_LINEN                     ((uint16_t)0x4000)            /*!< LIN mode enable */
07695
07696 /******************  Bit definition for USART_CR3 register  *******************/
07697 #define  USART_CR3_EIE                       ((uint16_t)0x0001)            /*!< Error Interrupt Enable */
07698 #define  USART_CR3_IREN                      ((uint16_t)0x0002)            /*!< IrDA mode Enable */
07699 #define  USART_CR3_IRLP                      ((uint16_t)0x0004)            /*!< IrDA Low-Power */
07700 #define  USART_CR3_HDSEL                     ((uint16_t)0x0008)            /*!< Half-Duplex Selection */
07701 #define  USART_CR3_NACK                      ((uint16_t)0x0010)            /*!< Smartcard NACK enable */
07702 #define  USART_CR3_SCEN                      ((uint16_t)0x0020)            /*!< Smartcard mode enable */
07703 #define  USART_CR3_DMAR                      ((uint16_t)0x0040)            /*!< DMA Enable Receiver */
07704 #define  USART_CR3_DMAT                      ((uint16_t)0x0080)            /*!< DMA Enable Transmitter */
07705 #define  USART_CR3_RTSE                      ((uint16_t)0x0100)            /*!< RTS Enable */
07706 #define  USART_CR3_CTSE                      ((uint16_t)0x0200)            /*!< CTS Enable */
07707 #define  USART_CR3_CTSIE                     ((uint16_t)0x0400)            /*!< CTS Interrupt Enable */
07708 #define  USART_CR3_ONEBIT                    ((uint16_t)0x0800)            /*!< One Bit method */
07709
07710 /******************  Bit definition for USART_GTPR register  ******************/
07711 #define  USART_GTPR_PSC                      ((uint16_t)0x00FF)            /*!< PSC[7:0] bits (Prescaler value) */
07712 #define  USART_GTPR_PSC_0                    ((uint16_t)0x0001)            /*!< Bit 0 */
07713 #define  USART_GTPR_PSC_1                    ((uint16_t)0x0002)            /*!< Bit 1 */
07714 #define  USART_GTPR_PSC_2                    ((uint16_t)0x0004)            /*!< Bit 2 */
07715 #define  USART_GTPR_PSC_3                    ((uint16_t)0x0008)            /*!< Bit 3 */
07716 #define  USART_GTPR_PSC_4                    ((uint16_t)0x0010)            /*!< Bit 4 */
07717 #define  USART_GTPR_PSC_5                    ((uint16_t)0x0020)            /*!< Bit 5 */
07718 #define  USART_GTPR_PSC_6                    ((uint16_t)0x0040)            /*!< Bit 6 */
07719 #define  USART_GTPR_PSC_7                    ((uint16_t)0x0080)            /*!< Bit 7 */
07720
07721 #define  USART_GTPR_GT                       ((uint16_t)0xFF00)            /*!< Guard time value */
07722
07723 /******************************************************************************/
07724 /*                                                                            */
07725 /*                                 Debug MCU                                  */
07726 /*                                                                            */
07727 /******************************************************************************/
07728
07729 /****************  Bit definition for DBGMCU_IDCODE register  *****************/
07730 #define  DBGMCU_IDCODE_DEV_ID                ((uint32_t)0x00000FFF)        /*!< Device Identifier */
07731
07732 #define  DBGMCU_IDCODE_REV_ID                ((uint32_t)0xFFFF0000)        /*!< REV_ID[15:0] bits (Revision Identifier) */
07733 #define  DBGMCU_IDCODE_REV_ID_0              ((uint32_t)0x00010000)        /*!< Bit 0 */
07734 #define  DBGMCU_IDCODE_REV_ID_1              ((uint32_t)0x00020000)        /*!< Bit 1 */
07735 #define  DBGMCU_IDCODE_REV_ID_2              ((uint32_t)0x00040000)        /*!< Bit 2 */
07736 #define  DBGMCU_IDCODE_REV_ID_3              ((uint32_t)0x00080000)        /*!< Bit 3 */
07737 #define  DBGMCU_IDCODE_REV_ID_4              ((uint32_t)0x00100000)        /*!< Bit 4 */
07738 #define  DBGMCU_IDCODE_REV_ID_5              ((uint32_t)0x00200000)        /*!< Bit 5 */
07739 #define  DBGMCU_IDCODE_REV_ID_6              ((uint32_t)0x00400000)        /*!< Bit 6 */
07740 #define  DBGMCU_IDCODE_REV_ID_7              ((uint32_t)0x00800000)        /*!< Bit 7 */
07741 #define  DBGMCU_IDCODE_REV_ID_8              ((uint32_t)0x01000000)        /*!< Bit 8 */
07742 #define  DBGMCU_IDCODE_REV_ID_9              ((uint32_t)0x02000000)        /*!< Bit 9 */
07743 #define  DBGMCU_IDCODE_REV_ID_10             ((uint32_t)0x04000000)        /*!< Bit 10 */
07744 #define  DBGMCU_IDCODE_REV_ID_11             ((uint32_t)0x08000000)        /*!< Bit 11 */
07745 #define  DBGMCU_IDCODE_REV_ID_12             ((uint32_t)0x10000000)        /*!< Bit 12 */
07746 #define  DBGMCU_IDCODE_REV_ID_13             ((uint32_t)0x20000000)        /*!< Bit 13 */
07747 #define  DBGMCU_IDCODE_REV_ID_14             ((uint32_t)0x40000000)        /*!< Bit 14 */
07748 #define  DBGMCU_IDCODE_REV_ID_15             ((uint32_t)0x80000000)        /*!< Bit 15 */
07749
07750 /******************  Bit definition for DBGMCU_CR register  *******************/
07751 #define  DBGMCU_CR_DBG_SLEEP                 ((uint32_t)0x00000001)        /*!< Debug Sleep Mode */
07752 #define  DBGMCU_CR_DBG_STOP                  ((uint32_t)0x00000002)        /*!< Debug Stop Mode */
07753 #define  DBGMCU_CR_DBG_STANDBY               ((uint32_t)0x00000004)        /*!< Debug Standby mode */
07754 #define  DBGMCU_CR_TRACE_IOEN                ((uint32_t)0x00000020)        /*!< Trace Pin Assignment Control */
07755
07756 #define  DBGMCU_CR_TRACE_MODE                ((uint32_t)0x000000C0)        /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
07757 #define  DBGMCU_CR_TRACE_MODE_0              ((uint32_t)0x00000040)        /*!< Bit 0 */
07758 #define  DBGMCU_CR_TRACE_MODE_1              ((uint32_t)0x00000080)        /*!< Bit 1 */
07759
07760 #define  DBGMCU_CR_DBG_IWDG_STOP             ((uint32_t)0x00000100)        /*!< Debug Independent Watchdog stopped when Core is halted */
07761 #define  DBGMCU_CR_DBG_WWDG_STOP             ((uint32_t)0x00000200)        /*!< Debug Window Watchdog stopped when Core is halted */
07762 #define  DBGMCU_CR_DBG_TIM1_STOP             ((uint32_t)0x00000400)        /*!< TIM1 counter stopped when core is halted */
07763 #define  DBGMCU_CR_DBG_TIM2_STOP             ((uint32_t)0x00000800)        /*!< TIM2 counter stopped when core is halted */
07764 #define  DBGMCU_CR_DBG_TIM3_STOP             ((uint32_t)0x00001000)        /*!< TIM3 counter stopped when core is halted */
07765 #define  DBGMCU_CR_DBG_TIM4_STOP             ((uint32_t)0x00002000)        /*!< TIM4 counter stopped when core is halted */
07766 #define  DBGMCU_CR_DBG_CAN1_STOP             ((uint32_t)0x00004000)        /*!< Debug CAN1 stopped when Core is halted */
07767 #define  DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT    ((uint32_t)0x00008000)        /*!< SMBUS timeout mode stopped when Core is halted */
07768 #define  DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT    ((uint32_t)0x00010000)        /*!< SMBUS timeout mode stopped when Core is halted */
07769 #define  DBGMCU_CR_DBG_TIM8_STOP             ((uint32_t)0x00020000)        /*!< TIM8 counter stopped when core is halted */
07770 #define  DBGMCU_CR_DBG_TIM5_STOP             ((uint32_t)0x00040000)        /*!< TIM5 counter stopped when core is halted */
07771 #define  DBGMCU_CR_DBG_TIM6_STOP             ((uint32_t)0x00080000)        /*!< TIM6 counter stopped when core is halted */
07772 #define  DBGMCU_CR_DBG_TIM7_STOP             ((uint32_t)0x00100000)        /*!< TIM7 counter stopped when core is halted */
07773 #define  DBGMCU_CR_DBG_CAN2_STOP             ((uint32_t)0x00200000)        /*!< Debug CAN2 stopped when Core is halted */
07774 #define  DBGMCU_CR_DBG_TIM15_STOP            ((uint32_t)0x00400000)        /*!< Debug TIM15 stopped when Core is halted */
07775 #define  DBGMCU_CR_DBG_TIM16_STOP            ((uint32_t)0x00800000)        /*!< Debug TIM16 stopped when Core is halted */
07776 #define  DBGMCU_CR_DBG_TIM17_STOP            ((uint32_t)0x01000000)        /*!< Debug TIM17 stopped when Core is halted */
07777 #define  DBGMCU_CR_DBG_TIM12_STOP            ((uint32_t)0x02000000)        /*!< Debug TIM12 stopped when Core is halted */
07778 #define  DBGMCU_CR_DBG_TIM13_STOP            ((uint32_t)0x04000000)        /*!< Debug TIM13 stopped when Core is halted */
07779 #define  DBGMCU_CR_DBG_TIM14_STOP            ((uint32_t)0x08000000)        /*!< Debug TIM14 stopped when Core is halted */
07780 #define  DBGMCU_CR_DBG_TIM9_STOP             ((uint32_t)0x10000000)        /*!< Debug TIM9 stopped when Core is halted */
07781 #define  DBGMCU_CR_DBG_TIM10_STOP            ((uint32_t)0x20000000)        /*!< Debug TIM10 stopped when Core is halted */
07782 #define  DBGMCU_CR_DBG_TIM11_STOP            ((uint32_t)0x40000000)        /*!< Debug TIM11 stopped when Core is halted */
07783
07784 /******************************************************************************/
07785 /*                                                                            */
07786 /*                      FLASH and Option Bytes Registers                      */
07787 /*                                                                            */
07788 /******************************************************************************/
07789
07790 /*******************  Bit definition for FLASH_ACR register  ******************/
07791 #define  FLASH_ACR_LATENCY                   ((uint8_t)0x03)               /*!< LATENCY[2:0] bits (Latency) */
07792 #define  FLASH_ACR_LATENCY_0                 ((uint8_t)0x00)               /*!< Bit 0 */
07793 #define  FLASH_ACR_LATENCY_1                 ((uint8_t)0x01)               /*!< Bit 0 */
07794 #define  FLASH_ACR_LATENCY_2                 ((uint8_t)0x02)               /*!< Bit 1 */
07795
07796 #define  FLASH_ACR_HLFCYA                    ((uint8_t)0x08)               /*!< Flash Half Cycle Access Enable */
07797 #define  FLASH_ACR_PRFTBE                    ((uint8_t)0x10)               /*!< Prefetch Buffer Enable */
07798 #define  FLASH_ACR_PRFTBS                    ((uint8_t)0x20)               /*!< Prefetch Buffer Status */
07799
07800 /******************  Bit definition for FLASH_KEYR register  ******************/
07801 #define  FLASH_KEYR_FKEYR                    ((uint32_t)0xFFFFFFFF)        /*!< FPEC Key */
07802
07803 /*****************  Bit definition for FLASH_OPTKEYR register  ****************/
07804 #define  FLASH_OPTKEYR_OPTKEYR               ((uint32_t)0xFFFFFFFF)        /*!< Option Byte Key */
07805
07806 /******************  Bit definition for FLASH_SR register  *******************/
07807 #define  FLASH_SR_BSY                        ((uint8_t)0x01)               /*!< Busy */
07808 #define  FLASH_SR_PGERR                      ((uint8_t)0x04)               /*!< Programming Error */
07809 #define  FLASH_SR_WRPRTERR                   ((uint8_t)0x10)               /*!< Write Protection Error */
07810 #define  FLASH_SR_EOP                        ((uint8_t)0x20)               /*!< End of operation */
07811
07812 /*******************  Bit definition for FLASH_CR register  *******************/
07813 #define  FLASH_CR_PG                         ((uint16_t)0x0001)            /*!< Programming */
07814 #define  FLASH_CR_PER                        ((uint16_t)0x0002)            /*!< Page Erase */
07815 #define  FLASH_CR_MER                        ((uint16_t)0x0004)            /*!< Mass Erase */
07816 #define  FLASH_CR_OPTPG                      ((uint16_t)0x0010)            /*!< Option Byte Programming */
07817 #define  FLASH_CR_OPTER                      ((uint16_t)0x0020)            /*!< Option Byte Erase */
07818 #define  FLASH_CR_STRT                       ((uint16_t)0x0040)            /*!< Start */
07819 #define  FLASH_CR_LOCK                       ((uint16_t)0x0080)            /*!< Lock */
07820 #define  FLASH_CR_OPTWRE                     ((uint16_t)0x0200)            /*!< Option Bytes Write Enable */
07821 #define  FLASH_CR_ERRIE                      ((uint16_t)0x0400)            /*!< Error Interrupt Enable */
07822 #define  FLASH_CR_EOPIE                      ((uint16_t)0x1000)            /*!< End of operation interrupt enable */
07823
07824 /*******************  Bit definition for FLASH_AR register  *******************/
07825 #define  FLASH_AR_FAR                        ((uint32_t)0xFFFFFFFF)        /*!< Flash Address */
07826
07827 /******************  Bit definition for FLASH_OBR register  *******************/
07828 #define  FLASH_OBR_OPTERR                    ((uint16_t)0x0001)            /*!< Option Byte Error */
07829 #define  FLASH_OBR_RDPRT                     ((uint16_t)0x0002)            /*!< Read protection */
07830
07831 #define  FLASH_OBR_USER                      ((uint16_t)0x03FC)            /*!< User Option Bytes */
07832 #define  FLASH_OBR_WDG_SW                    ((uint16_t)0x0004)            /*!< WDG_SW */
07833 #define  FLASH_OBR_nRST_STOP                 ((uint16_t)0x0008)            /*!< nRST_STOP */
07834 #define  FLASH_OBR_nRST_STDBY                ((uint16_t)0x0010)            /*!< nRST_STDBY */
07835 #define  FLASH_OBR_BFB2                      ((uint16_t)0x0020)            /*!< BFB2 */
07836
07837 /******************  Bit definition for FLASH_WRPR register  ******************/
07838 #define  FLASH_WRPR_WRP                        ((uint32_t)0xFFFFFFFF)        /*!< Write Protect */
07839
07840 /*----------------------------------------------------------------------------*/
07841
07842 /******************  Bit definition for FLASH_RDP register  *******************/
07843 #define  FLASH_RDP_RDP                       ((uint32_t)0x000000FF)        /*!< Read protection option byte */
07844 #define  FLASH_RDP_nRDP                      ((uint32_t)0x0000FF00)        /*!< Read protection complemented option byte */
07845
07846 /******************  Bit definition for FLASH_USER register  ******************/
07847 #define  FLASH_USER_USER                     ((uint32_t)0x00FF0000)        /*!< User option byte */
07848 #define  FLASH_USER_nUSER                    ((uint32_t)0xFF000000)        /*!< User complemented option byte */
07849
07850 /******************  Bit definition for FLASH_Data0 register  *****************/
07851 #define  FLASH_Data0_Data0                   ((uint32_t)0x000000FF)        /*!< User data storage option byte */
07852 #define  FLASH_Data0_nData0                  ((uint32_t)0x0000FF00)        /*!< User data storage complemented option byte */
07853
07854 /******************  Bit definition for FLASH_Data1 register  *****************/
07855 #define  FLASH_Data1_Data1                   ((uint32_t)0x00FF0000)        /*!< User data storage option byte */
07856 #define  FLASH_Data1_nData1                  ((uint32_t)0xFF000000)        /*!< User data storage complemented option byte */
07857
07858 /******************  Bit definition for FLASH_WRP0 register  ******************/
07859 #define  FLASH_WRP0_WRP0                     ((uint32_t)0x000000FF)        /*!< Flash memory write protection option bytes */
07860 #define  FLASH_WRP0_nWRP0                    ((uint32_t)0x0000FF00)        /*!< Flash memory write protection complemented option bytes */
07861
07862 /******************  Bit definition for FLASH_WRP1 register  ******************/
07863 #define  FLASH_WRP1_WRP1                     ((uint32_t)0x00FF0000)        /*!< Flash memory write protection option bytes */
07864 #define  FLASH_WRP1_nWRP1                    ((uint32_t)0xFF000000)        /*!< Flash memory write protection complemented option bytes */
07865
07866 /******************  Bit definition for FLASH_WRP2 register  ******************/
07867 #define  FLASH_WRP2_WRP2                     ((uint32_t)0x000000FF)        /*!< Flash memory write protection option bytes */
07868 #define  FLASH_WRP2_nWRP2                    ((uint32_t)0x0000FF00)        /*!< Flash memory write protection complemented option bytes */
07869
07870 /******************  Bit definition for FLASH_WRP3 register  ******************/
07871 #define  FLASH_WRP3_WRP3                     ((uint32_t)0x00FF0000)        /*!< Flash memory write protection option bytes */
07872 #define  FLASH_WRP3_nWRP3                    ((uint32_t)0xFF000000)        /*!< Flash memory write protection complemented option bytes */
07873
07874 #ifdef STM32F10X_CL
07875 /******************************************************************************/
07876 /*                Ethernet MAC Registers bits definitions                     */
07877 /******************************************************************************/
07878 /* Bit definition for Ethernet MAC Control Register register */
07879 #define ETH_MACCR_WD      ((uint32_t)0x00800000)  /* Watchdog disable */
07880 #define ETH_MACCR_JD      ((uint32_t)0x00400000)  /* Jabber disable */
07881 #define ETH_MACCR_IFG     ((uint32_t)0x000E0000)  /* Inter-frame gap */
07882   #define ETH_MACCR_IFG_96Bit     ((uint32_t)0x00000000)  /* Minimum IFG between frames during transmission is 96Bit */
07883   #define ETH_MACCR_IFG_88Bit     ((uint32_t)0x00020000)  /* Minimum IFG between frames during transmission is 88Bit */
07884   #define ETH_MACCR_IFG_80Bit     ((uint32_t)0x00040000)  /* Minimum IFG between frames during transmission is 80Bit */
07885   #define ETH_MACCR_IFG_72Bit     ((uint32_t)0x00060000)  /* Minimum IFG between frames during transmission is 72Bit */
07886   #define ETH_MACCR_IFG_64Bit     ((uint32_t)0x00080000)  /* Minimum IFG between frames during transmission is 64Bit */
07887   #define ETH_MACCR_IFG_56Bit     ((uint32_t)0x000A0000)  /* Minimum IFG between frames during transmission is 56Bit */
07888   #define ETH_MACCR_IFG_48Bit     ((uint32_t)0x000C0000)  /* Minimum IFG between frames during transmission is 48Bit */
07889   #define ETH_MACCR_IFG_40Bit     ((uint32_t)0x000E0000)  /* Minimum IFG between frames during transmission is 40Bit */
07890 #define ETH_MACCR_CSD     ((uint32_t)0x00010000)  /* Carrier sense disable (during transmission) */
07891 #define ETH_MACCR_FES     ((uint32_t)0x00004000)  /* Fast ethernet speed */
07892 #define ETH_MACCR_ROD     ((uint32_t)0x00002000)  /* Receive own disable */
07893 #define ETH_MACCR_LM      ((uint32_t)0x00001000)  /* loopback mode */
07894 #define ETH_MACCR_DM      ((uint32_t)0x00000800)  /* Duplex mode */
07895 #define ETH_MACCR_IPCO    ((uint32_t)0x00000400)  /* IP Checksum offload */
07896 #define ETH_MACCR_RD      ((uint32_t)0x00000200)  /* Retry disable */
07897 #define ETH_MACCR_APCS    ((uint32_t)0x00000080)  /* Automatic Pad/CRC stripping */
07898 #define ETH_MACCR_BL      ((uint32_t)0x00000060)  /* Back-off limit: random integer number (r) of slot time delays before rescheduling
07899                                                        a transmission attempt during retries after a collision: 0 =< r <2^k */
07900   #define ETH_MACCR_BL_10    ((uint32_t)0x00000000)  /* k = min (n, 10) */
07901   #define ETH_MACCR_BL_8     ((uint32_t)0x00000020)  /* k = min (n, 8) */
07902   #define ETH_MACCR_BL_4     ((uint32_t)0x00000040)  /* k = min (n, 4) */
07903   #define ETH_MACCR_BL_1     ((uint32_t)0x00000060)  /* k = min (n, 1) */
07904 #define ETH_MACCR_DC      ((uint32_t)0x00000010)  /* Defferal check */
07905 #define ETH_MACCR_TE      ((uint32_t)0x00000008)  /* Transmitter enable */
07906 #define ETH_MACCR_RE      ((uint32_t)0x00000004)  /* Receiver enable */
07907
07908 /* Bit definition for Ethernet MAC Frame Filter Register */
07909 #define ETH_MACFFR_RA     ((uint32_t)0x80000000)  /* Receive all */
07910 #define ETH_MACFFR_HPF    ((uint32_t)0x00000400)  /* Hash or perfect filter */
07911 #define ETH_MACFFR_SAF    ((uint32_t)0x00000200)  /* Source address filter enable */
07912 #define ETH_MACFFR_SAIF   ((uint32_t)0x00000100)  /* SA inverse filtering */
07913 #define ETH_MACFFR_PCF    ((uint32_t)0x000000C0)  /* Pass control frames: 3 cases */
07914   #define ETH_MACFFR_PCF_BlockAll                ((uint32_t)0x00000040)  /* MAC filters all control frames from reaching the application */
07915   #define ETH_MACFFR_PCF_ForwardAll              ((uint32_t)0x00000080)  /* MAC forwards all control frames to application even if they fail the Address Filter */
07916   #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0)  /* MAC forwards control frames that pass the Address Filter. */
07917 #define ETH_MACFFR_BFD    ((uint32_t)0x00000020)  /* Broadcast frame disable */
07918 #define ETH_MACFFR_PAM    ((uint32_t)0x00000010)  /* Pass all mutlicast */
07919 #define ETH_MACFFR_DAIF   ((uint32_t)0x00000008)  /* DA Inverse filtering */
07920 #define ETH_MACFFR_HM     ((uint32_t)0x00000004)  /* Hash multicast */
07921 #define ETH_MACFFR_HU     ((uint32_t)0x00000002)  /* Hash unicast */
07922 #define ETH_MACFFR_PM     ((uint32_t)0x00000001)  /* Promiscuous mode */
07923
07924 /* Bit definition for Ethernet MAC Hash Table High Register */
07925 #define ETH_MACHTHR_HTH   ((uint32_t)0xFFFFFFFF)  /* Hash table high */
07926
07927 /* Bit definition for Ethernet MAC Hash Table Low Register */
07928 #define ETH_MACHTLR_HTL   ((uint32_t)0xFFFFFFFF)  /* Hash table low */
07929
07930 /* Bit definition for Ethernet MAC MII Address Register */
07931 #define ETH_MACMIIAR_PA   ((uint32_t)0x0000F800)  /* Physical layer address */
07932 #define ETH_MACMIIAR_MR   ((uint32_t)0x000007C0)  /* MII register in the selected PHY */
07933 #define ETH_MACMIIAR_CR   ((uint32_t)0x0000001C)  /* CR clock range: 6 cases */
07934   #define ETH_MACMIIAR_CR_Div42   ((uint32_t)0x00000000)  /* HCLK:60-72 MHz; MDC clock= HCLK/42 */
07935   #define ETH_MACMIIAR_CR_Div16   ((uint32_t)0x00000008)  /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
07936   #define ETH_MACMIIAR_CR_Div26   ((uint32_t)0x0000000C)  /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
07937 #define ETH_MACMIIAR_MW   ((uint32_t)0x00000002)  /* MII write */
07938 #define ETH_MACMIIAR_MB   ((uint32_t)0x00000001)  /* MII busy */
07939
07940 /* Bit definition for Ethernet MAC MII Data Register */
07941 #define ETH_MACMIIDR_MD   ((uint32_t)0x0000FFFF)  /* MII data: read/write data from/to PHY */
07942
07943 /* Bit definition for Ethernet MAC Flow Control Register */
07944 #define ETH_MACFCR_PT     ((uint32_t)0xFFFF0000)  /* Pause time */
07945 #define ETH_MACFCR_ZQPD   ((uint32_t)0x00000080)  /* Zero-quanta pause disable */
07946 #define ETH_MACFCR_PLT    ((uint32_t)0x00000030)  /* Pause low threshold: 4 cases */
07947   #define ETH_MACFCR_PLT_Minus4   ((uint32_t)0x00000000)  /* Pause time minus 4 slot times */
07948   #define ETH_MACFCR_PLT_Minus28  ((uint32_t)0x00000010)  /* Pause time minus 28 slot times */
07949   #define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020)  /* Pause time minus 144 slot times */
07950   #define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030)  /* Pause time minus 256 slot times */
07951 #define ETH_MACFCR_UPFD   ((uint32_t)0x00000008)  /* Unicast pause frame detect */
07952 #define ETH_MACFCR_RFCE   ((uint32_t)0x00000004)  /* Receive flow control enable */
07953 #define ETH_MACFCR_TFCE   ((uint32_t)0x00000002)  /* Transmit flow control enable */
07954 #define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001)  /* Flow control busy/backpressure activate */
07955
07956 /* Bit definition for Ethernet MAC VLAN Tag Register */
07957 #define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000)  /* 12-bit VLAN tag comparison */
07958 #define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF)  /* VLAN tag identifier (for receive frames) */
07959
07960 /* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
07961 #define ETH_MACRWUFFR_D   ((uint32_t)0xFFFFFFFF)  /* Wake-up frame filter register data */
07962 /* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
07963    Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
07964 /* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
07965    Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
07966    Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
07967    Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
07968    Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
07969                               RSVD - Filter1 Command - RSVD - Filter0 Command
07970    Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
07971    Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
07972    Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
07973
07974 /* Bit definition for Ethernet MAC PMT Control and Status Register */
07975 #define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000)  /* Wake-Up Frame Filter Register Pointer Reset */
07976 #define ETH_MACPMTCSR_GU     ((uint32_t)0x00000200)  /* Global Unicast */
07977 #define ETH_MACPMTCSR_WFR    ((uint32_t)0x00000040)  /* Wake-Up Frame Received */
07978 #define ETH_MACPMTCSR_MPR    ((uint32_t)0x00000020)  /* Magic Packet Received */
07979 #define ETH_MACPMTCSR_WFE    ((uint32_t)0x00000004)  /* Wake-Up Frame Enable */
07980 #define ETH_MACPMTCSR_MPE    ((uint32_t)0x00000002)  /* Magic Packet Enable */
07981 #define ETH_MACPMTCSR_PD     ((uint32_t)0x00000001)  /* Power Down */
07982
07983 /* Bit definition for Ethernet MAC Status Register */
07984 #define ETH_MACSR_TSTS      ((uint32_t)0x00000200)  /* Time stamp trigger status */
07985 #define ETH_MACSR_MMCTS     ((uint32_t)0x00000040)  /* MMC transmit status */
07986 #define ETH_MACSR_MMMCRS    ((uint32_t)0x00000020)  /* MMC receive status */
07987 #define ETH_MACSR_MMCS      ((uint32_t)0x00000010)  /* MMC status */
07988 #define ETH_MACSR_PMTS      ((uint32_t)0x00000008)  /* PMT status */
07989
07990 /* Bit definition for Ethernet MAC Interrupt Mask Register */
07991 #define ETH_MACIMR_TSTIM     ((uint32_t)0x00000200)  /* Time stamp trigger interrupt mask */
07992 #define ETH_MACIMR_PMTIM     ((uint32_t)0x00000008)  /* PMT interrupt mask */
07993
07994 /* Bit definition for Ethernet MAC Address0 High Register */
07995 #define ETH_MACA0HR_MACA0H   ((uint32_t)0x0000FFFF)  /* MAC address0 high */
07996
07997 /* Bit definition for Ethernet MAC Address0 Low Register */
07998 #define ETH_MACA0LR_MACA0L   ((uint32_t)0xFFFFFFFF)  /* MAC address0 low */
07999
08000 /* Bit definition for Ethernet MAC Address1 High Register */
08001 #define ETH_MACA1HR_AE       ((uint32_t)0x80000000)  /* Address enable */
08002 #define ETH_MACA1HR_SA       ((uint32_t)0x40000000)  /* Source address */
08003 #define ETH_MACA1HR_MBC      ((uint32_t)0x3F000000)  /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
08004   #define ETH_MACA1HR_MBC_HBits15_8    ((uint32_t)0x20000000)  /* Mask MAC Address high reg bits [15:8] */
08005   #define ETH_MACA1HR_MBC_HBits7_0     ((uint32_t)0x10000000)  /* Mask MAC Address high reg bits [7:0] */
08006   #define ETH_MACA1HR_MBC_LBits31_24   ((uint32_t)0x08000000)  /* Mask MAC Address low reg bits [31:24] */
08007   #define ETH_MACA1HR_MBC_LBits23_16   ((uint32_t)0x04000000)  /* Mask MAC Address low reg bits [23:16] */
08008   #define ETH_MACA1HR_MBC_LBits15_8    ((uint32_t)0x02000000)  /* Mask MAC Address low reg bits [15:8] */
08009   #define ETH_MACA1HR_MBC_LBits7_0     ((uint32_t)0x01000000)  /* Mask MAC Address low reg bits [7:0] */
08010 #define ETH_MACA1HR_MACA1H   ((uint32_t)0x0000FFFF)  /* MAC address1 high */
08011
08012 /* Bit definition for Ethernet MAC Address1 Low Register */
08013 #define ETH_MACA1LR_MACA1L   ((uint32_t)0xFFFFFFFF)  /* MAC address1 low */
08014
08015 /* Bit definition for Ethernet MAC Address2 High Register */
08016 #define ETH_MACA2HR_AE       ((uint32_t)0x80000000)  /* Address enable */
08017 #define ETH_MACA2HR_SA       ((uint32_t)0x40000000)  /* Source address */
08018 #define ETH_MACA2HR_MBC      ((uint32_t)0x3F000000)  /* Mask byte control */
08019   #define ETH_MACA2HR_MBC_HBits15_8    ((uint32_t)0x20000000)  /* Mask MAC Address high reg bits [15:8] */
08020   #define ETH_MACA2HR_MBC_HBits7_0     ((uint32_t)0x10000000)  /* Mask MAC Address high reg bits [7:0] */
08021   #define ETH_MACA2HR_MBC_LBits31_24   ((uint32_t)0x08000000)  /* Mask MAC Address low reg bits [31:24] */
08022   #define ETH_MACA2HR_MBC_LBits23_16   ((uint32_t)0x04000000)  /* Mask MAC Address low reg bits [23:16] */
08023   #define ETH_MACA2HR_MBC_LBits15_8    ((uint32_t)0x02000000)  /* Mask MAC Address low reg bits [15:8] */
08024   #define ETH_MACA2HR_MBC_LBits7_0     ((uint32_t)0x01000000)  /* Mask MAC Address low reg bits [70] */
08025 #define ETH_MACA2HR_MACA2H   ((uint32_t)0x0000FFFF)  /* MAC address1 high */
08026
08027 /* Bit definition for Ethernet MAC Address2 Low Register */
08028 #define ETH_MACA2LR_MACA2L   ((uint32_t)0xFFFFFFFF)  /* MAC address2 low */
08029
08030 /* Bit definition for Ethernet MAC Address3 High Register */
08031 #define ETH_MACA3HR_AE       ((uint32_t)0x80000000)  /* Address enable */
08032 #define ETH_MACA3HR_SA       ((uint32_t)0x40000000)  /* Source address */
08033 #define ETH_MACA3HR_MBC      ((uint32_t)0x3F000000)  /* Mask byte control */
08034   #define ETH_MACA3HR_MBC_HBits15_8    ((uint32_t)0x20000000)  /* Mask MAC Address high reg bits [15:8] */
08035   #define ETH_MACA3HR_MBC_HBits7_0     ((uint32_t)0x10000000)  /* Mask MAC Address high reg bits [7:0] */
08036   #define ETH_MACA3HR_MBC_LBits31_24   ((uint32_t)0x08000000)  /* Mask MAC Address low reg bits [31:24] */
08037   #define ETH_MACA3HR_MBC_LBits23_16   ((uint32_t)0x04000000)  /* Mask MAC Address low reg bits [23:16] */
08038   #define ETH_MACA3HR_MBC_LBits15_8    ((uint32_t)0x02000000)  /* Mask MAC Address low reg bits [15:8] */
08039   #define ETH_MACA3HR_MBC_LBits7_0     ((uint32_t)0x01000000)  /* Mask MAC Address low reg bits [70] */
08040 #define ETH_MACA3HR_MACA3H   ((uint32_t)0x0000FFFF)  /* MAC address3 high */
08041
08042 /* Bit definition for Ethernet MAC Address3 Low Register */
08043 #define ETH_MACA3LR_MACA3L   ((uint32_t)0xFFFFFFFF)  /* MAC address3 low */
08044
08045 /******************************************************************************/
08046 /*                Ethernet MMC Registers bits definition                      */
08047 /******************************************************************************/
08048
08049 /* Bit definition for Ethernet MMC Contol Register */
08050 #define ETH_MMCCR_MCF        ((uint32_t)0x00000008)  /* MMC Counter Freeze */
08051 #define ETH_MMCCR_ROR        ((uint32_t)0x00000004)  /* Reset on Read */
08052 #define ETH_MMCCR_CSR        ((uint32_t)0x00000002)  /* Counter Stop Rollover */
08053 #define ETH_MMCCR_CR         ((uint32_t)0x00000001)  /* Counters Reset */
08054
08055 /* Bit definition for Ethernet MMC Receive Interrupt Register */
08056 #define ETH_MMCRIR_RGUFS     ((uint32_t)0x00020000)  /* Set when Rx good unicast frames counter reaches half the maximum value */
08057 #define ETH_MMCRIR_RFAES     ((uint32_t)0x00000040)  /* Set when Rx alignment error counter reaches half the maximum value */
08058 #define ETH_MMCRIR_RFCES     ((uint32_t)0x00000020)  /* Set when Rx crc error counter reaches half the maximum value */
08059
08060 /* Bit definition for Ethernet MMC Transmit Interrupt Register */
08061 #define ETH_MMCTIR_TGFS      ((uint32_t)0x00200000)  /* Set when Tx good frame count counter reaches half the maximum value */
08062 #define ETH_MMCTIR_TGFMSCS   ((uint32_t)0x00008000)  /* Set when Tx good multi col counter reaches half the maximum value */
08063 #define ETH_MMCTIR_TGFSCS    ((uint32_t)0x00004000)  /* Set when Tx good single col counter reaches half the maximum value */
08064
08065 /* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
08066 #define ETH_MMCRIMR_RGUFM    ((uint32_t)0x00020000)  /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
08067 #define ETH_MMCRIMR_RFAEM    ((uint32_t)0x00000040)  /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
08068 #define ETH_MMCRIMR_RFCEM    ((uint32_t)0x00000020)  /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
08069
08070 /* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
08071 #define ETH_MMCTIMR_TGFM     ((uint32_t)0x00200000)  /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
08072 #define ETH_MMCTIMR_TGFMSCM  ((uint32_t)0x00008000)  /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
08073 #define ETH_MMCTIMR_TGFSCM   ((uint32_t)0x00004000)  /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
08074
08075 /* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
08076 #define ETH_MMCTGFSCCR_TGFSCC     ((uint32_t)0xFFFFFFFF)  /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
08077
08078 /* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
08079 #define ETH_MMCTGFMSCCR_TGFMSCC   ((uint32_t)0xFFFFFFFF)  /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
08080
08081 /* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
08082 #define ETH_MMCTGFCR_TGFC    ((uint32_t)0xFFFFFFFF)  /* Number of good frames transmitted. */
08083
08084 /* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
08085 #define ETH_MMCRFCECR_RFCEC  ((uint32_t)0xFFFFFFFF)  /* Number of frames received with CRC error. */
08086
08087 /* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
08088 #define ETH_MMCRFAECR_RFAEC  ((uint32_t)0xFFFFFFFF)  /* Number of frames received with alignment (dribble) error */
08089
08090 /* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
08091 #define ETH_MMCRGUFCR_RGUFC  ((uint32_t)0xFFFFFFFF)  /* Number of good unicast frames received. */
08092
08093 /******************************************************************************/
08094 /*               Ethernet PTP Registers bits definition                       */
08095 /******************************************************************************/
08096
08097 /* Bit definition for Ethernet PTP Time Stamp Contol Register */
08098 #define ETH_PTPTSCR_TSARU    ((uint32_t)0x00000020)  /* Addend register update */
08099 #define ETH_PTPTSCR_TSITE    ((uint32_t)0x00000010)  /* Time stamp interrupt trigger enable */
08100 #define ETH_PTPTSCR_TSSTU    ((uint32_t)0x00000008)  /* Time stamp update */
08101 #define ETH_PTPTSCR_TSSTI    ((uint32_t)0x00000004)  /* Time stamp initialize */
08102 #define ETH_PTPTSCR_TSFCU    ((uint32_t)0x00000002)  /* Time stamp fine or coarse update */
08103 #define ETH_PTPTSCR_TSE      ((uint32_t)0x00000001)  /* Time stamp enable */
08104
08105 /* Bit definition for Ethernet PTP Sub-Second Increment Register */
08106 #define ETH_PTPSSIR_STSSI    ((uint32_t)0x000000FF)  /* System time Sub-second increment value */
08107
08108 /* Bit definition for Ethernet PTP Time Stamp High Register */
08109 #define ETH_PTPTSHR_STS      ((uint32_t)0xFFFFFFFF)  /* System Time second */
08110
08111 /* Bit definition for Ethernet PTP Time Stamp Low Register */
08112 #define ETH_PTPTSLR_STPNS    ((uint32_t)0x80000000)  /* System Time Positive or negative time */
08113 #define ETH_PTPTSLR_STSS     ((uint32_t)0x7FFFFFFF)  /* System Time sub-seconds */
08114
08115 /* Bit definition for Ethernet PTP Time Stamp High Update Register */
08116 #define ETH_PTPTSHUR_TSUS    ((uint32_t)0xFFFFFFFF)  /* Time stamp update seconds */
08117
08118 /* Bit definition for Ethernet PTP Time Stamp Low Update Register */
08119 #define ETH_PTPTSLUR_TSUPNS  ((uint32_t)0x80000000)  /* Time stamp update Positive or negative time */
08120 #define ETH_PTPTSLUR_TSUSS   ((uint32_t)0x7FFFFFFF)  /* Time stamp update sub-seconds */
08121
08122 /* Bit definition for Ethernet PTP Time Stamp Addend Register */
08123 #define ETH_PTPTSAR_TSA      ((uint32_t)0xFFFFFFFF)  /* Time stamp addend */
08124
08125 /* Bit definition for Ethernet PTP Target Time High Register */
08126 #define ETH_PTPTTHR_TTSH     ((uint32_t)0xFFFFFFFF)  /* Target time stamp high */
08127
08128 /* Bit definition for Ethernet PTP Target Time Low Register */
08129 #define ETH_PTPTTLR_TTSL     ((uint32_t)0xFFFFFFFF)  /* Target time stamp low */
08130
08131 /******************************************************************************/
08132 /*                 Ethernet DMA Registers bits definition                     */
08133 /******************************************************************************/
08134
08135 /* Bit definition for Ethernet DMA Bus Mode Register */
08136 #define ETH_DMABMR_AAB       ((uint32_t)0x02000000)  /* Address-Aligned beats */
08137 #define ETH_DMABMR_FPM        ((uint32_t)0x01000000)  /* 4xPBL mode */
08138 #define ETH_DMABMR_USP       ((uint32_t)0x00800000)  /* Use separate PBL */
08139 #define ETH_DMABMR_RDP       ((uint32_t)0x007E0000)  /* RxDMA PBL */
08140   #define ETH_DMABMR_RDP_1Beat    ((uint32_t)0x00020000)  /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
08141   #define ETH_DMABMR_RDP_2Beat    ((uint32_t)0x00040000)  /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
08142   #define ETH_DMABMR_RDP_4Beat    ((uint32_t)0x00080000)  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
08143   #define ETH_DMABMR_RDP_8Beat    ((uint32_t)0x00100000)  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
08144   #define ETH_DMABMR_RDP_16Beat   ((uint32_t)0x00200000)  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
08145   #define ETH_DMABMR_RDP_32Beat   ((uint32_t)0x00400000)  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
08146   #define ETH_DMABMR_RDP_4xPBL_4Beat   ((uint32_t)0x01020000)  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
08147   #define ETH_DMABMR_RDP_4xPBL_8Beat   ((uint32_t)0x01040000)  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
08148   #define ETH_DMABMR_RDP_4xPBL_16Beat  ((uint32_t)0x01080000)  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
08149   #define ETH_DMABMR_RDP_4xPBL_32Beat  ((uint32_t)0x01100000)  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
08150   #define ETH_DMABMR_RDP_4xPBL_64Beat  ((uint32_t)0x01200000)  /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
08151   #define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000)  /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
08152 #define ETH_DMABMR_FB        ((uint32_t)0x00010000)  /* Fixed Burst */
08153 #define ETH_DMABMR_RTPR      ((uint32_t)0x0000C000)  /* Rx Tx priority ratio */
08154   #define ETH_DMABMR_RTPR_1_1     ((uint32_t)0x00000000)  /* Rx Tx priority ratio */
08155   #define ETH_DMABMR_RTPR_2_1     ((uint32_t)0x00004000)  /* Rx Tx priority ratio */
08156   #define ETH_DMABMR_RTPR_3_1     ((uint32_t)0x00008000)  /* Rx Tx priority ratio */
08157   #define ETH_DMABMR_RTPR_4_1     ((uint32_t)0x0000C000)  /* Rx Tx priority ratio */
08158 #define ETH_DMABMR_PBL    ((uint32_t)0x00003F00)  /* Programmable burst length */
08159   #define ETH_DMABMR_PBL_1Beat    ((uint32_t)0x00000100)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
08160   #define ETH_DMABMR_PBL_2Beat    ((uint32_t)0x00000200)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
08161   #define ETH_DMABMR_PBL_4Beat    ((uint32_t)0x00000400)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
08162   #define ETH_DMABMR_PBL_8Beat    ((uint32_t)0x00000800)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
08163   #define ETH_DMABMR_PBL_16Beat   ((uint32_t)0x00001000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
08164   #define ETH_DMABMR_PBL_32Beat   ((uint32_t)0x00002000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
08165   #define ETH_DMABMR_PBL_4xPBL_4Beat   ((uint32_t)0x01000100)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
08166   #define ETH_DMABMR_PBL_4xPBL_8Beat   ((uint32_t)0x01000200)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
08167   #define ETH_DMABMR_PBL_4xPBL_16Beat  ((uint32_t)0x01000400)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
08168   #define ETH_DMABMR_PBL_4xPBL_32Beat  ((uint32_t)0x01000800)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
08169   #define ETH_DMABMR_PBL_4xPBL_64Beat  ((uint32_t)0x01001000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
08170   #define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
08171 #define ETH_DMABMR_DSL       ((uint32_t)0x0000007C)  /* Descriptor Skip Length */
08172 #define ETH_DMABMR_DA        ((uint32_t)0x00000002)  /* DMA arbitration scheme */
08173 #define ETH_DMABMR_SR        ((uint32_t)0x00000001)  /* Software reset */
08174
08175 /* Bit definition for Ethernet DMA Transmit Poll Demand Register */
08176 #define ETH_DMATPDR_TPD      ((uint32_t)0xFFFFFFFF)  /* Transmit poll demand */
08177
08178 /* Bit definition for Ethernet DMA Receive Poll Demand Register */
08179 #define ETH_DMARPDR_RPD      ((uint32_t)0xFFFFFFFF)  /* Receive poll demand  */
08180
08181 /* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
08182 #define ETH_DMARDLAR_SRL     ((uint32_t)0xFFFFFFFF)  /* Start of receive list */
08183
08184 /* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
08185 #define ETH_DMATDLAR_STL     ((uint32_t)0xFFFFFFFF)  /* Start of transmit list */
08186
08187 /* Bit definition for Ethernet DMA Status Register */
08188 #define ETH_DMASR_TSTS       ((uint32_t)0x20000000)  /* Time-stamp trigger status */
08189 #define ETH_DMASR_PMTS       ((uint32_t)0x10000000)  /* PMT status */
08190 #define ETH_DMASR_MMCS       ((uint32_t)0x08000000)  /* MMC status */
08191 #define ETH_DMASR_EBS        ((uint32_t)0x03800000)  /* Error bits status */
08192   /* combination with EBS[2:0] for GetFlagStatus function */
08193   #define ETH_DMASR_EBS_DescAccess      ((uint32_t)0x02000000)  /* Error bits 0-data buffer, 1-desc. access */
08194   #define ETH_DMASR_EBS_ReadTransf      ((uint32_t)0x01000000)  /* Error bits 0-write trnsf, 1-read transfr */
08195   #define ETH_DMASR_EBS_DataTransfTx    ((uint32_t)0x00800000)  /* Error bits 0-Rx DMA, 1-Tx DMA */
08196 #define ETH_DMASR_TPS         ((uint32_t)0x00700000)  /* Transmit process state */
08197   #define ETH_DMASR_TPS_Stopped         ((uint32_t)0x00000000)  /* Stopped - Reset or Stop Tx Command issued  */
08198   #define ETH_DMASR_TPS_Fetching        ((uint32_t)0x00100000)  /* Running - fetching the Tx descriptor */
08199   #define ETH_DMASR_TPS_Waiting         ((uint32_t)0x00200000)  /* Running - waiting for status */
08200   #define ETH_DMASR_TPS_Reading         ((uint32_t)0x00300000)  /* Running - reading the data from host memory */
08201   #define ETH_DMASR_TPS_Suspended       ((uint32_t)0x00600000)  /* Suspended - Tx Descriptor unavailabe */
08202   #define ETH_DMASR_TPS_Closing         ((uint32_t)0x00700000)  /* Running - closing Rx descriptor */
08203 #define ETH_DMASR_RPS         ((uint32_t)0x000E0000)  /* Receive process state */
08204   #define ETH_DMASR_RPS_Stopped         ((uint32_t)0x00000000)  /* Stopped - Reset or Stop Rx Command issued */
08205   #define ETH_DMASR_RPS_Fetching        ((uint32_t)0x00020000)  /* Running - fetching the Rx descriptor */
08206   #define ETH_DMASR_RPS_Waiting         ((uint32_t)0x00060000)  /* Running - waiting for packet */
08207   #define ETH_DMASR_RPS_Suspended       ((uint32_t)0x00080000)  /* Suspended - Rx Descriptor unavailable */
08208   #define ETH_DMASR_RPS_Closing         ((uint32_t)0x000A0000)  /* Running - closing descriptor */
08209   #define ETH_DMASR_RPS_Queuing         ((uint32_t)0x000E0000)  /* Running - queuing the recieve frame into host memory */
08210 #define ETH_DMASR_NIS        ((uint32_t)0x00010000)  /* Normal interrupt summary */
08211 #define ETH_DMASR_AIS        ((uint32_t)0x00008000)  /* Abnormal interrupt summary */
08212 #define ETH_DMASR_ERS        ((uint32_t)0x00004000)  /* Early receive status */
08213 #define ETH_DMASR_FBES       ((uint32_t)0x00002000)  /* Fatal bus error status */
08214 #define ETH_DMASR_ETS        ((uint32_t)0x00000400)  /* Early transmit status */
08215 #define ETH_DMASR_RWTS       ((uint32_t)0x00000200)  /* Receive watchdog timeout status */
08216 #define ETH_DMASR_RPSS       ((uint32_t)0x00000100)  /* Receive process stopped status */
08217 #define ETH_DMASR_RBUS       ((uint32_t)0x00000080)  /* Receive buffer unavailable status */
08218 #define ETH_DMASR_RS         ((uint32_t)0x00000040)  /* Receive status */
08219 #define ETH_DMASR_TUS        ((uint32_t)0x00000020)  /* Transmit underflow status */
08220 #define ETH_DMASR_ROS        ((uint32_t)0x00000010)  /* Receive overflow status */
08221 #define ETH_DMASR_TJTS       ((uint32_t)0x00000008)  /* Transmit jabber timeout status */
08222 #define ETH_DMASR_TBUS       ((uint32_t)0x00000004)  /* Transmit buffer unavailable status */
08223 #define ETH_DMASR_TPSS       ((uint32_t)0x00000002)  /* Transmit process stopped status */
08224 #define ETH_DMASR_TS         ((uint32_t)0x00000001)  /* Transmit status */
08225
08226 /* Bit definition for Ethernet DMA Operation Mode Register */
08227 #define ETH_DMAOMR_DTCEFD    ((uint32_t)0x04000000)  /* Disable Dropping of TCP/IP checksum error frames */
08228 #define ETH_DMAOMR_RSF       ((uint32_t)0x02000000)  /* Receive store and forward */
08229 #define ETH_DMAOMR_DFRF      ((uint32_t)0x01000000)  /* Disable flushing of received frames */
08230 #define ETH_DMAOMR_TSF       ((uint32_t)0x00200000)  /* Transmit store and forward */
08231 #define ETH_DMAOMR_FTF       ((uint32_t)0x00100000)  /* Flush transmit FIFO */
08232 #define ETH_DMAOMR_TTC       ((uint32_t)0x0001C000)  /* Transmit threshold control */
08233   #define ETH_DMAOMR_TTC_64Bytes       ((uint32_t)0x00000000)  /* threshold level of the MTL Transmit FIFO is 64 Bytes */
08234   #define ETH_DMAOMR_TTC_128Bytes      ((uint32_t)0x00004000)  /* threshold level of the MTL Transmit FIFO is 128 Bytes */
08235   #define ETH_DMAOMR_TTC_192Bytes      ((uint32_t)0x00008000)  /* threshold level of the MTL Transmit FIFO is 192 Bytes */
08236   #define ETH_DMAOMR_TTC_256Bytes      ((uint32_t)0x0000C000)  /* threshold level of the MTL Transmit FIFO is 256 Bytes */
08237   #define ETH_DMAOMR_TTC_40Bytes       ((uint32_t)0x00010000)  /* threshold level of the MTL Transmit FIFO is 40 Bytes */
08238   #define ETH_DMAOMR_TTC_32Bytes       ((uint32_t)0x00014000)  /* threshold level of the MTL Transmit FIFO is 32 Bytes */
08239   #define ETH_DMAOMR_TTC_24Bytes       ((uint32_t)0x00018000)  /* threshold level of the MTL Transmit FIFO is 24 Bytes */
08240   #define ETH_DMAOMR_TTC_16Bytes       ((uint32_t)0x0001C000)  /* threshold level of the MTL Transmit FIFO is 16 Bytes */
08241 #define ETH_DMAOMR_ST        ((uint32_t)0x00002000)  /* Start/stop transmission command */
08242 #define ETH_DMAOMR_FEF       ((uint32_t)0x00000080)  /* Forward error frames */
08243 #define ETH_DMAOMR_FUGF      ((uint32_t)0x00000040)  /* Forward undersized good frames */
08244 #define ETH_DMAOMR_RTC       ((uint32_t)0x00000018)  /* receive threshold control */
08245   #define ETH_DMAOMR_RTC_64Bytes       ((uint32_t)0x00000000)  /* threshold level of the MTL Receive FIFO is 64 Bytes */
08246   #define ETH_DMAOMR_RTC_32Bytes       ((uint32_t)0x00000008)  /* threshold level of the MTL Receive FIFO is 32 Bytes */
08247   #define ETH_DMAOMR_RTC_96Bytes       ((uint32_t)0x00000010)  /* threshold level of the MTL Receive FIFO is 96 Bytes */
08248   #define ETH_DMAOMR_RTC_128Bytes      ((uint32_t)0x00000018)  /* threshold level of the MTL Receive FIFO is 128 Bytes */
08249 #define ETH_DMAOMR_OSF       ((uint32_t)0x00000004)  /* operate on second frame */
08250 #define ETH_DMAOMR_SR        ((uint32_t)0x00000002)  /* Start/stop receive */
08251
08252 /* Bit definition for Ethernet DMA Interrupt Enable Register */
08253 #define ETH_DMAIER_NISE      ((uint32_t)0x00010000)  /* Normal interrupt summary enable */
08254 #define ETH_DMAIER_AISE      ((uint32_t)0x00008000)  /* Abnormal interrupt summary enable */
08255 #define ETH_DMAIER_ERIE      ((uint32_t)0x00004000)  /* Early receive interrupt enable */
08256 #define ETH_DMAIER_FBEIE     ((uint32_t)0x00002000)  /* Fatal bus error interrupt enable */
08257 #define ETH_DMAIER_ETIE      ((uint32_t)0x00000400)  /* Early transmit interrupt enable */
08258 #define ETH_DMAIER_RWTIE     ((uint32_t)0x00000200)  /* Receive watchdog timeout interrupt enable */
08259 #define ETH_DMAIER_RPSIE     ((uint32_t)0x00000100)  /* Receive process stopped interrupt enable */
08260 #define ETH_DMAIER_RBUIE     ((uint32_t)0x00000080)  /* Receive buffer unavailable interrupt enable */
08261 #define ETH_DMAIER_RIE       ((uint32_t)0x00000040)  /* Receive interrupt enable */
08262 #define ETH_DMAIER_TUIE      ((uint32_t)0x00000020)  /* Transmit Underflow interrupt enable */
08263 #define ETH_DMAIER_ROIE      ((uint32_t)0x00000010)  /* Receive Overflow interrupt enable */
08264 #define ETH_DMAIER_TJTIE     ((uint32_t)0x00000008)  /* Transmit jabber timeout interrupt enable */
08265 #define ETH_DMAIER_TBUIE     ((uint32_t)0x00000004)  /* Transmit buffer unavailable interrupt enable */
08266 #define ETH_DMAIER_TPSIE     ((uint32_t)0x00000002)  /* Transmit process stopped interrupt enable */
08267 #define ETH_DMAIER_TIE       ((uint32_t)0x00000001)  /* Transmit interrupt enable */
08268
08269 /* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
08270 #define ETH_DMAMFBOCR_OFOC   ((uint32_t)0x10000000)  /* Overflow bit for FIFO overflow counter */
08271 #define ETH_DMAMFBOCR_MFA    ((uint32_t)0x0FFE0000)  /* Number of frames missed by the application */
08272 #define ETH_DMAMFBOCR_OMFC   ((uint32_t)0x00010000)  /* Overflow bit for missed frame counter */
08273 #define ETH_DMAMFBOCR_MFC    ((uint32_t)0x0000FFFF)  /* Number of frames missed by the controller */
08274
08275 /* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
08276 #define ETH_DMACHTDR_HTDAP   ((uint32_t)0xFFFFFFFF)  /* Host transmit descriptor address pointer */
08277
08278 /* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
08279 #define ETH_DMACHRDR_HRDAP   ((uint32_t)0xFFFFFFFF)  /* Host receive descriptor address pointer */
08280
08281 /* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
08282 #define ETH_DMACHTBAR_HTBAP  ((uint32_t)0xFFFFFFFF)  /* Host transmit buffer address pointer */
08283
08284 /* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
08285 #define ETH_DMACHRBAR_HRBAP  ((uint32_t)0xFFFFFFFF)  /* Host receive buffer address pointer */
08286 #endif /* STM32F10X_CL */
08287
08288 /**
08289   * @}
08290   */
08291
08292  /**
08293   * @}
08294   */
08295
08296 #ifdef USE_STDPERIPH_DRIVER
08297   #include "stm32f10x_conf.h"
08298 #endif
08299
08300 /** @addtogroup Exported_macro
08301   * @{
08302   */
08303
08304 #define SET_BIT(REG, BIT)     ((REG) |= (BIT))
08305
08306 #define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
08307
08308 #define READ_BIT(REG, BIT)    ((REG) & (BIT))
08309
08310 #define CLEAR_REG(REG)        ((REG) = (0x0))
08311
08312 #define WRITE_REG(REG, VAL)   ((REG) = (VAL))
08313
08314 #define READ_REG(REG)         ((REG))
08315
08316 #define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
08317
08318 /**
08319   * @}
08320   */
08321
08322 #ifdef __cplusplus
08323 }
08324 #endif
08325
08326 #endif /* __STM32F10x_H */
08327
08328 /**
08329   * @}
08330   */
08331
08332   /**
08333   * @}
08334   */
08335
08336 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_adc.c Source File

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stm32f10x_adc.c

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f10x_adc.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    11-March-2011
00007   * @brief   This file provides all the ADC firmware functions.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x_adc.h"
00024 #include "stm32f10x_rcc.h"
00025
00026 /** @addtogroup STM32F10x_StdPeriph_Driver
00027   * @{
00028   */
00029
00030 /** @defgroup ADC
00031   * @brief ADC driver modules
00032   * @{
00033   */
00034
00035 /** @defgroup ADC_Private_TypesDefinitions
00036   * @{
00037   */
00038
00039 /**
00040   * @}
00041   */
00042
00043 /** @defgroup ADC_Private_Defines
00044   * @{
00045   */
00046
00047 /* ADC DISCNUM mask */
00048 #define CR1_DISCNUM_Reset           ((uint32_t)0xFFFF1FFF)
00049
00050 /* ADC DISCEN mask */
00051 #define CR1_DISCEN_Set              ((uint32_t)0x00000800)
00052 #define CR1_DISCEN_Reset            ((uint32_t)0xFFFFF7FF)
00053
00054 /* ADC JAUTO mask */
00055 #define CR1_JAUTO_Set               ((uint32_t)0x00000400)
00056 #define CR1_JAUTO_Reset             ((uint32_t)0xFFFFFBFF)
00057
00058 /* ADC JDISCEN mask */
00059 #define CR1_JDISCEN_Set             ((uint32_t)0x00001000)
00060 #define CR1_JDISCEN_Reset           ((uint32_t)0xFFFFEFFF)
00061
00062 /* ADC AWDCH mask */
00063 #define CR1_AWDCH_Reset             ((uint32_t)0xFFFFFFE0)
00064
00065 /* ADC Analog watchdog enable mode mask */
00066 #define CR1_AWDMode_Reset           ((uint32_t)0xFF3FFDFF)
00067
00068 /* CR1 register Mask */
00069 #define CR1_CLEAR_Mask              ((uint32_t)0xFFF0FEFF)
00070
00071 /* ADC ADON mask */
00072 #define CR2_ADON_Set                ((uint32_t)0x00000001)
00073 #define CR2_ADON_Reset              ((uint32_t)0xFFFFFFFE)
00074
00075 /* ADC DMA mask */
00076 #define CR2_DMA_Set                 ((uint32_t)0x00000100)
00077 #define CR2_DMA_Reset               ((uint32_t)0xFFFFFEFF)
00078
00079 /* ADC RSTCAL mask */
00080 #define CR2_RSTCAL_Set              ((uint32_t)0x00000008)
00081
00082 /* ADC CAL mask */
00083 #define CR2_CAL_Set                 ((uint32_t)0x00000004)
00084
00085 /* ADC SWSTART mask */
00086 #define CR2_SWSTART_Set             ((uint32_t)0x00400000)
00087
00088 /* ADC EXTTRIG mask */
00089 #define CR2_EXTTRIG_Set             ((uint32_t)0x00100000)
00090 #define CR2_EXTTRIG_Reset           ((uint32_t)0xFFEFFFFF)
00091
00092 /* ADC Software start mask */
00093 #define CR2_EXTTRIG_SWSTART_Set     ((uint32_t)0x00500000)
00094 #define CR2_EXTTRIG_SWSTART_Reset   ((uint32_t)0xFFAFFFFF)
00095
00096 /* ADC JEXTSEL mask */
00097 #define CR2_JEXTSEL_Reset           ((uint32_t)0xFFFF8FFF)
00098
00099 /* ADC JEXTTRIG mask */
00100 #define CR2_JEXTTRIG_Set            ((uint32_t)0x00008000)
00101 #define CR2_JEXTTRIG_Reset          ((uint32_t)0xFFFF7FFF)
00102
00103 /* ADC JSWSTART mask */
00104 #define CR2_JSWSTART_Set            ((uint32_t)0x00200000)
00105
00106 /* ADC injected software start mask */
00107 #define CR2_JEXTTRIG_JSWSTART_Set   ((uint32_t)0x00208000)
00108 #define CR2_JEXTTRIG_JSWSTART_Reset ((uint32_t)0xFFDF7FFF)
00109
00110 /* ADC TSPD mask */
00111 #define CR2_TSVREFE_Set             ((uint32_t)0x00800000)
00112 #define CR2_TSVREFE_Reset           ((uint32_t)0xFF7FFFFF)
00113
00114 /* CR2 register Mask */
00115 #define CR2_CLEAR_Mask              ((uint32_t)0xFFF1F7FD)
00116
00117 /* ADC SQx mask */
00118 #define SQR3_SQ_Set                 ((uint32_t)0x0000001F)
00119 #define SQR2_SQ_Set                 ((uint32_t)0x0000001F)
00120 #define SQR1_SQ_Set                 ((uint32_t)0x0000001F)
00121
00122 /* SQR1 register Mask */
00123 #define SQR1_CLEAR_Mask             ((uint32_t)0xFF0FFFFF)
00124
00125 /* ADC JSQx mask */
00126 #define JSQR_JSQ_Set                ((uint32_t)0x0000001F)
00127
00128 /* ADC JL mask */
00129 #define JSQR_JL_Set                 ((uint32_t)0x00300000)
00130 #define JSQR_JL_Reset               ((uint32_t)0xFFCFFFFF)
00131
00132 /* ADC SMPx mask */
00133 #define SMPR1_SMP_Set               ((uint32_t)0x00000007)
00134 #define SMPR2_SMP_Set               ((uint32_t)0x00000007)
00135
00136 /* ADC JDRx registers offset */
00137 #define JDR_Offset                  ((uint8_t)0x28)
00138
00139 /* ADC1 DR register base address */
00140 #define DR_ADDRESS                  ((uint32_t)0x4001244C)
00141
00142 /**
00143   * @}
00144   */
00145
00146 /** @defgroup ADC_Private_Macros
00147   * @{
00148   */
00149
00150 /**
00151   * @}
00152   */
00153
00154 /** @defgroup ADC_Private_Variables
00155   * @{
00156   */
00157
00158 /**
00159   * @}
00160   */
00161
00162 /** @defgroup ADC_Private_FunctionPrototypes
00163   * @{
00164   */
00165
00166 /**
00167   * @}
00168   */
00169
00170 /** @defgroup ADC_Private_Functions
00171   * @{
00172   */
00173
00174 /**
00175   * @brief  Deinitializes the ADCx peripheral registers to their default reset values.
00176   * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
00177   * @retval None
00178   */
00179 void ADC_DeInit(ADC_TypeDef* ADCx)
00180 {
00181   /* Check the parameters */
00182   assert_param(IS_ADC_ALL_PERIPH(ADCx));
00183
00184   if (ADCx == ADC1)
00185   {
00186     /* Enable ADC1 reset state */
00187     RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE);
00188     /* Release ADC1 from reset state */
00189     RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE);
00190   }
00191   else if (ADCx == ADC2)
00192   {
00193     /* Enable ADC2 reset state */
00194     RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, ENABLE);
00195     /* Release ADC2 from reset state */
00196     RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, DISABLE);
00197   }
00198   else
00199   {
00200     if (ADCx == ADC3)
00201     {
00202       /* Enable ADC3 reset state */
00203       RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC3, ENABLE);
00204       /* Release ADC3 from reset state */
00205       RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC3, DISABLE);
00206     }
00207   }
00208 }
00209
00210 /**
00211   * @brief  Initializes the ADCx peripheral according to the specified parameters
00212   *         in the ADC_InitStruct.
00213   * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
00214   * @param  ADC_InitStruct: pointer to an ADC_InitTypeDef structure that contains
00215   *         the configuration information for the specified ADC peripheral.
00216   * @retval None
00217   */
00218 void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct)
00219 {
00220   uint32_t tmpreg1 = 0;
00221   uint8_t tmpreg2 = 0;
00222   /* Check the parameters */
00223   assert_param(IS_ADC_ALL_PERIPH(ADCx));
00224   assert_param(IS_ADC_MODE(ADC_InitStruct->ADC_Mode));
00225   assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ScanConvMode));
00226   assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ContinuousConvMode));
00227   assert_param(IS_ADC_EXT_TRIG(ADC_InitStruct->ADC_ExternalTrigConv));
00228   assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign));
00229   assert_param(IS_ADC_REGULAR_LENGTH(ADC_InitStruct->ADC_NbrOfChannel));
00230
00231   /*---------------------------- ADCx CR1 Configuration -----------------*/
00232   /* Get the ADCx CR1 value */
00233   tmpreg1 = ADCx->CR1;
00234   /* Clear DUALMOD and SCAN bits */
00235   tmpreg1 &= CR1_CLEAR_Mask;
00236   /* Configure ADCx: Dual mode and scan conversion mode */
00237   /* Set DUALMOD bits according to ADC_Mode value */
00238   /* Set SCAN bit according to ADC_ScanConvMode value */
00239   tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_Mode | ((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8));
00240   /* Write to ADCx CR1 */
00241   ADCx->CR1 = tmpreg1;
00242
00243   /*---------------------------- ADCx CR2 Configuration -----------------*/
00244   /* Get the ADCx CR2 value */
00245   tmpreg1 = ADCx->CR2;
00246   /* Clear CONT, ALIGN and EXTSEL bits */
00247   tmpreg1 &= CR2_CLEAR_Mask;
00248   /* Configure ADCx: external trigger event and continuous conversion mode */
00249   /* Set ALIGN bit according to ADC_DataAlign value */
00250   /* Set EXTSEL bits according to ADC_ExternalTrigConv value */
00251   /* Set CONT bit according to ADC_ContinuousConvMode value */
00252   tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ExternalTrigConv |
00253             ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1));
00254   /* Write to ADCx CR2 */
00255   ADCx->CR2 = tmpreg1;
00256
00257   /*---------------------------- ADCx SQR1 Configuration -----------------*/
00258   /* Get the ADCx SQR1 value */
00259   tmpreg1 = ADCx->SQR1;
00260   /* Clear L bits */
00261   tmpreg1 &= SQR1_CLEAR_Mask;
00262   /* Configure ADCx: regular channel sequence length */
00263   /* Set L bits according to ADC_NbrOfChannel value */
00264   tmpreg2 |= (uint8_t) (ADC_InitStruct->ADC_NbrOfChannel - (uint8_t)1);
00265   tmpreg1 |= (uint32_t)tmpreg2 << 20;
00266   /* Write to ADCx SQR1 */
00267   ADCx->SQR1 = tmpreg1;
00268 }
00269
00270 /**
00271   * @brief  Fills each ADC_InitStruct member with its default value.
00272   * @param  ADC_InitStruct : pointer to an ADC_InitTypeDef structure which will be initialized.
00273   * @retval None
00274   */
00275 void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct)
00276 {
00277   /* Reset ADC init structure parameters values */
00278   /* Initialize the ADC_Mode member */
00279   ADC_InitStruct->ADC_Mode = ADC_Mode_Independent;
00280   /* initialize the ADC_ScanConvMode member */
00281   ADC_InitStruct->ADC_ScanConvMode = DISABLE;
00282   /* Initialize the ADC_ContinuousConvMode member */
00283   ADC_InitStruct->ADC_ContinuousConvMode = DISABLE;
00284   /* Initialize the ADC_ExternalTrigConv member */
00285   ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1;
00286   /* Initialize the ADC_DataAlign member */
00287   ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right;
00288   /* Initialize the ADC_NbrOfChannel member */
00289   ADC_InitStruct->ADC_NbrOfChannel = 1;
00290 }
00291
00292 /**
00293   * @brief  Enables or disables the specified ADC peripheral.
00294   * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
00295   * @param  NewState: new state of the ADCx peripheral.
00296   *   This parameter can be: ENABLE or DISABLE.
00297   * @retval None
00298   */
00299 void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState)
00300 {
00301   /* Check the parameters */
00302   assert_param(IS_ADC_ALL_PERIPH(ADCx));
00303   assert_param(IS_FUNCTIONAL_STATE(NewState));
00304   if (NewState != DISABLE)
00305   {
00306     /* Set the ADON bit to wake up the ADC from power down mode */
00307     ADCx->CR2 |= CR2_ADON_Set;
00308   }
00309   else
00310   {
00311     /* Disable the selected ADC peripheral */
00312     ADCx->CR2 &= CR2_ADON_Reset;
00313   }
00314 }
00315
00316 /**
00317   * @brief  Enables or disables the specified ADC DMA request.
00318   * @param  ADCx: where x can be 1 or 3 to select the ADC peripheral.
00319   *   Note: ADC2 hasn't a DMA capability.
00320   * @param  NewState: new state of the selected ADC DMA transfer.
00321   *   This parameter can be: ENABLE or DISABLE.
00322   * @retval None
00323   */
00324 void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState)
00325 {
00326   /* Check the parameters */
00327   assert_param(IS_ADC_DMA_PERIPH(ADCx));
00328   assert_param(IS_FUNCTIONAL_STATE(NewState));
00329   if (NewState != DISABLE)
00330   {
00331     /* Enable the selected ADC DMA request */
00332     ADCx->CR2 |= CR2_DMA_Set;
00333   }
00334   else
00335   {
00336     /* Disable the selected ADC DMA request */
00337     ADCx->CR2 &= CR2_DMA_Reset;
00338   }
00339 }
00340
00341 /**
00342   * @brief  Enables or disables the specified ADC interrupts.
00343   * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
00344   * @param  ADC_IT: specifies the ADC interrupt sources to be enabled or disabled.
00345   *   This parameter can be any combination of the following values:
00346   *     @arg ADC_IT_EOC: End of conversion interrupt mask
00347   *     @arg ADC_IT_AWD: Analog watchdog interrupt mask
00348   *     @arg ADC_IT_JEOC: End of injected conversion interrupt mask
00349   * @param  NewState: new state of the specified ADC interrupts.
00350   *   This parameter can be: ENABLE or DISABLE.
00351   * @retval None
00352   */
00353 void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState)
00354 {
00355   uint8_t itmask = 0;
00356   /* Check the parameters */
00357   assert_param(IS_ADC_ALL_PERIPH(ADCx));
00358   assert_param(IS_FUNCTIONAL_STATE(NewState));
00359   assert_param(IS_ADC_IT(ADC_IT));
00360   /* Get the ADC IT index */
00361   itmask = (uint8_t)ADC_IT;
00362   if (NewState != DISABLE)
00363   {
00364     /* Enable the selected ADC interrupts */
00365     ADCx->CR1 |= itmask;
00366   }
00367   else
00368   {
00369     /* Disable the selected ADC interrupts */
00370     ADCx->CR1 &= (~(uint32_t)itmask);
00371   }
00372 }
00373
00374 /**
00375   * @brief  Resets the selected ADC calibration registers.
00376   * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
00377   * @retval None
00378   */
00379 void ADC_ResetCalibration(ADC_TypeDef* ADCx)
00380 {
00381   /* Check the parameters */
00382   assert_param(IS_ADC_ALL_PERIPH(ADCx));
00383   /* Resets the selected ADC calibration registers */
00384   ADCx->CR2 |= CR2_RSTCAL_Set;
00385 }
00386
00387 /**
00388   * @brief  Gets the selected ADC reset calibration registers status.
00389   * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
00390   * @retval The new state of ADC reset calibration registers (SET or RESET).
00391   */
00392 FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx)
00393 {
00394   FlagStatus bitstatus = RESET;
00395   /* Check the parameters */
00396   assert_param(IS_ADC_ALL_PERIPH(ADCx));
00397   /* Check the status of RSTCAL bit */
00398   if ((ADCx->CR2 & CR2_RSTCAL_Set) != (uint32_t)RESET)
00399   {
00400     /* RSTCAL bit is set */
00401     bitstatus = SET;
00402   }
00403   else
00404   {
00405     /* RSTCAL bit is reset */
00406     bitstatus = RESET;
00407   }
00408   /* Return the RSTCAL bit status */
00409   return  bitstatus;
00410 }
00411
00412 /**
00413   * @brief  Starts the selected ADC calibration process.
00414   * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
00415   * @retval None
00416   */
00417 void ADC_StartCalibration(ADC_TypeDef* ADCx)
00418 {
00419   /* Check the parameters */
00420   assert_param(IS_ADC_ALL_PERIPH(ADCx));
00421   /* Enable the selected ADC calibration process */
00422   ADCx->CR2 |= CR2_CAL_Set;
00423 }
00424
00425 /**
00426   * @brief  Gets the selected ADC calibration status.
00427   * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
00428   * @retval The new state of ADC calibration (SET or RESET).
00429   */
00430 FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx)
00431 {
00432   FlagStatus bitstatus = RESET;
00433   /* Check the parameters */
00434   assert_param(IS_ADC_ALL_PERIPH(ADCx));
00435   /* Check the status of CAL bit */
00436   if ((ADCx->CR2 & CR2_CAL_Set) != (uint32_t)RESET)
00437   {
00438     /* CAL bit is set: calibration on going */
00439     bitstatus = SET;
00440   }
00441   else
00442   {
00443     /* CAL bit is reset: end of calibration */
00444     bitstatus = RESET;
00445   }
00446   /* Return the CAL bit status */
00447   return  bitstatus;
00448 }
00449
00450 /**
00451   * @brief  Enables or disables the selected ADC software start conversion .
00452   * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
00453   * @param  NewState: new state of the selected ADC software start conversion.
00454   *   This parameter can be: ENABLE or DISABLE.
00455   * @retval None
00456   */
00457 void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
00458 {
00459   /* Check the parameters */
00460   assert_param(IS_ADC_ALL_PERIPH(ADCx));
00461   assert_param(IS_FUNCTIONAL_STATE(NewState));
00462   if (NewState != DISABLE)
00463   {
00464     /* Enable the selected ADC conversion on external event and start the selected
00465        ADC conversion */
00466     ADCx->CR2 |= CR2_EXTTRIG_SWSTART_Set;
00467   }
00468   else
00469   {
00470     /* Disable the selected ADC conversion on external event and stop the selected
00471        ADC conversion */
00472     ADCx->CR2 &= CR2_EXTTRIG_SWSTART_Reset;
00473   }
00474 }
00475
00476 /**
00477   * @brief  Gets the selected ADC Software start conversion Status.
00478   * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
00479   * @retval The new state of ADC software start conversion (SET or RESET).
00480   */
00481 FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx)
00482 {
00483   FlagStatus bitstatus = RESET;
00484   /* Check the parameters */
00485   assert_param(IS_ADC_ALL_PERIPH(ADCx));
00486   /* Check the status of SWSTART bit */
00487   if ((ADCx->CR2 & CR2_SWSTART_Set) != (uint32_t)RESET)
00488   {
00489     /* SWSTART bit is set */
00490     bitstatus = SET;
00491   }
00492   else
00493   {
00494     /* SWSTART bit is reset */
00495     bitstatus = RESET;
00496   }
00497   /* Return the SWSTART bit status */
00498   return  bitstatus;
00499 }
00500
00501 /**
00502   * @brief  Configures the discontinuous mode for the selected ADC regular
00503   *         group channel.
00504   * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
00505   * @param  Number: specifies the discontinuous mode regular channel
00506   *         count value. This number must be between 1 and 8.
00507   * @retval None
00508   */
00509 void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number)
00510 {
00511   uint32_t tmpreg1 = 0;
00512   uint32_t tmpreg2 = 0;
00513   /* Check the parameters */
00514   assert_param(IS_ADC_ALL_PERIPH(ADCx));
00515   assert_param(IS_ADC_REGULAR_DISC_NUMBER(Number));
00516   /* Get the old register value */
00517   tmpreg1 = ADCx->CR1;
00518   /* Clear the old discontinuous mode channel count */
00519   tmpreg1 &= CR1_DISCNUM_Reset;
00520   /* Set the discontinuous mode channel count */
00521   tmpreg2 = Number - 1;
00522   tmpreg1 |= tmpreg2 << 13;
00523   /* Store the new register value */
00524   ADCx->CR1 = tmpreg1;
00525 }
00526
00527 /**
00528   * @brief  Enables or disables the discontinuous mode on regular group
00529   *         channel for the specified ADC
00530   * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
00531   * @param  NewState: new state of the selected ADC discontinuous mode
00532   *         on regular group channel.
00533   *         This parameter can be: ENABLE or DISABLE.
00534   * @retval None
00535   */
00536 void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
00537 {
00538   /* Check the parameters */
00539   assert_param(IS_ADC_ALL_PERIPH(ADCx));
00540   assert_param(IS_FUNCTIONAL_STATE(NewState));
00541   if (NewState != DISABLE)
00542   {
00543     /* Enable the selected ADC regular discontinuous mode */
00544     ADCx->CR1 |= CR1_DISCEN_Set;
00545   }
00546   else
00547   {
00548     /* Disable the selected ADC regular discontinuous mode */
00549     ADCx->CR1 &= CR1_DISCEN_Reset;
00550   }
00551 }
00552
00553 /**
00554   * @brief  Configures for the selected ADC regular channel its corresponding
00555   *         rank in the sequencer and its sample time.
00556   * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
00557   * @param  ADC_Channel: the ADC channel to configure.
00558   *   This parameter can be one of the following values:
00559   *     @arg ADC_Channel_0: ADC Channel0 selected
00560   *     @arg ADC_Channel_1: ADC Channel1 selected
00561   *     @arg ADC_Channel_2: ADC Channel2 selected
00562   *     @arg ADC_Channel_3: ADC Channel3 selected
00563   *     @arg ADC_Channel_4: ADC Channel4 selected
00564   *     @arg ADC_Channel_5: ADC Channel5 selected
00565   *     @arg ADC_Channel_6: ADC Channel6 selected
00566   *     @arg ADC_Channel_7: ADC Channel7 selected
00567   *     @arg ADC_Channel_8: ADC Channel8 selected
00568   *     @arg ADC_Channel_9: ADC Channel9 selected
00569   *     @arg ADC_Channel_10: ADC Channel10 selected
00570   *     @arg ADC_Channel_11: ADC Channel11 selected
00571   *     @arg ADC_Channel_12: ADC Channel12 selected
00572   *     @arg ADC_Channel_13: ADC Channel13 selected
00573   *     @arg ADC_Channel_14: ADC Channel14 selected
00574   *     @arg ADC_Channel_15: ADC Channel15 selected
00575   *     @arg ADC_Channel_16: ADC Channel16 selected
00576   *     @arg ADC_Channel_17: ADC Channel17 selected
00577   * @param  Rank: The rank in the regular group sequencer. This parameter must be between 1 to 16.
00578   * @param  ADC_SampleTime: The sample time value to be set for the selected channel.
00579   *   This parameter can be one of the following values:
00580   *     @arg ADC_SampleTime_1Cycles5: Sample time equal to 1.5 cycles
00581   *     @arg ADC_SampleTime_7Cycles5: Sample time equal to 7.5 cycles
00582   *     @arg ADC_SampleTime_13Cycles5: Sample time equal to 13.5 cycles
00583   *     @arg ADC_SampleTime_28Cycles5: Sample time equal to 28.5 cycles
00584   *     @arg ADC_SampleTime_41Cycles5: Sample time equal to 41.5 cycles
00585   *     @arg ADC_SampleTime_55Cycles5: Sample time equal to 55.5 cycles
00586   *     @arg ADC_SampleTime_71Cycles5: Sample time equal to 71.5 cycles
00587   *     @arg ADC_SampleTime_239Cycles5: Sample time equal to 239.5 cycles
00588   * @retval None
00589   */
00590 void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
00591 {
00592   uint32_t tmpreg1 = 0, tmpreg2 = 0;
00593   /* Check the parameters */
00594   assert_param(IS_ADC_ALL_PERIPH(ADCx));
00595   assert_param(IS_ADC_CHANNEL(ADC_Channel));
00596   assert_param(IS_ADC_REGULAR_RANK(Rank));
00597   assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));
00598   /* if ADC_Channel_10 ... ADC_Channel_17 is selected */
00599   if (ADC_Channel > ADC_Channel_9)
00600   {
00601     /* Get the old register value */
00602     tmpreg1 = ADCx->SMPR1;
00603     /* Calculate the mask to clear */
00604     tmpreg2 = SMPR1_SMP_Set << (3 * (ADC_Channel - 10));
00605     /* Clear the old channel sample time */
00606     tmpreg1 &= ~tmpreg2;
00607     /* Calculate the mask to set */
00608     tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10));
00609     /* Set the new channel sample time */
00610     tmpreg1 |= tmpreg2;
00611     /* Store the new register value */
00612     ADCx->SMPR1 = tmpreg1;
00613   }
00614   else /* ADC_Channel include in ADC_Channel_[0..9] */
00615   {
00616     /* Get the old register value */
00617     tmpreg1 = ADCx->SMPR2;
00618     /* Calculate the mask to clear */
00619     tmpreg2 = SMPR2_SMP_Set << (3 * ADC_Channel);
00620     /* Clear the old channel sample time */
00621     tmpreg1 &= ~tmpreg2;
00622     /* Calculate the mask to set */
00623     tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);
00624     /* Set the new channel sample time */
00625     tmpreg1 |= tmpreg2;
00626     /* Store the new register value */
00627     ADCx->SMPR2 = tmpreg1;
00628   }
00629   /* For Rank 1 to 6 */
00630   if (Rank < 7)
00631   {
00632     /* Get the old register value */
00633     tmpreg1 = ADCx->SQR3;
00634     /* Calculate the mask to clear */
00635     tmpreg2 = SQR3_SQ_Set << (5 * (Rank - 1));
00636     /* Clear the old SQx bits for the selected rank */
00637     tmpreg1 &= ~tmpreg2;
00638     /* Calculate the mask to set */
00639     tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1));
00640     /* Set the SQx bits for the selected rank */
00641     tmpreg1 |= tmpreg2;
00642     /* Store the new register value */
00643     ADCx->SQR3 = tmpreg1;
00644   }
00645   /* For Rank 7 to 12 */
00646   else if (Rank < 13)
00647   {
00648     /* Get the old register value */
00649     tmpreg1 = ADCx->SQR2;
00650     /* Calculate the mask to clear */
00651     tmpreg2 = SQR2_SQ_Set << (5 * (Rank - 7));
00652     /* Clear the old SQx bits for the selected rank */
00653     tmpreg1 &= ~tmpreg2;
00654     /* Calculate the mask to set */
00655     tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7));
00656     /* Set the SQx bits for the selected rank */
00657     tmpreg1 |= tmpreg2;
00658     /* Store the new register value */
00659     ADCx->SQR2 = tmpreg1;
00660   }
00661   /* For Rank 13 to 16 */
00662   else
00663   {
00664     /* Get the old register value */
00665     tmpreg1 = ADCx->SQR1;
00666     /* Calculate the mask to clear */
00667     tmpreg2 = SQR1_SQ_Set << (5 * (Rank - 13));
00668     /* Clear the old SQx bits for the selected rank */
00669     tmpreg1 &= ~tmpreg2;
00670     /* Calculate the mask to set */
00671     tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13));
00672     /* Set the SQx bits for the selected rank */
00673     tmpreg1 |= tmpreg2;
00674     /* Store the new register value */
00675     ADCx->SQR1 = tmpreg1;
00676   }
00677 }
00678
00679 /**
00680   * @brief  Enables or disables the ADCx conversion through external trigger.
00681   * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
00682   * @param  NewState: new state of the selected ADC external trigger start of conversion.
00683   *   This parameter can be: ENABLE or DISABLE.
00684   * @retval None
00685   */
00686 void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
00687 {
00688   /* Check the parameters */
00689   assert_param(IS_ADC_ALL_PERIPH(ADCx));
00690   assert_param(IS_FUNCTIONAL_STATE(NewState));
00691   if (NewState != DISABLE)
00692   {
00693     /* Enable the selected ADC conversion on external event */
00694     ADCx->CR2 |= CR2_EXTTRIG_Set;
00695   }
00696   else
00697   {
00698     /* Disable the selected ADC conversion on external event */
00699     ADCx->CR2 &= CR2_EXTTRIG_Reset;
00700   }
00701 }
00702
00703 /**
00704   * @brief  Returns the last ADCx conversion result data for regular channel.
00705   * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
00706   * @retval The Data conversion value.
00707   */
00708 uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx)
00709 {
00710   /* Check the parameters */
00711   assert_param(IS_ADC_ALL_PERIPH(ADCx));
00712   /* Return the selected ADC conversion value */
00713   return (uint16_t) ADCx->DR;
00714 }
00715
00716 /**
00717   * @brief  Returns the last ADC1 and ADC2 conversion result data in dual mode.
00718   * @retval The Data conversion value.
00719   */
00720 uint32_t ADC_GetDualModeConversionValue(void)
00721 {
00722   /* Return the dual mode conversion value */
00723   return (*(__IO uint32_t *) DR_ADDRESS);
00724 }
00725
00726 /**
00727   * @brief  Enables or disables the selected ADC automatic injected group
00728   *         conversion after regular one.
00729   * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
00730   * @param  NewState: new state of the selected ADC auto injected conversion
00731   *   This parameter can be: ENABLE or DISABLE.
00732   * @retval None
00733   */
00734 void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
00735 {
00736   /* Check the parameters */
00737   assert_param(IS_ADC_ALL_PERIPH(ADCx));
00738   assert_param(IS_FUNCTIONAL_STATE(NewState));
00739   if (NewState != DISABLE)
00740   {
00741     /* Enable the selected ADC automatic injected group conversion */
00742     ADCx->CR1 |= CR1_JAUTO_Set;
00743   }
00744   else
00745   {
00746     /* Disable the selected ADC automatic injected group conversion */
00747     ADCx->CR1 &= CR1_JAUTO_Reset;
00748   }
00749 }
00750
00751 /**
00752   * @brief  Enables or disables the discontinuous mode for injected group
00753   *         channel for the specified ADC
00754   * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
00755   * @param  NewState: new state of the selected ADC discontinuous mode
00756   *         on injected group channel.
00757   *   This parameter can be: ENABLE or DISABLE.
00758   * @retval None
00759   */
00760 void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
00761 {
00762   /* Check the parameters */
00763   assert_param(IS_ADC_ALL_PERIPH(ADCx));
00764   assert_param(IS_FUNCTIONAL_STATE(NewState));
00765   if (NewState != DISABLE)
00766   {
00767     /* Enable the selected ADC injected discontinuous mode */
00768     ADCx->CR1 |= CR1_JDISCEN_Set;
00769   }
00770   else
00771   {
00772     /* Disable the selected ADC injected discontinuous mode */
00773     ADCx->CR1 &= CR1_JDISCEN_Reset;
00774   }
00775 }
00776
00777 /**
00778   * @brief  Configures the ADCx external trigger for injected channels conversion.
00779   * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
00780   * @param  ADC_ExternalTrigInjecConv: specifies the ADC trigger to start injected conversion.
00781   *   This parameter can be one of the following values:
00782   *     @arg ADC_ExternalTrigInjecConv_T1_TRGO: Timer1 TRGO event selected (for ADC1, ADC2 and ADC3)
00783   *     @arg ADC_ExternalTrigInjecConv_T1_CC4: Timer1 capture compare4 selected (for ADC1, ADC2 and ADC3)
00784   *     @arg ADC_ExternalTrigInjecConv_T2_TRGO: Timer2 TRGO event selected (for ADC1 and ADC2)
00785   *     @arg ADC_ExternalTrigInjecConv_T2_CC1: Timer2 capture compare1 selected (for ADC1 and ADC2)
00786   *     @arg ADC_ExternalTrigInjecConv_T3_CC4: Timer3 capture compare4 selected (for ADC1 and ADC2)
00787   *     @arg ADC_ExternalTrigInjecConv_T4_TRGO: Timer4 TRGO event selected (for ADC1 and ADC2)
00788   *     @arg ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4: External interrupt line 15 or Timer8
00789   *                                                       capture compare4 event selected (for ADC1 and ADC2)
00790   *     @arg ADC_ExternalTrigInjecConv_T4_CC3: Timer4 capture compare3 selected (for ADC3 only)
00791   *     @arg ADC_ExternalTrigInjecConv_T8_CC2: Timer8 capture compare2 selected (for ADC3 only)
00792   *     @arg ADC_ExternalTrigInjecConv_T8_CC4: Timer8 capture compare4 selected (for ADC3 only)
00793   *     @arg ADC_ExternalTrigInjecConv_T5_TRGO: Timer5 TRGO event selected (for ADC3 only)
00794   *     @arg ADC_ExternalTrigInjecConv_T5_CC4: Timer5 capture compare4 selected (for ADC3 only)
00795   *     @arg ADC_ExternalTrigInjecConv_None: Injected conversion started by software and not
00796   *                                          by external trigger (for ADC1, ADC2 and ADC3)
00797   * @retval None
00798   */
00799 void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv)
00800 {
00801   uint32_t tmpreg = 0;
00802   /* Check the parameters */
00803   assert_param(IS_ADC_ALL_PERIPH(ADCx));
00804   assert_param(IS_ADC_EXT_INJEC_TRIG(ADC_ExternalTrigInjecConv));
00805   /* Get the old register value */
00806   tmpreg = ADCx->CR2;
00807   /* Clear the old external event selection for injected group */
00808   tmpreg &= CR2_JEXTSEL_Reset;
00809   /* Set the external event selection for injected group */
00810   tmpreg |= ADC_ExternalTrigInjecConv;
00811   /* Store the new register value */
00812   ADCx->CR2 = tmpreg;
00813 }
00814
00815 /**
00816   * @brief  Enables or disables the ADCx injected channels conversion through
00817   *         external trigger
00818   * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
00819   * @param  NewState: new state of the selected ADC external trigger start of
00820   *         injected conversion.
00821   *   This parameter can be: ENABLE or DISABLE.
00822   * @retval None
00823   */
00824 void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
00825 {
00826   /* Check the parameters */
00827   assert_param(IS_ADC_ALL_PERIPH(ADCx));
00828   assert_param(IS_FUNCTIONAL_STATE(NewState));
00829   if (NewState != DISABLE)
00830   {
00831     /* Enable the selected ADC external event selection for injected group */
00832     ADCx->CR2 |= CR2_JEXTTRIG_Set;
00833   }
00834   else
00835   {
00836     /* Disable the selected ADC external event selection for injected group */
00837     ADCx->CR2 &= CR2_JEXTTRIG_Reset;
00838   }
00839 }
00840
00841 /**
00842   * @brief  Enables or disables the selected ADC start of the injected
00843   *         channels conversion.
00844   * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
00845   * @param  NewState: new state of the selected ADC software start injected conversion.
00846   *   This parameter can be: ENABLE or DISABLE.
00847   * @retval None
00848   */
00849 void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
00850 {
00851   /* Check the parameters */
00852   assert_param(IS_ADC_ALL_PERIPH(ADCx));
00853   assert_param(IS_FUNCTIONAL_STATE(NewState));
00854   if (NewState != DISABLE)
00855   {
00856     /* Enable the selected ADC conversion for injected group on external event and start the selected
00857        ADC injected conversion */
00858     ADCx->CR2 |= CR2_JEXTTRIG_JSWSTART_Set;
00859   }
00860   else
00861   {
00862     /* Disable the selected ADC conversion on external event for injected group and stop the selected
00863        ADC injected conversion */
00864     ADCx->CR2 &= CR2_JEXTTRIG_JSWSTART_Reset;
00865   }
00866 }
00867
00868 /**
00869   * @brief  Gets the selected ADC Software start injected conversion Status.
00870   * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
00871   * @retval The new state of ADC software start injected conversion (SET or RESET).
00872   */
00873 FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx)
00874 {
00875   FlagStatus bitstatus = RESET;
00876   /* Check the parameters */
00877   assert_param(IS_ADC_ALL_PERIPH(ADCx));
00878   /* Check the status of JSWSTART bit */
00879   if ((ADCx->CR2 & CR2_JSWSTART_Set) != (uint32_t)RESET)
00880   {
00881     /* JSWSTART bit is set */
00882     bitstatus = SET;
00883   }
00884   else
00885   {
00886     /* JSWSTART bit is reset */
00887     bitstatus = RESET;
00888   }
00889   /* Return the JSWSTART bit status */
00890   return  bitstatus;
00891 }
00892
00893 /**
00894   * @brief  Configures for the selected ADC injected channel its corresponding
00895   *         rank in the sequencer and its sample time.
00896   * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
00897   * @param  ADC_Channel: the ADC channel to configure.
00898   *   This parameter can be one of the following values:
00899   *     @arg ADC_Channel_0: ADC Channel0 selected
00900   *     @arg ADC_Channel_1: ADC Channel1 selected
00901   *     @arg ADC_Channel_2: ADC Channel2 selected
00902   *     @arg ADC_Channel_3: ADC Channel3 selected
00903   *     @arg ADC_Channel_4: ADC Channel4 selected
00904   *     @arg ADC_Channel_5: ADC Channel5 selected
00905   *     @arg ADC_Channel_6: ADC Channel6 selected
00906   *     @arg ADC_Channel_7: ADC Channel7 selected
00907   *     @arg ADC_Channel_8: ADC Channel8 selected
00908   *     @arg ADC_Channel_9: ADC Channel9 selected
00909   *     @arg ADC_Channel_10: ADC Channel10 selected
00910   *     @arg ADC_Channel_11: ADC Channel11 selected
00911   *     @arg ADC_Channel_12: ADC Channel12 selected
00912   *     @arg ADC_Channel_13: ADC Channel13 selected
00913   *     @arg ADC_Channel_14: ADC Channel14 selected
00914   *     @arg ADC_Channel_15: ADC Channel15 selected
00915   *     @arg ADC_Channel_16: ADC Channel16 selected
00916   *     @arg ADC_Channel_17: ADC Channel17 selected
00917   * @param  Rank: The rank in the injected group sequencer. This parameter must be between 1 and 4.
00918   * @param  ADC_SampleTime: The sample time value to be set for the selected channel.
00919   *   This parameter can be one of the following values:
00920   *     @arg ADC_SampleTime_1Cycles5: Sample time equal to 1.5 cycles
00921   *     @arg ADC_SampleTime_7Cycles5: Sample time equal to 7.5 cycles
00922   *     @arg ADC_SampleTime_13Cycles5: Sample time equal to 13.5 cycles
00923   *     @arg ADC_SampleTime_28Cycles5: Sample time equal to 28.5 cycles
00924   *     @arg ADC_SampleTime_41Cycles5: Sample time equal to 41.5 cycles
00925   *     @arg ADC_SampleTime_55Cycles5: Sample time equal to 55.5 cycles
00926   *     @arg ADC_SampleTime_71Cycles5: Sample time equal to 71.5 cycles
00927   *     @arg ADC_SampleTime_239Cycles5: Sample time equal to 239.5 cycles
00928   * @retval None
00929   */
00930 void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
00931 {
00932   uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0;
00933   /* Check the parameters */
00934   assert_param(IS_ADC_ALL_PERIPH(ADCx));
00935   assert_param(IS_ADC_CHANNEL(ADC_Channel));
00936   assert_param(IS_ADC_INJECTED_RANK(Rank));
00937   assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));
00938   /* if ADC_Channel_10 ... ADC_Channel_17 is selected */
00939   if (ADC_Channel > ADC_Channel_9)
00940   {
00941     /* Get the old register value */
00942     tmpreg1 = ADCx->SMPR1;
00943     /* Calculate the mask to clear */
00944     tmpreg2 = SMPR1_SMP_Set << (3*(ADC_Channel - 10));
00945     /* Clear the old channel sample time */
00946     tmpreg1 &= ~tmpreg2;
00947     /* Calculate the mask to set */
00948     tmpreg2 = (uint32_t)ADC_SampleTime << (3*(ADC_Channel - 10));
00949     /* Set the new channel sample time */
00950     tmpreg1 |= tmpreg2;
00951     /* Store the new register value */
00952     ADCx->SMPR1 = tmpreg1;
00953   }
00954   else /* ADC_Channel include in ADC_Channel_[0..9] */
00955   {
00956     /* Get the old register value */
00957     tmpreg1 = ADCx->SMPR2;
00958     /* Calculate the mask to clear */
00959     tmpreg2 = SMPR2_SMP_Set << (3 * ADC_Channel);
00960     /* Clear the old channel sample time */
00961     tmpreg1 &= ~tmpreg2;
00962     /* Calculate the mask to set */
00963     tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);
00964     /* Set the new channel sample time */
00965     tmpreg1 |= tmpreg2;
00966     /* Store the new register value */
00967     ADCx->SMPR2 = tmpreg1;
00968   }
00969   /* Rank configuration */
00970   /* Get the old register value */
00971   tmpreg1 = ADCx->JSQR;
00972   /* Get JL value: Number = JL+1 */
00973   tmpreg3 =  (tmpreg1 & JSQR_JL_Set)>> 20;
00974   /* Calculate the mask to clear: ((Rank-1)+(4-JL-1)) */
00975   tmpreg2 = JSQR_JSQ_Set << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1)));
00976   /* Clear the old JSQx bits for the selected rank */
00977   tmpreg1 &= ~tmpreg2;
00978   /* Calculate the mask to set: ((Rank-1)+(4-JL-1)) */
00979   tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1)));
00980   /* Set the JSQx bits for the selected rank */
00981   tmpreg1 |= tmpreg2;
00982   /* Store the new register value */
00983   ADCx->JSQR = tmpreg1;
00984 }
00985
00986 /**
00987   * @brief  Configures the sequencer length for injected channels
00988   * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
00989   * @param  Length: The sequencer length.
00990   *   This parameter must be a number between 1 to 4.
00991   * @retval None
00992   */
00993 void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length)
00994 {
00995   uint32_t tmpreg1 = 0;
00996   uint32_t tmpreg2 = 0;
00997   /* Check the parameters */
00998   assert_param(IS_ADC_ALL_PERIPH(ADCx));
00999   assert_param(IS_ADC_INJECTED_LENGTH(Length));
01000
01001   /* Get the old register value */
01002   tmpreg1 = ADCx->JSQR;
01003   /* Clear the old injected sequnence lenght JL bits */
01004   tmpreg1 &= JSQR_JL_Reset;
01005   /* Set the injected sequnence lenght JL bits */
01006   tmpreg2 = Length - 1;
01007   tmpreg1 |= tmpreg2 << 20;
01008   /* Store the new register value */
01009   ADCx->JSQR = tmpreg1;
01010 }
01011
01012 /**
01013   * @brief  Set the injected channels conversion value offset
01014   * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
01015   * @param  ADC_InjectedChannel: the ADC injected channel to set its offset.
01016   *   This parameter can be one of the following values:
01017   *     @arg ADC_InjectedChannel_1: Injected Channel1 selected
01018   *     @arg ADC_InjectedChannel_2: Injected Channel2 selected
01019   *     @arg ADC_InjectedChannel_3: Injected Channel3 selected
01020   *     @arg ADC_InjectedChannel_4: Injected Channel4 selected
01021   * @param  Offset: the offset value for the selected ADC injected channel
01022   *   This parameter must be a 12bit value.
01023   * @retval None
01024   */
01025 void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset)
01026 {
01027   __IO uint32_t tmp = 0;
01028
01029   /* Check the parameters */
01030   assert_param(IS_ADC_ALL_PERIPH(ADCx));
01031   assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel));
01032   assert_param(IS_ADC_OFFSET(Offset));
01033
01034   tmp = (uint32_t)ADCx;
01035   tmp += ADC_InjectedChannel;
01036
01037   /* Set the selected injected channel data offset */
01038   *(__IO uint32_t *) tmp = (uint32_t)Offset;
01039 }
01040
01041 /**
01042   * @brief  Returns the ADC injected channel conversion result
01043   * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
01044   * @param  ADC_InjectedChannel: the converted ADC injected channel.
01045   *   This parameter can be one of the following values:
01046   *     @arg ADC_InjectedChannel_1: Injected Channel1 selected
01047   *     @arg ADC_InjectedChannel_2: Injected Channel2 selected
01048   *     @arg ADC_InjectedChannel_3: Injected Channel3 selected
01049   *     @arg ADC_InjectedChannel_4: Injected Channel4 selected
01050   * @retval The Data conversion value.
01051   */
01052 uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel)
01053 {
01054   __IO uint32_t tmp = 0;
01055
01056   /* Check the parameters */
01057   assert_param(IS_ADC_ALL_PERIPH(ADCx));
01058   assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel));
01059
01060   tmp = (uint32_t)ADCx;
01061   tmp += ADC_InjectedChannel + JDR_Offset;
01062
01063   /* Returns the selected injected channel conversion data value */
01064   return (uint16_t) (*(__IO uint32_t*)  tmp);
01065 }
01066
01067 /**
01068   * @brief  Enables or disables the analog watchdog on single/all regular
01069   *         or injected channels
01070   * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
01071   * @param  ADC_AnalogWatchdog: the ADC analog watchdog configuration.
01072   *   This parameter can be one of the following values:
01073   *     @arg ADC_AnalogWatchdog_SingleRegEnable: Analog watchdog on a single regular channel
01074   *     @arg ADC_AnalogWatchdog_SingleInjecEnable: Analog watchdog on a single injected channel
01075   *     @arg ADC_AnalogWatchdog_SingleRegOrInjecEnable: Analog watchdog on a single regular or injected channel
01076   *     @arg ADC_AnalogWatchdog_AllRegEnable: Analog watchdog on  all regular channel
01077   *     @arg ADC_AnalogWatchdog_AllInjecEnable: Analog watchdog on  all injected channel
01078   *     @arg ADC_AnalogWatchdog_AllRegAllInjecEnable: Analog watchdog on all regular and injected channels
01079   *     @arg ADC_AnalogWatchdog_None: No channel guarded by the analog watchdog
01080   * @retval None
01081   */
01082 void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog)
01083 {
01084   uint32_t tmpreg = 0;
01085   /* Check the parameters */
01086   assert_param(IS_ADC_ALL_PERIPH(ADCx));
01087   assert_param(IS_ADC_ANALOG_WATCHDOG(ADC_AnalogWatchdog));
01088   /* Get the old register value */
01089   tmpreg = ADCx->CR1;
01090   /* Clear AWDEN, AWDENJ and AWDSGL bits */
01091   tmpreg &= CR1_AWDMode_Reset;
01092   /* Set the analog watchdog enable mode */
01093   tmpreg |= ADC_AnalogWatchdog;
01094   /* Store the new register value */
01095   ADCx->CR1 = tmpreg;
01096 }
01097
01098 /**
01099   * @brief  Configures the high and low thresholds of the analog watchdog.
01100   * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
01101   * @param  HighThreshold: the ADC analog watchdog High threshold value.
01102   *   This parameter must be a 12bit value.
01103   * @param  LowThreshold: the ADC analog watchdog Low threshold value.
01104   *   This parameter must be a 12bit value.
01105   * @retval None
01106   */
01107 void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,
01108                                         uint16_t LowThreshold)
01109 {
01110   /* Check the parameters */
01111   assert_param(IS_ADC_ALL_PERIPH(ADCx));
01112   assert_param(IS_ADC_THRESHOLD(HighThreshold));
01113   assert_param(IS_ADC_THRESHOLD(LowThreshold));
01114   /* Set the ADCx high threshold */
01115   ADCx->HTR = HighThreshold;
01116   /* Set the ADCx low threshold */
01117   ADCx->LTR = LowThreshold;
01118 }
01119
01120 /**
01121   * @brief  Configures the analog watchdog guarded single channel
01122   * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
01123   * @param  ADC_Channel: the ADC channel to configure for the analog watchdog.
01124   *   This parameter can be one of the following values:
01125   *     @arg ADC_Channel_0: ADC Channel0 selected
01126   *     @arg ADC_Channel_1: ADC Channel1 selected
01127   *     @arg ADC_Channel_2: ADC Channel2 selected
01128   *     @arg ADC_Channel_3: ADC Channel3 selected
01129   *     @arg ADC_Channel_4: ADC Channel4 selected
01130   *     @arg ADC_Channel_5: ADC Channel5 selected
01131   *     @arg ADC_Channel_6: ADC Channel6 selected
01132   *     @arg ADC_Channel_7: ADC Channel7 selected
01133   *     @arg ADC_Channel_8: ADC Channel8 selected
01134   *     @arg ADC_Channel_9: ADC Channel9 selected
01135   *     @arg ADC_Channel_10: ADC Channel10 selected
01136   *     @arg ADC_Channel_11: ADC Channel11 selected
01137   *     @arg ADC_Channel_12: ADC Channel12 selected
01138   *     @arg ADC_Channel_13: ADC Channel13 selected
01139   *     @arg ADC_Channel_14: ADC Channel14 selected
01140   *     @arg ADC_Channel_15: ADC Channel15 selected
01141   *     @arg ADC_Channel_16: ADC Channel16 selected
01142   *     @arg ADC_Channel_17: ADC Channel17 selected
01143   * @retval None
01144   */
01145 void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel)
01146 {
01147   uint32_t tmpreg = 0;
01148   /* Check the parameters */
01149   assert_param(IS_ADC_ALL_PERIPH(ADCx));
01150   assert_param(IS_ADC_CHANNEL(ADC_Channel));
01151   /* Get the old register value */
01152   tmpreg = ADCx->CR1;
01153   /* Clear the Analog watchdog channel select bits */
01154   tmpreg &= CR1_AWDCH_Reset;
01155   /* Set the Analog watchdog channel */
01156   tmpreg |= ADC_Channel;
01157   /* Store the new register value */
01158   ADCx->CR1 = tmpreg;
01159 }
01160
01161 /**
01162   * @brief  Enables or disables the temperature sensor and Vrefint channel.
01163   * @param  NewState: new state of the temperature sensor.
01164   *   This parameter can be: ENABLE or DISABLE.
01165   * @retval None
01166   */
01167 void ADC_TempSensorVrefintCmd(FunctionalState NewState)
01168 {
01169   /* Check the parameters */
01170   assert_param(IS_FUNCTIONAL_STATE(NewState));
01171   if (NewState != DISABLE)
01172   {
01173     /* Enable the temperature sensor and Vrefint channel*/
01174     ADC1->CR2 |= CR2_TSVREFE_Set;
01175   }
01176   else
01177   {
01178     /* Disable the temperature sensor and Vrefint channel*/
01179     ADC1->CR2 &= CR2_TSVREFE_Reset;
01180   }
01181 }
01182
01183 /**
01184   * @brief  Checks whether the specified ADC flag is set or not.
01185   * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
01186   * @param  ADC_FLAG: specifies the flag to check.
01187   *   This parameter can be one of the following values:
01188   *     @arg ADC_FLAG_AWD: Analog watchdog flag
01189   *     @arg ADC_FLAG_EOC: End of conversion flag
01190   *     @arg ADC_FLAG_JEOC: End of injected group conversion flag
01191   *     @arg ADC_FLAG_JSTRT: Start of injected group conversion flag
01192   *     @arg ADC_FLAG_STRT: Start of regular group conversion flag
01193   * @retval The new state of ADC_FLAG (SET or RESET).
01194   */
01195 FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG)
01196 {
01197   FlagStatus bitstatus = RESET;
01198   /* Check the parameters */
01199   assert_param(IS_ADC_ALL_PERIPH(ADCx));
01200   assert_param(IS_ADC_GET_FLAG(ADC_FLAG));
01201   /* Check the status of the specified ADC flag */
01202   if ((ADCx->SR & ADC_FLAG) != (uint8_t)RESET)
01203   {
01204     /* ADC_FLAG is set */
01205     bitstatus = SET;
01206   }
01207   else
01208   {
01209     /* ADC_FLAG is reset */
01210     bitstatus = RESET;
01211   }
01212   /* Return the ADC_FLAG status */
01213   return  bitstatus;
01214 }
01215
01216 /**
01217   * @brief  Clears the ADCx's pending flags.
01218   * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
01219   * @param  ADC_FLAG: specifies the flag to clear.
01220   *   This parameter can be any combination of the following values:
01221   *     @arg ADC_FLAG_AWD: Analog watchdog flag
01222   *     @arg ADC_FLAG_EOC: End of conversion flag
01223   *     @arg ADC_FLAG_JEOC: End of injected group conversion flag
01224   *     @arg ADC_FLAG_JSTRT: Start of injected group conversion flag
01225   *     @arg ADC_FLAG_STRT: Start of regular group conversion flag
01226   * @retval None
01227   */
01228 void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG)
01229 {
01230   /* Check the parameters */
01231   assert_param(IS_ADC_ALL_PERIPH(ADCx));
01232   assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG));
01233   /* Clear the selected ADC flags */
01234   ADCx->SR = ~(uint32_t)ADC_FLAG;
01235 }
01236
01237 /**
01238   * @brief  Checks whether the specified ADC interrupt has occurred or not.
01239   * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
01240   * @param  ADC_IT: specifies the ADC interrupt source to check.
01241   *   This parameter can be one of the following values:
01242   *     @arg ADC_IT_EOC: End of conversion interrupt mask
01243   *     @arg ADC_IT_AWD: Analog watchdog interrupt mask
01244   *     @arg ADC_IT_JEOC: End of injected conversion interrupt mask
01245   * @retval The new state of ADC_IT (SET or RESET).
01246   */
01247 ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT)
01248 {
01249   ITStatus bitstatus = RESET;
01250   uint32_t itmask = 0, enablestatus = 0;
01251   /* Check the parameters */
01252   assert_param(IS_ADC_ALL_PERIPH(ADCx));
01253   assert_param(IS_ADC_GET_IT(ADC_IT));
01254   /* Get the ADC IT index */
01255   itmask = ADC_IT >> 8;
01256   /* Get the ADC_IT enable bit status */
01257   enablestatus = (ADCx->CR1 & (uint8_t)ADC_IT) ;
01258   /* Check the status of the specified ADC interrupt */
01259   if (((ADCx->SR & itmask) != (uint32_t)RESET) && enablestatus)
01260   {
01261     /* ADC_IT is set */
01262     bitstatus = SET;
01263   }
01264   else
01265   {
01266     /* ADC_IT is reset */
01267     bitstatus = RESET;
01268   }
01269   /* Return the ADC_IT status */
01270   return  bitstatus;
01271 }
01272
01273 /**
01274   * @brief  Clears the ADCx's interrupt pending bits.
01275   * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
01276   * @param  ADC_IT: specifies the ADC interrupt pending bit to clear.
01277   *   This parameter can be any combination of the following values:
01278   *     @arg ADC_IT_EOC: End of conversion interrupt mask
01279   *     @arg ADC_IT_AWD: Analog watchdog interrupt mask
01280   *     @arg ADC_IT_JEOC: End of injected conversion interrupt mask
01281   * @retval None
01282   */
01283 void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT)
01284 {
01285   uint8_t itmask = 0;
01286   /* Check the parameters */
01287   assert_param(IS_ADC_ALL_PERIPH(ADCx));
01288   assert_param(IS_ADC_IT(ADC_IT));
01289   /* Get the ADC IT index */
01290   itmask = (uint8_t)(ADC_IT >> 8);
01291   /* Clear the selected ADC interrupt pending bits */
01292   ADCx->SR = ~(uint32_t)itmask;
01293 }
01294
01295 /**
01296   * @}
01297   */
01298
01299 /**
01300   * @}
01301   */
01302
01303 /**
01304   * @}
01305   */
01306
01307 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_adc.h Source File

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stm32f10x_adc.h

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f10x_adc.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    11-March-2011
00007   * @brief   This file contains all the functions prototypes for the ADC firmware
00008   *          library.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00013   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00014   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00015   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00016   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00017   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00018   *
00019   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00020   ******************************************************************************
00021   */
00022
00023 /* Define to prevent recursive inclusion -------------------------------------*/
00024 #ifndef __STM32F10x_ADC_H
00025 #define __STM32F10x_ADC_H
00026
00027 #ifdef __cplusplus
00028  extern "C" {
00029 #endif
00030
00031 /* Includes ------------------------------------------------------------------*/
00032 #include "stm32f10x.h"
00033
00034 /** @addtogroup STM32F10x_StdPeriph_Driver
00035   * @{
00036   */
00037
00038 /** @addtogroup ADC
00039   * @{
00040   */
00041
00042 /** @defgroup ADC_Exported_Types
00043   * @{
00044   */
00045
00046 /**
00047   * @brief  ADC Init structure definition
00048   */
00049
00050 typedef struct
00051 {
00052   uint32_t ADC_Mode;                      /*!< Configures the ADC to operate in independent or
00053                                                dual mode.
00054                                                This parameter can be a value of @ref ADC_mode */
00055
00056   FunctionalState ADC_ScanConvMode;       /*!< Specifies whether the conversion is performed in
00057                                                Scan (multichannels) or Single (one channel) mode.
00058                                                This parameter can be set to ENABLE or DISABLE */
00059
00060   FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion is performed in
00061                                                Continuous or Single mode.
00062                                                This parameter can be set to ENABLE or DISABLE. */
00063
00064   uint32_t ADC_ExternalTrigConv;          /*!< Defines the external trigger used to start the analog
00065                                                to digital conversion of regular channels. This parameter
00066                                                can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */
00067
00068   uint32_t ADC_DataAlign;                 /*!< Specifies whether the ADC data alignment is left or right.
00069                                                This parameter can be a value of @ref ADC_data_align */
00070
00071   uint8_t ADC_NbrOfChannel;               /*!< Specifies the number of ADC channels that will be converted
00072                                                using the sequencer for regular channel group.
00073                                                This parameter must range from 1 to 16. */
00074 }ADC_InitTypeDef;
00075 /**
00076   * @}
00077   */
00078
00079 /** @defgroup ADC_Exported_Constants
00080   * @{
00081   */
00082
00083 #define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) || \
00084                                    ((PERIPH) == ADC2) || \
00085                                    ((PERIPH) == ADC3))
00086
00087 #define IS_ADC_DMA_PERIPH(PERIPH) (((PERIPH) == ADC1) || \
00088                                    ((PERIPH) == ADC3))
00089
00090 /** @defgroup ADC_mode
00091   * @{
00092   */
00093
00094 #define ADC_Mode_Independent                       ((uint32_t)0x00000000)
00095 #define ADC_Mode_RegInjecSimult                    ((uint32_t)0x00010000)
00096 #define ADC_Mode_RegSimult_AlterTrig               ((uint32_t)0x00020000)
00097 #define ADC_Mode_InjecSimult_FastInterl            ((uint32_t)0x00030000)
00098 #define ADC_Mode_InjecSimult_SlowInterl            ((uint32_t)0x00040000)
00099 #define ADC_Mode_InjecSimult                       ((uint32_t)0x00050000)
00100 #define ADC_Mode_RegSimult                         ((uint32_t)0x00060000)
00101 #define ADC_Mode_FastInterl                        ((uint32_t)0x00070000)
00102 #define ADC_Mode_SlowInterl                        ((uint32_t)0x00080000)
00103 #define ADC_Mode_AlterTrig                         ((uint32_t)0x00090000)
00104
00105 #define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \
00106                            ((MODE) == ADC_Mode_RegInjecSimult) || \
00107                            ((MODE) == ADC_Mode_RegSimult_AlterTrig) || \
00108                            ((MODE) == ADC_Mode_InjecSimult_FastInterl) || \
00109                            ((MODE) == ADC_Mode_InjecSimult_SlowInterl) || \
00110                            ((MODE) == ADC_Mode_InjecSimult) || \
00111                            ((MODE) == ADC_Mode_RegSimult) || \
00112                            ((MODE) == ADC_Mode_FastInterl) || \
00113                            ((MODE) == ADC_Mode_SlowInterl) || \
00114                            ((MODE) == ADC_Mode_AlterTrig))
00115 /**
00116   * @}
00117   */
00118
00119 /** @defgroup ADC_external_trigger_sources_for_regular_channels_conversion
00120   * @{
00121   */
00122
00123 #define ADC_ExternalTrigConv_T1_CC1                ((uint32_t)0x00000000) /*!< For ADC1 and ADC2 */
00124 #define ADC_ExternalTrigConv_T1_CC2                ((uint32_t)0x00020000) /*!< For ADC1 and ADC2 */
00125 #define ADC_ExternalTrigConv_T2_CC2                ((uint32_t)0x00060000) /*!< For ADC1 and ADC2 */
00126 #define ADC_ExternalTrigConv_T3_TRGO               ((uint32_t)0x00080000) /*!< For ADC1 and ADC2 */
00127 #define ADC_ExternalTrigConv_T4_CC4                ((uint32_t)0x000A0000) /*!< For ADC1 and ADC2 */
00128 #define ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO    ((uint32_t)0x000C0000) /*!< For ADC1 and ADC2 */
00129
00130 #define ADC_ExternalTrigConv_T1_CC3                ((uint32_t)0x00040000) /*!< For ADC1, ADC2 and ADC3 */
00131 #define ADC_ExternalTrigConv_None                  ((uint32_t)0x000E0000) /*!< For ADC1, ADC2 and ADC3 */
00132
00133 #define ADC_ExternalTrigConv_T3_CC1                ((uint32_t)0x00000000) /*!< For ADC3 only */
00134 #define ADC_ExternalTrigConv_T2_CC3                ((uint32_t)0x00020000) /*!< For ADC3 only */
00135 #define ADC_ExternalTrigConv_T8_CC1                ((uint32_t)0x00060000) /*!< For ADC3 only */
00136 #define ADC_ExternalTrigConv_T8_TRGO               ((uint32_t)0x00080000) /*!< For ADC3 only */
00137 #define ADC_ExternalTrigConv_T5_CC1                ((uint32_t)0x000A0000) /*!< For ADC3 only */
00138 #define ADC_ExternalTrigConv_T5_CC3                ((uint32_t)0x000C0000) /*!< For ADC3 only */
00139
00140 #define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \
00141                                   ((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \
00142                                   ((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || \
00143                                   ((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \
00144                                   ((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \
00145                                   ((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \
00146                                   ((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO) || \
00147                                   ((REGTRIG) == ADC_ExternalTrigConv_None) || \
00148                                   ((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \
00149                                   ((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \
00150                                   ((REGTRIG) == ADC_ExternalTrigConv_T8_CC1) || \
00151                                   ((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO) || \
00152                                   ((REGTRIG) == ADC_ExternalTrigConv_T5_CC1) || \
00153                                   ((REGTRIG) == ADC_ExternalTrigConv_T5_CC3))
00154 /**
00155   * @}
00156   */
00157
00158 /** @defgroup ADC_data_align
00159   * @{
00160   */
00161
00162 #define ADC_DataAlign_Right                        ((uint32_t)0x00000000)
00163 #define ADC_DataAlign_Left                         ((uint32_t)0x00000800)
00164 #define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \
00165                                   ((ALIGN) == ADC_DataAlign_Left))
00166 /**
00167   * @}
00168   */
00169
00170 /** @defgroup ADC_channels
00171   * @{
00172   */
00173
00174 #define ADC_Channel_0                               ((uint8_t)0x00)
00175 #define ADC_Channel_1                               ((uint8_t)0x01)
00176 #define ADC_Channel_2                               ((uint8_t)0x02)
00177 #define ADC_Channel_3                               ((uint8_t)0x03)
00178 #define ADC_Channel_4                               ((uint8_t)0x04)
00179 #define ADC_Channel_5                               ((uint8_t)0x05)
00180 #define ADC_Channel_6                               ((uint8_t)0x06)
00181 #define ADC_Channel_7                               ((uint8_t)0x07)
00182 #define ADC_Channel_8                               ((uint8_t)0x08)
00183 #define ADC_Channel_9                               ((uint8_t)0x09)
00184 #define ADC_Channel_10                              ((uint8_t)0x0A)
00185 #define ADC_Channel_11                              ((uint8_t)0x0B)
00186 #define ADC_Channel_12                              ((uint8_t)0x0C)
00187 #define ADC_Channel_13                              ((uint8_t)0x0D)
00188 #define ADC_Channel_14                              ((uint8_t)0x0E)
00189 #define ADC_Channel_15                              ((uint8_t)0x0F)
00190 #define ADC_Channel_16                              ((uint8_t)0x10)
00191 #define ADC_Channel_17                              ((uint8_t)0x11)
00192
00193 #define ADC_Channel_TempSensor                      ((uint8_t)ADC_Channel_16)
00194 #define ADC_Channel_Vrefint                         ((uint8_t)ADC_Channel_17)
00195
00196 #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || ((CHANNEL) == ADC_Channel_1) || \
00197                                  ((CHANNEL) == ADC_Channel_2) || ((CHANNEL) == ADC_Channel_3) || \
00198                                  ((CHANNEL) == ADC_Channel_4) || ((CHANNEL) == ADC_Channel_5) || \
00199                                  ((CHANNEL) == ADC_Channel_6) || ((CHANNEL) == ADC_Channel_7) || \
00200                                  ((CHANNEL) == ADC_Channel_8) || ((CHANNEL) == ADC_Channel_9) || \
00201                                  ((CHANNEL) == ADC_Channel_10) || ((CHANNEL) == ADC_Channel_11) || \
00202                                  ((CHANNEL) == ADC_Channel_12) || ((CHANNEL) == ADC_Channel_13) || \
00203                                  ((CHANNEL) == ADC_Channel_14) || ((CHANNEL) == ADC_Channel_15) || \
00204                                  ((CHANNEL) == ADC_Channel_16) || ((CHANNEL) == ADC_Channel_17))
00205 /**
00206   * @}
00207   */
00208
00209 /** @defgroup ADC_sampling_time
00210   * @{
00211   */
00212
00213 #define ADC_SampleTime_1Cycles5                    ((uint8_t)0x00)
00214 #define ADC_SampleTime_7Cycles5                    ((uint8_t)0x01)
00215 #define ADC_SampleTime_13Cycles5                   ((uint8_t)0x02)
00216 #define ADC_SampleTime_28Cycles5                   ((uint8_t)0x03)
00217 #define ADC_SampleTime_41Cycles5                   ((uint8_t)0x04)
00218 #define ADC_SampleTime_55Cycles5                   ((uint8_t)0x05)
00219 #define ADC_SampleTime_71Cycles5                   ((uint8_t)0x06)
00220 #define ADC_SampleTime_239Cycles5                  ((uint8_t)0x07)
00221 #define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_1Cycles5) || \
00222                                   ((TIME) == ADC_SampleTime_7Cycles5) || \
00223                                   ((TIME) == ADC_SampleTime_13Cycles5) || \
00224                                   ((TIME) == ADC_SampleTime_28Cycles5) || \
00225                                   ((TIME) == ADC_SampleTime_41Cycles5) || \
00226                                   ((TIME) == ADC_SampleTime_55Cycles5) || \
00227                                   ((TIME) == ADC_SampleTime_71Cycles5) || \
00228                                   ((TIME) == ADC_SampleTime_239Cycles5))
00229 /**
00230   * @}
00231   */
00232
00233 /** @defgroup ADC_external_trigger_sources_for_injected_channels_conversion
00234   * @{
00235   */
00236
00237 #define ADC_ExternalTrigInjecConv_T2_TRGO           ((uint32_t)0x00002000) /*!< For ADC1 and ADC2 */
00238 #define ADC_ExternalTrigInjecConv_T2_CC1            ((uint32_t)0x00003000) /*!< For ADC1 and ADC2 */
00239 #define ADC_ExternalTrigInjecConv_T3_CC4            ((uint32_t)0x00004000) /*!< For ADC1 and ADC2 */
00240 #define ADC_ExternalTrigInjecConv_T4_TRGO           ((uint32_t)0x00005000) /*!< For ADC1 and ADC2 */
00241 #define ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 ((uint32_t)0x00006000) /*!< For ADC1 and ADC2 */
00242
00243 #define ADC_ExternalTrigInjecConv_T1_TRGO           ((uint32_t)0x00000000) /*!< For ADC1, ADC2 and ADC3 */
00244 #define ADC_ExternalTrigInjecConv_T1_CC4            ((uint32_t)0x00001000) /*!< For ADC1, ADC2 and ADC3 */
00245 #define ADC_ExternalTrigInjecConv_None              ((uint32_t)0x00007000) /*!< For ADC1, ADC2 and ADC3 */
00246
00247 #define ADC_ExternalTrigInjecConv_T4_CC3            ((uint32_t)0x00002000) /*!< For ADC3 only */
00248 #define ADC_ExternalTrigInjecConv_T8_CC2            ((uint32_t)0x00003000) /*!< For ADC3 only */
00249 #define ADC_ExternalTrigInjecConv_T8_CC4            ((uint32_t)0x00004000) /*!< For ADC3 only */
00250 #define ADC_ExternalTrigInjecConv_T5_TRGO           ((uint32_t)0x00005000) /*!< For ADC3 only */
00251 #define ADC_ExternalTrigInjecConv_T5_CC4            ((uint32_t)0x00006000) /*!< For ADC3 only */
00252
00253 #define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO) || \
00254                                         ((INJTRIG) == ADC_ExternalTrigInjecConv_T1_CC4) || \
00255                                         ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \
00256                                         ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \
00257                                         ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \
00258                                         ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \
00259                                         ((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4) || \
00260                                         ((INJTRIG) == ADC_ExternalTrigInjecConv_None) || \
00261                                         ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \
00262                                         ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC2) || \
00263                                         ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC4) || \
00264                                         ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO) || \
00265                                         ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_CC4))
00266 /**
00267   * @}
00268   */
00269
00270 /** @defgroup ADC_injected_channel_selection
00271   * @{
00272   */
00273
00274 #define ADC_InjectedChannel_1                       ((uint8_t)0x14)
00275 #define ADC_InjectedChannel_2                       ((uint8_t)0x18)
00276 #define ADC_InjectedChannel_3                       ((uint8_t)0x1C)
00277 #define ADC_InjectedChannel_4                       ((uint8_t)0x20)
00278 #define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \
00279                                           ((CHANNEL) == ADC_InjectedChannel_2) || \
00280                                           ((CHANNEL) == ADC_InjectedChannel_3) || \
00281                                           ((CHANNEL) == ADC_InjectedChannel_4))
00282 /**
00283   * @}
00284   */
00285
00286 /** @defgroup ADC_analog_watchdog_selection
00287   * @{
00288   */
00289
00290 #define ADC_AnalogWatchdog_SingleRegEnable         ((uint32_t)0x00800200)
00291 #define ADC_AnalogWatchdog_SingleInjecEnable       ((uint32_t)0x00400200)
00292 #define ADC_AnalogWatchdog_SingleRegOrInjecEnable  ((uint32_t)0x00C00200)
00293 #define ADC_AnalogWatchdog_AllRegEnable            ((uint32_t)0x00800000)
00294 #define ADC_AnalogWatchdog_AllInjecEnable          ((uint32_t)0x00400000)
00295 #define ADC_AnalogWatchdog_AllRegAllInjecEnable    ((uint32_t)0x00C00000)
00296 #define ADC_AnalogWatchdog_None                    ((uint32_t)0x00000000)
00297
00298 #define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \
00299                                           ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \
00300                                           ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \
00301                                           ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \
00302                                           ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \
00303                                           ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \
00304                                           ((WATCHDOG) == ADC_AnalogWatchdog_None))
00305 /**
00306   * @}
00307   */
00308
00309 /** @defgroup ADC_interrupts_definition
00310   * @{
00311   */
00312
00313 #define ADC_IT_EOC                                 ((uint16_t)0x0220)
00314 #define ADC_IT_AWD                                 ((uint16_t)0x0140)
00315 #define ADC_IT_JEOC                                ((uint16_t)0x0480)
00316
00317 #define IS_ADC_IT(IT) ((((IT) & (uint16_t)0xF81F) == 0x00) && ((IT) != 0x00))
00318
00319 #define IS_ADC_GET_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \
00320                            ((IT) == ADC_IT_JEOC))
00321 /**
00322   * @}
00323   */
00324
00325 /** @defgroup ADC_flags_definition
00326   * @{
00327   */
00328
00329 #define ADC_FLAG_AWD                               ((uint8_t)0x01)
00330 #define ADC_FLAG_EOC                               ((uint8_t)0x02)
00331 #define ADC_FLAG_JEOC                              ((uint8_t)0x04)
00332 #define ADC_FLAG_JSTRT                             ((uint8_t)0x08)
00333 #define ADC_FLAG_STRT                              ((uint8_t)0x10)
00334 #define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint8_t)0xE0) == 0x00) && ((FLAG) != 0x00))
00335 #define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || ((FLAG) == ADC_FLAG_EOC) || \
00336                                ((FLAG) == ADC_FLAG_JEOC) || ((FLAG)== ADC_FLAG_JSTRT) || \
00337                                ((FLAG) == ADC_FLAG_STRT))
00338 /**
00339   * @}
00340   */
00341
00342 /** @defgroup ADC_thresholds
00343   * @{
00344   */
00345
00346 #define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF)
00347
00348 /**
00349   * @}
00350   */
00351
00352 /** @defgroup ADC_injected_offset
00353   * @{
00354   */
00355
00356 #define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF)
00357
00358 /**
00359   * @}
00360   */
00361
00362 /** @defgroup ADC_injected_length
00363   * @{
00364   */
00365
00366 #define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4))
00367
00368 /**
00369   * @}
00370   */
00371
00372 /** @defgroup ADC_injected_rank
00373   * @{
00374   */
00375
00376 #define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4))
00377
00378 /**
00379   * @}
00380   */
00381
00382
00383 /** @defgroup ADC_regular_length
00384   * @{
00385   */
00386
00387 #define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10))
00388 /**
00389   * @}
00390   */
00391
00392 /** @defgroup ADC_regular_rank
00393   * @{
00394   */
00395
00396 #define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10))
00397
00398 /**
00399   * @}
00400   */
00401
00402 /** @defgroup ADC_regular_discontinuous_mode_number
00403   * @{
00404   */
00405
00406 #define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))
00407
00408 /**
00409   * @}
00410   */
00411
00412 /**
00413   * @}
00414   */
00415
00416 /** @defgroup ADC_Exported_Macros
00417   * @{
00418   */
00419
00420 /**
00421   * @}
00422   */
00423
00424 /** @defgroup ADC_Exported_Functions
00425   * @{
00426   */
00427
00428 void ADC_DeInit(ADC_TypeDef* ADCx);
00429 void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);
00430 void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);
00431 void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
00432 void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);
00433 void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState);
00434 void ADC_ResetCalibration(ADC_TypeDef* ADCx);
00435 FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx);
00436 void ADC_StartCalibration(ADC_TypeDef* ADCx);
00437 FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx);
00438 void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
00439 FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx);
00440 void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number);
00441 void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
00442 void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
00443 void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
00444 uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx);
00445 uint32_t ADC_GetDualModeConversionValue(void);
00446 void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
00447 void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
00448 void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv);
00449 void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
00450 void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
00451 FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx);
00452 void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
00453 void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length);
00454 void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset);
00455 uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel);
00456 void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog);
00457 void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, uint16_t LowThreshold);
00458 void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel);
00459 void ADC_TempSensorVrefintCmd(FunctionalState NewState);
00460 FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
00461 void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
00462 ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT);
00463 void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT);
00464
00465 #ifdef __cplusplus
00466 }
00467 #endif
00468
00469 #endif /*__STM32F10x_ADC_H */
00470
00471 /**
00472   * @}
00473   */
00474
00475 /**
00476   * @}
00477   */
00478
00479 /**
00480   * @}
00481   */
00482
00483 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_bkp.c Source File

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stm32f10x_bkp.c

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f10x_bkp.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    11-March-2011
00007   * @brief   This file provides all the BKP firmware functions.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x_bkp.h"
00024 #include "stm32f10x_rcc.h"
00025
00026 /** @addtogroup STM32F10x_StdPeriph_Driver
00027   * @{
00028   */
00029
00030 /** @defgroup BKP
00031   * @brief BKP driver modules
00032   * @{
00033   */
00034
00035 /** @defgroup BKP_Private_TypesDefinitions
00036   * @{
00037   */
00038
00039 /**
00040   * @}
00041   */
00042
00043 /** @defgroup BKP_Private_Defines
00044   * @{
00045   */
00046
00047 /* ------------ BKP registers bit address in the alias region --------------- */
00048 #define BKP_OFFSET        (BKP_BASE - PERIPH_BASE)
00049
00050 /* --- CR Register ----*/
00051
00052 /* Alias word address of TPAL bit */
00053 #define CR_OFFSET         (BKP_OFFSET + 0x30)
00054 #define TPAL_BitNumber    0x01
00055 #define CR_TPAL_BB        (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPAL_BitNumber * 4))
00056
00057 /* Alias word address of TPE bit */
00058 #define TPE_BitNumber     0x00
00059 #define CR_TPE_BB         (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPE_BitNumber * 4))
00060
00061 /* --- CSR Register ---*/
00062
00063 /* Alias word address of TPIE bit */
00064 #define CSR_OFFSET        (BKP_OFFSET + 0x34)
00065 #define TPIE_BitNumber    0x02
00066 #define CSR_TPIE_BB       (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TPIE_BitNumber * 4))
00067
00068 /* Alias word address of TIF bit */
00069 #define TIF_BitNumber     0x09
00070 #define CSR_TIF_BB        (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TIF_BitNumber * 4))
00071
00072 /* Alias word address of TEF bit */
00073 #define TEF_BitNumber     0x08
00074 #define CSR_TEF_BB        (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEF_BitNumber * 4))
00075
00076 /* ---------------------- BKP registers bit mask ------------------------ */
00077
00078 /* RTCCR register bit mask */
00079 #define RTCCR_CAL_MASK    ((uint16_t)0xFF80)
00080 #define RTCCR_MASK        ((uint16_t)0xFC7F)
00081
00082 /**
00083   * @}
00084   */
00085
00086
00087 /** @defgroup BKP_Private_Macros
00088   * @{
00089   */
00090
00091 /**
00092   * @}
00093   */
00094
00095 /** @defgroup BKP_Private_Variables
00096   * @{
00097   */
00098
00099 /**
00100   * @}
00101   */
00102
00103 /** @defgroup BKP_Private_FunctionPrototypes
00104   * @{
00105   */
00106
00107 /**
00108   * @}
00109   */
00110
00111 /** @defgroup BKP_Private_Functions
00112   * @{
00113   */
00114
00115 /**
00116   * @brief  Deinitializes the BKP peripheral registers to their default reset values.
00117   * @param  None
00118   * @retval None
00119   */
00120 void BKP_DeInit(void)
00121 {
00122   RCC_BackupResetCmd(ENABLE);
00123   RCC_BackupResetCmd(DISABLE);
00124 }
00125
00126 /**
00127   * @brief  Configures the Tamper Pin active level.
00128   * @param  BKP_TamperPinLevel: specifies the Tamper Pin active level.
00129   *   This parameter can be one of the following values:
00130   *     @arg BKP_TamperPinLevel_High: Tamper pin active on high level
00131   *     @arg BKP_TamperPinLevel_Low: Tamper pin active on low level
00132   * @retval None
00133   */
00134 void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel)
00135 {
00136   /* Check the parameters */
00137   assert_param(IS_BKP_TAMPER_PIN_LEVEL(BKP_TamperPinLevel));
00138   *(__IO uint32_t *) CR_TPAL_BB = BKP_TamperPinLevel;
00139 }
00140
00141 /**
00142   * @brief  Enables or disables the Tamper Pin activation.
00143   * @param  NewState: new state of the Tamper Pin activation.
00144   *   This parameter can be: ENABLE or DISABLE.
00145   * @retval None
00146   */
00147 void BKP_TamperPinCmd(FunctionalState NewState)
00148 {
00149   /* Check the parameters */
00150   assert_param(IS_FUNCTIONAL_STATE(NewState));
00151   *(__IO uint32_t *) CR_TPE_BB = (uint32_t)NewState;
00152 }
00153
00154 /**
00155   * @brief  Enables or disables the Tamper Pin Interrupt.
00156   * @param  NewState: new state of the Tamper Pin Interrupt.
00157   *   This parameter can be: ENABLE or DISABLE.
00158   * @retval None
00159   */
00160 void BKP_ITConfig(FunctionalState NewState)
00161 {
00162   /* Check the parameters */
00163   assert_param(IS_FUNCTIONAL_STATE(NewState));
00164   *(__IO uint32_t *) CSR_TPIE_BB = (uint32_t)NewState;
00165 }
00166
00167 /**
00168   * @brief  Select the RTC output source to output on the Tamper pin.
00169   * @param  BKP_RTCOutputSource: specifies the RTC output source.
00170   *   This parameter can be one of the following values:
00171   *     @arg BKP_RTCOutputSource_None: no RTC output on the Tamper pin.
00172   *     @arg BKP_RTCOutputSource_CalibClock: output the RTC clock with frequency
00173   *                                          divided by 64 on the Tamper pin.
00174   *     @arg BKP_RTCOutputSource_Alarm: output the RTC Alarm pulse signal on
00175   *                                     the Tamper pin.
00176   *     @arg BKP_RTCOutputSource_Second: output the RTC Second pulse signal on
00177   *                                      the Tamper pin.
00178   * @retval None
00179   */
00180 void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource)
00181 {
00182   uint16_t tmpreg = 0;
00183   /* Check the parameters */
00184   assert_param(IS_BKP_RTC_OUTPUT_SOURCE(BKP_RTCOutputSource));
00185   tmpreg = BKP->RTCCR;
00186   /* Clear CCO, ASOE and ASOS bits */
00187   tmpreg &= RTCCR_MASK;
00188
00189   /* Set CCO, ASOE and ASOS bits according to BKP_RTCOutputSource value */
00190   tmpreg |= BKP_RTCOutputSource;
00191   /* Store the new value */
00192   BKP->RTCCR = tmpreg;
00193 }
00194
00195 /**
00196   * @brief  Sets RTC Clock Calibration value.
00197   * @param  CalibrationValue: specifies the RTC Clock Calibration value.
00198   *   This parameter must be a number between 0 and 0x7F.
00199   * @retval None
00200   */
00201 void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue)
00202 {
00203   uint16_t tmpreg = 0;
00204   /* Check the parameters */
00205   assert_param(IS_BKP_CALIBRATION_VALUE(CalibrationValue));
00206   tmpreg = BKP->RTCCR;
00207   /* Clear CAL[6:0] bits */
00208   tmpreg &= RTCCR_CAL_MASK;
00209   /* Set CAL[6:0] bits according to CalibrationValue value */
00210   tmpreg |= CalibrationValue;
00211   /* Store the new value */
00212   BKP->RTCCR = tmpreg;
00213 }
00214
00215 /**
00216   * @brief  Writes user data to the specified Data Backup Register.
00217   * @param  BKP_DR: specifies the Data Backup Register.
00218   *   This parameter can be BKP_DRx where x:[1, 42]
00219   * @param  Data: data to write
00220   * @retval None
00221   */
00222 void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data)
00223 {
00224   __IO uint32_t tmp = 0;
00225
00226   /* Check the parameters */
00227   assert_param(IS_BKP_DR(BKP_DR));
00228
00229   tmp = (uint32_t)BKP_BASE;
00230   tmp += BKP_DR;
00231
00232   *(__IO uint32_t *) tmp = Data;
00233 }
00234
00235 /**
00236   * @brief  Reads data from the specified Data Backup Register.
00237   * @param  BKP_DR: specifies the Data Backup Register.
00238   *   This parameter can be BKP_DRx where x:[1, 42]
00239   * @retval The content of the specified Data Backup Register
00240   */
00241 uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR)
00242 {
00243   __IO uint32_t tmp = 0;
00244
00245   /* Check the parameters */
00246   assert_param(IS_BKP_DR(BKP_DR));
00247
00248   tmp = (uint32_t)BKP_BASE;
00249   tmp += BKP_DR;
00250
00251   return (*(__IO uint16_t *) tmp);
00252 }
00253
00254 /**
00255   * @brief  Checks whether the Tamper Pin Event flag is set or not.
00256   * @param  None
00257   * @retval The new state of the Tamper Pin Event flag (SET or RESET).
00258   */
00259 FlagStatus BKP_GetFlagStatus(void)
00260 {
00261   return (FlagStatus)(*(__IO uint32_t *) CSR_TEF_BB);
00262 }
00263
00264 /**
00265   * @brief  Clears Tamper Pin Event pending flag.
00266   * @param  None
00267   * @retval None
00268   */
00269 void BKP_ClearFlag(void)
00270 {
00271   /* Set CTE bit to clear Tamper Pin Event flag */
00272   BKP->CSR |= BKP_CSR_CTE;
00273 }
00274
00275 /**
00276   * @brief  Checks whether the Tamper Pin Interrupt has occurred or not.
00277   * @param  None
00278   * @retval The new state of the Tamper Pin Interrupt (SET or RESET).
00279   */
00280 ITStatus BKP_GetITStatus(void)
00281 {
00282   return (ITStatus)(*(__IO uint32_t *) CSR_TIF_BB);
00283 }
00284
00285 /**
00286   * @brief  Clears Tamper Pin Interrupt pending bit.
00287   * @param  None
00288   * @retval None
00289   */
00290 void BKP_ClearITPendingBit(void)
00291 {
00292   /* Set CTI bit to clear Tamper Pin Interrupt pending bit */
00293   BKP->CSR |= BKP_CSR_CTI;
00294 }
00295
00296 /**
00297   * @}
00298   */
00299
00300 /**
00301   * @}
00302   */
00303
00304 /**
00305   * @}
00306   */
00307
00308 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_bkp.h Source File

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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Libraries
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  • inc

stm32f10x_bkp.h

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f10x_bkp.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    11-March-2011
00007   * @brief   This file contains all the functions prototypes for the BKP firmware
00008   *          library.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00013   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00014   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00015   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00016   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00017   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00018   *
00019   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00020   ******************************************************************************
00021   */
00022
00023 /* Define to prevent recursive inclusion -------------------------------------*/
00024 #ifndef __STM32F10x_BKP_H
00025 #define __STM32F10x_BKP_H
00026
00027 #ifdef __cplusplus
00028  extern "C" {
00029 #endif
00030
00031 /* Includes ------------------------------------------------------------------*/
00032 #include "stm32f10x.h"
00033
00034 /** @addtogroup STM32F10x_StdPeriph_Driver
00035   * @{
00036   */
00037
00038 /** @addtogroup BKP
00039   * @{
00040   */
00041
00042 /** @defgroup BKP_Exported_Types
00043   * @{
00044   */
00045
00046 /**
00047   * @}
00048   */
00049
00050 /** @defgroup BKP_Exported_Constants
00051   * @{
00052   */
00053
00054 /** @defgroup Tamper_Pin_active_level
00055   * @{
00056   */
00057
00058 #define BKP_TamperPinLevel_High           ((uint16_t)0x0000)
00059 #define BKP_TamperPinLevel_Low            ((uint16_t)0x0001)
00060 #define IS_BKP_TAMPER_PIN_LEVEL(LEVEL) (((LEVEL) == BKP_TamperPinLevel_High) || \
00061                                         ((LEVEL) == BKP_TamperPinLevel_Low))
00062 /**
00063   * @}
00064   */
00065
00066 /** @defgroup RTC_output_source_to_output_on_the_Tamper_pin
00067   * @{
00068   */
00069
00070 #define BKP_RTCOutputSource_None          ((uint16_t)0x0000)
00071 #define BKP_RTCOutputSource_CalibClock    ((uint16_t)0x0080)
00072 #define BKP_RTCOutputSource_Alarm         ((uint16_t)0x0100)
00073 #define BKP_RTCOutputSource_Second        ((uint16_t)0x0300)
00074 #define IS_BKP_RTC_OUTPUT_SOURCE(SOURCE) (((SOURCE) == BKP_RTCOutputSource_None) || \
00075                                           ((SOURCE) == BKP_RTCOutputSource_CalibClock) || \
00076                                           ((SOURCE) == BKP_RTCOutputSource_Alarm) || \
00077                                           ((SOURCE) == BKP_RTCOutputSource_Second))
00078 /**
00079   * @}
00080   */
00081
00082 /** @defgroup Data_Backup_Register
00083   * @{
00084   */
00085
00086 #define BKP_DR1                           ((uint16_t)0x0004)
00087 #define BKP_DR2                           ((uint16_t)0x0008)
00088 #define BKP_DR3                           ((uint16_t)0x000C)
00089 #define BKP_DR4                           ((uint16_t)0x0010)
00090 #define BKP_DR5                           ((uint16_t)0x0014)
00091 #define BKP_DR6                           ((uint16_t)0x0018)
00092 #define BKP_DR7                           ((uint16_t)0x001C)
00093 #define BKP_DR8                           ((uint16_t)0x0020)
00094 #define BKP_DR9                           ((uint16_t)0x0024)
00095 #define BKP_DR10                          ((uint16_t)0x0028)
00096 #define BKP_DR11                          ((uint16_t)0x0040)
00097 #define BKP_DR12                          ((uint16_t)0x0044)
00098 #define BKP_DR13                          ((uint16_t)0x0048)
00099 #define BKP_DR14                          ((uint16_t)0x004C)
00100 #define BKP_DR15                          ((uint16_t)0x0050)
00101 #define BKP_DR16                          ((uint16_t)0x0054)
00102 #define BKP_DR17                          ((uint16_t)0x0058)
00103 #define BKP_DR18                          ((uint16_t)0x005C)
00104 #define BKP_DR19                          ((uint16_t)0x0060)
00105 #define BKP_DR20                          ((uint16_t)0x0064)
00106 #define BKP_DR21                          ((uint16_t)0x0068)
00107 #define BKP_DR22                          ((uint16_t)0x006C)
00108 #define BKP_DR23                          ((uint16_t)0x0070)
00109 #define BKP_DR24                          ((uint16_t)0x0074)
00110 #define BKP_DR25                          ((uint16_t)0x0078)
00111 #define BKP_DR26                          ((uint16_t)0x007C)
00112 #define BKP_DR27                          ((uint16_t)0x0080)
00113 #define BKP_DR28                          ((uint16_t)0x0084)
00114 #define BKP_DR29                          ((uint16_t)0x0088)
00115 #define BKP_DR30                          ((uint16_t)0x008C)
00116 #define BKP_DR31                          ((uint16_t)0x0090)
00117 #define BKP_DR32                          ((uint16_t)0x0094)
00118 #define BKP_DR33                          ((uint16_t)0x0098)
00119 #define BKP_DR34                          ((uint16_t)0x009C)
00120 #define BKP_DR35                          ((uint16_t)0x00A0)
00121 #define BKP_DR36                          ((uint16_t)0x00A4)
00122 #define BKP_DR37                          ((uint16_t)0x00A8)
00123 #define BKP_DR38                          ((uint16_t)0x00AC)
00124 #define BKP_DR39                          ((uint16_t)0x00B0)
00125 #define BKP_DR40                          ((uint16_t)0x00B4)
00126 #define BKP_DR41                          ((uint16_t)0x00B8)
00127 #define BKP_DR42                          ((uint16_t)0x00BC)
00128
00129 #define IS_BKP_DR(DR) (((DR) == BKP_DR1)  || ((DR) == BKP_DR2)  || ((DR) == BKP_DR3)  || \
00130                        ((DR) == BKP_DR4)  || ((DR) == BKP_DR5)  || ((DR) == BKP_DR6)  || \
00131                        ((DR) == BKP_DR7)  || ((DR) == BKP_DR8)  || ((DR) == BKP_DR9)  || \
00132                        ((DR) == BKP_DR10) || ((DR) == BKP_DR11) || ((DR) == BKP_DR12) || \
00133                        ((DR) == BKP_DR13) || ((DR) == BKP_DR14) || ((DR) == BKP_DR15) || \
00134                        ((DR) == BKP_DR16) || ((DR) == BKP_DR17) || ((DR) == BKP_DR18) || \
00135                        ((DR) == BKP_DR19) || ((DR) == BKP_DR20) || ((DR) == BKP_DR21) || \
00136                        ((DR) == BKP_DR22) || ((DR) == BKP_DR23) || ((DR) == BKP_DR24) || \
00137                        ((DR) == BKP_DR25) || ((DR) == BKP_DR26) || ((DR) == BKP_DR27) || \
00138                        ((DR) == BKP_DR28) || ((DR) == BKP_DR29) || ((DR) == BKP_DR30) || \
00139                        ((DR) == BKP_DR31) || ((DR) == BKP_DR32) || ((DR) == BKP_DR33) || \
00140                        ((DR) == BKP_DR34) || ((DR) == BKP_DR35) || ((DR) == BKP_DR36) || \
00141                        ((DR) == BKP_DR37) || ((DR) == BKP_DR38) || ((DR) == BKP_DR39) || \
00142                        ((DR) == BKP_DR40) || ((DR) == BKP_DR41) || ((DR) == BKP_DR42))
00143
00144 #define IS_BKP_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x7F)
00145 /**
00146   * @}
00147   */
00148
00149 /**
00150   * @}
00151   */
00152
00153 /** @defgroup BKP_Exported_Macros
00154   * @{
00155   */
00156
00157 /**
00158   * @}
00159   */
00160
00161 /** @defgroup BKP_Exported_Functions
00162   * @{
00163   */
00164
00165 void BKP_DeInit(void);
00166 void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel);
00167 void BKP_TamperPinCmd(FunctionalState NewState);
00168 void BKP_ITConfig(FunctionalState NewState);
00169 void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource);
00170 void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue);
00171 void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data);
00172 uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR);
00173 FlagStatus BKP_GetFlagStatus(void);
00174 void BKP_ClearFlag(void);
00175 ITStatus BKP_GetITStatus(void);
00176 void BKP_ClearITPendingBit(void);
00177
00178 #ifdef __cplusplus
00179 }
00180 #endif
00181
00182 #endif /* __STM32F10x_BKP_H */
00183 /**
00184   * @}
00185   */
00186
00187 /**
00188   * @}
00189   */
00190
00191 /**
00192   * @}
00193   */
00194
00195 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_can.c Source File

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stm32f10x_can.c

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f10x_can.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    11-March-2011
00007   * @brief   This file provides all the CAN firmware functions.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x_can.h"
00024 #include "stm32f10x_rcc.h"
00025
00026 /** @addtogroup STM32F10x_StdPeriph_Driver
00027   * @{
00028   */
00029
00030 /** @defgroup CAN
00031   * @brief CAN driver modules
00032   * @{
00033   */
00034
00035 /** @defgroup CAN_Private_TypesDefinitions
00036   * @{
00037   */
00038
00039 /**
00040   * @}
00041   */
00042
00043 /** @defgroup CAN_Private_Defines
00044   * @{
00045   */
00046
00047 /* CAN Master Control Register bits */
00048
00049 #define MCR_DBF      ((uint32_t)0x00010000) /* software master reset */
00050
00051 /* CAN Mailbox Transmit Request */
00052 #define TMIDxR_TXRQ  ((uint32_t)0x00000001) /* Transmit mailbox request */
00053
00054 /* CAN Filter Master Register bits */
00055 #define FMR_FINIT    ((uint32_t)0x00000001) /* Filter init mode */
00056
00057 /* Time out for INAK bit */
00058 #define INAK_TIMEOUT        ((uint32_t)0x0000FFFF)
00059 /* Time out for SLAK bit */
00060 #define SLAK_TIMEOUT        ((uint32_t)0x0000FFFF)
00061
00062
00063
00064 /* Flags in TSR register */
00065 #define CAN_FLAGS_TSR              ((uint32_t)0x08000000)
00066 /* Flags in RF1R register */
00067 #define CAN_FLAGS_RF1R             ((uint32_t)0x04000000)
00068 /* Flags in RF0R register */
00069 #define CAN_FLAGS_RF0R             ((uint32_t)0x02000000)
00070 /* Flags in MSR register */
00071 #define CAN_FLAGS_MSR              ((uint32_t)0x01000000)
00072 /* Flags in ESR register */
00073 #define CAN_FLAGS_ESR              ((uint32_t)0x00F00000)
00074
00075 /* Mailboxes definition */
00076 #define CAN_TXMAILBOX_0                   ((uint8_t)0x00)
00077 #define CAN_TXMAILBOX_1                   ((uint8_t)0x01)
00078 #define CAN_TXMAILBOX_2                   ((uint8_t)0x02)
00079
00080
00081
00082 #define CAN_MODE_MASK              ((uint32_t) 0x00000003)
00083 /**
00084   * @}
00085   */
00086
00087 /** @defgroup CAN_Private_Macros
00088   * @{
00089   */
00090
00091 /**
00092   * @}
00093   */
00094
00095 /** @defgroup CAN_Private_Variables
00096   * @{
00097   */
00098
00099 /**
00100   * @}
00101   */
00102
00103 /** @defgroup CAN_Private_FunctionPrototypes
00104   * @{
00105   */
00106
00107 static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit);
00108
00109 /**
00110   * @}
00111   */
00112
00113 /** @defgroup CAN_Private_Functions
00114   * @{
00115   */
00116
00117 /**
00118   * @brief  Deinitializes the CAN peripheral registers to their default reset values.
00119   * @param  CANx: where x can be 1 or 2 to select the CAN peripheral.
00120   * @retval None.
00121   */
00122 void CAN_DeInit(CAN_TypeDef* CANx)
00123 {
00124   /* Check the parameters */
00125   assert_param(IS_CAN_ALL_PERIPH(CANx));
00126
00127   if (CANx == CAN1)
00128   {
00129     /* Enable CAN1 reset state */
00130     RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, ENABLE);
00131     /* Release CAN1 from reset state */
00132     RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, DISABLE);
00133   }
00134   else
00135   {
00136     /* Enable CAN2 reset state */
00137     RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, ENABLE);
00138     /* Release CAN2 from reset state */
00139     RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, DISABLE);
00140   }
00141 }
00142
00143 /**
00144   * @brief  Initializes the CAN peripheral according to the specified
00145   *         parameters in the CAN_InitStruct.
00146   * @param  CANx:           where x can be 1 or 2 to to select the CAN
00147   *                         peripheral.
00148   * @param  CAN_InitStruct: pointer to a CAN_InitTypeDef structure that
00149   *                         contains the configuration information for the
00150   *                         CAN peripheral.
00151   * @retval Constant indicates initialization succeed which will be
00152   *         CAN_InitStatus_Failed or CAN_InitStatus_Success.
00153   */
00154 uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct)
00155 {
00156   uint8_t InitStatus = CAN_InitStatus_Failed;
00157   uint32_t wait_ack = 0x00000000;
00158   /* Check the parameters */
00159   assert_param(IS_CAN_ALL_PERIPH(CANx));
00160   assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TTCM));
00161   assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_ABOM));
00162   assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_AWUM));
00163   assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_NART));
00164   assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_RFLM));
00165   assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TXFP));
00166   assert_param(IS_CAN_MODE(CAN_InitStruct->CAN_Mode));
00167   assert_param(IS_CAN_SJW(CAN_InitStruct->CAN_SJW));
00168   assert_param(IS_CAN_BS1(CAN_InitStruct->CAN_BS1));
00169   assert_param(IS_CAN_BS2(CAN_InitStruct->CAN_BS2));
00170   assert_param(IS_CAN_PRESCALER(CAN_InitStruct->CAN_Prescaler));
00171
00172   /* Exit from sleep mode */
00173   CANx->MCR &= (~(uint32_t)CAN_MCR_SLEEP);
00174
00175   /* Request initialisation */
00176   CANx->MCR |= CAN_MCR_INRQ ;
00177
00178   /* Wait the acknowledge */
00179   while (((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT))
00180   {
00181     wait_ack++;
00182   }
00183
00184   /* Check acknowledge */
00185   if ((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)
00186   {
00187     InitStatus = CAN_InitStatus_Failed;
00188   }
00189   else
00190   {
00191     /* Set the time triggered communication mode */
00192     if (CAN_InitStruct->CAN_TTCM == ENABLE)
00193     {
00194       CANx->MCR |= CAN_MCR_TTCM;
00195     }
00196     else
00197     {
00198       CANx->MCR &= ~(uint32_t)CAN_MCR_TTCM;
00199     }
00200
00201     /* Set the automatic bus-off management */
00202     if (CAN_InitStruct->CAN_ABOM == ENABLE)
00203     {
00204       CANx->MCR |= CAN_MCR_ABOM;
00205     }
00206     else
00207     {
00208       CANx->MCR &= ~(uint32_t)CAN_MCR_ABOM;
00209     }
00210
00211     /* Set the automatic wake-up mode */
00212     if (CAN_InitStruct->CAN_AWUM == ENABLE)
00213     {
00214       CANx->MCR |= CAN_MCR_AWUM;
00215     }
00216     else
00217     {
00218       CANx->MCR &= ~(uint32_t)CAN_MCR_AWUM;
00219     }
00220
00221     /* Set the no automatic retransmission */
00222     if (CAN_InitStruct->CAN_NART == ENABLE)
00223     {
00224       CANx->MCR |= CAN_MCR_NART;
00225     }
00226     else
00227     {
00228       CANx->MCR &= ~(uint32_t)CAN_MCR_NART;
00229     }
00230
00231     /* Set the receive FIFO locked mode */
00232     if (CAN_InitStruct->CAN_RFLM == ENABLE)
00233     {
00234       CANx->MCR |= CAN_MCR_RFLM;
00235     }
00236     else
00237     {
00238       CANx->MCR &= ~(uint32_t)CAN_MCR_RFLM;
00239     }
00240
00241     /* Set the transmit FIFO priority */
00242     if (CAN_InitStruct->CAN_TXFP == ENABLE)
00243     {
00244       CANx->MCR |= CAN_MCR_TXFP;
00245     }
00246     else
00247     {
00248       CANx->MCR &= ~(uint32_t)CAN_MCR_TXFP;
00249     }
00250
00251     /* Set the bit timing register */
00252     CANx->BTR = (uint32_t)((uint32_t)CAN_InitStruct->CAN_Mode << 30) | \
00253                 ((uint32_t)CAN_InitStruct->CAN_SJW << 24) | \
00254                 ((uint32_t)CAN_InitStruct->CAN_BS1 << 16) | \
00255                 ((uint32_t)CAN_InitStruct->CAN_BS2 << 20) | \
00256                ((uint32_t)CAN_InitStruct->CAN_Prescaler - 1);
00257
00258     /* Request leave initialisation */
00259     CANx->MCR &= ~(uint32_t)CAN_MCR_INRQ;
00260
00261    /* Wait the acknowledge */
00262    wait_ack = 0;
00263
00264    while (((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT))
00265    {
00266      wait_ack++;
00267    }
00268
00269     /* ...and check acknowledged */
00270     if ((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
00271     {
00272       InitStatus = CAN_InitStatus_Failed;
00273     }
00274     else
00275     {
00276       InitStatus = CAN_InitStatus_Success ;
00277     }
00278   }
00279
00280   /* At this step, return the status of initialization */
00281   return InitStatus;
00282 }
00283
00284 /**
00285   * @brief  Initializes the CAN peripheral according to the specified
00286   *         parameters in the CAN_FilterInitStruct.
00287   * @param  CAN_FilterInitStruct: pointer to a CAN_FilterInitTypeDef
00288   *                               structure that contains the configuration
00289   *                               information.
00290   * @retval None.
00291   */
00292 void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct)
00293 {
00294   uint32_t filter_number_bit_pos = 0;
00295   /* Check the parameters */
00296   assert_param(IS_CAN_FILTER_NUMBER(CAN_FilterInitStruct->CAN_FilterNumber));
00297   assert_param(IS_CAN_FILTER_MODE(CAN_FilterInitStruct->CAN_FilterMode));
00298   assert_param(IS_CAN_FILTER_SCALE(CAN_FilterInitStruct->CAN_FilterScale));
00299   assert_param(IS_CAN_FILTER_FIFO(CAN_FilterInitStruct->CAN_FilterFIFOAssignment));
00300   assert_param(IS_FUNCTIONAL_STATE(CAN_FilterInitStruct->CAN_FilterActivation));
00301
00302   filter_number_bit_pos = ((uint32_t)1) << CAN_FilterInitStruct->CAN_FilterNumber;
00303
00304   /* Initialisation mode for the filter */
00305   CAN1->FMR |= FMR_FINIT;
00306
00307   /* Filter Deactivation */
00308   CAN1->FA1R &= ~(uint32_t)filter_number_bit_pos;
00309
00310   /* Filter Scale */
00311   if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_16bit)
00312   {
00313     /* 16-bit scale for the filter */
00314     CAN1->FS1R &= ~(uint32_t)filter_number_bit_pos;
00315
00316     /* First 16-bit identifier and First 16-bit mask */
00317     /* Or First 16-bit identifier and Second 16-bit identifier */
00318     CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 =
00319     ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow) << 16) |
00320         (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow);
00321
00322     /* Second 16-bit identifier and Second 16-bit mask */
00323     /* Or Third 16-bit identifier and Fourth 16-bit identifier */
00324     CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 =
00325     ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) |
00326         (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh);
00327   }
00328
00329   if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_32bit)
00330   {
00331     /* 32-bit scale for the filter */
00332     CAN1->FS1R |= filter_number_bit_pos;
00333     /* 32-bit identifier or First 32-bit identifier */
00334     CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 =
00335     ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh) << 16) |
00336         (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow);
00337     /* 32-bit mask or Second 32-bit identifier */
00338     CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 =
00339     ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) |
00340         (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow);
00341   }
00342
00343   /* Filter Mode */
00344   if (CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdMask)
00345   {
00346     /*Id/Mask mode for the filter*/
00347     CAN1->FM1R &= ~(uint32_t)filter_number_bit_pos;
00348   }
00349   else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */
00350   {
00351     /*Identifier list mode for the filter*/
00352     CAN1->FM1R |= (uint32_t)filter_number_bit_pos;
00353   }
00354
00355   /* Filter FIFO assignment */
00356   if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO0)
00357   {
00358     /* FIFO 0 assignation for the filter */
00359     CAN1->FFA1R &= ~(uint32_t)filter_number_bit_pos;
00360   }
00361
00362   if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO1)
00363   {
00364     /* FIFO 1 assignation for the filter */
00365     CAN1->FFA1R |= (uint32_t)filter_number_bit_pos;
00366   }
00367
00368   /* Filter activation */
00369   if (CAN_FilterInitStruct->CAN_FilterActivation == ENABLE)
00370   {
00371     CAN1->FA1R |= filter_number_bit_pos;
00372   }
00373
00374   /* Leave the initialisation mode for the filter */
00375   CAN1->FMR &= ~FMR_FINIT;
00376 }
00377
00378 /**
00379   * @brief  Fills each CAN_InitStruct member with its default value.
00380   * @param  CAN_InitStruct: pointer to a CAN_InitTypeDef structure which
00381   *                         will be initialized.
00382   * @retval None.
00383   */
00384 void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct)
00385 {
00386   /* Reset CAN init structure parameters values */
00387
00388   /* Initialize the time triggered communication mode */
00389   CAN_InitStruct->CAN_TTCM = DISABLE;
00390
00391   /* Initialize the automatic bus-off management */
00392   CAN_InitStruct->CAN_ABOM = DISABLE;
00393
00394   /* Initialize the automatic wake-up mode */
00395   CAN_InitStruct->CAN_AWUM = DISABLE;
00396
00397   /* Initialize the no automatic retransmission */
00398   CAN_InitStruct->CAN_NART = DISABLE;
00399
00400   /* Initialize the receive FIFO locked mode */
00401   CAN_InitStruct->CAN_RFLM = DISABLE;
00402
00403   /* Initialize the transmit FIFO priority */
00404   CAN_InitStruct->CAN_TXFP = DISABLE;
00405
00406   /* Initialize the CAN_Mode member */
00407   CAN_InitStruct->CAN_Mode = CAN_Mode_Normal;
00408
00409   /* Initialize the CAN_SJW member */
00410   CAN_InitStruct->CAN_SJW = CAN_SJW_1tq;
00411
00412   /* Initialize the CAN_BS1 member */
00413   CAN_InitStruct->CAN_BS1 = CAN_BS1_4tq;
00414
00415   /* Initialize the CAN_BS2 member */
00416   CAN_InitStruct->CAN_BS2 = CAN_BS2_3tq;
00417
00418   /* Initialize the CAN_Prescaler member */
00419   CAN_InitStruct->CAN_Prescaler = 1;
00420 }
00421
00422 /**
00423   * @brief  Select the start bank filter for slave CAN.
00424   * @note   This function applies only to STM32 Connectivity line devices.
00425   * @param  CAN_BankNumber: Select the start slave bank filter from 1..27.
00426   * @retval None.
00427   */
00428 void CAN_SlaveStartBank(uint8_t CAN_BankNumber)
00429 {
00430   /* Check the parameters */
00431   assert_param(IS_CAN_BANKNUMBER(CAN_BankNumber));
00432
00433   /* Enter Initialisation mode for the filter */
00434   CAN1->FMR |= FMR_FINIT;
00435
00436   /* Select the start slave bank */
00437   CAN1->FMR &= (uint32_t)0xFFFFC0F1 ;
00438   CAN1->FMR |= (uint32_t)(CAN_BankNumber)<<8;
00439
00440   /* Leave Initialisation mode for the filter */
00441   CAN1->FMR &= ~FMR_FINIT;
00442 }
00443
00444 /**
00445   * @brief  Enables or disables the DBG Freeze for CAN.
00446   * @param  CANx:     where x can be 1 or 2 to to select the CAN peripheral.
00447   * @param  NewState: new state of the CAN peripheral. This parameter can
00448   *                   be: ENABLE or DISABLE.
00449   * @retval None.
00450   */
00451 void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState)
00452 {
00453   /* Check the parameters */
00454   assert_param(IS_CAN_ALL_PERIPH(CANx));
00455   assert_param(IS_FUNCTIONAL_STATE(NewState));
00456
00457   if (NewState != DISABLE)
00458   {
00459     /* Enable Debug Freeze  */
00460     CANx->MCR |= MCR_DBF;
00461   }
00462   else
00463   {
00464     /* Disable Debug Freeze */
00465     CANx->MCR &= ~MCR_DBF;
00466   }
00467 }
00468
00469
00470 /**
00471   * @brief  Enables or disabes the CAN Time TriggerOperation communication mode.
00472   * @param  CANx:      where x can be 1 or 2 to to select the CAN peripheral.
00473   * @param  NewState : Mode new state , can be one of @ref FunctionalState.
00474   * @note   when enabled, Time stamp (TIME[15:0]) value is sent in the last
00475   *         two data bytes of the 8-byte message: TIME[7:0] in data byte 6
00476   *         and TIME[15:8] in data byte 7
00477   * @note   DLC must be programmed as 8 in order Time Stamp (2 bytes) to be
00478   *         sent over the CAN bus.
00479   * @retval None
00480   */
00481 void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState)
00482 {
00483   /* Check the parameters */
00484   assert_param(IS_CAN_ALL_PERIPH(CANx));
00485   assert_param(IS_FUNCTIONAL_STATE(NewState));
00486   if (NewState != DISABLE)
00487   {
00488     /* Enable the TTCM mode */
00489     CANx->MCR |= CAN_MCR_TTCM;
00490
00491     /* Set TGT bits */
00492     CANx->sTxMailBox[0].TDTR |= ((uint32_t)CAN_TDT0R_TGT);
00493     CANx->sTxMailBox[1].TDTR |= ((uint32_t)CAN_TDT1R_TGT);
00494     CANx->sTxMailBox[2].TDTR |= ((uint32_t)CAN_TDT2R_TGT);
00495   }
00496   else
00497   {
00498     /* Disable the TTCM mode */
00499     CANx->MCR &= (uint32_t)(~(uint32_t)CAN_MCR_TTCM);
00500
00501     /* Reset TGT bits */
00502     CANx->sTxMailBox[0].TDTR &= ((uint32_t)~CAN_TDT0R_TGT);
00503     CANx->sTxMailBox[1].TDTR &= ((uint32_t)~CAN_TDT1R_TGT);
00504     CANx->sTxMailBox[2].TDTR &= ((uint32_t)~CAN_TDT2R_TGT);
00505   }
00506 }
00507 /**
00508   * @brief  Initiates the transmission of a message.
00509   * @param  CANx:      where x can be 1 or 2 to to select the CAN peripheral.
00510   * @param  TxMessage: pointer to a structure which contains CAN Id, CAN
00511   *                    DLC and CAN data.
00512   * @retval The number of the mailbox that is used for transmission
00513   *                    or CAN_TxStatus_NoMailBox if there is no empty mailbox.
00514   */
00515 uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage)
00516 {
00517   uint8_t transmit_mailbox = 0;
00518   /* Check the parameters */
00519   assert_param(IS_CAN_ALL_PERIPH(CANx));
00520   assert_param(IS_CAN_IDTYPE(TxMessage->IDE));
00521   assert_param(IS_CAN_RTR(TxMessage->RTR));
00522   assert_param(IS_CAN_DLC(TxMessage->DLC));
00523
00524   /* Select one empty transmit mailbox */
00525   if ((CANx->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)
00526   {
00527     transmit_mailbox = 0;
00528   }
00529   else if ((CANx->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)
00530   {
00531     transmit_mailbox = 1;
00532   }
00533   else if ((CANx->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)
00534   {
00535     transmit_mailbox = 2;
00536   }
00537   else
00538   {
00539     transmit_mailbox = CAN_TxStatus_NoMailBox;
00540   }
00541
00542   if (transmit_mailbox != CAN_TxStatus_NoMailBox)
00543   {
00544     /* Set up the Id */
00545     CANx->sTxMailBox[transmit_mailbox].TIR &= TMIDxR_TXRQ;
00546     if (TxMessage->IDE == CAN_Id_Standard)
00547     {
00548       assert_param(IS_CAN_STDID(TxMessage->StdId));
00549       CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->StdId << 21) | \
00550                                                   TxMessage->RTR);
00551     }
00552     else
00553     {
00554       assert_param(IS_CAN_EXTID(TxMessage->ExtId));
00555       CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->ExtId << 3) | \
00556                                                   TxMessage->IDE | \
00557                                                   TxMessage->RTR);
00558     }
00559
00560     /* Set up the DLC */
00561     TxMessage->DLC &= (uint8_t)0x0000000F;
00562     CANx->sTxMailBox[transmit_mailbox].TDTR &= (uint32_t)0xFFFFFFF0;
00563     CANx->sTxMailBox[transmit_mailbox].TDTR |= TxMessage->DLC;
00564
00565     /* Set up the data field */
00566     CANx->sTxMailBox[transmit_mailbox].TDLR = (((uint32_t)TxMessage->Data[3] << 24) |
00567                                              ((uint32_t)TxMessage->Data[2] << 16) |
00568                                              ((uint32_t)TxMessage->Data[1] << 8) |
00569                                              ((uint32_t)TxMessage->Data[0]));
00570     CANx->sTxMailBox[transmit_mailbox].TDHR = (((uint32_t)TxMessage->Data[7] << 24) |
00571                                              ((uint32_t)TxMessage->Data[6] << 16) |
00572                                              ((uint32_t)TxMessage->Data[5] << 8) |
00573                                              ((uint32_t)TxMessage->Data[4]));
00574     /* Request transmission */
00575     CANx->sTxMailBox[transmit_mailbox].TIR |= TMIDxR_TXRQ;
00576   }
00577   return transmit_mailbox;
00578 }
00579
00580 /**
00581   * @brief  Checks the transmission of a message.
00582   * @param  CANx:            where x can be 1 or 2 to to select the
00583   *                          CAN peripheral.
00584   * @param  TransmitMailbox: the number of the mailbox that is used for
00585   *                          transmission.
00586   * @retval CAN_TxStatus_Ok if the CAN driver transmits the message, CAN_TxStatus_Failed
00587   *         in an other case.
00588   */
00589 uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox)
00590 {
00591   uint32_t state = 0;
00592
00593   /* Check the parameters */
00594   assert_param(IS_CAN_ALL_PERIPH(CANx));
00595   assert_param(IS_CAN_TRANSMITMAILBOX(TransmitMailbox));
00596
00597   switch (TransmitMailbox)
00598   {
00599     case (CAN_TXMAILBOX_0):
00600       state =   CANx->TSR &  (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0);
00601       break;
00602     case (CAN_TXMAILBOX_1):
00603       state =   CANx->TSR &  (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1);
00604       break;
00605     case (CAN_TXMAILBOX_2):
00606       state =   CANx->TSR &  (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2);
00607       break;
00608     default:
00609       state = CAN_TxStatus_Failed;
00610       break;
00611   }
00612   switch (state)
00613   {
00614       /* transmit pending  */
00615     case (0x0): state = CAN_TxStatus_Pending;
00616       break;
00617       /* transmit failed  */
00618      case (CAN_TSR_RQCP0 | CAN_TSR_TME0): state = CAN_TxStatus_Failed;
00619       break;
00620      case (CAN_TSR_RQCP1 | CAN_TSR_TME1): state = CAN_TxStatus_Failed;
00621       break;
00622      case (CAN_TSR_RQCP2 | CAN_TSR_TME2): state = CAN_TxStatus_Failed;
00623       break;
00624       /* transmit succeeded  */
00625     case (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0):state = CAN_TxStatus_Ok;
00626       break;
00627     case (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1):state = CAN_TxStatus_Ok;
00628       break;
00629     case (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2):state = CAN_TxStatus_Ok;
00630       break;
00631     default: state = CAN_TxStatus_Failed;
00632       break;
00633   }
00634   return (uint8_t) state;
00635 }
00636
00637 /**
00638   * @brief  Cancels a transmit request.
00639   * @param  CANx:     where x can be 1 or 2 to to select the CAN peripheral.
00640   * @param  Mailbox:  Mailbox number.
00641   * @retval None.
00642   */
00643 void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox)
00644 {
00645   /* Check the parameters */
00646   assert_param(IS_CAN_ALL_PERIPH(CANx));
00647   assert_param(IS_CAN_TRANSMITMAILBOX(Mailbox));
00648   /* abort transmission */
00649   switch (Mailbox)
00650   {
00651     case (CAN_TXMAILBOX_0): CANx->TSR |= CAN_TSR_ABRQ0;
00652       break;
00653     case (CAN_TXMAILBOX_1): CANx->TSR |= CAN_TSR_ABRQ1;
00654       break;
00655     case (CAN_TXMAILBOX_2): CANx->TSR |= CAN_TSR_ABRQ2;
00656       break;
00657     default:
00658       break;
00659   }
00660 }
00661
00662
00663 /**
00664   * @brief  Receives a message.
00665   * @param  CANx:       where x can be 1 or 2 to to select the CAN peripheral.
00666   * @param  FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
00667   * @param  RxMessage:  pointer to a structure receive message which contains
00668   *                     CAN Id, CAN DLC, CAN datas and FMI number.
00669   * @retval None.
00670   */
00671 void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage)
00672 {
00673   /* Check the parameters */
00674   assert_param(IS_CAN_ALL_PERIPH(CANx));
00675   assert_param(IS_CAN_FIFO(FIFONumber));
00676   /* Get the Id */
00677   RxMessage->IDE = (uint8_t)0x04 & CANx->sFIFOMailBox[FIFONumber].RIR;
00678   if (RxMessage->IDE == CAN_Id_Standard)
00679   {
00680     RxMessage->StdId = (uint32_t)0x000007FF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 21);
00681   }
00682   else
00683   {
00684     RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 3);
00685   }
00686
00687   RxMessage->RTR = (uint8_t)0x02 & CANx->sFIFOMailBox[FIFONumber].RIR;
00688   /* Get the DLC */
00689   RxMessage->DLC = (uint8_t)0x0F & CANx->sFIFOMailBox[FIFONumber].RDTR;
00690   /* Get the FMI */
00691   RxMessage->FMI = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDTR >> 8);
00692   /* Get the data field */
00693   RxMessage->Data[0] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDLR;
00694   RxMessage->Data[1] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 8);
00695   RxMessage->Data[2] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 16);
00696   RxMessage->Data[3] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 24);
00697   RxMessage->Data[4] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDHR;
00698   RxMessage->Data[5] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 8);
00699   RxMessage->Data[6] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 16);
00700   RxMessage->Data[7] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 24);
00701   /* Release the FIFO */
00702   /* Release FIFO0 */
00703   if (FIFONumber == CAN_FIFO0)
00704   {
00705     CANx->RF0R |= CAN_RF0R_RFOM0;
00706   }
00707   /* Release FIFO1 */
00708   else /* FIFONumber == CAN_FIFO1 */
00709   {
00710     CANx->RF1R |= CAN_RF1R_RFOM1;
00711   }
00712 }
00713
00714 /**
00715   * @brief  Releases the specified FIFO.
00716   * @param  CANx:       where x can be 1 or 2 to to select the CAN peripheral.
00717   * @param  FIFONumber: FIFO to release, CAN_FIFO0 or CAN_FIFO1.
00718   * @retval None.
00719   */
00720 void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber)
00721 {
00722   /* Check the parameters */
00723   assert_param(IS_CAN_ALL_PERIPH(CANx));
00724   assert_param(IS_CAN_FIFO(FIFONumber));
00725   /* Release FIFO0 */
00726   if (FIFONumber == CAN_FIFO0)
00727   {
00728     CANx->RF0R |= CAN_RF0R_RFOM0;
00729   }
00730   /* Release FIFO1 */
00731   else /* FIFONumber == CAN_FIFO1 */
00732   {
00733     CANx->RF1R |= CAN_RF1R_RFOM1;
00734   }
00735 }
00736
00737 /**
00738   * @brief  Returns the number of pending messages.
00739   * @param  CANx:       where x can be 1 or 2 to to select the CAN peripheral.
00740   * @param  FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
00741   * @retval NbMessage : which is the number of pending message.
00742   */
00743 uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber)
00744 {
00745   uint8_t message_pending=0;
00746   /* Check the parameters */
00747   assert_param(IS_CAN_ALL_PERIPH(CANx));
00748   assert_param(IS_CAN_FIFO(FIFONumber));
00749   if (FIFONumber == CAN_FIFO0)
00750   {
00751     message_pending = (uint8_t)(CANx->RF0R&(uint32_t)0x03);
00752   }
00753   else if (FIFONumber == CAN_FIFO1)
00754   {
00755     message_pending = (uint8_t)(CANx->RF1R&(uint32_t)0x03);
00756   }
00757   else
00758   {
00759     message_pending = 0;
00760   }
00761   return message_pending;
00762 }
00763
00764
00765 /**
00766   * @brief   Select the CAN Operation mode.
00767   * @param CAN_OperatingMode : CAN Operating Mode. This parameter can be one
00768   *                            of @ref CAN_OperatingMode_TypeDef enumeration.
00769   * @retval status of the requested mode which can be
00770   *         - CAN_ModeStatus_Failed    CAN failed entering the specific mode
00771   *         - CAN_ModeStatus_Success   CAN Succeed entering the specific mode
00772
00773   */
00774 uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode)
00775 {
00776   uint8_t status = CAN_ModeStatus_Failed;
00777
00778   /* Timeout for INAK or also for SLAK bits*/
00779   uint32_t timeout = INAK_TIMEOUT;
00780
00781   /* Check the parameters */
00782   assert_param(IS_CAN_ALL_PERIPH(CANx));
00783   assert_param(IS_CAN_OPERATING_MODE(CAN_OperatingMode));
00784
00785   if (CAN_OperatingMode == CAN_OperatingMode_Initialization)
00786   {
00787     /* Request initialisation */
00788     CANx->MCR = (uint32_t)((CANx->MCR & (uint32_t)(~(uint32_t)CAN_MCR_SLEEP)) | CAN_MCR_INRQ);
00789
00790     /* Wait the acknowledge */
00791     while (((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_INAK) && (timeout != 0))
00792     {
00793       timeout--;
00794     }
00795     if ((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_INAK)
00796     {
00797       status = CAN_ModeStatus_Failed;
00798     }
00799     else
00800     {
00801       status = CAN_ModeStatus_Success;
00802     }
00803   }
00804   else  if (CAN_OperatingMode == CAN_OperatingMode_Normal)
00805   {
00806     /* Request leave initialisation and sleep mode  and enter Normal mode */
00807     CANx->MCR &= (uint32_t)(~(CAN_MCR_SLEEP|CAN_MCR_INRQ));
00808
00809     /* Wait the acknowledge */
00810     while (((CANx->MSR & CAN_MODE_MASK) != 0) && (timeout!=0))
00811     {
00812       timeout--;
00813     }
00814     if ((CANx->MSR & CAN_MODE_MASK) != 0)
00815     {
00816       status = CAN_ModeStatus_Failed;
00817     }
00818     else
00819     {
00820       status = CAN_ModeStatus_Success;
00821     }
00822   }
00823   else  if (CAN_OperatingMode == CAN_OperatingMode_Sleep)
00824   {
00825     /* Request Sleep mode */
00826     CANx->MCR = (uint32_t)((CANx->MCR & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP);
00827
00828     /* Wait the acknowledge */
00829     while (((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK) && (timeout!=0))
00830     {
00831       timeout--;
00832     }
00833     if ((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK)
00834     {
00835       status = CAN_ModeStatus_Failed;
00836     }
00837     else
00838     {
00839       status = CAN_ModeStatus_Success;
00840     }
00841   }
00842   else
00843   {
00844     status = CAN_ModeStatus_Failed;
00845   }
00846
00847   return  (uint8_t) status;
00848 }
00849
00850 /**
00851   * @brief  Enters the low power mode.
00852   * @param  CANx:   where x can be 1 or 2 to to select the CAN peripheral.
00853   * @retval status: CAN_Sleep_Ok if sleep entered, CAN_Sleep_Failed in an
00854   *                 other case.
00855   */
00856 uint8_t CAN_Sleep(CAN_TypeDef* CANx)
00857 {
00858   uint8_t sleepstatus = CAN_Sleep_Failed;
00859
00860   /* Check the parameters */
00861   assert_param(IS_CAN_ALL_PERIPH(CANx));
00862
00863   /* Request Sleep mode */
00864    CANx->MCR = (((CANx->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP);
00865
00866   /* Sleep mode status */
00867   if ((CANx->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) == CAN_MSR_SLAK)
00868   {
00869     /* Sleep mode not entered */
00870     sleepstatus =  CAN_Sleep_Ok;
00871   }
00872   /* return sleep mode status */
00873    return (uint8_t)sleepstatus;
00874 }
00875
00876 /**
00877   * @brief  Wakes the CAN up.
00878   * @param  CANx:    where x can be 1 or 2 to to select the CAN peripheral.
00879   * @retval status:  CAN_WakeUp_Ok if sleep mode left, CAN_WakeUp_Failed in an
00880   *                  other case.
00881   */
00882 uint8_t CAN_WakeUp(CAN_TypeDef* CANx)
00883 {
00884   uint32_t wait_slak = SLAK_TIMEOUT;
00885   uint8_t wakeupstatus = CAN_WakeUp_Failed;
00886
00887   /* Check the parameters */
00888   assert_param(IS_CAN_ALL_PERIPH(CANx));
00889
00890   /* Wake up request */
00891   CANx->MCR &= ~(uint32_t)CAN_MCR_SLEEP;
00892
00893   /* Sleep mode status */
00894   while(((CANx->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)&&(wait_slak!=0x00))
00895   {
00896    wait_slak--;
00897   }
00898   if((CANx->MSR & CAN_MSR_SLAK) != CAN_MSR_SLAK)
00899   {
00900    /* wake up done : Sleep mode exited */
00901     wakeupstatus = CAN_WakeUp_Ok;
00902   }
00903   /* return wakeup status */
00904   return (uint8_t)wakeupstatus;
00905 }
00906
00907
00908 /**
00909   * @brief  Returns the CANx's last error code (LEC).
00910   * @param  CANx:          where x can be 1 or 2 to to select the CAN peripheral.
00911   * @retval CAN_ErrorCode: specifies the Error code :
00912   *                        - CAN_ERRORCODE_NoErr            No Error
00913   *                        - CAN_ERRORCODE_StuffErr         Stuff Error
00914   *                        - CAN_ERRORCODE_FormErr          Form Error
00915   *                        - CAN_ERRORCODE_ACKErr           Acknowledgment Error
00916   *                        - CAN_ERRORCODE_BitRecessiveErr  Bit Recessive Error
00917   *                        - CAN_ERRORCODE_BitDominantErr   Bit Dominant Error
00918   *                        - CAN_ERRORCODE_CRCErr           CRC Error
00919   *                        - CAN_ERRORCODE_SoftwareSetErr   Software Set Error
00920   */
00921
00922 uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx)
00923 {
00924   uint8_t errorcode=0;
00925
00926   /* Check the parameters */
00927   assert_param(IS_CAN_ALL_PERIPH(CANx));
00928
00929   /* Get the error code*/
00930   errorcode = (((uint8_t)CANx->ESR) & (uint8_t)CAN_ESR_LEC);
00931
00932   /* Return the error code*/
00933   return errorcode;
00934 }
00935 /**
00936   * @brief  Returns the CANx Receive Error Counter (REC).
00937   * @note   In case of an error during reception, this counter is incremented
00938   *         by 1 or by 8 depending on the error condition as defined by the CAN
00939   *         standard. After every successful reception, the counter is
00940   *         decremented by 1 or reset to 120 if its value was higher than 128.
00941   *         When the counter value exceeds 127, the CAN controller enters the
00942   *         error passive state.
00943   * @param  CANx: where x can be 1 or 2 to to select the CAN peripheral.
00944   * @retval CAN Receive Error Counter.
00945   */
00946 uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx)
00947 {
00948   uint8_t counter=0;
00949
00950   /* Check the parameters */
00951   assert_param(IS_CAN_ALL_PERIPH(CANx));
00952
00953   /* Get the Receive Error Counter*/
00954   counter = (uint8_t)((CANx->ESR & CAN_ESR_REC)>> 24);
00955
00956   /* Return the Receive Error Counter*/
00957   return counter;
00958 }
00959
00960
00961 /**
00962   * @brief  Returns the LSB of the 9-bit CANx Transmit Error Counter(TEC).
00963   * @param  CANx:   where x can be 1 or 2 to to select the CAN peripheral.
00964   * @retval LSB of the 9-bit CAN Transmit Error Counter.
00965   */
00966 uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx)
00967 {
00968   uint8_t counter=0;
00969
00970   /* Check the parameters */
00971   assert_param(IS_CAN_ALL_PERIPH(CANx));
00972
00973   /* Get the LSB of the 9-bit CANx Transmit Error Counter(TEC) */
00974   counter = (uint8_t)((CANx->ESR & CAN_ESR_TEC)>> 16);
00975
00976   /* Return the LSB of the 9-bit CANx Transmit Error Counter(TEC) */
00977   return counter;
00978 }
00979
00980
00981 /**
00982   * @brief  Enables or disables the specified CANx interrupts.
00983   * @param  CANx:   where x can be 1 or 2 to to select the CAN peripheral.
00984   * @param  CAN_IT: specifies the CAN interrupt sources to be enabled or disabled.
00985   *                 This parameter can be:
00986   *                 - CAN_IT_TME,
00987   *                 - CAN_IT_FMP0,
00988   *                 - CAN_IT_FF0,
00989   *                 - CAN_IT_FOV0,
00990   *                 - CAN_IT_FMP1,
00991   *                 - CAN_IT_FF1,
00992   *                 - CAN_IT_FOV1,
00993   *                 - CAN_IT_EWG,
00994   *                 - CAN_IT_EPV,
00995   *                 - CAN_IT_LEC,
00996   *                 - CAN_IT_ERR,
00997   *                 - CAN_IT_WKU or
00998   *                 - CAN_IT_SLK.
00999   * @param  NewState: new state of the CAN interrupts.
01000   *                   This parameter can be: ENABLE or DISABLE.
01001   * @retval None.
01002   */
01003 void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState)
01004 {
01005   /* Check the parameters */
01006   assert_param(IS_CAN_ALL_PERIPH(CANx));
01007   assert_param(IS_CAN_IT(CAN_IT));
01008   assert_param(IS_FUNCTIONAL_STATE(NewState));
01009
01010   if (NewState != DISABLE)
01011   {
01012     /* Enable the selected CANx interrupt */
01013     CANx->IER |= CAN_IT;
01014   }
01015   else
01016   {
01017     /* Disable the selected CANx interrupt */
01018     CANx->IER &= ~CAN_IT;
01019   }
01020 }
01021 /**
01022   * @brief  Checks whether the specified CAN flag is set or not.
01023   * @param  CANx:     where x can be 1 or 2 to to select the CAN peripheral.
01024   * @param  CAN_FLAG: specifies the flag to check.
01025   *                   This parameter can be one of the following flags:
01026   *                  - CAN_FLAG_EWG
01027   *                  - CAN_FLAG_EPV
01028   *                  - CAN_FLAG_BOF
01029   *                  - CAN_FLAG_RQCP0
01030   *                  - CAN_FLAG_RQCP1
01031   *                  - CAN_FLAG_RQCP2
01032   *                  - CAN_FLAG_FMP1
01033   *                  - CAN_FLAG_FF1
01034   *                  - CAN_FLAG_FOV1
01035   *                  - CAN_FLAG_FMP0
01036   *                  - CAN_FLAG_FF0
01037   *                  - CAN_FLAG_FOV0
01038   *                  - CAN_FLAG_WKU
01039   *                  - CAN_FLAG_SLAK
01040   *                  - CAN_FLAG_LEC
01041   * @retval The new state of CAN_FLAG (SET or RESET).
01042   */
01043 FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG)
01044 {
01045   FlagStatus bitstatus = RESET;
01046
01047   /* Check the parameters */
01048   assert_param(IS_CAN_ALL_PERIPH(CANx));
01049   assert_param(IS_CAN_GET_FLAG(CAN_FLAG));
01050
01051
01052   if((CAN_FLAG & CAN_FLAGS_ESR) != (uint32_t)RESET)
01053   {
01054     /* Check the status of the specified CAN flag */
01055     if ((CANx->ESR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
01056     {
01057       /* CAN_FLAG is set */
01058       bitstatus = SET;
01059     }
01060     else
01061     {
01062       /* CAN_FLAG is reset */
01063       bitstatus = RESET;
01064     }
01065   }
01066   else if((CAN_FLAG & CAN_FLAGS_MSR) != (uint32_t)RESET)
01067   {
01068     /* Check the status of the specified CAN flag */
01069     if ((CANx->MSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
01070     {
01071       /* CAN_FLAG is set */
01072       bitstatus = SET;
01073     }
01074     else
01075     {
01076       /* CAN_FLAG is reset */
01077       bitstatus = RESET;
01078     }
01079   }
01080   else if((CAN_FLAG & CAN_FLAGS_TSR) != (uint32_t)RESET)
01081   {
01082     /* Check the status of the specified CAN flag */
01083     if ((CANx->TSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
01084     {
01085       /* CAN_FLAG is set */
01086       bitstatus = SET;
01087     }
01088     else
01089     {
01090       /* CAN_FLAG is reset */
01091       bitstatus = RESET;
01092     }
01093   }
01094   else if((CAN_FLAG & CAN_FLAGS_RF0R) != (uint32_t)RESET)
01095   {
01096     /* Check the status of the specified CAN flag */
01097     if ((CANx->RF0R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
01098     {
01099       /* CAN_FLAG is set */
01100       bitstatus = SET;
01101     }
01102     else
01103     {
01104       /* CAN_FLAG is reset */
01105       bitstatus = RESET;
01106     }
01107   }
01108   else /* If(CAN_FLAG & CAN_FLAGS_RF1R != (uint32_t)RESET) */
01109   {
01110     /* Check the status of the specified CAN flag */
01111     if ((uint32_t)(CANx->RF1R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
01112     {
01113       /* CAN_FLAG is set */
01114       bitstatus = SET;
01115     }
01116     else
01117     {
01118       /* CAN_FLAG is reset */
01119       bitstatus = RESET;
01120     }
01121   }
01122   /* Return the CAN_FLAG status */
01123   return  bitstatus;
01124 }
01125
01126 /**
01127   * @brief  Clears the CAN's pending flags.
01128   * @param  CANx:     where x can be 1 or 2 to to select the CAN peripheral.
01129   * @param  CAN_FLAG: specifies the flag to clear.
01130   *                   This parameter can be one of the following flags:
01131   *                    - CAN_FLAG_RQCP0
01132   *                    - CAN_FLAG_RQCP1
01133   *                    - CAN_FLAG_RQCP2
01134   *                    - CAN_FLAG_FF1
01135   *                    - CAN_FLAG_FOV1
01136   *                    - CAN_FLAG_FF0
01137   *                    - CAN_FLAG_FOV0
01138   *                    - CAN_FLAG_WKU
01139   *                    - CAN_FLAG_SLAK
01140   *                    - CAN_FLAG_LEC
01141   * @retval None.
01142   */
01143 void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG)
01144 {
01145   uint32_t flagtmp=0;
01146   /* Check the parameters */
01147   assert_param(IS_CAN_ALL_PERIPH(CANx));
01148   assert_param(IS_CAN_CLEAR_FLAG(CAN_FLAG));
01149
01150   if (CAN_FLAG == CAN_FLAG_LEC) /* ESR register */
01151   {
01152     /* Clear the selected CAN flags */
01153     CANx->ESR = (uint32_t)RESET;
01154   }
01155   else /* MSR or TSR or RF0R or RF1R */
01156   {
01157     flagtmp = CAN_FLAG & 0x000FFFFF;
01158
01159     if ((CAN_FLAG & CAN_FLAGS_RF0R)!=(uint32_t)RESET)
01160     {
01161       /* Receive Flags */
01162       CANx->RF0R = (uint32_t)(flagtmp);
01163     }
01164     else if ((CAN_FLAG & CAN_FLAGS_RF1R)!=(uint32_t)RESET)
01165     {
01166       /* Receive Flags */
01167       CANx->RF1R = (uint32_t)(flagtmp);
01168     }
01169     else if ((CAN_FLAG & CAN_FLAGS_TSR)!=(uint32_t)RESET)
01170     {
01171       /* Transmit Flags */
01172       CANx->TSR = (uint32_t)(flagtmp);
01173     }
01174     else /* If((CAN_FLAG & CAN_FLAGS_MSR)!=(uint32_t)RESET) */
01175     {
01176       /* Operating mode Flags */
01177       CANx->MSR = (uint32_t)(flagtmp);
01178     }
01179   }
01180 }
01181
01182 /**
01183   * @brief  Checks whether the specified CANx interrupt has occurred or not.
01184   * @param  CANx:    where x can be 1 or 2 to to select the CAN peripheral.
01185   * @param  CAN_IT:  specifies the CAN interrupt source to check.
01186   *                  This parameter can be one of the following flags:
01187   *                 -  CAN_IT_TME
01188   *                 -  CAN_IT_FMP0
01189   *                 -  CAN_IT_FF0
01190   *                 -  CAN_IT_FOV0
01191   *                 -  CAN_IT_FMP1
01192   *                 -  CAN_IT_FF1
01193   *                 -  CAN_IT_FOV1
01194   *                 -  CAN_IT_WKU
01195   *                 -  CAN_IT_SLK
01196   *                 -  CAN_IT_EWG
01197   *                 -  CAN_IT_EPV
01198   *                 -  CAN_IT_BOF
01199   *                 -  CAN_IT_LEC
01200   *                 -  CAN_IT_ERR
01201   * @retval The current state of CAN_IT (SET or RESET).
01202   */
01203 ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT)
01204 {
01205   ITStatus itstatus = RESET;
01206   /* Check the parameters */
01207   assert_param(IS_CAN_ALL_PERIPH(CANx));
01208   assert_param(IS_CAN_IT(CAN_IT));
01209
01210   /* check the enable interrupt bit */
01211  if((CANx->IER & CAN_IT) != RESET)
01212  {
01213    /* in case the Interrupt is enabled, .... */
01214     switch (CAN_IT)
01215     {
01216       case CAN_IT_TME:
01217                /* Check CAN_TSR_RQCPx bits */
01218                      itstatus = CheckITStatus(CANx->TSR, CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2);
01219               break;
01220       case CAN_IT_FMP0:
01221                /* Check CAN_RF0R_FMP0 bit */
01222                      itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FMP0);
01223               break;
01224       case CAN_IT_FF0:
01225                /* Check CAN_RF0R_FULL0 bit */
01226                itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FULL0);
01227               break;
01228       case CAN_IT_FOV0:
01229                /* Check CAN_RF0R_FOVR0 bit */
01230                itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FOVR0);
01231               break;
01232       case CAN_IT_FMP1:
01233                /* Check CAN_RF1R_FMP1 bit */
01234                itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FMP1);
01235               break;
01236       case CAN_IT_FF1:
01237                /* Check CAN_RF1R_FULL1 bit */
01238                      itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FULL1);
01239               break;
01240       case CAN_IT_FOV1:
01241                /* Check CAN_RF1R_FOVR1 bit */
01242                      itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FOVR1);
01243               break;
01244       case CAN_IT_WKU:
01245                /* Check CAN_MSR_WKUI bit */
01246                itstatus = CheckITStatus(CANx->MSR, CAN_MSR_WKUI);
01247               break;
01248       case CAN_IT_SLK:
01249                /* Check CAN_MSR_SLAKI bit */
01250                      itstatus = CheckITStatus(CANx->MSR, CAN_MSR_SLAKI);
01251               break;
01252       case CAN_IT_EWG:
01253                /* Check CAN_ESR_EWGF bit */
01254                      itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EWGF);
01255               break;
01256       case CAN_IT_EPV:
01257                /* Check CAN_ESR_EPVF bit */
01258                      itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EPVF);
01259               break;
01260       case CAN_IT_BOF:
01261                /* Check CAN_ESR_BOFF bit */
01262                      itstatus = CheckITStatus(CANx->ESR, CAN_ESR_BOFF);
01263               break;
01264       case CAN_IT_LEC:
01265                /* Check CAN_ESR_LEC bit */
01266                      itstatus = CheckITStatus(CANx->ESR, CAN_ESR_LEC);
01267               break;
01268       case CAN_IT_ERR:
01269                /* Check CAN_MSR_ERRI bit */
01270                itstatus = CheckITStatus(CANx->MSR, CAN_MSR_ERRI);
01271               break;
01272       default :
01273                /* in case of error, return RESET */
01274               itstatus = RESET;
01275               break;
01276     }
01277   }
01278   else
01279   {
01280    /* in case the Interrupt is not enabled, return RESET */
01281     itstatus  = RESET;
01282   }
01283
01284   /* Return the CAN_IT status */
01285   return  itstatus;
01286 }
01287
01288 /**
01289   * @brief  Clears the CANx's interrupt pending bits.
01290   * @param  CANx:    where x can be 1 or 2 to to select the CAN peripheral.
01291   * @param  CAN_IT: specifies the interrupt pending bit to clear.
01292   *                  -  CAN_IT_TME
01293   *                  -  CAN_IT_FF0
01294   *                  -  CAN_IT_FOV0
01295   *                  -  CAN_IT_FF1
01296   *                  -  CAN_IT_FOV1
01297   *                  -  CAN_IT_WKU
01298   *                  -  CAN_IT_SLK
01299   *                  -  CAN_IT_EWG
01300   *                  -  CAN_IT_EPV
01301   *                  -  CAN_IT_BOF
01302   *                  -  CAN_IT_LEC
01303   *                  -  CAN_IT_ERR
01304   * @retval None.
01305   */
01306 void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT)
01307 {
01308   /* Check the parameters */
01309   assert_param(IS_CAN_ALL_PERIPH(CANx));
01310   assert_param(IS_CAN_CLEAR_IT(CAN_IT));
01311
01312   switch (CAN_IT)
01313   {
01314       case CAN_IT_TME:
01315               /* Clear CAN_TSR_RQCPx (rc_w1)*/
01316               CANx->TSR = CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2;
01317               break;
01318       case CAN_IT_FF0:
01319               /* Clear CAN_RF0R_FULL0 (rc_w1)*/
01320               CANx->RF0R = CAN_RF0R_FULL0;
01321               break;
01322       case CAN_IT_FOV0:
01323               /* Clear CAN_RF0R_FOVR0 (rc_w1)*/
01324               CANx->RF0R = CAN_RF0R_FOVR0;
01325               break;
01326       case CAN_IT_FF1:
01327               /* Clear CAN_RF1R_FULL1 (rc_w1)*/
01328               CANx->RF1R = CAN_RF1R_FULL1;
01329               break;
01330       case CAN_IT_FOV1:
01331               /* Clear CAN_RF1R_FOVR1 (rc_w1)*/
01332               CANx->RF1R = CAN_RF1R_FOVR1;
01333               break;
01334       case CAN_IT_WKU:
01335               /* Clear CAN_MSR_WKUI (rc_w1)*/
01336               CANx->MSR = CAN_MSR_WKUI;
01337               break;
01338       case CAN_IT_SLK:
01339               /* Clear CAN_MSR_SLAKI (rc_w1)*/
01340               CANx->MSR = CAN_MSR_SLAKI;
01341               break;
01342       case CAN_IT_EWG:
01343               /* Clear CAN_MSR_ERRI (rc_w1) */
01344               CANx->MSR = CAN_MSR_ERRI;
01345               /* Note : the corresponding Flag is cleared by hardware depending
01346                         of the CAN Bus status*/
01347               break;
01348       case CAN_IT_EPV:
01349               /* Clear CAN_MSR_ERRI (rc_w1) */
01350               CANx->MSR = CAN_MSR_ERRI;
01351               /* Note : the corresponding Flag is cleared by hardware depending
01352                         of the CAN Bus status*/
01353               break;
01354       case CAN_IT_BOF:
01355               /* Clear CAN_MSR_ERRI (rc_w1) */
01356               CANx->MSR = CAN_MSR_ERRI;
01357               /* Note : the corresponding Flag is cleared by hardware depending
01358                         of the CAN Bus status*/
01359               break;
01360       case CAN_IT_LEC:
01361               /*  Clear LEC bits */
01362               CANx->ESR = RESET;
01363               /* Clear CAN_MSR_ERRI (rc_w1) */
01364               CANx->MSR = CAN_MSR_ERRI;
01365               break;
01366       case CAN_IT_ERR:
01367               /*Clear LEC bits */
01368               CANx->ESR = RESET;
01369               /* Clear CAN_MSR_ERRI (rc_w1) */
01370               CANx->MSR = CAN_MSR_ERRI;
01371               /* Note : BOFF, EPVF and EWGF Flags are cleared by hardware depending
01372                   of the CAN Bus status*/
01373               break;
01374       default :
01375               break;
01376    }
01377 }
01378
01379 /**
01380   * @brief  Checks whether the CAN interrupt has occurred or not.
01381   * @param  CAN_Reg: specifies the CAN interrupt register to check.
01382   * @param  It_Bit:  specifies the interrupt source bit to check.
01383   * @retval The new state of the CAN Interrupt (SET or RESET).
01384   */
01385 static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit)
01386 {
01387   ITStatus pendingbitstatus = RESET;
01388
01389   if ((CAN_Reg & It_Bit) != (uint32_t)RESET)
01390   {
01391     /* CAN_IT is set */
01392     pendingbitstatus = SET;
01393   }
01394   else
01395   {
01396     /* CAN_IT is reset */
01397     pendingbitstatus = RESET;
01398   }
01399   return pendingbitstatus;
01400 }
01401
01402
01403 /**
01404   * @}
01405   */
01406
01407 /**
01408   * @}
01409   */
01410
01411 /**
01412   * @}
01413   */
01414
01415 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_can.h Source File

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stm32f10x_can.h

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f10x_can.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    11-March-2011
00007   * @brief   This file contains all the functions prototypes for the CAN firmware
00008   *          library.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00013   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00014   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00015   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00016   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00017   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00018   *
00019   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00020   ******************************************************************************
00021   */
00022
00023 /* Define to prevent recursive inclusion -------------------------------------*/
00024 #ifndef __STM32F10x_CAN_H
00025 #define __STM32F10x_CAN_H
00026
00027 #ifdef __cplusplus
00028  extern "C" {
00029 #endif
00030
00031 /* Includes ------------------------------------------------------------------*/
00032 #include "stm32f10x.h"
00033
00034 /** @addtogroup STM32F10x_StdPeriph_Driver
00035   * @{
00036   */
00037
00038 /** @addtogroup CAN
00039   * @{
00040   */
00041
00042 /** @defgroup CAN_Exported_Types
00043   * @{
00044   */
00045
00046 #define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN1) || \
00047                                    ((PERIPH) == CAN2))
00048
00049 /**
00050   * @brief  CAN init structure definition
00051   */
00052
00053 typedef struct
00054 {
00055   uint16_t CAN_Prescaler;   /*!< Specifies the length of a time quantum.
00056                                  It ranges from 1 to 1024. */
00057
00058   uint8_t CAN_Mode;         /*!< Specifies the CAN operating mode.
00059                                  This parameter can be a value of
00060                                 @ref CAN_operating_mode */
00061
00062   uint8_t CAN_SJW;          /*!< Specifies the maximum number of time quanta
00063                                  the CAN hardware is allowed to lengthen or
00064                                  shorten a bit to perform resynchronization.
00065                                  This parameter can be a value of
00066                                  @ref CAN_synchronisation_jump_width */
00067
00068   uint8_t CAN_BS1;          /*!< Specifies the number of time quanta in Bit
00069                                  Segment 1. This parameter can be a value of
00070                                  @ref CAN_time_quantum_in_bit_segment_1 */
00071
00072   uint8_t CAN_BS2;          /*!< Specifies the number of time quanta in Bit
00073                                  Segment 2.
00074                                  This parameter can be a value of
00075                                  @ref CAN_time_quantum_in_bit_segment_2 */
00076
00077   FunctionalState CAN_TTCM; /*!< Enable or disable the time triggered
00078                                  communication mode. This parameter can be set
00079                                  either to ENABLE or DISABLE. */
00080
00081   FunctionalState CAN_ABOM;  /*!< Enable or disable the automatic bus-off
00082                                   management. This parameter can be set either
00083                                   to ENABLE or DISABLE. */
00084
00085   FunctionalState CAN_AWUM;  /*!< Enable or disable the automatic wake-up mode.
00086                                   This parameter can be set either to ENABLE or
00087                                   DISABLE. */
00088
00089   FunctionalState CAN_NART;  /*!< Enable or disable the no-automatic
00090                                   retransmission mode. This parameter can be
00091                                   set either to ENABLE or DISABLE. */
00092
00093   FunctionalState CAN_RFLM;  /*!< Enable or disable the Receive FIFO Locked mode.
00094                                   This parameter can be set either to ENABLE
00095                                   or DISABLE. */
00096
00097   FunctionalState CAN_TXFP;  /*!< Enable or disable the transmit FIFO priority.
00098                                   This parameter can be set either to ENABLE
00099                                   or DISABLE. */
00100 } CAN_InitTypeDef;
00101
00102 /**
00103   * @brief  CAN filter init structure definition
00104   */
00105
00106 typedef struct
00107 {
00108   uint16_t CAN_FilterIdHigh;         /*!< Specifies the filter identification number (MSBs for a 32-bit
00109                                               configuration, first one for a 16-bit configuration).
00110                                               This parameter can be a value between 0x0000 and 0xFFFF */
00111
00112   uint16_t CAN_FilterIdLow;          /*!< Specifies the filter identification number (LSBs for a 32-bit
00113                                               configuration, second one for a 16-bit configuration).
00114                                               This parameter can be a value between 0x0000 and 0xFFFF */
00115
00116   uint16_t CAN_FilterMaskIdHigh;     /*!< Specifies the filter mask number or identification number,
00117                                               according to the mode (MSBs for a 32-bit configuration,
00118                                               first one for a 16-bit configuration).
00119                                               This parameter can be a value between 0x0000 and 0xFFFF */
00120
00121   uint16_t CAN_FilterMaskIdLow;      /*!< Specifies the filter mask number or identification number,
00122                                               according to the mode (LSBs for a 32-bit configuration,
00123                                               second one for a 16-bit configuration).
00124                                               This parameter can be a value between 0x0000 and 0xFFFF */
00125
00126   uint16_t CAN_FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.
00127                                               This parameter can be a value of @ref CAN_filter_FIFO */
00128
00129   uint8_t CAN_FilterNumber;          /*!< Specifies the filter which will be initialized. It ranges from 0 to 13. */
00130
00131   uint8_t CAN_FilterMode;            /*!< Specifies the filter mode to be initialized.
00132                                               This parameter can be a value of @ref CAN_filter_mode */
00133
00134   uint8_t CAN_FilterScale;           /*!< Specifies the filter scale.
00135                                               This parameter can be a value of @ref CAN_filter_scale */
00136
00137   FunctionalState CAN_FilterActivation; /*!< Enable or disable the filter.
00138                                               This parameter can be set either to ENABLE or DISABLE. */
00139 } CAN_FilterInitTypeDef;
00140
00141 /**
00142   * @brief  CAN Tx message structure definition
00143   */
00144
00145 typedef struct
00146 {
00147   uint32_t StdId;  /*!< Specifies the standard identifier.
00148                         This parameter can be a value between 0 to 0x7FF. */
00149
00150   uint32_t ExtId;  /*!< Specifies the extended identifier.
00151                         This parameter can be a value between 0 to 0x1FFFFFFF. */
00152
00153   uint8_t IDE;     /*!< Specifies the type of identifier for the message that
00154                         will be transmitted. This parameter can be a value
00155                         of @ref CAN_identifier_type */
00156
00157   uint8_t RTR;     /*!< Specifies the type of frame for the message that will
00158                         be transmitted. This parameter can be a value of
00159                         @ref CAN_remote_transmission_request */
00160
00161   uint8_t DLC;     /*!< Specifies the length of the frame that will be
00162                         transmitted. This parameter can be a value between
00163                         0 to 8 */
00164
00165   uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0
00166                         to 0xFF. */
00167 } CanTxMsg;
00168
00169 /**
00170   * @brief  CAN Rx message structure definition
00171   */
00172
00173 typedef struct
00174 {
00175   uint32_t StdId;  /*!< Specifies the standard identifier.
00176                         This parameter can be a value between 0 to 0x7FF. */
00177
00178   uint32_t ExtId;  /*!< Specifies the extended identifier.
00179                         This parameter can be a value between 0 to 0x1FFFFFFF. */
00180
00181   uint8_t IDE;     /*!< Specifies the type of identifier for the message that
00182                         will be received. This parameter can be a value of
00183                         @ref CAN_identifier_type */
00184
00185   uint8_t RTR;     /*!< Specifies the type of frame for the received message.
00186                         This parameter can be a value of
00187                         @ref CAN_remote_transmission_request */
00188
00189   uint8_t DLC;     /*!< Specifies the length of the frame that will be received.
00190                         This parameter can be a value between 0 to 8 */
00191
00192   uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to
00193                         0xFF. */
00194
00195   uint8_t FMI;     /*!< Specifies the index of the filter the message stored in
00196                         the mailbox passes through. This parameter can be a
00197                         value between 0 to 0xFF */
00198 } CanRxMsg;
00199
00200 /**
00201   * @}
00202   */
00203
00204 /** @defgroup CAN_Exported_Constants
00205   * @{
00206   */
00207
00208 /** @defgroup CAN_sleep_constants
00209   * @{
00210   */
00211
00212 #define CAN_InitStatus_Failed              ((uint8_t)0x00) /*!< CAN initialization failed */
00213 #define CAN_InitStatus_Success             ((uint8_t)0x01) /*!< CAN initialization OK */
00214
00215 /**
00216   * @}
00217   */
00218
00219 /** @defgroup CAN_Mode
00220   * @{
00221   */
00222
00223 #define CAN_Mode_Normal             ((uint8_t)0x00)  /*!< normal mode */
00224 #define CAN_Mode_LoopBack           ((uint8_t)0x01)  /*!< loopback mode */
00225 #define CAN_Mode_Silent             ((uint8_t)0x02)  /*!< silent mode */
00226 #define CAN_Mode_Silent_LoopBack    ((uint8_t)0x03)  /*!< loopback combined with silent mode */
00227
00228 #define IS_CAN_MODE(MODE) (((MODE) == CAN_Mode_Normal) || \
00229                            ((MODE) == CAN_Mode_LoopBack)|| \
00230                            ((MODE) == CAN_Mode_Silent) || \
00231                            ((MODE) == CAN_Mode_Silent_LoopBack))
00232 /**
00233   * @}
00234   */
00235
00236
00237 /**
00238   * @defgroup CAN_Operating_Mode
00239   * @{
00240   */
00241 #define CAN_OperatingMode_Initialization  ((uint8_t)0x00) /*!< Initialization mode */
00242 #define CAN_OperatingMode_Normal          ((uint8_t)0x01) /*!< Normal mode */
00243 #define CAN_OperatingMode_Sleep           ((uint8_t)0x02) /*!< sleep mode */
00244
00245
00246 #define IS_CAN_OPERATING_MODE(MODE) (((MODE) == CAN_OperatingMode_Initialization) ||\
00247                                     ((MODE) == CAN_OperatingMode_Normal)|| \
00248                                                                                                                                                 ((MODE) == CAN_OperatingMode_Sleep))
00249 /**
00250   * @}
00251   */
00252
00253 /**
00254   * @defgroup CAN_Mode_Status
00255   * @{
00256   */
00257
00258 #define CAN_ModeStatus_Failed    ((uint8_t)0x00)                /*!< CAN entering the specific mode failed */
00259 #define CAN_ModeStatus_Success   ((uint8_t)!CAN_ModeStatus_Failed)   /*!< CAN entering the specific mode Succeed */
00260
00261
00262 /**
00263   * @}
00264   */
00265
00266 /** @defgroup CAN_synchronisation_jump_width
00267   * @{
00268   */
00269
00270 #define CAN_SJW_1tq                 ((uint8_t)0x00)  /*!< 1 time quantum */
00271 #define CAN_SJW_2tq                 ((uint8_t)0x01)  /*!< 2 time quantum */
00272 #define CAN_SJW_3tq                 ((uint8_t)0x02)  /*!< 3 time quantum */
00273 #define CAN_SJW_4tq                 ((uint8_t)0x03)  /*!< 4 time quantum */
00274
00275 #define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1tq) || ((SJW) == CAN_SJW_2tq)|| \
00276                          ((SJW) == CAN_SJW_3tq) || ((SJW) == CAN_SJW_4tq))
00277 /**
00278   * @}
00279   */
00280
00281 /** @defgroup CAN_time_quantum_in_bit_segment_1
00282   * @{
00283   */
00284
00285 #define CAN_BS1_1tq                 ((uint8_t)0x00)  /*!< 1 time quantum */
00286 #define CAN_BS1_2tq                 ((uint8_t)0x01)  /*!< 2 time quantum */
00287 #define CAN_BS1_3tq                 ((uint8_t)0x02)  /*!< 3 time quantum */
00288 #define CAN_BS1_4tq                 ((uint8_t)0x03)  /*!< 4 time quantum */
00289 #define CAN_BS1_5tq                 ((uint8_t)0x04)  /*!< 5 time quantum */
00290 #define CAN_BS1_6tq                 ((uint8_t)0x05)  /*!< 6 time quantum */
00291 #define CAN_BS1_7tq                 ((uint8_t)0x06)  /*!< 7 time quantum */
00292 #define CAN_BS1_8tq                 ((uint8_t)0x07)  /*!< 8 time quantum */
00293 #define CAN_BS1_9tq                 ((uint8_t)0x08)  /*!< 9 time quantum */
00294 #define CAN_BS1_10tq                ((uint8_t)0x09)  /*!< 10 time quantum */
00295 #define CAN_BS1_11tq                ((uint8_t)0x0A)  /*!< 11 time quantum */
00296 #define CAN_BS1_12tq                ((uint8_t)0x0B)  /*!< 12 time quantum */
00297 #define CAN_BS1_13tq                ((uint8_t)0x0C)  /*!< 13 time quantum */
00298 #define CAN_BS1_14tq                ((uint8_t)0x0D)  /*!< 14 time quantum */
00299 #define CAN_BS1_15tq                ((uint8_t)0x0E)  /*!< 15 time quantum */
00300 #define CAN_BS1_16tq                ((uint8_t)0x0F)  /*!< 16 time quantum */
00301
00302 #define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16tq)
00303 /**
00304   * @}
00305   */
00306
00307 /** @defgroup CAN_time_quantum_in_bit_segment_2
00308   * @{
00309   */
00310
00311 #define CAN_BS2_1tq                 ((uint8_t)0x00)  /*!< 1 time quantum */
00312 #define CAN_BS2_2tq                 ((uint8_t)0x01)  /*!< 2 time quantum */
00313 #define CAN_BS2_3tq                 ((uint8_t)0x02)  /*!< 3 time quantum */
00314 #define CAN_BS2_4tq                 ((uint8_t)0x03)  /*!< 4 time quantum */
00315 #define CAN_BS2_5tq                 ((uint8_t)0x04)  /*!< 5 time quantum */
00316 #define CAN_BS2_6tq                 ((uint8_t)0x05)  /*!< 6 time quantum */
00317 #define CAN_BS2_7tq                 ((uint8_t)0x06)  /*!< 7 time quantum */
00318 #define CAN_BS2_8tq                 ((uint8_t)0x07)  /*!< 8 time quantum */
00319
00320 #define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8tq)
00321
00322 /**
00323   * @}
00324   */
00325
00326 /** @defgroup CAN_clock_prescaler
00327   * @{
00328   */
00329
00330 #define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))
00331
00332 /**
00333   * @}
00334   */
00335
00336 /** @defgroup CAN_filter_number
00337   * @{
00338   */
00339 #ifndef STM32F10X_CL
00340   #define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 13)
00341 #else
00342   #define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27)
00343 #endif /* STM32F10X_CL */
00344 /**
00345   * @}
00346   */
00347
00348 /** @defgroup CAN_filter_mode
00349   * @{
00350   */
00351
00352 #define CAN_FilterMode_IdMask       ((uint8_t)0x00)  /*!< identifier/mask mode */
00353 #define CAN_FilterMode_IdList       ((uint8_t)0x01)  /*!< identifier list mode */
00354
00355 #define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FilterMode_IdMask) || \
00356                                   ((MODE) == CAN_FilterMode_IdList))
00357 /**
00358   * @}
00359   */
00360
00361 /** @defgroup CAN_filter_scale
00362   * @{
00363   */
00364
00365 #define CAN_FilterScale_16bit       ((uint8_t)0x00) /*!< Two 16-bit filters */
00366 #define CAN_FilterScale_32bit       ((uint8_t)0x01) /*!< One 32-bit filter */
00367
00368 #define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FilterScale_16bit) || \
00369                                     ((SCALE) == CAN_FilterScale_32bit))
00370
00371 /**
00372   * @}
00373   */
00374
00375 /** @defgroup CAN_filter_FIFO
00376   * @{
00377   */
00378
00379 #define CAN_Filter_FIFO0             ((uint8_t)0x00)  /*!< Filter FIFO 0 assignment for filter x */
00380 #define CAN_Filter_FIFO1             ((uint8_t)0x01)  /*!< Filter FIFO 1 assignment for filter x */
00381 #define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FilterFIFO0) || \
00382                                   ((FIFO) == CAN_FilterFIFO1))
00383 /**
00384   * @}
00385   */
00386
00387 /** @defgroup Start_bank_filter_for_slave_CAN
00388   * @{
00389   */
00390 #define IS_CAN_BANKNUMBER(BANKNUMBER) (((BANKNUMBER) >= 1) && ((BANKNUMBER) <= 27))
00391 /**
00392   * @}
00393   */
00394
00395 /** @defgroup CAN_Tx
00396   * @{
00397   */
00398
00399 #define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
00400 #define IS_CAN_STDID(STDID)   ((STDID) <= ((uint32_t)0x7FF))
00401 #define IS_CAN_EXTID(EXTID)   ((EXTID) <= ((uint32_t)0x1FFFFFFF))
00402 #define IS_CAN_DLC(DLC)       ((DLC) <= ((uint8_t)0x08))
00403
00404 /**
00405   * @}
00406   */
00407
00408 /** @defgroup CAN_identifier_type
00409   * @{
00410   */
00411
00412 #define CAN_Id_Standard             ((uint32_t)0x00000000)  /*!< Standard Id */
00413 #define CAN_Id_Extended             ((uint32_t)0x00000004)  /*!< Extended Id */
00414 #define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_Id_Standard) || \
00415                                ((IDTYPE) == CAN_Id_Extended))
00416 /**
00417   * @}
00418   */
00419
00420 /** @defgroup CAN_remote_transmission_request
00421   * @{
00422   */
00423
00424 #define CAN_RTR_Data                ((uint32_t)0x00000000)  /*!< Data frame */
00425 #define CAN_RTR_Remote              ((uint32_t)0x00000002)  /*!< Remote frame */
00426 #define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_Data) || ((RTR) == CAN_RTR_Remote))
00427
00428 /**
00429   * @}
00430   */
00431
00432 /** @defgroup CAN_transmit_constants
00433   * @{
00434   */
00435
00436 #define CAN_TxStatus_Failed         ((uint8_t)0x00)/*!< CAN transmission failed */
00437 #define CAN_TxStatus_Ok             ((uint8_t)0x01) /*!< CAN transmission succeeded */
00438 #define CAN_TxStatus_Pending        ((uint8_t)0x02) /*!< CAN transmission pending */
00439 #define CAN_TxStatus_NoMailBox      ((uint8_t)0x04) /*!< CAN cell did not provide an empty mailbox */
00440
00441 /**
00442   * @}
00443   */
00444
00445 /** @defgroup CAN_receive_FIFO_number_constants
00446   * @{
00447   */
00448
00449 #define CAN_FIFO0                 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */
00450 #define CAN_FIFO1                 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */
00451
00452 #define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
00453
00454 /**
00455   * @}
00456   */
00457
00458 /** @defgroup CAN_sleep_constants
00459   * @{
00460   */
00461
00462 #define CAN_Sleep_Failed     ((uint8_t)0x00) /*!< CAN did not enter the sleep mode */
00463 #define CAN_Sleep_Ok         ((uint8_t)0x01) /*!< CAN entered the sleep mode */
00464
00465 /**
00466   * @}
00467   */
00468
00469 /** @defgroup CAN_wake_up_constants
00470   * @{
00471   */
00472
00473 #define CAN_WakeUp_Failed        ((uint8_t)0x00) /*!< CAN did not leave the sleep mode */
00474 #define CAN_WakeUp_Ok            ((uint8_t)0x01) /*!< CAN leaved the sleep mode */
00475
00476 /**
00477   * @}
00478   */
00479
00480 /**
00481   * @defgroup   CAN_Error_Code_constants
00482   * @{
00483   */
00484
00485 #define CAN_ErrorCode_NoErr           ((uint8_t)0x00) /*!< No Error */
00486 #define CAN_ErrorCode_StuffErr        ((uint8_t)0x10) /*!< Stuff Error */
00487 #define CAN_ErrorCode_FormErr         ((uint8_t)0x20) /*!< Form Error */
00488 #define CAN_ErrorCode_ACKErr          ((uint8_t)0x30) /*!< Acknowledgment Error */
00489 #define CAN_ErrorCode_BitRecessiveErr ((uint8_t)0x40) /*!< Bit Recessive Error */
00490 #define CAN_ErrorCode_BitDominantErr  ((uint8_t)0x50) /*!< Bit Dominant Error */
00491 #define CAN_ErrorCode_CRCErr          ((uint8_t)0x60) /*!< CRC Error  */
00492 #define CAN_ErrorCode_SoftwareSetErr  ((uint8_t)0x70) /*!< Software Set Error */
00493
00494
00495 /**
00496   * @}
00497   */
00498
00499 /** @defgroup CAN_flags
00500   * @{
00501   */
00502 /* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
00503    and CAN_ClearFlag() functions. */
00504 /* If the flag is 0x1XXXXXXX, it means that it can only be used with CAN_GetFlagStatus() function.  */
00505
00506 /* Transmit Flags */
00507 #define CAN_FLAG_RQCP0             ((uint32_t)0x38000001) /*!< Request MailBox0 Flag */
00508 #define CAN_FLAG_RQCP1             ((uint32_t)0x38000100) /*!< Request MailBox1 Flag */
00509 #define CAN_FLAG_RQCP2             ((uint32_t)0x38010000) /*!< Request MailBox2 Flag */
00510
00511 /* Receive Flags */
00512 #define CAN_FLAG_FMP0              ((uint32_t)0x12000003) /*!< FIFO 0 Message Pending Flag */
00513 #define CAN_FLAG_FF0               ((uint32_t)0x32000008) /*!< FIFO 0 Full Flag            */
00514 #define CAN_FLAG_FOV0              ((uint32_t)0x32000010) /*!< FIFO 0 Overrun Flag         */
00515 #define CAN_FLAG_FMP1              ((uint32_t)0x14000003) /*!< FIFO 1 Message Pending Flag */
00516 #define CAN_FLAG_FF1               ((uint32_t)0x34000008) /*!< FIFO 1 Full Flag            */
00517 #define CAN_FLAG_FOV1              ((uint32_t)0x34000010) /*!< FIFO 1 Overrun Flag         */
00518
00519 /* Operating Mode Flags */
00520 #define CAN_FLAG_WKU               ((uint32_t)0x31000008) /*!< Wake up Flag */
00521 #define CAN_FLAG_SLAK              ((uint32_t)0x31000012) /*!< Sleep acknowledge Flag */
00522 /* Note: When SLAK intterupt is disabled (SLKIE=0), no polling on SLAKI is possible.
00523          In this case the SLAK bit can be polled.*/
00524
00525 /* Error Flags */
00526 #define CAN_FLAG_EWG               ((uint32_t)0x10F00001) /*!< Error Warning Flag   */
00527 #define CAN_FLAG_EPV               ((uint32_t)0x10F00002) /*!< Error Passive Flag   */
00528 #define CAN_FLAG_BOF               ((uint32_t)0x10F00004) /*!< Bus-Off Flag         */
00529 #define CAN_FLAG_LEC               ((uint32_t)0x30F00070) /*!< Last error code Flag */
00530
00531 #define IS_CAN_GET_FLAG(FLAG) (((FLAG) == CAN_FLAG_LEC)  || ((FLAG) == CAN_FLAG_BOF)   || \
00532                                ((FLAG) == CAN_FLAG_EPV)  || ((FLAG) == CAN_FLAG_EWG)   || \
00533                                ((FLAG) == CAN_FLAG_WKU)  || ((FLAG) == CAN_FLAG_FOV0)  || \
00534                                ((FLAG) == CAN_FLAG_FF0)  || ((FLAG) == CAN_FLAG_FMP0)  || \
00535                                ((FLAG) == CAN_FLAG_FOV1) || ((FLAG) == CAN_FLAG_FF1)   || \
00536                                ((FLAG) == CAN_FLAG_FMP1) || ((FLAG) == CAN_FLAG_RQCP2) || \
00537                                ((FLAG) == CAN_FLAG_RQCP1)|| ((FLAG) == CAN_FLAG_RQCP0) || \
00538                                ((FLAG) == CAN_FLAG_SLAK ))
00539
00540 #define IS_CAN_CLEAR_FLAG(FLAG)(((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_RQCP2) || \
00541                                 ((FLAG) == CAN_FLAG_RQCP1)  || ((FLAG) == CAN_FLAG_RQCP0) || \
00542                                 ((FLAG) == CAN_FLAG_FF0)  || ((FLAG) == CAN_FLAG_FOV0) ||\
00543                                 ((FLAG) == CAN_FLAG_FF1) || ((FLAG) == CAN_FLAG_FOV1) || \
00544                                 ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_SLAK))
00545 /**
00546   * @}
00547   */
00548
00549
00550 /** @defgroup CAN_interrupts
00551   * @{
00552   */
00553
00554
00555
00556 #define CAN_IT_TME                  ((uint32_t)0x00000001) /*!< Transmit mailbox empty Interrupt*/
00557
00558 /* Receive Interrupts */
00559 #define CAN_IT_FMP0                 ((uint32_t)0x00000002) /*!< FIFO 0 message pending Interrupt*/
00560 #define CAN_IT_FF0                  ((uint32_t)0x00000004) /*!< FIFO 0 full Interrupt*/
00561 #define CAN_IT_FOV0                 ((uint32_t)0x00000008) /*!< FIFO 0 overrun Interrupt*/
00562 #define CAN_IT_FMP1                 ((uint32_t)0x00000010) /*!< FIFO 1 message pending Interrupt*/
00563 #define CAN_IT_FF1                  ((uint32_t)0x00000020) /*!< FIFO 1 full Interrupt*/
00564 #define CAN_IT_FOV1                 ((uint32_t)0x00000040) /*!< FIFO 1 overrun Interrupt*/
00565
00566 /* Operating Mode Interrupts */
00567 #define CAN_IT_WKU                  ((uint32_t)0x00010000) /*!< Wake-up Interrupt*/
00568 #define CAN_IT_SLK                  ((uint32_t)0x00020000) /*!< Sleep acknowledge Interrupt*/
00569
00570 /* Error Interrupts */
00571 #define CAN_IT_EWG                  ((uint32_t)0x00000100) /*!< Error warning Interrupt*/
00572 #define CAN_IT_EPV                  ((uint32_t)0x00000200) /*!< Error passive Interrupt*/
00573 #define CAN_IT_BOF                  ((uint32_t)0x00000400) /*!< Bus-off Interrupt*/
00574 #define CAN_IT_LEC                  ((uint32_t)0x00000800) /*!< Last error code Interrupt*/
00575 #define CAN_IT_ERR                  ((uint32_t)0x00008000) /*!< Error Interrupt*/
00576
00577 /* Flags named as Interrupts : kept only for FW compatibility */
00578 #define CAN_IT_RQCP0   CAN_IT_TME
00579 #define CAN_IT_RQCP1   CAN_IT_TME
00580 #define CAN_IT_RQCP2   CAN_IT_TME
00581
00582
00583 #define IS_CAN_IT(IT)        (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0)  ||\
00584                              ((IT) == CAN_IT_FF0)  || ((IT) == CAN_IT_FOV0)  ||\
00585                              ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1)   ||\
00586                              ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG)   ||\
00587                              ((IT) == CAN_IT_EPV)  || ((IT) == CAN_IT_BOF)   ||\
00588                              ((IT) == CAN_IT_LEC)  || ((IT) == CAN_IT_ERR)   ||\
00589                              ((IT) == CAN_IT_WKU)  || ((IT) == CAN_IT_SLK))
00590
00591 #define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0)    ||\
00592                              ((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1)    ||\
00593                              ((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG)    ||\
00594                              ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF)    ||\
00595                              ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR)    ||\
00596                              ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
00597
00598 /**
00599   * @}
00600   */
00601
00602 /** @defgroup CAN_Legacy
00603   * @{
00604   */
00605 #define CANINITFAILED               CAN_InitStatus_Failed
00606 #define CANINITOK                   CAN_InitStatus_Success
00607 #define CAN_FilterFIFO0             CAN_Filter_FIFO0
00608 #define CAN_FilterFIFO1             CAN_Filter_FIFO1
00609 #define CAN_ID_STD                  CAN_Id_Standard
00610 #define CAN_ID_EXT                  CAN_Id_Extended
00611 #define CAN_RTR_DATA                CAN_RTR_Data
00612 #define CAN_RTR_REMOTE              CAN_RTR_Remote
00613 #define CANTXFAILE                  CAN_TxStatus_Failed
00614 #define CANTXOK                     CAN_TxStatus_Ok
00615 #define CANTXPENDING                CAN_TxStatus_Pending
00616 #define CAN_NO_MB                   CAN_TxStatus_NoMailBox
00617 #define CANSLEEPFAILED              CAN_Sleep_Failed
00618 #define CANSLEEPOK                  CAN_Sleep_Ok
00619 #define CANWAKEUPFAILED             CAN_WakeUp_Failed
00620 #define CANWAKEUPOK                 CAN_WakeUp_Ok
00621
00622 /**
00623   * @}
00624   */
00625
00626 /**
00627   * @}
00628   */
00629
00630 /** @defgroup CAN_Exported_Macros
00631   * @{
00632   */
00633
00634 /**
00635   * @}
00636   */
00637
00638 /** @defgroup CAN_Exported_Functions
00639   * @{
00640   */
00641 /*  Function used to set the CAN configuration to the default reset state *****/
00642 void CAN_DeInit(CAN_TypeDef* CANx);
00643
00644 /* Initialization and Configuration functions *********************************/
00645 uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct);
00646 void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct);
00647 void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct);
00648 void CAN_SlaveStartBank(uint8_t CAN_BankNumber);
00649 void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState);
00650 void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState);
00651
00652 /* Transmit functions *********************************************************/
00653 uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage);
00654 uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox);
00655 void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox);
00656
00657 /* Receive functions **********************************************************/
00658 void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage);
00659 void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber);
00660 uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber);
00661
00662
00663 /* Operation modes functions **************************************************/
00664 uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode);
00665 uint8_t CAN_Sleep(CAN_TypeDef* CANx);
00666 uint8_t CAN_WakeUp(CAN_TypeDef* CANx);
00667
00668 /* Error management functions *************************************************/
00669 uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx);
00670 uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx);
00671 uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx);
00672
00673 /* Interrupts and flags management functions **********************************/
00674 void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState);
00675 FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
00676 void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
00677 ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT);
00678 void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT);
00679
00680 #ifdef __cplusplus
00681 }
00682 #endif
00683
00684 #endif /* __STM32F10x_CAN_H */
00685 /**
00686   * @}
00687   */
00688
00689 /**
00690   * @}
00691   */
00692
00693 /**
00694   * @}
00695   */
00696
00697 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_cec.c Source File

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  • src

stm32f10x_cec.c

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f10x_cec.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    11-March-2011
00007   * @brief   This file provides all the CEC firmware functions.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x_cec.h"
00024 #include "stm32f10x_rcc.h"
00025
00026 /** @addtogroup STM32F10x_StdPeriph_Driver
00027   * @{
00028   */
00029
00030 /** @defgroup CEC
00031   * @brief CEC driver modules
00032   * @{
00033   */
00034
00035 /** @defgroup CEC_Private_TypesDefinitions
00036   * @{
00037   */
00038
00039 /**
00040   * @}
00041   */
00042
00043
00044 /** @defgroup CEC_Private_Defines
00045   * @{
00046   */
00047
00048 /* ------------ CEC registers bit address in the alias region ----------- */
00049 #define CEC_OFFSET                (CEC_BASE - PERIPH_BASE)
00050
00051 /* --- CFGR Register ---*/
00052
00053 /* Alias word address of PE bit */
00054 #define CFGR_OFFSET                 (CEC_OFFSET + 0x00)
00055 #define PE_BitNumber                0x00
00056 #define CFGR_PE_BB                  (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (PE_BitNumber * 4))
00057
00058 /* Alias word address of IE bit */
00059 #define IE_BitNumber                0x01
00060 #define CFGR_IE_BB                  (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (IE_BitNumber * 4))
00061
00062 /* --- CSR Register ---*/
00063
00064 /* Alias word address of TSOM bit */
00065 #define CSR_OFFSET                  (CEC_OFFSET + 0x10)
00066 #define TSOM_BitNumber              0x00
00067 #define CSR_TSOM_BB                 (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TSOM_BitNumber * 4))
00068
00069 /* Alias word address of TEOM bit */
00070 #define TEOM_BitNumber              0x01
00071 #define CSR_TEOM_BB                 (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEOM_BitNumber * 4))
00072
00073 #define CFGR_CLEAR_Mask            (uint8_t)(0xF3)        /* CFGR register Mask */
00074 #define FLAG_Mask                  ((uint32_t)0x00FFFFFF) /* CEC FLAG mask */
00075
00076 /**
00077   * @}
00078   */
00079
00080
00081 /** @defgroup CEC_Private_Macros
00082   * @{
00083   */
00084
00085 /**
00086   * @}
00087   */
00088
00089
00090 /** @defgroup CEC_Private_Variables
00091   * @{
00092   */
00093
00094 /**
00095   * @}
00096   */
00097
00098
00099 /** @defgroup CEC_Private_FunctionPrototypes
00100   * @{
00101   */
00102
00103 /**
00104   * @}
00105   */
00106
00107
00108 /** @defgroup CEC_Private_Functions
00109   * @{
00110   */
00111
00112 /**
00113   * @brief  Deinitializes the CEC peripheral registers to their default reset
00114   *         values.
00115   * @param  None
00116   * @retval None
00117   */
00118 void CEC_DeInit(void)
00119 {
00120   /* Enable CEC reset state */
00121   RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, ENABLE);
00122   /* Release CEC from reset state */
00123   RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, DISABLE);
00124 }
00125
00126
00127 /**
00128   * @brief  Initializes the CEC peripheral according to the specified
00129   *         parameters in the CEC_InitStruct.
00130   * @param  CEC_InitStruct: pointer to an CEC_InitTypeDef structure that
00131   *         contains the configuration information for the specified
00132   *         CEC peripheral.
00133   * @retval None
00134   */
00135 void CEC_Init(CEC_InitTypeDef* CEC_InitStruct)
00136 {
00137   uint16_t tmpreg = 0;
00138
00139   /* Check the parameters */
00140   assert_param(IS_CEC_BIT_TIMING_ERROR_MODE(CEC_InitStruct->CEC_BitTimingMode));
00141   assert_param(IS_CEC_BIT_PERIOD_ERROR_MODE(CEC_InitStruct->CEC_BitPeriodMode));
00142
00143   /*---------------------------- CEC CFGR Configuration -----------------*/
00144   /* Get the CEC CFGR value */
00145   tmpreg = CEC->CFGR;
00146
00147   /* Clear BTEM and BPEM bits */
00148   tmpreg &= CFGR_CLEAR_Mask;
00149
00150   /* Configure CEC: Bit Timing Error and Bit Period Error */
00151   tmpreg |= (uint16_t)(CEC_InitStruct->CEC_BitTimingMode | CEC_InitStruct->CEC_BitPeriodMode);
00152
00153   /* Write to CEC CFGR  register*/
00154   CEC->CFGR = tmpreg;
00155
00156 }
00157
00158 /**
00159   * @brief  Enables or disables the specified CEC peripheral.
00160   * @param  NewState: new state of the CEC peripheral.
00161   *     This parameter can be: ENABLE or DISABLE.
00162   * @retval None
00163   */
00164 void CEC_Cmd(FunctionalState NewState)
00165 {
00166   /* Check the parameters */
00167   assert_param(IS_FUNCTIONAL_STATE(NewState));
00168
00169   *(__IO uint32_t *) CFGR_PE_BB = (uint32_t)NewState;
00170
00171   if(NewState == DISABLE)
00172   {
00173     /* Wait until the PE bit is cleared by hardware (Idle Line detected) */
00174     while((CEC->CFGR & CEC_CFGR_PE) != (uint32_t)RESET)
00175     {
00176     }
00177   }
00178 }
00179
00180 /**
00181   * @brief  Enables or disables the CEC interrupt.
00182   * @param  NewState: new state of the CEC interrupt.
00183   *   This parameter can be: ENABLE or DISABLE.
00184   * @retval None
00185   */
00186 void CEC_ITConfig(FunctionalState NewState)
00187 {
00188   /* Check the parameters */
00189   assert_param(IS_FUNCTIONAL_STATE(NewState));
00190
00191   *(__IO uint32_t *) CFGR_IE_BB = (uint32_t)NewState;
00192 }
00193
00194 /**
00195   * @brief  Defines the Own Address of the CEC device.
00196   * @param  CEC_OwnAddress: The CEC own address
00197   * @retval None
00198   */
00199 void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress)
00200 {
00201   /* Check the parameters */
00202   assert_param(IS_CEC_ADDRESS(CEC_OwnAddress));
00203
00204   /* Set the CEC own address */
00205   CEC->OAR = CEC_OwnAddress;
00206 }
00207
00208 /**
00209   * @brief  Sets the CEC prescaler value.
00210   * @param  CEC_Prescaler: CEC prescaler new value
00211   * @retval None
00212   */
00213 void CEC_SetPrescaler(uint16_t CEC_Prescaler)
00214 {
00215   /* Check the parameters */
00216   assert_param(IS_CEC_PRESCALER(CEC_Prescaler));
00217
00218   /* Set the  Prescaler value*/
00219   CEC->PRES = CEC_Prescaler;
00220 }
00221
00222 /**
00223   * @brief  Transmits single data through the CEC peripheral.
00224   * @param  Data: the data to transmit.
00225   * @retval None
00226   */
00227 void CEC_SendDataByte(uint8_t Data)
00228 {
00229   /* Transmit Data */
00230   CEC->TXD = Data ;
00231 }
00232
00233
00234 /**
00235   * @brief  Returns the most recent received data by the CEC peripheral.
00236   * @param  None
00237   * @retval The received data.
00238   */
00239 uint8_t CEC_ReceiveDataByte(void)
00240 {
00241   /* Receive Data */
00242   return (uint8_t)(CEC->RXD);
00243 }
00244
00245 /**
00246   * @brief  Starts a new message.
00247   * @param  None
00248   * @retval None
00249   */
00250 void CEC_StartOfMessage(void)
00251 {
00252   /* Starts of new message */
00253   *(__IO uint32_t *) CSR_TSOM_BB = (uint32_t)0x1;
00254 }
00255
00256 /**
00257   * @brief  Transmits message with or without an EOM bit.
00258   * @param  NewState: new state of the CEC Tx End Of Message.
00259   *     This parameter can be: ENABLE or DISABLE.
00260   * @retval None
00261   */
00262 void CEC_EndOfMessageCmd(FunctionalState NewState)
00263 {
00264   /* Check the parameters */
00265   assert_param(IS_FUNCTIONAL_STATE(NewState));
00266
00267   /* The data byte will be transmitted with or without an EOM bit*/
00268   *(__IO uint32_t *) CSR_TEOM_BB = (uint32_t)NewState;
00269 }
00270
00271 /**
00272   * @brief  Gets the CEC flag status
00273   * @param  CEC_FLAG: specifies the CEC flag to check.
00274   *   This parameter can be one of the following values:
00275   *     @arg CEC_FLAG_BTE: Bit Timing Error
00276   *     @arg CEC_FLAG_BPE: Bit Period Error
00277   *     @arg CEC_FLAG_RBTFE: Rx Block Transfer Finished Error
00278   *     @arg CEC_FLAG_SBE: Start Bit Error
00279   *     @arg CEC_FLAG_ACKE: Block Acknowledge Error
00280   *     @arg CEC_FLAG_LINE: Line Error
00281   *     @arg CEC_FLAG_TBTFE: Tx Block Transfer Finished Error
00282   *     @arg CEC_FLAG_TEOM: Tx End Of Message
00283   *     @arg CEC_FLAG_TERR: Tx Error
00284   *     @arg CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished
00285   *     @arg CEC_FLAG_RSOM: Rx Start Of Message
00286   *     @arg CEC_FLAG_REOM: Rx End Of Message
00287   *     @arg CEC_FLAG_RERR: Rx Error
00288   *     @arg CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished
00289   * @retval The new state of CEC_FLAG (SET or RESET)
00290   */
00291 FlagStatus CEC_GetFlagStatus(uint32_t CEC_FLAG)
00292 {
00293   FlagStatus bitstatus = RESET;
00294   uint32_t cecreg = 0, cecbase = 0;
00295
00296   /* Check the parameters */
00297   assert_param(IS_CEC_GET_FLAG(CEC_FLAG));
00298
00299   /* Get the CEC peripheral base address */
00300   cecbase = (uint32_t)(CEC_BASE);
00301
00302   /* Read flag register index */
00303   cecreg = CEC_FLAG >> 28;
00304
00305   /* Get bit[23:0] of the flag */
00306   CEC_FLAG &= FLAG_Mask;
00307
00308   if(cecreg != 0)
00309   {
00310     /* Flag in CEC ESR Register */
00311     CEC_FLAG = (uint32_t)(CEC_FLAG >> 16);
00312
00313     /* Get the CEC ESR register address */
00314     cecbase += 0xC;
00315   }
00316   else
00317   {
00318     /* Get the CEC CSR register address */
00319     cecbase += 0x10;
00320   }
00321
00322   if(((*(__IO uint32_t *)cecbase) & CEC_FLAG) != (uint32_t)RESET)
00323   {
00324     /* CEC_FLAG is set */
00325     bitstatus = SET;
00326   }
00327   else
00328   {
00329     /* CEC_FLAG is reset */
00330     bitstatus = RESET;
00331   }
00332
00333   /* Return the CEC_FLAG status */
00334   return  bitstatus;
00335 }
00336
00337 /**
00338   * @brief  Clears the CEC's pending flags.
00339   * @param  CEC_FLAG: specifies the flag to clear.
00340   *   This parameter can be any combination of the following values:
00341   *     @arg CEC_FLAG_TERR: Tx Error
00342   *     @arg CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished
00343   *     @arg CEC_FLAG_RSOM: Rx Start Of Message
00344   *     @arg CEC_FLAG_REOM: Rx End Of Message
00345   *     @arg CEC_FLAG_RERR: Rx Error
00346   *     @arg CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished
00347   * @retval None
00348   */
00349 void CEC_ClearFlag(uint32_t CEC_FLAG)
00350 {
00351   uint32_t tmp = 0x0;
00352
00353   /* Check the parameters */
00354   assert_param(IS_CEC_CLEAR_FLAG(CEC_FLAG));
00355
00356   tmp = CEC->CSR & 0x2;
00357
00358   /* Clear the selected CEC flags */
00359   CEC->CSR &= (uint32_t)(((~(uint32_t)CEC_FLAG) & 0xFFFFFFFC) | tmp);
00360 }
00361
00362 /**
00363   * @brief  Checks whether the specified CEC interrupt has occurred or not.
00364   * @param  CEC_IT: specifies the CEC interrupt source to check.
00365   *   This parameter can be one of the following values:
00366   *     @arg CEC_IT_TERR: Tx Error
00367   *     @arg CEC_IT_TBTF: Tx Block Transfer Finished
00368   *     @arg CEC_IT_RERR: Rx Error
00369   *     @arg CEC_IT_RBTF: Rx Block Transfer Finished
00370   * @retval The new state of CEC_IT (SET or RESET).
00371   */
00372 ITStatus CEC_GetITStatus(uint8_t CEC_IT)
00373 {
00374   ITStatus bitstatus = RESET;
00375   uint32_t enablestatus = 0;
00376
00377   /* Check the parameters */
00378    assert_param(IS_CEC_GET_IT(CEC_IT));
00379
00380   /* Get the CEC IT enable bit status */
00381   enablestatus = (CEC->CFGR & (uint8_t)CEC_CFGR_IE) ;
00382
00383   /* Check the status of the specified CEC interrupt */
00384   if (((CEC->CSR & CEC_IT) != (uint32_t)RESET) && enablestatus)
00385   {
00386     /* CEC_IT is set */
00387     bitstatus = SET;
00388   }
00389   else
00390   {
00391     /* CEC_IT is reset */
00392     bitstatus = RESET;
00393   }
00394   /* Return the CEC_IT status */
00395   return  bitstatus;
00396 }
00397
00398 /**
00399   * @brief  Clears the CEC's interrupt pending bits.
00400   * @param  CEC_IT: specifies the CEC interrupt pending bit to clear.
00401   *   This parameter can be any combination of the following values:
00402   *     @arg CEC_IT_TERR: Tx Error
00403   *     @arg CEC_IT_TBTF: Tx Block Transfer Finished
00404   *     @arg CEC_IT_RERR: Rx Error
00405   *     @arg CEC_IT_RBTF: Rx Block Transfer Finished
00406   * @retval None
00407   */
00408 void CEC_ClearITPendingBit(uint16_t CEC_IT)
00409 {
00410   uint32_t tmp = 0x0;
00411
00412   /* Check the parameters */
00413   assert_param(IS_CEC_GET_IT(CEC_IT));
00414
00415   tmp = CEC->CSR & 0x2;
00416
00417   /* Clear the selected CEC interrupt pending bits */
00418   CEC->CSR &= (uint32_t)(((~(uint32_t)CEC_IT) & 0xFFFFFFFC) | tmp);
00419 }
00420
00421 /**
00422   * @}
00423   */
00424
00425 /**
00426   * @}
00427   */
00428
00429 /**
00430   * @}
00431   */
00432
00433 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_cec.h Source File

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stm32f10x_cec.h

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f10x_cec.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    11-March-2011
00007   * @brief   This file contains all the functions prototypes for the CEC firmware
00008   *          library.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00013   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00014   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00015   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00016   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00017   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00018   *
00019   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00020   ******************************************************************************
00021   */
00022
00023 /* Define to prevent recursive inclusion -------------------------------------*/
00024 #ifndef __STM32F10x_CEC_H
00025 #define __STM32F10x_CEC_H
00026
00027 #ifdef __cplusplus
00028  extern "C" {
00029 #endif
00030
00031 /* Includes ------------------------------------------------------------------*/
00032 #include "stm32f10x.h"
00033
00034 /** @addtogroup STM32F10x_StdPeriph_Driver
00035   * @{
00036   */
00037
00038 /** @addtogroup CEC
00039   * @{
00040   */
00041
00042
00043 /** @defgroup CEC_Exported_Types
00044   * @{
00045   */
00046
00047 /**
00048   * @brief  CEC Init structure definition
00049   */
00050 typedef struct
00051 {
00052   uint16_t CEC_BitTimingMode; /*!< Configures the CEC Bit Timing Error Mode.
00053                                This parameter can be a value of @ref CEC_BitTiming_Mode */
00054   uint16_t CEC_BitPeriodMode; /*!< Configures the CEC Bit Period Error Mode.
00055                                This parameter can be a value of @ref CEC_BitPeriod_Mode */
00056 }CEC_InitTypeDef;
00057
00058 /**
00059   * @}
00060   */
00061
00062 /** @defgroup CEC_Exported_Constants
00063   * @{
00064   */
00065
00066 /** @defgroup CEC_BitTiming_Mode
00067   * @{
00068   */
00069 #define CEC_BitTimingStdMode                    ((uint16_t)0x00) /*!< Bit timing error Standard Mode */
00070 #define CEC_BitTimingErrFreeMode                CEC_CFGR_BTEM   /*!< Bit timing error Free Mode */
00071
00072 #define IS_CEC_BIT_TIMING_ERROR_MODE(MODE) (((MODE) == CEC_BitTimingStdMode) || \
00073                                             ((MODE) == CEC_BitTimingErrFreeMode))
00074 /**
00075   * @}
00076   */
00077
00078 /** @defgroup CEC_BitPeriod_Mode
00079   * @{
00080   */
00081 #define CEC_BitPeriodStdMode                    ((uint16_t)0x00) /*!< Bit period error Standard Mode */
00082 #define CEC_BitPeriodFlexibleMode                CEC_CFGR_BPEM   /*!< Bit period error Flexible Mode */
00083
00084 #define IS_CEC_BIT_PERIOD_ERROR_MODE(MODE) (((MODE) == CEC_BitPeriodStdMode) || \
00085                                             ((MODE) == CEC_BitPeriodFlexibleMode))
00086 /**
00087   * @}
00088   */
00089
00090
00091 /** @defgroup CEC_interrupts_definition
00092   * @{
00093   */
00094 #define CEC_IT_TERR                              CEC_CSR_TERR
00095 #define CEC_IT_TBTRF                             CEC_CSR_TBTRF
00096 #define CEC_IT_RERR                              CEC_CSR_RERR
00097 #define CEC_IT_RBTF                              CEC_CSR_RBTF
00098 #define IS_CEC_GET_IT(IT) (((IT) == CEC_IT_TERR) || ((IT) == CEC_IT_TBTRF) || \
00099                            ((IT) == CEC_IT_RERR) || ((IT) == CEC_IT_RBTF))
00100 /**
00101   * @}
00102   */
00103
00104
00105 /** @defgroup CEC_Own_Address
00106   * @{
00107   */
00108 #define IS_CEC_ADDRESS(ADDRESS) ((ADDRESS) < 0x10)
00109 /**
00110   * @}
00111   */
00112
00113 /** @defgroup CEC_Prescaler
00114   * @{
00115   */
00116 #define IS_CEC_PRESCALER(PRESCALER) ((PRESCALER) <= 0x3FFF)
00117
00118 /**
00119   * @}
00120   */
00121
00122 /** @defgroup CEC_flags_definition
00123   * @{
00124   */
00125
00126 /**
00127   * @brief  ESR register flags
00128   */
00129 #define CEC_FLAG_BTE                            ((uint32_t)0x10010000)
00130 #define CEC_FLAG_BPE                            ((uint32_t)0x10020000)
00131 #define CEC_FLAG_RBTFE                          ((uint32_t)0x10040000)
00132 #define CEC_FLAG_SBE                            ((uint32_t)0x10080000)
00133 #define CEC_FLAG_ACKE                           ((uint32_t)0x10100000)
00134 #define CEC_FLAG_LINE                           ((uint32_t)0x10200000)
00135 #define CEC_FLAG_TBTFE                          ((uint32_t)0x10400000)
00136
00137 /**
00138   * @brief  CSR register flags
00139   */
00140 #define CEC_FLAG_TEOM                           ((uint32_t)0x00000002)
00141 #define CEC_FLAG_TERR                           ((uint32_t)0x00000004)
00142 #define CEC_FLAG_TBTRF                          ((uint32_t)0x00000008)
00143 #define CEC_FLAG_RSOM                           ((uint32_t)0x00000010)
00144 #define CEC_FLAG_REOM                           ((uint32_t)0x00000020)
00145 #define CEC_FLAG_RERR                           ((uint32_t)0x00000040)
00146 #define CEC_FLAG_RBTF                           ((uint32_t)0x00000080)
00147
00148 #define IS_CEC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFF03) == 0x00) && ((FLAG) != 0x00))
00149
00150 #define IS_CEC_GET_FLAG(FLAG) (((FLAG) == CEC_FLAG_BTE) || ((FLAG) == CEC_FLAG_BPE) || \
00151                                ((FLAG) == CEC_FLAG_RBTFE) || ((FLAG)== CEC_FLAG_SBE) || \
00152                                ((FLAG) == CEC_FLAG_ACKE) || ((FLAG) == CEC_FLAG_LINE) || \
00153                                ((FLAG) == CEC_FLAG_TBTFE) || ((FLAG) == CEC_FLAG_TEOM) || \
00154                                ((FLAG) == CEC_FLAG_TERR) || ((FLAG) == CEC_FLAG_TBTRF) || \
00155                                ((FLAG) == CEC_FLAG_RSOM) || ((FLAG) == CEC_FLAG_REOM) || \
00156                                ((FLAG) == CEC_FLAG_RERR) || ((FLAG) == CEC_FLAG_RBTF))
00157
00158 /**
00159   * @}
00160   */
00161
00162 /**
00163   * @}
00164   */
00165
00166 /** @defgroup CEC_Exported_Macros
00167   * @{
00168   */
00169
00170 /**
00171   * @}
00172   */
00173
00174 /** @defgroup CEC_Exported_Functions
00175   * @{
00176   */
00177 void CEC_DeInit(void);
00178 void CEC_Init(CEC_InitTypeDef* CEC_InitStruct);
00179 void CEC_Cmd(FunctionalState NewState);
00180 void CEC_ITConfig(FunctionalState NewState);
00181 void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress);
00182 void CEC_SetPrescaler(uint16_t CEC_Prescaler);
00183 void CEC_SendDataByte(uint8_t Data);
00184 uint8_t CEC_ReceiveDataByte(void);
00185 void CEC_StartOfMessage(void);
00186 void CEC_EndOfMessageCmd(FunctionalState NewState);
00187 FlagStatus CEC_GetFlagStatus(uint32_t CEC_FLAG);
00188 void CEC_ClearFlag(uint32_t CEC_FLAG);
00189 ITStatus CEC_GetITStatus(uint8_t CEC_IT);
00190 void CEC_ClearITPendingBit(uint16_t CEC_IT);
00191
00192 #ifdef __cplusplus
00193 }
00194 #endif
00195
00196 #endif /* __STM32F10x_CEC_H */
00197
00198 /**
00199   * @}
00200   */
00201
00202 /**
00203   * @}
00204   */
00205
00206 /**
00207   * @}
00208   */
00209
00210 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_crc.c Source File

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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Libraries
  • STM32F10x_StdPeriph_Driver
  • src

stm32f10x_crc.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32f10x_crc.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    11-March-2011
00007   * @brief   This file provides all the CRC firmware functions.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x_crc.h"
00024
00025 /** @addtogroup STM32F10x_StdPeriph_Driver
00026   * @{
00027   */
00028
00029 /** @defgroup CRC
00030   * @brief CRC driver modules
00031   * @{
00032   */
00033
00034 /** @defgroup CRC_Private_TypesDefinitions
00035   * @{
00036   */
00037
00038 /**
00039   * @}
00040   */
00041
00042 /** @defgroup CRC_Private_Defines
00043   * @{
00044   */
00045
00046 /**
00047   * @}
00048   */
00049
00050 /** @defgroup CRC_Private_Macros
00051   * @{
00052   */
00053
00054 /**
00055   * @}
00056   */
00057
00058 /** @defgroup CRC_Private_Variables
00059   * @{
00060   */
00061
00062 /**
00063   * @}
00064   */
00065
00066 /** @defgroup CRC_Private_FunctionPrototypes
00067   * @{
00068   */
00069
00070 /**
00071   * @}
00072   */
00073
00074 /** @defgroup CRC_Private_Functions
00075   * @{
00076   */
00077
00078 /**
00079   * @brief  Resets the CRC Data register (DR).
00080   * @param  None
00081   * @retval None
00082   */
00083 void CRC_ResetDR(void)
00084 {
00085   /* Reset CRC generator */
00086   CRC->CR = CRC_CR_RESET;
00087 }
00088
00089 /**
00090   * @brief  Computes the 32-bit CRC of a given data word(32-bit).
00091   * @param  Data: data word(32-bit) to compute its CRC
00092   * @retval 32-bit CRC
00093   */
00094 uint32_t CRC_CalcCRC(uint32_t Data)
00095 {
00096   CRC->DR = Data;
00097
00098   return (CRC->DR);
00099 }
00100
00101 /**
00102   * @brief  Computes the 32-bit CRC of a given buffer of data word(32-bit).
00103   * @param  pBuffer: pointer to the buffer containing the data to be computed
00104   * @param  BufferLength: length of the buffer to be computed
00105   * @retval 32-bit CRC
00106   */
00107 uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength)
00108 {
00109   uint32_t index = 0;
00110
00111   for(index = 0; index < BufferLength; index++)
00112   {
00113     CRC->DR = pBuffer[index];
00114   }
00115   return (CRC->DR);
00116 }
00117
00118 /**
00119   * @brief  Returns the current CRC value.
00120   * @param  None
00121   * @retval 32-bit CRC
00122   */
00123 uint32_t CRC_GetCRC(void)
00124 {
00125   return (CRC->DR);
00126 }
00127
00128 /**
00129   * @brief  Stores a 8-bit data in the Independent Data(ID) register.
00130   * @param  IDValue: 8-bit value to be stored in the ID register
00131   * @retval None
00132   */
00133 void CRC_SetIDRegister(uint8_t IDValue)
00134 {
00135   CRC->IDR = IDValue;
00136 }
00137
00138 /**
00139   * @brief  Returns the 8-bit data stored in the Independent Data(ID) register
00140   * @param  None
00141   * @retval 8-bit value of the ID register
00142   */
00143 uint8_t CRC_GetIDRegister(void)
00144 {
00145   return (CRC->IDR);
00146 }
00147
00148 /**
00149   * @}
00150   */
00151
00152 /**
00153   * @}
00154   */
00155
00156 /**
00157   * @}
00158   */
00159
00160 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_crc.h Source File

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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Libraries
  • STM32F10x_StdPeriph_Driver
  • inc

stm32f10x_crc.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32f10x_crc.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    11-March-2011
00007   * @brief   This file contains all the functions prototypes for the CRC firmware
00008   *          library.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00013   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00014   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00015   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00016   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00017   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00018   *
00019   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00020   ******************************************************************************
00021   */
00022
00023 /* Define to prevent recursive inclusion -------------------------------------*/
00024 #ifndef __STM32F10x_CRC_H
00025 #define __STM32F10x_CRC_H
00026
00027 #ifdef __cplusplus
00028  extern "C" {
00029 #endif
00030
00031 /* Includes ------------------------------------------------------------------*/
00032 #include "stm32f10x.h"
00033
00034 /** @addtogroup STM32F10x_StdPeriph_Driver
00035   * @{
00036   */
00037
00038 /** @addtogroup CRC
00039   * @{
00040   */
00041
00042 /** @defgroup CRC_Exported_Types
00043   * @{
00044   */
00045
00046 /**
00047   * @}
00048   */
00049
00050 /** @defgroup CRC_Exported_Constants
00051   * @{
00052   */
00053
00054 /**
00055   * @}
00056   */
00057
00058 /** @defgroup CRC_Exported_Macros
00059   * @{
00060   */
00061
00062 /**
00063   * @}
00064   */
00065
00066 /** @defgroup CRC_Exported_Functions
00067   * @{
00068   */
00069
00070 void CRC_ResetDR(void);
00071 uint32_t CRC_CalcCRC(uint32_t Data);
00072 uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength);
00073 uint32_t CRC_GetCRC(void);
00074 void CRC_SetIDRegister(uint8_t IDValue);
00075 uint8_t CRC_GetIDRegister(void);
00076
00077 #ifdef __cplusplus
00078 }
00079 #endif
00080
00081 #endif /* __STM32F10x_CRC_H */
00082 /**
00083   * @}
00084   */
00085
00086 /**
00087   * @}
00088   */
00089
00090 /**
00091   * @}
00092   */
00093
00094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_dac.c Source File

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  • src

stm32f10x_dac.c

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f10x_dac.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    11-March-2011
00007   * @brief   This file provides all the DAC firmware functions.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x_dac.h"
00024 #include "stm32f10x_rcc.h"
00025
00026 /** @addtogroup STM32F10x_StdPeriph_Driver
00027   * @{
00028   */
00029
00030 /** @defgroup DAC
00031   * @brief DAC driver modules
00032   * @{
00033   */
00034
00035 /** @defgroup DAC_Private_TypesDefinitions
00036   * @{
00037   */
00038
00039 /**
00040   * @}
00041   */
00042
00043 /** @defgroup DAC_Private_Defines
00044   * @{
00045   */
00046
00047 /* CR register Mask */
00048 #define CR_CLEAR_MASK              ((uint32_t)0x00000FFE)
00049
00050 /* DAC Dual Channels SWTRIG masks */
00051 #define DUAL_SWTRIG_SET            ((uint32_t)0x00000003)
00052 #define DUAL_SWTRIG_RESET          ((uint32_t)0xFFFFFFFC)
00053
00054 /* DHR registers offsets */
00055 #define DHR12R1_OFFSET             ((uint32_t)0x00000008)
00056 #define DHR12R2_OFFSET             ((uint32_t)0x00000014)
00057 #define DHR12RD_OFFSET             ((uint32_t)0x00000020)
00058
00059 /* DOR register offset */
00060 #define DOR_OFFSET                 ((uint32_t)0x0000002C)
00061 /**
00062   * @}
00063   */
00064
00065 /** @defgroup DAC_Private_Macros
00066   * @{
00067   */
00068
00069 /**
00070   * @}
00071   */
00072
00073 /** @defgroup DAC_Private_Variables
00074   * @{
00075   */
00076
00077 /**
00078   * @}
00079   */
00080
00081 /** @defgroup DAC_Private_FunctionPrototypes
00082   * @{
00083   */
00084
00085 /**
00086   * @}
00087   */
00088
00089 /** @defgroup DAC_Private_Functions
00090   * @{
00091   */
00092
00093 /**
00094   * @brief  Deinitializes the DAC peripheral registers to their default reset values.
00095   * @param  None
00096   * @retval None
00097   */
00098 void DAC_DeInit(void)
00099 {
00100   /* Enable DAC reset state */
00101   RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE);
00102   /* Release DAC from reset state */
00103   RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE);
00104 }
00105
00106 /**
00107   * @brief  Initializes the DAC peripheral according to the specified
00108   *         parameters in the DAC_InitStruct.
00109   * @param  DAC_Channel: the selected DAC channel.
00110   *   This parameter can be one of the following values:
00111   *     @arg DAC_Channel_1: DAC Channel1 selected
00112   *     @arg DAC_Channel_2: DAC Channel2 selected
00113   * @param  DAC_InitStruct: pointer to a DAC_InitTypeDef structure that
00114   *        contains the configuration information for the specified DAC channel.
00115   * @retval None
00116   */
00117 void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct)
00118 {
00119   uint32_t tmpreg1 = 0, tmpreg2 = 0;
00120   /* Check the DAC parameters */
00121   assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger));
00122   assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration));
00123   assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude));
00124   assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer));
00125 /*---------------------------- DAC CR Configuration --------------------------*/
00126   /* Get the DAC CR value */
00127   tmpreg1 = DAC->CR;
00128   /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
00129   tmpreg1 &= ~(CR_CLEAR_MASK << DAC_Channel);
00130   /* Configure for the selected DAC channel: buffer output, trigger, wave generation,
00131      mask/amplitude for wave generation */
00132   /* Set TSELx and TENx bits according to DAC_Trigger value */
00133   /* Set WAVEx bits according to DAC_WaveGeneration value */
00134   /* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */
00135   /* Set BOFFx bit according to DAC_OutputBuffer value */
00136   tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration |
00137              DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | DAC_InitStruct->DAC_OutputBuffer);
00138   /* Calculate CR register value depending on DAC_Channel */
00139   tmpreg1 |= tmpreg2 << DAC_Channel;
00140   /* Write to DAC CR */
00141   DAC->CR = tmpreg1;
00142 }
00143
00144 /**
00145   * @brief  Fills each DAC_InitStruct member with its default value.
00146   * @param  DAC_InitStruct : pointer to a DAC_InitTypeDef structure which will
00147   *         be initialized.
00148   * @retval None
00149   */
00150 void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct)
00151 {
00152 /*--------------- Reset DAC init structure parameters values -----------------*/
00153   /* Initialize the DAC_Trigger member */
00154   DAC_InitStruct->DAC_Trigger = DAC_Trigger_None;
00155   /* Initialize the DAC_WaveGeneration member */
00156   DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None;
00157   /* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */
00158   DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0;
00159   /* Initialize the DAC_OutputBuffer member */
00160   DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable;
00161 }
00162
00163 /**
00164   * @brief  Enables or disables the specified DAC channel.
00165   * @param  DAC_Channel: the selected DAC channel.
00166   *   This parameter can be one of the following values:
00167   *     @arg DAC_Channel_1: DAC Channel1 selected
00168   *     @arg DAC_Channel_2: DAC Channel2 selected
00169   * @param  NewState: new state of the DAC channel.
00170   *   This parameter can be: ENABLE or DISABLE.
00171   * @retval None
00172   */
00173 void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState)
00174 {
00175   /* Check the parameters */
00176   assert_param(IS_DAC_CHANNEL(DAC_Channel));
00177   assert_param(IS_FUNCTIONAL_STATE(NewState));
00178   if (NewState != DISABLE)
00179   {
00180     /* Enable the selected DAC channel */
00181     DAC->CR |= (DAC_CR_EN1 << DAC_Channel);
00182   }
00183   else
00184   {
00185     /* Disable the selected DAC channel */
00186     DAC->CR &= ~(DAC_CR_EN1 << DAC_Channel);
00187   }
00188 }
00189 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00190 /**
00191   * @brief  Enables or disables the specified DAC interrupts.
00192   * @param  DAC_Channel: the selected DAC channel.
00193   *   This parameter can be one of the following values:
00194   *     @arg DAC_Channel_1: DAC Channel1 selected
00195   *     @arg DAC_Channel_2: DAC Channel2 selected
00196   * @param  DAC_IT: specifies the DAC interrupt sources to be enabled or disabled.
00197   *   This parameter can be the following values:
00198   *     @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
00199   * @param  NewState: new state of the specified DAC interrupts.
00200   *   This parameter can be: ENABLE or DISABLE.
00201   * @retval None
00202   */
00203 void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState)
00204 {
00205   /* Check the parameters */
00206   assert_param(IS_DAC_CHANNEL(DAC_Channel));
00207   assert_param(IS_FUNCTIONAL_STATE(NewState));
00208   assert_param(IS_DAC_IT(DAC_IT));
00209
00210   if (NewState != DISABLE)
00211   {
00212     /* Enable the selected DAC interrupts */
00213     DAC->CR |=  (DAC_IT << DAC_Channel);
00214   }
00215   else
00216   {
00217     /* Disable the selected DAC interrupts */
00218     DAC->CR &= (~(uint32_t)(DAC_IT << DAC_Channel));
00219   }
00220 }
00221 #endif
00222
00223 /**
00224   * @brief  Enables or disables the specified DAC channel DMA request.
00225   * @param  DAC_Channel: the selected DAC channel.
00226   *   This parameter can be one of the following values:
00227   *     @arg DAC_Channel_1: DAC Channel1 selected
00228   *     @arg DAC_Channel_2: DAC Channel2 selected
00229   * @param  NewState: new state of the selected DAC channel DMA request.
00230   *   This parameter can be: ENABLE or DISABLE.
00231   * @retval None
00232   */
00233 void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState)
00234 {
00235   /* Check the parameters */
00236   assert_param(IS_DAC_CHANNEL(DAC_Channel));
00237   assert_param(IS_FUNCTIONAL_STATE(NewState));
00238   if (NewState != DISABLE)
00239   {
00240     /* Enable the selected DAC channel DMA request */
00241     DAC->CR |= (DAC_CR_DMAEN1 << DAC_Channel);
00242   }
00243   else
00244   {
00245     /* Disable the selected DAC channel DMA request */
00246     DAC->CR &= ~(DAC_CR_DMAEN1 << DAC_Channel);
00247   }
00248 }
00249
00250 /**
00251   * @brief  Enables or disables the selected DAC channel software trigger.
00252   * @param  DAC_Channel: the selected DAC channel.
00253   *   This parameter can be one of the following values:
00254   *     @arg DAC_Channel_1: DAC Channel1 selected
00255   *     @arg DAC_Channel_2: DAC Channel2 selected
00256   * @param  NewState: new state of the selected DAC channel software trigger.
00257   *   This parameter can be: ENABLE or DISABLE.
00258   * @retval None
00259   */
00260 void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState)
00261 {
00262   /* Check the parameters */
00263   assert_param(IS_DAC_CHANNEL(DAC_Channel));
00264   assert_param(IS_FUNCTIONAL_STATE(NewState));
00265   if (NewState != DISABLE)
00266   {
00267     /* Enable software trigger for the selected DAC channel */
00268     DAC->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4);
00269   }
00270   else
00271   {
00272     /* Disable software trigger for the selected DAC channel */
00273     DAC->SWTRIGR &= ~((uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4));
00274   }
00275 }
00276
00277 /**
00278   * @brief  Enables or disables simultaneously the two DAC channels software
00279   *   triggers.
00280   * @param  NewState: new state of the DAC channels software triggers.
00281   *   This parameter can be: ENABLE or DISABLE.
00282   * @retval None
00283   */
00284 void DAC_DualSoftwareTriggerCmd(FunctionalState NewState)
00285 {
00286   /* Check the parameters */
00287   assert_param(IS_FUNCTIONAL_STATE(NewState));
00288   if (NewState != DISABLE)
00289   {
00290     /* Enable software trigger for both DAC channels */
00291     DAC->SWTRIGR |= DUAL_SWTRIG_SET ;
00292   }
00293   else
00294   {
00295     /* Disable software trigger for both DAC channels */
00296     DAC->SWTRIGR &= DUAL_SWTRIG_RESET;
00297   }
00298 }
00299
00300 /**
00301   * @brief  Enables or disables the selected DAC channel wave generation.
00302   * @param  DAC_Channel: the selected DAC channel.
00303   *   This parameter can be one of the following values:
00304   *     @arg DAC_Channel_1: DAC Channel1 selected
00305   *     @arg DAC_Channel_2: DAC Channel2 selected
00306   * @param  DAC_Wave: Specifies the wave type to enable or disable.
00307   *   This parameter can be one of the following values:
00308   *     @arg DAC_Wave_Noise: noise wave generation
00309   *     @arg DAC_Wave_Triangle: triangle wave generation
00310   * @param  NewState: new state of the selected DAC channel wave generation.
00311   *   This parameter can be: ENABLE or DISABLE.
00312   * @retval None
00313   */
00314 void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState)
00315 {
00316   /* Check the parameters */
00317   assert_param(IS_DAC_CHANNEL(DAC_Channel));
00318   assert_param(IS_DAC_WAVE(DAC_Wave));
00319   assert_param(IS_FUNCTIONAL_STATE(NewState));
00320   if (NewState != DISABLE)
00321   {
00322     /* Enable the selected wave generation for the selected DAC channel */
00323     DAC->CR |= DAC_Wave << DAC_Channel;
00324   }
00325   else
00326   {
00327     /* Disable the selected wave generation for the selected DAC channel */
00328     DAC->CR &= ~(DAC_Wave << DAC_Channel);
00329   }
00330 }
00331
00332 /**
00333   * @brief  Set the specified data holding register value for DAC channel1.
00334   * @param  DAC_Align: Specifies the data alignment for DAC channel1.
00335   *   This parameter can be one of the following values:
00336   *     @arg DAC_Align_8b_R: 8bit right data alignment selected
00337   *     @arg DAC_Align_12b_L: 12bit left data alignment selected
00338   *     @arg DAC_Align_12b_R: 12bit right data alignment selected
00339   * @param  Data : Data to be loaded in the selected data holding register.
00340   * @retval None
00341   */
00342 void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data)
00343 {
00344   __IO uint32_t tmp = 0;
00345
00346   /* Check the parameters */
00347   assert_param(IS_DAC_ALIGN(DAC_Align));
00348   assert_param(IS_DAC_DATA(Data));
00349
00350   tmp = (uint32_t)DAC_BASE;
00351   tmp += DHR12R1_OFFSET + DAC_Align;
00352
00353   /* Set the DAC channel1 selected data holding register */
00354   *(__IO uint32_t *) tmp = Data;
00355 }
00356
00357 /**
00358   * @brief  Set the specified data holding register value for DAC channel2.
00359   * @param  DAC_Align: Specifies the data alignment for DAC channel2.
00360   *   This parameter can be one of the following values:
00361   *     @arg DAC_Align_8b_R: 8bit right data alignment selected
00362   *     @arg DAC_Align_12b_L: 12bit left data alignment selected
00363   *     @arg DAC_Align_12b_R: 12bit right data alignment selected
00364   * @param  Data : Data to be loaded in the selected data holding register.
00365   * @retval None
00366   */
00367 void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data)
00368 {
00369   __IO uint32_t tmp = 0;
00370
00371   /* Check the parameters */
00372   assert_param(IS_DAC_ALIGN(DAC_Align));
00373   assert_param(IS_DAC_DATA(Data));
00374
00375   tmp = (uint32_t)DAC_BASE;
00376   tmp += DHR12R2_OFFSET + DAC_Align;
00377
00378   /* Set the DAC channel2 selected data holding register */
00379   *(__IO uint32_t *)tmp = Data;
00380 }
00381
00382 /**
00383   * @brief  Set the specified data holding register value for dual channel
00384   *   DAC.
00385   * @param  DAC_Align: Specifies the data alignment for dual channel DAC.
00386   *   This parameter can be one of the following values:
00387   *     @arg DAC_Align_8b_R: 8bit right data alignment selected
00388   *     @arg DAC_Align_12b_L: 12bit left data alignment selected
00389   *     @arg DAC_Align_12b_R: 12bit right data alignment selected
00390   * @param  Data2: Data for DAC Channel2 to be loaded in the selected data
00391   *   holding register.
00392   * @param  Data1: Data for DAC Channel1 to be loaded in the selected data
00393   *   holding register.
00394   * @retval None
00395   */
00396 void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1)
00397 {
00398   uint32_t data = 0, tmp = 0;
00399
00400   /* Check the parameters */
00401   assert_param(IS_DAC_ALIGN(DAC_Align));
00402   assert_param(IS_DAC_DATA(Data1));
00403   assert_param(IS_DAC_DATA(Data2));
00404
00405   /* Calculate and set dual DAC data holding register value */
00406   if (DAC_Align == DAC_Align_8b_R)
00407   {
00408     data = ((uint32_t)Data2 << 8) | Data1;
00409   }
00410   else
00411   {
00412     data = ((uint32_t)Data2 << 16) | Data1;
00413   }
00414
00415   tmp = (uint32_t)DAC_BASE;
00416   tmp += DHR12RD_OFFSET + DAC_Align;
00417
00418   /* Set the dual DAC selected data holding register */
00419   *(__IO uint32_t *)tmp = data;
00420 }
00421
00422 /**
00423   * @brief  Returns the last data output value of the selected DAC channel.
00424   * @param  DAC_Channel: the selected DAC channel.
00425   *   This parameter can be one of the following values:
00426   *     @arg DAC_Channel_1: DAC Channel1 selected
00427   *     @arg DAC_Channel_2: DAC Channel2 selected
00428   * @retval The selected DAC channel data output value.
00429   */
00430 uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel)
00431 {
00432   __IO uint32_t tmp = 0;
00433
00434   /* Check the parameters */
00435   assert_param(IS_DAC_CHANNEL(DAC_Channel));
00436
00437   tmp = (uint32_t) DAC_BASE ;
00438   tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2);
00439
00440   /* Returns the DAC channel data output register value */
00441   return (uint16_t) (*(__IO uint32_t*) tmp);
00442 }
00443
00444 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00445 /**
00446   * @brief  Checks whether the specified DAC flag is set or not.
00447   * @param  DAC_Channel: thee selected DAC channel.
00448   *   This parameter can be one of the following values:
00449   *     @arg DAC_Channel_1: DAC Channel1 selected
00450   *     @arg DAC_Channel_2: DAC Channel2 selected
00451   * @param  DAC_FLAG: specifies the flag to check.
00452   *   This parameter can be only of the following value:
00453   *     @arg DAC_FLAG_DMAUDR: DMA underrun flag
00454   * @retval The new state of DAC_FLAG (SET or RESET).
00455   */
00456 FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG)
00457 {
00458   FlagStatus bitstatus = RESET;
00459   /* Check the parameters */
00460   assert_param(IS_DAC_CHANNEL(DAC_Channel));
00461   assert_param(IS_DAC_FLAG(DAC_FLAG));
00462
00463   /* Check the status of the specified DAC flag */
00464   if ((DAC->SR & (DAC_FLAG << DAC_Channel)) != (uint8_t)RESET)
00465   {
00466     /* DAC_FLAG is set */
00467     bitstatus = SET;
00468   }
00469   else
00470   {
00471     /* DAC_FLAG is reset */
00472     bitstatus = RESET;
00473   }
00474   /* Return the DAC_FLAG status */
00475   return  bitstatus;
00476 }
00477
00478 /**
00479   * @brief  Clears the DAC channelx's pending flags.
00480   * @param  DAC_Channel: the selected DAC channel.
00481   *   This parameter can be one of the following values:
00482   *     @arg DAC_Channel_1: DAC Channel1 selected
00483   *     @arg DAC_Channel_2: DAC Channel2 selected
00484   * @param  DAC_FLAG: specifies the flag to clear.
00485   *   This parameter can be of the following value:
00486   *     @arg DAC_FLAG_DMAUDR: DMA underrun flag
00487   * @retval None
00488   */
00489 void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG)
00490 {
00491   /* Check the parameters */
00492   assert_param(IS_DAC_CHANNEL(DAC_Channel));
00493   assert_param(IS_DAC_FLAG(DAC_FLAG));
00494
00495   /* Clear the selected DAC flags */
00496   DAC->SR = (DAC_FLAG << DAC_Channel);
00497 }
00498
00499 /**
00500   * @brief  Checks whether the specified DAC interrupt has occurred or not.
00501   * @param  DAC_Channel: the selected DAC channel.
00502   *   This parameter can be one of the following values:
00503   *     @arg DAC_Channel_1: DAC Channel1 selected
00504   *     @arg DAC_Channel_2: DAC Channel2 selected
00505   * @param  DAC_IT: specifies the DAC interrupt source to check.
00506   *   This parameter can be the following values:
00507   *     @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
00508   * @retval The new state of DAC_IT (SET or RESET).
00509   */
00510 ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT)
00511 {
00512   ITStatus bitstatus = RESET;
00513   uint32_t enablestatus = 0;
00514
00515   /* Check the parameters */
00516   assert_param(IS_DAC_CHANNEL(DAC_Channel));
00517   assert_param(IS_DAC_IT(DAC_IT));
00518
00519   /* Get the DAC_IT enable bit status */
00520   enablestatus = (DAC->CR & (DAC_IT << DAC_Channel)) ;
00521
00522   /* Check the status of the specified DAC interrupt */
00523   if (((DAC->SR & (DAC_IT << DAC_Channel)) != (uint32_t)RESET) && enablestatus)
00524   {
00525     /* DAC_IT is set */
00526     bitstatus = SET;
00527   }
00528   else
00529   {
00530     /* DAC_IT is reset */
00531     bitstatus = RESET;
00532   }
00533   /* Return the DAC_IT status */
00534   return  bitstatus;
00535 }
00536
00537 /**
00538   * @brief  Clears the DAC channelx's interrupt pending bits.
00539   * @param  DAC_Channel: the selected DAC channel.
00540   *   This parameter can be one of the following values:
00541   *     @arg DAC_Channel_1: DAC Channel1 selected
00542   *     @arg DAC_Channel_2: DAC Channel2 selected
00543   * @param  DAC_IT: specifies the DAC interrupt pending bit to clear.
00544   *   This parameter can be the following values:
00545   *     @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
00546   * @retval None
00547   */
00548 void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT)
00549 {
00550   /* Check the parameters */
00551   assert_param(IS_DAC_CHANNEL(DAC_Channel));
00552   assert_param(IS_DAC_IT(DAC_IT));
00553
00554   /* Clear the selected DAC interrupt pending bits */
00555   DAC->SR = (DAC_IT << DAC_Channel);
00556 }
00557 #endif
00558
00559 /**
00560   * @}
00561   */
00562
00563 /**
00564   * @}
00565   */
00566
00567 /**
00568   * @}
00569   */
00570
00571 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_dac.h Source File

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stm32f10x_dac.h

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f10x_dac.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    11-March-2011
00007   * @brief   This file contains all the functions prototypes for the DAC firmware
00008   *          library.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00013   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00014   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00015   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00016   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00017   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00018   *
00019   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00020   ******************************************************************************
00021   */
00022
00023 /* Define to prevent recursive inclusion -------------------------------------*/
00024 #ifndef __STM32F10x_DAC_H
00025 #define __STM32F10x_DAC_H
00026
00027 #ifdef __cplusplus
00028  extern "C" {
00029 #endif
00030
00031 /* Includes ------------------------------------------------------------------*/
00032 #include "stm32f10x.h"
00033
00034 /** @addtogroup STM32F10x_StdPeriph_Driver
00035   * @{
00036   */
00037
00038 /** @addtogroup DAC
00039   * @{
00040   */
00041
00042 /** @defgroup DAC_Exported_Types
00043   * @{
00044   */
00045
00046 /**
00047   * @brief  DAC Init structure definition
00048   */
00049
00050 typedef struct
00051 {
00052   uint32_t DAC_Trigger;                      /*!< Specifies the external trigger for the selected DAC channel.
00053                                                   This parameter can be a value of @ref DAC_trigger_selection */
00054
00055   uint32_t DAC_WaveGeneration;               /*!< Specifies whether DAC channel noise waves or triangle waves
00056                                                   are generated, or whether no wave is generated.
00057                                                   This parameter can be a value of @ref DAC_wave_generation */
00058
00059   uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or
00060                                                   the maximum amplitude triangle generation for the DAC channel.
00061                                                   This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */
00062
00063   uint32_t DAC_OutputBuffer;                 /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
00064                                                   This parameter can be a value of @ref DAC_output_buffer */
00065 }DAC_InitTypeDef;
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @defgroup DAC_Exported_Constants
00072   * @{
00073   */
00074
00075 /** @defgroup DAC_trigger_selection
00076   * @{
00077   */
00078
00079 #define DAC_Trigger_None                   ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register
00080                                                                        has been loaded, and not by external trigger */
00081 #define DAC_Trigger_T6_TRGO                ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
00082 #define DAC_Trigger_T8_TRGO                ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel
00083                                                                        only in High-density devices*/
00084 #define DAC_Trigger_T3_TRGO                ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel
00085                                                                        only in Connectivity line, Medium-density and Low-density Value Line devices */
00086 #define DAC_Trigger_T7_TRGO                ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
00087 #define DAC_Trigger_T5_TRGO                ((uint32_t)0x0000001C) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
00088 #define DAC_Trigger_T15_TRGO               ((uint32_t)0x0000001C) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel
00089                                                                        only in Medium-density and Low-density Value Line devices*/
00090 #define DAC_Trigger_T2_TRGO                ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
00091 #define DAC_Trigger_T4_TRGO                ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
00092 #define DAC_Trigger_Ext_IT9                ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
00093 #define DAC_Trigger_Software               ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */
00094
00095 #define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \
00096                                  ((TRIGGER) == DAC_Trigger_T6_TRGO) || \
00097                                  ((TRIGGER) == DAC_Trigger_T8_TRGO) || \
00098                                  ((TRIGGER) == DAC_Trigger_T7_TRGO) || \
00099                                  ((TRIGGER) == DAC_Trigger_T5_TRGO) || \
00100                                  ((TRIGGER) == DAC_Trigger_T2_TRGO) || \
00101                                  ((TRIGGER) == DAC_Trigger_T4_TRGO) || \
00102                                  ((TRIGGER) == DAC_Trigger_Ext_IT9) || \
00103                                  ((TRIGGER) == DAC_Trigger_Software))
00104
00105 /**
00106   * @}
00107   */
00108
00109 /** @defgroup DAC_wave_generation
00110   * @{
00111   */
00112
00113 #define DAC_WaveGeneration_None            ((uint32_t)0x00000000)
00114 #define DAC_WaveGeneration_Noise           ((uint32_t)0x00000040)
00115 #define DAC_WaveGeneration_Triangle        ((uint32_t)0x00000080)
00116 #define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \
00117                                     ((WAVE) == DAC_WaveGeneration_Noise) || \
00118                                     ((WAVE) == DAC_WaveGeneration_Triangle))
00119 /**
00120   * @}
00121   */
00122
00123 /** @defgroup DAC_lfsrunmask_triangleamplitude
00124   * @{
00125   */
00126
00127 #define DAC_LFSRUnmask_Bit0                ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
00128 #define DAC_LFSRUnmask_Bits1_0             ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
00129 #define DAC_LFSRUnmask_Bits2_0             ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
00130 #define DAC_LFSRUnmask_Bits3_0             ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
00131 #define DAC_LFSRUnmask_Bits4_0             ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
00132 #define DAC_LFSRUnmask_Bits5_0             ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
00133 #define DAC_LFSRUnmask_Bits6_0             ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
00134 #define DAC_LFSRUnmask_Bits7_0             ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
00135 #define DAC_LFSRUnmask_Bits8_0             ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
00136 #define DAC_LFSRUnmask_Bits9_0             ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
00137 #define DAC_LFSRUnmask_Bits10_0            ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
00138 #define DAC_LFSRUnmask_Bits11_0            ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
00139 #define DAC_TriangleAmplitude_1            ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */
00140 #define DAC_TriangleAmplitude_3            ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */
00141 #define DAC_TriangleAmplitude_7            ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */
00142 #define DAC_TriangleAmplitude_15           ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */
00143 #define DAC_TriangleAmplitude_31           ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */
00144 #define DAC_TriangleAmplitude_63           ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */
00145 #define DAC_TriangleAmplitude_127          ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */
00146 #define DAC_TriangleAmplitude_255          ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */
00147 #define DAC_TriangleAmplitude_511          ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */
00148 #define DAC_TriangleAmplitude_1023         ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */
00149 #define DAC_TriangleAmplitude_2047         ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */
00150 #define DAC_TriangleAmplitude_4095         ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */
00151
00152 #define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \
00153                                                       ((VALUE) == DAC_LFSRUnmask_Bits1_0) || \
00154                                                       ((VALUE) == DAC_LFSRUnmask_Bits2_0) || \
00155                                                       ((VALUE) == DAC_LFSRUnmask_Bits3_0) || \
00156                                                       ((VALUE) == DAC_LFSRUnmask_Bits4_0) || \
00157                                                       ((VALUE) == DAC_LFSRUnmask_Bits5_0) || \
00158                                                       ((VALUE) == DAC_LFSRUnmask_Bits6_0) || \
00159                                                       ((VALUE) == DAC_LFSRUnmask_Bits7_0) || \
00160                                                       ((VALUE) == DAC_LFSRUnmask_Bits8_0) || \
00161                                                       ((VALUE) == DAC_LFSRUnmask_Bits9_0) || \
00162                                                       ((VALUE) == DAC_LFSRUnmask_Bits10_0) || \
00163                                                       ((VALUE) == DAC_LFSRUnmask_Bits11_0) || \
00164                                                       ((VALUE) == DAC_TriangleAmplitude_1) || \
00165                                                       ((VALUE) == DAC_TriangleAmplitude_3) || \
00166                                                       ((VALUE) == DAC_TriangleAmplitude_7) || \
00167                                                       ((VALUE) == DAC_TriangleAmplitude_15) || \
00168                                                       ((VALUE) == DAC_TriangleAmplitude_31) || \
00169                                                       ((VALUE) == DAC_TriangleAmplitude_63) || \
00170                                                       ((VALUE) == DAC_TriangleAmplitude_127) || \
00171                                                       ((VALUE) == DAC_TriangleAmplitude_255) || \
00172                                                       ((VALUE) == DAC_TriangleAmplitude_511) || \
00173                                                       ((VALUE) == DAC_TriangleAmplitude_1023) || \
00174                                                       ((VALUE) == DAC_TriangleAmplitude_2047) || \
00175                                                       ((VALUE) == DAC_TriangleAmplitude_4095))
00176 /**
00177   * @}
00178   */
00179
00180 /** @defgroup DAC_output_buffer
00181   * @{
00182   */
00183
00184 #define DAC_OutputBuffer_Enable            ((uint32_t)0x00000000)
00185 #define DAC_OutputBuffer_Disable           ((uint32_t)0x00000002)
00186 #define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \
00187                                            ((STATE) == DAC_OutputBuffer_Disable))
00188 /**
00189   * @}
00190   */
00191
00192 /** @defgroup DAC_Channel_selection
00193   * @{
00194   */
00195
00196 #define DAC_Channel_1                      ((uint32_t)0x00000000)
00197 #define DAC_Channel_2                      ((uint32_t)0x00000010)
00198 #define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \
00199                                  ((CHANNEL) == DAC_Channel_2))
00200 /**
00201   * @}
00202   */
00203
00204 /** @defgroup DAC_data_alignment
00205   * @{
00206   */
00207
00208 #define DAC_Align_12b_R                    ((uint32_t)0x00000000)
00209 #define DAC_Align_12b_L                    ((uint32_t)0x00000004)
00210 #define DAC_Align_8b_R                     ((uint32_t)0x00000008)
00211 #define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \
00212                              ((ALIGN) == DAC_Align_12b_L) || \
00213                              ((ALIGN) == DAC_Align_8b_R))
00214 /**
00215   * @}
00216   */
00217
00218 /** @defgroup DAC_wave_generation
00219   * @{
00220   */
00221
00222 #define DAC_Wave_Noise                     ((uint32_t)0x00000040)
00223 #define DAC_Wave_Triangle                  ((uint32_t)0x00000080)
00224 #define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \
00225                            ((WAVE) == DAC_Wave_Triangle))
00226 /**
00227   * @}
00228   */
00229
00230 /** @defgroup DAC_data
00231   * @{
00232   */
00233
00234 #define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
00235 /**
00236   * @}
00237   */
00238 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL)  || defined (STM32F10X_HD_VL)
00239 /** @defgroup DAC_interrupts_definition
00240   * @{
00241   */
00242
00243 #define DAC_IT_DMAUDR                      ((uint32_t)0x00002000)
00244 #define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR))
00245
00246 /**
00247   * @}
00248   */
00249
00250 /** @defgroup DAC_flags_definition
00251   * @{
00252   */
00253
00254 #define DAC_FLAG_DMAUDR                    ((uint32_t)0x00002000)
00255 #define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR))
00256
00257 /**
00258   * @}
00259   */
00260 #endif
00261
00262 /**
00263   * @}
00264   */
00265
00266 /** @defgroup DAC_Exported_Macros
00267   * @{
00268   */
00269
00270 /**
00271   * @}
00272   */
00273
00274 /** @defgroup DAC_Exported_Functions
00275   * @{
00276   */
00277
00278 void DAC_DeInit(void);
00279 void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct);
00280 void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct);
00281 void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState);
00282 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00283 void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState);
00284 #endif
00285 void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState);
00286 void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState);
00287 void DAC_DualSoftwareTriggerCmd(FunctionalState NewState);
00288 void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState);
00289 void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data);
00290 void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data);
00291 void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1);
00292 uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel);
00293 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00294 FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG);
00295 void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG);
00296 ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT);
00297 void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT);
00298 #endif
00299
00300 #ifdef __cplusplus
00301 }
00302 #endif
00303
00304 #endif /*__STM32F10x_DAC_H */
00305 /**
00306   * @}
00307   */
00308
00309 /**
00310   * @}
00311   */
00312
00313 /**
00314   * @}
00315   */
00316
00317 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_dbgmcu.c Source File

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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Libraries
  • STM32F10x_StdPeriph_Driver
  • src

stm32f10x_dbgmcu.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32f10x_dbgmcu.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    11-March-2011
00007   * @brief   This file provides all the DBGMCU firmware functions.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x_dbgmcu.h"
00024
00025 /** @addtogroup STM32F10x_StdPeriph_Driver
00026   * @{
00027   */
00028
00029 /** @defgroup DBGMCU
00030   * @brief DBGMCU driver modules
00031   * @{
00032   */
00033
00034 /** @defgroup DBGMCU_Private_TypesDefinitions
00035   * @{
00036   */
00037
00038 /**
00039   * @}
00040   */
00041
00042 /** @defgroup DBGMCU_Private_Defines
00043   * @{
00044   */
00045
00046 #define IDCODE_DEVID_MASK    ((uint32_t)0x00000FFF)
00047 /**
00048   * @}
00049   */
00050
00051 /** @defgroup DBGMCU_Private_Macros
00052   * @{
00053   */
00054
00055 /**
00056   * @}
00057   */
00058
00059 /** @defgroup DBGMCU_Private_Variables
00060   * @{
00061   */
00062
00063 /**
00064   * @}
00065   */
00066
00067 /** @defgroup DBGMCU_Private_FunctionPrototypes
00068   * @{
00069   */
00070
00071 /**
00072   * @}
00073   */
00074
00075 /** @defgroup DBGMCU_Private_Functions
00076   * @{
00077   */
00078
00079 /**
00080   * @brief  Returns the device revision identifier.
00081   * @param  None
00082   * @retval Device revision identifier
00083   */
00084 uint32_t DBGMCU_GetREVID(void)
00085 {
00086    return(DBGMCU->IDCODE >> 16);
00087 }
00088
00089 /**
00090   * @brief  Returns the device identifier.
00091   * @param  None
00092   * @retval Device identifier
00093   */
00094 uint32_t DBGMCU_GetDEVID(void)
00095 {
00096    return(DBGMCU->IDCODE & IDCODE_DEVID_MASK);
00097 }
00098
00099 /**
00100   * @brief  Configures the specified peripheral and low power mode behavior
00101   *   when the MCU under Debug mode.
00102   * @param  DBGMCU_Periph: specifies the peripheral and low power mode.
00103   *   This parameter can be any combination of the following values:
00104   *     @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode
00105   *     @arg DBGMCU_STOP: Keep debugger connection during STOP mode
00106   *     @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode
00107   *     @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted
00108   *     @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted
00109   *     @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted
00110   *     @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted
00111   *     @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted
00112   *     @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted
00113   *     @arg DBGMCU_CAN1_STOP: Debug CAN2 stopped when Core is halted
00114   *     @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is halted
00115   *     @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is halted
00116   *     @arg DBGMCU_TIM5_STOP: TIM5 counter stopped when Core is halted
00117   *     @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted
00118   *     @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted
00119   *     @arg DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted
00120   *     @arg DBGMCU_CAN2_STOP: Debug CAN2 stopped when Core is halted
00121   *     @arg DBGMCU_TIM15_STOP: TIM15 counter stopped when Core is halted
00122   *     @arg DBGMCU_TIM16_STOP: TIM16 counter stopped when Core is halted
00123   *     @arg DBGMCU_TIM17_STOP: TIM17 counter stopped when Core is halted
00124   *     @arg DBGMCU_TIM9_STOP: TIM9 counter stopped when Core is halted
00125   *     @arg DBGMCU_TIM10_STOP: TIM10 counter stopped when Core is halted
00126   *     @arg DBGMCU_TIM11_STOP: TIM11 counter stopped when Core is halted
00127   *     @arg DBGMCU_TIM12_STOP: TIM12 counter stopped when Core is halted
00128   *     @arg DBGMCU_TIM13_STOP: TIM13 counter stopped when Core is halted
00129   *     @arg DBGMCU_TIM14_STOP: TIM14 counter stopped when Core is halted
00130   * @param  NewState: new state of the specified peripheral in Debug mode.
00131   *   This parameter can be: ENABLE or DISABLE.
00132   * @retval None
00133   */
00134 void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState)
00135 {
00136   /* Check the parameters */
00137   assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph));
00138   assert_param(IS_FUNCTIONAL_STATE(NewState));
00139
00140   if (NewState != DISABLE)
00141   {
00142     DBGMCU->CR |= DBGMCU_Periph;
00143   }
00144   else
00145   {
00146     DBGMCU->CR &= ~DBGMCU_Periph;
00147   }
00148 }
00149
00150 /**
00151   * @}
00152   */
00153
00154 /**
00155   * @}
00156   */
00157
00158 /**
00159   * @}
00160   */
00161
00162 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_dbgmcu.h Source File

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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Libraries
  • STM32F10x_StdPeriph_Driver
  • inc

stm32f10x_dbgmcu.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32f10x_dbgmcu.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    11-March-2011
00007   * @brief   This file contains all the functions prototypes for the DBGMCU
00008   *          firmware library.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00013   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00014   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00015   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00016   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00017   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00018   *
00019   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00020   ******************************************************************************
00021   */
00022
00023 /* Define to prevent recursive inclusion -------------------------------------*/
00024 #ifndef __STM32F10x_DBGMCU_H
00025 #define __STM32F10x_DBGMCU_H
00026
00027 #ifdef __cplusplus
00028  extern "C" {
00029 #endif
00030
00031 /* Includes ------------------------------------------------------------------*/
00032 #include "stm32f10x.h"
00033
00034 /** @addtogroup STM32F10x_StdPeriph_Driver
00035   * @{
00036   */
00037
00038 /** @addtogroup DBGMCU
00039   * @{
00040   */
00041
00042 /** @defgroup DBGMCU_Exported_Types
00043   * @{
00044   */
00045
00046 /**
00047   * @}
00048   */
00049
00050 /** @defgroup DBGMCU_Exported_Constants
00051   * @{
00052   */
00053
00054 #define DBGMCU_SLEEP                 ((uint32_t)0x00000001)
00055 #define DBGMCU_STOP                  ((uint32_t)0x00000002)
00056 #define DBGMCU_STANDBY               ((uint32_t)0x00000004)
00057 #define DBGMCU_IWDG_STOP             ((uint32_t)0x00000100)
00058 #define DBGMCU_WWDG_STOP             ((uint32_t)0x00000200)
00059 #define DBGMCU_TIM1_STOP             ((uint32_t)0x00000400)
00060 #define DBGMCU_TIM2_STOP             ((uint32_t)0x00000800)
00061 #define DBGMCU_TIM3_STOP             ((uint32_t)0x00001000)
00062 #define DBGMCU_TIM4_STOP             ((uint32_t)0x00002000)
00063 #define DBGMCU_CAN1_STOP             ((uint32_t)0x00004000)
00064 #define DBGMCU_I2C1_SMBUS_TIMEOUT    ((uint32_t)0x00008000)
00065 #define DBGMCU_I2C2_SMBUS_TIMEOUT    ((uint32_t)0x00010000)
00066 #define DBGMCU_TIM8_STOP             ((uint32_t)0x00020000)
00067 #define DBGMCU_TIM5_STOP             ((uint32_t)0x00040000)
00068 #define DBGMCU_TIM6_STOP             ((uint32_t)0x00080000)
00069 #define DBGMCU_TIM7_STOP             ((uint32_t)0x00100000)
00070 #define DBGMCU_CAN2_STOP             ((uint32_t)0x00200000)
00071 #define DBGMCU_TIM15_STOP            ((uint32_t)0x00400000)
00072 #define DBGMCU_TIM16_STOP            ((uint32_t)0x00800000)
00073 #define DBGMCU_TIM17_STOP            ((uint32_t)0x01000000)
00074 #define DBGMCU_TIM12_STOP            ((uint32_t)0x02000000)
00075 #define DBGMCU_TIM13_STOP            ((uint32_t)0x04000000)
00076 #define DBGMCU_TIM14_STOP            ((uint32_t)0x08000000)
00077 #define DBGMCU_TIM9_STOP             ((uint32_t)0x10000000)
00078 #define DBGMCU_TIM10_STOP            ((uint32_t)0x20000000)
00079 #define DBGMCU_TIM11_STOP            ((uint32_t)0x40000000)
00080
00081 #define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0x800000F8) == 0x00) && ((PERIPH) != 0x00))
00082 /**
00083   * @}
00084   */
00085
00086 /** @defgroup DBGMCU_Exported_Macros
00087   * @{
00088   */
00089
00090 /**
00091   * @}
00092   */
00093
00094 /** @defgroup DBGMCU_Exported_Functions
00095   * @{
00096   */
00097
00098 uint32_t DBGMCU_GetREVID(void);
00099 uint32_t DBGMCU_GetDEVID(void);
00100 void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState);
00101
00102 #ifdef __cplusplus
00103 }
00104 #endif
00105
00106 #endif /* __STM32F10x_DBGMCU_H */
00107 /**
00108   * @}
00109   */
00110
00111 /**
00112   * @}
00113   */
00114
00115 /**
00116   * @}
00117   */
00118
00119 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_dma.c Source File

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  • src

stm32f10x_dma.c

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f10x_dma.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    11-March-2011
00007   * @brief   This file provides all the DMA firmware functions.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x_dma.h"
00024 #include "stm32f10x_rcc.h"
00025
00026 /** @addtogroup STM32F10x_StdPeriph_Driver
00027   * @{
00028   */
00029
00030 /** @defgroup DMA
00031   * @brief DMA driver modules
00032   * @{
00033   */
00034
00035 /** @defgroup DMA_Private_TypesDefinitions
00036   * @{
00037   */
00038 /**
00039   * @}
00040   */
00041
00042 /** @defgroup DMA_Private_Defines
00043   * @{
00044   */
00045
00046
00047 /* DMA1 Channelx interrupt pending bit masks */
00048 #define DMA1_Channel1_IT_Mask    ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))
00049 #define DMA1_Channel2_IT_Mask    ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))
00050 #define DMA1_Channel3_IT_Mask    ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))
00051 #define DMA1_Channel4_IT_Mask    ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))
00052 #define DMA1_Channel5_IT_Mask    ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))
00053 #define DMA1_Channel6_IT_Mask    ((uint32_t)(DMA_ISR_GIF6 | DMA_ISR_TCIF6 | DMA_ISR_HTIF6 | DMA_ISR_TEIF6))
00054 #define DMA1_Channel7_IT_Mask    ((uint32_t)(DMA_ISR_GIF7 | DMA_ISR_TCIF7 | DMA_ISR_HTIF7 | DMA_ISR_TEIF7))
00055
00056 /* DMA2 Channelx interrupt pending bit masks */
00057 #define DMA2_Channel1_IT_Mask    ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))
00058 #define DMA2_Channel2_IT_Mask    ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))
00059 #define DMA2_Channel3_IT_Mask    ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))
00060 #define DMA2_Channel4_IT_Mask    ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))
00061 #define DMA2_Channel5_IT_Mask    ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))
00062
00063 /* DMA2 FLAG mask */
00064 #define FLAG_Mask                ((uint32_t)0x10000000)
00065
00066 /* DMA registers Masks */
00067 #define CCR_CLEAR_Mask           ((uint32_t)0xFFFF800F)
00068
00069 /**
00070   * @}
00071   */
00072
00073 /** @defgroup DMA_Private_Macros
00074   * @{
00075   */
00076
00077 /**
00078   * @}
00079   */
00080
00081 /** @defgroup DMA_Private_Variables
00082   * @{
00083   */
00084
00085 /**
00086   * @}
00087   */
00088
00089 /** @defgroup DMA_Private_FunctionPrototypes
00090   * @{
00091   */
00092
00093 /**
00094   * @}
00095   */
00096
00097 /** @defgroup DMA_Private_Functions
00098   * @{
00099   */
00100
00101 /**
00102   * @brief  Deinitializes the DMAy Channelx registers to their default reset
00103   *         values.
00104   * @param  DMAy_Channelx: where y can be 1 or 2 to select the DMA and
00105   *   x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
00106   * @retval None
00107   */
00108 void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx)
00109 {
00110   /* Check the parameters */
00111   assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
00112
00113   /* Disable the selected DMAy Channelx */
00114   DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN);
00115
00116   /* Reset DMAy Channelx control register */
00117   DMAy_Channelx->CCR  = 0;
00118
00119   /* Reset DMAy Channelx remaining bytes register */
00120   DMAy_Channelx->CNDTR = 0;
00121
00122   /* Reset DMAy Channelx peripheral address register */
00123   DMAy_Channelx->CPAR  = 0;
00124
00125   /* Reset DMAy Channelx memory address register */
00126   DMAy_Channelx->CMAR = 0;
00127
00128   if (DMAy_Channelx == DMA1_Channel1)
00129   {
00130     /* Reset interrupt pending bits for DMA1 Channel1 */
00131     DMA1->IFCR |= DMA1_Channel1_IT_Mask;
00132   }
00133   else if (DMAy_Channelx == DMA1_Channel2)
00134   {
00135     /* Reset interrupt pending bits for DMA1 Channel2 */
00136     DMA1->IFCR |= DMA1_Channel2_IT_Mask;
00137   }
00138   else if (DMAy_Channelx == DMA1_Channel3)
00139   {
00140     /* Reset interrupt pending bits for DMA1 Channel3 */
00141     DMA1->IFCR |= DMA1_Channel3_IT_Mask;
00142   }
00143   else if (DMAy_Channelx == DMA1_Channel4)
00144   {
00145     /* Reset interrupt pending bits for DMA1 Channel4 */
00146     DMA1->IFCR |= DMA1_Channel4_IT_Mask;
00147   }
00148   else if (DMAy_Channelx == DMA1_Channel5)
00149   {
00150     /* Reset interrupt pending bits for DMA1 Channel5 */
00151     DMA1->IFCR |= DMA1_Channel5_IT_Mask;
00152   }
00153   else if (DMAy_Channelx == DMA1_Channel6)
00154   {
00155     /* Reset interrupt pending bits for DMA1 Channel6 */
00156     DMA1->IFCR |= DMA1_Channel6_IT_Mask;
00157   }
00158   else if (DMAy_Channelx == DMA1_Channel7)
00159   {
00160     /* Reset interrupt pending bits for DMA1 Channel7 */
00161     DMA1->IFCR |= DMA1_Channel7_IT_Mask;
00162   }
00163   else if (DMAy_Channelx == DMA2_Channel1)
00164   {
00165     /* Reset interrupt pending bits for DMA2 Channel1 */
00166     DMA2->IFCR |= DMA2_Channel1_IT_Mask;
00167   }
00168   else if (DMAy_Channelx == DMA2_Channel2)
00169   {
00170     /* Reset interrupt pending bits for DMA2 Channel2 */
00171     DMA2->IFCR |= DMA2_Channel2_IT_Mask;
00172   }
00173   else if (DMAy_Channelx == DMA2_Channel3)
00174   {
00175     /* Reset interrupt pending bits for DMA2 Channel3 */
00176     DMA2->IFCR |= DMA2_Channel3_IT_Mask;
00177   }
00178   else if (DMAy_Channelx == DMA2_Channel4)
00179   {
00180     /* Reset interrupt pending bits for DMA2 Channel4 */
00181     DMA2->IFCR |= DMA2_Channel4_IT_Mask;
00182   }
00183   else
00184   {
00185     if (DMAy_Channelx == DMA2_Channel5)
00186     {
00187       /* Reset interrupt pending bits for DMA2 Channel5 */
00188       DMA2->IFCR |= DMA2_Channel5_IT_Mask;
00189     }
00190   }
00191 }
00192
00193 /**
00194   * @brief  Initializes the DMAy Channelx according to the specified
00195   *         parameters in the DMA_InitStruct.
00196   * @param  DMAy_Channelx: where y can be 1 or 2 to select the DMA and
00197   *   x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
00198   * @param  DMA_InitStruct: pointer to a DMA_InitTypeDef structure that
00199   *         contains the configuration information for the specified DMA Channel.
00200   * @retval None
00201   */
00202 void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct)
00203 {
00204   uint32_t tmpreg = 0;
00205
00206   /* Check the parameters */
00207   assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
00208   assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR));
00209   assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize));
00210   assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc));
00211   assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc));
00212   assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize));
00213   assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize));
00214   assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));
00215   assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));
00216   assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M));
00217
00218 /*--------------------------- DMAy Channelx CCR Configuration -----------------*/
00219   /* Get the DMAy_Channelx CCR value */
00220   tmpreg = DMAy_Channelx->CCR;
00221   /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
00222   tmpreg &= CCR_CLEAR_Mask;
00223   /* Configure DMAy Channelx: data transfer, data size, priority level and mode */
00224   /* Set DIR bit according to DMA_DIR value */
00225   /* Set CIRC bit according to DMA_Mode value */
00226   /* Set PINC bit according to DMA_PeripheralInc value */
00227   /* Set MINC bit according to DMA_MemoryInc value */
00228   /* Set PSIZE bits according to DMA_PeripheralDataSize value */
00229   /* Set MSIZE bits according to DMA_MemoryDataSize value */
00230   /* Set PL bits according to DMA_Priority value */
00231   /* Set the MEM2MEM bit according to DMA_M2M value */
00232   tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |
00233             DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
00234             DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
00235             DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;
00236
00237   /* Write to DMAy Channelx CCR */
00238   DMAy_Channelx->CCR = tmpreg;
00239
00240 /*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/
00241   /* Write to DMAy Channelx CNDTR */
00242   DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize;
00243
00244 /*--------------------------- DMAy Channelx CPAR Configuration ----------------*/
00245   /* Write to DMAy Channelx CPAR */
00246   DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr;
00247
00248 /*--------------------------- DMAy Channelx CMAR Configuration ----------------*/
00249   /* Write to DMAy Channelx CMAR */
00250   DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr;
00251 }
00252
00253 /**
00254   * @brief  Fills each DMA_InitStruct member with its default value.
00255   * @param  DMA_InitStruct : pointer to a DMA_InitTypeDef structure which will
00256   *         be initialized.
00257   * @retval None
00258   */
00259 void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)
00260 {
00261 /*-------------- Reset DMA init structure parameters values ------------------*/
00262   /* Initialize the DMA_PeripheralBaseAddr member */
00263   DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
00264   /* Initialize the DMA_MemoryBaseAddr member */
00265   DMA_InitStruct->DMA_MemoryBaseAddr = 0;
00266   /* Initialize the DMA_DIR member */
00267   DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;
00268   /* Initialize the DMA_BufferSize member */
00269   DMA_InitStruct->DMA_BufferSize = 0;
00270   /* Initialize the DMA_PeripheralInc member */
00271   DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
00272   /* Initialize the DMA_MemoryInc member */
00273   DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
00274   /* Initialize the DMA_PeripheralDataSize member */
00275   DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
00276   /* Initialize the DMA_MemoryDataSize member */
00277   DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
00278   /* Initialize the DMA_Mode member */
00279   DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
00280   /* Initialize the DMA_Priority member */
00281   DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
00282   /* Initialize the DMA_M2M member */
00283   DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;
00284 }
00285
00286 /**
00287   * @brief  Enables or disables the specified DMAy Channelx.
00288   * @param  DMAy_Channelx: where y can be 1 or 2 to select the DMA and
00289   *   x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
00290   * @param  NewState: new state of the DMAy Channelx.
00291   *   This parameter can be: ENABLE or DISABLE.
00292   * @retval None
00293   */
00294 void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState)
00295 {
00296   /* Check the parameters */
00297   assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
00298   assert_param(IS_FUNCTIONAL_STATE(NewState));
00299
00300   if (NewState != DISABLE)
00301   {
00302     /* Enable the selected DMAy Channelx */
00303     DMAy_Channelx->CCR |= DMA_CCR1_EN;
00304   }
00305   else
00306   {
00307     /* Disable the selected DMAy Channelx */
00308     DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN);
00309   }
00310 }
00311
00312 /**
00313   * @brief  Enables or disables the specified DMAy Channelx interrupts.
00314   * @param  DMAy_Channelx: where y can be 1 or 2 to select the DMA and
00315   *   x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
00316   * @param  DMA_IT: specifies the DMA interrupts sources to be enabled
00317   *   or disabled.
00318   *   This parameter can be any combination of the following values:
00319   *     @arg DMA_IT_TC:  Transfer complete interrupt mask
00320   *     @arg DMA_IT_HT:  Half transfer interrupt mask
00321   *     @arg DMA_IT_TE:  Transfer error interrupt mask
00322   * @param  NewState: new state of the specified DMA interrupts.
00323   *   This parameter can be: ENABLE or DISABLE.
00324   * @retval None
00325   */
00326 void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)
00327 {
00328   /* Check the parameters */
00329   assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
00330   assert_param(IS_DMA_CONFIG_IT(DMA_IT));
00331   assert_param(IS_FUNCTIONAL_STATE(NewState));
00332   if (NewState != DISABLE)
00333   {
00334     /* Enable the selected DMA interrupts */
00335     DMAy_Channelx->CCR |= DMA_IT;
00336   }
00337   else
00338   {
00339     /* Disable the selected DMA interrupts */
00340     DMAy_Channelx->CCR &= ~DMA_IT;
00341   }
00342 }
00343
00344 /**
00345   * @brief  Sets the number of data units in the current DMAy Channelx transfer.
00346   * @param  DMAy_Channelx: where y can be 1 or 2 to select the DMA and
00347   *         x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
00348   * @param  DataNumber: The number of data units in the current DMAy Channelx
00349   *         transfer.
00350   * @note   This function can only be used when the DMAy_Channelx is disabled.
00351   * @retval None.
00352   */
00353 void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber)
00354 {
00355   /* Check the parameters */
00356   assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
00357
00358 /*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/
00359   /* Write to DMAy Channelx CNDTR */
00360   DMAy_Channelx->CNDTR = DataNumber;
00361 }
00362
00363 /**
00364   * @brief  Returns the number of remaining data units in the current
00365   *         DMAy Channelx transfer.
00366   * @param  DMAy_Channelx: where y can be 1 or 2 to select the DMA and
00367   *   x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
00368   * @retval The number of remaining data units in the current DMAy Channelx
00369   *         transfer.
00370   */
00371 uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx)
00372 {
00373   /* Check the parameters */
00374   assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
00375   /* Return the number of remaining data units for DMAy Channelx */
00376   return ((uint16_t)(DMAy_Channelx->CNDTR));
00377 }
00378
00379 /**
00380   * @brief  Checks whether the specified DMAy Channelx flag is set or not.
00381   * @param  DMAy_FLAG: specifies the flag to check.
00382   *   This parameter can be one of the following values:
00383   *     @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
00384   *     @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
00385   *     @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
00386   *     @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
00387   *     @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
00388   *     @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
00389   *     @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
00390   *     @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
00391   *     @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
00392   *     @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
00393   *     @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
00394   *     @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
00395   *     @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
00396   *     @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
00397   *     @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
00398   *     @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
00399   *     @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
00400   *     @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
00401   *     @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
00402   *     @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
00403   *     @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.
00404   *     @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
00405   *     @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
00406   *     @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
00407   *     @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.
00408   *     @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
00409   *     @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
00410   *     @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
00411   *     @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.
00412   *     @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
00413   *     @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
00414   *     @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
00415   *     @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.
00416   *     @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
00417   *     @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
00418   *     @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
00419   *     @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.
00420   *     @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
00421   *     @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
00422   *     @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
00423   *     @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.
00424   *     @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
00425   *     @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
00426   *     @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
00427   *     @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.
00428   *     @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
00429   *     @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
00430   *     @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
00431   * @retval The new state of DMAy_FLAG (SET or RESET).
00432   */
00433 FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG)
00434 {
00435   FlagStatus bitstatus = RESET;
00436   uint32_t tmpreg = 0;
00437
00438   /* Check the parameters */
00439   assert_param(IS_DMA_GET_FLAG(DMAy_FLAG));
00440
00441   /* Calculate the used DMAy */
00442   if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET)
00443   {
00444     /* Get DMA2 ISR register value */
00445     tmpreg = DMA2->ISR ;
00446   }
00447   else
00448   {
00449     /* Get DMA1 ISR register value */
00450     tmpreg = DMA1->ISR ;
00451   }
00452
00453   /* Check the status of the specified DMAy flag */
00454   if ((tmpreg & DMAy_FLAG) != (uint32_t)RESET)
00455   {
00456     /* DMAy_FLAG is set */
00457     bitstatus = SET;
00458   }
00459   else
00460   {
00461     /* DMAy_FLAG is reset */
00462     bitstatus = RESET;
00463   }
00464
00465   /* Return the DMAy_FLAG status */
00466   return  bitstatus;
00467 }
00468
00469 /**
00470   * @brief  Clears the DMAy Channelx's pending flags.
00471   * @param  DMAy_FLAG: specifies the flag to clear.
00472   *   This parameter can be any combination (for the same DMA) of the following values:
00473   *     @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
00474   *     @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
00475   *     @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
00476   *     @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
00477   *     @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
00478   *     @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
00479   *     @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
00480   *     @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
00481   *     @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
00482   *     @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
00483   *     @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
00484   *     @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
00485   *     @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
00486   *     @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
00487   *     @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
00488   *     @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
00489   *     @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
00490   *     @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
00491   *     @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
00492   *     @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
00493   *     @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.
00494   *     @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
00495   *     @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
00496   *     @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
00497   *     @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.
00498   *     @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
00499   *     @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
00500   *     @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
00501   *     @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.
00502   *     @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
00503   *     @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
00504   *     @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
00505   *     @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.
00506   *     @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
00507   *     @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
00508   *     @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
00509   *     @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.
00510   *     @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
00511   *     @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
00512   *     @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
00513   *     @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.
00514   *     @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
00515   *     @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
00516   *     @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
00517   *     @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.
00518   *     @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
00519   *     @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
00520   *     @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
00521   * @retval None
00522   */
00523 void DMA_ClearFlag(uint32_t DMAy_FLAG)
00524 {
00525   /* Check the parameters */
00526   assert_param(IS_DMA_CLEAR_FLAG(DMAy_FLAG));
00527
00528   /* Calculate the used DMAy */
00529   if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET)
00530   {
00531     /* Clear the selected DMAy flags */
00532     DMA2->IFCR = DMAy_FLAG;
00533   }
00534   else
00535   {
00536     /* Clear the selected DMAy flags */
00537     DMA1->IFCR = DMAy_FLAG;
00538   }
00539 }
00540
00541 /**
00542   * @brief  Checks whether the specified DMAy Channelx interrupt has occurred or not.
00543   * @param  DMAy_IT: specifies the DMAy interrupt source to check.
00544   *   This parameter can be one of the following values:
00545   *     @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
00546   *     @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
00547   *     @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
00548   *     @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
00549   *     @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
00550   *     @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
00551   *     @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
00552   *     @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
00553   *     @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
00554   *     @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
00555   *     @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
00556   *     @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
00557   *     @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
00558   *     @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
00559   *     @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
00560   *     @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
00561   *     @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
00562   *     @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
00563   *     @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
00564   *     @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
00565   *     @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.
00566   *     @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
00567   *     @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
00568   *     @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
00569   *     @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.
00570   *     @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
00571   *     @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
00572   *     @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
00573   *     @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt.
00574   *     @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.
00575   *     @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.
00576   *     @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.
00577   *     @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt.
00578   *     @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.
00579   *     @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.
00580   *     @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.
00581   *     @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt.
00582   *     @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.
00583   *     @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.
00584   *     @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.
00585   *     @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt.
00586   *     @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.
00587   *     @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.
00588   *     @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.
00589   *     @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt.
00590   *     @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.
00591   *     @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.
00592   *     @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
00593   * @retval The new state of DMAy_IT (SET or RESET).
00594   */
00595 ITStatus DMA_GetITStatus(uint32_t DMAy_IT)
00596 {
00597   ITStatus bitstatus = RESET;
00598   uint32_t tmpreg = 0;
00599
00600   /* Check the parameters */
00601   assert_param(IS_DMA_GET_IT(DMAy_IT));
00602
00603   /* Calculate the used DMA */
00604   if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET)
00605   {
00606     /* Get DMA2 ISR register value */
00607     tmpreg = DMA2->ISR;
00608   }
00609   else
00610   {
00611     /* Get DMA1 ISR register value */
00612     tmpreg = DMA1->ISR;
00613   }
00614
00615   /* Check the status of the specified DMAy interrupt */
00616   if ((tmpreg & DMAy_IT) != (uint32_t)RESET)
00617   {
00618     /* DMAy_IT is set */
00619     bitstatus = SET;
00620   }
00621   else
00622   {
00623     /* DMAy_IT is reset */
00624     bitstatus = RESET;
00625   }
00626   /* Return the DMA_IT status */
00627   return  bitstatus;
00628 }
00629
00630 /**
00631   * @brief  Clears the DMAy Channelx's interrupt pending bits.
00632   * @param  DMAy_IT: specifies the DMAy interrupt pending bit to clear.
00633   *   This parameter can be any combination (for the same DMA) of the following values:
00634   *     @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
00635   *     @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
00636   *     @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
00637   *     @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
00638   *     @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
00639   *     @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
00640   *     @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
00641   *     @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
00642   *     @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
00643   *     @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
00644   *     @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
00645   *     @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
00646   *     @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
00647   *     @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
00648   *     @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
00649   *     @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
00650   *     @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
00651   *     @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
00652   *     @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
00653   *     @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
00654   *     @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.
00655   *     @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
00656   *     @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
00657   *     @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
00658   *     @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.
00659   *     @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
00660   *     @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
00661   *     @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
00662   *     @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt.
00663   *     @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.
00664   *     @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.
00665   *     @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.
00666   *     @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt.
00667   *     @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.
00668   *     @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.
00669   *     @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.
00670   *     @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt.
00671   *     @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.
00672   *     @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.
00673   *     @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.
00674   *     @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt.
00675   *     @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.
00676   *     @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.
00677   *     @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.
00678   *     @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt.
00679   *     @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.
00680   *     @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.
00681   *     @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
00682   * @retval None
00683   */
00684 void DMA_ClearITPendingBit(uint32_t DMAy_IT)
00685 {
00686   /* Check the parameters */
00687   assert_param(IS_DMA_CLEAR_IT(DMAy_IT));
00688
00689   /* Calculate the used DMAy */
00690   if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET)
00691   {
00692     /* Clear the selected DMAy interrupt pending bits */
00693     DMA2->IFCR = DMAy_IT;
00694   }
00695   else
00696   {
00697     /* Clear the selected DMAy interrupt pending bits */
00698     DMA1->IFCR = DMAy_IT;
00699   }
00700 }
00701
00702 /**
00703   * @}
00704   */
00705
00706 /**
00707   * @}
00708   */
00709
00710 /**
00711   * @}
00712   */
00713
00714 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_dma.h Source File

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stm32f10x_dma.h

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f10x_dma.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    11-March-2011
00007   * @brief   This file contains all the functions prototypes for the DMA firmware
00008   *          library.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00013   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00014   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00015   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00016   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00017   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00018   *
00019   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00020   ******************************************************************************
00021   */
00022
00023 /* Define to prevent recursive inclusion -------------------------------------*/
00024 #ifndef __STM32F10x_DMA_H
00025 #define __STM32F10x_DMA_H
00026
00027 #ifdef __cplusplus
00028  extern "C" {
00029 #endif
00030
00031 /* Includes ------------------------------------------------------------------*/
00032 #include "stm32f10x.h"
00033
00034 /** @addtogroup STM32F10x_StdPeriph_Driver
00035   * @{
00036   */
00037
00038 /** @addtogroup DMA
00039   * @{
00040   */
00041
00042 /** @defgroup DMA_Exported_Types
00043   * @{
00044   */
00045
00046 /**
00047   * @brief  DMA Init structure definition
00048   */
00049
00050 typedef struct
00051 {
00052   uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */
00053
00054   uint32_t DMA_MemoryBaseAddr;     /*!< Specifies the memory base address for DMAy Channelx. */
00055
00056   uint32_t DMA_DIR;                /*!< Specifies if the peripheral is the source or destination.
00057                                         This parameter can be a value of @ref DMA_data_transfer_direction */
00058
00059   uint32_t DMA_BufferSize;         /*!< Specifies the buffer size, in data unit, of the specified Channel.
00060                                         The data unit is equal to the configuration set in DMA_PeripheralDataSize
00061                                         or DMA_MemoryDataSize members depending in the transfer direction. */
00062
00063   uint32_t DMA_PeripheralInc;      /*!< Specifies whether the Peripheral address register is incremented or not.
00064                                         This parameter can be a value of @ref DMA_peripheral_incremented_mode */
00065
00066   uint32_t DMA_MemoryInc;          /*!< Specifies whether the memory address register is incremented or not.
00067                                         This parameter can be a value of @ref DMA_memory_incremented_mode */
00068
00069   uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width.
00070                                         This parameter can be a value of @ref DMA_peripheral_data_size */
00071
00072   uint32_t DMA_MemoryDataSize;     /*!< Specifies the Memory data width.
00073                                         This parameter can be a value of @ref DMA_memory_data_size */
00074
00075   uint32_t DMA_Mode;               /*!< Specifies the operation mode of the DMAy Channelx.
00076                                         This parameter can be a value of @ref DMA_circular_normal_mode.
00077                                         @note: The circular buffer mode cannot be used if the memory-to-memory
00078                                               data transfer is configured on the selected Channel */
00079
00080   uint32_t DMA_Priority;           /*!< Specifies the software priority for the DMAy Channelx.
00081                                         This parameter can be a value of @ref DMA_priority_level */
00082
00083   uint32_t DMA_M2M;                /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer.
00084                                         This parameter can be a value of @ref DMA_memory_to_memory */
00085 }DMA_InitTypeDef;
00086
00087 /**
00088   * @}
00089   */
00090
00091 /** @defgroup DMA_Exported_Constants
00092   * @{
00093   */
00094
00095 #define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \
00096                                    ((PERIPH) == DMA1_Channel2) || \
00097                                    ((PERIPH) == DMA1_Channel3) || \
00098                                    ((PERIPH) == DMA1_Channel4) || \
00099                                    ((PERIPH) == DMA1_Channel5) || \
00100                                    ((PERIPH) == DMA1_Channel6) || \
00101                                    ((PERIPH) == DMA1_Channel7) || \
00102                                    ((PERIPH) == DMA2_Channel1) || \
00103                                    ((PERIPH) == DMA2_Channel2) || \
00104                                    ((PERIPH) == DMA2_Channel3) || \
00105                                    ((PERIPH) == DMA2_Channel4) || \
00106                                    ((PERIPH) == DMA2_Channel5))
00107
00108 /** @defgroup DMA_data_transfer_direction
00109   * @{
00110   */
00111
00112 #define DMA_DIR_PeripheralDST              ((uint32_t)0x00000010)
00113 #define DMA_DIR_PeripheralSRC              ((uint32_t)0x00000000)
00114 #define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralDST) || \
00115                          ((DIR) == DMA_DIR_PeripheralSRC))
00116 /**
00117   * @}
00118   */
00119
00120 /** @defgroup DMA_peripheral_incremented_mode
00121   * @{
00122   */
00123
00124 #define DMA_PeripheralInc_Enable           ((uint32_t)0x00000040)
00125 #define DMA_PeripheralInc_Disable          ((uint32_t)0x00000000)
00126 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \
00127                                             ((STATE) == DMA_PeripheralInc_Disable))
00128 /**
00129   * @}
00130   */
00131
00132 /** @defgroup DMA_memory_incremented_mode
00133   * @{
00134   */
00135
00136 #define DMA_MemoryInc_Enable               ((uint32_t)0x00000080)
00137 #define DMA_MemoryInc_Disable              ((uint32_t)0x00000000)
00138 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \
00139                                         ((STATE) == DMA_MemoryInc_Disable))
00140 /**
00141   * @}
00142   */
00143
00144 /** @defgroup DMA_peripheral_data_size
00145   * @{
00146   */
00147
00148 #define DMA_PeripheralDataSize_Byte        ((uint32_t)0x00000000)
00149 #define DMA_PeripheralDataSize_HalfWord    ((uint32_t)0x00000100)
00150 #define DMA_PeripheralDataSize_Word        ((uint32_t)0x00000200)
00151 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \
00152                                            ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \
00153                                            ((SIZE) == DMA_PeripheralDataSize_Word))
00154 /**
00155   * @}
00156   */
00157
00158 /** @defgroup DMA_memory_data_size
00159   * @{
00160   */
00161
00162 #define DMA_MemoryDataSize_Byte            ((uint32_t)0x00000000)
00163 #define DMA_MemoryDataSize_HalfWord        ((uint32_t)0x00000400)
00164 #define DMA_MemoryDataSize_Word            ((uint32_t)0x00000800)
00165 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \
00166                                        ((SIZE) == DMA_MemoryDataSize_HalfWord) || \
00167                                        ((SIZE) == DMA_MemoryDataSize_Word))
00168 /**
00169   * @}
00170   */
00171
00172 /** @defgroup DMA_circular_normal_mode
00173   * @{
00174   */
00175
00176 #define DMA_Mode_Circular                  ((uint32_t)0x00000020)
00177 #define DMA_Mode_Normal                    ((uint32_t)0x00000000)
00178 #define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Circular) || ((MODE) == DMA_Mode_Normal))
00179 /**
00180   * @}
00181   */
00182
00183 /** @defgroup DMA_priority_level
00184   * @{
00185   */
00186
00187 #define DMA_Priority_VeryHigh              ((uint32_t)0x00003000)
00188 #define DMA_Priority_High                  ((uint32_t)0x00002000)
00189 #define DMA_Priority_Medium                ((uint32_t)0x00001000)
00190 #define DMA_Priority_Low                   ((uint32_t)0x00000000)
00191 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \
00192                                    ((PRIORITY) == DMA_Priority_High) || \
00193                                    ((PRIORITY) == DMA_Priority_Medium) || \
00194                                    ((PRIORITY) == DMA_Priority_Low))
00195 /**
00196   * @}
00197   */
00198
00199 /** @defgroup DMA_memory_to_memory
00200   * @{
00201   */
00202
00203 #define DMA_M2M_Enable                     ((uint32_t)0x00004000)
00204 #define DMA_M2M_Disable                    ((uint32_t)0x00000000)
00205 #define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Enable) || ((STATE) == DMA_M2M_Disable))
00206
00207 /**
00208   * @}
00209   */
00210
00211 /** @defgroup DMA_interrupts_definition
00212   * @{
00213   */
00214
00215 #define DMA_IT_TC                          ((uint32_t)0x00000002)
00216 #define DMA_IT_HT                          ((uint32_t)0x00000004)
00217 #define DMA_IT_TE                          ((uint32_t)0x00000008)
00218 #define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00))
00219
00220 #define DMA1_IT_GL1                        ((uint32_t)0x00000001)
00221 #define DMA1_IT_TC1                        ((uint32_t)0x00000002)
00222 #define DMA1_IT_HT1                        ((uint32_t)0x00000004)
00223 #define DMA1_IT_TE1                        ((uint32_t)0x00000008)
00224 #define DMA1_IT_GL2                        ((uint32_t)0x00000010)
00225 #define DMA1_IT_TC2                        ((uint32_t)0x00000020)
00226 #define DMA1_IT_HT2                        ((uint32_t)0x00000040)
00227 #define DMA1_IT_TE2                        ((uint32_t)0x00000080)
00228 #define DMA1_IT_GL3                        ((uint32_t)0x00000100)
00229 #define DMA1_IT_TC3                        ((uint32_t)0x00000200)
00230 #define DMA1_IT_HT3                        ((uint32_t)0x00000400)
00231 #define DMA1_IT_TE3                        ((uint32_t)0x00000800)
00232 #define DMA1_IT_GL4                        ((uint32_t)0x00001000)
00233 #define DMA1_IT_TC4                        ((uint32_t)0x00002000)
00234 #define DMA1_IT_HT4                        ((uint32_t)0x00004000)
00235 #define DMA1_IT_TE4                        ((uint32_t)0x00008000)
00236 #define DMA1_IT_GL5                        ((uint32_t)0x00010000)
00237 #define DMA1_IT_TC5                        ((uint32_t)0x00020000)
00238 #define DMA1_IT_HT5                        ((uint32_t)0x00040000)
00239 #define DMA1_IT_TE5                        ((uint32_t)0x00080000)
00240 #define DMA1_IT_GL6                        ((uint32_t)0x00100000)
00241 #define DMA1_IT_TC6                        ((uint32_t)0x00200000)
00242 #define DMA1_IT_HT6                        ((uint32_t)0x00400000)
00243 #define DMA1_IT_TE6                        ((uint32_t)0x00800000)
00244 #define DMA1_IT_GL7                        ((uint32_t)0x01000000)
00245 #define DMA1_IT_TC7                        ((uint32_t)0x02000000)
00246 #define DMA1_IT_HT7                        ((uint32_t)0x04000000)
00247 #define DMA1_IT_TE7                        ((uint32_t)0x08000000)
00248
00249 #define DMA2_IT_GL1                        ((uint32_t)0x10000001)
00250 #define DMA2_IT_TC1                        ((uint32_t)0x10000002)
00251 #define DMA2_IT_HT1                        ((uint32_t)0x10000004)
00252 #define DMA2_IT_TE1                        ((uint32_t)0x10000008)
00253 #define DMA2_IT_GL2                        ((uint32_t)0x10000010)
00254 #define DMA2_IT_TC2                        ((uint32_t)0x10000020)
00255 #define DMA2_IT_HT2                        ((uint32_t)0x10000040)
00256 #define DMA2_IT_TE2                        ((uint32_t)0x10000080)
00257 #define DMA2_IT_GL3                        ((uint32_t)0x10000100)
00258 #define DMA2_IT_TC3                        ((uint32_t)0x10000200)
00259 #define DMA2_IT_HT3                        ((uint32_t)0x10000400)
00260 #define DMA2_IT_TE3                        ((uint32_t)0x10000800)
00261 #define DMA2_IT_GL4                        ((uint32_t)0x10001000)
00262 #define DMA2_IT_TC4                        ((uint32_t)0x10002000)
00263 #define DMA2_IT_HT4                        ((uint32_t)0x10004000)
00264 #define DMA2_IT_TE4                        ((uint32_t)0x10008000)
00265 #define DMA2_IT_GL5                        ((uint32_t)0x10010000)
00266 #define DMA2_IT_TC5                        ((uint32_t)0x10020000)
00267 #define DMA2_IT_HT5                        ((uint32_t)0x10040000)
00268 #define DMA2_IT_TE5                        ((uint32_t)0x10080000)
00269
00270 #define IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00))
00271
00272 #define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \
00273                            ((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \
00274                            ((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \
00275                            ((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \
00276                            ((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \
00277                            ((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \
00278                            ((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \
00279                            ((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \
00280                            ((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \
00281                            ((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \
00282                            ((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \
00283                            ((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \
00284                            ((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \
00285                            ((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7) || \
00286                            ((IT) == DMA2_IT_GL1) || ((IT) == DMA2_IT_TC1) || \
00287                            ((IT) == DMA2_IT_HT1) || ((IT) == DMA2_IT_TE1) || \
00288                            ((IT) == DMA2_IT_GL2) || ((IT) == DMA2_IT_TC2) || \
00289                            ((IT) == DMA2_IT_HT2) || ((IT) == DMA2_IT_TE2) || \
00290                            ((IT) == DMA2_IT_GL3) || ((IT) == DMA2_IT_TC3) || \
00291                            ((IT) == DMA2_IT_HT3) || ((IT) == DMA2_IT_TE3) || \
00292                            ((IT) == DMA2_IT_GL4) || ((IT) == DMA2_IT_TC4) || \
00293                            ((IT) == DMA2_IT_HT4) || ((IT) == DMA2_IT_TE4) || \
00294                            ((IT) == DMA2_IT_GL5) || ((IT) == DMA2_IT_TC5) || \
00295                            ((IT) == DMA2_IT_HT5) || ((IT) == DMA2_IT_TE5))
00296
00297 /**
00298   * @}
00299   */
00300
00301 /** @defgroup DMA_flags_definition
00302   * @{
00303   */
00304 #define DMA1_FLAG_GL1                      ((uint32_t)0x00000001)
00305 #define DMA1_FLAG_TC1                      ((uint32_t)0x00000002)
00306 #define DMA1_FLAG_HT1                      ((uint32_t)0x00000004)
00307 #define DMA1_FLAG_TE1                      ((uint32_t)0x00000008)
00308 #define DMA1_FLAG_GL2                      ((uint32_t)0x00000010)
00309 #define DMA1_FLAG_TC2                      ((uint32_t)0x00000020)
00310 #define DMA1_FLAG_HT2                      ((uint32_t)0x00000040)
00311 #define DMA1_FLAG_TE2                      ((uint32_t)0x00000080)
00312 #define DMA1_FLAG_GL3                      ((uint32_t)0x00000100)
00313 #define DMA1_FLAG_TC3                      ((uint32_t)0x00000200)
00314 #define DMA1_FLAG_HT3                      ((uint32_t)0x00000400)
00315 #define DMA1_FLAG_TE3                      ((uint32_t)0x00000800)
00316 #define DMA1_FLAG_GL4                      ((uint32_t)0x00001000)
00317 #define DMA1_FLAG_TC4                      ((uint32_t)0x00002000)
00318 #define DMA1_FLAG_HT4                      ((uint32_t)0x00004000)
00319 #define DMA1_FLAG_TE4                      ((uint32_t)0x00008000)
00320 #define DMA1_FLAG_GL5                      ((uint32_t)0x00010000)
00321 #define DMA1_FLAG_TC5                      ((uint32_t)0x00020000)
00322 #define DMA1_FLAG_HT5                      ((uint32_t)0x00040000)
00323 #define DMA1_FLAG_TE5                      ((uint32_t)0x00080000)
00324 #define DMA1_FLAG_GL6                      ((uint32_t)0x00100000)
00325 #define DMA1_FLAG_TC6                      ((uint32_t)0x00200000)
00326 #define DMA1_FLAG_HT6                      ((uint32_t)0x00400000)
00327 #define DMA1_FLAG_TE6                      ((uint32_t)0x00800000)
00328 #define DMA1_FLAG_GL7                      ((uint32_t)0x01000000)
00329 #define DMA1_FLAG_TC7                      ((uint32_t)0x02000000)
00330 #define DMA1_FLAG_HT7                      ((uint32_t)0x04000000)
00331 #define DMA1_FLAG_TE7                      ((uint32_t)0x08000000)
00332
00333 #define DMA2_FLAG_GL1                      ((uint32_t)0x10000001)
00334 #define DMA2_FLAG_TC1                      ((uint32_t)0x10000002)
00335 #define DMA2_FLAG_HT1                      ((uint32_t)0x10000004)
00336 #define DMA2_FLAG_TE1                      ((uint32_t)0x10000008)
00337 #define DMA2_FLAG_GL2                      ((uint32_t)0x10000010)
00338 #define DMA2_FLAG_TC2                      ((uint32_t)0x10000020)
00339 #define DMA2_FLAG_HT2                      ((uint32_t)0x10000040)
00340 #define DMA2_FLAG_TE2                      ((uint32_t)0x10000080)
00341 #define DMA2_FLAG_GL3                      ((uint32_t)0x10000100)
00342 #define DMA2_FLAG_TC3                      ((uint32_t)0x10000200)
00343 #define DMA2_FLAG_HT3                      ((uint32_t)0x10000400)
00344 #define DMA2_FLAG_TE3                      ((uint32_t)0x10000800)
00345 #define DMA2_FLAG_GL4                      ((uint32_t)0x10001000)
00346 #define DMA2_FLAG_TC4                      ((uint32_t)0x10002000)
00347 #define DMA2_FLAG_HT4                      ((uint32_t)0x10004000)
00348 #define DMA2_FLAG_TE4                      ((uint32_t)0x10008000)
00349 #define DMA2_FLAG_GL5                      ((uint32_t)0x10010000)
00350 #define DMA2_FLAG_TC5                      ((uint32_t)0x10020000)
00351 #define DMA2_FLAG_HT5                      ((uint32_t)0x10040000)
00352 #define DMA2_FLAG_TE5                      ((uint32_t)0x10080000)
00353
00354 #define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00))
00355
00356 #define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \
00357                                ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \
00358                                ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \
00359                                ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \
00360                                ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \
00361                                ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \
00362                                ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \
00363                                ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \
00364                                ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \
00365                                ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \
00366                                ((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \
00367                                ((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \
00368                                ((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \
00369                                ((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7) || \
00370                                ((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) || \
00371                                ((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_TE1) || \
00372                                ((FLAG) == DMA2_FLAG_GL2) || ((FLAG) == DMA2_FLAG_TC2) || \
00373                                ((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_TE2) || \
00374                                ((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || \
00375                                ((FLAG) == DMA2_FLAG_HT3) || ((FLAG) == DMA2_FLAG_TE3) || \
00376                                ((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) || \
00377                                ((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || \
00378                                ((FLAG) == DMA2_FLAG_GL5) || ((FLAG) == DMA2_FLAG_TC5) || \
00379                                ((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5))
00380 /**
00381   * @}
00382   */
00383
00384 /** @defgroup DMA_Buffer_Size
00385   * @{
00386   */
00387
00388 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
00389
00390 /**
00391   * @}
00392   */
00393
00394 /**
00395   * @}
00396   */
00397
00398 /** @defgroup DMA_Exported_Macros
00399   * @{
00400   */
00401
00402 /**
00403   * @}
00404   */
00405
00406 /** @defgroup DMA_Exported_Functions
00407   * @{
00408   */
00409
00410 void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx);
00411 void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct);
00412 void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
00413 void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState);
00414 void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);
00415 void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber);
00416 uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx);
00417 FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG);
00418 void DMA_ClearFlag(uint32_t DMAy_FLAG);
00419 ITStatus DMA_GetITStatus(uint32_t DMAy_IT);
00420 void DMA_ClearITPendingBit(uint32_t DMAy_IT);
00421
00422 #ifdef __cplusplus
00423 }
00424 #endif
00425
00426 #endif /*__STM32F10x_DMA_H */
00427 /**
00428   * @}
00429   */
00430
00431 /**
00432   * @}
00433   */
00434
00435 /**
00436   * @}
00437   */
00438
00439 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_exti.c Source File

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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Libraries
  • STM32F10x_StdPeriph_Driver
  • src

stm32f10x_exti.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32f10x_exti.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    11-March-2011
00007   * @brief   This file provides all the EXTI firmware functions.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x_exti.h"
00024
00025 /** @addtogroup STM32F10x_StdPeriph_Driver
00026   * @{
00027   */
00028
00029 /** @defgroup EXTI
00030   * @brief EXTI driver modules
00031   * @{
00032   */
00033
00034 /** @defgroup EXTI_Private_TypesDefinitions
00035   * @{
00036   */
00037
00038 /**
00039   * @}
00040   */
00041
00042 /** @defgroup EXTI_Private_Defines
00043   * @{
00044   */
00045
00046 #define EXTI_LINENONE    ((uint32_t)0x00000)  /* No interrupt selected */
00047
00048 /**
00049   * @}
00050   */
00051
00052 /** @defgroup EXTI_Private_Macros
00053   * @{
00054   */
00055
00056 /**
00057   * @}
00058   */
00059
00060 /** @defgroup EXTI_Private_Variables
00061   * @{
00062   */
00063
00064 /**
00065   * @}
00066   */
00067
00068 /** @defgroup EXTI_Private_FunctionPrototypes
00069   * @{
00070   */
00071
00072 /**
00073   * @}
00074   */
00075
00076 /** @defgroup EXTI_Private_Functions
00077   * @{
00078   */
00079
00080 /**
00081   * @brief  Deinitializes the EXTI peripheral registers to their default reset values.
00082   * @param  None
00083   * @retval None
00084   */
00085 void EXTI_DeInit(void)
00086 {
00087   EXTI->IMR = 0x00000000;
00088   EXTI->EMR = 0x00000000;
00089   EXTI->RTSR = 0x00000000;
00090   EXTI->FTSR = 0x00000000;
00091   EXTI->PR = 0x000FFFFF;
00092 }
00093
00094 /**
00095   * @brief  Initializes the EXTI peripheral according to the specified
00096   *         parameters in the EXTI_InitStruct.
00097   * @param  EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure
00098   *         that contains the configuration information for the EXTI peripheral.
00099   * @retval None
00100   */
00101 void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct)
00102 {
00103   uint32_t tmp = 0;
00104
00105   /* Check the parameters */
00106   assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode));
00107   assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger));
00108   assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line));
00109   assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd));
00110
00111   tmp = (uint32_t)EXTI_BASE;
00112
00113   if (EXTI_InitStruct->EXTI_LineCmd != DISABLE)
00114   {
00115     /* Clear EXTI line configuration */
00116     EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line;
00117     EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line;
00118
00119     tmp += EXTI_InitStruct->EXTI_Mode;
00120
00121     *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
00122
00123     /* Clear Rising Falling edge configuration */
00124     EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line;
00125     EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line;
00126
00127     /* Select the trigger for the selected external interrupts */
00128     if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)
00129     {
00130       /* Rising Falling edge */
00131       EXTI->RTSR |= EXTI_InitStruct->EXTI_Line;
00132       EXTI->FTSR |= EXTI_InitStruct->EXTI_Line;
00133     }
00134     else
00135     {
00136       tmp = (uint32_t)EXTI_BASE;
00137       tmp += EXTI_InitStruct->EXTI_Trigger;
00138
00139       *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
00140     }
00141   }
00142   else
00143   {
00144     tmp += EXTI_InitStruct->EXTI_Mode;
00145
00146     /* Disable the selected external lines */
00147     *(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line;
00148   }
00149 }
00150
00151 /**
00152   * @brief  Fills each EXTI_InitStruct member with its reset value.
00153   * @param  EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will
00154   *         be initialized.
00155   * @retval None
00156   */
00157 void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct)
00158 {
00159   EXTI_InitStruct->EXTI_Line = EXTI_LINENONE;
00160   EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
00161   EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;
00162   EXTI_InitStruct->EXTI_LineCmd = DISABLE;
00163 }
00164
00165 /**
00166   * @brief  Generates a Software interrupt.
00167   * @param  EXTI_Line: specifies the EXTI lines to be enabled or disabled.
00168   *   This parameter can be any combination of EXTI_Linex where x can be (0..19).
00169   * @retval None
00170   */
00171 void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)
00172 {
00173   /* Check the parameters */
00174   assert_param(IS_EXTI_LINE(EXTI_Line));
00175
00176   EXTI->SWIER |= EXTI_Line;
00177 }
00178
00179 /**
00180   * @brief  Checks whether the specified EXTI line flag is set or not.
00181   * @param  EXTI_Line: specifies the EXTI line flag to check.
00182   *   This parameter can be:
00183   *     @arg EXTI_Linex: External interrupt line x where x(0..19)
00184   * @retval The new state of EXTI_Line (SET or RESET).
00185   */
00186 FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line)
00187 {
00188   FlagStatus bitstatus = RESET;
00189   /* Check the parameters */
00190   assert_param(IS_GET_EXTI_LINE(EXTI_Line));
00191
00192   if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET)
00193   {
00194     bitstatus = SET;
00195   }
00196   else
00197   {
00198     bitstatus = RESET;
00199   }
00200   return bitstatus;
00201 }
00202
00203 /**
00204   * @brief  Clears the EXTI's line pending flags.
00205   * @param  EXTI_Line: specifies the EXTI lines flags to clear.
00206   *   This parameter can be any combination of EXTI_Linex where x can be (0..19).
00207   * @retval None
00208   */
00209 void EXTI_ClearFlag(uint32_t EXTI_Line)
00210 {
00211   /* Check the parameters */
00212   assert_param(IS_EXTI_LINE(EXTI_Line));
00213
00214   EXTI->PR = EXTI_Line;
00215 }
00216
00217 /**
00218   * @brief  Checks whether the specified EXTI line is asserted or not.
00219   * @param  EXTI_Line: specifies the EXTI line to check.
00220   *   This parameter can be:
00221   *     @arg EXTI_Linex: External interrupt line x where x(0..19)
00222   * @retval The new state of EXTI_Line (SET or RESET).
00223   */
00224 ITStatus EXTI_GetITStatus(uint32_t EXTI_Line)
00225 {
00226   ITStatus bitstatus = RESET;
00227   uint32_t enablestatus = 0;
00228   /* Check the parameters */
00229   assert_param(IS_GET_EXTI_LINE(EXTI_Line));
00230
00231   enablestatus =  EXTI->IMR & EXTI_Line;
00232   if (((EXTI->PR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
00233   {
00234     bitstatus = SET;
00235   }
00236   else
00237   {
00238     bitstatus = RESET;
00239   }
00240   return bitstatus;
00241 }
00242
00243 /**
00244   * @brief  Clears the EXTI's line pending bits.
00245   * @param  EXTI_Line: specifies the EXTI lines to clear.
00246   *   This parameter can be any combination of EXTI_Linex where x can be (0..19).
00247   * @retval None
00248   */
00249 void EXTI_ClearITPendingBit(uint32_t EXTI_Line)
00250 {
00251   /* Check the parameters */
00252   assert_param(IS_EXTI_LINE(EXTI_Line));
00253
00254   EXTI->PR = EXTI_Line;
00255 }
00256
00257 /**
00258   * @}
00259   */
00260
00261 /**
00262   * @}
00263   */
00264
00265 /**
00266   * @}
00267   */
00268
00269 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_exti.h Source File

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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Libraries
  • STM32F10x_StdPeriph_Driver
  • inc

stm32f10x_exti.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32f10x_exti.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    11-March-2011
00007   * @brief   This file contains all the functions prototypes for the EXTI firmware
00008   *          library.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00013   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00014   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00015   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00016   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00017   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00018   *
00019   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00020   ******************************************************************************
00021   */
00022
00023 /* Define to prevent recursive inclusion -------------------------------------*/
00024 #ifndef __STM32F10x_EXTI_H
00025 #define __STM32F10x_EXTI_H
00026
00027 #ifdef __cplusplus
00028  extern "C" {
00029 #endif
00030
00031 /* Includes ------------------------------------------------------------------*/
00032 #include "stm32f10x.h"
00033
00034 /** @addtogroup STM32F10x_StdPeriph_Driver
00035   * @{
00036   */
00037
00038 /** @addtogroup EXTI
00039   * @{
00040   */
00041
00042 /** @defgroup EXTI_Exported_Types
00043   * @{
00044   */
00045
00046 /**
00047   * @brief  EXTI mode enumeration
00048   */
00049
00050 typedef enum
00051 {
00052   EXTI_Mode_Interrupt = 0x00,
00053   EXTI_Mode_Event = 0x04
00054 }EXTIMode_TypeDef;
00055
00056 #define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))
00057
00058 /**
00059   * @brief  EXTI Trigger enumeration
00060   */
00061
00062 typedef enum
00063 {
00064   EXTI_Trigger_Rising = 0x08,
00065   EXTI_Trigger_Falling = 0x0C,
00066   EXTI_Trigger_Rising_Falling = 0x10
00067 }EXTITrigger_TypeDef;
00068
00069 #define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \
00070                                   ((TRIGGER) == EXTI_Trigger_Falling) || \
00071                                   ((TRIGGER) == EXTI_Trigger_Rising_Falling))
00072 /**
00073   * @brief  EXTI Init Structure definition
00074   */
00075
00076 typedef struct
00077 {
00078   uint32_t EXTI_Line;               /*!< Specifies the EXTI lines to be enabled or disabled.
00079                                          This parameter can be any combination of @ref EXTI_Lines */
00080
00081   EXTIMode_TypeDef EXTI_Mode;       /*!< Specifies the mode for the EXTI lines.
00082                                          This parameter can be a value of @ref EXTIMode_TypeDef */
00083
00084   EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
00085                                          This parameter can be a value of @ref EXTIMode_TypeDef */
00086
00087   FunctionalState EXTI_LineCmd;     /*!< Specifies the new state of the selected EXTI lines.
00088                                          This parameter can be set either to ENABLE or DISABLE */
00089 }EXTI_InitTypeDef;
00090
00091 /**
00092   * @}
00093   */
00094
00095 /** @defgroup EXTI_Exported_Constants
00096   * @{
00097   */
00098
00099 /** @defgroup EXTI_Lines
00100   * @{
00101   */
00102
00103 #define EXTI_Line0       ((uint32_t)0x00001)  /*!< External interrupt line 0 */
00104 #define EXTI_Line1       ((uint32_t)0x00002)  /*!< External interrupt line 1 */
00105 #define EXTI_Line2       ((uint32_t)0x00004)  /*!< External interrupt line 2 */
00106 #define EXTI_Line3       ((uint32_t)0x00008)  /*!< External interrupt line 3 */
00107 #define EXTI_Line4       ((uint32_t)0x00010)  /*!< External interrupt line 4 */
00108 #define EXTI_Line5       ((uint32_t)0x00020)  /*!< External interrupt line 5 */
00109 #define EXTI_Line6       ((uint32_t)0x00040)  /*!< External interrupt line 6 */
00110 #define EXTI_Line7       ((uint32_t)0x00080)  /*!< External interrupt line 7 */
00111 #define EXTI_Line8       ((uint32_t)0x00100)  /*!< External interrupt line 8 */
00112 #define EXTI_Line9       ((uint32_t)0x00200)  /*!< External interrupt line 9 */
00113 #define EXTI_Line10      ((uint32_t)0x00400)  /*!< External interrupt line 10 */
00114 #define EXTI_Line11      ((uint32_t)0x00800)  /*!< External interrupt line 11 */
00115 #define EXTI_Line12      ((uint32_t)0x01000)  /*!< External interrupt line 12 */
00116 #define EXTI_Line13      ((uint32_t)0x02000)  /*!< External interrupt line 13 */
00117 #define EXTI_Line14      ((uint32_t)0x04000)  /*!< External interrupt line 14 */
00118 #define EXTI_Line15      ((uint32_t)0x08000)  /*!< External interrupt line 15 */
00119 #define EXTI_Line16      ((uint32_t)0x10000)  /*!< External interrupt line 16 Connected to the PVD Output */
00120 #define EXTI_Line17      ((uint32_t)0x20000)  /*!< External interrupt line 17 Connected to the RTC Alarm event */
00121 #define EXTI_Line18      ((uint32_t)0x40000)  /*!< External interrupt line 18 Connected to the USB Device/USB OTG FS
00122                                                    Wakeup from suspend event */
00123 #define EXTI_Line19      ((uint32_t)0x80000)  /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */
00124
00125 #define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFFF00000) == 0x00) && ((LINE) != (uint16_t)0x00))
00126 #define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \
00127                             ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \
00128                             ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \
00129                             ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \
00130                             ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \
00131                             ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \
00132                             ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \
00133                             ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \
00134                             ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \
00135                             ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19))
00136
00137
00138 /**
00139   * @}
00140   */
00141
00142 /**
00143   * @}
00144   */
00145
00146 /** @defgroup EXTI_Exported_Macros
00147   * @{
00148   */
00149
00150 /**
00151   * @}
00152   */
00153
00154 /** @defgroup EXTI_Exported_Functions
00155   * @{
00156   */
00157
00158 void EXTI_DeInit(void);
00159 void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct);
00160 void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct);
00161 void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);
00162 FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);
00163 void EXTI_ClearFlag(uint32_t EXTI_Line);
00164 ITStatus EXTI_GetITStatus(uint32_t EXTI_Line);
00165 void EXTI_ClearITPendingBit(uint32_t EXTI_Line);
00166
00167 #ifdef __cplusplus
00168 }
00169 #endif
00170
00171 #endif /* __STM32F10x_EXTI_H */
00172 /**
00173   * @}
00174   */
00175
00176 /**
00177   * @}
00178   */
00179
00180 /**
00181   * @}
00182   */
00183
00184 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_flash.c Source File

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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Libraries
  • STM32F10x_StdPeriph_Driver
  • src

stm32f10x_flash.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32f10x_flash.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    11-March-2011
00007   * @brief   This file provides all the FLASH firmware functions.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x_flash.h"
00024
00025 /** @addtogroup STM32F10x_StdPeriph_Driver
00026   * @{
00027   */
00028
00029 /** @defgroup FLASH
00030   * @brief FLASH driver modules
00031   * @{
00032   */
00033
00034 /** @defgroup FLASH_Private_TypesDefinitions
00035   * @{
00036   */
00037
00038 /**
00039   * @}
00040   */
00041
00042 /** @defgroup FLASH_Private_Defines
00043   * @{
00044   */
00045
00046 /* Flash Access Control Register bits */
00047 #define ACR_LATENCY_Mask         ((uint32_t)0x00000038)
00048 #define ACR_HLFCYA_Mask          ((uint32_t)0xFFFFFFF7)
00049 #define ACR_PRFTBE_Mask          ((uint32_t)0xFFFFFFEF)
00050
00051 /* Flash Access Control Register bits */
00052 #define ACR_PRFTBS_Mask          ((uint32_t)0x00000020)
00053
00054 /* Flash Control Register bits */
00055 #define CR_PG_Set                ((uint32_t)0x00000001)
00056 #define CR_PG_Reset              ((uint32_t)0x00001FFE)
00057 #define CR_PER_Set               ((uint32_t)0x00000002)
00058 #define CR_PER_Reset             ((uint32_t)0x00001FFD)
00059 #define CR_MER_Set               ((uint32_t)0x00000004)
00060 #define CR_MER_Reset             ((uint32_t)0x00001FFB)
00061 #define CR_OPTPG_Set             ((uint32_t)0x00000010)
00062 #define CR_OPTPG_Reset           ((uint32_t)0x00001FEF)
00063 #define CR_OPTER_Set             ((uint32_t)0x00000020)
00064 #define CR_OPTER_Reset           ((uint32_t)0x00001FDF)
00065 #define CR_STRT_Set              ((uint32_t)0x00000040)
00066 #define CR_LOCK_Set              ((uint32_t)0x00000080)
00067
00068 /* FLASH Mask */
00069 #define RDPRT_Mask               ((uint32_t)0x00000002)
00070 #define WRP0_Mask                ((uint32_t)0x000000FF)
00071 #define WRP1_Mask                ((uint32_t)0x0000FF00)
00072 #define WRP2_Mask                ((uint32_t)0x00FF0000)
00073 #define WRP3_Mask                ((uint32_t)0xFF000000)
00074 #define OB_USER_BFB2             ((uint16_t)0x0008)
00075
00076 /* FLASH Keys */
00077 #define RDP_Key                  ((uint16_t)0x00A5)
00078 #define FLASH_KEY1               ((uint32_t)0x45670123)
00079 #define FLASH_KEY2               ((uint32_t)0xCDEF89AB)
00080
00081 /* FLASH BANK address */
00082 #define FLASH_BANK1_END_ADDRESS   ((uint32_t)0x807FFFF)
00083
00084 /* Delay definition */
00085 #define EraseTimeout          ((uint32_t)0x000B0000)
00086 #define ProgramTimeout        ((uint32_t)0x00002000)
00087 /**
00088   * @}
00089   */
00090
00091 /** @defgroup FLASH_Private_Macros
00092   * @{
00093   */
00094
00095 /**
00096   * @}
00097   */
00098
00099 /** @defgroup FLASH_Private_Variables
00100   * @{
00101   */
00102
00103 /**
00104   * @}
00105   */
00106
00107 /** @defgroup FLASH_Private_FunctionPrototypes
00108   * @{
00109   */
00110
00111 /**
00112   * @}
00113   */
00114
00115 /** @defgroup FLASH_Private_Functions
00116   * @{
00117   */
00118
00119 /**
00120 @code
00121
00122  This driver provides functions to configure and program the Flash memory of all STM32F10x devices,
00123  including the latest STM32F10x_XL density devices.
00124
00125  STM32F10x_XL devices feature up to 1 Mbyte with dual bank architecture for read-while-write (RWW) capability:
00126     - bank1: fixed size of 512 Kbytes (256 pages of 2Kbytes each)
00127     - bank2: up to 512 Kbytes (up to 256 pages of 2Kbytes each)
00128  While other STM32F10x devices features only one bank with memory up to 512 Kbytes.
00129
00130  In version V3.3.0, some functions were updated and new ones were added to support
00131  STM32F10x_XL devices. Thus some functions manages all devices, while other are
00132  dedicated for XL devices only.
00133
00134  The table below presents the list of available functions depending on the used STM32F10x devices.
00135
00136    ***************************************************
00137    * Legacy functions used for all STM32F10x devices *
00138    ***************************************************
00139    +----------------------------------------------------------------------------------------------------------------------------------+
00140    |       Functions prototypes         |STM32F10x_XL|Other STM32F10x|    Comments                                                    |
00141    |                                    |   devices  |  devices      |                                                                |
00142    |----------------------------------------------------------------------------------------------------------------------------------|
00143    |FLASH_SetLatency                    |    Yes     |      Yes      | No change                                                      |
00144    |----------------------------------------------------------------------------------------------------------------------------------|
00145    |FLASH_HalfCycleAccessCmd            |    Yes     |      Yes      | No change                                                      |
00146    |----------------------------------------------------------------------------------------------------------------------------------|
00147    |FLASH_PrefetchBufferCmd             |    Yes     |      Yes      | No change                                                      |
00148    |----------------------------------------------------------------------------------------------------------------------------------|
00149    |FLASH_Unlock                        |    Yes     |      Yes      | - For STM32F10X_XL devices: unlock Bank1 and Bank2.            |
00150    |                                    |            |               | - For other devices: unlock Bank1 and it is equivalent         |
00151    |                                    |            |               |   to FLASH_UnlockBank1 function.                               |
00152    |----------------------------------------------------------------------------------------------------------------------------------|
00153    |FLASH_Lock                          |    Yes     |      Yes      | - For STM32F10X_XL devices: lock Bank1 and Bank2.              |
00154    |                                    |            |               | - For other devices: lock Bank1 and it is equivalent           |
00155    |                                    |            |               |   to FLASH_LockBank1 function.                                 |
00156    |----------------------------------------------------------------------------------------------------------------------------------|
00157    |FLASH_ErasePage                     |    Yes     |      Yes      | - For STM32F10x_XL devices: erase a page in Bank1 and Bank2    |
00158    |                                    |            |               | - For other devices: erase a page in Bank1                     |
00159    |----------------------------------------------------------------------------------------------------------------------------------|
00160    |FLASH_EraseAllPages                 |    Yes     |      Yes      | - For STM32F10x_XL devices: erase all pages in Bank1 and Bank2 |
00161    |                                    |            |               | - For other devices: erase all pages in Bank1                  |
00162    |----------------------------------------------------------------------------------------------------------------------------------|
00163    |FLASH_EraseOptionBytes              |    Yes     |      Yes      | No change                                                      |
00164    |----------------------------------------------------------------------------------------------------------------------------------|
00165    |FLASH_ProgramWord                   |    Yes     |      Yes      | Updated to program up to 1MByte (depending on the used device) |
00166    |----------------------------------------------------------------------------------------------------------------------------------|
00167    |FLASH_ProgramHalfWord               |    Yes     |      Yes      | Updated to program up to 1MByte (depending on the used device) |
00168    |----------------------------------------------------------------------------------------------------------------------------------|
00169    |FLASH_ProgramOptionByteData         |    Yes     |      Yes      | No change                                                      |
00170    |----------------------------------------------------------------------------------------------------------------------------------|
00171    |FLASH_EnableWriteProtection         |    Yes     |      Yes      | No change                                                      |
00172    |----------------------------------------------------------------------------------------------------------------------------------|
00173    |FLASH_ReadOutProtection             |    Yes     |      Yes      | No change                                                      |
00174    |----------------------------------------------------------------------------------------------------------------------------------|
00175    |FLASH_UserOptionByteConfig          |    Yes     |      Yes      | No change                                                      |
00176    |----------------------------------------------------------------------------------------------------------------------------------|
00177    |FLASH_GetUserOptionByte             |    Yes     |      Yes      | No change                                                      |
00178    |----------------------------------------------------------------------------------------------------------------------------------|
00179    |FLASH_GetWriteProtectionOptionByte  |    Yes     |      Yes      | No change                                                      |
00180    |----------------------------------------------------------------------------------------------------------------------------------|
00181    |FLASH_GetReadOutProtectionStatus    |    Yes     |      Yes      | No change                                                      |
00182    |----------------------------------------------------------------------------------------------------------------------------------|
00183    |FLASH_GetPrefetchBufferStatus       |    Yes     |      Yes      | No change                                                      |
00184    |----------------------------------------------------------------------------------------------------------------------------------|
00185    |FLASH_ITConfig                      |    Yes     |      Yes      | - For STM32F10x_XL devices: enable Bank1 and Bank2's interrupts|
00186    |                                    |            |               | - For other devices: enable Bank1's interrupts                 |
00187    |----------------------------------------------------------------------------------------------------------------------------------|
00188    |FLASH_GetFlagStatus                 |    Yes     |      Yes      | - For STM32F10x_XL devices: return Bank1 and Bank2's flag status|
00189    |                                    |            |               | - For other devices: return Bank1's flag status                |
00190    |----------------------------------------------------------------------------------------------------------------------------------|
00191    |FLASH_ClearFlag                     |    Yes     |      Yes      | - For STM32F10x_XL devices: clear Bank1 and Bank2's flag       |
00192    |                                    |            |               | - For other devices: clear Bank1's flag                        |
00193    |----------------------------------------------------------------------------------------------------------------------------------|
00194    |FLASH_GetStatus                     |    Yes     |      Yes      | - Return the status of Bank1 (for all devices)                 |
00195    |                                    |            |               |   equivalent to FLASH_GetBank1Status function                  |
00196    |----------------------------------------------------------------------------------------------------------------------------------|
00197    |FLASH_WaitForLastOperation          |    Yes     |      Yes      | - Wait for Bank1 last operation (for all devices)              |
00198    |                                    |            |               |   equivalent to: FLASH_WaitForLastBank1Operation function      |
00199    +----------------------------------------------------------------------------------------------------------------------------------+
00200
00201    ************************************************************************************************************************
00202    * New functions used for all STM32F10x devices to manage Bank1:                                                        *
00203    *   - These functions are mainly useful for STM32F10x_XL density devices, to have separate control for Bank1 and bank2 *
00204    *   - For other devices, these functions are optional (covered by functions listed above)                              *
00205    ************************************************************************************************************************
00206    +----------------------------------------------------------------------------------------------------------------------------------+
00207    |       Functions prototypes         |STM32F10x_XL|Other STM32F10x|    Comments                                                    |
00208    |                                    |   devices  |  devices      |                                                                |
00209    |----------------------------------------------------------------------------------------------------------------------------------|
00210    | FLASH_UnlockBank1                  |    Yes     |      Yes      | - Unlock Bank1                                                 |
00211    |----------------------------------------------------------------------------------------------------------------------------------|
00212    |FLASH_LockBank1                     |    Yes     |      Yes      | - Lock Bank1                                                   |
00213    |----------------------------------------------------------------------------------------------------------------------------------|
00214    | FLASH_EraseAllBank1Pages           |    Yes     |      Yes      | - Erase all pages in Bank1                                     |
00215    |----------------------------------------------------------------------------------------------------------------------------------|
00216    | FLASH_GetBank1Status               |    Yes     |      Yes      | - Return the status of Bank1                                   |
00217    |----------------------------------------------------------------------------------------------------------------------------------|
00218    | FLASH_WaitForLastBank1Operation    |    Yes     |      Yes      | - Wait for Bank1 last operation                                |
00219    +----------------------------------------------------------------------------------------------------------------------------------+
00220
00221    *****************************************************************************
00222    * New Functions used only with STM32F10x_XL density devices to manage Bank2 *
00223    *****************************************************************************
00224    +----------------------------------------------------------------------------------------------------------------------------------+
00225    |       Functions prototypes         |STM32F10x_XL|Other STM32F10x|    Comments                                                    |
00226    |                                    |   devices  |  devices      |                                                                |
00227    |----------------------------------------------------------------------------------------------------------------------------------|
00228    | FLASH_UnlockBank2                  |    Yes     |      No       | - Unlock Bank2                                                 |
00229    |----------------------------------------------------------------------------------------------------------------------------------|
00230    |FLASH_LockBank2                     |    Yes     |      No       | - Lock Bank2                                                   |
00231    |----------------------------------------------------------------------------------------------------------------------------------|
00232    | FLASH_EraseAllBank2Pages           |    Yes     |      No       | - Erase all pages in Bank2                                     |
00233    |----------------------------------------------------------------------------------------------------------------------------------|
00234    | FLASH_GetBank2Status               |    Yes     |      No       | - Return the status of Bank2                                   |
00235    |----------------------------------------------------------------------------------------------------------------------------------|
00236    | FLASH_WaitForLastBank2Operation    |    Yes     |      No       | - Wait for Bank2 last operation                                |
00237    |----------------------------------------------------------------------------------------------------------------------------------|
00238    | FLASH_BootConfig                   |    Yes     |      No       | - Configure to boot from Bank1 or Bank2                        |
00239    +----------------------------------------------------------------------------------------------------------------------------------+
00240 @endcode
00241 */
00242
00243
00244 /**
00245   * @brief  Sets the code latency value.
00246   * @note   This function can be used for all STM32F10x devices.
00247   * @param  FLASH_Latency: specifies the FLASH Latency value.
00248   *   This parameter can be one of the following values:
00249   *     @arg FLASH_Latency_0: FLASH Zero Latency cycle
00250   *     @arg FLASH_Latency_1: FLASH One Latency cycle
00251   *     @arg FLASH_Latency_2: FLASH Two Latency cycles
00252   * @retval None
00253   */
00254 void FLASH_SetLatency(uint32_t FLASH_Latency)
00255 {
00256   uint32_t tmpreg = 0;
00257
00258   /* Check the parameters */
00259   assert_param(IS_FLASH_LATENCY(FLASH_Latency));
00260
00261   /* Read the ACR register */
00262   tmpreg = FLASH->ACR;
00263
00264   /* Sets the Latency value */
00265   tmpreg &= ACR_LATENCY_Mask;
00266   tmpreg |= FLASH_Latency;
00267
00268   /* Write the ACR register */
00269   FLASH->ACR = tmpreg;
00270 }
00271
00272 /**
00273   * @brief  Enables or disables the Half cycle flash access.
00274   * @note   This function can be used for all STM32F10x devices.
00275   * @param  FLASH_HalfCycleAccess: specifies the FLASH Half cycle Access mode.
00276   *   This parameter can be one of the following values:
00277   *     @arg FLASH_HalfCycleAccess_Enable: FLASH Half Cycle Enable
00278   *     @arg FLASH_HalfCycleAccess_Disable: FLASH Half Cycle Disable
00279   * @retval None
00280   */
00281 void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess)
00282 {
00283   /* Check the parameters */
00284   assert_param(IS_FLASH_HALFCYCLEACCESS_STATE(FLASH_HalfCycleAccess));
00285
00286   /* Enable or disable the Half cycle access */
00287   FLASH->ACR &= ACR_HLFCYA_Mask;
00288   FLASH->ACR |= FLASH_HalfCycleAccess;
00289 }
00290
00291 /**
00292   * @brief  Enables or disables the Prefetch Buffer.
00293   * @note   This function can be used for all STM32F10x devices.
00294   * @param  FLASH_PrefetchBuffer: specifies the Prefetch buffer status.
00295   *   This parameter can be one of the following values:
00296   *     @arg FLASH_PrefetchBuffer_Enable: FLASH Prefetch Buffer Enable
00297   *     @arg FLASH_PrefetchBuffer_Disable: FLASH Prefetch Buffer Disable
00298   * @retval None
00299   */
00300 void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer)
00301 {
00302   /* Check the parameters */
00303   assert_param(IS_FLASH_PREFETCHBUFFER_STATE(FLASH_PrefetchBuffer));
00304
00305   /* Enable or disable the Prefetch Buffer */
00306   FLASH->ACR &= ACR_PRFTBE_Mask;
00307   FLASH->ACR |= FLASH_PrefetchBuffer;
00308 }
00309
00310 /**
00311   * @brief  Unlocks the FLASH Program Erase Controller.
00312   * @note   This function can be used for all STM32F10x devices.
00313   *         - For STM32F10X_XL devices this function unlocks Bank1 and Bank2.
00314   *         - For all other devices it unlocks Bank1 and it is equivalent
00315   *           to FLASH_UnlockBank1 function..
00316   * @param  None
00317   * @retval None
00318   */
00319 void FLASH_Unlock(void)
00320 {
00321   /* Authorize the FPEC of Bank1 Access */
00322   FLASH->KEYR = FLASH_KEY1;
00323   FLASH->KEYR = FLASH_KEY2;
00324
00325 #ifdef STM32F10X_XL
00326   /* Authorize the FPEC of Bank2 Access */
00327   FLASH->KEYR2 = FLASH_KEY1;
00328   FLASH->KEYR2 = FLASH_KEY2;
00329 #endif /* STM32F10X_XL */
00330 }
00331 /**
00332   * @brief  Unlocks the FLASH Bank1 Program Erase Controller.
00333   * @note   This function can be used for all STM32F10x devices.
00334   *         - For STM32F10X_XL devices this function unlocks Bank1.
00335   *         - For all other devices it unlocks Bank1 and it is
00336   *           equivalent to FLASH_Unlock function.
00337   * @param  None
00338   * @retval None
00339   */
00340 void FLASH_UnlockBank1(void)
00341 {
00342   /* Authorize the FPEC of Bank1 Access */
00343   FLASH->KEYR = FLASH_KEY1;
00344   FLASH->KEYR = FLASH_KEY2;
00345 }
00346
00347 #ifdef STM32F10X_XL
00348 /**
00349   * @brief  Unlocks the FLASH Bank2 Program Erase Controller.
00350   * @note   This function can be used only for STM32F10X_XL density devices.
00351   * @param  None
00352   * @retval None
00353   */
00354 void FLASH_UnlockBank2(void)
00355 {
00356   /* Authorize the FPEC of Bank2 Access */
00357   FLASH->KEYR2 = FLASH_KEY1;
00358   FLASH->KEYR2 = FLASH_KEY2;
00359
00360 }
00361 #endif /* STM32F10X_XL */
00362
00363 /**
00364   * @brief  Locks the FLASH Program Erase Controller.
00365   * @note   This function can be used for all STM32F10x devices.
00366   *         - For STM32F10X_XL devices this function Locks Bank1 and Bank2.
00367   *         - For all other devices it Locks Bank1 and it is equivalent
00368   *           to FLASH_LockBank1 function.
00369   * @param  None
00370   * @retval None
00371   */
00372 void FLASH_Lock(void)
00373 {
00374   /* Set the Lock Bit to lock the FPEC and the CR of  Bank1 */
00375   FLASH->CR |= CR_LOCK_Set;
00376
00377 #ifdef STM32F10X_XL
00378   /* Set the Lock Bit to lock the FPEC and the CR of  Bank2 */
00379   FLASH->CR2 |= CR_LOCK_Set;
00380 #endif /* STM32F10X_XL */
00381 }
00382
00383 /**
00384   * @brief  Locks the FLASH Bank1 Program Erase Controller.
00385   * @note   this function can be used for all STM32F10x devices.
00386   *         - For STM32F10X_XL devices this function Locks Bank1.
00387   *         - For all other devices it Locks Bank1 and it is equivalent
00388   *           to FLASH_Lock function.
00389   * @param  None
00390   * @retval None
00391   */
00392 void FLASH_LockBank1(void)
00393 {
00394   /* Set the Lock Bit to lock the FPEC and the CR of  Bank1 */
00395   FLASH->CR |= CR_LOCK_Set;
00396 }
00397
00398 #ifdef STM32F10X_XL
00399 /**
00400   * @brief  Locks the FLASH Bank2 Program Erase Controller.
00401   * @note   This function can be used only for STM32F10X_XL density devices.
00402   * @param  None
00403   * @retval None
00404   */
00405 void FLASH_LockBank2(void)
00406 {
00407   /* Set the Lock Bit to lock the FPEC and the CR of  Bank2 */
00408   FLASH->CR2 |= CR_LOCK_Set;
00409 }
00410 #endif /* STM32F10X_XL */
00411
00412 /**
00413   * @brief  Erases a specified FLASH page.
00414   * @note   This function can be used for all STM32F10x devices.
00415   * @param  Page_Address: The page address to be erased.
00416   * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
00417   *         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
00418   */
00419 FLASH_Status FLASH_ErasePage(uint32_t Page_Address)
00420 {
00421   FLASH_Status status = FLASH_COMPLETE;
00422   /* Check the parameters */
00423   assert_param(IS_FLASH_ADDRESS(Page_Address));
00424
00425 #ifdef STM32F10X_XL
00426   if(Page_Address < FLASH_BANK1_END_ADDRESS)
00427   {
00428     /* Wait for last operation to be completed */
00429     status = FLASH_WaitForLastBank1Operation(EraseTimeout);
00430     if(status == FLASH_COMPLETE)
00431     {
00432       /* if the previous operation is completed, proceed to erase the page */
00433       FLASH->CR|= CR_PER_Set;
00434       FLASH->AR = Page_Address;
00435       FLASH->CR|= CR_STRT_Set;
00436
00437       /* Wait for last operation to be completed */
00438       status = FLASH_WaitForLastBank1Operation(EraseTimeout);
00439
00440       /* Disable the PER Bit */
00441       FLASH->CR &= CR_PER_Reset;
00442     }
00443   }
00444   else
00445   {
00446     /* Wait for last operation to be completed */
00447     status = FLASH_WaitForLastBank2Operation(EraseTimeout);
00448     if(status == FLASH_COMPLETE)
00449     {
00450       /* if the previous operation is completed, proceed to erase the page */
00451       FLASH->CR2|= CR_PER_Set;
00452       FLASH->AR2 = Page_Address;
00453       FLASH->CR2|= CR_STRT_Set;
00454
00455       /* Wait for last operation to be completed */
00456       status = FLASH_WaitForLastBank2Operation(EraseTimeout);
00457
00458       /* Disable the PER Bit */
00459       FLASH->CR2 &= CR_PER_Reset;
00460     }
00461   }
00462 #else
00463   /* Wait for last operation to be completed */
00464   status = FLASH_WaitForLastOperation(EraseTimeout);
00465
00466   if(status == FLASH_COMPLETE)
00467   {
00468     /* if the previous operation is completed, proceed to erase the page */
00469     FLASH->CR|= CR_PER_Set;
00470     FLASH->AR = Page_Address;
00471     FLASH->CR|= CR_STRT_Set;
00472
00473     /* Wait for last operation to be completed */
00474     status = FLASH_WaitForLastOperation(EraseTimeout);
00475
00476     /* Disable the PER Bit */
00477     FLASH->CR &= CR_PER_Reset;
00478   }
00479 #endif /* STM32F10X_XL */
00480
00481   /* Return the Erase Status */
00482   return status;
00483 }
00484
00485 /**
00486   * @brief  Erases all FLASH pages.
00487   * @note   This function can be used for all STM32F10x devices.
00488   * @param  None
00489   * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
00490   *         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
00491   */
00492 FLASH_Status FLASH_EraseAllPages(void)
00493 {
00494   FLASH_Status status = FLASH_COMPLETE;
00495
00496 #ifdef STM32F10X_XL
00497   /* Wait for last operation to be completed */
00498   status = FLASH_WaitForLastBank1Operation(EraseTimeout);
00499
00500   if(status == FLASH_COMPLETE)
00501   {
00502     /* if the previous operation is completed, proceed to erase all pages */
00503      FLASH->CR |= CR_MER_Set;
00504      FLASH->CR |= CR_STRT_Set;
00505
00506     /* Wait for last operation to be completed */
00507     status = FLASH_WaitForLastBank1Operation(EraseTimeout);
00508
00509     /* Disable the MER Bit */
00510     FLASH->CR &= CR_MER_Reset;
00511   }
00512   if(status == FLASH_COMPLETE)
00513   {
00514     /* if the previous operation is completed, proceed to erase all pages */
00515      FLASH->CR2 |= CR_MER_Set;
00516      FLASH->CR2 |= CR_STRT_Set;
00517
00518     /* Wait for last operation to be completed */
00519     status = FLASH_WaitForLastBank2Operation(EraseTimeout);
00520
00521     /* Disable the MER Bit */
00522     FLASH->CR2 &= CR_MER_Reset;
00523   }
00524 #else
00525   /* Wait for last operation to be completed */
00526   status = FLASH_WaitForLastOperation(EraseTimeout);
00527   if(status == FLASH_COMPLETE)
00528   {
00529     /* if the previous operation is completed, proceed to erase all pages */
00530      FLASH->CR |= CR_MER_Set;
00531      FLASH->CR |= CR_STRT_Set;
00532
00533     /* Wait for last operation to be completed */
00534     status = FLASH_WaitForLastOperation(EraseTimeout);
00535
00536     /* Disable the MER Bit */
00537     FLASH->CR &= CR_MER_Reset;
00538   }
00539 #endif /* STM32F10X_XL */
00540
00541   /* Return the Erase Status */
00542   return status;
00543 }
00544
00545 /**
00546   * @brief  Erases all Bank1 FLASH pages.
00547   * @note   This function can be used for all STM32F10x devices.
00548   *         - For STM32F10X_XL devices this function erases all Bank1 pages.
00549   *         - For all other devices it erases all Bank1 pages and it is equivalent
00550   *           to FLASH_EraseAllPages function.
00551   * @param  None
00552   * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
00553   *         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
00554   */
00555 FLASH_Status FLASH_EraseAllBank1Pages(void)
00556 {
00557   FLASH_Status status = FLASH_COMPLETE;
00558   /* Wait for last operation to be completed */
00559   status = FLASH_WaitForLastBank1Operation(EraseTimeout);
00560
00561   if(status == FLASH_COMPLETE)
00562   {
00563     /* if the previous operation is completed, proceed to erase all pages */
00564      FLASH->CR |= CR_MER_Set;
00565      FLASH->CR |= CR_STRT_Set;
00566
00567     /* Wait for last operation to be completed */
00568     status = FLASH_WaitForLastBank1Operation(EraseTimeout);
00569
00570     /* Disable the MER Bit */
00571     FLASH->CR &= CR_MER_Reset;
00572   }
00573   /* Return the Erase Status */
00574   return status;
00575 }
00576
00577 #ifdef STM32F10X_XL
00578 /**
00579   * @brief  Erases all Bank2 FLASH pages.
00580   * @note   This function can be used only for STM32F10x_XL density devices.
00581   * @param  None
00582   * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
00583   *         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
00584   */
00585 FLASH_Status FLASH_EraseAllBank2Pages(void)
00586 {
00587   FLASH_Status status = FLASH_COMPLETE;
00588   /* Wait for last operation to be completed */
00589   status = FLASH_WaitForLastBank2Operation(EraseTimeout);
00590
00591   if(status == FLASH_COMPLETE)
00592   {
00593     /* if the previous operation is completed, proceed to erase all pages */
00594      FLASH->CR2 |= CR_MER_Set;
00595      FLASH->CR2 |= CR_STRT_Set;
00596
00597     /* Wait for last operation to be completed */
00598     status = FLASH_WaitForLastBank2Operation(EraseTimeout);
00599
00600     /* Disable the MER Bit */
00601     FLASH->CR2 &= CR_MER_Reset;
00602   }
00603   /* Return the Erase Status */
00604   return status;
00605 }
00606 #endif /* STM32F10X_XL */
00607
00608 /**
00609   * @brief  Erases the FLASH option bytes.
00610   * @note   This functions erases all option bytes except the Read protection (RDP).
00611   * @note   This function can be used for all STM32F10x devices.
00612   * @param  None
00613   * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
00614   *         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
00615   */
00616 FLASH_Status FLASH_EraseOptionBytes(void)
00617 {
00618   uint16_t rdptmp = RDP_Key;
00619
00620   FLASH_Status status = FLASH_COMPLETE;
00621
00622   /* Get the actual read protection Option Byte value */
00623   if(FLASH_GetReadOutProtectionStatus() != RESET)
00624   {
00625     rdptmp = 0x00;
00626   }
00627
00628   /* Wait for last operation to be completed */
00629   status = FLASH_WaitForLastOperation(EraseTimeout);
00630   if(status == FLASH_COMPLETE)
00631   {
00632     /* Authorize the small information block programming */
00633     FLASH->OPTKEYR = FLASH_KEY1;
00634     FLASH->OPTKEYR = FLASH_KEY2;
00635
00636     /* if the previous operation is completed, proceed to erase the option bytes */
00637     FLASH->CR |= CR_OPTER_Set;
00638     FLASH->CR |= CR_STRT_Set;
00639     /* Wait for last operation to be completed */
00640     status = FLASH_WaitForLastOperation(EraseTimeout);
00641
00642     if(status == FLASH_COMPLETE)
00643     {
00644       /* if the erase operation is completed, disable the OPTER Bit */
00645       FLASH->CR &= CR_OPTER_Reset;
00646
00647       /* Enable the Option Bytes Programming operation */
00648       FLASH->CR |= CR_OPTPG_Set;
00649       /* Restore the last read protection Option Byte value */
00650       OB->RDP = (uint16_t)rdptmp;
00651       /* Wait for last operation to be completed */
00652       status = FLASH_WaitForLastOperation(ProgramTimeout);
00653
00654       if(status != FLASH_TIMEOUT)
00655       {
00656         /* if the program operation is completed, disable the OPTPG Bit */
00657         FLASH->CR &= CR_OPTPG_Reset;
00658       }
00659     }
00660     else
00661     {
00662       if (status != FLASH_TIMEOUT)
00663       {
00664         /* Disable the OPTPG Bit */
00665         FLASH->CR &= CR_OPTPG_Reset;
00666       }
00667     }
00668   }
00669   /* Return the erase status */
00670   return status;
00671 }
00672
00673 /**
00674   * @brief  Programs a word at a specified address.
00675   * @note   This function can be used for all STM32F10x devices.
00676   * @param  Address: specifies the address to be programmed.
00677   * @param  Data: specifies the data to be programmed.
00678   * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
00679   *         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
00680   */
00681 FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data)
00682 {
00683   FLASH_Status status = FLASH_COMPLETE;
00684   __IO uint32_t tmp = 0;
00685
00686   /* Check the parameters */
00687   assert_param(IS_FLASH_ADDRESS(Address));
00688
00689 #ifdef STM32F10X_XL
00690   if(Address < FLASH_BANK1_END_ADDRESS - 2)
00691   {
00692     /* Wait for last operation to be completed */
00693     status = FLASH_WaitForLastBank1Operation(ProgramTimeout);
00694     if(status == FLASH_COMPLETE)
00695     {
00696       /* if the previous operation is completed, proceed to program the new first
00697         half word */
00698       FLASH->CR |= CR_PG_Set;
00699
00700       *(__IO uint16_t*)Address = (uint16_t)Data;
00701       /* Wait for last operation to be completed */
00702       status = FLASH_WaitForLastOperation(ProgramTimeout);
00703
00704       if(status == FLASH_COMPLETE)
00705       {
00706         /* if the previous operation is completed, proceed to program the new second
00707         half word */
00708         tmp = Address + 2;
00709
00710         *(__IO uint16_t*) tmp = Data >> 16;
00711
00712         /* Wait for last operation to be completed */
00713         status = FLASH_WaitForLastOperation(ProgramTimeout);
00714
00715         /* Disable the PG Bit */
00716         FLASH->CR &= CR_PG_Reset;
00717       }
00718       else
00719       {
00720         /* Disable the PG Bit */
00721         FLASH->CR &= CR_PG_Reset;
00722        }
00723     }
00724   }
00725   else if(Address == (FLASH_BANK1_END_ADDRESS - 1))
00726   {
00727     /* Wait for last operation to be completed */
00728     status = FLASH_WaitForLastBank1Operation(ProgramTimeout);
00729
00730     if(status == FLASH_COMPLETE)
00731     {
00732       /* if the previous operation is completed, proceed to program the new first
00733         half word */
00734       FLASH->CR |= CR_PG_Set;
00735
00736       *(__IO uint16_t*)Address = (uint16_t)Data;
00737
00738       /* Wait for last operation to be completed */
00739       status = FLASH_WaitForLastBank1Operation(ProgramTimeout);
00740
00741           /* Disable the PG Bit */
00742       FLASH->CR &= CR_PG_Reset;
00743     }
00744     else
00745     {
00746       /* Disable the PG Bit */
00747       FLASH->CR &= CR_PG_Reset;
00748     }
00749
00750     /* Wait for last operation to be completed */
00751     status = FLASH_WaitForLastBank2Operation(ProgramTimeout);
00752
00753     if(status == FLASH_COMPLETE)
00754     {
00755       /* if the previous operation is completed, proceed to program the new second
00756       half word */
00757       FLASH->CR2 |= CR_PG_Set;
00758       tmp = Address + 2;
00759
00760       *(__IO uint16_t*) tmp = Data >> 16;
00761
00762       /* Wait for last operation to be completed */
00763       status = FLASH_WaitForLastBank2Operation(ProgramTimeout);
00764
00765       /* Disable the PG Bit */
00766       FLASH->CR2 &= CR_PG_Reset;
00767     }
00768     else
00769     {
00770       /* Disable the PG Bit */
00771       FLASH->CR2 &= CR_PG_Reset;
00772     }
00773   }
00774   else
00775   {
00776     /* Wait for last operation to be completed */
00777     status = FLASH_WaitForLastBank2Operation(ProgramTimeout);
00778
00779     if(status == FLASH_COMPLETE)
00780     {
00781       /* if the previous operation is completed, proceed to program the new first
00782         half word */
00783       FLASH->CR2 |= CR_PG_Set;
00784
00785       *(__IO uint16_t*)Address = (uint16_t)Data;
00786       /* Wait for last operation to be completed */
00787       status = FLASH_WaitForLastBank2Operation(ProgramTimeout);
00788
00789       if(status == FLASH_COMPLETE)
00790       {
00791         /* if the previous operation is completed, proceed to program the new second
00792         half word */
00793         tmp = Address + 2;
00794
00795         *(__IO uint16_t*) tmp = Data >> 16;
00796
00797         /* Wait for last operation to be completed */
00798         status = FLASH_WaitForLastBank2Operation(ProgramTimeout);
00799
00800         /* Disable the PG Bit */
00801         FLASH->CR2 &= CR_PG_Reset;
00802       }
00803       else
00804       {
00805         /* Disable the PG Bit */
00806         FLASH->CR2 &= CR_PG_Reset;
00807       }
00808     }
00809   }
00810 #else
00811   /* Wait for last operation to be completed */
00812   status = FLASH_WaitForLastOperation(ProgramTimeout);
00813
00814   if(status == FLASH_COMPLETE)
00815   {
00816     /* if the previous operation is completed, proceed to program the new first
00817     half word */
00818     FLASH->CR |= CR_PG_Set;
00819
00820     *(__IO uint16_t*)Address = (uint16_t)Data;
00821     /* Wait for last operation to be completed */
00822     status = FLASH_WaitForLastOperation(ProgramTimeout);
00823
00824     if(status == FLASH_COMPLETE)
00825     {
00826       /* if the previous operation is completed, proceed to program the new second
00827       half word */
00828       tmp = Address + 2;
00829
00830       *(__IO uint16_t*) tmp = Data >> 16;
00831
00832       /* Wait for last operation to be completed */
00833       status = FLASH_WaitForLastOperation(ProgramTimeout);
00834
00835       /* Disable the PG Bit */
00836       FLASH->CR &= CR_PG_Reset;
00837     }
00838     else
00839     {
00840       /* Disable the PG Bit */
00841       FLASH->CR &= CR_PG_Reset;
00842     }
00843   }
00844 #endif /* STM32F10X_XL */
00845
00846   /* Return the Program Status */
00847   return status;
00848 }
00849
00850 /**
00851   * @brief  Programs a half word at a specified address.
00852   * @note   This function can be used for all STM32F10x devices.
00853   * @param  Address: specifies the address to be programmed.
00854   * @param  Data: specifies the data to be programmed.
00855   * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
00856   *         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
00857   */
00858 FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data)
00859 {
00860   FLASH_Status status = FLASH_COMPLETE;
00861   /* Check the parameters */
00862   assert_param(IS_FLASH_ADDRESS(Address));
00863
00864 #ifdef STM32F10X_XL
00865   /* Wait for last operation to be completed */
00866   status = FLASH_WaitForLastOperation(ProgramTimeout);
00867
00868   if(Address < FLASH_BANK1_END_ADDRESS)
00869   {
00870     if(status == FLASH_COMPLETE)
00871     {
00872       /* if the previous operation is completed, proceed to program the new data */
00873       FLASH->CR |= CR_PG_Set;
00874
00875       *(__IO uint16_t*)Address = Data;
00876       /* Wait for last operation to be completed */
00877       status = FLASH_WaitForLastBank1Operation(ProgramTimeout);
00878
00879       /* Disable the PG Bit */
00880       FLASH->CR &= CR_PG_Reset;
00881     }
00882   }
00883   else
00884   {
00885     if(status == FLASH_COMPLETE)
00886     {
00887       /* if the previous operation is completed, proceed to program the new data */
00888       FLASH->CR2 |= CR_PG_Set;
00889
00890       *(__IO uint16_t*)Address = Data;
00891       /* Wait for last operation to be completed */
00892       status = FLASH_WaitForLastBank2Operation(ProgramTimeout);
00893
00894       /* Disable the PG Bit */
00895       FLASH->CR2 &= CR_PG_Reset;
00896     }
00897   }
00898 #else
00899   /* Wait for last operation to be completed */
00900   status = FLASH_WaitForLastOperation(ProgramTimeout);
00901
00902   if(status == FLASH_COMPLETE)
00903   {
00904     /* if the previous operation is completed, proceed to program the new data */
00905     FLASH->CR |= CR_PG_Set;
00906
00907     *(__IO uint16_t*)Address = Data;
00908     /* Wait for last operation to be completed */
00909     status = FLASH_WaitForLastOperation(ProgramTimeout);
00910
00911     /* Disable the PG Bit */
00912     FLASH->CR &= CR_PG_Reset;
00913   }
00914 #endif  /* STM32F10X_XL */
00915
00916   /* Return the Program Status */
00917   return status;
00918 }
00919
00920 /**
00921   * @brief  Programs a half word at a specified Option Byte Data address.
00922   * @note   This function can be used for all STM32F10x devices.
00923   * @param  Address: specifies the address to be programmed.
00924   *   This parameter can be 0x1FFFF804 or 0x1FFFF806.
00925   * @param  Data: specifies the data to be programmed.
00926   * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
00927   *         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
00928   */
00929 FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data)
00930 {
00931   FLASH_Status status = FLASH_COMPLETE;
00932   /* Check the parameters */
00933   assert_param(IS_OB_DATA_ADDRESS(Address));
00934   status = FLASH_WaitForLastOperation(ProgramTimeout);
00935
00936   if(status == FLASH_COMPLETE)
00937   {
00938     /* Authorize the small information block programming */
00939     FLASH->OPTKEYR = FLASH_KEY1;
00940     FLASH->OPTKEYR = FLASH_KEY2;
00941     /* Enables the Option Bytes Programming operation */
00942     FLASH->CR |= CR_OPTPG_Set;
00943     *(__IO uint16_t*)Address = Data;
00944
00945     /* Wait for last operation to be completed */
00946     status = FLASH_WaitForLastOperation(ProgramTimeout);
00947     if(status != FLASH_TIMEOUT)
00948     {
00949       /* if the program operation is completed, disable the OPTPG Bit */
00950       FLASH->CR &= CR_OPTPG_Reset;
00951     }
00952   }
00953   /* Return the Option Byte Data Program Status */
00954   return status;
00955 }
00956
00957 /**
00958   * @brief  Write protects the desired pages
00959   * @note   This function can be used for all STM32F10x devices.
00960   * @param  FLASH_Pages: specifies the address of the pages to be write protected.
00961   *   This parameter can be:
00962   *     @arg For @b STM32_Low-density_devices: value between FLASH_WRProt_Pages0to3 and FLASH_WRProt_Pages28to31
00963   *     @arg For @b STM32_Medium-density_devices: value between FLASH_WRProt_Pages0to3
00964   *       and FLASH_WRProt_Pages124to127
00965   *     @arg For @b STM32_High-density_devices: value between FLASH_WRProt_Pages0to1 and
00966   *       FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to255
00967   *     @arg For @b STM32_Connectivity_line_devices: value between FLASH_WRProt_Pages0to1 and
00968   *       FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to127
00969   *     @arg For @b STM32_XL-density_devices: value between FLASH_WRProt_Pages0to1 and
00970   *       FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to511
00971   *     @arg FLASH_WRProt_AllPages
00972   * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
00973   *         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
00974   */
00975 FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages)
00976 {
00977   uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF, WRP2_Data = 0xFFFF, WRP3_Data = 0xFFFF;
00978
00979   FLASH_Status status = FLASH_COMPLETE;
00980
00981   /* Check the parameters */
00982   assert_param(IS_FLASH_WRPROT_PAGE(FLASH_Pages));
00983
00984   FLASH_Pages = (uint32_t)(~FLASH_Pages);
00985   WRP0_Data = (uint16_t)(FLASH_Pages & WRP0_Mask);
00986   WRP1_Data = (uint16_t)((FLASH_Pages & WRP1_Mask) >> 8);
00987   WRP2_Data = (uint16_t)((FLASH_Pages & WRP2_Mask) >> 16);
00988   WRP3_Data = (uint16_t)((FLASH_Pages & WRP3_Mask) >> 24);
00989
00990   /* Wait for last operation to be completed */
00991   status = FLASH_WaitForLastOperation(ProgramTimeout);
00992
00993   if(status == FLASH_COMPLETE)
00994   {
00995     /* Authorizes the small information block programming */
00996     FLASH->OPTKEYR = FLASH_KEY1;
00997     FLASH->OPTKEYR = FLASH_KEY2;
00998     FLASH->CR |= CR_OPTPG_Set;
00999     if(WRP0_Data != 0xFF)
01000     {
01001       OB->WRP0 = WRP0_Data;
01002
01003       /* Wait for last operation to be completed */
01004       status = FLASH_WaitForLastOperation(ProgramTimeout);
01005     }
01006     if((status == FLASH_COMPLETE) && (WRP1_Data != 0xFF))
01007     {
01008       OB->WRP1 = WRP1_Data;
01009
01010       /* Wait for last operation to be completed */
01011       status = FLASH_WaitForLastOperation(ProgramTimeout);
01012     }
01013     if((status == FLASH_COMPLETE) && (WRP2_Data != 0xFF))
01014     {
01015       OB->WRP2 = WRP2_Data;
01016
01017       /* Wait for last operation to be completed */
01018       status = FLASH_WaitForLastOperation(ProgramTimeout);
01019     }
01020
01021     if((status == FLASH_COMPLETE)&& (WRP3_Data != 0xFF))
01022     {
01023       OB->WRP3 = WRP3_Data;
01024
01025       /* Wait for last operation to be completed */
01026       status = FLASH_WaitForLastOperation(ProgramTimeout);
01027     }
01028
01029     if(status != FLASH_TIMEOUT)
01030     {
01031       /* if the program operation is completed, disable the OPTPG Bit */
01032       FLASH->CR &= CR_OPTPG_Reset;
01033     }
01034   }
01035   /* Return the write protection operation Status */
01036   return status;
01037 }
01038
01039 /**
01040   * @brief  Enables or disables the read out protection.
01041   * @note   If the user has already programmed the other option bytes before calling
01042   *   this function, he must re-program them since this function erases all option bytes.
01043   * @note   This function can be used for all STM32F10x devices.
01044   * @param  Newstate: new state of the ReadOut Protection.
01045   *   This parameter can be: ENABLE or DISABLE.
01046   * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
01047   *         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
01048   */
01049 FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState)
01050 {
01051   FLASH_Status status = FLASH_COMPLETE;
01052   /* Check the parameters */
01053   assert_param(IS_FUNCTIONAL_STATE(NewState));
01054   status = FLASH_WaitForLastOperation(EraseTimeout);
01055   if(status == FLASH_COMPLETE)
01056   {
01057     /* Authorizes the small information block programming */
01058     FLASH->OPTKEYR = FLASH_KEY1;
01059     FLASH->OPTKEYR = FLASH_KEY2;
01060     FLASH->CR |= CR_OPTER_Set;
01061     FLASH->CR |= CR_STRT_Set;
01062     /* Wait for last operation to be completed */
01063     status = FLASH_WaitForLastOperation(EraseTimeout);
01064     if(status == FLASH_COMPLETE)
01065     {
01066       /* if the erase operation is completed, disable the OPTER Bit */
01067       FLASH->CR &= CR_OPTER_Reset;
01068       /* Enable the Option Bytes Programming operation */
01069       FLASH->CR |= CR_OPTPG_Set;
01070       if(NewState != DISABLE)
01071       {
01072         OB->RDP = 0x00;
01073       }
01074       else
01075       {
01076         OB->RDP = RDP_Key;
01077       }
01078       /* Wait for last operation to be completed */
01079       status = FLASH_WaitForLastOperation(EraseTimeout);
01080
01081       if(status != FLASH_TIMEOUT)
01082       {
01083         /* if the program operation is completed, disable the OPTPG Bit */
01084         FLASH->CR &= CR_OPTPG_Reset;
01085       }
01086     }
01087     else
01088     {
01089       if(status != FLASH_TIMEOUT)
01090       {
01091         /* Disable the OPTER Bit */
01092         FLASH->CR &= CR_OPTER_Reset;
01093       }
01094     }
01095   }
01096   /* Return the protection operation Status */
01097   return status;
01098 }
01099
01100 /**
01101   * @brief  Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
01102   * @note   This function can be used for all STM32F10x devices.
01103   * @param  OB_IWDG: Selects the IWDG mode
01104   *   This parameter can be one of the following values:
01105   *     @arg OB_IWDG_SW: Software IWDG selected
01106   *     @arg OB_IWDG_HW: Hardware IWDG selected
01107   * @param  OB_STOP: Reset event when entering STOP mode.
01108   *   This parameter can be one of the following values:
01109   *     @arg OB_STOP_NoRST: No reset generated when entering in STOP
01110   *     @arg OB_STOP_RST: Reset generated when entering in STOP
01111   * @param  OB_STDBY: Reset event when entering Standby mode.
01112   *   This parameter can be one of the following values:
01113   *     @arg OB_STDBY_NoRST: No reset generated when entering in STANDBY
01114   *     @arg OB_STDBY_RST: Reset generated when entering in STANDBY
01115   * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
01116   *         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
01117   */
01118 FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY)
01119 {
01120   FLASH_Status status = FLASH_COMPLETE;
01121
01122   /* Check the parameters */
01123   assert_param(IS_OB_IWDG_SOURCE(OB_IWDG));
01124   assert_param(IS_OB_STOP_SOURCE(OB_STOP));
01125   assert_param(IS_OB_STDBY_SOURCE(OB_STDBY));
01126
01127   /* Authorize the small information block programming */
01128   FLASH->OPTKEYR = FLASH_KEY1;
01129   FLASH->OPTKEYR = FLASH_KEY2;
01130
01131   /* Wait for last operation to be completed */
01132   status = FLASH_WaitForLastOperation(ProgramTimeout);
01133
01134   if(status == FLASH_COMPLETE)
01135   {
01136     /* Enable the Option Bytes Programming operation */
01137     FLASH->CR |= CR_OPTPG_Set;
01138
01139     OB->USER = OB_IWDG | (uint16_t)(OB_STOP | (uint16_t)(OB_STDBY | ((uint16_t)0xF8)));
01140
01141     /* Wait for last operation to be completed */
01142     status = FLASH_WaitForLastOperation(ProgramTimeout);
01143     if(status != FLASH_TIMEOUT)
01144     {
01145       /* if the program operation is completed, disable the OPTPG Bit */
01146       FLASH->CR &= CR_OPTPG_Reset;
01147     }
01148   }
01149   /* Return the Option Byte program Status */
01150   return status;
01151 }
01152
01153 #ifdef STM32F10X_XL
01154 /**
01155   * @brief  Configures to boot from Bank1 or Bank2.
01156   * @note   This function can be used only for STM32F10x_XL density devices.
01157   * @param  FLASH_BOOT: select the FLASH Bank to boot from.
01158   *   This parameter can be one of the following values:
01159   *     @arg FLASH_BOOT_Bank1: At startup, if boot pins are set in boot from user Flash
01160   *        position and this parameter is selected the device will boot from Bank1(Default).
01161   *     @arg FLASH_BOOT_Bank2: At startup, if boot pins are set in boot from user Flash
01162   *        position and this parameter is selected the device will boot from Bank2 or Bank1,
01163   *        depending on the activation of the bank. The active banks are checked in
01164   *        the following order: Bank2, followed by Bank1.
01165   *        The active bank is recognized by the value programmed at the base address
01166   *        of the respective bank (corresponding to the initial stack pointer value
01167   *        in the interrupt vector table).
01168   *        For more information, please refer to AN2606 from www.st.com.
01169   * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
01170   *         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
01171   */
01172 FLASH_Status FLASH_BootConfig(uint16_t FLASH_BOOT)
01173 {
01174   FLASH_Status status = FLASH_COMPLETE;
01175   assert_param(IS_FLASH_BOOT(FLASH_BOOT));
01176   /* Authorize the small information block programming */
01177   FLASH->OPTKEYR = FLASH_KEY1;
01178   FLASH->OPTKEYR = FLASH_KEY2;
01179
01180   /* Wait for last operation to be completed */
01181   status = FLASH_WaitForLastOperation(ProgramTimeout);
01182
01183   if(status == FLASH_COMPLETE)
01184   {
01185     /* Enable the Option Bytes Programming operation */
01186     FLASH->CR |= CR_OPTPG_Set;
01187
01188     if(FLASH_BOOT == FLASH_BOOT_Bank1)
01189     {
01190       OB->USER |= OB_USER_BFB2;
01191     }
01192     else
01193     {
01194       OB->USER &= (uint16_t)(~(uint16_t)(OB_USER_BFB2));
01195     }
01196     /* Wait for last operation to be completed */
01197     status = FLASH_WaitForLastOperation(ProgramTimeout);
01198     if(status != FLASH_TIMEOUT)
01199     {
01200       /* if the program operation is completed, disable the OPTPG Bit */
01201       FLASH->CR &= CR_OPTPG_Reset;
01202     }
01203   }
01204   /* Return the Option Byte program Status */
01205   return status;
01206 }
01207 #endif /* STM32F10X_XL */
01208
01209 /**
01210   * @brief  Returns the FLASH User Option Bytes values.
01211   * @note   This function can be used for all STM32F10x devices.
01212   * @param  None
01213   * @retval The FLASH User Option Bytes values:IWDG_SW(Bit0), RST_STOP(Bit1)
01214   *         and RST_STDBY(Bit2).
01215   */
01216 uint32_t FLASH_GetUserOptionByte(void)
01217 {
01218   /* Return the User Option Byte */
01219   return (uint32_t)(FLASH->OBR >> 2);
01220 }
01221
01222 /**
01223   * @brief  Returns the FLASH Write Protection Option Bytes Register value.
01224   * @note   This function can be used for all STM32F10x devices.
01225   * @param  None
01226   * @retval The FLASH Write Protection  Option Bytes Register value
01227   */
01228 uint32_t FLASH_GetWriteProtectionOptionByte(void)
01229 {
01230   /* Return the Flash write protection Register value */
01231   return (uint32_t)(FLASH->WRPR);
01232 }
01233
01234 /**
01235   * @brief  Checks whether the FLASH Read Out Protection Status is set or not.
01236   * @note   This function can be used for all STM32F10x devices.
01237   * @param  None
01238   * @retval FLASH ReadOut Protection Status(SET or RESET)
01239   */
01240 FlagStatus FLASH_GetReadOutProtectionStatus(void)
01241 {
01242   FlagStatus readoutstatus = RESET;
01243   if ((FLASH->OBR & RDPRT_Mask) != (uint32_t)RESET)
01244   {
01245     readoutstatus = SET;
01246   }
01247   else
01248   {
01249     readoutstatus = RESET;
01250   }
01251   return readoutstatus;
01252 }
01253
01254 /**
01255   * @brief  Checks whether the FLASH Prefetch Buffer status is set or not.
01256   * @note   This function can be used for all STM32F10x devices.
01257   * @param  None
01258   * @retval FLASH Prefetch Buffer Status (SET or RESET).
01259   */
01260 FlagStatus FLASH_GetPrefetchBufferStatus(void)
01261 {
01262   FlagStatus bitstatus = RESET;
01263
01264   if ((FLASH->ACR & ACR_PRFTBS_Mask) != (uint32_t)RESET)
01265   {
01266     bitstatus = SET;
01267   }
01268   else
01269   {
01270     bitstatus = RESET;
01271   }
01272   /* Return the new state of FLASH Prefetch Buffer Status (SET or RESET) */
01273   return bitstatus;
01274 }
01275
01276 /**
01277   * @brief  Enables or disables the specified FLASH interrupts.
01278   * @note   This function can be used for all STM32F10x devices.
01279   *         - For STM32F10X_XL devices, enables or disables the specified FLASH interrupts
01280               for Bank1 and Bank2.
01281   *         - For other devices it enables or disables the specified FLASH interrupts for Bank1.
01282   * @param  FLASH_IT: specifies the FLASH interrupt sources to be enabled or disabled.
01283   *   This parameter can be any combination of the following values:
01284   *     @arg FLASH_IT_ERROR: FLASH Error Interrupt
01285   *     @arg FLASH_IT_EOP: FLASH end of operation Interrupt
01286   * @param  NewState: new state of the specified Flash interrupts.
01287   *   This parameter can be: ENABLE or DISABLE.
01288   * @retval None
01289   */
01290 void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState)
01291 {
01292 #ifdef STM32F10X_XL
01293   /* Check the parameters */
01294   assert_param(IS_FLASH_IT(FLASH_IT));
01295   assert_param(IS_FUNCTIONAL_STATE(NewState));
01296
01297   if((FLASH_IT & 0x80000000) != 0x0)
01298   {
01299     if(NewState != DISABLE)
01300     {
01301       /* Enable the interrupt sources */
01302       FLASH->CR2 |= (FLASH_IT & 0x7FFFFFFF);
01303     }
01304     else
01305     {
01306       /* Disable the interrupt sources */
01307       FLASH->CR2 &= ~(uint32_t)(FLASH_IT & 0x7FFFFFFF);
01308     }
01309   }
01310   else
01311   {
01312     if(NewState != DISABLE)
01313     {
01314       /* Enable the interrupt sources */
01315       FLASH->CR |= FLASH_IT;
01316     }
01317     else
01318     {
01319       /* Disable the interrupt sources */
01320       FLASH->CR &= ~(uint32_t)FLASH_IT;
01321     }
01322   }
01323 #else
01324   /* Check the parameters */
01325   assert_param(IS_FLASH_IT(FLASH_IT));
01326   assert_param(IS_FUNCTIONAL_STATE(NewState));
01327
01328   if(NewState != DISABLE)
01329   {
01330     /* Enable the interrupt sources */
01331     FLASH->CR |= FLASH_IT;
01332   }
01333   else
01334   {
01335     /* Disable the interrupt sources */
01336     FLASH->CR &= ~(uint32_t)FLASH_IT;
01337   }
01338 #endif /* STM32F10X_XL */
01339 }
01340
01341 /**
01342   * @brief  Checks whether the specified FLASH flag is set or not.
01343   * @note   This function can be used for all STM32F10x devices.
01344   *         - For STM32F10X_XL devices, this function checks whether the specified
01345   *           Bank1 or Bank2 flag is set or not.
01346   *         - For other devices, it checks whether the specified Bank1 flag is
01347   *           set or not.
01348   * @param  FLASH_FLAG: specifies the FLASH flag to check.
01349   *   This parameter can be one of the following values:
01350   *     @arg FLASH_FLAG_BSY: FLASH Busy flag
01351   *     @arg FLASH_FLAG_PGERR: FLASH Program error flag
01352   *     @arg FLASH_FLAG_WRPRTERR: FLASH Write protected error flag
01353   *     @arg FLASH_FLAG_EOP: FLASH End of Operation flag
01354   *     @arg FLASH_FLAG_OPTERR:  FLASH Option Byte error flag
01355   * @retval The new state of FLASH_FLAG (SET or RESET).
01356   */
01357 FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG)
01358 {
01359   FlagStatus bitstatus = RESET;
01360
01361 #ifdef STM32F10X_XL
01362   /* Check the parameters */
01363   assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)) ;
01364   if(FLASH_FLAG == FLASH_FLAG_OPTERR)
01365   {
01366     if((FLASH->OBR & FLASH_FLAG_OPTERR) != (uint32_t)RESET)
01367     {
01368       bitstatus = SET;
01369     }
01370     else
01371     {
01372       bitstatus = RESET;
01373     }
01374   }
01375   else
01376   {
01377     if((FLASH_FLAG & 0x80000000) != 0x0)
01378     {
01379       if((FLASH->SR2 & FLASH_FLAG) != (uint32_t)RESET)
01380       {
01381         bitstatus = SET;
01382       }
01383       else
01384       {
01385         bitstatus = RESET;
01386       }
01387     }
01388     else
01389     {
01390       if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET)
01391       {
01392         bitstatus = SET;
01393       }
01394       else
01395       {
01396         bitstatus = RESET;
01397       }
01398     }
01399   }
01400 #else
01401   /* Check the parameters */
01402   assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)) ;
01403   if(FLASH_FLAG == FLASH_FLAG_OPTERR)
01404   {
01405     if((FLASH->OBR & FLASH_FLAG_OPTERR) != (uint32_t)RESET)
01406     {
01407       bitstatus = SET;
01408     }
01409     else
01410     {
01411       bitstatus = RESET;
01412     }
01413   }
01414   else
01415   {
01416    if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET)
01417     {
01418       bitstatus = SET;
01419     }
01420     else
01421     {
01422       bitstatus = RESET;
01423     }
01424   }
01425 #endif /* STM32F10X_XL */
01426
01427   /* Return the new state of FLASH_FLAG (SET or RESET) */
01428   return bitstatus;
01429 }
01430
01431 /**
01432   * @brief  Clears the FLASH's pending flags.
01433   * @note   This function can be used for all STM32F10x devices.
01434   *         - For STM32F10X_XL devices, this function clears Bank1 or Bank2’s pending flags
01435   *         - For other devices, it clears Bank1’s pending flags.
01436   * @param  FLASH_FLAG: specifies the FLASH flags to clear.
01437   *   This parameter can be any combination of the following values:
01438   *     @arg FLASH_FLAG_PGERR: FLASH Program error flag
01439   *     @arg FLASH_FLAG_WRPRTERR: FLASH Write protected error flag
01440   *     @arg FLASH_FLAG_EOP: FLASH End of Operation flag
01441   * @retval None
01442   */
01443 void FLASH_ClearFlag(uint32_t FLASH_FLAG)
01444 {
01445 #ifdef STM32F10X_XL
01446   /* Check the parameters */
01447   assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)) ;
01448
01449   if((FLASH_FLAG & 0x80000000) != 0x0)
01450   {
01451     /* Clear the flags */
01452     FLASH->SR2 = FLASH_FLAG;
01453   }
01454   else
01455   {
01456     /* Clear the flags */
01457     FLASH->SR = FLASH_FLAG;
01458   }
01459
01460 #else
01461   /* Check the parameters */
01462   assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)) ;
01463
01464   /* Clear the flags */
01465   FLASH->SR = FLASH_FLAG;
01466 #endif /* STM32F10X_XL */
01467 }
01468
01469 /**
01470   * @brief  Returns the FLASH Status.
01471   * @note   This function can be used for all STM32F10x devices, it is equivalent
01472   *         to FLASH_GetBank1Status function.
01473   * @param  None
01474   * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
01475   *         FLASH_ERROR_WRP or FLASH_COMPLETE
01476   */
01477 FLASH_Status FLASH_GetStatus(void)
01478 {
01479   FLASH_Status flashstatus = FLASH_COMPLETE;
01480
01481   if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY)
01482   {
01483     flashstatus = FLASH_BUSY;
01484   }
01485   else
01486   {
01487     if((FLASH->SR & FLASH_FLAG_PGERR) != 0)
01488     {
01489       flashstatus = FLASH_ERROR_PG;
01490     }
01491     else
01492     {
01493       if((FLASH->SR & FLASH_FLAG_WRPRTERR) != 0 )
01494       {
01495         flashstatus = FLASH_ERROR_WRP;
01496       }
01497       else
01498       {
01499         flashstatus = FLASH_COMPLETE;
01500       }
01501     }
01502   }
01503   /* Return the Flash Status */
01504   return flashstatus;
01505 }
01506
01507 /**
01508   * @brief  Returns the FLASH Bank1 Status.
01509   * @note   This function can be used for all STM32F10x devices, it is equivalent
01510   *         to FLASH_GetStatus function.
01511   * @param  None
01512   * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
01513   *         FLASH_ERROR_WRP or FLASH_COMPLETE
01514   */
01515 FLASH_Status FLASH_GetBank1Status(void)
01516 {
01517   FLASH_Status flashstatus = FLASH_COMPLETE;
01518
01519   if((FLASH->SR & FLASH_FLAG_BANK1_BSY) == FLASH_FLAG_BSY)
01520   {
01521     flashstatus = FLASH_BUSY;
01522   }
01523   else
01524   {
01525     if((FLASH->SR & FLASH_FLAG_BANK1_PGERR) != 0)
01526     {
01527       flashstatus = FLASH_ERROR_PG;
01528     }
01529     else
01530     {
01531       if((FLASH->SR & FLASH_FLAG_BANK1_WRPRTERR) != 0 )
01532       {
01533         flashstatus = FLASH_ERROR_WRP;
01534       }
01535       else
01536       {
01537         flashstatus = FLASH_COMPLETE;
01538       }
01539     }
01540   }
01541   /* Return the Flash Status */
01542   return flashstatus;
01543 }
01544
01545 #ifdef STM32F10X_XL
01546 /**
01547   * @brief  Returns the FLASH Bank2 Status.
01548   * @note   This function can be used for STM32F10x_XL density devices.
01549   * @param  None
01550   * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
01551   *        FLASH_ERROR_WRP or FLASH_COMPLETE
01552   */
01553 FLASH_Status FLASH_GetBank2Status(void)
01554 {
01555   FLASH_Status flashstatus = FLASH_COMPLETE;
01556
01557   if((FLASH->SR2 & (FLASH_FLAG_BANK2_BSY & 0x7FFFFFFF)) == (FLASH_FLAG_BANK2_BSY & 0x7FFFFFFF))
01558   {
01559     flashstatus = FLASH_BUSY;
01560   }
01561   else
01562   {
01563     if((FLASH->SR2 & (FLASH_FLAG_BANK2_PGERR & 0x7FFFFFFF)) != 0)
01564     {
01565       flashstatus = FLASH_ERROR_PG;
01566     }
01567     else
01568     {
01569       if((FLASH->SR2 & (FLASH_FLAG_BANK2_WRPRTERR & 0x7FFFFFFF)) != 0 )
01570       {
01571         flashstatus = FLASH_ERROR_WRP;
01572       }
01573       else
01574       {
01575         flashstatus = FLASH_COMPLETE;
01576       }
01577     }
01578   }
01579   /* Return the Flash Status */
01580   return flashstatus;
01581 }
01582 #endif /* STM32F10X_XL */
01583 /**
01584   * @brief  Waits for a Flash operation to complete or a TIMEOUT to occur.
01585   * @note   This function can be used for all STM32F10x devices,
01586   *         it is equivalent to FLASH_WaitForLastBank1Operation.
01587   *         - For STM32F10X_XL devices this function waits for a Bank1 Flash operation
01588   *           to complete or a TIMEOUT to occur.
01589   *         - For all other devices it waits for a Flash operation to complete
01590   *           or a TIMEOUT to occur.
01591   * @param  Timeout: FLASH programming Timeout
01592   * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
01593   *         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
01594   */
01595 FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout)
01596 {
01597   FLASH_Status status = FLASH_COMPLETE;
01598
01599   /* Check for the Flash Status */
01600   status = FLASH_GetBank1Status();
01601   /* Wait for a Flash operation to complete or a TIMEOUT to occur */
01602   while((status == FLASH_BUSY) && (Timeout != 0x00))
01603   {
01604     status = FLASH_GetBank1Status();
01605     Timeout--;
01606   }
01607   if(Timeout == 0x00 )
01608   {
01609     status = FLASH_TIMEOUT;
01610   }
01611   /* Return the operation status */
01612   return status;
01613 }
01614
01615 /**
01616   * @brief  Waits for a Flash operation on Bank1 to complete or a TIMEOUT to occur.
01617   * @note   This function can be used for all STM32F10x devices,
01618   *         it is equivalent to FLASH_WaitForLastOperation.
01619   * @param  Timeout: FLASH programming Timeout
01620   * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
01621   *         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
01622   */
01623 FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout)
01624 {
01625   FLASH_Status status = FLASH_COMPLETE;
01626
01627   /* Check for the Flash Status */
01628   status = FLASH_GetBank1Status();
01629   /* Wait for a Flash operation to complete or a TIMEOUT to occur */
01630   while((status == FLASH_FLAG_BANK1_BSY) && (Timeout != 0x00))
01631   {
01632     status = FLASH_GetBank1Status();
01633     Timeout--;
01634   }
01635   if(Timeout == 0x00 )
01636   {
01637     status = FLASH_TIMEOUT;
01638   }
01639   /* Return the operation status */
01640   return status;
01641 }
01642
01643 #ifdef STM32F10X_XL
01644 /**
01645   * @brief  Waits for a Flash operation on Bank2 to complete or a TIMEOUT to occur.
01646   * @note   This function can be used only for STM32F10x_XL density devices.
01647   * @param  Timeout: FLASH programming Timeout
01648   * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
01649   *         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
01650   */
01651 FLASH_Status FLASH_WaitForLastBank2Operation(uint32_t Timeout)
01652 {
01653   FLASH_Status status = FLASH_COMPLETE;
01654
01655   /* Check for the Flash Status */
01656   status = FLASH_GetBank2Status();
01657   /* Wait for a Flash operation to complete or a TIMEOUT to occur */
01658   while((status == (FLASH_FLAG_BANK2_BSY & 0x7FFFFFFF)) && (Timeout != 0x00))
01659   {
01660     status = FLASH_GetBank2Status();
01661     Timeout--;
01662   }
01663   if(Timeout == 0x00 )
01664   {
01665     status = FLASH_TIMEOUT;
01666   }
01667   /* Return the operation status */
01668   return status;
01669 }
01670 #endif /* STM32F10X_XL */
01671
01672 /**
01673   * @}
01674   */
01675
01676 /**
01677   * @}
01678   */
01679
01680 /**
01681   * @}
01682   */
01683
01684 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_flash.h Source File

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stm32f10x_flash.h

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f10x_flash.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    11-March-2011
00007   * @brief   This file contains all the functions prototypes for the FLASH
00008   *          firmware library.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00013   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00014   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00015   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00016   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00017   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00018   *
00019   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00020   ******************************************************************************
00021   */
00022
00023 /* Define to prevent recursive inclusion -------------------------------------*/
00024 #ifndef __STM32F10x_FLASH_H
00025 #define __STM32F10x_FLASH_H
00026
00027 #ifdef __cplusplus
00028  extern "C" {
00029 #endif
00030
00031 /* Includes ------------------------------------------------------------------*/
00032 #include "stm32f10x.h"
00033
00034 /** @addtogroup STM32F10x_StdPeriph_Driver
00035   * @{
00036   */
00037
00038 /** @addtogroup FLASH
00039   * @{
00040   */
00041
00042 /** @defgroup FLASH_Exported_Types
00043   * @{
00044   */
00045
00046 /**
00047   * @brief  FLASH Status
00048   */
00049
00050 typedef enum
00051 {
00052   FLASH_BUSY = 1,
00053   FLASH_ERROR_PG,
00054   FLASH_ERROR_WRP,
00055   FLASH_COMPLETE,
00056   FLASH_TIMEOUT
00057 }FLASH_Status;
00058
00059 /**
00060   * @}
00061   */
00062
00063 /** @defgroup FLASH_Exported_Constants
00064   * @{
00065   */
00066
00067 /** @defgroup Flash_Latency
00068   * @{
00069   */
00070
00071 #define FLASH_Latency_0                ((uint32_t)0x00000000)  /*!< FLASH Zero Latency cycle */
00072 #define FLASH_Latency_1                ((uint32_t)0x00000001)  /*!< FLASH One Latency cycle */
00073 #define FLASH_Latency_2                ((uint32_t)0x00000002)  /*!< FLASH Two Latency cycles */
00074 #define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \
00075                                    ((LATENCY) == FLASH_Latency_1) || \
00076                                    ((LATENCY) == FLASH_Latency_2))
00077 /**
00078   * @}
00079   */
00080
00081 /** @defgroup Half_Cycle_Enable_Disable
00082   * @{
00083   */
00084
00085 #define FLASH_HalfCycleAccess_Enable   ((uint32_t)0x00000008)  /*!< FLASH Half Cycle Enable */
00086 #define FLASH_HalfCycleAccess_Disable  ((uint32_t)0x00000000)  /*!< FLASH Half Cycle Disable */
00087 #define IS_FLASH_HALFCYCLEACCESS_STATE(STATE) (((STATE) == FLASH_HalfCycleAccess_Enable) || \
00088                                                ((STATE) == FLASH_HalfCycleAccess_Disable))
00089 /**
00090   * @}
00091   */
00092
00093 /** @defgroup Prefetch_Buffer_Enable_Disable
00094   * @{
00095   */
00096
00097 #define FLASH_PrefetchBuffer_Enable    ((uint32_t)0x00000010)  /*!< FLASH Prefetch Buffer Enable */
00098 #define FLASH_PrefetchBuffer_Disable   ((uint32_t)0x00000000)  /*!< FLASH Prefetch Buffer Disable */
00099 #define IS_FLASH_PREFETCHBUFFER_STATE(STATE) (((STATE) == FLASH_PrefetchBuffer_Enable) || \
00100                                               ((STATE) == FLASH_PrefetchBuffer_Disable))
00101 /**
00102   * @}
00103   */
00104
00105 /** @defgroup Option_Bytes_Write_Protection
00106   * @{
00107   */
00108
00109 /* Values to be used with STM32 Low and Medium density devices */
00110 #define FLASH_WRProt_Pages0to3         ((uint32_t)0x00000001) /*!< STM32 Low and Medium density devices: Write protection of page 0 to 3 */
00111 #define FLASH_WRProt_Pages4to7         ((uint32_t)0x00000002) /*!< STM32 Low and Medium density devices: Write protection of page 4 to 7 */
00112 #define FLASH_WRProt_Pages8to11        ((uint32_t)0x00000004) /*!< STM32 Low and Medium density devices: Write protection of page 8 to 11 */
00113 #define FLASH_WRProt_Pages12to15       ((uint32_t)0x00000008) /*!< STM32 Low and Medium density devices: Write protection of page 12 to 15 */
00114 #define FLASH_WRProt_Pages16to19       ((uint32_t)0x00000010) /*!< STM32 Low and Medium density devices: Write protection of page 16 to 19 */
00115 #define FLASH_WRProt_Pages20to23       ((uint32_t)0x00000020) /*!< STM32 Low and Medium density devices: Write protection of page 20 to 23 */
00116 #define FLASH_WRProt_Pages24to27       ((uint32_t)0x00000040) /*!< STM32 Low and Medium density devices: Write protection of page 24 to 27 */
00117 #define FLASH_WRProt_Pages28to31       ((uint32_t)0x00000080) /*!< STM32 Low and Medium density devices: Write protection of page 28 to 31 */
00118
00119 /* Values to be used with STM32 Medium-density devices */
00120 #define FLASH_WRProt_Pages32to35       ((uint32_t)0x00000100) /*!< STM32 Medium-density devices: Write protection of page 32 to 35 */
00121 #define FLASH_WRProt_Pages36to39       ((uint32_t)0x00000200) /*!< STM32 Medium-density devices: Write protection of page 36 to 39 */
00122 #define FLASH_WRProt_Pages40to43       ((uint32_t)0x00000400) /*!< STM32 Medium-density devices: Write protection of page 40 to 43 */
00123 #define FLASH_WRProt_Pages44to47       ((uint32_t)0x00000800) /*!< STM32 Medium-density devices: Write protection of page 44 to 47 */
00124 #define FLASH_WRProt_Pages48to51       ((uint32_t)0x00001000) /*!< STM32 Medium-density devices: Write protection of page 48 to 51 */
00125 #define FLASH_WRProt_Pages52to55       ((uint32_t)0x00002000) /*!< STM32 Medium-density devices: Write protection of page 52 to 55 */
00126 #define FLASH_WRProt_Pages56to59       ((uint32_t)0x00004000) /*!< STM32 Medium-density devices: Write protection of page 56 to 59 */
00127 #define FLASH_WRProt_Pages60to63       ((uint32_t)0x00008000) /*!< STM32 Medium-density devices: Write protection of page 60 to 63 */
00128 #define FLASH_WRProt_Pages64to67       ((uint32_t)0x00010000) /*!< STM32 Medium-density devices: Write protection of page 64 to 67 */
00129 #define FLASH_WRProt_Pages68to71       ((uint32_t)0x00020000) /*!< STM32 Medium-density devices: Write protection of page 68 to 71 */
00130 #define FLASH_WRProt_Pages72to75       ((uint32_t)0x00040000) /*!< STM32 Medium-density devices: Write protection of page 72 to 75 */
00131 #define FLASH_WRProt_Pages76to79       ((uint32_t)0x00080000) /*!< STM32 Medium-density devices: Write protection of page 76 to 79 */
00132 #define FLASH_WRProt_Pages80to83       ((uint32_t)0x00100000) /*!< STM32 Medium-density devices: Write protection of page 80 to 83 */
00133 #define FLASH_WRProt_Pages84to87       ((uint32_t)0x00200000) /*!< STM32 Medium-density devices: Write protection of page 84 to 87 */
00134 #define FLASH_WRProt_Pages88to91       ((uint32_t)0x00400000) /*!< STM32 Medium-density devices: Write protection of page 88 to 91 */
00135 #define FLASH_WRProt_Pages92to95       ((uint32_t)0x00800000) /*!< STM32 Medium-density devices: Write protection of page 92 to 95 */
00136 #define FLASH_WRProt_Pages96to99       ((uint32_t)0x01000000) /*!< STM32 Medium-density devices: Write protection of page 96 to 99 */
00137 #define FLASH_WRProt_Pages100to103     ((uint32_t)0x02000000) /*!< STM32 Medium-density devices: Write protection of page 100 to 103 */
00138 #define FLASH_WRProt_Pages104to107     ((uint32_t)0x04000000) /*!< STM32 Medium-density devices: Write protection of page 104 to 107 */
00139 #define FLASH_WRProt_Pages108to111     ((uint32_t)0x08000000) /*!< STM32 Medium-density devices: Write protection of page 108 to 111 */
00140 #define FLASH_WRProt_Pages112to115     ((uint32_t)0x10000000) /*!< STM32 Medium-density devices: Write protection of page 112 to 115 */
00141 #define FLASH_WRProt_Pages116to119     ((uint32_t)0x20000000) /*!< STM32 Medium-density devices: Write protection of page 115 to 119 */
00142 #define FLASH_WRProt_Pages120to123     ((uint32_t)0x40000000) /*!< STM32 Medium-density devices: Write protection of page 120 to 123 */
00143 #define FLASH_WRProt_Pages124to127     ((uint32_t)0x80000000) /*!< STM32 Medium-density devices: Write protection of page 124 to 127 */
00144
00145 /* Values to be used with STM32 High-density and STM32F10X Connectivity line devices */
00146 #define FLASH_WRProt_Pages0to1         ((uint32_t)0x00000001) /*!< STM32 High-density, XL-density and Connectivity line devices:
00147                                                                    Write protection of page 0 to 1 */
00148 #define FLASH_WRProt_Pages2to3         ((uint32_t)0x00000002) /*!< STM32 High-density, XL-density and Connectivity line devices:
00149                                                                    Write protection of page 2 to 3 */
00150 #define FLASH_WRProt_Pages4to5         ((uint32_t)0x00000004) /*!< STM32 High-density, XL-density and Connectivity line devices:
00151                                                                    Write protection of page 4 to 5 */
00152 #define FLASH_WRProt_Pages6to7         ((uint32_t)0x00000008) /*!< STM32 High-density, XL-density and Connectivity line devices:
00153                                                                    Write protection of page 6 to 7 */
00154 #define FLASH_WRProt_Pages8to9         ((uint32_t)0x00000010) /*!< STM32 High-density, XL-density and Connectivity line devices:
00155                                                                    Write protection of page 8 to 9 */
00156 #define FLASH_WRProt_Pages10to11       ((uint32_t)0x00000020) /*!< STM32 High-density, XL-density and Connectivity line devices:
00157                                                                    Write protection of page 10 to 11 */
00158 #define FLASH_WRProt_Pages12to13       ((uint32_t)0x00000040) /*!< STM32 High-density, XL-density and Connectivity line devices:
00159                                                                    Write protection of page 12 to 13 */
00160 #define FLASH_WRProt_Pages14to15       ((uint32_t)0x00000080) /*!< STM32 High-density, XL-density and Connectivity line devices:
00161                                                                    Write protection of page 14 to 15 */
00162 #define FLASH_WRProt_Pages16to17       ((uint32_t)0x00000100) /*!< STM32 High-density, XL-density and Connectivity line devices:
00163                                                                    Write protection of page 16 to 17 */
00164 #define FLASH_WRProt_Pages18to19       ((uint32_t)0x00000200) /*!< STM32 High-density, XL-density and Connectivity line devices:
00165                                                                    Write protection of page 18 to 19 */
00166 #define FLASH_WRProt_Pages20to21       ((uint32_t)0x00000400) /*!< STM32 High-density, XL-density and Connectivity line devices:
00167                                                                    Write protection of page 20 to 21 */
00168 #define FLASH_WRProt_Pages22to23       ((uint32_t)0x00000800) /*!< STM32 High-density, XL-density and Connectivity line devices:
00169                                                                    Write protection of page 22 to 23 */
00170 #define FLASH_WRProt_Pages24to25       ((uint32_t)0x00001000) /*!< STM32 High-density, XL-density and Connectivity line devices:
00171                                                                    Write protection of page 24 to 25 */
00172 #define FLASH_WRProt_Pages26to27       ((uint32_t)0x00002000) /*!< STM32 High-density, XL-density and Connectivity line devices:
00173                                                                    Write protection of page 26 to 27 */
00174 #define FLASH_WRProt_Pages28to29       ((uint32_t)0x00004000) /*!< STM32 High-density, XL-density and Connectivity line devices:
00175                                                                    Write protection of page 28 to 29 */
00176 #define FLASH_WRProt_Pages30to31       ((uint32_t)0x00008000) /*!< STM32 High-density, XL-density and Connectivity line devices:
00177                                                                    Write protection of page 30 to 31 */
00178 #define FLASH_WRProt_Pages32to33       ((uint32_t)0x00010000) /*!< STM32 High-density, XL-density and Connectivity line devices:
00179                                                                    Write protection of page 32 to 33 */
00180 #define FLASH_WRProt_Pages34to35       ((uint32_t)0x00020000) /*!< STM32 High-density, XL-density and Connectivity line devices:
00181                                                                    Write protection of page 34 to 35 */
00182 #define FLASH_WRProt_Pages36to37       ((uint32_t)0x00040000) /*!< STM32 High-density, XL-density and Connectivity line devices:
00183                                                                    Write protection of page 36 to 37 */
00184 #define FLASH_WRProt_Pages38to39       ((uint32_t)0x00080000) /*!< STM32 High-density, XL-density and Connectivity line devices:
00185                                                                    Write protection of page 38 to 39 */
00186 #define FLASH_WRProt_Pages40to41       ((uint32_t)0x00100000) /*!< STM32 High-density, XL-density and Connectivity line devices:
00187                                                                    Write protection of page 40 to 41 */
00188 #define FLASH_WRProt_Pages42to43       ((uint32_t)0x00200000) /*!< STM32 High-density, XL-density and Connectivity line devices:
00189                                                                    Write protection of page 42 to 43 */
00190 #define FLASH_WRProt_Pages44to45       ((uint32_t)0x00400000) /*!< STM32 High-density, XL-density and Connectivity line devices:
00191                                                                    Write protection of page 44 to 45 */
00192 #define FLASH_WRProt_Pages46to47       ((uint32_t)0x00800000) /*!< STM32 High-density, XL-density and Connectivity line devices:
00193                                                                    Write protection of page 46 to 47 */
00194 #define FLASH_WRProt_Pages48to49       ((uint32_t)0x01000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
00195                                                                    Write protection of page 48 to 49 */
00196 #define FLASH_WRProt_Pages50to51       ((uint32_t)0x02000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
00197                                                                    Write protection of page 50 to 51 */
00198 #define FLASH_WRProt_Pages52to53       ((uint32_t)0x04000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
00199                                                                    Write protection of page 52 to 53 */
00200 #define FLASH_WRProt_Pages54to55       ((uint32_t)0x08000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
00201                                                                    Write protection of page 54 to 55 */
00202 #define FLASH_WRProt_Pages56to57       ((uint32_t)0x10000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
00203                                                                    Write protection of page 56 to 57 */
00204 #define FLASH_WRProt_Pages58to59       ((uint32_t)0x20000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
00205                                                                    Write protection of page 58 to 59 */
00206 #define FLASH_WRProt_Pages60to61       ((uint32_t)0x40000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
00207                                                                    Write protection of page 60 to 61 */
00208 #define FLASH_WRProt_Pages62to127      ((uint32_t)0x80000000) /*!< STM32 Connectivity line devices: Write protection of page 62 to 127 */
00209 #define FLASH_WRProt_Pages62to255      ((uint32_t)0x80000000) /*!< STM32 Medium-density devices: Write protection of page 62 to 255 */
00210 #define FLASH_WRProt_Pages62to511      ((uint32_t)0x80000000) /*!< STM32 XL-density devices: Write protection of page 62 to 511 */
00211
00212 #define FLASH_WRProt_AllPages          ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Pages */
00213
00214 #define IS_FLASH_WRPROT_PAGE(PAGE) (((PAGE) != 0x00000000))
00215
00216 #define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x080FFFFF))
00217
00218 #define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == 0x1FFFF804) || ((ADDRESS) == 0x1FFFF806))
00219
00220 /**
00221   * @}
00222   */
00223
00224 /** @defgroup Option_Bytes_IWatchdog
00225   * @{
00226   */
00227
00228 #define OB_IWDG_SW                     ((uint16_t)0x0001)  /*!< Software IWDG selected */
00229 #define OB_IWDG_HW                     ((uint16_t)0x0000)  /*!< Hardware IWDG selected */
00230 #define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
00231
00232 /**
00233   * @}
00234   */
00235
00236 /** @defgroup Option_Bytes_nRST_STOP
00237   * @{
00238   */
00239
00240 #define OB_STOP_NoRST                  ((uint16_t)0x0002) /*!< No reset generated when entering in STOP */
00241 #define OB_STOP_RST                    ((uint16_t)0x0000) /*!< Reset generated when entering in STOP */
00242 #define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST))
00243
00244 /**
00245   * @}
00246   */
00247
00248 /** @defgroup Option_Bytes_nRST_STDBY
00249   * @{
00250   */
00251
00252 #define OB_STDBY_NoRST                 ((uint16_t)0x0004) /*!< No reset generated when entering in STANDBY */
00253 #define OB_STDBY_RST                   ((uint16_t)0x0000) /*!< Reset generated when entering in STANDBY */
00254 #define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST))
00255
00256 #ifdef STM32F10X_XL
00257 /**
00258   * @}
00259   */
00260 /** @defgroup FLASH_Boot
00261   * @{
00262   */
00263 #define FLASH_BOOT_Bank1  ((uint16_t)0x0000) /*!< At startup, if boot pins are set in boot from user Flash position
00264                                                   and this parameter is selected the device will boot from Bank1(Default) */
00265 #define FLASH_BOOT_Bank2  ((uint16_t)0x0001) /*!< At startup, if boot pins are set in boot from user Flash position
00266                                                   and this parameter is selected the device will boot from Bank 2 or Bank 1,
00267                                                   depending on the activation of the bank */
00268 #define IS_FLASH_BOOT(BOOT) (((BOOT) == FLASH_BOOT_Bank1) || ((BOOT) == FLASH_BOOT_Bank2))
00269 #endif
00270 /**
00271   * @}
00272   */
00273 /** @defgroup FLASH_Interrupts
00274   * @{
00275   */
00276 #ifdef STM32F10X_XL
00277 #define FLASH_IT_BANK2_ERROR                 ((uint32_t)0x80000400)  /*!< FPEC BANK2 error interrupt source */
00278 #define FLASH_IT_BANK2_EOP                   ((uint32_t)0x80001000)  /*!< End of FLASH BANK2 Operation Interrupt source */
00279
00280 #define FLASH_IT_BANK1_ERROR                 FLASH_IT_ERROR          /*!< FPEC BANK1 error interrupt source */
00281 #define FLASH_IT_BANK1_EOP                   FLASH_IT_EOP            /*!< End of FLASH BANK1 Operation Interrupt source */
00282
00283 #define FLASH_IT_ERROR                 ((uint32_t)0x00000400)  /*!< FPEC BANK1 error interrupt source */
00284 #define FLASH_IT_EOP                   ((uint32_t)0x00001000)  /*!< End of FLASH BANK1 Operation Interrupt source */
00285 #define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0x7FFFEBFF) == 0x00000000) && (((IT) != 0x00000000)))
00286 #else
00287 #define FLASH_IT_ERROR                 ((uint32_t)0x00000400)  /*!< FPEC error interrupt source */
00288 #define FLASH_IT_EOP                   ((uint32_t)0x00001000)  /*!< End of FLASH Operation Interrupt source */
00289 #define FLASH_IT_BANK1_ERROR           FLASH_IT_ERROR          /*!< FPEC BANK1 error interrupt source */
00290 #define FLASH_IT_BANK1_EOP             FLASH_IT_EOP            /*!< End of FLASH BANK1 Operation Interrupt source */
00291
00292 #define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFFEBFF) == 0x00000000) && (((IT) != 0x00000000)))
00293 #endif
00294
00295 /**
00296   * @}
00297   */
00298
00299 /** @defgroup FLASH_Flags
00300   * @{
00301   */
00302 #ifdef STM32F10X_XL
00303 #define FLASH_FLAG_BANK2_BSY                 ((uint32_t)0x80000001)  /*!< FLASH BANK2 Busy flag */
00304 #define FLASH_FLAG_BANK2_EOP                 ((uint32_t)0x80000020)  /*!< FLASH BANK2 End of Operation flag */
00305 #define FLASH_FLAG_BANK2_PGERR               ((uint32_t)0x80000004)  /*!< FLASH BANK2 Program error flag */
00306 #define FLASH_FLAG_BANK2_WRPRTERR            ((uint32_t)0x80000010)  /*!< FLASH BANK2 Write protected error flag */
00307
00308 #define FLASH_FLAG_BANK1_BSY                 FLASH_FLAG_BSY       /*!< FLASH BANK1 Busy flag*/
00309 #define FLASH_FLAG_BANK1_EOP                 FLASH_FLAG_EOP       /*!< FLASH BANK1 End of Operation flag */
00310 #define FLASH_FLAG_BANK1_PGERR               FLASH_FLAG_PGERR     /*!< FLASH BANK1 Program error flag */
00311 #define FLASH_FLAG_BANK1_WRPRTERR            FLASH_FLAG_WRPRTERR  /*!< FLASH BANK1 Write protected error flag */
00312
00313 #define FLASH_FLAG_BSY                 ((uint32_t)0x00000001)  /*!< FLASH Busy flag */
00314 #define FLASH_FLAG_EOP                 ((uint32_t)0x00000020)  /*!< FLASH End of Operation flag */
00315 #define FLASH_FLAG_PGERR               ((uint32_t)0x00000004)  /*!< FLASH Program error flag */
00316 #define FLASH_FLAG_WRPRTERR            ((uint32_t)0x00000010)  /*!< FLASH Write protected error flag */
00317 #define FLASH_FLAG_OPTERR              ((uint32_t)0x00000001)  /*!< FLASH Option Byte error flag */
00318
00319 #define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0x7FFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000))
00320 #define IS_FLASH_GET_FLAG(FLAG)  (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \
00321                                   ((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || \
00322                                   ((FLAG) == FLASH_FLAG_OPTERR)|| \
00323                                   ((FLAG) == FLASH_FLAG_BANK1_BSY) || ((FLAG) == FLASH_FLAG_BANK1_EOP) || \
00324                                   ((FLAG) == FLASH_FLAG_BANK1_PGERR) || ((FLAG) == FLASH_FLAG_BANK1_WRPRTERR) || \
00325                                   ((FLAG) == FLASH_FLAG_BANK2_BSY) || ((FLAG) == FLASH_FLAG_BANK2_EOP) || \
00326                                   ((FLAG) == FLASH_FLAG_BANK2_PGERR) || ((FLAG) == FLASH_FLAG_BANK2_WRPRTERR))
00327 #else
00328 #define FLASH_FLAG_BSY                 ((uint32_t)0x00000001)  /*!< FLASH Busy flag */
00329 #define FLASH_FLAG_EOP                 ((uint32_t)0x00000020)  /*!< FLASH End of Operation flag */
00330 #define FLASH_FLAG_PGERR               ((uint32_t)0x00000004)  /*!< FLASH Program error flag */
00331 #define FLASH_FLAG_WRPRTERR            ((uint32_t)0x00000010)  /*!< FLASH Write protected error flag */
00332 #define FLASH_FLAG_OPTERR              ((uint32_t)0x00000001)  /*!< FLASH Option Byte error flag */
00333
00334 #define FLASH_FLAG_BANK1_BSY                 FLASH_FLAG_BSY       /*!< FLASH BANK1 Busy flag*/
00335 #define FLASH_FLAG_BANK1_EOP                 FLASH_FLAG_EOP       /*!< FLASH BANK1 End of Operation flag */
00336 #define FLASH_FLAG_BANK1_PGERR               FLASH_FLAG_PGERR     /*!< FLASH BANK1 Program error flag */
00337 #define FLASH_FLAG_BANK1_WRPRTERR            FLASH_FLAG_WRPRTERR  /*!< FLASH BANK1 Write protected error flag */
00338
00339 #define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000))
00340 #define IS_FLASH_GET_FLAG(FLAG)  (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \
00341                                   ((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || \
00342                                                                   ((FLAG) == FLASH_FLAG_BANK1_BSY) || ((FLAG) == FLASH_FLAG_BANK1_EOP) || \
00343                                   ((FLAG) == FLASH_FLAG_BANK1_PGERR) || ((FLAG) == FLASH_FLAG_BANK1_WRPRTERR) || \
00344                                   ((FLAG) == FLASH_FLAG_OPTERR))
00345 #endif
00346
00347 /**
00348   * @}
00349   */
00350
00351 /**
00352   * @}
00353   */
00354
00355 /** @defgroup FLASH_Exported_Macros
00356   * @{
00357   */
00358
00359 /**
00360   * @}
00361   */
00362
00363 /** @defgroup FLASH_Exported_Functions
00364   * @{
00365   */
00366
00367 /*------------ Functions used for all STM32F10x devices -----*/
00368 void FLASH_SetLatency(uint32_t FLASH_Latency);
00369 void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess);
00370 void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer);
00371 void FLASH_Unlock(void);
00372 void FLASH_Lock(void);
00373 FLASH_Status FLASH_ErasePage(uint32_t Page_Address);
00374 FLASH_Status FLASH_EraseAllPages(void);
00375 FLASH_Status FLASH_EraseOptionBytes(void);
00376 FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);
00377 FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);
00378 FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data);
00379 FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages);
00380 FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState);
00381 FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY);
00382 uint32_t FLASH_GetUserOptionByte(void);
00383 uint32_t FLASH_GetWriteProtectionOptionByte(void);
00384 FlagStatus FLASH_GetReadOutProtectionStatus(void);
00385 FlagStatus FLASH_GetPrefetchBufferStatus(void);
00386 void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);
00387 FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG);
00388 void FLASH_ClearFlag(uint32_t FLASH_FLAG);
00389 FLASH_Status FLASH_GetStatus(void);
00390 FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout);
00391
00392 /*------------ New function used for all STM32F10x devices -----*/
00393 void FLASH_UnlockBank1(void);
00394 void FLASH_LockBank1(void);
00395 FLASH_Status FLASH_EraseAllBank1Pages(void);
00396 FLASH_Status FLASH_GetBank1Status(void);
00397 FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout);
00398
00399 #ifdef STM32F10X_XL
00400 /*---- New Functions used only with STM32F10x_XL density devices -----*/
00401 void FLASH_UnlockBank2(void);
00402 void FLASH_LockBank2(void);
00403 FLASH_Status FLASH_EraseAllBank2Pages(void);
00404 FLASH_Status FLASH_GetBank2Status(void);
00405 FLASH_Status FLASH_WaitForLastBank2Operation(uint32_t Timeout);
00406 FLASH_Status FLASH_BootConfig(uint16_t FLASH_BOOT);
00407 #endif
00408
00409 #ifdef __cplusplus
00410 }
00411 #endif
00412
00413 #endif /* __STM32F10x_FLASH_H */
00414 /**
00415   * @}
00416   */
00417
00418 /**
00419   * @}
00420   */
00421
00422 /**
00423   * @}
00424   */
00425
00426 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_fsmc.c Source File

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stm32f10x_fsmc.c

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f10x_fsmc.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    11-March-2011
00007   * @brief   This file provides all the FSMC firmware functions.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x_fsmc.h"
00024 #include "stm32f10x_rcc.h"
00025
00026 /** @addtogroup STM32F10x_StdPeriph_Driver
00027   * @{
00028   */
00029
00030 /** @defgroup FSMC
00031   * @brief FSMC driver modules
00032   * @{
00033   */
00034
00035 /** @defgroup FSMC_Private_TypesDefinitions
00036   * @{
00037   */
00038 /**
00039   * @}
00040   */
00041
00042 /** @defgroup FSMC_Private_Defines
00043   * @{
00044   */
00045
00046 /* --------------------- FSMC registers bit mask ---------------------------- */
00047
00048 /* FSMC BCRx Mask */
00049 #define BCR_MBKEN_Set                       ((uint32_t)0x00000001)
00050 #define BCR_MBKEN_Reset                     ((uint32_t)0x000FFFFE)
00051 #define BCR_FACCEN_Set                      ((uint32_t)0x00000040)
00052
00053 /* FSMC PCRx Mask */
00054 #define PCR_PBKEN_Set                       ((uint32_t)0x00000004)
00055 #define PCR_PBKEN_Reset                     ((uint32_t)0x000FFFFB)
00056 #define PCR_ECCEN_Set                       ((uint32_t)0x00000040)
00057 #define PCR_ECCEN_Reset                     ((uint32_t)0x000FFFBF)
00058 #define PCR_MemoryType_NAND                 ((uint32_t)0x00000008)
00059 /**
00060   * @}
00061   */
00062
00063 /** @defgroup FSMC_Private_Macros
00064   * @{
00065   */
00066
00067 /**
00068   * @}
00069   */
00070
00071 /** @defgroup FSMC_Private_Variables
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @defgroup FSMC_Private_FunctionPrototypes
00080   * @{
00081   */
00082
00083 /**
00084   * @}
00085   */
00086
00087 /** @defgroup FSMC_Private_Functions
00088   * @{
00089   */
00090
00091 /**
00092   * @brief  Deinitializes the FSMC NOR/SRAM Banks registers to their default
00093   *         reset values.
00094   * @param  FSMC_Bank: specifies the FSMC Bank to be used
00095   *   This parameter can be one of the following values:
00096   *     @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1
00097   *     @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2
00098   *     @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3
00099   *     @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4
00100   * @retval None
00101   */
00102 void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank)
00103 {
00104   /* Check the parameter */
00105   assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));
00106
00107   /* FSMC_Bank1_NORSRAM1 */
00108   if(FSMC_Bank == FSMC_Bank1_NORSRAM1)
00109   {
00110     FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB;
00111   }
00112   /* FSMC_Bank1_NORSRAM2,  FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */
00113   else
00114   {
00115     FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2;
00116   }
00117   FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF;
00118   FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF;
00119 }
00120
00121 /**
00122   * @brief  Deinitializes the FSMC NAND Banks registers to their default reset values.
00123   * @param  FSMC_Bank: specifies the FSMC Bank to be used
00124   *   This parameter can be one of the following values:
00125   *     @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
00126   *     @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
00127   * @retval None
00128   */
00129 void FSMC_NANDDeInit(uint32_t FSMC_Bank)
00130 {
00131   /* Check the parameter */
00132   assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
00133
00134   if(FSMC_Bank == FSMC_Bank2_NAND)
00135   {
00136     /* Set the FSMC_Bank2 registers to their reset values */
00137     FSMC_Bank2->PCR2 = 0x00000018;
00138     FSMC_Bank2->SR2 = 0x00000040;
00139     FSMC_Bank2->PMEM2 = 0xFCFCFCFC;
00140     FSMC_Bank2->PATT2 = 0xFCFCFCFC;
00141   }
00142   /* FSMC_Bank3_NAND */
00143   else
00144   {
00145     /* Set the FSMC_Bank3 registers to their reset values */
00146     FSMC_Bank3->PCR3 = 0x00000018;
00147     FSMC_Bank3->SR3 = 0x00000040;
00148     FSMC_Bank3->PMEM3 = 0xFCFCFCFC;
00149     FSMC_Bank3->PATT3 = 0xFCFCFCFC;
00150   }
00151 }
00152
00153 /**
00154   * @brief  Deinitializes the FSMC PCCARD Bank registers to their default reset values.
00155   * @param  None
00156   * @retval None
00157   */
00158 void FSMC_PCCARDDeInit(void)
00159 {
00160   /* Set the FSMC_Bank4 registers to their reset values */
00161   FSMC_Bank4->PCR4 = 0x00000018;
00162   FSMC_Bank4->SR4 = 0x00000000;
00163   FSMC_Bank4->PMEM4 = 0xFCFCFCFC;
00164   FSMC_Bank4->PATT4 = 0xFCFCFCFC;
00165   FSMC_Bank4->PIO4 = 0xFCFCFCFC;
00166 }
00167
00168 /**
00169   * @brief  Initializes the FSMC NOR/SRAM Banks according to the specified
00170   *         parameters in the FSMC_NORSRAMInitStruct.
00171   * @param  FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef
00172   *         structure that contains the configuration information for
00173   *        the FSMC NOR/SRAM specified Banks.
00174   * @retval None
00175   */
00176 void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
00177 {
00178   /* Check the parameters */
00179   assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank));
00180   assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux));
00181   assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType));
00182   assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth));
00183   assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode));
00184   assert_param(IS_FSMC_ASYNWAIT(FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait));
00185   assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity));
00186   assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode));
00187   assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive));
00188   assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation));
00189   assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal));
00190   assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode));
00191   assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst));
00192   assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime));
00193   assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime));
00194   assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime));
00195   assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration));
00196   assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision));
00197   assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency));
00198   assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode));
00199
00200   /* Bank1 NOR/SRAM control register configuration */
00201   FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
00202             (uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux |
00203             FSMC_NORSRAMInitStruct->FSMC_MemoryType |
00204             FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth |
00205             FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode |
00206             FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait |
00207             FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity |
00208             FSMC_NORSRAMInitStruct->FSMC_WrapMode |
00209             FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive |
00210             FSMC_NORSRAMInitStruct->FSMC_WriteOperation |
00211             FSMC_NORSRAMInitStruct->FSMC_WaitSignal |
00212             FSMC_NORSRAMInitStruct->FSMC_ExtendedMode |
00213             FSMC_NORSRAMInitStruct->FSMC_WriteBurst;
00214
00215   if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR)
00216   {
00217     FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_Set;
00218   }
00219
00220   /* Bank1 NOR/SRAM timing register configuration */
00221   FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] =
00222             (uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime |
00223             (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) |
00224             (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) |
00225             (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) |
00226             (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) |
00227             (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) |
00228              FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode;
00229
00230
00231   /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */
00232   if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable)
00233   {
00234     assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime));
00235     assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime));
00236     assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime));
00237     assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision));
00238     assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency));
00239     assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode));
00240     FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
00241               (uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime |
00242               (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )|
00243               (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) |
00244               (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) |
00245               (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) |
00246                FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode;
00247   }
00248   else
00249   {
00250     FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF;
00251   }
00252 }
00253
00254 /**
00255   * @brief  Initializes the FSMC NAND Banks according to the specified
00256   *         parameters in the FSMC_NANDInitStruct.
00257   * @param  FSMC_NANDInitStruct : pointer to a FSMC_NANDInitTypeDef
00258   *         structure that contains the configuration information for the FSMC
00259   *         NAND specified Banks.
00260   * @retval None
00261   */
00262 void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)
00263 {
00264   uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000;
00265
00266   /* Check the parameters */
00267   assert_param( IS_FSMC_NAND_BANK(FSMC_NANDInitStruct->FSMC_Bank));
00268   assert_param( IS_FSMC_WAIT_FEATURE(FSMC_NANDInitStruct->FSMC_Waitfeature));
00269   assert_param( IS_FSMC_MEMORY_WIDTH(FSMC_NANDInitStruct->FSMC_MemoryDataWidth));
00270   assert_param( IS_FSMC_ECC_STATE(FSMC_NANDInitStruct->FSMC_ECC));
00271   assert_param( IS_FSMC_ECCPAGE_SIZE(FSMC_NANDInitStruct->FSMC_ECCPageSize));
00272   assert_param( IS_FSMC_TCLR_TIME(FSMC_NANDInitStruct->FSMC_TCLRSetupTime));
00273   assert_param( IS_FSMC_TAR_TIME(FSMC_NANDInitStruct->FSMC_TARSetupTime));
00274   assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));
00275   assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));
00276   assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));
00277   assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));
00278   assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));
00279   assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));
00280   assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));
00281   assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));
00282
00283   /* Set the tmppcr value according to FSMC_NANDInitStruct parameters */
00284   tmppcr = (uint32_t)FSMC_NANDInitStruct->FSMC_Waitfeature |
00285             PCR_MemoryType_NAND |
00286             FSMC_NANDInitStruct->FSMC_MemoryDataWidth |
00287             FSMC_NANDInitStruct->FSMC_ECC |
00288             FSMC_NANDInitStruct->FSMC_ECCPageSize |
00289             (FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9 )|
00290             (FSMC_NANDInitStruct->FSMC_TARSetupTime << 13);
00291
00292   /* Set tmppmem value according to FSMC_CommonSpaceTimingStructure parameters */
00293   tmppmem = (uint32_t)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
00294             (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
00295             (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
00296             (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24);
00297
00298   /* Set tmppatt value according to FSMC_AttributeSpaceTimingStructure parameters */
00299   tmppatt = (uint32_t)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
00300             (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
00301             (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
00302             (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);
00303
00304   if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND)
00305   {
00306     /* FSMC_Bank2_NAND registers configuration */
00307     FSMC_Bank2->PCR2 = tmppcr;
00308     FSMC_Bank2->PMEM2 = tmppmem;
00309     FSMC_Bank2->PATT2 = tmppatt;
00310   }
00311   else
00312   {
00313     /* FSMC_Bank3_NAND registers configuration */
00314     FSMC_Bank3->PCR3 = tmppcr;
00315     FSMC_Bank3->PMEM3 = tmppmem;
00316     FSMC_Bank3->PATT3 = tmppatt;
00317   }
00318 }
00319
00320 /**
00321   * @brief  Initializes the FSMC PCCARD Bank according to the specified
00322   *         parameters in the FSMC_PCCARDInitStruct.
00323   * @param  FSMC_PCCARDInitStruct : pointer to a FSMC_PCCARDInitTypeDef
00324   *         structure that contains the configuration information for the FSMC
00325   *         PCCARD Bank.
00326   * @retval None
00327   */
00328 void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)
00329 {
00330   /* Check the parameters */
00331   assert_param(IS_FSMC_WAIT_FEATURE(FSMC_PCCARDInitStruct->FSMC_Waitfeature));
00332   assert_param(IS_FSMC_TCLR_TIME(FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime));
00333   assert_param(IS_FSMC_TAR_TIME(FSMC_PCCARDInitStruct->FSMC_TARSetupTime));
00334
00335   assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));
00336   assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));
00337   assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));
00338   assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));
00339
00340   assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));
00341   assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));
00342   assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));
00343   assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));
00344   assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime));
00345   assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime));
00346   assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime));
00347   assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime));
00348
00349   /* Set the PCR4 register value according to FSMC_PCCARDInitStruct parameters */
00350   FSMC_Bank4->PCR4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_Waitfeature |
00351                      FSMC_MemoryDataWidth_16b |
00352                      (FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime << 9) |
00353                      (FSMC_PCCARDInitStruct->FSMC_TARSetupTime << 13);
00354
00355   /* Set PMEM4 register value according to FSMC_CommonSpaceTimingStructure parameters */
00356   FSMC_Bank4->PMEM4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
00357                       (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
00358                       (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
00359                       (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24);
00360
00361   /* Set PATT4 register value according to FSMC_AttributeSpaceTimingStructure parameters */
00362   FSMC_Bank4->PATT4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
00363                       (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
00364                       (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
00365                       (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);
00366
00367   /* Set PIO4 register value according to FSMC_IOSpaceTimingStructure parameters */
00368   FSMC_Bank4->PIO4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime |
00369                      (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
00370                      (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
00371                      (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime << 24);
00372 }
00373
00374 /**
00375   * @brief  Fills each FSMC_NORSRAMInitStruct member with its default value.
00376   * @param  FSMC_NORSRAMInitStruct: pointer to a FSMC_NORSRAMInitTypeDef
00377   *         structure which will be initialized.
00378   * @retval None
00379   */
00380 void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
00381 {
00382   /* Reset NOR/SRAM Init structure parameters values */
00383   FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1;
00384   FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable;
00385   FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM;
00386   FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
00387   FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
00388   FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
00389   FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
00390   FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable;
00391   FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
00392   FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable;
00393   FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable;
00394   FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
00395   FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable;
00396   FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF;
00397   FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF;
00398   FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF;
00399   FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
00400   FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF;
00401   FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF;
00402   FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;
00403   FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF;
00404   FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF;
00405   FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF;
00406   FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
00407   FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF;
00408   FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF;
00409   FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;
00410 }
00411
00412 /**
00413   * @brief  Fills each FSMC_NANDInitStruct member with its default value.
00414   * @param  FSMC_NANDInitStruct: pointer to a FSMC_NANDInitTypeDef
00415   *         structure which will be initialized.
00416   * @retval None
00417   */
00418 void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)
00419 {
00420   /* Reset NAND Init structure parameters values */
00421   FSMC_NANDInitStruct->FSMC_Bank = FSMC_Bank2_NAND;
00422   FSMC_NANDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;
00423   FSMC_NANDInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
00424   FSMC_NANDInitStruct->FSMC_ECC = FSMC_ECC_Disable;
00425   FSMC_NANDInitStruct->FSMC_ECCPageSize = FSMC_ECCPageSize_256Bytes;
00426   FSMC_NANDInitStruct->FSMC_TCLRSetupTime = 0x0;
00427   FSMC_NANDInitStruct->FSMC_TARSetupTime = 0x0;
00428   FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;
00429   FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
00430   FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
00431   FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
00432   FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;
00433   FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
00434   FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
00435   FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
00436 }
00437
00438 /**
00439   * @brief  Fills each FSMC_PCCARDInitStruct member with its default value.
00440   * @param  FSMC_PCCARDInitStruct: pointer to a FSMC_PCCARDInitTypeDef
00441   *         structure which will be initialized.
00442   * @retval None
00443   */
00444 void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)
00445 {
00446   /* Reset PCCARD Init structure parameters values */
00447   FSMC_PCCARDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;
00448   FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime = 0x0;
00449   FSMC_PCCARDInitStruct->FSMC_TARSetupTime = 0x0;
00450   FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;
00451   FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
00452   FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
00453   FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
00454   FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;
00455   FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
00456   FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
00457   FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
00458   FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime = 0xFC;
00459   FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
00460   FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
00461   FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
00462 }
00463
00464 /**
00465   * @brief  Enables or disables the specified NOR/SRAM Memory Bank.
00466   * @param  FSMC_Bank: specifies the FSMC Bank to be used
00467   *   This parameter can be one of the following values:
00468   *     @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1
00469   *     @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2
00470   *     @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3
00471   *     @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4
00472   * @param  NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.
00473   * @retval None
00474   */
00475 void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState)
00476 {
00477   assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));
00478   assert_param(IS_FUNCTIONAL_STATE(NewState));
00479
00480   if (NewState != DISABLE)
00481   {
00482     /* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */
00483     FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_Set;
00484   }
00485   else
00486   {
00487     /* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */
00488     FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_Reset;
00489   }
00490 }
00491
00492 /**
00493   * @brief  Enables or disables the specified NAND Memory Bank.
00494   * @param  FSMC_Bank: specifies the FSMC Bank to be used
00495   *   This parameter can be one of the following values:
00496   *     @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
00497   *     @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
00498   * @param  NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.
00499   * @retval None
00500   */
00501 void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState)
00502 {
00503   assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
00504   assert_param(IS_FUNCTIONAL_STATE(NewState));
00505
00506   if (NewState != DISABLE)
00507   {
00508     /* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */
00509     if(FSMC_Bank == FSMC_Bank2_NAND)
00510     {
00511       FSMC_Bank2->PCR2 |= PCR_PBKEN_Set;
00512     }
00513     else
00514     {
00515       FSMC_Bank3->PCR3 |= PCR_PBKEN_Set;
00516     }
00517   }
00518   else
00519   {
00520     /* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */
00521     if(FSMC_Bank == FSMC_Bank2_NAND)
00522     {
00523       FSMC_Bank2->PCR2 &= PCR_PBKEN_Reset;
00524     }
00525     else
00526     {
00527       FSMC_Bank3->PCR3 &= PCR_PBKEN_Reset;
00528     }
00529   }
00530 }
00531
00532 /**
00533   * @brief  Enables or disables the PCCARD Memory Bank.
00534   * @param  NewState: new state of the PCCARD Memory Bank.
00535   *   This parameter can be: ENABLE or DISABLE.
00536   * @retval None
00537   */
00538 void FSMC_PCCARDCmd(FunctionalState NewState)
00539 {
00540   assert_param(IS_FUNCTIONAL_STATE(NewState));
00541
00542   if (NewState != DISABLE)
00543   {
00544     /* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */
00545     FSMC_Bank4->PCR4 |= PCR_PBKEN_Set;
00546   }
00547   else
00548   {
00549     /* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */
00550     FSMC_Bank4->PCR4 &= PCR_PBKEN_Reset;
00551   }
00552 }
00553
00554 /**
00555   * @brief  Enables or disables the FSMC NAND ECC feature.
00556   * @param  FSMC_Bank: specifies the FSMC Bank to be used
00557   *   This parameter can be one of the following values:
00558   *     @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
00559   *     @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
00560   * @param  NewState: new state of the FSMC NAND ECC feature.
00561   *   This parameter can be: ENABLE or DISABLE.
00562   * @retval None
00563   */
00564 void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState)
00565 {
00566   assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
00567   assert_param(IS_FUNCTIONAL_STATE(NewState));
00568
00569   if (NewState != DISABLE)
00570   {
00571     /* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */
00572     if(FSMC_Bank == FSMC_Bank2_NAND)
00573     {
00574       FSMC_Bank2->PCR2 |= PCR_ECCEN_Set;
00575     }
00576     else
00577     {
00578       FSMC_Bank3->PCR3 |= PCR_ECCEN_Set;
00579     }
00580   }
00581   else
00582   {
00583     /* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */
00584     if(FSMC_Bank == FSMC_Bank2_NAND)
00585     {
00586       FSMC_Bank2->PCR2 &= PCR_ECCEN_Reset;
00587     }
00588     else
00589     {
00590       FSMC_Bank3->PCR3 &= PCR_ECCEN_Reset;
00591     }
00592   }
00593 }
00594
00595 /**
00596   * @brief  Returns the error correction code register value.
00597   * @param  FSMC_Bank: specifies the FSMC Bank to be used
00598   *   This parameter can be one of the following values:
00599   *     @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
00600   *     @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
00601   * @retval The Error Correction Code (ECC) value.
00602   */
00603 uint32_t FSMC_GetECC(uint32_t FSMC_Bank)
00604 {
00605   uint32_t eccval = 0x00000000;
00606
00607   if(FSMC_Bank == FSMC_Bank2_NAND)
00608   {
00609     /* Get the ECCR2 register value */
00610     eccval = FSMC_Bank2->ECCR2;
00611   }
00612   else
00613   {
00614     /* Get the ECCR3 register value */
00615     eccval = FSMC_Bank3->ECCR3;
00616   }
00617   /* Return the error correction code value */
00618   return(eccval);
00619 }
00620
00621 /**
00622   * @brief  Enables or disables the specified FSMC interrupts.
00623   * @param  FSMC_Bank: specifies the FSMC Bank to be used
00624   *   This parameter can be one of the following values:
00625   *     @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
00626   *     @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
00627   *     @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
00628   * @param  FSMC_IT: specifies the FSMC interrupt sources to be enabled or disabled.
00629   *   This parameter can be any combination of the following values:
00630   *     @arg FSMC_IT_RisingEdge: Rising edge detection interrupt.
00631   *     @arg FSMC_IT_Level: Level edge detection interrupt.
00632   *     @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.
00633   * @param  NewState: new state of the specified FSMC interrupts.
00634   *   This parameter can be: ENABLE or DISABLE.
00635   * @retval None
00636   */
00637 void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState)
00638 {
00639   assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
00640   assert_param(IS_FSMC_IT(FSMC_IT));
00641   assert_param(IS_FUNCTIONAL_STATE(NewState));
00642
00643   if (NewState != DISABLE)
00644   {
00645     /* Enable the selected FSMC_Bank2 interrupts */
00646     if(FSMC_Bank == FSMC_Bank2_NAND)
00647     {
00648       FSMC_Bank2->SR2 |= FSMC_IT;
00649     }
00650     /* Enable the selected FSMC_Bank3 interrupts */
00651     else if (FSMC_Bank == FSMC_Bank3_NAND)
00652     {
00653       FSMC_Bank3->SR3 |= FSMC_IT;
00654     }
00655     /* Enable the selected FSMC_Bank4 interrupts */
00656     else
00657     {
00658       FSMC_Bank4->SR4 |= FSMC_IT;
00659     }
00660   }
00661   else
00662   {
00663     /* Disable the selected FSMC_Bank2 interrupts */
00664     if(FSMC_Bank == FSMC_Bank2_NAND)
00665     {
00666
00667       FSMC_Bank2->SR2 &= (uint32_t)~FSMC_IT;
00668     }
00669     /* Disable the selected FSMC_Bank3 interrupts */
00670     else if (FSMC_Bank == FSMC_Bank3_NAND)
00671     {
00672       FSMC_Bank3->SR3 &= (uint32_t)~FSMC_IT;
00673     }
00674     /* Disable the selected FSMC_Bank4 interrupts */
00675     else
00676     {
00677       FSMC_Bank4->SR4 &= (uint32_t)~FSMC_IT;
00678     }
00679   }
00680 }
00681
00682 /**
00683   * @brief  Checks whether the specified FSMC flag is set or not.
00684   * @param  FSMC_Bank: specifies the FSMC Bank to be used
00685   *   This parameter can be one of the following values:
00686   *     @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
00687   *     @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
00688   *     @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
00689   * @param  FSMC_FLAG: specifies the flag to check.
00690   *   This parameter can be one of the following values:
00691   *     @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag.
00692   *     @arg FSMC_FLAG_Level: Level detection Flag.
00693   *     @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag.
00694   *     @arg FSMC_FLAG_FEMPT: Fifo empty Flag.
00695   * @retval The new state of FSMC_FLAG (SET or RESET).
00696   */
00697 FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
00698 {
00699   FlagStatus bitstatus = RESET;
00700   uint32_t tmpsr = 0x00000000;
00701
00702   /* Check the parameters */
00703   assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));
00704   assert_param(IS_FSMC_GET_FLAG(FSMC_FLAG));
00705
00706   if(FSMC_Bank == FSMC_Bank2_NAND)
00707   {
00708     tmpsr = FSMC_Bank2->SR2;
00709   }
00710   else if(FSMC_Bank == FSMC_Bank3_NAND)
00711   {
00712     tmpsr = FSMC_Bank3->SR3;
00713   }
00714   /* FSMC_Bank4_PCCARD*/
00715   else
00716   {
00717     tmpsr = FSMC_Bank4->SR4;
00718   }
00719
00720   /* Get the flag status */
00721   if ((tmpsr & FSMC_FLAG) != (uint16_t)RESET )
00722   {
00723     bitstatus = SET;
00724   }
00725   else
00726   {
00727     bitstatus = RESET;
00728   }
00729   /* Return the flag status */
00730   return bitstatus;
00731 }
00732
00733 /**
00734   * @brief  Clears the FSMC's pending flags.
00735   * @param  FSMC_Bank: specifies the FSMC Bank to be used
00736   *   This parameter can be one of the following values:
00737   *     @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
00738   *     @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
00739   *     @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
00740   * @param  FSMC_FLAG: specifies the flag to clear.
00741   *   This parameter can be any combination of the following values:
00742   *     @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag.
00743   *     @arg FSMC_FLAG_Level: Level detection Flag.
00744   *     @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag.
00745   * @retval None
00746   */
00747 void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
00748 {
00749  /* Check the parameters */
00750   assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));
00751   assert_param(IS_FSMC_CLEAR_FLAG(FSMC_FLAG)) ;
00752
00753   if(FSMC_Bank == FSMC_Bank2_NAND)
00754   {
00755     FSMC_Bank2->SR2 &= ~FSMC_FLAG;
00756   }
00757   else if(FSMC_Bank == FSMC_Bank3_NAND)
00758   {
00759     FSMC_Bank3->SR3 &= ~FSMC_FLAG;
00760   }
00761   /* FSMC_Bank4_PCCARD*/
00762   else
00763   {
00764     FSMC_Bank4->SR4 &= ~FSMC_FLAG;
00765   }
00766 }
00767
00768 /**
00769   * @brief  Checks whether the specified FSMC interrupt has occurred or not.
00770   * @param  FSMC_Bank: specifies the FSMC Bank to be used
00771   *   This parameter can be one of the following values:
00772   *     @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
00773   *     @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
00774   *     @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
00775   * @param  FSMC_IT: specifies the FSMC interrupt source to check.
00776   *   This parameter can be one of the following values:
00777   *     @arg FSMC_IT_RisingEdge: Rising edge detection interrupt.
00778   *     @arg FSMC_IT_Level: Level edge detection interrupt.
00779   *     @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.
00780   * @retval The new state of FSMC_IT (SET or RESET).
00781   */
00782 ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT)
00783 {
00784   ITStatus bitstatus = RESET;
00785   uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0;
00786
00787   /* Check the parameters */
00788   assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
00789   assert_param(IS_FSMC_GET_IT(FSMC_IT));
00790
00791   if(FSMC_Bank == FSMC_Bank2_NAND)
00792   {
00793     tmpsr = FSMC_Bank2->SR2;
00794   }
00795   else if(FSMC_Bank == FSMC_Bank3_NAND)
00796   {
00797     tmpsr = FSMC_Bank3->SR3;
00798   }
00799   /* FSMC_Bank4_PCCARD*/
00800   else
00801   {
00802     tmpsr = FSMC_Bank4->SR4;
00803   }
00804
00805   itstatus = tmpsr & FSMC_IT;
00806
00807   itenable = tmpsr & (FSMC_IT >> 3);
00808   if ((itstatus != (uint32_t)RESET)  && (itenable != (uint32_t)RESET))
00809   {
00810     bitstatus = SET;
00811   }
00812   else
00813   {
00814     bitstatus = RESET;
00815   }
00816   return bitstatus;
00817 }
00818
00819 /**
00820   * @brief  Clears the FSMC's interrupt pending bits.
00821   * @param  FSMC_Bank: specifies the FSMC Bank to be used
00822   *   This parameter can be one of the following values:
00823   *     @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
00824   *     @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
00825   *     @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
00826   * @param  FSMC_IT: specifies the interrupt pending bit to clear.
00827   *   This parameter can be any combination of the following values:
00828   *     @arg FSMC_IT_RisingEdge: Rising edge detection interrupt.
00829   *     @arg FSMC_IT_Level: Level edge detection interrupt.
00830   *     @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.
00831   * @retval None
00832   */
00833 void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT)
00834 {
00835   /* Check the parameters */
00836   assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
00837   assert_param(IS_FSMC_IT(FSMC_IT));
00838
00839   if(FSMC_Bank == FSMC_Bank2_NAND)
00840   {
00841     FSMC_Bank2->SR2 &= ~(FSMC_IT >> 3);
00842   }
00843   else if(FSMC_Bank == FSMC_Bank3_NAND)
00844   {
00845     FSMC_Bank3->SR3 &= ~(FSMC_IT >> 3);
00846   }
00847   /* FSMC_Bank4_PCCARD*/
00848   else
00849   {
00850     FSMC_Bank4->SR4 &= ~(FSMC_IT >> 3);
00851   }
00852 }
00853
00854 /**
00855   * @}
00856   */
00857
00858 /**
00859   * @}
00860   */
00861
00862 /**
00863   * @}
00864   */
00865
00866 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_fsmc.h Source File

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stm32f10x_fsmc.h

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f10x_fsmc.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    11-March-2011
00007   * @brief   This file contains all the functions prototypes for the FSMC firmware
00008   *          library.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00013   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00014   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00015   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00016   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00017   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00018   *
00019   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00020   ******************************************************************************
00021   */
00022
00023 /* Define to prevent recursive inclusion -------------------------------------*/
00024 #ifndef __STM32F10x_FSMC_H
00025 #define __STM32F10x_FSMC_H
00026
00027 #ifdef __cplusplus
00028  extern "C" {
00029 #endif
00030
00031 /* Includes ------------------------------------------------------------------*/
00032 #include "stm32f10x.h"
00033
00034 /** @addtogroup STM32F10x_StdPeriph_Driver
00035   * @{
00036   */
00037
00038 /** @addtogroup FSMC
00039   * @{
00040   */
00041
00042 /** @defgroup FSMC_Exported_Types
00043   * @{
00044   */
00045
00046 /**
00047   * @brief  Timing parameters For NOR/SRAM Banks
00048   */
00049
00050 typedef struct
00051 {
00052   uint32_t FSMC_AddressSetupTime;       /*!< Defines the number of HCLK cycles to configure
00053                                              the duration of the address setup time.
00054                                              This parameter can be a value between 0 and 0xF.
00055                                              @note: It is not used with synchronous NOR Flash memories. */
00056
00057   uint32_t FSMC_AddressHoldTime;        /*!< Defines the number of HCLK cycles to configure
00058                                              the duration of the address hold time.
00059                                              This parameter can be a value between 0 and 0xF.
00060                                              @note: It is not used with synchronous NOR Flash memories.*/
00061
00062   uint32_t FSMC_DataSetupTime;          /*!< Defines the number of HCLK cycles to configure
00063                                              the duration of the data setup time.
00064                                              This parameter can be a value between 0 and 0xFF.
00065                                              @note: It is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */
00066
00067   uint32_t FSMC_BusTurnAroundDuration;  /*!< Defines the number of HCLK cycles to configure
00068                                              the duration of the bus turnaround.
00069                                              This parameter can be a value between 0 and 0xF.
00070                                              @note: It is only used for multiplexed NOR Flash memories. */
00071
00072   uint32_t FSMC_CLKDivision;            /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles.
00073                                              This parameter can be a value between 1 and 0xF.
00074                                              @note: This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */
00075
00076   uint32_t FSMC_DataLatency;            /*!< Defines the number of memory clock cycles to issue
00077                                              to the memory before getting the first data.
00078                                              The value of this parameter depends on the memory type as shown below:
00079                                               - It must be set to 0 in case of a CRAM
00080                                               - It is don't care in asynchronous NOR, SRAM or ROM accesses
00081                                               - It may assume a value between 0 and 0xF in NOR Flash memories
00082                                                 with synchronous burst mode enable */
00083
00084   uint32_t FSMC_AccessMode;             /*!< Specifies the asynchronous access mode.
00085                                              This parameter can be a value of @ref FSMC_Access_Mode */
00086 }FSMC_NORSRAMTimingInitTypeDef;
00087
00088 /**
00089   * @brief  FSMC NOR/SRAM Init structure definition
00090   */
00091
00092 typedef struct
00093 {
00094   uint32_t FSMC_Bank;                /*!< Specifies the NOR/SRAM memory bank that will be used.
00095                                           This parameter can be a value of @ref FSMC_NORSRAM_Bank */
00096
00097   uint32_t FSMC_DataAddressMux;      /*!< Specifies whether the address and data values are
00098                                           multiplexed on the databus or not.
00099                                           This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
00100
00101   uint32_t FSMC_MemoryType;          /*!< Specifies the type of external memory attached to
00102                                           the corresponding memory bank.
00103                                           This parameter can be a value of @ref FSMC_Memory_Type */
00104
00105   uint32_t FSMC_MemoryDataWidth;     /*!< Specifies the external memory device width.
00106                                           This parameter can be a value of @ref FSMC_Data_Width */
00107
00108   uint32_t FSMC_BurstAccessMode;     /*!< Enables or disables the burst access mode for Flash memory,
00109                                           valid only with synchronous burst Flash memories.
00110                                           This parameter can be a value of @ref FSMC_Burst_Access_Mode */
00111
00112   uint32_t FSMC_AsynchronousWait;     /*!< Enables or disables wait signal during asynchronous transfers,
00113                                           valid only with asynchronous Flash memories.
00114                                           This parameter can be a value of @ref FSMC_AsynchronousWait */
00115
00116   uint32_t FSMC_WaitSignalPolarity;  /*!< Specifies the wait signal polarity, valid only when accessing
00117                                           the Flash memory in burst mode.
00118                                           This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
00119
00120   uint32_t FSMC_WrapMode;            /*!< Enables or disables the Wrapped burst access mode for Flash
00121                                           memory, valid only when accessing Flash memories in burst mode.
00122                                           This parameter can be a value of @ref FSMC_Wrap_Mode */
00123
00124   uint32_t FSMC_WaitSignalActive;    /*!< Specifies if the wait signal is asserted by the memory one
00125                                           clock cycle before the wait state or during the wait state,
00126                                           valid only when accessing memories in burst mode.
00127                                           This parameter can be a value of @ref FSMC_Wait_Timing */
00128
00129   uint32_t FSMC_WriteOperation;      /*!< Enables or disables the write operation in the selected bank by the FSMC.
00130                                           This parameter can be a value of @ref FSMC_Write_Operation */
00131
00132   uint32_t FSMC_WaitSignal;          /*!< Enables or disables the wait-state insertion via wait
00133                                           signal, valid for Flash memory access in burst mode.
00134                                           This parameter can be a value of @ref FSMC_Wait_Signal */
00135
00136   uint32_t FSMC_ExtendedMode;        /*!< Enables or disables the extended mode.
00137                                           This parameter can be a value of @ref FSMC_Extended_Mode */
00138
00139   uint32_t FSMC_WriteBurst;          /*!< Enables or disables the write burst operation.
00140                                           This parameter can be a value of @ref FSMC_Write_Burst */
00141
00142   FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the  ExtendedMode is not used*/
00143
00144   FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct;     /*!< Timing Parameters for write access if the  ExtendedMode is used*/
00145 }FSMC_NORSRAMInitTypeDef;
00146
00147 /**
00148   * @brief  Timing parameters For FSMC NAND and PCCARD Banks
00149   */
00150
00151 typedef struct
00152 {
00153   uint32_t FSMC_SetupTime;      /*!< Defines the number of HCLK cycles to setup address before
00154                                      the command assertion for NAND-Flash read or write access
00155                                      to common/Attribute or I/O memory space (depending on
00156                                      the memory space timing to be configured).
00157                                      This parameter can be a value between 0 and 0xFF.*/
00158
00159   uint32_t FSMC_WaitSetupTime;  /*!< Defines the minimum number of HCLK cycles to assert the
00160                                      command for NAND-Flash read or write access to
00161                                      common/Attribute or I/O memory space (depending on the
00162                                      memory space timing to be configured).
00163                                      This parameter can be a number between 0x00 and 0xFF */
00164
00165   uint32_t FSMC_HoldSetupTime;  /*!< Defines the number of HCLK clock cycles to hold address
00166                                      (and data for write access) after the command deassertion
00167                                      for NAND-Flash read or write access to common/Attribute
00168                                      or I/O memory space (depending on the memory space timing
00169                                      to be configured).
00170                                      This parameter can be a number between 0x00 and 0xFF */
00171
00172   uint32_t FSMC_HiZSetupTime;   /*!< Defines the number of HCLK clock cycles during which the
00173                                      databus is kept in HiZ after the start of a NAND-Flash
00174                                      write access to common/Attribute or I/O memory space (depending
00175                                      on the memory space timing to be configured).
00176                                      This parameter can be a number between 0x00 and 0xFF */
00177 }FSMC_NAND_PCCARDTimingInitTypeDef;
00178
00179 /**
00180   * @brief  FSMC NAND Init structure definition
00181   */
00182
00183 typedef struct
00184 {
00185   uint32_t FSMC_Bank;              /*!< Specifies the NAND memory bank that will be used.
00186                                       This parameter can be a value of @ref FSMC_NAND_Bank */
00187
00188   uint32_t FSMC_Waitfeature;      /*!< Enables or disables the Wait feature for the NAND Memory Bank.
00189                                        This parameter can be any value of @ref FSMC_Wait_feature */
00190
00191   uint32_t FSMC_MemoryDataWidth;  /*!< Specifies the external memory device width.
00192                                        This parameter can be any value of @ref FSMC_Data_Width */
00193
00194   uint32_t FSMC_ECC;              /*!< Enables or disables the ECC computation.
00195                                        This parameter can be any value of @ref FSMC_ECC */
00196
00197   uint32_t FSMC_ECCPageSize;      /*!< Defines the page size for the extended ECC.
00198                                        This parameter can be any value of @ref FSMC_ECC_Page_Size */
00199
00200   uint32_t FSMC_TCLRSetupTime;    /*!< Defines the number of HCLK cycles to configure the
00201                                        delay between CLE low and RE low.
00202                                        This parameter can be a value between 0 and 0xFF. */
00203
00204   uint32_t FSMC_TARSetupTime;     /*!< Defines the number of HCLK cycles to configure the
00205                                        delay between ALE low and RE low.
00206                                        This parameter can be a number between 0x0 and 0xFF */
00207
00208   FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_CommonSpaceTimingStruct;   /*!< FSMC Common Space Timing */
00209
00210   FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */
00211 }FSMC_NANDInitTypeDef;
00212
00213 /**
00214   * @brief  FSMC PCCARD Init structure definition
00215   */
00216
00217 typedef struct
00218 {
00219   uint32_t FSMC_Waitfeature;    /*!< Enables or disables the Wait feature for the Memory Bank.
00220                                     This parameter can be any value of @ref FSMC_Wait_feature */
00221
00222   uint32_t FSMC_TCLRSetupTime;  /*!< Defines the number of HCLK cycles to configure the
00223                                      delay between CLE low and RE low.
00224                                      This parameter can be a value between 0 and 0xFF. */
00225
00226   uint32_t FSMC_TARSetupTime;   /*!< Defines the number of HCLK cycles to configure the
00227                                      delay between ALE low and RE low.
00228                                      This parameter can be a number between 0x0 and 0xFF */
00229
00230
00231   FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */
00232
00233   FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_AttributeSpaceTimingStruct;  /*!< FSMC Attribute Space Timing */
00234
00235   FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_IOSpaceTimingStruct; /*!< FSMC IO Space Timing */
00236 }FSMC_PCCARDInitTypeDef;
00237
00238 /**
00239   * @}
00240   */
00241
00242 /** @defgroup FSMC_Exported_Constants
00243   * @{
00244   */
00245
00246 /** @defgroup FSMC_NORSRAM_Bank
00247   * @{
00248   */
00249 #define FSMC_Bank1_NORSRAM1                             ((uint32_t)0x00000000)
00250 #define FSMC_Bank1_NORSRAM2                             ((uint32_t)0x00000002)
00251 #define FSMC_Bank1_NORSRAM3                             ((uint32_t)0x00000004)
00252 #define FSMC_Bank1_NORSRAM4                             ((uint32_t)0x00000006)
00253 /**
00254   * @}
00255   */
00256
00257 /** @defgroup FSMC_NAND_Bank
00258   * @{
00259   */
00260 #define FSMC_Bank2_NAND                                 ((uint32_t)0x00000010)
00261 #define FSMC_Bank3_NAND                                 ((uint32_t)0x00000100)
00262 /**
00263   * @}
00264   */
00265
00266 /** @defgroup FSMC_PCCARD_Bank
00267   * @{
00268   */
00269 #define FSMC_Bank4_PCCARD                               ((uint32_t)0x00001000)
00270 /**
00271   * @}
00272   */
00273
00274 #define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \
00275                                     ((BANK) == FSMC_Bank1_NORSRAM2) || \
00276                                     ((BANK) == FSMC_Bank1_NORSRAM3) || \
00277                                     ((BANK) == FSMC_Bank1_NORSRAM4))
00278
00279 #define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
00280                                  ((BANK) == FSMC_Bank3_NAND))
00281
00282 #define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
00283                                     ((BANK) == FSMC_Bank3_NAND) || \
00284                                     ((BANK) == FSMC_Bank4_PCCARD))
00285
00286 #define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
00287                                ((BANK) == FSMC_Bank3_NAND) || \
00288                                ((BANK) == FSMC_Bank4_PCCARD))
00289
00290 /** @defgroup NOR_SRAM_Controller
00291   * @{
00292   */
00293
00294 /** @defgroup FSMC_Data_Address_Bus_Multiplexing
00295   * @{
00296   */
00297
00298 #define FSMC_DataAddressMux_Disable                       ((uint32_t)0x00000000)
00299 #define FSMC_DataAddressMux_Enable                        ((uint32_t)0x00000002)
00300 #define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \
00301                           ((MUX) == FSMC_DataAddressMux_Enable))
00302
00303 /**
00304   * @}
00305   */
00306
00307 /** @defgroup FSMC_Memory_Type
00308   * @{
00309   */
00310
00311 #define FSMC_MemoryType_SRAM                            ((uint32_t)0x00000000)
00312 #define FSMC_MemoryType_PSRAM                           ((uint32_t)0x00000004)
00313 #define FSMC_MemoryType_NOR                             ((uint32_t)0x00000008)
00314 #define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \
00315                                 ((MEMORY) == FSMC_MemoryType_PSRAM)|| \
00316                                 ((MEMORY) == FSMC_MemoryType_NOR))
00317
00318 /**
00319   * @}
00320   */
00321
00322 /** @defgroup FSMC_Data_Width
00323   * @{
00324   */
00325
00326 #define FSMC_MemoryDataWidth_8b                         ((uint32_t)0x00000000)
00327 #define FSMC_MemoryDataWidth_16b                        ((uint32_t)0x00000010)
00328 #define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \
00329                                      ((WIDTH) == FSMC_MemoryDataWidth_16b))
00330
00331 /**
00332   * @}
00333   */
00334
00335 /** @defgroup FSMC_Burst_Access_Mode
00336   * @{
00337   */
00338
00339 #define FSMC_BurstAccessMode_Disable                    ((uint32_t)0x00000000)
00340 #define FSMC_BurstAccessMode_Enable                     ((uint32_t)0x00000100)
00341 #define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \
00342                                   ((STATE) == FSMC_BurstAccessMode_Enable))
00343 /**
00344   * @}
00345   */
00346
00347 /** @defgroup FSMC_AsynchronousWait
00348   * @{
00349   */
00350 #define FSMC_AsynchronousWait_Disable                   ((uint32_t)0x00000000)
00351 #define FSMC_AsynchronousWait_Enable                    ((uint32_t)0x00008000)
00352 #define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_AsynchronousWait_Disable) || \
00353                                  ((STATE) == FSMC_AsynchronousWait_Enable))
00354
00355 /**
00356   * @}
00357   */
00358
00359 /** @defgroup FSMC_Wait_Signal_Polarity
00360   * @{
00361   */
00362
00363 #define FSMC_WaitSignalPolarity_Low                     ((uint32_t)0x00000000)
00364 #define FSMC_WaitSignalPolarity_High                    ((uint32_t)0x00000200)
00365 #define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \
00366                                          ((POLARITY) == FSMC_WaitSignalPolarity_High))
00367
00368 /**
00369   * @}
00370   */
00371
00372 /** @defgroup FSMC_Wrap_Mode
00373   * @{
00374   */
00375
00376 #define FSMC_WrapMode_Disable                           ((uint32_t)0x00000000)
00377 #define FSMC_WrapMode_Enable                            ((uint32_t)0x00000400)
00378 #define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \
00379                                  ((MODE) == FSMC_WrapMode_Enable))
00380
00381 /**
00382   * @}
00383   */
00384
00385 /** @defgroup FSMC_Wait_Timing
00386   * @{
00387   */
00388
00389 #define FSMC_WaitSignalActive_BeforeWaitState           ((uint32_t)0x00000000)
00390 #define FSMC_WaitSignalActive_DuringWaitState           ((uint32_t)0x00000800)
00391 #define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \
00392                                             ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState))
00393
00394 /**
00395   * @}
00396   */
00397
00398 /** @defgroup FSMC_Write_Operation
00399   * @{
00400   */
00401
00402 #define FSMC_WriteOperation_Disable                     ((uint32_t)0x00000000)
00403 #define FSMC_WriteOperation_Enable                      ((uint32_t)0x00001000)
00404 #define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \
00405                                             ((OPERATION) == FSMC_WriteOperation_Enable))
00406
00407 /**
00408   * @}
00409   */
00410
00411 /** @defgroup FSMC_Wait_Signal
00412   * @{
00413   */
00414
00415 #define FSMC_WaitSignal_Disable                         ((uint32_t)0x00000000)
00416 #define FSMC_WaitSignal_Enable                          ((uint32_t)0x00002000)
00417 #define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \
00418                                       ((SIGNAL) == FSMC_WaitSignal_Enable))
00419 /**
00420   * @}
00421   */
00422
00423 /** @defgroup FSMC_Extended_Mode
00424   * @{
00425   */
00426
00427 #define FSMC_ExtendedMode_Disable                       ((uint32_t)0x00000000)
00428 #define FSMC_ExtendedMode_Enable                        ((uint32_t)0x00004000)
00429
00430 #define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \
00431                                      ((MODE) == FSMC_ExtendedMode_Enable))
00432
00433 /**
00434   * @}
00435   */
00436
00437 /** @defgroup FSMC_Write_Burst
00438   * @{
00439   */
00440
00441 #define FSMC_WriteBurst_Disable                         ((uint32_t)0x00000000)
00442 #define FSMC_WriteBurst_Enable                          ((uint32_t)0x00080000)
00443 #define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \
00444                                     ((BURST) == FSMC_WriteBurst_Enable))
00445 /**
00446   * @}
00447   */
00448
00449 /** @defgroup FSMC_Address_Setup_Time
00450   * @{
00451   */
00452
00453 #define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF)
00454
00455 /**
00456   * @}
00457   */
00458
00459 /** @defgroup FSMC_Address_Hold_Time
00460   * @{
00461   */
00462
00463 #define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF)
00464
00465 /**
00466   * @}
00467   */
00468
00469 /** @defgroup FSMC_Data_Setup_Time
00470   * @{
00471   */
00472
00473 #define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF))
00474
00475 /**
00476   * @}
00477   */
00478
00479 /** @defgroup FSMC_Bus_Turn_around_Duration
00480   * @{
00481   */
00482
00483 #define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF)
00484
00485 /**
00486   * @}
00487   */
00488
00489 /** @defgroup FSMC_CLK_Division
00490   * @{
00491   */
00492
00493 #define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF)
00494
00495 /**
00496   * @}
00497   */
00498
00499 /** @defgroup FSMC_Data_Latency
00500   * @{
00501   */
00502
00503 #define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF)
00504
00505 /**
00506   * @}
00507   */
00508
00509 /** @defgroup FSMC_Access_Mode
00510   * @{
00511   */
00512
00513 #define FSMC_AccessMode_A                               ((uint32_t)0x00000000)
00514 #define FSMC_AccessMode_B                               ((uint32_t)0x10000000)
00515 #define FSMC_AccessMode_C                               ((uint32_t)0x20000000)
00516 #define FSMC_AccessMode_D                               ((uint32_t)0x30000000)
00517 #define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \
00518                                    ((MODE) == FSMC_AccessMode_B) || \
00519                                    ((MODE) == FSMC_AccessMode_C) || \
00520                                    ((MODE) == FSMC_AccessMode_D))
00521
00522 /**
00523   * @}
00524   */
00525
00526 /**
00527   * @}
00528   */
00529
00530 /** @defgroup NAND_PCCARD_Controller
00531   * @{
00532   */
00533
00534 /** @defgroup FSMC_Wait_feature
00535   * @{
00536   */
00537
00538 #define FSMC_Waitfeature_Disable                        ((uint32_t)0x00000000)
00539 #define FSMC_Waitfeature_Enable                         ((uint32_t)0x00000002)
00540 #define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \
00541                                        ((FEATURE) == FSMC_Waitfeature_Enable))
00542
00543 /**
00544   * @}
00545   */
00546
00547
00548 /** @defgroup FSMC_ECC
00549   * @{
00550   */
00551
00552 #define FSMC_ECC_Disable                                ((uint32_t)0x00000000)
00553 #define FSMC_ECC_Enable                                 ((uint32_t)0x00000040)
00554 #define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \
00555                                   ((STATE) == FSMC_ECC_Enable))
00556
00557 /**
00558   * @}
00559   */
00560
00561 /** @defgroup FSMC_ECC_Page_Size
00562   * @{
00563   */
00564
00565 #define FSMC_ECCPageSize_256Bytes                       ((uint32_t)0x00000000)
00566 #define FSMC_ECCPageSize_512Bytes                       ((uint32_t)0x00020000)
00567 #define FSMC_ECCPageSize_1024Bytes                      ((uint32_t)0x00040000)
00568 #define FSMC_ECCPageSize_2048Bytes                      ((uint32_t)0x00060000)
00569 #define FSMC_ECCPageSize_4096Bytes                      ((uint32_t)0x00080000)
00570 #define FSMC_ECCPageSize_8192Bytes                      ((uint32_t)0x000A0000)
00571 #define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \
00572                                     ((SIZE) == FSMC_ECCPageSize_512Bytes) || \
00573                                     ((SIZE) == FSMC_ECCPageSize_1024Bytes) || \
00574                                     ((SIZE) == FSMC_ECCPageSize_2048Bytes) || \
00575                                     ((SIZE) == FSMC_ECCPageSize_4096Bytes) || \
00576                                     ((SIZE) == FSMC_ECCPageSize_8192Bytes))
00577
00578 /**
00579   * @}
00580   */
00581
00582 /** @defgroup FSMC_TCLR_Setup_Time
00583   * @{
00584   */
00585
00586 #define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF)
00587
00588 /**
00589   * @}
00590   */
00591
00592 /** @defgroup FSMC_TAR_Setup_Time
00593   * @{
00594   */
00595
00596 #define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF)
00597
00598 /**
00599   * @}
00600   */
00601
00602 /** @defgroup FSMC_Setup_Time
00603   * @{
00604   */
00605
00606 #define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF)
00607
00608 /**
00609   * @}
00610   */
00611
00612 /** @defgroup FSMC_Wait_Setup_Time
00613   * @{
00614   */
00615
00616 #define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF)
00617
00618 /**
00619   * @}
00620   */
00621
00622 /** @defgroup FSMC_Hold_Setup_Time
00623   * @{
00624   */
00625
00626 #define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF)
00627
00628 /**
00629   * @}
00630   */
00631
00632 /** @defgroup FSMC_HiZ_Setup_Time
00633   * @{
00634   */
00635
00636 #define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF)
00637
00638 /**
00639   * @}
00640   */
00641
00642 /** @defgroup FSMC_Interrupt_sources
00643   * @{
00644   */
00645
00646 #define FSMC_IT_RisingEdge                              ((uint32_t)0x00000008)
00647 #define FSMC_IT_Level                                   ((uint32_t)0x00000010)
00648 #define FSMC_IT_FallingEdge                             ((uint32_t)0x00000020)
00649 #define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000))
00650 #define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \
00651                             ((IT) == FSMC_IT_Level) || \
00652                             ((IT) == FSMC_IT_FallingEdge))
00653 /**
00654   * @}
00655   */
00656
00657 /** @defgroup FSMC_Flags
00658   * @{
00659   */
00660
00661 #define FSMC_FLAG_RisingEdge                            ((uint32_t)0x00000001)
00662 #define FSMC_FLAG_Level                                 ((uint32_t)0x00000002)
00663 #define FSMC_FLAG_FallingEdge                           ((uint32_t)0x00000004)
00664 #define FSMC_FLAG_FEMPT                                 ((uint32_t)0x00000040)
00665 #define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \
00666                                 ((FLAG) == FSMC_FLAG_Level) || \
00667                                 ((FLAG) == FSMC_FLAG_FallingEdge) || \
00668                                 ((FLAG) == FSMC_FLAG_FEMPT))
00669
00670 #define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
00671
00672 /**
00673   * @}
00674   */
00675
00676 /**
00677   * @}
00678   */
00679
00680 /**
00681   * @}
00682   */
00683
00684 /** @defgroup FSMC_Exported_Macros
00685   * @{
00686   */
00687
00688 /**
00689   * @}
00690   */
00691
00692 /** @defgroup FSMC_Exported_Functions
00693   * @{
00694   */
00695
00696 void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank);
00697 void FSMC_NANDDeInit(uint32_t FSMC_Bank);
00698 void FSMC_PCCARDDeInit(void);
00699 void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
00700 void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
00701 void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
00702 void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
00703 void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
00704 void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
00705 void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState);
00706 void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState);
00707 void FSMC_PCCARDCmd(FunctionalState NewState);
00708 void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState);
00709 uint32_t FSMC_GetECC(uint32_t FSMC_Bank);
00710 void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState);
00711 FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
00712 void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
00713 ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT);
00714 void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT);
00715
00716 #ifdef __cplusplus
00717 }
00718 #endif
00719
00720 #endif /*__STM32F10x_FSMC_H */
00721 /**
00722   * @}
00723   */
00724
00725 /**
00726   * @}
00727   */
00728
00729 /**
00730   * @}
00731   */
00732
00733 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_gpio.c Source File

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  • STM32F10x_StdPeriph_Driver
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stm32f10x_gpio.c

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f10x_gpio.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    11-March-2011
00007   * @brief   This file provides all the GPIO firmware functions.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x_gpio.h"
00024 #include "stm32f10x_rcc.h"
00025
00026 /** @addtogroup STM32F10x_StdPeriph_Driver
00027   * @{
00028   */
00029
00030 /** @defgroup GPIO
00031   * @brief GPIO driver modules
00032   * @{
00033   */
00034
00035 /** @defgroup GPIO_Private_TypesDefinitions
00036   * @{
00037   */
00038
00039 /**
00040   * @}
00041   */
00042
00043 /** @defgroup GPIO_Private_Defines
00044   * @{
00045   */
00046
00047 /* ------------ RCC registers bit address in the alias region ----------------*/
00048 #define AFIO_OFFSET                 (AFIO_BASE - PERIPH_BASE)
00049
00050 /* --- EVENTCR Register -----*/
00051
00052 /* Alias word address of EVOE bit */
00053 #define EVCR_OFFSET                 (AFIO_OFFSET + 0x00)
00054 #define EVOE_BitNumber              ((uint8_t)0x07)
00055 #define EVCR_EVOE_BB                (PERIPH_BB_BASE + (EVCR_OFFSET * 32) + (EVOE_BitNumber * 4))
00056
00057
00058 /* ---  MAPR Register ---*/
00059 /* Alias word address of MII_RMII_SEL bit */
00060 #define MAPR_OFFSET                 (AFIO_OFFSET + 0x04)
00061 #define MII_RMII_SEL_BitNumber      ((u8)0x17)
00062 #define MAPR_MII_RMII_SEL_BB        (PERIPH_BB_BASE + (MAPR_OFFSET * 32) + (MII_RMII_SEL_BitNumber * 4))
00063
00064
00065 #define EVCR_PORTPINCONFIG_MASK     ((uint16_t)0xFF80)
00066 #define LSB_MASK                    ((uint16_t)0xFFFF)
00067 #define DBGAFR_POSITION_MASK        ((uint32_t)0x000F0000)
00068 #define DBGAFR_SWJCFG_MASK          ((uint32_t)0xF0FFFFFF)
00069 #define DBGAFR_LOCATION_MASK        ((uint32_t)0x00200000)
00070 #define DBGAFR_NUMBITS_MASK         ((uint32_t)0x00100000)
00071 /**
00072   * @}
00073   */
00074
00075 /** @defgroup GPIO_Private_Macros
00076   * @{
00077   */
00078
00079 /**
00080   * @}
00081   */
00082
00083 /** @defgroup GPIO_Private_Variables
00084   * @{
00085   */
00086
00087 /**
00088   * @}
00089   */
00090
00091 /** @defgroup GPIO_Private_FunctionPrototypes
00092   * @{
00093   */
00094
00095 /**
00096   * @}
00097   */
00098
00099 /** @defgroup GPIO_Private_Functions
00100   * @{
00101   */
00102
00103 /**
00104   * @brief  Deinitializes the GPIOx peripheral registers to their default reset values.
00105   * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
00106   * @retval None
00107   */
00108 void GPIO_DeInit(GPIO_TypeDef* GPIOx)
00109 {
00110   /* Check the parameters */
00111   assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
00112
00113   if (GPIOx == GPIOA)
00114   {
00115     RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE);
00116     RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE);
00117   }
00118   else if (GPIOx == GPIOB)
00119   {
00120     RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, ENABLE);
00121     RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, DISABLE);
00122   }
00123   else if (GPIOx == GPIOC)
00124   {
00125     RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE);
00126     RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE);
00127   }
00128   else if (GPIOx == GPIOD)
00129   {
00130     RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, ENABLE);
00131     RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, DISABLE);
00132   }
00133   else if (GPIOx == GPIOE)
00134   {
00135     RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, ENABLE);
00136     RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, DISABLE);
00137   }
00138   else if (GPIOx == GPIOF)
00139   {
00140     RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, ENABLE);
00141     RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, DISABLE);
00142   }
00143   else
00144   {
00145     if (GPIOx == GPIOG)
00146     {
00147       RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, ENABLE);
00148       RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, DISABLE);
00149     }
00150   }
00151 }
00152
00153 /**
00154   * @brief  Deinitializes the Alternate Functions (remap, event control
00155   *   and EXTI configuration) registers to their default reset values.
00156   * @param  None
00157   * @retval None
00158   */
00159 void GPIO_AFIODeInit(void)
00160 {
00161   RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE);
00162   RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, DISABLE);
00163 }
00164
00165 /**
00166   * @brief  Initializes the GPIOx peripheral according to the specified
00167   *         parameters in the GPIO_InitStruct.
00168   * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
00169   * @param  GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that
00170   *         contains the configuration information for the specified GPIO peripheral.
00171   * @retval None
00172   */
00173 void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
00174 {
00175   uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00;
00176   uint32_t tmpreg = 0x00, pinmask = 0x00;
00177   /* Check the parameters */
00178   assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
00179   assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));
00180   assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin));
00181
00182 /*---------------------------- GPIO Mode Configuration -----------------------*/
00183   currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F);
00184   if ((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10)) != 0x00)
00185   {
00186     /* Check the parameters */
00187     assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed));
00188     /* Output mode */
00189     currentmode |= (uint32_t)GPIO_InitStruct->GPIO_Speed;
00190   }
00191 /*---------------------------- GPIO CRL Configuration ------------------------*/
00192   /* Configure the eight low port pins */
00193   if (((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x00FF)) != 0x00)
00194   {
00195     tmpreg = GPIOx->CRL;
00196     for (pinpos = 0x00; pinpos < 0x08; pinpos++)
00197     {
00198       pos = ((uint32_t)0x01) << pinpos;
00199       /* Get the port pins position */
00200       currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;
00201       if (currentpin == pos)
00202       {
00203         pos = pinpos << 2;
00204         /* Clear the corresponding low control register bits */
00205         pinmask = ((uint32_t)0x0F) << pos;
00206         tmpreg &= ~pinmask;
00207         /* Write the mode configuration in the corresponding bits */
00208         tmpreg |= (currentmode << pos);
00209         /* Reset the corresponding ODR bit */
00210         if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
00211         {
00212           GPIOx->BRR = (((uint32_t)0x01) << pinpos);
00213         }
00214         else
00215         {
00216           /* Set the corresponding ODR bit */
00217           if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
00218           {
00219             GPIOx->BSRR = (((uint32_t)0x01) << pinpos);
00220           }
00221         }
00222       }
00223     }
00224     GPIOx->CRL = tmpreg;
00225   }
00226 /*---------------------------- GPIO CRH Configuration ------------------------*/
00227   /* Configure the eight high port pins */
00228   if (GPIO_InitStruct->GPIO_Pin > 0x00FF)
00229   {
00230     tmpreg = GPIOx->CRH;
00231     for (pinpos = 0x00; pinpos < 0x08; pinpos++)
00232     {
00233       pos = (((uint32_t)0x01) << (pinpos + 0x08));
00234       /* Get the port pins position */
00235       currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos);
00236       if (currentpin == pos)
00237       {
00238         pos = pinpos << 2;
00239         /* Clear the corresponding high control register bits */
00240         pinmask = ((uint32_t)0x0F) << pos;
00241         tmpreg &= ~pinmask;
00242         /* Write the mode configuration in the corresponding bits */
00243         tmpreg |= (currentmode << pos);
00244         /* Reset the corresponding ODR bit */
00245         if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
00246         {
00247           GPIOx->BRR = (((uint32_t)0x01) << (pinpos + 0x08));
00248         }
00249         /* Set the corresponding ODR bit */
00250         if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
00251         {
00252           GPIOx->BSRR = (((uint32_t)0x01) << (pinpos + 0x08));
00253         }
00254       }
00255     }
00256     GPIOx->CRH = tmpreg;
00257   }
00258 }
00259
00260 /**
00261   * @brief  Fills each GPIO_InitStruct member with its default value.
00262   * @param  GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will
00263   *         be initialized.
00264   * @retval None
00265   */
00266 void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)
00267 {
00268   /* Reset GPIO init structure parameters values */
00269   GPIO_InitStruct->GPIO_Pin  = GPIO_Pin_All;
00270   GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz;
00271   GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING;
00272 }
00273
00274 /**
00275   * @brief  Reads the specified input port pin.
00276   * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
00277   * @param  GPIO_Pin:  specifies the port bit to read.
00278   *   This parameter can be GPIO_Pin_x where x can be (0..15).
00279   * @retval The input port pin value.
00280   */
00281 uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
00282 {
00283   uint8_t bitstatus = 0x00;
00284
00285   /* Check the parameters */
00286   assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
00287   assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
00288
00289   if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET)
00290   {
00291     bitstatus = (uint8_t)Bit_SET;
00292   }
00293   else
00294   {
00295     bitstatus = (uint8_t)Bit_RESET;
00296   }
00297   return bitstatus;
00298 }
00299
00300 /**
00301   * @brief  Reads the specified GPIO input data port.
00302   * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
00303   * @retval GPIO input data port value.
00304   */
00305 uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx)
00306 {
00307   /* Check the parameters */
00308   assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
00309
00310   return ((uint16_t)GPIOx->IDR);
00311 }
00312
00313 /**
00314   * @brief  Reads the specified output data port bit.
00315   * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
00316   * @param  GPIO_Pin:  specifies the port bit to read.
00317   *   This parameter can be GPIO_Pin_x where x can be (0..15).
00318   * @retval The output port pin value.
00319   */
00320 uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
00321 {
00322   uint8_t bitstatus = 0x00;
00323   /* Check the parameters */
00324   assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
00325   assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
00326
00327   if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET)
00328   {
00329     bitstatus = (uint8_t)Bit_SET;
00330   }
00331   else
00332   {
00333     bitstatus = (uint8_t)Bit_RESET;
00334   }
00335   return bitstatus;
00336 }
00337
00338 /**
00339   * @brief  Reads the specified GPIO output data port.
00340   * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
00341   * @retval GPIO output data port value.
00342   */
00343 uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)
00344 {
00345   /* Check the parameters */
00346   assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
00347
00348   return ((uint16_t)GPIOx->ODR);
00349 }
00350
00351 /**
00352   * @brief  Sets the selected data port bits.
00353   * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
00354   * @param  GPIO_Pin: specifies the port bits to be written.
00355   *   This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
00356   * @retval None
00357   */
00358 void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
00359 {
00360   /* Check the parameters */
00361   assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
00362   assert_param(IS_GPIO_PIN(GPIO_Pin));
00363
00364   GPIOx->BSRR = GPIO_Pin;
00365 }
00366
00367 /**
00368   * @brief  Clears the selected data port bits.
00369   * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
00370   * @param  GPIO_Pin: specifies the port bits to be written.
00371   *   This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
00372   * @retval None
00373   */
00374 void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
00375 {
00376   /* Check the parameters */
00377   assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
00378   assert_param(IS_GPIO_PIN(GPIO_Pin));
00379
00380   GPIOx->BRR = GPIO_Pin;
00381 }
00382
00383 /**
00384   * @brief  Sets or clears the selected data port bit.
00385   * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
00386   * @param  GPIO_Pin: specifies the port bit to be written.
00387   *   This parameter can be one of GPIO_Pin_x where x can be (0..15).
00388   * @param  BitVal: specifies the value to be written to the selected bit.
00389   *   This parameter can be one of the BitAction enum values:
00390   *     @arg Bit_RESET: to clear the port pin
00391   *     @arg Bit_SET: to set the port pin
00392   * @retval None
00393   */
00394 void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
00395 {
00396   /* Check the parameters */
00397   assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
00398   assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
00399   assert_param(IS_GPIO_BIT_ACTION(BitVal));
00400
00401   if (BitVal != Bit_RESET)
00402   {
00403     GPIOx->BSRR = GPIO_Pin;
00404   }
00405   else
00406   {
00407     GPIOx->BRR = GPIO_Pin;
00408   }
00409 }
00410
00411 /**
00412   * @brief  Writes data to the specified GPIO data port.
00413   * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
00414   * @param  PortVal: specifies the value to be written to the port output data register.
00415   * @retval None
00416   */
00417 void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal)
00418 {
00419   /* Check the parameters */
00420   assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
00421
00422   GPIOx->ODR = PortVal;
00423 }
00424
00425 /**
00426   * @brief  Locks GPIO Pins configuration registers.
00427   * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
00428   * @param  GPIO_Pin: specifies the port bit to be written.
00429   *   This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
00430   * @retval None
00431   */
00432 void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
00433 {
00434   uint32_t tmp = 0x00010000;
00435
00436   /* Check the parameters */
00437   assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
00438   assert_param(IS_GPIO_PIN(GPIO_Pin));
00439
00440   tmp |= GPIO_Pin;
00441   /* Set LCKK bit */
00442   GPIOx->LCKR = tmp;
00443   /* Reset LCKK bit */
00444   GPIOx->LCKR =  GPIO_Pin;
00445   /* Set LCKK bit */
00446   GPIOx->LCKR = tmp;
00447   /* Read LCKK bit*/
00448   tmp = GPIOx->LCKR;
00449   /* Read LCKK bit*/
00450   tmp = GPIOx->LCKR;
00451 }
00452
00453 /**
00454   * @brief  Selects the GPIO pin used as Event output.
00455   * @param  GPIO_PortSource: selects the GPIO port to be used as source
00456   *   for Event output.
00457   *   This parameter can be GPIO_PortSourceGPIOx where x can be (A..E).
00458   * @param  GPIO_PinSource: specifies the pin for the Event output.
00459   *   This parameter can be GPIO_PinSourcex where x can be (0..15).
00460   * @retval None
00461   */
00462 void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource)
00463 {
00464   uint32_t tmpreg = 0x00;
00465   /* Check the parameters */
00466   assert_param(IS_GPIO_EVENTOUT_PORT_SOURCE(GPIO_PortSource));
00467   assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));
00468
00469   tmpreg = AFIO->EVCR;
00470   /* Clear the PORT[6:4] and PIN[3:0] bits */
00471   tmpreg &= EVCR_PORTPINCONFIG_MASK;
00472   tmpreg |= (uint32_t)GPIO_PortSource << 0x04;
00473   tmpreg |= GPIO_PinSource;
00474   AFIO->EVCR = tmpreg;
00475 }
00476
00477 /**
00478   * @brief  Enables or disables the Event Output.
00479   * @param  NewState: new state of the Event output.
00480   *   This parameter can be: ENABLE or DISABLE.
00481   * @retval None
00482   */
00483 void GPIO_EventOutputCmd(FunctionalState NewState)
00484 {
00485   /* Check the parameters */
00486   assert_param(IS_FUNCTIONAL_STATE(NewState));
00487
00488   *(__IO uint32_t *) EVCR_EVOE_BB = (uint32_t)NewState;
00489 }
00490
00491 /**
00492   * @brief  Changes the mapping of the specified pin.
00493   * @param  GPIO_Remap: selects the pin to remap.
00494   *   This parameter can be one of the following values:
00495   *     @arg GPIO_Remap_SPI1             : SPI1 Alternate Function mapping
00496   *     @arg GPIO_Remap_I2C1             : I2C1 Alternate Function mapping
00497   *     @arg GPIO_Remap_USART1           : USART1 Alternate Function mapping
00498   *     @arg GPIO_Remap_USART2           : USART2 Alternate Function mapping
00499   *     @arg GPIO_PartialRemap_USART3    : USART3 Partial Alternate Function mapping
00500   *     @arg GPIO_FullRemap_USART3       : USART3 Full Alternate Function mapping
00501   *     @arg GPIO_PartialRemap_TIM1      : TIM1 Partial Alternate Function mapping
00502   *     @arg GPIO_FullRemap_TIM1         : TIM1 Full Alternate Function mapping
00503   *     @arg GPIO_PartialRemap1_TIM2     : TIM2 Partial1 Alternate Function mapping
00504   *     @arg GPIO_PartialRemap2_TIM2     : TIM2 Partial2 Alternate Function mapping
00505   *     @arg GPIO_FullRemap_TIM2         : TIM2 Full Alternate Function mapping
00506   *     @arg GPIO_PartialRemap_TIM3      : TIM3 Partial Alternate Function mapping
00507   *     @arg GPIO_FullRemap_TIM3         : TIM3 Full Alternate Function mapping
00508   *     @arg GPIO_Remap_TIM4             : TIM4 Alternate Function mapping
00509   *     @arg GPIO_Remap1_CAN1            : CAN1 Alternate Function mapping
00510   *     @arg GPIO_Remap2_CAN1            : CAN1 Alternate Function mapping
00511   *     @arg GPIO_Remap_PD01             : PD01 Alternate Function mapping
00512   *     @arg GPIO_Remap_TIM5CH4_LSI      : LSI connected to TIM5 Channel4 input capture for calibration
00513   *     @arg GPIO_Remap_ADC1_ETRGINJ     : ADC1 External Trigger Injected Conversion remapping
00514   *     @arg GPIO_Remap_ADC1_ETRGREG     : ADC1 External Trigger Regular Conversion remapping
00515   *     @arg GPIO_Remap_ADC2_ETRGINJ     : ADC2 External Trigger Injected Conversion remapping
00516   *     @arg GPIO_Remap_ADC2_ETRGREG     : ADC2 External Trigger Regular Conversion remapping
00517   *     @arg GPIO_Remap_ETH              : Ethernet remapping (only for Connectivity line devices)
00518   *     @arg GPIO_Remap_CAN2             : CAN2 remapping (only for Connectivity line devices)
00519   *     @arg GPIO_Remap_SWJ_NoJTRST      : Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST
00520   *     @arg GPIO_Remap_SWJ_JTAGDisable  : JTAG-DP Disabled and SW-DP Enabled
00521   *     @arg GPIO_Remap_SWJ_Disable      : Full SWJ Disabled (JTAG-DP + SW-DP)
00522   *     @arg GPIO_Remap_SPI3             : SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices)
00523   *                                        When the SPI3/I2S3 is remapped using this function, the SWJ is configured
00524   *                                        to Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST.
00525   *     @arg GPIO_Remap_TIM2ITR1_PTP_SOF : Ethernet PTP output or USB OTG SOF (Start of Frame) connected
00526   *                                        to TIM2 Internal Trigger 1 for calibration (only for Connectivity line devices)
00527   *                                        If the GPIO_Remap_TIM2ITR1_PTP_SOF is enabled the TIM2 ITR1 is connected to
00528   *                                        Ethernet PTP output. When Reset TIM2 ITR1 is connected to USB OTG SOF output.
00529   *     @arg GPIO_Remap_PTP_PPS          : Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices)
00530   *     @arg GPIO_Remap_TIM15            : TIM15 Alternate Function mapping (only for Value line devices)
00531   *     @arg GPIO_Remap_TIM16            : TIM16 Alternate Function mapping (only for Value line devices)
00532   *     @arg GPIO_Remap_TIM17            : TIM17 Alternate Function mapping (only for Value line devices)
00533   *     @arg GPIO_Remap_CEC              : CEC Alternate Function mapping (only for Value line devices)
00534   *     @arg GPIO_Remap_TIM1_DMA         : TIM1 DMA requests mapping (only for Value line devices)
00535   *     @arg GPIO_Remap_TIM9             : TIM9 Alternate Function mapping (only for XL-density devices)
00536   *     @arg GPIO_Remap_TIM10            : TIM10 Alternate Function mapping (only for XL-density devices)
00537   *     @arg GPIO_Remap_TIM11            : TIM11 Alternate Function mapping (only for XL-density devices)
00538   *     @arg GPIO_Remap_TIM13            : TIM13 Alternate Function mapping (only for High density Value line and XL-density devices)
00539   *     @arg GPIO_Remap_TIM14            : TIM14 Alternate Function mapping (only for High density Value line and XL-density devices)
00540   *     @arg GPIO_Remap_FSMC_NADV        : FSMC_NADV Alternate Function mapping (only for High density Value line and XL-density devices)
00541   *     @arg GPIO_Remap_TIM67_DAC_DMA    : TIM6/TIM7 and DAC DMA requests remapping (only for High density Value line devices)
00542   *     @arg GPIO_Remap_TIM12            : TIM12 Alternate Function mapping (only for High density Value line devices)
00543   *     @arg GPIO_Remap_MISC             : Miscellaneous Remap (DMA2 Channel5 Position and DAC Trigger remapping,
00544   *                                        only for High density Value line devices)
00545   * @param  NewState: new state of the port pin remapping.
00546   *   This parameter can be: ENABLE or DISABLE.
00547   * @retval None
00548   */
00549 void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState)
00550 {
00551   uint32_t tmp = 0x00, tmp1 = 0x00, tmpreg = 0x00, tmpmask = 0x00;
00552
00553   /* Check the parameters */
00554   assert_param(IS_GPIO_REMAP(GPIO_Remap));
00555   assert_param(IS_FUNCTIONAL_STATE(NewState));
00556
00557   if((GPIO_Remap & 0x80000000) == 0x80000000)
00558   {
00559     tmpreg = AFIO->MAPR2;
00560   }
00561   else
00562   {
00563     tmpreg = AFIO->MAPR;
00564   }
00565
00566   tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10;
00567   tmp = GPIO_Remap & LSB_MASK;
00568
00569   if ((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK))
00570   {
00571     tmpreg &= DBGAFR_SWJCFG_MASK;
00572     AFIO->MAPR &= DBGAFR_SWJCFG_MASK;
00573   }
00574   else if ((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK)
00575   {
00576     tmp1 = ((uint32_t)0x03) << tmpmask;
00577     tmpreg &= ~tmp1;
00578     tmpreg |= ~DBGAFR_SWJCFG_MASK;
00579   }
00580   else
00581   {
00582     tmpreg &= ~(tmp << ((GPIO_Remap >> 0x15)*0x10));
00583     tmpreg |= ~DBGAFR_SWJCFG_MASK;
00584   }
00585
00586   if (NewState != DISABLE)
00587   {
00588     tmpreg |= (tmp << ((GPIO_Remap >> 0x15)*0x10));
00589   }
00590
00591   if((GPIO_Remap & 0x80000000) == 0x80000000)
00592   {
00593     AFIO->MAPR2 = tmpreg;
00594   }
00595   else
00596   {
00597     AFIO->MAPR = tmpreg;
00598   }
00599 }
00600
00601 /**
00602   * @brief  Selects the GPIO pin used as EXTI Line.
00603   * @param  GPIO_PortSource: selects the GPIO port to be used as source for EXTI lines.
00604   *   This parameter can be GPIO_PortSourceGPIOx where x can be (A..G).
00605   * @param  GPIO_PinSource: specifies the EXTI line to be configured.
00606   *   This parameter can be GPIO_PinSourcex where x can be (0..15).
00607   * @retval None
00608   */
00609 void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource)
00610 {
00611   uint32_t tmp = 0x00;
00612   /* Check the parameters */
00613   assert_param(IS_GPIO_EXTI_PORT_SOURCE(GPIO_PortSource));
00614   assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));
00615
00616   tmp = ((uint32_t)0x0F) << (0x04 * (GPIO_PinSource & (uint8_t)0x03));
00617   AFIO->EXTICR[GPIO_PinSource >> 0x02] &= ~tmp;
00618   AFIO->EXTICR[GPIO_PinSource >> 0x02] |= (((uint32_t)GPIO_PortSource) << (0x04 * (GPIO_PinSource & (uint8_t)0x03)));
00619 }
00620
00621 /**
00622   * @brief  Selects the Ethernet media interface.
00623   * @note   This function applies only to STM32 Connectivity line devices.
00624   * @param  GPIO_ETH_MediaInterface: specifies the Media Interface mode.
00625   *   This parameter can be one of the following values:
00626   *     @arg GPIO_ETH_MediaInterface_MII: MII mode
00627   *     @arg GPIO_ETH_MediaInterface_RMII: RMII mode
00628   * @retval None
00629   */
00630 void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface)
00631 {
00632   assert_param(IS_GPIO_ETH_MEDIA_INTERFACE(GPIO_ETH_MediaInterface));
00633
00634   /* Configure MII_RMII selection bit */
00635   *(__IO uint32_t *) MAPR_MII_RMII_SEL_BB = GPIO_ETH_MediaInterface;
00636 }
00637
00638 /**
00639   * @}
00640   */
00641
00642 /**
00643   * @}
00644   */
00645
00646 /**
00647   * @}
00648   */
00649
00650 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_gpio.h Source File

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stm32f10x_gpio.h

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f10x_gpio.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    11-March-2011
00007   * @brief   This file contains all the functions prototypes for the GPIO
00008   *          firmware library.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00013   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00014   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00015   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00016   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00017   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00018   *
00019   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00020   ******************************************************************************
00021   */
00022
00023 /* Define to prevent recursive inclusion -------------------------------------*/
00024 #ifndef __STM32F10x_GPIO_H
00025 #define __STM32F10x_GPIO_H
00026
00027 #ifdef __cplusplus
00028  extern "C" {
00029 #endif
00030
00031 /* Includes ------------------------------------------------------------------*/
00032 #include "stm32f10x.h"
00033
00034 /** @addtogroup STM32F10x_StdPeriph_Driver
00035   * @{
00036   */
00037
00038 /** @addtogroup GPIO
00039   * @{
00040   */
00041
00042 /** @defgroup GPIO_Exported_Types
00043   * @{
00044   */
00045
00046 #define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
00047                                     ((PERIPH) == GPIOB) || \
00048                                     ((PERIPH) == GPIOC) || \
00049                                     ((PERIPH) == GPIOD) || \
00050                                     ((PERIPH) == GPIOE) || \
00051                                     ((PERIPH) == GPIOF) || \
00052                                     ((PERIPH) == GPIOG))
00053
00054 /**
00055   * @brief  Output Maximum frequency selection
00056   */
00057
00058 typedef enum
00059 {
00060   GPIO_Speed_10MHz = 1,
00061   GPIO_Speed_2MHz,
00062   GPIO_Speed_50MHz
00063 }GPIOSpeed_TypeDef;
00064 #define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_10MHz) || ((SPEED) == GPIO_Speed_2MHz) || \
00065                               ((SPEED) == GPIO_Speed_50MHz))
00066
00067 /**
00068   * @brief  Configuration Mode enumeration
00069   */
00070
00071 typedef enum
00072 { GPIO_Mode_AIN = 0x0,
00073   GPIO_Mode_IN_FLOATING = 0x04,
00074   GPIO_Mode_IPD = 0x28,
00075   GPIO_Mode_IPU = 0x48,
00076   GPIO_Mode_Out_OD = 0x14,
00077   GPIO_Mode_Out_PP = 0x10,
00078   GPIO_Mode_AF_OD = 0x1C,
00079   GPIO_Mode_AF_PP = 0x18
00080 }GPIOMode_TypeDef;
00081
00082 #define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_AIN) || ((MODE) == GPIO_Mode_IN_FLOATING) || \
00083                             ((MODE) == GPIO_Mode_IPD) || ((MODE) == GPIO_Mode_IPU) || \
00084                             ((MODE) == GPIO_Mode_Out_OD) || ((MODE) == GPIO_Mode_Out_PP) || \
00085                             ((MODE) == GPIO_Mode_AF_OD) || ((MODE) == GPIO_Mode_AF_PP))
00086
00087 /**
00088   * @brief  GPIO Init structure definition
00089   */
00090
00091 typedef struct
00092 {
00093   uint16_t GPIO_Pin;             /*!< Specifies the GPIO pins to be configured.
00094                                       This parameter can be any value of @ref GPIO_pins_define */
00095
00096   GPIOSpeed_TypeDef GPIO_Speed;  /*!< Specifies the speed for the selected pins.
00097                                       This parameter can be a value of @ref GPIOSpeed_TypeDef */
00098
00099   GPIOMode_TypeDef GPIO_Mode;    /*!< Specifies the operating mode for the selected pins.
00100                                       This parameter can be a value of @ref GPIOMode_TypeDef */
00101 }GPIO_InitTypeDef;
00102
00103
00104 /**
00105   * @brief  Bit_SET and Bit_RESET enumeration
00106   */
00107
00108 typedef enum
00109 { Bit_RESET = 0,
00110   Bit_SET
00111 }BitAction;
00112
00113 #define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))
00114
00115 /**
00116   * @}
00117   */
00118
00119 /** @defgroup GPIO_Exported_Constants
00120   * @{
00121   */
00122
00123 /** @defgroup GPIO_pins_define
00124   * @{
00125   */
00126
00127 #define GPIO_Pin_0                 ((uint16_t)0x0001)  /*!< Pin 0 selected */
00128 #define GPIO_Pin_1                 ((uint16_t)0x0002)  /*!< Pin 1 selected */
00129 #define GPIO_Pin_2                 ((uint16_t)0x0004)  /*!< Pin 2 selected */
00130 #define GPIO_Pin_3                 ((uint16_t)0x0008)  /*!< Pin 3 selected */
00131 #define GPIO_Pin_4                 ((uint16_t)0x0010)  /*!< Pin 4 selected */
00132 #define GPIO_Pin_5                 ((uint16_t)0x0020)  /*!< Pin 5 selected */
00133 #define GPIO_Pin_6                 ((uint16_t)0x0040)  /*!< Pin 6 selected */
00134 #define GPIO_Pin_7                 ((uint16_t)0x0080)  /*!< Pin 7 selected */
00135 #define GPIO_Pin_8                 ((uint16_t)0x0100)  /*!< Pin 8 selected */
00136 #define GPIO_Pin_9                 ((uint16_t)0x0200)  /*!< Pin 9 selected */
00137 #define GPIO_Pin_10                ((uint16_t)0x0400)  /*!< Pin 10 selected */
00138 #define GPIO_Pin_11                ((uint16_t)0x0800)  /*!< Pin 11 selected */
00139 #define GPIO_Pin_12                ((uint16_t)0x1000)  /*!< Pin 12 selected */
00140 #define GPIO_Pin_13                ((uint16_t)0x2000)  /*!< Pin 13 selected */
00141 #define GPIO_Pin_14                ((uint16_t)0x4000)  /*!< Pin 14 selected */
00142 #define GPIO_Pin_15                ((uint16_t)0x8000)  /*!< Pin 15 selected */
00143 #define GPIO_Pin_All               ((uint16_t)0xFFFF)  /*!< All pins selected */
00144
00145 #define IS_GPIO_PIN(PIN) ((((PIN) & (uint16_t)0x00) == 0x00) && ((PIN) != (uint16_t)0x00))
00146
00147 #define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \
00148                               ((PIN) == GPIO_Pin_1) || \
00149                               ((PIN) == GPIO_Pin_2) || \
00150                               ((PIN) == GPIO_Pin_3) || \
00151                               ((PIN) == GPIO_Pin_4) || \
00152                               ((PIN) == GPIO_Pin_5) || \
00153                               ((PIN) == GPIO_Pin_6) || \
00154                               ((PIN) == GPIO_Pin_7) || \
00155                               ((PIN) == GPIO_Pin_8) || \
00156                               ((PIN) == GPIO_Pin_9) || \
00157                               ((PIN) == GPIO_Pin_10) || \
00158                               ((PIN) == GPIO_Pin_11) || \
00159                               ((PIN) == GPIO_Pin_12) || \
00160                               ((PIN) == GPIO_Pin_13) || \
00161                               ((PIN) == GPIO_Pin_14) || \
00162                               ((PIN) == GPIO_Pin_15))
00163
00164 /**
00165   * @}
00166   */
00167
00168 /** @defgroup GPIO_Remap_define
00169   * @{
00170   */
00171
00172 #define GPIO_Remap_SPI1             ((uint32_t)0x00000001)  /*!< SPI1 Alternate Function mapping */
00173 #define GPIO_Remap_I2C1             ((uint32_t)0x00000002)  /*!< I2C1 Alternate Function mapping */
00174 #define GPIO_Remap_USART1           ((uint32_t)0x00000004)  /*!< USART1 Alternate Function mapping */
00175 #define GPIO_Remap_USART2           ((uint32_t)0x00000008)  /*!< USART2 Alternate Function mapping */
00176 #define GPIO_PartialRemap_USART3    ((uint32_t)0x00140010)  /*!< USART3 Partial Alternate Function mapping */
00177 #define GPIO_FullRemap_USART3       ((uint32_t)0x00140030)  /*!< USART3 Full Alternate Function mapping */
00178 #define GPIO_PartialRemap_TIM1      ((uint32_t)0x00160040)  /*!< TIM1 Partial Alternate Function mapping */
00179 #define GPIO_FullRemap_TIM1         ((uint32_t)0x001600C0)  /*!< TIM1 Full Alternate Function mapping */
00180 #define GPIO_PartialRemap1_TIM2     ((uint32_t)0x00180100)  /*!< TIM2 Partial1 Alternate Function mapping */
00181 #define GPIO_PartialRemap2_TIM2     ((uint32_t)0x00180200)  /*!< TIM2 Partial2 Alternate Function mapping */
00182 #define GPIO_FullRemap_TIM2         ((uint32_t)0x00180300)  /*!< TIM2 Full Alternate Function mapping */
00183 #define GPIO_PartialRemap_TIM3      ((uint32_t)0x001A0800)  /*!< TIM3 Partial Alternate Function mapping */
00184 #define GPIO_FullRemap_TIM3         ((uint32_t)0x001A0C00)  /*!< TIM3 Full Alternate Function mapping */
00185 #define GPIO_Remap_TIM4             ((uint32_t)0x00001000)  /*!< TIM4 Alternate Function mapping */
00186 #define GPIO_Remap1_CAN1            ((uint32_t)0x001D4000)  /*!< CAN1 Alternate Function mapping */
00187 #define GPIO_Remap2_CAN1            ((uint32_t)0x001D6000)  /*!< CAN1 Alternate Function mapping */
00188 #define GPIO_Remap_PD01             ((uint32_t)0x00008000)  /*!< PD01 Alternate Function mapping */
00189 #define GPIO_Remap_TIM5CH4_LSI      ((uint32_t)0x00200001)  /*!< LSI connected to TIM5 Channel4 input capture for calibration */
00190 #define GPIO_Remap_ADC1_ETRGINJ     ((uint32_t)0x00200002)  /*!< ADC1 External Trigger Injected Conversion remapping */
00191 #define GPIO_Remap_ADC1_ETRGREG     ((uint32_t)0x00200004)  /*!< ADC1 External Trigger Regular Conversion remapping */
00192 #define GPIO_Remap_ADC2_ETRGINJ     ((uint32_t)0x00200008)  /*!< ADC2 External Trigger Injected Conversion remapping */
00193 #define GPIO_Remap_ADC2_ETRGREG     ((uint32_t)0x00200010)  /*!< ADC2 External Trigger Regular Conversion remapping */
00194 #define GPIO_Remap_ETH              ((uint32_t)0x00200020)  /*!< Ethernet remapping (only for Connectivity line devices) */
00195 #define GPIO_Remap_CAN2             ((uint32_t)0x00200040)  /*!< CAN2 remapping (only for Connectivity line devices) */
00196 #define GPIO_Remap_SWJ_NoJTRST      ((uint32_t)0x00300100)  /*!< Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST */
00197 #define GPIO_Remap_SWJ_JTAGDisable  ((uint32_t)0x00300200)  /*!< JTAG-DP Disabled and SW-DP Enabled */
00198 #define GPIO_Remap_SWJ_Disable      ((uint32_t)0x00300400)  /*!< Full SWJ Disabled (JTAG-DP + SW-DP) */
00199 #define GPIO_Remap_SPI3             ((uint32_t)0x00201100)  /*!< SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices) */
00200 #define GPIO_Remap_TIM2ITR1_PTP_SOF ((uint32_t)0x00202000)  /*!< Ethernet PTP output or USB OTG SOF (Start of Frame) connected
00201                                                                  to TIM2 Internal Trigger 1 for calibration
00202                                                                  (only for Connectivity line devices) */
00203 #define GPIO_Remap_PTP_PPS          ((uint32_t)0x00204000)  /*!< Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices) */
00204
00205 #define GPIO_Remap_TIM15            ((uint32_t)0x80000001)  /*!< TIM15 Alternate Function mapping (only for Value line devices) */
00206 #define GPIO_Remap_TIM16            ((uint32_t)0x80000002)  /*!< TIM16 Alternate Function mapping (only for Value line devices) */
00207 #define GPIO_Remap_TIM17            ((uint32_t)0x80000004)  /*!< TIM17 Alternate Function mapping (only for Value line devices) */
00208 #define GPIO_Remap_CEC              ((uint32_t)0x80000008)  /*!< CEC Alternate Function mapping (only for Value line devices) */
00209 #define GPIO_Remap_TIM1_DMA         ((uint32_t)0x80000010)  /*!< TIM1 DMA requests mapping (only for Value line devices) */
00210
00211 #define GPIO_Remap_TIM9             ((uint32_t)0x80000020)  /*!< TIM9 Alternate Function mapping (only for XL-density devices) */
00212 #define GPIO_Remap_TIM10            ((uint32_t)0x80000040)  /*!< TIM10 Alternate Function mapping (only for XL-density devices) */
00213 #define GPIO_Remap_TIM11            ((uint32_t)0x80000080)  /*!< TIM11 Alternate Function mapping (only for XL-density devices) */
00214 #define GPIO_Remap_TIM13            ((uint32_t)0x80000100)  /*!< TIM13 Alternate Function mapping (only for High density Value line and XL-density devices) */
00215 #define GPIO_Remap_TIM14            ((uint32_t)0x80000200)  /*!< TIM14 Alternate Function mapping (only for High density Value line and XL-density devices) */
00216 #define GPIO_Remap_FSMC_NADV        ((uint32_t)0x80000400)  /*!< FSMC_NADV Alternate Function mapping (only for High density Value line and XL-density devices) */
00217
00218 #define GPIO_Remap_TIM67_DAC_DMA    ((uint32_t)0x80000800)  /*!< TIM6/TIM7 and DAC DMA requests remapping (only for High density Value line devices) */
00219 #define GPIO_Remap_TIM12            ((uint32_t)0x80001000)  /*!< TIM12 Alternate Function mapping (only for High density Value line devices) */
00220 #define GPIO_Remap_MISC             ((uint32_t)0x80002000)  /*!< Miscellaneous Remap (DMA2 Channel5 Position and DAC Trigger remapping,
00221                                                                  only for High density Value line devices) */
00222
00223 #define IS_GPIO_REMAP(REMAP) (((REMAP) == GPIO_Remap_SPI1) || ((REMAP) == GPIO_Remap_I2C1) || \
00224                               ((REMAP) == GPIO_Remap_USART1) || ((REMAP) == GPIO_Remap_USART2) || \
00225                               ((REMAP) == GPIO_PartialRemap_USART3) || ((REMAP) == GPIO_FullRemap_USART3) || \
00226                               ((REMAP) == GPIO_PartialRemap_TIM1) || ((REMAP) == GPIO_FullRemap_TIM1) || \
00227                               ((REMAP) == GPIO_PartialRemap1_TIM2) || ((REMAP) == GPIO_PartialRemap2_TIM2) || \
00228                               ((REMAP) == GPIO_FullRemap_TIM2) || ((REMAP) == GPIO_PartialRemap_TIM3) || \
00229                               ((REMAP) == GPIO_FullRemap_TIM3) || ((REMAP) == GPIO_Remap_TIM4) || \
00230                               ((REMAP) == GPIO_Remap1_CAN1) || ((REMAP) == GPIO_Remap2_CAN1) || \
00231                               ((REMAP) == GPIO_Remap_PD01) || ((REMAP) == GPIO_Remap_TIM5CH4_LSI) || \
00232                               ((REMAP) == GPIO_Remap_ADC1_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC1_ETRGREG) || \
00233                               ((REMAP) == GPIO_Remap_ADC2_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC2_ETRGREG) || \
00234                               ((REMAP) == GPIO_Remap_ETH) ||((REMAP) == GPIO_Remap_CAN2) || \
00235                               ((REMAP) == GPIO_Remap_SWJ_NoJTRST) || ((REMAP) == GPIO_Remap_SWJ_JTAGDisable) || \
00236                               ((REMAP) == GPIO_Remap_SWJ_Disable)|| ((REMAP) == GPIO_Remap_SPI3) || \
00237                               ((REMAP) == GPIO_Remap_TIM2ITR1_PTP_SOF) || ((REMAP) == GPIO_Remap_PTP_PPS) || \
00238                               ((REMAP) == GPIO_Remap_TIM15) || ((REMAP) == GPIO_Remap_TIM16) || \
00239                               ((REMAP) == GPIO_Remap_TIM17) || ((REMAP) == GPIO_Remap_CEC) || \
00240                               ((REMAP) == GPIO_Remap_TIM1_DMA) || ((REMAP) == GPIO_Remap_TIM9) || \
00241                               ((REMAP) == GPIO_Remap_TIM10) || ((REMAP) == GPIO_Remap_TIM11) || \
00242                               ((REMAP) == GPIO_Remap_TIM13) || ((REMAP) == GPIO_Remap_TIM14) || \
00243                               ((REMAP) == GPIO_Remap_FSMC_NADV) || ((REMAP) == GPIO_Remap_TIM67_DAC_DMA) || \
00244                               ((REMAP) == GPIO_Remap_TIM12) || ((REMAP) == GPIO_Remap_MISC))
00245
00246 /**
00247   * @}
00248   */
00249
00250 /** @defgroup GPIO_Port_Sources
00251   * @{
00252   */
00253
00254 #define GPIO_PortSourceGPIOA       ((uint8_t)0x00)
00255 #define GPIO_PortSourceGPIOB       ((uint8_t)0x01)
00256 #define GPIO_PortSourceGPIOC       ((uint8_t)0x02)
00257 #define GPIO_PortSourceGPIOD       ((uint8_t)0x03)
00258 #define GPIO_PortSourceGPIOE       ((uint8_t)0x04)
00259 #define GPIO_PortSourceGPIOF       ((uint8_t)0x05)
00260 #define GPIO_PortSourceGPIOG       ((uint8_t)0x06)
00261 #define IS_GPIO_EVENTOUT_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \
00262                                                   ((PORTSOURCE) == GPIO_PortSourceGPIOB) || \
00263                                                   ((PORTSOURCE) == GPIO_PortSourceGPIOC) || \
00264                                                   ((PORTSOURCE) == GPIO_PortSourceGPIOD) || \
00265                                                   ((PORTSOURCE) == GPIO_PortSourceGPIOE))
00266
00267 #define IS_GPIO_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \
00268                                               ((PORTSOURCE) == GPIO_PortSourceGPIOB) || \
00269                                               ((PORTSOURCE) == GPIO_PortSourceGPIOC) || \
00270                                               ((PORTSOURCE) == GPIO_PortSourceGPIOD) || \
00271                                               ((PORTSOURCE) == GPIO_PortSourceGPIOE) || \
00272                                               ((PORTSOURCE) == GPIO_PortSourceGPIOF) || \
00273                                               ((PORTSOURCE) == GPIO_PortSourceGPIOG))
00274
00275 /**
00276   * @}
00277   */
00278
00279 /** @defgroup GPIO_Pin_sources
00280   * @{
00281   */
00282
00283 #define GPIO_PinSource0            ((uint8_t)0x00)
00284 #define GPIO_PinSource1            ((uint8_t)0x01)
00285 #define GPIO_PinSource2            ((uint8_t)0x02)
00286 #define GPIO_PinSource3            ((uint8_t)0x03)
00287 #define GPIO_PinSource4            ((uint8_t)0x04)
00288 #define GPIO_PinSource5            ((uint8_t)0x05)
00289 #define GPIO_PinSource6            ((uint8_t)0x06)
00290 #define GPIO_PinSource7            ((uint8_t)0x07)
00291 #define GPIO_PinSource8            ((uint8_t)0x08)
00292 #define GPIO_PinSource9            ((uint8_t)0x09)
00293 #define GPIO_PinSource10           ((uint8_t)0x0A)
00294 #define GPIO_PinSource11           ((uint8_t)0x0B)
00295 #define GPIO_PinSource12           ((uint8_t)0x0C)
00296 #define GPIO_PinSource13           ((uint8_t)0x0D)
00297 #define GPIO_PinSource14           ((uint8_t)0x0E)
00298 #define GPIO_PinSource15           ((uint8_t)0x0F)
00299
00300 #define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \
00301                                        ((PINSOURCE) == GPIO_PinSource1) || \
00302                                        ((PINSOURCE) == GPIO_PinSource2) || \
00303                                        ((PINSOURCE) == GPIO_PinSource3) || \
00304                                        ((PINSOURCE) == GPIO_PinSource4) || \
00305                                        ((PINSOURCE) == GPIO_PinSource5) || \
00306                                        ((PINSOURCE) == GPIO_PinSource6) || \
00307                                        ((PINSOURCE) == GPIO_PinSource7) || \
00308                                        ((PINSOURCE) == GPIO_PinSource8) || \
00309                                        ((PINSOURCE) == GPIO_PinSource9) || \
00310                                        ((PINSOURCE) == GPIO_PinSource10) || \
00311                                        ((PINSOURCE) == GPIO_PinSource11) || \
00312                                        ((PINSOURCE) == GPIO_PinSource12) || \
00313                                        ((PINSOURCE) == GPIO_PinSource13) || \
00314                                        ((PINSOURCE) == GPIO_PinSource14) || \
00315                                        ((PINSOURCE) == GPIO_PinSource15))
00316
00317 /**
00318   * @}
00319   */
00320
00321 /** @defgroup Ethernet_Media_Interface
00322   * @{
00323   */
00324 #define GPIO_ETH_MediaInterface_MII    ((u32)0x00000000)
00325 #define GPIO_ETH_MediaInterface_RMII   ((u32)0x00000001)
00326
00327 #define IS_GPIO_ETH_MEDIA_INTERFACE(INTERFACE) (((INTERFACE) == GPIO_ETH_MediaInterface_MII) || \
00328                                                 ((INTERFACE) == GPIO_ETH_MediaInterface_RMII))
00329
00330 /**
00331   * @}
00332   */
00333 /**
00334   * @}
00335   */
00336
00337 /** @defgroup GPIO_Exported_Macros
00338   * @{
00339   */
00340
00341 /**
00342   * @}
00343   */
00344
00345 /** @defgroup GPIO_Exported_Functions
00346   * @{
00347   */
00348
00349 void GPIO_DeInit(GPIO_TypeDef* GPIOx);
00350 void GPIO_AFIODeInit(void);
00351 void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
00352 void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);
00353 uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
00354 uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);
00355 uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
00356 uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);
00357 void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
00358 void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
00359 void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal);
00360 void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal);
00361 void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
00362 void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource);
00363 void GPIO_EventOutputCmd(FunctionalState NewState);
00364 void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState);
00365 void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource);
00366 void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface);
00367
00368 #ifdef __cplusplus
00369 }
00370 #endif
00371
00372 #endif /* __STM32F10x_GPIO_H */
00373 /**
00374   * @}
00375   */
00376
00377 /**
00378   * @}
00379   */
00380
00381 /**
00382   * @}
00383   */
00384
00385 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_i2c.c Source File

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stm32f10x_i2c.c

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f10x_i2c.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    11-March-2011
00007   * @brief   This file provides all the I2C firmware functions.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x_i2c.h"
00024 #include "stm32f10x_rcc.h"
00025
00026
00027 /** @addtogroup STM32F10x_StdPeriph_Driver
00028   * @{
00029   */
00030
00031 /** @defgroup I2C
00032   * @brief I2C driver modules
00033   * @{
00034   */
00035
00036 /** @defgroup I2C_Private_TypesDefinitions
00037   * @{
00038   */
00039
00040 /**
00041   * @}
00042   */
00043
00044 /** @defgroup I2C_Private_Defines
00045   * @{
00046   */
00047
00048 /* I2C SPE mask */
00049 #define CR1_PE_Set              ((uint16_t)0x0001)
00050 #define CR1_PE_Reset            ((uint16_t)0xFFFE)
00051
00052 /* I2C START mask */
00053 #define CR1_START_Set           ((uint16_t)0x0100)
00054 #define CR1_START_Reset         ((uint16_t)0xFEFF)
00055
00056 /* I2C STOP mask */
00057 #define CR1_STOP_Set            ((uint16_t)0x0200)
00058 #define CR1_STOP_Reset          ((uint16_t)0xFDFF)
00059
00060 /* I2C ACK mask */
00061 #define CR1_ACK_Set             ((uint16_t)0x0400)
00062 #define CR1_ACK_Reset           ((uint16_t)0xFBFF)
00063
00064 /* I2C ENGC mask */
00065 #define CR1_ENGC_Set            ((uint16_t)0x0040)
00066 #define CR1_ENGC_Reset          ((uint16_t)0xFFBF)
00067
00068 /* I2C SWRST mask */
00069 #define CR1_SWRST_Set           ((uint16_t)0x8000)
00070 #define CR1_SWRST_Reset         ((uint16_t)0x7FFF)
00071
00072 /* I2C PEC mask */
00073 #define CR1_PEC_Set             ((uint16_t)0x1000)
00074 #define CR1_PEC_Reset           ((uint16_t)0xEFFF)
00075
00076 /* I2C ENPEC mask */
00077 #define CR1_ENPEC_Set           ((uint16_t)0x0020)
00078 #define CR1_ENPEC_Reset         ((uint16_t)0xFFDF)
00079
00080 /* I2C ENARP mask */
00081 #define CR1_ENARP_Set           ((uint16_t)0x0010)
00082 #define CR1_ENARP_Reset         ((uint16_t)0xFFEF)
00083
00084 /* I2C NOSTRETCH mask */
00085 #define CR1_NOSTRETCH_Set       ((uint16_t)0x0080)
00086 #define CR1_NOSTRETCH_Reset     ((uint16_t)0xFF7F)
00087
00088 /* I2C registers Masks */
00089 #define CR1_CLEAR_Mask          ((uint16_t)0xFBF5)
00090
00091 /* I2C DMAEN mask */
00092 #define CR2_DMAEN_Set           ((uint16_t)0x0800)
00093 #define CR2_DMAEN_Reset         ((uint16_t)0xF7FF)
00094
00095 /* I2C LAST mask */
00096 #define CR2_LAST_Set            ((uint16_t)0x1000)
00097 #define CR2_LAST_Reset          ((uint16_t)0xEFFF)
00098
00099 /* I2C FREQ mask */
00100 #define CR2_FREQ_Reset          ((uint16_t)0xFFC0)
00101
00102 /* I2C ADD0 mask */
00103 #define OAR1_ADD0_Set           ((uint16_t)0x0001)
00104 #define OAR1_ADD0_Reset         ((uint16_t)0xFFFE)
00105
00106 /* I2C ENDUAL mask */
00107 #define OAR2_ENDUAL_Set         ((uint16_t)0x0001)
00108 #define OAR2_ENDUAL_Reset       ((uint16_t)0xFFFE)
00109
00110 /* I2C ADD2 mask */
00111 #define OAR2_ADD2_Reset         ((uint16_t)0xFF01)
00112
00113 /* I2C F/S mask */
00114 #define CCR_FS_Set              ((uint16_t)0x8000)
00115
00116 /* I2C CCR mask */
00117 #define CCR_CCR_Set             ((uint16_t)0x0FFF)
00118
00119 /* I2C FLAG mask */
00120 #define FLAG_Mask               ((uint32_t)0x00FFFFFF)
00121
00122 /* I2C Interrupt Enable mask */
00123 #define ITEN_Mask               ((uint32_t)0x07000000)
00124
00125 /**
00126   * @}
00127   */
00128
00129 /** @defgroup I2C_Private_Macros
00130   * @{
00131   */
00132
00133 /**
00134   * @}
00135   */
00136
00137 /** @defgroup I2C_Private_Variables
00138   * @{
00139   */
00140
00141 /**
00142   * @}
00143   */
00144
00145 /** @defgroup I2C_Private_FunctionPrototypes
00146   * @{
00147   */
00148
00149 /**
00150   * @}
00151   */
00152
00153 /** @defgroup I2C_Private_Functions
00154   * @{
00155   */
00156
00157 /**
00158   * @brief  Deinitializes the I2Cx peripheral registers to their default reset values.
00159   * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
00160   * @retval None
00161   */
00162 void I2C_DeInit(I2C_TypeDef* I2Cx)
00163 {
00164   /* Check the parameters */
00165   assert_param(IS_I2C_ALL_PERIPH(I2Cx));
00166
00167   if (I2Cx == I2C1)
00168   {
00169     /* Enable I2C1 reset state */
00170     RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE);
00171     /* Release I2C1 from reset state */
00172     RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE);
00173   }
00174   else
00175   {
00176     /* Enable I2C2 reset state */
00177     RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE);
00178     /* Release I2C2 from reset state */
00179     RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, DISABLE);
00180   }
00181 }
00182
00183 /**
00184   * @brief  Initializes the I2Cx peripheral according to the specified
00185   *   parameters in the I2C_InitStruct.
00186   * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
00187   * @param  I2C_InitStruct: pointer to a I2C_InitTypeDef structure that
00188   *   contains the configuration information for the specified I2C peripheral.
00189   * @retval None
00190   */
00191 void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct)
00192 {
00193   uint16_t tmpreg = 0, freqrange = 0;
00194   uint16_t result = 0x04;
00195   uint32_t pclk1 = 8000000;
00196   RCC_ClocksTypeDef  rcc_clocks;
00197   /* Check the parameters */
00198   assert_param(IS_I2C_ALL_PERIPH(I2Cx));
00199   assert_param(IS_I2C_CLOCK_SPEED(I2C_InitStruct->I2C_ClockSpeed));
00200   assert_param(IS_I2C_MODE(I2C_InitStruct->I2C_Mode));
00201   assert_param(IS_I2C_DUTY_CYCLE(I2C_InitStruct->I2C_DutyCycle));
00202   assert_param(IS_I2C_OWN_ADDRESS1(I2C_InitStruct->I2C_OwnAddress1));
00203   assert_param(IS_I2C_ACK_STATE(I2C_InitStruct->I2C_Ack));
00204   assert_param(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AcknowledgedAddress));
00205
00206 /*---------------------------- I2Cx CR2 Configuration ------------------------*/
00207   /* Get the I2Cx CR2 value */
00208   tmpreg = I2Cx->CR2;
00209   /* Clear frequency FREQ[5:0] bits */
00210   tmpreg &= CR2_FREQ_Reset;
00211   /* Get pclk1 frequency value */
00212   RCC_GetClocksFreq(&rcc_clocks);
00213   pclk1 = rcc_clocks.PCLK1_Frequency;
00214   /* Set frequency bits depending on pclk1 value */
00215   freqrange = (uint16_t)(pclk1 / 1000000);
00216   tmpreg |= freqrange;
00217   /* Write to I2Cx CR2 */
00218   I2Cx->CR2 = tmpreg;
00219
00220 /*---------------------------- I2Cx CCR Configuration ------------------------*/
00221   /* Disable the selected I2C peripheral to configure TRISE */
00222   I2Cx->CR1 &= CR1_PE_Reset;
00223   /* Reset tmpreg value */
00224   /* Clear F/S, DUTY and CCR[11:0] bits */
00225   tmpreg = 0;
00226
00227   /* Configure speed in standard mode */
00228   if (I2C_InitStruct->I2C_ClockSpeed <= 100000)
00229   {
00230     /* Standard mode speed calculate */
00231     result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1));
00232     /* Test if CCR value is under 0x4*/
00233     if (result < 0x04)
00234     {
00235       /* Set minimum allowed value */
00236       result = 0x04;
00237     }
00238     /* Set speed value for standard mode */
00239     tmpreg |= result;
00240     /* Set Maximum Rise Time for standard mode */
00241     I2Cx->TRISE = freqrange + 1;
00242   }
00243   /* Configure speed in fast mode */
00244   else /*(I2C_InitStruct->I2C_ClockSpeed <= 400000)*/
00245   {
00246     if (I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2)
00247     {
00248       /* Fast mode speed calculate: Tlow/Thigh = 2 */
00249       result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3));
00250     }
00251     else /*I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_16_9*/
00252     {
00253       /* Fast mode speed calculate: Tlow/Thigh = 16/9 */
00254       result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25));
00255       /* Set DUTY bit */
00256       result |= I2C_DutyCycle_16_9;
00257     }
00258
00259     /* Test if CCR value is under 0x1*/
00260     if ((result & CCR_CCR_Set) == 0)
00261     {
00262       /* Set minimum allowed value */
00263       result |= (uint16_t)0x0001;
00264     }
00265     /* Set speed value and set F/S bit for fast mode */
00266     tmpreg |= (uint16_t)(result | CCR_FS_Set);
00267     /* Set Maximum Rise Time for fast mode */
00268     I2Cx->TRISE = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1);
00269   }
00270
00271   /* Write to I2Cx CCR */
00272   I2Cx->CCR = tmpreg;
00273   /* Enable the selected I2C peripheral */
00274   I2Cx->CR1 |= CR1_PE_Set;
00275
00276 /*---------------------------- I2Cx CR1 Configuration ------------------------*/
00277   /* Get the I2Cx CR1 value */
00278   tmpreg = I2Cx->CR1;
00279   /* Clear ACK, SMBTYPE and  SMBUS bits */
00280   tmpreg &= CR1_CLEAR_Mask;
00281   /* Configure I2Cx: mode and acknowledgement */
00282   /* Set SMBTYPE and SMBUS bits according to I2C_Mode value */
00283   /* Set ACK bit according to I2C_Ack value */
00284   tmpreg |= (uint16_t)((uint32_t)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack);
00285   /* Write to I2Cx CR1 */
00286   I2Cx->CR1 = tmpreg;
00287
00288 /*---------------------------- I2Cx OAR1 Configuration -----------------------*/
00289   /* Set I2Cx Own Address1 and acknowledged address */
00290   I2Cx->OAR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1);
00291 }
00292
00293 /**
00294   * @brief  Fills each I2C_InitStruct member with its default value.
00295   * @param  I2C_InitStruct: pointer to an I2C_InitTypeDef structure which will be initialized.
00296   * @retval None
00297   */
00298 void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct)
00299 {
00300 /*---------------- Reset I2C init structure parameters values ----------------*/
00301   /* initialize the I2C_ClockSpeed member */
00302   I2C_InitStruct->I2C_ClockSpeed = 5000;
00303   /* Initialize the I2C_Mode member */
00304   I2C_InitStruct->I2C_Mode = I2C_Mode_I2C;
00305   /* Initialize the I2C_DutyCycle member */
00306   I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2;
00307   /* Initialize the I2C_OwnAddress1 member */
00308   I2C_InitStruct->I2C_OwnAddress1 = 0;
00309   /* Initialize the I2C_Ack member */
00310   I2C_InitStruct->I2C_Ack = I2C_Ack_Disable;
00311   /* Initialize the I2C_AcknowledgedAddress member */
00312   I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
00313 }
00314
00315 /**
00316   * @brief  Enables or disables the specified I2C peripheral.
00317   * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
00318   * @param  NewState: new state of the I2Cx peripheral.
00319   *   This parameter can be: ENABLE or DISABLE.
00320   * @retval None
00321   */
00322 void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
00323 {
00324   /* Check the parameters */
00325   assert_param(IS_I2C_ALL_PERIPH(I2Cx));
00326   assert_param(IS_FUNCTIONAL_STATE(NewState));
00327   if (NewState != DISABLE)
00328   {
00329     /* Enable the selected I2C peripheral */
00330     I2Cx->CR1 |= CR1_PE_Set;
00331   }
00332   else
00333   {
00334     /* Disable the selected I2C peripheral */
00335     I2Cx->CR1 &= CR1_PE_Reset;
00336   }
00337 }
00338
00339 /**
00340   * @brief  Enables or disables the specified I2C DMA requests.
00341   * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
00342   * @param  NewState: new state of the I2C DMA transfer.
00343   *   This parameter can be: ENABLE or DISABLE.
00344   * @retval None
00345   */
00346 void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
00347 {
00348   /* Check the parameters */
00349   assert_param(IS_I2C_ALL_PERIPH(I2Cx));
00350   assert_param(IS_FUNCTIONAL_STATE(NewState));
00351   if (NewState != DISABLE)
00352   {
00353     /* Enable the selected I2C DMA requests */
00354     I2Cx->CR2 |= CR2_DMAEN_Set;
00355   }
00356   else
00357   {
00358     /* Disable the selected I2C DMA requests */
00359     I2Cx->CR2 &= CR2_DMAEN_Reset;
00360   }
00361 }
00362
00363 /**
00364   * @brief  Specifies if the next DMA transfer will be the last one.
00365   * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
00366   * @param  NewState: new state of the I2C DMA last transfer.
00367   *   This parameter can be: ENABLE or DISABLE.
00368   * @retval None
00369   */
00370 void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
00371 {
00372   /* Check the parameters */
00373   assert_param(IS_I2C_ALL_PERIPH(I2Cx));
00374   assert_param(IS_FUNCTIONAL_STATE(NewState));
00375   if (NewState != DISABLE)
00376   {
00377     /* Next DMA transfer is the last transfer */
00378     I2Cx->CR2 |= CR2_LAST_Set;
00379   }
00380   else
00381   {
00382     /* Next DMA transfer is not the last transfer */
00383     I2Cx->CR2 &= CR2_LAST_Reset;
00384   }
00385 }
00386
00387 /**
00388   * @brief  Generates I2Cx communication START condition.
00389   * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
00390   * @param  NewState: new state of the I2C START condition generation.
00391   *   This parameter can be: ENABLE or DISABLE.
00392   * @retval None.
00393   */
00394 void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState)
00395 {
00396   /* Check the parameters */
00397   assert_param(IS_I2C_ALL_PERIPH(I2Cx));
00398   assert_param(IS_FUNCTIONAL_STATE(NewState));
00399   if (NewState != DISABLE)
00400   {
00401     /* Generate a START condition */
00402     I2Cx->CR1 |= CR1_START_Set;
00403   }
00404   else
00405   {
00406     /* Disable the START condition generation */
00407     I2Cx->CR1 &= CR1_START_Reset;
00408   }
00409 }
00410
00411 /**
00412   * @brief  Generates I2Cx communication STOP condition.
00413   * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
00414   * @param  NewState: new state of the I2C STOP condition generation.
00415   *   This parameter can be: ENABLE or DISABLE.
00416   * @retval None.
00417   */
00418 void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState)
00419 {
00420   /* Check the parameters */
00421   assert_param(IS_I2C_ALL_PERIPH(I2Cx));
00422   assert_param(IS_FUNCTIONAL_STATE(NewState));
00423   if (NewState != DISABLE)
00424   {
00425     /* Generate a STOP condition */
00426     I2Cx->CR1 |= CR1_STOP_Set;
00427   }
00428   else
00429   {
00430     /* Disable the STOP condition generation */
00431     I2Cx->CR1 &= CR1_STOP_Reset;
00432   }
00433 }
00434
00435 /**
00436   * @brief  Enables or disables the specified I2C acknowledge feature.
00437   * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
00438   * @param  NewState: new state of the I2C Acknowledgement.
00439   *   This parameter can be: ENABLE or DISABLE.
00440   * @retval None.
00441   */
00442 void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState)
00443 {
00444   /* Check the parameters */
00445   assert_param(IS_I2C_ALL_PERIPH(I2Cx));
00446   assert_param(IS_FUNCTIONAL_STATE(NewState));
00447   if (NewState != DISABLE)
00448   {
00449     /* Enable the acknowledgement */
00450     I2Cx->CR1 |= CR1_ACK_Set;
00451   }
00452   else
00453   {
00454     /* Disable the acknowledgement */
00455     I2Cx->CR1 &= CR1_ACK_Reset;
00456   }
00457 }
00458
00459 /**
00460   * @brief  Configures the specified I2C own address2.
00461   * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
00462   * @param  Address: specifies the 7bit I2C own address2.
00463   * @retval None.
00464   */
00465 void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address)
00466 {
00467   uint16_t tmpreg = 0;
00468
00469   /* Check the parameters */
00470   assert_param(IS_I2C_ALL_PERIPH(I2Cx));
00471
00472   /* Get the old register value */
00473   tmpreg = I2Cx->OAR2;
00474
00475   /* Reset I2Cx Own address2 bit [7:1] */
00476   tmpreg &= OAR2_ADD2_Reset;
00477
00478   /* Set I2Cx Own address2 */
00479   tmpreg |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE);
00480
00481   /* Store the new register value */
00482   I2Cx->OAR2 = tmpreg;
00483 }
00484
00485 /**
00486   * @brief  Enables or disables the specified I2C dual addressing mode.
00487   * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
00488   * @param  NewState: new state of the I2C dual addressing mode.
00489   *   This parameter can be: ENABLE or DISABLE.
00490   * @retval None
00491   */
00492 void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
00493 {
00494   /* Check the parameters */
00495   assert_param(IS_I2C_ALL_PERIPH(I2Cx));
00496   assert_param(IS_FUNCTIONAL_STATE(NewState));
00497   if (NewState != DISABLE)
00498   {
00499     /* Enable dual addressing mode */
00500     I2Cx->OAR2 |= OAR2_ENDUAL_Set;
00501   }
00502   else
00503   {
00504     /* Disable dual addressing mode */
00505     I2Cx->OAR2 &= OAR2_ENDUAL_Reset;
00506   }
00507 }
00508
00509 /**
00510   * @brief  Enables or disables the specified I2C general call feature.
00511   * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
00512   * @param  NewState: new state of the I2C General call.
00513   *   This parameter can be: ENABLE or DISABLE.
00514   * @retval None
00515   */
00516 void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
00517 {
00518   /* Check the parameters */
00519   assert_param(IS_I2C_ALL_PERIPH(I2Cx));
00520   assert_param(IS_FUNCTIONAL_STATE(NewState));
00521   if (NewState != DISABLE)
00522   {
00523     /* Enable generall call */
00524     I2Cx->CR1 |= CR1_ENGC_Set;
00525   }
00526   else
00527   {
00528     /* Disable generall call */
00529     I2Cx->CR1 &= CR1_ENGC_Reset;
00530   }
00531 }
00532
00533 /**
00534   * @brief  Enables or disables the specified I2C interrupts.
00535   * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
00536   * @param  I2C_IT: specifies the I2C interrupts sources to be enabled or disabled.
00537   *   This parameter can be any combination of the following values:
00538   *     @arg I2C_IT_BUF: Buffer interrupt mask
00539   *     @arg I2C_IT_EVT: Event interrupt mask
00540   *     @arg I2C_IT_ERR: Error interrupt mask
00541   * @param  NewState: new state of the specified I2C interrupts.
00542   *   This parameter can be: ENABLE or DISABLE.
00543   * @retval None
00544   */
00545 void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState)
00546 {
00547   /* Check the parameters */
00548   assert_param(IS_I2C_ALL_PERIPH(I2Cx));
00549   assert_param(IS_FUNCTIONAL_STATE(NewState));
00550   assert_param(IS_I2C_CONFIG_IT(I2C_IT));
00551
00552   if (NewState != DISABLE)
00553   {
00554     /* Enable the selected I2C interrupts */
00555     I2Cx->CR2 |= I2C_IT;
00556   }
00557   else
00558   {
00559     /* Disable the selected I2C interrupts */
00560     I2Cx->CR2 &= (uint16_t)~I2C_IT;
00561   }
00562 }
00563
00564 /**
00565   * @brief  Sends a data byte through the I2Cx peripheral.
00566   * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
00567   * @param  Data: Byte to be transmitted..
00568   * @retval None
00569   */
00570 void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data)
00571 {
00572   /* Check the parameters */
00573   assert_param(IS_I2C_ALL_PERIPH(I2Cx));
00574   /* Write in the DR register the data to be sent */
00575   I2Cx->DR = Data;
00576 }
00577
00578 /**
00579   * @brief  Returns the most recent received data by the I2Cx peripheral.
00580   * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
00581   * @retval The value of the received data.
00582   */
00583 uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx)
00584 {
00585   /* Check the parameters */
00586   assert_param(IS_I2C_ALL_PERIPH(I2Cx));
00587   /* Return the data in the DR register */
00588   return (uint8_t)I2Cx->DR;
00589 }
00590
00591 /**
00592   * @brief  Transmits the address byte to select the slave device.
00593   * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
00594   * @param  Address: specifies the slave address which will be transmitted
00595   * @param  I2C_Direction: specifies whether the I2C device will be a
00596   *   Transmitter or a Receiver. This parameter can be one of the following values
00597   *     @arg I2C_Direction_Transmitter: Transmitter mode
00598   *     @arg I2C_Direction_Receiver: Receiver mode
00599   * @retval None.
00600   */
00601 void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction)
00602 {
00603   /* Check the parameters */
00604   assert_param(IS_I2C_ALL_PERIPH(I2Cx));
00605   assert_param(IS_I2C_DIRECTION(I2C_Direction));
00606   /* Test on the direction to set/reset the read/write bit */
00607   if (I2C_Direction != I2C_Direction_Transmitter)
00608   {
00609     /* Set the address bit0 for read */
00610     Address |= OAR1_ADD0_Set;
00611   }
00612   else
00613   {
00614     /* Reset the address bit0 for write */
00615     Address &= OAR1_ADD0_Reset;
00616   }
00617   /* Send the address */
00618   I2Cx->DR = Address;
00619 }
00620
00621 /**
00622   * @brief  Reads the specified I2C register and returns its value.
00623   * @param  I2C_Register: specifies the register to read.
00624   *   This parameter can be one of the following values:
00625   *     @arg I2C_Register_CR1:  CR1 register.
00626   *     @arg I2C_Register_CR2:   CR2 register.
00627   *     @arg I2C_Register_OAR1:  OAR1 register.
00628   *     @arg I2C_Register_OAR2:  OAR2 register.
00629   *     @arg I2C_Register_DR:    DR register.
00630   *     @arg I2C_Register_SR1:   SR1 register.
00631   *     @arg I2C_Register_SR2:   SR2 register.
00632   *     @arg I2C_Register_CCR:   CCR register.
00633   *     @arg I2C_Register_TRISE: TRISE register.
00634   * @retval The value of the read register.
00635   */
00636 uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register)
00637 {
00638   __IO uint32_t tmp = 0;
00639
00640   /* Check the parameters */
00641   assert_param(IS_I2C_ALL_PERIPH(I2Cx));
00642   assert_param(IS_I2C_REGISTER(I2C_Register));
00643
00644   tmp = (uint32_t) I2Cx;
00645   tmp += I2C_Register;
00646
00647   /* Return the selected register value */
00648   return (*(__IO uint16_t *) tmp);
00649 }
00650
00651 /**
00652   * @brief  Enables or disables the specified I2C software reset.
00653   * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
00654   * @param  NewState: new state of the I2C software reset.
00655   *   This parameter can be: ENABLE or DISABLE.
00656   * @retval None
00657   */
00658 void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
00659 {
00660   /* Check the parameters */
00661   assert_param(IS_I2C_ALL_PERIPH(I2Cx));
00662   assert_param(IS_FUNCTIONAL_STATE(NewState));
00663   if (NewState != DISABLE)
00664   {
00665     /* Peripheral under reset */
00666     I2Cx->CR1 |= CR1_SWRST_Set;
00667   }
00668   else
00669   {
00670     /* Peripheral not under reset */
00671     I2Cx->CR1 &= CR1_SWRST_Reset;
00672   }
00673 }
00674
00675 /**
00676   * @brief  Selects the specified I2C NACK position in master receiver mode.
00677   *         This function is useful in I2C Master Receiver mode when the number
00678   *         of data to be received is equal to 2. In this case, this function
00679   *         should be called (with parameter I2C_NACKPosition_Next) before data
00680   *         reception starts,as described in the 2-byte reception procedure
00681   *         recommended in Reference Manual in Section: Master receiver.
00682   * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
00683   * @param  I2C_NACKPosition: specifies the NACK position.
00684   *   This parameter can be one of the following values:
00685   *     @arg I2C_NACKPosition_Next: indicates that the next byte will be the last
00686   *          received byte.
00687   *     @arg I2C_NACKPosition_Current: indicates that current byte is the last
00688   *          received byte.
00689   *
00690   * @note    This function configures the same bit (POS) as I2C_PECPositionConfig()
00691   *          but is intended to be used in I2C mode while I2C_PECPositionConfig()
00692   *          is intended to used in SMBUS mode.
00693   *
00694   * @retval None
00695   */
00696 void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition)
00697 {
00698   /* Check the parameters */
00699   assert_param(IS_I2C_ALL_PERIPH(I2Cx));
00700   assert_param(IS_I2C_NACK_POSITION(I2C_NACKPosition));
00701
00702   /* Check the input parameter */
00703   if (I2C_NACKPosition == I2C_NACKPosition_Next)
00704   {
00705     /* Next byte in shift register is the last received byte */
00706     I2Cx->CR1 |= I2C_NACKPosition_Next;
00707   }
00708   else
00709   {
00710     /* Current byte in shift register is the last received byte */
00711     I2Cx->CR1 &= I2C_NACKPosition_Current;
00712   }
00713 }
00714
00715 /**
00716   * @brief  Drives the SMBusAlert pin high or low for the specified I2C.
00717   * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
00718   * @param  I2C_SMBusAlert: specifies SMBAlert pin level.
00719   *   This parameter can be one of the following values:
00720   *     @arg I2C_SMBusAlert_Low: SMBAlert pin driven low
00721   *     @arg I2C_SMBusAlert_High: SMBAlert pin driven high
00722   * @retval None
00723   */
00724 void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert)
00725 {
00726   /* Check the parameters */
00727   assert_param(IS_I2C_ALL_PERIPH(I2Cx));
00728   assert_param(IS_I2C_SMBUS_ALERT(I2C_SMBusAlert));
00729   if (I2C_SMBusAlert == I2C_SMBusAlert_Low)
00730   {
00731     /* Drive the SMBusAlert pin Low */
00732     I2Cx->CR1 |= I2C_SMBusAlert_Low;
00733   }
00734   else
00735   {
00736     /* Drive the SMBusAlert pin High  */
00737     I2Cx->CR1 &= I2C_SMBusAlert_High;
00738   }
00739 }
00740
00741 /**
00742   * @brief  Enables or disables the specified I2C PEC transfer.
00743   * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
00744   * @param  NewState: new state of the I2C PEC transmission.
00745   *   This parameter can be: ENABLE or DISABLE.
00746   * @retval None
00747   */
00748 void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState)
00749 {
00750   /* Check the parameters */
00751   assert_param(IS_I2C_ALL_PERIPH(I2Cx));
00752   assert_param(IS_FUNCTIONAL_STATE(NewState));
00753   if (NewState != DISABLE)
00754   {
00755     /* Enable the selected I2C PEC transmission */
00756     I2Cx->CR1 |= CR1_PEC_Set;
00757   }
00758   else
00759   {
00760     /* Disable the selected I2C PEC transmission */
00761     I2Cx->CR1 &= CR1_PEC_Reset;
00762   }
00763 }
00764
00765 /**
00766   * @brief  Selects the specified I2C PEC position.
00767   * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
00768   * @param  I2C_PECPosition: specifies the PEC position.
00769   *   This parameter can be one of the following values:
00770   *     @arg I2C_PECPosition_Next: indicates that the next byte is PEC
00771   *     @arg I2C_PECPosition_Current: indicates that current byte is PEC
00772   *
00773   * @note    This function configures the same bit (POS) as I2C_NACKPositionConfig()
00774   *          but is intended to be used in SMBUS mode while I2C_NACKPositionConfig()
00775   *          is intended to used in I2C mode.
00776   *
00777   * @retval None
00778   */
00779 void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition)
00780 {
00781   /* Check the parameters */
00782   assert_param(IS_I2C_ALL_PERIPH(I2Cx));
00783   assert_param(IS_I2C_PEC_POSITION(I2C_PECPosition));
00784   if (I2C_PECPosition == I2C_PECPosition_Next)
00785   {
00786     /* Next byte in shift register is PEC */
00787     I2Cx->CR1 |= I2C_PECPosition_Next;
00788   }
00789   else
00790   {
00791     /* Current byte in shift register is PEC */
00792     I2Cx->CR1 &= I2C_PECPosition_Current;
00793   }
00794 }
00795
00796 /**
00797   * @brief  Enables or disables the PEC value calculation of the transferred bytes.
00798   * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
00799   * @param  NewState: new state of the I2Cx PEC value calculation.
00800   *   This parameter can be: ENABLE or DISABLE.
00801   * @retval None
00802   */
00803 void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState)
00804 {
00805   /* Check the parameters */
00806   assert_param(IS_I2C_ALL_PERIPH(I2Cx));
00807   assert_param(IS_FUNCTIONAL_STATE(NewState));
00808   if (NewState != DISABLE)
00809   {
00810     /* Enable the selected I2C PEC calculation */
00811     I2Cx->CR1 |= CR1_ENPEC_Set;
00812   }
00813   else
00814   {
00815     /* Disable the selected I2C PEC calculation */
00816     I2Cx->CR1 &= CR1_ENPEC_Reset;
00817   }
00818 }
00819
00820 /**
00821   * @brief  Returns the PEC value for the specified I2C.
00822   * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
00823   * @retval The PEC value.
00824   */
00825 uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx)
00826 {
00827   /* Check the parameters */
00828   assert_param(IS_I2C_ALL_PERIPH(I2Cx));
00829   /* Return the selected I2C PEC value */
00830   return ((I2Cx->SR2) >> 8);
00831 }
00832
00833 /**
00834   * @brief  Enables or disables the specified I2C ARP.
00835   * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
00836   * @param  NewState: new state of the I2Cx ARP.
00837   *   This parameter can be: ENABLE or DISABLE.
00838   * @retval None
00839   */
00840 void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
00841 {
00842   /* Check the parameters */
00843   assert_param(IS_I2C_ALL_PERIPH(I2Cx));
00844   assert_param(IS_FUNCTIONAL_STATE(NewState));
00845   if (NewState != DISABLE)
00846   {
00847     /* Enable the selected I2C ARP */
00848     I2Cx->CR1 |= CR1_ENARP_Set;
00849   }
00850   else
00851   {
00852     /* Disable the selected I2C ARP */
00853     I2Cx->CR1 &= CR1_ENARP_Reset;
00854   }
00855 }
00856
00857 /**
00858   * @brief  Enables or disables the specified I2C Clock stretching.
00859   * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
00860   * @param  NewState: new state of the I2Cx Clock stretching.
00861   *   This parameter can be: ENABLE or DISABLE.
00862   * @retval None
00863   */
00864 void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
00865 {
00866   /* Check the parameters */
00867   assert_param(IS_I2C_ALL_PERIPH(I2Cx));
00868   assert_param(IS_FUNCTIONAL_STATE(NewState));
00869   if (NewState == DISABLE)
00870   {
00871     /* Enable the selected I2C Clock stretching */
00872     I2Cx->CR1 |= CR1_NOSTRETCH_Set;
00873   }
00874   else
00875   {
00876     /* Disable the selected I2C Clock stretching */
00877     I2Cx->CR1 &= CR1_NOSTRETCH_Reset;
00878   }
00879 }
00880
00881 /**
00882   * @brief  Selects the specified I2C fast mode duty cycle.
00883   * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
00884   * @param  I2C_DutyCycle: specifies the fast mode duty cycle.
00885   *   This parameter can be one of the following values:
00886   *     @arg I2C_DutyCycle_2: I2C fast mode Tlow/Thigh = 2
00887   *     @arg I2C_DutyCycle_16_9: I2C fast mode Tlow/Thigh = 16/9
00888   * @retval None
00889   */
00890 void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle)
00891 {
00892   /* Check the parameters */
00893   assert_param(IS_I2C_ALL_PERIPH(I2Cx));
00894   assert_param(IS_I2C_DUTY_CYCLE(I2C_DutyCycle));
00895   if (I2C_DutyCycle != I2C_DutyCycle_16_9)
00896   {
00897     /* I2C fast mode Tlow/Thigh=2 */
00898     I2Cx->CCR &= I2C_DutyCycle_2;
00899   }
00900   else
00901   {
00902     /* I2C fast mode Tlow/Thigh=16/9 */
00903     I2Cx->CCR |= I2C_DutyCycle_16_9;
00904   }
00905 }
00906
00907
00908
00909 /**
00910  * @brief
00911  ****************************************************************************************
00912  *
00913  *                         I2C State Monitoring Functions
00914  *
00915  ****************************************************************************************
00916  * This I2C driver provides three different ways for I2C state monitoring
00917  *  depending on the application requirements and constraints:
00918  *
00919  *
00920  * 1) Basic state monitoring:
00921  *    Using I2C_CheckEvent() function:
00922  *    It compares the status registers (SR1 and SR2) content to a given event
00923  *    (can be the combination of one or more flags).
00924  *    It returns SUCCESS if the current status includes the given flags
00925  *    and returns ERROR if one or more flags are missing in the current status.
00926  *    - When to use:
00927  *      - This function is suitable for most applications as well as for startup
00928  *      activity since the events are fully described in the product reference manual
00929  *      (RM0008).
00930  *      - It is also suitable for users who need to define their own events.
00931  *    - Limitations:
00932  *      - If an error occurs (ie. error flags are set besides to the monitored flags),
00933  *        the I2C_CheckEvent() function may return SUCCESS despite the communication
00934  *        hold or corrupted real state.
00935  *        In this case, it is advised to use error interrupts to monitor the error
00936  *        events and handle them in the interrupt IRQ handler.
00937  *
00938  *        @note
00939  *        For error management, it is advised to use the following functions:
00940  *          - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).
00941  *          - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs.
00942  *            Where x is the peripheral instance (I2C1, I2C2 ...)
00943  *          - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into I2Cx_ER_IRQHandler()
00944  *            in order to determine which error occured.
00945  *          - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd()
00946  *            and/or I2C_GenerateStop() in order to clear the error flag and source,
00947  *            and return to correct communication status.
00948  *
00949  *
00950  *  2) Advanced state monitoring:
00951  *     Using the function I2C_GetLastEvent() which returns the image of both status
00952  *     registers in a single word (uint32_t) (Status Register 2 value is shifted left
00953  *     by 16 bits and concatenated to Status Register 1).
00954  *     - When to use:
00955  *       - This function is suitable for the same applications above but it allows to
00956  *         overcome the mentioned limitation of I2C_GetFlagStatus() function.
00957  *         The returned value could be compared to events already defined in the
00958  *         library (stm32f10x_i2c.h) or to custom values defined by user.
00959  *       - This function is suitable when multiple flags are monitored at the same time.
00960  *       - At the opposite of I2C_CheckEvent() function, this function allows user to
00961  *         choose when an event is accepted (when all events flags are set and no
00962  *         other flags are set or just when the needed flags are set like
00963  *         I2C_CheckEvent() function).
00964  *     - Limitations:
00965  *       - User may need to define his own events.
00966  *       - Same remark concerning the error management is applicable for this
00967  *         function if user decides to check only regular communication flags (and
00968  *         ignores error flags).
00969  *
00970  *
00971  *  3) Flag-based state monitoring:
00972  *     Using the function I2C_GetFlagStatus() which simply returns the status of
00973  *     one single flag (ie. I2C_FLAG_RXNE ...).
00974  *     - When to use:
00975  *        - This function could be used for specific applications or in debug phase.
00976  *        - It is suitable when only one flag checking is needed (most I2C events
00977  *          are monitored through multiple flags).
00978  *     - Limitations:
00979  *        - When calling this function, the Status register is accessed. Some flags are
00980  *          cleared when the status register is accessed. So checking the status
00981  *          of one Flag, may clear other ones.
00982  *        - Function may need to be called twice or more in order to monitor one
00983  *          single event.
00984  *
00985  *  For detailed description of Events, please refer to section I2C_Events in
00986  *  stm32f10x_i2c.h file.
00987  *
00988  */
00989
00990 /**
00991  *
00992  *  1) Basic state monitoring
00993  *******************************************************************************
00994  */
00995
00996 /**
00997   * @brief  Checks whether the last I2Cx Event is equal to the one passed
00998   *   as parameter.
00999   * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
01000   * @param  I2C_EVENT: specifies the event to be checked.
01001   *   This parameter can be one of the following values:
01002   *     @arg I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED           : EV1
01003   *     @arg I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED              : EV1
01004   *     @arg I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED     : EV1
01005   *     @arg I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED        : EV1
01006   *     @arg I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED            : EV1
01007   *     @arg I2C_EVENT_SLAVE_BYTE_RECEIVED                         : EV2
01008   *     @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)      : EV2
01009   *     @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)    : EV2
01010   *     @arg I2C_EVENT_SLAVE_BYTE_TRANSMITTED                      : EV3
01011   *     @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)   : EV3
01012   *     @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL) : EV3
01013   *     @arg I2C_EVENT_SLAVE_ACK_FAILURE                           : EV3_2
01014   *     @arg I2C_EVENT_SLAVE_STOP_DETECTED                         : EV4
01015   *     @arg I2C_EVENT_MASTER_MODE_SELECT                          : EV5
01016   *     @arg I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED            : EV6
01017   *     @arg I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED               : EV6
01018   *     @arg I2C_EVENT_MASTER_BYTE_RECEIVED                        : EV7
01019   *     @arg I2C_EVENT_MASTER_BYTE_TRANSMITTING                    : EV8
01020   *     @arg I2C_EVENT_MASTER_BYTE_TRANSMITTED                     : EV8_2
01021   *     @arg I2C_EVENT_MASTER_MODE_ADDRESS10                       : EV9
01022   *
01023   * @note: For detailed description of Events, please refer to section
01024   *    I2C_Events in stm32f10x_i2c.h file.
01025   *
01026   * @retval An ErrorStatus enumeration value:
01027   * - SUCCESS: Last event is equal to the I2C_EVENT
01028   * - ERROR: Last event is different from the I2C_EVENT
01029   */
01030 ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT)
01031 {
01032   uint32_t lastevent = 0;
01033   uint32_t flag1 = 0, flag2 = 0;
01034   ErrorStatus status = ERROR;
01035
01036   /* Check the parameters */
01037   assert_param(IS_I2C_ALL_PERIPH(I2Cx));
01038   assert_param(IS_I2C_EVENT(I2C_EVENT));
01039
01040   /* Read the I2Cx status register */
01041   flag1 = I2Cx->SR1;
01042   flag2 = I2Cx->SR2;
01043   flag2 = flag2 << 16;
01044
01045   /* Get the last event value from I2C status register */
01046   lastevent = (flag1 | flag2) & FLAG_Mask;
01047
01048   /* Check whether the last event contains the I2C_EVENT */
01049   if ((lastevent & I2C_EVENT) == I2C_EVENT)
01050   {
01051     /* SUCCESS: last event is equal to I2C_EVENT */
01052     status = SUCCESS;
01053   }
01054   else
01055   {
01056     /* ERROR: last event is different from I2C_EVENT */
01057     status = ERROR;
01058   }
01059   /* Return status */
01060   return status;
01061 }
01062
01063 /**
01064  *
01065  *  2) Advanced state monitoring
01066  *******************************************************************************
01067  */
01068
01069 /**
01070   * @brief  Returns the last I2Cx Event.
01071   * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
01072   *
01073   * @note: For detailed description of Events, please refer to section
01074   *    I2C_Events in stm32f10x_i2c.h file.
01075   *
01076   * @retval The last event
01077   */
01078 uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx)
01079 {
01080   uint32_t lastevent = 0;
01081   uint32_t flag1 = 0, flag2 = 0;
01082
01083   /* Check the parameters */
01084   assert_param(IS_I2C_ALL_PERIPH(I2Cx));
01085
01086   /* Read the I2Cx status register */
01087   flag1 = I2Cx->SR1;
01088   flag2 = I2Cx->SR2;
01089   flag2 = flag2 << 16;
01090
01091   /* Get the last event value from I2C status register */
01092   lastevent = (flag1 | flag2) & FLAG_Mask;
01093
01094   /* Return status */
01095   return lastevent;
01096 }
01097
01098 /**
01099  *
01100  *  3) Flag-based state monitoring
01101  *******************************************************************************
01102  */
01103
01104 /**
01105   * @brief  Checks whether the specified I2C flag is set or not.
01106   * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
01107   * @param  I2C_FLAG: specifies the flag to check.
01108   *   This parameter can be one of the following values:
01109   *     @arg I2C_FLAG_DUALF: Dual flag (Slave mode)
01110   *     @arg I2C_FLAG_SMBHOST: SMBus host header (Slave mode)
01111   *     @arg I2C_FLAG_SMBDEFAULT: SMBus default header (Slave mode)
01112   *     @arg I2C_FLAG_GENCALL: General call header flag (Slave mode)
01113   *     @arg I2C_FLAG_TRA: Transmitter/Receiver flag
01114   *     @arg I2C_FLAG_BUSY: Bus busy flag
01115   *     @arg I2C_FLAG_MSL: Master/Slave flag
01116   *     @arg I2C_FLAG_SMBALERT: SMBus Alert flag
01117   *     @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
01118   *     @arg I2C_FLAG_PECERR: PEC error in reception flag
01119   *     @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
01120   *     @arg I2C_FLAG_AF: Acknowledge failure flag
01121   *     @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
01122   *     @arg I2C_FLAG_BERR: Bus error flag
01123   *     @arg I2C_FLAG_TXE: Data register empty flag (Transmitter)
01124   *     @arg I2C_FLAG_RXNE: Data register not empty (Receiver) flag
01125   *     @arg I2C_FLAG_STOPF: Stop detection flag (Slave mode)
01126   *     @arg I2C_FLAG_ADD10: 10-bit header sent flag (Master mode)
01127   *     @arg I2C_FLAG_BTF: Byte transfer finished flag
01128   *     @arg I2C_FLAG_ADDR: Address sent flag (Master mode) "ADSL"
01129   *   Address matched flag (Slave mode)"ENDA"
01130   *     @arg I2C_FLAG_SB: Start bit flag (Master mode)
01131   * @retval The new state of I2C_FLAG (SET or RESET).
01132   */
01133 FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)
01134 {
01135   FlagStatus bitstatus = RESET;
01136   __IO uint32_t i2creg = 0, i2cxbase = 0;
01137
01138   /* Check the parameters */
01139   assert_param(IS_I2C_ALL_PERIPH(I2Cx));
01140   assert_param(IS_I2C_GET_FLAG(I2C_FLAG));
01141
01142   /* Get the I2Cx peripheral base address */
01143   i2cxbase = (uint32_t)I2Cx;
01144
01145   /* Read flag register index */
01146   i2creg = I2C_FLAG >> 28;
01147
01148   /* Get bit[23:0] of the flag */
01149   I2C_FLAG &= FLAG_Mask;
01150
01151   if(i2creg != 0)
01152   {
01153     /* Get the I2Cx SR1 register address */
01154     i2cxbase += 0x14;
01155   }
01156   else
01157   {
01158     /* Flag in I2Cx SR2 Register */
01159     I2C_FLAG = (uint32_t)(I2C_FLAG >> 16);
01160     /* Get the I2Cx SR2 register address */
01161     i2cxbase += 0x18;
01162   }
01163
01164   if(((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET)
01165   {
01166     /* I2C_FLAG is set */
01167     bitstatus = SET;
01168   }
01169   else
01170   {
01171     /* I2C_FLAG is reset */
01172     bitstatus = RESET;
01173   }
01174
01175   /* Return the I2C_FLAG status */
01176   return  bitstatus;
01177 }
01178
01179
01180
01181 /**
01182   * @brief  Clears the I2Cx's pending flags.
01183   * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
01184   * @param  I2C_FLAG: specifies the flag to clear.
01185   *   This parameter can be any combination of the following values:
01186   *     @arg I2C_FLAG_SMBALERT: SMBus Alert flag
01187   *     @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
01188   *     @arg I2C_FLAG_PECERR: PEC error in reception flag
01189   *     @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
01190   *     @arg I2C_FLAG_AF: Acknowledge failure flag
01191   *     @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
01192   *     @arg I2C_FLAG_BERR: Bus error flag
01193   *
01194   * @note
01195   *   - STOPF (STOP detection) is cleared by software sequence: a read operation
01196   *     to I2C_SR1 register (I2C_GetFlagStatus()) followed by a write operation
01197   *     to I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral).
01198   *   - ADD10 (10-bit header sent) is cleared by software sequence: a read
01199   *     operation to I2C_SR1 (I2C_GetFlagStatus()) followed by writing the
01200   *     second byte of the address in DR register.
01201   *   - BTF (Byte Transfer Finished) is cleared by software sequence: a read
01202   *     operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a
01203   *     read/write to I2C_DR register (I2C_SendData()).
01204   *   - ADDR (Address sent) is cleared by software sequence: a read operation to
01205   *     I2C_SR1 register (I2C_GetFlagStatus()) followed by a read operation to
01206   *     I2C_SR2 register ((void)(I2Cx->SR2)).
01207   *   - SB (Start Bit) is cleared software sequence: a read operation to I2C_SR1
01208   *     register (I2C_GetFlagStatus()) followed by a write operation to I2C_DR
01209   *     register  (I2C_SendData()).
01210   * @retval None
01211   */
01212 void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)
01213 {
01214   uint32_t flagpos = 0;
01215   /* Check the parameters */
01216   assert_param(IS_I2C_ALL_PERIPH(I2Cx));
01217   assert_param(IS_I2C_CLEAR_FLAG(I2C_FLAG));
01218   /* Get the I2C flag position */
01219   flagpos = I2C_FLAG & FLAG_Mask;
01220   /* Clear the selected I2C flag */
01221   I2Cx->SR1 = (uint16_t)~flagpos;
01222 }
01223
01224 /**
01225   * @brief  Checks whether the specified I2C interrupt has occurred or not.
01226   * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
01227   * @param  I2C_IT: specifies the interrupt source to check.
01228   *   This parameter can be one of the following values:
01229   *     @arg I2C_IT_SMBALERT: SMBus Alert flag
01230   *     @arg I2C_IT_TIMEOUT: Timeout or Tlow error flag
01231   *     @arg I2C_IT_PECERR: PEC error in reception flag
01232   *     @arg I2C_IT_OVR: Overrun/Underrun flag (Slave mode)
01233   *     @arg I2C_IT_AF: Acknowledge failure flag
01234   *     @arg I2C_IT_ARLO: Arbitration lost flag (Master mode)
01235   *     @arg I2C_IT_BERR: Bus error flag
01236   *     @arg I2C_IT_TXE: Data register empty flag (Transmitter)
01237   *     @arg I2C_IT_RXNE: Data register not empty (Receiver) flag
01238   *     @arg I2C_IT_STOPF: Stop detection flag (Slave mode)
01239   *     @arg I2C_IT_ADD10: 10-bit header sent flag (Master mode)
01240   *     @arg I2C_IT_BTF: Byte transfer finished flag
01241   *     @arg I2C_IT_ADDR: Address sent flag (Master mode) "ADSL"
01242   *                       Address matched flag (Slave mode)"ENDAD"
01243   *     @arg I2C_IT_SB: Start bit flag (Master mode)
01244   * @retval The new state of I2C_IT (SET or RESET).
01245   */
01246 ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT)
01247 {
01248   ITStatus bitstatus = RESET;
01249   uint32_t enablestatus = 0;
01250
01251   /* Check the parameters */
01252   assert_param(IS_I2C_ALL_PERIPH(I2Cx));
01253   assert_param(IS_I2C_GET_IT(I2C_IT));
01254
01255   /* Check if the interrupt source is enabled or not */
01256   enablestatus = (uint32_t)(((I2C_IT & ITEN_Mask) >> 16) & (I2Cx->CR2)) ;
01257
01258   /* Get bit[23:0] of the flag */
01259   I2C_IT &= FLAG_Mask;
01260
01261   /* Check the status of the specified I2C flag */
01262   if (((I2Cx->SR1 & I2C_IT) != (uint32_t)RESET) && enablestatus)
01263   {
01264     /* I2C_IT is set */
01265     bitstatus = SET;
01266   }
01267   else
01268   {
01269     /* I2C_IT is reset */
01270     bitstatus = RESET;
01271   }
01272   /* Return the I2C_IT status */
01273   return  bitstatus;
01274 }
01275
01276 /**
01277   * @brief  Clears the I2Cx’s interrupt pending bits.
01278   * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
01279   * @param  I2C_IT: specifies the interrupt pending bit to clear.
01280   *   This parameter can be any combination of the following values:
01281   *     @arg I2C_IT_SMBALERT: SMBus Alert interrupt
01282   *     @arg I2C_IT_TIMEOUT: Timeout or Tlow error interrupt
01283   *     @arg I2C_IT_PECERR: PEC error in reception  interrupt
01284   *     @arg I2C_IT_OVR: Overrun/Underrun interrupt (Slave mode)
01285   *     @arg I2C_IT_AF: Acknowledge failure interrupt
01286   *     @arg I2C_IT_ARLO: Arbitration lost interrupt (Master mode)
01287   *     @arg I2C_IT_BERR: Bus error interrupt
01288   *
01289   * @note
01290   *   - STOPF (STOP detection) is cleared by software sequence: a read operation
01291   *     to I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to
01292   *     I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral).
01293   *   - ADD10 (10-bit header sent) is cleared by software sequence: a read
01294   *     operation to I2C_SR1 (I2C_GetITStatus()) followed by writing the second
01295   *     byte of the address in I2C_DR register.
01296   *   - BTF (Byte Transfer Finished) is cleared by software sequence: a read
01297   *     operation to I2C_SR1 register (I2C_GetITStatus()) followed by a
01298   *     read/write to I2C_DR register (I2C_SendData()).
01299   *   - ADDR (Address sent) is cleared by software sequence: a read operation to
01300   *     I2C_SR1 register (I2C_GetITStatus()) followed by a read operation to
01301   *     I2C_SR2 register ((void)(I2Cx->SR2)).
01302   *   - SB (Start Bit) is cleared by software sequence: a read operation to
01303   *     I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to
01304   *     I2C_DR register (I2C_SendData()).
01305   * @retval None
01306   */
01307 void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT)
01308 {
01309   uint32_t flagpos = 0;
01310   /* Check the parameters */
01311   assert_param(IS_I2C_ALL_PERIPH(I2Cx));
01312   assert_param(IS_I2C_CLEAR_IT(I2C_IT));
01313   /* Get the I2C flag position */
01314   flagpos = I2C_IT & FLAG_Mask;
01315   /* Clear the selected I2C flag */
01316   I2Cx->SR1 = (uint16_t)~flagpos;
01317 }
01318
01319 /**
01320   * @}
01321   */
01322
01323 /**
01324   * @}
01325   */
01326
01327 /**
01328   * @}
01329   */
01330
01331 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_i2c.h Source File

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stm32f10x_i2c.h

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f10x_i2c.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    11-March-2011
00007   * @brief   This file contains all the functions prototypes for the I2C firmware
00008   *          library.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00013   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00014   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00015   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00016   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00017   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00018   *
00019   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00020   ******************************************************************************
00021   */
00022
00023 /* Define to prevent recursive inclusion -------------------------------------*/
00024 #ifndef __STM32F10x_I2C_H
00025 #define __STM32F10x_I2C_H
00026
00027 #ifdef __cplusplus
00028  extern "C" {
00029 #endif
00030
00031 /* Includes ------------------------------------------------------------------*/
00032 #include "stm32f10x.h"
00033
00034 /** @addtogroup STM32F10x_StdPeriph_Driver
00035   * @{
00036   */
00037
00038 /** @addtogroup I2C
00039   * @{
00040   */
00041
00042 /** @defgroup I2C_Exported_Types
00043   * @{
00044   */
00045
00046 /**
00047   * @brief  I2C Init structure definition
00048   */
00049
00050 typedef struct
00051 {
00052   uint32_t I2C_ClockSpeed;          /*!< Specifies the clock frequency.
00053                                          This parameter must be set to a value lower than 400kHz */
00054
00055   uint16_t I2C_Mode;                /*!< Specifies the I2C mode.
00056                                          This parameter can be a value of @ref I2C_mode */
00057
00058   uint16_t I2C_DutyCycle;           /*!< Specifies the I2C fast mode duty cycle.
00059                                          This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
00060
00061   uint16_t I2C_OwnAddress1;         /*!< Specifies the first device own address.
00062                                          This parameter can be a 7-bit or 10-bit address. */
00063
00064   uint16_t I2C_Ack;                 /*!< Enables or disables the acknowledgement.
00065                                          This parameter can be a value of @ref I2C_acknowledgement */
00066
00067   uint16_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged.
00068                                          This parameter can be a value of @ref I2C_acknowledged_address */
00069 }I2C_InitTypeDef;
00070
00071 /**
00072   * @}
00073   */
00074
00075
00076 /** @defgroup I2C_Exported_Constants
00077   * @{
00078   */
00079
00080 #define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \
00081                                    ((PERIPH) == I2C2))
00082 /** @defgroup I2C_mode
00083   * @{
00084   */
00085
00086 #define I2C_Mode_I2C                    ((uint16_t)0x0000)
00087 #define I2C_Mode_SMBusDevice            ((uint16_t)0x0002)
00088 #define I2C_Mode_SMBusHost              ((uint16_t)0x000A)
00089 #define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \
00090                            ((MODE) == I2C_Mode_SMBusDevice) || \
00091                            ((MODE) == I2C_Mode_SMBusHost))
00092 /**
00093   * @}
00094   */
00095
00096 /** @defgroup I2C_duty_cycle_in_fast_mode
00097   * @{
00098   */
00099
00100 #define I2C_DutyCycle_16_9              ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */
00101 #define I2C_DutyCycle_2                 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */
00102 #define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \
00103                                   ((CYCLE) == I2C_DutyCycle_2))
00104 /**
00105   * @}
00106   */
00107
00108 /** @defgroup I2C_acknowledgement
00109   * @{
00110   */
00111
00112 #define I2C_Ack_Enable                  ((uint16_t)0x0400)
00113 #define I2C_Ack_Disable                 ((uint16_t)0x0000)
00114 #define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \
00115                                  ((STATE) == I2C_Ack_Disable))
00116 /**
00117   * @}
00118   */
00119
00120 /** @defgroup I2C_transfer_direction
00121   * @{
00122   */
00123
00124 #define  I2C_Direction_Transmitter      ((uint8_t)0x00)
00125 #define  I2C_Direction_Receiver         ((uint8_t)0x01)
00126 #define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \
00127                                      ((DIRECTION) == I2C_Direction_Receiver))
00128 /**
00129   * @}
00130   */
00131
00132 /** @defgroup I2C_acknowledged_address
00133   * @{
00134   */
00135
00136 #define I2C_AcknowledgedAddress_7bit    ((uint16_t)0x4000)
00137 #define I2C_AcknowledgedAddress_10bit   ((uint16_t)0xC000)
00138 #define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \
00139                                              ((ADDRESS) == I2C_AcknowledgedAddress_10bit))
00140 /**
00141   * @}
00142   */
00143
00144 /** @defgroup I2C_registers
00145   * @{
00146   */
00147
00148 #define I2C_Register_CR1                ((uint8_t)0x00)
00149 #define I2C_Register_CR2                ((uint8_t)0x04)
00150 #define I2C_Register_OAR1               ((uint8_t)0x08)
00151 #define I2C_Register_OAR2               ((uint8_t)0x0C)
00152 #define I2C_Register_DR                 ((uint8_t)0x10)
00153 #define I2C_Register_SR1                ((uint8_t)0x14)
00154 #define I2C_Register_SR2                ((uint8_t)0x18)
00155 #define I2C_Register_CCR                ((uint8_t)0x1C)
00156 #define I2C_Register_TRISE              ((uint8_t)0x20)
00157 #define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \
00158                                    ((REGISTER) == I2C_Register_CR2) || \
00159                                    ((REGISTER) == I2C_Register_OAR1) || \
00160                                    ((REGISTER) == I2C_Register_OAR2) || \
00161                                    ((REGISTER) == I2C_Register_DR) || \
00162                                    ((REGISTER) == I2C_Register_SR1) || \
00163                                    ((REGISTER) == I2C_Register_SR2) || \
00164                                    ((REGISTER) == I2C_Register_CCR) || \
00165                                    ((REGISTER) == I2C_Register_TRISE))
00166 /**
00167   * @}
00168   */
00169
00170 /** @defgroup I2C_SMBus_alert_pin_level
00171   * @{
00172   */
00173
00174 #define I2C_SMBusAlert_Low              ((uint16_t)0x2000)
00175 #define I2C_SMBusAlert_High             ((uint16_t)0xDFFF)
00176 #define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \
00177                                    ((ALERT) == I2C_SMBusAlert_High))
00178 /**
00179   * @}
00180   */
00181
00182 /** @defgroup I2C_PEC_position
00183   * @{
00184   */
00185
00186 #define I2C_PECPosition_Next            ((uint16_t)0x0800)
00187 #define I2C_PECPosition_Current         ((uint16_t)0xF7FF)
00188 #define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \
00189                                        ((POSITION) == I2C_PECPosition_Current))
00190 /**
00191   * @}
00192   */
00193
00194 /** @defgroup I2C_NCAK_position
00195   * @{
00196   */
00197
00198 #define I2C_NACKPosition_Next           ((uint16_t)0x0800)
00199 #define I2C_NACKPosition_Current        ((uint16_t)0xF7FF)
00200 #define IS_I2C_NACK_POSITION(POSITION)  (((POSITION) == I2C_NACKPosition_Next) || \
00201                                          ((POSITION) == I2C_NACKPosition_Current))
00202 /**
00203   * @}
00204   */
00205
00206 /** @defgroup I2C_interrupts_definition
00207   * @{
00208   */
00209
00210 #define I2C_IT_BUF                      ((uint16_t)0x0400)
00211 #define I2C_IT_EVT                      ((uint16_t)0x0200)
00212 #define I2C_IT_ERR                      ((uint16_t)0x0100)
00213 #define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00))
00214 /**
00215   * @}
00216   */
00217
00218 /** @defgroup I2C_interrupts_definition
00219   * @{
00220   */
00221
00222 #define I2C_IT_SMBALERT                 ((uint32_t)0x01008000)
00223 #define I2C_IT_TIMEOUT                  ((uint32_t)0x01004000)
00224 #define I2C_IT_PECERR                   ((uint32_t)0x01001000)
00225 #define I2C_IT_OVR                      ((uint32_t)0x01000800)
00226 #define I2C_IT_AF                       ((uint32_t)0x01000400)
00227 #define I2C_IT_ARLO                     ((uint32_t)0x01000200)
00228 #define I2C_IT_BERR                     ((uint32_t)0x01000100)
00229 #define I2C_IT_TXE                      ((uint32_t)0x06000080)
00230 #define I2C_IT_RXNE                     ((uint32_t)0x06000040)
00231 #define I2C_IT_STOPF                    ((uint32_t)0x02000010)
00232 #define I2C_IT_ADD10                    ((uint32_t)0x02000008)
00233 #define I2C_IT_BTF                      ((uint32_t)0x02000004)
00234 #define I2C_IT_ADDR                     ((uint32_t)0x02000002)
00235 #define I2C_IT_SB                       ((uint32_t)0x02000001)
00236
00237 #define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00))
00238
00239 #define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \
00240                            ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \
00241                            ((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \
00242                            ((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \
00243                            ((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \
00244                            ((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \
00245                            ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB))
00246 /**
00247   * @}
00248   */
00249
00250 /** @defgroup I2C_flags_definition
00251   * @{
00252   */
00253
00254 /**
00255   * @brief  SR2 register flags
00256   */
00257
00258 #define I2C_FLAG_DUALF                  ((uint32_t)0x00800000)
00259 #define I2C_FLAG_SMBHOST                ((uint32_t)0x00400000)
00260 #define I2C_FLAG_SMBDEFAULT             ((uint32_t)0x00200000)
00261 #define I2C_FLAG_GENCALL                ((uint32_t)0x00100000)
00262 #define I2C_FLAG_TRA                    ((uint32_t)0x00040000)
00263 #define I2C_FLAG_BUSY                   ((uint32_t)0x00020000)
00264 #define I2C_FLAG_MSL                    ((uint32_t)0x00010000)
00265
00266 /**
00267   * @brief  SR1 register flags
00268   */
00269
00270 #define I2C_FLAG_SMBALERT               ((uint32_t)0x10008000)
00271 #define I2C_FLAG_TIMEOUT                ((uint32_t)0x10004000)
00272 #define I2C_FLAG_PECERR                 ((uint32_t)0x10001000)
00273 #define I2C_FLAG_OVR                    ((uint32_t)0x10000800)
00274 #define I2C_FLAG_AF                     ((uint32_t)0x10000400)
00275 #define I2C_FLAG_ARLO                   ((uint32_t)0x10000200)
00276 #define I2C_FLAG_BERR                   ((uint32_t)0x10000100)
00277 #define I2C_FLAG_TXE                    ((uint32_t)0x10000080)
00278 #define I2C_FLAG_RXNE                   ((uint32_t)0x10000040)
00279 #define I2C_FLAG_STOPF                  ((uint32_t)0x10000010)
00280 #define I2C_FLAG_ADD10                  ((uint32_t)0x10000008)
00281 #define I2C_FLAG_BTF                    ((uint32_t)0x10000004)
00282 #define I2C_FLAG_ADDR                   ((uint32_t)0x10000002)
00283 #define I2C_FLAG_SB                     ((uint32_t)0x10000001)
00284
00285 #define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00))
00286
00287 #define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \
00288                                ((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \
00289                                ((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \
00290                                ((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \
00291                                ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \
00292                                ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \
00293                                ((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \
00294                                ((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \
00295                                ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \
00296                                ((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \
00297                                ((FLAG) == I2C_FLAG_SB))
00298 /**
00299   * @}
00300   */
00301
00302 /** @defgroup I2C_Events
00303   * @{
00304   */
00305
00306 /*========================================
00307
00308                      I2C Master Events (Events grouped in order of communication)
00309                                                         ==========================================*/
00310 /**
00311   * @brief  Communication start
00312   *
00313   * After sending the START condition (I2C_GenerateSTART() function) the master
00314   * has to wait for this event. It means that the Start condition has been correctly
00315   * released on the I2C bus (the bus is free, no other devices is communicating).
00316   *
00317   */
00318 /* --EV5 */
00319 #define  I2C_EVENT_MASTER_MODE_SELECT                      ((uint32_t)0x00030001)  /* BUSY, MSL and SB flag */
00320
00321 /**
00322   * @brief  Address Acknowledge
00323   *
00324   * After checking on EV5 (start condition correctly released on the bus), the
00325   * master sends the address of the slave(s) with which it will communicate
00326   * (I2C_Send7bitAddress() function, it also determines the direction of the communication:
00327   * Master transmitter or Receiver). Then the master has to wait that a slave acknowledges
00328   * his address. If an acknowledge is sent on the bus, one of the following events will
00329   * be set:
00330   *
00331   *  1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED
00332   *     event is set.
00333   *
00334   *  2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED
00335   *     is set
00336   *
00337   *  3) In case of 10-Bit addressing mode, the master (just after generating the START
00338   *  and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData()
00339   *  function). Then master should wait on EV9. It means that the 10-bit addressing
00340   *  header has been correctly sent on the bus. Then master should send the second part of
00341   *  the 10-bit address (LSB) using the function I2C_Send7bitAddress(). Then master
00342   *  should wait for event EV6.
00343   *
00344   */
00345
00346 /* --EV6 */
00347 #define  I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED        ((uint32_t)0x00070082)  /* BUSY, MSL, ADDR, TXE and TRA flags */
00348 #define  I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED           ((uint32_t)0x00030002)  /* BUSY, MSL and ADDR flags */
00349 /* --EV9 */
00350 #define  I2C_EVENT_MASTER_MODE_ADDRESS10                   ((uint32_t)0x00030008)  /* BUSY, MSL and ADD10 flags */
00351
00352 /**
00353   * @brief Communication events
00354   *
00355   * If a communication is established (START condition generated and slave address
00356   * acknowledged) then the master has to check on one of the following events for
00357   * communication procedures:
00358   *
00359   * 1) Master Receiver mode: The master has to wait on the event EV7 then to read
00360   *    the data received from the slave (I2C_ReceiveData() function).
00361   *
00362   * 2) Master Transmitter mode: The master has to send data (I2C_SendData()
00363   *    function) then to wait on event EV8 or EV8_2.
00364   *    These two events are similar:
00365   *     - EV8 means that the data has been written in the data register and is
00366   *       being shifted out.
00367   *     - EV8_2 means that the data has been physically shifted out and output
00368   *       on the bus.
00369   *     In most cases, using EV8 is sufficient for the application.
00370   *     Using EV8_2 leads to a slower communication but ensure more reliable test.
00371   *     EV8_2 is also more suitable than EV8 for testing on the last data transmission
00372   *     (before Stop condition generation).
00373   *
00374   *  @note In case the  user software does not guarantee that this event EV7 is
00375   *  managed before the current byte end of transfer, then user may check on EV7
00376   *  and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)).
00377   *  In this case the communication may be slower.
00378   *
00379   */
00380
00381 /* Master RECEIVER mode -----------------------------*/
00382 /* --EV7 */
00383 #define  I2C_EVENT_MASTER_BYTE_RECEIVED                    ((uint32_t)0x00030040)  /* BUSY, MSL and RXNE flags */
00384
00385 /* Master TRANSMITTER mode --------------------------*/
00386 /* --EV8 */
00387 #define I2C_EVENT_MASTER_BYTE_TRANSMITTING                 ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */
00388 /* --EV8_2 */
00389 #define  I2C_EVENT_MASTER_BYTE_TRANSMITTED                 ((uint32_t)0x00070084)  /* TRA, BUSY, MSL, TXE and BTF flags */
00390
00391
00392 /*========================================
00393
00394                      I2C Slave Events (Events grouped in order of communication)
00395                                                         ==========================================*/
00396
00397 /**
00398   * @brief  Communication start events
00399   *
00400   * Wait on one of these events at the start of the communication. It means that
00401   * the I2C peripheral detected a Start condition on the bus (generated by master
00402   * device) followed by the peripheral address. The peripheral generates an ACK
00403   * condition on the bus (if the acknowledge feature is enabled through function
00404   * I2C_AcknowledgeConfig()) and the events listed above are set :
00405   *
00406   * 1) In normal case (only one address managed by the slave), when the address
00407   *   sent by the master matches the own address of the peripheral (configured by
00408   *   I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set
00409   *   (where XXX could be TRANSMITTER or RECEIVER).
00410   *
00411   * 2) In case the address sent by the master matches the second address of the
00412   *   peripheral (configured by the function I2C_OwnAddress2Config() and enabled
00413   *   by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED
00414   *   (where XXX could be TRANSMITTER or RECEIVER) are set.
00415   *
00416   * 3) In case the address sent by the master is General Call (address 0x00) and
00417   *   if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd())
00418   *   the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED.
00419   *
00420   */
00421
00422 /* --EV1  (all the events below are variants of EV1) */
00423 /* 1) Case of One Single Address managed by the slave */
00424 #define  I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED          ((uint32_t)0x00020002) /* BUSY and ADDR flags */
00425 #define  I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED       ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */
00426
00427 /* 2) Case of Dual address managed by the slave */
00428 #define  I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED    ((uint32_t)0x00820000)  /* DUALF and BUSY flags */
00429 #define  I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080)  /* DUALF, TRA, BUSY and TXE flags */
00430
00431 /* 3) Case of General Call enabled for the slave */
00432 #define  I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED        ((uint32_t)0x00120000)  /* GENCALL and BUSY flags */
00433
00434 /**
00435   * @brief  Communication events
00436   *
00437   * Wait on one of these events when EV1 has already been checked and:
00438   *
00439   * - Slave RECEIVER mode:
00440   *     - EV2: When the application is expecting a data byte to be received.
00441   *     - EV4: When the application is expecting the end of the communication: master
00442   *       sends a stop condition and data transmission is stopped.
00443   *
00444   * - Slave Transmitter mode:
00445   *    - EV3: When a byte has been transmitted by the slave and the application is expecting
00446   *      the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and
00447   *      I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. The second one can optionally be
00448   *      used when the user software doesn't guarantee the EV3 is managed before the
00449   *      current byte end of transfer.
00450   *    - EV3_2: When the master sends a NACK in order to tell slave that data transmission
00451   *      shall end (before sending the STOP condition). In this case slave has to stop sending
00452   *      data bytes and expect a Stop condition on the bus.
00453   *
00454   *  @note In case the  user software does not guarantee that the event EV2 is
00455   *  managed before the current byte end of transfer, then user may check on EV2
00456   *  and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)).
00457   * In this case the communication may be slower.
00458   *
00459   */
00460
00461 /* Slave RECEIVER mode --------------------------*/
00462 /* --EV2 */
00463 #define  I2C_EVENT_SLAVE_BYTE_RECEIVED                     ((uint32_t)0x00020040)  /* BUSY and RXNE flags */
00464 /* --EV4  */
00465 #define  I2C_EVENT_SLAVE_STOP_DETECTED                     ((uint32_t)0x00000010)  /* STOPF flag */
00466
00467 /* Slave TRANSMITTER mode -----------------------*/
00468 /* --EV3 */
00469 #define  I2C_EVENT_SLAVE_BYTE_TRANSMITTED                  ((uint32_t)0x00060084)  /* TRA, BUSY, TXE and BTF flags */
00470 #define  I2C_EVENT_SLAVE_BYTE_TRANSMITTING                 ((uint32_t)0x00060080)  /* TRA, BUSY and TXE flags */
00471 /* --EV3_2 */
00472 #define  I2C_EVENT_SLAVE_ACK_FAILURE                       ((uint32_t)0x00000400)  /* AF flag */
00473
00474 /*===========================      End of Events Description           ==========================================*/
00475
00476 #define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \
00477                              ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \
00478                              ((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \
00479                              ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \
00480                              ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \
00481                              ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \
00482                              ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \
00483                              ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \
00484                              ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \
00485                              ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \
00486                              ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \
00487                              ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \
00488                              ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \
00489                              ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \
00490                              ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \
00491                              ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \
00492                              ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \
00493                              ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \
00494                              ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \
00495                              ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE))
00496 /**
00497   * @}
00498   */
00499
00500 /** @defgroup I2C_own_address1
00501   * @{
00502   */
00503
00504 #define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF)
00505 /**
00506   * @}
00507   */
00508
00509 /** @defgroup I2C_clock_speed
00510   * @{
00511   */
00512
00513 #define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000))
00514 /**
00515   * @}
00516   */
00517
00518 /**
00519   * @}
00520   */
00521
00522 /** @defgroup I2C_Exported_Macros
00523   * @{
00524   */
00525
00526 /**
00527   * @}
00528   */
00529
00530 /** @defgroup I2C_Exported_Functions
00531   * @{
00532   */
00533
00534 void I2C_DeInit(I2C_TypeDef* I2Cx);
00535 void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);
00536 void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);
00537 void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
00538 void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
00539 void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
00540 void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);
00541 void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);
00542 void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState);
00543 void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address);
00544 void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
00545 void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
00546 void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState);
00547 void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data);
00548 uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx);
00549 void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction);
00550 uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register);
00551 void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
00552 void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition);
00553 void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert);
00554 void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
00555 void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition);
00556 void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
00557 uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx);
00558 void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
00559 void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
00560 void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle);
00561
00562 /**
00563  * @brief
00564  ****************************************************************************************
00565  *
00566  *                         I2C State Monitoring Functions
00567  *
00568  ****************************************************************************************
00569  * This I2C driver provides three different ways for I2C state monitoring
00570  *  depending on the application requirements and constraints:
00571  *
00572  *
00573  * 1) Basic state monitoring:
00574  *    Using I2C_CheckEvent() function:
00575  *    It compares the status registers (SR1 and SR2) content to a given event
00576  *    (can be the combination of one or more flags).
00577  *    It returns SUCCESS if the current status includes the given flags
00578  *    and returns ERROR if one or more flags are missing in the current status.
00579  *    - When to use:
00580  *      - This function is suitable for most applications as well as for startup
00581  *      activity since the events are fully described in the product reference manual
00582  *      (RM0008).
00583  *      - It is also suitable for users who need to define their own events.
00584  *    - Limitations:
00585  *      - If an error occurs (ie. error flags are set besides to the monitored flags),
00586  *        the I2C_CheckEvent() function may return SUCCESS despite the communication
00587  *        hold or corrupted real state.
00588  *        In this case, it is advised to use error interrupts to monitor the error
00589  *        events and handle them in the interrupt IRQ handler.
00590  *
00591  *        @note
00592  *        For error management, it is advised to use the following functions:
00593  *          - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).
00594  *          - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs.
00595  *            Where x is the peripheral instance (I2C1, I2C2 ...)
00596  *          - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into I2Cx_ER_IRQHandler()
00597  *            in order to determine which error occurred.
00598  *          - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd()
00599  *            and/or I2C_GenerateStop() in order to clear the error flag and source,
00600  *            and return to correct communication status.
00601  *
00602  *
00603  *  2) Advanced state monitoring:
00604  *     Using the function I2C_GetLastEvent() which returns the image of both status
00605  *     registers in a single word (uint32_t) (Status Register 2 value is shifted left
00606  *     by 16 bits and concatenated to Status Register 1).
00607  *     - When to use:
00608  *       - This function is suitable for the same applications above but it allows to
00609  *         overcome the limitations of I2C_GetFlagStatus() function (see below).
00610  *         The returned value could be compared to events already defined in the
00611  *         library (stm32f10x_i2c.h) or to custom values defined by user.
00612  *       - This function is suitable when multiple flags are monitored at the same time.
00613  *       - At the opposite of I2C_CheckEvent() function, this function allows user to
00614  *         choose when an event is accepted (when all events flags are set and no
00615  *         other flags are set or just when the needed flags are set like
00616  *         I2C_CheckEvent() function).
00617  *     - Limitations:
00618  *       - User may need to define his own events.
00619  *       - Same remark concerning the error management is applicable for this
00620  *         function if user decides to check only regular communication flags (and
00621  *         ignores error flags).
00622  *
00623  *
00624  *  3) Flag-based state monitoring:
00625  *     Using the function I2C_GetFlagStatus() which simply returns the status of
00626  *     one single flag (ie. I2C_FLAG_RXNE ...).
00627  *     - When to use:
00628  *        - This function could be used for specific applications or in debug phase.
00629  *        - It is suitable when only one flag checking is needed (most I2C events
00630  *          are monitored through multiple flags).
00631  *     - Limitations:
00632  *        - When calling this function, the Status register is accessed. Some flags are
00633  *          cleared when the status register is accessed. So checking the status
00634  *          of one Flag, may clear other ones.
00635  *        - Function may need to be called twice or more in order to monitor one
00636  *          single event.
00637  *
00638  */
00639
00640 /**
00641  *
00642  *  1) Basic state monitoring
00643  *******************************************************************************
00644  */
00645 ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT);
00646 /**
00647  *
00648  *  2) Advanced state monitoring
00649  *******************************************************************************
00650  */
00651 uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx);
00652 /**
00653  *
00654  *  3) Flag-based state monitoring
00655  *******************************************************************************
00656  */
00657 FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
00658 /**
00659  *
00660  *******************************************************************************
00661  */
00662
00663 void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
00664 ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
00665 void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
00666
00667 #ifdef __cplusplus
00668 }
00669 #endif
00670
00671 #endif /*__STM32F10x_I2C_H */
00672 /**
00673   * @}
00674   */
00675
00676 /**
00677   * @}
00678   */
00679
00680 /**
00681   * @}
00682   */
00683
00684 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_ip_dbg.c Source File

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  • RunTime_Check

stm32f10x_ip_dbg.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    Lib_DEBUG/RunTime_Check/stm32f10x_ip_dbg.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file provides all peripherals pointers initialization.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x_ip_dbg.h"
00024
00025 /** @addtogroup STM32F10x_StdPeriph_Examples
00026   * @{
00027   */
00028
00029 /** @addtogroup Lib_DEBUG_RunTime_Check
00030   * @{
00031   */
00032
00033 /* Private typedef -----------------------------------------------------------*/
00034 /* Private define ------------------------------------------------------------*/
00035 /* Private macro -------------------------------------------------------------*/
00036 /* Private variables ---------------------------------------------------------*/
00037 TIM_TypeDef             *TIM2_DBG;
00038 TIM_TypeDef             *TIM3_DBG;
00039 TIM_TypeDef             *TIM4_DBG;
00040 TIM_TypeDef             *TIM5_DBG;
00041 TIM_TypeDef             *TIM6_DBG;
00042 TIM_TypeDef             *TIM7_DBG;
00043 RTC_TypeDef             *RTC_DBG;
00044 WWDG_TypeDef            *WWDG_DBG;
00045 IWDG_TypeDef            *IWDG_DBG;
00046 SPI_TypeDef             *SPI2_DBG;
00047 SPI_TypeDef             *SPI3_DBG;
00048 USART_TypeDef           *USART2_DBG;
00049 USART_TypeDef           *USART3_DBG;
00050 USART_TypeDef           *UART4_DBG;
00051 USART_TypeDef           *UART5_DBG;
00052 I2C_TypeDef             *I2C1_DBG;
00053 I2C_TypeDef             *I2C2_DBG;
00054 CAN_TypeDef             *CAN1_DBG;
00055 BKP_TypeDef             *BKP_DBG;
00056 PWR_TypeDef             *PWR_DBG;
00057 DAC_TypeDef             *DAC_DBG;
00058 CEC_TypeDef             *CEC_DBG;
00059 AFIO_TypeDef            *AFIO_DBG;
00060 EXTI_TypeDef            *EXTI_DBG;
00061 GPIO_TypeDef            *GPIOA_DBG;
00062 GPIO_TypeDef            *GPIOB_DBG;
00063 GPIO_TypeDef            *GPIOC_DBG;
00064 GPIO_TypeDef            *GPIOD_DBG;
00065 GPIO_TypeDef            *GPIOE_DBG;
00066 GPIO_TypeDef            *GPIOF_DBG;
00067 GPIO_TypeDef            *GPIOG_DBG;
00068 ADC_TypeDef             *ADC1_DBG;
00069 ADC_TypeDef             *ADC2_DBG;
00070 TIM_TypeDef             *TIM1_DBG;
00071 SPI_TypeDef             *SPI1_DBG;
00072 TIM_TypeDef             *TIM8_DBG;
00073 USART_TypeDef           *USART1_DBG;
00074 ADC_TypeDef             *ADC3_DBG;
00075 TIM_TypeDef             *TIM15_DBG;
00076 TIM_TypeDef             *TIM16_DBG;
00077 TIM_TypeDef             *TIM17_DBG;
00078 SDIO_TypeDef            *SDIO_DBG;
00079 DMA_TypeDef             *DMA1_DBG;
00080 DMA_TypeDef             *DMA2_DBG;
00081 DMA_Channel_TypeDef     *DMA1_Channel1_DBG;
00082 DMA_Channel_TypeDef     *DMA1_Channel2_DBG;
00083 DMA_Channel_TypeDef     *DMA1_Channel3_DBG;
00084 DMA_Channel_TypeDef     *DMA1_Channel4_DBG;
00085 DMA_Channel_TypeDef     *DMA1_Channel5_DBG;
00086 DMA_Channel_TypeDef     *DMA1_Channel6_DBG;
00087 DMA_Channel_TypeDef     *DMA1_Channel7_DBG;
00088 DMA_Channel_TypeDef     *DMA2_Channel1_DBG;
00089 DMA_Channel_TypeDef     *DMA2_Channel2_DBG;
00090 DMA_Channel_TypeDef     *DMA2_Channel3_DBG;
00091 DMA_Channel_TypeDef     *DMA2_Channel4_DBG;
00092 DMA_Channel_TypeDef     *DMA2_Channel5_DBG;
00093 RCC_TypeDef             *RCC_DBG;
00094 CRC_TypeDef             *CRC_DBG;
00095 FLASH_TypeDef           *FLASH_DBG;
00096 OB_TypeDef              *OB_DBG;
00097 FSMC_Bank1_TypeDef      *FSMC_Bank1_DBG;
00098 FSMC_Bank1E_TypeDef     *FSMC_Bank1E_DBG;
00099 FSMC_Bank2_TypeDef      *FSMC_Bank2_DBG;
00100 FSMC_Bank3_TypeDef      *FSMC_Bank3_DBG;
00101 FSMC_Bank4_TypeDef      *FSMC_Bank4_DBG;
00102 DBGMCU_TypeDef          *DBGMCU_DBG;
00103 SysTick_Type            *SysTick_DBG;
00104 NVIC_Type               *NVIC_DBG;
00105 SCB_Type                *SCB_DBG;
00106
00107 /* Private function prototypes -----------------------------------------------*/
00108 /* Private functions ---------------------------------------------------------*/
00109
00110 /**
00111   * @brief  This function initialize peripherals pointers.
00112   * @param  None
00113   * @retval None
00114   */
00115 void debug(void)
00116 {
00117 /************************************* ADC ************************************/
00118   ADC1_DBG = (ADC_TypeDef *)  ADC1_BASE;
00119
00120   ADC2_DBG = (ADC_TypeDef *)  ADC2_BASE;
00121
00122   ADC3_DBG = (ADC_TypeDef *)  ADC3_BASE;
00123
00124 /************************************* BKP ************************************/
00125   BKP_DBG = (BKP_TypeDef *)  BKP_BASE;
00126
00127 /************************************* CAN ************************************/
00128   CAN1_DBG = (CAN_TypeDef *)  CAN1_BASE;
00129
00130 /************************************* CEC ************************************/
00131   CEC_DBG = (CEC_TypeDef *)  CEC_BASE;
00132
00133 /************************************* CRC ************************************/
00134   CRC_DBG = (CRC_TypeDef *)  CRC_BASE;
00135
00136 /************************************* DAC ************************************/
00137   DAC_DBG = (DAC_TypeDef *)  DAC_BASE;
00138
00139 /************************************* DBGMCU**********************************/
00140   DBGMCU_DBG = (DBGMCU_TypeDef *)  DBGMCU_BASE;
00141
00142
00143 /************************************* DMA ************************************/
00144   DMA1_DBG = (DMA_TypeDef *)  DMA1_BASE;
00145   DMA2_DBG = (DMA_TypeDef *)  DMA2_BASE;
00146
00147   DMA1_Channel1_DBG = (DMA_Channel_TypeDef *)  DMA1_Channel1_BASE;
00148
00149   DMA1_Channel2_DBG = (DMA_Channel_TypeDef *)  DMA1_Channel2_BASE;
00150
00151   DMA1_Channel3_DBG = (DMA_Channel_TypeDef *)  DMA1_Channel3_BASE;
00152
00153   DMA1_Channel4_DBG = (DMA_Channel_TypeDef *)  DMA1_Channel4_BASE;
00154
00155   DMA1_Channel5_DBG = (DMA_Channel_TypeDef *)  DMA1_Channel5_BASE;
00156
00157   DMA1_Channel6_DBG = (DMA_Channel_TypeDef *)  DMA1_Channel6_BASE;
00158
00159   DMA1_Channel7_DBG = (DMA_Channel_TypeDef *)  DMA1_Channel7_BASE;
00160
00161   DMA2_Channel1_DBG = (DMA_Channel_TypeDef *)  DMA2_Channel1_BASE;
00162
00163   DMA2_Channel2_DBG = (DMA_Channel_TypeDef *)  DMA2_Channel2_BASE;
00164
00165   DMA2_Channel3_DBG = (DMA_Channel_TypeDef *)  DMA2_Channel3_BASE;
00166
00167   DMA2_Channel4_DBG = (DMA_Channel_TypeDef *)  DMA2_Channel4_BASE;
00168
00169   DMA2_Channel5_DBG = (DMA_Channel_TypeDef *)  DMA2_Channel5_BASE;
00170
00171 /************************************* EXTI ***********************************/
00172   EXTI_DBG = (EXTI_TypeDef *)  EXTI_BASE;
00173
00174 /************************************* FLASH and Option Bytes *****************/
00175   FLASH_DBG = (FLASH_TypeDef *)  FLASH_R_BASE;
00176   OB_DBG = (OB_TypeDef *)        OB_BASE;
00177
00178 /************************************* FSMC ***********************************/
00179   FSMC_Bank1_DBG = (FSMC_Bank1_TypeDef *)    FSMC_Bank1_R_BASE;
00180   FSMC_Bank1E_DBG = (FSMC_Bank1E_TypeDef *)  FSMC_Bank1E_R_BASE;
00181   FSMC_Bank2_DBG = (FSMC_Bank2_TypeDef *)    FSMC_Bank2_R_BASE;
00182   FSMC_Bank3_DBG = (FSMC_Bank3_TypeDef *)    FSMC_Bank3_R_BASE;
00183   FSMC_Bank4_DBG = (FSMC_Bank4_TypeDef *)    FSMC_Bank4_R_BASE;
00184
00185 /************************************* GPIO ***********************************/
00186   GPIOA_DBG = (GPIO_TypeDef *)  GPIOA_BASE;
00187
00188   GPIOB_DBG = (GPIO_TypeDef *)  GPIOB_BASE;
00189
00190   GPIOC_DBG = (GPIO_TypeDef *)  GPIOC_BASE;
00191
00192   GPIOD_DBG = (GPIO_TypeDef *)  GPIOD_BASE;
00193
00194   GPIOE_DBG = (GPIO_TypeDef *)  GPIOE_BASE;
00195
00196   GPIOF_DBG = (GPIO_TypeDef *)  GPIOF_BASE;
00197
00198   GPIOG_DBG = (GPIO_TypeDef *)  GPIOG_BASE;
00199
00200   AFIO_DBG = (AFIO_TypeDef *)  AFIO_BASE;
00201
00202 /************************************* I2C ************************************/
00203   I2C1_DBG = (I2C_TypeDef *)  I2C1_BASE;
00204
00205   I2C2_DBG = (I2C_TypeDef *)  I2C2_BASE;
00206
00207 /************************************* IWDG ***********************************/
00208   IWDG_DBG = (IWDG_TypeDef *) IWDG_BASE;
00209
00210 /************************************* NVIC ***********************************/
00211   NVIC_DBG = (NVIC_Type *)  NVIC_BASE;
00212   SCB_DBG = (SCB_Type *)  SCB_BASE;
00213
00214 /************************************* PWR ************************************/
00215   PWR_DBG = (PWR_TypeDef *)  PWR_BASE;
00216
00217 /************************************* RCC ************************************/
00218   RCC_DBG = (RCC_TypeDef *)  RCC_BASE;
00219
00220 /************************************* RTC ************************************/
00221   RTC_DBG = (RTC_TypeDef *)  RTC_BASE;
00222
00223 /************************************* SDIO ***********************************/
00224   SDIO_DBG = (SDIO_TypeDef *)  SDIO_BASE;
00225
00226 /************************************* SPI ************************************/
00227   SPI1_DBG = (SPI_TypeDef *)  SPI1_BASE;
00228
00229   SPI2_DBG = (SPI_TypeDef *)  SPI2_BASE;
00230
00231   SPI3_DBG = (SPI_TypeDef *)  SPI3_BASE;
00232
00233 /************************************* SysTick ********************************/
00234   SysTick_DBG = (SysTick_Type *)  SysTick_BASE;
00235
00236 /************************************* TIM ************************************/
00237   TIM1_DBG = (TIM_TypeDef *)  TIM1_BASE;
00238
00239   TIM2_DBG = (TIM_TypeDef *)  TIM2_BASE;
00240
00241   TIM3_DBG = (TIM_TypeDef *)  TIM3_BASE;
00242
00243   TIM4_DBG = (TIM_TypeDef *)  TIM4_BASE;
00244
00245   TIM5_DBG = (TIM_TypeDef *)  TIM5_BASE;
00246
00247   TIM6_DBG = (TIM_TypeDef *)  TIM6_BASE;
00248
00249   TIM7_DBG = (TIM_TypeDef *)  TIM7_BASE;
00250
00251   TIM8_DBG = (TIM_TypeDef *)  TIM8_BASE;
00252
00253   TIM15_DBG = (TIM_TypeDef *)  TIM15_BASE;
00254
00255   TIM16_DBG = (TIM_TypeDef *)  TIM16_BASE;
00256
00257   TIM17_DBG = (TIM_TypeDef *)  TIM17_BASE;
00258
00259 /************************************* USART **********************************/
00260   USART1_DBG = (USART_TypeDef *) USART1_BASE;
00261
00262   USART2_DBG = (USART_TypeDef *) USART2_BASE;
00263
00264   USART3_DBG = (USART_TypeDef *) USART3_BASE;
00265
00266   UART4_DBG = (USART_TypeDef *) UART4_BASE;
00267
00268   UART5_DBG = (USART_TypeDef *) UART5_BASE;
00269
00270 /************************************* WWDG ***********************************/
00271   WWDG_DBG = (WWDG_TypeDef *)  WWDG_BASE;
00272 }
00273
00274 /**
00275   * @}
00276   */
00277
00278 /**
00279   * @}
00280   */
00281
00282 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_ip_dbg.h Source File

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  • Project
  • STM32F10x_StdPeriph_Examples
  • Lib_DEBUG
  • RunTime_Check

stm32f10x_ip_dbg.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    Lib_DEBUG/RunTime_Check/stm32f10x_ip_dbg.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the library peripherals Debug.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10X_IP_DBG_H
00024 #define __STM32F10X_IP_DBG_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void debug(void);
00035
00036 #endif /* __STM32F10X_IP_DBG_H */
00037
00038 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_iwdg.c Source File

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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Libraries
  • STM32F10x_StdPeriph_Driver
  • src

stm32f10x_iwdg.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32f10x_iwdg.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    11-March-2011
00007   * @brief   This file provides all the IWDG firmware functions.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x_iwdg.h"
00024
00025 /** @addtogroup STM32F10x_StdPeriph_Driver
00026   * @{
00027   */
00028
00029 /** @defgroup IWDG
00030   * @brief IWDG driver modules
00031   * @{
00032   */
00033
00034 /** @defgroup IWDG_Private_TypesDefinitions
00035   * @{
00036   */
00037
00038 /**
00039   * @}
00040   */
00041
00042 /** @defgroup IWDG_Private_Defines
00043   * @{
00044   */
00045
00046 /* ---------------------- IWDG registers bit mask ----------------------------*/
00047
00048 /* KR register bit mask */
00049 #define KR_KEY_Reload    ((uint16_t)0xAAAA)
00050 #define KR_KEY_Enable    ((uint16_t)0xCCCC)
00051
00052 /**
00053   * @}
00054   */
00055
00056 /** @defgroup IWDG_Private_Macros
00057   * @{
00058   */
00059
00060 /**
00061   * @}
00062   */
00063
00064 /** @defgroup IWDG_Private_Variables
00065   * @{
00066   */
00067
00068 /**
00069   * @}
00070   */
00071
00072 /** @defgroup IWDG_Private_FunctionPrototypes
00073   * @{
00074   */
00075
00076 /**
00077   * @}
00078   */
00079
00080 /** @defgroup IWDG_Private_Functions
00081   * @{
00082   */
00083
00084 /**
00085   * @brief  Enables or disables write access to IWDG_PR and IWDG_RLR registers.
00086   * @param  IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers.
00087   *   This parameter can be one of the following values:
00088   *     @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers
00089   *     @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers
00090   * @retval None
00091   */
00092 void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess)
00093 {
00094   /* Check the parameters */
00095   assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess));
00096   IWDG->KR = IWDG_WriteAccess;
00097 }
00098
00099 /**
00100   * @brief  Sets IWDG Prescaler value.
00101   * @param  IWDG_Prescaler: specifies the IWDG Prescaler value.
00102   *   This parameter can be one of the following values:
00103   *     @arg IWDG_Prescaler_4: IWDG prescaler set to 4
00104   *     @arg IWDG_Prescaler_8: IWDG prescaler set to 8
00105   *     @arg IWDG_Prescaler_16: IWDG prescaler set to 16
00106   *     @arg IWDG_Prescaler_32: IWDG prescaler set to 32
00107   *     @arg IWDG_Prescaler_64: IWDG prescaler set to 64
00108   *     @arg IWDG_Prescaler_128: IWDG prescaler set to 128
00109   *     @arg IWDG_Prescaler_256: IWDG prescaler set to 256
00110   * @retval None
00111   */
00112 void IWDG_SetPrescaler(uint8_t IWDG_Prescaler)
00113 {
00114   /* Check the parameters */
00115   assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler));
00116   IWDG->PR = IWDG_Prescaler;
00117 }
00118
00119 /**
00120   * @brief  Sets IWDG Reload value.
00121   * @param  Reload: specifies the IWDG Reload value.
00122   *   This parameter must be a number between 0 and 0x0FFF.
00123   * @retval None
00124   */
00125 void IWDG_SetReload(uint16_t Reload)
00126 {
00127   /* Check the parameters */
00128   assert_param(IS_IWDG_RELOAD(Reload));
00129   IWDG->RLR = Reload;
00130 }
00131
00132 /**
00133   * @brief  Reloads IWDG counter with value defined in the reload register
00134   *   (write access to IWDG_PR and IWDG_RLR registers disabled).
00135   * @param  None
00136   * @retval None
00137   */
00138 void IWDG_ReloadCounter(void)
00139 {
00140   IWDG->KR = KR_KEY_Reload;
00141 }
00142
00143 /**
00144   * @brief  Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled).
00145   * @param  None
00146   * @retval None
00147   */
00148 void IWDG_Enable(void)
00149 {
00150   IWDG->KR = KR_KEY_Enable;
00151 }
00152
00153 /**
00154   * @brief  Checks whether the specified IWDG flag is set or not.
00155   * @param  IWDG_FLAG: specifies the flag to check.
00156   *   This parameter can be one of the following values:
00157   *     @arg IWDG_FLAG_PVU: Prescaler Value Update on going
00158   *     @arg IWDG_FLAG_RVU: Reload Value Update on going
00159   * @retval The new state of IWDG_FLAG (SET or RESET).
00160   */
00161 FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG)
00162 {
00163   FlagStatus bitstatus = RESET;
00164   /* Check the parameters */
00165   assert_param(IS_IWDG_FLAG(IWDG_FLAG));
00166   if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET)
00167   {
00168     bitstatus = SET;
00169   }
00170   else
00171   {
00172     bitstatus = RESET;
00173   }
00174   /* Return the flag status */
00175   return bitstatus;
00176 }
00177
00178 /**
00179   * @}
00180   */
00181
00182 /**
00183   * @}
00184   */
00185
00186 /**
00187   * @}
00188   */
00189
00190 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_iwdg.h Source File

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  • Libraries
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  • inc

stm32f10x_iwdg.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32f10x_iwdg.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    11-March-2011
00007   * @brief   This file contains all the functions prototypes for the IWDG
00008   *          firmware library.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00013   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00014   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00015   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00016   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00017   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00018   *
00019   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00020   ******************************************************************************
00021   */
00022
00023 /* Define to prevent recursive inclusion -------------------------------------*/
00024 #ifndef __STM32F10x_IWDG_H
00025 #define __STM32F10x_IWDG_H
00026
00027 #ifdef __cplusplus
00028  extern "C" {
00029 #endif
00030
00031 /* Includes ------------------------------------------------------------------*/
00032 #include "stm32f10x.h"
00033
00034 /** @addtogroup STM32F10x_StdPeriph_Driver
00035   * @{
00036   */
00037
00038 /** @addtogroup IWDG
00039   * @{
00040   */
00041
00042 /** @defgroup IWDG_Exported_Types
00043   * @{
00044   */
00045
00046 /**
00047   * @}
00048   */
00049
00050 /** @defgroup IWDG_Exported_Constants
00051   * @{
00052   */
00053
00054 /** @defgroup IWDG_WriteAccess
00055   * @{
00056   */
00057
00058 #define IWDG_WriteAccess_Enable     ((uint16_t)0x5555)
00059 #define IWDG_WriteAccess_Disable    ((uint16_t)0x0000)
00060 #define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \
00061                                       ((ACCESS) == IWDG_WriteAccess_Disable))
00062 /**
00063   * @}
00064   */
00065
00066 /** @defgroup IWDG_prescaler
00067   * @{
00068   */
00069
00070 #define IWDG_Prescaler_4            ((uint8_t)0x00)
00071 #define IWDG_Prescaler_8            ((uint8_t)0x01)
00072 #define IWDG_Prescaler_16           ((uint8_t)0x02)
00073 #define IWDG_Prescaler_32           ((uint8_t)0x03)
00074 #define IWDG_Prescaler_64           ((uint8_t)0x04)
00075 #define IWDG_Prescaler_128          ((uint8_t)0x05)
00076 #define IWDG_Prescaler_256          ((uint8_t)0x06)
00077 #define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4)  || \
00078                                       ((PRESCALER) == IWDG_Prescaler_8)  || \
00079                                       ((PRESCALER) == IWDG_Prescaler_16) || \
00080                                       ((PRESCALER) == IWDG_Prescaler_32) || \
00081                                       ((PRESCALER) == IWDG_Prescaler_64) || \
00082                                       ((PRESCALER) == IWDG_Prescaler_128)|| \
00083                                       ((PRESCALER) == IWDG_Prescaler_256))
00084 /**
00085   * @}
00086   */
00087
00088 /** @defgroup IWDG_Flag
00089   * @{
00090   */
00091
00092 #define IWDG_FLAG_PVU               ((uint16_t)0x0001)
00093 #define IWDG_FLAG_RVU               ((uint16_t)0x0002)
00094 #define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU))
00095 #define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)
00096 /**
00097   * @}
00098   */
00099
00100 /**
00101   * @}
00102   */
00103
00104 /** @defgroup IWDG_Exported_Macros
00105   * @{
00106   */
00107
00108 /**
00109   * @}
00110   */
00111
00112 /** @defgroup IWDG_Exported_Functions
00113   * @{
00114   */
00115
00116 void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess);
00117 void IWDG_SetPrescaler(uint8_t IWDG_Prescaler);
00118 void IWDG_SetReload(uint16_t Reload);
00119 void IWDG_ReloadCounter(void);
00120 void IWDG_Enable(void);
00121 FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);
00122
00123 #ifdef __cplusplus
00124 }
00125 #endif
00126
00127 #endif /* __STM32F10x_IWDG_H */
00128 /**
00129   * @}
00130   */
00131
00132 /**
00133   * @}
00134   */
00135
00136 /**
00137   * @}
00138   */
00139
00140 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_pwr.c Source File

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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Libraries
  • STM32F10x_StdPeriph_Driver
  • src

stm32f10x_pwr.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32f10x_pwr.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    11-March-2011
00007   * @brief   This file provides all the PWR firmware functions.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x_pwr.h"
00024 #include "stm32f10x_rcc.h"
00025
00026 /** @addtogroup STM32F10x_StdPeriph_Driver
00027   * @{
00028   */
00029
00030 /** @defgroup PWR
00031   * @brief PWR driver modules
00032   * @{
00033   */
00034
00035 /** @defgroup PWR_Private_TypesDefinitions
00036   * @{
00037   */
00038
00039 /**
00040   * @}
00041   */
00042
00043 /** @defgroup PWR_Private_Defines
00044   * @{
00045   */
00046
00047 /* --------- PWR registers bit address in the alias region ---------- */
00048 #define PWR_OFFSET               (PWR_BASE - PERIPH_BASE)
00049
00050 /* --- CR Register ---*/
00051
00052 /* Alias word address of DBP bit */
00053 #define CR_OFFSET                (PWR_OFFSET + 0x00)
00054 #define DBP_BitNumber            0x08
00055 #define CR_DBP_BB                (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))
00056
00057 /* Alias word address of PVDE bit */
00058 #define PVDE_BitNumber           0x04
00059 #define CR_PVDE_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))
00060
00061 /* --- CSR Register ---*/
00062
00063 /* Alias word address of EWUP bit */
00064 #define CSR_OFFSET               (PWR_OFFSET + 0x04)
00065 #define EWUP_BitNumber           0x08
00066 #define CSR_EWUP_BB              (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))
00067
00068 /* ------------------ PWR registers bit mask ------------------------ */
00069
00070 /* CR register bit mask */
00071 #define CR_DS_MASK               ((uint32_t)0xFFFFFFFC)
00072 #define CR_PLS_MASK              ((uint32_t)0xFFFFFF1F)
00073
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @defgroup PWR_Private_Macros
00080   * @{
00081   */
00082
00083 /**
00084   * @}
00085   */
00086
00087 /** @defgroup PWR_Private_Variables
00088   * @{
00089   */
00090
00091 /**
00092   * @}
00093   */
00094
00095 /** @defgroup PWR_Private_FunctionPrototypes
00096   * @{
00097   */
00098
00099 /**
00100   * @}
00101   */
00102
00103 /** @defgroup PWR_Private_Functions
00104   * @{
00105   */
00106
00107 /**
00108   * @brief  Deinitializes the PWR peripheral registers to their default reset values.
00109   * @param  None
00110   * @retval None
00111   */
00112 void PWR_DeInit(void)
00113 {
00114   RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);
00115   RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);
00116 }
00117
00118 /**
00119   * @brief  Enables or disables access to the RTC and backup registers.
00120   * @param  NewState: new state of the access to the RTC and backup registers.
00121   *   This parameter can be: ENABLE or DISABLE.
00122   * @retval None
00123   */
00124 void PWR_BackupAccessCmd(FunctionalState NewState)
00125 {
00126   /* Check the parameters */
00127   assert_param(IS_FUNCTIONAL_STATE(NewState));
00128   *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState;
00129 }
00130
00131 /**
00132   * @brief  Enables or disables the Power Voltage Detector(PVD).
00133   * @param  NewState: new state of the PVD.
00134   *   This parameter can be: ENABLE or DISABLE.
00135   * @retval None
00136   */
00137 void PWR_PVDCmd(FunctionalState NewState)
00138 {
00139   /* Check the parameters */
00140   assert_param(IS_FUNCTIONAL_STATE(NewState));
00141   *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState;
00142 }
00143
00144 /**
00145   * @brief  Configures the voltage threshold detected by the Power Voltage Detector(PVD).
00146   * @param  PWR_PVDLevel: specifies the PVD detection level
00147   *   This parameter can be one of the following values:
00148   *     @arg PWR_PVDLevel_2V2: PVD detection level set to 2.2V
00149   *     @arg PWR_PVDLevel_2V3: PVD detection level set to 2.3V
00150   *     @arg PWR_PVDLevel_2V4: PVD detection level set to 2.4V
00151   *     @arg PWR_PVDLevel_2V5: PVD detection level set to 2.5V
00152   *     @arg PWR_PVDLevel_2V6: PVD detection level set to 2.6V
00153   *     @arg PWR_PVDLevel_2V7: PVD detection level set to 2.7V
00154   *     @arg PWR_PVDLevel_2V8: PVD detection level set to 2.8V
00155   *     @arg PWR_PVDLevel_2V9: PVD detection level set to 2.9V
00156   * @retval None
00157   */
00158 void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
00159 {
00160   uint32_t tmpreg = 0;
00161   /* Check the parameters */
00162   assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));
00163   tmpreg = PWR->CR;
00164   /* Clear PLS[7:5] bits */
00165   tmpreg &= CR_PLS_MASK;
00166   /* Set PLS[7:5] bits according to PWR_PVDLevel value */
00167   tmpreg |= PWR_PVDLevel;
00168   /* Store the new value */
00169   PWR->CR = tmpreg;
00170 }
00171
00172 /**
00173   * @brief  Enables or disables the WakeUp Pin functionality.
00174   * @param  NewState: new state of the WakeUp Pin functionality.
00175   *   This parameter can be: ENABLE or DISABLE.
00176   * @retval None
00177   */
00178 void PWR_WakeUpPinCmd(FunctionalState NewState)
00179 {
00180   /* Check the parameters */
00181   assert_param(IS_FUNCTIONAL_STATE(NewState));
00182   *(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)NewState;
00183 }
00184
00185 /**
00186   * @brief  Enters STOP mode.
00187   * @param  PWR_Regulator: specifies the regulator state in STOP mode.
00188   *   This parameter can be one of the following values:
00189   *     @arg PWR_Regulator_ON: STOP mode with regulator ON
00190   *     @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode
00191   * @param  PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.
00192   *   This parameter can be one of the following values:
00193   *     @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction
00194   *     @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction
00195   * @retval None
00196   */
00197 void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
00198 {
00199   uint32_t tmpreg = 0;
00200   /* Check the parameters */
00201   assert_param(IS_PWR_REGULATOR(PWR_Regulator));
00202   assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
00203
00204   /* Select the regulator state in STOP mode ---------------------------------*/
00205   tmpreg = PWR->CR;
00206   /* Clear PDDS and LPDS bits */
00207   tmpreg &= CR_DS_MASK;
00208   /* Set LPDS bit according to PWR_Regulator value */
00209   tmpreg |= PWR_Regulator;
00210   /* Store the new value */
00211   PWR->CR = tmpreg;
00212   /* Set SLEEPDEEP bit of Cortex System Control Register */
00213   SCB->SCR |= SCB_SCR_SLEEPDEEP;
00214
00215   /* Select STOP mode entry --------------------------------------------------*/
00216   if(PWR_STOPEntry == PWR_STOPEntry_WFI)
00217   {
00218     /* Request Wait For Interrupt */
00219     __WFI();
00220   }
00221   else
00222   {
00223     /* Request Wait For Event */
00224     __WFE();
00225   }
00226
00227   /* Reset SLEEPDEEP bit of Cortex System Control Register */
00228   SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP);
00229 }
00230
00231 /**
00232   * @brief  Enters STANDBY mode.
00233   * @param  None
00234   * @retval None
00235   */
00236 void PWR_EnterSTANDBYMode(void)
00237 {
00238   /* Clear Wake-up flag */
00239   PWR->CR |= PWR_CR_CWUF;
00240   /* Select STANDBY mode */
00241   PWR->CR |= PWR_CR_PDDS;
00242   /* Set SLEEPDEEP bit of Cortex System Control Register */
00243   SCB->SCR |= SCB_SCR_SLEEPDEEP;
00244 /* This option is used to ensure that store operations are completed */
00245 #if defined ( __CC_ARM   )
00246   __force_stores();
00247 #endif
00248   /* Request Wait For Interrupt */
00249   __WFI();
00250 }
00251
00252 /**
00253   * @brief  Checks whether the specified PWR flag is set or not.
00254   * @param  PWR_FLAG: specifies the flag to check.
00255   *   This parameter can be one of the following values:
00256   *     @arg PWR_FLAG_WU: Wake Up flag
00257   *     @arg PWR_FLAG_SB: StandBy flag
00258   *     @arg PWR_FLAG_PVDO: PVD Output
00259   * @retval The new state of PWR_FLAG (SET or RESET).
00260   */
00261 FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
00262 {
00263   FlagStatus bitstatus = RESET;
00264   /* Check the parameters */
00265   assert_param(IS_PWR_GET_FLAG(PWR_FLAG));
00266
00267   if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)
00268   {
00269     bitstatus = SET;
00270   }
00271   else
00272   {
00273     bitstatus = RESET;
00274   }
00275   /* Return the flag status */
00276   return bitstatus;
00277 }
00278
00279 /**
00280   * @brief  Clears the PWR's pending flags.
00281   * @param  PWR_FLAG: specifies the flag to clear.
00282   *   This parameter can be one of the following values:
00283   *     @arg PWR_FLAG_WU: Wake Up flag
00284   *     @arg PWR_FLAG_SB: StandBy flag
00285   * @retval None
00286   */
00287 void PWR_ClearFlag(uint32_t PWR_FLAG)
00288 {
00289   /* Check the parameters */
00290   assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));
00291
00292   PWR->CR |=  PWR_FLAG << 2;
00293 }
00294
00295 /**
00296   * @}
00297   */
00298
00299 /**
00300   * @}
00301   */
00302
00303 /**
00304   * @}
00305   */
00306
00307 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_pwr.h Source File

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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Libraries
  • STM32F10x_StdPeriph_Driver
  • inc

stm32f10x_pwr.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32f10x_pwr.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    11-March-2011
00007   * @brief   This file contains all the functions prototypes for the PWR firmware
00008   *          library.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00013   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00014   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00015   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00016   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00017   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00018   *
00019   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00020   ******************************************************************************
00021   */
00022
00023 /* Define to prevent recursive inclusion -------------------------------------*/
00024 #ifndef __STM32F10x_PWR_H
00025 #define __STM32F10x_PWR_H
00026
00027 #ifdef __cplusplus
00028  extern "C" {
00029 #endif
00030
00031 /* Includes ------------------------------------------------------------------*/
00032 #include "stm32f10x.h"
00033
00034 /** @addtogroup STM32F10x_StdPeriph_Driver
00035   * @{
00036   */
00037
00038 /** @addtogroup PWR
00039   * @{
00040   */
00041
00042 /** @defgroup PWR_Exported_Types
00043   * @{
00044   */
00045
00046 /**
00047   * @}
00048   */
00049
00050 /** @defgroup PWR_Exported_Constants
00051   * @{
00052   */
00053
00054 /** @defgroup PVD_detection_level
00055   * @{
00056   */
00057
00058 #define PWR_PVDLevel_2V2          ((uint32_t)0x00000000)
00059 #define PWR_PVDLevel_2V3          ((uint32_t)0x00000020)
00060 #define PWR_PVDLevel_2V4          ((uint32_t)0x00000040)
00061 #define PWR_PVDLevel_2V5          ((uint32_t)0x00000060)
00062 #define PWR_PVDLevel_2V6          ((uint32_t)0x00000080)
00063 #define PWR_PVDLevel_2V7          ((uint32_t)0x000000A0)
00064 #define PWR_PVDLevel_2V8          ((uint32_t)0x000000C0)
00065 #define PWR_PVDLevel_2V9          ((uint32_t)0x000000E0)
00066 #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_2V2) || ((LEVEL) == PWR_PVDLevel_2V3)|| \
00067                                  ((LEVEL) == PWR_PVDLevel_2V4) || ((LEVEL) == PWR_PVDLevel_2V5)|| \
00068                                  ((LEVEL) == PWR_PVDLevel_2V6) || ((LEVEL) == PWR_PVDLevel_2V7)|| \
00069                                  ((LEVEL) == PWR_PVDLevel_2V8) || ((LEVEL) == PWR_PVDLevel_2V9))
00070 /**
00071   * @}
00072   */
00073
00074 /** @defgroup Regulator_state_is_STOP_mode
00075   * @{
00076   */
00077
00078 #define PWR_Regulator_ON          ((uint32_t)0x00000000)
00079 #define PWR_Regulator_LowPower    ((uint32_t)0x00000001)
00080 #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \
00081                                      ((REGULATOR) == PWR_Regulator_LowPower))
00082 /**
00083   * @}
00084   */
00085
00086 /** @defgroup STOP_mode_entry
00087   * @{
00088   */
00089
00090 #define PWR_STOPEntry_WFI         ((uint8_t)0x01)
00091 #define PWR_STOPEntry_WFE         ((uint8_t)0x02)
00092 #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE))
00093
00094 /**
00095   * @}
00096   */
00097
00098 /** @defgroup PWR_Flag
00099   * @{
00100   */
00101
00102 #define PWR_FLAG_WU               ((uint32_t)0x00000001)
00103 #define PWR_FLAG_SB               ((uint32_t)0x00000002)
00104 #define PWR_FLAG_PVDO             ((uint32_t)0x00000004)
00105 #define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \
00106                                ((FLAG) == PWR_FLAG_PVDO))
00107
00108 #define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB))
00109 /**
00110   * @}
00111   */
00112
00113 /**
00114   * @}
00115   */
00116
00117 /** @defgroup PWR_Exported_Macros
00118   * @{
00119   */
00120
00121 /**
00122   * @}
00123   */
00124
00125 /** @defgroup PWR_Exported_Functions
00126   * @{
00127   */
00128
00129 void PWR_DeInit(void);
00130 void PWR_BackupAccessCmd(FunctionalState NewState);
00131 void PWR_PVDCmd(FunctionalState NewState);
00132 void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);
00133 void PWR_WakeUpPinCmd(FunctionalState NewState);
00134 void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
00135 void PWR_EnterSTANDBYMode(void);
00136 FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);
00137 void PWR_ClearFlag(uint32_t PWR_FLAG);
00138
00139 #ifdef __cplusplus
00140 }
00141 #endif
00142
00143 #endif /* __STM32F10x_PWR_H */
00144 /**
00145   * @}
00146   */
00147
00148 /**
00149   * @}
00150   */
00151
00152 /**
00153   * @}
00154   */
00155
00156 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_rcc.c Source File

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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Libraries
  • STM32F10x_StdPeriph_Driver
  • src

stm32f10x_rcc.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32f10x_rcc.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    11-March-2011
00007   * @brief   This file provides all the RCC firmware functions.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x_rcc.h"
00024
00025 /** @addtogroup STM32F10x_StdPeriph_Driver
00026   * @{
00027   */
00028
00029 /** @defgroup RCC
00030   * @brief RCC driver modules
00031   * @{
00032   */
00033
00034 /** @defgroup RCC_Private_TypesDefinitions
00035   * @{
00036   */
00037
00038 /**
00039   * @}
00040   */
00041
00042 /** @defgroup RCC_Private_Defines
00043   * @{
00044   */
00045
00046 /* ------------ RCC registers bit address in the alias region ----------- */
00047 #define RCC_OFFSET                (RCC_BASE - PERIPH_BASE)
00048
00049 /* --- CR Register ---*/
00050
00051 /* Alias word address of HSION bit */
00052 #define CR_OFFSET                 (RCC_OFFSET + 0x00)
00053 #define HSION_BitNumber           0x00
00054 #define CR_HSION_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))
00055
00056 /* Alias word address of PLLON bit */
00057 #define PLLON_BitNumber           0x18
00058 #define CR_PLLON_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))
00059
00060 #ifdef STM32F10X_CL
00061  /* Alias word address of PLL2ON bit */
00062  #define PLL2ON_BitNumber          0x1A
00063  #define CR_PLL2ON_BB              (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLL2ON_BitNumber * 4))
00064
00065  /* Alias word address of PLL3ON bit */
00066  #define PLL3ON_BitNumber          0x1C
00067  #define CR_PLL3ON_BB              (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLL3ON_BitNumber * 4))
00068 #endif /* STM32F10X_CL */
00069
00070 /* Alias word address of CSSON bit */
00071 #define CSSON_BitNumber           0x13
00072 #define CR_CSSON_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))
00073
00074 /* --- CFGR Register ---*/
00075
00076 /* Alias word address of USBPRE bit */
00077 #define CFGR_OFFSET               (RCC_OFFSET + 0x04)
00078
00079 #ifndef STM32F10X_CL
00080  #define USBPRE_BitNumber          0x16
00081  #define CFGR_USBPRE_BB            (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (USBPRE_BitNumber * 4))
00082 #else
00083  #define OTGFSPRE_BitNumber        0x16
00084  #define CFGR_OTGFSPRE_BB          (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (OTGFSPRE_BitNumber * 4))
00085 #endif /* STM32F10X_CL */
00086
00087 /* --- BDCR Register ---*/
00088
00089 /* Alias word address of RTCEN bit */
00090 #define BDCR_OFFSET               (RCC_OFFSET + 0x20)
00091 #define RTCEN_BitNumber           0x0F
00092 #define BDCR_RTCEN_BB             (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))
00093
00094 /* Alias word address of BDRST bit */
00095 #define BDRST_BitNumber           0x10
00096 #define BDCR_BDRST_BB             (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))
00097
00098 /* --- CSR Register ---*/
00099
00100 /* Alias word address of LSION bit */
00101 #define CSR_OFFSET                (RCC_OFFSET + 0x24)
00102 #define LSION_BitNumber           0x00
00103 #define CSR_LSION_BB              (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))
00104
00105 #ifdef STM32F10X_CL
00106 /* --- CFGR2 Register ---*/
00107
00108  /* Alias word address of I2S2SRC bit */
00109  #define CFGR2_OFFSET              (RCC_OFFSET + 0x2C)
00110  #define I2S2SRC_BitNumber         0x11
00111  #define CFGR2_I2S2SRC_BB          (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (I2S2SRC_BitNumber * 4))
00112
00113  /* Alias word address of I2S3SRC bit */
00114  #define I2S3SRC_BitNumber         0x12
00115  #define CFGR2_I2S3SRC_BB          (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (I2S3SRC_BitNumber * 4))
00116 #endif /* STM32F10X_CL */
00117
00118 /* ---------------------- RCC registers bit mask ------------------------ */
00119
00120 /* CR register bit mask */
00121 #define CR_HSEBYP_Reset           ((uint32_t)0xFFFBFFFF)
00122 #define CR_HSEBYP_Set             ((uint32_t)0x00040000)
00123 #define CR_HSEON_Reset            ((uint32_t)0xFFFEFFFF)
00124 #define CR_HSEON_Set              ((uint32_t)0x00010000)
00125 #define CR_HSITRIM_Mask           ((uint32_t)0xFFFFFF07)
00126
00127 /* CFGR register bit mask */
00128 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL)
00129  #define CFGR_PLL_Mask            ((uint32_t)0xFFC2FFFF)
00130 #else
00131  #define CFGR_PLL_Mask            ((uint32_t)0xFFC0FFFF)
00132 #endif /* STM32F10X_CL */
00133
00134 #define CFGR_PLLMull_Mask         ((uint32_t)0x003C0000)
00135 #define CFGR_PLLSRC_Mask          ((uint32_t)0x00010000)
00136 #define CFGR_PLLXTPRE_Mask        ((uint32_t)0x00020000)
00137 #define CFGR_SWS_Mask             ((uint32_t)0x0000000C)
00138 #define CFGR_SW_Mask              ((uint32_t)0xFFFFFFFC)
00139 #define CFGR_HPRE_Reset_Mask      ((uint32_t)0xFFFFFF0F)
00140 #define CFGR_HPRE_Set_Mask        ((uint32_t)0x000000F0)
00141 #define CFGR_PPRE1_Reset_Mask     ((uint32_t)0xFFFFF8FF)
00142 #define CFGR_PPRE1_Set_Mask       ((uint32_t)0x00000700)
00143 #define CFGR_PPRE2_Reset_Mask     ((uint32_t)0xFFFFC7FF)
00144 #define CFGR_PPRE2_Set_Mask       ((uint32_t)0x00003800)
00145 #define CFGR_ADCPRE_Reset_Mask    ((uint32_t)0xFFFF3FFF)
00146 #define CFGR_ADCPRE_Set_Mask      ((uint32_t)0x0000C000)
00147
00148 /* CSR register bit mask */
00149 #define CSR_RMVF_Set              ((uint32_t)0x01000000)
00150
00151 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL)
00152 /* CFGR2 register bit mask */
00153  #define CFGR2_PREDIV1SRC         ((uint32_t)0x00010000)
00154  #define CFGR2_PREDIV1            ((uint32_t)0x0000000F)
00155 #endif
00156 #ifdef STM32F10X_CL
00157  #define CFGR2_PREDIV2            ((uint32_t)0x000000F0)
00158  #define CFGR2_PLL2MUL            ((uint32_t)0x00000F00)
00159  #define CFGR2_PLL3MUL            ((uint32_t)0x0000F000)
00160 #endif /* STM32F10X_CL */
00161
00162 /* RCC Flag Mask */
00163 #define FLAG_Mask                 ((uint8_t)0x1F)
00164
00165 /* CIR register byte 2 (Bits[15:8]) base address */
00166 #define CIR_BYTE2_ADDRESS         ((uint32_t)0x40021009)
00167
00168 /* CIR register byte 3 (Bits[23:16]) base address */
00169 #define CIR_BYTE3_ADDRESS         ((uint32_t)0x4002100A)
00170
00171 /* CFGR register byte 4 (Bits[31:24]) base address */
00172 #define CFGR_BYTE4_ADDRESS        ((uint32_t)0x40021007)
00173
00174 /* BDCR register base address */
00175 #define BDCR_ADDRESS              (PERIPH_BASE + BDCR_OFFSET)
00176
00177 /**
00178   * @}
00179   */
00180
00181 /** @defgroup RCC_Private_Macros
00182   * @{
00183   */
00184
00185 /**
00186   * @}
00187   */
00188
00189 /** @defgroup RCC_Private_Variables
00190   * @{
00191   */
00192
00193 static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
00194 static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8};
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @defgroup RCC_Private_FunctionPrototypes
00201   * @{
00202   */
00203
00204 /**
00205   * @}
00206   */
00207
00208 /** @defgroup RCC_Private_Functions
00209   * @{
00210   */
00211
00212 /**
00213   * @brief  Resets the RCC clock configuration to the default reset state.
00214   * @param  None
00215   * @retval None
00216   */
00217 void RCC_DeInit(void)
00218 {
00219   /* Set HSION bit */
00220   RCC->CR |= (uint32_t)0x00000001;
00221
00222   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00223 #ifndef STM32F10X_CL
00224   RCC->CFGR &= (uint32_t)0xF8FF0000;
00225 #else
00226   RCC->CFGR &= (uint32_t)0xF0FF0000;
00227 #endif /* STM32F10X_CL */
00228
00229   /* Reset HSEON, CSSON and PLLON bits */
00230   RCC->CR &= (uint32_t)0xFEF6FFFF;
00231
00232   /* Reset HSEBYP bit */
00233   RCC->CR &= (uint32_t)0xFFFBFFFF;
00234
00235   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00236   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00237
00238 #ifdef STM32F10X_CL
00239   /* Reset PLL2ON and PLL3ON bits */
00240   RCC->CR &= (uint32_t)0xEBFFFFFF;
00241
00242   /* Disable all interrupts and clear pending bits  */
00243   RCC->CIR = 0x00FF0000;
00244
00245   /* Reset CFGR2 register */
00246   RCC->CFGR2 = 0x00000000;
00247 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00248   /* Disable all interrupts and clear pending bits  */
00249   RCC->CIR = 0x009F0000;
00250
00251   /* Reset CFGR2 register */
00252   RCC->CFGR2 = 0x00000000;
00253 #else
00254   /* Disable all interrupts and clear pending bits  */
00255   RCC->CIR = 0x009F0000;
00256 #endif /* STM32F10X_CL */
00257
00258 }
00259
00260 /**
00261   * @brief  Configures the External High Speed oscillator (HSE).
00262   * @note   HSE can not be stopped if it is used directly or through the PLL as system clock.
00263   * @param  RCC_HSE: specifies the new state of the HSE.
00264   *   This parameter can be one of the following values:
00265   *     @arg RCC_HSE_OFF: HSE oscillator OFF
00266   *     @arg RCC_HSE_ON: HSE oscillator ON
00267   *     @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock
00268   * @retval None
00269   */
00270 void RCC_HSEConfig(uint32_t RCC_HSE)
00271 {
00272   /* Check the parameters */
00273   assert_param(IS_RCC_HSE(RCC_HSE));
00274   /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/
00275   /* Reset HSEON bit */
00276   RCC->CR &= CR_HSEON_Reset;
00277   /* Reset HSEBYP bit */
00278   RCC->CR &= CR_HSEBYP_Reset;
00279   /* Configure HSE (RCC_HSE_OFF is already covered by the code section above) */
00280   switch(RCC_HSE)
00281   {
00282     case RCC_HSE_ON:
00283       /* Set HSEON bit */
00284       RCC->CR |= CR_HSEON_Set;
00285       break;
00286
00287     case RCC_HSE_Bypass:
00288       /* Set HSEBYP and HSEON bits */
00289       RCC->CR |= CR_HSEBYP_Set | CR_HSEON_Set;
00290       break;
00291
00292     default:
00293       break;
00294   }
00295 }
00296
00297 /**
00298   * @brief  Waits for HSE start-up.
00299   * @param  None
00300   * @retval An ErrorStatus enumuration value:
00301   * - SUCCESS: HSE oscillator is stable and ready to use
00302   * - ERROR: HSE oscillator not yet ready
00303   */
00304 ErrorStatus RCC_WaitForHSEStartUp(void)
00305 {
00306   __IO uint32_t StartUpCounter = 0;
00307   ErrorStatus status = ERROR;
00308   FlagStatus HSEStatus = RESET;
00309
00310   /* Wait till HSE is ready and if Time out is reached exit */
00311   do
00312   {
00313     HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);
00314     StartUpCounter++;
00315   } while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET));
00316
00317   if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
00318   {
00319     status = SUCCESS;
00320   }
00321   else
00322   {
00323     status = ERROR;
00324   }
00325   return (status);
00326 }
00327
00328 /**
00329   * @brief  Adjusts the Internal High Speed oscillator (HSI) calibration value.
00330   * @param  HSICalibrationValue: specifies the calibration trimming value.
00331   *   This parameter must be a number between 0 and 0x1F.
00332   * @retval None
00333   */
00334 void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)
00335 {
00336   uint32_t tmpreg = 0;
00337   /* Check the parameters */
00338   assert_param(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue));
00339   tmpreg = RCC->CR;
00340   /* Clear HSITRIM[4:0] bits */
00341   tmpreg &= CR_HSITRIM_Mask;
00342   /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */
00343   tmpreg |= (uint32_t)HSICalibrationValue << 3;
00344   /* Store the new value */
00345   RCC->CR = tmpreg;
00346 }
00347
00348 /**
00349   * @brief  Enables or disables the Internal High Speed oscillator (HSI).
00350   * @note   HSI can not be stopped if it is used directly or through the PLL as system clock.
00351   * @param  NewState: new state of the HSI. This parameter can be: ENABLE or DISABLE.
00352   * @retval None
00353   */
00354 void RCC_HSICmd(FunctionalState NewState)
00355 {
00356   /* Check the parameters */
00357   assert_param(IS_FUNCTIONAL_STATE(NewState));
00358   *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState;
00359 }
00360
00361 /**
00362   * @brief  Configures the PLL clock source and multiplication factor.
00363   * @note   This function must be used only when the PLL is disabled.
00364   * @param  RCC_PLLSource: specifies the PLL entry clock source.
00365   *   For @b STM32_Connectivity_line_devices or @b STM32_Value_line_devices,
00366   *   this parameter can be one of the following values:
00367   *     @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as PLL clock entry
00368   *     @arg RCC_PLLSource_PREDIV1: PREDIV1 clock selected as PLL clock entry
00369   *   For @b other_STM32_devices, this parameter can be one of the following values:
00370   *     @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as PLL clock entry
00371   *     @arg RCC_PLLSource_HSE_Div1: HSE oscillator clock selected as PLL clock entry
00372   *     @arg RCC_PLLSource_HSE_Div2: HSE oscillator clock divided by 2 selected as PLL clock entry
00373   * @param  RCC_PLLMul: specifies the PLL multiplication factor.
00374   *   For @b STM32_Connectivity_line_devices, this parameter can be RCC_PLLMul_x where x:{[4,9], 6_5}
00375   *   For @b other_STM32_devices, this parameter can be RCC_PLLMul_x where x:[2,16]
00376   * @retval None
00377   */
00378 void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul)
00379 {
00380   uint32_t tmpreg = 0;
00381
00382   /* Check the parameters */
00383   assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));
00384   assert_param(IS_RCC_PLL_MUL(RCC_PLLMul));
00385
00386   tmpreg = RCC->CFGR;
00387   /* Clear PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
00388   tmpreg &= CFGR_PLL_Mask;
00389   /* Set the PLL configuration bits */
00390   tmpreg |= RCC_PLLSource | RCC_PLLMul;
00391   /* Store the new value */
00392   RCC->CFGR = tmpreg;
00393 }
00394
00395 /**
00396   * @brief  Enables or disables the PLL.
00397   * @note   The PLL can not be disabled if it is used as system clock.
00398   * @param  NewState: new state of the PLL. This parameter can be: ENABLE or DISABLE.
00399   * @retval None
00400   */
00401 void RCC_PLLCmd(FunctionalState NewState)
00402 {
00403   /* Check the parameters */
00404   assert_param(IS_FUNCTIONAL_STATE(NewState));
00405
00406   *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState;
00407 }
00408
00409 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL)
00410 /**
00411   * @brief  Configures the PREDIV1 division factor.
00412   * @note
00413   *   - This function must be used only when the PLL is disabled.
00414   *   - This function applies only to STM32 Connectivity line and Value line
00415   *     devices.
00416   * @param  RCC_PREDIV1_Source: specifies the PREDIV1 clock source.
00417   *   This parameter can be one of the following values:
00418   *     @arg RCC_PREDIV1_Source_HSE: HSE selected as PREDIV1 clock
00419   *     @arg RCC_PREDIV1_Source_PLL2: PLL2 selected as PREDIV1 clock
00420   * @note
00421   *   For @b STM32_Value_line_devices this parameter is always RCC_PREDIV1_Source_HSE
00422   * @param  RCC_PREDIV1_Div: specifies the PREDIV1 clock division factor.
00423   *   This parameter can be RCC_PREDIV1_Divx where x:[1,16]
00424   * @retval None
00425   */
00426 void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div)
00427 {
00428   uint32_t tmpreg = 0;
00429
00430   /* Check the parameters */
00431   assert_param(IS_RCC_PREDIV1_SOURCE(RCC_PREDIV1_Source));
00432   assert_param(IS_RCC_PREDIV1(RCC_PREDIV1_Div));
00433
00434   tmpreg = RCC->CFGR2;
00435   /* Clear PREDIV1[3:0] and PREDIV1SRC bits */
00436   tmpreg &= ~(CFGR2_PREDIV1 | CFGR2_PREDIV1SRC);
00437   /* Set the PREDIV1 clock source and division factor */
00438   tmpreg |= RCC_PREDIV1_Source | RCC_PREDIV1_Div ;
00439   /* Store the new value */
00440   RCC->CFGR2 = tmpreg;
00441 }
00442 #endif
00443
00444 #ifdef STM32F10X_CL
00445 /**
00446   * @brief  Configures the PREDIV2 division factor.
00447   * @note
00448   *   - This function must be used only when both PLL2 and PLL3 are disabled.
00449   *   - This function applies only to STM32 Connectivity line devices.
00450   * @param  RCC_PREDIV2_Div: specifies the PREDIV2 clock division factor.
00451   *   This parameter can be RCC_PREDIV2_Divx where x:[1,16]
00452   * @retval None
00453   */
00454 void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div)
00455 {
00456   uint32_t tmpreg = 0;
00457
00458   /* Check the parameters */
00459   assert_param(IS_RCC_PREDIV2(RCC_PREDIV2_Div));
00460
00461   tmpreg = RCC->CFGR2;
00462   /* Clear PREDIV2[3:0] bits */
00463   tmpreg &= ~CFGR2_PREDIV2;
00464   /* Set the PREDIV2 division factor */
00465   tmpreg |= RCC_PREDIV2_Div;
00466   /* Store the new value */
00467   RCC->CFGR2 = tmpreg;
00468 }
00469
00470 /**
00471   * @brief  Configures the PLL2 multiplication factor.
00472   * @note
00473   *   - This function must be used only when the PLL2 is disabled.
00474   *   - This function applies only to STM32 Connectivity line devices.
00475   * @param  RCC_PLL2Mul: specifies the PLL2 multiplication factor.
00476   *   This parameter can be RCC_PLL2Mul_x where x:{[8,14], 16, 20}
00477   * @retval None
00478   */
00479 void RCC_PLL2Config(uint32_t RCC_PLL2Mul)
00480 {
00481   uint32_t tmpreg = 0;
00482
00483   /* Check the parameters */
00484   assert_param(IS_RCC_PLL2_MUL(RCC_PLL2Mul));
00485
00486   tmpreg = RCC->CFGR2;
00487   /* Clear PLL2Mul[3:0] bits */
00488   tmpreg &= ~CFGR2_PLL2MUL;
00489   /* Set the PLL2 configuration bits */
00490   tmpreg |= RCC_PLL2Mul;
00491   /* Store the new value */
00492   RCC->CFGR2 = tmpreg;
00493 }
00494
00495
00496 /**
00497   * @brief  Enables or disables the PLL2.
00498   * @note
00499   *   - The PLL2 can not be disabled if it is used indirectly as system clock
00500   *     (i.e. it is used as PLL clock entry that is used as System clock).
00501   *   - This function applies only to STM32 Connectivity line devices.
00502   * @param  NewState: new state of the PLL2. This parameter can be: ENABLE or DISABLE.
00503   * @retval None
00504   */
00505 void RCC_PLL2Cmd(FunctionalState NewState)
00506 {
00507   /* Check the parameters */
00508   assert_param(IS_FUNCTIONAL_STATE(NewState));
00509
00510   *(__IO uint32_t *) CR_PLL2ON_BB = (uint32_t)NewState;
00511 }
00512
00513
00514 /**
00515   * @brief  Configures the PLL3 multiplication factor.
00516   * @note
00517   *   - This function must be used only when the PLL3 is disabled.
00518   *   - This function applies only to STM32 Connectivity line devices.
00519   * @param  RCC_PLL3Mul: specifies the PLL3 multiplication factor.
00520   *   This parameter can be RCC_PLL3Mul_x where x:{[8,14], 16, 20}
00521   * @retval None
00522   */
00523 void RCC_PLL3Config(uint32_t RCC_PLL3Mul)
00524 {
00525   uint32_t tmpreg = 0;
00526
00527   /* Check the parameters */
00528   assert_param(IS_RCC_PLL3_MUL(RCC_PLL3Mul));
00529
00530   tmpreg = RCC->CFGR2;
00531   /* Clear PLL3Mul[3:0] bits */
00532   tmpreg &= ~CFGR2_PLL3MUL;
00533   /* Set the PLL3 configuration bits */
00534   tmpreg |= RCC_PLL3Mul;
00535   /* Store the new value */
00536   RCC->CFGR2 = tmpreg;
00537 }
00538
00539
00540 /**
00541   * @brief  Enables or disables the PLL3.
00542   * @note   This function applies only to STM32 Connectivity line devices.
00543   * @param  NewState: new state of the PLL3. This parameter can be: ENABLE or DISABLE.
00544   * @retval None
00545   */
00546 void RCC_PLL3Cmd(FunctionalState NewState)
00547 {
00548   /* Check the parameters */
00549
00550   assert_param(IS_FUNCTIONAL_STATE(NewState));
00551   *(__IO uint32_t *) CR_PLL3ON_BB = (uint32_t)NewState;
00552 }
00553 #endif /* STM32F10X_CL */
00554
00555 /**
00556   * @brief  Configures the system clock (SYSCLK).
00557   * @param  RCC_SYSCLKSource: specifies the clock source used as system clock.
00558   *   This parameter can be one of the following values:
00559   *     @arg RCC_SYSCLKSource_HSI: HSI selected as system clock
00560   *     @arg RCC_SYSCLKSource_HSE: HSE selected as system clock
00561   *     @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock
00562   * @retval None
00563   */
00564 void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
00565 {
00566   uint32_t tmpreg = 0;
00567   /* Check the parameters */
00568   assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));
00569   tmpreg = RCC->CFGR;
00570   /* Clear SW[1:0] bits */
00571   tmpreg &= CFGR_SW_Mask;
00572   /* Set SW[1:0] bits according to RCC_SYSCLKSource value */
00573   tmpreg |= RCC_SYSCLKSource;
00574   /* Store the new value */
00575   RCC->CFGR = tmpreg;
00576 }
00577
00578 /**
00579   * @brief  Returns the clock source used as system clock.
00580   * @param  None
00581   * @retval The clock source used as system clock. The returned value can
00582   *   be one of the following:
00583   *     - 0x00: HSI used as system clock
00584   *     - 0x04: HSE used as system clock
00585   *     - 0x08: PLL used as system clock
00586   */
00587 uint8_t RCC_GetSYSCLKSource(void)
00588 {
00589   return ((uint8_t)(RCC->CFGR & CFGR_SWS_Mask));
00590 }
00591
00592 /**
00593   * @brief  Configures the AHB clock (HCLK).
00594   * @param  RCC_SYSCLK: defines the AHB clock divider. This clock is derived from
00595   *   the system clock (SYSCLK).
00596   *   This parameter can be one of the following values:
00597   *     @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK
00598   *     @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
00599   *     @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
00600   *     @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
00601   *     @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
00602   *     @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
00603   *     @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
00604   *     @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
00605   *     @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
00606   * @retval None
00607   */
00608 void RCC_HCLKConfig(uint32_t RCC_SYSCLK)
00609 {
00610   uint32_t tmpreg = 0;
00611   /* Check the parameters */
00612   assert_param(IS_RCC_HCLK(RCC_SYSCLK));
00613   tmpreg = RCC->CFGR;
00614   /* Clear HPRE[3:0] bits */
00615   tmpreg &= CFGR_HPRE_Reset_Mask;
00616   /* Set HPRE[3:0] bits according to RCC_SYSCLK value */
00617   tmpreg |= RCC_SYSCLK;
00618   /* Store the new value */
00619   RCC->CFGR = tmpreg;
00620 }
00621
00622 /**
00623   * @brief  Configures the Low Speed APB clock (PCLK1).
00624   * @param  RCC_HCLK: defines the APB1 clock divider. This clock is derived from
00625   *   the AHB clock (HCLK).
00626   *   This parameter can be one of the following values:
00627   *     @arg RCC_HCLK_Div1: APB1 clock = HCLK
00628   *     @arg RCC_HCLK_Div2: APB1 clock = HCLK/2
00629   *     @arg RCC_HCLK_Div4: APB1 clock = HCLK/4
00630   *     @arg RCC_HCLK_Div8: APB1 clock = HCLK/8
00631   *     @arg RCC_HCLK_Div16: APB1 clock = HCLK/16
00632   * @retval None
00633   */
00634 void RCC_PCLK1Config(uint32_t RCC_HCLK)
00635 {
00636   uint32_t tmpreg = 0;
00637   /* Check the parameters */
00638   assert_param(IS_RCC_PCLK(RCC_HCLK));
00639   tmpreg = RCC->CFGR;
00640   /* Clear PPRE1[2:0] bits */
00641   tmpreg &= CFGR_PPRE1_Reset_Mask;
00642   /* Set PPRE1[2:0] bits according to RCC_HCLK value */
00643   tmpreg |= RCC_HCLK;
00644   /* Store the new value */
00645   RCC->CFGR = tmpreg;
00646 }
00647
00648 /**
00649   * @brief  Configures the High Speed APB clock (PCLK2).
00650   * @param  RCC_HCLK: defines the APB2 clock divider. This clock is derived from
00651   *   the AHB clock (HCLK).
00652   *   This parameter can be one of the following values:
00653   *     @arg RCC_HCLK_Div1: APB2 clock = HCLK
00654   *     @arg RCC_HCLK_Div2: APB2 clock = HCLK/2
00655   *     @arg RCC_HCLK_Div4: APB2 clock = HCLK/4
00656   *     @arg RCC_HCLK_Div8: APB2 clock = HCLK/8
00657   *     @arg RCC_HCLK_Div16: APB2 clock = HCLK/16
00658   * @retval None
00659   */
00660 void RCC_PCLK2Config(uint32_t RCC_HCLK)
00661 {
00662   uint32_t tmpreg = 0;
00663   /* Check the parameters */
00664   assert_param(IS_RCC_PCLK(RCC_HCLK));
00665   tmpreg = RCC->CFGR;
00666   /* Clear PPRE2[2:0] bits */
00667   tmpreg &= CFGR_PPRE2_Reset_Mask;
00668   /* Set PPRE2[2:0] bits according to RCC_HCLK value */
00669   tmpreg |= RCC_HCLK << 3;
00670   /* Store the new value */
00671   RCC->CFGR = tmpreg;
00672 }
00673
00674 /**
00675   * @brief  Enables or disables the specified RCC interrupts.
00676   * @param  RCC_IT: specifies the RCC interrupt sources to be enabled or disabled.
00677   *
00678   *   For @b STM32_Connectivity_line_devices, this parameter can be any combination
00679   *   of the following values
00680   *     @arg RCC_IT_LSIRDY: LSI ready interrupt
00681   *     @arg RCC_IT_LSERDY: LSE ready interrupt
00682   *     @arg RCC_IT_HSIRDY: HSI ready interrupt
00683   *     @arg RCC_IT_HSERDY: HSE ready interrupt
00684   *     @arg RCC_IT_PLLRDY: PLL ready interrupt
00685   *     @arg RCC_IT_PLL2RDY: PLL2 ready interrupt
00686   *     @arg RCC_IT_PLL3RDY: PLL3 ready interrupt
00687   *
00688   *   For @b other_STM32_devices, this parameter can be any combination of the
00689   *   following values
00690   *     @arg RCC_IT_LSIRDY: LSI ready interrupt
00691   *     @arg RCC_IT_LSERDY: LSE ready interrupt
00692   *     @arg RCC_IT_HSIRDY: HSI ready interrupt
00693   *     @arg RCC_IT_HSERDY: HSE ready interrupt
00694   *     @arg RCC_IT_PLLRDY: PLL ready interrupt
00695   *
00696   * @param  NewState: new state of the specified RCC interrupts.
00697   *   This parameter can be: ENABLE or DISABLE.
00698   * @retval None
00699   */
00700 void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)
00701 {
00702   /* Check the parameters */
00703   assert_param(IS_RCC_IT(RCC_IT));
00704   assert_param(IS_FUNCTIONAL_STATE(NewState));
00705   if (NewState != DISABLE)
00706   {
00707     /* Perform Byte access to RCC_CIR bits to enable the selected interrupts */
00708     *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT;
00709   }
00710   else
00711   {
00712     /* Perform Byte access to RCC_CIR bits to disable the selected interrupts */
00713     *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT;
00714   }
00715 }
00716
00717 #ifndef STM32F10X_CL
00718 /**
00719   * @brief  Configures the USB clock (USBCLK).
00720   * @param  RCC_USBCLKSource: specifies the USB clock source. This clock is
00721   *   derived from the PLL output.
00722   *   This parameter can be one of the following values:
00723   *     @arg RCC_USBCLKSource_PLLCLK_1Div5: PLL clock divided by 1,5 selected as USB
00724   *                                     clock source
00725   *     @arg RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB clock source
00726   * @retval None
00727   */
00728 void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource)
00729 {
00730   /* Check the parameters */
00731   assert_param(IS_RCC_USBCLK_SOURCE(RCC_USBCLKSource));
00732
00733   *(__IO uint32_t *) CFGR_USBPRE_BB = RCC_USBCLKSource;
00734 }
00735 #else
00736 /**
00737   * @brief  Configures the USB OTG FS clock (OTGFSCLK).
00738   *   This function applies only to STM32 Connectivity line devices.
00739   * @param  RCC_OTGFSCLKSource: specifies the USB OTG FS clock source.
00740   *   This clock is derived from the PLL output.
00741   *   This parameter can be one of the following values:
00742   *     @arg  RCC_OTGFSCLKSource_PLLVCO_Div3: PLL VCO clock divided by 2 selected as USB OTG FS clock source
00743   *     @arg  RCC_OTGFSCLKSource_PLLVCO_Div2: PLL VCO clock divided by 2 selected as USB OTG FS clock source
00744   * @retval None
00745   */
00746 void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource)
00747 {
00748   /* Check the parameters */
00749   assert_param(IS_RCC_OTGFSCLK_SOURCE(RCC_OTGFSCLKSource));
00750
00751   *(__IO uint32_t *) CFGR_OTGFSPRE_BB = RCC_OTGFSCLKSource;
00752 }
00753 #endif /* STM32F10X_CL */
00754
00755 /**
00756   * @brief  Configures the ADC clock (ADCCLK).
00757   * @param  RCC_PCLK2: defines the ADC clock divider. This clock is derived from
00758   *   the APB2 clock (PCLK2).
00759   *   This parameter can be one of the following values:
00760   *     @arg RCC_PCLK2_Div2: ADC clock = PCLK2/2
00761   *     @arg RCC_PCLK2_Div4: ADC clock = PCLK2/4
00762   *     @arg RCC_PCLK2_Div6: ADC clock = PCLK2/6
00763   *     @arg RCC_PCLK2_Div8: ADC clock = PCLK2/8
00764   * @retval None
00765   */
00766 void RCC_ADCCLKConfig(uint32_t RCC_PCLK2)
00767 {
00768   uint32_t tmpreg = 0;
00769   /* Check the parameters */
00770   assert_param(IS_RCC_ADCCLK(RCC_PCLK2));
00771   tmpreg = RCC->CFGR;
00772   /* Clear ADCPRE[1:0] bits */
00773   tmpreg &= CFGR_ADCPRE_Reset_Mask;
00774   /* Set ADCPRE[1:0] bits according to RCC_PCLK2 value */
00775   tmpreg |= RCC_PCLK2;
00776   /* Store the new value */
00777   RCC->CFGR = tmpreg;
00778 }
00779
00780 #ifdef STM32F10X_CL
00781 /**
00782   * @brief  Configures the I2S2 clock source(I2S2CLK).
00783   * @note
00784   *   - This function must be called before enabling I2S2 APB clock.
00785   *   - This function applies only to STM32 Connectivity line devices.
00786   * @param  RCC_I2S2CLKSource: specifies the I2S2 clock source.
00787   *   This parameter can be one of the following values:
00788   *     @arg RCC_I2S2CLKSource_SYSCLK: system clock selected as I2S2 clock entry
00789   *     @arg RCC_I2S2CLKSource_PLL3_VCO: PLL3 VCO clock selected as I2S2 clock entry
00790   * @retval None
00791   */
00792 void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource)
00793 {
00794   /* Check the parameters */
00795   assert_param(IS_RCC_I2S2CLK_SOURCE(RCC_I2S2CLKSource));
00796
00797   *(__IO uint32_t *) CFGR2_I2S2SRC_BB = RCC_I2S2CLKSource;
00798 }
00799
00800 /**
00801   * @brief  Configures the I2S3 clock source(I2S2CLK).
00802   * @note
00803   *   - This function must be called before enabling I2S3 APB clock.
00804   *   - This function applies only to STM32 Connectivity line devices.
00805   * @param  RCC_I2S3CLKSource: specifies the I2S3 clock source.
00806   *   This parameter can be one of the following values:
00807   *     @arg RCC_I2S3CLKSource_SYSCLK: system clock selected as I2S3 clock entry
00808   *     @arg RCC_I2S3CLKSource_PLL3_VCO: PLL3 VCO clock selected as I2S3 clock entry
00809   * @retval None
00810   */
00811 void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource)
00812 {
00813   /* Check the parameters */
00814   assert_param(IS_RCC_I2S3CLK_SOURCE(RCC_I2S3CLKSource));
00815
00816   *(__IO uint32_t *) CFGR2_I2S3SRC_BB = RCC_I2S3CLKSource;
00817 }
00818 #endif /* STM32F10X_CL */
00819
00820 /**
00821   * @brief  Configures the External Low Speed oscillator (LSE).
00822   * @param  RCC_LSE: specifies the new state of the LSE.
00823   *   This parameter can be one of the following values:
00824   *     @arg RCC_LSE_OFF: LSE oscillator OFF
00825   *     @arg RCC_LSE_ON: LSE oscillator ON
00826   *     @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock
00827   * @retval None
00828   */
00829 void RCC_LSEConfig(uint8_t RCC_LSE)
00830 {
00831   /* Check the parameters */
00832   assert_param(IS_RCC_LSE(RCC_LSE));
00833   /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/
00834   /* Reset LSEON bit */
00835   *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF;
00836   /* Reset LSEBYP bit */
00837   *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF;
00838   /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */
00839   switch(RCC_LSE)
00840   {
00841     case RCC_LSE_ON:
00842       /* Set LSEON bit */
00843       *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_ON;
00844       break;
00845
00846     case RCC_LSE_Bypass:
00847       /* Set LSEBYP and LSEON bits */
00848       *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON;
00849       break;
00850
00851     default:
00852       break;
00853   }
00854 }
00855
00856 /**
00857   * @brief  Enables or disables the Internal Low Speed oscillator (LSI).
00858   * @note   LSI can not be disabled if the IWDG is running.
00859   * @param  NewState: new state of the LSI. This parameter can be: ENABLE or DISABLE.
00860   * @retval None
00861   */
00862 void RCC_LSICmd(FunctionalState NewState)
00863 {
00864   /* Check the parameters */
00865   assert_param(IS_FUNCTIONAL_STATE(NewState));
00866   *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState;
00867 }
00868
00869 /**
00870   * @brief  Configures the RTC clock (RTCCLK).
00871   * @note   Once the RTC clock is selected it can't be changed unless the Backup domain is reset.
00872   * @param  RCC_RTCCLKSource: specifies the RTC clock source.
00873   *   This parameter can be one of the following values:
00874   *     @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock
00875   *     @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock
00876   *     @arg RCC_RTCCLKSource_HSE_Div128: HSE clock divided by 128 selected as RTC clock
00877   * @retval None
00878   */
00879 void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)
00880 {
00881   /* Check the parameters */
00882   assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));
00883   /* Select the RTC clock source */
00884   RCC->BDCR |= RCC_RTCCLKSource;
00885 }
00886
00887 /**
00888   * @brief  Enables or disables the RTC clock.
00889   * @note   This function must be used only after the RTC clock was selected using the RCC_RTCCLKConfig function.
00890   * @param  NewState: new state of the RTC clock. This parameter can be: ENABLE or DISABLE.
00891   * @retval None
00892   */
00893 void RCC_RTCCLKCmd(FunctionalState NewState)
00894 {
00895   /* Check the parameters */
00896   assert_param(IS_FUNCTIONAL_STATE(NewState));
00897   *(__IO uint32_t *) BDCR_RTCEN_BB = (uint32_t)NewState;
00898 }
00899
00900 /**
00901   * @brief  Returns the frequencies of different on chip clocks.
00902   * @param  RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold
00903   *         the clocks frequencies.
00904   * @note   The result of this function could be not correct when using
00905   *         fractional value for HSE crystal.
00906   * @retval None
00907   */
00908 void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
00909 {
00910   uint32_t tmp = 0, pllmull = 0, pllsource = 0, presc = 0;
00911
00912 #ifdef  STM32F10X_CL
00913   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00914 #endif /* STM32F10X_CL */
00915
00916 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00917   uint32_t prediv1factor = 0;
00918 #endif
00919
00920   /* Get SYSCLK source -------------------------------------------------------*/
00921   tmp = RCC->CFGR & CFGR_SWS_Mask;
00922
00923   switch (tmp)
00924   {
00925     case 0x00:  /* HSI used as system clock */
00926       RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
00927       break;
00928     case 0x04:  /* HSE used as system clock */
00929       RCC_Clocks->SYSCLK_Frequency = HSE_VALUE;
00930       break;
00931     case 0x08:  /* PLL used as system clock */
00932
00933       /* Get PLL clock source and multiplication factor ----------------------*/
00934       pllmull = RCC->CFGR & CFGR_PLLMull_Mask;
00935       pllsource = RCC->CFGR & CFGR_PLLSRC_Mask;
00936
00937 #ifndef STM32F10X_CL
00938       pllmull = ( pllmull >> 18) + 2;
00939
00940       if (pllsource == 0x00)
00941       {/* HSI oscillator clock divided by 2 selected as PLL clock entry */
00942         RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >> 1) * pllmull;
00943       }
00944       else
00945       {
00946  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00947        prediv1factor = (RCC->CFGR2 & CFGR2_PREDIV1) + 1;
00948        /* HSE oscillator clock selected as PREDIV1 clock entry */
00949        RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE / prediv1factor) * pllmull;
00950  #else
00951         /* HSE selected as PLL clock entry */
00952         if ((RCC->CFGR & CFGR_PLLXTPRE_Mask) != (uint32_t)RESET)
00953         {/* HSE oscillator clock divided by 2 */
00954           RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE >> 1) * pllmull;
00955         }
00956         else
00957         {
00958           RCC_Clocks->SYSCLK_Frequency = HSE_VALUE * pllmull;
00959         }
00960  #endif
00961       }
00962 #else
00963       pllmull = pllmull >> 18;
00964
00965       if (pllmull != 0x0D)
00966       {
00967          pllmull += 2;
00968       }
00969       else
00970       { /* PLL multiplication factor = PLL input clock * 6.5 */
00971         pllmull = 13 / 2;
00972       }
00973
00974       if (pllsource == 0x00)
00975       {/* HSI oscillator clock divided by 2 selected as PLL clock entry */
00976         RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >> 1) * pllmull;
00977       }
00978       else
00979       {/* PREDIV1 selected as PLL clock entry */
00980
00981         /* Get PREDIV1 clock source and division factor */
00982         prediv1source = RCC->CFGR2 & CFGR2_PREDIV1SRC;
00983         prediv1factor = (RCC->CFGR2 & CFGR2_PREDIV1) + 1;
00984
00985         if (prediv1source == 0)
00986         { /* HSE oscillator clock selected as PREDIV1 clock entry */
00987           RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE / prediv1factor) * pllmull;
00988         }
00989         else
00990         {/* PLL2 clock selected as PREDIV1 clock entry */
00991
00992           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00993           prediv2factor = ((RCC->CFGR2 & CFGR2_PREDIV2) >> 4) + 1;
00994           pll2mull = ((RCC->CFGR2 & CFGR2_PLL2MUL) >> 8 ) + 2;
00995           RCC_Clocks->SYSCLK_Frequency = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
00996         }
00997       }
00998 #endif /* STM32F10X_CL */
00999       break;
01000
01001     default:
01002       RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
01003       break;
01004   }
01005
01006   /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/
01007   /* Get HCLK prescaler */
01008   tmp = RCC->CFGR & CFGR_HPRE_Set_Mask;
01009   tmp = tmp >> 4;
01010   presc = APBAHBPrescTable[tmp];
01011   /* HCLK clock frequency */
01012   RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
01013   /* Get PCLK1 prescaler */
01014   tmp = RCC->CFGR & CFGR_PPRE1_Set_Mask;
01015   tmp = tmp >> 8;
01016   presc = APBAHBPrescTable[tmp];
01017   /* PCLK1 clock frequency */
01018   RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
01019   /* Get PCLK2 prescaler */
01020   tmp = RCC->CFGR & CFGR_PPRE2_Set_Mask;
01021   tmp = tmp >> 11;
01022   presc = APBAHBPrescTable[tmp];
01023   /* PCLK2 clock frequency */
01024   RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
01025   /* Get ADCCLK prescaler */
01026   tmp = RCC->CFGR & CFGR_ADCPRE_Set_Mask;
01027   tmp = tmp >> 14;
01028   presc = ADCPrescTable[tmp];
01029   /* ADCCLK clock frequency */
01030   RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc;
01031 }
01032
01033 /**
01034   * @brief  Enables or disables the AHB peripheral clock.
01035   * @param  RCC_AHBPeriph: specifies the AHB peripheral to gates its clock.
01036   *
01037   *   For @b STM32_Connectivity_line_devices, this parameter can be any combination
01038   *   of the following values:
01039   *     @arg RCC_AHBPeriph_DMA1
01040   *     @arg RCC_AHBPeriph_DMA2
01041   *     @arg RCC_AHBPeriph_SRAM
01042   *     @arg RCC_AHBPeriph_FLITF
01043   *     @arg RCC_AHBPeriph_CRC
01044   *     @arg RCC_AHBPeriph_OTG_FS
01045   *     @arg RCC_AHBPeriph_ETH_MAC
01046   *     @arg RCC_AHBPeriph_ETH_MAC_Tx
01047   *     @arg RCC_AHBPeriph_ETH_MAC_Rx
01048   *
01049   *   For @b other_STM32_devices, this parameter can be any combination of the
01050   *   following values:
01051   *     @arg RCC_AHBPeriph_DMA1
01052   *     @arg RCC_AHBPeriph_DMA2
01053   *     @arg RCC_AHBPeriph_SRAM
01054   *     @arg RCC_AHBPeriph_FLITF
01055   *     @arg RCC_AHBPeriph_CRC
01056   *     @arg RCC_AHBPeriph_FSMC
01057   *     @arg RCC_AHBPeriph_SDIO
01058   *
01059   * @note SRAM and FLITF clock can be disabled only during sleep mode.
01060   * @param  NewState: new state of the specified peripheral clock.
01061   *   This parameter can be: ENABLE or DISABLE.
01062   * @retval None
01063   */
01064 void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
01065 {
01066   /* Check the parameters */
01067   assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));
01068   assert_param(IS_FUNCTIONAL_STATE(NewState));
01069
01070   if (NewState != DISABLE)
01071   {
01072     RCC->AHBENR |= RCC_AHBPeriph;
01073   }
01074   else
01075   {
01076     RCC->AHBENR &= ~RCC_AHBPeriph;
01077   }
01078 }
01079
01080 /**
01081   * @brief  Enables or disables the High Speed APB (APB2) peripheral clock.
01082   * @param  RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.
01083   *   This parameter can be any combination of the following values:
01084   *     @arg RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB,
01085   *          RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE,
01086   *          RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1,
01087   *          RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1,
01088   *          RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3,
01089   *          RCC_APB2Periph_TIM15, RCC_APB2Periph_TIM16, RCC_APB2Periph_TIM17,
01090   *          RCC_APB2Periph_TIM9, RCC_APB2Periph_TIM10, RCC_APB2Periph_TIM11
01091   * @param  NewState: new state of the specified peripheral clock.
01092   *   This parameter can be: ENABLE or DISABLE.
01093   * @retval None
01094   */
01095 void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
01096 {
01097   /* Check the parameters */
01098   assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
01099   assert_param(IS_FUNCTIONAL_STATE(NewState));
01100   if (NewState != DISABLE)
01101   {
01102     RCC->APB2ENR |= RCC_APB2Periph;
01103   }
01104   else
01105   {
01106     RCC->APB2ENR &= ~RCC_APB2Periph;
01107   }
01108 }
01109
01110 /**
01111   * @brief  Enables or disables the Low Speed APB (APB1) peripheral clock.
01112   * @param  RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.
01113   *   This parameter can be any combination of the following values:
01114   *     @arg RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4,
01115   *          RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7,
01116   *          RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3,
01117   *          RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4,
01118   *          RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2,
01119   *          RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP,
01120   *          RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_CEC,
01121   *          RCC_APB1Periph_TIM12, RCC_APB1Periph_TIM13, RCC_APB1Periph_TIM14
01122   * @param  NewState: new state of the specified peripheral clock.
01123   *   This parameter can be: ENABLE or DISABLE.
01124   * @retval None
01125   */
01126 void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
01127 {
01128   /* Check the parameters */
01129   assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
01130   assert_param(IS_FUNCTIONAL_STATE(NewState));
01131   if (NewState != DISABLE)
01132   {
01133     RCC->APB1ENR |= RCC_APB1Periph;
01134   }
01135   else
01136   {
01137     RCC->APB1ENR &= ~RCC_APB1Periph;
01138   }
01139 }
01140
01141 #ifdef STM32F10X_CL
01142 /**
01143   * @brief  Forces or releases AHB peripheral reset.
01144   * @note   This function applies only to STM32 Connectivity line devices.
01145   * @param  RCC_AHBPeriph: specifies the AHB peripheral to reset.
01146   *   This parameter can be any combination of the following values:
01147   *     @arg RCC_AHBPeriph_OTG_FS
01148   *     @arg RCC_AHBPeriph_ETH_MAC
01149   * @param  NewState: new state of the specified peripheral reset.
01150   *   This parameter can be: ENABLE or DISABLE.
01151   * @retval None
01152   */
01153 void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
01154 {
01155   /* Check the parameters */
01156   assert_param(IS_RCC_AHB_PERIPH_RESET(RCC_AHBPeriph));
01157   assert_param(IS_FUNCTIONAL_STATE(NewState));
01158
01159   if (NewState != DISABLE)
01160   {
01161     RCC->AHBRSTR |= RCC_AHBPeriph;
01162   }
01163   else
01164   {
01165     RCC->AHBRSTR &= ~RCC_AHBPeriph;
01166   }
01167 }
01168 #endif /* STM32F10X_CL */
01169
01170 /**
01171   * @brief  Forces or releases High Speed APB (APB2) peripheral reset.
01172   * @param  RCC_APB2Periph: specifies the APB2 peripheral to reset.
01173   *   This parameter can be any combination of the following values:
01174   *     @arg RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB,
01175   *          RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE,
01176   *          RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1,
01177   *          RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1,
01178   *          RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3,
01179   *          RCC_APB2Periph_TIM15, RCC_APB2Periph_TIM16, RCC_APB2Periph_TIM17,
01180   *          RCC_APB2Periph_TIM9, RCC_APB2Periph_TIM10, RCC_APB2Periph_TIM11
01181   * @param  NewState: new state of the specified peripheral reset.
01182   *   This parameter can be: ENABLE or DISABLE.
01183   * @retval None
01184   */
01185 void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
01186 {
01187   /* Check the parameters */
01188   assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
01189   assert_param(IS_FUNCTIONAL_STATE(NewState));
01190   if (NewState != DISABLE)
01191   {
01192     RCC->APB2RSTR |= RCC_APB2Periph;
01193   }
01194   else
01195   {
01196     RCC->APB2RSTR &= ~RCC_APB2Periph;
01197   }
01198 }
01199
01200 /**
01201   * @brief  Forces or releases Low Speed APB (APB1) peripheral reset.
01202   * @param  RCC_APB1Periph: specifies the APB1 peripheral to reset.
01203   *   This parameter can be any combination of the following values:
01204   *     @arg RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4,
01205   *          RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7,
01206   *          RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3,
01207   *          RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4,
01208   *          RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2,
01209   *          RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP,
01210   *          RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_CEC,
01211   *          RCC_APB1Periph_TIM12, RCC_APB1Periph_TIM13, RCC_APB1Periph_TIM14
01212   * @param  NewState: new state of the specified peripheral clock.
01213   *   This parameter can be: ENABLE or DISABLE.
01214   * @retval None
01215   */
01216 void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
01217 {
01218   /* Check the parameters */
01219   assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
01220   assert_param(IS_FUNCTIONAL_STATE(NewState));
01221   if (NewState != DISABLE)
01222   {
01223     RCC->APB1RSTR |= RCC_APB1Periph;
01224   }
01225   else
01226   {
01227     RCC->APB1RSTR &= ~RCC_APB1Periph;
01228   }
01229 }
01230
01231 /**
01232   * @brief  Forces or releases the Backup domain reset.
01233   * @param  NewState: new state of the Backup domain reset.
01234   *   This parameter can be: ENABLE or DISABLE.
01235   * @retval None
01236   */
01237 void RCC_BackupResetCmd(FunctionalState NewState)
01238 {
01239   /* Check the parameters */
01240   assert_param(IS_FUNCTIONAL_STATE(NewState));
01241   *(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState;
01242 }
01243
01244 /**
01245   * @brief  Enables or disables the Clock Security System.
01246   * @param  NewState: new state of the Clock Security System..
01247   *   This parameter can be: ENABLE or DISABLE.
01248   * @retval None
01249   */
01250 void RCC_ClockSecuritySystemCmd(FunctionalState NewState)
01251 {
01252   /* Check the parameters */
01253   assert_param(IS_FUNCTIONAL_STATE(NewState));
01254   *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState;
01255 }
01256
01257 /**
01258   * @brief  Selects the clock source to output on MCO pin.
01259   * @param  RCC_MCO: specifies the clock source to output.
01260   *
01261   *   For @b STM32_Connectivity_line_devices, this parameter can be one of the
01262   *   following values:
01263   *     @arg RCC_MCO_NoClock: No clock selected
01264   *     @arg RCC_MCO_SYSCLK: System clock selected
01265   *     @arg RCC_MCO_HSI: HSI oscillator clock selected
01266   *     @arg RCC_MCO_HSE: HSE oscillator clock selected
01267   *     @arg RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected
01268   *     @arg RCC_MCO_PLL2CLK: PLL2 clock selected
01269   *     @arg RCC_MCO_PLL3CLK_Div2: PLL3 clock divided by 2 selected
01270   *     @arg RCC_MCO_XT1: External 3-25 MHz oscillator clock selected
01271   *     @arg RCC_MCO_PLL3CLK: PLL3 clock selected
01272   *
01273   *   For  @b other_STM32_devices, this parameter can be one of the following values:
01274   *     @arg RCC_MCO_NoClock: No clock selected
01275   *     @arg RCC_MCO_SYSCLK: System clock selected
01276   *     @arg RCC_MCO_HSI: HSI oscillator clock selected
01277   *     @arg RCC_MCO_HSE: HSE oscillator clock selected
01278   *     @arg RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected
01279   *
01280   * @retval None
01281   */
01282 void RCC_MCOConfig(uint8_t RCC_MCO)
01283 {
01284   /* Check the parameters */
01285   assert_param(IS_RCC_MCO(RCC_MCO));
01286
01287   /* Perform Byte access to MCO bits to select the MCO source */
01288   *(__IO uint8_t *) CFGR_BYTE4_ADDRESS = RCC_MCO;
01289 }
01290
01291 /**
01292   * @brief  Checks whether the specified RCC flag is set or not.
01293   * @param  RCC_FLAG: specifies the flag to check.
01294   *
01295   *   For @b STM32_Connectivity_line_devices, this parameter can be one of the
01296   *   following values:
01297   *     @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
01298   *     @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
01299   *     @arg RCC_FLAG_PLLRDY: PLL clock ready
01300   *     @arg RCC_FLAG_PLL2RDY: PLL2 clock ready
01301   *     @arg RCC_FLAG_PLL3RDY: PLL3 clock ready
01302   *     @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
01303   *     @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
01304   *     @arg RCC_FLAG_PINRST: Pin reset
01305   *     @arg RCC_FLAG_PORRST: POR/PDR reset
01306   *     @arg RCC_FLAG_SFTRST: Software reset
01307   *     @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
01308   *     @arg RCC_FLAG_WWDGRST: Window Watchdog reset
01309   *     @arg RCC_FLAG_LPWRRST: Low Power reset
01310   *
01311   *   For @b other_STM32_devices, this parameter can be one of the following values:
01312   *     @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
01313   *     @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
01314   *     @arg RCC_FLAG_PLLRDY: PLL clock ready
01315   *     @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
01316   *     @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
01317   *     @arg RCC_FLAG_PINRST: Pin reset
01318   *     @arg RCC_FLAG_PORRST: POR/PDR reset
01319   *     @arg RCC_FLAG_SFTRST: Software reset
01320   *     @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
01321   *     @arg RCC_FLAG_WWDGRST: Window Watchdog reset
01322   *     @arg RCC_FLAG_LPWRRST: Low Power reset
01323   *
01324   * @retval The new state of RCC_FLAG (SET or RESET).
01325   */
01326 FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
01327 {
01328   uint32_t tmp = 0;
01329   uint32_t statusreg = 0;
01330   FlagStatus bitstatus = RESET;
01331   /* Check the parameters */
01332   assert_param(IS_RCC_FLAG(RCC_FLAG));
01333
01334   /* Get the RCC register index */
01335   tmp = RCC_FLAG >> 5;
01336   if (tmp == 1)               /* The flag to check is in CR register */
01337   {
01338     statusreg = RCC->CR;
01339   }
01340   else if (tmp == 2)          /* The flag to check is in BDCR register */
01341   {
01342     statusreg = RCC->BDCR;
01343   }
01344   else                       /* The flag to check is in CSR register */
01345   {
01346     statusreg = RCC->CSR;
01347   }
01348
01349   /* Get the flag position */
01350   tmp = RCC_FLAG & FLAG_Mask;
01351   if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)
01352   {
01353     bitstatus = SET;
01354   }
01355   else
01356   {
01357     bitstatus = RESET;
01358   }
01359
01360   /* Return the flag status */
01361   return bitstatus;
01362 }
01363
01364 /**
01365   * @brief  Clears the RCC reset flags.
01366   * @note   The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
01367   *   RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
01368   * @param  None
01369   * @retval None
01370   */
01371 void RCC_ClearFlag(void)
01372 {
01373   /* Set RMVF bit to clear the reset flags */
01374   RCC->CSR |= CSR_RMVF_Set;
01375 }
01376
01377 /**
01378   * @brief  Checks whether the specified RCC interrupt has occurred or not.
01379   * @param  RCC_IT: specifies the RCC interrupt source to check.
01380   *
01381   *   For @b STM32_Connectivity_line_devices, this parameter can be one of the
01382   *   following values:
01383   *     @arg RCC_IT_LSIRDY: LSI ready interrupt
01384   *     @arg RCC_IT_LSERDY: LSE ready interrupt
01385   *     @arg RCC_IT_HSIRDY: HSI ready interrupt
01386   *     @arg RCC_IT_HSERDY: HSE ready interrupt
01387   *     @arg RCC_IT_PLLRDY: PLL ready interrupt
01388   *     @arg RCC_IT_PLL2RDY: PLL2 ready interrupt
01389   *     @arg RCC_IT_PLL3RDY: PLL3 ready interrupt
01390   *     @arg RCC_IT_CSS: Clock Security System interrupt
01391   *
01392   *   For @b other_STM32_devices, this parameter can be one of the following values:
01393   *     @arg RCC_IT_LSIRDY: LSI ready interrupt
01394   *     @arg RCC_IT_LSERDY: LSE ready interrupt
01395   *     @arg RCC_IT_HSIRDY: HSI ready interrupt
01396   *     @arg RCC_IT_HSERDY: HSE ready interrupt
01397   *     @arg RCC_IT_PLLRDY: PLL ready interrupt
01398   *     @arg RCC_IT_CSS: Clock Security System interrupt
01399   *
01400   * @retval The new state of RCC_IT (SET or RESET).
01401   */
01402 ITStatus RCC_GetITStatus(uint8_t RCC_IT)
01403 {
01404   ITStatus bitstatus = RESET;
01405   /* Check the parameters */
01406   assert_param(IS_RCC_GET_IT(RCC_IT));
01407
01408   /* Check the status of the specified RCC interrupt */
01409   if ((RCC->CIR & RCC_IT) != (uint32_t)RESET)
01410   {
01411     bitstatus = SET;
01412   }
01413   else
01414   {
01415     bitstatus = RESET;
01416   }
01417
01418   /* Return the RCC_IT status */
01419   return  bitstatus;
01420 }
01421
01422 /**
01423   * @brief  Clears the RCC's interrupt pending bits.
01424   * @param  RCC_IT: specifies the interrupt pending bit to clear.
01425   *
01426   *   For @b STM32_Connectivity_line_devices, this parameter can be any combination
01427   *   of the following values:
01428   *     @arg RCC_IT_LSIRDY: LSI ready interrupt
01429   *     @arg RCC_IT_LSERDY: LSE ready interrupt
01430   *     @arg RCC_IT_HSIRDY: HSI ready interrupt
01431   *     @arg RCC_IT_HSERDY: HSE ready interrupt
01432   *     @arg RCC_IT_PLLRDY: PLL ready interrupt
01433   *     @arg RCC_IT_PLL2RDY: PLL2 ready interrupt
01434   *     @arg RCC_IT_PLL3RDY: PLL3 ready interrupt
01435   *     @arg RCC_IT_CSS: Clock Security System interrupt
01436   *
01437   *   For @b other_STM32_devices, this parameter can be any combination of the
01438   *   following values:
01439   *     @arg RCC_IT_LSIRDY: LSI ready interrupt
01440   *     @arg RCC_IT_LSERDY: LSE ready interrupt
01441   *     @arg RCC_IT_HSIRDY: HSI ready interrupt
01442   *     @arg RCC_IT_HSERDY: HSE ready interrupt
01443   *     @arg RCC_IT_PLLRDY: PLL ready interrupt
01444   *
01445   *     @arg RCC_IT_CSS: Clock Security System interrupt
01446   * @retval None
01447   */
01448 void RCC_ClearITPendingBit(uint8_t RCC_IT)
01449 {
01450   /* Check the parameters */
01451   assert_param(IS_RCC_CLEAR_IT(RCC_IT));
01452
01453   /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt
01454      pending bits */
01455   *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT;
01456 }
01457
01458 /**
01459   * @}
01460   */
01461
01462 /**
01463   * @}
01464   */
01465
01466 /**
01467   * @}
01468   */
01469
01470 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_rcc.h Source File

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stm32f10x_rcc.h

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f10x_rcc.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    11-March-2011
00007   * @brief   This file contains all the functions prototypes for the RCC firmware
00008   *          library.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00013   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00014   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00015   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00016   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00017   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00018   *
00019   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00020   ******************************************************************************
00021   */
00022
00023 /* Define to prevent recursive inclusion -------------------------------------*/
00024 #ifndef __STM32F10x_RCC_H
00025 #define __STM32F10x_RCC_H
00026
00027 #ifdef __cplusplus
00028  extern "C" {
00029 #endif
00030
00031 /* Includes ------------------------------------------------------------------*/
00032 #include "stm32f10x.h"
00033
00034 /** @addtogroup STM32F10x_StdPeriph_Driver
00035   * @{
00036   */
00037
00038 /** @addtogroup RCC
00039   * @{
00040   */
00041
00042 /** @defgroup RCC_Exported_Types
00043   * @{
00044   */
00045
00046 typedef struct
00047 {
00048   uint32_t SYSCLK_Frequency;  /*!< returns SYSCLK clock frequency expressed in Hz */
00049   uint32_t HCLK_Frequency;    /*!< returns HCLK clock frequency expressed in Hz */
00050   uint32_t PCLK1_Frequency;   /*!< returns PCLK1 clock frequency expressed in Hz */
00051   uint32_t PCLK2_Frequency;   /*!< returns PCLK2 clock frequency expressed in Hz */
00052   uint32_t ADCCLK_Frequency;  /*!< returns ADCCLK clock frequency expressed in Hz */
00053 }RCC_ClocksTypeDef;
00054
00055 /**
00056   * @}
00057   */
00058
00059 /** @defgroup RCC_Exported_Constants
00060   * @{
00061   */
00062
00063 /** @defgroup HSE_configuration
00064   * @{
00065   */
00066
00067 #define RCC_HSE_OFF                      ((uint32_t)0x00000000)
00068 #define RCC_HSE_ON                       ((uint32_t)0x00010000)
00069 #define RCC_HSE_Bypass                   ((uint32_t)0x00040000)
00070 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
00071                          ((HSE) == RCC_HSE_Bypass))
00072
00073 /**
00074   * @}
00075   */
00076
00077 /** @defgroup PLL_entry_clock_source
00078   * @{
00079   */
00080
00081 #define RCC_PLLSource_HSI_Div2           ((uint32_t)0x00000000)
00082
00083 #if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_CL)
00084  #define RCC_PLLSource_HSE_Div1           ((uint32_t)0x00010000)
00085  #define RCC_PLLSource_HSE_Div2           ((uint32_t)0x00030000)
00086  #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \
00087                                    ((SOURCE) == RCC_PLLSource_HSE_Div1) || \
00088                                    ((SOURCE) == RCC_PLLSource_HSE_Div2))
00089 #else
00090  #define RCC_PLLSource_PREDIV1            ((uint32_t)0x00010000)
00091  #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \
00092                                    ((SOURCE) == RCC_PLLSource_PREDIV1))
00093 #endif /* STM32F10X_CL */
00094
00095 /**
00096   * @}
00097   */
00098
00099 /** @defgroup PLL_multiplication_factor
00100   * @{
00101   */
00102 #ifndef STM32F10X_CL
00103  #define RCC_PLLMul_2                    ((uint32_t)0x00000000)
00104  #define RCC_PLLMul_3                    ((uint32_t)0x00040000)
00105  #define RCC_PLLMul_4                    ((uint32_t)0x00080000)
00106  #define RCC_PLLMul_5                    ((uint32_t)0x000C0000)
00107  #define RCC_PLLMul_6                    ((uint32_t)0x00100000)
00108  #define RCC_PLLMul_7                    ((uint32_t)0x00140000)
00109  #define RCC_PLLMul_8                    ((uint32_t)0x00180000)
00110  #define RCC_PLLMul_9                    ((uint32_t)0x001C0000)
00111  #define RCC_PLLMul_10                   ((uint32_t)0x00200000)
00112  #define RCC_PLLMul_11                   ((uint32_t)0x00240000)
00113  #define RCC_PLLMul_12                   ((uint32_t)0x00280000)
00114  #define RCC_PLLMul_13                   ((uint32_t)0x002C0000)
00115  #define RCC_PLLMul_14                   ((uint32_t)0x00300000)
00116  #define RCC_PLLMul_15                   ((uint32_t)0x00340000)
00117  #define RCC_PLLMul_16                   ((uint32_t)0x00380000)
00118  #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3)   || \
00119                               ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5)   || \
00120                               ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7)   || \
00121                               ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9)   || \
00122                               ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \
00123                               ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \
00124                               ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \
00125                               ((MUL) == RCC_PLLMul_16))
00126
00127 #else
00128  #define RCC_PLLMul_4                    ((uint32_t)0x00080000)
00129  #define RCC_PLLMul_5                    ((uint32_t)0x000C0000)
00130  #define RCC_PLLMul_6                    ((uint32_t)0x00100000)
00131  #define RCC_PLLMul_7                    ((uint32_t)0x00140000)
00132  #define RCC_PLLMul_8                    ((uint32_t)0x00180000)
00133  #define RCC_PLLMul_9                    ((uint32_t)0x001C0000)
00134  #define RCC_PLLMul_6_5                  ((uint32_t)0x00340000)
00135
00136  #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \
00137                               ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \
00138                               ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \
00139                               ((MUL) == RCC_PLLMul_6_5))
00140 #endif /* STM32F10X_CL */
00141 /**
00142   * @}
00143   */
00144
00145 /** @defgroup PREDIV1_division_factor
00146   * @{
00147   */
00148 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL)
00149  #define  RCC_PREDIV1_Div1               ((uint32_t)0x00000000)
00150  #define  RCC_PREDIV1_Div2               ((uint32_t)0x00000001)
00151  #define  RCC_PREDIV1_Div3               ((uint32_t)0x00000002)
00152  #define  RCC_PREDIV1_Div4               ((uint32_t)0x00000003)
00153  #define  RCC_PREDIV1_Div5               ((uint32_t)0x00000004)
00154  #define  RCC_PREDIV1_Div6               ((uint32_t)0x00000005)
00155  #define  RCC_PREDIV1_Div7               ((uint32_t)0x00000006)
00156  #define  RCC_PREDIV1_Div8               ((uint32_t)0x00000007)
00157  #define  RCC_PREDIV1_Div9               ((uint32_t)0x00000008)
00158  #define  RCC_PREDIV1_Div10              ((uint32_t)0x00000009)
00159  #define  RCC_PREDIV1_Div11              ((uint32_t)0x0000000A)
00160  #define  RCC_PREDIV1_Div12              ((uint32_t)0x0000000B)
00161  #define  RCC_PREDIV1_Div13              ((uint32_t)0x0000000C)
00162  #define  RCC_PREDIV1_Div14              ((uint32_t)0x0000000D)
00163  #define  RCC_PREDIV1_Div15              ((uint32_t)0x0000000E)
00164  #define  RCC_PREDIV1_Div16              ((uint32_t)0x0000000F)
00165
00166  #define IS_RCC_PREDIV1(PREDIV1) (((PREDIV1) == RCC_PREDIV1_Div1) || ((PREDIV1) == RCC_PREDIV1_Div2) || \
00167                                   ((PREDIV1) == RCC_PREDIV1_Div3) || ((PREDIV1) == RCC_PREDIV1_Div4) || \
00168                                   ((PREDIV1) == RCC_PREDIV1_Div5) || ((PREDIV1) == RCC_PREDIV1_Div6) || \
00169                                   ((PREDIV1) == RCC_PREDIV1_Div7) || ((PREDIV1) == RCC_PREDIV1_Div8) || \
00170                                   ((PREDIV1) == RCC_PREDIV1_Div9) || ((PREDIV1) == RCC_PREDIV1_Div10) || \
00171                                   ((PREDIV1) == RCC_PREDIV1_Div11) || ((PREDIV1) == RCC_PREDIV1_Div12) || \
00172                                   ((PREDIV1) == RCC_PREDIV1_Div13) || ((PREDIV1) == RCC_PREDIV1_Div14) || \
00173                                   ((PREDIV1) == RCC_PREDIV1_Div15) || ((PREDIV1) == RCC_PREDIV1_Div16))
00174 #endif
00175 /**
00176   * @}
00177   */
00178
00179
00180 /** @defgroup PREDIV1_clock_source
00181   * @{
00182   */
00183 #ifdef STM32F10X_CL
00184 /* PREDIV1 clock source (for STM32 connectivity line devices) */
00185  #define  RCC_PREDIV1_Source_HSE         ((uint32_t)0x00000000)
00186  #define  RCC_PREDIV1_Source_PLL2        ((uint32_t)0x00010000)
00187
00188  #define IS_RCC_PREDIV1_SOURCE(SOURCE) (((SOURCE) == RCC_PREDIV1_Source_HSE) || \
00189                                         ((SOURCE) == RCC_PREDIV1_Source_PLL2))
00190 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00191 /* PREDIV1 clock source (for STM32 Value line devices) */
00192  #define  RCC_PREDIV1_Source_HSE         ((uint32_t)0x00000000)
00193
00194  #define IS_RCC_PREDIV1_SOURCE(SOURCE) (((SOURCE) == RCC_PREDIV1_Source_HSE))
00195 #endif
00196 /**
00197   * @}
00198   */
00199
00200 #ifdef STM32F10X_CL
00201 /** @defgroup PREDIV2_division_factor
00202   * @{
00203   */
00204
00205  #define  RCC_PREDIV2_Div1               ((uint32_t)0x00000000)
00206  #define  RCC_PREDIV2_Div2               ((uint32_t)0x00000010)
00207  #define  RCC_PREDIV2_Div3               ((uint32_t)0x00000020)
00208  #define  RCC_PREDIV2_Div4               ((uint32_t)0x00000030)
00209  #define  RCC_PREDIV2_Div5               ((uint32_t)0x00000040)
00210  #define  RCC_PREDIV2_Div6               ((uint32_t)0x00000050)
00211  #define  RCC_PREDIV2_Div7               ((uint32_t)0x00000060)
00212  #define  RCC_PREDIV2_Div8               ((uint32_t)0x00000070)
00213  #define  RCC_PREDIV2_Div9               ((uint32_t)0x00000080)
00214  #define  RCC_PREDIV2_Div10              ((uint32_t)0x00000090)
00215  #define  RCC_PREDIV2_Div11              ((uint32_t)0x000000A0)
00216  #define  RCC_PREDIV2_Div12              ((uint32_t)0x000000B0)
00217  #define  RCC_PREDIV2_Div13              ((uint32_t)0x000000C0)
00218  #define  RCC_PREDIV2_Div14              ((uint32_t)0x000000D0)
00219  #define  RCC_PREDIV2_Div15              ((uint32_t)0x000000E0)
00220  #define  RCC_PREDIV2_Div16              ((uint32_t)0x000000F0)
00221
00222  #define IS_RCC_PREDIV2(PREDIV2) (((PREDIV2) == RCC_PREDIV2_Div1) || ((PREDIV2) == RCC_PREDIV2_Div2) || \
00223                                   ((PREDIV2) == RCC_PREDIV2_Div3) || ((PREDIV2) == RCC_PREDIV2_Div4) || \
00224                                   ((PREDIV2) == RCC_PREDIV2_Div5) || ((PREDIV2) == RCC_PREDIV2_Div6) || \
00225                                   ((PREDIV2) == RCC_PREDIV2_Div7) || ((PREDIV2) == RCC_PREDIV2_Div8) || \
00226                                   ((PREDIV2) == RCC_PREDIV2_Div9) || ((PREDIV2) == RCC_PREDIV2_Div10) || \
00227                                   ((PREDIV2) == RCC_PREDIV2_Div11) || ((PREDIV2) == RCC_PREDIV2_Div12) || \
00228                                   ((PREDIV2) == RCC_PREDIV2_Div13) || ((PREDIV2) == RCC_PREDIV2_Div14) || \
00229                                   ((PREDIV2) == RCC_PREDIV2_Div15) || ((PREDIV2) == RCC_PREDIV2_Div16))
00230 /**
00231   * @}
00232   */
00233
00234
00235 /** @defgroup PLL2_multiplication_factor
00236   * @{
00237   */
00238
00239  #define  RCC_PLL2Mul_8                  ((uint32_t)0x00000600)
00240  #define  RCC_PLL2Mul_9                  ((uint32_t)0x00000700)
00241  #define  RCC_PLL2Mul_10                 ((uint32_t)0x00000800)
00242  #define  RCC_PLL2Mul_11                 ((uint32_t)0x00000900)
00243  #define  RCC_PLL2Mul_12                 ((uint32_t)0x00000A00)
00244  #define  RCC_PLL2Mul_13                 ((uint32_t)0x00000B00)
00245  #define  RCC_PLL2Mul_14                 ((uint32_t)0x00000C00)
00246  #define  RCC_PLL2Mul_16                 ((uint32_t)0x00000E00)
00247  #define  RCC_PLL2Mul_20                 ((uint32_t)0x00000F00)
00248
00249  #define IS_RCC_PLL2_MUL(MUL) (((MUL) == RCC_PLL2Mul_8) || ((MUL) == RCC_PLL2Mul_9)  || \
00250                                ((MUL) == RCC_PLL2Mul_10) || ((MUL) == RCC_PLL2Mul_11) || \
00251                                ((MUL) == RCC_PLL2Mul_12) || ((MUL) == RCC_PLL2Mul_13) || \
00252                                ((MUL) == RCC_PLL2Mul_14) || ((MUL) == RCC_PLL2Mul_16) || \
00253                                ((MUL) == RCC_PLL2Mul_20))
00254 /**
00255   * @}
00256   */
00257
00258
00259 /** @defgroup PLL3_multiplication_factor
00260   * @{
00261   */
00262
00263  #define  RCC_PLL3Mul_8                  ((uint32_t)0x00006000)
00264  #define  RCC_PLL3Mul_9                  ((uint32_t)0x00007000)
00265  #define  RCC_PLL3Mul_10                 ((uint32_t)0x00008000)
00266  #define  RCC_PLL3Mul_11                 ((uint32_t)0x00009000)
00267  #define  RCC_PLL3Mul_12                 ((uint32_t)0x0000A000)
00268  #define  RCC_PLL3Mul_13                 ((uint32_t)0x0000B000)
00269  #define  RCC_PLL3Mul_14                 ((uint32_t)0x0000C000)
00270  #define  RCC_PLL3Mul_16                 ((uint32_t)0x0000E000)
00271  #define  RCC_PLL3Mul_20                 ((uint32_t)0x0000F000)
00272
00273  #define IS_RCC_PLL3_MUL(MUL) (((MUL) == RCC_PLL3Mul_8) || ((MUL) == RCC_PLL3Mul_9)  || \
00274                                ((MUL) == RCC_PLL3Mul_10) || ((MUL) == RCC_PLL3Mul_11) || \
00275                                ((MUL) == RCC_PLL3Mul_12) || ((MUL) == RCC_PLL3Mul_13) || \
00276                                ((MUL) == RCC_PLL3Mul_14) || ((MUL) == RCC_PLL3Mul_16) || \
00277                                ((MUL) == RCC_PLL3Mul_20))
00278 /**
00279   * @}
00280   */
00281
00282 #endif /* STM32F10X_CL */
00283
00284
00285 /** @defgroup System_clock_source
00286   * @{
00287   */
00288
00289 #define RCC_SYSCLKSource_HSI             ((uint32_t)0x00000000)
00290 #define RCC_SYSCLKSource_HSE             ((uint32_t)0x00000001)
00291 #define RCC_SYSCLKSource_PLLCLK          ((uint32_t)0x00000002)
00292 #define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
00293                                       ((SOURCE) == RCC_SYSCLKSource_HSE) || \
00294                                       ((SOURCE) == RCC_SYSCLKSource_PLLCLK))
00295 /**
00296   * @}
00297   */
00298
00299 /** @defgroup AHB_clock_source
00300   * @{
00301   */
00302
00303 #define RCC_SYSCLK_Div1                  ((uint32_t)0x00000000)
00304 #define RCC_SYSCLK_Div2                  ((uint32_t)0x00000080)
00305 #define RCC_SYSCLK_Div4                  ((uint32_t)0x00000090)
00306 #define RCC_SYSCLK_Div8                  ((uint32_t)0x000000A0)
00307 #define RCC_SYSCLK_Div16                 ((uint32_t)0x000000B0)
00308 #define RCC_SYSCLK_Div64                 ((uint32_t)0x000000C0)
00309 #define RCC_SYSCLK_Div128                ((uint32_t)0x000000D0)
00310 #define RCC_SYSCLK_Div256                ((uint32_t)0x000000E0)
00311 #define RCC_SYSCLK_Div512                ((uint32_t)0x000000F0)
00312 #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
00313                            ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \
00314                            ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \
00315                            ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \
00316                            ((HCLK) == RCC_SYSCLK_Div512))
00317 /**
00318   * @}
00319   */
00320
00321 /** @defgroup APB1_APB2_clock_source
00322   * @{
00323   */
00324
00325 #define RCC_HCLK_Div1                    ((uint32_t)0x00000000)
00326 #define RCC_HCLK_Div2                    ((uint32_t)0x00000400)
00327 #define RCC_HCLK_Div4                    ((uint32_t)0x00000500)
00328 #define RCC_HCLK_Div8                    ((uint32_t)0x00000600)
00329 #define RCC_HCLK_Div16                   ((uint32_t)0x00000700)
00330 #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
00331                            ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \
00332                            ((PCLK) == RCC_HCLK_Div16))
00333 /**
00334   * @}
00335   */
00336
00337 /** @defgroup RCC_Interrupt_source
00338   * @{
00339   */
00340
00341 #define RCC_IT_LSIRDY                    ((uint8_t)0x01)
00342 #define RCC_IT_LSERDY                    ((uint8_t)0x02)
00343 #define RCC_IT_HSIRDY                    ((uint8_t)0x04)
00344 #define RCC_IT_HSERDY                    ((uint8_t)0x08)
00345 #define RCC_IT_PLLRDY                    ((uint8_t)0x10)
00346 #define RCC_IT_CSS                       ((uint8_t)0x80)
00347
00348 #ifndef STM32F10X_CL
00349  #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xE0) == 0x00) && ((IT) != 0x00))
00350  #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
00351                             ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
00352                             ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS))
00353  #define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x60) == 0x00) && ((IT) != 0x00))
00354 #else
00355  #define RCC_IT_PLL2RDY                  ((uint8_t)0x20)
00356  #define RCC_IT_PLL3RDY                  ((uint8_t)0x40)
00357  #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00))
00358  #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
00359                             ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
00360                             ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \
00361                             ((IT) == RCC_IT_PLL2RDY) || ((IT) == RCC_IT_PLL3RDY))
00362  #define IS_RCC_CLEAR_IT(IT) ((IT) != 0x00)
00363 #endif /* STM32F10X_CL */
00364
00365
00366 /**
00367   * @}
00368   */
00369
00370 #ifndef STM32F10X_CL
00371 /** @defgroup USB_Device_clock_source
00372   * @{
00373   */
00374
00375  #define RCC_USBCLKSource_PLLCLK_1Div5   ((uint8_t)0x00)
00376  #define RCC_USBCLKSource_PLLCLK_Div1    ((uint8_t)0x01)
00377
00378  #define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_1Div5) || \
00379                                       ((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1))
00380 /**
00381   * @}
00382   */
00383 #else
00384 /** @defgroup USB_OTG_FS_clock_source
00385   * @{
00386   */
00387  #define RCC_OTGFSCLKSource_PLLVCO_Div3    ((uint8_t)0x00)
00388  #define RCC_OTGFSCLKSource_PLLVCO_Div2    ((uint8_t)0x01)
00389
00390  #define IS_RCC_OTGFSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div3) || \
00391                                          ((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div2))
00392 /**
00393   * @}
00394   */
00395 #endif /* STM32F10X_CL */
00396
00397
00398 #ifdef STM32F10X_CL
00399 /** @defgroup I2S2_clock_source
00400   * @{
00401   */
00402  #define RCC_I2S2CLKSource_SYSCLK        ((uint8_t)0x00)
00403  #define RCC_I2S2CLKSource_PLL3_VCO      ((uint8_t)0x01)
00404
00405  #define IS_RCC_I2S2CLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_SYSCLK) || \
00406                                         ((SOURCE) == RCC_I2S2CLKSource_PLL3_VCO))
00407 /**
00408   * @}
00409   */
00410
00411 /** @defgroup I2S3_clock_source
00412   * @{
00413   */
00414  #define RCC_I2S3CLKSource_SYSCLK        ((uint8_t)0x00)
00415  #define RCC_I2S3CLKSource_PLL3_VCO      ((uint8_t)0x01)
00416
00417  #define IS_RCC_I2S3CLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S3CLKSource_SYSCLK) || \
00418                                         ((SOURCE) == RCC_I2S3CLKSource_PLL3_VCO))
00419 /**
00420   * @}
00421   */
00422 #endif /* STM32F10X_CL */
00423
00424
00425 /** @defgroup ADC_clock_source
00426   * @{
00427   */
00428
00429 #define RCC_PCLK2_Div2                   ((uint32_t)0x00000000)
00430 #define RCC_PCLK2_Div4                   ((uint32_t)0x00004000)
00431 #define RCC_PCLK2_Div6                   ((uint32_t)0x00008000)
00432 #define RCC_PCLK2_Div8                   ((uint32_t)0x0000C000)
00433 #define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_PCLK2_Div2) || ((ADCCLK) == RCC_PCLK2_Div4) || \
00434                                ((ADCCLK) == RCC_PCLK2_Div6) || ((ADCCLK) == RCC_PCLK2_Div8))
00435 /**
00436   * @}
00437   */
00438
00439 /** @defgroup LSE_configuration
00440   * @{
00441   */
00442
00443 #define RCC_LSE_OFF                      ((uint8_t)0x00)
00444 #define RCC_LSE_ON                       ((uint8_t)0x01)
00445 #define RCC_LSE_Bypass                   ((uint8_t)0x04)
00446 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
00447                          ((LSE) == RCC_LSE_Bypass))
00448 /**
00449   * @}
00450   */
00451
00452 /** @defgroup RTC_clock_source
00453   * @{
00454   */
00455
00456 #define RCC_RTCCLKSource_LSE             ((uint32_t)0x00000100)
00457 #define RCC_RTCCLKSource_LSI             ((uint32_t)0x00000200)
00458 #define RCC_RTCCLKSource_HSE_Div128      ((uint32_t)0x00000300)
00459 #define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \
00460                                       ((SOURCE) == RCC_RTCCLKSource_LSI) || \
00461                                       ((SOURCE) == RCC_RTCCLKSource_HSE_Div128))
00462 /**
00463   * @}
00464   */
00465
00466 /** @defgroup AHB_peripheral
00467   * @{
00468   */
00469
00470 #define RCC_AHBPeriph_DMA1               ((uint32_t)0x00000001)
00471 #define RCC_AHBPeriph_DMA2               ((uint32_t)0x00000002)
00472 #define RCC_AHBPeriph_SRAM               ((uint32_t)0x00000004)
00473 #define RCC_AHBPeriph_FLITF              ((uint32_t)0x00000010)
00474 #define RCC_AHBPeriph_CRC                ((uint32_t)0x00000040)
00475
00476 #ifndef STM32F10X_CL
00477  #define RCC_AHBPeriph_FSMC              ((uint32_t)0x00000100)
00478  #define RCC_AHBPeriph_SDIO              ((uint32_t)0x00000400)
00479  #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFAA8) == 0x00) && ((PERIPH) != 0x00))
00480 #else
00481  #define RCC_AHBPeriph_OTG_FS            ((uint32_t)0x00001000)
00482  #define RCC_AHBPeriph_ETH_MAC           ((uint32_t)0x00004000)
00483  #define RCC_AHBPeriph_ETH_MAC_Tx        ((uint32_t)0x00008000)
00484  #define RCC_AHBPeriph_ETH_MAC_Rx        ((uint32_t)0x00010000)
00485
00486  #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFE2FA8) == 0x00) && ((PERIPH) != 0x00))
00487  #define IS_RCC_AHB_PERIPH_RESET(PERIPH) ((((PERIPH) & 0xFFFFAFFF) == 0x00) && ((PERIPH) != 0x00))
00488 #endif /* STM32F10X_CL */
00489 /**
00490   * @}
00491   */
00492
00493 /** @defgroup APB2_peripheral
00494   * @{
00495   */
00496
00497 #define RCC_APB2Periph_AFIO              ((uint32_t)0x00000001)
00498 #define RCC_APB2Periph_GPIOA             ((uint32_t)0x00000004)
00499 #define RCC_APB2Periph_GPIOB             ((uint32_t)0x00000008)
00500 #define RCC_APB2Periph_GPIOC             ((uint32_t)0x00000010)
00501 #define RCC_APB2Periph_GPIOD             ((uint32_t)0x00000020)
00502 #define RCC_APB2Periph_GPIOE             ((uint32_t)0x00000040)
00503 #define RCC_APB2Periph_GPIOF             ((uint32_t)0x00000080)
00504 #define RCC_APB2Periph_GPIOG             ((uint32_t)0x00000100)
00505 #define RCC_APB2Periph_ADC1              ((uint32_t)0x00000200)
00506 #define RCC_APB2Periph_ADC2              ((uint32_t)0x00000400)
00507 #define RCC_APB2Periph_TIM1              ((uint32_t)0x00000800)
00508 #define RCC_APB2Periph_SPI1              ((uint32_t)0x00001000)
00509 #define RCC_APB2Periph_TIM8              ((uint32_t)0x00002000)
00510 #define RCC_APB2Periph_USART1            ((uint32_t)0x00004000)
00511 #define RCC_APB2Periph_ADC3              ((uint32_t)0x00008000)
00512 #define RCC_APB2Periph_TIM15             ((uint32_t)0x00010000)
00513 #define RCC_APB2Periph_TIM16             ((uint32_t)0x00020000)
00514 #define RCC_APB2Periph_TIM17             ((uint32_t)0x00040000)
00515 #define RCC_APB2Periph_TIM9              ((uint32_t)0x00080000)
00516 #define RCC_APB2Periph_TIM10             ((uint32_t)0x00100000)
00517 #define RCC_APB2Periph_TIM11             ((uint32_t)0x00200000)
00518
00519 #define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFC00002) == 0x00) && ((PERIPH) != 0x00))
00520 /**
00521   * @}
00522   */
00523
00524 /** @defgroup APB1_peripheral
00525   * @{
00526   */
00527
00528 #define RCC_APB1Periph_TIM2              ((uint32_t)0x00000001)
00529 #define RCC_APB1Periph_TIM3              ((uint32_t)0x00000002)
00530 #define RCC_APB1Periph_TIM4              ((uint32_t)0x00000004)
00531 #define RCC_APB1Periph_TIM5              ((uint32_t)0x00000008)
00532 #define RCC_APB1Periph_TIM6              ((uint32_t)0x00000010)
00533 #define RCC_APB1Periph_TIM7              ((uint32_t)0x00000020)
00534 #define RCC_APB1Periph_TIM12             ((uint32_t)0x00000040)
00535 #define RCC_APB1Periph_TIM13             ((uint32_t)0x00000080)
00536 #define RCC_APB1Periph_TIM14             ((uint32_t)0x00000100)
00537 #define RCC_APB1Periph_WWDG              ((uint32_t)0x00000800)
00538 #define RCC_APB1Periph_SPI2              ((uint32_t)0x00004000)
00539 #define RCC_APB1Periph_SPI3              ((uint32_t)0x00008000)
00540 #define RCC_APB1Periph_USART2            ((uint32_t)0x00020000)
00541 #define RCC_APB1Periph_USART3            ((uint32_t)0x00040000)
00542 #define RCC_APB1Periph_UART4             ((uint32_t)0x00080000)
00543 #define RCC_APB1Periph_UART5             ((uint32_t)0x00100000)
00544 #define RCC_APB1Periph_I2C1              ((uint32_t)0x00200000)
00545 #define RCC_APB1Periph_I2C2              ((uint32_t)0x00400000)
00546 #define RCC_APB1Periph_USB               ((uint32_t)0x00800000)
00547 #define RCC_APB1Periph_CAN1              ((uint32_t)0x02000000)
00548 #define RCC_APB1Periph_CAN2              ((uint32_t)0x04000000)
00549 #define RCC_APB1Periph_BKP               ((uint32_t)0x08000000)
00550 #define RCC_APB1Periph_PWR               ((uint32_t)0x10000000)
00551 #define RCC_APB1Periph_DAC               ((uint32_t)0x20000000)
00552 #define RCC_APB1Periph_CEC               ((uint32_t)0x40000000)
00553
00554 #define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x81013600) == 0x00) && ((PERIPH) != 0x00))
00555
00556 /**
00557   * @}
00558   */
00559
00560 /** @defgroup Clock_source_to_output_on_MCO_pin
00561   * @{
00562   */
00563
00564 #define RCC_MCO_NoClock                  ((uint8_t)0x00)
00565 #define RCC_MCO_SYSCLK                   ((uint8_t)0x04)
00566 #define RCC_MCO_HSI                      ((uint8_t)0x05)
00567 #define RCC_MCO_HSE                      ((uint8_t)0x06)
00568 #define RCC_MCO_PLLCLK_Div2              ((uint8_t)0x07)
00569
00570 #ifndef STM32F10X_CL
00571  #define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \
00572                           ((MCO) == RCC_MCO_SYSCLK)  || ((MCO) == RCC_MCO_HSE) || \
00573                           ((MCO) == RCC_MCO_PLLCLK_Div2))
00574 #else
00575  #define RCC_MCO_PLL2CLK                 ((uint8_t)0x08)
00576  #define RCC_MCO_PLL3CLK_Div2            ((uint8_t)0x09)
00577  #define RCC_MCO_XT1                     ((uint8_t)0x0A)
00578  #define RCC_MCO_PLL3CLK                 ((uint8_t)0x0B)
00579
00580  #define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \
00581                           ((MCO) == RCC_MCO_SYSCLK)  || ((MCO) == RCC_MCO_HSE) || \
00582                           ((MCO) == RCC_MCO_PLLCLK_Div2) || ((MCO) == RCC_MCO_PLL2CLK) || \
00583                           ((MCO) == RCC_MCO_PLL3CLK_Div2) || ((MCO) == RCC_MCO_XT1) || \
00584                           ((MCO) == RCC_MCO_PLL3CLK))
00585 #endif /* STM32F10X_CL */
00586
00587 /**
00588   * @}
00589   */
00590
00591 /** @defgroup RCC_Flag
00592   * @{
00593   */
00594
00595 #define RCC_FLAG_HSIRDY                  ((uint8_t)0x21)
00596 #define RCC_FLAG_HSERDY                  ((uint8_t)0x31)
00597 #define RCC_FLAG_PLLRDY                  ((uint8_t)0x39)
00598 #define RCC_FLAG_LSERDY                  ((uint8_t)0x41)
00599 #define RCC_FLAG_LSIRDY                  ((uint8_t)0x61)
00600 #define RCC_FLAG_PINRST                  ((uint8_t)0x7A)
00601 #define RCC_FLAG_PORRST                  ((uint8_t)0x7B)
00602 #define RCC_FLAG_SFTRST                  ((uint8_t)0x7C)
00603 #define RCC_FLAG_IWDGRST                 ((uint8_t)0x7D)
00604 #define RCC_FLAG_WWDGRST                 ((uint8_t)0x7E)
00605 #define RCC_FLAG_LPWRRST                 ((uint8_t)0x7F)
00606
00607 #ifndef STM32F10X_CL
00608  #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
00609                             ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
00610                             ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \
00611                             ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \
00612                             ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \
00613                             ((FLAG) == RCC_FLAG_LPWRRST))
00614 #else
00615  #define RCC_FLAG_PLL2RDY                ((uint8_t)0x3B)
00616  #define RCC_FLAG_PLL3RDY                ((uint8_t)0x3D)
00617  #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
00618                             ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
00619                             ((FLAG) == RCC_FLAG_PLL2RDY) || ((FLAG) == RCC_FLAG_PLL3RDY) || \
00620                             ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \
00621                             ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \
00622                             ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \
00623                             ((FLAG) == RCC_FLAG_LPWRRST))
00624 #endif /* STM32F10X_CL */
00625
00626 #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
00627 /**
00628   * @}
00629   */
00630
00631 /**
00632   * @}
00633   */
00634
00635 /** @defgroup RCC_Exported_Macros
00636   * @{
00637   */
00638
00639 /**
00640   * @}
00641   */
00642
00643 /** @defgroup RCC_Exported_Functions
00644   * @{
00645   */
00646
00647 void RCC_DeInit(void);
00648 void RCC_HSEConfig(uint32_t RCC_HSE);
00649 ErrorStatus RCC_WaitForHSEStartUp(void);
00650 void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
00651 void RCC_HSICmd(FunctionalState NewState);
00652 void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul);
00653 void RCC_PLLCmd(FunctionalState NewState);
00654
00655 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL)
00656  void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div);
00657 #endif
00658
00659 #ifdef  STM32F10X_CL
00660  void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div);
00661  void RCC_PLL2Config(uint32_t RCC_PLL2Mul);
00662  void RCC_PLL2Cmd(FunctionalState NewState);
00663  void RCC_PLL3Config(uint32_t RCC_PLL3Mul);
00664  void RCC_PLL3Cmd(FunctionalState NewState);
00665 #endif /* STM32F10X_CL */
00666
00667 void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
00668 uint8_t RCC_GetSYSCLKSource(void);
00669 void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
00670 void RCC_PCLK1Config(uint32_t RCC_HCLK);
00671 void RCC_PCLK2Config(uint32_t RCC_HCLK);
00672 void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
00673
00674 #ifndef STM32F10X_CL
00675  void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource);
00676 #else
00677  void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource);
00678 #endif /* STM32F10X_CL */
00679
00680 void RCC_ADCCLKConfig(uint32_t RCC_PCLK2);
00681
00682 #ifdef STM32F10X_CL
00683  void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource);
00684  void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource);
00685 #endif /* STM32F10X_CL */
00686
00687 void RCC_LSEConfig(uint8_t RCC_LSE);
00688 void RCC_LSICmd(FunctionalState NewState);
00689 void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
00690 void RCC_RTCCLKCmd(FunctionalState NewState);
00691 void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
00692 void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
00693 void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
00694 void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
00695
00696 #ifdef STM32F10X_CL
00697 void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
00698 #endif /* STM32F10X_CL */
00699
00700 void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
00701 void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
00702 void RCC_BackupResetCmd(FunctionalState NewState);
00703 void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
00704 void RCC_MCOConfig(uint8_t RCC_MCO);
00705 FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
00706 void RCC_ClearFlag(void);
00707 ITStatus RCC_GetITStatus(uint8_t RCC_IT);
00708 void RCC_ClearITPendingBit(uint8_t RCC_IT);
00709
00710 #ifdef __cplusplus
00711 }
00712 #endif
00713
00714 #endif /* __STM32F10x_RCC_H */
00715 /**
00716   * @}
00717   */
00718
00719 /**
00720   * @}
00721   */
00722
00723 /**
00724   * @}
00725   */
00726
00727 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_rtc.c Source File

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  • src

stm32f10x_rtc.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32f10x_rtc.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    11-March-2011
00007   * @brief   This file provides all the RTC firmware functions.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x_rtc.h"
00024
00025 /** @addtogroup STM32F10x_StdPeriph_Driver
00026   * @{
00027   */
00028
00029 /** @defgroup RTC
00030   * @brief RTC driver modules
00031   * @{
00032   */
00033
00034 /** @defgroup RTC_Private_TypesDefinitions
00035   * @{
00036   */
00037 /**
00038   * @}
00039   */
00040
00041 /** @defgroup RTC_Private_Defines
00042   * @{
00043   */
00044 #define RTC_LSB_MASK     ((uint32_t)0x0000FFFF)  /*!< RTC LSB Mask */
00045 #define PRLH_MSB_MASK    ((uint32_t)0x000F0000)  /*!< RTC Prescaler MSB Mask */
00046
00047 /**
00048   * @}
00049   */
00050
00051 /** @defgroup RTC_Private_Macros
00052   * @{
00053   */
00054
00055 /**
00056   * @}
00057   */
00058
00059 /** @defgroup RTC_Private_Variables
00060   * @{
00061   */
00062
00063 /**
00064   * @}
00065   */
00066
00067 /** @defgroup RTC_Private_FunctionPrototypes
00068   * @{
00069   */
00070
00071 /**
00072   * @}
00073   */
00074
00075 /** @defgroup RTC_Private_Functions
00076   * @{
00077   */
00078
00079 /**
00080   * @brief  Enables or disables the specified RTC interrupts.
00081   * @param  RTC_IT: specifies the RTC interrupts sources to be enabled or disabled.
00082   *   This parameter can be any combination of the following values:
00083   *     @arg RTC_IT_OW: Overflow interrupt
00084   *     @arg RTC_IT_ALR: Alarm interrupt
00085   *     @arg RTC_IT_SEC: Second interrupt
00086   * @param  NewState: new state of the specified RTC interrupts.
00087   *   This parameter can be: ENABLE or DISABLE.
00088   * @retval None
00089   */
00090 void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState)
00091 {
00092   /* Check the parameters */
00093   assert_param(IS_RTC_IT(RTC_IT));
00094   assert_param(IS_FUNCTIONAL_STATE(NewState));
00095
00096   if (NewState != DISABLE)
00097   {
00098     RTC->CRH |= RTC_IT;
00099   }
00100   else
00101   {
00102     RTC->CRH &= (uint16_t)~RTC_IT;
00103   }
00104 }
00105
00106 /**
00107   * @brief  Enters the RTC configuration mode.
00108   * @param  None
00109   * @retval None
00110   */
00111 void RTC_EnterConfigMode(void)
00112 {
00113   /* Set the CNF flag to enter in the Configuration Mode */
00114   RTC->CRL |= RTC_CRL_CNF;
00115 }
00116
00117 /**
00118   * @brief  Exits from the RTC configuration mode.
00119   * @param  None
00120   * @retval None
00121   */
00122 void RTC_ExitConfigMode(void)
00123 {
00124   /* Reset the CNF flag to exit from the Configuration Mode */
00125   RTC->CRL &= (uint16_t)~((uint16_t)RTC_CRL_CNF);
00126 }
00127
00128 /**
00129   * @brief  Gets the RTC counter value.
00130   * @param  None
00131   * @retval RTC counter value.
00132   */
00133 uint32_t RTC_GetCounter(void)
00134 {
00135   uint16_t tmp = 0;
00136   tmp = RTC->CNTL;
00137   return (((uint32_t)RTC->CNTH << 16 ) | tmp) ;
00138 }
00139
00140 /**
00141   * @brief  Sets the RTC counter value.
00142   * @param  CounterValue: RTC counter new value.
00143   * @retval None
00144   */
00145 void RTC_SetCounter(uint32_t CounterValue)
00146 {
00147   RTC_EnterConfigMode();
00148   /* Set RTC COUNTER MSB word */
00149   RTC->CNTH = CounterValue >> 16;
00150   /* Set RTC COUNTER LSB word */
00151   RTC->CNTL = (CounterValue & RTC_LSB_MASK);
00152   RTC_ExitConfigMode();
00153 }
00154
00155 /**
00156   * @brief  Sets the RTC prescaler value.
00157   * @param  PrescalerValue: RTC prescaler new value.
00158   * @retval None
00159   */
00160 void RTC_SetPrescaler(uint32_t PrescalerValue)
00161 {
00162   /* Check the parameters */
00163   assert_param(IS_RTC_PRESCALER(PrescalerValue));
00164
00165   RTC_EnterConfigMode();
00166   /* Set RTC PRESCALER MSB word */
00167   RTC->PRLH = (PrescalerValue & PRLH_MSB_MASK) >> 16;
00168   /* Set RTC PRESCALER LSB word */
00169   RTC->PRLL = (PrescalerValue & RTC_LSB_MASK);
00170   RTC_ExitConfigMode();
00171 }
00172
00173 /**
00174   * @brief  Sets the RTC alarm value.
00175   * @param  AlarmValue: RTC alarm new value.
00176   * @retval None
00177   */
00178 void RTC_SetAlarm(uint32_t AlarmValue)
00179 {
00180   RTC_EnterConfigMode();
00181   /* Set the ALARM MSB word */
00182   RTC->ALRH = AlarmValue >> 16;
00183   /* Set the ALARM LSB word */
00184   RTC->ALRL = (AlarmValue & RTC_LSB_MASK);
00185   RTC_ExitConfigMode();
00186 }
00187
00188 /**
00189   * @brief  Gets the RTC divider value.
00190   * @param  None
00191   * @retval RTC Divider value.
00192   */
00193 uint32_t RTC_GetDivider(void)
00194 {
00195   uint32_t tmp = 0x00;
00196   tmp = ((uint32_t)RTC->DIVH & (uint32_t)0x000F) << 16;
00197   tmp |= RTC->DIVL;
00198   return tmp;
00199 }
00200
00201 /**
00202   * @brief  Waits until last write operation on RTC registers has finished.
00203   * @note   This function must be called before any write to RTC registers.
00204   * @param  None
00205   * @retval None
00206   */
00207 void RTC_WaitForLastTask(void)
00208 {
00209   /* Loop until RTOFF flag is set */
00210   while ((RTC->CRL & RTC_FLAG_RTOFF) == (uint16_t)RESET)
00211   {
00212   }
00213 }
00214
00215 /**
00216   * @brief  Waits until the RTC registers (RTC_CNT, RTC_ALR and RTC_PRL)
00217   *   are synchronized with RTC APB clock.
00218   * @note   This function must be called before any read operation after an APB reset
00219   *   or an APB clock stop.
00220   * @param  None
00221   * @retval None
00222   */
00223 void RTC_WaitForSynchro(void)
00224 {
00225   /* Clear RSF flag */
00226   RTC->CRL &= (uint16_t)~RTC_FLAG_RSF;
00227   /* Loop until RSF flag is set */
00228   while ((RTC->CRL & RTC_FLAG_RSF) == (uint16_t)RESET)
00229   {
00230   }
00231 }
00232
00233 /**
00234   * @brief  Checks whether the specified RTC flag is set or not.
00235   * @param  RTC_FLAG: specifies the flag to check.
00236   *   This parameter can be one the following values:
00237   *     @arg RTC_FLAG_RTOFF: RTC Operation OFF flag
00238   *     @arg RTC_FLAG_RSF: Registers Synchronized flag
00239   *     @arg RTC_FLAG_OW: Overflow flag
00240   *     @arg RTC_FLAG_ALR: Alarm flag
00241   *     @arg RTC_FLAG_SEC: Second flag
00242   * @retval The new state of RTC_FLAG (SET or RESET).
00243   */
00244 FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG)
00245 {
00246   FlagStatus bitstatus = RESET;
00247
00248   /* Check the parameters */
00249   assert_param(IS_RTC_GET_FLAG(RTC_FLAG));
00250
00251   if ((RTC->CRL & RTC_FLAG) != (uint16_t)RESET)
00252   {
00253     bitstatus = SET;
00254   }
00255   else
00256   {
00257     bitstatus = RESET;
00258   }
00259   return bitstatus;
00260 }
00261
00262 /**
00263   * @brief  Clears the RTC's pending flags.
00264   * @param  RTC_FLAG: specifies the flag to clear.
00265   *   This parameter can be any combination of the following values:
00266   *     @arg RTC_FLAG_RSF: Registers Synchronized flag. This flag is cleared only after
00267   *                        an APB reset or an APB Clock stop.
00268   *     @arg RTC_FLAG_OW: Overflow flag
00269   *     @arg RTC_FLAG_ALR: Alarm flag
00270   *     @arg RTC_FLAG_SEC: Second flag
00271   * @retval None
00272   */
00273 void RTC_ClearFlag(uint16_t RTC_FLAG)
00274 {
00275   /* Check the parameters */
00276   assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG));
00277
00278   /* Clear the corresponding RTC flag */
00279   RTC->CRL &= (uint16_t)~RTC_FLAG;
00280 }
00281
00282 /**
00283   * @brief  Checks whether the specified RTC interrupt has occurred or not.
00284   * @param  RTC_IT: specifies the RTC interrupts sources to check.
00285   *   This parameter can be one of the following values:
00286   *     @arg RTC_IT_OW: Overflow interrupt
00287   *     @arg RTC_IT_ALR: Alarm interrupt
00288   *     @arg RTC_IT_SEC: Second interrupt
00289   * @retval The new state of the RTC_IT (SET or RESET).
00290   */
00291 ITStatus RTC_GetITStatus(uint16_t RTC_IT)
00292 {
00293   ITStatus bitstatus = RESET;
00294   /* Check the parameters */
00295   assert_param(IS_RTC_GET_IT(RTC_IT));
00296
00297   bitstatus = (ITStatus)(RTC->CRL & RTC_IT);
00298   if (((RTC->CRH & RTC_IT) != (uint16_t)RESET) && (bitstatus != (uint16_t)RESET))
00299   {
00300     bitstatus = SET;
00301   }
00302   else
00303   {
00304     bitstatus = RESET;
00305   }
00306   return bitstatus;
00307 }
00308
00309 /**
00310   * @brief  Clears the RTC's interrupt pending bits.
00311   * @param  RTC_IT: specifies the interrupt pending bit to clear.
00312   *   This parameter can be any combination of the following values:
00313   *     @arg RTC_IT_OW: Overflow interrupt
00314   *     @arg RTC_IT_ALR: Alarm interrupt
00315   *     @arg RTC_IT_SEC: Second interrupt
00316   * @retval None
00317   */
00318 void RTC_ClearITPendingBit(uint16_t RTC_IT)
00319 {
00320   /* Check the parameters */
00321   assert_param(IS_RTC_IT(RTC_IT));
00322
00323   /* Clear the corresponding RTC pending bit */
00324   RTC->CRL &= (uint16_t)~RTC_IT;
00325 }
00326
00327 /**
00328   * @}
00329   */
00330
00331 /**
00332   * @}
00333   */
00334
00335 /**
00336   * @}
00337   */
00338
00339 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_rtc.h Source File

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  • STM32F10x_StdPeriph_Lib_V3.5.0
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  • inc

stm32f10x_rtc.h

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f10x_rtc.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    11-March-2011
00007   * @brief   This file contains all the functions prototypes for the RTC firmware
00008   *          library.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00013   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00014   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00015   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00016   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00017   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00018   *
00019   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00020   ******************************************************************************
00021   */
00022
00023 /* Define to prevent recursive inclusion -------------------------------------*/
00024 #ifndef __STM32F10x_RTC_H
00025 #define __STM32F10x_RTC_H
00026
00027 #ifdef __cplusplus
00028  extern "C" {
00029 #endif
00030
00031 /* Includes ------------------------------------------------------------------*/
00032 #include "stm32f10x.h"
00033
00034 /** @addtogroup STM32F10x_StdPeriph_Driver
00035   * @{
00036   */
00037
00038 /** @addtogroup RTC
00039   * @{
00040   */
00041
00042 /** @defgroup RTC_Exported_Types
00043   * @{
00044   */
00045
00046 /**
00047   * @}
00048   */
00049
00050 /** @defgroup RTC_Exported_Constants
00051   * @{
00052   */
00053
00054 /** @defgroup RTC_interrupts_define
00055   * @{
00056   */
00057
00058 #define RTC_IT_OW            ((uint16_t)0x0004)  /*!< Overflow interrupt */
00059 #define RTC_IT_ALR           ((uint16_t)0x0002)  /*!< Alarm interrupt */
00060 #define RTC_IT_SEC           ((uint16_t)0x0001)  /*!< Second interrupt */
00061 #define IS_RTC_IT(IT) ((((IT) & (uint16_t)0xFFF8) == 0x00) && ((IT) != 0x00))
00062 #define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_OW) || ((IT) == RTC_IT_ALR) || \
00063                            ((IT) == RTC_IT_SEC))
00064 /**
00065   * @}
00066   */
00067
00068 /** @defgroup RTC_interrupts_flags
00069   * @{
00070   */
00071
00072 #define RTC_FLAG_RTOFF       ((uint16_t)0x0020)  /*!< RTC Operation OFF flag */
00073 #define RTC_FLAG_RSF         ((uint16_t)0x0008)  /*!< Registers Synchronized flag */
00074 #define RTC_FLAG_OW          ((uint16_t)0x0004)  /*!< Overflow flag */
00075 #define RTC_FLAG_ALR         ((uint16_t)0x0002)  /*!< Alarm flag */
00076 #define RTC_FLAG_SEC         ((uint16_t)0x0001)  /*!< Second flag */
00077 #define IS_RTC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFFF0) == 0x00) && ((FLAG) != 0x00))
00078 #define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_RTOFF) || ((FLAG) == RTC_FLAG_RSF) || \
00079                                ((FLAG) == RTC_FLAG_OW) || ((FLAG) == RTC_FLAG_ALR) || \
00080                                ((FLAG) == RTC_FLAG_SEC))
00081 #define IS_RTC_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFFFF)
00082
00083 /**
00084   * @}
00085   */
00086
00087 /**
00088   * @}
00089   */
00090
00091 /** @defgroup RTC_Exported_Macros
00092   * @{
00093   */
00094
00095 /**
00096   * @}
00097   */
00098
00099 /** @defgroup RTC_Exported_Functions
00100   * @{
00101   */
00102
00103 void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState);
00104 void RTC_EnterConfigMode(void);
00105 void RTC_ExitConfigMode(void);
00106 uint32_t  RTC_GetCounter(void);
00107 void RTC_SetCounter(uint32_t CounterValue);
00108 void RTC_SetPrescaler(uint32_t PrescalerValue);
00109 void RTC_SetAlarm(uint32_t AlarmValue);
00110 uint32_t  RTC_GetDivider(void);
00111 void RTC_WaitForLastTask(void);
00112 void RTC_WaitForSynchro(void);
00113 FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG);
00114 void RTC_ClearFlag(uint16_t RTC_FLAG);
00115 ITStatus RTC_GetITStatus(uint16_t RTC_IT);
00116 void RTC_ClearITPendingBit(uint16_t RTC_IT);
00117
00118 #ifdef __cplusplus
00119 }
00120 #endif
00121
00122 #endif /* __STM32F10x_RTC_H */
00123 /**
00124   * @}
00125   */
00126
00127 /**
00128   * @}
00129   */
00130
00131 /**
00132   * @}
00133   */
00134
00135 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_sdio.c Source File

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stm32f10x_sdio.c

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f10x_sdio.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    11-March-2011
00007   * @brief   This file provides all the SDIO firmware functions.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x_sdio.h"
00024 #include "stm32f10x_rcc.h"
00025
00026 /** @addtogroup STM32F10x_StdPeriph_Driver
00027   * @{
00028   */
00029
00030 /** @defgroup SDIO
00031   * @brief SDIO driver modules
00032   * @{
00033   */
00034
00035 /** @defgroup SDIO_Private_TypesDefinitions
00036   * @{
00037   */
00038
00039 /* ------------ SDIO registers bit address in the alias region ----------- */
00040 #define SDIO_OFFSET                (SDIO_BASE - PERIPH_BASE)
00041
00042 /* --- CLKCR Register ---*/
00043
00044 /* Alias word address of CLKEN bit */
00045 #define CLKCR_OFFSET              (SDIO_OFFSET + 0x04)
00046 #define CLKEN_BitNumber           0x08
00047 #define CLKCR_CLKEN_BB            (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4))
00048
00049 /* --- CMD Register ---*/
00050
00051 /* Alias word address of SDIOSUSPEND bit */
00052 #define CMD_OFFSET                (SDIO_OFFSET + 0x0C)
00053 #define SDIOSUSPEND_BitNumber     0x0B
00054 #define CMD_SDIOSUSPEND_BB        (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4))
00055
00056 /* Alias word address of ENCMDCOMPL bit */
00057 #define ENCMDCOMPL_BitNumber      0x0C
00058 #define CMD_ENCMDCOMPL_BB         (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4))
00059
00060 /* Alias word address of NIEN bit */
00061 #define NIEN_BitNumber            0x0D
00062 #define CMD_NIEN_BB               (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4))
00063
00064 /* Alias word address of ATACMD bit */
00065 #define ATACMD_BitNumber          0x0E
00066 #define CMD_ATACMD_BB             (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4))
00067
00068 /* --- DCTRL Register ---*/
00069
00070 /* Alias word address of DMAEN bit */
00071 #define DCTRL_OFFSET              (SDIO_OFFSET + 0x2C)
00072 #define DMAEN_BitNumber           0x03
00073 #define DCTRL_DMAEN_BB            (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4))
00074
00075 /* Alias word address of RWSTART bit */
00076 #define RWSTART_BitNumber         0x08
00077 #define DCTRL_RWSTART_BB          (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4))
00078
00079 /* Alias word address of RWSTOP bit */
00080 #define RWSTOP_BitNumber          0x09
00081 #define DCTRL_RWSTOP_BB           (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4))
00082
00083 /* Alias word address of RWMOD bit */
00084 #define RWMOD_BitNumber           0x0A
00085 #define DCTRL_RWMOD_BB            (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4))
00086
00087 /* Alias word address of SDIOEN bit */
00088 #define SDIOEN_BitNumber          0x0B
00089 #define DCTRL_SDIOEN_BB           (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4))
00090
00091 /* ---------------------- SDIO registers bit mask ------------------------ */
00092
00093 /* --- CLKCR Register ---*/
00094
00095 /* CLKCR register clear mask */
00096 #define CLKCR_CLEAR_MASK         ((uint32_t)0xFFFF8100)
00097
00098 /* --- PWRCTRL Register ---*/
00099
00100 /* SDIO PWRCTRL Mask */
00101 #define PWR_PWRCTRL_MASK         ((uint32_t)0xFFFFFFFC)
00102
00103 /* --- DCTRL Register ---*/
00104
00105 /* SDIO DCTRL Clear Mask */
00106 #define DCTRL_CLEAR_MASK         ((uint32_t)0xFFFFFF08)
00107
00108 /* --- CMD Register ---*/
00109
00110 /* CMD Register clear mask */
00111 #define CMD_CLEAR_MASK           ((uint32_t)0xFFFFF800)
00112
00113 /* SDIO RESP Registers Address */
00114 #define SDIO_RESP_ADDR           ((uint32_t)(SDIO_BASE + 0x14))
00115
00116 /**
00117   * @}
00118   */
00119
00120 /** @defgroup SDIO_Private_Defines
00121   * @{
00122   */
00123
00124 /**
00125   * @}
00126   */
00127
00128 /** @defgroup SDIO_Private_Macros
00129   * @{
00130   */
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @defgroup SDIO_Private_Variables
00137   * @{
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @defgroup SDIO_Private_FunctionPrototypes
00145   * @{
00146   */
00147
00148 /**
00149   * @}
00150   */
00151
00152 /** @defgroup SDIO_Private_Functions
00153   * @{
00154   */
00155
00156 /**
00157   * @brief  Deinitializes the SDIO peripheral registers to their default reset values.
00158   * @param  None
00159   * @retval None
00160   */
00161 void SDIO_DeInit(void)
00162 {
00163   SDIO->POWER = 0x00000000;
00164   SDIO->CLKCR = 0x00000000;
00165   SDIO->ARG = 0x00000000;
00166   SDIO->CMD = 0x00000000;
00167   SDIO->DTIMER = 0x00000000;
00168   SDIO->DLEN = 0x00000000;
00169   SDIO->DCTRL = 0x00000000;
00170   SDIO->ICR = 0x00C007FF;
00171   SDIO->MASK = 0x00000000;
00172 }
00173
00174 /**
00175   * @brief  Initializes the SDIO peripheral according to the specified
00176   *         parameters in the SDIO_InitStruct.
00177   * @param  SDIO_InitStruct : pointer to a SDIO_InitTypeDef structure
00178   *         that contains the configuration information for the SDIO peripheral.
00179   * @retval None
00180   */
00181 void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct)
00182 {
00183   uint32_t tmpreg = 0;
00184
00185   /* Check the parameters */
00186   assert_param(IS_SDIO_CLOCK_EDGE(SDIO_InitStruct->SDIO_ClockEdge));
00187   assert_param(IS_SDIO_CLOCK_BYPASS(SDIO_InitStruct->SDIO_ClockBypass));
00188   assert_param(IS_SDIO_CLOCK_POWER_SAVE(SDIO_InitStruct->SDIO_ClockPowerSave));
00189   assert_param(IS_SDIO_BUS_WIDE(SDIO_InitStruct->SDIO_BusWide));
00190   assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(SDIO_InitStruct->SDIO_HardwareFlowControl));
00191
00192 /*---------------------------- SDIO CLKCR Configuration ------------------------*/
00193   /* Get the SDIO CLKCR value */
00194   tmpreg = SDIO->CLKCR;
00195
00196   /* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */
00197   tmpreg &= CLKCR_CLEAR_MASK;
00198
00199   /* Set CLKDIV bits according to SDIO_ClockDiv value */
00200   /* Set PWRSAV bit according to SDIO_ClockPowerSave value */
00201   /* Set BYPASS bit according to SDIO_ClockBypass value */
00202   /* Set WIDBUS bits according to SDIO_BusWide value */
00203   /* Set NEGEDGE bits according to SDIO_ClockEdge value */
00204   /* Set HWFC_EN bits according to SDIO_HardwareFlowControl value */
00205   tmpreg |= (SDIO_InitStruct->SDIO_ClockDiv  | SDIO_InitStruct->SDIO_ClockPowerSave |
00206              SDIO_InitStruct->SDIO_ClockBypass | SDIO_InitStruct->SDIO_BusWide |
00207              SDIO_InitStruct->SDIO_ClockEdge | SDIO_InitStruct->SDIO_HardwareFlowControl);
00208
00209   /* Write to SDIO CLKCR */
00210   SDIO->CLKCR = tmpreg;
00211 }
00212
00213 /**
00214   * @brief  Fills each SDIO_InitStruct member with its default value.
00215   * @param  SDIO_InitStruct: pointer to an SDIO_InitTypeDef structure which
00216   *   will be initialized.
00217   * @retval None
00218   */
00219 void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct)
00220 {
00221   /* SDIO_InitStruct members default value */
00222   SDIO_InitStruct->SDIO_ClockDiv = 0x00;
00223   SDIO_InitStruct->SDIO_ClockEdge = SDIO_ClockEdge_Rising;
00224   SDIO_InitStruct->SDIO_ClockBypass = SDIO_ClockBypass_Disable;
00225   SDIO_InitStruct->SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable;
00226   SDIO_InitStruct->SDIO_BusWide = SDIO_BusWide_1b;
00227   SDIO_InitStruct->SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable;
00228 }
00229
00230 /**
00231   * @brief  Enables or disables the SDIO Clock.
00232   * @param  NewState: new state of the SDIO Clock. This parameter can be: ENABLE or DISABLE.
00233   * @retval None
00234   */
00235 void SDIO_ClockCmd(FunctionalState NewState)
00236 {
00237   /* Check the parameters */
00238   assert_param(IS_FUNCTIONAL_STATE(NewState));
00239
00240   *(__IO uint32_t *) CLKCR_CLKEN_BB = (uint32_t)NewState;
00241 }
00242
00243 /**
00244   * @brief  Sets the power status of the controller.
00245   * @param  SDIO_PowerState: new state of the Power state.
00246   *   This parameter can be one of the following values:
00247   *     @arg SDIO_PowerState_OFF
00248   *     @arg SDIO_PowerState_ON
00249   * @retval None
00250   */
00251 void SDIO_SetPowerState(uint32_t SDIO_PowerState)
00252 {
00253   /* Check the parameters */
00254   assert_param(IS_SDIO_POWER_STATE(SDIO_PowerState));
00255
00256   SDIO->POWER &= PWR_PWRCTRL_MASK;
00257   SDIO->POWER |= SDIO_PowerState;
00258 }
00259
00260 /**
00261   * @brief  Gets the power status of the controller.
00262   * @param  None
00263   * @retval Power status of the controller. The returned value can
00264   *   be one of the following:
00265   * - 0x00: Power OFF
00266   * - 0x02: Power UP
00267   * - 0x03: Power ON
00268   */
00269 uint32_t SDIO_GetPowerState(void)
00270 {
00271   return (SDIO->POWER & (~PWR_PWRCTRL_MASK));
00272 }
00273
00274 /**
00275   * @brief  Enables or disables the SDIO interrupts.
00276   * @param  SDIO_IT: specifies the SDIO interrupt sources to be enabled or disabled.
00277   *   This parameter can be one or a combination of the following values:
00278   *     @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
00279   *     @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
00280   *     @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
00281   *     @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
00282   *     @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
00283   *     @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
00284   *     @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
00285   *     @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
00286   *     @arg SDIO_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
00287   *     @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
00288   *                            bus mode interrupt
00289   *     @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
00290   *     @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt
00291   *     @arg SDIO_IT_TXACT:    Data transmit in progress interrupt
00292   *     @arg SDIO_IT_RXACT:    Data receive in progress interrupt
00293   *     @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
00294   *     @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
00295   *     @arg SDIO_IT_TXFIFOF:  Transmit FIFO full interrupt
00296   *     @arg SDIO_IT_RXFIFOF:  Receive FIFO full interrupt
00297   *     @arg SDIO_IT_TXFIFOE:  Transmit FIFO empty interrupt
00298   *     @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt
00299   *     @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt
00300   *     @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt
00301   *     @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
00302   *     @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
00303   * @param  NewState: new state of the specified SDIO interrupts.
00304   *   This parameter can be: ENABLE or DISABLE.
00305   * @retval None
00306   */
00307 void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState)
00308 {
00309   /* Check the parameters */
00310   assert_param(IS_SDIO_IT(SDIO_IT));
00311   assert_param(IS_FUNCTIONAL_STATE(NewState));
00312
00313   if (NewState != DISABLE)
00314   {
00315     /* Enable the SDIO interrupts */
00316     SDIO->MASK |= SDIO_IT;
00317   }
00318   else
00319   {
00320     /* Disable the SDIO interrupts */
00321     SDIO->MASK &= ~SDIO_IT;
00322   }
00323 }
00324
00325 /**
00326   * @brief  Enables or disables the SDIO DMA request.
00327   * @param  NewState: new state of the selected SDIO DMA request.
00328   *   This parameter can be: ENABLE or DISABLE.
00329   * @retval None
00330   */
00331 void SDIO_DMACmd(FunctionalState NewState)
00332 {
00333   /* Check the parameters */
00334   assert_param(IS_FUNCTIONAL_STATE(NewState));
00335
00336   *(__IO uint32_t *) DCTRL_DMAEN_BB = (uint32_t)NewState;
00337 }
00338
00339 /**
00340   * @brief  Initializes the SDIO Command according to the specified
00341   *         parameters in the SDIO_CmdInitStruct and send the command.
00342   * @param  SDIO_CmdInitStruct : pointer to a SDIO_CmdInitTypeDef
00343   *         structure that contains the configuration information for the SDIO command.
00344   * @retval None
00345   */
00346 void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct)
00347 {
00348   uint32_t tmpreg = 0;
00349
00350   /* Check the parameters */
00351   assert_param(IS_SDIO_CMD_INDEX(SDIO_CmdInitStruct->SDIO_CmdIndex));
00352   assert_param(IS_SDIO_RESPONSE(SDIO_CmdInitStruct->SDIO_Response));
00353   assert_param(IS_SDIO_WAIT(SDIO_CmdInitStruct->SDIO_Wait));
00354   assert_param(IS_SDIO_CPSM(SDIO_CmdInitStruct->SDIO_CPSM));
00355
00356 /*---------------------------- SDIO ARG Configuration ------------------------*/
00357   /* Set the SDIO Argument value */
00358   SDIO->ARG = SDIO_CmdInitStruct->SDIO_Argument;
00359
00360 /*---------------------------- SDIO CMD Configuration ------------------------*/
00361   /* Get the SDIO CMD value */
00362   tmpreg = SDIO->CMD;
00363   /* Clear CMDINDEX, WAITRESP, WAITINT, WAITPEND, CPSMEN bits */
00364   tmpreg &= CMD_CLEAR_MASK;
00365   /* Set CMDINDEX bits according to SDIO_CmdIndex value */
00366   /* Set WAITRESP bits according to SDIO_Response value */
00367   /* Set WAITINT and WAITPEND bits according to SDIO_Wait value */
00368   /* Set CPSMEN bits according to SDIO_CPSM value */
00369   tmpreg |= (uint32_t)SDIO_CmdInitStruct->SDIO_CmdIndex | SDIO_CmdInitStruct->SDIO_Response
00370            | SDIO_CmdInitStruct->SDIO_Wait | SDIO_CmdInitStruct->SDIO_CPSM;
00371
00372   /* Write to SDIO CMD */
00373   SDIO->CMD = tmpreg;
00374 }
00375
00376 /**
00377   * @brief  Fills each SDIO_CmdInitStruct member with its default value.
00378   * @param  SDIO_CmdInitStruct: pointer to an SDIO_CmdInitTypeDef
00379   *         structure which will be initialized.
00380   * @retval None
00381   */
00382 void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct)
00383 {
00384   /* SDIO_CmdInitStruct members default value */
00385   SDIO_CmdInitStruct->SDIO_Argument = 0x00;
00386   SDIO_CmdInitStruct->SDIO_CmdIndex = 0x00;
00387   SDIO_CmdInitStruct->SDIO_Response = SDIO_Response_No;
00388   SDIO_CmdInitStruct->SDIO_Wait = SDIO_Wait_No;
00389   SDIO_CmdInitStruct->SDIO_CPSM = SDIO_CPSM_Disable;
00390 }
00391
00392 /**
00393   * @brief  Returns command index of last command for which response received.
00394   * @param  None
00395   * @retval Returns the command index of the last command response received.
00396   */
00397 uint8_t SDIO_GetCommandResponse(void)
00398 {
00399   return (uint8_t)(SDIO->RESPCMD);
00400 }
00401
00402 /**
00403   * @brief  Returns response received from the card for the last command.
00404   * @param  SDIO_RESP: Specifies the SDIO response register.
00405   *   This parameter can be one of the following values:
00406   *     @arg SDIO_RESP1: Response Register 1
00407   *     @arg SDIO_RESP2: Response Register 2
00408   *     @arg SDIO_RESP3: Response Register 3
00409   *     @arg SDIO_RESP4: Response Register 4
00410   * @retval The Corresponding response register value.
00411   */
00412 uint32_t SDIO_GetResponse(uint32_t SDIO_RESP)
00413 {
00414   __IO uint32_t tmp = 0;
00415
00416   /* Check the parameters */
00417   assert_param(IS_SDIO_RESP(SDIO_RESP));
00418
00419   tmp = SDIO_RESP_ADDR + SDIO_RESP;
00420
00421   return (*(__IO uint32_t *) tmp);
00422 }
00423
00424 /**
00425   * @brief  Initializes the SDIO data path according to the specified
00426   *   parameters in the SDIO_DataInitStruct.
00427   * @param  SDIO_DataInitStruct : pointer to a SDIO_DataInitTypeDef structure that
00428   *   contains the configuration information for the SDIO command.
00429   * @retval None
00430   */
00431 void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct)
00432 {
00433   uint32_t tmpreg = 0;
00434
00435   /* Check the parameters */
00436   assert_param(IS_SDIO_DATA_LENGTH(SDIO_DataInitStruct->SDIO_DataLength));
00437   assert_param(IS_SDIO_BLOCK_SIZE(SDIO_DataInitStruct->SDIO_DataBlockSize));
00438   assert_param(IS_SDIO_TRANSFER_DIR(SDIO_DataInitStruct->SDIO_TransferDir));
00439   assert_param(IS_SDIO_TRANSFER_MODE(SDIO_DataInitStruct->SDIO_TransferMode));
00440   assert_param(IS_SDIO_DPSM(SDIO_DataInitStruct->SDIO_DPSM));
00441
00442 /*---------------------------- SDIO DTIMER Configuration ---------------------*/
00443   /* Set the SDIO Data TimeOut value */
00444   SDIO->DTIMER = SDIO_DataInitStruct->SDIO_DataTimeOut;
00445
00446 /*---------------------------- SDIO DLEN Configuration -----------------------*/
00447   /* Set the SDIO DataLength value */
00448   SDIO->DLEN = SDIO_DataInitStruct->SDIO_DataLength;
00449
00450 /*---------------------------- SDIO DCTRL Configuration ----------------------*/
00451   /* Get the SDIO DCTRL value */
00452   tmpreg = SDIO->DCTRL;
00453   /* Clear DEN, DTMODE, DTDIR and DBCKSIZE bits */
00454   tmpreg &= DCTRL_CLEAR_MASK;
00455   /* Set DEN bit according to SDIO_DPSM value */
00456   /* Set DTMODE bit according to SDIO_TransferMode value */
00457   /* Set DTDIR bit according to SDIO_TransferDir value */
00458   /* Set DBCKSIZE bits according to SDIO_DataBlockSize value */
00459   tmpreg |= (uint32_t)SDIO_DataInitStruct->SDIO_DataBlockSize | SDIO_DataInitStruct->SDIO_TransferDir
00460            | SDIO_DataInitStruct->SDIO_TransferMode | SDIO_DataInitStruct->SDIO_DPSM;
00461
00462   /* Write to SDIO DCTRL */
00463   SDIO->DCTRL = tmpreg;
00464 }
00465
00466 /**
00467   * @brief  Fills each SDIO_DataInitStruct member with its default value.
00468   * @param  SDIO_DataInitStruct: pointer to an SDIO_DataInitTypeDef structure which
00469   *         will be initialized.
00470   * @retval None
00471   */
00472 void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct)
00473 {
00474   /* SDIO_DataInitStruct members default value */
00475   SDIO_DataInitStruct->SDIO_DataTimeOut = 0xFFFFFFFF;
00476   SDIO_DataInitStruct->SDIO_DataLength = 0x00;
00477   SDIO_DataInitStruct->SDIO_DataBlockSize = SDIO_DataBlockSize_1b;
00478   SDIO_DataInitStruct->SDIO_TransferDir = SDIO_TransferDir_ToCard;
00479   SDIO_DataInitStruct->SDIO_TransferMode = SDIO_TransferMode_Block;
00480   SDIO_DataInitStruct->SDIO_DPSM = SDIO_DPSM_Disable;
00481 }
00482
00483 /**
00484   * @brief  Returns number of remaining data bytes to be transferred.
00485   * @param  None
00486   * @retval Number of remaining data bytes to be transferred
00487   */
00488 uint32_t SDIO_GetDataCounter(void)
00489 {
00490   return SDIO->DCOUNT;
00491 }
00492
00493 /**
00494   * @brief  Read one data word from Rx FIFO.
00495   * @param  None
00496   * @retval Data received
00497   */
00498 uint32_t SDIO_ReadData(void)
00499 {
00500   return SDIO->FIFO;
00501 }
00502
00503 /**
00504   * @brief  Write one data word to Tx FIFO.
00505   * @param  Data: 32-bit data word to write.
00506   * @retval None
00507   */
00508 void SDIO_WriteData(uint32_t Data)
00509 {
00510   SDIO->FIFO = Data;
00511 }
00512
00513 /**
00514   * @brief  Returns the number of words left to be written to or read from FIFO.
00515   * @param  None
00516   * @retval Remaining number of words.
00517   */
00518 uint32_t SDIO_GetFIFOCount(void)
00519 {
00520   return SDIO->FIFOCNT;
00521 }
00522
00523 /**
00524   * @brief  Starts the SD I/O Read Wait operation.
00525   * @param  NewState: new state of the Start SDIO Read Wait operation.
00526   *   This parameter can be: ENABLE or DISABLE.
00527   * @retval None
00528   */
00529 void SDIO_StartSDIOReadWait(FunctionalState NewState)
00530 {
00531   /* Check the parameters */
00532   assert_param(IS_FUNCTIONAL_STATE(NewState));
00533
00534   *(__IO uint32_t *) DCTRL_RWSTART_BB = (uint32_t) NewState;
00535 }
00536
00537 /**
00538   * @brief  Stops the SD I/O Read Wait operation.
00539   * @param  NewState: new state of the Stop SDIO Read Wait operation.
00540   *   This parameter can be: ENABLE or DISABLE.
00541   * @retval None
00542   */
00543 void SDIO_StopSDIOReadWait(FunctionalState NewState)
00544 {
00545   /* Check the parameters */
00546   assert_param(IS_FUNCTIONAL_STATE(NewState));
00547
00548   *(__IO uint32_t *) DCTRL_RWSTOP_BB = (uint32_t) NewState;
00549 }
00550
00551 /**
00552   * @brief  Sets one of the two options of inserting read wait interval.
00553   * @param  SDIO_ReadWaitMode: SD I/O Read Wait operation mode.
00554   *   This parameter can be:
00555   *     @arg SDIO_ReadWaitMode_CLK: Read Wait control by stopping SDIOCLK
00556   *     @arg SDIO_ReadWaitMode_DATA2: Read Wait control using SDIO_DATA2
00557   * @retval None
00558   */
00559 void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode)
00560 {
00561   /* Check the parameters */
00562   assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode));
00563
00564   *(__IO uint32_t *) DCTRL_RWMOD_BB = SDIO_ReadWaitMode;
00565 }
00566
00567 /**
00568   * @brief  Enables or disables the SD I/O Mode Operation.
00569   * @param  NewState: new state of SDIO specific operation.
00570   *   This parameter can be: ENABLE or DISABLE.
00571   * @retval None
00572   */
00573 void SDIO_SetSDIOOperation(FunctionalState NewState)
00574 {
00575   /* Check the parameters */
00576   assert_param(IS_FUNCTIONAL_STATE(NewState));
00577
00578   *(__IO uint32_t *) DCTRL_SDIOEN_BB = (uint32_t)NewState;
00579 }
00580
00581 /**
00582   * @brief  Enables or disables the SD I/O Mode suspend command sending.
00583   * @param  NewState: new state of the SD I/O Mode suspend command.
00584   *   This parameter can be: ENABLE or DISABLE.
00585   * @retval None
00586   */
00587 void SDIO_SendSDIOSuspendCmd(FunctionalState NewState)
00588 {
00589   /* Check the parameters */
00590   assert_param(IS_FUNCTIONAL_STATE(NewState));
00591
00592   *(__IO uint32_t *) CMD_SDIOSUSPEND_BB = (uint32_t)NewState;
00593 }
00594
00595 /**
00596   * @brief  Enables or disables the command completion signal.
00597   * @param  NewState: new state of command completion signal.
00598   *   This parameter can be: ENABLE or DISABLE.
00599   * @retval None
00600   */
00601 void SDIO_CommandCompletionCmd(FunctionalState NewState)
00602 {
00603   /* Check the parameters */
00604   assert_param(IS_FUNCTIONAL_STATE(NewState));
00605
00606   *(__IO uint32_t *) CMD_ENCMDCOMPL_BB = (uint32_t)NewState;
00607 }
00608
00609 /**
00610   * @brief  Enables or disables the CE-ATA interrupt.
00611   * @param  NewState: new state of CE-ATA interrupt. This parameter can be: ENABLE or DISABLE.
00612   * @retval None
00613   */
00614 void SDIO_CEATAITCmd(FunctionalState NewState)
00615 {
00616   /* Check the parameters */
00617   assert_param(IS_FUNCTIONAL_STATE(NewState));
00618
00619   *(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)((~((uint32_t)NewState)) & ((uint32_t)0x1));
00620 }
00621
00622 /**
00623   * @brief  Sends CE-ATA command (CMD61).
00624   * @param  NewState: new state of CE-ATA command. This parameter can be: ENABLE or DISABLE.
00625   * @retval None
00626   */
00627 void SDIO_SendCEATACmd(FunctionalState NewState)
00628 {
00629   /* Check the parameters */
00630   assert_param(IS_FUNCTIONAL_STATE(NewState));
00631
00632   *(__IO uint32_t *) CMD_ATACMD_BB = (uint32_t)NewState;
00633 }
00634
00635 /**
00636   * @brief  Checks whether the specified SDIO flag is set or not.
00637   * @param  SDIO_FLAG: specifies the flag to check.
00638   *   This parameter can be one of the following values:
00639   *     @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
00640   *     @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
00641   *     @arg SDIO_FLAG_CTIMEOUT: Command response timeout
00642   *     @arg SDIO_FLAG_DTIMEOUT: Data timeout
00643   *     @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
00644   *     @arg SDIO_FLAG_RXOVERR:  Received FIFO overrun error
00645   *     @arg SDIO_FLAG_CMDREND:  Command response received (CRC check passed)
00646   *     @arg SDIO_FLAG_CMDSENT:  Command sent (no response required)
00647   *     @arg SDIO_FLAG_DATAEND:  Data end (data counter, SDIDCOUNT, is zero)
00648   *     @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide
00649   *                              bus mode.
00650   *     @arg SDIO_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
00651   *     @arg SDIO_FLAG_CMDACT:   Command transfer in progress
00652   *     @arg SDIO_FLAG_TXACT:    Data transmit in progress
00653   *     @arg SDIO_FLAG_RXACT:    Data receive in progress
00654   *     @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
00655   *     @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
00656   *     @arg SDIO_FLAG_TXFIFOF:  Transmit FIFO full
00657   *     @arg SDIO_FLAG_RXFIFOF:  Receive FIFO full
00658   *     @arg SDIO_FLAG_TXFIFOE:  Transmit FIFO empty
00659   *     @arg SDIO_FLAG_RXFIFOE:  Receive FIFO empty
00660   *     @arg SDIO_FLAG_TXDAVL:   Data available in transmit FIFO
00661   *     @arg SDIO_FLAG_RXDAVL:   Data available in receive FIFO
00662   *     @arg SDIO_FLAG_SDIOIT:   SD I/O interrupt received
00663   *     @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
00664   * @retval The new state of SDIO_FLAG (SET or RESET).
00665   */
00666 FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG)
00667 {
00668   FlagStatus bitstatus = RESET;
00669
00670   /* Check the parameters */
00671   assert_param(IS_SDIO_FLAG(SDIO_FLAG));
00672
00673   if ((SDIO->STA & SDIO_FLAG) != (uint32_t)RESET)
00674   {
00675     bitstatus = SET;
00676   }
00677   else
00678   {
00679     bitstatus = RESET;
00680   }
00681   return bitstatus;
00682 }
00683
00684 /**
00685   * @brief  Clears the SDIO's pending flags.
00686   * @param  SDIO_FLAG: specifies the flag to clear.
00687   *   This parameter can be one or a combination of the following values:
00688   *     @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
00689   *     @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
00690   *     @arg SDIO_FLAG_CTIMEOUT: Command response timeout
00691   *     @arg SDIO_FLAG_DTIMEOUT: Data timeout
00692   *     @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
00693   *     @arg SDIO_FLAG_RXOVERR:  Received FIFO overrun error
00694   *     @arg SDIO_FLAG_CMDREND:  Command response received (CRC check passed)
00695   *     @arg SDIO_FLAG_CMDSENT:  Command sent (no response required)
00696   *     @arg SDIO_FLAG_DATAEND:  Data end (data counter, SDIDCOUNT, is zero)
00697   *     @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide
00698   *                              bus mode
00699   *     @arg SDIO_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
00700   *     @arg SDIO_FLAG_SDIOIT:   SD I/O interrupt received
00701   *     @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
00702   * @retval None
00703   */
00704 void SDIO_ClearFlag(uint32_t SDIO_FLAG)
00705 {
00706   /* Check the parameters */
00707   assert_param(IS_SDIO_CLEAR_FLAG(SDIO_FLAG));
00708
00709   SDIO->ICR = SDIO_FLAG;
00710 }
00711
00712 /**
00713   * @brief  Checks whether the specified SDIO interrupt has occurred or not.
00714   * @param  SDIO_IT: specifies the SDIO interrupt source to check.
00715   *   This parameter can be one of the following values:
00716   *     @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
00717   *     @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
00718   *     @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
00719   *     @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
00720   *     @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
00721   *     @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
00722   *     @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
00723   *     @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
00724   *     @arg SDIO_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
00725   *     @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
00726   *                            bus mode interrupt
00727   *     @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
00728   *     @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt
00729   *     @arg SDIO_IT_TXACT:    Data transmit in progress interrupt
00730   *     @arg SDIO_IT_RXACT:    Data receive in progress interrupt
00731   *     @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
00732   *     @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
00733   *     @arg SDIO_IT_TXFIFOF:  Transmit FIFO full interrupt
00734   *     @arg SDIO_IT_RXFIFOF:  Receive FIFO full interrupt
00735   *     @arg SDIO_IT_TXFIFOE:  Transmit FIFO empty interrupt
00736   *     @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt
00737   *     @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt
00738   *     @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt
00739   *     @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
00740   *     @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
00741   * @retval The new state of SDIO_IT (SET or RESET).
00742   */
00743 ITStatus SDIO_GetITStatus(uint32_t SDIO_IT)
00744 {
00745   ITStatus bitstatus = RESET;
00746
00747   /* Check the parameters */
00748   assert_param(IS_SDIO_GET_IT(SDIO_IT));
00749   if ((SDIO->STA & SDIO_IT) != (uint32_t)RESET)
00750   {
00751     bitstatus = SET;
00752   }
00753   else
00754   {
00755     bitstatus = RESET;
00756   }
00757   return bitstatus;
00758 }
00759
00760 /**
00761   * @brief  Clears the SDIO's interrupt pending bits.
00762   * @param  SDIO_IT: specifies the interrupt pending bit to clear.
00763   *   This parameter can be one or a combination of the following values:
00764   *     @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
00765   *     @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
00766   *     @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
00767   *     @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
00768   *     @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
00769   *     @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
00770   *     @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
00771   *     @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
00772   *     @arg SDIO_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
00773   *     @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
00774   *                            bus mode interrupt
00775   *     @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
00776   *     @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61
00777   * @retval None
00778   */
00779 void SDIO_ClearITPendingBit(uint32_t SDIO_IT)
00780 {
00781   /* Check the parameters */
00782   assert_param(IS_SDIO_CLEAR_IT(SDIO_IT));
00783
00784   SDIO->ICR = SDIO_IT;
00785 }
00786
00787 /**
00788   * @}
00789   */
00790
00791 /**
00792   * @}
00793   */
00794
00795 /**
00796   * @}
00797   */
00798
00799 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_sdio.h Source File

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stm32f10x_sdio.h

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f10x_sdio.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    11-March-2011
00007   * @brief   This file contains all the functions prototypes for the SDIO firmware
00008   *          library.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00013   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00014   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00015   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00016   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00017   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00018   *
00019   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00020   ******************************************************************************
00021   */
00022
00023 /* Define to prevent recursive inclusion -------------------------------------*/
00024 #ifndef __STM32F10x_SDIO_H
00025 #define __STM32F10x_SDIO_H
00026
00027 #ifdef __cplusplus
00028  extern "C" {
00029 #endif
00030
00031 /* Includes ------------------------------------------------------------------*/
00032 #include "stm32f10x.h"
00033
00034 /** @addtogroup STM32F10x_StdPeriph_Driver
00035   * @{
00036   */
00037
00038 /** @addtogroup SDIO
00039   * @{
00040   */
00041
00042 /** @defgroup SDIO_Exported_Types
00043   * @{
00044   */
00045
00046 typedef struct
00047 {
00048   uint32_t SDIO_ClockEdge;            /*!< Specifies the clock transition on which the bit capture is made.
00049                                            This parameter can be a value of @ref SDIO_Clock_Edge */
00050
00051   uint32_t SDIO_ClockBypass;          /*!< Specifies whether the SDIO Clock divider bypass is
00052                                            enabled or disabled.
00053                                            This parameter can be a value of @ref SDIO_Clock_Bypass */
00054
00055   uint32_t SDIO_ClockPowerSave;       /*!< Specifies whether SDIO Clock output is enabled or
00056                                            disabled when the bus is idle.
00057                                            This parameter can be a value of @ref SDIO_Clock_Power_Save */
00058
00059   uint32_t SDIO_BusWide;              /*!< Specifies the SDIO bus width.
00060                                            This parameter can be a value of @ref SDIO_Bus_Wide */
00061
00062   uint32_t SDIO_HardwareFlowControl;  /*!< Specifies whether the SDIO hardware flow control is enabled or disabled.
00063                                            This parameter can be a value of @ref SDIO_Hardware_Flow_Control */
00064
00065   uint8_t SDIO_ClockDiv;              /*!< Specifies the clock frequency of the SDIO controller.
00066                                            This parameter can be a value between 0x00 and 0xFF. */
00067
00068 } SDIO_InitTypeDef;
00069
00070 typedef struct
00071 {
00072   uint32_t SDIO_Argument;  /*!< Specifies the SDIO command argument which is sent
00073                                 to a card as part of a command message. If a command
00074                                 contains an argument, it must be loaded into this register
00075                                 before writing the command to the command register */
00076
00077   uint32_t SDIO_CmdIndex;  /*!< Specifies the SDIO command index. It must be lower than 0x40. */
00078
00079   uint32_t SDIO_Response;  /*!< Specifies the SDIO response type.
00080                                 This parameter can be a value of @ref SDIO_Response_Type */
00081
00082   uint32_t SDIO_Wait;      /*!< Specifies whether SDIO wait-for-interrupt request is enabled or disabled.
00083                                 This parameter can be a value of @ref SDIO_Wait_Interrupt_State */
00084
00085   uint32_t SDIO_CPSM;      /*!< Specifies whether SDIO Command path state machine (CPSM)
00086                                 is enabled or disabled.
00087                                 This parameter can be a value of @ref SDIO_CPSM_State */
00088 } SDIO_CmdInitTypeDef;
00089
00090 typedef struct
00091 {
00092   uint32_t SDIO_DataTimeOut;    /*!< Specifies the data timeout period in card bus clock periods. */
00093
00094   uint32_t SDIO_DataLength;     /*!< Specifies the number of data bytes to be transferred. */
00095
00096   uint32_t SDIO_DataBlockSize;  /*!< Specifies the data block size for block transfer.
00097                                      This parameter can be a value of @ref SDIO_Data_Block_Size */
00098
00099   uint32_t SDIO_TransferDir;    /*!< Specifies the data transfer direction, whether the transfer
00100                                      is a read or write.
00101                                      This parameter can be a value of @ref SDIO_Transfer_Direction */
00102
00103   uint32_t SDIO_TransferMode;   /*!< Specifies whether data transfer is in stream or block mode.
00104                                      This parameter can be a value of @ref SDIO_Transfer_Type */
00105
00106   uint32_t SDIO_DPSM;           /*!< Specifies whether SDIO Data path state machine (DPSM)
00107                                      is enabled or disabled.
00108                                      This parameter can be a value of @ref SDIO_DPSM_State */
00109 } SDIO_DataInitTypeDef;
00110
00111 /**
00112   * @}
00113   */
00114
00115 /** @defgroup SDIO_Exported_Constants
00116   * @{
00117   */
00118
00119 /** @defgroup SDIO_Clock_Edge
00120   * @{
00121   */
00122
00123 #define SDIO_ClockEdge_Rising               ((uint32_t)0x00000000)
00124 #define SDIO_ClockEdge_Falling              ((uint32_t)0x00002000)
00125 #define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_ClockEdge_Rising) || \
00126                                   ((EDGE) == SDIO_ClockEdge_Falling))
00127 /**
00128   * @}
00129   */
00130
00131 /** @defgroup SDIO_Clock_Bypass
00132   * @{
00133   */
00134
00135 #define SDIO_ClockBypass_Disable             ((uint32_t)0x00000000)
00136 #define SDIO_ClockBypass_Enable              ((uint32_t)0x00000400)
00137 #define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_ClockBypass_Disable) || \
00138                                      ((BYPASS) == SDIO_ClockBypass_Enable))
00139 /**
00140   * @}
00141   */
00142
00143 /** @defgroup SDIO_Clock_Power_Save
00144   * @{
00145   */
00146
00147 #define SDIO_ClockPowerSave_Disable         ((uint32_t)0x00000000)
00148 #define SDIO_ClockPowerSave_Enable          ((uint32_t)0x00000200)
00149 #define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_ClockPowerSave_Disable) || \
00150                                         ((SAVE) == SDIO_ClockPowerSave_Enable))
00151 /**
00152   * @}
00153   */
00154
00155 /** @defgroup SDIO_Bus_Wide
00156   * @{
00157   */
00158
00159 #define SDIO_BusWide_1b                     ((uint32_t)0x00000000)
00160 #define SDIO_BusWide_4b                     ((uint32_t)0x00000800)
00161 #define SDIO_BusWide_8b                     ((uint32_t)0x00001000)
00162 #define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BusWide_1b) || ((WIDE) == SDIO_BusWide_4b) || \
00163                                 ((WIDE) == SDIO_BusWide_8b))
00164
00165 /**
00166   * @}
00167   */
00168
00169 /** @defgroup SDIO_Hardware_Flow_Control
00170   * @{
00171   */
00172
00173 #define SDIO_HardwareFlowControl_Disable    ((uint32_t)0x00000000)
00174 #define SDIO_HardwareFlowControl_Enable     ((uint32_t)0x00004000)
00175 #define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HardwareFlowControl_Disable) || \
00176                                                 ((CONTROL) == SDIO_HardwareFlowControl_Enable))
00177 /**
00178   * @}
00179   */
00180
00181 /** @defgroup SDIO_Power_State
00182   * @{
00183   */
00184
00185 #define SDIO_PowerState_OFF                 ((uint32_t)0x00000000)
00186 #define SDIO_PowerState_ON                  ((uint32_t)0x00000003)
00187 #define IS_SDIO_POWER_STATE(STATE) (((STATE) == SDIO_PowerState_OFF) || ((STATE) == SDIO_PowerState_ON))
00188 /**
00189   * @}
00190   */
00191
00192
00193 /** @defgroup SDIO_Interrupt_sources
00194   * @{
00195   */
00196
00197 #define SDIO_IT_CCRCFAIL                    ((uint32_t)0x00000001)
00198 #define SDIO_IT_DCRCFAIL                    ((uint32_t)0x00000002)
00199 #define SDIO_IT_CTIMEOUT                    ((uint32_t)0x00000004)
00200 #define SDIO_IT_DTIMEOUT                    ((uint32_t)0x00000008)
00201 #define SDIO_IT_TXUNDERR                    ((uint32_t)0x00000010)
00202 #define SDIO_IT_RXOVERR                     ((uint32_t)0x00000020)
00203 #define SDIO_IT_CMDREND                     ((uint32_t)0x00000040)
00204 #define SDIO_IT_CMDSENT                     ((uint32_t)0x00000080)
00205 #define SDIO_IT_DATAEND                     ((uint32_t)0x00000100)
00206 #define SDIO_IT_STBITERR                    ((uint32_t)0x00000200)
00207 #define SDIO_IT_DBCKEND                     ((uint32_t)0x00000400)
00208 #define SDIO_IT_CMDACT                      ((uint32_t)0x00000800)
00209 #define SDIO_IT_TXACT                       ((uint32_t)0x00001000)
00210 #define SDIO_IT_RXACT                       ((uint32_t)0x00002000)
00211 #define SDIO_IT_TXFIFOHE                    ((uint32_t)0x00004000)
00212 #define SDIO_IT_RXFIFOHF                    ((uint32_t)0x00008000)
00213 #define SDIO_IT_TXFIFOF                     ((uint32_t)0x00010000)
00214 #define SDIO_IT_RXFIFOF                     ((uint32_t)0x00020000)
00215 #define SDIO_IT_TXFIFOE                     ((uint32_t)0x00040000)
00216 #define SDIO_IT_RXFIFOE                     ((uint32_t)0x00080000)
00217 #define SDIO_IT_TXDAVL                      ((uint32_t)0x00100000)
00218 #define SDIO_IT_RXDAVL                      ((uint32_t)0x00200000)
00219 #define SDIO_IT_SDIOIT                      ((uint32_t)0x00400000)
00220 #define SDIO_IT_CEATAEND                    ((uint32_t)0x00800000)
00221 #define IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00))
00222 /**
00223   * @}
00224   */
00225
00226 /** @defgroup SDIO_Command_Index
00227   * @{
00228   */
00229
00230 #define IS_SDIO_CMD_INDEX(INDEX)            ((INDEX) < 0x40)
00231 /**
00232   * @}
00233   */
00234
00235 /** @defgroup SDIO_Response_Type
00236   * @{
00237   */
00238
00239 #define SDIO_Response_No                    ((uint32_t)0x00000000)
00240 #define SDIO_Response_Short                 ((uint32_t)0x00000040)
00241 #define SDIO_Response_Long                  ((uint32_t)0x000000C0)
00242 #define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_Response_No) || \
00243                                     ((RESPONSE) == SDIO_Response_Short) || \
00244                                     ((RESPONSE) == SDIO_Response_Long))
00245 /**
00246   * @}
00247   */
00248
00249 /** @defgroup SDIO_Wait_Interrupt_State
00250   * @{
00251   */
00252
00253 #define SDIO_Wait_No                        ((uint32_t)0x00000000) /*!< SDIO No Wait, TimeOut is enabled */
00254 #define SDIO_Wait_IT                        ((uint32_t)0x00000100) /*!< SDIO Wait Interrupt Request */
00255 #define SDIO_Wait_Pend                      ((uint32_t)0x00000200) /*!< SDIO Wait End of transfer */
00256 #define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_Wait_No) || ((WAIT) == SDIO_Wait_IT) || \
00257                             ((WAIT) == SDIO_Wait_Pend))
00258 /**
00259   * @}
00260   */
00261
00262 /** @defgroup SDIO_CPSM_State
00263   * @{
00264   */
00265
00266 #define SDIO_CPSM_Disable                    ((uint32_t)0x00000000)
00267 #define SDIO_CPSM_Enable                     ((uint32_t)0x00000400)
00268 #define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_Enable) || ((CPSM) == SDIO_CPSM_Disable))
00269 /**
00270   * @}
00271   */
00272
00273 /** @defgroup SDIO_Response_Registers
00274   * @{
00275   */
00276
00277 #define SDIO_RESP1                          ((uint32_t)0x00000000)
00278 #define SDIO_RESP2                          ((uint32_t)0x00000004)
00279 #define SDIO_RESP3                          ((uint32_t)0x00000008)
00280 #define SDIO_RESP4                          ((uint32_t)0x0000000C)
00281 #define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || ((RESP) == SDIO_RESP2) || \
00282                             ((RESP) == SDIO_RESP3) || ((RESP) == SDIO_RESP4))
00283 /**
00284   * @}
00285   */
00286
00287 /** @defgroup SDIO_Data_Length
00288   * @{
00289   */
00290
00291 #define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)
00292 /**
00293   * @}
00294   */
00295
00296 /** @defgroup SDIO_Data_Block_Size
00297   * @{
00298   */
00299
00300 #define SDIO_DataBlockSize_1b               ((uint32_t)0x00000000)
00301 #define SDIO_DataBlockSize_2b               ((uint32_t)0x00000010)
00302 #define SDIO_DataBlockSize_4b               ((uint32_t)0x00000020)
00303 #define SDIO_DataBlockSize_8b               ((uint32_t)0x00000030)
00304 #define SDIO_DataBlockSize_16b              ((uint32_t)0x00000040)
00305 #define SDIO_DataBlockSize_32b              ((uint32_t)0x00000050)
00306 #define SDIO_DataBlockSize_64b              ((uint32_t)0x00000060)
00307 #define SDIO_DataBlockSize_128b             ((uint32_t)0x00000070)
00308 #define SDIO_DataBlockSize_256b             ((uint32_t)0x00000080)
00309 #define SDIO_DataBlockSize_512b             ((uint32_t)0x00000090)
00310 #define SDIO_DataBlockSize_1024b            ((uint32_t)0x000000A0)
00311 #define SDIO_DataBlockSize_2048b            ((uint32_t)0x000000B0)
00312 #define SDIO_DataBlockSize_4096b            ((uint32_t)0x000000C0)
00313 #define SDIO_DataBlockSize_8192b            ((uint32_t)0x000000D0)
00314 #define SDIO_DataBlockSize_16384b           ((uint32_t)0x000000E0)
00315 #define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DataBlockSize_1b) || \
00316                                   ((SIZE) == SDIO_DataBlockSize_2b) || \
00317                                   ((SIZE) == SDIO_DataBlockSize_4b) || \
00318                                   ((SIZE) == SDIO_DataBlockSize_8b) || \
00319                                   ((SIZE) == SDIO_DataBlockSize_16b) || \
00320                                   ((SIZE) == SDIO_DataBlockSize_32b) || \
00321                                   ((SIZE) == SDIO_DataBlockSize_64b) || \
00322                                   ((SIZE) == SDIO_DataBlockSize_128b) || \
00323                                   ((SIZE) == SDIO_DataBlockSize_256b) || \
00324                                   ((SIZE) == SDIO_DataBlockSize_512b) || \
00325                                   ((SIZE) == SDIO_DataBlockSize_1024b) || \
00326                                   ((SIZE) == SDIO_DataBlockSize_2048b) || \
00327                                   ((SIZE) == SDIO_DataBlockSize_4096b) || \
00328                                   ((SIZE) == SDIO_DataBlockSize_8192b) || \
00329                                   ((SIZE) == SDIO_DataBlockSize_16384b))
00330 /**
00331   * @}
00332   */
00333
00334 /** @defgroup SDIO_Transfer_Direction
00335   * @{
00336   */
00337
00338 #define SDIO_TransferDir_ToCard             ((uint32_t)0x00000000)
00339 #define SDIO_TransferDir_ToSDIO             ((uint32_t)0x00000002)
00340 #define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TransferDir_ToCard) || \
00341                                    ((DIR) == SDIO_TransferDir_ToSDIO))
00342 /**
00343   * @}
00344   */
00345
00346 /** @defgroup SDIO_Transfer_Type
00347   * @{
00348   */
00349
00350 #define SDIO_TransferMode_Block             ((uint32_t)0x00000000)
00351 #define SDIO_TransferMode_Stream            ((uint32_t)0x00000004)
00352 #define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TransferMode_Stream) || \
00353                                      ((MODE) == SDIO_TransferMode_Block))
00354 /**
00355   * @}
00356   */
00357
00358 /** @defgroup SDIO_DPSM_State
00359   * @{
00360   */
00361
00362 #define SDIO_DPSM_Disable                    ((uint32_t)0x00000000)
00363 #define SDIO_DPSM_Enable                     ((uint32_t)0x00000001)
00364 #define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_Enable) || ((DPSM) == SDIO_DPSM_Disable))
00365 /**
00366   * @}
00367   */
00368
00369 /** @defgroup SDIO_Flags
00370   * @{
00371   */
00372
00373 #define SDIO_FLAG_CCRCFAIL                  ((uint32_t)0x00000001)
00374 #define SDIO_FLAG_DCRCFAIL                  ((uint32_t)0x00000002)
00375 #define SDIO_FLAG_CTIMEOUT                  ((uint32_t)0x00000004)
00376 #define SDIO_FLAG_DTIMEOUT                  ((uint32_t)0x00000008)
00377 #define SDIO_FLAG_TXUNDERR                  ((uint32_t)0x00000010)
00378 #define SDIO_FLAG_RXOVERR                   ((uint32_t)0x00000020)
00379 #define SDIO_FLAG_CMDREND                   ((uint32_t)0x00000040)
00380 #define SDIO_FLAG_CMDSENT                   ((uint32_t)0x00000080)
00381 #define SDIO_FLAG_DATAEND                   ((uint32_t)0x00000100)
00382 #define SDIO_FLAG_STBITERR                  ((uint32_t)0x00000200)
00383 #define SDIO_FLAG_DBCKEND                   ((uint32_t)0x00000400)
00384 #define SDIO_FLAG_CMDACT                    ((uint32_t)0x00000800)
00385 #define SDIO_FLAG_TXACT                     ((uint32_t)0x00001000)
00386 #define SDIO_FLAG_RXACT                     ((uint32_t)0x00002000)
00387 #define SDIO_FLAG_TXFIFOHE                  ((uint32_t)0x00004000)
00388 #define SDIO_FLAG_RXFIFOHF                  ((uint32_t)0x00008000)
00389 #define SDIO_FLAG_TXFIFOF                   ((uint32_t)0x00010000)
00390 #define SDIO_FLAG_RXFIFOF                   ((uint32_t)0x00020000)
00391 #define SDIO_FLAG_TXFIFOE                   ((uint32_t)0x00040000)
00392 #define SDIO_FLAG_RXFIFOE                   ((uint32_t)0x00080000)
00393 #define SDIO_FLAG_TXDAVL                    ((uint32_t)0x00100000)
00394 #define SDIO_FLAG_RXDAVL                    ((uint32_t)0x00200000)
00395 #define SDIO_FLAG_SDIOIT                    ((uint32_t)0x00400000)
00396 #define SDIO_FLAG_CEATAEND                  ((uint32_t)0x00800000)
00397 #define IS_SDIO_FLAG(FLAG) (((FLAG)  == SDIO_FLAG_CCRCFAIL) || \
00398                             ((FLAG)  == SDIO_FLAG_DCRCFAIL) || \
00399                             ((FLAG)  == SDIO_FLAG_CTIMEOUT) || \
00400                             ((FLAG)  == SDIO_FLAG_DTIMEOUT) || \
00401                             ((FLAG)  == SDIO_FLAG_TXUNDERR) || \
00402                             ((FLAG)  == SDIO_FLAG_RXOVERR) || \
00403                             ((FLAG)  == SDIO_FLAG_CMDREND) || \
00404                             ((FLAG)  == SDIO_FLAG_CMDSENT) || \
00405                             ((FLAG)  == SDIO_FLAG_DATAEND) || \
00406                             ((FLAG)  == SDIO_FLAG_STBITERR) || \
00407                             ((FLAG)  == SDIO_FLAG_DBCKEND) || \
00408                             ((FLAG)  == SDIO_FLAG_CMDACT) || \
00409                             ((FLAG)  == SDIO_FLAG_TXACT) || \
00410                             ((FLAG)  == SDIO_FLAG_RXACT) || \
00411                             ((FLAG)  == SDIO_FLAG_TXFIFOHE) || \
00412                             ((FLAG)  == SDIO_FLAG_RXFIFOHF) || \
00413                             ((FLAG)  == SDIO_FLAG_TXFIFOF) || \
00414                             ((FLAG)  == SDIO_FLAG_RXFIFOF) || \
00415                             ((FLAG)  == SDIO_FLAG_TXFIFOE) || \
00416                             ((FLAG)  == SDIO_FLAG_RXFIFOE) || \
00417                             ((FLAG)  == SDIO_FLAG_TXDAVL) || \
00418                             ((FLAG)  == SDIO_FLAG_RXDAVL) || \
00419                             ((FLAG)  == SDIO_FLAG_SDIOIT) || \
00420                             ((FLAG)  == SDIO_FLAG_CEATAEND))
00421
00422 #define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00))
00423
00424 #define IS_SDIO_GET_IT(IT) (((IT)  == SDIO_IT_CCRCFAIL) || \
00425                             ((IT)  == SDIO_IT_DCRCFAIL) || \
00426                             ((IT)  == SDIO_IT_CTIMEOUT) || \
00427                             ((IT)  == SDIO_IT_DTIMEOUT) || \
00428                             ((IT)  == SDIO_IT_TXUNDERR) || \
00429                             ((IT)  == SDIO_IT_RXOVERR) || \
00430                             ((IT)  == SDIO_IT_CMDREND) || \
00431                             ((IT)  == SDIO_IT_CMDSENT) || \
00432                             ((IT)  == SDIO_IT_DATAEND) || \
00433                             ((IT)  == SDIO_IT_STBITERR) || \
00434                             ((IT)  == SDIO_IT_DBCKEND) || \
00435                             ((IT)  == SDIO_IT_CMDACT) || \
00436                             ((IT)  == SDIO_IT_TXACT) || \
00437                             ((IT)  == SDIO_IT_RXACT) || \
00438                             ((IT)  == SDIO_IT_TXFIFOHE) || \
00439                             ((IT)  == SDIO_IT_RXFIFOHF) || \
00440                             ((IT)  == SDIO_IT_TXFIFOF) || \
00441                             ((IT)  == SDIO_IT_RXFIFOF) || \
00442                             ((IT)  == SDIO_IT_TXFIFOE) || \
00443                             ((IT)  == SDIO_IT_RXFIFOE) || \
00444                             ((IT)  == SDIO_IT_TXDAVL) || \
00445                             ((IT)  == SDIO_IT_RXDAVL) || \
00446                             ((IT)  == SDIO_IT_SDIOIT) || \
00447                             ((IT)  == SDIO_IT_CEATAEND))
00448
00449 #define IS_SDIO_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00))
00450
00451 /**
00452   * @}
00453   */
00454
00455 /** @defgroup SDIO_Read_Wait_Mode
00456   * @{
00457   */
00458
00459 #define SDIO_ReadWaitMode_CLK               ((uint32_t)0x00000001)
00460 #define SDIO_ReadWaitMode_DATA2             ((uint32_t)0x00000000)
00461 #define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_ReadWaitMode_CLK) || \
00462                                      ((MODE) == SDIO_ReadWaitMode_DATA2))
00463 /**
00464   * @}
00465   */
00466
00467 /**
00468   * @}
00469   */
00470
00471 /** @defgroup SDIO_Exported_Macros
00472   * @{
00473   */
00474
00475 /**
00476   * @}
00477   */
00478
00479 /** @defgroup SDIO_Exported_Functions
00480   * @{
00481   */
00482
00483 void SDIO_DeInit(void);
00484 void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct);
00485 void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct);
00486 void SDIO_ClockCmd(FunctionalState NewState);
00487 void SDIO_SetPowerState(uint32_t SDIO_PowerState);
00488 uint32_t SDIO_GetPowerState(void);
00489 void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState);
00490 void SDIO_DMACmd(FunctionalState NewState);
00491 void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct);
00492 void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct);
00493 uint8_t SDIO_GetCommandResponse(void);
00494 uint32_t SDIO_GetResponse(uint32_t SDIO_RESP);
00495 void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct);
00496 void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct);
00497 uint32_t SDIO_GetDataCounter(void);
00498 uint32_t SDIO_ReadData(void);
00499 void SDIO_WriteData(uint32_t Data);
00500 uint32_t SDIO_GetFIFOCount(void);
00501 void SDIO_StartSDIOReadWait(FunctionalState NewState);
00502 void SDIO_StopSDIOReadWait(FunctionalState NewState);
00503 void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode);
00504 void SDIO_SetSDIOOperation(FunctionalState NewState);
00505 void SDIO_SendSDIOSuspendCmd(FunctionalState NewState);
00506 void SDIO_CommandCompletionCmd(FunctionalState NewState);
00507 void SDIO_CEATAITCmd(FunctionalState NewState);
00508 void SDIO_SendCEATACmd(FunctionalState NewState);
00509 FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG);
00510 void SDIO_ClearFlag(uint32_t SDIO_FLAG);
00511 ITStatus SDIO_GetITStatus(uint32_t SDIO_IT);
00512 void SDIO_ClearITPendingBit(uint32_t SDIO_IT);
00513
00514 #ifdef __cplusplus
00515 }
00516 #endif
00517
00518 #endif /* __STM32F10x_SDIO_H */
00519 /**
00520   * @}
00521   */
00522
00523 /**
00524   * @}
00525   */
00526
00527 /**
00528   * @}
00529   */
00530
00531 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_spi.c Source File

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stm32f10x_spi.c

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f10x_spi.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    11-March-2011
00007   * @brief   This file provides all the SPI firmware functions.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x_spi.h"
00024 #include "stm32f10x_rcc.h"
00025
00026 /** @addtogroup STM32F10x_StdPeriph_Driver
00027   * @{
00028   */
00029
00030 /** @defgroup SPI
00031   * @brief SPI driver modules
00032   * @{
00033   */
00034
00035 /** @defgroup SPI_Private_TypesDefinitions
00036   * @{
00037   */
00038
00039 /**
00040   * @}
00041   */
00042
00043
00044 /** @defgroup SPI_Private_Defines
00045   * @{
00046   */
00047
00048 /* SPI SPE mask */
00049 #define CR1_SPE_Set          ((uint16_t)0x0040)
00050 #define CR1_SPE_Reset        ((uint16_t)0xFFBF)
00051
00052 /* I2S I2SE mask */
00053 #define I2SCFGR_I2SE_Set     ((uint16_t)0x0400)
00054 #define I2SCFGR_I2SE_Reset   ((uint16_t)0xFBFF)
00055
00056 /* SPI CRCNext mask */
00057 #define CR1_CRCNext_Set      ((uint16_t)0x1000)
00058
00059 /* SPI CRCEN mask */
00060 #define CR1_CRCEN_Set        ((uint16_t)0x2000)
00061 #define CR1_CRCEN_Reset      ((uint16_t)0xDFFF)
00062
00063 /* SPI SSOE mask */
00064 #define CR2_SSOE_Set         ((uint16_t)0x0004)
00065 #define CR2_SSOE_Reset       ((uint16_t)0xFFFB)
00066
00067 /* SPI registers Masks */
00068 #define CR1_CLEAR_Mask       ((uint16_t)0x3040)
00069 #define I2SCFGR_CLEAR_Mask   ((uint16_t)0xF040)
00070
00071 /* SPI or I2S mode selection masks */
00072 #define SPI_Mode_Select      ((uint16_t)0xF7FF)
00073 #define I2S_Mode_Select      ((uint16_t)0x0800)
00074
00075 /* I2S clock source selection masks */
00076 #define I2S2_CLOCK_SRC       ((uint32_t)(0x00020000))
00077 #define I2S3_CLOCK_SRC       ((uint32_t)(0x00040000))
00078 #define I2S_MUL_MASK         ((uint32_t)(0x0000F000))
00079 #define I2S_DIV_MASK         ((uint32_t)(0x000000F0))
00080
00081 /**
00082   * @}
00083   */
00084
00085 /** @defgroup SPI_Private_Macros
00086   * @{
00087   */
00088
00089 /**
00090   * @}
00091   */
00092
00093 /** @defgroup SPI_Private_Variables
00094   * @{
00095   */
00096
00097 /**
00098   * @}
00099   */
00100
00101 /** @defgroup SPI_Private_FunctionPrototypes
00102   * @{
00103   */
00104
00105 /**
00106   * @}
00107   */
00108
00109 /** @defgroup SPI_Private_Functions
00110   * @{
00111   */
00112
00113 /**
00114   * @brief  Deinitializes the SPIx peripheral registers to their default
00115   *         reset values (Affects also the I2Ss).
00116   * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
00117   * @retval None
00118   */
00119 void SPI_I2S_DeInit(SPI_TypeDef* SPIx)
00120 {
00121   /* Check the parameters */
00122   assert_param(IS_SPI_ALL_PERIPH(SPIx));
00123
00124   if (SPIx == SPI1)
00125   {
00126     /* Enable SPI1 reset state */
00127     RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE);
00128     /* Release SPI1 from reset state */
00129     RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE);
00130   }
00131   else if (SPIx == SPI2)
00132   {
00133     /* Enable SPI2 reset state */
00134     RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE);
00135     /* Release SPI2 from reset state */
00136     RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE);
00137   }
00138   else
00139   {
00140     if (SPIx == SPI3)
00141     {
00142       /* Enable SPI3 reset state */
00143       RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE);
00144       /* Release SPI3 from reset state */
00145       RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE);
00146     }
00147   }
00148 }
00149
00150 /**
00151   * @brief  Initializes the SPIx peripheral according to the specified
00152   *         parameters in the SPI_InitStruct.
00153   * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
00154   * @param  SPI_InitStruct: pointer to a SPI_InitTypeDef structure that
00155   *         contains the configuration information for the specified SPI peripheral.
00156   * @retval None
00157   */
00158 void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct)
00159 {
00160   uint16_t tmpreg = 0;
00161
00162   /* check the parameters */
00163   assert_param(IS_SPI_ALL_PERIPH(SPIx));
00164
00165   /* Check the SPI parameters */
00166   assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction));
00167   assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode));
00168   assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize));
00169   assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL));
00170   assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA));
00171   assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS));
00172   assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler));
00173   assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit));
00174   assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial));
00175
00176 /*---------------------------- SPIx CR1 Configuration ------------------------*/
00177   /* Get the SPIx CR1 value */
00178   tmpreg = SPIx->CR1;
00179   /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */
00180   tmpreg &= CR1_CLEAR_Mask;
00181   /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler
00182      master/salve mode, CPOL and CPHA */
00183   /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */
00184   /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */
00185   /* Set LSBFirst bit according to SPI_FirstBit value */
00186   /* Set BR bits according to SPI_BaudRatePrescaler value */
00187   /* Set CPOL bit according to SPI_CPOL value */
00188   /* Set CPHA bit according to SPI_CPHA value */
00189   tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode |
00190                   SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL |
00191                   SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS |
00192                   SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit);
00193   /* Write to SPIx CR1 */
00194   SPIx->CR1 = tmpreg;
00195
00196   /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
00197   SPIx->I2SCFGR &= SPI_Mode_Select;
00198
00199 /*---------------------------- SPIx CRCPOLY Configuration --------------------*/
00200   /* Write to SPIx CRCPOLY */
00201   SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial;
00202 }
00203
00204 /**
00205   * @brief  Initializes the SPIx peripheral according to the specified
00206   *         parameters in the I2S_InitStruct.
00207   * @param  SPIx: where x can be  2 or 3 to select the SPI peripheral
00208   *         (configured in I2S mode).
00209   * @param  I2S_InitStruct: pointer to an I2S_InitTypeDef structure that
00210   *         contains the configuration information for the specified SPI peripheral
00211   *         configured in I2S mode.
00212   * @note
00213   *  The function calculates the optimal prescaler needed to obtain the most
00214   *  accurate audio frequency (depending on the I2S clock source, the PLL values
00215   *  and the product configuration). But in case the prescaler value is greater
00216   *  than 511, the default value (0x02) will be configured instead.  *
00217   * @retval None
00218   */
00219 void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct)
00220 {
00221   uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;
00222   uint32_t tmp = 0;
00223   RCC_ClocksTypeDef RCC_Clocks;
00224   uint32_t sourceclock = 0;
00225
00226   /* Check the I2S parameters */
00227   assert_param(IS_SPI_23_PERIPH(SPIx));
00228   assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode));
00229   assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard));
00230   assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat));
00231   assert_param(IS_I2S_MCLK_OUTPUT(I2S_InitStruct->I2S_MCLKOutput));
00232   assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq));
00233   assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL));
00234
00235 /*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/
00236   /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
00237   SPIx->I2SCFGR &= I2SCFGR_CLEAR_Mask;
00238   SPIx->I2SPR = 0x0002;
00239
00240   /* Get the I2SCFGR register value */
00241   tmpreg = SPIx->I2SCFGR;
00242
00243   /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/
00244   if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default)
00245   {
00246     i2sodd = (uint16_t)0;
00247     i2sdiv = (uint16_t)2;
00248   }
00249   /* If the requested audio frequency is not the default, compute the prescaler */
00250   else
00251   {
00252     /* Check the frame length (For the Prescaler computing) */
00253     if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b)
00254     {
00255       /* Packet length is 16 bits */
00256       packetlength = 1;
00257     }
00258     else
00259     {
00260       /* Packet length is 32 bits */
00261       packetlength = 2;
00262     }
00263
00264     /* Get the I2S clock source mask depending on the peripheral number */
00265     if(((uint32_t)SPIx) == SPI2_BASE)
00266     {
00267       /* The mask is relative to I2S2 */
00268       tmp = I2S2_CLOCK_SRC;
00269     }
00270     else
00271     {
00272       /* The mask is relative to I2S3 */
00273       tmp = I2S3_CLOCK_SRC;
00274     }
00275
00276     /* Check the I2S clock source configuration depending on the Device:
00277        Only Connectivity line devices have the PLL3 VCO clock */
00278 #ifdef STM32F10X_CL
00279     if((RCC->CFGR2 & tmp) != 0)
00280     {
00281       /* Get the configuration bits of RCC PLL3 multiplier */
00282       tmp = (uint32_t)((RCC->CFGR2 & I2S_MUL_MASK) >> 12);
00283
00284       /* Get the value of the PLL3 multiplier */
00285       if((tmp > 5) && (tmp < 15))
00286       {
00287         /* Multiplier is between 8 and 14 (value 15 is forbidden) */
00288         tmp += 2;
00289       }
00290       else
00291       {
00292         if (tmp == 15)
00293         {
00294           /* Multiplier is 20 */
00295           tmp = 20;
00296         }
00297       }
00298       /* Get the PREDIV2 value */
00299       sourceclock = (uint32_t)(((RCC->CFGR2 & I2S_DIV_MASK) >> 4) + 1);
00300
00301       /* Calculate the Source Clock frequency based on PLL3 and PREDIV2 values */
00302       sourceclock = (uint32_t) ((HSE_Value / sourceclock) * tmp * 2);
00303     }
00304     else
00305     {
00306       /* I2S Clock source is System clock: Get System Clock frequency */
00307       RCC_GetClocksFreq(&RCC_Clocks);
00308
00309       /* Get the source clock value: based on System Clock value */
00310       sourceclock = RCC_Clocks.SYSCLK_Frequency;
00311     }
00312 #else /* STM32F10X_HD */
00313     /* I2S Clock source is System clock: Get System Clock frequency */
00314     RCC_GetClocksFreq(&RCC_Clocks);
00315
00316     /* Get the source clock value: based on System Clock value */
00317     sourceclock = RCC_Clocks.SYSCLK_Frequency;
00318 #endif /* STM32F10X_CL */
00319
00320     /* Compute the Real divider depending on the MCLK output state with a floating point */
00321     if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable)
00322     {
00323       /* MCLK output is enabled */
00324       tmp = (uint16_t)(((((sourceclock / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5);
00325     }
00326     else
00327     {
00328       /* MCLK output is disabled */
00329       tmp = (uint16_t)(((((sourceclock / (32 * packetlength)) *10 ) / I2S_InitStruct->I2S_AudioFreq)) + 5);
00330     }
00331
00332     /* Remove the floating point */
00333     tmp = tmp / 10;
00334
00335     /* Check the parity of the divider */
00336     i2sodd = (uint16_t)(tmp & (uint16_t)0x0001);
00337
00338     /* Compute the i2sdiv prescaler */
00339     i2sdiv = (uint16_t)((tmp - i2sodd) / 2);
00340
00341     /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
00342     i2sodd = (uint16_t) (i2sodd << 8);
00343   }
00344
00345   /* Test if the divider is 1 or 0 or greater than 0xFF */
00346   if ((i2sdiv < 2) || (i2sdiv > 0xFF))
00347   {
00348     /* Set the default values */
00349     i2sdiv = 2;
00350     i2sodd = 0;
00351   }
00352
00353   /* Write to SPIx I2SPR register the computed value */
00354   SPIx->I2SPR = (uint16_t)(i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput));
00355
00356   /* Configure the I2S with the SPI_InitStruct values */
00357   tmpreg |= (uint16_t)(I2S_Mode_Select | (uint16_t)(I2S_InitStruct->I2S_Mode | \
00358                   (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \
00359                   (uint16_t)I2S_InitStruct->I2S_CPOL))));
00360
00361   /* Write to SPIx I2SCFGR */
00362   SPIx->I2SCFGR = tmpreg;
00363 }
00364
00365 /**
00366   * @brief  Fills each SPI_InitStruct member with its default value.
00367   * @param  SPI_InitStruct : pointer to a SPI_InitTypeDef structure which will be initialized.
00368   * @retval None
00369   */
00370 void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct)
00371 {
00372 /*--------------- Reset SPI init structure parameters values -----------------*/
00373   /* Initialize the SPI_Direction member */
00374   SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex;
00375   /* initialize the SPI_Mode member */
00376   SPI_InitStruct->SPI_Mode = SPI_Mode_Slave;
00377   /* initialize the SPI_DataSize member */
00378   SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b;
00379   /* Initialize the SPI_CPOL member */
00380   SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low;
00381   /* Initialize the SPI_CPHA member */
00382   SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge;
00383   /* Initialize the SPI_NSS member */
00384   SPI_InitStruct->SPI_NSS = SPI_NSS_Hard;
00385   /* Initialize the SPI_BaudRatePrescaler member */
00386   SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
00387   /* Initialize the SPI_FirstBit member */
00388   SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB;
00389   /* Initialize the SPI_CRCPolynomial member */
00390   SPI_InitStruct->SPI_CRCPolynomial = 7;
00391 }
00392
00393 /**
00394   * @brief  Fills each I2S_InitStruct member with its default value.
00395   * @param  I2S_InitStruct : pointer to a I2S_InitTypeDef structure which will be initialized.
00396   * @retval None
00397   */
00398 void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct)
00399 {
00400 /*--------------- Reset I2S init structure parameters values -----------------*/
00401   /* Initialize the I2S_Mode member */
00402   I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx;
00403
00404   /* Initialize the I2S_Standard member */
00405   I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips;
00406
00407   /* Initialize the I2S_DataFormat member */
00408   I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b;
00409
00410   /* Initialize the I2S_MCLKOutput member */
00411   I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable;
00412
00413   /* Initialize the I2S_AudioFreq member */
00414   I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default;
00415
00416   /* Initialize the I2S_CPOL member */
00417   I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low;
00418 }
00419
00420 /**
00421   * @brief  Enables or disables the specified SPI peripheral.
00422   * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
00423   * @param  NewState: new state of the SPIx peripheral.
00424   *   This parameter can be: ENABLE or DISABLE.
00425   * @retval None
00426   */
00427 void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
00428 {
00429   /* Check the parameters */
00430   assert_param(IS_SPI_ALL_PERIPH(SPIx));
00431   assert_param(IS_FUNCTIONAL_STATE(NewState));
00432   if (NewState != DISABLE)
00433   {
00434     /* Enable the selected SPI peripheral */
00435     SPIx->CR1 |= CR1_SPE_Set;
00436   }
00437   else
00438   {
00439     /* Disable the selected SPI peripheral */
00440     SPIx->CR1 &= CR1_SPE_Reset;
00441   }
00442 }
00443
00444 /**
00445   * @brief  Enables or disables the specified SPI peripheral (in I2S mode).
00446   * @param  SPIx: where x can be 2 or 3 to select the SPI peripheral.
00447   * @param  NewState: new state of the SPIx peripheral.
00448   *   This parameter can be: ENABLE or DISABLE.
00449   * @retval None
00450   */
00451 void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
00452 {
00453   /* Check the parameters */
00454   assert_param(IS_SPI_23_PERIPH(SPIx));
00455   assert_param(IS_FUNCTIONAL_STATE(NewState));
00456   if (NewState != DISABLE)
00457   {
00458     /* Enable the selected SPI peripheral (in I2S mode) */
00459     SPIx->I2SCFGR |= I2SCFGR_I2SE_Set;
00460   }
00461   else
00462   {
00463     /* Disable the selected SPI peripheral (in I2S mode) */
00464     SPIx->I2SCFGR &= I2SCFGR_I2SE_Reset;
00465   }
00466 }
00467
00468 /**
00469   * @brief  Enables or disables the specified SPI/I2S interrupts.
00470   * @param  SPIx: where x can be
00471   *   - 1, 2 or 3 in SPI mode
00472   *   - 2 or 3 in I2S mode
00473   * @param  SPI_I2S_IT: specifies the SPI/I2S interrupt source to be enabled or disabled.
00474   *   This parameter can be one of the following values:
00475   *     @arg SPI_I2S_IT_TXE: Tx buffer empty interrupt mask
00476   *     @arg SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask
00477   *     @arg SPI_I2S_IT_ERR: Error interrupt mask
00478   * @param  NewState: new state of the specified SPI/I2S interrupt.
00479   *   This parameter can be: ENABLE or DISABLE.
00480   * @retval None
00481   */
00482 void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState)
00483 {
00484   uint16_t itpos = 0, itmask = 0 ;
00485   /* Check the parameters */
00486   assert_param(IS_SPI_ALL_PERIPH(SPIx));
00487   assert_param(IS_FUNCTIONAL_STATE(NewState));
00488   assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT));
00489
00490   /* Get the SPI/I2S IT index */
00491   itpos = SPI_I2S_IT >> 4;
00492
00493   /* Set the IT mask */
00494   itmask = (uint16_t)1 << (uint16_t)itpos;
00495
00496   if (NewState != DISABLE)
00497   {
00498     /* Enable the selected SPI/I2S interrupt */
00499     SPIx->CR2 |= itmask;
00500   }
00501   else
00502   {
00503     /* Disable the selected SPI/I2S interrupt */
00504     SPIx->CR2 &= (uint16_t)~itmask;
00505   }
00506 }
00507
00508 /**
00509   * @brief  Enables or disables the SPIx/I2Sx DMA interface.
00510   * @param  SPIx: where x can be
00511   *   - 1, 2 or 3 in SPI mode
00512   *   - 2 or 3 in I2S mode
00513   * @param  SPI_I2S_DMAReq: specifies the SPI/I2S DMA transfer request to be enabled or disabled.
00514   *   This parameter can be any combination of the following values:
00515   *     @arg SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request
00516   *     @arg SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request
00517   * @param  NewState: new state of the selected SPI/I2S DMA transfer request.
00518   *   This parameter can be: ENABLE or DISABLE.
00519   * @retval None
00520   */
00521 void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState)
00522 {
00523   /* Check the parameters */
00524   assert_param(IS_SPI_ALL_PERIPH(SPIx));
00525   assert_param(IS_FUNCTIONAL_STATE(NewState));
00526   assert_param(IS_SPI_I2S_DMAREQ(SPI_I2S_DMAReq));
00527   if (NewState != DISABLE)
00528   {
00529     /* Enable the selected SPI/I2S DMA requests */
00530     SPIx->CR2 |= SPI_I2S_DMAReq;
00531   }
00532   else
00533   {
00534     /* Disable the selected SPI/I2S DMA requests */
00535     SPIx->CR2 &= (uint16_t)~SPI_I2S_DMAReq;
00536   }
00537 }
00538
00539 /**
00540   * @brief  Transmits a Data through the SPIx/I2Sx peripheral.
00541   * @param  SPIx: where x can be
00542   *   - 1, 2 or 3 in SPI mode
00543   *   - 2 or 3 in I2S mode
00544   * @param  Data : Data to be transmitted.
00545   * @retval None
00546   */
00547 void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data)
00548 {
00549   /* Check the parameters */
00550   assert_param(IS_SPI_ALL_PERIPH(SPIx));
00551
00552   /* Write in the DR register the data to be sent */
00553   SPIx->DR = Data;
00554 }
00555
00556 /**
00557   * @brief  Returns the most recent received data by the SPIx/I2Sx peripheral.
00558   * @param  SPIx: where x can be
00559   *   - 1, 2 or 3 in SPI mode
00560   *   - 2 or 3 in I2S mode
00561   * @retval The value of the received data.
00562   */
00563 uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx)
00564 {
00565   /* Check the parameters */
00566   assert_param(IS_SPI_ALL_PERIPH(SPIx));
00567
00568   /* Return the data in the DR register */
00569   return SPIx->DR;
00570 }
00571
00572 /**
00573   * @brief  Configures internally by software the NSS pin for the selected SPI.
00574   * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
00575   * @param  SPI_NSSInternalSoft: specifies the SPI NSS internal state.
00576   *   This parameter can be one of the following values:
00577   *     @arg SPI_NSSInternalSoft_Set: Set NSS pin internally
00578   *     @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally
00579   * @retval None
00580   */
00581 void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft)
00582 {
00583   /* Check the parameters */
00584   assert_param(IS_SPI_ALL_PERIPH(SPIx));
00585   assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft));
00586   if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset)
00587   {
00588     /* Set NSS pin internally by software */
00589     SPIx->CR1 |= SPI_NSSInternalSoft_Set;
00590   }
00591   else
00592   {
00593     /* Reset NSS pin internally by software */
00594     SPIx->CR1 &= SPI_NSSInternalSoft_Reset;
00595   }
00596 }
00597
00598 /**
00599   * @brief  Enables or disables the SS output for the selected SPI.
00600   * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
00601   * @param  NewState: new state of the SPIx SS output.
00602   *   This parameter can be: ENABLE or DISABLE.
00603   * @retval None
00604   */
00605 void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState)
00606 {
00607   /* Check the parameters */
00608   assert_param(IS_SPI_ALL_PERIPH(SPIx));
00609   assert_param(IS_FUNCTIONAL_STATE(NewState));
00610   if (NewState != DISABLE)
00611   {
00612     /* Enable the selected SPI SS output */
00613     SPIx->CR2 |= CR2_SSOE_Set;
00614   }
00615   else
00616   {
00617     /* Disable the selected SPI SS output */
00618     SPIx->CR2 &= CR2_SSOE_Reset;
00619   }
00620 }
00621
00622 /**
00623   * @brief  Configures the data size for the selected SPI.
00624   * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
00625   * @param  SPI_DataSize: specifies the SPI data size.
00626   *   This parameter can be one of the following values:
00627   *     @arg SPI_DataSize_16b: Set data frame format to 16bit
00628   *     @arg SPI_DataSize_8b: Set data frame format to 8bit
00629   * @retval None
00630   */
00631 void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize)
00632 {
00633   /* Check the parameters */
00634   assert_param(IS_SPI_ALL_PERIPH(SPIx));
00635   assert_param(IS_SPI_DATASIZE(SPI_DataSize));
00636   /* Clear DFF bit */
00637   SPIx->CR1 &= (uint16_t)~SPI_DataSize_16b;
00638   /* Set new DFF bit value */
00639   SPIx->CR1 |= SPI_DataSize;
00640 }
00641
00642 /**
00643   * @brief  Transmit the SPIx CRC value.
00644   * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
00645   * @retval None
00646   */
00647 void SPI_TransmitCRC(SPI_TypeDef* SPIx)
00648 {
00649   /* Check the parameters */
00650   assert_param(IS_SPI_ALL_PERIPH(SPIx));
00651
00652   /* Enable the selected SPI CRC transmission */
00653   SPIx->CR1 |= CR1_CRCNext_Set;
00654 }
00655
00656 /**
00657   * @brief  Enables or disables the CRC value calculation of the transferred bytes.
00658   * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
00659   * @param  NewState: new state of the SPIx CRC value calculation.
00660   *   This parameter can be: ENABLE or DISABLE.
00661   * @retval None
00662   */
00663 void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState)
00664 {
00665   /* Check the parameters */
00666   assert_param(IS_SPI_ALL_PERIPH(SPIx));
00667   assert_param(IS_FUNCTIONAL_STATE(NewState));
00668   if (NewState != DISABLE)
00669   {
00670     /* Enable the selected SPI CRC calculation */
00671     SPIx->CR1 |= CR1_CRCEN_Set;
00672   }
00673   else
00674   {
00675     /* Disable the selected SPI CRC calculation */
00676     SPIx->CR1 &= CR1_CRCEN_Reset;
00677   }
00678 }
00679
00680 /**
00681   * @brief  Returns the transmit or the receive CRC register value for the specified SPI.
00682   * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
00683   * @param  SPI_CRC: specifies the CRC register to be read.
00684   *   This parameter can be one of the following values:
00685   *     @arg SPI_CRC_Tx: Selects Tx CRC register
00686   *     @arg SPI_CRC_Rx: Selects Rx CRC register
00687   * @retval The selected CRC register value..
00688   */
00689 uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC)
00690 {
00691   uint16_t crcreg = 0;
00692   /* Check the parameters */
00693   assert_param(IS_SPI_ALL_PERIPH(SPIx));
00694   assert_param(IS_SPI_CRC(SPI_CRC));
00695   if (SPI_CRC != SPI_CRC_Rx)
00696   {
00697     /* Get the Tx CRC register */
00698     crcreg = SPIx->TXCRCR;
00699   }
00700   else
00701   {
00702     /* Get the Rx CRC register */
00703     crcreg = SPIx->RXCRCR;
00704   }
00705   /* Return the selected CRC register */
00706   return crcreg;
00707 }
00708
00709 /**
00710   * @brief  Returns the CRC Polynomial register value for the specified SPI.
00711   * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
00712   * @retval The CRC Polynomial register value.
00713   */
00714 uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx)
00715 {
00716   /* Check the parameters */
00717   assert_param(IS_SPI_ALL_PERIPH(SPIx));
00718
00719   /* Return the CRC polynomial register */
00720   return SPIx->CRCPR;
00721 }
00722
00723 /**
00724   * @brief  Selects the data transfer direction in bi-directional mode for the specified SPI.
00725   * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
00726   * @param  SPI_Direction: specifies the data transfer direction in bi-directional mode.
00727   *   This parameter can be one of the following values:
00728   *     @arg SPI_Direction_Tx: Selects Tx transmission direction
00729   *     @arg SPI_Direction_Rx: Selects Rx receive direction
00730   * @retval None
00731   */
00732 void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction)
00733 {
00734   /* Check the parameters */
00735   assert_param(IS_SPI_ALL_PERIPH(SPIx));
00736   assert_param(IS_SPI_DIRECTION(SPI_Direction));
00737   if (SPI_Direction == SPI_Direction_Tx)
00738   {
00739     /* Set the Tx only mode */
00740     SPIx->CR1 |= SPI_Direction_Tx;
00741   }
00742   else
00743   {
00744     /* Set the Rx only mode */
00745     SPIx->CR1 &= SPI_Direction_Rx;
00746   }
00747 }
00748
00749 /**
00750   * @brief  Checks whether the specified SPI/I2S flag is set or not.
00751   * @param  SPIx: where x can be
00752   *   - 1, 2 or 3 in SPI mode
00753   *   - 2 or 3 in I2S mode
00754   * @param  SPI_I2S_FLAG: specifies the SPI/I2S flag to check.
00755   *   This parameter can be one of the following values:
00756   *     @arg SPI_I2S_FLAG_TXE: Transmit buffer empty flag.
00757   *     @arg SPI_I2S_FLAG_RXNE: Receive buffer not empty flag.
00758   *     @arg SPI_I2S_FLAG_BSY: Busy flag.
00759   *     @arg SPI_I2S_FLAG_OVR: Overrun flag.
00760   *     @arg SPI_FLAG_MODF: Mode Fault flag.
00761   *     @arg SPI_FLAG_CRCERR: CRC Error flag.
00762   *     @arg I2S_FLAG_UDR: Underrun Error flag.
00763   *     @arg I2S_FLAG_CHSIDE: Channel Side flag.
00764   * @retval The new state of SPI_I2S_FLAG (SET or RESET).
00765   */
00766 FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)
00767 {
00768   FlagStatus bitstatus = RESET;
00769   /* Check the parameters */
00770   assert_param(IS_SPI_ALL_PERIPH(SPIx));
00771   assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG));
00772   /* Check the status of the specified SPI/I2S flag */
00773   if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET)
00774   {
00775     /* SPI_I2S_FLAG is set */
00776     bitstatus = SET;
00777   }
00778   else
00779   {
00780     /* SPI_I2S_FLAG is reset */
00781     bitstatus = RESET;
00782   }
00783   /* Return the SPI_I2S_FLAG status */
00784   return  bitstatus;
00785 }
00786
00787 /**
00788   * @brief  Clears the SPIx CRC Error (CRCERR) flag.
00789   * @param  SPIx: where x can be
00790   *   - 1, 2 or 3 in SPI mode
00791   * @param  SPI_I2S_FLAG: specifies the SPI flag to clear.
00792   *   This function clears only CRCERR flag.
00793   * @note
00794   *   - OVR (OverRun error) flag is cleared by software sequence: a read
00795   *     operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by a read
00796   *     operation to SPI_SR register (SPI_I2S_GetFlagStatus()).
00797   *   - UDR (UnderRun error) flag is cleared by a read operation to
00798   *     SPI_SR register (SPI_I2S_GetFlagStatus()).
00799   *   - MODF (Mode Fault) flag is cleared by software sequence: a read/write
00800   *     operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by a
00801   *     write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI).
00802   * @retval None
00803   */
00804 void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)
00805 {
00806   /* Check the parameters */
00807   assert_param(IS_SPI_ALL_PERIPH(SPIx));
00808   assert_param(IS_SPI_I2S_CLEAR_FLAG(SPI_I2S_FLAG));
00809
00810     /* Clear the selected SPI CRC Error (CRCERR) flag */
00811     SPIx->SR = (uint16_t)~SPI_I2S_FLAG;
00812 }
00813
00814 /**
00815   * @brief  Checks whether the specified SPI/I2S interrupt has occurred or not.
00816   * @param  SPIx: where x can be
00817   *   - 1, 2 or 3 in SPI mode
00818   *   - 2 or 3 in I2S mode
00819   * @param  SPI_I2S_IT: specifies the SPI/I2S interrupt source to check.
00820   *   This parameter can be one of the following values:
00821   *     @arg SPI_I2S_IT_TXE: Transmit buffer empty interrupt.
00822   *     @arg SPI_I2S_IT_RXNE: Receive buffer not empty interrupt.
00823   *     @arg SPI_I2S_IT_OVR: Overrun interrupt.
00824   *     @arg SPI_IT_MODF: Mode Fault interrupt.
00825   *     @arg SPI_IT_CRCERR: CRC Error interrupt.
00826   *     @arg I2S_IT_UDR: Underrun Error interrupt.
00827   * @retval The new state of SPI_I2S_IT (SET or RESET).
00828   */
00829 ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)
00830 {
00831   ITStatus bitstatus = RESET;
00832   uint16_t itpos = 0, itmask = 0, enablestatus = 0;
00833
00834   /* Check the parameters */
00835   assert_param(IS_SPI_ALL_PERIPH(SPIx));
00836   assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT));
00837
00838   /* Get the SPI/I2S IT index */
00839   itpos = 0x01 << (SPI_I2S_IT & 0x0F);
00840
00841   /* Get the SPI/I2S IT mask */
00842   itmask = SPI_I2S_IT >> 4;
00843
00844   /* Set the IT mask */
00845   itmask = 0x01 << itmask;
00846
00847   /* Get the SPI_I2S_IT enable bit status */
00848   enablestatus = (SPIx->CR2 & itmask) ;
00849
00850   /* Check the status of the specified SPI/I2S interrupt */
00851   if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus)
00852   {
00853     /* SPI_I2S_IT is set */
00854     bitstatus = SET;
00855   }
00856   else
00857   {
00858     /* SPI_I2S_IT is reset */
00859     bitstatus = RESET;
00860   }
00861   /* Return the SPI_I2S_IT status */
00862   return bitstatus;
00863 }
00864
00865 /**
00866   * @brief  Clears the SPIx CRC Error (CRCERR) interrupt pending bit.
00867   * @param  SPIx: where x can be
00868   *   - 1, 2 or 3 in SPI mode
00869   * @param  SPI_I2S_IT: specifies the SPI interrupt pending bit to clear.
00870   *   This function clears only CRCERR interrupt pending bit.
00871   * @note
00872   *   - OVR (OverRun Error) interrupt pending bit is cleared by software
00873   *     sequence: a read operation to SPI_DR register (SPI_I2S_ReceiveData())
00874   *     followed by a read operation to SPI_SR register (SPI_I2S_GetITStatus()).
00875   *   - UDR (UnderRun Error) interrupt pending bit is cleared by a read
00876   *     operation to SPI_SR register (SPI_I2S_GetITStatus()).
00877   *   - MODF (Mode Fault) interrupt pending bit is cleared by software sequence:
00878   *     a read/write operation to SPI_SR register (SPI_I2S_GetITStatus())
00879   *     followed by a write operation to SPI_CR1 register (SPI_Cmd() to enable
00880   *     the SPI).
00881   * @retval None
00882   */
00883 void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)
00884 {
00885   uint16_t itpos = 0;
00886   /* Check the parameters */
00887   assert_param(IS_SPI_ALL_PERIPH(SPIx));
00888   assert_param(IS_SPI_I2S_CLEAR_IT(SPI_I2S_IT));
00889
00890   /* Get the SPI IT index */
00891   itpos = 0x01 << (SPI_I2S_IT & 0x0F);
00892
00893   /* Clear the selected SPI CRC Error (CRCERR) interrupt pending bit */
00894   SPIx->SR = (uint16_t)~itpos;
00895 }
00896 /**
00897   * @}
00898   */
00899
00900 /**
00901   * @}
00902   */
00903
00904 /**
00905   * @}
00906   */
00907
00908 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_spi.h Source File

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stm32f10x_spi.h

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f10x_spi.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    11-March-2011
00007   * @brief   This file contains all the functions prototypes for the SPI firmware
00008   *          library.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00013   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00014   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00015   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00016   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00017   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00018   *
00019   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00020   ******************************************************************************
00021   */
00022
00023 /* Define to prevent recursive inclusion -------------------------------------*/
00024 #ifndef __STM32F10x_SPI_H
00025 #define __STM32F10x_SPI_H
00026
00027 #ifdef __cplusplus
00028  extern "C" {
00029 #endif
00030
00031 /* Includes ------------------------------------------------------------------*/
00032 #include "stm32f10x.h"
00033
00034 /** @addtogroup STM32F10x_StdPeriph_Driver
00035   * @{
00036   */
00037
00038 /** @addtogroup SPI
00039   * @{
00040   */
00041
00042 /** @defgroup SPI_Exported_Types
00043   * @{
00044   */
00045
00046 /**
00047   * @brief  SPI Init structure definition
00048   */
00049
00050 typedef struct
00051 {
00052   uint16_t SPI_Direction;           /*!< Specifies the SPI unidirectional or bidirectional data mode.
00053                                          This parameter can be a value of @ref SPI_data_direction */
00054
00055   uint16_t SPI_Mode;                /*!< Specifies the SPI operating mode.
00056                                          This parameter can be a value of @ref SPI_mode */
00057
00058   uint16_t SPI_DataSize;            /*!< Specifies the SPI data size.
00059                                          This parameter can be a value of @ref SPI_data_size */
00060
00061   uint16_t SPI_CPOL;                /*!< Specifies the serial clock steady state.
00062                                          This parameter can be a value of @ref SPI_Clock_Polarity */
00063
00064   uint16_t SPI_CPHA;                /*!< Specifies the clock active edge for the bit capture.
00065                                          This parameter can be a value of @ref SPI_Clock_Phase */
00066
00067   uint16_t SPI_NSS;                 /*!< Specifies whether the NSS signal is managed by
00068                                          hardware (NSS pin) or by software using the SSI bit.
00069                                          This parameter can be a value of @ref SPI_Slave_Select_management */
00070
00071   uint16_t SPI_BaudRatePrescaler;   /*!< Specifies the Baud Rate prescaler value which will be
00072                                          used to configure the transmit and receive SCK clock.
00073                                          This parameter can be a value of @ref SPI_BaudRate_Prescaler.
00074                                          @note The communication clock is derived from the master
00075                                                clock. The slave clock does not need to be set. */
00076
00077   uint16_t SPI_FirstBit;            /*!< Specifies whether data transfers start from MSB or LSB bit.
00078                                          This parameter can be a value of @ref SPI_MSB_LSB_transmission */
00079
00080   uint16_t SPI_CRCPolynomial;       /*!< Specifies the polynomial used for the CRC calculation. */
00081 }SPI_InitTypeDef;
00082
00083 /**
00084   * @brief  I2S Init structure definition
00085   */
00086
00087 typedef struct
00088 {
00089
00090   uint16_t I2S_Mode;         /*!< Specifies the I2S operating mode.
00091                                   This parameter can be a value of @ref I2S_Mode */
00092
00093   uint16_t I2S_Standard;     /*!< Specifies the standard used for the I2S communication.
00094                                   This parameter can be a value of @ref I2S_Standard */
00095
00096   uint16_t I2S_DataFormat;   /*!< Specifies the data format for the I2S communication.
00097                                   This parameter can be a value of @ref I2S_Data_Format */
00098
00099   uint16_t I2S_MCLKOutput;   /*!< Specifies whether the I2S MCLK output is enabled or not.
00100                                   This parameter can be a value of @ref I2S_MCLK_Output */
00101
00102   uint32_t I2S_AudioFreq;    /*!< Specifies the frequency selected for the I2S communication.
00103                                   This parameter can be a value of @ref I2S_Audio_Frequency */
00104
00105   uint16_t I2S_CPOL;         /*!< Specifies the idle state of the I2S clock.
00106                                   This parameter can be a value of @ref I2S_Clock_Polarity */
00107 }I2S_InitTypeDef;
00108
00109 /**
00110   * @}
00111   */
00112
00113 /** @defgroup SPI_Exported_Constants
00114   * @{
00115   */
00116
00117 #define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \
00118                                    ((PERIPH) == SPI2) || \
00119                                    ((PERIPH) == SPI3))
00120
00121 #define IS_SPI_23_PERIPH(PERIPH) (((PERIPH) == SPI2) || \
00122                                   ((PERIPH) == SPI3))
00123
00124 /** @defgroup SPI_data_direction
00125   * @{
00126   */
00127
00128 #define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)
00129 #define SPI_Direction_2Lines_RxOnly     ((uint16_t)0x0400)
00130 #define SPI_Direction_1Line_Rx          ((uint16_t)0x8000)
00131 #define SPI_Direction_1Line_Tx          ((uint16_t)0xC000)
00132 #define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \
00133                                      ((MODE) == SPI_Direction_2Lines_RxOnly) || \
00134                                      ((MODE) == SPI_Direction_1Line_Rx) || \
00135                                      ((MODE) == SPI_Direction_1Line_Tx))
00136 /**
00137   * @}
00138   */
00139
00140 /** @defgroup SPI_mode
00141   * @{
00142   */
00143
00144 #define SPI_Mode_Master                 ((uint16_t)0x0104)
00145 #define SPI_Mode_Slave                  ((uint16_t)0x0000)
00146 #define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \
00147                            ((MODE) == SPI_Mode_Slave))
00148 /**
00149   * @}
00150   */
00151
00152 /** @defgroup SPI_data_size
00153   * @{
00154   */
00155
00156 #define SPI_DataSize_16b                ((uint16_t)0x0800)
00157 #define SPI_DataSize_8b                 ((uint16_t)0x0000)
00158 #define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || \
00159                                    ((DATASIZE) == SPI_DataSize_8b))
00160 /**
00161   * @}
00162   */
00163
00164 /** @defgroup SPI_Clock_Polarity
00165   * @{
00166   */
00167
00168 #define SPI_CPOL_Low                    ((uint16_t)0x0000)
00169 #define SPI_CPOL_High                   ((uint16_t)0x0002)
00170 #define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \
00171                            ((CPOL) == SPI_CPOL_High))
00172 /**
00173   * @}
00174   */
00175
00176 /** @defgroup SPI_Clock_Phase
00177   * @{
00178   */
00179
00180 #define SPI_CPHA_1Edge                  ((uint16_t)0x0000)
00181 #define SPI_CPHA_2Edge                  ((uint16_t)0x0001)
00182 #define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \
00183                            ((CPHA) == SPI_CPHA_2Edge))
00184 /**
00185   * @}
00186   */
00187
00188 /** @defgroup SPI_Slave_Select_management
00189   * @{
00190   */
00191
00192 #define SPI_NSS_Soft                    ((uint16_t)0x0200)
00193 #define SPI_NSS_Hard                    ((uint16_t)0x0000)
00194 #define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \
00195                          ((NSS) == SPI_NSS_Hard))
00196 /**
00197   * @}
00198   */
00199
00200 /** @defgroup SPI_BaudRate_Prescaler
00201   * @{
00202   */
00203
00204 #define SPI_BaudRatePrescaler_2         ((uint16_t)0x0000)
00205 #define SPI_BaudRatePrescaler_4         ((uint16_t)0x0008)
00206 #define SPI_BaudRatePrescaler_8         ((uint16_t)0x0010)
00207 #define SPI_BaudRatePrescaler_16        ((uint16_t)0x0018)
00208 #define SPI_BaudRatePrescaler_32        ((uint16_t)0x0020)
00209 #define SPI_BaudRatePrescaler_64        ((uint16_t)0x0028)
00210 #define SPI_BaudRatePrescaler_128       ((uint16_t)0x0030)
00211 #define SPI_BaudRatePrescaler_256       ((uint16_t)0x0038)
00212 #define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \
00213                                               ((PRESCALER) == SPI_BaudRatePrescaler_4) || \
00214                                               ((PRESCALER) == SPI_BaudRatePrescaler_8) || \
00215                                               ((PRESCALER) == SPI_BaudRatePrescaler_16) || \
00216                                               ((PRESCALER) == SPI_BaudRatePrescaler_32) || \
00217                                               ((PRESCALER) == SPI_BaudRatePrescaler_64) || \
00218                                               ((PRESCALER) == SPI_BaudRatePrescaler_128) || \
00219                                               ((PRESCALER) == SPI_BaudRatePrescaler_256))
00220 /**
00221   * @}
00222   */
00223
00224 /** @defgroup SPI_MSB_LSB_transmission
00225   * @{
00226   */
00227
00228 #define SPI_FirstBit_MSB                ((uint16_t)0x0000)
00229 #define SPI_FirstBit_LSB                ((uint16_t)0x0080)
00230 #define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \
00231                                ((BIT) == SPI_FirstBit_LSB))
00232 /**
00233   * @}
00234   */
00235
00236 /** @defgroup I2S_Mode
00237   * @{
00238   */
00239
00240 #define I2S_Mode_SlaveTx                ((uint16_t)0x0000)
00241 #define I2S_Mode_SlaveRx                ((uint16_t)0x0100)
00242 #define I2S_Mode_MasterTx               ((uint16_t)0x0200)
00243 #define I2S_Mode_MasterRx               ((uint16_t)0x0300)
00244 #define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \
00245                            ((MODE) == I2S_Mode_SlaveRx) || \
00246                            ((MODE) == I2S_Mode_MasterTx) || \
00247                            ((MODE) == I2S_Mode_MasterRx) )
00248 /**
00249   * @}
00250   */
00251
00252 /** @defgroup I2S_Standard
00253   * @{
00254   */
00255
00256 #define I2S_Standard_Phillips           ((uint16_t)0x0000)
00257 #define I2S_Standard_MSB                ((uint16_t)0x0010)
00258 #define I2S_Standard_LSB                ((uint16_t)0x0020)
00259 #define I2S_Standard_PCMShort           ((uint16_t)0x0030)
00260 #define I2S_Standard_PCMLong            ((uint16_t)0x00B0)
00261 #define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \
00262                                    ((STANDARD) == I2S_Standard_MSB) || \
00263                                    ((STANDARD) == I2S_Standard_LSB) || \
00264                                    ((STANDARD) == I2S_Standard_PCMShort) || \
00265                                    ((STANDARD) == I2S_Standard_PCMLong))
00266 /**
00267   * @}
00268   */
00269
00270 /** @defgroup I2S_Data_Format
00271   * @{
00272   */
00273
00274 #define I2S_DataFormat_16b              ((uint16_t)0x0000)
00275 #define I2S_DataFormat_16bextended      ((uint16_t)0x0001)
00276 #define I2S_DataFormat_24b              ((uint16_t)0x0003)
00277 #define I2S_DataFormat_32b              ((uint16_t)0x0005)
00278 #define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \
00279                                     ((FORMAT) == I2S_DataFormat_16bextended) || \
00280                                     ((FORMAT) == I2S_DataFormat_24b) || \
00281                                     ((FORMAT) == I2S_DataFormat_32b))
00282 /**
00283   * @}
00284   */
00285
00286 /** @defgroup I2S_MCLK_Output
00287   * @{
00288   */
00289
00290 #define I2S_MCLKOutput_Enable           ((uint16_t)0x0200)
00291 #define I2S_MCLKOutput_Disable          ((uint16_t)0x0000)
00292 #define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \
00293                                     ((OUTPUT) == I2S_MCLKOutput_Disable))
00294 /**
00295   * @}
00296   */
00297
00298 /** @defgroup I2S_Audio_Frequency
00299   * @{
00300   */
00301
00302 #define I2S_AudioFreq_192k               ((uint32_t)192000)
00303 #define I2S_AudioFreq_96k                ((uint32_t)96000)
00304 #define I2S_AudioFreq_48k                ((uint32_t)48000)
00305 #define I2S_AudioFreq_44k                ((uint32_t)44100)
00306 #define I2S_AudioFreq_32k                ((uint32_t)32000)
00307 #define I2S_AudioFreq_22k                ((uint32_t)22050)
00308 #define I2S_AudioFreq_16k                ((uint32_t)16000)
00309 #define I2S_AudioFreq_11k                ((uint32_t)11025)
00310 #define I2S_AudioFreq_8k                 ((uint32_t)8000)
00311 #define I2S_AudioFreq_Default            ((uint32_t)2)
00312
00313 #define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \
00314                                   ((FREQ) <= I2S_AudioFreq_192k)) || \
00315                                  ((FREQ) == I2S_AudioFreq_Default))
00316 /**
00317   * @}
00318   */
00319
00320 /** @defgroup I2S_Clock_Polarity
00321   * @{
00322   */
00323
00324 #define I2S_CPOL_Low                    ((uint16_t)0x0000)
00325 #define I2S_CPOL_High                   ((uint16_t)0x0008)
00326 #define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \
00327                            ((CPOL) == I2S_CPOL_High))
00328 /**
00329   * @}
00330   */
00331
00332 /** @defgroup SPI_I2S_DMA_transfer_requests
00333   * @{
00334   */
00335
00336 #define SPI_I2S_DMAReq_Tx               ((uint16_t)0x0002)
00337 #define SPI_I2S_DMAReq_Rx               ((uint16_t)0x0001)
00338 #define IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00))
00339 /**
00340   * @}
00341   */
00342
00343 /** @defgroup SPI_NSS_internal_software_management
00344   * @{
00345   */
00346
00347 #define SPI_NSSInternalSoft_Set         ((uint16_t)0x0100)
00348 #define SPI_NSSInternalSoft_Reset       ((uint16_t)0xFEFF)
00349 #define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \
00350                                        ((INTERNAL) == SPI_NSSInternalSoft_Reset))
00351 /**
00352   * @}
00353   */
00354
00355 /** @defgroup SPI_CRC_Transmit_Receive
00356   * @{
00357   */
00358
00359 #define SPI_CRC_Tx                      ((uint8_t)0x00)
00360 #define SPI_CRC_Rx                      ((uint8_t)0x01)
00361 #define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx))
00362 /**
00363   * @}
00364   */
00365
00366 /** @defgroup SPI_direction_transmit_receive
00367   * @{
00368   */
00369
00370 #define SPI_Direction_Rx                ((uint16_t)0xBFFF)
00371 #define SPI_Direction_Tx                ((uint16_t)0x4000)
00372 #define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \
00373                                      ((DIRECTION) == SPI_Direction_Tx))
00374 /**
00375   * @}
00376   */
00377
00378 /** @defgroup SPI_I2S_interrupts_definition
00379   * @{
00380   */
00381
00382 #define SPI_I2S_IT_TXE                  ((uint8_t)0x71)
00383 #define SPI_I2S_IT_RXNE                 ((uint8_t)0x60)
00384 #define SPI_I2S_IT_ERR                  ((uint8_t)0x50)
00385 #define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \
00386                                  ((IT) == SPI_I2S_IT_RXNE) || \
00387                                  ((IT) == SPI_I2S_IT_ERR))
00388 #define SPI_I2S_IT_OVR                  ((uint8_t)0x56)
00389 #define SPI_IT_MODF                     ((uint8_t)0x55)
00390 #define SPI_IT_CRCERR                   ((uint8_t)0x54)
00391 #define I2S_IT_UDR                      ((uint8_t)0x53)
00392 #define IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR))
00393 #define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \
00394                                ((IT) == I2S_IT_UDR) || ((IT) == SPI_IT_CRCERR) || \
00395                                ((IT) == SPI_IT_MODF) || ((IT) == SPI_I2S_IT_OVR))
00396 /**
00397   * @}
00398   */
00399
00400 /** @defgroup SPI_I2S_flags_definition
00401   * @{
00402   */
00403
00404 #define SPI_I2S_FLAG_RXNE               ((uint16_t)0x0001)
00405 #define SPI_I2S_FLAG_TXE                ((uint16_t)0x0002)
00406 #define I2S_FLAG_CHSIDE                 ((uint16_t)0x0004)
00407 #define I2S_FLAG_UDR                    ((uint16_t)0x0008)
00408 #define SPI_FLAG_CRCERR                 ((uint16_t)0x0010)
00409 #define SPI_FLAG_MODF                   ((uint16_t)0x0020)
00410 #define SPI_I2S_FLAG_OVR                ((uint16_t)0x0040)
00411 #define SPI_I2S_FLAG_BSY                ((uint16_t)0x0080)
00412 #define IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR))
00413 #define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \
00414                                    ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \
00415                                    ((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) || \
00416                                    ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE))
00417 /**
00418   * @}
00419   */
00420
00421 /** @defgroup SPI_CRC_polynomial
00422   * @{
00423   */
00424
00425 #define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1)
00426 /**
00427   * @}
00428   */
00429
00430 /**
00431   * @}
00432   */
00433
00434 /** @defgroup SPI_Exported_Macros
00435   * @{
00436   */
00437
00438 /**
00439   * @}
00440   */
00441
00442 /** @defgroup SPI_Exported_Functions
00443   * @{
00444   */
00445
00446 void SPI_I2S_DeInit(SPI_TypeDef* SPIx);
00447 void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct);
00448 void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct);
00449 void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct);
00450 void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct);
00451 void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
00452 void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
00453 void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
00454 void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);
00455 void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data);
00456 uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx);
00457 void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft);
00458 void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
00459 void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize);
00460 void SPI_TransmitCRC(SPI_TypeDef* SPIx);
00461 void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState);
00462 uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC);
00463 uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx);
00464 void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction);
00465 FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
00466 void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
00467 ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
00468 void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
00469
00470 #ifdef __cplusplus
00471 }
00472 #endif
00473
00474 #endif /*__STM32F10x_SPI_H */
00475 /**
00476   * @}
00477   */
00478
00479 /**
00480   * @}
00481   */
00482
00483 /**
00484   * @}
00485   */
00486
00487 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/main.c

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00001 /**
00002   ******************************************************************************
00003   * @file    ADC/ADC1_DMA/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x.h"
00024
00025 /** @addtogroup STM32F10x_StdPeriph_Examples
00026   * @{
00027   */
00028
00029 /** @addtogroup ADC_ADC1_DMA
00030   * @{
00031   */
00032
00033
00034 /* Private typedef -----------------------------------------------------------*/
00035 /* Private define ------------------------------------------------------------*/
00036 #define ADC1_DR_Address    ((uint32_t)0x4001244C)
00037
00038 /* Private macro -------------------------------------------------------------*/
00039 /* Private variables ---------------------------------------------------------*/
00040 ADC_InitTypeDef ADC_InitStructure;
00041 DMA_InitTypeDef DMA_InitStructure;
00042 __IO uint16_t ADCConvertedValue;
00043
00044 /* Private function prototypes -----------------------------------------------*/
00045 void RCC_Configuration(void);
00046 void GPIO_Configuration(void);
00047
00048 /* Private functions ---------------------------------------------------------*/
00049
00050 /**
00051   * @brief   Main program
00052   * @param  None
00053   * @retval None
00054   */
00055 int main(void)
00056 {
00057   /*!< At this stage the microcontroller clock setting is already configured,
00058        this is done through SystemInit() function which is called from startup
00059        file (startup_stm32f10x_xx.s) before to branch to application main.
00060        To reconfigure the default setting of SystemInit() function, refer to
00061        system_stm32f10x.c file
00062      */
00063
00064   /* System clocks configuration ---------------------------------------------*/
00065   RCC_Configuration();
00066
00067   /* GPIO configuration ------------------------------------------------------*/
00068   GPIO_Configuration();
00069
00070   /* DMA1 channel1 configuration ----------------------------------------------*/
00071   DMA_DeInit(DMA1_Channel1);
00072   DMA_InitStructure.DMA_PeripheralBaseAddr = ADC1_DR_Address;
00073   DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)&ADCConvertedValue;
00074   DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
00075   DMA_InitStructure.DMA_BufferSize = 1;
00076   DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
00077   DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Disable;
00078   DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord;
00079   DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
00080   DMA_InitStructure.DMA_Mode = DMA_Mode_Circular;
00081   DMA_InitStructure.DMA_Priority = DMA_Priority_High;
00082   DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
00083   DMA_Init(DMA1_Channel1, &DMA_InitStructure);
00084
00085   /* Enable DMA1 channel1 */
00086   DMA_Cmd(DMA1_Channel1, ENABLE);
00087
00088   /* ADC1 configuration ------------------------------------------------------*/
00089   ADC_InitStructure.ADC_Mode = ADC_Mode_Independent;
00090   ADC_InitStructure.ADC_ScanConvMode = ENABLE;
00091   ADC_InitStructure.ADC_ContinuousConvMode = ENABLE;
00092   ADC_InitStructure.ADC_ExternalTrigConv = ADC_ExternalTrigConv_None;
00093   ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right;
00094   ADC_InitStructure.ADC_NbrOfChannel = 1;
00095   ADC_Init(ADC1, &ADC_InitStructure);
00096
00097   /* ADC1 regular channel14 configuration */
00098   ADC_RegularChannelConfig(ADC1, ADC_Channel_14, 1, ADC_SampleTime_55Cycles5);
00099
00100   /* Enable ADC1 DMA */
00101   ADC_DMACmd(ADC1, ENABLE);
00102
00103   /* Enable ADC1 */
00104   ADC_Cmd(ADC1, ENABLE);
00105
00106   /* Enable ADC1 reset calibration register */
00107   ADC_ResetCalibration(ADC1);
00108   /* Check the end of ADC1 reset calibration register */
00109   while(ADC_GetResetCalibrationStatus(ADC1));
00110
00111   /* Start ADC1 calibration */
00112   ADC_StartCalibration(ADC1);
00113   /* Check the end of ADC1 calibration */
00114   while(ADC_GetCalibrationStatus(ADC1));
00115
00116   /* Start ADC1 Software Conversion */
00117   ADC_SoftwareStartConvCmd(ADC1, ENABLE);
00118
00119   while (1)
00120   {
00121   }
00122 }
00123
00124 /**
00125   * @brief  Configures the different system clocks.
00126   * @param  None
00127   * @retval None
00128   */
00129 void RCC_Configuration(void)
00130 {
00131 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00132   /* ADCCLK = PCLK2/2 */
00133   RCC_ADCCLKConfig(RCC_PCLK2_Div2);
00134 #else
00135   /* ADCCLK = PCLK2/4 */
00136   RCC_ADCCLKConfig(RCC_PCLK2_Div4);
00137 #endif
00138   /* Enable peripheral clocks ------------------------------------------------*/
00139   /* Enable DMA1 clock */
00140   RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE);
00141
00142   /* Enable ADC1 and GPIOC clock */
00143   RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1 | RCC_APB2Periph_GPIOC, ENABLE);
00144 }
00145
00146 /**
00147   * @brief  Configures the different GPIO ports.
00148   * @param  None
00149   * @retval None
00150   */
00151 void GPIO_Configuration(void)
00152 {
00153   GPIO_InitTypeDef GPIO_InitStructure;
00154
00155   /* Configure PC.04 (ADC Channel14) as analog input -------------------------*/
00156   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4;
00157   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AIN;
00158   GPIO_Init(GPIOC, &GPIO_InitStructure);
00159 }
00160
00161 #ifdef  USE_FULL_ASSERT
00162
00163 /**
00164   * @brief  Reports the name of the source file and the source line number
00165   *         where the assert_param error has occurred.
00166   * @param  file: pointer to the source file name
00167   * @param  line: assert_param error line source number
00168   * @retval None
00169   */
00170 void assert_failed(uint8_t* file, uint32_t line)
00171 {
00172   /* User can add his own implementation to report the file name and line number,
00173      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00174
00175   /* Infinite loop */
00176   while (1)
00177   {
00178   }
00179 }
00180
00181 #endif
00182
00183 /**
00184   * @}
00185   */
00186
00187 /**
00188   * @}
00189   */
00190
00191 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: readme.txt File Reference

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readme.txt File Reference

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/stm32f10x_conf.h

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00001 /**
00002   ******************************************************************************
00003   * @file    ADC/ADC1_DMA/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052 /* Exported types ------------------------------------------------------------*/
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Uncomment the line below to expanse the "assert_param" macro in the
00055    Standard Peripheral Library drivers code */
00056 /* #define USE_FULL_ASSERT    1 */
00057
00058 /* Exported macro ------------------------------------------------------------*/
00059 #ifdef  USE_FULL_ASSERT
00060
00061 /**
00062   * @brief  The assert_param macro is used for function's parameters check.
00063   * @param  expr: If expr is false, it calls assert_failed function which reports
00064   *         the name of the source file and the source line number of the call
00065   *         that failed. If expr is true, it returns no value.
00066   * @retval None
00067   */
00068   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00069 /* Exported functions ------------------------------------------------------- */
00070   void assert_failed(uint8_t* file, uint32_t line);
00071 #else
00072   #define assert_param(expr) ((void)0)
00073 #endif /* USE_FULL_ASSERT */
00074
00075 #endif /* __STM32F10x_CONF_H */
00076
00077 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/stm32f10x_it.c

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00001 /**
00002   ******************************************************************************
00003   * @file    ADC/ADC1_DMA/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and peripherals
00009   *          interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026
00027 /** @addtogroup STM32F10x_StdPeriph_Examples
00028   * @{
00029   */
00030
00031 /** @addtogroup ADC_ADC1_DMA
00032   * @{
00033   */
00034
00035 /* Private typedef -----------------------------------------------------------*/
00036 /* Private define ------------------------------------------------------------*/
00037 /* Private macro -------------------------------------------------------------*/
00038 /* Private variables ---------------------------------------------------------*/
00039 /* Private function prototypes -----------------------------------------------*/
00040 /* Private functions ---------------------------------------------------------*/
00041
00042 /******************************************************************************/
00043 /*            Cortex-M3 Processor Exceptions Handlers                         */
00044 /******************************************************************************/
00045
00046 /**
00047   * @brief  This function handles NMI exception.
00048   * @param  None
00049   * @retval None
00050   */
00051 void NMI_Handler(void)
00052 {
00053 }
00054
00055 /**
00056   * @brief  This function handles Hard Fault exception.
00057   * @param  None
00058   * @retval None
00059   */
00060 void HardFault_Handler(void)
00061 {
00062   /* Go to infinite loop when Hard Fault exception occurs */
00063   while (1)
00064   {
00065   }
00066 }
00067
00068 /**
00069   * @brief  This function handles Memory Manage exception.
00070   * @param  None
00071   * @retval None
00072   */
00073 void MemManage_Handler(void)
00074 {
00075   /* Go to infinite loop when Memory Manage exception occurs */
00076   while (1)
00077   {
00078   }
00079 }
00080
00081 /**
00082   * @brief  This function handles Bus Fault exception.
00083   * @param  None
00084   * @retval None
00085   */
00086 void BusFault_Handler(void)
00087 {
00088   /* Go to infinite loop when Bus Fault exception occurs */
00089   while (1)
00090   {
00091   }
00092 }
00093
00094 /**
00095   * @brief  This function handles Usage Fault exception.
00096   * @param  None
00097   * @retval None
00098   */
00099 void UsageFault_Handler(void)
00100 {
00101   /* Go to infinite loop when Usage Fault exception occurs */
00102   while (1)
00103   {
00104   }
00105 }
00106
00107 /**
00108   * @brief  This function handles SVCall exception.
00109   * @param  None
00110   * @retval None
00111   */
00112 void SVC_Handler(void)
00113 {
00114 }
00115
00116 /**
00117   * @brief  This function handles Debug Monitor exception.
00118   * @param  None
00119   * @retval None
00120   */
00121 void DebugMon_Handler(void)
00122 {
00123 }
00124
00125 /**
00126   * @brief  This function handles PendSV_Handler exception.
00127   * @param  None
00128   * @retval None
00129   */
00130 void PendSV_Handler(void)
00131 {
00132 }
00133
00134 /**
00135   * @brief  This function handles SysTick Handler.
00136   * @param  None
00137   * @retval None
00138   */
00139 void SysTick_Handler(void)
00140 {
00141 }
00142
00143 /******************************************************************************/
00144 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00145 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00146 /*  available peripheral interrupt handler's name please refer to the startup */
00147 /*  file (startup_stm32f10x_xx.s).                                            */
00148 /******************************************************************************/
00149
00150 /**
00151   * @brief  This function handles PPP interrupt request.
00152   * @param  None
00153   * @retval None
00154   */
00155 /*void PPP_IRQHandler(void)
00156 {
00157 }*/
00158
00159 /**
00160   * @}
00161   */
00162
00163 /**
00164   * @}
00165   */
00166
00167 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/stm32f10x_it.h

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00001 /**
00002   ******************************************************************************
00003   * @file    ADC/ADC1_DMA/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043
00044 #endif /* __STM32F10x_IT_H */
00045
00046 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/main.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    ADC/AnalogWatchdog/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x.h"
00024 #include "stm32_eval.h"
00025
00026 /** @addtogroup STM32F10x_StdPeriph_Examples
00027   * @{
00028   */
00029
00030 /** @addtogroup ADC_AnalogWatchdog
00031   * @{
00032   */
00033
00034 /* Private typedef -----------------------------------------------------------*/
00035 /* Private define ------------------------------------------------------------*/
00036 /* Private macro -------------------------------------------------------------*/
00037 /* Private variables ---------------------------------------------------------*/
00038 ADC_InitTypeDef  ADC_InitStructure;
00039
00040 /* Private function prototypes -----------------------------------------------*/
00041 void RCC_Configuration(void);
00042 void GPIO_Configuration(void);
00043 void NVIC_Configuration(void);
00044
00045 /* Private functions ---------------------------------------------------------*/
00046
00047 /**
00048   * @brief   Main program
00049   * @param  None
00050   * @retval None
00051   */
00052 int main(void)
00053 {
00054   /*!< At this stage the microcontroller clock setting is already configured,
00055        this is done through SystemInit() function which is called from startup
00056        file (startup_stm32f10x_xx.s) before to branch to application main.
00057        To reconfigure the default setting of SystemInit() function, refer to
00058        system_stm32f10x.c file
00059      */
00060
00061   /* System clocks configuration ---------------------------------------------*/
00062   RCC_Configuration();
00063
00064   /* NVIC configuration ------------------------------------------------------*/
00065   NVIC_Configuration();
00066
00067   /* GPIO configuration ------------------------------------------------------*/
00068   GPIO_Configuration();
00069
00070   /* Configure LED GPIO Pin ------------------------------------------------- */
00071   STM_EVAL_LEDInit(LED1);
00072
00073   /* ADC1 Configuration ------------------------------------------------------*/
00074   ADC_InitStructure.ADC_Mode = ADC_Mode_Independent;
00075   ADC_InitStructure.ADC_ScanConvMode = DISABLE;
00076   ADC_InitStructure.ADC_ContinuousConvMode = ENABLE;
00077   ADC_InitStructure.ADC_ExternalTrigConv = ADC_ExternalTrigConv_None;
00078   ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right;
00079   ADC_InitStructure.ADC_NbrOfChannel = 1;
00080   ADC_Init(ADC1, &ADC_InitStructure);
00081
00082   /* ADC1 regular channel14 configuration */
00083   ADC_RegularChannelConfig(ADC1, ADC_Channel_14, 1, ADC_SampleTime_13Cycles5);
00084
00085   /* Configure high and low analog watchdog thresholds */
00086   ADC_AnalogWatchdogThresholdsConfig(ADC1, 0x0B00, 0x0300);
00087   /* Configure channel14 as the single analog watchdog guarded channel */
00088   ADC_AnalogWatchdogSingleChannelConfig(ADC1, ADC_Channel_14);
00089   /* Enable analog watchdog on one regular channel */
00090   ADC_AnalogWatchdogCmd(ADC1, ADC_AnalogWatchdog_SingleRegEnable);
00091
00092   /* Enable AWD interrupt */
00093   ADC_ITConfig(ADC1, ADC_IT_AWD, ENABLE);
00094
00095   /* Enable ADC1 */
00096   ADC_Cmd(ADC1, ENABLE);
00097
00098   /* Enable ADC1 reset calibration register */
00099   ADC_ResetCalibration(ADC1);
00100   /* Check the end of ADC1 reset calibration register */
00101   while(ADC_GetResetCalibrationStatus(ADC1));
00102
00103   /* Start ADC1 calibration */
00104   ADC_StartCalibration(ADC1);
00105   /* Check the end of ADC1 calibration */
00106   while(ADC_GetCalibrationStatus(ADC1));
00107
00108   /* Start ADC1 Software Conversion */
00109   ADC_SoftwareStartConvCmd(ADC1, ENABLE);
00110
00111   while (1)
00112   {
00113   }
00114 }
00115
00116 /**
00117   * @brief  Configures the different system clocks.
00118   * @param  None
00119   * @retval None
00120   */
00121 void RCC_Configuration(void)
00122 {
00123 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00124   /* ADCCLK = PCLK2/2 */
00125   RCC_ADCCLKConfig(RCC_PCLK2_Div2);
00126 #else
00127   /* ADCCLK = PCLK2/4 */
00128   RCC_ADCCLKConfig(RCC_PCLK2_Div4);
00129 #endif
00130 /* Enable peripheral clocks --------------------------------------------------*/
00131   /* Enable ADC1 and GPIO_LED clock */
00132   RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1, ENABLE);
00133 }
00134
00135 /**
00136   * @brief  Configures the different GPIO ports.
00137   * @param  None
00138   * @retval None
00139   */
00140 void GPIO_Configuration(void)
00141 {
00142   GPIO_InitTypeDef GPIO_InitStructure;
00143
00144   /* Configure PC.04 (ADC Channel14) as analog input -------------------------*/
00145   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4;
00146   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AIN;
00147   GPIO_Init(GPIOC, &GPIO_InitStructure);
00148 }
00149
00150 /**
00151   * @brief  Configures NVIC and Vector Table base location.
00152   * @param  None
00153   * @retval None
00154   */
00155 void NVIC_Configuration(void)
00156 {
00157   NVIC_InitTypeDef NVIC_InitStructure;
00158
00159   /* Configure and enable ADC interrupt */
00160 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00161   NVIC_InitStructure.NVIC_IRQChannel = ADC1_IRQn;
00162 #else
00163   NVIC_InitStructure.NVIC_IRQChannel = ADC1_2_IRQn;
00164 #endif
00165   NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
00166   NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
00167   NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
00168   NVIC_Init(&NVIC_InitStructure);
00169 }
00170
00171 #ifdef  USE_FULL_ASSERT
00172
00173 /**
00174   * @brief  Reports the name of the source file and the source line number
00175   *         where the assert_param error has occurred.
00176   * @param  file: pointer to the source file name
00177   * @param  line: assert_param error line source number
00178   * @retval None
00179   */
00180 void assert_failed(uint8_t* file, uint32_t line)
00181 {
00182   /* User can add his own implementation to report the file name and line number,
00183      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00184
00185   /* Infinite loop */
00186   while (1)
00187   {
00188   }
00189 }
00190
00191 #endif
00192
00193 /**
00194   * @}
00195   */
00196
00197 /**
00198   * @}
00199   */
00200
00201 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/stm32f10x_conf.h

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00001 /**
00002   ******************************************************************************
00003   * @file    ADC/AnalogWatchdog/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052 /* Exported types ------------------------------------------------------------*/
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Uncomment the line below to expanse the "assert_param" macro in the
00055    Standard Peripheral Library drivers code */
00056 /* #define USE_FULL_ASSERT    1 */
00057
00058 /* Exported macro ------------------------------------------------------------*/
00059 #ifdef  USE_FULL_ASSERT
00060
00061 /**
00062   * @brief  The assert_param macro is used for function's parameters check.
00063   * @param  expr: If expr is false, it calls assert_failed function which reports
00064   *         the name of the source file and the source line number of the call
00065   *         that failed. If expr is true, it returns no value.
00066   * @retval None
00067   */
00068   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00069 /* Exported functions ------------------------------------------------------- */
00070   void assert_failed(uint8_t* file, uint32_t line);
00071 #else
00072   #define assert_param(expr) ((void)0)
00073 #endif /* USE_FULL_ASSERT */
00074
00075 #endif /* __STM32F10x_CONF_H */
00076
00077 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/stm32f10x_it.c

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00001 /**
00002   ******************************************************************************
00003   * @file    ADC/AnalogWatchdog/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and peripherals
00009   *          interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026 #include "stm32_eval.h"
00027
00028 /** @addtogroup STM32F10x_StdPeriph_Examples
00029   * @{
00030   */
00031
00032 /** @addtogroup ADC_AnalogWatchdog
00033   * @{
00034   */
00035
00036 /* Private typedef -----------------------------------------------------------*/
00037 /* Private define ------------------------------------------------------------*/
00038 /* Private macro -------------------------------------------------------------*/
00039 /* Private variables ---------------------------------------------------------*/
00040 /* Private function prototypes -----------------------------------------------*/
00041 /* Private functions ---------------------------------------------------------*/
00042
00043 /******************************************************************************/
00044 /*            Cortex-M3 Processor Exceptions Handlers                         */
00045 /******************************************************************************/
00046
00047 /**
00048   * @brief  This function handles NMI exception.
00049   * @param  None
00050   * @retval None
00051   */
00052 void NMI_Handler(void)
00053 {
00054 }
00055
00056 /**
00057   * @brief  This function handles Hard Fault exception.
00058   * @param  None
00059   * @retval None
00060   */
00061 void HardFault_Handler(void)
00062 {
00063   /* Go to infinite loop when Hard Fault exception occurs */
00064   while (1)
00065   {
00066   }
00067 }
00068
00069 /**
00070   * @brief  This function handles Memory Manage exception.
00071   * @param  None
00072   * @retval None
00073   */
00074 void MemManage_Handler(void)
00075 {
00076   /* Go to infinite loop when Memory Manage exception occurs */
00077   while (1)
00078   {
00079   }
00080 }
00081
00082 /**
00083   * @brief  This function handles Bus Fault exception.
00084   * @param  None
00085   * @retval None
00086   */
00087 void BusFault_Handler(void)
00088 {
00089   /* Go to infinite loop when Bus Fault exception occurs */
00090   while (1)
00091   {
00092   }
00093 }
00094
00095 /**
00096   * @brief  This function handles Usage Fault exception.
00097   * @param  None
00098   * @retval None
00099   */
00100 void UsageFault_Handler(void)
00101 {
00102   /* Go to infinite loop when Usage Fault exception occurs */
00103   while (1)
00104   {
00105   }
00106 }
00107
00108 /**
00109   * @brief  This function handles SVCall exception.
00110   * @param  None
00111   * @retval None
00112   */
00113 void SVC_Handler(void)
00114 {
00115 }
00116
00117 /**
00118   * @brief  This function handles Debug Monitor exception.
00119   * @param  None
00120   * @retval None
00121   */
00122 void DebugMon_Handler(void)
00123 {
00124 }
00125
00126 /**
00127   * @brief  This function handles PendSV_Handler exception.
00128   * @param  None
00129   * @retval None
00130   */
00131 void PendSV_Handler(void)
00132 {
00133 }
00134
00135 /**
00136   * @brief  This function handles SysTick Handler.
00137   * @param  None
00138   * @retval None
00139   */
00140 void SysTick_Handler(void)
00141 {
00142 }
00143
00144 /******************************************************************************/
00145 /*            STM32F10x Peripherals Interrupt Handlers                        */
00146 /******************************************************************************/
00147
00148 /**
00149   * @brief  This function handles ADC1 and ADC2 global interrupts requests.
00150   * @param  None
00151   * @retval None
00152   */
00153 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00154 void ADC1_IRQHandler(void)
00155 #else
00156 void ADC1_2_IRQHandler(void)
00157 #endif
00158 {
00159   /* Toggle LED1 */
00160   STM_EVAL_LEDOn(LED1);
00161   STM_EVAL_LEDOff(LED1);
00162
00163   /* Clear ADC1 AWD pending interrupt bit */
00164   ADC_ClearITPendingBit(ADC1, ADC_IT_AWD);
00165 }
00166
00167 /******************************************************************************/
00168 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00169 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00170 /*  available peripheral interrupt handler's name please refer to the startup */
00171 /*  file (startup_stm32f10x_xx.s).                                            */
00172 /******************************************************************************/
00173
00174 /**
00175   * @brief  This function handles PPP interrupt request.
00176   * @param  None
00177   * @retval None
00178   */
00179 /*void PPP_IRQHandler(void)
00180 {
00181 }*/
00182
00183 /**
00184   * @}
00185   */
00186
00187 /**
00188   * @}
00189   */
00190
00191 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/stm32f10x_it.h

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00001 /**
00002   ******************************************************************************
00003   * @file    ADC/AnalogWatchdog/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00044 void ADC1_IRQHandler(void);
00045 #else
00046 void ADC1_2_IRQHandler(void);
00047 #endif
00048
00049 #endif /* __STM32F10x_IT_H */
00050
00051 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/main.c

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00001 /**
00002   ******************************************************************************
00003   * @file    ADC/ExtLinesTrigger/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x.h"
00024
00025 /** @addtogroup STM32F10x_StdPeriph_Examples
00026   * @{
00027   */
00028
00029 /** @addtogroup ADC_ExtLinesTrigger
00030   * @{
00031   */
00032
00033 /* Private typedef -----------------------------------------------------------*/
00034 /* Private define ------------------------------------------------------------*/
00035 #define ADC1_DR_Address    ((uint32_t)0x4001244C)
00036
00037 /* Private macro -------------------------------------------------------------*/
00038 /* Private variables ---------------------------------------------------------*/
00039 ADC_InitTypeDef   ADC_InitStructure;
00040 DMA_InitTypeDef   DMA_InitStructure;
00041 __IO uint16_t ADC_RegularConvertedValueTab[64], ADC_InjectedConvertedValueTab[32];
00042
00043 /* Private function prototypes -----------------------------------------------*/
00044 void RCC_Configuration(void);
00045 void GPIO_Configuration(void);
00046 void NVIC_Configuration(void);
00047 void EXTI_Configuration(void);
00048
00049 /* Private functions ---------------------------------------------------------*/
00050
00051 /**
00052   * @brief   Main program
00053   * @param  None
00054   * @retval None
00055   */
00056 int main(void)
00057 {
00058   /*!< At this stage the microcontroller clock setting is already configured,
00059        this is done through SystemInit() function which is called from startup
00060        file (startup_stm32f10x_xx.s) before to branch to application main.
00061        To reconfigure the default setting of SystemInit() function, refer to
00062        system_stm32f10x.c file
00063      */
00064
00065   /* System clocks configuration ---------------------------------------------*/
00066   RCC_Configuration();
00067
00068   /* NVIC configuration ------------------------------------------------------*/
00069   NVIC_Configuration();
00070
00071   /* GPIO configuration ------------------------------------------------------*/
00072   GPIO_Configuration();
00073
00074   /* EXTI configuration ------------------------------------------------------*/
00075   EXTI_Configuration();
00076
00077   /* DMA1 channel1 configuration ----------------------------------------------*/
00078   DMA_DeInit(DMA1_Channel1);
00079   DMA_InitStructure.DMA_PeripheralBaseAddr = ADC1_DR_Address;
00080   DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)ADC_RegularConvertedValueTab;
00081   DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
00082   DMA_InitStructure.DMA_BufferSize = 64;
00083   DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
00084   DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
00085   DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord;
00086   DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
00087   DMA_InitStructure.DMA_Mode = DMA_Mode_Circular;
00088   DMA_InitStructure.DMA_Priority = DMA_Priority_High;
00089   DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
00090   DMA_Init(DMA1_Channel1, &DMA_InitStructure);
00091
00092   /* Enable DMA1 channel1 */
00093   DMA_Cmd(DMA1_Channel1, ENABLE);
00094
00095   /* ADC1 configuration ------------------------------------------------------*/
00096   ADC_InitStructure.ADC_Mode = ADC_Mode_Independent;
00097   ADC_InitStructure.ADC_ScanConvMode = ENABLE;
00098   ADC_InitStructure.ADC_ContinuousConvMode = DISABLE;
00099   ADC_InitStructure.ADC_ExternalTrigConv = ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO;
00100   ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right;
00101   ADC_InitStructure.ADC_NbrOfChannel = 2;
00102   ADC_Init(ADC1, &ADC_InitStructure);
00103
00104   /* ADC1 regular channels configuration */
00105   ADC_RegularChannelConfig(ADC1, ADC_Channel_4, 1, ADC_SampleTime_28Cycles5);
00106   ADC_RegularChannelConfig(ADC1, ADC_Channel_14, 2, ADC_SampleTime_28Cycles5);
00107
00108   /* Regular discontinuous mode channel number configuration */
00109   ADC_DiscModeChannelCountConfig(ADC1, 1);
00110   /* Enable regular discontinuous mode */
00111   ADC_DiscModeCmd(ADC1, ENABLE);
00112
00113   /* Enable ADC1 external trigger conversion */
00114   ADC_ExternalTrigConvCmd(ADC1, ENABLE);
00115
00116   /* Set injected sequencer length */
00117   ADC_InjectedSequencerLengthConfig(ADC1, 2);
00118   /* ADC1 injected channel configuration */
00119   ADC_InjectedChannelConfig(ADC1, ADC_Channel_11, 1, ADC_SampleTime_28Cycles5);
00120   ADC_InjectedChannelConfig(ADC1, ADC_Channel_12, 2, ADC_SampleTime_28Cycles5);
00121   /* ADC1 injected external trigger configuration */
00122   ADC_ExternalTrigInjectedConvConfig(ADC1, ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4);
00123   /* Enable ADC1 injected external trigger conversion */
00124   ADC_ExternalTrigInjectedConvCmd(ADC1, ENABLE);
00125
00126   /* Enable JEOC interrupt */
00127   ADC_ITConfig(ADC1, ADC_IT_JEOC, ENABLE);
00128
00129   /* Enable ADC1 DMA */
00130   ADC_DMACmd(ADC1, ENABLE);
00131
00132   /* Enable ADC1 */
00133   ADC_Cmd(ADC1, ENABLE);
00134
00135   /* Enable ADC1 reset calibration register */
00136   ADC_ResetCalibration(ADC1);
00137   /* Check the end of ADC1 reset calibration register */
00138   while(ADC_GetResetCalibrationStatus(ADC1));
00139
00140   /* Start ADC1 calibration */
00141   ADC_StartCalibration(ADC1);
00142   /* Check the end of ADC1 calibration */
00143   while(ADC_GetCalibrationStatus(ADC1));
00144
00145   while (1)
00146   {
00147   }
00148 }
00149
00150 /**
00151   * @brief  Configures the different system clocks.
00152   * @param  None
00153   * @retval None
00154   */
00155 void RCC_Configuration(void)
00156 {
00157 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00158   /* ADCCLK = PCLK2/2 */
00159   RCC_ADCCLKConfig(RCC_PCLK2_Div2);
00160 #else
00161   /* ADCCLK = PCLK2/4 */
00162   RCC_ADCCLKConfig(RCC_PCLK2_Div4);
00163 #endif
00164   /* Enable peripheral clocks ------------------------------------------------*/
00165   /* Enable DMA1 clock */
00166   RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE);
00167
00168   /* Enable GPIOs and ADC1 clock */
00169   RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOC |
00170                          RCC_APB2Periph_GPIOE | RCC_APB2Periph_AFIO |
00171                          RCC_APB2Periph_ADC1, ENABLE);
00172 }
00173
00174 /**
00175   * @brief  Configures the different EXTI lines.
00176   * @param  None
00177   * @retval None
00178   */
00179 void EXTI_Configuration(void)
00180 {
00181   EXTI_InitTypeDef EXTI_InitStructure;
00182 #ifdef STM32F10X_HD_VL
00183   /* Select the EXTI Line11 the GPIO pin source */
00184   GPIO_EXTILineConfig(GPIO_PortSourceGPIOF, GPIO_PinSource11);
00185 #else
00186   GPIO_EXTILineConfig(GPIO_PortSourceGPIOE, GPIO_PinSource11);
00187 #endif
00188
00189   /* EXTI line11 configuration -----------------------------------------------*/
00190   EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Event;
00191   EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;
00192   EXTI_InitStructure.EXTI_Line = EXTI_Line11;
00193   EXTI_InitStructure.EXTI_LineCmd = ENABLE;
00194   EXTI_Init(&EXTI_InitStructure);
00195
00196   /* Select the EXTI Line15 the GPIO pin source */
00197   GPIO_EXTILineConfig(GPIO_PortSourceGPIOE, GPIO_PinSource15);
00198   /* EXTI line15 configuration -----------------------------------------------*/
00199   EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Event;
00200   EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;
00201   EXTI_InitStructure.EXTI_Line = EXTI_Line15;
00202   EXTI_InitStructure.EXTI_LineCmd = ENABLE;
00203   EXTI_Init(&EXTI_InitStructure);
00204 }
00205
00206 /**
00207   * @brief  Configures the different GPIO ports.
00208   * @param  None
00209   * @retval None
00210   */
00211 void GPIO_Configuration(void)
00212 {
00213   GPIO_InitTypeDef GPIO_InitStructure;
00214
00215   /* Configure PC.01, PC.02 and PC.04 (ADC Channel11, Channel12 and Channel14)
00216    as analog input -----------------------------------------------------------*/
00217   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_4;
00218   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AIN;
00219   GPIO_Init(GPIOC, &GPIO_InitStructure);
00220
00221   /* Configure PA.04 (ADC Channel4) as analog input --------------------------*/
00222   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4;
00223   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AIN;
00224   GPIO_Init(GPIOA, &GPIO_InitStructure);
00225
00226   /* Configure EXTI line11 ---------------------------------------------------*/
00227   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11;
00228   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
00229 #ifdef STM32F10X_HD_VL
00230   GPIO_Init(GPIOF, &GPIO_InitStructure);
00231 #else
00232   GPIO_Init(GPIOE, &GPIO_InitStructure);
00233 #endif
00234
00235   /* Configure EXTI line15 ---------------------------------------------------*/
00236   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_15;
00237   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
00238   GPIO_Init(GPIOE, &GPIO_InitStructure);
00239 }
00240
00241 /**
00242   * @brief  Configures NVIC and Vector Table base location.
00243   * @param  None
00244   * @retval None
00245   */
00246 void NVIC_Configuration(void)
00247 {
00248   NVIC_InitTypeDef NVIC_InitStructure;
00249
00250     /* Configure and enable ADC interrupt */
00251 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00252   NVIC_InitStructure.NVIC_IRQChannel = ADC1_IRQn;
00253 #else
00254   NVIC_InitStructure.NVIC_IRQChannel = ADC1_2_IRQn;
00255 #endif
00256   NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
00257   NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
00258   NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
00259   NVIC_Init(&NVIC_InitStructure);
00260 }
00261
00262 #ifdef  USE_FULL_ASSERT
00263
00264 /**
00265   * @brief  Reports the name of the source file and the source line number
00266   *         where the assert_param error has occurred.
00267   * @param  file: pointer to the source file name
00268   * @param  line: assert_param error line source number
00269   * @retval None
00270   */
00271 void assert_failed(uint8_t* file, uint32_t line)
00272 {
00273   /* User can add his own implementation to report the file name and line number,
00274      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00275
00276   /* Infinite loop */
00277   while (1)
00278   {
00279   }
00280 }
00281
00282 #endif
00283
00284 /**
00285   * @}
00286   */
00287
00288 /**
00289   * @}
00290   */
00291
00292 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_conf.h

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00001 /**
00002   ******************************************************************************
00003   * @file    ADC/ExtLinesTrigger/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052 /* Exported types ------------------------------------------------------------*/
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Uncomment the line below to expanse the "assert_param" macro in the
00055    Standard Peripheral Library drivers code */
00056 /* #define USE_FULL_ASSERT    1 */
00057
00058 /* Exported macro ------------------------------------------------------------*/
00059 #ifdef  USE_FULL_ASSERT
00060
00061 /**
00062   * @brief  The assert_param macro is used for function's parameters check.
00063   * @param  expr: If expr is false, it calls assert_failed function which reports
00064   *         the name of the source file and the source line number of the call
00065   *         that failed. If expr is true, it returns no value.
00066   * @retval None
00067   */
00068   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00069 /* Exported functions ------------------------------------------------------- */
00070   void assert_failed(uint8_t* file, uint32_t line);
00071 #else
00072   #define assert_param(expr) ((void)0)
00073 #endif /* USE_FULL_ASSERT */
00074
00075 #endif /* __STM32F10x_CONF_H */
00076
00077 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_it.c

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00001 /**
00002   ******************************************************************************
00003   * @file    ADC/ExtLinesTrigger/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and peripherals
00009   *          interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026
00027 /** @addtogroup STM32F10x_StdPeriph_Examples
00028   * @{
00029   */
00030
00031 /** @addtogroup ADC_ExtLinesTrigger
00032   * @{
00033   */
00034
00035 /* Private typedef -----------------------------------------------------------*/
00036 /* Private define ------------------------------------------------------------*/
00037 /* Private macro -------------------------------------------------------------*/
00038 /* Private variables ---------------------------------------------------------*/
00039 extern __IO uint16_t ADC_InjectedConvertedValueTab[32];
00040 uint32_t Index = 0;
00041
00042 /* Private function prototypes -----------------------------------------------*/
00043 /* Private functions ---------------------------------------------------------*/
00044
00045 /******************************************************************************/
00046 /*            Cortex-M3 Processor Exceptions Handlers                         */
00047 /******************************************************************************/
00048
00049 /**
00050   * @brief  This function handles NMI exception.
00051   * @param  None
00052   * @retval None
00053   */
00054 void NMI_Handler(void)
00055 {
00056 }
00057
00058 /**
00059   * @brief  This function handles Hard Fault exception.
00060   * @param  None
00061   * @retval None
00062   */
00063 void HardFault_Handler(void)
00064 {
00065   /* Go to infinite loop when Hard Fault exception occurs */
00066   while (1)
00067   {
00068   }
00069 }
00070
00071 /**
00072   * @brief  This function handles Memory Manage exception.
00073   * @param  None
00074   * @retval None
00075   */
00076 void MemManage_Handler(void)
00077 {
00078   /* Go to infinite loop when Memory Manage exception occurs */
00079   while (1)
00080   {
00081   }
00082 }
00083
00084 /**
00085   * @brief  This function handles Bus Fault exception.
00086   * @param  None
00087   * @retval None
00088   */
00089 void BusFault_Handler(void)
00090 {
00091   /* Go to infinite loop when Bus Fault exception occurs */
00092   while (1)
00093   {
00094   }
00095 }
00096
00097 /**
00098   * @brief  This function handles Usage Fault exception.
00099   * @param  None
00100   * @retval None
00101   */
00102 void UsageFault_Handler(void)
00103 {
00104   /* Go to infinite loop when Usage Fault exception occurs */
00105   while (1)
00106   {
00107   }
00108 }
00109
00110 /**
00111   * @brief  This function handles SVCall exception.
00112   * @param  None
00113   * @retval None
00114   */
00115 void SVC_Handler(void)
00116 {
00117 }
00118
00119 /**
00120   * @brief  This function handles Debug Monitor exception.
00121   * @param  None
00122   * @retval None
00123   */
00124 void DebugMon_Handler(void)
00125 {
00126 }
00127
00128 /**
00129   * @brief  This function handles PendSV_Handler exception.
00130   * @param  None
00131   * @retval None
00132   */
00133 void PendSV_Handler(void)
00134 {
00135 }
00136
00137 /**
00138   * @brief  This function handles SysTick Handler.
00139   * @param  None
00140   * @retval None
00141   */
00142 void SysTick_Handler(void)
00143 {
00144 }
00145
00146 /******************************************************************************/
00147 /*            STM32F10x Peripherals Interrupt Handlers                        */
00148 /******************************************************************************/
00149
00150 /**
00151   * @brief  This function handles ADC1 and ADC2 global interrupts requests.
00152   * @param  None
00153   * @retval None
00154   */
00155 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00156 void ADC1_IRQHandler(void)
00157 #else
00158 void ADC1_2_IRQHandler(void)
00159 #endif
00160 {
00161   /* Clear ADC1 JEOC pending interrupt bit */
00162   ADC_ClearITPendingBit(ADC1, ADC_IT_JEOC);
00163
00164   /* Get injected channel11 and channel12 converted value */
00165   ADC_InjectedConvertedValueTab[Index++] = ADC_GetInjectedConversionValue(ADC1, ADC_InjectedChannel_1);
00166   ADC_InjectedConvertedValueTab[Index++] = ADC_GetInjectedConversionValue(ADC1, ADC_InjectedChannel_2);
00167
00168   if (Index == 32)
00169   {
00170     Index = 0;
00171   }
00172 }
00173
00174 /******************************************************************************/
00175 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00176 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00177 /*  available peripheral interrupt handler's name please refer to the startup */
00178 /*  file (startup_stm32f10x_xx.s).                                            */
00179 /******************************************************************************/
00180
00181 /**
00182   * @brief  This function handles PPP interrupt request.
00183   * @param  None
00184   * @retval None
00185   */
00186 /*void PPP_IRQHandler(void)
00187 {
00188 }*/
00189
00190 /**
00191   * @}
00192   */
00193
00194 /**
00195   * @}
00196   */
00197
00198 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_it.h

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00001 /**
00002   ******************************************************************************
00003   * @file    ADC/ExtLinesTrigger/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL)
00044 void ADC1_IRQHandler(void);
00045 #else
00046 void ADC1_2_IRQHandler(void);
00047 #endif
00048
00049 #endif /* __STM32F10x_IT_H */
00050
00051 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/main.c

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00001 /**
00002   ******************************************************************************
00003   * @file    ADC/RegSimul_DualMode/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x.h"
00024
00025 /** @addtogroup STM32F10x_StdPeriph_Examples
00026   * @{
00027   */
00028
00029 /** @addtogroup ADC_RegSimul_DualMode
00030   * @{
00031   */
00032
00033 /* Private typedef -----------------------------------------------------------*/
00034 /* Private define ------------------------------------------------------------*/
00035 #define ADC1_DR_Address    ((uint32_t)0x4001244C)
00036
00037 /* Private macro -------------------------------------------------------------*/
00038 /* Private variables ---------------------------------------------------------*/
00039 ADC_InitTypeDef ADC_InitStructure;
00040 DMA_InitTypeDef DMA_InitStructure;
00041 __IO uint32_t ADC_DualConvertedValueTab[16];
00042
00043 /* Private function prototypes -----------------------------------------------*/
00044 void RCC_Configuration(void);
00045 void GPIO_Configuration(void);
00046
00047 /* Private functions ---------------------------------------------------------*/
00048
00049 /**
00050   * @brief   Main program
00051   * @param  None
00052   * @retval None
00053   */
00054 int main(void)
00055 {
00056   /*!< At this stage the microcontroller clock setting is already configured,
00057        this is done through SystemInit() function which is called from startup
00058        file (startup_stm32f10x_xx.s) before to branch to application main.
00059        To reconfigure the default setting of SystemInit() function, refer to
00060        system_stm32f10x.c file
00061      */
00062
00063   /* System clocks configuration ---------------------------------------------*/
00064   RCC_Configuration();
00065
00066   /* GPIO configuration ------------------------------------------------------*/
00067   GPIO_Configuration();
00068
00069   /* DMA1 channel1 configuration ----------------------------------------------*/
00070   DMA_DeInit(DMA1_Channel1);
00071   DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)ADC1_DR_Address;
00072   DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)ADC_DualConvertedValueTab;
00073   DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
00074   DMA_InitStructure.DMA_BufferSize = 16;
00075   DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
00076   DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
00077   DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Word;
00078   DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Word;
00079   DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
00080   DMA_InitStructure.DMA_Priority = DMA_Priority_High;
00081   DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
00082   DMA_Init(DMA1_Channel1, &DMA_InitStructure);
00083   /* Enable DMA1 Channel1 */
00084   DMA_Cmd(DMA1_Channel1, ENABLE);
00085
00086   /* ADC1 configuration ------------------------------------------------------*/
00087   ADC_InitStructure.ADC_Mode = ADC_Mode_RegSimult;
00088   ADC_InitStructure.ADC_ScanConvMode = ENABLE;
00089   ADC_InitStructure.ADC_ContinuousConvMode = ENABLE;
00090   ADC_InitStructure.ADC_ExternalTrigConv = ADC_ExternalTrigConv_None;
00091   ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right;
00092   ADC_InitStructure.ADC_NbrOfChannel = 2;
00093   ADC_Init(ADC1, &ADC_InitStructure);
00094   /* ADC1 regular channels configuration */
00095   ADC_RegularChannelConfig(ADC1, ADC_Channel_14, 1, ADC_SampleTime_239Cycles5);
00096   ADC_RegularChannelConfig(ADC1, ADC_Channel_17, 2, ADC_SampleTime_239Cycles5);
00097   /* Enable ADC1 DMA */
00098   ADC_DMACmd(ADC1, ENABLE);
00099
00100   /* ADC2 configuration ------------------------------------------------------*/
00101   ADC_InitStructure.ADC_Mode = ADC_Mode_RegSimult;
00102   ADC_InitStructure.ADC_ScanConvMode = ENABLE;
00103   ADC_InitStructure.ADC_ContinuousConvMode = ENABLE;
00104   ADC_InitStructure.ADC_ExternalTrigConv = ADC_ExternalTrigConv_None;
00105   ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right;
00106   ADC_InitStructure.ADC_NbrOfChannel = 2;
00107   ADC_Init(ADC2, &ADC_InitStructure);
00108   /* ADC2 regular channels configuration */
00109   ADC_RegularChannelConfig(ADC2, ADC_Channel_11, 1, ADC_SampleTime_239Cycles5);
00110   ADC_RegularChannelConfig(ADC2, ADC_Channel_12, 2, ADC_SampleTime_239Cycles5);
00111   /* Enable ADC2 external trigger conversion */
00112   ADC_ExternalTrigConvCmd(ADC2, ENABLE);
00113
00114   /* Enable ADC1 */
00115   ADC_Cmd(ADC1, ENABLE);
00116   /* Enable Vrefint channel17 */
00117   ADC_TempSensorVrefintCmd(ENABLE);
00118
00119   /* Enable ADC1 reset calibration register */
00120   ADC_ResetCalibration(ADC1);
00121   /* Check the end of ADC1 reset calibration register */
00122   while(ADC_GetResetCalibrationStatus(ADC1));
00123
00124   /* Start ADC1 calibration */
00125   ADC_StartCalibration(ADC1);
00126   /* Check the end of ADC1 calibration */
00127   while(ADC_GetCalibrationStatus(ADC1));
00128
00129   /* Enable ADC2 */
00130   ADC_Cmd(ADC2, ENABLE);
00131
00132   /* Enable ADC2 reset calibration register */
00133   ADC_ResetCalibration(ADC2);
00134   /* Check the end of ADC2 reset calibration register */
00135   while(ADC_GetResetCalibrationStatus(ADC2));
00136
00137   /* Start ADC2 calibration */
00138   ADC_StartCalibration(ADC2);
00139   /* Check the end of ADC2 calibration */
00140   while(ADC_GetCalibrationStatus(ADC2));
00141
00142   /* Start ADC1 Software Conversion */
00143   ADC_SoftwareStartConvCmd(ADC1, ENABLE);
00144
00145   /* Test on DMA1 channel1 transfer complete flag */
00146   while(!DMA_GetFlagStatus(DMA1_FLAG_TC1));
00147   /* Clear DMA1 channel1 transfer complete flag */
00148   DMA_ClearFlag(DMA1_FLAG_TC1);
00149
00150   while (1)
00151   {
00152   }
00153 }
00154
00155 /**
00156   * @brief  Configures the different system clocks.
00157   * @param  None
00158   * @retval None
00159   */
00160 void RCC_Configuration(void)
00161 {
00162   /* ADCCLK = PCLK2/4 */
00163   RCC_ADCCLKConfig(RCC_PCLK2_Div4);
00164   /* Enable peripheral clocks ------------------------------------------------*/
00165   /* Enable DMA1 clock */
00166   RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE);
00167
00168   /* Enable ADC1, ADC2 and GPIOC clock */
00169   RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1 | RCC_APB2Periph_ADC2 |
00170                          RCC_APB2Periph_GPIOC, ENABLE);
00171 }
00172
00173 /**
00174   * @brief  Configures the different GPIO ports.
00175   * @param  None
00176   * @retval None
00177   */
00178 void GPIO_Configuration(void)
00179 {
00180   GPIO_InitTypeDef GPIO_InitStructure;
00181
00182   /* Configure PC.01, PC.02 and PC.04 (ADC Channel11, Channel12 and Channel14)
00183     as analog input ----------------------------------------------------------*/
00184   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_4;
00185   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AIN;
00186   GPIO_Init(GPIOC, &GPIO_InitStructure);
00187 }
00188
00189 #ifdef  USE_FULL_ASSERT
00190
00191 /**
00192   * @brief  Reports the name of the source file and the source line number
00193   *         where the assert_param error has occurred.
00194   * @param  file: pointer to the source file name
00195   * @param  line: assert_param error line source number
00196   * @retval None
00197   */
00198 void assert_failed(uint8_t* file, uint32_t line)
00199 {
00200   /* User can add his own implementation to report the file name and line number,
00201      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00202
00203   /* Infinite loop */
00204   while (1)
00205   {
00206   }
00207 }
00208
00209 #endif
00210
00211 /**
00212   * @}
00213   */
00214
00215 /**
00216   * @}
00217   */
00218
00219 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/stm32f10x_conf.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    ADC/RegSimul_DualMode/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052 /* Exported types ------------------------------------------------------------*/
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Uncomment the line below to expanse the "assert_param" macro in the
00055    Standard Peripheral Library drivers code */
00056 /* #define USE_FULL_ASSERT    1 */
00057
00058 /* Exported macro ------------------------------------------------------------*/
00059 #ifdef  USE_FULL_ASSERT
00060
00061 /**
00062   * @brief  The assert_param macro is used for function's parameters check.
00063   * @param  expr: If expr is false, it calls assert_failed function which reports
00064   *         the name of the source file and the source line number of the call
00065   *         that failed. If expr is true, it returns no value.
00066   * @retval None
00067   */
00068   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00069 /* Exported functions ------------------------------------------------------- */
00070   void assert_failed(uint8_t* file, uint32_t line);
00071 #else
00072   #define assert_param(expr) ((void)0)
00073 #endif /* USE_FULL_ASSERT */
00074
00075 #endif /* __STM32F10x_CONF_H */
00076
00077 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/stm32f10x_it.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    ADC/RegSimul_DualMode/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and peripherals
00009   *          interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026
00027 /** @addtogroup STM32F10x_StdPeriph_Examples
00028   * @{
00029   */
00030
00031 /** @addtogroup ADC_RegSimul_DualMode
00032   * @{
00033   */
00034
00035 /* Private typedef -----------------------------------------------------------*/
00036 /* Private define ------------------------------------------------------------*/
00037 /* Private macro -------------------------------------------------------------*/
00038 /* Private variables ---------------------------------------------------------*/
00039 /* Private function prototypes -----------------------------------------------*/
00040 /* Private functions ---------------------------------------------------------*/
00041
00042 /******************************************************************************/
00043 /*            Cortex-M3 Processor Exceptions Handlers                         */
00044 /******************************************************************************/
00045
00046 /**
00047   * @brief  This function handles NMI exception.
00048   * @param  None
00049   * @retval None
00050   */
00051 void NMI_Handler(void)
00052 {
00053 }
00054
00055 /**
00056   * @brief  This function handles Hard Fault exception.
00057   * @param  None
00058   * @retval None
00059   */
00060 void HardFault_Handler(void)
00061 {
00062   /* Go to infinite loop when Hard Fault exception occurs */
00063   while (1)
00064   {
00065   }
00066 }
00067
00068 /**
00069   * @brief  This function handles Memory Manage exception.
00070   * @param  None
00071   * @retval None
00072   */
00073 void MemManage_Handler(void)
00074 {
00075   /* Go to infinite loop when Memory Manage exception occurs */
00076   while (1)
00077   {
00078   }
00079 }
00080
00081 /**
00082   * @brief  This function handles Bus Fault exception.
00083   * @param  None
00084   * @retval None
00085   */
00086 void BusFault_Handler(void)
00087 {
00088   /* Go to infinite loop when Bus Fault exception occurs */
00089   while (1)
00090   {
00091   }
00092 }
00093
00094 /**
00095   * @brief  This function handles Usage Fault exception.
00096   * @param  None
00097   * @retval None
00098   */
00099 void UsageFault_Handler(void)
00100 {
00101   /* Go to infinite loop when Usage Fault exception occurs */
00102   while (1)
00103   {
00104   }
00105 }
00106
00107 /**
00108   * @brief  This function handles SVCall exception.
00109   * @param  None
00110   * @retval None
00111   */
00112 void SVC_Handler(void)
00113 {
00114 }
00115
00116 /**
00117   * @brief  This function handles Debug Monitor exception.
00118   * @param  None
00119   * @retval None
00120   */
00121 void DebugMon_Handler(void)
00122 {
00123 }
00124
00125 /**
00126   * @brief  This function handles PendSV_Handler exception.
00127   * @param  None
00128   * @retval None
00129   */
00130 void PendSV_Handler(void)
00131 {
00132 }
00133
00134 /**
00135   * @brief  This function handles SysTick Handler.
00136   * @param  None
00137   * @retval None
00138   */
00139 void SysTick_Handler(void)
00140 {
00141 }
00142
00143 /******************************************************************************/
00144 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00145 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00146 /*  available peripheral interrupt handler's name please refer to the startup */
00147 /*  file (startup_stm32f10x_xx.s).                                            */
00148 /******************************************************************************/
00149
00150 /**
00151   * @brief  This function handles PPP interrupt request.
00152   * @param  None
00153   * @retval None
00154   */
00155 /*void PPP_IRQHandler(void)
00156 {
00157 }*/
00158
00159 /**
00160   * @}
00161   */
00162
00163 /**
00164   * @}
00165   */
00166
00167 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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  • RegSimul_DualMode

STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/stm32f10x_it.h

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00001 /**
00002   ******************************************************************************
00003   * @file    ADC/RegSimul_DualMode/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043
00044 #endif /* __STM32F10x_IT_H */
00045
00046 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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  • TIMTrigger_AutoInjection

STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/main.c

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00001 /**
00002   ******************************************************************************
00003   * @file    ADC/TIMTrigger_AutoInjection/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x.h"
00024
00025 /** @addtogroup STM32F10x_StdPeriph_Examples
00026   * @{
00027   */
00028
00029 /** @addtogroup ADC_TIMTrigger_AutoInjection
00030   * @{
00031   */
00032
00033 /* Private typedef -----------------------------------------------------------*/
00034 /* Private define ------------------------------------------------------------*/
00035 #define ADC1_DR_Address    ((uint32_t)0x4001244C)
00036
00037 /* Private macro -------------------------------------------------------------*/
00038 /* Private variables ---------------------------------------------------------*/
00039 ADC_InitTypeDef           ADC_InitStructure;
00040 DMA_InitTypeDef           DMA_InitStructure;
00041 TIM_TimeBaseInitTypeDef   TIM_TimeBaseStructure;
00042 TIM_OCInitTypeDef         TIM_OCInitStructure;
00043 __IO uint16_t ADC_RegularConvertedValueTab[32], ADC_InjectedConvertedValueTab[32];
00044
00045 /* Private function prototypes -----------------------------------------------*/
00046 void RCC_Configuration(void);
00047 void GPIO_Configuration(void);
00048 void NVIC_Configuration(void);
00049
00050 /* Private functions ---------------------------------------------------------*/
00051
00052 /**
00053   * @brief   Main program
00054   * @param  None
00055   * @retval None
00056   */
00057 int main(void)
00058 {
00059   /*!< At this stage the microcontroller clock setting is already configured,
00060        this is done through SystemInit() function which is called from startup
00061        file (startup_stm32f10x_xx.s) before to branch to application main.
00062        To reconfigure the default setting of SystemInit() function, refer to
00063        system_stm32f10x.c file
00064      */
00065
00066   /* System clocks configuration ---------------------------------------------*/
00067   RCC_Configuration();
00068
00069   /* NVIC configuration ------------------------------------------------------*/
00070   NVIC_Configuration();
00071
00072   /* GPIO configuration ------------------------------------------------------*/
00073   GPIO_Configuration();
00074
00075   /* TIM1 configuration ------------------------------------------------------*/
00076   /* Time Base configuration */
00077   TIM_TimeBaseStructInit(&TIM_TimeBaseStructure);
00078   TIM_TimeBaseStructure.TIM_Period = 0xFF;
00079   TIM_TimeBaseStructure.TIM_Prescaler = 0x4;
00080   TIM_TimeBaseStructure.TIM_ClockDivision = 0x0;
00081   TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
00082   TIM_TimeBaseInit(TIM1, &TIM_TimeBaseStructure);
00083   /* TIM1 channel1 configuration in PWM mode */
00084   TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1;
00085   TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
00086   TIM_OCInitStructure.TIM_Pulse = 0x7F;
00087   TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_Low;
00088   TIM_OC1Init(TIM1, &TIM_OCInitStructure);
00089
00090   /* DMA1 Channel1 Configuration ----------------------------------------------*/
00091   DMA_DeInit(DMA1_Channel1);
00092   DMA_InitStructure.DMA_PeripheralBaseAddr = ADC1_DR_Address;
00093   DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)ADC_RegularConvertedValueTab;
00094   DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
00095   DMA_InitStructure.DMA_BufferSize = 32;
00096   DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
00097   DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
00098   DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord;
00099   DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
00100   DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
00101   DMA_InitStructure.DMA_Priority = DMA_Priority_High;
00102   DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
00103   DMA_Init(DMA1_Channel1, &DMA_InitStructure);
00104
00105   /* Enable DMA1 channel1 */
00106   DMA_Cmd(DMA1_Channel1, ENABLE);
00107
00108   /* ADC1 configuration ------------------------------------------------------*/
00109   ADC_InitStructure.ADC_Mode = ADC_Mode_Independent;
00110   ADC_InitStructure.ADC_ScanConvMode = DISABLE;
00111   ADC_InitStructure.ADC_ContinuousConvMode = DISABLE;
00112   ADC_InitStructure.ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1;
00113   ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right;
00114   ADC_InitStructure.ADC_NbrOfChannel = 1;
00115   ADC_Init(ADC1, &ADC_InitStructure);
00116
00117   /* ADC1 regular channel14 configuration */
00118   ADC_RegularChannelConfig(ADC1, ADC_Channel_14, 1, ADC_SampleTime_13Cycles5);
00119
00120   /* Set injected sequencer length */
00121   ADC_InjectedSequencerLengthConfig(ADC1, 1);
00122   /* ADC1 injected channel Configuration */
00123   ADC_InjectedChannelConfig(ADC1, ADC_Channel_11, 1, ADC_SampleTime_71Cycles5);
00124   /* ADC1 injected external trigger configuration */
00125   ADC_ExternalTrigInjectedConvConfig(ADC1, ADC_ExternalTrigInjecConv_None);
00126
00127   /* Enable automatic injected conversion start after regular one */
00128   ADC_AutoInjectedConvCmd(ADC1, ENABLE);
00129
00130   /* Enable ADC1 DMA */
00131   ADC_DMACmd(ADC1, ENABLE);
00132
00133   /* Enable ADC1 external trigger */
00134   ADC_ExternalTrigConvCmd(ADC1, ENABLE);
00135
00136   /* Enable JEOC interrupt */
00137   ADC_ITConfig(ADC1, ADC_IT_JEOC, ENABLE);
00138
00139   /* Enable ADC1 */
00140   ADC_Cmd(ADC1, ENABLE);
00141
00142   /* Enable ADC1 reset calibration register */
00143   ADC_ResetCalibration(ADC1);
00144   /* Check the end of ADC1 reset calibration register */
00145   while(ADC_GetResetCalibrationStatus(ADC1));
00146
00147   /* Start ADC1 calibration */
00148   ADC_StartCalibration(ADC1);
00149   /* Check the end of ADC1 calibration */
00150   while(ADC_GetCalibrationStatus(ADC1));
00151
00152   /* TIM1 counter enable */
00153   TIM_Cmd(TIM1, ENABLE);
00154   /* TIM1 main Output Enable */
00155   TIM_CtrlPWMOutputs(TIM1, ENABLE);
00156
00157   /* Test on channel1 transfer complete flag */
00158   while(!DMA_GetFlagStatus(DMA1_FLAG_TC1));
00159   /* Clear channel1 transfer complete flag */
00160   DMA_ClearFlag(DMA1_FLAG_TC1);
00161
00162   /* TIM1 counter disable */
00163   TIM_Cmd(TIM1, DISABLE);
00164
00165   while (1)
00166   {
00167   }
00168 }
00169
00170 /**
00171   * @brief  Configures the different system clocks.
00172   * @param  None
00173   * @retval None
00174   */
00175 void RCC_Configuration(void)
00176 {
00177 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00178   /* ADCCLK = PCLK2/2 */
00179   RCC_ADCCLKConfig(RCC_PCLK2_Div2);
00180 #else
00181   /* ADCCLK = PCLK2/4 */
00182   RCC_ADCCLKConfig(RCC_PCLK2_Div4);
00183 #endif
00184   /* Enable peripheral clocks ------------------------------------------------*/
00185   /* Enable DMA1 clock */
00186   RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE);
00187
00188   /* Enable GPIOA, GPIOC, ADC1 and TIM1 clock */
00189   RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOC |
00190                          RCC_APB2Periph_ADC1 | RCC_APB2Periph_TIM1, ENABLE);
00191 }
00192
00193 /**
00194   * @brief  Configures the different GPIO ports.
00195   * @param  None
00196   * @retval None
00197   */
00198 void GPIO_Configuration(void)
00199 {
00200   GPIO_InitTypeDef GPIO_InitStructure;
00201
00202   /* Configure TIM1_CH1 (PA8) as alternate function push-pull */
00203   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8;
00204   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00205   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
00206   GPIO_Init(GPIOA, &GPIO_InitStructure);
00207
00208   /* Configure PC.06 as output push-pull */
00209   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
00210   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
00211   GPIO_Init(GPIOC, &GPIO_InitStructure);
00212
00213   /* Configure PC.01 and PC.04 (ADC Channel11 and Channel14) as analog input */
00214   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_4;
00215   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AIN;
00216   GPIO_Init(GPIOC, &GPIO_InitStructure);
00217 }
00218
00219 /**
00220   * @brief  Configures NVIC and Vector Table base location.
00221   * @param  None
00222   * @retval None
00223   */
00224 void NVIC_Configuration(void)
00225 {
00226   NVIC_InitTypeDef NVIC_InitStructure;
00227
00228     /* Configure and enable ADC interrupt */
00229 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00230   NVIC_InitStructure.NVIC_IRQChannel = ADC1_IRQn;
00231 #else
00232   NVIC_InitStructure.NVIC_IRQChannel = ADC1_2_IRQn;
00233 #endif
00234   NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
00235   NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
00236   NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
00237   NVIC_Init(&NVIC_InitStructure);
00238 }
00239
00240 #ifdef  USE_FULL_ASSERT
00241
00242 /**
00243   * @brief  Reports the name of the source file and the source line number
00244   *         where the assert_param error has occurred.
00245   * @param  file: pointer to the source file name
00246   * @param  line: assert_param error line source number
00247   * @retval None
00248   */
00249 void assert_failed(uint8_t* file, uint32_t line)
00250 {
00251   /* User can add his own implementation to report the file name and line number,
00252      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00253
00254   /* Infinite loop */
00255   while (1)
00256   {
00257   }
00258 }
00259
00260 #endif
00261
00262 /**
00263   * @}
00264   */
00265
00266 /**
00267   * @}
00268   */
00269
00270 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_conf.h

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00001 /**
00002   ******************************************************************************
00003   * @file    ADC/TIMTrigger_AutoInjection/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052 /* Exported types ------------------------------------------------------------*/
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Uncomment the line below to expanse the "assert_param" macro in the
00055    Standard Peripheral Library drivers code */
00056 /* #define USE_FULL_ASSERT    1 */
00057
00058 /* Exported macro ------------------------------------------------------------*/
00059 #ifdef  USE_FULL_ASSERT
00060
00061 /**
00062   * @brief  The assert_param macro is used for function's parameters check.
00063   * @param  expr: If expr is false, it calls assert_failed function which reports
00064   *         the name of the source file and the source line number of the call
00065   *         that failed. If expr is true, it returns no value.
00066   * @retval None
00067   */
00068   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00069 /* Exported functions ------------------------------------------------------- */
00070   void assert_failed(uint8_t* file, uint32_t line);
00071 #else
00072   #define assert_param(expr) ((void)0)
00073 #endif /* USE_FULL_ASSERT */
00074
00075 #endif /* __STM32F10x_CONF_H */
00076
00077 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_it.c

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00001 /**
00002   ******************************************************************************
00003   * @file    ADC/TIMTrigger_AutoInjection/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and peripherals
00009   *          interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026
00027 /** @addtogroup STM32F10x_StdPeriph_Examples
00028   * @{
00029   */
00030
00031 /** @addtogroup ADC_TIMTrigger_AutoInjection
00032   * @{
00033   */
00034
00035 /* Private typedef -----------------------------------------------------------*/
00036 /* Private define ------------------------------------------------------------*/
00037 /* Private macro -------------------------------------------------------------*/
00038 /* Private variables ---------------------------------------------------------*/
00039 extern __IO uint16_t ADC_InjectedConvertedValueTab[32];
00040 __IO uint32_t Index;
00041
00042 /* Private function prototypes -----------------------------------------------*/
00043 /* Private functions ---------------------------------------------------------*/
00044
00045 /******************************************************************************/
00046 /*            Cortex-M3 Processor Exceptions Handlers                         */
00047 /******************************************************************************/
00048
00049 /**
00050   * @brief  This function handles NMI exception.
00051   * @param  None
00052   * @retval None
00053   */
00054 void NMI_Handler(void)
00055 {
00056 }
00057
00058 /**
00059   * @brief  This function handles Hard Fault exception.
00060   * @param  None
00061   * @retval None
00062   */
00063 void HardFault_Handler(void)
00064 {
00065   /* Go to infinite loop when Hard Fault exception occurs */
00066   while (1)
00067   {
00068   }
00069 }
00070
00071 /**
00072   * @brief  This function handles Memory Manage exception.
00073   * @param  None
00074   * @retval None
00075   */
00076 void MemManage_Handler(void)
00077 {
00078   /* Go to infinite loop when Memory Manage exception occurs */
00079   while (1)
00080   {
00081   }
00082 }
00083
00084 /**
00085   * @brief  This function handles Bus Fault exception.
00086   * @param  None
00087   * @retval None
00088   */
00089 void BusFault_Handler(void)
00090 {
00091   /* Go to infinite loop when Bus Fault exception occurs */
00092   while (1)
00093   {
00094   }
00095 }
00096
00097 /**
00098   * @brief  This function handles Usage Fault exception.
00099   * @param  None
00100   * @retval None
00101   */
00102 void UsageFault_Handler(void)
00103 {
00104   /* Go to infinite loop when Usage Fault exception occurs */
00105   while (1)
00106   {
00107   }
00108 }
00109
00110 /**
00111   * @brief  This function handles SVCall exception.
00112   * @param  None
00113   * @retval None
00114   */
00115 void SVC_Handler(void)
00116 {
00117 }
00118
00119 /**
00120   * @brief  This function handles Debug Monitor exception.
00121   * @param  None
00122   * @retval None
00123   */
00124 void DebugMon_Handler(void)
00125 {
00126 }
00127
00128 /**
00129   * @brief  This function handles PendSV_Handler exception.
00130   * @param  None
00131   * @retval None
00132   */
00133 void PendSV_Handler(void)
00134 {
00135 }
00136
00137 /**
00138   * @brief  This function handles SysTick Handler.
00139   * @param  None
00140   * @retval None
00141   */
00142 void SysTick_Handler(void)
00143 {
00144 }
00145
00146 /******************************************************************************/
00147 /*            STM32F10x Peripherals Interrupt Handlers                        */
00148 /******************************************************************************/
00149
00150 /**
00151   * @brief  This function handles ADC1 and ADC2 global interrupts requests.
00152   * @param  None
00153   * @retval None
00154   */
00155 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00156 void ADC1_IRQHandler(void)
00157 #else
00158 void ADC1_2_IRQHandler(void)
00159 #endif
00160 {
00161   /* Set PC.06 pin */
00162   GPIO_WriteBit(GPIOC, GPIO_Pin_6, Bit_SET);
00163   /* Get injected channel11 converted value */
00164   ADC_InjectedConvertedValueTab[Index++] = ADC_GetInjectedConversionValue(ADC1, ADC_InjectedChannel_1);
00165   /* Clear ADC1 JEOC pending interrupt bit */
00166   ADC_ClearITPendingBit(ADC1, ADC_IT_JEOC);
00167   /* Reset PC.06 pin */
00168   GPIO_WriteBit(GPIOC, GPIO_Pin_6, Bit_RESET);
00169 }
00170
00171 /******************************************************************************/
00172 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00173 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00174 /*  available peripheral interrupt handler's name please refer to the startup */
00175 /*  file (startup_stm32f10x_xx.s).                                            */
00176 /******************************************************************************/
00177
00178 /**
00179   * @brief  This function handles PPP interrupt request.
00180   * @param  None
00181   * @retval None
00182   */
00183 /*void PPP_IRQHandler(void)
00184 {
00185 }*/
00186
00187 /**
00188   * @}
00189   */
00190
00191 /**
00192   * @}
00193   */
00194
00195 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_it.h

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00001 /**
00002   ******************************************************************************
00003   * @file    ADC/TIMTrigger_AutoInjection/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL)
00044 void ADC1_IRQHandler(void);
00045 #else
00046 void ADC1_2_IRQHandler(void);
00047 #endif
00048
00049 #endif /* __STM32F10x_IT_H */
00050
00051 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c

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00001 /**
00002   ******************************************************************************
00003   * @file    ADC/3ADCs_DMA/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x.h"
00024
00025 /** @addtogroup STM32F10x_StdPeriph_Examples
00026   * @{
00027   */
00028
00029 /** @addtogroup ADC_3ADCs_DMA
00030   * @{
00031   */
00032
00033 /* Private typedef -----------------------------------------------------------*/
00034 /* Private define ------------------------------------------------------------*/
00035 #define ADC1_DR_Address    ((uint32_t)0x4001244C)
00036 #define ADC3_DR_Address    ((uint32_t)0x40013C4C)
00037
00038 /* Private macro -------------------------------------------------------------*/
00039 /* Private variables ---------------------------------------------------------*/
00040 ADC_InitTypeDef ADC_InitStructure;
00041 DMA_InitTypeDef DMA_InitStructure;
00042 __IO uint16_t ADC1ConvertedValue = 0, ADC3ConvertedValue = 0;
00043
00044 /* Private function prototypes -----------------------------------------------*/
00045 void RCC_Configuration(void);
00046 void GPIO_Configuration(void);
00047 void NVIC_Configuration(void);
00048
00049 /* Private functions ---------------------------------------------------------*/
00050
00051 /**
00052   * @brief   Main program
00053   * @param  None
00054   * @retval None
00055   */
00056 int main(void)
00057 {
00058   /*!< At this stage the microcontroller clock setting is already configured,
00059        this is done through SystemInit() function which is called from startup
00060        file (startup_stm32f10x_xx.s) before to branch to application main.
00061        To reconfigure the default setting of SystemInit() function, refer to
00062        system_stm32f10x.c file
00063      */
00064
00065   /* System clocks configuration ---------------------------------------------*/
00066   RCC_Configuration();
00067
00068   /* NVIC configuration ------------------------------------------------------*/
00069   NVIC_Configuration();
00070
00071   /* GPIO configuration ------------------------------------------------------*/
00072   GPIO_Configuration();
00073
00074   /* DMA1 channel1 configuration ----------------------------------------------*/
00075   DMA_DeInit(DMA1_Channel1);
00076   DMA_InitStructure.DMA_PeripheralBaseAddr = ADC1_DR_Address;
00077   DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)&ADC1ConvertedValue;
00078   DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
00079   DMA_InitStructure.DMA_BufferSize = 1;
00080   DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
00081   DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Disable;
00082   DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord;
00083   DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
00084   DMA_InitStructure.DMA_Mode = DMA_Mode_Circular;
00085   DMA_InitStructure.DMA_Priority = DMA_Priority_High;
00086   DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
00087   DMA_Init(DMA1_Channel1, &DMA_InitStructure);
00088   /* Enable DMA1 channel1 */
00089   DMA_Cmd(DMA1_Channel1, ENABLE);
00090
00091   /* DMA2 channel5 configuration ----------------------------------------------*/
00092   DMA_DeInit(DMA2_Channel5);
00093   DMA_InitStructure.DMA_PeripheralBaseAddr = ADC3_DR_Address;
00094   DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)&ADC3ConvertedValue;
00095   DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
00096   DMA_InitStructure.DMA_BufferSize = 1;
00097   DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
00098   DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Disable;
00099   DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord;
00100   DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
00101   DMA_InitStructure.DMA_Mode = DMA_Mode_Circular;
00102   DMA_InitStructure.DMA_Priority = DMA_Priority_High;
00103   DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
00104   DMA_Init(DMA2_Channel5, &DMA_InitStructure);
00105   /* Enable DMA2 channel5 */
00106   DMA_Cmd(DMA2_Channel5, ENABLE);
00107
00108   /* ADC1 configuration ------------------------------------------------------*/
00109   ADC_InitStructure.ADC_Mode = ADC_Mode_Independent;
00110   ADC_InitStructure.ADC_ScanConvMode = DISABLE;
00111   ADC_InitStructure.ADC_ContinuousConvMode = ENABLE;
00112   ADC_InitStructure.ADC_ExternalTrigConv = ADC_ExternalTrigConv_None;
00113   ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right;
00114   ADC_InitStructure.ADC_NbrOfChannel = 1;
00115   ADC_Init(ADC1, &ADC_InitStructure);
00116   /* ADC1 regular channels configuration */
00117   ADC_RegularChannelConfig(ADC1, ADC_Channel_14, 1, ADC_SampleTime_28Cycles5);
00118   /* Enable ADC1 DMA */
00119   ADC_DMACmd(ADC1, ENABLE);
00120
00121   /* ADC2 configuration ------------------------------------------------------*/
00122   ADC_InitStructure.ADC_Mode = ADC_Mode_Independent;
00123   ADC_InitStructure.ADC_ScanConvMode = DISABLE;
00124   ADC_InitStructure.ADC_ContinuousConvMode = ENABLE;
00125   ADC_InitStructure.ADC_ExternalTrigConv = ADC_ExternalTrigConv_None;
00126   ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right;
00127   ADC_InitStructure.ADC_NbrOfChannel = 1;
00128   ADC_Init(ADC2, &ADC_InitStructure);
00129   /* ADC2 regular channels configuration */
00130   ADC_RegularChannelConfig(ADC2, ADC_Channel_13, 1, ADC_SampleTime_28Cycles5);
00131   /* Enable ADC2 EOC interrupt */
00132   ADC_ITConfig(ADC2, ADC_IT_EOC, ENABLE);
00133
00134   /* ADC3 configuration ------------------------------------------------------*/
00135   ADC_InitStructure.ADC_Mode = ADC_Mode_Independent;
00136   ADC_InitStructure.ADC_ScanConvMode = DISABLE;
00137   ADC_InitStructure.ADC_ContinuousConvMode = ENABLE;
00138   ADC_InitStructure.ADC_ExternalTrigConv = ADC_ExternalTrigConv_None;
00139   ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right;
00140   ADC_InitStructure.ADC_NbrOfChannel = 1;
00141   ADC_Init(ADC3, &ADC_InitStructure);
00142   /* ADC3 regular channel14 configuration */
00143   ADC_RegularChannelConfig(ADC3, ADC_Channel_12, 1, ADC_SampleTime_28Cycles5);
00144   /* Enable ADC3 DMA */
00145   ADC_DMACmd(ADC3, ENABLE);
00146
00147   /* Enable ADC1 */
00148   ADC_Cmd(ADC1, ENABLE);
00149
00150   /* Enable ADC1 reset calibration register */
00151   ADC_ResetCalibration(ADC1);
00152   /* Check the end of ADC1 reset calibration register */
00153   while(ADC_GetResetCalibrationStatus(ADC1));
00154
00155   /* Start ADC1 calibration */
00156   ADC_StartCalibration(ADC1);
00157   /* Check the end of ADC1 calibration */
00158   while(ADC_GetCalibrationStatus(ADC1));
00159
00160   /* Enable ADC2 */
00161   ADC_Cmd(ADC2, ENABLE);
00162
00163   /* Enable ADC2 reset calibration register */
00164   ADC_ResetCalibration(ADC2);
00165   /* Check the end of ADC2 reset calibration register */
00166   while(ADC_GetResetCalibrationStatus(ADC2));
00167
00168   /* Start ADC2 calibration */
00169   ADC_StartCalibration(ADC2);
00170   /* Check the end of ADC2 calibration */
00171   while(ADC_GetCalibrationStatus(ADC2));
00172
00173   /* Enable ADC3 */
00174   ADC_Cmd(ADC3, ENABLE);
00175
00176   /* Enable ADC3 reset calibration register */
00177   ADC_ResetCalibration(ADC3);
00178   /* Check the end of ADC3 reset calibration register */
00179   while(ADC_GetResetCalibrationStatus(ADC3));
00180
00181   /* Start ADC3 calibration */
00182   ADC_StartCalibration(ADC3);
00183   /* Check the end of ADC3 calibration */
00184   while(ADC_GetCalibrationStatus(ADC3));
00185
00186   /* Start ADC1 Software Conversion */
00187   ADC_SoftwareStartConvCmd(ADC1, ENABLE);
00188   /* Start ADC2 Software Conversion */
00189   ADC_SoftwareStartConvCmd(ADC2, ENABLE);
00190   /* Start ADC3 Software Conversion */
00191   ADC_SoftwareStartConvCmd(ADC3, ENABLE);
00192
00193   while (1)
00194   {
00195   }
00196 }
00197
00198 /**
00199   * @brief  Configures the different system clocks.
00200   * @param  None
00201   * @retval None
00202   */
00203 void RCC_Configuration(void)
00204 {
00205   /* ADCCLK = PCLK2/4 */
00206   RCC_ADCCLKConfig(RCC_PCLK2_Div4);
00207
00208   /* Enable peripheral clocks ------------------------------------------------*/
00209   /* Enable DMA1 and DMA2 clocks */
00210   RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1 | RCC_AHBPeriph_DMA2, ENABLE);
00211
00212   /* Enable ADC1, ADC2, ADC3 and GPIOC clocks */
00213   RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1 | RCC_APB2Periph_ADC2 |
00214                          RCC_APB2Periph_ADC3 | RCC_APB2Periph_GPIOC, ENABLE);
00215 }
00216
00217 /**
00218   * @brief  Configures the different GPIO ports.
00219   * @param  None
00220   * @retval None
00221   */
00222 void GPIO_Configuration(void)
00223 {
00224   GPIO_InitTypeDef GPIO_InitStructure;
00225
00226   /* Configure PC.02, PC.03 and PC.04 (ADC Channel12, ADC Channel13 and
00227      ADC Channel14) as analog inputs */
00228   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_4;
00229   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AIN;
00230   GPIO_Init(GPIOC, &GPIO_InitStructure);
00231 }
00232
00233 /**
00234   * @brief  Configures Vector Table base location.
00235   * @param  None
00236   * @retval None
00237   */
00238 void NVIC_Configuration(void)
00239 {
00240   NVIC_InitTypeDef NVIC_InitStructure;
00241
00242   /* Configure and enable ADC interrupt */
00243   NVIC_InitStructure.NVIC_IRQChannel = ADC1_2_IRQn;
00244   NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
00245   NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
00246   NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
00247   NVIC_Init(&NVIC_InitStructure);
00248 }
00249
00250 #ifdef  USE_FULL_ASSERT
00251
00252 /**
00253   * @brief  Reports the name of the source file and the source line number
00254   *         where the assert_param error has occurred.
00255   * @param  file: pointer to the source file name
00256   * @param  line: assert_param error line source number
00257   * @retval None
00258   */
00259 void assert_failed(uint8_t* file, uint32_t line)
00260 {
00261   /* User can add his own implementation to report the file name and line number,
00262      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00263
00264   /* Infinite loop */
00265   while (1)
00266   {
00267   }
00268 }
00269
00270 #endif
00271
00272 /**
00273   * @}
00274   */
00275
00276 /**
00277   * @}
00278   */
00279
00280 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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  • 3ADCs_DMA

STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_conf.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    ADC/3ADCs_DMA/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052 /* Exported types ------------------------------------------------------------*/
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Uncomment the line below to expanse the "assert_param" macro in the
00055    Standard Peripheral Library drivers code */
00056 /* #define USE_FULL_ASSERT    1 */
00057
00058 /* Exported macro ------------------------------------------------------------*/
00059 #ifdef  USE_FULL_ASSERT
00060
00061 /**
00062   * @brief  The assert_param macro is used for function's parameters check.
00063   * @param  expr: If expr is false, it calls assert_failed function which reports
00064   *         the name of the source file and the source line number of the call
00065   *         that failed. If expr is true, it returns no value.
00066   * @retval None
00067   */
00068   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00069 /* Exported functions ------------------------------------------------------- */
00070   void assert_failed(uint8_t* file, uint32_t line);
00071 #else
00072   #define assert_param(expr) ((void)0)
00073 #endif /* USE_FULL_ASSERT */
00074
00075 #endif /* __STM32F10x_CONF_H */
00076
00077 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_it.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    ADC/3ADCs_DMA/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and peripherals
00009   *          interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026
00027 /** @addtogroup STM32F10x_StdPeriph_Examples
00028   * @{
00029   */
00030
00031 /** @addtogroup ADC_3ADCs_DMA
00032   * @{
00033   */
00034
00035 /* Private typedef -----------------------------------------------------------*/
00036 /* Private define ------------------------------------------------------------*/
00037 /* Private macro -------------------------------------------------------------*/
00038 /* Private variables ---------------------------------------------------------*/
00039 __IO uint16_t ADC2ConvertedValue;
00040
00041 /* Private function prototypes -----------------------------------------------*/
00042 /* Private functions ---------------------------------------------------------*/
00043
00044 /******************************************************************************/
00045 /*            Cortex-M3 Processor Exceptions Handlers                         */
00046 /******************************************************************************/
00047
00048 /**
00049   * @brief  This function handles NMI exception.
00050   * @param  None
00051   * @retval None
00052   */
00053 void NMI_Handler(void)
00054 {
00055 }
00056
00057 /**
00058   * @brief  This function handles Hard Fault exception.
00059   * @param  None
00060   * @retval None
00061   */
00062 void HardFault_Handler(void)
00063 {
00064   /* Go to infinite loop when Hard Fault exception occurs */
00065   while (1)
00066   {
00067   }
00068 }
00069
00070 /**
00071   * @brief  This function handles Memory Manage exception.
00072   * @param  None
00073   * @retval None
00074   */
00075 void MemManage_Handler(void)
00076 {
00077   /* Go to infinite loop when Memory Manage exception occurs */
00078   while (1)
00079   {
00080   }
00081 }
00082
00083 /**
00084   * @brief  This function handles Bus Fault exception.
00085   * @param  None
00086   * @retval None
00087   */
00088 void BusFault_Handler(void)
00089 {
00090   /* Go to infinite loop when Bus Fault exception occurs */
00091   while (1)
00092   {
00093   }
00094 }
00095
00096 /**
00097   * @brief  This function handles Usage Fault exception.
00098   * @param  None
00099   * @retval None
00100   */
00101 void UsageFault_Handler(void)
00102 {
00103   /* Go to infinite loop when Usage Fault exception occurs */
00104   while (1)
00105   {
00106   }
00107 }
00108
00109 /**
00110   * @brief  This function handles SVCall exception.
00111   * @param  None
00112   * @retval None
00113   */
00114 void SVC_Handler(void)
00115 {
00116 }
00117
00118 /**
00119   * @brief  This function handles Debug Monitor exception.
00120   * @param  None
00121   * @retval None
00122   */
00123 void DebugMon_Handler(void)
00124 {
00125 }
00126
00127 /**
00128   * @brief  This function handles PendSV_Handler exception.
00129   * @param  None
00130   * @retval None
00131   */
00132 void PendSV_Handler(void)
00133 {
00134 }
00135
00136 /**
00137   * @brief  This function handles SysTick Handler.
00138   * @param  None
00139   * @retval None
00140   */
00141 void SysTick_Handler(void)
00142 {
00143 }
00144
00145 /******************************************************************************/
00146 /*            STM32F10x Peripherals Interrupt Handlers                        */
00147 /******************************************************************************/
00148
00149 /**
00150   * @brief  This function handles ADC1 and ADC2 global interrupts requests.
00151   * @param  None
00152   * @retval None
00153   */
00154 void ADC1_2_IRQHandler(void)
00155 {
00156   /* Get injected channel13 converted value */
00157   ADC2ConvertedValue = ADC_GetConversionValue(ADC2);
00158 }
00159
00160 /******************************************************************************/
00161 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00162 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00163 /*  available peripheral interrupt handler's name please refer to the startup */
00164 /*  file (startup_stm32f10x_xx.s).                                            */
00165 /******************************************************************************/
00166
00167 /**
00168   * @brief  This function handles PPP interrupt request.
00169   * @param  None
00170   * @retval None
00171   */
00172 /*void PPP_IRQHandler(void)
00173 {
00174 }*/
00175
00176 /**
00177   * @}
00178   */
00179
00180 /**
00181   * @}
00182   */
00183
00184 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_it.h

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00001 /**
00002   ******************************************************************************
00003   * @file    ADC/3ADCs_DMA/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043 void ADC1_2_IRQHandler(void);
00044
00045 #endif /* __STM32F10x_IT_H */
00046
00047 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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STM32F10x_StdPeriph_Examples/BKP/Backup_Data/main.c

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00001 /**
00002   ******************************************************************************
00003   * @file    BKP/Backup_Data/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x.h"
00024 #include "stm32_eval.h"
00025
00026 /** @addtogroup STM32F10x_StdPeriph_Examples
00027   * @{
00028   */
00029
00030 /** @addtogroup BKP_Backup_Data
00031   * @{
00032   */
00033
00034 /* Private typedef -----------------------------------------------------------*/
00035 /* Private define ------------------------------------------------------------*/
00036 #if defined USE_STM3210B_EVAL || defined USE_STM32100B_EVAL
00037   #define BKP_DR_NUMBER              10
00038 #else
00039   #define BKP_DR_NUMBER              42
00040 #endif /* USE_STM3210B_EVAL or USE_STM32100B_EVAL */
00041
00042 /* Private macro -------------------------------------------------------------*/
00043 /* Private variables ---------------------------------------------------------*/
00044 #if defined USE_STM3210B_EVAL || defined USE_STM32100B_EVAL
00045 uint16_t BKPDataReg[BKP_DR_NUMBER] =
00046   {
00047     BKP_DR1, BKP_DR2, BKP_DR3, BKP_DR4, BKP_DR5, BKP_DR6, BKP_DR7, BKP_DR8,
00048     BKP_DR9, BKP_DR10
00049   };
00050 #else
00051 uint16_t BKPDataReg[BKP_DR_NUMBER] =
00052   {
00053     BKP_DR1, BKP_DR2, BKP_DR3, BKP_DR4, BKP_DR5, BKP_DR6, BKP_DR7, BKP_DR8,
00054     BKP_DR9, BKP_DR10, BKP_DR11, BKP_DR12, BKP_DR13, BKP_DR14, BKP_DR15, BKP_DR16,
00055     BKP_DR17, BKP_DR18, BKP_DR19, BKP_DR20, BKP_DR21, BKP_DR22, BKP_DR23, BKP_DR24,
00056     BKP_DR25, BKP_DR26, BKP_DR27, BKP_DR28, BKP_DR29, BKP_DR30, BKP_DR31, BKP_DR32,
00057     BKP_DR33, BKP_DR34, BKP_DR35, BKP_DR36, BKP_DR37, BKP_DR38, BKP_DR39, BKP_DR40,
00058     BKP_DR41, BKP_DR42
00059   };
00060 #endif /* USE_STM3210B_EVAL or USE_STM32100B_EVAL */
00061
00062 /* Private function prototypes -----------------------------------------------*/
00063 void WriteToBackupReg(uint16_t FirstBackupData);
00064 uint8_t CheckBackupReg(uint16_t FirstBackupData);
00065
00066 /* Private functions ---------------------------------------------------------*/
00067
00068 /**
00069   * @brief   Main program.
00070   * @param  None
00071   * @retval None
00072   */
00073 int main(void)
00074 {
00075   /*!< At this stage the microcontroller clock setting is already configured,
00076        this is done through SystemInit() function which is called from startup
00077        file (startup_stm32f10x_xx.s) before to branch to application main.
00078        To reconfigure the default setting of SystemInit() function, refer to
00079        system_stm32f10x.c file
00080      */
00081
00082   /* Initialize Leds mounted on STM3210X-EVAL board */
00083   STM_EVAL_LEDInit(LED1);
00084   STM_EVAL_LEDInit(LED2);
00085   STM_EVAL_LEDInit(LED3);
00086   STM_EVAL_LEDInit(LED4);
00087
00088   /* Enable PWR and BKP clock */
00089   RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR | RCC_APB1Periph_BKP, ENABLE);
00090
00091   /* Enable write access to Backup domain */
00092   PWR_BackupAccessCmd(ENABLE);
00093
00094   /* Clear Tamper pin Event(TE) pending flag */
00095   BKP_ClearFlag();
00096
00097   /* Check if the Power On Reset flag is set */
00098   if(RCC_GetFlagStatus(RCC_FLAG_PORRST) != RESET)
00099   {
00100     /* Clear reset flags */
00101     RCC_ClearFlag();
00102
00103     /* Turn on LED3 */
00104     STM_EVAL_LEDOn(LED3);
00105
00106     /* Check if Backup data registers are programmed */
00107     if(CheckBackupReg(0x3210) == 0x00)
00108     { /* Backup data registers values are correct */
00109
00110       /* Turn on LED1 */
00111       STM_EVAL_LEDOn(LED1);
00112     }
00113     else
00114     { /* Backup data registers values are not correct or they are not yet
00115          programmed (when the first time the program is executed) */
00116
00117       /* Write data to Backup data registers */
00118       WriteToBackupReg(0x3210);
00119
00120       /* Turn on LED2 */
00121       STM_EVAL_LEDOn(LED2);
00122     }
00123   }
00124
00125   /* Turn on LED4 */
00126   STM_EVAL_LEDOn(LED4);
00127
00128   while (1)
00129   {
00130   }
00131 }
00132
00133 /**
00134   * @brief  Writes data Backup DRx registers.
00135   * @param  FirstBackupData: data to be written to Backup data registers.
00136   * @retval None
00137   */
00138 void WriteToBackupReg(uint16_t FirstBackupData)
00139 {
00140   uint32_t index = 0;
00141
00142   for (index = 0; index < BKP_DR_NUMBER; index++)
00143   {
00144     BKP_WriteBackupRegister(BKPDataReg[index], FirstBackupData + (index * 0x5A));
00145   }
00146 }
00147
00148 /**
00149   * @brief  Checks if the Backup DRx registers values are correct or not.
00150   * @param  FirstBackupData: data to be compared with Backup data registers.
00151   * @retval
00152   *          - 0: All Backup DRx registers values are correct
00153   *          - Value different from 0: Number of the first Backup register
00154   *            which value is not correct
00155   */
00156 uint8_t CheckBackupReg(uint16_t FirstBackupData)
00157 {
00158   uint32_t index = 0;
00159
00160   for (index = 0; index < BKP_DR_NUMBER; index++)
00161   {
00162     if (BKP_ReadBackupRegister(BKPDataReg[index]) != (FirstBackupData + (index * 0x5A)))
00163     {
00164       return (index + 1);
00165     }
00166   }
00167
00168   return 0;
00169 }
00170
00171 #ifdef  USE_FULL_ASSERT
00172
00173 /**
00174   * @brief  Reports the name of the source file and the source line number
00175   *         where the assert_param error has occurred.
00176   * @param  file: pointer to the source file name
00177   * @param  line: assert_param error line source number
00178   * @retval None
00179   */
00180 void assert_failed(uint8_t* file, uint32_t line)
00181 {
00182   /* User can add his own implementation to report the file name and line number,
00183      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00184
00185   /* Infinite loop */
00186   while (1)
00187   {
00188   }
00189 }
00190
00191 #endif
00192
00193 /**
00194   * @}
00195   */
00196
00197 /**
00198   * @}
00199   */
00200
00201 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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STM32F10x_StdPeriph_Examples/BKP/Backup_Data/stm32f10x_conf.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    BKP/Backup_Data/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052 /* Exported types ------------------------------------------------------------*/
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Uncomment the line below to expanse the "assert_param" macro in the
00055    Standard Peripheral Library drivers code */
00056 /* #define USE_FULL_ASSERT    1 */
00057
00058 /* Exported macro ------------------------------------------------------------*/
00059 #ifdef  USE_FULL_ASSERT
00060
00061 /**
00062   * @brief  The assert_param macro is used for function's parameters check.
00063   * @param  expr: If expr is false, it calls assert_failed function which reports
00064   *         the name of the source file and the source line number of the call
00065   *         that failed. If expr is true, it returns no value.
00066   * @retval None
00067   */
00068   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00069 /* Exported functions ------------------------------------------------------- */
00070   void assert_failed(uint8_t* file, uint32_t line);
00071 #else
00072   #define assert_param(expr) ((void)0)
00073 #endif /* USE_FULL_ASSERT */
00074
00075 #endif /* __STM32F10x_CONF_H */
00076
00077 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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STM32F10x_StdPeriph_Examples/BKP/Backup_Data/stm32f10x_it.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    BKP/Backup_Data/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and peripherals
00009   *          interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026
00027 /** @addtogroup STM32F10x_StdPeriph_Examples
00028   * @{
00029   */
00030
00031 /** @addtogroup BKP_Backup_Data
00032   * @{
00033   */
00034
00035 /* Private typedef -----------------------------------------------------------*/
00036 /* Private define ------------------------------------------------------------*/
00037 /* Private macro -------------------------------------------------------------*/
00038 /* Private variables ---------------------------------------------------------*/
00039 /* Private function prototypes -----------------------------------------------*/
00040 /* Private functions ---------------------------------------------------------*/
00041
00042 /******************************************************************************/
00043 /*            Cortex-M3 Processor Exceptions Handlers                         */
00044 /******************************************************************************/
00045
00046 /**
00047   * @brief  This function handles NMI exception.
00048   * @param  None
00049   * @retval None
00050   */
00051 void NMI_Handler(void)
00052 {
00053 }
00054
00055 /**
00056   * @brief  This function handles Hard Fault exception.
00057   * @param  None
00058   * @retval None
00059   */
00060 void HardFault_Handler(void)
00061 {
00062   /* Go to infinite loop when Hard Fault exception occurs */
00063   while (1)
00064   {
00065   }
00066 }
00067
00068 /**
00069   * @brief  This function handles Memory Manage exception.
00070   * @param  None
00071   * @retval None
00072   */
00073 void MemManage_Handler(void)
00074 {
00075   /* Go to infinite loop when Memory Manage exception occurs */
00076   while (1)
00077   {
00078   }
00079 }
00080
00081 /**
00082   * @brief  This function handles Bus Fault exception.
00083   * @param  None
00084   * @retval None
00085   */
00086 void BusFault_Handler(void)
00087 {
00088   /* Go to infinite loop when Bus Fault exception occurs */
00089   while (1)
00090   {
00091   }
00092 }
00093
00094 /**
00095   * @brief  This function handles Usage Fault exception.
00096   * @param  None
00097   * @retval None
00098   */
00099 void UsageFault_Handler(void)
00100 {
00101   /* Go to infinite loop when Usage Fault exception occurs */
00102   while (1)
00103   {
00104   }
00105 }
00106
00107 /**
00108   * @brief  This function handles SVCall exception.
00109   * @param  None
00110   * @retval None
00111   */
00112 void SVC_Handler(void)
00113 {
00114 }
00115
00116 /**
00117   * @brief  This function handles Debug Monitor exception.
00118   * @param  None
00119   * @retval None
00120   */
00121 void DebugMon_Handler(void)
00122 {
00123 }
00124
00125 /**
00126   * @brief  This function handles PendSV_Handler exception.
00127   * @param  None
00128   * @retval None
00129   */
00130 void PendSV_Handler(void)
00131 {
00132 }
00133
00134 /**
00135   * @brief  This function handles SysTick Handler.
00136   * @param  None
00137   * @retval None
00138   */
00139 void SysTick_Handler(void)
00140 {
00141 }
00142
00143 /******************************************************************************/
00144 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00145 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00146 /*  available peripheral interrupt handler's name please refer to the startup */
00147 /*  file (startup_stm32f10x_xx.s).                                            */
00148 /******************************************************************************/
00149
00150 /**
00151   * @brief  This function handles PPP interrupt request.
00152   * @param  None
00153   * @retval None
00154   */
00155 /*void PPP_IRQHandler(void)
00156 {
00157 }*/
00158
00159 /**
00160   * @}
00161   */
00162
00163 /**
00164   * @}
00165   */
00166
00167 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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STM32F10x_StdPeriph_Examples/BKP/Backup_Data/stm32f10x_it.h

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00001 /**
00002   ******************************************************************************
00003   * @file    BKP/Backup_Data/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043
00044 #endif /* __STM32F10x_IT_H */
00045
00046 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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STM32F10x_StdPeriph_Examples/BKP/Tamper/main.c

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00001 /**
00002   ******************************************************************************
00003   * @file    BKP/Tamper/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "main.h"
00024
00025 /** @addtogroup STM32F10x_StdPeriph_Examples
00026   * @{
00027   */
00028
00029 /** @addtogroup BKP_Tamper
00030   * @{
00031   */
00032
00033 /* Private typedef -----------------------------------------------------------*/
00034 /* Private define ------------------------------------------------------------*/
00035 #if defined USE_STM3210B_EVAL || defined USE_STM32100B_EVAL
00036   #define BKP_DR_NUMBER              10
00037 #else
00038   #define BKP_DR_NUMBER              42
00039 #endif /* USE_STM3210B_EVAL or USE_STM32100B_EVAL */
00040
00041 /* Private macro -------------------------------------------------------------*/
00042 /* Private variables ---------------------------------------------------------*/
00043 #if defined USE_STM3210B_EVAL || defined USE_STM32100B_EVAL
00044 uint16_t BKPDataReg[BKP_DR_NUMBER] =
00045   {
00046     BKP_DR1, BKP_DR2, BKP_DR3, BKP_DR4, BKP_DR5, BKP_DR6, BKP_DR7, BKP_DR8,
00047     BKP_DR9, BKP_DR10
00048   };
00049 #else
00050 uint16_t BKPDataReg[BKP_DR_NUMBER] =
00051   {
00052     BKP_DR1, BKP_DR2, BKP_DR3, BKP_DR4, BKP_DR5, BKP_DR6, BKP_DR7, BKP_DR8,
00053     BKP_DR9, BKP_DR10, BKP_DR11, BKP_DR12, BKP_DR13, BKP_DR14, BKP_DR15, BKP_DR16,
00054     BKP_DR17, BKP_DR18, BKP_DR19, BKP_DR20, BKP_DR21, BKP_DR22, BKP_DR23, BKP_DR24,
00055     BKP_DR25, BKP_DR26, BKP_DR27, BKP_DR28, BKP_DR29, BKP_DR30, BKP_DR31, BKP_DR32,
00056     BKP_DR33, BKP_DR34, BKP_DR35, BKP_DR36, BKP_DR37, BKP_DR38, BKP_DR39, BKP_DR40,
00057     BKP_DR41, BKP_DR42
00058   };
00059 #endif /* USE_STM3210B_EVAL or USE_STM32100B_EVAL */
00060
00061 /* Private function prototypes -----------------------------------------------*/
00062 void GPIO_Configuration(void);
00063 void NVIC_Configuration(void);
00064 void WriteToBackupReg(uint16_t FirstBackupData);
00065 uint32_t CheckBackupReg(uint16_t FirstBackupData);
00066
00067 /* Private functions ---------------------------------------------------------*/
00068
00069 /**
00070   * @brief   Main program.
00071   * @param  None
00072   * @retval None
00073   */
00074 int main(void)
00075 {
00076   /*!< At this stage the microcontroller clock setting is already configured,
00077        this is done through SystemInit() function which is called from startup
00078        file (startup_stm32f10x_xx.s) before to branch to application main.
00079        To reconfigure the default setting of SystemInit() function, refer to
00080        system_stm32f10x.c file
00081      */
00082
00083   /* NVIC configuration */
00084   NVIC_Configuration();
00085
00086   /* Initialize Leds mounted on STM3210X-EVAL board */
00087   STM_EVAL_LEDInit(LED1);
00088   STM_EVAL_LEDInit(LED2);
00089   STM_EVAL_LEDInit(LED3);
00090   STM_EVAL_LEDInit(LED4);
00091
00092   /* Enable PWR and BKP clock */
00093   RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR | RCC_APB1Periph_BKP, ENABLE);
00094
00095   /* Enable write access to Backup domain */
00096   PWR_BackupAccessCmd(ENABLE);
00097
00098   /* Disable Tamper pin */
00099   BKP_TamperPinCmd(DISABLE);
00100
00101   /* Disable Tamper interrupt */
00102   BKP_ITConfig(DISABLE);
00103
00104   /* Tamper pin active on low level */
00105   BKP_TamperPinLevelConfig(BKP_TamperPinLevel_Low);
00106
00107   /* Clear Tamper pin Event(TE) pending flag */
00108   BKP_ClearFlag();
00109
00110   /* Enable Tamper interrupt */
00111   BKP_ITConfig(ENABLE);
00112
00113   /* Enable Tamper pin */
00114   BKP_TamperPinCmd(ENABLE);
00115
00116   /* Write data to Backup DRx registers */
00117   WriteToBackupReg(0xA53C);
00118
00119   /* Check if the written data are correct */
00120   if(CheckBackupReg(0xA53C) == 0x00)
00121   {
00122     /* Turn on LED1 */
00123     STM_EVAL_LEDOn(LED1);
00124   }
00125   else
00126   {
00127     /* Turn on LED2 */
00128     STM_EVAL_LEDOn(LED2);
00129   }
00130
00131   while (1)
00132   {
00133   }
00134 }
00135
00136 /**
00137   * @brief  Configures NVIC and Vector Table base location.
00138   * @param  None
00139   * @retval None
00140   */
00141 void NVIC_Configuration(void)
00142 {
00143   NVIC_InitTypeDef NVIC_InitStructure;
00144
00145   /* Enable TAMPER IRQChannel */
00146   NVIC_InitStructure.NVIC_IRQChannel = TAMPER_IRQn;
00147   NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
00148   NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
00149   NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
00150   NVIC_Init(&NVIC_InitStructure);
00151 }
00152
00153 /**
00154   * @brief  Writes data Backup DRx registers.
00155   * @param  FirstBackupData: data to be written to Backup data registers.
00156   * @retval None
00157   */
00158 void WriteToBackupReg(uint16_t FirstBackupData)
00159 {
00160   uint32_t index = 0;
00161
00162   for (index = 0; index < BKP_DR_NUMBER; index++)
00163   {
00164     BKP_WriteBackupRegister(BKPDataReg[index], FirstBackupData + (index * 0x5A));
00165   }
00166 }
00167
00168 /**
00169   * @brief  Checks if the Backup DRx registers values are correct or not.
00170   * @param  FirstBackupData: data to be compared with Backup data registers.
00171   * @retval
00172   *         - 0: All Backup DRx registers values are correct
00173   *         - Value different from 0: Number of the first Backup register
00174   *           which value is not correct
00175   */
00176 uint32_t CheckBackupReg(uint16_t FirstBackupData)
00177 {
00178   uint32_t index = 0;
00179
00180   for (index = 0; index < BKP_DR_NUMBER; index++)
00181   {
00182     if (BKP_ReadBackupRegister(BKPDataReg[index]) != (FirstBackupData + (index * 0x5A)))
00183     {
00184       return (index + 1);
00185     }
00186   }
00187
00188   return 0;
00189 }
00190
00191 /**
00192   * @brief  Checks if the Backup DRx registers are reset or not.
00193   * @param  None
00194   * @retval
00195   *          - 0: All Backup DRx registers are reset
00196   *          - Value different from 0: Number of the first Backup register
00197   *            not reset
00198   */
00199 uint32_t IsBackupRegReset(void)
00200 {
00201   uint32_t index = 0;
00202
00203   for (index = 0; index < BKP_DR_NUMBER; index++)
00204   {
00205     if (BKP_ReadBackupRegister(BKPDataReg[index]) != 0x0000)
00206     {
00207       return (index + 1);
00208     }
00209   }
00210
00211   return 0;
00212 }
00213
00214 #ifdef  USE_FULL_ASSERT
00215
00216 /**
00217   * @brief  Reports the name of the source file and the source line number
00218   *         where the assert_param error has occurred.
00219   * @param  file: pointer to the source file name
00220   * @param  line: assert_param error line source number
00221   * @retval None
00222   */
00223 void assert_failed(uint8_t* file, uint32_t line)
00224 {
00225   /* User can add his own implementation to report the file name and line number,
00226      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00227
00228   /* Infinite loop */
00229   while (1)
00230   {
00231   }
00232 }
00233
00234 #endif
00235
00236 /**
00237   * @}
00238   */
00239
00240 /**
00241   * @}
00242   */
00243
00244 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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  • BKP
  • Tamper

STM32F10x_StdPeriph_Examples/BKP/Tamper/stm32f10x_conf.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    BKP/Tamper/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052 /* Exported types ------------------------------------------------------------*/
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Uncomment the line below to expanse the "assert_param" macro in the
00055    Standard Peripheral Library drivers code */
00056 /* #define USE_FULL_ASSERT    1 */
00057
00058 /* Exported macro ------------------------------------------------------------*/
00059 #ifdef  USE_FULL_ASSERT
00060
00061 /**
00062   * @brief  The assert_param macro is used for function's parameters check.
00063   * @param  expr: If expr is false, it calls assert_failed function which reports
00064   *         the name of the source file and the source line number of the call
00065   *         that failed. If expr is true, it returns no value.
00066   * @retval None
00067   */
00068   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00069 /* Exported functions ------------------------------------------------------- */
00070   void assert_failed(uint8_t* file, uint32_t line);
00071 #else
00072   #define assert_param(expr) ((void)0)
00073 #endif /* USE_FULL_ASSERT */
00074
00075 #endif /* __STM32F10x_CONF_H */
00076
00077 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • BKP
  • Tamper

STM32F10x_StdPeriph_Examples/BKP/Tamper/stm32f10x_it.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    BKP/Tamper/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and peripherals
00009   *          interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026 #include "main.h"
00027
00028 /** @addtogroup STM32F10x_StdPeriph_Examples
00029   * @{
00030   */
00031
00032 /** @addtogroup BKP_Tamper
00033   * @{
00034   */
00035
00036 /* Private typedef -----------------------------------------------------------*/
00037 /* Private define ------------------------------------------------------------*/
00038 /* Private macro -------------------------------------------------------------*/
00039 /* Private variables ---------------------------------------------------------*/
00040 /* Private function prototypes -----------------------------------------------*/
00041 /* Private functions ---------------------------------------------------------*/
00042
00043 /******************************************************************************/
00044 /*            Cortex-M3 Processor Exceptions Handlers                         */
00045 /******************************************************************************/
00046
00047 /**
00048   * @brief  This function handles NMI exception.
00049   * @param  None
00050   * @retval None
00051   */
00052 void NMI_Handler(void)
00053 {
00054 }
00055
00056 /**
00057   * @brief  This function handles Hard Fault exception.
00058   * @param  None
00059   * @retval None
00060   */
00061 void HardFault_Handler(void)
00062 {
00063   /* Go to infinite loop when Hard Fault exception occurs */
00064   while (1)
00065   {
00066   }
00067 }
00068
00069 /**
00070   * @brief  This function handles Memory Manage exception.
00071   * @param  None
00072   * @retval None
00073   */
00074 void MemManage_Handler(void)
00075 {
00076   /* Go to infinite loop when Memory Manage exception occurs */
00077   while (1)
00078   {
00079   }
00080 }
00081
00082 /**
00083   * @brief  This function handles Bus Fault exception.
00084   * @param  None
00085   * @retval None
00086   */
00087 void BusFault_Handler(void)
00088 {
00089   /* Go to infinite loop when Bus Fault exception occurs */
00090   while (1)
00091   {
00092   }
00093 }
00094
00095 /**
00096   * @brief  This function handles Usage Fault exception.
00097   * @param  None
00098   * @retval None
00099   */
00100 void UsageFault_Handler(void)
00101 {
00102   /* Go to infinite loop when Usage Fault exception occurs */
00103   while (1)
00104   {
00105   }
00106 }
00107
00108 /**
00109   * @brief  This function handles SVCall exception.
00110   * @param  None
00111   * @retval None
00112   */
00113 void SVC_Handler(void)
00114 {
00115 }
00116
00117 /**
00118   * @brief  This function handles Debug Monitor exception.
00119   * @param  None
00120   * @retval None
00121   */
00122 void DebugMon_Handler(void)
00123 {
00124 }
00125
00126 /**
00127   * @brief  This function handles PendSV_Handler exception.
00128   * @param  None
00129   * @retval None
00130   */
00131 void PendSV_Handler(void)
00132 {
00133 }
00134
00135 /**
00136   * @brief  This function handles SysTick Handler.
00137   * @param  None
00138   * @retval None
00139   */
00140 void SysTick_Handler(void)
00141 {
00142 }
00143
00144 /******************************************************************************/
00145 /*            STM32F10x Peripherals Interrupt Handlers                        */
00146 /******************************************************************************/
00147
00148 /**
00149   * @brief  This function handles Tamper interrupt request.
00150   * @param  None
00151   * @retval None
00152   */
00153 void TAMPER_IRQHandler(void)
00154 {
00155   if(BKP_GetITStatus() != RESET)
00156   { /* Tamper detection event occurred */
00157
00158     /* Check if Backup registers are cleared */
00159     if(IsBackupRegReset() == 0)
00160     {/* OK, Backup registers are reset as expected */
00161
00162       /* Turn on LED3 */
00163       STM_EVAL_LEDOn(LED3);
00164     }
00165     else
00166     {/* Backup registers are not reset */
00167       /* Turn on LED4 */
00168       STM_EVAL_LEDOn(LED4);
00169     }
00170
00171     /* Clear Tamper pin interrupt pending bit */
00172     BKP_ClearITPendingBit();
00173
00174     /* Clear Tamper pin Event(TE) pending flag */
00175     BKP_ClearFlag();
00176
00177     /* Disable Tamper pin */
00178     BKP_TamperPinCmd(DISABLE);
00179
00180     /* Enable Tamper pin */
00181     BKP_TamperPinCmd(ENABLE);
00182
00183   }
00184 }
00185
00186 /******************************************************************************/
00187 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00188 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00189 /*  available peripheral interrupt handler's name please refer to the startup */
00190 /*  file (startup_stm32f10x_xx.s).                                            */
00191 /******************************************************************************/
00192
00193 /**
00194   * @brief  This function handles PPP interrupt request.
00195   * @param  None
00196   * @retval None
00197   */
00198 /*void PPP_IRQHandler(void)
00199 {
00200 }*/
00201
00202 /**
00203   * @}
00204   */
00205
00206 /**
00207   * @}
00208   */
00209
00210 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • BKP
  • Tamper

STM32F10x_StdPeriph_Examples/BKP/Tamper/stm32f10x_it.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    BKP/Tamper/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043 void TAMPER_IRQHandler(void);
00044
00045 #endif /* __STM32F10x_IT_H */
00046
00047 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • CAN
  • DualCAN

STM32F10x_StdPeriph_Examples/CAN/DualCAN/main.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    CAN/DualCAN/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32_eval.h"
00024 #include "stm3210c_eval_lcd.h"
00025
00026 /** @addtogroup STM32F10x_StdPeriph_Examples
00027   * @{
00028   */
00029
00030 /** @addtogroup CAN_DualCAN
00031   * @{
00032   */
00033
00034 /* Private typedef -----------------------------------------------------------*/
00035 /* Private define ------------------------------------------------------------*/
00036
00037 #define CAN_BAUDRATE  1000      /* 1MBps   */
00038 /* #define CAN_BAUDRATE  500*/  /* 500kBps */
00039 /* #define CAN_BAUDRATE  250*/  /* 250kBps */
00040 /* #define CAN_BAUDRATE  125*/  /* 125kBps */
00041 /* #define CAN_BAUDRATE  100*/  /* 100kBps */
00042 /* #define CAN_BAUDRATE  50*/   /* 50kBps  */
00043 /* #define CAN_BAUDRATE  20*/   /* 20kBps  */
00044 /* #define CAN_BAUDRATE  10*/   /* 10kBps  */
00045 /* Private macro -------------------------------------------------------------*/
00046 /* Private variables ---------------------------------------------------------*/
00047 CAN_InitTypeDef        CAN_InitStructure;
00048 CAN_FilterInitTypeDef  CAN_FilterInitStructure;
00049 CanTxMsg TxMessage;
00050
00051 /* Private function prototypes -----------------------------------------------*/
00052 void NVIC_Config(void);
00053 void CAN_Config(void);
00054 void LED_Display(uint8_t Ledstatus);
00055 void Init_RxMes(CanRxMsg *RxMessage);
00056 void Delay(void);
00057
00058 /* Private functions ---------------------------------------------------------*/
00059
00060 /**
00061   * @brief  Main program.
00062   * @param  None
00063   * @retval None
00064   */
00065 int main(void)
00066 {
00067   /*!< At this stage the microcontroller clock setting is already configured,
00068        this is done through SystemInit() function which is called from startup
00069        file (startup_stm32f10x_xx.s) before to branch to application main.
00070        To reconfigure the default setting of SystemInit() function, refer to
00071        system_stm32f10x.c file
00072      */
00073
00074   /* NVIC configuration */
00075   NVIC_Config();
00076
00077   /* Configures LED 1..4 */
00078   STM_EVAL_LEDInit(LED1);
00079   STM_EVAL_LEDInit(LED2);
00080   STM_EVAL_LEDInit(LED3);
00081   STM_EVAL_LEDInit(LED4);
00082
00083   /* LCD Initialization */
00084   STM3210C_LCD_Init();
00085   LCD_Clear(LCD_COLOR_WHITE);
00086
00087   /* Set the LCD Back Color */
00088   LCD_SetBackColor(LCD_COLOR_RED);
00089   /* Set the LCD Text Color */
00090   LCD_SetTextColor(LCD_COLOR_GREEN);
00091
00092   LCD_DisplayStringLine(LCD_LINE_0, "   STM3210C-EVAL    ");
00093   LCD_DisplayStringLine(LCD_LINE_1, " STM32F10x Dual CAN ");
00094   LCD_DisplayStringLine(LCD_LINE_2, "To start Press on:  ");
00095   LCD_DisplayStringLine(LCD_LINE_3, "Key or Tamper Button");
00096
00097   /* Set the LCD Back Color */
00098   LCD_SetBackColor(LCD_COLOR_BLUE);
00099
00100 #if CAN_BAUDRATE == 1000 /* 1MBps */
00101   LCD_DisplayStringLine(LCD_LINE_4, " BAUDRATE = 1MBps   ");
00102 #elif CAN_BAUDRATE == 500 /* 500KBps */
00103   LCD_DisplayStringLine(LCD_LINE_4, " BAUDRATE = 500kBps   ");
00104 #elif CAN_BAUDRATE == 250 /* 250KBps */
00105   LCD_DisplayStringLine(LCD_LINE_4, " BAUDRATE = 250kBps   ");
00106 #elif CAN_BAUDRATE == 125 /* 125KBps */
00107   LCD_DisplayStringLine(LCD_LINE_4, " BAUDRATE = 125kBps   ");
00108 #elif  CAN_BAUDRATE == 100 /* 100KBps */
00109   LCD_DisplayStringLine(LCD_LINE_4, " BAUDRATE = 100kBps   ");
00110 #elif  CAN_BAUDRATE == 50 /* 50KBps */
00111   LCD_DisplayStringLine(LCD_LINE_4, " BAUDRATE = 50kBps   ");
00112 #elif  CAN_BAUDRATE == 20 /* 20KBps */
00113   LCD_DisplayStringLine(LCD_LINE_4, " BAUDRATE = 20kBps   ");
00114 #elif  CAN_BAUDRATE == 10 /* 10KBps */
00115   LCD_DisplayStringLine(LCD_LINE_4, " BAUDRATE = 10kBps   ");
00116 #endif
00117   /* Set the LCD Text Color */
00118   LCD_SetTextColor(LCD_COLOR_WHITE);
00119
00120   /* Configure BUTTON_KEY */
00121   STM_EVAL_PBInit(BUTTON_KEY, BUTTON_MODE_GPIO);
00122
00123   /* Configure BUTTON_TAMPER */
00124   STM_EVAL_PBInit(BUTTON_TAMPER, BUTTON_MODE_GPIO);
00125
00126   /* CANs configuration */
00127   CAN_Config();
00128
00129   /* IT Configuration for CAN1 */
00130   CAN_ITConfig(CAN1, CAN_IT_FMP0, ENABLE);
00131
00132   /* IT Configuration for CAN2 */
00133   CAN_ITConfig(CAN2, CAN_IT_FMP0, ENABLE);
00134
00135   /* turn off all leds*/
00136   STM_EVAL_LEDOff(LED1);
00137   STM_EVAL_LEDOff(LED2);
00138   STM_EVAL_LEDOff(LED3);
00139   STM_EVAL_LEDOff(LED4);
00140
00141   /* Infinite loop */
00142   while(1)
00143   {
00144     if(STM_EVAL_PBGetState(BUTTON_KEY)== RESET)
00145     {
00146       /* Turn On LED1 */
00147       LED_Display(0x01);
00148       TxMessage.Data[0] = 0x55;
00149       CAN_Transmit(CAN1, &TxMessage);
00150
00151       /* Loop while KEY button is pressed */
00152       while(STM_EVAL_PBGetState(BUTTON_KEY)== RESET)
00153       {
00154       }
00155     }
00156     if(STM_EVAL_PBGetState(BUTTON_TAMPER)== RESET)
00157     {
00158       /* Turn On LED2 */
00159       LED_Display(0x2);
00160       TxMessage.Data[0] = 0xAA;
00161       CAN_Transmit(CAN2, &TxMessage);
00162
00163       /* Loop while TAMPER button is pressed */
00164       while(STM_EVAL_PBGetState(BUTTON_TAMPER)== RESET)
00165       {
00166       }
00167     }
00168   }
00169 }
00170
00171 /**
00172   * @brief  Configures CAN1 and CAN2.
00173   * @param  None
00174   * @retval None
00175   */
00176 void CAN_Config(void)
00177 {
00178   GPIO_InitTypeDef  GPIO_InitStructure;
00179
00180   /* Configure CAN1 and CAN2 IOs **********************************************/
00181   /* GPIOB, GPIOD and AFIO clocks enable */
00182   RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO | RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOB, ENABLE);
00183
00184   /* Configure CAN1 RX pin */
00185   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0;
00186   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
00187   GPIO_Init(GPIOD, &GPIO_InitStructure);
00188
00189   /* Configure CAN2 RX pin */
00190   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5;
00191   GPIO_Init(GPIOB, &GPIO_InitStructure);
00192
00193   /* Configure CAN1 TX pin */
00194   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1;
00195   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
00196   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00197   GPIO_Init(GPIOD, &GPIO_InitStructure);
00198
00199   /* Configure CAN2 TX pin */
00200   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
00201   GPIO_Init(GPIOB, &GPIO_InitStructure);
00202
00203   /* Remap CAN1 and CAN2 GPIOs */
00204   GPIO_PinRemapConfig(GPIO_Remap2_CAN1 , ENABLE);
00205   GPIO_PinRemapConfig(GPIO_Remap_CAN2, ENABLE);
00206
00207   /* Configure CAN1 and CAN2 **************************************************/
00208   /* CAN1 and CAN2 Periph clocks enable */
00209   RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN1 | RCC_APB1Periph_CAN2, ENABLE);
00210
00211    /* CAN1 and CAN2 register init */
00212   CAN_DeInit(CAN1);
00213   CAN_DeInit(CAN2);
00214
00215   /* Struct init*/
00216   CAN_StructInit(&CAN_InitStructure);
00217
00218   /* CAN1 and CAN2  cell init */
00219   CAN_InitStructure.CAN_TTCM = DISABLE;
00220   CAN_InitStructure.CAN_ABOM = DISABLE;
00221   CAN_InitStructure.CAN_AWUM = DISABLE;
00222   CAN_InitStructure.CAN_NART = DISABLE;
00223   CAN_InitStructure.CAN_RFLM = DISABLE;
00224   CAN_InitStructure.CAN_TXFP = ENABLE;
00225   CAN_InitStructure.CAN_Mode = CAN_Mode_Normal;
00226   CAN_InitStructure.CAN_SJW = CAN_SJW_1tq;
00227   CAN_InitStructure.CAN_BS1 = CAN_BS1_3tq;
00228   CAN_InitStructure.CAN_BS2 = CAN_BS2_2tq;
00229
00230 #if CAN_BAUDRATE == 1000 /* 1MBps */
00231   CAN_InitStructure.CAN_Prescaler =6;
00232 #elif CAN_BAUDRATE == 500 /* 500KBps */
00233   CAN_InitStructure.CAN_Prescaler =12;
00234 #elif CAN_BAUDRATE == 250 /* 250KBps */
00235   CAN_InitStructure.CAN_Prescaler =24;
00236 #elif CAN_BAUDRATE == 125 /* 125KBps */
00237   CAN_InitStructure.CAN_Prescaler =48;
00238 #elif  CAN_BAUDRATE == 100 /* 100KBps */
00239   CAN_InitStructure.CAN_Prescaler =60;
00240 #elif  CAN_BAUDRATE == 50 /* 50KBps */
00241   CAN_InitStructure.CAN_Prescaler =120;
00242 #elif  CAN_BAUDRATE == 20 /* 20KBps */
00243   CAN_InitStructure.CAN_Prescaler =300;
00244 #elif  CAN_BAUDRATE == 10 /* 10KBps */
00245   CAN_InitStructure.CAN_Prescaler =600;
00246 #else
00247    #error "Please select first the CAN Baudrate in Private defines in main.c "
00248 #endif  /* CAN_BAUDRATE == 1000 */
00249
00250
00251   /*Initializes the CAN1  and CAN2 */
00252   CAN_Init(CAN1, &CAN_InitStructure);
00253   CAN_Init(CAN2, &CAN_InitStructure);
00254
00255   /* CAN1 filter init */
00256   CAN_FilterInitStructure.CAN_FilterNumber = 1;
00257   CAN_FilterInitStructure.CAN_FilterMode = CAN_FilterMode_IdMask;
00258   CAN_FilterInitStructure.CAN_FilterScale = CAN_FilterScale_32bit;
00259   CAN_FilterInitStructure.CAN_FilterIdHigh = 0x6420;
00260   CAN_FilterInitStructure.CAN_FilterIdLow = 0x0000;
00261   CAN_FilterInitStructure.CAN_FilterMaskIdHigh = 0x0000;
00262   CAN_FilterInitStructure.CAN_FilterMaskIdLow = 0x0000;
00263   CAN_FilterInitStructure.CAN_FilterFIFOAssignment = 0;
00264   CAN_FilterInitStructure.CAN_FilterActivation = ENABLE;
00265   CAN_FilterInit(&CAN_FilterInitStructure);
00266
00267   /* CAN2 filter init */
00268   CAN_FilterInitStructure.CAN_FilterIdHigh =0x2460;
00269   CAN_FilterInitStructure.CAN_FilterNumber = 15;
00270   CAN_FilterInit(&CAN_FilterInitStructure);
00271
00272   /* Transmit */
00273   TxMessage.StdId = 0x321;
00274   TxMessage.ExtId = 0x01;
00275   TxMessage.RTR = CAN_RTR_DATA;
00276   TxMessage.IDE = CAN_ID_STD;
00277   TxMessage.DLC = 1;
00278 }
00279
00280 /**
00281   * @brief  Initializes a Rx Message.
00282   * @param  CanRxMsg *RxMessage.
00283   * @retval None
00284   */
00285 void Init_RxMes(CanRxMsg *RxMessage)
00286 {
00287   uint8_t i = 0;
00288
00289   RxMessage->StdId = 0;
00290   RxMessage->ExtId = 0;
00291   RxMessage->IDE = CAN_ID_STD;
00292   RxMessage->DLC = 0;
00293   RxMessage->FMI = 0;
00294   for (i = 0; i < 8; i++)
00295   {
00296     RxMessage->Data[i] = 0;
00297   }
00298 }
00299
00300 /**
00301   * @brief  Configures the NVIC for CAN.
00302   * @param  None
00303   * @retval None
00304   */
00305 void NVIC_Config(void)
00306 {
00307   NVIC_InitTypeDef  NVIC_InitStructure;
00308
00309   NVIC_PriorityGroupConfig(NVIC_PriorityGroup_1);
00310
00311   NVIC_InitStructure.NVIC_IRQChannel = CAN1_RX0_IRQn;
00312   NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x0;
00313   NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x0;
00314   NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
00315   NVIC_Init(&NVIC_InitStructure);
00316
00317   NVIC_InitStructure.NVIC_IRQChannel = CAN2_RX0_IRQn;
00318   NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x1;
00319   NVIC_Init(&NVIC_InitStructure);
00320 }
00321
00322 /**
00323   * @brief  Turn ON/OFF the dedicate led.
00324   * @param  Ledstatus: Communication status.
00325   * @retval None
00326   */
00327 void LED_Display(uint8_t Ledstatus)
00328 {
00329
00330
00331   switch(Ledstatus)
00332   {
00333     case(1):
00334       STM_EVAL_LEDOn(LED1);
00335       LCD_DisplayStringLine(LCD_LINE_5, "CAN1 send Frame     ");
00336       LCD_DisplayStringLine(LCD_LINE_6, "                    ");
00337       break;
00338
00339     case(2):
00340       STM_EVAL_LEDOn(LED2);
00341       LCD_DisplayStringLine(LCD_LINE_5, "                    ");
00342       LCD_DisplayStringLine(LCD_LINE_6, "CAN2 send Frame     ");
00343       break;
00344
00345     case(3):
00346       STM_EVAL_LEDOff(LED1);
00347       STM_EVAL_LEDOn(LED3);
00348       LCD_DisplayStringLine(LCD_LINE_5, "CAN1 receive Passed ");
00349       break;
00350
00351     case(4):
00352       STM_EVAL_LEDOff(LED2);
00353       STM_EVAL_LEDOn(LED4);
00354       LCD_DisplayStringLine(LCD_LINE_6, "CAN2 receive Passed ");
00355       break;
00356
00357     case(5):
00358       STM_EVAL_LEDOff(LED1);
00359       STM_EVAL_LEDOff(LED3);
00360       LCD_DisplayStringLine(LCD_LINE_7, "Communication Failed ");
00361       break;
00362
00363     case(6):
00364       STM_EVAL_LEDOff(LED2);
00365       STM_EVAL_LEDOff(LED4);
00366       LCD_DisplayStringLine(LCD_LINE_7, "Communication Failed ");
00367       break;
00368
00369     default:
00370       break;
00371   }
00372 }
00373
00374 /**
00375   * @brief  Delay
00376   * @param  None
00377   * @retval None
00378   */
00379 void Delay(void)
00380 {
00381   uint16_t nTime = 0x0000;
00382
00383   for(nTime = 0; nTime <0xFFF; nTime++)
00384   {
00385   }
00386 }
00387
00388 #ifdef  USE_FULL_ASSERT
00389
00390 /**
00391   * @brief  Reports the name of the source file and the source line number
00392   *         where the assert_param error has occurred.
00393   * @param  file: pointer to the source file name
00394   * @param  line: assert_param error line source number
00395   * @retval None
00396   */
00397 void assert_failed(uint8_t* file, uint32_t line)
00398 {
00399   /* User can add his own implementation to report the file name and line number,
00400      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00401
00402   /* Infinite loop */
00403   while (1)
00404   {
00405   }
00406 }
00407
00408 #endif
00409
00410 /**
00411   * @}
00412   */
00413
00414 /**
00415   * @}
00416   */
00417
00418 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_conf.h

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00001 /**
00002   ******************************************************************************
00003   * @file    CAN/DualCAN/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052 /* Exported types ------------------------------------------------------------*/
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Uncomment the line below to expanse the "assert_param" macro in the
00055    Standard Peripheral Library drivers code */
00056 /* #define USE_FULL_ASSERT    1 */
00057
00058 /* Exported macro ------------------------------------------------------------*/
00059 #ifdef  USE_FULL_ASSERT
00060
00061 /**
00062   * @brief  The assert_param macro is used for function's parameters check.
00063   * @param  expr: If expr is false, it calls assert_failed function which reports
00064   *         the name of the source file and the source line number of the call
00065   *         that failed. If expr is true, it returns no value.
00066   * @retval None
00067   */
00068   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00069 /* Exported functions ------------------------------------------------------- */
00070   void assert_failed(uint8_t* file, uint32_t line);
00071 #else
00072   #define assert_param(expr) ((void)0)
00073 #endif /* USE_FULL_ASSERT */
00074
00075 #endif /* __STM32F10x_CONF_H */
00076
00077 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_it.c

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00001 /**
00002   ******************************************************************************
00003   * @file    CAN/DualCAN/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and
00009   *          peripherals interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026
00027 /** @addtogroup STM32F10x_StdPeriph_Examples
00028   * @{
00029   */
00030
00031 /** @addtogroup CAN_DualCAN
00032   * @{
00033   */
00034
00035 /* Private typedef -----------------------------------------------------------*/
00036 /* Private define ------------------------------------------------------------*/
00037 /* Private macro -------------------------------------------------------------*/
00038 /* Private variables ---------------------------------------------------------*/
00039 CanRxMsg RxMessage;
00040 extern void LED_Display(uint8_t Ledstatus);
00041
00042 /* Private function prototypes -----------------------------------------------*/
00043 /* Private functions ---------------------------------------------------------*/
00044
00045 /******************************************************************************/
00046 /*            Cortex-M3 Processor Exceptions Handlers                         */
00047 /******************************************************************************/
00048
00049 /**
00050   * @brief   This function handles NMI exception.
00051   * @param  None
00052   * @retval None
00053   */
00054 void NMI_Handler(void)
00055 {
00056 }
00057
00058 /**
00059   * @brief  This function handles Hard Fault exception.
00060   * @param  None
00061   * @retval None
00062   */
00063 void HardFault_Handler(void)
00064 {
00065   /* Go to infinite loop when Hard Fault exception occurs */
00066   while (1)
00067   {
00068   }
00069 }
00070
00071 /**
00072   * @brief  This function handles Memory Manage exception.
00073   * @param  None
00074   * @retval None
00075   */
00076 void MemManage_Handler(void)
00077 {
00078   /* Go to infinite loop when Memory Manage exception occurs */
00079   while (1)
00080   {
00081   }
00082 }
00083
00084 /**
00085   * @brief  This function handles Bus Fault exception.
00086   * @param  None
00087   * @retval None
00088   */
00089 void BusFault_Handler(void)
00090 {
00091   /* Go to infinite loop when Bus Fault exception occurs */
00092   while (1)
00093   {
00094   }
00095 }
00096
00097 /**
00098   * @brief  This function handles Usage Fault exception.
00099   * @param  None
00100   * @retval None
00101   */
00102 void UsageFault_Handler(void)
00103 {
00104   /* Go to infinite loop when Usage Fault exception occurs */
00105   while (1)
00106   {
00107   }
00108 }
00109
00110 /**
00111   * @brief  This function handles SVCall exception.
00112   * @param  None
00113   * @retval None
00114   */
00115 void SVC_Handler(void)
00116 {
00117 }
00118
00119 /**
00120   * @brief  This function handles Debug Monitor exception.
00121   * @param  None
00122   * @retval None
00123   */
00124 void DebugMon_Handler(void)
00125 {
00126 }
00127
00128 /**
00129   * @brief  This function handles PendSVC exception.
00130   * @param  None
00131   * @retval None
00132   */
00133 void PendSV_Handler(void)
00134 {
00135 }
00136
00137 /**
00138   * @brief  This function handles SysTick Handler.
00139   * @param  None
00140   * @retval None
00141   */
00142 void SysTick_Handler(void)
00143 {
00144 }
00145
00146 /******************************************************************************/
00147 /*            STM32F10x Peripherals Interrupt Handlers                        */
00148 /******************************************************************************/
00149
00150
00151 /**
00152   * @brief  This function handles CAN1 RX0 Handler.
00153   * @param  None
00154   * @retval None
00155   */
00156 void CAN1_RX0_IRQHandler(void)
00157 {
00158   CAN_Receive(CAN1, CAN_FIFO0, &RxMessage);
00159
00160   if ((RxMessage.StdId == 0x321)&&(RxMessage.IDE == CAN_ID_STD)&&(RxMessage.DLC == 1)&&(RxMessage.Data[0] == 0xAA))
00161   {
00162     /* Turn On LED3 */
00163     LED_Display(0x03); /* OK */
00164   }
00165   else
00166   {
00167     /* Turn Off LED3 */
00168     LED_Display(0x05); /* Error */
00169   }
00170 }
00171
00172 /**
00173   * @brief  This function handles CAN2 RX0 Handler.
00174   * @param  None
00175   * @retval None
00176   */
00177
00178 void CAN2_RX0_IRQHandler(void)
00179 {
00180   CAN_Receive(CAN2, CAN_FIFO0, &RxMessage);
00181
00182   if ((RxMessage.StdId == 0x321)&&(RxMessage.IDE == CAN_ID_STD)&&(RxMessage.DLC == 1)&&(RxMessage.Data[0] == 0x55))
00183   {
00184     /* Turn On LED4 */
00185     LED_Display(0x04); /* OK */
00186   }
00187   else
00188   {
00189     /* Turn Off LED4 */
00190     LED_Display(0x06); /* Error */
00191   }
00192 }
00193
00194 /******************************************************************************/
00195 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00196 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00197 /*  available peripheral interrupt handler's name please refer to the startup */
00198 /*  file (startup_stm32f10x_xx.s).                                            */
00199 /******************************************************************************/
00200
00201 /**
00202   * @brief  This function handles PPP interrupt request.
00203   * @param  None
00204   * @retval None
00205   */
00206 /*void PPP_IRQHandler(void)
00207 {
00208 }*/
00209
00210 /**
00211   * @}
00212   */
00213
00214 /**
00215   * @}
00216   */
00217
00218
00219 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_it.h

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00001 /**
00002   ******************************************************************************
00003   * @file    CAN/DualCAN/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043 void CAN1_RX0_IRQHandler(void);
00044 void CAN2_RX0_IRQHandler(void);
00045
00046 #endif /* __STM32F10x_IT_H */
00047
00048 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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  • LoopBack

STM32F10x_StdPeriph_Examples/CAN/LoopBack/main.c

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00001 /**
00002   ******************************************************************************
00003   * @file    CAN/LoopBack/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x.h"
00024 #include "stm32_eval.h"
00025
00026 /** @addtogroup STM32F10x_StdPeriph_Examples
00027   * @{
00028   */
00029
00030 /** @addtogroup CAN_LoopBack
00031   * @{
00032   */
00033
00034
00035
00036 /* Private define ------------------------------------------------------------*/
00037 #define __CAN1_USED__
00038 /* #define __CAN2_USED__*/   /* Please check that you device is
00039                                 Connectivity line when using CAN2 */
00040
00041 #ifdef  __CAN1_USED__
00042   #define CANx CAN1
00043 #else /*__CAN2_USED__*/
00044   #define CANx CAN2
00045 #endif  /* __CAN1_USED__ */
00046
00047 /* Private typedef -----------------------------------------------------------*/
00048 typedef enum {FAILED = 0, PASSED = !FAILED} TestStatus;
00049 /* Private macro -------------------------------------------------------------*/
00050 /* Private variables ---------------------------------------------------------*/
00051 __IO uint32_t ret = 0; /* for return of the interrupt handling */
00052 volatile TestStatus TestRx;
00053
00054 /* Private function prototypes -----------------------------------------------*/
00055 void NVIC_Configuration(void);
00056 TestStatus CAN_Polling(void);
00057 TestStatus CAN_Interrupt(void);
00058
00059 /* Private functions ---------------------------------------------------------*/
00060
00061 /**
00062   * @brief  Main program.
00063   * @param  None
00064   * @retval None
00065   */
00066 int main(void)
00067 {
00068   /*!< At this stage the microcontroller clock setting is already configured,
00069        this is done through SystemInit() function which is called from startup
00070        file (startup_stm32f10x_xx.s) before to branch to application main.
00071        To reconfigure the default setting of SystemInit() function, refer to
00072        system_stm32f10x.c file
00073      */
00074
00075
00076
00077 #ifdef  __CAN1_USED__
00078   /* CANx Periph clock enable */
00079   RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN1, ENABLE);
00080 #else /*__CAN2_USED__*/
00081   /* CAN1 & 2  Periph clock enable */
00082   RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN1, ENABLE);
00083   RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN2, ENABLE);
00084 #endif  /* __CAN1_USED__ */
00085
00086   /* NVIC Configuration */
00087   NVIC_Configuration();
00088
00089   /* Configures LED 1..4 */
00090   STM_EVAL_LEDInit(LED1);
00091   STM_EVAL_LEDInit(LED2);
00092   STM_EVAL_LEDInit(LED3);
00093   STM_EVAL_LEDInit(LED4);
00094
00095   /* Turns selected LED Off */
00096   STM_EVAL_LEDOff(LED1);
00097   STM_EVAL_LEDOff(LED2);
00098   STM_EVAL_LEDOff(LED3);
00099   STM_EVAL_LEDOff(LED4);
00100
00101   /* CAN transmit at 125Kb/s and receive by polling in loopback mode */
00102   TestRx = CAN_Polling();
00103
00104   if (TestRx == FAILED)
00105   {
00106     /* Turn on led LD3 */
00107     STM_EVAL_LEDOn(LED3);
00108   }
00109   else
00110   {
00111     /* Turn on led LD1 */
00112     STM_EVAL_LEDOn(LED1);
00113   }
00114
00115   /* CAN transmit at 500Kb/s and receive by interrupt in loopback mode */
00116   TestRx = CAN_Interrupt();
00117
00118   if (TestRx == FAILED)
00119   {
00120     /* Turn on led LD4 */
00121     STM_EVAL_LEDOn(LED4);
00122   }
00123   else
00124   {
00125     /* Turn on led LD2 */
00126     STM_EVAL_LEDOn(LED2);
00127   }
00128
00129   /* Infinite loop */
00130   while (1)
00131   {
00132   }
00133 }
00134
00135 /**
00136   * @brief  Configures the CAN, transmit and receive by polling
00137   * @param  None
00138   * @retval PASSED if the reception is well done, FAILED in other case
00139   */
00140 TestStatus CAN_Polling(void)
00141 {
00142   CAN_InitTypeDef        CAN_InitStructure;
00143   CAN_FilterInitTypeDef  CAN_FilterInitStructure;
00144   CanTxMsg TxMessage;
00145   CanRxMsg RxMessage;
00146   uint32_t i = 0;
00147   uint8_t TransmitMailbox = 0;
00148
00149   /* CAN register init */
00150   CAN_DeInit(CANx);
00151
00152   CAN_StructInit(&CAN_InitStructure);
00153
00154   /* CAN cell init */
00155   CAN_InitStructure.CAN_TTCM=DISABLE;
00156   CAN_InitStructure.CAN_ABOM=DISABLE;
00157   CAN_InitStructure.CAN_AWUM=DISABLE;
00158   CAN_InitStructure.CAN_NART=DISABLE;
00159   CAN_InitStructure.CAN_RFLM=DISABLE;
00160   CAN_InitStructure.CAN_TXFP=DISABLE;
00161   CAN_InitStructure.CAN_Mode=CAN_Mode_LoopBack;
00162
00163   /* Baudrate = 125kbps*/
00164   CAN_InitStructure.CAN_SJW=CAN_SJW_1tq;
00165   CAN_InitStructure.CAN_BS1=CAN_BS1_2tq;
00166   CAN_InitStructure.CAN_BS2=CAN_BS2_3tq;
00167   CAN_InitStructure.CAN_Prescaler=48;
00168   CAN_Init(CANx, &CAN_InitStructure);
00169
00170   /* CAN filter init */
00171 #ifdef  __CAN1_USED__
00172   CAN_FilterInitStructure.CAN_FilterNumber=0;
00173 #else /*__CAN2_USED__*/
00174   CAN_FilterInitStructure.CAN_FilterNumber=14;
00175 #endif  /* __CAN1_USED__ */
00176   CAN_FilterInitStructure.CAN_FilterMode=CAN_FilterMode_IdMask;
00177   CAN_FilterInitStructure.CAN_FilterScale=CAN_FilterScale_32bit;
00178   CAN_FilterInitStructure.CAN_FilterIdHigh=0x0000;
00179   CAN_FilterInitStructure.CAN_FilterIdLow=0x0000;
00180   CAN_FilterInitStructure.CAN_FilterMaskIdHigh=0x0000;
00181   CAN_FilterInitStructure.CAN_FilterMaskIdLow=0x0000;
00182   CAN_FilterInitStructure.CAN_FilterFIFOAssignment=0;
00183
00184
00185   CAN_FilterInitStructure.CAN_FilterActivation=ENABLE;
00186   CAN_FilterInit(&CAN_FilterInitStructure);
00187
00188   /* transmit */
00189   TxMessage.StdId=0x11;
00190   TxMessage.RTR=CAN_RTR_DATA;
00191   TxMessage.IDE=CAN_ID_STD;
00192   TxMessage.DLC=2;
00193   TxMessage.Data[0]=0xCA;
00194   TxMessage.Data[1]=0xFE;
00195
00196   TransmitMailbox=CAN_Transmit(CANx, &TxMessage);
00197   i = 0;
00198   while((CAN_TransmitStatus(CANx, TransmitMailbox) != CANTXOK) && (i != 0xFFFF))
00199   {
00200     i++;
00201   }
00202
00203   i = 0;
00204   while((CAN_MessagePending(CANx, CAN_FIFO0) < 1) && (i != 0xFFFF))
00205   {
00206     i++;
00207   }
00208
00209   /* receive */
00210   RxMessage.StdId=0x00;
00211   RxMessage.IDE=CAN_ID_STD;
00212   RxMessage.DLC=0;
00213   RxMessage.Data[0]=0x00;
00214   RxMessage.Data[1]=0x00;
00215   CAN_Receive(CANx, CAN_FIFO0, &RxMessage);
00216
00217   if (RxMessage.StdId!=0x11)
00218   {
00219     return FAILED;
00220   }
00221
00222   if (RxMessage.IDE!=CAN_ID_STD)
00223   {
00224     return FAILED;
00225   }
00226
00227   if (RxMessage.DLC!=2)
00228   {
00229     return FAILED;
00230   }
00231
00232   if ((RxMessage.Data[0]<<8|RxMessage.Data[1])!=0xCAFE)
00233   {
00234     return FAILED;
00235   }
00236
00237   return PASSED; /* Test Passed */
00238 }
00239
00240 /**
00241   * @brief  Configures the CAN, transmit and receive using interrupt.
00242   * @param  None
00243   * @retval PASSED if the reception is well done, FAILED in other case
00244   */
00245 TestStatus CAN_Interrupt(void)
00246 {
00247   CAN_InitTypeDef        CAN_InitStructure;
00248   CAN_FilterInitTypeDef  CAN_FilterInitStructure;
00249   CanTxMsg TxMessage;
00250   uint32_t i = 0;
00251
00252   /* CAN register init */
00253   CAN_DeInit(CANx);
00254
00255
00256   CAN_StructInit(&CAN_InitStructure);
00257
00258   /* CAN cell init */
00259   CAN_InitStructure.CAN_TTCM=DISABLE;
00260   CAN_InitStructure.CAN_ABOM=DISABLE;
00261   CAN_InitStructure.CAN_AWUM=DISABLE;
00262   CAN_InitStructure.CAN_NART=DISABLE;
00263   CAN_InitStructure.CAN_RFLM=DISABLE;
00264   CAN_InitStructure.CAN_TXFP=DISABLE;
00265   CAN_InitStructure.CAN_Mode=CAN_Mode_LoopBack;
00266   CAN_InitStructure.CAN_SJW=CAN_SJW_1tq;
00267
00268   /* Baudrate = 500 Kbps */
00269   CAN_InitStructure.CAN_BS1=CAN_BS1_2tq;
00270   CAN_InitStructure.CAN_BS2=CAN_BS2_3tq;
00271   CAN_InitStructure.CAN_Prescaler=12;
00272   CAN_Init(CANx, &CAN_InitStructure);
00273
00274   /* CAN filter init */
00275 #ifdef  __CAN1_USED__
00276   CAN_FilterInitStructure.CAN_FilterNumber=1;
00277 #else /*__CAN2_USED__*/
00278   CAN_FilterInitStructure.CAN_FilterNumber=15;
00279 #endif  /* __CAN1_USED__ */
00280   CAN_FilterInitStructure.CAN_FilterMode=CAN_FilterMode_IdMask;
00281   CAN_FilterInitStructure.CAN_FilterScale=CAN_FilterScale_32bit;
00282   CAN_FilterInitStructure.CAN_FilterIdHigh=0x0000;
00283   CAN_FilterInitStructure.CAN_FilterIdLow=0x0000;
00284   CAN_FilterInitStructure.CAN_FilterMaskIdHigh=0x0000;
00285   CAN_FilterInitStructure.CAN_FilterMaskIdLow=0x0000;
00286   CAN_FilterInitStructure.CAN_FilterFIFOAssignment=CAN_FIFO0;
00287   CAN_FilterInitStructure.CAN_FilterActivation=ENABLE;
00288   CAN_FilterInit(&CAN_FilterInitStructure);
00289
00290   /* CAN FIFO0 message pending interrupt enable */
00291   CAN_ITConfig(CANx, CAN_IT_FMP0, ENABLE);
00292
00293   /* transmit 1 message */
00294   TxMessage.StdId=0;
00295   TxMessage.ExtId=0x1234;
00296   TxMessage.IDE=CAN_ID_EXT;
00297   TxMessage.RTR=CAN_RTR_DATA;
00298   TxMessage.DLC=2;
00299   TxMessage.Data[0]=0xDE;
00300   TxMessage.Data[1]=0xCA;
00301   CAN_Transmit(CANx, &TxMessage);
00302
00303   /* initialize the value that will be returned */
00304   ret = 0xFF;
00305
00306   /* receive message with interrupt handling */
00307   i=0;
00308   while((ret == 0xFF) && (i < 0xFFF))
00309   {
00310     i++;
00311   }
00312
00313   if (i == 0xFFF)
00314   {
00315     ret=0;
00316   }
00317
00318   /* disable interrupt handling */
00319   CAN_ITConfig(CANx, CAN_IT_FMP0, DISABLE);
00320
00321   return (TestStatus)ret;
00322 }
00323
00324 /**
00325   * @brief  Configures the NVIC and Vector Table base address.
00326   * @param  None
00327   * @retval None
00328   */
00329 void NVIC_Configuration(void)
00330 {
00331   NVIC_InitTypeDef NVIC_InitStructure;
00332
00333   /* Enable CANx RX0 interrupt IRQ channel */
00334 #ifndef STM32F10X_CL
00335
00336 #ifdef  __CAN1_USED__
00337   NVIC_InitStructure.NVIC_IRQChannel = USB_LP_CAN1_RX0_IRQn;
00338 #else  /*__CAN2_USED__*/
00339   /* CAN2 is not implemented in the device */
00340    #error "CAN2 is implemented only in Connectivity line devices"
00341
00342 #endif /*__CAN1_USED__*/
00343 #else
00344 #ifdef  __CAN1_USED__
00345   NVIC_InitStructure.NVIC_IRQChannel = CAN1_RX0_IRQn;
00346 #else  /*__CAN2_USED__*/
00347   NVIC_InitStructure.NVIC_IRQChannel = CAN2_RX0_IRQn;
00348 #endif /*__CAN1_USED__*/
00349
00350 #endif /* STM32F10X_CL*/
00351   NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
00352   NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
00353   NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
00354   NVIC_Init(&NVIC_InitStructure);
00355 }
00356
00357
00358 #ifdef  USE_FULL_ASSERT
00359
00360 /**
00361   * @brief  Reports the name of the source file and the source line number
00362   *         where the assert_param error has occurred.
00363   * @param  file: pointer to the source file name
00364   * @param  line: assert_param error line source number
00365   * @retval None
00366   */
00367 void assert_failed(uint8_t* file, uint32_t line)
00368 {
00369   /* User can add his own implementation to report the file name and line number,
00370      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00371
00372   /* Infinite loop */
00373   while (1)
00374   {
00375   }
00376 }
00377
00378 #endif
00379
00380 /**
00381   * @}
00382   */
00383
00384 /**
00385   * @}
00386   */
00387
00388 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_conf.h

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00001 /**
00002   ******************************************************************************
00003   * @file    CAN/LoopBack/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052 /* Exported types ------------------------------------------------------------*/
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Uncomment the line below to expanse the "assert_param" macro in the
00055    Standard Peripheral Library drivers code */
00056 /* #define USE_FULL_ASSERT    1 */
00057
00058 /* Exported macro ------------------------------------------------------------*/
00059 #ifdef  USE_FULL_ASSERT
00060
00061 /**
00062   * @brief  The assert_param macro is used for function's parameters check.
00063   * @param  expr: If expr is false, it calls assert_failed function which reports
00064   *         the name of the source file and the source line number of the call
00065   *         that failed. If expr is true, it returns no value.
00066   * @retval None
00067   */
00068   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00069 /* Exported functions ------------------------------------------------------- */
00070   void assert_failed(uint8_t* file, uint32_t line);
00071 #else
00072   #define assert_param(expr) ((void)0)
00073 #endif /* USE_FULL_ASSERT */
00074
00075 #endif /* __STM32F10x_CONF_H */
00076
00077 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_it.c

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00001 /**
00002   ******************************************************************************
00003   * @file    CAN/LoopBack/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and
00009   *          peripherals interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026
00027 /** @addtogroup STM32F10x_StdPeriph_Examples
00028   * @{
00029   */
00030
00031 /** @addtogroup CAN_LoopBack
00032   * @{
00033   */
00034
00035 /* Private typedef -----------------------------------------------------------*/
00036 /* Private define ------------------------------------------------------------*/
00037 /* Private macro -------------------------------------------------------------*/
00038 /* Private variables ---------------------------------------------------------*/
00039 extern __IO uint32_t ret;
00040
00041 /* Private function prototypes -----------------------------------------------*/
00042 /* Private functions ---------------------------------------------------------*/
00043
00044 /******************************************************************************/
00045 /*            Cortex-M3 Processor Exceptions Handlers                         */
00046 /******************************************************************************/
00047
00048 /**
00049   * @brief   This function handles NMI exception.
00050   * @param  None
00051   * @retval None
00052   */
00053 void NMI_Handler(void)
00054 {
00055 }
00056
00057 /**
00058   * @brief  This function handles Hard Fault exception.
00059   * @param  None
00060   * @retval None
00061   */
00062 void HardFault_Handler(void)
00063 {
00064   /* Go to infinite loop when Hard Fault exception occurs */
00065   while (1)
00066   {
00067   }
00068 }
00069
00070 /**
00071   * @brief  This function handles Memory Manage exception.
00072   * @param  None
00073   * @retval None
00074   */
00075 void MemManage_Handler(void)
00076 {
00077   /* Go to infinite loop when Memory Manage exception occurs */
00078   while (1)
00079   {
00080   }
00081 }
00082
00083 /**
00084   * @brief  This function handles Bus Fault exception.
00085   * @param  None
00086   * @retval None
00087   */
00088 void BusFault_Handler(void)
00089 {
00090   /* Go to infinite loop when Bus Fault exception occurs */
00091   while (1)
00092   {
00093   }
00094 }
00095
00096 /**
00097   * @brief  This function handles Usage Fault exception.
00098   * @param  None
00099   * @retval None
00100   */
00101 void UsageFault_Handler(void)
00102 {
00103   /* Go to infinite loop when Usage Fault exception occurs */
00104   while (1)
00105   {
00106   }
00107 }
00108
00109 /**
00110   * @brief  This function handles SVCall exception.
00111   * @param  None
00112   * @retval None
00113   */
00114 void SVC_Handler(void)
00115 {
00116 }
00117
00118 /**
00119   * @brief  This function handles Debug Monitor exception.
00120   * @param  None
00121   * @retval None
00122   */
00123 void DebugMon_Handler(void)
00124 {
00125 }
00126
00127 /**
00128   * @brief  This function handles PendSVC exception.
00129   * @param  None
00130   * @retval None
00131   */
00132 void PendSV_Handler(void)
00133 {
00134 }
00135
00136 /**
00137   * @brief  This function handles SysTick Handler.
00138   * @param  None
00139   * @retval None
00140   */
00141 void SysTick_Handler(void)
00142 {
00143 }
00144
00145 /******************************************************************************/
00146 /*            STM32F10x Peripherals Interrupt Handlers                        */
00147 /******************************************************************************/
00148
00149 /**
00150   * @brief  This function handles CAN1 Handler.
00151   * @param  None
00152   * @retval None
00153   */
00154 #ifndef STM32F10X_CL
00155 void USB_LP_CAN1_RX0_IRQHandler(void)
00156 #else
00157 void CAN1_RX0_IRQHandler(void)
00158 #endif
00159 {
00160   CanRxMsg RxMessage;
00161
00162   RxMessage.StdId=0x00;
00163   RxMessage.ExtId=0x00;
00164   RxMessage.IDE=0;
00165   RxMessage.DLC=0;
00166   RxMessage.FMI=0;
00167   RxMessage.Data[0]=0x00;
00168   RxMessage.Data[1]=0x00;
00169
00170   CAN_Receive(CAN1, CAN_FIFO0, &RxMessage);
00171
00172   if((RxMessage.ExtId==0x1234) && (RxMessage.IDE==CAN_ID_EXT)
00173      && (RxMessage.DLC==2) && ((RxMessage.Data[1]|RxMessage.Data[0]<<8)==0xDECA))
00174   {
00175     ret = 1;
00176   }
00177   else
00178   {
00179     ret = 0;
00180   }
00181 }
00182
00183 /**
00184   * @brief  This function handles CAN2 Handler.
00185   * @param  None
00186   * @retval None
00187   */
00188 #ifdef STM32F10X_CL
00189 void CAN2_RX0_IRQHandler(void)
00190
00191 {
00192   CanRxMsg RxMessage;
00193
00194   RxMessage.StdId=0x00;
00195   RxMessage.ExtId=0x00;
00196   RxMessage.IDE=0;
00197   RxMessage.DLC=0;
00198   RxMessage.FMI=0;
00199   RxMessage.Data[0]=0x00;
00200   RxMessage.Data[1]=0x00;
00201
00202   CAN_Receive(CAN2, CAN_FIFO0, &RxMessage);
00203
00204   if((RxMessage.ExtId==0x1234) && (RxMessage.IDE==CAN_ID_EXT)
00205      && (RxMessage.DLC==2) && ((RxMessage.Data[1]|RxMessage.Data[0]<<8)==0xDECA))
00206   {
00207     ret = 1;
00208   }
00209   else
00210   {
00211     ret = 0;
00212   }
00213 }
00214 #endif
00215 /******************************************************************************/
00216 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00217 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00218 /*  available peripheral interrupt handler's name please refer to the startup */
00219 /*  file (startup_stm32f10x_xx.s).                                            */
00220 /******************************************************************************/
00221
00222 /**
00223   * @brief  This function handles PPP interrupt request.
00224   * @param  None
00225   * @retval None
00226   */
00227 /*void PPP_IRQHandler(void)
00228 {
00229 }*/
00230
00231 /**
00232   * @}
00233   */
00234
00235 /**
00236   * @}
00237   */
00238
00239 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_it.h

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00001 /**
00002   ******************************************************************************
00003   * @file    CAN/LoopBack/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043 #ifdef STM32F10X_CL
00044 void CAN1_RX0_IRQHandler(void);
00045 #else
00046 void USB_LP_CAN1_RX0_IRQHandler(void);
00047 #endif
00048
00049 #endif /* __STM32F10x_IT_H */
00050
00051 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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STM32F10x_StdPeriph_Examples/CAN/Networking/main.c

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00001 /**
00002   ******************************************************************************
00003   * @file    CAN/Networking/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x.h"
00024 #include "platform_config.h"
00025
00026 /** @addtogroup STM32F10x_StdPeriph_Examples
00027   * @{
00028   */
00029
00030 /** @addtogroup CAN_Networking
00031   * @{
00032   */
00033
00034
00035 /* Private typedef -----------------------------------------------------------*/
00036 /* Private define ------------------------------------------------------------*/
00037 #define __CAN1_USED__
00038 /* #define __CAN2_USED__*/
00039
00040 #ifdef  __CAN1_USED__
00041   #define CANx                       CAN1
00042   #define GPIO_CAN                   GPIO_CAN1
00043   #define GPIO_Remapping_CAN         GPIO_Remapping_CAN1
00044   #define GPIO_CAN                   GPIO_CAN1
00045   #define GPIO_Pin_CAN_RX            GPIO_Pin_CAN1_RX
00046   #define GPIO_Pin_CAN_TX            GPIO_Pin_CAN1_TX
00047 #else /*__CAN2_USED__*/
00048   #define CANx                       CAN2
00049   #define GPIO_CAN                   GPIO_CAN2
00050   #define GPIO_Remapping_CAN             GPIO_Remap_CAN2
00051   #define GPIO_CAN                   GPIO_CAN2
00052   #define GPIO_Pin_CAN_RX            GPIO_Pin_CAN2_RX
00053   #define GPIO_Pin_CAN_TX            GPIO_Pin_CAN2_TX
00054 #endif  /* __CAN1_USED__ */
00055
00056 #define KEY_PRESSED     0x01
00057 #define KEY_NOT_PRESSED 0x00
00058
00059 /* Private macro -------------------------------------------------------------*/
00060 /* Private variables ---------------------------------------------------------*/
00061 CAN_InitTypeDef        CAN_InitStructure;
00062 CAN_FilterInitTypeDef  CAN_FilterInitStructure;
00063 CanTxMsg TxMessage;
00064 uint8_t KeyNumber = 0x0;
00065
00066 /* Private function prototypes -----------------------------------------------*/
00067 void NVIC_Config(void);
00068 void CAN_Config(void);
00069 void LED_Display(uint8_t Ledstatus);
00070 void Init_RxMes(CanRxMsg *RxMessage);
00071 void Delay(void);
00072
00073 /* Private functions ---------------------------------------------------------*/
00074
00075 /**
00076   * @brief  Main program.
00077   * @param  None
00078   * @retval None
00079   */
00080 int main(void)
00081 {
00082   /*!< At this stage the microcontroller clock setting is already configured,
00083        this is done through SystemInit() function which is called from startup
00084        file (startup_stm32f10x_xx.s) before to branch to application main.
00085        To reconfigure the default setting of SystemInit() function, refer to
00086        system_stm32f10x.c file
00087      */
00088
00089   /* NVIC configuration */
00090   NVIC_Config();
00091
00092   /* Configures LED 1..4 */
00093   STM_EVAL_LEDInit(LED1);
00094   STM_EVAL_LEDInit(LED2);
00095   STM_EVAL_LEDInit(LED3);
00096   STM_EVAL_LEDInit(LED4);
00097
00098   /* Configure Push button key */
00099   STM_EVAL_PBInit(BUTTON_KEY, BUTTON_MODE_GPIO);
00100
00101   /* CAN configuration */
00102   CAN_Config();
00103
00104   CAN_ITConfig(CANx, CAN_IT_FMP0, ENABLE);
00105
00106   /* turn off all leds*/
00107   STM_EVAL_LEDOff(LED1);
00108   STM_EVAL_LEDOff(LED2);
00109   STM_EVAL_LEDOff(LED3);
00110   STM_EVAL_LEDOff(LED4);
00111
00112   /* Infinite loop */
00113   while(1)
00114   {
00115     while(STM_EVAL_PBGetState(BUTTON_KEY) == KEY_PRESSED)
00116     {
00117       if(KeyNumber == 0x4)
00118       {
00119         KeyNumber = 0x00;
00120       }
00121       else
00122       {
00123         LED_Display(++KeyNumber);
00124         TxMessage.Data[0] = KeyNumber;
00125         CAN_Transmit(CANx, &TxMessage);
00126         Delay();
00127
00128         while(STM_EVAL_PBGetState(BUTTON_KEY) != KEY_NOT_PRESSED)
00129         {
00130         }
00131       }
00132     }
00133   }
00134 }
00135
00136 /**
00137   * @brief  Configures the CAN.
00138   * @param  None
00139   * @retval None
00140   */
00141 void CAN_Config(void)
00142 {
00143   GPIO_InitTypeDef  GPIO_InitStructure;
00144
00145   /* GPIO clock enable */
00146   RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE);
00147 #ifdef  __CAN1_USED__
00148   RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIO_CAN1, ENABLE);
00149 #else /*__CAN2_USED__*/
00150   RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIO_CAN1, ENABLE);
00151   RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIO_CAN2, ENABLE);
00152 #endif  /* __CAN1_USED__ */
00153   /* Configure CAN pin: RX */
00154   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_CAN_RX;
00155   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
00156   GPIO_Init(GPIO_CAN, &GPIO_InitStructure);
00157
00158   /* Configure CAN pin: TX */
00159   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_CAN_TX;
00160   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
00161   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00162   GPIO_Init(GPIO_CAN, &GPIO_InitStructure);
00163
00164   GPIO_PinRemapConfig(GPIO_Remapping_CAN , ENABLE);
00165
00166   /* CANx Periph clock enable */
00167 #ifdef  __CAN1_USED__
00168   RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN1, ENABLE);
00169 #else /*__CAN2_USED__*/
00170   RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN1, ENABLE);
00171   RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN2, ENABLE);
00172 #endif  /* __CAN1_USED__ */
00173
00174
00175   /* CAN register init */
00176   CAN_DeInit(CANx);
00177   CAN_StructInit(&CAN_InitStructure);
00178
00179   /* CAN cell init */
00180   CAN_InitStructure.CAN_TTCM = DISABLE;
00181   CAN_InitStructure.CAN_ABOM = DISABLE;
00182   CAN_InitStructure.CAN_AWUM = DISABLE;
00183   CAN_InitStructure.CAN_NART = DISABLE;
00184   CAN_InitStructure.CAN_RFLM = DISABLE;
00185   CAN_InitStructure.CAN_TXFP = DISABLE;
00186   CAN_InitStructure.CAN_Mode = CAN_Mode_Normal;
00187
00188   /* CAN Baudrate = 1MBps*/
00189   CAN_InitStructure.CAN_SJW = CAN_SJW_1tq;
00190   CAN_InitStructure.CAN_BS1 = CAN_BS1_3tq;
00191   CAN_InitStructure.CAN_BS2 = CAN_BS2_5tq;
00192   CAN_InitStructure.CAN_Prescaler = 4;
00193   CAN_Init(CANx, &CAN_InitStructure);
00194
00195   /* CAN filter init */
00196 #ifdef  __CAN1_USED__
00197   CAN_FilterInitStructure.CAN_FilterNumber = 0;
00198 #else /*__CAN2_USED__*/
00199   CAN_FilterInitStructure.CAN_FilterNumber = 14;
00200 #endif  /* __CAN1_USED__ */
00201   CAN_FilterInitStructure.CAN_FilterMode = CAN_FilterMode_IdMask;
00202   CAN_FilterInitStructure.CAN_FilterScale = CAN_FilterScale_32bit;
00203   CAN_FilterInitStructure.CAN_FilterIdHigh = 0x0000;
00204   CAN_FilterInitStructure.CAN_FilterIdLow = 0x0000;
00205   CAN_FilterInitStructure.CAN_FilterMaskIdHigh = 0x0000;
00206   CAN_FilterInitStructure.CAN_FilterMaskIdLow = 0x0000;
00207   CAN_FilterInitStructure.CAN_FilterFIFOAssignment = 0;
00208   CAN_FilterInitStructure.CAN_FilterActivation = ENABLE;
00209   CAN_FilterInit(&CAN_FilterInitStructure);
00210
00211   /* Transmit */
00212   TxMessage.StdId = 0x321;
00213   TxMessage.ExtId = 0x01;
00214   TxMessage.RTR = CAN_RTR_DATA;
00215   TxMessage.IDE = CAN_ID_STD;
00216   TxMessage.DLC = 1;
00217 }
00218
00219 /**
00220   * @brief  Configures the NVIC for CAN.
00221   * @param  None
00222   * @retval None
00223   */
00224 void NVIC_Config(void)
00225 {
00226   NVIC_InitTypeDef  NVIC_InitStructure;
00227
00228   NVIC_PriorityGroupConfig(NVIC_PriorityGroup_0);
00229
00230 #ifndef STM32F10X_CL
00231 #ifdef  __CAN1_USED__
00232   NVIC_InitStructure.NVIC_IRQChannel = USB_LP_CAN1_RX0_IRQn;
00233 #else  /*__CAN2_USED__*/
00234   /* CAN2 is not implemented in the device */
00235    #error "CAN2 is implemented only in Connectivity line devices"
00236 #endif /*__CAN1_USED__*/
00237 #else
00238 #ifdef  __CAN1_USED__
00239   NVIC_InitStructure.NVIC_IRQChannel = CAN1_RX0_IRQn;
00240 #else  /*__CAN2_USED__*/
00241   NVIC_InitStructure.NVIC_IRQChannel = CAN2_RX0_IRQn;
00242 #endif /*__CAN1_USED__*/
00243
00244 #endif /* STM32F10X_CL*/
00245   NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x0;
00246   NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x0;
00247   NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
00248   NVIC_Init(&NVIC_InitStructure);
00249 }
00250
00251 /**
00252   * @brief  Initializes a Rx Message.
00253   * @param  CanRxMsg *RxMessage
00254   * @retval None
00255   */
00256 void Init_RxMes(CanRxMsg *RxMessage)
00257 {
00258   uint8_t i = 0;
00259
00260   RxMessage->StdId = 0x00;
00261   RxMessage->ExtId = 0x00;
00262   RxMessage->IDE = CAN_ID_STD;
00263   RxMessage->DLC = 0;
00264   RxMessage->FMI = 0;
00265   for (i = 0;i < 8;i++)
00266   {
00267     RxMessage->Data[i] = 0x00;
00268   }
00269 }
00270
00271 /**
00272   * @brief  Turn ON/OFF the dedicate led
00273   * @param  Ledstatus: Led number from 0 to 3.
00274   * @retval None
00275   */
00276 void LED_Display(uint8_t Ledstatus)
00277 {
00278   /* Turn off all leds */
00279   STM_EVAL_LEDOff(LED1);
00280   STM_EVAL_LEDOff(LED2);
00281   STM_EVAL_LEDOff(LED3);
00282   STM_EVAL_LEDOff(LED4);
00283
00284   switch(Ledstatus)
00285   {
00286     case(1):
00287       STM_EVAL_LEDOn(LED1);
00288       break;
00289
00290     case(2):
00291       STM_EVAL_LEDOn(LED2);
00292       break;
00293
00294     case(3):
00295       STM_EVAL_LEDOn(LED3);
00296       break;
00297
00298     case(4):
00299       STM_EVAL_LEDOn(LED4);
00300       break;
00301     default:
00302       break;
00303   }
00304 }
00305
00306 /**
00307   * @brief  Delay
00308   * @param  None
00309   * @retval None
00310   */
00311 void Delay(void)
00312 {
00313   uint16_t nTime = 0x0000;
00314
00315   for(nTime = 0; nTime <0xFFF; nTime++)
00316   {
00317   }
00318 }
00319
00320 #ifdef  USE_FULL_ASSERT
00321
00322 /**
00323   * @brief  Reports the name of the source file and the source line number
00324   *         where the assert_param error has occurred.
00325   * @param  file: pointer to the source file name
00326   * @param  line: assert_param error line source number
00327   * @retval None
00328   */
00329 void assert_failed(uint8_t* file, uint32_t line)
00330 {
00331   /* User can add his own implementation to report the file name and line number,
00332      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00333
00334   /* Infinite loop */
00335   while (1)
00336   {
00337   }
00338 }
00339
00340 #endif
00341
00342 /**
00343   * @}
00344   */
00345
00346 /**
00347   * @}
00348   */
00349
00350 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_conf.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    CAN/Networking/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052 /* Exported types ------------------------------------------------------------*/
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Uncomment the line below to expanse the "assert_param" macro in the
00055    Standard Peripheral Library drivers code */
00056 /* #define USE_FULL_ASSERT    1 */
00057
00058 /* Exported macro ------------------------------------------------------------*/
00059 #ifdef  USE_FULL_ASSERT
00060
00061 /**
00062   * @brief  The assert_param macro is used for function's parameters check.
00063   * @param  expr: If expr is false, it calls assert_failed function which reports
00064   *         the name of the source file and the source line number of the call
00065   *         that failed. If expr is true, it returns no value.
00066   * @retval None
00067   */
00068   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00069 /* Exported functions ------------------------------------------------------- */
00070   void assert_failed(uint8_t* file, uint32_t line);
00071 #else
00072   #define assert_param(expr) ((void)0)
00073 #endif /* USE_FULL_ASSERT */
00074
00075 #endif /* __STM32F10x_CONF_H */
00076
00077 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_it.c

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00001 /**
00002   ******************************************************************************
00003   * @file    CAN/Networking/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and
00009   *          peripherals interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026
00027 /** @addtogroup STM32F10x_StdPeriph_Examples
00028   * @{
00029   */
00030
00031 /** @addtogroup CAN_Networking
00032   * @{
00033   */
00034
00035 /* Private typedef -----------------------------------------------------------*/
00036 /* Private define ------------------------------------------------------------*/
00037 /* Private macro -------------------------------------------------------------*/
00038 /* Private variables ---------------------------------------------------------*/
00039 CanRxMsg RxMessage;
00040 extern uint8_t KeyNumber;
00041 extern void LED_Display(uint8_t Ledstatus);
00042
00043 /* Private function prototypes -----------------------------------------------*/
00044 /* Private functions ---------------------------------------------------------*/
00045
00046 /******************************************************************************/
00047 /*            Cortex-M3 Processor Exceptions Handlers                         */
00048 /******************************************************************************/
00049
00050 /**
00051   * @brief  This function handles NMI exception.
00052   * @param  None
00053   * @retval None
00054   */
00055 void NMI_Handler(void)
00056 {
00057 }
00058
00059 /**
00060   * @brief  This function handles Hard Fault exception.
00061   * @param  None
00062   * @retval None
00063   */
00064 void HardFault_Handler(void)
00065 {
00066   /* Go to infinite loop when Hard Fault exception occurs */
00067   while (1)
00068   {
00069   }
00070 }
00071
00072 /**
00073   * @brief  This function handles Memory Manage exception.
00074   * @param  None
00075   * @retval None
00076   */
00077 void MemManage_Handler(void)
00078 {
00079   /* Go to infinite loop when Memory Manage exception occurs */
00080   while (1)
00081   {
00082   }
00083 }
00084
00085 /**
00086   * @brief  This function handles Bus Fault exception.
00087   * @param  None
00088   * @retval None
00089   */
00090 void BusFault_Handler(void)
00091 {
00092   /* Go to infinite loop when Bus Fault exception occurs */
00093   while (1)
00094   {
00095   }
00096 }
00097
00098 /**
00099   * @brief  This function handles Usage Fault exception.
00100   * @param  None
00101   * @retval None
00102   */
00103 void UsageFault_Handler(void)
00104 {
00105   /* Go to infinite loop when Usage Fault exception occurs */
00106   while (1)
00107   {
00108   }
00109 }
00110
00111 /**
00112   * @brief  This function handles SVCall exception.
00113   * @param  None
00114   * @retval None
00115   */
00116 void SVC_Handler(void)
00117 {
00118 }
00119
00120 /**
00121   * @brief  This function handles Debug Monitor exception.
00122   * @param  None
00123   * @retval None
00124   */
00125 void DebugMon_Handler(void)
00126 {
00127 }
00128
00129 /**
00130   * @brief  This function handles PendSVC exception.
00131   * @param  None
00132   * @retval None
00133   */
00134 void PendSV_Handler(void)
00135 {
00136 }
00137
00138 /**
00139   * @brief  This function handles SysTick Handler.
00140   * @param  None
00141   * @retval None
00142   */
00143 void SysTick_Handler(void)
00144 {
00145 }
00146
00147 /******************************************************************************/
00148 /*            STM32F10x Peripherals Interrupt Handlers                        */
00149 /******************************************************************************/
00150
00151 /**
00152   * @brief  This function handles CAN1 Handler.
00153   * @param  None
00154   * @retval None
00155   */
00156 #ifndef STM32F10X_CL
00157 void USB_LP_CAN1_RX0_IRQHandler(void)
00158 #else
00159 void CAN1_RX0_IRQHandler(void)
00160 #endif
00161 {
00162   CAN_Receive(CAN1, CAN_FIFO0, &RxMessage);
00163   if ((RxMessage.StdId == 0x321)&&(RxMessage.IDE == CAN_ID_STD) && (RxMessage.DLC == 1))
00164   {
00165     LED_Display(RxMessage.Data[0]);
00166     KeyNumber = RxMessage.Data[0];
00167   }
00168 }
00169
00170 /**
00171   * @brief  This function handles CAN2 Handler.
00172   * @param  None
00173   * @retval None
00174   */
00175 #ifdef STM32F10X_CL
00176 void CAN2_RX0_IRQHandler(void)
00177 {
00178   CAN_Receive(CAN2, CAN_FIFO0, &RxMessage);
00179   if ((RxMessage.StdId == 0x321)&&(RxMessage.IDE == CAN_ID_STD) && (RxMessage.DLC == 1))
00180   {
00181     LED_Display(RxMessage.Data[0]);
00182     KeyNumber = RxMessage.Data[0];
00183   }
00184 }
00185 #endif
00186 /******************************************************************************/
00187 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00188 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00189 /*  available peripheral interrupt handler's name please refer to the startup */
00190 /*  file (startup_stm32f10x_xx.s).                                            */
00191 /******************************************************************************/
00192
00193 /**
00194   * @brief  This function handles PPP interrupt request.
00195   * @param  None
00196   * @retval None
00197   */
00198 /*void PPP_IRQHandler(void)
00199 {
00200 }*/
00201
00202 /**
00203   * @}
00204   */
00205
00206 /**
00207   * @}
00208   */
00209
00210
00211 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_it.h

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00001 /**
00002   ******************************************************************************
00003   * @file    CAN/Networking/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043 #ifndef STM32F10X_CL
00044 void USB_LP_CAN1_RX0_IRQHandler(void);
00045 #else
00046 void CAN1_RX0_IRQHandler(void);
00047 #endif
00048
00049 #endif /* __STM32F10x_IT_H */
00050
00051 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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  • CEC
  • DataExchangeInterrupt

STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/main.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    CEC/DataExchangeInterrupt/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x.h"
00024 #include "stm32_eval.h"
00025
00026 /** @addtogroup STM32F10x_StdPeriph_Examples
00027   * @{
00028   */
00029
00030 /** @addtogroup CEC_DataExchangeInterrupt
00031   * @{
00032   */
00033
00034
00035 /* Private typedef -----------------------------------------------------------*/
00036 typedef enum {FAILED = 0, PASSED = !FAILED} TestStatus;
00037
00038 /* Private define ------------------------------------------------------------*/
00039 /* Private macro -------------------------------------------------------------*/
00040 /* Private variables ---------------------------------------------------------*/
00041 CEC_InitTypeDef CEC_InitStructure;
00042
00043 uint8_t ByteNumber = 10;
00044 volatile TestStatus TransferStatus = FAILED;
00045 extern uint8_t TransmitBuffer[10];
00046 extern uint8_t ReceiveBuffer[10];
00047 extern __IO uint8_t ReceivedFrame;
00048
00049 /* Private function prototypes -----------------------------------------------*/
00050 void RCC_Configuration(void);
00051 void NVIC_Configuration(void);
00052 void GPIO_Configuration(void);
00053 TestStatus Buffercmp(uint8_t* pBuffer1, uint8_t* pBuffer2, uint16_t BufferLength);
00054
00055 /* Private functions ---------------------------------------------------------*/
00056
00057 /**
00058   * @brief  Main program
00059   * @param  None
00060   * @retval None
00061   */
00062 int main(void)
00063 {
00064   /*!< At this stage the microcontroller clock setting is already configured,
00065        this is done through SystemInit() function which is called from startup
00066        file (startup_stm32f10x_xx.s) before to branch to application main.
00067        To reconfigure the default setting of SystemInit() function, refer to
00068        system_stm32f10x.c file
00069      */
00070
00071   /* RCC configuration */
00072   RCC_Configuration();
00073
00074   /* NVIC configuration */
00075   NVIC_Configuration();
00076
00077   /* GPIO configuration */
00078   GPIO_Configuration();
00079
00080   /* Configure the CEC peripheral */
00081   CEC_InitStructure.CEC_BitTimingMode = CEC_BitTimingStdMode;
00082   CEC_InitStructure.CEC_BitPeriodMode = CEC_BitPeriodStdMode;
00083   CEC_Init(&CEC_InitStructure);
00084
00085   /* Set Prescaler value for APB1 clock PCLK1 = 24MHz */
00086   CEC_SetPrescaler(0x4AF);
00087
00088   /* Set the CEC initiator address */
00089   CEC_OwnAddressConfig(MY_DEVICE_ADDRESS);
00090
00091   /* Activate CEC interrupts associated to the set of RBTF,RERR, TBTF, TERR flags */
00092   CEC_ITConfig(ENABLE);
00093
00094   /* Enable CEC */
00095   CEC_Cmd(ENABLE);
00096
00097   /* If a frame has been received */
00098   while(ReceivedFrame == 0)
00099   {
00100   }
00101
00102   /* Check the received data with the send ones */
00103   TransferStatus = Buffercmp(TransmitBuffer, ReceiveBuffer, ByteNumber);
00104   /* TransferStatus = PASSED, if the data transmitted from CEC Device1 and
00105      received by CEC Device2 are the same */
00106   /* TransferStatus = FAILED, if the data transmitted from CEC Device1 and
00107      received by CEC Device2 are different */
00108
00109   if (TransferStatus == PASSED)
00110   {
00111     /* OK */
00112     /* Turn on LED1 */
00113     STM_EVAL_LEDOn(LED1);
00114   }
00115   else
00116   {
00117     /* KO */
00118     /* Turn on LED2 */
00119     STM_EVAL_LEDOn(LED2);
00120   }
00121   while(1)
00122   {
00123   }
00124 }
00125
00126 /**
00127   * @brief  Configures the different system clocks.
00128   * @param  None
00129   * @retval None
00130   */
00131 void RCC_Configuration(void)
00132 {
00133   /* Enable CEC clock */
00134   RCC_APB1PeriphClockCmd(RCC_APB1Periph_CEC, ENABLE);
00135
00136   /* Initialize LEDs and Key Button available on STM32F100B-EVAL board ***/
00137   /* Configure LED1, LED2, LED3 and LED4 */
00138   STM_EVAL_LEDInit(LED1);
00139   STM_EVAL_LEDInit(LED2);
00140   STM_EVAL_LEDInit(LED3);
00141   STM_EVAL_LEDInit(LED4);
00142
00143   /* Configure the Key Push button and its associated EXTI Line */
00144   STM_EVAL_PBInit(Button_KEY, Mode_EXTI);
00145 }
00146
00147 /**
00148   * @brief  Configures the different NVIC interrupts.
00149   * @param  None
00150   * @retval None
00151   */
00152 void NVIC_Configuration(void)
00153 {
00154   NVIC_InitTypeDef NVIC_InitStructure;
00155
00156   /* Configure two bits for preemption priority */
00157   NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);
00158
00159   /* Enable the CEC global Interrupt (with higher priority) */
00160   NVIC_InitStructure.NVIC_IRQChannel = CEC_IRQn;
00161   NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
00162   NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
00163   NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
00164   NVIC_Init(&NVIC_InitStructure);
00165 }
00166
00167 /**
00168   * @brief  Configures the different GPIO ports.
00169   * @param  None
00170   * @retval None
00171   */
00172 void GPIO_Configuration(void)
00173 {
00174   GPIO_InitTypeDef GPIO_InitStructure;
00175
00176   /* Enable GPIOB  clocks */
00177   RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE);
00178
00179   /* Configure GPIOB Pin 8 (CEC line) as Output open drain */
00180   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8;
00181   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00182   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_OD;
00183   GPIO_Init(GPIOB, &GPIO_InitStructure);
00184 }
00185
00186 /**
00187   * @brief  Compares two buffers.
00188   * @param  pBuffer1, pBuffer2: buffers to be compared.
00189   * @param  BufferLength: buffer's length
00190   * @retval PASSED: pBuffer1 identical to pBuffer2
00191   *         FAILED: pBuffer1 differs from pBuffer2
00192   */
00193 TestStatus Buffercmp(uint8_t* pBuffer1, uint8_t* pBuffer2, uint16_t BufferLength)
00194 {
00195   while(BufferLength--)
00196   {
00197     if(*pBuffer1 != *pBuffer2)
00198     {
00199       return FAILED;
00200     }
00201
00202     pBuffer1++;
00203     pBuffer2++;
00204   }
00205
00206   return PASSED;
00207 }
00208
00209 #ifdef  USE_FULL_ASSERT
00210
00211 /**
00212   * @brief  Reports the name of the source file and the source line number
00213   *         where the assert_param error has occurred.
00214   * @param  file: pointer to the source file name
00215   * @param  line: assert_param error line source number
00216   * @retval None
00217   */
00218 void assert_failed(uint8_t* file, uint32_t line)
00219 {
00220   /* User can add his own implementation to report the file name and line number,
00221      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00222
00223   /* Infinite loop */
00224   while (1)
00225   {
00226   }
00227 }
00228
00229 #endif
00230
00231 /**
00232   * @}
00233   */
00234
00235 /**
00236   * @}
00237   */
00238
00239 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
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  • CEC
  • DataExchangeInterrupt

STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_conf.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    CEC/DataExchangeInterrupt/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052 /* Exported types ------------------------------------------------------------*/
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Uncomment the line below to expanse the "assert_param" macro in the
00055    Standard Peripheral Library drivers code */
00056 /* #define USE_FULL_ASSERT    1 */
00057
00058 #if !defined (CEC_DEVICE1) && !defined (CEC_DEVICE2)
00059   #define CEC_DEVICE1  1
00060   /* #define CEC_DEVICE2  2 */
00061 #endif
00062
00063 #ifdef CEC_DEVICE1
00064  #define MY_DEVICE_ADDRESS  0x01 /* My device address: is my initiator address
00065                                     in case of transmit and the follower address
00066                                     in case of receive */
00067  #define FOLLOWER           0x02
00068 #elif defined  CEC_DEVICE2
00069  #define MY_DEVICE_ADDRESS  0x02 /* My device address: is my initiator address
00070                                     in case of transmit and the follower address
00071                                     in case of receive */
00072  #define FOLLOWER           0x01
00073 #endif
00074
00075 /* Exported macro ------------------------------------------------------------*/
00076 #ifdef  USE_FULL_ASSERT
00077
00078 /**
00079   * @brief  The assert_param macro is used for function's parameters check.
00080   * @param  expr: If expr is false, it calls assert_failed function which reports
00081   *         the name of the source file and the source line number of the call
00082   *         that failed. If expr is true, it returns no value.
00083   * @retval None
00084   */
00085   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00086 /* Exported functions ------------------------------------------------------- */
00087   void assert_failed(uint8_t* file, uint32_t line);
00088 #else
00089   #define assert_param(expr) ((void)0)
00090 #endif /* USE_FULL_ASSERT */
00091
00092 #endif /* __STM32F10x_CONF_H */
00093
00094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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  • DataExchangeInterrupt

STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    CEC/DataExchangeInterrupt/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and
00009   *          peripherals interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026 #include "stm32_eval.h"
00027
00028 /** @addtogroup STM32F10x_StdPeriph_Examples
00029   * @{
00030   */
00031
00032 /** @addtogroup CEC_DataExchangeInterrupt
00033   * @{
00034   */
00035
00036 /* Private typedef -----------------------------------------------------------*/
00037 /* Private define ------------------------------------------------------------*/
00038 /* Private macro -------------------------------------------------------------*/
00039 /* Private variables ---------------------------------------------------------*/
00040 /* Receive buffer */
00041 uint8_t ReceiveBuffer[10];
00042 /* Transmit buffer */
00043 uint8_t TransmitBuffer[10] = {0xDF, 0x12, 0xD3, 0x56, 0x97,
00044                               0xA1, 0xEC, 0x7B, 0x4F, 0x22};
00045 __IO uint8_t ReceivedFrame = 0;
00046 uint8_t send_inc = 0, rcv_inc = 0;
00047 uint8_t HeaderBlockValueToSend = 0;
00048 uint8_t InitiatorAddress = 0;
00049 uint8_t TransErrorCode = 0;
00050 uint8_t RecepErrorCode = 0;
00051 extern uint8_t ByteNumber;
00052
00053 /* Private function prototypes -----------------------------------------------*/
00054 /* Private functions ---------------------------------------------------------*/
00055
00056 /******************************************************************************/
00057 /*            Cortex-M3 Processor Exceptions Handlers                         */
00058 /******************************************************************************/
00059
00060 /**
00061   * @brief   This function handles NMI exception.
00062   * @param  None
00063   * @retval None
00064   */
00065 void NMI_Handler(void)
00066 {
00067 }
00068
00069 /**
00070   * @brief  This function handles Hard Fault exception.
00071   * @param  None
00072   * @retval None
00073   */
00074 void HardFault_Handler(void)
00075 {
00076   /* Go to infinite loop when Hard Fault exception occurs */
00077   while (1)
00078   {
00079   }
00080 }
00081
00082 /**
00083   * @brief  This function handles Memory Manage exception.
00084   * @param  None
00085   * @retval None
00086   */
00087 void MemManage_Handler(void)
00088 {
00089   /* Go to infinite loop when Memory Manage exception occurs */
00090   while (1)
00091   {
00092   }
00093 }
00094
00095 /**
00096   * @brief  This function handles Bus Fault exception.
00097   * @param  None
00098   * @retval None
00099   */
00100 void BusFault_Handler(void)
00101 {
00102   /* Go to infinite loop when Bus Fault exception occurs */
00103   while (1)
00104   {
00105   }
00106 }
00107
00108 /**
00109   * @brief  This function handles Usage Fault exception.
00110   * @param  None
00111   * @retval None
00112   */
00113 void UsageFault_Handler(void)
00114 {
00115   /* Go to infinite loop when Usage Fault exception occurs */
00116   while (1)
00117   {
00118   }
00119 }
00120
00121 /**
00122   * @brief  This function handles SVCall exception.
00123   * @param  None
00124   * @retval None
00125   */
00126 void SVC_Handler(void)
00127 {
00128 }
00129
00130 /**
00131   * @brief  This function handles Debug Monitor exception.
00132   * @param  None
00133   * @retval None
00134   */
00135 void DebugMon_Handler(void)
00136 {
00137 }
00138
00139 /**
00140   * @brief  This function handles PendSVC exception.
00141   * @param  None
00142   * @retval None
00143   */
00144 void PendSV_Handler(void)
00145 {
00146 }
00147
00148 /**
00149   * @brief  This function handles SysTick Handler.
00150   * @param  None
00151   * @retval None
00152   */
00153 void SysTick_Handler(void)
00154 {
00155 }
00156
00157 /**
00158   * @brief  This function handles EXTI Lines 9 to 5 interrupts requests.
00159   * @param  None
00160   * @retval None
00161   */
00162 void EXTI9_5_IRQHandler(void)
00163 {
00164   /* Generate rising edge on Key button to detect when we push key button to initiate
00165      transmission */
00166   if(EXTI_GetITStatus(KEY_BUTTON_EXTI_LINE) != RESET)
00167   {
00168     /* Turn on LED3 */
00169     STM_EVAL_LEDOn(LED3);
00170
00171     /* Build the Header block to send */
00172     HeaderBlockValueToSend = (((MY_DEVICE_ADDRESS & 0xF) << 4) | (FOLLOWER & 0xF));
00173
00174     /* Write single Data in the TX Buffer to Transmit through the CEC peripheral */
00175     CEC_SendDataByte(HeaderBlockValueToSend);
00176
00177     /* Initiate Message Transmission */
00178     CEC_StartOfMessage();
00179
00180     /* Clear Key Button EXTI line pending bit */
00181     EXTI_ClearITPendingBit(KEY_BUTTON_EXTI_LINE);
00182   }
00183 }
00184
00185 /**
00186   * @brief  This function handles CEC global interrupt request.
00187   * @param  None
00188   * @retval None
00189   */
00190 void CEC_IRQHandler(void)
00191 {
00192   /* Turn on LED4 */
00193   STM_EVAL_LEDOn(LED4);
00194 /********************** Reception *********************************************/
00195   /* Check if a reception error occurred */
00196   if (CEC_GetFlagStatus(CEC_FLAG_RERR))
00197   {
00198     /* Set receive status bit (Error) */
00199     RecepErrorCode = CEC->ESR;
00200     CEC_ClearFlag(CEC_FLAG_RERR | CEC_FLAG_RSOM | CEC_FLAG_REOM  | CEC_FLAG_RBTF);
00201   }
00202   else if (CEC_GetFlagStatus(CEC_FLAG_RBTF))
00203   {
00204     /* Check if the byte received is the last one of the message */
00205     if (CEC_GetFlagStatus(CEC_FLAG_REOM))
00206     {
00207       ReceiveBuffer[rcv_inc] = CEC_ReceiveDataByte();
00208       rcv_inc++;
00209       ReceivedFrame = 1;
00210     }
00211     /* Check if the byte received is a Header */
00212     else if (CEC_GetFlagStatus(CEC_FLAG_RSOM))
00213     {
00214
00215       InitiatorAddress = ((CEC_ReceiveDataByte() >> 4) & 0x0F);
00216       rcv_inc = 0;
00217     }
00218     /* Receive each byte except header in the reception buffer */
00219     else
00220     {
00221       ReceiveBuffer[rcv_inc] = CEC_ReceiveDataByte();
00222       rcv_inc++;
00223     }
00224     /* Clear all reception flags */
00225     CEC_ClearFlag(CEC_FLAG_RSOM | CEC_FLAG_REOM  | CEC_FLAG_RBTF);
00226   }
00227
00228 /********************** Transmission ******************************************/
00229   /* Check if a transmission error occurred */
00230   if (CEC_GetFlagStatus(CEC_FLAG_TERR))
00231   {
00232     TransErrorCode = CEC->ESR;
00233     CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR);
00234
00235   }
00236   /* Check if end of message bit is set in the data to be transmitted */
00237   else if (CEC_GetFlagStatus(CEC_FLAG_TEOM))
00238   {
00239     CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_RBTF);
00240     CEC_EndOfMessageCmd(DISABLE);
00241   }
00242   /* Check if data byte has been sent */
00243   else if (CEC_GetFlagStatus(CEC_FLAG_TBTRF))
00244   {
00245     /* Set EOM bit if the byte to be transmitted is the last one of the Transmit Buffer */
00246     if (send_inc == (ByteNumber - 1))
00247     {
00248       CEC_SendDataByte(TransmitBuffer[send_inc]);
00249       send_inc++;
00250       CEC_ClearFlag(CEC_FLAG_TBTRF);
00251       CEC_EndOfMessageCmd(ENABLE);
00252     }
00253     else
00254     {
00255       /* Put the byte in the TX Buffer */
00256       CEC_SendDataByte(TransmitBuffer[send_inc]);
00257       send_inc++;
00258       CEC_ClearFlag(CEC_FLAG_TBTRF);
00259     }
00260   }
00261 }
00262
00263 /******************************************************************************/
00264 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00265 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00266 /*  available peripheral interrupt handler's name please refer to the startup */
00267 /*  file (startup_stm32f10x_xx.s).                                            */
00268 /******************************************************************************/
00269
00270 /**
00271   * @brief  This function handles PPP interrupt request.
00272   * @param  None
00273   * @retval None
00274   */
00275 /*void PPP_IRQHandler(void)
00276 {
00277 }*/
00278
00279 /**
00280   * @}
00281   */
00282
00283 /**
00284   * @}
00285   */
00286
00287 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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  • CEC
  • DataExchangeInterrupt

STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    CEC/DataExchangeInterrupt/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 #ifdef __cplusplus
00027  extern "C" {
00028 #endif
00029
00030 /* Includes ------------------------------------------------------------------*/
00031 #include "stm32f10x.h"
00032
00033 /* Exported types ------------------------------------------------------------*/
00034 /* Exported constants --------------------------------------------------------*/
00035 /* Exported macro ------------------------------------------------------------*/
00036 /* Exported functions ------------------------------------------------------- */
00037
00038 void NMI_Handler(void);
00039 void HardFault_Handler(void);
00040 void MemManage_Handler(void);
00041 void BusFault_Handler(void);
00042 void UsageFault_Handler(void);
00043 void SVC_Handler(void);
00044 void DebugMon_Handler(void);
00045 void PendSV_Handler(void);
00046 void SysTick_Handler(void);
00047 void EXTI9_5_IRQHandler(void);
00048 void CEC_IRQHandler(void);
00049
00050 #ifdef __cplusplus
00051 }
00052 #endif
00053
00054 #endif /* __STM32F10x_IT_H */
00055
00056 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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STM32F10x_StdPeriph_Examples/CortexM3/BitBand/main.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    CortexM3/BitBand/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x.h"
00024
00025 /** @addtogroup STM32F10x_StdPeriph_Examples
00026   * @{
00027   */
00028
00029 /** @addtogroup CortexM3_BitBand
00030   * @{
00031   */
00032
00033 /* Private typedef -----------------------------------------------------------*/
00034 /* Private define ------------------------------------------------------------*/
00035 #define RAM_BASE       0x20000000
00036 #define RAM_BB_BASE    0x22000000
00037
00038 /* Private macro -------------------------------------------------------------*/
00039 #define  Var_ResetBit_BB(VarAddr, BitNumber)    \
00040           (*(__IO uint32_t *) (RAM_BB_BASE | ((VarAddr - RAM_BASE) << 5) | ((BitNumber) << 2)) = 0)
00041
00042 #define Var_SetBit_BB(VarAddr, BitNumber)       \
00043           (*(__IO uint32_t *) (RAM_BB_BASE | ((VarAddr - RAM_BASE) << 5) | ((BitNumber) << 2)) = 1)
00044
00045 #define Var_GetBit_BB(VarAddr, BitNumber)       \
00046           (*(__IO uint32_t *) (RAM_BB_BASE | ((VarAddr - RAM_BASE) << 5) | ((BitNumber) << 2)))
00047
00048 /* Private variables ---------------------------------------------------------*/
00049
00050 __IO uint32_t Var, VarAddr = 0, VarBitValue = 0;
00051
00052 /* Private function prototypes -----------------------------------------------*/
00053 /* Private functions ---------------------------------------------------------*/
00054
00055 /**
00056   * @brief   Main program.
00057   * @param  None
00058   * @retval None
00059   */
00060 int main(void)
00061 {
00062   /*!< At this stage the microcontroller clock setting is already configured,
00063        this is done through SystemInit() function which is called from startup
00064        file (startup_stm32f10x_xx.s) before to branch to application main.
00065        To reconfigure the default setting of SystemInit() function, refer to
00066        system_stm32f10x.c file
00067      */
00068
00069   Var = 0x00005AA5;
00070
00071 /* A mapping formula shows how to reference each word in the alias region to a
00072    corresponding bit in the bit-band region. The mapping formula is:
00073    bit_word_addr = bit_band_base + (byte_offset x 32) + (bit_number + 4)
00074
00075 where:
00076    - bit_word_addr: is the address of the word in the alias memory region that
00077                     maps to the targeted bit.
00078    - bit_band_base is the starting address of the alias region
00079    - byte_offset is the number of the byte in the bit-band region that contains
00080      the targeted bit
00081    - bit_number is the bit position (0-7) of the targeted bit */
00082
00083 /* Get the variable address --------------------------------------------------*/
00084   VarAddr = (uint32_t)&Var;
00085
00086 /* Modify variable bit using bit-band access ---------------------------------*/
00087   /* Modify Var variable bit 0 -----------------------------------------------*/
00088   Var_ResetBit_BB(VarAddr, 0);  /* Var = 0x00005AA4 */
00089   Var_SetBit_BB(VarAddr, 0);    /* Var = 0x00005AA5 */
00090
00091   /* Modify Var variable bit 11 ----------------------------------------------*/
00092   Var_ResetBit_BB(VarAddr, 11);             /* Var = 0x000052A5 */
00093   /* Get Var variable bit 11 value */
00094   VarBitValue = Var_GetBit_BB(VarAddr, 11); /* VarBitValue = 0x00000000 */
00095
00096   Var_SetBit_BB(VarAddr, 11);               /* Var = 0x00005AA5 */
00097   /* Get Var variable bit 11 value */
00098   VarBitValue = Var_GetBit_BB(VarAddr, 11);    /* VarBitValue = 0x00000001 */
00099
00100   /* Modify Var variable bit 31 ----------------------------------------------*/
00101   Var_SetBit_BB(VarAddr, 31);               /* Var = 0x80005AA5 */
00102   /* Get Var variable bit 31 value */
00103   VarBitValue = Var_GetBit_BB(VarAddr, 31); /* VarBitValue = 0x00000001 */
00104
00105   Var_ResetBit_BB(VarAddr, 31);             /* Var = 0x00005AA5 */
00106   /* Get Var variable bit 31 value */
00107   VarBitValue = Var_GetBit_BB(VarAddr, 31); /* VarBitValue = 0x00000000 */
00108
00109   while (1)
00110   {
00111   }
00112 }
00113
00114 #ifdef  USE_FULL_ASSERT
00115
00116 /**
00117   * @brief  Reports the name of the source file and the source line number
00118   *         where the assert_param error has occurred.
00119   * @param  file: pointer to the source file name
00120   * @param  line: assert_param error line source number
00121   * @retval None
00122   */
00123 void assert_failed(uint8_t* file, uint32_t line)
00124 {
00125   /* User can add his own implementation to report the file name and line number,
00126      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00127
00128   /* Infinite loop */
00129   while (1)
00130   {
00131   }
00132 }
00133
00134 #endif
00135
00136 /**
00137   * @}
00138   */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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STM32F10x_StdPeriph_Examples/CortexM3/BitBand/stm32f10x_conf.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    CortexM3/BitBand/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052 /* Exported types ------------------------------------------------------------*/
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Uncomment the line below to expanse the "assert_param" macro in the
00055    Standard Peripheral Library drivers code */
00056 /* #define USE_FULL_ASSERT    1 */
00057
00058 /* Exported macro ------------------------------------------------------------*/
00059 #ifdef  USE_FULL_ASSERT
00060 /**
00061   * @brief  The assert_param macro is used for function's parameters check.
00062   * @param  expr: If expr is false, it calls assert_failed function which reports
00063   *         the name of the source file and the source line number of the call
00064   *         that failed. If expr is true, it returns no value.
00065   * @retval None
00066   */
00067   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00068 /* Exported functions ------------------------------------------------------- */
00069   void assert_failed(uint8_t* file, uint32_t line);
00070 #else
00071   #define assert_param(expr) ((void)0)
00072 #endif /* USE_FULL_ASSERT */
00073
00074 #endif /* __STM32F10x_CONF_H */
00075
00076 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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STM32F10x_StdPeriph_Examples/CortexM3/BitBand/stm32f10x_it.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    CortexM3/BitBand/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and peripherals
00009   *          interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026
00027 /** @addtogroup STM32F10x_StdPeriph_Examples
00028   * @{
00029   */
00030
00031 /** @addtogroup CortexM3_BitBand
00032   * @{
00033   */
00034
00035 /* Private typedef -----------------------------------------------------------*/
00036 /* Private define ------------------------------------------------------------*/
00037 /* Private macro -------------------------------------------------------------*/
00038 /* Private variables ---------------------------------------------------------*/
00039 /* Private function prototypes -----------------------------------------------*/
00040 /* Private functions ---------------------------------------------------------*/
00041
00042 /******************************************************************************/
00043 /*            Cortex-M3 Processor Exceptions Handlers                         */
00044 /******************************************************************************/
00045
00046 /**
00047   * @brief  This function handles NMI exception.
00048   * @param  None
00049   * @retval None
00050   */
00051 void NMI_Handler(void)
00052 {
00053 }
00054
00055 /**
00056   * @brief  This function handles Hard Fault exception.
00057   * @param  None
00058   * @retval None
00059   */
00060 void HardFault_Handler(void)
00061 {
00062   /* Go to infinite loop when Hard Fault exception occurs */
00063   while (1)
00064   {
00065   }
00066 }
00067
00068 /**
00069   * @brief  This function handles Memory Manage exception.
00070   * @param  None
00071   * @retval None
00072   */
00073 void MemManage_Handler(void)
00074 {
00075   /* Go to infinite loop when Memory Manage exception occurs */
00076   while (1)
00077   {
00078   }
00079 }
00080
00081 /**
00082   * @brief  This function handles Bus Fault exception.
00083   * @param  None
00084   * @retval None
00085   */
00086 void BusFault_Handler(void)
00087 {
00088   /* Go to infinite loop when Bus Fault exception occurs */
00089   while (1)
00090   {
00091   }
00092 }
00093
00094 /**
00095   * @brief  This function handles Usage Fault exception.
00096   * @param  None
00097   * @retval None
00098   */
00099 void UsageFault_Handler(void)
00100 {
00101   /* Go to infinite loop when Usage Fault exception occurs */
00102   while (1)
00103   {
00104   }
00105 }
00106
00107 /**
00108   * @brief  This function handles SVCall exception.
00109   * @param  None
00110   * @retval None
00111   */
00112 void SVC_Handler(void)
00113 {
00114 }
00115
00116 /**
00117   * @brief  This function handles Debug Monitor exception.
00118   * @param  None
00119   * @retval None
00120   */
00121 void DebugMon_Handler(void)
00122 {
00123 }
00124
00125 /**
00126   * @brief  This function handles PendSV_Handler exception.
00127   * @param  None
00128   * @retval None
00129   */
00130 void PendSV_Handler(void)
00131 {
00132 }
00133
00134 /**
00135   * @brief  This function handles SysTick Handler.
00136   * @param  None
00137   * @retval None
00138   */
00139 void SysTick_Handler(void)
00140 {
00141 }
00142
00143 /******************************************************************************/
00144 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00145 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00146 /*  available peripheral interrupt handler's name please refer to the startup */
00147 /*  file (startup_stm32f10x_xx.s).                                            */
00148 /******************************************************************************/
00149
00150 /**
00151   * @brief  This function handles PPP interrupt request.
00152   * @param  None
00153   * @retval None
00154   */
00155 /*void PPP_IRQHandler(void)
00156 {
00157 }*/
00158
00159 /**
00160   * @}
00161   */
00162
00163 /**
00164   * @}
00165   */
00166
00167 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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STM32F10x_StdPeriph_Examples/CortexM3/BitBand/stm32f10x_it.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    CortexM3/BitBand/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043
00044 #endif /* __STM32F10x_IT_H */
00045
00046 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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  • Mode_Privilege

STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/main.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    CortexM3/Mode_Privilege/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x.h"
00024
00025 /** @addtogroup STM32F10x_StdPeriph_Examples
00026   * @{
00027   */
00028
00029 /** @addtogroup CortexM3_Mode_Privilege
00030   * @{
00031   */
00032
00033 /* Private typedef -----------------------------------------------------------*/
00034 /* Private define ------------------------------------------------------------*/
00035 #define SP_PROCESS_SIZE             0x200  /* Process stack size */
00036 #define SP_PROCESS                  0x02   /* Process stack */
00037 #define SP_MAIN                     0x00   /* Main stack */
00038 #define THREAD_MODE_PRIVILEGED      0x00   /* Thread mode has privileged access */
00039 #define THREAD_MODE_UNPRIVILEGED    0x01   /* Thread mode has unprivileged access */
00040
00041 /* Private macro -------------------------------------------------------------*/
00042 #if defined ( __CC_ARM   )
00043 __ASM void __SVC(void)
00044 {
00045   SVC 0x01
00046   BX R14
00047 }
00048 #elif defined ( __ICCARM__ )
00049 static __INLINE  void __SVC()                     { __ASM ("svc 0x01");}
00050 #elif defined   (  __GNUC__  )
00051 static __INLINE void __SVC()                      { __ASM volatile ("svc 0x01");}
00052
00053 #endif
00054
00055 /* Private variables ---------------------------------------------------------*/
00056 __IO uint8_t PSPMemAlloc[SP_PROCESS_SIZE];
00057 __IO uint32_t Index = 0, PSPValue = 0, CurrentStack = 0, ThreadMode = 0;
00058
00059 /* Private function prototypes -----------------------------------------------*/
00060 /* Private functions ---------------------------------------------------------*/
00061
00062 /**
00063   * @brief   Main program.
00064   * @param  None
00065   * @retval None
00066   */
00067 int main(void)
00068 {
00069   /*!< At this stage the microcontroller clock setting is already configured,
00070        this is done through SystemInit() function which is called from startup
00071        file (startup_stm32f10x_xx.s) before to branch to application main.
00072        To reconfigure the default setting of SystemInit() function, refer to
00073        system_stm32f10x.c file
00074      */
00075
00076 /* Switch Thread mode Stack from Main to Process -----------------------------*/
00077   /* Initialize memory reserved for Process Stack */
00078   for(Index = 0; Index < SP_PROCESS_SIZE; Index++)
00079   {
00080     PSPMemAlloc[Index] = 0x00;
00081   }
00082
00083   /* Set Process stack value */
00084   __set_PSP((uint32_t)PSPMemAlloc + SP_PROCESS_SIZE);
00085
00086   /* Select Process Stack as Thread mode Stack */
00087   __set_CONTROL(SP_PROCESS);
00088
00089   /* Get the Thread mode stack used */
00090   if((__get_CONTROL() & 0x02) == SP_MAIN)
00091   {
00092     /* Main stack is used as the current stack */
00093     CurrentStack = SP_MAIN;
00094   }
00095   else
00096   {
00097     /* Process stack is used as the current stack */
00098     CurrentStack = SP_PROCESS;
00099
00100     /* Get process stack pointer value */
00101     PSPValue = __get_PSP();
00102   }
00103
00104 /* Switch Thread mode from privileged to unprivileged ------------------------*/
00105   /* Thread mode has unprivileged access */
00106   __set_CONTROL(THREAD_MODE_UNPRIVILEGED | SP_PROCESS);
00107
00108   /* Unprivileged access mainly affect ability to:
00109       - Use or not use certain instructions such as MSR fields
00110       - Access System Control Space (SCS) registers such as NVIC and SysTick */
00111
00112   /* Check Thread mode privilege status */
00113   if((__get_CONTROL() & 0x01) == THREAD_MODE_PRIVILEGED)
00114   {
00115     /* Thread mode has privileged access  */
00116     ThreadMode = THREAD_MODE_PRIVILEGED;
00117   }
00118   else
00119   {
00120     /* Thread mode has unprivileged access*/
00121     ThreadMode = THREAD_MODE_UNPRIVILEGED;
00122   }
00123
00124 /* Switch back Thread mode from unprivileged to privileged -------------------*/
00125   /* Try to switch back Thread mode to privileged (Not possible, this can be
00126      done only in Handler mode) */
00127   __set_CONTROL(THREAD_MODE_PRIVILEGED | SP_PROCESS);
00128
00129   /* Generate a system call exception, and in the ISR switch back Thread mode
00130     to privileged */
00131   __SVC();
00132
00133   /* Check Thread mode privilege status */
00134   if((__get_CONTROL() & 0x01) == THREAD_MODE_PRIVILEGED)
00135   {
00136     /* Thread mode has privileged access  */
00137     ThreadMode = THREAD_MODE_PRIVILEGED;
00138   }
00139   else
00140   {
00141     /* Thread mode has unprivileged access*/
00142     ThreadMode = THREAD_MODE_UNPRIVILEGED;
00143   }
00144
00145   while (1)
00146   {
00147   }
00148 }
00149
00150 #ifdef  USE_FULL_ASSERT
00151
00152 /**
00153   * @brief  Reports the name of the source file and the source line number
00154   *         where the assert_param error has occurred.
00155   * @param  file: pointer to the source file name
00156   * @param  line: assert_param error line source number
00157   * @retval None
00158   */
00159 void assert_failed(uint8_t* file, uint32_t line)
00160 {
00161   /* User can add his own implementation to report the file name and line number,
00162      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00163
00164   /* Infinite loop */
00165   while (1)
00166   {
00167   }
00168 }
00169
00170 #endif
00171
00172 /**
00173   * @}
00174   */
00175
00176 /**
00177   * @}
00178   */
00179
00180 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f10x_conf.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    CortexM3/Mode_Privilege/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052 /* Exported types ------------------------------------------------------------*/
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Uncomment the line below to expanse the "assert_param" macro in the
00055    Standard Peripheral Library drivers code */
00056 /* #define USE_FULL_ASSERT    1 */
00057
00058 /* Exported macro ------------------------------------------------------------*/
00059 #ifdef  USE_FULL_ASSERT
00060 /**
00061   * @brief  The assert_param macro is used for function's parameters check.
00062   * @param  expr: If expr is false, it calls assert_failed function which reports
00063   *         the name of the source file and the source line number of the call
00064   *         that failed. If expr is true, it returns no value.
00065   * @retval None
00066   */
00067   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00068 /* Exported functions ------------------------------------------------------- */
00069   void assert_failed(uint8_t* file, uint32_t line);
00070 #else
00071   #define assert_param(expr) ((void)0)
00072 #endif /* USE_FULL_ASSERT */
00073
00074 #endif /* __STM32F10x_CONF_H */
00075
00076 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f10x_it.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    CortexM3/Mode_Privilege/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and peripherals
00009   *          interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026
00027 /** @addtogroup STM32F10x_StdPeriph_Examples
00028   * @{
00029   */
00030
00031 /** @addtogroup CortexM3_Mode_Privilege
00032   * @{
00033   */
00034
00035 /* Private typedef -----------------------------------------------------------*/
00036 /* Private define ------------------------------------------------------------*/
00037 /* Private macro -------------------------------------------------------------*/
00038 /* Private variables ---------------------------------------------------------*/
00039 /* Private function prototypes -----------------------------------------------*/
00040 /* Private functions ---------------------------------------------------------*/
00041
00042 /******************************************************************************/
00043 /*            Cortex-M3 Processor Exceptions Handlers                         */
00044 /******************************************************************************/
00045
00046 /**
00047   * @brief  This function handles NMI exception.
00048   * @param  None
00049   * @retval None
00050   */
00051 void NMI_Handler(void)
00052 {
00053 }
00054
00055 /**
00056   * @brief  This function handles Hard Fault exception.
00057   * @param  None
00058   * @retval None
00059   */
00060 void HardFault_Handler(void)
00061 {
00062   /* Go to infinite loop when Hard Fault exception occurs */
00063   while (1)
00064   {
00065   }
00066 }
00067
00068 /**
00069   * @brief  This function handles Memory Manage exception.
00070   * @param  None
00071   * @retval None
00072   */
00073 void MemManage_Handler(void)
00074 {
00075   /* Go to infinite loop when Memory Manage exception occurs */
00076   while (1)
00077   {
00078   }
00079 }
00080
00081 /**
00082   * @brief  This function handles Bus Fault exception.
00083   * @param  None
00084   * @retval None
00085   */
00086 void BusFault_Handler(void)
00087 {
00088   /* Go to infinite loop when Bus Fault exception occurs */
00089   while (1)
00090   {
00091   }
00092 }
00093
00094 /**
00095   * @brief  This function handles Usage Fault exception.
00096   * @param  None
00097   * @retval None
00098   */
00099 void UsageFault_Handler(void)
00100 {
00101   /* Go to infinite loop when Usage Fault exception occurs */
00102   while (1)
00103   {
00104   }
00105 }
00106
00107 /**
00108   * @brief  This function handles Debug Monitor exception.
00109   * @param  None
00110   * @retval None
00111   */
00112 void DebugMon_Handler(void)
00113 {
00114 }
00115
00116 /**
00117   * @brief  This function handles SVCall exception.
00118   * @param  None
00119   * @retval None
00120   */
00121 void SVC_Handler(void)
00122 {
00123   /* Switch back Thread mode to privileged */
00124   __set_CONTROL(2);
00125 }
00126
00127 /**
00128   * @brief  This function handles PendSV_Handler exception.
00129   * @param  None
00130   * @retval None
00131   */
00132 void PendSV_Handler(void)
00133 {
00134 }
00135
00136 /**
00137   * @brief  This function handles SysTick Handler.
00138   * @param  None
00139   * @retval None
00140   */
00141 void SysTick_Handler(void)
00142 {
00143 }
00144
00145 /******************************************************************************/
00146 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00147 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00148 /*  available peripheral interrupt handler's name please refer to the startup */
00149 /*  file (startup_stm32f10x_xx.s).                                            */
00150 /******************************************************************************/
00151
00152 /**
00153   * @brief  This function handles PPP interrupt request.
00154   * @param  None
00155   * @retval None
00156   */
00157 /*void PPP_IRQHandler(void)
00158 {
00159 }*/
00160
00161 /**
00162   * @}
00163   */
00164
00165 /**
00166   * @}
00167   */
00168
00169 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f10x_it.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    CortexM3/Mode_Privilege/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043
00044 #endif /* __STM32F10x_IT_H */
00045
00046 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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STM32F10x_StdPeriph_Examples/CortexM3/MPU/main.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    CortexM3/MPU/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023
00024 #include "main.h"
00025 #include "stm32_eval.h"
00026
00027 /** @addtogroup STM32F10x_StdPeriph_Examples
00028   * @{
00029   */
00030
00031 /** @addtogroup CortexM3_MPU
00032   * @{
00033   */
00034
00035 /* Private typedef -----------------------------------------------------------*/
00036 /* Private define ------------------------------------------------------------*/
00037 #define ACCESS_PERMISSION
00038
00039 /* Private macro -------------------------------------------------------------*/
00040 /* Private variables ---------------------------------------------------------*/
00041 /* Private function prototypes -----------------------------------------------*/
00042 void MPU_SETUP(void);
00043
00044 /* Private functions ---------------------------------------------------------*/
00045 /**
00046   * @brief  Main program.
00047   * @param  None
00048   * @retval None
00049   */
00050 int main(void)
00051 {
00052
00053   /*!< At this stage the microcontroller clock setting is already configured,
00054        this is done through SystemInit() function which is called from startup
00055        file (startup_stm32f10x_xx.s) before to branch to application main.
00056        To reconfigure the default setting of SystemInit() function, refer to
00057        system_stm32f10x.c file
00058      */
00059
00060   /* Configure LED1 and LED2 */
00061   STM_EVAL_LEDInit(LED1);
00062   STM_EVAL_LEDInit(LED2);
00063
00064   /* Set MPU regions */
00065   MPU_SETUP();
00066
00067   #ifdef ACCESS_PERMISSION
00068     accesspermission();
00069   #endif
00070
00071   /* Infinite loop */
00072   while (1)
00073   {
00074     /* Turn On LED1 */
00075     STM_EVAL_LEDOn(LED1);
00076   }
00077 }
00078
00079 /**
00080   * @brief  Configures the main MPU regions.
00081   * @param  None
00082   * @retval None
00083   */
00084 void MPU_SETUP(void)
00085 {
00086   /* Disable MPU */
00087   MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
00088
00089   /* Configure RAM region as Region NÝ0, 8kB of size and R/W region */
00090   MPU->RNR  = RAM_REGION_NUMBER;
00091   MPU->RBAR = RAM_ADDRESS_START;
00092   MPU->RASR = RAM_SIZE | portMPU_REGION_READ_WRITE;
00093
00094   /* Configure FLASH region as REGION NÝ1, 1MB of size and R/W region */
00095   MPU->RNR  = FLASH_REGION_NUMBER;
00096   MPU->RBAR = FLASH_ADDRESS_START;
00097   MPU->RASR = FLASH_SIZE | portMPU_REGION_READ_WRITE;
00098
00099   /* Configure Peripheral region as REGION NÝ2, 0.5GB of size, R/W and Execute
00100   Never region */
00101   MPU->RNR  = PERIPH_REGION_NUMBER;
00102   MPU->RBAR = PERIPH_ADDRESS_START;
00103   MPU->RASR = PERIPH_SIZE |portMPU_REGION_READ_WRITE | MPU_RASR_XN_Msk;
00104
00105   /* Enable the memory fault exception */
00106   SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
00107
00108   /* Enable MPU */
00109   MPU->CTRL |= MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_ENABLE_Msk;
00110 }
00111
00112 #ifdef  USE_FULL_ASSERT
00113
00114 /**
00115   * @brief  Reports the name of the source file and the source line number
00116   *         where the assert_param error has occurred.
00117   * @param  file: pointer to the source file name
00118   * @param  line: assert_param error line source number
00119   * @retval None
00120   */
00121 void assert_failed(uint8_t* file, uint32_t line)
00122 {
00123   /* User can add his own implementation to report the file name and line number,
00124      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00125
00126   /* Infinite loop */
00127   while (1)
00128   {
00129   }
00130 }
00131 #endif
00132
00133 /**
00134   * @}
00135   */
00136
00137 /**
00138   * @}
00139   */
00140
00141 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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STM32F10x_StdPeriph_Examples/CortexM3/MPU/stm32f10x_conf.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    CortexM3/MPU/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052 /* Exported types ------------------------------------------------------------*/
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Uncomment the line below to expanse the "assert_param" macro in the
00055    Standard Peripheral Library drivers code */
00056 /* #define USE_FULL_ASSERT    1 */
00057
00058 /* Exported macro ------------------------------------------------------------*/
00059 #ifdef  USE_FULL_ASSERT
00060 /**
00061   * @brief  The assert_param macro is used for function's parameters check.
00062   * @param  expr: If expr is false, it calls assert_failed function which reports
00063   *         the name of the source file and the source line number of the call
00064   *         that failed. If expr is true, it returns no value.
00065   * @retval None
00066   */
00067   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00068 /* Exported functions ------------------------------------------------------- */
00069   void assert_failed(uint8_t* file, uint32_t line);
00070 #else
00071   #define assert_param(expr) ((void)0)
00072 #endif /* USE_FULL_ASSERT */
00073
00074 #endif /* __STM32F10x_CONF_H */
00075
00076 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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STM32F10x_StdPeriph_Examples/CortexM3/MPU/stm32f10x_it.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    CortexM3/MPU/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and peripherals
00009   *          interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026 #include "stm32_eval.h"
00027
00028 /** @addtogroup STM32F10x_StdPeriph_Examples
00029   * @{
00030   */
00031
00032 /** @addtogroup CortexM3_MPU
00033   * @{
00034   */
00035
00036 /* Private typedef -----------------------------------------------------------*/
00037 /* Private define ------------------------------------------------------------*/
00038 /* Private macro -------------------------------------------------------------*/
00039 /* Private variables ---------------------------------------------------------*/
00040 /* Private function prototypes -----------------------------------------------*/
00041 /* Private functions ---------------------------------------------------------*/
00042
00043 /******************************************************************************/
00044 /*            Cortex-M3 Processor Exceptions Handlers                         */
00045 /******************************************************************************/
00046
00047 /**
00048   * @brief  This function handles NMI exception.
00049   * @param  None
00050   * @retval None
00051   */
00052 void NMI_Handler(void)
00053 {
00054 }
00055
00056 /**
00057   * @brief  This function handles Hard Fault exception.
00058   * @param  None
00059   * @retval None
00060   */
00061 void HardFault_Handler(void)
00062 {
00063   /* Go to infinite loop when Hard Fault exception occurs */
00064   while (1)
00065   {
00066   }
00067 }
00068
00069 /**
00070   * @brief  This function handles Memory Manage exception.
00071   * @param  None
00072   * @retval None
00073   */
00074 void MemManage_Handler(void)
00075 {
00076   while (1)
00077   {
00078     /* Turn on LED2 */
00079     STM_EVAL_LEDOn(LED2);
00080   }
00081 }
00082
00083 /**
00084   * @brief  This function handles Bus Fault exception.
00085   * @param  None
00086   * @retval None
00087   */
00088 void BusFault_Handler(void)
00089 {
00090   /* Go to infinite loop when Bus Fault exception occurs */
00091   while (1)
00092   {
00093   }
00094 }
00095
00096 /**
00097   * @brief  This function handles Usage Fault exception.
00098   * @param  None
00099   * @retval None
00100   */
00101 void UsageFault_Handler(void)
00102 {
00103   /* Go to infinite loop when Usage Fault exception occurs */
00104   while (1)
00105   {
00106   }
00107 }
00108
00109 /**
00110   * @brief  This function handles Debug Monitor exception.
00111   * @param  None
00112   * @retval None
00113   */
00114 void DebugMon_Handler(void)
00115 {
00116 }
00117
00118 /**
00119   * @brief  This function handles SVCall exception.
00120   * @param  None
00121   * @retval None
00122   */
00123 void SVC_Handler(void)
00124 {
00125 }
00126
00127 /**
00128   * @brief  This function handles PendSV_Handler exception.
00129   * @param  None
00130   * @retval None
00131   */
00132 void PendSV_Handler(void)
00133 {
00134 }
00135
00136 /**
00137   * @brief  This function handles SysTick Handler.
00138   * @param  None
00139   * @retval None
00140   */
00141 void SysTick_Handler(void)
00142 {
00143 }
00144
00145 /******************************************************************************/
00146 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00147 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00148 /*  available peripheral interrupt handler's name please refer to the startup */
00149 /*  file (startup_stm32f10x_xx.s).                                            */
00150 /******************************************************************************/
00151
00152 /**
00153   * @brief  This function handles PPP interrupt request.
00154   * @param  None
00155   * @retval None
00156   */
00157 /*void PPP_IRQHandler(void)
00158 {
00159 }*/
00160
00161 /**
00162   * @}
00163   */
00164
00165 /**
00166   * @}
00167   */
00168
00169 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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STM32F10x_StdPeriph_Examples/CortexM3/MPU/stm32f10x_it.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    CortexM3/MPU/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043
00044 #endif /* __STM32F10x_IT_H */
00045
00046 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/main.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    CRC/CRC_Calculation/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x.h"
00024
00025 /** @addtogroup STM32F10x_StdPeriph_Examples
00026   * @{
00027   */
00028
00029 /** @addtogroup CRC_Calculation
00030   * @{
00031   */
00032
00033 /* Private typedef -----------------------------------------------------------*/
00034 /* Private define ------------------------------------------------------------*/
00035 #define BUFFER_SIZE    114
00036
00037 /* Private macro -------------------------------------------------------------*/
00038 /* Private variables ---------------------------------------------------------*/
00039 static const uint32_t DataBuffer[BUFFER_SIZE] =
00040   {
00041     0x00001021, 0x20423063, 0x408450a5, 0x60c670e7, 0x9129a14a, 0xb16bc18c,
00042     0xd1ade1ce, 0xf1ef1231, 0x32732252, 0x52b54294, 0x72f762d6, 0x93398318,
00043     0xa35ad3bd, 0xc39cf3ff, 0xe3de2462, 0x34430420, 0x64e674c7, 0x44a45485,
00044     0xa56ab54b, 0x85289509, 0xf5cfc5ac, 0xd58d3653, 0x26721611, 0x063076d7,
00045     0x569546b4, 0xb75ba77a, 0x97198738, 0xf7dfe7fe, 0xc7bc48c4, 0x58e56886,
00046     0x78a70840, 0x18612802, 0xc9ccd9ed, 0xe98ef9af, 0x89489969, 0xa90ab92b,
00047     0x4ad47ab7, 0x6a961a71, 0x0a503a33, 0x2a12dbfd, 0xfbbfeb9e, 0x9b798b58,
00048     0xbb3bab1a, 0x6ca67c87, 0x5cc52c22, 0x3c030c60, 0x1c41edae, 0xfd8fcdec,
00049     0xad2abd0b, 0x8d689d49, 0x7e976eb6, 0x5ed54ef4, 0x2e321e51, 0x0e70ff9f,
00050     0xefbedfdd, 0xcffcbf1b, 0x9f598f78, 0x918881a9, 0xb1caa1eb, 0xd10cc12d,
00051     0xe16f1080, 0x00a130c2, 0x20e35004, 0x40257046, 0x83b99398, 0xa3fbb3da,
00052     0xc33dd31c, 0xe37ff35e, 0x129022f3, 0x32d24235, 0x52146277, 0x7256b5ea,
00053     0x95a88589, 0xf56ee54f, 0xd52cc50d, 0x34e224c3, 0x04817466, 0x64475424,
00054     0x4405a7db, 0xb7fa8799, 0xe75ff77e, 0xc71dd73c, 0x26d336f2, 0x069116b0,
00055     0x76764615, 0x5634d94c, 0xc96df90e, 0xe92f99c8, 0xb98aa9ab, 0x58444865,
00056     0x78066827, 0x18c008e1, 0x28a3cb7d, 0xdb5ceb3f, 0xfb1e8bf9, 0x9bd8abbb,
00057     0x4a755a54, 0x6a377a16, 0x0af11ad0, 0x2ab33a92, 0xed0fdd6c, 0xcd4dbdaa,
00058     0xad8b9de8, 0x8dc97c26, 0x5c644c45, 0x3ca22c83, 0x1ce00cc1, 0xef1fff3e,
00059     0xdf7caf9b, 0xbfba8fd9, 0x9ff86e17, 0x7e364e55, 0x2e933eb2, 0x0ed11ef0
00060   };
00061
00062 __IO uint32_t CRCValue = 0;
00063
00064 /* Private function prototypes -----------------------------------------------*/
00065 void Delay(__IO uint32_t nCount);
00066
00067 /* Private functions ---------------------------------------------------------*/
00068
00069 /**
00070   * @brief  Main program.
00071   * @param  None
00072   * @retval None
00073   */
00074 int main(void)
00075 {
00076   /*!< At this stage the microcontroller clock setting is already configured,
00077        this is done through SystemInit() function which is called from startup
00078        file (startup_stm32f10x_xx.s) before to branch to application main.
00079        To reconfigure the default setting of SystemInit() function, refer to
00080        system_stm32f10x.c file
00081      */
00082
00083   /* Enable CRC clock */
00084   RCC_AHBPeriphClockCmd(RCC_AHBPeriph_CRC, ENABLE);
00085
00086   /* Compute the CRC of "DataBuffer" */
00087   CRCValue = CRC_CalcBlockCRC((uint32_t *)DataBuffer, BUFFER_SIZE);
00088
00089   while (1)
00090   {
00091   }
00092 }
00093
00094 /**
00095   * @brief  Inserts a delay time.
00096   * @param  nCount: specifies the delay time length.
00097   * @retval None
00098   */
00099 void Delay(__IO uint32_t nCount)
00100 {
00101   for(; nCount != 0; nCount--);
00102 }
00103
00104 #ifdef  USE_FULL_ASSERT
00105
00106 /**
00107   * @brief  Reports the name of the source file and the source line number
00108   *         where the assert_param error has occurred.
00109   * @param  file: pointer to the source file name
00110   * @param  line: assert_param error line source number
00111   * @retval None
00112   */
00113 void assert_failed(uint8_t* file, uint32_t line)
00114 {
00115   /* User can add his own implementation to report the file name and line number,
00116      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00117
00118   /* Infinite loop */
00119   while (1)
00120   {
00121   }
00122 }
00123
00124 #endif
00125
00126 /**
00127   * @}
00128   */
00129
00130 /**
00131   * @}
00132   */
00133
00134 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/stm32f10x_conf.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    CRC/CRC_Calculation/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052 /* Exported types ------------------------------------------------------------*/
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Uncomment the line below to expanse the "assert_param" macro in the
00055    Standard Peripheral Library drivers code */
00056 /* #define USE_FULL_ASSERT    1 */
00057
00058 /* Exported macro ------------------------------------------------------------*/
00059 #ifdef  USE_FULL_ASSERT
00060
00061 /**
00062   * @brief  The assert_param macro is used for function's parameters check.
00063   * @param  expr: If expr is false, it calls assert_failed function which reports
00064   *         the name of the source file and the source line number of the call
00065   *         that failed. If expr is true, it returns no value.
00066   * @retval None
00067   */
00068   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00069 /* Exported functions ------------------------------------------------------- */
00070   void assert_failed(uint8_t* file, uint32_t line);
00071 #else
00072   #define assert_param(expr) ((void)0)
00073 #endif /* USE_FULL_ASSERT */
00074
00075 #endif /* __STM32F10x_CONF_H */
00076
00077 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/stm32f10x_it.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    CRC/CRC_Calculation/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and peripherals
00009   *          interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026
00027 /** @addtogroup STM32F10x_StdPeriph_Examples
00028   * @{
00029   */
00030
00031 /** @addtogroup CRC_Calculation
00032   * @{
00033   */
00034
00035 /* Private typedef -----------------------------------------------------------*/
00036 /* Private define ------------------------------------------------------------*/
00037 /* Private macro -------------------------------------------------------------*/
00038 /* Private variables ---------------------------------------------------------*/
00039 /* Private function prototypes -----------------------------------------------*/
00040 /* Private functions ---------------------------------------------------------*/
00041
00042 /******************************************************************************/
00043 /*            Cortex-M3 Processor Exceptions Handlers                         */
00044 /******************************************************************************/
00045
00046 /**
00047   * @brief  This function handles NMI exception.
00048   * @param  None
00049   * @retval None
00050   */
00051 void NMI_Handler(void)
00052 {
00053 }
00054
00055 /**
00056   * @brief  This function handles Hard Fault exception.
00057   * @param  None
00058   * @retval None
00059   */
00060 void HardFault_Handler(void)
00061 {
00062   /* Go to infinite loop when Hard Fault exception occurs */
00063   while (1)
00064   {
00065   }
00066 }
00067
00068 /**
00069   * @brief  This function handles Memory Manage exception.
00070   * @param  None
00071   * @retval None
00072   */
00073 void MemManage_Handler(void)
00074 {
00075   /* Go to infinite loop when Memory Manage exception occurs */
00076   while (1)
00077   {
00078   }
00079 }
00080
00081 /**
00082   * @brief  This function handles Bus Fault exception.
00083   * @param  None
00084   * @retval None
00085   */
00086 void BusFault_Handler(void)
00087 {
00088   /* Go to infinite loop when Bus Fault exception occurs */
00089   while (1)
00090   {
00091   }
00092 }
00093
00094 /**
00095   * @brief  This function handles Usage Fault exception.
00096   * @param  None
00097   * @retval None
00098   */
00099 void UsageFault_Handler(void)
00100 {
00101   /* Go to infinite loop when Usage Fault exception occurs */
00102   while (1)
00103   {
00104   }
00105 }
00106
00107 /**
00108   * @brief  This function handles SVCall exception.
00109   * @param  None
00110   * @retval None
00111   */
00112 void SVC_Handler(void)
00113 {
00114 }
00115
00116 /**
00117   * @brief  This function handles Debug Monitor exception.
00118   * @param  None
00119   * @retval None
00120   */
00121 void DebugMon_Handler(void)
00122 {
00123 }
00124
00125 /**
00126   * @brief  This function handles PendSV_Handler exception.
00127   * @param  None
00128   * @retval None
00129   */
00130 void PendSV_Handler(void)
00131 {
00132 }
00133
00134 /**
00135   * @brief  This function handles SysTick Handler.
00136   * @param  None
00137   * @retval None
00138   */
00139 void SysTick_Handler(void)
00140 {
00141 }
00142
00143 /******************************************************************************/
00144 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00145 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00146 /*  available peripheral interrupt handler's name please refer to the startup */
00147 /*  file (startup_stm32f10x_xx.s).                                            */
00148 /******************************************************************************/
00149
00150 /**
00151   * @brief  This function handles PPP interrupt request.
00152   * @param  None
00153   * @retval None
00154   */
00155 /*void PPP_IRQHandler(void)
00156 {
00157 }*/
00158
00159 /**
00160   * @}
00161   */
00162
00163 /**
00164   * @}
00165   */
00166
00167 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/stm32f10x_it.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    CRC/CRC_Calculation/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043
00044 #endif /* __STM32F10x_IT_H */
00045
00046 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/main.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    DAC/DualModeDMA_SineWave/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x.h"
00024
00025 /** @addtogroup STM32F10x_StdPeriph_Examples
00026   * @{
00027   */
00028
00029 /** @addtogroup DAC_DualModeDMA_SineWave
00030   * @{
00031   */
00032
00033 /* Private typedef -----------------------------------------------------------*/
00034 /* Private define ------------------------------------------------------------*/
00035 #define DAC_DHR12RD_Address      0x40007420
00036
00037 /* Init Structure definition */
00038 DAC_InitTypeDef            DAC_InitStructure;
00039 DMA_InitTypeDef            DMA_InitStructure;
00040 TIM_TimeBaseInitTypeDef    TIM_TimeBaseStructure;
00041 uint32_t Idx = 0;
00042
00043 /* Private macro -------------------------------------------------------------*/
00044 /* Private variables ---------------------------------------------------------*/
00045 const uint16_t Sine12bit[32] = {
00046                       2047, 2447, 2831, 3185, 3498, 3750, 3939, 4056, 4095, 4056,
00047                       3939, 3750, 3495, 3185, 2831, 2447, 2047, 1647, 1263, 909,
00048                       599, 344, 155, 38, 0, 38, 155, 344, 599, 909, 1263, 1647};
00049
00050 uint32_t DualSine12bit[32];
00051
00052 /* Private function prototypes -----------------------------------------------*/
00053 void RCC_Configuration(void);
00054 void GPIO_Configuration(void);
00055 void Delay(__IO uint32_t nCount);
00056
00057 /* Private functions ---------------------------------------------------------*/
00058
00059 /**
00060   * @brief   Main program.
00061   * @param  None
00062   * @retval None
00063   */
00064 int main(void)
00065 {
00066   /*!< At this stage the microcontroller clock setting is already configured,
00067        this is done through SystemInit() function which is called from startup
00068        file (startup_stm32f10x_xx.s) before to branch to application main.
00069        To reconfigure the default setting of SystemInit() function, refer to
00070        system_stm32f10x.c file
00071      */
00072
00073
00074   /* System Clocks Configuration */
00075   RCC_Configuration();
00076
00077   /* Once the DAC channel is enabled, the corresponding GPIO pin is automatically
00078      connected to the DAC converter. In order to avoid parasitic consumption,
00079      the GPIO pin should be configured in analog */
00080   GPIO_Configuration();
00081
00082   /* TIM2 Configuration */
00083   /* Time base configuration */
00084   TIM_TimeBaseStructInit(&TIM_TimeBaseStructure);
00085   TIM_TimeBaseStructure.TIM_Period = 0x19;
00086   TIM_TimeBaseStructure.TIM_Prescaler = 0x0;
00087   TIM_TimeBaseStructure.TIM_ClockDivision = 0x0;
00088   TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
00089   TIM_TimeBaseInit(TIM2, &TIM_TimeBaseStructure);
00090
00091   /* TIM2 TRGO selection */
00092   TIM_SelectOutputTrigger(TIM2, TIM_TRGOSource_Update);
00093
00094   /* DAC channel1 Configuration */
00095   DAC_InitStructure.DAC_Trigger = DAC_Trigger_T2_TRGO;
00096   DAC_InitStructure.DAC_WaveGeneration = DAC_WaveGeneration_None;
00097   DAC_InitStructure.DAC_OutputBuffer = DAC_OutputBuffer_Disable;
00098   DAC_Init(DAC_Channel_1, &DAC_InitStructure);
00099
00100   /* DAC channel2 Configuration */
00101   DAC_Init(DAC_Channel_2, &DAC_InitStructure);
00102
00103   /* Fill Sine32bit table */
00104   for (Idx = 0; Idx < 32; Idx++)
00105   {
00106     DualSine12bit[Idx] = (Sine12bit[Idx] << 16) + (Sine12bit[Idx]);
00107   }
00108
00109 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL
00110   /* DMA2 channel4 configuration */
00111   DMA_DeInit(DMA2_Channel4);
00112 #else
00113   /* DMA1 channel4 configuration */
00114   DMA_DeInit(DMA1_Channel4);
00115 #endif
00116   DMA_InitStructure.DMA_PeripheralBaseAddr = DAC_DHR12RD_Address;
00117   DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)&DualSine12bit;
00118   DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
00119   DMA_InitStructure.DMA_BufferSize = 32;
00120   DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
00121   DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
00122   DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Word;
00123   DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Word;
00124   DMA_InitStructure.DMA_Mode = DMA_Mode_Circular;
00125   DMA_InitStructure.DMA_Priority = DMA_Priority_High;
00126   DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
00127
00128 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL
00129   DMA_Init(DMA2_Channel4, &DMA_InitStructure);
00130   /* Enable DMA2 Channel4 */
00131   DMA_Cmd(DMA2_Channel4, ENABLE);
00132 #else
00133   DMA_Init(DMA1_Channel4, &DMA_InitStructure);
00134   /* Enable DMA1 Channel4 */
00135   DMA_Cmd(DMA1_Channel4, ENABLE);
00136 #endif
00137
00138   /* Enable DAC Channel1: Once the DAC channel1 is enabled, PA.04 is
00139      automatically connected to the DAC converter. */
00140   DAC_Cmd(DAC_Channel_1, ENABLE);
00141   /* Enable DAC Channel2: Once the DAC channel2 is enabled, PA.05 is
00142      automatically connected to the DAC converter. */
00143   DAC_Cmd(DAC_Channel_2, ENABLE);
00144
00145   /* Enable DMA for DAC Channel2 */
00146   DAC_DMACmd(DAC_Channel_2, ENABLE);
00147
00148   /* TIM2 enable counter */
00149   TIM_Cmd(TIM2, ENABLE);
00150
00151   while (1)
00152   {
00153   }
00154 }
00155
00156
00157 /**
00158   * @brief  Configures the different system clocks.
00159   * @param  None
00160   * @retval None
00161   */
00162 void RCC_Configuration(void)
00163 {
00164   /* Enable peripheral clocks ------------------------------------------------*/
00165 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL
00166   /* DMA2 clock enable */
00167   RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA2, ENABLE);
00168 #else
00169   /* DMA1 clock enable */
00170   RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE);
00171 #endif
00172   /* GPIOA Periph clock enable */
00173   RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);
00174   /* DAC Periph clock enable */
00175   RCC_APB1PeriphClockCmd(RCC_APB1Periph_DAC, ENABLE);
00176   /* TIM2 Periph clock enable */
00177   RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2, ENABLE);
00178 }
00179
00180
00181 /**
00182   * @brief  Configures the different GPIO ports.
00183   * @param  None
00184   * @retval None
00185   */
00186 void GPIO_Configuration(void)
00187 {
00188   GPIO_InitTypeDef GPIO_InitStructure;
00189
00190   /* Once the DAC channel is enabled, the corresponding GPIO pin is automatically
00191      connected to the DAC converter. In order to avoid parasitic consumption,
00192      the GPIO pin should be configured in analog */
00193   GPIO_InitStructure.GPIO_Pin =  GPIO_Pin_4 | GPIO_Pin_5;
00194   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AIN;
00195   GPIO_Init(GPIOA, &GPIO_InitStructure);
00196 }
00197
00198 /**
00199   * @brief  Inserts a delay time.
00200   * @param  nCount: specifies the delay time length.
00201   * @retval None
00202   */
00203 void Delay(__IO uint32_t nCount)
00204 {
00205   for(; nCount != 0; nCount--);
00206 }
00207
00208 #ifdef  USE_FULL_ASSERT
00209
00210 /**
00211   * @brief  Reports the name of the source file and the source line number
00212   *         where the assert_param error has occurred.
00213   * @param  file: pointer to the source file name
00214   * @param  line: assert_param error line source number
00215   * @retval None
00216   */
00217 void assert_failed(uint8_t* file, uint32_t line)
00218 {
00219   /* User can add his own implementation to report the file name and line number,
00220      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00221
00222   /* Infinite loop */
00223   while (1)
00224   {
00225   }
00226 }
00227
00228 #endif
00229
00230 /**
00231   * @}
00232   */
00233
00234 /**
00235   * @}
00236   */
00237
00238 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/stm32f10x_conf.h

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00001 /**
00002   ******************************************************************************
00003   * @file    DAC/DualModeDMA_SineWave/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052 /* Exported types ------------------------------------------------------------*/
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Uncomment the line below to expanse the "assert_param" macro in the
00055    Standard Peripheral Library drivers code */
00056 /* #define USE_FULL_ASSERT    1 */
00057
00058 /* Exported macro ------------------------------------------------------------*/
00059 #ifdef  USE_FULL_ASSERT
00060
00061 /**
00062   * @brief  The assert_param macro is used for function's parameters check.
00063   * @param  expr: If expr is false, it calls assert_failed function which reports
00064   *         the name of the source file and the source line number of the call
00065   *         that failed. If expr is true, it returns no value.
00066   * @retval None
00067   */
00068   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00069 /* Exported functions ------------------------------------------------------- */
00070   void assert_failed(uint8_t* file, uint32_t line);
00071 #else
00072   #define assert_param(expr) ((void)0)
00073 #endif /* USE_FULL_ASSERT */
00074
00075 #endif /* __STM32F10x_CONF_H */
00076
00077 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/stm32f10x_it.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    DAC/DualModeDMA_SineWave/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and peripherals
00009   *          interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026
00027 /** @addtogroup STM32F10x_StdPeriph_Examples
00028   * @{
00029   */
00030
00031 /** @addtogroup DAC_DualModeDMA_SineWave
00032   * @{
00033   */
00034
00035 /* Private typedef -----------------------------------------------------------*/
00036 /* Private define ------------------------------------------------------------*/
00037 /* Private macro -------------------------------------------------------------*/
00038 /* Private variables ---------------------------------------------------------*/
00039 /* Private function prototypes -----------------------------------------------*/
00040 /* Private functions ---------------------------------------------------------*/
00041
00042 /******************************************************************************/
00043 /*            Cortex-M3 Processor Exceptions Handlers                         */
00044 /******************************************************************************/
00045
00046 /**
00047   * @brief  This function handles NMI exception.
00048   * @param  None
00049   * @retval None
00050   */
00051 void NMI_Handler(void)
00052 {
00053 }
00054
00055 /**
00056   * @brief  This function handles Hard Fault exception.
00057   * @param  None
00058   * @retval None
00059   */
00060 void HardFault_Handler(void)
00061 {
00062   /* Go to infinite loop when Hard Fault exception occurs */
00063   while (1)
00064   {
00065   }
00066 }
00067
00068 /**
00069   * @brief  This function handles Memory Manage exception.
00070   * @param  None
00071   * @retval None
00072   */
00073 void MemManage_Handler(void)
00074 {
00075   /* Go to infinite loop when Memory Manage exception occurs */
00076   while (1)
00077   {
00078   }
00079 }
00080
00081 /**
00082   * @brief  This function handles Bus Fault exception.
00083   * @param  None
00084   * @retval None
00085   */
00086 void BusFault_Handler(void)
00087 {
00088   /* Go to infinite loop when Bus Fault exception occurs */
00089   while (1)
00090   {
00091   }
00092 }
00093
00094 /**
00095   * @brief  This function handles Usage Fault exception.
00096   * @param  None
00097   * @retval None
00098   */
00099 void UsageFault_Handler(void)
00100 {
00101   /* Go to infinite loop when Usage Fault exception occurs */
00102   while (1)
00103   {
00104   }
00105 }
00106
00107 /**
00108   * @brief  This function handles SVCall exception.
00109   * @param  None
00110   * @retval None
00111   */
00112 void SVC_Handler(void)
00113 {
00114 }
00115
00116 /**
00117   * @brief  This function handles Debug Monitor exception.
00118   * @param  None
00119   * @retval None
00120   */
00121 void DebugMon_Handler(void)
00122 {
00123 }
00124
00125 /**
00126   * @brief  This function handles PendSV_Handler exception.
00127   * @param  None
00128   * @retval None
00129   */
00130 void PendSV_Handler(void)
00131 {
00132 }
00133
00134 /**
00135   * @brief  This function handles SysTick Handler.
00136   * @param  None
00137   * @retval None
00138   */
00139 void SysTick_Handler(void)
00140 {
00141 }
00142
00143 /******************************************************************************/
00144 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00145 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00146 /*  available peripheral interrupt handler's name please refer to the startup */
00147 /*  file (startup_stm32f10x_xx.s).                                            */
00148 /******************************************************************************/
00149
00150 /**
00151   * @brief  This function handles PPP interrupt request.
00152   * @param  None
00153   * @retval None
00154   */
00155 /*void PPP_IRQHandler(void)
00156 {
00157 }*/
00158
00159 /**
00160   * @}
00161   */
00162
00163 /**
00164   * @}
00165   */
00166
00167 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/stm32f10x_it.h

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00001 /**
00002   ******************************************************************************
00003   * @file    DAC/DualModeDMA_SineWave/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043
00044 #endif /* __STM32F10x_IT_H */
00045
00046 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/main.c

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00001 /**
00002   ******************************************************************************
00003   * @file    DAC/OneChannel_NoiseWave/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x.h"
00024
00025 /** @addtogroup STM32F10x_StdPeriph_Examples
00026   * @{
00027   */
00028
00029 /** @addtogroup DAC_OneChannel_NoiseWave
00030   * @{
00031   */
00032
00033 /* Private typedef -----------------------------------------------------------*/
00034 /* Private define ------------------------------------------------------------*/
00035 /* Init Structure definition */
00036 DAC_InitTypeDef            DAC_InitStructure;
00037
00038 /* Private macro -------------------------------------------------------------*/
00039 /* Private variables ---------------------------------------------------------*/
00040 /* Private function prototypes -----------------------------------------------*/
00041 void RCC_Configuration(void);
00042 void GPIO_Configuration(void);
00043 void Delay(__IO uint32_t nCount);
00044
00045 /* Private functions ---------------------------------------------------------*/
00046
00047 /**
00048   * @brief   Main program.
00049   * @param  None
00050   * @retval None
00051   */
00052 int main(void)
00053 {
00054   /*!< At this stage the microcontroller clock setting is already configured,
00055        this is done through SystemInit() function which is called from startup
00056        file (startup_stm32f10x_xx.s) before to branch to application main.
00057        To reconfigure the default setting of SystemInit() function, refer to
00058        system_stm32f10x.c file
00059      */
00060
00061   /* System Clocks Configuration */
00062   RCC_Configuration();
00063
00064   /* Once the DAC channel is enabled, the corresponding GPIO pin is automatically
00065      connected to the DAC converter. In order to avoid parasitic consumption,
00066      the GPIO pin should be configured in analog */
00067   GPIO_Configuration();
00068
00069   /* DAC channel1 Configuration */
00070   DAC_InitStructure.DAC_Trigger = DAC_Trigger_Software;
00071   DAC_InitStructure.DAC_WaveGeneration = DAC_WaveGeneration_Noise;
00072   DAC_InitStructure.DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bits8_0;
00073   DAC_InitStructure.DAC_OutputBuffer = DAC_OutputBuffer_Enable;
00074   DAC_Init(DAC_Channel_1, &DAC_InitStructure);
00075
00076   /* Enable DAC Channel1: Once the DAC channel1 is enabled, PA.04 is
00077      automatically connected to the DAC converter. */
00078   DAC_Cmd(DAC_Channel_1, ENABLE);
00079
00080   /* Set DAC Channel1 DHR12L register */
00081   DAC_SetChannel1Data(DAC_Align_12b_L, 0x7FF0);
00082
00083   while (1)
00084   {
00085     /* Start DAC Channel1 conversion by software */
00086     DAC_SoftwareTriggerCmd(DAC_Channel_1, ENABLE);
00087   }
00088 }
00089
00090 /**
00091   * @brief  Configures the different system clocks.
00092   * @param  None
00093   * @retval None
00094   */
00095 void RCC_Configuration(void)
00096 {
00097   /* Enable peripheral clocks ------------------------------------------------*/
00098   /* GPIOA Periph clock enable */
00099   RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);
00100   /* DAC Periph clock enable */
00101   RCC_APB1PeriphClockCmd(RCC_APB1Periph_DAC, ENABLE);
00102 }
00103
00104 /**
00105   * @brief  Configures the different GPIO ports.
00106   * @param  None
00107   * @retval None
00108   */
00109 void GPIO_Configuration(void)
00110 {
00111   GPIO_InitTypeDef GPIO_InitStructure;
00112
00113   /* Once the DAC channel is enabled, the corresponding GPIO pin is automatically
00114      connected to the DAC converter. In order to avoid parasitic consumption,
00115      the GPIO pin should be configured in analog */
00116   GPIO_InitStructure.GPIO_Pin =  GPIO_Pin_4;
00117   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AIN;
00118   GPIO_Init(GPIOA, &GPIO_InitStructure);
00119 }
00120
00121 /**
00122   * @brief  Inserts a delay time.
00123   * @param  nCount: specifies the delay time length.
00124   * @retval None
00125   */
00126 void Delay(__IO uint32_t nCount)
00127 {
00128   for(; nCount != 0; nCount--);
00129 }
00130
00131 #ifdef  USE_FULL_ASSERT
00132
00133 /**
00134   * @brief  Reports the name of the source file and the source line number
00135   *         where the assert_param error has occurred.
00136   * @param  file: pointer to the source file name
00137   * @param  line: assert_param error line source number
00138   * @retval None
00139   */
00140 void assert_failed(uint8_t* file, uint32_t line)
00141 {
00142   /* User can add his own implementation to report the file name and line number,
00143      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00144
00145   /* Infinite loop */
00146   while (1)
00147   {
00148   }
00149 }
00150
00151 #endif
00152
00153 /**
00154   * @}
00155   */
00156
00157 /**
00158   * @}
00159   */
00160
00161 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/stm32f10x_conf.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    DAC/OneChannel_NoiseWave/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052 /* Exported types ------------------------------------------------------------*/
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Uncomment the line below to expanse the "assert_param" macro in the
00055    Standard Peripheral Library drivers code */
00056 /* #define USE_FULL_ASSERT    1 */
00057
00058 /* Exported macro ------------------------------------------------------------*/
00059 #ifdef  USE_FULL_ASSERT
00060
00061 /**
00062   * @brief  The assert_param macro is used for function's parameters check.
00063   * @param  expr: If expr is false, it calls assert_failed function which reports
00064   *         the name of the source file and the source line number of the call
00065   *         that failed. If expr is true, it returns no value.
00066   * @retval None
00067   */
00068   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00069 /* Exported functions ------------------------------------------------------- */
00070   void assert_failed(uint8_t* file, uint32_t line);
00071 #else
00072   #define assert_param(expr) ((void)0)
00073 #endif /* USE_FULL_ASSERT */
00074
00075 #endif /* __STM32F10x_CONF_H */
00076
00077 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/stm32f10x_it.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    DAC/OneChannel_NoiseWave/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and peripherals
00009   *          interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026
00027 /** @addtogroup STM32F10x_StdPeriph_Examples
00028   * @{
00029   */
00030
00031 /** @addtogroup DAC_OneChannel_NoiseWave
00032   * @{
00033   */
00034
00035 /* Private typedef -----------------------------------------------------------*/
00036 /* Private define ------------------------------------------------------------*/
00037 /* Private macro -------------------------------------------------------------*/
00038 /* Private variables ---------------------------------------------------------*/
00039 /* Private function prototypes -----------------------------------------------*/
00040 /* Private functions ---------------------------------------------------------*/
00041
00042 /******************************************************************************/
00043 /*            Cortex-M3 Processor Exceptions Handlers                         */
00044 /******************************************************************************/
00045
00046 /**
00047   * @brief  This function handles NMI exception.
00048   * @param  None
00049   * @retval None
00050   */
00051 void NMI_Handler(void)
00052 {
00053 }
00054
00055 /**
00056   * @brief  This function handles Hard Fault exception.
00057   * @param  None
00058   * @retval None
00059   */
00060 void HardFault_Handler(void)
00061 {
00062   /* Go to infinite loop when Hard Fault exception occurs */
00063   while (1)
00064   {
00065   }
00066 }
00067
00068 /**
00069   * @brief  This function handles Memory Manage exception.
00070   * @param  None
00071   * @retval None
00072   */
00073 void MemManage_Handler(void)
00074 {
00075   /* Go to infinite loop when Memory Manage exception occurs */
00076   while (1)
00077   {
00078   }
00079 }
00080
00081 /**
00082   * @brief  This function handles Bus Fault exception.
00083   * @param  None
00084   * @retval None
00085   */
00086 void BusFault_Handler(void)
00087 {
00088   /* Go to infinite loop when Bus Fault exception occurs */
00089   while (1)
00090   {
00091   }
00092 }
00093
00094 /**
00095   * @brief  This function handles Usage Fault exception.
00096   * @param  None
00097   * @retval None
00098   */
00099 void UsageFault_Handler(void)
00100 {
00101   /* Go to infinite loop when Usage Fault exception occurs */
00102   while (1)
00103   {
00104   }
00105 }
00106
00107 /**
00108   * @brief  This function handles SVCall exception.
00109   * @param  None
00110   * @retval None
00111   */
00112 void SVC_Handler(void)
00113 {
00114 }
00115
00116 /**
00117   * @brief  This function handles Debug Monitor exception.
00118   * @param  None
00119   * @retval None
00120   */
00121 void DebugMon_Handler(void)
00122 {
00123 }
00124
00125 /**
00126   * @brief  This function handles PendSV_Handler exception.
00127   * @param  None
00128   * @retval None
00129   */
00130 void PendSV_Handler(void)
00131 {
00132 }
00133
00134 /**
00135   * @brief  This function handles SysTick Handler.
00136   * @param  None
00137   * @retval None
00138   */
00139 void SysTick_Handler(void)
00140 {
00141 }
00142
00143 /******************************************************************************/
00144 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00145 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00146 /*  available peripheral interrupt handler's name please refer to the startup */
00147 /*  file (startup_stm32f10x_xx.s).                                            */
00148 /******************************************************************************/
00149
00150 /**
00151   * @brief  This function handles PPP interrupt request.
00152   * @param  None
00153   * @retval None
00154   */
00155 /*void PPP_IRQHandler(void)
00156 {
00157 }*/
00158
00159 /**
00160   * @}
00161   */
00162
00163 /**
00164   * @}
00165   */
00166
00167 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/stm32f10x_it.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    DAC/OneChannel_NoiseWave/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043
00044 #endif /* __STM32F10x_IT_H */
00045
00046 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/main.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    DAC/OneChannelDMA_Escalator/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x.h"
00024
00025 /** @addtogroup STM32F10x_StdPeriph_Examples
00026   * @{
00027   */
00028
00029 /** @addtogroup DAC_OneChannelDMA_Escalator
00030   * @{
00031   */
00032
00033 /* Private typedef -----------------------------------------------------------*/
00034 /* Private define ------------------------------------------------------------*/
00035 #define DAC_DHR8R1_Address      0x40007410
00036
00037 /* Init Structure definition */
00038 DAC_InitTypeDef            DAC_InitStructure;
00039 DMA_InitTypeDef            DMA_InitStructure;
00040
00041 /* Private macro -------------------------------------------------------------*/
00042 /* Private variables ---------------------------------------------------------*/
00043 const uint8_t Escalator8bit[6] = {0x0, 0x33, 0x66, 0x99, 0xCC, 0xFF};
00044
00045 /* Private function prototypes -----------------------------------------------*/
00046 void RCC_Configuration(void);
00047 void GPIO_Configuration(void);
00048 void Delay(__IO uint32_t nCount);
00049
00050 /* Private functions ---------------------------------------------------------*/
00051
00052 /**
00053   * @brief   Main program.
00054   * @param  None
00055   * @retval None
00056   */
00057 int main(void)
00058 {
00059   /*!< At this stage the microcontroller clock setting is already configured,
00060        this is done through SystemInit() function which is called from startup
00061        file (startup_stm32f10x_xx.s) before to branch to application main.
00062        To reconfigure the default setting of SystemInit() function, refer to
00063        system_stm32f10x.c file
00064      */
00065
00066   /* System Clocks Configuration */
00067   RCC_Configuration();
00068
00069   /* Once the DAC channel is enabled, the corresponding GPIO pin is automatically
00070      connected to the DAC converter. In order to avoid parasitic consumption,
00071      the GPIO pin should be configured in analog */
00072   GPIO_Configuration();
00073
00074   /* TIM6 Configuration */
00075   TIM_PrescalerConfig(TIM6, 0xF, TIM_PSCReloadMode_Update);
00076   TIM_SetAutoreload(TIM6, 0xFF);
00077   /* TIM6 TRGO selection */
00078   TIM_SelectOutputTrigger(TIM6, TIM_TRGOSource_Update);
00079
00080   /* DAC channel1 Configuration */
00081   DAC_InitStructure.DAC_Trigger = DAC_Trigger_T6_TRGO;
00082   DAC_InitStructure.DAC_WaveGeneration = DAC_WaveGeneration_None;
00083   DAC_InitStructure.DAC_OutputBuffer = DAC_OutputBuffer_Disable;
00084   DAC_Init(DAC_Channel_1, &DAC_InitStructure);
00085
00086 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL
00087   /* DMA2 channel3 configuration */
00088   DMA_DeInit(DMA2_Channel3);
00089 #else
00090   /* DMA1 channel3 configuration */
00091   DMA_DeInit(DMA1_Channel3);
00092 #endif
00093
00094   DMA_InitStructure.DMA_PeripheralBaseAddr = DAC_DHR8R1_Address;
00095   DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)&Escalator8bit;
00096   DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
00097   DMA_InitStructure.DMA_BufferSize = 6;
00098   DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
00099   DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
00100   DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
00101   DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
00102   DMA_InitStructure.DMA_Mode = DMA_Mode_Circular;
00103   DMA_InitStructure.DMA_Priority = DMA_Priority_High;
00104   DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
00105
00106 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL
00107   DMA_Init(DMA2_Channel3, &DMA_InitStructure);
00108   /* Enable DMA2 Channel3 */
00109   DMA_Cmd(DMA2_Channel3, ENABLE);
00110 #else
00111   DMA_Init(DMA1_Channel3, &DMA_InitStructure);
00112   /* Enable DMA1 Channel3 */
00113   DMA_Cmd(DMA1_Channel3, ENABLE);
00114 #endif
00115
00116   /* Enable DAC Channel1: Once the DAC channel1 is enabled, PA.04 is
00117      automatically connected to the DAC converter. */
00118   DAC_Cmd(DAC_Channel_1, ENABLE);
00119
00120   /* Enable DMA for DAC Channel1 */
00121   DAC_DMACmd(DAC_Channel_1, ENABLE);
00122
00123   /* TIM6 enable counter */
00124   TIM_Cmd(TIM6, ENABLE);
00125
00126   while (1)
00127   {
00128   }
00129 }
00130
00131
00132 /**
00133   * @brief  Configures the different system clocks.
00134   * @param  None
00135   * @retval None
00136   */
00137 void RCC_Configuration(void)
00138 {
00139   /* Enable peripheral clocks ------------------------------------------------*/
00140 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL
00141   /* DMA2 clock enable */
00142   RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA2, ENABLE);
00143 #else
00144   /* DMA1 clock enable */
00145   RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE);
00146 #endif
00147   /* GPIOA Periph clock enable */
00148   RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);
00149   /* DAC Periph clock enable */
00150   RCC_APB1PeriphClockCmd(RCC_APB1Periph_DAC, ENABLE);
00151   /* TIM6 Periph clock enable */
00152   RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM6, ENABLE);
00153 }
00154
00155 /**
00156   * @brief  Configures the different GPIO ports.
00157   * @param  None
00158   * @retval None
00159   */
00160 void GPIO_Configuration(void)
00161 {
00162   GPIO_InitTypeDef GPIO_InitStructure;
00163
00164   /* Once the DAC channel is enabled, the corresponding GPIO pin is automatically
00165      connected to the DAC converter. In order to avoid parasitic consumption,
00166      the GPIO pin should be configured in analog */
00167   GPIO_InitStructure.GPIO_Pin =  GPIO_Pin_4;
00168   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AIN;
00169   GPIO_Init(GPIOA, &GPIO_InitStructure);
00170 }
00171
00172 /**
00173   * @brief  Inserts a delay time.
00174   * @param  nCount: specifies the delay time length.
00175   * @retval None
00176   */
00177 void Delay(__IO uint32_t nCount)
00178 {
00179   for(; nCount != 0; nCount--);
00180 }
00181
00182 #ifdef  USE_FULL_ASSERT
00183
00184 /**
00185   * @brief  Reports the name of the source file and the source line number
00186   *         where the assert_param error has occurred.
00187   * @param  file: pointer to the source file name
00188   * @param  line: assert_param error line source number
00189   * @retval None
00190   */
00191 void assert_failed(uint8_t* file, uint32_t line)
00192 {
00193   /* User can add his own implementation to report the file name and line number,
00194      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00195
00196   /* Infinite loop */
00197   while (1)
00198   {
00199   }
00200 }
00201
00202 #endif
00203
00204 /**
00205   * @}
00206   */
00207
00208 /**
00209   * @}
00210   */
00211
00212 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/stm32f10x_conf.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    DAC/OneChannelDMA_Escalator/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052 /* Exported types ------------------------------------------------------------*/
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Uncomment the line below to expanse the "assert_param" macro in the
00055    Standard Peripheral Library drivers code */
00056 /* #define USE_FULL_ASSERT    1 */
00057
00058 /* Exported macro ------------------------------------------------------------*/
00059 #ifdef  USE_FULL_ASSERT
00060
00061 /**
00062   * @brief  The assert_param macro is used for function's parameters check.
00063   * @param  expr: If expr is false, it calls assert_failed function which reports
00064   *         the name of the source file and the source line number of the call
00065   *         that failed. If expr is true, it returns no value.
00066   * @retval None
00067   */
00068   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00069 /* Exported functions ------------------------------------------------------- */
00070   void assert_failed(uint8_t* file, uint32_t line);
00071 #else
00072   #define assert_param(expr) ((void)0)
00073 #endif /* USE_FULL_ASSERT */
00074
00075 #endif /* __STM32F10x_CONF_H */
00076
00077 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/stm32f10x_it.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    DAC/OneChannelDMA_Escalator/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and peripherals
00009   *          interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026
00027 /** @addtogroup STM32F10x_StdPeriph_Examples
00028   * @{
00029   */
00030
00031 /** @addtogroup DAC_OneChannelDMA_Escalator
00032   * @{
00033   */
00034
00035 /* Private typedef -----------------------------------------------------------*/
00036 /* Private define ------------------------------------------------------------*/
00037 /* Private macro -------------------------------------------------------------*/
00038 /* Private variables ---------------------------------------------------------*/
00039 /* Private function prototypes -----------------------------------------------*/
00040 /* Private functions ---------------------------------------------------------*/
00041
00042 /******************************************************************************/
00043 /*            Cortex-M3 Processor Exceptions Handlers                         */
00044 /******************************************************************************/
00045
00046 /**
00047   * @brief  This function handles NMI exception.
00048   * @param  None
00049   * @retval None
00050   */
00051 void NMI_Handler(void)
00052 {
00053 }
00054
00055 /**
00056   * @brief  This function handles Hard Fault exception.
00057   * @param  None
00058   * @retval None
00059   */
00060 void HardFault_Handler(void)
00061 {
00062   /* Go to infinite loop when Hard Fault exception occurs */
00063   while (1)
00064   {
00065   }
00066 }
00067
00068 /**
00069   * @brief  This function handles Memory Manage exception.
00070   * @param  None
00071   * @retval None
00072   */
00073 void MemManage_Handler(void)
00074 {
00075   /* Go to infinite loop when Memory Manage exception occurs */
00076   while (1)
00077   {
00078   }
00079 }
00080
00081 /**
00082   * @brief  This function handles Bus Fault exception.
00083   * @param  None
00084   * @retval None
00085   */
00086 void BusFault_Handler(void)
00087 {
00088   /* Go to infinite loop when Bus Fault exception occurs */
00089   while (1)
00090   {
00091   }
00092 }
00093
00094 /**
00095   * @brief  This function handles Usage Fault exception.
00096   * @param  None
00097   * @retval None
00098   */
00099 void UsageFault_Handler(void)
00100 {
00101   /* Go to infinite loop when Usage Fault exception occurs */
00102   while (1)
00103   {
00104   }
00105 }
00106
00107 /**
00108   * @brief  This function handles SVCall exception.
00109   * @param  None
00110   * @retval None
00111   */
00112 void SVC_Handler(void)
00113 {
00114 }
00115
00116 /**
00117   * @brief  This function handles Debug Monitor exception.
00118   * @param  None
00119   * @retval None
00120   */
00121 void DebugMon_Handler(void)
00122 {
00123 }
00124
00125 /**
00126   * @brief  This function handles PendSV_Handler exception.
00127   * @param  None
00128   * @retval None
00129   */
00130 void PendSV_Handler(void)
00131 {
00132 }
00133
00134 /**
00135   * @brief  This function handles SysTick Handler.
00136   * @param  None
00137   * @retval None
00138   */
00139 void SysTick_Handler(void)
00140 {
00141 }
00142
00143 /******************************************************************************/
00144 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00145 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00146 /*  available peripheral interrupt handler's name please refer to the startup */
00147 /*  file (startup_stm32f10x_xx.s).                                            */
00148 /******************************************************************************/
00149
00150 /**
00151   * @brief  This function handles PPP interrupt request.
00152   * @param  None
00153   * @retval None
00154   */
00155 /*void PPP_IRQHandler(void)
00156 {
00157 }*/
00158
00159 /**
00160   * @}
00161   */
00162
00163 /**
00164   * @}
00165   */
00166
00167 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/stm32f10x_it.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    DAC/OneChannelDMA_Escalator/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043
00044 #endif /* __STM32F10x_IT_H */
00045
00046 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/main.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    DAC/TwoChannels_TriangleWave/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x.h"
00024
00025 /** @addtogroup STM32F10x_StdPeriph_Examples
00026   * @{
00027   */
00028
00029 /** @addtogroup DAC_TwoChannels_TriangleWave
00030   * @{
00031   */
00032
00033 /* Private typedef -----------------------------------------------------------*/
00034 /* Private define ------------------------------------------------------------*/
00035 /* Init Structure definition */
00036 DAC_InitTypeDef            DAC_InitStructure;
00037 TIM_TimeBaseInitTypeDef    TIM_TimeBaseStructure;
00038
00039 /* Private macro -------------------------------------------------------------*/
00040 /* Private variables ---------------------------------------------------------*/
00041 /* Private function prototypes -----------------------------------------------*/
00042 void RCC_Configuration(void);
00043 void GPIO_Configuration(void);
00044 void Delay(__IO uint32_t nCount);
00045
00046 /* Private functions ---------------------------------------------------------*/
00047
00048 /**
00049   * @brief   Main program.
00050   * @param  None
00051   * @retval None
00052   */
00053 int main(void)
00054 {
00055   /*!< At this stage the microcontroller clock setting is already configured,
00056        this is done through SystemInit() function which is called from startup
00057        file (startup_stm32f10x_xx.s) before to branch to application main.
00058        To reconfigure the default setting of SystemInit() function, refer to
00059        system_stm32f10x.c file
00060      */
00061
00062   /* System Clocks Configuration */
00063   RCC_Configuration();
00064
00065   /* Once the DAC channel is enabled, the corresponding GPIO pin is automatically
00066      connected to the DAC converter. In order to avoid parasitic consumption,
00067      the GPIO pin should be configured in analog */
00068   GPIO_Configuration();
00069
00070   /* TIM2 Configuration */
00071   TIM_TimeBaseStructInit(&TIM_TimeBaseStructure);
00072   TIM_TimeBaseStructure.TIM_Period = 0xF;
00073   TIM_TimeBaseStructure.TIM_Prescaler = 0xF;
00074   TIM_TimeBaseStructure.TIM_ClockDivision = 0x0;
00075   TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
00076   TIM_TimeBaseInit(TIM2, &TIM_TimeBaseStructure);
00077
00078   /* TIM2 TRGO selection */
00079   TIM_SelectOutputTrigger(TIM2, TIM_TRGOSource_Update);
00080
00081   /* DAC channel1 Configuration */
00082   DAC_InitStructure.DAC_Trigger = DAC_Trigger_T2_TRGO;
00083   DAC_InitStructure.DAC_WaveGeneration = DAC_WaveGeneration_Triangle;
00084   DAC_InitStructure.DAC_LFSRUnmask_TriangleAmplitude = DAC_TriangleAmplitude_2047;
00085   DAC_InitStructure.DAC_OutputBuffer = DAC_OutputBuffer_Disable;
00086   DAC_Init(DAC_Channel_1, &DAC_InitStructure);
00087
00088   /* DAC channel2 Configuration */
00089   DAC_InitStructure.DAC_LFSRUnmask_TriangleAmplitude = DAC_TriangleAmplitude_1023;
00090   DAC_Init(DAC_Channel_2, &DAC_InitStructure);
00091
00092   /* Enable DAC Channel1: Once the DAC channel1 is enabled, PA.04 is
00093      automatically connected to the DAC converter. */
00094   DAC_Cmd(DAC_Channel_1, ENABLE);
00095
00096   /* Enable DAC Channel2: Once the DAC channel2 is enabled, PA.05 is
00097      automatically connected to the DAC converter. */
00098   DAC_Cmd(DAC_Channel_2, ENABLE);
00099
00100   /* Set DAC dual channel DHR12RD register */
00101   DAC_SetDualChannelData(DAC_Align_12b_R, 0x100, 0x100);
00102
00103   /* TIM2 enable counter */
00104   TIM_Cmd(TIM2, ENABLE);
00105
00106   while (1)
00107   {
00108   }
00109 }
00110
00111 /**
00112   * @brief  Configures the different system clocks.
00113   * @param  None
00114   * @retval None
00115   */
00116 void RCC_Configuration(void)
00117 {
00118   /* Enable peripheral clocks ------------------------------------------------*/
00119   /* GPIOA Periph clock enable */
00120   RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);
00121   /* DAC Periph clock enable */
00122   RCC_APB1PeriphClockCmd(RCC_APB1Periph_DAC, ENABLE);
00123   /* TIM2 Periph clock enable */
00124   RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2, ENABLE);
00125 }
00126
00127 /**
00128   * @brief  Configures the different GPIO ports.
00129   * @param  None
00130   * @retval None
00131   */
00132 void GPIO_Configuration(void)
00133 {
00134   GPIO_InitTypeDef GPIO_InitStructure;
00135
00136   /* Once the DAC channel is enabled, the corresponding GPIO pin is automatically
00137      connected to the DAC converter. In order to avoid parasitic consumption,
00138      the GPIO pin should be configured in analog */
00139   GPIO_InitStructure.GPIO_Pin =  GPIO_Pin_4 | GPIO_Pin_5;
00140   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AIN;
00141   GPIO_Init(GPIOA, &GPIO_InitStructure);
00142 }
00143
00144 /**
00145   * @brief  Inserts a delay time.
00146   * @param  nCount: specifies the delay time length.
00147   * @retval None
00148   */
00149 void Delay(__IO uint32_t nCount)
00150 {
00151   for(; nCount != 0; nCount--);
00152 }
00153
00154 #ifdef  USE_FULL_ASSERT
00155
00156 /**
00157   * @brief  Reports the name of the source file and the source line number
00158   *         where the assert_param error has occurred.
00159   * @param  file: pointer to the source file name
00160   * @param  line: assert_param error line source number
00161   * @retval None
00162   */
00163 void assert_failed(uint8_t* file, uint32_t line)
00164 {
00165   /* User can add his own implementation to report the file name and line number,
00166      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00167
00168   /* Infinite loop */
00169   while (1)
00170   {
00171   }
00172 }
00173
00174 #endif
00175
00176 /**
00177   * @}
00178   */
00179
00180 /**
00181   * @}
00182   */
00183
00184 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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  • TwoChannels_TriangleWave

STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/stm32f10x_conf.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    DAC/TwoChannels_TriangleWave/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052 /* Exported types ------------------------------------------------------------*/
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Uncomment the line below to expanse the "assert_param" macro in the
00055    Standard Peripheral Library drivers code */
00056 /* #define USE_FULL_ASSERT    1 */
00057
00058 /* Exported macro ------------------------------------------------------------*/
00059 #ifdef  USE_FULL_ASSERT
00060
00061 /**
00062   * @brief  The assert_param macro is used for function's parameters check.
00063   * @param  expr: If expr is false, it calls assert_failed function which reports
00064   *         the name of the source file and the source line number of the call
00065   *         that failed. If expr is true, it returns no value.
00066   * @retval None
00067   */
00068   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00069 /* Exported functions ------------------------------------------------------- */
00070   void assert_failed(uint8_t* file, uint32_t line);
00071 #else
00072   #define assert_param(expr) ((void)0)
00073 #endif /* USE_FULL_ASSERT */
00074
00075 #endif /* __STM32F10x_CONF_H */
00076
00077 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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  • TwoChannels_TriangleWave

STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/stm32f10x_it.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    DAC/TwoChannels_TriangleWave/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and peripherals
00009   *          interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026
00027 /** @addtogroup STM32F10x_StdPeriph_Examples
00028   * @{
00029   */
00030
00031 /** @addtogroup DAC_TwoChannels_TriangleWave
00032   * @{
00033   */
00034
00035 /* Private typedef -----------------------------------------------------------*/
00036 /* Private define ------------------------------------------------------------*/
00037 /* Private macro -------------------------------------------------------------*/
00038 /* Private variables ---------------------------------------------------------*/
00039 /* Private function prototypes -----------------------------------------------*/
00040 /* Private functions ---------------------------------------------------------*/
00041
00042 /******************************************************************************/
00043 /*            Cortex-M3 Processor Exceptions Handlers                         */
00044 /******************************************************************************/
00045
00046
00047 /**
00048   * @brief  This function handles NMI exception.
00049   * @param  None
00050   * @retval None
00051   */
00052 void NMI_Handler(void)
00053 {
00054 }
00055
00056 /**
00057   * @brief  This function handles Hard Fault exception.
00058   * @param  None
00059   * @retval None
00060   */
00061 void HardFault_Handler(void)
00062 {
00063   /* Go to infinite loop when Hard Fault exception occurs */
00064   while (1)
00065   {
00066   }
00067 }
00068
00069 /**
00070   * @brief  This function handles Memory Manage exception.
00071   * @param  None
00072   * @retval None
00073   */
00074 void MemManage_Handler(void)
00075 {
00076   /* Go to infinite loop when Memory Manage exception occurs */
00077   while (1)
00078   {
00079   }
00080 }
00081
00082 /**
00083   * @brief  This function handles Bus Fault exception.
00084   * @param  None
00085   * @retval None
00086   */
00087 void BusFault_Handler(void)
00088 {
00089   /* Go to infinite loop when Bus Fault exception occurs */
00090   while (1)
00091   {
00092   }
00093 }
00094
00095 /**
00096   * @brief  This function handles Usage Fault exception.
00097   * @param  None
00098   * @retval None
00099   */
00100 void UsageFault_Handler(void)
00101 {
00102   /* Go to infinite loop when Usage Fault exception occurs */
00103   while (1)
00104   {
00105   }
00106 }
00107
00108 /**
00109   * @brief  This function handles SVCall exception.
00110   * @param  None
00111   * @retval None
00112   */
00113 void SVC_Handler(void)
00114 {
00115 }
00116
00117 /**
00118   * @brief  This function handles Debug Monitor exception.
00119   * @param  None
00120   * @retval None
00121   */
00122 void DebugMon_Handler(void)
00123 {
00124 }
00125
00126 /**
00127   * @brief  This function handles PendSV_Handler exception.
00128   * @param  None
00129   * @retval None
00130   */
00131 void PendSV_Handler(void)
00132 {
00133 }
00134
00135 /**
00136   * @brief  This function handles SysTick Handler.
00137   * @param  None
00138   * @retval None
00139   */
00140 void SysTick_Handler(void)
00141 {
00142 }
00143
00144 /******************************************************************************/
00145 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00146 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00147 /*  available peripheral interrupt handler's name please refer to the startup */
00148 /*  file (startup_stm32f10x_xx.s).                                            */
00149 /******************************************************************************/
00150
00151 /**
00152   * @brief  This function handles PPP interrupt request.
00153   * @param  None
00154   * @retval None
00155   */
00156 /*void PPP_IRQHandler(void)
00157 {
00158 }*/
00159
00160 /**
00161   * @}
00162   */
00163
00164 /**
00165   * @}
00166   */
00167
00168 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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  • TwoChannels_TriangleWave

STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/stm32f10x_it.h

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00001 /**
00002   ******************************************************************************
00003   * @file    DAC/TwoChannels_TriangleWave/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043
00044 #endif /* __STM32F10x_IT_H */
00045
00046 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/main.c

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00001 /**
00002   ******************************************************************************
00003   * @file    DMA/ADC_TIM1/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x.h"
00024
00025 /** @addtogroup STM32F10x_StdPeriph_Examples
00026   * @{
00027   */
00028
00029 /** @addtogroup DMA_ADC_TIM1
00030   * @{
00031   */
00032
00033 /* Private typedef -----------------------------------------------------------*/
00034 /* Private define ------------------------------------------------------------*/
00035 #define ADC1_DR_Address     0x4001244C
00036 #define TIM1_CCR1_Address   0x40012C34
00037
00038 /* Private macro -------------------------------------------------------------*/
00039 /* Private variables ---------------------------------------------------------*/
00040 ADC_InitTypeDef           ADC_InitStructure;
00041 TIM_TimeBaseInitTypeDef   TIM_TimeBaseStructure;
00042 TIM_OCInitTypeDef         TIM_OCInitStructure;
00043 DMA_InitTypeDef           DMA_InitStructure;
00044
00045 /* Private function prototypes -----------------------------------------------*/
00046 void RCC_Configuration(void);
00047 void GPIO_Configuration(void);
00048
00049 /* Private functions ---------------------------------------------------------*/
00050
00051 /**
00052   * @brief   Main program
00053   * @param  None
00054   * @retval None
00055   */
00056 int main(void)
00057 {
00058   /*!< At this stage the microcontroller clock setting is already configured,
00059        this is done through SystemInit() function which is called from startup
00060        file (startup_stm32f10x_xx.s) before to branch to application main.
00061        To reconfigure the default setting of SystemInit() function, refer to
00062        system_stm32f10x.c file
00063      */
00064
00065   /* System Clocks Configuration */
00066   RCC_Configuration();
00067
00068   /* Configure the GPIO ports */
00069   GPIO_Configuration();
00070
00071   /* DMA1 Channel5 configuration ----------------------------------------------*/
00072   DMA_DeInit(DMA1_Channel5);
00073   DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)TIM1_CCR1_Address;
00074   DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)ADC1_DR_Address;
00075   DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
00076   DMA_InitStructure.DMA_BufferSize = 1;
00077   DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
00078   DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Disable;
00079   DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord;
00080   DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
00081   DMA_InitStructure.DMA_Mode = DMA_Mode_Circular;
00082   DMA_InitStructure.DMA_Priority = DMA_Priority_High;
00083   DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
00084   DMA_Init(DMA1_Channel5, &DMA_InitStructure);
00085   /* Enable DMA1 Channel5 */
00086   DMA_Cmd(DMA1_Channel5, ENABLE);
00087
00088   /* ADC1 configuration ------------------------------------------------------*/
00089   ADC_InitStructure.ADC_Mode = ADC_Mode_Independent;
00090   ADC_InitStructure.ADC_ScanConvMode = DISABLE;
00091   ADC_InitStructure.ADC_ContinuousConvMode = ENABLE;
00092   ADC_InitStructure.ADC_ExternalTrigConv = ADC_ExternalTrigConv_None;
00093   ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right;
00094   ADC_InitStructure.ADC_NbrOfChannel = 1;
00095   ADC_Init(ADC1, &ADC_InitStructure);
00096
00097   /* ADC1 RegularChannelConfig Test */
00098   ADC_RegularChannelConfig(ADC1, ADC_Channel_14, 1, ADC_SampleTime_55Cycles5);
00099
00100   /* TIM1 configuration ------------------------------------------------------*/
00101   /* Time Base configuration */
00102   TIM_TimeBaseStructInit(&TIM_TimeBaseStructure);
00103   TIM_TimeBaseStructure.TIM_Period = 0xFF0;
00104   TIM_TimeBaseStructure.TIM_Prescaler = 0x0;
00105   TIM_TimeBaseStructure.TIM_ClockDivision = 0x0;
00106   TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
00107   TIM_TimeBaseInit(TIM1, &TIM_TimeBaseStructure);
00108   /* Channel1 Configuration in PWM mode */
00109   TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1;
00110   TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
00111   TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High;
00112   TIM_OC1Init(TIM1, &TIM_OCInitStructure);
00113
00114   /* Enable TIM1 */
00115   TIM_Cmd(TIM1, ENABLE);
00116   /* Enable TIM1 outputs */
00117   TIM_CtrlPWMOutputs(TIM1, ENABLE);
00118
00119   /* Enable TIM1 DMA interface */
00120   TIM_DMACmd(TIM1, TIM_DMA_Update, ENABLE);
00121
00122   /* Enable ADC1 */
00123   ADC_Cmd(ADC1, ENABLE);
00124
00125   /* Enable ADC1 reset calibration register */
00126   ADC_ResetCalibration(ADC1);
00127   /* Check the end of ADC1 reset calibration register */
00128   while(ADC_GetResetCalibrationStatus(ADC1));
00129
00130   /* Start ADC1 calibration */
00131   ADC_StartCalibration(ADC1);
00132   /* Check the end of ADC1 calibration */
00133   while(ADC_GetCalibrationStatus(ADC1));
00134
00135   /* Start ADC1 conversion */
00136   ADC_SoftwareStartConvCmd(ADC1, ENABLE);
00137
00138   while (1)
00139   {
00140   }
00141 }
00142
00143 /**
00144   * @brief  Configures the different system clocks.
00145   * @param  None
00146   * @retval None
00147   */
00148 void RCC_Configuration(void)
00149 {
00150   /* ADCCLK = PCLK2/8 */
00151   RCC_ADCCLKConfig(RCC_PCLK2_Div8);
00152
00153   /* Enable peripheral clocks ------------------------------------------------*/
00154   /* Enable DMA1 clock */
00155   RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE);
00156   /* Enable GPIOA, GPIOC, ADC1 and TIM1 Periph clock */
00157   RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOC |
00158                          RCC_APB2Periph_ADC1 | RCC_APB2Periph_TIM1, ENABLE);
00159 }
00160
00161 /**
00162   * @brief  Configures the different GPIO ports.
00163   * @param  None
00164   * @retval None
00165   */
00166 void GPIO_Configuration(void)
00167 {
00168   GPIO_InitTypeDef GPIO_InitStructure;
00169
00170   /* Configure TIM1 Channel1 output */
00171   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8;
00172   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
00173   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00174   GPIO_Init(GPIOA, &GPIO_InitStructure);
00175
00176   /* Configure ADC Channel14 as analog input */
00177   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4  ;
00178   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AIN;
00179   GPIO_Init(GPIOC, &GPIO_InitStructure);
00180 }
00181
00182 #ifdef  USE_FULL_ASSERT
00183
00184 /**
00185   * @brief  Reports the name of the source file and the source line number
00186   *         where the assert_param error has occurred.
00187   * @param  file: pointer to the source file name
00188   * @param  line: assert_param error line source number
00189   * @retval None
00190   */
00191 void assert_failed(uint8_t* file, uint32_t line)
00192 {
00193   /* User can add his own implementation to report the file name and line number,
00194      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00195
00196   /* Infinite loop */
00197   while (1)
00198   {
00199   }
00200 }
00201
00202 #endif
00203
00204 /**
00205   * @}
00206   */
00207
00208 /**
00209   * @}
00210   */
00211
00212 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/stm32f10x_conf.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    DMA/ADC_TIM1/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052 /* Exported types ------------------------------------------------------------*/
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Uncomment the line below to expanse the "assert_param" macro in the
00055    Standard Peripheral Library drivers code */
00056 /* #define USE_FULL_ASSERT    1 */
00057
00058 /* Exported macro ------------------------------------------------------------*/
00059 #ifdef  USE_FULL_ASSERT
00060
00061 /**
00062   * @brief  The assert_param macro is used for function's parameters check.
00063   * @param  expr: If expr is false, it calls assert_failed function which reports
00064   *         the name of the source file and the source line number of the call
00065   *         that failed. If expr is true, it returns no value.
00066   * @retval None
00067   */
00068   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00069 /* Exported functions ------------------------------------------------------- */
00070   void assert_failed(uint8_t* file, uint32_t line);
00071 #else
00072   #define assert_param(expr) ((void)0)
00073 #endif /* USE_FULL_ASSERT */
00074
00075 #endif /* __STM32F10x_CONF_H */
00076
00077 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/stm32f10x_it.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    DMA/ADC_TIM1/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and peripherals
00009   *          interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026
00027 /** @addtogroup STM32F10x_StdPeriph_Examples
00028   * @{
00029   */
00030
00031 /** @addtogroup DMA_ADC_TIM1
00032   * @{
00033   */
00034
00035 /* Private typedef -----------------------------------------------------------*/
00036 /* Private define ------------------------------------------------------------*/
00037 /* Private macro -------------------------------------------------------------*/
00038 /* Private variables ---------------------------------------------------------*/
00039 /* Private function prototypes -----------------------------------------------*/
00040 /* Private functions ---------------------------------------------------------*/
00041
00042 /******************************************************************************/
00043 /*            Cortex-M3 Processor Exceptions Handlers                         */
00044 /******************************************************************************/
00045
00046 /**
00047   * @brief  This function handles NMI exception.
00048   * @param  None
00049   * @retval None
00050   */
00051 void NMI_Handler(void)
00052 {
00053 }
00054
00055
00056
00057 /**
00058   * @brief  This function handles Hard Fault exception.
00059   * @param  None
00060   * @retval None
00061   */
00062 void HardFault_Handler(void)
00063 {
00064   /* Go to infinite loop when Hard Fault exception occurs */
00065   while (1)
00066   {
00067   }
00068 }
00069
00070 /**
00071   * @brief  This function handles Memory Manage exception.
00072   * @param  None
00073   * @retval None
00074   */
00075 void MemManage_Handler(void)
00076 {
00077   /* Go to infinite loop when Memory Manage exception occurs */
00078   while (1)
00079   {
00080   }
00081 }
00082
00083 /**
00084   * @brief  This function handles Bus Fault exception.
00085   * @param  None
00086   * @retval None
00087   */
00088 void BusFault_Handler(void)
00089 {
00090   /* Go to infinite loop when Bus Fault exception occurs */
00091   while (1)
00092   {
00093   }
00094 }
00095
00096 /**
00097   * @brief  This function handles Usage Fault exception.
00098   * @param  None
00099   * @retval None
00100   */
00101 void UsageFault_Handler(void)
00102 {
00103   /* Go to infinite loop when Usage Fault exception occurs */
00104   while (1)
00105   {
00106   }
00107 }
00108
00109 /**
00110   * @brief  This function handles SVCall exception.
00111   * @param  None
00112   * @retval None
00113   */
00114 void SVC_Handler(void)
00115 {
00116 }
00117
00118 /**
00119   * @brief  This function handles Debug Monitor exception.
00120   * @param  None
00121   * @retval None
00122   */
00123 void DebugMon_Handler(void)
00124 {
00125 }
00126
00127 /**
00128   * @brief  This function handles PendSV_Handler exception.
00129   * @param  None
00130   * @retval None
00131   */
00132 void PendSV_Handler(void)
00133 {
00134 }
00135
00136 /**
00137   * @brief  This function handles SysTick Handler.
00138   * @param  None
00139   * @retval None
00140   */
00141 void SysTick_Handler(void)
00142 {
00143 }
00144
00145 /******************************************************************************/
00146 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00147 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00148 /*  available peripheral interrupt handler's name please refer to the startup */
00149 /*  file (startup_stm32f10x_xx.s).                                            */
00150 /******************************************************************************/
00151
00152 /**
00153   * @brief  This function handles PPP interrupt request.
00154   * @param  None
00155   * @retval None
00156   */
00157 /*void PPP_IRQHandler(void)
00158 {
00159 }*/
00160
00161 /**
00162   * @}
00163   */
00164
00165 /**
00166   * @}
00167   */
00168
00169 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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  • ADC_TIM1

STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/stm32f10x_it.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    DMA/ADC_TIM1/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043
00044 #endif /* __STM32F10x_IT_H */
00045
00046 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/main.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    DMA/FLASH_RAM/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x.h"
00024
00025 /** @addtogroup STM32F10x_StdPeriph_Examples
00026   * @{
00027   */
00028
00029 /** @addtogroup DMA_FLASH_RAM
00030   * @{
00031   */
00032
00033 /* Private typedef -----------------------------------------------------------*/
00034 typedef enum {FAILED = 0, PASSED = !FAILED} TestStatus;
00035
00036 /* Private define ------------------------------------------------------------*/
00037 #define BufferSize  32
00038
00039 /* Private macro -------------------------------------------------------------*/
00040 /* Private variables ---------------------------------------------------------*/
00041 DMA_InitTypeDef  DMA_InitStructure;
00042 __IO uint32_t CurrDataCounterBegin = 0;
00043 __IO uint32_t CurrDataCounterEnd = 0x01; /* This variable should not be initialized to 0 */
00044
00045 TestStatus TransferStatus = FAILED;
00046 const uint32_t SRC_Const_Buffer[BufferSize]= {
00047                                     0x01020304,0x05060708,0x090A0B0C,0x0D0E0F10,
00048                                     0x11121314,0x15161718,0x191A1B1C,0x1D1E1F20,
00049                                     0x21222324,0x25262728,0x292A2B2C,0x2D2E2F30,
00050                                     0x31323334,0x35363738,0x393A3B3C,0x3D3E3F40,
00051                                     0x41424344,0x45464748,0x494A4B4C,0x4D4E4F50,
00052                                     0x51525354,0x55565758,0x595A5B5C,0x5D5E5F60,
00053                                     0x61626364,0x65666768,0x696A6B6C,0x6D6E6F70,
00054                                     0x71727374,0x75767778,0x797A7B7C,0x7D7E7F80};
00055 uint32_t DST_Buffer[BufferSize];
00056
00057 /* Private function prototypes -----------------------------------------------*/
00058 void RCC_Configuration(void);
00059 void NVIC_Configuration(void);
00060 TestStatus Buffercmp(const uint32_t* pBuffer, uint32_t* pBuffer1, uint16_t BufferLength);
00061
00062 /* Private functions ---------------------------------------------------------*/
00063
00064 /**
00065   * @brief  Main program
00066   * @param  None
00067   * @retval None
00068   */
00069 int main(void)
00070 {
00071   /*!< At this stage the microcontroller clock setting is already configured,
00072        this is done through SystemInit() function which is called from startup
00073        file (startup_stm32f10x_xx.s) before to branch to application main.
00074        To reconfigure the default setting of SystemInit() function, refer to
00075        system_stm32f10x.c file
00076      */
00077
00078   /* System Clocks Configuration */
00079   RCC_Configuration();
00080
00081   /* NVIC configuration */
00082   NVIC_Configuration();
00083
00084   /* DMA1 channel6 configuration */
00085   DMA_DeInit(DMA1_Channel6);
00086   DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)SRC_Const_Buffer;
00087   DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)DST_Buffer;
00088   DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
00089   DMA_InitStructure.DMA_BufferSize = BufferSize;
00090   DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Enable;
00091   DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
00092   DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Word;
00093   DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Word;
00094   DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
00095   DMA_InitStructure.DMA_Priority = DMA_Priority_High;
00096   DMA_InitStructure.DMA_M2M = DMA_M2M_Enable;
00097   DMA_Init(DMA1_Channel6, &DMA_InitStructure);
00098
00099   /* Enable DMA1 Channel6 Transfer Complete interrupt */
00100   DMA_ITConfig(DMA1_Channel6, DMA_IT_TC, ENABLE);
00101
00102   /* Get Current Data Counter value before transfer begins */
00103   CurrDataCounterBegin = DMA_GetCurrDataCounter(DMA1_Channel6);
00104
00105   /* Enable DMA1 Channel6 transfer */
00106   DMA_Cmd(DMA1_Channel6, ENABLE);
00107
00108   /* Wait the end of transmission */
00109   while (CurrDataCounterEnd != 0)
00110   {
00111   }
00112
00113   /* Check if the transmitted and received data are equal */
00114   TransferStatus = Buffercmp(SRC_Const_Buffer, DST_Buffer, BufferSize);
00115   /* TransferStatus = PASSED, if the transmitted and received data
00116      are the same */
00117   /* TransferStatus = FAILED, if the transmitted and received data
00118      are different */
00119
00120   while (1)
00121   {
00122   }
00123 }
00124
00125 /**
00126   * @brief  Configures the different system clocks.
00127   * @param  None
00128   * @retval None
00129   */
00130 void RCC_Configuration(void)
00131 {
00132   /* Enable peripheral clocks ------------------------------------------------*/
00133   /* Enable DMA1 clock */
00134   RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE);
00135 }
00136
00137 /**
00138   * @brief  Configure the nested vectored interrupt controller.
00139   * @param  None
00140   * @retval None
00141   */
00142 void NVIC_Configuration(void)
00143 {
00144   NVIC_InitTypeDef NVIC_InitStructure;
00145
00146   /* Enable DMA1 channel6 IRQ Channel */
00147   NVIC_InitStructure.NVIC_IRQChannel = DMA1_Channel6_IRQn;
00148   NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
00149   NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
00150   NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
00151   NVIC_Init(&NVIC_InitStructure);
00152 }
00153
00154 /**
00155   * @brief  Compares two buffers.
00156   * @param  pBuffer, pBuffer1: buffers to be compared.
00157   * @param  BufferLength: buffer's length
00158   * @retval PASSED: pBuffer identical to pBuffer1
00159   *         FAILED: pBuffer differs from pBuffer1
00160   */
00161 TestStatus Buffercmp(const uint32_t* pBuffer, uint32_t* pBuffer1, uint16_t BufferLength)
00162 {
00163   while(BufferLength--)
00164   {
00165     if(*pBuffer != *pBuffer1)
00166     {
00167       return FAILED;
00168     }
00169
00170     pBuffer++;
00171     pBuffer1++;
00172   }
00173
00174   return PASSED;
00175 }
00176
00177 #ifdef  USE_FULL_ASSERT
00178
00179 /**
00180   * @brief  Reports the name of the source file and the source line number
00181   *         where the assert_param error has occurred.
00182   * @param  file: pointer to the source file name
00183   * @param  line: assert_param error line source number
00184   * @retval None
00185   */
00186 void assert_failed(uint8_t* file, uint32_t line)
00187 {
00188   /* User can add his own implementation to report the file name and line number,
00189      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00190
00191   /* Infinite loop */
00192   while (1)
00193   {
00194   }
00195 }
00196
00197 #endif
00198 /**
00199   * @}
00200   */
00201
00202 /**
00203   * @}
00204   */
00205
00206 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/stm32f10x_conf.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file DMA/FLASH_RAM/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052
00053 /* Exported types ------------------------------------------------------------*/
00054 /* Exported constants --------------------------------------------------------*/
00055 /* Uncomment the line below to expanse the "assert_param" macro in the
00056    Standard Peripheral Library drivers code */
00057 /* #define USE_FULL_ASSERT    1 */
00058
00059 /* Exported macro ------------------------------------------------------------*/
00060 #ifdef  USE_FULL_ASSERT
00061
00062 /**
00063   * @brief  The assert_param macro is used for function's parameters check.
00064   * @param  expr: If expr is false, it calls assert_failed function which reports
00065   *         the name of the source file and the source line number of the call
00066   *         that failed. If expr is true, it returns no value.
00067   * @retval None
00068   */
00069   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00070 /* Exported functions ------------------------------------------------------- */
00071   void assert_failed(uint8_t* file, uint32_t line);
00072 #else
00073   #define assert_param(expr) ((void)0)
00074 #endif /* USE_FULL_ASSERT */
00075
00076 #endif /* __STM32F10x_CONF_H */
00077
00078 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/stm32f10x_it.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    DMA/FLASH_RAM/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and peripherals
00009   *          interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026
00027 /** @addtogroup STM32F10x_StdPeriph_Examples
00028   * @{
00029   */
00030
00031 /** @addtogroup DMA_FLASH_RAM
00032   * @{
00033   */
00034
00035 /* Private typedef -----------------------------------------------------------*/
00036 /* Private define ------------------------------------------------------------*/
00037 /* Private macro -------------------------------------------------------------*/
00038 /* Private variables ---------------------------------------------------------*/
00039 extern __IO uint16_t CurrDataCounterEnd;
00040
00041 /* Private function prototypes -----------------------------------------------*/
00042 /* Private functions ---------------------------------------------------------*/
00043
00044 /******************************************************************************/
00045 /*            Cortex-M3 Processor Exceptions Handlers                         */
00046 /******************************************************************************/
00047
00048 /**
00049   * @brief  This function handles NMI exception.
00050   * @param  None
00051   * @retval None
00052   */
00053 void NMI_Handler(void)
00054 {
00055 }
00056
00057 /**
00058   * @brief  This function handles Hard Fault exception.
00059   * @param  None
00060   * @retval None
00061   */
00062 void HardFault_Handler(void)
00063 {
00064   /* Go to infinite loop when Hard Fault exception occurs */
00065   while (1)
00066   {
00067   }
00068 }
00069
00070 /**
00071   * @brief  This function handles Memory Manage exception.
00072   * @param  None
00073   * @retval None
00074   */
00075 void MemManage_Handler(void)
00076 {
00077   /* Go to infinite loop when Memory Manage exception occurs */
00078   while (1)
00079   {
00080   }
00081 }
00082
00083 /**
00084   * @brief  This function handles Bus Fault exception.
00085   * @param  None
00086   * @retval None
00087   */
00088 void BusFault_Handler(void)
00089 {
00090   /* Go to infinite loop when Bus Fault exception occurs */
00091   while (1)
00092   {
00093   }
00094 }
00095
00096 /**
00097   * @brief  This function handles Usage Fault exception.
00098   * @param  None
00099   * @retval None
00100   */
00101 void UsageFault_Handler(void)
00102 {
00103   /* Go to infinite loop when Usage Fault exception occurs */
00104   while (1)
00105   {
00106   }
00107 }
00108
00109 /**
00110   * @brief  This function handles SVCall exception.
00111   * @param  None
00112   * @retval None
00113   */
00114 void SVC_Handler(void)
00115 {
00116 }
00117
00118 /**
00119   * @brief  This function handles Debug Monitor exception.
00120   * @param  None
00121   * @retval None
00122   */
00123 void DebugMon_Handler(void)
00124 {
00125 }
00126
00127 /**
00128   * @brief  This function handles PendSV_Handler exception.
00129   * @param  None
00130   * @retval None
00131   */
00132 void PendSV_Handler(void)
00133 {
00134 }
00135
00136 /**
00137   * @brief  This function handles SysTick Handler.
00138   * @param  None
00139   * @retval None
00140   */
00141 void SysTick_Handler(void)
00142 {
00143 }
00144
00145 /******************************************************************************/
00146 /*            STM32F10x Peripherals Interrupt Handlers                        */
00147 /******************************************************************************/
00148
00149 /**
00150   * @brief  This function handles DMA1 Channel 6 interrupt request.
00151   * @param  None
00152   * @retval None
00153   */
00154 void DMA1_Channel6_IRQHandler(void)
00155 {
00156   /* Test on DMA1 Channel6 Transfer Complete interrupt */
00157   if(DMA_GetITStatus(DMA1_IT_TC6))
00158   {
00159     /* Get Current Data Counter value after complete transfer */
00160     CurrDataCounterEnd = DMA_GetCurrDataCounter(DMA1_Channel6);
00161     /* Clear DMA1 Channel6 Half Transfer, Transfer Complete and Global interrupt pending bits */
00162     DMA_ClearITPendingBit(DMA1_IT_GL6);
00163   }
00164 }
00165
00166 /******************************************************************************/
00167 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00168 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00169 /*  available peripheral interrupt handler's name please refer to the startup */
00170 /*  file (startup_stm32f10x_xx.s).                                            */
00171 /******************************************************************************/
00172
00173 /**
00174   * @brief  This function handles PPP interrupt request.
00175   * @param  None
00176   * @retval None
00177   */
00178 /*void PPP_IRQHandler(void)
00179 {
00180 }*/
00181
00182 /**
00183   * @}
00184   */
00185
00186 /**
00187   * @}
00188   */
00189
00190 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/stm32f10x_it.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file DMA/FLASH_RAM/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043 void DMA1_Channel6_IRQHandler(void);
00044
00045 #endif /* __STM32F10x_IT_H */
00046
00047 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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STM32F10x_StdPeriph_Examples/DMA/FSMC/main.c

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00001 /**
00002   ******************************************************************************
00003   * @file    DMA/FSMC/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #ifdef STM32F10X_HD_VL /* High-density Value line devices */
00024  #include "stm32100e_eval_fsmc_sram.h"
00025 #else /* High- and XL-density */
00026  #include "stm3210e_eval_fsmc_sram.h"
00027 #endif
00028
00029 /** @addtogroup STM32F10x_StdPeriph_Examples
00030   * @{
00031   */
00032
00033 /** @addtogroup DMA_FSMC
00034   * @{
00035   */
00036
00037 /* Private typedef -----------------------------------------------------------*/
00038 typedef enum {FAILED = 0, PASSED = !FAILED} TestStatus;
00039
00040 /* Private define ------------------------------------------------------------*/
00041 #define BufferSize  32
00042 #define Bank1_SRAM3_ADDR    ((uint32_t)0x68000000)
00043
00044 /* Private macro -------------------------------------------------------------*/
00045 /* Private variables ---------------------------------------------------------*/
00046 DMA_InitTypeDef    DMA_InitStructure;
00047 volatile TestStatus TransferStatus;
00048 const uint32_t SRC_Const_Buffer[BufferSize]= {
00049                             0x01020304,0x05060708,0x090A0B0C,0x0D0E0F10,
00050                             0x11121314,0x15161718,0x191A1B1C,0x1D1E1F20,
00051                             0x21222324,0x25262728,0x292A2B2C,0x2D2E2F30,
00052                             0x31323334,0x35363738,0x393A3B3C,0x3D3E3F40,
00053                             0x41424344,0x45464748,0x494A4B4C,0x4D4E4F50,
00054                             0x51525354,0x55565758,0x595A5B5C,0x5D5E5F60,
00055                             0x61626364,0x65666768,0x696A6B6C,0x6D6E6F70,
00056                             0x71727374,0x75767778,0x797A7B7C,0x7D7E7F80};
00057 uint8_t DST_Buffer[4*BufferSize];
00058 uint32_t Idx = 0;
00059
00060 /* Private function prototypes -----------------------------------------------*/
00061 void RCC_Configuration(void);
00062 TestStatus Buffercmp(const uint32_t* pBuffer, uint32_t* pBuffer1, uint16_t BufferLength);
00063
00064 /* Private functions ---------------------------------------------------------*/
00065
00066 /**
00067   * @brief  Main program.
00068   * @param  None
00069   * @retval None
00070   */
00071 int main(void)
00072 {
00073   /*!< At this stage the microcontroller clock setting is already configured,
00074        this is done through SystemInit() function which is called from startup
00075        file (startup_stm32f10x_xx.s) before to branch to application main.
00076        To reconfigure the default setting of SystemInit() function, refer to
00077        system_stm32f10x.c file
00078      */
00079
00080   /* System Clocks Configuration */
00081   RCC_Configuration();
00082
00083   /* FSMC for SRAM and SRAM pins configuration */
00084   SRAM_Init();
00085
00086   /* Write to FSMC -----------------------------------------------------------*/
00087   /* DMA2 channel5 configuration */
00088   DMA_DeInit(DMA2_Channel5);
00089   DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)SRC_Const_Buffer;
00090   DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)Bank1_SRAM3_ADDR;
00091   DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
00092   DMA_InitStructure.DMA_BufferSize = 32;
00093   DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Enable;
00094   DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
00095   DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Word;
00096   DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Word;
00097   DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
00098   DMA_InitStructure.DMA_Priority = DMA_Priority_High;
00099   DMA_InitStructure.DMA_M2M = DMA_M2M_Enable;
00100   DMA_Init(DMA2_Channel5, &DMA_InitStructure);
00101
00102   /* Enable DMA2 channel5 */
00103   DMA_Cmd(DMA2_Channel5, ENABLE);
00104
00105   /* Check if DMA2 channel5 transfer is finished */
00106   while(!DMA_GetFlagStatus(DMA2_FLAG_TC5));
00107
00108   /* Clear DMA2 channel5 transfer complete flag bit */
00109   DMA_ClearFlag(DMA2_FLAG_TC5);
00110
00111   /* Read from FSMC ----------------------------------------------------------*/
00112   /* Destination buffer initialization */
00113   for(Idx=0; Idx<128; Idx++) DST_Buffer[Idx]=0;
00114
00115   /* DMA1 channel3 configuration */
00116   DMA_DeInit(DMA1_Channel3);
00117   DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)Bank1_SRAM3_ADDR;
00118   DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)DST_Buffer;
00119   DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
00120   DMA_InitStructure.DMA_BufferSize = 128;
00121   DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Enable;
00122   DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
00123   DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
00124   DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
00125   DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
00126   DMA_InitStructure.DMA_Priority = DMA_Priority_High;
00127   DMA_InitStructure.DMA_M2M = DMA_M2M_Enable;
00128   DMA_Init(DMA1_Channel3, &DMA_InitStructure);
00129
00130   /* Enable DMA1 channel3 */
00131   DMA_Cmd(DMA1_Channel3, ENABLE);
00132
00133   /* Check if DMA1 channel3 transfer is finished */
00134   while(!DMA_GetFlagStatus(DMA1_FLAG_TC3));
00135
00136   /* Clear DMA1 channel3 transfer complete flag bit */
00137   DMA_ClearFlag(DMA1_FLAG_TC3);
00138
00139   /* Check if the transmitted and received data are equal */
00140   TransferStatus = Buffercmp(SRC_Const_Buffer, (uint32_t*)DST_Buffer, BufferSize);
00141   /* TransferStatus = PASSED, if the transmitted and received data
00142      are the same */
00143   /* TransferStatus = FAILED, if the transmitted and received data
00144      are different */
00145
00146   while (1)
00147   {
00148   }
00149 }
00150
00151 /**
00152   * @brief  Configures the different system clocks.
00153   * @param  None
00154   * @retval None
00155   */
00156 void RCC_Configuration(void)
00157 {
00158   /* Enable peripheral clocks ------------------------------------------------*/
00159   /* DMA1 and DMA2 clock enable */
00160   RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1 | RCC_AHBPeriph_DMA2, ENABLE);
00161   /* FSMC clock enable */
00162   RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, ENABLE);
00163 }
00164
00165 /**
00166   * @brief  Compares two buffers.
00167   * @param  pBuffer, pBuffer1: buffers to be compared.
00168   * @param  BufferLength: buffer's length
00169   * @retval PASSED: pBuffer identical to pBuffer1
00170   *         FAILED: pBuffer differs from pBuffer1
00171   */
00172 TestStatus Buffercmp(const uint32_t* pBuffer, uint32_t* pBuffer1, uint16_t BufferLength)
00173 {
00174   while(BufferLength--)
00175   {
00176     if(*pBuffer != *pBuffer1)
00177     {
00178       return FAILED;
00179     }
00180
00181     pBuffer++;
00182     pBuffer1++;
00183   }
00184
00185   return PASSED;
00186 }
00187
00188 #ifdef  USE_FULL_ASSERT
00189
00190 /**
00191   * @brief  Reports the name of the source file and the source line number
00192   *         where the assert_param error has occurred.
00193   * @param  file: pointer to the source file name
00194   * @param  line: assert_param error line source number
00195   * @retval None
00196   */
00197 void assert_failed(uint8_t* file, uint32_t line)
00198 {
00199   /* User can add his own implementation to report the file name and line number,
00200      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00201
00202   /* Infinite loop */
00203   while (1)
00204   {
00205   }
00206 }
00207
00208 #endif
00209
00210 /**
00211   * @}
00212   */
00213
00214 /**
00215   * @}
00216   */
00217
00218 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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STM32F10x_StdPeriph_Examples/DMA/FSMC/stm32f10x_conf.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    DMA/FSMC/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052 /* Exported types ------------------------------------------------------------*/
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Uncomment the line below to expanse the "assert_param" macro in the
00055    Standard Peripheral Library drivers code */
00056 /* #define USE_FULL_ASSERT    1 */
00057
00058 /* Exported macro ------------------------------------------------------------*/
00059 #ifdef  USE_FULL_ASSERT
00060
00061 /**
00062   * @brief  The assert_param macro is used for function's parameters check.
00063   * @param  expr: If expr is false, it calls assert_failed function which reports
00064   *         the name of the source file and the source line number of the call
00065   *         that failed. If expr is true, it returns no value.
00066   * @retval None
00067   */
00068   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00069 /* Exported functions ------------------------------------------------------- */
00070   void assert_failed(uint8_t* file, uint32_t line);
00071 #else
00072   #define assert_param(expr) ((void)0)
00073 #endif /* USE_FULL_ASSERT */
00074
00075 #endif /* __STM32F10x_CONF_H */
00076
00077 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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STM32F10x_StdPeriph_Examples/DMA/FSMC/stm32f10x_it.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    DMA/FSMC/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and peripherals
00009   *          interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026
00027 /** @addtogroup STM32F10x_StdPeriph_Examples
00028   * @{
00029   */
00030
00031 /** @addtogroup DMA_FSMC
00032   * @{
00033   */
00034
00035 /* Private typedef -----------------------------------------------------------*/
00036 /* Private define ------------------------------------------------------------*/
00037 /* Private macro -------------------------------------------------------------*/
00038 /* Private variables ---------------------------------------------------------*/
00039 /* Private function prototypes -----------------------------------------------*/
00040 /* Private functions ---------------------------------------------------------*/
00041
00042 /******************************************************************************/
00043 /*            Cortex-M3 Processor Exceptions Handlers                         */
00044 /******************************************************************************/
00045
00046 /**
00047   * @brief  This function handles NMI exception.
00048   * @param  None
00049   * @retval None
00050   */
00051 void NMI_Handler(void)
00052 {
00053 }
00054
00055 /**
00056   * @brief  This function handles Hard Fault exception.
00057   * @param  None
00058   * @retval None
00059   */
00060 void HardFault_Handler(void)
00061 {
00062   /* Go to infinite loop when Hard Fault exception occurs */
00063   while (1)
00064   {
00065   }
00066 }
00067
00068 /**
00069   * @brief  This function handles Memory Manage exception.
00070   * @param  None
00071   * @retval None
00072   */
00073 void MemManage_Handler(void)
00074 {
00075   /* Go to infinite loop when Memory Manage exception occurs */
00076   while (1)
00077   {
00078   }
00079 }
00080
00081 /**
00082   * @brief  This function handles Bus Fault exception.
00083   * @param  None
00084   * @retval None
00085   */
00086 void BusFault_Handler(void)
00087 {
00088   /* Go to infinite loop when Bus Fault exception occurs */
00089   while (1)
00090   {
00091   }
00092 }
00093
00094 /**
00095   * @brief  This function handles Usage Fault exception.
00096   * @param  None
00097   * @retval None
00098   */
00099 void UsageFault_Handler(void)
00100 {
00101   /* Go to infinite loop when Usage Fault exception occurs */
00102   while (1)
00103   {
00104   }
00105 }
00106
00107 /**
00108   * @brief  This function handles SVCall exception.
00109   * @param  None
00110   * @retval None
00111   */
00112 void SVC_Handler(void)
00113 {
00114 }
00115
00116 /**
00117   * @brief  This function handles Debug Monitor exception.
00118   * @param  None
00119   * @retval None
00120   */
00121 void DebugMon_Handler(void)
00122 {
00123 }
00124
00125 /**
00126   * @brief  This function handles PendSV_Handler exception.
00127   * @param  None
00128   * @retval None
00129   */
00130 void PendSV_Handler(void)
00131 {
00132 }
00133
00134 /**
00135   * @brief  This function handles SysTick Handler.
00136   * @param  None
00137   * @retval None
00138   */
00139 void SysTick_Handler(void)
00140 {
00141 }
00142
00143 /******************************************************************************/
00144 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00145 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00146 /*  available peripheral interrupt handler's name please refer to the startup */
00147 /*  file (startup_stm32f10x_xx.s).                                            */
00148 /******************************************************************************/
00149
00150 /**
00151   * @brief  This function handles PPP interrupt request.
00152   * @param  None
00153   * @retval None
00154   */
00155 /*void PPP_IRQHandler(void)
00156 {
00157 }*/
00158
00159 /**
00160   * @}
00161   */
00162
00163 /**
00164   * @}
00165   */
00166
00167 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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STM32F10x_StdPeriph_Examples/DMA/FSMC/stm32f10x_it.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    DMA/FSMC/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043
00044 #endif /* __STM32F10x_IT_H */
00045
00046 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/main.c

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00001 /**
00002   ******************************************************************************
00003   * @file    DMA/I2C_RAM/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x.h"
00024
00025 /** @addtogroup STM32F10x_StdPeriph_Examples
00026   * @{
00027   */
00028
00029 /** @addtogroup DMA_I2C_RAM
00030   * @{
00031   */
00032
00033 /* Private typedef -----------------------------------------------------------*/
00034 typedef enum { FAILED = 0, PASSED = !FAILED} TestStatus;
00035
00036 /* Private define ------------------------------------------------------------*/
00037 #define I2C1_DR_Address        0x40005410
00038 #define I2C2_DR_Address        0x40005810
00039 #define I2C1_SLAVE_ADDRESS7    0x30
00040 #define I2C2_SLAVE_ADDRESS7    0x30
00041 #define BufferSize             8
00042 #define ClockSpeed             100000
00043
00044 /* Private macro -------------------------------------------------------------*/
00045 /* Private variables ---------------------------------------------------------*/
00046 I2C_InitTypeDef  I2C_InitStructure;
00047 DMA_InitTypeDef  DMA_InitStructure;
00048 uint8_t I2C1_Buffer_Tx[BufferSize] = {1, 2, 3, 4, 5, 6, 7, 8};
00049 uint8_t I2C2_Buffer_Rx[BufferSize];
00050 uint8_t Tx_Idx = 0, Rx_Idx = 0;
00051 volatile TestStatus TransferStatus;
00052
00053 /* Private function prototypes -----------------------------------------------*/
00054 void RCC_Configuration(void);
00055 void GPIO_Configuration(void);
00056 TestStatus Buffercmp(uint8_t* pBuffer, uint8_t* pBuffer1, uint16_t BufferLength);
00057
00058 /* Private functions ---------------------------------------------------------*/
00059
00060 /**
00061   * @brief   Main program
00062   * @param  None
00063   * @retval None
00064   */
00065 int main(void)
00066 {
00067   /*!< At this stage the microcontroller clock setting is already configured,
00068        this is done through SystemInit() function which is called from startup
00069        file (startup_stm32f10x_xx.s) before to branch to application main.
00070        To reconfigure the default setting of SystemInit() function, refer to
00071        system_stm32f10x.c file
00072      */
00073
00074   /* System Clocks Configuration */
00075   RCC_Configuration();
00076
00077   /* Configure the GPIO ports */
00078   GPIO_Configuration();
00079
00080   /* DMA1 channel5 configuration ----------------------------------------------*/
00081   DMA_DeInit(DMA1_Channel5);
00082   DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)I2C2_DR_Address;
00083   DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)I2C2_Buffer_Rx;
00084   DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
00085   DMA_InitStructure.DMA_BufferSize = BufferSize;
00086   DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
00087   DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
00088   DMA_InitStructure.DMA_PeripheralDataSize = DMA_MemoryDataSize_Byte;
00089   DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
00090   DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
00091   DMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh;
00092   DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
00093   DMA_Init(DMA1_Channel5, &DMA_InitStructure);
00094
00095   /* DMA1 channel6 configuration ----------------------------------------------*/
00096   DMA_DeInit(DMA1_Channel6);
00097   DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)I2C1_DR_Address;
00098   DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)I2C1_Buffer_Tx;
00099   DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
00100   DMA_InitStructure.DMA_Priority = DMA_Priority_High;
00101   DMA_Init(DMA1_Channel6, &DMA_InitStructure);
00102
00103   /* Enable I2C1 and I2C2 ----------------------------------------------------*/
00104   I2C_Cmd(I2C1, ENABLE);
00105   I2C_Cmd(I2C2, ENABLE);
00106
00107   /* I2C1 configuration ------------------------------------------------------*/
00108   I2C_InitStructure.I2C_Mode = I2C_Mode_I2C;
00109   I2C_InitStructure.I2C_DutyCycle = I2C_DutyCycle_2;
00110   I2C_InitStructure.I2C_OwnAddress1 = I2C1_SLAVE_ADDRESS7;
00111   I2C_InitStructure.I2C_Ack = I2C_Ack_Enable;
00112   I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
00113   I2C_InitStructure.I2C_ClockSpeed = ClockSpeed;
00114   I2C_Init(I2C1, &I2C_InitStructure);
00115   /* I2C2 configuration ------------------------------------------------------*/
00116   I2C_InitStructure.I2C_OwnAddress1 = I2C2_SLAVE_ADDRESS7;
00117   I2C_Init(I2C2, &I2C_InitStructure);
00118
00119   /*----- Transmission Phase -----*/
00120   /* Send I2C1 START condition */
00121   I2C_GenerateSTART(I2C1, ENABLE);
00122   /* Test on I2C1 EV5 and clear it */
00123   while(!I2C_CheckEvent(I2C1, I2C_EVENT_MASTER_MODE_SELECT));
00124   /* Send I2C2 slave Address for write */
00125   I2C_Send7bitAddress(I2C1, I2C2_SLAVE_ADDRESS7, I2C_Direction_Transmitter);
00126   /* Test on I2C2 EV1 and clear it */
00127   while(!I2C_CheckEvent(I2C2, I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED));
00128   /* Test on I2C1 EV6 and clear it */
00129   while(!I2C_CheckEvent(I2C1, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED));
00130
00131   /* Enable I2C2 DMA */
00132   I2C_DMACmd(I2C2, ENABLE);
00133   /* Enable I2C1 DMA */
00134   I2C_DMACmd(I2C1, ENABLE);
00135
00136   /* Enable DMA1 Channel5 */
00137   DMA_Cmd(DMA1_Channel5, ENABLE);
00138   /* Enable DMA1 Channel6 */
00139   DMA_Cmd(DMA1_Channel6, ENABLE);
00140
00141   /* DMA1 Channel5 transfer complete test */
00142   while(!DMA_GetFlagStatus(DMA1_FLAG_TC5));
00143   /* DMA1 Channel6 transfer complete test */
00144   while(!DMA_GetFlagStatus(DMA1_FLAG_TC6));
00145
00146   /* Send I2C1 STOP Condition */
00147   I2C_GenerateSTOP(I2C1, ENABLE);
00148   /* Test on I2C2 EV4 */
00149   while(!I2C_CheckEvent(I2C2, I2C_EVENT_SLAVE_STOP_DETECTED));
00150   /* Clear I2C2 STOPF flag: read operation to I2C_SR1 followed by a
00151   write operation to I2C_CR1 */
00152   (void)(I2C_GetFlagStatus(I2C2, I2C_FLAG_STOPF));
00153   I2C_Cmd(I2C2, ENABLE);
00154
00155
00156   /* Check if the transmitted and received data are equal */
00157   TransferStatus = Buffercmp(I2C1_Buffer_Tx, I2C2_Buffer_Rx, BufferSize);
00158   /* TransferStatus = PASSED, if the transmitted and received data
00159      are the same */
00160   /* TransferStatus = FAILED, if the transmitted and received data
00161      are different */
00162
00163   while (1)
00164   {
00165   }
00166 }
00167
00168 /**
00169   * @brief  Configures the different system clocks.
00170   * @param  None
00171   * @retval None
00172   */
00173 void RCC_Configuration(void)
00174 {
00175   /* Enable DMA1 clock */
00176   RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE);
00177   /* Enable GPIOB clock */
00178   RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE);
00179   /* Enable I2C1 and I2C2 clock */
00180   RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2C1 | RCC_APB1Periph_I2C2, ENABLE);
00181 }
00182
00183 /**
00184   * @brief  Configures the different GPIO ports.
00185   * @param  None
00186   * @retval None
00187   */
00188 void GPIO_Configuration(void)
00189 {
00190   GPIO_InitTypeDef GPIO_InitStructure;
00191
00192   /* Configure I2C1 pins: SCL and SDA */
00193   GPIO_InitStructure.GPIO_Pin =  GPIO_Pin_6 | GPIO_Pin_7;
00194   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00195   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_OD;
00196   GPIO_Init(GPIOB, &GPIO_InitStructure);
00197
00198   /* Configure I2C2 pins: SCL and SDA */
00199   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10 | GPIO_Pin_11;
00200   GPIO_Init(GPIOB, &GPIO_InitStructure);
00201 }
00202
00203 /**
00204   * @brief  Compares two buffers.
00205   * @param  pBuffer, pBuffer1: buffers to be compared.
00206   * @param  BufferLength: buffer's length
00207   * @retval PASSED: pBuffer identical to pBuffer1
00208   *         FAILED: pBuffer differs from pBuffer1
00209   */
00210 TestStatus Buffercmp(uint8_t* pBuffer, uint8_t* pBuffer1, uint16_t BufferLength)
00211 {
00212   while(BufferLength--)
00213   {
00214     if(*pBuffer != *pBuffer1)
00215     {
00216       return FAILED;
00217     }
00218
00219     pBuffer++;
00220     pBuffer1++;
00221   }
00222
00223   return PASSED;
00224 }
00225
00226 #ifdef  USE_FULL_ASSERT
00227
00228 /**
00229   * @brief  Reports the name of the source file and the source line number
00230   *         where the assert_param error has occurred.
00231   * @param  file: pointer to the source file name
00232   * @param  line: assert_param error line source number
00233   * @retval None
00234   */
00235 void assert_failed(uint8_t* file, uint32_t line)
00236 {
00237   /* User can add his own implementation to report the file name and line number,
00238      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00239
00240   /* Infinite loop */
00241   while (1)
00242   {
00243   }
00244 }
00245
00246 #endif
00247
00248 /**
00249   * @}
00250   */
00251
00252 /**
00253   * @}
00254   */
00255
00256 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/stm32f10x_conf.h

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00001 /**
00002   ******************************************************************************
00003   * @file DMA/I2C_RAM/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052 /* Exported types ------------------------------------------------------------*/
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Uncomment the line below to expanse the "assert_param" macro in the
00055    Standard Peripheral Library drivers code */
00056 /* #define USE_FULL_ASSERT    1 */
00057
00058 /* Exported macro ------------------------------------------------------------*/
00059 #ifdef  USE_FULL_ASSERT
00060
00061 /**
00062   * @brief  The assert_param macro is used for function's parameters check.
00063   * @param  expr: If expr is false, it calls assert_failed function which reports
00064   *         the name of the source file and the source line number of the call
00065   *         that failed. If expr is true, it returns no value.
00066   * @retval None
00067   */
00068   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00069 /* Exported functions ------------------------------------------------------- */
00070   void assert_failed(uint8_t* file, uint32_t line);
00071 #else
00072   #define assert_param(expr) ((void)0)
00073 #endif /* USE_FULL_ASSERT */
00074
00075 #endif /* __STM32F10x_CONF_H */
00076
00077 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/stm32f10x_it.c

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00001 /**
00002   ******************************************************************************
00003   * @file    DMA/I2C_RAM/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and peripherals
00009   *          interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026
00027 /** @addtogroup STM32F10x_StdPeriph_Examples
00028   * @{
00029   */
00030
00031 /** @addtogroup DMA_I2C_RAM
00032   * @{
00033   */
00034
00035 /* Private typedef -----------------------------------------------------------*/
00036 /* Private define ------------------------------------------------------------*/
00037 /* Private macro -------------------------------------------------------------*/
00038 /* Private variables ---------------------------------------------------------*/
00039 /* Private function prototypes -----------------------------------------------*/
00040 /* Private functions ---------------------------------------------------------*/
00041
00042 /******************************************************************************/
00043 /*            Cortex-M3 Processor Exceptions Handlers                         */
00044 /******************************************************************************/
00045
00046 /**
00047   * @brief  This function handles NMI exception.
00048   * @param  None
00049   * @retval None
00050   */
00051 void NMI_Handler(void)
00052 {
00053 }
00054
00055 /**
00056   * @brief  This function handles Hard Fault exception.
00057   * @param  None
00058   * @retval None
00059   */
00060 void HardFault_Handler(void)
00061 {
00062   /* Go to infinite loop when Hard Fault exception occurs */
00063   while (1)
00064   {
00065   }
00066 }
00067
00068 /**
00069   * @brief  This function handles Memory Manage exception.
00070   * @param  None
00071   * @retval None
00072   */
00073 void MemManage_Handler(void)
00074 {
00075   /* Go to infinite loop when Memory Manage exception occurs */
00076   while (1)
00077   {
00078   }
00079 }
00080
00081 /**
00082   * @brief  This function handles Bus Fault exception.
00083   * @param  None
00084   * @retval None
00085   */
00086 void BusFault_Handler(void)
00087 {
00088   /* Go to infinite loop when Bus Fault exception occurs */
00089   while (1)
00090   {
00091   }
00092 }
00093
00094 /**
00095   * @brief  This function handles Usage Fault exception.
00096   * @param  None
00097   * @retval None
00098   */
00099 void UsageFault_Handler(void)
00100 {
00101   /* Go to infinite loop when Usage Fault exception occurs */
00102   while (1)
00103   {
00104   }
00105 }
00106
00107 /**
00108   * @brief  This function handles SVCall exception.
00109   * @param  None
00110   * @retval None
00111   */
00112 void SVC_Handler(void)
00113 {
00114 }
00115
00116 /**
00117   * @brief  This function handles Debug Monitor exception.
00118   * @param  None
00119   * @retval None
00120   */
00121 void DebugMon_Handler(void)
00122 {
00123 }
00124
00125 /**
00126   * @brief  This function handles PendSV_Handler exception.
00127   * @param  None
00128   * @retval None
00129   */
00130 void PendSV_Handler(void)
00131 {
00132 }
00133
00134 /**
00135   * @brief  This function handles SysTick Handler.
00136   * @param  None
00137   * @retval None
00138   */
00139 void SysTick_Handler(void)
00140 {
00141 }
00142
00143 /******************************************************************************/
00144 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00145 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00146 /*  available peripheral interrupt handler's name please refer to the startup */
00147 /*  file (startup_stm32f10x_xx.s).                                            */
00148 /******************************************************************************/
00149
00150 /**
00151   * @brief  This function handles PPP interrupt request.
00152   * @param  None
00153   * @retval None
00154   */
00155 /*void PPP_IRQHandler(void)
00156 {
00157 }*/
00158
00159 /**
00160   * @}
00161   */
00162
00163 /**
00164   * @}
00165   */
00166
00167 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/stm32f10x_it.h

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00001 /**
00002   ******************************************************************************
00003   * @file DMA/I2C_RAM/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043
00044 #endif /* __STM32F10x_IT_H */
00045
00046 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/main.c

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00001 /**
00002   ******************************************************************************
00003   * @file    DMA/SPI_RAM/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x.h"
00024 #include "platform_config.h"
00025 #include "stm32_eval.h"
00026
00027 /** @addtogroup STM32F10x_StdPeriph_Examples
00028   * @{
00029   */
00030
00031 /** @addtogroup DMA_SPI_RAM
00032   * @{
00033   */
00034
00035 /* Private typedef -----------------------------------------------------------*/
00036 typedef enum { FAILED = 0, PASSED = !FAILED} TestStatus;
00037
00038 /* Private define ------------------------------------------------------------*/
00039 #define BufferSize         32
00040 #define CRCPolynomial      7
00041
00042 /* Private macro -------------------------------------------------------------*/
00043 /* Private variables ---------------------------------------------------------*/
00044 SPI_InitTypeDef    SPI_InitStructure;
00045 DMA_InitTypeDef    DMA_InitStructure;
00046 uint8_t SPI_MASTER_Buffer_Rx[BufferSize], SPI_SLAVE_Buffer_Rx[BufferSize];
00047 volatile uint8_t SPI_MASTERCRCValue = 0, SPI_SLAVECRCValue = 0;
00048 volatile TestStatus TransferStatus1 = FAILED, TransferStatus2 = FAILED;
00049
00050 uint8_t SPI_MASTER_Buffer_Tx[BufferSize] = {0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,
00051                                             0x09,0x0A,0x0B,0x0C,0x0D,0x0E,0x0F,0x10,
00052                                             0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x18,
00053                                             0x19,0x1A,0x1B,0x1C,0x1D,0x1E,0x1F,0x20};
00054
00055 uint8_t SPI_SLAVE_Buffer_Tx[BufferSize] = {0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,
00056                                            0x59,0x5A,0x5B,0x5C,0x5D,0x5E,0x5F,0x60,
00057                                            0x61,0x62,0x63,0x64,0x65,0x66,0x67,0x68,
00058                                            0x69,0x6A,0x6B,0x6C,0x6D,0x6E,0x6F,0x70};
00059
00060 /* Private function prototypes -----------------------------------------------*/
00061 void RCC_Configuration(void);
00062 void GPIO_Configuration(void);
00063 TestStatus Buffercmp(uint8_t* pBuffer, uint8_t* pBuffer1, uint16_t BufferLength);
00064
00065 /* Private functions ---------------------------------------------------------*/
00066
00067 /**
00068   * @brief  Main program
00069   * @param  None
00070   * @retval None
00071   */
00072 int main(void)
00073 {
00074   /*!< At this stage the microcontroller clock setting is already configured,
00075        this is done through SystemInit() function which is called from startup
00076        file (startup_stm32f10x_xx.s) before to branch to application main.
00077        To reconfigure the default setting of SystemInit() function, refer to
00078        system_stm32f10x.c file
00079      */
00080
00081   /* Configure the STM32_EVAL LED */
00082   STM_EVAL_LEDInit(LED1);
00083   STM_EVAL_LEDInit(LED2);
00084   /* Turn Off LED1 and LED2 */
00085   STM_EVAL_LEDOff(LED1);
00086   STM_EVAL_LEDOff(LED2);
00087
00088   /* System Clocks Configuration */
00089   RCC_Configuration();
00090
00091   /* Configure the GPIO ports */
00092   GPIO_Configuration();
00093
00094   /* SPI_MASTER configuration ------------------------------------------------*/
00095   SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
00096   SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
00097   SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
00098   SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low;
00099   SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge;
00100   SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
00101   SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_8;
00102   SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
00103   SPI_InitStructure.SPI_CRCPolynomial = CRCPolynomial;
00104   SPI_Init(SPI_MASTER, &SPI_InitStructure);
00105
00106   /* SPI_SLAVE configuration -------------------------------------------------*/
00107   SPI_InitStructure.SPI_Mode = SPI_Mode_Slave;
00108   SPI_Init(SPI_SLAVE, &SPI_InitStructure);
00109
00110   /* SPI_MASTER_Rx_DMA_Channel configuration ---------------------------------*/
00111   DMA_DeInit(SPI_MASTER_Rx_DMA_Channel);
00112   DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)SPI_MASTER_DR_Base;
00113   DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)SPI_MASTER_Buffer_Rx;
00114   DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
00115   DMA_InitStructure.DMA_BufferSize = BufferSize;
00116   DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
00117   DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
00118   DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
00119   DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
00120   DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
00121   DMA_InitStructure.DMA_Priority = DMA_Priority_High;
00122   DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
00123   DMA_Init(SPI_MASTER_Rx_DMA_Channel, &DMA_InitStructure);
00124
00125   /* SPI_MASTER_Tx_DMA_Channel configuration ---------------------------------*/
00126   DMA_DeInit(SPI_MASTER_Tx_DMA_Channel);
00127   DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)SPI_MASTER_DR_Base;
00128   DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)SPI_MASTER_Buffer_Tx;
00129   DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
00130   DMA_InitStructure.DMA_Priority = DMA_Priority_Low;
00131   DMA_Init(SPI_MASTER_Tx_DMA_Channel, &DMA_InitStructure);
00132
00133   /* SPI_SLAVE_Rx_DMA_Channel configuration ----------------------------------*/
00134   DMA_DeInit(SPI_SLAVE_Rx_DMA_Channel);
00135   DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)SPI_SLAVE_DR_Base;
00136   DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)SPI_SLAVE_Buffer_Rx;
00137   DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
00138   DMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh;
00139   DMA_Init(SPI_SLAVE_Rx_DMA_Channel, &DMA_InitStructure);
00140
00141   /* SPI_SLAVE_Tx_DMA_Channel configuration ----------------------------------*/
00142   DMA_DeInit(SPI_SLAVE_Tx_DMA_Channel);
00143   DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)SPI_SLAVE_DR_Base;
00144   DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)SPI_SLAVE_Buffer_Tx;
00145   DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
00146   DMA_InitStructure.DMA_Priority = DMA_Priority_Medium;
00147   DMA_Init(SPI_SLAVE_Tx_DMA_Channel, &DMA_InitStructure);
00148
00149   /* Enable SPI_MASTER DMA Tx request */
00150   SPI_I2S_DMACmd(SPI_MASTER, SPI_I2S_DMAReq_Tx, ENABLE);
00151   /* Enable SPI_MASTER DMA Rx request */
00152   SPI_I2S_DMACmd(SPI_MASTER, SPI_I2S_DMAReq_Rx, ENABLE);
00153   /* Enable SPI_SLAVE DMA Tx request */
00154   SPI_I2S_DMACmd(SPI_SLAVE, SPI_I2S_DMAReq_Tx, ENABLE);
00155   /* Enable SPI_SLAVE DMA Rx request */
00156   SPI_I2S_DMACmd(SPI_SLAVE, SPI_I2S_DMAReq_Rx, ENABLE);
00157
00158   /* Enable SPI_MASTER CRC calculation */
00159   SPI_CalculateCRC(SPI_MASTER, ENABLE);
00160   /* Enable SPI_SLAVE CRC calculation */
00161   SPI_CalculateCRC(SPI_SLAVE, ENABLE);
00162
00163   /* Enable SPI_SLAVE */
00164   SPI_Cmd(SPI_SLAVE, ENABLE);
00165   /* Enable SPI_MASTER */
00166   SPI_Cmd(SPI_MASTER, ENABLE);
00167
00168   /* Enable DMA channels */
00169   DMA_Cmd(SPI_MASTER_Rx_DMA_Channel, ENABLE);
00170   DMA_Cmd(SPI_SLAVE_Rx_DMA_Channel, ENABLE);
00171   DMA_Cmd(SPI_SLAVE_Tx_DMA_Channel, ENABLE);
00172   DMA_Cmd(SPI_MASTER_Tx_DMA_Channel, ENABLE);
00173
00174   /* Transfer complete */
00175   while(!DMA_GetFlagStatus(SPI_MASTER_Rx_DMA_FLAG));
00176   while(!DMA_GetFlagStatus(SPI_SLAVE_Rx_DMA_FLAG));
00177   while(!DMA_GetFlagStatus(SPI_SLAVE_Tx_DMA_FLAG));
00178   while(!DMA_GetFlagStatus(SPI_MASTER_Tx_DMA_FLAG));
00179
00180   /* Wait for SPI_MASTER data reception: CRC transmitted by SPI_SLAVE */
00181   while(SPI_I2S_GetFlagStatus(SPI_MASTER, SPI_I2S_FLAG_RXNE) == RESET);
00182   /* Wait for SPI_SLAVE data reception: CRC transmitted by SPI_MASTER */
00183   while(SPI_I2S_GetFlagStatus(SPI_SLAVE, SPI_I2S_FLAG_RXNE) == RESET);
00184
00185   /* Check the correctness of written dada */
00186   TransferStatus1 = Buffercmp(SPI_SLAVE_Buffer_Rx, SPI_MASTER_Buffer_Tx, BufferSize);
00187   TransferStatus2 = Buffercmp(SPI_MASTER_Buffer_Rx, SPI_SLAVE_Buffer_Tx, BufferSize);
00188   /* TransferStatus1, TransferStatus2 = PASSED, if the data transmitted and received
00189      are correct */
00190   /* TransferStatus1, TransferStatus2 = FAILED, if the data transmitted and received
00191      are different */
00192
00193   /* Test on the SPI_MASTER CRCR ERROR flag */
00194   if ((SPI_I2S_GetFlagStatus(SPI_MASTER, SPI_FLAG_CRCERR)) != RESET)
00195   {
00196     TransferStatus1 = FAILED;
00197   }
00198   /* Test on the SPI_SLAVE CRCR ERROR flag */
00199   if ((SPI_I2S_GetFlagStatus(SPI_SLAVE, SPI_FLAG_CRCERR)) != RESET)
00200   {
00201     TransferStatus2 = FAILED;
00202   }
00203
00204   /* Read SPI_MASTER received CRC value */
00205   SPI_MASTERCRCValue = SPI_I2S_ReceiveData(SPI_MASTER);
00206   /* Read SPI_SLAVE received CRC value */
00207   SPI_SLAVECRCValue = SPI_I2S_ReceiveData(SPI_SLAVE);
00208
00209   if (TransferStatus1 != FAILED)
00210   {
00211     /* OK */
00212     /* Turn on LD1 */
00213     STM_EVAL_LEDOn(LED1);
00214   }
00215   else
00216   {
00217     /* KO */
00218     /* Turn Off LD1 */
00219     STM_EVAL_LEDOff(LED1);
00220   }
00221
00222   if (TransferStatus2 != FAILED)
00223   {
00224     /* OK */
00225     /* Turn on LD2 */
00226     STM_EVAL_LEDOn(LED2);
00227   }
00228   else
00229   {
00230     /* KO */
00231     /* Turn Off LD2 */
00232     STM_EVAL_LEDOff(LED2);
00233   }
00234
00235   while (1)
00236   {
00237   }
00238 }
00239
00240 /**
00241   * @brief  Configures the different system clocks.
00242   * @param  None
00243   * @retval None
00244   */
00245 void RCC_Configuration(void)
00246 {
00247   /* PCLK2 = HCLK/2 */
00248   RCC_PCLK2Config(RCC_HCLK_Div2);
00249
00250   /* Enable peripheral clocks ------------------------------------------------*/
00251   /* Enable DMA1 or/and DMA2 clock */
00252   RCC_AHBPeriphClockCmd(SPI_MASTER_DMA_CLK | SPI_SLAVE_DMA_CLK, ENABLE);
00253
00254 #ifdef USE_STM3210C_EVAL
00255   /* Enable GPIO clock for SPI_MASTER and SPI_SLAVE */
00256   RCC_APB2PeriphClockCmd(SPI_MASTER_GPIO_CLK | SPI_SLAVE_GPIO_CLK |
00257   RCC_APB2Periph_AFIO, ENABLE);
00258
00259   /* Enable SPI_MASTER Periph clock */
00260   RCC_APB1PeriphClockCmd(SPI_MASTER_CLK, ENABLE);
00261
00262 #else
00263   /* Enable SPI_MASTER clock and GPIO clock for SPI_MASTER and SPI_SLAVE */
00264   RCC_APB2PeriphClockCmd(SPI_MASTER_GPIO_CLK | SPI_SLAVE_GPIO_CLK |
00265                          SPI_MASTER_CLK, ENABLE);
00266 #endif
00267   /* Enable SPI_SLAVE Periph clock */
00268   RCC_APB1PeriphClockCmd(SPI_SLAVE_CLK, ENABLE);
00269 }
00270
00271 /**
00272   * @brief  Configures the different GPIO ports.
00273   * @param  None
00274   * @retval None
00275   */
00276 void GPIO_Configuration(void)
00277 {
00278   GPIO_InitTypeDef GPIO_InitStructure;
00279
00280 #ifdef USE_STM3210C_EVAL
00281   /* Enable SPI3 Pins Software Remapping */
00282   GPIO_PinRemapConfig(GPIO_Remap_SPI3, ENABLE);
00283 #endif
00284
00285   /* Configure SPI_MASTER pins: SCK and MOSI */
00286   GPIO_InitStructure.GPIO_Pin = SPI_MASTER_PIN_SCK | SPI_MASTER_PIN_MOSI;
00287   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00288   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
00289   GPIO_Init(SPI_MASTER_GPIO, &GPIO_InitStructure);
00290   /* Configure SPI_MASTER pins:  MISO */
00291   GPIO_InitStructure.GPIO_Pin = SPI_MASTER_PIN_MISO;
00292   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
00293   GPIO_Init(SPI_MASTER_GPIO, &GPIO_InitStructure);
00294
00295   /* Configure SPI_SLAVE pins: SCK and MOSI */
00296   GPIO_InitStructure.GPIO_Pin = SPI_SLAVE_PIN_SCK | SPI_SLAVE_PIN_MOSI;
00297   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
00298   GPIO_Init(SPI_SLAVE_GPIO, &GPIO_InitStructure);
00299   /* Configure SPI_SLAVE pins: MISO  */
00300   GPIO_InitStructure.GPIO_Pin = SPI_SLAVE_PIN_MISO ;
00301   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
00302   GPIO_Init(SPI_SLAVE_GPIO, &GPIO_InitStructure);
00303 }
00304
00305 /**
00306   * @brief  Compares two buffers.
00307   * @param  pBuffer, pBuffer1: buffers to be compared.
00308   * @param  BufferLength: buffer's length
00309   * @retval PASSED: pBuffer identical to pBuffer1
00310   *         FAILED: pBuffer differs from pBuffer1
00311   */
00312 TestStatus Buffercmp(uint8_t* pBuffer, uint8_t* pBuffer1, uint16_t BufferLength)
00313 {
00314   while(BufferLength--)
00315   {
00316     if(*pBuffer != *pBuffer1)
00317     {
00318       return FAILED;
00319     }
00320
00321     pBuffer++;
00322     pBuffer1++;
00323   }
00324
00325   return PASSED;
00326 }
00327
00328 #ifdef  USE_FULL_ASSERT
00329
00330 /**
00331   * @brief  Reports the name of the source file and the source line number
00332   *         where the assert_param error has occurred.
00333   * @param  file: pointer to the source file name
00334   * @param  line: assert_param error line source number
00335   * @retval None
00336   */
00337 void assert_failed(uint8_t* file, uint32_t line)
00338 {
00339   /* User can add his own implementation to report the file name and line number,
00340      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00341
00342   /* Infinite loop */
00343   while (1)
00344   {
00345   }
00346 }
00347
00348 #endif
00349
00350 /**
00351   * @}
00352   */
00353
00354 /**
00355   * @}
00356   */
00357
00358 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/stm32f10x_conf.h

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00001 /**
00002   ******************************************************************************
00003   * @file DMA/SPI_RAM/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052 /* Exported types ------------------------------------------------------------*/
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Uncomment the line below to expanse the "assert_param" macro in the
00055    Standard Peripheral Library drivers code */
00056 /* #define USE_FULL_ASSERT    1 */
00057
00058 /* Exported macro ------------------------------------------------------------*/
00059 #ifdef  USE_FULL_ASSERT
00060
00061 /**
00062   * @brief  The assert_param macro is used for function's parameters check.
00063   * @param  expr: If expr is false, it calls assert_failed function which reports
00064   *         the name of the source file and the source line number of the call
00065   *         that failed. If expr is true, it returns no value.
00066   * @retval None
00067   */
00068   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00069 /* Exported functions ------------------------------------------------------- */
00070   void assert_failed(uint8_t* file, uint32_t line);
00071 #else
00072   #define assert_param(expr) ((void)0)
00073 #endif /* USE_FULL_ASSERT */
00074
00075 #endif /* __STM32F10x_CONF_H */
00076
00077 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/stm32f10x_it.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    DMA/SPI_RAM/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and peripherals
00009   *          interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026
00027 /** @addtogroup STM32F10x_StdPeriph_Examples
00028   * @{
00029   */
00030
00031 /** @addtogroup DMA_SPI_RAM
00032   * @{
00033   */
00034
00035 /* Private typedef -----------------------------------------------------------*/
00036 /* Private define ------------------------------------------------------------*/
00037 /* Private macro -------------------------------------------------------------*/
00038 /* Private variables ---------------------------------------------------------*/
00039 /* Private function prototypes -----------------------------------------------*/
00040 /* Private functions ---------------------------------------------------------*/
00041
00042 /******************************************************************************/
00043 /*            Cortex-M3 Processor Exceptions Handlers                         */
00044 /******************************************************************************/
00045
00046 /**
00047   * @brief  This function handles NMI exception.
00048   * @param  None
00049   * @retval None
00050   */
00051 void NMI_Handler(void)
00052 {
00053 }
00054
00055 /**
00056   * @brief  This function handles Hard Fault exception.
00057   * @param  None
00058   * @retval None
00059   */
00060 void HardFault_Handler(void)
00061 {
00062   /* Go to infinite loop when Hard Fault exception occurs */
00063   while (1)
00064   {
00065   }
00066 }
00067
00068 /**
00069   * @brief  This function handles Memory Manage exception.
00070   * @param  None
00071   * @retval None
00072   */
00073 void MemManage_Handler(void)
00074 {
00075   /* Go to infinite loop when Memory Manage exception occurs */
00076   while (1)
00077   {
00078   }
00079 }
00080
00081 /**
00082   * @brief  This function handles Bus Fault exception.
00083   * @param  None
00084   * @retval None
00085   */
00086 void BusFault_Handler(void)
00087 {
00088   /* Go to infinite loop when Bus Fault exception occurs */
00089   while (1)
00090   {
00091   }
00092 }
00093
00094 /**
00095   * @brief  This function handles Usage Fault exception.
00096   * @param  None
00097   * @retval None
00098   */
00099 void UsageFault_Handler(void)
00100 {
00101   /* Go to infinite loop when Usage Fault exception occurs */
00102   while (1)
00103   {
00104   }
00105 }
00106
00107 /**
00108   * @brief  This function handles SVCall exception.
00109   * @param  None
00110   * @retval None
00111   */
00112 void SVC_Handler(void)
00113 {
00114 }
00115
00116 /**
00117   * @brief  This function handles Debug Monitor exception.
00118   * @param  None
00119   * @retval None
00120   */
00121 void DebugMon_Handler(void)
00122 {
00123 }
00124
00125 /**
00126   * @brief  This function handles PendSV_Handler exception.
00127   * @param  None
00128   * @retval None
00129   */
00130 void PendSV_Handler(void)
00131 {
00132 }
00133
00134 /**
00135   * @brief  This function handles SysTick Handler.
00136   * @param  None
00137   * @retval None
00138   */
00139 void SysTick_Handler(void)
00140 {
00141 }
00142
00143 /******************************************************************************/
00144 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00145 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00146 /*  available peripheral interrupt handler's name please refer to the startup */
00147 /*  file (startup_stm32f10x_xx.s).                                            */
00148 /******************************************************************************/
00149
00150 /**
00151   * @brief  This function handles PPP interrupt request.
00152   * @param  None
00153   * @retval None
00154   */
00155 /*void PPP_IRQHandler(void)
00156 {
00157 }*/
00158
00159 /**
00160   * @}
00161   */
00162
00163 /**
00164   * @}
00165   */
00166
00167 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/stm32f10x_it.h

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00001 /**
00002   ******************************************************************************
00003   * @file DMA/SPI_RAM/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043
00044 #endif /* __STM32F10x_IT_H */
00045
00046 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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  • EXTI_Config

STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/main.c

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00001 /**
00002   ******************************************************************************
00003   * @file    EXTI/EXTI_Config/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x.h"
00024 #include "stm32_eval.h"
00025
00026 /** @addtogroup STM32F10x_StdPeriph_Examples
00027   * @{
00028   */
00029
00030 /** @addtogroup EXTI_Config
00031   * @{
00032   */
00033
00034 /* Private typedef -----------------------------------------------------------*/
00035 /* Private define ------------------------------------------------------------*/
00036 /* Private macro -------------------------------------------------------------*/
00037 /* Private variables ---------------------------------------------------------*/
00038 EXTI_InitTypeDef   EXTI_InitStructure;
00039 GPIO_InitTypeDef   GPIO_InitStructure;
00040 NVIC_InitTypeDef   NVIC_InitStructure;
00041
00042 /* Private function prototypes -----------------------------------------------*/
00043 void EXTI0_Config(void);
00044 void EXTI9_5_Config(void);
00045
00046 /* Private functions ---------------------------------------------------------*/
00047
00048 /**
00049   * @brief  Main program.
00050   * @param  None
00051   * @retval None
00052   */
00053 int main(void)
00054 {
00055   /*!< At this stage the microcontroller clock setting is already configured,
00056        this is done through SystemInit() function which is called from startup
00057        file (startup_stm32f10x_xx.s) before to branch to application main.
00058        To reconfigure the default setting of SystemInit() function, refer to
00059        system_stm32f10x.c file
00060      */
00061
00062   /* Initialize LED1 and Key Button mounted on STM3210X-EVAL board */
00063   STM_EVAL_LEDInit(LED1);
00064   STM_EVAL_LEDInit(LED2);
00065
00066   /* Configure PA.00 in interrupt mode */
00067   EXTI0_Config();
00068
00069   /* Configure PB.09 or PG.08 in interrupt mode */
00070   EXTI9_5_Config();
00071
00072   /* Generate software interrupt: simulate a falling edge applied on EXTI0 line */
00073   EXTI_GenerateSWInterrupt(EXTI_Line0);
00074
00075   while (1)
00076   {
00077   }
00078 }
00079
00080 /**
00081   * @brief  Configure PA.00 in interrupt mode
00082   * @param  None
00083   * @retval None
00084   */
00085 void EXTI0_Config(void)
00086 {
00087   /* Enable GPIOA clock */
00088   RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);
00089
00090   /* Configure PA.00 pin as input floating */
00091   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0;
00092   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
00093   GPIO_Init(GPIOA, &GPIO_InitStructure);
00094
00095   /* Enable AFIO clock */
00096   RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE);
00097
00098   /* Connect EXTI0 Line to PA.00 pin */
00099   GPIO_EXTILineConfig(GPIO_PortSourceGPIOA, GPIO_PinSource0);
00100
00101   /* Configure EXTI0 line */
00102   EXTI_InitStructure.EXTI_Line = EXTI_Line0;
00103   EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
00104   EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;
00105   EXTI_InitStructure.EXTI_LineCmd = ENABLE;
00106   EXTI_Init(&EXTI_InitStructure);
00107
00108   /* Enable and set EXTI0 Interrupt to the lowest priority */
00109   NVIC_InitStructure.NVIC_IRQChannel = EXTI0_IRQn;
00110   NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x0F;
00111   NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x0F;
00112   NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
00113   NVIC_Init(&NVIC_InitStructure);
00114 }
00115
00116 /**
00117   * @brief  Configure PB.09 or PG.08 in interrupt mode
00118   * @param  None
00119   * @retval None
00120   */
00121 void EXTI9_5_Config(void)
00122 {
00123 #if defined (STM32F10X_HD_VL) || defined (STM32F10X_HD) || defined (STM32F10X_XL)
00124   /* Enable GPIOG clock */
00125   RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOG, ENABLE);
00126
00127   /* Configure PG.08 pin as input floating */
00128   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8;
00129   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
00130   GPIO_Init(GPIOG, &GPIO_InitStructure);
00131
00132   /* Enable AFIO clock */
00133   RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE);
00134   /* Connect EXTI8 Line to PG.08 pin */
00135   GPIO_EXTILineConfig(GPIO_PortSourceGPIOG, GPIO_PinSource8);
00136
00137   /* Configure EXTI8 line */
00138   EXTI_InitStructure.EXTI_Line = EXTI_Line8;
00139   EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
00140   EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling;
00141   EXTI_InitStructure.EXTI_LineCmd = ENABLE;
00142   EXTI_Init(&EXTI_InitStructure);
00143
00144   /* Enable and set EXTI9_5 Interrupt to the lowest priority */
00145   NVIC_InitStructure.NVIC_IRQChannel = EXTI9_5_IRQn;
00146   NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x0F;
00147   NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x0F;
00148   NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
00149
00150   NVIC_Init(&NVIC_InitStructure);
00151 #else
00152   /* Enable GPIOB clock */
00153   RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE);
00154
00155   /* Configure PB.09 pin as input floating */
00156   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;
00157   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
00158   GPIO_Init(GPIOB, &GPIO_InitStructure);
00159
00160   /* Enable AFIO clock */
00161   RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE);
00162   /* Connect EXTI9 Line to PB.09 pin */
00163   GPIO_EXTILineConfig(GPIO_PortSourceGPIOB, GPIO_PinSource9);
00164
00165   /* Configure EXTI9 line */
00166   EXTI_InitStructure.EXTI_Line = EXTI_Line9;
00167   EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
00168   EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling;
00169   EXTI_InitStructure.EXTI_LineCmd = ENABLE;
00170   EXTI_Init(&EXTI_InitStructure);
00171
00172   /* Enable and set EXTI9_5 Interrupt to the lowest priority */
00173   NVIC_InitStructure.NVIC_IRQChannel = EXTI9_5_IRQn;
00174   NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x0F;
00175   NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x0F;
00176   NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
00177
00178   NVIC_Init(&NVIC_InitStructure);
00179 #endif
00180 }
00181
00182 #ifdef  USE_FULL_ASSERT
00183
00184 /**
00185   * @brief  Reports the name of the source file and the source line number
00186   *         where the assert_param error has occurred.
00187   * @param  file: pointer to the source file name
00188   * @param  line: assert_param error line source number
00189   * @retval None
00190   */
00191 void assert_failed(uint8_t* file, uint32_t line)
00192 {
00193   /* User can add his own implementation to report the file name and line number,
00194      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00195
00196   /* Infinite loop */
00197   while (1)
00198   {
00199   }
00200 }
00201
00202 #endif
00203
00204 /**
00205   * @}
00206   */
00207
00208 /**
00209   * @}
00210   */
00211
00212 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/stm32f10x_conf.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    EXTI/EXTI_Config/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052 /* Exported types ------------------------------------------------------------*/
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Uncomment the line below to expanse the "assert_param" macro in the
00055    Standard Peripheral Library drivers code */
00056 /* #define USE_FULL_ASSERT    1 */
00057
00058 /* Exported macro ------------------------------------------------------------*/
00059 #ifdef  USE_FULL_ASSERT
00060
00061 /**
00062   * @brief  The assert_param macro is used for function's parameters check.
00063   * @param  expr: If expr is false, it calls assert_failed function which reports
00064   *         the name of the source file and the source line number of the call
00065   *         that failed. If expr is true, it returns no value.
00066   * @retval None
00067   */
00068   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00069 /* Exported functions ------------------------------------------------------- */
00070   void assert_failed(uint8_t* file, uint32_t line);
00071 #else
00072   #define assert_param(expr) ((void)0)
00073 #endif /* USE_FULL_ASSERT */
00074
00075 #endif /* __STM32F10x_CONF_H */
00076
00077 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/stm32f10x_it.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    EXTI/EXTI_Config/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and peripherals
00009   *          interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026 #include "stm32_eval.h"
00027
00028 /** @addtogroup STM32F10x_StdPeriph_Examples
00029   * @{
00030   */
00031
00032 /** @addtogroup EXTI_Config
00033   * @{
00034   */
00035
00036 /* Private typedef -----------------------------------------------------------*/
00037 /* Private define ------------------------------------------------------------*/
00038 /* Private macro -------------------------------------------------------------*/
00039 /* Private variables ---------------------------------------------------------*/
00040 /* Private function prototypes -----------------------------------------------*/
00041 /* Private functions ---------------------------------------------------------*/
00042
00043 /******************************************************************************/
00044 /*            Cortex-M3 Processor Exceptions Handlers                         */
00045 /******************************************************************************/
00046
00047 /**
00048   * @brief  This function handles NMI exception.
00049   * @param  None
00050   * @retval None
00051   */
00052 void NMI_Handler(void)
00053 {
00054 }
00055
00056 /**
00057   * @brief  This function handles Hard Fault exception.
00058   * @param  None
00059   * @retval None
00060   */
00061 void HardFault_Handler(void)
00062 {
00063   /* Go to infinite loop when Hard Fault exception occurs */
00064   while (1)
00065   {
00066   }
00067 }
00068
00069 /**
00070   * @brief  This function handles Memory Manage exception.
00071   * @param  None
00072   * @retval None
00073   */
00074 void MemManage_Handler(void)
00075 {
00076   /* Go to infinite loop when Memory Manage exception occurs */
00077   while (1)
00078   {
00079   }
00080 }
00081
00082 /**
00083   * @brief  This function handles Bus Fault exception.
00084   * @param  None
00085   * @retval None
00086   */
00087 void BusFault_Handler(void)
00088 {
00089   /* Go to infinite loop when Bus Fault exception occurs */
00090   while (1)
00091   {
00092   }
00093 }
00094
00095 /**
00096   * @brief  This function handles Usage Fault exception.
00097   * @param  None
00098   * @retval None
00099   */
00100 void UsageFault_Handler(void)
00101 {
00102   /* Go to infinite loop when Usage Fault exception occurs */
00103   while (1)
00104   {
00105   }
00106 }
00107
00108 /**
00109   * @brief  This function handles SVCall exception.
00110   * @param  None
00111   * @retval None
00112   */
00113 void SVC_Handler(void)
00114 {
00115 }
00116
00117 /**
00118   * @brief  This function handles Debug Monitor exception.
00119   * @param  None
00120   * @retval None
00121   */
00122 void DebugMon_Handler(void)
00123 {
00124 }
00125
00126 /**
00127   * @brief  This function handles PendSV_Handler exception.
00128   * @param  None
00129   * @retval None
00130   */
00131 void PendSV_Handler(void)
00132 {
00133 }
00134
00135 /**
00136   * @brief  This function handles SysTick Handler.
00137   * @param  None
00138   * @retval None
00139   */
00140 void SysTick_Handler(void)
00141 {
00142 }
00143
00144 /******************************************************************************/
00145 /*            STM32F10x Peripherals Interrupt Handlers                        */
00146 /******************************************************************************/
00147
00148 /**
00149   * @brief  This function handles External line 0 interrupt request.
00150   * @param  None
00151   * @retval None
00152   */
00153 void EXTI0_IRQHandler(void)
00154 {
00155   if(EXTI_GetITStatus(EXTI_Line0) != RESET)
00156   {
00157     /* Toggle LED1 */
00158      STM_EVAL_LEDToggle(LED1);
00159
00160     /* Clear the  EXTI line 0 pending bit */
00161     EXTI_ClearITPendingBit(EXTI_Line0);
00162   }
00163 }
00164
00165 /**
00166   * @brief  This function handles External lines 9 to 5 interrupt request.
00167   * @param  None
00168   * @retval None
00169   */
00170 void EXTI9_5_IRQHandler(void)
00171 {
00172 #if defined (STM32F10X_HD_VL) || defined (STM32F10X_HD) || defined (STM32F10X_XL)
00173   if(EXTI_GetITStatus(EXTI_Line8) != RESET)
00174   {
00175     /* Toggle LED2 */
00176      STM_EVAL_LEDToggle(LED2);
00177
00178     /* Clear the  EXTI line 8 pending bit */
00179     EXTI_ClearITPendingBit(EXTI_Line8);
00180   }
00181 #else
00182   if(EXTI_GetITStatus(EXTI_Line9) != RESET)
00183   {
00184     /* Toggle LED2 */
00185      STM_EVAL_LEDToggle(LED2);
00186
00187     /* Clear the  EXTI line 9 pending bit */
00188     EXTI_ClearITPendingBit(EXTI_Line9);
00189   }
00190 #endif
00191 }
00192
00193 /******************************************************************************/
00194 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00195 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00196 /*  available peripheral interrupt handler's name please refer to the startup */
00197 /*  file (startup_stm32f10x_xx.s).                                            */
00198 /******************************************************************************/
00199
00200 /**
00201   * @brief  This function handles PPP interrupt request.
00202   * @param  None
00203   * @retval None
00204   */
00205 /*void PPP_IRQHandler(void)
00206 {
00207 }*/
00208
00209 /**
00210   * @}
00211   */
00212
00213 /**
00214   * @}
00215   */
00216
00217 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/stm32f10x_it.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    EXTI/EXTI_Config/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043 void EXTI0_IRQHandler(void);
00044 void EXTI9_5_IRQHandler(void);
00045
00046 #endif /* __STM32F10x_IT_H */
00047
00048 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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  • Dual_Boot

STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/main.c

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00001 /**
00002   ******************************************************************************
00003   * @file    FLASH/Dual_Boot/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "main.h"
00024
00025
00026 /** @addtogroup STM32F10x_StdPeriph_Examples
00027   * @{
00028   */
00029
00030 /** @addtogroup Dual_Boot
00031   * @{
00032   */
00033
00034 /* Private typedef -----------------------------------------------------------*/
00035 typedef enum {FAILED = 0, PASSED = !FAILED} TestStatus;
00036
00037 /* Private define ------------------------------------------------------------*/
00038 /* Uncomment one of the lines below to select which bank to boot from  */
00039 #if !defined(BOOT_FROM_BANK1) && !defined(BOOT_FROM_BANK2)
00040 //#define BOOT_FROM_BANK1           /* The program will be loaded on Flash Bank1 */
00041 //#define BOOT_FROM_BANK2           /* The program will be loaded on Flash Bank2 */
00042 #endif
00043
00044 #if defined(BOOT_FROM_BANK1)
00045  #define MESSAGE4   " Running from Bank 1"
00046 #elif defined(BOOT_FROM_BANK2)
00047  #define MESSAGE4   " Running from Bank 2"
00048 #else
00049  #error "Select Boot from Bank1 or Bank2 using defines:BOOT_FROM_BANK1 or BOOT_FROM_BANK2!"
00050 #endif
00051
00052 #define MESSAGE1   "  STM32 XL Density  "
00053 #define MESSAGE2   " Device running on  "
00054 #define MESSAGE3   "   STM3210E-EVAL    "
00055
00056 #define MESSAGE5   " Joystick-DOWN: reset BFB2"
00057 #define MESSAGE6   "  bit to Boot from Bank2  "
00058 #define MESSAGE7   " Joystick-UP: set BFB2    "
00059 #define MESSAGE8   "  bit to Boot from Bank1  "
00060
00061 #define MESSAGE9   " Joystick-SEL: program to "
00062 #define MESSAGE10  " 0x0 the base @ of Bank1/2"
00063
00064 #define MESSAGE11   "  Operation Failed !"
00065 #define MESSAGE12   "Bank 1/2 base @ -> 0"
00066
00067 #define BANK1_START_ADDRESS       0x08000000
00068 #define BANK2_START_ADDRESS       0x08080000
00069
00070 /* Private macro -------------------------------------------------------------*/
00071 /* Private variables ---------------------------------------------------------*/
00072 USART_InitTypeDef USART_InitStructure;
00073
00074 static __IO uint32_t TimingDelay;
00075 RCC_ClocksTypeDef RCC_Clocks;
00076
00077 /* Private function prototypes -----------------------------------------------*/
00078 void Delay(__IO uint32_t nTime);
00079
00080 /* Private functions ---------------------------------------------------------*/
00081
00082 /**
00083   * @brief   Main program
00084   * @param  None
00085   * @retval None
00086   */
00087 int main(void)
00088 {
00089   /*!< At this stage the microcontroller clock setting is already configured,
00090        this is done through SystemInit() function which is called from startup
00091        file (startup_stm32f10x_xx.s) before to branch to application main.
00092        To reconfigure the default setting of SystemInit() function, refer to
00093        system_stm32f10x.c file
00094      */
00095
00096   /* Set the vector table address */
00097 #if defined(BOOT_FROM_BANK1)
00098   /* Set the vector table to the Bank1 start address */
00099   NVIC_SetVectorTable(NVIC_VectTab_FLASH, BANK1_START_ADDRESS);
00100 #elif defined(BOOT_FROM_BANK2)
00101   /* Set the vector table to the Bank1 start address */
00102   NVIC_SetVectorTable(NVIC_VectTab_FLASH, BANK2_START_ADDRESS);
00103 #endif /* BOOT_FROM_BANK1 */
00104
00105   /* Initialize LEDs, Buttons and LCD on STM3210E-EVAL board *****************/
00106   STM_EVAL_LEDInit(LED1);
00107   STM_EVAL_LEDInit(LED2);
00108   STM_EVAL_LEDInit(LED3);
00109   STM_EVAL_LEDInit(LED4);
00110
00111   /* SysTick end of count event each 10ms */
00112   RCC_GetClocksFreq(&RCC_Clocks);
00113   SysTick_Config(RCC_Clocks.HCLK_Frequency / 100);
00114
00115   /* Configure the Joystick buttons */
00116   STM_EVAL_PBInit(BUTTON_UP, BUTTON_MODE_GPIO);
00117   STM_EVAL_PBInit(BUTTON_SEL, BUTTON_MODE_GPIO);
00118   STM_EVAL_PBInit(BUTTON_DOWN, BUTTON_MODE_GPIO);
00119   /* Initialize the LCD */
00120   STM3210E_LCD_Init();
00121
00122   /* Display message on STM3210E-EVAL LCD *************************************/
00123   /* Clear the LCD */
00124   LCD_Clear(LCD_COLOR_WHITE);
00125
00126   /* Set the LCD Back Color */
00127 #if defined(BOOT_FROM_BANK1)
00128   LCD_SetBackColor(LCD_COLOR_BLUE);
00129 #elif defined(BOOT_FROM_BANK2)
00130   LCD_SetBackColor(LCD_COLOR_RED);
00131 #endif /* BOOT_FROM_BANK1 */
00132
00133   /* Set the LCD Text Color */
00134   LCD_SetTextColor(LCD_COLOR_WHITE);
00135   LCD_DisplayStringLine(LCD_LINE_0, MESSAGE1);
00136   LCD_DisplayStringLine(LCD_LINE_1, MESSAGE2);
00137   LCD_DisplayStringLine(LCD_LINE_2, MESSAGE3);
00138   LCD_DisplayStringLine(LCD_LINE_4, MESSAGE4);
00139
00140   LCD_SetFont(&Font12x12);
00141   LCD_DisplayStringLine(LCD_LINE_12, MESSAGE5);
00142   LCD_DisplayStringLine(LCD_LINE_13, MESSAGE6);
00143   LCD_DisplayStringLine(LCD_LINE_15, MESSAGE7);
00144   LCD_DisplayStringLine(LCD_LINE_16, MESSAGE8);
00145   LCD_DisplayStringLine(LCD_LINE_18, MESSAGE9);
00146   LCD_DisplayStringLine(LCD_LINE_19, MESSAGE10);
00147   LCD_SetFont(&Font16x24);
00148
00149   /* Turn on leds available on STM3210E-EVAL **********************************/
00150   STM_EVAL_LEDOn(LED1);
00151   STM_EVAL_LEDOn(LED2);
00152   STM_EVAL_LEDOn(LED3);
00153   STM_EVAL_LEDOn(LED4);
00154
00155   /* Infinite loop */
00156   while (1)
00157   {
00158     /*--- If Joystick DOWN button is pushed, reset BFB2 bit to enable boot from Bank2
00159           (active after next reset, w/ Boot pins set in Boot from Flash memory position ---*/
00160     if (STM_EVAL_PBGetState(BUTTON_DOWN) == 0)
00161     {
00162       /* Reset BFB2 bit to enable boot from Flash Bank2 */
00163       FLASH_Unlock();
00164       FLASH_EraseOptionBytes();
00165
00166       if (FLASH_BootConfig(FLASH_BOOT_Bank2) == FLASH_COMPLETE)
00167       {
00168         /* Generate System Reset to load the new option byte values */
00169         NVIC_SystemReset();
00170       }
00171       else
00172       {
00173         /* Display information */
00174         LCD_DisplayStringLine(LCD_LINE_6, MESSAGE11);
00175       }
00176     }
00177
00178     /*--- If Joystick UP button is pushed, set BFB2 bit to enable boot from Bank1
00179           (active after next reset, w/ Boot pins set in Boot from Flash memory position ---*/
00180     if (STM_EVAL_PBGetState(BUTTON_UP) == 0)
00181     {
00182       /* Set BFB2 bit to enable boot from Flash Bank2 */
00183       FLASH_Unlock();
00184       FLASH_EraseOptionBytes();
00185       if (FLASH_BootConfig(FLASH_BOOT_Bank1) == FLASH_COMPLETE)
00186       {
00187         /* Generate System Reset to load the new option byte values */
00188         NVIC_SystemReset();
00189       }
00190       else
00191       {
00192         /* Display information */
00193         LCD_DisplayStringLine(LCD_LINE_6, MESSAGE11);
00194       }
00195     }
00196
00197     /*--- If Joystick UP button is pushed, program the content of address 0x08080000
00198           (base address of Bank2) and 0x08000000(base address of Bank1) to 0x00 --*/
00199     if (STM_EVAL_PBGetState(BUTTON_SEL) == 0)
00200     {
00201       FLASH_Unlock();
00202       /* Erase stack pointer value at Bank 2 start address */
00203       FLASH_ProgramWord(BANK2_START_ADDRESS, 0x00);
00204       /* Erase stack pointer value at Bank 1 start address */
00205       FLASH_ProgramWord(BANK1_START_ADDRESS, 0x00);
00206       FLASH_Lock();
00207
00208       LCD_ClearLine(LCD_LINE_7);
00209       LCD_ClearLine(LCD_LINE_8);
00210       LCD_ClearLine(LCD_LINE_9);
00211
00212       /* Check if erase operation is OK */
00213       if ((uint32_t)(*(uint32_t *)BANK2_START_ADDRESS) ==  0x00)
00214       {
00215         if ((uint32_t)(*(uint32_t *)BANK1_START_ADDRESS) !=  0x00)
00216         {
00217           /* Display information */
00218           LCD_DisplayStringLine(LCD_LINE_6, MESSAGE11);
00219         }
00220         else
00221         {
00222           /* Display information */
00223           LCD_DisplayStringLine(LCD_LINE_6, MESSAGE12);
00224         }
00225       }
00226       else
00227       {
00228         /* Display information */
00229         LCD_DisplayStringLine(LCD_LINE_6, MESSAGE11);
00230       }
00231     }
00232
00233     /* Toggle LD3 */
00234     STM_EVAL_LEDToggle(LED3);
00235
00236     /* Insert 50 ms delay */
00237     Delay(5);
00238
00239     /* Toggle LD2 */
00240     STM_EVAL_LEDToggle(LED2);
00241
00242     /* Insert 100 ms delay */
00243     Delay(10);
00244   }
00245 }
00246
00247 /**
00248   * @brief  Inserts a delay time.
00249   * @param  nTime: specifies the delay time length, in 10 ms.
00250   * @retval None
00251   */
00252 void Delay(__IO uint32_t nTime)
00253 {
00254   TimingDelay = nTime;
00255
00256   while (TimingDelay != 0);
00257 }
00258
00259 /**
00260   * @brief  Decrements the TimingDelay variable.
00261   * @param  None
00262   * @retval None
00263   */
00264 void TimingDelay_Decrement(void)
00265 {
00266   if (TimingDelay != 0x00)
00267   {
00268     TimingDelay--;
00269   }
00270 }
00271
00272 #ifdef  USE_FULL_ASSERT
00273
00274 /**
00275   * @brief  Reports the name of the source file and the source line number
00276   *         where the assert_param error has occurred.
00277   * @param  file: pointer to the source file name
00278   * @param  line: assert_param error line source number
00279   * @retval None
00280   */
00281 void assert_failed(uint8_t* file, uint32_t line)
00282 {
00283   /* User can add his own implementation to report the file name and line number,
00284      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00285
00286   while (1)
00287   {}
00288 }
00289
00290 #endif
00291
00292 /**
00293   * @}
00294   */
00295
00296 /**
00297   * @}
00298   */
00299
00300 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/stm32f10x_conf.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    FLASH/Dual_Boot/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052 /* Exported types ------------------------------------------------------------*/
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Uncomment the line below to expanse the "assert_param" macro in the
00055    Standard Peripheral Library drivers code */
00056 /* #define USE_FULL_ASSERT    1 */
00057
00058 /* Exported macro ------------------------------------------------------------*/
00059 #ifdef  USE_FULL_ASSERT
00060
00061 /**
00062   * @brief  The assert_param macro is used for function's parameters check.
00063   * @param  expr: If expr is false, it calls assert_failed function which reports
00064   *         the name of the source file and the source line number of the call
00065   *         that failed. If expr is true, it returns no value.
00066   * @retval None
00067   */
00068   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00069 /* Exported functions ------------------------------------------------------- */
00070   void assert_failed(uint8_t* file, uint32_t line);
00071 #else
00072   #define assert_param(expr) ((void)0)
00073 #endif /* USE_FULL_ASSERT */
00074
00075 #endif /* __STM32F10x_CONF_H */
00076
00077 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/stm32f10x_it.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    FLASH/Dual_Boot/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and peripherals
00009   *          interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026 #include "main.h"
00027
00028 /** @addtogroup STM32F10x_StdPeriph_Examples
00029   * @{
00030   */
00031
00032 /** @addtogroup Dual_Boot
00033   * @{
00034   */
00035
00036 /* Private typedef -----------------------------------------------------------*/
00037 /* Private define ------------------------------------------------------------*/
00038 /* Private macro -------------------------------------------------------------*/
00039 /* Private variables ---------------------------------------------------------*/
00040 /* Private function prototypes -----------------------------------------------*/
00041 /* Private functions ---------------------------------------------------------*/
00042
00043 /******************************************************************************/
00044 /*            Cortex-M3 Processor Exceptions Handlers                         */
00045 /******************************************************************************/
00046
00047 /**
00048   * @brief  This function handles NMI exception.
00049   * @param  None
00050   * @retval None
00051   */
00052 void NMI_Handler(void)
00053 {
00054 }
00055
00056 /**
00057   * @brief  This function handles Hard Fault exception.
00058   * @param  None
00059   * @retval None
00060   */
00061 void HardFault_Handler(void)
00062 {
00063   /* Go to infinite loop when Hard Fault exception occurs */
00064   while (1)
00065   {
00066   }
00067 }
00068
00069 /**
00070   * @brief  This function handles Memory Manage exception.
00071   * @param  None
00072   * @retval None
00073   */
00074 void MemManage_Handler(void)
00075 {
00076   /* Go to infinite loop when Memory Manage exception occurs */
00077   while (1)
00078   {
00079   }
00080 }
00081
00082 /**
00083   * @brief  This function handles Bus Fault exception.
00084   * @param  None
00085   * @retval None
00086   */
00087 void BusFault_Handler(void)
00088 {
00089   /* Go to infinite loop when Bus Fault exception occurs */
00090   while (1)
00091   {
00092   }
00093 }
00094
00095 /**
00096   * @brief  This function handles Usage Fault exception.
00097   * @param  None
00098   * @retval None
00099   */
00100 void UsageFault_Handler(void)
00101 {
00102   /* Go to infinite loop when Usage Fault exception occurs */
00103   while (1)
00104   {
00105   }
00106 }
00107
00108 /**
00109   * @brief  This function handles SVCall exception.
00110   * @param  None
00111   * @retval None
00112   */
00113 void SVC_Handler(void)
00114 {
00115 }
00116
00117 /**
00118   * @brief  This function handles Debug Monitor exception.
00119   * @param  None
00120   * @retval None
00121   */
00122 void DebugMon_Handler(void)
00123 {
00124 }
00125
00126 /**
00127   * @brief  This function handles PendSV_Handler exception.
00128   * @param  None
00129   * @retval None
00130   */
00131 void PendSV_Handler(void)
00132 {
00133 }
00134
00135 /**
00136   * @brief  This function handles SysTick Handler.
00137   * @param  None
00138   * @retval None
00139   */
00140 void SysTick_Handler(void)
00141 {
00142   TimingDelay_Decrement();
00143 }
00144
00145 /******************************************************************************/
00146 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00147 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00148 /*  available peripheral interrupt handler's name please refer to the startup */
00149 /*  file (startup_stm32f10x_xx.s).                                            */
00150 /******************************************************************************/
00151
00152 /**
00153   * @brief  This function handles PPP interrupt request.
00154   * @param  None
00155   * @retval None
00156   */
00157 /*void PPP_IRQHandler(void)
00158 {
00159 }*/
00160
00161 /**
00162   * @}
00163   */
00164
00165 /**
00166   * @}
00167   */
00168
00169 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/stm32f10x_it.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    FLASH/Dual_Boot/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043
00044 #endif /* __STM32F10x_IT_H */
00045
00046 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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STM32F10x_StdPeriph_Examples/FLASH/Program/main.c

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00001 /**
00002   ******************************************************************************
00003   * @file    FLASH/Program/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x.h"
00024
00025
00026 /** @addtogroup STM32F10x_StdPeriph_Examples
00027   * @{
00028   */
00029
00030 /** @addtogroup FLASH_Program
00031   * @{
00032   */
00033
00034 /* Private typedef -----------------------------------------------------------*/
00035 typedef enum {FAILED = 0, PASSED = !FAILED} TestStatus;
00036
00037 /* Private define ------------------------------------------------------------*/
00038 /* Define the STM32F10x FLASH Page Size depending on the used STM32 device */
00039 #if defined (STM32F10X_HD) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL) || defined (STM32F10X_XL)
00040   #define FLASH_PAGE_SIZE    ((uint16_t)0x800)
00041 #else
00042   #define FLASH_PAGE_SIZE    ((uint16_t)0x400)
00043 #endif
00044
00045 #define BANK1_WRITE_START_ADDR  ((uint32_t)0x08008000)
00046 #define BANK1_WRITE_END_ADDR    ((uint32_t)0x0800C000)
00047
00048 #ifdef STM32F10X_XL
00049  #define BANK2_WRITE_START_ADDR   ((uint32_t)0x08088000)
00050  #define BANK2_WRITE_END_ADDR     ((uint32_t)0x0808C000)
00051 #endif /* STM32F10X_XL */
00052
00053 /* Private macro -------------------------------------------------------------*/
00054 /* Private variables ---------------------------------------------------------*/
00055 uint32_t EraseCounter = 0x00, Address = 0x00;
00056 uint32_t Data = 0x3210ABCD;
00057 uint32_t NbrOfPage = 0x00;
00058 volatile FLASH_Status FLASHStatus = FLASH_COMPLETE;
00059 volatile TestStatus MemoryProgramStatus = PASSED;
00060
00061 #ifdef STM32F10X_XL
00062 volatile TestStatus MemoryProgramStatus2 = PASSED;
00063 #endif /* STM32F10X_XL */
00064
00065 /* Private function prototypes -----------------------------------------------*/
00066 /* Private functions ---------------------------------------------------------*/
00067
00068 /**
00069   * @brief   Main program
00070   * @param  None
00071   * @retval None
00072   */
00073 int main(void)
00074 {
00075   /*!< At this stage the microcontroller clock setting is already configured,
00076        this is done through SystemInit() function which is called from startup
00077        file (startup_stm32f10x_xx.s) before to branch to application main.
00078        To reconfigure the default setting of SystemInit() function, refer to
00079        system_stm32f10x.c file
00080      */
00081
00082 /* Porgram FLASH Bank1 ********************************************************/
00083   /* Unlock the Flash Bank1 Program Erase controller */
00084   FLASH_UnlockBank1();
00085
00086   /* Define the number of page to be erased */
00087   NbrOfPage = (BANK1_WRITE_END_ADDR - BANK1_WRITE_START_ADDR) / FLASH_PAGE_SIZE;
00088
00089   /* Clear All pending flags */
00090   FLASH_ClearFlag(FLASH_FLAG_EOP | FLASH_FLAG_PGERR | FLASH_FLAG_WRPRTERR);
00091
00092   /* Erase the FLASH pages */
00093   for(EraseCounter = 0; (EraseCounter < NbrOfPage) && (FLASHStatus == FLASH_COMPLETE); EraseCounter++)
00094   {
00095     FLASHStatus = FLASH_ErasePage(BANK1_WRITE_START_ADDR + (FLASH_PAGE_SIZE * EraseCounter));
00096   }
00097
00098   /* Program Flash Bank1 */
00099   Address = BANK1_WRITE_START_ADDR;
00100
00101   while((Address < BANK1_WRITE_END_ADDR) && (FLASHStatus == FLASH_COMPLETE))
00102   {
00103     FLASHStatus = FLASH_ProgramWord(Address, Data);
00104     Address = Address + 4;
00105   }
00106
00107   FLASH_LockBank1();
00108
00109   /* Check the correctness of written data */
00110   Address = BANK1_WRITE_START_ADDR;
00111
00112   while((Address < BANK1_WRITE_END_ADDR) && (MemoryProgramStatus != FAILED))
00113   {
00114     if((*(__IO uint32_t*) Address) != Data)
00115     {
00116       MemoryProgramStatus = FAILED;
00117     }
00118     Address += 4;
00119   }
00120
00121 #ifdef STM32F10X_XL
00122 /* Program FLASH Bank2 ********************************************************/
00123   /* Unlock the Flash Bank2 Program Erase controller */
00124   FLASH_UnlockBank2();
00125
00126   /* Define the number of page to be erased */
00127   NbrOfPage = (BANK2_WRITE_END_ADDR - BANK2_WRITE_START_ADDR) / FLASH_PAGE_SIZE;
00128
00129   /* Clear All pending flags */
00130   FLASH_ClearFlag(FLASH_FLAG_EOP | FLASH_FLAG_PGERR | FLASH_FLAG_WRPRTERR);
00131
00132   /* Erase the FLASH pages */
00133   for(EraseCounter = 0; (EraseCounter < NbrOfPage) && (FLASHStatus == FLASH_COMPLETE); EraseCounter++)
00134   {
00135     FLASHStatus = FLASH_ErasePage(BANK2_WRITE_START_ADDR + (FLASH_PAGE_SIZE * EraseCounter));
00136   }
00137
00138   /* Program Flash Bank2 */
00139   Address = BANK2_WRITE_START_ADDR;
00140
00141   while((Address < BANK2_WRITE_END_ADDR) && (FLASHStatus == FLASH_COMPLETE))
00142   {
00143     FLASHStatus = FLASH_ProgramWord(Address, Data);
00144     Address = Address + 4;
00145   }
00146
00147   FLASH_LockBank2();
00148
00149   /* Check the correctness of written data */
00150   Address = BANK2_WRITE_START_ADDR;
00151
00152   while((Address < BANK2_WRITE_END_ADDR) && (MemoryProgramStatus2 != FAILED))
00153   {
00154     if((*(__IO uint32_t*) Address) != Data)
00155     {
00156       MemoryProgramStatus2 = FAILED;
00157     }
00158     Address += 4;
00159   }
00160
00161 #endif /* STM32F10X_XL */
00162
00163   while (1)
00164   {
00165   }
00166 }
00167
00168 #ifdef  USE_FULL_ASSERT
00169
00170 /**
00171   * @brief  Reports the name of the source file and the source line number
00172   *         where the assert_param error has occurred.
00173   * @param  file: pointer to the source file name
00174   * @param  line: assert_param error line source number
00175   * @retval None
00176   */
00177 void assert_failed(uint8_t* file, uint32_t line)
00178 {
00179   /* User can add his own implementation to report the file name and line number,
00180      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00181
00182   while (1)
00183   {
00184   }
00185 }
00186
00187 #endif
00188
00189 /**
00190   * @}
00191   */
00192
00193 /**
00194   * @}
00195   */
00196
00197 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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STM32F10x_StdPeriph_Examples/FLASH/Program/stm32f10x_conf.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    FLASH/Program/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052 /* Exported types ------------------------------------------------------------*/
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Uncomment the line below to expanse the "assert_param" macro in the
00055    Standard Peripheral Library drivers code */
00056 /* #define USE_FULL_ASSERT    1 */
00057
00058 /* Exported macro ------------------------------------------------------------*/
00059 #ifdef  USE_FULL_ASSERT
00060
00061 /**
00062   * @brief  The assert_param macro is used for function's parameters check.
00063   * @param  expr: If expr is false, it calls assert_failed function which reports
00064   *         the name of the source file and the source line number of the call
00065   *         that failed. If expr is true, it returns no value.
00066   * @retval None
00067   */
00068   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00069 /* Exported functions ------------------------------------------------------- */
00070   void assert_failed(uint8_t* file, uint32_t line);
00071 #else
00072   #define assert_param(expr) ((void)0)
00073 #endif /* USE_FULL_ASSERT */
00074
00075 #endif /* __STM32F10x_CONF_H */
00076
00077 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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STM32F10x_StdPeriph_Examples/FLASH/Program/stm32f10x_it.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    FLASH/Program/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and peripherals
00009   *          interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026
00027 /** @addtogroup STM32F10x_StdPeriph_Examples
00028   * @{
00029   */
00030
00031 /** @addtogroup FLASH_Program
00032   * @{
00033   */
00034
00035 /* Private typedef -----------------------------------------------------------*/
00036 /* Private define ------------------------------------------------------------*/
00037 /* Private macro -------------------------------------------------------------*/
00038 /* Private variables ---------------------------------------------------------*/
00039 /* Private function prototypes -----------------------------------------------*/
00040 /* Private functions ---------------------------------------------------------*/
00041
00042 /******************************************************************************/
00043 /*            Cortex-M3 Processor Exceptions Handlers                         */
00044 /******************************************************************************/
00045
00046 /**
00047   * @brief  This function handles NMI exception.
00048   * @param  None
00049   * @retval None
00050   */
00051 void NMI_Handler(void)
00052 {
00053 }
00054
00055 /**
00056   * @brief  This function handles Hard Fault exception.
00057   * @param  None
00058   * @retval None
00059   */
00060 void HardFault_Handler(void)
00061 {
00062   /* Go to infinite loop when Hard Fault exception occurs */
00063   while (1)
00064   {
00065   }
00066 }
00067
00068 /**
00069   * @brief  This function handles Memory Manage exception.
00070   * @param  None
00071   * @retval None
00072   */
00073 void MemManage_Handler(void)
00074 {
00075   /* Go to infinite loop when Memory Manage exception occurs */
00076   while (1)
00077   {
00078   }
00079 }
00080
00081 /**
00082   * @brief  This function handles Bus Fault exception.
00083   * @param  None
00084   * @retval None
00085   */
00086 void BusFault_Handler(void)
00087 {
00088   /* Go to infinite loop when Bus Fault exception occurs */
00089   while (1)
00090   {
00091   }
00092 }
00093
00094 /**
00095   * @brief  This function handles Usage Fault exception.
00096   * @param  None
00097   * @retval None
00098   */
00099 void UsageFault_Handler(void)
00100 {
00101   /* Go to infinite loop when Usage Fault exception occurs */
00102   while (1)
00103   {
00104   }
00105 }
00106
00107 /**
00108   * @brief  This function handles SVCall exception.
00109   * @param  None
00110   * @retval None
00111   */
00112 void SVC_Handler(void)
00113 {
00114 }
00115
00116 /**
00117   * @brief  This function handles Debug Monitor exception.
00118   * @param  None
00119   * @retval None
00120   */
00121 void DebugMon_Handler(void)
00122 {
00123 }
00124
00125 /**
00126   * @brief  This function handles PendSV_Handler exception.
00127   * @param  None
00128   * @retval None
00129   */
00130 void PendSV_Handler(void)
00131 {
00132 }
00133
00134 /**
00135   * @brief  This function handles SysTick Handler.
00136   * @param  None
00137   * @retval None
00138   */
00139 void SysTick_Handler(void)
00140 {
00141 }
00142
00143 /******************************************************************************/
00144 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00145 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00146 /*  available peripheral interrupt handler's name please refer to the startup */
00147 /*  file (startup_stm32f10x_xx.s).                                            */
00148 /******************************************************************************/
00149
00150 /**
00151   * @brief  This function handles PPP interrupt request.
00152   * @param  None
00153   * @retval None
00154   */
00155 /*void PPP_IRQHandler(void)
00156 {
00157 }*/
00158
00159 /**
00160   * @}
00161   */
00162
00163 /**
00164   * @}
00165   */
00166
00167 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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STM32F10x_StdPeriph_Examples/FLASH/Program/stm32f10x_it.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    FLASH/Program/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043
00044 #endif /* __STM32F10x_IT_H */
00045
00046 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/main.c

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00001 /**
00002   ******************************************************************************
00003   * @file    FLASH/Write_Protection/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x.h"
00024
00025 /** @addtogroup STM32F10x_StdPeriph_Examples
00026   * @{
00027   */
00028
00029 /** @addtogroup FLASH_Write_Protection
00030   * @{
00031   */
00032
00033 /* Private typedef -----------------------------------------------------------*/
00034 typedef enum {FAILED = 0, PASSED = !FAILED} TestStatus;
00035
00036 /* Private define ------------------------------------------------------------*/
00037 /* Define the STM32F10x FLASH Page Size depending on the used device */
00038 #if defined (STM32F10X_HD) || defined (STM32F10X_HD_VL) || (STM32F10X_CL) || defined (STM32F10X_XL)
00039   #define FLASH_PAGE_SIZE    ((uint16_t)0x800)
00040   #define FLASH_PAGES_TO_BE_PROTECTED (FLASH_WRProt_Pages12to13 | FLASH_WRProt_Pages14to15)
00041 #else
00042   #define FLASH_PAGE_SIZE    ((uint16_t)0x400)
00043   #define FLASH_PAGES_TO_BE_PROTECTED (FLASH_WRProt_Pages24to27 | FLASH_WRProt_Pages28to31)
00044 #endif
00045
00046 #define BANK1_WRITE_START_ADDR  ((uint32_t)0x08006000)
00047 #define BANK1_WRITE_END_ADDR    ((uint32_t)0x08008000)
00048
00049 /* Uncomment this line to program the Falsh pages */
00050 //#define FLASH_PAGE_PROGRAM
00051 /* Uncomment this line to Enable Write Protection */
00052 //#define WRITE_PROTECTION_ENABLE
00053 /* Uncomment this line to Disable Write Protection */
00054 #define WRITE_PROTECTION_DISABLE
00055
00056 /* Private macro -------------------------------------------------------------*/
00057 /* Private variables ---------------------------------------------------------*/
00058 uint32_t EraseCounter = 0x0, Address = 0x0;
00059 uint16_t Data = 0x1753;
00060 uint32_t WRPR_Value = 0xFFFFFFFF, ProtectedPages = 0x0;
00061 uint32_t NbrOfPage;
00062 volatile FLASH_Status FLASHStatus = FLASH_COMPLETE;
00063 volatile TestStatus MemoryProgramStatus = PASSED;
00064
00065 /* Private function prototypes -----------------------------------------------*/
00066 /* Private functions ---------------------------------------------------------*/
00067
00068 /**
00069   * @brief   Main program
00070   * @param  None
00071   * @retval None
00072   */
00073 int main(void)
00074 {
00075   /*!< At this stage the microcontroller clock setting is already configured,
00076        this is done through SystemInit() function which is called from startup
00077        file (startup_stm32f10x_xx.s) before to branch to application main.
00078        To reconfigure the default setting of SystemInit() function, refer to
00079        system_stm32f10x.c file
00080      */
00081
00082   /* Unlock the Flash Program Erase controller */
00083   FLASH_Unlock();
00084
00085   /* Get pages write protection status */
00086   WRPR_Value = FLASH_GetWriteProtectionOptionByte();
00087
00088 #ifdef WRITE_PROTECTION_DISABLE
00089
00090   /* Get pages already write protected */
00091   ProtectedPages = ~(WRPR_Value | FLASH_PAGES_TO_BE_PROTECTED);
00092
00093   /* Check if desired pages are already write protected */
00094   if((WRPR_Value | (~FLASH_PAGES_TO_BE_PROTECTED)) != 0xFFFFFFFF )
00095   {
00096     /* Erase all the option Bytes */
00097     FLASHStatus = FLASH_EraseOptionBytes();
00098
00099   /* Check if there is write protected pages */
00100   if(ProtectedPages != 0x0)
00101   {
00102       /* Restore write protected pages */
00103       FLASHStatus = FLASH_EnableWriteProtection(ProtectedPages);
00104     }
00105     /* Generate System Reset to load the new option byte values */
00106     NVIC_SystemReset();
00107   }
00108
00109 #elif defined WRITE_PROTECTION_ENABLE
00110
00111   /* Get current write protected pages and the new pages to be protected */
00112   ProtectedPages =  (~WRPR_Value) | FLASH_PAGES_TO_BE_PROTECTED;
00113
00114   /* Check if desired pages are not yet write protected */
00115   if(((~WRPR_Value) & FLASH_PAGES_TO_BE_PROTECTED )!= FLASH_PAGES_TO_BE_PROTECTED)
00116   {
00117
00118     /* Erase all the option Bytes because if a program operation is
00119       performed on a protected page, the Flash memory returns a
00120       protection error */
00121     FLASHStatus = FLASH_EraseOptionBytes();
00122
00123     /* Enable the pages write protection */
00124     FLASHStatus = FLASH_EnableWriteProtection(ProtectedPages);
00125
00126     /* Generate System Reset to load the new option byte values */
00127     NVIC_SystemReset();
00128   }
00129
00130 #endif
00131
00132 #ifdef FLASH_PAGE_PROGRAM
00133   /* Get the number of pages to be erased */
00134   NbrOfPage = (BANK1_WRITE_END_ADDR - BANK1_WRITE_START_ADDR) / FLASH_PAGE_SIZE;
00135
00136   /* The selected pages are not write protected */
00137   if ( (WRPR_Value & FLASH_PAGES_TO_BE_PROTECTED) != 0x00)
00138   {
00139     /* Clear All pending flags */
00140     FLASH_ClearFlag(FLASH_FLAG_BSY | FLASH_FLAG_EOP|FLASH_FLAG_PGERR |FLASH_FLAG_WRPRTERR);
00141
00142     /* erase the FLASH pages */
00143     for(EraseCounter = 0; (EraseCounter < NbrOfPage) && (FLASHStatus == FLASH_COMPLETE); EraseCounter++)
00144     {
00145       FLASHStatus = FLASH_ErasePage(BANK1_WRITE_START_ADDR + (FLASH_PAGE_SIZE * EraseCounter));
00146     }
00147
00148     /* FLASH Half Word program of data 0x1753 at addresses defined by  BANK1_WRITE_START_ADDR and BANK1_WRITE_END_ADDR */
00149     Address = BANK1_WRITE_START_ADDR;
00150
00151     while((Address < BANK1_WRITE_END_ADDR) && (FLASHStatus == FLASH_COMPLETE))
00152     {
00153       FLASHStatus = FLASH_ProgramHalfWord(Address, Data);
00154       Address = Address + 2;
00155     }
00156
00157     /* Check the correctness of written data */
00158     Address = BANK1_WRITE_START_ADDR;
00159
00160     while((Address < BANK1_WRITE_END_ADDR) && (MemoryProgramStatus != FAILED))
00161     {
00162       if((*(__IO uint16_t*) Address) != Data)
00163       {
00164         MemoryProgramStatus = FAILED;
00165       }
00166       Address += 2;
00167     }
00168   }
00169   else
00170   {
00171     /* Error to program the flash : The desired pages are write protected */
00172     MemoryProgramStatus = FAILED;
00173   }
00174
00175 #endif
00176
00177   while (1)
00178   {
00179   }
00180 }
00181
00182 #ifdef  USE_FULL_ASSERT
00183
00184 /**
00185   * @brief  Reports the name of the source file and the source line number
00186   *         where the assert_param error has occurred.
00187   * @param  file: pointer to the source file name
00188   * @param  line: assert_param error line source number
00189   * @retval None
00190   */
00191 void assert_failed(uint8_t* file, uint32_t line)
00192 {
00193   /* User can add his own implementation to report the file name and line number,
00194      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00195
00196   while (1)
00197   {
00198   }
00199 }
00200
00201 #endif
00202
00203 /**
00204   * @}
00205   */
00206
00207 /**
00208   * @}
00209   */
00210
00211 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/stm32f10x_conf.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    FLASH/Write_Protection/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052
00053 /* Exported types ------------------------------------------------------------*/
00054 /* Exported constants --------------------------------------------------------*/
00055 /* Uncomment the line below to expanse the "assert_param" macro in the
00056    Standard Peripheral Library drivers code */
00057 /* #define USE_FULL_ASSERT    1 */
00058
00059 /* Exported macro ------------------------------------------------------------*/
00060 #ifdef  USE_FULL_ASSERT
00061
00062 /**
00063   * @brief  The assert_param macro is used for function's parameters check.
00064   * @param  expr: If expr is false, it calls assert_failed function which reports
00065   *         the name of the source file and the source line number of the call
00066   *         that failed. If expr is true, it returns no value.
00067   * @retval None
00068   */
00069   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00070 /* Exported functions ------------------------------------------------------- */
00071   void assert_failed(uint8_t* file, uint32_t line);
00072 #else
00073   #define assert_param(expr) ((void)0)
00074 #endif /* USE_FULL_ASSERT */
00075
00076 #endif /* __STM32F10x_CONF_H */
00077
00078 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/stm32f10x_it.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    FLASH/Write_Protection/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and
00009   *          peripherals interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026
00027 /** @addtogroup STM32F10x_StdPeriph_Examples
00028   * @{
00029   */
00030
00031 /** @addtogroup FLASH_Write_Protection
00032   * @{
00033   */
00034
00035 /* Private typedef -----------------------------------------------------------*/
00036 /* Private define ------------------------------------------------------------*/
00037 /* Private macro -------------------------------------------------------------*/
00038 /* Private variables ---------------------------------------------------------*/
00039 /* Private function prototypes -----------------------------------------------*/
00040 /* Private functions ---------------------------------------------------------*/
00041
00042 /******************************************************************************/
00043 /*            Cortex-M3 Processor Exceptions Handlers                         */
00044 /******************************************************************************/
00045
00046 /**
00047   * @brief  This function handles NMI exception.
00048   * @param  None
00049   * @retval None
00050   */
00051 void NMI_Handler(void)
00052 {
00053 }
00054
00055 /**
00056   * @brief  This function handles Hard Fault exception.
00057   * @param  None
00058   * @retval None
00059   */
00060 void HardFault_Handler(void)
00061 {
00062   /* Go to infinite loop when Hard Fault exception occurs */
00063   while (1)
00064   {
00065   }
00066 }
00067
00068 /**
00069   * @brief  This function handles Memory Manage exception.
00070   * @param  None
00071   * @retval None
00072   */
00073 void MemManage_Handler(void)
00074 {
00075   /* Go to infinite loop when Memory Manage exception occurs */
00076   while (1)
00077   {
00078   }
00079 }
00080
00081 /**
00082   * @brief  This function handles Bus Fault exception.
00083   * @param  None
00084   * @retval None
00085   */
00086 void BusFault_Handler(void)
00087 {
00088   /* Go to infinite loop when Bus Fault exception occurs */
00089   while (1)
00090   {
00091   }
00092 }
00093
00094 /**
00095   * @brief  This function handles Usage Fault exception.
00096   * @param  None
00097   * @retval None
00098   */
00099 void UsageFault_Handler(void)
00100 {
00101   /* Go to infinite loop when Usage Fault exception occurs */
00102   while (1)
00103   {
00104   }
00105 }
00106
00107 /**
00108   * @brief  This function handles SVCall exception.
00109   * @param  None
00110   * @retval None
00111   */
00112 void SVC_Handler(void)
00113 {
00114 }
00115
00116 /**
00117   * @brief  This function handles Debug Monitor exception.
00118   * @param  None
00119   * @retval None
00120   */
00121 void DebugMon_Handler(void)
00122 {
00123 }
00124
00125 /**
00126   * @brief  This function handles PendSV_Handler exception.
00127   * @param  None
00128   * @retval None
00129   */
00130 void PendSV_Handler(void)
00131 {
00132 }
00133
00134 /**
00135   * @brief  This function handles SysTick Handler.
00136   * @param  None
00137   * @retval None
00138   */
00139 void SysTick_Handler(void)
00140 {
00141 }
00142
00143 /******************************************************************************/
00144 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00145 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00146 /*  available peripheral interrupt handler's name please refer to the startup */
00147 /*  file (startup_stm32f10x_xx.s).                                            */
00148 /******************************************************************************/
00149
00150 /**
00151   * @brief  This function handles PPP interrupt request.
00152   * @param  None
00153   * @retval None
00154   */
00155 /*void PPP_IRQHandler(void)
00156 {
00157 }*/
00158
00159 /**
00160   * @}
00161   */
00162
00163 /**
00164   * @}
00165   */
00166
00167 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/stm32f10x_it.h

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00001 /**
00002   ******************************************************************************
00003   * @file    FLASH/Write_Protection/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043
00044 #endif /* __STM32F10x_IT_H */
00045
00046 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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STM32F10x_StdPeriph_Examples/FSMC/NAND/main.c

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00001 /**
00002   ******************************************************************************
00003   * @file    FSMC/NAND/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm3210e_eval_fsmc_nand.h"
00024 #include "stm32_eval.h"
00025
00026 /** @addtogroup STM32F10x_StdPeriph_Examples
00027   * @{
00028   */
00029
00030 /** @addtogroup FSMC_NAND
00031   * @{
00032   */
00033
00034 /* Private typedef -----------------------------------------------------------*/
00035 /* Private define ------------------------------------------------------------*/
00036 #define BUFFER_SIZE         0x400
00037 #define NAND_ST_MakerID     0x20
00038 #define NAND_ST_DeviceID    0x76
00039
00040 /* Private macro -------------------------------------------------------------*/
00041 /* Private variables ---------------------------------------------------------*/
00042 NAND_IDTypeDef NAND_ID;
00043 NAND_ADDRESS WriteReadAddr;
00044 uint8_t TxBuffer[BUFFER_SIZE], RxBuffer[BUFFER_SIZE];
00045 uint32_t PageNumber = 2, WriteReadStatus = 0, status= 0;
00046 uint32_t j = 0;
00047
00048 /* Private function prototypes -----------------------------------------------*/
00049 void Fill_Buffer(uint8_t *pBuffer, uint16_t BufferLenght, uint32_t Offset);
00050
00051 /* Private functions ---------------------------------------------------------*/
00052
00053 /**
00054   * @brief   Main program.
00055   * @param  None
00056   * @retval None
00057   */
00058 int main(void)
00059 {
00060   /*!< At this stage the microcontroller clock setting is already configured,
00061        this is done through SystemInit() function which is called from startup
00062        file (startup_stm32f10x_xx.s) before to branch to application main.
00063        To reconfigure the default setting of SystemInit() function, refer to
00064        system_stm32f10x.c file
00065      */
00066
00067   /* Initialize Leds mounted on STM3210X-EVAL board */
00068   STM_EVAL_LEDInit(LED1);
00069   STM_EVAL_LEDInit(LED2);
00070   STM_EVAL_LEDInit(LED3);
00071
00072   /* Enable the FSMC Clock */
00073   RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, ENABLE);
00074
00075   /* FSMC Initialization */
00076   NAND_Init();
00077
00078   /* NAND read ID command */
00079   NAND_ReadID(&NAND_ID);
00080
00081   /* Verify the NAND ID */
00082   if((NAND_ID.Maker_ID == NAND_ST_MakerID) && (NAND_ID.Device_ID == NAND_ST_DeviceID))
00083   {
00084
00085     /* NAND memory address to write to */
00086     WriteReadAddr.Zone = 0x00;
00087     WriteReadAddr.Block = 0x00;
00088     WriteReadAddr.Page = 0x00;
00089
00090     /* Erase the NAND first Block */
00091     status = NAND_EraseBlock(WriteReadAddr);
00092
00093     /* Write data to FSMC NAND memory */
00094     /* Fill the buffer to send */
00095     Fill_Buffer(TxBuffer, BUFFER_SIZE , 0x66);
00096
00097     status = NAND_WriteSmallPage(TxBuffer, WriteReadAddr, PageNumber);
00098
00099     /* Read back the written data */
00100     status = NAND_ReadSmallPage (RxBuffer, WriteReadAddr, PageNumber);
00101
00102     /* Verify the written data */
00103     for(j = 0; j < BUFFER_SIZE; j++)
00104     {
00105       if(TxBuffer[j] != RxBuffer[j])
00106       {
00107         WriteReadStatus++;
00108       }
00109     }
00110
00111     if (WriteReadStatus == 0)
00112     {
00113       /* OK */
00114       /* Turn on LED1 */
00115       STM_EVAL_LEDOn(LED1);
00116     }
00117     else
00118     {
00119       /* KO */
00120       /* Turn on LED2 */
00121       STM_EVAL_LEDOn(LED2);
00122     }
00123   }
00124   else
00125   {
00126     /* Turn on LED3 */
00127     STM_EVAL_LEDOn(LED3);
00128   }
00129
00130   while(1)
00131   {
00132   }
00133 }
00134
00135 /**
00136   * @brief  Fill the buffer
00137   * @param  pBuffer: pointer on the Buffer to fill
00138   * @param  BufferSize: size of the buffer to fill
00139   * @param  Offset: first value to fill on the Buffer
00140   */
00141 void Fill_Buffer(uint8_t *pBuffer, uint16_t BufferLenght, uint32_t Offset)
00142 {
00143   uint16_t IndexTmp = 0;
00144
00145   /* Put in global buffer same values */
00146   for (IndexTmp = 0; IndexTmp < BufferLenght; IndexTmp++ )
00147   {
00148     pBuffer[IndexTmp] = IndexTmp + Offset;
00149   }
00150 }
00151
00152 #ifdef  USE_FULL_ASSERT
00153
00154 /**
00155   * @brief  Reports the name of the source file and the source line number
00156   *         where the assert_param error has occurred.
00157   * @param  file: pointer to the source file name
00158   * @param  line: assert_param error line source number
00159   * @retval None
00160   */
00161 void assert_failed(uint8_t* file, uint32_t line)
00162 {
00163   /* User can add his own implementation to report the file name and line number,
00164      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00165
00166   /* Infinite loop */
00167   while (1)
00168   {
00169   }
00170 }
00171
00172 #endif
00173 /**
00174   * @}
00175   */
00176
00177 /**
00178   * @}
00179   */
00180
00181 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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STM32F10x_StdPeriph_Examples/FSMC/NAND/stm32f10x_conf.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    FSMC/NAND/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052 /* Exported types ------------------------------------------------------------*/
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Uncomment the line below to expanse the "assert_param" macro in the
00055    Standard Peripheral Library drivers code */
00056 /* #define USE_FULL_ASSERT    1 */
00057
00058 /* Exported macro ------------------------------------------------------------*/
00059 #ifdef  USE_FULL_ASSERT
00060
00061 /**
00062   * @brief  The assert_param macro is used for function's parameters check.
00063   * @param  expr: If expr is false, it calls assert_failed function which reports
00064   *         the name of the source file and the source line number of the call
00065   *         that failed. If expr is true, it returns no value.
00066   * @retval None
00067   */
00068   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00069 /* Exported functions ------------------------------------------------------- */
00070   void assert_failed(uint8_t* file, uint32_t line);
00071 #else
00072   #define assert_param(expr) ((void)0)
00073 #endif /* USE_FULL_ASSERT */
00074
00075 #endif /* __STM32F10x_CONF_H */
00076
00077 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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STM32F10x_StdPeriph_Examples/FSMC/NAND/stm32f10x_it.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    FSMC/NAND/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and peripherals
00009   *          interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026
00027 /** @addtogroup STM32F10x_StdPeriph_Examples
00028   * @{
00029   */
00030
00031 /** @addtogroup FSMC_NAND
00032   * @{
00033   */
00034
00035 /* Private typedef -----------------------------------------------------------*/
00036 /* Private define ------------------------------------------------------------*/
00037 /* Private macro -------------------------------------------------------------*/
00038 /* Private variables ---------------------------------------------------------*/
00039 /* Private function prototypes -----------------------------------------------*/
00040 /* Private functions ---------------------------------------------------------*/
00041
00042 /******************************************************************************/
00043 /*            Cortex-M3 Processor Exceptions Handlers                         */
00044 /******************************************************************************/
00045
00046 /**
00047   * @brief  This function handles NMI exception.
00048   * @param  None
00049   * @retval None
00050   */
00051 void NMI_Handler(void)
00052 {
00053 }
00054
00055 /**
00056   * @brief  This function handles Hard Fault exception.
00057   * @param  None
00058   * @retval None
00059   */
00060 void HardFault_Handler(void)
00061 {
00062   /* Go to infinite loop when Hard Fault exception occurs */
00063   while (1)
00064   {
00065   }
00066 }
00067
00068 /**
00069   * @brief  This function handles Memory Manage exception.
00070   * @param  None
00071   * @retval None
00072   */
00073 void MemManage_Handler(void)
00074 {
00075   /* Go to infinite loop when Memory Manage exception occurs */
00076   while (1)
00077   {
00078   }
00079 }
00080
00081 /**
00082   * @brief  This function handles Bus Fault exception.
00083   * @param  None
00084   * @retval None
00085   */
00086 void BusFault_Handler(void)
00087 {
00088   /* Go to infinite loop when Bus Fault exception occurs */
00089   while (1)
00090   {
00091   }
00092 }
00093
00094 /**
00095   * @brief  This function handles Usage Fault exception.
00096   * @param  None
00097   * @retval None
00098   */
00099 void UsageFault_Handler(void)
00100 {
00101   /* Go to infinite loop when Usage Fault exception occurs */
00102   while (1)
00103   {
00104   }
00105 }
00106
00107 /**
00108   * @brief  This function handles SVCall exception.
00109   * @param  None
00110   * @retval None
00111   */
00112 void SVC_Handler(void)
00113 {
00114 }
00115
00116 /**
00117   * @brief  This function handles Debug Monitor exception.
00118   * @param  None
00119   * @retval None
00120   */
00121 void DebugMon_Handler(void)
00122 {
00123 }
00124
00125 /**
00126   * @brief  This function handles PendSV_Handler exception.
00127   * @param  None
00128   * @retval None
00129   */
00130 void PendSV_Handler(void)
00131 {
00132 }
00133
00134 /**
00135   * @brief  This function handles SysTick Handler.
00136   * @param  None
00137   * @retval None
00138   */
00139 void SysTick_Handler(void)
00140 {
00141 }
00142
00143 /******************************************************************************/
00144 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00145 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00146 /*  available peripheral interrupt handler's name please refer to the startup */
00147 /*  file (startup_stm32f10x_xx.s).                                            */
00148 /******************************************************************************/
00149
00150 /**
00151   * @brief  This function handles PPP interrupt request.
00152   * @param  None
00153   * @retval None
00154   */
00155 /*void PPP_IRQHandler(void)
00156 {
00157 }*/
00158
00159 /**
00160   * @}
00161   */
00162
00163 /**
00164   * @}
00165   */
00166
00167 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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STM32F10x_StdPeriph_Examples/FSMC/NAND/stm32f10x_it.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    FSMC/NAND/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043
00044 #endif /* __STM32F10x_IT_H */
00045
00046 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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STM32F10x_StdPeriph_Examples/FSMC/NOR/main.c

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00001 /**
00002   ******************************************************************************
00003   * @file    FSMC/NOR/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm3210e_eval_fsmc_nor.h"
00024 #include "stm32_eval.h"
00025
00026 /** @addtogroup STM32F10x_StdPeriph_Examples
00027   * @{
00028   */
00029
00030 /** @addtogroup FSMC_NOR
00031   * @{
00032   */
00033
00034 /* Private typedef -----------------------------------------------------------*/
00035 /* Private define ------------------------------------------------------------*/
00036 #define BUFFER_SIZE        0x400
00037 #define WRITE_READ_ADDR    0x8000
00038
00039 /* Private macro -------------------------------------------------------------*/
00040 /* Private variables ---------------------------------------------------------*/
00041 uint16_t TxBuffer[BUFFER_SIZE];
00042 uint16_t RxBuffer[BUFFER_SIZE];
00043 uint32_t WriteReadStatus = 0, Index = 0;
00044 NOR_IDTypeDef NOR_ID;
00045
00046 /* Private function prototypes -----------------------------------------------*/
00047 void RCC_Configuration(void);
00048 void Fill_Buffer(uint16_t *pBuffer, uint16_t BufferLenght, uint32_t Offset);
00049
00050 /* Private functions ---------------------------------------------------------*/
00051
00052 /**
00053   * @brief   Main program.
00054   * @param  None
00055   * @retval None
00056   */
00057 int main(void)
00058 {
00059   /*!< At this stage the microcontroller clock setting is already configured,
00060        this is done through SystemInit() function which is called from startup
00061        file (startup_stm32f10x_xx.s) before to branch to application main.
00062        To reconfigure the default setting of SystemInit() function, refer to
00063        system_stm32f10x.c file
00064      */
00065
00066   /* Initialize Leds mounted on STM3210X-EVAL board */
00067   STM_EVAL_LEDInit(LED1);
00068   STM_EVAL_LEDInit(LED2);
00069
00070   /* Write/read to/from FSMC SRAM memory  *************************************/
00071   /* Enable the FSMC Clock */
00072   RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, ENABLE);
00073
00074   /* Configure FSMC Bank1 NOR/SRAM2 */
00075   NOR_Init();
00076
00077   /* Read NOR memory ID */
00078   NOR_ReadID(&NOR_ID);
00079
00080   NOR_ReturnToReadMode();
00081
00082   /* Erase the NOR memory block to write on */
00083   NOR_EraseBlock(WRITE_READ_ADDR);
00084
00085   /* Write data to FSMC NOR memory */
00086   /* Fill the buffer to send */
00087   Fill_Buffer(TxBuffer, BUFFER_SIZE, 0x3210);
00088   NOR_WriteBuffer(TxBuffer, WRITE_READ_ADDR, BUFFER_SIZE);
00089
00090   /* Read data from FSMC NOR memory */
00091   NOR_ReadBuffer(RxBuffer, WRITE_READ_ADDR, BUFFER_SIZE);
00092
00093   /* Read back NOR memory and check content correctness */
00094   for (Index = 0x00; (Index < BUFFER_SIZE) && (WriteReadStatus == 0); Index++)
00095   {
00096     if (RxBuffer[Index] != TxBuffer[Index])
00097     {
00098       WriteReadStatus = Index + 1;
00099     }
00100   }
00101
00102   if (WriteReadStatus == 0)
00103   {
00104     /* OK */
00105     /* Turn on LED1 */
00106     STM_EVAL_LEDOn(LED1);
00107   }
00108   else
00109   {
00110     /* KO */
00111     /* Turn on LED2 */
00112     STM_EVAL_LEDOn(LED2);
00113   }
00114
00115   while (1)
00116   {
00117   }
00118 }
00119
00120 /**
00121   * @brief  Fill the global buffer
00122   * @param  pBuffer: pointer on the Buffer to fill
00123   * @param  BufferSize: size of the buffer to fill
00124   * @param  Offset: first value to fill on the Buffer
00125   */
00126 void Fill_Buffer(uint16_t *pBuffer, uint16_t BufferLenght, uint32_t Offset)
00127 {
00128   uint16_t IndexTmp = 0;
00129
00130   /* Put in global buffer same values */
00131   for (IndexTmp = 0; IndexTmp < BufferLenght; IndexTmp++ )
00132   {
00133     pBuffer[IndexTmp] = IndexTmp + Offset;
00134   }
00135 }
00136
00137 #ifdef  USE_FULL_ASSERT
00138
00139 /**
00140   * @brief  Reports the name of the source file and the source line number
00141   *         where the assert_param error has occurred.
00142   * @param  file: pointer to the source file name
00143   * @param  line: assert_param error line source number
00144   * @retval None
00145   */
00146 void assert_failed(uint8_t* file, uint32_t line)
00147 {
00148   /* User can add his own implementation to report the file name and line number,
00149      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00150
00151   /* Infinite loop */
00152   while (1)
00153   {
00154   }
00155 }
00156
00157 #endif
00158
00159 /**
00160   * @}
00161   */
00162
00163 /**
00164   * @}
00165   */
00166
00167 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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STM32F10x_StdPeriph_Examples/FSMC/NOR/stm32f10x_conf.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    FSMC/NOR/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052 /* Exported types ------------------------------------------------------------*/
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Uncomment the line below to expanse the "assert_param" macro in the
00055    Standard Peripheral Library drivers code */
00056 /* #define USE_FULL_ASSERT    1 */
00057
00058 /* Exported macro ------------------------------------------------------------*/
00059 #ifdef  USE_FULL_ASSERT
00060
00061 /**
00062   * @brief  The assert_param macro is used for function's parameters check.
00063   * @param  expr: If expr is false, it calls assert_failed function which reports
00064   *         the name of the source file and the source line number of the call
00065   *         that failed. If expr is true, it returns no value.
00066   * @retval None
00067   */
00068   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00069 /* Exported functions ------------------------------------------------------- */
00070   void assert_failed(uint8_t* file, uint32_t line);
00071 #else
00072   #define assert_param(expr) ((void)0)
00073 #endif /* USE_FULL_ASSERT */
00074
00075 #endif /* __STM32F10x_CONF_H */
00076
00077 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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STM32F10x_StdPeriph_Examples/FSMC/NOR/stm32f10x_it.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    FSMC/NOR/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and peripherals
00009   *          interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026
00027 /** @addtogroup STM32F10x_StdPeriph_Examples
00028   * @{
00029   */
00030
00031 /** @addtogroup FSMC_NOR
00032   * @{
00033   */
00034
00035 /* Private typedef -----------------------------------------------------------*/
00036 /* Private define ------------------------------------------------------------*/
00037 /* Private macro -------------------------------------------------------------*/
00038 /* Private variables ---------------------------------------------------------*/
00039 /* Private function prototypes -----------------------------------------------*/
00040 /* Private functions ---------------------------------------------------------*/
00041
00042 /******************************************************************************/
00043 /*            Cortex-M3 Processor Exceptions Handlers                         */
00044 /******************************************************************************/
00045
00046 /**
00047   * @brief  This function handles NMI exception.
00048   * @param  None
00049   * @retval None
00050   */
00051 void NMI_Handler(void)
00052 {
00053 }
00054
00055 /**
00056   * @brief  This function handles Hard Fault exception.
00057   * @param  None
00058   * @retval None
00059   */
00060 void HardFault_Handler(void)
00061 {
00062   /* Go to infinite loop when Hard Fault exception occurs */
00063   while (1)
00064   {
00065   }
00066 }
00067
00068 /**
00069   * @brief  This function handles Memory Manage exception.
00070   * @param  None
00071   * @retval None
00072   */
00073 void MemManage_Handler(void)
00074 {
00075   /* Go to infinite loop when Memory Manage exception occurs */
00076   while (1)
00077   {
00078   }
00079 }
00080
00081 /**
00082   * @brief  This function handles Bus Fault exception.
00083   * @param  None
00084   * @retval None
00085   */
00086 void BusFault_Handler(void)
00087 {
00088   /* Go to infinite loop when Bus Fault exception occurs */
00089   while (1)
00090   {
00091   }
00092 }
00093
00094 /**
00095   * @brief  This function handles Usage Fault exception.
00096   * @param  None
00097   * @retval None
00098   */
00099 void UsageFault_Handler(void)
00100 {
00101   /* Go to infinite loop when Usage Fault exception occurs */
00102   while (1)
00103   {
00104   }
00105 }
00106
00107 /**
00108   * @brief  This function handles SVCall exception.
00109   * @param  None
00110   * @retval None
00111   */
00112 void SVC_Handler(void)
00113 {
00114 }
00115
00116 /**
00117   * @brief  This function handles Debug Monitor exception.
00118   * @param  None
00119   * @retval None
00120   */
00121 void DebugMon_Handler(void)
00122 {
00123 }
00124
00125 /**
00126   * @brief  This function handles PendSV_Handler exception.
00127   * @param  None
00128   * @retval None
00129   */
00130 void PendSV_Handler(void)
00131 {
00132 }
00133
00134 /**
00135   * @brief  This function handles SysTick Handler.
00136   * @param  None
00137   * @retval None
00138   */
00139 void SysTick_Handler(void)
00140 {
00141 }
00142
00143 /******************************************************************************/
00144 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00145 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00146 /*  available peripheral interrupt handler's name please refer to the startup */
00147 /*  file (startup_stm32f10x_xx.s).                                            */
00148 /******************************************************************************/
00149
00150 /**
00151   * @brief  This function handles PPP interrupt request.
00152   * @param  None
00153   * @retval None
00154   */
00155 /*void PPP_IRQHandler(void)
00156 {
00157 }*/
00158
00159 /**
00160   * @}
00161   */
00162
00163 /**
00164   * @}
00165   */
00166
00167 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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STM32F10x_StdPeriph_Examples/FSMC/NOR/stm32f10x_it.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    FSMC/NOR/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043
00044 #endif /* __STM32F10x_IT_H */
00045
00046 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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  • binary

STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/main.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    FSMC/NOR_CodeExecute/binary/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x.h"
00024 #include "stm32_eval.h"
00025
00026 /** @addtogroup STM32F10x_StdPeriph_Examples
00027   * @{
00028   */
00029
00030 /** @addtogroup FSMC_NOR_CodeExecute_binary
00031   * @{
00032   */
00033
00034 /* Private typedef -----------------------------------------------------------*/
00035 /* Private define ------------------------------------------------------------*/
00036 /* Private macro -------------------------------------------------------------*/
00037 /* Private variables ---------------------------------------------------------*/
00038 /* Private function prototypes -----------------------------------------------*/
00039 void Delay(__IO uint32_t nCount);
00040
00041 /* Private functions ---------------------------------------------------------*/
00042
00043 /**
00044   * @brief  Main program.
00045   * @param  None
00046   * @retval None
00047   */
00048 int main(void)
00049 {
00050   /*!< At this stage the microcontroller clock setting is already configured,
00051        this is done through SystemInit() function which is called from startup
00052        file (startup_stm32f10x_xx.s) before to branch to application main.
00053        To reconfigure the default setting of SystemInit() function, refer to
00054        system_stm32f10x.c file
00055      */
00056
00057   /* Initialize Leds mounted on STM3210X-EVAL board */
00058   STM_EVAL_LEDInit(LED1);
00059   STM_EVAL_LEDInit(LED2);
00060   STM_EVAL_LEDInit(LED3);
00061   STM_EVAL_LEDInit(LED4);
00062
00063   while (1)
00064   {
00065     /* Turn on LED1 */
00066     STM_EVAL_LEDOn(LED1);
00067     /* Insert delay */
00068     Delay(0xAFFFF);
00069
00070     /* Turn on LED2 */
00071     STM_EVAL_LEDOn(LED2);
00072     /* Turn on LED3 */
00073     STM_EVAL_LEDOn(LED3);
00074     /* Turn off LED1 */
00075     STM_EVAL_LEDOff(LED1);
00076     /* Insert delay */
00077     Delay(0xAFFFF);
00078
00079     /* Turn on LED4 */
00080     STM_EVAL_LEDOn(LED4);
00081     /* Turn off LED2 */
00082     STM_EVAL_LEDOff(LED2);
00083     /* Turn off LED3 */
00084     STM_EVAL_LEDOff(LED3);
00085     /* Insert delay */
00086     Delay(0xAFFFF);
00087
00088     /* Turn off LED4 */
00089     STM_EVAL_LEDOff(LED4);
00090   }
00091 }
00092
00093 /**
00094   * @brief  Inserts a delay time.
00095   * @param  nCount: specifies the delay time length.
00096   * @retval None
00097   */
00098 void Delay(__IO uint32_t nCount)
00099 {
00100   for(; nCount != 0; nCount--);
00101 }
00102
00103 #ifdef  USE_FULL_ASSERT
00104
00105 /**
00106   * @brief  Reports the name of the source file and the source line number
00107   *         where the assert_param error has occurred.
00108   * @param  file: pointer to the source file name
00109   * @param  line: assert_param error line source number
00110   * @retval None
00111   */
00112 void assert_failed(uint8_t* file, uint32_t line)
00113 {
00114   /* User can add his own implementation to report the file name and line number,
00115      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00116
00117   /* Infinite loop */
00118   while (1)
00119   {
00120   }
00121 }
00122
00123 #endif
00124
00125 /**
00126   * @}
00127   */
00128
00129 /**
00130   * @}
00131   */
00132
00133 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/stm32f10x_conf.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    FSMC/NOR_CodeExecute/binary/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052 /* Exported types ------------------------------------------------------------*/
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Uncomment the line below to expanse the "assert_param" macro in the
00055    Standard Peripheral Library drivers code */
00056 /* #define USE_FULL_ASSERT    1 */
00057
00058 /* Exported macro ------------------------------------------------------------*/
00059 #ifdef  USE_FULL_ASSERT
00060
00061 /**
00062   * @brief  The assert_param macro is used for function's parameters check.
00063   * @param  expr: If expr is false, it calls assert_failed function which reports
00064   *         the name of the source file and the source line number of the call
00065   *         that failed. If expr is true, it returns no value.
00066   * @retval None
00067   */
00068   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00069 /* Exported functions ------------------------------------------------------- */
00070   void assert_failed(uint8_t* file, uint32_t line);
00071 #else
00072   #define assert_param(expr) ((void)0)
00073 #endif /* USE_FULL_ASSERT */
00074
00075 #endif /* __STM32F10x_CONF_H */
00076
00077 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/stm32f10x_it.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    FSMC/NOR_CodeExecute/binary/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and
00009   *          peripherals interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026
00027 /** @addtogroup STM32F10x_StdPeriph_Examples
00028   * @{
00029   */
00030
00031 /** @addtogroup FSMC_NOR_CodeExecute_binary
00032   * @{
00033   */
00034
00035 /* Private typedef -----------------------------------------------------------*/
00036 /* Private define ------------------------------------------------------------*/
00037 /* Private macro -------------------------------------------------------------*/
00038 /* Private variables ---------------------------------------------------------*/
00039 /* Private function prototypes -----------------------------------------------*/
00040 /* Private functions ---------------------------------------------------------*/
00041
00042 /******************************************************************************/
00043 /*            Cortex-M3 Processor Exceptions Handlers                         */
00044 /******************************************************************************/
00045
00046 /**
00047   * @brief  This function handles NMI exception.
00048   * @param  None
00049   * @retval None
00050   */
00051 void NMI_Handler(void)
00052 {
00053 }
00054
00055 /**
00056   * @brief  This function handles Hard Fault exception.
00057   * @param  None
00058   * @retval None
00059   */
00060 void HardFault_Handler(void)
00061 {
00062   /* Go to infinite loop when Hard Fault exception occurs */
00063   while (1)
00064   {
00065   }
00066 }
00067
00068 /**
00069   * @brief  This function handles Memory Manage exception.
00070   * @param  None
00071   * @retval None
00072   */
00073 void MemManage_Handler(void)
00074 {
00075   /* Go to infinite loop when Memory Manage exception occurs */
00076   while (1)
00077   {
00078   }
00079 }
00080
00081 /**
00082   * @brief  This function handles Bus Fault exception.
00083   * @param  None
00084   * @retval None
00085   */
00086 void BusFault_Handler(void)
00087 {
00088   /* Go to infinite loop when Bus Fault exception occurs */
00089   while (1)
00090   {
00091   }
00092 }
00093
00094 /**
00095   * @brief  This function handles Usage Fault exception.
00096   * @param  None
00097   * @retval None
00098   */
00099 void UsageFault_Handler(void)
00100 {
00101   /* Go to infinite loop when Usage Fault exception occurs */
00102   while (1)
00103   {
00104   }
00105 }
00106
00107 /**
00108   * @brief  This function handles SVCall exception.
00109   * @param  None
00110   * @retval None
00111   */
00112 void SVC_Handler(void)
00113 {
00114 }
00115
00116 /**
00117   * @brief  This function handles Debug Monitor exception.
00118   * @param  None
00119   * @retval None
00120   */
00121 void DebugMon_Handler(void)
00122 {
00123 }
00124
00125 /**
00126   * @brief  This function handles PendSV_Handler exception.
00127   * @param  None
00128   * @retval None
00129   */
00130 void PendSV_Handler(void)
00131 {
00132 }
00133
00134 /**
00135   * @brief  This function handles SysTick Handler.
00136   * @param  None
00137   * @retval None
00138   */
00139 void SysTick_Handler(void)
00140 {
00141 }
00142
00143 /******************************************************************************/
00144 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00145 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00146 /*  available peripheral interrupt handler's name please refer to the startup */
00147 /*  file (startup_stm32f10x_xx.s).                                            */
00148 /******************************************************************************/
00149
00150 /**
00151   * @brief  This function handles PPP interrupt request.
00152   * @param  None
00153   * @retval None
00154   */
00155 /*void PPP_IRQHandler(void)
00156 {
00157 }*/
00158
00159 /**
00160   * @}
00161   */
00162
00163 /**
00164   * @}
00165   */
00166
00167 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/stm32f10x_it.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    FSMC/NOR_CodeExecute/binary/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043
00044 #endif /* __STM32F10x_IT_H */
00045
00046 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/main.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    FSMC/NOR_CodeExecute/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm3210e_eval_fsmc_nor.h"
00024
00025 /** @addtogroup STM32F10x_StdPeriph_Examples
00026   * @{
00027   */
00028
00029 /** @addtogroup FSMC_NOR_CodeExecute
00030   * @{
00031   */
00032
00033 /* Private typedef -----------------------------------------------------------*/
00034 typedef  void (*pFunction)(void);
00035
00036 /* Private define ------------------------------------------------------------*/
00037 #define ApplicationAddress       ((uint32_t)0x64000000)
00038
00039 /* Private macro -------------------------------------------------------------*/
00040 /* Private variables ---------------------------------------------------------*/
00041 pFunction Jump_To_Application;
00042 __IO uint32_t JumpAddress;
00043
00044 /* Private function prototypes -----------------------------------------------*/
00045 /* Private functions ---------------------------------------------------------*/
00046
00047 /**
00048   * @brief  Main program.
00049   * @param  None
00050   * @retval None
00051   */
00052 int main(void)
00053 {
00054   /*!< At this stage the microcontroller clock setting is already configured,
00055        this is done through SystemInit() function which is called from startup
00056        file (startup_stm32f10x_xx.s) before to branch to application main.
00057        To reconfigure the default setting of SystemInit() function, refer to
00058        system_stm32f10x.c file
00059      */
00060
00061   /* FSMC NOR configuration  **************************************************/
00062   /* Enable the FSMC Clock */
00063   RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, ENABLE);
00064
00065   /* Configure FSMC Bank1 NOR/SRAM2 */
00066   NOR_Init();
00067
00068   /* Jump to code loaded in NOR memory and execute it *************************/
00069   JumpAddress = *(__IO uint32_t*) (ApplicationAddress + 4);
00070   Jump_To_Application = (pFunction) JumpAddress;
00071
00072   /* Initialize user application's Stack Pointer */
00073   __set_MSP(*(__IO uint32_t*) ApplicationAddress);
00074
00075   Jump_To_Application();
00076
00077   while (1)
00078   {
00079   }
00080 }
00081
00082 #ifdef  USE_FULL_ASSERT
00083
00084 /**
00085   * @brief  Reports the name of the source file and the source line number
00086   *         where the assert_param error has occurred.
00087   * @param  file: pointer to the source file name
00088   * @param  line: assert_param error line source number
00089   * @retval None
00090   */
00091 void assert_failed(uint8_t* file, uint32_t line)
00092 {
00093   /* User can add his own implementation to report the file name and line number,
00094      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00095
00096   /* Infinite loop */
00097   while (1)
00098   {
00099   }
00100 }
00101
00102 #endif
00103
00104 /**
00105   * @}
00106   */
00107
00108 /**
00109   * @}
00110   */
00111
00112 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/stm32f10x_conf.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    FSMC/NOR_CodeExecute/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052 /* Exported types ------------------------------------------------------------*/
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Uncomment the line below to expanse the "assert_param" macro in the
00055    Standard Peripheral Library drivers code */
00056 /* #define USE_FULL_ASSERT    1 */
00057
00058 /* Exported macro ------------------------------------------------------------*/
00059 #ifdef  USE_FULL_ASSERT
00060
00061 /**
00062   * @brief  The assert_param macro is used for function's parameters check.
00063   * @param  expr: If expr is false, it calls assert_failed function which reports
00064   *         the name of the source file and the source line number of the call
00065   *         that failed. If expr is true, it returns no value.
00066   * @retval None
00067   */
00068   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00069 /* Exported functions ------------------------------------------------------- */
00070   void assert_failed(uint8_t* file, uint32_t line);
00071 #else
00072   #define assert_param(expr) ((void)0)
00073 #endif /* USE_FULL_ASSERT */
00074
00075 #endif /* __STM32F10x_CONF_H */
00076
00077 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/stm32f10x_it.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    FSMC/NOR_CodeExecute/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and peripherals
00009   *          interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026
00027 /** @addtogroup STM32F10x_StdPeriph_Examples
00028   * @{
00029   */
00030
00031 /** @addtogroup FSMC_NOR_CodeExecute
00032   * @{
00033   */
00034
00035 /* Private typedef -----------------------------------------------------------*/
00036 /* Private define ------------------------------------------------------------*/
00037 /* Private macro -------------------------------------------------------------*/
00038 /* Private variables ---------------------------------------------------------*/
00039 /* Private function prototypes -----------------------------------------------*/
00040 /* Private functions ---------------------------------------------------------*/
00041
00042 /******************************************************************************/
00043 /*            Cortex-M3 Processor Exceptions Handlers                         */
00044 /******************************************************************************/
00045
00046 /**
00047   * @brief  This function handles NMI exception.
00048   * @param  None
00049   * @retval None
00050   */
00051 void NMI_Handler(void)
00052 {
00053 }
00054
00055 /**
00056   * @brief  This function handles Hard Fault exception.
00057   * @param  None
00058   * @retval None
00059   */
00060 void HardFault_Handler(void)
00061 {
00062   /* Go to infinite loop when Hard Fault exception occurs */
00063   while (1)
00064   {
00065   }
00066 }
00067
00068 /**
00069   * @brief  This function handles Memory Manage exception.
00070   * @param  None
00071   * @retval None
00072   */
00073 void MemManage_Handler(void)
00074 {
00075   /* Go to infinite loop when Memory Manage exception occurs */
00076   while (1)
00077   {
00078   }
00079 }
00080
00081 /**
00082   * @brief  This function handles Bus Fault exception.
00083   * @param  None
00084   * @retval None
00085   */
00086 void BusFault_Handler(void)
00087 {
00088   /* Go to infinite loop when Bus Fault exception occurs */
00089   while (1)
00090   {
00091   }
00092 }
00093
00094 /**
00095   * @brief  This function handles Usage Fault exception.
00096   * @param  None
00097   * @retval None
00098   */
00099 void UsageFault_Handler(void)
00100 {
00101   /* Go to infinite loop when Usage Fault exception occurs */
00102   while (1)
00103   {
00104   }
00105 }
00106
00107 /**
00108   * @brief  This function handles SVCall exception.
00109   * @param  None
00110   * @retval None
00111   */
00112 void SVC_Handler(void)
00113 {
00114 }
00115
00116 /**
00117   * @brief  This function handles Debug Monitor exception.
00118   * @param  None
00119   * @retval None
00120   */
00121 void DebugMon_Handler(void)
00122 {
00123 }
00124
00125 /**
00126   * @brief  This function handles PendSV_Handler exception.
00127   * @param  None
00128   * @retval None
00129   */
00130 void PendSV_Handler(void)
00131 {
00132 }
00133
00134 /**
00135   * @brief  This function handles SysTick Handler.
00136   * @param  None
00137   * @retval None
00138   */
00139 void SysTick_Handler(void)
00140 {
00141 }
00142
00143 /******************************************************************************/
00144 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00145 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00146 /*  available peripheral interrupt handler's name please refer to the startup */
00147 /*  file (startup_stm32f10x_xx.s).                                            */
00148 /******************************************************************************/
00149
00150 /**
00151   * @brief  This function handles PPP interrupt request.
00152   * @param  None
00153   * @retval None
00154   */
00155 /*void PPP_IRQHandler(void)
00156 {
00157 }*/
00158
00159 /**
00160   * @}
00161   */
00162
00163 /**
00164   * @}
00165   */
00166
00167 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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  • NOR_CodeExecute

STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/stm32f10x_it.h

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00001 /**
00002   ******************************************************************************
00003   * @file    FSMC/NOR_CodeExecute/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043
00044 #endif /* __STM32F10x_IT_H */
00045
00046 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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STM32F10x_StdPeriph_Examples/FSMC/OneNAND/main.c

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00001 /**
00002   ******************************************************************************
00003   * @file    FSMC/OneNAND/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32_eval.h"
00024 #include "stm32100e_eval_fsmc_onenand.h"
00025
00026 /** @addtogroup STM32F10x_StdPeriph_Examples
00027   * @{
00028   */
00029
00030 /** @addtogroup FSMC_OneNAND
00031   * @{
00032   */
00033
00034 /* Private typedef -----------------------------------------------------------*/
00035 /* Private define ------------------------------------------------------------*/
00036 #define OneNAND_SAMSUNG_MANUFACTURER_ID     0x00EC
00037 #define OneNAND_SAMSUNG_DEVICE_ID           0x0025
00038
00039 #define OneNAND_BUFFER_SIZE                 0x0400 /* Page size: 1024 x 16 bits = 2048 Bytes */
00040 #define OneNAND_WRITE_BLOCK_NUMBER          0x0000 /* should be between 0 and 511, the block size is 128 KBytes */
00041 #define OneNAND_WRITE_PAGE_NUMBER           0x0000 /* The page size inside a Block is 2 KBytes */
00042 #define OneNAND_NUMBER_OF_PAGE_PER_BLOCK    0x0040 /* 64 pages per block */
00043
00044 /* Private macro -------------------------------------------------------------*/
00045 /* Private variables ---------------------------------------------------------*/
00046 OneNAND_IDTypeDef OneNAND_ID;
00047 OneNAND_ADDRESS Address;
00048 uint16_t TxBuffer[OneNAND_BUFFER_SIZE], RxBuffer_A[OneNAND_BUFFER_SIZE], RxBuffer_S[OneNAND_BUFFER_SIZE];
00049 uint32_t j = 0, PageIndex = 0, Status = 0;
00050
00051 /* Private function prototypes -----------------------------------------------*/
00052 void Fill_hBuffer(uint16_t *pBuffer, uint16_t BufferLenght, uint32_t Offset);
00053
00054 /* Private functions ---------------------------------------------------------*/
00055 /**
00056   * @brief  Main program.
00057   * @param  None
00058   * @retval None
00059   */
00060 int main(void)
00061 {
00062   /*!< At this stage the microcontroller clock setting is already configured,
00063        this is done through SystemInit() function which is called from startup
00064        file (startup_stm32f10x_xx.s) before to branch to application main.
00065        To reconfigure the default setting of SystemInit() function, refer to
00066        system_stm32f10x.c file
00067      */
00068
00069   /* Initialize LEDs on STM3220F-EVAL board */
00070   STM_EVAL_LEDInit(LED1);
00071   STM_EVAL_LEDInit(LED2);
00072   STM_EVAL_LEDInit(LED3);
00073   STM_EVAL_LEDInit(LED4);
00074
00075   /* FSMC Initialization */
00076   OneNAND_Init();
00077
00078   /* Read OneNAND memory ID */
00079   OneNAND_ReadID(&OneNAND_ID);
00080
00081   /* Verify the OneNAND ID */
00082   if((OneNAND_ID.Manufacturer_ID == OneNAND_SAMSUNG_MANUFACTURER_ID) &&
00083      (OneNAND_ID.Device_ID == OneNAND_SAMSUNG_DEVICE_ID))
00084   {
00085     /* Fill the buffer to send */
00086     Fill_hBuffer(TxBuffer, OneNAND_BUFFER_SIZE , 0x320F);
00087     Address.Block = OneNAND_WRITE_BLOCK_NUMBER;
00088     Address.Page = OneNAND_WRITE_PAGE_NUMBER;
00089
00090
00091     /***** Erase then write to the OneNAND memory ******************************/
00092     /* Unlock the selected OneNAND block */
00093     Status = OneNAND_UnlockBlock(OneNAND_WRITE_BLOCK_NUMBER);
00094
00095     if (Status == 0)
00096     {
00097       /* Erase the selected OneNAND block */
00098       Status = OneNAND_EraseBlock(Address.Block);
00099
00100       if (Status == 0)
00101       {
00102         /* Write data to the OneNAND memory (128Kbytes by page 2KBytes each) */
00103         for(PageIndex = 0; (PageIndex < OneNAND_NUMBER_OF_PAGE_PER_BLOCK) && (Status ==0); PageIndex++)
00104         {
00105           Status = OneNAND_WriteBuffer(TxBuffer, Address, OneNAND_BUFFER_SIZE);
00106           Address.Page++;
00107         }
00108
00109         if (Status == 0)
00110         {
00111           /***** Verify of the written data using asynchronous read ***********/
00112           Fill_hBuffer(RxBuffer_A, OneNAND_BUFFER_SIZE , 0xFF);
00113           Status = 0;
00114           Address.Block = OneNAND_WRITE_BLOCK_NUMBER;
00115           Address.Page = OneNAND_WRITE_PAGE_NUMBER;
00116
00117           for(PageIndex = 0; PageIndex < OneNAND_NUMBER_OF_PAGE_PER_BLOCK; PageIndex++)
00118           {
00119             /* Read back the written data (By page) */
00120             OneNAND_AsynchronousRead(RxBuffer_A, Address, OneNAND_BUFFER_SIZE);
00121
00122             /* Verify the written data */
00123             for(j = 0; j < OneNAND_BUFFER_SIZE; j++)
00124             {
00125               if(TxBuffer[j] != RxBuffer_A[j])
00126               {
00127                 Status++;
00128               }
00129             }
00130             Address.Page++;
00131           }
00132
00133           if (Status != 0)
00134           {
00135             /* Turn ON LED2 */
00136             STM_EVAL_LEDOn(LED2);
00137           }
00138
00139           /***** Verify of the written data using synchronous read ************/
00140           Fill_hBuffer(RxBuffer_S, OneNAND_BUFFER_SIZE , 0xFF);
00141           Status = 0;
00142           Address.Block = OneNAND_WRITE_BLOCK_NUMBER;
00143           Address.Page = OneNAND_WRITE_PAGE_NUMBER;
00144
00145           for(PageIndex = 0; PageIndex < OneNAND_NUMBER_OF_PAGE_PER_BLOCK; PageIndex++)
00146           {
00147             /* Read back the written data (By page) */
00148             OneNAND_SynchronousRead(RxBuffer_S, Address, OneNAND_BUFFER_SIZE);
00149
00150             /* Verify the written data */
00151             for(j = 0; j < OneNAND_BUFFER_SIZE; j++)
00152             {
00153               if(TxBuffer[j] != RxBuffer_S[j])
00154               {
00155                 Status++;
00156               }
00157             }
00158             Address.Page++;
00159           }
00160
00161           if (Status != 0)
00162           {
00163             /* Turn ON LED3 */
00164             STM_EVAL_LEDOn(LED3);
00165           }
00166         }
00167         else
00168         {
00169           /* Turn ON LED4 */
00170           STM_EVAL_LEDOn(LED4);
00171         }
00172       }
00173       else
00174       {
00175         /* Turn ON LED2 and LED4*/
00176         STM_EVAL_LEDOn(LED2);
00177         STM_EVAL_LEDOn(LED4);
00178       }
00179     }
00180     else
00181     {
00182       /* Turn ON LED3 and LED4 */
00183       STM_EVAL_LEDOn(LED3);
00184       STM_EVAL_LEDOn(LED4);
00185     }
00186   }
00187   else
00188   {
00189     /* Turn ON LED2, LED3 and LED4 */
00190     STM_EVAL_LEDOn(LED2);
00191     STM_EVAL_LEDOn(LED3);
00192     STM_EVAL_LEDOn(LED4);
00193   }
00194
00195   if (Status == 0)
00196   {
00197    /* Turn ON LED1 */
00198    STM_EVAL_LEDOn(LED1);
00199   }
00200
00201   /* Infinite loop */
00202   while (1)
00203   {
00204   }
00205 }
00206
00207 /**
00208   * @brief  Fills a global 16-bit buffer
00209   * @param  pBuffer: pointer on the Buffer to fill
00210   * @param  BufferSize: size of the buffer to fill
00211   * @param  Offset: first value to fill on the Buffer
00212   * @retval None
00213   */
00214 void Fill_hBuffer(uint16_t *pBuffer, uint16_t BufferLenght, uint32_t Offset)
00215 {
00216   uint16_t IndexTmp = 0;
00217
00218   /* Put in global buffer different values */
00219   for (IndexTmp = 0; IndexTmp < BufferLenght; IndexTmp++ )
00220   {
00221     pBuffer[IndexTmp] = IndexTmp + Offset;
00222   }
00223 }
00224
00225 #ifdef  USE_FULL_ASSERT
00226
00227 /**
00228   * @brief  Reports the name of the source file and the source line number
00229   *         where the assert_param error has occurred.
00230   * @param  file: pointer to the source file name
00231   * @param  line: assert_param error line source number
00232   * @retval None
00233   */
00234 void assert_failed(uint8_t* file, uint32_t line)
00235 {
00236   /* User can add his own implementation to report the file name and line number,
00237      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00238
00239   /* Infinite loop */
00240   while (1)
00241   {
00242   }
00243 }
00244
00245 #endif
00246
00247 /**
00248   * @}
00249   */
00250
00251
00252 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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STM32F10x_StdPeriph_Examples/FSMC/OneNAND/stm32f10x_conf.h

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00001 /**
00002   ******************************************************************************
00003   * @file    FSMC/OneNAND/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052 /* Exported types ------------------------------------------------------------*/
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Uncomment the line below to expanse the "assert_param" macro in the
00055    Standard Peripheral Library drivers code */
00056 /* #define USE_FULL_ASSERT    1 */
00057
00058 /* Exported macro ------------------------------------------------------------*/
00059 #ifdef  USE_FULL_ASSERT
00060
00061 /**
00062   * @brief  The assert_param macro is used for function's parameters check.
00063   * @param  expr: If expr is false, it calls assert_failed function which reports
00064   *         the name of the source file and the source line number of the call
00065   *         that failed. If expr is true, it returns no value.
00066   * @retval None
00067   */
00068   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00069 /* Exported functions ------------------------------------------------------- */
00070   void assert_failed(uint8_t* file, uint32_t line);
00071 #else
00072   #define assert_param(expr) ((void)0)
00073 #endif /* USE_FULL_ASSERT */
00074
00075 #endif /* __STM32F10x_CONF_H */
00076
00077 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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STM32F10x_StdPeriph_Examples/FSMC/OneNAND/stm32f10x_it.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    FSMC/OneNAND/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and
00009   *          peripherals interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026
00027 /** @addtogroup STM32F10x_StdPeriph_Examples
00028   * @{
00029   */
00030
00031 /** @addtogroup FSMC_OneNAND
00032   * @{
00033   */
00034
00035 /* Private typedef -----------------------------------------------------------*/
00036 /* Private define ------------------------------------------------------------*/
00037 /* Private macro -------------------------------------------------------------*/
00038 /* Private variables ---------------------------------------------------------*/
00039 /* Private function prototypes -----------------------------------------------*/
00040 /* Private functions ---------------------------------------------------------*/
00041
00042 /******************************************************************************/
00043 /*            Cortex-M3 Processor Exceptions Handlers                         */
00044 /******************************************************************************/
00045
00046 /**
00047   * @brief  This function handles NMI exception.
00048   * @param  None
00049   * @retval None
00050   */
00051 void NMI_Handler(void)
00052 {
00053 }
00054
00055 /**
00056   * @brief  This function handles Hard Fault exception.
00057   * @param  None
00058   * @retval None
00059   */
00060 void HardFault_Handler(void)
00061 {
00062   /* Go to infinite loop when Hard Fault exception occurs */
00063   while (1)
00064   {
00065   }
00066 }
00067
00068 /**
00069   * @brief  This function handles Memory Manage exception.
00070   * @param  None
00071   * @retval None
00072   */
00073 void MemManage_Handler(void)
00074 {
00075   /* Go to infinite loop when Memory Manage exception occurs */
00076   while (1)
00077   {
00078   }
00079 }
00080
00081 /**
00082   * @brief  This function handles Bus Fault exception.
00083   * @param  None
00084   * @retval None
00085   */
00086 void BusFault_Handler(void)
00087 {
00088   /* Go to infinite loop when Bus Fault exception occurs */
00089   while (1)
00090   {
00091   }
00092 }
00093
00094 /**
00095   * @brief  This function handles Usage Fault exception.
00096   * @param  None
00097   * @retval None
00098   */
00099 void UsageFault_Handler(void)
00100 {
00101   /* Go to infinite loop when Usage Fault exception occurs */
00102   while (1)
00103   {
00104   }
00105 }
00106
00107 /**
00108   * @brief  This function handles SVCall exception.
00109   * @param  None
00110   * @retval None
00111   */
00112 void SVC_Handler(void)
00113 {
00114 }
00115
00116 /**
00117   * @brief  This function handles Debug Monitor exception.
00118   * @param  None
00119   * @retval None
00120   */
00121 void DebugMon_Handler(void)
00122 {
00123 }
00124
00125 /**
00126   * @brief  This function handles PendSV_Handler exception.
00127   * @param  None
00128   * @retval None
00129   */
00130 void PendSV_Handler(void)
00131 {
00132 }
00133
00134 /**
00135   * @brief  This function handles SysTick Handler.
00136   * @param  None
00137   * @retval None
00138   */
00139 void SysTick_Handler(void)
00140 {
00141 }
00142
00143 /******************************************************************************/
00144 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00145 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00146 /*  available peripheral interrupt handler's name please refer to the startup */
00147 /*  file (startup_stm32f10x_xx.s).                                            */
00148 /******************************************************************************/
00149
00150 /**
00151   * @brief  This function handles PPP interrupt request.
00152   * @param  None
00153   * @retval None
00154   */
00155 /*void PPP_IRQHandler(void)
00156 {
00157 }*/
00158
00159 /**
00160   * @}
00161   */
00162
00163 /**
00164   * @}
00165   */
00166
00167 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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STM32F10x_StdPeriph_Examples/FSMC/OneNAND/stm32f10x_it.h

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00001 /**
00002   ******************************************************************************
00003   * @file    FSMC/OneNAND/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043
00044 #endif /* __STM32F10x_IT_H */
00045
00046 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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STM32F10x_StdPeriph_Examples/FSMC/SRAM/main.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    FSMC/SRAM/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #ifdef STM32F10X_HD_VL /* High-density Value line devices */
00024 #include "stm32100e_eval_fsmc_sram.h"
00025 #else /* High- and XL-denisty devices */
00026 #include "stm3210e_eval_fsmc_sram.h"
00027 #endif
00028
00029 #include "stm32_eval.h"
00030
00031 /** @addtogroup STM32F10x_StdPeriph_Examples
00032   * @{
00033   */
00034
00035 /** @addtogroup FSMC_SRAM
00036   * @{
00037   */
00038
00039 /* Private typedef -----------------------------------------------------------*/
00040 /* Private define ------------------------------------------------------------*/
00041 #define BUFFER_SIZE        0x400
00042 #define WRITE_READ_ADDR    0x8000
00043
00044 /* Private macro -------------------------------------------------------------*/
00045 /* Private variables ---------------------------------------------------------*/
00046 uint16_t TxBuffer[BUFFER_SIZE];
00047 uint16_t RxBuffer[BUFFER_SIZE];
00048 uint32_t WriteReadStatus = 0, Index = 0;
00049
00050 /* Private function prototypes -----------------------------------------------*/
00051 void Fill_Buffer(uint16_t *pBuffer, uint16_t BufferLenght, uint32_t Offset);
00052
00053 /* Private functions ---------------------------------------------------------*/
00054
00055 /**
00056   * @brief  Main program.
00057   * @param  None
00058   * @retval None
00059   */
00060 int main(void)
00061 {
00062   /*!< At this stage the microcontroller clock setting is already configured,
00063        this is done through SystemInit() function which is called from startup
00064        file (startup_stm32f10x_xx.s) before to branch to application main.
00065        To reconfigure the default setting of SystemInit() function, refer to
00066        system_stm32f10x.c file
00067      */
00068
00069   /* Initialize Leds mounted on STM3210X-EVAL board */
00070   STM_EVAL_LEDInit(LED1);
00071   STM_EVAL_LEDInit(LED2);
00072
00073   /* Write/read to/from FSMC SRAM memory  *************************************/
00074   /* Enable the FSMC Clock */
00075   RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, ENABLE);
00076
00077   /* Configure FSMC Bank1 NOR/SRAM3 */
00078   SRAM_Init();
00079
00080   /* Write data to FSMC SRAM memory */
00081   /* Fill the buffer to send */
00082   Fill_Buffer(TxBuffer, BUFFER_SIZE, 0x3212);
00083   SRAM_WriteBuffer(TxBuffer, WRITE_READ_ADDR, BUFFER_SIZE);
00084
00085
00086   /* Read data from FSMC SRAM memory */
00087   SRAM_ReadBuffer(RxBuffer, WRITE_READ_ADDR, BUFFER_SIZE);
00088
00089   /* Read back SRAM memory and check content correctness */
00090   for (Index = 0x00; (Index < BUFFER_SIZE) && (WriteReadStatus == 0); Index++)
00091   {
00092     if (RxBuffer[Index] != TxBuffer[Index])
00093     {
00094       WriteReadStatus = Index + 1;
00095     }
00096   }
00097
00098   if (WriteReadStatus == 0)
00099   {
00100     /* OK */
00101     /* Turn on LED1 */
00102     STM_EVAL_LEDOn(LED1);
00103   }
00104   else
00105   {
00106     /* KO */
00107     /* Turn on LED2 */
00108     STM_EVAL_LEDOn(LED2);
00109   }
00110
00111   while (1)
00112   {
00113   }
00114 }
00115
00116 /**
00117   * @brief  Fill the global buffer
00118   * @param  pBuffer: pointer on the Buffer to fill
00119   * @param  BufferSize: size of the buffer to fill
00120   * @param  Offset: first value to fill on the Buffer
00121   */
00122 void Fill_Buffer(uint16_t *pBuffer, uint16_t BufferLenght, uint32_t Offset)
00123 {
00124   uint16_t IndexTmp = 0;
00125
00126   /* Put in global buffer same values */
00127   for (IndexTmp = 0; IndexTmp < BufferLenght; IndexTmp++ )
00128   {
00129     pBuffer[IndexTmp] = IndexTmp + Offset;
00130   }
00131 }
00132
00133 #ifdef  USE_FULL_ASSERT
00134
00135 /**
00136   * @brief  Reports the name of the source file and the source line number
00137   *         where the assert_param error has occurred.
00138   * @param  file: pointer to the source file name
00139   * @param  line: assert_param error line source number
00140   * @retval None
00141   */
00142 void assert_failed(uint8_t* file, uint32_t line)
00143 {
00144   /* User can add his own implementation to report the file name and line number,
00145      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00146
00147   /* Infinite loop */
00148   while (1)
00149   {
00150   }
00151 }
00152
00153 #endif
00154
00155 /**
00156   * @}
00157   */
00158
00159 /**
00160   * @}
00161   */
00162
00163 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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STM32F10x_StdPeriph_Examples/FSMC/SRAM/stm32f10x_conf.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    FSMC/SRAM/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052 /* Exported types ------------------------------------------------------------*/
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Uncomment the line below to expanse the "assert_param" macro in the
00055    Standard Peripheral Library drivers code */
00056 /* #define USE_FULL_ASSERT    1 */
00057
00058 /* Exported macro ------------------------------------------------------------*/
00059 #ifdef  USE_FULL_ASSERT
00060
00061 /**
00062   * @brief  The assert_param macro is used for function's parameters check.
00063   * @param  expr: If expr is false, it calls assert_failed function which reports
00064   *         the name of the source file and the source line number of the call
00065   *         that failed. If expr is true, it returns no value.
00066   * @retval None
00067   */
00068   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00069 /* Exported functions ------------------------------------------------------- */
00070   void assert_failed(uint8_t* file, uint32_t line);
00071 #else
00072   #define assert_param(expr) ((void)0)
00073 #endif /* USE_FULL_ASSERT */
00074
00075 #endif /* __STM32F10x_CONF_H */
00076
00077 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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STM32F10x_StdPeriph_Examples/FSMC/SRAM/stm32f10x_it.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    FSMC/SRAM/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and
00009   *          peripherals interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026
00027 /** @addtogroup STM32F10x_StdPeriph_Examples
00028   * @{
00029   */
00030
00031 /** @addtogroup FSMC_SRAM
00032   * @{
00033   */
00034
00035 /* Private typedef -----------------------------------------------------------*/
00036 /* Private define ------------------------------------------------------------*/
00037 /* Private macro -------------------------------------------------------------*/
00038 /* Private variables ---------------------------------------------------------*/
00039 /* Private function prototypes -----------------------------------------------*/
00040 /* Private functions ---------------------------------------------------------*/
00041
00042 /******************************************************************************/
00043 /*            Cortex-M3 Processor Exceptions Handlers                         */
00044 /******************************************************************************/
00045
00046 /**
00047   * @brief  This function handles NMI exception.
00048   * @param  None
00049   * @retval None
00050   */
00051 void NMI_Handler(void)
00052 {
00053 }
00054
00055 /**
00056   * @brief  This function handles Hard Fault exception.
00057   * @param  None
00058   * @retval None
00059   */
00060 void HardFault_Handler(void)
00061 {
00062   /* Go to infinite loop when Hard Fault exception occurs */
00063   while (1)
00064   {
00065   }
00066 }
00067
00068 /**
00069   * @brief  This function handles Memory Manage exception.
00070   * @param  None
00071   * @retval None
00072   */
00073 void MemManage_Handler(void)
00074 {
00075   /* Go to infinite loop when Memory Manage exception occurs */
00076   while (1)
00077   {
00078   }
00079 }
00080
00081 /**
00082   * @brief  This function handles Bus Fault exception.
00083   * @param  None
00084   * @retval None
00085   */
00086 void BusFault_Handler(void)
00087 {
00088   /* Go to infinite loop when Bus Fault exception occurs */
00089   while (1)
00090   {
00091   }
00092 }
00093
00094 /**
00095   * @brief  This function handles Usage Fault exception.
00096   * @param  None
00097   * @retval None
00098   */
00099 void UsageFault_Handler(void)
00100 {
00101   /* Go to infinite loop when Usage Fault exception occurs */
00102   while (1)
00103   {
00104   }
00105 }
00106
00107 /**
00108   * @brief  This function handles SVCall exception.
00109   * @param  None
00110   * @retval None
00111   */
00112 void SVC_Handler(void)
00113 {
00114 }
00115
00116 /**
00117   * @brief  This function handles Debug Monitor exception.
00118   * @param  None
00119   * @retval None
00120   */
00121 void DebugMon_Handler(void)
00122 {
00123 }
00124
00125 /**
00126   * @brief  This function handles PendSV_Handler exception.
00127   * @param  None
00128   * @retval None
00129   */
00130 void PendSV_Handler(void)
00131 {
00132 }
00133
00134 /**
00135   * @brief  This function handles SysTick Handler.
00136   * @param  None
00137   * @retval None
00138   */
00139 void SysTick_Handler(void)
00140 {
00141 }
00142
00143 /******************************************************************************/
00144 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00145 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00146 /*  available peripheral interrupt handler's name please refer to the startup */
00147 /*  file (startup_stm32f10x_xx.s).                                            */
00148 /******************************************************************************/
00149
00150 /**
00151   * @brief  This function handles PPP interrupt request.
00152   * @param  None
00153   * @retval None
00154   */
00155 /*void PPP_IRQHandler(void)
00156 {
00157 }*/
00158
00159 /**
00160   * @}
00161   */
00162
00163 /**
00164   * @}
00165   */
00166
00167 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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STM32F10x_StdPeriph_Examples/FSMC/SRAM/stm32f10x_it.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    FSMC/SRAM/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043
00044 #endif /* __STM32F10x_IT_H */
00045
00046 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/main.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    FSMC/SRAM_DataMemory/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x.h"
00024
00025 /** @addtogroup STM32F10x_StdPeriph_Examples
00026   * @{
00027   */
00028
00029 /** @addtogroup FSMC_SRAM_DataMemory
00030   * @{
00031   */
00032
00033 /* Private typedef -----------------------------------------------------------*/
00034 /* Private define ------------------------------------------------------------*/
00035 /* Private macro -------------------------------------------------------------*/
00036 /* Private variables ---------------------------------------------------------*/
00037 uint32_t Tab[1024], Index;
00038 __IO uint32_t TabAddr, MSPValue = 0;
00039
00040 /* Private function prototypes -----------------------------------------------*/
00041 /* Private functions ---------------------------------------------------------*/
00042
00043 /**
00044   * @brief  Main program.
00045   * @param  None
00046   * @retval None
00047   */
00048 int main(void)
00049 {
00050   /*!< At this stage the microcontroller clock setting is already configured,
00051        this is done through SystemInit() function which is called from startup
00052        file (startup_stm32f10x_xx.s) before to branch to application main.
00053        To reconfigure the default setting of SystemInit() function, refer to
00054        system_stm32f10x.c file
00055      */
00056
00057   for (Index = 0; Index <1024 ; Index++)
00058   {
00059      Tab[Index] =Index;
00060   }
00061
00062   TabAddr = (uint32_t)Tab; /* should be 0x680xxxxx */
00063
00064   /* Get main stack pointer value */
00065   MSPValue = __get_MSP(); /* should be 0x680xxxxx */
00066
00067   /* Infinite loop */
00068   while (1)
00069   {
00070   }
00071 }
00072
00073 #ifdef  USE_FULL_ASSERT
00074
00075 /**
00076   * @brief  Reports the name of the source file and the source line number
00077   *         where the assert_param error has occurred.
00078   * @param  file: pointer to the source file name
00079   * @param  line: assert_param error line source number
00080   * @retval None
00081   */
00082 void assert_failed(uint8_t* file, uint32_t line)
00083 {
00084   /* User can add his own implementation to report the file name and line number,
00085      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00086
00087   /* Infinite loop */
00088   while (1)
00089   {
00090   }
00091 }
00092
00093 #endif
00094
00095 /**
00096   * @}
00097   */
00098
00099 /**
00100   * @}
00101   */
00102
00103 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/stm32f10x_conf.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    FSMC/SRAM_DataMemory/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052 /* Exported types ------------------------------------------------------------*/
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Uncomment the line below to expanse the "assert_param" macro in the
00055    Standard Peripheral Library drivers code */
00056 /* #define USE_FULL_ASSERT    1 */
00057
00058 /* Exported macro ------------------------------------------------------------*/
00059 #ifdef  USE_FULL_ASSERT
00060
00061 /**
00062   * @brief  The assert_param macro is used for function's parameters check.
00063   * @param  expr: If expr is false, it calls assert_failed function which reports
00064   *         the name of the source file and the source line number of the call
00065   *         that failed. If expr is true, it returns no value.
00066   * @retval None
00067   */
00068   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00069 /* Exported functions ------------------------------------------------------- */
00070   void assert_failed(uint8_t* file, uint32_t line);
00071 #else
00072   #define assert_param(expr) ((void)0)
00073 #endif /* USE_FULL_ASSERT */
00074
00075 #endif /* __STM32F10x_CONF_H */
00076
00077 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/stm32f10x_it.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    FSMC/SRAM_DataMemory/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and
00009   *          peripherals interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026
00027 /** @addtogroup STM32F10x_StdPeriph_Examples
00028   * @{
00029   */
00030
00031 /** @addtogroup FSMC_SRAM_DataMemory
00032   * @{
00033   */
00034
00035 /* Private typedef -----------------------------------------------------------*/
00036 /* Private define ------------------------------------------------------------*/
00037 /* Private macro -------------------------------------------------------------*/
00038 /* Private variables ---------------------------------------------------------*/
00039 /* Private function prototypes -----------------------------------------------*/
00040 /* Private functions ---------------------------------------------------------*/
00041
00042 /******************************************************************************/
00043 /*            Cortex-M3 Processor Exceptions Handlers                         */
00044 /******************************************************************************/
00045
00046 /**
00047   * @brief  This function handles NMI exception.
00048   * @param  None
00049   * @retval None
00050   */
00051 void NMI_Handler(void)
00052 {
00053 }
00054
00055 /**
00056   * @brief  This function handles Hard Fault exception.
00057   * @param  None
00058   * @retval None
00059   */
00060 void HardFault_Handler(void)
00061 {
00062   /* Go to infinite loop when Hard Fault exception occurs */
00063   while (1)
00064   {
00065   }
00066 }
00067
00068 /**
00069   * @brief  This function handles Memory Manage exception.
00070   * @param  None
00071   * @retval None
00072   */
00073 void MemManage_Handler(void)
00074 {
00075   /* Go to infinite loop when Memory Manage exception occurs */
00076   while (1)
00077   {
00078   }
00079 }
00080
00081 /**
00082   * @brief  This function handles Bus Fault exception.
00083   * @param  None
00084   * @retval None
00085   */
00086 void BusFault_Handler(void)
00087 {
00088   /* Go to infinite loop when Bus Fault exception occurs */
00089   while (1)
00090   {
00091   }
00092 }
00093
00094 /**
00095   * @brief  This function handles Usage Fault exception.
00096   * @param  None
00097   * @retval None
00098   */
00099 void UsageFault_Handler(void)
00100 {
00101   /* Go to infinite loop when Usage Fault exception occurs */
00102   while (1)
00103   {
00104   }
00105 }
00106
00107 /**
00108   * @brief  This function handles SVCall exception.
00109   * @param  None
00110   * @retval None
00111   */
00112 void SVC_Handler(void)
00113 {
00114 }
00115
00116 /**
00117   * @brief  This function handles Debug Monitor exception.
00118   * @param  None
00119   * @retval None
00120   */
00121 void DebugMon_Handler(void)
00122 {
00123 }
00124
00125 /**
00126   * @brief  This function handles PendSV_Handler exception.
00127   * @param  None
00128   * @retval None
00129   */
00130 void PendSV_Handler(void)
00131 {
00132 }
00133
00134 /**
00135   * @brief  This function handles SysTick Handler.
00136   * @param  None
00137   * @retval None
00138   */
00139 void SysTick_Handler(void)
00140 {
00141 }
00142
00143 /******************************************************************************/
00144 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00145 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00146 /*  available peripheral interrupt handler's name please refer to the startup */
00147 /*  file (startup_stm32f10x_xx.s).                                            */
00148 /******************************************************************************/
00149
00150 /**
00151   * @brief  This function handles PPP interrupt request.
00152   * @param  None
00153   * @retval None
00154   */
00155 /*void PPP_IRQHandler(void)
00156 {
00157 }*/
00158
00159 /**
00160   * @}
00161   */
00162
00163 /**
00164   * @}
00165   */
00166
00167 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/stm32f10x_it.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    FSMC/SRAM_DataMemory/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043
00044 #endif /* __STM32F10x_IT_H */
00045
00046 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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STM32F10x_StdPeriph_Examples/GPIO/IOToggle/main.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    GPIO/IOToggle/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x.h"
00024 #include "stm32_eval.h"
00025
00026 /** @addtogroup STM32F10x_StdPeriph_Examples
00027   * @{
00028   */
00029
00030 /** @addtogroup GPIO_IOToggle
00031   * @{
00032   */
00033
00034 /* Private typedef -----------------------------------------------------------*/
00035 /* Private define ------------------------------------------------------------*/
00036 /* Private macro -------------------------------------------------------------*/
00037 /* Private variables ---------------------------------------------------------*/
00038 GPIO_InitTypeDef GPIO_InitStructure;
00039
00040 /* Private function prototypes -----------------------------------------------*/
00041 /* Private functions ---------------------------------------------------------*/
00042
00043 /**
00044   * @brief  Main program.
00045   * @param  None
00046   * @retval None
00047   */
00048 int main(void)
00049 {
00050   /*!< At this stage the microcontroller clock setting is already configured,
00051        this is done through SystemInit() function which is called from startup
00052        file (startup_stm32f10x_xx.s) before to branch to application main.
00053        To reconfigure the default setting of SystemInit() function, refer to
00054        system_stm32f10x.c file
00055      */
00056
00057   /* GPIOD Periph clock enable */
00058   RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD, ENABLE);
00059
00060   /* Configure PD0 and PD2 in output pushpull mode */
00061   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_2;
00062   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00063   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
00064   GPIO_Init(GPIOD, &GPIO_InitStructure);
00065
00066   /* To achieve GPIO toggling maximum frequency, the following  sequence is mandatory.
00067      You can monitor PD0 or PD2 on the scope to measure the output signal.
00068      If you need to fine tune this frequency, you can add more GPIO set/reset
00069      cycles to minimize more the infinite loop timing.
00070      This code needs to be compiled with high speed optimization option.  */
00071   while (1)
00072   {
00073     /* Set PD0 and PD2 */
00074     GPIOD->BSRR = 0x00000005;
00075     /* Reset PD0 and PD2 */
00076     GPIOD->BRR  = 0x00000005;
00077
00078     /* Set PD0 and PD2 */
00079     GPIOD->BSRR = 0x00000005;
00080     /* Reset PD0 and PD2 */
00081     GPIOD->BRR  = 0x00000005;
00082
00083     /* Set PD0 and PD2 */
00084     GPIOD->BSRR = 0x00000005;
00085     /* Reset PD0 and PD2 */
00086     GPIOD->BRR  = 0x00000005;
00087
00088     /* Set PD0 and PD2 */
00089     GPIOD->BSRR = 0x00000005;
00090     /* Reset PD0 and PD2 */
00091     GPIOD->BRR  = 0x00000005;
00092
00093     /* Set PD0 and PD2 */
00094     GPIOD->BSRR = 0x00000005;
00095     /* Reset PD0 and PD2 */
00096     GPIOD->BRR  = 0x00000005;
00097
00098     /* Set PD0 and PD2 */
00099     GPIOD->BSRR = 0x00000005;
00100     /* Reset PD0 and PD2 */
00101     GPIOD->BRR  = 0x00000005;
00102
00103     /* Set PD0 and PD2 */
00104     GPIOD->BSRR = 0x00000005;
00105     /* Reset PD0 and PD2 */
00106     GPIOD->BRR  = 0x00000005;
00107
00108     /* Set PD0 and PD2 */
00109     GPIOD->BSRR = 0x00000005;
00110     /* Reset PD0 and PD2 */
00111     GPIOD->BRR  = 0x00000005;
00112
00113     /* Set PD0 and PD2 */
00114     GPIOD->BSRR = 0x00000005;
00115     /* Reset PD0 and PD2 */
00116     GPIOD->BRR  = 0x00000005;
00117
00118     /* Set PD0 and PD2 */
00119     GPIOD->BSRR = 0x00000005;
00120     /* Reset PD0 and PD2 */
00121     GPIOD->BRR  = 0x00000005;
00122   }
00123 }
00124
00125 #ifdef  USE_FULL_ASSERT
00126
00127 /**
00128   * @brief  Reports the name of the source file and the source line number
00129   *         where the assert_param error has occurred.
00130   * @param  file: pointer to the source file name
00131   * @param  line: assert_param error line source number
00132   * @retval None
00133   */
00134 void assert_failed(uint8_t* file, uint32_t line)
00135 {
00136   /* User can add his own implementation to report the file name and line number,
00137      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00138
00139   /* Infinite loop */
00140   while (1)
00141   {
00142   }
00143 }
00144
00145 #endif
00146
00147 /**
00148   * @}
00149   */
00150
00151 /**
00152   * @}
00153   */
00154
00155 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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STM32F10x_StdPeriph_Examples/GPIO/IOToggle/stm32f10x_conf.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    GPIO/IOToggle/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052 /* Exported types ------------------------------------------------------------*/
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Uncomment the line below to expanse the "assert_param" macro in the
00055    Standard Peripheral Library drivers code */
00056 /* #define USE_FULL_ASSERT    1 */
00057
00058 /* Exported macro ------------------------------------------------------------*/
00059 #ifdef  USE_FULL_ASSERT
00060
00061 /**
00062   * @brief  The assert_param macro is used for function's parameters check.
00063   * @param  expr: If expr is false, it calls assert_failed function which reports
00064   *         the name of the source file and the source line number of the call
00065   *         that failed. If expr is true, it returns no value.
00066   * @retval None
00067   */
00068   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00069 /* Exported functions ------------------------------------------------------- */
00070   void assert_failed(uint8_t* file, uint32_t line);
00071 #else
00072   #define assert_param(expr) ((void)0)
00073 #endif /* USE_FULL_ASSERT */
00074
00075 #endif /* __STM32F10x_CONF_H */
00076
00077 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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STM32F10x_StdPeriph_Examples/GPIO/IOToggle/stm32f10x_it.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    GPIO/IOToggle/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and peripherals
00009   *          interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026
00027 /** @addtogroup STM32F10x_StdPeriph_Examples
00028   * @{
00029   */
00030
00031 /** @addtogroup GPIO_IOToggle
00032   * @{
00033   */
00034
00035 /* Private typedef -----------------------------------------------------------*/
00036 /* Private define ------------------------------------------------------------*/
00037 /* Private macro -------------------------------------------------------------*/
00038 /* Private variables ---------------------------------------------------------*/
00039 /* Private function prototypes -----------------------------------------------*/
00040 /* Private functions ---------------------------------------------------------*/
00041
00042 /******************************************************************************/
00043 /*            Cortex-M3 Processor Exceptions Handlers                         */
00044 /******************************************************************************/
00045
00046 /**
00047   * @brief  This function handles NMI exception.
00048   * @param  None
00049   * @retval None
00050   */
00051 void NMI_Handler(void)
00052 {
00053 }
00054
00055 /**
00056   * @brief  This function handles Hard Fault exception.
00057   * @param  None
00058   * @retval None
00059   */
00060 void HardFault_Handler(void)
00061 {
00062   /* Go to infinite loop when Hard Fault exception occurs */
00063   while (1)
00064   {
00065   }
00066 }
00067
00068 /**
00069   * @brief  This function handles Memory Manage exception.
00070   * @param  None
00071   * @retval None
00072   */
00073 void MemManage_Handler(void)
00074 {
00075   /* Go to infinite loop when Memory Manage exception occurs */
00076   while (1)
00077   {
00078   }
00079 }
00080
00081 /**
00082   * @brief  This function handles Bus Fault exception.
00083   * @param  None
00084   * @retval None
00085   */
00086 void BusFault_Handler(void)
00087 {
00088   /* Go to infinite loop when Bus Fault exception occurs */
00089   while (1)
00090   {
00091   }
00092 }
00093
00094 /**
00095   * @brief  This function handles Usage Fault exception.
00096   * @param  None
00097   * @retval None
00098   */
00099 void UsageFault_Handler(void)
00100 {
00101   /* Go to infinite loop when Usage Fault exception occurs */
00102   while (1)
00103   {
00104   }
00105 }
00106
00107 /**
00108   * @brief  This function handles SVCall exception.
00109   * @param  None
00110   * @retval None
00111   */
00112 void SVC_Handler(void)
00113 {
00114 }
00115
00116 /**
00117   * @brief  This function handles Debug Monitor exception.
00118   * @param  None
00119   * @retval None
00120   */
00121 void DebugMon_Handler(void)
00122 {
00123 }
00124
00125 /**
00126   * @brief  This function handles PendSV_Handler exception.
00127   * @param  None
00128   * @retval None
00129   */
00130 void PendSV_Handler(void)
00131 {
00132 }
00133
00134 /**
00135   * @brief  This function handles SysTick Handler.
00136   * @param  None
00137   * @retval None
00138   */
00139 void SysTick_Handler(void)
00140 {
00141 }
00142
00143 /******************************************************************************/
00144 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00145 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00146 /*  available peripheral interrupt handler's name please refer to the startup */
00147 /*  file (startup_stm32f10x_xx.s).                                            */
00148 /******************************************************************************/
00149
00150 /**
00151   * @brief  This function handles PPP interrupt request.
00152   * @param  None
00153   * @retval None
00154   */
00155 /*void PPP_IRQHandler(void)
00156 {
00157 }*/
00158
00159 /**
00160   * @}
00161   */
00162
00163 /**
00164   * @}
00165   */
00166
00167 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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STM32F10x_StdPeriph_Examples/GPIO/IOToggle/stm32f10x_it.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    GPIO/IOToggle/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043
00044 #endif /* __STM32F10x_IT_H */
00045
00046 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/main.c

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00001 /**
00002   ******************************************************************************
00003   * @file    GPIO/JTAG_Remap/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x.h"
00024 #include "stm32_eval.h"
00025
00026 /** @addtogroup STM32F10x_StdPeriph_Examples
00027   * @{
00028   */
00029
00030 /** @addtogroup GPIO_JTAG_Remap
00031   * @{
00032   */
00033
00034 /* Private typedef -----------------------------------------------------------*/
00035 /* Private define ------------------------------------------------------------*/
00036 /* Private macro -------------------------------------------------------------*/
00037 /* Private variables ---------------------------------------------------------*/
00038 GPIO_InitTypeDef GPIO_InitStructure;
00039
00040 /* Private function prototypes -----------------------------------------------*/
00041 void RCC_Configuration(void);
00042 void Delay(__IO uint32_t nCount);
00043
00044 /* Private functions ---------------------------------------------------------*/
00045
00046 /**
00047   * @brief  Main program.
00048   * @param  None
00049   * @retval None
00050   */
00051 int main(void)
00052 {
00053   /*!< At this stage the microcontroller clock setting is already configured,
00054        this is done through SystemInit() function which is called from startup
00055        file (startup_stm32f10x_xx.s) before to branch to application main.
00056        To reconfigure the default setting of SystemInit() function, refer to
00057        system_stm32f10x.c file
00058      */
00059
00060   /* Configure the system clocks */
00061   RCC_Configuration();
00062
00063   /* Initialize LEDs and Key Button mounted on STM3210X-EVAL board */
00064   STM_EVAL_LEDInit(LED1);
00065   STM_EVAL_LEDInit(LED2);
00066
00067   STM_EVAL_PBInit(BUTTON_KEY, BUTTON_MODE_GPIO);
00068
00069   /* Test if Key Button GPIO Pin level is low (Key push-button on Eval Board pressed) */
00070   if (STM_EVAL_PBGetState(BUTTON_KEY) == 0x00)
00071   { /* Key is pressed */
00072
00073      /* Turn on LED1 */
00074      STM_EVAL_LEDOn(LED1);
00075
00076     /* Disable the Serial Wire Jtag Debug Port SWJ-DP */
00077     GPIO_PinRemapConfig(GPIO_Remap_SWJ_Disable, ENABLE);
00078
00079     /* Configure PA.13 (JTMS/SWDAT), PA.14 (JTCK/SWCLK) and PA.15 (JTDI) as
00080        output push-pull */
00081     GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15;
00082     GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00083     GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
00084     GPIO_Init(GPIOA, &GPIO_InitStructure);
00085
00086     /* Configure PB.03 (JTDO) and PB.04 (JTRST) as output push-pull */
00087     GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3 | GPIO_Pin_4;
00088     GPIO_Init(GPIOB, &GPIO_InitStructure);
00089
00090     while (1)
00091     {
00092       /* Toggle JTMS/SWDAT pin */
00093       GPIO_WriteBit(GPIOA, GPIO_Pin_13, (BitAction)(1 - GPIO_ReadOutputDataBit(GPIOA, GPIO_Pin_13)));
00094       /* Insert delay */
00095       Delay(0x5FFFF);
00096
00097       /* Toggle JTCK/SWCLK pin */
00098       GPIO_WriteBit(GPIOA, GPIO_Pin_14, (BitAction)(1 - GPIO_ReadOutputDataBit(GPIOA, GPIO_Pin_14)));
00099       /* Insert delay */
00100       Delay(0x5FFFF);
00101
00102       /* Toggle JTDI pin */
00103       GPIO_WriteBit(GPIOA, GPIO_Pin_15, (BitAction)(1 - GPIO_ReadOutputDataBit(GPIOA, GPIO_Pin_15)));
00104       /* Insert delay */
00105       Delay(0x5FFFF);
00106
00107       /* Toggle JTDO pin */
00108       GPIO_WriteBit(GPIOB, GPIO_Pin_3, (BitAction)(1 - GPIO_ReadOutputDataBit(GPIOB, GPIO_Pin_3)));
00109       /* Insert delay */
00110       Delay(0x5FFFF);
00111
00112       /* Toggle JTRST pin */
00113       GPIO_WriteBit(GPIOB, GPIO_Pin_4, (BitAction)(1 - GPIO_ReadOutputDataBit(GPIOB, GPIO_Pin_4)));
00114       /* Insert delay */
00115       Delay(0x5FFFF);
00116     }
00117   }
00118   else
00119   {
00120     /* Turn on LED2 */
00121     STM_EVAL_LEDOn(LED2);
00122
00123     while (1)
00124     {
00125     }
00126   }
00127 }
00128
00129 /**
00130   * @brief  Configures the different system clocks.
00131   * @param  None
00132   * @retval None
00133   */
00134 void RCC_Configuration(void)
00135 {
00136   /* Enable GPIOA, GPIOB, RCC_APB2Periph_GPIO_KEY_BUTTON and AFIO clocks */
00137   RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB |
00138                          RCC_APB2Periph_AFIO, ENABLE);
00139 }
00140
00141 /**
00142   * @brief  Inserts a delay time.
00143   * @param  nCount: specifies the delay time length.
00144   * @retval None
00145   */
00146 void Delay(__IO uint32_t nCount)
00147 {
00148   for(; nCount != 0; nCount--);
00149 }
00150
00151 #ifdef  USE_FULL_ASSERT
00152
00153 /**
00154   * @brief  Reports the name of the source file and the source line number
00155   *         where the assert_param error has occurred.
00156   * @param  file: pointer to the source file name
00157   * @param  line: assert_param error line source number
00158   * @retval None
00159   */
00160 void assert_failed(uint8_t* file, uint32_t line)
00161 {
00162   /* User can add his own implementation to report the file name and line number,
00163      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00164
00165   /* Infinite loop */
00166   while (1)
00167   {
00168   }
00169 }
00170
00171 #endif
00172
00173 /**
00174   * @}
00175   */
00176
00177 /**
00178   * @}
00179   */
00180
00181 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/stm32f10x_conf.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    GPIO/JTAG_Remap/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052 /* Exported types ------------------------------------------------------------*/
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Uncomment the line below to expanse the "assert_param" macro in the
00055    Standard Peripheral Library drivers code */
00056 /* #define USE_FULL_ASSERT    1 */
00057
00058 /* Exported macro ------------------------------------------------------------*/
00059 #ifdef  USE_FULL_ASSERT
00060
00061 /**
00062   * @brief  The assert_param macro is used for function's parameters check.
00063   * @param  expr: If expr is false, it calls assert_failed function which reports
00064   *         the name of the source file and the source line number of the call
00065   *         that failed. If expr is true, it returns no value.
00066   * @retval None
00067   */
00068   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00069 /* Exported functions ------------------------------------------------------- */
00070   void assert_failed(uint8_t* file, uint32_t line);
00071 #else
00072   #define assert_param(expr) ((void)0)
00073 #endif /* USE_FULL_ASSERT */
00074
00075 #endif /* __STM32F10x_CONF_H */
00076
00077 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/stm32f10x_it.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    GPIO/JTAG_Remap/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and peripherals
00009   *          interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026
00027 /** @addtogroup STM32F10x_StdPeriph_Examples
00028   * @{
00029   */
00030
00031 /** @addtogroup GPIO_JTAG_Remap
00032   * @{
00033   */
00034
00035 /* Private typedef -----------------------------------------------------------*/
00036 /* Private define ------------------------------------------------------------*/
00037 /* Private macro -------------------------------------------------------------*/
00038 /* Private variables ---------------------------------------------------------*/
00039 /* Private function prototypes -----------------------------------------------*/
00040 /* Private functions ---------------------------------------------------------*/
00041
00042 /******************************************************************************/
00043 /*            Cortex-M3 Processor Exceptions Handlers                         */
00044 /******************************************************************************/
00045
00046 /**
00047   * @brief  This function handles NMI exception.
00048   * @param  None
00049   * @retval None
00050   */
00051 void NMI_Handler(void)
00052 {
00053 }
00054
00055 /**
00056   * @brief  This function handles Hard Fault exception.
00057   * @param  None
00058   * @retval None
00059   */
00060 void HardFault_Handler(void)
00061 {
00062   /* Go to infinite loop when Hard Fault exception occurs */
00063   while (1)
00064   {
00065   }
00066 }
00067
00068 /**
00069   * @brief  This function handles Memory Manage exception.
00070   * @param  None
00071   * @retval None
00072   */
00073 void MemManage_Handler(void)
00074 {
00075   /* Go to infinite loop when Memory Manage exception occurs */
00076   while (1)
00077   {
00078   }
00079 }
00080
00081 /**
00082   * @brief  This function handles Bus Fault exception.
00083   * @param  None
00084   * @retval None
00085   */
00086 void BusFault_Handler(void)
00087 {
00088   /* Go to infinite loop when Bus Fault exception occurs */
00089   while (1)
00090   {
00091   }
00092 }
00093
00094 /**
00095   * @brief  This function handles Usage Fault exception.
00096   * @param  None
00097   * @retval None
00098   */
00099 void UsageFault_Handler(void)
00100 {
00101   /* Go to infinite loop when Usage Fault exception occurs */
00102   while (1)
00103   {
00104   }
00105 }
00106
00107 /**
00108   * @brief  This function handles SVCall exception.
00109   * @param  None
00110   * @retval None
00111   */
00112 void SVC_Handler(void)
00113 {
00114 }
00115
00116 /**
00117   * @brief  This function handles Debug Monitor exception.
00118   * @param  None
00119   * @retval None
00120   */
00121 void DebugMon_Handler(void)
00122 {
00123 }
00124
00125 /**
00126   * @brief  This function handles PendSV_Handler exception.
00127   * @param  None
00128   * @retval None
00129   */
00130 void PendSV_Handler(void)
00131 {
00132 }
00133
00134 /**
00135   * @brief  This function handles SysTick Handler.
00136   * @param  None
00137   * @retval None
00138   */
00139 void SysTick_Handler(void)
00140 {
00141 }
00142
00143 /******************************************************************************/
00144 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00145 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00146 /*  available peripheral interrupt handler's name please refer to the startup */
00147 /*  file (startup_stm32f10x_xx.s).                                            */
00148 /******************************************************************************/
00149
00150 /**
00151   * @brief  This function handles PPP interrupt request.
00152   * @param  None
00153   * @retval None
00154   */
00155 /*void PPP_IRQHandler(void)
00156 {
00157 }*/
00158
00159 /**
00160   * @}
00161   */
00162
00163 /**
00164   * @}
00165   */
00166
00167 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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  • JTAG_Remap

STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/stm32f10x_it.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    GPIO/JTAG_Remap/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043
00044 #endif /* __STM32F10x_IT_H */
00045
00046 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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  • I2C
  • EEPROM

STM32F10x_StdPeriph_Examples/I2C/EEPROM/main.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    I2C/EEPROM/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32_eval_i2c_ee.h"
00024
00025
00026 #ifdef USE_STM3210E_EVAL
00027  #include "stm3210e_eval_lcd.h"
00028 #elif defined(USE_STM3210B_EVAL)
00029  #include "stm3210b_eval_lcd.h"
00030 #elif defined(USE_STM3210C_EVAL)
00031  #include "stm3210c_eval_lcd.h"
00032 #elif defined(USE_STM32100B_EVAL)
00033  #include "stm32100b_eval_lcd.h"
00034 #elif defined(USE_STM32100E_EVAL)
00035  #include "stm32100e_eval_lcd.h"
00036 #endif /* USE_STM3210E_EVAL */
00037
00038 /** @addtogroup STM32F10x_StdPeriph_Examples
00039   * @{
00040   */
00041
00042 /** @addtogroup I2C_EEPROM
00043   * @{
00044   */
00045
00046 /* Private typedef -----------------------------------------------------------*/
00047 typedef enum {FAILED = 0, PASSED = !FAILED} TestStatus;
00048
00049 /* Private define ------------------------------------------------------------*/
00050 /* Uncomment the following line to enable using LCD screen for messages display */
00051 #define ENABLE_LCD_MSG_DISPLAY
00052
00053 #define sEE_WRITE_ADDRESS1        0x50
00054 #define sEE_READ_ADDRESS1         0x50
00055 #define BUFFER_SIZE1             (countof(Tx1_Buffer)-1)
00056 #define BUFFER_SIZE2             (countof(Tx2_Buffer)-1)
00057 #define sEE_WRITE_ADDRESS2       (sEE_WRITE_ADDRESS1 + BUFFER_SIZE1)
00058 #define sEE_READ_ADDRESS2        (sEE_READ_ADDRESS1 + BUFFER_SIZE1)
00059
00060 /* Private macro -------------------------------------------------------------*/
00061 #define countof(a) (sizeof(a) / sizeof(*(a)))
00062
00063 /* Private variables ---------------------------------------------------------*/
00064 uint8_t Tx1_Buffer[] = "/* STM32F10xx I2C Firmware Library EEPROM driver example: \
00065                         buffer 1 transfer into address sEE_WRITE_ADDRESS1 */ \
00066                         Example Description \
00067                         This firmware provides a basic example of how to use the I2C firmware library and\
00068                         an associate I2C EEPROM driver to communicate with an I2C EEPROM device (here the\
00069                         example is interfacing with M24C64 EEPROM)\
00070                           \
00071                         I2C peripheral is configured in Master transmitter during write operation and in\
00072                         Master receiver during read operation from I2C EEPROM. \
00073                           \
00074                         The peripheral used is I2C1 but can be configured by modifying the defines values\
00075                         in stm32xxxx_eval.h file. The speed is set to 200kHz and can be configured by \
00076                         modifying the relative define in stm32_eval_i2c_ee.h file.\
00077                          \
00078                         For M24C64 devices all the memory is accessible through the two-bytes \
00079                         addressing mode and need to define block addresses. In this case, only the physical \
00080                         address has to be defined (according to the address pins (E0,E1 and E2) connection).\
00081                         This address is defined in i2c_ee.h (default is 0xA0: E0, E1 and E2 tied to ground).\
00082                         The EEPROM addresses where the program start the write and the read operations \
00083                         is defined in the main.c file. \
00084                          \
00085                         First, the content of Tx1_Buffer is written to the EEPROM_WriteAddress1 and the\
00086                         written data are read. The written and the read buffers data are then compared.\
00087                         Following the read operation, the program waits that the EEPROM reverts to its \
00088                         Standby state. A second write operation is, then, performed and this time, Tx2_Buffer\
00089                         is written to EEPROM_WriteAddress2, which represents the address just after the last \
00090                         written one in the first write. After completion of the second write operation, the \
00091                         written data are read. The contents of the written and the read buffers are compared.\
00092                          \
00093                         All transfers are managed in DMA mode (except when 1-byte read/write operation is\
00094                         required). Once sEE_ReadBuffer() or sEE_WriteBuffer() function is called, the \
00095                         use application may perform other tasks in parallel while Read/Write operation is\
00096                         managed by DMA.\
00097                           \
00098                         This example provides the possibility to use the STM32XXXX-EVAL LCD screen for\
00099                         messages display (transfer status: Ongoing, PASSED, FAILED).\
00100                         To enable this option uncomment the define ENABLE_LCD_MSG_DISPLAY in the main.c\
00101                         file.                                                                              ";
00102 uint8_t Tx2_Buffer[] = "/* STM32F10xx I2C Firmware Library EEPROM driver example: \
00103                         buffer 2 transfer into address sEE_WRITE_ADDRESS2 */";
00104 uint8_t Rx1_Buffer[BUFFER_SIZE1], Rx2_Buffer[BUFFER_SIZE2];
00105 volatile TestStatus TransferStatus1 = FAILED, TransferStatus2 = FAILED;
00106 volatile uint16_t NumDataRead = 0;
00107
00108 /* Private functions ---------------------------------------------------------*/
00109 TestStatus Buffercmp(uint8_t* pBuffer1, uint8_t* pBuffer2, uint16_t BufferLength);
00110
00111 /**
00112   * @brief  Main program
00113   * @param  None
00114   * @retval None
00115   */
00116 int main(void)
00117 {
00118   /*!< At this stage the microcontroller clock setting is already configured,
00119        this is done through SystemInit() function which is called from startup
00120        file (startup_stm32f10x_xx.s) before to branch to application main.
00121        To reconfigure the default setting of SystemInit() function, refer to
00122        system_stm32f10x.c file
00123      */
00124
00125 #ifdef ENABLE_LCD_MSG_DISPLAY
00126   /* Initialize the LCD screen for information display */
00127  #ifdef USE_STM3210E_EVAL
00128   STM3210E_LCD_Init();
00129  #elif defined(USE_STM3210B_EVAL)
00130   STM3210B_LCD_Init();
00131  #elif defined(USE_STM3210C_EVAL)
00132   STM3210C_LCD_Init();
00133  #elif defined(USE_STM32100B_EVAL)
00134   STM32100B_LCD_Init();
00135  #elif defined(USE_STM32100E_EVAL)
00136   STM32100E_LCD_Init();
00137  #endif /* USE_STM3210E_EVAL */
00138
00139   /* Display application information */
00140   LCD_Clear(LCD_COLOR_BLUE);
00141   LCD_SetBackColor(LCD_COLOR_BLUE);
00142   LCD_SetTextColor(LCD_COLOR_WHITE);
00143   LCD_DisplayStringLine(LCD_LINE_0, "SMT32F1xx FW Library");
00144   LCD_DisplayStringLine(LCD_LINE_1, "   EEPROM Example   ");
00145 #endif /* ENABLE_LCD_MSG_DISPLAY */
00146
00147   /* Initialize the I2C EEPROM driver ----------------------------------------*/
00148   sEE_Init();
00149
00150   /* First write in the memory followed by a read of the written data --------*/
00151   /* Write on I2C EEPROM from sEE_WRITE_ADDRESS1 */
00152   sEE_WriteBuffer(Tx1_Buffer, sEE_WRITE_ADDRESS1, BUFFER_SIZE1);
00153
00154   /* Set the Number of data to be read */
00155   NumDataRead = BUFFER_SIZE1;
00156
00157   /* Read from I2C EEPROM from sEE_READ_ADDRESS1 */
00158   sEE_ReadBuffer(Rx1_Buffer, sEE_READ_ADDRESS1, (uint16_t *)(&NumDataRead));
00159
00160 #ifdef ENABLE_LCD_MSG_DISPLAY
00161   LCD_DisplayStringLine(LCD_LINE_3, " Transfer 1 Ongoing ");
00162 #endif /* ENABLE_LCD_MSG_DISPLAY */
00163
00164   /* Wait till DMA transfer is complete (Transfer complete interrupt handler
00165     resets the variable holding the number of data to be read) */
00166   while (NumDataRead > 0)
00167   {
00168     /* Starting from this point, if the requested number of data is higher than 1,
00169        then only the DMA is managing the data transfer. Meanwhile, CPU is free to
00170        perform other tasks:
00171
00172       // Add your code here:
00173       //...
00174       //...
00175
00176        For simplicity reasons, this example is just waiting till the end of the
00177        transfer. */
00178   }
00179
00180   /* Check if the data written to the memory is read correctly */
00181   TransferStatus1 = Buffercmp(Tx1_Buffer, Rx1_Buffer, BUFFER_SIZE1);
00182   /* TransferStatus1 = PASSED, if the transmitted and received data
00183      to/from the EEPROM are the same */
00184   /* TransferStatus1 = FAILED, if the transmitted and received data
00185      to/from the EEPROM are different */
00186 #ifdef ENABLE_LCD_MSG_DISPLAY
00187   if (TransferStatus1 == PASSED)
00188   {
00189     LCD_DisplayStringLine(LCD_LINE_3, " Transfer 1 PASSED  ");
00190   }
00191   else
00192   {
00193     LCD_DisplayStringLine(LCD_LINE_3, " Transfer 1 FAILED  ");
00194   }
00195 #endif /* ENABLE_LCD_MSG_DISPLAY */
00196
00197 /*----------------------------------
00198
00199                                     ------------------------------------------*/
00200
00201   /* Second write in the memory followed by a read of the written data -------*/
00202   /* Write on I2C EEPROM from sEE_WRITE_ADDRESS2 */
00203   sEE_WriteBuffer(Tx2_Buffer, sEE_WRITE_ADDRESS2, BUFFER_SIZE2);
00204
00205   /* Set the Number of data to be read */
00206   NumDataRead = BUFFER_SIZE2;
00207
00208   /* Read from I2C EEPROM from sEE_READ_ADDRESS2 */
00209   sEE_ReadBuffer(Rx2_Buffer, sEE_READ_ADDRESS2, (uint16_t *)(&NumDataRead));
00210
00211 #ifdef ENABLE_LCD_MSG_DISPLAY
00212   LCD_DisplayStringLine(LCD_LINE_5, " Transfer 2 Ongoing ");
00213 #endif /* ENABLE_LCD_MSG_DISPLAY */
00214
00215   /* Wait till DMA transfer is complete (Transfer complete interrupt handler
00216     resets the variable holding the number of data to be read) */
00217   while (NumDataRead > 0)
00218   {
00219     /* Starting from this point, if the requested number of data is higher than 1,
00220        then only the DMA is managing the data transfer. Meanwhile, CPU is free to
00221        perform other tasks:
00222
00223       // Add your code here:
00224       //...
00225       //...
00226
00227        For simplicity reasons, this example is just waiting till the end of the
00228        transfer. */
00229   }
00230
00231   /* Check if the data written to the memory is read correctly */
00232   TransferStatus2 = Buffercmp(Tx2_Buffer, Rx2_Buffer, BUFFER_SIZE2);
00233   /* TransferStatus2 = PASSED, if the transmitted and received data
00234      to/from the EEPROM are the same */
00235   /* TransferStatus2 = FAILED, if the transmitted and received data
00236      to/from the EEPROM are different */
00237 #ifdef ENABLE_LCD_MSG_DISPLAY
00238   if (TransferStatus1 == PASSED)
00239   {
00240     LCD_DisplayStringLine(LCD_LINE_5, " Transfer 2 PASSED  ");
00241   }
00242   else
00243   {
00244     LCD_DisplayStringLine(LCD_LINE_5, " Transfer 2 FAILED  ");
00245   }
00246 #endif /* ENABLE_LCD_MSG_DISPLAY */
00247
00248   /* Free all used resources */
00249   sEE_DeInit();
00250
00251 #ifdef ENABLE_LCD_MSG_DISPLAY
00252   /* Display end of example information */
00253   LCD_DisplayStringLine(LCD_LINE_7, "---End Of Example---");
00254 #endif /* ENABLE_LCD_MSG_DISPLAY */
00255
00256   while (1)
00257   {
00258   }
00259 }
00260
00261 #ifndef USE_DEFAULT_TIMEOUT_CALLBACK
00262 /**
00263   * @brief  Example of timeout situation management.
00264   * @param  None.
00265   * @retval None.
00266   */
00267 uint32_t sEE_TIMEOUT_UserCallback(void)
00268 {
00269   /* Use application may try to recover the communication by resetting I2C
00270     peripheral (calling the function I2C_SoftwareResetCmd()) then re-start
00271     the transmission/reception from a previously stored recover point.
00272     For simplicity reasons, this example only shows a basic way for errors
00273     managements which consists of stopping all the process and requiring system
00274     reset. */
00275
00276 #ifdef ENABLE_LCD_MSG_DISPLAY
00277   /* Display error message on screen */
00278   LCD_Clear(LCD_COLOR_RED);
00279   LCD_DisplayStringLine(LCD_LINE_4, "Communication ERROR!");
00280   LCD_DisplayStringLine(LCD_LINE_5, "Try again after res-");
00281   LCD_DisplayStringLine(LCD_LINE_6, "  etting the Board  ");
00282 #endif /* ENABLE_LCD_MSG_DISPLAY */
00283
00284   /* Block communication and all processes */
00285   while (1)
00286   {
00287   }
00288 }
00289
00290 #endif /* USE_DEFAULT_TIMEOUT_CALLBACK */
00291
00292 /**
00293   * @brief  Compares two buffers.
00294   * @param  pBuffer1, pBuffer2: buffers to be compared.
00295   * @param  BufferLength: buffer's length
00296   * @retval PASSED: pBuffer1 identical to pBuffer2
00297   *         FAILED: pBuffer1 differs from pBuffer2
00298   */
00299 TestStatus Buffercmp(uint8_t* pBuffer1, uint8_t* pBuffer2, uint16_t BufferLength)
00300 {
00301   while(BufferLength--)
00302   {
00303     if(*pBuffer1 != *pBuffer2)
00304     {
00305       return FAILED;
00306     }
00307
00308     pBuffer1++;
00309     pBuffer2++;
00310   }
00311
00312   return PASSED;
00313 }
00314
00315 #ifdef  USE_FULL_ASSERT
00316
00317 /**
00318   * @brief  Reports the name of the source file and the source line number
00319   *         where the assert_param error has occurred.
00320   * @param  file: pointer to the source file name
00321   * @param  line: assert_param error line source number
00322   * @retval None
00323   */
00324 void assert_failed(uint8_t* file, uint32_t line)
00325 {
00326   /* User can add his own implementation to report the file name and line number,
00327      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00328
00329   /* Infinite loop */
00330   while (1)
00331   {
00332   }
00333 }
00334
00335 #endif
00336
00337 /**
00338   * @}
00339   */
00340
00341 /**
00342   * @}
00343   */
00344
00345 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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STM32F10x_StdPeriph_Examples/I2C/EEPROM/stm32f10x_conf.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    I2C/EEPROM/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052 /* Exported types ------------------------------------------------------------*/
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Uncomment the line below to expanse the "assert_param" macro in the
00055    Standard Peripheral Library drivers code */
00056 #define USE_FULL_ASSERT    1 */
00057
00058 /* Exported macro ------------------------------------------------------------*/
00059 #ifdef  USE_FULL_ASSERT
00060
00061 /**
00062   * @brief  The assert_param macro is used for function's parameters check.
00063   * @param  expr: If expr is false, it calls assert_failed function which reports
00064   *         the name of the source file and the source line number of the call
00065   *         that failed. If expr is true, it returns no value.
00066   * @retval None
00067   */
00068   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00069 /* Exported functions ------------------------------------------------------- */
00070   void assert_failed(uint8_t* file, uint32_t line);
00071 #else
00072   #define assert_param(expr) ((void)0)
00073 #endif /* USE_FULL_ASSERT */
00074
00075 #endif /* __STM32F10x_CONF_H */
00076
00077 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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STM32F10x_StdPeriph_Examples/I2C/EEPROM/stm32f10x_it.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    I2C/EEPROM/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and
00009   *          peripherals interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026
00027 /** @addtogroup STM32F10x_StdPeriph_Examples
00028   * @{
00029   */
00030
00031 /** @addtogroup I2C_EEPROM
00032   * @{
00033   */
00034
00035 /* Private typedef -----------------------------------------------------------*/
00036 /* Private define ------------------------------------------------------------*/
00037 /* Private macro -------------------------------------------------------------*/
00038 /* Private variables ---------------------------------------------------------*/
00039 /* Private function prototypes -----------------------------------------------*/
00040 /* Private functions ---------------------------------------------------------*/
00041
00042 /******************************************************************************/
00043 /*            Cortex-M3 Processor Exceptions Handlers                         */
00044 /******************************************************************************/
00045
00046 /**
00047   * @brief  This function handles NMI exception.
00048   * @param  None
00049   * @retval None
00050   */
00051 void NMI_Handler(void)
00052 {
00053 }
00054
00055 /**
00056   * @brief  This function handles Hard Fault exception.
00057   * @param  None
00058   * @retval None
00059   */
00060 void HardFault_Handler(void)
00061 {
00062   /* Go to infinite loop when Hard Fault exception occurs */
00063   while (1)
00064   {
00065   }
00066 }
00067
00068 /**
00069   * @brief  This function handles Memory Manage exception.
00070   * @param  None
00071   * @retval None
00072   */
00073 void MemManage_Handler(void)
00074 {
00075   /* Go to infinite loop when Memory Manage exception occurs */
00076   while (1)
00077   {
00078   }
00079 }
00080
00081 /**
00082   * @brief  This function handles Bus Fault exception.
00083   * @param  None
00084   * @retval None
00085   */
00086 void BusFault_Handler(void)
00087 {
00088   /* Go to infinite loop when Bus Fault exception occurs */
00089   while (1)
00090   {
00091   }
00092 }
00093
00094 /**
00095   * @brief  This function handles Usage Fault exception.
00096   * @param  None
00097   * @retval None
00098   */
00099 void UsageFault_Handler(void)
00100 {
00101   /* Go to infinite loop when Usage Fault exception occurs */
00102   while (1)
00103   {
00104   }
00105 }
00106
00107 /**
00108   * @brief  This function handles SVCall exception.
00109   * @param  None
00110   * @retval None
00111   */
00112 void SVC_Handler(void)
00113 {
00114 }
00115
00116 /**
00117   * @brief  This function handles Debug Monitor exception.
00118   * @param  None
00119   * @retval None
00120   */
00121 void DebugMon_Handler(void)
00122 {
00123 }
00124
00125 /**
00126   * @brief  This function handles PendSV_Handler exception.
00127   * @param  None
00128   * @retval None
00129   */
00130 void PendSV_Handler(void)
00131 {
00132 }
00133
00134 /**
00135   * @brief  This function handles SysTick Handler.
00136   * @param  None
00137   * @retval None
00138   */
00139 void SysTick_Handler(void)
00140 {
00141 }
00142
00143 /******************************************************************************/
00144 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00145 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00146 /*  available peripheral interrupt handler's name please refer to the startup */
00147 /*  file (startup_stm32f10x_xx.s).                                            */
00148 /******************************************************************************/
00149
00150 /**
00151   * @brief  This function handles PPP interrupt request.
00152   * @param  None
00153   * @retval None
00154   */
00155 /*void PPP_IRQHandler(void)
00156 {
00157 }*/
00158
00159 /**
00160   * @}
00161   */
00162
00163 /**
00164   * @}
00165   */
00166
00167 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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STM32F10x_StdPeriph_Examples/I2C/EEPROM/stm32f10x_it.h

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00001 /**
00002   ******************************************************************************
00003   * @file    I2C/EEPROM/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043
00044 #endif /* __STM32F10x_IT_H */
00045
00046 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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  • I2C_TSENSOR

STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/main.c

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00001 /**
00002   ******************************************************************************
00003   * @file    I2C/I2C_TSENSOR/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x.h"
00024 #include <stdlib.h>
00025 #include "stm32_eval_i2c_tsensor.h"
00026 #include "stm32_eval.h"
00027
00028 #ifdef USE_STM32100E_EVAL
00029   #include "stm32100e_eval_lcd.h"
00030 #elif defined USE_STM3210E_EVAL
00031   #include "stm3210e_eval_lcd.h"
00032 #elif defined USE_STM32100B_EVAL
00033   #include "stm32100b_eval_lcd.h"
00034 #elif defined USE_STM3210B_EVAL
00035   #include "stm3210b_eval_lcd.h"
00036 #endif
00037
00038 /** @addtogroup STM32F10x_StdPeriph_Examples
00039   * @{
00040   */
00041
00042 /** @addtogroup I2C_TSENSOR
00043   * @{
00044   */
00045
00046 /* Private typedef -----------------------------------------------------------*/
00047 typedef enum {FAILED = 0, PASSED = !FAILED} TestStatus;
00048
00049 /* Private define ------------------------------------------------------------*/
00050 #define TEMPERATURE_THYS    31
00051 #define TEMPERATURE_TOS     32
00052
00053 /* Private macro -------------------------------------------------------------*/
00054 /* Private variables ---------------------------------------------------------*/
00055 static uint8_t TempCelsiusDisplay[]     = "       +abc.d C     ";
00056 static uint8_t TempFahrenheitDisplay[]  = "       +abc.d F     ";
00057 static int32_t TempValue = 0, TempValueCelsius = 0, TempValueFahrenheit = 0;
00058 __IO uint8_t SMbusAlertOccurred = 0;
00059 uint32_t index = 0;
00060
00061 /* Private functions ---------------------------------------------------------*/
00062 void NVIC_Configuration(void);
00063
00064 /**
00065   * @brief   Main program
00066   * @param  None
00067   * @retval None
00068   */
00069 int main(void)
00070 {
00071   /*!< At this stage the microcontroller clock setting is already configured,
00072        this is done through SystemInit() function which is called from startup
00073        file (startup_stm32f10x_xx.s) before to branch to application main.
00074        To reconfigure the default setting of SystemInit() function, refer to
00075        system_stm32f10x.c file
00076      */
00077
00078   /* NVIC Configuration */
00079   NVIC_Configuration();
00080
00081   /* Initialize the LCD */
00082 #ifdef USE_STM32100E_EVAL
00083   STM32100E_LCD_Init();
00084 #elif defined USE_STM3210E_EVAL
00085   STM3210E_LCD_Init();
00086 #elif defined USE_STM32100B_EVAL
00087   STM32100B_LCD_Init();
00088 #elif defined USE_STM3210B_EVAL
00089   STM3210B_LCD_Init();
00090 #endif
00091
00092
00093 #ifdef USE_STM3210E_EVAL
00094   /* Disable FSMC only for STM32 High-density and XL-density devices */
00095   RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, DISABLE);
00096 #endif /* USE_STM3210E_EVAL */
00097
00098   /* Initialize the Temperature Sensor */
00099   LM75_Init();
00100
00101   if (LM75_GetStatus() == SUCCESS)
00102   {
00103 #ifdef USE_STM3210E_EVAL
00104     /* Enable FSMC */
00105     RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, ENABLE);
00106 #endif /* USE_STM3210E_EVAL */
00107
00108     /* Clear the LCD */
00109     LCD_Clear(LCD_COLOR_WHITE);
00110
00111     /* Set the Back Color */
00112     LCD_SetBackColor(LCD_COLOR_BLUE);
00113
00114     /* Set the Text Color */
00115     LCD_SetTextColor(LCD_COLOR_GREEN);
00116
00117     LCD_DisplayStringLine(LCD_LINE_0, "     Temperature    ");
00118
00119 #ifdef USE_STM3210E_EVAL
00120     /* Disable FSMC */
00121     RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, DISABLE);
00122
00123     /* Initialize the Temperature Sensor */
00124     LM75_Init();
00125
00126 #endif /* USE_STM3210E_EVAL */
00127
00128     /* Configure the Temperature sensor device STLM75:
00129     - Thermostat mode Interrupt
00130     - Fault tolerance: 00
00131     */
00132     LM75_WriteConfReg(0x02);
00133
00134     /* Configure the THYS and TOS in order to use the SMbus alert interrupt */
00135     LM75_WriteReg(LM75_REG_THYS, TEMPERATURE_THYS << 8);  /*31ÝC*/
00136     LM75_WriteReg(LM75_REG_TOS, TEMPERATURE_TOS << 8);   /*32ÝC*/
00137
00138     I2C_ClearITPendingBit(LM75_I2C, I2C_IT_SMBALERT);
00139
00140     SMbusAlertOccurred = 0;
00141
00142     /* Infinite Loop */
00143     while (1)
00144     {
00145 #ifdef USE_STM3210E_EVAL
00146     /* Disable FSMC */
00147     RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, DISABLE);
00148
00149     /* Initialize the Temperature Sensor */
00150     LM75_Init();
00151 #endif /* USE_STM3210E_EVAL */
00152
00153       /* Get double of Temperature value */
00154       TempValue = LM75_ReadTemp();
00155
00156 #ifdef USE_STM3210E_EVAL
00157       /* Enable FSMC */
00158       RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, ENABLE);
00159 #endif /* USE_STM3210E_EVAL */
00160
00161       if (TempValue <= 256)
00162       {
00163         /* Positive temperature measured */
00164         TempCelsiusDisplay[7] = '+';
00165
00166         /* Initialize the temperature sensor value*/
00167         TempValueCelsius = TempValue;
00168       }
00169       else
00170       {
00171         /* Negative temperature measured */
00172         TempCelsiusDisplay[7] = '-';
00173         /* Remove temperature value sign */
00174         TempValueCelsius = 0x200 - TempValue;
00175       }
00176
00177       /* Calculate temperature digits in ÝC */
00178       if ((TempValueCelsius & 0x01) == 0x01)
00179       {
00180         TempCelsiusDisplay[12] = 0x05 + 0x30;
00181         TempFahrenheitDisplay[12] = 0x05 + 0x30;
00182       }
00183       else
00184       {
00185         TempCelsiusDisplay[12] = 0x00 + 0x30;
00186         TempFahrenheitDisplay[12] = 0x00 + 0x30;
00187       }
00188
00189       TempValueCelsius >>= 1;
00190
00191       TempCelsiusDisplay[8] = (TempValueCelsius / 100) + 0x30;
00192       TempCelsiusDisplay[9] = ((TempValueCelsius % 100) / 10) + 0x30;
00193       TempCelsiusDisplay[10] = ((TempValueCelsius % 100) % 10) + 0x30;
00194
00195       if (TempValue > 256)
00196       {
00197         if (((9 * TempValueCelsius) / 5) <= 32)
00198         {
00199           /* Convert temperature ÝC to Fahrenheit */
00200           TempValueFahrenheit = abs (32 - ((9 * TempValueCelsius) / 5));
00201
00202           /* Calculate temperature digits in ÝF */
00203           TempFahrenheitDisplay[8] = (TempValueFahrenheit / 100) + 0x30;
00204           TempFahrenheitDisplay[9] = ((TempValueFahrenheit % 100) / 10) + 0x30;
00205           TempFahrenheitDisplay[10] = ((TempValueFahrenheit % 100) % 10) + 0x30;
00206           /* Positive temperature measured */
00207           TempFahrenheitDisplay[7] = '+';
00208         }
00209         else
00210         {
00211           /* Convert temperature ÝC to Fahrenheit */
00212           TempValueFahrenheit = abs(((9 * TempValueCelsius) / 5) - 32);
00213           /* Calculate temperature digits in ÝF */
00214           TempFahrenheitDisplay[8] = (TempValueFahrenheit / 100) + 0x30;
00215           TempFahrenheitDisplay[9] = ((TempValueFahrenheit % 100) / 10) + 0x30;
00216           TempFahrenheitDisplay[10] = ((TempValueFahrenheit % 100) % 10) + 0x30;
00217
00218           /* Negative temperature measured */
00219           TempFahrenheitDisplay[7] = '-';
00220         }
00221       }
00222       else
00223       {
00224         /* Convert temperature ÝC to Fahrenheit */
00225         TempValueFahrenheit = ((9 * TempValueCelsius) / 5) + 32;
00226
00227         /* Calculate temperature digits in ÝF */
00228         TempFahrenheitDisplay[8] = (TempValueFahrenheit / 100) + 0x30;
00229         TempFahrenheitDisplay[9] = ((TempValueFahrenheit % 100) / 10) + 0x30;
00230         TempFahrenheitDisplay[10] = ((TempValueFahrenheit % 100) % 10) + 0x30;
00231
00232         /* Positive temperature measured */
00233         TempFahrenheitDisplay[7] = '+';
00234       }
00235
00236       /* Display Fahrenheit value on LCD */
00237       for (index = 0; index < 20; index++)
00238       {
00239         LCD_DisplayChar(LCD_LINE_6, (319 - (16 * index)), TempCelsiusDisplay[index]);
00240
00241         LCD_DisplayChar(LCD_LINE_7, (319 - (16 * index)), TempFahrenheitDisplay[index]);
00242       }
00243
00244       if (SMbusAlertOccurred == 1)
00245       {
00246         /* Set the Back Color */
00247         LCD_SetBackColor(LCD_COLOR_BLUE);
00248         /* Set the Text Color */
00249         LCD_SetTextColor(LCD_COLOR_RED);
00250         LCD_DisplayStringLine(LCD_LINE_2, "Warning: Temp exceed");
00251         LCD_DisplayStringLine(LCD_LINE_3, "        32 C        ");
00252       }
00253       if (SMbusAlertOccurred == 2)
00254       {
00255         /* Set the Back Color */
00256         LCD_SetBackColor(LCD_COLOR_WHITE);
00257         /* Set the Text Color */
00258         LCD_SetTextColor(LCD_COLOR_WHITE);
00259         LCD_ClearLine(LCD_LINE_2);
00260         LCD_ClearLine(LCD_LINE_3);
00261         SMbusAlertOccurred = 0;
00262         /* Set the Back Color */
00263         LCD_SetBackColor(LCD_COLOR_BLUE);
00264         /* Set the Text Color */
00265         LCD_SetTextColor(LCD_COLOR_GREEN);
00266       }
00267     }
00268   }
00269   else
00270   {
00271     LCD_Clear(LCD_COLOR_WHITE);
00272     LCD_DisplayStringLine(LCD_LINE_2, " LM75 not correctly ");
00273     LCD_DisplayStringLine(LCD_LINE_3, " initialized...     ");
00274     LCD_DisplayStringLine(LCD_LINE_4, " Please restart the ");
00275     LCD_DisplayStringLine(LCD_LINE_5, " example.           ");
00276     /* Infinite Loop */
00277     while(1)
00278     {
00279     }
00280   }
00281 }
00282
00283 /**
00284   * @brief  Configures the different interrupt.
00285   * @param  None
00286   * @retval None
00287   */
00288 void NVIC_Configuration(void)
00289 {
00290   NVIC_InitTypeDef NVIC_InitStructure;
00291
00292   /* Re-configure and enable I2C2 error interrupt to have the higher priority */
00293 #ifdef USE_STM32100E_EVAL
00294   NVIC_InitStructure.NVIC_IRQChannel = I2C2_ER_IRQn;
00295 #else
00296   NVIC_InitStructure.NVIC_IRQChannel = I2C1_ER_IRQn;
00297 #endif
00298   NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
00299   NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
00300   NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
00301   NVIC_Init(&NVIC_InitStructure);
00302 }
00303
00304 #ifdef  USE_FULL_ASSERT
00305
00306 /**
00307   * @brief  Reports the name of the source file and the source line number
00308   *         where the assert_param error has occurred.
00309   * @param  file: pointer to the source file name
00310   * @param  line: assert_param error line source number
00311   * @retval None
00312   */
00313 void assert_failed(uint8_t* file, uint32_t line)
00314 {
00315   /* User can add his own implementation to report the file name and line number,
00316      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00317
00318   /* Infinite loop */
00319   while (1)
00320   {
00321   }
00322 }
00323
00324 #endif
00325
00326 /**
00327   * @}
00328   */
00329
00330 /**
00331   * @}
00332   */
00333
00334 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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  • I2C
  • I2C_TSENSOR

STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/stm32f10x_conf.h

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00001 /**
00002   ******************************************************************************
00003   * @file    I2C/I2C_TSENSOR/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052 /* Exported types ------------------------------------------------------------*/
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Uncomment the line below to expanse the "assert_param" macro in the
00055    Standard Peripheral Library drivers code */
00056 /* #define USE_FULL_ASSERT    1 */
00057
00058 /* Exported macro ------------------------------------------------------------*/
00059 #ifdef  USE_FULL_ASSERT
00060
00061 /**
00062   * @brief  The assert_param macro is used for function's parameters check.
00063   * @param  expr: If expr is false, it calls assert_failed function which reports
00064   *         the name of the source file and the source line number of the call
00065   *         that failed. If expr is true, it returns no value.
00066   * @retval None
00067   */
00068   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00069 /* Exported functions ------------------------------------------------------- */
00070   void assert_failed(uint8_t* file, uint32_t line);
00071 #else
00072   #define assert_param(expr) ((void)0)
00073 #endif /* USE_FULL_ASSERT */
00074
00075 #endif /* __STM32F10x_CONF_H */
00076
00077 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/stm32f10x_it.c

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00001 /**
00002   ******************************************************************************
00003   * @file    I2C/I2C_TSENSOR/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and peripherals
00009   *          interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026 #include "stm32_eval_i2c_tsensor.h"
00027
00028 /** @addtogroup STM32F10x_StdPeriph_Examples
00029   * @{
00030   */
00031
00032 /** @addtogroup I2C_TSENSOR
00033   * @{
00034   */
00035
00036 /* Private typedef -----------------------------------------------------------*/
00037 /* Private define ------------------------------------------------------------*/
00038 /* Private macro -------------------------------------------------------------*/
00039 /* Private variables ---------------------------------------------------------*/
00040 extern __IO uint8_t SMbusAlertOccurred;
00041
00042 /* Private function prototypes -----------------------------------------------*/
00043 /* Private functions ---------------------------------------------------------*/
00044
00045 /******************************************************************************/
00046 /*            Cortex-M3 Processor Exceptions Handlers                         */
00047 /******************************************************************************/
00048
00049 /**
00050   * @brief  This function handles NMI exception.
00051   * @param  None
00052   * @retval None
00053   */
00054 void NMI_Handler(void)
00055 {
00056 }
00057
00058 /**
00059   * @brief  This function handles Hard Fault exception.
00060   * @param  None
00061   * @retval None
00062   */
00063 void HardFault_Handler(void)
00064 {
00065   /* Go to infinite loop when Hard Fault exception occurs */
00066   while (1)
00067   {
00068   }
00069 }
00070
00071 /**
00072   * @brief  This function handles Memory Manage exception.
00073   * @param  None
00074   * @retval None
00075   */
00076 void MemManage_Handler(void)
00077 {
00078   /* Go to infinite loop when Memory Manage exception occurs */
00079   while (1)
00080   {
00081   }
00082 }
00083
00084 /**
00085   * @brief  This function handles Bus Fault exception.
00086   * @param  None
00087   * @retval None
00088   */
00089 void BusFault_Handler(void)
00090 {
00091   /* Go to infinite loop when Bus Fault exception occurs */
00092   while (1)
00093   {
00094   }
00095 }
00096
00097 /**
00098   * @brief  This function handles Usage Fault exception.
00099   * @param  None
00100   * @retval None
00101   */
00102 void UsageFault_Handler(void)
00103 {
00104   /* Go to infinite loop when Usage Fault exception occurs */
00105   while (1)
00106   {
00107   }
00108 }
00109
00110 /**
00111   * @brief  This function handles SVCall exception.
00112   * @param  None
00113   * @retval None
00114   */
00115 void SVC_Handler(void)
00116 {
00117 }
00118
00119 /**
00120   * @brief  This function handles Debug Monitor exception.
00121   * @param  None
00122   * @retval None
00123   */
00124 void DebugMon_Handler(void)
00125 {
00126 }
00127
00128 /**
00129   * @brief  This function handles PendSV_Handler exception.
00130   * @param  None
00131   * @retval None
00132   */
00133 void PendSV_Handler(void)
00134 {
00135 }
00136
00137 /**
00138   * @brief  This function handles SysTick Handler.
00139   * @param  None
00140   * @retval None
00141   */
00142 void SysTick_Handler(void)
00143 {
00144 }
00145
00146 /******************************************************************************/
00147 /*            STM32F10x Peripherals Interrupt Handlers                        */
00148 /******************************************************************************/
00149 /**
00150   * @brief  This function handles I2C2 Error interrupt request.
00151   * @param  None
00152   * @retval None
00153   */
00154 #ifdef USE_STM32100E_EVAL
00155 void I2C2_ER_IRQHandler(void)
00156 #else
00157 void I2C1_ER_IRQHandler(void)
00158 #endif /* STM32100E-EVAL */
00159 {
00160   /* Check on I2C2 SMBALERT flag and clear it */
00161   if (I2C_GetITStatus(LM75_I2C, I2C_IT_SMBALERT))
00162   {
00163     I2C_ClearITPendingBit(LM75_I2C, I2C_IT_SMBALERT);
00164     SMbusAlertOccurred++;
00165   }
00166   /* Check on I2C2 Time out flag and clear it */
00167   if (I2C_GetITStatus(LM75_I2C, I2C_IT_TIMEOUT))
00168   {
00169     I2C_ClearITPendingBit(LM75_I2C, I2C_IT_TIMEOUT);
00170   }
00171   /* Check on I2C2 Arbitration Lost flag and clear it */
00172   if (I2C_GetITStatus(LM75_I2C, I2C_IT_ARLO))
00173   {
00174     I2C_ClearITPendingBit(LM75_I2C, I2C_IT_ARLO);
00175   }
00176
00177   /* Check on I2C2 PEC error flag and clear it */
00178   if (I2C_GetITStatus(LM75_I2C, I2C_IT_PECERR))
00179   {
00180     I2C_ClearITPendingBit(LM75_I2C, I2C_IT_PECERR);
00181   }
00182   /* Check on I2C2 Overrun/Underrun error flag and clear it */
00183   if (I2C_GetITStatus(LM75_I2C, I2C_IT_OVR))
00184   {
00185     I2C_ClearITPendingBit(LM75_I2C, I2C_IT_OVR);
00186   }
00187   /* Check on I2C2 Acknowledge failure error flag and clear it */
00188   if (I2C_GetITStatus(LM75_I2C, I2C_IT_AF))
00189   {
00190     I2C_ClearITPendingBit(LM75_I2C, I2C_IT_AF);
00191   }
00192   /* Check on I2C2 Bus error flag and clear it */
00193   if (I2C_GetITStatus(LM75_I2C, I2C_IT_BERR))
00194   {
00195     I2C_ClearITPendingBit(LM75_I2C, I2C_IT_BERR);
00196   }
00197 }
00198
00199 /******************************************************************************/
00200 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00201 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00202 /*  available peripheral interrupt handler's name please refer to the startup */
00203 /*  file (startup_stm32f10x_xx.s).                                            */
00204 /******************************************************************************/
00205
00206 /**
00207   * @brief  This function handles PPP interrupt request.
00208   * @param  None
00209   * @retval None
00210   */
00211 /*void PPP_IRQHandler(void)
00212 {
00213 }*/
00214
00215 /**
00216   * @}
00217   */
00218
00219 /**
00220   * @}
00221   */
00222
00223 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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  • I2C
  • I2C_TSENSOR

STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/stm32f10x_it.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    I2C/I2C_TSENSOR/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043
00044 #endif /* __STM32F10x_IT_H */
00045
00046 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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STM32F10x_StdPeriph_Examples/I2C/IOExpander/main.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    I2C/IOExpander/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "main.h"
00024
00025 /** @addtogroup STM32F10x_StdPeriph_Examples
00026   * @{
00027   */
00028
00029 /** @addtogroup I2C_IOExpander
00030   * @{
00031   */
00032
00033 /* Private typedef -----------------------------------------------------------*/
00034 /* Private define ------------------------------------------------------------*/
00035 #ifdef USE_STM3210C_EVAL
00036   #define MESSAGE1   "   STM3210C-EVAL    "
00037 #elif defined (USE_STM32100E_EVAL)
00038   #define MESSAGE1   "   STM32100E-EVAL   "
00039 #endif
00040
00041 #define MESSAGE2   "  Example on how to "
00042 #define MESSAGE3   " use the IO Expander"
00043
00044 /* Private macro -------------------------------------------------------------*/
00045 /* Private variables ---------------------------------------------------------*/
00046 /* Private function prototypes -----------------------------------------------*/
00047 /* Private functions ---------------------------------------------------------*/
00048
00049 /**
00050   * @brief  Main program.
00051   * @param  None
00052   * @retval None
00053   */
00054 int main(void)
00055 {
00056   /* Initialize LEDs and push-buttons mounted on STM3210X-EVAL board */
00057   STM_EVAL_LEDInit(LED1);
00058   STM_EVAL_LEDInit(LED2);
00059   STM_EVAL_LEDInit(LED3);
00060   STM_EVAL_LEDInit(LED4);
00061
00062    /* Initialize the LCD */
00063 #ifdef USE_STM3210C_EVAL
00064   STM3210C_LCD_Init();
00065 #elif defined (USE_STM32100E_EVAL)
00066   STM32100E_LCD_Init();
00067 #endif /* USE_STM3210C_EVAL */
00068
00069   /* Clear the LCD */
00070   LCD_Clear(White);
00071
00072   /* Set the LCD Back Color */
00073   LCD_SetBackColor(Blue);
00074
00075   /* Set the LCD Text Color */
00076   LCD_SetTextColor(White);
00077
00078   /* Display messages on the LCD */
00079   LCD_DisplayStringLine(Line0, MESSAGE1);
00080   LCD_DisplayStringLine(Line1, MESSAGE2);
00081   LCD_DisplayStringLine(Line2, MESSAGE3);
00082
00083   /* Configure the IO Expander */
00084   if (IOE_Config() == IOE_OK)
00085   {
00086     /* Display "IO Expander OK" on the LCD */
00087     LCD_DisplayStringLine(Line4, "   IO Expander OK   ");
00088   }
00089   else
00090   {
00091     LCD_DisplayStringLine(Line4, "IO Expander FAILED ");
00092     LCD_DisplayStringLine(Line5, " Please Reset the  ");
00093     LCD_DisplayStringLine(Line6, "   board and start ");
00094     LCD_DisplayStringLine(Line7, "    again          ");
00095     while(1);
00096   }
00097
00098   /* Draw a rectangle with the specifies parameters and Blue Color */
00099   LCD_SetTextColor(Blue);
00100   LCD_DrawRect(180, 310, 40, 60);
00101
00102   /* Draw a rectangle with the specifies parameters and Red Color */
00103   LCD_SetTextColor(Red);
00104   LCD_DrawRect(180, 230, 40, 60);
00105
00106   /* Draw a rectangle with the specifies parameters and Yellow Color */
00107   LCD_SetTextColor(Yellow);
00108   LCD_DrawRect(180, 150, 40, 60);
00109
00110   /* Draw a rectangle with the specifies parameters and Black Color */
00111   LCD_SetTextColor(Black);
00112   LCD_DrawRect(180, 70, 40, 60);
00113
00114
00115 #ifdef IOE_INTERRUPT_MODE
00116
00117  #ifdef  USE_STM32100E_EVAL
00118   /* Enable the Touch Screen interrupts */
00119   IOE_ITConfig(IOE_ITSRC_TSC);
00120
00121  #else
00122   /* Enable the Touch Screen and Joystick interrupts */
00123   IOE_ITConfig(IOE_ITSRC_JOYSTICK | IOE_ITSRC_TSC);
00124  #endif /* USE_STM32100E_EVAL */
00125
00126 #endif /* IOE_INTERRUPT_MODE */
00127
00128   /* Loop infinitely */
00129   while(1)
00130   {
00131 #ifdef IOE_POLLING_MODE
00132  static TS_STATE* TS_State;
00133
00134  #ifdef  USE_STM3210C_EVAL
00135
00136     static JOY_State_TypeDef JoyState = JOY_NONE;
00137
00138     /* Get the Joytick State */
00139     JoyState = IOE_JoyStickGetState();
00140
00141     switch (JoyState)
00142     {
00143         /* None Joystick has been selected */
00144     case JOY_NONE:
00145       LCD_DisplayStringLine(Line5, "JOY:     ----       ");
00146       break;
00147     case JOY_UP:
00148       LCD_DisplayStringLine(Line5, "JOY:     UP         ");
00149       break;
00150     case JOY_DOWN:
00151       LCD_DisplayStringLine(Line5, "JOY:    DOWN        ");
00152       break;
00153     case JOY_LEFT:
00154       LCD_DisplayStringLine(Line5, "JOY:    LEFT        ");
00155       break;
00156     case JOY_RIGHT:
00157       LCD_DisplayStringLine(Line5, "JOY:    RIGHT       ");
00158       break;
00159     case JOY_CENTER:
00160       LCD_DisplayStringLine(Line5, "JOY:    CENTER      ");
00161       break;
00162     default:
00163       LCD_DisplayStringLine(Line5, "JOY:    ERROR       ");
00164       break;
00165     }
00166  #endif /* USE_STM3210C_EVAL */
00167
00168
00169     /* Update the structure with the current position of the Touch screen */
00170     TS_State = IOE_TS_GetState();
00171
00172     if ((TS_State->TouchDetected) && (TS_State->Y < 220) && (TS_State->Y > 180))
00173     {
00174       if ((TS_State->X > 10) && (TS_State->X < 70))
00175       {
00176       /* Display LD4 on the LCD and turn on LED4 */
00177         LCD_DisplayStringLine(Line6, " LD4                ");
00178         STM_EVAL_LEDOn(LED4);
00179       }
00180       else if ((TS_State->X > 90) && (TS_State->X < 150))
00181       {
00182       /* Display LD3 on the LCD and turn on LED3 */
00183         LCD_DisplayStringLine(Line6, "      LD3           ");
00184         STM_EVAL_LEDOn(LED3);
00185       }
00186       else if ((TS_State->X > 170) && (TS_State->X < 230))
00187       {
00188       /* Display LD2 on the LCD and turn on LED2 */
00189         LCD_DisplayStringLine(Line6, "           LD2      ");
00190         STM_EVAL_LEDOn(LED2);
00191       }
00192       else if ((TS_State->X > 250) && (TS_State->X < 310))
00193       {
00194       /* Display LD1 on the LCD and turn on LED1 */
00195         LCD_DisplayStringLine(Line6, "                LD1 ");
00196         STM_EVAL_LEDOn(LED1);
00197       }
00198
00199     }
00200     else
00201     {
00202     /* Turn off LED1..4 */
00203       STM_EVAL_LEDOff(LED1);
00204       STM_EVAL_LEDOff(LED2);
00205       STM_EVAL_LEDOff(LED3);
00206       STM_EVAL_LEDOff(LED4);
00207     }
00208
00209 #endif /* IOE_POLLING_MODE */
00210   }
00211 }
00212
00213 #ifdef  USE_FULL_ASSERT
00214
00215 /**
00216   * @brief  Reports the name of the source file and the source line number
00217   *         where the assert_param error has occurred.
00218   * @param  file: pointer to the source file name
00219   * @param  line: assert_param error line source number
00220   * @retval None
00221   */
00222 void assert_failed(uint8_t* file, uint32_t line)
00223 {
00224   /* User can add his own implementation to report the file name and line number,
00225      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00226
00227    LCD_DisplayStringLine(Line0, "assert_param error!!");
00228
00229   /* Infinite loop */
00230   while (1)
00231   {
00232   }
00233 }
00234
00235 #endif
00236
00237 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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  • I2C
  • IOExpander

STM32F10x_StdPeriph_Examples/I2C/IOExpander/stm32f10x_conf.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    I2C/IOExpander/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052 /* Exported types ------------------------------------------------------------*/
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Uncomment the line below to expanse the "assert_param" macro in the
00055    Standard Peripheral Library drivers code */
00056 /* #define USE_FULL_ASSERT    1 */
00057
00058 /* Exported macro ------------------------------------------------------------*/
00059 #ifdef  USE_FULL_ASSERT
00060
00061 /**
00062   * @brief  The assert_param macro is used for function's parameters check.
00063   * @param  expr: If expr is false, it calls assert_failed function which reports
00064   *         the name of the source file and the source line number of the call
00065   *         that failed. If expr is true, it returns no value.
00066   * @retval None
00067   */
00068   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00069 /* Exported functions ------------------------------------------------------- */
00070   void assert_failed(uint8_t* file, uint32_t line);
00071 #else
00072   #define assert_param(expr) ((void)0)
00073 #endif /* USE_FULL_ASSERT */
00074
00075 #endif /* __STM32F10x_CONF_H */
00076
00077 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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STM32F10x_StdPeriph_Examples/I2C/IOExpander/stm32f10x_it.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    I2C/IOExpander/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and peripherals
00009   *          interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026 #include "main.h"
00027
00028 /** @addtogroup STM32F10x_StdPeriph_Examples
00029   * @{
00030   */
00031
00032 /** @addtogroup I2C_IOExpander
00033   * @{
00034   */
00035
00036 /* Private typedef -----------------------------------------------------------*/
00037 /* Private define ------------------------------------------------------------*/
00038 /* Private macro -------------------------------------------------------------*/
00039 /* Private variables ---------------------------------------------------------*/
00040 /* Private function prototypes -----------------------------------------------*/
00041 /* Private functions ---------------------------------------------------------*/
00042
00043 /******************************************************************************/
00044 /*            Cortex-M3 Processor Exceptions Handlers                         */
00045 /******************************************************************************/
00046
00047 /**
00048   * @brief  This function handles NMI exception.
00049   * @param  None
00050   * @retval None
00051   */
00052 void NMI_Handler(void)
00053 {
00054 }
00055
00056 /**
00057   * @brief  This function handles Hard Fault exception.
00058   * @param  None
00059   * @retval None
00060   */
00061 void HardFault_Handler(void)
00062 {
00063   /* Go to infinite loop when Hard Fault exception occurs */
00064   while (1)
00065   {
00066   }
00067 }
00068
00069 /**
00070   * @brief  This function handles Memory Manage exception.
00071   * @param  None
00072   * @retval None
00073   */
00074 void MemManage_Handler(void)
00075 {
00076   /* Go to infinite loop when Memory Manage exception occurs */
00077   while (1)
00078   {
00079   }
00080 }
00081
00082 /**
00083   * @brief  This function handles Bus Fault exception.
00084   * @param  None
00085   * @retval None
00086   */
00087 void BusFault_Handler(void)
00088 {
00089   /* Go to infinite loop when Bus Fault exception occurs */
00090   while (1)
00091   {
00092   }
00093 }
00094
00095 /**
00096   * @brief  This function handles Usage Fault exception.
00097   * @param  None
00098   * @retval None
00099   */
00100 void UsageFault_Handler(void)
00101 {
00102   /* Go to infinite loop when Usage Fault exception occurs */
00103   while (1)
00104   {
00105   }
00106 }
00107
00108 /**
00109   * @brief  This function handles SVCall exception.
00110   * @param  None
00111   * @retval None
00112   */
00113 void SVC_Handler(void)
00114 {
00115 }
00116
00117 /**
00118   * @brief  This function handles Debug Monitor exception.
00119   * @param  None
00120   * @retval None
00121   */
00122 void DebugMon_Handler(void)
00123 {
00124 }
00125
00126 /**
00127   * @brief  This function handles PendSVC exception.
00128   * @param  None
00129   * @retval None
00130   */
00131 void PendSV_Handler(void)
00132 {
00133 }
00134
00135
00136 /******************************************************************************/
00137 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00138 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00139 /*  available peripheral interrupt handler's name please refer to the startup */
00140 /*  file (startup_stm32f10x_xx.s).                                            */
00141 /******************************************************************************/
00142
00143 /**
00144   * @brief  This function handles External lines 15 to 10 interrupt request.
00145   * @param  None
00146   * @retval None
00147   */
00148 void EXTI15_10_IRQHandler(void)
00149 {
00150   /* Checks whether the IOE EXTI line is asserted or not */
00151   if(EXTI_GetITStatus(IOE_IT_EXTI_LINE) != RESET)
00152   {
00153
00154 #ifdef IOE_INTERRUPT_MODE
00155     /* Check if the interrupt source is the Touch Screen */
00156     if (IOE_GetGITStatus(IOE_1_ADDR, IOE_TS_IT) & IOE_TS_IT)
00157     {
00158       static TS_STATE* TS_State;
00159
00160       /* Update the structure with the current position */
00161       TS_State = IOE_TS_GetState();
00162
00163       if ((TS_State->TouchDetected) && (TS_State->Y < 220) && (TS_State->Y > 180))
00164       {
00165         if ((TS_State->X > 10) && (TS_State->X < 70))
00166         {
00167           LCD_DisplayStringLine(Line6, " LD4                ");
00168           STM_EVAL_LEDOn(LED4);
00169         }
00170         else if ((TS_State->X > 90) && (TS_State->X < 150))
00171         {
00172           LCD_DisplayStringLine(Line6, "      LD3           ");
00173           STM_EVAL_LEDOn(LED3);
00174         }
00175         else if ((TS_State->X > 170) && (TS_State->X < 230))
00176         {
00177           LCD_DisplayStringLine(Line6, "           LD2      ");
00178           STM_EVAL_LEDOn(LED2);
00179         }
00180         else if ((TS_State->X > 250) && (TS_State->X < 310))
00181         {
00182           LCD_DisplayStringLine(Line6, "                LD1 ");
00183           STM_EVAL_LEDOn(LED1);
00184         }
00185       }
00186       else
00187       {
00188         STM_EVAL_LEDOff(LED1);
00189         STM_EVAL_LEDOff(LED2);
00190         STM_EVAL_LEDOff(LED3);
00191         STM_EVAL_LEDOff(LED4);
00192       }
00193
00194       /* Clear the interrupt pending bits */
00195       IOE_ClearGITPending(IOE_1_ADDR, IOE_TS_IT);
00196     }
00197  #ifdef USE_STM3210C_EVAL
00198     else if (IOE_GetGITStatus(IOE_2_ADDR, IOE_GIT_GPIO))
00199     {
00200       static JOY_State_TypeDef JoyState = JOY_NONE;
00201
00202       /* Get the Joystick State */
00203       JoyState = IOE_JoyStickGetState();
00204
00205       switch (JoyState)
00206       {
00207       case JOY_NONE:
00208         LCD_DisplayStringLine(Line5, "JOY: IT  ----       ");
00209         break;
00210       case JOY_UP:
00211         LCD_DisplayStringLine(Line5, "JOY: IT  UP         ");
00212         break;
00213       case JOY_DOWN:
00214         LCD_DisplayStringLine(Line5, "JOY: IT DOWN        ");
00215         break;
00216       case JOY_LEFT:
00217         LCD_DisplayStringLine(Line5, "JOY: IT LEFT        ");
00218         break;
00219       case JOY_RIGHT:
00220         LCD_DisplayStringLine(Line5, "JOY: IT  RIGHT      ");
00221         break;
00222       case JOY_CENTER:
00223         LCD_DisplayStringLine(Line5, "JOY: IT CENTER      ");
00224         break;
00225       default:
00226         LCD_DisplayStringLine(Line5, "JOY: IT ERROR       ");
00227         break;
00228       }
00229
00230       /* Clear the interrupt pending bits */
00231       IOE_ClearGITPending(IOE_2_ADDR, IOE_GIT_GPIO);
00232       IOE_ClearIOITPending(IOE_2_ADDR, IOE_JOY_IT);
00233     }
00234     /* CLear all pending interrupt */
00235     IOE_ClearGITPending(IOE_2_ADDR, ALL_IT);
00236     IOE_ClearIOITPending(IOE_2_ADDR, IOE_JOY_IT);
00237  #endif /* USE_STM3210C_EVAL */
00238
00239     /* CLear all pending interrupt */
00240     IOE_ClearGITPending(IOE_1_ADDR, ALL_IT);
00241
00242 #endif /* IOE_INTERRUPT_MODE */
00243
00244     EXTI_ClearITPendingBit(IOE_IT_EXTI_LINE);
00245   }
00246 }
00247
00248 /**
00249   * @}
00250   */
00251
00252
00253 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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  • I2C
  • IOExpander

STM32F10x_StdPeriph_Examples/I2C/IOExpander/stm32f10x_it.h

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00001 /**
00002   ******************************************************************************
00003   * @file    I2C/IOExpander/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043 void EXTI15_10_IRQHandler(void);
00044
00045 #endif /* __STM32F10x_IT_H */
00046
00047 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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STM32F10x_StdPeriph_Examples/I2S/Interrupt/main.c

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00001 /**
00002   ******************************************************************************
00003   * @file    I2S/Interrupt/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x.h"
00024
00025 /** @addtogroup STM32F10x_StdPeriph_Examples
00026   * @{
00027   */
00028
00029 /** @addtogroup I2S_Interrupt
00030   * @{
00031   */
00032
00033 /* Private typedef -----------------------------------------------------------*/
00034 typedef enum {FAILED = 0, PASSED = !FAILED} TestStatus;
00035
00036 /* Private define ------------------------------------------------------------*/
00037 /* Private macro -------------------------------------------------------------*/
00038 /* Private variables ---------------------------------------------------------*/
00039 I2S_InitTypeDef I2S_InitStructure;
00040 const uint16_t I2S3_Buffer_Tx[32] = {0x0102, 0x0304, 0x0506, 0x0708, 0x090A, 0x0B0C,
00041                                      0x0D0E, 0x0F10, 0x1112, 0x1314, 0x1516, 0x1718,
00042                                      0x191A, 0x1B1C, 0x1D1E, 0x1F20, 0x2122, 0x2324,
00043                                      0x2526, 0x2728, 0x292A, 0x2B2C, 0x2D2E, 0x2F30,
00044                                      0x3132, 0x3334, 0x3536, 0x3738, 0x393A, 0x3B3C,
00045                                      0x3D3E, 0x3F40};
00046
00047 uint16_t I2S2_Buffer_Rx[32];
00048 __IO uint32_t TxIdx = 0, RxIdx = 0;
00049 TestStatus TransferStatus1 = FAILED, TransferStatus2 = FAILED;
00050 ErrorStatus HSEStartUpStatus;
00051
00052 /* Private function prototypes -----------------------------------------------*/
00053 void RCC_Configuration(void);
00054 void GPIO_Configuration(void);
00055 void NVIC_Configuration(void);
00056 TestStatus Buffercmp(uint16_t* pBuffer1, uint16_t* pBuffer2, uint16_t BufferLength);
00057 TestStatus Buffercmp24bits(uint16_t* pBuffer1, uint16_t* pBuffer2, uint16_t BufferLength);
00058
00059 /* Private functions ---------------------------------------------------------*/
00060
00061 /**
00062   * @brief  Main program
00063   * @param  None
00064   * @retval None
00065   */
00066 int main(void)
00067 {
00068   /*!< At this stage the microcontroller clock setting is already configured,
00069        this is done through SystemInit() function which is called from startup
00070        file (startup_stm32f10x_xx.s) before to branch to application main.
00071        To reconfigure the default setting of SystemInit() function, refer to
00072        system_stm32f10x.c file
00073      */
00074
00075   /* System clocks configuration ---------------------------------------------*/
00076   RCC_Configuration();
00077
00078   /* NVIC configuration ------------------------------------------------------*/
00079   NVIC_Configuration();
00080
00081   /* GPIO configuration ------------------------------------------------------*/
00082   GPIO_Configuration();
00083
00084   SPI_I2S_DeInit(SPI3);
00085   SPI_I2S_DeInit(SPI2);
00086
00087   /* I2S peripheral configuration */
00088   I2S_InitStructure.I2S_Standard = I2S_Standard_Phillips;
00089   I2S_InitStructure.I2S_DataFormat = I2S_DataFormat_16bextended;
00090   I2S_InitStructure.I2S_MCLKOutput = I2S_MCLKOutput_Disable;
00091   I2S_InitStructure.I2S_AudioFreq = I2S_AudioFreq_48k;
00092   I2S_InitStructure.I2S_CPOL = I2S_CPOL_Low;
00093
00094   /* I2S3 Master Transmitter to I2S2 Slave Receiver communication -----------*/
00095   /* I2S3 configuration */
00096   I2S_InitStructure.I2S_Mode = I2S_Mode_MasterTx;
00097   I2S_Init(SPI3, &I2S_InitStructure);
00098
00099   /* I2S2 configuration */
00100   I2S_InitStructure.I2S_Mode = I2S_Mode_SlaveRx;
00101   I2S_Init(SPI2, &I2S_InitStructure);
00102
00103   /* Enable the I2S3 TxE interrupt */
00104   SPI_I2S_ITConfig(SPI3, SPI_I2S_IT_TXE, ENABLE);
00105
00106   /* Enable the I2S2 RxNE interrupt */
00107   SPI_I2S_ITConfig(SPI2, SPI_I2S_IT_RXNE, ENABLE);
00108
00109   /* Enable the I2S2 */
00110   I2S_Cmd(SPI2, ENABLE);
00111
00112   /* Enable the I2S3 */
00113   I2S_Cmd(SPI3, ENABLE);
00114
00115   /* Wait the end of communication */
00116   while (RxIdx < 32)
00117   {}
00118
00119   TransferStatus1 = Buffercmp(I2S2_Buffer_Rx, (uint16_t*)I2S3_Buffer_Tx, 32);
00120   /* TransferStatus1 = PASSED, if the data transmitted from I2S3 and received by
00121                                I2S2 are the same
00122      TransferStatus1 = FAILED, if the data transmitted from I2S3 and received by
00123                                I2S2 are different */
00124
00125   /* Reinitialize the buffers */
00126   for (RxIdx = 0; RxIdx < 32; RxIdx++)
00127   {
00128     I2S2_Buffer_Rx[RxIdx] = 0;
00129   }
00130   TxIdx = 0;
00131   RxIdx = 0;
00132
00133   SPI_I2S_DeInit(SPI3);
00134   SPI_I2S_DeInit(SPI2);
00135
00136   /* I2S peripheral configuration */
00137   I2S_InitStructure.I2S_Standard = I2S_Standard_Phillips;
00138   I2S_InitStructure.I2S_DataFormat = I2S_DataFormat_24b;
00139   I2S_InitStructure.I2S_MCLKOutput = I2S_MCLKOutput_Disable;
00140   I2S_InitStructure.I2S_AudioFreq = I2S_AudioFreq_16k;
00141   I2S_InitStructure.I2S_CPOL = I2S_CPOL_Low;
00142
00143   /* I2S3 Master Transmitter to I2S2 Slave Receiver communication -----------*/
00144   /* I2S3 configuration */
00145   I2S_InitStructure.I2S_Mode = I2S_Mode_MasterTx;
00146   I2S_Init(SPI3, &I2S_InitStructure);
00147
00148   /* I2S2 configuration */
00149   I2S_InitStructure.I2S_Mode = I2S_Mode_SlaveRx;
00150   I2S_Init(SPI2, &I2S_InitStructure);
00151
00152   /* Enable the I2S3 TxE interrupt */
00153   SPI_I2S_ITConfig(SPI3, SPI_I2S_IT_TXE, ENABLE);
00154
00155   /* Enable the I2S2 RxNE interrupt */
00156   SPI_I2S_ITConfig(SPI2, SPI_I2S_IT_RXNE, ENABLE);
00157
00158   /* Enable the I2S2 */
00159   I2S_Cmd(SPI2, ENABLE);
00160
00161   /* Enable the I2S3 */
00162   I2S_Cmd(SPI3, ENABLE);
00163
00164   /* Wait the end of communication */
00165   while (RxIdx < 32)
00166   {
00167   }
00168
00169   TransferStatus2 = Buffercmp24bits(I2S2_Buffer_Rx, (uint16_t*)I2S3_Buffer_Tx, 32);
00170   /* TransferStatus2 = PASSED, if the data transmitted from I2S3 and received by
00171                                I2S2 are the same
00172      TransferStatus2 = FAILED, if the data transmitted from I2S3 and received by
00173                                I2S2 are different */
00174
00175   while (1)
00176   {
00177   }
00178 }
00179
00180 /**
00181   * @brief  Configures the different system clocks.
00182   * @param  None
00183   * @retval None
00184   */
00185 void RCC_Configuration(void)
00186 {
00187   /* RCC system reset(for debug purpose) */
00188   RCC_DeInit();
00189
00190   /* Enable HSE */
00191   RCC_HSEConfig(RCC_HSE_ON);
00192
00193   /* Wait till HSE is ready */
00194   HSEStartUpStatus = RCC_WaitForHSEStartUp();
00195
00196   if(HSEStartUpStatus == SUCCESS)
00197   {
00198     /* Enable Prefetch Buffer */
00199     FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable);
00200
00201     /* Flash 2 wait state */
00202     FLASH_SetLatency(FLASH_Latency_2);
00203
00204     /* HCLK = SYSCLK */
00205     RCC_HCLKConfig(RCC_SYSCLK_Div1);
00206
00207     /* PCLK2 = HCLK */
00208     RCC_PCLK2Config(RCC_HCLK_Div1);
00209
00210     /* PCLK1 = HCLK/2 */
00211     RCC_PCLK1Config(RCC_HCLK_Div2);
00212
00213     /* ADCCLK = PCLK2/4 */
00214     RCC_ADCCLKConfig(RCC_PCLK2_Div4);
00215
00216 #ifndef STM32F10X_CL
00217     /* PLLCLK = 8MHz * 9 = 72 MHz */
00218     RCC_PLLConfig(RCC_PLLSource_HSE_Div1, RCC_PLLMul_9);
00219
00220 #else
00221     /* Configure PLLs *********************************************************/
00222     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00223     RCC_PREDIV2Config(RCC_PREDIV2_Div5);
00224     RCC_PLL2Config(RCC_PLL2Mul_8);
00225
00226     /* Enable PLL2 */
00227     RCC_PLL2Cmd(ENABLE);
00228
00229     /* Wait till PLL2 is ready */
00230     while (RCC_GetFlagStatus(RCC_FLAG_PLL2RDY) == RESET)
00231     {}
00232
00233     /* PLL configuration: PLLCLK = (PLL2 / 5) * 9 = 72 MHz */
00234     RCC_PREDIV1Config(RCC_PREDIV1_Source_PLL2, RCC_PREDIV1_Div5);
00235     RCC_PLLConfig(RCC_PLLSource_PREDIV1, RCC_PLLMul_9);
00236
00237     /* PLL3 configuration: PLL3CLK = (HSE / 5) * 11 => PLL3_VCO = 110 MHz */
00238     RCC_PLL3Config(RCC_PLL3Mul_11);
00239     /* Enable PLL3 */
00240     RCC_PLL3Cmd(ENABLE);
00241     /* Wait till PLL3 is ready */
00242     while (RCC_GetFlagStatus(RCC_FLAG_PLL3RDY) == RESET)
00243     {}
00244
00245     /* Configure I2S clock source: On Connectivity Line Devices, the I2S can be
00246         clocked by PLL3 VCO instead of SYS_CLK in order to guarantee higher
00247         precision */
00248     RCC_I2S3CLKConfig(RCC_I2S3CLKSource_PLL3_VCO);
00249     RCC_I2S2CLKConfig(RCC_I2S2CLKSource_PLL3_VCO);
00250 #endif
00251
00252     /* Enable PLL */
00253     RCC_PLLCmd(ENABLE);
00254
00255     /* Wait till PLL is ready */
00256     while(RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET)
00257     {
00258     }
00259
00260     /* Select PLL as system clock source */
00261     RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
00262
00263     /* Wait till PLL is used as system clock source */
00264     while(RCC_GetSYSCLKSource() != 0x08)
00265     {
00266     }
00267   }
00268
00269   /* Enable peripheral clocks ------------------------------------------------*/
00270   /* GPIOA, GPIOB and AFIO clocks enable */
00271   RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB |
00272                          RCC_APB2Periph_AFIO, ENABLE);
00273
00274 #ifdef USE_STM3210C_EVAL
00275   /* GPIOC Clock enable (for the SPI3 remapped pins)  */
00276   RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC , ENABLE);
00277 #endif /* USE_STM3210C_EVAL */
00278
00279   /* SPI3 and SPI2 clocks enable */
00280   RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI3 | RCC_APB1Periph_SPI2, ENABLE);
00281 }
00282
00283 /**
00284   * @brief  Configures the different GPIO ports.
00285   * @param  None
00286   * @retval None
00287   */
00288 void GPIO_Configuration(void)
00289 {
00290   GPIO_InitTypeDef GPIO_InitStructure;
00291
00292 #ifdef USE_STM3210E_EVAL
00293   /* Disable the JTAG interface and enable the SWJ interface
00294       This operation is not necessary for Connectivity Line devices since
00295       SPI3 I/Os can be remapped on other GPIO pins */
00296   GPIO_PinRemapConfig(GPIO_Remap_SWJ_JTAGDisable, ENABLE);
00297 #endif /* USE_STM3210E_EVAL */
00298
00299   /* Configure SPI2 pins: CK, WS and SD ---------------------------------*/
00300   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_15;
00301   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00302   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
00303   GPIO_Init(GPIOB, &GPIO_InitStructure);
00304
00305 #ifdef USE_STM3210C_EVAL
00306
00307   /* Remap SPI3 on PC10-PC11-PC12-PA4 GPIO pins ------------------------*/
00308   GPIO_PinRemapConfig(GPIO_Remap_SPI3, ENABLE);
00309
00310   /* Configure SPI3 pins: CK and SD ------------------------------------*/
00311   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10 | GPIO_Pin_12;
00312   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
00313   GPIO_Init(GPIOC, &GPIO_InitStructure);
00314
00315   /* Configure SPI3 pins: WS -------------------------------------------*/
00316   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4;
00317   GPIO_Init(GPIOA, &GPIO_InitStructure);
00318
00319 #elif defined (USE_STM3210E_EVAL)
00320
00321   /* Configure SPI3 pins: CK and SD ------------------------------------*/
00322   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3 | GPIO_Pin_5;
00323   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
00324   GPIO_Init(GPIOB, &GPIO_InitStructure);
00325
00326   /* Configure SPI3 pins: WS -------------------------------------------*/
00327   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_15;
00328   GPIO_Init(GPIOA, &GPIO_InitStructure);
00329
00330 #endif /* USE_STM3210C_EVAL */
00331 }
00332
00333 /**
00334   * @brief  Configure the nested vectored interrupt controller.
00335   * @param  None
00336   * @retval None
00337   */
00338 void NVIC_Configuration(void)
00339 {
00340   NVIC_InitTypeDef NVIC_InitStructure;
00341
00342   NVIC_PriorityGroupConfig(NVIC_PriorityGroup_0);
00343
00344   /* SPI3 IRQ Channel configuration */
00345   NVIC_InitStructure.NVIC_IRQChannel = SPI3_IRQn;
00346   NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
00347   NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
00348   NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
00349   NVIC_Init(&NVIC_InitStructure);
00350
00351   /* SPI2 IRQ channel configuration */
00352   NVIC_InitStructure.NVIC_IRQChannel = SPI2_IRQn;
00353   NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
00354   NVIC_Init(&NVIC_InitStructure);
00355 }
00356
00357 /**
00358   * @brief  Compares two buffers.
00359   * @param  pBuffer1, pBuffer2: buffers to be compared.
00360   * @param  BufferLength: buffer's length
00361   * @retval PASSED: pBuffer1 identical to pBuffer2
00362   *         FAILED: pBuffer1 differs from pBuffer2
00363   */
00364 TestStatus Buffercmp(uint16_t* pBuffer1, uint16_t* pBuffer2, uint16_t BufferLength)
00365 {
00366   while (BufferLength--)
00367   {
00368     if (*pBuffer1 != *pBuffer2)
00369     {
00370       return FAILED;
00371     }
00372
00373     pBuffer1++;
00374     pBuffer2++;
00375   }
00376
00377   return PASSED;
00378 }
00379
00380 /**
00381   * @brief  Compares two buffers in 24 bits data format.
00382   * @param  pBuffer1, pBuffer2: buffers to be compared.
00383   * @param  BufferLength: buffer's length
00384   * @retval PASSED: pBuffer1 identical to pBuffer2
00385   *         FAILED: pBuffer1 differs from pBuffer2
00386   */
00387 TestStatus Buffercmp24bits(uint16_t* pBuffer1, uint16_t* pBuffer2, uint16_t BufferLength)
00388 {
00389   while (BufferLength--)
00390   {
00391     if (*pBuffer1 != *pBuffer2)
00392     {
00393       if (*pBuffer1 != (*pBuffer2 & 0xFF00))
00394       {
00395         return FAILED;
00396       }
00397     }
00398
00399     pBuffer1++;
00400     pBuffer2++;
00401   }
00402
00403   return PASSED;
00404 }
00405
00406 #ifdef  USE_FULL_ASSERT
00407
00408 /**
00409   * @brief  Reports the name of the source file and the source line number
00410   *         where the assert_param error has occurred.
00411   * @param  file: pointer to the source file name
00412   * @param  line: assert_param error line source number
00413   * @retval None
00414   */
00415 void assert_failed(uint8_t* file, uint32_t line)
00416 {
00417   /* User can add his own implementation to report the file name and line number,
00418      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00419
00420   /* Infinite loop */
00421   while (1)
00422   {}
00423 }
00424
00425 #endif
00426
00427 /**
00428   * @}
00429   */
00430
00431 /**
00432   * @}
00433   */
00434
00435 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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  • I2S
  • Interrupt

STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_conf.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    I2S/Interrupt/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052 /* Exported types ------------------------------------------------------------*/
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Uncomment the line below to expanse the "assert_param" macro in the
00055    Standard Peripheral Library drivers code */
00056 /* #define USE_FULL_ASSERT    1 */
00057
00058 /* Exported macro ------------------------------------------------------------*/
00059 #ifdef  USE_FULL_ASSERT
00060
00061 /**
00062   * @brief  The assert_param macro is used for function's parameters check.
00063   * @param  expr: If expr is false, it calls assert_failed function which reports
00064   *         the name of the source file and the source line number of the call
00065   *         that failed. If expr is true, it returns no value.
00066   * @retval None
00067   */
00068   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00069 /* Exported functions ------------------------------------------------------- */
00070   void assert_failed(uint8_t* file, uint32_t line);
00071 #else
00072   #define assert_param(expr) ((void)0)
00073 #endif /* USE_FULL_ASSERT */
00074
00075 #endif /* __STM32F10x_CONF_H */
00076
00077 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_it.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    I2S/Interrupt/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and peripherals
00009   *          interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026
00027 /** @addtogroup STM32F10x_StdPeriph_Examples
00028   * @{
00029   */
00030
00031 /** @addtogroup I2S_Interrupt
00032   * @{
00033   */
00034
00035 /* Private typedef -----------------------------------------------------------*/
00036 /* Private define ------------------------------------------------------------*/
00037 /* Private macro -------------------------------------------------------------*/
00038 /* Private variables ---------------------------------------------------------*/
00039 extern const uint16_t I2S3_Buffer_Tx[32];
00040 extern uint16_t I2S2_Buffer_Rx[32];
00041 extern  __IO uint32_t TxIdx, RxIdx;
00042
00043 /* Private function prototypes -----------------------------------------------*/
00044 /* Private functions ---------------------------------------------------------*/
00045
00046 /******************************************************************************/
00047 /*            Cortex-M3 Processor Exceptions Handlers                         */
00048 /******************************************************************************/
00049
00050 /**
00051   * @brief  This function handles NMI exception.
00052   * @param  None
00053   * @retval None
00054   */
00055 void NMI_Handler(void)
00056 {
00057 }
00058
00059 /**
00060   * @brief  This function handles Hard Fault exception.
00061   * @param  None
00062   * @retval None
00063   */
00064 void HardFault_Handler(void)
00065 {
00066   /* Go to infinite loop when Hard Fault exception occurs */
00067   while (1)
00068   {}
00069 }
00070
00071 /**
00072   * @brief  This function handles Memory Manage exception.
00073   * @param  None
00074   * @retval None
00075   */
00076 void MemManage_Handler(void)
00077 {
00078   /* Go to infinite loop when Memory Manage exception occurs */
00079   while (1)
00080   {}
00081 }
00082
00083 /**
00084   * @brief  This function handles Bus Fault exception.
00085   * @param  None
00086   * @retval None
00087   */
00088 void BusFault_Handler(void)
00089 {
00090   /* Go to infinite loop when Bus Fault exception occurs */
00091   while (1)
00092   {}
00093 }
00094
00095 /**
00096   * @brief  This function handles Usage Fault exception.
00097   * @param  None
00098   * @retval None
00099   */
00100 void UsageFault_Handler(void)
00101 {
00102   /* Go to infinite loop when Usage Fault exception occurs */
00103   while (1)
00104   {}
00105 }
00106
00107 /**
00108   * @brief  This function handles Debug Monitor exception.
00109   * @param  None
00110   * @retval None
00111   */
00112 void DebugMon_Handler(void)
00113 {
00114 }
00115
00116 /**
00117   * @brief  This function handles SVCall exception.
00118   * @param  None
00119   * @retval None
00120   */
00121 void SVC_Handler(void)
00122 {
00123 }
00124
00125 /**
00126   * @brief  This function handles PendSV_Handler exception.
00127   * @param  None
00128   * @retval None
00129   */
00130 void PendSV_Handler(void)
00131 {
00132 }
00133
00134 /**
00135   * @brief  This function handles SysTick Handler.
00136   * @param  None
00137   * @retval None
00138   */
00139 void SysTick_Handler(void)
00140 {
00141 }
00142
00143 /******************************************************************************/
00144 /*            STM32F10x Peripherals Interrupt Handlers                        */
00145 /******************************************************************************/
00146
00147 /**
00148   * @brief  This function handles SPI3 global interrupt request.
00149   * @param  None
00150   * @retval None
00151   */
00152 void SPI3_IRQHandler(void)
00153 {
00154   /* Check the interrupt source */
00155   if (SPI_I2S_GetITStatus(SPI3, SPI_I2S_IT_TXE) == SET)
00156   {
00157     /* Send a data from I2S3 */
00158     SPI_I2S_SendData(SPI3, I2S3_Buffer_Tx[TxIdx++]);
00159   }
00160
00161   /* Check the end of buffer transfer */
00162   if (RxIdx == 32)
00163   {
00164     /* Disable the I2S3 TXE interrupt to end the communication */
00165     SPI_I2S_ITConfig(SPI3, SPI_I2S_IT_TXE, DISABLE);
00166   }
00167 }
00168
00169 /**
00170   * @brief  This function handles SPI2 global interrupt request.
00171   * @param  None
00172   * @retval None
00173   */
00174 void SPI2_IRQHandler(void)
00175 {
00176   /* Check the interrupt source */
00177   if (SPI_I2S_GetITStatus(SPI2, SPI_I2S_IT_RXNE) == SET)
00178   {
00179     /* Store the I2S2 received data in the relative data table */
00180     I2S2_Buffer_Rx[RxIdx++] = SPI_I2S_ReceiveData(SPI2);
00181   }
00182 }
00183
00184 /******************************************************************************/
00185 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00186 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00187 /*  available peripheral interrupt handler's name please refer to the startup */
00188 /*  file (startup_stm32f10x_xx.s).                                            */
00189 /******************************************************************************/
00190
00191 /**
00192   * @brief  This function handles PPP interrupt request.
00193   * @param  None
00194   * @retval None
00195   */
00196 /*void PPP_IRQHandler(void)
00197 {
00198 }*/
00199
00200 /**
00201   * @}
00202   */
00203
00204 /**
00205   * @}
00206   */
00207
00208 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_it.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    I2S/Interrupt/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043 void SPI2_IRQHandler(void);
00044 void SPI3_IRQHandler(void);
00045
00046 #endif /* __STM32F10x_IT_H */
00047
00048 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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  • SPI_I2S_Switch

STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/main.c

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00001 /**
00002   ******************************************************************************
00003   * @file    I2S/SPI_I2S_Switch/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x.h"
00024
00025 /* Local includes ------------------------------------------------------------*/
00026
00027 /** @addtogroup STM32F10x_StdPeriph_Examples
00028   * @{
00029   */
00030
00031 /** @addtogroup I2S_SPI_I2S_Switch
00032   * @{
00033   */
00034
00035 /* Private typedef -----------------------------------------------------------*/
00036 typedef enum {FAILED = 0, PASSED = !FAILED} TestStatus;
00037
00038 /* Private define ------------------------------------------------------------*/
00039 #define BufferSize   32
00040
00041 /* Private macro -------------------------------------------------------------*/
00042 /* Private variables ---------------------------------------------------------*/
00043 I2S_InitTypeDef I2S_InitStructure;
00044 SPI_InitTypeDef SPI_InitStructure;
00045 uint16_t I2S3_Buffer_Tx[BufferSize] = {0x0102, 0x0304, 0x0506, 0x0708, 0x090A, 0x0B0C,
00046                                   0x0D0E, 0x0F10, 0x1112, 0x1314, 0x1516, 0x1718,
00047                                   0x191A, 0x1B1C, 0x1D1E, 0x1F20, 0x2122, 0x2324,
00048                                   0x2526, 0x2728, 0x292A, 0x2B2C, 0x2D2E, 0x2F30,
00049                                   0x3132, 0x3334, 0x3536, 0x3738, 0x393A, 0x3B3C,
00050                                   0x3D3E, 0x3F40};
00051
00052 uint16_t SPI3_Buffer_Tx[BufferSize] = {0x5152, 0x5354, 0x5556, 0x5758, 0x595A, 0x5B5C,
00053                                   0x5D5E, 0x5F60, 0x6162, 0x6364, 0x6566, 0x6768,
00054                                   0x696A, 0x6B6C, 0x6D6E, 0x6F70, 0x7172, 0x7374,
00055                                   0x7576, 0x7778, 0x797A, 0x7B7C, 0x7D7E, 0x7F80,
00056                                   0x8182, 0x8384, 0x8586, 0x8788, 0x898A, 0x8B8C,
00057                                   0x8D8E, 0x8F90};
00058
00059 __IO uint16_t I2S2_Buffer_Rx[BufferSize];
00060 __IO uint16_t SPI2_Buffer_Rx[BufferSize];
00061 __IO uint8_t TxIdx = 0, RxIdx = 0;
00062 volatile TestStatus TransferStatus1 = FAILED, TransferStatus2 = FAILED;
00063 volatile TestStatus TransferStatus3 = FAILED;
00064 ErrorStatus HSEStartUpStatus;
00065
00066 /* Private functions ---------------------------------------------------------*/
00067 void RCC_Configuration(void);
00068 void GPIO_Configuration(void);
00069 TestStatus Buffercmp(uint16_t* pBuffer1, uint16_t* pBuffer2, uint16_t BufferLength);
00070
00071 /**
00072   * @brief   Main program
00073   * @param  None
00074   * @retval None
00075   */
00076 int main(void)
00077 {
00078   /*!< At this stage the microcontroller clock setting is already configured,
00079        this is done through SystemInit() function which is called from startup
00080        file (startup_stm32f10x_xx.s) before to branch to application main.
00081        To reconfigure the default setting of SystemInit() function, refer to
00082        system_stm32f10x.c file
00083      */
00084
00085   /* System clocks configuration ---------------------------------------------*/
00086   RCC_Configuration();
00087
00088   /* GPIO configuration ------------------------------------------------------*/
00089   GPIO_Configuration();
00090
00091   /* Deinitializes the SPI2 and SPI3 peripheral registers --------------------*/
00092   SPI_I2S_DeInit(SPI2);
00093   SPI_I2S_DeInit(SPI3);
00094
00095   /* I2S peripheral configuration */
00096   I2S_InitStructure.I2S_Standard = I2S_Standard_Phillips;
00097   I2S_InitStructure.I2S_DataFormat = I2S_DataFormat_16bextended;
00098   I2S_InitStructure.I2S_MCLKOutput = I2S_MCLKOutput_Disable;
00099   I2S_InitStructure.I2S_AudioFreq = I2S_AudioFreq_48k;
00100   I2S_InitStructure.I2S_CPOL = I2S_CPOL_Low;
00101
00102   /* I2S3 Master Transmitter to I2S2 Slave Receiver communication ------------*/
00103   /* I2S3 configuration */
00104   I2S_InitStructure.I2S_Mode = I2S_Mode_MasterTx;
00105   I2S_Init(SPI3, &I2S_InitStructure);
00106
00107   /* I2S2 configuration */
00108   I2S_InitStructure.I2S_Mode = I2S_Mode_SlaveRx;
00109   I2S_Init(SPI2, &I2S_InitStructure);
00110
00111   /* Enable the I2S2 */
00112   I2S_Cmd(SPI2, ENABLE);
00113
00114   /* Enable the I2S3 */
00115   I2S_Cmd(SPI3, ENABLE);
00116
00117   /* Begin the communication in I2S mode */
00118   while (RxIdx < BufferSize)
00119   {
00120     /* Wait the Tx buffer to be empty */
00121     while (SPI_I2S_GetFlagStatus(SPI3, SPI_I2S_FLAG_TXE) == RESET)
00122     {}
00123     /* Send a data from I2S3 */
00124     SPI_I2S_SendData(SPI3, I2S3_Buffer_Tx[TxIdx++]);
00125
00126     /* Wait the Rx buffer to be full */
00127     while (SPI_I2S_GetFlagStatus(SPI2, SPI_I2S_FLAG_RXNE) == RESET)
00128     {}
00129     /* Store the I2S2 received data in the relative data table */
00130     I2S2_Buffer_Rx[RxIdx++] = SPI_I2S_ReceiveData(SPI2);
00131   }
00132
00133   TransferStatus1 = Buffercmp((uint16_t *)I2S2_Buffer_Rx, I2S3_Buffer_Tx, BufferSize);
00134   /* TransferStatus1 = PASSED, if the data transmitted from I2S3 and received by
00135                                I2S2 are the same
00136      TransferStatus1 = FAILED, if the data transmitted from I2S3 and received by
00137                                I2S2 are different */
00138
00139   /* Reset TxIdx, RxIdx indexes */
00140   TxIdx = 0;
00141   RxIdx = 0;
00142
00143   /* Switch to SPI mode communication ----------------------------------------*/
00144   /* SPI3 configuration */
00145   SPI_InitStructure.SPI_Direction = SPI_Direction_1Line_Tx;
00146   SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
00147   SPI_InitStructure.SPI_DataSize = SPI_DataSize_16b;
00148   SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low;
00149   SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge;
00150   SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
00151   SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_4;
00152   SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
00153   SPI_InitStructure.SPI_CRCPolynomial = 7;
00154   SPI_Init(SPI3, &SPI_InitStructure);
00155
00156   /* SPI2 configuration ------------------------------------------------------*/
00157   SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_RxOnly;
00158   SPI_InitStructure.SPI_Mode = SPI_Mode_Slave;
00159   SPI_Init(SPI2, &SPI_InitStructure);
00160
00161   /* Enable SPI2 */
00162   SPI_Cmd(SPI2, ENABLE);
00163   /* Enable SPI3 */
00164   SPI_Cmd(SPI3, ENABLE);
00165
00166   /* Begin the communication in SPI mode */
00167   while (RxIdx < BufferSize)
00168   {
00169     /* Wait the Tx buffer to be empty */
00170     while (SPI_I2S_GetFlagStatus(SPI3, SPI_I2S_FLAG_TXE) == RESET)
00171     {}
00172     /* Send a data from SPI3 */
00173     SPI_I2S_SendData(SPI3, SPI3_Buffer_Tx[TxIdx++]);
00174
00175     /* Wait the Rx buffer to be full */
00176     while (SPI_I2S_GetFlagStatus(SPI2, SPI_I2S_FLAG_RXNE) == RESET)
00177     {}
00178     /* Store the SPI2 received data in the relative data table */
00179     SPI2_Buffer_Rx[RxIdx++] = SPI_I2S_ReceiveData(SPI2);
00180   }
00181
00182   TransferStatus2 = Buffercmp((uint16_t *)SPI2_Buffer_Rx, SPI3_Buffer_Tx, BufferSize);
00183   /* TransferStatus2 = PASSED, if the data transmitted from SPI3 and received by
00184                                SPI2 are the same
00185      TransferStatus2 = FAILED, if the data transmitted from SPI3 and received by
00186                                SPI2 are different */
00187
00188   /* Reset TxIdx, RxIdx indexes and receive table values */
00189   for (TxIdx = 0; TxIdx < BufferSize; TxIdx++)
00190   {
00191     I2S2_Buffer_Rx[TxIdx] = 0;
00192   }
00193
00194   TxIdx = 0;
00195   RxIdx = 0;
00196
00197   /* I2S3 Slave Transmitter to I2S2 Master Receiver communication ------------*/
00198   /* I2S3 configuration */
00199   I2S_InitStructure.I2S_Mode = I2S_Mode_SlaveTx;
00200   I2S_Init(SPI3, &I2S_InitStructure);
00201
00202   /* I2S2 configuration */
00203   I2S_InitStructure.I2S_Mode = I2S_Mode_MasterRx;
00204   I2S_Init(SPI2, &I2S_InitStructure);
00205
00206   /* Wait the Tx buffer to be empty */
00207   while (SPI_I2S_GetFlagStatus(SPI3, SPI_I2S_FLAG_TXE) == RESET)
00208   {}
00209   /* Prepare the first data to be sent from the slave */
00210   SPI_I2S_SendData(SPI3, I2S3_Buffer_Tx[TxIdx++]);
00211
00212   /* Enable the I2S3 */
00213   I2S_Cmd(SPI3, ENABLE);
00214
00215   /* Enable the I2S2 */
00216   I2S_Cmd(SPI2, ENABLE);
00217
00218   /* Begin the communication in I2S mode */
00219   while (RxIdx < BufferSize)
00220   {
00221     /* Wait the Rx buffer to be full */
00222     while (SPI_I2S_GetFlagStatus(SPI2, SPI_I2S_FLAG_RXNE) == RESET)
00223     {}
00224     /* Store the I2S2 received data in the relative data table */
00225     I2S2_Buffer_Rx[RxIdx++] = SPI_I2S_ReceiveData(SPI2);
00226
00227     /* Wait the Tx buffer to be empty */
00228     while (SPI_I2S_GetFlagStatus(SPI3, SPI_I2S_FLAG_TXE) == RESET)
00229     {}
00230     /* Send a data from I2S3 */
00231     SPI_I2S_SendData(SPI3, I2S3_Buffer_Tx[TxIdx++]);
00232   }
00233
00234   TransferStatus3 = Buffercmp((uint16_t *)I2S2_Buffer_Rx, I2S3_Buffer_Tx, BufferSize);
00235   /* TransferStatus3 = PASSED, if the data transmitted from I2S3 and received by
00236                                I2S2 are the same
00237      TransferStatus3 = FAILED, if the data transmitted from I2S3 and received by
00238                                I2S2 are different */
00239
00240   while (1)
00241   {}
00242 }
00243
00244 /**
00245   * @brief  Configures the different system clocks.
00246   * @param  None
00247   * @retval None
00248   */
00249 void RCC_Configuration(void)
00250 {
00251   /* RCC system reset(for debug purpose) */
00252   RCC_DeInit();
00253
00254   /* Enable HSE */
00255   RCC_HSEConfig(RCC_HSE_ON);
00256
00257   /* Wait till HSE is ready */
00258   HSEStartUpStatus = RCC_WaitForHSEStartUp();
00259
00260   if(HSEStartUpStatus == SUCCESS)
00261   {
00262     /* Enable Prefetch Buffer */
00263     FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable);
00264
00265     /* Flash 2 wait state */
00266     FLASH_SetLatency(FLASH_Latency_2);
00267
00268     /* HCLK = SYSCLK */
00269     RCC_HCLKConfig(RCC_SYSCLK_Div1);
00270
00271     /* PCLK2 = HCLK */
00272     RCC_PCLK2Config(RCC_HCLK_Div1);
00273
00274     /* PCLK1 = HCLK/2 */
00275     RCC_PCLK1Config(RCC_HCLK_Div2);
00276
00277     /* ADCCLK = PCLK2/4 */
00278     RCC_ADCCLKConfig(RCC_PCLK2_Div4);
00279
00280 #ifndef STM32F10X_CL
00281     /* PLLCLK = 8MHz * 9 = 72 MHz */
00282     RCC_PLLConfig(RCC_PLLSource_HSE_Div1, RCC_PLLMul_9);
00283
00284 #else
00285     /* Configure PLLs *********************************************************/
00286     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00287     RCC_PREDIV2Config(RCC_PREDIV2_Div5);
00288     RCC_PLL2Config(RCC_PLL2Mul_8);
00289
00290     /* Enable PLL2 */
00291     RCC_PLL2Cmd(ENABLE);
00292
00293     /* Wait till PLL2 is ready */
00294     while (RCC_GetFlagStatus(RCC_FLAG_PLL2RDY) == RESET)
00295     {}
00296
00297     /* PLL configuration: PLLCLK = (PLL2 / 5) * 9 = 72 MHz */
00298     RCC_PREDIV1Config(RCC_PREDIV1_Source_PLL2, RCC_PREDIV1_Div5);
00299     RCC_PLLConfig(RCC_PLLSource_PREDIV1, RCC_PLLMul_9);
00300
00301     /* PPL3 configuration: PLL3CLK = (HSE / 5) * 11 = PLL3_VCO = 110 MHz */
00302     RCC_PLL3Config(RCC_PLL3Mul_11);
00303     /* Enable PLL3 */
00304     RCC_PLL3Cmd(ENABLE);
00305     /* Wait till PLL3 is ready */
00306     while (RCC_GetFlagStatus(RCC_FLAG_PLL3RDY) == RESET)
00307     {}
00308
00309     /* Configure I2S clock source: On Connectivity Line Devices, the I2S can be
00310         clocked by PLL3 VCO instead of SYS_CLK in order to guarantee higher
00311         precision */
00312     RCC_I2S3CLKConfig(RCC_I2S3CLKSource_PLL3_VCO);
00313     RCC_I2S2CLKConfig(RCC_I2S2CLKSource_PLL3_VCO);
00314 #endif
00315
00316     /* Enable PLL */
00317     RCC_PLLCmd(ENABLE);
00318
00319     /* Wait till PLL is ready */
00320     while(RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET)
00321     {
00322     }
00323
00324     /* Select PLL as system clock source */
00325     RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
00326
00327     /* Wait till PLL is used as system clock source */
00328     while(RCC_GetSYSCLKSource() != 0x08)
00329     {
00330     }
00331   }
00332
00333   /* Enable peripheral clocks --------------------------------------------------*/
00334   /* GPIOA, GPIOB and AFIO clocks enable */
00335   RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB |
00336                          RCC_APB2Periph_AFIO, ENABLE);
00337
00338 #ifdef USE_STM3210C_EVAL
00339   /* GPIOC Clock enable (for the SPI3 remapped pins)  */
00340   RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC , ENABLE);
00341 #endif /* USE_STM3210C_EVAL */
00342
00343   /* SPI2 and SPI3 clocks enable */
00344   RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2 | RCC_APB1Periph_SPI3, ENABLE);
00345 }
00346
00347 /**
00348   * @brief  Configures the different GPIO ports.
00349   * @param  None
00350   * @retval None
00351   */
00352 void GPIO_Configuration(void)
00353 {
00354   GPIO_InitTypeDef GPIO_InitStructure;
00355
00356 #ifdef USE_STM3210E_EVAL
00357   /* Disable the JTAG interface and enable the SWJ interface
00358       This operation is not necessary for Connectivity Line devices since
00359       SPI3 I/Os can be remapped on other GPIO pins */
00360   GPIO_PinRemapConfig(GPIO_Remap_SWJ_JTAGDisable, ENABLE);
00361 #endif /* USE_STM3210E_EVAL */
00362
00363   /* Configure SPI2 pins: CK, WS and SD ---------------------------------*/
00364   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_15;
00365   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00366   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
00367   GPIO_Init(GPIOB, &GPIO_InitStructure);
00368
00369 #ifdef USE_STM3210C_EVAL
00370
00371   /* Remap SPI3 on PC10-PC11-PC12-PA4 GPIO pins ------------------------*/
00372   GPIO_PinRemapConfig(GPIO_Remap_SPI3, ENABLE);
00373
00374   /* Configure SPI3 pins: CK and SD ------------------------------------*/
00375   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10 | GPIO_Pin_12;
00376   GPIO_Init(GPIOC, &GPIO_InitStructure);
00377
00378   /* Configure SPI3 pins: WS -------------------------------------------*/
00379   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4;
00380   GPIO_Init(GPIOA, &GPIO_InitStructure);
00381
00382 #elif defined (USE_STM3210E_EVAL)
00383
00384   /* Configure SPI3 pins: CK and SD ------------------------------------*/
00385   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3 | GPIO_Pin_5;
00386   GPIO_Init(GPIOB, &GPIO_InitStructure);
00387
00388   /* Configure SPI3 pins: WS -------------------------------------------*/
00389   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_15;
00390   GPIO_Init(GPIOA, &GPIO_InitStructure);
00391
00392 #endif /* USE_STM3210C_EVAL */
00393 }
00394
00395 /**
00396   * @brief  Compares two buffers.
00397   * @param  pBuffer1, pBuffer2: buffers to be compared.
00398   * @param  BufferLength: buffer's length
00399   * @retval PASSED: pBuffer1 identical to pBuffer2
00400   *         FAILED: pBuffer1 differs from pBuffer2
00401   */
00402 TestStatus Buffercmp(uint16_t* pBuffer1, uint16_t* pBuffer2, uint16_t BufferLength)
00403 {
00404   while (BufferLength--)
00405   {
00406     if (*pBuffer1 != *pBuffer2)
00407     {
00408       return FAILED;
00409     }
00410
00411     pBuffer1++;
00412     pBuffer2++;
00413   }
00414
00415   return PASSED;
00416 }
00417
00418 #ifdef  USE_FULL_ASSERT
00419
00420 /**
00421   * @brief  Reports the name of the source file and the source line number
00422   *         where the assert_param error has occurred.
00423   * @param  file: pointer to the source file name
00424   * @param  line: assert_param error line source number
00425   * @retval None
00426   */
00427 void assert_failed(uint8_t* file, uint32_t line)
00428 {
00429   /* User can add his own implementation to report the file name and line number,
00430      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00431
00432   /* Infinite loop */
00433   while (1)
00434   {}
00435 }
00436
00437 #endif
00438
00439 /**
00440   * @}
00441   */
00442
00443 /**
00444   * @}
00445   */
00446
00447 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/stm32f10x_conf.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    I2S/SPI_I2S_Switch/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022
00023 /* Define to prevent recursive inclusion -------------------------------------*/
00024 #ifndef __STM32F10x_CONF_H
00025 #define __STM32F10x_CONF_H
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00029 #include "stm32f10x_adc.h"
00030 #include "stm32f10x_bkp.h"
00031 #include "stm32f10x_can.h"
00032 #include "stm32f10x_cec.h"
00033 #include "stm32f10x_crc.h"
00034 #include "stm32f10x_dac.h"
00035 #include "stm32f10x_dbgmcu.h"
00036 #include "stm32f10x_dma.h"
00037 #include "stm32f10x_exti.h"
00038 #include "stm32f10x_flash.h"
00039 #include "stm32f10x_fsmc.h"
00040 #include "stm32f10x_gpio.h"
00041 #include "stm32f10x_i2c.h"
00042 #include "stm32f10x_iwdg.h"
00043 #include "stm32f10x_pwr.h"
00044 #include "stm32f10x_rcc.h"
00045 #include "stm32f10x_rtc.h"
00046 #include "stm32f10x_sdio.h"
00047 #include "stm32f10x_spi.h"
00048 #include "stm32f10x_tim.h"
00049 #include "stm32f10x_usart.h"
00050 #include "stm32f10x_wwdg.h"
00051 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00052
00053
00054 /* Exported types ------------------------------------------------------------*/
00055 /* Exported constants --------------------------------------------------------*/
00056 /* Uncomment the line below to expanse the "assert_param" macro in the
00057    Standard Peripheral Library drivers code */
00058 /* #define USE_FULL_ASSERT    1 */
00059
00060 /* Exported macro ------------------------------------------------------------*/
00061 #ifdef  USE_FULL_ASSERT
00062
00063 /**
00064   * @brief  The assert_param macro is used for function's parameters check.
00065   * @param  expr: If expr is false, it calls assert_failed function which reports
00066   *         the name of the source file and the source line number of the call
00067   *         that failed. If expr is true, it returns no value.
00068   * @retval None
00069   */
00070   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00071 /* Exported functions ------------------------------------------------------- */
00072   void assert_failed(uint8_t* file, uint32_t line);
00073 #else
00074   #define assert_param(expr) ((void)0)
00075 #endif /* USE_FULL_ASSERT */
00076
00077 #endif /* __STM32F10x_CONF_H */
00078
00079 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/stm32f10x_it.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    I2S/SPI_I2S_Switch/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and peripherals
00009   *          interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026
00027 /** @addtogroup STM32F10x_StdPeriph_Examples
00028   * @{
00029   */
00030
00031 /** @addtogroup I2S_SPI_I2S_Switch
00032   * @{
00033   */
00034
00035 /* Private typedef -----------------------------------------------------------*/
00036 /* Private define ------------------------------------------------------------*/
00037 /* Private macro -------------------------------------------------------------*/
00038 /* Private variables ---------------------------------------------------------*/
00039 /* Private function prototypes -----------------------------------------------*/
00040 /* Private functions ---------------------------------------------------------*/
00041
00042 /******************************************************************************/
00043 /*            Cortex-M3 Processor Exceptions Handlers                         */
00044 /******************************************************************************/
00045
00046 /**
00047   * @brief  This function handles NMI exception.
00048   * @param  None
00049   * @retval None
00050   */
00051 void NMI_Handler(void)
00052 {
00053 }
00054
00055 /**
00056   * @brief  This function handles Hard Fault exception.
00057   * @param  None
00058   * @retval None
00059   */
00060 void HardFault_Handler(void)
00061 {
00062   /* Go to infinite loop when Hard Fault exception occurs */
00063   while (1)
00064   {}
00065 }
00066
00067 /**
00068   * @brief  This function handles Memory Manage exception.
00069   * @param  None
00070   * @retval None
00071   */
00072 void MemManage_Handler(void)
00073 {
00074   /* Go to infinite loop when Memory Manage exception occurs */
00075   while (1)
00076   {}
00077 }
00078
00079 /**
00080   * @brief  This function handles Bus Fault exception.
00081   * @param  None
00082   * @retval None
00083   */
00084 void BusFault_Handler(void)
00085 {
00086   /* Go to infinite loop when Bus Fault exception occurs */
00087   while (1)
00088   {}
00089 }
00090
00091 /**
00092   * @brief  This function handles Usage Fault exception.
00093   * @param  None
00094   * @retval None
00095   */
00096 void UsageFault_Handler(void)
00097 {
00098   /* Go to infinite loop when Usage Fault exception occurs */
00099   while (1)
00100   {}
00101 }
00102
00103 /**
00104   * @brief  This function handles Debug Monitor exception.
00105   * @param  None
00106   * @retval None
00107   */
00108 void DebugMon_Handler(void)
00109 {
00110 }
00111
00112 /**
00113   * @brief  This function handles SVCall exception.
00114   * @param  None
00115   * @retval None
00116   */
00117 void SVC_Handler(void)
00118 {
00119 }
00120
00121 /**
00122   * @brief  This function handles PendSV_Handler exception.
00123   * @param  None
00124   * @retval None
00125   */
00126 void PendSV_Handler(void)
00127 {
00128 }
00129
00130 /**
00131   * @brief  This function handles SysTick Handler.
00132   * @param  None
00133   * @retval None
00134   */
00135 void SysTick_Handler(void)
00136 {
00137 }
00138
00139 /******************************************************************************/
00140 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00141 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00142 /*  available peripheral interrupt handler's name please refer to the startup */
00143 /*  file (startup_stm32f10x_xx.s).                                            */
00144 /******************************************************************************/
00145
00146 /**
00147   * @brief  This function handles PPP interrupt request.
00148   * @param  None
00149   * @retval None
00150   */
00151 /*void PPP_Switch_IRQHandler(void)
00152 {
00153 }*/
00154
00155 /**
00156   * @}
00157   */
00158
00159 /**
00160   * @}
00161   */
00162
00163 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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  • SPI_I2S_Switch

STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/stm32f10x_it.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    I2S/SPI_I2S_Switch/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043
00044 #endif /* __STM32F10x_IT_H */
00045
00046 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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  • IWDG_Reset

STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/main.c

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00001 /**
00002   ******************************************************************************
00003   * @file    IWDG/IWDG_Reset/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x.h"
00024 #include "stm32_eval.h"
00025
00026 /** @addtogroup STM32F10x_StdPeriph_Examples
00027   * @{
00028   */
00029
00030 /** @addtogroup IWDG_Reset
00031   * @{
00032   */
00033
00034 /* Private typedef -----------------------------------------------------------*/
00035 /* Private define ------------------------------------------------------------*/
00036 /* Uncomment/Comment depending on your STM32 device.
00037    The LSI is internally connected to TIM5 IC4 only on STM32F10x Connectivity
00038    line, High-Density Value line, High-Density and XL-Density Devices */
00039 #define LSI_TIM_MEASURE
00040
00041 /* Private macro -------------------------------------------------------------*/
00042 /* Private variables ---------------------------------------------------------*/
00043 __IO uint32_t TimingDelay = 0;
00044 __IO uint32_t LsiFreq = 40000;
00045 extern __IO uint16_t CaptureNumber;
00046
00047 /* Private function prototypes -----------------------------------------------*/
00048 void Delay(__IO uint32_t nTime);
00049 void TIM5_ConfigForLSI(void);
00050
00051 /* Private functions ---------------------------------------------------------*/
00052
00053 /**
00054   * @brief  Main program.
00055   * @param  None
00056   * @retval None
00057   */
00058 int main(void)
00059 {
00060   /*!< At this stage the microcontroller clock setting is already configured,
00061        this is done through SystemInit() function which is called from startup
00062        file (startup_stm32f10x_xx.s) before to branch to application main.
00063        To reconfigure the default setting of SystemInit() function, refer to
00064        system_stm32f10x.c file
00065      */
00066
00067   /* Initialize LED1 and Key Button mounted on STM3210X-EVAL board */
00068   STM_EVAL_LEDInit(LED1);
00069   STM_EVAL_LEDInit(LED2);
00070   STM_EVAL_PBInit(BUTTON_KEY, BUTTON_MODE_EXTI);
00071
00072   /* Setup SysTick Timer for 1 msec interrupts  */
00073   if (SysTick_Config(SystemCoreClock / 1000))
00074   {
00075     /* Capture error */
00076     while (1);
00077   }
00078
00079
00080   /* Check if the system has resumed from IWDG reset */
00081   if (RCC_GetFlagStatus(RCC_FLAG_IWDGRST) != RESET)
00082   {
00083     /* IWDGRST flag set */
00084     /* Turn on LED1 */
00085     STM_EVAL_LEDOn(LED1);
00086
00087     /* Clear reset flags */
00088     RCC_ClearFlag();
00089   }
00090   else
00091   {
00092     /* IWDGRST flag is not set */
00093     /* Turn off LED1 */
00094     STM_EVAL_LEDOff(LED1);
00095   }
00096
00097 #ifdef LSI_TIM_MEASURE
00098   /* Enable the LSI OSC */
00099   RCC_LSICmd(ENABLE);
00100
00101   /* Wait till LSI is ready */
00102   while (RCC_GetFlagStatus(RCC_FLAG_LSIRDY) == RESET)
00103   {}
00104
00105   /* TIM Configuration -------------------------------------------------------*/
00106   TIM5_ConfigForLSI();
00107
00108   /* Wait until the TIM5 get 2 LSI edges */
00109   while(CaptureNumber != 2)
00110   {
00111   }
00112
00113   /* Disable TIM5 CC4 Interrupt Request */
00114   TIM_ITConfig(TIM5, TIM_IT_CC4, DISABLE);
00115 #endif
00116
00117   /* IWDG timeout equal to 250 ms (the timeout may varies due to LSI frequency
00118      dispersion) */
00119   /* Enable write access to IWDG_PR and IWDG_RLR registers */
00120   IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable);
00121
00122   /* IWDG counter clock: LSI/32 */
00123   IWDG_SetPrescaler(IWDG_Prescaler_32);
00124
00125   /* Set counter reload value to obtain 250ms IWDG TimeOut.
00126      Counter Reload Value = 250ms/IWDG counter clock period
00127                           = 250ms / (LSI/32)
00128                           = 0.25s / (LsiFreq/32)
00129                           = LsiFreq/(32 * 4)
00130                           = LsiFreq/128
00131    */
00132   IWDG_SetReload(LsiFreq/128);
00133
00134   /* Reload IWDG counter */
00135   IWDG_ReloadCounter();
00136
00137   /* Enable IWDG (the LSI oscillator will be enabled by hardware) */
00138   IWDG_Enable();
00139
00140   while (1)
00141   {
00142     /* Toggle LED2 */
00143     STM_EVAL_LEDToggle(LED2);
00144
00145     /* Insert 240 ms delay */
00146     Delay(240);
00147
00148     /* Reload IWDG counter */
00149     IWDG_ReloadCounter();
00150   }
00151 }
00152
00153 /**
00154   * @brief  Inserts a delay time.
00155   * @param  nTime: specifies the delay time length, in milliseconds.
00156   * @retval None
00157   */
00158 void Delay(__IO uint32_t nTime)
00159 {
00160   TimingDelay = nTime;
00161
00162   while(TimingDelay != 0);
00163 }
00164
00165 #ifdef LSI_TIM_MEASURE
00166 /**
00167   * @brief  Configures TIM5 to measure the LSI oscillator frequency.
00168   * @param  None
00169   * @retval None
00170   */
00171 void TIM5_ConfigForLSI(void)
00172 {
00173   NVIC_InitTypeDef NVIC_InitStructure;
00174   TIM_ICInitTypeDef  TIM_ICInitStructure;
00175
00176   /* Enable TIM5 clocks */
00177   RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM5, ENABLE);
00178
00179   /* Enable the TIM5 Interrupt */
00180   NVIC_InitStructure.NVIC_IRQChannel = TIM5_IRQn;
00181   NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
00182   NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
00183   NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
00184   NVIC_Init(&NVIC_InitStructure);
00185
00186   /* Configure TIM5 prescaler */
00187   TIM_PrescalerConfig(TIM5, 0, TIM_PSCReloadMode_Immediate);
00188
00189   /* Connect internally the TM5_CH4 Input Capture to the LSI clock output */
00190   GPIO_PinRemapConfig(GPIO_Remap_TIM5CH4_LSI, ENABLE);
00191
00192   /* TIM5 configuration: Input Capture mode ---------------------
00193      The LSI oscillator is connected to TIM5 CH4
00194      The Rising edge is used as active edge,
00195      The TIM5 CCR4 is used to compute the frequency value
00196   ------------------------------------------------------------ */
00197   TIM_ICInitStructure.TIM_Channel = TIM_Channel_4;
00198   TIM_ICInitStructure.TIM_ICPolarity = TIM_ICPolarity_Rising;
00199   TIM_ICInitStructure.TIM_ICSelection = TIM_ICSelection_DirectTI;
00200   TIM_ICInitStructure.TIM_ICPrescaler = TIM_ICPSC_DIV8;
00201   TIM_ICInitStructure.TIM_ICFilter = 0;
00202   TIM_ICInit(TIM5, &TIM_ICInitStructure);
00203
00204   /* TIM10 Counter Enable */
00205   TIM_Cmd(TIM5, ENABLE);
00206
00207   /* Reset the flags */
00208   TIM5->SR = 0;
00209
00210   /* Enable the CC4 Interrupt Request */
00211   TIM_ITConfig(TIM5, TIM_IT_CC4, ENABLE);
00212 }
00213 #endif
00214
00215 #ifdef  USE_FULL_ASSERT
00216
00217 /**
00218   * @brief  Reports the name of the source file and the source line number
00219   *         where the assert_param error has occurred.
00220   * @param  file: pointer to the source file name
00221   * @param  line: assert_param error line source number
00222   * @retval None
00223   */
00224 void assert_failed(uint8_t* file, uint32_t line)
00225 {
00226   /* User can add his own implementation to report the file name and line number,
00227      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00228
00229   /* Infinite loop */
00230   while (1)
00231   {}
00232 }
00233
00234 #endif
00235
00236 /**
00237   * @}
00238   */
00239
00240 /**
00241   * @}
00242   */
00243
00244 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_conf.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    IWDG/IWDG_Reset/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052 /* Exported types ------------------------------------------------------------*/
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Uncomment the line below to expanse the "assert_param" macro in the
00055    Standard Peripheral Library drivers code */
00056 /* #define USE_FULL_ASSERT    1 */
00057
00058 /* Exported macro ------------------------------------------------------------*/
00059 #ifdef  USE_FULL_ASSERT
00060
00061 /**
00062   * @brief  The assert_param macro is used for function's parameters check.
00063   * @param  expr: If expr is false, it calls assert_failed function which reports
00064   *         the name of the source file and the source line number of the call
00065   *         that failed. If expr is true, it returns no value.
00066   * @retval None
00067   */
00068   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00069 /* Exported functions ------------------------------------------------------- */
00070   void assert_failed(uint8_t* file, uint32_t line);
00071 #else
00072   #define assert_param(expr) ((void)0)
00073 #endif /* USE_FULL_ASSERT */
00074
00075 #endif /* __STM32F10x_CONF_H */
00076
00077 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_it.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    IWDG/IWDG_Reset/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and peripherals
00009   *          interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026 #include "stm32_eval.h"
00027
00028 /** @addtogroup STM32F10x_StdPeriph_Examples
00029   * @{
00030   */
00031
00032 /** @addtogroup IWDG_Reset
00033   * @{
00034   */
00035
00036 /* Private typedef -----------------------------------------------------------*/
00037 /* Private define ------------------------------------------------------------*/
00038 /* Private macro -------------------------------------------------------------*/
00039 /* Private variables ---------------------------------------------------------*/
00040 extern __IO uint32_t TimingDelay;
00041 __IO uint16_t IC1ReadValue1 = 0, IC1ReadValue2 = 0;
00042 __IO uint16_t CaptureNumber = 0;
00043 __IO uint32_t Capture = 0;
00044 extern uint32_t LsiFreq;
00045
00046 /* Private function prototypes -----------------------------------------------*/
00047 /* Private functions ---------------------------------------------------------*/
00048
00049 /******************************************************************************/
00050 /*            Cortex-M3 Processor Exceptions Handlers                         */
00051 /******************************************************************************/
00052
00053 /**
00054   * @brief  This function handles NMI exception.
00055   * @param  None
00056   * @retval None
00057   */
00058 void NMI_Handler(void)
00059 {
00060 }
00061
00062 /**
00063   * @brief  This function handles Hard Fault exception.
00064   * @param  None
00065   * @retval None
00066   */
00067 void HardFault_Handler(void)
00068 {
00069   /* Go to infinite loop when Hard Fault exception occurs */
00070   while (1)
00071   {}
00072 }
00073
00074 /**
00075   * @brief  This function handles Memory Manage exception.
00076   * @param  None
00077   * @retval None
00078   */
00079 void MemManage_Handler(void)
00080 {
00081   /* Go to infinite loop when Memory Manage exception occurs */
00082   while (1)
00083   {}
00084 }
00085
00086 /**
00087   * @brief  This function handles Bus Fault exception.
00088   * @param  None
00089   * @retval None
00090   */
00091 void BusFault_Handler(void)
00092 {
00093   /* Go to infinite loop when Bus Fault exception occurs */
00094   while (1)
00095   {}
00096 }
00097
00098 /**
00099   * @brief  This function handles Usage Fault exception.
00100   * @param  None
00101   * @retval None
00102   */
00103 void UsageFault_Handler(void)
00104 {
00105   /* Go to infinite loop when Usage Fault exception occurs */
00106   while (1)
00107   {}
00108 }
00109
00110 /**
00111   * @brief  This function handles Debug Monitor exception.
00112   * @param  None
00113   * @retval None
00114   */
00115 void DebugMon_Handler(void)
00116 {
00117 }
00118
00119 /**
00120   * @brief  This function handles SVCall exception.
00121   * @param  None
00122   * @retval None
00123   */
00124 void SVC_Handler(void)
00125 {
00126 }
00127
00128 /**
00129   * @brief  This function handles PendSV_Handler exception.
00130   * @param  None
00131   * @retval None
00132   */
00133 void PendSV_Handler(void)
00134 {
00135 }
00136
00137 /**
00138   * @brief  This function handles SysTick Handler.
00139   * @param  None
00140   * @retval None
00141   */
00142 void SysTick_Handler(void)
00143 {
00144   TimingDelay--;
00145 }
00146
00147 /******************************************************************************/
00148 /*            STM32F10x Peripherals Interrupt Handlers                        */
00149 /******************************************************************************/
00150
00151 /**
00152   * @brief  This function handles External lines 9 to 5 interrupt request.
00153   * @param  None
00154   * @retval None
00155   */
00156 void EXTI9_5_IRQHandler(void)
00157 {
00158   if (EXTI_GetITStatus(KEY_BUTTON_EXTI_LINE) != RESET)
00159   {
00160     /* Clear the Key Button EXTI Line Pending Bit */
00161     EXTI_ClearITPendingBit(KEY_BUTTON_EXTI_LINE);
00162
00163     /* As the following address is invalid (not mapped), a Hardfault exception
00164           will be generated with an infinite loop and when the IWDG counter reaches 0
00165     the IWDG reset occurs */
00166           *(__IO uint32_t *) 0x000000FF = 0xFF;
00167   }
00168 }
00169
00170 /**
00171   * @brief  This function handles TIM5 global interrupt request.
00172   * @param  None
00173   * @retval None
00174   */
00175 void TIM5_IRQHandler(void)
00176 {
00177   if (TIM_GetITStatus(TIM5, TIM_IT_CC4) != RESET)
00178   {
00179     if(CaptureNumber == 0)
00180     {
00181       /* Get the Input Capture value */
00182       IC1ReadValue1 = TIM_GetCapture4(TIM5);
00183     }
00184     else if(CaptureNumber == 1)
00185     {
00186       /* Get the Input Capture value */
00187       IC1ReadValue2 = TIM_GetCapture4(TIM5);
00188
00189       /* Capture computation */
00190       if (IC1ReadValue2 > IC1ReadValue1)
00191       {
00192         Capture = (IC1ReadValue2 - IC1ReadValue1);
00193       }
00194       else
00195       {
00196         Capture = ((0xFFFF - IC1ReadValue1) + IC1ReadValue2);
00197       }
00198       /* Frequency computation */
00199       LsiFreq = (uint32_t) SystemCoreClock / Capture;
00200       LsiFreq *= 8;
00201     }
00202
00203     CaptureNumber++;
00204
00205     /* Clear TIM5 Capture compare interrupt pending bit */
00206     TIM_ClearITPendingBit(TIM5, TIM_IT_CC4);
00207   }
00208 }
00209
00210 /******************************************************************************/
00211 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00212 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00213 /*  available peripheral interrupt handler's name please refer to the startup */
00214 /*  file (startup_stm32f10x_xx.s).                                            */
00215 /******************************************************************************/
00216
00217 /**
00218   * @brief  This function handles PPP interrupt request.
00219   * @param  None
00220   * @retval None
00221   */
00222 /*void PPP_IRQHandler(void)
00223 {
00224 }*/
00225
00226 /**
00227   * @}
00228   */
00229 /**
00230   * @}
00231   */
00232
00233 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_it.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    IWDG/IWDG_Reset/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043 void EXTI9_5_IRQHandler(void);
00044 void TIM5_IRQHandler(void);
00045
00046 #endif /* __STM32F10x_IT_H */
00047
00048 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/main.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    Lib_DEBUG/RunTime_Check/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x.h"
00024 #include "stm32f10x_ip_dbg.h"
00025 #include "stm32_eval.h"
00026 #include <stdio.h>
00027
00028 /** @addtogroup STM32F10x_StdPeriph_Examples
00029   * @{
00030   */
00031
00032 /** @addtogroup Lib_DEBUG_RunTime_Check
00033   * @{
00034   */
00035
00036 /* Private typedef -----------------------------------------------------------*/
00037 /* Private define ------------------------------------------------------------*/
00038 /* Private macro -------------------------------------------------------------*/
00039 /* Private variables ---------------------------------------------------------*/
00040  USART_InitTypeDef USART_InitStructure;
00041
00042 /* Private function prototypes -----------------------------------------------*/
00043 #ifdef __GNUC__
00044   /* With GCC/RAISONANCE, small printf (option LD Linker->Libraries->Small printf
00045      set to 'Yes') calls __io_putchar() */
00046   #define PUTCHAR_PROTOTYPE int __io_putchar(int ch)
00047 #else
00048   #define PUTCHAR_PROTOTYPE int fputc(int ch, FILE *f)
00049 #endif /* __GNUC__ */
00050
00051 /* Private functions ---------------------------------------------------------*/
00052
00053 /**
00054   * @brief  Main program.
00055   * @param  None
00056   * @retval None
00057   */
00058 int main(void)
00059 {
00060   /*!< At this stage the microcontroller clock setting is already configured,
00061        this is done through SystemInit() function which is called from startup
00062        file (startup_stm32f10x_xx.s) before to branch to application main.
00063        To reconfigure the default setting of SystemInit() function, refer to
00064        system_stm32f10x.c file
00065      */
00066
00067   GPIO_InitTypeDef GPIOA_InitStructure;
00068
00069   /* USARTx configured as follow:
00070         - BaudRate = 115200 baud
00071         - Word Length = 8 Bits
00072         - One Stop Bit
00073         - No parity
00074         - Hardware flow control disabled (RTS and CTS signals)
00075         - Receive and transmit enabled
00076   */
00077   USART_InitStructure.USART_BaudRate = 115200;
00078   USART_InitStructure.USART_WordLength = USART_WordLength_8b;
00079   USART_InitStructure.USART_StopBits = USART_StopBits_1;
00080   USART_InitStructure.USART_Parity = USART_Parity_No;
00081   USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
00082   USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
00083
00084   STM_EVAL_COMInit(COM1, &USART_InitStructure);
00085
00086   /* Initialize all peripherals pointers */
00087   debug();
00088
00089   printf("\r\n STM32F10x Firmware Library compiled with FULL ASSERT function... \n\r");
00090   printf("...Run-time checking enabled  \n\r");
00091
00092   /* Simulate wrong parameter passed to library function ---------------------*/
00093   /* To enable SPI1 clock, RCC_APB2PeriphClockCmd function must be used and
00094      not RCC_APB1PeriphClockCmd */
00095   RCC_APB1PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE);
00096
00097   /* Some member of GPIOA_InitStructure structure are not initialized */
00098   GPIOA_InitStructure.GPIO_Pin = GPIO_Pin_6;
00099   GPIOA_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
00100   /* GPIOA_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; */
00101   GPIO_Init(GPIOA, &GPIOA_InitStructure);
00102
00103   while (1)
00104   {
00105   }
00106
00107 }
00108
00109 #ifdef  USE_FULL_ASSERT
00110
00111 /**
00112   * @brief  Reports the name of the source file and the source line number
00113   *         where the assert_param error has occurred.
00114   * @param  file: pointer to the source file name
00115   * @param  line: assert_param error line source number
00116   * @retval None
00117   */
00118 void assert_failed(uint8_t* file, uint32_t line)
00119 {
00120   /* User can add his own implementation to report the file name and line number */
00121
00122   printf("\n\r Wrong parameter value detected on\r\n");
00123   printf("       file  %s\r\n", file);
00124   printf("       line  %d\r\n", line);
00125
00126   /* Infinite loop */
00127   /* while (1)
00128   {
00129   } */
00130 }
00131
00132 #endif
00133
00134 /**
00135   * @brief  Retargets the C library printf function to the USART.
00136   * @param  None
00137   * @retval None
00138   */
00139 PUTCHAR_PROTOTYPE
00140 {
00141   /* Place your implementation of fputc here */
00142   /* e.g. write a character to the USART */
00143   USART_SendData(EVAL_COM1, (uint8_t) ch);
00144
00145   /* Loop until the end of transmission */
00146   while(USART_GetFlagStatus(EVAL_COM1, USART_FLAG_TC) == RESET)
00147   {
00148   }
00149
00150   return ch;
00151 }
00152
00153 /**
00154   * @}
00155   */
00156
00157 /**
00158   * @}
00159   */
00160
00161 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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  • RunTime_Check

STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/stm32f10x_conf.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    Lib_DEBUG/RunTime_Check/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052 /* Exported types ------------------------------------------------------------*/
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Uncomment the line below to expanse the "assert_param" macro in the
00055    Standard Peripheral Library drivers code */
00056 #define USE_FULL_ASSERT    1
00057
00058 /* Exported macro ------------------------------------------------------------*/
00059 #ifdef  USE_FULL_ASSERT
00060
00061 /**
00062   * @brief  The assert_param macro is used for function's parameters check.
00063   * @param  expr: If expr is false, it calls assert_failed function which reports
00064   *         the name of the source file and the source line number of the call
00065   *         that failed. If expr is true, it returns no value.
00066   * @retval None
00067   */
00068   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00069 /* Exported functions ------------------------------------------------------- */
00070   void assert_failed(uint8_t* file, uint32_t line);
00071 #else
00072   #define assert_param(expr) ((void)0)
00073 #endif /* USE_FULL_ASSERT */
00074
00075 #endif /* __STM32F10x_CONF_H */
00076
00077 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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  • RunTime_Check

STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/stm32f10x_it.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    Lib_DEBUG/RunTime_Check/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *         This file provides template for all exceptions handler and
00009   *         peripherals interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026
00027 /** @addtogroup STM32F10x_StdPeriph_Examples
00028   * @{
00029   */
00030
00031 /** @addtogroup Lib_DEBUG_RunTime_Check
00032   * @{
00033   */
00034
00035 /* Private typedef -----------------------------------------------------------*/
00036 /* Private define ------------------------------------------------------------*/
00037 /* Private macro -------------------------------------------------------------*/
00038 /* Private variables ---------------------------------------------------------*/
00039 /* Private function prototypes -----------------------------------------------*/
00040 /* Private functions ---------------------------------------------------------*/
00041
00042 /******************************************************************************/
00043 /*            Cortex-M3 Processor Exceptions Handlers                         */
00044 /******************************************************************************/
00045
00046 /**
00047   * @brief  This function handles NMI exception.
00048   * @param  None
00049   * @retval None
00050   */
00051 void NMI_Handler(void)
00052 {
00053 }
00054
00055 /**
00056   * @brief  This function handles Hard Fault exception.
00057   * @param  None
00058   * @retval None
00059   */
00060 void HardFault_Handler(void)
00061 {
00062   /* Go to infinite loop when Hard Fault exception occurs */
00063   while (1)
00064   {
00065   }
00066 }
00067
00068 /**
00069   * @brief  This function handles Memory Manage exception.
00070   * @param  None
00071   * @retval None
00072   */
00073 void MemManage_Handler(void)
00074 {
00075   /* Go to infinite loop when Memory Manage exception occurs */
00076   while (1)
00077   {
00078   }
00079 }
00080
00081 /**
00082   * @brief  This function handles Bus Fault exception.
00083   * @param  None
00084   * @retval None
00085   */
00086 void BusFault_Handler(void)
00087 {
00088   /* Go to infinite loop when Bus Fault exception occurs */
00089   while (1)
00090   {
00091   }
00092 }
00093
00094 /**
00095   * @brief  This function handles Usage Fault exception.
00096   * @param  None
00097   * @retval None
00098   */
00099 void UsageFault_Handler(void)
00100 {
00101   /* Go to infinite loop when Usage Fault exception occurs */
00102   while (1)
00103   {
00104   }
00105 }
00106
00107 /**
00108   * @brief  This function handles SVCall exception.
00109   * @param  None
00110   * @retval None
00111   */
00112 void SVC_Handler(void)
00113 {
00114 }
00115
00116 /**
00117   * @brief  This function handles Debug Monitor exception.
00118   * @param  None
00119   * @retval None
00120   */
00121 void DebugMon_Handler(void)
00122 {
00123 }
00124
00125 /**
00126   * @brief  This function handles PendSV_Handler exception.
00127   * @param  None
00128   * @retval None
00129   */
00130 void PendSV_Handler(void)
00131 {
00132 }
00133
00134 /**
00135   * @brief  This function handles SysTick Handler.
00136   * @param  None
00137   * @retval None
00138   */
00139 void SysTick_Handler(void)
00140 {
00141 }
00142
00143 /******************************************************************************/
00144 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00145 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00146 /*  available peripheral interrupt handler's name please refer to the startup */
00147 /*  file (startup_stm32f10x_xx.s).                                            */
00148 /******************************************************************************/
00149
00150 /**
00151   * @brief  This function handles PPP interrupt request.
00152   * @param  None
00153   * @retval None
00154   */
00155 /*void PPP_IRQHandler(void)
00156 {
00157 }*/
00158
00159 /**
00160   * @}
00161   */
00162
00163 /**
00164   * @}
00165   */
00166
00167 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/stm32f10x_it.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    Lib_DEBUG/RunTime_Check/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043
00044 #endif /* __STM32F10x_IT_H */
00045
00046 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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  • DMA_WFIMode

STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/main.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    NVIC/DMA_WFIMode/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x.h"
00024 #include "stm32_eval.h"
00025
00026 /** @addtogroup STM32F10x_StdPeriph_Examples
00027   * @{
00028   */
00029
00030 /** @addtogroup NVIC_DMA_WFIMode
00031   * @{
00032   */
00033
00034 /* Private typedef -----------------------------------------------------------*/
00035 /* Private define ------------------------------------------------------------*/
00036 #ifdef USE_STM3210C_EVAL
00037 #define USARTy_DR_Address    0x40004404
00038 #define USARTy_DMA1_Channel  DMA1_Channel6
00039 #define USARTy_DMA1_IRQn     DMA1_Channel6_IRQn
00040 #else
00041 #define USARTy_DR_Address    0x40013804
00042 #define USARTy_DMA1_Channel  DMA1_Channel5
00043 #define USARTy_DMA1_IRQn     DMA1_Channel5_IRQn
00044 #endif
00045
00046 /* Private macro -------------------------------------------------------------*/
00047 /* Private variables ---------------------------------------------------------*/
00048 NVIC_InitTypeDef  NVIC_InitStructure;
00049 USART_InitTypeDef  USART_InitStructure;
00050 DMA_InitTypeDef  DMA_InitStructure;
00051 __IO uint32_t LowPowerMode = 0;
00052 uint16_t DST_Buffer[10]= {0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
00053
00054 /* Private function prototypes -----------------------------------------------*/
00055 void RCC_Configuration(void);
00056 void DMA_Configuration(void);
00057 uint8_t Buffercmp16(uint16_t* pBuffer1, uint16_t* pBuffer2, uint16_t BufferLength);
00058 void Delay(__IO uint32_t nCount);
00059
00060 /* Private functions ---------------------------------------------------------*/
00061
00062 /**
00063   * @brief  Main program.
00064   * @param  None
00065   * @retval None
00066   */
00067 int main(void)
00068 {
00069   /*!< At this stage the microcontroller clock setting is already configured,
00070        this is done through SystemInit() function which is called from startup
00071        file (startup_stm32f10x_xx.s) before to branch to application main.
00072        To reconfigure the default setting of SystemInit() function, refer to
00073        system_stm32f10x.c file
00074      */
00075
00076   /* Configure the system clocks */
00077   RCC_Configuration();
00078
00079   /* Initialize Leds and Key Button mounted on STM3210X-EVAL board */
00080   STM_EVAL_LEDInit(LED1);
00081   STM_EVAL_LEDInit(LED2);
00082   STM_EVAL_LEDInit(LED3);
00083   STM_EVAL_LEDInit(LED4);
00084   STM_EVAL_PBInit(BUTTON_KEY, BUTTON_MODE_EXTI);
00085
00086   /* Configures the DMA Channel */
00087   DMA_Configuration();
00088
00089 /* EVAL_COM1 configuration ---------------------------------------------------*/
00090   /* EVAL_COM1 configured as follow:
00091         - BaudRate = 115200 baud
00092         - Word Length = 8 Bits
00093         - One Stop Bit
00094         - No parity
00095         - Hardware flow control disabled (RTS and CTS signals)
00096         - Receive and transmit enabled
00097   */
00098   USART_InitStructure.USART_BaudRate = 115200;
00099   USART_InitStructure.USART_WordLength = USART_WordLength_8b;
00100   USART_InitStructure.USART_StopBits = USART_StopBits_1;
00101   USART_InitStructure.USART_Parity = USART_Parity_No;
00102   USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
00103   USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
00104
00105   STM_EVAL_COMInit(COM1, &USART_InitStructure);
00106   USART_DMACmd(EVAL_COM1, USART_DMAReq_Rx, ENABLE);
00107
00108   NVIC_PriorityGroupConfig(NVIC_PriorityGroup_1);
00109
00110   /* Enable the USARTy_DMA1_IRQn Interrupt */
00111   NVIC_InitStructure.NVIC_IRQChannel = USARTy_DMA1_IRQn;
00112   NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
00113   NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
00114   NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
00115   NVIC_Init(&NVIC_InitStructure);
00116
00117   /* Enable the EXTI9_5  Interrupt */
00118   NVIC_InitStructure.NVIC_IRQChannel = EXTI9_5_IRQn;
00119   NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
00120   NVIC_Init(&NVIC_InitStructure);
00121
00122   while (1)
00123   {
00124     if(LowPowerMode == 1)
00125     {
00126
00127       STM_EVAL_LEDOff(LED2);
00128       STM_EVAL_LEDOff(LED3);
00129
00130       /* Request to enter WFI mode */
00131       __WFI();
00132       LowPowerMode = 0;
00133     }
00134
00135     Delay(0xFFFFF);
00136     STM_EVAL_LEDToggle(LED1);
00137   }
00138 }
00139
00140 /**
00141   * @brief  Configures the different system clocks
00142   * @param  None
00143   * @retval None
00144   */
00145 void RCC_Configuration(void)
00146 {
00147   /* DMA1 clock enable */
00148   RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE);
00149 }
00150
00151 /**
00152   * @brief  Configures the used DMA Channel.
00153   * @param  None
00154   * @retval None
00155   */
00156 void DMA_Configuration(void)
00157 {
00158   DMA_InitTypeDef  DMA_InitStructure;
00159
00160   /* USARTy_DMA1_Channel Config */
00161   DMA_DeInit(USARTy_DMA1_Channel);
00162   DMA_InitStructure.DMA_PeripheralBaseAddr = USARTy_DR_Address;
00163   DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)DST_Buffer;
00164   DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
00165   DMA_InitStructure.DMA_BufferSize = 10;
00166   DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
00167   DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
00168   DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord;
00169   DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
00170   DMA_InitStructure.DMA_Mode = DMA_Mode_Circular;
00171   DMA_InitStructure.DMA_Priority = DMA_Priority_High;
00172   DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
00173   DMA_Init(USARTy_DMA1_Channel, &DMA_InitStructure);
00174
00175   /* Enable USARTy_DMA1_Channel Transfer complete interrupt */
00176   DMA_ITConfig(USARTy_DMA1_Channel, DMA_IT_TC, ENABLE);
00177
00178   /* USARTy_DMA1_Channel enable */
00179   DMA_Cmd(USARTy_DMA1_Channel, ENABLE);
00180 }
00181
00182 /**
00183   * @brief  Compares two buffers.
00184   * @param  pBuffer1, pBuffer2: buffers to be compared.
00185   * @param  BufferLength: buffer's length
00186   * @retval 0: pBuffer1 identical to pBuffer2
00187   *         1: pBuffer1 differs from pBuffer2
00188   */
00189 uint8_t Buffercmp16(uint16_t* pBuffer1, uint16_t* pBuffer2, uint16_t BufferLength)
00190 {
00191   while(BufferLength--)
00192   {
00193     if(*pBuffer1 != *pBuffer2)
00194     {
00195       return 1;
00196     }
00197
00198     pBuffer1++;
00199     pBuffer2++;
00200   }
00201   return 0;
00202 }
00203
00204 /**
00205   * @brief  Inserts a delay time.
00206   * @param  nCount: specifies the delay time length.
00207   * @retval None
00208   */
00209 void Delay(__IO uint32_t nCount)
00210 {
00211   for(; nCount != 0; nCount--);
00212 }
00213
00214 #ifdef  USE_FULL_ASSERT
00215
00216 /**
00217   * @brief  Reports the name of the source file and the source line number
00218   *         where the assert_param error has occurred.
00219   * @param  file: pointer to the source file name
00220   * @param  line: assert_param error line source number
00221   * @retval None
00222   */
00223 void assert_failed(uint8_t* file, uint32_t line)
00224 {
00225   /* User can add his own implementation to report the file name and line number,
00226      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00227
00228   /* Infinite loop */
00229   while (1)
00230   {
00231   }
00232 }
00233
00234 #endif
00235
00236 /**
00237   * @}
00238   */
00239
00240 /**
00241   * @}
00242   */
00243
00244 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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  • DMA_WFIMode

STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_conf.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    NVIC/DMA_WFIMode/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052 /* Exported types ------------------------------------------------------------*/
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Uncomment the line below to expanse the "assert_param" macro in the
00055    Standard Peripheral Library drivers code */
00056 /* #define USE_FULL_ASSERT    1 */
00057
00058 /* Exported macro ------------------------------------------------------------*/
00059 #ifdef  USE_FULL_ASSERT
00060
00061 /**
00062   * @brief  The assert_param macro is used for function's parameters check.
00063   * @param  expr: If expr is false, it calls assert_failed function which reports
00064   *         the name of the source file and the source line number of the call
00065   *         that failed. If expr is true, it returns no value.
00066   * @retval None
00067   */
00068   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00069 /* Exported functions ------------------------------------------------------- */
00070   void assert_failed(uint8_t* file, uint32_t line);
00071 #else
00072   #define assert_param(expr) ((void)0)
00073 #endif /* USE_FULL_ASSERT */
00074
00075 #endif /* __STM32F10x_CONF_H */
00076
00077 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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  • DMA_WFIMode

STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_it.c

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00001 /**
00002   ******************************************************************************
00003   * @file    NVIC/DMA_WFIMode/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and peripherals
00009   *          interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026 #include "stm32_eval.h"
00027
00028 /** @addtogroup STM32F10x_StdPeriph_Examples
00029   * @{
00030   */
00031
00032 /** @addtogroup NVIC_DMA_WFIMode
00033   * @{
00034   */
00035
00036 /* Private typedef -----------------------------------------------------------*/
00037 /* Private define ------------------------------------------------------------*/
00038 /* Private macro -------------------------------------------------------------*/
00039 /* Private variables ---------------------------------------------------------*/
00040 uint8_t TestStatus = 0;
00041 uint16_t SRC_Buffer[10] = {0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39};
00042 extern uint16_t DST_Buffer[10];
00043 extern __IO uint32_t LowPowerMode;
00044 extern uint8_t Buffercmp16(uint16_t*, uint16_t*, uint16_t);
00045 extern void DMA_Configuration(void);
00046
00047 /* Private function prototypes -----------------------------------------------*/
00048 /* Private functions ---------------------------------------------------------*/
00049
00050 /******************************************************************************/
00051 /*            Cortex-M3 Processor Exceptions Handlers                         */
00052 /******************************************************************************/
00053
00054 /**
00055   * @brief  This function handles NMI exception.
00056   * @param  None
00057   * @retval None
00058   */
00059 void NMI_Handler(void)
00060 {
00061 }
00062
00063 /**
00064   * @brief  This function handles Hard Fault exception.
00065   * @param  None
00066   * @retval None
00067   */
00068 void HardFault_Handler(void)
00069 {
00070   /* Go to infinite loop when Hard Fault exception occurs */
00071   while (1)
00072   {
00073   }
00074 }
00075
00076 /**
00077   * @brief  This function handles Memory Manage exception.
00078   * @param  None
00079   * @retval None
00080   */
00081 void MemManage_Handler(void)
00082 {
00083   /* Go to infinite loop when Memory Manage exception occurs */
00084   while (1)
00085   {
00086   }
00087 }
00088
00089 /**
00090   * @brief  This function handles Bus Fault exception.
00091   * @param  None
00092   * @retval None
00093   */
00094 void BusFault_Handler(void)
00095 {
00096   /* Go to infinite loop when Bus Fault exception occurs */
00097   while (1)
00098   {
00099   }
00100 }
00101
00102 /**
00103   * @brief  This function handles Usage Fault exception.
00104   * @param  None
00105   * @retval None
00106   */
00107 void UsageFault_Handler(void)
00108 {
00109   /* Go to infinite loop when Usage Fault exception occurs */
00110   while (1)
00111   {
00112   }
00113 }
00114
00115 /**
00116   * @brief  This function handles SVCall exception.
00117   * @param  None
00118   * @retval None
00119   */
00120 void SVC_Handler(void)
00121 {
00122 }
00123
00124 /**
00125   * @brief  This function handles Debug Monitor exception.
00126   * @param  None
00127   * @retval None
00128   */
00129 void DebugMon_Handler(void)
00130 {
00131 }
00132
00133 /**
00134   * @brief  This function handles PendSV_Handler exception.
00135   * @param  None
00136   * @retval None
00137   */
00138 void PendSV_Handler(void)
00139 {
00140 }
00141
00142 /**
00143   * @brief  This function handles SysTick Handler.
00144   * @param  None
00145   * @retval None
00146   */
00147 void SysTick_Handler(void)
00148 {
00149 }
00150
00151 /******************************************************************************/
00152 /*            STM32F10x Peripherals Interrupt Handlers                        */
00153 /******************************************************************************/
00154
00155 /**
00156   * @brief  This function handles DMA1 Channel 5 interrupt request.
00157   * @param  None
00158   * @retval None
00159   */
00160 void DMA1_Channel5_IRQHandler(void)
00161 {
00162   if(DMA_GetITStatus(DMA1_IT_TC5))
00163   {
00164     DMA_ClearITPendingBit(DMA1_IT_GL5);
00165
00166     /* Check the received buffer */
00167     TestStatus = Buffercmp16(SRC_Buffer, DST_Buffer, 10);
00168
00169     if(TestStatus == 0)
00170     {
00171       STM_EVAL_LEDToggle(LED2);
00172     }
00173     else
00174     {
00175       STM_EVAL_LEDToggle(LED3);
00176     }
00177   }
00178 }
00179
00180 /**
00181   * @brief  This function handles DMA1 Channel 6 interrupt request.
00182   * @param  None
00183   * @retval None
00184   */
00185 void DMA1_Channel6_IRQHandler(void)
00186 {
00187   if(DMA_GetITStatus(DMA1_IT_TC6))
00188   {
00189     DMA_ClearITPendingBit(DMA1_IT_GL6);
00190
00191     /* Check the received buffer */
00192     TestStatus = Buffercmp16(SRC_Buffer, DST_Buffer, 10);
00193
00194     if(TestStatus == 0)
00195     {
00196       STM_EVAL_LEDToggle(LED2);
00197     }
00198     else
00199     {
00200       STM_EVAL_LEDToggle(LED3);
00201     }
00202   }
00203 }
00204
00205 /**
00206   * @brief  This function handles External lines 9 to 5 interrupt request.
00207   * @param  None
00208   * @retval None
00209   */
00210 void EXTI9_5_IRQHandler(void)
00211 {
00212   if(EXTI_GetITStatus(KEY_BUTTON_EXTI_LINE) != RESET)
00213   {
00214     EXTI_ClearITPendingBit(KEY_BUTTON_EXTI_LINE);
00215
00216     LowPowerMode = 1;
00217   }
00218 }
00219
00220 /******************************************************************************/
00221 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00222 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00223 /*  available peripheral interrupt handler's name please refer to the startup */
00224 /*  file (startup_stm32f10x_xx.s).                                            */
00225 /******************************************************************************/
00226
00227 /**
00228   * @brief  This function handles PPP interrupt request.
00229   * @param  None
00230   * @retval None
00231   */
00232 /*void PPP_IRQHandler(void)
00233 {
00234 }*/
00235
00236 /**
00237   * @}
00238   */
00239
00240 /**
00241   * @}
00242   */
00243
00244 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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  • DMA_WFIMode

STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_it.h

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00001 /**
00002   ******************************************************************************
00003   * @file    NVIC/DMA_WFIMode/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043 void DMA1_Channel5_IRQHandler(void);
00044 void DMA1_Channel6_IRQHandler(void);
00045 void EXTI9_5_IRQHandler(void);
00046
00047 #endif /* __STM32F10x_IT_H */
00048
00049 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/main.c

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00001 /**
00002   ******************************************************************************
00003   * @file    NVIC/IRQ_Mask/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x.h"
00024 #include "stm32_eval.h"
00025
00026 /** @addtogroup STM32F10x_StdPeriph_Examples
00027   * @{
00028   */
00029
00030 /** @addtogroup IRQ_Mask
00031   * @{
00032   */
00033
00034 /* Private typedef -----------------------------------------------------------*/
00035 /* Private define ------------------------------------------------------------*/
00036 /* Private macro -------------------------------------------------------------*/
00037 /* Private variables ---------------------------------------------------------*/
00038 /* Private function prototypes -----------------------------------------------*/
00039 void TIM_Config(void);
00040
00041 /* Private functions ---------------------------------------------------------*/
00042
00043 /**
00044   * @brief   Main program.
00045   * @param  None
00046   * @retval None
00047   */
00048 int main(void)
00049 {
00050   /*!< At this stage the microcontroller clock setting is already configured,
00051        this is done through SystemInit() function which is called from startup
00052        file (startup_stm32f10x_xx.s) before to branch to application main.
00053        To reconfigure the default setting of SystemInit() function, refer to
00054        system_stm32f10x.c file
00055      */
00056
00057   /* Initialize Leds mounted on STM3210X-EVAL board */
00058   STM_EVAL_LEDInit(LED1);
00059   STM_EVAL_LEDInit(LED2);
00060   STM_EVAL_LEDInit(LED3);
00061   STM_EVAL_LEDInit(LED4);
00062
00063   /* Initialize the KEY and WAKEUP buttons mounted on STM3210X-EVAL board */
00064   STM_EVAL_PBInit(BUTTON_KEY, BUTTON_MODE_GPIO);
00065   STM_EVAL_PBInit(BUTTON_WAKEUP, BUTTON_MODE_EXTI);
00066
00067   /* TIM configuration -------------------------------------------------------*/
00068   TIM_Config();
00069
00070   while (1)
00071   {
00072     /* Wait until KEY button is pressed. */
00073     while(STM_EVAL_PBGetState(BUTTON_KEY) == RESET)
00074     {
00075     }
00076     while(STM_EVAL_PBGetState(BUTTON_KEY) != RESET)
00077     {
00078     }
00079
00080     /* This instruction raises the execution priority to 0. This prevents all
00081        exceptions with configurable priority from activating, other than through
00082        the HardFault fault escalation mechanism. */
00083     __disable_irq();
00084
00085     /* Turn LED4 ON */
00086     STM_EVAL_LEDOn(LED4);
00087
00088     /* Wait until KEY button is pressed. */
00089     while(STM_EVAL_PBGetState(BUTTON_KEY) == RESET)
00090     {
00091     }
00092     while(STM_EVAL_PBGetState(BUTTON_KEY) != RESET)
00093     {
00094     }
00095
00096     /* This instruction will allow all exceptions with configurable priority to
00097        be activated. */
00098     __enable_irq();
00099
00100     /* Turn LED4 OFF */
00101     STM_EVAL_LEDOff(LED4);
00102   }
00103 }
00104
00105 /**
00106   * @brief  Configures the used Timers.
00107   * @param  None
00108   * @retval None
00109   */
00110 void TIM_Config(void)
00111 {
00112   TIM_TimeBaseInitTypeDef  TIM_TimeBaseStructure;
00113   TIM_OCInitTypeDef  TIM_OCInitStructure;
00114   NVIC_InitTypeDef  NVIC_InitStructure;
00115
00116   /* Enable TIM2, TIM3 and TIM4 clocks */
00117   RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2 | RCC_APB1Periph_TIM3 |
00118                          RCC_APB1Periph_TIM4, ENABLE);
00119
00120   /* TIM2 configuration */
00121   TIM_TimeBaseStructure.TIM_Period = 0x4AF;
00122   TIM_TimeBaseStructure.TIM_Prescaler = ((SystemCoreClock/1200) - 1);
00123   TIM_TimeBaseStructure.TIM_ClockDivision = 0x0;
00124   TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
00125   TIM_TimeBaseInit(TIM2, &TIM_TimeBaseStructure);
00126   TIM_OCStructInit(&TIM_OCInitStructure);
00127
00128   /* Output Compare Timing Mode configuration: Channel1 */
00129   TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_Timing;
00130   TIM_OCInitStructure.TIM_Pulse = 0x0;
00131   TIM_OC1Init(TIM2, &TIM_OCInitStructure);
00132
00133   /* TIM3 configuration */
00134   TIM_TimeBaseStructure.TIM_Period = 0x95F;
00135   TIM_TimeBaseInit(TIM3, &TIM_TimeBaseStructure);
00136
00137   /* Output Compare Timing Mode configuration: Channel1 */
00138   TIM_OC1Init(TIM3, &TIM_OCInitStructure);
00139
00140   /* TIM4 configuration */
00141   TIM_TimeBaseStructure.TIM_Period = 0xE0F;
00142   TIM_TimeBaseInit(TIM4, &TIM_TimeBaseStructure);
00143
00144   /* Output Compare Timing Mode configuration: Channel1 */
00145   TIM_OC1Init(TIM4, &TIM_OCInitStructure);
00146
00147   /* Immediate load of TIM2,TIM3 and TIM4 Precaler values */
00148   TIM_PrescalerConfig(TIM2, ((SystemCoreClock/1200) - 1), TIM_PSCReloadMode_Immediate);
00149   TIM_PrescalerConfig(TIM3, ((SystemCoreClock/1200) - 1), TIM_PSCReloadMode_Immediate);
00150   TIM_PrescalerConfig(TIM4, ((SystemCoreClock/1200) - 1), TIM_PSCReloadMode_Immediate);
00151
00152   /* Clear TIM2, TIM3 and TIM4 update pending flags */
00153   TIM_ClearFlag(TIM2, TIM_FLAG_Update);
00154   TIM_ClearFlag(TIM3, TIM_FLAG_Update);
00155   TIM_ClearFlag(TIM4, TIM_FLAG_Update);
00156
00157   /* Configure two bits for preemption priority */
00158   NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);
00159
00160   /* Enable the TIM2 Interrupt */
00161   NVIC_InitStructure.NVIC_IRQChannel = TIM2_IRQn;
00162   NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
00163   NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
00164   NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
00165   NVIC_Init(&NVIC_InitStructure);
00166
00167   /* Enable the TIM3 Interrupt */
00168   NVIC_InitStructure.NVIC_IRQChannel = TIM3_IRQn;
00169   NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
00170   NVIC_Init(&NVIC_InitStructure);
00171
00172   /* Enable the TIM4 Interrupt */
00173   NVIC_InitStructure.NVIC_IRQChannel = TIM4_IRQn;
00174   NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2;
00175   NVIC_Init(&NVIC_InitStructure);
00176
00177   /* Enable TIM2, TIM3 and TIM4 Update interrupts */
00178   TIM_ITConfig(TIM2, TIM_IT_Update, ENABLE);
00179   TIM_ITConfig(TIM3, TIM_IT_Update, ENABLE);
00180   TIM_ITConfig(TIM4, TIM_IT_Update, ENABLE);
00181
00182   /* TIM2, TIM3 and TIM4 enable counters */
00183   TIM_Cmd(TIM2, ENABLE);
00184   TIM_Cmd(TIM3, ENABLE);
00185   TIM_Cmd(TIM4, ENABLE);
00186 }
00187
00188
00189 #ifdef  USE_FULL_ASSERT
00190
00191 /**
00192   * @brief  Reports the name of the source file and the source line number
00193   *         where the assert_param error has occurred.
00194   * @param  file: pointer to the source file name
00195   * @param  line: assert_param error line source number
00196   * @retval None
00197   */
00198 void assert_failed(uint8_t* file, uint32_t line)
00199 {
00200   /* User can add his own implementation to report the file name and line number,
00201      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00202
00203   /* Infinite loop */
00204   while (1)
00205   {
00206   }
00207 }
00208
00209 #endif
00210
00211 /**
00212   * @}
00213   */
00214
00215 /**
00216   * @}
00217   */
00218
00219 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_conf.h

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00001 /**
00002   ******************************************************************************
00003   * @file    NVIC/IRQ_Mask/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052 /* Exported types ------------------------------------------------------------*/
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Uncomment the line below to expanse the "assert_param" macro in the
00055    Standard Peripheral Library drivers code */
00056 /* #define USE_FULL_ASSERT    1 */
00057
00058 /* Exported macro ------------------------------------------------------------*/
00059 #ifdef  USE_FULL_ASSERT
00060
00061 /**
00062   * @brief  The assert_param macro is used for function's parameters check.
00063   * @param  expr: If expr is false, it calls assert_failed function which reports
00064   *         the name of the source file and the source line number of the call
00065   *         that failed. If expr is true, it returns no value.
00066   * @retval None
00067   */
00068   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00069 /* Exported functions ------------------------------------------------------- */
00070   void assert_failed(uint8_t* file, uint32_t line);
00071 #else
00072   #define assert_param(expr) ((void)0)
00073 #endif /* USE_FULL_ASSERT */
00074
00075 #endif /* __STM32F10x_CONF_H */
00076
00077 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_it.c

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00001 /**
00002   ******************************************************************************
00003   * @file    NVIC/IRQ_Mask/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and
00009   *          peripherals interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026 #include "stm32_eval.h"
00027
00028 /** @addtogroup STM32F10x_StdPeriph_Examples
00029   * @{
00030   */
00031
00032 /** @addtogroup IRQ_Mask
00033   * @{
00034   */
00035
00036 /* Private typedef -----------------------------------------------------------*/
00037 /* Private define ------------------------------------------------------------*/
00038 /* Private macro -------------------------------------------------------------*/
00039 /* Private variables ---------------------------------------------------------*/
00040 __IO uint32_t index = 0;
00041
00042 /* Private function prototypes -----------------------------------------------*/
00043 /* Private functions ---------------------------------------------------------*/
00044
00045 /******************************************************************************/
00046 /*            Cortex-M3 Processor Exceptions Handlers                         */
00047 /******************************************************************************/
00048
00049 /**
00050   * @brief  This function handles NMI exception.
00051   * @param  None
00052   * @retval None
00053   */
00054 void NMI_Handler(void)
00055 {
00056 }
00057
00058 /**
00059   * @brief  This function handles Hard Fault exception.
00060   * @param  None
00061   * @retval None
00062   */
00063 void HardFault_Handler(void)
00064 {
00065   /* Go to infinite loop when Hard Fault exception occurs */
00066   while (1)
00067   {
00068   }
00069 }
00070
00071 /**
00072   * @brief  This function handles Memory Manage exception.
00073   * @param  None
00074   * @retval None
00075   */
00076 void MemManage_Handler(void)
00077 {
00078   /* Go to infinite loop when Memory Manage exception occurs */
00079   while (1)
00080   {
00081   }
00082 }
00083
00084 /**
00085   * @brief  This function handles Bus Fault exception.
00086   * @param  None
00087   * @retval None
00088   */
00089 void BusFault_Handler(void)
00090 {
00091   /* Go to infinite loop when Bus Fault exception occurs */
00092   while (1)
00093   {
00094   }
00095 }
00096
00097 /**
00098   * @brief  This function handles Usage Fault exception.
00099   * @param  None
00100   * @retval None
00101   */
00102 void UsageFault_Handler(void)
00103 {
00104   /* Go to infinite loop when Usage Fault exception occurs */
00105   while (1)
00106   {
00107   }
00108 }
00109
00110 /**
00111   * @brief  This function handles SVCall exception.
00112   * @param  None
00113   * @retval None
00114   */
00115 void SVC_Handler(void)
00116 {
00117 }
00118
00119 /**
00120   * @brief  This function handles Debug Monitor exception.
00121   * @param  None
00122   * @retval None
00123   */
00124 void DebugMon_Handler(void)
00125 {
00126 }
00127
00128 /**
00129   * @brief  This function handles PendSV_Handler exception.
00130   * @param  None
00131   * @retval None
00132   */
00133 void PendSV_Handler(void)
00134 {
00135 }
00136
00137 /**
00138   * @brief  This function handles SysTick Handler.
00139   * @param  None
00140   * @retval None
00141   */
00142 void SysTick_Handler(void)
00143 {
00144 }
00145
00146 /******************************************************************************/
00147 /*            STM32F10x Peripherals Interrupt Handlers                        */
00148 /******************************************************************************/
00149
00150 /**
00151   * @brief  This function handles EXTI Lines 0 interrupt request.
00152   * @param  None
00153   * @retval None
00154   */
00155 void EXTI0_IRQHandler(void)
00156 {
00157   if(EXTI_GetITStatus(WAKEUP_BUTTON_EXTI_LINE) != RESET)
00158   {
00159     if(index == 0)
00160     {
00161       /* Configure the BASEPRI register to 0x40 (Preemption priority = 1).
00162          Only IRQ with higher preemption priority than 1 are permitted.
00163          This will mask TIM3 and TIM4 IRQ from generation. */
00164       __set_BASEPRI(0x40);
00165       index++;
00166     }
00167     else
00168     {
00169       /* Configure the BASEPRI register to 0x00 (Preemption priority = 0).
00170          When this BASEPRI register is set to 0, it has no effect on the current
00171          priority.
00172          TIM2, TIM3 and TIM4 generation is controlled by NVIC priority registers. */
00173       __set_BASEPRI(0x00);
00174       index = 0;
00175     }
00176     /* Clears the SEL Button EXTI line pending bits. */
00177     EXTI_ClearITPendingBit(WAKEUP_BUTTON_EXTI_LINE);
00178   }
00179 }
00180
00181 /**
00182   * @brief  This function handles TIM2 global interrupt request.
00183   * @param  None
00184   * @retval None
00185   */
00186 void TIM2_IRQHandler(void)
00187 {
00188   /* Clear TIM2 update interrupt */
00189   TIM_ClearITPendingBit(TIM2, TIM_IT_Update);
00190
00191   /* Toggle LED1 */
00192   STM_EVAL_LEDToggle(LED1);
00193 }
00194
00195 /**
00196   * @brief  This function handles TIM3 global interrupt request.
00197   * @param  None
00198   * @retval None
00199   */
00200 void TIM3_IRQHandler(void)
00201 {
00202   /* Clear TIM3 update interrupt */
00203   TIM_ClearITPendingBit(TIM3, TIM_IT_Update);
00204
00205   /* Toggle LED2 */
00206   STM_EVAL_LEDToggle(LED2);
00207 }
00208
00209 /**
00210   * @brief  This function handles TIM4 global interrupt request.
00211   * @param  None
00212   * @retval None
00213   */
00214 void TIM4_IRQHandler(void)
00215 {
00216   /* Clear TIM4 update interrupt */
00217   TIM_ClearITPendingBit(TIM4, TIM_IT_Update);
00218
00219   /* Toggle LED3 */
00220   STM_EVAL_LEDToggle(LED3);
00221 }
00222
00223 /******************************************************************************/
00224 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00225 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00226 /*  available peripheral interrupt handler's name please refer to the startup */
00227 /*  file (startup_stm32f10x_xx.s).                                            */
00228 /******************************************************************************/
00229
00230 /**
00231   * @brief  This function handles PPP interrupt request.
00232   * @param  None
00233   * @retval None
00234   */
00235 /*void PPP_IRQHandler(void)
00236 {
00237 }*/
00238
00239 /**
00240   * @}
00241   */
00242
00243 /**
00244   * @}
00245   */
00246
00247 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_it.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    NVIC/IRQ_Mask/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043 void EXTI0_IRQHandler(void);
00044 void TIM2_IRQHandler(void);
00045 void TIM3_IRQHandler(void);
00046 void TIM4_IRQHandler(void);
00047
00048 #endif /* __STM32F10x_IT_H */
00049
00050 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/main.c

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00001 /**
00002   ******************************************************************************
00003   * @file    NVIC/IRQ_Priority/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x.h"
00024 #include "stm32_eval.h"
00025
00026 /** @addtogroup STM32F10x_StdPeriph_Examples
00027   * @{
00028   */
00029
00030 /** @addtogroup IRQ_Priority
00031   * @{
00032   */
00033
00034 /* Private typedef -----------------------------------------------------------*/
00035 /* Private define ------------------------------------------------------------*/
00036 /* Private macro -------------------------------------------------------------*/
00037 /* Private variables ---------------------------------------------------------*/
00038 __IO uint8_t PreemptionOccured = 0;
00039 __IO uint8_t PreemptionPriorityValue = 0;
00040
00041 /* Private function prototypes -----------------------------------------------*/
00042 void NVIC_Config(void);
00043 void Delay(__IO uint32_t nCount);
00044
00045 /* Private functions ---------------------------------------------------------*/
00046
00047 /**
00048   * @brief  Main program.
00049   * @param  None
00050   * @retval None
00051   */
00052 int main(void)
00053 {
00054   /*!< At this stage the microcontroller clock setting is already configured,
00055        this is done through SystemInit() function which is called from startup
00056        file (startup_stm32f10x_xx.s) before to branch to application main.
00057        To reconfigure the default setting of SystemInit() function, refer to
00058        system_stm32f10x.c file
00059      */
00060
00061   /* NVIC configuration ------------------------------------------------------*/
00062   NVIC_Config();
00063
00064   /* Initialize LED1..LED4, Key and Sel Joystick Buttons mounted on STM3210X-EVAL
00065      board */
00066   STM_EVAL_LEDInit(LED1);
00067   STM_EVAL_LEDInit(LED2);
00068   STM_EVAL_LEDInit(LED3);
00069   STM_EVAL_LEDInit(LED4);
00070   STM_EVAL_PBInit(BUTTON_KEY, BUTTON_MODE_EXTI);
00071   STM_EVAL_PBInit(BUTTON_WAKEUP, BUTTON_MODE_EXTI);
00072
00073   /* Configure the SysTick Handler Priority: Preemption priority and subpriority */
00074   NVIC_SetPriority(SysTick_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), !PreemptionPriorityValue, 0));
00075
00076   while (1)
00077   {
00078     if(PreemptionOccured != 0)
00079     {
00080       /* Toggel The lED1 */
00081       STM_EVAL_LEDToggle(LED1);
00082
00083       /* Insert delay Time */
00084       Delay(0x5FFFF);
00085
00086       STM_EVAL_LEDToggle(LED2);
00087
00088       Delay(0x5FFFF);
00089
00090       STM_EVAL_LEDToggle(LED3);
00091
00092       Delay(0x5FFFF);
00093
00094       STM_EVAL_LEDToggle(LED4);
00095
00096       Delay(0x5FFFF);
00097     }
00098   }
00099 }
00100
00101 /**
00102   * @brief  Configures the NVIC interrupts.
00103   * @param  None
00104   * @retval None
00105   */
00106 void NVIC_Config(void)
00107 {
00108   NVIC_InitTypeDef NVIC_InitStructure;
00109
00110   /* Configure the preemption priority and subpriority:
00111      - 1 bits for pre-emption priority: possible value are 0 or 1
00112      - 3 bits for subpriority: possible value are 0..7
00113      - Lower values gives higher priority
00114    */
00115   NVIC_PriorityGroupConfig(NVIC_PriorityGroup_1);
00116
00117   /* Enable the WAKEUP_BUTTON_EXTI_IRQn Interrupt */
00118   NVIC_InitStructure.NVIC_IRQChannel = WAKEUP_BUTTON_EXTI_IRQn;
00119   NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = PreemptionPriorityValue;
00120   NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
00121   NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
00122   NVIC_Init(&NVIC_InitStructure);
00123
00124   /* Enable the KEY_BUTTON_EXTI_IRQn Interrupt */
00125   NVIC_InitStructure.NVIC_IRQChannel = KEY_BUTTON_EXTI_IRQn;
00126   NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
00127   NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;
00128   NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
00129   NVIC_Init(&NVIC_InitStructure);
00130 }
00131
00132 /**
00133   * @brief  Inserts a delay time.
00134   * @param  nCount: specifies the delay time length.
00135   * @retval None
00136   */
00137 void Delay(__IO uint32_t nCount)
00138 {
00139   for(; nCount != 0; nCount--);
00140 }
00141
00142 #ifdef  USE_FULL_ASSERT
00143
00144 /**
00145   * @brief  Reports the name of the source file and the source line number
00146   *         where the assert_param error has occurred.
00147   * @param  file: pointer to the source file name
00148   * @param  line: assert_param error line source number
00149   * @retval None
00150   */
00151 void assert_failed(uint8_t* file, uint32_t line)
00152 {
00153   /* User can add his own implementation to report the file name and line number,
00154      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00155
00156   /* Infinite loop */
00157   while (1)
00158   {
00159   }
00160 }
00161
00162 #endif
00163
00164 /**
00165   * @}
00166   */
00167
00168 /**
00169   * @}
00170   */
00171
00172 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_conf.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    NVIC/IRQ_Priority/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052 /* Exported types ------------------------------------------------------------*/
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Uncomment the line below to expanse the "assert_param" macro in the
00055    Standard Peripheral Library drivers code */
00056 /* #define USE_FULL_ASSERT    1 */
00057
00058 /* Exported macro ------------------------------------------------------------*/
00059 #ifdef  USE_FULL_ASSERT
00060
00061 /**
00062   * @brief  The assert_param macro is used for function's parameters check.
00063   * @param  expr: If expr is false, it calls assert_failed function which reports
00064   *         the name of the source file and the source line number of the call
00065   *         that failed. If expr is true, it returns no value.
00066   * @retval None
00067   */
00068   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00069 /* Exported functions ------------------------------------------------------- */
00070   void assert_failed(uint8_t* file, uint32_t line);
00071 #else
00072   #define assert_param(expr) ((void)0)
00073 #endif /* USE_FULL_ASSERT */
00074
00075 #endif /* __STM32F10x_CONF_H */
00076
00077 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_it.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    NVIC/IRQ_Priority/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and peripherals
00009   *          interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026 #include "stm32_eval.h"
00027
00028 /** @addtogroup STM32F10x_StdPeriph_Examples
00029   * @{
00030   */
00031
00032 /** @addtogroup IRQ_Priority
00033   * @{
00034   */
00035
00036 /* Private typedef -----------------------------------------------------------*/
00037 /* Private define ------------------------------------------------------------*/
00038 /* Private macro -------------------------------------------------------------*/
00039 /* Private variables ---------------------------------------------------------*/
00040 extern uint8_t PreemptionOccured;
00041 extern uint8_t PreemptionPriorityValue;
00042
00043 /* Private function prototypes -----------------------------------------------*/
00044 /* Private functions ---------------------------------------------------------*/
00045
00046 /******************************************************************************/
00047 /*            Cortex-M3 Processor Exceptions Handlers                         */
00048 /******************************************************************************/
00049
00050 /**
00051   * @brief  This function handles NMI exception.
00052   * @param  None
00053   * @retval None
00054   */
00055 void NMI_Handler(void)
00056 {
00057 }
00058
00059 /**
00060   * @brief  This function handles Hard Fault exception.
00061   * @param  None
00062   * @retval None
00063   */
00064 void HardFault_Handler(void)
00065 {
00066   /* Go to infinite loop when Hard Fault exception occurs */
00067   while (1)
00068   {
00069   }
00070 }
00071
00072 /**
00073   * @brief  This function handles Memory Manage exception.
00074   * @param  None
00075   * @retval None
00076   */
00077 void MemManage_Handler(void)
00078 {
00079   /* Go to infinite loop when Memory Manage exception occurs */
00080   while (1)
00081   {
00082   }
00083 }
00084
00085 /**
00086   * @brief  This function handles Bus Fault exception.
00087   * @param  None
00088   * @retval None
00089   */
00090 void BusFault_Handler(void)
00091 {
00092   /* Go to infinite loop when Bus Fault exception occurs */
00093   while (1)
00094   {
00095   }
00096 }
00097
00098 /**
00099   * @brief  This function handles Usage Fault exception.
00100   * @param  None
00101   * @retval None
00102   */
00103 void UsageFault_Handler(void)
00104 {
00105   /* Go to infinite loop when Usage Fault exception occurs */
00106   while (1)
00107   {
00108   }
00109 }
00110
00111 /**
00112   * @brief  This function handles SVCall exception.
00113   * @param  None
00114   * @retval None
00115   */
00116 void SVC_Handler(void)
00117 {
00118 }
00119
00120 /**
00121   * @brief  This function handles Debug Monitor exception.
00122   * @param  None
00123   * @retval None
00124   */
00125 void DebugMon_Handler(void)
00126 {
00127 }
00128
00129 /**
00130   * @brief  This function handles PendSV_Handler exception.
00131   * @param  None
00132   * @retval None
00133   */
00134 void PendSV_Handler(void)
00135 {
00136 }
00137
00138 /**
00139   * @brief  This function handles SysTick Handler.
00140   * @param  None
00141   * @retval None
00142   */
00143 void SysTick_Handler(void)
00144 {
00145   /* If the EXTI0 IRQ Handler was preempted by SysTick Handler */
00146   if(NVIC_GetActive(WAKEUP_BUTTON_EXTI_IRQn) != 0)
00147   {
00148     PreemptionOccured = 1;
00149   }
00150 }
00151
00152 /******************************************************************************/
00153 /*            STM32F10x Peripherals Interrupt Handlers                        */
00154 /******************************************************************************/
00155
00156 /**
00157   * @brief  This function handles External interrupt Line 0 request.
00158   * @param  None
00159   * @retval None
00160   */
00161 void EXTI0_IRQHandler(void)
00162 {
00163   /* Generate SysTick exception */
00164   SCB->ICSR |= 0x04000000;
00165
00166   /* Clear WAKEUP_BUTTON_EXTI_LINE pending bit */
00167   EXTI_ClearITPendingBit(WAKEUP_BUTTON_EXTI_LINE);
00168 }
00169
00170 /**
00171   * @brief  This function handles External lines 9 to 5 interrupt request.
00172   * @param  None
00173   * @retval None
00174   */
00175 void EXTI9_5_IRQHandler(void)
00176 {
00177   NVIC_InitTypeDef NVIC_InitStructure;
00178
00179   if(EXTI_GetITStatus(KEY_BUTTON_EXTI_LINE) != RESET)
00180   {
00181     PreemptionPriorityValue = !PreemptionPriorityValue;
00182     PreemptionOccured = 0;
00183
00184     /* Modify the WAKEUP_BUTTON_EXTI_IRQn Interrupt Preemption Priority */
00185     NVIC_InitStructure.NVIC_IRQChannel = WAKEUP_BUTTON_EXTI_IRQn;
00186     NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = PreemptionPriorityValue;
00187     NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
00188     NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
00189     NVIC_Init(&NVIC_InitStructure);
00190
00191     /* Configure the SysTick Handler Priority: Preemption priority and subpriority */
00192     NVIC_SetPriority(SysTick_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), !PreemptionPriorityValue, 0));
00193
00194     /* Clear KEY_BUTTON_EXTI_LINE pending bit */
00195     EXTI_ClearITPendingBit(KEY_BUTTON_EXTI_LINE);
00196   }
00197 }
00198
00199 /******************************************************************************/
00200 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00201 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00202 /*  available peripheral interrupt handler's name please refer to the startup */
00203 /*  file (startup_stm32f10x_xx.s).                                            */
00204 /******************************************************************************/
00205
00206 /**
00207   * @brief  This function handles PPP interrupt request.
00208   * @param  None
00209   * @retval None
00210   */
00211 /*void PPP_IRQHandler(void)
00212 {
00213 }*/
00214
00215 /**
00216   * @}
00217   */
00218
00219 /**
00220   * @}
00221   */
00222
00223 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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  • IRQ_Priority

STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_it.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    NVIC/IRQ_Priority/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043 void EXTI0_IRQHandler(void);
00044 void EXTI9_5_IRQHandler(void);
00045
00046 #endif /* __STM32F10x_IT_H */
00047
00048 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/main.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    NVIC/VectorTable_Relocation/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "main.h"
00024
00025 /** @addtogroup STM32F10x_StdPeriph_Examples
00026   * @{
00027   */
00028
00029 /** @addtogroup NVIC_VectorTable_Relocation
00030   * @{
00031   */
00032
00033 /* Private typedef -----------------------------------------------------------*/
00034 /* Private define ------------------------------------------------------------*/
00035 /* Private macro -------------------------------------------------------------*/
00036 /* Private variables ---------------------------------------------------------*/
00037 static __IO uint32_t TimingDelay;
00038
00039 /* Private function prototypes -----------------------------------------------*/
00040 void Delay(__IO uint32_t nTime);
00041
00042 /* Private functions ---------------------------------------------------------*/
00043
00044 /**
00045   * @brief  Main program.
00046   * @param  None
00047   * @retval None
00048   */
00049 int main(void)
00050 {
00051   /*!< At this stage the microcontroller clock setting is already configured,
00052        this is done through SystemInit() function which is called from startup
00053        file (startup_stm32f10x_xx.s) before to branch to application main.
00054        To reconfigure the default setting of SystemInit() function, refer to
00055        system_stm32f10x.c file
00056      */
00057
00058   /* Initialize Leds mounted on STM3210X-EVAL board */
00059   STM_EVAL_LEDInit(LED1);
00060   STM_EVAL_LEDInit(LED2);
00061   STM_EVAL_LEDInit(LED3);
00062   STM_EVAL_LEDInit(LED4);
00063
00064   /* Turn on LED1 and LED3 */
00065   STM_EVAL_LEDOn(LED1);
00066   STM_EVAL_LEDOn(LED3);
00067
00068   /* Setup SysTick Timer for 1 msec interrupts  */
00069   if (SysTick_Config(SystemCoreClock / 1000))
00070   {
00071     /* Capture error */
00072     while (1);
00073   }
00074
00075   while (1)
00076   {
00077     /* Toggle LED1, LED2, LED3 and LED4 */
00078     STM_EVAL_LEDToggle(LED1);
00079     STM_EVAL_LEDToggle(LED2);
00080     STM_EVAL_LEDToggle(LED3);
00081     STM_EVAL_LEDToggle(LED4);
00082
00083     /* Insert 500 ms delay */
00084     Delay(500);
00085
00086     /* Toggle LED1, LED2, LED3 and LED4 */
00087     STM_EVAL_LEDToggle(LED1);
00088     STM_EVAL_LEDToggle(LED2);
00089     STM_EVAL_LEDToggle(LED3);
00090     STM_EVAL_LEDToggle(LED4);
00091
00092     /* Insert 300 ms delay */
00093     Delay(300);
00094   }
00095 }
00096
00097 /**
00098   * @brief  Inserts a delay time.
00099   * @param  nTime: specifies the delay time length, in milliseconds.
00100   * @retval None
00101   */
00102 void Delay(__IO uint32_t nTime)
00103 {
00104   TimingDelay = nTime;
00105
00106   while(TimingDelay != 0)
00107   {
00108   }
00109 }
00110
00111 /**
00112   * @brief  Decrements the TimingDelay variable.
00113   * @param  None
00114   * @retval None
00115   */
00116 void TimingDelay_Decrement(void)
00117 {
00118   if (TimingDelay != 0x00)
00119   {
00120     TimingDelay--;
00121   }
00122 }
00123
00124 #ifdef  USE_FULL_ASSERT
00125
00126 /**
00127   * @brief  Reports the name of the source file and the source line number
00128   *         where the assert_param error has occurred.
00129   * @param  file: pointer to the source file name
00130   * @param  line: assert_param error line source number
00131   * @retval None
00132   */
00133 void assert_failed(uint8_t* file, uint32_t line)
00134 {
00135   /* User can add his own implementation to report the file name and line number,
00136      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00137
00138   /* Infinite loop */
00139   while (1)
00140   {
00141   }
00142 }
00143
00144 #endif
00145
00146 /**
00147   * @}
00148   */
00149
00150 /**
00151   * @}
00152   */
00153
00154 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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  • NVIC
  • VectorTable_Relocation

STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f10x_conf.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    NVIC/VectorTable_Relocation/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052 /* Exported types ------------------------------------------------------------*/
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Uncomment the line below to expanse the "assert_param" macro in the
00055    Standard Peripheral Library drivers code */
00056 /* #define USE_FULL_ASSERT    1 */
00057
00058 /* Exported macro ------------------------------------------------------------*/
00059 #ifdef  USE_FULL_ASSERT
00060
00061 /**
00062   * @brief  The assert_param macro is used for function's parameters check.
00063   * @param  expr: If expr is false, it calls assert_failed function which reports
00064   *         the name of the source file and the source line number of the call
00065   *         that failed. If expr is true, it returns no value.
00066   * @retval None
00067   */
00068   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00069 /* Exported functions ------------------------------------------------------- */
00070   void assert_failed(uint8_t* file, uint32_t line);
00071 #else
00072   #define assert_param(expr) ((void)0)
00073 #endif /* USE_FULL_ASSERT */
00074
00075 #endif /* __STM32F10x_CONF_H */
00076
00077 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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  • VectorTable_Relocation

STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f10x_it.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    NVIC/VectorTable_Relocation/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and peripherals
00009   *          interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026 #include "main.h"
00027
00028 /** @addtogroup STM32F10x_StdPeriph_Examples
00029   * @{
00030   */
00031
00032 /** @addtogroup NVIC_VectorTable_Relocation
00033   * @{
00034   */
00035
00036 /* Private typedef -----------------------------------------------------------*/
00037 /* Private define ------------------------------------------------------------*/
00038 /* Private macro -------------------------------------------------------------*/
00039 /* Private variables ---------------------------------------------------------*/
00040 /* Private function prototypes -----------------------------------------------*/
00041 /* Private functions ---------------------------------------------------------*/
00042
00043 /******************************************************************************/
00044 /*            Cortex-M3 Processor Exceptions Handlers                         */
00045 /******************************************************************************/
00046
00047 /**
00048   * @brief  This function handles NMI exception.
00049   * @param  None
00050   * @retval None
00051   */
00052 void NMI_Handler(void)
00053 {
00054 }
00055
00056 /**
00057   * @brief  This function handles Hard Fault exception.
00058   * @param  None
00059   * @retval None
00060   */
00061 void HardFault_Handler(void)
00062 {
00063   /* Go to infinite loop when Hard Fault exception occurs */
00064   while (1)
00065   {
00066   }
00067 }
00068
00069 /**
00070   * @brief  This function handles Memory Manage exception.
00071   * @param  None
00072   * @retval None
00073   */
00074 void MemManage_Handler(void)
00075 {
00076   /* Go to infinite loop when Memory Manage exception occurs */
00077   while (1)
00078   {
00079   }
00080 }
00081
00082 /**
00083   * @brief  This function handles Bus Fault exception.
00084   * @param  None
00085   * @retval None
00086   */
00087 void BusFault_Handler(void)
00088 {
00089   /* Go to infinite loop when Bus Fault exception occurs */
00090   while (1)
00091   {
00092   }
00093 }
00094
00095 /**
00096   * @brief  This function handles Usage Fault exception.
00097   * @param  None
00098   * @retval None
00099   */
00100 void UsageFault_Handler(void)
00101 {
00102   /* Go to infinite loop when Usage Fault exception occurs */
00103   while (1)
00104   {
00105   }
00106 }
00107
00108 /**
00109   * @brief  This function handles SVCall exception.
00110   * @param  None
00111   * @retval None
00112   */
00113 void SVC_Handler(void)
00114 {
00115 }
00116
00117 /**
00118   * @brief  This function handles Debug Monitor exception.
00119   * @param  None
00120   * @retval None
00121   */
00122 void DebugMon_Handler(void)
00123 {
00124 }
00125
00126 /**
00127   * @brief  This function handles PendSV_Handler exception.
00128   * @param  None
00129   * @retval None
00130   */
00131 void PendSV_Handler(void)
00132 {
00133 }
00134
00135 /**
00136   * @brief  This function handles SysTick Handler.
00137   * @param  None
00138   * @retval None
00139   */
00140 void SysTick_Handler(void)
00141 {
00142   TimingDelay_Decrement();
00143 }
00144
00145 /******************************************************************************/
00146 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00147 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00148 /*  available peripheral interrupt handler's name please refer to the startup */
00149 /*  file (startup_stm32f10x_xx.s).                                            */
00150 /******************************************************************************/
00151
00152 /**
00153   * @brief  This function handles PPP interrupt request.
00154   * @param  None
00155   * @retval None
00156   */
00157 /*void PPP_IRQHandler(void)
00158 {
00159 }*/
00160
00161 /**
00162   * @}
00163   */
00164
00165 /**
00166   * @}
00167   */
00168
00169 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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  • NVIC
  • VectorTable_Relocation

STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f10x_it.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    NVIC/VectorTable_Relocation/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043
00044 #endif /* __STM32F10x_IT_H */
00045
00046 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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  • PWR
  • PVD

STM32F10x_StdPeriph_Examples/PWR/PVD/main.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    PWR/PVD/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x.h"
00024 #include "stm32_eval.h"
00025
00026 /** @addtogroup STM32F10x_StdPeriph_Examples
00027   * @{
00028   */
00029
00030 /** @addtogroup PWR_PVD
00031   * @{
00032   */
00033
00034 /* Private typedef -----------------------------------------------------------*/
00035 /* Private define ------------------------------------------------------------*/
00036 /* Private macro -------------------------------------------------------------*/
00037 /* Private variables ---------------------------------------------------------*/
00038 /* Private function prototypes -----------------------------------------------*/
00039 void EXTI_Configuration(void);
00040 void NVIC_Configuration(void);
00041
00042 /* Private functions ---------------------------------------------------------*/
00043
00044 /**
00045   * @brief  Main program.
00046   * @param  None
00047   * @retval None
00048   */
00049 int main(void)
00050 {
00051   /*!< At this stage the microcontroller clock setting is already configured,
00052        this is done through SystemInit() function which is called from startup
00053        file (startup_stm32f10x_xx.s) before to branch to application main.
00054        To reconfigure the default setting of SystemInit() function, refer to
00055        system_stm32f10x.c file
00056      */
00057
00058   /* Initialize LEDs and Key Button mounted on STM3210X-EVAL board */
00059   STM_EVAL_LEDInit(LED1);
00060
00061   /* Enable PWR and BKP clock */
00062   RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR | RCC_APB1Periph_BKP, ENABLE);
00063
00064   /* Configure EXTI Line to generate an interrupt on falling edge */
00065   EXTI_Configuration();
00066
00067   /* NVIC configuration */
00068   NVIC_Configuration();
00069
00070   /* Configure the PVD Level to 2.9V */
00071   PWR_PVDLevelConfig(PWR_PVDLevel_2V9);
00072
00073   /* Enable the PVD Output */
00074   PWR_PVDCmd(ENABLE);
00075
00076   while (1)
00077   {
00078   }
00079 }
00080
00081 /**
00082   * @brief  Configures EXTI Lines.
00083   * @param  None
00084   * @retval None
00085   */
00086 void EXTI_Configuration(void)
00087 {
00088   EXTI_InitTypeDef EXTI_InitStructure;
00089
00090   /* Configure EXTI Line16(PVD Output) to generate an interrupt on rising and
00091      falling edges */
00092   EXTI_ClearITPendingBit(EXTI_Line17);
00093   EXTI_InitStructure.EXTI_Line = EXTI_Line17;
00094   EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
00095   EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising_Falling;
00096   EXTI_InitStructure.EXTI_LineCmd = ENABLE;
00097   EXTI_Init(&EXTI_InitStructure);
00098 }
00099
00100 /**
00101   * @brief  Configures NVIC and Vector Table base location.
00102   * @param  None
00103   * @retval None
00104   */
00105 void NVIC_Configuration(void)
00106 {
00107   NVIC_InitTypeDef NVIC_InitStructure;
00108
00109   /* Configure one bit for preemption priority */
00110   NVIC_PriorityGroupConfig(NVIC_PriorityGroup_1);
00111
00112   /* Enable the PVD Interrupt */
00113   NVIC_InitStructure.NVIC_IRQChannel = PVD_IRQn;
00114   NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
00115   NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
00116   NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
00117   NVIC_Init(&NVIC_InitStructure);
00118 }
00119
00120 #ifdef  USE_FULL_ASSERT
00121
00122 /**
00123   * @brief  Reports the name of the source file and the source line number
00124   *         where the assert_param error has occurred.
00125   * @param  file: pointer to the source file name
00126   * @param  line: assert_param error line source number
00127   * @retval None
00128   */
00129 void assert_failed(uint8_t* file, uint32_t line)
00130 {
00131   /* User can add his own implementation to report the file name and line number,
00132      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00133
00134   /* Infinite loop */
00135   while (1)
00136   {
00137   }
00138 }
00139
00140 #endif
00141
00142 /**
00143   * @}
00144   */
00145
00146 /**
00147   * @}
00148   */
00149
00150 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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STM32F10x_StdPeriph_Examples/PWR/PVD/stm32f10x_conf.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    PWR/PVD/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052 /* Exported types ------------------------------------------------------------*/
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Uncomment the line below to expanse the "assert_param" macro in the
00055    Standard Peripheral Library drivers code */
00056 /* #define USE_FULL_ASSERT    1 */
00057
00058 /* Exported macro ------------------------------------------------------------*/
00059 #ifdef  USE_FULL_ASSERT
00060
00061 /**
00062   * @brief  The assert_param macro is used for function's parameters check.
00063   * @param  expr: If expr is false, it calls assert_failed function which reports
00064   *         the name of the source file and the source line number of the call
00065   *         that failed. If expr is true, it returns no value.
00066   * @retval None
00067   */
00068   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00069 /* Exported functions ------------------------------------------------------- */
00070   void assert_failed(uint8_t* file, uint32_t line);
00071 #else
00072   #define assert_param(expr) ((void)0)
00073 #endif /* USE_FULL_ASSERT */
00074
00075 #endif /* __STM32F10x_CONF_H */
00076
00077 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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STM32F10x_StdPeriph_Examples/PWR/PVD/stm32f10x_it.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    PWR/PVD/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and peripherals
00009   *          interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026 #include "stm32_eval.h"
00027
00028 /** @addtogroup STM32F10x_StdPeriph_Examples
00029   * @{
00030   */
00031
00032 /** @addtogroup PWR_PVD
00033   * @{
00034   */
00035
00036 /* Private typedef -----------------------------------------------------------*/
00037 /* Private define ------------------------------------------------------------*/
00038 /* Private macro -------------------------------------------------------------*/
00039 /* Private variables ---------------------------------------------------------*/
00040 /* Private function prototypes -----------------------------------------------*/
00041 /* Private functions ---------------------------------------------------------*/
00042
00043 /******************************************************************************/
00044 /*            Cortex-M3 Processor Exceptions Handlers                         */
00045 /******************************************************************************/
00046
00047 /**
00048   * @brief  This function handles NMI exception.
00049   * @param  None
00050   * @retval None
00051   */
00052 void NMI_Handler(void)
00053 {
00054 }
00055
00056 /**
00057   * @brief  This function handles Hard Fault exception.
00058   * @param  None
00059   * @retval None
00060   */
00061 void HardFault_Handler(void)
00062 {
00063   /* Go to infinite loop when Hard Fault exception occurs */
00064   while (1)
00065   {
00066   }
00067 }
00068
00069 /**
00070   * @brief  This function handles Memory Manage exception.
00071   * @param  None
00072   * @retval None
00073   */
00074 void MemManage_Handler(void)
00075 {
00076   /* Go to infinite loop when Memory Manage exception occurs */
00077   while (1)
00078   {
00079   }
00080 }
00081
00082 /**
00083   * @brief  This function handles Bus Fault exception.
00084   * @param  None
00085   * @retval None
00086   */
00087 void BusFault_Handler(void)
00088 {
00089   /* Go to infinite loop when Bus Fault exception occurs */
00090   while (1)
00091   {
00092   }
00093 }
00094
00095 /**
00096   * @brief  This function handles Usage Fault exception.
00097   * @param  None
00098   * @retval None
00099   */
00100 void UsageFault_Handler(void)
00101 {
00102   /* Go to infinite loop when Usage Fault exception occurs */
00103   while (1)
00104   {
00105   }
00106 }
00107
00108 /**
00109   * @brief  This function handles SVCall exception.
00110   * @param  None
00111   * @retval None
00112   */
00113 void SVC_Handler(void)
00114 {
00115 }
00116
00117 /**
00118   * @brief  This function handles Debug Monitor exception.
00119   * @param  None
00120   * @retval None
00121   */
00122 void DebugMon_Handler(void)
00123 {
00124 }
00125
00126 /**
00127   * @brief  This function handles PendSV_Handler exception.
00128   * @param  None
00129   * @retval None
00130   */
00131 void PendSV_Handler(void)
00132 {
00133 }
00134
00135 /**
00136   * @brief  This function handles SysTick Handler.
00137   * @param  None
00138   * @retval None
00139   */
00140 void SysTick_Handler(void)
00141 {
00142 }
00143
00144 /******************************************************************************/
00145 /*            STM32F10x Peripherals Interrupt Handlers                        */
00146 /******************************************************************************/
00147
00148 /**
00149   * @brief  This function handles the PVD Output interrupt request.
00150   * @param  None
00151   * @retval None
00152   */
00153 void PVD_IRQHandler(void)
00154 {
00155   if(EXTI_GetITStatus(EXTI_Line16) != RESET)
00156   {
00157     /* Toggle LED1 */
00158     STM_EVAL_LEDToggle(LED1);
00159
00160     /* Clear the Key Button EXTI line pending bit */
00161     EXTI_ClearITPendingBit(EXTI_Line16);
00162   }
00163 }
00164
00165
00166 /******************************************************************************/
00167 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00168 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00169 /*  available peripheral interrupt handler's name please refer to the startup */
00170 /*  file (startup_stm32f10x_xx.s).                                            */
00171 /******************************************************************************/
00172
00173 /**
00174   * @brief  This function handles PPP interrupt request.
00175   * @param  None
00176   * @retval None
00177   */
00178 /*void PPP_IRQHandler(void)
00179 {
00180 }*/
00181
00182 /**
00183   * @}
00184   */
00185
00186 /**
00187   * @}
00188   */
00189
00190 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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STM32F10x_StdPeriph_Examples/PWR/PVD/stm32f10x_it.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    PWR/PVD/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043 void PVD_IRQHandler(void);
00044
00045 #endif /* __STM32F10x_IT_H */
00046
00047 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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STM32F10x_StdPeriph_Examples/PWR/STANDBY/main.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    PWR/STANDBY/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x.h"
00024 #include "stm32_eval.h"
00025
00026 /** @addtogroup STM32F10x_StdPeriph_Examples
00027   * @{
00028   */
00029
00030 /** @addtogroup PWR_STANDBY
00031   * @{
00032   */
00033
00034 /* Private typedef -----------------------------------------------------------*/
00035 /* Private define ------------------------------------------------------------*/
00036 /* Private macro -------------------------------------------------------------*/
00037 /* Private variables ---------------------------------------------------------*/
00038
00039 /* Private function prototypes -----------------------------------------------*/
00040 void RTC_Configuration(void);
00041 void SysTick_Configuration(void);
00042
00043 /* Private functions ---------------------------------------------------------*/
00044
00045 /**
00046   * @brief  Main program.
00047   * @param  None
00048   * @retval None
00049   */
00050 int main(void)
00051 {
00052   /*!< At this stage the microcontroller clock setting is already configured,
00053        this is done through SystemInit() function which is called from startup
00054        file (startup_stm32f10x_xx.s) before to branch to application main.
00055        To reconfigure the default setting of SystemInit() function, refer to
00056        system_stm32f10x.c file
00057      */
00058
00059   /* Initialize LEDs and Key Button mounted on STM3210X-EVAL board */
00060   STM_EVAL_LEDInit(LED1);
00061   STM_EVAL_LEDInit(LED2);
00062   STM_EVAL_PBInit(BUTTON_KEY, BUTTON_MODE_EXTI);
00063
00064   /* Turn on LED1 */
00065   STM_EVAL_LEDOn(LED1);
00066
00067   /* Enable PWR and BKP clock */
00068   RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR | RCC_APB1Periph_BKP, ENABLE);
00069
00070   /* Enable WKUP pin */
00071   PWR_WakeUpPinCmd(ENABLE);
00072
00073   /* Allow access to BKP Domain */
00074   PWR_BackupAccessCmd(ENABLE);
00075
00076   /* Configure RTC clock source and prescaler */
00077   RTC_Configuration();
00078
00079   /* Configure the SysTick to generate an interrupt each 250 ms */
00080   SysTick_Configuration();
00081
00082   while (1)
00083   {
00084   }
00085 }
00086
00087 /**
00088   * @brief  Configures RTC clock source and prescaler.
00089   * @param  None
00090   * @retval None
00091   */
00092 void RTC_Configuration(void)
00093 {
00094   /* Check if the StandBy flag is set */
00095   if(PWR_GetFlagStatus(PWR_FLAG_SB) != RESET)
00096   {/* System resumed from STANDBY mode */
00097
00098     /* Turn on LED2 */
00099     STM_EVAL_LEDOn(LED2);
00100
00101     /* Clear StandBy flag */
00102     PWR_ClearFlag(PWR_FLAG_SB);
00103
00104     /* Wait for RTC APB registers synchronisation */
00105     RTC_WaitForSynchro();
00106     /* No need to configure the RTC as the RTC configuration(clock source, enable,
00107        prescaler,...) is kept after wake-up from STANDBY */
00108   }
00109   else
00110   {/* StandBy flag is not set */
00111
00112     /* RTC clock source configuration ----------------------------------------*/
00113     /* Reset Backup Domain */
00114     BKP_DeInit();
00115
00116     /* Enable LSE OSC */
00117     RCC_LSEConfig(RCC_LSE_ON);
00118     /* Wait till LSE is ready */
00119     while(RCC_GetFlagStatus(RCC_FLAG_LSERDY) == RESET)
00120     {
00121     }
00122
00123     /* Select the RTC Clock Source */
00124     RCC_RTCCLKConfig(RCC_RTCCLKSource_LSE);
00125
00126     /* Enable the RTC Clock */
00127     RCC_RTCCLKCmd(ENABLE);
00128
00129     /* RTC configuration -----------------------------------------------------*/
00130     /* Wait for RTC APB registers synchronisation */
00131     RTC_WaitForSynchro();
00132
00133     /* Set the RTC time base to 1s */
00134     RTC_SetPrescaler(32767);
00135     /* Wait until last write operation on RTC registers has finished */
00136     RTC_WaitForLastTask();
00137   }
00138 }
00139
00140 /**
00141   * @brief  Configures the SysTick to generate an interrupt each 250 ms.
00142   * @param  None
00143   * @retval None
00144   */
00145 void SysTick_Configuration(void)
00146 {
00147   /* SysTick interrupt each 250 ms with SysTick Clock equal to (HCLK/8) */
00148   if (SysTick_Config((SystemCoreClock/8) / 4))
00149   {
00150     /* Capture error */
00151     while (1);
00152   }
00153
00154   /* Select AHB clock(HCLK) divided by 8 as SysTick clock source */
00155   SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK_Div8);
00156
00157   /* Set SysTick Preemption Priority to 1 */
00158   NVIC_SetPriority(SysTick_IRQn, 0x04);
00159 }
00160
00161 #ifdef  USE_FULL_ASSERT
00162
00163 /**
00164   * @brief  Reports the name of the source file and the source line number
00165   *         where the assert_param error has occurred.
00166   * @param  file: pointer to the source file name
00167   * @param  line: assert_param error line source number
00168   * @retval None
00169   */
00170 void assert_failed(uint8_t* file, uint32_t line)
00171 {
00172   /* User can add his own implementation to report the file name and line number,
00173      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00174
00175   /* Infinite loop */
00176   while (1)
00177   {
00178   }
00179 }
00180
00181 #endif
00182
00183 /**
00184   * @}
00185   */
00186
00187 /**
00188   * @}
00189   */
00190
00191 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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STM32F10x_StdPeriph_Examples/PWR/STANDBY/stm32f10x_conf.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    PWR/STANDBY/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052 /* Exported types ------------------------------------------------------------*/
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Uncomment the line below to expanse the "assert_param" macro in the
00055    Standard Peripheral Library drivers code */
00056 /* #define USE_FULL_ASSERT    1 */
00057
00058 /* Exported macro ------------------------------------------------------------*/
00059 #ifdef  USE_FULL_ASSERT
00060
00061 /**
00062   * @brief  The assert_param macro is used for function's parameters check.
00063   * @param  expr: If expr is false, it calls assert_failed function which reports
00064   *         the name of the source file and the source line number of the call
00065   *         that failed. If expr is true, it returns no value.
00066   * @retval None
00067   */
00068   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00069 /* Exported functions ------------------------------------------------------- */
00070   void assert_failed(uint8_t* file, uint32_t line);
00071 #else
00072   #define assert_param(expr) ((void)0)
00073 #endif /* USE_FULL_ASSERT */
00074
00075 #endif /* __STM32F10x_CONF_H */
00076
00077 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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STM32F10x_StdPeriph_Examples/PWR/STANDBY/stm32f10x_it.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    PWR/STANDBY/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and peripherals
00009   *          interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026 #include "stm32_eval.h"
00027
00028 /** @addtogroup STM32F10x_StdPeriph_Examples
00029   * @{
00030   */
00031
00032 /** @addtogroup PWR_STANDBY
00033   * @{
00034   */
00035
00036 /* Private typedef -----------------------------------------------------------*/
00037 /* Private define ------------------------------------------------------------*/
00038 /* Private macro -------------------------------------------------------------*/
00039 /* Private variables ---------------------------------------------------------*/
00040 /* Private function prototypes -----------------------------------------------*/
00041 /* Private functions ---------------------------------------------------------*/
00042
00043 /******************************************************************************/
00044 /*            Cortex-M3 Processor Exceptions Handlers                         */
00045 /******************************************************************************/
00046
00047 /**
00048   * @brief  This function handles NMI exception.
00049   * @param  None
00050   * @retval None
00051   */
00052 void NMI_Handler(void)
00053 {
00054 }
00055
00056 /**
00057   * @brief  This function handles Hard Fault exception.
00058   * @param  None
00059   * @retval None
00060   */
00061 void HardFault_Handler(void)
00062 {
00063   /* Go to infinite loop when Hard Fault exception occurs */
00064   while (1)
00065   {
00066   }
00067 }
00068
00069 /**
00070   * @brief  This function handles Memory Manage exception.
00071   * @param  None
00072   * @retval None
00073   */
00074 void MemManage_Handler(void)
00075 {
00076   /* Go to infinite loop when Memory Manage exception occurs */
00077   while (1)
00078   {
00079   }
00080 }
00081
00082 /**
00083   * @brief  This function handles Bus Fault exception.
00084   * @param  None
00085   * @retval None
00086   */
00087 void BusFault_Handler(void)
00088 {
00089   /* Go to infinite loop when Bus Fault exception occurs */
00090   while (1)
00091   {
00092   }
00093 }
00094
00095 /**
00096   * @brief  This function handles Usage Fault exception.
00097   * @param  None
00098   * @retval None
00099   */
00100 void UsageFault_Handler(void)
00101 {
00102   /* Go to infinite loop when Usage Fault exception occurs */
00103   while (1)
00104   {
00105   }
00106 }
00107
00108 /**
00109   * @brief  This function handles SVCall exception.
00110   * @param  None
00111   * @retval None
00112   */
00113 void SVC_Handler(void)
00114 {
00115 }
00116
00117 /**
00118   * @brief  This function handles Debug Monitor exception.
00119   * @param  None
00120   * @retval None
00121   */
00122 void DebugMon_Handler(void)
00123 {
00124 }
00125
00126 /**
00127   * @brief  This function handles PendSV_Handler exception.
00128   * @param  None
00129   * @retval None
00130   */
00131 void PendSV_Handler(void)
00132 {
00133 }
00134
00135 /**
00136   * @brief  This function handles SysTick Handler.
00137   * @param  None
00138   * @retval None
00139   */
00140 void SysTick_Handler(void)
00141 {
00142   /* Toggle LED1 */
00143   STM_EVAL_LEDToggle(LED1);
00144 }
00145
00146 /******************************************************************************/
00147 /*            STM32F10x Peripherals Interrupt Handlers                        */
00148 /******************************************************************************/
00149
00150 /**
00151   * @brief  This function handles External lines 9 to 5 interrupt request.
00152   * @param  None
00153   * @retval None
00154   */
00155 void EXTI9_5_IRQHandler(void)
00156 {
00157   if(EXTI_GetITStatus(KEY_BUTTON_EXTI_LINE) != RESET)
00158   {
00159     /* Clear the Key Button EXTI line pending bit */
00160     EXTI_ClearITPendingBit(KEY_BUTTON_EXTI_LINE);
00161
00162     /* Turn on LED1 */
00163     STM_EVAL_LEDOn(LED1);
00164
00165     /* Wait till RTC Second event occurs */
00166     RTC_ClearFlag(RTC_FLAG_SEC);
00167     while(RTC_GetFlagStatus(RTC_FLAG_SEC) == RESET);
00168
00169     /* Set the RTC Alarm after 3s */
00170     RTC_SetAlarm(RTC_GetCounter()+ 3);
00171     /* Wait until last write operation on RTC registers has finished */
00172     RTC_WaitForLastTask();
00173
00174     /* Request to enter STANDBY mode (Wake Up flag is cleared in PWR_EnterSTANDBYMode function) */
00175     PWR_EnterSTANDBYMode();
00176   }
00177 }
00178
00179 /******************************************************************************/
00180 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00181 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00182 /*  available peripheral interrupt handler's name please refer to the startup */
00183 /*  file (startup_stm32f10x_xx.s).                                            */
00184 /******************************************************************************/
00185
00186 /**
00187   * @brief  This function handles PPP interrupt request.
00188   * @param  None
00189   * @retval None
00190   */
00191 /*void PPP_IRQHandler(void)
00192 {
00193 }*/
00194
00195 /**
00196   * @}
00197   */
00198
00199 /**
00200   * @}
00201   */
00202
00203 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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STM32F10x_StdPeriph_Examples/PWR/STANDBY/stm32f10x_it.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    PWR/STANDBY/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043 void EXTI9_5_IRQHandler(void);
00044
00045 #endif /* __STM32F10x_IT_H */
00046
00047 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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STM32F10x_StdPeriph_Examples/PWR/STOP/main.c

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00001 /**
00002   ******************************************************************************
00003   * @file    PWR/STOP/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x.h"
00024 #include "stm32_eval.h"
00025
00026 /** @addtogroup STM32F10x_StdPeriph_Examples
00027   * @{
00028   */
00029
00030 /** @addtogroup PWR_STOP
00031   * @{
00032   */
00033
00034 /* Private typedef -----------------------------------------------------------*/
00035 /* Private define ------------------------------------------------------------*/
00036 /* Private macro -------------------------------------------------------------*/
00037 /* Private variables ---------------------------------------------------------*/
00038 extern __IO uint32_t TimingDelay;
00039 ErrorStatus HSEStartUpStatus;
00040
00041 /* Private function prototypes -----------------------------------------------*/
00042 void SYSCLKConfig_STOP(void);
00043 void EXTI_Configuration(void);
00044 void RTC_Configuration(void);
00045 void NVIC_Configuration(void);
00046 void SysTick_Configuration(void);
00047 void Delay(__IO uint32_t nTime);
00048
00049 /* Private functions ---------------------------------------------------------*/
00050
00051 /**
00052   * @brief   Main program.
00053   * @param  None
00054   * @retval None
00055   */
00056 int main(void)
00057 {
00058   /*!< At this stage the microcontroller clock setting is already configured,
00059        this is done through SystemInit() function which is called from startup
00060        file (startup_stm32f10x_xx.s) before to branch to application main.
00061        To reconfigure the default setting of SystemInit() function, refer to
00062        system_stm32f10x.c file
00063      */
00064
00065   /* Initialize LEDs and Key Button mounted on STM3210X-EVAL board */
00066   STM_EVAL_LEDInit(LED1);
00067   STM_EVAL_LEDInit(LED2);
00068   STM_EVAL_LEDInit(LED3);
00069   STM_EVAL_PBInit(BUTTON_KEY, BUTTON_MODE_EXTI);
00070
00071   /* Enable PWR and BKP clock */
00072   RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR | RCC_APB1Periph_BKP, ENABLE);
00073
00074   /* Configure EXTI Line to generate an interrupt on falling edge */
00075   EXTI_Configuration();
00076
00077   /* Configure RTC clock source and prescaler */
00078   RTC_Configuration();
00079
00080   /* NVIC configuration */
00081   NVIC_Configuration();
00082
00083   /* Configure the SysTick to generate an interrupt each 1 millisecond */
00084   SysTick_Configuration();
00085
00086   /* Turn on LED1 */
00087   STM_EVAL_LEDOn(LED1);
00088
00089   while (1)
00090   {
00091     /* Insert 1.5 second delay */
00092     Delay(1500);
00093
00094     /* Wait till RTC Second event occurs */
00095     RTC_ClearFlag(RTC_FLAG_SEC);
00096     while(RTC_GetFlagStatus(RTC_FLAG_SEC) == RESET);
00097
00098     /* Alarm in 3 second */
00099     RTC_SetAlarm(RTC_GetCounter()+ 3);
00100     /* Wait until last write operation on RTC registers has finished */
00101     RTC_WaitForLastTask();
00102
00103     /* Turn off LED1 */
00104     STM_EVAL_LEDOff(LED1);
00105
00106     /* Request to enter STOP mode with regulator in low power mode*/
00107     PWR_EnterSTOPMode(PWR_Regulator_LowPower, PWR_STOPEntry_WFI);
00108
00109     /* At this stage the system has resumed from STOP mode -------------------*/
00110     /* Turn on LED1 */
00111     STM_EVAL_LEDOn(LED1);
00112
00113     /* Configures system clock after wake-up from STOP: enable HSE, PLL and select
00114        PLL as system clock source (HSE and PLL are disabled in STOP mode) */
00115     SYSCLKConfig_STOP();
00116   }
00117 }
00118
00119 /**
00120   * @brief  Configures system clock after wake-up from STOP: enable HSE, PLL
00121   *         and select PLL as system clock source.
00122   * @param  None
00123   * @retval None
00124   */
00125 void SYSCLKConfig_STOP(void)
00126 {
00127   /* Enable HSE */
00128   RCC_HSEConfig(RCC_HSE_ON);
00129
00130   /* Wait till HSE is ready */
00131   HSEStartUpStatus = RCC_WaitForHSEStartUp();
00132
00133   if(HSEStartUpStatus == SUCCESS)
00134   {
00135
00136 #ifdef STM32F10X_CL
00137     /* Enable PLL2 */
00138     RCC_PLL2Cmd(ENABLE);
00139
00140     /* Wait till PLL2 is ready */
00141     while(RCC_GetFlagStatus(RCC_FLAG_PLL2RDY) == RESET)
00142     {
00143     }
00144
00145 #endif
00146
00147     /* Enable PLL */
00148     RCC_PLLCmd(ENABLE);
00149
00150     /* Wait till PLL is ready */
00151     while(RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET)
00152     {
00153     }
00154
00155     /* Select PLL as system clock source */
00156     RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
00157
00158     /* Wait till PLL is used as system clock source */
00159     while(RCC_GetSYSCLKSource() != 0x08)
00160     {
00161     }
00162   }
00163 }
00164
00165 /**
00166   * @brief  Configures EXTI Lines.
00167   * @param  None
00168   * @retval None
00169   */
00170 void EXTI_Configuration(void)
00171 {
00172   EXTI_InitTypeDef EXTI_InitStructure;
00173
00174   /* Configure EXTI Line17(RTC Alarm) to generate an interrupt on rising edge */
00175   EXTI_ClearITPendingBit(EXTI_Line17);
00176   EXTI_InitStructure.EXTI_Line = EXTI_Line17;
00177   EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
00178   EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;
00179   EXTI_InitStructure.EXTI_LineCmd = ENABLE;
00180   EXTI_Init(&EXTI_InitStructure);
00181 }
00182
00183 /**
00184   * @brief  Configures RTC clock source and prescaler.
00185   * @param  None
00186   * @retval None
00187   */
00188 void RTC_Configuration(void)
00189 {
00190   /* RTC clock source configuration ------------------------------------------*/
00191   /* Allow access to BKP Domain */
00192   PWR_BackupAccessCmd(ENABLE);
00193
00194   /* Reset Backup Domain */
00195   BKP_DeInit();
00196
00197   /* Enable the LSE OSC */
00198   RCC_LSEConfig(RCC_LSE_ON);
00199   /* Wait till LSE is ready */
00200   while(RCC_GetFlagStatus(RCC_FLAG_LSERDY) == RESET)
00201   {
00202   }
00203
00204   /* Select the RTC Clock Source */
00205   RCC_RTCCLKConfig(RCC_RTCCLKSource_LSE);
00206
00207   /* Enable the RTC Clock */
00208   RCC_RTCCLKCmd(ENABLE);
00209
00210   /* RTC configuration -------------------------------------------------------*/
00211   /* Wait for RTC APB registers synchronisation */
00212   RTC_WaitForSynchro();
00213
00214   /* Set the RTC time base to 1s */
00215   RTC_SetPrescaler(32767);
00216   /* Wait until last write operation on RTC registers has finished */
00217   RTC_WaitForLastTask();
00218
00219   /* Enable the RTC Alarm interrupt */
00220   RTC_ITConfig(RTC_IT_ALR, ENABLE);
00221   /* Wait until last write operation on RTC registers has finished */
00222   RTC_WaitForLastTask();
00223 }
00224
00225 /**
00226   * @brief  Configures NVIC and Vector Table base location.
00227   * @param  None
00228   * @retval None
00229   */
00230 void NVIC_Configuration(void)
00231 {
00232   NVIC_InitTypeDef NVIC_InitStructure;
00233
00234   /* 2 bits for Preemption Priority and 2 bits for Sub Priority */
00235   NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);
00236
00237   NVIC_InitStructure.NVIC_IRQChannel = RTCAlarm_IRQn;
00238   NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
00239   NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
00240   NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
00241   NVIC_Init(&NVIC_InitStructure);
00242 }
00243
00244 /**
00245   * @brief  Configures the SysTick to generate an interrupt each 1 millisecond.
00246   * @param  None
00247   * @retval None
00248   */
00249 void SysTick_Configuration(void)
00250 {
00251   /* Setup SysTick Timer for 1 msec interrupts  */
00252   if (SysTick_Config(SystemCoreClock / 1000))
00253   {
00254     /* Capture error */
00255     while (1);
00256   }
00257   /* Set SysTick Priority to 3 */
00258   NVIC_SetPriority(SysTick_IRQn, 0x0C);
00259 }
00260
00261 /**
00262   * @brief  Inserts a delay time.
00263   * @param  nTime: specifies the delay time length, in milliseconds.
00264   * @retval None
00265   */
00266 void Delay(__IO uint32_t nTime)
00267 {
00268   TimingDelay = nTime;
00269
00270   while(TimingDelay != 0);
00271
00272 }
00273
00274 #ifdef  USE_FULL_ASSERT
00275
00276 /**
00277   * @brief  Reports the name of the source file and the source line number
00278   *         where the assert_param error has occurred.
00279   * @param  file: pointer to the source file name
00280   * @param  line: assert_param error line source number
00281   * @retval None
00282   */
00283 void assert_failed(uint8_t* file, uint32_t line)
00284 {
00285   /* User can add his own implementation to report the file name and line number,
00286      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00287
00288   /* Infinite loop */
00289   while (1)
00290   {
00291   }
00292 }
00293
00294 #endif
00295
00296 /**
00297   * @}
00298   */
00299
00300 /**
00301   * @}
00302   */
00303
00304 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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  • STOP

STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_conf.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    PWR/STOP/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052 /* Exported types ------------------------------------------------------------*/
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Uncomment the line below to expanse the "assert_param" macro in the
00055    Standard Peripheral Library drivers code */
00056 /* #define USE_FULL_ASSERT    1 */
00057
00058 /* Exported macro ------------------------------------------------------------*/
00059 #ifdef  USE_FULL_ASSERT
00060
00061 /**
00062   * @brief  The assert_param macro is used for function's parameters check.
00063   * @param  expr: If expr is false, it calls assert_failed function which reports
00064   *         the name of the source file and the source line number of the call
00065   *         that failed. If expr is true, it returns no value.
00066   * @retval None
00067   */
00068   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00069 /* Exported functions ------------------------------------------------------- */
00070   void assert_failed(uint8_t* file, uint32_t line);
00071 #else
00072   #define assert_param(expr) ((void)0)
00073 #endif /* USE_FULL_ASSERT */
00074
00075 #endif /* __STM32F10x_CONF_H */
00076
00077 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_it.c

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00001 /**
00002   ******************************************************************************
00003   * @file    PWR/STOP/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and peripherals
00009   *          interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026 #include "stm32_eval.h"
00027
00028 /** @addtogroup STM32F10x_StdPeriph_Examples
00029   * @{
00030   */
00031
00032 /** @addtogroup PWR_STOP
00033   * @{
00034   */
00035
00036 /* Private typedef -----------------------------------------------------------*/
00037 /* Private define ------------------------------------------------------------*/
00038 /* Private macro -------------------------------------------------------------*/
00039 /* Private variables ---------------------------------------------------------*/
00040 __IO uint32_t TimingDelay = 0;
00041
00042 /* Private function prototypes -----------------------------------------------*/
00043 /* Private functions ---------------------------------------------------------*/
00044
00045 /******************************************************************************/
00046 /*            Cortex-M3 Processor Exceptions Handlers                         */
00047 /******************************************************************************/
00048
00049 /**
00050   * @brief  This function handles NMI exception.
00051   * @param  None
00052   * @retval None
00053   */
00054 void NMI_Handler(void)
00055 {
00056 }
00057
00058 /**
00059   * @brief  This function handles Hard Fault exception.
00060   * @param  None
00061   * @retval None
00062   */
00063 void HardFault_Handler(void)
00064 {
00065   /* Go to infinite loop when Hard Fault exception occurs */
00066   while (1)
00067   {
00068   }
00069 }
00070
00071 /**
00072   * @brief  This function handles Memory Manage exception.
00073   * @param  None
00074   * @retval None
00075   */
00076 void MemManage_Handler(void)
00077 {
00078   /* Go to infinite loop when Memory Manage exception occurs */
00079   while (1)
00080   {
00081   }
00082 }
00083
00084 /**
00085   * @brief  This function handles Bus Fault exception.
00086   * @param  None
00087   * @retval None
00088   */
00089 void BusFault_Handler(void)
00090 {
00091   /* Go to infinite loop when Bus Fault exception occurs */
00092   while (1)
00093   {
00094   }
00095 }
00096
00097 /**
00098   * @brief  This function handles Usage Fault exception.
00099   * @param  None
00100   * @retval None
00101   */
00102 void UsageFault_Handler(void)
00103 {
00104   /* Go to infinite loop when Usage Fault exception occurs */
00105   while (1)
00106   {
00107   }
00108 }
00109
00110 /**
00111   * @brief  This function handles SVCall exception.
00112   * @param  None
00113   * @retval None
00114   */
00115 void SVC_Handler(void)
00116 {
00117 }
00118
00119 /**
00120   * @brief  This function handles Debug Monitor exception.
00121   * @param  None
00122   * @retval None
00123   */
00124 void DebugMon_Handler(void)
00125 {
00126 }
00127
00128 /**
00129   * @brief  This function handles PendSV_Handler exception.
00130   * @param  None
00131   * @retval None
00132   */
00133 void PendSV_Handler(void)
00134 {
00135 }
00136
00137 /**
00138   * @brief  This function handles SysTick Handler.
00139   * @param  None
00140   * @retval None
00141   */
00142 void SysTick_Handler(void)
00143 {
00144   TimingDelay--;
00145 }
00146
00147 /******************************************************************************/
00148 /*            STM32F10x Peripherals Interrupt Handlers                        */
00149 /******************************************************************************/
00150
00151 /**
00152   * @brief  This function handles External lines 9 to 5 interrupt request.
00153   * @param  None
00154   * @retval None
00155   */
00156 void EXTI9_5_IRQHandler(void)
00157 {
00158   if(EXTI_GetITStatus(KEY_BUTTON_EXTI_LINE) != RESET)
00159   {
00160     /* Clear the Key Button EXTI line pending bit */
00161     EXTI_ClearITPendingBit(KEY_BUTTON_EXTI_LINE);
00162
00163     /* Toggle LED2 */
00164     STM_EVAL_LEDToggle(LED2);
00165   }
00166 }
00167
00168 /**
00169   * @brief  This function handles RTC Alarm interrupt request.
00170   * @param  None
00171   * @retval None
00172   */
00173 void RTCAlarm_IRQHandler(void)
00174 {
00175   if(RTC_GetITStatus(RTC_IT_ALR) != RESET)
00176   {
00177     /* Toggle LED3 */
00178     STM_EVAL_LEDToggle(LED3);
00179
00180     /* Clear EXTI line17 pending bit */
00181     EXTI_ClearITPendingBit(EXTI_Line17);
00182
00183     /* Check if the Wake-Up flag is set */
00184     if(PWR_GetFlagStatus(PWR_FLAG_WU) != RESET)
00185     {
00186       /* Clear Wake Up flag */
00187       PWR_ClearFlag(PWR_FLAG_WU);
00188     }
00189
00190     /* Wait until last write operation on RTC registers has finished */
00191     RTC_WaitForLastTask();
00192     /* Clear RTC Alarm interrupt pending bit */
00193     RTC_ClearITPendingBit(RTC_IT_ALR);
00194     /* Wait until last write operation on RTC registers has finished */
00195     RTC_WaitForLastTask();
00196   }
00197 }
00198
00199 /******************************************************************************/
00200 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00201 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00202 /*  available peripheral interrupt handler's name please refer to the startup */
00203 /*  file (startup_stm32f10x_xx.s).                                            */
00204 /******************************************************************************/
00205
00206 /**
00207   * @brief  This function handles PPP interrupt request.
00208   * @param  None
00209   * @retval None
00210   */
00211 /*void PPP_IRQHandler(void)
00212 {
00213 }*/
00214
00215 /**
00216   * @}
00217   */
00218
00219 /**
00220   * @}
00221   */
00222
00223 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_it.h

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00001 /**
00002   ******************************************************************************
00003   * @file    PWR/STOP/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043 void EXTI9_5_IRQHandler(void);
00044 void RTCAlarm_IRQHandler(void);
00045
00046 #endif /* __STM32F10x_IT_H */
00047
00048 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/main.c

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00001 /**
00002   ******************************************************************************
00003   * @file    RCC/RCC_ClockConfig/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "main.h"
00024
00025 /** @addtogroup STM32F10x_StdPeriph_Examples
00026   * @{
00027   */
00028
00029
00030 /** @addtogroup RCC_ClockConfig
00031   * @{
00032   */
00033
00034 /* Private typedef -----------------------------------------------------------*/
00035 /* Private define ------------------------------------------------------------*/
00036 #define DELAY_COUNT    0x3FFFF
00037
00038 /* Private macro -------------------------------------------------------------*/
00039 /* Private variables ---------------------------------------------------------*/
00040 GPIO_InitTypeDef GPIO_InitStructure;
00041 RCC_ClocksTypeDef RCC_ClockFreq;
00042 ErrorStatus HSEStartUpStatus;
00043
00044 /* Private function prototypes -----------------------------------------------*/
00045 void NVIC_Configuration(void);
00046 void Delay(__IO uint32_t nCount);
00047
00048 void SetSysClock(void);
00049 #ifdef SYSCLK_HSE
00050   void SetSysClockToHSE(void);
00051 #elif defined SYSCLK_FREQ_24MHz
00052   void SetSysClockTo24(void);
00053 #elif defined SYSCLK_FREQ_36MHz
00054   void SetSysClockTo36(void);
00055 #elif defined SYSCLK_FREQ_48MHz
00056   void SetSysClockTo48(void);
00057 #elif defined SYSCLK_FREQ_56MHz
00058   void SetSysClockTo56(void);
00059 #elif defined SYSCLK_FREQ_72MHz
00060   void SetSysClockTo72(void);
00061 #endif
00062
00063 /* Private functions ---------------------------------------------------------*/
00064
00065 /**
00066   * @brief  Main program.
00067   * @param  None
00068   * @retval None
00069   */
00070 int main(void)
00071 {
00072   /*!< At this stage the microcontroller clock setting is already configured,
00073        this is done through SystemInit() function which is called from startup
00074        file (startup_stm32f10x_xx.s) before to branch to application main.
00075        To reconfigure the default setting of SystemInit() function, refer to
00076        system_stm32f10x.c file
00077      */
00078
00079   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
00080   SetSysClock();
00081
00082   /* This function fills the RCC_ClockFreq structure with the current
00083      frequencies of different on chip clocks (for debug purpose) */
00084   RCC_GetClocksFreq(&RCC_ClockFreq);
00085
00086   /* Enable Clock Security System(CSS): this will generate an NMI exception
00087      when HSE clock fails */
00088   RCC_ClockSecuritySystemCmd(ENABLE);
00089
00090   /* NVIC configuration ------------------------------------------------------*/
00091   NVIC_Configuration();
00092
00093   /* Initialize Leds mounted on STM3210X-EVAL board --------------------------*/
00094   STM_EVAL_LEDInit(LED1);
00095   STM_EVAL_LEDInit(LED2);
00096   STM_EVAL_LEDInit(LED3);
00097   STM_EVAL_LEDInit(LED4);
00098
00099   /* Output HSE clock on MCO pin ---------------------------------------------*/
00100   RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);
00101
00102   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8;
00103   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
00104   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00105   GPIO_Init(GPIOA, &GPIO_InitStructure);
00106   RCC_MCOConfig(RCC_MCO_HSE);
00107
00108   while (1)
00109   {
00110     /* Toggle LED1 */
00111     STM_EVAL_LEDToggle(LED1);
00112     /* Insert delay */
00113     Delay(DELAY_COUNT);
00114
00115     /* Toggle LED2 */
00116     STM_EVAL_LEDToggle(LED2);
00117         /* Insert delay */
00118     Delay(DELAY_COUNT);
00119
00120     /* Toggle LED3 */
00121     STM_EVAL_LEDToggle(LED3);
00122     /* Insert delay */
00123     Delay(DELAY_COUNT);
00124
00125     /* Toggle LED4 */
00126     STM_EVAL_LEDToggle(LED4);
00127     /* Insert a delay */
00128     Delay(DELAY_COUNT);
00129   }
00130 }
00131
00132 /**
00133   * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1
00134   *         prescalers.
00135   * @param  None
00136   * @retval None
00137   */
00138 void SetSysClock(void)
00139 {
00140 /* The System clock configuration functions defined below assume that:
00141         - For Low, Medium and High density devices an external 8MHz crystal is
00142           used to drive the System clock.
00143         - For Connectivity line devices an external 25MHz crystal is used to drive
00144           the System clock.
00145      If you are using different crystal you have to adapt those functions accordingly.*/
00146
00147 #if defined SYSCLK_HSE
00148   SetSysClockToHSE();
00149 #elif defined SYSCLK_FREQ_24MHz
00150   SetSysClockTo24();
00151 #elif defined SYSCLK_FREQ_36MHz
00152   SetSysClockTo36();
00153 #elif defined SYSCLK_FREQ_48MHz
00154   SetSysClockTo48();
00155 #elif defined SYSCLK_FREQ_56MHz
00156   SetSysClockTo56();
00157 #elif defined SYSCLK_FREQ_72MHz
00158   SetSysClockTo72();
00159 #endif
00160
00161  /* If none of the define above is enabled, the HSI is used as System clock
00162     source (default after reset) */
00163 }
00164
00165 /**
00166   * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
00167   *         and PCLK1 prescalers.
00168   * @param  None
00169   * @retval None
00170   */
00171 void SetSysClockToHSE(void)
00172 {
00173   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration -----------------------------*/
00174   /* RCC system reset(for debug purpose) */
00175   RCC_DeInit();
00176
00177   /* Enable HSE */
00178   RCC_HSEConfig(RCC_HSE_ON);
00179
00180   /* Wait till HSE is ready */
00181   HSEStartUpStatus = RCC_WaitForHSEStartUp();
00182
00183   if (HSEStartUpStatus == SUCCESS)
00184   {
00185 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00186     /* Enable Prefetch Buffer */
00187     FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable);
00188
00189 #ifndef STM32F10X_CL
00190     /* Flash 0 wait state */
00191     FLASH_SetLatency(FLASH_Latency_0);
00192 #else
00193     if (HSE_Value <= 24000000)
00194         {
00195       /* Flash 0 wait state */
00196       FLASH_SetLatency(FLASH_Latency_0);
00197         }
00198         else
00199         {
00200       /* Flash 1 wait state */
00201       FLASH_SetLatency(FLASH_Latency_1);
00202         }
00203
00204 #endif /* STM32F10X_CL */
00205 #endif /* STM32F10X_LD_VL && STM32F10X_MD_VL */
00206
00207     /* HCLK = SYSCLK */
00208     RCC_HCLKConfig(RCC_SYSCLK_Div1);
00209
00210     /* PCLK2 = HCLK */
00211     RCC_PCLK2Config(RCC_HCLK_Div1);
00212
00213     /* PCLK1 = HCLK */
00214     RCC_PCLK1Config(RCC_HCLK_Div1);
00215
00216     /* Select HSE as system clock source */
00217     RCC_SYSCLKConfig(RCC_SYSCLKSource_HSE);
00218
00219     /* Wait till PLL is used as system clock source */
00220     while (RCC_GetSYSCLKSource() != 0x04)
00221     {
00222     }
00223   }
00224   else
00225   { /* If HSE fails to start-up, the application will have wrong clock configuration.
00226        User can add here some code to deal with this error */
00227
00228     /* Go to infinite loop */
00229     while (1)
00230     {
00231     }
00232   }
00233 }
00234
00235 /**
00236   * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
00237   *         and PCLK1 prescalers.
00238   * @param  None
00239   * @retval None
00240   */
00241 void SetSysClockTo24(void)
00242 {
00243   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration -----------------------------*/
00244   /* RCC system reset(for debug purpose) */
00245   RCC_DeInit();
00246
00247   /* Enable HSE */
00248   RCC_HSEConfig(RCC_HSE_ON);
00249
00250   /* Wait till HSE is ready */
00251   HSEStartUpStatus = RCC_WaitForHSEStartUp();
00252
00253   if (HSEStartUpStatus == SUCCESS)
00254   {
00255 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00256     /* Enable Prefetch Buffer */
00257     FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable);
00258
00259     /* Flash 0 wait state */
00260     FLASH_SetLatency(FLASH_Latency_0);
00261 #endif /* STM32F10X_LD_VL && STM32F10X_MD_VL */
00262
00263     /* HCLK = SYSCLK */
00264     RCC_HCLKConfig(RCC_SYSCLK_Div1);
00265
00266     /* PCLK2 = HCLK */
00267     RCC_PCLK2Config(RCC_HCLK_Div1);
00268
00269     /* PCLK1 = HCLK */
00270     RCC_PCLK1Config(RCC_HCLK_Div1);
00271
00272 #ifdef STM32F10X_CL
00273     /* Configure PLLs *********************************************************/
00274     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00275     RCC_PREDIV2Config(RCC_PREDIV2_Div5);
00276     RCC_PLL2Config(RCC_PLL2Mul_8);
00277
00278     /* Enable PLL2 */
00279     RCC_PLL2Cmd(ENABLE);
00280
00281     /* Wait till PLL2 is ready */
00282     while (RCC_GetFlagStatus(RCC_FLAG_PLL2RDY) == RESET)
00283     {}
00284
00285     /* PLL configuration: PLLCLK = (PLL2 / 10) * 6 = 24 MHz */
00286     RCC_PREDIV1Config(RCC_PREDIV1_Source_PLL2, RCC_PREDIV1_Div10);
00287     RCC_PLLConfig(RCC_PLLSource_PREDIV1, RCC_PLLMul_6);
00288 #elif defined STM32F10X_LD_VL || defined STM32F10X_MD_VL || defined STM32F10X_HD_VL
00289     /* PLLCLK = (8MHz/2) * 6 = 24 MHz */
00290     RCC_PREDIV1Config(RCC_PREDIV1_Source_HSE, RCC_PREDIV1_Div2);
00291     RCC_PLLConfig(RCC_PLLSource_PREDIV1, RCC_PLLMul_6);
00292 #else
00293     /* PLLCLK = 8MHz * 3 = 24 MHz */
00294     RCC_PLLConfig(RCC_PLLSource_HSE_Div1, RCC_PLLMul_3);
00295 #endif
00296
00297     /* Enable PLL */
00298     RCC_PLLCmd(ENABLE);
00299
00300     /* Wait till PLL is ready */
00301     while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET)
00302     {
00303     }
00304
00305     /* Select PLL as system clock source */
00306     RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
00307
00308     /* Wait till PLL is used as system clock source */
00309     while (RCC_GetSYSCLKSource() != 0x08)
00310     {
00311     }
00312   }
00313   else
00314   { /* If HSE fails to start-up, the application will have wrong clock configuration.
00315        User can add here some code to deal with this error */
00316
00317     /* Go to infinite loop */
00318     while (1)
00319     {
00320     }
00321   }
00322 }
00323 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
00324 /**
00325   * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
00326   *         and PCLK1 prescalers.
00327   * @param  None
00328   * @retval None
00329   */
00330 void SetSysClockTo36(void)
00331 {
00332   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration -----------------------------*/
00333   /* RCC system reset(for debug purpose) */
00334   RCC_DeInit();
00335
00336   /* Enable HSE */
00337   RCC_HSEConfig(RCC_HSE_ON);
00338
00339   /* Wait till HSE is ready */
00340   HSEStartUpStatus = RCC_WaitForHSEStartUp();
00341
00342   if (HSEStartUpStatus == SUCCESS)
00343   {
00344     /* Enable Prefetch Buffer */
00345     FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable);
00346
00347     /* Flash 1 wait state */
00348     FLASH_SetLatency(FLASH_Latency_1);
00349
00350     /* HCLK = SYSCLK */
00351     RCC_HCLKConfig(RCC_SYSCLK_Div1);
00352
00353     /* PCLK2 = HCLK */
00354     RCC_PCLK2Config(RCC_HCLK_Div1);
00355
00356     /* PCLK1 = HCLK */
00357     RCC_PCLK1Config(RCC_HCLK_Div1);
00358
00359 #ifdef STM32F10X_CL
00360     /* Configure PLLs *********************************************************/
00361     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00362     RCC_PREDIV2Config(RCC_PREDIV2_Div5);
00363     RCC_PLL2Config(RCC_PLL2Mul_8);
00364
00365     /* Enable PLL2 */
00366     RCC_PLL2Cmd(ENABLE);
00367
00368     /* Wait till PLL2 is ready */
00369     while (RCC_GetFlagStatus(RCC_FLAG_PLL2RDY) == RESET)
00370     {}
00371
00372     /* PLL configuration: PLLCLK = (PLL2 / 10) * 9 = 36 MHz */
00373     RCC_PREDIV1Config(RCC_PREDIV1_Source_PLL2, RCC_PREDIV1_Div10);
00374     RCC_PLLConfig(RCC_PLLSource_PREDIV1, RCC_PLLMul_9);
00375 #else
00376     /* PLLCLK = (8MHz / 2) * 9 = 36 MHz */
00377     RCC_PLLConfig(RCC_PLLSource_HSE_Div2, RCC_PLLMul_9);
00378 #endif
00379
00380     /* Enable PLL */
00381     RCC_PLLCmd(ENABLE);
00382
00383     /* Wait till PLL is ready */
00384     while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET)
00385     {
00386     }
00387
00388     /* Select PLL as system clock source */
00389     RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
00390
00391     /* Wait till PLL is used as system clock source */
00392     while (RCC_GetSYSCLKSource() != 0x08)
00393     {
00394     }
00395   }
00396   else
00397   { /* If HSE fails to start-up, the application will have wrong clock configuration.
00398        User can add here some code to deal with this error */
00399
00400     /* Go to infinite loop */
00401     while (1)
00402     {
00403     }
00404   }
00405 }
00406
00407 /**
00408   * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
00409   *         and PCLK1 prescalers.
00410   * @param  None
00411   * @retval None
00412   */
00413 void SetSysClockTo48(void)
00414 {
00415   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration -----------------------------*/
00416   /* RCC system reset(for debug purpose) */
00417   RCC_DeInit();
00418
00419   /* Enable HSE */
00420   RCC_HSEConfig(RCC_HSE_ON);
00421
00422   /* Wait till HSE is ready */
00423   HSEStartUpStatus = RCC_WaitForHSEStartUp();
00424
00425   if (HSEStartUpStatus == SUCCESS)
00426   {
00427     /* Enable Prefetch Buffer */
00428     FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable);
00429
00430     /* Flash 1 wait state */
00431     FLASH_SetLatency(FLASH_Latency_1);
00432
00433     /* HCLK = SYSCLK */
00434     RCC_HCLKConfig(RCC_SYSCLK_Div1);
00435
00436     /* PCLK2 = HCLK */
00437     RCC_PCLK2Config(RCC_HCLK_Div1);
00438
00439     /* PCLK1 = HCLK/2 */
00440     RCC_PCLK1Config(RCC_HCLK_Div2);
00441
00442 #ifdef STM32F10X_CL
00443     /* Configure PLLs *********************************************************/
00444     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00445     RCC_PREDIV2Config(RCC_PREDIV2_Div5);
00446     RCC_PLL2Config(RCC_PLL2Mul_8);
00447
00448     /* Enable PLL2 */
00449     RCC_PLL2Cmd(ENABLE);
00450
00451     /* Wait till PLL2 is ready */
00452     while (RCC_GetFlagStatus(RCC_FLAG_PLL2RDY) == RESET)
00453     {}
00454
00455     /* PLL configuration: PLLCLK = (PLL2 / 5) * 6 = 48 MHz */
00456     RCC_PREDIV1Config(RCC_PREDIV1_Source_PLL2, RCC_PREDIV1_Div5);
00457     RCC_PLLConfig(RCC_PLLSource_PREDIV1, RCC_PLLMul_6);
00458 #else
00459     /* PLLCLK = 8MHz * 6 = 48 MHz */
00460     RCC_PLLConfig(RCC_PLLSource_HSE_Div1, RCC_PLLMul_6);
00461 #endif
00462
00463     /* Enable PLL */
00464     RCC_PLLCmd(ENABLE);
00465
00466     /* Wait till PLL is ready */
00467     while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET)
00468     {
00469     }
00470
00471     /* Select PLL as system clock source */
00472     RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
00473
00474     /* Wait till PLL is used as system clock source */
00475     while (RCC_GetSYSCLKSource() != 0x08)
00476     {
00477     }
00478   }
00479   else
00480   { /* If HSE fails to start-up, the application will have wrong clock configuration.
00481        User can add here some code to deal with this error */
00482
00483     /* Go to infinite loop */
00484     while (1)
00485     {
00486     }
00487   }
00488 }
00489
00490 /**
00491   * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
00492   *         and PCLK1 prescalers.
00493   * @param  None
00494   * @retval None
00495   */
00496 void SetSysClockTo56(void)
00497 {
00498   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration -----------------------------*/
00499   /* RCC system reset(for debug purpose) */
00500   RCC_DeInit();
00501
00502   /* Enable HSE */
00503   RCC_HSEConfig(RCC_HSE_ON);
00504
00505   /* Wait till HSE is ready */
00506   HSEStartUpStatus = RCC_WaitForHSEStartUp();
00507
00508   if (HSEStartUpStatus == SUCCESS)
00509   {
00510     /* Enable Prefetch Buffer */
00511     FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable);
00512
00513     /* Flash 2 wait state */
00514     FLASH_SetLatency(FLASH_Latency_2);
00515
00516     /* HCLK = SYSCLK */
00517     RCC_HCLKConfig(RCC_SYSCLK_Div1);
00518
00519     /* PCLK2 = HCLK */
00520     RCC_PCLK2Config(RCC_HCLK_Div1);
00521
00522     /* PCLK1 = HCLK/2 */
00523     RCC_PCLK1Config(RCC_HCLK_Div2);
00524
00525 #ifdef STM32F10X_CL
00526     /* Configure PLLs *********************************************************/
00527     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00528     RCC_PREDIV2Config(RCC_PREDIV2_Div5);
00529     RCC_PLL2Config(RCC_PLL2Mul_8);
00530
00531     /* Enable PLL2 */
00532     RCC_PLL2Cmd(ENABLE);
00533
00534     /* Wait till PLL2 is ready */
00535     while (RCC_GetFlagStatus(RCC_FLAG_PLL2RDY) == RESET)
00536     {}
00537
00538     /* PLL configuration: PLLCLK = (PLL2 / 5) * 7 = 56 MHz */
00539     RCC_PREDIV1Config(RCC_PREDIV1_Source_PLL2, RCC_PREDIV1_Div5);
00540     RCC_PLLConfig(RCC_PLLSource_PREDIV1, RCC_PLLMul_7);
00541 #else
00542     /* PLLCLK = 8MHz * 7 = 56 MHz */
00543     RCC_PLLConfig(RCC_PLLSource_HSE_Div1, RCC_PLLMul_7);
00544 #endif
00545
00546     /* Enable PLL */
00547     RCC_PLLCmd(ENABLE);
00548
00549     /* Wait till PLL is ready */
00550     while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET)
00551     {
00552     }
00553
00554     /* Select PLL as system clock source */
00555     RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
00556
00557     /* Wait till PLL is used as system clock source */
00558     while (RCC_GetSYSCLKSource() != 0x08)
00559     {
00560     }
00561   }
00562   else
00563   { /* If HSE fails to start-up, the application will have wrong clock configuration.
00564        User can add here some code to deal with this error */
00565
00566     /* Go to infinite loop */
00567     while (1)
00568     {
00569     }
00570   }
00571 }
00572
00573 /**
00574   * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
00575   *         and PCLK1 prescalers.
00576   * @param  None
00577   * @retval None
00578   */
00579 void SetSysClockTo72(void)
00580 {
00581   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration -----------------------------*/
00582   /* RCC system reset(for debug purpose) */
00583   RCC_DeInit();
00584
00585   /* Enable HSE */
00586   RCC_HSEConfig(RCC_HSE_ON);
00587
00588   /* Wait till HSE is ready */
00589   HSEStartUpStatus = RCC_WaitForHSEStartUp();
00590
00591   if (HSEStartUpStatus == SUCCESS)
00592   {
00593     /* Enable Prefetch Buffer */
00594     FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable);
00595
00596     /* Flash 2 wait state */
00597     FLASH_SetLatency(FLASH_Latency_2);
00598
00599     /* HCLK = SYSCLK */
00600     RCC_HCLKConfig(RCC_SYSCLK_Div1);
00601
00602     /* PCLK2 = HCLK */
00603     RCC_PCLK2Config(RCC_HCLK_Div1);
00604
00605     /* PCLK1 = HCLK/2 */
00606     RCC_PCLK1Config(RCC_HCLK_Div2);
00607
00608 #ifdef STM32F10X_CL
00609     /* Configure PLLs *********************************************************/
00610     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
00611     RCC_PREDIV2Config(RCC_PREDIV2_Div5);
00612     RCC_PLL2Config(RCC_PLL2Mul_8);
00613
00614     /* Enable PLL2 */
00615     RCC_PLL2Cmd(ENABLE);
00616
00617     /* Wait till PLL2 is ready */
00618     while (RCC_GetFlagStatus(RCC_FLAG_PLL2RDY) == RESET)
00619     {}
00620
00621     /* PLL configuration: PLLCLK = (PLL2 / 5) * 9 = 72 MHz */
00622     RCC_PREDIV1Config(RCC_PREDIV1_Source_PLL2, RCC_PREDIV1_Div5);
00623     RCC_PLLConfig(RCC_PLLSource_PREDIV1, RCC_PLLMul_9);
00624 #else
00625     /* PLLCLK = 8MHz * 9 = 72 MHz */
00626     RCC_PLLConfig(RCC_PLLSource_HSE_Div1, RCC_PLLMul_9);
00627 #endif
00628
00629     /* Enable PLL */
00630     RCC_PLLCmd(ENABLE);
00631
00632     /* Wait till PLL is ready */
00633     while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET)
00634     {
00635     }
00636
00637     /* Select PLL as system clock source */
00638     RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
00639
00640     /* Wait till PLL is used as system clock source */
00641     while(RCC_GetSYSCLKSource() != 0x08)
00642     {
00643     }
00644   }
00645   else
00646   { /* If HSE fails to start-up, the application will have wrong clock configuration.
00647        User can add here some code to deal with this error */
00648
00649     /* Go to infinite loop */
00650     while (1)
00651     {
00652     }
00653   }
00654 }
00655
00656 #endif /* STM32F10X_LD_VL && STM32F10X_MD_VL */
00657
00658 /**
00659   * @brief  Configures Vector Table base location.
00660   * @param  None
00661   * @retval None
00662   */
00663 void NVIC_Configuration(void)
00664 {
00665   NVIC_InitTypeDef NVIC_InitStructure;
00666
00667   /* Enable and configure RCC global IRQ channel */
00668   NVIC_InitStructure.NVIC_IRQChannel = RCC_IRQn;
00669   NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
00670   NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
00671   NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
00672   NVIC_Init(&NVIC_InitStructure);
00673 }
00674
00675 /**
00676   * @brief  Inserts a delay time.
00677   * @param  nCount: specifies the delay time length.
00678   * @retval None
00679   */
00680 void Delay(__IO uint32_t nCount)
00681 {
00682   for(; nCount!= 0;nCount--);
00683 }
00684
00685 #ifdef  USE_FULL_ASSERT
00686
00687 /**
00688   * @brief  Reports the name of the source file and the source line number
00689   *         where the assert_param error has occurred.
00690   * @param  file: pointer to the source file name
00691   * @param  line: assert_param error line source number
00692   * @retval None
00693   */
00694 void assert_failed(uint8_t* file, uint32_t line)
00695 {
00696   /* User can add his own implementation to report the file name and line number,
00697      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00698
00699   /* Infinite loop */
00700   while (1)
00701   {
00702   }
00703 }
00704
00705 #endif
00706
00707 /**
00708   * @}
00709   */
00710
00711 /**
00712   * @}
00713   */
00714
00715 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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  • RCC_ClockConfig

STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/stm32f10x_conf.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    RCC/RCC_ClockConfig/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052 /* Exported types ------------------------------------------------------------*/
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Uncomment the line below to expanse the "assert_param" macro in the
00055    Standard Peripheral Library drivers code */
00056 /* #define USE_FULL_ASSERT    1 */
00057
00058 /* Exported macro ------------------------------------------------------------*/
00059 #ifdef  USE_FULL_ASSERT
00060
00061 /**
00062   * @brief  The assert_param macro is used for function's parameters check.
00063   * @param  expr: If expr is false, it calls assert_failed function which reports
00064   *         the name of the source file and the source line number of the call
00065   *         that failed. If expr is true, it returns no value.
00066   * @retval None
00067   */
00068   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00069 /* Exported functions ------------------------------------------------------- */
00070   void assert_failed(uint8_t* file, uint32_t line);
00071 #else
00072   #define assert_param(expr) ((void)0)
00073 #endif /* USE_FULL_ASSERT */
00074
00075 #endif /* __STM32F10x_CONF_H */
00076
00077 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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  • RCC_ClockConfig

STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/stm32f10x_it.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    RCC/RCC_ClockConfig/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and peripherals
00009   *          interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026 #include "main.h"
00027
00028 /** @addtogroup STM32F10x_StdPeriph_Examples
00029   * @{
00030   */
00031
00032 /** @addtogroup RCC_ClockConfig
00033   * @{
00034   */
00035
00036 /* Private typedef -----------------------------------------------------------*/
00037 /* Private define ------------------------------------------------------------*/
00038 /* Private macro -------------------------------------------------------------*/
00039 /* Private variables ---------------------------------------------------------*/
00040 /* Private function prototypes -----------------------------------------------*/
00041 /* Private functions ---------------------------------------------------------*/
00042
00043 /******************************************************************************/
00044 /*            Cortex-M3 Processor Exceptions Handlers                         */
00045 /******************************************************************************/
00046
00047 /**
00048   * @brief  This function handles NMI exception.
00049   * @param  None
00050   * @retval None
00051   */
00052 void NMI_Handler(void)
00053 {
00054   /* This interrupt is generated when HSE clock fails */
00055
00056   if (RCC_GetITStatus(RCC_IT_CSS) != RESET)
00057   {/* At this stage: HSE, PLL are disabled (but no change on PLL config) and HSI
00058        is selected as system clock source */
00059
00060     /* Enable HSE */
00061     RCC_HSEConfig(RCC_HSE_ON);
00062
00063     /* Enable HSE Ready interrupt */
00064     RCC_ITConfig(RCC_IT_HSERDY, ENABLE);
00065
00066 #ifndef SYSCLK_HSE
00067  #ifdef STM32F10X_CL
00068     /* Enable PLL and PLL2 Ready interrupts */
00069     RCC_ITConfig(RCC_IT_PLLRDY | RCC_IT_PLL2RDY, ENABLE);
00070  #else
00071     /* Enable PLL Ready interrupt */
00072     RCC_ITConfig(RCC_IT_PLLRDY, ENABLE);
00073  #endif /* STM32F10X_CL */
00074 #endif /* SYSCLK_HSE */
00075
00076     /* Clear Clock Security System interrupt pending bit */
00077     RCC_ClearITPendingBit(RCC_IT_CSS);
00078
00079     /* Once HSE clock recover, the HSERDY interrupt is generated and in the RCC ISR
00080        routine the system clock will be reconfigured to its previous state (before
00081        HSE clock failure) */
00082   }
00083 }
00084
00085 /**
00086   * @brief  This function handles Hard Fault exception.
00087   * @param  None
00088   * @retval None
00089   */
00090 void HardFault_Handler(void)
00091 {
00092   /* Go to infinite loop when Hard Fault exception occurs */
00093   while (1)
00094   {
00095   }
00096 }
00097
00098 /**
00099   * @brief  This function handles Memory Manage exception.
00100   * @param  None
00101   * @retval None
00102   */
00103 void MemManage_Handler(void)
00104 {
00105   /* Go to infinite loop when Memory Manage exception occurs */
00106   while (1)
00107   {
00108   }
00109 }
00110
00111 /**
00112   * @brief  This function handles Bus Fault exception.
00113   * @param  None
00114   * @retval None
00115   */
00116 void BusFault_Handler(void)
00117 {
00118   /* Go to infinite loop when Bus Fault exception occurs */
00119   while (1)
00120   {
00121   }
00122 }
00123
00124 /**
00125   * @brief  This function handles Usage Fault exception.
00126   * @param  None
00127   * @retval None
00128   */
00129 void UsageFault_Handler(void)
00130 {
00131   /* Go to infinite loop when Usage Fault exception occurs */
00132   while (1)
00133   {
00134   }
00135 }
00136
00137 /**
00138   * @brief  This function handles SVCall exception.
00139   * @param  None
00140   * @retval None
00141   */
00142 void SVC_Handler(void)
00143 {
00144 }
00145
00146 /**
00147   * @brief  This function handles Debug Monitor exception.
00148   * @param  None
00149   * @retval None
00150   */
00151 void DebugMon_Handler(void)
00152 {
00153 }
00154
00155 /**
00156   * @brief  This function handles PendSV_Handler exception.
00157   * @param  None
00158   * @retval None
00159   */
00160 void PendSV_Handler(void)
00161 {
00162 }
00163
00164 /**
00165   * @brief  This function handles SysTick Handler.
00166   * @param  None
00167   * @retval None
00168   */
00169 void SysTick_Handler(void)
00170 {
00171 }
00172
00173 /******************************************************************************/
00174 /*            STM32F10x Peripherals Interrupt Handlers                        */
00175 /******************************************************************************/
00176
00177 /**
00178   * @brief  This function handles RCC interrupt request.
00179   * @param  None
00180   * @retval None
00181   */
00182 void RCC_IRQHandler(void)
00183 {
00184   if(RCC_GetITStatus(RCC_IT_HSERDY) != RESET)
00185   {
00186     /* Clear HSERDY interrupt pending bit */
00187     RCC_ClearITPendingBit(RCC_IT_HSERDY);
00188
00189     /* Check if the HSE clock is still available */
00190     if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
00191     {
00192 #ifdef SYSCLK_HSE
00193       /* Select HSE as system clock source */
00194       RCC_SYSCLKConfig(RCC_SYSCLKSource_HSE);
00195 #else
00196  #ifdef STM32F10X_CL
00197       /* Enable PLL2 */
00198       RCC_PLL2Cmd(ENABLE);
00199  #else
00200       /* Enable PLL: once the PLL is ready the PLLRDY interrupt is generated */
00201       RCC_PLLCmd(ENABLE);
00202  #endif /* STM32F10X_CL */
00203 #endif /* SYSCLK_HSE */
00204     }
00205   }
00206
00207 #ifdef STM32F10X_CL
00208   if(RCC_GetITStatus(RCC_IT_PLL2RDY) != RESET)
00209   {
00210     /* Clear PLL2RDY interrupt pending bit */
00211     RCC_ClearITPendingBit(RCC_IT_PLL2RDY);
00212
00213     /* Enable PLL: once the PLL is ready the PLLRDY interrupt is generated */
00214     RCC_PLLCmd(ENABLE);
00215   }
00216 #endif /* STM32F10X_CL */
00217
00218   if(RCC_GetITStatus(RCC_IT_PLLRDY) != RESET)
00219   {
00220     /* Clear PLLRDY interrupt pending bit */
00221     RCC_ClearITPendingBit(RCC_IT_PLLRDY);
00222
00223     /* Check if the PLL is still locked */
00224     if (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) != RESET)
00225     {
00226       /* Select PLL as system clock source */
00227       RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
00228     }
00229   }
00230 }
00231
00232 /******************************************************************************/
00233 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00234 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00235 /*  available peripheral interrupt handler's name please refer to the startup */
00236 /*  file (startup_stm32f10x_xx.s).                                            */
00237 /******************************************************************************/
00238
00239 /**
00240   * @brief  This function handles PPP interrupt request.
00241   * @param  None
00242   * @retval None
00243   */
00244 /*void PPP_IRQHandler(void)
00245 {
00246 }*/
00247
00248 /**
00249   * @}
00250   */
00251
00252 /**
00253   * @}
00254   */
00255
00256 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/stm32f10x_it.h

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00001 /**
00002   ******************************************************************************
00003   * @file    RCC/RCC_ClockConfig/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043 void RCC_IRQHandler(void);
00044
00045 #endif /* __STM32F10x_IT_H */
00046
00047 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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STM32F10x_StdPeriph_Examples/RTC/Calendar/main.c

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00001 /**
00002   ******************************************************************************
00003   * @file    RTC/Calendar/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x.h"
00024 #include "stm32_eval.h"
00025 #include <stdio.h>
00026
00027 /** @addtogroup STM32F10x_StdPeriph_Examples
00028   * @{
00029   */
00030
00031 /** @addtogroup RTC_Calendar
00032   * @{
00033   */
00034
00035 /* Private typedef -----------------------------------------------------------*/
00036 /* Private define ------------------------------------------------------------*/
00037 #define RTCClockOutput_Enable  /* RTC Clock/64 is output on tamper pin(PC.13) */
00038
00039 /* Private macro -------------------------------------------------------------*/
00040 /* Private variables ---------------------------------------------------------*/
00041 __IO uint32_t TimeDisplay = 0;
00042 USART_InitTypeDef USART_InitStructure;
00043
00044 /* Private function prototypes -----------------------------------------------*/
00045 void RTC_Configuration(void);
00046 void NVIC_Configuration(void);
00047 uint32_t Time_Regulate(void);
00048 void Time_Adjust(void);
00049 void Time_Show(void);
00050 void Time_Display(uint32_t TimeVar);
00051 uint8_t USART_Scanf(uint32_t value);
00052
00053 #ifdef __GNUC__
00054 /* With GCC/RAISONANCE, small printf (option LD Linker->Libraries->Small printf
00055    set to 'Yes') calls __io_putchar() */
00056 #define PUTCHAR_PROTOTYPE int __io_putchar(int ch)
00057 #else
00058 #define PUTCHAR_PROTOTYPE int fputc(int ch, FILE *f)
00059 #endif /* __GNUC__ */
00060
00061 /* Private functions ---------------------------------------------------------*/
00062
00063 /**
00064   * @brief  Main program.
00065   * @param  None
00066   * @retval None
00067   */
00068 int main(void)
00069 {
00070   /*!< At this stage the microcontroller clock setting is already configured,
00071        this is done through SystemInit() function which is called from startup
00072        file (startup_stm32f10x_xx.s) before to branch to application main.
00073        To reconfigure the default setting of SystemInit() function, refer to
00074        system_stm32f10x.c file
00075      */
00076
00077   /* Initialize LED1 mounted on STM3210X-EVAL board */
00078   STM_EVAL_LEDInit(LED1);
00079
00080   /* USARTx configured as follow:
00081         - BaudRate = 115200 baud
00082         - Word Length = 8 Bits
00083         - One Stop Bit
00084         - No parity
00085         - Hardware flow control disabled (RTS and CTS signals)
00086         - Receive and transmit enabled
00087   */
00088   USART_InitStructure.USART_BaudRate = 115200;
00089   USART_InitStructure.USART_WordLength = USART_WordLength_8b;
00090   USART_InitStructure.USART_StopBits = USART_StopBits_1;
00091   USART_InitStructure.USART_Parity = USART_Parity_No;
00092   USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
00093   USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
00094
00095   STM_EVAL_COMInit(COM1, &USART_InitStructure);
00096
00097
00098   /* NVIC configuration */
00099   NVIC_Configuration();
00100
00101   if (BKP_ReadBackupRegister(BKP_DR1) != 0xA5A5)
00102   {
00103     /* Backup data register value is not correct or not yet programmed (when
00104        the first time the program is executed) */
00105
00106     printf("\r\n\n RTC not yet configured....");
00107
00108     /* RTC Configuration */
00109     RTC_Configuration();
00110
00111     printf("\r\n RTC configured....");
00112
00113     /* Adjust time by values entered by the user on the hyperterminal */
00114     Time_Adjust();
00115
00116     BKP_WriteBackupRegister(BKP_DR1, 0xA5A5);
00117   }
00118   else
00119   {
00120     /* Check if the Power On Reset flag is set */
00121     if (RCC_GetFlagStatus(RCC_FLAG_PORRST) != RESET)
00122     {
00123       printf("\r\n\n Power On Reset occurred....");
00124     }
00125     /* Check if the Pin Reset flag is set */
00126     else if (RCC_GetFlagStatus(RCC_FLAG_PINRST) != RESET)
00127     {
00128       printf("\r\n\n External Reset occurred....");
00129     }
00130
00131     printf("\r\n No need to configure RTC....");
00132     /* Wait for RTC registers synchronization */
00133     RTC_WaitForSynchro();
00134
00135     /* Enable the RTC Second */
00136     RTC_ITConfig(RTC_IT_SEC, ENABLE);
00137     /* Wait until last write operation on RTC registers has finished */
00138     RTC_WaitForLastTask();
00139   }
00140
00141 #ifdef RTCClockOutput_Enable
00142   /* Enable PWR and BKP clocks */
00143   RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR | RCC_APB1Periph_BKP, ENABLE);
00144
00145   /* Allow access to BKP Domain */
00146   PWR_BackupAccessCmd(ENABLE);
00147
00148   /* Disable the Tamper Pin */
00149   BKP_TamperPinCmd(DISABLE); /* To output RTCCLK/64 on Tamper pin, the tamper
00150                                  functionality must be disabled */
00151
00152   /* Enable RTC Clock Output on Tamper Pin */
00153   BKP_RTCOutputConfig(BKP_RTCOutputSource_CalibClock);
00154 #endif
00155
00156   /* Clear reset flags */
00157   RCC_ClearFlag();
00158
00159   /* Display time in infinite loop */
00160   Time_Show();
00161 }
00162
00163
00164 /**
00165   * @brief  Configures the nested vectored interrupt controller.
00166   * @param  None
00167   * @retval None
00168   */
00169 void NVIC_Configuration(void)
00170 {
00171   NVIC_InitTypeDef NVIC_InitStructure;
00172
00173   /* Configure one bit for preemption priority */
00174   NVIC_PriorityGroupConfig(NVIC_PriorityGroup_1);
00175
00176   /* Enable the RTC Interrupt */
00177   NVIC_InitStructure.NVIC_IRQChannel = RTC_IRQn;
00178   NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
00179   NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
00180   NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
00181   NVIC_Init(&NVIC_InitStructure);
00182 }
00183
00184 /**
00185   * @brief  Configures the RTC.
00186   * @param  None
00187   * @retval None
00188   */
00189 void RTC_Configuration(void)
00190 {
00191   /* Enable PWR and BKP clocks */
00192   RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR | RCC_APB1Periph_BKP, ENABLE);
00193
00194   /* Allow access to BKP Domain */
00195   PWR_BackupAccessCmd(ENABLE);
00196
00197   /* Reset Backup Domain */
00198   BKP_DeInit();
00199
00200   /* Enable LSE */
00201   RCC_LSEConfig(RCC_LSE_ON);
00202   /* Wait till LSE is ready */
00203   while (RCC_GetFlagStatus(RCC_FLAG_LSERDY) == RESET)
00204   {}
00205
00206   /* Select LSE as RTC Clock Source */
00207   RCC_RTCCLKConfig(RCC_RTCCLKSource_LSE);
00208
00209   /* Enable RTC Clock */
00210   RCC_RTCCLKCmd(ENABLE);
00211
00212   /* Wait for RTC registers synchronization */
00213   RTC_WaitForSynchro();
00214
00215   /* Wait until last write operation on RTC registers has finished */
00216   RTC_WaitForLastTask();
00217
00218   /* Enable the RTC Second */
00219   RTC_ITConfig(RTC_IT_SEC, ENABLE);
00220
00221   /* Wait until last write operation on RTC registers has finished */
00222   RTC_WaitForLastTask();
00223
00224   /* Set RTC prescaler: set RTC period to 1sec */
00225   RTC_SetPrescaler(32767); /* RTC period = RTCCLK/RTC_PR = (32.768 KHz)/(32767+1) */
00226
00227   /* Wait until last write operation on RTC registers has finished */
00228   RTC_WaitForLastTask();
00229 }
00230
00231 /**
00232   * @brief  Returns the time entered by user, using Hyperterminal.
00233   * @param  None
00234   * @retval Current time RTC counter value
00235   */
00236 uint32_t Time_Regulate(void)
00237 {
00238   uint32_t Tmp_HH = 0xFF, Tmp_MM = 0xFF, Tmp_SS = 0xFF;
00239
00240   printf("\r\n==============Time Settings=====================================");
00241   printf("\r\n  Please Set Hours");
00242
00243   while (Tmp_HH == 0xFF)
00244   {
00245     Tmp_HH = USART_Scanf(23);
00246   }
00247   printf(":  %d", Tmp_HH);
00248   printf("\r\n  Please Set Minutes");
00249   while (Tmp_MM == 0xFF)
00250   {
00251     Tmp_MM = USART_Scanf(59);
00252   }
00253   printf(":  %d", Tmp_MM);
00254   printf("\r\n  Please Set Seconds");
00255   while (Tmp_SS == 0xFF)
00256   {
00257     Tmp_SS = USART_Scanf(59);
00258   }
00259   printf(":  %d", Tmp_SS);
00260
00261   /* Return the value to store in RTC counter register */
00262   return((Tmp_HH*3600 + Tmp_MM*60 + Tmp_SS));
00263 }
00264
00265 /**
00266   * @brief  Adjusts time.
00267   * @param  None
00268   * @retval None
00269   */
00270 void Time_Adjust(void)
00271 {
00272   /* Wait until last write operation on RTC registers has finished */
00273   RTC_WaitForLastTask();
00274   /* Change the current time */
00275   RTC_SetCounter(Time_Regulate());
00276   /* Wait until last write operation on RTC registers has finished */
00277   RTC_WaitForLastTask();
00278 }
00279
00280 /**
00281   * @brief  Displays the current time.
00282   * @param  TimeVar: RTC counter value.
00283   * @retval None
00284   */
00285 void Time_Display(uint32_t TimeVar)
00286 {
00287   uint32_t THH = 0, TMM = 0, TSS = 0;
00288
00289   /* Reset RTC Counter when Time is 23:59:59 */
00290   if (RTC_GetCounter() == 0x0001517F)
00291   {
00292      RTC_SetCounter(0x0);
00293      /* Wait until last write operation on RTC registers has finished */
00294      RTC_WaitForLastTask();
00295   }
00296
00297   /* Compute  hours */
00298   THH = TimeVar / 3600;
00299   /* Compute minutes */
00300   TMM = (TimeVar % 3600) / 60;
00301   /* Compute seconds */
00302   TSS = (TimeVar % 3600) % 60;
00303
00304   printf("Time: %0.2d:%0.2d:%0.2d\r", THH, TMM, TSS);
00305 }
00306
00307 /**
00308   * @brief  Shows the current time (HH:MM:SS) on the Hyperterminal.
00309   * @param  None
00310   * @retval None
00311   */
00312 void Time_Show(void)
00313 {
00314   printf("\n\r");
00315
00316   /* Infinite loop */
00317   while (1)
00318   {
00319     /* If 1s has been elapsed */
00320     if (TimeDisplay == 1)
00321     {
00322       /* Display current time */
00323       Time_Display(RTC_GetCounter());
00324       TimeDisplay = 0;
00325     }
00326   }
00327 }
00328
00329
00330 /**
00331   * @brief  Retargets the C library printf function to the USART.
00332   * @param  None
00333   * @retval None
00334   */
00335 PUTCHAR_PROTOTYPE
00336 {
00337   /* Place your implementation of fputc here */
00338   /* e.g. write a character to the USART */
00339   USART_SendData(EVAL_COM1, (uint8_t) ch);
00340
00341   /* Loop until the end of transmission */
00342   while (USART_GetFlagStatus(EVAL_COM1, USART_FLAG_TC) == RESET)
00343   {}
00344
00345   return ch;
00346 }
00347
00348 /**
00349   * @brief  Gets numeric values from the hyperterminal.
00350   * @param  None
00351   * @retval None
00352   */
00353 uint8_t USART_Scanf(uint32_t value)
00354 {
00355   uint32_t index = 0;
00356   uint32_t tmp[2] = {0, 0};
00357
00358   while (index < 2)
00359   {
00360     /* Loop until RXNE = 1 */
00361     while (USART_GetFlagStatus(EVAL_COM1, USART_FLAG_RXNE) == RESET)
00362     {}
00363     tmp[index++] = (USART_ReceiveData(EVAL_COM1));
00364     if ((tmp[index - 1] < 0x30) || (tmp[index - 1] > 0x39))
00365     {
00366       printf("\n\rPlease enter valid number between 0 and 9");
00367       index--;
00368     }
00369   }
00370   /* Calculate the Corresponding value */
00371   index = (tmp[1] - 0x30) + ((tmp[0] - 0x30) * 10);
00372   /* Checks */
00373   if (index > value)
00374   {
00375     printf("\n\rPlease enter valid number between 0 and %d", value);
00376     return 0xFF;
00377   }
00378   return index;
00379 }
00380
00381 #ifdef  USE_FULL_ASSERT
00382
00383 /**
00384   * @brief  Reports the name of the source file and the source line number
00385   *         where the assert_param error has occurred.
00386   * @param  file: pointer to the source file name
00387   * @param  line: assert_param error line source number
00388   * @retval None
00389   */
00390 void assert_failed(uint8_t* file, uint32_t line)
00391 {
00392   /* User can add his own implementation to report the file name and line number,
00393      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00394
00395   /* Infinite loop */
00396   while (1)
00397   {}
00398 }
00399
00400 #endif
00401
00402 /**
00403   * @}
00404   */
00405
00406 /**
00407   * @}
00408   */
00409
00410 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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STM32F10x_StdPeriph_Examples/RTC/Calendar/stm32f10x_conf.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    RTC/Calendar/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052
00053 /* Exported types ------------------------------------------------------------*/
00054 /* Exported constants --------------------------------------------------------*/
00055 /* Uncomment the line below to expanse the "assert_param" macro in the
00056    Standard Peripheral Library drivers code */
00057 /* #define USE_FULL_ASSERT    1 */
00058
00059 /* Exported macro ------------------------------------------------------------*/
00060 #ifdef  USE_FULL_ASSERT
00061
00062 /**
00063   * @brief  The assert_param macro is used for function's parameters check.
00064   * @param  expr: If expr is false, it calls assert_failed function which reports
00065   *         the name of the source file and the source line number of the call
00066   *         that failed. If expr is true, it returns no value.
00067   * @retval None
00068   */
00069   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00070 /* Exported functions ------------------------------------------------------- */
00071   void assert_failed(uint8_t* file, uint32_t line);
00072 #else
00073   #define assert_param(expr) ((void)0)
00074 #endif /* USE_FULL_ASSERT */
00075
00076 #endif /* __STM32F10x_CONF_H */
00077
00078 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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STM32F10x_StdPeriph_Examples/RTC/Calendar/stm32f10x_it.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    RTC/Calendar/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and
00009   *          peripherals interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026 #include "stm32_eval.h"
00027
00028 /** @addtogroup STM32F10x_StdPeriph_Examples
00029   * @{
00030   */
00031
00032 /** @addtogroup RTC_Calendar
00033   * @{
00034   */
00035
00036 /* Private typedef -----------------------------------------------------------*/
00037 /* Private define ------------------------------------------------------------*/
00038 /* Private macro -------------------------------------------------------------*/
00039 /* Private variables ---------------------------------------------------------*/
00040 extern __IO uint32_t TimeDisplay;
00041
00042 /* Private function prototypes -----------------------------------------------*/
00043 /* Private functions ---------------------------------------------------------*/
00044
00045 /******************************************************************************/
00046 /*            Cortex-M3 Processor Exceptions Handlers                         */
00047 /******************************************************************************/
00048
00049 /**
00050   * @brief  This function handles NMI exception.
00051   * @param  None
00052   * @retval None
00053   */
00054 void NMI_Handler(void)
00055 {
00056 }
00057
00058 /**
00059   * @brief  This function handles Hard Fault exception.
00060   * @param  None
00061   * @retval None
00062   */
00063 void HardFault_Handler(void)
00064 {
00065   /* Go to infinite loop when Hard Fault exception occurs */
00066   while (1)
00067   {}
00068 }
00069
00070 /**
00071   * @brief  This function handles Memory Manage exception.
00072   * @param  None
00073   * @retval None
00074   */
00075 void MemManage_Handler(void)
00076 {
00077   /* Go to infinite loop when Memory Manage exception occurs */
00078   while (1)
00079   {}
00080 }
00081
00082 /**
00083   * @brief  This function handles Bus Fault exception.
00084   * @param  None
00085   * @retval None
00086   */
00087 void BusFault_Handler(void)
00088 {
00089   /* Go to infinite loop when Bus Fault exception occurs */
00090   while (1)
00091   {}
00092 }
00093
00094 /**
00095   * @brief  This function handles Usage Fault exception.
00096   * @param  None
00097   * @retval None
00098   */
00099 void UsageFault_Handler(void)
00100 {
00101   /* Go to infinite loop when Usage Fault exception occurs */
00102   while (1)
00103   {}
00104 }
00105
00106 /**
00107   * @brief  This function handles Debug Monitor exception.
00108   * @param  None
00109   * @retval None
00110   */
00111 void DebugMon_Handler(void)
00112 {
00113 }
00114
00115 /**
00116   * @brief  This function handles SVCall exception.
00117   * @param  None
00118   * @retval None
00119   */
00120 void SVC_Handler(void)
00121 {
00122 }
00123
00124 /**
00125   * @brief  This function handles PendSV_Handler exception.
00126   * @param  None
00127   * @retval None
00128   */
00129 void PendSV_Handler(void)
00130 {
00131 }
00132
00133 /**
00134   * @brief  This function handles SysTick Handler.
00135   * @param  None
00136   * @retval None
00137   */
00138 void SysTick_Handler(void)
00139 {
00140 }
00141
00142 /******************************************************************************/
00143 /*            STM32F10x Peripherals Interrupt Handlers                        */
00144 /******************************************************************************/
00145
00146 /**
00147   * @brief  This function handles RTC global interrupt request.
00148   * @param  None
00149   * @retval None
00150   */
00151 void RTC_IRQHandler(void)
00152 {
00153   if (RTC_GetITStatus(RTC_IT_SEC) != RESET)
00154   {
00155     /* Clear the RTC Second interrupt */
00156     RTC_ClearITPendingBit(RTC_IT_SEC);
00157
00158     /* Toggle LED1 */
00159     STM_EVAL_LEDToggle(LED1);
00160
00161     /* Enable time update */
00162     TimeDisplay = 1;
00163
00164     /* Wait until last write operation on RTC registers has finished */
00165     RTC_WaitForLastTask();
00166
00167   }
00168 }
00169
00170 /******************************************************************************/
00171 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00172 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00173 /*  available peripheral interrupt handler's name please refer to the startup */
00174 /*  file (startup_stm32f10x_xx.s).                                            */
00175 /******************************************************************************/
00176
00177 /**
00178   * @brief  This function handles PPP interrupt request.
00179   * @param  None
00180   * @retval None
00181   */
00182 /*void PPP_IRQHandler(void)
00183 {
00184 }*/
00185
00186 /**
00187   * @}
00188   */
00189
00190 /**
00191   * @}
00192   */
00193
00194 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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STM32F10x_StdPeriph_Examples/RTC/Calendar/stm32f10x_it.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    RTC/Calendar/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043 void RTC_IRQHandler(void);
00044
00045 #endif /* __STM32F10x_IT_H */
00046
00047 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/main.c

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00001 /**
00002   ******************************************************************************
00003   * @file    RTC/LSI_Calib/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "main.h"
00024 #include <stdio.h>
00025
00026 /** @addtogroup STM32F10x_StdPeriph_Examples
00027   * @{
00028   */
00029
00030 /** @addtogroup RTC_LSI_Calib
00031   * @{
00032   */
00033
00034 /* Private typedef -----------------------------------------------------------*/
00035 /* Private define ------------------------------------------------------------*/
00036 #define RTCClockOutput_Enable  /* RTC Clock/64 is output on tamper pin(PC.13) */
00037
00038 /* Private macro -------------------------------------------------------------*/
00039 /* Private variables ---------------------------------------------------------*/
00040
00041 TIM_TimeBaseInitTypeDef  TIM_TimeBaseStructure;
00042 TIM_ICInitTypeDef  TIM_ICInitStructure;
00043 RCC_ClocksTypeDef RCC_Clocks;
00044 __IO uint32_t PeriodValue = 0,  LsiFreq = 0;
00045 __IO uint32_t OperationComplete = 0;
00046
00047 /* Private function prototypes -----------------------------------------------*/
00048 void RTC_Configuration(void);
00049 void NVIC_Configuration(void);
00050
00051 /* Private functions ---------------------------------------------------------*/
00052
00053 /**
00054   * @brief  Main program.
00055   * @param  None
00056   * @retval None
00057   */
00058 int main(void)
00059 {
00060   /*!< At this stage the microcontroller clock setting is already configured,
00061        this is done through SystemInit() function which is called from startup
00062        file (startup_stm32f10x_xx.s) before to branch to application main.
00063        To reconfigure the default setting of SystemInit() function, refer to
00064        system_stm32f10x.c file
00065      */
00066
00067   /* Initialize LEDs and Key Button mounted on STM3210X-EVAL board */
00068   STM_EVAL_LEDInit(LED1);
00069   STM_EVAL_LEDInit(LED2);
00070   STM_EVAL_PBInit(BUTTON_KEY, BUTTON_MODE_GPIO);
00071
00072   /* RTC Configuration */
00073   RTC_Configuration();
00074
00075   /* Wait until Key Push button is pressed */
00076   while (STM_EVAL_PBGetState(BUTTON_KEY) != 0)
00077   {
00078   }
00079
00080   /* Get the Frequency value */
00081   RCC_GetClocksFreq(&RCC_Clocks);
00082
00083   /* Enable TIM5 APB1 clocks */
00084   RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM5, ENABLE);
00085
00086   /* Connect internally the TM5_CH4 Input Capture to the LSI clock output */
00087   GPIO_PinRemapConfig(GPIO_Remap_TIM5CH4_LSI, ENABLE);
00088
00089   /* TIM5 Time base configuration */
00090   TIM_TimeBaseStructure.TIM_Prescaler = 0;
00091   TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
00092   TIM_TimeBaseStructure.TIM_Period = 0xFFFF;
00093   TIM_TimeBaseStructure.TIM_ClockDivision = TIM_CKD_DIV1;
00094   TIM_TimeBaseInit(TIM5, &TIM_TimeBaseStructure);
00095
00096   /* TIM5 Channel4 Input capture Mode configuration */
00097   TIM_ICInitStructure.TIM_Channel = TIM_Channel_4;
00098   TIM_ICInitStructure.TIM_ICPolarity = TIM_ICPolarity_Rising;
00099   TIM_ICInitStructure.TIM_ICSelection = TIM_ICSelection_DirectTI;
00100   TIM_ICInitStructure.TIM_ICPrescaler = TIM_ICPSC_DIV1;
00101   TIM_ICInitStructure.TIM_ICFilter = 0;
00102   TIM_ICInit(TIM5, &TIM_ICInitStructure);
00103
00104   /* Reinitialize the index for the interrupt */
00105   OperationComplete = 0;
00106
00107   /* Enable the TIM5 Input Capture counter */
00108   TIM_Cmd(TIM5, ENABLE);
00109   /* Reset all TIM5 flags */
00110   TIM5->SR = 0;
00111   /* Enable the TIM5 channel 4 */
00112   TIM_ITConfig(TIM5, TIM_IT_CC4, ENABLE);
00113
00114   /* NVIC configuration */
00115   NVIC_Configuration();
00116
00117   /* Wait the TIM5 measuring operation to be completed */
00118   while (OperationComplete != 2)
00119   {}
00120
00121   /* Compute the actual frequency of the LSI. (TIM5_CLK = 2 * PCLK1)  */
00122   if (PeriodValue != 0)
00123   {
00124 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00125     LsiFreq = (uint32_t)((uint32_t)(RCC_Clocks.PCLK1_Frequency) / (uint32_t)PeriodValue);
00126 #else
00127     LsiFreq = (uint32_t)((uint32_t)(RCC_Clocks.PCLK1_Frequency * 2) / (uint32_t)PeriodValue);
00128 #endif
00129   }
00130
00131   /* Adjust the RTC prescaler value */
00132   RTC_SetPrescaler(LsiFreq - 1);
00133
00134   /* Wait until last write operation on RTC registers has finished */
00135   RTC_WaitForLastTask();
00136
00137   /* Turn on LED2 */
00138   STM_EVAL_LEDOn(LED2);
00139
00140   while (1)
00141   {
00142     /* Infinite loop */
00143   }
00144
00145 }
00146
00147 /**
00148   * @brief  Configures the nested vectored interrupt controller.
00149   * @param  None
00150   * @retval None
00151   */
00152 void NVIC_Configuration(void)
00153 {
00154   NVIC_InitTypeDef NVIC_InitStructure;
00155
00156   /* Configure one bit for preemption priority */
00157   NVIC_PriorityGroupConfig(NVIC_PriorityGroup_1);
00158
00159   /* Enable the RTC Interrupt */
00160   NVIC_InitStructure.NVIC_IRQChannel = RTC_IRQn;
00161   NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
00162   NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
00163   NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
00164   NVIC_Init(&NVIC_InitStructure);
00165
00166   /* Enable the TIM5 Interrupt */
00167   NVIC_InitStructure.NVIC_IRQChannel = TIM5_IRQn;
00168   NVIC_InitStructure.NVIC_IRQChannelSubPriority = 2;
00169   NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
00170   NVIC_Init(&NVIC_InitStructure);
00171 }
00172
00173 /**
00174   * @brief  Configures the RTC.
00175   * @param  None
00176   * @retval None
00177   */
00178 void RTC_Configuration(void)
00179 {
00180   /* Enable PWR and BKP clocks */
00181   RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR | RCC_APB1Periph_BKP, ENABLE);
00182
00183   /* Allow access to BKP Domain */
00184   PWR_BackupAccessCmd(ENABLE);
00185
00186   /* Reset Backup Domain */
00187   BKP_DeInit();
00188
00189   /* Enable the LSI OSC */
00190   RCC_LSICmd(ENABLE);
00191   /* Wait till LSI is ready */
00192   while (RCC_GetFlagStatus(RCC_FLAG_LSIRDY) == RESET)
00193   {}
00194   /* Select the RTC Clock Source */
00195   RCC_RTCCLKConfig(RCC_RTCCLKSource_LSI);
00196
00197   /* Enable RTC Clock */
00198   RCC_RTCCLKCmd(ENABLE);
00199
00200   /* Wait for RTC registers synchronization */
00201   RTC_WaitForSynchro();
00202
00203   /* Wait until last write operation on RTC registers has finished */
00204   RTC_WaitForLastTask();
00205
00206   /* Enable the RTC Second */
00207   RTC_ITConfig(RTC_IT_SEC, ENABLE);
00208
00209   /* Wait until last write operation on RTC registers has finished */
00210   RTC_WaitForLastTask();
00211
00212   /* Set RTC prescaler: set RTC period to 1sec */
00213   RTC_SetPrescaler(40000);
00214
00215   /* Wait until last write operation on RTC registers has finished */
00216   RTC_WaitForLastTask();
00217
00218   /* To output second signal on Tamper pin, the tamper functionality
00219        must be disabled (by default this functionality is disabled) */
00220   BKP_TamperPinCmd(DISABLE);
00221
00222   /* Enable the RTC Second Output on Tamper Pin */
00223   BKP_RTCOutputConfig(BKP_RTCOutputSource_Second);
00224 }
00225
00226 /**
00227   * @brief  Increments OperationComplete variable and return its value
00228   *         before increment operation.
00229   * @param  None
00230   * @retval OperationComplete value before increment
00231   */
00232 uint32_t IncrementVar_OperationComplete(void)
00233 {
00234   OperationComplete++;
00235
00236   return (uint32_t)(OperationComplete -1);
00237 }
00238
00239 /**
00240   * @brief  Returns OperationComplete value.
00241   * @param  None
00242   * @retval OperationComplete value
00243   */
00244 uint32_t GetVar_OperationComplete(void)
00245 {
00246   return (uint32_t)OperationComplete;
00247 }
00248
00249 /**
00250   * @brief  Sets the PeriodValue variable with input parameter.
00251   * @param  Value: Value of PeriodValue to be set.
00252   * @retval None
00253   */
00254 void SetVar_PeriodValue(uint32_t Value)
00255 {
00256   PeriodValue = (uint32_t)(Value);
00257 }
00258
00259 #ifdef  USE_FULL_ASSERT
00260
00261 /**
00262   * @brief  Reports the name of the source file and the source line number
00263   *         where the assert_param error has occurred.
00264   * @param  file: pointer to the source file name
00265   * @param  line: assert_param error line source number
00266   * @retval None
00267   */
00268 void assert_failed(uint8_t* file, uint32_t line)
00269 {
00270   /* User can add his own implementation to report the file name and line number,
00271      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00272
00273   /* Infinite loop */
00274   while (1)
00275   {}
00276 }
00277
00278 #endif
00279
00280 /**
00281   * @}
00282   */
00283
00284 /**
00285   * @}
00286   */
00287
00288 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_conf.h

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00001 /**
00002   ******************************************************************************
00003   * @file RTC/LSI_Calib/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052 /* Exported types ------------------------------------------------------------*/
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Uncomment the line below to expanse the "assert_param" macro in the
00055    Standard Peripheral Library drivers code */
00056 /* #define USE_FULL_ASSERT    1 */
00057
00058 /* Exported macro ------------------------------------------------------------*/
00059 #ifdef  USE_FULL_ASSERT
00060
00061 /**
00062   * @brief  The assert_param macro is used for function's parameters check.
00063   * @param  expr: If expr is false, it calls assert_failed function which reports
00064   *         the name of the source file and the source line number of the call
00065   *         that failed. If expr is true, it returns no value.
00066   * @retval None
00067   */
00068   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00069 /* Exported functions ------------------------------------------------------- */
00070   void assert_failed(uint8_t* file, uint32_t line);
00071 #else
00072   #define assert_param(expr) ((void)0)
00073 #endif /* USE_FULL_ASSERT */
00074
00075 #endif /* __STM32F10x_CONF_H */
00076
00077 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_it.c

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00001 /**
00002   ******************************************************************************
00003   * @file    RTC/LSI_Calib/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and peripherals
00009   *          interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026 #include "main.h"
00027
00028 /** @addtogroup STM32F10x_StdPeriph_Examples
00029   * @{
00030   */
00031
00032 /** @addtogroup RTC_LSI_Calib
00033   * @{
00034   */
00035
00036 /* Private typedef -----------------------------------------------------------*/
00037 /* Private define ------------------------------------------------------------*/
00038 /* Private macro -------------------------------------------------------------*/
00039 /* Private variables ---------------------------------------------------------*/
00040 uint16_t tmpCC4[2] = {0, 0};
00041
00042 /* Private function prototypes -----------------------------------------------*/
00043 /* Private functions ---------------------------------------------------------*/
00044
00045 /******************************************************************************/
00046 /*            Cortex-M3 Processor Exceptions Handlers                         */
00047 /******************************************************************************/
00048
00049 /**
00050   * @brief  This function handles NMI exception.
00051   * @param  None
00052   * @retval None
00053   */
00054 void NMI_Handler(void)
00055 {
00056 }
00057
00058 /**
00059   * @brief  This function handles Hard Fault exception.
00060   * @param  None
00061   * @retval None
00062   */
00063 void HardFault_Handler(void)
00064 {
00065   /* Go to infinite loop when Hard Fault exception occurs */
00066   while (1)
00067   {}
00068 }
00069
00070 /**
00071   * @brief  This function handles Memory Manage exception.
00072   * @param  None
00073   * @retval None
00074   */
00075 void MemManage_Handler(void)
00076 {
00077   /* Go to infinite loop when Memory Manage exception occurs */
00078   while (1)
00079   {}
00080 }
00081
00082 /**
00083   * @brief  This function handles Bus Fault exception.
00084   * @param  None
00085   * @retval None
00086   */
00087 void BusFault_Handler(void)
00088 {
00089   /* Go to infinite loop when Bus Fault exception occurs */
00090   while (1)
00091   {}
00092 }
00093
00094 /**
00095   * @brief  This function handles Usage Fault exception.
00096   * @param  None
00097   * @retval None
00098   */
00099 void UsageFault_Handler(void)
00100 {
00101   /* Go to infinite loop when Usage Fault exception occurs */
00102   while (1)
00103   {}
00104 }
00105
00106 /**
00107   * @brief  This function handles Debug Monitor exception.
00108   * @param  None
00109   * @retval None
00110   */
00111 void DebugMon_Handler(void)
00112 {
00113 }
00114
00115 /**
00116   * @brief  This function handles SVCall exception.
00117   * @param  None
00118   * @retval None
00119   */
00120 void SVC_Handler(void)
00121 {
00122 }
00123
00124 /**
00125   * @brief  This function handles PendSV_Handler exception.
00126   * @param  None
00127   * @retval None
00128   */
00129 void PendSV_Handler(void)
00130 {
00131 }
00132
00133 /**
00134   * @brief  This function handles SysTick Handler.
00135   * @param  None
00136   * @retval None
00137   */
00138 void SysTick_Handler(void)
00139 {
00140 }
00141
00142 /******************************************************************************/
00143 /*            STM32F10x Peripherals Interrupt Handlers                        */
00144 /******************************************************************************/
00145
00146 /**
00147   * @brief  This function handles RTC global interrupt request.
00148   * @param  None
00149   * @retval None
00150   */
00151 void RTC_IRQHandler(void)
00152 {
00153   if (RTC_GetITStatus(RTC_IT_SEC) != RESET)
00154   {
00155     /* Toggle LED1 */
00156     STM_EVAL_LEDToggle(LED1);
00157
00158     /* Clear Interrupt pending bit */
00159     RTC_ClearITPendingBit(RTC_FLAG_SEC);
00160   }
00161 }
00162
00163 /**
00164   * @brief  This function handles TIM5 global interrupt request.
00165   * @param  None
00166   * @retval None
00167   */
00168 void TIM5_IRQHandler(void)
00169 {
00170   uint32_t tmp = 0;
00171
00172   if (TIM_GetITStatus(TIM5, TIM_IT_CC4) == SET)
00173   {
00174     tmpCC4[IncrementVar_OperationComplete()] = (uint16_t)(TIM5->CCR4);
00175
00176     TIM_ClearITPendingBit(TIM5, TIM_IT_CC4);
00177
00178     if (GetVar_OperationComplete() >= 2)
00179     {
00180       /* Compute the period length */
00181       tmp = (uint16_t)(tmpCC4[1] - tmpCC4[0] + 1);
00182       SetVar_PeriodValue(tmp);
00183
00184       /* Disable the interrupt */
00185       TIM_ITConfig(TIM5, TIM_IT_CC4, DISABLE);
00186       TIM_Cmd(TIM5, DISABLE);
00187     }
00188   }
00189 }
00190
00191 /******************************************************************************/
00192 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00193 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00194 /*  available peripheral interrupt handler's name please refer to the startup */
00195 /*  file (startup_stm32f10x_xx.s).                                            */
00196 /******************************************************************************/
00197
00198 /**
00199   * @brief  This function handles PPP interrupt request.
00200   * @param  None
00201   * @retval None
00202   */
00203 /*void PPP_IRQHandler(void)
00204 {
00205 }*/
00206
00207 /**
00208   * @}
00209   */
00210
00211 /**
00212   * @}
00213   */
00214
00215 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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  • LSI_Calib

STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_it.h

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00001 /**
00002   ******************************************************************************
00003   * @file    RTC/LSI_Calib/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043 void RTC_IRQHandler(void);
00044 void TIM5_IRQHandler(void);
00045
00046 #endif /* __STM32F10x_IT_H */
00047
00048 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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STM32F10x_StdPeriph_Examples/SDIO/uSDCard/main.c

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00001 /**
00002   ******************************************************************************
00003   * @file    SDIO/uSDCard/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x.h"
00024 #include "stm32_eval_sdio_sd.h"
00025
00026 /** @addtogroup STM32F10x_StdPeriph_Examples
00027   * @{
00028   */
00029
00030 /** @addtogroup SDIO_uSDCard
00031   * @{
00032   */
00033
00034 /* Private typedef -----------------------------------------------------------*/
00035 typedef enum {FAILED = 0, PASSED = !FAILED} TestStatus;
00036
00037 /* Private define ------------------------------------------------------------*/
00038 #define BLOCK_SIZE            512 /* Block Size in Bytes */
00039
00040 #define NUMBER_OF_BLOCKS      32  /* For Multi Blocks operation (Read/Write) */
00041 #define MULTI_BUFFER_SIZE    (BLOCK_SIZE * NUMBER_OF_BLOCKS)
00042
00043 #define SD_OPERATION_ERASE          0
00044 #define SD_OPERATION_BLOCK          1
00045 #define SD_OPERATION_MULTI_BLOCK    2
00046 #define SD_OPERATION_END            3
00047
00048 /* Private macro -------------------------------------------------------------*/
00049 /* Private variables ---------------------------------------------------------*/
00050 uint8_t Buffer_Block_Tx[BLOCK_SIZE], Buffer_Block_Rx[BLOCK_SIZE];
00051 uint8_t Buffer_MultiBlock_Tx[MULTI_BUFFER_SIZE], Buffer_MultiBlock_Rx[MULTI_BUFFER_SIZE];
00052 volatile TestStatus EraseStatus = FAILED, TransferStatus1 = FAILED, TransferStatus2 = FAILED;
00053 SD_Error Status = SD_OK;
00054 __IO uint32_t SDCardOperation = SD_OPERATION_ERASE;
00055
00056 /* Private function prototypes -----------------------------------------------*/
00057 void NVIC_Configuration(void);
00058 void SD_EraseTest(void);
00059 void SD_SingleBlockTest(void);
00060 void SD_MultiBlockTest(void);
00061 void Fill_Buffer(uint8_t *pBuffer, uint32_t BufferLength, uint32_t Offset);
00062 TestStatus Buffercmp(uint8_t* pBuffer1, uint8_t* pBuffer2, uint32_t BufferLength);
00063 TestStatus eBuffercmp(uint8_t* pBuffer, uint32_t BufferLength);
00064
00065 /* Private functions ---------------------------------------------------------*/
00066
00067 /**
00068   * @brief  Main program.
00069   * @param  None
00070   * @retval None
00071   */
00072 int main(void)
00073 {
00074   /*!< At this stage the microcontroller clock setting is already configured,
00075        this is done through SystemInit() function which is called from startup
00076        file (startup_stm32f10x_xx.s) before to branch to application main.
00077        To reconfigure the default setting of SystemInit() function, refer to
00078        system_stm32f10x.c file
00079      */
00080
00081   /* Initialize LEDs available on STM3210X-EVAL board *************************/
00082   STM_EVAL_LEDInit(LED1);
00083   STM_EVAL_LEDInit(LED2);
00084   STM_EVAL_LEDInit(LED3);
00085   STM_EVAL_LEDInit(LED4);
00086
00087   /* Interrupt Config */
00088   NVIC_Configuration();
00089
00090   /*------------------------------ SD Init ---------------------------------- */
00091   if((Status = SD_Init()) != SD_OK)
00092   {
00093     STM_EVAL_LEDOn(LED4);
00094   }
00095
00096   while((Status == SD_OK) && (SDCardOperation != SD_OPERATION_END) && (SD_Detect()== SD_PRESENT))
00097   {
00098     switch(SDCardOperation)
00099     {
00100       /*-------------------------- SD Erase Test ---------------------------- */
00101       case (SD_OPERATION_ERASE):
00102       {
00103         SD_EraseTest();
00104         SDCardOperation = SD_OPERATION_BLOCK;
00105         break;
00106       }
00107       /*-------------------------- SD Single Block Test --------------------- */
00108       case (SD_OPERATION_BLOCK):
00109       {
00110         SD_SingleBlockTest();
00111         SDCardOperation = SD_OPERATION_MULTI_BLOCK;
00112         break;
00113       }
00114       /*-------------------------- SD Multi Blocks Test --------------------- */
00115       case (SD_OPERATION_MULTI_BLOCK):
00116       {
00117         SD_MultiBlockTest();
00118         SDCardOperation = SD_OPERATION_END;
00119         break;
00120       }
00121     }
00122   }
00123
00124   /* Infinite loop */
00125   while (1)
00126   {}
00127 }
00128
00129 /**
00130   * @brief  Configures SDIO IRQ channel.
00131   * @param  None
00132   * @retval None
00133   */
00134 void NVIC_Configuration(void)
00135 {
00136   NVIC_InitTypeDef NVIC_InitStructure;
00137
00138   /* Configure the NVIC Preemption Priority Bits */
00139   NVIC_PriorityGroupConfig(NVIC_PriorityGroup_1);
00140
00141   NVIC_InitStructure.NVIC_IRQChannel = SDIO_IRQn;
00142   NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
00143   NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
00144   NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
00145   NVIC_Init(&NVIC_InitStructure);
00146 }
00147
00148 /**
00149   * @brief  Tests the SD card erase operation.
00150   * @param  None
00151   * @retval None
00152   */
00153 void SD_EraseTest(void)
00154 {
00155   /*------------------- Block Erase ------------------------------------------*/
00156   if (Status == SD_OK)
00157   {
00158     /* Erase NumberOfBlocks Blocks of WRITE_BL_LEN(512 Bytes) */
00159     Status = SD_Erase(0x00, (BLOCK_SIZE * NUMBER_OF_BLOCKS));
00160   }
00161
00162   if (Status == SD_OK)
00163   {
00164     Status = SD_ReadMultiBlocks(Buffer_MultiBlock_Rx, 0x00, BLOCK_SIZE, NUMBER_OF_BLOCKS);
00165
00166     /* Check if the Transfer is finished */
00167     Status = SD_WaitReadOperation();
00168
00169     /* Wait until end of DMA transfer */
00170     while(SD_GetStatus() != SD_TRANSFER_OK);
00171   }
00172
00173   /* Check the correctness of erased blocks */
00174   if (Status == SD_OK)
00175   {
00176     EraseStatus = eBuffercmp(Buffer_MultiBlock_Rx, MULTI_BUFFER_SIZE);
00177   }
00178
00179   if(EraseStatus == PASSED)
00180   {
00181     STM_EVAL_LEDOn(LED1);
00182   }
00183   else
00184   {
00185     STM_EVAL_LEDOff(LED1);
00186     STM_EVAL_LEDOn(LED4);
00187   }
00188 }
00189
00190 /**
00191   * @brief  Tests the SD card Single Blocks operations.
00192   * @param  None
00193   * @retval None
00194   */
00195 void SD_SingleBlockTest(void)
00196 {
00197   /*------------------- Block Read/Write --------------------------*/
00198   /* Fill the buffer to send */
00199   Fill_Buffer(Buffer_Block_Tx, BLOCK_SIZE, 0x320F);
00200
00201   if (Status == SD_OK)
00202   {
00203     /* Write block of 512 bytes on address 0 */
00204     Status = SD_WriteBlock(Buffer_Block_Tx, 0x00, BLOCK_SIZE);
00205     /* Check if the Transfer is finished */
00206     Status = SD_WaitWriteOperation();
00207     while(SD_GetStatus() != SD_TRANSFER_OK);
00208   }
00209
00210   if (Status == SD_OK)
00211   {
00212     /* Read block of 512 bytes from address 0 */
00213     Status = SD_ReadBlock(Buffer_Block_Rx, 0x00, BLOCK_SIZE);
00214     /* Check if the Transfer is finished */
00215     Status = SD_WaitReadOperation();
00216     while(SD_GetStatus() != SD_TRANSFER_OK);
00217   }
00218
00219   /* Check the correctness of written data */
00220   if (Status == SD_OK)
00221   {
00222     TransferStatus1 = Buffercmp(Buffer_Block_Tx, Buffer_Block_Rx, BLOCK_SIZE);
00223   }
00224
00225   if(TransferStatus1 == PASSED)
00226   {
00227     STM_EVAL_LEDOn(LED2);
00228   }
00229   else
00230   {
00231     STM_EVAL_LEDOff(LED2);
00232     STM_EVAL_LEDOn(LED4);
00233   }
00234 }
00235
00236 /**
00237   * @brief  Tests the SD card Multiple Blocks operations.
00238   * @param  None
00239   * @retval None
00240   */
00241 void SD_MultiBlockTest(void)
00242 {
00243   /*--------------- Multiple Block Read/Write ---------------------*/
00244   /* Fill the buffer to send */
00245   Fill_Buffer(Buffer_MultiBlock_Tx, MULTI_BUFFER_SIZE, 0x0);
00246
00247   if (Status == SD_OK)
00248   {
00249     /* Write multiple block of many bytes on address 0 */
00250     Status = SD_WriteMultiBlocks(Buffer_MultiBlock_Tx, 0x00, BLOCK_SIZE, NUMBER_OF_BLOCKS);
00251     /* Check if the Transfer is finished */
00252     Status = SD_WaitWriteOperation();
00253     while(SD_GetStatus() != SD_TRANSFER_OK);
00254   }
00255
00256   if (Status == SD_OK)
00257   {
00258     /* Read block of many bytes from address 0 */
00259     Status = SD_ReadMultiBlocks(Buffer_MultiBlock_Rx, 0x00, BLOCK_SIZE, NUMBER_OF_BLOCKS);
00260     /* Check if the Transfer is finished */
00261     Status = SD_WaitReadOperation();
00262     while(SD_GetStatus() != SD_TRANSFER_OK);
00263   }
00264
00265   /* Check the correctness of written data */
00266   if (Status == SD_OK)
00267   {
00268     TransferStatus2 = Buffercmp(Buffer_MultiBlock_Tx, Buffer_MultiBlock_Rx, MULTI_BUFFER_SIZE);
00269   }
00270
00271   if(TransferStatus2 == PASSED)
00272   {
00273     STM_EVAL_LEDOn(LED3);
00274   }
00275   else
00276   {
00277     STM_EVAL_LEDOff(LED3);
00278     STM_EVAL_LEDOn(LED4);
00279   }
00280 }
00281
00282 /**
00283   * @brief  Compares two buffers.
00284   * @param  pBuffer1, pBuffer2: buffers to be compared.
00285   * @param  BufferLength: buffer's length
00286   * @retval PASSED: pBuffer1 identical to pBuffer2
00287   *         FAILED: pBuffer1 differs from pBuffer2
00288   */
00289 TestStatus Buffercmp(uint8_t* pBuffer1, uint8_t* pBuffer2, uint32_t BufferLength)
00290 {
00291   while (BufferLength--)
00292   {
00293     if (*pBuffer1 != *pBuffer2)
00294     {
00295       return FAILED;
00296     }
00297
00298     pBuffer1++;
00299     pBuffer2++;
00300   }
00301
00302   return PASSED;
00303 }
00304
00305 /**
00306   * @brief  Fills buffer with user predefined data.
00307   * @param  pBuffer: pointer on the Buffer to fill
00308   * @param  BufferLength: size of the buffer to fill
00309   * @param  Offset: first value to fill on the Buffer
00310   * @retval None
00311   */
00312 void Fill_Buffer(uint8_t *pBuffer, uint32_t BufferLength, uint32_t Offset)
00313 {
00314   uint16_t index = 0;
00315
00316   /* Put in global buffer same values */
00317   for (index = 0; index < BufferLength; index++)
00318   {
00319     pBuffer[index] = index + Offset;
00320   }
00321 }
00322
00323 /**
00324   * @brief  Checks if a buffer has all its values are equal to zero.
00325   * @param  pBuffer: buffer to be compared.
00326   * @param  BufferLength: buffer's length
00327   * @retval PASSED: pBuffer values are zero
00328   *         FAILED: At least one value from pBuffer buffer is different from zero.
00329   */
00330 TestStatus eBuffercmp(uint8_t* pBuffer, uint32_t BufferLength)
00331 {
00332   while (BufferLength--)
00333   {
00334     /* In some SD Cards the erased state is 0xFF, in others it's 0x00 */
00335     if ((*pBuffer != 0xFF) && (*pBuffer != 0x00))
00336     {
00337       return FAILED;
00338     }
00339
00340     pBuffer++;
00341   }
00342
00343   return PASSED;
00344 }
00345
00346 #ifdef  USE_FULL_ASSERT
00347 /**
00348   * @brief  Reports the name of the source file and the source line number
00349   *         where the assert_param error has occurred.
00350   * @param  file: pointer to the source file name
00351   * @param  line: assert_param error line source number
00352   * @retval None
00353   */
00354 void assert_failed(uint8_t* file, uint32_t line)
00355 {
00356   /* User can add his own implementation to report the file name and line number,
00357      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00358
00359   /* Infinite loop */
00360   while (1)
00361   {}
00362 }
00363 #endif
00364
00365 /**
00366   * @}
00367   */
00368
00369 /**
00370   * @}
00371   */
00372
00373 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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STM32F10x_StdPeriph_Examples/SDIO/uSDCard/stm32f10x_conf.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    SDIO/uSDCard/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052 /* Exported types ------------------------------------------------------------*/
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Uncomment the line below to expanse the "assert_param" macro in the
00055    Standard Peripheral Library drivers code */
00056 /* #define USE_FULL_ASSERT    1 */
00057
00058 /* Exported macro ------------------------------------------------------------*/
00059 #ifdef  USE_FULL_ASSERT
00060
00061 /**
00062   * @brief  The assert_param macro is used for function's parameters check.
00063   * @param  expr: If expr is false, it calls assert_failed function which reports
00064   *         the name of the source file and the source line number of the call
00065   *         that failed. If expr is true, it returns no value.
00066   * @retval None
00067   */
00068   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00069 /* Exported functions ------------------------------------------------------- */
00070   void assert_failed(uint8_t* file, uint32_t line);
00071 #else
00072   #define assert_param(expr) ((void)0)
00073 #endif /* USE_FULL_ASSERT */
00074
00075 #endif /* __STM32F10x_CONF_H */
00076
00077 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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STM32F10x_StdPeriph_Examples/SDIO/uSDCard/stm32f10x_it.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    SDIO/uSDCard/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and
00009   *          peripherals interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026 #include "stm32_eval_sdio_sd.h"
00027
00028 /** @addtogroup STM32F10x_StdPeriph_Examples
00029   * @{
00030   */
00031
00032 /** @addtogroup SDIO_uSDCard
00033   * @{
00034   */
00035
00036 /* Private typedef -----------------------------------------------------------*/
00037 /* Private define ------------------------------------------------------------*/
00038 /* Private macro -------------------------------------------------------------*/
00039 /* Private variables ---------------------------------------------------------*/
00040 /* Private function prototypes -----------------------------------------------*/
00041 /* Private functions ---------------------------------------------------------*/
00042
00043 /******************************************************************************/
00044 /*            Cortex-M3 Processor Exceptions Handlers                         */
00045 /******************************************************************************/
00046
00047 /**
00048   * @brief  This function handles NMI exception.
00049   * @param  None
00050   * @retval None
00051   */
00052 void NMI_Handler(void)
00053 {
00054 }
00055
00056 /**
00057   * @brief  This function handles Hard Fault exception.
00058   * @param  None
00059   * @retval None
00060   */
00061 void HardFault_Handler(void)
00062 {
00063   /* Go to infinite loop when Hard Fault exception occurs */
00064   while (1)
00065   {}
00066 }
00067
00068 /**
00069   * @brief  This function handles Memory Manage exception.
00070   * @param  None
00071   * @retval None
00072   */
00073 void MemManage_Handler(void)
00074 {
00075   /* Go to infinite loop when Memory Manage exception occurs */
00076   while (1)
00077   {}
00078 }
00079
00080 /**
00081   * @brief  This function handles Bus Fault exception.
00082   * @param  None
00083   * @retval None
00084   */
00085 void BusFault_Handler(void)
00086 {
00087   /* Go to infinite loop when Bus Fault exception occurs */
00088   while (1)
00089   {}
00090 }
00091
00092 /**
00093   * @brief  This function handles Usage Fault exception.
00094   * @param  None
00095   * @retval None
00096   */
00097 void UsageFault_Handler(void)
00098 {
00099   /* Go to infinite loop when Usage Fault exception occurs */
00100   while (1)
00101   {}
00102 }
00103
00104 /**
00105   * @brief  This function handles Debug Monitor exception.
00106   * @param  None
00107   * @retval None
00108   */
00109 void DebugMon_Handler(void)
00110 {
00111 }
00112
00113 /**
00114   * @brief  This function handles SVCall exception.
00115   * @param  None
00116   * @retval None
00117   */
00118 void SVC_Handler(void)
00119 {
00120 }
00121
00122 /**
00123   * @brief  This function handles PendSV_Handler exception.
00124   * @param  None
00125   * @retval None
00126   */
00127 void PendSV_Handler(void)
00128 {
00129 }
00130
00131 /**
00132   * @brief  This function handles SysTick Handler.
00133   * @param  None
00134   * @retval None
00135   */
00136 void SysTick_Handler(void)
00137 {
00138 }
00139
00140 /******************************************************************************/
00141 /*            STM32F10x Peripherals Interrupt Handlers                        */
00142 /******************************************************************************/
00143
00144 /**
00145   * @brief  This function handles SDIO global interrupt request.
00146   * @param  None
00147   * @retval None
00148   */
00149 void SDIO_IRQHandler(void)
00150 {
00151   /* Process All SDIO Interrupt Sources */
00152   SD_ProcessIRQSrc();
00153 }
00154
00155 /******************************************************************************/
00156 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00157 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00158 /*  available peripheral interrupt handler's name please refer to the startup */
00159 /*  file (startup_stm32f10x_xx.s).                                            */
00160 /******************************************************************************/
00161
00162 /**
00163   * @brief  This function handles PPP interrupt request.
00164   * @param  None
00165   * @retval None
00166   */
00167 /*void PPP_IRQHandler(void)
00168 {
00169 }*/
00170
00171 /**
00172   * @}
00173   */
00174
00175 /**
00176   * @}
00177   */
00178
00179 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • SDIO
  • uSDCard

STM32F10x_StdPeriph_Examples/SDIO/uSDCard/stm32f10x_it.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    SDIO/uSDCard/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043 void SDIO_IRQHandler(void);
00044
00045 #endif /* __STM32F10x_IT_H */
00046
00047 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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STM32F10x_StdPeriph_Examples/SPI/CRC/main.c

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00001 /**
00002   ******************************************************************************
00003   * @file    SPI/CRC/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x.h"
00024
00025 /** @addtogroup STM32F10x_StdPeriph_Examples
00026   * @{
00027   */
00028
00029 /** @addtogroup SPI_CRC
00030   * @{
00031   */
00032
00033 /* Private typedef -----------------------------------------------------------*/
00034 typedef enum {FAILED = 0, PASSED = !FAILED} TestStatus;
00035
00036 /* Private define ------------------------------------------------------------*/
00037 #define BufferSize  32
00038
00039 /* Private macro -------------------------------------------------------------*/
00040 /* Private variables ---------------------------------------------------------*/
00041 SPI_InitTypeDef  SPI_InitStructure;
00042 uint16_t SPI1_Buffer_Tx[BufferSize] = {0x0102, 0x0304, 0x0506, 0x0708, 0x090A, 0x0B0C,
00043                                   0x0D0E, 0x0F10, 0x1112, 0x1314, 0x1516, 0x1718,
00044                                   0x191A, 0x1B1C, 0x1D1E, 0x1F20, 0x2122, 0x2324,
00045                                   0x2526, 0x2728, 0x292A, 0x2B2C, 0x2D2E, 0x2F30,
00046                                   0x3132, 0x3334, 0x3536, 0x3738, 0x393A, 0x3B3C,
00047                                   0x3D3E, 0x3F40};
00048 uint16_t SPI2_Buffer_Tx[BufferSize] = {0x5152, 0x5354, 0x5556, 0x5758, 0x595A, 0x5B5C,
00049                                   0x5D5E, 0x5F60, 0x6162, 0x6364, 0x6566, 0x6768,
00050                                   0x696A, 0x6B6C, 0x6D6E, 0x6F70, 0x7172, 0x7374,
00051                                   0x7576, 0x7778, 0x797A, 0x7B7C, 0x7D7E, 0x7F80,
00052                                   0x8182, 0x8384, 0x8586, 0x8788, 0x898A, 0x8B8C,
00053                                   0x8D8E, 0x8F90};
00054 uint16_t SPI1_Buffer_Rx[BufferSize], SPI2_Buffer_Rx[BufferSize];
00055 uint32_t TxIdx = 0, RxIdx = 0;
00056 __IO uint16_t CRC1Value = 0, CRC2Value = 0;
00057 volatile TestStatus TransferStatus1 = FAILED, TransferStatus2 = FAILED;
00058
00059 /* Private functions ---------------------------------------------------------*/
00060 void RCC_Configuration(void);
00061 void GPIO_Configuration(void);
00062 TestStatus Buffercmp(uint16_t* pBuffer1, uint16_t* pBuffer2, uint16_t BufferLength);
00063
00064 /**
00065   * @brief  Main program
00066   * @param  None
00067   * @retval None
00068   */
00069 int main(void)
00070 {
00071   /*!< At this stage the microcontroller clock setting is already configured,
00072        this is done through SystemInit() function which is called from startup
00073        file (startup_stm32f10x_xx.s) before to branch to application main.
00074        To reconfigure the default setting of SystemInit() function, refer to
00075        system_stm32f10x.c file
00076      */
00077
00078   /* System clocks configuration ---------------------------------------------*/
00079   RCC_Configuration();
00080
00081   /* GPIO configuration ------------------------------------------------------*/
00082   GPIO_Configuration();
00083
00084   /* SPI1 configuration ------------------------------------------------------*/
00085   SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
00086   SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
00087   SPI_InitStructure.SPI_DataSize = SPI_DataSize_16b;
00088   SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low;
00089   SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge;
00090   SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
00091   SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_8;
00092   SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
00093   SPI_InitStructure.SPI_CRCPolynomial = 7;
00094   SPI_Init(SPI1, &SPI_InitStructure);
00095
00096   /* SPI2 configuration ------------------------------------------------------*/
00097   SPI_InitStructure.SPI_Mode = SPI_Mode_Slave;
00098   SPI_Init(SPI2, &SPI_InitStructure);
00099
00100   /* Enable SPI1 CRC calculation */
00101   SPI_CalculateCRC(SPI1, ENABLE);
00102   /* Enable SPI2 CRC calculation */
00103   SPI_CalculateCRC(SPI2, ENABLE);
00104
00105   /* Enable SPI1 */
00106   SPI_Cmd(SPI1, ENABLE);
00107   /* Enable SPI2 */
00108   SPI_Cmd(SPI2, ENABLE);
00109
00110   /* Transfer procedure */
00111   while (TxIdx < BufferSize - 1)
00112   {
00113     /* Wait for SPI1 Tx buffer empty */
00114     while (SPI_I2S_GetFlagStatus(SPI1, SPI_I2S_FLAG_TXE) == RESET);
00115     /* Send SPI2 data */
00116     SPI_I2S_SendData(SPI2, SPI2_Buffer_Tx[TxIdx]);
00117     /* Send SPI1 data */
00118     SPI_I2S_SendData(SPI1, SPI1_Buffer_Tx[TxIdx++]);
00119     /* Wait for SPI2 data reception */
00120     while (SPI_I2S_GetFlagStatus(SPI2, SPI_I2S_FLAG_RXNE) == RESET);
00121     /* Read SPI2 received data */
00122     SPI2_Buffer_Rx[RxIdx] = SPI_I2S_ReceiveData(SPI2);
00123     /* Wait for SPI1 data reception */
00124     while (SPI_I2S_GetFlagStatus(SPI1, SPI_I2S_FLAG_RXNE) == RESET);
00125     /* Read SPI1 received data */
00126     SPI1_Buffer_Rx[RxIdx++] = SPI_I2S_ReceiveData(SPI1);
00127   }
00128
00129   /* Wait for SPI1 Tx buffer empty */
00130   while (SPI_I2S_GetFlagStatus(SPI1, SPI_I2S_FLAG_TXE) == RESET);
00131   /* Wait for SPI2 Tx buffer empty */
00132   while (SPI_I2S_GetFlagStatus(SPI2, SPI_I2S_FLAG_TXE) == RESET);
00133
00134   /* Send last SPI2_Buffer_Tx data */
00135   SPI_I2S_SendData(SPI2, SPI2_Buffer_Tx[TxIdx]);
00136   /* Enable SPI2 CRC transmission */
00137   SPI_TransmitCRC(SPI2);
00138   /* Send last SPI1_Buffer_Tx data */
00139   SPI_I2S_SendData(SPI1, SPI1_Buffer_Tx[TxIdx]);
00140   /* Enable SPI1 CRC transmission */
00141   SPI_TransmitCRC(SPI1);
00142
00143   /* Wait for SPI1 last data reception */
00144   while (SPI_I2S_GetFlagStatus(SPI1, SPI_I2S_FLAG_RXNE) == RESET);
00145   /* Read SPI1 last received data */
00146   SPI1_Buffer_Rx[RxIdx] = SPI_I2S_ReceiveData(SPI1);
00147
00148   /* Wait for SPI2 last data reception */
00149   while (SPI_I2S_GetFlagStatus(SPI2, SPI_I2S_FLAG_RXNE) == RESET);
00150   /* Read SPI2 last received data */
00151   SPI2_Buffer_Rx[RxIdx] = SPI_I2S_ReceiveData(SPI2);
00152
00153   /* Wait for SPI1 data reception: CRC transmitted by SPI2 */
00154   while (SPI_I2S_GetFlagStatus(SPI1, SPI_I2S_FLAG_RXNE) == RESET);
00155   /* Wait for SPI2 data reception: CRC transmitted by SPI1 */
00156   while (SPI_I2S_GetFlagStatus(SPI2, SPI_I2S_FLAG_RXNE) == RESET);
00157
00158   /* Check the received data with the send ones */
00159   TransferStatus1 = Buffercmp(SPI2_Buffer_Rx, SPI1_Buffer_Tx, BufferSize);
00160   TransferStatus2 = Buffercmp(SPI1_Buffer_Rx, SPI2_Buffer_Tx, BufferSize);
00161   /* TransferStatus1, TransferStatus2 = PASSED, if the data transmitted and received
00162      are correct */
00163   /* TransferStatus1, TransferStatus2 = FAILED, if the data transmitted and received
00164      are different */
00165
00166   /* Test on the SPI1 CRC Error flag */
00167   if ((SPI_I2S_GetFlagStatus(SPI1, SPI_FLAG_CRCERR)) == SET)
00168   {
00169     TransferStatus2 = FAILED;
00170   }
00171
00172   /* Test on the SPI2 CRC Error flag */
00173   if ((SPI_I2S_GetFlagStatus(SPI2, SPI_FLAG_CRCERR)) == SET)
00174   {
00175     TransferStatus1 = FAILED;
00176   }
00177
00178   /* Read SPI1 received CRC value */
00179   CRC1Value = SPI_I2S_ReceiveData(SPI1);
00180   /* Read SPI2 received CRC value */
00181   CRC2Value = SPI_I2S_ReceiveData(SPI2);
00182
00183   while (1)
00184   {}
00185 }
00186
00187 /**
00188   * @brief  Configures the different system clocks.
00189   * @param  None
00190   * @retval None
00191   */
00192 void RCC_Configuration(void)
00193 {
00194   /* PCLK2 = HCLK/2 */
00195   RCC_PCLK2Config(RCC_HCLK_Div2);
00196
00197   /* Enable peripheral clocks --------------------------------------------------*/
00198   /* GPIOA, GPIOB and SPI1 clock enable */
00199   RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB |
00200                          RCC_APB2Periph_SPI1, ENABLE);
00201
00202   /* SPI2 Periph clock enable */
00203   RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE);
00204 }
00205
00206 /**
00207   * @brief  Configures the different GPIO ports.
00208   * @param  None
00209   * @retval None
00210   */
00211 void GPIO_Configuration(void)
00212 {
00213   GPIO_InitTypeDef GPIO_InitStructure;
00214
00215   /* Configure SPI1 pins: SCK, MISO and MOSI ---------------------------------*/
00216   /* Confugure SCK and MOSI pins as Alternate Function Push Pull */
00217   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5 | GPIO_Pin_7;
00218   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00219   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
00220   GPIO_Init(GPIOA, &GPIO_InitStructure);
00221   /* Confugure MISO pin as Input Floating  */
00222   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
00223   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
00224   GPIO_Init(GPIOA, &GPIO_InitStructure);
00225
00226   /* Configure SPI2 pins: SCK, MISO and MOSI ---------------------------------*/
00227   /* Confugure SCK and MOSI pins as Input Floating */
00228   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13 | GPIO_Pin_15;
00229   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00230   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
00231   GPIO_Init(GPIOB, &GPIO_InitStructure);
00232   /* Confugure MISO pin as Alternate Function Push Pull */
00233   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_14;
00234   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
00235   GPIO_Init(GPIOB, &GPIO_InitStructure);
00236
00237 }
00238
00239 /**
00240   * @brief  Compares two buffers.
00241   * @param  pBuffer1, pBuffer2: buffers to be compared.
00242   * @param  BufferLength: buffer's length
00243   * @retval PASSED: pBuffer1 identical to pBuffer2
00244   *         FAILED: pBuffer1 differs from pBuffer2
00245   */
00246 TestStatus Buffercmp(uint16_t* pBuffer1, uint16_t* pBuffer2, uint16_t BufferLength)
00247 {
00248   while (BufferLength--)
00249   {
00250     if (*pBuffer1 != *pBuffer2)
00251     {
00252       return FAILED;
00253     }
00254
00255     pBuffer1++;
00256     pBuffer2++;
00257   }
00258
00259   return PASSED;
00260 }
00261
00262 #ifdef  USE_FULL_ASSERT
00263
00264 /**
00265   * @brief  Reports the name of the source file and the source line number
00266   *         where the assert_param error has occurred.
00267   * @param  file: pointer to the source file name
00268   * @param  line: assert_param error line source number
00269   * @retval None
00270   */
00271 void assert_failed(uint8_t* file, uint32_t line)
00272 {
00273   /* User can add his own implementation to report the file name and line number,
00274      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00275
00276   /* Infinite loop */
00277   while (1)
00278   {}
00279 }
00280
00281 #endif
00282
00283 /**
00284   * @}
00285   */
00286
00287 /**
00288   * @}
00289   */
00290
00291 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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STM32F10x_StdPeriph_Examples/SPI/CRC/stm32f10x_conf.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file SPI/CRC/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052 /* Exported types ------------------------------------------------------------*/
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Uncomment the line below to expanse the "assert_param" macro in the
00055    Standard Peripheral Library drivers code */
00056 /* #define USE_FULL_ASSERT    1 */
00057
00058 /* Exported macro ------------------------------------------------------------*/
00059 #ifdef  USE_FULL_ASSERT
00060
00061 /**
00062   * @brief  The assert_param macro is used for function's parameters check.
00063   * @param  expr: If expr is false, it calls assert_failed function which reports
00064   *         the name of the source file and the source line number of the call
00065   *         that failed. If expr is true, it returns no value.
00066   * @retval None
00067   */
00068   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00069 /* Exported functions ------------------------------------------------------- */
00070   void assert_failed(uint8_t* file, uint32_t line);
00071 #else
00072   #define assert_param(expr) ((void)0)
00073 #endif /* USE_FULL_ASSERT */
00074
00075 #endif /* __STM32F10x_CONF_H */
00076
00077 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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STM32F10x_StdPeriph_Examples/SPI/CRC/stm32f10x_it.c

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00001 /**
00002   ******************************************************************************
00003   * @file    SPI/CRC/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and peripherals
00009   *          interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026
00027 /** @addtogroup STM32F10x_StdPeriph_Examples
00028   * @{
00029   */
00030
00031 /** @addtogroup SPI_CRC
00032   * @{
00033   */
00034
00035 /* Private typedef -----------------------------------------------------------*/
00036 /* Private define ------------------------------------------------------------*/
00037 /* Private macro -------------------------------------------------------------*/
00038 /* Private variables ---------------------------------------------------------*/
00039 /* Private function prototypes -----------------------------------------------*/
00040 /* Private functions ---------------------------------------------------------*/
00041
00042 /******************************************************************************/
00043 /*            Cortex-M3 Processor Exceptions Handlers                         */
00044 /******************************************************************************/
00045
00046 /**
00047   * @brief  This function handles NMI exception.
00048   * @param  None
00049   * @retval None
00050   */
00051 void NMI_Handler(void)
00052 {
00053 }
00054
00055 /**
00056   * @brief  This function handles Hard Fault exception.
00057   * @param  None
00058   * @retval None
00059   */
00060 void HardFault_Handler(void)
00061 {
00062   /* Go to infinite loop when Hard Fault exception occurs */
00063   while (1)
00064   {}
00065 }
00066
00067 /**
00068   * @brief  This function handles Memory Manage exception.
00069   * @param  None
00070   * @retval None
00071   */
00072 void MemManage_Handler(void)
00073 {
00074   /* Go to infinite loop when Memory Manage exception occurs */
00075   while (1)
00076   {}
00077 }
00078
00079 /**
00080   * @brief  This function handles Bus Fault exception.
00081   * @param  None
00082   * @retval None
00083   */
00084 void BusFault_Handler(void)
00085 {
00086   /* Go to infinite loop when Bus Fault exception occurs */
00087   while (1)
00088   {}
00089 }
00090
00091 /**
00092   * @brief  This function handles Usage Fault exception.
00093   * @param  None
00094   * @retval None
00095   */
00096 void UsageFault_Handler(void)
00097 {
00098   /* Go to infinite loop when Usage Fault exception occurs */
00099   while (1)
00100   {}
00101 }
00102
00103 /**
00104   * @brief  This function handles Debug Monitor exception.
00105   * @param  None
00106   * @retval None
00107   */
00108 void DebugMon_Handler(void)
00109 {}
00110
00111 /**
00112   * @brief  This function handles SVCall exception.
00113   * @param  None
00114   * @retval None
00115   */
00116 void SVC_Handler(void)
00117 {}
00118
00119 /**
00120   * @brief  This function handles PendSV_Handler exception.
00121   * @param  None
00122   * @retval None
00123   */
00124 void PendSV_Handler(void)
00125 {}
00126
00127 /**
00128   * @brief  This function handles SysTick Handler.
00129   * @param  None
00130   * @retval None
00131   */
00132 void SysTick_Handler(void)
00133 {}
00134
00135 /******************************************************************************/
00136 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00137 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00138 /*  available peripheral interrupt handler's name please refer to the startup */
00139 /*  file (startup_stm32f10x_xx.s).                                            */
00140 /******************************************************************************/
00141
00142 /**
00143   * @brief  This function handles PPP interrupt request.
00144   * @param  None
00145   * @retval None
00146   */
00147 /*void PPP_IRQHandler(void)
00148 {
00149 }*/
00150
00151 /**
00152   * @}
00153   */
00154
00155 /**
00156   * @}
00157   */
00158
00159 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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STM32F10x_StdPeriph_Examples/SPI/CRC/stm32f10x_it.h

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00001 /**
00002   ******************************************************************************
00003   * @file SPI/CRC/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043
00044 #endif /* __STM32F10x_IT_H */
00045
00046 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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STM32F10x_StdPeriph_Examples/SPI/DMA/main.c

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00001 /**
00002   ******************************************************************************
00003   * @file    SPI/DMA/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x.h"
00024 #include "platform_config.h"
00025
00026
00027 /** @addtogroup STM32F10x_StdPeriph_Examples
00028   * @{
00029   */
00030
00031 /** @addtogroup SPI_DMA
00032   * @{
00033   */
00034
00035 /* Private typedef -----------------------------------------------------------*/
00036 typedef enum {FAILED = 0, PASSED = !FAILED} TestStatus;
00037
00038 /* Private define ------------------------------------------------------------*/
00039 #define BufferSize       32
00040
00041 /* Private macro -------------------------------------------------------------*/
00042 /* Private variables ---------------------------------------------------------*/
00043 SPI_InitTypeDef  SPI_InitStructure;
00044 DMA_InitTypeDef  DMA_InitStructure;
00045 GPIO_InitTypeDef GPIO_InitStructure;
00046
00047 uint8_t SPI_MASTER_Buffer_Tx[BufferSize] = {0x01, 0x02, 0x03, 0x04, 0x05, 0x06,
00048                                             0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C,
00049                                             0x0D, 0x0E, 0x0F, 0x10, 0x11, 0x12,
00050                                             0x13, 0x14, 0x15, 0x16, 0x17, 0x18,
00051                                             0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E,
00052                                             0x1F, 0x20};
00053 uint8_t SPI_SLAVE_Buffer_Rx[BufferSize];
00054 __IO uint8_t TxIdx = 0;
00055 volatile TestStatus TransferStatus = FAILED;
00056
00057
00058 /* Private function prototypes -----------------------------------------------*/
00059 void RCC_Configuration(void);
00060 void GPIO_Configuration(void);
00061 TestStatus Buffercmp(uint8_t* pBuffer1, uint8_t* pBuffer2, uint16_t BufferLength);
00062
00063 /* Private functions ---------------------------------------------------------*/
00064
00065 /**
00066   * @brief  Main program
00067   * @param  None
00068   * @retval None
00069   */
00070 int main(void)
00071 {
00072   /*!< At this stage the microcontroller clock setting is already configured,
00073        this is done through SystemInit() function which is called from startup
00074        file (startup_stm32f10x_xx.s) before to branch to application main.
00075        To reconfigure the default setting of SystemInit() function, refer to
00076        system_stm32f10x.c file
00077      */
00078
00079   /* System clocks configuration ---------------------------------------------*/
00080   RCC_Configuration();
00081
00082   /* GPIO configuration ------------------------------------------------------*/
00083   GPIO_Configuration();
00084
00085   /* SPI_SLAVE_Rx_DMA_Channel configuration ---------------------------------------------*/
00086   DMA_DeInit(SPI_SLAVE_Rx_DMA_Channel);
00087   DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)SPI_SLAVE_DR_Base;
00088   DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)SPI_SLAVE_Buffer_Rx;
00089   DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
00090   DMA_InitStructure.DMA_BufferSize = BufferSize;
00091   DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
00092   DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
00093   DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
00094   DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
00095   DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
00096   DMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh;
00097   DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
00098   DMA_Init(SPI_SLAVE_Rx_DMA_Channel, &DMA_InitStructure);
00099
00100   /* SPI_MASTER configuration ------------------------------------------------------*/
00101   SPI_InitStructure.SPI_Direction = SPI_Direction_1Line_Tx;
00102   SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
00103   SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
00104   SPI_InitStructure.SPI_CPOL = SPI_CPOL_High;
00105   SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge;
00106   SPI_InitStructure.SPI_NSS = SPI_NSS_Hard;
00107   SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_4;
00108   SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
00109   SPI_InitStructure.SPI_CRCPolynomial = 7;
00110   SPI_Init(SPI_MASTER, &SPI_InitStructure);
00111
00112   /* SPI_SLAVE configuration ------------------------------------------------------*/
00113   SPI_InitStructure.SPI_Direction = SPI_Direction_1Line_Rx;
00114   SPI_InitStructure.SPI_Mode = SPI_Mode_Slave;
00115   SPI_Init(SPI_SLAVE, &SPI_InitStructure);
00116
00117   /* Enable SPI_MASTER NSS output for master mode */
00118   SPI_SSOutputCmd(SPI_MASTER, ENABLE);
00119
00120   /* Enable SPI_SLAVE Rx request */
00121   SPI_I2S_DMACmd(SPI_SLAVE, SPI_I2S_DMAReq_Rx, ENABLE);
00122
00123   /* Enable SPI_SLAVE */
00124   SPI_Cmd(SPI_SLAVE, ENABLE);
00125   /* Enable SPI_MASTER */
00126   SPI_Cmd(SPI_MASTER, ENABLE);
00127
00128   /* Enable DMA1 Channel4 */
00129   DMA_Cmd(SPI_SLAVE_Rx_DMA_Channel, ENABLE);
00130
00131   /* Transfer procedure */
00132   while (TxIdx < BufferSize)
00133   {
00134     /* Wait for SPI_MASTER Tx buffer empty */
00135     while (SPI_I2S_GetFlagStatus(SPI_MASTER, SPI_I2S_FLAG_TXE) == RESET);
00136     /* Send SPI_MASTER data */
00137     SPI_I2S_SendData(SPI_MASTER, SPI_MASTER_Buffer_Tx[TxIdx++]);
00138   }
00139
00140   /* Wait for DMA1 channel4 transfer complete */
00141   while (!DMA_GetFlagStatus(SPI_SLAVE_Rx_DMA_FLAG));
00142
00143   /* Check the correctness of written data */
00144   TransferStatus = Buffercmp(SPI_SLAVE_Buffer_Rx, SPI_MASTER_Buffer_Tx, BufferSize);
00145   /* TransferStatus = PASSED, if the transmitted and received data
00146      are equal */
00147   /* TransferStatus = FAILED, if the transmitted and received data
00148      are different */
00149
00150   while (1)
00151   {}
00152 }
00153
00154 /**
00155   * @brief  Configures the different system clocks.
00156   * @param  None
00157   * @retval None
00158   */
00159 void RCC_Configuration(void)
00160 {
00161   /* PCLK2 = HCLK/2 */
00162   RCC_PCLK2Config(RCC_HCLK_Div2);
00163
00164   /* Enable peripheral clocks --------------------------------------------------*/
00165   /* Enable SPI_SLAVE DMA clock */
00166   RCC_AHBPeriphClockCmd(SPI_SLAVE_DMA_CLK, ENABLE);
00167
00168 #ifdef USE_STM3210C_EVAL
00169   /* Enable GPIO clock for SPI_MASTER and SPI_SLAVE */
00170   RCC_APB2PeriphClockCmd(SPI_MASTER_GPIO_CLK | SPI_SLAVE_GPIO_CLK |
00171                          RCC_APB2Periph_AFIO, ENABLE);
00172
00173   /* Enable SPI_MASTER Periph clock */
00174   RCC_APB1PeriphClockCmd(SPI_MASTER_CLK, ENABLE);
00175
00176 #else
00177   /* Enable SPI_MASTER clock and GPIO clock for SPI_MASTER and SPI_SLAVE */
00178   RCC_APB2PeriphClockCmd(SPI_MASTER_GPIO_CLK | SPI_SLAVE_GPIO_CLK |
00179                          SPI_MASTER_CLK, ENABLE);
00180 #endif
00181   /* Enable SPI_SLAVE Periph clock */
00182   RCC_APB1PeriphClockCmd(SPI_SLAVE_CLK, ENABLE);
00183 }
00184
00185 /**
00186   * @brief  Configures the different GPIO ports.
00187   * @param  None
00188   * @retval None
00189   */
00190 void GPIO_Configuration(void)
00191 {
00192   GPIO_InitTypeDef GPIO_InitStructure;
00193
00194 #ifdef USE_STM3210C_EVAL
00195   /* Enable SPI3 Pins Software Remapping */
00196   GPIO_PinRemapConfig(GPIO_Remap_SPI3, ENABLE);
00197
00198   /* Configure SPI_MASTER pins: SCK and MOSI */
00199   GPIO_InitStructure.GPIO_Pin = SPI_MASTER_PIN_SCK | SPI_MASTER_PIN_MOSI;
00200   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00201   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
00202   GPIO_Init(SPI_MASTER_GPIO, &GPIO_InitStructure);
00203
00204   /* Configure SPI_MASTER NSS pin */
00205   GPIO_InitStructure.GPIO_Pin = SPI_MASTER_PIN_NSS;
00206   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00207   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
00208   GPIO_Init(SPI_MASTER_GPIO_NSS, &GPIO_InitStructure);
00209
00210 #else
00211   /* Configure SPI_MASTER pins: NSS, SCK and MOSI */
00212   GPIO_InitStructure.GPIO_Pin = SPI_MASTER_PIN_NSS | SPI_MASTER_PIN_SCK | SPI_MASTER_PIN_MOSI;
00213   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00214   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
00215   GPIO_Init(SPI_MASTER_GPIO, &GPIO_InitStructure);
00216 #endif
00217
00218   /* Configure SPI_SLAVE pins: NSS, SCK and MISO*/
00219   GPIO_InitStructure.GPIO_Pin = SPI_SLAVE_PIN_NSS | SPI_SLAVE_PIN_SCK;
00220   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
00221   GPIO_Init(SPI_SLAVE_GPIO, &GPIO_InitStructure);
00222
00223   GPIO_InitStructure.GPIO_Pin =  SPI_SLAVE_PIN_MISO;
00224   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
00225   GPIO_Init(SPI_SLAVE_GPIO, &GPIO_InitStructure);
00226
00227 }
00228
00229 /**
00230   * @brief  Compares two buffers.
00231   * @param  pBuffer1, pBuffer2: buffers to be compared.
00232   * @param  BufferLength: buffer's length
00233   * @retval PASSED: pBuffer1 identical to pBuffer2
00234   *         FAILED: pBuffer1 differs from pBuffer2
00235   */
00236 TestStatus Buffercmp(uint8_t* pBuffer1, uint8_t* pBuffer2, uint16_t BufferLength)
00237 {
00238   while (BufferLength--)
00239   {
00240     if (*pBuffer1 != *pBuffer2)
00241     {
00242       return FAILED;
00243     }
00244
00245     pBuffer1++;
00246     pBuffer2++;
00247   }
00248
00249   return PASSED;
00250 }
00251
00252 #ifdef  USE_FULL_ASSERT
00253
00254 /**
00255   * @brief  Reports the name of the source file and the source line number
00256   *         where the assert_param error has occurred.
00257   * @param  file: pointer to the source file name
00258   * @param  line: assert_param error line source number
00259   * @retval None
00260   */
00261 void assert_failed(uint8_t* file, uint32_t line)
00262 {
00263   /* User can add his own implementation to report the file name and line number,
00264      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00265
00266   /* Infinite loop */
00267   while (1)
00268   {}
00269 }
00270
00271 #endif
00272
00273 /**
00274   * @}
00275   */
00276
00277 /**
00278   * @}
00279   */
00280
00281 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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STM32F10x_StdPeriph_Examples/SPI/DMA/stm32f10x_conf.h

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00001 /**
00002   ******************************************************************************
00003   * @file SPI/DMA/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052 /* Exported types ------------------------------------------------------------*/
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Uncomment the line below to expanse the "assert_param" macro in the
00055    Standard Peripheral Library drivers code */
00056 /* #define USE_FULL_ASSERT    1 */
00057
00058 /* Exported macro ------------------------------------------------------------*/
00059 #ifdef  USE_FULL_ASSERT
00060
00061 /**
00062   * @brief  The assert_param macro is used for function's parameters check.
00063   * @param  expr: If expr is false, it calls assert_failed function which reports
00064   *         the name of the source file and the source line number of the call
00065   *         that failed. If expr is true, it returns no value.
00066   * @retval None
00067   */
00068   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00069 /* Exported functions ------------------------------------------------------- */
00070   void assert_failed(uint8_t* file, uint32_t line);
00071 #else
00072   #define assert_param(expr) ((void)0)
00073 #endif /* USE_FULL_ASSERT */
00074
00075 #endif /* __STM32F10x_CONF_H */
00076
00077 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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STM32F10x_StdPeriph_Examples/SPI/DMA/stm32f10x_it.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    SPI/DMA/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and peripherals
00009   *          interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026
00027 /** @addtogroup STM32F10x_StdPeriph_Examples
00028   * @{
00029   */
00030
00031 /** @addtogroup SPI_DMA
00032   * @{
00033   */
00034
00035 /* Private typedef -----------------------------------------------------------*/
00036 /* Private define ------------------------------------------------------------*/
00037 /* Private macro -------------------------------------------------------------*/
00038 /* Private variables ---------------------------------------------------------*/
00039 /* Private function prototypes -----------------------------------------------*/
00040 /* Private functions ---------------------------------------------------------*/
00041
00042 /******************************************************************************/
00043 /*            Cortex-M3 Processor Exceptions Handlers                         */
00044 /******************************************************************************/
00045
00046 /**
00047   * @brief  This function handles NMI exception.
00048   * @param  None
00049   * @retval None
00050   */
00051 void NMI_Handler(void)
00052 {
00053 }
00054
00055 /**
00056   * @brief  This function handles Hard Fault exception.
00057   * @param  None
00058   * @retval None
00059   */
00060 void HardFault_Handler(void)
00061 {
00062   /* Go to infinite loop when Hard Fault exception occurs */
00063   while (1)
00064   {}
00065 }
00066
00067 /**
00068   * @brief  This function handles Memory Manage exception.
00069   * @param  None
00070   * @retval None
00071   */
00072 void MemManage_Handler(void)
00073 {
00074   /* Go to infinite loop when Memory Manage exception occurs */
00075   while (1)
00076   {}
00077 }
00078
00079 /**
00080   * @brief  This function handles Bus Fault exception.
00081   * @param  None
00082   * @retval None
00083   */
00084 void BusFault_Handler(void)
00085 {
00086   /* Go to infinite loop when Bus Fault exception occurs */
00087   while (1)
00088   {}
00089 }
00090
00091 /**
00092   * @brief  This function handles Usage Fault exception.
00093   * @param  None
00094   * @retval None
00095   */
00096 void UsageFault_Handler(void)
00097 {
00098   /* Go to infinite loop when Usage Fault exception occurs */
00099   while (1)
00100   {}
00101 }
00102
00103 /**
00104   * @brief  This function handles Debug Monitor exception.
00105   * @param  None
00106   * @retval None
00107   */
00108 void DebugMon_Handler(void)
00109 {}
00110
00111 /**
00112   * @brief  This function handles SVCall exception.
00113   * @param  None
00114   * @retval None
00115   */
00116 void SVC_Handler(void)
00117 {}
00118
00119 /**
00120   * @brief  This function handles PendSV_Handler exception.
00121   * @param  None
00122   * @retval None
00123   */
00124 void PendSV_Handler(void)
00125 {}
00126
00127 /**
00128   * @brief  This function handles SysTick Handler.
00129   * @param  None
00130   * @retval None
00131   */
00132 void SysTick_Handler(void)
00133 {}
00134
00135 /******************************************************************************/
00136 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00137 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00138 /*  available peripheral interrupt handler's name please refer to the startup */
00139 /*  file (startup_stm32f10x_xx.s).                                            */
00140 /******************************************************************************/
00141
00142 /**
00143   * @brief  This function handles PPP interrupt request.
00144   * @param  None
00145   * @retval None
00146   */
00147 /*void PPP_IRQHandler(void)
00148 {
00149 }*/
00150
00151 /**
00152   * @}
00153   */
00154
00155 /**
00156   * @}
00157   */
00158
00159 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • SPI
  • DMA

STM32F10x_StdPeriph_Examples/SPI/DMA/stm32f10x_it.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file SPI/DMA/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043
00044 #endif /* __STM32F10x_IT_H */
00045
00046 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • SPI
  • FullDuplex_SoftNSS

STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/main.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    SPI/FullDuplex_SoftNSS/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x.h"
00024 #include "platform_config.h"
00025
00026 /** @addtogroup STM32F10x_StdPeriph_Examples
00027   * @{
00028   */
00029
00030 /** @addtogroup SPI_FullDuplex_SoftNSS
00031   * @{
00032   */
00033
00034 /* Private typedef -----------------------------------------------------------*/
00035 typedef enum {FAILED = 0, PASSED = !FAILED} TestStatus;
00036
00037 /* Private define ------------------------------------------------------------*/
00038 #define BufferSize 32
00039
00040 /* Private macro -------------------------------------------------------------*/
00041 /* Private variables ---------------------------------------------------------*/
00042 SPI_InitTypeDef   SPI_InitStructure;
00043 uint8_t SPIy_Buffer_Tx[BufferSize] = {0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
00044                                       0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E,
00045                                       0x0F, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15,
00046                                       0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C,
00047                                       0x1D, 0x1E, 0x1F, 0x20};
00048 uint8_t SPIz_Buffer_Tx[BufferSize] = {0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
00049                                       0x58, 0x59, 0x5A, 0x5B, 0x5C, 0x5D, 0x5E,
00050                                       0x5F, 0x60, 0x61, 0x62, 0x63, 0x64, 0x65,
00051                                       0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C,
00052                                       0x6D, 0x6E, 0x6F, 0x70};
00053 uint8_t SPIy_Buffer_Rx[BufferSize], SPIz_Buffer_Rx[BufferSize];
00054 __IO uint8_t TxIdx = 0, RxIdx = 0, k = 0;
00055 volatile TestStatus TransferStatus1 = FAILED, TransferStatus2 = FAILED;
00056 volatile TestStatus TransferStatus3 = FAILED, TransferStatus4 = FAILED;
00057
00058 /* Private functions ---------------------------------------------------------*/
00059 void RCC_Configuration(void);
00060 void GPIO_Configuration(uint16_t SPIy_Mode, uint16_t SPIz_Mode);
00061 TestStatus Buffercmp(uint8_t* pBuffer1, uint8_t* pBuffer2, uint16_t BufferLength);
00062
00063 /**
00064   * @brief  Main program
00065   * @param  None
00066   * @retval None
00067   */
00068 int main(void)
00069 {
00070   /*!< At this stage the microcontroller clock setting is already configured,
00071        this is done through SystemInit() function which is called from startup
00072        file (startup_stm32f10x_xx.s) before to branch to application main.
00073        To reconfigure the default setting of SystemInit() function, refer to
00074        system_stm32f10x.c file
00075      */
00076
00077   /* System clocks configuration ---------------------------------------------*/
00078   RCC_Configuration();
00079
00080   /* 1st phase: SPIy Master and SPIz Slave */
00081   /* GPIO configuration ------------------------------------------------------*/
00082   GPIO_Configuration(SPI_Mode_Master, SPI_Mode_Slave);
00083
00084   /* SPIy Config -------------------------------------------------------------*/
00085   SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
00086   SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
00087   SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
00088   SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low;
00089   SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge;
00090   SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
00091   SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_4;
00092   SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_LSB;
00093   SPI_InitStructure.SPI_CRCPolynomial = 7;
00094   SPI_Init(SPIy, &SPI_InitStructure);
00095
00096   /* SPIz Config -------------------------------------------------------------*/
00097   SPI_InitStructure.SPI_Mode = SPI_Mode_Slave;
00098   SPI_Init(SPIz, &SPI_InitStructure);
00099
00100   /* Enable SPIy */
00101   SPI_Cmd(SPIy, ENABLE);
00102   /* Enable SPIz */
00103   SPI_Cmd(SPIz, ENABLE);
00104
00105   /* Transfer procedure */
00106   while (TxIdx < BufferSize)
00107   {
00108     /* Wait for SPIy Tx buffer empty */
00109     while (SPI_I2S_GetFlagStatus(SPIy, SPI_I2S_FLAG_TXE) == RESET);
00110     /* Send SPIz data */
00111     SPI_I2S_SendData(SPIz, SPIz_Buffer_Tx[TxIdx]);
00112     /* Send SPIy data */
00113     SPI_I2S_SendData(SPIy, SPIy_Buffer_Tx[TxIdx++]);
00114     /* Wait for SPIz data reception */
00115     while (SPI_I2S_GetFlagStatus(SPIz, SPI_I2S_FLAG_RXNE) == RESET);
00116     /* Read SPIz received data */
00117     SPIz_Buffer_Rx[RxIdx] = SPI_I2S_ReceiveData(SPIz);
00118     /* Wait for SPIy data reception */
00119     while (SPI_I2S_GetFlagStatus(SPIy, SPI_I2S_FLAG_RXNE) == RESET);
00120     /* Read SPIy received data */
00121     SPIy_Buffer_Rx[RxIdx++] = SPI_I2S_ReceiveData(SPIy);
00122   }
00123
00124   /* Check the correctness of written dada */
00125   TransferStatus1 = Buffercmp(SPIz_Buffer_Rx, SPIy_Buffer_Tx, BufferSize);
00126   TransferStatus2 = Buffercmp(SPIy_Buffer_Rx, SPIz_Buffer_Tx, BufferSize);
00127   /* TransferStatus1, TransferStatus2 = PASSED, if the transmitted and received data
00128      are equal */
00129   /* TransferStatus1, TransferStatus2 = FAILED, if the transmitted and received data
00130      are different */
00131
00132   /* 2nd phase: SPIy Slave and SPIz Master */
00133   /* GPIO configuration ------------------------------------------------------*/
00134   GPIO_Configuration(SPI_Mode_Slave , SPI_Mode_Master);
00135
00136   /* SPIy Re-configuration ---------------------------------------------------*/
00137   SPI_InitStructure.SPI_Mode = SPI_Mode_Slave;
00138   SPI_Init(SPIy, &SPI_InitStructure);
00139
00140   /* SPIz Re-configuration ---------------------------------------------------*/
00141   SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
00142   SPI_Init(SPIz, &SPI_InitStructure);
00143
00144   /* Reset TxIdx, RxIdx indexes and receive tables values */
00145   TxIdx = 0;
00146   RxIdx = 0;
00147   for (k = 0; k < BufferSize; k++)  SPIz_Buffer_Rx[k] = 0;
00148   for (k = 0; k < BufferSize; k++)  SPIy_Buffer_Rx[k] = 0;
00149
00150   /* Transfer procedure */
00151   while (TxIdx < BufferSize)
00152   {
00153     /* Wait for SPIz Tx buffer empty */
00154     while (SPI_I2S_GetFlagStatus(SPIz, SPI_I2S_FLAG_TXE) == RESET);
00155     /* Send SPIy data */
00156     SPI_I2S_SendData(SPIy, SPIy_Buffer_Tx[TxIdx]);
00157     /* Send SPIz data */
00158     SPI_I2S_SendData(SPIz, SPIz_Buffer_Tx[TxIdx++]);
00159     /* Wait for SPIy data reception */
00160     while (SPI_I2S_GetFlagStatus(SPIy, SPI_I2S_FLAG_RXNE) == RESET);
00161     /* Read SPIy received data */
00162     SPIy_Buffer_Rx[RxIdx] = SPI_I2S_ReceiveData(SPIy);
00163     /* Wait for SPIz data reception */
00164     while (SPI_I2S_GetFlagStatus(SPIz, SPI_I2S_FLAG_RXNE) == RESET);
00165     /* Read SPIz received data */
00166     SPIz_Buffer_Rx[RxIdx++] = SPI_I2S_ReceiveData(SPIz);
00167   }
00168
00169   /* Check the correctness of written dada */
00170   TransferStatus3 = Buffercmp(SPIz_Buffer_Rx, SPIy_Buffer_Tx, BufferSize);
00171   TransferStatus4 = Buffercmp(SPIy_Buffer_Rx, SPIz_Buffer_Tx, BufferSize);
00172   /* TransferStatus3, TransferStatus4 = PASSED, if the transmitted and received data
00173      are equal */
00174   /* TransferStatus3, TransferStatus4 = FAILED, if the transmitted and received data
00175      are different */
00176
00177   while (1)
00178   {}
00179 }
00180
00181 /**
00182   * @brief  Configures the different system clocks.
00183   * @param  None
00184   * @retval None
00185   */
00186 void RCC_Configuration(void)
00187 {
00188   /* PCLK2 = HCLK/2 */
00189   RCC_PCLK2Config(RCC_HCLK_Div2);
00190
00191 /* Enable peripheral clocks --------------------------------------------------*/
00192 #ifdef USE_STM3210C_EVAL
00193   /* Enable GPIO clock for SPIy and SPIz */
00194   RCC_APB2PeriphClockCmd(SPIy_GPIO_CLK | SPIz_GPIO_CLK | RCC_APB2Periph_AFIO, ENABLE);
00195
00196   /* Enable SPIy Periph clock */
00197   RCC_APB1PeriphClockCmd(SPIy_CLK, ENABLE);
00198
00199 #else
00200   /* Enable SPIy clock and GPIO clock for SPIy and SPIz */
00201   RCC_APB2PeriphClockCmd(SPIy_GPIO_CLK | SPIz_GPIO_CLK | SPIy_CLK, ENABLE);
00202 #endif
00203   /* Enable SPIz Periph clock */
00204   RCC_APB1PeriphClockCmd(SPIz_CLK, ENABLE);
00205 }
00206
00207 /**
00208   * @brief  Configures the different SPIy and SPIz GPIO ports.
00209   * @param  SPIy_Mode: Specifies the SPIy operating mode.
00210   *            This parameter can be:
00211   *              -  SPIy_Mode_Master
00212   *              -  SPIy_Mode_Slave
00213   * @param  SPIz_Mode: Specifies the SPIz operating mode.
00214   *            This parameter can be:
00215   *              -  SPIz_Mode_Master
00216   *              -  SPIz_Mode_Slave
00217   * @retval None
00218   */
00219 void GPIO_Configuration(uint16_t SPIy_Mode, uint16_t SPIz_Mode)
00220 {
00221   GPIO_InitTypeDef GPIO_InitStructure;
00222
00223 #ifdef USE_STM3210C_EVAL
00224   /* Enable SPI3 Pins Software Remapping */
00225   GPIO_PinRemapConfig(GPIO_Remap_SPI3, ENABLE);
00226 #endif
00227
00228   /* Configure SPIy pins: SCK, MISO and MOSI ---------------------------------*/
00229   GPIO_InitStructure.GPIO_Pin = SPIy_PIN_SCK | SPIy_PIN_MOSI;
00230   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00231
00232   if(SPIy_Mode == SPI_Mode_Master)
00233   {
00234     /* Configure SCK and MOSI pins as Alternate Function Push Pull */
00235     GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
00236   }
00237   else
00238   {
00239     /* Configure SCK and MOSI pins as Input Floating */
00240     GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
00241   }
00242   GPIO_Init(SPIy_GPIO, &GPIO_InitStructure);
00243
00244   GPIO_InitStructure.GPIO_Pin = SPIy_PIN_MISO;
00245
00246   if(SPIy_Mode == SPI_Mode_Master)
00247   {
00248     /* Configure MISO pin as Input Floating  */
00249     GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
00250   }
00251   else
00252   {
00253     /* Configure MISO pin as Alternate Function Push Pull */
00254     GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
00255   }
00256   GPIO_Init(SPIy_GPIO, &GPIO_InitStructure);
00257
00258   /* Configure SPIz pins: SCK, MISO and MOSI ---------------------------------*/
00259   GPIO_InitStructure.GPIO_Pin = SPIz_PIN_SCK | SPIz_PIN_MOSI;
00260
00261   if(SPIz_Mode == SPI_Mode_Slave)
00262   {
00263     /* Configure SCK and MOSI pins as Input Floating */
00264     GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
00265   }
00266   else
00267   {
00268     /* Configure SCK and MOSI pins as Alternate Function Push Pull */
00269     GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
00270   }
00271   GPIO_Init(SPIz_GPIO, &GPIO_InitStructure);
00272
00273   GPIO_InitStructure.GPIO_Pin = SPIz_PIN_MISO;
00274   if(SPIz_Mode == SPI_Mode_Slave)
00275   {
00276     /* Configure MISO pin as Alternate Function Push Pull */
00277     GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
00278   }
00279   else
00280   { /* Configure MISO pin as Input Floating  */
00281     GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
00282   }
00283   GPIO_Init(SPIz_GPIO, &GPIO_InitStructure);
00284 }
00285 /**
00286   * @brief  Compares two buffers.
00287   * @param  pBuffer1, pBuffer2: buffers to be compared.
00288   * @param  BufferLength: buffer's length
00289   * @retval PASSED: pBuffer1 identical to pBuffer2
00290   *         FAILED: pBuffer1 differs from pBuffer2
00291   */
00292 TestStatus Buffercmp(uint8_t* pBuffer1, uint8_t* pBuffer2, uint16_t BufferLength)
00293 {
00294   while (BufferLength--)
00295   {
00296     if (*pBuffer1 != *pBuffer2)
00297     {
00298       return FAILED;
00299     }
00300
00301     pBuffer1++;
00302     pBuffer2++;
00303   }
00304
00305   return PASSED;
00306 }
00307
00308 #ifdef  USE_FULL_ASSERT
00309
00310 /**
00311   * @brief  Reports the name of the source file and the source line number
00312   *         where the assert_param error has occurred.
00313   * @param  file: pointer to the source file name
00314   * @param  line: assert_param error line source number
00315   * @retval None
00316   */
00317 void assert_failed(uint8_t* file, uint32_t line)
00318 {
00319   /* User can add his own implementation to report the file name and line number,
00320      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00321
00322   /* Infinite loop */
00323   while (1)
00324   {}
00325 }
00326
00327 #endif
00328 /**
00329   * @}
00330   */
00331
00332 /**
00333   * @}
00334   */
00335
00336 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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  • Project
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  • SPI
  • FullDuplex_SoftNSS

STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/stm32f10x_conf.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file SPI/FullDuplex_SoftNSS/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022
00023 /* Define to prevent recursive inclusion -------------------------------------*/
00024 #ifndef __STM32F10x_CONF_H
00025 #define __STM32F10x_CONF_H
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00029 #include "stm32f10x_adc.h"
00030 #include "stm32f10x_bkp.h"
00031 #include "stm32f10x_can.h"
00032 #include "stm32f10x_cec.h"
00033 #include "stm32f10x_crc.h"
00034 #include "stm32f10x_dac.h"
00035 #include "stm32f10x_dbgmcu.h"
00036 #include "stm32f10x_dma.h"
00037 #include "stm32f10x_exti.h"
00038 #include "stm32f10x_flash.h"
00039 #include "stm32f10x_fsmc.h"
00040 #include "stm32f10x_gpio.h"
00041 #include "stm32f10x_i2c.h"
00042 #include "stm32f10x_iwdg.h"
00043 #include "stm32f10x_pwr.h"
00044 #include "stm32f10x_rcc.h"
00045 #include "stm32f10x_rtc.h"
00046 #include "stm32f10x_sdio.h"
00047 #include "stm32f10x_spi.h"
00048 #include "stm32f10x_tim.h"
00049 #include "stm32f10x_usart.h"
00050 #include "stm32f10x_wwdg.h"
00051 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00052
00053 /* Exported types ------------------------------------------------------------*/
00054 /* Exported constants --------------------------------------------------------*/
00055 /* Uncomment the line below to expanse the "assert_param" macro in the
00056    Standard Peripheral Library drivers code */
00057 /* #define USE_FULL_ASSERT    1 */
00058
00059 /* Exported macro ------------------------------------------------------------*/
00060 #ifdef  USE_FULL_ASSERT
00061
00062 /**
00063   * @brief  The assert_param macro is used for function's parameters check.
00064   * @param  expr: If expr is false, it calls assert_failed function which reports
00065   *         the name of the source file and the source line number of the call
00066   *         that failed. If expr is true, it returns no value.
00067   * @retval None
00068   */
00069   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00070 /* Exported functions ------------------------------------------------------- */
00071   void assert_failed(uint8_t* file, uint32_t line);
00072 #else
00073   #define assert_param(expr) ((void)0)
00074 #endif /* USE_FULL_ASSERT */
00075
00076 #endif /* __STM32F10x_CONF_H */
00077
00078 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/stm32f10x_it.c

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00001 /**
00002   ******************************************************************************
00003   * @file    SPI/FullDuplex_SoftNSS/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and peripherals
00009   *          interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026
00027 /** @addtogroup STM32F10x_StdPeriph_Examples
00028   * @{
00029   */
00030
00031 /** @addtogroup SPI_FullDuplex_SoftNSS
00032   * @{
00033   */
00034
00035 /* Private typedef -----------------------------------------------------------*/
00036 /* Private define ------------------------------------------------------------*/
00037 /* Private macro -------------------------------------------------------------*/
00038 /* Private variables ---------------------------------------------------------*/
00039 /* Private function prototypes -----------------------------------------------*/
00040 /* Private functions ---------------------------------------------------------*/
00041
00042 /******************************************************************************/
00043 /*            Cortex-M3 Processor Exceptions Handlers                         */
00044 /******************************************************************************/
00045
00046 /**
00047   * @brief  This function handles NMI exception.
00048   * @param  None
00049   * @retval None
00050   */
00051 void NMI_Handler(void)
00052 {
00053 }
00054
00055 /**
00056   * @brief  This function handles Hard Fault exception.
00057   * @param  None
00058   * @retval None
00059   */
00060 void HardFault_Handler(void)
00061 {
00062   /* Go to infinite loop when Hard Fault exception occurs */
00063   while (1)
00064   {}
00065 }
00066
00067 /**
00068   * @brief  This function handles Memory Manage exception.
00069   * @param  None
00070   * @retval None
00071   */
00072 void MemManage_Handler(void)
00073 {
00074   /* Go to infinite loop when Memory Manage exception occurs */
00075   while (1)
00076   {}
00077 }
00078
00079 /**
00080   * @brief  This function handles Bus Fault exception.
00081   * @param  None
00082   * @retval None
00083   */
00084 void BusFault_Handler(void)
00085 {
00086   /* Go to infinite loop when Bus Fault exception occurs */
00087   while (1)
00088   {}
00089 }
00090
00091 /**
00092   * @brief  This function handles Usage Fault exception.
00093   * @param  None
00094   * @retval None
00095   */
00096 void UsageFault_Handler(void)
00097 {
00098   /* Go to infinite loop when Usage Fault exception occurs */
00099   while (1)
00100   {}
00101 }
00102
00103 /**
00104   * @brief  This function handles Debug Monitor exception.
00105   * @param  None
00106   * @retval None
00107   */
00108 void DebugMon_Handler(void)
00109 {}
00110
00111 /**
00112   * @brief  This function handles SVCall exception.
00113   * @param  None
00114   * @retval None
00115   */
00116 void SVC_Handler(void)
00117 {}
00118
00119 /**
00120   * @brief  This function handles PendSV_Handler exception.
00121   * @param  None
00122   * @retval None
00123   */
00124 void PendSV_Handler(void)
00125 {}
00126
00127 /**
00128   * @brief  This function handles SysTick Handler.
00129   * @param  None
00130   * @retval None
00131   */
00132 void SysTick_Handler(void)
00133 {}
00134
00135 /******************************************************************************/
00136 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00137 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00138 /*  available peripheral interrupt handler's name please refer to the startup */
00139 /*  file (startup_stm32f10x_xx.s).                                            */
00140 /******************************************************************************/
00141
00142 /**
00143   * @brief  This function handles PPP interrupt request.
00144   * @param  None
00145   * @retval None
00146   */
00147 /*void PPP_IRQHandler(void)
00148 {
00149 }*/
00150
00151 /**
00152   * @}
00153   */
00154
00155 /**
00156   * @}
00157   */
00158
00159 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/stm32f10x_it.h

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00001 /**
00002   ******************************************************************************
00003   * @file    SPI/FullDuplex_SoftNSS/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043
00044 #endif /* __STM32F10x_IT_H */
00045
00046 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/main.c

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00001 /**
00002   ******************************************************************************
00003   * @file    SPI/Simplex_Interrupt/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x.h"
00024 #include "platform_config.h"
00025
00026 /** @addtogroup STM32F10x_StdPeriph_Examples
00027   * @{
00028   */
00029
00030 /** @addtogroup SPI_Simplex_Interrupt
00031   * @{
00032   */
00033
00034 /* Private typedef -----------------------------------------------------------*/
00035 typedef enum {FAILED = 0, PASSED = !FAILED} TestStatus;
00036
00037 /* Private define ------------------------------------------------------------*/
00038 #define BufferSize 32
00039
00040 /* Private macro -------------------------------------------------------------*/
00041 /* Private variables ---------------------------------------------------------*/
00042 SPI_InitTypeDef SPI_InitStructure;
00043 uint8_t SPI_MASTER_Buffer_Tx[BufferSize] = {0x01, 0x02, 0x03, 0x04, 0x05, 0x06,
00044                                             0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C,
00045                                             0x0D, 0x0E, 0x0F, 0x10, 0x11, 0x12,
00046                                             0x13, 0x14, 0x15, 0x16, 0x17, 0x18,
00047                                             0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E,
00048                                             0x1F, 0x20};
00049 uint8_t SPI_SLAVE_Buffer_Rx[BufferSize];
00050 __IO uint8_t TxIdx = 0, RxIdx = 0;
00051 volatile TestStatus TransferStatus = FAILED;
00052
00053 /* Private functions ---------------------------------------------------------*/
00054 void RCC_Configuration(void);
00055 void GPIO_Configuration(void);
00056 void NVIC_Configuration(void);
00057 TestStatus Buffercmp(uint8_t* pBuffer1, uint8_t* pBuffer2, uint16_t BufferLength);
00058
00059 /**
00060   * @brief  Main program
00061   * @param  None
00062   * @retval None
00063   */
00064 int main(void)
00065 {
00066   /*!< At this stage the microcontroller clock setting is already configured,
00067        this is done through SystemInit() function which is called from startup
00068        file (startup_stm32f10x_xx.s) before to branch to application main.
00069        To reconfigure the default setting of SystemInit() function, refer to
00070        system_stm32f10x.c file
00071      */
00072
00073   /* System clocks configuration ---------------------------------------------*/
00074   RCC_Configuration();
00075
00076   /* NVIC configuration ------------------------------------------------------*/
00077   NVIC_Configuration();
00078
00079   /* GPIO configuration ------------------------------------------------------*/
00080   GPIO_Configuration();
00081
00082   /* SPI_MASTER configuration ------------------------------------------------*/
00083   SPI_InitStructure.SPI_Direction = SPI_Direction_1Line_Tx;
00084   SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
00085   SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
00086   SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low;
00087   SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge;
00088   SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
00089   SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_4;
00090   SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
00091   SPI_InitStructure.SPI_CRCPolynomial = 7;
00092   SPI_Init(SPI_MASTER, &SPI_InitStructure);
00093
00094   /* SPI_SLAVE configuration -------------------------------------------------*/
00095   SPI_InitStructure.SPI_Direction = SPI_Direction_1Line_Rx;
00096   SPI_InitStructure.SPI_Mode = SPI_Mode_Slave;
00097   SPI_Init(SPI_SLAVE, &SPI_InitStructure);
00098
00099   /* Enable SPI_MASTER TXE interrupt */
00100   SPI_I2S_ITConfig(SPI_MASTER, SPI_I2S_IT_TXE, ENABLE);
00101   /* Enable SPI_SLAVE RXNE interrupt */
00102   SPI_I2S_ITConfig(SPI_SLAVE, SPI_I2S_IT_RXNE, ENABLE);
00103
00104   /* Enable SPI_SLAVE */
00105   SPI_Cmd(SPI_SLAVE, ENABLE);
00106   /* Enable SPI_MASTER */
00107   SPI_Cmd(SPI_MASTER, ENABLE);
00108
00109   /* Transfer procedure */
00110   while (RxIdx < BufferSize)
00111   {}
00112
00113   /* Check the correctness of written dada */
00114   TransferStatus = Buffercmp(SPI_SLAVE_Buffer_Rx, SPI_MASTER_Buffer_Tx, BufferSize);
00115   /* TransferStatus = PASSED, if the transmitted and received data
00116      are equal */
00117   /* TransferStatus = FAILED, if the transmitted and received data
00118      are different */
00119
00120   while (1)
00121   {}
00122 }
00123
00124 /**
00125   * @brief  Configures the different system clocks.
00126   * @param  None
00127   * @retval None
00128   */
00129 void RCC_Configuration(void)
00130 {
00131   /* PCLK2 = HCLK/2 */
00132   RCC_PCLK2Config(RCC_HCLK_Div2);
00133
00134 /* Enable peripheral clocks --------------------------------------------------*/
00135 #ifdef USE_STM3210C_EVAL
00136   /* Enable GPIO clock for SPI_MASTER and SPI_SLAVE */
00137   RCC_APB2PeriphClockCmd(SPI_MASTER_GPIO_CLK | SPI_SLAVE_GPIO_CLK |
00138                          RCC_APB2Periph_AFIO, ENABLE);
00139
00140   /* Enable SPI_MASTER Periph clock */
00141   RCC_APB1PeriphClockCmd(SPI_MASTER_CLK, ENABLE);
00142 #else
00143   /* Enable SPI_MASTER clock and GPIO clock for SPI_MASTER and SPI_SLAVE */
00144   RCC_APB2PeriphClockCmd(SPI_MASTER_GPIO_CLK | SPI_SLAVE_GPIO_CLK |
00145                          SPI_MASTER_CLK, ENABLE);
00146 #endif
00147   /* Enable SPI_SLAVE Periph clock */
00148   RCC_APB1PeriphClockCmd(SPI_SLAVE_CLK, ENABLE);
00149 }
00150
00151 /**
00152   * @brief  Configures the different GPIO ports.
00153   * @param  None
00154   * @retval None
00155   */
00156 void GPIO_Configuration(void)
00157 {
00158   GPIO_InitTypeDef GPIO_InitStructure;
00159
00160 #ifdef USE_STM3210C_EVAL
00161   /* Enable SPI3 Pins Software Remapping */
00162   GPIO_PinRemapConfig(GPIO_Remap_SPI3, ENABLE);
00163 #endif
00164
00165   /* Configure SPI_MASTER pins: SCK and MOSI ---------------------------------*/
00166   /* Configure SCK and MOSI pins as Alternate Function Push Pull */
00167   GPIO_InitStructure.GPIO_Pin = SPI_MASTER_PIN_SCK | SPI_MASTER_PIN_MOSI;
00168   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00169   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
00170   GPIO_Init(SPI_MASTER_GPIO, &GPIO_InitStructure);
00171
00172   /* Configure SPI_SLAVE pins: SCK and MISO ---------------------------------*/
00173   /* Configure SCK and MOSI pins as Input Floating */
00174   GPIO_InitStructure.GPIO_Pin = SPI_SLAVE_PIN_SCK ;
00175   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
00176   GPIO_Init(SPI_SLAVE_GPIO, &GPIO_InitStructure);
00177   /* Configure MISO pin as Alternate Function Push Pull */
00178   GPIO_InitStructure.GPIO_Pin = SPI_SLAVE_PIN_MISO;
00179   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
00180   GPIO_Init(SPI_SLAVE_GPIO, &GPIO_InitStructure);
00181 }
00182
00183 /**
00184   * @brief  Configure the nested vectored interrupt controller.
00185   * @param  None
00186   * @retval None
00187   */
00188 void NVIC_Configuration(void)
00189 {
00190   NVIC_InitTypeDef NVIC_InitStructure;
00191
00192   /* 1 bit for pre-emption priority, 3 bits for subpriority */
00193   NVIC_PriorityGroupConfig(NVIC_PriorityGroup_1);
00194
00195   /* Configure and enable SPI_MASTER interrupt -------------------------------*/
00196   NVIC_InitStructure.NVIC_IRQChannel = SPI_MASTER_IRQn;
00197   NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
00198   NVIC_InitStructure.NVIC_IRQChannelSubPriority = 2;
00199   NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
00200   NVIC_Init(&NVIC_InitStructure);
00201
00202   /* Configure and enable SPI_SLAVE interrupt --------------------------------*/
00203   NVIC_InitStructure.NVIC_IRQChannel = SPI_SLAVE_IRQn;
00204   NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
00205   NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;
00206   NVIC_Init(&NVIC_InitStructure);
00207 }
00208
00209 /**
00210   * @brief  Compares two buffers.
00211   * @param  pBuffer1, pBuffer2: buffers to be compared.
00212   * @param  BufferLength: buffer's length
00213   * @retval PASSED: pBuffer1 identical to pBuffer2
00214   *         FAILED: pBuffer1 differs from pBuffer2
00215   */
00216 TestStatus Buffercmp(uint8_t* pBuffer1, uint8_t* pBuffer2, uint16_t BufferLength)
00217 {
00218   while (BufferLength--)
00219   {
00220     if (*pBuffer1 != *pBuffer2)
00221     {
00222       return FAILED;
00223     }
00224
00225     pBuffer1++;
00226     pBuffer2++;
00227   }
00228
00229   return PASSED;
00230 }
00231
00232 #ifdef  USE_FULL_ASSERT
00233
00234 /**
00235   * @brief  Reports the name of the source file and the source line number
00236   *         where the assert_param error has occurred.
00237   * @param  file: pointer to the source file name
00238   * @param  line: assert_param error line source number
00239   * @retval None
00240   */
00241 void assert_failed(uint8_t* file, uint32_t line)
00242 {
00243   /* User can add his own implementation to report the file name and line number,
00244      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00245
00246   /* Infinite loop */
00247   while (1)
00248   {}
00249 }
00250
00251 #endif
00252
00253 /**
00254   * @}
00255   */
00256
00257 /**
00258   * @}
00259   */
00260
00261 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_conf.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file SPI/Simplex_Interrupt/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052 /* Exported types ------------------------------------------------------------*/
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Uncomment the line below to expanse the "assert_param" macro in the
00055    Standard Peripheral Library drivers code */
00056 /* #define USE_FULL_ASSERT    1 */
00057
00058 /* Exported macro ------------------------------------------------------------*/
00059 #ifdef  USE_FULL_ASSERT
00060
00061 /**
00062   * @brief  The assert_param macro is used for function's parameters check.
00063   * @param  expr: If expr is false, it calls assert_failed function which reports
00064   *         the name of the source file and the source line number of the call
00065   *         that failed. If expr is true, it returns no value.
00066   * @retval None
00067   */
00068   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00069 /* Exported functions ------------------------------------------------------- */
00070   void assert_failed(uint8_t* file, uint32_t line);
00071 #else
00072   #define assert_param(expr) ((void)0)
00073 #endif /* USE_FULL_ASSERT */
00074
00075 #endif /* __STM32F10x_CONF_H */
00076
00077 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.c

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00001 /**
00002   ******************************************************************************
00003   * @file    SPI/Simplex_Interrupt/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and peripherals
00009   *          interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026 #include "platform_config.h"
00027
00028 /** @addtogroup STM32F10x_StdPeriph_Examples
00029   * @{
00030   */
00031
00032 /** @addtogroup SPI_Simplex_Interrupt
00033   * @{
00034   */
00035
00036 /* Private typedef -----------------------------------------------------------*/
00037 /* Private define ------------------------------------------------------------*/
00038 #define BufferSize  32
00039
00040 /* Private macro -------------------------------------------------------------*/
00041 /* Private variables ---------------------------------------------------------*/
00042 extern __IO uint8_t TxIdx, RxIdx;
00043 extern uint8_t SPI_MASTER_Buffer_Tx[BufferSize], SPI_SLAVE_Buffer_Rx[BufferSize];
00044
00045 /* Private variables ---------------------------------------------------------*/
00046 /* Private function prototypes -----------------------------------------------*/
00047 /* Private functions ---------------------------------------------------------*/
00048
00049 /******************************************************************************/
00050 /*            Cortex-M3 Processor Exceptions Handlers                         */
00051 /******************************************************************************/
00052
00053 /**
00054   * @brief  This function handles NMI exception.
00055   * @param  None
00056   * @retval None
00057   */
00058 void NMI_Handler(void)
00059 {
00060 }
00061
00062 /**
00063   * @brief  This function handles Hard Fault exception.
00064   * @param  None
00065   * @retval None
00066   */
00067 void HardFault_Handler(void)
00068 {
00069   /* Go to infinite loop when Hard Fault exception occurs */
00070   while (1)
00071   {}
00072 }
00073
00074 /**
00075   * @brief  This function handles Memory Manage exception.
00076   * @param  None
00077   * @retval None
00078   */
00079 void MemManage_Handler(void)
00080 {
00081   /* Go to infinite loop when Memory Manage exception occurs */
00082   while (1)
00083   {}
00084 }
00085
00086 /**
00087   * @brief  This function handles Bus Fault exception.
00088   * @param  None
00089   * @retval None
00090   */
00091 void BusFault_Handler(void)
00092 {
00093   /* Go to infinite loop when Bus Fault exception occurs */
00094   while (1)
00095   {}
00096 }
00097
00098 /**
00099   * @brief  This function handles Usage Fault exception.
00100   * @param  None
00101   * @retval None
00102   */
00103 void UsageFault_Handler(void)
00104 {
00105   /* Go to infinite loop when Usage Fault exception occurs */
00106   while (1)
00107   {}
00108 }
00109
00110 /**
00111   * @brief  This function handles Debug Monitor exception.
00112   * @param  None
00113   * @retval None
00114   */
00115 void DebugMon_Handler(void)
00116 {}
00117
00118 /**
00119   * @brief  This function handles SVCall exception.
00120   * @param  None
00121   * @retval None
00122   */
00123 void SVC_Handler(void)
00124 {}
00125
00126 /**
00127   * @brief  This function handles PendSV_Handler exception.
00128   * @param  None
00129   * @retval None
00130   */
00131 void PendSV_Handler(void)
00132 {}
00133
00134 /**
00135   * @brief  This function handles SysTick Handler.
00136   * @param  None
00137   * @retval None
00138   */
00139 void SysTick_Handler(void)
00140 {}
00141
00142 /******************************************************************************/
00143 /*            STM32F10x Peripherals Interrupt Handlers                        */
00144 /******************************************************************************/
00145
00146 /**
00147   * @brief  This function handles SPI1 or SPI3 global interrupt request.
00148   * @param  None
00149   * @retval None
00150   */
00151 #ifndef  USE_STM3210C_EVAL
00152  void SPI1_IRQHandler(void)
00153 #else
00154  void SPI3_IRQHandler(void)
00155 #endif
00156 {
00157   if (SPI_I2S_GetITStatus(SPI_MASTER, SPI_I2S_IT_TXE) != RESET)
00158   {
00159     /* Send SPI_MASTER data */
00160     SPI_I2S_SendData(SPI_MASTER, SPI_MASTER_Buffer_Tx[TxIdx++]);
00161
00162     /* Disable SPI_MASTER TXE interrupt */
00163     if (TxIdx == BufferSize)
00164     {
00165       SPI_I2S_ITConfig(SPI_MASTER, SPI_I2S_IT_TXE, DISABLE);
00166     }
00167   }
00168 }
00169
00170 /**
00171   * @brief  This function handles SPI2 global interrupt request.
00172   * @param  None
00173   * @retval None
00174   */
00175 void SPI2_IRQHandler(void)
00176 {
00177   /* Store SPI_SLAVE received data */
00178   SPI_SLAVE_Buffer_Rx[RxIdx++] = SPI_I2S_ReceiveData(SPI_SLAVE);
00179 }
00180
00181 /******************************************************************************/
00182 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00183 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00184 /*  available peripheral interrupt handler's name please refer to the startup */
00185 /*  file (startup_stm32f10x_xx.s).                                            */
00186 /******************************************************************************/
00187
00188 /**
00189   * @brief  This function handles PPP interrupt request.
00190   * @param  None
00191   * @retval None
00192   */
00193 /*void PPP_IRQHandler(void)
00194 {
00195 }*/
00196
00197 /**
00198   * @}
00199   */
00200
00201 /**
00202   * @}
00203   */
00204
00205 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file SPI/Simplex_Interrupt/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043 void SPI1_IRQHandler(void);
00044 void SPI2_IRQHandler(void);
00045 void SPI3_IRQHandler(void);
00046
00047 #endif /* __STM32F10x_IT_H */
00048
00049 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/main.c

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00001 /**
00002   ******************************************************************************
00003   * @file    SPI/SPI_FLASH/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32_eval.h"
00024 #include "stm32_eval_spi_flash.h"
00025
00026 /** @addtogroup STM32F10x_StdPeriph_Examples
00027   * @{
00028   */
00029
00030 /** @addtogroup SPI_FLASH
00031   * @{
00032   */
00033
00034 /* Private typedef -----------------------------------------------------------*/
00035 typedef enum {FAILED = 0, PASSED = !FAILED} TestStatus;
00036
00037 /* Private define ------------------------------------------------------------*/
00038 #define  FLASH_WriteAddress     0x700000
00039 #define  FLASH_ReadAddress      FLASH_WriteAddress
00040 #define  FLASH_SectorToErase    FLASH_WriteAddress
00041
00042 #if defined(USE_STM32100B_EVAL) || defined(USE_STM32100E_EVAL)
00043   #define  sFLASH_ID       sFLASH_M25P128_ID
00044 #else
00045   #define  sFLASH_ID       sFLASH_M25P64_ID
00046 #endif
00047
00048 #define  BufferSize (countof(Tx_Buffer)-1)
00049
00050 /* Private macro -------------------------------------------------------------*/
00051 #define countof(a) (sizeof(a) / sizeof(*(a)))
00052
00053 /* Private variables ---------------------------------------------------------*/
00054 uint8_t Tx_Buffer[] = "STM32F10x SPI Firmware Library Example: communication with an M25P SPI FLASH";
00055 uint8_t  Rx_Buffer[BufferSize];
00056 __IO uint8_t Index = 0x0;
00057 volatile TestStatus TransferStatus1 = FAILED, TransferStatus2 = PASSED;
00058 __IO uint32_t FlashID = 0;
00059
00060 /* Private functions ---------------------------------------------------------*/
00061 TestStatus Buffercmp(uint8_t* pBuffer1, uint8_t* pBuffer2, uint16_t BufferLength);
00062
00063 /**
00064   * @brief  Main program
00065   * @param  None
00066   * @retval None
00067   */
00068 int main(void)
00069 {
00070   /*!< At this stage the microcontroller clock setting is already configured,
00071        this is done through SystemInit() function which is called from startup
00072        file (startup_stm32f10x_xx.s) before to branch to application main.
00073        To reconfigure the default setting of SystemInit() function, refer to
00074        system_stm32f10x.c file
00075      */
00076
00077   /* Initialize Leds mounted on STM3210X-EVAL board */
00078   STM_EVAL_LEDInit(LED1);
00079   STM_EVAL_LEDInit(LED2);
00080
00081   /* Initialize the SPI FLASH driver */
00082   sFLASH_Init();
00083
00084   /* Get SPI Flash ID */
00085   FlashID = sFLASH_ReadID();
00086
00087   /* Check the SPI Flash ID */
00088   if (FlashID == sFLASH_ID)
00089   {
00090     /* OK: Turn on LD1 */
00091     STM_EVAL_LEDOn(LED1);
00092
00093     /* Perform a write in the Flash followed by a read of the written data */
00094     /* Erase SPI FLASH Sector to write on */
00095     sFLASH_EraseSector(FLASH_SectorToErase);
00096
00097     /* Write Tx_Buffer data to SPI FLASH memory */
00098     sFLASH_WriteBuffer(Tx_Buffer, FLASH_WriteAddress, BufferSize);
00099
00100     /* Read data from SPI FLASH memory */
00101     sFLASH_ReadBuffer(Rx_Buffer, FLASH_ReadAddress, BufferSize);
00102
00103     /* Check the correctness of written dada */
00104     TransferStatus1 = Buffercmp(Tx_Buffer, Rx_Buffer, BufferSize);
00105     /* TransferStatus1 = PASSED, if the transmitted and received data by SPI1
00106        are the same */
00107     /* TransferStatus1 = FAILED, if the transmitted and received data by SPI1
00108        are different */
00109
00110     /* Perform an erase in the Flash followed by a read of the written data */
00111     /* Erase SPI FLASH Sector to write on */
00112     sFLASH_EraseSector(FLASH_SectorToErase);
00113
00114     /* Read data from SPI FLASH memory */
00115     sFLASH_ReadBuffer(Rx_Buffer, FLASH_ReadAddress, BufferSize);
00116
00117     /* Check the correctness of erasing operation dada */
00118     for (Index = 0; Index < BufferSize; Index++)
00119     {
00120       if (Rx_Buffer[Index] != 0xFF)
00121       {
00122         TransferStatus2 = FAILED;
00123       }
00124     }
00125     /* TransferStatus2 = PASSED, if the specified sector part is erased */
00126     /* TransferStatus2 = FAILED, if the specified sector part is not well erased */
00127   }
00128   else
00129   {
00130     /* Error: Turn on LD2 */
00131     STM_EVAL_LEDOn(LED2);
00132   }
00133
00134   while (1)
00135   {}
00136 }
00137
00138 /**
00139   * @brief  Compares two buffers.
00140   * @param  pBuffer1, pBuffer2: buffers to be compared.
00141   * @param  BufferLength: buffer's length
00142   * @retval PASSED: pBuffer1 identical to pBuffer2
00143   *         FAILED: pBuffer1 differs from pBuffer2
00144   */
00145 TestStatus Buffercmp(uint8_t* pBuffer1, uint8_t* pBuffer2, uint16_t BufferLength)
00146 {
00147   while (BufferLength--)
00148   {
00149     if (*pBuffer1 != *pBuffer2)
00150     {
00151       return FAILED;
00152     }
00153
00154     pBuffer1++;
00155     pBuffer2++;
00156   }
00157
00158   return PASSED;
00159 }
00160
00161 #ifdef  USE_FULL_ASSERT
00162
00163 /**
00164   * @brief  Reports the name of the source file and the source line number
00165   *         where the assert_param error has occurred.
00166   * @param  file: pointer to the source file name
00167   * @param  line: assert_param error line source number
00168   * @retval None
00169   */
00170 void assert_failed(uint8_t* file, uint32_t line)
00171 {
00172   /* User can add his own implementation to report the file name and line number,
00173      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00174
00175   /* Infinite loop */
00176   while (1)
00177   {}
00178 }
00179
00180 #endif
00181 /**
00182   * @}
00183   */
00184
00185 /**
00186   * @}
00187   */
00188
00189 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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  • SPI_FLASH

STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/stm32f10x_conf.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    SPI/SPI_FLASH/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052 /* Exported types ------------------------------------------------------------*/
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Uncomment the line below to expanse the "assert_param" macro in the
00055    Standard Peripheral Library drivers code */
00056 /* #define USE_FULL_ASSERT    1 */
00057
00058 /* Exported macro ------------------------------------------------------------*/
00059 #ifdef  USE_FULL_ASSERT
00060
00061 /**
00062   * @brief  The assert_param macro is used for function's parameters check.
00063   * @param  expr: If expr is false, it calls assert_failed function which reports
00064   *         the name of the source file and the source line number of the call
00065   *         that failed. If expr is true, it returns no value.
00066   * @retval None
00067   */
00068   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00069 /* Exported functions ------------------------------------------------------- */
00070   void assert_failed(uint8_t* file, uint32_t line);
00071 #else
00072   #define assert_param(expr) ((void)0)
00073 #endif /* USE_FULL_ASSERT */
00074
00075 #endif /* __STM32F10x_CONF_H */
00076
00077 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/stm32f10x_it.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    SPI/SPI_FLASH/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and peripherals
00009   *          interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026
00027 /** @addtogroup STM32F10x_StdPeriph_Examples
00028   * @{
00029   */
00030
00031 /** @addtogroup SPI_FLASH
00032   * @{
00033   */
00034
00035 /* Private typedef -----------------------------------------------------------*/
00036 /* Private define ------------------------------------------------------------*/
00037 /* Private macro -------------------------------------------------------------*/
00038 /* Private variables ---------------------------------------------------------*/
00039 /* Private function prototypes -----------------------------------------------*/
00040 /* Private functions ---------------------------------------------------------*/
00041
00042 /******************************************************************************/
00043 /*            Cortex-M3 Processor Exceptions Handlers                         */
00044 /******************************************************************************/
00045
00046 /**
00047   * @brief  This function handles NMI exception.
00048   * @param  None
00049   * @retval None
00050   */
00051 void NMI_Handler(void)
00052 {
00053 }
00054
00055 /**
00056   * @brief  This function handles Hard Fault exception.
00057   * @param  None
00058   * @retval None
00059   */
00060 void HardFault_Handler(void)
00061 {
00062   /* Go to infinite loop when Hard Fault exception occurs */
00063   while (1)
00064   {}
00065 }
00066
00067 /**
00068   * @brief  This function handles Memory Manage exception.
00069   * @param  None
00070   * @retval None
00071   */
00072 void MemManage_Handler(void)
00073 {
00074   /* Go to infinite loop when Memory Manage exception occurs */
00075   while (1)
00076   {}
00077 }
00078
00079 /**
00080   * @brief  This function handles Bus Fault exception.
00081   * @param  None
00082   * @retval None
00083   */
00084 void BusFault_Handler(void)
00085 {
00086   /* Go to infinite loop when Bus Fault exception occurs */
00087   while (1)
00088   {}
00089 }
00090
00091 /**
00092   * @brief  This function handles Usage Fault exception.
00093   * @param  None
00094   * @retval None
00095   */
00096 void UsageFault_Handler(void)
00097 {
00098   /* Go to infinite loop when Usage Fault exception occurs */
00099   while (1)
00100   {}
00101 }
00102
00103 /**
00104   * @brief  This function handles Debug Monitor exception.
00105   * @param  None
00106   * @retval None
00107   */
00108 void DebugMon_Handler(void)
00109 {}
00110
00111 /**
00112   * @brief  This function handles SVCall exception.
00113   * @param  None
00114   * @retval None
00115   */
00116 void SVC_Handler(void)
00117 {}
00118
00119 /**
00120   * @brief  This function handles PendSV_Handler exception.
00121   * @param  None
00122   * @retval None
00123   */
00124 void PendSV_Handler(void)
00125 {}
00126
00127 /**
00128   * @brief  This function handles SysTick Handler.
00129   * @param  None
00130   * @retval None
00131   */
00132 void SysTick_Handler(void)
00133 {}
00134
00135 /******************************************************************************/
00136 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00137 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00138 /*  available peripheral interrupt handler's name please refer to the startup */
00139 /*  file (startup_stm32f10x_xx.s).                                            */
00140 /******************************************************************************/
00141
00142 /**
00143   * @brief  This function handles PPP interrupt request.
00144   * @param  None
00145   * @retval None
00146   */
00147 /*void PPP_IRQHandler(void)
00148 {
00149 }*/
00150
00151 /**
00152   * @}
00153   */
00154
00155 /**
00156   * @}
00157   */
00158
00159 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/stm32f10x_it.h

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00001 /**
00002   ******************************************************************************
00003   * @file    SPI/SPI_FLASH/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043
00044 #endif /* __STM32F10x_IT_H */
00045
00046 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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STM32F10x_StdPeriph_Examples/SysTick/TimeBase/main.c

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00001 /**
00002   ******************************************************************************
00003   * @file    SysTick/TimeBase/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "main.h"
00024
00025 /** @addtogroup STM32F10x_StdPeriph_Examples
00026   * @{
00027   */
00028
00029 /** @addtogroup SysTick_TimeBase
00030   * @{
00031   */
00032
00033 /* Private typedef -----------------------------------------------------------*/
00034 /* Private define ------------------------------------------------------------*/
00035 /* Private macro -------------------------------------------------------------*/
00036 /* Private variables ---------------------------------------------------------*/
00037 static __IO uint32_t TimingDelay;
00038
00039 /* Private function prototypes -----------------------------------------------*/
00040 void Delay(__IO uint32_t nTime);
00041
00042 /* Private functions ---------------------------------------------------------*/
00043
00044 /**
00045   * @brief  Main program.
00046   * @param  None
00047   * @retval None
00048   */
00049 int main(void)
00050 {
00051   /*!< At this stage the microcontroller clock setting is already configured,
00052        this is done through SystemInit() function which is called from startup
00053        file (startup_stm32f10x_xx.s) before to branch to application main.
00054        To reconfigure the default setting of SystemInit() function, refer to
00055        system_stm32f10x.c file
00056      */
00057
00058   /* Initialize Leds mounted on STM3210X-EVAL board */
00059   STM_EVAL_LEDInit(LED1);
00060   STM_EVAL_LEDInit(LED2);
00061   STM_EVAL_LEDInit(LED3);
00062   STM_EVAL_LEDInit(LED4);
00063
00064   /* Turn on LED1 and LED3 */
00065   STM_EVAL_LEDOn(LED1);
00066   STM_EVAL_LEDOn(LED3);
00067
00068   /* Setup SysTick Timer for 1 msec interrupts.
00069      ------------------------------------------
00070     1. The SysTick_Config() function is a CMSIS function which configure:
00071        - The SysTick Reload register with value passed as function parameter.
00072        - Configure the SysTick IRQ priority to the lowest value (0x0F).
00073        - Reset the SysTick Counter register.
00074        - Configure the SysTick Counter clock source to be Core Clock Source (HCLK).
00075        - Enable the SysTick Interrupt.
00076        - Start the SysTick Counter.
00077
00078     2. You can change the SysTick Clock source to be HCLK_Div8 by calling the
00079        SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK_Div8) just after the
00080        SysTick_Config() function call. The SysTick_CLKSourceConfig() is defined
00081        inside the misc.c file.
00082
00083     3. You can change the SysTick IRQ priority by calling the
00084        NVIC_SetPriority(SysTick_IRQn,...) just after the SysTick_Config() function
00085        call. The NVIC_SetPriority() is defined inside the core_cm3.h file.
00086
00087     4. To adjust the SysTick time base, use the following formula:
00088
00089          Reload Value = SysTick Counter Clock (Hz) x  Desired Time base (s)
00090
00091        - Reload Value is the parameter to be passed for SysTick_Config() function
00092        - Reload Value should not exceed 0xFFFFFF
00093    */
00094   if (SysTick_Config(SystemCoreClock / 1000))
00095   {
00096     /* Capture error */
00097     while (1);
00098   }
00099
00100   while (1)
00101   {
00102     /* Toggle LED2 and LED4 */
00103     STM_EVAL_LEDToggle(LED2);
00104     STM_EVAL_LEDToggle(LED4);
00105
00106     /* Insert 50 ms delay */
00107     Delay(50);
00108
00109     /* Toggle LED1 and LED3 */
00110     STM_EVAL_LEDToggle(LED1);
00111     STM_EVAL_LEDToggle(LED3);
00112
00113     /* Insert 100 ms delay */
00114     Delay(100);
00115   }
00116 }
00117
00118 /**
00119   * @brief  Inserts a delay time.
00120   * @param  nTime: specifies the delay time length, in milliseconds.
00121   * @retval None
00122   */
00123 void Delay(__IO uint32_t nTime)
00124 {
00125   TimingDelay = nTime;
00126
00127   while(TimingDelay != 0);
00128 }
00129
00130 /**
00131   * @brief  Decrements the TimingDelay variable.
00132   * @param  None
00133   * @retval None
00134   */
00135 void TimingDelay_Decrement(void)
00136 {
00137   if (TimingDelay != 0x00)
00138   {
00139     TimingDelay--;
00140   }
00141 }
00142
00143 #ifdef  USE_FULL_ASSERT
00144
00145 /**
00146   * @brief  Reports the name of the source file and the source line number
00147   *         where the assert_param error has occurred.
00148   * @param  file: pointer to the source file name
00149   * @param  line: assert_param error line source number
00150   * @retval None
00151   */
00152 void assert_failed(uint8_t* file, uint32_t line)
00153 {
00154   /* User can add his own implementation to report the file name and line number,
00155      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00156
00157   /* Infinite loop */
00158   while (1)
00159   {
00160   }
00161 }
00162
00163 #endif
00164
00165 /**
00166   * @}
00167   */
00168
00169 /**
00170   * @}
00171   */
00172
00173 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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STM32F10x_StdPeriph_Examples/SysTick/TimeBase/stm32f10x_conf.h

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00001 /**
00002   ******************************************************************************
00003   * @file    SysTick/TimeBase/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052 /* Exported types ------------------------------------------------------------*/
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Uncomment the line below to expanse the "assert_param" macro in the
00055    Standard Peripheral Library drivers code */
00056 /* #define USE_FULL_ASSERT    1 */
00057
00058 /* Exported macro ------------------------------------------------------------*/
00059 #ifdef  USE_FULL_ASSERT
00060
00061 /**
00062   * @brief  The assert_param macro is used for function's parameters check.
00063   * @param  expr: If expr is false, it calls assert_failed function which reports
00064   *         the name of the source file and the source line number of the call
00065   *         that failed. If expr is true, it returns no value.
00066   * @retval None
00067   */
00068   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00069 /* Exported functions ------------------------------------------------------- */
00070   void assert_failed(uint8_t* file, uint32_t line);
00071 #else
00072   #define assert_param(expr) ((void)0)
00073 #endif /* USE_FULL_ASSERT */
00074
00075 #endif /* __STM32F10x_CONF_H */
00076
00077 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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STM32F10x_StdPeriph_Examples/SysTick/TimeBase/stm32f10x_it.c

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00001 /**
00002   ******************************************************************************
00003   * @file    SysTick/TimeBase/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and peripherals
00009   *          interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026 #include "main.h"
00027
00028 /** @addtogroup STM32F10x_StdPeriph_Examples
00029   * @{
00030   */
00031
00032 /** @addtogroup SysTick_TimeBase
00033   * @{
00034   */
00035
00036 /* Private typedef -----------------------------------------------------------*/
00037 /* Private define ------------------------------------------------------------*/
00038 /* Private macro -------------------------------------------------------------*/
00039 /* Private variables ---------------------------------------------------------*/
00040 /* Private function prototypes -----------------------------------------------*/
00041 /* Private functions ---------------------------------------------------------*/
00042
00043 /******************************************************************************/
00044 /*            Cortex-M3 Processor Exceptions Handlers                         */
00045 /******************************************************************************/
00046
00047 /**
00048   * @brief  This function handles NMI exception.
00049   * @param  None
00050   * @retval None
00051   */
00052 void NMI_Handler(void)
00053 {
00054 }
00055
00056 /**
00057   * @brief  This function handles Hard Fault exception.
00058   * @param  None
00059   * @retval None
00060   */
00061 void HardFault_Handler(void)
00062 {
00063   /* Go to infinite loop when Hard Fault exception occurs */
00064   while (1)
00065   {
00066   }
00067 }
00068
00069 /**
00070   * @brief  This function handles Memory Manage exception.
00071   * @param  None
00072   * @retval None
00073   */
00074 void MemManage_Handler(void)
00075 {
00076   /* Go to infinite loop when Memory Manage exception occurs */
00077   while (1)
00078   {
00079   }
00080 }
00081
00082 /**
00083   * @brief  This function handles Bus Fault exception.
00084   * @param  None
00085   * @retval None
00086   */
00087 void BusFault_Handler(void)
00088 {
00089   /* Go to infinite loop when Bus Fault exception occurs */
00090   while (1)
00091   {
00092   }
00093 }
00094
00095 /**
00096   * @brief  This function handles Usage Fault exception.
00097   * @param  None
00098   * @retval None
00099   */
00100 void UsageFault_Handler(void)
00101 {
00102   /* Go to infinite loop when Usage Fault exception occurs */
00103   while (1)
00104   {
00105   }
00106 }
00107
00108 /**
00109   * @brief  This function handles SVCall exception.
00110   * @param  None
00111   * @retval None
00112   */
00113 void SVC_Handler(void)
00114 {
00115 }
00116
00117 /**
00118   * @brief  This function handles Debug Monitor exception.
00119   * @param  None
00120   * @retval None
00121   */
00122 void DebugMon_Handler(void)
00123 {
00124 }
00125
00126 /**
00127   * @brief  This function handles PendSV_Handler exception.
00128   * @param  None
00129   * @retval None
00130   */
00131 void PendSV_Handler(void)
00132 {
00133 }
00134
00135 /**
00136   * @brief  This function handles SysTick Handler.
00137   * @param  None
00138   * @retval None
00139   */
00140 void SysTick_Handler(void)
00141 {
00142   TimingDelay_Decrement();
00143 }
00144
00145 /******************************************************************************/
00146 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00147 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00148 /*  available peripheral interrupt handler's name please refer to the startup */
00149 /*  file (startup_stm32f10x_xx.s).                                            */
00150 /******************************************************************************/
00151
00152 /**
00153   * @brief  This function handles PPP interrupt request.
00154   * @param  None
00155   * @retval None
00156   */
00157 /*void PPP_IRQHandler(void)
00158 {
00159 }*/
00160
00161 /**
00162   * @}
00163   */
00164
00165 /**
00166   * @}
00167   */
00168
00169 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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STM32F10x_StdPeriph_Examples/SysTick/TimeBase/stm32f10x_it.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    SysTick/TimeBase/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043
00044 #endif /* __STM32F10x_IT_H */
00045
00046 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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  • Cascade_Synchro

STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/main.c

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00001 /**
00002   ******************************************************************************
00003   * @file    TIM/Cascade_Synchro/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x.h"
00024
00025 /** @addtogroup STM32F10x_StdPeriph_Examples
00026   * @{
00027   */
00028
00029 /** @addtogroup TIM_Cascade_Synchro
00030   * @{
00031   */
00032
00033 /* Private typedef -----------------------------------------------------------*/
00034 /* Private define ------------------------------------------------------------*/
00035 /* Private macro -------------------------------------------------------------*/
00036 /* Private variables ---------------------------------------------------------*/
00037 TIM_TimeBaseInitTypeDef  TIM_TimeBaseStructure;
00038 TIM_OCInitTypeDef  TIM_OCInitStructure;
00039
00040 /* Private function prototypes -----------------------------------------------*/
00041 void RCC_Configuration(void);
00042 void GPIO_Configuration(void);
00043
00044 /* Private functions ---------------------------------------------------------*/
00045
00046 /**
00047   * @brief  Main program
00048   * @param  None
00049   * @retval None
00050   */
00051 int main(void)
00052 {
00053   /*!< At this stage the microcontroller clock setting is already configured,
00054        this is done through SystemInit() function which is called from startup
00055        file (startup_stm32f10x_xx.s) before to branch to application main.
00056        To reconfigure the default setting of SystemInit() function, refer to
00057        system_stm32f10x.c file
00058      */
00059
00060   /* System Clocks Configuration */
00061   RCC_Configuration();
00062
00063   /* GPIO Configuration */
00064   GPIO_Configuration();
00065
00066   /* Timers synchronisation in cascade mode ----------------------------
00067      1/TIM2 is configured as Master Timer:
00068      - PWM Mode is used
00069      - The TIM2 Update event is used as Trigger Output
00070
00071      2/TIM3 is slave for TIM2 and Master for TIM4,
00072      - PWM Mode is used
00073      - The ITR1(TIM2) is used as input trigger
00074      - Gated mode is used, so start and stop of slave counter
00075       are controlled by the Master trigger output signal(TIM2 update event).
00076       - The TIM3 Update event is used as Trigger Output.
00077
00078       3/TIM4 is slave for TIM3,
00079      - PWM Mode is used
00080      - The ITR2(TIM3) is used as input trigger
00081      - Gated mode is used, so start and stop of slave counter
00082       are controlled by the Master trigger output signal(TIM3 update event).
00083
00084      * For Low-density, Medium-density, High-density and Connectivity line devices:
00085        The TIMxCLK is fixed to 72 MHz, the TIM2 counter clock is 72 MHz.
00086
00087        The Master Timer TIM2 is running at TIM2 frequency :
00088        TIM2 frequency = (TIM2 counter clock)/ (TIM2 period + 1) = 281.250 KHz
00089        and the duty cycle = TIM2_CCR1/(TIM2_ARR + 1) = 25%.
00090
00091        The TIM3 is running:
00092        - At (TIM2 frequency)/ (TIM3 period + 1) = 70.312 KHz and a duty cycle
00093          equal to TIM3_CCR1/(TIM3_ARR + 1) = 25%
00094
00095         The TIM4 is running:
00096       - At (TIM3 frequency)/ (TIM4 period + 1) = 17.578 KHz and a duty cycle
00097         equal to TIM4_CCR1/(TIM4_ARR + 1) = 25%
00098
00099      * For Low-Density Value line,Medium-Density and High-Density Value line devices:
00100        The TIMxCLK is fixed to 24 MHz, the TIM2 counter clock is 24 MHz.
00101        So TIM2 frequency = 93.750 KHz,
00102        TIM3 is running at 23.437 KHz,
00103        and TIM4 is running at 5.85 KHz
00104   -------------------------------------------------------------------- */
00105
00106   /* Time base configuration */
00107   TIM_TimeBaseStructure.TIM_Period = 255;
00108   TIM_TimeBaseStructure.TIM_Prescaler = 0;
00109   TIM_TimeBaseStructure.TIM_ClockDivision = 0;
00110   TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
00111
00112   TIM_TimeBaseInit(TIM2, &TIM_TimeBaseStructure);
00113
00114   TIM_TimeBaseStructure.TIM_Period = 3;
00115   TIM_TimeBaseInit(TIM3, &TIM_TimeBaseStructure);
00116
00117   TIM_TimeBaseStructure.TIM_Period = 3;
00118   TIM_TimeBaseInit(TIM4, &TIM_TimeBaseStructure);
00119
00120   /* Master Configuration in PWM1 Mode */
00121   TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1;
00122   TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
00123   TIM_OCInitStructure.TIM_Pulse = 64;
00124   TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High;
00125
00126   TIM_OC1Init(TIM2, &TIM_OCInitStructure);
00127
00128   /* Select the Master Slave Mode */
00129   TIM_SelectMasterSlaveMode(TIM2, TIM_MasterSlaveMode_Enable);
00130
00131   /* Master Mode selection */
00132   TIM_SelectOutputTrigger(TIM2, TIM_TRGOSource_Update);
00133
00134   /* Slaves Configuration: PWM1 Mode */
00135   TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1;
00136   TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
00137   TIM_OCInitStructure.TIM_Pulse = 1;
00138
00139   TIM_OC1Init(TIM3, &TIM_OCInitStructure);
00140
00141   TIM_OC1Init(TIM4, &TIM_OCInitStructure);
00142
00143   /* Slave Mode selection: TIM3 */
00144   TIM_SelectSlaveMode(TIM3, TIM_SlaveMode_Gated);
00145   TIM_SelectInputTrigger(TIM3, TIM_TS_ITR1);
00146
00147   /* Select the Master Slave Mode */
00148   TIM_SelectMasterSlaveMode(TIM3, TIM_MasterSlaveMode_Enable);
00149
00150   /* Master Mode selection: TIM3 */
00151   TIM_SelectOutputTrigger(TIM3, TIM_TRGOSource_Update);
00152
00153   /* Slave Mode selection: TIM4 */
00154   TIM_SelectSlaveMode(TIM4, TIM_SlaveMode_Gated);
00155   TIM_SelectInputTrigger(TIM4, TIM_TS_ITR2);
00156
00157   /* TIM enable counter */
00158   TIM_Cmd(TIM3, ENABLE);
00159   TIM_Cmd(TIM2, ENABLE);
00160   TIM_Cmd(TIM4, ENABLE);
00161
00162   while (1)
00163   {
00164   }
00165 }
00166
00167 /**
00168   * @brief  Configures the different system clocks.
00169   * @param  None
00170   * @retval None
00171   */
00172 void RCC_Configuration(void)
00173 {
00174   /* TIM2, TIM3 and TIM4 clock enable */
00175   RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2 | RCC_APB1Periph_TIM3 |
00176                          RCC_APB1Periph_TIM4, ENABLE);
00177
00178   /* GPIOA, GPIOB, GPIOC and AFIO clocks enable */
00179   RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB |
00180                          RCC_APB2Periph_GPIOC | RCC_APB2Periph_AFIO, ENABLE);
00181 }
00182
00183 /**
00184   * @brief  Configure the GPIOD Pins.
00185   * @param  None
00186   * @retval None
00187   */
00188 void GPIO_Configuration(void)
00189 {
00190   GPIO_InitTypeDef GPIO_InitStructure;
00191
00192 #ifdef STM32F10X_CL
00193   /*GPIOB Configuration:  PC6(TIM3 CH1) as alternate function push-pull */
00194   GPIO_InitStructure.GPIO_Pin =  GPIO_Pin_6 ;
00195   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
00196   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00197
00198   GPIO_Init(GPIOC, &GPIO_InitStructure);
00199
00200   GPIO_PinRemapConfig(GPIO_FullRemap_TIM3, ENABLE);
00201
00202 #else
00203 /* GPIOA Configuration: PA6(TIM3 CH1) as alternate function push-pull */
00204   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
00205   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
00206   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00207
00208   GPIO_Init(GPIOA, &GPIO_InitStructure);
00209 #endif
00210   /* GPIOA Configuration: PA0(TIM2 CH1) as alternate function push-pull */
00211   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0;
00212   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
00213   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00214
00215   GPIO_Init(GPIOA, &GPIO_InitStructure);
00216
00217   /* GPIOB Configuration: PB6(TIM4 CH1) as alternate function push-pull */
00218   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
00219
00220   GPIO_Init(GPIOB, &GPIO_InitStructure);
00221 }
00222
00223 #ifdef  USE_FULL_ASSERT
00224
00225 /**
00226   * @brief  Reports the name of the source file and the source line number
00227   *         where the assert_param error has occurred.
00228   * @param  file: pointer to the source file name
00229   * @param  line: assert_param error line source number
00230   * @retval None
00231   */
00232 void assert_failed(uint8_t* file, uint32_t line)
00233 {
00234   /* User can add his own implementation to report the file name and line number,
00235      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00236
00237   while (1)
00238   {}
00239 }
00240
00241 #endif
00242
00243 /**
00244   * @}
00245   */
00246
00247 /**
00248   * @}
00249   */
00250
00251 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f10x_conf.h

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00001 /**
00002   ******************************************************************************
00003   * @file    TIM/Cascade_Synchro/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052 /* Exported types ------------------------------------------------------------*/
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Uncomment the line below to expanse the "assert_param" macro in the
00055    Standard Peripheral Library drivers code */
00056 /* #define USE_FULL_ASSERT    1 */
00057
00058 /* Exported macro ------------------------------------------------------------*/
00059 #ifdef  USE_FULL_ASSERT
00060
00061 /**
00062   * @brief  The assert_param macro is used for function's parameters check.
00063   * @param  expr: If expr is false, it calls assert_failed function which reports
00064   *         the name of the source file and the source line number of the call
00065   *         that failed. If expr is true, it returns no value.
00066   * @retval None
00067   */
00068   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00069 /* Exported functions ------------------------------------------------------- */
00070   void assert_failed(uint8_t* file, uint32_t line);
00071 #else
00072   #define assert_param(expr) ((void)0)
00073 #endif /* USE_FULL_ASSERT */
00074
00075 #endif /* __STM32F10x_CONF_H */
00076
00077 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f10x_it.c

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00001 /**
00002   ******************************************************************************
00003   * @file    TIM/Cascade_Synchro/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and peripherals
00009   *          interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026
00027 /** @addtogroup STM32F10x_StdPeriph_Examples
00028   * @{
00029   */
00030
00031 /** @addtogroup TIM_Cascade_Synchro
00032   * @{
00033   */
00034
00035 /* Private typedef -----------------------------------------------------------*/
00036 /* Private define ------------------------------------------------------------*/
00037 /* Private macro -------------------------------------------------------------*/
00038 /* Private variables ---------------------------------------------------------*/
00039 /* Private function prototypes -----------------------------------------------*/
00040 /* Private functions ---------------------------------------------------------*/
00041
00042 /******************************************************************************/
00043 /*            Cortex-M3 Processor Exceptions Handlers                         */
00044 /******************************************************************************/
00045
00046 /**
00047   * @brief  This function handles NMI exception.
00048   * @param  None
00049   * @retval None
00050   */
00051 void NMI_Handler(void)
00052 {}
00053
00054 /**
00055   * @brief  This function handles Hard Fault exception.
00056   * @param  None
00057   * @retval None
00058   */
00059 void HardFault_Handler(void)
00060 {
00061   /* Go to infinite loop when Hard Fault exception occurs */
00062   while (1)
00063   {}
00064 }
00065
00066 /**
00067   * @brief  This function handles Memory Manage exception.
00068   * @param  None
00069   * @retval None
00070   */
00071 void MemManage_Handler(void)
00072 {
00073   /* Go to infinite loop when Memory Manage exception occurs */
00074   while (1)
00075   {}
00076 }
00077
00078 /**
00079   * @brief  This function handles Bus Fault exception.
00080   * @param  None
00081   * @retval None
00082   */
00083 void BusFault_Handler(void)
00084 {
00085   /* Go to infinite loop when Bus Fault exception occurs */
00086   while (1)
00087   {}
00088 }
00089
00090 /**
00091   * @brief  This function handles Usage Fault exception.
00092   * @param  None
00093   * @retval None
00094   */
00095 void UsageFault_Handler(void)
00096 {
00097   /* Go to infinite loop when Usage Fault exception occurs */
00098   while (1)
00099   {}
00100 }
00101
00102 /**
00103   * @brief  This function handles Debug Monitor exception.
00104   * @param  None
00105   * @retval None
00106   */
00107 void DebugMon_Handler(void)
00108 {}
00109
00110 /**
00111   * @brief  This function handles SVCall exception.
00112   * @param  None
00113   * @retval None
00114   */
00115 void SVC_Handler(void)
00116 {}
00117
00118 /**
00119   * @brief  This function handles PendSV_Handler exception.
00120   * @param  None
00121   * @retval None
00122   */
00123 void PendSV_Handler(void)
00124 {}
00125
00126 /**
00127   * @brief  This function handles SysTick Handler.
00128   * @param  None
00129   * @retval None
00130   */
00131 void SysTick_Handler(void)
00132 {}
00133
00134 /******************************************************************************/
00135 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00136 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00137 /*  available peripheral interrupt handler's name please refer to the startup */
00138 /*  file (startup_stm32f10x_xx.s).                                            */
00139 /******************************************************************************/
00140
00141 /**
00142   * @brief  This function handles PPP interrupt request.
00143   * @param  None
00144   * @retval None
00145   */
00146 /*void PPP_IRQHandler(void)
00147 {
00148 }*/
00149
00150 /**
00151   * @}
00152   */
00153
00154 /**
00155   * @}
00156   */
00157
00158 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f10x_it.h

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00001 /**
00002   ******************************************************************************
00003   * @file    TIM/Cascade_Synchro/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043
00044 #endif /* __STM32F10x_IT_H */
00045
00046 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/main.c

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00001 /**
00002   ******************************************************************************
00003   * @file    TIM/ComplementarySignals/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x.h"
00024
00025 /** @addtogroup STM32F10x_StdPeriph_Examples
00026   * @{
00027   */
00028
00029 /** @addtogroup TIM_ComplementarySignals
00030   * @{
00031   */
00032
00033 /* Private typedef -----------------------------------------------------------*/
00034 /* Private define ------------------------------------------------------------*/
00035 /* Private macro -------------------------------------------------------------*/
00036 /* Private variables ---------------------------------------------------------*/
00037 TIM_TimeBaseInitTypeDef  TIM_TimeBaseStructure;
00038 TIM_OCInitTypeDef  TIM_OCInitStructure;
00039 TIM_BDTRInitTypeDef TIM_BDTRInitStructure;
00040 uint16_t TimerPeriod = 0;
00041 uint16_t Channel1Pulse = 0, Channel2Pulse = 0, Channel3Pulse = 0;
00042
00043 /* Private function prototypes -----------------------------------------------*/
00044 void RCC_Configuration(void);
00045 void GPIO_Configuration(void);
00046
00047 /* Private functions ---------------------------------------------------------*/
00048
00049 /**
00050   * @brief  Main program
00051   * @param  None
00052   * @retval None
00053   */
00054 int main(void)
00055 {
00056   /*!< At this stage the microcontroller clock setting is already configured,
00057        this is done through SystemInit() function which is called from startup
00058        file (startup_stm32f10x_xx.s) before to branch to application main.
00059        To reconfigure the default setting of SystemInit() function, refer to
00060        system_stm32f10x.c file
00061      */
00062
00063   /* System Clocks Configuration */
00064   RCC_Configuration();
00065
00066   /* GPIO Configuration */
00067   GPIO_Configuration();
00068
00069   /* -----------------------------------------------------------------------
00070   TIM1 Configuration to:
00071
00072   1/ Generate 3 complementary PWM signals with 3 different duty cycles:
00073     TIM1CLK is fixed to SystemCoreClock, the TIM1 Prescaler is equal to 0 so the
00074     TIM1 counter clock used is SystemCoreClock.
00075     * SystemCoreClock is set to 72 MHz for Low-density, Medium-density, High-density
00076     and Connectivity line devices. For Low-Density Value line and Medium-Density
00077     Value line devices, SystemCoreClock is set to 24 MHz.
00078
00079     The objective is to generate PWM signal at 17.57 KHz:
00080     - TIM1_Period = (SystemCoreClock / 17570) - 1
00081
00082     The Three Duty cycles are computed as the following description:
00083
00084     The channel 1 duty cycle is set to 50% so channel 1N is set to 50%.
00085     The channel 2 duty cycle is set to 25% so channel 2N is set to 75%.
00086     The channel 3 duty cycle is set to 12.5% so channel 3N is set to 87.5%.
00087     The Timer pulse is calculated as follows:
00088       - ChannelxPulse = DutyCycle * (TIM1_Period - 1) / 100
00089
00090   2/ Insert a dead time equal to 11/SystemCoreClock ns
00091   3/ Configure the break feature, active at High level, and using the automatic
00092      output enable feature
00093   4/ Use the Locking parameters level1.
00094   ----------------------------------------------------------------------- */
00095
00096   /* Compute the value to be set in ARR register to generate signal frequency at 17.57 Khz */
00097   TimerPeriod = (SystemCoreClock / 17570) - 1;
00098   /* Compute CCR1 value to generate a duty cycle at 50% for channel 1 */
00099   Channel1Pulse = (uint16_t) (((uint32_t) 5 * (TimerPeriod - 1)) / 10);
00100   /* Compute CCR2 value to generate a duty cycle at 25%  for channel 2 */
00101   Channel2Pulse = (uint16_t) (((uint32_t) 25 * (TimerPeriod - 1)) / 100);
00102   /* Compute CCR3 value to generate a duty cycle at 12.5%  for channel 3 */
00103   Channel3Pulse = (uint16_t) (((uint32_t) 125 * (TimerPeriod - 1)) / 1000);
00104
00105   /* Time Base configuration */
00106   TIM_TimeBaseStructure.TIM_Prescaler = 0;
00107   TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
00108   TIM_TimeBaseStructure.TIM_Period = TimerPeriod;
00109   TIM_TimeBaseStructure.TIM_ClockDivision = 0;
00110   TIM_TimeBaseStructure.TIM_RepetitionCounter = 0;
00111
00112   TIM_TimeBaseInit(TIM1, &TIM_TimeBaseStructure);
00113
00114   /* Channel 1, 2 and 3 Configuration in PWM mode */
00115   TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM2;
00116   TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
00117   TIM_OCInitStructure.TIM_OutputNState = TIM_OutputNState_Enable;
00118   TIM_OCInitStructure.TIM_Pulse = Channel1Pulse;
00119   TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_Low;
00120   TIM_OCInitStructure.TIM_OCNPolarity = TIM_OCNPolarity_Low;
00121   TIM_OCInitStructure.TIM_OCIdleState = TIM_OCIdleState_Set;
00122   TIM_OCInitStructure.TIM_OCNIdleState = TIM_OCIdleState_Reset;
00123
00124   TIM_OC1Init(TIM1, &TIM_OCInitStructure);
00125
00126   TIM_OCInitStructure.TIM_Pulse = Channel2Pulse;
00127   TIM_OC2Init(TIM1, &TIM_OCInitStructure);
00128
00129   TIM_OCInitStructure.TIM_Pulse = Channel3Pulse;
00130   TIM_OC3Init(TIM1, &TIM_OCInitStructure);
00131
00132   /* Automatic Output enable, Break, dead time and lock configuration*/
00133   TIM_BDTRInitStructure.TIM_OSSRState = TIM_OSSRState_Enable;
00134   TIM_BDTRInitStructure.TIM_OSSIState = TIM_OSSIState_Enable;
00135   TIM_BDTRInitStructure.TIM_LOCKLevel = TIM_LOCKLevel_1;
00136   TIM_BDTRInitStructure.TIM_DeadTime = 11;
00137   TIM_BDTRInitStructure.TIM_Break = TIM_Break_Enable;
00138   TIM_BDTRInitStructure.TIM_BreakPolarity = TIM_BreakPolarity_High;
00139   TIM_BDTRInitStructure.TIM_AutomaticOutput = TIM_AutomaticOutput_Enable;
00140
00141   TIM_BDTRConfig(TIM1, &TIM_BDTRInitStructure);
00142
00143   /* TIM1 counter enable */
00144   TIM_Cmd(TIM1, ENABLE);
00145
00146   /* Main Output Enable */
00147   TIM_CtrlPWMOutputs(TIM1, ENABLE);
00148
00149   while (1)
00150   {
00151   }
00152 }
00153
00154 /**
00155   * @brief  Configures the different system clocks.
00156   * @param  None
00157   * @retval None
00158   */
00159 void RCC_Configuration(void)
00160 {
00161   /* TIM1, GPIOA, GPIOB, GPIOE and AFIO clocks enable */
00162   RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM1 | RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOE|
00163                          RCC_APB2Periph_GPIOB |RCC_APB2Periph_AFIO, ENABLE);
00164 }
00165
00166 /**
00167   * @brief  Configure the TIM1 Pins.
00168   * @param  None
00169   * @retval None
00170   */
00171 void GPIO_Configuration(void)
00172 {
00173   GPIO_InitTypeDef GPIO_InitStructure;
00174
00175 #ifdef STM32F10X_CL
00176   /* GPIOE Configuration: Channel 1/1N, 2/2N, 3/3N as alternate function push-pull */
00177   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9|GPIO_Pin_11|GPIO_Pin_13|
00178                                 GPIO_Pin_8|GPIO_Pin_10|GPIO_Pin_12;
00179   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
00180   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00181
00182   GPIO_Init(GPIOE, &GPIO_InitStructure);
00183
00184   /* GPIOE Configuration: BKIN pin */
00185   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_15;
00186   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
00187   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00188
00189   GPIO_Init(GPIOE, &GPIO_InitStructure);
00190
00191   /* TIM1 Full remapping pins */
00192   GPIO_PinRemapConfig(GPIO_FullRemap_TIM1, ENABLE);
00193
00194 #else
00195   /* GPIOA Configuration: Channel 1, 2 and 3 as alternate function push-pull */
00196   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10;
00197   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
00198   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00199   GPIO_Init(GPIOA, &GPIO_InitStructure);
00200
00201   /* GPIOB Configuration: Channel 1N, 2N and 3N as alternate function push-pull */
00202   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15;
00203   GPIO_Init(GPIOB, &GPIO_InitStructure);
00204
00205   /* GPIOB Configuration: BKIN pin */
00206   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12;
00207   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
00208   GPIO_Init(GPIOB, &GPIO_InitStructure);
00209 #endif
00210 }
00211
00212 #ifdef  USE_FULL_ASSERT
00213
00214 /**
00215   * @brief  Reports the name of the source file and the source line number
00216   *         where the assert_param error has occurred.
00217   * @param  file: pointer to the source file name
00218   * @param  line: assert_param error line source number
00219   * @retval None
00220   */
00221 void assert_failed(uint8_t* file, uint32_t line)
00222 {
00223   /* User can add his own implementation to report the file name and line number,
00224      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00225
00226   while (1)
00227   {}
00228 }
00229
00230 #endif
00231
00232 /**
00233   * @}
00234   */
00235
00236 /**
00237   * @}
00238   */
00239
00240 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/stm32f10x_conf.h

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00001 /**
00002   ******************************************************************************
00003   * @file    TIM/ComplementarySignals/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052 /* Exported types ------------------------------------------------------------*/
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Uncomment the line below to expanse the "assert_param" macro in the
00055    Standard Peripheral Library drivers code */
00056 /* #define USE_FULL_ASSERT    1 */
00057
00058 /* Exported macro ------------------------------------------------------------*/
00059 #ifdef  USE_FULL_ASSERT
00060
00061 /**
00062   * @brief  The assert_param macro is used for function's parameters check.
00063   * @param  expr: If expr is false, it calls assert_failed function which reports
00064   *         the name of the source file and the source line number of the call
00065   *         that failed. If expr is true, it returns no value.
00066   * @retval None
00067   */
00068   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00069 /* Exported functions ------------------------------------------------------- */
00070   void assert_failed(uint8_t* file, uint32_t line);
00071 #else
00072   #define assert_param(expr) ((void)0)
00073 #endif /* USE_FULL_ASSERT */
00074
00075 #endif /* __STM32F10x_CONF_H */
00076
00077 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/stm32f10x_it.c

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00001 /**
00002   ******************************************************************************
00003   * @file    TIM/ComplementarySignals/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *         This file provides template for all exceptions handler and
00009   *         peripherals interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026
00027 /** @addtogroup STM32F10x_StdPeriph_Examples
00028   * @{
00029   */
00030
00031 /** @addtogroup TIM_ComplementarySignals
00032   * @{
00033   */
00034
00035 /* Private typedef -----------------------------------------------------------*/
00036 /* Private define ------------------------------------------------------------*/
00037 /* Private macro -------------------------------------------------------------*/
00038 /* Private variables ---------------------------------------------------------*/
00039 /* Private function prototypes -----------------------------------------------*/
00040 /* Private functions ---------------------------------------------------------*/
00041
00042 /******************************************************************************/
00043 /*            Cortex-M3 Processor Exceptions Handlers                         */
00044 /******************************************************************************/
00045
00046 /**
00047   * @brief  This function handles NMI exception.
00048   * @param  None
00049   * @retval None
00050   */
00051 void NMI_Handler(void)
00052 {}
00053
00054 /**
00055   * @brief  This function handles Hard Fault exception.
00056   * @param  None
00057   * @retval None
00058   */
00059 void HardFault_Handler(void)
00060 {
00061   /* Go to infinite loop when Hard Fault exception occurs */
00062   while (1)
00063   {}
00064 }
00065
00066 /**
00067   * @brief  This function handles Memory Manage exception.
00068   * @param  None
00069   * @retval None
00070   */
00071 void MemManage_Handler(void)
00072 {
00073   /* Go to infinite loop when Memory Manage exception occurs */
00074   while (1)
00075   {}
00076 }
00077
00078 /**
00079   * @brief  This function handles Bus Fault exception.
00080   * @param  None
00081   * @retval None
00082   */
00083 void BusFault_Handler(void)
00084 {
00085   /* Go to infinite loop when Bus Fault exception occurs */
00086   while (1)
00087   {}
00088 }
00089
00090 /**
00091   * @brief  This function handles Usage Fault exception.
00092   * @param  None
00093   * @retval None
00094   */
00095 void UsageFault_Handler(void)
00096 {
00097   /* Go to infinite loop when Usage Fault exception occurs */
00098   while (1)
00099   {}
00100 }
00101
00102 /**
00103   * @brief  This function handles Debug Monitor exception.
00104   * @param  None
00105   * @retval None
00106   */
00107 void DebugMon_Handler(void)
00108 {}
00109
00110 /**
00111   * @brief  This function handles SVCall exception.
00112   * @param  None
00113   * @retval None
00114   */
00115 void SVC_Handler(void)
00116 {}
00117
00118 /**
00119   * @brief  This function handles PendSV_Handler exception.
00120   * @param  None
00121   * @retval None
00122   */
00123 void PendSV_Handler(void)
00124 {}
00125
00126 /**
00127   * @brief  This function handles SysTick Handler.
00128   * @param  None
00129   * @retval None
00130   */
00131 void SysTick_Handler(void)
00132 {}
00133
00134 /******************************************************************************/
00135 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00136 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00137 /*  available peripheral interrupt handler's name please refer to the startup */
00138 /*  file (startup_stm32f10x_xx.s).                                            */
00139 /******************************************************************************/
00140
00141 /**
00142   * @brief  This function handles PPP interrupt request.
00143   * @param  None
00144   * @retval None
00145   */
00146 /*void PPP_IRQHandler(void)
00147 {
00148 }*/
00149
00150 /**
00151   * @}
00152   */
00153
00154 /**
00155   * @}
00156   */
00157
00158 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/stm32f10x_it.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    TIM/ComplementarySignals/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043
00044 #endif /* __STM32F10x_IT_H */
00045
00046 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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STM32F10x_StdPeriph_Examples/TIM/DMA/main.c

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00001 /**
00002   ******************************************************************************
00003   * @file    TIM/DMA/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x.h"
00024
00025 /** @addtogroup STM32F10x_StdPeriph_Examples
00026   * @{
00027   */
00028
00029 /** @addtogroup TIM_DMA
00030   * @{
00031   */
00032
00033 /* Private typedef -----------------------------------------------------------*/
00034 /* Private define ------------------------------------------------------------*/
00035 #define TIM1_CCR3_Address    0x40012C3C
00036
00037 /* Private macro -------------------------------------------------------------*/
00038 /* Private variables ---------------------------------------------------------*/
00039 TIM_TimeBaseInitTypeDef  TIM_TimeBaseStructure;
00040 TIM_OCInitTypeDef  TIM_OCInitStructure;
00041 uint16_t SRC_Buffer[3] = {0, 0, 0};
00042 uint16_t TimerPeriod = 0;
00043
00044 /* Private function prototypes -----------------------------------------------*/
00045 void RCC_Configuration(void);
00046 void GPIO_Configuration(void);
00047 void DMA_Configuration(void);
00048
00049 /* Private functions ---------------------------------------------------------*/
00050
00051 /**
00052   * @brief  Main program
00053   * @param  None
00054   * @retval None
00055   */
00056 int main(void)
00057 {
00058   /*!< At this stage the microcontroller clock setting is already configured,
00059        this is done through SystemInit() function which is called from startup
00060        file (startup_stm32f10x_xx.s) before to branch to application main.
00061        To reconfigure the default setting of SystemInit() function, refer to
00062        system_stm32f10x.c file
00063      */
00064
00065   /* System Clocks Configuration */
00066   RCC_Configuration();
00067
00068   /* GPIO Configuration */
00069   GPIO_Configuration();
00070
00071   /* DMA Configuration */
00072   DMA_Configuration();
00073
00074   /* TIM1 DMA Transfer example -------------------------------------------------
00075   TIM1CLK = SystemCoreClock, Prescaler = 0, TIM1 counter clock = SystemCoreClock
00076   SystemCoreClock is set to 72 MHz for Low-density, Medium-density, High-density
00077   and Connectivity line devices and to 24 MHz for Low-Density Value line and
00078   Medium-Density Value line devices.
00079
00080   The objective is to configure TIM1 channel 3 to generate complementary PWM
00081   signal with a frequency equal to 17.57 KHz:
00082      - TIM1_Period = (SystemCoreClock / 17570) - 1
00083   and a variable duty cycle that is changed by the DMA after a specific number of
00084   Update DMA request.
00085
00086   The number of this repetitive requests is defined by the TIM1 Repetition counter,
00087   each 3 Update Requests, the TIM1 Channel 3 Duty Cycle changes to the next new
00088   value defined by the SRC_Buffer .
00089   -----------------------------------------------------------------------------*/
00090   /* Compute the value to be set in ARR register to generate signal frequency at 17.57 Khz */
00091   TimerPeriod = (SystemCoreClock / 17570 ) - 1;
00092   /* Compute CCR1 value to generate a duty cycle at 50% */
00093   SRC_Buffer[0] = (uint16_t) (((uint32_t) 5 * (TimerPeriod - 1)) / 10);
00094   /* Compute CCR1 value to generate a duty cycle at 37.5% */
00095   SRC_Buffer[1] = (uint16_t) (((uint32_t) 375 * (TimerPeriod - 1)) / 1000);
00096   /* Compute CCR1 value to generate a duty cycle at 25% */
00097   SRC_Buffer[2] = (uint16_t) (((uint32_t) 25 * (TimerPeriod - 1)) / 100);
00098
00099   /* TIM1 Peripheral Configuration --------------------------------------------*/
00100   /* Time Base configuration */
00101   TIM_TimeBaseStructure.TIM_Prescaler = 0;
00102   TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
00103   TIM_TimeBaseStructure.TIM_Period = TimerPeriod;
00104   TIM_TimeBaseStructure.TIM_ClockDivision = 0;
00105   TIM_TimeBaseStructure.TIM_RepetitionCounter = 2;
00106
00107   TIM_TimeBaseInit(TIM1, &TIM_TimeBaseStructure);
00108
00109   /* Channel 3 Configuration in PWM mode */
00110   TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM2;
00111   TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
00112   TIM_OCInitStructure.TIM_OutputNState = TIM_OutputNState_Enable;
00113   TIM_OCInitStructure.TIM_Pulse = SRC_Buffer[0];
00114   TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_Low;
00115   TIM_OCInitStructure.TIM_OCNPolarity = TIM_OCNPolarity_Low;
00116   TIM_OCInitStructure.TIM_OCIdleState = TIM_OCIdleState_Set;
00117   TIM_OCInitStructure.TIM_OCNIdleState = TIM_OCIdleState_Reset;
00118
00119   TIM_OC3Init(TIM1, &TIM_OCInitStructure);
00120
00121   /* TIM1 Update DMA Request enable */
00122   TIM_DMACmd(TIM1, TIM_DMA_Update, ENABLE);
00123
00124   /* TIM1 counter enable */
00125   TIM_Cmd(TIM1, ENABLE);
00126
00127   /* Main Output Enable */
00128   TIM_CtrlPWMOutputs(TIM1, ENABLE);
00129
00130   while (1)
00131   {}
00132 }
00133
00134 /**
00135   * @brief  Configures the different system clocks.
00136   * @param  None
00137   * @retval None
00138   */
00139 void RCC_Configuration(void)
00140 {
00141   /* TIM1, GPIOA and GPIOB clock enable */
00142   RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM1 | RCC_APB2Periph_GPIOA |
00143                          RCC_APB2Periph_GPIOB, ENABLE);
00144   /* DMA clock enable */
00145   RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE);
00146 }
00147
00148 /**
00149   * @brief  Configure the TIM1 Pins.
00150   * @param  None
00151   * @retval None
00152   */
00153 void GPIO_Configuration(void)
00154 {
00155   GPIO_InitTypeDef GPIO_InitStructure;
00156
00157   /* GPIOA Configuration: Channel 3 as alternate function push-pull */
00158   GPIO_InitStructure.GPIO_Pin =  GPIO_Pin_10;
00159   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
00160   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00161   GPIO_Init(GPIOA, &GPIO_InitStructure);
00162
00163   /* GPIOB Configuration: Channel 3N as alternate function push-pull */
00164   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_15;
00165   GPIO_Init(GPIOB, &GPIO_InitStructure);
00166 }
00167
00168 /**
00169   * @brief  Configures the DMA.
00170   * @param  None
00171   * @retval None
00172   */
00173 void DMA_Configuration(void)
00174 {
00175   DMA_InitTypeDef DMA_InitStructure;
00176
00177   /* DMA1 Channel5 Config */
00178   DMA_DeInit(DMA1_Channel5);
00179
00180   DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)TIM1_CCR3_Address;
00181   DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)SRC_Buffer;
00182   DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
00183   DMA_InitStructure.DMA_BufferSize = 3;
00184   DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
00185   DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
00186   DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord;
00187   DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
00188   DMA_InitStructure.DMA_Mode = DMA_Mode_Circular;
00189   DMA_InitStructure.DMA_Priority = DMA_Priority_High;
00190   DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
00191
00192   DMA_Init(DMA1_Channel5, &DMA_InitStructure);
00193
00194   /* DMA1 Channel5 enable */
00195   DMA_Cmd(DMA1_Channel5, ENABLE);
00196 }
00197
00198 #ifdef  USE_FULL_ASSERT
00199
00200 /**
00201   * @brief  Reports the name of the source file and the source line number
00202   *         where the assert_param error has occurred.
00203   * @param  file: pointer to the source file name
00204   * @param  line: assert_param error line source number
00205   * @retval None
00206   */
00207 void assert_failed(uint8_t* file, uint32_t line)
00208 {
00209   /* User can add his own implementation to report the file name and line number,
00210      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00211
00212   while (1)
00213   {}
00214 }
00215
00216 #endif
00217
00218 /**
00219   * @}
00220   */
00221
00222 /**
00223   * @}
00224   */
00225
00226 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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STM32F10x_StdPeriph_Examples/TIM/DMA/stm32f10x_conf.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    TIM/DMA/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052 /* Exported types ------------------------------------------------------------*/
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Uncomment the line below to expanse the "assert_param" macro in the
00055    Standard Peripheral Library drivers code */
00056 /* #define USE_FULL_ASSERT    1 */
00057
00058 /* Exported macro ------------------------------------------------------------*/
00059 #ifdef  USE_FULL_ASSERT
00060
00061 /**
00062   * @brief  The assert_param macro is used for function's parameters check.
00063   * @param  expr: If expr is false, it calls assert_failed function which reports
00064   *         the name of the source file and the source line number of the call
00065   *         that failed. If expr is true, it returns no value.
00066   * @retval None
00067   */
00068   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00069 /* Exported functions ------------------------------------------------------- */
00070   void assert_failed(uint8_t* file, uint32_t line);
00071 #else
00072   #define assert_param(expr) ((void)0)
00073 #endif /* USE_FULL_ASSERT */
00074
00075 #endif /* __STM32F10x_CONF_H */
00076
00077 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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STM32F10x_StdPeriph_Examples/TIM/DMA/stm32f10x_it.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    TIM/DMA/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and peripherals
00009   *          interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026
00027 /** @addtogroup STM32F10x_StdPeriph_Examples
00028   * @{
00029   */
00030
00031 /** @addtogroup TIM_DMA
00032   * @{
00033   */
00034
00035 /* Private typedef -----------------------------------------------------------*/
00036 /* Private define ------------------------------------------------------------*/
00037 /* Private macro -------------------------------------------------------------*/
00038 /* Private variables ---------------------------------------------------------*/
00039 /* Private function prototypes -----------------------------------------------*/
00040 /* Private functions ---------------------------------------------------------*/
00041
00042 /******************************************************************************/
00043 /*            Cortex-M3 Processor Exceptions Handlers                         */
00044 /******************************************************************************/
00045
00046 /**
00047   * @brief  This function handles NMI exception.
00048   * @param  None
00049   * @retval None
00050   */
00051 void NMI_Handler(void)
00052 {
00053 }
00054
00055 /**
00056   * @brief  This function handles Hard Fault exception.
00057   * @param  None
00058   * @retval None
00059   */
00060 void HardFault_Handler(void)
00061 {
00062   /* Go to infinite loop when Hard Fault exception occurs */
00063   while (1)
00064   {}
00065 }
00066
00067 /**
00068   * @brief  This function handles Memory Manage exception.
00069   * @param  None
00070   * @retval None
00071   */
00072 void MemManage_Handler(void)
00073 {
00074   /* Go to infinite loop when Memory Manage exception occurs */
00075   while (1)
00076   {}
00077 }
00078
00079 /**
00080   * @brief  This function handles Bus Fault exception.
00081   * @param  None
00082   * @retval None
00083   */
00084 void BusFault_Handler(void)
00085 {
00086   /* Go to infinite loop when Bus Fault exception occurs */
00087   while (1)
00088   {}
00089 }
00090
00091 /**
00092   * @brief  This function handles Usage Fault exception.
00093   * @param  None
00094   * @retval None
00095   */
00096 void UsageFault_Handler(void)
00097 {
00098   /* Go to infinite loop when Usage Fault exception occurs */
00099   while (1)
00100   {}
00101 }
00102
00103 /**
00104   * @brief  This function handles Debug Monitor exception.
00105   * @param  None
00106   * @retval None
00107   */
00108 void DebugMon_Handler(void)
00109 {}
00110
00111 /**
00112   * @brief  This function handles SVCall exception.
00113   * @param  None
00114   * @retval None
00115   */
00116 void SVC_Handler(void)
00117 {}
00118
00119 /**
00120   * @brief  This function handles PendSV_Handler exception.
00121   * @param  None
00122   * @retval None
00123   */
00124 void PendSV_Handler(void)
00125 {}
00126
00127 /**
00128   * @brief  This function handles SysTick Handler.
00129   * @param  None
00130   * @retval None
00131   */
00132 void SysTick_Handler(void)
00133 {}
00134
00135 /******************************************************************************/
00136 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00137 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00138 /*  available peripheral interrupt handler's name please refer to the startup */
00139 /*  file (startup_stm32f10x_xx.s).                                            */
00140 /******************************************************************************/
00141
00142 /**
00143   * @brief  This function handles PPP interrupt request.
00144   * @param  None
00145   * @retval None
00146   */
00147 /*void PPP_IRQHandler(void)
00148 {
00149 }*/
00150
00151 /**
00152   * @}
00153   */
00154
00155 /**
00156   * @}
00157   */
00158
00159 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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STM32F10x_StdPeriph_Examples/TIM/DMA/stm32f10x_it.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    TIM/DMA/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043
00044 #endif /* __STM32F10x_IT_H */
00045
00046 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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STM32F10x_StdPeriph_Examples/TIM/DMABurst/main.c

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00001 /**
00002   ******************************************************************************
00003   * @file    TIM/DMABurst/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x.h"
00024
00025 /** @addtogroup STM32F10x_StdPeriph_Examples
00026   * @{
00027   */
00028
00029 /** @addtogroup TIM_DMABurst
00030   * @{
00031   */
00032
00033 /* Private typedef -----------------------------------------------------------*/
00034 /* Private define ------------------------------------------------------------*/
00035 #define TIM1_DMAR_ADDRESS ((uint32_t)0x40012C4C) /* TIM ARR (Auto Reload Register) address */
00036
00037 /* Private macro -------------------------------------------------------------*/
00038 /* Private variables ---------------------------------------------------------*/
00039 GPIO_InitTypeDef         GPIO_InitStructure;
00040 DMA_InitTypeDef          DMA_InitStructure;
00041 TIM_TimeBaseInitTypeDef  TIM_TimeBaseStructure;
00042 TIM_OCInitTypeDef        TIM_OCInitStructure;
00043 uint16_t SRC_Buffer[6] = {0x0FFF, 0x0000, 0x0555};
00044
00045 /* Private function prototypes -----------------------------------------------*/
00046 /* Private functions ---------------------------------------------------------*/
00047
00048 /**
00049   * @brief  Main program
00050   * @param  None
00051   * @retval None
00052   */
00053 int main(void)
00054 {
00055   /*!< At this stage the microcontroller clock setting is already configured,
00056        this is done through SystemInit() function which is called from startup
00057        file (startup_stm32f10x_xx.s) before to branch to application main.
00058        To reconfigure the default setting of SystemInit() function, refer to
00059        system_stm32f10x.c file
00060      */
00061
00062   /* TIM1 and GPIOA clock enable */
00063   RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM1 | RCC_APB2Periph_GPIOA, ENABLE);
00064
00065   /* DMA clock enable */
00066   RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE);
00067
00068   /* GPIOA Configuration: Channel 1 as alternate function push-pull */
00069   GPIO_InitStructure.GPIO_Pin =  GPIO_Pin_8;
00070   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
00071   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00072   GPIO_Init(GPIOA, &GPIO_InitStructure);
00073
00074   /* TIM1 DeInit */
00075   TIM_DeInit(TIM1);
00076
00077   /* DMA1 Channel5 Config */
00078   DMA_DeInit(DMA1_Channel5);
00079
00080   DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)TIM1_DMAR_ADDRESS;
00081   DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)SRC_Buffer;
00082   DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
00083   DMA_InitStructure.DMA_BufferSize = 3;
00084   DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
00085   DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
00086   DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord;
00087   DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
00088   DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
00089   DMA_InitStructure.DMA_Priority = DMA_Priority_High;
00090   DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
00091   DMA_Init(DMA1_Channel5, &DMA_InitStructure);
00092
00093   /* Time base configuration */
00094   /* -----------------------------------------------------------------------
00095     TIM1 Configuration: generate 1 PWM signal using the DMA burst mode:
00096     The TIM1CLK frequency is set to SystemCoreClock (Hz), to get TIM1 counter
00097     clock at 24 MHz the Prescaler is computed as following:
00098      - Prescaler = (TIM1CLK / TIM1 counter clock) - 1
00099     SystemCoreClock is set to 72 MHz for Low-density, Medium-density, High-density
00100     and Connectivity line devices and to 24 MHz for Low-Density Value line and
00101     Medium-Density Value line devices
00102
00103     The TIM1 period is 5.8 KHz: TIM1 Frequency = TIM1 counter clock/(ARR + 1)
00104                                                = 24 MHz / 4096 = 5.8KHz KHz
00105     TIM1 Channel1 duty cycle = (TIM1_CCR1/ TIM1_ARR)* 100 = 33.33%
00106   ----------------------------------------------------------------------- */
00107   TIM_TimeBaseStructure.TIM_Period = 0xFFFF;
00108   TIM_TimeBaseStructure.TIM_Prescaler = (uint16_t) (SystemCoreClock / 24000000) - 1;
00109   TIM_TimeBaseStructure.TIM_ClockDivision = 0x0;
00110   TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
00111   TIM_TimeBaseInit(TIM1, &TIM_TimeBaseStructure);
00112
00113   /* TIM Configuration in PWM Mode */
00114   TIM_OCInitStructure.TIM_OCMode =  TIM_OCMode_PWM1;
00115   TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
00116   TIM_OCInitStructure.TIM_Pulse = 0xFFF;
00117   TIM_OC1Init(TIM1, &TIM_OCInitStructure);
00118
00119   /* TIM1 DMAR Base register and DMA Burst Length Config */
00120   TIM_DMAConfig(TIM1, TIM_DMABase_ARR, TIM_DMABurstLength_3Transfers);
00121
00122   /* TIM1 DMA Update enable */
00123   TIM_DMACmd(TIM1, TIM_DMA_Update, ENABLE);
00124
00125   /* TIM1 enable */
00126   TIM_Cmd(TIM1, ENABLE);
00127
00128   /* TIM1 PWM Outputs Enable */
00129   TIM_CtrlPWMOutputs(TIM1, ENABLE);
00130
00131   /* DMA1 Channel5 enable */
00132   DMA_Cmd(DMA1_Channel5, ENABLE);
00133
00134   /* Wait until DMA1 Channel5 end of Transfer */
00135   while (!DMA_GetFlagStatus(DMA1_FLAG_TC5))
00136   {
00137   }
00138
00139   /* Infinite loop */
00140   while(1)
00141   {
00142   }
00143 }
00144
00145
00146 #ifdef  USE_FULL_ASSERT
00147
00148 /**
00149   * @brief  Reports the name of the source file and the source line number
00150   *         where the assert_param error has occurred.
00151   * @param  file: pointer to the source file name
00152   * @param  line: assert_param error line source number
00153   * @retval None
00154   */
00155 void assert_failed(uint8_t* file, uint32_t line)
00156 {
00157   /* User can add his own implementation to report the file name and line number,
00158      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00159
00160   while (1)
00161   {}
00162 }
00163 #endif
00164
00165 /**
00166   * @}
00167   */
00168
00169 /**
00170   * @}
00171   */
00172
00173 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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STM32F10x_StdPeriph_Examples/TIM/DMABurst/stm32f10x_conf.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    TIM/DMABurst/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052 /* Exported types ------------------------------------------------------------*/
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Uncomment the line below to expanse the "assert_param" macro in the
00055    Standard Peripheral Library drivers code */
00056 /* #define USE_FULL_ASSERT    1 */
00057
00058 /* Exported macro ------------------------------------------------------------*/
00059 #ifdef  USE_FULL_ASSERT
00060
00061 /**
00062   * @brief  The assert_param macro is used for function's parameters check.
00063   * @param  expr: If expr is false, it calls assert_failed function which reports
00064   *         the name of the source file and the source line number of the call
00065   *         that failed. If expr is true, it returns no value.
00066   * @retval None
00067   */
00068   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00069 /* Exported functions ------------------------------------------------------- */
00070   void assert_failed(uint8_t* file, uint32_t line);
00071 #else
00072   #define assert_param(expr) ((void)0)
00073 #endif /* USE_FULL_ASSERT */
00074
00075 #endif /* __STM32F10x_CONF_H */
00076
00077 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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STM32F10x_StdPeriph_Examples/TIM/DMABurst/stm32f10x_it.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    TIM/DMABurst/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and peripherals
00009   *          interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026
00027 /** @addtogroup STM32F10x_StdPeriph_Examples
00028   * @{
00029   */
00030
00031 /** @addtogroup TIM_DMABurst
00032   * @{
00033   */
00034
00035 /* Private typedef -----------------------------------------------------------*/
00036 /* Private define ------------------------------------------------------------*/
00037 /* Private macro -------------------------------------------------------------*/
00038 /* Private variables ---------------------------------------------------------*/
00039 /* Private function prototypes -----------------------------------------------*/
00040 /* Private functions ---------------------------------------------------------*/
00041
00042 /******************************************************************************/
00043 /*            Cortex-M3 Processor Exceptions Handlers                         */
00044 /******************************************************************************/
00045
00046 /**
00047   * @brief  This function handles NMI exception.
00048   * @param  None
00049   * @retval None
00050   */
00051 void NMI_Handler(void)
00052 {
00053 }
00054
00055 /**
00056   * @brief  This function handles Hard Fault exception.
00057   * @param  None
00058   * @retval None
00059   */
00060 void HardFault_Handler(void)
00061 {
00062   /* Go to infinite loop when Hard Fault exception occurs */
00063   while (1)
00064   {
00065   }
00066 }
00067
00068 /**
00069   * @brief  This function handles Memory Manage exception.
00070   * @param  None
00071   * @retval None
00072   */
00073 void MemManage_Handler(void)
00074 {
00075   /* Go to infinite loop when Memory Manage exception occurs */
00076   while (1)
00077   {
00078   }
00079 }
00080
00081 /**
00082   * @brief  This function handles Bus Fault exception.
00083   * @param  None
00084   * @retval None
00085   */
00086 void BusFault_Handler(void)
00087 {
00088   /* Go to infinite loop when Bus Fault exception occurs */
00089   while (1)
00090   {
00091   }
00092 }
00093
00094 /**
00095   * @brief  This function handles Usage Fault exception.
00096   * @param  None
00097   * @retval None
00098   */
00099 void UsageFault_Handler(void)
00100 {
00101   /* Go to infinite loop when Usage Fault exception occurs */
00102   while (1)
00103   {
00104   }
00105 }
00106
00107 /**
00108   * @brief  This function handles SVCall exception.
00109   * @param  None
00110   * @retval None
00111   */
00112 void SVC_Handler(void)
00113 {
00114 }
00115
00116 /**
00117   * @brief  This function handles Debug Monitor exception.
00118   * @param  None
00119   * @retval None
00120   */
00121 void DebugMon_Handler(void)
00122 {
00123 }
00124
00125 /**
00126   * @brief  This function handles PendSV_Handler exception.
00127   * @param  None
00128   * @retval None
00129   */
00130 void PendSV_Handler(void)
00131 {
00132 }
00133
00134 /**
00135   * @brief  This function handles SysTick Handler.
00136   * @param  None
00137   * @retval None
00138   */
00139 void SysTick_Handler(void)
00140 {
00141 }
00142
00143 /******************************************************************************/
00144 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00145 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00146 /*  available peripheral interrupt handler's name please refer to the startup */
00147 /*  file (startup_stm32f10x_xx.s).                                            */
00148 /******************************************************************************/
00149
00150 /**
00151   * @brief  This function handles PPP interrupt request.
00152   * @param  None
00153   * @retval None
00154   */
00155 /*void PPP_IRQHandler(void)
00156 {
00157 }*/
00158
00159 /**
00160   * @}
00161   */
00162
00163 /**
00164   * @}
00165   */
00166
00167 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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  • TIM
  • DMABurst

STM32F10x_StdPeriph_Examples/TIM/DMABurst/stm32f10x_it.h

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00001 /**
00002   ******************************************************************************
00003   * @file    TIM/DMABurst/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043
00044 #endif /* __STM32F10x_IT_H */
00045
00046 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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  • ExtTrigger_Synchro

STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/main.c

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00001 /**
00002   ******************************************************************************
00003   * @file    TIM/ExtTrigger_Synchro/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x.h"
00024
00025 /** @addtogroup STM32F10x_StdPeriph_Examples
00026   * @{
00027   */
00028
00029 /** @addtogroup TIM_ExtTrigger_Synchro
00030   * @{
00031   */
00032
00033 /* Private typedef -----------------------------------------------------------*/
00034 /* Private define ------------------------------------------------------------*/
00035 /* Private macro -------------------------------------------------------------*/
00036 /* Private variables ---------------------------------------------------------*/
00037 TIM_TimeBaseInitTypeDef  TIM_TimeBaseStructure;
00038 TIM_ICInitTypeDef  TIM_ICInitStructure;
00039 TIM_OCInitTypeDef  TIM_OCInitStructure;
00040
00041 /* Private function prototypes -----------------------------------------------*/
00042 void RCC_Configuration(void);
00043 void GPIO_Configuration(void);
00044
00045 /* Private functions ---------------------------------------------------------*/
00046
00047 /**
00048   * @brief   Main program
00049   * @param  None
00050   * @retval None
00051   */
00052 int main(void)
00053 {
00054   /*!< At this stage the microcontroller clock setting is already configured,
00055        this is done through SystemInit() function which is called from startup
00056        file (startup_stm32f10x_xx.s) before to branch to application main.
00057        To reconfigure the default setting of SystemInit() function, refer to
00058        system_stm32f10x.c file
00059      */
00060
00061   /* System Clocks Configuration */
00062   RCC_Configuration();
00063
00064   /* Configure the GPIO ports */
00065   GPIO_Configuration();
00066
00067   /* Timers synchronisation in cascade mode with an external trigger -----
00068     1/TIM1 is configured as Master Timer:
00069      - Toggle Mode is used
00070      - The TIM1 Enable event is used as Trigger Output
00071
00072     2/TIM1 is configured as Slave Timer for an external Trigger connected
00073      to TIM1 TI2 pin (TIM1 CH2 configured as input pin):
00074      - The TIM1 TI2FP2 is used as Trigger Input
00075      - Rising edge is used to start and stop the TIM1: Gated Mode.
00076
00077     3/TIM3 is slave for TIM1 and Master for TIM4,
00078      - Toggle Mode is used
00079      - The ITR1(TIM1) is used as input trigger
00080      - Gated mode is used, so start and stop of slave counter
00081        are controlled by the Master trigger output signal(TIM1 enable event).
00082      - The TIM3 enable event is used as Trigger Output.
00083
00084     4/TIM4 is slave for TIM3,
00085      - Toggle Mode is used
00086      - The ITR2(TIM3) is used as input trigger
00087      - Gated mode is used, so start and stop of slave counter
00088        are controlled by the Master trigger output signal(TIM3 enable event).
00089
00090     * For Low-density, Medium-density, High-density and Connectivity line devices:
00091       The TIMxCLK is fixed to 72 MHZ, the Prescaler is equal to 2 so the TIMx clock
00092       counter is equal to 24 MHz.
00093       The Three Timers are running at:
00094       TIMx frequency = TIMx clock counter/ 2*(TIMx_Period + 1) = 162.1 KHz.
00095
00096     * For Low-Density Value line and Medium-Density Value line devices:
00097       The TIMxCLK is fixed to 24 MHz, the Prescaler is equal to 2 so the TIMx clock
00098       counter is equal to 8 MHz.
00099       TIMx frequency = TIMx clock counter/ 2*(TIMx_Period + 1) = 54 KHz.
00100
00101     The starts and stops of the TIM1 counters are controlled by the
00102     external trigger.
00103     The TIM3 starts and stops are controlled by the TIM1, and the TIM4
00104     starts and stops are controlled by the TIM3.
00105   -------------------------------------------------------------------- */
00106
00107   /* Time base configuration */
00108   TIM_TimeBaseStructure.TIM_Period = 73;
00109   TIM_TimeBaseStructure.TIM_Prescaler = 2;
00110   TIM_TimeBaseStructure.TIM_ClockDivision = 0;
00111   TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
00112
00113   TIM_TimeBaseInit(TIM1, &TIM_TimeBaseStructure);
00114
00115   TIM_TimeBaseStructure.TIM_Period = 73;
00116   TIM_TimeBaseInit(TIM3, &TIM_TimeBaseStructure);
00117
00118   TIM_TimeBaseStructure.TIM_Period = 73;
00119   TIM_TimeBaseInit(TIM4, &TIM_TimeBaseStructure);
00120
00121   /* Master Configuration in Toggle Mode */
00122   TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_Toggle;
00123   TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
00124   TIM_OCInitStructure.TIM_Pulse = 64;
00125   TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High;
00126
00127   TIM_OC1Init(TIM1, &TIM_OCInitStructure);
00128
00129   /* TIM1 Input Capture Configuration */
00130   TIM_ICInitStructure.TIM_Channel = TIM_Channel_2;
00131   TIM_ICInitStructure.TIM_ICPolarity = TIM_ICPolarity_Rising;
00132   TIM_ICInitStructure.TIM_ICSelection = TIM_ICSelection_DirectTI;
00133   TIM_ICInitStructure.TIM_ICPrescaler = TIM_ICPSC_DIV1;
00134   TIM_ICInitStructure.TIM_ICFilter = 0;
00135
00136   TIM_ICInit(TIM1, &TIM_ICInitStructure);
00137
00138   /* TIM1 Input trigger configuration: External Trigger connected to TI2 */
00139   TIM_SelectInputTrigger(TIM1, TIM_TS_TI2FP2);
00140   TIM_SelectSlaveMode(TIM1, TIM_SlaveMode_Gated);
00141
00142   /* Select the Master Slave Mode */
00143   TIM_SelectMasterSlaveMode(TIM1, TIM_MasterSlaveMode_Enable);
00144
00145   /* Master Mode selection: TIM1 */
00146   TIM_SelectOutputTrigger(TIM1, TIM_TRGOSource_Enable);
00147
00148   /* Slaves Configuration: Toggle Mode */
00149   TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_Toggle;
00150   TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
00151
00152   TIM_OC1Init(TIM3, &TIM_OCInitStructure);
00153
00154   TIM_OC1Init(TIM4, &TIM_OCInitStructure);
00155
00156   /* Slave Mode selection: TIM3 */
00157   TIM_SelectInputTrigger(TIM3, TIM_TS_ITR0);
00158   TIM_SelectSlaveMode(TIM3, TIM_SlaveMode_Gated);
00159
00160   /* Select the Master Slave Mode */
00161   TIM_SelectMasterSlaveMode(TIM3, TIM_MasterSlaveMode_Enable);
00162
00163   /* Master Mode selection: TIM3 */
00164   TIM_SelectOutputTrigger(TIM3, TIM_TRGOSource_Enable);
00165
00166   /* Slave Mode selection: TIM4 */
00167   TIM_SelectInputTrigger(TIM4, TIM_TS_ITR2);
00168   TIM_SelectSlaveMode(TIM4, TIM_SlaveMode_Gated);
00169
00170   /* TIM1 Main Output Enable */
00171   TIM_CtrlPWMOutputs(TIM1, ENABLE);
00172
00173   /* TIM enable counter */
00174   TIM_Cmd(TIM1, ENABLE);
00175   TIM_Cmd(TIM3, ENABLE);
00176   TIM_Cmd(TIM4, ENABLE);
00177
00178   while (1)
00179   {}
00180 }
00181
00182 /**
00183   * @brief  Configures the different system clocks.
00184   * @param  None
00185   * @retval None
00186   */
00187 void RCC_Configuration(void)
00188 {
00189   /* TIM1, TIM3 and TIM4 clock enable */
00190   RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM3 |
00191                          RCC_APB1Periph_TIM4, ENABLE);
00192
00193   /* TIM1, GPIOA, GPIOE, GPIOC and GPIOB clocks enable */
00194   RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM1 | RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB |
00195                          RCC_APB2Periph_GPIOE | RCC_APB2Periph_GPIOC | RCC_APB2Periph_AFIO, ENABLE);
00196 }
00197
00198 /**
00199   * @brief  Configure the GPIO Pins.
00200   * @param  None
00201   * @retval None
00202   */
00203 void GPIO_Configuration(void)
00204 {
00205   GPIO_InitTypeDef GPIO_InitStructure;
00206 #ifdef STM32F10X_CL
00207   /* GPIOE Configuration: Channel 1 as alternate function push-pull */
00208   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;
00209   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
00210   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00211
00212   GPIO_Init(GPIOE, &GPIO_InitStructure);
00213
00214    /* GPIOE Configuration: Channel 2 as Input floating */
00215   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11;
00216   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
00217
00218   GPIO_Init(GPIOE, &GPIO_InitStructure);
00219
00220   /* TIM1 Full remapping pins */
00221   GPIO_PinRemapConfig(GPIO_FullRemap_TIM1, ENABLE);
00222
00223  /*GPIOB Configuration: TIM3 channel1, 2, 3 and 4 */
00224   GPIO_InitStructure.GPIO_Pin =  GPIO_Pin_6;
00225   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
00226   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00227
00228   GPIO_Init(GPIOC, &GPIO_InitStructure);
00229
00230   GPIO_PinRemapConfig(GPIO_FullRemap_TIM3, ENABLE);
00231
00232   /* GPIOB Configuration: PB.06(TIM4 CH1) as alternate function push-pull */
00233   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
00234
00235   GPIO_Init(GPIOB, &GPIO_InitStructure);
00236
00237 #else
00238   /* GPIOA Configuration: PA.08(TIM1 CH1) and PA.06(TIM3 CH1) as alternate function push-pull */
00239   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8 | GPIO_Pin_6;
00240   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
00241   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00242
00243   GPIO_Init(GPIOA, &GPIO_InitStructure);
00244
00245   /* GPIOB Configuration: PB.06(TIM4 CH1) as alternate function push-pull */
00246   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
00247
00248   GPIO_Init(GPIOB, &GPIO_InitStructure);
00249
00250   /* GPIOA Configuration: PA.09(TIM1 CH2) */
00251   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;
00252   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
00253
00254   GPIO_Init(GPIOA, &GPIO_InitStructure);
00255
00256 #endif
00257
00258 }
00259
00260 #ifdef  USE_FULL_ASSERT
00261
00262 /**
00263   * @brief  Reports the name of the source file and the source line number
00264   *         where the assert_param error has occurred.
00265   * @param  file: pointer to the source file name
00266   * @param  line: assert_param error line source number
00267   * @retval None
00268   */
00269 void assert_failed(uint8_t* file, uint32_t line)
00270 {
00271   /* User can add his own implementation to report the file name and line number,
00272      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00273
00274   while (1)
00275   {}
00276 }
00277
00278 #endif
00279
00280 /**
00281   * @}
00282   */
00283
00284 /**
00285   * @}
00286   */
00287
00288 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/stm32f10x_conf.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    TIM/ExtTrigger_Synchro/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052 /* Exported types ------------------------------------------------------------*/
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Uncomment the line below to expanse the "assert_param" macro in the
00055    Standard Peripheral Library drivers code */
00056 /* #define USE_FULL_ASSERT    1 */
00057
00058 /* Exported macro ------------------------------------------------------------*/
00059 #ifdef  USE_FULL_ASSERT
00060
00061 /**
00062   * @brief  The assert_param macro is used for function's parameters check.
00063   * @param  expr: If expr is false, it calls assert_failed function which reports
00064   *         the name of the source file and the source line number of the call
00065   *         that failed. If expr is true, it returns no value.
00066   * @retval None
00067   */
00068   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00069 /* Exported functions ------------------------------------------------------- */
00070   void assert_failed(uint8_t* file, uint32_t line);
00071 #else
00072   #define assert_param(expr) ((void)0)
00073 #endif /* USE_FULL_ASSERT */
00074
00075 #endif /* __STM32F10x_CONF_H */
00076
00077 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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  • ExtTrigger_Synchro

STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/stm32f10x_it.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    TIM/ExtTrigger_Synchro/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *        This file provides template for all exceptions handler and
00009   *        peripherals interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026
00027 /** @addtogroup STM32F10x_StdPeriph_Examples
00028   * @{
00029   */
00030
00031 /** @addtogroup TIM_ExtTrigger_Synchro
00032   * @{
00033   */
00034
00035 /* Private typedef -----------------------------------------------------------*/
00036 /* Private define ------------------------------------------------------------*/
00037 /* Private macro -------------------------------------------------------------*/
00038 /* Private variables ---------------------------------------------------------*/
00039 /* Private function prototypes -----------------------------------------------*/
00040 /* Private functions ---------------------------------------------------------*/
00041
00042 /******************************************************************************/
00043 /*            Cortex-M3 Processor Exceptions Handlers                         */
00044 /******************************************************************************/
00045
00046 /**
00047   * @brief  This function handles NMI exception.
00048   * @param  None
00049   * @retval None
00050   */
00051 void NMI_Handler(void)
00052 {
00053 }
00054
00055 /**
00056   * @brief  This function handles Hard Fault exception.
00057   * @param  None
00058   * @retval None
00059   */
00060 void HardFault_Handler(void)
00061 {
00062   /* Go to infinite loop when Hard Fault exception occurs */
00063   while (1)
00064   {}
00065 }
00066
00067 /**
00068   * @brief  This function handles Memory Manage exception.
00069   * @param  None
00070   * @retval None
00071   */
00072 void MemManage_Handler(void)
00073 {
00074   /* Go to infinite loop when Memory Manage exception occurs */
00075   while (1)
00076   {}
00077 }
00078
00079 /**
00080   * @brief  This function handles Bus Fault exception.
00081   * @param  None
00082   * @retval None
00083   */
00084 void BusFault_Handler(void)
00085 {
00086   /* Go to infinite loop when Bus Fault exception occurs */
00087   while (1)
00088   {}
00089 }
00090
00091 /**
00092   * @brief  This function handles Usage Fault exception.
00093   * @param  None
00094   * @retval None
00095   */
00096 void UsageFault_Handler(void)
00097 {
00098   /* Go to infinite loop when Usage Fault exception occurs */
00099   while (1)
00100   {}
00101 }
00102
00103 /**
00104   * @brief  This function handles Debug Monitor exception.
00105   * @param  None
00106   * @retval None
00107   */
00108 void DebugMon_Handler(void)
00109 {}
00110
00111 /**
00112   * @brief  This function handles SVCall exception.
00113   * @param  None
00114   * @retval None
00115   */
00116 void SVC_Handler(void)
00117 {}
00118
00119 /**
00120   * @brief  This function handles PendSV_Handler exception.
00121   * @param  None
00122   * @retval None
00123   */
00124 void PendSV_Handler(void)
00125 {}
00126
00127 /**
00128   * @brief  This function handles SysTick Handler.
00129   * @param  None
00130   * @retval None
00131   */
00132 void SysTick_Handler(void)
00133 {}
00134
00135 /******************************************************************************/
00136 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00137 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00138 /*  available peripheral interrupt handler's name please refer to the startup */
00139 /*  file (startup_stm32f10x_xx.s).                                            */
00140 /******************************************************************************/
00141
00142 /**
00143   * @brief  This function handles PPP interrupt request.
00144   * @param  None
00145   * @retval None
00146   */
00147 /*void TPPP_IRQHandler(void)
00148 {
00149 }*/
00150
00151 /**
00152   * @}
00153   */
00154
00155 /**
00156   * @}
00157   */
00158
00159 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/stm32f10x_it.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    TIM/ExtTrigger_Synchro/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043
00044 #endif /* __STM32F10x_IT_H */
00045
00046 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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STM32F10x_StdPeriph_Examples/TIM/InputCapture/main.c

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00001 /**
00002   ******************************************************************************
00003   * @file    TIM/InputCapture/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x.h"
00024
00025 /** @addtogroup STM32F10x_StdPeriph_Examples
00026   * @{
00027   */
00028
00029 /** @addtogroup TIM_Input_Capture
00030   * @{
00031   */
00032
00033 /* Private typedef -----------------------------------------------------------*/
00034 /* Private define ------------------------------------------------------------*/
00035 /* Private macro -------------------------------------------------------------*/
00036 /* Private variables ---------------------------------------------------------*/
00037 TIM_ICInitTypeDef  TIM_ICInitStructure;
00038
00039 /* Private function prototypes -----------------------------------------------*/
00040 void RCC_Configuration(void);
00041 void GPIO_Configuration(void);
00042 void NVIC_Configuration(void);
00043
00044 /* Private functions ---------------------------------------------------------*/
00045
00046 /**
00047   * @brief  Main program
00048   * @param  None
00049   * @retval None
00050   */
00051 int main(void)
00052 {
00053   /*!< At this stage the microcontroller clock setting is already configured,
00054        this is done through SystemInit() function which is called from startup
00055        file (startup_stm32f10x_xx.s) before to branch to application main.
00056        To reconfigure the default setting of SystemInit() function, refer to
00057        system_stm32f10x.c file
00058      */
00059
00060   /* System Clocks Configuration */
00061   RCC_Configuration();
00062
00063   /* NVIC configuration */
00064   NVIC_Configuration();
00065
00066   /* Configure the GPIO ports */
00067   GPIO_Configuration();
00068
00069   /* TIM3 configuration: Input Capture mode ---------------------
00070      The external signal is connected to TIM3 CH2 pin (PA.07)
00071      The Rising edge is used as active edge,
00072      The TIM3 CCR2 is used to compute the frequency value
00073   ------------------------------------------------------------ */
00074
00075   TIM_ICInitStructure.TIM_Channel = TIM_Channel_2;
00076   TIM_ICInitStructure.TIM_ICPolarity = TIM_ICPolarity_Rising;
00077   TIM_ICInitStructure.TIM_ICSelection = TIM_ICSelection_DirectTI;
00078   TIM_ICInitStructure.TIM_ICPrescaler = TIM_ICPSC_DIV1;
00079   TIM_ICInitStructure.TIM_ICFilter = 0x0;
00080
00081   TIM_ICInit(TIM3, &TIM_ICInitStructure);
00082
00083   /* TIM enable counter */
00084   TIM_Cmd(TIM3, ENABLE);
00085
00086   /* Enable the CC2 Interrupt Request */
00087   TIM_ITConfig(TIM3, TIM_IT_CC2, ENABLE);
00088
00089   while (1);
00090 }
00091
00092 /**
00093   * @brief  Configures the different system clocks.
00094   * @param  None
00095   * @retval None
00096   */
00097 void RCC_Configuration(void)
00098 {
00099   /* TIM3 clock enable */
00100   RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM3, ENABLE);
00101
00102   /* GPIOA and GPIOB clock enable */
00103   RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);
00104 }
00105
00106 /**
00107   * @brief  Configure the GPIOD Pins.
00108   * @param  None
00109   * @retval None
00110   */
00111 void GPIO_Configuration(void)
00112 {
00113   GPIO_InitTypeDef GPIO_InitStructure;
00114
00115   /* TIM3 channel 2 pin (PA.07) configuration */
00116   GPIO_InitStructure.GPIO_Pin =  GPIO_Pin_7;
00117   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
00118   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00119
00120   GPIO_Init(GPIOA, &GPIO_InitStructure);
00121 }
00122
00123 /**
00124   * @brief  Configure the nested vectored interrupt controller.
00125   * @param  None
00126   * @retval None
00127   */
00128 void NVIC_Configuration(void)
00129 {
00130   NVIC_InitTypeDef NVIC_InitStructure;
00131
00132   /* Enable the TIM3 global Interrupt */
00133   NVIC_InitStructure.NVIC_IRQChannel = TIM3_IRQn;
00134   NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
00135   NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;
00136   NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
00137   NVIC_Init(&NVIC_InitStructure);
00138 }
00139
00140 #ifdef  USE_FULL_ASSERT
00141
00142 /**
00143   * @brief  Reports the name of the source file and the source line number
00144   *         where the assert_param error has occurred.
00145   * @param  file: pointer to the source file name
00146   * @param  line: assert_param error line source number
00147   * @retval None
00148   */
00149 void assert_failed(uint8_t* file, uint32_t line)
00150 {
00151   /* User can add his own implementation to report the file name and line number,
00152      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00153
00154   while (1)
00155   {}
00156 }
00157
00158 #endif
00159
00160 /**
00161   * @}
00162   */
00163
00164 /**
00165   * @}
00166   */
00167
00168 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_conf.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    TIM/InputCapture/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052 /* Exported types ------------------------------------------------------------*/
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Uncomment the line below to expanse the "assert_param" macro in the
00055    Standard Peripheral Library drivers code */
00056 /* #define USE_FULL_ASSERT    1 */
00057
00058 /* Exported macro ------------------------------------------------------------*/
00059 #ifdef  USE_FULL_ASSERT
00060
00061 /**
00062   * @brief  The assert_param macro is used for function's parameters check.
00063   * @param  expr: If expr is false, it calls assert_failed function which reports
00064   *         the name of the source file and the source line number of the call
00065   *         that failed. If expr is true, it returns no value.
00066   * @retval None
00067   */
00068   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00069 /* Exported functions ------------------------------------------------------- */
00070   void assert_failed(uint8_t* file, uint32_t line);
00071 #else
00072   #define assert_param(expr) ((void)0)
00073 #endif /* USE_FULL_ASSERT */
00074
00075 #endif /* __STM32F10x_CONF_H */
00076
00077 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_it.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    TIM/InputCapture/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and
00009   *          peripherals interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026
00027 /** @addtogroup STM32F10x_StdPeriph_Examples
00028   * @{
00029   */
00030
00031 /** @addtogroup TIM_Input_Capture
00032   * @{
00033   */
00034
00035 /* Private typedef -----------------------------------------------------------*/
00036 /* Private define ------------------------------------------------------------*/
00037 /* Private macro -------------------------------------------------------------*/
00038 /* Private variables ---------------------------------------------------------*/
00039 __IO uint16_t IC3ReadValue1 = 0, IC3ReadValue2 = 0;
00040 __IO uint16_t CaptureNumber = 0;
00041 __IO uint32_t Capture = 0;
00042 __IO uint32_t TIM3Freq = 0;
00043
00044 /* Private function prototypes -----------------------------------------------*/
00045 /* Private functions ---------------------------------------------------------*/
00046
00047 /******************************************************************************/
00048 /*            Cortex-M3 Processor Exceptions Handlers                         */
00049 /******************************************************************************/
00050
00051 /**
00052   * @brief  This function handles NMI exception.
00053   * @param  None
00054   * @retval None
00055   */
00056 void NMI_Handler(void)
00057 {
00058 }
00059
00060 /**
00061   * @brief  This function handles Hard Fault exception.
00062   * @param  None
00063   * @retval None
00064   */
00065 void HardFault_Handler(void)
00066 {
00067   /* Go to infinite loop when Hard Fault exception occurs */
00068   while (1)
00069   {}
00070 }
00071
00072 /**
00073   * @brief  This function handles Memory Manage exception.
00074   * @param  None
00075   * @retval None
00076   */
00077 void MemManage_Handler(void)
00078 {
00079   /* Go to infinite loop when Memory Manage exception occurs */
00080   while (1)
00081   {}
00082 }
00083
00084 /**
00085   * @brief  This function handles Bus Fault exception.
00086   * @param  None
00087   * @retval None
00088   */
00089 void BusFault_Handler(void)
00090 {
00091   /* Go to infinite loop when Bus Fault exception occurs */
00092   while (1)
00093   {}
00094 }
00095
00096 /**
00097   * @brief  This function handles Usage Fault exception.
00098   * @param  None
00099   * @retval None
00100   */
00101 void UsageFault_Handler(void)
00102 {
00103   /* Go to infinite loop when Usage Fault exception occurs */
00104   while (1)
00105   {}
00106 }
00107
00108 /**
00109   * @brief  This function handles Debug Monitor exception.
00110   * @param  None
00111   * @retval None
00112   */
00113 void DebugMon_Handler(void)
00114 {}
00115
00116 /**
00117   * @brief  This function handles SVCall exception.
00118   * @param  None
00119   * @retval None
00120   */
00121 void SVC_Handler(void)
00122 {}
00123
00124 /**
00125   * @brief  This function handles PendSV_Handler exception.
00126   * @param  None
00127   * @retval None
00128   */
00129 void PendSV_Handler(void)
00130 {}
00131
00132 /**
00133   * @brief  This function handles SysTick Handler.
00134   * @param  None
00135   * @retval None
00136   */
00137 void SysTick_Handler(void)
00138 {}
00139
00140 /******************************************************************************/
00141 /*            STM32F10x Peripherals Interrupt Handlers                        */
00142 /******************************************************************************/
00143 /**
00144   * @brief  This function handles TIM3 global interrupt request.
00145   * @param  None
00146   * @retval None
00147   */
00148 void TIM3_IRQHandler(void)
00149 {
00150   if(TIM_GetITStatus(TIM3, TIM_IT_CC2) == SET)
00151   {
00152     /* Clear TIM3 Capture compare interrupt pending bit */
00153     TIM_ClearITPendingBit(TIM3, TIM_IT_CC2);
00154     if(CaptureNumber == 0)
00155     {
00156       /* Get the Input Capture value */
00157       IC3ReadValue1 = TIM_GetCapture2(TIM3);
00158       CaptureNumber = 1;
00159     }
00160     else if(CaptureNumber == 1)
00161     {
00162       /* Get the Input Capture value */
00163       IC3ReadValue2 = TIM_GetCapture2(TIM3);
00164
00165       /* Capture computation */
00166       if (IC3ReadValue2 > IC3ReadValue1)
00167       {
00168         Capture = (IC3ReadValue2 - IC3ReadValue1);
00169       }
00170       else
00171       {
00172         Capture = ((0xFFFF - IC3ReadValue1) + IC3ReadValue2);
00173       }
00174       /* Frequency computation */
00175       TIM3Freq = (uint32_t) SystemCoreClock / Capture;
00176       CaptureNumber = 0;
00177     }
00178   }
00179 }
00180
00181 /******************************************************************************/
00182 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00183 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00184 /*  available peripheral interrupt handler's name please refer to the startup */
00185 /*  file (startup_stm32f10x_xx.s).                                            */
00186 /******************************************************************************/
00187
00188 /**
00189   * @brief  This function handles PPP interrupt request.
00190   * @param  None
00191   * @retval None
00192   */
00193 /*void PPP_IRQHandler(void)
00194 {
00195 }*/
00196
00197 /**
00198   * @}
00199   */
00200
00201 /**
00202   * @}
00203   */
00204
00205 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_it.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    TIM/InputCapture/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043 void TIM3_IRQHandler(void);
00044
00045 #endif /* __STM32F10x_IT_H */
00046
00047 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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STM32F10x_StdPeriph_Examples/TIM/OCActive/main.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    TIM/OCActive/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x.h"
00024
00025 /** @addtogroup STM32F10x_StdPeriph_Examples
00026   * @{
00027   */
00028
00029 /** @addtogroup TIM_OCActive
00030   * @{
00031   */
00032
00033 /* Private typedef -----------------------------------------------------------*/
00034 /* Private define ------------------------------------------------------------*/
00035 /* Private macro -------------------------------------------------------------*/
00036 /* Private variables ---------------------------------------------------------*/
00037 TIM_TimeBaseInitTypeDef  TIM_TimeBaseStructure;
00038 TIM_OCInitTypeDef  TIM_OCInitStructure;
00039 uint16_t CCR1_Val = 1000;
00040 uint16_t CCR2_Val = 500;
00041 uint16_t CCR3_Val = 250;
00042 uint16_t CCR4_Val = 125;
00043 uint16_t PrescalerValue = 0;
00044
00045 /* Private function prototypes -----------------------------------------------*/
00046 void RCC_Configuration(void);
00047 void GPIO_Configuration(void);
00048
00049 /* Private functions ---------------------------------------------------------*/
00050
00051 /**
00052   * @brief  Main program
00053   * @param  None
00054   * @retval None
00055   */
00056 int main(void)
00057 {
00058   /*!< At this stage the microcontroller clock setting is already configured,
00059        this is done through SystemInit() function which is called from startup
00060        file (startup_stm32f10x_xx.s) before to branch to application main.
00061        To reconfigure the default setting of SystemInit() function, refer to
00062        system_stm32f10x.c file
00063      */
00064
00065  /* System Clocks Configuration */
00066   RCC_Configuration();
00067
00068   /* Configure the GPIO ports */
00069   GPIO_Configuration();
00070
00071   /* ---------------------------------------------------------------
00072     TIM3 Configuration:
00073     TIM3CLK = SystemCoreClock / 2,
00074     The objective is to get TIM3 counter clock at 1 KHz:
00075      - Prescaler = (TIM3CLK / TIM3 counter clock) - 1
00076     And generate 4 signals with 4 different delays:
00077     TIM3_CH1 delay = CCR1_Val/TIM3 counter clock = 1000 ms
00078     TIM3_CH2 delay = CCR2_Val/TIM3 counter clock = 500 ms
00079     TIM3_CH3 delay = CCR3_Val/TIM3 counter clock = 250 ms
00080     TIM3_CH4 delay = CCR4_Val/TIM3 counter clock = 125 ms
00081
00082   * SystemCoreClock is set to 72 MHz for Low-density, Medium-density, High-density
00083     and Connectivity line devices and to 24 MHz for Low-Density Value line and
00084     Medium-Density Value line devices
00085   --------------------------------------------------------------- */
00086   /*Compute the prescaler value */
00087   PrescalerValue = (uint16_t) (SystemCoreClock / 2000) - 1;
00088   /* Time base configuration */
00089   TIM_TimeBaseStructure.TIM_Period = 65535;
00090   TIM_TimeBaseStructure.TIM_Prescaler = PrescalerValue;
00091   TIM_TimeBaseStructure.TIM_ClockDivision = 0;
00092   TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
00093
00094   TIM_TimeBaseInit(TIM3, &TIM_TimeBaseStructure);
00095
00096   /* Output Compare Active Mode configuration: Channel1 */
00097   TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_Active;
00098   TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
00099   TIM_OCInitStructure.TIM_Pulse = CCR1_Val;
00100   TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High;
00101   TIM_OC1Init(TIM3, &TIM_OCInitStructure);
00102
00103   TIM_OC1PreloadConfig(TIM3, TIM_OCPreload_Disable);
00104
00105   /* Output Compare Active Mode configuration: Channel2 */
00106   TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
00107   TIM_OCInitStructure.TIM_Pulse = CCR2_Val;
00108
00109   TIM_OC2Init(TIM3, &TIM_OCInitStructure);
00110
00111   TIM_OC2PreloadConfig(TIM3, TIM_OCPreload_Disable);
00112
00113   /* Output Compare Active Mode configuration: Channel3 */
00114   TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
00115   TIM_OCInitStructure.TIM_Pulse = CCR3_Val;
00116
00117   TIM_OC3Init(TIM3, &TIM_OCInitStructure);
00118
00119   TIM_OC3PreloadConfig(TIM3, TIM_OCPreload_Disable);
00120
00121   /* Output Compare Active Mode configuration: Channel4 */
00122   TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
00123   TIM_OCInitStructure.TIM_Pulse = CCR4_Val;
00124
00125   TIM_OC4Init(TIM3, &TIM_OCInitStructure);
00126
00127   TIM_OC4PreloadConfig(TIM3, TIM_OCPreload_Disable);
00128
00129   TIM_ARRPreloadConfig(TIM3, ENABLE);
00130
00131 #ifdef STM32F10X_CL
00132   /* Set PD.07 pin */
00133   GPIO_SetBits(GPIOD, GPIO_Pin_7);
00134 #else
00135   /* Set PC.06 pin */
00136   GPIO_SetBits(GPIOC, GPIO_Pin_6);
00137 #endif
00138
00139   /* TIM3 enable counter */
00140   TIM_Cmd(TIM3, ENABLE);
00141
00142   while (1)
00143   {}
00144 }
00145
00146 /**
00147   * @brief  Configures the different system clocks.
00148   * @param  None
00149   * @retval None
00150   */
00151 void RCC_Configuration(void)
00152 {
00153   /* PCLK1 = HCLK/4 */
00154   RCC_PCLK1Config(RCC_HCLK_Div4);
00155
00156   /* TIM3 clock enable */
00157   RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM3, ENABLE);
00158
00159   /* GPIOA and GPIOC clock enable */
00160   RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOB |
00161                          RCC_APB2Periph_GPIOC | RCC_APB2Periph_AFIO, ENABLE);
00162 }
00163
00164 /**
00165   * @brief  Configure the TIM3 and the GPIOE Pins.
00166   * @param  None
00167   * @retval None
00168   */
00169 void GPIO_Configuration(void)
00170 {
00171   GPIO_InitTypeDef GPIO_InitStructure;
00172
00173 #ifdef STM32F10X_CL
00174   /*GPIOB Configuration: TIM3 channel1, 2, 3 and 4 */
00175   GPIO_InitStructure.GPIO_Pin =  GPIO_Pin_6 | GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9;
00176   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
00177   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00178
00179   GPIO_Init(GPIOC, &GPIO_InitStructure);
00180
00181   GPIO_PinRemapConfig(GPIO_FullRemap_TIM3, ENABLE);
00182
00183  /* GPIOD Configuration: Pin7 an Output push-pull */
00184   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7;
00185   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
00186
00187   GPIO_Init(GPIOD, &GPIO_InitStructure);
00188 #else
00189   /* GPIOA Configuration:TIM3 Channel1, 2, 3 and 4 as alternate function push-pull */
00190   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6 | GPIO_Pin_7;
00191   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
00192   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00193
00194   GPIO_Init(GPIOA, &GPIO_InitStructure);
00195
00196   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1;
00197   GPIO_Init(GPIOB, &GPIO_InitStructure);
00198
00199   /* GPIOC Configuration: Pin6 an Output push-pull */
00200   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
00201   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
00202
00203   GPIO_Init(GPIOC, &GPIO_InitStructure);
00204 #endif
00205 }
00206
00207 #ifdef  USE_FULL_ASSERT
00208
00209 /**
00210   * @brief  Reports the name of the source file and the source line number
00211   *         where the assert_param error has occurred.
00212   * @param  file: pointer to the source file name
00213   * @param  line: assert_param error line source number
00214   * @retval None
00215   */
00216 void assert_failed(uint8_t* file, uint32_t line)
00217 {
00218   /* User can add his own implementation to report the file name and line number,
00219      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00220
00221   while (1)
00222   {}
00223 }
00224
00225 #endif
00226
00227 /**
00228   * @}
00229   */
00230
00231 /**
00232   * @}
00233   */
00234
00235 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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STM32F10x_StdPeriph_Examples/TIM/OCActive/stm32f10x_conf.h

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00001 /**
00002   ******************************************************************************
00003   * @file    TIM/OCActive/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052 /* Exported types ------------------------------------------------------------*/
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Uncomment the line below to expanse the "assert_param" macro in the
00055    Standard Peripheral Library drivers code */
00056 /* #define USE_FULL_ASSERT    1 */
00057
00058 /* Exported macro ------------------------------------------------------------*/
00059 #ifdef  USE_FULL_ASSERT
00060
00061 /**
00062   * @brief  The assert_param macro is used for function's parameters check.
00063   * @param  expr: If expr is false, it calls assert_failed function which reports
00064   *         the name of the source file and the source line number of the call
00065   *         that failed. If expr is true, it returns no value.
00066   * @retval None
00067   */
00068   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00069 /* Exported functions ------------------------------------------------------- */
00070   void assert_failed(uint8_t* file, uint32_t line);
00071 #else
00072   #define assert_param(expr) ((void)0)
00073 #endif /* USE_FULL_ASSERT */
00074
00075 #endif /* __STM32F10x_CONF_H */
00076
00077 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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STM32F10x_StdPeriph_Examples/TIM/OCActive/stm32f10x_it.c

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00001 /**
00002   ******************************************************************************
00003   * @file    TIM/OCActive/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *        This file provides template for all exceptions handler and
00009   *        peripherals interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026
00027 /** @addtogroup STM32F10x_StdPeriph_Examples
00028   * @{
00029   */
00030
00031 /** @addtogroup TIM_OCActive
00032   * @{
00033   */
00034
00035 /* Private typedef -----------------------------------------------------------*/
00036 /* Private define ------------------------------------------------------------*/
00037 /* Private macro -------------------------------------------------------------*/
00038 /* Private variables ---------------------------------------------------------*/
00039 /* Private function prototypes -----------------------------------------------*/
00040 /* Private functions ---------------------------------------------------------*/
00041
00042 /******************************************************************************/
00043 /*            Cortex-M3 Processor Exceptions Handlers                         */
00044 /******************************************************************************/
00045
00046 /**
00047   * @brief  This function handles NMI exception.
00048   * @param  None
00049   * @retval None
00050   */
00051 void NMI_Handler(void)
00052 {
00053 }
00054
00055 /**
00056   * @brief  This function handles Hard Fault exception.
00057   * @param  None
00058   * @retval None
00059   */
00060 void HardFault_Handler(void)
00061 {
00062   /* Go to infinite loop when Hard Fault exception occurs */
00063   while (1)
00064   {}
00065 }
00066
00067 /**
00068   * @brief  This function handles Memory Manage exception.
00069   * @param  None
00070   * @retval None
00071   */
00072 void MemManage_Handler(void)
00073 {
00074   /* Go to infinite loop when Memory Manage exception occurs */
00075   while (1)
00076   {}
00077 }
00078
00079 /**
00080   * @brief  This function handles Bus Fault exception.
00081   * @param  None
00082   * @retval None
00083   */
00084 void BusFault_Handler(void)
00085 {
00086   /* Go to infinite loop when Bus Fault exception occurs */
00087   while (1)
00088   {}
00089 }
00090
00091 /**
00092   * @brief  This function handles Usage Fault exception.
00093   * @param  None
00094   * @retval None
00095   */
00096 void UsageFault_Handler(void)
00097 {
00098   /* Go to infinite loop when Usage Fault exception occurs */
00099   while (1)
00100   {}
00101 }
00102
00103 /**
00104   * @brief  This function handles Debug Monitor exception.
00105   * @param  None
00106   * @retval None
00107   */
00108 void DebugMon_Handler(void)
00109 {}
00110
00111 /**
00112   * @brief  This function handles SVCall exception.
00113   * @param  None
00114   * @retval None
00115   */
00116 void SVC_Handler(void)
00117 {}
00118
00119 /**
00120   * @brief  This function handles PendSV_Handler exception.
00121   * @param  None
00122   * @retval None
00123   */
00124 void PendSV_Handler(void)
00125 {}
00126
00127 /**
00128   * @brief  This function handles SysTick Handler.
00129   * @param  None
00130   * @retval None
00131   */
00132 void SysTick_Handler(void)
00133 {}
00134
00135 /******************************************************************************/
00136 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00137 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00138 /*  available peripheral interrupt handler's name please refer to the startup */
00139 /*  file (startup_stm32f10x_xx.s).                                            */
00140 /******************************************************************************/
00141
00142 /**
00143   * @brief  This function handles PPP interrupt request.
00144   * @param  None
00145   * @retval None
00146   */
00147 /*void PPP_IRQHandler(void)
00148 {
00149 }*/
00150
00151 /**
00152   * @}
00153   */
00154
00155 /**
00156   * @}
00157   */
00158
00159 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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STM32F10x_StdPeriph_Examples/TIM/OCActive/stm32f10x_it.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    TIM/OCActive/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043
00044 #endif /* __STM32F10x_IT_H */
00045
00046 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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STM32F10x_StdPeriph_Examples/TIM/OCInactive/main.c

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00001 /**
00002   ******************************************************************************
00003   * @file    TIM/OCInactive/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x.h"
00024
00025 /** @addtogroup STM32F10x_StdPeriph_Examples
00026   * @{
00027   */
00028
00029 /** @addtogroup TIM_OCInactive
00030   * @{
00031   */
00032
00033 /* Private typedef -----------------------------------------------------------*/
00034 /* Private define ------------------------------------------------------------*/
00035 /* Private macro -------------------------------------------------------------*/
00036 /* Private variables ---------------------------------------------------------*/
00037 TIM_TimeBaseInitTypeDef  TIM_TimeBaseStructure;
00038 TIM_OCInitTypeDef  TIM_OCInitStructure;
00039 uint16_t CCR1_Val = 1000;
00040 uint16_t CCR2_Val = 500;
00041 uint16_t CCR3_Val = 250;
00042 uint16_t CCR4_Val = 125;
00043 uint16_t PrescalerValue = 0;
00044
00045 /* Private function prototypes -----------------------------------------------*/
00046 void RCC_Configuration(void);
00047 void GPIO_Configuration(void);
00048 void NVIC_Configuration(void);
00049
00050 /* Private functions ---------------------------------------------------------*/
00051
00052 /**
00053   * @brief  Main program
00054   * @param  None
00055   * @retval None
00056   */
00057 int main(void)
00058 {
00059   /*!< At this stage the microcontroller clock setting is already configured,
00060        this is done through SystemInit() function which is called from startup
00061        file (startup_stm32f10x_xx.s) before to branch to application main.
00062        To reconfigure the default setting of SystemInit() function, refer to
00063        system_stm32f10x.c file
00064      */
00065
00066   /* System Clocks Configuration */
00067   RCC_Configuration();
00068
00069   /* NVIC Configuration */
00070   NVIC_Configuration();
00071
00072   /* GPIO Configuration */
00073   GPIO_Configuration();
00074
00075   /* ---------------------------------------------------------------
00076     TIM2 Configuration:
00077     TIM2CLK = SystemCoreClock / 2,
00078     The objective is to get TIM2 counter clock at 1 KHz:
00079      - Prescaler = (TIM2CLK / TIM2 counter clock) - 1
00080     And generate 4 signals with 4 different delays:
00081     TIM2_CH1 delay = CCR1_Val/TIM2 counter clock = 1000 ms
00082     TIM2_CH2 delay = CCR2_Val/TIM2 counter clock = 500 ms
00083     TIM2_CH3 delay = CCR3_Val/TIM2 counter clock = 250 ms
00084     TIM2_CH4 delay = CCR4_Val/TIM2 counter clock = 125 ms
00085
00086   * SystemCoreClock is set to 72 MHz for Low-density, Medium-density, High-density
00087     and Connectivity line devices and to 24 MHz for Low-Density Value line and
00088     Medium-Density Value line devices
00089   --------------------------------------------------------------- */
00090   /* Compute the prescaler value */
00091   PrescalerValue = (uint16_t) (SystemCoreClock / 2000) - 1;
00092   /* Time base configuration */
00093   TIM_TimeBaseStructure.TIM_Period = 65535;
00094   TIM_TimeBaseStructure.TIM_Prescaler = PrescalerValue;
00095   TIM_TimeBaseStructure.TIM_ClockDivision = 0;
00096   TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
00097
00098   TIM_TimeBaseInit(TIM2, &TIM_TimeBaseStructure);
00099
00100   /* Output Compare Active Mode configuration: Channel1 */
00101   TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_Inactive;
00102   TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
00103   TIM_OCInitStructure.TIM_Pulse = CCR1_Val;
00104   TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High;
00105
00106   TIM_OC1Init(TIM2, &TIM_OCInitStructure);
00107
00108   TIM_OC1PreloadConfig(TIM2, TIM_OCPreload_Disable);
00109
00110   /* Output Compare Active Mode configuration: Channel2 */
00111   TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
00112   TIM_OCInitStructure.TIM_Pulse = CCR2_Val;
00113
00114   TIM_OC2Init(TIM2, &TIM_OCInitStructure);
00115
00116   TIM_OC2PreloadConfig(TIM2, TIM_OCPreload_Disable);
00117
00118   /* Output Compare Active Mode configuration: Channel3 */
00119   TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
00120   TIM_OCInitStructure.TIM_Pulse = CCR3_Val;
00121
00122   TIM_OC3Init(TIM2, &TIM_OCInitStructure);
00123
00124   TIM_OC3PreloadConfig(TIM2, TIM_OCPreload_Disable);
00125
00126   /* Output Compare Active Mode configuration: Channel4 */
00127   TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
00128   TIM_OCInitStructure.TIM_Pulse = CCR4_Val;
00129
00130   TIM_OC4Init(TIM2, &TIM_OCInitStructure);
00131
00132   TIM_OC4PreloadConfig(TIM2, TIM_OCPreload_Disable);
00133
00134   TIM_ARRPreloadConfig(TIM2, ENABLE);
00135
00136   /* TIM IT enable */
00137   TIM_ITConfig(TIM2, TIM_IT_CC1 | TIM_IT_CC2 | TIM_IT_CC3 | TIM_IT_CC4, ENABLE);
00138
00139   /* Set PC.06, PC.07, PC.08 and PC.09 pins */
00140   GPIO_SetBits(GPIOC, GPIO_Pin_6 | GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9);
00141
00142   /* TIM2 enable counter */
00143   TIM_Cmd(TIM2, ENABLE);
00144
00145   while (1)
00146   {}
00147 }
00148
00149 /**
00150   * @brief  Configures the different system clocks.
00151   * @param  None
00152   * @retval None
00153   */
00154 void RCC_Configuration(void)
00155 {
00156   /* PCLK1 = HCLK/4 */
00157   RCC_PCLK1Config(RCC_HCLK_Div4);
00158
00159   /* TIM2 clock enable */
00160   RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2, ENABLE);
00161
00162   /* GPIOC clock enable */
00163   RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC, ENABLE);
00164 }
00165
00166 /**
00167   * @brief  Configure the GPIOD Pins.
00168   * @param  None
00169   * @retval None
00170   */
00171 void GPIO_Configuration(void)
00172 {
00173   GPIO_InitTypeDef GPIO_InitStructure;
00174
00175   /* GPIOC Configuration: Pin6, 7, 8 and 9 as output push-pull */
00176   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6 | GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9;
00177   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
00178   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00179
00180   GPIO_Init(GPIOC, &GPIO_InitStructure);
00181 }
00182
00183 /**
00184   * @brief  Configure the nested vectored interrupt controller.
00185   * @param  None
00186   * @retval None
00187   */
00188 void NVIC_Configuration(void)
00189 {
00190   NVIC_InitTypeDef NVIC_InitStructure;
00191
00192   /* Enable the TIM2 Interrupt */
00193   NVIC_InitStructure.NVIC_IRQChannel = TIM2_IRQn;
00194   NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
00195   NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;
00196   NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
00197
00198   NVIC_Init(&NVIC_InitStructure);
00199
00200 }
00201
00202 #ifdef  USE_FULL_ASSERT
00203
00204 /**
00205   * @brief  Reports the name of the source file and the source line number
00206   *         where the assert_param error has occurred.
00207   * @param  file: pointer to the source file name
00208   * @param  line: assert_param error line source number
00209   * @retval None
00210   */
00211 void assert_failed(uint8_t* file, uint32_t line)
00212 {
00213   /* User can add his own implementation to report the file name and line number,
00214      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00215
00216   while (1)
00217   {}
00218 }
00219
00220 #endif
00221 /**
00222   * @}
00223   */
00224
00225 /**
00226   * @}
00227   */
00228
00229 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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STM32F10x_StdPeriph_Examples/TIM/OCInactive/stm32f10x_conf.h

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00001 /**
00002   ******************************************************************************
00003   * @file    TIM/OCInactive/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052 /* Exported types ------------------------------------------------------------*/
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Uncomment the line below to expanse the "assert_param" macro in the
00055    Standard Peripheral Library drivers code */
00056 /* #define USE_FULL_ASSERT    1 */
00057
00058 /* Exported macro ------------------------------------------------------------*/
00059 #ifdef  USE_FULL_ASSERT
00060
00061 /**
00062   * @brief  The assert_param macro is used for function's parameters check.
00063   * @param  expr: If expr is false, it calls assert_failed function which reports
00064   *         the name of the source file and the source line number of the call
00065   *         that failed. If expr is true, it returns no value.
00066   * @retval None
00067   */
00068   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00069 /* Exported functions ------------------------------------------------------- */
00070   void assert_failed(uint8_t* file, uint32_t line);
00071 #else
00072   #define assert_param(expr) ((void)0)
00073 #endif /* USE_FULL_ASSERT */
00074
00075 #endif /* __STM32F10x_CONF_H */
00076
00077 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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STM32F10x_StdPeriph_Examples/TIM/OCInactive/stm32f10x_it.c

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00001 /**
00002   ******************************************************************************
00003   * @file    TIM/OCInactive/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and peripherals
00009   *          interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026
00027 /** @addtogroup STM32F10x_StdPeriph_Examples
00028   * @{
00029   */
00030
00031 /** @addtogroup TIM_OCInactive
00032   * @{
00033   */
00034
00035 /* Private typedef -----------------------------------------------------------*/
00036 /* Private define ------------------------------------------------------------*/
00037 /* Private macro -------------------------------------------------------------*/
00038 /* Private variables ---------------------------------------------------------*/
00039 /* Private function prototypes -----------------------------------------------*/
00040 /* Private functions ---------------------------------------------------------*/
00041
00042 /******************************************************************************/
00043 /*            Cortex-M3 Processor Exceptions Handlers                         */
00044 /******************************************************************************/
00045
00046 /**
00047   * @brief  This function handles NMI exception.
00048   * @param  None
00049   * @retval None
00050   */
00051 void NMI_Handler(void)
00052 {
00053 }
00054
00055 /**
00056   * @brief  This function handles Hard Fault exception.
00057   * @param  None
00058   * @retval None
00059   */
00060 void HardFault_Handler(void)
00061 {
00062   /* Go to infinite loop when Hard Fault exception occurs */
00063   while (1)
00064   {}
00065 }
00066
00067 /**
00068   * @brief  This function handles Memory Manage exception.
00069   * @param  None
00070   * @retval None
00071   */
00072 void MemManage_Handler(void)
00073 {
00074   /* Go to infinite loop when Memory Manage exception occurs */
00075   while (1)
00076   {}
00077 }
00078
00079 /**
00080   * @brief  This function handles Bus Fault exception.
00081   * @param  None
00082   * @retval None
00083   */
00084 void BusFault_Handler(void)
00085 {
00086   /* Go to infinite loop when Bus Fault exception occurs */
00087   while (1)
00088   {}
00089 }
00090
00091 /**
00092   * @brief  This function handles Usage Fault exception.
00093   * @param  None
00094   * @retval None
00095   */
00096 void UsageFault_Handler(void)
00097 {
00098   /* Go to infinite loop when Usage Fault exception occurs */
00099   while (1)
00100   {}
00101 }
00102
00103 /**
00104   * @brief  This function handles Debug Monitor exception.
00105   * @param  None
00106   * @retval None
00107   */
00108 void DebugMon_Handler(void)
00109 {}
00110
00111 /**
00112   * @brief  This function handles SVCall exception.
00113   * @param  None
00114   * @retval None
00115   */
00116 void SVC_Handler(void)
00117 {}
00118
00119 /**
00120   * @brief  This function handles PendSV_Handler exception.
00121   * @param  None
00122   * @retval None
00123   */
00124 void PendSV_Handler(void)
00125 {}
00126
00127 /**
00128   * @brief  This function handles SysTick Handler.
00129   * @param  None
00130   * @retval None
00131   */
00132 void SysTick_Handler(void)
00133 {}
00134
00135 /******************************************************************************/
00136 /*            STM32F10x Peripherals Interrupt Handlers                        */
00137 /******************************************************************************/
00138
00139 /**
00140   * @brief  This function handles TIM2 global interrupt request.
00141   * @param  None
00142   * @retval None
00143   */
00144 void TIM2_IRQHandler(void)
00145 {
00146   if (TIM_GetITStatus(TIM2, TIM_IT_CC1) != RESET)
00147   {
00148     /* Clear TIM2 Capture Compare1 interrupt pending bit*/
00149     TIM_ClearITPendingBit(TIM2, TIM_IT_CC1);
00150
00151     /* PC.06 turnoff after 1000 ms */
00152     GPIO_ResetBits(GPIOC, GPIO_Pin_6);
00153   }
00154   else if (TIM_GetITStatus(TIM2, TIM_IT_CC2) != RESET)
00155   {
00156     /* Clear TIM2 Capture Compare2 interrupt pending bit*/
00157     TIM_ClearITPendingBit(TIM2, TIM_IT_CC2);
00158
00159     /* PC.07 turnoff after 500 ms */
00160     GPIO_ResetBits(GPIOC, GPIO_Pin_7);
00161   }
00162   else if (TIM_GetITStatus(TIM2, TIM_IT_CC3) != RESET)
00163   {
00164     /* Clear TIM2 Capture Compare3 interrupt pending bit*/
00165     TIM_ClearITPendingBit(TIM2, TIM_IT_CC3);
00166
00167     /* PC.08 turnoff after 250 ms */
00168     GPIO_ResetBits(GPIOC, GPIO_Pin_8);
00169   }
00170   else
00171   {
00172     /* Clear TIM2 Capture Compare4 interrupt pending bit*/
00173     TIM_ClearITPendingBit(TIM2, TIM_IT_CC4);
00174
00175     /* PC.09 turnoff after 125 ms */
00176     GPIO_ResetBits(GPIOC, GPIO_Pin_9);
00177   }
00178 }
00179
00180 /******************************************************************************/
00181 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00182 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00183 /*  available peripheral interrupt handler's name please refer to the startup */
00184 /*  file (startup_stm32f10x_xx.s).                                            */
00185 /******************************************************************************/
00186
00187 /**
00188   * @brief  This function handles PPP interrupt request.
00189   * @param  None
00190   * @retval None
00191   */
00192 /*void PPP_IRQHandler(void)
00193 {
00194 }*/
00195
00196 /**
00197   * @}
00198   */
00199
00200 /**
00201   * @}
00202   */
00203
00204 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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STM32F10x_StdPeriph_Examples/TIM/OCInactive/stm32f10x_it.h

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00001 /**
00002   ******************************************************************************
00003   * @file    TIM/OCInactive/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043 void TIM2_IRQHandler(void);
00044
00045 #endif /* __STM32F10x_IT_H */
00046
00047 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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STM32F10x_StdPeriph_Examples/TIM/OCToggle/main.c

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00001 /**
00002   ******************************************************************************
00003   * @file    TIM/OCToggle/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x.h"
00024
00025 /** @addtogroup STM32F10x_StdPeriph_Examples
00026   * @{
00027   */
00028
00029 /** @addtogroup TIM_OCToggle
00030   * @{
00031   */
00032
00033 /* Private typedef -----------------------------------------------------------*/
00034 /* Private define ------------------------------------------------------------*/
00035 /* Private macro -------------------------------------------------------------*/
00036 /* Private variables ---------------------------------------------------------*/
00037 TIM_TimeBaseInitTypeDef  TIM_TimeBaseStructure;
00038 TIM_OCInitTypeDef  TIM_OCInitStructure;
00039 __IO uint16_t CCR1_Val = 32768;
00040 __IO uint16_t CCR2_Val = 16384;
00041 __IO uint16_t CCR3_Val = 8192;
00042 __IO uint16_t CCR4_Val = 4096;
00043 uint16_t PrescalerValue = 0;
00044
00045 /* Private function prototypes -----------------------------------------------*/
00046 void RCC_Configuration(void);
00047 void GPIO_Configuration(void);
00048 void NVIC_Configuration(void);
00049
00050 /* Private functions ---------------------------------------------------------*/
00051
00052 /**
00053   * @brief  Main program
00054   * @param  None
00055   * @retval None
00056   */
00057 int main(void)
00058 {
00059   /*!< At this stage the microcontroller clock setting is already configured,
00060        this is done through SystemInit() function which is called from startup
00061        file (startup_stm32f10x_xx.s) before to branch to application main.
00062        To reconfigure the default setting of SystemInit() function, refer to
00063        system_stm32f10x.c file
00064      */
00065
00066   /* System Clocks Configuration */
00067   RCC_Configuration();
00068
00069   /* NVIC Configuration */
00070   NVIC_Configuration();
00071
00072   /* GPIO Configuration */
00073   GPIO_Configuration();
00074
00075   /* ---------------------------------------------------------------------------
00076     TIM3 Configuration: Output Compare Toggle Mode:
00077     TIM3CLK = SystemCoreClock / 2,
00078     The objective is to get TIM3 counter clock at 12 MHz:
00079      - Prescaler = (TIM3CLK / TIM3 counter clock) - 1
00080     CC1 update rate = TIM3 counter clock / CCR1_Val = 366.2 Hz
00081     CC2 update rate = TIM3 counter clock / CCR2_Val = 732.4 Hz
00082     CC3 update rate = TIM3 counter clock / CCR3_Val = 1464.8 Hz
00083     CC4 update rate = TIM3 counter clock / CCR4_Val = 2929.6 Hz
00084   ----------------------------------------------------------------------------*/
00085   /* Compute the prescaler value */
00086   PrescalerValue = (uint16_t) (SystemCoreClock / 24000000) - 1;
00087
00088   /* Time base configuration */
00089   TIM_TimeBaseStructure.TIM_Period = 65535;
00090   TIM_TimeBaseStructure.TIM_Prescaler = PrescalerValue;
00091   TIM_TimeBaseStructure.TIM_ClockDivision = 0;
00092   TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
00093
00094   TIM_TimeBaseInit(TIM3, &TIM_TimeBaseStructure);
00095
00096   /* Output Compare Toggle Mode configuration: Channel1 */
00097   TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_Toggle;
00098   TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
00099   TIM_OCInitStructure.TIM_Pulse = CCR1_Val;
00100   TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_Low;
00101   TIM_OC1Init(TIM3, &TIM_OCInitStructure);
00102
00103   TIM_OC1PreloadConfig(TIM3, TIM_OCPreload_Disable);
00104
00105   /* Output Compare Toggle Mode configuration: Channel2 */
00106   TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
00107   TIM_OCInitStructure.TIM_Pulse = CCR2_Val;
00108
00109   TIM_OC2Init(TIM3, &TIM_OCInitStructure);
00110
00111   TIM_OC2PreloadConfig(TIM3, TIM_OCPreload_Disable);
00112
00113   /* Output Compare Toggle Mode configuration: Channel3 */
00114   TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
00115   TIM_OCInitStructure.TIM_Pulse = CCR3_Val;
00116
00117   TIM_OC3Init(TIM3, &TIM_OCInitStructure);
00118
00119   TIM_OC3PreloadConfig(TIM3, TIM_OCPreload_Disable);
00120
00121   /* Output Compare Toggle Mode configuration: Channel4 */
00122   TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
00123   TIM_OCInitStructure.TIM_Pulse = CCR4_Val;
00124
00125   TIM_OC4Init(TIM3, &TIM_OCInitStructure);
00126
00127   TIM_OC4PreloadConfig(TIM3, TIM_OCPreload_Disable);
00128
00129   /* TIM enable counter */
00130   TIM_Cmd(TIM3, ENABLE);
00131
00132   /* TIM IT enable */
00133   TIM_ITConfig(TIM3, TIM_IT_CC1 | TIM_IT_CC2 | TIM_IT_CC3 | TIM_IT_CC4, ENABLE);
00134
00135   while (1)
00136   {}
00137 }
00138
00139 /**
00140   * @brief  Configures the different system clocks.
00141   * @param  None
00142   * @retval None
00143   */
00144 void RCC_Configuration(void)
00145 {
00146   /* PCLK1 = HCLK/4 */
00147   RCC_PCLK1Config(RCC_HCLK_Div4);
00148
00149   /* TIM3 clock enable */
00150   RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM3, ENABLE);
00151
00152   /* GPIOA clock enable */
00153   RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB|
00154                          RCC_APB2Periph_GPIOC | RCC_APB2Periph_AFIO, ENABLE);
00155 }
00156
00157 /**
00158   * @brief  Configure the TIM3 Pins.
00159   * @param  None
00160   * @retval None
00161   */
00162 void GPIO_Configuration(void)
00163 {
00164   GPIO_InitTypeDef GPIO_InitStructure;
00165
00166 #ifdef STM32F10X_CL
00167   /*GPIOB Configuration: TIM3 channel1, 2, 3 and 4 */
00168   GPIO_InitStructure.GPIO_Pin =  GPIO_Pin_6 | GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9;
00169   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
00170   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00171
00172   GPIO_Init(GPIOC, &GPIO_InitStructure);
00173
00174   GPIO_PinRemapConfig(GPIO_FullRemap_TIM3, ENABLE);
00175
00176 #else
00177   /* GPIOA Configuration:TIM3 Channel1, 2, 3 and 4 as alternate function push-pull */
00178   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6 | GPIO_Pin_7;
00179   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
00180   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00181
00182   GPIO_Init(GPIOA, &GPIO_InitStructure);
00183
00184   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1;
00185   GPIO_Init(GPIOB, &GPIO_InitStructure);
00186 #endif
00187 }
00188
00189 /**
00190   * @brief  Configure the nested vectored interrupt controller.
00191   * @param  None
00192   * @retval None
00193   */
00194 void NVIC_Configuration(void)
00195 {
00196   NVIC_InitTypeDef NVIC_InitStructure;
00197
00198   /* Enable the TIM3 global Interrupt */
00199   NVIC_InitStructure.NVIC_IRQChannel = TIM3_IRQn;
00200   NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
00201   NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
00202   NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
00203   NVIC_Init(&NVIC_InitStructure);
00204 }
00205
00206 #ifdef  USE_FULL_ASSERT
00207
00208 /**
00209   * @brief  Reports the name of the source file and the source line number
00210   *         where the assert_param error has occurred.
00211   * @param  file: pointer to the source file name
00212   * @param  line: assert_param error line source number
00213   * @retval None
00214   */
00215 void assert_failed(uint8_t* file, uint32_t line)
00216 {
00217   /* User can add his own implementation to report the file name and line number,
00218      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00219
00220   while (1)
00221   {}
00222 }
00223
00224 #endif
00225 /**
00226   * @}
00227   */
00228
00229 /**
00230   * @}
00231   */
00232
00233 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_conf.h

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00001 /**
00002   ******************************************************************************
00003   * @file    TIM/OCToggle/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052 /* Exported types ------------------------------------------------------------*/
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Uncomment the line below to expanse the "assert_param" macro in the
00055    Standard Peripheral Library drivers code */
00056 /* #define USE_FULL_ASSERT    1 */
00057
00058 /* Exported macro ------------------------------------------------------------*/
00059 #ifdef  USE_FULL_ASSERT
00060
00061 /**
00062   * @brief  The assert_param macro is used for function's parameters check.
00063   * @param  expr: If expr is false, it calls assert_failed function which reports
00064   *         the name of the source file and the source line number of the call
00065   *         that failed. If expr is true, it returns no value.
00066   * @retval None
00067   */
00068   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00069 /* Exported functions ------------------------------------------------------- */
00070   void assert_failed(uint8_t* file, uint32_t line);
00071 #else
00072   #define assert_param(expr) ((void)0)
00073 #endif /* USE_FULL_ASSERT */
00074
00075 #endif /* __STM32F10x_CONF_H */
00076
00077 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_it.c

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00001 /**
00002   ******************************************************************************
00003   * @file    TIM/OCToggle/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and peripherals
00009   *          interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026
00027 /** @addtogroup STM32F10x_StdPeriph_Examples
00028   * @{
00029   */
00030
00031 /** @addtogroup TIM_OCToggle
00032   * @{
00033   */
00034
00035 /* Private typedef -----------------------------------------------------------*/
00036 /* Private define ------------------------------------------------------------*/
00037 /* Private macro -------------------------------------------------------------*/
00038 /* Private variables ---------------------------------------------------------*/
00039 uint16_t capture = 0;
00040 extern __IO uint16_t CCR1_Val;
00041 extern __IO uint16_t CCR2_Val;
00042 extern __IO uint16_t CCR3_Val;
00043 extern __IO uint16_t CCR4_Val;
00044
00045 /* Private function prototypes -----------------------------------------------*/
00046 /* Private functions ---------------------------------------------------------*/
00047
00048 /******************************************************************************/
00049 /*            Cortex-M3 Processor Exceptions Handlers                         */
00050 /******************************************************************************/
00051
00052 /**
00053   * @brief  This function handles NMI exception.
00054   * @param  None
00055   * @retval None
00056   */
00057 void NMI_Handler(void)
00058 {
00059 }
00060
00061 /**
00062   * @brief  This function handles Hard Fault exception.
00063   * @param  None
00064   * @retval None
00065   */
00066 void HardFault_Handler(void)
00067 {
00068   /* Go to infinite loop when Hard Fault exception occurs */
00069   while (1)
00070   {}
00071 }
00072
00073 /**
00074   * @brief  This function handles Memory Manage exception.
00075   * @param  None
00076   * @retval None
00077   */
00078 void MemManage_Handler(void)
00079 {
00080   /* Go to infinite loop when Memory Manage exception occurs */
00081   while (1)
00082   {}
00083 }
00084
00085 /**
00086   * @brief  This function handles Bus Fault exception.
00087   * @param  None
00088   * @retval None
00089   */
00090 void BusFault_Handler(void)
00091 {
00092   /* Go to infinite loop when Bus Fault exception occurs */
00093   while (1)
00094   {}
00095 }
00096
00097 /**
00098   * @brief  This function handles Usage Fault exception.
00099   * @param  None
00100   * @retval None
00101   */
00102 void UsageFault_Handler(void)
00103 {
00104   /* Go to infinite loop when Usage Fault exception occurs */
00105   while (1)
00106   {}
00107 }
00108
00109 /**
00110   * @brief  This function handles Debug Monitor exception.
00111   * @param  None
00112   * @retval None
00113   */
00114 void DebugMon_Handler(void)
00115 {}
00116
00117 /**
00118   * @brief  This function handles SVCall exception.
00119   * @param  None
00120   * @retval None
00121   */
00122 void SVC_Handler(void)
00123 {}
00124
00125 /**
00126   * @brief  This function handles PendSV_Handler exception.
00127   * @param  None
00128   * @retval None
00129   */
00130 void PendSV_Handler(void)
00131 {}
00132
00133 /**
00134   * @brief  This function handles SysTick Handler.
00135   * @param  None
00136   * @retval None
00137   */
00138 void SysTick_Handler(void)
00139 {}
00140
00141 /******************************************************************************/
00142 /*            STM32F10x Peripherals Interrupt Handlers                        */
00143 /******************************************************************************/
00144
00145 /**
00146   * @brief  This function handles TIM3 global interrupt request.
00147   * @param  None
00148   * @retval None
00149   */
00150 void TIM3_IRQHandler(void)
00151 {
00152   /* TIM3_CH1 toggling with frequency = 183.1 Hz */
00153   if (TIM_GetITStatus(TIM3, TIM_IT_CC1) != RESET)
00154   {
00155     TIM_ClearITPendingBit(TIM3, TIM_IT_CC1 );
00156     capture = TIM_GetCapture1(TIM3);
00157     TIM_SetCompare1(TIM3, capture + CCR1_Val );
00158   }
00159
00160   /* TIM3_CH2 toggling with frequency = 366.2 Hz */
00161   if (TIM_GetITStatus(TIM3, TIM_IT_CC2) != RESET)
00162   {
00163     TIM_ClearITPendingBit(TIM3, TIM_IT_CC2);
00164     capture = TIM_GetCapture2(TIM3);
00165     TIM_SetCompare2(TIM3, capture + CCR2_Val);
00166   }
00167
00168   /* TIM3_CH3 toggling with frequency = 732.4 Hz */
00169   if (TIM_GetITStatus(TIM3, TIM_IT_CC3) != RESET)
00170   {
00171     TIM_ClearITPendingBit(TIM3, TIM_IT_CC3);
00172     capture = TIM_GetCapture3(TIM3);
00173     TIM_SetCompare3(TIM3, capture + CCR3_Val);
00174   }
00175
00176   /* TIM3_CH4 toggling with frequency = 1464.8 Hz */
00177   if (TIM_GetITStatus(TIM3, TIM_IT_CC4) != RESET)
00178   {
00179     TIM_ClearITPendingBit(TIM3, TIM_IT_CC4);
00180     capture = TIM_GetCapture4(TIM3);
00181     TIM_SetCompare4(TIM3, capture + CCR4_Val);
00182   }
00183 }
00184
00185 /******************************************************************************/
00186 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00187 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00188 /*  available peripheral interrupt handler's name please refer to the startup */
00189 /*  file (startup_stm32f10x_xx.s).                                            */
00190 /******************************************************************************/
00191
00192 /**
00193   * @brief  This function handles PPP interrupt request.
00194   * @param  None
00195   * @retval None
00196   */
00197 /*void PPP_IRQHandler(void)
00198 {
00199 }*/
00200
00201 /**
00202   * @}
00203   */
00204
00205 /**
00206   * @}
00207   */
00208
00209 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_it.h

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00001 /**
00002   ******************************************************************************
00003   * @file    TIM/OCToggle/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043 void TIM3_IRQHandler(void);
00044
00045 #endif /* __STM32F10x_IT_H */
00046
00047 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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STM32F10x_StdPeriph_Examples/TIM/OnePulse/main.c

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00001 /**
00002   ******************************************************************************
00003   * @file    TIM/OnePulse/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x.h"
00024
00025 /** @addtogroup STM32F10x_StdPeriph_Examples
00026   * @{
00027   */
00028
00029 /** @addtogroup TIM_OnePulse
00030   * @{
00031   */
00032
00033 /* Private typedef -----------------------------------------------------------*/
00034 /* Private define ------------------------------------------------------------*/
00035 /* Private macro -------------------------------------------------------------*/
00036 /* Private variables ---------------------------------------------------------*/
00037 TIM_TimeBaseInitTypeDef  TIM_TimeBaseStructure;
00038 TIM_ICInitTypeDef  TIM_ICInitStructure;
00039 TIM_OCInitTypeDef  TIM_OCInitStructure;
00040 uint16_t PrescalerValue = 0;
00041
00042 /* Private function prototypes -----------------------------------------------*/
00043 void RCC_Configuration(void);
00044 void GPIO_Configuration(void);
00045
00046 /* Private functions ---------------------------------------------------------*/
00047
00048 /**
00049   * @brief  Main program
00050   * @param  None
00051   * @retval None
00052   */
00053 int main(void)
00054 {
00055   /*!< At this stage the microcontroller clock setting is already configured,
00056        this is done through SystemInit() function which is called from startup
00057        file (startup_stm32f10x_xx.s) before to branch to application main.
00058        To reconfigure the default setting of SystemInit() function, refer to
00059        system_stm32f10x.c file
00060      */
00061
00062   /* System Clocks Configuration */
00063   RCC_Configuration();
00064
00065   /* Configure the GPIO ports */
00066   GPIO_Configuration();
00067
00068   /* TIM4 configuration: One Pulse mode ------------------------
00069      The external signal is connected to TIM4_CH2 pin (PB.07),
00070      The Rising edge is used as active edge,
00071      The One Pulse signal is output on TIM4_CH1 pin (PB.06)
00072      The TIM_Pulse defines the delay value
00073      The (TIM_Period -  TIM_Pulse) defines the One Pulse value.
00074      TIM2CLK = SystemCoreClock, we want to get TIM2 counter clock at 24 MHz:
00075      - Prescaler = (TIM2CLK / TIM2 counter clock) - 1
00076      The Autoreload value is 65535 (TIM4->ARR), so the maximum frequency value
00077      to trigger the TIM4 input is 24000000/65535 = 300 Hz.
00078
00079      The TIM_Pulse defines the delay value, the delay value is fixed
00080      to 682.6 us:
00081      delay =  CCR1/TIM4 counter clock = 682.6 us.
00082      The (TIM_Period - TIM_Pulse) defines the One Pulse value,
00083      the pulse value is fixed to 2.048 ms:
00084      One Pulse value = (TIM_Period - TIM_Pulse) / TIM4 counter clock = 2.048 ms.
00085
00086   * SystemCoreClock is set to 72 MHz for Low-density, Medium-density, High-density
00087     and Connectivity line devices and to 24 MHz for Value line devices
00088   ------------------------------------------------------------ */
00089
00090   /* Compute the prescaler value */
00091   PrescalerValue = (uint16_t) (SystemCoreClock / 24000000) - 1;
00092   /* Time base configuration */
00093   TIM_TimeBaseStructure.TIM_Period = 65535;
00094   TIM_TimeBaseStructure.TIM_Prescaler = PrescalerValue;
00095   TIM_TimeBaseStructure.TIM_ClockDivision = 0;
00096   TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
00097
00098   TIM_TimeBaseInit(TIM4, &TIM_TimeBaseStructure);
00099
00100   /* TIM4 PWM2 Mode configuration: Channel1 */
00101   TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM2;
00102   TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
00103   TIM_OCInitStructure.TIM_Pulse = 16383;
00104   TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High;
00105
00106   TIM_OC1Init(TIM4, &TIM_OCInitStructure);
00107
00108   /* TIM4 configuration in Input Capture Mode */
00109
00110   TIM_ICStructInit(&TIM_ICInitStructure);
00111
00112   TIM_ICInitStructure.TIM_Channel = TIM_Channel_2;
00113   TIM_ICInitStructure.TIM_ICPolarity = TIM_ICPolarity_Rising;
00114   TIM_ICInitStructure.TIM_ICSelection = TIM_ICSelection_DirectTI;
00115   TIM_ICInitStructure.TIM_ICPrescaler = TIM_ICPSC_DIV1;
00116   TIM_ICInitStructure.TIM_ICFilter = 0;
00117
00118   TIM_ICInit(TIM4, &TIM_ICInitStructure);
00119
00120   /* One Pulse Mode selection */
00121   TIM_SelectOnePulseMode(TIM4, TIM_OPMode_Single);
00122
00123   /* Input Trigger selection */
00124   TIM_SelectInputTrigger(TIM4, TIM_TS_TI2FP2);
00125
00126   /* Slave Mode selection: Trigger Mode */
00127   TIM_SelectSlaveMode(TIM4, TIM_SlaveMode_Trigger);
00128
00129   while (1)
00130   {}
00131 }
00132
00133 /**
00134   * @brief  Configures the different system clocks.
00135   * @param  None
00136   * @retval None
00137   */
00138 void RCC_Configuration(void)
00139 {
00140   /* TIM4 clock enable */
00141   RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM4, ENABLE);
00142
00143   /* GPIOB clock enable */
00144   RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE);
00145 }
00146
00147 /**
00148   * @brief  Configure the GPIOD Pins.
00149   * @param  None
00150   * @retval None
00151   */
00152 void GPIO_Configuration(void)
00153 {
00154   GPIO_InitTypeDef GPIO_InitStructure;
00155
00156   /* TIM4_CH1 pin (PB.06) configuration */
00157   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
00158   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
00159   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00160
00161   GPIO_Init(GPIOB, &GPIO_InitStructure);
00162
00163   /* TIM4_CH2 pin (PB.07) configuration */
00164   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7;
00165   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
00166
00167   GPIO_Init(GPIOB, &GPIO_InitStructure);
00168 }
00169
00170 #ifdef  USE_FULL_ASSERT
00171
00172 /**
00173   * @brief  Reports the name of the source file and the source line number
00174   *         where the assert_param error has occurred.
00175   * @param  file: pointer to the source file name
00176   * @param  line: assert_param error line source number
00177   * @retval None
00178   */
00179 void assert_failed(uint8_t* file, uint32_t line)
00180 {
00181   /* User can add his own implementation to report the file name and line number,
00182      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00183
00184   while (1)
00185   {}
00186 }
00187
00188 #endif
00189
00190 /**
00191   * @}
00192   */
00193
00194 /**
00195   * @}
00196   */
00197
00198 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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STM32F10x_StdPeriph_Examples/TIM/OnePulse/stm32f10x_conf.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    TIM/OnePulse/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052 /* Exported types ------------------------------------------------------------*/
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Uncomment the line below to expanse the "assert_param" macro in the
00055    Standard Peripheral Library drivers code */
00056 /* #define USE_FULL_ASSERT    1 */
00057
00058 /* Exported macro ------------------------------------------------------------*/
00059 #ifdef  USE_FULL_ASSERT
00060
00061 /**
00062   * @brief  The assert_param macro is used for function's parameters check.
00063   * @param  expr: If expr is false, it calls assert_failed function which reports
00064   *         the name of the source file and the source line number of the call
00065   *         that failed. If expr is true, it returns no value.
00066   * @retval None
00067   */
00068   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00069 /* Exported functions ------------------------------------------------------- */
00070   void assert_failed(uint8_t* file, uint32_t line);
00071 #else
00072   #define assert_param(expr) ((void)0)
00073 #endif /* USE_FULL_ASSERT */
00074
00075 #endif /* __STM32F10x_CONF_H */
00076
00077 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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STM32F10x_StdPeriph_Examples/TIM/OnePulse/stm32f10x_it.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    TIM/OnePulse/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *        This file provides template for all exceptions handler and
00009   *        peripherals interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026
00027 /** @addtogroup STM32F10x_StdPeriph_Examples
00028   * @{
00029   */
00030
00031 /** @addtogroup TIM_OnePulse
00032   * @{
00033   */
00034
00035 /* Private typedef -----------------------------------------------------------*/
00036 /* Private define ------------------------------------------------------------*/
00037 /* Private macro -------------------------------------------------------------*/
00038 /* Private variables ---------------------------------------------------------*/
00039 /* Private function prototypes -----------------------------------------------*/
00040 /* Private functions ---------------------------------------------------------*/
00041
00042 /******************************************************************************/
00043 /*            Cortex-M3 Processor Exceptions Handlers                         */
00044 /******************************************************************************/
00045
00046 /**
00047   * @brief  This function handles NMI exception.
00048   * @param  None
00049   * @retval None
00050   */
00051 void NMI_Handler(void)
00052 {}
00053
00054 /**
00055   * @brief  This function handles Hard Fault exception.
00056   * @param  None
00057   * @retval None
00058   */
00059 void HardFault_Handler(void)
00060 {
00061   /* Go to infinite loop when Hard Fault exception occurs */
00062   while (1)
00063   {}
00064 }
00065
00066 /**
00067   * @brief  This function handles Memory Manage exception.
00068   * @param  None
00069   * @retval None
00070   */
00071 void MemManage_Handler(void)
00072 {
00073   /* Go to infinite loop when Memory Manage exception occurs */
00074   while (1)
00075   {}
00076 }
00077
00078 /**
00079   * @brief  This function handles Bus Fault exception.
00080   * @param  None
00081   * @retval None
00082   */
00083 void BusFault_Handler(void)
00084 {
00085   /* Go to infinite loop when Bus Fault exception occurs */
00086   while (1)
00087   {}
00088 }
00089
00090 /**
00091   * @brief  This function handles Usage Fault exception.
00092   * @param  None
00093   * @retval None
00094   */
00095 void UsageFault_Handler(void)
00096 {
00097   /* Go to infinite loop when Usage Fault exception occurs */
00098   while (1)
00099   {}
00100 }
00101
00102 /**
00103   * @brief  This function handles Debug Monitor exception.
00104   * @param  None
00105   * @retval None
00106   */
00107 void DebugMon_Handler(void)
00108 {}
00109
00110 /**
00111   * @brief  This function handles SVCall exception.
00112   * @param  None
00113   * @retval None
00114   */
00115 void SVC_Handler(void)
00116 {}
00117
00118 /**
00119   * @brief  This function handles PendSV_Handler exception.
00120   * @param  None
00121   * @retval None
00122   */
00123 void PendSV_Handler(void)
00124 {}
00125
00126 /**
00127   * @brief  This function handles SysTick Handler.
00128   * @param  None
00129   * @retval None
00130   */
00131 void SysTick_Handler(void)
00132 {}
00133
00134 /******************************************************************************/
00135 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00136 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00137 /*  available peripheral interrupt handler's name please refer to the startup */
00138 /*  file (startup_stm32f10x_xx.s).                                            */
00139 /******************************************************************************/
00140
00141 /**
00142   * @brief  This function handles PPP interrupt request.
00143   * @param  None
00144   * @retval None
00145   */
00146 /*void PPP_IRQHandler(void)
00147 {
00148 }*/
00149
00150 /**
00151   * @}
00152   */
00153
00154 /**
00155   * @}
00156   */
00157
00158 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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STM32F10x_StdPeriph_Examples/TIM/OnePulse/stm32f10x_it.h

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00001 /**
00002   ******************************************************************************
00003   * @file    TIM/OnePulse/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043
00044 #endif /* __STM32F10x_IT_H */
00045
00046 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/main.c

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00001 /**
00002   ******************************************************************************
00003   * @file    TIM/Parallel_Synchro/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x.h"
00024
00025 /** @addtogroup STM32F10x_StdPeriph_Examples
00026   * @{
00027   */
00028
00029 /** @addtogroup TIM_Parallel_Synchro
00030   * @{
00031   */
00032
00033 /* Private typedef -----------------------------------------------------------*/
00034 /* Private define ------------------------------------------------------------*/
00035 /* Private macro -------------------------------------------------------------*/
00036 /* Private variables ---------------------------------------------------------*/
00037 TIM_TimeBaseInitTypeDef  TIM_TimeBaseStructure;
00038 TIM_OCInitTypeDef  TIM_OCInitStructure;
00039
00040 /* Private function prototypes -----------------------------------------------*/
00041 void RCC_Configuration(void);
00042 void GPIO_Configuration(void);
00043
00044 /* Private functions ---------------------------------------------------------*/
00045
00046 /**
00047   * @brief  Main program
00048   * @param  None
00049   * @retval None
00050   */
00051 int main(void)
00052 {
00053   /*!< At this stage the microcontroller clock setting is already configured,
00054        this is done through SystemInit() function which is called from startup
00055        file (startup_stm32f10x_xx.s) before to branch to application main.
00056        To reconfigure the default setting of SystemInit() function, refer to
00057        system_stm32f10x.c file
00058      */
00059
00060   /* System Clocks Configuration */
00061   RCC_Configuration();
00062
00063   /* GPIO Configuration */
00064   GPIO_Configuration();
00065
00066   /* Timers synchronisation in parallel mode ----------------------------
00067      1/TIM2 is configured as Master Timer:
00068      - PWM Mode is used
00069      - The TIM2 Update event is used as Trigger Output
00070      2/TIM3 and TIM4 are slaves for TIM2,
00071      - PWM Mode is used
00072      - The ITR1(TIM2) is used as input trigger for both slaves
00073      - Gated mode is used, so starts and stops of slaves counters
00074       are controlled by the Master trigger output signal(update event).
00075
00076   * For Low-density, Medium-density, High-density and Connectivity line devices:
00077      The TIMxCLK is fixed to 72 MHz, the TIM2 counter clock is 72 MHz.
00078      The Master Timer TIM2 is running at 281.250 KHz and the duty cycle
00079      is equal to 25%
00080      The TIM3 is running:
00081      - At (TIM2 frequency)/ (TIM3 period + 1) = 28.125 KHz and a duty cycle
00082      equal to TIM3_CCR1/(TIM3_ARR + 1) = 30%
00083      The TIM4 is running:
00084      - At (TIM2 frequency)/ (TIM4 period + 1) = 56.250 KHz and a duty cycle
00085      equal to TIM4_CCR1/(TIM4_ARR + 1) = 60%
00086
00087   * For Value line devices:
00088      The TIMxCLK is fixed to 24 MHz, the TIM2 counter clock is 24 MHz.
00089      TIM2 frequency = 93.750 KHz,
00090      TIM3 frequency = 23.437 KHz,
00091      TIM4 frequency = 18.75 KHz
00092   -------------------------------------------------------------------- */
00093
00094   /* Time base configuration */
00095   TIM_TimeBaseStructure.TIM_Period = 255;
00096   TIM_TimeBaseStructure.TIM_Prescaler = 0;
00097   TIM_TimeBaseStructure.TIM_ClockDivision = 0;
00098   TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
00099
00100   TIM_TimeBaseInit(TIM2, &TIM_TimeBaseStructure);
00101
00102   TIM_TimeBaseStructure.TIM_Period = 9;
00103   TIM_TimeBaseInit(TIM3, &TIM_TimeBaseStructure);
00104
00105   TIM_TimeBaseStructure.TIM_Period = 4;
00106   TIM_TimeBaseInit(TIM4, &TIM_TimeBaseStructure);
00107
00108   /* Master Configuration in PWM1 Mode */
00109   TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1;
00110   TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
00111   TIM_OCInitStructure.TIM_Pulse = 64;
00112   TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High;
00113
00114   TIM_OC1Init(TIM2, &TIM_OCInitStructure);
00115
00116   /* Select the Master Slave Mode */
00117   TIM_SelectMasterSlaveMode(TIM2, TIM_MasterSlaveMode_Enable);
00118
00119   /* Master Mode selection */
00120   TIM_SelectOutputTrigger(TIM2, TIM_TRGOSource_Update);
00121
00122   /* Slaves Configuration: PWM1 Mode */
00123   TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1;
00124   TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
00125   TIM_OCInitStructure.TIM_Pulse = 3;
00126
00127   TIM_OC1Init(TIM3, &TIM_OCInitStructure);
00128
00129   TIM_OC1Init(TIM4, &TIM_OCInitStructure);
00130
00131   /* Slave Mode selection: TIM3 */
00132   TIM_SelectSlaveMode(TIM3, TIM_SlaveMode_Gated);
00133   TIM_SelectInputTrigger(TIM3, TIM_TS_ITR1);
00134
00135   /* Slave Mode selection: TIM4 */
00136   TIM_SelectSlaveMode(TIM4, TIM_SlaveMode_Gated);
00137   TIM_SelectInputTrigger(TIM4, TIM_TS_ITR1);
00138
00139   /* TIM enable counter */
00140   TIM_Cmd(TIM3, ENABLE);
00141   TIM_Cmd(TIM2, ENABLE);
00142   TIM_Cmd(TIM4, ENABLE);
00143
00144   while (1)
00145   {}
00146 }
00147
00148 /**
00149   * @brief  Configures the different system clocks.
00150   * @param  None
00151   * @retval None
00152   */
00153 void RCC_Configuration(void)
00154 {
00155   /* TIM2, TIM3 and TIM4 clock enable */
00156   RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2 | RCC_APB1Periph_TIM3 |
00157                          RCC_APB1Periph_TIM4, ENABLE);
00158
00159   /* GPIOA, GPIOB, GPIOC and AFIO clocks enable */
00160   RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB |
00161                          RCC_APB2Periph_GPIOC | RCC_APB2Periph_AFIO, ENABLE);
00162 }
00163
00164 /**
00165   * @brief  Configure the GPIO Pins.
00166   * @param  None
00167   * @retval None
00168   */
00169 void GPIO_Configuration(void)
00170 {
00171   GPIO_InitTypeDef GPIO_InitStructure;
00172
00173 #ifdef STM32F10X_CL
00174   /*GPIOB Configuration:  PC6(TIM3 CH1) as alternate function push-pull */
00175   GPIO_InitStructure.GPIO_Pin =  GPIO_Pin_6 ;
00176   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
00177   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00178
00179   GPIO_Init(GPIOC, &GPIO_InitStructure);
00180
00181   GPIO_PinRemapConfig(GPIO_FullRemap_TIM3, ENABLE);
00182
00183 #else
00184 /* GPIOA Configuration: PA6(TIM3 CH1) as alternate function push-pull */
00185   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
00186   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
00187   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00188
00189   GPIO_Init(GPIOA, &GPIO_InitStructure);
00190 #endif
00191   /* GPIOA Configuration: PA0(TIM2 CH1) as alternate function push-pull */
00192   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0;
00193   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
00194   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00195
00196   GPIO_Init(GPIOA, &GPIO_InitStructure);
00197
00198   /* GPIOB Configuration: PB6(TIM4 CH1) as alternate function push-pull */
00199   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
00200
00201   GPIO_Init(GPIOB, &GPIO_InitStructure);
00202 }
00203
00204 #ifdef  USE_FULL_ASSERT
00205
00206 /**
00207   * @brief  Reports the name of the source file and the source line number
00208   *         where the assert_param error has occurred.
00209   * @param  file: pointer to the source file name
00210   * @param  line: assert_param error line source number
00211   * @retval None
00212   */
00213 void assert_failed(uint8_t* file, uint32_t line)
00214 {
00215   /* User can add his own implementation to report the file name and line number,
00216      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00217
00218   while (1)
00219   {}
00220 }
00221
00222 #endif
00223
00224 /**
00225   * @}
00226   */
00227
00228 /**
00229   * @}
00230   */
00231
00232 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/stm32f10x_conf.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    TIM/Parallel_Synchro/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052 /* Exported types ------------------------------------------------------------*/
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Uncomment the line below to expanse the "assert_param" macro in the
00055    Standard Peripheral Library drivers code */
00056 /* #define USE_FULL_ASSERT    1 */
00057
00058 /* Exported macro ------------------------------------------------------------*/
00059 #ifdef  USE_FULL_ASSERT
00060
00061 /**
00062   * @brief  The assert_param macro is used for function's parameters check.
00063   * @param  expr: If expr is false, it calls assert_failed function which reports
00064   *         the name of the source file and the source line number of the call
00065   *         that failed. If expr is true, it returns no value.
00066   * @retval None
00067   */
00068   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00069 /* Exported functions ------------------------------------------------------- */
00070   void assert_failed(uint8_t* file, uint32_t line);
00071 #else
00072   #define assert_param(expr) ((void)0)
00073 #endif /* USE_FULL_ASSERT */
00074
00075 #endif /* __STM32F10x_CONF_H */
00076
00077 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/stm32f10x_it.c

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00001 /**
00002   ******************************************************************************
00003   * @file    TIM/Parallel_Synchro/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *         This file provides template for all exceptions handler and
00009   *         peripherals interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026
00027 /** @addtogroup STM32F10x_StdPeriph_Examples
00028   * @{
00029   */
00030
00031 /** @addtogroup TIM_Parallel_Synchro
00032   * @{
00033   */
00034
00035 /* Private typedef -----------------------------------------------------------*/
00036 /* Private define ------------------------------------------------------------*/
00037 /* Private macro -------------------------------------------------------------*/
00038 /* Private variables ---------------------------------------------------------*/
00039 /* Private function prototypes -----------------------------------------------*/
00040 /* Private functions ---------------------------------------------------------*/
00041
00042 /******************************************************************************/
00043 /*            Cortex-M3 Processor Exceptions Handlers                         */
00044 /******************************************************************************/
00045
00046 /**
00047   * @brief  This function handles NMI exception.
00048   * @param  None
00049   * @retval None
00050   */
00051 void NMI_Handler(void)
00052 {
00053 }
00054
00055 /**
00056   * @brief  This function handles Hard Fault exception.
00057   * @param  None
00058   * @retval None
00059   */
00060 void HardFault_Handler(void)
00061 {
00062   /* Go to infinite loop when Hard Fault exception occurs */
00063   while (1)
00064   {}
00065 }
00066
00067 /**
00068   * @brief  This function handles Memory Manage exception.
00069   * @param  None
00070   * @retval None
00071   */
00072 void MemManage_Handler(void)
00073 {
00074   /* Go to infinite loop when Memory Manage exception occurs */
00075   while (1)
00076   {}
00077 }
00078
00079 /**
00080   * @brief  This function handles Bus Fault exception.
00081   * @param  None
00082   * @retval None
00083   */
00084 void BusFault_Handler(void)
00085 {
00086   /* Go to infinite loop when Bus Fault exception occurs */
00087   while (1)
00088   {}
00089 }
00090
00091 /**
00092   * @brief  This function handles Usage Fault exception.
00093   * @param  None
00094   * @retval None
00095   */
00096 void UsageFault_Handler(void)
00097 {
00098   /* Go to infinite loop when Usage Fault exception occurs */
00099   while (1)
00100   {}
00101 }
00102
00103 /**
00104   * @brief  This function handles Debug Monitor exception.
00105   * @param  None
00106   * @retval None
00107   */
00108 void DebugMon_Handler(void)
00109 {}
00110
00111 /**
00112   * @brief  This function handles SVCall exception.
00113   * @param  None
00114   * @retval None
00115   */
00116 void SVC_Handler(void)
00117 {}
00118
00119 /**
00120   * @brief  This function handles PendSV_Handler exception.
00121   * @param  None
00122   * @retval None
00123   */
00124 void PendSV_Handler(void)
00125 {}
00126
00127 /**
00128   * @brief  This function handles SysTick Handler.
00129   * @param  None
00130   * @retval None
00131   */
00132 void SysTick_Handler(void)
00133 {}
00134
00135 /******************************************************************************/
00136 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00137 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00138 /*  available peripheral interrupt handler's name please refer to the startup */
00139 /*  file (startup_stm32f10x_xx.s).                                            */
00140 /******************************************************************************/
00141
00142 /**
00143   * @brief  This function handles PPP interrupt request.
00144   * @param  None
00145   * @retval None
00146   */
00147 /*void PPP_IRQHandler(void)
00148 {
00149 }*/
00150
00151 /**
00152   * @}
00153   */
00154
00155 /**
00156   * @}
00157   */
00158
00159 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/stm32f10x_it.h

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00001 /**
00002   ******************************************************************************
00003   * @file    TIM/Parallel_Synchro/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043
00044 #endif /* __STM32F10x_IT_H */
00045
00046 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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STM32F10x_StdPeriph_Examples/TIM/PWM_Input/main.c

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00001 /**
00002   ******************************************************************************
00003   * @file    TIM/PWM_Input/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x.h"
00024
00025 /** @addtogroup STM32F10x_StdPeriph_Examples
00026   * @{
00027   */
00028
00029 /** @addtogroup TIM_PWM_Input
00030   * @{
00031   */
00032
00033 /* Private typedef -----------------------------------------------------------*/
00034 /* Private define ------------------------------------------------------------*/
00035 /* Private macro -------------------------------------------------------------*/
00036 /* Private variables ---------------------------------------------------------*/
00037 TIM_ICInitTypeDef  TIM_ICInitStructure;
00038
00039 /* Private function prototypes -----------------------------------------------*/
00040 void RCC_Configuration(void);
00041 void GPIO_Configuration(void);
00042 void NVIC_Configuration(void);
00043
00044 /* Private functions ---------------------------------------------------------*/
00045
00046 /**
00047   * @brief   Main program
00048   * @param  None
00049   * @retval None
00050   */
00051 int main(void)
00052 {
00053   /*!< At this stage the microcontroller clock setting is already configured,
00054        this is done through SystemInit() function which is called from startup
00055        file (startup_stm32f10x_xx.s) before to branch to application main.
00056        To reconfigure the default setting of SystemInit() function, refer to
00057        system_stm32f10x.c file
00058      */
00059
00060   /* System Clocks Configuration */
00061   RCC_Configuration();
00062
00063   /* NVIC configuration */
00064   NVIC_Configuration();
00065
00066   /* Configure the GPIO ports */
00067   GPIO_Configuration();
00068
00069   /* TIM3 configuration: PWM Input mode ------------------------
00070      The external signal is connected to TIM3 CH2 pin (PA.01),
00071      The Rising edge is used as active edge,
00072      The TIM3 CCR2 is used to compute the frequency value
00073      The TIM3 CCR1 is used to compute the duty cycle value
00074   ------------------------------------------------------------ */
00075
00076   TIM_ICInitStructure.TIM_Channel = TIM_Channel_2;
00077   TIM_ICInitStructure.TIM_ICPolarity = TIM_ICPolarity_Rising;
00078   TIM_ICInitStructure.TIM_ICSelection = TIM_ICSelection_DirectTI;
00079   TIM_ICInitStructure.TIM_ICPrescaler = TIM_ICPSC_DIV1;
00080   TIM_ICInitStructure.TIM_ICFilter = 0x0;
00081
00082   TIM_PWMIConfig(TIM3, &TIM_ICInitStructure);
00083
00084   /* Select the TIM3 Input Trigger: TI2FP2 */
00085   TIM_SelectInputTrigger(TIM3, TIM_TS_TI2FP2);
00086
00087   /* Select the slave Mode: Reset Mode */
00088   TIM_SelectSlaveMode(TIM3, TIM_SlaveMode_Reset);
00089
00090   /* Enable the Master/Slave Mode */
00091   TIM_SelectMasterSlaveMode(TIM3, TIM_MasterSlaveMode_Enable);
00092
00093   /* TIM enable counter */
00094   TIM_Cmd(TIM3, ENABLE);
00095
00096   /* Enable the CC2 Interrupt Request */
00097   TIM_ITConfig(TIM3, TIM_IT_CC2, ENABLE);
00098
00099   while (1);
00100 }
00101
00102 /**
00103   * @brief  Configures the different system clocks.
00104   * @param  None
00105   * @retval None
00106   */
00107 void RCC_Configuration(void)
00108 {
00109   /* TIM3 clock enable */
00110   RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM3, ENABLE);
00111
00112   /* GPIOA clock enable */
00113   RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);
00114 }
00115
00116 /**
00117   * @brief  Configure the GPIO Pins.
00118   * @param  None
00119   * @retval None
00120   */
00121 void GPIO_Configuration(void)
00122 {
00123   GPIO_InitTypeDef GPIO_InitStructure;
00124
00125   /* TIM3 channel 2 pin (PA.07) configuration */
00126   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7;
00127   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
00128   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00129
00130   GPIO_Init(GPIOA, &GPIO_InitStructure);
00131 }
00132
00133 /**
00134   * @brief  Configure the nested vectored interrupt controller.
00135   * @param  None
00136   * @retval None
00137   */
00138 void NVIC_Configuration(void)
00139 {
00140   NVIC_InitTypeDef NVIC_InitStructure;
00141
00142   /* Enable the TIM3 global Interrupt */
00143   NVIC_InitStructure.NVIC_IRQChannel = TIM3_IRQn;
00144   NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
00145   NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;
00146   NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
00147   NVIC_Init(&NVIC_InitStructure);
00148 }
00149
00150 #ifdef  USE_FULL_ASSERT
00151
00152 /**
00153   * @brief  Reports the name of the source file and the source line number
00154   *         where the assert_param error has occurred.
00155   * @param  file: pointer to the source file name
00156   * @param  line: assert_param error line source number
00157   * @retval None
00158   */
00159 void assert_failed(uint8_t* file, uint32_t line)
00160 {
00161   /* User can add his own implementation to report the file name and line number,
00162      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00163
00164   while (1)
00165   {}
00166 }
00167
00168 #endif
00169
00170 /**
00171   * @}
00172   */
00173
00174 /**
00175   * @}
00176   */
00177
00178 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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STM32F10x_StdPeriph_Examples/TIM/PWM_Input/stm32f10x_conf.h

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00001 /**
00002   ******************************************************************************
00003   * @file    TIM/PWM_Input/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052 /* Exported types ------------------------------------------------------------*/
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Uncomment the line below to expanse the "assert_param" macro in the
00055    Standard Peripheral Library drivers code */
00056 /* #define USE_FULL_ASSERT    1 */
00057
00058 /* Exported macro ------------------------------------------------------------*/
00059 #ifdef  USE_FULL_ASSERT
00060
00061 /**
00062   * @brief  The assert_param macro is used for function's parameters check.
00063   * @param  expr: If expr is false, it calls assert_failed function which reports
00064   *         the name of the source file and the source line number of the call
00065   *         that failed. If expr is true, it returns no value.
00066   * @retval None
00067   */
00068   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00069 /* Exported functions ------------------------------------------------------- */
00070   void assert_failed(uint8_t* file, uint32_t line);
00071 #else
00072   #define assert_param(expr) ((void)0)
00073 #endif /* USE_FULL_ASSERT */
00074
00075 #endif /* __STM32F10x_CONF_H */
00076
00077 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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STM32F10x_StdPeriph_Examples/TIM/PWM_Input/stm32f10x_it.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    TIM/PWM_Input/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and peripherals
00009   *          interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026
00027 /** @addtogroup STM32F10x_StdPeriph_Examples
00028   * @{
00029   */
00030
00031 /** @addtogroup TIM_PWM_Input
00032   * @{
00033   */
00034
00035 /* Private typedef -----------------------------------------------------------*/
00036 /* Private define ------------------------------------------------------------*/
00037 /* Private macro -------------------------------------------------------------*/
00038 /* Private variables ---------------------------------------------------------*/
00039 __IO uint16_t IC2Value = 0;
00040 __IO uint16_t DutyCycle = 0;
00041 __IO uint32_t Frequency = 0;
00042
00043 /* Private function prototypes -----------------------------------------------*/
00044 /* Private functions ---------------------------------------------------------*/
00045
00046 /******************************************************************************/
00047 /*            Cortex-M3 Processor Exceptions Handlers                         */
00048 /******************************************************************************/
00049
00050 /**
00051   * @brief  This function handles NMI exception.
00052   * @param  None
00053   * @retval None
00054   */
00055 void NMI_Handler(void)
00056 {
00057 }
00058
00059 /**
00060   * @brief  This function handles Hard Fault exception.
00061   * @param  None
00062   * @retval None
00063   */
00064 void HardFault_Handler(void)
00065 {
00066   /* Go to infinite loop when Hard Fault exception occurs */
00067   while (1)
00068   {}
00069 }
00070
00071 /**
00072   * @brief  This function handles Memory Manage exception.
00073   * @param  None
00074   * @retval None
00075   */
00076 void MemManage_Handler(void)
00077 {
00078   /* Go to infinite loop when Memory Manage exception occurs */
00079   while (1)
00080   {}
00081 }
00082
00083 /**
00084   * @brief  This function handles Bus Fault exception.
00085   * @param  None
00086   * @retval None
00087   */
00088 void BusFault_Handler(void)
00089 {
00090   /* Go to infinite loop when Bus Fault exception occurs */
00091   while (1)
00092   {}
00093 }
00094
00095 /**
00096   * @brief  This function handles Usage Fault exception.
00097   * @param  None
00098   * @retval None
00099   */
00100 void UsageFault_Handler(void)
00101 {
00102   /* Go to infinite loop when Usage Fault exception occurs */
00103   while (1)
00104   {}
00105 }
00106
00107 /**
00108   * @brief  This function handles Debug Monitor exception.
00109   * @param  None
00110   * @retval None
00111   */
00112 void DebugMon_Handler(void)
00113 {}
00114
00115 /**
00116   * @brief  This function handles SVCall exception.
00117   * @param  None
00118   * @retval None
00119   */
00120 void SVC_Handler(void)
00121 {}
00122
00123 /**
00124   * @brief  This function handles PendSV_Handler exception.
00125   * @param  None
00126   * @retval None
00127   */
00128 void PendSV_Handler(void)
00129 {}
00130
00131 /**
00132   * @brief  This function handles SysTick Handler.
00133   * @param  None
00134   * @retval None
00135   */
00136 void SysTick_Handler(void)
00137 {}
00138
00139 /******************************************************************************/
00140 /*            STM32F10x Peripherals Interrupt Handlers                        */
00141 /******************************************************************************/
00142
00143 /**
00144   * @brief  This function handles TIM3 global interrupt request.
00145   * @param  None
00146   * @retval None
00147   */
00148 void TIM3_IRQHandler(void)
00149 {
00150   /* Clear TIM3 Capture compare interrupt pending bit */
00151   TIM_ClearITPendingBit(TIM3, TIM_IT_CC2);
00152
00153   /* Get the Input Capture value */
00154   IC2Value = TIM_GetCapture2(TIM3);
00155
00156   if (IC2Value != 0)
00157   {
00158     /* Duty cycle computation */
00159     DutyCycle = (TIM_GetCapture1(TIM3) * 100) / IC2Value;
00160
00161     /* Frequency computation */
00162     Frequency = SystemCoreClock / IC2Value;
00163   }
00164   else
00165   {
00166     DutyCycle = 0;
00167     Frequency = 0;
00168   }
00169 }
00170
00171 /******************************************************************************/
00172 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00173 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00174 /*  available peripheral interrupt handler's name please refer to the startup */
00175 /*  file (startup_stm32f10x_xx.s).                                            */
00176 /******************************************************************************/
00177
00178 /**
00179   * @brief  This function handles PPP interrupt request.
00180   * @param  None
00181   * @retval None
00182   */
00183 /*void PPP_IRQHandler(void)
00184 {
00185 }*/
00186
00187 /**
00188   * @}
00189   */
00190
00191 /**
00192   * @}
00193   */
00194
00195 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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STM32F10x_StdPeriph_Examples/TIM/PWM_Input/stm32f10x_it.h

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00001 /**
00002   ******************************************************************************
00003   * @file    TIM/PWM_Input/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043 void TIM3_IRQHandler(void);
00044
00045 #endif /* __STM32F10x_IT_H */
00046
00047 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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STM32F10x_StdPeriph_Examples/TIM/PWM_Output/main.c

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00001 /**
00002   ******************************************************************************
00003   * @file    TIM/PWM_Output/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x.h"
00024
00025 /** @addtogroup STM32F10x_StdPeriph_Examples
00026   * @{
00027   */
00028
00029 /** @addtogroup TIM_PWM_Output
00030   * @{
00031   */
00032
00033 /* Private typedef -----------------------------------------------------------*/
00034 /* Private define ------------------------------------------------------------*/
00035 /* Private macro -------------------------------------------------------------*/
00036 /* Private variables ---------------------------------------------------------*/
00037 TIM_TimeBaseInitTypeDef  TIM_TimeBaseStructure;
00038 TIM_OCInitTypeDef  TIM_OCInitStructure;
00039 uint16_t CCR1_Val = 333;
00040 uint16_t CCR2_Val = 249;
00041 uint16_t CCR3_Val = 166;
00042 uint16_t CCR4_Val = 83;
00043 uint16_t PrescalerValue = 0;
00044
00045 /* Private function prototypes -----------------------------------------------*/
00046 void RCC_Configuration(void);
00047 void GPIO_Configuration(void);
00048
00049 /* Private functions ---------------------------------------------------------*/
00050
00051 /**
00052   * @brief  Main program
00053   * @param  None
00054   * @retval None
00055   */
00056 int main(void)
00057 {
00058   /*!< At this stage the microcontroller clock setting is already configured,
00059        this is done through SystemInit() function which is called from startup
00060        file (startup_stm32f10x_xx.s) before to branch to application main.
00061        To reconfigure the default setting of SystemInit() function, refer to
00062        system_stm32f10x.c file
00063      */
00064
00065   /* System Clocks Configuration */
00066   RCC_Configuration();
00067
00068   /* GPIO Configuration */
00069   GPIO_Configuration();
00070
00071   /* -----------------------------------------------------------------------
00072     TIM3 Configuration: generate 4 PWM signals with 4 different duty cycles:
00073     The TIM3CLK frequency is set to SystemCoreClock (Hz), to get TIM3 counter
00074     clock at 24 MHz the Prescaler is computed as following:
00075      - Prescaler = (TIM3CLK / TIM3 counter clock) - 1
00076     SystemCoreClock is set to 72 MHz for Low-density, Medium-density, High-density
00077     and Connectivity line devices and to 24 MHz for Low-Density Value line and
00078     Medium-Density Value line devices
00079
00080     The TIM3 is running at 36 KHz: TIM3 Frequency = TIM3 counter clock/(ARR + 1)
00081                                                   = 24 MHz / 666 = 36 KHz
00082     TIM3 Channel1 duty cycle = (TIM3_CCR1/ TIM3_ARR)* 100 = 50%
00083     TIM3 Channel2 duty cycle = (TIM3_CCR2/ TIM3_ARR)* 100 = 37.5%
00084     TIM3 Channel3 duty cycle = (TIM3_CCR3/ TIM3_ARR)* 100 = 25%
00085     TIM3 Channel4 duty cycle = (TIM3_CCR4/ TIM3_ARR)* 100 = 12.5%
00086   ----------------------------------------------------------------------- */
00087   /* Compute the prescaler value */
00088   PrescalerValue = (uint16_t) (SystemCoreClock / 24000000) - 1;
00089   /* Time base configuration */
00090   TIM_TimeBaseStructure.TIM_Period = 665;
00091   TIM_TimeBaseStructure.TIM_Prescaler = PrescalerValue;
00092   TIM_TimeBaseStructure.TIM_ClockDivision = 0;
00093   TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
00094
00095   TIM_TimeBaseInit(TIM3, &TIM_TimeBaseStructure);
00096
00097   /* PWM1 Mode configuration: Channel1 */
00098   TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1;
00099   TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
00100   TIM_OCInitStructure.TIM_Pulse = CCR1_Val;
00101   TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High;
00102
00103   TIM_OC1Init(TIM3, &TIM_OCInitStructure);
00104
00105   TIM_OC1PreloadConfig(TIM3, TIM_OCPreload_Enable);
00106
00107   /* PWM1 Mode configuration: Channel2 */
00108   TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
00109   TIM_OCInitStructure.TIM_Pulse = CCR2_Val;
00110
00111   TIM_OC2Init(TIM3, &TIM_OCInitStructure);
00112
00113   TIM_OC2PreloadConfig(TIM3, TIM_OCPreload_Enable);
00114
00115   /* PWM1 Mode configuration: Channel3 */
00116   TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
00117   TIM_OCInitStructure.TIM_Pulse = CCR3_Val;
00118
00119   TIM_OC3Init(TIM3, &TIM_OCInitStructure);
00120
00121   TIM_OC3PreloadConfig(TIM3, TIM_OCPreload_Enable);
00122
00123   /* PWM1 Mode configuration: Channel4 */
00124   TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
00125   TIM_OCInitStructure.TIM_Pulse = CCR4_Val;
00126
00127   TIM_OC4Init(TIM3, &TIM_OCInitStructure);
00128
00129   TIM_OC4PreloadConfig(TIM3, TIM_OCPreload_Enable);
00130
00131   TIM_ARRPreloadConfig(TIM3, ENABLE);
00132
00133   /* TIM3 enable counter */
00134   TIM_Cmd(TIM3, ENABLE);
00135
00136   while (1)
00137   {}
00138 }
00139
00140 /**
00141   * @brief  Configures the different system clocks.
00142   * @param  None
00143   * @retval None
00144   */
00145 void RCC_Configuration(void)
00146 {
00147   /* TIM3 clock enable */
00148   RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM3, ENABLE);
00149
00150   /* GPIOA and GPIOB clock enable */
00151   RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB |
00152                          RCC_APB2Periph_GPIOC | RCC_APB2Periph_AFIO, ENABLE);
00153 }
00154
00155 /**
00156   * @brief  Configure the TIM3 Ouput Channels.
00157   * @param  None
00158   * @retval None
00159   */
00160 void GPIO_Configuration(void)
00161 {
00162   GPIO_InitTypeDef GPIO_InitStructure;
00163
00164 #ifdef STM32F10X_CL
00165   /*GPIOB Configuration: TIM3 channel1, 2, 3 and 4 */
00166   GPIO_InitStructure.GPIO_Pin =  GPIO_Pin_6 | GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9;
00167   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
00168   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00169
00170   GPIO_Init(GPIOC, &GPIO_InitStructure);
00171
00172   GPIO_PinRemapConfig(GPIO_FullRemap_TIM3, ENABLE);
00173
00174 #else
00175   /* GPIOA Configuration:TIM3 Channel1, 2, 3 and 4 as alternate function push-pull */
00176   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6 | GPIO_Pin_7;
00177   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
00178   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00179
00180   GPIO_Init(GPIOA, &GPIO_InitStructure);
00181
00182   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1;
00183   GPIO_Init(GPIOB, &GPIO_InitStructure);
00184 #endif
00185 }
00186
00187 #ifdef  USE_FULL_ASSERT
00188
00189 /**
00190   * @brief  Reports the name of the source file and the source line number
00191   *         where the assert_param error has occurred.
00192   * @param  file: pointer to the source file name
00193   * @param  line: assert_param error line source number
00194   * @retval None
00195   */
00196 void assert_failed(uint8_t* file, uint32_t line)
00197 {
00198   /* User can add his own implementation to report the file name and line number,
00199      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00200
00201   while (1)
00202   {}
00203 }
00204
00205 #endif
00206
00207 /**
00208   * @}
00209   */
00210
00211 /**
00212   * @}
00213   */
00214
00215 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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STM32F10x_StdPeriph_Examples/TIM/PWM_Output/stm32f10x_conf.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    TIM/PWM_Output/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052 /* Exported types ------------------------------------------------------------*/
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Uncomment the line below to expanse the "assert_param" macro in the
00055    Standard Peripheral Library drivers code */
00056 /* #define USE_FULL_ASSERT    1 */
00057
00058 /* Exported macro ------------------------------------------------------------*/
00059 #ifdef  USE_FULL_ASSERT
00060
00061 /**
00062   * @brief  The assert_param macro is used for function's parameters check.
00063   * @param  expr: If expr is false, it calls assert_failed function which reports
00064   *         the name of the source file and the source line number of the call
00065   *         that failed. If expr is true, it returns no value.
00066   * @retval None
00067   */
00068   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00069 /* Exported functions ------------------------------------------------------- */
00070   void assert_failed(uint8_t* file, uint32_t line);
00071 #else
00072   #define assert_param(expr) ((void)0)
00073 #endif /* USE_FULL_ASSERT */
00074
00075 #endif /* __STM32F10x_CONF_H */
00076
00077 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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STM32F10x_StdPeriph_Examples/TIM/PWM_Output/stm32f10x_it.c

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00001 /**
00002   ******************************************************************************
00003   * @file    TIM/PWM_Output/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *         This file provides template for all exceptions handler and
00009   *         peripherals interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026
00027 /** @addtogroup STM32F10x_StdPeriph_Examples
00028   * @{
00029   */
00030
00031 /** @addtogroup TIM_PWM_Output
00032   * @{
00033   */
00034
00035 /* Private typedef -----------------------------------------------------------*/
00036 /* Private define ------------------------------------------------------------*/
00037 /* Private macro -------------------------------------------------------------*/
00038 /* Private variables ---------------------------------------------------------*/
00039 /* Private function prototypes -----------------------------------------------*/
00040 /* Private functions ---------------------------------------------------------*/
00041
00042 /******************************************************************************/
00043 /*            Cortex-M3 Processor Exceptions Handlers                         */
00044 /******************************************************************************/
00045
00046 /**
00047   * @brief  This function handles NMI exception.
00048   * @param  None
00049   * @retval None
00050   */
00051 void NMI_Handler(void)
00052 {
00053 }
00054
00055 /**
00056   * @brief  This function handles Hard Fault exception.
00057   * @param  None
00058   * @retval None
00059   */
00060 void HardFault_Handler(void)
00061 {
00062   /* Go to infinite loop when Hard Fault exception occurs */
00063   while (1)
00064   {}
00065 }
00066
00067 /**
00068   * @brief  This function handles Memory Manage exception.
00069   * @param  None
00070   * @retval None
00071   */
00072 void MemManage_Handler(void)
00073 {
00074   /* Go to infinite loop when Memory Manage exception occurs */
00075   while (1)
00076   {}
00077 }
00078
00079 /**
00080   * @brief  This function handles Bus Fault exception.
00081   * @param  None
00082   * @retval None
00083   */
00084 void BusFault_Handler(void)
00085 {
00086   /* Go to infinite loop when Bus Fault exception occurs */
00087   while (1)
00088   {}
00089 }
00090
00091 /**
00092   * @brief  This function handles Usage Fault exception.
00093   * @param  None
00094   * @retval None
00095   */
00096 void UsageFault_Handler(void)
00097 {
00098   /* Go to infinite loop when Usage Fault exception occurs */
00099   while (1)
00100   {}
00101 }
00102
00103 /**
00104   * @brief  This function handles Debug Monitor exception.
00105   * @param  None
00106   * @retval None
00107   */
00108 void DebugMon_Handler(void)
00109 {}
00110
00111 /**
00112   * @brief  This function handles SVCall exception.
00113   * @param  None
00114   * @retval None
00115   */
00116 void SVC_Handler(void)
00117 {}
00118
00119 /**
00120   * @brief  This function handles PendSV_Handler exception.
00121   * @param  None
00122   * @retval None
00123   */
00124 void PendSV_Handler(void)
00125 {}
00126
00127 /**
00128   * @brief  This function handles SysTick Handler.
00129   * @param  None
00130   * @retval None
00131   */
00132 void SysTick_Handler(void)
00133 {}
00134
00135 /******************************************************************************/
00136 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00137 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00138 /*  available peripheral interrupt handler's name please refer to the startup */
00139 /*  file (startup_stm32f10x_xx.s).                                            */
00140 /******************************************************************************/
00141
00142 /**
00143   * @brief  This function handles PPP interrupt request.
00144   * @param  None
00145   * @retval None
00146   */
00147 /*void PPP_IRQHandler(void)
00148 {
00149 }*/
00150
00151 /**
00152   * @}
00153   */
00154
00155 /**
00156   * @}
00157   */
00158
00159 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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STM32F10x_StdPeriph_Examples/TIM/PWM_Output/stm32f10x_it.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    TIM/PWM_Output/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043
00044 #endif /* __STM32F10x_IT_H */
00045
00046 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/main.c

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00001 /**
00002   ******************************************************************************
00003   * @file    TIM/TIM1_Synchro/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x.h"
00024
00025 /** @addtogroup STM32F10x_StdPeriph_Examples
00026   * @{
00027   */
00028
00029 /** @addtogroup TIM_TIM1_Synchro
00030   * @{
00031   */
00032
00033 /* Private typedef -----------------------------------------------------------*/
00034 /* Private define ------------------------------------------------------------*/
00035 /* Private macro -------------------------------------------------------------*/
00036 /* Private variables ---------------------------------------------------------*/
00037 TIM_TimeBaseInitTypeDef  TIM_TimeBaseStructure;
00038 TIM_OCInitTypeDef  TIM_OCInitStructure;
00039 TIM_BDTRInitTypeDef TIM_BDTRInitStructure;
00040
00041 /* Private function prototypes -----------------------------------------------*/
00042 void RCC_Configuration(void);
00043 void GPIO_Configuration(void);
00044
00045 /* Private functions ---------------------------------------------------------*/
00046
00047 /**
00048   * @brief   Main program
00049   * @param  None
00050   * @retval None
00051   */
00052 int main(void)
00053 {
00054   /*!< At this stage the microcontroller clock setting is already configured,
00055        this is done through SystemInit() function which is called from startup
00056        file (startup_stm32f10x_xx.s) before to branch to application main.
00057        To reconfigure the default setting of SystemInit() function, refer to
00058        system_stm32f10x.c file
00059      */
00060
00061   /* System Clocks Configuration */
00062   RCC_Configuration();
00063
00064   /* GPIO Configuration */
00065   GPIO_Configuration();
00066
00067   /* TIM1 and Timers(TIM3 and TIM4) synchronisation in parallel mode -----------
00068      1/TIM1 is configured as Master Timer:
00069      - PWM Mode is used
00070      - The TIM1 Update event is used as Trigger Output
00071
00072      2/TIM3 and TIM4 are slaves for TIM1,
00073      - PWM Mode is used
00074      - The ITR0(TIM1) is used as input trigger for both slaves
00075      - Gated mode is used, so starts and stops of slaves counters
00076        are controlled by the Master trigger output signal(update event).
00077
00078   o For Low-density, Medium-density, High-density and Connectivity line devices:
00079     The TIMxCLK is fixed to 72 MHz, Prescaler = 0 so the TIM1 counter clock is 72 MHz.
00080
00081     The Master Timer TIM1 is running at:
00082     TIM1 frequency = TIM1 counter clock / (TIM1_Period + 1) = 281.250 KHz
00083     and the duty cycle is equal to: TIM1_CCR1/(TIM1_ARR + 1) = 50%
00084
00085     The TIM3 is running at:
00086     (TIM1 frequency)/ ((TIM3 period +1)* (Repetition_Counter+1)) = 18.750 KHz and
00087     a duty cycle equal to TIM3_CCR1/(TIM3_ARR + 1) = 33.3%
00088
00089     The TIM4 is running at:
00090     (TIM1 frequency)/ ((TIM4 period +1)* (Repetition_Counter+1)) = 28.125 KHz and
00091     a duty cycle equal to TIM4_CCR1/(TIM4_ARR + 1) = 50%
00092
00093   o For Low-Density Value line and Medium-Density Value line devices:
00094     The TIMxCLK is fixed to 24 MHz, Prescaler = 0 so the TIM1 counter clock is 24 MHz.
00095     TIM1 frequency = 93.75 KHz
00096     TIM3 frequency = 6.25 KHz
00097     TIM4 frequency = 9.375 KHz
00098   --------------------------------------------------------------------------- */
00099
00100   /* TIM3 Peripheral Configuration ----------------------------------------*/
00101   /* TIM3 Slave Configuration: PWM1 Mode */
00102   TIM_TimeBaseStructure.TIM_Period = 2;
00103   TIM_TimeBaseStructure.TIM_Prescaler = 0;
00104   TIM_TimeBaseStructure.TIM_ClockDivision = 0;
00105   TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
00106
00107   TIM_TimeBaseInit(TIM3, &TIM_TimeBaseStructure);
00108
00109   TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1;
00110   TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
00111   TIM_OCInitStructure.TIM_Pulse = 1;
00112
00113   TIM_OC1Init(TIM3, &TIM_OCInitStructure);
00114
00115   /* Slave Mode selection: TIM3 */
00116   TIM_SelectSlaveMode(TIM3, TIM_SlaveMode_Gated);
00117   TIM_SelectInputTrigger(TIM3, TIM_TS_ITR0);
00118
00119   /* TIM4 Peripheral Configuration ----------------------------------------*/
00120   /* TIM4 Slave Configuration: PWM1 Mode */
00121   TIM_TimeBaseStructure.TIM_Period = 1;
00122   TIM_TimeBaseStructure.TIM_Prescaler = 0;
00123   TIM_TimeBaseStructure.TIM_ClockDivision = 0;
00124   TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
00125
00126   TIM_TimeBaseInit(TIM4, &TIM_TimeBaseStructure);
00127
00128   TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1;
00129   TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
00130   TIM_OCInitStructure.TIM_Pulse = 1;
00131
00132   TIM_OC1Init(TIM4, &TIM_OCInitStructure);
00133
00134   /* Slave Mode selection: TIM4 */
00135   TIM_SelectSlaveMode(TIM4, TIM_SlaveMode_Gated);
00136   TIM_SelectInputTrigger(TIM4, TIM_TS_ITR0);
00137
00138   /* TIM1 Peripheral Configuration ----------------------------------------*/
00139   /* Time Base configuration */
00140   TIM_TimeBaseStructure.TIM_Prescaler = 0;
00141   TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
00142   TIM_TimeBaseStructure.TIM_Period = 255;
00143   TIM_TimeBaseStructure.TIM_ClockDivision = 0;
00144   TIM_TimeBaseStructure.TIM_RepetitionCounter = 4;
00145
00146   TIM_TimeBaseInit(TIM1, &TIM_TimeBaseStructure);
00147
00148   /* Channel 1 Configuration in PWM mode */
00149   TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM2;
00150   TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
00151   TIM_OCInitStructure.TIM_OutputNState = TIM_OutputNState_Enable;
00152   TIM_OCInitStructure.TIM_Pulse = 127;
00153   TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_Low;
00154   TIM_OCInitStructure.TIM_OCNPolarity = TIM_OCNPolarity_Low;
00155   TIM_OCInitStructure.TIM_OCIdleState = TIM_OCIdleState_Set;
00156   TIM_OCInitStructure.TIM_OCNIdleState = TIM_OCIdleState_Reset;
00157
00158   TIM_OC1Init(TIM1, &TIM_OCInitStructure);
00159
00160   /* Automatic Output enable, Break, dead time and lock configuration*/
00161   TIM_BDTRInitStructure.TIM_OSSRState = TIM_OSSRState_Enable;
00162   TIM_BDTRInitStructure.TIM_OSSIState = TIM_OSSIState_Enable;
00163   TIM_BDTRInitStructure.TIM_LOCKLevel = TIM_LOCKLevel_1;
00164   TIM_BDTRInitStructure.TIM_DeadTime = 5;
00165   TIM_BDTRInitStructure.TIM_Break = TIM_Break_Disable;
00166   TIM_BDTRInitStructure.TIM_BreakPolarity = TIM_BreakPolarity_High;
00167   TIM_BDTRInitStructure.TIM_AutomaticOutput = TIM_AutomaticOutput_Disable;
00168
00169   TIM_BDTRConfig(TIM1, &TIM_BDTRInitStructure);
00170
00171   /* Master Mode selection */
00172   TIM_SelectOutputTrigger(TIM1, TIM_TRGOSource_Update);
00173
00174   /* Select the Master Slave Mode */
00175   TIM_SelectMasterSlaveMode(TIM1, TIM_MasterSlaveMode_Enable);
00176
00177   /* TIM1 counter enable */
00178   TIM_Cmd(TIM1, ENABLE);
00179
00180   /* TIM enable counter */
00181   TIM_Cmd(TIM3, ENABLE);
00182   TIM_Cmd(TIM4, ENABLE);
00183
00184   /* Main Output Enable */
00185   TIM_CtrlPWMOutputs(TIM1, ENABLE);
00186
00187   while (1)
00188   {}
00189 }
00190
00191 /**
00192   * @brief  Configures the different system clocks.
00193   * @param  None
00194   * @retval None
00195   */
00196 void RCC_Configuration(void)
00197 {
00198   /* TIM1, GPIOA and GPIOB clock enable */
00199   RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM1 | RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOE |
00200                          RCC_APB2Periph_GPIOC | RCC_APB2Periph_GPIOB | RCC_APB2Periph_AFIO, ENABLE);
00201
00202   /* TIM3 and TIM4 clock enable */
00203   RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM3 | RCC_APB1Periph_TIM4, ENABLE);
00204 }
00205
00206 /**
00207   * @brief  Configures TIM1, TIM3 and TIM4 Pins.
00208   * @param  None
00209   * @retval None
00210   */
00211 void GPIO_Configuration(void)
00212 {
00213   GPIO_InitTypeDef GPIO_InitStructure;
00214
00215 #ifdef STM32F10X_CL
00216   /* GPIOC Configuration: TIM3 channel1 as alternate function push-pull */
00217   GPIO_InitStructure.GPIO_Pin =  GPIO_Pin_6;
00218   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
00219   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00220
00221   GPIO_Init(GPIOC, &GPIO_InitStructure);
00222
00223   GPIO_PinRemapConfig(GPIO_FullRemap_TIM3, ENABLE);
00224
00225   /* GPIOE Configuration: TIM1 channel1 as alternate function push-pull */
00226   GPIO_InitStructure.GPIO_Pin =  GPIO_Pin_8;
00227
00228   GPIO_Init(GPIOE, &GPIO_InitStructure);
00229
00230   GPIO_PinRemapConfig(GPIO_FullRemap_TIM1, ENABLE);
00231
00232 #else
00233
00234   /* GPIOA Configuration: TIM1 Channel1 and TIM3 Channel1 as alternate function push-pull */
00235   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6 | GPIO_Pin_8;
00236   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
00237   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00238   GPIO_Init(GPIOA, &GPIO_InitStructure);
00239 #endif
00240
00241   /* GPIOB Configuration: TIM4 Channel1 as alternate function push-pull */
00242   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
00243   GPIO_Init(GPIOB, &GPIO_InitStructure);
00244 }
00245
00246 #ifdef  USE_FULL_ASSERT
00247
00248 /**
00249   * @brief  Reports the name of the source file and the source line number
00250   *         where the assert_param error has occurred.
00251   * @param  file: pointer to the source file name
00252   * @param  line: assert_param error line source number
00253   * @retval None
00254   */
00255 void assert_failed(uint8_t* file, uint32_t line)
00256 {
00257   /* User can add his own implementation to report the file name and line number,
00258      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00259
00260   while (1)
00261   {}
00262 }
00263
00264 #endif
00265
00266 /**
00267   * @}
00268   */
00269
00270 /**
00271   * @}
00272   */
00273
00274 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f10x_conf.h

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00001 /**
00002   ******************************************************************************
00003   * @file    TIM/TIM1_Synchro/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052
00053 /* Exported types ------------------------------------------------------------*/
00054 /* Exported constants --------------------------------------------------------*/
00055 /* Uncomment the line below to expanse the "assert_param" macro in the
00056    Standard Peripheral Library drivers code */
00057 /* #define USE_FULL_ASSERT    1 */
00058
00059 /* Exported macro ------------------------------------------------------------*/
00060 #ifdef  USE_FULL_ASSERT
00061
00062 /**
00063   * @brief  The assert_param macro is used for function's parameters check.
00064   * @param  expr: If expr is false, it calls assert_failed function which reports
00065   *         the name of the source file and the source line number of the call
00066   *         that failed. If expr is true, it returns no value.
00067   * @retval None
00068   */
00069   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00070 /* Exported functions ------------------------------------------------------- */
00071   void assert_failed(uint8_t* file, uint32_t line);
00072 #else
00073   #define assert_param(expr) ((void)0)
00074 #endif /* USE_FULL_ASSERT */
00075
00076 #endif /* __STM32F10x_CONF_H */
00077
00078 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f10x_it.c

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00001 /**
00002   ******************************************************************************
00003   * @file    TIM/TIM1_Synchro/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and peripherals
00009   *          interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026
00027 /** @addtogroup STM32F10x_StdPeriph_Examples
00028   * @{
00029   */
00030
00031 /** @addtogroup TIM_TIM1_Synchro
00032   * @{
00033   */
00034
00035 /* Private typedef -----------------------------------------------------------*/
00036 /* Private define ------------------------------------------------------------*/
00037 /* Private macro -------------------------------------------------------------*/
00038 /* Private variables ---------------------------------------------------------*/
00039 /* Private function prototypes -----------------------------------------------*/
00040 /* Private functions ---------------------------------------------------------*/
00041
00042 /******************************************************************************/
00043 /*            Cortex-M3 Processor Exceptions Handlers                         */
00044 /******************************************************************************/
00045
00046 /**
00047   * @brief  This function handles NMI exception.
00048   * @param  None
00049   * @retval None
00050   */
00051 void NMI_Handler(void)
00052 {
00053 }
00054
00055 /**
00056   * @brief  This function handles Hard Fault exception.
00057   * @param  None
00058   * @retval None
00059   */
00060 void HardFault_Handler(void)
00061 {
00062   /* Go to infinite loop when Hard Fault exception occurs */
00063   while (1)
00064   {}
00065 }
00066
00067 /**
00068   * @brief  This function handles Memory Manage exception.
00069   * @param  None
00070   * @retval None
00071   */
00072 void MemManage_Handler(void)
00073 {
00074   /* Go to infinite loop when Memory Manage exception occurs */
00075   while (1)
00076   {}
00077 }
00078
00079 /**
00080   * @brief  This function handles Bus Fault exception.
00081   * @param  None
00082   * @retval None
00083   */
00084 void BusFault_Handler(void)
00085 {
00086   /* Go to infinite loop when Bus Fault exception occurs */
00087   while (1)
00088   {}
00089 }
00090
00091 /**
00092   * @brief  This function handles Usage Fault exception.
00093   * @param  None
00094   * @retval None
00095   */
00096 void UsageFault_Handler(void)
00097 {
00098   /* Go to infinite loop when Usage Fault exception occurs */
00099   while (1)
00100   {}
00101 }
00102
00103 /**
00104   * @brief  This function handles Debug Monitor exception.
00105   * @param  None
00106   * @retval None
00107   */
00108 void DebugMon_Handler(void)
00109 {}
00110
00111 /**
00112   * @brief  This function handles SVCall exception.
00113   * @param  None
00114   * @retval None
00115   */
00116 void SVC_Handler(void)
00117 {}
00118
00119 /**
00120   * @brief  This function handles PendSV_Handler exception.
00121   * @param  None
00122   * @retval None
00123   */
00124 void PendSV_Handler(void)
00125 {}
00126
00127 /**
00128   * @brief  This function handles SysTick Handler.
00129   * @param  None
00130   * @retval None
00131   */
00132 void SysTick_Handler(void)
00133 {}
00134
00135 /******************************************************************************/
00136 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00137 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00138 /*  available peripheral interrupt handler's name please refer to the startup */
00139 /*  file (startup_stm32f10x_xx.s).                                            */
00140 /******************************************************************************/
00141
00142 /**
00143   * @brief  This function handles PPP interrupt request.
00144   * @param  None
00145   * @retval None
00146   */
00147 /*void PPP_IRQHandler(void)
00148 {
00149 }*/
00150
00151 /**
00152   * @}
00153   */
00154
00155 /**
00156   * @}
00157   */
00158
00159 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f10x_it.h

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00001 /**
00002   ******************************************************************************
00003   * @file    TIM/TIM1_Synchro/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043
00044 #endif /* __STM32F10x_IT_H */
00045
00046 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/main.c

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00001 /**
00002   ******************************************************************************
00003   * @file    TIM/TIM9_OCToggle/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x.h"
00024
00025 /** @addtogroup STM32F10x_StdPeriph_Examples
00026   * @{
00027   */
00028
00029 /** @addtogroup TIM9_OCToggle
00030   * @{
00031   */
00032
00033 /* Private typedef -----------------------------------------------------------*/
00034 /* Private define ------------------------------------------------------------*/
00035 /* Private macro -------------------------------------------------------------*/
00036 /* Private variables ---------------------------------------------------------*/
00037 TIM_TimeBaseInitTypeDef  TIM_TimeBaseStructure;
00038 TIM_OCInitTypeDef  TIM_OCInitStructure;
00039 __IO uint16_t CCR1Val = 32768;
00040 __IO uint16_t CCR2Val = 16384;
00041 uint16_t PrescalerValue = 0;
00042
00043 /* Private function prototypes -----------------------------------------------*/
00044 void GPIO_Configuration(void);
00045 void NVIC_Configuration(void);
00046
00047 /* Private functions ---------------------------------------------------------*/
00048
00049 /**
00050   * @brief  Main program
00051   * @param  None
00052   * @retval None
00053   */
00054 int main(void)
00055 {
00056   /*!< At this stage the microcontroller clock setting is already configured,
00057        this is done through SystemInit() function which is called from startup
00058        file (startup_stm32f10x_xx.s) before to branch to application main.
00059        To reconfigure the default setting of SystemInit() function, refer to
00060        system_stm32f10x.c file
00061      */
00062
00063   /* Configure TIM9 pins */
00064   GPIO_Configuration();
00065
00066   /* NVIC Configuration */
00067   NVIC_Configuration();
00068
00069   /* ---------------------------------------------------------------------------
00070     TIM9 Configuration: Output Compare Toggle Mode:
00071     TIM9CLK = SystemCoreClock (72MHz),
00072     The objective is to get TIM9 counter clock at 24 MHz:
00073      - Prescaler = (TIM9CLK / TIM9 counter clock) - 1
00074     CC1 update rate = TIM9 counter clock / CCR1Val = 732.4 Hz
00075     CC2 update rate = TIM9 counter clock / CCR2Val = 1464.8 Hz
00076   ----------------------------------------------------------------------------*/
00077   /* Compute the prescaler value */
00078   PrescalerValue = (uint16_t) (SystemCoreClock / 24000000) - 1;
00079
00080   /* Time base configuration */
00081   TIM_TimeBaseStructure.TIM_Period = 65535;
00082   TIM_TimeBaseStructure.TIM_Prescaler = PrescalerValue;
00083   TIM_TimeBaseStructure.TIM_ClockDivision = 0;
00084   TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
00085
00086   TIM_TimeBaseInit(TIM9, &TIM_TimeBaseStructure);
00087
00088   /* Output Compare Toggle Mode configuration: Channel1 */
00089   TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_Toggle;
00090   TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
00091   TIM_OCInitStructure.TIM_Pulse = CCR1Val;
00092   TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_Low;
00093   TIM_OC1Init(TIM9, &TIM_OCInitStructure);
00094
00095   TIM_OC1PreloadConfig(TIM9, TIM_OCPreload_Disable);
00096
00097   /* Output Compare Toggle Mode configuration: Channel2 */
00098   TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
00099   TIM_OCInitStructure.TIM_Pulse = CCR2Val;
00100
00101   TIM_OC2Init(TIM9, &TIM_OCInitStructure);
00102
00103   TIM_OC2PreloadConfig(TIM9, TIM_OCPreload_Disable);
00104
00105   /* TIM enable counter */
00106   TIM_Cmd(TIM9, ENABLE);
00107
00108   /* TIM IT enable */
00109   TIM_ITConfig(TIM9, TIM_IT_CC1 | TIM_IT_CC2, ENABLE);
00110
00111   while (1)
00112   {
00113   }
00114 }
00115
00116 /**
00117   * @brief  Configure TIM9 pins.
00118   * @param  None
00119   * @retval None
00120   */
00121 void GPIO_Configuration(void)
00122 {
00123   GPIO_InitTypeDef GPIO_InitStructure;
00124
00125   /* Enable TIM9 and GPIOA clock  */
00126   RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM9 | RCC_APB2Periph_GPIOA, ENABLE);
00127
00128   /* GPIOA Configuration:TIM9 Channel1 and 2 as alternate function push-pull */
00129   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2 | GPIO_Pin_3;
00130   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
00131   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00132
00133   GPIO_Init(GPIOA, &GPIO_InitStructure);
00134 }
00135
00136 /**
00137   * @brief  Configure the nested vectored interrupt controller.
00138   * @param  None
00139   * @retval None
00140   */
00141 void NVIC_Configuration(void)
00142 {
00143   NVIC_InitTypeDef NVIC_InitStructure;
00144
00145   /* Enable the TIM9 global Interrupt */
00146   NVIC_InitStructure.NVIC_IRQChannel =  TIM1_BRK_TIM9_IRQn;
00147   NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
00148   NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
00149   NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
00150   NVIC_Init(&NVIC_InitStructure);
00151 }
00152
00153 #ifdef  USE_FULL_ASSERT
00154
00155 /**
00156   * @brief  Reports the name of the source file and the source line number
00157   *         where the assert_param error has occurred.
00158   * @param  file: pointer to the source file name
00159   * @param  line: assert_param error line source number
00160   * @retval None
00161   */
00162 void assert_failed(uint8_t* file, uint32_t line)
00163 {
00164   /* User can add his own implementation to report the file name and line number,
00165      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00166
00167   while (1)
00168   {}
00169 }
00170
00171 #endif
00172 /**
00173   * @}
00174   */
00175
00176 /**
00177   * @}
00178   */
00179
00180 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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  • Project
  • STM32F10x_StdPeriph_Examples
  • TIM
  • TIM9_OCToggle

STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_conf.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    TIM/TIM9_OCToggle/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052 /* Exported types ------------------------------------------------------------*/
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Uncomment the line below to expanse the "assert_param" macro in the
00055    Standard Peripheral Library drivers code */
00056 /* #define USE_FULL_ASSERT    1 */
00057
00058 /* Exported macro ------------------------------------------------------------*/
00059 #ifdef  USE_FULL_ASSERT
00060
00061 /**
00062   * @brief  The assert_param macro is used for function's parameters check.
00063   * @param  expr: If expr is false, it calls assert_failed function which reports
00064   *         the name of the source file and the source line number of the call
00065   *         that failed. If expr is true, it returns no value.
00066   * @retval None
00067   */
00068   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00069 /* Exported functions ------------------------------------------------------- */
00070   void assert_failed(uint8_t* file, uint32_t line);
00071 #else
00072   #define assert_param(expr) ((void)0)
00073 #endif /* USE_FULL_ASSERT */
00074
00075 #endif /* __STM32F10x_CONF_H */
00076
00077 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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  • TIM9_OCToggle

STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_it.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    TIM/TIM9_OCToggle/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and peripherals
00009   *          interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026
00027 /** @addtogroup STM32F10x_StdPeriph_Examples
00028   * @{
00029   */
00030
00031 /** @addtogroup TIM9_OCToggle
00032   * @{
00033   */
00034
00035 /* Private typedef -----------------------------------------------------------*/
00036 /* Private define ------------------------------------------------------------*/
00037 /* Private macro -------------------------------------------------------------*/
00038 /* Private variables ---------------------------------------------------------*/
00039 uint16_t capture = 0;
00040 extern __IO uint16_t CCR1Val;
00041 extern __IO uint16_t CCR2Val;
00042
00043 /* Private function prototypes -----------------------------------------------*/
00044 /* Private functions ---------------------------------------------------------*/
00045
00046 /******************************************************************************/
00047 /*            Cortex-M3 Processor Exceptions Handlers                         */
00048 /******************************************************************************/
00049
00050 /**
00051   * @brief  This function handles NMI exception.
00052   * @param  None
00053   * @retval None
00054   */
00055 void NMI_Handler(void)
00056 {
00057 }
00058
00059 /**
00060   * @brief  This function handles Hard Fault exception.
00061   * @param  None
00062   * @retval None
00063   */
00064 void HardFault_Handler(void)
00065 {
00066   /* Go to infinite loop when Hard Fault exception occurs */
00067   while (1)
00068   {}
00069 }
00070
00071 /**
00072   * @brief  This function handles Memory Manage exception.
00073   * @param  None
00074   * @retval None
00075   */
00076 void MemManage_Handler(void)
00077 {
00078   /* Go to infinite loop when Memory Manage exception occurs */
00079   while (1)
00080   {}
00081 }
00082
00083 /**
00084   * @brief  This function handles Bus Fault exception.
00085   * @param  None
00086   * @retval None
00087   */
00088 void BusFault_Handler(void)
00089 {
00090   /* Go to infinite loop when Bus Fault exception occurs */
00091   while (1)
00092   {}
00093 }
00094
00095 /**
00096   * @brief  This function handles Usage Fault exception.
00097   * @param  None
00098   * @retval None
00099   */
00100 void UsageFault_Handler(void)
00101 {
00102   /* Go to infinite loop when Usage Fault exception occurs */
00103   while (1)
00104   {}
00105 }
00106
00107 /**
00108   * @brief  This function handles Debug Monitor exception.
00109   * @param  None
00110   * @retval None
00111   */
00112 void DebugMon_Handler(void)
00113 {}
00114
00115 /**
00116   * @brief  This function handles SVCall exception.
00117   * @param  None
00118   * @retval None
00119   */
00120 void SVC_Handler(void)
00121 {}
00122
00123 /**
00124   * @brief  This function handles PendSV_Handler exception.
00125   * @param  None
00126   * @retval None
00127   */
00128 void PendSV_Handler(void)
00129 {}
00130
00131 /**
00132   * @brief  This function handles SysTick Handler.
00133   * @param  None
00134   * @retval None
00135   */
00136 void SysTick_Handler(void)
00137 {}
00138
00139 /******************************************************************************/
00140 /*            STM32F10x Peripherals Interrupt Handlers                        */
00141 /******************************************************************************/
00142
00143 /**
00144   * @brief  This function handles TIM1 Break and TIM9 interrupts request.
00145   * @param  None
00146   * @retval None
00147   */
00148 void TIM1_BRK_TIM9_IRQHandler(void)
00149 {
00150   /* TIM9_CH1 toggling with frequency = 366.2 Hz */
00151   if (TIM_GetITStatus(TIM9, TIM_IT_CC1) != RESET)
00152   {
00153     TIM_ClearITPendingBit(TIM9, TIM_IT_CC1 );
00154     capture = TIM_GetCapture1(TIM9);
00155     TIM_SetCompare1(TIM9, capture + CCR1Val );
00156   }
00157
00158   /* TIM9_CH2 toggling with frequency = 732.4 Hz */
00159   if (TIM_GetITStatus(TIM9, TIM_IT_CC2) != RESET)
00160   {
00161     TIM_ClearITPendingBit(TIM9, TIM_IT_CC2);
00162     capture = TIM_GetCapture2(TIM9);
00163     TIM_SetCompare2(TIM9, capture + CCR2Val);
00164   }
00165 }
00166
00167 /******************************************************************************/
00168 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00169 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00170 /*  available peripheral interrupt handler's name please refer to the startup */
00171 /*  file (startup_stm32f10x_xx.s).                                            */
00172 /******************************************************************************/
00173
00174 /**
00175   * @brief  This function handles PPP interrupt request.
00176   * @param  None
00177   * @retval None
00178   */
00179 /*void PPP_IRQHandler(void)
00180 {
00181 }*/
00182
00183 /**
00184   * @}
00185   */
00186
00187 /**
00188   * @}
00189   */
00190
00191 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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  • TIM9_OCToggle

STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_it.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    TIM/TIM9_OCToggle/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043 void TIM3_IRQHandler(void);
00044
00045 #endif /* __STM32F10x_IT_H */
00046
00047 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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  • TIM10_PWMOutput

STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/main.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    TIM/TIM10_PWMOutput/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x.h"
00024
00025 /** @addtogroup STM32F10x_StdPeriph_Examples
00026   * @{
00027   */
00028
00029 /** @addtogroup TIM10_PWMOutput
00030   * @{
00031   */
00032
00033 /* Private typedef -----------------------------------------------------------*/
00034 /* Private define ------------------------------------------------------------*/
00035 /* Private macro -------------------------------------------------------------*/
00036 /* Private variables ---------------------------------------------------------*/
00037 TIM_TimeBaseInitTypeDef  TIM_TimeBaseStructure;
00038 TIM_OCInitTypeDef  TIM_OCInitStructure;
00039 uint16_t CCR1Val = 249;
00040 uint16_t PrescalerValue = 0;
00041
00042 /* Private function prototypes -----------------------------------------------*/
00043 void RCC_Configuration(void);
00044 void GPIO_Configuration(void);
00045
00046 /* Private functions ---------------------------------------------------------*/
00047
00048 /**
00049   * @brief   Main program
00050   * @param  None
00051   * @retval None
00052   */
00053 int main(void)
00054 {
00055   /*!< At this stage the microcontroller clock setting is already configured,
00056        this is done through SystemInit() function which is called from startup
00057        file (startup_stm32f10x_xx.s) before to branch to application main.
00058        To reconfigure the default setting of SystemInit() function, refer to
00059        system_stm32f10x.c file
00060      */
00061
00062   /* GPIO Configuration */
00063   GPIO_Configuration();
00064
00065   /* -----------------------------------------------------------------------
00066     TIM10 Configuration: generate 1 PWM signal.
00067     The TIM10CLK frequency is set to SystemCoreClock (72 MHz), to get TIM10 counter
00068     clock at 24 MHz the Prescaler is computed as following:
00069      - Prescaler = (TIM10CLK / TIM10 counter clock) - 1
00070
00071     The TIM10 is running at 36 KHz: TIM10 Frequency = TIM10 counter clock/(ARR + 1)
00072                                                   = 24 MHz / 666 = 36 KHz
00073     TIM10 Channel1 duty cycle = (TIM10_CCR1/ TIM10_ARR)* 100 = 37.5%
00074   ----------------------------------------------------------------------- */
00075   /* Compute the prescaler value */
00076   PrescalerValue = (uint16_t) (SystemCoreClock / 24000000) - 1;
00077   /* Time base configuration */
00078   TIM_TimeBaseStructure.TIM_Period = 665;
00079   TIM_TimeBaseStructure.TIM_Prescaler = PrescalerValue;
00080   TIM_TimeBaseStructure.TIM_ClockDivision = 0;
00081   TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
00082
00083   TIM_TimeBaseInit(TIM10, &TIM_TimeBaseStructure);
00084
00085   /* PWM1 Mode configuration: Channel1 */
00086   TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1;
00087   TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
00088   TIM_OCInitStructure.TIM_Pulse = CCR1Val;
00089   TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High;
00090
00091   TIM_OC1Init(TIM10, &TIM_OCInitStructure);
00092
00093   TIM_OC1PreloadConfig(TIM10, TIM_OCPreload_Enable);
00094
00095   TIM_ARRPreloadConfig(TIM10, ENABLE);
00096
00097   /* TIM10 enable counter */
00098   TIM_Cmd(TIM10, ENABLE);
00099
00100   while (1)
00101   {}
00102 }
00103
00104 /**
00105   * @brief  Configure TIM10 pin.
00106   * @param  None
00107   * @retval None
00108   */
00109 void GPIO_Configuration(void)
00110 {
00111   GPIO_InitTypeDef GPIO_InitStructure;
00112
00113   /* Enable TIM10 and GPIOF clock */
00114   RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM10 | RCC_APB2Periph_GPIOF |
00115                          RCC_APB2Periph_AFIO, ENABLE);
00116
00117   /* Remap TIM10_CH1 on PF6 pin */
00118   GPIO_PinRemapConfig(GPIO_Remap_TIM10, ENABLE);
00119
00120   /* GPIOF Configuration: TIM10 Channel1 as alternate function push-pull */
00121   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
00122   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
00123   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00124
00125   GPIO_Init(GPIOF, &GPIO_InitStructure);
00126 }
00127
00128 #ifdef  USE_FULL_ASSERT
00129
00130 /**
00131   * @brief  Reports the name of the source file and the source line number
00132   *         where the assert_param error has occurred.
00133   * @param  file: pointer to the source file name
00134   * @param  line: assert_param error line source number
00135   * @retval None
00136   */
00137 void assert_failed(uint8_t* file, uint32_t line)
00138 {
00139   /* User can add his own implementation to report the file name and line number,
00140      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00141
00142   while (1)
00143   {}
00144 }
00145
00146 #endif
00147
00148 /**
00149   * @}
00150   */
00151
00152 /**
00153   * @}
00154   */
00155
00156 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/stm32f10x_conf.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    TIM/TIM10_PWMOutput/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052 /* Exported types ------------------------------------------------------------*/
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Uncomment the line below to expanse the "assert_param" macro in the
00055    Standard Peripheral Library drivers code */
00056 /* #define USE_FULL_ASSERT    1 */
00057
00058 /* Exported macro ------------------------------------------------------------*/
00059 #ifdef  USE_FULL_ASSERT
00060
00061 /**
00062   * @brief  The assert_param macro is used for function's parameters check.
00063   * @param  expr: If expr is false, it calls assert_failed function which reports
00064   *         the name of the source file and the source line number of the call
00065   *         that failed. If expr is true, it returns no value.
00066   * @retval None
00067   */
00068   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00069 /* Exported functions ------------------------------------------------------- */
00070   void assert_failed(uint8_t* file, uint32_t line);
00071 #else
00072   #define assert_param(expr) ((void)0)
00073 #endif /* USE_FULL_ASSERT */
00074
00075 #endif /* __STM32F10x_CONF_H */
00076
00077 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/stm32f10x_it.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    TIM/TIM10_PWMOutput/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *         This file provides template for all exceptions handler and
00009   *         peripherals interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026
00027 /** @addtogroup STM32F10x_StdPeriph_Examples
00028   * @{
00029   */
00030
00031 /** @addtogroup TIM10_PWMOutput
00032   * @{
00033   */
00034
00035 /* Private typedef -----------------------------------------------------------*/
00036 /* Private define ------------------------------------------------------------*/
00037 /* Private macro -------------------------------------------------------------*/
00038 /* Private variables ---------------------------------------------------------*/
00039 /* Private function prototypes -----------------------------------------------*/
00040 /* Private functions ---------------------------------------------------------*/
00041
00042 /******************************************************************************/
00043 /*            Cortex-M3 Processor Exceptions Handlers                         */
00044 /******************************************************************************/
00045
00046 /**
00047   * @brief  This function handles NMI exception.
00048   * @param  None
00049   * @retval None
00050   */
00051 void NMI_Handler(void)
00052 {
00053 }
00054
00055 /**
00056   * @brief  This function handles Hard Fault exception.
00057   * @param  None
00058   * @retval None
00059   */
00060 void HardFault_Handler(void)
00061 {
00062   /* Go to infinite loop when Hard Fault exception occurs */
00063   while (1)
00064   {}
00065 }
00066
00067 /**
00068   * @brief  This function handles Memory Manage exception.
00069   * @param  None
00070   * @retval None
00071   */
00072 void MemManage_Handler(void)
00073 {
00074   /* Go to infinite loop when Memory Manage exception occurs */
00075   while (1)
00076   {}
00077 }
00078
00079 /**
00080   * @brief  This function handles Bus Fault exception.
00081   * @param  None
00082   * @retval None
00083   */
00084 void BusFault_Handler(void)
00085 {
00086   /* Go to infinite loop when Bus Fault exception occurs */
00087   while (1)
00088   {}
00089 }
00090
00091 /**
00092   * @brief  This function handles Usage Fault exception.
00093   * @param  None
00094   * @retval None
00095   */
00096 void UsageFault_Handler(void)
00097 {
00098   /* Go to infinite loop when Usage Fault exception occurs */
00099   while (1)
00100   {}
00101 }
00102
00103 /**
00104   * @brief  This function handles Debug Monitor exception.
00105   * @param  None
00106   * @retval None
00107   */
00108 void DebugMon_Handler(void)
00109 {}
00110
00111 /**
00112   * @brief  This function handles SVCall exception.
00113   * @param  None
00114   * @retval None
00115   */
00116 void SVC_Handler(void)
00117 {}
00118
00119 /**
00120   * @brief  This function handles PendSV_Handler exception.
00121   * @param  None
00122   * @retval None
00123   */
00124 void PendSV_Handler(void)
00125 {}
00126
00127 /**
00128   * @brief  This function handles SysTick Handler.
00129   * @param  None
00130   * @retval None
00131   */
00132 void SysTick_Handler(void)
00133 {}
00134
00135 /******************************************************************************/
00136 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00137 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00138 /*  available peripheral interrupt handler's name please refer to the startup */
00139 /*  file (startup_stm32f10x_xx.s).                                            */
00140 /******************************************************************************/
00141
00142 /**
00143   * @brief  This function handles PPP interrupt request.
00144   * @param  None
00145   * @retval None
00146   */
00147 /*void PPP_IRQHandler(void)
00148 {
00149 }*/
00150
00151 /**
00152   * @}
00153   */
00154
00155 /**
00156   * @}
00157   */
00158
00159 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/stm32f10x_it.h

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00001 /**
00002   ******************************************************************************
00003   * @file    TIM/TIM10_PWMOutput/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043
00044 #endif /* __STM32F10x_IT_H */
00045
00046 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/main.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    TIM/TIM15_ComplementarySignals/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x.h"
00024
00025 /** @addtogroup STM32F10x_StdPeriph_Examples
00026   * @{
00027   */
00028
00029 /** @addtogroup TIM15_ComplementarySignals
00030   * @{
00031   */
00032
00033 /* Private typedef -----------------------------------------------------------*/
00034 /* Private define ------------------------------------------------------------*/
00035 /* Private macro -------------------------------------------------------------*/
00036 /* Private variables ---------------------------------------------------------*/
00037 TIM_TimeBaseInitTypeDef  TIM_TimeBaseStructure;
00038 TIM_OCInitTypeDef  TIM_OCInitStructure;
00039 TIM_BDTRInitTypeDef TIM_BDTRInitStructure;
00040 uint16_t CCR1_Val = 32767;
00041
00042 /* Private function prototypes -----------------------------------------------*/
00043 void RCC_Configuration(void);
00044 void GPIO_Configuration(void);
00045
00046 /* Private functions ---------------------------------------------------------*/
00047
00048 /**
00049   * @brief  Main program
00050   * @param  None
00051   * @retval None
00052   */
00053 int main(void)
00054 {
00055   /*!< At this stage the microcontroller clock setting is already configured,
00056        this is done through SystemInit() function which is called from startup
00057        file (startup_stm32f10x_xx.s) before to branch to application main.
00058        To reconfigure the default setting of SystemInit() function, refer to
00059        system_stm32f10x.c file
00060      */
00061
00062   /* System Clocks Configuration */
00063   RCC_Configuration();
00064
00065   /* GPIO Configuration */
00066   GPIO_Configuration();
00067
00068   /* -----------------------------------------------------------------------
00069   TIM15 Configuration to:
00070
00071   1/ Generate a complementary PWM signals with 50% duty cycles:
00072   TIM15CLK = 24 MHz, Prescaler = 0, TIM15 counter clock = 24 MHz
00073   TIM15 frequency = TIM15CLK/(TIM15_Period + 1) = 366 Hz
00074
00075   TIM15 Channel1 duty cycle = TIM15->CCR1 / TIM15_Period = 50%
00076   TIM15 Channel1N duty cycle = (TIM15_Period - TIM15_CCR1) / (TIM15_Period + 1) = 50%
00077
00078   2/ Insert a dead time equal to 1.62 us
00079   3/ Configure the break feature, active at High level, and using the automatic
00080      output enable feature
00081   4/ Use the Locking parameters level1.
00082   ----------------------------------------------------------------------- */
00083
00084   /* Time Base configuration */
00085   TIM_TimeBaseStructure.TIM_Prescaler = 0;
00086   TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
00087   TIM_TimeBaseStructure.TIM_Period = 65535;
00088   TIM_TimeBaseStructure.TIM_ClockDivision = 0;
00089   TIM_TimeBaseStructure.TIM_RepetitionCounter = 0;
00090
00091   TIM_TimeBaseInit(TIM15, &TIM_TimeBaseStructure);
00092
00093   /* Channel 1 Configuration in PWM mode */
00094   TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM2;
00095   TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
00096   TIM_OCInitStructure.TIM_OutputNState = TIM_OutputNState_Enable;
00097   TIM_OCInitStructure.TIM_Pulse = CCR1_Val;
00098   TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_Low;
00099   TIM_OCInitStructure.TIM_OCNPolarity = TIM_OCNPolarity_Low;
00100   TIM_OCInitStructure.TIM_OCIdleState = TIM_OCIdleState_Set;
00101   TIM_OCInitStructure.TIM_OCNIdleState = TIM_OCIdleState_Reset;
00102
00103   TIM_OC1Init(TIM15, &TIM_OCInitStructure);
00104
00105   /* Automatic Output enable, Break, dead time and lock configuration*/
00106   TIM_BDTRInitStructure.TIM_OSSRState = TIM_OSSRState_Enable;
00107   TIM_BDTRInitStructure.TIM_OSSIState = TIM_OSSIState_Enable;
00108   TIM_BDTRInitStructure.TIM_LOCKLevel = TIM_LOCKLevel_1;
00109   TIM_BDTRInitStructure.TIM_DeadTime = 39;
00110   TIM_BDTRInitStructure.TIM_Break = TIM_Break_Enable;
00111   TIM_BDTRInitStructure.TIM_BreakPolarity = TIM_BreakPolarity_High;
00112   TIM_BDTRInitStructure.TIM_AutomaticOutput = TIM_AutomaticOutput_Enable;
00113
00114   TIM_BDTRConfig(TIM15, &TIM_BDTRInitStructure);
00115
00116   /* TIM15 counter enable */
00117   TIM_Cmd(TIM15, ENABLE);
00118
00119   /* Main Output Enable */
00120   TIM_CtrlPWMOutputs(TIM15, ENABLE);
00121
00122   while (1)
00123   {
00124   }
00125 }
00126
00127 /**
00128   * @brief  Configures the different system clocks.
00129   * @param  None
00130   * @retval None
00131   */
00132 void RCC_Configuration(void)
00133 {
00134   /* TIM15, GPIOA, GPIOB and AFIO clocks enable */
00135   RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM15 | RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB
00136                          | RCC_APB2Periph_AFIO, ENABLE);
00137 }
00138
00139 /**
00140   * @brief  Configure the TIM1 Pins.
00141   * @param  None
00142   * @retval None
00143   */
00144 void GPIO_Configuration(void)
00145 {
00146   GPIO_InitTypeDef GPIO_InitStructure;
00147
00148   /* GPIOA Configuration: Channel 1 as alternate function push-pull */
00149   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
00150   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
00151   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00152   GPIO_Init(GPIOA, &GPIO_InitStructure);
00153
00154   /* GPIOB Configuration: Channel 1N as alternate function push-pull */
00155   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_15;
00156   GPIO_Init(GPIOB, &GPIO_InitStructure);
00157
00158   /* GPIOA Configuration: BKIN pin */
00159   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;
00160   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
00161   GPIO_Init(GPIOB, &GPIO_InitStructure);
00162 }
00163
00164 #ifdef  USE_FULL_ASSERT
00165
00166 /**
00167   * @brief  Reports the name of the source file and the source line number
00168   *         where the assert_param error has occurred.
00169   * @param  file: pointer to the source file name
00170   * @param  line: assert_param error line source number
00171   * @retval None
00172   */
00173 void assert_failed(uint8_t* file, uint32_t line)
00174 {
00175   /* User can add his own implementation to report the file name and line number,
00176      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00177
00178   while (1)
00179   {}
00180 }
00181
00182 #endif
00183
00184 /**
00185   * @}
00186   */
00187
00188 /**
00189   * @}
00190   */
00191
00192 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/stm32f10x_conf.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    TIM/TIM15_ComplementarySignals/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052 /* Exported types ------------------------------------------------------------*/
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Uncomment the line below to expanse the "assert_param" macro in the
00055    Standard Peripheral Library drivers code */
00056 /* #define USE_FULL_ASSERT    1 */
00057
00058 /* Exported macro ------------------------------------------------------------*/
00059 #ifdef  USE_FULL_ASSERT
00060
00061 /**
00062   * @brief  The assert_param macro is used for function's parameters check.
00063   * @param  expr: If expr is false, it calls assert_failed function which reports
00064   *         the name of the source file and the source line number of the call
00065   *         that failed. If expr is true, it returns no value.
00066   * @retval None
00067   */
00068   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00069 /* Exported functions ------------------------------------------------------- */
00070   void assert_failed(uint8_t* file, uint32_t line);
00071 #else
00072   #define assert_param(expr) ((void)0)
00073 #endif /* USE_FULL_ASSERT */
00074
00075 #endif /* __STM32F10x_CONF_H */
00076
00077 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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  • STM32F10x_StdPeriph_Examples
  • TIM
  • TIM15_ComplementarySignals

STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/stm32f10x_it.c

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00001 /**
00002   ******************************************************************************
00003   * @file    TIM/TIM15_ComplementarySignals/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and
00009   *          peripherals interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026
00027 /** @addtogroup STM32F10x_StdPeriph_Examples
00028   * @{
00029   */
00030
00031 /** @addtogroup TIM15_ComplementarySignals
00032   * @{
00033   */
00034
00035 /* Private typedef -----------------------------------------------------------*/
00036 /* Private define ------------------------------------------------------------*/
00037 /* Private macro -------------------------------------------------------------*/
00038 /* Private variables ---------------------------------------------------------*/
00039 /* Private function prototypes -----------------------------------------------*/
00040 /* Private functions ---------------------------------------------------------*/
00041
00042 /******************************************************************************/
00043 /*            Cortex-M3 Processor Exceptions Handlers                         */
00044 /******************************************************************************/
00045
00046 /**
00047   * @brief  This function handles NMI exception.
00048   * @param  None
00049   * @retval None
00050   */
00051 void NMI_Handler(void)
00052 {}
00053
00054 /**
00055   * @brief  This function handles Hard Fault exception.
00056   * @param  None
00057   * @retval None
00058   */
00059 void HardFault_Handler(void)
00060 {
00061   /* Go to infinite loop when Hard Fault exception occurs */
00062   while (1)
00063   {}
00064 }
00065
00066 /**
00067   * @brief  This function handles Memory Manage exception.
00068   * @param  None
00069   * @retval None
00070   */
00071 void MemManage_Handler(void)
00072 {
00073   /* Go to infinite loop when Memory Manage exception occurs */
00074   while (1)
00075   {}
00076 }
00077
00078 /**
00079   * @brief  This function handles Bus Fault exception.
00080   * @param  None
00081   * @retval None
00082   */
00083 void BusFault_Handler(void)
00084 {
00085   /* Go to infinite loop when Bus Fault exception occurs */
00086   while (1)
00087   {}
00088 }
00089
00090 /**
00091   * @brief  This function handles Usage Fault exception.
00092   * @param  None
00093   * @retval None
00094   */
00095 void UsageFault_Handler(void)
00096 {
00097   /* Go to infinite loop when Usage Fault exception occurs */
00098   while (1)
00099   {}
00100 }
00101
00102 /**
00103   * @brief  This function handles Debug Monitor exception.
00104   * @param  None
00105   * @retval None
00106   */
00107 void DebugMon_Handler(void)
00108 {}
00109
00110 /**
00111   * @brief  This function handles SVCall exception.
00112   * @param  None
00113   * @retval None
00114   */
00115 void SVC_Handler(void)
00116 {}
00117
00118 /**
00119   * @brief  This function handles PendSV_Handler exception.
00120   * @param  None
00121   * @retval None
00122   */
00123 void PendSV_Handler(void)
00124 {}
00125
00126 /**
00127   * @brief  This function handles SysTick Handler.
00128   * @param  None
00129   * @retval None
00130   */
00131 void SysTick_Handler(void)
00132 {}
00133
00134 /******************************************************************************/
00135 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00136 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00137 /*  available peripheral interrupt handler's name please refer to the startup */
00138 /*  file (startup_stm32f10x_xx.s).                                            */
00139 /******************************************************************************/
00140
00141 /**
00142   * @brief  This function handles PPP interrupt request.
00143   * @param  None
00144   * @retval None
00145   */
00146 /*void PPP_IRQHandler(void)
00147 {
00148 }*/
00149
00150 /**
00151   * @}
00152   */
00153
00154 /**
00155   * @}
00156   */
00157
00158 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/stm32f10x_it.h

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00001 /**
00002   ******************************************************************************
00003   * @file    TIM/TIM15_ComplementarySignals/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043
00044 #endif /* __STM32F10x_IT_H */
00045
00046 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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STM32F10x_StdPeriph_Examples/TIM/TimeBase/main.c

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00001 /**
00002   ******************************************************************************
00003   * @file    TIM/TimeBase/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x.h"
00024
00025 /** @addtogroup STM32F10x_StdPeriph_Examples
00026   * @{
00027   */
00028
00029 /** @addtogroup TIM_TimeBase
00030   * @{
00031   */
00032
00033 /* Private typedef -----------------------------------------------------------*/
00034 /* Private define ------------------------------------------------------------*/
00035 /* Private macro -------------------------------------------------------------*/
00036 /* Private variables ---------------------------------------------------------*/
00037 TIM_TimeBaseInitTypeDef  TIM_TimeBaseStructure;
00038 TIM_OCInitTypeDef  TIM_OCInitStructure;
00039 __IO uint16_t CCR1_Val = 40961;
00040 __IO uint16_t CCR2_Val = 27309;
00041 __IO uint16_t CCR3_Val = 13654;
00042 __IO uint16_t CCR4_Val = 6826;
00043 uint16_t PrescalerValue = 0;
00044
00045 /* Private function prototypes -----------------------------------------------*/
00046 void RCC_Configuration(void);
00047 void GPIO_Configuration(void);
00048 void NVIC_Configuration(void);
00049
00050 /* Private functions ---------------------------------------------------------*/
00051
00052 /**
00053   * @brief  Main program
00054   * @param  None
00055   * @retval None
00056   */
00057 int main(void)
00058 {
00059   /*!< At this stage the microcontroller clock setting is already configured,
00060        this is done through SystemInit() function which is called from startup
00061        file (startup_stm32f10x_xx.s) before to branch to application main.
00062        To reconfigure the default setting of SystemInit() function, refer to
00063        system_stm32f10x.c file
00064      */
00065
00066   /* System Clocks Configuration */
00067   RCC_Configuration();
00068
00069   /* NVIC Configuration */
00070   NVIC_Configuration();
00071
00072   /* GPIO Configuration */
00073   GPIO_Configuration();
00074
00075   /* ---------------------------------------------------------------
00076     TIM2 Configuration: Output Compare Timing Mode:
00077     TIM2 counter clock at 6 MHz
00078     CC1 update rate = TIM2 counter clock / CCR1_Val = 146.48 Hz
00079     CC2 update rate = TIM2 counter clock / CCR2_Val = 219.7 Hz
00080     CC3 update rate = TIM2 counter clock / CCR3_Val = 439.4 Hz
00081     CC4 update rate = TIM2 counter clock / CCR4_Val = 878.9 Hz
00082   --------------------------------------------------------------- */
00083
00084   /* Compute the prescaler value */
00085   PrescalerValue = (uint16_t) (SystemCoreClock / 12000000) - 1;
00086
00087   /* Time base configuration */
00088   TIM_TimeBaseStructure.TIM_Period = 65535;
00089   TIM_TimeBaseStructure.TIM_Prescaler = 0;
00090   TIM_TimeBaseStructure.TIM_ClockDivision = 0;
00091   TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
00092
00093   TIM_TimeBaseInit(TIM2, &TIM_TimeBaseStructure);
00094
00095   /* Prescaler configuration */
00096   TIM_PrescalerConfig(TIM2, PrescalerValue, TIM_PSCReloadMode_Immediate);
00097
00098   /* Output Compare Timing Mode configuration: Channel1 */
00099   TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_Timing;
00100   TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
00101   TIM_OCInitStructure.TIM_Pulse = CCR1_Val;
00102   TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High;
00103
00104   TIM_OC1Init(TIM2, &TIM_OCInitStructure);
00105
00106   TIM_OC1PreloadConfig(TIM2, TIM_OCPreload_Disable);
00107
00108   /* Output Compare Timing Mode configuration: Channel2 */
00109   TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
00110   TIM_OCInitStructure.TIM_Pulse = CCR2_Val;
00111
00112   TIM_OC2Init(TIM2, &TIM_OCInitStructure);
00113
00114   TIM_OC2PreloadConfig(TIM2, TIM_OCPreload_Disable);
00115
00116   /* Output Compare Timing Mode configuration: Channel3 */
00117   TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
00118   TIM_OCInitStructure.TIM_Pulse = CCR3_Val;
00119
00120   TIM_OC3Init(TIM2, &TIM_OCInitStructure);
00121
00122   TIM_OC3PreloadConfig(TIM2, TIM_OCPreload_Disable);
00123
00124   /* Output Compare Timing Mode configuration: Channel4 */
00125   TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
00126   TIM_OCInitStructure.TIM_Pulse = CCR4_Val;
00127
00128   TIM_OC4Init(TIM2, &TIM_OCInitStructure);
00129
00130   TIM_OC4PreloadConfig(TIM2, TIM_OCPreload_Disable);
00131
00132   /* TIM IT enable */
00133   TIM_ITConfig(TIM2, TIM_IT_CC1 | TIM_IT_CC2 | TIM_IT_CC3 | TIM_IT_CC4, ENABLE);
00134
00135   /* TIM2 enable counter */
00136   TIM_Cmd(TIM2, ENABLE);
00137
00138   while (1);
00139 }
00140
00141 /**
00142   * @brief  Configures the different system clocks.
00143   * @param  None
00144   * @retval None
00145   */
00146 void RCC_Configuration(void)
00147 {
00148   /* PCLK1 = HCLK/4 */
00149   RCC_PCLK1Config(RCC_HCLK_Div4);
00150
00151   /* TIM2 clock enable */
00152   RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2, ENABLE);
00153
00154   /* GPIOC clock enable */
00155   RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC, ENABLE);
00156 }
00157
00158 /**
00159   * @brief  Configure the GPIO Pins.
00160   * @param  None
00161   * @retval None
00162   */
00163 void GPIO_Configuration(void)
00164 {
00165   GPIO_InitTypeDef GPIO_InitStructure;
00166
00167   /* GPIOC Configuration:Pin6, 7, 8 and 9 as alternate function push-pull */
00168   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6 | GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9;
00169   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
00170   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00171
00172   GPIO_Init(GPIOC, &GPIO_InitStructure);
00173 }
00174
00175 /**
00176   * @brief  Configure the nested vectored interrupt controller.
00177   * @param  None
00178   * @retval None
00179   */
00180 void NVIC_Configuration(void)
00181 {
00182   NVIC_InitTypeDef NVIC_InitStructure;
00183
00184   /* Enable the TIM2 global Interrupt */
00185   NVIC_InitStructure.NVIC_IRQChannel = TIM2_IRQn;
00186   NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
00187   NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;
00188   NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
00189
00190   NVIC_Init(&NVIC_InitStructure);
00191 }
00192
00193 #ifdef  USE_FULL_ASSERT
00194
00195 /**
00196   * @brief  Reports the name of the source file and the source line number
00197   *         where the assert_param error has occurred.
00198   * @param  file: pointer to the source file name
00199   * @param  line: assert_param error line source number
00200   * @retval None
00201   */
00202 void assert_failed(uint8_t* file, uint32_t line)
00203 {
00204   /* User can add his own implementation to report the file name and line number,
00205      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00206
00207   while (1)
00208   {}
00209 }
00210
00211 #endif
00212
00213 /**
00214   * @}
00215   */
00216
00217 /**
00218   * @}
00219   */
00220
00221 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_conf.h

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00001 /**
00002   ******************************************************************************
00003   * @file    TIM/TimeBase/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052 /* Exported types ------------------------------------------------------------*/
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Uncomment the line below to expanse the "assert_param" macro in the
00055    Standard Peripheral Library drivers code */
00056 /* #define USE_FULL_ASSERT    1 */
00057
00058 /* Exported macro ------------------------------------------------------------*/
00059 #ifdef  USE_FULL_ASSERT
00060
00061 /**
00062   * @brief  The assert_param macro is used for function's parameters check.
00063   * @param  expr: If expr is false, it calls assert_failed function which reports
00064   *         the name of the source file and the source line number of the call
00065   *         that failed. If expr is true, it returns no value.
00066   * @retval None
00067   */
00068   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00069 /* Exported functions ------------------------------------------------------- */
00070   void assert_failed(uint8_t* file, uint32_t line);
00071 #else
00072   #define assert_param(expr) ((void)0)
00073 #endif /* USE_FULL_ASSERT */
00074
00075 #endif /* __STM32F10x_CONF_H */
00076
00077 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_it.c

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00001 /**
00002   ******************************************************************************
00003   * @file    TIM/TimeBase/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and peripherals
00009   *          interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026
00027 /** @addtogroup STM32F10x_StdPeriph_Examples
00028   * @{
00029   */
00030
00031 /** @addtogroup TIM_TimeBase
00032   * @{
00033   */
00034
00035 /* Private typedef -----------------------------------------------------------*/
00036 /* Private define ------------------------------------------------------------*/
00037 /* Private macro -------------------------------------------------------------*/
00038 /* Private variables ---------------------------------------------------------*/
00039 uint16_t capture = 0;
00040 extern __IO uint16_t CCR1_Val;
00041 extern __IO uint16_t CCR2_Val;
00042 extern __IO uint16_t CCR3_Val;
00043 extern __IO uint16_t CCR4_Val;
00044
00045 /* Private function prototypes -----------------------------------------------*/
00046 /* Private functions ---------------------------------------------------------*/
00047
00048 /******************************************************************************/
00049 /*            Cortex-M3 Processor Exceptions Handlers                         */
00050 /******************************************************************************/
00051
00052 /**
00053   * @brief  This function handles NMI exception.
00054   * @param  None
00055   * @retval None
00056   */
00057 void NMI_Handler(void)
00058 {
00059 }
00060
00061 /**
00062   * @brief  This function handles Hard Fault exception.
00063   * @param  None
00064   * @retval None
00065   */
00066 void HardFault_Handler(void)
00067 {
00068   /* Go to infinite loop when Hard Fault exception occurs */
00069   while (1)
00070   {}
00071 }
00072
00073 /**
00074   * @brief  This function handles Memory Manage exception.
00075   * @param  None
00076   * @retval None
00077   */
00078 void MemManage_Handler(void)
00079 {
00080   /* Go to infinite loop when Memory Manage exception occurs */
00081   while (1)
00082   {}
00083 }
00084
00085 /**
00086   * @brief  This function handles Bus Fault exception.
00087   * @param  None
00088   * @retval None
00089   */
00090 void BusFault_Handler(void)
00091 {
00092   /* Go to infinite loop when Bus Fault exception occurs */
00093   while (1)
00094   {}
00095 }
00096
00097 /**
00098   * @brief  This function handles Usage Fault exception.
00099   * @param  None
00100   * @retval None
00101   */
00102 void UsageFault_Handler(void)
00103 {
00104   /* Go to infinite loop when Usage Fault exception occurs */
00105   while (1)
00106   {}
00107 }
00108
00109 /**
00110   * @brief  This function handles Debug Monitor exception.
00111   * @param  None
00112   * @retval None
00113   */
00114 void DebugMon_Handler(void)
00115 {}
00116
00117 /**
00118   * @brief  This function handles SVCall exception.
00119   * @param  None
00120   * @retval None
00121   */
00122 void SVC_Handler(void)
00123 {}
00124
00125 /**
00126   * @brief  This function handles PendSV_Handler exception.
00127   * @param  None
00128   * @retval None
00129   */
00130 void PendSV_Handler(void)
00131 {}
00132
00133 /**
00134   * @brief  This function handles SysTick Handler.
00135   * @param  None
00136   * @retval None
00137   */
00138 void SysTick_Handler(void)
00139 {}
00140
00141 /******************************************************************************/
00142 /*            STM32F10x Peripherals Interrupt Handlers                        */
00143 /******************************************************************************/
00144
00145 /**
00146   * @brief  This function handles TIM2 global interrupt request.
00147   * @param  None
00148   * @retval None
00149   */
00150 void TIM2_IRQHandler(void)
00151 {
00152   if (TIM_GetITStatus(TIM2, TIM_IT_CC1) != RESET)
00153   {
00154     TIM_ClearITPendingBit(TIM2, TIM_IT_CC1);
00155
00156     /* Pin PC.06 toggling with frequency = 73.24 Hz */
00157     GPIO_WriteBit(GPIOC, GPIO_Pin_6, (BitAction)(1 - GPIO_ReadOutputDataBit(GPIOC, GPIO_Pin_6)));
00158     capture = TIM_GetCapture1(TIM2);
00159     TIM_SetCompare1(TIM2, capture + CCR1_Val);
00160   }
00161   else if (TIM_GetITStatus(TIM2, TIM_IT_CC2) != RESET)
00162   {
00163     TIM_ClearITPendingBit(TIM2, TIM_IT_CC2);
00164
00165     /* Pin PC.07 toggling with frequency = 109.8 Hz */
00166     GPIO_WriteBit(GPIOC, GPIO_Pin_7, (BitAction)(1 - GPIO_ReadOutputDataBit(GPIOC, GPIO_Pin_7)));
00167     capture = TIM_GetCapture2(TIM2);
00168     TIM_SetCompare2(TIM2, capture + CCR2_Val);
00169   }
00170   else if (TIM_GetITStatus(TIM2, TIM_IT_CC3) != RESET)
00171   {
00172     TIM_ClearITPendingBit(TIM2, TIM_IT_CC3);
00173
00174     /* Pin PC.08 toggling with frequency = 219.7 Hz */
00175     GPIO_WriteBit(GPIOC, GPIO_Pin_8, (BitAction)(1 - GPIO_ReadOutputDataBit(GPIOC, GPIO_Pin_8)));
00176     capture = TIM_GetCapture3(TIM2);
00177     TIM_SetCompare3(TIM2, capture + CCR3_Val);
00178   }
00179   else
00180   {
00181     TIM_ClearITPendingBit(TIM2, TIM_IT_CC4);
00182
00183     /* Pin PC.09 toggling with frequency = 439.4 Hz */
00184     GPIO_WriteBit(GPIOC, GPIO_Pin_9, (BitAction)(1 - GPIO_ReadOutputDataBit(GPIOC, GPIO_Pin_9)));
00185     capture = TIM_GetCapture4(TIM2);
00186     TIM_SetCompare4(TIM2, capture + CCR4_Val);
00187   }
00188 }
00189
00190 /******************************************************************************/
00191 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00192 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00193 /*  available peripheral interrupt handler's name please refer to the startup */
00194 /*  file (startup_stm32f10x_xx.s).                                            */
00195 /******************************************************************************/
00196
00197 /**
00198   * @brief  This function handles PPP interrupt request.
00199   * @param  None
00200   * @retval None
00201   */
00202 /*void PPP_IRQHandler(void)
00203 {
00204 }*/
00205
00206 /**
00207   * @}
00208   */
00209
00210 /**
00211   * @}
00212   */
00213
00214 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_it.h

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00001 /**
00002   ******************************************************************************
00003   * @file    TIM/TimeBase/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043 void TIM2_IRQHandler(void);
00044
00045 #endif /* __STM32F10x_IT_H */
00046
00047 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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STM32F10x_StdPeriph_Examples/TIM/6Steps/main.c

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00001 /**
00002   ******************************************************************************
00003   * @file    TIM/6Steps/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x.h"
00024
00025 /** @addtogroup STM32F10x_StdPeriph_Examples
00026   * @{
00027   */
00028
00029 /** @addtogroup TIM_6Steps
00030   * @{
00031   */
00032
00033 /* Private typedef -----------------------------------------------------------*/
00034 /* Private define ------------------------------------------------------------*/
00035 /* Private macro -------------------------------------------------------------*/
00036 /* Private variables ---------------------------------------------------------*/
00037 TIM_TimeBaseInitTypeDef  TIM_TimeBaseStructure;
00038 TIM_OCInitTypeDef  TIM_OCInitStructure;
00039 TIM_BDTRInitTypeDef TIM_BDTRInitStructure;
00040 uint16_t CCR1_Val = 32767;
00041 uint16_t CCR2_Val = 24575;
00042 uint16_t CCR3_Val = 16383;
00043 uint16_t CCR4_Val = 8191;
00044
00045 /* Private function prototypes -----------------------------------------------*/
00046 void RCC_Configuration(void);
00047 void GPIO_Configuration(void);
00048 void SysTick_Configuration(void);
00049 void NVIC_Configuration(void);
00050
00051 /* Private functions ---------------------------------------------------------*/
00052
00053 /**
00054   * @brief   Main program
00055   * @param  None
00056   * @retval None
00057   */
00058 int main(void)
00059 {
00060   /*!< At this stage the microcontroller clock setting is already configured,
00061        this is done through SystemInit() function which is called from startup
00062        file (startup_stm32f10x_xx.s) before to branch to application main.
00063        To reconfigure the default setting of SystemInit() function, refer to
00064        system_stm32f10x.c file
00065      */
00066
00067   /* System Clocks Configuration */
00068   RCC_Configuration();
00069
00070   /* NVIC Configuration */
00071   NVIC_Configuration();
00072
00073   /* GPIO Configuration */
00074   GPIO_Configuration();
00075
00076   /* SysTick Configuration */
00077   SysTick_Configuration();
00078
00079   /*-----------------------------------------------------------------------------
00080   The STM32F10x TIM1 peripheral offers the possibility to program in advance the
00081   configuration for the next TIM1 outputs behaviour (step) and change the configuration
00082   of all the channels at the same time. This operation is possible when the COM
00083   (commutation) event is used.
00084   The COM event can be generated by software by setting the COM bit in the TIM1_EGR
00085   register or by hardware (on TRC rising edge).
00086   In this example, a software COM event is generated each 100 ms: using the Systick
00087   interrupt.
00088   The TIM1 is configured in Timing Mode, each time a COM event occurs,
00089   a new TIM1 configuration will be set in advance.
00090   The following Table  describes the TIM1 Channels states:
00091               -----------------------------------------------
00092              | Step1 | Step2 | Step3 | Step4 | Step5 | Step6 |
00093    ----------------------------------------------------------
00094   |Channel1  |   1   |   0   |   0   |   0   |   0   |   1   |
00095    ----------------------------------------------------------
00096   |Channel1N |   0   |   0   |   1   |   1   |   0   |   0   |
00097    ----------------------------------------------------------
00098   |Channel2  |   0   |   0   |   0   |   1   |   1   |   0   |
00099    ----------------------------------------------------------
00100   |Channel2N |   1   |   1   |   0   |   0   |   0   |   0   |
00101    ----------------------------------------------------------
00102   |Channel3  |   0   |   1   |   1   |   0   |   0   |   0   |
00103    ----------------------------------------------------------
00104   |Channel3N |   0   |   0   |   0   |   0   |   1   |   1   |
00105    ----------------------------------------------------------
00106   -----------------------------------------------------------------------------*/
00107
00108   /* Time Base configuration */
00109   TIM_TimeBaseStructure.TIM_Prescaler = 0;
00110   TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
00111   TIM_TimeBaseStructure.TIM_Period = 4095;
00112   TIM_TimeBaseStructure.TIM_ClockDivision = 0;
00113   TIM_TimeBaseStructure.TIM_RepetitionCounter = 0;
00114
00115   TIM_TimeBaseInit(TIM1, &TIM_TimeBaseStructure);
00116
00117   /* Channel 1, 2,3 and 4 Configuration in PWM mode */
00118   TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_Timing;
00119   TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
00120   TIM_OCInitStructure.TIM_OutputNState = TIM_OutputNState_Enable;
00121   TIM_OCInitStructure.TIM_Pulse = 2047;
00122   TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High;
00123   TIM_OCInitStructure.TIM_OCNPolarity = TIM_OCNPolarity_High;
00124   TIM_OCInitStructure.TIM_OCIdleState = TIM_OCIdleState_Set;
00125   TIM_OCInitStructure.TIM_OCNIdleState = TIM_OCNIdleState_Set;
00126
00127   TIM_OC1Init(TIM1, &TIM_OCInitStructure);
00128
00129   TIM_OCInitStructure.TIM_Pulse = 1023;
00130   TIM_OC2Init(TIM1, &TIM_OCInitStructure);
00131
00132   TIM_OCInitStructure.TIM_Pulse = 511;
00133   TIM_OC3Init(TIM1, &TIM_OCInitStructure);
00134
00135   /* Automatic Output enable, Break, dead time and lock configuration*/
00136   TIM_BDTRInitStructure.TIM_OSSRState = TIM_OSSRState_Enable;
00137   TIM_BDTRInitStructure.TIM_OSSIState = TIM_OSSIState_Enable;
00138   TIM_BDTRInitStructure.TIM_LOCKLevel = TIM_LOCKLevel_OFF;
00139   TIM_BDTRInitStructure.TIM_DeadTime = 1;
00140   TIM_BDTRInitStructure.TIM_Break = TIM_Break_Enable;
00141   TIM_BDTRInitStructure.TIM_BreakPolarity = TIM_BreakPolarity_High;
00142   TIM_BDTRInitStructure.TIM_AutomaticOutput = TIM_AutomaticOutput_Enable;
00143
00144   TIM_BDTRConfig(TIM1, &TIM_BDTRInitStructure);
00145
00146   TIM_CCPreloadControl(TIM1, ENABLE);
00147
00148   TIM_ITConfig(TIM1, TIM_IT_COM, ENABLE);
00149
00150   /* TIM1 counter enable */
00151   TIM_Cmd(TIM1, ENABLE);
00152
00153   /* Main Output Enable */
00154   TIM_CtrlPWMOutputs(TIM1, ENABLE);
00155
00156   while (1)
00157   {}
00158 }
00159
00160 /**
00161   * @brief  Configures the different system clocks.
00162   * @param  None
00163   * @retval None
00164   */
00165 void RCC_Configuration(void)
00166 {
00167   /* TIM1, GPIOA, GPIOB, GPIOE and AFIO clocks enable */
00168   RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM1 | RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOE|
00169                          RCC_APB2Periph_GPIOB |RCC_APB2Periph_AFIO, ENABLE);
00170 }
00171
00172 /**
00173   * @brief  Configure the TIM1 Pins.
00174   * @param  None
00175   * @retval None
00176   */
00177 void GPIO_Configuration(void)
00178 {
00179   GPIO_InitTypeDef GPIO_InitStructure;
00180
00181 #ifdef STM32F10X_CL
00182   /* GPIOE Configuration: Channel 1/1N, 2/2N, 3/3N as alternate function push-pull */
00183   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9|GPIO_Pin_11|GPIO_Pin_13|
00184                                 GPIO_Pin_8|GPIO_Pin_10|GPIO_Pin_12;
00185   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
00186   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00187
00188   GPIO_Init(GPIOE, &GPIO_InitStructure);
00189
00190   /* GPIOE Configuration: BKIN pin */
00191   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_15;
00192   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
00193   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00194
00195   GPIO_Init(GPIOE, &GPIO_InitStructure);
00196
00197   /* TIM1 Full remapping pins */
00198   GPIO_PinRemapConfig(GPIO_FullRemap_TIM1, ENABLE);
00199
00200 #else
00201   /* GPIOA Configuration: Channel 1, 2 and 3 as alternate function push-pull */
00202   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10;
00203   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
00204   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00205   GPIO_Init(GPIOA, &GPIO_InitStructure);
00206
00207   /* GPIOB Configuration: Channel 1N, 2N and 3N as alternate function push-pull */
00208   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15;
00209   GPIO_Init(GPIOB, &GPIO_InitStructure);
00210
00211   /* GPIOB Configuration: BKIN pin */
00212   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12;
00213   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
00214   GPIO_Init(GPIOB, &GPIO_InitStructure);
00215 #endif
00216 }
00217
00218 /**
00219   * @brief  Configures the SysTick.
00220   * @param  None
00221   * @retval None
00222   */
00223 void SysTick_Configuration(void)
00224 {
00225   /* Setup SysTick Timer for 100 msec interrupts  */
00226   if (SysTick_Config((SystemCoreClock) / 10))
00227   {
00228     /* Capture error */
00229     while (1);
00230   }
00231
00232    NVIC_SetPriority(SysTick_IRQn, 0x0);
00233 }
00234
00235 /**
00236   * @brief  Configures the nested vectored interrupt controller.
00237   * @param  None
00238   * @retval None
00239   */
00240 void NVIC_Configuration(void)
00241 {
00242   NVIC_InitTypeDef NVIC_InitStructure;
00243
00244   /* Enable the TIM1 Interrupt */
00245 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00246   NVIC_InitStructure.NVIC_IRQChannel = TIM1_TRG_COM_TIM17_IRQn;
00247 #else
00248   NVIC_InitStructure.NVIC_IRQChannel = TIM1_TRG_COM_IRQn;
00249 #endif
00250   NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
00251   NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;
00252   NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
00253   NVIC_Init(&NVIC_InitStructure);
00254
00255 }
00256
00257 #ifdef  USE_FULL_ASSERT
00258
00259 /**
00260   * @brief  Reports the name of the source file and the source line number
00261   *         where the assert_param error has occurred.
00262   * @param  file: pointer to the source file name
00263   * @param  line: assert_param error line source number
00264   * @retval None
00265   */
00266 void assert_failed(uint8_t* file, uint32_t line)
00267 {
00268   /* User can add his own implementation to report the file name and line number,
00269      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00270
00271   while (1)
00272   {}
00273 }
00274
00275 #endif
00276 /**
00277   * @}
00278   */
00279
00280 /**
00281   * @}
00282   */
00283
00284 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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STM32F10x_StdPeriph_Examples/TIM/6Steps/stm32f10x_conf.h

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00001 /**
00002   ******************************************************************************
00003   * @file    TIM/6Steps/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052
00053 /* Exported types ------------------------------------------------------------*/
00054 /* Exported constants --------------------------------------------------------*/
00055 /* Uncomment the line below to expanse the "assert_param" macro in the
00056    Standard Peripheral Library drivers code */
00057 /* #define USE_FULL_ASSERT    1 */
00058
00059 /* Exported macro ------------------------------------------------------------*/
00060 #ifdef  USE_FULL_ASSERT
00061
00062 /**
00063   * @brief  The assert_param macro is used for function's parameters check.
00064   * @param  expr: If expr is false, it calls assert_failed function which reports
00065   *         the name of the source file and the source line number of the call
00066   *         that failed. If expr is true, it returns no value.
00067   * @retval None
00068   */
00069   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00070 /* Exported functions ------------------------------------------------------- */
00071   void assert_failed(uint8_t* file, uint32_t line);
00072 #else
00073   #define assert_param(expr) ((void)0)
00074 #endif /* USE_FULL_ASSERT */
00075
00076 #endif /* __STM32F10x_CONF_H */
00077
00078 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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STM32F10x_StdPeriph_Examples/TIM/6Steps/stm32f10x_it.c

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00001 /**
00002   ******************************************************************************
00003   * @file    TIM/6Steps/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and peripherals
00009   *          interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026
00027 /** @addtogroup STM32F10x_StdPeriph_Examples
00028   * @{
00029   */
00030
00031 /** @addtogroup TIM_6Steps
00032   * @{
00033   */
00034
00035 /* Private typedef -----------------------------------------------------------*/
00036 /* Private define ------------------------------------------------------------*/
00037 /* Private macro -------------------------------------------------------------*/
00038 /* Private variables ---------------------------------------------------------*/
00039 __IO uint32_t step = 1;
00040
00041 /* Private function prototypes -----------------------------------------------*/
00042 /* Private functions ---------------------------------------------------------*/
00043
00044 /******************************************************************************/
00045 /*            Cortex-M3 Processor Exceptions Handlers                         */
00046 /******************************************************************************/
00047
00048 /**
00049   * @brief  This function handles NMI exception.
00050   * @param  None
00051   * @retval None
00052   */
00053 void NMI_Handler(void)
00054 {
00055 }
00056
00057 /**
00058   * @brief  This function handles Hard Fault exception.
00059   * @param  None
00060   * @retval None
00061   */
00062 void HardFault_Handler(void)
00063 {
00064   /* Go to infinite loop when Hard Fault exception occurs */
00065   while (1)
00066   {}
00067 }
00068
00069 /**
00070   * @brief  This function handles Memory Manage exception.
00071   * @param  None
00072   * @retval None
00073   */
00074 void MemManage_Handler(void)
00075 {
00076   /* Go to infinite loop when Memory Manage exception occurs */
00077   while (1)
00078   {}
00079 }
00080
00081 /**
00082   * @brief  This function handles Bus Fault exception.
00083   * @param  None
00084   * @retval None
00085   */
00086 void BusFault_Handler(void)
00087 {
00088   /* Go to infinite loop when Bus Fault exception occurs */
00089   while (1)
00090   {}
00091 }
00092
00093 /**
00094   * @brief  This function handles Usage Fault exception.
00095   * @param  None
00096   * @retval None
00097   */
00098 void UsageFault_Handler(void)
00099 {
00100   /* Go to infinite loop when Usage Fault exception occurs */
00101   while (1)
00102   {}
00103 }
00104
00105 /**
00106   * @brief  This function handles Debug Monitor exception.
00107   * @param  None
00108   * @retval None
00109   */
00110 void DebugMon_Handler(void)
00111 {}
00112
00113 /**
00114   * @brief  This function handles SVCall exception.
00115   * @param  None
00116   * @retval None
00117   */
00118 void SVC_Handler(void)
00119 {}
00120
00121 /**
00122   * @brief  This function handles PendSV_Handler exception.
00123   * @param  None
00124   * @retval None
00125   */
00126 void PendSV_Handler(void)
00127 {}
00128
00129 /**
00130   * @brief  This function handles SysTick Handler.
00131   * @param  None
00132   * @retval None
00133   */
00134 void SysTick_Handler(void)
00135 {
00136   /* Generate TIM1 COM event by software */
00137   TIM_GenerateEvent(TIM1, TIM_EventSource_COM);
00138 }
00139
00140 /******************************************************************************/
00141 /*            STM32F10x Peripherals Interrupt Handlers                        */
00142 /******************************************************************************/
00143
00144 /**
00145   * @brief  This function handles TIM1 Trigger and commutation interrupts
00146   *   requests.
00147   * @param  None
00148   * @retval None
00149   */
00150 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00151 void TIM1_TRG_COM_TIM17_IRQHandler(void)
00152 #else
00153 void TIM1_TRG_COM_IRQHandler(void)
00154 #endif
00155 {
00156    /* Clear TIM1 COM pending bit */
00157    TIM_ClearITPendingBit(TIM1, TIM_IT_COM);
00158
00159   if (step == 1)
00160   {
00161     /* Next step: Step 2 Configuration ---------------------------- */
00162     /*  Channel3 configuration */
00163     TIM_CCxCmd(TIM1, TIM_Channel_3, TIM_CCx_Disable);
00164     TIM_CCxNCmd(TIM1, TIM_Channel_3, TIM_CCxN_Disable);
00165
00166     /*  Channel1 configuration */
00167     TIM_SelectOCxM(TIM1, TIM_Channel_1, TIM_OCMode_PWM1);
00168     TIM_CCxCmd(TIM1, TIM_Channel_1, TIM_CCx_Enable);
00169     TIM_CCxNCmd(TIM1, TIM_Channel_1, TIM_CCxN_Disable);
00170
00171     /*  Channel2 configuration */
00172     TIM_SelectOCxM(TIM1, TIM_Channel_2, TIM_OCMode_PWM1 );
00173     TIM_CCxCmd(TIM1, TIM_Channel_2, TIM_CCx_Disable);
00174     TIM_CCxNCmd(TIM1, TIM_Channel_2, TIM_CCxN_Enable);
00175     step++;
00176   }
00177   else if (step == 2)
00178   {
00179     /* Next step: Step 3 Configuration ---------------------------- */
00180     /*  Channel2 configuration */
00181     TIM_SelectOCxM(TIM1, TIM_Channel_2, TIM_OCMode_PWM1);
00182     TIM_CCxCmd(TIM1, TIM_Channel_2, TIM_CCx_Disable);
00183     TIM_CCxNCmd(TIM1, TIM_Channel_2, TIM_CCxN_Enable);
00184
00185     /*  Channel3 configuration */
00186     TIM_SelectOCxM(TIM1, TIM_Channel_3, TIM_OCMode_PWM1);
00187     TIM_CCxCmd(TIM1, TIM_Channel_3, TIM_CCx_Enable);
00188      TIM_CCxNCmd(TIM1, TIM_Channel_3, TIM_CCxN_Disable);
00189
00190     /*  Channel1 configuration */
00191     TIM_CCxCmd(TIM1, TIM_Channel_1, TIM_CCx_Disable);
00192     TIM_CCxNCmd(TIM1, TIM_Channel_1, TIM_CCxN_Disable);
00193     step++;
00194   }
00195   else if (step == 3)
00196   {
00197     /* Next step: Step 4 Configuration ---------------------------- */
00198     /*  Channel3 configuration */
00199     TIM_SelectOCxM(TIM1, TIM_Channel_3, TIM_OCMode_PWM1);
00200     TIM_CCxCmd(TIM1, TIM_Channel_3, TIM_CCx_Enable);
00201     TIM_CCxNCmd(TIM1, TIM_Channel_3, TIM_CCxN_Disable);
00202
00203     /*  Channel2 configuration */
00204     TIM_CCxCmd(TIM1, TIM_Channel_2, TIM_CCx_Disable);
00205     TIM_CCxNCmd(TIM1, TIM_Channel_2, TIM_CCxN_Disable);
00206
00207     /*  Channel1 configuration */
00208     TIM_SelectOCxM(TIM1, TIM_Channel_1, TIM_OCMode_PWM1);
00209     TIM_CCxCmd(TIM1, TIM_Channel_1, TIM_CCx_Disable);
00210     TIM_CCxNCmd(TIM1, TIM_Channel_1, TIM_CCxN_Enable);
00211     step++;
00212   }
00213   else if (step == 4)
00214   {
00215     /* Next step: Step 5 Configuration ---------------------------- */
00216     /*  Channel3 configuration */
00217     TIM_CCxCmd(TIM1, TIM_Channel_3, TIM_CCx_Disable);
00218     TIM_CCxNCmd(TIM1, TIM_Channel_3, TIM_CCxN_Disable);
00219
00220     /*  Channel1 configuration */
00221     TIM_SelectOCxM(TIM1, TIM_Channel_1, TIM_OCMode_PWM1);
00222     TIM_CCxCmd(TIM1, TIM_Channel_1, TIM_CCx_Disable);
00223     TIM_CCxNCmd(TIM1, TIM_Channel_1, TIM_CCxN_Enable);
00224
00225     /*  Channel2 configuration */
00226     TIM_SelectOCxM(TIM1, TIM_Channel_2, TIM_OCMode_PWM1);
00227     TIM_CCxCmd(TIM1, TIM_Channel_2, TIM_CCx_Enable);
00228     TIM_CCxNCmd(TIM1, TIM_Channel_2, TIM_CCxN_Disable);
00229     step++;
00230   }
00231   else if (step == 5)
00232   {
00233     /* Next step: Step 6 Configuration ---------------------------- */
00234     /*  Channel3 configuration */
00235     TIM_SelectOCxM(TIM1, TIM_Channel_3, TIM_OCMode_PWM1);
00236     TIM_CCxCmd(TIM1, TIM_Channel_3, TIM_CCx_Disable);
00237     TIM_CCxNCmd(TIM1, TIM_Channel_3, TIM_CCxN_Enable);
00238
00239     /*  Channel1 configuration */
00240     TIM_CCxCmd(TIM1, TIM_Channel_1, TIM_CCx_Disable);
00241     TIM_CCxNCmd(TIM1, TIM_Channel_1, TIM_CCxN_Disable);
00242
00243     /*  Channel2 configuration */
00244     TIM_SelectOCxM(TIM1, TIM_Channel_2, TIM_OCMode_PWM1);
00245     TIM_CCxCmd(TIM1, TIM_Channel_2, TIM_CCx_Enable);
00246     TIM_CCxNCmd(TIM1, TIM_Channel_2, TIM_CCxN_Disable);
00247     step++;
00248   }
00249   else
00250   {
00251     /* Next step: Step 1 Configuration ---------------------------- */
00252     /*  Channel1 configuration */
00253     TIM_SelectOCxM(TIM1, TIM_Channel_1, TIM_OCMode_PWM1);
00254     TIM_CCxCmd(TIM1, TIM_Channel_1, TIM_CCx_Enable);
00255     TIM_CCxNCmd(TIM1, TIM_Channel_2, TIM_CCxN_Disable);
00256
00257     /*  Channel3 configuration */
00258     TIM_SelectOCxM(TIM1, TIM_Channel_3, TIM_OCMode_PWM1);
00259     TIM_CCxCmd(TIM1, TIM_Channel_3, TIM_CCx_Disable);
00260     TIM_CCxNCmd(TIM1, TIM_Channel_3, TIM_CCxN_Enable);
00261
00262     /*  Channel2 configuration */
00263     TIM_CCxCmd(TIM1, TIM_Channel_2, TIM_CCx_Disable);
00264     TIM_CCxNCmd(TIM1, TIM_Channel_2, TIM_CCxN_Disable);
00265     step = 1;
00266   }
00267 }
00268
00269 /******************************************************************************/
00270 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00271 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00272 /*  available peripheral interrupt handler's name please refer to the startup */
00273 /*  file (startup_stm32f10x_xx.s).                                            */
00274 /******************************************************************************/
00275
00276 /**
00277   * @brief  This function handles PPP interrupt request.
00278   * @param  None
00279   * @retval None
00280   */
00281 /*void PPP_IRQHandler(void)
00282 {
00283 }*/
00284
00285 /**
00286   * @}
00287   */
00288
00289 /**
00290   * @}
00291   */
00292
00293 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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STM32F10x_StdPeriph_Examples/TIM/6Steps/stm32f10x_it.h

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00001 /**
00002   ******************************************************************************
00003   * @file    TIM/6Steps/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL)
00044 void TIM1_TRG_COM_TIM17_IRQHandler(void);
00045 #else
00046 void TIM1_TRG_COM_IRQHandler(void);
00047 #endif
00048
00049 #endif /* __STM32F10x_IT_H */
00050
00051 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/main.c

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00001 /**
00002   ******************************************************************************
00003   * @file    TIM/7PWM_Output/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x.h"
00024
00025 /** @addtogroup STM32F10x_StdPeriph_Examples
00026   * @{
00027   */
00028
00029 /** @addtogroup TIM_7PWM_Output
00030   * @{
00031   */
00032
00033 /* Private typedef -----------------------------------------------------------*/
00034 /* Private define ------------------------------------------------------------*/
00035 /* Private macro -------------------------------------------------------------*/
00036 /* Private variables ---------------------------------------------------------*/
00037 TIM_TimeBaseInitTypeDef  TIM_TimeBaseStructure;
00038 TIM_OCInitTypeDef  TIM_OCInitStructure;
00039 uint16_t TimerPeriod = 0;
00040 uint16_t Channel1Pulse = 0, Channel2Pulse = 0, Channel3Pulse = 0, Channel4Pulse = 0;
00041
00042 /* Private function prototypes -----------------------------------------------*/
00043 void RCC_Configuration(void);
00044 void GPIO_Configuration(void);
00045
00046 /* Private functions ---------------------------------------------------------*/
00047
00048 /**
00049   * @brief   Main program
00050   * @param  None
00051   * @retval None
00052   */
00053 int main(void)
00054 {
00055   /*!< At this stage the microcontroller clock setting is already configured,
00056        this is done through SystemInit() function which is called from startup
00057        file (startup_stm32f10x_xx.s) before to branch to application main.
00058        To reconfigure the default setting of SystemInit() function, refer to
00059        system_stm32f10x.c file
00060      */
00061
00062   /* System Clocks Configuration */
00063   RCC_Configuration();
00064
00065   /* GPIO Configuration */
00066   GPIO_Configuration();
00067
00068   /* TIM1 Configuration ---------------------------------------------------
00069    Generate 7 PWM signals with 4 different duty cycles:
00070    TIM1CLK = SystemCoreClock, Prescaler = 0, TIM1 counter clock = SystemCoreClock
00071    SystemCoreClock is set to 72 MHz for Low-density, Medium-density, High-density
00072    and Connectivity line devices and to 24 MHz for Low-Density Value line and
00073    Medium-Density Value line devices
00074
00075    The objective is to generate 7 PWM signal at 17.57 KHz:
00076      - TIM1_Period = (SystemCoreClock / 17570) - 1
00077    The channel 1 and channel 1N duty cycle is set to 50%
00078    The channel 2 and channel 2N duty cycle is set to 37.5%
00079    The channel 3 and channel 3N duty cycle is set to 25%
00080    The channel 4 duty cycle is set to 12.5%
00081    The Timer pulse is calculated as follows:
00082      - ChannelxPulse = DutyCycle * (TIM1_Period - 1) / 100
00083   ----------------------------------------------------------------------- */
00084   /* Compute the value to be set in ARR regiter to generate signal frequency at 17.57 Khz */
00085   TimerPeriod = (SystemCoreClock / 17570 ) - 1;
00086   /* Compute CCR1 value to generate a duty cycle at 50% for channel 1 and 1N */
00087   Channel1Pulse = (uint16_t) (((uint32_t) 5 * (TimerPeriod - 1)) / 10);
00088   /* Compute CCR2 value to generate a duty cycle at 37.5%  for channel 2 and 2N */
00089   Channel2Pulse = (uint16_t) (((uint32_t) 375 * (TimerPeriod - 1)) / 1000);
00090   /* Compute CCR3 value to generate a duty cycle at 25%  for channel 3 and 3N */
00091   Channel3Pulse = (uint16_t) (((uint32_t) 25 * (TimerPeriod - 1)) / 100);
00092   /* Compute CCR4 value to generate a duty cycle at 12.5%  for channel 4 */
00093   Channel4Pulse = (uint16_t) (((uint32_t) 125 * (TimerPeriod- 1)) / 1000);
00094
00095   /* Time Base configuration */
00096   TIM_TimeBaseStructure.TIM_Prescaler = 0;
00097   TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
00098   TIM_TimeBaseStructure.TIM_Period = TimerPeriod;
00099   TIM_TimeBaseStructure.TIM_ClockDivision = 0;
00100   TIM_TimeBaseStructure.TIM_RepetitionCounter = 0;
00101
00102   TIM_TimeBaseInit(TIM1, &TIM_TimeBaseStructure);
00103
00104   /* Channel 1, 2,3 and 4 Configuration in PWM mode */
00105   TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM2;
00106   TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
00107   TIM_OCInitStructure.TIM_OutputNState = TIM_OutputNState_Enable;
00108   TIM_OCInitStructure.TIM_Pulse = Channel1Pulse;
00109   TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_Low;
00110   TIM_OCInitStructure.TIM_OCNPolarity = TIM_OCNPolarity_High;
00111   TIM_OCInitStructure.TIM_OCIdleState = TIM_OCIdleState_Set;
00112   TIM_OCInitStructure.TIM_OCNIdleState = TIM_OCIdleState_Reset;
00113
00114   TIM_OC1Init(TIM1, &TIM_OCInitStructure);
00115
00116   TIM_OCInitStructure.TIM_Pulse = Channel2Pulse;
00117   TIM_OC2Init(TIM1, &TIM_OCInitStructure);
00118
00119   TIM_OCInitStructure.TIM_Pulse = Channel3Pulse;
00120   TIM_OC3Init(TIM1, &TIM_OCInitStructure);
00121
00122   TIM_OCInitStructure.TIM_Pulse = Channel4Pulse;
00123   TIM_OC4Init(TIM1, &TIM_OCInitStructure);
00124
00125   /* TIM1 counter enable */
00126   TIM_Cmd(TIM1, ENABLE);
00127
00128   /* TIM1 Main Output Enable */
00129   TIM_CtrlPWMOutputs(TIM1, ENABLE);
00130
00131   while (1)
00132   {}
00133 }
00134
00135 /**
00136   * @brief  Configures the different system clocks.
00137   * @param  None
00138   * @retval None
00139   */
00140 void RCC_Configuration(void)
00141 {
00142   /* TIM1, GPIOA, GPIOB, GPIOE and AFIO clocks enable */
00143   RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM1 | RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOE|
00144                          RCC_APB2Periph_GPIOB |RCC_APB2Periph_AFIO, ENABLE);
00145 }
00146
00147 /**
00148   * @brief  Configure the TIM1 Pins.
00149   * @param  None
00150   * @retval None
00151   */
00152 void GPIO_Configuration(void)
00153 {
00154   GPIO_InitTypeDef GPIO_InitStructure;
00155
00156 #ifdef STM32F10X_CL
00157   /* GPIOE Configuration: Channel 1/1N, 2/2N, 3/3N and 4 as alternate function push-pull */
00158   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9|GPIO_Pin_11|GPIO_Pin_13|GPIO_Pin_14|
00159                                 GPIO_Pin_8|GPIO_Pin_10|GPIO_Pin_12;
00160   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
00161   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00162
00163   GPIO_Init(GPIOE, &GPIO_InitStructure);
00164
00165   /* TIM1 Full remapping pins */
00166   GPIO_PinRemapConfig(GPIO_FullRemap_TIM1, ENABLE);
00167
00168 #else
00169   /* GPIOA Configuration: Channel 1, 2 and 3 as alternate function push-pull */
00170   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11;
00171   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
00172   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00173   GPIO_Init(GPIOA, &GPIO_InitStructure);
00174
00175   /* GPIOB Configuration: Channel 1N, 2N and 3N as alternate function push-pull */
00176   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15;
00177   GPIO_Init(GPIOB, &GPIO_InitStructure);
00178
00179 #endif
00180 }
00181
00182 #ifdef  USE_FULL_ASSERT
00183
00184 /**
00185   * @brief  Reports the name of the source file and the source line number
00186   *         where the assert_param error has occurred.
00187   * @param  file: pointer to the source file name
00188   * @param  line: assert_param error line source number
00189   * @retval None
00190   */
00191 void assert_failed(uint8_t* file, uint32_t line)
00192 {
00193   /* User can add his own implementation to report the file name and line number,
00194      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00195
00196   while (1)
00197   {}
00198 }
00199
00200 #endif
00201
00202 /**
00203   * @}
00204   */
00205
00206 /**
00207   * @}
00208   */
00209
00210 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/stm32f10x_conf.h

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00001 /**
00002   ******************************************************************************
00003   * @file    TIM/7PWM_Output/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052
00053 /* Exported types ------------------------------------------------------------*/
00054 /* Exported constants --------------------------------------------------------*/
00055 /* Uncomment the line below to expanse the "assert_param" macro in the
00056    Standard Peripheral Library drivers code */
00057 /* #define USE_FULL_ASSERT    1 */
00058
00059 /* Exported macro ------------------------------------------------------------*/
00060 #ifdef  USE_FULL_ASSERT
00061
00062 /**
00063   * @brief  The assert_param macro is used for function's parameters check.
00064   * @param  expr: If expr is false, it calls assert_failed function which reports
00065   *         the name of the source file and the source line number of the call
00066   *         that failed. If expr is true, it returns no value.
00067   * @retval None
00068   */
00069   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00070 /* Exported functions ------------------------------------------------------- */
00071   void assert_failed(uint8_t* file, uint32_t line);
00072 #else
00073   #define assert_param(expr) ((void)0)
00074 #endif /* USE_FULL_ASSERT */
00075
00076 #endif /* __STM32F10x_CONF_H */
00077
00078 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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  • 7PWM_Output

STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/stm32f10x_it.c

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00001 /**
00002   ******************************************************************************
00003   * @file    TIM/7PWM_Output/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and peripherals
00009   *          interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026
00027 /** @addtogroup STM32F10x_StdPeriph_Examples
00028   * @{
00029   */
00030
00031 /** @addtogroup TIM_7PWM_Output
00032   * @{
00033   */
00034
00035 /* Private typedef -----------------------------------------------------------*/
00036 /* Private define ------------------------------------------------------------*/
00037 /* Private macro -------------------------------------------------------------*/
00038 /* Private variables ---------------------------------------------------------*/
00039 /* Private function prototypes -----------------------------------------------*/
00040 /* Private functions ---------------------------------------------------------*/
00041
00042 /******************************************************************************/
00043 /*            Cortex-M3 Processor Exceptions Handlers                         */
00044 /******************************************************************************/
00045
00046 /**
00047   * @brief  This function handles NMI exception.
00048   * @param  None
00049   * @retval None
00050   */
00051 void NMI_Handler(void)
00052 {}
00053
00054 /**
00055   * @brief  This function handles Hard Fault exception.
00056   * @param  None
00057   * @retval None
00058   */
00059 void HardFault_Handler(void)
00060 {
00061   /* Go to infinite loop when Hard Fault exception occurs */
00062   while (1)
00063   {}
00064 }
00065
00066 /**
00067   * @brief  This function handles Memory Manage exception.
00068   * @param  None
00069   * @retval None
00070   */
00071 void MemManage_Handler(void)
00072 {
00073   /* Go to infinite loop when Memory Manage exception occurs */
00074   while (1)
00075   {}
00076 }
00077
00078 /**
00079   * @brief  This function handles Bus Fault exception.
00080   * @param  None
00081   * @retval None
00082   */
00083 void BusFault_Handler(void)
00084 {
00085   /* Go to infinite loop when Bus Fault exception occurs */
00086   while (1)
00087   {}
00088 }
00089
00090 /**
00091   * @brief  This function handles Usage Fault exception.
00092   * @param  None
00093   * @retval None
00094   */
00095 void UsageFault_Handler(void)
00096 {
00097   /* Go to infinite loop when Usage Fault exception occurs */
00098   while (1)
00099   {}
00100 }
00101
00102 /**
00103   * @brief  This function handles Debug Monitor exception.
00104   * @param  None
00105   * @retval None
00106   */
00107 void DebugMon_Handler(void)
00108 {}
00109
00110 /**
00111   * @brief  This function handles SVCall exception.
00112   * @param  None
00113   * @retval None
00114   */
00115 void SVC_Handler(void)
00116 {}
00117
00118 /**
00119   * @brief  This function handles PendSV_Handler exception.
00120   * @param  None
00121   * @retval None
00122   */
00123 void PendSV_Handler(void)
00124 {}
00125
00126 /**
00127   * @brief  This function handles SysTick Handler.
00128   * @param  None
00129   * @retval None
00130   */
00131 void SysTick_Handler(void)
00132 {}
00133
00134 /******************************************************************************/
00135 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00136 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00137 /*  available peripheral interrupt handler's name please refer to the startup */
00138 /*  file (startup_stm32f10x_xx.s).                                            */
00139 /******************************************************************************/
00140
00141 /**
00142   * @brief  This function handles PPP interrupt request.
00143   * @param  None
00144   * @retval None
00145   */
00146 /*void PPP_IRQHandler(void)
00147 {
00148 }*/
00149
00150 /**
00151   * @}
00152   */
00153
00154 /**
00155   * @}
00156   */
00157
00158 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/stm32f10x_it.h

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00001 /**
00002   ******************************************************************************
00003   * @file    TIM/7PWM_Output/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043
00044 #endif /* __STM32F10x_IT_H */
00045
00046 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/main.c

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00001 /**
00002   ******************************************************************************
00003   * @file    USART/DMA_Interrupt/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x.h"
00024 #include "platform_config.h"
00025
00026 /** @addtogroup STM32F10x_StdPeriph_Examples
00027   * @{
00028   */
00029
00030 /** @addtogroup USART_DMA_Interrupt
00031   * @{
00032   */
00033
00034 /* Private typedef -----------------------------------------------------------*/
00035 typedef enum {FAILED = 0, PASSED = !FAILED} TestStatus;
00036
00037 /* Private define ------------------------------------------------------------*/
00038 #define TxBufferSize1   (countof(TxBuffer1) - 1)
00039 #define TxBufferSize2   (countof(TxBuffer2) - 1)
00040
00041 /* Private macro -------------------------------------------------------------*/
00042 #define countof(a)   (sizeof(a) / sizeof(*(a)))
00043
00044 /* Private variables ---------------------------------------------------------*/
00045 USART_InitTypeDef USART_InitStructure;
00046 uint8_t TxBuffer1[] = "USART DMA Interrupt: USARTy -> USARTz using DMA Tx and Rx Flag";
00047 uint8_t TxBuffer2[] = "USART DMA Interrupt: USARTz -> USARTy using DMA Tx and Rx Interrupt";
00048 uint8_t RxBuffer1[TxBufferSize2];
00049 uint8_t RxBuffer2[TxBufferSize1];
00050 uint8_t NbrOfDataToRead = TxBufferSize1;
00051 uint32_t index = 0;
00052 volatile TestStatus TransferStatus1 = FAILED, TransferStatus2 = FAILED;
00053
00054 /* Private function prototypes -----------------------------------------------*/
00055 void RCC_Configuration(void);
00056 void GPIO_Configuration(void);
00057 void NVIC_Configuration(void);
00058 void DMA_Configuration(void);
00059 TestStatus Buffercmp(uint8_t* pBuffer1, uint8_t* pBuffer2, uint16_t BufferLength);
00060
00061 /* Private functions ---------------------------------------------------------*/
00062
00063 /**
00064   * @brief  Main program
00065   * @param  None
00066   * @retval None
00067   */
00068 int main(void)
00069 {
00070   /*!< At this stage the microcontroller clock setting is already configured,
00071        this is done through SystemInit() function which is called from startup
00072        file (startup_stm32f10x_xx.s) before to branch to application main.
00073        To reconfigure the default setting of SystemInit() function, refer to
00074        system_stm32f10x.c file
00075      */
00076
00077   /* System Clocks Configuration */
00078   RCC_Configuration();
00079
00080   /* NVIC configuration */
00081   NVIC_Configuration();
00082
00083   /* Configure the GPIO ports */
00084   GPIO_Configuration();
00085
00086   /* Configure the DMA */
00087   DMA_Configuration();
00088
00089 /* USARTy and USARTz configuration -------------------------------------------*/
00090   /* USARTy and USARTz configured as follow:
00091         - BaudRate = 230400 baud
00092         - Word Length = 8 Bits
00093         - One Stop Bit
00094         - No parity
00095         - Hardware flow control disabled (RTS and CTS signals)
00096         - Receive and transmit enabled
00097   */
00098
00099   USART_InitStructure.USART_BaudRate = 230400;
00100   USART_InitStructure.USART_WordLength = USART_WordLength_8b;
00101   USART_InitStructure.USART_StopBits = USART_StopBits_1;
00102   USART_InitStructure.USART_Parity = USART_Parity_No;
00103   USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
00104   USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
00105
00106   /* Configure USARTy */
00107   USART_Init(USARTy, &USART_InitStructure);
00108
00109   /* Configure USARTz */
00110   USART_Init(USARTz, &USART_InitStructure);
00111
00112   /* Enable USARTy DMA TX request */
00113   USART_DMACmd(USARTy, USART_DMAReq_Tx, ENABLE);
00114
00115   /* Enable USARTz DMA TX request */
00116   USART_DMACmd(USARTz, USART_DMAReq_Tx, ENABLE);
00117
00118   /* Enable the USARTz Receive Interrupt */
00119   USART_ITConfig(USARTz, USART_IT_RXNE, ENABLE);
00120
00121   /* Enable USARTy */
00122   USART_Cmd(USARTy, ENABLE);
00123
00124   /* Enable USARTz */
00125   USART_Cmd(USARTz, ENABLE);
00126
00127   /* Enable USARTy DMA TX Channel */
00128   DMA_Cmd(USARTy_Tx_DMA_Channel, ENABLE);
00129
00130   /* Enable USARTz DMA TX Channel */
00131   DMA_Cmd(USARTz_Tx_DMA_Channel, ENABLE);
00132
00133   /* Receive the TxBuffer2 */
00134   while(index < TxBufferSize2)
00135   {
00136      while(USART_GetFlagStatus(USARTy, USART_FLAG_RXNE) == RESET)
00137      {
00138      }
00139      RxBuffer1[index++] = USART_ReceiveData(USARTy);
00140   }
00141
00142   /* Wait until USARTy TX DMA1 Channel  Transfer Complete */
00143   while (DMA_GetFlagStatus(USARTy_Tx_DMA_FLAG) == RESET)
00144   {
00145   }
00146   /* Wait until USARTz TX DMA1 Channel Transfer Complete */
00147   while (DMA_GetFlagStatus(USARTz_Tx_DMA_FLAG) == RESET)
00148   {
00149   }
00150
00151   /* Check the received data with the send ones */
00152   TransferStatus1 = Buffercmp(TxBuffer2, RxBuffer1, TxBufferSize2);
00153   /* TransferStatus1 = PASSED, if the data transmitted from USARTz and
00154      received by USARTy are the same */
00155   /* TransferStatus1 = FAILED, if the data transmitted from USARTz and
00156      received by USARTy are different */
00157   TransferStatus2 = Buffercmp(TxBuffer1, RxBuffer2, TxBufferSize1);
00158   /* TransferStatus2 = PASSED, if the data transmitted from USARTy and
00159      received by USARTz are the same */
00160   /* TransferStatus2 = FAILED, if the data transmitted from USARTy and
00161      received by USARTz are different */
00162
00163   while (1)
00164   {
00165   }
00166 }
00167
00168 /**
00169   * @brief  Configures the different system clocks.
00170   * @param  None
00171   * @retval None
00172   */
00173 void RCC_Configuration(void)
00174 {
00175   /* DMA clock enable */
00176   RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE);
00177
00178   /* Enable GPIO clock */
00179   RCC_APB2PeriphClockCmd(USARTy_GPIO_CLK | USARTz_GPIO_CLK | RCC_APB2Periph_AFIO, ENABLE);
00180
00181 #ifndef USE_STM3210C_EVAL
00182   /* Enable USARTy Clock */
00183   RCC_APB2PeriphClockCmd(USARTy_CLK, ENABLE);
00184 #else
00185   /* Enable USARTy Clock */
00186   RCC_APB1PeriphClockCmd(USARTy_CLK, ENABLE);
00187 #endif
00188   /* Enable USARTz Clock */
00189   RCC_APB1PeriphClockCmd(USARTz_CLK, ENABLE);
00190 }
00191
00192 /**
00193   * @brief  Configures the different GPIO ports.
00194   * @param  None
00195   * @retval None
00196   */
00197 void GPIO_Configuration(void)
00198 {
00199   GPIO_InitTypeDef GPIO_InitStructure;
00200
00201 #ifdef USE_STM3210C_EVAL
00202   /* Enable the USART3 Pins Software Remapping */
00203   GPIO_PinRemapConfig(GPIO_PartialRemap_USART3, ENABLE);
00204
00205   /* Enable the USART2 Pins Software Remapping */
00206   GPIO_PinRemapConfig(GPIO_Remap_USART2, ENABLE);
00207 #elif defined(USE_STM3210B_EVAL) || defined(USE_STM32100B_EVAL)
00208   /* Enable the USART2 Pins Software Remapping */
00209   GPIO_PinRemapConfig(GPIO_Remap_USART2, ENABLE);
00210 #endif
00211
00212   /* Configure USARTy Rx as input floating */
00213   GPIO_InitStructure.GPIO_Pin = USARTy_RxPin;
00214   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
00215   GPIO_Init(USARTy_GPIO, &GPIO_InitStructure);
00216
00217   /* Configure USARTz Rx as input floating */
00218   GPIO_InitStructure.GPIO_Pin = USARTz_RxPin;
00219   GPIO_Init(USARTz_GPIO, &GPIO_InitStructure);
00220
00221   /* Configure USARTy Tx as alternate function push-pull */
00222   GPIO_InitStructure.GPIO_Pin = USARTy_TxPin;
00223   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00224   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
00225   GPIO_Init(USARTy_GPIO, &GPIO_InitStructure);
00226
00227   /* Configure USARTz Tx as alternate function push-pull */
00228   GPIO_InitStructure.GPIO_Pin = USARTz_TxPin;
00229   GPIO_Init(USARTz_GPIO, &GPIO_InitStructure);
00230 }
00231
00232 /**
00233   * @brief  Configures the nested vectored interrupt controller.
00234   * @param  None
00235   * @retval None
00236   */
00237 void NVIC_Configuration(void)
00238 {
00239    NVIC_InitTypeDef NVIC_InitStructure;
00240
00241   /* Enable the USARTz Interrupt */
00242   NVIC_InitStructure.NVIC_IRQChannel = USARTz_IRQn;
00243   NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
00244   NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
00245   NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
00246   NVIC_Init(&NVIC_InitStructure);
00247 }
00248
00249 /**
00250   * @brief  Configures the DMA.
00251   * @param  None
00252   * @retval None
00253   */
00254 void DMA_Configuration(void)
00255 {
00256   DMA_InitTypeDef DMA_InitStructure;
00257
00258   /* USARTy_Tx_DMA_Channel (triggered by USARTy Tx event) Config */
00259   DMA_DeInit(USARTy_Tx_DMA_Channel);
00260   DMA_InitStructure.DMA_PeripheralBaseAddr = USARTy_DR_Base;
00261   DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)TxBuffer1;
00262   DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
00263   DMA_InitStructure.DMA_BufferSize = TxBufferSize1;
00264   DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
00265   DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
00266   DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
00267   DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
00268   DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
00269   DMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh;
00270   DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
00271   DMA_Init(USARTy_Tx_DMA_Channel, &DMA_InitStructure);
00272
00273   /* USARTz_Tx_DMA_Channel (triggered by USARTz Tx event) Config */
00274   DMA_DeInit(USARTz_Tx_DMA_Channel);
00275   DMA_InitStructure.DMA_PeripheralBaseAddr = USARTz_DR_Base;
00276   DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)TxBuffer2;
00277   DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
00278   DMA_InitStructure.DMA_BufferSize = TxBufferSize2;
00279   DMA_Init(USARTz_Tx_DMA_Channel, &DMA_InitStructure);
00280 }
00281
00282 /**
00283   * @brief  Compares two buffers.
00284   * @param  pBuffer1, pBuffer2: buffers to be compared.
00285   * @param  BufferLength: buffer's length
00286   * @retval PASSED: pBuffer1 identical to pBuffer2
00287   *         FAILED: pBuffer1 differs from pBuffer2
00288   */
00289 TestStatus Buffercmp(uint8_t* pBuffer1, uint8_t* pBuffer2, uint16_t BufferLength)
00290 {
00291   while(BufferLength--)
00292   {
00293     if(*pBuffer1 != *pBuffer2)
00294     {
00295       return FAILED;
00296     }
00297
00298     pBuffer1++;
00299     pBuffer2++;
00300   }
00301
00302   return PASSED;
00303 }
00304
00305 #ifdef  USE_FULL_ASSERT
00306
00307 /**
00308   * @brief  Reports the name of the source file and the source line number
00309   *         where the assert_param error has occurred.
00310   * @param  file: pointer to the source file name
00311   * @param  line: assert_param error line source number
00312   * @retval None
00313   */
00314 void assert_failed(uint8_t* file, uint32_t line)
00315 {
00316   /* User can add his own implementation to report the file name and line number,
00317      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00318
00319   /* Infinite loop */
00320   while (1)
00321   {
00322   }
00323 }
00324
00325 #endif
00326
00327 /**
00328   * @}
00329   */
00330
00331 /**
00332   * @}
00333   */
00334
00335 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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  • DMA_Interrupt

STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_conf.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    USART/DMA_Interrupt/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052 /* Exported types ------------------------------------------------------------*/
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Uncomment the line below to expanse the "assert_param" macro in the
00055    Standard Peripheral Library drivers code */
00056 /* #define USE_FULL_ASSERT    1 */
00057
00058 /* Exported macro ------------------------------------------------------------*/
00059 #ifdef  USE_FULL_ASSERT
00060 /**
00061   * @brief  The assert_param macro is used for function's parameters check.
00062   * @param  expr: If expr is false, it calls assert_failed function which reports
00063   *         the name of the source file and the source line number of the call
00064   *         that failed. If expr is true, it returns no value.
00065   * @retval None
00066   */
00067   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00068 /* Exported functions ------------------------------------------------------- */
00069   void assert_failed(uint8_t* file, uint32_t line);
00070 #else
00071   #define assert_param(expr) ((void)0)
00072 #endif /* USE_FULL_ASSERT */
00073
00074 #endif /* __STM32F10x_CONF_H */
00075
00076 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_it.c

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00001 /**
00002   ******************************************************************************
00003   * @file    USART/DMA_Interrupt/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and peripherals
00009   *          interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026
00027 /** @addtogroup STM32F10x_StdPeriph_Examples
00028   * @{
00029   */
00030
00031 /** @addtogroup USART_DMA_Interrupt
00032   * @{
00033   */
00034
00035 /* Private typedef -----------------------------------------------------------*/
00036 /* Private define ------------------------------------------------------------*/
00037 /* Private macro -------------------------------------------------------------*/
00038 /* Private variables ---------------------------------------------------------*/
00039 uint8_t RxCounter = 0;
00040 extern uint8_t RxBuffer2[];
00041 extern uint8_t NbrOfDataToRead;
00042
00043 /* Private function prototypes -----------------------------------------------*/
00044 /* Private functions ---------------------------------------------------------*/
00045
00046 /******************************************************************************/
00047 /*            Cortex-M3 Processor Exceptions Handlers                         */
00048 /******************************************************************************/
00049
00050 /**
00051   * @brief  This function handles NMI exception.
00052   * @param  None
00053   * @retval None
00054   */
00055 void NMI_Handler(void)
00056 {
00057 }
00058
00059 /**
00060   * @brief  This function handles Hard Fault exception.
00061   * @param  None
00062   * @retval None
00063   */
00064 void HardFault_Handler(void)
00065 {
00066   /* Go to infinite loop when Hard Fault exception occurs */
00067   while (1)
00068   {
00069   }
00070 }
00071
00072 /**
00073   * @brief  This function handles Memory Manage exception.
00074   * @param  None
00075   * @retval None
00076   */
00077 void MemManage_Handler(void)
00078 {
00079   /* Go to infinite loop when Memory Manage exception occurs */
00080   while (1)
00081   {
00082   }
00083 }
00084
00085 /**
00086   * @brief  This function handles Bus Fault exception.
00087   * @param  None
00088   * @retval None
00089   */
00090 void BusFault_Handler(void)
00091 {
00092   /* Go to infinite loop when Bus Fault exception occurs */
00093   while (1)
00094   {
00095   }
00096 }
00097
00098 /**
00099   * @brief  This function handles Usage Fault exception.
00100   * @param  None
00101   * @retval None
00102   */
00103 void UsageFault_Handler(void)
00104 {
00105   /* Go to infinite loop when Usage Fault exception occurs */
00106   while (1)
00107   {
00108   }
00109 }
00110
00111 /**
00112   * @brief  This function handles SVCall exception.
00113   * @param  None
00114   * @retval None
00115   */
00116 void SVC_Handler(void)
00117 {
00118 }
00119
00120 /**
00121   * @brief  This function handles Debug Monitor exception.
00122   * @param  None
00123   * @retval None
00124   */
00125 void DebugMon_Handler(void)
00126 {
00127 }
00128
00129 /**
00130   * @brief  This function handles PendSV_Handler exception.
00131   * @param  None
00132   * @retval None
00133   */
00134 void PendSV_Handler(void)
00135 {
00136 }
00137
00138 /**
00139   * @brief  This function handles SysTick Handler.
00140   * @param  None
00141   * @retval None
00142   */
00143 void SysTick_Handler(void)
00144 {
00145 }
00146
00147 /******************************************************************************/
00148 /*            STM32F10x Peripherals Interrupt Handlers                        */
00149 /******************************************************************************/
00150
00151 /**
00152   * @brief  This function handles USART2 global interrupt request.
00153   * @param  None
00154   * @retval None
00155   */
00156 void USART2_IRQHandler(void)
00157 {
00158   if(USART_GetITStatus(USART2, USART_IT_RXNE) != RESET)
00159   {
00160     /* Read one byte from the receive data register */
00161     RxBuffer2[RxCounter++] = USART_ReceiveData(USART2);
00162
00163     if(RxCounter == NbrOfDataToRead)
00164     {
00165       /* Disable the USART2 Receive interrupt */
00166       USART_ITConfig(USART2, USART_IT_RXNE, DISABLE);
00167     }
00168   }
00169 }
00170
00171 /**
00172   * @brief  This function handles USART3 global interrupt request.
00173   * @param  None
00174   * @retval None
00175   */
00176 void USART3_IRQHandler(void)
00177 {
00178   if(USART_GetITStatus(USART3, USART_IT_RXNE) != RESET)
00179   {
00180     /* Read one byte from the receive data register */
00181     RxBuffer2[RxCounter++] = USART_ReceiveData(USART3);
00182
00183     if(RxCounter == NbrOfDataToRead)
00184     {
00185       /* Disable the USART3 Receive interrupt */
00186       USART_ITConfig(USART3, USART_IT_RXNE, DISABLE);
00187     }
00188   }
00189 }
00190
00191 /******************************************************************************/
00192 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00193 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00194 /*  available peripheral interrupt handler's name please refer to the startup */
00195 /*  file (startup_stm32f10x_xx.s).                                            */
00196 /******************************************************************************/
00197
00198 /**
00199   * @brief  This function handles PPP interrupt request.
00200   * @param  None
00201   * @retval None
00202   */
00203 /*void PPP_IRQHandler(void)
00204 {
00205 }*/
00206
00207 /**
00208   * @}
00209   */
00210
00211 /**
00212   * @}
00213   */
00214
00215 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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  • DMA_Interrupt

STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_it.h

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00001 /**
00002   ******************************************************************************
00003   * @file    USART/DMA_Interrupt/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043 void USART2_IRQHandler(void);
00044
00045 #endif /* __STM32F10x_IT_H */
00046
00047 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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STM32F10x_StdPeriph_Examples/USART/DMA_Polling/main.c

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00001 /**
00002   ******************************************************************************
00003   * @file    USART/DMA_Polling/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x.h"
00024 #include "platform_config.h"
00025
00026 /** @addtogroup STM32F10x_StdPeriph_Examples
00027   * @{
00028   */
00029
00030 /** @addtogroup USART_DMA_Polling
00031   * @{
00032   */
00033
00034 /* Private typedef -----------------------------------------------------------*/
00035 typedef enum { FAILED = 0, PASSED = !FAILED} TestStatus;
00036
00037 /* Private define ------------------------------------------------------------*/
00038 #define TxBufferSize1   (countof(TxBuffer1) - 1)
00039 #define TxBufferSize2   (countof(TxBuffer2) - 1)
00040
00041 /* Private macro -------------------------------------------------------------*/
00042 #define countof(a)   (sizeof(a) / sizeof(*(a)))
00043
00044 /* Private variables ---------------------------------------------------------*/
00045 USART_InitTypeDef USART_InitStructure;
00046 uint8_t TxBuffer1[] = "USART DMA Polling: USARTy -> USARTz using DMA";
00047 uint8_t TxBuffer2[] = "USART DMA Polling: USARTz -> USARTy using DMA";
00048 uint8_t RxBuffer1[TxBufferSize2];
00049 uint8_t RxBuffer2[TxBufferSize1];
00050 volatile TestStatus TransferStatus1 = FAILED;
00051 volatile TestStatus TransferStatus2 = FAILED;
00052
00053 /* Private function prototypes -----------------------------------------------*/
00054 void RCC_Configuration(void);
00055 void GPIO_Configuration(void);
00056 void DMA_Configuration(void);
00057 TestStatus Buffercmp(uint8_t* pBuffer1, uint8_t* pBuffer2, uint16_t BufferLength);
00058
00059 /* Private functions ---------------------------------------------------------*/
00060
00061 /**
00062   * @brief  Main program
00063   * @param  None
00064   * @retval None
00065   */
00066 int main(void)
00067 {
00068   /*!< At this stage the microcontroller clock setting is already configured,
00069        this is done through SystemInit() function which is called from startup
00070        file (startup_stm32f10x_xx.s) before to branch to application main.
00071        To reconfigure the default setting of SystemInit() function, refer to
00072        system_stm32f10x.c file
00073      */
00074
00075   /* System Clocks Configuration */
00076   RCC_Configuration();
00077
00078   /* Configure the GPIO ports */
00079   GPIO_Configuration();
00080
00081   /* Configure the DMA */
00082   DMA_Configuration();
00083
00084 /* USARTy and USARTz configuration ------------------------------------------------------*/
00085   /* USARTy and USARTz configured as follow:
00086         - BaudRate = 230400 baud
00087         - Word Length = 8 Bits
00088         - One Stop Bit
00089         - No parity
00090         - Hardware flow control disabled (RTS and CTS signals)
00091         - Receive and transmit enabled
00092   */
00093   USART_InitStructure.USART_BaudRate = 230400;
00094   USART_InitStructure.USART_WordLength = USART_WordLength_8b;
00095   USART_InitStructure.USART_StopBits = USART_StopBits_1;
00096   USART_InitStructure.USART_Parity = USART_Parity_No;
00097   USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
00098   USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
00099
00100   /* Configure USARTy */
00101   USART_Init(USARTy, &USART_InitStructure);
00102   /* Configure USARTz */
00103   USART_Init(USARTz, &USART_InitStructure);
00104
00105   /* Enable USARTy DMA Rx and TX request */
00106   USART_DMACmd(USARTy, USART_DMAReq_Rx | USART_DMAReq_Tx, ENABLE);
00107   /* Enable USARTz DMA Rx and TX request */
00108   USART_DMACmd(USARTz, USART_DMAReq_Rx | USART_DMAReq_Tx, ENABLE);
00109
00110   /* Enable USARTy TX DMA1 Channel */
00111   DMA_Cmd(USARTy_Tx_DMA_Channel, ENABLE);
00112   /* Enable USARTy RX DMA1 Channel */
00113   DMA_Cmd(USARTy_Rx_DMA_Channel, ENABLE);
00114
00115   /* Enable USARTz TX DMA1 Channel */
00116   DMA_Cmd(USARTz_Tx_DMA_Channel, ENABLE);
00117   /* Enable USARTz RX DMA1 Channel */
00118   DMA_Cmd(USARTz_Rx_DMA_Channel, ENABLE);
00119
00120   /* Enable the USARTy */
00121   USART_Cmd(USARTy, ENABLE);
00122   /* Enable the USARTz */
00123   USART_Cmd(USARTz, ENABLE);
00124
00125   /* Wait until USARTy TX DMA1 Channel Transfer Complete */
00126   while (DMA_GetFlagStatus(USARTy_Tx_DMA_FLAG) == RESET)
00127   {
00128   }
00129   /* Wait until USARTy RX DMA1 Channel Transfer Complete */
00130   while (DMA_GetFlagStatus(USARTy_Rx_DMA_FLAG) == RESET)
00131   {
00132   }
00133
00134   /* Wait until USARTz TX DMA1 Channel Transfer Complete */
00135   while (DMA_GetFlagStatus(USARTz_Tx_DMA_FLAG) == RESET)
00136   {
00137   }
00138   /* Wait until USARTz RX DMA1 Channel Transfer Complete */
00139   while (DMA_GetFlagStatus(USARTz_Rx_DMA_FLAG) == RESET)
00140   {
00141   }
00142
00143   /* Check the received data with the send ones */
00144   TransferStatus1 = Buffercmp(TxBuffer2, RxBuffer1, TxBufferSize2);
00145   /* TransferStatus1 = PASSED, if the data transmitted from USARTz and
00146      received by USARTy are the same */
00147   /* TransferStatus1 = FAILED, if the data transmitted from USARTz and
00148      received by USARTy are different */
00149   TransferStatus2 = Buffercmp(TxBuffer1, RxBuffer2, TxBufferSize1);
00150   /* TransferStatus2 = PASSED, if the data transmitted from USARTy and
00151      received by USARTz are the same */
00152   /* TransferStatus2 = FAILED, if the data transmitted from USARTy and
00153      received by USARTz are different */
00154
00155   while (1)
00156   {
00157   }
00158 }
00159
00160 /**
00161   * @brief  Configures the different system clocks.
00162   * @param  None
00163   * @retval None
00164   */
00165 void RCC_Configuration(void)
00166 {
00167   /* DMA clock enable */
00168   RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE);
00169
00170   /* Enable GPIO clock */
00171   RCC_APB2PeriphClockCmd(USARTy_GPIO_CLK | USARTz_GPIO_CLK | RCC_APB2Periph_AFIO, ENABLE);
00172
00173 #ifndef USE_STM3210C_EVAL
00174   /* Enable USARTy Clock */
00175   RCC_APB2PeriphClockCmd(USARTy_CLK, ENABLE);
00176 #else
00177   /* Enable USARTy Clock */
00178   RCC_APB1PeriphClockCmd(USARTy_CLK, ENABLE);
00179 #endif
00180   /* Enable USARTz Clock */
00181   RCC_APB1PeriphClockCmd(USARTz_CLK, ENABLE);
00182 }
00183
00184 /**
00185   * @brief  Configures the different GPIO ports.
00186   * @param  None
00187   * @retval None
00188   */
00189 void GPIO_Configuration(void)
00190 {
00191   GPIO_InitTypeDef GPIO_InitStructure;
00192
00193 #ifdef USE_STM3210C_EVAL
00194   /* Enable the USART3 Pins Software Remapping */
00195   GPIO_PinRemapConfig(GPIO_PartialRemap_USART3, ENABLE);
00196
00197   /* Enable the USART2 Pins Software Remapping */
00198   GPIO_PinRemapConfig(GPIO_Remap_USART2, ENABLE);
00199 #elif defined(USE_STM3210B_EVAL) || defined(USE_STM32100B_EVAL)
00200   /* Enable the USART2 Pins Software Remapping */
00201   GPIO_PinRemapConfig(GPIO_Remap_USART2, ENABLE);
00202 #endif
00203
00204   /* Configure USARTy Rx as input floating */
00205   GPIO_InitStructure.GPIO_Pin = USARTy_RxPin;
00206   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
00207   GPIO_Init(USARTy_GPIO, &GPIO_InitStructure);
00208
00209   /* Configure USARTz Rx as input floating */
00210   GPIO_InitStructure.GPIO_Pin = USARTz_RxPin;
00211   GPIO_Init(USARTz_GPIO, &GPIO_InitStructure);
00212
00213   /* Configure USARTy Tx as alternate function push-pull */
00214   GPIO_InitStructure.GPIO_Pin = USARTy_TxPin;
00215   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00216   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
00217   GPIO_Init(USARTy_GPIO, &GPIO_InitStructure);
00218
00219   /* Configure USARTz Tx as alternate function push-pull */
00220   GPIO_InitStructure.GPIO_Pin = USARTz_TxPin;
00221   GPIO_Init(USARTz_GPIO, &GPIO_InitStructure);
00222 }
00223
00224 /**
00225   * @brief  Configures the DMA.
00226   * @param  None
00227   * @retval None
00228   */
00229 void DMA_Configuration(void)
00230 {
00231   DMA_InitTypeDef DMA_InitStructure;
00232
00233   /* USARTy TX DMA1 Channel (triggered by USARTy Tx event) Config */
00234   DMA_DeInit(USARTy_Tx_DMA_Channel);
00235   DMA_InitStructure.DMA_PeripheralBaseAddr = USARTy_DR_Base;
00236   DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)TxBuffer1;
00237   DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
00238   DMA_InitStructure.DMA_BufferSize = TxBufferSize1;
00239   DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
00240   DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
00241   DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
00242   DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
00243   DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
00244   DMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh;
00245   DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
00246   DMA_Init(USARTy_Tx_DMA_Channel, &DMA_InitStructure);
00247
00248   /* USARTy RX DMA1 Channel (triggered by USARTy Rx event) Config */
00249   DMA_DeInit(USARTy_Rx_DMA_Channel);
00250   DMA_InitStructure.DMA_PeripheralBaseAddr = USARTy_DR_Base;
00251   DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)RxBuffer1;
00252   DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
00253   DMA_InitStructure.DMA_BufferSize = TxBufferSize2;
00254   DMA_Init(USARTy_Rx_DMA_Channel, &DMA_InitStructure);
00255
00256   /* USARTz TX DMA1 Channel (triggered by USARTz Tx event) Config */
00257   DMA_DeInit(USARTz_Tx_DMA_Channel);
00258   DMA_InitStructure.DMA_PeripheralBaseAddr = USARTz_DR_Base;
00259   DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)TxBuffer2;
00260   DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
00261   DMA_InitStructure.DMA_BufferSize = TxBufferSize2;
00262   DMA_Init(USARTz_Tx_DMA_Channel, &DMA_InitStructure);
00263
00264   /* USARTz RX DMA1 Channel (triggered by USARTz Rx event) Config */
00265   DMA_DeInit(USARTz_Rx_DMA_Channel);
00266   DMA_InitStructure.DMA_PeripheralBaseAddr = USARTz_DR_Base;
00267   DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)RxBuffer2;
00268   DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
00269   DMA_InitStructure.DMA_BufferSize = TxBufferSize1;
00270   DMA_Init(USARTz_Rx_DMA_Channel, &DMA_InitStructure);
00271 }
00272
00273 /**
00274   * @brief  Compares two buffers.
00275   * @param  pBuffer1, pBuffer2: buffers to be compared.
00276   * @param  BufferLength: buffer's length
00277   * @retval PASSED: pBuffer1 identical to pBuffer2
00278   *         FAILED: pBuffer1 differs from pBuffer2
00279   */
00280 TestStatus Buffercmp(uint8_t* pBuffer1, uint8_t* pBuffer2, uint16_t BufferLength)
00281 {
00282   while(BufferLength--)
00283   {
00284     if(*pBuffer1 != *pBuffer2)
00285     {
00286       return FAILED;
00287     }
00288
00289     pBuffer1++;
00290     pBuffer2++;
00291   }
00292
00293   return PASSED;
00294 }
00295
00296 #ifdef  USE_FULL_ASSERT
00297
00298 /**
00299   * @brief  Reports the name of the source file and the source line number
00300   *         where the assert_param error has occurred.
00301   * @param  file: pointer to the source file name
00302   * @param  line: assert_param error line source number
00303   * @retval None
00304   */
00305 void assert_failed(uint8_t* file, uint32_t line)
00306 {
00307   /* User can add his own implementation to report the file name and line number,
00308      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00309
00310   /* Infinite loop */
00311   while (1)
00312   {
00313   }
00314 }
00315
00316 #endif
00317
00318 /**
00319   * @}
00320   */
00321
00322 /**
00323   * @}
00324   */
00325
00326 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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STM32F10x_StdPeriph_Examples/USART/DMA_Polling/stm32f10x_conf.h

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00001 /**
00002   ******************************************************************************
00003   * @file    USART/DMA_Polling/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052 /* Exported types ------------------------------------------------------------*/
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Uncomment the line below to expanse the "assert_param" macro in the
00055    Standard Peripheral Library drivers code */
00056 /* #define USE_FULL_ASSERT    1 */
00057
00058 /* Exported macro ------------------------------------------------------------*/
00059 #ifdef  USE_FULL_ASSERT
00060 /**
00061   * @brief  The assert_param macro is used for function's parameters check.
00062   * @param  expr: If expr is false, it calls assert_failed function which reports
00063   *         the name of the source file and the source line number of the call
00064   *         that failed. If expr is true, it returns no value.
00065   * @retval None
00066   */
00067   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00068 /* Exported functions ------------------------------------------------------- */
00069   void assert_failed(uint8_t* file, uint32_t line);
00070 #else
00071   #define assert_param(expr) ((void)0)
00072 #endif /* USE_FULL_ASSERT */
00073
00074 #endif /* __STM32F10x_CONF_H */
00075
00076 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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STM32F10x_StdPeriph_Examples/USART/DMA_Polling/stm32f10x_it.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    USART/DMA_Polling/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and peripherals
00009   *          interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026
00027 /** @addtogroup STM32F10x_StdPeriph_Examples
00028   * @{
00029   */
00030
00031 /** @addtogroup USART_DMA_Polling
00032   * @{
00033   */
00034
00035 /* Private typedef -----------------------------------------------------------*/
00036 /* Private define ------------------------------------------------------------*/
00037 /* Private macro -------------------------------------------------------------*/
00038 /* Private variables ---------------------------------------------------------*/
00039 /* Private function prototypes -----------------------------------------------*/
00040 /* Private functions ---------------------------------------------------------*/
00041
00042 /******************************************************************************/
00043 /*            Cortex-M3 Processor Exceptions Handlers                         */
00044 /******************************************************************************/
00045
00046 /**
00047   * @brief  This function handles NMI exception.
00048   * @param  None
00049   * @retval None
00050   */
00051 void NMI_Handler(void)
00052 {
00053 }
00054
00055 /**
00056   * @brief  This function handles Hard Fault exception.
00057   * @param  None
00058   * @retval None
00059   */
00060 void HardFault_Handler(void)
00061 {
00062   /* Go to infinite loop when Hard Fault exception occurs */
00063   while (1)
00064   {
00065   }
00066 }
00067
00068 /**
00069   * @brief  This function handles Memory Manage exception.
00070   * @param  None
00071   * @retval None
00072   */
00073 void MemManage_Handler(void)
00074 {
00075   /* Go to infinite loop when Memory Manage exception occurs */
00076   while (1)
00077   {
00078   }
00079 }
00080
00081 /**
00082   * @brief  This function handles Bus Fault exception.
00083   * @param  None
00084   * @retval None
00085   */
00086 void BusFault_Handler(void)
00087 {
00088   /* Go to infinite loop when Bus Fault exception occurs */
00089   while (1)
00090   {
00091   }
00092 }
00093
00094 /**
00095   * @brief  This function handles Usage Fault exception.
00096   * @param  None
00097   * @retval None
00098   */
00099 void UsageFault_Handler(void)
00100 {
00101   /* Go to infinite loop when Usage Fault exception occurs */
00102   while (1)
00103   {
00104   }
00105 }
00106
00107 /**
00108   * @brief  This function handles SVCall exception.
00109   * @param  None
00110   * @retval None
00111   */
00112 void SVC_Handler(void)
00113 {
00114 }
00115
00116 /**
00117   * @brief  This function handles Debug Monitor exception.
00118   * @param  None
00119   * @retval None
00120   */
00121 void DebugMon_Handler(void)
00122 {
00123 }
00124
00125 /**
00126   * @brief  This function handles PendSV_Handler exception.
00127   * @param  None
00128   * @retval None
00129   */
00130 void PendSV_Handler(void)
00131 {
00132 }
00133
00134 /**
00135   * @brief  This function handles SysTick Handler.
00136   * @param  None
00137   * @retval None
00138   */
00139 void SysTick_Handler(void)
00140 {
00141 }
00142
00143 /******************************************************************************/
00144 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00145 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00146 /*  available peripheral interrupt handler's name please refer to the startup */
00147 /*  file (startup_stm32f10x_xx.s).                                            */
00148 /******************************************************************************/
00149
00150 /**
00151   * @brief  This function handles PPP interrupt request.
00152   * @param  None
00153   * @retval None
00154   */
00155 /*void PPP_IRQHandler(void)
00156 {
00157 }*/
00158
00159 /**
00160   * @}
00161   */
00162
00163 /**
00164   * @}
00165   */
00166
00167 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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STM32F10x_StdPeriph_Examples/USART/DMA_Polling/stm32f10x_it.h

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00001 /**
00002   ******************************************************************************
00003   * @file    USART/DMA_Polling/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043
00044 #endif /* __STM32F10x_IT_H */
00045
00046 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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STM32F10x_StdPeriph_Examples/USART/HalfDuplex/main.c

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00001 /**
00002   ******************************************************************************
00003   * @file    USART/HalfDuplex/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x.h"
00024 #include "platform_config.h"
00025
00026 /** @addtogroup STM32F10x_StdPeriph_Examples
00027   * @{
00028   */
00029
00030 /** @addtogroup USART_HalfDuplex
00031   * @{
00032   */
00033
00034 /* Private typedef -----------------------------------------------------------*/
00035 typedef enum {FAILED = 0, PASSED = !FAILED} TestStatus;
00036
00037 /* Private define ------------------------------------------------------------*/
00038 #define TxBufferSize1   (countof(TxBuffer1) - 1)
00039 #define TxBufferSize2   (countof(TxBuffer2) - 1)
00040
00041 /* Private macro -------------------------------------------------------------*/
00042 #define countof(a)   (sizeof(a) / sizeof(*(a)))
00043
00044 /* Private variables ---------------------------------------------------------*/
00045 USART_InitTypeDef USART_InitStructure;
00046 uint8_t TxBuffer1[] = "USART Half Duplex: USARTy -> USARTz using HalfDuplex mode";
00047 uint8_t TxBuffer2[] = "USART Half Duplex: USARTz -> USARTy using HalfDuplex mode";
00048 uint8_t RxBuffer1[TxBufferSize2];
00049 uint8_t RxBuffer2[TxBufferSize1];
00050 uint32_t NbrOfDataToRead1 = TxBufferSize2;
00051 uint32_t NbrOfDataToRead2 = TxBufferSize1;
00052 uint8_t TxCounter1 = 0, RxCounter1 = 0;
00053 uint8_t TxCounter2 = 0, RxCounter2 = 0;
00054 volatile TestStatus TransferStatus1 = FAILED, TransferStatus2 = FAILED;
00055
00056 /* Private function prototypes -----------------------------------------------*/
00057 void RCC_Configuration(void);
00058 void GPIO_Configuration(void);
00059 TestStatus Buffercmp(uint8_t* pBuffer1, uint8_t* pBuffer2, uint16_t BufferLength);
00060
00061 /* Private functions ---------------------------------------------------------*/
00062
00063 /**
00064   * @brief   Main program
00065   * @param  None
00066   * @retval None
00067   */
00068 int main(void)
00069 {
00070   /*!< At this stage the microcontroller clock setting is already configured,
00071        this is done through SystemInit() function which is called from startup
00072        file (startup_stm32f10x_xx.s) before to branch to application main.
00073        To reconfigure the default setting of SystemInit() function, refer to
00074        system_stm32f10x.c file
00075      */
00076
00077   /* System Clocks Configuration */
00078   RCC_Configuration();
00079
00080   /* Configure the GPIO ports */
00081   GPIO_Configuration();
00082
00083 /* USARTy and USARTz configuration -------------------------------------------*/
00084   /* USARTy and USARTz configured as follow:
00085         - BaudRate = 230400 baud
00086         - Word Length = 8 Bits
00087         - One Stop Bit
00088         - No parity
00089         - Hardware flow control disabled (RTS and CTS signals)
00090         - Receive and transmit enabled
00091
00092   */
00093   USART_InitStructure.USART_BaudRate = 230400;
00094   USART_InitStructure.USART_WordLength = USART_WordLength_8b;
00095   USART_InitStructure.USART_StopBits = USART_StopBits_1;
00096   USART_InitStructure.USART_Parity = USART_Parity_No;
00097   USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
00098   USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
00099
00100   /* Configure USARTy */
00101   USART_Init(USARTy, &USART_InitStructure);
00102   /* Configure USARTz */
00103   USART_Init(USARTz, &USART_InitStructure);
00104
00105   /* Enable the USARTy */
00106   USART_Cmd(USARTy, ENABLE);
00107   /* Enable the USARTz */
00108   USART_Cmd(USARTz, ENABLE);
00109
00110   /* Enable USARTy Half Duplex Mode*/
00111   USART_HalfDuplexCmd(USARTy, ENABLE);
00112   /* Enable USARTz Half Duplex Mode*/
00113   USART_HalfDuplexCmd(USARTz, ENABLE);
00114
00115   while(NbrOfDataToRead2--)
00116   {
00117     /* Wait until end of transmit */
00118     while(USART_GetFlagStatus(USARTy, USART_FLAG_TXE) == RESET)
00119     {
00120     }
00121     /* Write one byte in the USARTy Transmit Data Register */
00122     USART_SendData(USARTy, TxBuffer1[TxCounter1++]);
00123
00124     /* Wait the byte is entirely received by USARTz */
00125     while(USART_GetFlagStatus(USARTz, USART_FLAG_RXNE) == RESET)
00126     {
00127     }
00128     /* Store the received byte in the RxBuffer2 */
00129     RxBuffer2[RxCounter2++] = USART_ReceiveData(USARTz);
00130   }
00131
00132   /* Clear the USARTy Data Register */
00133   USART_ReceiveData(USARTy);
00134
00135   while(NbrOfDataToRead1--)
00136   {
00137     /* Wait until end of transmit */
00138     while(USART_GetFlagStatus(USARTz, USART_FLAG_TXE)== RESET)
00139     {
00140     }
00141     /* Write one byte in the USARTz Transmit Data Register */
00142     USART_SendData(USARTz, TxBuffer2[TxCounter2++]);
00143
00144     /* Wait the byte is entirely received by USARTy */
00145     while(USART_GetFlagStatus(USARTy,USART_FLAG_RXNE) == RESET)
00146     {
00147     }
00148     /* Store the received byte in the RxBuffer1 */
00149     RxBuffer1[RxCounter1++] = USART_ReceiveData(USARTy);
00150   }
00151
00152   /* Check the received data with the send ones */
00153   TransferStatus1 = Buffercmp(TxBuffer1, RxBuffer2, TxBufferSize1);
00154   /* TransferStatus = PASSED, if the data transmitted from USARTy and
00155      received by USARTz are the same */
00156   /* TransferStatus = FAILED, if the data transmitted from USARTy and
00157      received by USARTz are different */
00158   TransferStatus2 = Buffercmp(TxBuffer2, RxBuffer1, TxBufferSize2);
00159   /* TransferStatus = PASSED, if the data transmitted from USARTz and
00160      received by USARTy are the same */
00161   /* TransferStatus = FAILED, if the data transmitted from USARTz and
00162      received by USARTy are different */
00163
00164   while (1)
00165   {
00166   }
00167 }
00168
00169 /**
00170   * @brief  Configures the different system clocks.
00171   * @param  None
00172   * @retval None
00173   */
00174 void RCC_Configuration(void)
00175 {
00176   /* Enable GPIO clock */
00177   RCC_APB2PeriphClockCmd(USARTy_GPIO_CLK | USARTz_GPIO_CLK | RCC_APB2Periph_AFIO, ENABLE);
00178
00179 #ifndef USE_STM3210C_EVAL
00180   /* Enable USARTy Clock */
00181   RCC_APB2PeriphClockCmd(USARTy_CLK, ENABLE);
00182 #else
00183   /* Enable USARTy Clock */
00184   RCC_APB1PeriphClockCmd(USARTy_CLK, ENABLE);
00185 #endif
00186   /* Enable USARTz Clock */
00187   RCC_APB1PeriphClockCmd(USARTz_CLK, ENABLE);
00188 }
00189
00190 /**
00191   * @brief  Configures the different GPIO ports.
00192   * @param  None
00193   * @retval None
00194   */
00195 void GPIO_Configuration(void)
00196 {
00197   GPIO_InitTypeDef GPIO_InitStructure;
00198
00199 #ifdef USE_STM3210C_EVAL
00200   /* Enable the USART3 Pins Software Remapping */
00201   GPIO_PinRemapConfig(GPIO_PartialRemap_USART3, ENABLE);
00202
00203   /* Enable the USART2 Pins Software Remapping */
00204   GPIO_PinRemapConfig(GPIO_Remap_USART2, ENABLE);
00205 #elif defined(USE_STM3210B_EVAL) || defined(USE_STM32100B_EVAL)
00206   /* Enable the USART2 Pins Software Remapping */
00207   GPIO_PinRemapConfig(GPIO_Remap_USART2, ENABLE);
00208 #endif
00209
00210   /* Configure USARTy Tx as alternate function open-drain */
00211   GPIO_InitStructure.GPIO_Pin = USARTy_TxPin;
00212   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00213   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_OD;
00214   GPIO_Init(USARTy_GPIO, &GPIO_InitStructure);
00215
00216   /* Configure USARTz Tx as alternate function open-drain */
00217   GPIO_InitStructure.GPIO_Pin = USARTz_TxPin;
00218   GPIO_Init(USARTz_GPIO, &GPIO_InitStructure);
00219 }
00220
00221 /**
00222   * @brief  Compares two buffers.
00223   * @param  pBuffer1, pBuffer2: buffers to be compared.
00224   * @param  BufferLength: buffer's length
00225   * @retval PASSED: pBuffer1 identical to pBuffer2
00226   *         FAILED: pBuffer1 differs from pBuffer2
00227   */
00228 TestStatus Buffercmp(uint8_t* pBuffer1, uint8_t* pBuffer2, uint16_t BufferLength)
00229 {
00230   while(BufferLength--)
00231   {
00232     if(*pBuffer1 != *pBuffer2)
00233     {
00234       return FAILED;
00235     }
00236
00237     pBuffer1++;
00238     pBuffer2++;
00239   }
00240
00241   return PASSED;
00242 }
00243
00244 #ifdef  USE_FULL_ASSERT
00245
00246 /**
00247   * @brief  Reports the name of the source file and the source line number
00248   *         where the assert_param error has occurred.
00249   * @param  file: pointer to the source file name
00250   * @param  line: assert_param error line source number
00251   * @retval None
00252   */
00253 void assert_failed(uint8_t* file, uint32_t line)
00254 {
00255   /* User can add his own implementation to report the file name and line number,
00256      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00257
00258   /* Infinite loop */
00259   while (1)
00260   {
00261   }
00262 }
00263
00264 #endif
00265
00266 /**
00267   * @}
00268   */
00269
00270 /**
00271   * @}
00272   */
00273
00274 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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  • HalfDuplex

STM32F10x_StdPeriph_Examples/USART/HalfDuplex/stm32f10x_conf.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    USART/HalfDuplex/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052 /* Exported types ------------------------------------------------------------*/
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Uncomment the line below to expanse the "assert_param" macro in the
00055    Standard Peripheral Library drivers code */
00056 /* #define USE_FULL_ASSERT    1 */
00057
00058 /* Exported macro ------------------------------------------------------------*/
00059 #ifdef  USE_FULL_ASSERT
00060 /**
00061   * @brief  The assert_param macro is used for function's parameters check.
00062   * @param  expr: If expr is false, it calls assert_failed function which reports
00063   *         the name of the source file and the source line number of the call
00064   *         that failed. If expr is true, it returns no value.
00065   * @retval None
00066   */
00067   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00068 /* Exported functions ------------------------------------------------------- */
00069   void assert_failed(uint8_t* file, uint32_t line);
00070 #else
00071   #define assert_param(expr) ((void)0)
00072 #endif /* USE_FULL_ASSERT */
00073
00074 #endif /* __STM32F10x_CONF_H */
00075
00076 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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STM32F10x_StdPeriph_Examples/USART/HalfDuplex/stm32f10x_it.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    USART/HalfDuplex/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and peripherals
00009   *          interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026
00027 /** @addtogroup STM32F10x_StdPeriph_Examples
00028   * @{
00029   */
00030
00031 /** @addtogroup USART_HalfDuplex
00032   * @{
00033   */
00034
00035 /* Private typedef -----------------------------------------------------------*/
00036 /* Private define ------------------------------------------------------------*/
00037 /* Private macro -------------------------------------------------------------*/
00038 /* Private variables ---------------------------------------------------------*/
00039 /* Private function prototypes -----------------------------------------------*/
00040 /* Private functions ---------------------------------------------------------*/
00041
00042 /******************************************************************************/
00043 /*            Cortex-M3 Processor Exceptions Handlers                         */
00044 /******************************************************************************/
00045
00046 /**
00047   * @brief  This function handles NMI exception.
00048   * @param  None
00049   * @retval None
00050   */
00051 void NMI_Handler(void)
00052 {
00053 }
00054
00055 /**
00056   * @brief  This function handles Hard Fault exception.
00057   * @param  None
00058   * @retval None
00059   */
00060 void HardFault_Handler(void)
00061 {
00062   /* Go to infinite loop when Hard Fault exception occurs */
00063   while (1)
00064   {
00065   }
00066 }
00067
00068 /**
00069   * @brief  This function handles Memory Manage exception.
00070   * @param  None
00071   * @retval None
00072   */
00073 void MemManage_Handler(void)
00074 {
00075   /* Go to infinite loop when Memory Manage exception occurs */
00076   while (1)
00077   {
00078   }
00079 }
00080
00081 /**
00082   * @brief  This function handles Bus Fault exception.
00083   * @param  None
00084   * @retval None
00085   */
00086 void BusFault_Handler(void)
00087 {
00088   /* Go to infinite loop when Bus Fault exception occurs */
00089   while (1)
00090   {
00091   }
00092 }
00093
00094 /**
00095   * @brief  This function handles Usage Fault exception.
00096   * @param  None
00097   * @retval None
00098   */
00099 void UsageFault_Handler(void)
00100 {
00101   /* Go to infinite loop when Usage Fault exception occurs */
00102   while (1)
00103   {
00104   }
00105 }
00106
00107 /**
00108   * @brief  This function handles SVCall exception.
00109   * @param  None
00110   * @retval None
00111   */
00112 void SVC_Handler(void)
00113 {
00114 }
00115
00116 /**
00117   * @brief  This function handles Debug Monitor exception.
00118   * @param  None
00119   * @retval None
00120   */
00121 void DebugMon_Handler(void)
00122 {
00123 }
00124
00125 /**
00126   * @brief  This function handles PendSV_Handler exception.
00127   * @param  None
00128   * @retval None
00129   */
00130 void PendSV_Handler(void)
00131 {
00132 }
00133
00134 /**
00135   * @brief  This function handles SysTick Handler.
00136   * @param  None
00137   * @retval None
00138   */
00139 void SysTick_Handler(void)
00140 {
00141 }
00142
00143 /******************************************************************************/
00144 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00145 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00146 /*  available peripheral interrupt handler's name please refer to the startup */
00147 /*  file (startup_stm32f10x_xx.s).                                            */
00148 /******************************************************************************/
00149
00150 /**
00151   * @brief  This function handles PPP interrupt request.
00152   * @param  None
00153   * @retval None
00154   */
00155 /*void PPP_IRQHandler(void)
00156 {
00157 }*/
00158
00159 /**
00160   * @}
00161   */
00162
00163 /**
00164   * @}
00165   */
00166
00167 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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STM32F10x_StdPeriph_Examples/USART/HalfDuplex/stm32f10x_it.h

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00001 /**
00002   ******************************************************************************
00003   * @file    USART/HalfDuplex/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043
00044 #endif /* __STM32F10x_IT_H */
00045
00046 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/main.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    USART/HyperTerminal_HwFlowControl/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x.h"
00024 #include "platform_config.h"
00025
00026 /** @addtogroup STM32F10x_StdPeriph_Examples
00027   * @{
00028   */
00029
00030 /** @addtogroup USART_HyperTerminal_HwFlowControl
00031   * @{
00032   */
00033
00034 /* Private typedef -----------------------------------------------------------*/
00035 /* Private define ------------------------------------------------------------*/
00036 #define TxBufferSize   (countof(TxBuffer) - 1)
00037 #define RxBufferSize   0xFF
00038
00039 /* Private macro -------------------------------------------------------------*/
00040 #define countof(a)   (sizeof(a) / sizeof(*(a)))
00041
00042 /* Private variables ---------------------------------------------------------*/
00043 USART_InitTypeDef USART_InitStructure;
00044 uint8_t TxBuffer[] = "\n\rUSART Hyperterminal Hardware Flow Control Example: USART - \
00045 Hyperterminal communication using hardware flow control\n\r";
00046 uint8_t RxBuffer[RxBufferSize];
00047 uint8_t NbrOfDataToTransfer = TxBufferSize;
00048 uint8_t TxCounter = 0;
00049 uint8_t RxCounter = 0;
00050
00051 /* Private function prototypes -----------------------------------------------*/
00052 void RCC_Configuration(void);
00053 void GPIO_Configuration(void);
00054
00055 /* Private functions ---------------------------------------------------------*/
00056
00057 /**
00058   * @brief   Main program
00059   * @param  None
00060   * @retval None
00061   */
00062 int main(void)
00063 {
00064   /*!< At this stage the microcontroller clock setting is already configured,
00065        this is done through SystemInit() function which is called from startup
00066        file (startup_stm32f10x_xx.s) before to branch to application main.
00067        To reconfigure the default setting of SystemInit() function, refer to
00068        system_stm32f10x.c file
00069      */
00070
00071   /* System Clocks Configuration */
00072   RCC_Configuration();
00073
00074   /* Configure the GPIO ports */
00075   GPIO_Configuration();
00076
00077 /* USART2 configuration ------------------------------------------------------*/
00078   /* USART2 configured as follow:
00079         - BaudRate = 115200 baud
00080         - Word Length = 8 Bits
00081         - One Stop Bit
00082         - No parity
00083         - Hardware flow control enabled (RTS and CTS signals)
00084         - Receive and transmit enabled
00085   */
00086   USART_InitStructure.USART_BaudRate = 115200;
00087   USART_InitStructure.USART_WordLength = USART_WordLength_8b;
00088   USART_InitStructure.USART_StopBits = USART_StopBits_1;
00089   USART_InitStructure.USART_Parity = USART_Parity_No ;
00090   USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_RTS_CTS;
00091   USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
00092
00093   USART_Init(USART2, &USART_InitStructure);
00094   /* Enable the USART2 */
00095   USART_Cmd(USART2, ENABLE);
00096
00097 /* Communication hyperterminal-USART2 using hardware flow control -------------*/
00098   /* Send a buffer from USART to hyperterminal */
00099   while(NbrOfDataToTransfer--)
00100   {
00101     USART_SendData(USART2, TxBuffer[TxCounter++]);
00102     while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET);
00103   }
00104
00105   /* Receive a string (Max RxBufferSize bytes) from the Hyperterminal ended by '\r' (Enter key) */
00106   do
00107   {
00108     if((USART_GetFlagStatus(USART2, USART_FLAG_RXNE) != RESET)&&(RxCounter < RxBufferSize))
00109     {
00110        RxBuffer[RxCounter] = USART_ReceiveData(USART2);
00111        USART_SendData(USART2, RxBuffer[RxCounter++]);
00112     }
00113
00114   }while((RxBuffer[RxCounter - 1] != '\r')&&(RxCounter != RxBufferSize));
00115
00116   while (1)
00117   {
00118   }
00119 }
00120
00121 /**
00122   * @brief  Configures the different system clocks.
00123   * @param  None
00124   * @retval None
00125   */
00126 void RCC_Configuration(void)
00127 {
00128   /* Enable GPIOx and AFIO clocks */
00129   RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOx | RCC_APB2Periph_AFIO, ENABLE);
00130
00131   /* Enable USART2 clocks */
00132   RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE);
00133 }
00134
00135 /**
00136   * @brief  Configures the different GPIO ports.
00137   * @param  None
00138   * @retval None
00139   */
00140 void GPIO_Configuration(void)
00141 {
00142   GPIO_InitTypeDef GPIO_InitStructure;
00143
00144 #if defined(USE_STM3210B_EVAL) || defined(USE_STM32100B_EVAL)
00145   /* Enable the USART2 Pins Software Remapping */
00146   GPIO_PinRemapConfig(GPIO_Remap_USART2, ENABLE);
00147 #endif
00148
00149   /* Configure USART2 RTS and USART2 Tx as alternate function push-pull */
00150   GPIO_InitStructure.GPIO_Pin = GPIO_RTSPin | GPIO_TxPin;
00151   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00152   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
00153   GPIO_Init(GPIOx, &GPIO_InitStructure);
00154
00155   /* Configure USART2 CTS and USART2 Rx as input floating */
00156   GPIO_InitStructure.GPIO_Pin = GPIO_CTSPin | GPIO_RxPin;
00157   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
00158   GPIO_Init(GPIOx, &GPIO_InitStructure);
00159 }
00160
00161 #ifdef  USE_FULL_ASSERT
00162
00163 /**
00164   * @brief  Reports the name of the source file and the source line number
00165   *         where the assert_param error has occurred.
00166   * @param  file: pointer to the source file name
00167   * @param  line: assert_param error line source number
00168   * @retval None
00169   */
00170 void assert_failed(uint8_t* file, uint32_t line)
00171 {
00172   /* User can add his own implementation to report the file name and line number,
00173      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00174
00175   /* Infinite loop */
00176   while (1)
00177   {
00178   }
00179 }
00180
00181 #endif
00182
00183 /**
00184   * @}
00185   */
00186
00187 /**
00188   * @}
00189   */
00190
00191 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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  • HyperTerminal_HwFlowControl

STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/stm32f10x_conf.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    USART/HyperTerminal_HwFlowControl/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052 /* Exported types ------------------------------------------------------------*/
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Uncomment the line below to expanse the "assert_param" macro in the
00055    Standard Peripheral Library drivers code */
00056 /* #define USE_FULL_ASSERT    1 */
00057
00058 /* Exported macro ------------------------------------------------------------*/
00059 #ifdef  USE_FULL_ASSERT
00060 /**
00061   * @brief  The assert_param macro is used for function's parameters check.
00062   * @param  expr: If expr is false, it calls assert_failed function which reports
00063   *         the name of the source file and the source line number of the call
00064   *         that failed. If expr is true, it returns no value.
00065   * @retval None
00066   */
00067   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00068 /* Exported functions ------------------------------------------------------- */
00069   void assert_failed(uint8_t* file, uint32_t line);
00070 #else
00071   #define assert_param(expr) ((void)0)
00072 #endif /* USE_FULL_ASSERT */
00073
00074 #endif /* __STM32F10x_CONF_H */
00075
00076 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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  • HyperTerminal_HwFlowControl

STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/stm32f10x_it.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    USART/HyperTerminal_HwFlowControl/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and
00009   *          peripherals interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026
00027 /** @addtogroup STM32F10x_StdPeriph_Examples
00028   * @{
00029   */
00030
00031 /** @addtogroup USART_HyperTerminal_HwFlowControl
00032   * @{
00033   */
00034
00035 /* Private typedef -----------------------------------------------------------*/
00036 /* Private define ------------------------------------------------------------*/
00037 /* Private macro -------------------------------------------------------------*/
00038 /* Private variables ---------------------------------------------------------*/
00039 /* Private function prototypes -----------------------------------------------*/
00040 /* Private functions ---------------------------------------------------------*/
00041
00042 /******************************************************************************/
00043 /*            Cortex-M3 Processor Exceptions Handlers                         */
00044 /******************************************************************************/
00045
00046 /**
00047   * @brief  This function handles NMI exception.
00048   * @param  None
00049   * @retval None
00050   */
00051 void NMI_Handler(void)
00052 {
00053 }
00054
00055 /**
00056   * @brief  This function handles Hard Fault exception.
00057   * @param  None
00058   * @retval None
00059   */
00060 void HardFault_Handler(void)
00061 {
00062   /* Go to infinite loop when Hard Fault exception occurs */
00063   while (1)
00064   {
00065   }
00066 }
00067
00068 /**
00069   * @brief  This function handles Memory Manage exception.
00070   * @param  None
00071   * @retval None
00072   */
00073 void MemManage_Handler(void)
00074 {
00075   /* Go to infinite loop when Memory Manage exception occurs */
00076   while (1)
00077   {
00078   }
00079 }
00080
00081 /**
00082   * @brief  This function handles Bus Fault exception.
00083   * @param  None
00084   * @retval None
00085   */
00086 void BusFault_Handler(void)
00087 {
00088   /* Go to infinite loop when Bus Fault exception occurs */
00089   while (1)
00090   {
00091   }
00092 }
00093
00094 /**
00095   * @brief  This function handles Usage Fault exception.
00096   * @param  None
00097   * @retval None
00098   */
00099 void UsageFault_Handler(void)
00100 {
00101   /* Go to infinite loop when Usage Fault exception occurs */
00102   while (1)
00103   {
00104   }
00105 }
00106
00107 /**
00108   * @brief  This function handles SVCall exception.
00109   * @param  None
00110   * @retval None
00111   */
00112 void SVC_Handler(void)
00113 {
00114 }
00115
00116 /**
00117   * @brief  This function handles Debug Monitor exception.
00118   * @param  None
00119   * @retval None
00120   */
00121 void DebugMon_Handler(void)
00122 {
00123 }
00124
00125 /**
00126   * @brief  This function handles PendSV_Handler exception.
00127   * @param  None
00128   * @retval None
00129   */
00130 void PendSV_Handler(void)
00131 {
00132 }
00133
00134 /**
00135   * @brief  This function handles SysTick Handler.
00136   * @param  None
00137   * @retval None
00138   */
00139 void SysTick_Handler(void)
00140 {
00141 }
00142
00143 /******************************************************************************/
00144 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00145 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00146 /*  available peripheral interrupt handler's name please refer to the startup */
00147 /*  file (startup_stm32f10x_xx.s).                                            */
00148 /******************************************************************************/
00149
00150 /**
00151   * @brief  This function handles PPP interrupt request.
00152   * @param  None
00153   * @retval None
00154   */
00155 /*void PPP_IRQHandler(void)
00156 {
00157 }*/
00158
00159 /**
00160   * @}
00161   */
00162
00163 /**
00164   * @}
00165   */
00166
00167 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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  • HyperTerminal_HwFlowControl

STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/stm32f10x_it.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    USART/HyperTerminal_HwFlowControl/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043
00044 #endif /* __STM32F10x_IT_H */
00045
00046 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/main.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    USART/HyperTerminal_Interrupt/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x.h"
00024 #include "stm32_eval.h"
00025
00026 /** @addtogroup STM32F10x_StdPeriph_Examples
00027   * @{
00028   */
00029
00030 /** @addtogroup USART_HyperTerminal_Interrupt
00031   * @{
00032   */
00033
00034 /* Private typedef -----------------------------------------------------------*/
00035 /* Private define ------------------------------------------------------------*/
00036 #ifdef USE_STM3210C_EVAL
00037   #define USARTx_IRQn   USART2_IRQn
00038 #else
00039   #define USARTx_IRQn   USART1_IRQn
00040 #endif
00041
00042 /* Private macro -------------------------------------------------------------*/
00043 /* Private variables ---------------------------------------------------------*/
00044 USART_InitTypeDef USART_InitStructure;
00045
00046 /* Private function prototypes -----------------------------------------------*/
00047 void NVIC_Configuration(void);
00048
00049 /* Private functions ---------------------------------------------------------*/
00050
00051 /**
00052   * @brief   Main program
00053   * @param  None
00054   * @retval None
00055   */
00056 int main(void)
00057 {
00058   /*!< At this stage the microcontroller clock setting is already configured,
00059        this is done through SystemInit() function which is called from startup
00060        file (startup_stm32f10x_xx.s) before to branch to application main.
00061        To reconfigure the default setting of SystemInit() function, refer to
00062        system_stm32f10x.c file
00063      */
00064
00065   /* NVIC configuration */
00066   NVIC_Configuration();
00067
00068 /* USARTx configuration ------------------------------------------------------*/
00069   /* USARTx configured as follow:
00070         - BaudRate = 9600 baud
00071         - Word Length = 8 Bits
00072         - Two Stop Bit
00073         - Odd parity
00074         - Hardware flow control disabled (RTS and CTS signals)
00075         - Receive and transmit enabled
00076   */
00077   USART_InitStructure.USART_BaudRate = 9600;
00078   USART_InitStructure.USART_WordLength = USART_WordLength_8b;
00079   USART_InitStructure.USART_StopBits = USART_StopBits_2;
00080   USART_InitStructure.USART_Parity = USART_Parity_Odd;
00081   USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
00082   USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
00083
00084   STM_EVAL_COMInit(COM1, &USART_InitStructure);
00085
00086   /* Enable the EVAL_COM1 Transmit interrupt: this interrupt is generated when the
00087      EVAL_COM1 transmit data register is empty */
00088   USART_ITConfig(EVAL_COM1, USART_IT_TXE, ENABLE);
00089
00090   /* Enable the EVAL_COM1 Receive interrupt: this interrupt is generated when the
00091      EVAL_COM1 receive data register is not empty */
00092   USART_ITConfig(EVAL_COM1, USART_IT_RXNE, ENABLE);
00093
00094   while (1)
00095   {
00096   }
00097 }
00098
00099 /**
00100   * @brief  Configures the nested vectored interrupt controller.
00101   * @param  None
00102   * @retval None
00103   */
00104 void NVIC_Configuration(void)
00105 {
00106   NVIC_InitTypeDef NVIC_InitStructure;
00107
00108   /* Enable the USARTx Interrupt */
00109   NVIC_InitStructure.NVIC_IRQChannel = USARTx_IRQn;
00110   NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
00111   NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
00112   NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
00113   NVIC_Init(&NVIC_InitStructure);
00114 }
00115
00116 #ifdef  USE_FULL_ASSERT
00117
00118 /**
00119   * @brief  Reports the name of the source file and the source line number
00120   *         where the assert_param error has occurred.
00121   * @param  file: pointer to the source file name
00122   * @param  line: assert_param error line source number
00123   * @retval None
00124   */
00125 void assert_failed(uint8_t* file, uint32_t line)
00126 {
00127   /* User can add his own implementation to report the file name and line number,
00128      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00129
00130   /* Infinite loop */
00131   while (1)
00132   {
00133   }
00134 }
00135
00136 #endif
00137
00138 /**
00139   * @}
00140   */
00141
00142 /**
00143   * @}
00144   */
00145
00146 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_conf.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    USART/HyperTerminal_Interrupt/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052 /* Exported types ------------------------------------------------------------*/
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Uncomment the line below to expanse the "assert_param" macro in the
00055    Standard Peripheral Library drivers code */
00056 /* #define USE_FULL_ASSERT    1 */
00057
00058 /* Exported macro ------------------------------------------------------------*/
00059 #ifdef  USE_FULL_ASSERT
00060 /**
00061   * @brief  The assert_param macro is used for function's parameters check.
00062   * @param  expr: If expr is false, it calls assert_failed function which reports
00063   *         the name of the source file and the source line number of the call
00064   *         that failed. If expr is true, it returns no value.
00065   * @retval None
00066   */
00067   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00068 /* Exported functions ------------------------------------------------------- */
00069   void assert_failed(uint8_t* file, uint32_t line);
00070 #else
00071   #define assert_param(expr) ((void)0)
00072 #endif /* USE_FULL_ASSERT */
00073
00074 #endif /* __STM32F10x_CONF_H */
00075
00076 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    USART/HyperTerminal_Interrupt/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and peripherals
00009   *          interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026 #include "stm32_eval.h"
00027
00028 /** @addtogroup STM32F10x_StdPeriph_Examples
00029   * @{
00030   */
00031
00032 /** @addtogroup USART_HyperTerminal_Interrupt
00033   * @{
00034   */
00035
00036 /* Private typedef -----------------------------------------------------------*/
00037 /* Private define ------------------------------------------------------------*/
00038 #ifdef USE_STM3210C_EVAL
00039   #define USARTx_IRQHandler   USART2_IRQHandler
00040 #else
00041   #define USARTx_IRQHandler   USART1_IRQHandler
00042 #endif
00043
00044 #define TxBufferSize   (countof(TxBuffer) - 1)
00045 #define RxBufferSize   0x20
00046
00047 /* Private macro -------------------------------------------------------------*/
00048 #define countof(a)   (sizeof(a) / sizeof(*(a)))
00049
00050 /* Private variables ---------------------------------------------------------*/
00051 uint8_t TxBuffer[] = "\n\rUSART Hyperterminal Interrupts Example: USART-Hyperterminal\
00052  communication using Interrupt\n\r";
00053 uint8_t RxBuffer[RxBufferSize];
00054 uint8_t NbrOfDataToTransfer = TxBufferSize;
00055 uint8_t NbrOfDataToRead = RxBufferSize;
00056 uint8_t TxCounter = 0;
00057 uint16_t RxCounter = 0;
00058
00059 /* Private function prototypes -----------------------------------------------*/
00060 /* Private functions ---------------------------------------------------------*/
00061
00062 /******************************************************************************/
00063 /*            Cortex-M3 Processor Exceptions Handlers                         */
00064 /******************************************************************************/
00065
00066 /**
00067   * @brief  This function handles NMI exception.
00068   * @param  None
00069   * @retval None
00070   */
00071 void NMI_Handler(void)
00072 {
00073 }
00074
00075 /**
00076   * @brief  This function handles Hard Fault exception.
00077   * @param  None
00078   * @retval None
00079   */
00080 void HardFault_Handler(void)
00081 {
00082   /* Go to infinite loop when Hard Fault exception occurs */
00083   while (1)
00084   {
00085   }
00086 }
00087
00088 /**
00089   * @brief  This function handles Memory Manage exception.
00090   * @param  None
00091   * @retval None
00092   */
00093 void MemManage_Handler(void)
00094 {
00095   /* Go to infinite loop when Memory Manage exception occurs */
00096   while (1)
00097   {
00098   }
00099 }
00100
00101 /**
00102   * @brief  This function handles Bus Fault exception.
00103   * @param  None
00104   * @retval None
00105   */
00106 void BusFault_Handler(void)
00107 {
00108   /* Go to infinite loop when Bus Fault exception occurs */
00109   while (1)
00110   {
00111   }
00112 }
00113
00114 /**
00115   * @brief  This function handles Usage Fault exception.
00116   * @param  None
00117   * @retval None
00118   */
00119 void UsageFault_Handler(void)
00120 {
00121   /* Go to infinite loop when Usage Fault exception occurs */
00122   while (1)
00123   {
00124   }
00125 }
00126
00127 /**
00128   * @brief  This function handles SVCall exception.
00129   * @param  None
00130   * @retval None
00131   */
00132 void SVC_Handler(void)
00133 {
00134 }
00135
00136 /**
00137   * @brief  This function handles Debug Monitor exception.
00138   * @param  None
00139   * @retval None
00140   */
00141 void DebugMon_Handler(void)
00142 {
00143 }
00144
00145 /**
00146   * @brief  This function handles PendSV_Handler exception.
00147   * @param  None
00148   * @retval None
00149   */
00150 void PendSV_Handler(void)
00151 {
00152 }
00153
00154 /**
00155   * @brief  This function handles SysTick Handler.
00156   * @param  None
00157   * @retval None
00158   */
00159 void SysTick_Handler(void)
00160 {
00161 }
00162
00163 /******************************************************************************/
00164 /*            STM32F10x Peripherals Interrupt Handlers                        */
00165 /******************************************************************************/
00166
00167 /**
00168   * @brief  This function handles USARTx global interrupt request.
00169   * @param  None
00170   * @retval None
00171   */
00172 void USARTx_IRQHandler(void)
00173 {
00174   if(USART_GetITStatus(EVAL_COM1, USART_IT_RXNE) != RESET)
00175   {
00176     /* Read one byte from the receive data register */
00177     RxBuffer[RxCounter++] = (USART_ReceiveData(EVAL_COM1) & 0x7F);
00178
00179     if(RxCounter == NbrOfDataToRead)
00180     {
00181       /* Disable the EVAL_COM1 Receive interrupt */
00182       USART_ITConfig(EVAL_COM1, USART_IT_RXNE, DISABLE);
00183     }
00184   }
00185
00186   if(USART_GetITStatus(EVAL_COM1, USART_IT_TXE) != RESET)
00187   {
00188     /* Write one byte to the transmit data register */
00189     USART_SendData(EVAL_COM1, TxBuffer[TxCounter++]);
00190
00191     if(TxCounter == NbrOfDataToTransfer)
00192     {
00193       /* Disable the EVAL_COM1 Transmit interrupt */
00194       USART_ITConfig(EVAL_COM1, USART_IT_TXE, DISABLE);
00195     }
00196   }
00197 }
00198
00199 /******************************************************************************/
00200 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00201 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00202 /*  available peripheral interrupt handler's name please refer to the startup */
00203 /*  file (startup_stm32f10x_xx.s).                                            */
00204 /******************************************************************************/
00205
00206 /**
00207   * @brief  This function handles PPP interrupt request.
00208   * @param  None
00209   * @retval None
00210   */
00211 /*void PPP_IRQHandler(void)
00212 {
00213 }*/
00214
00215 /**
00216   * @}
00217   */
00218
00219 /**
00220   * @}
00221   */
00222
00223 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    USART/HyperTerminal_Interrupt/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043 void USART1_IRQHandler(void);
00044 void USART2_IRQHandler(void);
00045
00046 #endif /* __STM32F10x_IT_H */
00047
00048 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c

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00001 /**
00002   ******************************************************************************
00003   * @file    USART/Interrupt/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x.h"
00024 #include "platform_config.h"
00025
00026 /** @addtogroup STM32F10x_StdPeriph_Examples
00027   * @{
00028   */
00029
00030 /** @addtogroup USART_Interrupt
00031   * @{
00032   */
00033
00034 /* Private typedef -----------------------------------------------------------*/
00035 typedef enum { FAILED = 0, PASSED = !FAILED} TestStatus;
00036
00037 /* Private define ------------------------------------------------------------*/
00038 #define TxBufferSize1   (countof(TxBuffer1) - 1)
00039 #define TxBufferSize2   (countof(TxBuffer2) - 1)
00040 #define RxBufferSize1   TxBufferSize2
00041 #define RxBufferSize2   TxBufferSize1
00042
00043 /* Private macro -------------------------------------------------------------*/
00044 #define countof(a)   (sizeof(a) / sizeof(*(a)))
00045
00046 /* Private variables ---------------------------------------------------------*/
00047 USART_InitTypeDef USART_InitStructure;
00048 uint8_t TxBuffer1[] = "USART Interrupt Example: USARTy -> USARTz using Interrupt";
00049 uint8_t TxBuffer2[] = "USART Interrupt Example: USARTz -> USARTy using Interrupt";
00050 uint8_t RxBuffer1[RxBufferSize1];
00051 uint8_t RxBuffer2[RxBufferSize2];
00052 __IO uint8_t TxCounter1 = 0x00;
00053 __IO uint8_t TxCounter2 = 0x00;
00054 __IO uint8_t RxCounter1 = 0x00;
00055 __IO uint8_t RxCounter2 = 0x00;
00056 uint8_t NbrOfDataToTransfer1 = TxBufferSize1;
00057 uint8_t NbrOfDataToTransfer2 = TxBufferSize2;
00058 uint8_t NbrOfDataToRead1 = RxBufferSize1;
00059 uint8_t NbrOfDataToRead2 = RxBufferSize2;
00060 __IO TestStatus TransferStatus1 = FAILED;
00061 __IO TestStatus TransferStatus2 = FAILED;
00062
00063 /* Private function prototypes -----------------------------------------------*/
00064 void RCC_Configuration(void);
00065 void GPIO_Configuration(void);
00066 void NVIC_Configuration(void);
00067 TestStatus Buffercmp(uint8_t* pBuffer1, uint8_t* pBuffer2, uint16_t BufferLength);
00068
00069 /* Private functions ---------------------------------------------------------*/
00070
00071 /**
00072   * @brief   Main program
00073   * @param  None
00074   * @retval None
00075   */
00076 int main(void)
00077 {
00078   /*!< At this stage the microcontroller clock setting is already configured,
00079        this is done through SystemInit() function which is called from startup
00080        file (startup_stm32f10x_xx.s) before to branch to application main.
00081        To reconfigure the default setting of SystemInit() function, refer to
00082        system_stm32f10x.c file
00083      */
00084
00085   /* System Clocks Configuration */
00086   RCC_Configuration();
00087
00088   /* NVIC configuration */
00089   NVIC_Configuration();
00090
00091   /* Configure the GPIO ports */
00092   GPIO_Configuration();
00093
00094 /* USARTy and USARTz configuration ------------------------------------------------------*/
00095   /* USARTy and USARTz configured as follow:
00096         - BaudRate = 9600 baud
00097         - Word Length = 8 Bits
00098         - One Stop Bit
00099         - No parity
00100         - Hardware flow control disabled (RTS and CTS signals)
00101         - Receive and transmit enabled
00102   */
00103   USART_InitStructure.USART_BaudRate = 9600;
00104   USART_InitStructure.USART_WordLength = USART_WordLength_8b;
00105   USART_InitStructure.USART_StopBits = USART_StopBits_1;
00106   USART_InitStructure.USART_Parity = USART_Parity_No;
00107   USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
00108   USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
00109
00110   /* Configure USARTy */
00111   USART_Init(USARTy, &USART_InitStructure);
00112   /* Configure USARTz */
00113   USART_Init(USARTz, &USART_InitStructure);
00114
00115   /* Enable USARTy Receive and Transmit interrupts */
00116   USART_ITConfig(USARTy, USART_IT_RXNE, ENABLE);
00117   USART_ITConfig(USARTy, USART_IT_TXE, ENABLE);
00118
00119   /* Enable USARTz Receive and Transmit interrupts */
00120   USART_ITConfig(USARTz, USART_IT_RXNE, ENABLE);
00121   USART_ITConfig(USARTz, USART_IT_TXE, ENABLE);
00122
00123   /* Enable the USARTy */
00124   USART_Cmd(USARTy, ENABLE);
00125   /* Enable the USARTz */
00126   USART_Cmd(USARTz, ENABLE);
00127
00128   /* Wait until end of transmission from USARTy to USARTz */
00129   while(RxCounter2 < RxBufferSize2)
00130   {
00131   }
00132
00133   /* Wait until end of transmission from USARTz to USARTy */
00134   while(RxCounter1 < RxBufferSize1)
00135   {
00136   }
00137
00138   /* Check the received data with the send ones */
00139   TransferStatus1 = Buffercmp(TxBuffer2, RxBuffer1, RxBufferSize1);
00140   /* TransferStatus1 = PASSED, if the data transmitted from USARTz and
00141      received by USARTy are the same */
00142   /* TransferStatus1 = FAILED, if the data transmitted from USARTz and
00143      received by USARTy are different */
00144   TransferStatus2 = Buffercmp(TxBuffer1, RxBuffer2, RxBufferSize2);
00145   /* TransferStatus2 = PASSED, if the data transmitted from USARTy and
00146      received by USARTz are the same */
00147   /* TransferStatus2 = FAILED, if the data transmitted from USARTy and
00148      received by USARTz are different */
00149
00150   while (1)
00151   {
00152   }
00153 }
00154
00155 /**
00156   * @brief  Configures the different system clocks.
00157   * @param  None
00158   * @retval None
00159   */
00160 void RCC_Configuration(void)
00161 {
00162   /* Enable GPIO clock */
00163   RCC_APB2PeriphClockCmd(USARTy_GPIO_CLK | USARTz_GPIO_CLK | RCC_APB2Periph_AFIO, ENABLE);
00164
00165 #ifndef USE_STM3210C_EVAL
00166   /* Enable USARTy Clock */
00167   RCC_APB2PeriphClockCmd(USARTy_CLK, ENABLE);
00168 #else
00169   /* Enable USARTy Clock */
00170   RCC_APB1PeriphClockCmd(USARTy_CLK, ENABLE);
00171 #endif
00172   /* Enable USARTz Clock */
00173   RCC_APB1PeriphClockCmd(USARTz_CLK, ENABLE);
00174 }
00175
00176 /**
00177   * @brief  Configures the different GPIO ports.
00178   * @param  None
00179   * @retval None
00180   */
00181 void GPIO_Configuration(void)
00182 {
00183   GPIO_InitTypeDef GPIO_InitStructure;
00184
00185 #ifdef USE_STM3210C_EVAL
00186   /* Enable the USART3 Pins Software Remapping */
00187   GPIO_PinRemapConfig(GPIO_PartialRemap_USART3, ENABLE);
00188
00189   /* Enable the USART2 Pins Software Remapping */
00190   GPIO_PinRemapConfig(GPIO_Remap_USART2, ENABLE);
00191 #elif defined USE_STM3210B_EVAL || defined USE_STM32100B_EVAL
00192   /* Enable the USART2 Pins Software Remapping */
00193   GPIO_PinRemapConfig(GPIO_Remap_USART2, ENABLE);
00194 #endif
00195
00196   /* Configure USARTy Rx as input floating */
00197   GPIO_InitStructure.GPIO_Pin = USARTy_RxPin;
00198   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
00199   GPIO_Init(USARTy_GPIO, &GPIO_InitStructure);
00200
00201   /* Configure USARTz Rx as input floating */
00202   GPIO_InitStructure.GPIO_Pin = USARTz_RxPin;
00203   GPIO_Init(USARTz_GPIO, &GPIO_InitStructure);
00204
00205   /* Configure USARTy Tx as alternate function push-pull */
00206   GPIO_InitStructure.GPIO_Pin = USARTy_TxPin;
00207   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00208   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
00209   GPIO_Init(USARTy_GPIO, &GPIO_InitStructure);
00210
00211   /* Configure USARTz Tx as alternate function push-pull */
00212   GPIO_InitStructure.GPIO_Pin = USARTz_TxPin;
00213   GPIO_Init(USARTz_GPIO, &GPIO_InitStructure);
00214 }
00215
00216 /**
00217   * @brief  Configures the nested vectored interrupt controller.
00218   * @param  None
00219   * @retval None
00220   */
00221 void NVIC_Configuration(void)
00222 {
00223   NVIC_InitTypeDef NVIC_InitStructure;
00224
00225   /* Configure the NVIC Preemption Priority Bits */
00226   NVIC_PriorityGroupConfig(NVIC_PriorityGroup_0);
00227
00228   /* Enable the USARTy Interrupt */
00229   NVIC_InitStructure.NVIC_IRQChannel = USARTy_IRQn;
00230   NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
00231   NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
00232   NVIC_Init(&NVIC_InitStructure);
00233
00234   /* Enable the USARTz Interrupt */
00235   NVIC_InitStructure.NVIC_IRQChannel = USARTz_IRQn;
00236   NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;
00237   NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
00238   NVIC_Init(&NVIC_InitStructure);
00239 }
00240
00241 /**
00242   * @brief  Compares two buffers.
00243   * @param  pBuffer1, pBuffer2: buffers to be compared.
00244   * @param  BufferLength: buffer's length
00245   * @retval PASSED: pBuffer1 identical to pBuffer2
00246   *         FAILED: pBuffer1 differs from pBuffer2
00247   */
00248 TestStatus Buffercmp(uint8_t* pBuffer1, uint8_t* pBuffer2, uint16_t BufferLength)
00249 {
00250   while(BufferLength--)
00251   {
00252     if(*pBuffer1 != *pBuffer2)
00253     {
00254       return FAILED;
00255     }
00256
00257     pBuffer1++;
00258     pBuffer2++;
00259   }
00260
00261   return PASSED;
00262 }
00263
00264 #ifdef  USE_FULL_ASSERT
00265
00266 /**
00267   * @brief  Reports the name of the source file and the source line number
00268   *         where the assert_param error has occurred.
00269   * @param  file: pointer to the source file name
00270   * @param  line: assert_param error line source number
00271   * @retval None
00272   */
00273 void assert_failed(uint8_t* file, uint32_t line)
00274 {
00275   /* User can add his own implementation to report the file name and line number,
00276      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00277
00278   /* Infinite loop */
00279   while (1)
00280   {
00281   }
00282 }
00283
00284 #endif
00285
00286 /**
00287   * @}
00288   */
00289
00290 /**
00291   * @}
00292   */
00293
00294 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_conf.h

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00001 /**
00002   ******************************************************************************
00003   * @file    USART/Interrupt/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052 /* Exported types ------------------------------------------------------------*/
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Uncomment the line below to expanse the "assert_param" macro in the
00055    Standard Peripheral Library drivers code */
00056 /* #define USE_FULL_ASSERT    1 */
00057
00058 /* Exported macro ------------------------------------------------------------*/
00059 #ifdef  USE_FULL_ASSERT
00060 /**
00061   * @brief  The assert_param macro is used for function's parameters check.
00062   * @param  expr: If expr is false, it calls assert_failed function which reports
00063   *         the name of the source file and the source line number of the call
00064   *         that failed. If expr is true, it returns no value.
00065   * @retval None
00066   */
00067   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00068 /* Exported functions ------------------------------------------------------- */
00069   void assert_failed(uint8_t* file, uint32_t line);
00070 #else
00071   #define assert_param(expr) ((void)0)
00072 #endif /* USE_FULL_ASSERT */
00073
00074 #endif /* __STM32F10x_CONF_H */
00075
00076 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.c

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00001 /**
00002   ******************************************************************************
00003   * @file    USART/Interrupt/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and peripherals
00009   *          interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026 #include "platform_config.h"
00027
00028 /** @addtogroup STM32F10x_StdPeriph_Examples
00029   * @{
00030   */
00031
00032 /** @addtogroup USART_Interrupt
00033   * @{
00034   */
00035
00036 /* Private typedef -----------------------------------------------------------*/
00037 /* Private define ------------------------------------------------------------*/
00038 /* Private macro -------------------------------------------------------------*/
00039 /* Private variables ---------------------------------------------------------*/
00040 extern uint8_t TxBuffer1[];
00041 extern uint8_t TxBuffer2[];
00042 extern uint8_t RxBuffer1[];
00043 extern uint8_t RxBuffer2[];
00044 extern __IO uint8_t TxCounter1;
00045 extern __IO uint8_t TxCounter2;
00046 extern __IO uint8_t RxCounter1;
00047 extern __IO uint8_t RxCounter2;
00048 extern uint8_t NbrOfDataToTransfer1;
00049 extern uint8_t NbrOfDataToTransfer2;
00050 extern uint8_t NbrOfDataToRead1;
00051 extern uint8_t NbrOfDataToRead2;
00052
00053 /* Private function prototypes -----------------------------------------------*/
00054 /* Private functions ---------------------------------------------------------*/
00055
00056 /******************************************************************************/
00057 /*            Cortex-M3 Processor Exceptions Handlers                         */
00058 /******************************************************************************/
00059
00060 /**
00061   * @brief  This function handles NMI exception.
00062   * @param  None
00063   * @retval None
00064   */
00065 void NMI_Handler(void)
00066 {
00067 }
00068
00069 /**
00070   * @brief  This function handles Hard Fault exception.
00071   * @param  None
00072   * @retval None
00073   */
00074 void HardFault_Handler(void)
00075 {
00076   /* Go to infinite loop when Hard Fault exception occurs */
00077   while (1)
00078   {
00079   }
00080 }
00081
00082 /**
00083   * @brief  This function handles Memory Manage exception.
00084   * @param  None
00085   * @retval None
00086   */
00087 void MemManage_Handler(void)
00088 {
00089   /* Go to infinite loop when Memory Manage exception occurs */
00090   while (1)
00091   {
00092   }
00093 }
00094
00095 /**
00096   * @brief  This function handles Bus Fault exception.
00097   * @param  None
00098   * @retval None
00099   */
00100 void BusFault_Handler(void)
00101 {
00102   /* Go to infinite loop when Bus Fault exception occurs */
00103   while (1)
00104   {
00105   }
00106 }
00107
00108 /**
00109   * @brief  This function handles Usage Fault exception.
00110   * @param  None
00111   * @retval None
00112   */
00113 void UsageFault_Handler(void)
00114 {
00115   /* Go to infinite loop when Usage Fault exception occurs */
00116   while (1)
00117   {
00118   }
00119 }
00120
00121 /**
00122   * @brief  This function handles SVCall exception.
00123   * @param  None
00124   * @retval None
00125   */
00126 void SVC_Handler(void)
00127 {
00128 }
00129
00130 /**
00131   * @brief  This function handles Debug Monitor exception.
00132   * @param  None
00133   * @retval None
00134   */
00135 void DebugMon_Handler(void)
00136 {
00137 }
00138
00139 /**
00140   * @brief  This function handles PendSV_Handler exception.
00141   * @param  None
00142   * @retval None
00143   */
00144 void PendSV_Handler(void)
00145 {
00146 }
00147
00148 /**
00149   * @brief  This function handles SysTick Handler.
00150   * @param  None
00151   * @retval None
00152   */
00153 void SysTick_Handler(void)
00154 {
00155 }
00156
00157 /******************************************************************************/
00158 /*            STM32F10x Peripherals Interrupt Handlers                        */
00159 /******************************************************************************/
00160
00161 /**
00162   * @brief  This function handles USARTy global interrupt request.
00163   * @param  None
00164   * @retval None
00165   */
00166 void USARTy_IRQHandler(void)
00167 {
00168   if(USART_GetITStatus(USARTy, USART_IT_RXNE) != RESET)
00169   {
00170     /* Read one byte from the receive data register */
00171     RxBuffer1[RxCounter1++] = USART_ReceiveData(USARTy);
00172
00173     if(RxCounter1 == NbrOfDataToRead1)
00174     {
00175       /* Disable the USARTy Receive interrupt */
00176       USART_ITConfig(USARTy, USART_IT_RXNE, DISABLE);
00177     }
00178   }
00179
00180   if(USART_GetITStatus(USARTy, USART_IT_TXE) != RESET)
00181   {
00182     /* Write one byte to the transmit data register */
00183     USART_SendData(USARTy, TxBuffer1[TxCounter1++]);
00184
00185     if(TxCounter1 == NbrOfDataToTransfer1)
00186     {
00187       /* Disable the USARTy Transmit interrupt */
00188       USART_ITConfig(USARTy, USART_IT_TXE, DISABLE);
00189     }
00190   }
00191 }
00192
00193 /**
00194   * @brief  This function handles USARTz global interrupt request.
00195   * @param  None
00196   * @retval None
00197   */
00198 void USARTz_IRQHandler(void)
00199 {
00200   if(USART_GetITStatus(USARTz, USART_IT_RXNE) != RESET)
00201   {
00202     /* Read one byte from the receive data register */
00203     RxBuffer2[RxCounter2++] = USART_ReceiveData(USARTz);
00204
00205     if(RxCounter2 == NbrOfDataToRead1)
00206     {
00207       /* Disable the USARTz Receive interrupt */
00208       USART_ITConfig(USARTz, USART_IT_RXNE, DISABLE);
00209     }
00210   }
00211
00212   if(USART_GetITStatus(USARTz, USART_IT_TXE) != RESET)
00213   {
00214     /* Write one byte to the transmit data register */
00215     USART_SendData(USARTz, TxBuffer2[TxCounter2++]);
00216
00217     if(TxCounter2 == NbrOfDataToTransfer2)
00218     {
00219       /* Disable the USARTz Transmit interrupt */
00220       USART_ITConfig(USARTz, USART_IT_TXE, DISABLE);
00221     }
00222   }
00223 }
00224
00225 /******************************************************************************/
00226 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00227 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00228 /*  available peripheral interrupt handler's name please refer to the startup */
00229 /*  file (startup_stm32f10x_xx.s).                                            */
00230 /******************************************************************************/
00231
00232 /**
00233   * @brief  This function handles PPP interrupt request.
00234   * @param  None
00235   * @retval None
00236   */
00237 /*void PPP_IRQHandler(void)
00238 {
00239 }*/
00240
00241 /**
00242   * @}
00243   */
00244
00245 /**
00246   * @}
00247   */
00248
00249 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.h

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00001 /**
00002   ******************************************************************************
00003   * @file    USART/Interrupt/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043 void USART1_IRQHandler(void);
00044 void USART2_IRQHandler(void);
00045 void USART3_IRQHandler(void);
00046
00047 #endif /* __STM32F10x_IT_H */
00048
00049 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/main.c

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00001 /**
00002   ******************************************************************************
00003   * @file    USART/IrDA/Receive/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x.h"
00024 #include "platform_config.h"
00025
00026 /** @addtogroup STM32F10x_StdPeriph_Examples
00027   * @{
00028   */
00029
00030 /** @addtogroup USART_IrDA_Receive
00031   * @{
00032   */
00033
00034 /* Private typedef -----------------------------------------------------------*/
00035 /* Private define ------------------------------------------------------------*/
00036 /* Private macro -------------------------------------------------------------*/
00037 /* Private variables ---------------------------------------------------------*/
00038 USART_InitTypeDef USART_InitStructure;
00039 JOYState_TypeDef ReceivedData = JOY_NONE;
00040
00041 /* Private function prototypes -----------------------------------------------*/
00042 void RCC_Configuration(void);
00043 void GPIO_Configuration(void);
00044
00045 /* Private functions ---------------------------------------------------------*/
00046
00047 /**
00048   * @brief  Main program
00049   * @param  None
00050   * @retval None
00051   */
00052 int main(void)
00053 {
00054   /*!< At this stage the microcontroller clock setting is already configured,
00055        this is done through SystemInit() function which is called from startup
00056        file (startup_stm32f10x_xx.s) before to branch to application main.
00057        To reconfigure the default setting of SystemInit() function, refer to
00058        system_stm32f10x.c file
00059      */
00060
00061   /* System Clocks Configuration */
00062   RCC_Configuration();
00063
00064   /* Configure the GPIO ports */
00065   GPIO_Configuration();
00066
00067   /* Initialize Leds mounted on STM3210X-EVAL board */
00068   STM_EVAL_LEDInit(LED1);
00069   STM_EVAL_LEDInit(LED2);
00070   STM_EVAL_LEDInit(LED3);
00071   STM_EVAL_LEDInit(LED4);
00072
00073 /* USARTy configuration ------------------------------------------------------*/
00074   /* USARTy configured as follow:
00075         - BaudRate = 115200 baud
00076         - Word Length = 8 Bits
00077         - One Stop Bit
00078         - No parity
00079         - Hardware flow control disabled (RTS and CTS signals)
00080         - Receive and transmit enabled
00081   */
00082   USART_InitStructure.USART_BaudRate = 115200;
00083   USART_InitStructure.USART_WordLength = USART_WordLength_8b;
00084   USART_InitStructure.USART_StopBits = USART_StopBits_1;
00085   USART_InitStructure.USART_Parity = USART_Parity_No ;
00086   USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
00087   USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
00088
00089   /* Configure the USARTy */
00090   USART_Init(USARTy, &USART_InitStructure);
00091   /* Enable the USARTy */
00092   USART_Cmd(USARTy, ENABLE);
00093
00094   /* Set the USARTy prescaler */
00095   USART_SetPrescaler(USARTy, 0x1);
00096   /* Configure the USARTy IrDA mode */
00097   USART_IrDAConfig(USARTy, USART_IrDAMode_Normal);
00098
00099   /* Enable the USARTy IrDA mode */
00100   USART_IrDACmd(USARTy, ENABLE);
00101
00102   while (1)
00103   {
00104     /* Wait until a byte is received */
00105     while(USART_GetFlagStatus(USARTy, USART_FLAG_RXNE) == RESET)
00106     {
00107     }
00108     /* Read the received byte */
00109     ReceivedData = (JOYState_TypeDef)USART_ReceiveData(USARTy);
00110
00111     switch(ReceivedData)
00112     {
00113       case JOY_UP:
00114         STM_EVAL_LEDOn(LED1);
00115         STM_EVAL_LEDOff(LED2);
00116         STM_EVAL_LEDOff(LED3);
00117         STM_EVAL_LEDOff(LED4);
00118         break;
00119       case JOY_DOWN:
00120         STM_EVAL_LEDOn(LED2);
00121         STM_EVAL_LEDOff(LED1);
00122         STM_EVAL_LEDOff(LED3);
00123         STM_EVAL_LEDOff(LED4);
00124         break;
00125       case JOY_LEFT:
00126         STM_EVAL_LEDOn(LED3);
00127         STM_EVAL_LEDOff(LED1);
00128         STM_EVAL_LEDOff(LED2);
00129         STM_EVAL_LEDOff(LED4);
00130         break;
00131       case JOY_RIGHT:
00132         STM_EVAL_LEDOn(LED4);
00133         STM_EVAL_LEDOff(LED1);
00134         STM_EVAL_LEDOff(LED2);
00135         STM_EVAL_LEDOff(LED3);
00136         break;
00137       case JOY_SEL:
00138         STM_EVAL_LEDOn(LED1);
00139         STM_EVAL_LEDOn(LED2);
00140         STM_EVAL_LEDOn(LED3);
00141         STM_EVAL_LEDOn(LED4);
00142         break;
00143       case JOY_NONE:
00144         break;
00145       default:
00146         break;
00147     }
00148   }
00149 }
00150
00151 /**
00152   * @brief  Configures the different system clocks.
00153   * @param  None
00154   * @retval None
00155   */
00156 void RCC_Configuration(void)
00157 {
00158   /* Enable GPIO clock */
00159   RCC_APB2PeriphClockCmd(USARTy_GPIO_CLK | RCC_APB2Periph_AFIO, ENABLE);
00160
00161   /* Enable USARTy clocks */
00162   RCC_APB1PeriphClockCmd(USARTy_CLK, ENABLE);
00163 }
00164
00165 /**
00166   * @brief  Configures the different GPIO ports.
00167   * @param  None
00168   * @retval None
00169   */
00170 void GPIO_Configuration(void)
00171 {
00172   GPIO_InitTypeDef GPIO_InitStructure;
00173
00174 #ifndef USE_STM3210C_EVAL
00175   /* Enable the USART3 Pins Partial Software Remapping */
00176   GPIO_PinRemapConfig(GPIO_PartialRemap_USART3, ENABLE);
00177 #else
00178   /* Enable the USART2 Pins Software Remapping */
00179   GPIO_PinRemapConfig(GPIO_Remap_USART2, ENABLE);
00180 #endif
00181
00182   /* Configure USARTy Tx as alternate function push-pull */
00183   GPIO_InitStructure.GPIO_Pin = USARTy_TxPin;
00184   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00185   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
00186   GPIO_Init(USARTy_GPIO, &GPIO_InitStructure);
00187
00188   /* Configure USARTy Rx as input floating */
00189   GPIO_InitStructure.GPIO_Pin = USARTy_RxPin;
00190   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
00191   GPIO_Init(USARTy_GPIO, &GPIO_InitStructure);
00192 }
00193
00194 #ifdef  USE_FULL_ASSERT
00195
00196 /**
00197   * @brief  Reports the name of the source file and the source line number
00198   *         where the assert_param error has occurred.
00199   * @param  file: pointer to the source file name
00200   * @param  line: assert_param error line source number
00201   * @retval None
00202   */
00203 void assert_failed(uint8_t* file, uint32_t line)
00204 {
00205   /* User can add his own implementation to report the file name and line number,
00206      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00207
00208   /* Infinite loop */
00209   while (1)
00210   {
00211   }
00212 }
00213
00214 #endif
00215
00216 /**
00217   * @}
00218   */
00219
00220 /**
00221   * @}
00222   */
00223
00224 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/stm32f10x_conf.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    USART/IrDA/Receive/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052 /* Exported types ------------------------------------------------------------*/
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Uncomment the line below to expanse the "assert_param" macro in the
00055    Standard Peripheral Library drivers code */
00056 /* #define USE_FULL_ASSERT    1 */
00057
00058 /* Exported macro ------------------------------------------------------------*/
00059 #ifdef  USE_FULL_ASSERT
00060 /**
00061   * @brief  The assert_param macro is used for function's parameters check.
00062   * @param  expr: If expr is false, it calls assert_failed function which reports
00063   *         the name of the source file and the source line number of the call
00064   *         that failed. If expr is true, it returns no value.
00065   * @retval None
00066   */
00067   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00068 /* Exported functions ------------------------------------------------------- */
00069   void assert_failed(uint8_t* file, uint32_t line);
00070 #else
00071   #define assert_param(expr) ((void)0)
00072 #endif /* USE_FULL_ASSERT */
00073
00074 #endif /* __STM32F10x_CONF_H */
00075
00076 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/stm32f10x_it.c

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00001 /**
00002   ******************************************************************************
00003   * @file    USART/IrDA/Receive/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and peripherals
00009   *          interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026
00027 /** @addtogroup STM32F10x_StdPeriph_Examples
00028   * @{
00029   */
00030
00031 /** @addtogroup USART_IrDA_Receive
00032   * @{
00033   */
00034
00035 /* Private typedef -----------------------------------------------------------*/
00036 /* Private define ------------------------------------------------------------*/
00037 /* Private macro -------------------------------------------------------------*/
00038 /* Private variables ---------------------------------------------------------*/
00039 /* Private function prototypes -----------------------------------------------*/
00040 /* Private functions ---------------------------------------------------------*/
00041
00042 /******************************************************************************/
00043 /*            Cortex-M3 Processor Exceptions Handlers                         */
00044 /******************************************************************************/
00045
00046 /**
00047   * @brief  This function handles NMI exception.
00048   * @param  None
00049   * @retval None
00050   */
00051 void NMI_Handler(void)
00052 {
00053 }
00054
00055 /**
00056   * @brief  This function handles Hard Fault exception.
00057   * @param  None
00058   * @retval None
00059   */
00060 void HardFault_Handler(void)
00061 {
00062   /* Go to infinite loop when Hard Fault exception occurs */
00063   while (1)
00064   {
00065   }
00066 }
00067
00068 /**
00069   * @brief  This function handles Memory Manage exception.
00070   * @param  None
00071   * @retval None
00072   */
00073 void MemManage_Handler(void)
00074 {
00075   /* Go to infinite loop when Memory Manage exception occurs */
00076   while (1)
00077   {
00078   }
00079 }
00080
00081 /**
00082   * @brief  This function handles Bus Fault exception.
00083   * @param  None
00084   * @retval None
00085   */
00086 void BusFault_Handler(void)
00087 {
00088   /* Go to infinite loop when Bus Fault exception occurs */
00089   while (1)
00090   {
00091   }
00092 }
00093
00094 /**
00095   * @brief  This function handles Usage Fault exception.
00096   * @param  None
00097   * @retval None
00098   */
00099 void UsageFault_Handler(void)
00100 {
00101   /* Go to infinite loop when Usage Fault exception occurs */
00102   while (1)
00103   {
00104   }
00105 }
00106
00107 /**
00108   * @brief  This function handles SVCall exception.
00109   * @param  None
00110   * @retval None
00111   */
00112 void SVC_Handler(void)
00113 {
00114 }
00115
00116 /**
00117   * @brief  This function handles Debug Monitor exception.
00118   * @param  None
00119   * @retval None
00120   */
00121 void DebugMon_Handler(void)
00122 {
00123 }
00124
00125 /**
00126   * @brief  This function handles PendSV_Handler exception.
00127   * @param  None
00128   * @retval None
00129   */
00130 void PendSV_Handler(void)
00131 {
00132 }
00133
00134 /**
00135   * @brief  This function handles SysTick Handler.
00136   * @param  None
00137   * @retval None
00138   */
00139 void SysTick_Handler(void)
00140 {
00141 }
00142
00143 /******************************************************************************/
00144 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00145 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00146 /*  available peripheral interrupt handler's name please refer to the startup */
00147 /*  file (startup_stm32f10x_xx.s).                                            */
00148 /******************************************************************************/
00149
00150 /**
00151   * @brief  This function handles PPP interrupt request.
00152   * @param  None
00153   * @retval None
00154   */
00155 /*void PPP_IRQHandler(void)
00156 {
00157 }*/
00158
00159 /**
00160   * @}
00161   */
00162
00163 /**
00164   * @}
00165   */
00166
00167 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/stm32f10x_it.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    USART/IrDA/Receive/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043
00044 #endif /* __STM32F10x_IT_H */
00045
00046 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/main.c

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00001 /**
00002   ******************************************************************************
00003   * @file    USART/IrDA/Transmit/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x.h"
00024 #include "platform_config.h"
00025
00026 /** @addtogroup STM32F10x_StdPeriph_Examples
00027   * @{
00028   */
00029
00030 /** @addtogroup USART_IrDA_Transmit
00031   * @{
00032   */
00033
00034 /* Private typedef -----------------------------------------------------------*/
00035 /* Private define ------------------------------------------------------------*/
00036 /* Private macro -------------------------------------------------------------*/
00037 /* Private variables ---------------------------------------------------------*/
00038 USART_InitTypeDef USART_InitStructure;
00039 JOYState_TypeDef MyKey = JOY_NONE;
00040
00041 /* Private function prototypes -----------------------------------------------*/
00042 void RCC_Configuration(void);
00043 void GPIO_Configuration(void);
00044 JOYState_TypeDef ReadKey(void);
00045
00046 /* Private functions ---------------------------------------------------------*/
00047
00048 /**
00049   * @brief  Main program
00050   * @param  None
00051   * @retval None
00052   */
00053 int main(void)
00054 {
00055   /*!< At this stage the microcontroller clock setting is already configured,
00056        this is done through SystemInit() function which is called from startup
00057        file (startup_stm32f10x_xx.s) before to branch to application main.
00058        To reconfigure the default setting of SystemInit() function, refer to
00059        system_stm32f10x.c file
00060      */
00061
00062   /* System Clocks Configuration */
00063   RCC_Configuration();
00064
00065   /* Configure the GPIO ports */
00066   GPIO_Configuration();
00067
00068 #ifndef USE_STM3210C_EVAL
00069   /* Initialize JoyStick Button mounted on STM3210X-EVAL board */
00070   STM_EVAL_PBInit(BUTTON_UP, BUTTON_MODE_GPIO);
00071   STM_EVAL_PBInit(BUTTON_DOWN, BUTTON_MODE_GPIO);
00072   STM_EVAL_PBInit(BUTTON_LEFT, BUTTON_MODE_GPIO);
00073   STM_EVAL_PBInit(BUTTON_RIGHT, BUTTON_MODE_GPIO);
00074   STM_EVAL_PBInit(BUTTON_SEL, BUTTON_MODE_GPIO);
00075 #else
00076   /* Configure the IO Expander */
00077   if (IOE_Config())
00078   {
00079     /* IO Expander config error */
00080     while(1);
00081   }
00082
00083 #endif
00084
00085 /* USARTy configuration ------------------------------------------------------*/
00086   /* USARTy configured as follow:
00087         - BaudRate = 115200 baud
00088         - Word Length = 8 Bits
00089         - One Stop Bit
00090         - No parity
00091         - Hardware flow control disabled (RTS and CTS signals)
00092         - Receive and transmit enabled
00093   */
00094   USART_InitStructure.USART_BaudRate = 115200;
00095   USART_InitStructure.USART_WordLength = USART_WordLength_8b;
00096   USART_InitStructure.USART_StopBits = USART_StopBits_1;
00097   USART_InitStructure.USART_Parity = USART_Parity_No ;
00098   USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
00099   USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
00100
00101   /* Configure the USARTy */
00102   USART_Init(USARTy, &USART_InitStructure);
00103   /* Enable the USARTy */
00104   USART_Cmd(USARTy, ENABLE);
00105   /* Set the USARTy prescaler */
00106   USART_SetPrescaler(USARTy, 0x1);
00107   /* Configure the USARTy IrDA mode */
00108   USART_IrDAConfig(USARTy, USART_IrDAMode_Normal);
00109
00110   /* Enable the USARTy IrDA mode */
00111   USART_IrDACmd(USARTy, ENABLE);
00112
00113
00114   while (1)
00115   {
00116     /* Read Key */
00117     MyKey = ReadKey();
00118
00119     switch(MyKey)
00120     {
00121       case JOY_UP:
00122         USART_SendData(USARTy, JOY_UP);
00123         while(USART_GetFlagStatus(USARTy, USART_FLAG_TXE) == RESET)
00124         {
00125         }
00126         break;
00127       case JOY_DOWN:
00128         USART_SendData(USARTy, JOY_DOWN);
00129         while(USART_GetFlagStatus(USARTy, USART_FLAG_TXE) == RESET)
00130         {
00131         }
00132         break;
00133       case JOY_LEFT:
00134         USART_SendData(USARTy, JOY_LEFT);
00135         while(USART_GetFlagStatus(USARTy, USART_FLAG_TXE) == RESET)
00136         {
00137         }
00138         break;
00139       case JOY_RIGHT:
00140         USART_SendData(USARTy, JOY_RIGHT);
00141         while(USART_GetFlagStatus(USARTy, USART_FLAG_TXE) == RESET)
00142         {
00143         }
00144         break;
00145       case JOY_SEL:
00146         USART_SendData(USARTy, JOY_SEL);
00147         while(USART_GetFlagStatus(USARTy, USART_FLAG_TXE) == RESET)
00148         {
00149         }
00150         break;
00151       case JOY_NONE:
00152         USART_SendData(USARTy, JOY_NONE);
00153         while(USART_GetFlagStatus(USARTy, USART_FLAG_TXE) == RESET)
00154         {
00155         }
00156         break;
00157       default:
00158         break;
00159     }
00160   }
00161 }
00162
00163 /**
00164   * @brief  Configures the different system clocks.
00165   * @param  None
00166   * @retval None
00167   */
00168 void RCC_Configuration(void)
00169 {
00170   /* Enable GPIO clock */
00171   RCC_APB2PeriphClockCmd(USARTy_GPIO_CLK | RCC_APB2Periph_AFIO, ENABLE);
00172
00173   /* Enable USARTy clocks */
00174   RCC_APB1PeriphClockCmd(USARTy_CLK, ENABLE);
00175 }
00176
00177 /**
00178   * @brief  Configures the different GPIO ports.
00179   * @param  None
00180   * @retval None
00181   */
00182 void GPIO_Configuration(void)
00183 {
00184   GPIO_InitTypeDef GPIO_InitStructure;
00185
00186 #ifndef USE_STM3210C_EVAL
00187   /* Enable the USART3 Pins Partial Software Remapping */
00188   GPIO_PinRemapConfig(GPIO_PartialRemap_USART3, ENABLE);
00189 #else
00190   /* Enable the USART2 Pins Software Remapping */
00191   GPIO_PinRemapConfig(GPIO_Remap_USART2, ENABLE);
00192 #endif
00193
00194   /* Configure USARTy Tx as alternate function push-pull */
00195   GPIO_InitStructure.GPIO_Pin = USARTy_TxPin;
00196   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00197   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
00198   GPIO_Init(USARTy_GPIO, &GPIO_InitStructure);
00199
00200   /* Configure USARTy Rx as input floating */
00201   GPIO_InitStructure.GPIO_Pin = USARTy_RxPin;
00202   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
00203   GPIO_Init(USARTy_GPIO, &GPIO_InitStructure);
00204 }
00205
00206 /**
00207   * @brief  Reads key from board.
00208   * @param  None
00209   * @retval Return JOY_RIGHT, JOY_LEFT, JOY_SEL, JOY_UP, JOY_DOWN or JOY_NONE
00210   */
00211 JOYState_TypeDef ReadKey(void)
00212 {
00213 #ifndef USE_STM3210C_EVAL
00214   /* "right" key is pressed */
00215   if(!STM_EVAL_PBGetState(BUTTON_RIGHT))
00216   {
00217     while(STM_EVAL_PBGetState(BUTTON_RIGHT) == Bit_RESET);
00218     return JOY_RIGHT;
00219   }
00220   /* "left" key is pressed */
00221   if(!STM_EVAL_PBGetState(BUTTON_LEFT))
00222   {
00223     while(STM_EVAL_PBGetState(BUTTON_LEFT) == Bit_RESET);
00224     return JOY_LEFT;
00225   }
00226   /* "up" key is pressed */
00227   if(!STM_EVAL_PBGetState(BUTTON_UP))
00228   {
00229     while(STM_EVAL_PBGetState(BUTTON_UP) == Bit_RESET);
00230     return JOY_UP;
00231   }
00232   /* "down" key is pressed */
00233   if(!STM_EVAL_PBGetState(BUTTON_DOWN))
00234   {
00235     while(STM_EVAL_PBGetState(BUTTON_DOWN) == Bit_RESET);
00236     return JOY_DOWN;
00237   }
00238   /* "sel" key is pressed */
00239   if(!STM_EVAL_PBGetState(BUTTON_SEL))
00240   {
00241     while(STM_EVAL_PBGetState(BUTTON_SEL) == Bit_RESET);
00242     return JOY_SEL;
00243   }
00244   /* No key is pressed */
00245   else
00246   {
00247     return JOY_NONE;
00248   }
00249 #else
00250   return IOE_JoyStickGetState();
00251 #endif
00252 }
00253
00254 #ifdef  USE_FULL_ASSERT
00255
00256 /**
00257   * @brief  Reports the name of the source file and the source line number
00258   *         where the assert_param error has occurred.
00259   * @param  file: pointer to the source file name
00260   * @param  line: assert_param error line source number
00261   * @retval None
00262   */
00263 void assert_failed(uint8_t* file, uint32_t line)
00264 {
00265   /* User can add his own implementation to report the file name and line number,
00266      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00267
00268   /* Infinite loop */
00269   while (1)
00270   {
00271   }
00272 }
00273
00274 #endif
00275
00276 /**
00277   * @}
00278   */
00279
00280 /**
00281   * @}
00282   */
00283
00284 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/stm32f10x_conf.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    USART/IrDA/Transmit/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052 /* Exported types ------------------------------------------------------------*/
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Uncomment the line below to expanse the "assert_param" macro in the
00055    Standard Peripheral Library drivers code */
00056 /* #define USE_FULL_ASSERT    1 */
00057
00058 /* Exported macro ------------------------------------------------------------*/
00059 #ifdef  USE_FULL_ASSERT
00060 /**
00061   * @brief  The assert_param macro is used for function's parameters check.
00062   * @param  expr: If expr is false, it calls assert_failed function which reports
00063   *         the name of the source file and the source line number of the call
00064   *         that failed. If expr is true, it returns no value.
00065   * @retval None
00066   */
00067   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00068 /* Exported functions ------------------------------------------------------- */
00069   void assert_failed(uint8_t* file, uint32_t line);
00070 #else
00071   #define assert_param(expr) ((void)0)
00072 #endif /* USE_FULL_ASSERT */
00073
00074 #endif /* __STM32F10x_CONF_H */
00075
00076 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/stm32f10x_it.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    USART/IrDA/Transmit/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and peripherals
00009   *          interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026
00027 /** @addtogroup STM32F10x_StdPeriph_Examples
00028   * @{
00029   */
00030
00031 /** @addtogroup USART_IrDA_Transmit
00032   * @{
00033   */
00034
00035 /* Private typedef -----------------------------------------------------------*/
00036 /* Private define ------------------------------------------------------------*/
00037 /* Private macro -------------------------------------------------------------*/
00038 /* Private variables ---------------------------------------------------------*/
00039 /* Private function prototypes -----------------------------------------------*/
00040 /* Private functions ---------------------------------------------------------*/
00041
00042 /******************************************************************************/
00043 /*            Cortex-M3 Processor Exceptions Handlers                         */
00044 /******************************************************************************/
00045
00046 /**
00047   * @brief  This function handles NMI exception.
00048   * @param  None
00049   * @retval None
00050   */
00051 void NMI_Handler(void)
00052 {
00053 }
00054
00055 /**
00056   * @brief  This function handles Hard Fault exception.
00057   * @param  None
00058   * @retval None
00059   */
00060 void HardFault_Handler(void)
00061 {
00062   /* Go to infinite loop when Hard Fault exception occurs */
00063   while (1)
00064   {
00065   }
00066 }
00067
00068 /**
00069   * @brief  This function handles Memory Manage exception.
00070   * @param  None
00071   * @retval None
00072   */
00073 void MemManage_Handler(void)
00074 {
00075   /* Go to infinite loop when Memory Manage exception occurs */
00076   while (1)
00077   {
00078   }
00079 }
00080
00081 /**
00082   * @brief  This function handles Bus Fault exception.
00083   * @param  None
00084   * @retval None
00085   */
00086 void BusFault_Handler(void)
00087 {
00088   /* Go to infinite loop when Bus Fault exception occurs */
00089   while (1)
00090   {
00091   }
00092 }
00093
00094 /**
00095   * @brief  This function handles Usage Fault exception.
00096   * @param  None
00097   * @retval None
00098   */
00099 void UsageFault_Handler(void)
00100 {
00101   /* Go to infinite loop when Usage Fault exception occurs */
00102   while (1)
00103   {
00104   }
00105 }
00106
00107 /**
00108   * @brief  This function handles SVCall exception.
00109   * @param  None
00110   * @retval None
00111   */
00112 void SVC_Handler(void)
00113 {
00114 }
00115
00116 /**
00117   * @brief  This function handles Debug Monitor exception.
00118   * @param  None
00119   * @retval None
00120   */
00121 void DebugMon_Handler(void)
00122 {
00123 }
00124
00125 /**
00126   * @brief  This function handles PendSV_Handler exception.
00127   * @param  None
00128   * @retval None
00129   */
00130 void PendSV_Handler(void)
00131 {
00132 }
00133
00134 /**
00135   * @brief  This function handles SysTick Handler.
00136   * @param  None
00137   * @retval None
00138   */
00139 void SysTick_Handler(void)
00140 {
00141 }
00142
00143 /******************************************************************************/
00144 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00145 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00146 /*  available peripheral interrupt handler's name please refer to the startup */
00147 /*  file (startup_stm32f10x_xx.s).                                            */
00148 /******************************************************************************/
00149
00150 /**
00151   * @brief  This function handles PPP interrupt request.
00152   * @param  None
00153   * @retval None
00154   */
00155 /*void PPP_IRQHandler(void)
00156 {
00157 }*/
00158
00159 /**
00160   * @}
00161   */
00162
00163 /**
00164   * @}
00165   */
00166
00167 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/stm32f10x_it.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    USART/IrDA/Transmit/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022
00023 /* Define to prevent recursive inclusion -------------------------------------*/
00024 #ifndef __STM32F10x_IT_H
00025 #define __STM32F10x_IT_H
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32f10x.h"
00029
00030 /* Exported types ------------------------------------------------------------*/
00031 /* Exported constants --------------------------------------------------------*/
00032 /* Exported macro ------------------------------------------------------------*/
00033 /* Exported functions ------------------------------------------------------- */
00034
00035 void NMI_Handler(void);
00036 void HardFault_Handler(void);
00037 void MemManage_Handler(void);
00038 void BusFault_Handler(void);
00039 void UsageFault_Handler(void);
00040 void SVC_Handler(void);
00041 void DebugMon_Handler(void);
00042 void PendSV_Handler(void);
00043 void SysTick_Handler(void);
00044
00045 #endif /* __STM32F10x_IT_H */
00046
00047 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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STM32F10x_StdPeriph_Examples/USART/MultiProcessor/main.c

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00001 /**
00002   ******************************************************************************
00003   * @file    USART/MultiProcessor/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x.h"
00024 #include "platform_config.h"
00025
00026 /** @addtogroup STM32F10x_StdPeriph_Examples
00027   * @{
00028   */
00029
00030 /** @addtogroup USART_MultiProcessor
00031   * @{
00032   */
00033
00034 /* Private typedef -----------------------------------------------------------*/
00035 /* Private define ------------------------------------------------------------*/
00036 /* Private macro -------------------------------------------------------------*/
00037 /* Private variables ---------------------------------------------------------*/
00038 USART_InitTypeDef USART_InitStructure;
00039
00040 /* Private function prototypes -----------------------------------------------*/
00041 void RCC_Configuration(void);
00042 void GPIO_Configuration(void);
00043 void Delay(__IO uint32_t nCount);
00044
00045 /* Private functions ---------------------------------------------------------*/
00046 /**
00047   * @brief  Main program
00048   * @param  None
00049   * @retval None
00050   */
00051 int main(void)
00052 {
00053   /*!< At this stage the microcontroller clock setting is already configured,
00054        this is done through SystemInit() function which is called from startup
00055        file (startup_stm32f10x_xx.s) before to branch to application main.
00056        To reconfigure the default setting of SystemInit() function, refer to
00057        system_stm32f10x.c file
00058      */
00059
00060   /* System Clocks Configuration */
00061   RCC_Configuration();
00062
00063   /* Configure the GPIO ports */
00064   GPIO_Configuration();
00065
00066   /* Initialize Leds, Wakeup and Key Buttons mounted on STM3210X-EVAL board */
00067   STM_EVAL_LEDInit(LED1);
00068   STM_EVAL_LEDInit(LED2);
00069   STM_EVAL_LEDInit(LED3);
00070   STM_EVAL_LEDInit(LED4);
00071   STM_EVAL_PBInit(BUTTON_WAKEUP, BUTTON_MODE_EXTI);
00072   STM_EVAL_PBInit(BUTTON_KEY, BUTTON_MODE_EXTI);
00073
00074 /* USARTy and USARTz configuration -------------------------------------------*/
00075   /* USARTy and USARTz configured as follow:
00076         - BaudRate = 9600 baud
00077         - Word Length = 9 Bits
00078         - One Stop Bit
00079         - No parity
00080         - Hardware flow control disabled (RTS and CTS signals)
00081         - Receive and transmit enabled
00082   */
00083   USART_InitStructure.USART_BaudRate = 9600;
00084   USART_InitStructure.USART_WordLength = USART_WordLength_9b;
00085   USART_InitStructure.USART_StopBits = USART_StopBits_1;
00086   USART_InitStructure.USART_Parity = USART_Parity_No;
00087   USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
00088   USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
00089
00090   /* Configure USARTy */
00091   USART_Init(USARTy, &USART_InitStructure);
00092   /* Configure USARTz */
00093   USART_Init(USARTz, &USART_InitStructure);
00094
00095   /* Enable the USARTy */
00096   USART_Cmd(USARTy, ENABLE);
00097   /* Enable the USARTz */
00098   USART_Cmd(USARTz, ENABLE);
00099
00100   /* Set the USARTy Address */
00101   USART_SetAddress(USARTy, 0x1);
00102   /* Set the USARTz Address */
00103   USART_SetAddress(USARTz, 0x2);
00104
00105   /* Select the USARTz WakeUp Method */
00106   USART_WakeUpConfig(USARTz, USART_WakeUp_AddressMark);
00107
00108   while (1)
00109   {
00110     /* Send one byte from USARTy to USARTz */
00111     USART_SendData(USARTy, 0x33);
00112
00113     /* Wait while USART1 TXE = 0 */
00114     while(USART_GetFlagStatus(USARTz, USART_FLAG_TXE) == RESET)
00115     {
00116     }
00117
00118     if(USART_GetFlagStatus(USARTz, USART_FLAG_RXNE) != RESET)
00119     {
00120       if(USART_ReceiveData(USARTz) == 0x33)
00121       {
00122         STM_EVAL_LEDToggle(LED1);
00123         Delay(0x5FFFF);
00124         STM_EVAL_LEDToggle(LED2);
00125         Delay(0x5FFFF);
00126         STM_EVAL_LEDToggle(LED3);
00127         Delay(0x5FFFF);
00128         STM_EVAL_LEDToggle(LED4);
00129         Delay(0x5FFFF);
00130       }
00131     }
00132   }
00133 }
00134
00135 /**
00136   * @brief  Configures the different system clocks.
00137   * @param  None
00138   * @retval None
00139   */
00140 void RCC_Configuration(void)
00141 {
00142   /* Enable GPIO clock */
00143   RCC_APB2PeriphClockCmd(USARTy_GPIO_CLK | USARTz_GPIO_CLK | RCC_APB2Periph_AFIO, ENABLE);
00144
00145 #ifndef USE_STM3210C_EVAL
00146   /* Enable USARTy Clock */
00147   RCC_APB2PeriphClockCmd(USARTy_CLK, ENABLE);
00148 #else
00149   /* Enable USARTy Clock */
00150   RCC_APB1PeriphClockCmd(USARTy_CLK, ENABLE);
00151 #endif
00152   /* Enable USARTz Clock */
00153   RCC_APB1PeriphClockCmd(USARTz_CLK, ENABLE);
00154 }
00155
00156 /**
00157   * @brief  Configures the different GPIO ports.
00158   * @param  None
00159   * @retval None
00160   */
00161 void GPIO_Configuration(void)
00162 {
00163   GPIO_InitTypeDef GPIO_InitStructure;
00164
00165 #ifdef USE_STM3210C_EVAL
00166   /* Enable the USART3 Pins Software Remapping */
00167   GPIO_PinRemapConfig(GPIO_PartialRemap_USART3, ENABLE);
00168
00169   /* Enable the USART2 Pins Software Remapping */
00170   GPIO_PinRemapConfig(GPIO_Remap_USART2, ENABLE);
00171 #elif defined(USE_STM3210B_EVAL) || defined(USE_STM32100B_EVAL)
00172   /* Enable the USART2 Pins Software Remapping */
00173   GPIO_PinRemapConfig(GPIO_Remap_USART2, ENABLE);
00174 #endif
00175
00176   /* Configure USARTy Rx as input floating */
00177   GPIO_InitStructure.GPIO_Pin = USARTy_RxPin;
00178   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
00179   GPIO_Init(USARTy_GPIO, &GPIO_InitStructure);
00180
00181   /* Configure USARTz Rx as input floating */
00182   GPIO_InitStructure.GPIO_Pin = USARTz_RxPin;
00183   GPIO_Init(USARTz_GPIO, &GPIO_InitStructure);
00184
00185   /* Configure USARTy Tx as alternate function push-pull */
00186   GPIO_InitStructure.GPIO_Pin = USARTy_TxPin;
00187   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00188   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
00189   GPIO_Init(USARTy_GPIO, &GPIO_InitStructure);
00190
00191   /* Configure USARTz Tx as alternate function push-pull */
00192   GPIO_InitStructure.GPIO_Pin = USARTz_TxPin;
00193   GPIO_Init(USARTz_GPIO, &GPIO_InitStructure);
00194 }
00195
00196 /**
00197   * @brief  Inserts a delay time.
00198   * @param  nCount: specifies the delay time length.
00199   * @retval None
00200   */
00201 void Delay(__IO uint32_t nCount)
00202 {
00203   /* Decrement nCount value */
00204   for(; nCount != 0; nCount--);
00205 }
00206
00207 #ifdef  USE_FULL_ASSERT
00208
00209 /**
00210   * @brief  Reports the name of the source file and the source line number
00211   *         where the assert_param error has occurred.
00212   * @param  file: pointer to the source file name
00213   * @param  line: assert_param error line source number
00214   * @retval None
00215   */
00216 void assert_failed(uint8_t* file, uint32_t line)
00217 {
00218   /* User can add his own implementation to report the file name and line number,
00219      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00220
00221   /* Infinite loop */
00222   while (1)
00223   {
00224   }
00225 }
00226
00227 #endif
00228
00229 /**
00230   * @}
00231   */
00232
00233 /**
00234   * @}
00235   */
00236
00237 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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STM32F10x_StdPeriph_Examples/USART/MultiProcessor/stm32f10x_conf.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    USART/MultiProcessor/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052 /* Exported types ------------------------------------------------------------*/
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Uncomment the line below to expanse the "assert_param" macro in the
00055    Standard Peripheral Library drivers code */
00056 /* #define USE_FULL_ASSERT    1 */
00057
00058 /* Exported macro ------------------------------------------------------------*/
00059 #ifdef  USE_FULL_ASSERT
00060 /**
00061   * @brief  The assert_param macro is used for function's parameters check.
00062   * @param  expr: If expr is false, it calls assert_failed function which reports
00063   *         the name of the source file and the source line number of the call
00064   *         that failed. If expr is true, it returns no value.
00065   * @retval None
00066   */
00067   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00068 /* Exported functions ------------------------------------------------------- */
00069   void assert_failed(uint8_t* file, uint32_t line);
00070 #else
00071   #define assert_param(expr) ((void)0)
00072 #endif /* USE_FULL_ASSERT */
00073
00074 #endif /* __STM32F10x_CONF_H */
00075
00076 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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STM32F10x_StdPeriph_Examples/USART/MultiProcessor/stm32f10x_it.c

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00001 /**
00002   ******************************************************************************
00003   * @file    USART/MultiProcessor/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and peripherals
00009   *          interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026 #include "platform_config.h"
00027
00028 /** @addtogroup STM32F10x_StdPeriph_Examples
00029   * @{
00030   */
00031
00032 /** @addtogroup USART_MultiProcessor
00033   * @{
00034   */
00035
00036 /* Private typedef -----------------------------------------------------------*/
00037 /* Private define ------------------------------------------------------------*/
00038 /* Private macro -------------------------------------------------------------*/
00039 /* Private variables ---------------------------------------------------------*/
00040 /* Private function prototypes -----------------------------------------------*/
00041 /* Private functions ---------------------------------------------------------*/
00042
00043 /******************************************************************************/
00044 /*            Cortex-M3 Processor Exceptions Handlers                         */
00045 /******************************************************************************/
00046
00047 /**
00048   * @brief  This function handles NMI exception.
00049   * @param  None
00050   * @retval None
00051   */
00052 void NMI_Handler(void)
00053 {
00054 }
00055
00056 /**
00057   * @brief  This function handles Hard Fault exception.
00058   * @param  None
00059   * @retval None
00060   */
00061 void HardFault_Handler(void)
00062 {
00063   /* Go to infinite loop when Hard Fault exception occurs */
00064   while (1)
00065   {
00066   }
00067 }
00068
00069 /**
00070   * @brief  This function handles Memory Manage exception.
00071   * @param  None
00072   * @retval None
00073   */
00074 void MemManage_Handler(void)
00075 {
00076   /* Go to infinite loop when Memory Manage exception occurs */
00077   while (1)
00078   {
00079   }
00080 }
00081
00082 /**
00083   * @brief  This function handles Bus Fault exception.
00084   * @param  None
00085   * @retval None
00086   */
00087 void BusFault_Handler(void)
00088 {
00089   /* Go to infinite loop when Bus Fault exception occurs */
00090   while (1)
00091   {
00092   }
00093 }
00094
00095 /**
00096   * @brief  This function handles Usage Fault exception.
00097   * @param  None
00098   * @retval None
00099   */
00100 void UsageFault_Handler(void)
00101 {
00102   /* Go to infinite loop when Usage Fault exception occurs */
00103   while (1)
00104   {
00105   }
00106 }
00107
00108 /**
00109   * @brief  This function handles SVCall exception.
00110   * @param  None
00111   * @retval None
00112   */
00113 void SVC_Handler(void)
00114 {
00115 }
00116
00117 /**
00118   * @brief  This function handles Debug Monitor exception.
00119   * @param  None
00120   * @retval None
00121   */
00122 void DebugMon_Handler(void)
00123 {
00124 }
00125
00126 /**
00127   * @brief  This function handles PendSV_Handler exception.
00128   * @param  None
00129   * @retval None
00130   */
00131 void PendSV_Handler(void)
00132 {
00133 }
00134
00135 /**
00136   * @brief  This function handles SysTick Handler.
00137   * @param  None
00138   * @retval None
00139   */
00140 void SysTick_Handler(void)
00141 {
00142 }
00143
00144 /******************************************************************************/
00145 /*            STM32F10x Peripherals Interrupt Handlers                        */
00146 /******************************************************************************/
00147
00148 /**
00149   * @brief  This function handles External interrupt Line 0 request.
00150   * @param  None
00151   * @retval None
00152   */
00153 void EXTI0_IRQHandler(void)
00154 {
00155   /* Send the address mark (0x102) to wakeup USARTz */
00156   USART_SendData(USARTy, 0x102);
00157
00158   /* Wait while USARTy TXE = 0 */
00159   while(USART_GetFlagStatus(USARTy, USART_FLAG_TXE) == RESET)
00160   {
00161   }
00162
00163   /* Clear EXTI Line 0 Pending Bit */
00164   EXTI_ClearITPendingBit(EXTI_Line0);
00165 }
00166
00167 /**
00168   * @brief  This function handles External lines 9 to 5 interrupt request.
00169   * @param  None
00170   * @retval None
00171   */
00172 void EXTI9_5_IRQHandler(void)
00173 {
00174   if(EXTI_GetITStatus(KEY_BUTTON_EXTI_LINE) != RESET)
00175   {
00176     /* Flush DR register and clear the USARTz RXNE flag */
00177     USART_ReceiveData(USARTz);
00178
00179     /* Enable the USARTz mute mode*/
00180     USART_ReceiverWakeUpCmd(USARTz, ENABLE);
00181
00182     /* Clear Key Button EXTI Line Pending Bit */
00183     EXTI_ClearITPendingBit(KEY_BUTTON_EXTI_LINE);
00184   }
00185 }
00186
00187 /******************************************************************************/
00188 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00189 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00190 /*  available peripheral interrupt handler's name please refer to the startup */
00191 /*  file (startup_stm32f10x_xx.s).                                            */
00192 /******************************************************************************/
00193
00194 /**
00195   * @brief  This function handles PPP interrupt request.
00196   * @param  None
00197   * @retval None
00198   */
00199 /*void PPP_IRQHandler(void)
00200 {
00201 }*/
00202
00203 /**
00204   * @}
00205   */
00206
00207 /**
00208   * @}
00209   */
00210
00211 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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STM32F10x_StdPeriph_Examples/USART/MultiProcessor/stm32f10x_it.h

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00001 /**
00002   ******************************************************************************
00003   * @file    USART/MultiProcessor/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043 void EXTI0_IRQHandler(void);
00044 void EXTI9_5_IRQHandler(void);
00045
00046 #endif /* __STM32F10x_IT_H */
00047
00048 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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STM32F10x_StdPeriph_Examples/USART/Polling/main.c

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00001 /**
00002   ******************************************************************************
00003   * @file    USART/Polling/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x.h"
00024 #include "platform_config.h"
00025
00026 /** @addtogroup STM32F10x_StdPeriph_Examples
00027   * @{
00028   */
00029
00030 /** @addtogroup USART_Polling
00031   * @{
00032   */
00033
00034 /* Private typedef -----------------------------------------------------------*/
00035 typedef enum { FAILED = 0, PASSED = !FAILED} TestStatus;
00036
00037 /* Private define ------------------------------------------------------------*/
00038 #define TxBufferSize   (countof(TxBuffer))
00039
00040 /* Private macro -------------------------------------------------------------*/
00041 #define countof(a)   (sizeof(a) / sizeof(*(a)))
00042
00043 /* Private variables ---------------------------------------------------------*/
00044 USART_InitTypeDef USART_InitStructure;
00045 uint8_t TxBuffer[] = "Buffer Send from USARTy to USARTz using Flags";
00046 uint8_t RxBuffer[TxBufferSize];
00047 __IO uint8_t TxCounter = 0, RxCounter = 0;
00048 volatile TestStatus TransferStatus = FAILED;
00049
00050 /* Private function prototypes -----------------------------------------------*/
00051 void RCC_Configuration(void);
00052 void GPIO_Configuration(void);
00053 TestStatus Buffercmp(uint8_t* pBuffer1, uint8_t* pBuffer2, uint16_t BufferLength);
00054 __IO uint8_t index = 0;
00055
00056 /* Private functions ---------------------------------------------------------*/
00057
00058 /**
00059   * @brief  Main program
00060   * @param  None
00061   * @retval None
00062   */
00063 int main(void)
00064 {
00065   /*!< At this stage the microcontroller clock setting is already configured,
00066        this is done through SystemInit() function which is called from startup
00067        file (startup_stm32f10x_xx.s) before to branch to application main.
00068        To reconfigure the default setting of SystemInit() function, refer to
00069        system_stm32f10x.c file
00070      */
00071
00072   /* System Clocks Configuration */
00073   RCC_Configuration();
00074
00075   /* Configure the GPIO ports */
00076   GPIO_Configuration();
00077
00078 /* USARTy and USARTz configuration ------------------------------------------------------*/
00079   /* USARTy and USARTz configured as follow:
00080         - BaudRate = 230400 baud
00081         - Word Length = 8 Bits
00082         - One Stop Bit
00083         - Even parity
00084         - Hardware flow control disabled (RTS and CTS signals)
00085         - Receive and transmit enabled
00086   */
00087   USART_InitStructure.USART_BaudRate = 230400;
00088   USART_InitStructure.USART_WordLength = USART_WordLength_8b;
00089   USART_InitStructure.USART_StopBits = USART_StopBits_1;
00090   USART_InitStructure.USART_Parity = USART_Parity_Even;
00091   USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
00092   USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
00093
00094   /* Configure USARTy */
00095   USART_Init(USARTy, &USART_InitStructure);
00096   /* Configure USARTz */
00097   USART_Init(USARTz, &USART_InitStructure);
00098
00099   /* Enable the USARTy */
00100   USART_Cmd(USARTy, ENABLE);
00101
00102   /* Enable the USARTz */
00103   USART_Cmd(USARTz, ENABLE);
00104
00105   while(TxCounter < TxBufferSize)
00106   {
00107     /* Send one byte from USARTy to USARTz */
00108     USART_SendData(USARTy, TxBuffer[TxCounter++]);
00109
00110     /* Loop until USARTy DR register is empty */
00111     while(USART_GetFlagStatus(USARTy, USART_FLAG_TXE) == RESET)
00112     {
00113     }
00114
00115     /* Loop until the USARTz Receive Data Register is not empty */
00116     while(USART_GetFlagStatus(USARTz, USART_FLAG_RXNE) == RESET)
00117     {
00118     }
00119
00120     /* Store the received byte in RxBuffer */
00121     RxBuffer[RxCounter++] = (USART_ReceiveData(USARTz) & 0x7F);
00122
00123   }
00124   /* Check the received data with the send ones */
00125   TransferStatus = Buffercmp(TxBuffer, RxBuffer, TxBufferSize);
00126   /* TransferStatus = PASSED, if the data transmitted from USARTy and
00127      received by USARTz are the same */
00128   /* TransferStatus = FAILED, if the data transmitted from USARTy and
00129      received by USARTz are different */
00130
00131   while (1)
00132   {
00133   }
00134 }
00135
00136 /**
00137   * @brief  Configures the different system clocks.
00138   * @param  None
00139   * @retval None
00140   */
00141 void RCC_Configuration(void)
00142 {
00143   /* Enable GPIO clock */
00144   RCC_APB2PeriphClockCmd(USARTy_GPIO_CLK | USARTz_GPIO_CLK | RCC_APB2Periph_AFIO, ENABLE);
00145
00146 #ifndef USE_STM3210C_EVAL
00147   /* Enable USARTy Clock */
00148   RCC_APB2PeriphClockCmd(USARTy_CLK, ENABLE);
00149 #else
00150   /* Enable USARTy Clock */
00151   RCC_APB1PeriphClockCmd(USARTy_CLK, ENABLE);
00152 #endif
00153   /* Enable USARTz Clock */
00154   RCC_APB1PeriphClockCmd(USARTz_CLK, ENABLE);
00155 }
00156
00157 /**
00158   * @brief  Configures the different GPIO ports.
00159   * @param  None
00160   * @retval None
00161   */
00162 void GPIO_Configuration(void)
00163 {
00164   GPIO_InitTypeDef GPIO_InitStructure;
00165
00166 #ifdef USE_STM3210C_EVAL
00167   /* Enable the USART3 Pins Software Remapping */
00168   GPIO_PinRemapConfig(GPIO_PartialRemap_USART3, ENABLE);
00169
00170   /* Enable the USART2 Pins Software Remapping */
00171   GPIO_PinRemapConfig(GPIO_Remap_USART2, ENABLE);
00172 #elif defined(USE_STM3210B_EVAL) || defined(USE_STM32100B_EVAL)
00173   /* Enable the USART2 Pins Software Remapping */
00174   GPIO_PinRemapConfig(GPIO_Remap_USART2, ENABLE);
00175 #endif
00176
00177   /* Configure USARTy Rx as input floating */
00178   GPIO_InitStructure.GPIO_Pin = USARTy_RxPin;
00179   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
00180   GPIO_Init(USARTy_GPIO, &GPIO_InitStructure);
00181
00182   /* Configure USARTz Rx as input floating */
00183   GPIO_InitStructure.GPIO_Pin = USARTz_RxPin;
00184   GPIO_Init(USARTz_GPIO, &GPIO_InitStructure);
00185
00186   /* Configure USARTy Tx as alternate function push-pull */
00187   GPIO_InitStructure.GPIO_Pin = USARTy_TxPin;
00188   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00189   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
00190   GPIO_Init(USARTy_GPIO, &GPIO_InitStructure);
00191
00192   /* Configure USARTz Tx as alternate function push-pull */
00193   GPIO_InitStructure.GPIO_Pin = USARTz_TxPin;
00194   GPIO_Init(USARTz_GPIO, &GPIO_InitStructure);
00195 }
00196
00197 /**
00198   * @brief  Compares two buffers.
00199   * @param  pBuffer1, pBuffer2: buffers to be compared.
00200   * @param  BufferLength: buffer's length
00201   * @retval PASSED: pBuffer1 identical to pBuffer2
00202   *         FAILED: pBuffer1 differs from pBuffer2
00203   */
00204 TestStatus Buffercmp(uint8_t* pBuffer1, uint8_t* pBuffer2, uint16_t BufferLength)
00205 {
00206   while(BufferLength--)
00207   {
00208     if(*pBuffer1 != *pBuffer2)
00209     {
00210       return FAILED;
00211     }
00212
00213     pBuffer1++;
00214     pBuffer2++;
00215   }
00216
00217   return PASSED;
00218 }
00219
00220 #ifdef  USE_FULL_ASSERT
00221
00222 /**
00223   * @brief  Reports the name of the source file and the source line number
00224   *         where the assert_param error has occurred.
00225   * @param  file: pointer to the source file name
00226   * @param  line: assert_param error line source number
00227   * @retval None
00228   */
00229 void assert_failed(uint8_t* file, uint32_t line)
00230 {
00231   /* User can add his own implementation to report the file name and line number,
00232      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00233
00234   /* Infinite loop */
00235   while (1)
00236   {
00237   }
00238 }
00239
00240 #endif
00241
00242 /**
00243   * @}
00244   */
00245
00246 /**
00247   * @}
00248   */
00249
00250 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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STM32F10x_StdPeriph_Examples/USART/Polling/stm32f10x_conf.h

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00001 /**
00002   ******************************************************************************
00003   * @file    USART/Polling/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052 /* Exported types ------------------------------------------------------------*/
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Uncomment the line below to expanse the "assert_param" macro in the
00055    Standard Peripheral Library drivers code */
00056 /* #define USE_FULL_ASSERT    1 */
00057
00058 /* Exported macro ------------------------------------------------------------*/
00059 #ifdef  USE_FULL_ASSERT
00060 /**
00061   * @brief  The assert_param macro is used for function's parameters check.
00062   * @param  expr: If expr is false, it calls assert_failed function which reports
00063   *         the name of the source file and the source line number of the call
00064   *         that failed. If expr is true, it returns no value.
00065   * @retval None
00066   */
00067   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00068 /* Exported functions ------------------------------------------------------- */
00069   void assert_failed(uint8_t* file, uint32_t line);
00070 #else
00071   #define assert_param(expr) ((void)0)
00072 #endif /* USE_FULL_ASSERT */
00073
00074 #endif /* __STM32F10x_CONF_H */
00075
00076 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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STM32F10x_StdPeriph_Examples/USART/Polling/stm32f10x_it.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    USART/Polling/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and peripherals
00009   *          interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026
00027 /** @addtogroup STM32F10x_StdPeriph_Examples
00028   * @{
00029   */
00030
00031 /** @addtogroup USART_Polling
00032   * @{
00033   */
00034
00035 /* Private typedef -----------------------------------------------------------*/
00036 /* Private define ------------------------------------------------------------*/
00037 /* Private macro -------------------------------------------------------------*/
00038 /* Private variables ---------------------------------------------------------*/
00039 /* Private function prototypes -----------------------------------------------*/
00040 /* Private functions ---------------------------------------------------------*/
00041
00042 /******************************************************************************/
00043 /*            Cortex-M3 Processor Exceptions Handlers                         */
00044 /******************************************************************************/
00045
00046 /**
00047   * @brief  This function handles NMI exception.
00048   * @param  None
00049   * @retval None
00050   */
00051 void NMI_Handler(void)
00052 {
00053 }
00054
00055 /**
00056   * @brief  This function handles Hard Fault exception.
00057   * @param  None
00058   * @retval None
00059   */
00060 void HardFault_Handler(void)
00061 {
00062   /* Go to infinite loop when Hard Fault exception occurs */
00063   while (1)
00064   {
00065   }
00066 }
00067
00068 /**
00069   * @brief  This function handles Memory Manage exception.
00070   * @param  None
00071   * @retval None
00072   */
00073 void MemManage_Handler(void)
00074 {
00075   /* Go to infinite loop when Memory Manage exception occurs */
00076   while (1)
00077   {
00078   }
00079 }
00080
00081 /**
00082   * @brief  This function handles Bus Fault exception.
00083   * @param  None
00084   * @retval None
00085   */
00086 void BusFault_Handler(void)
00087 {
00088   /* Go to infinite loop when Bus Fault exception occurs */
00089   while (1)
00090   {
00091   }
00092 }
00093
00094 /**
00095   * @brief  This function handles Usage Fault exception.
00096   * @param  None
00097   * @retval None
00098   */
00099 void UsageFault_Handler(void)
00100 {
00101   /* Go to infinite loop when Usage Fault exception occurs */
00102   while (1)
00103   {
00104   }
00105 }
00106
00107 /**
00108   * @brief  This function handles SVCall exception.
00109   * @param  None
00110   * @retval None
00111   */
00112 void SVC_Handler(void)
00113 {
00114 }
00115
00116 /**
00117   * @brief  This function handles Debug Monitor exception.
00118   * @param  None
00119   * @retval None
00120   */
00121 void DebugMon_Handler(void)
00122 {
00123 }
00124
00125 /**
00126   * @brief  This function handles PendSV_Handler exception.
00127   * @param  None
00128   * @retval None
00129   */
00130 void PendSV_Handler(void)
00131 {
00132 }
00133
00134 /**
00135   * @brief  This function handles SysTick Handler.
00136   * @param  None
00137   * @retval None
00138   */
00139 void SysTick_Handler(void)
00140 {
00141 }
00142
00143 /******************************************************************************/
00144 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00145 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00146 /*  available peripheral interrupt handler's name please refer to the startup */
00147 /*  file (startup_stm32f10x_xx.s).                                            */
00148 /******************************************************************************/
00149
00150 /**
00151   * @brief  This function handles PPP interrupt request.
00152   * @param  None
00153   * @retval None
00154   */
00155 /*void PPP_IRQHandler(void)
00156 {
00157 }*/
00158
00159 /**
00160   * @}
00161   */
00162
00163 /**
00164   * @}
00165   */
00166
00167 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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STM32F10x_StdPeriph_Examples/USART/Polling/stm32f10x_it.h

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00001 /**
00002   ******************************************************************************
00003   * @file    USART/Polling/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043
00044 #endif /* __STM32F10x_IT_H */
00045
00046 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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STM32F10x_StdPeriph_Examples/USART/Printf/main.c

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00001 /**
00002   ******************************************************************************
00003   * @file    USART/Printf/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x.h"
00024 #include "stm32_eval.h"
00025 #include <stdio.h>
00026
00027 /** @addtogroup STM32F10x_StdPeriph_Examples
00028   * @{
00029   */
00030
00031 /** @addtogroup USART_Printf
00032   * @{
00033   */
00034
00035 /* Private typedef -----------------------------------------------------------*/
00036 /* Private define ------------------------------------------------------------*/
00037 /* Private macro -------------------------------------------------------------*/
00038 /* Private variables ---------------------------------------------------------*/
00039 USART_InitTypeDef USART_InitStructure;
00040
00041 /* Private function prototypes -----------------------------------------------*/
00042
00043 #ifdef __GNUC__
00044   /* With GCC/RAISONANCE, small printf (option LD Linker->Libraries->Small printf
00045      set to 'Yes') calls __io_putchar() */
00046   #define PUTCHAR_PROTOTYPE int __io_putchar(int ch)
00047 #else
00048   #define PUTCHAR_PROTOTYPE int fputc(int ch, FILE *f)
00049 #endif /* __GNUC__ */
00050
00051 /* Private functions ---------------------------------------------------------*/
00052
00053 /**
00054   * @brief  Main program
00055   * @param  None
00056   * @retval None
00057   */
00058 int main(void)
00059 {
00060   /*!< At this stage the microcontroller clock setting is already configured,
00061        this is done through SystemInit() function which is called from startup
00062        file (startup_stm32f10x_xx.s) before to branch to application main.
00063        To reconfigure the default setting of SystemInit() function, refer to
00064        system_stm32f10x.c file
00065      */
00066
00067   /* USARTx configured as follow:
00068         - BaudRate = 115200 baud
00069         - Word Length = 8 Bits
00070         - One Stop Bit
00071         - No parity
00072         - Hardware flow control disabled (RTS and CTS signals)
00073         - Receive and transmit enabled
00074   */
00075   USART_InitStructure.USART_BaudRate = 115200;
00076   USART_InitStructure.USART_WordLength = USART_WordLength_8b;
00077   USART_InitStructure.USART_StopBits = USART_StopBits_1;
00078   USART_InitStructure.USART_Parity = USART_Parity_No;
00079   USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
00080   USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
00081
00082   STM_EVAL_COMInit(COM1, &USART_InitStructure);
00083
00084   /* Output a message on Hyperterminal using printf function */
00085   printf("\n\rUSART Printf Example: retarget the C library printf function to the USART\n\r");
00086
00087   while (1)
00088   {
00089   }
00090 }
00091
00092 /**
00093   * @brief  Retargets the C library printf function to the USART.
00094   * @param  None
00095   * @retval None
00096   */
00097 PUTCHAR_PROTOTYPE
00098 {
00099   /* Place your implementation of fputc here */
00100   /* e.g. write a character to the USART */
00101   USART_SendData(EVAL_COM1, (uint8_t) ch);
00102
00103   /* Loop until the end of transmission */
00104   while (USART_GetFlagStatus(EVAL_COM1, USART_FLAG_TC) == RESET)
00105   {}
00106
00107   return ch;
00108 }
00109
00110 #ifdef  USE_FULL_ASSERT
00111
00112 /**
00113   * @brief  Reports the name of the source file and the source line number
00114   *         where the assert_param error has occurred.
00115   * @param  file: pointer to the source file name
00116   * @param  line: assert_param error line source number
00117   * @retval None
00118   */
00119 void assert_failed(uint8_t* file, uint32_t line)
00120 {
00121   /* User can add his own implementation to report the file name and line number,
00122      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00123
00124   /* Infinite loop */
00125   while (1)
00126   {
00127   }
00128 }
00129
00130 #endif
00131
00132 /**
00133   * @}
00134   */
00135
00136 /**
00137   * @}
00138   */
00139
00140 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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STM32F10x_StdPeriph_Examples/USART/Printf/stm32f10x_conf.h

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00001 /**
00002   ******************************************************************************
00003   * @file USART/Printf/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052 /* Exported types ------------------------------------------------------------*/
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Uncomment the line below to expanse the "assert_param" macro in the
00055    Standard Peripheral Library drivers code */
00056 /* #define USE_FULL_ASSERT    1 */
00057
00058 /* Exported macro ------------------------------------------------------------*/
00059 #ifdef  USE_FULL_ASSERT
00060 /**
00061   * @brief  The assert_param macro is used for function's parameters check.
00062   * @param  expr: If expr is false, it calls assert_failed function which reports
00063   *         the name of the source file and the source line number of the call
00064   *         that failed. If expr is true, it returns no value.
00065   * @retval None
00066   */
00067   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00068 /* Exported functions ------------------------------------------------------- */
00069   void assert_failed(uint8_t* file, uint32_t line);
00070 #else
00071   #define assert_param(expr) ((void)0)
00072 #endif /* USE_FULL_ASSERT */
00073
00074 #endif /* __STM32F10x_CONF_H */
00075
00076 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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STM32F10x_StdPeriph_Examples/USART/Printf/stm32f10x_it.c

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00001 /**
00002   ******************************************************************************
00003   * @file    USART/Printf/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and peripherals
00009   *          interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026
00027 /** @addtogroup STM32F10x_StdPeriph_Examples
00028   * @{
00029   */
00030
00031 /** @addtogroup USART_Printf
00032   * @{
00033   */
00034
00035 /* Private typedef -----------------------------------------------------------*/
00036 /* Private define ------------------------------------------------------------*/
00037 /* Private macro -------------------------------------------------------------*/
00038 /* Private variables ---------------------------------------------------------*/
00039 /* Private function prototypes -----------------------------------------------*/
00040 /* Private functions ---------------------------------------------------------*/
00041
00042 /******************************************************************************/
00043 /*            Cortex-M3 Processor Exceptions Handlers                         */
00044 /******************************************************************************/
00045
00046 /**
00047   * @brief  This function handles NMI exception.
00048   * @param  None
00049   * @retval None
00050   */
00051 void NMI_Handler(void)
00052 {
00053 }
00054
00055 /**
00056   * @brief  This function handles Hard Fault exception.
00057   * @param  None
00058   * @retval None
00059   */
00060 void HardFault_Handler(void)
00061 {
00062   /* Go to infinite loop when Hard Fault exception occurs */
00063   while (1)
00064   {
00065   }
00066 }
00067
00068 /**
00069   * @brief  This function handles Memory Manage exception.
00070   * @param  None
00071   * @retval None
00072   */
00073 void MemManage_Handler(void)
00074 {
00075   /* Go to infinite loop when Memory Manage exception occurs */
00076   while (1)
00077   {
00078   }
00079 }
00080
00081 /**
00082   * @brief  This function handles Bus Fault exception.
00083   * @param  None
00084   * @retval None
00085   */
00086 void BusFault_Handler(void)
00087 {
00088   /* Go to infinite loop when Bus Fault exception occurs */
00089   while (1)
00090   {
00091   }
00092 }
00093
00094 /**
00095   * @brief  This function handles Usage Fault exception.
00096   * @param  None
00097   * @retval None
00098   */
00099 void UsageFault_Handler(void)
00100 {
00101   /* Go to infinite loop when Usage Fault exception occurs */
00102   while (1)
00103   {
00104   }
00105 }
00106
00107 /**
00108   * @brief  This function handles SVCall exception.
00109   * @param  None
00110   * @retval None
00111   */
00112 void SVC_Handler(void)
00113 {
00114 }
00115
00116 /**
00117   * @brief  This function handles Debug Monitor exception.
00118   * @param  None
00119   * @retval None
00120   */
00121 void DebugMon_Handler(void)
00122 {
00123 }
00124
00125 /**
00126   * @brief  This function handles PendSV_Handler exception.
00127   * @param  None
00128   * @retval None
00129   */
00130 void PendSV_Handler(void)
00131 {
00132 }
00133
00134 /**
00135   * @brief  This function handles SysTick Handler.
00136   * @param  None
00137   * @retval None
00138   */
00139 void SysTick_Handler(void)
00140 {
00141 }
00142
00143 /******************************************************************************/
00144 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00145 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00146 /*  available peripheral interrupt handler's name please refer to the startup */
00147 /*  file (startup_stm32f10x_xx.s).                                            */
00148 /******************************************************************************/
00149
00150 /**
00151   * @brief  This function handles PPP interrupt request.
00152   * @param  None
00153   * @retval None
00154   */
00155 /*void PPP_IRQHandler(void)
00156 {
00157 }*/
00158
00159 /**
00160   * @}
00161   */
00162
00163 /**
00164   * @}
00165   */
00166
00167 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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STM32F10x_StdPeriph_Examples/USART/Printf/stm32f10x_it.h

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00001 /**
00002   ******************************************************************************
00003   * @file    USART/Printf/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043
00044 #endif /* __STM32F10x_IT_H */
00045
00046 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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STM32F10x_StdPeriph_Examples/USART/Smartcard/main.c

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00001 /**
00002   ******************************************************************************
00003   * @file    USART/Smartcard/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x.h"
00024 #include "platform_config.h"
00025
00026 /* Private define ------------------------------------------------------------*/
00027 #define T0_PROTOCOL           0x00 /* T0 PROTOCOL */
00028 #define SETUP_LENGHT          20
00029 #define HIST_LENGHT           20
00030 #define SC_Receive_Timeout    0x4000 /* direction to reader */
00031
00032 /** @addtogroup STM32F10x_StdPeriph_Examples
00033   * @{
00034   */
00035
00036 /** @addtogroup USART_Smartcard
00037   * @{
00038   */
00039
00040 /* Private typedef -----------------------------------------------------------*/
00041 /* ATR STRUCTURE - ANSWER TO RESET */
00042 typedef  struct
00043 {
00044   uint8_t TS; /* Bit Convention */
00045   uint8_t T0; /* High Nibble = N. of setup byte; low nibble = N. of historical byte */
00046   uint8_t T[SETUP_LENGHT]; /* Setup array */
00047   uint8_t H[HIST_LENGHT]; /* Historical array */
00048   uint8_t Tlenght; /* Setup array dimension */
00049   uint8_t Hlenght; /* Historical array dimension */
00050 } SC_ATR;
00051
00052 typedef enum {FAILED = 0, PASSED = !FAILED} TestStatus;
00053
00054 /* Private macro -------------------------------------------------------------*/
00055 /* Private variables ---------------------------------------------------------*/
00056 USART_InitTypeDef USART_InitStructure;
00057 USART_ClockInitTypeDef USART_ClockInitStructure;
00058 SC_ATR  SC_A2R;
00059 __IO uint32_t index = 0, Counter = 0;
00060 volatile TestStatus ATRDecodeStatus = FAILED;
00061 __IO uint32_t CardInserted = 0, CardProtocol = 1;
00062
00063 __IO uint8_t DST_Buffer[50]= {
00064                      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
00065                      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
00066                      0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
00067
00068 /* Private function prototypes -----------------------------------------------*/
00069 /* Private functions ---------------------------------------------------------*/
00070 void RCC_Configuration(void);
00071 void GPIO_Configuration(void);
00072 void EXTI_Configuration(void);
00073 void NVIC_Configuration(void);
00074 uint8_t SC_decode_Answer2reset(__IO uint8_t *card);
00075
00076 /**
00077   * @brief  Main program
00078   * @param  None
00079   * @retval None
00080   */
00081 int main(void)
00082 {
00083   /*!< At this stage the microcontroller clock setting is already configured,
00084        this is done through SystemInit() function which is called from startup
00085        file (startup_stm32f10x_xx.s) before to branch to application main.
00086        To reconfigure the default setting of SystemInit() function, refer to
00087        system_stm32f10x.c file
00088      */
00089
00090   /* System Clocks Configuration */
00091   RCC_Configuration();
00092
00093   /* NVIC configuration */
00094   NVIC_Configuration();
00095
00096   /* Configure the GPIO ports */
00097   GPIO_Configuration();
00098
00099   /* Configure the EXTI Controller */
00100   EXTI_Configuration();
00101
00102
00103 /* SC_USART configuration ----------------------------------------------------*/
00104   /* SC_USART configured as follow:
00105         - Word Length = 9 Bits
00106         - 0.5 Stop Bit
00107         - Even parity
00108         - BaudRate = 12096 baud
00109         - Hardware flow control disabled (RTS and CTS signals)
00110         - Tx and Rx enabled
00111         - USART Clock enabled
00112         - USART CPOL Low
00113         - USART CPHA on first edge
00114         - USART Last Bit Clock Enabled
00115   */
00116
00117   /* SC_USART Clock set to 4.5MHz (PCLK1 = 36 MHZ / 8) */
00118   USART_SetPrescaler(SC_USART, 0x04);
00119   /* SC_USART Guard Time set to 2 Bit */
00120   USART_SetGuardTime(SC_USART, 0x2);
00121
00122   USART_ClockInitStructure.USART_Clock = USART_Clock_Enable;
00123   USART_ClockInitStructure.USART_CPOL = USART_CPOL_Low;
00124   USART_ClockInitStructure.USART_CPHA = USART_CPHA_1Edge;
00125   USART_ClockInitStructure.USART_LastBit = USART_LastBit_Enable;
00126   USART_ClockInit(SC_USART, &USART_ClockInitStructure);
00127
00128   USART_InitStructure.USART_BaudRate = 12096;
00129   USART_InitStructure.USART_WordLength = USART_WordLength_9b;
00130   USART_InitStructure.USART_StopBits = USART_StopBits_1_5;
00131   USART_InitStructure.USART_Parity = USART_Parity_Even;
00132   USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
00133   USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
00134   USART_Init(SC_USART, &USART_InitStructure);
00135
00136   /* Enable the SC_USART Parity Error Interrupt */
00137   USART_ITConfig(SC_USART, USART_IT_PE, ENABLE);
00138
00139   /* Enable SC_USART */
00140   USART_Cmd(SC_USART, ENABLE);
00141
00142   /* Enable the NACK Transmission */
00143   USART_SmartCardNACKCmd(SC_USART, ENABLE);
00144
00145   /* Enable the Smartcard Interface */
00146   USART_SmartCardCmd(SC_USART, ENABLE);
00147
00148   /* Loop while no Smartcard is detected */
00149   while(CardInserted == 0)
00150   {
00151   }
00152
00153   /* Read Smartcard ATR response */
00154   for(index = 0; index < 40; index++, Counter = 0)
00155   {
00156     while((USART_GetFlagStatus(SC_USART, USART_FLAG_RXNE) == RESET) && (Counter != SC_Receive_Timeout))
00157     {
00158       Counter++;
00159     }
00160
00161     if(Counter != SC_Receive_Timeout)
00162     {
00163       DST_Buffer[index] = USART_ReceiveData(SC_USART);
00164     }
00165   }
00166
00167   /* Decode ATR */
00168   CardProtocol = SC_decode_Answer2reset(DST_Buffer);
00169
00170   /* Test if the inserted card is ISO7816-3 T=0 compatible */
00171   if(CardProtocol == 0)
00172   {
00173     /* Inserted card is ISO7816-3 T=0 compatible */
00174     ATRDecodeStatus = PASSED;
00175   }
00176   else
00177   {
00178     /* Inserted Smartcard is not ISO7816-3 T=0 compatible */
00179     ATRDecodeStatus = FAILED;
00180   }
00181
00182   while (1)
00183   {
00184   }
00185 }
00186
00187 /**
00188   * @brief  Configures the different system clocks.
00189   * @param  None
00190   * @retval None
00191   */
00192 void RCC_Configuration(void)
00193 {
00194   /* Enable GPIO_3_5V, SC_USART_GPIO_CLK, GPIO_CMDVCC, GPIO_RESET, GPIO_OFF and
00195      AFIO clocks */
00196   RCC_APB2PeriphClockCmd(RCC_APB2Periph_3_5V | SC_USART_GPIO_CLK | RCC_APB2Periph_RESET |
00197                          RCC_APB2Periph_CMDVCC | RCC_APB2Periph_OFF | RCC_APB2Periph_AFIO, ENABLE);
00198
00199   /* Enable SC_USART clocks */
00200   RCC_APB1PeriphClockCmd(SC_USART_CLK, ENABLE);
00201 }
00202
00203 /**
00204   * @brief  Configures the different GPIO ports.
00205   * @param  None
00206   * @retval None
00207   */
00208 void GPIO_Configuration(void)
00209 {
00210   GPIO_InitTypeDef GPIO_InitStructure;
00211
00212 #ifdef USE_STM3210C_EVAL
00213   /* Enable the USART3 Pins Software Full Remapping */
00214   GPIO_PinRemapConfig(GPIO_FullRemap_USART3, ENABLE);
00215 #endif
00216   /* Configure SC_USART CK as alternate function push-pull */
00217   GPIO_InitStructure.GPIO_Pin = SC_USART_ClkPin;
00218   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00219   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
00220   GPIO_Init(SC_USART_GPIO, &GPIO_InitStructure);
00221
00222   /* Configure SC_USART Tx as alternate function open-drain */
00223   GPIO_InitStructure.GPIO_Pin = SC_USART_TxPin;
00224   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_OD;
00225   GPIO_Init(SC_USART_GPIO, &GPIO_InitStructure);
00226
00227   /* Configure Smartcard Reset  */
00228   GPIO_InitStructure.GPIO_Pin = SC_RESET;
00229   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
00230   GPIO_Init(GPIO_RESET, &GPIO_InitStructure);
00231
00232   /* Set RSTIN HIGH */
00233   GPIO_SetBits(GPIO_RESET, SC_RESET);
00234
00235   /* Configure Smartcard 3/5V  */
00236   GPIO_InitStructure.GPIO_Pin = SC_3_5V;
00237   GPIO_Init(GPIO_3_5V, &GPIO_InitStructure);
00238
00239   /* Select 5 V */
00240   GPIO_SetBits(GPIO_3_5V, SC_3_5V);
00241
00242   /* Configure Smartcard CMDVCC  */
00243   GPIO_InitStructure.GPIO_Pin = SC_CMDVCC;
00244   GPIO_Init(GPIO_CMDVCC, &GPIO_InitStructure);
00245
00246   /* Select Smartcard CMDVCC */
00247   GPIO_SetBits(GPIO_CMDVCC, SC_CMDVCC);
00248
00249   /* Select Smartcard OFF */
00250   GPIO_InitStructure.GPIO_Pin = SC_OFF;
00251   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
00252   GPIO_Init(GPIO_OFF, &GPIO_InitStructure);
00253 }
00254
00255 /**
00256   * @brief  Configures the External Interrupts controller.
00257   * @param  None
00258   * @retval None
00259   */
00260 void EXTI_Configuration(void)
00261 {
00262   EXTI_InitTypeDef EXTI_InitStructure;
00263
00264   /* Smartcard OFF */
00265   GPIO_EXTILineConfig(SC_PortSource, SC_PinSource);
00266
00267   EXTI_StructInit(&EXTI_InitStructure);
00268   EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
00269   EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;
00270   EXTI_InitStructure.EXTI_Line = SC_EXTI;
00271   EXTI_InitStructure.EXTI_LineCmd = ENABLE;
00272   EXTI_Init(&EXTI_InitStructure);
00273
00274   /* Clear SC EXTI Line Pending Bit */
00275   EXTI_ClearITPendingBit(SC_EXTI);
00276 }
00277
00278 /**
00279   * @brief  Configures the nested vectored interrupt controller.
00280   * @param  None
00281   * @retval None
00282   */
00283 void NVIC_Configuration(void)
00284 {
00285   NVIC_InitTypeDef NVIC_InitStructure;
00286
00287   /* Configure the NVIC Preemption Priority Bits */
00288   NVIC_PriorityGroupConfig(NVIC_PriorityGroup_1);
00289   /* Clear the SC_EXTI IRQ Pending Bit */
00290   NVIC_ClearPendingIRQ(SC_EXTI_IRQ);
00291
00292   NVIC_InitStructure.NVIC_IRQChannel = SC_EXTI_IRQ;
00293   NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
00294   NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
00295   NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
00296   NVIC_Init(&NVIC_InitStructure);
00297
00298   NVIC_InitStructure.NVIC_IRQChannel = SC_USART_IRQn;
00299   NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
00300   NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
00301   NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
00302   NVIC_Init(&NVIC_InitStructure);
00303 }
00304
00305 /**
00306   * @brief  Decode the Card ATR Response.
00307   * @param  card: pointer to the buffer containing the Card ATR.
00308   * @retval Card protocol
00309   */
00310 uint8_t SC_decode_Answer2reset(__IO uint8_t *card)
00311 {
00312   uint32_t i = 0, flag = 0, buf = 0, protocol = 0;
00313
00314   SC_A2R.TS = 0;
00315   SC_A2R.T0 = 0;
00316   for (i = 0; i < SETUP_LENGHT; i++)
00317   {
00318     SC_A2R.T[i] = 0;
00319   }
00320   for (i = 0;i < HIST_LENGHT; i++)
00321   {
00322     SC_A2R.H[i] = 0;
00323   }
00324   SC_A2R.Tlenght = 0;
00325   SC_A2R.Hlenght = 0;
00326
00327   SC_A2R.TS = card[0]; /* INITIAL CHARACTER */
00328   SC_A2R.T0 = card[1]; /* FORMAT CHARACTER */
00329
00330   SC_A2R.Hlenght = SC_A2R.T0 & 0x0F;
00331
00332   if((SC_A2R.T0 & 0x80) == 0x80) flag = 1;
00333
00334   for(i = 0; i < 4; i++)
00335   {
00336     SC_A2R.Tlenght = SC_A2R.Tlenght + (((SC_A2R.T0 & 0xF0) >> (4 + i)) & 0x1);
00337   }
00338
00339   for(i = 0; i < SC_A2R.Tlenght; i++)
00340   {
00341     SC_A2R.T[i] = card[i + 2];
00342   }
00343
00344   protocol = SC_A2R.T[SC_A2R.Tlenght - 1] & 0x0F;
00345
00346   while(flag)
00347   {
00348     if ((SC_A2R.T[SC_A2R.Tlenght-1] & 0x80)== 0x80)
00349     {
00350       flag = 1;
00351     }
00352     else
00353     {
00354       flag = 0;
00355     }
00356     buf = SC_A2R.Tlenght;
00357     SC_A2R.Tlenght = 0;
00358
00359     for(i = 0; i < 4; i++)
00360     {
00361       SC_A2R.Tlenght = SC_A2R.Tlenght + (((SC_A2R.T[buf - 1] & 0xF0) >> (4 + i)) & 0x1);
00362     }
00363     for(i = 0; i < SC_A2R.Tlenght; i++)
00364     {
00365       SC_A2R.T[buf + i] = card[i + 2 + buf];
00366     }
00367     SC_A2R.Tlenght += buf;
00368   }
00369
00370   for(i = 0;i < SC_A2R.Hlenght; i++)
00371   {
00372     SC_A2R.H[i] = card[i + 2 + SC_A2R.Tlenght];
00373   }
00374
00375   return ((uint8_t)protocol);
00376 }
00377
00378 #ifdef  USE_FULL_ASSERT
00379
00380 /**
00381   * @brief  Reports the name of the source file and the source line number
00382   *         where the assert_param error has occurred.
00383   * @param  file: pointer to the source file name
00384   * @param  line: assert_param error line source number
00385   * @retval None
00386   */
00387 void assert_failed(uint8_t* file, uint32_t line)
00388 {
00389   /* User can add his own implementation to report the file name and line number,
00390      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00391
00392   /* Infinite loop */
00393   while (1)
00394   {
00395   }
00396 }
00397
00398 #endif
00399
00400 /**
00401   * @}
00402   */
00403
00404 /**
00405   * @}
00406   */
00407
00408 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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  • USART
  • Smartcard

STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_conf.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    USART/Smartcard/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052 /* Exported types ------------------------------------------------------------*/
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Uncomment the line below to expanse the "assert_param" macro in the
00055    Standard Peripheral Library drivers code */
00056 /* #define USE_FULL_ASSERT    1 */
00057
00058 /* Exported macro ------------------------------------------------------------*/
00059 #ifdef  USE_FULL_ASSERT
00060
00061 /**
00062   * @brief  The assert_param macro is used for function's parameters check.
00063   * @param  expr: If expr is false, it calls assert_failed function which reports
00064   *         the name of the source file and the source line number of the call
00065   *         that failed. If expr is true, it returns no value.
00066   * @retval None
00067   */
00068   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00069 /* Exported functions ------------------------------------------------------- */
00070   void assert_failed(uint8_t* file, uint32_t line);
00071 #else
00072   #define assert_param(expr) ((void)0)
00073 #endif /* USE_FULL_ASSERT */
00074
00075 #endif /* __STM32F10x_CONF_H */
00076
00077 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_it.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    USART/Smartcard/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and peripherals
00009   *          interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026 #include "platform_config.h"
00027
00028 /** @addtogroup STM32F10x_StdPeriph_Examples
00029   * @{
00030   */
00031
00032 /** @addtogroup USART_Smartcard
00033   * @{
00034   */
00035
00036 /* Private typedef -----------------------------------------------------------*/
00037 /* Private define ------------------------------------------------------------*/
00038 /* Private macro -------------------------------------------------------------*/
00039 /* Private variables ---------------------------------------------------------*/
00040 extern __IO uint32_t CardInserted;
00041
00042 /* Private function prototypes -----------------------------------------------*/
00043 /* Private functions ---------------------------------------------------------*/
00044
00045 /******************************************************************************/
00046 /*            Cortex-M3 Processor Exceptions Handlers                         */
00047 /******************************************************************************/
00048
00049 /**
00050   * @brief  This function handles NMI exception.
00051   * @param  None
00052   * @retval None
00053   */
00054 void NMI_Handler(void)
00055 {
00056 }
00057
00058 /**
00059   * @brief  This function handles Hard Fault exception.
00060   * @param  None
00061   * @retval None
00062   */
00063 void HardFault_Handler(void)
00064 {
00065   /* Go to infinite loop when Hard Fault exception occurs */
00066   while (1)
00067   {
00068   }
00069 }
00070
00071 /**
00072   * @brief  This function handles Memory Manage exception.
00073   * @param  None
00074   * @retval None
00075   */
00076 void MemManage_Handler(void)
00077 {
00078   /* Go to infinite loop when Memory Manage exception occurs */
00079   while (1)
00080   {
00081   }
00082 }
00083
00084 /**
00085   * @brief  This function handles Bus Fault exception.
00086   * @param  None
00087   * @retval None
00088   */
00089 void BusFault_Handler(void)
00090 {
00091   /* Go to infinite loop when Bus Fault exception occurs */
00092   while (1)
00093   {
00094   }
00095 }
00096
00097 /**
00098   * @brief  This function handles Usage Fault exception.
00099   * @param  None
00100   * @retval None
00101   */
00102 void UsageFault_Handler(void)
00103 {
00104   /* Go to infinite loop when Usage Fault exception occurs */
00105   while (1)
00106   {
00107   }
00108 }
00109
00110 /**
00111   * @brief  This function handles SVCall exception.
00112   * @param  None
00113   * @retval None
00114   */
00115 void SVC_Handler(void)
00116 {
00117 }
00118
00119 /**
00120   * @brief  This function handles Debug Monitor exception.
00121   * @param  None
00122   * @retval None
00123   */
00124 void DebugMon_Handler(void)
00125 {
00126 }
00127
00128 /**
00129   * @brief  This function handles PendSV_Handler exception.
00130   * @param  None
00131   * @retval None
00132   */
00133 void PendSV_Handler(void)
00134 {
00135 }
00136
00137 /**
00138   * @brief  This function handles SysTick Handler.
00139   * @param  None
00140   * @retval None
00141   */
00142 void SysTick_Handler(void)
00143 {
00144 }
00145
00146 /******************************************************************************/
00147 /*            STM32F10x Peripherals Interrupt Handlers                        */
00148 /******************************************************************************/
00149
00150 /**
00151   * @brief  This function handles External lines 9 to 5 interrupt request.
00152   * @param  None
00153   * @retval None
00154   */
00155 void EXTI9_5_IRQHandler(void)
00156 {
00157   /* Select Smart Card CMDVCC */
00158   GPIO_ResetBits(GPIO_CMDVCC, SC_CMDVCC);
00159
00160   /* Set RSTIN LOW */
00161   GPIO_ResetBits(GPIO_RESET, SC_RESET);
00162
00163   /* Set RSTIN HIGH */
00164   GPIO_SetBits(GPIO_RESET, SC_RESET);
00165
00166   /* Clear SC EXTIT Line Pending Bit */
00167   EXTI_ClearITPendingBit(SC_EXTI);
00168
00169   /* Smart card detected */
00170   CardInserted = 1;
00171 }
00172
00173 /**
00174   * @brief  This function handles SC_USART global interrupt request.
00175   * @param  None
00176   * @retval None
00177   */
00178 void SC_USART_IRQHandler(void)
00179 {
00180   /* If the SC_USART detects a parity error */
00181   if(USART_GetITStatus(SC_USART, USART_IT_PE) != RESET)
00182   {
00183     /* Enable SC_USART RXNE Interrupt (until receiving the corrupted byte) */
00184     USART_ITConfig(SC_USART, USART_IT_RXNE, ENABLE);
00185     /* Flush the SC_USART DR register */
00186     USART_ReceiveData(SC_USART);
00187   }
00188
00189   if(USART_GetITStatus(SC_USART, USART_IT_RXNE) != RESET)
00190   {
00191     /* Disable SC_USART RXNE Interrupt */
00192     USART_ITConfig(SC_USART, USART_IT_RXNE, DISABLE);
00193     USART_ReceiveData(SC_USART);
00194   }
00195 }
00196
00197 /**
00198   * @brief  This function handles External lines 15 to 10 interrupt request.
00199   * @param  None
00200   * @retval None
00201   */
00202 void EXTI15_10_IRQHandler(void)
00203 {
00204   /* Select Smart Card CMDVCC */
00205   GPIO_ResetBits(GPIO_CMDVCC, SC_CMDVCC);
00206
00207   /* Set RSTIN LOW */
00208   GPIO_ResetBits(GPIO_RESET, SC_RESET);
00209
00210   /* Set RSTIN HIGH */
00211   GPIO_SetBits(GPIO_RESET, SC_RESET);
00212
00213   /* Clear SC EXTIT Line Pending Bit */
00214   EXTI_ClearITPendingBit(SC_EXTI);
00215
00216   /* Smart card detected */
00217   CardInserted = 1;
00218 }
00219
00220 /******************************************************************************/
00221 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00222 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00223 /*  available peripheral interrupt handler's name please refer to the startup */
00224 /*  file (startup_stm32f10x_xx.s).                                            */
00225 /******************************************************************************/
00226
00227 /**
00228   * @brief  This function handles PPP interrupt request.
00229   * @param  None
00230   * @retval None
00231   */
00232 /*void PPP_IRQHandler(void)
00233 {
00234 }*/
00235
00236 /**
00237   * @}
00238   */
00239
00240
00241 /**
00242   * @}
00243   */
00244
00245 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_it.h

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00001 /**
00002   ******************************************************************************
00003   * @file    USART/Smartcard/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043 void EXTI9_5_IRQHandler(void);
00044 void USART3_IRQHandler(void);
00045 void EXTI15_10_IRQHandler(void);
00046
00047 #endif /* __STM32F10x_IT_H */
00048
00049 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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STM32F10x_StdPeriph_Examples/USART/Synchronous/main.c

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00001 /**
00002   ******************************************************************************
00003   * @file    USART/Synchronous/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x.h"
00024 #include "platform_config.h"
00025
00026 /** @addtogroup STM32F10x_StdPeriph_Examples
00027   * @{
00028   */
00029
00030 /** @addtogroup USART_Synchronous
00031   * @{
00032   */
00033
00034 /* Private typedef -----------------------------------------------------------*/
00035 typedef enum {FAILED = 0, PASSED = !FAILED} TestStatus;
00036
00037 /* Private define ------------------------------------------------------------*/
00038 #define TxBufferSize1   (countof(TxBuffer1) - 1)
00039 #define TxBufferSize2   (countof(TxBuffer2) - 1)
00040 #define DYMMY_BYTE      0x00
00041
00042 /* Private macro -------------------------------------------------------------*/
00043 #define countof(a)   (sizeof(a) / sizeof(*(a)))
00044
00045 /* Private variables ---------------------------------------------------------*/
00046 USART_InitTypeDef USART_InitStructure;
00047 USART_ClockInitTypeDef USART_ClockInitStructure;
00048
00049 uint8_t TxBuffer1[] = "USART Synchronous Example: USARTy -> SPIy using TXE and RXNE Flags";
00050 uint8_t TxBuffer2[] = "USART Synchronous Example: SPIy -> USARTy using TXE and RXNE Flags";
00051 uint8_t RxBuffer1[TxBufferSize2];
00052 uint8_t RxBuffer2[TxBufferSize1];
00053 __IO uint8_t NbrOfDataToRead1 = TxBufferSize2;
00054 __IO uint8_t NbrOfDataToRead2 = TxBufferSize1;
00055 __IO uint8_t TxCounter1 = 0, RxCounter1 = 0;
00056 __IO uint8_t TxCounter2 = 0, RxCounter2 = 0;
00057 volatile TestStatus TransferStatus1 = FAILED, TransferStatus2 = FAILED;
00058
00059 /* Private function prototypes -----------------------------------------------*/
00060 void RCC_Configuration(void);
00061 void GPIO_Configuration(void);
00062 void SPI_Configuration(void);
00063 TestStatus Buffercmp(uint8_t* pBuffer1, uint8_t* pBuffer2, uint16_t BufferLength);
00064
00065 /* Private functions ---------------------------------------------------------*/
00066
00067 /**
00068   * @brief  Main program
00069   * @param  None
00070   * @retval None
00071   */
00072 int main(void)
00073 {
00074   /*!< At this stage the microcontroller clock setting is already configured,
00075        this is done through SystemInit() function which is called from startup
00076        file (startup_stm32f10x_xx.s) before to branch to application main.
00077        To reconfigure the default setting of SystemInit() function, refer to
00078        system_stm32f10x.c file
00079      */
00080
00081   /* System Clocks Configuration */
00082   RCC_Configuration();
00083
00084   /* Configure the GPIO ports */
00085   GPIO_Configuration();
00086
00087   /* Configure the SPI */
00088   SPI_Configuration();
00089
00090 /* USARTy configuration ------------------------------------------------------*/
00091   /* USARTy configured as follow:
00092         - BaudRate = 115200 baud
00093         - Word Length = 8 Bits
00094         - One Stop Bit
00095         - No parity
00096         - Hardware flow control disabled (RTS and CTS signals)
00097         - Receive and transmit enabled
00098         - USART Clock Enabled
00099         - USART CPOL: Clock is active High
00100         - USART CPHA: Data is captured on the second edge
00101         - USART LastBit: The clock pulse of the last data bit is output to
00102                          the SCLK pin
00103   */
00104   USART_ClockInitStructure.USART_Clock = USART_Clock_Enable;
00105   USART_ClockInitStructure.USART_CPOL = USART_CPOL_High;
00106   USART_ClockInitStructure.USART_CPHA = USART_CPHA_2Edge;
00107   USART_ClockInitStructure.USART_LastBit = USART_LastBit_Enable;
00108   USART_ClockInit(USARTy, &USART_ClockInitStructure);
00109
00110   USART_InitStructure.USART_BaudRate = 115200;
00111   USART_InitStructure.USART_WordLength = USART_WordLength_8b;
00112   USART_InitStructure.USART_StopBits = USART_StopBits_1;
00113   USART_InitStructure.USART_Parity = USART_Parity_No ;
00114   USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
00115   USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
00116   USART_Init(USARTy, &USART_InitStructure);
00117
00118   /* Configure the USARTy */
00119   USART_Init(USARTy, &USART_InitStructure);
00120
00121   /* Enable the USARTy */
00122   USART_Cmd(USARTy, ENABLE);
00123
00124   while(NbrOfDataToRead2--)
00125   {
00126     /* Write one byte in the USARTy Transmit Data Register */
00127     USART_SendData(USARTy, TxBuffer1[TxCounter1++]);
00128     /* Wait until end of transmit */
00129     while(USART_GetFlagStatus(USARTy, USART_FLAG_TC) == RESET)
00130     {
00131     }
00132     /* Wait the byte is entirely received by SPIy */
00133     while(SPI_I2S_GetFlagStatus(SPIy, SPI_I2S_FLAG_RXNE) == RESET)
00134     {
00135     }
00136     /* Store the received byte in the RxBuffer2 */
00137     RxBuffer2[RxCounter2++] = SPI_I2S_ReceiveData(SPIy);
00138   }
00139
00140   /* Clear the USARTy Data Register */
00141   USART_ReceiveData(USARTy);
00142
00143   while(NbrOfDataToRead1--)
00144   {
00145     /* Wait until end of transmit */
00146     while(SPI_I2S_GetFlagStatus(SPIy, SPI_I2S_FLAG_TXE)== RESET)
00147     {
00148     }
00149     /* Write one byte in the SPIy Transmit Data Register */
00150     SPI_I2S_SendData(SPIy, TxBuffer2[TxCounter2++]);
00151
00152     /* Send a Dummy byte to generate clock to slave */
00153     USART_SendData(USARTy, DYMMY_BYTE);
00154     /* Wait until end of transmit */
00155     while(USART_GetFlagStatus(USARTy, USART_FLAG_TC) == RESET)
00156     {
00157     }
00158     /* Wait the byte is entirely received by USARTy */
00159     while(USART_GetFlagStatus(USARTy, USART_FLAG_RXNE) == RESET)
00160     {
00161     }
00162     /* Store the received byte in the RxBuffer1 */
00163     RxBuffer1[RxCounter1++] = USART_ReceiveData(USARTy);
00164   }
00165
00166   /* Check the received data with the send ones */
00167   TransferStatus1 = Buffercmp(TxBuffer1, RxBuffer2, TxBufferSize1);
00168   /* TransferStatus = PASSED, if the data transmitted from USARTy and
00169      received by SPIy are the same */
00170   /* TransferStatus = FAILED, if the data transmitted from USARTy and
00171      received by SPIy are different */
00172   TransferStatus2 = Buffercmp(TxBuffer2, RxBuffer1, TxBufferSize2);
00173   /* TransferStatus = PASSED, if the data transmitted from SPIy and
00174      received by USARTy are the same */
00175   /* TransferStatus = FAILED, if the data transmitted from SPIy and
00176      received by USARTy are different */
00177
00178   while (1)
00179   {
00180   }
00181 }
00182
00183 /**
00184   * @brief  Configures the different system clocks.
00185   * @param  None
00186   * @retval None
00187   */
00188 void RCC_Configuration(void)
00189 {
00190   /* Enable GPIO clock */
00191   RCC_APB2PeriphClockCmd(USARTy_GPIO_CLK | SPIy_GPIO_CLK | RCC_APB2Periph_AFIO, ENABLE);
00192
00193   /* Enable USARTy Clock */
00194   RCC_APB2PeriphClockCmd(USARTy_CLK, ENABLE);
00195   /* Enable SPIy Clock */
00196   RCC_APB2PeriphClockCmd(SPIy_CLK, ENABLE);
00197 }
00198
00199 /**
00200   * @brief  Configures the different GPIO ports.
00201   * @param  None
00202   * @retval None
00203   */
00204 void GPIO_Configuration(void)
00205 {
00206   GPIO_InitTypeDef GPIO_InitStructure;
00207
00208   /* Configure USARTy TX and USARTy CK pins as alternate function push-pull */
00209   GPIO_InitStructure.GPIO_Pin = USARTy_TxPin | USARTy_ClkPin;
00210   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00211   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
00212   GPIO_Init(USARTy_GPIO, &GPIO_InitStructure);
00213
00214   /* Configure SPI1 pins: SCK, MISO and MOSI */
00215   GPIO_InitStructure.GPIO_Pin = SPIy_SCKPin | SPIy_MISOPin | SPIy_MOSIPin;
00216   GPIO_Init(SPIy_GPIO, &GPIO_InitStructure);
00217
00218   /* Configure USARTy RX as input floating */
00219   GPIO_InitStructure.GPIO_Pin = USARTy_RxPin;
00220   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
00221   GPIO_Init(USARTy_GPIO, &GPIO_InitStructure);
00222 }
00223
00224 /**
00225   * @brief  Configures the SPI.
00226   * @param  None
00227   * @retval None
00228   */
00229 void SPI_Configuration(void)
00230 {
00231   SPI_InitTypeDef SPI_InitStructure;
00232
00233   SPI_StructInit(&SPI_InitStructure);
00234
00235   SPI_I2S_DeInit(SPIy);
00236
00237   /* SPIy Config */
00238   SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
00239   SPI_InitStructure.SPI_Mode = SPI_Mode_Slave;
00240   SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
00241   SPI_InitStructure.SPI_CPOL = SPI_CPOL_High;
00242   SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge;
00243   SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
00244   SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_LSB;
00245
00246   /* Configure SPIy */
00247   SPI_Init(SPIy, &SPI_InitStructure);
00248
00249   /* SPIy enable */
00250   SPI_Cmd(SPIy, ENABLE);
00251 }
00252
00253 /**
00254   * @brief  Compares two buffers.
00255   * @param  pBuffer1, pBuffer2: buffers to be compared.
00256   * @param  BufferLength: buffer's length
00257   * @retval PASSED: pBuffer1 identical to pBuffer2
00258   *         FAILED: pBuffer1 differs from pBuffer2
00259   */
00260 TestStatus Buffercmp(uint8_t* pBuffer1, uint8_t* pBuffer2, uint16_t BufferLength)
00261 {
00262   while(BufferLength--)
00263   {
00264     if(*pBuffer1 != *pBuffer2)
00265     {
00266       return FAILED;
00267     }
00268
00269     pBuffer1++;
00270     pBuffer2++;
00271   }
00272
00273   return PASSED;
00274 }
00275
00276 #ifdef  USE_FULL_ASSERT
00277
00278 /**
00279   * @brief  Reports the name of the source file and the source line number
00280   *         where the assert_param error has occurred.
00281   * @param  file: pointer to the source file name
00282   * @param  line: assert_param error line source number
00283   * @retval None
00284   */
00285 void assert_failed(uint8_t* file, uint32_t line)
00286 {
00287   /* User can add his own implementation to report the file name and line number,
00288      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00289
00290   /* Infinite loop */
00291   while (1)
00292   {
00293   }
00294 }
00295
00296 #endif
00297
00298 /**
00299   * @}
00300   */
00301
00302 /**
00303   * @}
00304   */
00305
00306 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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STM32F10x_StdPeriph_Examples/USART/Synchronous/stm32f10x_conf.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    USART/Synchronous/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052 /* Exported types ------------------------------------------------------------*/
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Uncomment the line below to expanse the "assert_param" macro in the
00055    Standard Peripheral Library drivers code */
00056 /* #define USE_FULL_ASSERT    1 */
00057
00058 /* Exported macro ------------------------------------------------------------*/
00059 #ifdef  USE_FULL_ASSERT
00060
00061 /**
00062   * @brief  The assert_param macro is used for function's parameters check.
00063   * @param  expr: If expr is false, it calls assert_failed function which reports
00064   *         the name of the source file and the source line number of the call
00065   *         that failed. If expr is true, it returns no value.
00066   * @retval None
00067   */
00068   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00069 /* Exported functions ------------------------------------------------------- */
00070   void assert_failed(uint8_t* file, uint32_t line);
00071 #else
00072   #define assert_param(expr) ((void)0)
00073 #endif /* USE_FULL_ASSERT */
00074
00075 #endif /* __STM32F10x_CONF_H */
00076
00077 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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STM32F10x_StdPeriph_Examples/USART/Synchronous/stm32f10x_it.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    USART/Synchronous/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and peripherals
00009   *          interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026
00027 /** @addtogroup STM32F10x_StdPeriph_Examples
00028   * @{
00029   */
00030
00031 /** @addtogroup USART_Synchronous
00032   * @{
00033   */
00034
00035 /* Private typedef -----------------------------------------------------------*/
00036 /* Private define ------------------------------------------------------------*/
00037 /* Private macro -------------------------------------------------------------*/
00038 /* Private variables ---------------------------------------------------------*/
00039 /* Private function prototypes -----------------------------------------------*/
00040 /* Private functions ---------------------------------------------------------*/
00041
00042 /******************************************************************************/
00043 /*            Cortex-M3 Processor Exceptions Handlers                         */
00044 /******************************************************************************/
00045
00046 /**
00047   * @brief  This function handles NMI exception.
00048   * @param  None
00049   * @retval None
00050   */
00051 void NMI_Handler(void)
00052 {
00053 }
00054
00055 /**
00056   * @brief  This function handles Hard Fault exception.
00057   * @param  None
00058   * @retval None
00059   */
00060 void HardFault_Handler(void)
00061 {
00062   /* Go to infinite loop when Hard Fault exception occurs */
00063   while (1)
00064   {
00065   }
00066 }
00067
00068 /**
00069   * @brief  This function handles Memory Manage exception.
00070   * @param  None
00071   * @retval None
00072   */
00073 void MemManage_Handler(void)
00074 {
00075   /* Go to infinite loop when Memory Manage exception occurs */
00076   while (1)
00077   {
00078   }
00079 }
00080
00081 /**
00082   * @brief  This function handles Bus Fault exception.
00083   * @param  None
00084   * @retval None
00085   */
00086 void BusFault_Handler(void)
00087 {
00088   /* Go to infinite loop when Bus Fault exception occurs */
00089   while (1)
00090   {
00091   }
00092 }
00093
00094 /**
00095   * @brief  This function handles Usage Fault exception.
00096   * @param  None
00097   * @retval None
00098   */
00099 void UsageFault_Handler(void)
00100 {
00101   /* Go to infinite loop when Usage Fault exception occurs */
00102   while (1)
00103   {
00104   }
00105 }
00106
00107 /**
00108   * @brief  This function handles SVCall exception.
00109   * @param  None
00110   * @retval None
00111   */
00112 void SVC_Handler(void)
00113 {
00114 }
00115
00116 /**
00117   * @brief  This function handles Debug Monitor exception.
00118   * @param  None
00119   * @retval None
00120   */
00121 void DebugMon_Handler(void)
00122 {
00123 }
00124
00125 /**
00126   * @brief  This function handles PendSV_Handler exception.
00127   * @param  None
00128   * @retval None
00129   */
00130 void PendSV_Handler(void)
00131 {
00132 }
00133
00134 /**
00135   * @brief  This function handles SysTick Handler.
00136   * @param  None
00137   * @retval None
00138   */
00139 void SysTick_Handler(void)
00140 {
00141 }
00142
00143 /******************************************************************************/
00144 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00145 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00146 /*  available peripheral interrupt handler's name please refer to the startup */
00147 /*  file (startup_stm32f10x_xx.s).                                            */
00148 /******************************************************************************/
00149
00150 /**
00151   * @brief  This function handles PPP interrupt request.
00152   * @param  None
00153   * @retval None
00154   */
00155 /*void PPP_IRQHandler(void)
00156 {
00157 }*/
00158
00159 /**
00160   * @}
00161   */
00162
00163 /**
00164   * @}
00165   */
00166
00167 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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STM32F10x_StdPeriph_Examples/USART/Synchronous/stm32f10x_it.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    USART/Synchronous/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043
00044 #endif /* __STM32F10x_IT_H */
00045
00046 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/main.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    WWDG/WWDG_Reset/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022
00023 /* Includes ------------------------------------------------------------------*/
00024 #include "stm32f10x.h"
00025 #include "stm32_eval.h"
00026
00027 /** @addtogroup STM32F10x_StdPeriph_Examples
00028   * @{
00029   */
00030
00031 /** @addtogroup WWDG_Reset
00032   * @{
00033   */
00034
00035 /* Private typedef -----------------------------------------------------------*/
00036 /* Private define ------------------------------------------------------------*/
00037 /* Private macro -------------------------------------------------------------*/
00038 /* Private variables ---------------------------------------------------------*/
00039 __IO uint32_t TimingDelay = 0;
00040
00041 /* Private function prototypes -----------------------------------------------*/
00042 void Delay(__IO uint32_t nTime);
00043
00044 /* Private functions ---------------------------------------------------------*/
00045
00046 /**
00047   * @brief  Main program.
00048   * @param  None
00049   * @retval None
00050   */
00051 int main(void)
00052 {
00053   /*!< At this stage the microcontroller clock setting is already configured,
00054        this is done through SystemInit() function which is called from startup
00055        file (startup_stm32f10x_xx.s) before to branch to application main.
00056        To reconfigure the default setting of SystemInit() function, refer to
00057        system_stm32f10x.c file
00058      */
00059
00060   /* Initialize LED1 and Key Button mounted on STM3210X-EVAL board */
00061   STM_EVAL_LEDInit(LED1);
00062   STM_EVAL_LEDInit(LED2);
00063   STM_EVAL_PBInit(BUTTON_KEY, BUTTON_MODE_EXTI);
00064
00065
00066   /* Check if the system has resumed from WWDG reset */
00067   if (RCC_GetFlagStatus(RCC_FLAG_WWDGRST) != RESET)
00068   {
00069     /* WWDGRST flag set */
00070     /* Turn on LED1 */
00071     STM_EVAL_LEDOn(LED1);
00072
00073     /* Clear reset flags */
00074     RCC_ClearFlag();
00075   }
00076   else
00077   {
00078     /* WWDGRST flag is not set */
00079     /* Turn off LED1 */
00080     STM_EVAL_LEDOff(LED1);
00081   }
00082
00083   /* Setup SysTick Timer for 1 msec interrupts  */
00084   if (SysTick_Config(SystemCoreClock / 1000))
00085   {
00086     /* Capture error */
00087     while (1);
00088   }
00089
00090   /* WWDG configuration */
00091   /* Enable WWDG clock */
00092   RCC_APB1PeriphClockCmd(RCC_APB1Periph_WWDG, ENABLE);
00093
00094 /* On Value line devices, WWDG clock counter = (PCLK1 (24MHz)/4096)/8 = 732 Hz (~1366 us)  */
00095 /* On other devices, WWDG clock counter = (PCLK1(36MHz)/4096)/8 = 1099 Hz (~910 us)  */
00096   WWDG_SetPrescaler(WWDG_Prescaler_8);
00097
00098   /* Set Window value to 80; WWDG counter should be refreshed only when the counter
00099     is below 80 (and greater than 64) otherwise a reset will be generated */
00100   WWDG_SetWindowValue(80);
00101
00102   /* - On Value line devices,
00103     Enable WWDG and set counter value to 127, WWDG timeout = ~1366 us * 64 = 87.42 ms
00104     In this case the refresh window is: ~1366us * (127-80) = 64.20 ms < refresh window < ~1366us * 64 = 87.42ms
00105      - On other devices
00106     Enable WWDG and set counter value to 127, WWDG timeout = ~910 us * 64 = 58.25 ms
00107     In this case the refresh window is: ~910 us * (127-80) = 42.77 ms < refresh window < ~910 us * 64 = 58.25ms
00108   */
00109   WWDG_Enable(127);
00110
00111   while (1)
00112   {
00113     /* Toggle LED2 */
00114     STM_EVAL_LEDToggle(LED2);
00115
00116 #if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL)
00117     /* Insert 44 ms delay */
00118     Delay(44);
00119 #else
00120     /* Insert 66 ms delay */
00121     Delay(66);
00122 #endif
00123
00124     /* Update WWDG counter */
00125     WWDG_SetCounter(127);
00126   }
00127 }
00128
00129 /**
00130   * @brief  Inserts a delay time.
00131   * @param  nTime: specifies the delay time length, in milliseconds.
00132   * @retval None
00133   */
00134 void Delay(__IO uint32_t nTime)
00135 {
00136   TimingDelay = nTime;
00137   while(TimingDelay != 0)
00138   {
00139   }
00140 }
00141
00142 #ifdef  USE_FULL_ASSERT
00143
00144 /**
00145   * @brief  Reports the name of the source file and the source line number
00146   *         where the assert_param error has occurred.
00147   * @param  file: pointer to the source file name
00148   * @param  line: assert_param error line source number
00149   * @retval None
00150   */
00151 void assert_failed(uint8_t* file, uint32_t line)
00152 {
00153   /* User can add his own implementation to report the file name and line number,
00154      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00155
00156   /* Infinite loop */
00157   while (1)
00158   {}
00159 }
00160
00161 #endif
00162
00163 /**
00164   * @}
00165   */
00166
00167 /**
00168   * @}
00169   */
00170
00171 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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  • WWDG
  • WWDG_Reset

STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_conf.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    WWDG/WWDG_Reset/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052 /* Exported types ------------------------------------------------------------*/
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Uncomment the line below to expanse the "assert_param" macro in the
00055    Standard Peripheral Library drivers code */
00056 /* #define USE_FULL_ASSERT    1 */
00057
00058 /* Exported macro ------------------------------------------------------------*/
00059 #ifdef  USE_FULL_ASSERT
00060
00061 /**
00062   * @brief  The assert_param macro is used for function's parameters check.
00063   * @param  expr: If expr is false, it calls assert_failed function which reports
00064   *         the name of the source file and the source line number of the call
00065   *         that failed. If expr is true, it returns no value.
00066   * @retval None
00067   */
00068   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00069 /* Exported functions ------------------------------------------------------- */
00070   void assert_failed(uint8_t* file, uint32_t line);
00071 #else
00072   #define assert_param(expr) ((void)0)
00073 #endif /* USE_FULL_ASSERT */
00074
00075 #endif /* __STM32F10x_CONF_H */
00076
00077 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_it.c

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00001 /**
00002   ******************************************************************************
00003   * @file    WWDG/WWDG_Reset/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and peripherals
00009   *          interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026 #include "stm32_eval.h"
00027
00028 /** @addtogroup STM32F10x_StdPeriph_Examples
00029   * @{
00030   */
00031
00032 /** @addtogroup WWDG_Reset
00033   * @{
00034   */
00035
00036 /* Private typedef -----------------------------------------------------------*/
00037 /* Private define ------------------------------------------------------------*/
00038 /* Private macro -------------------------------------------------------------*/
00039 /* Private variables ---------------------------------------------------------*/
00040 extern __IO uint32_t TimingDelay;
00041
00042 /* Private function prototypes -----------------------------------------------*/
00043 /* Private functions ---------------------------------------------------------*/
00044
00045 /******************************************************************************/
00046 /*            Cortex-M3 Processor Exceptions Handlers                         */
00047 /******************************************************************************/
00048
00049 /**
00050   * @brief  This function handles NMI exception.
00051   * @param  None
00052   * @retval None
00053   */
00054 void NMI_Handler(void)
00055 {
00056 }
00057
00058 /**
00059   * @brief  This function handles Hard Fault exception.
00060   * @param  None
00061   * @retval None
00062   */
00063 void HardFault_Handler(void)
00064 {
00065   /* Go to infinite loop when Hard Fault exception occurs */
00066   while (1)
00067   {}
00068 }
00069
00070 /**
00071   * @brief  This function handles Memory Manage exception.
00072   * @param  None
00073   * @retval None
00074   */
00075 void MemManage_Handler(void)
00076 {
00077   /* Go to infinite loop when Memory Manage exception occurs */
00078   while (1)
00079   {}
00080 }
00081
00082 /**
00083   * @brief  This function handles Bus Fault exception.
00084   * @param  None
00085   * @retval None
00086   */
00087 void BusFault_Handler(void)
00088 {
00089   /* Go to infinite loop when Bus Fault exception occurs */
00090   while (1)
00091   {}
00092 }
00093
00094 /**
00095   * @brief  This function handles Usage Fault exception.
00096   * @param  None
00097   * @retval None
00098   */
00099 void UsageFault_Handler(void)
00100 {
00101   /* Go to infinite loop when Usage Fault exception occurs */
00102   while (1)
00103   {}
00104 }
00105
00106 /**
00107   * @brief  This function handles Debug Monitor exception.
00108   * @param  None
00109   * @retval None
00110   */
00111 void DebugMon_Handler(void)
00112 {
00113 }
00114
00115 /**
00116   * @brief  This function handles SVCall exception.
00117   * @param  None
00118   * @retval None
00119   */
00120 void SVC_Handler(void)
00121 {
00122 }
00123
00124 /**
00125   * @brief  This function handles PendSV_Handler exception.
00126   * @param  None
00127   * @retval None
00128   */
00129 void PendSV_Handler(void)
00130 {
00131 }
00132
00133 /**
00134   * @brief  This function handles SysTick Handler.
00135   * @param  None
00136   * @retval None
00137   */
00138 void SysTick_Handler(void)
00139 {
00140   TimingDelay--;
00141 }
00142
00143 /******************************************************************************/
00144 /*            STM32F10x Peripherals Interrupt Handlers                        */
00145 /******************************************************************************/
00146
00147 /**
00148   * @brief  This function handles External lines 9 to 5 interrupt request.
00149   * @param  None
00150   * @retval None
00151   */
00152 void EXTI9_5_IRQHandler(void)
00153 {
00154   if (EXTI_GetITStatus(KEY_BUTTON_EXTI_LINE) != RESET)
00155   {
00156     /* Clear the Key Button EXTI Line Pending Bit */
00157     EXTI_ClearITPendingBit(KEY_BUTTON_EXTI_LINE);
00158
00159     /* As the following address is invalid (not mapped), a Hardfault exception
00160           will be generated with an infinite loop and when the WWDG counter falls to 63
00161     the WWDG reset occurs */
00162           *(__IO uint32_t *) 0x000000FF = 0xFF;
00163   }
00164 }
00165
00166 /******************************************************************************/
00167 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00168 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00169 /*  available peripheral interrupt handler's name please refer to the startup */
00170 /*  file (startup_stm32f10x_xx.s).                                            */
00171 /******************************************************************************/
00172
00173 /**
00174   * @brief  This function handles PPP interrupt request.
00175   * @param  None
00176   * @retval None
00177   */
00178 /*void PPP_IRQHandler(void)
00179 {
00180 }*/
00181
00182
00183 /**
00184   * @}
00185   */
00186
00187 /**
00188   * @}
00189   */
00190
00191 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_it.h

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00001 /**
00002   ******************************************************************************
00003   * @file    WWDG/WWDG_Reset/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Exported macro ------------------------------------------------------------*/
00032 /* Exported functions ------------------------------------------------------- */
00033
00034 void NMI_Handler(void);
00035 void HardFault_Handler(void);
00036 void MemManage_Handler(void);
00037 void BusFault_Handler(void);
00038 void UsageFault_Handler(void);
00039 void SVC_Handler(void);
00040 void DebugMon_Handler(void);
00041 void PendSV_Handler(void);
00042 void SysTick_Handler(void);
00043 void EXTI9_5_IRQHandler(void);
00044
00045 #endif /* __STM32F10x_IT_H */
00046
00047 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.c Source File

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STM32F10x_StdPeriph_Template/main.c

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00001 /**
00002   ******************************************************************************
00003   * @file    Project/STM32F10x_StdPeriph_Template/main.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main program body
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x.h"
00024 #include "stm32_eval.h"
00025 #include <stdio.h>
00026
00027 #ifdef USE_STM32100B_EVAL
00028  #include "stm32100b_eval_lcd.h"
00029 #elif defined USE_STM3210B_EVAL
00030  #include "stm3210b_eval_lcd.h"
00031 #elif defined USE_STM3210E_EVAL
00032  #include "stm3210e_eval_lcd.h"
00033 #elif defined USE_STM3210C_EVAL
00034  #include "stm3210c_eval_lcd.h"
00035 #elif defined USE_STM32100E_EVAL
00036  #include "stm32100e_eval_lcd.h"
00037 #endif
00038
00039 /** @addtogroup STM32F10x_StdPeriph_Template
00040   * @{
00041   */
00042
00043 /* Private typedef -----------------------------------------------------------*/
00044 /* Private define ------------------------------------------------------------*/
00045 #ifdef USE_STM32100B_EVAL
00046   #define MESSAGE1   "STM32 MD Value Line "
00047   #define MESSAGE2   " Device running on  "
00048   #define MESSAGE3   "  STM32100B-EVAL    "
00049 #elif defined (USE_STM3210B_EVAL)
00050   #define MESSAGE1   "STM32 Medium Density"
00051   #define MESSAGE2   " Device running on  "
00052   #define MESSAGE3   "   STM3210B-EVAL    "
00053 #elif defined (STM32F10X_XL) && defined (USE_STM3210E_EVAL)
00054   #define MESSAGE1   "  STM32 XL Density  "
00055   #define MESSAGE2   " Device running on  "
00056   #define MESSAGE3   "   STM3210E-EVAL    "
00057 #elif defined (USE_STM3210E_EVAL)
00058   #define MESSAGE1   " STM32 High Density "
00059   #define MESSAGE2   " Device running on  "
00060   #define MESSAGE3   "   STM3210E-EVAL    "
00061 #elif defined (USE_STM3210C_EVAL)
00062   #define MESSAGE1   " STM32 Connectivity "
00063   #define MESSAGE2   " Line Device running"
00064   #define MESSAGE3   " on STM3210C-EVAL   "
00065 #elif defined (USE_STM32100E_EVAL)
00066   #define MESSAGE1   "STM32 HD Value Line "
00067   #define MESSAGE2   " Device running on  "
00068   #define MESSAGE3   "  STM32100E-EVAL    "
00069 #endif
00070
00071 /* Private macro -------------------------------------------------------------*/
00072 /* Private variables ---------------------------------------------------------*/
00073  USART_InitTypeDef USART_InitStructure;
00074
00075 /* Private function prototypes -----------------------------------------------*/
00076 #ifdef __GNUC__
00077 /* With GCC/RAISONANCE, small printf (option LD Linker->Libraries->Small printf
00078    set to 'Yes') calls __io_putchar() */
00079 #define PUTCHAR_PROTOTYPE int __io_putchar(int ch)
00080 #else
00081 #define PUTCHAR_PROTOTYPE int fputc(int ch, FILE *f)
00082 #endif /* __GNUC__ */
00083
00084 /* Private functions ---------------------------------------------------------*/
00085
00086 /**
00087   * @brief  Main program.
00088   * @param  None
00089   * @retval None
00090   */
00091 int main(void)
00092 {
00093   /*!< At this stage the microcontroller clock setting is already configured,
00094        this is done through SystemInit() function which is called from startup
00095        file (startup_stm32f10x_xx.s) before to branch to application main.
00096        To reconfigure the default setting of SystemInit() function, refer to
00097        system_stm32f10x.c file
00098      */
00099
00100   /* Initialize LEDs, Key Button, LCD and COM port(USART) available on
00101      STM3210X-EVAL board ******************************************************/
00102   STM_EVAL_LEDInit(LED1);
00103   STM_EVAL_LEDInit(LED2);
00104   STM_EVAL_LEDInit(LED3);
00105   STM_EVAL_LEDInit(LED4);
00106
00107   /* USARTx configured as follow:
00108         - BaudRate = 115200 baud
00109         - Word Length = 8 Bits
00110         - One Stop Bit
00111         - No parity
00112         - Hardware flow control disabled (RTS and CTS signals)
00113         - Receive and transmit enabled
00114   */
00115   USART_InitStructure.USART_BaudRate = 115200;
00116   USART_InitStructure.USART_WordLength = USART_WordLength_8b;
00117   USART_InitStructure.USART_StopBits = USART_StopBits_1;
00118   USART_InitStructure.USART_Parity = USART_Parity_No;
00119   USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
00120   USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
00121
00122   STM_EVAL_COMInit(COM1, &USART_InitStructure);
00123
00124   /* Initialize the LCD */
00125 #ifdef USE_STM32100B_EVAL
00126   STM32100B_LCD_Init();
00127 #elif defined (USE_STM3210B_EVAL)
00128   STM3210B_LCD_Init();
00129 #elif defined (USE_STM3210E_EVAL)
00130   STM3210E_LCD_Init();
00131 #elif defined (USE_STM3210C_EVAL)
00132   STM3210C_LCD_Init();
00133 #elif defined (USE_STM32100E_EVAL)
00134   STM32100E_LCD_Init();
00135 #endif
00136
00137   /* Display message on STM3210X-EVAL LCD *************************************/
00138   /* Clear the LCD */
00139   LCD_Clear(LCD_COLOR_WHITE);
00140
00141   /* Set the LCD Back Color */
00142   LCD_SetBackColor(LCD_COLOR_BLUE);
00143   /* Set the LCD Text Color */
00144   LCD_SetTextColor(LCD_COLOR_WHITE);
00145   LCD_DisplayStringLine(LCD_LINE_0, (uint8_t *)MESSAGE1);
00146   LCD_DisplayStringLine(LCD_LINE_1, (uint8_t *)MESSAGE2);
00147   LCD_DisplayStringLine(LCD_LINE_2, (uint8_t *)MESSAGE3);
00148
00149   /* Retarget the C library printf function to the USARTx, can be USART1 or USART2
00150      depending on the EVAL board you are using ********************************/
00151   printf("\n\r %s", MESSAGE1);
00152   printf(" %s", MESSAGE2);
00153   printf(" %s\n\r", MESSAGE3);
00154
00155   /* Turn on leds available on STM3210X-EVAL **********************************/
00156   STM_EVAL_LEDOn(LED1);
00157   STM_EVAL_LEDOn(LED2);
00158   STM_EVAL_LEDOn(LED3);
00159   STM_EVAL_LEDOn(LED4);
00160
00161   /* Add your application code here
00162      */
00163
00164   /* Infinite loop */
00165   while (1)
00166   {
00167   }
00168 }
00169
00170 /**
00171   * @brief  Retargets the C library printf function to the USART.
00172   * @param  None
00173   * @retval None
00174   */
00175 PUTCHAR_PROTOTYPE
00176 {
00177   /* Place your implementation of fputc here */
00178   /* e.g. write a character to the USART */
00179   USART_SendData(EVAL_COM1, (uint8_t) ch);
00180
00181   /* Loop until the end of transmission */
00182   while (USART_GetFlagStatus(EVAL_COM1, USART_FLAG_TC) == RESET)
00183   {}
00184
00185   return ch;
00186 }
00187
00188 #ifdef  USE_FULL_ASSERT
00189
00190 /**
00191   * @brief  Reports the name of the source file and the source line number
00192   *         where the assert_param error has occurred.
00193   * @param  file: pointer to the source file name
00194   * @param  line: assert_param error line source number
00195   * @retval None
00196   */
00197 void assert_failed(uint8_t* file, uint32_t line)
00198 {
00199   /* User can add his own implementation to report the file name and line number,
00200      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00201
00202   /* Infinite loop */
00203   while (1)
00204   {
00205   }
00206 }
00207 #endif
00208
00209 /**
00210   * @}
00211   */
00212
00213
00214 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_conf.h Source File

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STM32F10x_StdPeriph_Template/stm32f10x_conf.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    Project/STM32F10x_StdPeriph_Template/stm32f10x_conf.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Library configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_CONF_H
00024 #define __STM32F10x_CONF_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
00028 #include "stm32f10x_adc.h"
00029 #include "stm32f10x_bkp.h"
00030 #include "stm32f10x_can.h"
00031 #include "stm32f10x_cec.h"
00032 #include "stm32f10x_crc.h"
00033 #include "stm32f10x_dac.h"
00034 #include "stm32f10x_dbgmcu.h"
00035 #include "stm32f10x_dma.h"
00036 #include "stm32f10x_exti.h"
00037 #include "stm32f10x_flash.h"
00038 #include "stm32f10x_fsmc.h"
00039 #include "stm32f10x_gpio.h"
00040 #include "stm32f10x_i2c.h"
00041 #include "stm32f10x_iwdg.h"
00042 #include "stm32f10x_pwr.h"
00043 #include "stm32f10x_rcc.h"
00044 #include "stm32f10x_rtc.h"
00045 #include "stm32f10x_sdio.h"
00046 #include "stm32f10x_spi.h"
00047 #include "stm32f10x_tim.h"
00048 #include "stm32f10x_usart.h"
00049 #include "stm32f10x_wwdg.h"
00050 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
00051
00052 /* Exported types ------------------------------------------------------------*/
00053 /* Exported constants --------------------------------------------------------*/
00054 /* Uncomment the line below to expanse the "assert_param" macro in the
00055    Standard Peripheral Library drivers code */
00056 /* #define USE_FULL_ASSERT    1 */
00057
00058 /* Exported macro ------------------------------------------------------------*/
00059 #ifdef  USE_FULL_ASSERT
00060
00061 /**
00062   * @brief  The assert_param macro is used for function's parameters check.
00063   * @param  expr: If expr is false, it calls assert_failed function which reports
00064   *         the name of the source file and the source line number of the call
00065   *         that failed. If expr is true, it returns no value.
00066   * @retval None
00067   */
00068   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00069 /* Exported functions ------------------------------------------------------- */
00070   void assert_failed(uint8_t* file, uint32_t line);
00071 #else
00072   #define assert_param(expr) ((void)0)
00073 #endif /* USE_FULL_ASSERT */
00074
00075 #endif /* __STM32F10x_CONF_H */
00076
00077 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.c Source File

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STM32F10x_StdPeriph_Template/stm32f10x_it.c

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00001 /**
00002   ******************************************************************************
00003   * @file    Project/STM32F10x_StdPeriph_Template/stm32f10x_it.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and
00009   *          peripherals interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32f10x_it.h"
00026
00027 /** @addtogroup STM32F10x_StdPeriph_Template
00028   * @{
00029   */
00030
00031 /* Private typedef -----------------------------------------------------------*/
00032 /* Private define ------------------------------------------------------------*/
00033 /* Private macro -------------------------------------------------------------*/
00034 /* Private variables ---------------------------------------------------------*/
00035 /* Private function prototypes -----------------------------------------------*/
00036 /* Private functions ---------------------------------------------------------*/
00037
00038 /******************************************************************************/
00039 /*            Cortex-M3 Processor Exceptions Handlers                         */
00040 /******************************************************************************/
00041
00042 /**
00043   * @brief  This function handles NMI exception.
00044   * @param  None
00045   * @retval None
00046   */
00047 void NMI_Handler(void)
00048 {
00049 }
00050
00051 /**
00052   * @brief  This function handles Hard Fault exception.
00053   * @param  None
00054   * @retval None
00055   */
00056 void HardFault_Handler(void)
00057 {
00058   /* Go to infinite loop when Hard Fault exception occurs */
00059   while (1)
00060   {
00061   }
00062 }
00063
00064 /**
00065   * @brief  This function handles Memory Manage exception.
00066   * @param  None
00067   * @retval None
00068   */
00069 void MemManage_Handler(void)
00070 {
00071   /* Go to infinite loop when Memory Manage exception occurs */
00072   while (1)
00073   {
00074   }
00075 }
00076
00077 /**
00078   * @brief  This function handles Bus Fault exception.
00079   * @param  None
00080   * @retval None
00081   */
00082 void BusFault_Handler(void)
00083 {
00084   /* Go to infinite loop when Bus Fault exception occurs */
00085   while (1)
00086   {
00087   }
00088 }
00089
00090 /**
00091   * @brief  This function handles Usage Fault exception.
00092   * @param  None
00093   * @retval None
00094   */
00095 void UsageFault_Handler(void)
00096 {
00097   /* Go to infinite loop when Usage Fault exception occurs */
00098   while (1)
00099   {
00100   }
00101 }
00102
00103 /**
00104   * @brief  This function handles SVCall exception.
00105   * @param  None
00106   * @retval None
00107   */
00108 void SVC_Handler(void)
00109 {
00110 }
00111
00112 /**
00113   * @brief  This function handles Debug Monitor exception.
00114   * @param  None
00115   * @retval None
00116   */
00117 void DebugMon_Handler(void)
00118 {
00119 }
00120
00121 /**
00122   * @brief  This function handles PendSVC exception.
00123   * @param  None
00124   * @retval None
00125   */
00126 void PendSV_Handler(void)
00127 {
00128 }
00129
00130 /**
00131   * @brief  This function handles SysTick Handler.
00132   * @param  None
00133   * @retval None
00134   */
00135 void SysTick_Handler(void)
00136 {
00137 }
00138
00139 /******************************************************************************/
00140 /*                 STM32F10x Peripherals Interrupt Handlers                   */
00141 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00142 /*  available peripheral interrupt handler's name please refer to the startup */
00143 /*  file (startup_stm32f10x_xx.s).                                            */
00144 /******************************************************************************/
00145
00146 /**
00147   * @brief  This function handles PPP interrupt request.
00148   * @param  None
00149   * @retval None
00150   */
00151 /*void PPP_IRQHandler(void)
00152 {
00153 }*/
00154
00155 /**
00156   * @}
00157   */
00158
00159
00160 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_it.h Source File

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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Template

STM32F10x_StdPeriph_Template/stm32f10x_it.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    Project/STM32F10x_StdPeriph_Template/stm32f10x_it.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   This file contains the headers of the interrupt handlers.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32F10x_IT_H
00024 #define __STM32F10x_IT_H
00025
00026 #ifdef __cplusplus
00027  extern "C" {
00028 #endif
00029
00030 /* Includes ------------------------------------------------------------------*/
00031 #include "stm32f10x.h"
00032
00033 /* Exported types ------------------------------------------------------------*/
00034 /* Exported constants --------------------------------------------------------*/
00035 /* Exported macro ------------------------------------------------------------*/
00036 /* Exported functions ------------------------------------------------------- */
00037
00038 void NMI_Handler(void);
00039 void HardFault_Handler(void);
00040 void MemManage_Handler(void);
00041 void BusFault_Handler(void);
00042 void UsageFault_Handler(void);
00043 void SVC_Handler(void);
00044 void DebugMon_Handler(void);
00045 void PendSV_Handler(void);
00046 void SysTick_Handler(void);
00047
00048 #ifdef __cplusplus
00049 }
00050 #endif
00051
00052 #endif /* __STM32F10x_IT_H */
00053
00054 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_tim.c Source File

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  • STM32F10x_StdPeriph_Lib_V3.5.0
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  • src

stm32f10x_tim.c

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f10x_tim.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    11-March-2011
00007   * @brief   This file provides all the TIM firmware functions.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x_tim.h"
00024 #include "stm32f10x_rcc.h"
00025
00026 /** @addtogroup STM32F10x_StdPeriph_Driver
00027   * @{
00028   */
00029
00030 /** @defgroup TIM
00031   * @brief TIM driver modules
00032   * @{
00033   */
00034
00035 /** @defgroup TIM_Private_TypesDefinitions
00036   * @{
00037   */
00038
00039 /**
00040   * @}
00041   */
00042
00043 /** @defgroup TIM_Private_Defines
00044   * @{
00045   */
00046
00047 /* ---------------------- TIM registers bit mask ------------------------ */
00048 #define SMCR_ETR_Mask               ((uint16_t)0x00FF)
00049 #define CCMR_Offset                 ((uint16_t)0x0018)
00050 #define CCER_CCE_Set                ((uint16_t)0x0001)
00051 #define CCER_CCNE_Set               ((uint16_t)0x0004)
00052
00053 /**
00054   * @}
00055   */
00056
00057 /** @defgroup TIM_Private_Macros
00058   * @{
00059   */
00060
00061 /**
00062   * @}
00063   */
00064
00065 /** @defgroup TIM_Private_Variables
00066   * @{
00067   */
00068
00069 /**
00070   * @}
00071   */
00072
00073 /** @defgroup TIM_Private_FunctionPrototypes
00074   * @{
00075   */
00076
00077 static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
00078                        uint16_t TIM_ICFilter);
00079 static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
00080                        uint16_t TIM_ICFilter);
00081 static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
00082                        uint16_t TIM_ICFilter);
00083 static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
00084                        uint16_t TIM_ICFilter);
00085 /**
00086   * @}
00087   */
00088
00089 /** @defgroup TIM_Private_Macros
00090   * @{
00091   */
00092
00093 /**
00094   * @}
00095   */
00096
00097 /** @defgroup TIM_Private_Variables
00098   * @{
00099   */
00100
00101 /**
00102   * @}
00103   */
00104
00105 /** @defgroup TIM_Private_FunctionPrototypes
00106   * @{
00107   */
00108
00109 /**
00110   * @}
00111   */
00112
00113 /** @defgroup TIM_Private_Functions
00114   * @{
00115   */
00116
00117 /**
00118   * @brief  Deinitializes the TIMx peripheral registers to their default reset values.
00119   * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
00120   * @retval None
00121   */
00122 void TIM_DeInit(TIM_TypeDef* TIMx)
00123 {
00124   /* Check the parameters */
00125   assert_param(IS_TIM_ALL_PERIPH(TIMx));
00126
00127   if (TIMx == TIM1)
00128   {
00129     RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE);
00130     RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE);
00131   }
00132   else if (TIMx == TIM2)
00133   {
00134     RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE);
00135     RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE);
00136   }
00137   else if (TIMx == TIM3)
00138   {
00139     RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE);
00140     RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE);
00141   }
00142   else if (TIMx == TIM4)
00143   {
00144     RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE);
00145     RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE);
00146   }
00147   else if (TIMx == TIM5)
00148   {
00149     RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE);
00150     RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE);
00151   }
00152   else if (TIMx == TIM6)
00153   {
00154     RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE);
00155     RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE);
00156   }
00157   else if (TIMx == TIM7)
00158   {
00159     RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE);
00160     RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE);
00161   }
00162   else if (TIMx == TIM8)
00163   {
00164     RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE);
00165     RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE);
00166   }
00167   else if (TIMx == TIM9)
00168   {
00169     RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, ENABLE);
00170     RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, DISABLE);
00171    }
00172   else if (TIMx == TIM10)
00173   {
00174     RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, ENABLE);
00175     RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, DISABLE);
00176   }
00177   else if (TIMx == TIM11)
00178   {
00179     RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, ENABLE);
00180     RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, DISABLE);
00181   }
00182   else if (TIMx == TIM12)
00183   {
00184     RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, ENABLE);
00185     RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, DISABLE);
00186   }
00187   else if (TIMx == TIM13)
00188   {
00189     RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, ENABLE);
00190     RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, DISABLE);
00191   }
00192   else if (TIMx == TIM14)
00193   {
00194     RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, ENABLE);
00195     RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, DISABLE);
00196   }
00197   else if (TIMx == TIM15)
00198   {
00199     RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, ENABLE);
00200     RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, DISABLE);
00201   }
00202   else if (TIMx == TIM16)
00203   {
00204     RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, ENABLE);
00205     RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, DISABLE);
00206   }
00207   else
00208   {
00209     if (TIMx == TIM17)
00210     {
00211       RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, ENABLE);
00212       RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, DISABLE);
00213     }
00214   }
00215 }
00216
00217 /**
00218   * @brief  Initializes the TIMx Time Base Unit peripheral according to
00219   *         the specified parameters in the TIM_TimeBaseInitStruct.
00220   * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
00221   * @param  TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef
00222   *         structure that contains the configuration information for the
00223   *         specified TIM peripheral.
00224   * @retval None
00225   */
00226 void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
00227 {
00228   uint16_t tmpcr1 = 0;
00229
00230   /* Check the parameters */
00231   assert_param(IS_TIM_ALL_PERIPH(TIMx));
00232   assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode));
00233   assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision));
00234
00235   tmpcr1 = TIMx->CR1;
00236
00237   if((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM2) || (TIMx == TIM3)||
00238      (TIMx == TIM4) || (TIMx == TIM5))
00239   {
00240     /* Select the Counter Mode */
00241     tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS)));
00242     tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode;
00243   }
00244
00245   if((TIMx != TIM6) && (TIMx != TIM7))
00246   {
00247     /* Set the clock division */
00248     tmpcr1 &= (uint16_t)(~((uint16_t)TIM_CR1_CKD));
00249     tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision;
00250   }
00251
00252   TIMx->CR1 = tmpcr1;
00253
00254   /* Set the Autoreload value */
00255   TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ;
00256
00257   /* Set the Prescaler value */
00258   TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler;
00259
00260   if ((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM15)|| (TIMx == TIM16) || (TIMx == TIM17))
00261   {
00262     /* Set the Repetition Counter value */
00263     TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter;
00264   }
00265
00266   /* Generate an update event to reload the Prescaler and the Repetition counter
00267      values immediately */
00268   TIMx->EGR = TIM_PSCReloadMode_Immediate;
00269 }
00270
00271 /**
00272   * @brief  Initializes the TIMx Channel1 according to the specified
00273   *         parameters in the TIM_OCInitStruct.
00274   * @param  TIMx: where x can be  1 to 17 except 6 and 7 to select the TIM peripheral.
00275   * @param  TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
00276   *         that contains the configuration information for the specified TIM peripheral.
00277   * @retval None
00278   */
00279 void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
00280 {
00281   uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
00282
00283   /* Check the parameters */
00284   assert_param(IS_TIM_LIST8_PERIPH(TIMx));
00285   assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
00286   assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
00287   assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
00288  /* Disable the Channel 1: Reset the CC1E Bit */
00289   TIMx->CCER &= (uint16_t)(~(uint16_t)TIM_CCER_CC1E);
00290   /* Get the TIMx CCER register value */
00291   tmpccer = TIMx->CCER;
00292   /* Get the TIMx CR2 register value */
00293   tmpcr2 =  TIMx->CR2;
00294
00295   /* Get the TIMx CCMR1 register value */
00296   tmpccmrx = TIMx->CCMR1;
00297
00298   /* Reset the Output Compare Mode Bits */
00299   tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC1M));
00300   tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC1S));
00301
00302   /* Select the Output Compare Mode */
00303   tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
00304
00305   /* Reset the Output Polarity level */
00306   tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1P));
00307   /* Set the Output Compare Polarity */
00308   tmpccer |= TIM_OCInitStruct->TIM_OCPolarity;
00309
00310   /* Set the Output State */
00311   tmpccer |= TIM_OCInitStruct->TIM_OutputState;
00312
00313   if((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM15)||
00314      (TIMx == TIM16)|| (TIMx == TIM17))
00315   {
00316     assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
00317     assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
00318     assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
00319     assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
00320
00321     /* Reset the Output N Polarity level */
00322     tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NP));
00323     /* Set the Output N Polarity */
00324     tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity;
00325
00326     /* Reset the Output N State */
00327     tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NE));
00328     /* Set the Output N State */
00329     tmpccer |= TIM_OCInitStruct->TIM_OutputNState;
00330
00331     /* Reset the Output Compare and Output Compare N IDLE State */
00332     tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1));
00333     tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1N));
00334
00335     /* Set the Output Idle state */
00336     tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState;
00337     /* Set the Output N Idle state */
00338     tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState;
00339   }
00340   /* Write to TIMx CR2 */
00341   TIMx->CR2 = tmpcr2;
00342
00343   /* Write to TIMx CCMR1 */
00344   TIMx->CCMR1 = tmpccmrx;
00345
00346   /* Set the Capture Compare Register value */
00347   TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse;
00348
00349   /* Write to TIMx CCER */
00350   TIMx->CCER = tmpccer;
00351 }
00352
00353 /**
00354   * @brief  Initializes the TIMx Channel2 according to the specified
00355   *         parameters in the TIM_OCInitStruct.
00356   * @param  TIMx: where x can be  1, 2, 3, 4, 5, 8, 9, 12 or 15 to select
00357   *         the TIM peripheral.
00358   * @param  TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
00359   *         that contains the configuration information for the specified TIM peripheral.
00360   * @retval None
00361   */
00362 void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
00363 {
00364   uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
00365
00366   /* Check the parameters */
00367   assert_param(IS_TIM_LIST6_PERIPH(TIMx));
00368   assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
00369   assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
00370   assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
00371    /* Disable the Channel 2: Reset the CC2E Bit */
00372   TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC2E));
00373
00374   /* Get the TIMx CCER register value */
00375   tmpccer = TIMx->CCER;
00376   /* Get the TIMx CR2 register value */
00377   tmpcr2 =  TIMx->CR2;
00378
00379   /* Get the TIMx CCMR1 register value */
00380   tmpccmrx = TIMx->CCMR1;
00381
00382   /* Reset the Output Compare mode and Capture/Compare selection Bits */
00383   tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC2M));
00384   tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S));
00385
00386   /* Select the Output Compare Mode */
00387   tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
00388
00389   /* Reset the Output Polarity level */
00390   tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2P));
00391   /* Set the Output Compare Polarity */
00392   tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4);
00393
00394   /* Set the Output State */
00395   tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4);
00396
00397   if((TIMx == TIM1) || (TIMx == TIM8))
00398   {
00399     assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
00400     assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
00401     assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
00402     assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
00403
00404     /* Reset the Output N Polarity level */
00405     tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NP));
00406     /* Set the Output N Polarity */
00407     tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4);
00408
00409     /* Reset the Output N State */
00410     tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NE));
00411     /* Set the Output N State */
00412     tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4);
00413
00414     /* Reset the Output Compare and Output Compare N IDLE State */
00415     tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2));
00416     tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2N));
00417
00418     /* Set the Output Idle state */
00419     tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2);
00420     /* Set the Output N Idle state */
00421     tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2);
00422   }
00423   /* Write to TIMx CR2 */
00424   TIMx->CR2 = tmpcr2;
00425
00426   /* Write to TIMx CCMR1 */
00427   TIMx->CCMR1 = tmpccmrx;
00428
00429   /* Set the Capture Compare Register value */
00430   TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse;
00431
00432   /* Write to TIMx CCER */
00433   TIMx->CCER = tmpccer;
00434 }
00435
00436 /**
00437   * @brief  Initializes the TIMx Channel3 according to the specified
00438   *         parameters in the TIM_OCInitStruct.
00439   * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
00440   * @param  TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
00441   *         that contains the configuration information for the specified TIM peripheral.
00442   * @retval None
00443   */
00444 void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
00445 {
00446   uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
00447
00448   /* Check the parameters */
00449   assert_param(IS_TIM_LIST3_PERIPH(TIMx));
00450   assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
00451   assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
00452   assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
00453   /* Disable the Channel 2: Reset the CC2E Bit */
00454   TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC3E));
00455
00456   /* Get the TIMx CCER register value */
00457   tmpccer = TIMx->CCER;
00458   /* Get the TIMx CR2 register value */
00459   tmpcr2 =  TIMx->CR2;
00460
00461   /* Get the TIMx CCMR2 register value */
00462   tmpccmrx = TIMx->CCMR2;
00463
00464   /* Reset the Output Compare mode and Capture/Compare selection Bits */
00465   tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC3M));
00466   tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC3S));
00467   /* Select the Output Compare Mode */
00468   tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
00469
00470   /* Reset the Output Polarity level */
00471   tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3P));
00472   /* Set the Output Compare Polarity */
00473   tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8);
00474
00475   /* Set the Output State */
00476   tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8);
00477
00478   if((TIMx == TIM1) || (TIMx == TIM8))
00479   {
00480     assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
00481     assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
00482     assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
00483     assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
00484
00485     /* Reset the Output N Polarity level */
00486     tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NP));
00487     /* Set the Output N Polarity */
00488     tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8);
00489     /* Reset the Output N State */
00490     tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NE));
00491
00492     /* Set the Output N State */
00493     tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8);
00494     /* Reset the Output Compare and Output Compare N IDLE State */
00495     tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3));
00496     tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3N));
00497     /* Set the Output Idle state */
00498     tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4);
00499     /* Set the Output N Idle state */
00500     tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4);
00501   }
00502   /* Write to TIMx CR2 */
00503   TIMx->CR2 = tmpcr2;
00504
00505   /* Write to TIMx CCMR2 */
00506   TIMx->CCMR2 = tmpccmrx;
00507
00508   /* Set the Capture Compare Register value */
00509   TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse;
00510
00511   /* Write to TIMx CCER */
00512   TIMx->CCER = tmpccer;
00513 }
00514
00515 /**
00516   * @brief  Initializes the TIMx Channel4 according to the specified
00517   *         parameters in the TIM_OCInitStruct.
00518   * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
00519   * @param  TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
00520   *         that contains the configuration information for the specified TIM peripheral.
00521   * @retval None
00522   */
00523 void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
00524 {
00525   uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
00526
00527   /* Check the parameters */
00528   assert_param(IS_TIM_LIST3_PERIPH(TIMx));
00529   assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
00530   assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
00531   assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
00532   /* Disable the Channel 2: Reset the CC4E Bit */
00533   TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC4E));
00534
00535   /* Get the TIMx CCER register value */
00536   tmpccer = TIMx->CCER;
00537   /* Get the TIMx CR2 register value */
00538   tmpcr2 =  TIMx->CR2;
00539
00540   /* Get the TIMx CCMR2 register value */
00541   tmpccmrx = TIMx->CCMR2;
00542
00543   /* Reset the Output Compare mode and Capture/Compare selection Bits */
00544   tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC4M));
00545   tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC4S));
00546
00547   /* Select the Output Compare Mode */
00548   tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
00549
00550   /* Reset the Output Polarity level */
00551   tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC4P));
00552   /* Set the Output Compare Polarity */
00553   tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12);
00554
00555   /* Set the Output State */
00556   tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12);
00557
00558   if((TIMx == TIM1) || (TIMx == TIM8))
00559   {
00560     assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
00561     /* Reset the Output Compare IDLE State */
00562     tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS4));
00563     /* Set the Output Idle state */
00564     tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6);
00565   }
00566   /* Write to TIMx CR2 */
00567   TIMx->CR2 = tmpcr2;
00568
00569   /* Write to TIMx CCMR2 */
00570   TIMx->CCMR2 = tmpccmrx;
00571
00572   /* Set the Capture Compare Register value */
00573   TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse;
00574
00575   /* Write to TIMx CCER */
00576   TIMx->CCER = tmpccer;
00577 }
00578
00579 /**
00580   * @brief  Initializes the TIM peripheral according to the specified
00581   *         parameters in the TIM_ICInitStruct.
00582   * @param  TIMx: where x can be  1 to 17 except 6 and 7 to select the TIM peripheral.
00583   * @param  TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure
00584   *         that contains the configuration information for the specified TIM peripheral.
00585   * @retval None
00586   */
00587 void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
00588 {
00589   /* Check the parameters */
00590   assert_param(IS_TIM_CHANNEL(TIM_ICInitStruct->TIM_Channel));
00591   assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection));
00592   assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler));
00593   assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter));
00594
00595   if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||
00596      (TIMx == TIM4) ||(TIMx == TIM5))
00597   {
00598     assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity));
00599   }
00600   else
00601   {
00602     assert_param(IS_TIM_IC_POLARITY_LITE(TIM_ICInitStruct->TIM_ICPolarity));
00603   }
00604   if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
00605   {
00606     assert_param(IS_TIM_LIST8_PERIPH(TIMx));
00607     /* TI1 Configuration */
00608     TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
00609                TIM_ICInitStruct->TIM_ICSelection,
00610                TIM_ICInitStruct->TIM_ICFilter);
00611     /* Set the Input Capture Prescaler value */
00612     TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
00613   }
00614   else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2)
00615   {
00616     assert_param(IS_TIM_LIST6_PERIPH(TIMx));
00617     /* TI2 Configuration */
00618     TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
00619                TIM_ICInitStruct->TIM_ICSelection,
00620                TIM_ICInitStruct->TIM_ICFilter);
00621     /* Set the Input Capture Prescaler value */
00622     TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
00623   }
00624   else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3)
00625   {
00626     assert_param(IS_TIM_LIST3_PERIPH(TIMx));
00627     /* TI3 Configuration */
00628     TI3_Config(TIMx,  TIM_ICInitStruct->TIM_ICPolarity,
00629                TIM_ICInitStruct->TIM_ICSelection,
00630                TIM_ICInitStruct->TIM_ICFilter);
00631     /* Set the Input Capture Prescaler value */
00632     TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
00633   }
00634   else
00635   {
00636     assert_param(IS_TIM_LIST3_PERIPH(TIMx));
00637     /* TI4 Configuration */
00638     TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
00639                TIM_ICInitStruct->TIM_ICSelection,
00640                TIM_ICInitStruct->TIM_ICFilter);
00641     /* Set the Input Capture Prescaler value */
00642     TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
00643   }
00644 }
00645
00646 /**
00647   * @brief  Configures the TIM peripheral according to the specified
00648   *         parameters in the TIM_ICInitStruct to measure an external PWM signal.
00649   * @param  TIMx: where x can be  1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
00650   * @param  TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure
00651   *         that contains the configuration information for the specified TIM peripheral.
00652   * @retval None
00653   */
00654 void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
00655 {
00656   uint16_t icoppositepolarity = TIM_ICPolarity_Rising;
00657   uint16_t icoppositeselection = TIM_ICSelection_DirectTI;
00658   /* Check the parameters */
00659   assert_param(IS_TIM_LIST6_PERIPH(TIMx));
00660   /* Select the Opposite Input Polarity */
00661   if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising)
00662   {
00663     icoppositepolarity = TIM_ICPolarity_Falling;
00664   }
00665   else
00666   {
00667     icoppositepolarity = TIM_ICPolarity_Rising;
00668   }
00669   /* Select the Opposite Input */
00670   if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI)
00671   {
00672     icoppositeselection = TIM_ICSelection_IndirectTI;
00673   }
00674   else
00675   {
00676     icoppositeselection = TIM_ICSelection_DirectTI;
00677   }
00678   if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
00679   {
00680     /* TI1 Configuration */
00681     TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
00682                TIM_ICInitStruct->TIM_ICFilter);
00683     /* Set the Input Capture Prescaler value */
00684     TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
00685     /* TI2 Configuration */
00686     TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
00687     /* Set the Input Capture Prescaler value */
00688     TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
00689   }
00690   else
00691   {
00692     /* TI2 Configuration */
00693     TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
00694                TIM_ICInitStruct->TIM_ICFilter);
00695     /* Set the Input Capture Prescaler value */
00696     TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
00697     /* TI1 Configuration */
00698     TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
00699     /* Set the Input Capture Prescaler value */
00700     TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
00701   }
00702 }
00703
00704 /**
00705   * @brief  Configures the: Break feature, dead time, Lock level, the OSSI,
00706   *         the OSSR State and the AOE(automatic output enable).
00707   * @param  TIMx: where x can be  1 or 8 to select the TIM
00708   * @param  TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure that
00709   *         contains the BDTR Register configuration  information for the TIM peripheral.
00710   * @retval None
00711   */
00712 void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)
00713 {
00714   /* Check the parameters */
00715   assert_param(IS_TIM_LIST2_PERIPH(TIMx));
00716   assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState));
00717   assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState));
00718   assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel));
00719   assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break));
00720   assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity));
00721   assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput));
00722   /* Set the Lock level, the Break enable Bit and the Ploarity, the OSSR State,
00723      the OSSI State, the dead time value and the Automatic Output Enable Bit */
00724   TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState |
00725              TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime |
00726              TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity |
00727              TIM_BDTRInitStruct->TIM_AutomaticOutput;
00728 }
00729
00730 /**
00731   * @brief  Fills each TIM_TimeBaseInitStruct member with its default value.
00732   * @param  TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef
00733   *         structure which will be initialized.
00734   * @retval None
00735   */
00736 void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
00737 {
00738   /* Set the default configuration */
00739   TIM_TimeBaseInitStruct->TIM_Period = 0xFFFF;
00740   TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000;
00741   TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1;
00742   TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up;
00743   TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000;
00744 }
00745
00746 /**
00747   * @brief  Fills each TIM_OCInitStruct member with its default value.
00748   * @param  TIM_OCInitStruct : pointer to a TIM_OCInitTypeDef structure which will
00749   *         be initialized.
00750   * @retval None
00751   */
00752 void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct)
00753 {
00754   /* Set the default configuration */
00755   TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing;
00756   TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable;
00757   TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable;
00758   TIM_OCInitStruct->TIM_Pulse = 0x0000;
00759   TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High;
00760   TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High;
00761   TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset;
00762   TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset;
00763 }
00764
00765 /**
00766   * @brief  Fills each TIM_ICInitStruct member with its default value.
00767   * @param  TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure which will
00768   *         be initialized.
00769   * @retval None
00770   */
00771 void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct)
00772 {
00773   /* Set the default configuration */
00774   TIM_ICInitStruct->TIM_Channel = TIM_Channel_1;
00775   TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising;
00776   TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI;
00777   TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1;
00778   TIM_ICInitStruct->TIM_ICFilter = 0x00;
00779 }
00780
00781 /**
00782   * @brief  Fills each TIM_BDTRInitStruct member with its default value.
00783   * @param  TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure which
00784   *         will be initialized.
00785   * @retval None
00786   */
00787 void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct)
00788 {
00789   /* Set the default configuration */
00790   TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable;
00791   TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable;
00792   TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF;
00793   TIM_BDTRInitStruct->TIM_DeadTime = 0x00;
00794   TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable;
00795   TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low;
00796   TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable;
00797 }
00798
00799 /**
00800   * @brief  Enables or disables the specified TIM peripheral.
00801   * @param  TIMx: where x can be 1 to 17 to select the TIMx peripheral.
00802   * @param  NewState: new state of the TIMx peripheral.
00803   *   This parameter can be: ENABLE or DISABLE.
00804   * @retval None
00805   */
00806 void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState)
00807 {
00808   /* Check the parameters */
00809   assert_param(IS_TIM_ALL_PERIPH(TIMx));
00810   assert_param(IS_FUNCTIONAL_STATE(NewState));
00811
00812   if (NewState != DISABLE)
00813   {
00814     /* Enable the TIM Counter */
00815     TIMx->CR1 |= TIM_CR1_CEN;
00816   }
00817   else
00818   {
00819     /* Disable the TIM Counter */
00820     TIMx->CR1 &= (uint16_t)(~((uint16_t)TIM_CR1_CEN));
00821   }
00822 }
00823
00824 /**
00825   * @brief  Enables or disables the TIM peripheral Main Outputs.
00826   * @param  TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIMx peripheral.
00827   * @param  NewState: new state of the TIM peripheral Main Outputs.
00828   *   This parameter can be: ENABLE or DISABLE.
00829   * @retval None
00830   */
00831 void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState)
00832 {
00833   /* Check the parameters */
00834   assert_param(IS_TIM_LIST2_PERIPH(TIMx));
00835   assert_param(IS_FUNCTIONAL_STATE(NewState));
00836   if (NewState != DISABLE)
00837   {
00838     /* Enable the TIM Main Output */
00839     TIMx->BDTR |= TIM_BDTR_MOE;
00840   }
00841   else
00842   {
00843     /* Disable the TIM Main Output */
00844     TIMx->BDTR &= (uint16_t)(~((uint16_t)TIM_BDTR_MOE));
00845   }
00846 }
00847
00848 /**
00849   * @brief  Enables or disables the specified TIM interrupts.
00850   * @param  TIMx: where x can be 1 to 17 to select the TIMx peripheral.
00851   * @param  TIM_IT: specifies the TIM interrupts sources to be enabled or disabled.
00852   *   This parameter can be any combination of the following values:
00853   *     @arg TIM_IT_Update: TIM update Interrupt source
00854   *     @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
00855   *     @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
00856   *     @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
00857   *     @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
00858   *     @arg TIM_IT_COM: TIM Commutation Interrupt source
00859   *     @arg TIM_IT_Trigger: TIM Trigger Interrupt source
00860   *     @arg TIM_IT_Break: TIM Break Interrupt source
00861   * @note
00862   *   - TIM6 and TIM7 can only generate an update interrupt.
00863   *   - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1,
00864   *      TIM_IT_CC2 or TIM_IT_Trigger.
00865   *   - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1.
00866   *   - TIM_IT_Break is used only with TIM1, TIM8 and TIM15.
00867   *   - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17.
00868   * @param  NewState: new state of the TIM interrupts.
00869   *   This parameter can be: ENABLE or DISABLE.
00870   * @retval None
00871   */
00872 void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState)
00873 {
00874   /* Check the parameters */
00875   assert_param(IS_TIM_ALL_PERIPH(TIMx));
00876   assert_param(IS_TIM_IT(TIM_IT));
00877   assert_param(IS_FUNCTIONAL_STATE(NewState));
00878
00879   if (NewState != DISABLE)
00880   {
00881     /* Enable the Interrupt sources */
00882     TIMx->DIER |= TIM_IT;
00883   }
00884   else
00885   {
00886     /* Disable the Interrupt sources */
00887     TIMx->DIER &= (uint16_t)~TIM_IT;
00888   }
00889 }
00890
00891 /**
00892   * @brief  Configures the TIMx event to be generate by software.
00893   * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
00894   * @param  TIM_EventSource: specifies the event source.
00895   *   This parameter can be one or more of the following values:
00896   *     @arg TIM_EventSource_Update: Timer update Event source
00897   *     @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source
00898   *     @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source
00899   *     @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source
00900   *     @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source
00901   *     @arg TIM_EventSource_COM: Timer COM event source
00902   *     @arg TIM_EventSource_Trigger: Timer Trigger Event source
00903   *     @arg TIM_EventSource_Break: Timer Break event source
00904   * @note
00905   *   - TIM6 and TIM7 can only generate an update event.
00906   *   - TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1 and TIM8.
00907   * @retval None
00908   */
00909 void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource)
00910 {
00911   /* Check the parameters */
00912   assert_param(IS_TIM_ALL_PERIPH(TIMx));
00913   assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource));
00914
00915   /* Set the event sources */
00916   TIMx->EGR = TIM_EventSource;
00917 }
00918
00919 /**
00920   * @brief  Configures the TIMx's DMA interface.
00921   * @param  TIMx: where x can be  1, 2, 3, 4, 5, 8, 15, 16 or 17 to select
00922   *   the TIM peripheral.
00923   * @param  TIM_DMABase: DMA Base address.
00924   *   This parameter can be one of the following values:
00925   *     @arg TIM_DMABase_CR, TIM_DMABase_CR2, TIM_DMABase_SMCR,
00926   *          TIM_DMABase_DIER, TIM1_DMABase_SR, TIM_DMABase_EGR,
00927   *          TIM_DMABase_CCMR1, TIM_DMABase_CCMR2, TIM_DMABase_CCER,
00928   *          TIM_DMABase_CNT, TIM_DMABase_PSC, TIM_DMABase_ARR,
00929   *          TIM_DMABase_RCR, TIM_DMABase_CCR1, TIM_DMABase_CCR2,
00930   *          TIM_DMABase_CCR3, TIM_DMABase_CCR4, TIM_DMABase_BDTR,
00931   *          TIM_DMABase_DCR.
00932   * @param  TIM_DMABurstLength: DMA Burst length.
00933   *   This parameter can be one value between:
00934   *   TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
00935   * @retval None
00936   */
00937 void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)
00938 {
00939   /* Check the parameters */
00940   assert_param(IS_TIM_LIST4_PERIPH(TIMx));
00941   assert_param(IS_TIM_DMA_BASE(TIM_DMABase));
00942   assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength));
00943   /* Set the DMA Base and the DMA Burst Length */
00944   TIMx->DCR = TIM_DMABase | TIM_DMABurstLength;
00945 }
00946
00947 /**
00948   * @brief  Enables or disables the TIMx's DMA Requests.
00949   * @param  TIMx: where x can be  1, 2, 3, 4, 5, 6, 7, 8, 15, 16 or 17
00950   *   to select the TIM peripheral.
00951   * @param  TIM_DMASource: specifies the DMA Request sources.
00952   *   This parameter can be any combination of the following values:
00953   *     @arg TIM_DMA_Update: TIM update Interrupt source
00954   *     @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
00955   *     @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
00956   *     @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
00957   *     @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
00958   *     @arg TIM_DMA_COM: TIM Commutation DMA source
00959   *     @arg TIM_DMA_Trigger: TIM Trigger DMA source
00960   * @param  NewState: new state of the DMA Request sources.
00961   *   This parameter can be: ENABLE or DISABLE.
00962   * @retval None
00963   */
00964 void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState)
00965 {
00966   /* Check the parameters */
00967   assert_param(IS_TIM_LIST9_PERIPH(TIMx));
00968   assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource));
00969   assert_param(IS_FUNCTIONAL_STATE(NewState));
00970
00971   if (NewState != DISABLE)
00972   {
00973     /* Enable the DMA sources */
00974     TIMx->DIER |= TIM_DMASource;
00975   }
00976   else
00977   {
00978     /* Disable the DMA sources */
00979     TIMx->DIER &= (uint16_t)~TIM_DMASource;
00980   }
00981 }
00982
00983 /**
00984   * @brief  Configures the TIMx internal Clock
00985   * @param  TIMx: where x can be  1, 2, 3, 4, 5, 8, 9, 12 or 15
00986   *         to select the TIM peripheral.
00987   * @retval None
00988   */
00989 void TIM_InternalClockConfig(TIM_TypeDef* TIMx)
00990 {
00991   /* Check the parameters */
00992   assert_param(IS_TIM_LIST6_PERIPH(TIMx));
00993   /* Disable slave mode to clock the prescaler directly with the internal clock */
00994   TIMx->SMCR &=  (uint16_t)(~((uint16_t)TIM_SMCR_SMS));
00995 }
00996
00997 /**
00998   * @brief  Configures the TIMx Internal Trigger as External Clock
00999   * @param  TIMx: where x can be  1, 2, 3, 4, 5, 9, 12 or 15 to select the TIM peripheral.
01000   * @param  TIM_ITRSource: Trigger source.
01001   *   This parameter can be one of the following values:
01002   * @param  TIM_TS_ITR0: Internal Trigger 0
01003   * @param  TIM_TS_ITR1: Internal Trigger 1
01004   * @param  TIM_TS_ITR2: Internal Trigger 2
01005   * @param  TIM_TS_ITR3: Internal Trigger 3
01006   * @retval None
01007   */
01008 void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
01009 {
01010   /* Check the parameters */
01011   assert_param(IS_TIM_LIST6_PERIPH(TIMx));
01012   assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource));
01013   /* Select the Internal Trigger */
01014   TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource);
01015   /* Select the External clock mode1 */
01016   TIMx->SMCR |= TIM_SlaveMode_External1;
01017 }
01018
01019 /**
01020   * @brief  Configures the TIMx Trigger as External Clock
01021   * @param  TIMx: where x can be  1, 2, 3, 4, 5, 9, 12 or 15 to select the TIM peripheral.
01022   * @param  TIM_TIxExternalCLKSource: Trigger source.
01023   *   This parameter can be one of the following values:
01024   *     @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector
01025   *     @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1
01026   *     @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2
01027   * @param  TIM_ICPolarity: specifies the TIx Polarity.
01028   *   This parameter can be one of the following values:
01029   *     @arg TIM_ICPolarity_Rising
01030   *     @arg TIM_ICPolarity_Falling
01031   * @param  ICFilter : specifies the filter value.
01032   *   This parameter must be a value between 0x0 and 0xF.
01033   * @retval None
01034   */
01035 void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
01036                                 uint16_t TIM_ICPolarity, uint16_t ICFilter)
01037 {
01038   /* Check the parameters */
01039   assert_param(IS_TIM_LIST6_PERIPH(TIMx));
01040   assert_param(IS_TIM_TIXCLK_SOURCE(TIM_TIxExternalCLKSource));
01041   assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity));
01042   assert_param(IS_TIM_IC_FILTER(ICFilter));
01043   /* Configure the Timer Input Clock Source */
01044   if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2)
01045   {
01046     TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
01047   }
01048   else
01049   {
01050     TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
01051   }
01052   /* Select the Trigger source */
01053   TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource);
01054   /* Select the External clock mode1 */
01055   TIMx->SMCR |= TIM_SlaveMode_External1;
01056 }
01057
01058 /**
01059   * @brief  Configures the External clock Mode1
01060   * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
01061   * @param  TIM_ExtTRGPrescaler: The external Trigger Prescaler.
01062   *   This parameter can be one of the following values:
01063   *     @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
01064   *     @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
01065   *     @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
01066   *     @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
01067   * @param  TIM_ExtTRGPolarity: The external Trigger Polarity.
01068   *   This parameter can be one of the following values:
01069   *     @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
01070   *     @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
01071   * @param  ExtTRGFilter: External Trigger Filter.
01072   *   This parameter must be a value between 0x00 and 0x0F
01073   * @retval None
01074   */
01075 void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
01076                              uint16_t ExtTRGFilter)
01077 {
01078   uint16_t tmpsmcr = 0;
01079   /* Check the parameters */
01080   assert_param(IS_TIM_LIST3_PERIPH(TIMx));
01081   assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
01082   assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
01083   assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
01084   /* Configure the ETR Clock source */
01085   TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
01086
01087   /* Get the TIMx SMCR register value */
01088   tmpsmcr = TIMx->SMCR;
01089   /* Reset the SMS Bits */
01090   tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));
01091   /* Select the External clock mode1 */
01092   tmpsmcr |= TIM_SlaveMode_External1;
01093   /* Select the Trigger selection : ETRF */
01094   tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS));
01095   tmpsmcr |= TIM_TS_ETRF;
01096   /* Write to TIMx SMCR */
01097   TIMx->SMCR = tmpsmcr;
01098 }
01099
01100 /**
01101   * @brief  Configures the External clock Mode2
01102   * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
01103   * @param  TIM_ExtTRGPrescaler: The external Trigger Prescaler.
01104   *   This parameter can be one of the following values:
01105   *     @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
01106   *     @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
01107   *     @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
01108   *     @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
01109   * @param  TIM_ExtTRGPolarity: The external Trigger Polarity.
01110   *   This parameter can be one of the following values:
01111   *     @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
01112   *     @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
01113   * @param  ExtTRGFilter: External Trigger Filter.
01114   *   This parameter must be a value between 0x00 and 0x0F
01115   * @retval None
01116   */
01117 void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
01118                              uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
01119 {
01120   /* Check the parameters */
01121   assert_param(IS_TIM_LIST3_PERIPH(TIMx));
01122   assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
01123   assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
01124   assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
01125   /* Configure the ETR Clock source */
01126   TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
01127   /* Enable the External clock mode2 */
01128   TIMx->SMCR |= TIM_SMCR_ECE;
01129 }
01130
01131 /**
01132   * @brief  Configures the TIMx External Trigger (ETR).
01133   * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
01134   * @param  TIM_ExtTRGPrescaler: The external Trigger Prescaler.
01135   *   This parameter can be one of the following values:
01136   *     @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
01137   *     @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
01138   *     @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
01139   *     @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
01140   * @param  TIM_ExtTRGPolarity: The external Trigger Polarity.
01141   *   This parameter can be one of the following values:
01142   *     @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
01143   *     @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
01144   * @param  ExtTRGFilter: External Trigger Filter.
01145   *   This parameter must be a value between 0x00 and 0x0F
01146   * @retval None
01147   */
01148 void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
01149                    uint16_t ExtTRGFilter)
01150 {
01151   uint16_t tmpsmcr = 0;
01152   /* Check the parameters */
01153   assert_param(IS_TIM_LIST3_PERIPH(TIMx));
01154   assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
01155   assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
01156   assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
01157   tmpsmcr = TIMx->SMCR;
01158   /* Reset the ETR Bits */
01159   tmpsmcr &= SMCR_ETR_Mask;
01160   /* Set the Prescaler, the Filter value and the Polarity */
01161   tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8)));
01162   /* Write to TIMx SMCR */
01163   TIMx->SMCR = tmpsmcr;
01164 }
01165
01166 /**
01167   * @brief  Configures the TIMx Prescaler.
01168   * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
01169   * @param  Prescaler: specifies the Prescaler Register value
01170   * @param  TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode
01171   *   This parameter can be one of the following values:
01172   *     @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event.
01173   *     @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediately.
01174   * @retval None
01175   */
01176 void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)
01177 {
01178   /* Check the parameters */
01179   assert_param(IS_TIM_ALL_PERIPH(TIMx));
01180   assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode));
01181   /* Set the Prescaler value */
01182   TIMx->PSC = Prescaler;
01183   /* Set or reset the UG Bit */
01184   TIMx->EGR = TIM_PSCReloadMode;
01185 }
01186
01187 /**
01188   * @brief  Specifies the TIMx Counter Mode to be used.
01189   * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
01190   * @param  TIM_CounterMode: specifies the Counter Mode to be used
01191   *   This parameter can be one of the following values:
01192   *     @arg TIM_CounterMode_Up: TIM Up Counting Mode
01193   *     @arg TIM_CounterMode_Down: TIM Down Counting Mode
01194   *     @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1
01195   *     @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2
01196   *     @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3
01197   * @retval None
01198   */
01199 void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode)
01200 {
01201   uint16_t tmpcr1 = 0;
01202   /* Check the parameters */
01203   assert_param(IS_TIM_LIST3_PERIPH(TIMx));
01204   assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode));
01205   tmpcr1 = TIMx->CR1;
01206   /* Reset the CMS and DIR Bits */
01207   tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS)));
01208   /* Set the Counter Mode */
01209   tmpcr1 |= TIM_CounterMode;
01210   /* Write to TIMx CR1 register */
01211   TIMx->CR1 = tmpcr1;
01212 }
01213
01214 /**
01215   * @brief  Selects the Input Trigger source
01216   * @param  TIMx: where x can be  1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
01217   * @param  TIM_InputTriggerSource: The Input Trigger source.
01218   *   This parameter can be one of the following values:
01219   *     @arg TIM_TS_ITR0: Internal Trigger 0
01220   *     @arg TIM_TS_ITR1: Internal Trigger 1
01221   *     @arg TIM_TS_ITR2: Internal Trigger 2
01222   *     @arg TIM_TS_ITR3: Internal Trigger 3
01223   *     @arg TIM_TS_TI1F_ED: TI1 Edge Detector
01224   *     @arg TIM_TS_TI1FP1: Filtered Timer Input 1
01225   *     @arg TIM_TS_TI2FP2: Filtered Timer Input 2
01226   *     @arg TIM_TS_ETRF: External Trigger input
01227   * @retval None
01228   */
01229 void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
01230 {
01231   uint16_t tmpsmcr = 0;
01232   /* Check the parameters */
01233   assert_param(IS_TIM_LIST6_PERIPH(TIMx));
01234   assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource));
01235   /* Get the TIMx SMCR register value */
01236   tmpsmcr = TIMx->SMCR;
01237   /* Reset the TS Bits */
01238   tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS));
01239   /* Set the Input Trigger source */
01240   tmpsmcr |= TIM_InputTriggerSource;
01241   /* Write to TIMx SMCR */
01242   TIMx->SMCR = tmpsmcr;
01243 }
01244
01245 /**
01246   * @brief  Configures the TIMx Encoder Interface.
01247   * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
01248   * @param  TIM_EncoderMode: specifies the TIMx Encoder Mode.
01249   *   This parameter can be one of the following values:
01250   *     @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level.
01251   *     @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level.
01252   *     @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending
01253   *                                on the level of the other input.
01254   * @param  TIM_IC1Polarity: specifies the IC1 Polarity
01255   *   This parameter can be one of the following values:
01256   *     @arg TIM_ICPolarity_Falling: IC Falling edge.
01257   *     @arg TIM_ICPolarity_Rising: IC Rising edge.
01258   * @param  TIM_IC2Polarity: specifies the IC2 Polarity
01259   *   This parameter can be one of the following values:
01260   *     @arg TIM_ICPolarity_Falling: IC Falling edge.
01261   *     @arg TIM_ICPolarity_Rising: IC Rising edge.
01262   * @retval None
01263   */
01264 void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
01265                                 uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity)
01266 {
01267   uint16_t tmpsmcr = 0;
01268   uint16_t tmpccmr1 = 0;
01269   uint16_t tmpccer = 0;
01270
01271   /* Check the parameters */
01272   assert_param(IS_TIM_LIST5_PERIPH(TIMx));
01273   assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode));
01274   assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity));
01275   assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity));
01276
01277   /* Get the TIMx SMCR register value */
01278   tmpsmcr = TIMx->SMCR;
01279
01280   /* Get the TIMx CCMR1 register value */
01281   tmpccmr1 = TIMx->CCMR1;
01282
01283   /* Get the TIMx CCER register value */
01284   tmpccer = TIMx->CCER;
01285
01286   /* Set the encoder Mode */
01287   tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));
01288   tmpsmcr |= TIM_EncoderMode;
01289
01290   /* Select the Capture Compare 1 and the Capture Compare 2 as input */
01291   tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S)));
01292   tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0;
01293
01294   /* Set the TI1 and the TI2 Polarities */
01295   tmpccer &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCER_CC1P)) & ((uint16_t)~((uint16_t)TIM_CCER_CC2P)));
01296   tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4));
01297
01298   /* Write to TIMx SMCR */
01299   TIMx->SMCR = tmpsmcr;
01300   /* Write to TIMx CCMR1 */
01301   TIMx->CCMR1 = tmpccmr1;
01302   /* Write to TIMx CCER */
01303   TIMx->CCER = tmpccer;
01304 }
01305
01306 /**
01307   * @brief  Forces the TIMx output 1 waveform to active or inactive level.
01308   * @param  TIMx: where x can be  1 to 17 except 6 and 7 to select the TIM peripheral.
01309   * @param  TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
01310   *   This parameter can be one of the following values:
01311   *     @arg TIM_ForcedAction_Active: Force active level on OC1REF
01312   *     @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF.
01313   * @retval None
01314   */
01315 void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
01316 {
01317   uint16_t tmpccmr1 = 0;
01318   /* Check the parameters */
01319   assert_param(IS_TIM_LIST8_PERIPH(TIMx));
01320   assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
01321   tmpccmr1 = TIMx->CCMR1;
01322   /* Reset the OC1M Bits */
01323   tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1M);
01324   /* Configure The Forced output Mode */
01325   tmpccmr1 |= TIM_ForcedAction;
01326   /* Write to TIMx CCMR1 register */
01327   TIMx->CCMR1 = tmpccmr1;
01328 }
01329
01330 /**
01331   * @brief  Forces the TIMx output 2 waveform to active or inactive level.
01332   * @param  TIMx: where x can be  1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
01333   * @param  TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
01334   *   This parameter can be one of the following values:
01335   *     @arg TIM_ForcedAction_Active: Force active level on OC2REF
01336   *     @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF.
01337   * @retval None
01338   */
01339 void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
01340 {
01341   uint16_t tmpccmr1 = 0;
01342   /* Check the parameters */
01343   assert_param(IS_TIM_LIST6_PERIPH(TIMx));
01344   assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
01345   tmpccmr1 = TIMx->CCMR1;
01346   /* Reset the OC2M Bits */
01347   tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2M);
01348   /* Configure The Forced output Mode */
01349   tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8);
01350   /* Write to TIMx CCMR1 register */
01351   TIMx->CCMR1 = tmpccmr1;
01352 }
01353
01354 /**
01355   * @brief  Forces the TIMx output 3 waveform to active or inactive level.
01356   * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
01357   * @param  TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
01358   *   This parameter can be one of the following values:
01359   *     @arg TIM_ForcedAction_Active: Force active level on OC3REF
01360   *     @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF.
01361   * @retval None
01362   */
01363 void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
01364 {
01365   uint16_t tmpccmr2 = 0;
01366   /* Check the parameters */
01367   assert_param(IS_TIM_LIST3_PERIPH(TIMx));
01368   assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
01369   tmpccmr2 = TIMx->CCMR2;
01370   /* Reset the OC1M Bits */
01371   tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3M);
01372   /* Configure The Forced output Mode */
01373   tmpccmr2 |= TIM_ForcedAction;
01374   /* Write to TIMx CCMR2 register */
01375   TIMx->CCMR2 = tmpccmr2;
01376 }
01377
01378 /**
01379   * @brief  Forces the TIMx output 4 waveform to active or inactive level.
01380   * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
01381   * @param  TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
01382   *   This parameter can be one of the following values:
01383   *     @arg TIM_ForcedAction_Active: Force active level on OC4REF
01384   *     @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF.
01385   * @retval None
01386   */
01387 void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
01388 {
01389   uint16_t tmpccmr2 = 0;
01390   /* Check the parameters */
01391   assert_param(IS_TIM_LIST3_PERIPH(TIMx));
01392   assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
01393   tmpccmr2 = TIMx->CCMR2;
01394   /* Reset the OC2M Bits */
01395   tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4M);
01396   /* Configure The Forced output Mode */
01397   tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8);
01398   /* Write to TIMx CCMR2 register */
01399   TIMx->CCMR2 = tmpccmr2;
01400 }
01401
01402 /**
01403   * @brief  Enables or disables TIMx peripheral Preload register on ARR.
01404   * @param  TIMx: where x can be  1 to 17 to select the TIM peripheral.
01405   * @param  NewState: new state of the TIMx peripheral Preload register
01406   *   This parameter can be: ENABLE or DISABLE.
01407   * @retval None
01408   */
01409 void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
01410 {
01411   /* Check the parameters */
01412   assert_param(IS_TIM_ALL_PERIPH(TIMx));
01413   assert_param(IS_FUNCTIONAL_STATE(NewState));
01414   if (NewState != DISABLE)
01415   {
01416     /* Set the ARR Preload Bit */
01417     TIMx->CR1 |= TIM_CR1_ARPE;
01418   }
01419   else
01420   {
01421     /* Reset the ARR Preload Bit */
01422     TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_ARPE);
01423   }
01424 }
01425
01426 /**
01427   * @brief  Selects the TIM peripheral Commutation event.
01428   * @param  TIMx: where x can be  1, 8, 15, 16 or 17 to select the TIMx peripheral
01429   * @param  NewState: new state of the Commutation event.
01430   *   This parameter can be: ENABLE or DISABLE.
01431   * @retval None
01432   */
01433 void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState)
01434 {
01435   /* Check the parameters */
01436   assert_param(IS_TIM_LIST2_PERIPH(TIMx));
01437   assert_param(IS_FUNCTIONAL_STATE(NewState));
01438   if (NewState != DISABLE)
01439   {
01440     /* Set the COM Bit */
01441     TIMx->CR2 |= TIM_CR2_CCUS;
01442   }
01443   else
01444   {
01445     /* Reset the COM Bit */
01446     TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCUS);
01447   }
01448 }
01449
01450 /**
01451   * @brief  Selects the TIMx peripheral Capture Compare DMA source.
01452   * @param  TIMx: where x can be  1, 2, 3, 4, 5, 8, 15, 16 or 17 to select
01453   *         the TIM peripheral.
01454   * @param  NewState: new state of the Capture Compare DMA source
01455   *   This parameter can be: ENABLE or DISABLE.
01456   * @retval None
01457   */
01458 void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState)
01459 {
01460   /* Check the parameters */
01461   assert_param(IS_TIM_LIST4_PERIPH(TIMx));
01462   assert_param(IS_FUNCTIONAL_STATE(NewState));
01463   if (NewState != DISABLE)
01464   {
01465     /* Set the CCDS Bit */
01466     TIMx->CR2 |= TIM_CR2_CCDS;
01467   }
01468   else
01469   {
01470     /* Reset the CCDS Bit */
01471     TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCDS);
01472   }
01473 }
01474
01475 /**
01476   * @brief  Sets or Resets the TIM peripheral Capture Compare Preload Control bit.
01477   * @param  TIMx: where x can be   1, 2, 3, 4, 5, 8 or 15
01478   *         to select the TIMx peripheral
01479   * @param  NewState: new state of the Capture Compare Preload Control bit
01480   *   This parameter can be: ENABLE or DISABLE.
01481   * @retval None
01482   */
01483 void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState)
01484 {
01485   /* Check the parameters */
01486   assert_param(IS_TIM_LIST5_PERIPH(TIMx));
01487   assert_param(IS_FUNCTIONAL_STATE(NewState));
01488   if (NewState != DISABLE)
01489   {
01490     /* Set the CCPC Bit */
01491     TIMx->CR2 |= TIM_CR2_CCPC;
01492   }
01493   else
01494   {
01495     /* Reset the CCPC Bit */
01496     TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCPC);
01497   }
01498 }
01499
01500 /**
01501   * @brief  Enables or disables the TIMx peripheral Preload register on CCR1.
01502   * @param  TIMx: where x can be  1 to 17 except 6 and 7 to select the TIM peripheral.
01503   * @param  TIM_OCPreload: new state of the TIMx peripheral Preload register
01504   *   This parameter can be one of the following values:
01505   *     @arg TIM_OCPreload_Enable
01506   *     @arg TIM_OCPreload_Disable
01507   * @retval None
01508   */
01509 void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
01510 {
01511   uint16_t tmpccmr1 = 0;
01512   /* Check the parameters */
01513   assert_param(IS_TIM_LIST8_PERIPH(TIMx));
01514   assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
01515   tmpccmr1 = TIMx->CCMR1;
01516   /* Reset the OC1PE Bit */
01517   tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1PE);
01518   /* Enable or Disable the Output Compare Preload feature */
01519   tmpccmr1 |= TIM_OCPreload;
01520   /* Write to TIMx CCMR1 register */
01521   TIMx->CCMR1 = tmpccmr1;
01522 }
01523
01524 /**
01525   * @brief  Enables or disables the TIMx peripheral Preload register on CCR2.
01526   * @param  TIMx: where x can be  1, 2, 3, 4, 5, 8, 9, 12 or 15 to select
01527   *         the TIM peripheral.
01528   * @param  TIM_OCPreload: new state of the TIMx peripheral Preload register
01529   *   This parameter can be one of the following values:
01530   *     @arg TIM_OCPreload_Enable
01531   *     @arg TIM_OCPreload_Disable
01532   * @retval None
01533   */
01534 void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
01535 {
01536   uint16_t tmpccmr1 = 0;
01537   /* Check the parameters */
01538   assert_param(IS_TIM_LIST6_PERIPH(TIMx));
01539   assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
01540   tmpccmr1 = TIMx->CCMR1;
01541   /* Reset the OC2PE Bit */
01542   tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2PE);
01543   /* Enable or Disable the Output Compare Preload feature */
01544   tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8);
01545   /* Write to TIMx CCMR1 register */
01546   TIMx->CCMR1 = tmpccmr1;
01547 }
01548
01549 /**
01550   * @brief  Enables or disables the TIMx peripheral Preload register on CCR3.
01551   * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
01552   * @param  TIM_OCPreload: new state of the TIMx peripheral Preload register
01553   *   This parameter can be one of the following values:
01554   *     @arg TIM_OCPreload_Enable
01555   *     @arg TIM_OCPreload_Disable
01556   * @retval None
01557   */
01558 void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
01559 {
01560   uint16_t tmpccmr2 = 0;
01561   /* Check the parameters */
01562   assert_param(IS_TIM_LIST3_PERIPH(TIMx));
01563   assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
01564   tmpccmr2 = TIMx->CCMR2;
01565   /* Reset the OC3PE Bit */
01566   tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3PE);
01567   /* Enable or Disable the Output Compare Preload feature */
01568   tmpccmr2 |= TIM_OCPreload;
01569   /* Write to TIMx CCMR2 register */
01570   TIMx->CCMR2 = tmpccmr2;
01571 }
01572
01573 /**
01574   * @brief  Enables or disables the TIMx peripheral Preload register on CCR4.
01575   * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
01576   * @param  TIM_OCPreload: new state of the TIMx peripheral Preload register
01577   *   This parameter can be one of the following values:
01578   *     @arg TIM_OCPreload_Enable
01579   *     @arg TIM_OCPreload_Disable
01580   * @retval None
01581   */
01582 void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
01583 {
01584   uint16_t tmpccmr2 = 0;
01585   /* Check the parameters */
01586   assert_param(IS_TIM_LIST3_PERIPH(TIMx));
01587   assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
01588   tmpccmr2 = TIMx->CCMR2;
01589   /* Reset the OC4PE Bit */
01590   tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4PE);
01591   /* Enable or Disable the Output Compare Preload feature */
01592   tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8);
01593   /* Write to TIMx CCMR2 register */
01594   TIMx->CCMR2 = tmpccmr2;
01595 }
01596
01597 /**
01598   * @brief  Configures the TIMx Output Compare 1 Fast feature.
01599   * @param  TIMx: where x can be  1 to 17 except 6 and 7 to select the TIM peripheral.
01600   * @param  TIM_OCFast: new state of the Output Compare Fast Enable Bit.
01601   *   This parameter can be one of the following values:
01602   *     @arg TIM_OCFast_Enable: TIM output compare fast enable
01603   *     @arg TIM_OCFast_Disable: TIM output compare fast disable
01604   * @retval None
01605   */
01606 void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
01607 {
01608   uint16_t tmpccmr1 = 0;
01609   /* Check the parameters */
01610   assert_param(IS_TIM_LIST8_PERIPH(TIMx));
01611   assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
01612   /* Get the TIMx CCMR1 register value */
01613   tmpccmr1 = TIMx->CCMR1;
01614   /* Reset the OC1FE Bit */
01615   tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1FE);
01616   /* Enable or Disable the Output Compare Fast Bit */
01617   tmpccmr1 |= TIM_OCFast;
01618   /* Write to TIMx CCMR1 */
01619   TIMx->CCMR1 = tmpccmr1;
01620 }
01621
01622 /**
01623   * @brief  Configures the TIMx Output Compare 2 Fast feature.
01624   * @param  TIMx: where x can be  1, 2, 3, 4, 5, 8, 9, 12 or 15 to select
01625   *         the TIM peripheral.
01626   * @param  TIM_OCFast: new state of the Output Compare Fast Enable Bit.
01627   *   This parameter can be one of the following values:
01628   *     @arg TIM_OCFast_Enable: TIM output compare fast enable
01629   *     @arg TIM_OCFast_Disable: TIM output compare fast disable
01630   * @retval None
01631   */
01632 void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
01633 {
01634   uint16_t tmpccmr1 = 0;
01635   /* Check the parameters */
01636   assert_param(IS_TIM_LIST6_PERIPH(TIMx));
01637   assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
01638   /* Get the TIMx CCMR1 register value */
01639   tmpccmr1 = TIMx->CCMR1;
01640   /* Reset the OC2FE Bit */
01641   tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2FE);
01642   /* Enable or Disable the Output Compare Fast Bit */
01643   tmpccmr1 |= (uint16_t)(TIM_OCFast << 8);
01644   /* Write to TIMx CCMR1 */
01645   TIMx->CCMR1 = tmpccmr1;
01646 }
01647
01648 /**
01649   * @brief  Configures the TIMx Output Compare 3 Fast feature.
01650   * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
01651   * @param  TIM_OCFast: new state of the Output Compare Fast Enable Bit.
01652   *   This parameter can be one of the following values:
01653   *     @arg TIM_OCFast_Enable: TIM output compare fast enable
01654   *     @arg TIM_OCFast_Disable: TIM output compare fast disable
01655   * @retval None
01656   */
01657 void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
01658 {
01659   uint16_t tmpccmr2 = 0;
01660   /* Check the parameters */
01661   assert_param(IS_TIM_LIST3_PERIPH(TIMx));
01662   assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
01663   /* Get the TIMx CCMR2 register value */
01664   tmpccmr2 = TIMx->CCMR2;
01665   /* Reset the OC3FE Bit */
01666   tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3FE);
01667   /* Enable or Disable the Output Compare Fast Bit */
01668   tmpccmr2 |= TIM_OCFast;
01669   /* Write to TIMx CCMR2 */
01670   TIMx->CCMR2 = tmpccmr2;
01671 }
01672
01673 /**
01674   * @brief  Configures the TIMx Output Compare 4 Fast feature.
01675   * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
01676   * @param  TIM_OCFast: new state of the Output Compare Fast Enable Bit.
01677   *   This parameter can be one of the following values:
01678   *     @arg TIM_OCFast_Enable: TIM output compare fast enable
01679   *     @arg TIM_OCFast_Disable: TIM output compare fast disable
01680   * @retval None
01681   */
01682 void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
01683 {
01684   uint16_t tmpccmr2 = 0;
01685   /* Check the parameters */
01686   assert_param(IS_TIM_LIST3_PERIPH(TIMx));
01687   assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
01688   /* Get the TIMx CCMR2 register value */
01689   tmpccmr2 = TIMx->CCMR2;
01690   /* Reset the OC4FE Bit */
01691   tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4FE);
01692   /* Enable or Disable the Output Compare Fast Bit */
01693   tmpccmr2 |= (uint16_t)(TIM_OCFast << 8);
01694   /* Write to TIMx CCMR2 */
01695   TIMx->CCMR2 = tmpccmr2;
01696 }
01697
01698 /**
01699   * @brief  Clears or safeguards the OCREF1 signal on an external event
01700   * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
01701   * @param  TIM_OCClear: new state of the Output Compare Clear Enable Bit.
01702   *   This parameter can be one of the following values:
01703   *     @arg TIM_OCClear_Enable: TIM Output clear enable
01704   *     @arg TIM_OCClear_Disable: TIM Output clear disable
01705   * @retval None
01706   */
01707 void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
01708 {
01709   uint16_t tmpccmr1 = 0;
01710   /* Check the parameters */
01711   assert_param(IS_TIM_LIST3_PERIPH(TIMx));
01712   assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
01713
01714   tmpccmr1 = TIMx->CCMR1;
01715
01716   /* Reset the OC1CE Bit */
01717   tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1CE);
01718   /* Enable or Disable the Output Compare Clear Bit */
01719   tmpccmr1 |= TIM_OCClear;
01720   /* Write to TIMx CCMR1 register */
01721   TIMx->CCMR1 = tmpccmr1;
01722 }
01723
01724 /**
01725   * @brief  Clears or safeguards the OCREF2 signal on an external event
01726   * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
01727   * @param  TIM_OCClear: new state of the Output Compare Clear Enable Bit.
01728   *   This parameter can be one of the following values:
01729   *     @arg TIM_OCClear_Enable: TIM Output clear enable
01730   *     @arg TIM_OCClear_Disable: TIM Output clear disable
01731   * @retval None
01732   */
01733 void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
01734 {
01735   uint16_t tmpccmr1 = 0;
01736   /* Check the parameters */
01737   assert_param(IS_TIM_LIST3_PERIPH(TIMx));
01738   assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
01739   tmpccmr1 = TIMx->CCMR1;
01740   /* Reset the OC2CE Bit */
01741   tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2CE);
01742   /* Enable or Disable the Output Compare Clear Bit */
01743   tmpccmr1 |= (uint16_t)(TIM_OCClear << 8);
01744   /* Write to TIMx CCMR1 register */
01745   TIMx->CCMR1 = tmpccmr1;
01746 }
01747
01748 /**
01749   * @brief  Clears or safeguards the OCREF3 signal on an external event
01750   * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
01751   * @param  TIM_OCClear: new state of the Output Compare Clear Enable Bit.
01752   *   This parameter can be one of the following values:
01753   *     @arg TIM_OCClear_Enable: TIM Output clear enable
01754   *     @arg TIM_OCClear_Disable: TIM Output clear disable
01755   * @retval None
01756   */
01757 void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
01758 {
01759   uint16_t tmpccmr2 = 0;
01760   /* Check the parameters */
01761   assert_param(IS_TIM_LIST3_PERIPH(TIMx));
01762   assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
01763   tmpccmr2 = TIMx->CCMR2;
01764   /* Reset the OC3CE Bit */
01765   tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3CE);
01766   /* Enable or Disable the Output Compare Clear Bit */
01767   tmpccmr2 |= TIM_OCClear;
01768   /* Write to TIMx CCMR2 register */
01769   TIMx->CCMR2 = tmpccmr2;
01770 }
01771
01772 /**
01773   * @brief  Clears or safeguards the OCREF4 signal on an external event
01774   * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
01775   * @param  TIM_OCClear: new state of the Output Compare Clear Enable Bit.
01776   *   This parameter can be one of the following values:
01777   *     @arg TIM_OCClear_Enable: TIM Output clear enable
01778   *     @arg TIM_OCClear_Disable: TIM Output clear disable
01779   * @retval None
01780   */
01781 void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
01782 {
01783   uint16_t tmpccmr2 = 0;
01784   /* Check the parameters */
01785   assert_param(IS_TIM_LIST3_PERIPH(TIMx));
01786   assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
01787   tmpccmr2 = TIMx->CCMR2;
01788   /* Reset the OC4CE Bit */
01789   tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4CE);
01790   /* Enable or Disable the Output Compare Clear Bit */
01791   tmpccmr2 |= (uint16_t)(TIM_OCClear << 8);
01792   /* Write to TIMx CCMR2 register */
01793   TIMx->CCMR2 = tmpccmr2;
01794 }
01795
01796 /**
01797   * @brief  Configures the TIMx channel 1 polarity.
01798   * @param  TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
01799   * @param  TIM_OCPolarity: specifies the OC1 Polarity
01800   *   This parameter can be one of the following values:
01801   *     @arg TIM_OCPolarity_High: Output Compare active high
01802   *     @arg TIM_OCPolarity_Low: Output Compare active low
01803   * @retval None
01804   */
01805 void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
01806 {
01807   uint16_t tmpccer = 0;
01808   /* Check the parameters */
01809   assert_param(IS_TIM_LIST8_PERIPH(TIMx));
01810   assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
01811   tmpccer = TIMx->CCER;
01812   /* Set or Reset the CC1P Bit */
01813   tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1P);
01814   tmpccer |= TIM_OCPolarity;
01815   /* Write to TIMx CCER register */
01816   TIMx->CCER = tmpccer;
01817 }
01818
01819 /**
01820   * @brief  Configures the TIMx Channel 1N polarity.
01821   * @param  TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIM peripheral.
01822   * @param  TIM_OCNPolarity: specifies the OC1N Polarity
01823   *   This parameter can be one of the following values:
01824   *     @arg TIM_OCNPolarity_High: Output Compare active high
01825   *     @arg TIM_OCNPolarity_Low: Output Compare active low
01826   * @retval None
01827   */
01828 void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
01829 {
01830   uint16_t tmpccer = 0;
01831   /* Check the parameters */
01832   assert_param(IS_TIM_LIST2_PERIPH(TIMx));
01833   assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
01834
01835   tmpccer = TIMx->CCER;
01836   /* Set or Reset the CC1NP Bit */
01837   tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1NP);
01838   tmpccer |= TIM_OCNPolarity;
01839   /* Write to TIMx CCER register */
01840   TIMx->CCER = tmpccer;
01841 }
01842
01843 /**
01844   * @brief  Configures the TIMx channel 2 polarity.
01845   * @param  TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
01846   * @param  TIM_OCPolarity: specifies the OC2 Polarity
01847   *   This parameter can be one of the following values:
01848   *     @arg TIM_OCPolarity_High: Output Compare active high
01849   *     @arg TIM_OCPolarity_Low: Output Compare active low
01850   * @retval None
01851   */
01852 void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
01853 {
01854   uint16_t tmpccer = 0;
01855   /* Check the parameters */
01856   assert_param(IS_TIM_LIST6_PERIPH(TIMx));
01857   assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
01858   tmpccer = TIMx->CCER;
01859   /* Set or Reset the CC2P Bit */
01860   tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2P);
01861   tmpccer |= (uint16_t)(TIM_OCPolarity << 4);
01862   /* Write to TIMx CCER register */
01863   TIMx->CCER = tmpccer;
01864 }
01865
01866 /**
01867   * @brief  Configures the TIMx Channel 2N polarity.
01868   * @param  TIMx: where x can be 1 or 8 to select the TIM peripheral.
01869   * @param  TIM_OCNPolarity: specifies the OC2N Polarity
01870   *   This parameter can be one of the following values:
01871   *     @arg TIM_OCNPolarity_High: Output Compare active high
01872   *     @arg TIM_OCNPolarity_Low: Output Compare active low
01873   * @retval None
01874   */
01875 void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
01876 {
01877   uint16_t tmpccer = 0;
01878   /* Check the parameters */
01879   assert_param(IS_TIM_LIST1_PERIPH(TIMx));
01880   assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
01881
01882   tmpccer = TIMx->CCER;
01883   /* Set or Reset the CC2NP Bit */
01884   tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2NP);
01885   tmpccer |= (uint16_t)(TIM_OCNPolarity << 4);
01886   /* Write to TIMx CCER register */
01887   TIMx->CCER = tmpccer;
01888 }
01889
01890 /**
01891   * @brief  Configures the TIMx channel 3 polarity.
01892   * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
01893   * @param  TIM_OCPolarity: specifies the OC3 Polarity
01894   *   This parameter can be one of the following values:
01895   *     @arg TIM_OCPolarity_High: Output Compare active high
01896   *     @arg TIM_OCPolarity_Low: Output Compare active low
01897   * @retval None
01898   */
01899 void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
01900 {
01901   uint16_t tmpccer = 0;
01902   /* Check the parameters */
01903   assert_param(IS_TIM_LIST3_PERIPH(TIMx));
01904   assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
01905   tmpccer = TIMx->CCER;
01906   /* Set or Reset the CC3P Bit */
01907   tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3P);
01908   tmpccer |= (uint16_t)(TIM_OCPolarity << 8);
01909   /* Write to TIMx CCER register */
01910   TIMx->CCER = tmpccer;
01911 }
01912
01913 /**
01914   * @brief  Configures the TIMx Channel 3N polarity.
01915   * @param  TIMx: where x can be 1 or 8 to select the TIM peripheral.
01916   * @param  TIM_OCNPolarity: specifies the OC3N Polarity
01917   *   This parameter can be one of the following values:
01918   *     @arg TIM_OCNPolarity_High: Output Compare active high
01919   *     @arg TIM_OCNPolarity_Low: Output Compare active low
01920   * @retval None
01921   */
01922 void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
01923 {
01924   uint16_t tmpccer = 0;
01925
01926   /* Check the parameters */
01927   assert_param(IS_TIM_LIST1_PERIPH(TIMx));
01928   assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
01929
01930   tmpccer = TIMx->CCER;
01931   /* Set or Reset the CC3NP Bit */
01932   tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3NP);
01933   tmpccer |= (uint16_t)(TIM_OCNPolarity << 8);
01934   /* Write to TIMx CCER register */
01935   TIMx->CCER = tmpccer;
01936 }
01937
01938 /**
01939   * @brief  Configures the TIMx channel 4 polarity.
01940   * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
01941   * @param  TIM_OCPolarity: specifies the OC4 Polarity
01942   *   This parameter can be one of the following values:
01943   *     @arg TIM_OCPolarity_High: Output Compare active high
01944   *     @arg TIM_OCPolarity_Low: Output Compare active low
01945   * @retval None
01946   */
01947 void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
01948 {
01949   uint16_t tmpccer = 0;
01950   /* Check the parameters */
01951   assert_param(IS_TIM_LIST3_PERIPH(TIMx));
01952   assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
01953   tmpccer = TIMx->CCER;
01954   /* Set or Reset the CC4P Bit */
01955   tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC4P);
01956   tmpccer |= (uint16_t)(TIM_OCPolarity << 12);
01957   /* Write to TIMx CCER register */
01958   TIMx->CCER = tmpccer;
01959 }
01960
01961 /**
01962   * @brief  Enables or disables the TIM Capture Compare Channel x.
01963   * @param  TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
01964   * @param  TIM_Channel: specifies the TIM Channel
01965   *   This parameter can be one of the following values:
01966   *     @arg TIM_Channel_1: TIM Channel 1
01967   *     @arg TIM_Channel_2: TIM Channel 2
01968   *     @arg TIM_Channel_3: TIM Channel 3
01969   *     @arg TIM_Channel_4: TIM Channel 4
01970   * @param  TIM_CCx: specifies the TIM Channel CCxE bit new state.
01971   *   This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable.
01972   * @retval None
01973   */
01974 void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx)
01975 {
01976   uint16_t tmp = 0;
01977
01978   /* Check the parameters */
01979   assert_param(IS_TIM_LIST8_PERIPH(TIMx));
01980   assert_param(IS_TIM_CHANNEL(TIM_Channel));
01981   assert_param(IS_TIM_CCX(TIM_CCx));
01982
01983   tmp = CCER_CCE_Set << TIM_Channel;
01984
01985   /* Reset the CCxE Bit */
01986   TIMx->CCER &= (uint16_t)~ tmp;
01987
01988   /* Set or reset the CCxE Bit */
01989   TIMx->CCER |=  (uint16_t)(TIM_CCx << TIM_Channel);
01990 }
01991
01992 /**
01993   * @brief  Enables or disables the TIM Capture Compare Channel xN.
01994   * @param  TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIM peripheral.
01995   * @param  TIM_Channel: specifies the TIM Channel
01996   *   This parameter can be one of the following values:
01997   *     @arg TIM_Channel_1: TIM Channel 1
01998   *     @arg TIM_Channel_2: TIM Channel 2
01999   *     @arg TIM_Channel_3: TIM Channel 3
02000   * @param  TIM_CCxN: specifies the TIM Channel CCxNE bit new state.
02001   *   This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable.
02002   * @retval None
02003   */
02004 void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN)
02005 {
02006   uint16_t tmp = 0;
02007
02008   /* Check the parameters */
02009   assert_param(IS_TIM_LIST2_PERIPH(TIMx));
02010   assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel));
02011   assert_param(IS_TIM_CCXN(TIM_CCxN));
02012
02013   tmp = CCER_CCNE_Set << TIM_Channel;
02014
02015   /* Reset the CCxNE Bit */
02016   TIMx->CCER &= (uint16_t) ~tmp;
02017
02018   /* Set or reset the CCxNE Bit */
02019   TIMx->CCER |=  (uint16_t)(TIM_CCxN << TIM_Channel);
02020 }
02021
02022 /**
02023   * @brief  Selects the TIM Output Compare Mode.
02024   * @note   This function disables the selected channel before changing the Output
02025   *         Compare Mode.
02026   *         User has to enable this channel using TIM_CCxCmd and TIM_CCxNCmd functions.
02027   * @param  TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
02028   * @param  TIM_Channel: specifies the TIM Channel
02029   *   This parameter can be one of the following values:
02030   *     @arg TIM_Channel_1: TIM Channel 1
02031   *     @arg TIM_Channel_2: TIM Channel 2
02032   *     @arg TIM_Channel_3: TIM Channel 3
02033   *     @arg TIM_Channel_4: TIM Channel 4
02034   * @param  TIM_OCMode: specifies the TIM Output Compare Mode.
02035   *   This parameter can be one of the following values:
02036   *     @arg TIM_OCMode_Timing
02037   *     @arg TIM_OCMode_Active
02038   *     @arg TIM_OCMode_Toggle
02039   *     @arg TIM_OCMode_PWM1
02040   *     @arg TIM_OCMode_PWM2
02041   *     @arg TIM_ForcedAction_Active
02042   *     @arg TIM_ForcedAction_InActive
02043   * @retval None
02044   */
02045 void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode)
02046 {
02047   uint32_t tmp = 0;
02048   uint16_t tmp1 = 0;
02049
02050   /* Check the parameters */
02051   assert_param(IS_TIM_LIST8_PERIPH(TIMx));
02052   assert_param(IS_TIM_CHANNEL(TIM_Channel));
02053   assert_param(IS_TIM_OCM(TIM_OCMode));
02054
02055   tmp = (uint32_t) TIMx;
02056   tmp += CCMR_Offset;
02057
02058   tmp1 = CCER_CCE_Set << (uint16_t)TIM_Channel;
02059
02060   /* Disable the Channel: Reset the CCxE Bit */
02061   TIMx->CCER &= (uint16_t) ~tmp1;
02062
02063   if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3))
02064   {
02065     tmp += (TIM_Channel>>1);
02066
02067     /* Reset the OCxM bits in the CCMRx register */
02068     *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC1M);
02069
02070     /* Configure the OCxM bits in the CCMRx register */
02071     *(__IO uint32_t *) tmp |= TIM_OCMode;
02072   }
02073   else
02074   {
02075     tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1;
02076
02077     /* Reset the OCxM bits in the CCMRx register */
02078     *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC2M);
02079
02080     /* Configure the OCxM bits in the CCMRx register */
02081     *(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8);
02082   }
02083 }
02084
02085 /**
02086   * @brief  Enables or Disables the TIMx Update event.
02087   * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
02088   * @param  NewState: new state of the TIMx UDIS bit
02089   *   This parameter can be: ENABLE or DISABLE.
02090   * @retval None
02091   */
02092 void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
02093 {
02094   /* Check the parameters */
02095   assert_param(IS_TIM_ALL_PERIPH(TIMx));
02096   assert_param(IS_FUNCTIONAL_STATE(NewState));
02097   if (NewState != DISABLE)
02098   {
02099     /* Set the Update Disable Bit */
02100     TIMx->CR1 |= TIM_CR1_UDIS;
02101   }
02102   else
02103   {
02104     /* Reset the Update Disable Bit */
02105     TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_UDIS);
02106   }
02107 }
02108
02109 /**
02110   * @brief  Configures the TIMx Update Request Interrupt source.
02111   * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
02112   * @param  TIM_UpdateSource: specifies the Update source.
02113   *   This parameter can be one of the following values:
02114   *     @arg TIM_UpdateSource_Regular: Source of update is the counter overflow/underflow
02115                                        or the setting of UG bit, or an update generation
02116                                        through the slave mode controller.
02117   *     @arg TIM_UpdateSource_Global: Source of update is counter overflow/underflow.
02118   * @retval None
02119   */
02120 void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource)
02121 {
02122   /* Check the parameters */
02123   assert_param(IS_TIM_ALL_PERIPH(TIMx));
02124   assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource));
02125   if (TIM_UpdateSource != TIM_UpdateSource_Global)
02126   {
02127     /* Set the URS Bit */
02128     TIMx->CR1 |= TIM_CR1_URS;
02129   }
02130   else
02131   {
02132     /* Reset the URS Bit */
02133     TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_URS);
02134   }
02135 }
02136
02137 /**
02138   * @brief  Enables or disables the TIMx's Hall sensor interface.
02139   * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
02140   * @param  NewState: new state of the TIMx Hall sensor interface.
02141   *   This parameter can be: ENABLE or DISABLE.
02142   * @retval None
02143   */
02144 void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState)
02145 {
02146   /* Check the parameters */
02147   assert_param(IS_TIM_LIST6_PERIPH(TIMx));
02148   assert_param(IS_FUNCTIONAL_STATE(NewState));
02149   if (NewState != DISABLE)
02150   {
02151     /* Set the TI1S Bit */
02152     TIMx->CR2 |= TIM_CR2_TI1S;
02153   }
02154   else
02155   {
02156     /* Reset the TI1S Bit */
02157     TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_TI1S);
02158   }
02159 }
02160
02161 /**
02162   * @brief  Selects the TIMx's One Pulse Mode.
02163   * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
02164   * @param  TIM_OPMode: specifies the OPM Mode to be used.
02165   *   This parameter can be one of the following values:
02166   *     @arg TIM_OPMode_Single
02167   *     @arg TIM_OPMode_Repetitive
02168   * @retval None
02169   */
02170 void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode)
02171 {
02172   /* Check the parameters */
02173   assert_param(IS_TIM_ALL_PERIPH(TIMx));
02174   assert_param(IS_TIM_OPM_MODE(TIM_OPMode));
02175   /* Reset the OPM Bit */
02176   TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_OPM);
02177   /* Configure the OPM Mode */
02178   TIMx->CR1 |= TIM_OPMode;
02179 }
02180
02181 /**
02182   * @brief  Selects the TIMx Trigger Output Mode.
02183   * @param  TIMx: where x can be 1, 2, 3, 4, 5, 6, 7, 8, 9, 12 or 15 to select the TIM peripheral.
02184   * @param  TIM_TRGOSource: specifies the Trigger Output source.
02185   *   This paramter can be one of the following values:
02186   *
02187   *  - For all TIMx
02188   *     @arg TIM_TRGOSource_Reset:  The UG bit in the TIM_EGR register is used as the trigger output (TRGO).
02189   *     @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output (TRGO).
02190   *     @arg TIM_TRGOSource_Update: The update event is selected as the trigger output (TRGO).
02191   *
02192   *  - For all TIMx except TIM6 and TIM7
02193   *     @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag
02194   *                              is to be set, as soon as a capture or compare match occurs (TRGO).
02195   *     @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output (TRGO).
02196   *     @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output (TRGO).
02197   *     @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output (TRGO).
02198   *     @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output (TRGO).
02199   *
02200   * @retval None
02201   */
02202 void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource)
02203 {
02204   /* Check the parameters */
02205   assert_param(IS_TIM_LIST7_PERIPH(TIMx));
02206   assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource));
02207   /* Reset the MMS Bits */
02208   TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_MMS);
02209   /* Select the TRGO source */
02210   TIMx->CR2 |=  TIM_TRGOSource;
02211 }
02212
02213 /**
02214   * @brief  Selects the TIMx Slave Mode.
02215   * @param  TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
02216   * @param  TIM_SlaveMode: specifies the Timer Slave Mode.
02217   *   This parameter can be one of the following values:
02218   *     @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal (TRGI) re-initializes
02219   *                               the counter and triggers an update of the registers.
02220   *     @arg TIM_SlaveMode_Gated:     The counter clock is enabled when the trigger signal (TRGI) is high.
02221   *     @arg TIM_SlaveMode_Trigger:   The counter starts at a rising edge of the trigger TRGI.
02222   *     @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter.
02223   * @retval None
02224   */
02225 void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode)
02226 {
02227   /* Check the parameters */
02228   assert_param(IS_TIM_LIST6_PERIPH(TIMx));
02229   assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode));
02230  /* Reset the SMS Bits */
02231   TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_SMS);
02232   /* Select the Slave Mode */
02233   TIMx->SMCR |= TIM_SlaveMode;
02234 }
02235
02236 /**
02237   * @brief  Sets or Resets the TIMx Master/Slave Mode.
02238   * @param  TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
02239   * @param  TIM_MasterSlaveMode: specifies the Timer Master Slave Mode.
02240   *   This parameter can be one of the following values:
02241   *     @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer
02242   *                                      and its slaves (through TRGO).
02243   *     @arg TIM_MasterSlaveMode_Disable: No action
02244   * @retval None
02245   */
02246 void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode)
02247 {
02248   /* Check the parameters */
02249   assert_param(IS_TIM_LIST6_PERIPH(TIMx));
02250   assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode));
02251   /* Reset the MSM Bit */
02252   TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_MSM);
02253
02254   /* Set or Reset the MSM Bit */
02255   TIMx->SMCR |= TIM_MasterSlaveMode;
02256 }
02257
02258 /**
02259   * @brief  Sets the TIMx Counter Register value
02260   * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
02261   * @param  Counter: specifies the Counter register new value.
02262   * @retval None
02263   */
02264 void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter)
02265 {
02266   /* Check the parameters */
02267   assert_param(IS_TIM_ALL_PERIPH(TIMx));
02268   /* Set the Counter Register value */
02269   TIMx->CNT = Counter;
02270 }
02271
02272 /**
02273   * @brief  Sets the TIMx Autoreload Register value
02274   * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
02275   * @param  Autoreload: specifies the Autoreload register new value.
02276   * @retval None
02277   */
02278 void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload)
02279 {
02280   /* Check the parameters */
02281   assert_param(IS_TIM_ALL_PERIPH(TIMx));
02282   /* Set the Autoreload Register value */
02283   TIMx->ARR = Autoreload;
02284 }
02285
02286 /**
02287   * @brief  Sets the TIMx Capture Compare1 Register value
02288   * @param  TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
02289   * @param  Compare1: specifies the Capture Compare1 register new value.
02290   * @retval None
02291   */
02292 void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1)
02293 {
02294   /* Check the parameters */
02295   assert_param(IS_TIM_LIST8_PERIPH(TIMx));
02296   /* Set the Capture Compare1 Register value */
02297   TIMx->CCR1 = Compare1;
02298 }
02299
02300 /**
02301   * @brief  Sets the TIMx Capture Compare2 Register value
02302   * @param  TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
02303   * @param  Compare2: specifies the Capture Compare2 register new value.
02304   * @retval None
02305   */
02306 void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2)
02307 {
02308   /* Check the parameters */
02309   assert_param(IS_TIM_LIST6_PERIPH(TIMx));
02310   /* Set the Capture Compare2 Register value */
02311   TIMx->CCR2 = Compare2;
02312 }
02313
02314 /**
02315   * @brief  Sets the TIMx Capture Compare3 Register value
02316   * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
02317   * @param  Compare3: specifies the Capture Compare3 register new value.
02318   * @retval None
02319   */
02320 void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3)
02321 {
02322   /* Check the parameters */
02323   assert_param(IS_TIM_LIST3_PERIPH(TIMx));
02324   /* Set the Capture Compare3 Register value */
02325   TIMx->CCR3 = Compare3;
02326 }
02327
02328 /**
02329   * @brief  Sets the TIMx Capture Compare4 Register value
02330   * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
02331   * @param  Compare4: specifies the Capture Compare4 register new value.
02332   * @retval None
02333   */
02334 void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4)
02335 {
02336   /* Check the parameters */
02337   assert_param(IS_TIM_LIST3_PERIPH(TIMx));
02338   /* Set the Capture Compare4 Register value */
02339   TIMx->CCR4 = Compare4;
02340 }
02341
02342 /**
02343   * @brief  Sets the TIMx Input Capture 1 prescaler.
02344   * @param  TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
02345   * @param  TIM_ICPSC: specifies the Input Capture1 prescaler new value.
02346   *   This parameter can be one of the following values:
02347   *     @arg TIM_ICPSC_DIV1: no prescaler
02348   *     @arg TIM_ICPSC_DIV2: capture is done once every 2 events
02349   *     @arg TIM_ICPSC_DIV4: capture is done once every 4 events
02350   *     @arg TIM_ICPSC_DIV8: capture is done once every 8 events
02351   * @retval None
02352   */
02353 void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
02354 {
02355   /* Check the parameters */
02356   assert_param(IS_TIM_LIST8_PERIPH(TIMx));
02357   assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
02358   /* Reset the IC1PSC Bits */
02359   TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC1PSC);
02360   /* Set the IC1PSC value */
02361   TIMx->CCMR1 |= TIM_ICPSC;
02362 }
02363
02364 /**
02365   * @brief  Sets the TIMx Input Capture 2 prescaler.
02366   * @param  TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
02367   * @param  TIM_ICPSC: specifies the Input Capture2 prescaler new value.
02368   *   This parameter can be one of the following values:
02369   *     @arg TIM_ICPSC_DIV1: no prescaler
02370   *     @arg TIM_ICPSC_DIV2: capture is done once every 2 events
02371   *     @arg TIM_ICPSC_DIV4: capture is done once every 4 events
02372   *     @arg TIM_ICPSC_DIV8: capture is done once every 8 events
02373   * @retval None
02374   */
02375 void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
02376 {
02377   /* Check the parameters */
02378   assert_param(IS_TIM_LIST6_PERIPH(TIMx));
02379   assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
02380   /* Reset the IC2PSC Bits */
02381   TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC2PSC);
02382   /* Set the IC2PSC value */
02383   TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8);
02384 }
02385
02386 /**
02387   * @brief  Sets the TIMx Input Capture 3 prescaler.
02388   * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
02389   * @param  TIM_ICPSC: specifies the Input Capture3 prescaler new value.
02390   *   This parameter can be one of the following values:
02391   *     @arg TIM_ICPSC_DIV1: no prescaler
02392   *     @arg TIM_ICPSC_DIV2: capture is done once every 2 events
02393   *     @arg TIM_ICPSC_DIV4: capture is done once every 4 events
02394   *     @arg TIM_ICPSC_DIV8: capture is done once every 8 events
02395   * @retval None
02396   */
02397 void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
02398 {
02399   /* Check the parameters */
02400   assert_param(IS_TIM_LIST3_PERIPH(TIMx));
02401   assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
02402   /* Reset the IC3PSC Bits */
02403   TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC3PSC);
02404   /* Set the IC3PSC value */
02405   TIMx->CCMR2 |= TIM_ICPSC;
02406 }
02407
02408 /**
02409   * @brief  Sets the TIMx Input Capture 4 prescaler.
02410   * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
02411   * @param  TIM_ICPSC: specifies the Input Capture4 prescaler new value.
02412   *   This parameter can be one of the following values:
02413   *     @arg TIM_ICPSC_DIV1: no prescaler
02414   *     @arg TIM_ICPSC_DIV2: capture is done once every 2 events
02415   *     @arg TIM_ICPSC_DIV4: capture is done once every 4 events
02416   *     @arg TIM_ICPSC_DIV8: capture is done once every 8 events
02417   * @retval None
02418   */
02419 void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
02420 {
02421   /* Check the parameters */
02422   assert_param(IS_TIM_LIST3_PERIPH(TIMx));
02423   assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
02424   /* Reset the IC4PSC Bits */
02425   TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC4PSC);
02426   /* Set the IC4PSC value */
02427   TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8);
02428 }
02429
02430 /**
02431   * @brief  Sets the TIMx Clock Division value.
02432   * @param  TIMx: where x can be  1 to 17 except 6 and 7 to select
02433   *   the TIM peripheral.
02434   * @param  TIM_CKD: specifies the clock division value.
02435   *   This parameter can be one of the following value:
02436   *     @arg TIM_CKD_DIV1: TDTS = Tck_tim
02437   *     @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim
02438   *     @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim
02439   * @retval None
02440   */
02441 void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD)
02442 {
02443   /* Check the parameters */
02444   assert_param(IS_TIM_LIST8_PERIPH(TIMx));
02445   assert_param(IS_TIM_CKD_DIV(TIM_CKD));
02446   /* Reset the CKD Bits */
02447   TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_CKD);
02448   /* Set the CKD value */
02449   TIMx->CR1 |= TIM_CKD;
02450 }
02451
02452 /**
02453   * @brief  Gets the TIMx Input Capture 1 value.
02454   * @param  TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
02455   * @retval Capture Compare 1 Register value.
02456   */
02457 uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx)
02458 {
02459   /* Check the parameters */
02460   assert_param(IS_TIM_LIST8_PERIPH(TIMx));
02461   /* Get the Capture 1 Register value */
02462   return TIMx->CCR1;
02463 }
02464
02465 /**
02466   * @brief  Gets the TIMx Input Capture 2 value.
02467   * @param  TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
02468   * @retval Capture Compare 2 Register value.
02469   */
02470 uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx)
02471 {
02472   /* Check the parameters */
02473   assert_param(IS_TIM_LIST6_PERIPH(TIMx));
02474   /* Get the Capture 2 Register value */
02475   return TIMx->CCR2;
02476 }
02477
02478 /**
02479   * @brief  Gets the TIMx Input Capture 3 value.
02480   * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
02481   * @retval Capture Compare 3 Register value.
02482   */
02483 uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx)
02484 {
02485   /* Check the parameters */
02486   assert_param(IS_TIM_LIST3_PERIPH(TIMx));
02487   /* Get the Capture 3 Register value */
02488   return TIMx->CCR3;
02489 }
02490
02491 /**
02492   * @brief  Gets the TIMx Input Capture 4 value.
02493   * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
02494   * @retval Capture Compare 4 Register value.
02495   */
02496 uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx)
02497 {
02498   /* Check the parameters */
02499   assert_param(IS_TIM_LIST3_PERIPH(TIMx));
02500   /* Get the Capture 4 Register value */
02501   return TIMx->CCR4;
02502 }
02503
02504 /**
02505   * @brief  Gets the TIMx Counter value.
02506   * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
02507   * @retval Counter Register value.
02508   */
02509 uint16_t TIM_GetCounter(TIM_TypeDef* TIMx)
02510 {
02511   /* Check the parameters */
02512   assert_param(IS_TIM_ALL_PERIPH(TIMx));
02513   /* Get the Counter Register value */
02514   return TIMx->CNT;
02515 }
02516
02517 /**
02518   * @brief  Gets the TIMx Prescaler value.
02519   * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
02520   * @retval Prescaler Register value.
02521   */
02522 uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx)
02523 {
02524   /* Check the parameters */
02525   assert_param(IS_TIM_ALL_PERIPH(TIMx));
02526   /* Get the Prescaler Register value */
02527   return TIMx->PSC;
02528 }
02529
02530 /**
02531   * @brief  Checks whether the specified TIM flag is set or not.
02532   * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
02533   * @param  TIM_FLAG: specifies the flag to check.
02534   *   This parameter can be one of the following values:
02535   *     @arg TIM_FLAG_Update: TIM update Flag
02536   *     @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
02537   *     @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
02538   *     @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
02539   *     @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
02540   *     @arg TIM_FLAG_COM: TIM Commutation Flag
02541   *     @arg TIM_FLAG_Trigger: TIM Trigger Flag
02542   *     @arg TIM_FLAG_Break: TIM Break Flag
02543   *     @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag
02544   *     @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag
02545   *     @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag
02546   *     @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag
02547   * @note
02548   *   - TIM6 and TIM7 can have only one update flag.
02549   *   - TIM9, TIM12 and TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1,
02550   *      TIM_FLAG_CC2 or TIM_FLAG_Trigger.
02551   *   - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1.
02552   *   - TIM_FLAG_Break is used only with TIM1, TIM8 and TIM15.
02553   *   - TIM_FLAG_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17.
02554   * @retval The new state of TIM_FLAG (SET or RESET).
02555   */
02556 FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
02557 {
02558   ITStatus bitstatus = RESET;
02559   /* Check the parameters */
02560   assert_param(IS_TIM_ALL_PERIPH(TIMx));
02561   assert_param(IS_TIM_GET_FLAG(TIM_FLAG));
02562
02563   if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET)
02564   {
02565     bitstatus = SET;
02566   }
02567   else
02568   {
02569     bitstatus = RESET;
02570   }
02571   return bitstatus;
02572 }
02573
02574 /**
02575   * @brief  Clears the TIMx's pending flags.
02576   * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
02577   * @param  TIM_FLAG: specifies the flag bit to clear.
02578   *   This parameter can be any combination of the following values:
02579   *     @arg TIM_FLAG_Update: TIM update Flag
02580   *     @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
02581   *     @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
02582   *     @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
02583   *     @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
02584   *     @arg TIM_FLAG_COM: TIM Commutation Flag
02585   *     @arg TIM_FLAG_Trigger: TIM Trigger Flag
02586   *     @arg TIM_FLAG_Break: TIM Break Flag
02587   *     @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag
02588   *     @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag
02589   *     @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag
02590   *     @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag
02591   * @note
02592   *   - TIM6 and TIM7 can have only one update flag.
02593   *   - TIM9, TIM12 and TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1,
02594   *      TIM_FLAG_CC2 or TIM_FLAG_Trigger.
02595   *   - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1.
02596   *   - TIM_FLAG_Break is used only with TIM1, TIM8 and TIM15.
02597   *   - TIM_FLAG_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17.
02598   * @retval None
02599   */
02600 void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
02601 {
02602   /* Check the parameters */
02603   assert_param(IS_TIM_ALL_PERIPH(TIMx));
02604   assert_param(IS_TIM_CLEAR_FLAG(TIM_FLAG));
02605
02606   /* Clear the flags */
02607   TIMx->SR = (uint16_t)~TIM_FLAG;
02608 }
02609
02610 /**
02611   * @brief  Checks whether the TIM interrupt has occurred or not.
02612   * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
02613   * @param  TIM_IT: specifies the TIM interrupt source to check.
02614   *   This parameter can be one of the following values:
02615   *     @arg TIM_IT_Update: TIM update Interrupt source
02616   *     @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
02617   *     @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
02618   *     @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
02619   *     @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
02620   *     @arg TIM_IT_COM: TIM Commutation Interrupt source
02621   *     @arg TIM_IT_Trigger: TIM Trigger Interrupt source
02622   *     @arg TIM_IT_Break: TIM Break Interrupt source
02623   * @note
02624   *   - TIM6 and TIM7 can generate only an update interrupt.
02625   *   - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1,
02626   *      TIM_IT_CC2 or TIM_IT_Trigger.
02627   *   - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1.
02628   *   - TIM_IT_Break is used only with TIM1, TIM8 and TIM15.
02629   *   - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17.
02630   * @retval The new state of the TIM_IT(SET or RESET).
02631   */
02632 ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT)
02633 {
02634   ITStatus bitstatus = RESET;
02635   uint16_t itstatus = 0x0, itenable = 0x0;
02636   /* Check the parameters */
02637   assert_param(IS_TIM_ALL_PERIPH(TIMx));
02638   assert_param(IS_TIM_GET_IT(TIM_IT));
02639
02640   itstatus = TIMx->SR & TIM_IT;
02641
02642   itenable = TIMx->DIER & TIM_IT;
02643   if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET))
02644   {
02645     bitstatus = SET;
02646   }
02647   else
02648   {
02649     bitstatus = RESET;
02650   }
02651   return bitstatus;
02652 }
02653
02654 /**
02655   * @brief  Clears the TIMx's interrupt pending bits.
02656   * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
02657   * @param  TIM_IT: specifies the pending bit to clear.
02658   *   This parameter can be any combination of the following values:
02659   *     @arg TIM_IT_Update: TIM1 update Interrupt source
02660   *     @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
02661   *     @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
02662   *     @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
02663   *     @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
02664   *     @arg TIM_IT_COM: TIM Commutation Interrupt source
02665   *     @arg TIM_IT_Trigger: TIM Trigger Interrupt source
02666   *     @arg TIM_IT_Break: TIM Break Interrupt source
02667   * @note
02668   *   - TIM6 and TIM7 can generate only an update interrupt.
02669   *   - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1,
02670   *      TIM_IT_CC2 or TIM_IT_Trigger.
02671   *   - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1.
02672   *   - TIM_IT_Break is used only with TIM1, TIM8 and TIM15.
02673   *   - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17.
02674   * @retval None
02675   */
02676 void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT)
02677 {
02678   /* Check the parameters */
02679   assert_param(IS_TIM_ALL_PERIPH(TIMx));
02680   assert_param(IS_TIM_IT(TIM_IT));
02681   /* Clear the IT pending Bit */
02682   TIMx->SR = (uint16_t)~TIM_IT;
02683 }
02684
02685 /**
02686   * @brief  Configure the TI1 as Input.
02687   * @param  TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
02688   * @param  TIM_ICPolarity : The Input Polarity.
02689   *   This parameter can be one of the following values:
02690   *     @arg TIM_ICPolarity_Rising
02691   *     @arg TIM_ICPolarity_Falling
02692   * @param  TIM_ICSelection: specifies the input to be used.
02693   *   This parameter can be one of the following values:
02694   *     @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
02695   *     @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
02696   *     @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
02697   * @param  TIM_ICFilter: Specifies the Input Capture Filter.
02698   *   This parameter must be a value between 0x00 and 0x0F.
02699   * @retval None
02700   */
02701 static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
02702                        uint16_t TIM_ICFilter)
02703 {
02704   uint16_t tmpccmr1 = 0, tmpccer = 0;
02705   /* Disable the Channel 1: Reset the CC1E Bit */
02706   TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC1E);
02707   tmpccmr1 = TIMx->CCMR1;
02708   tmpccer = TIMx->CCER;
02709   /* Select the Input and set the filter */
02710   tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC1F)));
02711   tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
02712
02713   if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||
02714      (TIMx == TIM4) ||(TIMx == TIM5))
02715   {
02716     /* Select the Polarity and set the CC1E Bit */
02717     tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P));
02718     tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E);
02719   }
02720   else
02721   {
02722     /* Select the Polarity and set the CC1E Bit */
02723     tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P | TIM_CCER_CC1NP));
02724     tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E);
02725   }
02726
02727   /* Write to TIMx CCMR1 and CCER registers */
02728   TIMx->CCMR1 = tmpccmr1;
02729   TIMx->CCER = tmpccer;
02730 }
02731
02732 /**
02733   * @brief  Configure the TI2 as Input.
02734   * @param  TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
02735   * @param  TIM_ICPolarity : The Input Polarity.
02736   *   This parameter can be one of the following values:
02737   *     @arg TIM_ICPolarity_Rising
02738   *     @arg TIM_ICPolarity_Falling
02739   * @param  TIM_ICSelection: specifies the input to be used.
02740   *   This parameter can be one of the following values:
02741   *     @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
02742   *     @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
02743   *     @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
02744   * @param  TIM_ICFilter: Specifies the Input Capture Filter.
02745   *   This parameter must be a value between 0x00 and 0x0F.
02746   * @retval None
02747   */
02748 static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
02749                        uint16_t TIM_ICFilter)
02750 {
02751   uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0;
02752   /* Disable the Channel 2: Reset the CC2E Bit */
02753   TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC2E);
02754   tmpccmr1 = TIMx->CCMR1;
02755   tmpccer = TIMx->CCER;
02756   tmp = (uint16_t)(TIM_ICPolarity << 4);
02757   /* Select the Input and set the filter */
02758   tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC2S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC2F)));
02759   tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12);
02760   tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8);
02761
02762   if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||
02763      (TIMx == TIM4) ||(TIMx == TIM5))
02764   {
02765     /* Select the Polarity and set the CC2E Bit */
02766     tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P));
02767     tmpccer |=  (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E);
02768   }
02769   else
02770   {
02771     /* Select the Polarity and set the CC2E Bit */
02772     tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P | TIM_CCER_CC2NP));
02773     tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC2E);
02774   }
02775
02776   /* Write to TIMx CCMR1 and CCER registers */
02777   TIMx->CCMR1 = tmpccmr1 ;
02778   TIMx->CCER = tmpccer;
02779 }
02780
02781 /**
02782   * @brief  Configure the TI3 as Input.
02783   * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
02784   * @param  TIM_ICPolarity : The Input Polarity.
02785   *   This parameter can be one of the following values:
02786   *     @arg TIM_ICPolarity_Rising
02787   *     @arg TIM_ICPolarity_Falling
02788   * @param  TIM_ICSelection: specifies the input to be used.
02789   *   This parameter can be one of the following values:
02790   *     @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
02791   *     @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
02792   *     @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
02793   * @param  TIM_ICFilter: Specifies the Input Capture Filter.
02794   *   This parameter must be a value between 0x00 and 0x0F.
02795   * @retval None
02796   */
02797 static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
02798                        uint16_t TIM_ICFilter)
02799 {
02800   uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
02801   /* Disable the Channel 3: Reset the CC3E Bit */
02802   TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC3E);
02803   tmpccmr2 = TIMx->CCMR2;
02804   tmpccer = TIMx->CCER;
02805   tmp = (uint16_t)(TIM_ICPolarity << 8);
02806   /* Select the Input and set the filter */
02807   tmpccmr2 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR2_CC3S)) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC3F)));
02808   tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
02809
02810   if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||
02811      (TIMx == TIM4) ||(TIMx == TIM5))
02812   {
02813     /* Select the Polarity and set the CC3E Bit */
02814     tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P));
02815     tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E);
02816   }
02817   else
02818   {
02819     /* Select the Polarity and set the CC3E Bit */
02820     tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P | TIM_CCER_CC3NP));
02821     tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC3E);
02822   }
02823
02824   /* Write to TIMx CCMR2 and CCER registers */
02825   TIMx->CCMR2 = tmpccmr2;
02826   TIMx->CCER = tmpccer;
02827 }
02828
02829 /**
02830   * @brief  Configure the TI4 as Input.
02831   * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
02832   * @param  TIM_ICPolarity : The Input Polarity.
02833   *   This parameter can be one of the following values:
02834   *     @arg TIM_ICPolarity_Rising
02835   *     @arg TIM_ICPolarity_Falling
02836   * @param  TIM_ICSelection: specifies the input to be used.
02837   *   This parameter can be one of the following values:
02838   *     @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
02839   *     @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
02840   *     @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
02841   * @param  TIM_ICFilter: Specifies the Input Capture Filter.
02842   *   This parameter must be a value between 0x00 and 0x0F.
02843   * @retval None
02844   */
02845 static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
02846                        uint16_t TIM_ICFilter)
02847 {
02848   uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
02849
02850    /* Disable the Channel 4: Reset the CC4E Bit */
02851   TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC4E);
02852   tmpccmr2 = TIMx->CCMR2;
02853   tmpccer = TIMx->CCER;
02854   tmp = (uint16_t)(TIM_ICPolarity << 12);
02855   /* Select the Input and set the filter */
02856   tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CCMR2_CC4S) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC4F)));
02857   tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8);
02858   tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12);
02859
02860   if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||
02861      (TIMx == TIM4) ||(TIMx == TIM5))
02862   {
02863     /* Select the Polarity and set the CC4E Bit */
02864     tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC4P));
02865     tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E);
02866   }
02867   else
02868   {
02869     /* Select the Polarity and set the CC4E Bit */
02870     tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P | TIM_CCER_CC4NP));
02871     tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC4E);
02872   }
02873   /* Write to TIMx CCMR2 and CCER registers */
02874   TIMx->CCMR2 = tmpccmr2;
02875   TIMx->CCER = tmpccer;
02876 }
02877
02878 /**
02879   * @}
02880   */
02881
02882 /**
02883   * @}
02884   */
02885
02886 /**
02887   * @}
02888   */
02889
02890 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_tim.h Source File

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stm32f10x_tim.h

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f10x_tim.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    11-March-2011
00007   * @brief   This file contains all the functions prototypes for the TIM firmware
00008   *          library.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00013   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00014   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00015   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00016   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00017   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00018   *
00019   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00020   ******************************************************************************
00021   */
00022
00023 /* Define to prevent recursive inclusion -------------------------------------*/
00024 #ifndef __STM32F10x_TIM_H
00025 #define __STM32F10x_TIM_H
00026
00027 #ifdef __cplusplus
00028  extern "C" {
00029 #endif
00030
00031 /* Includes ------------------------------------------------------------------*/
00032 #include "stm32f10x.h"
00033
00034 /** @addtogroup STM32F10x_StdPeriph_Driver
00035   * @{
00036   */
00037
00038 /** @addtogroup TIM
00039   * @{
00040   */
00041
00042 /** @defgroup TIM_Exported_Types
00043   * @{
00044   */
00045
00046 /**
00047   * @brief  TIM Time Base Init structure definition
00048   * @note   This structure is used with all TIMx except for TIM6 and TIM7.
00049   */
00050
00051 typedef struct
00052 {
00053   uint16_t TIM_Prescaler;         /*!< Specifies the prescaler value used to divide the TIM clock.
00054                                        This parameter can be a number between 0x0000 and 0xFFFF */
00055
00056   uint16_t TIM_CounterMode;       /*!< Specifies the counter mode.
00057                                        This parameter can be a value of @ref TIM_Counter_Mode */
00058
00059   uint16_t TIM_Period;            /*!< Specifies the period value to be loaded into the active
00060                                        Auto-Reload Register at the next update event.
00061                                        This parameter must be a number between 0x0000 and 0xFFFF.  */
00062
00063   uint16_t TIM_ClockDivision;     /*!< Specifies the clock division.
00064                                       This parameter can be a value of @ref TIM_Clock_Division_CKD */
00065
00066   uint8_t TIM_RepetitionCounter;  /*!< Specifies the repetition counter value. Each time the RCR downcounter
00067                                        reaches zero, an update event is generated and counting restarts
00068                                        from the RCR value (N).
00069                                        This means in PWM mode that (N+1) corresponds to:
00070                                           - the number of PWM periods in edge-aligned mode
00071                                           - the number of half PWM period in center-aligned mode
00072                                        This parameter must be a number between 0x00 and 0xFF.
00073                                        @note This parameter is valid only for TIM1 and TIM8. */
00074 } TIM_TimeBaseInitTypeDef;
00075
00076 /**
00077   * @brief  TIM Output Compare Init structure definition
00078   */
00079
00080 typedef struct
00081 {
00082   uint16_t TIM_OCMode;        /*!< Specifies the TIM mode.
00083                                    This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
00084
00085   uint16_t TIM_OutputState;   /*!< Specifies the TIM Output Compare state.
00086                                    This parameter can be a value of @ref TIM_Output_Compare_state */
00087
00088   uint16_t TIM_OutputNState;  /*!< Specifies the TIM complementary Output Compare state.
00089                                    This parameter can be a value of @ref TIM_Output_Compare_N_state
00090                                    @note This parameter is valid only for TIM1 and TIM8. */
00091
00092   uint16_t TIM_Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
00093                                    This parameter can be a number between 0x0000 and 0xFFFF */
00094
00095   uint16_t TIM_OCPolarity;    /*!< Specifies the output polarity.
00096                                    This parameter can be a value of @ref TIM_Output_Compare_Polarity */
00097
00098   uint16_t TIM_OCNPolarity;   /*!< Specifies the complementary output polarity.
00099                                    This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
00100                                    @note This parameter is valid only for TIM1 and TIM8. */
00101
00102   uint16_t TIM_OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
00103                                    This parameter can be a value of @ref TIM_Output_Compare_Idle_State
00104                                    @note This parameter is valid only for TIM1 and TIM8. */
00105
00106   uint16_t TIM_OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
00107                                    This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
00108                                    @note This parameter is valid only for TIM1 and TIM8. */
00109 } TIM_OCInitTypeDef;
00110
00111 /**
00112   * @brief  TIM Input Capture Init structure definition
00113   */
00114
00115 typedef struct
00116 {
00117
00118   uint16_t TIM_Channel;      /*!< Specifies the TIM channel.
00119                                   This parameter can be a value of @ref TIM_Channel */
00120
00121   uint16_t TIM_ICPolarity;   /*!< Specifies the active edge of the input signal.
00122                                   This parameter can be a value of @ref TIM_Input_Capture_Polarity */
00123
00124   uint16_t TIM_ICSelection;  /*!< Specifies the input.
00125                                   This parameter can be a value of @ref TIM_Input_Capture_Selection */
00126
00127   uint16_t TIM_ICPrescaler;  /*!< Specifies the Input Capture Prescaler.
00128                                   This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
00129
00130   uint16_t TIM_ICFilter;     /*!< Specifies the input capture filter.
00131                                   This parameter can be a number between 0x0 and 0xF */
00132 } TIM_ICInitTypeDef;
00133
00134 /**
00135   * @brief  BDTR structure definition
00136   * @note   This structure is used only with TIM1 and TIM8.
00137   */
00138
00139 typedef struct
00140 {
00141
00142   uint16_t TIM_OSSRState;        /*!< Specifies the Off-State selection used in Run mode.
00143                                       This parameter can be a value of @ref OSSR_Off_State_Selection_for_Run_mode_state */
00144
00145   uint16_t TIM_OSSIState;        /*!< Specifies the Off-State used in Idle state.
00146                                       This parameter can be a value of @ref OSSI_Off_State_Selection_for_Idle_mode_state */
00147
00148   uint16_t TIM_LOCKLevel;        /*!< Specifies the LOCK level parameters.
00149                                       This parameter can be a value of @ref Lock_level */
00150
00151   uint16_t TIM_DeadTime;         /*!< Specifies the delay time between the switching-off and the
00152                                       switching-on of the outputs.
00153                                       This parameter can be a number between 0x00 and 0xFF  */
00154
00155   uint16_t TIM_Break;            /*!< Specifies whether the TIM Break input is enabled or not.
00156                                       This parameter can be a value of @ref Break_Input_enable_disable */
00157
00158   uint16_t TIM_BreakPolarity;    /*!< Specifies the TIM Break Input pin polarity.
00159                                       This parameter can be a value of @ref Break_Polarity */
00160
00161   uint16_t TIM_AutomaticOutput;  /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
00162                                       This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
00163 } TIM_BDTRInitTypeDef;
00164
00165 /** @defgroup TIM_Exported_constants
00166   * @{
00167   */
00168
00169 #define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
00170                                    ((PERIPH) == TIM2) || \
00171                                    ((PERIPH) == TIM3) || \
00172                                    ((PERIPH) == TIM4) || \
00173                                    ((PERIPH) == TIM5) || \
00174                                    ((PERIPH) == TIM6) || \
00175                                    ((PERIPH) == TIM7) || \
00176                                    ((PERIPH) == TIM8) || \
00177                                    ((PERIPH) == TIM9) || \
00178                                    ((PERIPH) == TIM10)|| \
00179                                    ((PERIPH) == TIM11)|| \
00180                                    ((PERIPH) == TIM12)|| \
00181                                    ((PERIPH) == TIM13)|| \
00182                                    ((PERIPH) == TIM14)|| \
00183                                    ((PERIPH) == TIM15)|| \
00184                                    ((PERIPH) == TIM16)|| \
00185                                    ((PERIPH) == TIM17))
00186
00187 /* LIST1: TIM 1 and 8 */
00188 #define IS_TIM_LIST1_PERIPH(PERIPH)  (((PERIPH) == TIM1) || \
00189                                       ((PERIPH) == TIM8))
00190
00191 /* LIST2: TIM 1, 8, 15 16 and 17 */
00192 #define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
00193                                      ((PERIPH) == TIM8) || \
00194                                      ((PERIPH) == TIM15)|| \
00195                                      ((PERIPH) == TIM16)|| \
00196                                      ((PERIPH) == TIM17))
00197
00198 /* LIST3: TIM 1, 2, 3, 4, 5 and 8 */
00199 #define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
00200                                      ((PERIPH) == TIM2) || \
00201                                      ((PERIPH) == TIM3) || \
00202                                      ((PERIPH) == TIM4) || \
00203                                      ((PERIPH) == TIM5) || \
00204                                      ((PERIPH) == TIM8))
00205
00206 /* LIST4: TIM 1, 2, 3, 4, 5, 8, 15, 16 and 17 */
00207 #define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
00208                                      ((PERIPH) == TIM2) || \
00209                                      ((PERIPH) == TIM3) || \
00210                                      ((PERIPH) == TIM4) || \
00211                                      ((PERIPH) == TIM5) || \
00212                                      ((PERIPH) == TIM8) || \
00213                                      ((PERIPH) == TIM15)|| \
00214                                      ((PERIPH) == TIM16)|| \
00215                                      ((PERIPH) == TIM17))
00216
00217 /* LIST5: TIM 1, 2, 3, 4, 5, 8 and 15 */
00218 #define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
00219                                      ((PERIPH) == TIM2) || \
00220                                      ((PERIPH) == TIM3) || \
00221                                      ((PERIPH) == TIM4) || \
00222                                      ((PERIPH) == TIM5) || \
00223                                      ((PERIPH) == TIM8) || \
00224                                      ((PERIPH) == TIM15))
00225
00226 /* LIST6: TIM 1, 2, 3, 4, 5, 8, 9, 12 and 15 */
00227 #define IS_TIM_LIST6_PERIPH(PERIPH)  (((PERIPH) == TIM1) || \
00228                                       ((PERIPH) == TIM2) || \
00229                                       ((PERIPH) == TIM3) || \
00230                                       ((PERIPH) == TIM4) || \
00231                                       ((PERIPH) == TIM5) || \
00232                                       ((PERIPH) == TIM8) || \
00233                                       ((PERIPH) == TIM9) || \
00234                                                                           ((PERIPH) == TIM12)|| \
00235                                       ((PERIPH) == TIM15))
00236
00237 /* LIST7: TIM 1, 2, 3, 4, 5, 6, 7, 8, 9, 12 and 15 */
00238 #define IS_TIM_LIST7_PERIPH(PERIPH)  (((PERIPH) == TIM1) || \
00239                                       ((PERIPH) == TIM2) || \
00240                                       ((PERIPH) == TIM3) || \
00241                                       ((PERIPH) == TIM4) || \
00242                                       ((PERIPH) == TIM5) || \
00243                                       ((PERIPH) == TIM6) || \
00244                                       ((PERIPH) == TIM7) || \
00245                                       ((PERIPH) == TIM8) || \
00246                                       ((PERIPH) == TIM9) || \
00247                                       ((PERIPH) == TIM12)|| \
00248                                       ((PERIPH) == TIM15))
00249
00250 /* LIST8: TIM 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13, 14, 15, 16 and 17 */
00251 #define IS_TIM_LIST8_PERIPH(PERIPH)  (((PERIPH) == TIM1) || \
00252                                       ((PERIPH) == TIM2) || \
00253                                       ((PERIPH) == TIM3) || \
00254                                       ((PERIPH) == TIM4) || \
00255                                       ((PERIPH) == TIM5) || \
00256                                       ((PERIPH) == TIM8) || \
00257                                       ((PERIPH) == TIM9) || \
00258                                       ((PERIPH) == TIM10)|| \
00259                                       ((PERIPH) == TIM11)|| \
00260                                       ((PERIPH) == TIM12)|| \
00261                                       ((PERIPH) == TIM13)|| \
00262                                       ((PERIPH) == TIM14)|| \
00263                                       ((PERIPH) == TIM15)|| \
00264                                       ((PERIPH) == TIM16)|| \
00265                                       ((PERIPH) == TIM17))
00266
00267 /* LIST9: TIM 1, 2, 3, 4, 5, 6, 7, 8, 15, 16, and 17 */
00268 #define IS_TIM_LIST9_PERIPH(PERIPH)  (((PERIPH) == TIM1) || \
00269                                       ((PERIPH) == TIM2) || \
00270                                       ((PERIPH) == TIM3) || \
00271                                       ((PERIPH) == TIM4) || \
00272                                       ((PERIPH) == TIM5) || \
00273                                       ((PERIPH) == TIM6) || \
00274                                       ((PERIPH) == TIM7) || \
00275                                       ((PERIPH) == TIM8) || \
00276                                       ((PERIPH) == TIM15)|| \
00277                                       ((PERIPH) == TIM16)|| \
00278                                       ((PERIPH) == TIM17))
00279
00280 /**
00281   * @}
00282   */
00283
00284 /** @defgroup TIM_Output_Compare_and_PWM_modes
00285   * @{
00286   */
00287
00288 #define TIM_OCMode_Timing                  ((uint16_t)0x0000)
00289 #define TIM_OCMode_Active                  ((uint16_t)0x0010)
00290 #define TIM_OCMode_Inactive                ((uint16_t)0x0020)
00291 #define TIM_OCMode_Toggle                  ((uint16_t)0x0030)
00292 #define TIM_OCMode_PWM1                    ((uint16_t)0x0060)
00293 #define TIM_OCMode_PWM2                    ((uint16_t)0x0070)
00294 #define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \
00295                               ((MODE) == TIM_OCMode_Active) || \
00296                               ((MODE) == TIM_OCMode_Inactive) || \
00297                               ((MODE) == TIM_OCMode_Toggle)|| \
00298                               ((MODE) == TIM_OCMode_PWM1) || \
00299                               ((MODE) == TIM_OCMode_PWM2))
00300 #define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \
00301                           ((MODE) == TIM_OCMode_Active) || \
00302                           ((MODE) == TIM_OCMode_Inactive) || \
00303                           ((MODE) == TIM_OCMode_Toggle)|| \
00304                           ((MODE) == TIM_OCMode_PWM1) || \
00305                           ((MODE) == TIM_OCMode_PWM2) ||        \
00306                           ((MODE) == TIM_ForcedAction_Active) || \
00307                           ((MODE) == TIM_ForcedAction_InActive))
00308 /**
00309   * @}
00310   */
00311
00312 /** @defgroup TIM_One_Pulse_Mode
00313   * @{
00314   */
00315
00316 #define TIM_OPMode_Single                  ((uint16_t)0x0008)
00317 #define TIM_OPMode_Repetitive              ((uint16_t)0x0000)
00318 #define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \
00319                                ((MODE) == TIM_OPMode_Repetitive))
00320 /**
00321   * @}
00322   */
00323
00324 /** @defgroup TIM_Channel
00325   * @{
00326   */
00327
00328 #define TIM_Channel_1                      ((uint16_t)0x0000)
00329 #define TIM_Channel_2                      ((uint16_t)0x0004)
00330 #define TIM_Channel_3                      ((uint16_t)0x0008)
00331 #define TIM_Channel_4                      ((uint16_t)0x000C)
00332 #define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
00333                                  ((CHANNEL) == TIM_Channel_2) || \
00334                                  ((CHANNEL) == TIM_Channel_3) || \
00335                                  ((CHANNEL) == TIM_Channel_4))
00336 #define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
00337                                       ((CHANNEL) == TIM_Channel_2))
00338 #define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
00339                                                ((CHANNEL) == TIM_Channel_2) || \
00340                                                ((CHANNEL) == TIM_Channel_3))
00341 /**
00342   * @}
00343   */
00344
00345 /** @defgroup TIM_Clock_Division_CKD
00346   * @{
00347   */
00348
00349 #define TIM_CKD_DIV1                       ((uint16_t)0x0000)
00350 #define TIM_CKD_DIV2                       ((uint16_t)0x0100)
00351 #define TIM_CKD_DIV4                       ((uint16_t)0x0200)
00352 #define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \
00353                              ((DIV) == TIM_CKD_DIV2) || \
00354                              ((DIV) == TIM_CKD_DIV4))
00355 /**
00356   * @}
00357   */
00358
00359 /** @defgroup TIM_Counter_Mode
00360   * @{
00361   */
00362
00363 #define TIM_CounterMode_Up                 ((uint16_t)0x0000)
00364 #define TIM_CounterMode_Down               ((uint16_t)0x0010)
00365 #define TIM_CounterMode_CenterAligned1     ((uint16_t)0x0020)
00366 #define TIM_CounterMode_CenterAligned2     ((uint16_t)0x0040)
00367 #define TIM_CounterMode_CenterAligned3     ((uint16_t)0x0060)
00368 #define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) ||  \
00369                                    ((MODE) == TIM_CounterMode_Down) || \
00370                                    ((MODE) == TIM_CounterMode_CenterAligned1) || \
00371                                    ((MODE) == TIM_CounterMode_CenterAligned2) || \
00372                                    ((MODE) == TIM_CounterMode_CenterAligned3))
00373 /**
00374   * @}
00375   */
00376
00377 /** @defgroup TIM_Output_Compare_Polarity
00378   * @{
00379   */
00380
00381 #define TIM_OCPolarity_High                ((uint16_t)0x0000)
00382 #define TIM_OCPolarity_Low                 ((uint16_t)0x0002)
00383 #define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \
00384                                       ((POLARITY) == TIM_OCPolarity_Low))
00385 /**
00386   * @}
00387   */
00388
00389 /** @defgroup TIM_Output_Compare_N_Polarity
00390   * @{
00391   */
00392
00393 #define TIM_OCNPolarity_High               ((uint16_t)0x0000)
00394 #define TIM_OCNPolarity_Low                ((uint16_t)0x0008)
00395 #define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \
00396                                        ((POLARITY) == TIM_OCNPolarity_Low))
00397 /**
00398   * @}
00399   */
00400
00401 /** @defgroup TIM_Output_Compare_state
00402   * @{
00403   */
00404
00405 #define TIM_OutputState_Disable            ((uint16_t)0x0000)
00406 #define TIM_OutputState_Enable             ((uint16_t)0x0001)
00407 #define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \
00408                                     ((STATE) == TIM_OutputState_Enable))
00409 /**
00410   * @}
00411   */
00412
00413 /** @defgroup TIM_Output_Compare_N_state
00414   * @{
00415   */
00416
00417 #define TIM_OutputNState_Disable           ((uint16_t)0x0000)
00418 #define TIM_OutputNState_Enable            ((uint16_t)0x0004)
00419 #define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \
00420                                      ((STATE) == TIM_OutputNState_Enable))
00421 /**
00422   * @}
00423   */
00424
00425 /** @defgroup TIM_Capture_Compare_state
00426   * @{
00427   */
00428
00429 #define TIM_CCx_Enable                      ((uint16_t)0x0001)
00430 #define TIM_CCx_Disable                     ((uint16_t)0x0000)
00431 #define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \
00432                          ((CCX) == TIM_CCx_Disable))
00433 /**
00434   * @}
00435   */
00436
00437 /** @defgroup TIM_Capture_Compare_N_state
00438   * @{
00439   */
00440
00441 #define TIM_CCxN_Enable                     ((uint16_t)0x0004)
00442 #define TIM_CCxN_Disable                    ((uint16_t)0x0000)
00443 #define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \
00444                            ((CCXN) == TIM_CCxN_Disable))
00445 /**
00446   * @}
00447   */
00448
00449 /** @defgroup Break_Input_enable_disable
00450   * @{
00451   */
00452
00453 #define TIM_Break_Enable                   ((uint16_t)0x1000)
00454 #define TIM_Break_Disable                  ((uint16_t)0x0000)
00455 #define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \
00456                                    ((STATE) == TIM_Break_Disable))
00457 /**
00458   * @}
00459   */
00460
00461 /** @defgroup Break_Polarity
00462   * @{
00463   */
00464
00465 #define TIM_BreakPolarity_Low              ((uint16_t)0x0000)
00466 #define TIM_BreakPolarity_High             ((uint16_t)0x2000)
00467 #define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \
00468                                          ((POLARITY) == TIM_BreakPolarity_High))
00469 /**
00470   * @}
00471   */
00472
00473 /** @defgroup TIM_AOE_Bit_Set_Reset
00474   * @{
00475   */
00476
00477 #define TIM_AutomaticOutput_Enable         ((uint16_t)0x4000)
00478 #define TIM_AutomaticOutput_Disable        ((uint16_t)0x0000)
00479 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \
00480                                               ((STATE) == TIM_AutomaticOutput_Disable))
00481 /**
00482   * @}
00483   */
00484
00485 /** @defgroup Lock_level
00486   * @{
00487   */
00488
00489 #define TIM_LOCKLevel_OFF                  ((uint16_t)0x0000)
00490 #define TIM_LOCKLevel_1                    ((uint16_t)0x0100)
00491 #define TIM_LOCKLevel_2                    ((uint16_t)0x0200)
00492 #define TIM_LOCKLevel_3                    ((uint16_t)0x0300)
00493 #define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \
00494                                   ((LEVEL) == TIM_LOCKLevel_1) || \
00495                                   ((LEVEL) == TIM_LOCKLevel_2) || \
00496                                   ((LEVEL) == TIM_LOCKLevel_3))
00497 /**
00498   * @}
00499   */
00500
00501 /** @defgroup OSSI_Off_State_Selection_for_Idle_mode_state
00502   * @{
00503   */
00504
00505 #define TIM_OSSIState_Enable               ((uint16_t)0x0400)
00506 #define TIM_OSSIState_Disable              ((uint16_t)0x0000)
00507 #define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \
00508                                   ((STATE) == TIM_OSSIState_Disable))
00509 /**
00510   * @}
00511   */
00512
00513 /** @defgroup OSSR_Off_State_Selection_for_Run_mode_state
00514   * @{
00515   */
00516
00517 #define TIM_OSSRState_Enable               ((uint16_t)0x0800)
00518 #define TIM_OSSRState_Disable              ((uint16_t)0x0000)
00519 #define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \
00520                                   ((STATE) == TIM_OSSRState_Disable))
00521 /**
00522   * @}
00523   */
00524
00525 /** @defgroup TIM_Output_Compare_Idle_State
00526   * @{
00527   */
00528
00529 #define TIM_OCIdleState_Set                ((uint16_t)0x0100)
00530 #define TIM_OCIdleState_Reset              ((uint16_t)0x0000)
00531 #define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \
00532                                     ((STATE) == TIM_OCIdleState_Reset))
00533 /**
00534   * @}
00535   */
00536
00537 /** @defgroup TIM_Output_Compare_N_Idle_State
00538   * @{
00539   */
00540
00541 #define TIM_OCNIdleState_Set               ((uint16_t)0x0200)
00542 #define TIM_OCNIdleState_Reset             ((uint16_t)0x0000)
00543 #define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \
00544                                      ((STATE) == TIM_OCNIdleState_Reset))
00545 /**
00546   * @}
00547   */
00548
00549 /** @defgroup TIM_Input_Capture_Polarity
00550   * @{
00551   */
00552
00553 #define  TIM_ICPolarity_Rising             ((uint16_t)0x0000)
00554 #define  TIM_ICPolarity_Falling            ((uint16_t)0x0002)
00555 #define  TIM_ICPolarity_BothEdge           ((uint16_t)0x000A)
00556 #define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \
00557                                       ((POLARITY) == TIM_ICPolarity_Falling))
00558 #define IS_TIM_IC_POLARITY_LITE(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \
00559                                            ((POLARITY) == TIM_ICPolarity_Falling)|| \
00560                                            ((POLARITY) == TIM_ICPolarity_BothEdge))
00561 /**
00562   * @}
00563   */
00564
00565 /** @defgroup TIM_Input_Capture_Selection
00566   * @{
00567   */
00568
00569 #define TIM_ICSelection_DirectTI           ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be
00570                                                                    connected to IC1, IC2, IC3 or IC4, respectively */
00571 #define TIM_ICSelection_IndirectTI         ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be
00572                                                                    connected to IC2, IC1, IC4 or IC3, respectively. */
00573 #define TIM_ICSelection_TRC                ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */
00574 #define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \
00575                                         ((SELECTION) == TIM_ICSelection_IndirectTI) || \
00576                                         ((SELECTION) == TIM_ICSelection_TRC))
00577 /**
00578   * @}
00579   */
00580
00581 /** @defgroup TIM_Input_Capture_Prescaler
00582   * @{
00583   */
00584
00585 #define TIM_ICPSC_DIV1                     ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */
00586 #define TIM_ICPSC_DIV2                     ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */
00587 #define TIM_ICPSC_DIV4                     ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */
00588 #define TIM_ICPSC_DIV8                     ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */
00589 #define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
00590                                         ((PRESCALER) == TIM_ICPSC_DIV2) || \
00591                                         ((PRESCALER) == TIM_ICPSC_DIV4) || \
00592                                         ((PRESCALER) == TIM_ICPSC_DIV8))
00593 /**
00594   * @}
00595   */
00596
00597 /** @defgroup TIM_interrupt_sources
00598   * @{
00599   */
00600
00601 #define TIM_IT_Update                      ((uint16_t)0x0001)
00602 #define TIM_IT_CC1                         ((uint16_t)0x0002)
00603 #define TIM_IT_CC2                         ((uint16_t)0x0004)
00604 #define TIM_IT_CC3                         ((uint16_t)0x0008)
00605 #define TIM_IT_CC4                         ((uint16_t)0x0010)
00606 #define TIM_IT_COM                         ((uint16_t)0x0020)
00607 #define TIM_IT_Trigger                     ((uint16_t)0x0040)
00608 #define TIM_IT_Break                       ((uint16_t)0x0080)
00609 #define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000))
00610
00611 #define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \
00612                            ((IT) == TIM_IT_CC1) || \
00613                            ((IT) == TIM_IT_CC2) || \
00614                            ((IT) == TIM_IT_CC3) || \
00615                            ((IT) == TIM_IT_CC4) || \
00616                            ((IT) == TIM_IT_COM) || \
00617                            ((IT) == TIM_IT_Trigger) || \
00618                            ((IT) == TIM_IT_Break))
00619 /**
00620   * @}
00621   */
00622
00623 /** @defgroup TIM_DMA_Base_address
00624   * @{
00625   */
00626
00627 #define TIM_DMABase_CR1                    ((uint16_t)0x0000)
00628 #define TIM_DMABase_CR2                    ((uint16_t)0x0001)
00629 #define TIM_DMABase_SMCR                   ((uint16_t)0x0002)
00630 #define TIM_DMABase_DIER                   ((uint16_t)0x0003)
00631 #define TIM_DMABase_SR                     ((uint16_t)0x0004)
00632 #define TIM_DMABase_EGR                    ((uint16_t)0x0005)
00633 #define TIM_DMABase_CCMR1                  ((uint16_t)0x0006)
00634 #define TIM_DMABase_CCMR2                  ((uint16_t)0x0007)
00635 #define TIM_DMABase_CCER                   ((uint16_t)0x0008)
00636 #define TIM_DMABase_CNT                    ((uint16_t)0x0009)
00637 #define TIM_DMABase_PSC                    ((uint16_t)0x000A)
00638 #define TIM_DMABase_ARR                    ((uint16_t)0x000B)
00639 #define TIM_DMABase_RCR                    ((uint16_t)0x000C)
00640 #define TIM_DMABase_CCR1                   ((uint16_t)0x000D)
00641 #define TIM_DMABase_CCR2                   ((uint16_t)0x000E)
00642 #define TIM_DMABase_CCR3                   ((uint16_t)0x000F)
00643 #define TIM_DMABase_CCR4                   ((uint16_t)0x0010)
00644 #define TIM_DMABase_BDTR                   ((uint16_t)0x0011)
00645 #define TIM_DMABase_DCR                    ((uint16_t)0x0012)
00646 #define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \
00647                                ((BASE) == TIM_DMABase_CR2) || \
00648                                ((BASE) == TIM_DMABase_SMCR) || \
00649                                ((BASE) == TIM_DMABase_DIER) || \
00650                                ((BASE) == TIM_DMABase_SR) || \
00651                                ((BASE) == TIM_DMABase_EGR) || \
00652                                ((BASE) == TIM_DMABase_CCMR1) || \
00653                                ((BASE) == TIM_DMABase_CCMR2) || \
00654                                ((BASE) == TIM_DMABase_CCER) || \
00655                                ((BASE) == TIM_DMABase_CNT) || \
00656                                ((BASE) == TIM_DMABase_PSC) || \
00657                                ((BASE) == TIM_DMABase_ARR) || \
00658                                ((BASE) == TIM_DMABase_RCR) || \
00659                                ((BASE) == TIM_DMABase_CCR1) || \
00660                                ((BASE) == TIM_DMABase_CCR2) || \
00661                                ((BASE) == TIM_DMABase_CCR3) || \
00662                                ((BASE) == TIM_DMABase_CCR4) || \
00663                                ((BASE) == TIM_DMABase_BDTR) || \
00664                                ((BASE) == TIM_DMABase_DCR))
00665 /**
00666   * @}
00667   */
00668
00669 /** @defgroup TIM_DMA_Burst_Length
00670   * @{
00671   */
00672
00673 #define TIM_DMABurstLength_1Transfer           ((uint16_t)0x0000)
00674 #define TIM_DMABurstLength_2Transfers          ((uint16_t)0x0100)
00675 #define TIM_DMABurstLength_3Transfers          ((uint16_t)0x0200)
00676 #define TIM_DMABurstLength_4Transfers          ((uint16_t)0x0300)
00677 #define TIM_DMABurstLength_5Transfers          ((uint16_t)0x0400)
00678 #define TIM_DMABurstLength_6Transfers          ((uint16_t)0x0500)
00679 #define TIM_DMABurstLength_7Transfers          ((uint16_t)0x0600)
00680 #define TIM_DMABurstLength_8Transfers          ((uint16_t)0x0700)
00681 #define TIM_DMABurstLength_9Transfers          ((uint16_t)0x0800)
00682 #define TIM_DMABurstLength_10Transfers         ((uint16_t)0x0900)
00683 #define TIM_DMABurstLength_11Transfers         ((uint16_t)0x0A00)
00684 #define TIM_DMABurstLength_12Transfers         ((uint16_t)0x0B00)
00685 #define TIM_DMABurstLength_13Transfers         ((uint16_t)0x0C00)
00686 #define TIM_DMABurstLength_14Transfers         ((uint16_t)0x0D00)
00687 #define TIM_DMABurstLength_15Transfers         ((uint16_t)0x0E00)
00688 #define TIM_DMABurstLength_16Transfers         ((uint16_t)0x0F00)
00689 #define TIM_DMABurstLength_17Transfers         ((uint16_t)0x1000)
00690 #define TIM_DMABurstLength_18Transfers         ((uint16_t)0x1100)
00691 #define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \
00692                                    ((LENGTH) == TIM_DMABurstLength_2Transfers) || \
00693                                    ((LENGTH) == TIM_DMABurstLength_3Transfers) || \
00694                                    ((LENGTH) == TIM_DMABurstLength_4Transfers) || \
00695                                    ((LENGTH) == TIM_DMABurstLength_5Transfers) || \
00696                                    ((LENGTH) == TIM_DMABurstLength_6Transfers) || \
00697                                    ((LENGTH) == TIM_DMABurstLength_7Transfers) || \
00698                                    ((LENGTH) == TIM_DMABurstLength_8Transfers) || \
00699                                    ((LENGTH) == TIM_DMABurstLength_9Transfers) || \
00700                                    ((LENGTH) == TIM_DMABurstLength_10Transfers) || \
00701                                    ((LENGTH) == TIM_DMABurstLength_11Transfers) || \
00702                                    ((LENGTH) == TIM_DMABurstLength_12Transfers) || \
00703                                    ((LENGTH) == TIM_DMABurstLength_13Transfers) || \
00704                                    ((LENGTH) == TIM_DMABurstLength_14Transfers) || \
00705                                    ((LENGTH) == TIM_DMABurstLength_15Transfers) || \
00706                                    ((LENGTH) == TIM_DMABurstLength_16Transfers) || \
00707                                    ((LENGTH) == TIM_DMABurstLength_17Transfers) || \
00708                                    ((LENGTH) == TIM_DMABurstLength_18Transfers))
00709 /**
00710   * @}
00711   */
00712
00713 /** @defgroup TIM_DMA_sources
00714   * @{
00715   */
00716
00717 #define TIM_DMA_Update                     ((uint16_t)0x0100)
00718 #define TIM_DMA_CC1                        ((uint16_t)0x0200)
00719 #define TIM_DMA_CC2                        ((uint16_t)0x0400)
00720 #define TIM_DMA_CC3                        ((uint16_t)0x0800)
00721 #define TIM_DMA_CC4                        ((uint16_t)0x1000)
00722 #define TIM_DMA_COM                        ((uint16_t)0x2000)
00723 #define TIM_DMA_Trigger                    ((uint16_t)0x4000)
00724 #define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000))
00725
00726 /**
00727   * @}
00728   */
00729
00730 /** @defgroup TIM_External_Trigger_Prescaler
00731   * @{
00732   */
00733
00734 #define TIM_ExtTRGPSC_OFF                  ((uint16_t)0x0000)
00735 #define TIM_ExtTRGPSC_DIV2                 ((uint16_t)0x1000)
00736 #define TIM_ExtTRGPSC_DIV4                 ((uint16_t)0x2000)
00737 #define TIM_ExtTRGPSC_DIV8                 ((uint16_t)0x3000)
00738 #define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \
00739                                          ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \
00740                                          ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \
00741                                          ((PRESCALER) == TIM_ExtTRGPSC_DIV8))
00742 /**
00743   * @}
00744   */
00745
00746 /** @defgroup TIM_Internal_Trigger_Selection
00747   * @{
00748   */
00749
00750 #define TIM_TS_ITR0                        ((uint16_t)0x0000)
00751 #define TIM_TS_ITR1                        ((uint16_t)0x0010)
00752 #define TIM_TS_ITR2                        ((uint16_t)0x0020)
00753 #define TIM_TS_ITR3                        ((uint16_t)0x0030)
00754 #define TIM_TS_TI1F_ED                     ((uint16_t)0x0040)
00755 #define TIM_TS_TI1FP1                      ((uint16_t)0x0050)
00756 #define TIM_TS_TI2FP2                      ((uint16_t)0x0060)
00757 #define TIM_TS_ETRF                        ((uint16_t)0x0070)
00758 #define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
00759                                              ((SELECTION) == TIM_TS_ITR1) || \
00760                                              ((SELECTION) == TIM_TS_ITR2) || \
00761                                              ((SELECTION) == TIM_TS_ITR3) || \
00762                                              ((SELECTION) == TIM_TS_TI1F_ED) || \
00763                                              ((SELECTION) == TIM_TS_TI1FP1) || \
00764                                              ((SELECTION) == TIM_TS_TI2FP2) || \
00765                                              ((SELECTION) == TIM_TS_ETRF))
00766 #define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
00767                                                       ((SELECTION) == TIM_TS_ITR1) || \
00768                                                       ((SELECTION) == TIM_TS_ITR2) || \
00769                                                       ((SELECTION) == TIM_TS_ITR3))
00770 /**
00771   * @}
00772   */
00773
00774 /** @defgroup TIM_TIx_External_Clock_Source
00775   * @{
00776   */
00777
00778 #define TIM_TIxExternalCLK1Source_TI1      ((uint16_t)0x0050)
00779 #define TIM_TIxExternalCLK1Source_TI2      ((uint16_t)0x0060)
00780 #define TIM_TIxExternalCLK1Source_TI1ED    ((uint16_t)0x0040)
00781 #define IS_TIM_TIXCLK_SOURCE(SOURCE) (((SOURCE) == TIM_TIxExternalCLK1Source_TI1) || \
00782                                       ((SOURCE) == TIM_TIxExternalCLK1Source_TI2) || \
00783                                       ((SOURCE) == TIM_TIxExternalCLK1Source_TI1ED))
00784 /**
00785   * @}
00786   */
00787
00788 /** @defgroup TIM_External_Trigger_Polarity
00789   * @{
00790   */
00791 #define TIM_ExtTRGPolarity_Inverted        ((uint16_t)0x8000)
00792 #define TIM_ExtTRGPolarity_NonInverted     ((uint16_t)0x0000)
00793 #define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \
00794                                        ((POLARITY) == TIM_ExtTRGPolarity_NonInverted))
00795 /**
00796   * @}
00797   */
00798
00799 /** @defgroup TIM_Prescaler_Reload_Mode
00800   * @{
00801   */
00802
00803 #define TIM_PSCReloadMode_Update           ((uint16_t)0x0000)
00804 #define TIM_PSCReloadMode_Immediate        ((uint16_t)0x0001)
00805 #define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \
00806                                          ((RELOAD) == TIM_PSCReloadMode_Immediate))
00807 /**
00808   * @}
00809   */
00810
00811 /** @defgroup TIM_Forced_Action
00812   * @{
00813   */
00814
00815 #define TIM_ForcedAction_Active            ((uint16_t)0x0050)
00816 #define TIM_ForcedAction_InActive          ((uint16_t)0x0040)
00817 #define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \
00818                                       ((ACTION) == TIM_ForcedAction_InActive))
00819 /**
00820   * @}
00821   */
00822
00823 /** @defgroup TIM_Encoder_Mode
00824   * @{
00825   */
00826
00827 #define TIM_EncoderMode_TI1                ((uint16_t)0x0001)
00828 #define TIM_EncoderMode_TI2                ((uint16_t)0x0002)
00829 #define TIM_EncoderMode_TI12               ((uint16_t)0x0003)
00830 #define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \
00831                                    ((MODE) == TIM_EncoderMode_TI2) || \
00832                                    ((MODE) == TIM_EncoderMode_TI12))
00833 /**
00834   * @}
00835   */
00836
00837
00838 /** @defgroup TIM_Event_Source
00839   * @{
00840   */
00841
00842 #define TIM_EventSource_Update             ((uint16_t)0x0001)
00843 #define TIM_EventSource_CC1                ((uint16_t)0x0002)
00844 #define TIM_EventSource_CC2                ((uint16_t)0x0004)
00845 #define TIM_EventSource_CC3                ((uint16_t)0x0008)
00846 #define TIM_EventSource_CC4                ((uint16_t)0x0010)
00847 #define TIM_EventSource_COM                ((uint16_t)0x0020)
00848 #define TIM_EventSource_Trigger            ((uint16_t)0x0040)
00849 #define TIM_EventSource_Break              ((uint16_t)0x0080)
00850 #define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000))
00851
00852 /**
00853   * @}
00854   */
00855
00856 /** @defgroup TIM_Update_Source
00857   * @{
00858   */
00859
00860 #define TIM_UpdateSource_Global            ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow
00861                                                                    or the setting of UG bit, or an update generation
00862                                                                    through the slave mode controller. */
00863 #define TIM_UpdateSource_Regular           ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */
00864 #define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \
00865                                       ((SOURCE) == TIM_UpdateSource_Regular))
00866 /**
00867   * @}
00868   */
00869
00870 /** @defgroup TIM_Output_Compare_Preload_State
00871   * @{
00872   */
00873
00874 #define TIM_OCPreload_Enable               ((uint16_t)0x0008)
00875 #define TIM_OCPreload_Disable              ((uint16_t)0x0000)
00876 #define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \
00877                                        ((STATE) == TIM_OCPreload_Disable))
00878 /**
00879   * @}
00880   */
00881
00882 /** @defgroup TIM_Output_Compare_Fast_State
00883   * @{
00884   */
00885
00886 #define TIM_OCFast_Enable                  ((uint16_t)0x0004)
00887 #define TIM_OCFast_Disable                 ((uint16_t)0x0000)
00888 #define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \
00889                                     ((STATE) == TIM_OCFast_Disable))
00890
00891 /**
00892   * @}
00893   */
00894
00895 /** @defgroup TIM_Output_Compare_Clear_State
00896   * @{
00897   */
00898
00899 #define TIM_OCClear_Enable                 ((uint16_t)0x0080)
00900 #define TIM_OCClear_Disable                ((uint16_t)0x0000)
00901 #define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \
00902                                      ((STATE) == TIM_OCClear_Disable))
00903 /**
00904   * @}
00905   */
00906
00907 /** @defgroup TIM_Trigger_Output_Source
00908   * @{
00909   */
00910
00911 #define TIM_TRGOSource_Reset               ((uint16_t)0x0000)
00912 #define TIM_TRGOSource_Enable              ((uint16_t)0x0010)
00913 #define TIM_TRGOSource_Update              ((uint16_t)0x0020)
00914 #define TIM_TRGOSource_OC1                 ((uint16_t)0x0030)
00915 #define TIM_TRGOSource_OC1Ref              ((uint16_t)0x0040)
00916 #define TIM_TRGOSource_OC2Ref              ((uint16_t)0x0050)
00917 #define TIM_TRGOSource_OC3Ref              ((uint16_t)0x0060)
00918 #define TIM_TRGOSource_OC4Ref              ((uint16_t)0x0070)
00919 #define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \
00920                                     ((SOURCE) == TIM_TRGOSource_Enable) || \
00921                                     ((SOURCE) == TIM_TRGOSource_Update) || \
00922                                     ((SOURCE) == TIM_TRGOSource_OC1) || \
00923                                     ((SOURCE) == TIM_TRGOSource_OC1Ref) || \
00924                                     ((SOURCE) == TIM_TRGOSource_OC2Ref) || \
00925                                     ((SOURCE) == TIM_TRGOSource_OC3Ref) || \
00926                                     ((SOURCE) == TIM_TRGOSource_OC4Ref))
00927 /**
00928   * @}
00929   */
00930
00931 /** @defgroup TIM_Slave_Mode
00932   * @{
00933   */
00934
00935 #define TIM_SlaveMode_Reset                ((uint16_t)0x0004)
00936 #define TIM_SlaveMode_Gated                ((uint16_t)0x0005)
00937 #define TIM_SlaveMode_Trigger              ((uint16_t)0x0006)
00938 #define TIM_SlaveMode_External1            ((uint16_t)0x0007)
00939 #define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \
00940                                  ((MODE) == TIM_SlaveMode_Gated) || \
00941                                  ((MODE) == TIM_SlaveMode_Trigger) || \
00942                                  ((MODE) == TIM_SlaveMode_External1))
00943 /**
00944   * @}
00945   */
00946
00947 /** @defgroup TIM_Master_Slave_Mode
00948   * @{
00949   */
00950
00951 #define TIM_MasterSlaveMode_Enable         ((uint16_t)0x0080)
00952 #define TIM_MasterSlaveMode_Disable        ((uint16_t)0x0000)
00953 #define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \
00954                                  ((STATE) == TIM_MasterSlaveMode_Disable))
00955 /**
00956   * @}
00957   */
00958
00959 /** @defgroup TIM_Flags
00960   * @{
00961   */
00962
00963 #define TIM_FLAG_Update                    ((uint16_t)0x0001)
00964 #define TIM_FLAG_CC1                       ((uint16_t)0x0002)
00965 #define TIM_FLAG_CC2                       ((uint16_t)0x0004)
00966 #define TIM_FLAG_CC3                       ((uint16_t)0x0008)
00967 #define TIM_FLAG_CC4                       ((uint16_t)0x0010)
00968 #define TIM_FLAG_COM                       ((uint16_t)0x0020)
00969 #define TIM_FLAG_Trigger                   ((uint16_t)0x0040)
00970 #define TIM_FLAG_Break                     ((uint16_t)0x0080)
00971 #define TIM_FLAG_CC1OF                     ((uint16_t)0x0200)
00972 #define TIM_FLAG_CC2OF                     ((uint16_t)0x0400)
00973 #define TIM_FLAG_CC3OF                     ((uint16_t)0x0800)
00974 #define TIM_FLAG_CC4OF                     ((uint16_t)0x1000)
00975 #define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \
00976                                ((FLAG) == TIM_FLAG_CC1) || \
00977                                ((FLAG) == TIM_FLAG_CC2) || \
00978                                ((FLAG) == TIM_FLAG_CC3) || \
00979                                ((FLAG) == TIM_FLAG_CC4) || \
00980                                ((FLAG) == TIM_FLAG_COM) || \
00981                                ((FLAG) == TIM_FLAG_Trigger) || \
00982                                ((FLAG) == TIM_FLAG_Break) || \
00983                                ((FLAG) == TIM_FLAG_CC1OF) || \
00984                                ((FLAG) == TIM_FLAG_CC2OF) || \
00985                                ((FLAG) == TIM_FLAG_CC3OF) || \
00986                                ((FLAG) == TIM_FLAG_CC4OF))
00987
00988
00989 #define IS_TIM_CLEAR_FLAG(TIM_FLAG) ((((TIM_FLAG) & (uint16_t)0xE100) == 0x0000) && ((TIM_FLAG) != 0x0000))
00990 /**
00991   * @}
00992   */
00993
00994 /** @defgroup TIM_Input_Capture_Filer_Value
00995   * @{
00996   */
00997
00998 #define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
00999 /**
01000   * @}
01001   */
01002
01003 /** @defgroup TIM_External_Trigger_Filter
01004   * @{
01005   */
01006
01007 #define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF)
01008 /**
01009   * @}
01010   */
01011
01012 /** @defgroup TIM_Legacy
01013   * @{
01014   */
01015
01016 #define TIM_DMABurstLength_1Byte           TIM_DMABurstLength_1Transfer
01017 #define TIM_DMABurstLength_2Bytes          TIM_DMABurstLength_2Transfers
01018 #define TIM_DMABurstLength_3Bytes          TIM_DMABurstLength_3Transfers
01019 #define TIM_DMABurstLength_4Bytes          TIM_DMABurstLength_4Transfers
01020 #define TIM_DMABurstLength_5Bytes          TIM_DMABurstLength_5Transfers
01021 #define TIM_DMABurstLength_6Bytes          TIM_DMABurstLength_6Transfers
01022 #define TIM_DMABurstLength_7Bytes          TIM_DMABurstLength_7Transfers
01023 #define TIM_DMABurstLength_8Bytes          TIM_DMABurstLength_8Transfers
01024 #define TIM_DMABurstLength_9Bytes          TIM_DMABurstLength_9Transfers
01025 #define TIM_DMABurstLength_10Bytes         TIM_DMABurstLength_10Transfers
01026 #define TIM_DMABurstLength_11Bytes         TIM_DMABurstLength_11Transfers
01027 #define TIM_DMABurstLength_12Bytes         TIM_DMABurstLength_12Transfers
01028 #define TIM_DMABurstLength_13Bytes         TIM_DMABurstLength_13Transfers
01029 #define TIM_DMABurstLength_14Bytes         TIM_DMABurstLength_14Transfers
01030 #define TIM_DMABurstLength_15Bytes         TIM_DMABurstLength_15Transfers
01031 #define TIM_DMABurstLength_16Bytes         TIM_DMABurstLength_16Transfers
01032 #define TIM_DMABurstLength_17Bytes         TIM_DMABurstLength_17Transfers
01033 #define TIM_DMABurstLength_18Bytes         TIM_DMABurstLength_18Transfers
01034 /**
01035   * @}
01036   */
01037
01038 /**
01039   * @}
01040   */
01041
01042 /** @defgroup TIM_Exported_Macros
01043   * @{
01044   */
01045
01046 /**
01047   * @}
01048   */
01049
01050 /** @defgroup TIM_Exported_Functions
01051   * @{
01052   */
01053
01054 void TIM_DeInit(TIM_TypeDef* TIMx);
01055 void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
01056 void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
01057 void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
01058 void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
01059 void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
01060 void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
01061 void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
01062 void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct);
01063 void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
01064 void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct);
01065 void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct);
01066 void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct);
01067 void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);
01068 void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState);
01069 void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState);
01070 void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource);
01071 void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength);
01072 void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState);
01073 void TIM_InternalClockConfig(TIM_TypeDef* TIMx);
01074 void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
01075 void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
01076                                 uint16_t TIM_ICPolarity, uint16_t ICFilter);
01077 void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
01078                              uint16_t ExtTRGFilter);
01079 void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
01080                              uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);
01081 void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
01082                    uint16_t ExtTRGFilter);
01083 void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode);
01084 void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode);
01085 void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
01086 void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
01087                                 uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity);
01088 void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
01089 void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
01090 void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
01091 void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
01092 void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
01093 void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState);
01094 void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState);
01095 void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState);
01096 void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
01097 void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
01098 void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
01099 void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
01100 void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
01101 void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
01102 void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
01103 void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
01104 void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
01105 void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
01106 void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
01107 void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
01108 void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
01109 void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
01110 void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
01111 void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
01112 void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
01113 void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
01114 void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
01115 void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx);
01116 void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN);
01117 void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode);
01118 void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
01119 void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource);
01120 void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState);
01121 void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode);
01122 void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource);
01123 void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);
01124 void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode);
01125 void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter);
01126 void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload);
01127 void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1);
01128 void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2);
01129 void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3);
01130 void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4);
01131 void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
01132 void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
01133 void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
01134 void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
01135 void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD);
01136 uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx);
01137 uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx);
01138 uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx);
01139 uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx);
01140 uint16_t TIM_GetCounter(TIM_TypeDef* TIMx);
01141 uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx);
01142 FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
01143 void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
01144 ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT);
01145 void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT);
01146
01147 #ifdef __cplusplus
01148 }
01149 #endif
01150
01151 #endif /*__STM32F10x_TIM_H */
01152 /**
01153   * @}
01154   */
01155
01156 /**
01157   * @}
01158   */
01159
01160 /**
01161   * @}
01162   */
01163
01164 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_usart.c Source File

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stm32f10x_usart.c

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f10x_usart.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    11-March-2011
00007   * @brief   This file provides all the USART firmware functions.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x_usart.h"
00024 #include "stm32f10x_rcc.h"
00025
00026 /** @addtogroup STM32F10x_StdPeriph_Driver
00027   * @{
00028   */
00029
00030 /** @defgroup USART
00031   * @brief USART driver modules
00032   * @{
00033   */
00034
00035 /** @defgroup USART_Private_TypesDefinitions
00036   * @{
00037   */
00038
00039 /**
00040   * @}
00041   */
00042
00043 /** @defgroup USART_Private_Defines
00044   * @{
00045   */
00046
00047 #define CR1_UE_Set                ((uint16_t)0x2000)  /*!< USART Enable Mask */
00048 #define CR1_UE_Reset              ((uint16_t)0xDFFF)  /*!< USART Disable Mask */
00049
00050 #define CR1_WAKE_Mask             ((uint16_t)0xF7FF)  /*!< USART WakeUp Method Mask */
00051
00052 #define CR1_RWU_Set               ((uint16_t)0x0002)  /*!< USART mute mode Enable Mask */
00053 #define CR1_RWU_Reset             ((uint16_t)0xFFFD)  /*!< USART mute mode Enable Mask */
00054 #define CR1_SBK_Set               ((uint16_t)0x0001)  /*!< USART Break Character send Mask */
00055 #define CR1_CLEAR_Mask            ((uint16_t)0xE9F3)  /*!< USART CR1 Mask */
00056 #define CR2_Address_Mask          ((uint16_t)0xFFF0)  /*!< USART address Mask */
00057
00058 #define CR2_LINEN_Set              ((uint16_t)0x4000)  /*!< USART LIN Enable Mask */
00059 #define CR2_LINEN_Reset            ((uint16_t)0xBFFF)  /*!< USART LIN Disable Mask */
00060
00061 #define CR2_LBDL_Mask             ((uint16_t)0xFFDF)  /*!< USART LIN Break detection Mask */
00062 #define CR2_STOP_CLEAR_Mask       ((uint16_t)0xCFFF)  /*!< USART CR2 STOP Bits Mask */
00063 #define CR2_CLOCK_CLEAR_Mask      ((uint16_t)0xF0FF)  /*!< USART CR2 Clock Mask */
00064
00065 #define CR3_SCEN_Set              ((uint16_t)0x0020)  /*!< USART SC Enable Mask */
00066 #define CR3_SCEN_Reset            ((uint16_t)0xFFDF)  /*!< USART SC Disable Mask */
00067
00068 #define CR3_NACK_Set              ((uint16_t)0x0010)  /*!< USART SC NACK Enable Mask */
00069 #define CR3_NACK_Reset            ((uint16_t)0xFFEF)  /*!< USART SC NACK Disable Mask */
00070
00071 #define CR3_HDSEL_Set             ((uint16_t)0x0008)  /*!< USART Half-Duplex Enable Mask */
00072 #define CR3_HDSEL_Reset           ((uint16_t)0xFFF7)  /*!< USART Half-Duplex Disable Mask */
00073
00074 #define CR3_IRLP_Mask             ((uint16_t)0xFFFB)  /*!< USART IrDA LowPower mode Mask */
00075 #define CR3_CLEAR_Mask            ((uint16_t)0xFCFF)  /*!< USART CR3 Mask */
00076
00077 #define CR3_IREN_Set              ((uint16_t)0x0002)  /*!< USART IrDA Enable Mask */
00078 #define CR3_IREN_Reset            ((uint16_t)0xFFFD)  /*!< USART IrDA Disable Mask */
00079 #define GTPR_LSB_Mask             ((uint16_t)0x00FF)  /*!< Guard Time Register LSB Mask */
00080 #define GTPR_MSB_Mask             ((uint16_t)0xFF00)  /*!< Guard Time Register MSB Mask */
00081 #define IT_Mask                   ((uint16_t)0x001F)  /*!< USART Interrupt Mask */
00082
00083 /* USART OverSampling-8 Mask */
00084 #define CR1_OVER8_Set             ((u16)0x8000)  /* USART OVER8 mode Enable Mask */
00085 #define CR1_OVER8_Reset           ((u16)0x7FFF)  /* USART OVER8 mode Disable Mask */
00086
00087 /* USART One Bit Sampling Mask */
00088 #define CR3_ONEBITE_Set           ((u16)0x0800)  /* USART ONEBITE mode Enable Mask */
00089 #define CR3_ONEBITE_Reset         ((u16)0xF7FF)  /* USART ONEBITE mode Disable Mask */
00090
00091 /**
00092   * @}
00093   */
00094
00095 /** @defgroup USART_Private_Macros
00096   * @{
00097   */
00098
00099 /**
00100   * @}
00101   */
00102
00103 /** @defgroup USART_Private_Variables
00104   * @{
00105   */
00106
00107 /**
00108   * @}
00109   */
00110
00111 /** @defgroup USART_Private_FunctionPrototypes
00112   * @{
00113   */
00114
00115 /**
00116   * @}
00117   */
00118
00119 /** @defgroup USART_Private_Functions
00120   * @{
00121   */
00122
00123 /**
00124   * @brief  Deinitializes the USARTx peripheral registers to their default reset values.
00125   * @param  USARTx: Select the USART or the UART peripheral.
00126   *   This parameter can be one of the following values:
00127   *      USART1, USART2, USART3, UART4 or UART5.
00128   * @retval None
00129   */
00130 void USART_DeInit(USART_TypeDef* USARTx)
00131 {
00132   /* Check the parameters */
00133   assert_param(IS_USART_ALL_PERIPH(USARTx));
00134
00135   if (USARTx == USART1)
00136   {
00137     RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE);
00138     RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE);
00139   }
00140   else if (USARTx == USART2)
00141   {
00142     RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE);
00143     RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE);
00144   }
00145   else if (USARTx == USART3)
00146   {
00147     RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE);
00148     RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE);
00149   }
00150   else if (USARTx == UART4)
00151   {
00152     RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE);
00153     RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE);
00154   }
00155   else
00156   {
00157     if (USARTx == UART5)
00158     {
00159       RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE);
00160       RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE);
00161     }
00162   }
00163 }
00164
00165 /**
00166   * @brief  Initializes the USARTx peripheral according to the specified
00167   *         parameters in the USART_InitStruct .
00168   * @param  USARTx: Select the USART or the UART peripheral.
00169   *   This parameter can be one of the following values:
00170   *   USART1, USART2, USART3, UART4 or UART5.
00171   * @param  USART_InitStruct: pointer to a USART_InitTypeDef structure
00172   *         that contains the configuration information for the specified USART
00173   *         peripheral.
00174   * @retval None
00175   */
00176 void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct)
00177 {
00178   uint32_t tmpreg = 0x00, apbclock = 0x00;
00179   uint32_t integerdivider = 0x00;
00180   uint32_t fractionaldivider = 0x00;
00181   uint32_t usartxbase = 0;
00182   RCC_ClocksTypeDef RCC_ClocksStatus;
00183   /* Check the parameters */
00184   assert_param(IS_USART_ALL_PERIPH(USARTx));
00185   assert_param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate));
00186   assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength));
00187   assert_param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits));
00188   assert_param(IS_USART_PARITY(USART_InitStruct->USART_Parity));
00189   assert_param(IS_USART_MODE(USART_InitStruct->USART_Mode));
00190   assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl));
00191   /* The hardware flow control is available only for USART1, USART2 and USART3 */
00192   if (USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None)
00193   {
00194     assert_param(IS_USART_123_PERIPH(USARTx));
00195   }
00196
00197   usartxbase = (uint32_t)USARTx;
00198
00199 /*---------------------------- USART CR2 Configuration -----------------------*/
00200   tmpreg = USARTx->CR2;
00201   /* Clear STOP[13:12] bits */
00202   tmpreg &= CR2_STOP_CLEAR_Mask;
00203   /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit ------------*/
00204   /* Set STOP[13:12] bits according to USART_StopBits value */
00205   tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits;
00206
00207   /* Write to USART CR2 */
00208   USARTx->CR2 = (uint16_t)tmpreg;
00209
00210 /*---------------------------- USART CR1 Configuration -----------------------*/
00211   tmpreg = USARTx->CR1;
00212   /* Clear M, PCE, PS, TE and RE bits */
00213   tmpreg &= CR1_CLEAR_Mask;
00214   /* Configure the USART Word Length, Parity and mode ----------------------- */
00215   /* Set the M bits according to USART_WordLength value */
00216   /* Set PCE and PS bits according to USART_Parity value */
00217   /* Set TE and RE bits according to USART_Mode value */
00218   tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity |
00219             USART_InitStruct->USART_Mode;
00220   /* Write to USART CR1 */
00221   USARTx->CR1 = (uint16_t)tmpreg;
00222
00223 /*---------------------------- USART CR3 Configuration -----------------------*/
00224   tmpreg = USARTx->CR3;
00225   /* Clear CTSE and RTSE bits */
00226   tmpreg &= CR3_CLEAR_Mask;
00227   /* Configure the USART HFC -------------------------------------------------*/
00228   /* Set CTSE and RTSE bits according to USART_HardwareFlowControl value */
00229   tmpreg |= USART_InitStruct->USART_HardwareFlowControl;
00230   /* Write to USART CR3 */
00231   USARTx->CR3 = (uint16_t)tmpreg;
00232
00233 /*---------------------------- USART BRR Configuration -----------------------*/
00234   /* Configure the USART Baud Rate -------------------------------------------*/
00235   RCC_GetClocksFreq(&RCC_ClocksStatus);
00236   if (usartxbase == USART1_BASE)
00237   {
00238     apbclock = RCC_ClocksStatus.PCLK2_Frequency;
00239   }
00240   else
00241   {
00242     apbclock = RCC_ClocksStatus.PCLK1_Frequency;
00243   }
00244
00245   /* Determine the integer part */
00246   if ((USARTx->CR1 & CR1_OVER8_Set) != 0)
00247   {
00248     /* Integer part computing in case Oversampling mode is 8 Samples */
00249     integerdivider = ((25 * apbclock) / (2 * (USART_InitStruct->USART_BaudRate)));
00250   }
00251   else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */
00252   {
00253     /* Integer part computing in case Oversampling mode is 16 Samples */
00254     integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate)));
00255   }
00256   tmpreg = (integerdivider / 100) << 4;
00257
00258   /* Determine the fractional part */
00259   fractionaldivider = integerdivider - (100 * (tmpreg >> 4));
00260
00261   /* Implement the fractional part in the register */
00262   if ((USARTx->CR1 & CR1_OVER8_Set) != 0)
00263   {
00264     tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07);
00265   }
00266   else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */
00267   {
00268     tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F);
00269   }
00270
00271   /* Write to USART BRR */
00272   USARTx->BRR = (uint16_t)tmpreg;
00273 }
00274
00275 /**
00276   * @brief  Fills each USART_InitStruct member with its default value.
00277   * @param  USART_InitStruct: pointer to a USART_InitTypeDef structure
00278   *         which will be initialized.
00279   * @retval None
00280   */
00281 void USART_StructInit(USART_InitTypeDef* USART_InitStruct)
00282 {
00283   /* USART_InitStruct members default value */
00284   USART_InitStruct->USART_BaudRate = 9600;
00285   USART_InitStruct->USART_WordLength = USART_WordLength_8b;
00286   USART_InitStruct->USART_StopBits = USART_StopBits_1;
00287   USART_InitStruct->USART_Parity = USART_Parity_No ;
00288   USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
00289   USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None;
00290 }
00291
00292 /**
00293   * @brief  Initializes the USARTx peripheral Clock according to the
00294   *          specified parameters in the USART_ClockInitStruct .
00295   * @param  USARTx: where x can be 1, 2, 3 to select the USART peripheral.
00296   * @param  USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef
00297   *         structure that contains the configuration information for the specified
00298   *         USART peripheral.
00299   * @note The Smart Card and Synchronous modes are not available for UART4 and UART5.
00300   * @retval None
00301   */
00302 void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct)
00303 {
00304   uint32_t tmpreg = 0x00;
00305   /* Check the parameters */
00306   assert_param(IS_USART_123_PERIPH(USARTx));
00307   assert_param(IS_USART_CLOCK(USART_ClockInitStruct->USART_Clock));
00308   assert_param(IS_USART_CPOL(USART_ClockInitStruct->USART_CPOL));
00309   assert_param(IS_USART_CPHA(USART_ClockInitStruct->USART_CPHA));
00310   assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->USART_LastBit));
00311
00312 /*---------------------------- USART CR2 Configuration -----------------------*/
00313   tmpreg = USARTx->CR2;
00314   /* Clear CLKEN, CPOL, CPHA and LBCL bits */
00315   tmpreg &= CR2_CLOCK_CLEAR_Mask;
00316   /* Configure the USART Clock, CPOL, CPHA and LastBit ------------*/
00317   /* Set CLKEN bit according to USART_Clock value */
00318   /* Set CPOL bit according to USART_CPOL value */
00319   /* Set CPHA bit according to USART_CPHA value */
00320   /* Set LBCL bit according to USART_LastBit value */
00321   tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL |
00322                  USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit;
00323   /* Write to USART CR2 */
00324   USARTx->CR2 = (uint16_t)tmpreg;
00325 }
00326
00327 /**
00328   * @brief  Fills each USART_ClockInitStruct member with its default value.
00329   * @param  USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef
00330   *         structure which will be initialized.
00331   * @retval None
00332   */
00333 void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct)
00334 {
00335   /* USART_ClockInitStruct members default value */
00336   USART_ClockInitStruct->USART_Clock = USART_Clock_Disable;
00337   USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low;
00338   USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge;
00339   USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable;
00340 }
00341
00342 /**
00343   * @brief  Enables or disables the specified USART peripheral.
00344   * @param  USARTx: Select the USART or the UART peripheral.
00345   *         This parameter can be one of the following values:
00346   *           USART1, USART2, USART3, UART4 or UART5.
00347   * @param  NewState: new state of the USARTx peripheral.
00348   *         This parameter can be: ENABLE or DISABLE.
00349   * @retval None
00350   */
00351 void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState)
00352 {
00353   /* Check the parameters */
00354   assert_param(IS_USART_ALL_PERIPH(USARTx));
00355   assert_param(IS_FUNCTIONAL_STATE(NewState));
00356
00357   if (NewState != DISABLE)
00358   {
00359     /* Enable the selected USART by setting the UE bit in the CR1 register */
00360     USARTx->CR1 |= CR1_UE_Set;
00361   }
00362   else
00363   {
00364     /* Disable the selected USART by clearing the UE bit in the CR1 register */
00365     USARTx->CR1 &= CR1_UE_Reset;
00366   }
00367 }
00368
00369 /**
00370   * @brief  Enables or disables the specified USART interrupts.
00371   * @param  USARTx: Select the USART or the UART peripheral.
00372   *   This parameter can be one of the following values:
00373   *   USART1, USART2, USART3, UART4 or UART5.
00374   * @param  USART_IT: specifies the USART interrupt sources to be enabled or disabled.
00375   *   This parameter can be one of the following values:
00376   *     @arg USART_IT_CTS:  CTS change interrupt (not available for UART4 and UART5)
00377   *     @arg USART_IT_LBD:  LIN Break detection interrupt
00378   *     @arg USART_IT_TXE:  Transmit Data Register empty interrupt
00379   *     @arg USART_IT_TC:   Transmission complete interrupt
00380   *     @arg USART_IT_RXNE: Receive Data register not empty interrupt
00381   *     @arg USART_IT_IDLE: Idle line detection interrupt
00382   *     @arg USART_IT_PE:   Parity Error interrupt
00383   *     @arg USART_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)
00384   * @param  NewState: new state of the specified USARTx interrupts.
00385   *   This parameter can be: ENABLE or DISABLE.
00386   * @retval None
00387   */
00388 void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState)
00389 {
00390   uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00;
00391   uint32_t usartxbase = 0x00;
00392   /* Check the parameters */
00393   assert_param(IS_USART_ALL_PERIPH(USARTx));
00394   assert_param(IS_USART_CONFIG_IT(USART_IT));
00395   assert_param(IS_FUNCTIONAL_STATE(NewState));
00396   /* The CTS interrupt is not available for UART4 and UART5 */
00397   if (USART_IT == USART_IT_CTS)
00398   {
00399     assert_param(IS_USART_123_PERIPH(USARTx));
00400   }
00401
00402   usartxbase = (uint32_t)USARTx;
00403
00404   /* Get the USART register index */
00405   usartreg = (((uint8_t)USART_IT) >> 0x05);
00406
00407   /* Get the interrupt position */
00408   itpos = USART_IT & IT_Mask;
00409   itmask = (((uint32_t)0x01) << itpos);
00410
00411   if (usartreg == 0x01) /* The IT is in CR1 register */
00412   {
00413     usartxbase += 0x0C;
00414   }
00415   else if (usartreg == 0x02) /* The IT is in CR2 register */
00416   {
00417     usartxbase += 0x10;
00418   }
00419   else /* The IT is in CR3 register */
00420   {
00421     usartxbase += 0x14;
00422   }
00423   if (NewState != DISABLE)
00424   {
00425     *(__IO uint32_t*)usartxbase  |= itmask;
00426   }
00427   else
00428   {
00429     *(__IO uint32_t*)usartxbase &= ~itmask;
00430   }
00431 }
00432
00433 /**
00434   * @brief  Enables or disables the USART’s DMA interface.
00435   * @param  USARTx: Select the USART or the UART peripheral.
00436   *   This parameter can be one of the following values:
00437   *   USART1, USART2, USART3, UART4 or UART5.
00438   * @param  USART_DMAReq: specifies the DMA request.
00439   *   This parameter can be any combination of the following values:
00440   *     @arg USART_DMAReq_Tx: USART DMA transmit request
00441   *     @arg USART_DMAReq_Rx: USART DMA receive request
00442   * @param  NewState: new state of the DMA Request sources.
00443   *   This parameter can be: ENABLE or DISABLE.
00444   * @note The DMA mode is not available for UART5 except in the STM32
00445   *       High density value line devices(STM32F10X_HD_VL).
00446   * @retval None
00447   */
00448 void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState)
00449 {
00450   /* Check the parameters */
00451   assert_param(IS_USART_ALL_PERIPH(USARTx));
00452   assert_param(IS_USART_DMAREQ(USART_DMAReq));
00453   assert_param(IS_FUNCTIONAL_STATE(NewState));
00454   if (NewState != DISABLE)
00455   {
00456     /* Enable the DMA transfer for selected requests by setting the DMAT and/or
00457        DMAR bits in the USART CR3 register */
00458     USARTx->CR3 |= USART_DMAReq;
00459   }
00460   else
00461   {
00462     /* Disable the DMA transfer for selected requests by clearing the DMAT and/or
00463        DMAR bits in the USART CR3 register */
00464     USARTx->CR3 &= (uint16_t)~USART_DMAReq;
00465   }
00466 }
00467
00468 /**
00469   * @brief  Sets the address of the USART node.
00470   * @param  USARTx: Select the USART or the UART peripheral.
00471   *   This parameter can be one of the following values:
00472   *   USART1, USART2, USART3, UART4 or UART5.
00473   * @param  USART_Address: Indicates the address of the USART node.
00474   * @retval None
00475   */
00476 void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address)
00477 {
00478   /* Check the parameters */
00479   assert_param(IS_USART_ALL_PERIPH(USARTx));
00480   assert_param(IS_USART_ADDRESS(USART_Address));
00481
00482   /* Clear the USART address */
00483   USARTx->CR2 &= CR2_Address_Mask;
00484   /* Set the USART address node */
00485   USARTx->CR2 |= USART_Address;
00486 }
00487
00488 /**
00489   * @brief  Selects the USART WakeUp method.
00490   * @param  USARTx: Select the USART or the UART peripheral.
00491   *   This parameter can be one of the following values:
00492   *   USART1, USART2, USART3, UART4 or UART5.
00493   * @param  USART_WakeUp: specifies the USART wakeup method.
00494   *   This parameter can be one of the following values:
00495   *     @arg USART_WakeUp_IdleLine: WakeUp by an idle line detection
00496   *     @arg USART_WakeUp_AddressMark: WakeUp by an address mark
00497   * @retval None
00498   */
00499 void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp)
00500 {
00501   /* Check the parameters */
00502   assert_param(IS_USART_ALL_PERIPH(USARTx));
00503   assert_param(IS_USART_WAKEUP(USART_WakeUp));
00504
00505   USARTx->CR1 &= CR1_WAKE_Mask;
00506   USARTx->CR1 |= USART_WakeUp;
00507 }
00508
00509 /**
00510   * @brief  Determines if the USART is in mute mode or not.
00511   * @param  USARTx: Select the USART or the UART peripheral.
00512   *   This parameter can be one of the following values:
00513   *   USART1, USART2, USART3, UART4 or UART5.
00514   * @param  NewState: new state of the USART mute mode.
00515   *   This parameter can be: ENABLE or DISABLE.
00516   * @retval None
00517   */
00518 void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState)
00519 {
00520   /* Check the parameters */
00521   assert_param(IS_USART_ALL_PERIPH(USARTx));
00522   assert_param(IS_FUNCTIONAL_STATE(NewState));
00523
00524   if (NewState != DISABLE)
00525   {
00526     /* Enable the USART mute mode  by setting the RWU bit in the CR1 register */
00527     USARTx->CR1 |= CR1_RWU_Set;
00528   }
00529   else
00530   {
00531     /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */
00532     USARTx->CR1 &= CR1_RWU_Reset;
00533   }
00534 }
00535
00536 /**
00537   * @brief  Sets the USART LIN Break detection length.
00538   * @param  USARTx: Select the USART or the UART peripheral.
00539   *   This parameter can be one of the following values:
00540   *   USART1, USART2, USART3, UART4 or UART5.
00541   * @param  USART_LINBreakDetectLength: specifies the LIN break detection length.
00542   *   This parameter can be one of the following values:
00543   *     @arg USART_LINBreakDetectLength_10b: 10-bit break detection
00544   *     @arg USART_LINBreakDetectLength_11b: 11-bit break detection
00545   * @retval None
00546   */
00547 void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength)
00548 {
00549   /* Check the parameters */
00550   assert_param(IS_USART_ALL_PERIPH(USARTx));
00551   assert_param(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength));
00552
00553   USARTx->CR2 &= CR2_LBDL_Mask;
00554   USARTx->CR2 |= USART_LINBreakDetectLength;
00555 }
00556
00557 /**
00558   * @brief  Enables or disables the USART’s LIN mode.
00559   * @param  USARTx: Select the USART or the UART peripheral.
00560   *   This parameter can be one of the following values:
00561   *   USART1, USART2, USART3, UART4 or UART5.
00562   * @param  NewState: new state of the USART LIN mode.
00563   *   This parameter can be: ENABLE or DISABLE.
00564   * @retval None
00565   */
00566 void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState)
00567 {
00568   /* Check the parameters */
00569   assert_param(IS_USART_ALL_PERIPH(USARTx));
00570   assert_param(IS_FUNCTIONAL_STATE(NewState));
00571
00572   if (NewState != DISABLE)
00573   {
00574     /* Enable the LIN mode by setting the LINEN bit in the CR2 register */
00575     USARTx->CR2 |= CR2_LINEN_Set;
00576   }
00577   else
00578   {
00579     /* Disable the LIN mode by clearing the LINEN bit in the CR2 register */
00580     USARTx->CR2 &= CR2_LINEN_Reset;
00581   }
00582 }
00583
00584 /**
00585   * @brief  Transmits single data through the USARTx peripheral.
00586   * @param  USARTx: Select the USART or the UART peripheral.
00587   *   This parameter can be one of the following values:
00588   *   USART1, USART2, USART3, UART4 or UART5.
00589   * @param  Data: the data to transmit.
00590   * @retval None
00591   */
00592 void USART_SendData(USART_TypeDef* USARTx, uint16_t Data)
00593 {
00594   /* Check the parameters */
00595   assert_param(IS_USART_ALL_PERIPH(USARTx));
00596   assert_param(IS_USART_DATA(Data));
00597
00598   /* Transmit Data */
00599   USARTx->DR = (Data & (uint16_t)0x01FF);
00600 }
00601
00602 /**
00603   * @brief  Returns the most recent received data by the USARTx peripheral.
00604   * @param  USARTx: Select the USART or the UART peripheral.
00605   *   This parameter can be one of the following values:
00606   *   USART1, USART2, USART3, UART4 or UART5.
00607   * @retval The received data.
00608   */
00609 uint16_t USART_ReceiveData(USART_TypeDef* USARTx)
00610 {
00611   /* Check the parameters */
00612   assert_param(IS_USART_ALL_PERIPH(USARTx));
00613
00614   /* Receive Data */
00615   return (uint16_t)(USARTx->DR & (uint16_t)0x01FF);
00616 }
00617
00618 /**
00619   * @brief  Transmits break characters.
00620   * @param  USARTx: Select the USART or the UART peripheral.
00621   *   This parameter can be one of the following values:
00622   *   USART1, USART2, USART3, UART4 or UART5.
00623   * @retval None
00624   */
00625 void USART_SendBreak(USART_TypeDef* USARTx)
00626 {
00627   /* Check the parameters */
00628   assert_param(IS_USART_ALL_PERIPH(USARTx));
00629
00630   /* Send break characters */
00631   USARTx->CR1 |= CR1_SBK_Set;
00632 }
00633
00634 /**
00635   * @brief  Sets the specified USART guard time.
00636   * @param  USARTx: where x can be 1, 2 or 3 to select the USART peripheral.
00637   * @param  USART_GuardTime: specifies the guard time.
00638   * @note The guard time bits are not available for UART4 and UART5.
00639   * @retval None
00640   */
00641 void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime)
00642 {
00643   /* Check the parameters */
00644   assert_param(IS_USART_123_PERIPH(USARTx));
00645
00646   /* Clear the USART Guard time */
00647   USARTx->GTPR &= GTPR_LSB_Mask;
00648   /* Set the USART guard time */
00649   USARTx->GTPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08);
00650 }
00651
00652 /**
00653   * @brief  Sets the system clock prescaler.
00654   * @param  USARTx: Select the USART or the UART peripheral.
00655   *   This parameter can be one of the following values:
00656   *   USART1, USART2, USART3, UART4 or UART5.
00657   * @param  USART_Prescaler: specifies the prescaler clock.
00658   * @note   The function is used for IrDA mode with UART4 and UART5.
00659   * @retval None
00660   */
00661 void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler)
00662 {
00663   /* Check the parameters */
00664   assert_param(IS_USART_ALL_PERIPH(USARTx));
00665
00666   /* Clear the USART prescaler */
00667   USARTx->GTPR &= GTPR_MSB_Mask;
00668   /* Set the USART prescaler */
00669   USARTx->GTPR |= USART_Prescaler;
00670 }
00671
00672 /**
00673   * @brief  Enables or disables the USART’s Smart Card mode.
00674   * @param  USARTx: where x can be 1, 2 or 3 to select the USART peripheral.
00675   * @param  NewState: new state of the Smart Card mode.
00676   *   This parameter can be: ENABLE or DISABLE.
00677   * @note The Smart Card mode is not available for UART4 and UART5.
00678   * @retval None
00679   */
00680 void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState)
00681 {
00682   /* Check the parameters */
00683   assert_param(IS_USART_123_PERIPH(USARTx));
00684   assert_param(IS_FUNCTIONAL_STATE(NewState));
00685   if (NewState != DISABLE)
00686   {
00687     /* Enable the SC mode by setting the SCEN bit in the CR3 register */
00688     USARTx->CR3 |= CR3_SCEN_Set;
00689   }
00690   else
00691   {
00692     /* Disable the SC mode by clearing the SCEN bit in the CR3 register */
00693     USARTx->CR3 &= CR3_SCEN_Reset;
00694   }
00695 }
00696
00697 /**
00698   * @brief  Enables or disables NACK transmission.
00699   * @param  USARTx: where x can be 1, 2 or 3 to select the USART peripheral.
00700   * @param  NewState: new state of the NACK transmission.
00701   *   This parameter can be: ENABLE or DISABLE.
00702   * @note The Smart Card mode is not available for UART4 and UART5.
00703   * @retval None
00704   */
00705 void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState)
00706 {
00707   /* Check the parameters */
00708   assert_param(IS_USART_123_PERIPH(USARTx));
00709   assert_param(IS_FUNCTIONAL_STATE(NewState));
00710   if (NewState != DISABLE)
00711   {
00712     /* Enable the NACK transmission by setting the NACK bit in the CR3 register */
00713     USARTx->CR3 |= CR3_NACK_Set;
00714   }
00715   else
00716   {
00717     /* Disable the NACK transmission by clearing the NACK bit in the CR3 register */
00718     USARTx->CR3 &= CR3_NACK_Reset;
00719   }
00720 }
00721
00722 /**
00723   * @brief  Enables or disables the USART’s Half Duplex communication.
00724   * @param  USARTx: Select the USART or the UART peripheral.
00725   *   This parameter can be one of the following values:
00726   *   USART1, USART2, USART3, UART4 or UART5.
00727   * @param  NewState: new state of the USART Communication.
00728   *   This parameter can be: ENABLE or DISABLE.
00729   * @retval None
00730   */
00731 void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState)
00732 {
00733   /* Check the parameters */
00734   assert_param(IS_USART_ALL_PERIPH(USARTx));
00735   assert_param(IS_FUNCTIONAL_STATE(NewState));
00736
00737   if (NewState != DISABLE)
00738   {
00739     /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
00740     USARTx->CR3 |= CR3_HDSEL_Set;
00741   }
00742   else
00743   {
00744     /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CR3 register */
00745     USARTx->CR3 &= CR3_HDSEL_Reset;
00746   }
00747 }
00748
00749
00750 /**
00751   * @brief  Enables or disables the USART's 8x oversampling mode.
00752   * @param  USARTx: Select the USART or the UART peripheral.
00753   *   This parameter can be one of the following values:
00754   *   USART1, USART2, USART3, UART4 or UART5.
00755   * @param  NewState: new state of the USART one bit sampling method.
00756   *   This parameter can be: ENABLE or DISABLE.
00757   * @note
00758   *     This function has to be called before calling USART_Init()
00759   *     function in order to have correct baudrate Divider value.
00760   * @retval None
00761   */
00762 void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState)
00763 {
00764   /* Check the parameters */
00765   assert_param(IS_USART_ALL_PERIPH(USARTx));
00766   assert_param(IS_FUNCTIONAL_STATE(NewState));
00767
00768   if (NewState != DISABLE)
00769   {
00770     /* Enable the 8x Oversampling mode by setting the OVER8 bit in the CR1 register */
00771     USARTx->CR1 |= CR1_OVER8_Set;
00772   }
00773   else
00774   {
00775     /* Disable the 8x Oversampling mode by clearing the OVER8 bit in the CR1 register */
00776     USARTx->CR1 &= CR1_OVER8_Reset;
00777   }
00778 }
00779
00780 /**
00781   * @brief  Enables or disables the USART's one bit sampling method.
00782   * @param  USARTx: Select the USART or the UART peripheral.
00783   *   This parameter can be one of the following values:
00784   *   USART1, USART2, USART3, UART4 or UART5.
00785   * @param  NewState: new state of the USART one bit sampling method.
00786   *   This parameter can be: ENABLE or DISABLE.
00787   * @retval None
00788   */
00789 void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState)
00790 {
00791   /* Check the parameters */
00792   assert_param(IS_USART_ALL_PERIPH(USARTx));
00793   assert_param(IS_FUNCTIONAL_STATE(NewState));
00794
00795   if (NewState != DISABLE)
00796   {
00797     /* Enable the one bit method by setting the ONEBITE bit in the CR3 register */
00798     USARTx->CR3 |= CR3_ONEBITE_Set;
00799   }
00800   else
00801   {
00802     /* Disable tthe one bit method by clearing the ONEBITE bit in the CR3 register */
00803     USARTx->CR3 &= CR3_ONEBITE_Reset;
00804   }
00805 }
00806
00807 /**
00808   * @brief  Configures the USART's IrDA interface.
00809   * @param  USARTx: Select the USART or the UART peripheral.
00810   *   This parameter can be one of the following values:
00811   *   USART1, USART2, USART3, UART4 or UART5.
00812   * @param  USART_IrDAMode: specifies the IrDA mode.
00813   *   This parameter can be one of the following values:
00814   *     @arg USART_IrDAMode_LowPower
00815   *     @arg USART_IrDAMode_Normal
00816   * @retval None
00817   */
00818 void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode)
00819 {
00820   /* Check the parameters */
00821   assert_param(IS_USART_ALL_PERIPH(USARTx));
00822   assert_param(IS_USART_IRDA_MODE(USART_IrDAMode));
00823
00824   USARTx->CR3 &= CR3_IRLP_Mask;
00825   USARTx->CR3 |= USART_IrDAMode;
00826 }
00827
00828 /**
00829   * @brief  Enables or disables the USART's IrDA interface.
00830   * @param  USARTx: Select the USART or the UART peripheral.
00831   *   This parameter can be one of the following values:
00832   *   USART1, USART2, USART3, UART4 or UART5.
00833   * @param  NewState: new state of the IrDA mode.
00834   *   This parameter can be: ENABLE or DISABLE.
00835   * @retval None
00836   */
00837 void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState)
00838 {
00839   /* Check the parameters */
00840   assert_param(IS_USART_ALL_PERIPH(USARTx));
00841   assert_param(IS_FUNCTIONAL_STATE(NewState));
00842
00843   if (NewState != DISABLE)
00844   {
00845     /* Enable the IrDA mode by setting the IREN bit in the CR3 register */
00846     USARTx->CR3 |= CR3_IREN_Set;
00847   }
00848   else
00849   {
00850     /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */
00851     USARTx->CR3 &= CR3_IREN_Reset;
00852   }
00853 }
00854
00855 /**
00856   * @brief  Checks whether the specified USART flag is set or not.
00857   * @param  USARTx: Select the USART or the UART peripheral.
00858   *   This parameter can be one of the following values:
00859   *   USART1, USART2, USART3, UART4 or UART5.
00860   * @param  USART_FLAG: specifies the flag to check.
00861   *   This parameter can be one of the following values:
00862   *     @arg USART_FLAG_CTS:  CTS Change flag (not available for UART4 and UART5)
00863   *     @arg USART_FLAG_LBD:  LIN Break detection flag
00864   *     @arg USART_FLAG_TXE:  Transmit data register empty flag
00865   *     @arg USART_FLAG_TC:   Transmission Complete flag
00866   *     @arg USART_FLAG_RXNE: Receive data register not empty flag
00867   *     @arg USART_FLAG_IDLE: Idle Line detection flag
00868   *     @arg USART_FLAG_ORE:  OverRun Error flag
00869   *     @arg USART_FLAG_NE:   Noise Error flag
00870   *     @arg USART_FLAG_FE:   Framing Error flag
00871   *     @arg USART_FLAG_PE:   Parity Error flag
00872   * @retval The new state of USART_FLAG (SET or RESET).
00873   */
00874 FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG)
00875 {
00876   FlagStatus bitstatus = RESET;
00877   /* Check the parameters */
00878   assert_param(IS_USART_ALL_PERIPH(USARTx));
00879   assert_param(IS_USART_FLAG(USART_FLAG));
00880   /* The CTS flag is not available for UART4 and UART5 */
00881   if (USART_FLAG == USART_FLAG_CTS)
00882   {
00883     assert_param(IS_USART_123_PERIPH(USARTx));
00884   }
00885
00886   if ((USARTx->SR & USART_FLAG) != (uint16_t)RESET)
00887   {
00888     bitstatus = SET;
00889   }
00890   else
00891   {
00892     bitstatus = RESET;
00893   }
00894   return bitstatus;
00895 }
00896
00897 /**
00898   * @brief  Clears the USARTx's pending flags.
00899   * @param  USARTx: Select the USART or the UART peripheral.
00900   *   This parameter can be one of the following values:
00901   *   USART1, USART2, USART3, UART4 or UART5.
00902   * @param  USART_FLAG: specifies the flag to clear.
00903   *   This parameter can be any combination of the following values:
00904   *     @arg USART_FLAG_CTS:  CTS Change flag (not available for UART4 and UART5).
00905   *     @arg USART_FLAG_LBD:  LIN Break detection flag.
00906   *     @arg USART_FLAG_TC:   Transmission Complete flag.
00907   *     @arg USART_FLAG_RXNE: Receive data register not empty flag.
00908   *
00909   * @note
00910   *   - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
00911   *     error) and IDLE (Idle line detected) flags are cleared by software
00912   *     sequence: a read operation to USART_SR register (USART_GetFlagStatus())
00913   *     followed by a read operation to USART_DR register (USART_ReceiveData()).
00914   *   - RXNE flag can be also cleared by a read to the USART_DR register
00915   *     (USART_ReceiveData()).
00916   *   - TC flag can be also cleared by software sequence: a read operation to
00917   *     USART_SR register (USART_GetFlagStatus()) followed by a write operation
00918   *     to USART_DR register (USART_SendData()).
00919   *   - TXE flag is cleared only by a write to the USART_DR register
00920   *     (USART_SendData()).
00921   * @retval None
00922   */
00923 void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG)
00924 {
00925   /* Check the parameters */
00926   assert_param(IS_USART_ALL_PERIPH(USARTx));
00927   assert_param(IS_USART_CLEAR_FLAG(USART_FLAG));
00928   /* The CTS flag is not available for UART4 and UART5 */
00929   if ((USART_FLAG & USART_FLAG_CTS) == USART_FLAG_CTS)
00930   {
00931     assert_param(IS_USART_123_PERIPH(USARTx));
00932   }
00933
00934   USARTx->SR = (uint16_t)~USART_FLAG;
00935 }
00936
00937 /**
00938   * @brief  Checks whether the specified USART interrupt has occurred or not.
00939   * @param  USARTx: Select the USART or the UART peripheral.
00940   *   This parameter can be one of the following values:
00941   *   USART1, USART2, USART3, UART4 or UART5.
00942   * @param  USART_IT: specifies the USART interrupt source to check.
00943   *   This parameter can be one of the following values:
00944   *     @arg USART_IT_CTS:  CTS change interrupt (not available for UART4 and UART5)
00945   *     @arg USART_IT_LBD:  LIN Break detection interrupt
00946   *     @arg USART_IT_TXE:  Tansmit Data Register empty interrupt
00947   *     @arg USART_IT_TC:   Transmission complete interrupt
00948   *     @arg USART_IT_RXNE: Receive Data register not empty interrupt
00949   *     @arg USART_IT_IDLE: Idle line detection interrupt
00950   *     @arg USART_IT_ORE:  OverRun Error interrupt
00951   *     @arg USART_IT_NE:   Noise Error interrupt
00952   *     @arg USART_IT_FE:   Framing Error interrupt
00953   *     @arg USART_IT_PE:   Parity Error interrupt
00954   * @retval The new state of USART_IT (SET or RESET).
00955   */
00956 ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT)
00957 {
00958   uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00;
00959   ITStatus bitstatus = RESET;
00960   /* Check the parameters */
00961   assert_param(IS_USART_ALL_PERIPH(USARTx));
00962   assert_param(IS_USART_GET_IT(USART_IT));
00963   /* The CTS interrupt is not available for UART4 and UART5 */
00964   if (USART_IT == USART_IT_CTS)
00965   {
00966     assert_param(IS_USART_123_PERIPH(USARTx));
00967   }
00968
00969   /* Get the USART register index */
00970   usartreg = (((uint8_t)USART_IT) >> 0x05);
00971   /* Get the interrupt position */
00972   itmask = USART_IT & IT_Mask;
00973   itmask = (uint32_t)0x01 << itmask;
00974
00975   if (usartreg == 0x01) /* The IT  is in CR1 register */
00976   {
00977     itmask &= USARTx->CR1;
00978   }
00979   else if (usartreg == 0x02) /* The IT  is in CR2 register */
00980   {
00981     itmask &= USARTx->CR2;
00982   }
00983   else /* The IT  is in CR3 register */
00984   {
00985     itmask &= USARTx->CR3;
00986   }
00987
00988   bitpos = USART_IT >> 0x08;
00989   bitpos = (uint32_t)0x01 << bitpos;
00990   bitpos &= USARTx->SR;
00991   if ((itmask != (uint16_t)RESET)&&(bitpos != (uint16_t)RESET))
00992   {
00993     bitstatus = SET;
00994   }
00995   else
00996   {
00997     bitstatus = RESET;
00998   }
00999
01000   return bitstatus;
01001 }
01002
01003 /**
01004   * @brief  Clears the USARTx's interrupt pending bits.
01005   * @param  USARTx: Select the USART or the UART peripheral.
01006   *   This parameter can be one of the following values:
01007   *   USART1, USART2, USART3, UART4 or UART5.
01008   * @param  USART_IT: specifies the interrupt pending bit to clear.
01009   *   This parameter can be one of the following values:
01010   *     @arg USART_IT_CTS:  CTS change interrupt (not available for UART4 and UART5)
01011   *     @arg USART_IT_LBD:  LIN Break detection interrupt
01012   *     @arg USART_IT_TC:   Transmission complete interrupt.
01013   *     @arg USART_IT_RXNE: Receive Data register not empty interrupt.
01014   *
01015   * @note
01016   *   - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
01017   *     error) and IDLE (Idle line detected) pending bits are cleared by
01018   *     software sequence: a read operation to USART_SR register
01019   *     (USART_GetITStatus()) followed by a read operation to USART_DR register
01020   *     (USART_ReceiveData()).
01021   *   - RXNE pending bit can be also cleared by a read to the USART_DR register
01022   *     (USART_ReceiveData()).
01023   *   - TC pending bit can be also cleared by software sequence: a read
01024   *     operation to USART_SR register (USART_GetITStatus()) followed by a write
01025   *     operation to USART_DR register (USART_SendData()).
01026   *   - TXE pending bit is cleared only by a write to the USART_DR register
01027   *     (USART_SendData()).
01028   * @retval None
01029   */
01030 void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT)
01031 {
01032   uint16_t bitpos = 0x00, itmask = 0x00;
01033   /* Check the parameters */
01034   assert_param(IS_USART_ALL_PERIPH(USARTx));
01035   assert_param(IS_USART_CLEAR_IT(USART_IT));
01036   /* The CTS interrupt is not available for UART4 and UART5 */
01037   if (USART_IT == USART_IT_CTS)
01038   {
01039     assert_param(IS_USART_123_PERIPH(USARTx));
01040   }
01041
01042   bitpos = USART_IT >> 0x08;
01043   itmask = ((uint16_t)0x01 << (uint16_t)bitpos);
01044   USARTx->SR = (uint16_t)~itmask;
01045 }
01046 /**
01047   * @}
01048   */
01049
01050 /**
01051   * @}
01052   */
01053
01054 /**
01055   * @}
01056   */
01057
01058 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_usart.h Source File

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stm32f10x_usart.h

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f10x_usart.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    11-March-2011
00007   * @brief   This file contains all the functions prototypes for the USART
00008   *          firmware library.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00013   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00014   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00015   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00016   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00017   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00018   *
00019   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00020   ******************************************************************************
00021   */
00022
00023 /* Define to prevent recursive inclusion -------------------------------------*/
00024 #ifndef __STM32F10x_USART_H
00025 #define __STM32F10x_USART_H
00026
00027 #ifdef __cplusplus
00028  extern "C" {
00029 #endif
00030
00031 /* Includes ------------------------------------------------------------------*/
00032 #include "stm32f10x.h"
00033
00034 /** @addtogroup STM32F10x_StdPeriph_Driver
00035   * @{
00036   */
00037
00038 /** @addtogroup USART
00039   * @{
00040   */
00041
00042 /** @defgroup USART_Exported_Types
00043   * @{
00044   */
00045
00046 /**
00047   * @brief  USART Init Structure definition
00048   */
00049
00050 typedef struct
00051 {
00052   uint32_t USART_BaudRate;            /*!< This member configures the USART communication baud rate.
00053                                            The baud rate is computed using the following formula:
00054                                             - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate)))
00055                                             - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */
00056
00057   uint16_t USART_WordLength;          /*!< Specifies the number of data bits transmitted or received in a frame.
00058                                            This parameter can be a value of @ref USART_Word_Length */
00059
00060   uint16_t USART_StopBits;            /*!< Specifies the number of stop bits transmitted.
00061                                            This parameter can be a value of @ref USART_Stop_Bits */
00062
00063   uint16_t USART_Parity;              /*!< Specifies the parity mode.
00064                                            This parameter can be a value of @ref USART_Parity
00065                                            @note When parity is enabled, the computed parity is inserted
00066                                                  at the MSB position of the transmitted data (9th bit when
00067                                                  the word length is set to 9 data bits; 8th bit when the
00068                                                  word length is set to 8 data bits). */
00069
00070   uint16_t USART_Mode;                /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
00071                                            This parameter can be a value of @ref USART_Mode */
00072
00073   uint16_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled
00074                                            or disabled.
00075                                            This parameter can be a value of @ref USART_Hardware_Flow_Control */
00076 } USART_InitTypeDef;
00077
00078 /**
00079   * @brief  USART Clock Init Structure definition
00080   */
00081
00082 typedef struct
00083 {
00084
00085   uint16_t USART_Clock;   /*!< Specifies whether the USART clock is enabled or disabled.
00086                                This parameter can be a value of @ref USART_Clock */
00087
00088   uint16_t USART_CPOL;    /*!< Specifies the steady state value of the serial clock.
00089                                This parameter can be a value of @ref USART_Clock_Polarity */
00090
00091   uint16_t USART_CPHA;    /*!< Specifies the clock transition on which the bit capture is made.
00092                                This parameter can be a value of @ref USART_Clock_Phase */
00093
00094   uint16_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
00095                                data bit (MSB) has to be output on the SCLK pin in synchronous mode.
00096                                This parameter can be a value of @ref USART_Last_Bit */
00097 } USART_ClockInitTypeDef;
00098
00099 /**
00100   * @}
00101   */
00102
00103 /** @defgroup USART_Exported_Constants
00104   * @{
00105   */
00106
00107 #define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \
00108                                      ((PERIPH) == USART2) || \
00109                                      ((PERIPH) == USART3) || \
00110                                      ((PERIPH) == UART4) || \
00111                                      ((PERIPH) == UART5))
00112
00113 #define IS_USART_123_PERIPH(PERIPH) (((PERIPH) == USART1) || \
00114                                      ((PERIPH) == USART2) || \
00115                                      ((PERIPH) == USART3))
00116
00117 #define IS_USART_1234_PERIPH(PERIPH) (((PERIPH) == USART1) || \
00118                                       ((PERIPH) == USART2) || \
00119                                       ((PERIPH) == USART3) || \
00120                                       ((PERIPH) == UART4))
00121 /** @defgroup USART_Word_Length
00122   * @{
00123   */
00124
00125 #define USART_WordLength_8b                  ((uint16_t)0x0000)
00126 #define USART_WordLength_9b                  ((uint16_t)0x1000)
00127
00128 #define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \
00129                                       ((LENGTH) == USART_WordLength_9b))
00130 /**
00131   * @}
00132   */
00133
00134 /** @defgroup USART_Stop_Bits
00135   * @{
00136   */
00137
00138 #define USART_StopBits_1                     ((uint16_t)0x0000)
00139 #define USART_StopBits_0_5                   ((uint16_t)0x1000)
00140 #define USART_StopBits_2                     ((uint16_t)0x2000)
00141 #define USART_StopBits_1_5                   ((uint16_t)0x3000)
00142 #define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \
00143                                      ((STOPBITS) == USART_StopBits_0_5) || \
00144                                      ((STOPBITS) == USART_StopBits_2) || \
00145                                      ((STOPBITS) == USART_StopBits_1_5))
00146 /**
00147   * @}
00148   */
00149
00150 /** @defgroup USART_Parity
00151   * @{
00152   */
00153
00154 #define USART_Parity_No                      ((uint16_t)0x0000)
00155 #define USART_Parity_Even                    ((uint16_t)0x0400)
00156 #define USART_Parity_Odd                     ((uint16_t)0x0600)
00157 #define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \
00158                                  ((PARITY) == USART_Parity_Even) || \
00159                                  ((PARITY) == USART_Parity_Odd))
00160 /**
00161   * @}
00162   */
00163
00164 /** @defgroup USART_Mode
00165   * @{
00166   */
00167
00168 #define USART_Mode_Rx                        ((uint16_t)0x0004)
00169 #define USART_Mode_Tx                        ((uint16_t)0x0008)
00170 #define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00))
00171 /**
00172   * @}
00173   */
00174
00175 /** @defgroup USART_Hardware_Flow_Control
00176   * @{
00177   */
00178 #define USART_HardwareFlowControl_None       ((uint16_t)0x0000)
00179 #define USART_HardwareFlowControl_RTS        ((uint16_t)0x0100)
00180 #define USART_HardwareFlowControl_CTS        ((uint16_t)0x0200)
00181 #define USART_HardwareFlowControl_RTS_CTS    ((uint16_t)0x0300)
00182 #define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\
00183                               (((CONTROL) == USART_HardwareFlowControl_None) || \
00184                                ((CONTROL) == USART_HardwareFlowControl_RTS) || \
00185                                ((CONTROL) == USART_HardwareFlowControl_CTS) || \
00186                                ((CONTROL) == USART_HardwareFlowControl_RTS_CTS))
00187 /**
00188   * @}
00189   */
00190
00191 /** @defgroup USART_Clock
00192   * @{
00193   */
00194 #define USART_Clock_Disable                  ((uint16_t)0x0000)
00195 #define USART_Clock_Enable                   ((uint16_t)0x0800)
00196 #define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \
00197                                ((CLOCK) == USART_Clock_Enable))
00198 /**
00199   * @}
00200   */
00201
00202 /** @defgroup USART_Clock_Polarity
00203   * @{
00204   */
00205
00206 #define USART_CPOL_Low                       ((uint16_t)0x0000)
00207 #define USART_CPOL_High                      ((uint16_t)0x0400)
00208 #define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High))
00209
00210 /**
00211   * @}
00212   */
00213
00214 /** @defgroup USART_Clock_Phase
00215   * @{
00216   */
00217
00218 #define USART_CPHA_1Edge                     ((uint16_t)0x0000)
00219 #define USART_CPHA_2Edge                     ((uint16_t)0x0200)
00220 #define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge))
00221
00222 /**
00223   * @}
00224   */
00225
00226 /** @defgroup USART_Last_Bit
00227   * @{
00228   */
00229
00230 #define USART_LastBit_Disable                ((uint16_t)0x0000)
00231 #define USART_LastBit_Enable                 ((uint16_t)0x0100)
00232 #define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \
00233                                    ((LASTBIT) == USART_LastBit_Enable))
00234 /**
00235   * @}
00236   */
00237
00238 /** @defgroup USART_Interrupt_definition
00239   * @{
00240   */
00241
00242 #define USART_IT_PE                          ((uint16_t)0x0028)
00243 #define USART_IT_TXE                         ((uint16_t)0x0727)
00244 #define USART_IT_TC                          ((uint16_t)0x0626)
00245 #define USART_IT_RXNE                        ((uint16_t)0x0525)
00246 #define USART_IT_IDLE                        ((uint16_t)0x0424)
00247 #define USART_IT_LBD                         ((uint16_t)0x0846)
00248 #define USART_IT_CTS                         ((uint16_t)0x096A)
00249 #define USART_IT_ERR                         ((uint16_t)0x0060)
00250 #define USART_IT_ORE                         ((uint16_t)0x0360)
00251 #define USART_IT_NE                          ((uint16_t)0x0260)
00252 #define USART_IT_FE                          ((uint16_t)0x0160)
00253 #define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
00254                                ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
00255                                ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
00256                                ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR))
00257 #define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
00258                             ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
00259                             ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
00260                             ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \
00261                             ((IT) == USART_IT_NE) || ((IT) == USART_IT_FE))
00262 #define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
00263                                ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS))
00264 /**
00265   * @}
00266   */
00267
00268 /** @defgroup USART_DMA_Requests
00269   * @{
00270   */
00271
00272 #define USART_DMAReq_Tx                      ((uint16_t)0x0080)
00273 #define USART_DMAReq_Rx                      ((uint16_t)0x0040)
00274 #define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00))
00275
00276 /**
00277   * @}
00278   */
00279
00280 /** @defgroup USART_WakeUp_methods
00281   * @{
00282   */
00283
00284 #define USART_WakeUp_IdleLine                ((uint16_t)0x0000)
00285 #define USART_WakeUp_AddressMark             ((uint16_t)0x0800)
00286 #define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \
00287                                  ((WAKEUP) == USART_WakeUp_AddressMark))
00288 /**
00289   * @}
00290   */
00291
00292 /** @defgroup USART_LIN_Break_Detection_Length
00293   * @{
00294   */
00295
00296 #define USART_LINBreakDetectLength_10b      ((uint16_t)0x0000)
00297 #define USART_LINBreakDetectLength_11b      ((uint16_t)0x0020)
00298 #define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \
00299                                (((LENGTH) == USART_LINBreakDetectLength_10b) || \
00300                                 ((LENGTH) == USART_LINBreakDetectLength_11b))
00301 /**
00302   * @}
00303   */
00304
00305 /** @defgroup USART_IrDA_Low_Power
00306   * @{
00307   */
00308
00309 #define USART_IrDAMode_LowPower              ((uint16_t)0x0004)
00310 #define USART_IrDAMode_Normal                ((uint16_t)0x0000)
00311 #define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \
00312                                   ((MODE) == USART_IrDAMode_Normal))
00313 /**
00314   * @}
00315   */
00316
00317 /** @defgroup USART_Flags
00318   * @{
00319   */
00320
00321 #define USART_FLAG_CTS                       ((uint16_t)0x0200)
00322 #define USART_FLAG_LBD                       ((uint16_t)0x0100)
00323 #define USART_FLAG_TXE                       ((uint16_t)0x0080)
00324 #define USART_FLAG_TC                        ((uint16_t)0x0040)
00325 #define USART_FLAG_RXNE                      ((uint16_t)0x0020)
00326 #define USART_FLAG_IDLE                      ((uint16_t)0x0010)
00327 #define USART_FLAG_ORE                       ((uint16_t)0x0008)
00328 #define USART_FLAG_NE                        ((uint16_t)0x0004)
00329 #define USART_FLAG_FE                        ((uint16_t)0x0002)
00330 #define USART_FLAG_PE                        ((uint16_t)0x0001)
00331 #define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \
00332                              ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \
00333                              ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \
00334                              ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \
00335                              ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE))
00336
00337 #define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00))
00338 #define IS_USART_PERIPH_FLAG(PERIPH, USART_FLAG) ((((*(uint32_t*)&(PERIPH)) != UART4_BASE) &&\
00339                                                   ((*(uint32_t*)&(PERIPH)) != UART5_BASE)) \
00340                                                   || ((USART_FLAG) != USART_FLAG_CTS))
00341 #define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x0044AA21))
00342 #define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF)
00343 #define IS_USART_DATA(DATA) ((DATA) <= 0x1FF)
00344
00345 /**
00346   * @}
00347   */
00348
00349 /**
00350   * @}
00351   */
00352
00353 /** @defgroup USART_Exported_Macros
00354   * @{
00355   */
00356
00357 /**
00358   * @}
00359   */
00360
00361 /** @defgroup USART_Exported_Functions
00362   * @{
00363   */
00364
00365 void USART_DeInit(USART_TypeDef* USARTx);
00366 void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct);
00367 void USART_StructInit(USART_InitTypeDef* USART_InitStruct);
00368 void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct);
00369 void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct);
00370 void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
00371 void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState);
00372 void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState);
00373 void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address);
00374 void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp);
00375 void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState);
00376 void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength);
00377 void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState);
00378 void USART_SendData(USART_TypeDef* USARTx, uint16_t Data);
00379 uint16_t USART_ReceiveData(USART_TypeDef* USARTx);
00380 void USART_SendBreak(USART_TypeDef* USARTx);
00381 void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime);
00382 void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler);
00383 void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState);
00384 void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState);
00385 void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState);
00386 void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
00387 void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState);
00388 void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode);
00389 void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState);
00390 FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG);
00391 void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG);
00392 ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT);
00393 void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT);
00394
00395 #ifdef __cplusplus
00396 }
00397 #endif
00398
00399 #endif /* __STM32F10x_USART_H */
00400 /**
00401   * @}
00402   */
00403
00404 /**
00405   * @}
00406   */
00407
00408 /**
00409   * @}
00410   */
00411
00412 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_wwdg.c Source File

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  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Libraries
  • STM32F10x_StdPeriph_Driver
  • src

stm32f10x_wwdg.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32f10x_wwdg.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    11-March-2011
00007   * @brief   This file provides all the WWDG firmware functions.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x_wwdg.h"
00024 #include "stm32f10x_rcc.h"
00025
00026 /** @addtogroup STM32F10x_StdPeriph_Driver
00027   * @{
00028   */
00029
00030 /** @defgroup WWDG
00031   * @brief WWDG driver modules
00032   * @{
00033   */
00034
00035 /** @defgroup WWDG_Private_TypesDefinitions
00036   * @{
00037   */
00038
00039 /**
00040   * @}
00041   */
00042
00043 /** @defgroup WWDG_Private_Defines
00044   * @{
00045   */
00046
00047 /* ----------- WWDG registers bit address in the alias region ----------- */
00048 #define WWDG_OFFSET       (WWDG_BASE - PERIPH_BASE)
00049
00050 /* Alias word address of EWI bit */
00051 #define CFR_OFFSET        (WWDG_OFFSET + 0x04)
00052 #define EWI_BitNumber     0x09
00053 #define CFR_EWI_BB        (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4))
00054
00055 /* --------------------- WWDG registers bit mask ------------------------ */
00056
00057 /* CR register bit mask */
00058 #define CR_WDGA_Set       ((uint32_t)0x00000080)
00059
00060 /* CFR register bit mask */
00061 #define CFR_WDGTB_Mask    ((uint32_t)0xFFFFFE7F)
00062 #define CFR_W_Mask        ((uint32_t)0xFFFFFF80)
00063 #define BIT_Mask          ((uint8_t)0x7F)
00064
00065 /**
00066   * @}
00067   */
00068
00069 /** @defgroup WWDG_Private_Macros
00070   * @{
00071   */
00072
00073 /**
00074   * @}
00075   */
00076
00077 /** @defgroup WWDG_Private_Variables
00078   * @{
00079   */
00080
00081 /**
00082   * @}
00083   */
00084
00085 /** @defgroup WWDG_Private_FunctionPrototypes
00086   * @{
00087   */
00088
00089 /**
00090   * @}
00091   */
00092
00093 /** @defgroup WWDG_Private_Functions
00094   * @{
00095   */
00096
00097 /**
00098   * @brief  Deinitializes the WWDG peripheral registers to their default reset values.
00099   * @param  None
00100   * @retval None
00101   */
00102 void WWDG_DeInit(void)
00103 {
00104   RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE);
00105   RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE);
00106 }
00107
00108 /**
00109   * @brief  Sets the WWDG Prescaler.
00110   * @param  WWDG_Prescaler: specifies the WWDG Prescaler.
00111   *   This parameter can be one of the following values:
00112   *     @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1
00113   *     @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2
00114   *     @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4
00115   *     @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8
00116   * @retval None
00117   */
00118 void WWDG_SetPrescaler(uint32_t WWDG_Prescaler)
00119 {
00120   uint32_t tmpreg = 0;
00121   /* Check the parameters */
00122   assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler));
00123   /* Clear WDGTB[1:0] bits */
00124   tmpreg = WWDG->CFR & CFR_WDGTB_Mask;
00125   /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */
00126   tmpreg |= WWDG_Prescaler;
00127   /* Store the new value */
00128   WWDG->CFR = tmpreg;
00129 }
00130
00131 /**
00132   * @brief  Sets the WWDG window value.
00133   * @param  WindowValue: specifies the window value to be compared to the downcounter.
00134   *   This parameter value must be lower than 0x80.
00135   * @retval None
00136   */
00137 void WWDG_SetWindowValue(uint8_t WindowValue)
00138 {
00139   __IO uint32_t tmpreg = 0;
00140
00141   /* Check the parameters */
00142   assert_param(IS_WWDG_WINDOW_VALUE(WindowValue));
00143   /* Clear W[6:0] bits */
00144
00145   tmpreg = WWDG->CFR & CFR_W_Mask;
00146
00147   /* Set W[6:0] bits according to WindowValue value */
00148   tmpreg |= WindowValue & (uint32_t) BIT_Mask;
00149
00150   /* Store the new value */
00151   WWDG->CFR = tmpreg;
00152 }
00153
00154 /**
00155   * @brief  Enables the WWDG Early Wakeup interrupt(EWI).
00156   * @param  None
00157   * @retval None
00158   */
00159 void WWDG_EnableIT(void)
00160 {
00161   *(__IO uint32_t *) CFR_EWI_BB = (uint32_t)ENABLE;
00162 }
00163
00164 /**
00165   * @brief  Sets the WWDG counter value.
00166   * @param  Counter: specifies the watchdog counter value.
00167   *   This parameter must be a number between 0x40 and 0x7F.
00168   * @retval None
00169   */
00170 void WWDG_SetCounter(uint8_t Counter)
00171 {
00172   /* Check the parameters */
00173   assert_param(IS_WWDG_COUNTER(Counter));
00174   /* Write to T[6:0] bits to configure the counter value, no need to do
00175      a read-modify-write; writing a 0 to WDGA bit does nothing */
00176   WWDG->CR = Counter & BIT_Mask;
00177 }
00178
00179 /**
00180   * @brief  Enables WWDG and load the counter value.
00181   * @param  Counter: specifies the watchdog counter value.
00182   *   This parameter must be a number between 0x40 and 0x7F.
00183   * @retval None
00184   */
00185 void WWDG_Enable(uint8_t Counter)
00186 {
00187   /* Check the parameters */
00188   assert_param(IS_WWDG_COUNTER(Counter));
00189   WWDG->CR = CR_WDGA_Set | Counter;
00190 }
00191
00192 /**
00193   * @brief  Checks whether the Early Wakeup interrupt flag is set or not.
00194   * @param  None
00195   * @retval The new state of the Early Wakeup interrupt flag (SET or RESET)
00196   */
00197 FlagStatus WWDG_GetFlagStatus(void)
00198 {
00199   return (FlagStatus)(WWDG->SR);
00200 }
00201
00202 /**
00203   * @brief  Clears Early Wakeup interrupt flag.
00204   * @param  None
00205   * @retval None
00206   */
00207 void WWDG_ClearFlag(void)
00208 {
00209   WWDG->SR = (uint32_t)RESET;
00210 }
00211
00212 /**
00213   * @}
00214   */
00215
00216 /**
00217   * @}
00218   */
00219
00220 /**
00221   * @}
00222   */
00223
00224 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32f10x_wwdg.h Source File

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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Libraries
  • STM32F10x_StdPeriph_Driver
  • inc

stm32f10x_wwdg.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32f10x_wwdg.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    11-March-2011
00007   * @brief   This file contains all the functions prototypes for the WWDG firmware
00008   *          library.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00013   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00014   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00015   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00016   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00017   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00018   *
00019   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00020   ******************************************************************************
00021   */
00022
00023 /* Define to prevent recursive inclusion -------------------------------------*/
00024 #ifndef __STM32F10x_WWDG_H
00025 #define __STM32F10x_WWDG_H
00026
00027 #ifdef __cplusplus
00028  extern "C" {
00029 #endif
00030
00031 /* Includes ------------------------------------------------------------------*/
00032 #include "stm32f10x.h"
00033
00034 /** @addtogroup STM32F10x_StdPeriph_Driver
00035   * @{
00036   */
00037
00038 /** @addtogroup WWDG
00039   * @{
00040   */
00041
00042 /** @defgroup WWDG_Exported_Types
00043   * @{
00044   */
00045
00046 /**
00047   * @}
00048   */
00049
00050 /** @defgroup WWDG_Exported_Constants
00051   * @{
00052   */
00053
00054 /** @defgroup WWDG_Prescaler
00055   * @{
00056   */
00057
00058 #define WWDG_Prescaler_1    ((uint32_t)0x00000000)
00059 #define WWDG_Prescaler_2    ((uint32_t)0x00000080)
00060 #define WWDG_Prescaler_4    ((uint32_t)0x00000100)
00061 #define WWDG_Prescaler_8    ((uint32_t)0x00000180)
00062 #define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \
00063                                       ((PRESCALER) == WWDG_Prescaler_2) || \
00064                                       ((PRESCALER) == WWDG_Prescaler_4) || \
00065                                       ((PRESCALER) == WWDG_Prescaler_8))
00066 #define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F)
00067 #define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F))
00068
00069 /**
00070   * @}
00071   */
00072
00073 /**
00074   * @}
00075   */
00076
00077 /** @defgroup WWDG_Exported_Macros
00078   * @{
00079   */
00080 /**
00081   * @}
00082   */
00083
00084 /** @defgroup WWDG_Exported_Functions
00085   * @{
00086   */
00087
00088 void WWDG_DeInit(void);
00089 void WWDG_SetPrescaler(uint32_t WWDG_Prescaler);
00090 void WWDG_SetWindowValue(uint8_t WindowValue);
00091 void WWDG_EnableIT(void);
00092 void WWDG_SetCounter(uint8_t Counter);
00093 void WWDG_Enable(uint8_t Counter);
00094 FlagStatus WWDG_GetFlagStatus(void);
00095 void WWDG_ClearFlag(void);
00096
00097 #ifdef __cplusplus
00098 }
00099 #endif
00100
00101 #endif /* __STM32F10x_WWDG_H */
00102
00103 /**
00104   * @}
00105   */
00106
00107 /**
00108   * @}
00109   */
00110
00111 /**
00112   * @}
00113   */
00114
00115 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32l152_eval.c Source File

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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • STM32L152_EVAL

stm32l152_eval.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32l152_eval.c
00004   * @author  MCD Application Team
00005   * @version V4.5.0
00006   * @date    07-March-2011
00007   * @brief   This file provides:
00008   *            - set of firmware functions to manage Leds, push-button and COM ports
00009   *            - low level initialization functions for SD card (on SPI) and
00010   *              temperature sensor (LM75) available on STM32L152-EVAL
00011   *              evaluation board RevB from STMicroelectronics.
00012   ******************************************************************************
00013   * @attention
00014   *
00015   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00016   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00017   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00018   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00019   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00020   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00021   *
00022   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00023   ******************************************************************************
00024   */
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32l152_eval.h"
00028 #include "stm32l1xx_spi.h"
00029 #include "stm32l1xx_i2c.h"
00030
00031 /** @addtogroup Utilities
00032   * @{
00033   */
00034
00035 /** @addtogroup STM32_EVAL
00036   * @{
00037   */
00038
00039 /** @addtogroup STM32L152_EVAL
00040   * @{
00041   */
00042
00043 /** @defgroup STM32L152_EVAL_LOW_LEVEL
00044   * @brief This file provides firmware functions to manage Leds, push-buttons,
00045   *        COM ports, SD card on SPI and temperature sensor (LM75) available on
00046   *        STM32L152-EVAL evaluation board from STMicroelectronics.
00047   * @{
00048   */
00049
00050 /** @defgroup STM32L152_EVAL_LOW_LEVEL_Private_TypesDefinitions
00051   * @{
00052   */
00053 /**
00054   * @}
00055   */
00056
00057
00058 /** @defgroup STM32L152_EVAL_LOW_LEVEL_Private_Defines
00059   * @{
00060   */
00061 /**
00062   * @}
00063   */
00064
00065
00066 /** @defgroup STM32L152_EVAL_LOW_LEVEL_Private_Macros
00067   * @{
00068   */
00069 /**
00070   * @}
00071   */
00072
00073
00074 /** @defgroup STM32L152_EVAL_LOW_LEVEL_Private_Variables
00075   * @{
00076   */
00077 GPIO_TypeDef* GPIO_PORT[LEDn] = {LED1_GPIO_PORT, LED2_GPIO_PORT, LED3_GPIO_PORT,
00078                                  LED4_GPIO_PORT};
00079 const uint16_t GPIO_PIN[LEDn] = {LED1_PIN, LED2_PIN, LED3_PIN,
00080                                  LED4_PIN};
00081 const uint32_t GPIO_CLK[LEDn] = {LED1_GPIO_CLK, LED2_GPIO_CLK, LED3_GPIO_CLK,
00082                                  LED4_GPIO_CLK};
00083
00084 GPIO_TypeDef* BUTTON_PORT[BUTTONn] = {KEY_BUTTON_GPIO_PORT, RIGHT_BUTTON_GPIO_PORT,
00085                                       LEFT_BUTTON_GPIO_PORT, UP_BUTTON_GPIO_PORT,
00086                                       DOWN_BUTTON_GPIO_PORT, SEL_BUTTON_GPIO_PORT};
00087
00088 const uint16_t BUTTON_PIN[BUTTONn] = {KEY_BUTTON_PIN, RIGHT_BUTTON_PIN,
00089                                       LEFT_BUTTON_PIN, UP_BUTTON_PIN,
00090                                       DOWN_BUTTON_PIN, SEL_BUTTON_PIN};
00091
00092 const uint32_t BUTTON_CLK[BUTTONn] = {KEY_BUTTON_GPIO_CLK, RIGHT_BUTTON_GPIO_CLK,
00093                                       LEFT_BUTTON_GPIO_CLK, UP_BUTTON_GPIO_CLK,
00094                                       DOWN_BUTTON_GPIO_CLK, SEL_BUTTON_GPIO_CLK};
00095
00096 const uint16_t BUTTON_EXTI_LINE[BUTTONn] = {KEY_BUTTON_EXTI_LINE,
00097                                             RIGHT_BUTTON_EXTI_LINE,
00098                                             LEFT_BUTTON_EXTI_LINE,
00099                                             UP_BUTTON_EXTI_LINE,
00100                                             DOWN_BUTTON_EXTI_LINE,
00101                                             SEL_BUTTON_EXTI_LINE};
00102
00103 const uint16_t BUTTON_PORT_SOURCE[BUTTONn] = {KEY_BUTTON_EXTI_PORT_SOURCE,
00104                                               RIGHT_BUTTON_EXTI_PORT_SOURCE,
00105                                               LEFT_BUTTON_EXTI_PORT_SOURCE,
00106                                               UP_BUTTON_EXTI_PORT_SOURCE,
00107                                               DOWN_BUTTON_EXTI_PORT_SOURCE,
00108                                               SEL_BUTTON_EXTI_PORT_SOURCE};
00109
00110 const uint16_t BUTTON_PIN_SOURCE[BUTTONn] = {KEY_BUTTON_EXTI_PIN_SOURCE,
00111                                              RIGHT_BUTTON_EXTI_PIN_SOURCE,
00112                                              LEFT_BUTTON_EXTI_PIN_SOURCE,
00113                                              UP_BUTTON_EXTI_PIN_SOURCE,
00114                                              DOWN_BUTTON_EXTI_PIN_SOURCE,
00115                                              SEL_BUTTON_EXTI_PIN_SOURCE};
00116
00117 const uint16_t BUTTON_IRQn[BUTTONn] = {KEY_BUTTON_EXTI_IRQn, RIGHT_BUTTON_EXTI_IRQn,
00118                                        LEFT_BUTTON_EXTI_IRQn, UP_BUTTON_EXTI_IRQn,
00119                                        DOWN_BUTTON_EXTI_IRQn, SEL_BUTTON_EXTI_IRQn};
00120
00121 USART_TypeDef* COM_USART[COMn] = {EVAL_COM1, EVAL_COM2};
00122
00123 GPIO_TypeDef* COM_TX_PORT[COMn] = {EVAL_COM1_TX_GPIO_PORT, EVAL_COM2_TX_GPIO_PORT};
00124
00125 GPIO_TypeDef* COM_RX_PORT[COMn] = {EVAL_COM1_RX_GPIO_PORT, EVAL_COM2_RX_GPIO_PORT};
00126
00127 const uint32_t COM_USART_CLK[COMn] = {EVAL_COM1_CLK, EVAL_COM2_CLK};
00128
00129 const uint32_t COM_TX_PORT_CLK[COMn] = {EVAL_COM1_TX_GPIO_CLK, EVAL_COM2_TX_GPIO_CLK};
00130
00131 const uint32_t COM_RX_PORT_CLK[COMn] = {EVAL_COM1_RX_GPIO_CLK, EVAL_COM2_RX_GPIO_CLK};
00132
00133 const uint16_t COM_TX_PIN[COMn] = {EVAL_COM1_TX_PIN, EVAL_COM2_TX_PIN};
00134
00135 const uint16_t COM_RX_PIN[COMn] = {EVAL_COM1_RX_PIN, EVAL_COM2_RX_PIN};
00136
00137 const uint16_t COM_TX_PIN_SOURCE[COMn] = {EVAL_COM1_TX_SOURCE, EVAL_COM2_TX_SOURCE};
00138
00139 const uint16_t COM_RX_PIN_SOURCE[COMn] = {EVAL_COM1_RX_SOURCE, EVAL_COM2_RX_SOURCE};
00140
00141 const uint16_t COM_TX_AF[COMn] = {EVAL_COM1_TX_AF, EVAL_COM2_TX_AF};
00142
00143 const uint16_t COM_RX_AF[COMn] = {EVAL_COM1_RX_AF, EVAL_COM2_RX_AF};
00144
00145 DMA_InitTypeDef   sEEDMA_InitStructure;
00146
00147 /**
00148   * @}
00149   */
00150
00151
00152 /** @defgroup STM32L152_EVAL_LOW_LEVEL_Private_FunctionPrototypes
00153   * @{
00154   */
00155
00156 /**
00157   * @}
00158   */
00159
00160 /** @defgroup STM32L152_EVAL_LOW_LEVEL_Private_Functions
00161   * @{
00162   */
00163
00164 /**
00165   * @brief  Configures LED GPIO.
00166   * @param  Led: Specifies the Led to be configured.
00167   *   This parameter can be one of following parameters:
00168   *     @arg LED1
00169   *     @arg LED2
00170   *     @arg LED3
00171   *     @arg LED4
00172   * @retval None
00173   */
00174 void STM_EVAL_LEDInit(Led_TypeDef Led)
00175 {
00176   GPIO_InitTypeDef  GPIO_InitStructure;
00177
00178   /* Enable the GPIO_LED Clock */
00179   RCC_AHBPeriphClockCmd(GPIO_CLK[Led], ENABLE);
00180
00181   /* Configure the GPIO_LED pin */
00182   GPIO_InitStructure.GPIO_Pin = GPIO_PIN[Led];
00183   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
00184   GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
00185   GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
00186   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_40MHz;
00187   GPIO_Init(GPIO_PORT[Led], &GPIO_InitStructure);
00188   GPIO_PORT[Led]->BSRRL = GPIO_PIN[Led];
00189 }
00190
00191 /**
00192   * @brief  Turns selected LED On.
00193   * @param  Led: Specifies the Led to be set on.
00194   *   This parameter can be one of following parameters:
00195   *     @arg LED1
00196   *     @arg LED2
00197   *     @arg LED3
00198   *     @arg LED4
00199   * @retval None
00200   */
00201 void STM_EVAL_LEDOn(Led_TypeDef Led)
00202 {
00203   GPIO_PORT[Led]->BSRRH = GPIO_PIN[Led];
00204 }
00205
00206 /**
00207   * @brief  Turns selected LED Off.
00208   * @param  Led: Specifies the Led to be set off.
00209   *   This parameter can be one of following parameters:
00210   *     @arg LED1
00211   *     @arg LED2
00212   *     @arg LED3
00213   *     @arg LED4
00214   * @retval None
00215   */
00216 void STM_EVAL_LEDOff(Led_TypeDef Led)
00217 {
00218   GPIO_PORT[Led]->BSRRL = GPIO_PIN[Led];
00219 }
00220
00221 /**
00222   * @brief  Toggles the selected LED.
00223   * @param  Led: Specifies the Led to be toggled.
00224   *   This parameter can be one of following parameters:
00225   *     @arg LED1
00226   *     @arg LED2
00227   *     @arg LED3
00228   *     @arg LED4
00229   * @retval None
00230   */
00231 void STM_EVAL_LEDToggle(Led_TypeDef Led)
00232 {
00233   GPIO_PORT[Led]->ODR ^= GPIO_PIN[Led];
00234 }
00235
00236 /**
00237   * @brief  Configures Button GPIO and EXTI Line.
00238   * @param  Button: Specifies the Button to be configured.
00239   *   This parameter can be one of following parameters:
00240   *     @arg BUTTON_KEY: Key Push Button
00241   *     @arg BUTTON_RIGHT: Joystick Right Push Button
00242   *     @arg BUTTON_LEFT: Joystick Left Push Button
00243   *     @arg BUTTON_UP: Joystick Up Push Button
00244   *     @arg BUTTON_DOWN: Joystick Down Push Button
00245   *     @arg BUTTON_SEL: Joystick Sel Push Button
00246   * @param  Button_Mode: Specifies Button mode.
00247   *   This parameter can be one of following parameters:
00248   *     @arg BUTTON_MODE_GPIO: Button will be used as simple IO
00249   *     @arg BUTTON_MODE_EXTI: Button will be connected to EXTI line with interrupt
00250   *                     generation capability
00251   * @retval None
00252   */
00253 void STM_EVAL_PBInit(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode)
00254 {
00255   GPIO_InitTypeDef GPIO_InitStructure;
00256   EXTI_InitTypeDef EXTI_InitStructure;
00257   NVIC_InitTypeDef NVIC_InitStructure;
00258
00259   /* There is no Wakeup and Tamper buttons on STM32L152-EVAL, the Button value should
00260      be greater than 1. */
00261   if(Button > 1)
00262   {
00263     Button = (Button_TypeDef) (Button - 2);
00264
00265     /* Enable the BUTTON Clock */
00266     RCC_AHBPeriphClockCmd(BUTTON_CLK[Button], ENABLE);
00267     RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
00268
00269     /* Configure Button pin as input */
00270     GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
00271     GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
00272     GPIO_InitStructure.GPIO_Pin = BUTTON_PIN[Button];
00273     GPIO_Init(BUTTON_PORT[Button], &GPIO_InitStructure);
00274
00275
00276     if (Button_Mode == BUTTON_MODE_EXTI)
00277     {
00278       /* Connect Button EXTI Line to Button GPIO Pin */
00279       SYSCFG_EXTILineConfig(BUTTON_PORT_SOURCE[Button], BUTTON_PIN_SOURCE[Button]);
00280
00281       /* Configure Button EXTI line */
00282       EXTI_InitStructure.EXTI_Line = BUTTON_EXTI_LINE[Button];
00283       EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
00284
00285       if(Button != BUTTON_KEY)
00286       {
00287         EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling;
00288       }
00289       else
00290       {
00291         EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;
00292       }
00293       EXTI_InitStructure.EXTI_LineCmd = ENABLE;
00294       EXTI_Init(&EXTI_InitStructure);
00295
00296       /* Enable and set Button EXTI Interrupt to the lowest priority */
00297       NVIC_InitStructure.NVIC_IRQChannel = BUTTON_IRQn[Button];
00298       NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x0F;
00299       NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x0F;
00300       NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
00301
00302       NVIC_Init(&NVIC_InitStructure);
00303     }
00304   }
00305 }
00306
00307 /**
00308   * @brief  Returns the selected Button state.
00309   * @param  Button: Specifies the Button to be checked.
00310   *   This parameter can be one of following parameters:
00311   *     @arg BUTTON_KEY: Key Push Button
00312   *     @arg BUTTON_RIGHT: Joystick Right Push Button
00313   *     @arg BUTTON_LEFT: Joystick Left Push Button
00314   *     @arg BUTTON_UP: Joystick Up Push Button
00315   *     @arg BUTTON_DOWN: Joystick Down Push Button
00316   *     @arg BUTTON_SEL: Joystick Sel Push Button
00317   * @retval - When Button > 1, the Button GPIO pin value is returned.
00318   *         - When Button = 0 or 1, error code (0xFF) is returned.
00319   */
00320 uint32_t STM_EVAL_PBGetState(Button_TypeDef Button)
00321 {
00322   /* There is no Wakeup and Tamper pins on STM32L152-EVAL, the Button value should
00323      be greater than 1. */
00324   if(Button > 1)
00325   {
00326     Button = (Button_TypeDef) (Button - 2);
00327     return GPIO_ReadInputDataBit(BUTTON_PORT[Button], BUTTON_PIN[Button]);
00328   }
00329   else
00330   {
00331     return 0xFF; /* Error Code */
00332   }
00333 }
00334
00335 /**
00336   * @brief  Configures COM port.
00337   * @param  COM: Specifies the COM port to be configured.
00338   *   This parameter can be one of following parameters:
00339   *     @arg COM1
00340   *     @arg COM2
00341   * @param  USART_InitStruct: pointer to a USART_InitTypeDef structure that
00342   *   contains the configuration information for the specified USART peripheral.
00343   * @retval None
00344   */
00345 void STM_EVAL_COMInit(COM_TypeDef COM, USART_InitTypeDef* USART_InitStruct)
00346 {
00347   GPIO_InitTypeDef GPIO_InitStructure;
00348
00349   /* Enable GPIO clock */
00350   RCC_AHBPeriphClockCmd(COM_TX_PORT_CLK[COM] | COM_RX_PORT_CLK[COM], ENABLE);
00351
00352   /* Enable UART clock */
00353   RCC_APB1PeriphClockCmd(COM_USART_CLK[COM], ENABLE);
00354
00355   /* Connect PXx to USARTx_Tx */
00356   GPIO_PinAFConfig(COM_TX_PORT[COM], COM_TX_PIN_SOURCE[COM], COM_TX_AF[COM]);
00357
00358   /* Connect PXx to USARTx_Rx */
00359   GPIO_PinAFConfig(COM_RX_PORT[COM], COM_RX_PIN_SOURCE[COM], COM_RX_AF[COM]);
00360
00361   /* Configure USART Tx as alternate function push-pull */
00362   GPIO_InitStructure.GPIO_Pin = COM_TX_PIN[COM];
00363   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
00364   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_40MHz;
00365   GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
00366   GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
00367   GPIO_Init(COM_TX_PORT[COM], &GPIO_InitStructure);
00368
00369   /* Configure USART Rx as alternate function push-pull */
00370   GPIO_InitStructure.GPIO_Pin = COM_RX_PIN[COM];
00371   GPIO_Init(COM_RX_PORT[COM], &GPIO_InitStructure);
00372
00373   /* USART configuration */
00374   USART_Init(COM_USART[COM], USART_InitStruct);
00375
00376   /* Enable USART */
00377   USART_Cmd(COM_USART[COM], ENABLE);
00378 }
00379
00380 /**
00381   * @brief  DeInitializes the SPI interface.
00382   * @param  None
00383   * @retval None
00384   */
00385 void SD_LowLevel_DeInit(void)
00386 {
00387   GPIO_InitTypeDef  GPIO_InitStructure;
00388
00389   SPI_Cmd(SD_SPI, DISABLE); /*!< SD_SPI disable */
00390   SPI_DeInit(SD_SPI);   /*!< DeInitializes the SD_SPI */
00391
00392   /*!< SD_SPI Periph clock disable */
00393   RCC_APB1PeriphClockCmd(SD_SPI_CLK, DISABLE);
00394
00395   /*!< Configure SD_SPI pins: SCK */
00396   GPIO_InitStructure.GPIO_Pin = SD_SPI_SCK_PIN;
00397   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
00398   GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
00399   GPIO_Init(SD_SPI_SCK_GPIO_PORT, &GPIO_InitStructure);
00400
00401   /*!< Configure SD_SPI pins: MISO */
00402   GPIO_InitStructure.GPIO_Pin = SD_SPI_MISO_PIN;
00403   GPIO_Init(SD_SPI_MISO_GPIO_PORT, &GPIO_InitStructure);
00404
00405   /*!< Configure SD_SPI pins: MOSI */
00406   GPIO_InitStructure.GPIO_Pin = SD_SPI_MOSI_PIN;
00407   GPIO_Init(SD_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure);
00408
00409   /*!< Configure SD_SPI_CS_PIN pin: SD Card CS pin */
00410   GPIO_InitStructure.GPIO_Pin = SD_CS_PIN;
00411   GPIO_Init(SD_CS_GPIO_PORT, &GPIO_InitStructure);
00412
00413   /*!< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin */
00414   GPIO_InitStructure.GPIO_Pin = SD_DETECT_PIN;
00415   GPIO_Init(SD_DETECT_GPIO_PORT, &GPIO_InitStructure);
00416 }
00417
00418 /**
00419   * @brief  Initializes the SD Card and put it into StandBy State (Ready for
00420   *         data transfer).
00421   * @param  None
00422   * @retval None
00423   */
00424 void SD_LowLevel_Init(void)
00425 {
00426   GPIO_InitTypeDef  GPIO_InitStructure;
00427   SPI_InitTypeDef   SPI_InitStructure;
00428
00429   /*!< SD_SPI_CS_GPIO, SD_SPI_MOSI_GPIO, SD_SPI_MISO_GPIO, SD_SPI_DETECT_GPIO
00430        and SD_SPI_SCK_GPIO Periph clock enable */
00431   RCC_AHBPeriphClockCmd(SD_CS_GPIO_CLK | SD_SPI_MOSI_GPIO_CLK | SD_SPI_MISO_GPIO_CLK |
00432                         SD_SPI_SCK_GPIO_CLK | SD_DETECT_GPIO_CLK, ENABLE);
00433
00434   /*!< SD_SPI Periph clock enable */
00435   RCC_APB1PeriphClockCmd(SD_SPI_CLK, ENABLE);
00436
00437   /*!< Configure SD_SPI pins: SCK */
00438   GPIO_InitStructure.GPIO_Pin = SD_SPI_SCK_PIN;
00439   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
00440   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_40MHz;
00441   GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
00442   GPIO_InitStructure.GPIO_PuPd  = GPIO_PuPd_UP;
00443   GPIO_Init(SD_SPI_SCK_GPIO_PORT, &GPIO_InitStructure);
00444
00445   /*!< Configure SD_SPI pins: MISO */
00446   GPIO_InitStructure.GPIO_Pin = SD_SPI_MISO_PIN;
00447   GPIO_Init(SD_SPI_MISO_GPIO_PORT, &GPIO_InitStructure);
00448
00449   /*!< Configure SD_SPI pins: MOSI */
00450   GPIO_InitStructure.GPIO_Pin = SD_SPI_MOSI_PIN;
00451   GPIO_Init(SD_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure);
00452
00453   /*!< Configure SD_SPI_CS_PIN pin: SD Card CS pin */
00454   GPIO_InitStructure.GPIO_Pin = SD_CS_PIN;
00455   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
00456   GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
00457   GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
00458   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_40MHz;
00459   GPIO_Init(SD_CS_GPIO_PORT, &GPIO_InitStructure);
00460
00461   /*!< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin */
00462   GPIO_InitStructure.GPIO_Pin = SD_DETECT_PIN;
00463   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
00464   GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
00465   GPIO_Init(SD_DETECT_GPIO_PORT, &GPIO_InitStructure);
00466
00467   /* Connect PXx to SD_SPI_SCK */
00468   GPIO_PinAFConfig(SD_SPI_SCK_GPIO_PORT, SD_SPI_SCK_SOURCE, SD_SPI_SCK_AF);
00469
00470   /* Connect PXx to SD_SPI_MISO */
00471   GPIO_PinAFConfig(SD_SPI_MISO_GPIO_PORT, SD_SPI_MISO_SOURCE, SD_SPI_MISO_AF);
00472
00473   /* Connect PXx to SD_SPI_MOSI */
00474   GPIO_PinAFConfig(SD_SPI_MOSI_GPIO_PORT, SD_SPI_MOSI_SOURCE, SD_SPI_MOSI_AF);
00475
00476   /*!< SD_SPI Config */
00477   SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
00478   SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
00479   SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
00480   SPI_InitStructure.SPI_CPOL = SPI_CPOL_High;
00481   SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge;
00482   SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
00483   SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
00484
00485   SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
00486   SPI_InitStructure.SPI_CRCPolynomial = 7;
00487   SPI_Init(SD_SPI, &SPI_InitStructure);
00488
00489   SPI_Cmd(SD_SPI, ENABLE); /*!< SD_SPI enable */
00490 }
00491
00492 /**
00493   * @brief  DeInitializes the LM75_I2C.
00494   * @param  None
00495   * @retval None
00496   */
00497 void LM75_LowLevel_DeInit(void)
00498 {
00499   GPIO_InitTypeDef  GPIO_InitStructure;
00500
00501   /*!< Disable LM75_I2C */
00502   I2C_Cmd(LM75_I2C, DISABLE);
00503
00504   /*!< DeInitializes the LM75_I2C */
00505   I2C_DeInit(LM75_I2C);
00506
00507   /*!< LM75_I2C Periph clock disable */
00508   RCC_APB1PeriphClockCmd(LM75_I2C_CLK, DISABLE);
00509
00510   /*!< Configure LM75_I2C pins: SCL */
00511   GPIO_InitStructure.GPIO_Pin = LM75_I2C_SCL_PIN;
00512   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
00513   GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
00514   GPIO_Init(LM75_I2C_SCL_GPIO_PORT, &GPIO_InitStructure);
00515
00516   /*!< Configure LM75_I2C pins: SDA */
00517   GPIO_InitStructure.GPIO_Pin = LM75_I2C_SDA_PIN;
00518   GPIO_Init(LM75_I2C_SDA_GPIO_PORT, &GPIO_InitStructure);
00519
00520   /*!< Configure LM75_I2C pin: SMBUS ALERT */
00521   GPIO_InitStructure.GPIO_Pin = LM75_I2C_SMBUSALERT_PIN;
00522   GPIO_Init(LM75_I2C_SMBUSALERT_GPIO_PORT, &GPIO_InitStructure);
00523 }
00524
00525 /**
00526   * @brief  Initializes the LM75_I2C.
00527   * @param  None
00528   * @retval None
00529   */
00530 void LM75_LowLevel_Init(void)
00531 {
00532   GPIO_InitTypeDef  GPIO_InitStructure;
00533
00534   /*!< LM75_I2C Periph clock enable */
00535   RCC_APB1PeriphClockCmd(LM75_I2C_CLK, ENABLE);
00536
00537   /*!< LM75_I2C_SCL_GPIO_CLK, LM75_I2C_SDA_GPIO_CLK
00538        and LM75_I2C_SMBUSALERT_GPIO_CLK Periph clock enable */
00539   RCC_AHBPeriphClockCmd(LM75_I2C_SCL_GPIO_CLK | LM75_I2C_SDA_GPIO_CLK |
00540                         LM75_I2C_SMBUSALERT_GPIO_CLK, ENABLE);
00541
00542   /*!< Configure LM75_I2C pins: SCL */
00543   GPIO_InitStructure.GPIO_Pin = LM75_I2C_SCL_PIN;
00544   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
00545   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_40MHz;
00546   GPIO_InitStructure.GPIO_OType = GPIO_OType_OD;
00547   GPIO_InitStructure.GPIO_PuPd  = GPIO_PuPd_NOPULL;
00548   GPIO_Init(LM75_I2C_SCL_GPIO_PORT, &GPIO_InitStructure);
00549
00550   /*!< Configure LM75_I2C pins: SDA */
00551   GPIO_InitStructure.GPIO_Pin = LM75_I2C_SDA_PIN;
00552   GPIO_Init(LM75_I2C_SDA_GPIO_PORT, &GPIO_InitStructure);
00553
00554   /*!< Configure LM75_I2C pin: SMBUS ALERT */
00555   GPIO_InitStructure.GPIO_Pin = LM75_I2C_SMBUSALERT_PIN;
00556   GPIO_Init(LM75_I2C_SMBUSALERT_GPIO_PORT, &GPIO_InitStructure);
00557
00558
00559   /* Connect PXx to I2C_SCL */
00560   GPIO_PinAFConfig(LM75_I2C_SCL_GPIO_PORT, LM75_I2C_SCL_SOURCE, LM75_I2C_SCL_AF);
00561
00562   /* Connect PXx to I2C_SDA */
00563   GPIO_PinAFConfig(LM75_I2C_SDA_GPIO_PORT, LM75_I2C_SDA_SOURCE, LM75_I2C_SDA_AF);
00564
00565   /* Connect PXx to I2C_SMBUSALER */
00566   GPIO_PinAFConfig(LM75_I2C_SMBUSALERT_GPIO_PORT, LM75_I2C_SMBUSALERT_SOURCE, LM75_I2C_SMBUSALERT_AF);
00567 }
00568
00569 /**
00570   * @brief  DeInitializes peripherals used by the I2C EEPROM driver.
00571   * @param  None
00572   * @retval None
00573   */
00574 void sEE_LowLevel_DeInit(void)
00575 {
00576   GPIO_InitTypeDef  GPIO_InitStructure;
00577   NVIC_InitTypeDef NVIC_InitStructure;
00578
00579   /* sEE_I2C Peripheral Disable */
00580   I2C_Cmd(sEE_I2C, DISABLE);
00581
00582   /* sEE_I2C DeInit */
00583   I2C_DeInit(sEE_I2C);
00584
00585   /*!< sEE_I2C Periph clock disable */
00586   RCC_APB1PeriphClockCmd(sEE_I2C_CLK, DISABLE);
00587
00588   /*!< GPIO configuration */
00589   /*!< Configure sEE_I2C pins: SCL */
00590   GPIO_InitStructure.GPIO_Pin = sEE_I2C_SCL_PIN;
00591   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
00592   GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
00593   GPIO_Init(sEE_I2C_SCL_GPIO_PORT, &GPIO_InitStructure);
00594
00595   /*!< Configure sEE_I2C pins: SDA */
00596   GPIO_InitStructure.GPIO_Pin = sEE_I2C_SDA_PIN;
00597   GPIO_Init(sEE_I2C_SDA_GPIO_PORT, &GPIO_InitStructure);
00598
00599   /* Configure and enable I2C DMA TX Channel interrupt */
00600   NVIC_InitStructure.NVIC_IRQChannel = sEE_I2C_DMA_TX_IRQn;
00601   NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = sEE_I2C_DMA_PREPRIO;
00602   NVIC_InitStructure.NVIC_IRQChannelSubPriority = sEE_I2C_DMA_SUBPRIO;
00603   NVIC_InitStructure.NVIC_IRQChannelCmd = DISABLE;
00604   NVIC_Init(&NVIC_InitStructure);
00605
00606   /* Configure and enable I2C DMA RX Channel interrupt */
00607   NVIC_InitStructure.NVIC_IRQChannel = sEE_I2C_DMA_RX_IRQn;
00608   NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = sEE_I2C_DMA_PREPRIO;
00609   NVIC_InitStructure.NVIC_IRQChannelSubPriority = sEE_I2C_DMA_SUBPRIO;
00610   NVIC_Init(&NVIC_InitStructure);
00611
00612   /* Disable and Deinitialize the DMA channels */
00613   DMA_Cmd(sEE_I2C_DMA_CHANNEL_TX, DISABLE);
00614   DMA_Cmd(sEE_I2C_DMA_CHANNEL_RX, DISABLE);
00615   DMA_DeInit(sEE_I2C_DMA_CHANNEL_TX);
00616   DMA_DeInit(sEE_I2C_DMA_CHANNEL_RX);
00617 }
00618
00619 /**
00620   * @brief  Initializes peripherals used by the I2C EEPROM driver.
00621   * @param  None
00622   * @retval None
00623   */
00624 void sEE_LowLevel_Init(void)
00625 {
00626   GPIO_InitTypeDef  GPIO_InitStructure;
00627   NVIC_InitTypeDef NVIC_InitStructure;
00628
00629   /*!< sEE_I2C Periph clock enable */
00630   RCC_APB1PeriphClockCmd(sEE_I2C_CLK, ENABLE);
00631
00632   /*!< sEE_I2C_SCL_GPIO_CLK and sEE_I2C_SDA_GPIO_CLK Periph clock enable */
00633   RCC_AHBPeriphClockCmd(sEE_I2C_SCL_GPIO_CLK | sEE_I2C_SDA_GPIO_CLK, ENABLE);
00634
00635   RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
00636
00637   /* Reset sEE_I2C peripheral */
00638   RCC_APB1PeriphResetCmd(sEE_I2C_CLK, ENABLE);
00639
00640   /* Release reset signal of sEE_I2C IP */
00641   RCC_APB1PeriphResetCmd(sEE_I2C_CLK, DISABLE);
00642
00643   /*!< GPIO configuration */
00644   /*!< Configure sEE_I2C pins: SCL */
00645   GPIO_InitStructure.GPIO_Pin = sEE_I2C_SCL_PIN;
00646   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
00647   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_40MHz;
00648   GPIO_InitStructure.GPIO_OType = GPIO_OType_OD;
00649   GPIO_InitStructure.GPIO_PuPd  = GPIO_PuPd_NOPULL;
00650   GPIO_Init(sEE_I2C_SCL_GPIO_PORT, &GPIO_InitStructure);
00651
00652   /*!< Configure sEE_I2C pins: SDA */
00653   GPIO_InitStructure.GPIO_Pin = sEE_I2C_SDA_PIN;
00654   GPIO_Init(sEE_I2C_SDA_GPIO_PORT, &GPIO_InitStructure);
00655
00656   /* Connect PXx to I2C_SCL*/
00657   GPIO_PinAFConfig(sEE_I2C_SCL_GPIO_PORT, sEE_I2C_SCL_SOURCE, sEE_I2C_SCL_AF);
00658
00659   /* Connect PXx to I2C_SDA*/
00660   GPIO_PinAFConfig(sEE_I2C_SDA_GPIO_PORT, sEE_I2C_SDA_SOURCE, sEE_I2C_SDA_AF);
00661
00662   /* Configure and enable I2C DMA TX Channel interrupt */
00663   NVIC_InitStructure.NVIC_IRQChannel = sEE_I2C_DMA_TX_IRQn;
00664   NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = sEE_I2C_DMA_PREPRIO;
00665   NVIC_InitStructure.NVIC_IRQChannelSubPriority = sEE_I2C_DMA_SUBPRIO;
00666   NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
00667   NVIC_Init(&NVIC_InitStructure);
00668
00669   /* Configure and enable I2C DMA RX Channel interrupt */
00670   NVIC_InitStructure.NVIC_IRQChannel = sEE_I2C_DMA_RX_IRQn;
00671   NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = sEE_I2C_DMA_PREPRIO;
00672   NVIC_InitStructure.NVIC_IRQChannelSubPriority = sEE_I2C_DMA_SUBPRIO;
00673   NVIC_Init(&NVIC_InitStructure);
00674
00675   /*!< I2C DMA TX and RX channels configuration */
00676   /* Enable the DMA clock */
00677   RCC_AHBPeriphClockCmd(sEE_I2C_DMA_CLK, ENABLE);
00678
00679   /* I2C TX DMA Channel configuration */
00680   DMA_DeInit(sEE_I2C_DMA_CHANNEL_TX);
00681   sEEDMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)sEE_I2C_DR_Address;
00682   sEEDMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)0;   /* This parameter will be configured durig communication */
00683   sEEDMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;    /* This parameter will be configured durig communication */
00684   sEEDMA_InitStructure.DMA_BufferSize = 0xFFFF;            /* This parameter will be configured durig communication */
00685   sEEDMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
00686   sEEDMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
00687   sEEDMA_InitStructure.DMA_PeripheralDataSize = DMA_MemoryDataSize_Byte;
00688   sEEDMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
00689   sEEDMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
00690   sEEDMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh;
00691   sEEDMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
00692   DMA_Init(sEE_I2C_DMA_CHANNEL_TX, &sEEDMA_InitStructure);
00693
00694   /* I2C RX DMA Channel configuration */
00695   DMA_DeInit(sEE_I2C_DMA_CHANNEL_RX);
00696   DMA_Init(sEE_I2C_DMA_CHANNEL_RX, &sEEDMA_InitStructure);
00697
00698   /* Enable the DMA Channels Interrupts */
00699   DMA_ITConfig(sEE_I2C_DMA_CHANNEL_TX, DMA_IT_TC, ENABLE);
00700   DMA_ITConfig(sEE_I2C_DMA_CHANNEL_RX, DMA_IT_TC, ENABLE);
00701 }
00702
00703 /**
00704   * @brief  Initializes DMA channel used by the I2C EEPROM driver.
00705   * @param  None
00706   * @retval None
00707   */
00708 void sEE_LowLevel_DMAConfig(uint32_t pBuffer, uint32_t BufferSize, uint32_t Direction)
00709 {
00710   /* Initialize the DMA with the new parameters */
00711   if (Direction == sEE_DIRECTION_TX)
00712   {
00713     /* Configure the DMA Tx Channel with the buffer address and the buffer size */
00714     sEEDMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)pBuffer;
00715     sEEDMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
00716     sEEDMA_InitStructure.DMA_BufferSize = (uint32_t)BufferSize;
00717     DMA_Init(sEE_I2C_DMA_CHANNEL_TX, &sEEDMA_InitStructure);
00718   }
00719   else
00720   {
00721     /* Configure the DMA Rx Channel with the buffer address and the buffer size */
00722     sEEDMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)pBuffer;
00723     sEEDMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
00724     sEEDMA_InitStructure.DMA_BufferSize = (uint32_t)BufferSize;
00725     DMA_Init(sEE_I2C_DMA_CHANNEL_RX, &sEEDMA_InitStructure);
00726   }
00727 }
00728
00729 /**
00730   * @}
00731   */
00732
00733
00734 /**
00735   * @}
00736   */
00737
00738 /**
00739   * @}
00740   */
00741
00742 /**
00743   * @}
00744   */
00745
00746 /**
00747   * @}
00748   */
00749
00750 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32l152_eval.h Source File

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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • STM32L152_EVAL

stm32l152_eval.h

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l152_eval.h
00004   * @author  MCD Application Team
00005   * @version V4.5.0
00006   * @date    07-March-2011
00007   * @brief   This file contains definitions for STM32L152_EVAL's Leds, push-buttons
00008   *          and COM ports hardware resources.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00013   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00014   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00015   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00016   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00017   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00018   *
00019   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00020   ******************************************************************************
00021   */
00022
00023 /* Define to prevent recursive inclusion -------------------------------------*/
00024 #ifndef __STM32L152_EVAL_H
00025 #define __STM32L152_EVAL_H
00026
00027 #ifdef __cplusplus
00028  extern "C" {
00029 #endif
00030
00031 /* Includes ------------------------------------------------------------------*/
00032 #include "stm32_eval.h"
00033
00034 /** @addtogroup Utilities
00035   * @{
00036   */
00037
00038 /** @addtogroup STM32_EVAL
00039   * @{
00040   */
00041
00042 /** @addtogroup STM32L152_EVAL
00043   * @{
00044   */
00045
00046 /** @addtogroup STM32L152_EVAL_LOW_LEVEL
00047   * @{
00048   */
00049
00050 /** @defgroup STM32L152_EVAL_LOW_LEVEL_Exported_Types
00051   * @{
00052   */
00053 /**
00054   * @}
00055   */
00056
00057 /** @defgroup STM32L152_EVAL_LOW_LEVEL_Exported_Constants
00058   * @{
00059   */
00060
00061 /** @addtogroup STM32L152_EVAL_LOW_LEVEL_LED
00062   * @{
00063   */
00064 #define LEDn                             4
00065
00066 #define LED1_PIN                         GPIO_Pin_0
00067 #define LED1_GPIO_PORT                   GPIOD
00068 #define LED1_GPIO_CLK                    RCC_AHBPeriph_GPIOD
00069
00070 #define LED2_PIN                         GPIO_Pin_1
00071 #define LED2_GPIO_PORT                   GPIOD
00072 #define LED2_GPIO_CLK                    RCC_AHBPeriph_GPIOD
00073
00074 #define LED3_PIN                         GPIO_Pin_4
00075 #define LED3_GPIO_PORT                   GPIOD
00076 #define LED3_GPIO_CLK                    RCC_AHBPeriph_GPIOD
00077
00078 #define LED4_PIN                         GPIO_Pin_5
00079 #define LED4_GPIO_PORT                   GPIOD
00080 #define LED4_GPIO_CLK                    RCC_AHBPeriph_GPIOD
00081
00082 /**
00083   * @}
00084   */
00085
00086 /** @addtogroup STM32L152_EVAL_LOW_LEVEL_BUTTON
00087   * @{
00088   */
00089 #define BUTTONn                          6
00090 /* On STM32L152-EVAL board, the KEY button is connected to PC.13 and it can
00091 be use as Tamper and Wakeup pin buttons. */
00092
00093 /**
00094  * @brief Key push-button
00095  */
00096 #define KEY_BUTTON_PIN                   GPIO_Pin_0
00097 #define KEY_BUTTON_GPIO_PORT             GPIOA
00098 #define KEY_BUTTON_GPIO_CLK              RCC_AHBPeriph_GPIOA
00099 #define KEY_BUTTON_EXTI_LINE             EXTI_Line0
00100 #define KEY_BUTTON_EXTI_PORT_SOURCE      EXTI_PortSourceGPIOA
00101 #define KEY_BUTTON_EXTI_PIN_SOURCE       EXTI_PinSource0
00102 #define KEY_BUTTON_EXTI_IRQn             EXTI0_IRQn
00103
00104 /**
00105  * @brief Joystick Right push-button
00106  */
00107 #define RIGHT_BUTTON_PIN                 GPIO_Pin_11
00108 #define RIGHT_BUTTON_GPIO_PORT           GPIOE
00109 #define RIGHT_BUTTON_GPIO_CLK            RCC_AHBPeriph_GPIOE
00110 #define RIGHT_BUTTON_EXTI_LINE           EXTI_Line11
00111 #define RIGHT_BUTTON_EXTI_PORT_SOURCE    EXTI_PortSourceGPIOE
00112 #define RIGHT_BUTTON_EXTI_PIN_SOURCE     EXTI_PinSource11
00113 #define RIGHT_BUTTON_EXTI_IRQn           EXTI15_10_IRQn
00114
00115 /**
00116  * @brief Joystick Left push-button
00117  */
00118 #define LEFT_BUTTON_PIN                  GPIO_Pin_12
00119 #define LEFT_BUTTON_GPIO_PORT            GPIOE
00120 #define LEFT_BUTTON_GPIO_CLK             RCC_AHBPeriph_GPIOE
00121 #define LEFT_BUTTON_EXTI_LINE            EXTI_Line12
00122 #define LEFT_BUTTON_EXTI_PORT_SOURCE     EXTI_PortSourceGPIOE
00123 #define LEFT_BUTTON_EXTI_PIN_SOURCE      EXTI_PinSource12
00124 #define LEFT_BUTTON_EXTI_IRQn            EXTI15_10_IRQn
00125
00126 /**
00127  * @brief Joystick Up push-button
00128  */
00129 #define UP_BUTTON_PIN                    GPIO_Pin_9
00130 #define UP_BUTTON_GPIO_PORT              GPIOE
00131 #define UP_BUTTON_GPIO_CLK               RCC_AHBPeriph_GPIOE
00132 #define UP_BUTTON_EXTI_LINE              EXTI_Line9
00133 #define UP_BUTTON_EXTI_PORT_SOURCE       EXTI_PortSourceGPIOE
00134 #define UP_BUTTON_EXTI_PIN_SOURCE        EXTI_PinSource9
00135 #define UP_BUTTON_EXTI_IRQn              EXTI9_5_IRQn
00136
00137 /**
00138  * @brief Joystick Down push-button
00139  */
00140 #define DOWN_BUTTON_PIN                  GPIO_Pin_10
00141 #define DOWN_BUTTON_GPIO_PORT            GPIOE
00142 #define DOWN_BUTTON_GPIO_CLK             RCC_AHBPeriph_GPIOE
00143 #define DOWN_BUTTON_EXTI_LINE            EXTI_Line10
00144 #define DOWN_BUTTON_EXTI_PORT_SOURCE     EXTI_PortSourceGPIOE
00145 #define DOWN_BUTTON_EXTI_PIN_SOURCE      EXTI_PinSource10
00146 #define DOWN_BUTTON_EXTI_IRQn            EXTI15_10_IRQn
00147
00148 /**
00149  * @brief Joystick Sel push-button
00150  */
00151 #define SEL_BUTTON_PIN                   GPIO_Pin_8
00152 #define SEL_BUTTON_GPIO_PORT             GPIOE
00153 #define SEL_BUTTON_GPIO_CLK              RCC_AHBPeriph_GPIOE
00154 #define SEL_BUTTON_EXTI_LINE             EXTI_Line8
00155 #define SEL_BUTTON_EXTI_PORT_SOURCE      EXTI_PortSourceGPIOE
00156 #define SEL_BUTTON_EXTI_PIN_SOURCE       EXTI_PinSource8
00157 #define SEL_BUTTON_EXTI_IRQn             EXTI9_5_IRQn
00158
00159 /**
00160   * @}
00161   */
00162
00163 /** @addtogroup STM32L152_EVAL_LOW_LEVEL_COM
00164   * @{
00165   */
00166 #define COMn                             2
00167
00168 /**
00169  * @brief Definition for COM port1, connected to USART2
00170  */
00171 #define EVAL_COM1                        USART2
00172 #define EVAL_COM1_CLK                    RCC_APB1Periph_USART2
00173
00174 #define EVAL_COM1_TX_PIN                 GPIO_Pin_5
00175 #define EVAL_COM1_TX_GPIO_PORT           GPIOD
00176 #define EVAL_COM1_TX_GPIO_CLK            RCC_AHBPeriph_GPIOD
00177 #define EVAL_COM1_TX_SOURCE              GPIO_PinSource5
00178 #define EVAL_COM1_TX_AF                  GPIO_AF_USART2
00179
00180 #define EVAL_COM1_RX_PIN                 GPIO_Pin_6
00181 #define EVAL_COM1_RX_GPIO_PORT           GPIOD
00182 #define EVAL_COM1_RX_GPIO_CLK            RCC_AHBPeriph_GPIOD
00183 #define EVAL_COM1_RX_SOURCE              GPIO_PinSource6
00184 #define EVAL_COM1_RX_AF                  GPIO_AF_USART2
00185
00186 #define EVAL_COM1_RTS_PIN                GPIO_Pin_4
00187 #define EVAL_COM1_RTS_GPIO_PORT          GPIOD
00188 #define EVAL_COM1_RTS_GPIO_CLK           RCC_AHBPeriph_GPIOD
00189 #define EVAL_COM1_RTS_SOURCE             GPIO_PinSource4
00190 #define EVAL_COM1_RTS_AF                 GPIO_AF_USART2
00191
00192 #define EVAL_COM1_CTS_PIN                GPIO_Pin_3
00193 #define EVAL_COM1_CTS_GPIO_PORT          GPIOD
00194 #define EVAL_COM1_CTS_GPIO_CLK           RCC_AHBPeriph_GPIOD
00195 #define EVAL_COM1_CTS_SOURCE             GPIO_PinSource3
00196 #define EVAL_COM1_CTS_AF                 GPIO_AF_USART2
00197
00198 #define EVAL_COM1_IRQn                   USART2_IRQn
00199
00200 /**
00201  * @brief Definition for COM port2, connected to USART3
00202  */
00203 #define EVAL_COM2                        USART3
00204 #define EVAL_COM2_CLK                    RCC_APB1Periph_USART3
00205
00206 #define EVAL_COM2_TX_PIN                 GPIO_Pin_10
00207 #define EVAL_COM2_TX_GPIO_PORT           GPIOC
00208 #define EVAL_COM2_TX_GPIO_CLK            RCC_AHBPeriph_GPIOC
00209 #define EVAL_COM2_TX_SOURCE              GPIO_PinSource10
00210 #define EVAL_COM2_TX_AF                  GPIO_AF_USART3
00211
00212 #define EVAL_COM2_RX_PIN                 GPIO_Pin_11
00213 #define EVAL_COM2_RX_GPIO_PORT           GPIOC
00214 #define EVAL_COM2_RX_GPIO_CLK            RCC_AHBPeriph_GPIOC
00215 #define EVAL_COM2_RX_SOURCE              GPIO_PinSource11
00216 #define EVAL_COM2_RX_AF                  GPIO_AF_USART3
00217
00218 #define EVAL_COM2_IRQn                   USART3_IRQn
00219
00220 /**
00221   * @}
00222   */
00223
00224 /** @addtogroup STM32L152_EVAL_LOW_LEVEL_SD_FLASH
00225   * @{
00226   */
00227 /**
00228   * @brief  SD Card SPI Interface
00229   */
00230 #define SD_SPI                           SPI2
00231 #define SD_SPI_CLK                       RCC_APB1Periph_SPI2
00232 #define SD_SPI_SCK_PIN                   GPIO_Pin_13                 /* PB.13 */
00233 #define SD_SPI_SCK_GPIO_PORT             GPIOB                       /* GPIOB */
00234 #define SD_SPI_SCK_GPIO_CLK              RCC_AHBPeriph_GPIOB
00235 #define SD_SPI_SCK_SOURCE                GPIO_PinSource13
00236 #define SD_SPI_SCK_AF                    GPIO_AF_SPI2
00237 #define SD_SPI_MISO_PIN                  GPIO_Pin_14                 /* PB.14 */
00238 #define SD_SPI_MISO_GPIO_PORT            GPIOB                       /* GPIOB */
00239 #define SD_SPI_MISO_GPIO_CLK             RCC_AHBPeriph_GPIOB
00240 #define SD_SPI_MISO_SOURCE               GPIO_PinSource14
00241 #define SD_SPI_MISO_AF                   GPIO_AF_SPI2
00242 #define SD_SPI_MOSI_PIN                  GPIO_Pin_15                 /* PB.15 */
00243 #define SD_SPI_MOSI_GPIO_PORT            GPIOB                       /* GPIOB */
00244 #define SD_SPI_MOSI_GPIO_CLK             RCC_AHBPeriph_GPIOB
00245 #define SD_SPI_MOSI_SOURCE               GPIO_PinSource15
00246 #define SD_SPI_MOSI_AF                   GPIO_AF_SPI2
00247 #define SD_CS_PIN                        GPIO_Pin_7                  /* PD.07 */
00248 #define SD_CS_GPIO_PORT                  GPIOD                       /* GPIOD */
00249 #define SD_CS_GPIO_CLK                   RCC_AHBPeriph_GPIOD
00250 #define SD_DETECT_PIN                    GPIO_Pin_6                  /* PE.06 */
00251 #define SD_DETECT_EXTI_LINE              EXTI_Line6
00252 #define SD_DETECT_EXTI_PIN_SOURCE        EXTI_PinSource6
00253
00254 #define SD_DETECT_GPIO_PORT              GPIOE                       /* GPIOE */
00255 #define SD_DETECT_GPIO_CLK               RCC_AHBPeriph_GPIOE
00256 #define SD_DETECT_EXTI_PORT_SOURCE       EXTI_PortSourceGPIOE
00257 #define SD_DETECT_EXTI_IRQn              EXTI9_5_IRQn
00258 /**
00259   * @}
00260   */
00261
00262 /** @addtogroup STM32L152_EVAL_LOW_LEVEL_TSENSOR_I2C
00263   * @{
00264   */
00265 /**
00266   * @brief  LM75 Temperature Sensor I2C Interface pins
00267   */
00268 #define LM75_I2C                         I2C1
00269 #define LM75_I2C_CLK                     RCC_APB1Periph_I2C1
00270 #define LM75_I2C_SCL_PIN                 GPIO_Pin_6                  /* PB.06 */
00271 #define LM75_I2C_SCL_GPIO_PORT           GPIOB                       /* GPIOB */
00272 #define LM75_I2C_SCL_GPIO_CLK            RCC_AHBPeriph_GPIOB
00273 #define LM75_I2C_SCL_SOURCE              GPIO_PinSource6
00274 #define LM75_I2C_SCL_AF                  GPIO_AF_I2C1
00275 #define LM75_I2C_SDA_PIN                 GPIO_Pin_7                  /* PB.07 */
00276 #define LM75_I2C_SDA_GPIO_PORT           GPIOB                       /* GPIOB */
00277 #define LM75_I2C_SDA_GPIO_CLK            RCC_AHBPeriph_GPIOB
00278 #define LM75_I2C_SDA_SOURCE              GPIO_PinSource7
00279 #define LM75_I2C_SDA_AF                  GPIO_AF_I2C1
00280 #define LM75_I2C_SMBUSALERT_PIN          GPIO_Pin_5                  /* PB.05 */
00281 #define LM75_I2C_SMBUSALERT_GPIO_PORT    GPIOB                       /* GPIOB */
00282 #define LM75_I2C_SMBUSALERT_GPIO_CLK     RCC_AHBPeriph_GPIOB
00283 #define LM75_I2C_SMBUSALERT_SOURCE       GPIO_PinSource5
00284 #define LM75_I2C_SMBUSALERT_AF           GPIO_AF_I2C1
00285 #define LM75_I2C_DR                      ((uint32_t)0x40005410)
00286
00287 #define LM75_DMA_CLK                     RCC_AHBPeriph_DMA1
00288 #define LM75_DMA_TX_CHANNEL              DMA1_Channel6
00289 #define LM75_DMA_RX_CHANNEL              DMA1_Channel7
00290 #define LM75_DMA_TX_TCFLAG               DMA1_FLAG_TC6
00291 #define LM75_DMA_RX_TCFLAG               DMA1_FLAG_TC7
00292
00293 /**
00294   * @}
00295   */
00296
00297 /** @addtogroup STM32L152_EVAL_LOW_LEVEL_I2C_EE
00298   * @{
00299   */
00300 /**
00301   * @brief  I2C EEPROM Interface pins
00302   */
00303
00304 #define sEE_I2C                          I2C1
00305 #define sEE_I2C_CLK                      RCC_APB1Periph_I2C1
00306 #define sEE_I2C_SCL_PIN                  GPIO_Pin_6                  /* PB.06 */
00307 #define sEE_I2C_SCL_GPIO_PORT            GPIOB                       /* GPIOB */
00308 #define sEE_I2C_SCL_GPIO_CLK             RCC_AHBPeriph_GPIOB
00309 #define sEE_I2C_SCL_SOURCE               GPIO_PinSource6
00310 #define sEE_I2C_SCL_AF                   GPIO_AF_I2C1
00311 #define sEE_I2C_SDA_PIN                  GPIO_Pin_7                  /* PB.07 */
00312 #define sEE_I2C_SDA_GPIO_PORT            GPIOB                       /* GPIOB */
00313 #define sEE_I2C_SDA_GPIO_CLK             RCC_AHBPeriph_GPIOB
00314 #define sEE_I2C_SDA_SOURCE               GPIO_PinSource7
00315 #define sEE_I2C_SDA_AF                   GPIO_AF_I2C1
00316 #define sEE_M24C64_32
00317
00318 #define sEE_I2C_DMA                      DMA1
00319 #define sEE_I2C_DMA_CHANNEL_TX           DMA1_Channel6
00320 #define sEE_I2C_DMA_CHANNEL_RX           DMA1_Channel7
00321 #define sEE_I2C_DMA_FLAG_TX_TC           DMA1_IT_TC6
00322 #define sEE_I2C_DMA_FLAG_TX_GL           DMA1_IT_GL6
00323 #define sEE_I2C_DMA_FLAG_RX_TC           DMA1_IT_TC7
00324 #define sEE_I2C_DMA_FLAG_RX_GL           DMA1_IT_GL7
00325 #define sEE_I2C_DMA_CLK                  RCC_AHBPeriph_DMA1
00326 #define sEE_I2C_DR_Address               ((uint32_t)0x40005410)
00327 #define sEE_USE_DMA
00328
00329 #define sEE_I2C_DMA_TX_IRQn              DMA1_Channel6_IRQn
00330 #define sEE_I2C_DMA_RX_IRQn              DMA1_Channel7_IRQn
00331 #define sEE_I2C_DMA_TX_IRQHandler        DMA1_Channel6_IRQHandler
00332 #define sEE_I2C_DMA_RX_IRQHandler        DMA1_Channel7_IRQHandler
00333 #define sEE_I2C_DMA_PREPRIO              0
00334 #define sEE_I2C_DMA_SUBPRIO              0
00335
00336 #define sEE_DIRECTION_TX                 0
00337 #define sEE_DIRECTION_RX                 1
00338
00339 /* Time constant for the delay caclulation allowing to have a millisecond
00340    incrementing counter. This value should be equal to (System Clock / 1000).
00341    ie. if system clock = 24MHz then sEE_TIME_CONST should be 24. */
00342 #define sEE_TIME_CONST          24
00343
00344 /**
00345   * @}
00346   */
00347
00348 /**
00349   * @}
00350   */
00351
00352 /** @defgroup STM32L152_EVAL_LOW_LEVEL_Exported_Macros
00353   * @{
00354   */
00355 /**
00356   * @}
00357   */
00358
00359
00360 /** @defgroup STM32L152_EVAL_LOW_LEVEL_Exported_Functions
00361   * @{
00362   */
00363 void STM_EVAL_LEDInit(Led_TypeDef Led);
00364 void STM_EVAL_LEDOn(Led_TypeDef Led);
00365 void STM_EVAL_LEDOff(Led_TypeDef Led);
00366 void STM_EVAL_LEDToggle(Led_TypeDef Led);
00367 void STM_EVAL_PBInit(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode);
00368 uint32_t STM_EVAL_PBGetState(Button_TypeDef Button);
00369 void STM_EVAL_COMInit(COM_TypeDef COM, USART_InitTypeDef* USART_InitStruct);
00370 void SD_LowLevel_DeInit(void);
00371 void SD_LowLevel_Init(void);
00372 void LM75_LowLevel_DeInit(void);
00373 void LM75_LowLevel_Init(void);
00374 void sEE_LowLevel_DeInit(void);
00375 void sEE_LowLevel_Init(void);
00376 void sEE_LowLevel_DMAConfig(uint32_t pBuffer, uint32_t BufferSize, uint32_t Direction);
00377
00378 /**
00379   * @}
00380   */
00381
00382 #ifdef __cplusplus
00383 }
00384 #endif
00385
00386 #endif /* __STM32L152_EVAL_H */
00387 /**
00388   * @}
00389   */
00390
00391 /**
00392   * @}
00393   */
00394
00395 /**
00396   * @}
00397   */
00398
00399 /**
00400   * @}
00401   */
00402
00403 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32l152_eval_glass_lcd.c Source File

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stm32l152_eval_glass_lcd.c

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l152_eval_glass_lcd.c
00004   * @author  MCD Application Team
00005   * @version V4.5.0
00006   * @date    07-March-2011
00007   * @brief   This file includes the LCD Glass driver for Pacific Display
00008   *          (LCD_PD878, PD878-DP-FH-W-LV-6-RH) Module of STM32L152-EVAL board RevB.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00013   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00014   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00015   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00016   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00017   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00018   *
00019   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00020   ******************************************************************************
00021   */
00022
00023 /* Includes ------------------------------------------------------------------*/
00024 #include "stm32l152_eval_glass_lcd.h"
00025
00026 /** @addtogroup Utilities
00027   * @{
00028   */
00029
00030 /** @addtogroup STM32_EVAL
00031   * @{
00032   */
00033
00034 /** @addtogroup STM32L152_EVAL
00035   * @{
00036   */
00037
00038 /** @defgroup STM32L152_EVAL_GLASS_LCD
00039   * @brief This file includes the LCD Glass driver for Pacific Display
00040   *        (LCD_PD878, PD878-DP-FH-W-LV-6-RH) Module of STM32L152-EVAL board.
00041   * @{
00042   */
00043
00044 /** @defgroup STM32L152_EVAL_GLASS_LCD_Private_Types
00045   * @{
00046   */
00047 /**
00048   * @}
00049   */
00050
00051
00052 /** @defgroup STM32L152_EVAL_GLASS_LCD_Private_Defines
00053   * @{
00054   */
00055 /**
00056   * @}
00057   */
00058
00059
00060 /** @defgroup STM32L152_EVAL_GLASS_LCD_Private_Macros
00061   * @{
00062   */
00063 /**
00064   * @}
00065   */
00066
00067
00068 /** @defgroup STM32L152_EVAL_GLASS_LCD_Private_Variables
00069   * @{
00070   */
00071
00072 /**
00073   @verbatim
00074 ================================================================================
00075                               GLASS LCD MAPPING
00076 ================================================================================
00077                A
00078       --  ----------
00079     X \/  |\   |I  /|
00080          F| H  |  J |B
00081           |  \ | /  |
00082           --G-- --K--
00083           |   /| \  |
00084         E |  L |  N |C
00085           | /  |M  \|   _
00086           -----------  | |DP
00087               D         -
00088
00089 A LCD character coding is based on the following matrix:
00090
00091
00092 { X , F , E , D  }
00093 { I , J , K , N  }
00094 { A , B , C , DP }
00095 { H , G , L , M  }
00096
00097 The character A for example is:
00098 -------------------------------
00099  { 0 , 1 , 1 , 0 }
00100  { 0 , 0 , 1 , 0 }
00101  { 1 , 1 , 1 , 0 }
00102  { 0 , 1 , 0 , 0 }
00103 -------------------
00104 =  4   D   7   0   hex
00105
00106 => 'A' = 0x4D70
00107
00108   @endverbatim
00109   */
00110
00111 /**
00112   * @brief LETTERS AND NUMBERS MAPPING DEFINITION
00113   */
00114 uint8_t digit[4];     /* Digit LCD RAM buffer */
00115 __I uint16_t mask[4] = {0xF000, 0x0F00, 0x00F0, 0x000F};
00116 __I uint8_t shift[4] = {0x0C, 0x08, 0x04, 0x00};
00117
00118 /* Letters and number map of PD_878 LCD */
00119 __I uint16_t LetterMap[26]=
00120 {
00121 /* A       B       C       D       E       F       G       H       I  */
00122 0x4D70, 0x6469, 0x4111, 0x6449, 0x4911, 0x4910, 0x4171, 0x0D70, 0x6009,
00123 /* J       K       L       M       N       O       P       Q       R  */
00124 0x0451, 0x0B12, 0x0111, 0x8750, 0x8552, 0x4551, 0x4D30, 0x4553, 0x4D32,
00125 /* S       T       U       V       W       X       Y       Z  */
00126 0x4961, 0x6008, 0x0551, 0x0390, 0x05D2, 0x8282, 0x8208, 0x4281
00127 };
00128
00129 __I uint16_t NumberMap[10]=
00130 {
00131 /* 0       1       2       3       4       5       6       7       8       9  */
00132 0x47D1, 0x0640, 0x4C31, 0x4C61, 0x0D60, 0x4961, 0x4971, 0x4440, 0x4D71, 0x4D61
00133 };
00134
00135 /**
00136   * @}
00137   */
00138
00139
00140 /** @defgroup STM32L152_EVAL_LCD_Private_Function_Prototypes
00141   * @{
00142   */
00143 static void Convert(uint8_t* c, Point_Typedef point, Apostrophe_Typedef apostrophe);
00144 static void delay(__IO uint32_t nCount);
00145 static void LCD_GPIOConfig(void);
00146
00147 /**
00148   * @}
00149   */
00150
00151 /** @defgroup STM32L152_EVAL_LCD_Private_Functions
00152   * @{
00153   */
00154
00155 /**
00156   * @brief  Configures the LCD GLASS relative GPIO port IOs and LCD peripheral.
00157   * @param  None
00158   * @retval None
00159   */
00160 void LCD_GLASS_Init(void)
00161 {
00162   LCD_InitTypeDef LCD_InitStructure;
00163
00164   LCD_GPIOConfig(); /*!< Configure the LCD Glass GPIO pins */
00165
00166   /*!< Configure the LCD interface -------------------------------------------*/
00167   RCC_APB1PeriphClockCmd(RCC_APB1Periph_LCD, ENABLE); /*!< Enable LCD APB1 Clock */
00168
00169   LCD_InitStructure.LCD_Prescaler = LCD_Prescaler_8;
00170   LCD_InitStructure.LCD_Divider = LCD_Divider_16;
00171   LCD_InitStructure.LCD_Duty = LCD_Duty_1_4;
00172   LCD_InitStructure.LCD_Bias = LCD_Bias_1_3;
00173   LCD_InitStructure.LCD_VoltageSource = LCD_VoltageSource_Internal;
00174   LCD_Init(&LCD_InitStructure);
00175
00176   /*!< Configure the Pulse On Duration */
00177   LCD_PulseOnDurationConfig(LCD_PulseOnDuration_2);
00178
00179   /*!< Configure the LCD Contrast (3.51V) */
00180   LCD_ContrastConfig(LCD_Contrast_Level_7);
00181
00182   /*!< Wait Until the LCD FCR register is synchronized */
00183   LCD_WaitForSynchro();
00184
00185   /*!< Enable LCD peripheral */
00186   LCD_Cmd(ENABLE);
00187
00188   /*!< Wait Until the LCD is enabled */
00189   while(LCD_GetFlagStatus(LCD_FLAG_ENS) == RESET)
00190   {
00191   }
00192   /*!< Wait Until the LCD Booster is ready */
00193   while(LCD_GetFlagStatus(LCD_FLAG_RDY) == RESET)
00194   {
00195   }
00196 }
00197
00198 /**
00199   * @brief  This function writes a char in the LCD RAM.
00200   * @param  ch: The character to dispaly.
00201   * @param  point: A point to add in front of char.
00202   *          This parameter  can be one of the following values:
00203   *              @arg POINT_OFF: No point to add in front of char.
00204   *              @arg POINT_ON: Add a point in front of char.
00205   * @param  apostrophe: Flag indicating if a apostrophe has to be add in front
00206   *                     of displayed character.
00207   *          This parameter  can be one of the following values:
00208   *              @arg APOSTROPHE_OFF: No apostrophe to add in back of char.
00209   *              @arg APOSTROPHE_ON: Add an apostrophe in back of char.
00210   * @param  position: Position in the LCD of the caracter to write.
00211   *                   This parameter can be any value in range [0:7].
00212   * @retval None
00213   */
00214 void LCD_GLASS_DisplayChar(uint8_t* ch, Point_Typedef point, Apostrophe_Typedef apostrophe, uint8_t position)
00215 {
00216   /*!< Wait Until the last LCD RAM update finish */
00217   while(LCD_GetFlagStatus(LCD_FLAG_UDR) != RESET)
00218   {
00219   }
00220   /*!< LCD Write Char */
00221   LCD_GLASS_WriteChar(ch, point, apostrophe, position);
00222
00223   /*!< Requesy LCD RAM update */
00224   LCD_UpdateDisplayRequest();
00225 }
00226
00227 /**
00228   * @brief  This function writes a char in the LCD RAM.
00229   * @param  ptr: Pointer to string to display on the LCD Glass.
00230   * @retval None
00231   */
00232 void LCD_GLASS_DisplayString(uint8_t* ptr)
00233 {
00234   uint32_t i = 0x00;
00235
00236   /*!< Wait Until the last LCD RAM update finish */
00237   while(LCD_GetFlagStatus(LCD_FLAG_UDR) != RESET)
00238   {
00239   }
00240
00241   /*!< Send the string character by character on lCD */
00242   while ((*ptr != 0) & (i < 8))
00243   {
00244     /*!< Display one character on LCD */
00245     LCD_GLASS_WriteChar(ptr, POINT_OFF, APOSTROPHE_OFF, i);
00246     /*!< Point on the next character */
00247     ptr++;
00248     /*!< Increment the character counter */
00249     i++;
00250   }
00251   /*!< Requesy LCD RAM update */
00252   LCD_UpdateDisplayRequest();
00253 }
00254
00255 /**
00256   * @brief  This function writes a char in the LCD RAM.
00257   * @param  ch: The character to dispaly.
00258   * @param  point: A point to add in front of char.
00259   *          This parameter  can be one of the following values:
00260   *              @arg POINT_OFF : No point to add in front of char.
00261   *              @arg POINT_ON : Add a point in front of char.
00262   * @param  apostrophe: Flag indicating if a apostrophe has to be add in front
00263   *                     of displayed character.
00264   *          This parameter  can be one of the following values:
00265   *              @arg APOSTROPHE_OFF : No apostrophe to add in back of char.
00266   *              @arg APOSTROPHE_ON : Add an apostrophe in back of char.
00267   * @param  position: Position in the LCD of the caracter to write.
00268   *          This parameter can be any value in range [0:7].
00269   * @retval None
00270   */
00271 void LCD_GLASS_WriteChar(uint8_t* ch, Point_Typedef point, Apostrophe_Typedef apostrophe, uint8_t position)
00272 {
00273   uint32_t tmp = 0x00;
00274
00275   Convert(ch, point, apostrophe); /*!< Convert the corresponding character */
00276
00277   switch (position)
00278   {
00279     case 7:
00280       /*!< Clear the corresponding segments (SEG0, SEG1, SEG2, SEG3) */
00281       LCD->RAM[LCD_RAMRegister_0] &= (uint32_t)(0xFFFFFFF0);
00282       LCD->RAM[LCD_RAMRegister_2] &= (uint32_t)(0xFFFFFFF0);
00283       LCD->RAM[LCD_RAMRegister_4] &= (uint32_t)(0xFFFFFFF0);
00284       LCD->RAM[LCD_RAMRegister_6] &= (uint32_t)(0xFFFFFFF0);
00285
00286       /*!< Write the corresponding segments (SEG0, SEG1, SEG2, SEG3) */
00287       LCD->RAM[LCD_RAMRegister_0] |= (uint32_t)(digit[0]);
00288       LCD->RAM[LCD_RAMRegister_2] |= (uint32_t)(digit[1]);
00289       LCD->RAM[LCD_RAMRegister_4] |= (uint32_t)(digit[2]);
00290       LCD->RAM[LCD_RAMRegister_6] |= (uint32_t)(digit[3]);
00291       break;
00292
00293     case 6:
00294       /*!< Clear the corresponding segments (SEG4, SEG5, SEG6, SEG10) */
00295       LCD->RAM[LCD_RAMRegister_0] &= (uint32_t)(0xFFFFFB8F);
00296       LCD->RAM[LCD_RAMRegister_2] &= (uint32_t)(0xFFFFFB8F);
00297       LCD->RAM[LCD_RAMRegister_4] &= (uint32_t)(0xFFFFFB8F);
00298       LCD->RAM[LCD_RAMRegister_6] &= (uint32_t)(0xFFFFFB8F);
00299
00300       /*!< Write the corresponding segments (SEG4, SEG5, SEG6, SEG10) */
00301       tmp = (((digit[0] & 0x8) << 7) | ((digit[0]& 0x7) << 4));
00302       LCD->RAM[LCD_RAMRegister_0] |= (uint32_t) tmp;
00303       tmp = (((digit[1] & 0x8) << 7) | ((digit[1]& 0x7) << 4));
00304       LCD->RAM[LCD_RAMRegister_2] |= (uint32_t) tmp;
00305       tmp = (((digit[2] & 0x8) << 7) | ((digit[2]& 0x7) << 4));
00306       LCD->RAM[LCD_RAMRegister_4] |= (uint32_t) tmp;
00307       tmp = (((digit[3] & 0x8) << 7) | ((digit[3]& 0x7) << 4));
00308       LCD->RAM[LCD_RAMRegister_6] |= (uint32_t) tmp;
00309       break;
00310
00311     case 5:
00312       /*!< Clear the corresponding segments (SEG11, SEG16, SEG18, SEG19) */
00313       LCD->RAM[LCD_RAMRegister_0] &= (uint32_t)(0xFFF2F7FF);
00314       LCD->RAM[LCD_RAMRegister_2] &= (uint32_t)(0xFFF2F7FF);
00315       LCD->RAM[LCD_RAMRegister_4] &= (uint32_t)(0xFFF2F7FF);
00316       LCD->RAM[LCD_RAMRegister_6] &= (uint32_t)(0xFFF2F7FF);
00317
00318       /*!< Write the corresponding segments (SEG11, SEG16, SEG18, SEG19) */
00319       tmp = (((digit[0] & 0x1) << 11) | ((digit[0]& 0x2) << 15) | ((digit[0]& 0xC) << 16));
00320       LCD->RAM[LCD_RAMRegister_0] |= (uint32_t)(tmp);
00321       tmp = (((digit[1] & 0x1) << 11) | ((digit[1]& 0x2) << 15) | ((digit[1]& 0xC) << 16));
00322       LCD->RAM[LCD_RAMRegister_2] |= (uint32_t)(tmp);
00323       tmp = (((digit[2] & 0x1) << 11) | ((digit[2]& 0x2) << 15) | ((digit[2]& 0xC) << 16));
00324       LCD->RAM[LCD_RAMRegister_4] |= (uint32_t)(tmp);
00325       tmp = (((digit[3] & 0x1) << 11) | ((digit[3]& 0x2) << 15) | ((digit[3]& 0xC) << 16));
00326       LCD->RAM[LCD_RAMRegister_6] |= (uint32_t)(tmp);
00327       break;
00328
00329     case 4:
00330       /*!< Clear the corresponding segments (SEG20, SEG21, SEG22, SEG23) */
00331       LCD->RAM[LCD_RAMRegister_0] &= (uint32_t)(0xFF0FFFFF);
00332       LCD->RAM[LCD_RAMRegister_2] &= (uint32_t)(0xFF0FFFFF);
00333       LCD->RAM[LCD_RAMRegister_4] &= (uint32_t)(0xFF0FFFFF);
00334       LCD->RAM[LCD_RAMRegister_6] &= (uint32_t)(0xFF0FFFFF);
00335
00336       /*!< Write the corresponding segments (SEG20, SEG21, SEG22, SEG23) */
00337       LCD->RAM[LCD_RAMRegister_0] |= (uint32_t)(digit[0] << 20);
00338       LCD->RAM[LCD_RAMRegister_2] |= (uint32_t)(digit[1] << 20);
00339       LCD->RAM[LCD_RAMRegister_4] |= (uint32_t)(digit[2] << 20);
00340       LCD->RAM[LCD_RAMRegister_6] |= (uint32_t)(digit[3] << 20);
00341       break;
00342
00343     case 3:
00344       /*!< Clear the corresponding segments (SEG28, SEG29, SEG30, SEG31) */
00345       LCD->RAM[LCD_RAMRegister_0] &= (uint32_t)(0x0FFFFFFF);
00346       LCD->RAM[LCD_RAMRegister_2] &= (uint32_t)(0x0FFFFFFF);
00347       LCD->RAM[LCD_RAMRegister_4] &= (uint32_t)(0x0FFFFFFF);
00348       LCD->RAM[LCD_RAMRegister_6] &= (uint32_t)(0x0FFFFFFF);
00349
00350       /*!< Write the corresponding segments (SEG28, SEG29, SEG30, SEG31) */
00351       LCD->RAM[LCD_RAMRegister_0] |= (uint32_t)(digit[0] << 28);
00352       LCD->RAM[LCD_RAMRegister_2] |= (uint32_t)(digit[1] << 28);
00353       LCD->RAM[LCD_RAMRegister_4] |= (uint32_t)(digit[2] << 28);
00354       LCD->RAM[LCD_RAMRegister_6] |= (uint32_t)(digit[3] << 28);
00355       break;
00356
00357     case 2:
00358       /*!< Clear the corresponding segments (SEG32, SEG33, SEG34, SEG35) */
00359       LCD->RAM[LCD_RAMRegister_1] &= (uint32_t)(0xFFFFFFF0);
00360       LCD->RAM[LCD_RAMRegister_3] &= (uint32_t)(0xFFFFFFF0);
00361       LCD->RAM[LCD_RAMRegister_5] &= (uint32_t)(0xFFFFFFF0);
00362       LCD->RAM[LCD_RAMRegister_7] &= (uint32_t)(0xFFFFFFF0);
00363
00364       /*!< Write the corresponding segments (SEG32, SEG33, SEG34, SEG35) */
00365       LCD->RAM[LCD_RAMRegister_1] |= (uint32_t)(digit[0] << 0);
00366       LCD->RAM[LCD_RAMRegister_3] |= (uint32_t)(digit[1] << 0);
00367       LCD->RAM[LCD_RAMRegister_5] |= (uint32_t)(digit[2] << 0);
00368       LCD->RAM[LCD_RAMRegister_7] |= (uint32_t)(digit[3] << 0);
00369       break;
00370
00371     case 1:
00372       /*!< Clear the corresponding segments (SEG36, SEG37, SEG38, SEG39) */
00373       LCD->RAM[LCD_RAMRegister_1] &= (uint32_t)(0xFFFFFF0F);
00374       LCD->RAM[LCD_RAMRegister_3] &= (uint32_t)(0xFFFFFF0F);
00375       LCD->RAM[LCD_RAMRegister_5] &= (uint32_t)(0xFFFFFF0F);
00376       LCD->RAM[LCD_RAMRegister_7] &= (uint32_t)(0xFFFFFF0F);
00377
00378       /*!< Write the corresponding segments (SEG36, SEG37, SEG38, SEG39) */
00379       LCD->RAM[LCD_RAMRegister_1] |= (uint32_t)(digit[0] << 4);
00380       LCD->RAM[LCD_RAMRegister_3] |= (uint32_t)(digit[1] << 4);
00381       LCD->RAM[LCD_RAMRegister_5] |= (uint32_t)(digit[2] << 4);
00382       LCD->RAM[LCD_RAMRegister_7] |= (uint32_t)(digit[3] << 4);
00383
00384       break;
00385
00386     case 0:
00387       /*!< Clear the corresponding segments (SEG40, SEG41, SEG42, SEG43) */
00388       LCD->RAM[LCD_RAMRegister_1] &= (uint32_t)(0xFFFFF0FF);
00389       LCD->RAM[LCD_RAMRegister_3] &= (uint32_t)(0xFFFFF0FF);
00390       LCD->RAM[LCD_RAMRegister_5] &= (uint32_t)(0xFFFFF0FF);
00391       LCD->RAM[LCD_RAMRegister_7] &= (uint32_t)(0xFFFFF0FF);
00392
00393       /*!< Write the corresponding segments (SEG40, SEG41, SEG42, SEG43) */
00394       LCD->RAM[LCD_RAMRegister_1] |= (uint32_t)(digit[0] << 8);
00395       LCD->RAM[LCD_RAMRegister_3] |= (uint32_t)(digit[1] << 8);
00396       LCD->RAM[LCD_RAMRegister_5] |= (uint32_t)(digit[2] << 8);
00397       LCD->RAM[LCD_RAMRegister_7] |= (uint32_t)(digit[3] << 8);
00398       break;
00399   }
00400 }
00401
00402 /**
00403   * @brief  Display a string in scrolling mode
00404   * @note   The LCD should be cleared before to start the write operation.
00405   * @param  ptr: Pointer to string to display on the LCD Glass.
00406   * @param  nScroll: Specifies how many time the message will be scrolled
00407   * @param  ScrollSpeed: Speciifes the speed of the scroll.
00408   *                     Low value gives higher speed.
00409   * @retval None
00410   */
00411 void LCD_GLASS_ScrollString(uint8_t* ptr, uint16_t nScroll, uint16_t ScrollSpeed)
00412 {
00413   uint8_t Repetition = 0;
00414   uint8_t* ptr1;
00415   uint8_t str[8] = "";
00416   ptr1 = ptr;
00417
00418   LCD_GLASS_DisplayString(ptr1);
00419
00420   delay(ScrollSpeed);
00421
00422   for (Repetition = 0; Repetition < nScroll; Repetition++)
00423   {
00424     *(str + 1) = *ptr1;
00425     *(str + 2) = *(ptr1 + 1);
00426     *(str + 3) = *(ptr1 + 2);
00427     *(str + 4) = *(ptr1 + 3);
00428     *(str + 5) = *(ptr1 + 4);
00429     *(str + 6) = *(ptr1 + 5);
00430     *(str + 7) =*(ptr1 + 6);
00431     *(str) = *(ptr1 + 7);
00432     LCD_GLASS_Clear();
00433     LCD_GLASS_DisplayString(str);
00434     delay(ScrollSpeed);
00435
00436     *(str + 1) = *(ptr1 + 7);
00437     *(str + 2) = *ptr1;
00438     *(str + 3) = *(ptr1 + 1);
00439     *(str + 4) = *(ptr1 + 2);
00440     *(str + 5) = *(ptr1 + 3);
00441     *(str + 6) = *(ptr1 + 4);
00442     *(str + 7) = *(ptr1 + 5);
00443     *(str) = *(ptr1 + 6);
00444     LCD_GLASS_Clear();
00445     LCD_GLASS_DisplayString(str);
00446     delay(ScrollSpeed);
00447
00448     *(str + 1) = *(ptr1 + 6);
00449     *(str + 2) = *(ptr1 + 7);
00450     *(str + 3) = *ptr1;
00451     *(str + 4) = *(ptr1 + 1);
00452     *(str + 5) = *(ptr1 + 2);
00453     *(str + 6) = *(ptr1 + 3);
00454     *(str + 7) = *(ptr1 + 4);
00455     *(str) = *(ptr1 + 5);
00456     LCD_GLASS_Clear();
00457     LCD_GLASS_DisplayString(str);
00458     delay(ScrollSpeed);
00459
00460     *(str + 1) = *(ptr1 + 5);
00461     *(str + 2) = *(ptr1 + 6);
00462     *(str + 3) = *(ptr1 + 7);
00463     *(str + 4) = *ptr1;
00464     *(str + 5) = *(ptr1 + 1);
00465     *(str + 6) = *(ptr1 + 2);
00466     *(str + 7) = *(ptr1 + 3);
00467     *(str) = *(ptr1 + 4);
00468     LCD_GLASS_Clear();
00469     LCD_GLASS_DisplayString(str);
00470     delay(ScrollSpeed);
00471
00472     *(str + 1) = *(ptr1 + 4);
00473     *(str + 2) = *(ptr1 + 5);
00474     *(str + 3) = *(ptr1 + 6);
00475     *(str + 4) = *(ptr1 + 7);
00476     *(str + 5) = *ptr1;
00477     *(str + 6) = *(ptr1 + 1);
00478     *(str + 7) = *(ptr1 + 2);
00479     *(str) = *(ptr1 + 3);
00480     LCD_GLASS_Clear();
00481     LCD_GLASS_DisplayString(str);
00482     delay(ScrollSpeed);
00483
00484     *(str + 1) = *(ptr1 + 3);
00485     *(str + 2) = *(ptr1 + 4);
00486     *(str + 3) = *(ptr1 + 5);
00487     *(str + 4) = *(ptr1 + 6);
00488     *(str + 5) = *(ptr1 + 7);
00489     *(str + 6) = *ptr1;
00490     *(str + 7) = *(ptr1 + 1);
00491     *(str) = *(ptr1 + 2);
00492     LCD_GLASS_Clear();
00493     LCD_GLASS_DisplayString(str);
00494     delay(ScrollSpeed);
00495
00496     *(str + 1) = *(ptr1 + 2);
00497     *(str + 2) = *(ptr1 + 3);
00498     *(str + 3) = *(ptr1 + 4);
00499     *(str + 4) = *(ptr1 + 5);
00500     *(str + 5) = *(ptr1 + 6);
00501     *(str + 6) = *(ptr1 + 7);
00502     *(str + 7) = *ptr1;
00503     *(str) = *(ptr1 + 1);
00504     LCD_GLASS_Clear();
00505     LCD_GLASS_DisplayString(str);
00506     delay(ScrollSpeed);
00507
00508     *(str + 1) = *(ptr1 + 1);
00509     *(str + 2) = *(ptr1 + 2);
00510     *(str + 3) = *(ptr1 + 3);
00511     *(str + 4) = *(ptr1 + 4);
00512     *(str + 5) = *(ptr1 + 5);
00513     *(str + 6) = *(ptr1 + 6);
00514     *(str + 7) = *(ptr1 + 7);
00515     *(str) = *(ptr1);
00516     LCD_GLASS_Clear();
00517     LCD_GLASS_DisplayString(str);
00518     delay(ScrollSpeed);
00519   }
00520 }
00521
00522 /**
00523   * @brief This function Clear a char in the LCD RAM.
00524   * @param position: Position in the LCD of the caracter to write.
00525   *                  This parameter can be any value in range [0:7].
00526   * @retval None
00527   */
00528 void LCD_GLASS_ClearChar(uint8_t position)
00529 {
00530   switch (position)
00531   {
00532     case 7:
00533       /*!< Clear the corresponding segments (SEG0, SEG1, SEG2, SEG3) */
00534       LCD->RAM[LCD_RAMRegister_0] &= (uint32_t)(0xFFFFFFF0);
00535       LCD->RAM[LCD_RAMRegister_2] &= (uint32_t)(0xFFFFFFF0);
00536       LCD->RAM[LCD_RAMRegister_4] &= (uint32_t)(0xFFFFFFF0);
00537       LCD->RAM[LCD_RAMRegister_6] &= (uint32_t)(0xFFFFFFF0);
00538       break;
00539
00540     case 6:
00541       /*!< Clear the corresponding segments (SEG4, SEG5, SEG6, SEG10) */
00542       LCD->RAM[LCD_RAMRegister_0] &= (uint32_t)(0xFFFFFB8F);
00543       LCD->RAM[LCD_RAMRegister_2] &= (uint32_t)(0xFFFFFB8F);
00544       LCD->RAM[LCD_RAMRegister_4] &= (uint32_t)(0xFFFFFB8F);
00545       LCD->RAM[LCD_RAMRegister_6] &= (uint32_t)(0xFFFFFB8F);
00546       break;
00547
00548     case 5:
00549       /*!< Clear the corresponding segments (SEG11, SEG16, SEG18, SEG19) */
00550       LCD->RAM[LCD_RAMRegister_0] &= (uint32_t)(0xFFF2F7FF);
00551       LCD->RAM[LCD_RAMRegister_2] &= (uint32_t)(0xFFF2F7FF);
00552       LCD->RAM[LCD_RAMRegister_4] &= (uint32_t)(0xFFF2F7FF);
00553       LCD->RAM[LCD_RAMRegister_6] &= (uint32_t)(0xFFF2F7FF);
00554       break;
00555
00556     case 4:
00557       /*!< Clear the corresponding segments (SEG20, SEG21, SEG22, SEG23) */
00558       LCD->RAM[LCD_RAMRegister_0] &= (uint32_t)(0xFF0FFFFF);
00559       LCD->RAM[LCD_RAMRegister_2] &= (uint32_t)(0xFF0FFFFF);
00560       LCD->RAM[LCD_RAMRegister_4] &= (uint32_t)(0xFF0FFFFF);
00561       LCD->RAM[LCD_RAMRegister_6] &= (uint32_t)(0xFF0FFFFF);
00562       break;
00563
00564     case 3:
00565       /*!< Clear the corresponding segments (SEG28, SEG29, SEG30, SEG31) */
00566       LCD->RAM[LCD_RAMRegister_0] &= (uint32_t)(0x0FFFFFFF);
00567       LCD->RAM[LCD_RAMRegister_2] &= (uint32_t)(0x0FFFFFFF);
00568       LCD->RAM[LCD_RAMRegister_4] &= (uint32_t)(0x0FFFFFFF);
00569       LCD->RAM[LCD_RAMRegister_6] &= (uint32_t)(0x0FFFFFFF);
00570       break;
00571
00572     case 2:
00573       /*!< Clear the corresponding segments (SEG32, SEG33, SEG34, SEG35) */
00574       LCD->RAM[LCD_RAMRegister_1] &= (uint32_t)(0xFFFFFFF0);
00575       LCD->RAM[LCD_RAMRegister_3] &= (uint32_t)(0xFFFFFFF0);
00576       LCD->RAM[LCD_RAMRegister_5] &= (uint32_t)(0xFFFFFFF0);
00577       LCD->RAM[LCD_RAMRegister_7] &= (uint32_t)(0xFFFFFFF0);
00578       break;
00579
00580     case 1:
00581       /*!< Clear the corresponding segments (SEG36, SEG37, SEG38, SEG39) */
00582       LCD->RAM[LCD_RAMRegister_1] &= (uint32_t)(0xFFFFFF0F);
00583       LCD->RAM[LCD_RAMRegister_3] &= (uint32_t)(0xFFFFFF0F);
00584       LCD->RAM[LCD_RAMRegister_5] &= (uint32_t)(0xFFFFFF0F);
00585       LCD->RAM[LCD_RAMRegister_7] &= (uint32_t)(0xFFFFFF0F);
00586       break;
00587
00588     case 0:
00589       /*!< Clear the corresponding segments (SEG40, SEG41, SEG42, SEG43) */
00590       LCD->RAM[LCD_RAMRegister_1] &= (uint32_t)(0xFFFFF0FF);
00591       LCD->RAM[LCD_RAMRegister_3] &= (uint32_t)(0xFFFFF0FF);
00592       LCD->RAM[LCD_RAMRegister_5] &= (uint32_t)(0xFFFFF0FF);
00593       LCD->RAM[LCD_RAMRegister_7] &= (uint32_t)(0xFFFFF0FF);
00594       break;
00595   }
00596 }
00597
00598 /**
00599   * @brief  This function Clear the whole LCD RAM.
00600   * @param  None
00601   * @retval None
00602   */
00603 void LCD_GLASS_Clear(void)
00604 {
00605   uint32_t counter = 0;
00606
00607   for (counter = 0; counter < 0x0F; counter++)
00608   {
00609     LCD->RAM[counter] =  (uint32_t)0x00;
00610   }
00611 }
00612
00613 /**
00614   * @brief  Converts an ascii char to an LCD digit.
00615   * @param  c: Char to display.
00616   * @param  point: A point to add in front of char.
00617   *          This parameter  can be one of the following values:
00618   *              @arg POINT_OFF : No point to add in front of char.
00619   *              @arg POINT_ON : Add a point in front of char.
00620   * @param  apostrophe: Flag indicating if a apostrophe has to be add in front
00621   *                     of displayed character.
00622   *          This parameter  can be one of the following values:
00623   *              @arg APOSTROPHE_OFF : No apostrophe to add in back of char.
00624   *              @arg APOSTROPHE_ON : Add an apostrophe in back of char.
00625   * @retval None
00626   */
00627 static void Convert(uint8_t* c, Point_Typedef point, Apostrophe_Typedef apostrophe)
00628 {
00629   uint16_t ch = 0, tmp = 0;
00630   uint8_t i = 0;
00631
00632   /*!< The character c is a letter in upper case*/
00633   if ((*c < 0x5B) & (*c > 0x40))
00634   {
00635     ch = LetterMap[*c - 0x41];
00636   }
00637
00638   /*!< The character c is a number*/
00639   if ((*c < 0x3A) & (*c > 0x2F))
00640   {
00641     ch = NumberMap[*c - 0x30];
00642   }
00643
00644   /*!< The character c is a space character */
00645   if (*c == 0x20)
00646   {
00647     ch =0x00;
00648   }
00649
00650   /*!< Set the DP seg in the character that can be displayed if the point is on */
00651   if (point == POINT_ON)
00652   {
00653     ch |= 0x0004;
00654   }
00655
00656   /*!< Set the X seg in the character that can be displayed if the apostrophe is on */
00657   if (apostrophe == APOSTROPHE_ON)
00658   {
00659     ch |= 0x1000;
00660   }
00661
00662   for (i = 0; i < 4; i++)
00663   {
00664     tmp = ch & mask[i];
00665     digit[i] =(uint8_t)(tmp >> shift[i]);
00666   }
00667 }
00668
00669 /**
00670   * @brief  Configures the LCD Segments and Coms GPIOs.
00671   * @param  None
00672   * @retval None
00673   */
00674 static void LCD_GPIOConfig(void)
00675 {
00676   GPIO_InitTypeDef GPIO_InitStructure;
00677
00678   /*!< Enable GPIOA, GPIOB, GPIOC, GPIOD and GPIOE AHB Clocks */
00679   RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA | RCC_AHBPeriph_GPIOB | RCC_AHBPeriph_GPIOC
00680                         | RCC_AHBPeriph_GPIOD | RCC_AHBPeriph_GPIOE, ENABLE);
00681
00682   /*!< Connect PA.08 to LCD COM0 */
00683   GPIO_PinAFConfig(GPIOA, GPIO_PinSource8, GPIO_AF_LCD);
00684
00685   /*!< Connect PA.09 to LCD COM1 */
00686   GPIO_PinAFConfig(GPIOA, GPIO_PinSource9, GPIO_AF_LCD);
00687
00688   /*!< Connect PA.10 to LCD COM2 */
00689   GPIO_PinAFConfig(GPIOA, GPIO_PinSource10, GPIO_AF_LCD);
00690
00691   /*!< Connect PB.09 to LCD COM3 */
00692   GPIO_PinAFConfig(GPIOB, GPIO_PinSource9, GPIO_AF_LCD);
00693
00694   /*!< Connect PA.01 to LCD SEG0 */
00695   GPIO_PinAFConfig(GPIOA, GPIO_PinSource1, GPIO_AF_LCD);
00696
00697   /*!< Connect PA.02 to LCD SEG1 */
00698   GPIO_PinAFConfig(GPIOA, GPIO_PinSource2, GPIO_AF_LCD);
00699
00700   /*!< Connect PA.03 to LCD SEG2 */
00701   GPIO_PinAFConfig(GPIOA, GPIO_PinSource3, GPIO_AF_LCD);
00702
00703   /*!< Connect PA.06 to LCD SEG3 */
00704   GPIO_PinAFConfig(GPIOA, GPIO_PinSource6, GPIO_AF_LCD);
00705
00706   /*!< Connect PA.07 to LCD SEG4 */
00707   GPIO_PinAFConfig(GPIOA, GPIO_PinSource7, GPIO_AF_LCD);
00708
00709   /*!< Connect PB.00 to LCD SEG5 */
00710   GPIO_PinAFConfig(GPIOB, GPIO_PinSource0, GPIO_AF_LCD);
00711
00712   /*!< Connect PB.01 to LCD SEG6 */
00713   GPIO_PinAFConfig(GPIOB, GPIO_PinSource1, GPIO_AF_LCD);
00714
00715   /*!< Connect PB.10 to LCD SEG10 */
00716   GPIO_PinAFConfig(GPIOB, GPIO_PinSource10, GPIO_AF_LCD);
00717
00718   /*!< Connect PB.11 to LCD SEG11 */
00719   GPIO_PinAFConfig(GPIOB, GPIO_PinSource11, GPIO_AF_LCD);
00720
00721   /*!< Connect PB.08 to LCD SEG16 */
00722   GPIO_PinAFConfig(GPIOB, GPIO_PinSource8, GPIO_AF_LCD);
00723
00724   /*!< Connect PC.00 to LCD SEG18 */
00725   GPIO_PinAFConfig(GPIOC, GPIO_PinSource0, GPIO_AF_LCD);
00726
00727   /*!< Connect PC.01 to LCD SEG19 */
00728   GPIO_PinAFConfig(GPIOC, GPIO_PinSource1, GPIO_AF_LCD);
00729
00730   /*!< Connect PC.02 to LCD SEG20 */
00731   GPIO_PinAFConfig(GPIOC, GPIO_PinSource2, GPIO_AF_LCD);
00732
00733   /*!< Connect PC.03 to LCD SEG21 */
00734   GPIO_PinAFConfig(GPIOC, GPIO_PinSource3, GPIO_AF_LCD);
00735
00736   /*!< Connect PC.04 to LCD SEG22 */
00737   GPIO_PinAFConfig(GPIOC, GPIO_PinSource4, GPIO_AF_LCD);
00738
00739   /*!< Connect PC.05 to LCD SEG23 */
00740   GPIO_PinAFConfig(GPIOC, GPIO_PinSource5, GPIO_AF_LCD);
00741
00742   /*!< Connect PD.08 to LCD SEG28 */
00743   GPIO_PinAFConfig(GPIOD, GPIO_PinSource8, GPIO_AF_LCD);
00744
00745   /*!< Connect PD.09 to LCD SEG29 */
00746   GPIO_PinAFConfig(GPIOD, GPIO_PinSource9, GPIO_AF_LCD);
00747
00748   /*!< Connect PD.10 to LCD SEG30 */
00749   GPIO_PinAFConfig(GPIOD, GPIO_PinSource10, GPIO_AF_LCD);
00750
00751   /*!< Connect PD.11 to LCD SEG31 */
00752   GPIO_PinAFConfig(GPIOD, GPIO_PinSource11, GPIO_AF_LCD);
00753
00754   /*!< Connect PD.12 to LCD SEG32 */
00755   GPIO_PinAFConfig(GPIOD, GPIO_PinSource12, GPIO_AF_LCD);
00756
00757   /*!< Connect PD.13 to LCD SEG33 */
00758   GPIO_PinAFConfig(GPIOD, GPIO_PinSource13, GPIO_AF_LCD);
00759
00760   /*!< Connect PD.14 to LCD SEG34 */
00761   GPIO_PinAFConfig(GPIOD, GPIO_PinSource14, GPIO_AF_LCD);
00762
00763   /*!< Connect PD.15 to LCD SEG35 */
00764   GPIO_PinAFConfig(GPIOD, GPIO_PinSource15, GPIO_AF_LCD);
00765
00766   /*!< Connect PE.00 to LCD SEG36 */
00767   GPIO_PinAFConfig(GPIOE, GPIO_PinSource0, GPIO_AF_LCD);
00768
00769   /*!< Connect PE.01 to LCD SEG37 */
00770   GPIO_PinAFConfig(GPIOE, GPIO_PinSource1, GPIO_AF_LCD);
00771
00772   /*!< Connect PE.02 to LCD SEG38 */
00773   GPIO_PinAFConfig(GPIOE, GPIO_PinSource2, GPIO_AF_LCD);
00774
00775   /*!< Connect PE.03 to LCD SEG39 */
00776   GPIO_PinAFConfig(GPIOE, GPIO_PinSource3, GPIO_AF_LCD);
00777
00778   /*!< Connect PC.10 to LCD SEG40 */
00779   GPIO_PinAFConfig(GPIOC, GPIO_PinSource10, GPIO_AF_LCD);
00780
00781   /*!< Connect PC.11 to LCD SEG41 */
00782   GPIO_PinAFConfig(GPIOC, GPIO_PinSource11, GPIO_AF_LCD);
00783
00784   /*!< Connect PC.12 to LCD SEG42 */
00785   GPIO_PinAFConfig(GPIOC, GPIO_PinSource12, GPIO_AF_LCD);
00786
00787   /*!< Connect PD.02 to LCD SEG43 */
00788   GPIO_PinAFConfig(GPIOD, GPIO_PinSource2, GPIO_AF_LCD);
00789
00790   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_6 | \
00791                                 GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10;
00792   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_40MHz;
00793   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
00794   GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
00795   GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
00796   GPIO_Init(GPIOA, &GPIO_InitStructure);
00797
00798   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_8 | GPIO_Pin_9 | \
00799                                 GPIO_Pin_10 | GPIO_Pin_11;
00800   GPIO_Init(GPIOB, &GPIO_InitStructure);
00801
00802   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | \
00803                                 GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_10 | GPIO_Pin_11 | \
00804                                 GPIO_Pin_12;
00805   GPIO_Init(GPIOC, &GPIO_InitStructure);
00806
00807   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | \
00808                                 GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | \
00809                                 GPIO_Pin_15;
00810   GPIO_Init(GPIOD, &GPIO_InitStructure);
00811
00812   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3;
00813   GPIO_Init(GPIOE, &GPIO_InitStructure);
00814 }
00815
00816 /**
00817   * @brief  Inserts a delay time.
00818   * @param  nCount: specifies the delay time length.
00819   * @retval None
00820   */
00821 static void delay(__IO uint32_t nCount)
00822 {
00823   __IO uint32_t index = 0;
00824   for(index = (0xFF * nCount); index != 0; index--)
00825   {
00826   }
00827 }
00828
00829 /**
00830   * @}
00831   */
00832
00833
00834 /**
00835   * @}
00836   */
00837
00838 /**
00839   * @}
00840   */
00841
00842 /**
00843   * @}
00844   */
00845
00846
00847 /**
00848   * @}
00849   */
00850
00851 /**
00852   * @}
00853   */
00854
00855 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32l152_eval_glass_lcd.h Source File

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • STM32L152_EVAL

stm32l152_eval_glass_lcd.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32l152_eval_glass_lcd.h
00004   * @author  MCD Application Team
00005   * @version V4.5.0
00006   * @date    07-March-2011
00007   * @brief   Header file for stm32l152_eval_glass_lcd.c module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM32L152_EVAL_GLASS_LCD_H
00024 #define __STM32L152_EVAL_GLASS_LCD_H
00025
00026 #ifdef __cplusplus
00027  extern "C" {
00028 #endif
00029
00030 /* Includes ------------------------------------------------------------------*/
00031 #include "stm32l1xx.h"
00032
00033 /** @addtogroup Utilities
00034   * @{
00035   */
00036
00037 /** @addtogroup STM32_EVAL
00038   * @{
00039   */
00040
00041 /** @addtogroup STM32L152_EVAL
00042   * @{
00043   */
00044
00045 /** @addtogroup STM32L152_EVAL_GLASS_LCD
00046   * @{
00047   */
00048
00049
00050 /** @defgroup STM32L152_EVAL_GLASS_LCD_Exported_Types
00051   * @{
00052   */
00053 typedef enum
00054 {
00055   POINT_OFF = 0,
00056   POINT_ON = 1
00057 }Point_Typedef;
00058
00059 typedef enum
00060 {
00061   APOSTROPHE_OFF = 0,
00062   APOSTROPHE_ON = 1
00063 }Apostrophe_Typedef;
00064 /**
00065   * @}
00066   */
00067
00068 /** @defgroup STM32L152_EVAL_GLASS_LCD_Exported_Constants
00069   * @{
00070   */
00071
00072 /**
00073   * @}
00074   */
00075
00076 /** @defgroup STM32L152_EVAL_GLASS_LCD_Exported_Macros
00077   * @{
00078   */
00079 /**
00080   * @}
00081   */
00082
00083
00084 /** @defgroup STM32L152_EVAL_GLASS_LCD_Exported_Functions
00085   * @{
00086   */
00087 void LCD_GLASS_Init(void);
00088 void LCD_GLASS_DisplayChar(uint8_t* ch, Point_Typedef point, Apostrophe_Typedef apostrophe,uint8_t position);
00089 void LCD_GLASS_DisplayString(uint8_t* ptr);
00090 void LCD_GLASS_WriteChar(uint8_t* ch, Point_Typedef point, Apostrophe_Typedef apostrophe,uint8_t position);
00091 void LCD_GLASS_ClearChar(uint8_t position);
00092 void LCD_GLASS_Clear(void);
00093 void LCD_GLASS_ScrollString(uint8_t* ptr, uint16_t nScroll, uint16_t ScrollSpeed);
00094
00095 /**
00096   * @}
00097   */
00098
00099 #ifdef __cplusplus
00100 }
00101 #endif
00102
00103 #endif /* __STM32L152_EVAL_GLASS_LCD_H */
00104
00105 /**
00106   * @}
00107   */
00108
00109 /**
00110   * @}
00111   */
00112
00113 /**
00114   * @}
00115   */
00116
00117 /**
00118   * @}
00119   */
00120
00121 /**
00122   * @}
00123   */
00124
00125 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32l152_eval_i2c_ee.c Source File

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  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • STM32L152_EVAL

stm32l152_eval_i2c_ee.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32l152_eval_i2c_ee.c
00004   * @author  MCD Application Team
00005   * @version V4.5.0
00006   * @date    07-March-2011
00007   * @brief   This file provides a set of functions needed to manage an I2C M24CXX
00008   *          EEPROM memory.
00009   *
00010   *          ===================================================================
00011   *          Notes:
00012   *           - This driver is intended for STM32L1xx families devices only.
00013   *           - There is no I2C EEPROM memory available in STM32L152-EVAL board,
00014   *             to use this driver you have to build your own hardware.
00015   *          ===================================================================
00016   *
00017   *          It implements a high level communication layer for read and write
00018   *          from/to this memory. The needed STM32 hardware resources (I2C and
00019   *          GPIO) are defined in stm32l152_eval.h file, and the initialization is
00020   *          performed in sEE_LowLevel_Init() function declared in stm32l152_eval.c
00021   *          file.
00022   *          You can easily tailor this driver to any other development board,
00023   *          by just adapting the defines for hardware resources and
00024   *          sEE_LowLevel_Init() function.
00025   *
00026   *          @note In this driver, basic read and write functions (sEE_ReadBuffer()
00027   *                and sEE_WritePage()) use the DMA to perform the data transfer
00028   *                to/from EEPROM memory (except when number of requested data is
00029   *                equal to 1). Thus, after calling these two functions, user
00030   *                application may perform other tasks while DMA is transferring
00031   *                data. The application should then monitor the variable holding
00032   *                the number of data in order to determine when the transfer is
00033   *                completed (variable decremented to 0). Stopping transfer tasks
00034   *                are performed into DMA interrupt handlers (which are integrated
00035   *                into this driver).
00036   *
00037   *     +-----------------------------------------------------------------+
00038   *     |                        Pin assignment                           |
00039   *     +---------------------------------------+-----------+-------------+
00040   *     |  STM32 I2C Pins                       |   sEE     |   Pin       |
00041   *     +---------------------------------------+-----------+-------------+
00042   *     | .                                     |   E0(GND) |    1  (0V)  |
00043   *     | .                                     |   E1(GND) |    2  (0V)  |
00044   *     | .                                     |   E2(GND) |    3  (0V)  |
00045   *     | .                                     |   E0(VSS) |    4  (0V)  |
00046   *     | sEE_I2C_SDA_PIN/ SDA                  |   SDA     |    5        |
00047   *     | sEE_I2C_SCL_PIN/ SCL                  |   SCL     |    6        |
00048   *     | .                                     |   /WC(VDD)|    7 (3.3V) |
00049   *     | .                                     |   VDD     |    8 (3.3V) |
00050   *     +---------------------------------------+-----------+-------------+
00051   ******************************************************************************
00052   * @attention
00053   *
00054   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00055   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00056   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00057   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00058   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00059   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00060   *
00061   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00062   ******************************************************************************
00063   */
00064
00065 /* Includes ------------------------------------------------------------------*/
00066 #include "stm32l152_eval_i2c_ee.h"
00067
00068 /** @addtogroup Utilities
00069   * @{
00070   */
00071
00072 /** @addtogroup STM32_EVAL
00073   * @{
00074   */
00075
00076 /** @addtogroup STM32L152_EVAL
00077   * @{
00078   */
00079
00080 /** @addtogroup STM32L152_EVAL_I2C_EE
00081   * @brief      This file includes the I2C EEPROM driver of STM32L152-EVAL board.
00082   * @{
00083   */
00084
00085 /** @defgroup STM32L152_EVAL_I2C_EE_Private_Types
00086   * @{
00087   */
00088 /**
00089   * @}
00090   */
00091
00092
00093 /** @defgroup STM32L152_EVAL_I2C_EE_Private_Defines
00094   * @{
00095   */
00096 /**
00097   * @}
00098   */
00099
00100
00101 /** @defgroup STM32L152_EVAL_I2C_EE_Private_Macros
00102   * @{
00103   */
00104 /**
00105   * @}
00106   */
00107
00108
00109 /** @defgroup STM32L152_EVAL_I2C_EE_Private_Variables
00110   * @{
00111   */
00112 __IO uint16_t  sEEAddress = 0;
00113 __IO uint32_t  sEETimeout = sEE_LONG_TIMEOUT;
00114 __IO uint16_t* sEEDataReadPointer;
00115 __IO uint8_t*  sEEDataWritePointer;
00116 __IO uint8_t   sEEDataNum;
00117 /**
00118   * @}
00119   */
00120
00121
00122 /** @defgroup STM32L152_EVAL_I2C_EE_Private_Function_Prototypes
00123   * @{
00124   */
00125 /**
00126   * @}
00127   */
00128
00129
00130 /** @defgroup STM32L152_EVAL_I2C_EE_Private_Functions
00131   * @{
00132   */
00133
00134 /**
00135   * @brief  DeInitializes peripherals used by the I2C EEPROM driver.
00136   * @param  None
00137   * @retval None
00138   */
00139 void sEE_DeInit(void)
00140 {
00141   sEE_LowLevel_DeInit();
00142 }
00143
00144 /**
00145   * @brief  Initializes peripherals used by the I2C EEPROM driver.
00146   * @param  None
00147   * @retval None
00148   */
00149 void sEE_Init(void)
00150 {
00151   I2C_InitTypeDef  I2C_InitStructure;
00152
00153   sEE_LowLevel_Init();
00154
00155   /*!< I2C configuration */
00156   /* sEE_I2C configuration */
00157   I2C_InitStructure.I2C_Mode = I2C_Mode_I2C;
00158   I2C_InitStructure.I2C_DutyCycle = I2C_DutyCycle_2;
00159   I2C_InitStructure.I2C_OwnAddress1 = I2C_SLAVE_ADDRESS7;
00160   I2C_InitStructure.I2C_Ack = I2C_Ack_Enable;
00161   I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
00162   I2C_InitStructure.I2C_ClockSpeed = I2C_SPEED;
00163
00164   /* sEE_I2C Peripheral Enable */
00165   I2C_Cmd(sEE_I2C, ENABLE);
00166   /* Apply sEE_I2C configuration after enabling it */
00167   I2C_Init(sEE_I2C, &I2C_InitStructure);
00168
00169   /* Enable the sEE_I2C peripheral DMA requests */
00170   I2C_DMACmd(sEE_I2C, ENABLE);
00171
00172 #if defined (sEE_M24C64_32)
00173   /*!< Select the EEPROM address according to the state of E0, E1, E2 pins */
00174   sEEAddress = sEE_HW_ADDRESS;
00175 #elif defined (sEE_M24C08)
00176   /*!< depending on the sEE Address selected in the i2c_ee.h file */
00177  #ifdef sEE_Block0_ADDRESS
00178   /*!< Select the sEE Block0 to write on */
00179   sEEAddress = sEE_Block0_ADDRESS;
00180  #endif
00181
00182  #ifdef sEE_Block1_ADDRESS
00183   /*!< Select the sEE Block1 to write on */
00184   sEEAddress = sEE_Block1_ADDRESS;
00185  #endif
00186
00187  #ifdef sEE_Block2_ADDRESS
00188   /*!< Select the sEE Block2 to write on */
00189   sEEAddress = sEE_Block2_ADDRESS;
00190  #endif
00191
00192  #ifdef sEE_Block3_ADDRESS
00193   /*!< Select the sEE Block3 to write on */
00194   sEEAddress = sEE_Block3_ADDRESS;
00195  #endif
00196 #endif /*!< sEE_M24C64_32 */
00197 }
00198
00199 /**
00200   * @brief  Reads a block of data from the EEPROM.
00201   * @param  pBuffer : pointer to the buffer that receives the data read from
00202   *         the EEPROM.
00203   * @param  ReadAddr : EEPROM's internal address to start reading from.
00204   * @param  NumByteToRead : pointer to the variable holding number of bytes to
00205   *         be read from the EEPROM.
00206   *
00207   *        @note The variable pointed by NumByteToRead is reset to 0 when all the
00208   *              data are read from the EEPROM. Application should monitor this
00209   *              variable in order know when the transfer is complete.
00210   *
00211   * @note When number of data to be read is higher than 1, this function just
00212   *       configures the communication and enable the DMA channel to transfer data.
00213   *       Meanwhile, the user application may perform other tasks.
00214   *       When number of data to be read is 1, then the DMA is not used. The byte
00215   *       is read in polling mode.
00216   *
00217   * @retval sEE_OK (0) if operation is correctly performed, else return value
00218   *         different from sEE_OK (0) or the timeout user callback.
00219   */
00220 uint32_t sEE_ReadBuffer(uint8_t* pBuffer, uint16_t ReadAddr, uint16_t* NumByteToRead)
00221 {
00222   /* Set the pointer to the Number of data to be read. This pointer will be used
00223       by the DMA Transfer Completer interrupt Handler in order to reset the
00224       variable to 0. User should check on this variable in order to know if the
00225       DMA transfer has been complete or not. */
00226   sEEDataReadPointer = NumByteToRead;
00227
00228   /*!< While the bus is busy */
00229   sEETimeout = sEE_LONG_TIMEOUT;
00230   while(I2C_GetFlagStatus(sEE_I2C, I2C_FLAG_BUSY))
00231   {
00232     if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
00233   }
00234
00235   /*!< Send START condition */
00236   I2C_GenerateSTART(sEE_I2C, ENABLE);
00237
00238   /*!< Test on EV5 and clear it (cleared by reading SR1 then writing to DR) */
00239   sEETimeout = sEE_FLAG_TIMEOUT;
00240   while(!I2C_CheckEvent(sEE_I2C, I2C_EVENT_MASTER_MODE_SELECT))
00241   {
00242     if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
00243   }
00244
00245   /*!< Send EEPROM address for write */
00246   I2C_Send7bitAddress(sEE_I2C, sEEAddress, I2C_Direction_Transmitter);
00247
00248   /*!< Test on EV6 and clear it */
00249   sEETimeout = sEE_FLAG_TIMEOUT;
00250   while(!I2C_CheckEvent(sEE_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED))
00251   {
00252     if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
00253   }
00254
00255 #ifdef sEE_M24C08
00256
00257   /*!< Send the EEPROM's internal address to read from: Only one byte address */
00258   I2C_SendData(sEE_I2C, ReadAddr);
00259
00260 #elif defined (sEE_M24C64_32)
00261
00262   /*!< Send the EEPROM's internal address to read from: MSB of the address first */
00263   I2C_SendData(sEE_I2C, (uint8_t)((ReadAddr & 0xFF00) >> 8));
00264
00265   /*!< Test on EV8 and clear it */
00266   sEETimeout = sEE_FLAG_TIMEOUT;
00267   while(!I2C_CheckEvent(sEE_I2C, I2C_EVENT_MASTER_BYTE_TRANSMITTING))
00268   {
00269     if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
00270   }
00271
00272   /*!< Send the EEPROM's internal address to read from: LSB of the address */
00273   I2C_SendData(sEE_I2C, (uint8_t)(ReadAddr & 0x00FF));
00274
00275 #endif /*!< sEE_M24C08 */
00276
00277   /*!< Test on EV8 and clear it */
00278   sEETimeout = sEE_FLAG_TIMEOUT;
00279   while(I2C_GetFlagStatus(sEE_I2C, I2C_FLAG_BTF) == RESET)
00280   {
00281     if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
00282   }
00283
00284   /*!< Send STRAT condition a second time */
00285   I2C_GenerateSTART(sEE_I2C, ENABLE);
00286
00287   /*!< Test on EV5 and clear it (cleared by reading SR1 then writing to DR) */
00288   sEETimeout = sEE_FLAG_TIMEOUT;
00289   while(!I2C_CheckEvent(sEE_I2C, I2C_EVENT_MASTER_MODE_SELECT))
00290   {
00291     if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
00292   }
00293
00294   /*!< Send EEPROM address for read */
00295   I2C_Send7bitAddress(sEE_I2C, sEEAddress, I2C_Direction_Receiver);
00296
00297   /* If number of data to be read is 1, then DMA couldn't be used */
00298   /* One Byte Master Reception procedure (POLLING) ---------------------------*/
00299   if ((uint16_t)(*NumByteToRead) < 2)
00300   {
00301     /* Wait on ADDR flag to be set (ADDR is still not cleared at this level */
00302     sEETimeout = sEE_FLAG_TIMEOUT;
00303     while(I2C_GetFlagStatus(sEE_I2C, I2C_FLAG_ADDR) == RESET)
00304     {
00305       if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
00306     }
00307
00308     /*!< Disable Acknowledgement */
00309     I2C_AcknowledgeConfig(sEE_I2C, DISABLE);
00310
00311     /* Clear ADDR register by reading SR1 then SR2 register (SR1 has already been read) */
00312     (void)sEE_I2C->SR2;
00313
00314     /*!< Send STOP Condition */
00315     I2C_GenerateSTOP(sEE_I2C, ENABLE);
00316
00317     /* Wait for the byte to be received */
00318     sEETimeout = sEE_FLAG_TIMEOUT;
00319     while(I2C_GetFlagStatus(sEE_I2C, I2C_FLAG_RXNE) == RESET)
00320     {
00321       if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
00322     }
00323
00324     /*!< Read the byte received from the EEPROM */
00325     *pBuffer = I2C_ReceiveData(sEE_I2C);
00326
00327     /*!< Decrement the read bytes counter */
00328     (uint16_t)(*NumByteToRead)--;
00329
00330     /* Wait to make sure that STOP control bit has been cleared */
00331     sEETimeout = sEE_FLAG_TIMEOUT;
00332     while(sEE_I2C->CR1 & I2C_CR1_STOP)
00333     {
00334       if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
00335     }
00336
00337     /*!< Re-Enable Acknowledgement to be ready for another reception */
00338     I2C_AcknowledgeConfig(sEE_I2C, ENABLE);
00339   }
00340   else/* More than one Byte Master Reception procedure (DMA) -----------------*/
00341   {
00342     /*!< Test on EV6 and clear it */
00343     sEETimeout = sEE_FLAG_TIMEOUT;
00344     while(!I2C_CheckEvent(sEE_I2C, I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED))
00345     {
00346       if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
00347     }
00348
00349     /* Configure the DMA Rx Channel with the buffer address and the buffer size */
00350     sEE_LowLevel_DMAConfig((uint32_t)pBuffer, (uint16_t)(*NumByteToRead), sEE_DIRECTION_RX);
00351
00352     /* Inform the DMA that the next End Of Transfer Signal will be the last one */
00353     I2C_DMALastTransferCmd(sEE_I2C, ENABLE);
00354
00355     /* Enable the DMA Rx Channel */
00356     DMA_Cmd(sEE_I2C_DMA_CHANNEL_RX, ENABLE);
00357   }
00358
00359   /* If all operations OK, return sEE_OK (0) */
00360   return sEE_OK;
00361 }
00362
00363 /**
00364   * @brief  Writes more than one byte to the EEPROM with a single WRITE cycle.
00365   *
00366   * @note   The number of bytes (combined to write start address) must not
00367   *         cross the EEPROM page boundary. This function can only write into
00368   *         the boundaries of an EEPROM page.
00369   *         This function doesn't check on boundaries condition (in this driver
00370   *         the function sEE_WriteBuffer() which calls sEE_WritePage() is
00371   *         responsible of checking on Page boundaries).
00372   *
00373   * @param  pBuffer : pointer to the buffer containing the data to be written to
00374   *         the EEPROM.
00375   * @param  WriteAddr : EEPROM's internal address to write to.
00376   * @param  NumByteToWrite : pointer to the variable holding number of bytes to
00377   *         be written into the EEPROM.
00378   *
00379   *        @note The variable pointed by NumByteToWrite is reset to 0 when all the
00380   *              data are written to the EEPROM. Application should monitor this
00381   *              variable in order know when the transfer is complete.
00382   *
00383   * @note This function just configure the communication and enable the DMA
00384   *       channel to transfer data. Meanwhile, the user application may perform
00385   *       other tasks in parallel.
00386   *
00387   * @retval sEE_OK (0) if operation is correctly performed, else return value
00388   *         different from sEE_OK (0) or the timeout user callback.
00389   */
00390 uint32_t sEE_WritePage(uint8_t* pBuffer, uint16_t WriteAddr, uint8_t* NumByteToWrite)
00391 {
00392   /* Set the pointer to the Number of data to be written. This pointer will be used
00393       by the DMA Transfer Completer interrupt Handler in order to reset the
00394       variable to 0. User should check on this variable in order to know if the
00395       DMA transfer has been complete or not. */
00396   sEEDataWritePointer = NumByteToWrite;
00397
00398   /*!< While the bus is busy */
00399   sEETimeout = sEE_LONG_TIMEOUT;
00400   while(I2C_GetFlagStatus(sEE_I2C, I2C_FLAG_BUSY))
00401   {
00402     if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
00403   }
00404
00405   /*!< Send START condition */
00406   I2C_GenerateSTART(sEE_I2C, ENABLE);
00407
00408   /*!< Test on EV5 and clear it */
00409   sEETimeout = sEE_FLAG_TIMEOUT;
00410   while(!I2C_CheckEvent(sEE_I2C, I2C_EVENT_MASTER_MODE_SELECT))
00411   {
00412     if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
00413   }
00414
00415   /*!< Send EEPROM address for write */
00416   sEETimeout = sEE_FLAG_TIMEOUT;
00417   I2C_Send7bitAddress(sEE_I2C, sEEAddress, I2C_Direction_Transmitter);
00418
00419   /*!< Test on EV6 and clear it */
00420   sEETimeout = sEE_FLAG_TIMEOUT;
00421   while(!I2C_CheckEvent(sEE_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED))
00422   {
00423     if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
00424   }
00425
00426 #ifdef sEE_M24C08
00427
00428   /*!< Send the EEPROM's internal address to write to : only one byte Address */
00429   I2C_SendData(sEE_I2C, WriteAddr);
00430
00431 #elif defined(sEE_M24C64_32)
00432
00433   /*!< Send the EEPROM's internal address to write to : MSB of the address first */
00434   I2C_SendData(sEE_I2C, (uint8_t)((WriteAddr & 0xFF00) >> 8));
00435
00436   /*!< Test on EV8 and clear it */
00437   sEETimeout = sEE_FLAG_TIMEOUT;
00438   while(!I2C_CheckEvent(sEE_I2C, I2C_EVENT_MASTER_BYTE_TRANSMITTING))
00439   {
00440     if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
00441   }
00442
00443   /*!< Send the EEPROM's internal address to write to : LSB of the address */
00444   I2C_SendData(sEE_I2C, (uint8_t)(WriteAddr & 0x00FF));
00445
00446 #endif /*!< sEE_M24C08 */
00447
00448   /*!< Test on EV8 and clear it */
00449   sEETimeout = sEE_FLAG_TIMEOUT;
00450   while(!I2C_CheckEvent(sEE_I2C, I2C_EVENT_MASTER_BYTE_TRANSMITTING))
00451   {
00452     if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
00453   }
00454
00455   /* Configure the DMA Tx Channel with the buffer address and the buffer size */
00456   sEE_LowLevel_DMAConfig((uint32_t)pBuffer, (uint8_t)(*NumByteToWrite), sEE_DIRECTION_TX);
00457
00458   /* Enable the DMA Tx Channel */
00459   DMA_Cmd(sEE_I2C_DMA_CHANNEL_TX, ENABLE);
00460
00461   /* If all operations OK, return sEE_OK (0) */
00462   return sEE_OK;
00463 }
00464
00465 /**
00466   * @brief  Writes buffer of data to the I2C EEPROM.
00467   * @param  pBuffer : pointer to the buffer  containing the data to be written
00468   *         to the EEPROM.
00469   * @param  WriteAddr : EEPROM's internal address to write to.
00470   * @param  NumByteToWrite : number of bytes to write to the EEPROM.
00471   * @retval None
00472   */
00473 void sEE_WriteBuffer(uint8_t* pBuffer, uint16_t WriteAddr, uint16_t NumByteToWrite)
00474 {
00475   uint8_t NumOfPage = 0, NumOfSingle = 0, count = 0;
00476   uint16_t Addr = 0;
00477
00478   Addr = WriteAddr % sEE_PAGESIZE;
00479   count = sEE_PAGESIZE - Addr;
00480   NumOfPage =  NumByteToWrite / sEE_PAGESIZE;
00481   NumOfSingle = NumByteToWrite % sEE_PAGESIZE;
00482
00483   /*!< If WriteAddr is sEE_PAGESIZE aligned  */
00484   if(Addr == 0)
00485   {
00486     /*!< If NumByteToWrite < sEE_PAGESIZE */
00487     if(NumOfPage == 0)
00488     {
00489       /* Store the number of data to be written */
00490       sEEDataNum = NumOfSingle;
00491       /* Start writing data */
00492       sEE_WritePage(pBuffer, WriteAddr, (uint8_t*)(&sEEDataNum));
00493       /* Wait transfer through DMA to be complete */
00494       sEETimeout = sEE_LONG_TIMEOUT;
00495       while (sEEDataNum > 0)
00496       {
00497         if((sEETimeout--) == 0) {sEE_TIMEOUT_UserCallback(); return;};
00498       }
00499       sEE_WaitEepromStandbyState();
00500     }
00501     /*!< If NumByteToWrite > sEE_PAGESIZE */
00502     else
00503     {
00504       while(NumOfPage--)
00505       {
00506         /* Store the number of data to be written */
00507         sEEDataNum = sEE_PAGESIZE;
00508         sEE_WritePage(pBuffer, WriteAddr, (uint8_t*)(&sEEDataNum));
00509         /* Wait transfer through DMA to be complete */
00510         sEETimeout = sEE_LONG_TIMEOUT;
00511         while (sEEDataNum > 0)
00512         {
00513           if((sEETimeout--) == 0) {sEE_TIMEOUT_UserCallback(); return;};
00514         }
00515         sEE_WaitEepromStandbyState();
00516         WriteAddr +=  sEE_PAGESIZE;
00517         pBuffer += sEE_PAGESIZE;
00518       }
00519
00520       if(NumOfSingle!=0)
00521       {
00522         /* Store the number of data to be written */
00523         sEEDataNum = NumOfSingle;
00524         sEE_WritePage(pBuffer, WriteAddr, (uint8_t*)(&sEEDataNum));
00525         /* Wait transfer through DMA to be complete */
00526         sEETimeout = sEE_LONG_TIMEOUT;
00527         while (sEEDataNum > 0)
00528         {
00529           if((sEETimeout--) == 0) {sEE_TIMEOUT_UserCallback(); return;};
00530         }
00531         sEE_WaitEepromStandbyState();
00532       }
00533     }
00534   }
00535   /*!< If WriteAddr is not sEE_PAGESIZE aligned  */
00536   else
00537   {
00538     /*!< If NumByteToWrite < sEE_PAGESIZE */
00539     if(NumOfPage== 0)
00540     {
00541       /*!< If the number of data to be written is more than the remaining space
00542       in the current page: */
00543       if (NumByteToWrite > count)
00544       {
00545         /* Store the number of data to be written */
00546         sEEDataNum = count;
00547         /*!< Write the data conained in same page */
00548         sEE_WritePage(pBuffer, WriteAddr, (uint8_t*)(&sEEDataNum));
00549         /* Wait transfer through DMA to be complete */
00550         sEETimeout = sEE_LONG_TIMEOUT;
00551         while (sEEDataNum > 0)
00552         {
00553           if((sEETimeout--) == 0) {sEE_TIMEOUT_UserCallback(); return;};
00554         }
00555         sEE_WaitEepromStandbyState();
00556
00557         /* Store the number of data to be written */
00558         sEEDataNum = (NumByteToWrite - count);
00559         /*!< Write the remaining data in the following page */
00560         sEE_WritePage((uint8_t*)(pBuffer + count), (WriteAddr + count), (uint8_t*)(&sEEDataNum));
00561         /* Wait transfer through DMA to be complete */
00562         sEETimeout = sEE_LONG_TIMEOUT;
00563         while (sEEDataNum > 0)
00564         {
00565           if((sEETimeout--) == 0) {sEE_TIMEOUT_UserCallback(); return;};
00566         }
00567         sEE_WaitEepromStandbyState();
00568       }
00569       else
00570       {
00571         /* Store the number of data to be written */
00572         sEEDataNum = NumOfSingle;
00573         sEE_WritePage(pBuffer, WriteAddr, (uint8_t*)(&sEEDataNum));
00574         /* Wait transfer through DMA to be complete */
00575         sEETimeout = sEE_LONG_TIMEOUT;
00576         while (sEEDataNum > 0)
00577         {
00578           if((sEETimeout--) == 0) {sEE_TIMEOUT_UserCallback(); return;};
00579         }
00580         sEE_WaitEepromStandbyState();
00581       }
00582     }
00583     /*!< If NumByteToWrite > sEE_PAGESIZE */
00584     else
00585     {
00586       NumByteToWrite -= count;
00587       NumOfPage =  NumByteToWrite / sEE_PAGESIZE;
00588       NumOfSingle = NumByteToWrite % sEE_PAGESIZE;
00589
00590       if(count != 0)
00591       {
00592         /* Store the number of data to be written */
00593         sEEDataNum = count;
00594         sEE_WritePage(pBuffer, WriteAddr, (uint8_t*)(&sEEDataNum));
00595         /* Wait transfer through DMA to be complete */
00596         sEETimeout = sEE_LONG_TIMEOUT;
00597         while (sEEDataNum > 0)
00598         {
00599           if((sEETimeout--) == 0) {sEE_TIMEOUT_UserCallback(); return;};
00600         }
00601         sEE_WaitEepromStandbyState();
00602         WriteAddr += count;
00603         pBuffer += count;
00604       }
00605
00606       while(NumOfPage--)
00607       {
00608         /* Store the number of data to be written */
00609         sEEDataNum = sEE_PAGESIZE;
00610         sEE_WritePage(pBuffer, WriteAddr, (uint8_t*)(&sEEDataNum));
00611         /* Wait transfer through DMA to be complete */
00612         sEETimeout = sEE_LONG_TIMEOUT;
00613         while (sEEDataNum > 0)
00614         {
00615           if((sEETimeout--) == 0) {sEE_TIMEOUT_UserCallback(); return;};
00616         }
00617         sEE_WaitEepromStandbyState();
00618         WriteAddr +=  sEE_PAGESIZE;
00619         pBuffer += sEE_PAGESIZE;
00620       }
00621       if(NumOfSingle != 0)
00622       {
00623         /* Store the number of data to be written */
00624         sEEDataNum = NumOfSingle;
00625         sEE_WritePage(pBuffer, WriteAddr, (uint8_t*)(&sEEDataNum));
00626         /* Wait transfer through DMA to be complete */
00627         sEETimeout = sEE_LONG_TIMEOUT;
00628         while (sEEDataNum > 0)
00629         {
00630           if((sEETimeout--) == 0) {sEE_TIMEOUT_UserCallback(); return;};
00631         }
00632         sEE_WaitEepromStandbyState();
00633       }
00634     }
00635   }
00636 }
00637
00638 /**
00639   * @brief  Wait for EEPROM Standby state.
00640   *
00641   * @note  This function allows to wait and check that EEPROM has finished the
00642   *        last operation. It is mostly used after Write operation: after receiving
00643   *        the buffer to be written, the EEPROM may need additional time to actually
00644   *        perform the write operation. During this time, it doesn't answer to
00645   *        I2C packets addressed to it. Once the write operation is complete
00646   *        the EEPROM responds to its address.
00647   *
00648   * @param  None
00649   * @retval sEE_OK (0) if operation is correctly performed, else return value
00650   *         different from sEE_OK (0) or the timeout user callback.
00651   */
00652 uint32_t sEE_WaitEepromStandbyState(void)
00653 {
00654   __IO uint16_t tmpSR1 = 0;
00655   __IO uint32_t sEETrials = 0;
00656
00657   /*!< While the bus is busy */
00658   sEETimeout = sEE_LONG_TIMEOUT;
00659   while(I2C_GetFlagStatus(sEE_I2C, I2C_FLAG_BUSY))
00660   {
00661     if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
00662   }
00663
00664   /* Keep looping till the slave acknowledge his address or maximum number
00665      of trials is reached (this number is defined by sEE_MAX_TRIALS_NUMBER define
00666      in stm32_eval_i2c_ee.h file) */
00667   while (1)
00668   {
00669     /*!< Send START condition */
00670     I2C_GenerateSTART(sEE_I2C, ENABLE);
00671
00672     /*!< Test on EV5 and clear it */
00673     sEETimeout = sEE_FLAG_TIMEOUT;
00674     while(!I2C_CheckEvent(sEE_I2C, I2C_EVENT_MASTER_MODE_SELECT))
00675     {
00676       if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
00677     }
00678
00679     /*!< Send EEPROM address for write */
00680     I2C_Send7bitAddress(sEE_I2C, sEEAddress, I2C_Direction_Transmitter);
00681
00682     /* Wait for ADDR flag to be set (Slave acknowledged his address) */
00683     sEETimeout = sEE_LONG_TIMEOUT;
00684     do
00685     {
00686       /* Get the current value of the SR1 register */
00687       tmpSR1 = sEE_I2C->SR1;
00688
00689       /* Update the timeout value and exit if it reach 0 */
00690       if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
00691     }
00692     /* Keep looping till the Address is acknowledged or the AF flag is
00693        set (address not acknowledged at time) */
00694     while((tmpSR1 & (I2C_SR1_ADDR | I2C_SR1_AF)) == 0);
00695
00696     /* Check if the ADDR flag has been set */
00697     if (tmpSR1 & I2C_SR1_ADDR)
00698     {
00699       /* Clear ADDR Flag by reading SR1 then SR2 registers (SR1 have already
00700          been read) */
00701       (void)sEE_I2C->SR2;
00702
00703       /*!< STOP condition */
00704       I2C_GenerateSTOP(sEE_I2C, ENABLE);
00705
00706       /* Exit the function */
00707       return sEE_OK;
00708     }
00709     else
00710     {
00711       /*!< Clear AF flag */
00712       I2C_ClearFlag(sEE_I2C, I2C_FLAG_AF);
00713     }
00714
00715     /* Check if the maximum allowed numbe of trials has bee reached */
00716     if (sEETrials++ == sEE_MAX_TRIALS_NUMBER)
00717     {
00718       /* If the maximum number of trials has been reached, exit the function */
00719       return sEE_TIMEOUT_UserCallback();
00720     }
00721   }
00722 }
00723
00724 /**
00725   * @brief  This function handles the DMA Tx Channel interrupt Handler.
00726   * @param  None
00727   * @retval None
00728   */
00729 void sEE_I2C_DMA_TX_IRQHandler(void)
00730 {
00731   /* Check if the DMA transfer is complete */
00732   if(DMA_GetFlagStatus(sEE_I2C_DMA_FLAG_TX_TC) != RESET)
00733   {
00734     /* Disable the DMA Tx Channel and Clear all its Flags */
00735     DMA_Cmd(sEE_I2C_DMA_CHANNEL_TX, DISABLE);
00736     DMA_ClearFlag(sEE_I2C_DMA_FLAG_TX_GL);
00737
00738     /*!< Wait till all data have been physically transferred on the bus */
00739     sEETimeout = sEE_LONG_TIMEOUT;
00740     while(!I2C_GetFlagStatus(sEE_I2C, I2C_FLAG_BTF))
00741     {
00742       if((sEETimeout--) == 0) sEE_TIMEOUT_UserCallback();
00743     }
00744
00745     /*!< Send STOP condition */
00746     I2C_GenerateSTOP(sEE_I2C, ENABLE);
00747
00748     /* Reset the variable holding the number of data to be written */
00749     *sEEDataWritePointer = 0;
00750   }
00751 }
00752
00753 /**
00754   * @brief  This function handles the DMA Rx Channel interrupt Handler.
00755   * @param  None
00756   * @retval None
00757   */
00758 void sEE_I2C_DMA_RX_IRQHandler(void)
00759 {
00760   /* Check if the DMA transfer is complete */
00761   if(DMA_GetFlagStatus(sEE_I2C_DMA_FLAG_RX_TC) != RESET)
00762   {
00763     /*!< Send STOP Condition */
00764     I2C_GenerateSTOP(sEE_I2C, ENABLE);
00765
00766     /* Disable the DMA Rx Channel and Clear all its Flags */
00767     DMA_Cmd(sEE_I2C_DMA_CHANNEL_RX, DISABLE);
00768     DMA_ClearFlag(sEE_I2C_DMA_FLAG_RX_GL);
00769
00770     /* Reset the variable holding the number of data to be read */
00771     *sEEDataReadPointer = 0;
00772   }
00773 }
00774
00775 #ifdef USE_DEFAULT_TIMEOUT_CALLBACK
00776 /**
00777   * @brief  Basic management of the timeout situation.
00778   * @param  None.
00779   * @retval None.
00780   */
00781 uint32_t sEE_TIMEOUT_UserCallback(void)
00782 {
00783   /* Block communication and all processes */
00784   while (1)
00785   {
00786   }
00787 }
00788 #endif /* USE_DEFAULT_TIMEOUT_CALLBACK */
00789
00790 /**
00791   * @}
00792   */
00793
00794 /**
00795   * @}
00796   */
00797
00798 /**
00799   * @}
00800   */
00801
00802 /**
00803   * @}
00804   */
00805
00806 /**
00807   * @}
00808   */
00809
00810 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32l152_eval_i2c_ee.h Source File

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • STM32L152_EVAL

stm32l152_eval_i2c_ee.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32l152_eval_i2c_ee.h
00004   * @author  MCD Application Team
00005   * @version V4.5.0
00006   * @date    07-March-2011
00007   * @brief   This file contains all the functions prototypes for the stm32l152_eval_i2c_ee
00008   *          firmware driver.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00013   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00014   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00015   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00016   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00017   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00018   *
00019   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00020   ******************************************************************************
00021   */
00022
00023 /* Define to prevent recursive inclusion -------------------------------------*/
00024 #ifndef __STM32L152_EVAL_I2C_EE_H
00025 #define __STM32L152_EVAL_I2C_EE_H
00026
00027 #ifdef __cplusplus
00028  extern "C" {
00029 #endif
00030
00031 /* Includes ------------------------------------------------------------------*/
00032 #include "stm32_eval.h"
00033
00034 /** @addtogroup Utilities
00035   * @{
00036   */
00037
00038 /** @addtogroup STM32_EVAL
00039   * @{
00040   */
00041
00042 /** @addtogroup STM32L152_EVAL
00043   * @{
00044   */
00045
00046 /** @addtogroup STM32L152_EVAL_I2C_EE
00047   * @{
00048   */
00049
00050 /** @defgroup STM32L152_EVAL_I2C_EE_Exported_Types
00051   * @{
00052   */
00053
00054 /**
00055   * @}
00056   */
00057
00058 /** @defgroup STM32L152_EVAL_I2C_EE_Exported_Constants
00059   * @{
00060   */
00061
00062 /* Uncomment the following line to use the default sEE_TIMEOUT_UserCallback()
00063    function implemented in stm32_evel_i2c_ee.c file.
00064    sEE_TIMEOUT_UserCallback() function is called whenever a timeout condition
00065    occure during communication (waiting on an event that doesn't occur, bus
00066    errors, busy devices ...). */
00067 /* #define USE_DEFAULT_TIMEOUT_CALLBACK */
00068
00069 #if !defined (sEE_M24C08) && !defined (sEE_M24C64_32)
00070 /* Use the defines below the choose the EEPROM type */
00071 /* #define sEE_M24C08*/  /* Support the device: M24C08. */
00072 /* note: Could support: M24C01, M24C02, M24C04 and M24C16 if the blocks and
00073    HW address are correctly defined*/
00074 #define sEE_M24C64_32  /* Support the devices: M24C32 and M24C64 */
00075 #endif
00076
00077 #ifdef sEE_M24C64_32
00078 /* For M24C32 and M24C64 devices, E0,E1 and E2 pins are all used for device
00079   address selection (ne need for additional address lines). According to the
00080   Harware connection on the board (on STM3210C-EVAL board E0 = E1 = E2 = 0) */
00081
00082  #define sEE_HW_ADDRESS         0xA0   /* E0 = E1 = E2 = 0 */
00083
00084 #elif defined (sEE_M24C08)
00085 /* The M24C08W contains 4 blocks (128byte each) with the adresses below: E2 = 0
00086    EEPROM Addresses defines */
00087  #define sEE_Block0_ADDRESS     0xA0   /* E2 = 0 */
00088  /*#define sEE_Block1_ADDRESS     0xA2*/ /* E2 = 0 */
00089  /*#define sEE_Block2_ADDRESS     0xA4*/ /* E2 = 0 */
00090  /*#define sEE_Block3_ADDRESS     0xA6*/ /* E2 = 0 */
00091
00092 #endif /* sEE_M24C64_32 */
00093
00094 #define I2C_SPEED               200000
00095 #define I2C_SLAVE_ADDRESS7      0xA0
00096
00097 #if defined (sEE_M24C08)
00098  #define sEE_PAGESIZE           16
00099 #elif defined (sEE_M24C64_32)
00100  #define sEE_PAGESIZE           32
00101 #endif
00102
00103 /* Maximum Timeout values for flags and events waiting loops. These timeouts are
00104    not based on accurate values, they just guarantee that the application will
00105    not remain stuck if the I2C communication is corrupted.
00106    You may modify these timeout values depending on CPU frequency and application
00107    conditions (interrupts routines ...). */
00108 #define sEE_FLAG_TIMEOUT         ((uint32_t)0x1000)
00109 #define sEE_LONG_TIMEOUT         ((uint32_t)(10 * sEE_FLAG_TIMEOUT))
00110
00111 /* Maximum number of trials for sEE_WaitEepromStandbyState() function */
00112 #define sEE_MAX_TRIALS_NUMBER     300
00113
00114 /* Defintions for the state of the DMA transfer */
00115 #define sEE_STATE_READY           0
00116 #define sEE_STATE_BUSY            1
00117 #define sEE_STATE_ERROR           2
00118
00119 #define sEE_OK                    0
00120 #define sEE_FAIL                  1
00121
00122 /**
00123   * @}
00124   */
00125
00126 /** @defgroup STM32L152_EVAL_I2C_EE_Exported_Macros
00127   * @{
00128   */
00129 /**
00130   * @}
00131   */
00132
00133 /** @defgroup STM32L152_EVAL_I2C_EE_Exported_Functions
00134   * @{
00135   */
00136 void     sEE_DeInit(void);
00137 void     sEE_Init(void);
00138 uint32_t sEE_ReadBuffer(uint8_t* pBuffer, uint16_t ReadAddr, uint16_t* NumByteToRead);
00139 uint32_t sEE_WritePage(uint8_t* pBuffer, uint16_t WriteAddr, uint8_t* NumByteToWrite);
00140 void     sEE_WriteBuffer(uint8_t* pBuffer, uint16_t WriteAddr, uint16_t NumByteToWrite);
00141 uint32_t sEE_WaitEepromStandbyState(void);
00142
00143 /* USER Callbacks: These are functions for which prototypes only are declared in
00144    EEPROM driver and that should be implemented into user applicaiton. */
00145 /* sEE_TIMEOUT_UserCallback() function is called whenever a timeout condition
00146    occure during communication (waiting on an event that doesn't occur, bus
00147    errors, busy devices ...).
00148    You can use the default timeout callback implementation by uncommenting the
00149    define USE_DEFAULT_TIMEOUT_CALLBACK in stm32_evel_i2c_ee.h file.
00150    Typically the user implementation of this callback should reset I2C peripheral
00151    and re-initialize communication or in worst case reset all the application. */
00152 uint32_t sEE_TIMEOUT_UserCallback(void);
00153
00154 #ifdef __cplusplus
00155 }
00156 #endif
00157
00158 #endif /* __STM32L152_EVAL_I2C_EE_H */
00159 /**
00160   * @}
00161   */
00162
00163 /**
00164   * @}
00165   */
00166
00167 /**
00168   * @}
00169   */
00170
00171 /**
00172   * @}
00173   */
00174
00175 /**
00176   * @}
00177   */
00178
00179 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
00180
00181


STM32F10x Standard Peripherals Firmware Library: stm32l152_eval_lcd.c Source File

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • STM32L152_EVAL

stm32l152_eval_lcd.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32l152_eval_lcd.c
00004   * @author  MCD Application Team
00005   * @version V4.5.0
00006   * @date    07-March-2011
00007   * @brief   This file includes the LCD driver for AM-240320L8TNQW00H (LCD_ILI9320),
00008   *          AM-240320LDTNQW00H (LCD_SPFD5408B) Liquid Crystal Display Module
00009   *          of STM32L152-EVAL board RevB.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32l152_eval_lcd.h"
00026 #include "../Common/fonts.c"
00027
00028 /** @addtogroup Utilities
00029   * @{
00030   */
00031
00032 /** @addtogroup STM32_EVAL
00033   * @{
00034   */
00035
00036 /** @addtogroup STM32L152_EVAL
00037   * @{
00038   */
00039
00040 /** @defgroup STM32L152_EVAL_LCD
00041   * @brief   This file includes the LCD driver for AM-240320L8TNQW00H (LCD_ILI9320),
00042   *          AM-240320LDTNQW00H (LCD_SPFD5408B) Liquid Crystal Display Module
00043   *          of STM32L152-EVAL board.
00044   * @{
00045   */
00046
00047 /** @defgroup STM32L152_EVAL_LCD_Private_Types
00048   * @{
00049   */
00050 /**
00051   * @}
00052   */
00053
00054 /** @defgroup STM32L152_EVAL_LCD_Private_Defines
00055   * @{
00056   */
00057 #define LCD_ILI9320        0x9320
00058 #define LCD_SPFD5408       0x5408
00059 #define START_BYTE         0x70
00060 #define SET_INDEX          0x00
00061 #define READ_STATUS        0x01
00062 #define LCD_WRITE_REG      0x02
00063 #define LCD_READ_REG       0x03
00064 #define MAX_POLY_CORNERS   200
00065 #define POLY_Y(Z)          ((int32_t)((Points + Z)->X))
00066 #define POLY_X(Z)          ((int32_t)((Points + Z)->Y))
00067 /**
00068   * @}
00069   */
00070
00071 /** @defgroup STM32L152_EVAL_LCD_Private_Macros
00072   * @{
00073   */
00074 #define ABS(X)  ((X) > 0 ? (X) : -(X))
00075 /**
00076   * @}
00077   */
00078
00079 /** @defgroup STM32L152_EVAL_LCD_Private_Variables
00080   * @{
00081   */
00082 static sFONT *LCD_Currentfonts;
00083 /* Global variables to set the written text color */
00084 static __IO uint16_t TextColor = 0x0000, BackColor = 0xFFFF;
00085 static __IO uint32_t LCDType = LCD_SPFD5408;
00086 /**
00087   * @}
00088   */
00089
00090 /** @defgroup STM32L152_EVAL_LCD_Private_Function_Prototypes
00091   * @{
00092   */
00093 #ifndef USE_Delay
00094 static void delay(__IO uint32_t nCount);
00095 #endif /* USE_Delay*/
00096
00097 static void PutPixel(int16_t x, int16_t y);
00098 static void LCD_PolyLineRelativeClosed(pPoint Points, uint16_t PointCount, uint16_t Closed);
00099
00100 /**
00101   * @}
00102   */
00103
00104 /** @defgroup STM32L152_EVAL_LCD_Private_Functions
00105   * @{
00106   */
00107
00108 /**
00109   * @brief  DeInitializes the LCD.
00110   * @param  None
00111   * @retval None
00112   */
00113 void STM32L152_LCD_DeInit(void)
00114 {
00115   GPIO_InitTypeDef GPIO_InitStructure;
00116
00117   /*!< LCD Display Off */
00118   LCD_DisplayOff();
00119
00120   /*!< LCD_SPI disable */
00121   SPI_Cmd(LCD_SPI, DISABLE);
00122
00123   /*!< LCD_SPI DeInit */
00124   SPI_DeInit(LCD_SPI);
00125
00126   /*!< Disable SPI clock  */
00127   RCC_APB1PeriphClockCmd(LCD_SPI_CLK, DISABLE);
00128
00129   /* Configure NCS in Output Push-Pull mode */
00130   GPIO_InitStructure.GPIO_Pin = LCD_NCS_PIN;
00131   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
00132   GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
00133   GPIO_Init(LCD_NCS_GPIO_PORT, &GPIO_InitStructure);
00134
00135   /* Configure SPI pins: SCK, MISO and MOSI */
00136   GPIO_InitStructure.GPIO_Pin = LCD_SPI_SCK_PIN;
00137   GPIO_Init(LCD_SPI_SCK_GPIO_PORT, &GPIO_InitStructure);
00138
00139   GPIO_InitStructure.GPIO_Pin = LCD_SPI_MISO_PIN;
00140   GPIO_Init(LCD_SPI_MISO_GPIO_PORT, &GPIO_InitStructure);
00141
00142   GPIO_InitStructure.GPIO_Pin = LCD_SPI_MOSI_PIN;
00143   GPIO_Init(LCD_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure);
00144 }
00145
00146 /**
00147   * @brief  Setups the LCD.
00148   * @param  None
00149   * @retval None
00150   */
00151 void LCD_Setup(void)
00152 {
00153 /* Configure the LCD Control pins --------------------------------------------*/
00154   LCD_CtrlLinesConfig();
00155
00156 /* Configure the LCD_SPI interface ----------------------------------------------*/
00157   LCD_SPIConfig();
00158
00159   if(LCDType == LCD_SPFD5408)
00160   {
00161     /* Start Initial Sequence --------------------------------------------------*/
00162     LCD_WriteReg(LCD_REG_227, 0x3008); /* Set internal timing */
00163     LCD_WriteReg(LCD_REG_231, 0x0012); /* Set internal timing */
00164     LCD_WriteReg(LCD_REG_239, 0x1231); /* Set internal timing */
00165     LCD_WriteReg(LCD_REG_1, 0x0100);   /* Set SS and SM bit */
00166     LCD_WriteReg(LCD_REG_2, 0x0700);   /* Set 1 line inversion */
00167     LCD_WriteReg(LCD_REG_3, 0x1030);   /* Set GRAM write direction and BGR=1. */
00168     LCD_WriteReg(LCD_REG_4, 0x0000);   /* Resize register */
00169     LCD_WriteReg(LCD_REG_8, 0x0202);   /* Set the back porch and front porch */
00170     LCD_WriteReg(LCD_REG_9, 0x0000);   /* Set non-display area refresh cycle ISC[3:0] */
00171     LCD_WriteReg(LCD_REG_10, 0x0000);  /* FMARK function */
00172     LCD_WriteReg(LCD_REG_12, 0x0000);  /* RGB interface setting */
00173     LCD_WriteReg(LCD_REG_13, 0x0000);  /* Frame marker Position */
00174     LCD_WriteReg(LCD_REG_15, 0x0000);  /* RGB interface polarity */
00175     /* Power On sequence -------------------------------------------------------*/
00176     LCD_WriteReg(LCD_REG_16, 0x0000);  /* SAP, BT[3:0], AP, DSTB, SLP, STB */
00177     LCD_WriteReg(LCD_REG_17, 0x0000);  /* DC1[2:0], DC0[2:0], VC[2:0] */
00178     LCD_WriteReg(LCD_REG_18, 0x0000);  /* VREG1OUT voltage */
00179     LCD_WriteReg(LCD_REG_19, 0x0000);  /* VDV[4:0] for VCOM amplitude */
00180     _delay_(20);                /* Dis-charge capacitor power voltage (200ms) */
00181     LCD_WriteReg(LCD_REG_17, 0x0007);  /* DC1[2:0], DC0[2:0], VC[2:0] */
00182     _delay_(5);                 /* Delay 50 ms */
00183     LCD_WriteReg(LCD_REG_16, 0x12B0);  /* SAP, BT[3:0], AP, DSTB, SLP, STB */
00184     _delay_(5);                  /* Delay 50 ms */
00185     LCD_WriteReg(LCD_REG_18, 0x01BD);  /* External reference voltage= Vci */
00186     _delay_(5);                 /* Delay 50 ms */
00187     LCD_WriteReg(LCD_REG_19, 0x1400);       /* VDV[4:0] for VCOM amplitude */
00188     LCD_WriteReg(LCD_REG_41, 0x000E);  /* VCM[4:0] for VCOMH */
00189     _delay_(5);                 /* Delay 50 ms */
00190     LCD_WriteReg(LCD_REG_32, 0x0000);  /* GRAM horizontal Address */
00191     LCD_WriteReg(LCD_REG_33, 0x013F);  /* GRAM Vertical Address */
00192     /* Adjust the Gamma Curve --------------------------------------------------*/
00193     LCD_WriteReg(LCD_REG_48, 0x0007);
00194     LCD_WriteReg(LCD_REG_49, 0x0302);
00195     LCD_WriteReg(LCD_REG_50, 0x0105);
00196     LCD_WriteReg(LCD_REG_53, 0x0206);
00197     LCD_WriteReg(LCD_REG_54, 0x0808);
00198     LCD_WriteReg(LCD_REG_55, 0x0206);
00199     LCD_WriteReg(LCD_REG_56, 0x0504);
00200     LCD_WriteReg(LCD_REG_57, 0x0007);
00201     LCD_WriteReg(LCD_REG_60, 0x0105);
00202     LCD_WriteReg(LCD_REG_61, 0x0808);
00203     /* Set GRAM area -----------------------------------------------------------*/
00204     LCD_WriteReg(LCD_REG_80, 0x0000);  /* Horizontal GRAM Start Address */
00205     LCD_WriteReg(LCD_REG_81, 0x00EF);  /* Horizontal GRAM End Address */
00206     LCD_WriteReg(LCD_REG_82, 0x0000);  /* Vertical GRAM Start Address */
00207     LCD_WriteReg(LCD_REG_83, 0x013F);  /* Vertical GRAM End Address */
00208     LCD_WriteReg(LCD_REG_96,  0xA700); /* Gate Scan Line */
00209     LCD_WriteReg(LCD_REG_97,  0x0001); /* NDL,VLE, REV */
00210     LCD_WriteReg(LCD_REG_106, 0x0000); /* Set scrolling line */
00211     /* Partial Display Control -------------------------------------------------*/
00212     LCD_WriteReg(LCD_REG_128, 0x0000);
00213     LCD_WriteReg(LCD_REG_129, 0x0000);
00214     LCD_WriteReg(LCD_REG_130, 0x0000);
00215     LCD_WriteReg(LCD_REG_131, 0x0000);
00216     LCD_WriteReg(LCD_REG_132, 0x0000);
00217     LCD_WriteReg(LCD_REG_133, 0x0000);
00218     /* Panel Control -----------------------------------------------------------*/
00219     LCD_WriteReg(LCD_REG_144, 0x0010);
00220     LCD_WriteReg(LCD_REG_146, 0x0000);
00221     LCD_WriteReg(LCD_REG_147, 0x0003);
00222     LCD_WriteReg(LCD_REG_149, 0x0110);
00223     LCD_WriteReg(LCD_REG_151, 0x0000);
00224     LCD_WriteReg(LCD_REG_152, 0x0000);
00225     /* Set GRAM write direction and BGR = 1
00226        I/D=01 (Horizontal : increment, Vertical : decrement)
00227        AM=1 (address is updated in vertical writing direction) */
00228     LCD_WriteReg(LCD_REG_3, 0x1018);
00229     LCD_WriteReg(LCD_REG_7, 0x0112);   /* 262K color and display ON */
00230   }
00231   else if(LCDType == LCD_ILI9320)
00232   {
00233     _delay_(5); /* Delay 50 ms */
00234     /* Start Initial Sequence ------------------------------------------------*/
00235     LCD_WriteReg(LCD_REG_229, 0x8000); /* Set the internal vcore voltage */
00236     LCD_WriteReg(LCD_REG_0,  0x0001); /* Start internal OSC. */
00237     LCD_WriteReg(LCD_REG_1,  0x0100); /* set SS and SM bit */
00238     LCD_WriteReg(LCD_REG_2,  0x0700); /* set 1 line inversion */
00239     LCD_WriteReg(LCD_REG_3,  0x1030); /* set GRAM write direction and BGR=1. */
00240     LCD_WriteReg(LCD_REG_4,  0x0000); /* Resize register */
00241     LCD_WriteReg(LCD_REG_8,  0x0202); /* set the back porch and front porch */
00242     LCD_WriteReg(LCD_REG_9,  0x0000); /* set non-display area refresh cycle ISC[3:0] */
00243     LCD_WriteReg(LCD_REG_10, 0x0000); /* FMARK function */
00244     LCD_WriteReg(LCD_REG_12, 0x0000); /* RGB interface setting */
00245     LCD_WriteReg(LCD_REG_13, 0x0000); /* Frame marker Position */
00246     LCD_WriteReg(LCD_REG_15, 0x0000); /* RGB interface polarity */
00247     /* Power On sequence -----------------------------------------------------*/
00248     LCD_WriteReg(LCD_REG_16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
00249     LCD_WriteReg(LCD_REG_17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */
00250     LCD_WriteReg(LCD_REG_18, 0x0000); /* VREG1OUT voltage */
00251     LCD_WriteReg(LCD_REG_19, 0x0000); /* VDV[4:0] for VCOM amplitude */
00252     _delay_(20);                      /* Dis-charge capacitor power voltage (200ms) */
00253     LCD_WriteReg(LCD_REG_16, 0x17B0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
00254     LCD_WriteReg(LCD_REG_17, 0x0137); /* DC1[2:0], DC0[2:0], VC[2:0] */
00255     _delay_(5);                       /* Delay 50 ms */
00256     LCD_WriteReg(LCD_REG_18, 0x0139); /* VREG1OUT voltage */
00257     _delay_(5);                       /* Delay 50 ms */
00258     LCD_WriteReg(LCD_REG_19, 0x1d00); /* VDV[4:0] for VCOM amplitude */
00259     LCD_WriteReg(LCD_REG_41, 0x0013); /* VCM[4:0] for VCOMH */
00260     _delay_(5);                       /* Delay 50 ms */
00261     LCD_WriteReg(LCD_REG_32, 0x0000); /* GRAM horizontal Address */
00262     LCD_WriteReg(LCD_REG_33, 0x0000); /* GRAM Vertical Address */
00263     /* Adjust the Gamma Curve ------------------------------------------------*/
00264     LCD_WriteReg(LCD_REG_48, 0x0006);
00265     LCD_WriteReg(LCD_REG_49, 0x0101);
00266     LCD_WriteReg(LCD_REG_50, 0x0003);
00267     LCD_WriteReg(LCD_REG_53, 0x0106);
00268     LCD_WriteReg(LCD_REG_54, 0x0b02);
00269     LCD_WriteReg(LCD_REG_55, 0x0302);
00270     LCD_WriteReg(LCD_REG_56, 0x0707);
00271     LCD_WriteReg(LCD_REG_57, 0x0007);
00272     LCD_WriteReg(LCD_REG_60, 0x0600);
00273     LCD_WriteReg(LCD_REG_61, 0x020b);
00274
00275     /* Set GRAM area ---------------------------------------------------------*/
00276     LCD_WriteReg(LCD_REG_80, 0x0000); /* Horizontal GRAM Start Address */
00277     LCD_WriteReg(LCD_REG_81, 0x00EF); /* Horizontal GRAM End Address */
00278     LCD_WriteReg(LCD_REG_82, 0x0000); /* Vertical GRAM Start Address */
00279     LCD_WriteReg(LCD_REG_83, 0x013F); /* Vertical GRAM End Address */
00280     LCD_WriteReg(LCD_REG_96,  0x2700); /* Gate Scan Line */
00281     LCD_WriteReg(LCD_REG_97,  0x0001); /* NDL,VLE, REV */
00282     LCD_WriteReg(LCD_REG_106, 0x0000); /* set scrolling line */
00283     /* Partial Display Control -----------------------------------------------*/
00284     LCD_WriteReg(LCD_REG_128, 0x0000);
00285     LCD_WriteReg(LCD_REG_129, 0x0000);
00286     LCD_WriteReg(LCD_REG_130, 0x0000);
00287     LCD_WriteReg(LCD_REG_131, 0x0000);
00288     LCD_WriteReg(LCD_REG_132, 0x0000);
00289     LCD_WriteReg(LCD_REG_133, 0x0000);
00290     /* Panel Control ---------------------------------------------------------*/
00291     LCD_WriteReg(LCD_REG_144, 0x0010);
00292     LCD_WriteReg(LCD_REG_146, 0x0000);
00293     LCD_WriteReg(LCD_REG_147, 0x0003);
00294     LCD_WriteReg(LCD_REG_149, 0x0110);
00295     LCD_WriteReg(LCD_REG_151, 0x0000);
00296     LCD_WriteReg(LCD_REG_152, 0x0000);
00297     /* Set GRAM write direction and BGR = 1 */
00298     /* I/D=01 (Horizontal : increment, Vertical : decrement) */
00299     /* AM=1 (address is updated in vertical writing direction) */
00300     LCD_WriteReg(LCD_REG_3, 0x1018);
00301     LCD_WriteReg(LCD_REG_7, 0x0173); /* 262K color and display ON */
00302   }
00303 }
00304
00305
00306 /**
00307   * @brief  Initializes the LCD.
00308   * @param  None
00309   * @retval None
00310   */
00311 void STM32L152_LCD_Init(void)
00312 {
00313   /* Setups the LCD */
00314   LCD_Setup();
00315
00316   /* Try to read new LCD controller ID 0x5408 */
00317   if (LCD_ReadReg(LCD_REG_0) == LCD_SPFD5408)
00318   {
00319     LCDType = LCD_SPFD5408;
00320   }
00321   else
00322   {
00323     LCDType = LCD_ILI9320;
00324     /* Setups the LCD */
00325     LCD_Setup();
00326   }
00327
00328   LCD_SetFont(&LCD_DEFAULT_FONT);
00329 }
00330
00331 /**
00332   * @brief  Sets the LCD Text and Background colors.
00333   * @param  _TextColor: specifies the Text Color.
00334   * @param  _BackColor: specifies the Background Color.
00335   * @retval None
00336   */
00337 void LCD_SetColors(__IO uint16_t _TextColor, __IO uint16_t _BackColor)
00338 {
00339   TextColor = _TextColor;
00340   BackColor = _BackColor;
00341 }
00342
00343 /**
00344   * @brief  Gets the LCD Text and Background colors.
00345   * @param  _TextColor: pointer to the variable that will contain the Text
00346             Color.
00347   * @param  _BackColor: pointer to the variable that will contain the Background
00348             Color.
00349   * @retval None
00350   */
00351 void LCD_GetColors(__IO uint16_t *_TextColor, __IO uint16_t *_BackColor)
00352 {
00353   *_TextColor = TextColor; *_BackColor = BackColor;
00354 }
00355
00356 /**
00357   * @brief  Sets the Text color.
00358   * @param  Color: specifies the Text color code RGB(5-6-5).
00359   * @retval None
00360   */
00361 void LCD_SetTextColor(__IO uint16_t Color)
00362 {
00363   TextColor = Color;
00364 }
00365
00366
00367 /**
00368   * @brief  Sets the Background color.
00369   * @param  Color: specifies the Background color code RGB(5-6-5).
00370   * @retval None
00371   */
00372 void LCD_SetBackColor(__IO uint16_t Color)
00373 {
00374   BackColor = Color;
00375 }
00376
00377 /**
00378   * @brief  Sets the Text Font.
00379   * @param  fonts: specifies the font to be used.
00380   * @retval None
00381   */
00382 void LCD_SetFont(sFONT *fonts)
00383 {
00384   LCD_Currentfonts = fonts;
00385 }
00386
00387 /**
00388   * @brief  Gets the Text Font.
00389   * @param  None.
00390   * @retval the used font.
00391   */
00392 sFONT *LCD_GetFont(void)
00393 {
00394   return LCD_Currentfonts;
00395 }
00396
00397 /**
00398   * @brief  Clears the selected line.
00399   * @param  Line: the Line to be cleared.
00400   *   This parameter can be one of the following values:
00401   *     @arg Linex: where x can be 0..n
00402   * @retval None
00403   */
00404 void LCD_ClearLine(uint8_t Line)
00405 {
00406   uint16_t refcolumn = LCD_PIXEL_WIDTH - 1;
00407
00408   /* Send the string character by character on lCD */
00409   while (((refcolumn + 1) & 0xFFFF) >= LCD_Currentfonts->Width)
00410   {
00411     /* Display one character on LCD */
00412     LCD_DisplayChar(Line, refcolumn, ' ');
00413     /* Decrement the column position by 16 */
00414     refcolumn -= LCD_Currentfonts->Width;
00415   }
00416 }
00417
00418
00419 /**
00420   * @brief  Clears the hole LCD.
00421   * @param  Color: the color of the background.
00422   * @retval None
00423   */
00424 void LCD_Clear(uint16_t Color)
00425 {
00426   uint32_t index = 0;
00427
00428   LCD_SetCursor(0x00, 0x013F);
00429
00430   LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
00431
00432   for(index = 0; index < 76800; index++)
00433   {
00434     LCD_WriteRAM(Color);
00435   }
00436
00437   LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
00438
00439 }
00440
00441
00442 /**
00443   * @brief  Sets the cursor position.
00444   * @param  Xpos: specifies the X position.
00445   * @param  Ypos: specifies the Y position.
00446   * @retval None
00447   */
00448 void LCD_SetCursor(uint8_t Xpos, uint16_t Ypos)
00449 {
00450   LCD_WriteReg(LCD_REG_32, Xpos);
00451   LCD_WriteReg(LCD_REG_33, Ypos);
00452 }
00453
00454
00455 /**
00456   * @brief  Draws a character on LCD.
00457   * @param  Xpos: the Line where to display the character shape.
00458   * @param  Ypos: start column address.
00459   * @param  c: pointer to the character data.
00460   * @retval None
00461   */
00462 void LCD_DrawChar(uint8_t Xpos, uint16_t Ypos, const uint16_t *c)
00463 {
00464   uint32_t index = 0, i = 0;
00465   uint8_t Xaddress = 0;
00466
00467   Xaddress = Xpos;
00468
00469   LCD_SetCursor(Xaddress, Ypos);
00470
00471   for(index = 0; index < LCD_Currentfonts->Height; index++)
00472   {
00473     LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
00474
00475     for(i = 0; i < LCD_Currentfonts->Width; i++)
00476     {
00477       if((((c[index] & ((0x80 << ((LCD_Currentfonts->Width / 12 ) * 8 ) ) >> i)) == 0x00) &&(LCD_Currentfonts->Width <= 12))||
00478         (((c[index] & (0x1 << i)) == 0x00)&&(LCD_Currentfonts->Width > 12 )))
00479
00480       {
00481         LCD_WriteRAM(BackColor);
00482       }
00483       else
00484       {
00485         LCD_WriteRAM(TextColor);
00486       }
00487     }
00488
00489     LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
00490     Xaddress++;
00491     LCD_SetCursor(Xaddress, Ypos);
00492   }
00493 }
00494
00495
00496 /**
00497   * @brief  Displays one character (16dots width, 24dots height).
00498   * @param  Line: the Line where to display the character shape .
00499   *   This parameter can be one of the following values:
00500   *     @arg Linex: where x can be 0..9
00501   * @param  Column: start column address.
00502   * @param  Ascii: character ascii code, must be between 0x20 and 0x7E.
00503   * @retval None
00504   */
00505 void LCD_DisplayChar(uint8_t Line, uint16_t Column, uint8_t Ascii)
00506 {
00507   Ascii -= 32;
00508   LCD_DrawChar(Line, Column, &LCD_Currentfonts->table[Ascii * LCD_Currentfonts->Height]);
00509 }
00510
00511
00512 /**
00513   * @brief  Displays a maximum of 20 char on the LCD.
00514   * @param  Line: the Line where to display the character shape .
00515   *   This parameter can be one of the following values:
00516   *     @arg Linex: where x can be 0..9
00517   * @param  *ptr: pointer to string to display on LCD.
00518   * @retval None
00519   */
00520 void LCD_DisplayStringLine(uint8_t Line, uint8_t *ptr)
00521 {
00522   uint16_t refcolumn = LCD_PIXEL_WIDTH - 1;
00523
00524   /* Send the string character by character on lCD */
00525   while ((*ptr != 0) & (((refcolumn + 1) & 0xFFFF) >= LCD_Currentfonts->Width))
00526   {
00527     /* Display one character on LCD */
00528     LCD_DisplayChar(Line, refcolumn, *ptr);
00529     /* Decrement the column position by 16 */
00530     refcolumn -= LCD_Currentfonts->Width;
00531     /* Point on the next character */
00532     ptr++;
00533   }
00534 }
00535
00536
00537 /**
00538   * @brief  Sets a display window
00539   * @param  Xpos: specifies the X buttom left position.
00540   * @param  Ypos: specifies the Y buttom left position.
00541   * @param  Height: display window height.
00542   * @param  Width: display window width.
00543   * @retval None
00544   */
00545 void LCD_SetDisplayWindow(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width)
00546 {
00547   /* Horizontal GRAM Start Address */
00548   if(Xpos >= Height)
00549   {
00550     LCD_WriteReg(LCD_REG_80, (Xpos - Height + 1));
00551   }
00552   else
00553   {
00554     LCD_WriteReg(LCD_REG_80, 0);
00555   }
00556   /* Horizontal GRAM End Address */
00557   LCD_WriteReg(LCD_REG_81, Xpos);
00558   /* Vertical GRAM Start Address */
00559   if(Ypos >= Width)
00560   {
00561     LCD_WriteReg(LCD_REG_82, (Ypos - Width + 1));
00562   }
00563   else
00564   {
00565     LCD_WriteReg(LCD_REG_82, 0);
00566   }
00567   /* Vertical GRAM End Address */
00568   LCD_WriteReg(LCD_REG_83, Ypos);
00569
00570   LCD_SetCursor(Xpos, Ypos);
00571 }
00572
00573
00574 /**
00575   * @brief  Disables LCD Window mode.
00576   * @param  None
00577   * @retval None
00578   */
00579 void LCD_WindowModeDisable(void)
00580 {
00581   LCD_SetDisplayWindow(239, 0x13F, 240, 320);
00582   LCD_WriteReg(LCD_REG_3, 0x1018);
00583 }
00584
00585 /**
00586   * @brief  Displays a line.
00587   * @param  Xpos: specifies the X position.
00588   * @param  Ypos: specifies the Y position.
00589   * @param  Length: line length.
00590   * @param  Direction: line direction.
00591   *   This parameter can be one of the following values: Vertical or Horizontal.
00592   * @retval None
00593   */
00594 void LCD_DrawLine(uint8_t Xpos, uint16_t Ypos, uint16_t Length, uint8_t Direction)
00595 {
00596   uint32_t i = 0;
00597
00598   LCD_SetCursor(Xpos, Ypos);
00599
00600   if(Direction == LCD_DIR_HORIZONTAL)
00601   {
00602     LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
00603
00604     for(i = 0; i < Length; i++)
00605     {
00606       LCD_WriteRAM(TextColor);
00607     }
00608     LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
00609   }
00610   else
00611   {
00612     for(i = 0; i < Length; i++)
00613     {
00614       LCD_WriteRAMWord(TextColor);
00615       Xpos++;
00616       LCD_SetCursor(Xpos, Ypos);
00617     }
00618   }
00619 }
00620
00621
00622 /**
00623   * @brief  Displays a rectangle.
00624   * @param  Xpos: specifies the X position.
00625   * @param  Ypos: specifies the Y position.
00626   * @param  Height: display rectangle height.
00627   * @param  Width: display rectangle width.
00628   * @retval None
00629   */
00630 void LCD_DrawRect(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width)
00631 {
00632   LCD_DrawLine(Xpos, Ypos, Width, LCD_DIR_HORIZONTAL);
00633   LCD_DrawLine((Xpos + Height), Ypos, Width, LCD_DIR_HORIZONTAL);
00634
00635   LCD_DrawLine(Xpos, Ypos, Height, LCD_DIR_VERTICAL);
00636   LCD_DrawLine(Xpos, (Ypos - Width + 1), Height, LCD_DIR_VERTICAL);
00637 }
00638
00639
00640 /**
00641   * @brief  Displays a circle.
00642   * @param  Xpos: specifies the X position.
00643   * @param  Ypos: specifies the Y position.
00644   * @param  Radius
00645   * @retval None
00646   */
00647 void LCD_DrawCircle(uint8_t Xpos, uint16_t Ypos, uint16_t Radius)
00648 {
00649   int32_t  D;/* Decision Variable */
00650   uint32_t  CurX;/* Current X Value */
00651   uint32_t  CurY;/* Current Y Value */
00652
00653   D = 3 - (Radius << 1);
00654   CurX = 0;
00655   CurY = Radius;
00656
00657   while (CurX <= CurY)
00658   {
00659     LCD_SetCursor(Xpos + CurX, Ypos + CurY);
00660     LCD_WriteRAMWord(TextColor);
00661     LCD_SetCursor(Xpos + CurX, Ypos - CurY);
00662     LCD_WriteRAMWord(TextColor);
00663
00664     LCD_SetCursor(Xpos - CurX, Ypos + CurY);
00665     LCD_WriteRAMWord(TextColor);
00666
00667     LCD_SetCursor(Xpos - CurX, Ypos - CurY);
00668     LCD_WriteRAMWord(TextColor);
00669
00670     LCD_SetCursor(Xpos + CurY, Ypos + CurX);
00671     LCD_WriteRAMWord(TextColor);
00672
00673     LCD_SetCursor(Xpos + CurY, Ypos - CurX);
00674     LCD_WriteRAMWord(TextColor);
00675
00676     LCD_SetCursor(Xpos - CurY, Ypos + CurX);
00677     LCD_WriteRAMWord(TextColor);
00678
00679     LCD_SetCursor(Xpos - CurY, Ypos - CurX);
00680     LCD_WriteRAMWord(TextColor);
00681
00682     if (D < 0)
00683     {
00684       D += (CurX << 2) + 6;
00685     }
00686     else
00687     {
00688       D += ((CurX - CurY) << 2) + 10;
00689       CurY--;
00690     }
00691     CurX++;
00692   }
00693 }
00694
00695
00696 /**
00697   * @brief  Displays a monocolor picture.
00698   * @param  Pict: pointer to the picture array.
00699   * @retval None
00700   */
00701 void LCD_DrawMonoPict(const uint32_t *Pict)
00702 {
00703   uint32_t index = 0, i = 0;
00704   LCD_SetCursor(0, (LCD_PIXEL_WIDTH - 1));
00705
00706   LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
00707
00708   for(index = 0; index < 2400; index++)
00709   {
00710     for(i = 0; i < 32; i++)
00711     {
00712       if((Pict[index] & (1 << i)) == 0x00)
00713       {
00714         LCD_WriteRAM(BackColor);
00715       }
00716       else
00717       {
00718         LCD_WriteRAM(TextColor);
00719       }
00720     }
00721   }
00722
00723   LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
00724 }
00725
00726 #ifdef USE_LCD_DrawBMP
00727 /**
00728   * @brief  Displays a bitmap picture loaded in the SPI Flash.
00729   * @param  BmpAddress: Bmp picture address in the SPI Flash.
00730   * @retval None
00731   */
00732 void LCD_DrawBMP(uint32_t BmpAddress)
00733 {
00734   uint32_t i = 0, size = 0;
00735   /* Read bitmap size */
00736   sFLASH_ReadBuffer((uint8_t*)&size, BmpAddress + 2, 4);
00737   /* get bitmap data address offset */
00738   sFLASH_ReadBuffer((uint8_t*)&i, BmpAddress + 10, 4);
00739
00740   size = (size - i)/2;
00741   sFLASH_StartReadSequence(BmpAddress + i);
00742   /* Disable LCD_SPI  */
00743   SPI_Cmd(LCD_SPI, DISABLE);
00744   /* SPI in 16-bit mode */
00745   SPI_DataSizeConfig(LCD_SPI, SPI_DataSize_16b);
00746   /* Enable LCD_SPI  */
00747   SPI_Cmd(LCD_SPI, ENABLE);
00748
00749   if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
00750   {
00751     /* Set GRAM write direction and BGR = 1 */
00752     /* I/D=00 (Horizontal : decrement, Vertical : decrement) */
00753     /* AM=1 (address is updated in vertical writing direction) */
00754     LCD_WriteReg(LCD_REG_3, 0x1008);
00755     LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
00756   }
00757
00758   /* Read bitmap data from SPI Flash and send them to LCD */
00759   for(i = 0; i < size; i++)
00760   {
00761     LCD_WriteRAM(__REV16(sFLASH_SendHalfWord(0xA5A5)));
00762   }
00763   if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
00764   {
00765     LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
00766   }
00767
00768   /* Deselect the FLASH: Chip Select high */
00769   sFLASH_CS_HIGH();
00770   /* Disable LCD_SPI  */
00771   SPI_Cmd(LCD_SPI, DISABLE);
00772   /* SPI in 8-bit mode */
00773   SPI_DataSizeConfig(LCD_SPI, SPI_DataSize_8b);
00774   /* Enable LCD_SPI  */
00775   SPI_Cmd(LCD_SPI, ENABLE);
00776
00777   if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
00778   {
00779     /* Set GRAM write direction and BGR = 1 */
00780     /* I/D = 01 (Horizontal : increment, Vertical : decrement) */
00781     /* AM = 1 (address is updated in vertical writing direction) */
00782     LCD_WriteReg(LCD_REG_3, 0x1018);
00783   }
00784 }
00785 #endif /* USE_LCD_DrawBMP */
00786
00787 /**
00788   * @brief  Displays a full rectangle.
00789   * @param  Xpos: specifies the X position.
00790   * @param  Ypos: specifies the Y position.
00791   * @param  Height: rectangle height.
00792   * @param  Width: rectangle width.
00793   * @retval None
00794   */
00795 void LCD_DrawFullRect(uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height)
00796 {
00797   LCD_SetTextColor(TextColor);
00798
00799   LCD_DrawLine(Xpos, Ypos, Width, LCD_DIR_HORIZONTAL);
00800   LCD_DrawLine((Xpos + Height), Ypos, Width, LCD_DIR_HORIZONTAL);
00801
00802   LCD_DrawLine(Xpos, Ypos, Height, LCD_DIR_VERTICAL);
00803   LCD_DrawLine(Xpos, (Ypos - Width + 1), Height, LCD_DIR_VERTICAL);
00804
00805   Width -= 2;
00806   Height--;
00807   Ypos--;
00808
00809   LCD_SetTextColor(BackColor);
00810
00811   while(Height--)
00812   {
00813     LCD_DrawLine(++Xpos, Ypos, Width, LCD_DIR_HORIZONTAL);
00814   }
00815
00816   LCD_SetTextColor(TextColor);
00817 }
00818
00819 /**
00820   * @brief  Displays a full circle.
00821   * @param  Xpos: specifies the X position.
00822   * @param  Ypos: specifies the Y position.
00823   * @param  Radius
00824   * @retval None
00825   */
00826 void LCD_DrawFullCircle(uint16_t Xpos, uint16_t Ypos, uint16_t Radius)
00827 {
00828   int32_t  D;    /* Decision Variable */
00829   uint32_t  CurX;/* Current X Value */
00830   uint32_t  CurY;/* Current Y Value */
00831
00832   D = 3 - (Radius << 1);
00833
00834   CurX = 0;
00835   CurY = Radius;
00836
00837   LCD_SetTextColor(BackColor);
00838
00839   while (CurX <= CurY)
00840   {
00841     if(CurY > 0)
00842     {
00843       LCD_DrawLine(Xpos - CurX, Ypos + CurY, 2*CurY, LCD_DIR_HORIZONTAL);
00844       LCD_DrawLine(Xpos + CurX, Ypos + CurY, 2*CurY, LCD_DIR_HORIZONTAL);
00845     }
00846
00847     if(CurX > 0)
00848     {
00849       LCD_DrawLine(Xpos - CurY, Ypos + CurX, 2*CurX, LCD_DIR_HORIZONTAL);
00850       LCD_DrawLine(Xpos + CurY, Ypos + CurX, 2*CurX, LCD_DIR_HORIZONTAL);
00851     }
00852     if (D < 0)
00853     {
00854       D += (CurX << 2) + 6;
00855     }
00856     else
00857     {
00858       D += ((CurX - CurY) << 2) + 10;
00859       CurY--;
00860     }
00861     CurX++;
00862   }
00863
00864   LCD_SetTextColor(TextColor);
00865   LCD_DrawCircle(Xpos, Ypos, Radius);
00866 }
00867
00868 /**
00869   * @brief  Displays an uni line (between two points).
00870   * @param  x1: specifies the point 1 x position.
00871   * @param  y1: specifies the point 1 y position.
00872   * @param  x2: specifies the point 2 x position.
00873   * @param  y2: specifies the point 2 y position.
00874   * @retval None
00875   */
00876 void LCD_DrawUniLine(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2)
00877 {
00878   int16_t deltax = 0, deltay = 0, x = 0, y = 0, xinc1 = 0, xinc2 = 0,
00879   yinc1 = 0, yinc2 = 0, den = 0, num = 0, numadd = 0, numpixels = 0,
00880   curpixel = 0;
00881
00882   deltax = ABS(x2 - x1);        /* The difference between the x's */
00883   deltay = ABS(y2 - y1);        /* The difference between the y's */
00884   x = x1;                       /* Start x off at the first pixel */
00885   y = y1;                       /* Start y off at the first pixel */
00886
00887   if (x2 >= x1)                 /* The x-values are increasing */
00888   {
00889     xinc1 = 1;
00890     xinc2 = 1;
00891   }
00892   else                          /* The x-values are decreasing */
00893   {
00894     xinc1 = -1;
00895     xinc2 = -1;
00896   }
00897
00898   if (y2 >= y1)                 /* The y-values are increasing */
00899   {
00900     yinc1 = 1;
00901     yinc2 = 1;
00902   }
00903   else                          /* The y-values are decreasing */
00904   {
00905     yinc1 = -1;
00906     yinc2 = -1;
00907   }
00908
00909   if (deltax >= deltay)         /* There is at least one x-value for every y-value */
00910   {
00911     xinc1 = 0;                  /* Don't change the x when numerator >= denominator */
00912     yinc2 = 0;                  /* Don't change the y for every iteration */
00913     den = deltax;
00914     num = deltax / 2;
00915     numadd = deltay;
00916     numpixels = deltax;         /* There are more x-values than y-values */
00917   }
00918   else                          /* There is at least one y-value for every x-value */
00919   {
00920     xinc2 = 0;                  /* Don't change the x for every iteration */
00921     yinc1 = 0;                  /* Don't change the y when numerator >= denominator */
00922     den = deltay;
00923     num = deltay / 2;
00924     numadd = deltax;
00925     numpixels = deltay;         /* There are more y-values than x-values */
00926   }
00927
00928   for (curpixel = 0; curpixel <= numpixels; curpixel++)
00929   {
00930     PutPixel(x, y);             /* Draw the current pixel */
00931     num += numadd;              /* Increase the numerator by the top of the fraction */
00932     if (num >= den)             /* Check if numerator >= denominator */
00933     {
00934       num -= den;               /* Calculate the new numerator value */
00935       x += xinc1;               /* Change the x as appropriate */
00936       y += yinc1;               /* Change the y as appropriate */
00937     }
00938     x += xinc2;                 /* Change the x as appropriate */
00939     y += yinc2;                 /* Change the y as appropriate */
00940   }
00941 }
00942
00943 /**
00944   * @brief  Displays an polyline (between many points).
00945   * @param  Points: pointer to the points array.
00946   * @param  PointCount: Number of points.
00947   * @retval None
00948   */
00949 void LCD_PolyLine(pPoint Points, uint16_t PointCount)
00950 {
00951   int16_t X = 0, Y = 0;
00952
00953   if(PointCount < 2)
00954   {
00955     return;
00956   }
00957
00958   while(--PointCount)
00959   {
00960     X = Points->X;
00961     Y = Points->Y;
00962     Points++;
00963     LCD_DrawUniLine(X, Y, Points->X, Points->Y);
00964   }
00965 }
00966
00967 /**
00968   * @brief  Displays an relative polyline (between many points).
00969   * @param  Points: pointer to the points array.
00970   * @param  PointCount: Number of points.
00971   * @param  Closed: specifies if the draw is closed or not.
00972   *           1: closed, 0 : not closed.
00973   * @retval None
00974   */
00975 static void LCD_PolyLineRelativeClosed(pPoint Points, uint16_t PointCount, uint16_t Closed)
00976 {
00977   int16_t X = 0, Y = 0;
00978   pPoint First = Points;
00979
00980   if(PointCount < 2)
00981   {
00982     return;
00983   }
00984   X = Points->X;
00985   Y = Points->Y;
00986   while(--PointCount)
00987   {
00988     Points++;
00989     LCD_DrawUniLine(X, Y, X + Points->X, Y + Points->Y);
00990     X = X + Points->X;
00991     Y = Y + Points->Y;
00992   }
00993   if(Closed)
00994   {
00995     LCD_DrawUniLine(First->X, First->Y, X, Y);
00996   }
00997 }
00998
00999 /**
01000   * @brief  Displays a closed polyline (between many points).
01001   * @param  Points: pointer to the points array.
01002   * @param  PointCount: Number of points.
01003   * @retval None
01004   */
01005 void LCD_ClosedPolyLine(pPoint Points, uint16_t PointCount)
01006 {
01007   LCD_PolyLine(Points, PointCount);
01008   LCD_DrawUniLine(Points->X, Points->Y, (Points+PointCount-1)->X, (Points+PointCount-1)->Y);
01009 }
01010
01011 /**
01012   * @brief  Displays a relative polyline (between many points).
01013   * @param  Points: pointer to the points array.
01014   * @param  PointCount: Number of points.
01015   * @retval None
01016   */
01017 void LCD_PolyLineRelative(pPoint Points, uint16_t PointCount)
01018 {
01019   LCD_PolyLineRelativeClosed(Points, PointCount, 0);
01020 }
01021
01022 /**
01023   * @brief  Displays a closed relative polyline (between many points).
01024   * @param  Points: pointer to the points array.
01025   * @param  PointCount: Number of points.
01026   * @retval None
01027   */
01028 void LCD_ClosedPolyLineRelative(pPoint Points, uint16_t PointCount)
01029 {
01030   LCD_PolyLineRelativeClosed(Points, PointCount, 1);
01031 }
01032
01033
01034 /**
01035   * @brief  Displays a  full polyline (between many points).
01036   * @param  Points: pointer to the points array.
01037   * @param  PointCount: Number of points.
01038   * @retval None
01039   */
01040 void LCD_FillPolyLine(pPoint Points, uint16_t PointCount)
01041 {
01042   /*  public-domain code by Darel Rex Finley, 2007 */
01043   uint16_t  nodes = 0, nodeX[MAX_POLY_CORNERS], pixelX = 0, pixelY = 0, i = 0,
01044   j = 0, swap = 0;
01045   uint16_t  IMAGE_LEFT = 0, IMAGE_RIGHT = 0, IMAGE_TOP = 0, IMAGE_BOTTOM = 0;
01046
01047   IMAGE_LEFT = IMAGE_RIGHT = Points->X;
01048   IMAGE_TOP= IMAGE_BOTTOM = Points->Y;
01049
01050   for(i = 1; i < PointCount; i++)
01051   {
01052     pixelX = POLY_X(i);
01053     if(pixelX < IMAGE_LEFT)
01054     {
01055       IMAGE_LEFT = pixelX;
01056     }
01057     if(pixelX > IMAGE_RIGHT)
01058     {
01059       IMAGE_RIGHT = pixelX;
01060     }
01061
01062     pixelY = POLY_Y(i);
01063     if(pixelY < IMAGE_TOP)
01064     {
01065       IMAGE_TOP = pixelY;
01066     }
01067     if(pixelY > IMAGE_BOTTOM)
01068     {
01069       IMAGE_BOTTOM = pixelY;
01070     }
01071   }
01072
01073   LCD_SetTextColor(BackColor);
01074
01075   /*  Loop through the rows of the image. */
01076   for (pixelY = IMAGE_TOP; pixelY < IMAGE_BOTTOM; pixelY++)
01077   {
01078     /* Build a list of nodes. */
01079     nodes = 0; j = PointCount-1;
01080
01081     for (i = 0; i < PointCount; i++)
01082     {
01083       if (POLY_Y(i)<(double) pixelY && POLY_Y(j)>=(double) pixelY || POLY_Y(j)<(double) pixelY && POLY_Y(i)>=(double) pixelY)
01084       {
01085         nodeX[nodes++]=(int) (POLY_X(i)+((pixelY-POLY_Y(i))*(POLY_X(j)-POLY_X(i)))/(POLY_Y(j)-POLY_Y(i)));
01086       }
01087       j = i;
01088     }
01089
01090     /* Sort the nodes, via a simple "Bubble" sort. */
01091     i = 0;
01092     while (i < nodes-1)
01093     {
01094       if (nodeX[i]>nodeX[i+1])
01095       {
01096         swap = nodeX[i];
01097         nodeX[i] = nodeX[i+1];
01098         nodeX[i+1] = swap;
01099         if(i)
01100         {
01101           i--;
01102         }
01103       }
01104       else
01105       {
01106         i++;
01107       }
01108     }
01109
01110     /*  Fill the pixels between node pairs. */
01111     for (i = 0; i < nodes; i+=2)
01112     {
01113       if(nodeX[i] >= IMAGE_RIGHT)
01114       {
01115         break;
01116       }
01117       if(nodeX[i+1] > IMAGE_LEFT)
01118       {
01119         if (nodeX[i] < IMAGE_LEFT)
01120         {
01121           nodeX[i]=IMAGE_LEFT;
01122         }
01123         if(nodeX[i+1] > IMAGE_RIGHT)
01124         {
01125           nodeX[i+1] = IMAGE_RIGHT;
01126         }
01127         LCD_SetTextColor(BackColor);
01128         LCD_DrawLine(pixelY, nodeX[i+1], nodeX[i+1] - nodeX[i], LCD_DIR_HORIZONTAL);
01129         LCD_SetTextColor(TextColor);
01130         PutPixel(pixelY, nodeX[i+1]);
01131         PutPixel(pixelY, nodeX[i]);
01132         /* for (j=nodeX[i]; j<nodeX[i+1]; j++) PutPixel(j,pixelY); */
01133       }
01134     }
01135   }
01136
01137   /* draw the edges */
01138   LCD_SetTextColor(TextColor);
01139 }
01140
01141 /**
01142   * @brief  Reset LCD control line(/CS) and Send Start-Byte
01143   * @param  Start_Byte: the Start-Byte to be sent
01144   * @retval None
01145   */
01146 void LCD_nCS_StartByte(uint8_t Start_Byte)
01147 {
01148   LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_RESET);
01149
01150   SPI_SendData(LCD_SPI, Start_Byte);
01151
01152   while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_BSY) != RESET)
01153   {
01154   }
01155 }
01156
01157
01158 /**
01159   * @brief  Writes index to select the LCD register.
01160   * @param  LCD_Reg: address of the selected register.
01161   * @retval None
01162   */
01163 void LCD_WriteRegIndex(uint8_t LCD_Reg)
01164 {
01165   /* Reset LCD control line(/CS) and Send Start-Byte */
01166   LCD_nCS_StartByte(START_BYTE | SET_INDEX);
01167
01168   /* Write 16-bit Reg Index (High Byte is 0) */
01169   SPI_SendData(LCD_SPI, 0x00);
01170
01171   while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_BSY) != RESET)
01172   {
01173   }
01174
01175   SPI_SendData(LCD_SPI, LCD_Reg);
01176
01177   while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_BSY) != RESET)
01178   {
01179   }
01180
01181   LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
01182 }
01183
01184
01185 /**
01186   * @brief  Writes to the selected LCD ILI9320 register.
01187   * @param  LCD_Reg: address of the selected register.
01188   * @param  LCD_RegValue: value to write to the selected register.
01189   * @retval None
01190   */
01191 void LCD_WriteReg(uint8_t LCD_Reg, uint16_t LCD_RegValue)
01192 {
01193   /* Write 16-bit Index (then Write Reg) */
01194   LCD_WriteRegIndex(LCD_Reg);
01195
01196   /* Write 16-bit Reg */
01197   /* Reset LCD control line(/CS) and Send Start-Byte */
01198   LCD_nCS_StartByte(START_BYTE | LCD_WRITE_REG);
01199
01200   SPI_SendData(LCD_SPI, LCD_RegValue >> 8);
01201
01202   while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_BSY) != RESET)
01203   {
01204   }
01205
01206   SPI_SendData(LCD_SPI, (LCD_RegValue & 0xFF));
01207
01208   while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_BSY) != RESET)
01209   {
01210   }
01211
01212   LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
01213 }
01214
01215
01216 /**
01217   * @brief  Reads the selected LCD Register.
01218   * @param  LCD_Reg: address of the selected register.
01219   * @retval LCD Register Value.
01220   */
01221 uint16_t LCD_ReadReg(uint8_t LCD_Reg)
01222 {
01223   uint16_t tmp = 0;
01224   uint8_t i = 0;
01225
01226   /* LCD_SPI prescaler: 4 */
01227   LCD_SPI->CR1 &= 0xFFC7;
01228   LCD_SPI->CR1 |= 0x0008;
01229   /* Write 16-bit Index (then Read Reg) */
01230   LCD_WriteRegIndex(LCD_Reg);
01231   /* Read 16-bit Reg */
01232   /* Reset LCD control line(/CS) and Send Start-Byte */
01233   LCD_nCS_StartByte(START_BYTE | LCD_READ_REG);
01234
01235   for(i = 0; i < 5; i++)
01236   {
01237     SPI_SendData(LCD_SPI, 0xFF);
01238     while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_BSY) != RESET)
01239     {
01240     }
01241     /* One byte of invalid dummy data read after the start byte */
01242     while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_RXNE) == RESET)
01243     {
01244     }
01245     SPI_ReceiveData(LCD_SPI);
01246   }
01247
01248   SPI_SendData(LCD_SPI, 0xFF);
01249
01250   /* Read upper byte */
01251   while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_BSY) != RESET)
01252   {
01253   }
01254
01255   /* Read lower byte */
01256   while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_RXNE) == RESET)
01257   {
01258   }
01259   tmp = SPI_ReceiveData(LCD_SPI);
01260
01261
01262   SPI_SendData(LCD_SPI, 0xFF);
01263   while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_BSY) != RESET)
01264   {
01265   }
01266
01267   /* Read lower byte */
01268   while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_RXNE) == RESET)
01269   {
01270   }
01271
01272   tmp = ((tmp & 0xFF) << 8) | SPI_ReceiveData(LCD_SPI);
01273   LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
01274
01275   /* LCD_SPI prescaler: 2 */
01276   LCD_SPI->CR1 &= 0xFFC7;
01277
01278   return tmp;
01279 }
01280
01281
01282 /**
01283   * @brief  Prepare to write to the LCD RAM.
01284   * @param  None
01285   * @retval None
01286   */
01287 void LCD_WriteRAM_Prepare(void)
01288 {
01289   LCD_WriteRegIndex(LCD_REG_34); /* Select GRAM Reg */
01290
01291   /* Reset LCD control line(/CS) and Send Start-Byte */
01292   LCD_nCS_StartByte(START_BYTE | LCD_WRITE_REG);
01293 }
01294
01295
01296 /**
01297   * @brief  Writes 1 word to the LCD RAM.
01298   * @param  RGB_Code: the pixel color in RGB mode (5-6-5).
01299   * @retval None
01300   */
01301 void LCD_WriteRAMWord(uint16_t RGB_Code)
01302 {
01303   LCD_WriteRAM_Prepare();
01304
01305   LCD_WriteRAM(RGB_Code);
01306
01307   LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
01308 }
01309
01310 /**
01311   * @brief  Writes to the LCD RAM.
01312   * @param  RGB_Code: the pixel color in RGB mode (5-6-5).
01313   * @retval None
01314   */
01315 void LCD_WriteRAM(uint16_t RGB_Code)
01316 {
01317   SPI_SendData(LCD_SPI, RGB_Code >> 8);
01318   while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_BSY) != RESET)
01319   {
01320   }
01321   SPI_SendData(LCD_SPI, RGB_Code & 0xFF);
01322   while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_BSY) != RESET)
01323   {
01324   }
01325 }
01326
01327
01328 /**
01329   * @brief  Power on the LCD.
01330   * @param  None
01331   * @retval None
01332   */
01333 void LCD_PowerOn(void)
01334 {
01335   /* Power On sequence ---------------------------------------------------------*/
01336   LCD_WriteReg(LCD_REG_16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
01337   LCD_WriteReg(LCD_REG_17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */
01338   LCD_WriteReg(LCD_REG_18, 0x0000); /* VREG1OUT voltage */
01339   LCD_WriteReg(LCD_REG_19, 0x0000); /* VDV[4:0] for VCOM amplitude */
01340   _delay_(20);                 /* Dis-charge capacitor power voltage (200ms) */
01341   LCD_WriteReg(LCD_REG_16, 0x17B0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
01342   LCD_WriteReg(LCD_REG_17, 0x0137); /* DC1[2:0], DC0[2:0], VC[2:0] */
01343   _delay_(5);                /* Delay 50 ms */
01344   LCD_WriteReg(LCD_REG_18, 0x0139); /* VREG1OUT voltage */
01345   _delay_(5);                /* delay 50 ms */
01346   LCD_WriteReg(LCD_REG_19, 0x1d00); /* VDV[4:0] for VCOM amplitude */
01347   LCD_WriteReg(LCD_REG_41, 0x0013); /* VCM[4:0] for VCOMH */
01348   _delay_(5);                /* delay 50 ms */
01349   LCD_WriteReg(LCD_REG_7, 0x0173);  /* 262K color and display ON */
01350 }
01351
01352
01353 /**
01354   * @brief  Enables the Display.
01355   * @param  None
01356   * @retval None
01357   */
01358 void LCD_DisplayOn(void)
01359 {
01360   /* Display On */
01361   LCD_WriteReg(LCD_REG_7, 0x0173); /* 262K color and display ON */
01362 }
01363
01364
01365 /**
01366   * @brief  Disables the Display.
01367   * @param  None
01368   * @retval None
01369   */
01370 void LCD_DisplayOff(void)
01371 {
01372   /* Display Off */
01373   LCD_WriteReg(LCD_REG_7, 0x0);
01374 }
01375
01376
01377 /**
01378   * @brief  Configures LCD control lines in Output Push-Pull mode.
01379   * @param  None
01380   * @retval None
01381   */
01382 void LCD_CtrlLinesConfig(void)
01383 {
01384   GPIO_InitTypeDef GPIO_InitStructure;
01385
01386   RCC_AHBPeriphClockCmd(LCD_NCS_GPIO_CLK, ENABLE);
01387
01388   /* Configure NCS (PF.02) in Output Push-Pull mode */
01389   GPIO_InitStructure.GPIO_Pin = LCD_NCS_PIN;
01390   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
01391   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
01392   GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
01393   GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
01394   GPIO_Init(LCD_NCS_GPIO_PORT, &GPIO_InitStructure);
01395
01396   LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
01397 }
01398
01399
01400 /**
01401   * @brief  Sets or reset LCD control lines.
01402   * @param  GPIOx: where x can be B or D to select the GPIO peripheral.
01403   * @param  CtrlPins: the Control line.
01404   *   This parameter can be:
01405   *     @arg LCD_NCS_PIN: Chip Select pin
01406   *     @arg LCD_NWR_PIN: Read/Write Selection pin
01407   *     @arg LCD_RS_PIN: Register/RAM Selection pin
01408   * @param  BitVal: specifies the value to be written to the selected bit.
01409   *   This parameter can be:
01410   *     @arg Bit_RESET: to clear the port pin
01411   *     @arg Bit_SET: to set the port pin
01412   * @retval None
01413   */
01414 void LCD_CtrlLinesWrite(GPIO_TypeDef* GPIOx, uint16_t CtrlPins, BitAction BitVal)
01415 {
01416   /* Set or Reset the control line */
01417   GPIO_WriteBit(GPIOx, CtrlPins, BitVal);
01418 }
01419
01420
01421 /**
01422   * @brief  Configures the LCD_SPI interface.
01423   * @param  None
01424   * @retval None
01425   */
01426 void LCD_SPIConfig(void)
01427 {
01428   SPI_InitTypeDef    SPI_InitStructure;
01429   GPIO_InitTypeDef   GPIO_InitStructure;
01430
01431   /* Enable LCD_SPI_SCK_GPIO_CLK, LCD_SPI_MISO_GPIO_CLK and LCD_SPI_MOSI_GPIO_CLK clock */
01432   RCC_AHBPeriphClockCmd(LCD_SPI_SCK_GPIO_CLK | LCD_SPI_MISO_GPIO_CLK | LCD_SPI_MOSI_GPIO_CLK, ENABLE);
01433
01434   /* Enable LCD_SPI and SYSCFG clock  */
01435   RCC_APB2PeriphClockCmd(LCD_SPI_CLK | RCC_APB2Periph_SYSCFG, ENABLE);
01436
01437   /* Configure LCD_SPI SCK pin */
01438   GPIO_InitStructure.GPIO_Pin = LCD_SPI_SCK_PIN;
01439   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_40MHz;
01440   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
01441   GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
01442   GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
01443   GPIO_Init(LCD_SPI_SCK_GPIO_PORT, &GPIO_InitStructure);
01444
01445   /* Configure LCD_SPI MISO pin */
01446   GPIO_InitStructure.GPIO_Pin = LCD_SPI_MISO_PIN;
01447   GPIO_Init(LCD_SPI_MISO_GPIO_PORT, &GPIO_InitStructure);
01448
01449   /* Configure LCD_SPI MOSI pin */
01450   GPIO_InitStructure.GPIO_Pin = LCD_SPI_MOSI_PIN;
01451   GPIO_Init(LCD_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure);
01452
01453   /* Connect PE.13 to SPI SCK */
01454   GPIO_PinAFConfig(LCD_SPI_SCK_GPIO_PORT, LCD_SPI_SCK_SOURCE, LCD_SPI_SCK_AF);
01455
01456   /* Connect PE.14 to SPI MISO */
01457   GPIO_PinAFConfig(LCD_SPI_MISO_GPIO_PORT, LCD_SPI_MISO_SOURCE, LCD_SPI_MISO_AF);
01458
01459   /* Connect PE.15 to SPI MOSI */
01460   GPIO_PinAFConfig(LCD_SPI_MOSI_GPIO_PORT, LCD_SPI_MOSI_SOURCE, LCD_SPI_MOSI_AF);
01461
01462   SPI_DeInit(LCD_SPI);
01463
01464   /* SPI Config */
01465   SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
01466   SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
01467   SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
01468   SPI_InitStructure.SPI_CPOL = SPI_CPOL_High;
01469   SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge;
01470   SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
01471   SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
01472   SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
01473   SPI_InitStructure.SPI_CRCPolynomial = 7;
01474   SPI_Init(LCD_SPI, &SPI_InitStructure);
01475
01476   /* SPI enable */
01477   SPI_Cmd(LCD_SPI, ENABLE);
01478 }
01479
01480 /**
01481   * @brief  Displays a pixel.
01482   * @param  x: pixel x.
01483   * @param  y: pixel y.
01484   * @retval None
01485   */
01486 static void PutPixel(int16_t x, int16_t y)
01487 {
01488   if(x < 0 || x > 239 || y < 0 || y > 319)
01489   {
01490     return;
01491   }
01492   LCD_DrawLine(x, y, 1, LCD_DIR_HORIZONTAL);
01493 }
01494
01495 #ifndef USE_Delay
01496 /**
01497   * @brief  Inserts a delay time.
01498   * @param  nCount: specifies the delay time length.
01499   * @retval None
01500   */
01501 static void delay(__IO uint32_t nCount)
01502 {
01503   __IO uint32_t index = 0;
01504   for(index = (34000 * nCount); index != 0; index--)
01505   {
01506   }
01507 }
01508 #endif /* USE_Delay*/
01509 /**
01510   * @}
01511   */
01512
01513 /**
01514   * @}
01515   */
01516
01517 /**
01518   * @}
01519   */
01520
01521 /**
01522   * @}
01523   */
01524
01525 /**
01526   * @}
01527   */
01528
01529 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32l152_eval_lcd.h Source File

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  • STM32L152_EVAL

stm32l152_eval_lcd.h

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l152_eval_lcd.h
00004   * @author  MCD Application Team
00005   * @version V4.5.0
00006   * @date    07-March-2011
00007   * @brief   This file contains all the functions prototypes for the stm32l152_eval_lcd
00008   *          firmware driver.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00013   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00014   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00015   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00016   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00017   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00018   *
00019   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00020   ******************************************************************************
00021   */
00022
00023 /* Define to prevent recursive inclusion -------------------------------------*/
00024 #ifndef __STM32L152_EVAL_LCD_H
00025 #define __STM32L152_EVAL_LCD_H
00026
00027 #ifdef __cplusplus
00028  extern "C" {
00029 #endif
00030
00031 /* Includes ------------------------------------------------------------------*/
00032 #include "stm32l1xx.h"
00033 #include "../Common/fonts.h"
00034
00035 /** @addtogroup Utilities
00036   * @{
00037   */
00038
00039 /** @addtogroup STM32_EVAL
00040   * @{
00041   */
00042
00043 /** @addtogroup STM32L152_EVAL
00044   * @{
00045   */
00046
00047 /** @addtogroup STM32L152_EVAL_LCD
00048   * @{
00049   */
00050
00051
00052 /** @defgroup STM32L152_EVAL_LCD_Exported_Types
00053   * @{
00054   */
00055 typedef struct
00056 {
00057   int16_t X;
00058   int16_t Y;
00059 } Point, * pPoint;
00060 /**
00061   * @}
00062   */
00063
00064 /** @defgroup STM32L152_EVAL_LCD_Exported_Constants
00065   * @{
00066   */
00067
00068 /**
00069  * @brief Uncomment the line below if you want to use LCD_DrawBMP function to
00070  *        display a bitmap picture on the LCD. This function assumes that the bitmap
00071  *        file is loaded in the SPI Flash (mounted on STM32L152-EVAL board), however
00072  *        user can tailor it according to his application hardware requirement.
00073  */
00074 /*#define USE_LCD_DrawBMP*/
00075
00076 /**
00077  * @brief Uncomment the line below if you want to use user defined Delay function
00078  *        (for precise timing), otherwise default _delay_ function defined within
00079  *         this driver is used (less precise timing).
00080  */
00081 /* #define USE_Delay */
00082
00083 #ifdef USE_Delay
00084 #include "main.h"
00085
00086   #define _delay_     Delay  /* !< User can provide more timing precise _delay_ function
00087                                    (with 10ms time base), using SysTick for example */
00088 #else
00089   #define _delay_     delay      /* !< Default _delay_ function with less precise timing */
00090 #endif
00091
00092
00093 /**
00094   * @brief  LCD Control pins
00095   */
00096 #define LCD_NCS_PIN             GPIO_Pin_2
00097 #define LCD_NCS_GPIO_PORT       GPIOH
00098 #define LCD_NCS_GPIO_CLK        RCC_AHBPeriph_GPIOH
00099
00100 /**
00101   * @brief  LCD SPI Interface pins
00102   */
00103 #define LCD_SPI_SCK_PIN               GPIO_Pin_13                    /* PE.13 */
00104 #define LCD_SPI_SCK_GPIO_PORT         GPIOE                          /* GPIOE */
00105 #define LCD_SPI_SCK_GPIO_CLK          RCC_AHBPeriph_GPIOE
00106 #define LCD_SPI_SCK_SOURCE            GPIO_PinSource13
00107 #define LCD_SPI_SCK_AF                GPIO_AF_SPI1
00108 #define LCD_SPI_MISO_PIN              GPIO_Pin_14                    /* PE.14 */
00109 #define LCD_SPI_MISO_GPIO_PORT        GPIOE                          /* GPIOE */
00110 #define LCD_SPI_MISO_GPIO_CLK         RCC_AHBPeriph_GPIOE
00111 #define LCD_SPI_MISO_SOURCE           GPIO_PinSource14
00112 #define LCD_SPI_MISO_AF               GPIO_AF_SPI1
00113 #define LCD_SPI_MOSI_PIN              GPIO_Pin_15                    /* PE.15 */
00114 #define LCD_SPI_MOSI_GPIO_PORT        GPIOE                          /* GPIOE */
00115 #define LCD_SPI_MOSI_GPIO_CLK         RCC_AHBPeriph_GPIOE
00116 #define LCD_SPI_MOSI_SOURCE           GPIO_PinSource15
00117 #define LCD_SPI_MOSI_AF               GPIO_AF_SPI1
00118 #define LCD_SPI                       SPI1
00119 #define LCD_SPI_CLK                   RCC_APB2Periph_SPI1
00120
00121
00122 /**
00123   * @brief  LCD Registers
00124   */
00125 #define LCD_REG_0             0x00
00126 #define LCD_REG_1             0x01
00127 #define LCD_REG_2             0x02
00128 #define LCD_REG_3             0x03
00129 #define LCD_REG_4             0x04
00130 #define LCD_REG_5             0x05
00131 #define LCD_REG_6             0x06
00132 #define LCD_REG_7             0x07
00133 #define LCD_REG_8             0x08
00134 #define LCD_REG_9             0x09
00135 #define LCD_REG_10            0x0A
00136 #define LCD_REG_12            0x0C
00137 #define LCD_REG_13            0x0D
00138 #define LCD_REG_14            0x0E
00139 #define LCD_REG_15            0x0F
00140 #define LCD_REG_16            0x10
00141 #define LCD_REG_17            0x11
00142 #define LCD_REG_18            0x12
00143 #define LCD_REG_19            0x13
00144 #define LCD_REG_20            0x14
00145 #define LCD_REG_21            0x15
00146 #define LCD_REG_22            0x16
00147 #define LCD_REG_23            0x17
00148 #define LCD_REG_24            0x18
00149 #define LCD_REG_25            0x19
00150 #define LCD_REG_26            0x1A
00151 #define LCD_REG_27            0x1B
00152 #define LCD_REG_28            0x1C
00153 #define LCD_REG_29            0x1D
00154 #define LCD_REG_30            0x1E
00155 #define LCD_REG_31            0x1F
00156 #define LCD_REG_32            0x20
00157 #define LCD_REG_33            0x21
00158 #define LCD_REG_34            0x22
00159 #define LCD_REG_36            0x24
00160 #define LCD_REG_37            0x25
00161 #define LCD_REG_40            0x28
00162 #define LCD_REG_41            0x29
00163 #define LCD_REG_43            0x2B
00164 #define LCD_REG_45            0x2D
00165 #define LCD_REG_48            0x30
00166 #define LCD_REG_49            0x31
00167 #define LCD_REG_50            0x32
00168 #define LCD_REG_51            0x33
00169 #define LCD_REG_52            0x34
00170 #define LCD_REG_53            0x35
00171 #define LCD_REG_54            0x36
00172 #define LCD_REG_55            0x37
00173 #define LCD_REG_56            0x38
00174 #define LCD_REG_57            0x39
00175 #define LCD_REG_59            0x3B
00176 #define LCD_REG_60            0x3C
00177 #define LCD_REG_61            0x3D
00178 #define LCD_REG_62            0x3E
00179 #define LCD_REG_63            0x3F
00180 #define LCD_REG_64            0x40
00181 #define LCD_REG_65            0x41
00182 #define LCD_REG_66            0x42
00183 #define LCD_REG_67            0x43
00184 #define LCD_REG_68            0x44
00185 #define LCD_REG_69            0x45
00186 #define LCD_REG_70            0x46
00187 #define LCD_REG_71            0x47
00188 #define LCD_REG_72            0x48
00189 #define LCD_REG_73            0x49
00190 #define LCD_REG_74            0x4A
00191 #define LCD_REG_75            0x4B
00192 #define LCD_REG_76            0x4C
00193 #define LCD_REG_77            0x4D
00194 #define LCD_REG_78            0x4E
00195 #define LCD_REG_79            0x4F
00196 #define LCD_REG_80            0x50
00197 #define LCD_REG_81            0x51
00198 #define LCD_REG_82            0x52
00199 #define LCD_REG_83            0x53
00200 #define LCD_REG_96            0x60
00201 #define LCD_REG_97            0x61
00202 #define LCD_REG_106           0x6A
00203 #define LCD_REG_118           0x76
00204 #define LCD_REG_128           0x80
00205 #define LCD_REG_129           0x81
00206 #define LCD_REG_130           0x82
00207 #define LCD_REG_131           0x83
00208 #define LCD_REG_132           0x84
00209 #define LCD_REG_133           0x85
00210 #define LCD_REG_134           0x86
00211 #define LCD_REG_135           0x87
00212 #define LCD_REG_136           0x88
00213 #define LCD_REG_137           0x89
00214 #define LCD_REG_139           0x8B
00215 #define LCD_REG_140           0x8C
00216 #define LCD_REG_141           0x8D
00217 #define LCD_REG_143           0x8F
00218 #define LCD_REG_144           0x90
00219 #define LCD_REG_145           0x91
00220 #define LCD_REG_146           0x92
00221 #define LCD_REG_147           0x93
00222 #define LCD_REG_148           0x94
00223 #define LCD_REG_149           0x95
00224 #define LCD_REG_150           0x96
00225 #define LCD_REG_151           0x97
00226 #define LCD_REG_152           0x98
00227 #define LCD_REG_153           0x99
00228 #define LCD_REG_154           0x9A
00229 #define LCD_REG_157           0x9D
00230 #define LCD_REG_192           0xC0
00231 #define LCD_REG_193           0xC1
00232 #define LCD_REG_227           0xE3
00233 #define LCD_REG_229           0xE5
00234 #define LCD_REG_231           0xE7
00235 #define LCD_REG_239           0xEF
00236
00237
00238 /**
00239   * @brief  LCD color
00240   */
00241 #define LCD_COLOR_WHITE          0xFFFF
00242 #define LCD_COLOR_BLACK          0x0000
00243 #define LCD_COLOR_GREY           0xF7DE
00244 #define LCD_COLOR_BLUE           0x001F
00245 #define LCD_COLOR_BLUE2          0x051F
00246 #define LCD_COLOR_RED            0xF800
00247 #define LCD_COLOR_MAGENTA        0xF81F
00248 #define LCD_COLOR_GREEN          0x07E0
00249 #define LCD_COLOR_CYAN           0x7FFF
00250 #define LCD_COLOR_YELLOW         0xFFE0
00251
00252 /**
00253   * @brief  LCD Lines depending on the chosen fonts.
00254   */
00255 #define LCD_LINE_0               LINE(0)
00256 #define LCD_LINE_1               LINE(1)
00257 #define LCD_LINE_2               LINE(2)
00258 #define LCD_LINE_3               LINE(3)
00259 #define LCD_LINE_4               LINE(4)
00260 #define LCD_LINE_5               LINE(5)
00261 #define LCD_LINE_6               LINE(6)
00262 #define LCD_LINE_7               LINE(7)
00263 #define LCD_LINE_8               LINE(8)
00264 #define LCD_LINE_9               LINE(9)
00265 #define LCD_LINE_10              LINE(10)
00266 #define LCD_LINE_11              LINE(11)
00267 #define LCD_LINE_12              LINE(12)
00268 #define LCD_LINE_13              LINE(13)
00269 #define LCD_LINE_14              LINE(14)
00270 #define LCD_LINE_15              LINE(15)
00271 #define LCD_LINE_16              LINE(16)
00272 #define LCD_LINE_17              LINE(17)
00273 #define LCD_LINE_18              LINE(18)
00274 #define LCD_LINE_19              LINE(19)
00275 #define LCD_LINE_20              LINE(20)
00276 #define LCD_LINE_21              LINE(21)
00277 #define LCD_LINE_22              LINE(22)
00278 #define LCD_LINE_23              LINE(23)
00279 #define LCD_LINE_24              LINE(24)
00280 #define LCD_LINE_25              LINE(25)
00281 #define LCD_LINE_26              LINE(26)
00282 #define LCD_LINE_27              LINE(27)
00283 #define LCD_LINE_28              LINE(28)
00284 #define LCD_LINE_29              LINE(29)
00285
00286
00287 /**
00288   * @brief LCD default font
00289   */
00290 #define LCD_DEFAULT_FONT         Font16x24
00291
00292 /**
00293   * @brief  LCD Direction
00294   */
00295 #define LCD_DIR_HORIZONTAL       0x0000
00296 #define LCD_DIR_VERTICAL         0x0001
00297
00298 /**
00299   * @brief  LCD Size (Width and Height)
00300   */
00301 #define LCD_PIXEL_WIDTH          0x0140
00302 #define LCD_PIXEL_HEIGHT         0x00F0
00303
00304 /**
00305   * @}
00306   */
00307
00308 /** @defgroup STM32L152_EVAL_LCD_Exported_Macros
00309   * @{
00310   */
00311 #define ASSEMBLE_RGB(R, G, B)    ((((R)& 0xF8) << 8) | (((G) & 0xFC) << 3) | (((B) & 0xF8) >> 3))
00312
00313 /**
00314   * @}
00315   */
00316
00317 /** @defgroup STM32L152_EVAL_LCD_Exported_Functions
00318   * @{
00319   */
00320 void STM32L152_LCD_DeInit(void);
00321 void LCD_Setup(void);
00322 void STM32L152_LCD_Init(void);
00323 void LCD_SetColors(__IO uint16_t _TextColor, __IO uint16_t _BackColor);
00324 void LCD_GetColors(__IO uint16_t *_TextColor, __IO uint16_t *_BackColor);
00325 void LCD_SetTextColor(__IO uint16_t Color);
00326 void LCD_SetBackColor(__IO uint16_t Color);
00327 void LCD_ClearLine(uint8_t Line);
00328 void LCD_Clear(uint16_t Color);
00329 void LCD_SetCursor(uint8_t Xpos, uint16_t Ypos);
00330 void LCD_DrawChar(uint8_t Xpos, uint16_t Ypos, const uint16_t *c);
00331 void LCD_DisplayChar(uint8_t Line, uint16_t Column, uint8_t Ascii);
00332 void LCD_SetFont(sFONT *fonts);
00333 sFONT *LCD_GetFont(void);
00334 void LCD_DisplayStringLine(uint8_t Line, uint8_t *ptr);
00335 void LCD_SetDisplayWindow(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width);
00336 void LCD_WindowModeDisable(void);
00337 void LCD_DrawLine(uint8_t Xpos, uint16_t Ypos, uint16_t Length, uint8_t Direction);
00338 void LCD_DrawRect(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width);
00339 void LCD_DrawCircle(uint8_t Xpos, uint16_t Ypos, uint16_t Radius);
00340 void LCD_DrawMonoPict(const uint32_t *Pict);
00341 void LCD_DrawBMP(uint32_t BmpAddress);
00342 void LCD_DrawUniLine(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2);
00343 void LCD_DrawFullRect(uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height);
00344 void LCD_DrawFullCircle(uint16_t Xpos, uint16_t Ypos, uint16_t Radius);
00345 void LCD_PolyLine(pPoint Points, uint16_t PointCount);
00346 void LCD_PolyLineRelative(pPoint Points, uint16_t PointCount);
00347 void LCD_ClosedPolyLine(pPoint Points, uint16_t PointCount);
00348 void LCD_ClosedPolyLineRelative(pPoint Points, uint16_t PointCount);
00349 void LCD_FillPolyLine(pPoint Points, uint16_t PointCount);
00350 void LCD_nCS_StartByte(uint8_t Start_Byte);
00351 void LCD_WriteRegIndex(uint8_t LCD_Reg);
00352 void LCD_WriteReg(uint8_t LCD_Reg, uint16_t LCD_RegValue);
00353 void LCD_WriteRAM_Prepare(void);
00354 void LCD_WriteRAMWord(uint16_t RGB_Code);
00355 uint16_t LCD_ReadReg(uint8_t LCD_Reg);
00356 void LCD_WriteRAM(uint16_t RGB_Code);
00357 void LCD_PowerOn(void);
00358 void LCD_DisplayOn(void);
00359 void LCD_DisplayOff(void);
00360
00361 void LCD_CtrlLinesConfig(void);
00362 void LCD_CtrlLinesWrite(GPIO_TypeDef* GPIOx, uint16_t CtrlPins, BitAction BitVal);
00363 void LCD_SPIConfig(void);
00364
00365 /**
00366   * @}
00367   */
00368
00369 #ifdef __cplusplus
00370 }
00371 #endif
00372
00373 #endif /* __STM32L152_EVAL_LCD_H */
00374
00375
00376 /**
00377   * @}
00378   */
00379
00380 /**
00381   * @}
00382   */
00383
00384 /**
00385   * @}
00386   */
00387
00388 /**
00389   * @}
00390   */
00391
00392 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm3210b_eval.c Source File

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  • Utilities
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  • STM3210B_EVAL

stm3210b_eval.c

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00001 /**
00002   ******************************************************************************
00003   * @file    stm3210b_eval.c
00004   * @author  MCD Application Team
00005   * @version V4.5.0
00006   * @date    07-March-2011
00007   * @brief   This file provides
00008   *            - set of firmware functions to manage Leds, push-button and COM ports
00009   *            - low level initialization functions for SD card (on SPI), SPI serial
00010   *              flash (sFLASH) and temperature sensor (LM75)
00011   *          available on STM3210B-EVAL evaluation board from STMicroelectronics.
00012   ******************************************************************************
00013   * @attention
00014   *
00015   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00016   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00017   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00018   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00019   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00020   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00021   *
00022   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00023   ******************************************************************************
00024   */
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm3210b_eval.h"
00028
00029 /** @addtogroup Utilities
00030   * @{
00031   */
00032
00033 /** @addtogroup STM32_EVAL
00034   * @{
00035   */
00036
00037 /** @addtogroup STM3210B_EVAL
00038   * @{
00039   */
00040
00041 /** @defgroup STM3210B_EVAL_LOW_LEVEL
00042   * @brief This file provides firmware functions to manage Leds, push-buttons,
00043   *        COM ports, SD card on SPI, serial flash (sFLASH), serial EEPROM (sEE)
00044   *        and temperature sensor (LM75) available on STM3210B-EVAL evaluation
00045   *        board from STMicroelectronics.
00046   * @{
00047   */
00048
00049 /** @defgroup STM3210B_EVAL_LOW_LEVEL_Private_TypesDefinitions
00050   * @{
00051   */
00052 /**
00053   * @}
00054   */
00055
00056
00057 /** @defgroup STM3210B_EVAL_LOW_LEVEL_Private_Defines
00058   * @{
00059   */
00060 /**
00061   * @}
00062   */
00063
00064
00065 /** @defgroup STM3210B_EVAL_LOW_LEVEL_Private_Macros
00066   * @{
00067   */
00068 /**
00069   * @}
00070   */
00071
00072
00073 /** @defgroup STM3210B_EVAL_LOW_LEVEL_Private_Variables
00074   * @{
00075   */
00076 GPIO_TypeDef* GPIO_PORT[LEDn] = {LED1_GPIO_PORT, LED2_GPIO_PORT, LED3_GPIO_PORT,
00077                                  LED4_GPIO_PORT};
00078 const uint16_t GPIO_PIN[LEDn] = {LED1_PIN, LED2_PIN, LED3_PIN,
00079                                  LED4_PIN};
00080 const uint32_t GPIO_CLK[LEDn] = {LED1_GPIO_CLK, LED2_GPIO_CLK, LED3_GPIO_CLK,
00081                                  LED4_GPIO_CLK};
00082
00083 GPIO_TypeDef* BUTTON_PORT[BUTTONn] = {WAKEUP_BUTTON_GPIO_PORT, TAMPER_BUTTON_GPIO_PORT,
00084                                       KEY_BUTTON_GPIO_PORT, RIGHT_BUTTON_GPIO_PORT,
00085                                       LEFT_BUTTON_GPIO_PORT, UP_BUTTON_GPIO_PORT,
00086                                       DOWN_BUTTON_GPIO_PORT, SEL_BUTTON_GPIO_PORT};
00087
00088 const uint16_t BUTTON_PIN[BUTTONn] = {WAKEUP_BUTTON_PIN, TAMPER_BUTTON_PIN,
00089                                       KEY_BUTTON_PIN, RIGHT_BUTTON_PIN,
00090                                       LEFT_BUTTON_PIN, UP_BUTTON_PIN,
00091                                       DOWN_BUTTON_PIN, SEL_BUTTON_PIN};
00092
00093 const uint32_t BUTTON_CLK[BUTTONn] = {WAKEUP_BUTTON_GPIO_CLK, TAMPER_BUTTON_GPIO_CLK,
00094                                       KEY_BUTTON_GPIO_CLK, RIGHT_BUTTON_GPIO_CLK,
00095                                       LEFT_BUTTON_GPIO_CLK, UP_BUTTON_GPIO_CLK,
00096                                       DOWN_BUTTON_GPIO_CLK, SEL_BUTTON_GPIO_CLK};
00097
00098 const uint16_t BUTTON_EXTI_LINE[BUTTONn] = {WAKEUP_BUTTON_EXTI_LINE,
00099                                             TAMPER_BUTTON_EXTI_LINE,
00100                                             KEY_BUTTON_EXTI_LINE,
00101                                             RIGHT_BUTTON_EXTI_LINE,
00102                                             LEFT_BUTTON_EXTI_LINE,
00103                                             UP_BUTTON_EXTI_LINE,
00104                                             DOWN_BUTTON_EXTI_LINE,
00105                                             SEL_BUTTON_EXTI_LINE};
00106
00107 const uint16_t BUTTON_PORT_SOURCE[BUTTONn] = {WAKEUP_BUTTON_EXTI_PORT_SOURCE,
00108                                               TAMPER_BUTTON_EXTI_PORT_SOURCE,
00109                                               KEY_BUTTON_EXTI_PORT_SOURCE,
00110                                               RIGHT_BUTTON_EXTI_PORT_SOURCE,
00111                                               LEFT_BUTTON_EXTI_PORT_SOURCE,
00112                                               UP_BUTTON_EXTI_PORT_SOURCE,
00113                                               DOWN_BUTTON_EXTI_PORT_SOURCE,
00114                                               SEL_BUTTON_EXTI_PORT_SOURCE};
00115
00116 const uint16_t BUTTON_PIN_SOURCE[BUTTONn] = {WAKEUP_BUTTON_EXTI_PIN_SOURCE,
00117                                              TAMPER_BUTTON_EXTI_PIN_SOURCE,
00118                                              KEY_BUTTON_EXTI_PIN_SOURCE,
00119                                              RIGHT_BUTTON_EXTI_PIN_SOURCE,
00120                                              LEFT_BUTTON_EXTI_PIN_SOURCE,
00121                                              UP_BUTTON_EXTI_PIN_SOURCE,
00122                                              DOWN_BUTTON_EXTI_PIN_SOURCE,
00123                                              SEL_BUTTON_EXTI_PIN_SOURCE};
00124
00125 const uint16_t BUTTON_IRQn[BUTTONn] = {WAKEUP_BUTTON_EXTI_IRQn, TAMPER_BUTTON_EXTI_IRQn,
00126                                        KEY_BUTTON_EXTI_IRQn, RIGHT_BUTTON_EXTI_IRQn,
00127                                        LEFT_BUTTON_EXTI_IRQn, UP_BUTTON_EXTI_IRQn,
00128                                        DOWN_BUTTON_EXTI_IRQn, SEL_BUTTON_EXTI_IRQn};
00129
00130 USART_TypeDef* COM_USART[COMn] = {EVAL_COM1, EVAL_COM2};
00131
00132 GPIO_TypeDef* COM_TX_PORT[COMn] = {EVAL_COM1_TX_GPIO_PORT, EVAL_COM2_TX_GPIO_PORT};
00133
00134 GPIO_TypeDef* COM_RX_PORT[COMn] = {EVAL_COM1_RX_GPIO_PORT, EVAL_COM2_RX_GPIO_PORT};
00135
00136 const uint32_t COM_USART_CLK[COMn] = {EVAL_COM1_CLK, EVAL_COM2_CLK};
00137
00138 const uint32_t COM_TX_PORT_CLK[COMn] = {EVAL_COM1_TX_GPIO_CLK, EVAL_COM2_TX_GPIO_CLK};
00139
00140 const uint32_t COM_RX_PORT_CLK[COMn] = {EVAL_COM1_RX_GPIO_CLK, EVAL_COM2_RX_GPIO_CLK};
00141
00142 const uint16_t COM_TX_PIN[COMn] = {EVAL_COM1_TX_PIN, EVAL_COM2_TX_PIN};
00143
00144 const uint16_t COM_RX_PIN[COMn] = {EVAL_COM1_RX_PIN, EVAL_COM2_RX_PIN};
00145
00146
00147 /**
00148   * @}
00149   */
00150
00151
00152 /** @defgroup STM3210B_EVAL_LOW_LEVEL_Private_FunctionPrototypes
00153   * @{
00154   */
00155
00156 /**
00157   * @}
00158   */
00159
00160
00161 /** @defgroup STM3210B_EVAL_LOW_LEVEL_Private_Functions
00162   * @{
00163   */
00164
00165 /**
00166   * @brief  Configures LED GPIO.
00167   * @param  Led: Specifies the Led to be configured.
00168   *   This parameter can be one of following parameters:
00169   *     @arg LED1
00170   *     @arg LED2
00171   *     @arg LED3
00172   *     @arg LED4
00173   * @retval None
00174   */
00175 void STM_EVAL_LEDInit(Led_TypeDef Led)
00176 {
00177   GPIO_InitTypeDef  GPIO_InitStructure;
00178
00179   /* Enable the GPIO_LED Clock */
00180   RCC_APB2PeriphClockCmd(GPIO_CLK[Led], ENABLE);
00181
00182   /* Configure the GPIO_LED pin */
00183   GPIO_InitStructure.GPIO_Pin = GPIO_PIN[Led];
00184   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
00185   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00186
00187   GPIO_Init(GPIO_PORT[Led], &GPIO_InitStructure);
00188 }
00189
00190 /**
00191   * @brief  Turns selected LED On.
00192   * @param  Led: Specifies the Led to be set on.
00193   *   This parameter can be one of following parameters:
00194   *     @arg LED1
00195   *     @arg LED2
00196   *     @arg LED3
00197   *     @arg LED4
00198   * @retval None
00199   */
00200 void STM_EVAL_LEDOn(Led_TypeDef Led)
00201 {
00202   GPIO_PORT[Led]->BSRR = GPIO_PIN[Led];
00203 }
00204
00205 /**
00206   * @brief  Turns selected LED Off.
00207   * @param  Led: Specifies the Led to be set off.
00208   *   This parameter can be one of following parameters:
00209   *     @arg LED1
00210   *     @arg LED2
00211   *     @arg LED3
00212   *     @arg LED4
00213   * @retval None
00214   */
00215 void STM_EVAL_LEDOff(Led_TypeDef Led)
00216 {
00217   GPIO_PORT[Led]->BRR = GPIO_PIN[Led];
00218 }
00219
00220 /**
00221   * @brief  Toggles the selected LED.
00222   * @param  Led: Specifies the Led to be toggled.
00223   *   This parameter can be one of following parameters:
00224   *     @arg LED1
00225   *     @arg LED2
00226   *     @arg LED3
00227   *     @arg LED4
00228   * @retval None
00229   */
00230 void STM_EVAL_LEDToggle(Led_TypeDef Led)
00231 {
00232   GPIO_PORT[Led]->ODR ^= GPIO_PIN[Led];
00233 }
00234
00235 /**
00236   * @brief  Configures Button GPIO and EXTI Line.
00237   * @param  Button: Specifies the Button to be configured.
00238   *   This parameter can be one of following parameters:
00239   *     @arg BUTTON_WAKEUP: Wakeup Push Button
00240   *     @arg BUTTON_TAMPER: Tamper Push Button
00241   *     @arg BUTTON_KEY: Key Push Button
00242   *     @arg BUTTON_RIGHT: Joystick Right Push Button
00243   *     @arg BUTTON_LEFT: Joystick Left Push Button
00244   *     @arg BUTTON_UP: Joystick Up Push Button
00245   *     @arg BUTTON_DOWN: Joystick Down Push Button
00246   *     @arg BUTTON_SEL: Joystick Sel Push Button
00247   * @param  Button_Mode: Specifies Button mode.
00248   *   This parameter can be one of following parameters:
00249   *     @arg BUTTON_MODE_GPIO: Button will be used as simple IO
00250   *     @arg BUTTON_MODE_EXTI: Button will be connected to EXTI line with interrupt
00251   *                     generation capability
00252   * @retval None
00253   */
00254 void STM_EVAL_PBInit(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode)
00255 {
00256   GPIO_InitTypeDef GPIO_InitStructure;
00257   EXTI_InitTypeDef EXTI_InitStructure;
00258   NVIC_InitTypeDef NVIC_InitStructure;
00259
00260   /* Enable the BUTTON Clock */
00261   RCC_APB2PeriphClockCmd(BUTTON_CLK[Button] | RCC_APB2Periph_AFIO, ENABLE);
00262
00263   /* Configure Button pin as input floating */
00264   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
00265   GPIO_InitStructure.GPIO_Pin = BUTTON_PIN[Button];
00266   GPIO_Init(BUTTON_PORT[Button], &GPIO_InitStructure);
00267
00268
00269   if (Button_Mode == BUTTON_MODE_EXTI)
00270   {
00271     /* Connect Button EXTI Line to Button GPIO Pin */
00272     GPIO_EXTILineConfig(BUTTON_PORT_SOURCE[Button], BUTTON_PIN_SOURCE[Button]);
00273
00274     /* Configure Button EXTI line */
00275     EXTI_InitStructure.EXTI_Line = BUTTON_EXTI_LINE[Button];
00276     EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
00277
00278     if(Button != BUTTON_WAKEUP)
00279     {
00280       EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling;
00281     }
00282     else
00283     {
00284       EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;
00285     }
00286     EXTI_InitStructure.EXTI_LineCmd = ENABLE;
00287     EXTI_Init(&EXTI_InitStructure);
00288
00289     /* Enable and set Button EXTI Interrupt to the lowest priority */
00290     NVIC_InitStructure.NVIC_IRQChannel = BUTTON_IRQn[Button];
00291     NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x0F;
00292     NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x0F;
00293     NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
00294
00295     NVIC_Init(&NVIC_InitStructure);
00296   }
00297 }
00298
00299 /**
00300   * @brief  Returns the selected Button state.
00301   * @param  Button: Specifies the Button to be checked.
00302   *   This parameter can be one of following parameters:
00303   *     @arg BUTTON_WAKEUP: Wakeup Push Button
00304   *     @arg BUTTON_TAMPER: Tamper Push Button
00305   *     @arg BUTTON_KEY: Key Push Button
00306   *     @arg BUTTON_RIGHT: Joystick Right Push Button
00307   *     @arg BUTTON_LEFT: Joystick Left Push Button
00308   *     @arg BUTTON_UP: Joystick Up Push Button
00309   *     @arg BUTTON_DOWN: Joystick Down Push Button
00310   *     @arg BUTTON_SEL: Joystick Sel Push Button
00311   * @retval The Button GPIO pin value.
00312   */
00313 uint32_t STM_EVAL_PBGetState(Button_TypeDef Button)
00314 {
00315   return GPIO_ReadInputDataBit(BUTTON_PORT[Button], BUTTON_PIN[Button]);
00316 }
00317
00318 /**
00319   * @brief  Configures COM port.
00320   * @param  COM: Specifies the COM port to be configured.
00321   *   This parameter can be one of following parameters:
00322   *     @arg COM1
00323   *     @arg COM2
00324   * @param  USART_InitStruct: pointer to a USART_InitTypeDef structure that
00325   *   contains the configuration information for the specified USART peripheral.
00326   * @retval None
00327   */
00328 void STM_EVAL_COMInit(COM_TypeDef COM, USART_InitTypeDef* USART_InitStruct)
00329 {
00330   GPIO_InitTypeDef GPIO_InitStructure;
00331
00332   /* Enable GPIO clock */
00333   RCC_APB2PeriphClockCmd(COM_TX_PORT_CLK[COM] | COM_RX_PORT_CLK[COM] | RCC_APB2Periph_AFIO, ENABLE);
00334
00335   if (COM == COM1)
00336   {
00337     RCC_APB2PeriphClockCmd(COM_USART_CLK[COM], ENABLE);
00338   }
00339   else
00340   {
00341     /* Enable the USART2 Pins Software Remapping */
00342     GPIO_PinRemapConfig(GPIO_Remap_USART2, ENABLE);
00343     RCC_APB1PeriphClockCmd(COM_USART_CLK[COM], ENABLE);
00344   }
00345
00346   /* Configure USART Tx as alternate function push-pull */
00347   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
00348   GPIO_InitStructure.GPIO_Pin = COM_TX_PIN[COM];
00349   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00350   GPIO_Init(COM_TX_PORT[COM], &GPIO_InitStructure);
00351
00352
00353   /* Configure USART Rx as input floating */
00354   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
00355   GPIO_InitStructure.GPIO_Pin = COM_RX_PIN[COM];
00356   GPIO_Init(COM_RX_PORT[COM], &GPIO_InitStructure);
00357
00358   /* USART configuration */
00359   USART_Init(COM_USART[COM], USART_InitStruct);
00360
00361   /* Enable USART */
00362   USART_Cmd(COM_USART[COM], ENABLE);
00363 }
00364
00365 /**
00366   * @brief  DeInitializes the SD/SD communication.
00367   * @param  None
00368   * @retval None
00369   */
00370 void SD_LowLevel_DeInit(void)
00371 {
00372   GPIO_InitTypeDef  GPIO_InitStructure;
00373
00374   SPI_Cmd(SD_SPI, DISABLE); /*!< SD_SPI disable */
00375   SPI_I2S_DeInit(SD_SPI);   /*!< DeInitializes the SD_SPI */
00376
00377   /*!< SD_SPI Periph clock disable */
00378   RCC_APB2PeriphClockCmd(SD_SPI_CLK, DISABLE);
00379
00380   /*!< Configure SD_SPI pins: SCK */
00381   GPIO_InitStructure.GPIO_Pin = SD_SPI_SCK_PIN;
00382   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
00383   GPIO_Init(SD_SPI_SCK_GPIO_PORT, &GPIO_InitStructure);
00384
00385   /*!< Configure SD_SPI pins: MISO */
00386   GPIO_InitStructure.GPIO_Pin = SD_SPI_MISO_PIN;
00387   GPIO_Init(SD_SPI_MISO_GPIO_PORT, &GPIO_InitStructure);
00388
00389   /*!< Configure SD_SPI pins: MOSI */
00390   GPIO_InitStructure.GPIO_Pin = SD_SPI_MOSI_PIN;
00391   GPIO_Init(SD_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure);
00392
00393   /*!< Configure SD_SPI_CS_PIN pin: SD Card CS pin */
00394   GPIO_InitStructure.GPIO_Pin = SD_CS_PIN;
00395   GPIO_Init(SD_CS_GPIO_PORT, &GPIO_InitStructure);
00396
00397   /*!< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin */
00398   GPIO_InitStructure.GPIO_Pin = SD_DETECT_PIN;
00399   GPIO_Init(SD_DETECT_GPIO_PORT, &GPIO_InitStructure);
00400 }
00401
00402 /**
00403   * @brief  Initializes the SD_SPI and CS pins.
00404   * @param  None
00405   * @retval None
00406   */
00407 void SD_LowLevel_Init(void)
00408 {
00409   GPIO_InitTypeDef  GPIO_InitStructure;
00410   SPI_InitTypeDef   SPI_InitStructure;
00411
00412   /*!< SD_SPI_CS_GPIO, SD_SPI_MOSI_GPIO, SD_SPI_MISO_GPIO, SD_SPI_DETECT_GPIO
00413        and SD_SPI_SCK_GPIO Periph clock enable */
00414   RCC_APB2PeriphClockCmd(SD_CS_GPIO_CLK | SD_SPI_MOSI_GPIO_CLK | SD_SPI_MISO_GPIO_CLK |
00415                          SD_SPI_SCK_GPIO_CLK | SD_DETECT_GPIO_CLK, ENABLE);
00416
00417   /*!< SD_SPI Periph clock enable */
00418   RCC_APB2PeriphClockCmd(SD_SPI_CLK, ENABLE);
00419
00420
00421   /*!< Configure SD_SPI pins: SCK */
00422   GPIO_InitStructure.GPIO_Pin = SD_SPI_SCK_PIN;
00423   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00424   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
00425   GPIO_Init(SD_SPI_SCK_GPIO_PORT, &GPIO_InitStructure);
00426
00427   /*!< Configure SD_SPI pins: MOSI */
00428   GPIO_InitStructure.GPIO_Pin = SD_SPI_MOSI_PIN;
00429   GPIO_Init(SD_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure);
00430
00431   /*!< Configure SD_SPI pins: MISO */
00432   GPIO_InitStructure.GPIO_Pin = SD_SPI_MISO_PIN;
00433   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
00434   GPIO_Init(SD_SPI_MISO_GPIO_PORT, &GPIO_InitStructure);
00435
00436   /*!< Configure SD_SPI_CS_PIN pin: SD Card CS pin */
00437   GPIO_InitStructure.GPIO_Pin = SD_CS_PIN;
00438   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
00439   GPIO_Init(SD_CS_GPIO_PORT, &GPIO_InitStructure);
00440
00441   /*!< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin */
00442   GPIO_InitStructure.GPIO_Pin = SD_DETECT_PIN;
00443   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
00444   GPIO_Init(SD_DETECT_GPIO_PORT, &GPIO_InitStructure);
00445
00446   /*!< SD_SPI Config */
00447   SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
00448   SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
00449   SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
00450   SPI_InitStructure.SPI_CPOL = SPI_CPOL_High;
00451   SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge;
00452   SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
00453   SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_4;
00454   SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
00455   SPI_InitStructure.SPI_CRCPolynomial = 7;
00456   SPI_Init(SD_SPI, &SPI_InitStructure);
00457
00458   SPI_Cmd(SD_SPI, ENABLE); /*!< SD_SPI enable */
00459 }
00460
00461 /**
00462   * @brief  DeInitializes the peripherals used by the SPI FLASH driver.
00463   * @param  None
00464   * @retval None
00465   */
00466 void sFLASH_LowLevel_DeInit(void)
00467 {
00468   GPIO_InitTypeDef GPIO_InitStructure;
00469
00470   /*!< Disable the sFLASH_SPI  */
00471   SPI_Cmd(sFLASH_SPI, DISABLE);
00472
00473   /*!< DeInitializes the sFLASH_SPI */
00474   SPI_I2S_DeInit(sFLASH_SPI);
00475
00476   /*!< sFLASH_SPI Periph clock disable */
00477   RCC_APB2PeriphClockCmd(sFLASH_SPI_CLK, DISABLE);
00478
00479   /*!< Configure sFLASH_SPI pins: SCK */
00480   GPIO_InitStructure.GPIO_Pin = sFLASH_SPI_SCK_PIN;
00481   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
00482   GPIO_Init(sFLASH_SPI_SCK_GPIO_PORT, &GPIO_InitStructure);
00483
00484   /*!< Configure sFLASH_SPI pins: MISO */
00485   GPIO_InitStructure.GPIO_Pin = sFLASH_SPI_MISO_PIN;
00486   GPIO_Init(sFLASH_SPI_MISO_GPIO_PORT, &GPIO_InitStructure);
00487
00488   /*!< Configure sFLASH_SPI pins: MOSI */
00489   GPIO_InitStructure.GPIO_Pin = sFLASH_SPI_MOSI_PIN;
00490   GPIO_Init(sFLASH_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure);
00491
00492   /*!< Configure sFLASH_CS_PIN pin: sFLASH Card CS pin */
00493   GPIO_InitStructure.GPIO_Pin = sFLASH_CS_PIN;
00494   GPIO_Init(sFLASH_CS_GPIO_PORT, &GPIO_InitStructure);
00495 }
00496
00497 /**
00498   * @brief  Initializes the peripherals used by the SPI FLASH driver.
00499   * @param  None
00500   * @retval None
00501   */
00502 void sFLASH_LowLevel_Init(void)
00503 {
00504   GPIO_InitTypeDef GPIO_InitStructure;
00505
00506   /*!< sFLASH_SPI_CS_GPIO, sFLASH_SPI_MOSI_GPIO, sFLASH_SPI_MISO_GPIO
00507        and sFLASH_SPI_SCK_GPIO Periph clock enable */
00508   RCC_APB2PeriphClockCmd(sFLASH_CS_GPIO_CLK | sFLASH_SPI_MOSI_GPIO_CLK | sFLASH_SPI_MISO_GPIO_CLK |
00509                          sFLASH_SPI_SCK_GPIO_CLK, ENABLE);
00510
00511   /*!< sFLASH_SPI Periph clock enable */
00512   RCC_APB2PeriphClockCmd(sFLASH_SPI_CLK, ENABLE);
00513
00514   /*!< Configure sFLASH_SPI pins: SCK */
00515   GPIO_InitStructure.GPIO_Pin = sFLASH_SPI_SCK_PIN;
00516   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00517   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
00518   GPIO_Init(sFLASH_SPI_SCK_GPIO_PORT, &GPIO_InitStructure);
00519
00520   /*!< Configure sFLASH_SPI pins: MOSI */
00521   GPIO_InitStructure.GPIO_Pin = sFLASH_SPI_MOSI_PIN;
00522   GPIO_Init(sFLASH_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure);
00523
00524   /*!< Configure sFLASH_SPI pins: MISO */
00525   GPIO_InitStructure.GPIO_Pin = sFLASH_SPI_MISO_PIN;
00526   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
00527   GPIO_Init(sFLASH_SPI_MISO_GPIO_PORT, &GPIO_InitStructure);
00528
00529   /*!< Configure sFLASH_CS_PIN pin: sFLASH Card CS pin */
00530   GPIO_InitStructure.GPIO_Pin = sFLASH_CS_PIN;
00531   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
00532   GPIO_Init(sFLASH_CS_GPIO_PORT, &GPIO_InitStructure);
00533 }
00534
00535 /**
00536   * @brief  DeInitializes the LM75_I2C.
00537   * @param  None
00538   * @retval None
00539   */
00540 void LM75_LowLevel_DeInit(void)
00541 {
00542   GPIO_InitTypeDef  GPIO_InitStructure;
00543
00544   /*!< Disable LM75_I2C */
00545   I2C_Cmd(LM75_I2C, DISABLE);
00546   /*!< DeInitializes the LM75_I2C */
00547   I2C_DeInit(LM75_I2C);
00548
00549   /*!< LM75_I2C Periph clock disable */
00550   RCC_APB1PeriphClockCmd(LM75_I2C_CLK, DISABLE);
00551
00552   /*!< Configure LM75_I2C pins: SCL */
00553   GPIO_InitStructure.GPIO_Pin = LM75_I2C_SCL_PIN;
00554   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
00555   GPIO_Init(LM75_I2C_SCL_GPIO_PORT, &GPIO_InitStructure);
00556
00557   /*!< Configure LM75_I2C pins: SDA */
00558   GPIO_InitStructure.GPIO_Pin = LM75_I2C_SDA_PIN;
00559   GPIO_Init(LM75_I2C_SDA_GPIO_PORT, &GPIO_InitStructure);
00560
00561   /*!< Configure LM75_I2C pin: SMBUS ALERT */
00562   GPIO_InitStructure.GPIO_Pin = LM75_I2C_SMBUSALERT_PIN;
00563   GPIO_Init(LM75_I2C_SMBUSALERT_GPIO_PORT, &GPIO_InitStructure);
00564 }
00565
00566 /**
00567   * @brief  Initializes the LM75_I2C.
00568   * @param  None
00569   * @retval None
00570   */
00571 void LM75_LowLevel_Init(void)
00572 {
00573   GPIO_InitTypeDef  GPIO_InitStructure;
00574
00575   /*!< LM75_I2C Periph clock enable */
00576   RCC_APB1PeriphClockCmd(LM75_I2C_CLK, ENABLE);
00577
00578   /*!< LM75_I2C_SCL_GPIO_CLK, LM75_I2C_SDA_GPIO_CLK
00579        and LM75_I2C_SMBUSALERT_GPIO_CLK Periph clock enable */
00580   RCC_APB2PeriphClockCmd(LM75_I2C_SCL_GPIO_CLK | LM75_I2C_SDA_GPIO_CLK |
00581                          LM75_I2C_SMBUSALERT_GPIO_CLK, ENABLE);
00582
00583   /*!< Configure LM75_I2C pins: SCL */
00584   GPIO_InitStructure.GPIO_Pin = LM75_I2C_SCL_PIN;
00585   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00586   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_OD;
00587   GPIO_Init(LM75_I2C_SCL_GPIO_PORT, &GPIO_InitStructure);
00588
00589   /*!< Configure LM75_I2C pins: SDA */
00590   GPIO_InitStructure.GPIO_Pin = LM75_I2C_SDA_PIN;
00591   GPIO_Init(LM75_I2C_SDA_GPIO_PORT, &GPIO_InitStructure);
00592
00593   /*!< Configure LM75_I2C pin: SMBUS ALERT */
00594   GPIO_InitStructure.GPIO_Pin = LM75_I2C_SMBUSALERT_PIN;
00595   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
00596   GPIO_Init(LM75_I2C_SMBUSALERT_GPIO_PORT, &GPIO_InitStructure);
00597 }
00598
00599 /**
00600   * @}
00601   */
00602
00603
00604 /**
00605   * @}
00606   */
00607
00608 /**
00609   * @}
00610   */
00611
00612 /**
00613   * @}
00614   */
00615
00616 /**
00617   * @}
00618   */
00619
00620 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm3210b_eval.h Source File

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • STM3210B_EVAL

stm3210b_eval.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm3210b_eval.h
00004   * @author  MCD Application Team
00005   * @version V4.5.0
00006   * @date    07-March-2011
00007   * @brief   This file contains definitions for STM3210B_EVAL's Leds, push-buttons
00008   *          COM ports, SD Card (on SPI), sFLASH (on SPI) and Temperature sensor
00009   *          LM75 (on I2C) hardware resources.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Define to prevent recursive inclusion -------------------------------------*/
00025 #ifndef __STM3210B_EVAL_H
00026 #define __STM3210B_EVAL_H
00027
00028 #ifdef __cplusplus
00029  extern "C" {
00030 #endif
00031
00032 /* Includes ------------------------------------------------------------------*/
00033 #include "stm32_eval.h"
00034 #include "stm32f10x_spi.h"
00035 #include "stm32f10x_i2c.h"
00036
00037 /** @addtogroup Utilities
00038   * @{
00039   */
00040
00041 /** @addtogroup STM32_EVAL
00042   * @{
00043   */
00044
00045 /** @addtogroup STM3210B_EVAL
00046   * @{
00047   */
00048
00049 /** @addtogroup STM3210B_EVAL_LOW_LEVEL
00050   * @{
00051   */
00052
00053 /** @defgroup STM3210B_EVAL_LOW_LEVEL_Exported_Types
00054   * @{
00055   */
00056 /**
00057   * @}
00058   */
00059
00060
00061 /** @defgroup STM3210B_EVAL_LOW_LEVEL_Exported_Constants
00062   * @{
00063   */
00064 /** @addtogroup STM3210B_EVAL_LOW_LEVEL_LED
00065   * @{
00066   */
00067 #define LEDn                             4
00068 #define LED1_PIN                         GPIO_Pin_6
00069 #define LED1_GPIO_PORT                   GPIOC
00070 #define LED1_GPIO_CLK                    RCC_APB2Periph_GPIOC
00071
00072 #define LED2_PIN                         GPIO_Pin_7
00073 #define LED2_GPIO_PORT                   GPIOC
00074 #define LED2_GPIO_CLK                    RCC_APB2Periph_GPIOC
00075
00076 #define LED3_PIN                         GPIO_Pin_8
00077 #define LED3_GPIO_PORT                   GPIOC
00078 #define LED3_GPIO_CLK                    RCC_APB2Periph_GPIOC
00079
00080 #define LED4_PIN                         GPIO_Pin_9
00081 #define LED4_GPIO_PORT                   GPIOC
00082 #define LED4_GPIO_CLK                    RCC_APB2Periph_GPIOC
00083
00084 /**
00085   * @}
00086   */
00087
00088 /** @addtogroup STM3210B_EVAL_LOW_LEVEL_BUTTON
00089   * @{
00090   */
00091 #define BUTTONn                          8
00092
00093 /**
00094  * @brief Wakeup push-button
00095  */
00096 #define WAKEUP_BUTTON_PIN                GPIO_Pin_0
00097 #define WAKEUP_BUTTON_GPIO_PORT          GPIOA
00098 #define WAKEUP_BUTTON_GPIO_CLK           RCC_APB2Periph_GPIOA
00099 #define WAKEUP_BUTTON_EXTI_LINE          EXTI_Line0
00100 #define WAKEUP_BUTTON_EXTI_PORT_SOURCE   GPIO_PortSourceGPIOA
00101 #define WAKEUP_BUTTON_EXTI_PIN_SOURCE    GPIO_PinSource0
00102 #define WAKEUP_BUTTON_EXTI_IRQn          EXTI0_IRQn
00103 /**
00104  * @brief Tamper push-button
00105  */
00106 #define TAMPER_BUTTON_PIN                GPIO_Pin_13
00107 #define TAMPER_BUTTON_GPIO_PORT          GPIOC
00108 #define TAMPER_BUTTON_GPIO_CLK           RCC_APB2Periph_GPIOC
00109 #define TAMPER_BUTTON_EXTI_LINE          EXTI_Line13
00110 #define TAMPER_BUTTON_EXTI_PORT_SOURCE   GPIO_PortSourceGPIOC
00111 #define TAMPER_BUTTON_EXTI_PIN_SOURCE    GPIO_PinSource13
00112 #define TAMPER_BUTTON_EXTI_IRQn          EXTI15_10_IRQn
00113 /**
00114  * @brief Key push-button
00115  */
00116 #define KEY_BUTTON_PIN                   GPIO_Pin_9
00117 #define KEY_BUTTON_GPIO_PORT             GPIOB
00118 #define KEY_BUTTON_GPIO_CLK              RCC_APB2Periph_GPIOB
00119 #define KEY_BUTTON_EXTI_LINE             EXTI_Line9
00120 #define KEY_BUTTON_EXTI_PORT_SOURCE      GPIO_PortSourceGPIOB
00121 #define KEY_BUTTON_EXTI_PIN_SOURCE       GPIO_PinSource9
00122 #define KEY_BUTTON_EXTI_IRQn             EXTI9_5_IRQn
00123 /**
00124  * @brief Joystick Right push-button
00125  */
00126 #define RIGHT_BUTTON_PIN                 GPIO_Pin_0
00127 #define RIGHT_BUTTON_GPIO_PORT           GPIOE
00128 #define RIGHT_BUTTON_GPIO_CLK            RCC_APB2Periph_GPIOE
00129 #define RIGHT_BUTTON_EXTI_LINE           EXTI_Line0
00130 #define RIGHT_BUTTON_EXTI_PORT_SOURCE    GPIO_PortSourceGPIOE
00131 #define RIGHT_BUTTON_EXTI_PIN_SOURCE     GPIO_PinSource0
00132 #define RIGHT_BUTTON_EXTI_IRQn           EXTI0_IRQn
00133 /**
00134  * @brief Joystick Left push-button
00135  */
00136 #define LEFT_BUTTON_PIN                  GPIO_Pin_1
00137 #define LEFT_BUTTON_GPIO_PORT            GPIOE
00138 #define LEFT_BUTTON_GPIO_CLK             RCC_APB2Periph_GPIOE
00139 #define LEFT_BUTTON_EXTI_LINE            EXTI_Line1
00140 #define LEFT_BUTTON_EXTI_PORT_SOURCE     GPIO_PortSourceGPIOE
00141 #define LEFT_BUTTON_EXTI_PIN_SOURCE      GPIO_PinSource1
00142 #define LEFT_BUTTON_EXTI_IRQn            EXTI1_IRQn
00143 /**
00144  * @brief Joystick Up push-button
00145  */
00146 #define UP_BUTTON_PIN                    GPIO_Pin_8
00147 #define UP_BUTTON_GPIO_PORT              GPIOD
00148 #define UP_BUTTON_GPIO_CLK               RCC_APB2Periph_GPIOD
00149 #define UP_BUTTON_EXTI_LINE              EXTI_Line8
00150 #define UP_BUTTON_EXTI_PORT_SOURCE       GPIO_PortSourceGPIOD
00151 #define UP_BUTTON_EXTI_PIN_SOURCE        GPIO_PinSource8
00152 #define UP_BUTTON_EXTI_IRQn              EXTI9_5_IRQn
00153 /**
00154  * @brief Joystick Down push-button
00155  */
00156 #define DOWN_BUTTON_PIN                  GPIO_Pin_14
00157 #define DOWN_BUTTON_GPIO_PORT            GPIOD
00158 #define DOWN_BUTTON_GPIO_CLK             RCC_APB2Periph_GPIOD
00159 #define DOWN_BUTTON_EXTI_LINE            EXTI_Line14
00160 #define DOWN_BUTTON_EXTI_PORT_SOURCE     GPIO_PortSourceGPIOD
00161 #define DOWN_BUTTON_EXTI_PIN_SOURCE      GPIO_PinSource14
00162 #define DOWN_BUTTON_EXTI_IRQn            EXTI15_10_IRQn
00163 /**
00164  * @brief Joystick Sel push-button
00165  */
00166 #define SEL_BUTTON_PIN                   GPIO_Pin_12
00167 #define SEL_BUTTON_GPIO_PORT             GPIOD
00168 #define SEL_BUTTON_GPIO_CLK              RCC_APB2Periph_GPIOD
00169 #define SEL_BUTTON_EXTI_LINE             EXTI_Line12
00170 #define SEL_BUTTON_EXTI_PORT_SOURCE      GPIO_PortSourceGPIOD
00171 #define SEL_BUTTON_EXTI_PIN_SOURCE       GPIO_PinSource12
00172 #define SEL_BUTTON_EXTI_IRQn             EXTI15_10_IRQn
00173 /**
00174   * @}
00175   */
00176
00177 /** @addtogroup STM3210B_EVAL_LOW_LEVEL_COM
00178   * @{
00179   */
00180 #define COMn                             2
00181
00182 /**
00183  * @brief Definition for COM port1, connected to USART1
00184  */
00185 #define EVAL_COM1                        USART1
00186 #define EVAL_COM1_CLK                    RCC_APB2Periph_USART1
00187 #define EVAL_COM1_TX_PIN                 GPIO_Pin_9
00188 #define EVAL_COM1_TX_GPIO_PORT           GPIOA
00189 #define EVAL_COM1_TX_GPIO_CLK            RCC_APB2Periph_GPIOA
00190 #define EVAL_COM1_RX_PIN                 GPIO_Pin_10
00191 #define EVAL_COM1_RX_GPIO_PORT           GPIOA
00192 #define EVAL_COM1_RX_GPIO_CLK            RCC_APB2Periph_GPIOA
00193 #define EVAL_COM1_IRQn                   USART1_IRQn
00194
00195 /**
00196  * @brief Definition for COM port2, connected to USART2 (USART2 pins remapped on GPIOD)
00197  */
00198 #define EVAL_COM2                        USART2
00199 #define EVAL_COM2_CLK                    RCC_APB1Periph_USART2
00200 #define EVAL_COM2_TX_PIN                 GPIO_Pin_5
00201 #define EVAL_COM2_TX_GPIO_PORT           GPIOD
00202 #define EVAL_COM2_TX_GPIO_CLK            RCC_APB2Periph_GPIOD
00203 #define EVAL_COM2_RX_PIN                 GPIO_Pin_6
00204 #define EVAL_COM2_RX_GPIO_PORT           GPIOD
00205 #define EVAL_COM2_RX_GPIO_CLK            RCC_APB2Periph_GPIOD
00206 #define EVAL_COM2_IRQn                   USART2_IRQn
00207
00208 /**
00209   * @}
00210   */
00211
00212 /** @addtogroup STM3210B_EVAL_LOW_LEVEL_SD_SPI
00213   * @{
00214   */
00215 /**
00216   * @brief  SD SPI Interface pins
00217   */
00218 #define SD_SPI                           SPI1
00219 #define SD_SPI_CLK                       RCC_APB2Periph_SPI1
00220 #define SD_SPI_SCK_PIN                   GPIO_Pin_5                  /* PA.05 */
00221 #define SD_SPI_SCK_GPIO_PORT             GPIOA                       /* GPIOA */
00222 #define SD_SPI_SCK_GPIO_CLK              RCC_APB2Periph_GPIOA
00223 #define SD_SPI_MISO_PIN                  GPIO_Pin_6                  /* PA.06 */
00224 #define SD_SPI_MISO_GPIO_PORT            GPIOA                       /* GPIOA */
00225 #define SD_SPI_MISO_GPIO_CLK             RCC_APB2Periph_GPIOA
00226 #define SD_SPI_MOSI_PIN                  GPIO_Pin_7                  /* PA.07 */
00227 #define SD_SPI_MOSI_GPIO_PORT            GPIOA                       /* GPIOA */
00228 #define SD_SPI_MOSI_GPIO_CLK             RCC_APB2Periph_GPIOA
00229 #define SD_CS_PIN                        GPIO_Pin_12                 /* PC.12 */
00230 #define SD_CS_GPIO_PORT                  GPIOC                       /* GPIOC */
00231 #define SD_CS_GPIO_CLK                   RCC_APB2Periph_GPIOC
00232 #define SD_DETECT_PIN                    GPIO_Pin_7                  /* PE.07 */
00233 #define SD_DETECT_GPIO_PORT              GPIOE                       /* GPIOE */
00234 #define SD_DETECT_GPIO_CLK               RCC_APB2Periph_GPIOE
00235
00236 /**
00237   * @}
00238   */
00239
00240 /** @addtogroup STM3210B_EVAL_LOW_LEVEL_M25P_FLASH_SPI
00241   * @{
00242   */
00243 /**
00244   * @brief  M25P FLASH SPI Interface pins
00245   */
00246 #define sFLASH_SPI                       SPI1
00247 #define sFLASH_SPI_CLK                   RCC_APB2Periph_SPI1
00248 #define sFLASH_SPI_SCK_PIN               GPIO_Pin_5                  /* PA.05 */
00249 #define sFLASH_SPI_SCK_GPIO_PORT         GPIOA                       /* GPIOA */
00250 #define sFLASH_SPI_SCK_GPIO_CLK          RCC_APB2Periph_GPIOA
00251 #define sFLASH_SPI_MISO_PIN              GPIO_Pin_6                  /* PA.06 */
00252 #define sFLASH_SPI_MISO_GPIO_PORT        GPIOA                       /* GPIOA */
00253 #define sFLASH_SPI_MISO_GPIO_CLK         RCC_APB2Periph_GPIOA
00254 #define sFLASH_SPI_MOSI_PIN              GPIO_Pin_7                  /* PA.07 */
00255 #define sFLASH_SPI_MOSI_GPIO_PORT        GPIOA                       /* GPIOA */
00256 #define sFLASH_SPI_MOSI_GPIO_CLK         RCC_APB2Periph_GPIOA
00257 #define sFLASH_CS_PIN                    GPIO_Pin_4                  /* PA.04 */
00258 #define sFLASH_CS_GPIO_PORT              GPIOA                       /* GPIOA */
00259 #define sFLASH_CS_GPIO_CLK               RCC_APB2Periph_GPIOA
00260
00261 /**
00262   * @}
00263   */
00264
00265 /** @addtogroup STM3210B_EVAL_LOW_LEVEL_TSENSOR_I2C
00266   * @{
00267   */
00268 /**
00269   * @brief  LM75 Temperature Sensor I2C Interface pins
00270   */
00271 #define LM75_I2C                         I2C1
00272 #define LM75_I2C_CLK                     RCC_APB1Periph_I2C1
00273 #define LM75_I2C_SCL_PIN                 GPIO_Pin_6                  /* PB.06 */
00274 #define LM75_I2C_SCL_GPIO_PORT           GPIOB                       /* GPIOB */
00275 #define LM75_I2C_SCL_GPIO_CLK            RCC_APB2Periph_GPIOB
00276 #define LM75_I2C_SDA_PIN                 GPIO_Pin_7                  /* PB.07 */
00277 #define LM75_I2C_SDA_GPIO_PORT           GPIOB                       /* GPIOB */
00278 #define LM75_I2C_SDA_GPIO_CLK            RCC_APB2Periph_GPIOB
00279 #define LM75_I2C_SMBUSALERT_PIN          GPIO_Pin_5                  /* PB.05 */
00280 #define LM75_I2C_SMBUSALERT_GPIO_PORT    GPIOB                       /* GPIOB */
00281 #define LM75_I2C_SMBUSALERT_GPIO_CLK     RCC_APB2Periph_GPIOB
00282 #define LM75_I2C_DR                      ((uint32_t)0x40005410)
00283
00284 #define LM75_DMA_CLK                     RCC_AHBPeriph_DMA1
00285 #define LM75_DMA_TX_CHANNEL              DMA1_Channel6
00286 #define LM75_DMA_RX_CHANNEL              DMA1_Channel7
00287 #define LM75_DMA_TX_TCFLAG               DMA1_FLAG_TC6
00288 #define LM75_DMA_RX_TCFLAG               DMA1_FLAG_TC7
00289
00290 /**
00291   * @}
00292   */
00293
00294 /**
00295   * @}
00296   */
00297
00298 /** @defgroup STM3210B_EVAL_LOW_LEVEL_Exported_Macros
00299   * @{
00300   */
00301 /**
00302   * @}
00303   */
00304
00305 /** @defgroup STM3210B_EVAL_LOW_LEVEL_Exported_Functions
00306   * @{
00307   */
00308 void STM_EVAL_LEDInit(Led_TypeDef Led);
00309 void STM_EVAL_LEDOn(Led_TypeDef Led);
00310 void STM_EVAL_LEDOff(Led_TypeDef Led);
00311 void STM_EVAL_LEDToggle(Led_TypeDef Led);
00312 void STM_EVAL_PBInit(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode);
00313 uint32_t STM_EVAL_PBGetState(Button_TypeDef Button);
00314 void STM_EVAL_COMInit(COM_TypeDef COM, USART_InitTypeDef* USART_InitStruct);
00315 void SD_LowLevel_DeInit(void);
00316 void SD_LowLevel_Init(void);
00317 void sFLASH_LowLevel_DeInit(void);
00318 void sFLASH_LowLevel_Init(void);
00319 void LM75_LowLevel_DeInit(void);
00320 void LM75_LowLevel_Init(void);
00321
00322 /**
00323   * @}
00324   */
00325
00326 #ifdef __cplusplus
00327 }
00328 #endif
00329
00330 #endif /* __STM3210B_EVAL_H */
00331 /**
00332   * @}
00333   */
00334
00335 /**
00336   * @}
00337   */
00338
00339 /**
00340   * @}
00341   */
00342
00343 /**
00344   * @}
00345   */
00346
00347 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm3210b_eval_lcd.c Source File

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • STM3210B_EVAL

stm3210b_eval_lcd.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm3210b_eval_lcd.c
00004   * @author  MCD Application Team
00005   * @version V4.5.0
00006   * @date    07-March-2011
00007   * @brief   This file includes the LCD driver for AM-240320LTNQW00H (LCD_HX8312),
00008   *          AM-240320L8TNQW00H (LCD_ILI9320), AM-240320LDTNQW00H (LCD_SPFD5408B)
00009   *          Liquid Crystal Display Module of STM3210B-EVAL board.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm3210b_eval_lcd.h"
00026 #include "../Common/fonts.c"
00027
00028 /** @addtogroup Utilities
00029   * @{
00030   */
00031
00032 /** @addtogroup STM32_EVAL
00033   * @{
00034   */
00035
00036 /** @addtogroup STM3210B_EVAL
00037   * @{
00038   */
00039
00040 /** @defgroup STM3210B_EVAL_LCD
00041   * @briefThis file includes the LCD driver for AM-240320LTNQW00H (LCD_HX8312),
00042   *          AM-240320L8TNQW00H (LCD_ILI9320), AM-240320LDTNQW00H (LCD_SPFD5408B)
00043   *          Liquid Crystal Display Module of STM3210B-EVAL board.
00044   * @{
00045   */
00046
00047 /** @defgroup STM3210B_EVAL_LCD_Private_Types
00048   * @{
00049   */
00050 /**
00051   * @}
00052   */
00053
00054
00055 /** @defgroup STM3210B_EVAL_LCD_Private_Defines
00056   * @{
00057   */
00058 #define LCD_ILI9320        0x9320
00059 #define LCD_HX8312         0x8312
00060 #define LCD_SPFD5408       0x5408
00061 #define START_BYTE         0x70
00062 #define SET_INDEX          0x00
00063 #define READ_STATUS        0x01
00064 #define LCD_WRITE_REG      0x02
00065 #define LCD_READ_REG       0x03
00066 #define MAX_POLY_CORNERS   200
00067 #define POLY_Y(Z)          ((int32_t)((Points + Z)->X))
00068 #define POLY_X(Z)          ((int32_t)((Points + Z)->Y))
00069 /**
00070   * @}
00071   */
00072
00073
00074 /** @defgroup STM3210B_EVAL_LCD_Private_Macros
00075   * @{
00076   */
00077 #define ABS(X)  ((X) > 0 ? (X) : -(X))
00078 /**
00079   * @}
00080   */
00081
00082
00083 /** @defgroup STM3210B_EVAL_LCD_Private_Variables
00084   * @{
00085   */
00086 static sFONT *LCD_Currentfonts;
00087 /* Global variables to set the written text color */
00088 static __IO uint16_t TextColor = 0x0000, BackColor = 0xFFFF;
00089 static __IO uint32_t LCDType = LCD_ILI9320;
00090 /**
00091   * @}
00092   */
00093
00094
00095 /** @defgroup STM3210B_EVAL_LCD_Private_Function_Prototypes
00096   * @{
00097   */
00098 #ifndef USE_Delay
00099 static void delay(vu32 nCount);
00100 #endif /* USE_Delay*/
00101
00102 static void LCD_WriteRegHX8312(uint8_t LCD_Reg, uint8_t LCD_RegValue);
00103 static void LCD_WriteRegILI9320(uint8_t LCD_Reg, uint16_t LCD_RegValue);
00104 static void PutPixel(int16_t x, int16_t y);
00105 static void LCD_PolyLineRelativeClosed(pPoint Points, uint16_t PointCount, uint16_t Closed);
00106 /**
00107   * @}
00108   */
00109
00110
00111 /** @defgroup STM3210B_EVAL_LCD_Private_Functions
00112   * @{
00113   */
00114
00115 /**
00116   * @brief  DeInitializes the LCD.
00117   * @param  None
00118   * @retval None
00119   */
00120 void LCD_DeInit(void)
00121 {
00122   GPIO_InitTypeDef GPIO_InitStructure;
00123
00124   /*!< LCD Display Off */
00125   LCD_DisplayOff();
00126
00127   /*!< LCD_SPI disable */
00128   SPI_Cmd(LCD_SPI, DISABLE);
00129
00130   /*!< LCD_SPI DeInit */
00131   SPI_I2S_DeInit(LCD_SPI);
00132
00133   /*!< Disable SPI clock  */
00134   RCC_APB1PeriphClockCmd(LCD_SPI_CLK, DISABLE);
00135
00136   /* Configure NCS in Output Push-Pull mode */
00137   GPIO_InitStructure.GPIO_Pin = LCD_NCS_PIN;
00138   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
00139   GPIO_Init(LCD_NCS_GPIO_PORT, &GPIO_InitStructure);
00140
00141   /* Configure NWR(RNW), RS in Output Push-Pull mode */
00142   GPIO_InitStructure.GPIO_Pin = LCD_RS_PIN;
00143   GPIO_Init(LCD_RS_GPIO_PORT, &GPIO_InitStructure);
00144
00145   GPIO_InitStructure.GPIO_Pin = LCD_NWR_PIN;
00146   GPIO_Init(LCD_NWR_GPIO_PORT, &GPIO_InitStructure);
00147
00148   /* Configure SPI pins: SCK, MISO and MOSI */
00149   GPIO_InitStructure.GPIO_Pin = LCD_SPI_SCK_PIN;
00150   GPIO_Init(LCD_SPI_SCK_GPIO_PORT, &GPIO_InitStructure);
00151
00152   GPIO_InitStructure.GPIO_Pin = LCD_SPI_MISO_PIN;
00153   GPIO_Init(LCD_SPI_MISO_GPIO_PORT, &GPIO_InitStructure);
00154
00155   GPIO_InitStructure.GPIO_Pin = LCD_SPI_MOSI_PIN;
00156   GPIO_Init(LCD_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure);
00157 }
00158
00159 /**
00160   * @brief  Setups the LCD.
00161   * @param  None
00162   * @retval None
00163   */
00164 void LCD_Setup(void)
00165 {
00166 /* Configure the LCD Control pins --------------------------------------------*/
00167   LCD_CtrlLinesConfig();
00168
00169 /* Configure the LCD_SPI interface ----------------------------------------------*/
00170   LCD_SPIConfig();
00171   if(LCDType == LCD_ILI9320)
00172   {
00173     _delay_(5); /* Delay 50 ms */
00174     /* Start Initial Sequence ------------------------------------------------*/
00175     LCD_WriteReg(LCD_REG_229, 0x8000); /* Set the internal vcore voltage */
00176     LCD_WriteReg(LCD_REG_0,  0x0001); /* Start internal OSC. */
00177     LCD_WriteReg(LCD_REG_1,  0x0100); /* set SS and SM bit */
00178     LCD_WriteReg(LCD_REG_2,  0x0700); /* set 1 line inversion */
00179     LCD_WriteReg(LCD_REG_3,  0x1030); /* set GRAM write direction and BGR=1. */
00180     LCD_WriteReg(LCD_REG_4,  0x0000); /* Resize register */
00181     LCD_WriteReg(LCD_REG_8,  0x0202); /* set the back porch and front porch */
00182     LCD_WriteReg(LCD_REG_9,  0x0000); /* set non-display area refresh cycle ISC[3:0] */
00183     LCD_WriteReg(LCD_REG_10, 0x0000); /* FMARK function */
00184     LCD_WriteReg(LCD_REG_12, 0x0000); /* RGB interface setting */
00185     LCD_WriteReg(LCD_REG_13, 0x0000); /* Frame marker Position */
00186     LCD_WriteReg(LCD_REG_15, 0x0000); /* RGB interface polarity */
00187     /* Power On sequence -----------------------------------------------------*/
00188     LCD_WriteReg(LCD_REG_16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
00189     LCD_WriteReg(LCD_REG_17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */
00190     LCD_WriteReg(LCD_REG_18, 0x0000); /* VREG1OUT voltage */
00191     LCD_WriteReg(LCD_REG_19, 0x0000); /* VDV[4:0] for VCOM amplitude */
00192     _delay_(20);               /* Dis-charge capacitor power voltage (200ms) */
00193     LCD_WriteReg(LCD_REG_16, 0x17B0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
00194     LCD_WriteReg(LCD_REG_17, 0x0137); /* DC1[2:0], DC0[2:0], VC[2:0] */
00195     _delay_(5);                /* Delay 50 ms */
00196     LCD_WriteReg(LCD_REG_18, 0x0139); /* VREG1OUT voltage */
00197     _delay_(5);                /* Delay 50 ms */
00198     LCD_WriteReg(LCD_REG_19, 0x1d00); /* VDV[4:0] for VCOM amplitude */
00199     LCD_WriteReg(LCD_REG_41, 0x0013); /* VCM[4:0] for VCOMH */
00200     _delay_(5);                /* Delay 50 ms */
00201     LCD_WriteReg(LCD_REG_32, 0x0000); /* GRAM horizontal Address */
00202     LCD_WriteReg(LCD_REG_33, 0x0000); /* GRAM Vertical Address */
00203     /* Adjust the Gamma Curve ------------------------------------------------*/
00204     LCD_WriteReg(LCD_REG_48, 0x0006);
00205     LCD_WriteReg(LCD_REG_49, 0x0101);
00206     LCD_WriteReg(LCD_REG_50, 0x0003);
00207     LCD_WriteReg(LCD_REG_53, 0x0106);
00208     LCD_WriteReg(LCD_REG_54, 0x0b02);
00209     LCD_WriteReg(LCD_REG_55, 0x0302);
00210     LCD_WriteReg(LCD_REG_56, 0x0707);
00211     LCD_WriteReg(LCD_REG_57, 0x0007);
00212     LCD_WriteReg(LCD_REG_60, 0x0600);
00213     LCD_WriteReg(LCD_REG_61, 0x020b);
00214
00215     /* Set GRAM area ---------------------------------------------------------*/
00216     LCD_WriteReg(LCD_REG_80, 0x0000); /* Horizontal GRAM Start Address */
00217     LCD_WriteReg(LCD_REG_81, 0x00EF); /* Horizontal GRAM End Address */
00218     LCD_WriteReg(LCD_REG_82, 0x0000); /* Vertical GRAM Start Address */
00219     LCD_WriteReg(LCD_REG_83, 0x013F); /* Vertical GRAM End Address */
00220     LCD_WriteReg(LCD_REG_96,  0x2700); /* Gate Scan Line */
00221     LCD_WriteReg(LCD_REG_97,  0x0001); /* NDL,VLE, REV */
00222     LCD_WriteReg(LCD_REG_106, 0x0000); /* set scrolling line */
00223     /* Partial Display Control -----------------------------------------------*/
00224     LCD_WriteReg(LCD_REG_128, 0x0000);
00225     LCD_WriteReg(LCD_REG_129, 0x0000);
00226     LCD_WriteReg(LCD_REG_130, 0x0000);
00227     LCD_WriteReg(LCD_REG_131, 0x0000);
00228     LCD_WriteReg(LCD_REG_132, 0x0000);
00229     LCD_WriteReg(LCD_REG_133, 0x0000);
00230     /* Panel Control ---------------------------------------------------------*/
00231     LCD_WriteReg(LCD_REG_144, 0x0010);
00232     LCD_WriteReg(LCD_REG_146, 0x0000);
00233     LCD_WriteReg(LCD_REG_147, 0x0003);
00234     LCD_WriteReg(LCD_REG_149, 0x0110);
00235     LCD_WriteReg(LCD_REG_151, 0x0000);
00236     LCD_WriteReg(LCD_REG_152, 0x0000);
00237     /* Set GRAM write direction and BGR = 1 */
00238     /* I/D=01 (Horizontal : increment, Vertical : decrement) */
00239     /* AM=1 (address is updated in vertical writing direction) */
00240     LCD_WriteReg(LCD_REG_3, 0x1018);
00241     LCD_WriteReg(LCD_REG_7, 0x0173); /* 262K color and display ON */
00242   }
00243   else if(LCDType == LCD_SPFD5408)
00244   {
00245     /* Start Initial Sequence --------------------------------------------------*/
00246     LCD_WriteReg(LCD_REG_227, 0x3008); /* Set internal timing */
00247     LCD_WriteReg(LCD_REG_231, 0x0012); /* Set internal timing */
00248     LCD_WriteReg(LCD_REG_239, 0x1231); /* Set internal timing */
00249     LCD_WriteReg(LCD_REG_1, 0x0100);   /* Set SS and SM bit */
00250     LCD_WriteReg(LCD_REG_2, 0x0700);   /* Set 1 line inversion */
00251     LCD_WriteReg(LCD_REG_3, 0x1030);   /* Set GRAM write direction and BGR=1. */
00252     LCD_WriteReg(LCD_REG_4, 0x0000);   /* Resize register */
00253     LCD_WriteReg(LCD_REG_8, 0x0202);   /* Set the back porch and front porch */
00254     LCD_WriteReg(LCD_REG_9, 0x0000);   /* Set non-display area refresh cycle ISC[3:0] */
00255     LCD_WriteReg(LCD_REG_10, 0x0000);  /* FMARK function */
00256     LCD_WriteReg(LCD_REG_12, 0x0000);  /* RGB interface setting */
00257     LCD_WriteReg(LCD_REG_13, 0x0000);  /* Frame marker Position */
00258     LCD_WriteReg(LCD_REG_15, 0x0000);  /* RGB interface polarity */
00259     /* Power On sequence -------------------------------------------------------*/
00260     LCD_WriteReg(LCD_REG_16, 0x0000);  /* SAP, BT[3:0], AP, DSTB, SLP, STB */
00261     LCD_WriteReg(LCD_REG_17, 0x0000);  /* DC1[2:0], DC0[2:0], VC[2:0] */
00262     LCD_WriteReg(LCD_REG_18, 0x0000);  /* VREG1OUT voltage */
00263     LCD_WriteReg(LCD_REG_19, 0x0000);  /* VDV[4:0] for VCOM amplitude */
00264     _delay_(20);                /* Dis-charge capacitor power voltage (200ms) */
00265     LCD_WriteReg(LCD_REG_17, 0x0007);  /* DC1[2:0], DC0[2:0], VC[2:0] */
00266     _delay_(5);                 /* Delay 50 ms */
00267     LCD_WriteReg(LCD_REG_16, 0x12B0);  /* SAP, BT[3:0], AP, DSTB, SLP, STB */
00268     _delay_(5);                  /* Delay 50 ms */
00269     LCD_WriteReg(LCD_REG_18, 0x01BD);  /* External reference voltage= Vci */
00270     _delay_(5);                 /* Delay 50 ms */
00271     LCD_WriteReg(LCD_REG_19, 0x1400);       /* VDV[4:0] for VCOM amplitude */
00272     LCD_WriteReg(LCD_REG_41, 0x000E);  /* VCM[4:0] for VCOMH */
00273     _delay_(5);                 /* Delay 50 ms */
00274     LCD_WriteReg(LCD_REG_32, 0x0000);  /* GRAM horizontal Address */
00275     LCD_WriteReg(LCD_REG_33, 0x013F);  /* GRAM Vertical Address */
00276     /* Adjust the Gamma Curve --------------------------------------------------*/
00277     LCD_WriteReg(LCD_REG_48, 0x0007);
00278     LCD_WriteReg(LCD_REG_49, 0x0302);
00279     LCD_WriteReg(LCD_REG_50, 0x0105);
00280     LCD_WriteReg(LCD_REG_53, 0x0206);
00281     LCD_WriteReg(LCD_REG_54, 0x0808);
00282     LCD_WriteReg(LCD_REG_55, 0x0206);
00283     LCD_WriteReg(LCD_REG_56, 0x0504);
00284     LCD_WriteReg(LCD_REG_57, 0x0007);
00285     LCD_WriteReg(LCD_REG_60, 0x0105);
00286     LCD_WriteReg(LCD_REG_61, 0x0808);
00287     /* Set GRAM area -----------------------------------------------------------*/
00288     LCD_WriteReg(LCD_REG_80, 0x0000);  /* Horizontal GRAM Start Address */
00289     LCD_WriteReg(LCD_REG_81, 0x00EF);  /* Horizontal GRAM End Address */
00290     LCD_WriteReg(LCD_REG_82, 0x0000);  /* Vertical GRAM Start Address */
00291     LCD_WriteReg(LCD_REG_83, 0x013F);  /* Vertical GRAM End Address */
00292     LCD_WriteReg(LCD_REG_96,  0xA700); /* Gate Scan Line */
00293     LCD_WriteReg(LCD_REG_97,  0x0001); /* NDL,VLE, REV */
00294     LCD_WriteReg(LCD_REG_106, 0x0000); /* Set scrolling line */
00295     /* Partial Display Control -------------------------------------------------*/
00296     LCD_WriteReg(LCD_REG_128, 0x0000);
00297     LCD_WriteReg(LCD_REG_129, 0x0000);
00298     LCD_WriteReg(LCD_REG_130, 0x0000);
00299     LCD_WriteReg(LCD_REG_131, 0x0000);
00300     LCD_WriteReg(LCD_REG_132, 0x0000);
00301     LCD_WriteReg(LCD_REG_133, 0x0000);
00302     /* Panel Control -----------------------------------------------------------*/
00303     LCD_WriteReg(LCD_REG_144, 0x0010);
00304     LCD_WriteReg(LCD_REG_146, 0x0000);
00305     LCD_WriteReg(LCD_REG_147, 0x0003);
00306     LCD_WriteReg(LCD_REG_149, 0x0110);
00307     LCD_WriteReg(LCD_REG_151, 0x0000);
00308     LCD_WriteReg(LCD_REG_152, 0x0000);
00309     /* Set GRAM write direction and BGR = 1
00310        I/D=01 (Horizontal : increment, Vertical : decrement)
00311        AM=1 (address is updated in vertical writing direction) */
00312     LCD_WriteReg(LCD_REG_3, 0x1018);
00313     LCD_WriteReg(LCD_REG_7, 0x0112);   /* 262K color and display ON */
00314   }
00315   else if(LCDType == LCD_HX8312)
00316   {
00317     /* Enable the LCD Oscillator ---------------------------------------------*/
00318     LCD_WriteReg(LCD_REG_1, 0x10);
00319     LCD_WriteReg(LCD_REG_0, 0xA0);
00320     LCD_WriteReg(LCD_REG_3, 0x01);
00321     _delay_(1); /* Delay 10 ms */
00322     LCD_WriteReg(LCD_REG_3, 0x00);
00323     LCD_WriteReg(LCD_REG_43, 0x04);
00324
00325     LCD_WriteReg(LCD_REG_40, 0x18);
00326     LCD_WriteReg(LCD_REG_26, 0x05);
00327     LCD_WriteReg(LCD_REG_37, 0x05);
00328     LCD_WriteReg(LCD_REG_25, 0x00);
00329
00330     /* LCD Power On ----------------------------------------------------------*/
00331     LCD_WriteReg(LCD_REG_28, 0x73);
00332     LCD_WriteReg(LCD_REG_36, 0x74);
00333     LCD_WriteReg(LCD_REG_30, 0x01);
00334     LCD_WriteReg(LCD_REG_24, 0xC1);
00335     _delay_(1); /* Delay 10 ms */
00336     LCD_WriteReg(LCD_REG_24, 0xE1);
00337     LCD_WriteReg(LCD_REG_24, 0xF1);
00338     _delay_(6); /* Delay 60 ms */
00339     LCD_WriteReg(LCD_REG_24, 0xF5);
00340     _delay_(6); /* Delay 60 ms */
00341     LCD_WriteReg(LCD_REG_27, 0x09);
00342     _delay_(1); /* Delay 10 ms */
00343     LCD_WriteReg(LCD_REG_31, 0x11);
00344     LCD_WriteReg(LCD_REG_32, 0x0E);
00345     LCD_WriteReg(LCD_REG_30, 0x81);
00346     _delay_(1); /* Delay 10 ms */
00347
00348     /* Chip Set --------------------------------------------------------------*/
00349     LCD_WriteReg(LCD_REG_157, 0x00);
00350     LCD_WriteReg(LCD_REG_192, 0x00);
00351
00352     LCD_WriteReg(LCD_REG_14, 0x00);
00353     LCD_WriteReg(LCD_REG_15, 0x00);
00354     LCD_WriteReg(LCD_REG_16, 0x00);
00355     LCD_WriteReg(LCD_REG_17, 0x00);
00356     LCD_WriteReg(LCD_REG_18, 0x00);
00357     LCD_WriteReg(LCD_REG_19, 0x00);
00358     LCD_WriteReg(LCD_REG_20, 0x00);
00359     LCD_WriteReg(LCD_REG_21, 0x00);
00360     LCD_WriteReg(LCD_REG_22, 0x00);
00361     LCD_WriteReg(LCD_REG_23, 0x00);
00362
00363     LCD_WriteReg(LCD_REG_52, 0x01);
00364     LCD_WriteReg(LCD_REG_53, 0x00);
00365     LCD_WriteReg(LCD_REG_75, 0x00);
00366     LCD_WriteReg(LCD_REG_76, 0x00);
00367     LCD_WriteReg(LCD_REG_78, 0x00);
00368     LCD_WriteReg(LCD_REG_79, 0x00);
00369     LCD_WriteReg(LCD_REG_80, 0x00);
00370
00371     LCD_WriteReg(LCD_REG_60, 0x00);
00372     LCD_WriteReg(LCD_REG_61, 0x00);
00373     LCD_WriteReg(LCD_REG_62, 0x01);
00374     LCD_WriteReg(LCD_REG_63, 0x3F);
00375     LCD_WriteReg(LCD_REG_64, 0x02);
00376     LCD_WriteReg(LCD_REG_65, 0x02);
00377     LCD_WriteReg(LCD_REG_66, 0x00);
00378     LCD_WriteReg(LCD_REG_67, 0x00);
00379     LCD_WriteReg(LCD_REG_68, 0x00);
00380     LCD_WriteReg(LCD_REG_69, 0x00);
00381     LCD_WriteReg(LCD_REG_70, 0xEF);
00382     LCD_WriteReg(LCD_REG_71, 0x00);
00383     LCD_WriteReg(LCD_REG_72, 0x00);
00384     LCD_WriteReg(LCD_REG_73, 0x01);
00385     LCD_WriteReg(LCD_REG_74, 0x3F);
00386
00387     LCD_WriteReg(LCD_REG_29, 0x08);  /* R29:Gate scan direction setting */
00388
00389     LCD_WriteReg(LCD_REG_134, 0x00);
00390     LCD_WriteReg(LCD_REG_135, 0x30);
00391     LCD_WriteReg(LCD_REG_136, 0x02);
00392     LCD_WriteReg(LCD_REG_137, 0x05);
00393
00394     LCD_WriteReg(LCD_REG_141, 0x01);  /* R141:Register set-up mode for one line clock */
00395     LCD_WriteReg(LCD_REG_139, 0x20);  /* R139:One line SYSCLK number in one-line */
00396     LCD_WriteReg(LCD_REG_51, 0x01);  /* R51:N line inversion setting */
00397     LCD_WriteReg(LCD_REG_55, 0x01);  /* R55:Scanning method setting */
00398     LCD_WriteReg(LCD_REG_118, 0x00);
00399
00400     /* Gamma Set -------------------------------------------------------------*/
00401     LCD_WriteReg(LCD_REG_143, 0x10);
00402     LCD_WriteReg(LCD_REG_144, 0x67);
00403     LCD_WriteReg(LCD_REG_145, 0x07);
00404     LCD_WriteReg(LCD_REG_146, 0x65);
00405     LCD_WriteReg(LCD_REG_147, 0x07);
00406     LCD_WriteReg(LCD_REG_148, 0x01);
00407     LCD_WriteReg(LCD_REG_149, 0x76);
00408     LCD_WriteReg(LCD_REG_150, 0x56);
00409     LCD_WriteReg(LCD_REG_151, 0x00);
00410     LCD_WriteReg(LCD_REG_152, 0x06);
00411     LCD_WriteReg(LCD_REG_153, 0x03);
00412     LCD_WriteReg(LCD_REG_154, 0x00);
00413
00414     /* Display On ------------------------------------------------------------*/
00415     LCD_WriteReg(LCD_REG_1, 0x50);
00416     LCD_WriteReg(LCD_REG_5, 0x04);
00417     LCD_WriteReg(LCD_REG_0, 0x80);
00418     LCD_WriteReg(LCD_REG_59, 0x01);
00419     _delay_(4);  /* Delay 40 ms */
00420     LCD_WriteReg(LCD_REG_0, 0x20);
00421   }
00422 }
00423
00424
00425 /**
00426   * @brief  Initializes the LCD.
00427   * @param  None
00428   * @retval None
00429   */
00430 void STM3210B_LCD_Init(void)
00431 {
00432   /* Setups the LCD */
00433   LCD_Setup();
00434   /* Try to read new LCD controller ID 0x9320 */
00435   if (LCD_ReadReg(LCD_REG_0) == LCD_ILI9320)
00436   {
00437     LCDType = LCD_ILI9320;
00438   }
00439   else
00440   {
00441     LCDType = LCD_SPFD5408;
00442     /* Setups the LCD */
00443     LCD_Setup();
00444     /* Try to read new LCD controller ID 0x5408 */
00445     if (LCD_ReadReg(LCD_REG_0) != LCD_SPFD5408)
00446     {
00447       LCDType = LCD_HX8312;
00448       /* Setups the LCD */
00449       LCD_Setup();
00450     }
00451   }
00452   LCD_SetFont(&LCD_DEFAULT_FONT);
00453 }
00454
00455 /**
00456   * @brief  Sets the LCD Text and Background colors.
00457   * @param  _TextColor: specifies the Text Color.
00458   * @param  _BackColor: specifies the Background Color.
00459   * @retval None
00460   */
00461 void LCD_SetColors(__IO uint16_t _TextColor, __IO uint16_t _BackColor)
00462 {
00463   TextColor = _TextColor;
00464   BackColor = _BackColor;
00465 }
00466
00467 /**
00468   * @brief  Gets the LCD Text and Background colors.
00469   * @param  _TextColor: pointer to the variable that will contain the Text
00470             Color.
00471   * @param  _BackColor: pointer to the variable that will contain the Background
00472             Color.
00473   * @retval None
00474   */
00475 void LCD_GetColors(__IO uint16_t *_TextColor, __IO uint16_t *_BackColor)
00476 {
00477   *_TextColor = TextColor; *_BackColor = BackColor;
00478 }
00479
00480 /**
00481   * @brief  Sets the Text color.
00482   * @param  Color: specifies the Text color code RGB(5-6-5).
00483   * @retval None
00484   */
00485 void LCD_SetTextColor(__IO uint16_t Color)
00486 {
00487   TextColor = Color;
00488 }
00489
00490
00491 /**
00492   * @brief  Sets the Background color.
00493   * @param  Color: specifies the Background color code RGB(5-6-5).
00494   * @retval None
00495   */
00496 void LCD_SetBackColor(__IO uint16_t Color)
00497 {
00498   BackColor = Color;
00499 }
00500
00501 /**
00502   * @brief  Sets the Text Font.
00503   * @param  fonts: specifies the font to be used.
00504   * @retval None
00505   */
00506 void LCD_SetFont(sFONT *fonts)
00507 {
00508   LCD_Currentfonts = fonts;
00509 }
00510
00511 /**
00512   * @brief  Gets the Text Font.
00513   * @param  None.
00514   * @retval the used font.
00515   */
00516 sFONT *LCD_GetFont(void)
00517 {
00518   return LCD_Currentfonts;
00519 }
00520
00521 /**
00522   * @brief  Clears the selected line.
00523   * @param  Line: the Line to be cleared.
00524   *   This parameter can be one of the following values:
00525   *     @arg Linex: where x can be 0..n
00526   * @retval None
00527   */
00528 void LCD_ClearLine(uint8_t Line)
00529 {
00530   uint16_t refcolumn = LCD_PIXEL_WIDTH - 1;
00531   /* Send the string character by character on lCD */
00532   while (((refcolumn + 1) & 0xFFFF) >= LCD_Currentfonts->Width)
00533   {
00534     /* Display one character on LCD */
00535     LCD_DisplayChar(Line, refcolumn, ' ');
00536     /* Decrement the column position by 16 */
00537     refcolumn -= LCD_Currentfonts->Width;
00538   }
00539 }
00540
00541
00542 /**
00543   * @brief  Clears the hole LCD.
00544   * @param  Color: the color of the background.
00545   * @retval None
00546   */
00547 void LCD_Clear(uint16_t Color)
00548 {
00549   uint32_t index = 0;
00550
00551   LCD_SetCursor(0x00, 0x013F);
00552   if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
00553   {
00554     LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
00555   }
00556   for(index = 0; index < 76800; index++)
00557   {
00558     LCD_WriteRAM(Color);
00559   }
00560   if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
00561   {
00562     LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
00563   }
00564 }
00565
00566
00567 /**
00568   * @brief  Sets the cursor position.
00569   * @param  Xpos: specifies the X position.
00570   * @param  Ypos: specifies the Y position.
00571   * @retval None
00572   */
00573 void LCD_SetCursor(uint8_t Xpos, uint16_t Ypos)
00574 {
00575   if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
00576   {
00577     LCD_WriteReg(LCD_REG_32, Xpos);
00578     LCD_WriteReg(LCD_REG_33, Ypos);
00579   }
00580   else if(LCDType == LCD_HX8312)
00581   {
00582     LCD_WriteReg(LCD_REG_66, Xpos);
00583     LCD_WriteReg(LCD_REG_67, ((Ypos & 0x100)>> 8));
00584     LCD_WriteReg(LCD_REG_68, (Ypos & 0xFF));
00585   }
00586 }
00587
00588
00589 /**
00590   * @brief  Draws a character on LCD.
00591   * @param  Xpos: the Line where to display the character shape.
00592   * @param  Ypos: start column address.
00593   * @param  c: pointer to the character data.
00594   * @retval None
00595   */
00596 void LCD_DrawChar(uint8_t Xpos, uint16_t Ypos, const uint16_t *c)
00597 {
00598   uint32_t index = 0, i = 0;
00599   uint8_t Xaddress = 0;
00600
00601   Xaddress = Xpos;
00602
00603   LCD_SetCursor(Xaddress, Ypos);
00604
00605   for(index = 0; index < LCD_Currentfonts->Height; index++)
00606   {
00607     if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
00608     {
00609       LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
00610     }
00611     for(i = 0; i < LCD_Currentfonts->Width; i++)
00612     {
00613       if((((c[index] & ((0x80 << ((LCD_Currentfonts->Width / 12 ) * 8 ) ) >> i)) == 0x00) &&(LCD_Currentfonts->Width <= 12))||
00614         (((c[index] & (0x1 << i)) == 0x00)&&(LCD_Currentfonts->Width > 12 )))
00615
00616       {
00617         LCD_WriteRAM(BackColor);
00618       }
00619       else
00620       {
00621         LCD_WriteRAM(TextColor);
00622       }
00623     }
00624     if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
00625     {
00626       LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
00627     }
00628     Xaddress++;
00629     LCD_SetCursor(Xaddress, Ypos);
00630   }
00631 }
00632
00633
00634 /**
00635   * @brief  Displays one character (16dots width, 24dots height).
00636   * @param  Line: the Line where to display the character shape .
00637   *   This parameter can be one of the following values:
00638   *     @arg Linex: where x can be 0..9
00639   * @param  Column: start column address.
00640   * @param  Ascii: character ascii code, must be between 0x20 and 0x7E.
00641   * @retval None
00642   */
00643 void LCD_DisplayChar(uint8_t Line, uint16_t Column, uint8_t Ascii)
00644 {
00645   Ascii -= 32;
00646   LCD_DrawChar(Line, Column, &LCD_Currentfonts->table[Ascii * LCD_Currentfonts->Height]);
00647 }
00648
00649
00650 /**
00651   * @brief  Displays a maximum of 20 char on the LCD.
00652   * @param  Line: the Line where to display the character shape .
00653   *   This parameter can be one of the following values:
00654   *     @arg Linex: where x can be 0..9
00655   * @param  *ptr: pointer to string to display on LCD.
00656   * @retval None
00657   */
00658 void LCD_DisplayStringLine(uint8_t Line, uint8_t *ptr)
00659 {
00660   uint16_t refcolumn = LCD_PIXEL_WIDTH - 1;
00661
00662   /* Send the string character by character on lCD */
00663   while ((*ptr != 0) & (((refcolumn + 1) & 0xFFFF) >= LCD_Currentfonts->Width))
00664   {
00665     /* Display one character on LCD */
00666     LCD_DisplayChar(Line, refcolumn, *ptr);
00667     /* Decrement the column position by 16 */
00668     refcolumn -= LCD_Currentfonts->Width;
00669     /* Point on the next character */
00670     ptr++;
00671   }
00672 }
00673
00674
00675 /**
00676   * @brief  Sets a display window
00677   * @param  Xpos: specifies the X buttom left position.
00678   * @param  Ypos: specifies the Y buttom left position.
00679   * @param  Height: display window height.
00680   * @param  Width: display window width.
00681   * @retval None
00682   */
00683 void LCD_SetDisplayWindow(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width)
00684 {
00685   if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
00686   {
00687     /* Horizontal GRAM Start Address */
00688     if(Xpos >= Height)
00689     {
00690       LCD_WriteReg(LCD_REG_80, (Xpos - Height + 1));
00691     }
00692     else
00693     {
00694       LCD_WriteReg(LCD_REG_80, 0);
00695     }
00696     /* Horizontal GRAM End Address */
00697     LCD_WriteReg(LCD_REG_81, Xpos);
00698     /* Vertical GRAM Start Address */
00699     if(Ypos >= Width)
00700     {
00701       LCD_WriteReg(LCD_REG_82, (Ypos - Width + 1));
00702     }
00703     else
00704     {
00705       LCD_WriteReg(LCD_REG_82, 0);
00706     }
00707     /* Vertical GRAM End Address */
00708     LCD_WriteReg(LCD_REG_83, Ypos);
00709   }
00710   else if(LCDType == LCD_HX8312)
00711   {
00712     LCD_WriteReg(LCD_REG_1, 0xD0);
00713     LCD_WriteReg(LCD_REG_5, 0x14);
00714
00715     LCD_WriteReg(LCD_REG_69, (Xpos - Height + 1));
00716     LCD_WriteReg(LCD_REG_70, Xpos);
00717
00718     LCD_WriteReg(LCD_REG_71, (((Ypos - Width + 1) & 0x100)>> 8));
00719     LCD_WriteReg(LCD_REG_72, ((Ypos - Width + 1) & 0xFF));
00720     LCD_WriteReg(LCD_REG_73, ((Ypos & 0x100)>> 8));
00721     LCD_WriteReg(LCD_REG_74, (Ypos & 0xFF));
00722   }
00723   LCD_SetCursor(Xpos, Ypos);
00724 }
00725
00726
00727 /**
00728   * @brief  Disables LCD Window mode.
00729   * @param  None
00730   * @retval None
00731   */
00732 void LCD_WindowModeDisable(void)
00733 {
00734   if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
00735   {
00736     LCD_SetDisplayWindow(239, 0x13F, 240, 320);
00737     LCD_WriteReg(LCD_REG_3, 0x1018);
00738   }
00739   else if(LCDType == LCD_HX8312)
00740   {
00741     LCD_WriteReg(LCD_REG_1, 0x50);
00742     LCD_WriteReg(LCD_REG_5, 0x04);
00743   }
00744
00745 }
00746
00747
00748 /**
00749   * @brief  Displays a line.
00750   * @param  Xpos: specifies the X position.
00751   * @param  Ypos: specifies the Y position.
00752   * @param  Length: line length.
00753   * @param  Direction: line direction.
00754   *   This parameter can be one of the following values: Vertical or Horizontal.
00755   * @retval None
00756   */
00757 void LCD_DrawLine(uint8_t Xpos, uint16_t Ypos, uint16_t Length, uint8_t Direction)
00758 {
00759   uint32_t i = 0;
00760
00761   LCD_SetCursor(Xpos, Ypos);
00762   if(Direction == LCD_DIR_HORIZONTAL)
00763   {
00764     if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
00765     {
00766       LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
00767     }
00768     for(i = 0; i < Length; i++)
00769     {
00770       LCD_WriteRAM(TextColor);
00771     }
00772     if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
00773     {
00774       LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
00775     }
00776   }
00777   else
00778   {
00779    for(i = 0; i < Length; i++)
00780     {
00781       if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
00782       {
00783         LCD_WriteRAMWord(TextColor);
00784       }
00785       else  if(LCDType == LCD_HX8312)
00786       {
00787         LCD_WriteRAM(TextColor);
00788       }
00789       Xpos++;
00790       LCD_SetCursor(Xpos, Ypos);
00791     }
00792   }
00793 }
00794
00795
00796 /**
00797   * @brief  Displays a rectangle.
00798   * @param  Xpos: specifies the X position.
00799   * @param  Ypos: specifies the Y position.
00800   * @param  Height: display rectangle height.
00801   * @param  Width: display rectangle width.
00802   * @retval None
00803   */
00804 void LCD_DrawRect(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width)
00805 {
00806   LCD_DrawLine(Xpos, Ypos, Width, LCD_DIR_HORIZONTAL);
00807   LCD_DrawLine((Xpos + Height), Ypos, Width, LCD_DIR_HORIZONTAL);
00808
00809   LCD_DrawLine(Xpos, Ypos, Height, LCD_DIR_VERTICAL);
00810   LCD_DrawLine(Xpos, (Ypos - Width + 1), Height, LCD_DIR_VERTICAL);
00811 }
00812
00813
00814 /**
00815   * @brief  Displays a circle.
00816   * @param  Xpos: specifies the X position.
00817   * @param  Ypos: specifies the Y position.
00818   * @param  Radius
00819   * @retval None
00820   */
00821 void LCD_DrawCircle(uint8_t Xpos, uint16_t Ypos, uint16_t Radius)
00822 {
00823   int32_t  D;/* Decision Variable */
00824   uint32_t  CurX;/* Current X Value */
00825   uint32_t  CurY;/* Current Y Value */
00826
00827   D = 3 - (Radius << 1);
00828   CurX = 0;
00829   CurY = Radius;
00830
00831   while (CurX <= CurY)
00832   {
00833     LCD_SetCursor(Xpos + CurX, Ypos + CurY);
00834     if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
00835     {
00836       LCD_WriteRAMWord(TextColor);
00837     }
00838     else if(LCDType == LCD_HX8312)
00839     {
00840       LCD_WriteRAM(TextColor);
00841     }
00842     LCD_SetCursor(Xpos + CurX, Ypos - CurY);
00843
00844     if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
00845     {
00846       LCD_WriteRAMWord(TextColor);
00847     }
00848     else if(LCDType == LCD_HX8312)
00849     {
00850       LCD_WriteRAM(TextColor);
00851     }
00852     LCD_SetCursor(Xpos - CurX, Ypos + CurY);
00853
00854     if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
00855     {
00856       LCD_WriteRAMWord(TextColor);
00857     }
00858     else if(LCDType == LCD_HX8312)
00859     {
00860       LCD_WriteRAM(TextColor);
00861     }
00862     LCD_SetCursor(Xpos - CurX, Ypos - CurY);
00863
00864     if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
00865     {
00866       LCD_WriteRAMWord(TextColor);
00867     }
00868     else if(LCDType == LCD_HX8312)
00869     {
00870       LCD_WriteRAM(TextColor);
00871     }
00872     LCD_SetCursor(Xpos + CurY, Ypos + CurX);
00873     if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
00874     {
00875       LCD_WriteRAMWord(TextColor);
00876     }
00877     else if(LCDType == LCD_HX8312)
00878     {
00879       LCD_WriteRAM(TextColor);
00880     }
00881     LCD_SetCursor(Xpos + CurY, Ypos - CurX);
00882
00883     if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
00884     {
00885       LCD_WriteRAMWord(TextColor);
00886     }
00887     else if(LCDType == LCD_HX8312)
00888     {
00889       LCD_WriteRAM(TextColor);
00890     }
00891     LCD_SetCursor(Xpos - CurY, Ypos + CurX);
00892
00893     if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
00894     {
00895       LCD_WriteRAMWord(TextColor);
00896     }
00897     else if(LCDType == LCD_HX8312)
00898     {
00899       LCD_WriteRAM(TextColor);
00900     }
00901     LCD_SetCursor(Xpos - CurY, Ypos - CurX);
00902
00903     if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
00904     {
00905       LCD_WriteRAMWord(TextColor);
00906     }
00907     else if(LCDType == LCD_HX8312)
00908     {
00909       LCD_WriteRAM(TextColor);
00910     }
00911     if (D < 0)
00912     {
00913       D += (CurX << 2) + 6;
00914     }
00915     else
00916     {
00917       D += ((CurX - CurY) << 2) + 10;
00918       CurY--;
00919     }
00920     CurX++;
00921   }
00922 }
00923
00924
00925 /**
00926   * @brief  Displays a monocolor picture.
00927   * @param  Pict: pointer to the picture array.
00928   * @retval None
00929   */
00930 void LCD_DrawMonoPict(const uint32_t *Pict)
00931 {
00932   uint32_t index = 0, i = 0;
00933   LCD_SetCursor(0, (LCD_PIXEL_WIDTH - 1));
00934
00935   if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
00936   {
00937     LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
00938   }
00939
00940   for(index = 0; index < 2400; index++)
00941   {
00942     for(i = 0; i < 32; i++)
00943     {
00944       if((Pict[index] & (1 << i)) == 0x00)
00945       {
00946         LCD_WriteRAM(BackColor);
00947       }
00948       else
00949       {
00950         LCD_WriteRAM(TextColor);
00951       }
00952     }
00953   }
00954
00955   if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
00956   {
00957     LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
00958   }
00959 }
00960
00961 #ifdef USE_LCD_DrawBMP
00962 /**
00963   * @brief  Displays a bitmap picture loaded in the SPI Flash.
00964   * @param  BmpAddress: Bmp picture address in the SPI Flash.
00965   * @retval None
00966   */
00967 void LCD_DrawBMP(uint32_t BmpAddress)
00968 {
00969   uint32_t i = 0, size = 0;
00970   /* Read bitmap size */
00971   sFLASH_ReadBuffer((uint8_t*)&size, BmpAddress + 2, 4);
00972   /* get bitmap data address offset */
00973   sFLASH_ReadBuffer((uint8_t*)&i, BmpAddress + 10, 4);
00974
00975   size = (size - i)/2;
00976   sFLASH_StartReadSequence(BmpAddress + i);
00977   /* Disable LCD_SPI  */
00978   SPI_Cmd(LCD_SPI, DISABLE);
00979   /* SPI in 16-bit mode */
00980   SPI_DataSizeConfig(LCD_SPI, SPI_DataSize_16b);
00981   /* Enable LCD_SPI  */
00982   SPI_Cmd(LCD_SPI, ENABLE);
00983
00984   if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
00985   {
00986     /* Set GRAM write direction and BGR = 1 */
00987     /* I/D=00 (Horizontal : decrement, Vertical : decrement) */
00988     /* AM=1 (address is updated in vertical writing direction) */
00989     LCD_WriteReg(LCD_REG_3, 0x1008);
00990     LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
00991   }
00992
00993   /* Read bitmap data from SPI Flash and send them to LCD */
00994   for(i = 0; i < size; i++)
00995   {
00996     LCD_WriteRAM(__REV16(sFLASH_SendHalfWord(0xA5A5)));
00997   }
00998   if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
00999   {
01000     LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
01001   }
01002
01003   /* Deselect the FLASH: Chip Select high */
01004   sFLASH_CS_HIGH();
01005   /* Disable LCD_SPI  */
01006   SPI_Cmd(LCD_SPI, DISABLE);
01007   /* SPI in 8-bit mode */
01008   SPI_DataSizeConfig(LCD_SPI, SPI_DataSize_8b);
01009   /* Enable LCD_SPI  */
01010   SPI_Cmd(LCD_SPI, ENABLE);
01011
01012   if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
01013   {
01014     /* Set GRAM write direction and BGR = 1 */
01015     /* I/D = 01 (Horizontal : increment, Vertical : decrement) */
01016     /* AM = 1 (address is updated in vertical writing direction) */
01017     LCD_WriteReg(LCD_REG_3, 0x1018);
01018   }
01019 }
01020 #endif /* USE_LCD_DrawBMP */
01021
01022 /**
01023   * @brief  Displays a full rectangle.
01024   * @param  Xpos: specifies the X position.
01025   * @param  Ypos: specifies the Y position.
01026   * @param  Height: rectangle height.
01027   * @param  Width: rectangle width.
01028   * @retval None
01029   */
01030 void LCD_DrawFullRect(uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height)
01031 {
01032   LCD_SetTextColor(TextColor);
01033
01034   LCD_DrawLine(Xpos, Ypos, Width, LCD_DIR_HORIZONTAL);
01035   LCD_DrawLine((Xpos + Height), Ypos, Width, LCD_DIR_HORIZONTAL);
01036
01037   LCD_DrawLine(Xpos, Ypos, Height, LCD_DIR_VERTICAL);
01038   LCD_DrawLine(Xpos, (Ypos - Width + 1), Height, LCD_DIR_VERTICAL);
01039
01040   Width -= 2;
01041   Height--;
01042   Ypos--;
01043
01044   LCD_SetTextColor(BackColor);
01045
01046   while(Height--)
01047   {
01048     LCD_DrawLine(++Xpos, Ypos, Width, LCD_DIR_HORIZONTAL);
01049   }
01050
01051   LCD_SetTextColor(TextColor);
01052 }
01053
01054 /**
01055   * @brief  Displays a full circle.
01056   * @param  Xpos: specifies the X position.
01057   * @param  Ypos: specifies the Y position.
01058   * @param  Radius
01059   * @retval None
01060   */
01061 void LCD_DrawFullCircle(uint16_t Xpos, uint16_t Ypos, uint16_t Radius)
01062 {
01063   int32_t  D;    /* Decision Variable */
01064   uint32_t  CurX;/* Current X Value */
01065   uint32_t  CurY;/* Current Y Value */
01066
01067   D = 3 - (Radius << 1);
01068
01069   CurX = 0;
01070   CurY = Radius;
01071
01072   LCD_SetTextColor(BackColor);
01073
01074   while (CurX <= CurY)
01075   {
01076     if(CurY > 0)
01077     {
01078       LCD_DrawLine(Xpos - CurX, Ypos + CurY, 2*CurY, LCD_DIR_HORIZONTAL);
01079       LCD_DrawLine(Xpos + CurX, Ypos + CurY, 2*CurY, LCD_DIR_HORIZONTAL);
01080     }
01081
01082     if(CurX > 0)
01083     {
01084       LCD_DrawLine(Xpos - CurY, Ypos + CurX, 2*CurX, LCD_DIR_HORIZONTAL);
01085       LCD_DrawLine(Xpos + CurY, Ypos + CurX, 2*CurX, LCD_DIR_HORIZONTAL);
01086     }
01087     if (D < 0)
01088     {
01089       D += (CurX << 2) + 6;
01090     }
01091     else
01092     {
01093       D += ((CurX - CurY) << 2) + 10;
01094       CurY--;
01095     }
01096     CurX++;
01097   }
01098
01099   LCD_SetTextColor(TextColor);
01100   LCD_DrawCircle(Xpos, Ypos, Radius);
01101 }
01102
01103 /**
01104   * @brief  Displays an uni line (between two points).
01105   * @param  x1: specifies the point 1 x position.
01106   * @param  y1: specifies the point 1 y position.
01107   * @param  x2: specifies the point 2 x position.
01108   * @param  y2: specifies the point 2 y position.
01109   * @retval None
01110   */
01111 void LCD_DrawUniLine(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2)
01112 {
01113   int16_t deltax = 0, deltay = 0, x = 0, y = 0, xinc1 = 0, xinc2 = 0,
01114   yinc1 = 0, yinc2 = 0, den = 0, num = 0, numadd = 0, numpixels = 0,
01115   curpixel = 0;
01116
01117   deltax = ABS(x2 - x1);        /* The difference between the x's */
01118   deltay = ABS(y2 - y1);        /* The difference between the y's */
01119   x = x1;                       /* Start x off at the first pixel */
01120   y = y1;                       /* Start y off at the first pixel */
01121
01122   if (x2 >= x1)                 /* The x-values are increasing */
01123   {
01124     xinc1 = 1;
01125     xinc2 = 1;
01126   }
01127   else                          /* The x-values are decreasing */
01128   {
01129     xinc1 = -1;
01130     xinc2 = -1;
01131   }
01132
01133   if (y2 >= y1)                 /* The y-values are increasing */
01134   {
01135     yinc1 = 1;
01136     yinc2 = 1;
01137   }
01138   else                          /* The y-values are decreasing */
01139   {
01140     yinc1 = -1;
01141     yinc2 = -1;
01142   }
01143
01144   if (deltax >= deltay)         /* There is at least one x-value for every y-value */
01145   {
01146     xinc1 = 0;                  /* Don't change the x when numerator >= denominator */
01147     yinc2 = 0;                  /* Don't change the y for every iteration */
01148     den = deltax;
01149     num = deltax / 2;
01150     numadd = deltay;
01151     numpixels = deltax;         /* There are more x-values than y-values */
01152   }
01153   else                          /* There is at least one y-value for every x-value */
01154   {
01155     xinc2 = 0;                  /* Don't change the x for every iteration */
01156     yinc1 = 0;                  /* Don't change the y when numerator >= denominator */
01157     den = deltay;
01158     num = deltay / 2;
01159     numadd = deltax;
01160     numpixels = deltay;         /* There are more y-values than x-values */
01161   }
01162
01163   for (curpixel = 0; curpixel <= numpixels; curpixel++)
01164   {
01165     PutPixel(x, y);             /* Draw the current pixel */
01166     num += numadd;              /* Increase the numerator by the top of the fraction */
01167     if (num >= den)             /* Check if numerator >= denominator */
01168     {
01169       num -= den;               /* Calculate the new numerator value */
01170       x += xinc1;               /* Change the x as appropriate */
01171       y += yinc1;               /* Change the y as appropriate */
01172     }
01173     x += xinc2;                 /* Change the x as appropriate */
01174     y += yinc2;                 /* Change the y as appropriate */
01175   }
01176 }
01177
01178 /**
01179   * @brief  Displays an polyline (between many points).
01180   * @param  Points: pointer to the points array.
01181   * @param  PointCount: Number of points.
01182   * @retval None
01183   */
01184 void LCD_PolyLine(pPoint Points, uint16_t PointCount)
01185 {
01186   int16_t X = 0, Y = 0;
01187
01188   if(PointCount < 2)
01189   {
01190     return;
01191   }
01192
01193   while(--PointCount)
01194   {
01195     X = Points->X;
01196     Y = Points->Y;
01197     Points++;
01198     LCD_DrawUniLine(X, Y, Points->X, Points->Y);
01199   }
01200 }
01201
01202 /**
01203   * @brief  Displays an relative polyline (between many points).
01204   * @param  Points: pointer to the points array.
01205   * @param  PointCount: Number of points.
01206   * @param  Closed: specifies if the draw is closed or not.
01207   *           1: closed, 0 : not closed.
01208   * @retval None
01209   */
01210 static void LCD_PolyLineRelativeClosed(pPoint Points, uint16_t PointCount, uint16_t Closed)
01211 {
01212   int16_t X = 0, Y = 0;
01213   pPoint First = Points;
01214
01215   if(PointCount < 2)
01216   {
01217     return;
01218   }
01219   X = Points->X;
01220   Y = Points->Y;
01221   while(--PointCount)
01222   {
01223     Points++;
01224     LCD_DrawUniLine(X, Y, X + Points->X, Y + Points->Y);
01225     X = X + Points->X;
01226     Y = Y + Points->Y;
01227   }
01228   if(Closed)
01229   {
01230     LCD_DrawUniLine(First->X, First->Y, X, Y);
01231   }
01232 }
01233
01234 /**
01235   * @brief  Displays a closed polyline (between many points).
01236   * @param  Points: pointer to the points array.
01237   * @param  PointCount: Number of points.
01238   * @retval None
01239   */
01240 void LCD_ClosedPolyLine(pPoint Points, uint16_t PointCount)
01241 {
01242   LCD_PolyLine(Points, PointCount);
01243   LCD_DrawUniLine(Points->X, Points->Y, (Points+PointCount-1)->X, (Points+PointCount-1)->Y);
01244 }
01245
01246 /**
01247   * @brief  Displays a relative polyline (between many points).
01248   * @param  Points: pointer to the points array.
01249   * @param  PointCount: Number of points.
01250   * @retval None
01251   */
01252 void LCD_PolyLineRelative(pPoint Points, uint16_t PointCount)
01253 {
01254   LCD_PolyLineRelativeClosed(Points, PointCount, 0);
01255 }
01256
01257 /**
01258   * @brief  Displays a closed relative polyline (between many points).
01259   * @param  Points: pointer to the points array.
01260   * @param  PointCount: Number of points.
01261   * @retval None
01262   */
01263 void LCD_ClosedPolyLineRelative(pPoint Points, uint16_t PointCount)
01264 {
01265   LCD_PolyLineRelativeClosed(Points, PointCount, 1);
01266 }
01267
01268
01269 /**
01270   * @brief  Displays a  full polyline (between many points).
01271   * @param  Points: pointer to the points array.
01272   * @param  PointCount: Number of points.
01273   * @retval None
01274   */
01275 void LCD_FillPolyLine(pPoint Points, uint16_t PointCount)
01276 {
01277   /*  public-domain code by Darel Rex Finley, 2007 */
01278   uint16_t  nodes = 0, nodeX[MAX_POLY_CORNERS], pixelX = 0, pixelY = 0, i = 0,
01279   j = 0, swap = 0;
01280   uint16_t  IMAGE_LEFT = 0, IMAGE_RIGHT = 0, IMAGE_TOP = 0, IMAGE_BOTTOM = 0;
01281
01282   IMAGE_LEFT = IMAGE_RIGHT = Points->X;
01283   IMAGE_TOP= IMAGE_BOTTOM = Points->Y;
01284
01285   for(i = 1; i < PointCount; i++)
01286   {
01287     pixelX = POLY_X(i);
01288     if(pixelX < IMAGE_LEFT)
01289     {
01290       IMAGE_LEFT = pixelX;
01291     }
01292     if(pixelX > IMAGE_RIGHT)
01293     {
01294       IMAGE_RIGHT = pixelX;
01295     }
01296
01297     pixelY = POLY_Y(i);
01298     if(pixelY < IMAGE_TOP)
01299     {
01300       IMAGE_TOP = pixelY;
01301     }
01302     if(pixelY > IMAGE_BOTTOM)
01303     {
01304       IMAGE_BOTTOM = pixelY;
01305     }
01306   }
01307
01308   LCD_SetTextColor(BackColor);
01309
01310   /*  Loop through the rows of the image. */
01311   for (pixelY = IMAGE_TOP; pixelY < IMAGE_BOTTOM; pixelY++)
01312   {
01313     /* Build a list of nodes. */
01314     nodes = 0; j = PointCount-1;
01315
01316     for (i = 0; i < PointCount; i++)
01317     {
01318       if (POLY_Y(i)<(double) pixelY && POLY_Y(j)>=(double) pixelY || POLY_Y(j)<(double) pixelY && POLY_Y(i)>=(double) pixelY)
01319       {
01320         nodeX[nodes++]=(int) (POLY_X(i)+((pixelY-POLY_Y(i))*(POLY_X(j)-POLY_X(i)))/(POLY_Y(j)-POLY_Y(i)));
01321       }
01322       j = i;
01323     }
01324
01325     /* Sort the nodes, via a simple "Bubble" sort. */
01326     i = 0;
01327     while (i < nodes-1)
01328     {
01329       if (nodeX[i]>nodeX[i+1])
01330       {
01331         swap = nodeX[i];
01332         nodeX[i] = nodeX[i+1];
01333         nodeX[i+1] = swap;
01334         if(i)
01335         {
01336           i--;
01337         }
01338       }
01339       else
01340       {
01341         i++;
01342       }
01343     }
01344
01345     /*  Fill the pixels between node pairs. */
01346     for (i = 0; i < nodes; i+=2)
01347     {
01348       if(nodeX[i] >= IMAGE_RIGHT)
01349       {
01350         break;
01351       }
01352       if(nodeX[i+1] > IMAGE_LEFT)
01353       {
01354         if (nodeX[i] < IMAGE_LEFT)
01355         {
01356           nodeX[i]=IMAGE_LEFT;
01357         }
01358         if(nodeX[i+1] > IMAGE_RIGHT)
01359         {
01360           nodeX[i+1] = IMAGE_RIGHT;
01361         }
01362         LCD_SetTextColor(BackColor);
01363         LCD_DrawLine(pixelY, nodeX[i+1], nodeX[i+1] - nodeX[i], LCD_DIR_HORIZONTAL);
01364         LCD_SetTextColor(TextColor);
01365         PutPixel(pixelY, nodeX[i+1]);
01366         PutPixel(pixelY, nodeX[i]);
01367         /* for (j=nodeX[i]; j<nodeX[i+1]; j++) PutPixel(j,pixelY); */
01368       }
01369     }
01370   }
01371
01372   /* draw the edges */
01373   LCD_SetTextColor(TextColor);
01374 }
01375
01376 /**
01377   * @brief  Reset LCD control line(/CS) and Send Start-Byte
01378   * @param  Start_Byte: the Start-Byte to be sent
01379   * @retval None
01380   */
01381 void LCD_nCS_StartByte(uint8_t Start_Byte)
01382 {
01383   LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_RESET);
01384
01385   SPI_I2S_SendData(LCD_SPI, Start_Byte);
01386
01387   while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
01388   {
01389   }
01390 }
01391
01392
01393 /**
01394   * @brief  Writes index to select the LCD register.
01395   * @param  LCD_Reg: address of the selected register.
01396   * @retval None
01397   */
01398 void LCD_WriteRegIndex(uint8_t LCD_Reg)
01399 {
01400   /* Reset LCD control line(/CS) and Send Start-Byte */
01401   LCD_nCS_StartByte(START_BYTE | SET_INDEX);
01402
01403   /* Write 16-bit Reg Index (High Byte is 0) */
01404   SPI_I2S_SendData(LCD_SPI, 0x00);
01405
01406   while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
01407   {
01408   }
01409
01410   SPI_I2S_SendData(LCD_SPI, LCD_Reg);
01411
01412   while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
01413   {
01414   }
01415
01416   LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
01417 }
01418
01419
01420 /**
01421   * @brief  Writes to the selected LCD ILI9320 register.
01422   * @param  LCD_Reg: address of the selected register.
01423   * @param  LCD_RegValue: value to write to the selected register.
01424   * @retval None
01425   */
01426 static void LCD_WriteRegILI9320(uint8_t LCD_Reg, uint16_t LCD_RegValue)
01427 {
01428   /* Write 16-bit Index (then Write Reg) */
01429   LCD_WriteRegIndex(LCD_Reg);
01430
01431   /* Write 16-bit Reg */
01432   /* Reset LCD control line(/CS) and Send Start-Byte */
01433   LCD_nCS_StartByte(START_BYTE | LCD_WRITE_REG);
01434
01435   SPI_I2S_SendData(LCD_SPI, LCD_RegValue>>8);
01436
01437   while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
01438   {
01439   }
01440
01441   SPI_I2S_SendData(LCD_SPI, (LCD_RegValue & 0xFF));
01442
01443   while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
01444   {
01445   }
01446
01447   LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
01448 }
01449
01450
01451 /**
01452   * @brief  Reads the selected LCD Register.
01453   * @param  LCD_Reg: address of the selected register.
01454   * @retval LCD Register Value.
01455   */
01456 uint16_t LCD_ReadReg(uint8_t LCD_Reg)
01457 {
01458   uint16_t tmp = 0;
01459   uint8_t i = 0;
01460
01461   /* LCD_SPI prescaler: 4 */
01462   LCD_SPI->CR1 &= 0xFFC7;
01463   LCD_SPI->CR1 |= 0x0008;
01464   /* Write 16-bit Index (then Read Reg) */
01465   LCD_WriteRegIndex(LCD_Reg);
01466   /* Read 16-bit Reg */
01467   /* Reset LCD control line(/CS) and Send Start-Byte */
01468   LCD_nCS_StartByte(START_BYTE | LCD_READ_REG);
01469
01470   for(i = 0; i < 5; i++)
01471   {
01472     SPI_I2S_SendData(LCD_SPI, 0xFF);
01473     while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
01474     {
01475     }
01476     /* One byte of invalid dummy data read after the start byte */
01477     while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_RXNE) == RESET)
01478     {
01479     }
01480     SPI_I2S_ReceiveData(LCD_SPI);
01481   }
01482
01483   SPI_I2S_SendData(LCD_SPI, 0xFF);
01484
01485   /* Read upper byte */
01486   while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
01487   {
01488   }
01489
01490   /* Read lower byte */
01491   while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_RXNE) == RESET)
01492   {
01493   }
01494   tmp = SPI_I2S_ReceiveData(LCD_SPI);
01495
01496
01497   SPI_I2S_SendData(LCD_SPI, 0xFF);
01498   while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
01499   {
01500   }
01501
01502   /* Read lower byte */
01503   while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_RXNE) == RESET)
01504   {
01505   }
01506
01507   tmp = ((tmp & 0xFF) << 8) | SPI_I2S_ReceiveData(LCD_SPI);
01508   LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
01509
01510   /* LCD_SPI prescaler: 2 */
01511   LCD_SPI->CR1 &= 0xFFC7;
01512
01513   return tmp;
01514 }
01515
01516
01517 /**
01518   * @brief  Prepare to write to the LCD RAM.
01519   * @param  None
01520   * @retval None
01521   */
01522 void LCD_WriteRAM_Prepare(void)
01523 {
01524   LCD_WriteRegIndex(LCD_REG_34); /* Select GRAM Reg */
01525
01526   /* Reset LCD control line(/CS) and Send Start-Byte */
01527   LCD_nCS_StartByte(START_BYTE | LCD_WRITE_REG);
01528 }
01529
01530
01531 /**
01532   * @brief  Writes 1 word to the LCD RAM.
01533   * @param  RGB_Code: the pixel color in RGB mode (5-6-5).
01534   * @retval None
01535   */
01536 void LCD_WriteRAMWord(uint16_t RGB_Code)
01537 {
01538
01539   LCD_WriteRAM_Prepare();
01540
01541   LCD_WriteRAM(RGB_Code);
01542
01543   LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
01544 }
01545
01546
01547 /**
01548   * @brief  Writes to the selected LCD HX8312 register.
01549   * @param  LCD_Reg: address of the selected register.
01550   * @param  LCD_RegValue: value to write to the selected register.
01551   * @retval None
01552   */
01553 static void LCD_WriteRegHX8312(uint8_t LCD_Reg, uint8_t LCD_RegValue)
01554 {
01555   uint16_t tmp = 0;
01556
01557   LCD_CtrlLinesWrite(LCD_NWR_GPIO_PORT, LCD_NWR_PIN, Bit_RESET);
01558   LCD_CtrlLinesWrite(LCD_RS_GPIO_PORT, LCD_RS_PIN, Bit_RESET);
01559   LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_RESET);
01560
01561   tmp = LCD_Reg << 8;
01562   tmp |= LCD_RegValue;
01563
01564   SPI_I2S_SendData(LCD_SPI, tmp);
01565
01566   while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
01567   {
01568   }
01569
01570   LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
01571 }
01572
01573
01574 /**
01575   * @brief  Writes to the selected LCD register.
01576   * @param  LCD_Reg: address of the selected register.
01577   * @param  LCD_RegValue: value to write to the selected register.
01578   * @retval None
01579   */
01580 void LCD_WriteReg(uint8_t LCD_Reg, uint16_t LCD_RegValue)
01581 {
01582   if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
01583   {
01584     LCD_WriteRegILI9320(LCD_Reg, LCD_RegValue);
01585   }
01586   else if(LCDType == LCD_HX8312)
01587   {
01588     LCD_WriteRegHX8312(LCD_Reg, ((uint8_t)LCD_RegValue));
01589   }
01590 }
01591
01592
01593 /**
01594   * @brief  Writes to the LCD RAM.
01595   * @param  RGB_Code: the pixel color in RGB mode (5-6-5).
01596   * @retval None
01597   */
01598 void LCD_WriteRAM(uint16_t RGB_Code)
01599 {
01600   if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
01601   {
01602     SPI_I2S_SendData(LCD_SPI, RGB_Code >> 8);
01603     while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
01604     {
01605     }
01606     SPI_I2S_SendData(LCD_SPI, RGB_Code & 0xFF);
01607     while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
01608     {
01609     }
01610   }
01611
01612   if(LCDType == LCD_HX8312)
01613   {
01614     LCD_CtrlLinesWrite(LCD_NWR_GPIO_PORT, LCD_NWR_PIN, Bit_RESET);
01615     LCD_CtrlLinesWrite(LCD_RS_GPIO_PORT, LCD_RS_PIN, Bit_SET);
01616     LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_RESET);
01617     SPI_I2S_SendData(LCD_SPI, RGB_Code);
01618
01619     while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
01620     {
01621     }
01622
01623     LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
01624   }
01625 }
01626
01627
01628 /**
01629   * @brief  Power on the LCD.
01630   * @param  None
01631   * @retval None
01632   */
01633 void LCD_PowerOn(void)
01634 {
01635   if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
01636   {
01637     /* Power On sequence ---------------------------------------------------------*/
01638     LCD_WriteReg(LCD_REG_16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
01639     LCD_WriteReg(LCD_REG_17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */
01640     LCD_WriteReg(LCD_REG_18, 0x0000); /* VREG1OUT voltage */
01641     LCD_WriteReg(LCD_REG_19, 0x0000); /* VDV[4:0] for VCOM amplitude */
01642     _delay_(20);               /* Dis-charge capacitor power voltage (200ms) */
01643     LCD_WriteReg(LCD_REG_16, 0x17B0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
01644     LCD_WriteReg(LCD_REG_17, 0x0137); /* DC1[2:0], DC0[2:0], VC[2:0] */
01645     _delay_(5);                /* Delay 50 ms */
01646     LCD_WriteReg(LCD_REG_18, 0x0139); /* VREG1OUT voltage */
01647     _delay_(5);                /* delay 50 ms */
01648     LCD_WriteReg(LCD_REG_19, 0x1d00); /* VDV[4:0] for VCOM amplitude */
01649     LCD_WriteReg(LCD_REG_41, 0x0013); /* VCM[4:0] for VCOMH */
01650     _delay_(5);                /* delay 50 ms */
01651     LCD_WriteReg(LCD_REG_7, 0x0173);  /* 262K color and display ON */
01652   }
01653   else if(LCDType == LCD_HX8312)
01654   {
01655     /* Power On Set */
01656     LCD_WriteReg(LCD_REG_28, 0x73);
01657     LCD_WriteReg(LCD_REG_36, 0x74);
01658     LCD_WriteReg(LCD_REG_30, 0x01);
01659     LCD_WriteReg(LCD_REG_24, 0xC1);
01660     _delay_(1); /* Delay 10 ms */
01661     LCD_WriteReg(LCD_REG_24, 0xE1);
01662     LCD_WriteReg(LCD_REG_24, 0xF1);
01663     _delay_(6); /* Delay 60 ms */
01664     LCD_WriteReg(LCD_REG_24, 0xF5);
01665     _delay_(6); /* Delay 60 ms */
01666     LCD_WriteReg(LCD_REG_27, 0x09);
01667     _delay_(1); /* Delay 10 ms */
01668     LCD_WriteReg(LCD_REG_31, 0x11);
01669     LCD_WriteReg(LCD_REG_32, 0x0E);
01670     LCD_WriteReg(LCD_REG_30, 0x81);
01671     _delay_(1); /* Delay 10 ms */
01672   }
01673 }
01674
01675
01676 /**
01677   * @brief  Enables the Display.
01678   * @param  None
01679   * @retval None
01680   */
01681 void LCD_DisplayOn(void)
01682 {
01683   if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
01684   {
01685     /* Display On */
01686     LCD_WriteReg(LCD_REG_7, 0x0173); /* 262K color and display ON */
01687   }
01688   else if(LCDType == LCD_HX8312)
01689   {
01690     LCD_WriteReg(LCD_REG_1, 0x50);
01691     LCD_WriteReg(LCD_REG_5, 0x04);
01692     /* Display On */
01693     LCD_WriteReg(LCD_REG_0, 0x80);
01694     LCD_WriteReg(LCD_REG_59, 0x01);
01695     _delay_(4); /* Delay 40 ms */
01696     LCD_WriteReg(LCD_REG_0, 0x20);
01697   }
01698 }
01699
01700
01701 /**
01702   * @brief  Disables the Display.
01703   * @param  None
01704   * @retval None
01705   */
01706 void LCD_DisplayOff(void)
01707 {
01708   if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
01709   {
01710     /* Display Off */
01711     LCD_WriteReg(LCD_REG_7, 0x0);
01712   }
01713   else if(LCDType == LCD_HX8312)
01714   {
01715     /* Display Off */
01716     LCD_WriteReg(LCD_REG_0, 0xA0);
01717     _delay_(4);  /* Delay 40 ms */
01718     LCD_WriteReg(LCD_REG_59, 0x00);
01719   }
01720 }
01721
01722
01723 /**
01724   * @brief  Configures LCD control lines in Output Push-Pull mode.
01725   * @param  None
01726   * @retval None
01727   */
01728 void LCD_CtrlLinesConfig(void)
01729 {
01730   GPIO_InitTypeDef GPIO_InitStructure;
01731
01732   /* Enable GPIO clock */
01733   RCC_APB2PeriphClockCmd(LCD_NCS_GPIO_CLK | LCD_NWR_GPIO_CLK | LCD_RS_GPIO_CLK, ENABLE);
01734
01735   /* Configure NCS in Output Push-Pull mode */
01736   GPIO_InitStructure.GPIO_Pin = LCD_NCS_PIN;
01737   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
01738   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
01739   GPIO_Init(LCD_NCS_GPIO_PORT, &GPIO_InitStructure);
01740
01741   /* Configure NWR(RNW), RS in Output Push-Pull mode */
01742   GPIO_InitStructure.GPIO_Pin = LCD_RS_PIN;
01743   GPIO_Init(LCD_RS_GPIO_PORT, &GPIO_InitStructure);
01744
01745   GPIO_InitStructure.GPIO_Pin = LCD_NWR_PIN;
01746   GPIO_Init(LCD_NWR_GPIO_PORT, &GPIO_InitStructure);
01747
01748   LCD_CtrlLinesWrite(LCD_NWR_GPIO_PORT, LCD_NWR_PIN, Bit_SET);
01749   LCD_CtrlLinesWrite(LCD_RS_GPIO_PORT, LCD_RS_PIN, Bit_SET);
01750 }
01751
01752
01753 /**
01754   * @brief  Sets or reset LCD control lines.
01755   * @param  GPIOx: where x can be B or D to select the GPIO peripheral.
01756   * @param  CtrlPins: the Control line.
01757   *   This parameter can be:
01758   *     @arg LCD_NCS_PIN: Chip Select pin
01759   *     @arg LCD_NWR_PIN: Read/Write Selection pin
01760   *     @arg LCD_RS_PIN: Register/RAM Selection pin
01761   * @param  BitVal: specifies the value to be written to the selected bit.
01762   *   This parameter can be:
01763   *     @arg Bit_RESET: to clear the port pin
01764   *     @arg Bit_SET: to set the port pin
01765   * @retval None
01766   */
01767 void LCD_CtrlLinesWrite(GPIO_TypeDef* GPIOx, uint16_t CtrlPins, BitAction BitVal)
01768 {
01769   /* Set or Reset the control line */
01770   GPIO_WriteBit(GPIOx, CtrlPins, BitVal);
01771 }
01772
01773 /**
01774   * @brief  Configures the LCD_SPI interface.
01775   * @param  None
01776   * @retval None
01777   */
01778 void LCD_SPIConfig(void)
01779 {
01780   SPI_InitTypeDef    SPI_InitStructure;
01781   GPIO_InitTypeDef   GPIO_InitStructure;
01782
01783   /* Enable GPIO clock */
01784   RCC_APB2PeriphClockCmd(LCD_SPI_SCK_GPIO_CLK | LCD_SPI_MISO_GPIO_CLK | LCD_SPI_MOSI_GPIO_CLK, ENABLE);
01785
01786   /* Enable SPI clock  */
01787   RCC_APB1PeriphClockCmd(LCD_SPI_CLK, ENABLE);
01788
01789   /* Configure SPI pins: SCK, MISO and MOSI */
01790   GPIO_InitStructure.GPIO_Pin = LCD_SPI_SCK_PIN;
01791   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
01792   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
01793   GPIO_Init(LCD_SPI_SCK_GPIO_PORT, &GPIO_InitStructure);
01794
01795   GPIO_InitStructure.GPIO_Pin = LCD_SPI_MISO_PIN;
01796   GPIO_Init(LCD_SPI_MISO_GPIO_PORT, &GPIO_InitStructure);
01797
01798   GPIO_InitStructure.GPIO_Pin = LCD_SPI_MOSI_PIN;
01799   GPIO_Init(LCD_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure);
01800
01801   SPI_I2S_DeInit(LCD_SPI);
01802
01803   /* SPI Config */
01804   SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
01805   SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
01806
01807   if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
01808   {
01809     SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
01810     SPI_InitStructure.SPI_CPOL = SPI_CPOL_High;
01811     SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge;
01812   }
01813   else if(LCDType == LCD_HX8312)
01814   {
01815     SPI_InitStructure.SPI_DataSize = SPI_DataSize_16b;
01816     SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low;
01817     SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge;
01818   }
01819   SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
01820   SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
01821   SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
01822
01823   SPI_Init(LCD_SPI, &SPI_InitStructure);
01824
01825   /* SPI enable */
01826   SPI_Cmd(LCD_SPI, ENABLE);
01827 }
01828
01829 /**
01830   * @brief  Displays a pixel.
01831   * @param  x: pixel x.
01832   * @param  y: pixel y.
01833   * @retval None
01834   */
01835 static void PutPixel(int16_t x, int16_t y)
01836 {
01837   if(x < 0 || x > 239 || y < 0 || y > 319)
01838   {
01839     return;
01840   }
01841   LCD_DrawLine(x, y, 1, LCD_DIR_HORIZONTAL);
01842 }
01843
01844 #ifndef USE_Delay
01845 /**
01846   * @brief  Inserts a delay time.
01847   * @param  nCount: specifies the delay time length.
01848   * @retval None
01849   */
01850 static void delay(vu32 nCount)
01851 {
01852   vu32 index = 0;
01853   for(index = (100000 * nCount); index != 0; index--)
01854   {
01855   }
01856 }
01857 #endif /* USE_Delay*/
01858 /**
01859   * @}
01860   */
01861
01862 /**
01863   * @}
01864   */
01865
01866 /**
01867   * @}
01868   */
01869
01870 /**
01871   * @}
01872   */
01873
01874 /**
01875   * @}
01876   */
01877
01878 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm3210b_eval_lcd.h Source File

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • STM3210B_EVAL

stm3210b_eval_lcd.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm3210b_eval_lcd.h
00004   * @author  MCD Application Team
00005   * @version V4.5.0
00006   * @date    07-March-2011
00007   * @brief   This file contains all the functions prototypes for the stm3210b_eval_lcd
00008   *          firmware driver.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00013   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00014   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00015   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00016   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00017   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00018   *
00019   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00020   ******************************************************************************
00021   */
00022
00023 /* Define to prevent recursive inclusion -------------------------------------*/
00024 #ifndef __STM3210B_EVAL_LCD_H
00025 #define __STM3210B_EVAL_LCD_H
00026
00027 #ifdef __cplusplus
00028  extern "C" {
00029 #endif
00030
00031 /* Includes ------------------------------------------------------------------*/
00032 #include "stm32f10x.h"
00033 #include "../Common/fonts.h"
00034
00035 /** @addtogroup Utilities
00036   * @{
00037   */
00038
00039 /** @addtogroup STM32_EVAL
00040   * @{
00041   */
00042
00043 /** @addtogroup STM3210B_EVAL
00044   * @{
00045   */
00046
00047 /** @addtogroup STM3210B_EVAL_LCD
00048   * @{
00049   */
00050
00051
00052 /** @defgroup STM3210B_EVAL_LCD_Exported_Types
00053   * @{
00054   */
00055 typedef struct
00056 {
00057   int16_t X;
00058   int16_t Y;
00059 } Point, * pPoint;
00060 /**
00061   * @}
00062   */
00063
00064
00065
00066 /** @defgroup STM3210B_EVAL_LCD_Exported_Constants
00067   * @{
00068   */
00069
00070 /**
00071  * @brief Uncomment the line below if you want to use LCD_DrawBMP function to
00072  *        display a bitmap picture on the LCD. This function assumes that the bitmap
00073  *        file is loaded in the SPI Flash (mounted on STM3210B-EVAL board), however
00074  *        user can tailor it according to his application hardware requirement.
00075  */
00076 /*#define USE_LCD_DrawBMP*/
00077
00078 /**
00079  * @brief Uncomment the line below if you want to use user defined Delay function
00080  *        (for precise timing), otherwise default _delay_ function defined within
00081  *         this driver is used (less precise timing).
00082  */
00083 /* #define USE_Delay */
00084
00085 #ifdef USE_Delay
00086 #include "main.h"
00087
00088   #define _delay_     Delay  /* !< User can provide more timing precise _delay_ function
00089                                    (with 10ms time base), using SysTick for example */
00090 #else
00091   #define _delay_     delay      /* !< Default _delay_ function with less precise timing */
00092 #endif
00093
00094
00095 /**
00096   * @brief  LCD Control pins
00097   */
00098 #define LCD_NCS_PIN             GPIO_Pin_2
00099 #define LCD_NCS_GPIO_PORT       GPIOB
00100 #define LCD_NCS_GPIO_CLK        RCC_APB2Periph_GPIOB
00101 #define LCD_NWR_PIN             GPIO_Pin_15
00102 #define LCD_NWR_GPIO_PORT       GPIOD
00103 #define LCD_NWR_GPIO_CLK        RCC_APB2Periph_GPIOD
00104 #define LCD_RS_PIN              GPIO_Pin_7
00105 #define LCD_RS_GPIO_PORT        GPIOD
00106 #define LCD_RS_GPIO_CLK         RCC_APB2Periph_GPIOD
00107
00108 /**
00109   * @brief  LCD SPI Interface pins
00110   */
00111 #define LCD_SPI                             SPI2
00112 #define LCD_SPI_CLK                       RCC_APB1Periph_SPI2
00113 #define LCD_SPI_SCK_PIN         GPIO_Pin_13
00114 #define LCD_SPI_SCK_GPIO_PORT   GPIOB
00115 #define LCD_SPI_SCK_GPIO_CLK    RCC_APB2Periph_GPIOB
00116 #define LCD_SPI_MISO_PIN        GPIO_Pin_14
00117 #define LCD_SPI_MISO_GPIO_PORT  GPIOB
00118 #define LCD_SPI_MISO_GPIO_CLK   RCC_APB2Periph_GPIOB
00119 #define LCD_SPI_MOSI_PIN        GPIO_Pin_15
00120 #define LCD_SPI_MOSI_GPIO_PORT  GPIOB
00121 #define LCD_SPI_MOSI_GPIO_CLK   RCC_APB2Periph_GPIOB
00122
00123 /**
00124   * @brief  LCD Registers
00125   */
00126 #define LCD_REG_0             0x00
00127 #define LCD_REG_1             0x01
00128 #define LCD_REG_2             0x02
00129 #define LCD_REG_3             0x03
00130 #define LCD_REG_4             0x04
00131 #define LCD_REG_5             0x05
00132 #define LCD_REG_6             0x06
00133 #define LCD_REG_7             0x07
00134 #define LCD_REG_8             0x08
00135 #define LCD_REG_9             0x09
00136 #define LCD_REG_10            0x0A
00137 #define LCD_REG_12            0x0C
00138 #define LCD_REG_13            0x0D
00139 #define LCD_REG_14            0x0E
00140 #define LCD_REG_15            0x0F
00141 #define LCD_REG_16            0x10
00142 #define LCD_REG_17            0x11
00143 #define LCD_REG_18            0x12
00144 #define LCD_REG_19            0x13
00145 #define LCD_REG_20            0x14
00146 #define LCD_REG_21            0x15
00147 #define LCD_REG_22            0x16
00148 #define LCD_REG_23            0x17
00149 #define LCD_REG_24            0x18
00150 #define LCD_REG_25            0x19
00151 #define LCD_REG_26            0x1A
00152 #define LCD_REG_27            0x1B
00153 #define LCD_REG_28            0x1C
00154 #define LCD_REG_29            0x1D
00155 #define LCD_REG_30            0x1E
00156 #define LCD_REG_31            0x1F
00157 #define LCD_REG_32            0x20
00158 #define LCD_REG_33            0x21
00159 #define LCD_REG_34            0x22
00160 #define LCD_REG_36            0x24
00161 #define LCD_REG_37            0x25
00162 #define LCD_REG_40            0x28
00163 #define LCD_REG_41            0x29
00164 #define LCD_REG_43            0x2B
00165 #define LCD_REG_45            0x2D
00166 #define LCD_REG_48            0x30
00167 #define LCD_REG_49            0x31
00168 #define LCD_REG_50            0x32
00169 #define LCD_REG_51            0x33
00170 #define LCD_REG_52            0x34
00171 #define LCD_REG_53            0x35
00172 #define LCD_REG_54            0x36
00173 #define LCD_REG_55            0x37
00174 #define LCD_REG_56            0x38
00175 #define LCD_REG_57            0x39
00176 #define LCD_REG_59            0x3B
00177 #define LCD_REG_60            0x3C
00178 #define LCD_REG_61            0x3D
00179 #define LCD_REG_62            0x3E
00180 #define LCD_REG_63            0x3F
00181 #define LCD_REG_64            0x40
00182 #define LCD_REG_65            0x41
00183 #define LCD_REG_66            0x42
00184 #define LCD_REG_67            0x43
00185 #define LCD_REG_68            0x44
00186 #define LCD_REG_69            0x45
00187 #define LCD_REG_70            0x46
00188 #define LCD_REG_71            0x47
00189 #define LCD_REG_72            0x48
00190 #define LCD_REG_73            0x49
00191 #define LCD_REG_74            0x4A
00192 #define LCD_REG_75            0x4B
00193 #define LCD_REG_76            0x4C
00194 #define LCD_REG_77            0x4D
00195 #define LCD_REG_78            0x4E
00196 #define LCD_REG_79            0x4F
00197 #define LCD_REG_80            0x50
00198 #define LCD_REG_81            0x51
00199 #define LCD_REG_82            0x52
00200 #define LCD_REG_83            0x53
00201 #define LCD_REG_96            0x60
00202 #define LCD_REG_97            0x61
00203 #define LCD_REG_106           0x6A
00204 #define LCD_REG_118           0x76
00205 #define LCD_REG_128           0x80
00206 #define LCD_REG_129           0x81
00207 #define LCD_REG_130           0x82
00208 #define LCD_REG_131           0x83
00209 #define LCD_REG_132           0x84
00210 #define LCD_REG_133           0x85
00211 #define LCD_REG_134           0x86
00212 #define LCD_REG_135           0x87
00213 #define LCD_REG_136           0x88
00214 #define LCD_REG_137           0x89
00215 #define LCD_REG_139           0x8B
00216 #define LCD_REG_140           0x8C
00217 #define LCD_REG_141           0x8D
00218 #define LCD_REG_143           0x8F
00219 #define LCD_REG_144           0x90
00220 #define LCD_REG_145           0x91
00221 #define LCD_REG_146           0x92
00222 #define LCD_REG_147           0x93
00223 #define LCD_REG_148           0x94
00224 #define LCD_REG_149           0x95
00225 #define LCD_REG_150           0x96
00226 #define LCD_REG_151           0x97
00227 #define LCD_REG_152           0x98
00228 #define LCD_REG_153           0x99
00229 #define LCD_REG_154           0x9A
00230 #define LCD_REG_157           0x9D
00231 #define LCD_REG_192           0xC0
00232 #define LCD_REG_193           0xC1
00233 #define LCD_REG_227           0xE3
00234 #define LCD_REG_229           0xE5
00235 #define LCD_REG_231           0xE7
00236 #define LCD_REG_239           0xEF
00237
00238
00239 /**
00240   * @brief  LCD color
00241   */
00242 #define LCD_COLOR_WHITE          0xFFFF
00243 #define LCD_COLOR_BLACK          0x0000
00244 #define LCD_COLOR_GREY           0xF7DE
00245 #define LCD_COLOR_BLUE           0x001F
00246 #define LCD_COLOR_BLUE2          0x051F
00247 #define LCD_COLOR_RED            0xF800
00248 #define LCD_COLOR_MAGENTA        0xF81F
00249 #define LCD_COLOR_GREEN          0x07E0
00250 #define LCD_COLOR_CYAN           0x7FFF
00251 #define LCD_COLOR_YELLOW         0xFFE0
00252
00253 /**
00254   * @brief  LCD Lines depending on the chosen fonts.
00255   */
00256 #define LCD_LINE_0               LINE(0)
00257 #define LCD_LINE_1               LINE(1)
00258 #define LCD_LINE_2               LINE(2)
00259 #define LCD_LINE_3               LINE(3)
00260 #define LCD_LINE_4               LINE(4)
00261 #define LCD_LINE_5               LINE(5)
00262 #define LCD_LINE_6               LINE(6)
00263 #define LCD_LINE_7               LINE(7)
00264 #define LCD_LINE_8               LINE(8)
00265 #define LCD_LINE_9               LINE(9)
00266 #define LCD_LINE_10              LINE(10)
00267 #define LCD_LINE_11              LINE(11)
00268 #define LCD_LINE_12              LINE(12)
00269 #define LCD_LINE_13              LINE(13)
00270 #define LCD_LINE_14              LINE(14)
00271 #define LCD_LINE_15              LINE(15)
00272 #define LCD_LINE_16              LINE(16)
00273 #define LCD_LINE_17              LINE(17)
00274 #define LCD_LINE_18              LINE(18)
00275 #define LCD_LINE_19              LINE(19)
00276 #define LCD_LINE_20              LINE(20)
00277 #define LCD_LINE_21              LINE(21)
00278 #define LCD_LINE_22              LINE(22)
00279 #define LCD_LINE_23              LINE(23)
00280 #define LCD_LINE_24              LINE(24)
00281 #define LCD_LINE_25              LINE(25)
00282 #define LCD_LINE_26              LINE(26)
00283 #define LCD_LINE_27              LINE(27)
00284 #define LCD_LINE_28              LINE(28)
00285 #define LCD_LINE_29              LINE(29)
00286
00287 /**
00288   * @brief LCD default font
00289   */
00290 #define LCD_DEFAULT_FONT         Font16x24
00291
00292 /**
00293   * @brief  LCD Direction
00294   */
00295 #define LCD_DIR_HORIZONTAL       0x0000
00296 #define LCD_DIR_VERTICAL         0x0001
00297
00298 /**
00299   * @brief  LCD Size (Width and Height)
00300   */
00301 #define LCD_PIXEL_WIDTH          0x0140
00302 #define LCD_PIXEL_HEIGHT         0x00F0
00303
00304 /**
00305   * @}
00306   */
00307
00308 /** @defgroup STM3210B_EVAL_LCD_Exported_Macros
00309   * @{
00310   */
00311 #define ASSEMBLE_RGB(R, G, B)    ((((R)& 0xF8) << 8) | (((G) & 0xFC) << 3) | (((B) & 0xF8) >> 3))
00312 /**
00313   * @}
00314   */
00315
00316
00317
00318 /** @defgroup STM3210B_EVAL_LCD_Exported_Functions
00319   * @{
00320   */
00321 void LCD_DeInit(void);
00322 void LCD_Setup(void);
00323 void STM3210B_LCD_Init(void);
00324 void LCD_SetColors(__IO uint16_t _TextColor, __IO uint16_t _BackColor);
00325 void LCD_GetColors(__IO uint16_t *_TextColor, __IO uint16_t *_BackColor);
00326 void LCD_SetTextColor(__IO uint16_t Color);
00327 void LCD_SetBackColor(__IO uint16_t Color);
00328 void LCD_ClearLine(uint8_t Line);
00329 void LCD_Clear(uint16_t Color);
00330 void LCD_SetCursor(uint8_t Xpos, uint16_t Ypos);
00331 void LCD_DrawChar(uint8_t Xpos, uint16_t Ypos, const uint16_t *c);
00332 void LCD_DisplayChar(uint8_t Line, uint16_t Column, uint8_t Ascii);
00333 void LCD_SetFont(sFONT *fonts);
00334 sFONT *LCD_GetFont(void);
00335 void LCD_DisplayStringLine(uint8_t Line, uint8_t *ptr);
00336 void LCD_SetDisplayWindow(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width);
00337 void LCD_WindowModeDisable(void);
00338 void LCD_DrawLine(uint8_t Xpos, uint16_t Ypos, uint16_t Length, uint8_t Direction);
00339 void LCD_DrawRect(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width);
00340 void LCD_DrawCircle(uint8_t Xpos, uint16_t Ypos, uint16_t Radius);
00341 void LCD_DrawMonoPict(const uint32_t *Pict);
00342 void LCD_DrawBMP(uint32_t BmpAddress);
00343 void LCD_DrawUniLine(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2);
00344 void LCD_DrawFullRect(uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height);
00345 void LCD_DrawFullCircle(uint16_t Xpos, uint16_t Ypos, uint16_t Radius);
00346 void LCD_PolyLine(pPoint Points, uint16_t PointCount);
00347 void LCD_PolyLineRelative(pPoint Points, uint16_t PointCount);
00348 void LCD_ClosedPolyLine(pPoint Points, uint16_t PointCount);
00349 void LCD_ClosedPolyLineRelative(pPoint Points, uint16_t PointCount);
00350 void LCD_FillPolyLine(pPoint Points, uint16_t PointCount);
00351
00352 void LCD_nCS_StartByte(uint8_t Start_Byte);
00353 void LCD_WriteRegIndex(uint8_t LCD_Reg);
00354 void LCD_WriteReg(uint8_t LCD_Reg, uint16_t LCD_RegValue);
00355 void LCD_WriteRAM_Prepare(void);
00356 void LCD_WriteRAMWord(uint16_t RGB_Code);
00357 uint16_t LCD_ReadReg(uint8_t LCD_Reg);
00358 void LCD_WriteRAM(uint16_t RGB_Code);
00359 void LCD_PowerOn(void);
00360 void LCD_DisplayOn(void);
00361 void LCD_DisplayOff(void);
00362
00363 void LCD_CtrlLinesConfig(void);
00364 void LCD_CtrlLinesWrite(GPIO_TypeDef* GPIOx, uint16_t CtrlPins, BitAction BitVal);
00365 void LCD_SPIConfig(void);
00366
00367 /**
00368   * @}
00369   */
00370
00371 #ifdef __cplusplus
00372 }
00373 #endif
00374
00375 #endif /* __STM3210B_EVAL_LCD_H */
00376
00377
00378 /**
00379   * @}
00380   */
00381
00382 /**
00383   * @}
00384   */
00385
00386 /**
00387   * @}
00388   */
00389
00390 /**
00391   * @}
00392   */
00393
00394 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm3210c_eval.c Source File

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • STM3210C_EVAL

stm3210c_eval.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm3210c_eval.c
00004   * @author  MCD Application Team
00005   * @version V4.5.0
00006   * @date    07-March-2011
00007   * @brief   This file provides
00008   *            - set of firmware functions to manage Leds, push-button and COM ports
00009   *            - low level initialization functions for SD card (on SPI) and I2C
00010   *              serial EEPROM (sEE)
00011   *          available on STM3210C-EVAL evaluation board from STMicroelectronics.
00012   ******************************************************************************
00013   * @attention
00014   *
00015   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00016   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00017   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00018   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00019   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00020   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00021   *
00022   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00023   ******************************************************************************
00024   */
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm3210c_eval.h"
00028 #include "stm32f10x_spi.h"
00029 #include "stm32f10x_i2c.h"
00030 #include "stm32f10x_dma.h"
00031
00032 /** @addtogroup Utilities
00033   * @{
00034   */
00035
00036 /** @addtogroup STM32_EVAL
00037   * @{
00038   */
00039
00040 /** @addtogroup STM3210C_EVAL
00041   * @{
00042   */
00043
00044 /** @defgroup STM3210C_EVAL_LOW_LEVEL
00045   * @brief This file provides firmware functions to manage Leds, push-buttons,
00046   *        COM ports, SD card on SPI and EEPROM (sEE) available on STM3210C-EVAL
00047   *        evaluation board from STMicroelectronics.
00048   * @{
00049   */
00050
00051 /** @defgroup STM3210C_EVAL_LOW_LEVEL_Private_TypesDefinitions
00052   * @{
00053   */
00054 /**
00055   * @}
00056   */
00057
00058
00059 /** @defgroup STM3210C_EVAL_LOW_LEVEL_Private_Defines
00060   * @{
00061   */
00062 /**
00063   * @}
00064   */
00065
00066
00067 /** @defgroup STM3210C_EVAL_LOW_LEVEL_Private_Macros
00068   * @{
00069   */
00070 /**
00071   * @}
00072   */
00073
00074
00075 /** @defgroup STM3210C_EVAL_LOW_LEVEL_Private_Variables
00076   * @{
00077   */
00078 GPIO_TypeDef* GPIO_PORT[LEDn] = {LED1_GPIO_PORT, LED2_GPIO_PORT, LED3_GPIO_PORT,
00079                                  LED4_GPIO_PORT};
00080 const uint16_t GPIO_PIN[LEDn] = {LED1_PIN, LED2_PIN, LED3_PIN,
00081                                  LED4_PIN};
00082 const uint32_t GPIO_CLK[LEDn] = {LED1_GPIO_CLK, LED2_GPIO_CLK, LED3_GPIO_CLK,
00083                                  LED4_GPIO_CLK};
00084
00085 GPIO_TypeDef* BUTTON_PORT[BUTTONn] = {WAKEUP_BUTTON_GPIO_PORT, TAMPER_BUTTON_GPIO_PORT,
00086                                       KEY_BUTTON_GPIO_PORT};
00087
00088 const uint16_t BUTTON_PIN[BUTTONn] = {WAKEUP_BUTTON_PIN, TAMPER_BUTTON_PIN,
00089                                       KEY_BUTTON_PIN};
00090
00091 const uint32_t BUTTON_CLK[BUTTONn] = {WAKEUP_BUTTON_GPIO_CLK, TAMPER_BUTTON_GPIO_CLK,
00092                                       KEY_BUTTON_GPIO_CLK};
00093
00094 const uint16_t BUTTON_EXTI_LINE[BUTTONn] = {WAKEUP_BUTTON_EXTI_LINE,
00095                                             TAMPER_BUTTON_EXTI_LINE,
00096                                             KEY_BUTTON_EXTI_LINE};
00097
00098 const uint16_t BUTTON_PORT_SOURCE[BUTTONn] = {WAKEUP_BUTTON_EXTI_PORT_SOURCE,
00099                                               TAMPER_BUTTON_EXTI_PORT_SOURCE,
00100                                               KEY_BUTTON_EXTI_PORT_SOURCE};
00101
00102 const uint16_t BUTTON_PIN_SOURCE[BUTTONn] = {WAKEUP_BUTTON_EXTI_PIN_SOURCE,
00103                                              TAMPER_BUTTON_EXTI_PIN_SOURCE,
00104                                              KEY_BUTTON_EXTI_PIN_SOURCE};
00105
00106 const uint16_t BUTTON_IRQn[BUTTONn] = {WAKEUP_BUTTON_EXTI_IRQn, TAMPER_BUTTON_EXTI_IRQn,
00107                                        KEY_BUTTON_EXTI_IRQn};
00108
00109 USART_TypeDef* COM_USART[COMn] = {EVAL_COM1};
00110
00111 GPIO_TypeDef* COM_TX_PORT[COMn] = {EVAL_COM1_TX_GPIO_PORT};
00112
00113 GPIO_TypeDef* COM_RX_PORT[COMn] = {EVAL_COM1_RX_GPIO_PORT};
00114
00115 const uint32_t COM_USART_CLK[COMn] = {EVAL_COM1_CLK};
00116
00117 const uint32_t COM_TX_PORT_CLK[COMn] = {EVAL_COM1_TX_GPIO_CLK};
00118
00119 const uint32_t COM_RX_PORT_CLK[COMn] = {EVAL_COM1_RX_GPIO_CLK};
00120
00121 const uint16_t COM_TX_PIN[COMn] = {EVAL_COM1_TX_PIN};
00122
00123 const uint16_t COM_RX_PIN[COMn] = {EVAL_COM1_RX_PIN};
00124
00125 DMA_InitTypeDef   sEEDMA_InitStructure;
00126
00127 /**
00128   * @}
00129   */
00130
00131
00132 /** @defgroup STM3210C_EVAL_LOW_LEVEL_Private_FunctionPrototypes
00133   * @{
00134   */
00135 /**
00136   * @}
00137   */
00138
00139 /** @defgroup STM3210C_EVAL_LOW_LEVEL_Private_Functions
00140   * @{
00141   */
00142
00143 /**
00144   * @brief  Configures LED GPIO.
00145   * @param  Led: Specifies the Led to be configured.
00146   *   This parameter can be one of following parameters:
00147   *     @arg LED1
00148   *     @arg LED2
00149   *     @arg LED3
00150   *     @arg LED4
00151   * @retval None
00152   */
00153 void STM_EVAL_LEDInit(Led_TypeDef Led)
00154 {
00155   GPIO_InitTypeDef  GPIO_InitStructure;
00156
00157   /* Enable the GPIO_LED Clock */
00158   RCC_APB2PeriphClockCmd(GPIO_CLK[Led], ENABLE);
00159
00160   /* Configure the GPIO_LED pin */
00161   GPIO_InitStructure.GPIO_Pin = GPIO_PIN[Led];
00162   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
00163   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00164
00165   GPIO_Init(GPIO_PORT[Led], &GPIO_InitStructure);
00166 }
00167
00168 /**
00169   * @brief  Turns selected LED On.
00170   * @param  Led: Specifies the Led to be set on.
00171   *   This parameter can be one of following parameters:
00172   *     @arg LED1
00173   *     @arg LED2
00174   *     @arg LED3
00175   *     @arg LED4
00176   * @retval None
00177   */
00178 void STM_EVAL_LEDOn(Led_TypeDef Led)
00179 {
00180   GPIO_PORT[Led]->BSRR = GPIO_PIN[Led];
00181 }
00182
00183 /**
00184   * @brief  Turns selected LED Off.
00185   * @param  Led: Specifies the Led to be set off.
00186   *   This parameter can be one of following parameters:
00187   *     @arg LED1
00188   *     @arg LED2
00189   *     @arg LED3
00190   *     @arg LED4
00191   * @retval None
00192   */
00193 void STM_EVAL_LEDOff(Led_TypeDef Led)
00194 {
00195   GPIO_PORT[Led]->BRR = GPIO_PIN[Led];
00196 }
00197
00198 /**
00199   * @brief  Toggles the selected LED.
00200   * @param  Led: Specifies the Led to be toggled.
00201   *   This parameter can be one of following parameters:
00202   *     @arg LED1
00203   *     @arg LED2
00204   *     @arg LED3
00205   *     @arg LED4
00206   * @retval None
00207   */
00208 void STM_EVAL_LEDToggle(Led_TypeDef Led)
00209 {
00210   GPIO_PORT[Led]->ODR ^= GPIO_PIN[Led];
00211 }
00212
00213 /**
00214   * @brief  Configures Button GPIO and EXTI Line.
00215   * @param  Button: Specifies the Button to be configured.
00216   *   This parameter can be one of following parameters:
00217   *     @arg BUTTON_WAKEUP: Wakeup Push Button
00218   *     @arg BUTTON_TAMPER: Tamper Push Button
00219   *     @arg BUTTON_KEY: Key Push Button
00220   *     @arg BUTTON_RIGHT: Joystick Right Push Button
00221   *     @arg BUTTON_LEFT: Joystick Left Push Button
00222   *     @arg BUTTON_UP: Joystick Up Push Button
00223   *     @arg BUTTON_DOWN: Joystick Down Push Button
00224   *     @arg BUTTON_SEL: Joystick Sel Push Button
00225   * @param  Button_Mode: Specifies Button mode.
00226   *   This parameter can be one of following parameters:
00227   *     @arg BUTTON_MODE_GPIO: Button will be used as simple IO
00228   *     @arg BUTTON_MODE_EXTI: Button will be connected to EXTI line with interrupt
00229   *                     generation capability
00230   * @retval None
00231   */
00232 void STM_EVAL_PBInit(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode)
00233 {
00234   GPIO_InitTypeDef GPIO_InitStructure;
00235   EXTI_InitTypeDef EXTI_InitStructure;
00236   NVIC_InitTypeDef NVIC_InitStructure;
00237
00238   /* Enable the BUTTON Clock */
00239   RCC_APB2PeriphClockCmd(BUTTON_CLK[Button] | RCC_APB2Periph_AFIO, ENABLE);
00240
00241   /* Configure Button pin as input floating */
00242   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
00243   GPIO_InitStructure.GPIO_Pin = BUTTON_PIN[Button];
00244   GPIO_Init(BUTTON_PORT[Button], &GPIO_InitStructure);
00245
00246
00247   if (Button_Mode == BUTTON_MODE_EXTI)
00248   {
00249     /* Connect Button EXTI Line to Button GPIO Pin */
00250     GPIO_EXTILineConfig(BUTTON_PORT_SOURCE[Button], BUTTON_PIN_SOURCE[Button]);
00251
00252     /* Configure Button EXTI line */
00253     EXTI_InitStructure.EXTI_Line = BUTTON_EXTI_LINE[Button];
00254     EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
00255
00256     if(Button != BUTTON_WAKEUP)
00257     {
00258       EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling;
00259     }
00260     else
00261     {
00262       EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;
00263     }
00264     EXTI_InitStructure.EXTI_LineCmd = ENABLE;
00265     EXTI_Init(&EXTI_InitStructure);
00266
00267     /* Enable and set Button EXTI Interrupt to the lowest priority */
00268     NVIC_InitStructure.NVIC_IRQChannel = BUTTON_IRQn[Button];
00269     NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x0F;
00270     NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x0F;
00271     NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
00272
00273     NVIC_Init(&NVIC_InitStructure);
00274   }
00275 }
00276
00277 /**
00278   * @brief  Returns the selected Button state.
00279   * @param  Button: Specifies the Button to be checked.
00280   *   This parameter can be one of following parameters:
00281   *     @arg BUTTON_WAKEUP: Wakeup Push Button
00282   *     @arg BUTTON_TAMPER: Tamper Push Button
00283   *     @arg BUTTON_KEY: Key Push Button
00284   *     @arg BUTTON_RIGHT: Joystick Right Push Button
00285   *     @arg BUTTON_LEFT: Joystick Left Push Button
00286   *     @arg BUTTON_UP: Joystick Up Push Button
00287   *     @arg BUTTON_DOWN: Joystick Down Push Button
00288   *     @arg BUTTON_SEL: Joystick Sel Push Button
00289   * @retval The Button GPIO pin value.
00290   */
00291 uint32_t STM_EVAL_PBGetState(Button_TypeDef Button)
00292 {
00293   return GPIO_ReadInputDataBit(BUTTON_PORT[Button], BUTTON_PIN[Button]);
00294 }
00295
00296
00297 /**
00298   * @brief  Configures COM port.
00299   * @param  COM: Specifies the COM port to be configured.
00300   *   This parameter can be one of following parameters:
00301   *     @arg COM1
00302   *     @arg COM2
00303   * @param  USART_InitStruct: pointer to a USART_InitTypeDef structure that
00304   *   contains the configuration information for the specified USART peripheral.
00305   * @retval None
00306   */
00307 void STM_EVAL_COMInit(COM_TypeDef COM, USART_InitTypeDef* USART_InitStruct)
00308 {
00309   GPIO_InitTypeDef GPIO_InitStructure;
00310
00311   /* Enable GPIO clock */
00312   RCC_APB2PeriphClockCmd(COM_TX_PORT_CLK[COM] | COM_RX_PORT_CLK[COM] | RCC_APB2Periph_AFIO, ENABLE);
00313
00314   if (COM == COM1)
00315   {
00316     /* Enable the USART2 Pins Software Remapping */
00317     GPIO_PinRemapConfig(GPIO_Remap_USART2, ENABLE);
00318     RCC_APB1PeriphClockCmd(COM_USART_CLK[COM], ENABLE);
00319   }
00320
00321   /* Configure USART Tx as alternate function push-pull */
00322   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
00323   GPIO_InitStructure.GPIO_Pin = COM_TX_PIN[COM];
00324   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00325   GPIO_Init(COM_TX_PORT[COM], &GPIO_InitStructure);
00326
00327   /* Configure USART Rx as input floating */
00328   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
00329   GPIO_InitStructure.GPIO_Pin = COM_RX_PIN[COM];
00330   GPIO_Init(COM_RX_PORT[COM], &GPIO_InitStructure);
00331
00332   /* USART configuration */
00333   USART_Init(COM_USART[COM], USART_InitStruct);
00334
00335   /* Enable USART */
00336   USART_Cmd(COM_USART[COM], ENABLE);
00337 }
00338
00339 /**
00340   * @brief  DeInitializes the SD/SD communication.
00341   * @param  None
00342   * @retval None
00343   */
00344 void SD_LowLevel_DeInit(void)
00345 {
00346   GPIO_InitTypeDef  GPIO_InitStructure;
00347
00348   SPI_Cmd(SD_SPI, DISABLE); /*!< SD_SPI disable */
00349   SPI_I2S_DeInit(SD_SPI);   /*!< DeInitializes the SD_SPI */
00350
00351   /*!< SD_SPI Periph clock disable */
00352   RCC_APB1PeriphClockCmd(SD_SPI_CLK, DISABLE);
00353   /*!< DeRemap SPI3 Pins */
00354   GPIO_PinRemapConfig(GPIO_Remap_SPI3, DISABLE);
00355
00356   /*!< Configure SD_SPI pins: SCK */
00357   GPIO_InitStructure.GPIO_Pin = SD_SPI_SCK_PIN;
00358   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
00359   GPIO_Init(SD_SPI_SCK_GPIO_PORT, &GPIO_InitStructure);
00360
00361   /*!< Configure SD_SPI pins: MISO */
00362   GPIO_InitStructure.GPIO_Pin = SD_SPI_MISO_PIN;
00363   GPIO_Init(SD_SPI_MISO_GPIO_PORT, &GPIO_InitStructure);
00364
00365   /*!< Configure SD_SPI pins: MOSI */
00366   GPIO_InitStructure.GPIO_Pin = SD_SPI_MOSI_PIN;
00367   GPIO_Init(SD_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure);
00368
00369   /*!< Configure SD_SPI_CS_PIN pin: SD Card CS pin */
00370   GPIO_InitStructure.GPIO_Pin = SD_CS_PIN;
00371   GPIO_Init(SD_CS_GPIO_PORT, &GPIO_InitStructure);
00372
00373   /*!< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin */
00374   GPIO_InitStructure.GPIO_Pin = SD_DETECT_PIN;
00375   GPIO_Init(SD_DETECT_GPIO_PORT, &GPIO_InitStructure);
00376 }
00377
00378 /**
00379   * @brief  Initializes the SD_SPI and CS pins.
00380   * @param  None
00381   * @retval None
00382   */
00383 void SD_LowLevel_Init(void)
00384 {
00385   GPIO_InitTypeDef  GPIO_InitStructure;
00386   SPI_InitTypeDef   SPI_InitStructure;
00387
00388   /*!< SD_SPI_CS_GPIO, SD_SPI_MOSI_GPIO, SD_SPI_MISO_GPIO, SD_SPI_DETECT_GPIO
00389        and SD_SPI_SCK_GPIO Periph clock enable */
00390   RCC_APB2PeriphClockCmd(SD_CS_GPIO_CLK | SD_SPI_MOSI_GPIO_CLK | SD_SPI_MISO_GPIO_CLK |
00391                          SD_SPI_SCK_GPIO_CLK | SD_DETECT_GPIO_CLK, ENABLE);
00392
00393   /*!< SD_SPI Periph clock enable */
00394   RCC_APB1PeriphClockCmd(SD_SPI_CLK, ENABLE);
00395   /*!< AFIO Periph clock enable */
00396   RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE);
00397   /*!< Remap SPI3 Pins */
00398   GPIO_PinRemapConfig(GPIO_Remap_SPI3,ENABLE);
00399
00400   /*!< Configure SD_SPI pins: SCK */
00401   GPIO_InitStructure.GPIO_Pin = SD_SPI_SCK_PIN;
00402   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00403   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
00404   GPIO_Init(SD_SPI_SCK_GPIO_PORT, &GPIO_InitStructure);
00405
00406   /*!< Configure SD_SPI pins: MOSI */
00407   GPIO_InitStructure.GPIO_Pin = SD_SPI_MOSI_PIN;
00408   GPIO_Init(SD_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure);
00409
00410   /*!< Configure SD_SPI pins: MISO */
00411   GPIO_InitStructure.GPIO_Pin = SD_SPI_MISO_PIN;
00412   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
00413   GPIO_Init(SD_SPI_MISO_GPIO_PORT, &GPIO_InitStructure);
00414
00415   /*!< Configure SD_SPI_CS_PIN pin: SD Card CS pin */
00416   GPIO_InitStructure.GPIO_Pin = SD_CS_PIN;
00417   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
00418   GPIO_Init(SD_CS_GPIO_PORT, &GPIO_InitStructure);
00419
00420   /*!< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin */
00421   GPIO_InitStructure.GPIO_Pin = SD_DETECT_PIN;
00422   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
00423   GPIO_Init(SD_DETECT_GPIO_PORT, &GPIO_InitStructure);
00424
00425   /*!< SD_SPI Config */
00426   SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
00427   SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
00428   SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
00429   SPI_InitStructure.SPI_CPOL = SPI_CPOL_High;
00430   SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge;
00431   SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
00432   SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
00433   SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
00434   SPI_InitStructure.SPI_CRCPolynomial = 7;
00435   SPI_Init(SD_SPI, &SPI_InitStructure);
00436
00437   SPI_Cmd(SD_SPI, ENABLE); /*!< SD_SPI enable */
00438 }
00439
00440 /**
00441   * @brief  DeInitializes peripherals used by the I2C EEPROM driver.
00442   * @param  None
00443   * @retval None
00444   */
00445 void sEE_LowLevel_DeInit(void)
00446 {
00447   GPIO_InitTypeDef  GPIO_InitStructure;
00448   NVIC_InitTypeDef NVIC_InitStructure;
00449
00450   /* sEE_I2C Peripheral Disable */
00451   I2C_Cmd(sEE_I2C, DISABLE);
00452
00453   /* sEE_I2C DeInit */
00454   I2C_DeInit(sEE_I2C);
00455
00456   /*!< sEE_I2C Periph clock disable */
00457   RCC_APB1PeriphClockCmd(sEE_I2C_CLK, DISABLE);
00458
00459   /*!< GPIO configuration */
00460   /*!< Configure sEE_I2C pins: SCL */
00461   GPIO_InitStructure.GPIO_Pin = sEE_I2C_SCL_PIN;
00462   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
00463   GPIO_Init(sEE_I2C_SCL_GPIO_PORT, &GPIO_InitStructure);
00464
00465   /*!< Configure sEE_I2C pins: SDA */
00466   GPIO_InitStructure.GPIO_Pin = sEE_I2C_SDA_PIN;
00467   GPIO_Init(sEE_I2C_SDA_GPIO_PORT, &GPIO_InitStructure);
00468
00469   /* Configure and enable I2C DMA TX Channel interrupt */
00470   NVIC_InitStructure.NVIC_IRQChannel = sEE_I2C_DMA_TX_IRQn;
00471   NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = sEE_I2C_DMA_PREPRIO;
00472   NVIC_InitStructure.NVIC_IRQChannelSubPriority = sEE_I2C_DMA_SUBPRIO;
00473   NVIC_InitStructure.NVIC_IRQChannelCmd = DISABLE;
00474   NVIC_Init(&NVIC_InitStructure);
00475
00476   /* Configure and enable I2C DMA RX Channel interrupt */
00477   NVIC_InitStructure.NVIC_IRQChannel = sEE_I2C_DMA_RX_IRQn;
00478   NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = sEE_I2C_DMA_PREPRIO;
00479   NVIC_InitStructure.NVIC_IRQChannelSubPriority = sEE_I2C_DMA_SUBPRIO;
00480   NVIC_Init(&NVIC_InitStructure);
00481
00482   /* Disable and Deinitialize the DMA channels */
00483   DMA_Cmd(sEE_I2C_DMA_CHANNEL_TX, DISABLE);
00484   DMA_Cmd(sEE_I2C_DMA_CHANNEL_RX, DISABLE);
00485   DMA_DeInit(sEE_I2C_DMA_CHANNEL_TX);
00486   DMA_DeInit(sEE_I2C_DMA_CHANNEL_RX);
00487 }
00488
00489 /**
00490   * @brief  Initializes peripherals used by the I2C EEPROM driver.
00491   * @param  None
00492   * @retval None
00493   */
00494 void sEE_LowLevel_Init(void)
00495 {
00496   GPIO_InitTypeDef  GPIO_InitStructure;
00497   NVIC_InitTypeDef NVIC_InitStructure;
00498
00499   /*!< sEE_I2C_SCL_GPIO_CLK and sEE_I2C_SDA_GPIO_CLK Periph clock enable */
00500   RCC_APB2PeriphClockCmd(sEE_I2C_SCL_GPIO_CLK | sEE_I2C_SDA_GPIO_CLK, ENABLE);
00501
00502   /*!< sEE_I2C Periph clock enable */
00503   RCC_APB1PeriphClockCmd(sEE_I2C_CLK, ENABLE);
00504
00505   /*!< GPIO configuration */
00506   /*!< Configure sEE_I2C pins: SCL */
00507   GPIO_InitStructure.GPIO_Pin = sEE_I2C_SCL_PIN;
00508   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00509   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_OD;
00510   GPIO_Init(sEE_I2C_SCL_GPIO_PORT, &GPIO_InitStructure);
00511
00512   /*!< Configure sEE_I2C pins: SDA */
00513   GPIO_InitStructure.GPIO_Pin = sEE_I2C_SDA_PIN;
00514   GPIO_Init(sEE_I2C_SDA_GPIO_PORT, &GPIO_InitStructure);
00515
00516   /* Configure and enable I2C DMA TX Channel interrupt */
00517   NVIC_InitStructure.NVIC_IRQChannel = sEE_I2C_DMA_TX_IRQn;
00518   NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = sEE_I2C_DMA_PREPRIO;
00519   NVIC_InitStructure.NVIC_IRQChannelSubPriority = sEE_I2C_DMA_SUBPRIO;
00520   NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
00521   NVIC_Init(&NVIC_InitStructure);
00522
00523   /* Configure and enable I2C DMA RX Channel interrupt */
00524   NVIC_InitStructure.NVIC_IRQChannel = sEE_I2C_DMA_RX_IRQn;
00525   NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = sEE_I2C_DMA_PREPRIO;
00526   NVIC_InitStructure.NVIC_IRQChannelSubPriority = sEE_I2C_DMA_SUBPRIO;
00527   NVIC_Init(&NVIC_InitStructure);
00528
00529   /*!< I2C DMA TX and RX channels configuration */
00530   /* Enable the DMA clock */
00531   RCC_AHBPeriphClockCmd(sEE_I2C_DMA_CLK, ENABLE);
00532
00533   /* I2C TX DMA Channel configuration */
00534   DMA_DeInit(sEE_I2C_DMA_CHANNEL_TX);
00535   sEEDMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)sEE_I2C_DR_Address;
00536   sEEDMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)0;   /* This parameter will be configured durig communication */
00537   sEEDMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;    /* This parameter will be configured durig communication */
00538   sEEDMA_InitStructure.DMA_BufferSize = 0xFFFF;            /* This parameter will be configured durig communication */
00539   sEEDMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
00540   sEEDMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
00541   sEEDMA_InitStructure.DMA_PeripheralDataSize = DMA_MemoryDataSize_Byte;
00542   sEEDMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
00543   sEEDMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
00544   sEEDMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh;
00545   sEEDMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
00546   DMA_Init(sEE_I2C_DMA_CHANNEL_TX, &sEEDMA_InitStructure);
00547
00548   /* I2C RX DMA Channel configuration */
00549   DMA_DeInit(sEE_I2C_DMA_CHANNEL_RX);
00550   DMA_Init(sEE_I2C_DMA_CHANNEL_RX, &sEEDMA_InitStructure);
00551
00552   /* Enable the DMA Channels Interrupts */
00553   DMA_ITConfig(sEE_I2C_DMA_CHANNEL_TX, DMA_IT_TC, ENABLE);
00554   DMA_ITConfig(sEE_I2C_DMA_CHANNEL_RX, DMA_IT_TC, ENABLE);
00555 }
00556
00557
00558 /**
00559   * @brief  Initializes DMA channel used by the I2C EEPROM driver.
00560   * @param  None
00561   * @retval None
00562   */
00563 void sEE_LowLevel_DMAConfig(uint32_t pBuffer, uint32_t BufferSize, uint32_t Direction)
00564 {
00565   /* Initialize the DMA with the new parameters */
00566   if (Direction == sEE_DIRECTION_TX)
00567   {
00568     /* Configure the DMA Tx Channel with the buffer address and the buffer size */
00569     sEEDMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)pBuffer;
00570     sEEDMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
00571     sEEDMA_InitStructure.DMA_BufferSize = (uint32_t)BufferSize;
00572     DMA_Init(sEE_I2C_DMA_CHANNEL_TX, &sEEDMA_InitStructure);
00573   }
00574   else
00575   {
00576     /* Configure the DMA Rx Channel with the buffer address and the buffer size */
00577     sEEDMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)pBuffer;
00578     sEEDMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
00579     sEEDMA_InitStructure.DMA_BufferSize = (uint32_t)BufferSize;
00580     DMA_Init(sEE_I2C_DMA_CHANNEL_RX, &sEEDMA_InitStructure);
00581   }
00582 }
00583
00584 /**
00585   * @}
00586   */
00587
00588 /**
00589   * @}
00590   */
00591
00592 /**
00593   * @}
00594   */
00595
00596 /**
00597   * @}
00598   */
00599
00600 /**
00601   * @}
00602   */
00603
00604 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm3210c_eval.h Source File

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  • Utilities
  • STM32_EVAL
  • STM3210C_EVAL

stm3210c_eval.h

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00001 /**
00002   ******************************************************************************
00003   * @file    stm3210c_eval.h
00004   * @author  MCD Application Team
00005   * @version V4.5.0
00006   * @date    07-March-2011
00007   * @brief   This file contains definitions for STM3210C_EVAL's Leds, push-buttons
00008   *          COM ports, SD Card on SPI and sEE on I2C hardware resources.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00013   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00014   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00015   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00016   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00017   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00018   *
00019   * <h2><center>&copy; COPYRIGHT 210 STMicroelectronics</center></h2>
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM3210C_EVAL_H
00024 #define __STM3210C_EVAL_H
00025
00026 #ifdef __cplusplus
00027  extern "C" {
00028 #endif
00029
00030 /* Includes ------------------------------------------------------------------*/
00031 #include "stm32_eval.h"
00032
00033 /** @addtogroup Utilities
00034   * @{
00035   */
00036
00037 /** @addtogroup STM32_EVAL
00038   * @{
00039   */
00040
00041 /** @addtogroup STM3210C_EVAL
00042   * @{
00043   */
00044
00045 /** @addtogroup STM3210C_EVAL_LOW_LEVEL
00046   * @{
00047   */
00048
00049 /** @defgroup STM3210C_EVAL_LOW_LEVEL_Exported_Types
00050   * @{
00051   */
00052 /**
00053   * @}
00054   */
00055
00056 /** @defgroup STM3210C_EVAL_LOW_LEVEL_Exported_Constants
00057   * @{
00058   */
00059
00060 /** @addtogroup STM3210C_EVAL_LOW_LEVEL_LED
00061   * @{
00062   */
00063 #define LEDn                             4
00064
00065 #define LED1_PIN                         GPIO_Pin_7
00066 #define LED1_GPIO_PORT                   GPIOD
00067 #define LED1_GPIO_CLK                    RCC_APB2Periph_GPIOD
00068
00069 #define LED2_PIN                         GPIO_Pin_13
00070 #define LED2_GPIO_PORT                   GPIOD
00071 #define LED2_GPIO_CLK                    RCC_APB2Periph_GPIOD
00072
00073 #define LED3_PIN                         GPIO_Pin_3
00074 #define LED3_GPIO_PORT                   GPIOD
00075 #define LED3_GPIO_CLK                    RCC_APB2Periph_GPIOD
00076
00077 #define LED4_PIN                         GPIO_Pin_4
00078 #define LED4_GPIO_PORT                   GPIOD
00079 #define LED4_GPIO_CLK                    RCC_APB2Periph_GPIOD
00080
00081
00082 /**
00083   * @}
00084   */
00085
00086 /** @addtogroup STM3210C_EVAL_LOW_LEVEL_BUTTON
00087   * @{
00088   */
00089 #define BUTTONn                          3 /*!< Joystick pins are connected to
00090                                                 an IO Expander (accessible through
00091                                                 I2C1 interface) */
00092
00093 /**
00094  * @brief Wakeup push-button
00095  */
00096 #define WAKEUP_BUTTON_PIN                GPIO_Pin_0
00097 #define WAKEUP_BUTTON_GPIO_PORT          GPIOA
00098 #define WAKEUP_BUTTON_GPIO_CLK           RCC_APB2Periph_GPIOA
00099 #define WAKEUP_BUTTON_EXTI_LINE          EXTI_Line0
00100 #define WAKEUP_BUTTON_EXTI_PORT_SOURCE   GPIO_PortSourceGPIOA
00101 #define WAKEUP_BUTTON_EXTI_PIN_SOURCE    GPIO_PinSource0
00102 #define WAKEUP_BUTTON_EXTI_IRQn          EXTI0_IRQn
00103
00104 /**
00105  * @brief Tamper push-button
00106  */
00107 #define TAMPER_BUTTON_PIN                GPIO_Pin_13
00108 #define TAMPER_BUTTON_GPIO_PORT          GPIOC
00109 #define TAMPER_BUTTON_GPIO_CLK           RCC_APB2Periph_GPIOC
00110 #define TAMPER_BUTTON_EXTI_LINE          EXTI_Line13
00111 #define TAMPER_BUTTON_EXTI_PORT_SOURCE   GPIO_PortSourceGPIOC
00112 #define TAMPER_BUTTON_EXTI_PIN_SOURCE    GPIO_PinSource13
00113 #define TAMPER_BUTTON_EXTI_IRQn          EXTI15_10_IRQn
00114
00115 /**
00116  * @brief Key push-button
00117  */
00118 #define KEY_BUTTON_PIN                   GPIO_Pin_9
00119 #define KEY_BUTTON_GPIO_PORT             GPIOB
00120 #define KEY_BUTTON_GPIO_CLK              RCC_APB2Periph_GPIOB
00121 #define KEY_BUTTON_EXTI_LINE             EXTI_Line9
00122 #define KEY_BUTTON_EXTI_PORT_SOURCE      GPIO_PortSourceGPIOB
00123 #define KEY_BUTTON_EXTI_PIN_SOURCE       GPIO_PinSource9
00124 #define KEY_BUTTON_EXTI_IRQn             EXTI9_5_IRQn
00125 /**
00126   * @}
00127   */
00128
00129 /** @addtogroup STM3210C_EVAL_LOW_LEVEL_COM
00130   * @{
00131   */
00132 #define COMn                             1
00133
00134 /**
00135  * @brief Definition for COM port1, connected to USART2 (USART2 pins remapped on GPIOD)
00136  */
00137 #define EVAL_COM1                        USART2
00138 #define EVAL_COM1_CLK                    RCC_APB1Periph_USART2
00139 #define EVAL_COM1_TX_PIN                 GPIO_Pin_5
00140 #define EVAL_COM1_TX_GPIO_PORT           GPIOD
00141 #define EVAL_COM1_TX_GPIO_CLK            RCC_APB2Periph_GPIOD
00142 #define EVAL_COM1_RX_PIN                 GPIO_Pin_6
00143 #define EVAL_COM1_RX_GPIO_PORT           GPIOD
00144 #define EVAL_COM1_RX_GPIO_CLK            RCC_APB2Periph_GPIOD
00145 #define EVAL_COM1_IRQn                   USART2_IRQn
00146
00147 /**
00148   * @}
00149   */
00150
00151 /** @addtogroup STM3210B_EVAL_SD_SPI
00152   * @{
00153   */
00154 /**
00155   * @brief  SD SPI Interface pins
00156   */
00157 #define SD_SPI                           SPI3
00158 #define SD_SPI_CLK                       RCC_APB1Periph_SPI3
00159 #define SD_SPI_SCK_PIN                   GPIO_Pin_10                 /* PC.10 */
00160 #define SD_SPI_SCK_GPIO_PORT             GPIOC                       /* GPIOC */
00161 #define SD_SPI_SCK_GPIO_CLK              RCC_APB2Periph_GPIOC
00162 #define SD_SPI_MISO_PIN                  GPIO_Pin_11                 /* PC.11 */
00163 #define SD_SPI_MISO_GPIO_PORT            GPIOC                       /* GPIOC */
00164 #define SD_SPI_MISO_GPIO_CLK             RCC_APB2Periph_GPIOC
00165 #define SD_SPI_MOSI_PIN                  GPIO_Pin_12                 /* PC.12 */
00166 #define SD_SPI_MOSI_GPIO_PORT            GPIOC                       /* GPIOC */
00167 #define SD_SPI_MOSI_GPIO_CLK             RCC_APB2Periph_GPIOC
00168 #define SD_CS_PIN                        GPIO_Pin_4                  /* PA.04 */
00169 #define SD_CS_GPIO_PORT                  GPIOA                       /* GPIOA */
00170 #define SD_CS_GPIO_CLK                   RCC_APB2Periph_GPIOA
00171 #define SD_DETECT_PIN                    GPIO_Pin_0                  /* PE.00 */
00172 #define SD_DETECT_GPIO_PORT              GPIOE                       /* GPIOE */
00173 #define SD_DETECT_GPIO_CLK               RCC_APB2Periph_GPIOE
00174
00175 /**
00176   * @}
00177   */
00178
00179 /** @addtogroup STM3210C_EVAL_LOW_LEVEL_I2C_EE
00180   * @{
00181   */
00182 /**
00183   * @brief  I2C EEPROM Interface pins
00184   */
00185 #define sEE_I2C                          I2C1
00186 #define sEE_I2C_CLK                      RCC_APB1Periph_I2C1
00187 #define sEE_I2C_SCL_PIN                  GPIO_Pin_6                  /* PB.06 */
00188 #define sEE_I2C_SCL_GPIO_PORT            GPIOB                       /* GPIOB */
00189 #define sEE_I2C_SCL_GPIO_CLK             RCC_APB2Periph_GPIOB
00190 #define sEE_I2C_SDA_PIN                  GPIO_Pin_7                  /* PB.07 */
00191 #define sEE_I2C_SDA_GPIO_PORT            GPIOB                       /* GPIOB */
00192 #define sEE_I2C_SDA_GPIO_CLK             RCC_APB2Periph_GPIOB
00193 #define sEE_M24C64_32
00194
00195 #define sEE_I2C_DMA                      DMA1
00196 #define sEE_I2C_DMA_CHANNEL_TX           DMA1_Channel6
00197 #define sEE_I2C_DMA_CHANNEL_RX           DMA1_Channel7
00198 #define sEE_I2C_DMA_FLAG_TX_TC           DMA1_IT_TC6
00199 #define sEE_I2C_DMA_FLAG_TX_GL           DMA1_IT_GL6
00200 #define sEE_I2C_DMA_FLAG_RX_TC           DMA1_IT_TC7
00201 #define sEE_I2C_DMA_FLAG_RX_GL           DMA1_IT_GL7
00202 #define sEE_I2C_DMA_CLK                  RCC_AHBPeriph_DMA1
00203 #define sEE_I2C_DR_Address               ((uint32_t)0x40005410)
00204 #define sEE_USE_DMA
00205
00206 #define sEE_I2C_DMA_TX_IRQn              DMA1_Channel6_IRQn
00207 #define sEE_I2C_DMA_RX_IRQn              DMA1_Channel7_IRQn
00208 #define sEE_I2C_DMA_TX_IRQHandler        DMA1_Channel6_IRQHandler
00209 #define sEE_I2C_DMA_RX_IRQHandler        DMA1_Channel7_IRQHandler
00210 #define sEE_I2C_DMA_PREPRIO              0
00211 #define sEE_I2C_DMA_SUBPRIO              0
00212
00213 #define sEE_DIRECTION_TX                 0
00214 #define sEE_DIRECTION_RX                 1
00215
00216 /* Time constant for the delay caclulation allowing to have a millisecond
00217    incrementing counter. This value should be equal to (System Clock / 1000).
00218    ie. if system clock = 72MHz then sEE_TIME_CONST should be 72. */
00219 #define sEE_TIME_CONST                   72
00220
00221 /**
00222   * @}
00223   */
00224
00225 /**
00226   * @}
00227   */
00228
00229 /** @defgroup STM3210C_EVAL_LOW_LEVEL_Exported_Macros
00230   * @{
00231   */
00232 /**
00233   * @}
00234   */
00235
00236
00237 /** @defgroup STM3210C_EVAL_LOW_LEVEL_Exported_Functions
00238   * @{
00239   */
00240 void STM_EVAL_LEDInit(Led_TypeDef Led);
00241 void STM_EVAL_LEDOn(Led_TypeDef Led);
00242 void STM_EVAL_LEDOff(Led_TypeDef Led);
00243 void STM_EVAL_LEDToggle(Led_TypeDef Led);
00244 void STM_EVAL_PBInit(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode);
00245 uint32_t STM_EVAL_PBGetState(Button_TypeDef Button);
00246 void STM_EVAL_COMInit(COM_TypeDef COM, USART_InitTypeDef* USART_InitStruct);
00247 void SD_LowLevel_DeInit(void);
00248 void SD_LowLevel_Init(void);
00249 void sEE_LowLevel_DeInit(void);
00250 void sEE_LowLevel_Init(void);
00251 void sEE_LowLevel_DMAConfig(uint32_t pBuffer, uint32_t BufferSize, uint32_t Direction);
00252 /**
00253   * @}
00254   */
00255
00256 #ifdef __cplusplus
00257 }
00258 #endif
00259
00260 #endif /* __STM3210C_EVAL_H */
00261 /**
00262   * @}
00263   */
00264
00265 /**
00266   * @}
00267   */
00268
00269 /**
00270   * @}
00271   */
00272
00273 /**
00274   * @}
00275   */
00276
00277 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm3210c_eval_ioe.c Source File

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • STM3210C_EVAL

stm3210c_eval_ioe.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm3210c_eval_ioe.c
00004   * @author  MCD Application Team
00005   * @version V4.5.0
00006   * @date    07-March-2011
00007   * @brief   This file includes the IO Expander driver for STMPE811 IO Expander
00008   *          devices.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00013   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00014   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00015   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00016   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00017   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00018   *
00019   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00020   ******************************************************************************
00021   */
00022
00023   /* File Info : ---------------------------------------------------------------
00024
00025     Note:
00026     -----
00027     - This driver uses the DMA method for sending and receiving data on I2C bus
00028       which allow higher efficiency and reliability of the communication.
00029
00030     SUPPORTED FEATURES:
00031       - IO Read/write : Set/Reset and Read (Polling/Interrupt)
00032       - Joystick: config and Read (Polling/Interrupt)
00033       - Touch Screen Features: Single point mode (Polling/Interrupt)
00034       - TempSensor Feature: accuracy not determined (Polling).
00035
00036     UNSUPPORTED FEATURES:
00037       - Row ADC Feature is not supported (not implemented on STM3210C-EVAL board)
00038   ----------------------------------------------------------------------------*/
00039
00040 /* Includes ------------------------------------------------------------------*/
00041 #include "stm3210c_eval_ioe.h"
00042
00043 /** @addtogroup Utilities
00044   * @{
00045   */
00046
00047 /** @addtogroup STM32_EVAL
00048   * @{
00049   */
00050
00051 /** @addtogroup STM3210C_EVAL
00052   * @{
00053   */
00054
00055 /** @defgroup STM3210C_EVAL_IOE
00056   * @brief  This file includes the IO Expander driver for STMPE811 IO Expander
00057   *         devices.
00058   * @{
00059   */
00060
00061 /** @defgroup STM3210C_EVAL_IOE_Private_TypesDefinitions
00062   * @{
00063   */
00064 /**
00065   * @}
00066   */
00067
00068
00069 /** @defgroup STM3210C_EVAL_IOE_Private_Defines
00070   * @{
00071   */
00072 #define TIMEOUT_MAX             0x1000   /*<! The value of the maximal timeout for I2C waiting loops */
00073
00074 #define TS_CONVERSION_DELAY     0x10000  /*<! The application should wait before ADC end of conversion.
00075                                               This delay depends on the system clock frequency, the value 0x10000
00076                                               is selected for system clock equal to 72 MHz. For lower frequencies
00077                                               please modify the delay accordingly. */
00078 /**
00079   * @}
00080   */
00081
00082
00083 /** @defgroup STM3210C_EVAL_IOE_Private_Macros
00084   * @{
00085   */
00086 /**
00087   * @}
00088   */
00089
00090
00091 /** @defgroup STM3210C_EVAL_IOE_Private_Variables
00092   * @{
00093   */
00094 TS_STATE TS_State;              /*<! The global structure holding the TS state */
00095
00096 uint32_t IOE_TimeOut = TIMEOUT_MAX; /*<! Value of Timeout when I2C communication fails */
00097
00098 /**
00099   * @}
00100   */
00101
00102
00103 /** @defgroup STM3210C_EVAL_IOE_Private_FunctionPrototypes
00104   * @{
00105   */
00106 static uint16_t IOE_TS_Read_X(void);
00107 static uint16_t IOE_TS_Read_Y(void);
00108 static uint16_t IOE_TS_Read_Z(void);
00109
00110 static void IOE_GPIO_Config(void);
00111 static void IOE_I2C_Config(void);
00112 static void IOE_DMA_Config(IOE_DMADirection_TypeDef Direction, uint8_t* buffer);
00113 static void IOE_EXTI_Config(void);
00114
00115 #ifndef USE_Delay
00116 static void delay(__IO uint32_t nCount);
00117 #endif /* USE_Delay*/
00118 /**
00119   * @}
00120   */
00121
00122
00123 /** @defgroup STM3210C_EVAL_IOE_Private_Functions
00124   * @{
00125   */
00126
00127
00128 /**
00129   * @brief  Initializes and Configures the two IO_Expanders Functionalities
00130   *         (IOs, Touch Screen ..) and configures all STM3210C-EVAL necessary
00131   *         hardware (GPIOs, APB clocks ..).
00132   * @param  None
00133   * @retval IOE_OK if all initializations done correctly. Other value if error.
00134   */
00135 uint8_t IOE_Config(void)
00136 {
00137   /* Configure the needed pins */
00138   IOE_GPIO_Config();
00139
00140   /* Configure the I2C peripheral */
00141   IOE_I2C_Config();
00142
00143   /* Read IO Expander 1 ID  */
00144   if(IOE_IsOperational(IOE_1_ADDR))
00145   {
00146     return IOE1_NOT_OPERATIONAL;
00147   }
00148   if(IOE_IsOperational(IOE_2_ADDR))
00149   {
00150     return IOE2_NOT_OPERATIONAL;
00151   }
00152
00153   /* Generate IOExpander Software reset */
00154   IOE_Reset(IOE_1_ADDR);
00155   IOE_Reset(IOE_2_ADDR);
00156
00157   /* ---------------------- IO Expander 1 configuration --------------------- */
00158   /* Enable the GPIO, Touch Screen and ADC functionalities */
00159   IOE_FnctCmd(IOE_1_ADDR, IOE_IO_FCT | IOE_TS_FCT | IOE_ADC_FCT, ENABLE);
00160   /* Configure the VBAT pin in output mode pin*/
00161   IOE_IOPinConfig(IOE_1_ADDR, VBAT_DIV_PIN , Direction_OUT);
00162   /* ENABLE the alternate function for IN1 pin */
00163   IOE_IOAFConfig(IOE_1_ADDR, VBAT_DIV_PIN, ENABLE);
00164
00165   /* Apply the default state for the out pins */
00166   IOE_WriteIOPin(VBAT_DIV_PIN, BitReset);
00167   /* Configure the MEMS interrupt pins in Input mode */
00168   IOE_IOPinConfig(IOE_2_ADDR, (uint32_t)(MEMS_INT1_PIN | MEMS_INT2_PIN), Direction_IN);
00169
00170   /* ENABLE the alternate function for the Joystick pins */
00171   IOE_IOAFConfig(IOE_2_ADDR, (uint32_t)(MEMS_INT1_PIN | MEMS_INT2_PIN), ENABLE);
00172   /* Configure the IOs to detect Falling and Rising Edges */
00173   IOE_IOEdgeConfig(IOE_2_ADDR, (uint32_t)(MEMS_INT1_PIN | MEMS_INT2_PIN), (uint32_t)(EDGE_FALLING | EDGE_RISING));
00174   /* Touch Screen controller configuration */
00175   IOE_TS_Config();
00176
00177   /* ------------------------------------------------------------------------ */
00178
00179   /* ---------------------- IO Expander 2 configuration --------------------- */
00180   /* Enable the GPIO, Temperature Sensor and ADC functionalities */
00181   IOE_FnctCmd(IOE_2_ADDR, IOE_IO_FCT | IOE_TEMPSENS_FCT | IOE_ADC_FCT, ENABLE);
00182
00183   /* Configure the Audio Codec Reset pin in output mode pin*/
00184   IOE_IOPinConfig(IOE_2_ADDR, (uint32_t)(AUDIO_RESET_PIN), Direction_OUT);
00185   IOE_IOPinConfig(IOE_2_ADDR, (uint32_t)(MII_INT_PIN), Direction_IN);
00186
00187   /* ENABLE the alternate function for IN1 pin */
00188   IOE_IOAFConfig(IOE_2_ADDR, (uint32_t)(AUDIO_RESET_PIN | MII_INT_PIN), ENABLE);
00189
00190   /* Apply the default state for the out pins */
00191   IOE_WriteIOPin(AUDIO_RESET_PIN, BitReset);
00192   IOE_WriteIOPin(MII_INT_PIN, BitReset);
00193   /* Configure the Joystick pins in Input mode */
00194   IOE_IOPinConfig(IOE_2_ADDR, JOY_IO_PINS , Direction_IN);
00195
00196   /* ENABLE the alternate function for the Joystick pins */
00197   IOE_IOAFConfig(IOE_2_ADDR, JOY_IO_PINS, ENABLE);
00198   /* Configure the IOs to detect Falling and Rising Edges */
00199   IOE_IOEdgeConfig(IOE_2_ADDR, JOY_IO_PINS, (uint8_t)(EDGE_FALLING | EDGE_RISING));
00200
00201   /* Temperature Sensor module configuration */
00202   IOE_TempSens_Config();
00203   /* ------------------------------------------------------------------------ */
00204
00205   /* Configuration is OK */
00206   return IOE_OK;
00207 }
00208
00209 /**
00210   * @brief  Configures The selected interrupts on the IO Expanders.
00211   * @param  IOE_ITSRC_Source: the source of the interrupts. Could be one or a
00212   *         combination of the following parameters:
00213   *   @arg  IOE_ITSRC_JOYSTICK: Joystick IO intputs.
00214   *   @arg  IOE_ITSRC_TSC: Touch Screen interrupts.
00215   *   @arg  IOE_ITSRC_INMEMS: MEMS interrupt lines.
00216   * @retval IOE_OK: if all initializations are OK. Other value if error.
00217   */
00218 uint8_t IOE_ITConfig(uint32_t IOE_ITSRC_Source)
00219 {
00220   /* Configure the Interrupt output pin to generate low level (INT_CTRL) */
00221   IOE_ITOutConfig(Polarity_High, Type_Level);
00222
00223   /* Manage the Joystick Interrupts */
00224   if (IOE_ITSRC_Source & IOE_ITSRC_JOYSTICK)
00225   {
00226     /* Enable the Global interrupt */
00227     IOE_GITCmd(IOE_2_ADDR, ENABLE);
00228
00229     /* Enable the Joystick pins to generate interrupt (GPIO_INT_EN) */
00230     IOE_IOITConfig(IOE_2_ADDR, IOE_JOY_IT, ENABLE);
00231
00232     /* Enable the Global GPIO Interrupt */
00233     IOE_GITConfig(IOE_2_ADDR, IOE_GIT_GPIO, ENABLE);
00234
00235     /* Read the GPIO_IT_STA to clear all pending bits if any */
00236     I2C_ReadDeviceRegister(IOE_2_ADDR, IOE_REG_GPIO_INT_STA);
00237
00238     /* Enable the Joystick pins to generate interrupt */
00239     IOE_IOITConfig(IOE_2_ADDR, IOE_JOY_IT, ENABLE);
00240
00241     /* Read the GPIO_IT_STA to clear all pending bits if any */
00242     I2C_ReadDeviceRegister(IOE_2_ADDR, IOE_REG_GPIO_INT_STA);
00243   }
00244
00245   /* Manage the MEMS Interrupts lines  */
00246   if (IOE_ITSRC_Source & IOE_ITSRC_INMEMS)
00247   {
00248     /* Enable the Global interrupt */
00249     IOE_GITCmd(IOE_1_ADDR, ENABLE);
00250
00251     /* Enable the pins to generate interrupt (GPIO_INT_EN) */
00252     IOE_IOITConfig(IOE_1_ADDR, IOE_INMEMS_IT, ENABLE);
00253
00254     /* Enable the Global GPIO Interrupt */
00255     IOE_GITConfig(IOE_1_ADDR, IOE_GIT_GPIO, ENABLE);
00256
00257     /* Read the GPIO_IT_STA to clear all pending bits if any */
00258     I2C_ReadDeviceRegister(IOE_1_ADDR, IOE_REG_GPIO_INT_STA);
00259
00260     /* Enable the pins to generate interrupt */
00261     IOE_IOITConfig(IOE_1_ADDR, IOE_INMEMS_IT, ENABLE);
00262
00263     /* Read the GPIO_IT_STA to clear all pending bits if any */
00264     I2C_ReadDeviceRegister(IOE_1_ADDR, IOE_REG_GPIO_INT_STA);
00265   }
00266
00267   /* Manage the Touch Screen Interrupts */
00268   if (IOE_ITSRC_Source & IOE_ITSRC_TSC)
00269   {
00270     /* Enable the Global interrupt */
00271     IOE_GITCmd(IOE_1_ADDR, ENABLE);
00272
00273     /* Enable the Global GPIO Interrupt */
00274     IOE_GITConfig(IOE_1_ADDR, (uint8_t)(IOE_GIT_TOUCH | IOE_GIT_FTH | IOE_GIT_FOV), ENABLE);
00275
00276     /* Read the GPIO_IT_STA to clear all pending bits if any */
00277     I2C_ReadDeviceRegister(IOE_1_ADDR, IOE_REG_GPIO_INT_STA);
00278   }
00279
00280   /* Configure the Interrupt line as EXTI source */
00281   IOE_EXTI_Config();
00282
00283   /* If all OK return IOE_OK */
00284   return IOE_OK;
00285 }
00286
00287 /**
00288   * @brief  Writes a bit value to an output IO pin.
00289   * @param IO_Pin: The output pin to be set or reset. This parameter can be one
00290   *        of the following values:
00291   *   @arg  AUDIO_RESET_PIN: Audio codec reset pin
00292   *   @arg  MII_INT_PIN: Ethernet Phy MII interrupt pin
00293   *   @arg  VBAT_DIV_PIN: Battery devider pin
00294   * @param BitVal: The value to be set. This parameter can be one of the
00295   *        following values: BitSet or BitReset. See IOE_BitVal_TypeDef.
00296   * @retval IOE_OK or PARAM_ERROR
00297   */
00298 uint8_t IOE_WriteIOPin(uint8_t IO_Pin, IOE_BitValue_TypeDef BitVal)
00299 {
00300   uint8_t DeviceAddr = 0;
00301
00302   /* Get the IO expander Address according to which pin is to be controlled */
00303   if (IO_Pin & IO1_OUT_ALL_PINS)
00304   {
00305     DeviceAddr = IOE_1_ADDR;
00306   }
00307   else if (IO_Pin & IO2_OUT_ALL_PINS)
00308   {
00309     DeviceAddr = IOE_2_ADDR;
00310   }
00311   else
00312   {
00313     return PARAM_ERROR;
00314   }
00315
00316   /* Apply the bit value to the selected pin */
00317   if (BitVal == BitReset)
00318   {
00319     /* Set the register */
00320     I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_GPIO_CLR_PIN, IO_Pin);
00321   }
00322   else
00323   {
00324     /* Set the register */
00325     I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_GPIO_SET_PIN, IO_Pin);
00326   }
00327
00328   return IOE_OK;
00329 }
00330
00331
00332 /**
00333   * @brief  Returns the status of the selected input IO pin.
00334   * @param IO_Pin: The input pin to be read. This parameter can be one
00335   *  of the following values:
00336   *   @arg  MEMS_INT1_PIN: MEMS interrupt line 1.
00337   *   @arg  MEMS_INT2_PIN: MEMS interrupt line 2.
00338   *   @arg  JOY_IO_PINS: Joystick IO pins (use IOE_JoyStickGetState for these pins)
00339   * @retval None
00340   */
00341 uint8_t IOE_ReadIOPin(uint32_t IO_Pin)
00342 {
00343   uint8_t DeviceAddr = 0;
00344   uint8_t tmp = 0;
00345   if (IO_Pin & IO1_IN_ALL_PINS)
00346   {
00347     DeviceAddr = IOE_1_ADDR;
00348   }
00349   else if (IO_Pin & IO2_IN_ALL_PINS)
00350   {
00351     DeviceAddr = IOE_2_ADDR;
00352   }
00353   else
00354   {
00355     return PARAM_ERROR;
00356   }
00357
00358   /* Get all the Pins status */
00359   tmp = I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_GPIO_MP_STA);
00360   if ((tmp & (uint8_t)IO_Pin) != 0)
00361   {
00362     return BitSet;
00363   }
00364   else
00365   {
00366     return BitReset;
00367   }
00368 }
00369
00370
00371 /**
00372   * @brief  Returns the current Joystick status.
00373   * @param  None
00374   * @retval The code of the Joystick key pressed:
00375   *   @arg  JOY_NONE
00376   *   @arg  JOY_SEL
00377   *   @arg  JOY_DOWN
00378   *   @arg  JOY_LEFT
00379   *   @arg  JOY_RIGHT
00380   *   @arg  JOY_UP
00381   */
00382 JOYState_TypeDef
00383  IOE_JoyStickGetState(void)
00384 {
00385   uint8_t tmp = 0;
00386   /* Read the status of all pins */
00387   tmp = (uint32_t)I2C_ReadDeviceRegister(IOE_2_ADDR, IOE_REG_GPIO_MP_STA);
00388
00389   /* Check the pressed keys */
00390   if ((tmp & JOY_IO_NONE) == JOY_IO_NONE)
00391   {
00392     return (JOYState_TypeDef) JOY_NONE;
00393   }
00394   else if (!(tmp & JOY_IO_SEL))
00395   {
00396     return (JOYState_TypeDef) JOY_SEL;
00397   }
00398   else if (!(tmp & JOY_IO_DOWN))
00399   {
00400     return (JOYState_TypeDef) JOY_DOWN;
00401   }
00402   else if (!(tmp & JOY_IO_LEFT))
00403   {
00404     return (JOYState_TypeDef) JOY_LEFT;
00405   }
00406   else if (!(tmp & JOY_IO_RIGHT))
00407   {
00408     return (JOYState_TypeDef) JOY_RIGHT;
00409   }
00410   else if (!(tmp & JOY_IO_UP))
00411   {
00412     return (JOYState_TypeDef) JOY_UP;
00413   }
00414   else
00415   {
00416     return (JOYState_TypeDef) JOY_NONE;
00417   }
00418 }
00419
00420 /**
00421   * @brief  Returns Status and positions of the Touch screen.
00422   * @param  None
00423   * @retval Pointer to TS_STATE structure holding Touch Screen information.
00424   */
00425 TS_STATE* IOE_TS_GetState(void)
00426 {
00427   uint32_t xDiff, yDiff , x , y, count;
00428   static uint32_t _x = 0, _y = 0;
00429
00430   /* Check if the Touch detect event happenned */
00431   TS_State.TouchDetected = (I2C_ReadDeviceRegister(IOE_1_ADDR, IOE_REG_TSC_CTRL) & 0x80);
00432
00433   /* Wait till end of ADC conversion */
00434   for (count = TS_CONVERSION_DELAY; count > 0; count--);
00435
00436   if(TS_State.TouchDetected)
00437   {
00438     x = IOE_TS_Read_X();
00439     y = IOE_TS_Read_Y();
00440     xDiff = x > _x? (x - _x): (_x - x);
00441     yDiff = y > _y? (y - _y): (_y - y);
00442     if (xDiff + yDiff > 5)
00443     {
00444       _x = x;
00445       _y = y;
00446     }
00447   }
00448   /* Update the X position */
00449   TS_State.X = _x;
00450
00451   /* Update the Y position */
00452   TS_State.Y = _y;
00453
00454   /* Update the Z Pression index */
00455   TS_State.Z = IOE_TS_Read_Z();
00456
00457   /* Clear the interrupt pending bit and enable the FIFO again */
00458   I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_FIFO_STA, 0x01);
00459   I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_FIFO_STA, 0x00);
00460
00461   /* Return pointer to the updated structure */
00462   return &TS_State;
00463 }
00464
00465 /**
00466   * @brief  Returns the temperature row value (in 16 bit format).
00467   * @param  None
00468   * @retval The temperature row value.
00469   */
00470 uint32_t IOE_TempSens_GetData(void)
00471 {
00472   static __IO uint32_t tmp = 0;
00473
00474   /* Aquire data enable */
00475   I2C_WriteDeviceRegister(IOE_2_ADDR, IOE_REG_TEMP_CTRL, 0x03);
00476
00477   /* Enable the TEMPSENS module */
00478   tmp = (uint32_t)((I2C_ReadDeviceRegister(IOE_2_ADDR, IOE_REG_TEMP_DATA) & 0x03) << 8);
00479   tmp |= (uint32_t)I2C_ReadDeviceRegister(IOE_2_ADDR, IOE_REG_TEMP_DATA + 1);
00480
00481   tmp = (uint32_t)((33 * tmp * 100) / 751);
00482   tmp = (uint32_t)((tmp + 5) / 10);
00483
00484   /* return the temprature row value */
00485   return tmp;
00486 }
00487
00488 /**
00489   * @brief  Checks the selected Global interrupt source pending bit
00490   * @param  DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR
00491   *         or IOE_2_ADDR.
00492   * @param  Global_IT: the Global interrupt source to be checked, could be:
00493   *   @arg  Global_IT_GPIO : All IOs interrupt
00494   *   @arg  Global_IT_ADC : ADC interrupt
00495   *   @arg  Global_IT_TEMP : Temperature Sensor interrupts
00496   *   @arg  Global_IT_FE : Touch Screen Controller FIFO Error interrupt
00497   *   @arg  Global_IT_FF : Touch Screen Controller FIFO Full interrupt
00498   *   @arg  Global_IT_FOV : Touch Screen Controller FIFO Overrun interrupt
00499   *   @arg  Global_IT_FTH : Touch Screen Controller FIFO Threshold interrupt
00500   *   @arg  Global_IT_TOUCH : Touch Screen Controller Touch Detected interrupt
00501   * @retval Status of the checked flag. Could be SET or RESET.
00502   */
00503 FlagStatus IOE_GetGITStatus(uint8_t DeviceAddr, uint8_t Global_IT)
00504 {
00505   __IO uint8_t tmp = 0;
00506
00507   /* get the Interrupt status */
00508   tmp = I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_INT_STA);
00509
00510   if ((tmp & (uint8_t)Global_IT) != 0)
00511   {
00512     return SET;
00513   }
00514   else
00515   {
00516     return RESET;
00517   }
00518 }
00519
00520 /**
00521   * @brief  Clears the selected Global interrupt pending bit(s)
00522   * @param  DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR
00523   *         or IOE_2_ADDR.
00524   * @param  Global_IT: the Global interrupt to be cleared, could be any combination
00525   *         of the following values:
00526   *   @arg  Global_IT_GPIO : All IOs interrupt
00527   *   @arg  Global_IT_ADC : ADC interrupt
00528   *   @arg  Global_IT_TEMP : Temperature Sensor interrupts
00529   *   @arg  Global_IT_FE : Touch Screen Controller FIFO Error interrupt
00530   *   @arg  Global_IT_FF : Touch Screen Controller FIFO Full interrupt
00531   *   @arg  Global_IT_FOV : Touch Screen Controller FIFO Overrun interrupt
00532   *   @arg  Global_IT_FTH : Touch Screen Controller FIFO Threshold interrupt
00533   *   @arg  Global_IT_TOUCH : Touch Screen Controller Touch Detected interrupt
00534   * @retval IOE_OK: if all initializations are OK. Other value if error.
00535   */
00536 uint8_t IOE_ClearGITPending(uint8_t DeviceAddr, uint8_t Global_IT)
00537 {
00538   /* Write 1 to the bits that have to be cleared */
00539   I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_INT_STA, Global_IT);
00540
00541   /* If all OK return IOE_OK */
00542   return IOE_OK;
00543 }
00544
00545 /**
00546   * @brief  Checks the status of the selected IO interrupt pending bit
00547   * @param  DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR
00548   *         or IOE_2_ADDR.
00549   * @param  IO_IT: the IO interrupt to be checked could be IO_ITx Where x can be
00550   *         from 0 to 7.
00551   * @retval Status of the checked flag. Could be SET or RESET.
00552   */
00553 FlagStatus IOE_GetIOITStatus(uint8_t DeviceAddr, uint8_t IO_IT)
00554 {
00555   uint8_t tmp = 0;
00556
00557   /* get the Interrupt status */
00558   tmp = I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_GPIO_INT_STA);
00559
00560   if ((tmp & (uint8_t)IO_IT) != 0)
00561   {
00562     return SET;
00563   }
00564   else
00565   {
00566     return RESET;
00567   }
00568 }
00569
00570 /**
00571   * @brief  Clears the selected IO interrupt pending bit(s).
00572   * @param  DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR
00573   *         or IOE_2_ADDR.
00574   * @param  IO_IT: the IO interrupt to be checked could be IO_ITx Where x can be
00575   *         from 0 to 7.
00576   * @retval IOE_OK: if all initializations are OK. Other value if error.
00577   */
00578 uint8_t IOE_ClearIOITPending(uint8_t DeviceAddr, uint8_t IO_IT)
00579 {
00580   /* Write 1 to the bits that have to be cleared */
00581   I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_GPIO_INT_STA, IO_IT);
00582
00583   /* Clear the Edge detection pending bit*/
00584   I2C_WriteDeviceRegister(IOE_2_ADDR, IOE_REG_GPIO_ED, IO_IT);
00585
00586   /* Clear the Rising edge pending bit */
00587   I2C_WriteDeviceRegister(IOE_2_ADDR, IOE_REG_GPIO_RE, IO_IT);
00588
00589   /* Clear the Falling edge pending bit */
00590   I2C_WriteDeviceRegister(IOE_2_ADDR, IOE_REG_GPIO_FE, IO_IT);
00591
00592   /* If all OK return IOE_OK */
00593   return IOE_OK;
00594 }
00595
00596 /**
00597   * @brief  Checks if the selected device is correctly configured and
00598   *         communicates correctly ont the I2C bus.
00599   * @param  DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR
00600   *         or IOE_2_ADDR.
00601   * @retval IOE_OK if IOE is operational. Other value if failure.
00602   */
00603 uint8_t IOE_IsOperational(uint8_t DeviceAddr)
00604 {
00605   /* Return Error if the ID is not correct */
00606   if( IOE_ReadID(DeviceAddr) != (uint16_t)STMPE811_ID )
00607   {
00608     /* Check if a Timeout occured */
00609     if (IOE_TimeOut == 0)
00610     {
00611       return (IOE_TimeoutUserCallback());
00612     }
00613     else
00614     {
00615       return IOE_FAILURE; /* ID is not Correct */
00616     }
00617   }
00618   else
00619   {
00620     return IOE_OK; /* ID is correct */
00621   }
00622 }
00623
00624 /**
00625   * @brief  Resets the IO Expander by Software (SYS_CTRL1, RESET bit).
00626   * @param  DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR
00627   *         or IOE_2_ADDR.
00628   * @retval IOE_OK: if all initializations are OK. Other value if error.
00629   */
00630 uint8_t IOE_Reset(uint8_t DeviceAddr)
00631 {
00632   /* Power Down the IO_Expander */
00633   I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_SYS_CTRL1, 0x02);
00634
00635   /* wait for a delay to insure registers erasing */
00636   _delay_(2);
00637
00638   /* Power On the Codec after the power off => all registers are reinitialized*/
00639   I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_SYS_CTRL1, 0x00);
00640
00641   /* If all OK return IOE_OK */
00642   return IOE_OK;
00643 }
00644
00645 /**
00646   * @brief  Reads the selected device's ID.
00647   * @param  DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR
00648   *         or IOE_2_ADDR.
00649   * @retval The Device ID (two bytes).
00650   */
00651 uint16_t IOE_ReadID(uint8_t DeviceAddr)
00652 {
00653   uint16_t tmp = 0;
00654
00655   /* Read device ID  */
00656   tmp = I2C_ReadDeviceRegister(DeviceAddr, 0);
00657   tmp = (uint32_t)(tmp << 8);
00658   tmp |= (uint32_t)I2C_ReadDeviceRegister(DeviceAddr, 1);
00659
00660   /* Return the ID */
00661   return (uint16_t)tmp;
00662 }
00663
00664 /**
00665   * @brief  Configures the selcted IO Expander functionalities.
00666   * @param  DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR
00667   *         or IOE_2_ADDR.
00668   * @param  IOE_TEMPSENS_FCT: the functions to be configured. could be any
00669   *         combination of the following values:
00670   *   @arg  IOE_IO_FCT : IO function
00671   *   @arg  IOE_TS_FCT : Touch Screen function
00672   *   @arg  IOE_ADC_FCT : ADC function
00673   *   @arg  IOE_TEMPSENS_FCT : Tempreature Sensor function
00674   * @retval IOE_OK: if all initializations are OK. Other value if error.
00675   */
00676 uint8_t IOE_FnctCmd(uint8_t DeviceAddr, uint8_t Fct, FunctionalState NewState)
00677 {
00678   uint8_t tmp = 0;
00679
00680   /* Get the register value */
00681   tmp = I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_SYS_CTRL2);
00682
00683   if (NewState != DISABLE)
00684   {
00685     /* Set the Functionalities to be Enabled */
00686     tmp &= ~(uint8_t)Fct;
00687   }
00688   else
00689   {
00690     /* Set the Functionalities to be Disabled */
00691     tmp |= (uint8_t)Fct;
00692   }
00693
00694   /* Set the register value */
00695   I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_SYS_CTRL2, tmp);
00696
00697   /* If all OK return IOE_OK */
00698   return IOE_OK;
00699 }
00700
00701 /**
00702   * @brief  Configures the selected pin direction (to be an input or an output)
00703   * @param  DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR
00704   *         or IOE_2_ADDR.
00705   * @param  IO_Pin: IO_Pin_x: Where x can be from 0 to 7.
00706   * @param  Direction: could be Direction_IN or Direction_OUT.
00707   * @retval IOE_OK: if all initializations are OK. Other value if error.
00708   */
00709 uint8_t IOE_IOPinConfig(uint8_t DeviceAddr, uint8_t IO_Pin, uint8_t Direction)
00710 {
00711   uint8_t tmp = 0;
00712
00713   /* Get all the Pins direction */
00714   tmp = I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_GPIO_DIR);
00715
00716   if (Direction != Direction_IN)
00717   {
00718     tmp |= (uint8_t)IO_Pin;
00719   }
00720   else
00721   {
00722     tmp &= ~(uint8_t)IO_Pin;
00723   }
00724
00725   /* Write the register new value */
00726   I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_GPIO_DIR, tmp);
00727
00728   /* If all OK return IOE_OK */
00729   return IOE_OK;
00730 }
00731
00732 /**
00733   * @brief  Enables or disables the Global interrupt.
00734   * @param  DeviceAddr: The address of the IOExpander, could be :I OE_1_ADDR
00735   *         or IOE_2_ADDR.
00736   * @param  NewState: could be ENABLE or DISABLE.
00737   * @retval IOE_OK: if all initializations are OK. Other value if error.
00738   */
00739 uint8_t IOE_GITCmd(uint8_t DeviceAddr, FunctionalState NewState)
00740 {
00741   uint8_t tmp = 0;
00742
00743   /* Read the Interrupt Control register  */
00744   I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_INT_CTRL);
00745
00746   if (NewState != DISABLE)
00747   {
00748     /* Set the global interrupts to be Enabled */
00749     tmp |= (uint8_t)IOE_GIT_EN;
00750   }
00751   else
00752   {
00753     /* Set the global interrupts to be Disabled */
00754     tmp &= ~(uint8_t)IOE_GIT_EN;
00755   }
00756
00757   /* Write Back the Interrupt Control register */
00758   I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_INT_CTRL, tmp);
00759
00760   /* If all OK return IOE_OK */
00761   return IOE_OK;
00762 }
00763
00764 /**
00765   * @brief  Configures the selected source to generate or not a global interrupt
00766   * @param DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR
00767   *        or IOE_2_ADDR.
00768   * @param Global_IT: the interrupt source to be configured, could be:
00769   *   @arg  Global_IT_GPIO : All IOs interrupt
00770   *   @arg  Global_IT_ADC : ADC interrupt
00771   *   @arg  Global_IT_TEMP : Temperature Sensor interrupts
00772   *   @arg  Global_IT_FE : Touch Screen Controller FIFO Error interrupt
00773   *   @arg  Global_IT_FF : Touch Screen Controller FIFO Full interrupt
00774   *   @arg  Global_IT_FOV : Touch Screen Controller FIFO Overrun interrupt
00775   *   @arg  Global_IT_FTH : Touch Screen Controller FIFO Threshold interrupt
00776   *   @arg  Global_IT_TOUCH : Touch Screen Controller Touch Detected interrupt
00777   * @retval IOE_OK: if all initializations are OK. Other value if error.
00778   */
00779 uint8_t IOE_GITConfig(uint8_t DeviceAddr, uint8_t Global_IT, FunctionalState NewState)
00780 {
00781   uint8_t tmp = 0;
00782
00783   /* Get the current value of the INT_EN register */
00784   tmp = I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_INT_EN);
00785
00786   if (NewState != DISABLE)
00787   {
00788     /* Set the interrupts to be Enabled */
00789     tmp |= (uint8_t)Global_IT;
00790   }
00791   else
00792   {
00793     /* Set the interrupts to be Disabled */
00794     tmp &= ~(uint8_t)Global_IT;
00795   }
00796   /* Set the register */
00797   I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_INT_EN, tmp);
00798
00799   /* If all OK return IOE_OK */
00800   return IOE_OK;
00801 }
00802
00803 /**
00804   * @brief  Configures the selected pins to generate an interrupt or not.
00805   * @param  DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR
00806   *         or IOE_2_ADDR.
00807   * @param  IO_IT: The IO interrupt to be configured. This parameter could be any
00808   *         combination of the following values:
00809   *   @arg  IO_IT_x: where x can be from 0 to 7.
00810   * @param  NewState: could be ENABLE or DISABLE.
00811   * @retval IOE_OK: if all initializations are OK. Other value if error.
00812   */
00813 uint8_t IOE_IOITConfig(uint8_t DeviceAddr, uint8_t IO_IT, FunctionalState NewState)
00814 {
00815   uint8_t tmp = 0;
00816
00817   tmp = I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_GPIO_INT_EN);
00818
00819   if (NewState != DISABLE)
00820   {
00821     /* Set the interrupts to be Enabled */
00822     tmp |= (uint8_t)IO_IT;
00823   }
00824   else
00825   {
00826     /* Set the interrupts to be Disabled */
00827     tmp &= ~(uint8_t)IO_IT;
00828   }
00829
00830   /* Set the register */
00831   I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_GPIO_INT_EN, tmp);
00832
00833   /* If all OK return IOE_OK */
00834   return IOE_OK;
00835 }
00836
00837 /**
00838   * @brief  Configures the touch Screen Controller (Single point detection)
00839   * @param  None
00840   * @retval IOE_OK if all initializations are OK. Other value if error.
00841   */
00842 uint8_t IOE_TS_Config(void)
00843 {
00844   uint8_t tmp = 0;
00845
00846   /* Enable TSC Fct: already done in IOE_Config */
00847   tmp = I2C_ReadDeviceRegister(IOE_1_ADDR, IOE_REG_SYS_CTRL2);
00848   tmp &= ~(uint32_t)(IOE_TS_FCT | IOE_ADC_FCT);
00849   I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_SYS_CTRL2, tmp);
00850
00851   /* Enable the TSC gloabl interrupts */
00852   tmp = I2C_ReadDeviceRegister(IOE_1_ADDR, IOE_REG_INT_EN);
00853   tmp |= (uint32_t)(IOE_GIT_TOUCH | IOE_GIT_FTH | IOE_GIT_FOV);
00854   I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_INT_EN, tmp);
00855
00856   /* Select Sample Time, bit number and ADC Reference */
00857   I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_ADC_CTRL1, 0x49);
00858
00859   /* Wait for ~20 ms */
00860   _delay_(2);
00861
00862   /* Select the ADC clock speed: 3.25 MHz */
00863   I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_ADC_CTRL2, 0x01);
00864
00865   /* Select TSC pins in non default mode */
00866   tmp = I2C_ReadDeviceRegister(IOE_1_ADDR, IOE_REG_GPIO_AF);
00867   tmp &= ~(uint8_t)TOUCH_IO_ALL;
00868   I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_GPIO_AF, tmp);
00869
00870   /* Select 2 nF filter capacitor */
00871   I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_TSC_CFG, 0x9A);
00872
00873   /* Select single point reading  */
00874   I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_FIFO_TH, 0x01);
00875
00876   /* Write 0x01 to clear the FIFO memory content. */
00877   I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_FIFO_STA, 0x01);
00878
00879   /* Write 0x00 to put the FIFO back into operation mode  */
00880   I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_FIFO_STA, 0x00);
00881
00882   /* set the data format for Z value: 7 fractional part and 1 whole part */
00883   I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_TSC_FRACT_XYZ, 0x01);
00884
00885   /* set the driving capability of the device for TSC pins: 50mA */
00886   I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_TSC_I_DRIVE, 0x01);
00887
00888   /* Use no tracking index, touchscreen controller operation mode (XYZ) and
00889      enable the TSC */
00890   I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_TSC_CTRL, 0x01);
00891
00892   /*  Clear all the status pending bits */
00893   I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_INT_STA, 0xFF);
00894
00895   /* Initialize the TS structure to their default values */
00896   TS_State.TouchDetected = TS_State.X = TS_State.Y = TS_State.Z = 0;
00897
00898   /* All configuration done */
00899   return IOE_OK;
00900 }
00901
00902 /**
00903   * @brief  Configures and enables the Temperature sensor module.
00904   * @param  None
00905   * @retval IOE_OK if all initializations are OK. Other value if error.
00906   */
00907 uint8_t IOE_TempSens_Config(void)
00908 {
00909   __IO uint8_t tmp = 0;
00910
00911   /* Enable Temperature Sensor Fct: already done in IOE_Config */
00912   tmp = I2C_ReadDeviceRegister(IOE_2_ADDR, IOE_REG_SYS_CTRL2);
00913   tmp &= ~(uint32_t)(IOE_TEMPSENS_FCT | IOE_ADC_FCT);
00914   I2C_WriteDeviceRegister(IOE_2_ADDR, IOE_REG_SYS_CTRL2, tmp);
00915
00916   /* Enable the TEMPSENS module */
00917   I2C_WriteDeviceRegister(IOE_2_ADDR, IOE_REG_TEMP_CTRL, 0x01);
00918
00919   /* Aquire data enable */
00920   I2C_WriteDeviceRegister(IOE_2_ADDR, IOE_REG_TEMP_CTRL, 0x3);
00921
00922   /* All configuration done */
00923   return IOE_OK;
00924 }
00925
00926 /**
00927   * @brief  Configures the selected pin to be in Alternate function or not
00928   * @param  DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR
00929   *         or IOE_2_ADDR.
00930   * @param  IO_Pin: IO_Pin_x, Where x can be from 0 to 7.
00931   * @param  NewState: State of the AF for the selected pin, could be
00932   *         ENABLE or DISABLE.
00933   * @retval IOE_OK: if all initializations are OK. Other value if error.
00934   */
00935 uint8_t IOE_IOAFConfig(uint8_t DeviceAddr, uint8_t IO_Pin, FunctionalState NewState)
00936 {
00937   uint8_t tmp = 0;
00938
00939   /* Get the current state of the GPIO_AF register */
00940   tmp = I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_GPIO_AF);
00941
00942   if (NewState != DISABLE)
00943   {
00944     /* Enable the selected pins alternate function */
00945     tmp |= (uint8_t)IO_Pin;
00946   }
00947   else
00948   {
00949     /* Disable the selected pins alternate function */
00950     tmp &= ~(uint8_t)IO_Pin;
00951   }
00952
00953   /* Write back the new valu in GPIO_AF register */
00954   I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_GPIO_AF, tmp);
00955
00956   /* If all OK return IOE_OK */
00957   return IOE_OK;
00958 }
00959
00960 /**
00961   * @brief  Configures the Edge for which a transition is detectable for the
00962   *         the selected pin.
00963   * @param  DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR
00964   *         or IOE_2_ADDR.
00965   * @param  IO_Pin: IO_Pin_x, Where x can be from 0 to 7.
00966   * @param  Edge: The edge which will be detected. This parameter can be one or a
00967   *         a combination of follwing values: EDGE_FALLING and EDGE_RISING .
00968   * @retval IOE_OK: if all initializations are OK. Other value if error.
00969   */
00970 uint8_t IOE_IOEdgeConfig(uint8_t DeviceAddr, uint8_t IO_Pin, uint8_t Edge)
00971 {
00972   uint8_t tmp1 = 0, tmp2 = 0;
00973
00974   /* Get the registers values */
00975   tmp1 = I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_GPIO_FE);
00976   tmp2 = I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_GPIO_RE);
00977
00978   /* Disable the Falling Edge */
00979   tmp1 &= ~(uint8_t)IO_Pin;
00980   /* Disable the Falling Edge */
00981   tmp2 &= ~(uint8_t)IO_Pin;
00982
00983   /* Enable the Falling edge if selected */
00984   if (Edge & EDGE_FALLING)
00985   {
00986     tmp1 |= (uint8_t)IO_Pin;
00987   }
00988
00989   /* Enable the Rising edge if selected */
00990   if (Edge & EDGE_RISING)
00991   {
00992     tmp2 |= (uint8_t)IO_Pin;
00993   }
00994
00995   /* Write back the registers values */
00996   I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_GPIO_FE, tmp1);
00997   I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_GPIO_RE, tmp2);
00998
00999   /* if OK return 0 */
01000   return IOE_OK;
01001 }
01002
01003 /**
01004   * @brief  Configures the Interrupt line active state and format (level/edge)
01005   * @param  Polarity: could be
01006   *   @arg  Polarity_Low: Interrupt line is active Low/Falling edge
01007   *   @arg  Polarity_High: Interrupt line is active High/Rising edge
01008   * @param  Type: Interrupt line activity type, could be one of the following values
01009   *   @arg  Type_Level: Interrupt line is active in level model
01010   *   @arg  Type_Edge: Interrupt line is active in edge model
01011   * @retval IOE_OK: if all initializations are OK. Other value if error.
01012   */
01013 uint8_t IOE_ITOutConfig(uint8_t Polarity, uint8_t Type)
01014 {
01015   uint8_t tmp = 0;
01016
01017   /*  Get the register IOE_REG_INT_CTRL value */
01018   tmp = I2C_ReadDeviceRegister(IOE_1_ADDR, IOE_REG_INT_CTRL);
01019
01020   /* Mask the polarity and type bits */
01021   tmp &= ~(uint8_t)0x06;
01022
01023   /* Modify the Interrupt Output line configuration */
01024   tmp |= (uint8_t)(Polarity | Type);
01025
01026   /* Set the register */
01027   I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_INT_CTRL, tmp);
01028
01029
01030   /*  Get the register IOE_REG_INT_CTRL value */
01031   tmp = I2C_ReadDeviceRegister(IOE_2_ADDR, IOE_REG_INT_CTRL);
01032   /* Mask the polarity and type bits */
01033   tmp &= ~(uint8_t)0x06;
01034
01035   /* Modify the Interrupt Output line configuration */
01036   tmp |= (uint8_t)(Polarity | Type);
01037
01038   /* Set the register */
01039   I2C_WriteDeviceRegister(IOE_2_ADDR, IOE_REG_INT_CTRL, tmp);
01040
01041   /* If all OK return IOE_OK */
01042   return IOE_OK;
01043 }
01044
01045 /**
01046   * @brief  Writes a value in a register of the device through I2C.
01047   * @param  DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR
01048   *         or IOE_2_ADDR.
01049   * @param  RegisterAddr: The target register adress
01050   * @param  RegisterValue: The target register value to be written
01051   * @retval IOE_OK: if all operations are OK. Other value if error.
01052   */
01053 uint8_t I2C_WriteDeviceRegister(uint8_t DeviceAddr, uint8_t RegisterAddr, uint8_t RegisterValue)
01054 {
01055   uint32_t read_verif = 0;
01056   uint8_t IOE_BufferTX = 0;
01057
01058   /* Get Value to be written */
01059   IOE_BufferTX = RegisterValue;
01060
01061   /* Configure DMA Peripheral */
01062   IOE_DMA_Config(IOE_DMA_TX, (uint8_t*)(&IOE_BufferTX));
01063
01064   /* Enable the I2C peripheral */
01065   I2C_GenerateSTART(IOE_I2C, ENABLE);
01066
01067   /* Test on SB Flag */
01068   IOE_TimeOut = TIMEOUT_MAX;
01069   while (I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_SB) == RESET)
01070   {
01071     if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback());
01072   }
01073
01074   /* Transmit the slave address and enable writing operation */
01075   I2C_Send7bitAddress(IOE_I2C, DeviceAddr, I2C_Direction_Transmitter);
01076
01077   /* Test on ADDR Flag */
01078   IOE_TimeOut = TIMEOUT_MAX;
01079   while (!I2C_CheckEvent(IOE_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED))
01080   {
01081     if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback());
01082   }
01083
01084   /* Transmit the first address for r/w operations */
01085   I2C_SendData(IOE_I2C, RegisterAddr);
01086
01087   /* Test on TXE FLag (data dent) */
01088   IOE_TimeOut = TIMEOUT_MAX;
01089   while ((!I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_TXE)) && (!I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_BTF)))
01090   {
01091     if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback());
01092   }
01093
01094   /* Enable I2C DMA request */
01095   I2C_DMACmd(IOE_I2C,ENABLE);
01096
01097   /* Enable DMA TX Channel */
01098   DMA_Cmd(IOE_DMA_TX_CHANNEL, ENABLE);
01099
01100   /* Wait until DMA Transfer Complete */
01101   IOE_TimeOut = TIMEOUT_MAX;
01102   while (!DMA_GetFlagStatus(IOE_DMA_TX_TCFLAG))
01103   {
01104     if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback());
01105   }
01106
01107   /* Wait until BTF Flag is set before generating STOP */
01108   IOE_TimeOut = 2 * TIMEOUT_MAX;
01109   while ((!I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_BTF)))
01110   {
01111   }
01112
01113   /* Send STOP Condition */
01114   I2C_GenerateSTOP(IOE_I2C, ENABLE);
01115
01116   /* Disable DMA TX Channel */
01117   DMA_Cmd(IOE_DMA_TX_CHANNEL, DISABLE);
01118
01119   /* Disable I2C DMA request */
01120   I2C_DMACmd(IOE_I2C,DISABLE);
01121
01122   /* Clear DMA TX Transfer Complete Flag */
01123   DMA_ClearFlag(IOE_DMA_TX_TCFLAG);
01124
01125 #ifdef VERIFY_WRITTENDATA
01126   /* Verify (if needed) that the loaded data is correct  */
01127
01128   /* Read the just written register*/
01129   read_verif = I2C_ReadDeviceRegister(DeviceAddr, RegisterAddr);
01130   /* Load the register and verify its value  */
01131   if (read_verif != RegisterValue)
01132   {
01133     /* Control data wrongly tranfered */
01134     read_verif = IOE_FAILURE;
01135   }
01136   else
01137   {
01138     /* Control data correctly transfered */
01139     read_verif = 0;
01140   }
01141 #endif
01142
01143   /* Return the verifying value: 0 (Passed) or 1 (Failed) */
01144   return read_verif;
01145 }
01146
01147 /**
01148   * @brief  Reads a register of the device through I2C.
01149   * @param  DeviceAddr: The address of the device, could be : IOE_1_ADDR
01150   *         or IOE_2_ADDR.
01151   * @param  RegisterAddr: The target register adress (between 00x and 0x24)
01152   * @retval The value of the read register (0xAA if Timout occured)
01153   */
01154 uint8_t I2C_ReadDeviceRegister(uint8_t DeviceAddr, uint8_t RegisterAddr)
01155 {
01156   uint8_t IOE_BufferRX[2] = {0x00, 0x00};
01157
01158   /* Configure DMA Peripheral */
01159   IOE_DMA_Config(IOE_DMA_RX, (uint8_t*)IOE_BufferRX);
01160
01161   /* Enable DMA NACK automatic generation */
01162   I2C_DMALastTransferCmd(IOE_I2C, ENABLE);
01163
01164   /* Enable the I2C peripheral */
01165   I2C_GenerateSTART(IOE_I2C, ENABLE);
01166
01167   /* Test on SB Flag */
01168   IOE_TimeOut = TIMEOUT_MAX;
01169   while (!I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_SB))
01170   {
01171     if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback());
01172   }
01173
01174   /* Send device address for write */
01175   I2C_Send7bitAddress(IOE_I2C, DeviceAddr, I2C_Direction_Transmitter);
01176
01177   /* Test on ADDR Flag */
01178   IOE_TimeOut = TIMEOUT_MAX;
01179   while (!I2C_CheckEvent(IOE_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED))
01180   {
01181     if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback());
01182   }
01183
01184   /* Send the device's internal address to write to */
01185   I2C_SendData(IOE_I2C, RegisterAddr);
01186
01187   /* Test on TXE FLag (data dent) */
01188   IOE_TimeOut = TIMEOUT_MAX;
01189   while ((!I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_TXE)) && (!I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_BTF)))
01190   {
01191     if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback());
01192   }
01193
01194   /* Send START condition a second time */
01195   I2C_GenerateSTART(IOE_I2C, ENABLE);
01196
01197   /* Test on SB Flag */
01198   IOE_TimeOut = TIMEOUT_MAX;
01199   while (!I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_SB))
01200   {
01201     if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback());
01202   }
01203
01204   /* Send IOExpander address for read */
01205   I2C_Send7bitAddress(IOE_I2C, DeviceAddr, I2C_Direction_Receiver);
01206
01207   /* Test on ADDR Flag */
01208   IOE_TimeOut = TIMEOUT_MAX;
01209   while (!I2C_CheckEvent(IOE_I2C, I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED))
01210   {
01211     if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback());
01212   }
01213
01214   /* Enable I2C DMA request */
01215   I2C_DMACmd(IOE_I2C,ENABLE);
01216
01217   /* Enable DMA RX Channel */
01218   DMA_Cmd(IOE_DMA_RX_CHANNEL, ENABLE);
01219
01220   /* Wait until DMA Transfer Complete */
01221   IOE_TimeOut = 2 * TIMEOUT_MAX;
01222   while (!DMA_GetFlagStatus(IOE_DMA_RX_TCFLAG))
01223   {
01224     if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback());
01225   }
01226
01227   /* Send STOP Condition */
01228   I2C_GenerateSTOP(IOE_I2C, ENABLE);
01229
01230   /* Disable DMA RX Channel */
01231   DMA_Cmd(IOE_DMA_RX_CHANNEL, DISABLE);
01232
01233   /* Disable I2C DMA request */
01234   I2C_DMACmd(IOE_I2C,DISABLE);
01235
01236   /* Clear DMA RX Transfer Complete Flag */
01237   DMA_ClearFlag(IOE_DMA_RX_TCFLAG);
01238
01239   /* return a pointer to the IOE_Buffer */
01240   return (uint8_t)IOE_BufferRX[0];
01241 }
01242
01243
01244 /**
01245   * @brief  Reads a buffer of 2 bytes from the device registers.
01246   * @param  DeviceAddr: The address of the device, could be : IOE_1_ADDR
01247   *         or IOE_2_ADDR.
01248   * @param  RegisterAddr: The target register adress (between 00x and 0x24)
01249   * @retval A pointer to the buffer containing the two returned bytes (in halfword).
01250   */
01251 uint16_t I2C_ReadDataBuffer(uint8_t DeviceAddr, uint32_t RegisterAddr)
01252 {
01253   uint8_t tmp= 0;
01254   uint8_t IOE_BufferRX[2] = {0x00, 0x00};
01255
01256   /* Configure DMA Peripheral */
01257   IOE_DMA_Config(IOE_DMA_RX, (uint8_t*)IOE_BufferRX);
01258
01259   /* Enable DMA NACK automatic generation */
01260   I2C_DMALastTransferCmd(IOE_I2C, ENABLE);
01261
01262   /* Enable the I2C peripheral */
01263   I2C_GenerateSTART(IOE_I2C, ENABLE);
01264
01265   /* Test on SB Flag */
01266   IOE_TimeOut = TIMEOUT_MAX;
01267   while (!I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_SB))
01268   {
01269     if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback());
01270   }
01271
01272   /* Send device address for write */
01273   I2C_Send7bitAddress(IOE_I2C, DeviceAddr, I2C_Direction_Transmitter);
01274
01275   /* Test on ADDR Flag */
01276   IOE_TimeOut = TIMEOUT_MAX;
01277   while (!I2C_CheckEvent(IOE_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED))
01278   {
01279     if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback());
01280   }
01281
01282   /* Send the device's internal address to write to */
01283   I2C_SendData(IOE_I2C, RegisterAddr);
01284
01285   /* Test on TXE FLag (data dent) */
01286   IOE_TimeOut = TIMEOUT_MAX;
01287   while ((!I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_TXE)) && (!I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_BTF)))
01288   {
01289     if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback());
01290   }
01291
01292   /* Send START condition a second time */
01293   I2C_GenerateSTART(IOE_I2C, ENABLE);
01294
01295   /* Test on SB Flag */
01296   IOE_TimeOut = TIMEOUT_MAX;
01297   while (!I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_SB))
01298   {
01299     if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback());
01300   }
01301
01302   /* Send IOExpander address for read */
01303   I2C_Send7bitAddress(IOE_I2C, DeviceAddr, I2C_Direction_Receiver);
01304
01305   /* Test on ADDR Flag */
01306   IOE_TimeOut = TIMEOUT_MAX;
01307   while (!I2C_CheckEvent(IOE_I2C, I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED))
01308   {
01309     if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback());
01310   }
01311
01312   /* Enable I2C DMA request */
01313   I2C_DMACmd(IOE_I2C,ENABLE);
01314
01315   /* Enable DMA RX Channel */
01316   DMA_Cmd(IOE_DMA_RX_CHANNEL, ENABLE);
01317
01318   /* Wait until DMA Transfer Complete */
01319   IOE_TimeOut = 2 * TIMEOUT_MAX;
01320   while (!DMA_GetFlagStatus(IOE_DMA_RX_TCFLAG))
01321   {
01322     if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback());
01323   }
01324
01325   /* Send STOP Condition */
01326   I2C_GenerateSTOP(IOE_I2C, ENABLE);
01327
01328   /* Disable DMA RX Channel */
01329   DMA_Cmd(IOE_DMA_RX_CHANNEL, DISABLE);
01330
01331   /* Disable I2C DMA request */
01332   I2C_DMACmd(IOE_I2C,DISABLE);
01333
01334   /* Clear DMA RX Transfer Complete Flag */
01335   DMA_ClearFlag(IOE_DMA_RX_TCFLAG);
01336
01337   /* Reorganize received data */
01338   tmp = IOE_BufferRX[0];
01339   IOE_BufferRX[0] = IOE_BufferRX[1];
01340   IOE_BufferRX[1] = tmp;
01341
01342   /* return a pointer to the IOE_Buffer */
01343   return *(uint16_t *)IOE_BufferRX;
01344 }
01345
01346 /**
01347   * @brief  Return Touch Screen X position value
01348   * @param  None
01349   * @retval X position.
01350   */
01351 static uint16_t IOE_TS_Read_X(void)
01352 {
01353   int32_t x, xr;
01354
01355   x = I2C_ReadDataBuffer(IOE_1_ADDR, IOE_REG_TSC_DATA_Y);
01356
01357   /* first correction */
01358   xr =  (x * 320) >> 12;
01359   /* second correction */
01360   xr = ((xr * 32)/29) - 17;
01361
01362   if(xr <= 0)
01363     xr = 0;
01364
01365   return (uint16_t)(xr);
01366 }
01367
01368 /**
01369   * @brief  Return Touch Screen Y position value
01370   * @param  None
01371   * @retval Y position.
01372   */
01373 static uint16_t IOE_TS_Read_Y(void)
01374 {
01375   int32_t y, yr;
01376   y= I2C_ReadDataBuffer(IOE_1_ADDR, IOE_REG_TSC_DATA_X);
01377
01378   yr= (y * 240) >> 12;
01379   yr = ((yr * 240) / 217) - 12;
01380
01381   if(yr <= 0)
01382     yr = 0;
01383
01384   return (uint16_t)(yr);
01385 }
01386
01387 /**
01388   * @brief  Return Touch Screen Z position value
01389   * @param  None
01390   * @retval Z position.
01391   */
01392 static uint16_t IOE_TS_Read_Z(void)
01393 {
01394   uint32_t z;
01395   z = I2C_ReadDataBuffer(IOE_1_ADDR, IOE_REG_TSC_DATA_Z);
01396
01397
01398   if(z <= 0)
01399     z = 0;
01400
01401   return (uint16_t)(z);
01402 }
01403
01404 /**
01405   * @brief  Initializes the GPIO pins used by the IO expander.
01406   * @param  None
01407   * @retval None
01408   */
01409 static void IOE_GPIO_Config(void)
01410 {
01411   GPIO_InitTypeDef GPIO_InitStructure;
01412
01413   /* Enable IOE_I2C and IOE_I2C_PORT & Alternate Function clocks */
01414   RCC_APB1PeriphClockCmd(IOE_I2C_CLK, ENABLE);
01415   RCC_APB2PeriphClockCmd(IOE_I2C_SCL_GPIO_CLK | IOE_I2C_SDA_GPIO_CLK | IOE_IT_GPIO_CLK
01416                          | RCC_APB2Periph_AFIO, ENABLE);
01417
01418   /* Reset IOE_I2C IP */
01419   RCC_APB1PeriphResetCmd(IOE_I2C_CLK, ENABLE);
01420
01421   /* Release reset signal of IOE_I2C IP */
01422   RCC_APB1PeriphResetCmd(IOE_I2C_CLK, DISABLE);
01423
01424   /* IOE_I2C SCL and SDA pins configuration */
01425   GPIO_InitStructure.GPIO_Pin = IOE_I2C_SCL_PIN;
01426   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_10MHz;
01427   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_OD;
01428   GPIO_Init(IOE_I2C_SCL_GPIO_PORT, &GPIO_InitStructure);
01429
01430   /* IOE_I2C SCL and SDA pins configuration */
01431   GPIO_InitStructure.GPIO_Pin = IOE_I2C_SDA_PIN;
01432   GPIO_Init(IOE_I2C_SDA_GPIO_PORT, &GPIO_InitStructure);
01433
01434   /* Set EXTI pin as Input PullUp - IO_Expander_INT */
01435   GPIO_InitStructure.GPIO_Pin = IOE_IT_PIN;
01436   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
01437   GPIO_Init(IOE_IT_GPIO_PORT, &GPIO_InitStructure);
01438
01439   /* Connect IO Expander IT line to EXTI line */
01440   GPIO_EXTILineConfig(IOE_IT_EXTI_PORT_SOURCE, IOE_IT_EXTI_PIN_SOURCE);
01441 }
01442
01443
01444 /**
01445   * @brief  Configure the I2C Peripheral used to communicate with IO_Expanders.
01446   * @param  None
01447   * @retval None
01448   */
01449 static void IOE_I2C_Config(void)
01450 {
01451   I2C_InitTypeDef I2C_InitStructure;
01452
01453   /* IOE_I2C configuration */
01454   I2C_InitStructure.I2C_Mode = I2C_Mode_I2C;
01455   I2C_InitStructure.I2C_DutyCycle = I2C_DutyCycle_2;
01456   I2C_InitStructure.I2C_OwnAddress1 = 0x00;
01457   I2C_InitStructure.I2C_Ack = I2C_Ack_Enable;
01458   I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
01459   I2C_InitStructure.I2C_ClockSpeed = IOE_I2C_SPEED;
01460
01461   I2C_Init(IOE_I2C, &I2C_InitStructure);
01462 }
01463
01464 /**
01465   * @brief  Configure the DMA Peripheral used to handle communication via I2C.
01466   * @param  None
01467   * @retval None
01468   */
01469
01470 static void IOE_DMA_Config(IOE_DMADirection_TypeDef Direction, uint8_t* buffer)
01471 {
01472   DMA_InitTypeDef DMA_InitStructure;
01473
01474   RCC_AHBPeriphClockCmd(IOE_DMA_CLK, ENABLE);
01475
01476   /* Initialize the DMA_PeripheralBaseAddr member */
01477   DMA_InitStructure.DMA_PeripheralBaseAddr = IOE_I2C_DR;
01478   /* Initialize the DMA_MemoryBaseAddr member */
01479   DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)buffer;
01480    /* Initialize the DMA_PeripheralInc member */
01481   DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
01482   /* Initialize the DMA_MemoryInc member */
01483   DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
01484   /* Initialize the DMA_PeripheralDataSize member */
01485   DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
01486   /* Initialize the DMA_MemoryDataSize member */
01487   DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
01488   /* Initialize the DMA_Mode member */
01489   DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
01490   /* Initialize the DMA_Priority member */
01491   DMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh;
01492   /* Initialize the DMA_M2M member */
01493   DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
01494
01495   /* If using DMA for Reception */
01496   if (Direction == IOE_DMA_RX)
01497   {
01498     /* Initialize the DMA_DIR member */
01499     DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
01500
01501     /* Initialize the DMA_BufferSize member */
01502     DMA_InitStructure.DMA_BufferSize = 2;
01503
01504     DMA_DeInit(IOE_DMA_RX_CHANNEL);
01505
01506     DMA_Init(IOE_DMA_RX_CHANNEL, &DMA_InitStructure);
01507   }
01508    /* If using DMA for Transmission */
01509   else if (Direction == IOE_DMA_TX)
01510   {
01511     /* Initialize the DMA_DIR member */
01512     DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
01513
01514     /* Initialize the DMA_BufferSize member */
01515     DMA_InitStructure.DMA_BufferSize = 1;
01516
01517     DMA_DeInit(IOE_DMA_TX_CHANNEL);
01518
01519     DMA_Init(IOE_DMA_TX_CHANNEL, &DMA_InitStructure);
01520   }
01521 }
01522
01523 /**
01524   * @brief  Configures the IO expander Interrupt line and GPIO in EXTI mode.
01525   * @param  None
01526   * @retval None
01527   */
01528 static void IOE_EXTI_Config(void)
01529 {
01530   GPIO_InitTypeDef GPIO_InitStructure;
01531   NVIC_InitTypeDef NVIC_InitStructure;
01532   EXTI_InitTypeDef EXTI_InitStructure;
01533
01534   /* Enable Button GPIO clock */
01535   RCC_APB2PeriphClockCmd(IOE_IT_GPIO_CLK | RCC_APB2Periph_AFIO, ENABLE);
01536
01537   /* Configure Button pin as input floating */
01538   GPIO_InitStructure.GPIO_Pin = IOE_IT_PIN;
01539   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
01540   GPIO_Init(IOE_IT_GPIO_PORT, &GPIO_InitStructure);
01541
01542   /* Connect Button EXTI Line to Button GPIO Pin */
01543   GPIO_EXTILineConfig(IOE_IT_EXTI_PORT_SOURCE, IOE_IT_EXTI_PIN_SOURCE);
01544
01545   /* Configure Button EXTI line */
01546   EXTI_InitStructure.EXTI_Line = IOE_IT_EXTI_LINE;
01547   EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
01548   EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising_Falling;
01549   EXTI_InitStructure.EXTI_LineCmd = ENABLE;
01550   EXTI_Init(&EXTI_InitStructure);
01551
01552   /* Enable and set Button EXTI Interrupt to the lowest priority */
01553   NVIC_InitStructure.NVIC_IRQChannel = IOE_IT_EXTI_IRQn;
01554   NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x0F;
01555   NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x0F;
01556   NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
01557   NVIC_Init(&NVIC_InitStructure);
01558 }
01559
01560 #ifndef USE_Delay
01561 /**
01562   * @brief  Inserts a delay time.
01563   * @param  nCount: specifies the delay time length.
01564   * @retval None
01565   */
01566 static void delay(__IO uint32_t nCount)
01567 {
01568   __IO uint32_t index = 0;
01569   for(index = (100000 * nCount); index != 0; index--)
01570   {
01571   }
01572 }
01573 #endif /* USE_Delay*/
01574 /**
01575   * @}
01576   */
01577
01578 /**
01579   * @}
01580   */
01581
01582 /**
01583   * @}
01584   */
01585
01586 /**
01587   * @}
01588   */
01589
01590 /**
01591   * @}
01592   */
01593
01594 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm3210c_eval_ioe.h Source File

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stm3210c_eval_ioe.h

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00001 /**
00002   ******************************************************************************
00003   * @file    stm3210c_eval_ioe.h
00004   * @author  MCD Application Team
00005   * @version V4.5.0
00006   * @date    07-March-2011
00007   * @brief   This file contains all the functions prototypes for the IO Expander
00008   *   firmware driver.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00013   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00014   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00015   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00016   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00017   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00018   *
00019   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00020   ******************************************************************************
00021   */
00022
00023   /* File Info : ---------------------------------------------------------------
00024     SUPPORTED FEATURES:
00025       - IO Read/write : Set/Reset and Read (Polling/Interrupt)
00026       - Joystick: config and Read (Polling/Interrupt)
00027       - Touch Screen Features: Single point mode (Polling/Interrupt)
00028       - TempSensor Feature: accuracy not determined (Polling).
00029
00030     UNSUPPORTED FEATURES:
00031       - Row ADC Feature is not supported (not implemented on STM3210C-EVAL board)
00032   ----------------------------------------------------------------------------*/
00033
00034
00035 /* Define to prevent recursive inclusion -------------------------------------*/
00036 #ifndef __STM3210C_EVAL_IOE_H
00037 #define __STM3210C_EVAL_IOE_H
00038
00039 #ifdef __cplusplus
00040  extern "C" {
00041 #endif
00042
00043 /* Includes ------------------------------------------------------------------*/
00044 #include "stm32f10x.h"
00045
00046 /** @addtogroup Utilities
00047   * @{
00048   */
00049
00050 /** @addtogroup STM32_EVAL
00051   * @{
00052   */
00053
00054 /** @addtogroup STM3210C_EVAL
00055   * @{
00056   */
00057
00058 /** @defgroup STM3210C_EVAL_IOE
00059   * @{
00060   */
00061
00062 /** @defgroup STM3210C_EVAL_IOE_Exported_Types
00063   * @{
00064   */
00065
00066 /**
00067   * @brief  Touch Screen Information structure
00068   */
00069 typedef struct
00070 {
00071   uint16_t TouchDetected;
00072   uint16_t X;
00073   uint16_t Y;
00074   uint16_t Z;
00075 }TS_STATE;
00076
00077 /**
00078   * @brief  Joystick State definitions
00079   */
00080 #ifndef __STM32_EVAL_H
00081 typedef enum
00082 {
00083   JOY_NONE = 0,
00084   JOY_SEL = 1,
00085   JOY_DOWN = 2,
00086   JOY_LEFT = 3,
00087   JOY_RIGHT = 4,
00088   JOY_UP = 5
00089 } JOYState_TypeDef
00090 ;
00091 #endif /* __STM32_EVAL_H */
00092
00093 /**
00094   * @brief  IO_Expander Error codes
00095   */
00096 typedef enum
00097 {
00098   IOE_OK = 0,
00099   IOE_FAILURE,
00100   IOE_TIMEOUT,
00101   PARAM_ERROR,
00102   IOE1_NOT_OPERATIONAL,
00103   IOE2_NOT_OPERATIONAL
00104 }IOE_Status_TypDef;
00105
00106 /**
00107   * @brief  IO bit values
00108   */
00109 typedef enum
00110 {
00111   BitReset = 0,
00112   BitSet = 1
00113 }IOE_BitValue_TypeDef;
00114
00115 /**
00116   * @brief  IOE DMA Direction
00117   */
00118 typedef enum
00119 {
00120   IOE_DMA_TX = 0,
00121   IOE_DMA_RX = 1
00122 }IOE_DMADirection_TypeDef;
00123
00124 /**
00125   * @}
00126   */
00127
00128
00129 /** @defgroup STM3210C_EVAL_IOE_Exported_Constants
00130   * @{
00131   */
00132
00133 /**
00134  * @brief Uncomment the line below to enable verfying each written byte in write
00135  *        operation. The I2C_WriteDeviceRegister() function will then compare the
00136  *        written and read data and return error status if a mismatch occurs.
00137  */
00138 /* #define VERIFY_WRITTENDATA */
00139
00140 /**
00141  * @brief Uncomment the line below if you want to use user defined Delay function
00142  *        (for precise timing), otherwise default _delay_ function defined within
00143  *         this driver is used (less precise timing).
00144  */
00145 /* #define USE_Delay */
00146
00147 /**
00148  * @brief Uncomment the line below if you want to use user timeout callback.
00149  *        Function prototypes is declared in this file but function body may be
00150  *        implemented into user application.
00151  */
00152 /* #define USE_TIMEOUT_USER_CALLBACK */
00153
00154 #ifdef USE_Delay
00155 #include "main.h"
00156
00157   #define _delay_     Delay  /* !< User can provide more timing precise _delay_ function
00158                                    (with 10ms time base), using SysTick for example */
00159 #else
00160   #define _delay_     delay      /* !< Default _delay_ function with less precise timing */
00161 #endif
00162
00163 /*------------------------------------------------------------------------------
00164     Hardware Configuration
00165 ------------------------------------------------------------------------------*/
00166 /**
00167   * @brief  I2C port definitions
00168   */
00169 #define IOE_I2C                          I2C1
00170 #define IOE_I2C_CLK                      RCC_APB1Periph_I2C1
00171 #define IOE_I2C_SCL_PIN                  GPIO_Pin_6
00172 #define IOE_I2C_SCL_GPIO_PORT            GPIOB
00173 #define IOE_I2C_SCL_GPIO_CLK             RCC_APB2Periph_GPIOB
00174 #define IOE_I2C_SDA_PIN                  GPIO_Pin_7
00175 #define IOE_I2C_SDA_GPIO_PORT            GPIOB
00176 #define IOE_I2C_SDA_GPIO_CLK             RCC_APB2Periph_GPIOB
00177 #define IOE_I2C_DR                       ((uint32_t)0x40005410)
00178 #define IOE_I2C_SPEED                    300000
00179
00180 /**
00181   * @brief  IOE DMA definitions
00182   */
00183 #define IOE_DMA                          DMA1
00184 #define IOE_DMA_CLK                      RCC_AHBPeriph_DMA1
00185 #define IOE_DMA_TX_CHANNEL               DMA1_Channel6
00186 #define IOE_DMA_RX_CHANNEL               DMA1_Channel7
00187 #define IOE_DMA_TX_TCFLAG                DMA1_FLAG_TC6
00188 #define IOE_DMA_RX_TCFLAG                DMA1_FLAG_TC7
00189
00190
00191 /**
00192   * @brief  IO Expander Interrupt line on EXTI
00193   */
00194 #define IOE_IT_PIN                       GPIO_Pin_14
00195 #define IOE_IT_GPIO_PORT                 GPIOB
00196 #define IOE_IT_GPIO_CLK                  RCC_APB2Periph_GPIOB
00197 #define IOE_IT_EXTI_PORT_SOURCE          GPIO_PortSourceGPIOB
00198 #define IOE_IT_EXTI_PIN_SOURCE           GPIO_PinSource14
00199 #define IOE_IT_EXTI_LINE                 EXTI_Line14
00200 #define IOE_IT_EXTI_IRQn                 EXTI15_10_IRQn
00201
00202 /**
00203   * @brief Eval Board IO Pins definition
00204   */
00205 #define AUDIO_RESET_PIN             IO_Pin_2 /* IO_Exapnader_2 */ /* Output */
00206 #define MII_INT_PIN                 IO_Pin_0 /* IO_Exapnader_2 */ /* Output */
00207 #define VBAT_DIV_PIN                IO_Pin_0 /* IO_Exapnader_1 */ /* Output */
00208 #define MEMS_INT1_PIN               IO_Pin_3 /* IO_Exapnader_1 */ /* Input */
00209 #define MEMS_INT2_PIN               IO_Pin_2 /* IO_Exapnader_1 */ /* Input */
00210
00211
00212 /**
00213   * @brief Eval Board both IO Exapanders Pins definition
00214   */
00215 #define IO1_IN_ALL_PINS          (uint32_t)(MEMS_INT1_PIN | MEMS_INT2_PIN)
00216 #define IO2_IN_ALL_PINS          (uint32_t)(JOY_IO_PINS)
00217 #define IO1_OUT_ALL_PINS         (uint32_t)(VBAT_DIV_PIN)
00218 #define IO2_OUT_ALL_PINS         (uint32_t)(AUDIO_RESET_PIN | MII_INT_PIN)
00219
00220 /**
00221   * @brief  The 7 bits IO Expanders adresses and chip IDs
00222   */
00223 #define IOE_1_ADDR                 0x82
00224 #define IOE_2_ADDR                 0x88
00225 #define STMPE811_ID                0x0811
00226
00227
00228 /*------------------------------------------------------------------------------
00229     Functional and Interrupt Management
00230 ------------------------------------------------------------------------------*/
00231 /**
00232   * @brief  IO Expander Functionalities definitions
00233   */
00234 #define IOE_ADC_FCT              0x01
00235 #define IOE_TS_FCT               0x02
00236 #define IOE_IO_FCT               0x04
00237 #define IOE_TEMPSENS_FCT         0x08
00238
00239 /**
00240   * @brief  Interrupt source configuration definitons
00241   */
00242 #define IOE_ITSRC_TSC           0x01  /* IO_Exapnder 1 */
00243 #define IOE_ITSRC_INMEMS        0x02  /* IO_Exapnder 1 */
00244 #define IOE_ITSRC_JOYSTICK      0x04  /* IO_Exapnder 2 */
00245 #define IOE_ITSRC_TEMPSENS      0x08  /* IO_Exapnder 2 */
00246
00247 /**
00248   * @brief  Glaobal Interrupts definitions
00249   */
00250 #define IOE_GIT_GPIO             0x80
00251 #define IOE_GIT_ADC              0x40
00252 #define IOE_GIT_TEMP             0x20
00253 #define IOE_GIT_FE               0x10
00254 #define IOE_GIT_FF               0x08
00255 #define IOE_GIT_FOV              0x04
00256 #define IOE_GIT_FTH              0x02
00257 #define IOE_GIT_TOUCH            0x01
00258
00259
00260 /*------------------------------------------------------------------------------
00261     STMPE811 device register definition
00262 ------------------------------------------------------------------------------*/
00263 /**
00264   * @brief  Identification registers
00265   */
00266 #define IOE_REG_CHP_ID             0x00
00267 #define IOE_REG_ID_VER             0x02
00268
00269 /**
00270   * @brief  General Control Registers
00271   */
00272 #define IOE_REG_SYS_CTRL1          0x03
00273 #define IOE_REG_SYS_CTRL2          0x04
00274 #define IOE_REG_SPI_CFG            0x08
00275
00276 /**
00277   * @brief  Interrupt Control register
00278   */
00279 #define IOE_REG_INT_CTRL           0x09
00280 #define IOE_REG_INT_EN             0x0A
00281 #define IOE_REG_INT_STA            0x0B
00282 #define IOE_REG_GPIO_INT_EN        0x0C
00283 #define IOE_REG_GPIO_INT_STA       0x0D
00284
00285 /**
00286   * @brief  GPIO Registers
00287   */
00288 #define IOE_REG_GPIO_SET_PIN       0x10
00289 #define IOE_REG_GPIO_CLR_PIN       0x11
00290 #define IOE_REG_GPIO_MP_STA        0x12
00291 #define IOE_REG_GPIO_DIR           0x13
00292 #define IOE_REG_GPIO_ED            0x14
00293 #define IOE_REG_GPIO_RE            0x15
00294 #define IOE_REG_GPIO_FE            0x16
00295 #define IOE_REG_GPIO_AF            0x17
00296
00297 /**
00298   * @brief  ADC Registers
00299   */
00300 #define IOE_REG_ADC_INT_EN         0x0E
00301 #define IOE_REG_ADC_INT_STA        0x0F
00302 #define IOE_REG_ADC_CTRL1          0x20
00303 #define IOE_REG_ADC_CTRL2          0x21
00304 #define IOE_REG_ADC_CAPT           0x22
00305 #define IOE_REG_ADC_DATA_CH0       0x30 /* 16-Bit register */
00306 #define IOE_REG_ADC_DATA_CH1       0x32 /* 16-Bit register */
00307 #define IOE_REG_ADC_DATA_CH2       0x34 /* 16-Bit register */
00308 #define IOE_REG_ADC_DATA_CH3       0x36 /* 16-Bit register */
00309 #define IOE_REG_ADC_DATA_CH4       0x38 /* 16-Bit register */
00310 #define IOE_REG_ADC_DATA_CH5       0x3A /* 16-Bit register */
00311 #define IOE_REG_ADC_DATA_CH6       0x3B /* 16-Bit register */
00312 #define IOE_REG_ADC_DATA_CH7       0x3C /* 16-Bit register */
00313
00314 /**
00315   * @brief  TouchScreen Registers
00316   */
00317 #define IOE_REG_TSC_CTRL           0x40
00318 #define IOE_REG_TSC_CFG            0x41
00319 #define IOE_REG_WDM_TR_X           0x42
00320 #define IOE_REG_WDM_TR_Y           0x44
00321 #define IOE_REG_WDM_BL_X           0x46
00322 #define IOE_REG_WDM_BL_Y           0x48
00323 #define IOE_REG_FIFO_TH            0x4A
00324 #define IOE_REG_FIFO_STA           0x4B
00325 #define IOE_REG_FIFO_SIZE          0x4C
00326 #define IOE_REG_TSC_DATA_X         0x4D
00327 #define IOE_REG_TSC_DATA_Y         0x4F
00328 #define IOE_REG_TSC_DATA_Z         0x51
00329 #define IOE_REG_TSC_DATA_XYZ       0x52
00330 #define IOE_REG_TSC_FRACT_XYZ      0x56
00331 #define IOE_REG_TSC_DATA           0x57
00332 #define IOE_REG_TSC_I_DRIVE        0x58
00333 #define IOE_REG_TSC_SHIELD         0x59
00334
00335 /**
00336   * @brief  Temperature Sensor registers
00337   */
00338 #define IOE_REG_TEMP_CTRL          0x60
00339 #define IOE_REG_TEMP_DATA          0x61
00340 #define IOE_REG_TEMP_TH            0x62
00341
00342
00343 /*------------------------------------------------------------------------------
00344     Functions parameters defines
00345 ------------------------------------------------------------------------------*/
00346 /**
00347   * @brief Touch Screen Pins definition
00348   */
00349 #define TOUCH_YD                    IO_Pin_1 /* IO_Exapnader_1 */ /* Input */
00350 #define TOUCH_XD                    IO_Pin_2 /* IO_Exapnader_1 */ /* Input */
00351 #define TOUCH_YU                    IO_Pin_3 /* IO_Exapnader_1 */ /* Input */
00352 #define TOUCH_XU                    IO_Pin_4 /* IO_Exapnader_1 */ /* Input */
00353 #define TOUCH_IO_ALL                (uint32_t)(IO_Pin_1 | IO_Pin_2 | IO_Pin_3 | IO_Pin_4)
00354
00355 /**
00356   * @brief  JOYSTICK Pins definition
00357   */
00358 #define JOY_IO_SEL                   IO_Pin_7
00359 #define JOY_IO_DOWN                  IO_Pin_6
00360 #define JOY_IO_LEFT                  IO_Pin_5
00361 #define JOY_IO_RIGHT                 IO_Pin_4
00362 #define JOY_IO_UP                    IO_Pin_3
00363 #define JOY_IO_NONE                  JOY_IO_PINS
00364 #define JOY_IO_PINS                  (uint32_t)(IO_Pin_3 | IO_Pin_4 | IO_Pin_5 | IO_Pin_6 | IO_Pin_7)
00365
00366 /**
00367   * @brief  IO Pins
00368   */
00369 #define IO_Pin_0                 0x01
00370 #define IO_Pin_1                 0x02
00371 #define IO_Pin_2                 0x04
00372 #define IO_Pin_3                 0x08
00373 #define IO_Pin_4                 0x10
00374 #define IO_Pin_5                 0x20
00375 #define IO_Pin_6                 0x40
00376 #define IO_Pin_7                 0x80
00377 #define IO_Pin_ALL               0xFF
00378
00379 /**
00380   * @brief  IO Pin directions
00381   */
00382 #define Direction_IN             0x00
00383 #define Direction_OUT            0x01
00384
00385 /**
00386   * @brief  Interrupt Line output parameters
00387   */
00388 #define Polarity_Low             0x00
00389 #define Polarity_High            0x04
00390 #define Type_Level               0x00
00391 #define Type_Edge                0x02
00392
00393 /**
00394   * @brief IO Interrupts
00395   */
00396 #define IO_IT_0                  0x01
00397 #define IO_IT_1                  0x02
00398 #define IO_IT_2                  0x04
00399 #define IO_IT_3                  0x08
00400 #define IO_IT_4                  0x10
00401 #define IO_IT_5                  0x20
00402 #define IO_IT_6                  0x40
00403 #define IO_IT_7                  0x80
00404 #define ALL_IT                   0xFF
00405 #define IOE_JOY_IT               (uint8_t)(IO_IT_3 | IO_IT_4 | IO_IT_5 | IO_IT_6 | IO_IT_7)
00406 #define IOE_TS_IT                (uint8_t)(IO_IT_0 | IO_IT_1 | IO_IT_2)
00407 #define IOE_INMEMS_IT            (uint8_t)(IO_IT_2 | IO_IT_3)
00408
00409 /**
00410   * @brief  Edge detection value
00411   */
00412 #define EDGE_FALLING              0x01
00413 #define EDGE_RISING               0x02
00414
00415 /**
00416   * @brief  Global interrupt Enable bit
00417   */
00418 #define IOE_GIT_EN                0x01
00419
00420 /**
00421   * @}
00422   */
00423
00424
00425
00426 /** @defgroup STM3210C_EVAL_IOE_Exported_Macros
00427   * @{
00428   */
00429 /**
00430   * @}
00431   */
00432
00433
00434
00435 /** @defgroup STM3210C_EVAL_IOE_Exported_Functions
00436   * @{
00437   */
00438
00439 /**
00440   * @brief  Configuration and initialization functions
00441   */
00442 uint8_t IOE_Config(void);
00443 uint8_t IOE_ITConfig(uint32_t IOE_ITSRC_Source);
00444
00445 /**
00446   * @brief  Timeout user callback function. This function is called when a timeout
00447   *         condition occurs during communication with IO Expander. Only protoype
00448   *         of this function is decalred in IO Expander driver. Its implementation
00449   *         may be done into user application. This function may typically stop
00450   *         current operations and reset the I2C peripheral and IO Expander.
00451   *         To enable this function use uncomment the define USE_TIMEOUT_USER_CALLBACK
00452   *         at the top of this file.
00453   */
00454 #ifdef USE_TIMEOUT_USER_CALLBACK
00455  uint8_t IOE_TimeoutUserCallback(void);
00456 #else
00457  #define IOE_TimeoutUserCallback()  IOE_TIMEOUT
00458 #endif /* USE_TIMEOUT_USER_CALLBACK */
00459
00460 /**
00461   * @brief IO pins control functions
00462   */
00463 uint8_t IOE_WriteIOPin(uint8_t IO_Pin, IOE_BitValue_TypeDef BitVal);
00464 uint8_t IOE_ReadIOPin(uint32_t IO_Pin);
00465 JOYState_TypeDef
00466  IOE_JoyStickGetState(void);
00467
00468 /**
00469   * @brief Touch Screen controller functions
00470   */
00471 TS_STATE* IOE_TS_GetState(void);
00472
00473 /**
00474   * @brief Interrupts Mangement functions
00475   */
00476 FlagStatus IOE_GetGITStatus(uint8_t DeviceAddr, uint8_t Global_IT);
00477 uint8_t IOE_ClearGITPending(uint8_t DeviceAddr, uint8_t IO_IT);
00478 FlagStatus IOE_GetIOITStatus(uint8_t DeviceAddr, uint8_t IO_IT);
00479 uint8_t IOE_ClearIOITPending(uint8_t DeviceAddr, uint8_t IO_IT);
00480
00481 /**
00482   * @brief Temperature Sensor functions
00483   */
00484 uint32_t IOE_TempSens_GetData(void);
00485
00486 /**
00487   * @brief IO-Expander Control functions
00488   */
00489 uint8_t IOE_IsOperational(uint8_t DeviceAddr);
00490 uint8_t IOE_Reset(uint8_t DeviceAddr);
00491 uint16_t IOE_ReadID(uint8_t DeviceAddr);
00492
00493 uint8_t IOE_FnctCmd(uint8_t DeviceAddr, uint8_t Fct, FunctionalState NewState);
00494 uint8_t IOE_IOPinConfig(uint8_t DeviceAddr, uint8_t IO_Pin, uint8_t Direction);
00495 uint8_t IOE_GITCmd(uint8_t DeviceAddr, FunctionalState NewState);
00496 uint8_t IOE_GITConfig(uint8_t DeviceAddr, uint8_t Global_IT, FunctionalState NewState);
00497 uint8_t IOE_IOITConfig(uint8_t DeviceAddr, uint8_t IO_IT, FunctionalState NewState);
00498
00499 /**
00500   * @brief Low Layer functions
00501   */
00502 uint8_t IOE_TS_Config(void);
00503 uint8_t IOE_TempSens_Config(void);
00504 uint8_t IOE_IOAFConfig(uint8_t DeviceAddr, uint8_t IO_Pin, FunctionalState NewState);
00505 uint8_t IOE_IOEdgeConfig(uint8_t DeviceAddr, uint8_t IO_Pin, uint8_t Edge);
00506 uint8_t IOE_ITOutConfig(uint8_t Polarity, uint8_t Type);
00507
00508 uint8_t I2C_WriteDeviceRegister(uint8_t DeviceAddr, uint8_t RegisterAddr, uint8_t RegisterValue);
00509 uint8_t I2C_ReadDeviceRegister(uint8_t DeviceAddr, uint8_t RegisterAddr);
00510 uint16_t I2C_ReadDataBuffer(uint8_t DeviceAddr, uint32_t RegisterAddr);
00511
00512 #ifdef __cplusplus
00513 }
00514
00515 #endif
00516 #endif /* __STM3210C_EVAL_IOE_H */
00517
00518 /**
00519   * @}
00520   */
00521
00522 /**
00523   * @}
00524   */
00525
00526 /**
00527   * @}
00528   */
00529
00530 /**
00531   * @}
00532   */
00533
00534 /**
00535   * @}
00536   */
00537 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm3210c_eval_lcd.c Source File

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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • STM3210C_EVAL

stm3210c_eval_lcd.c

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00001 /**
00002   ******************************************************************************
00003   * @file    stm3210c_eval_lcd.c
00004   * @author  MCD Application Team
00005   * @version V4.5.0
00006   * @date    07-March-2011
00007   * @brief   This file includes the LCD driver for AM-240320L8TNQW00H (LCD_ILI9320)
00008   *          Liquid Crystal Display Module of STM3210C-EVAL board.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00013   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00014   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00015   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00016   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00017   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00018   *
00019   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00020   ******************************************************************************
00021   */
00022
00023 /* Includes ------------------------------------------------------------------*/
00024 #include "stm3210c_eval_lcd.h"
00025 #include "../Common/fonts.c"
00026
00027 /** @addtogroup Utilities
00028   * @{
00029   */
00030
00031 /** @addtogroup STM32_EVAL
00032   * @{
00033   */
00034
00035 /** @addtogroup STM3210C_EVAL
00036   * @{
00037   */
00038
00039 /** @defgroup STM3210C_EVAL_LCD
00040   * @brief This file includes the LCD driver for AM-240320L8TNQW00H (LCD_ILI9320)
00041   *        Liquid Crystal Display Module of STM3210C-EVAL board.
00042   * @{
00043   */
00044
00045 /** @defgroup STM3210C_EVAL_LCD_Private_TypesDefinitions
00046   * @{
00047   */
00048 /**
00049   * @}
00050   */
00051
00052
00053 /** @defgroup STM3210C_EVAL_LCD_Private_Defines
00054   * @{
00055   */
00056 #define START_BYTE         0x70
00057 #define SET_INDEX          0x00
00058 #define READ_STATUS        0x01
00059 #define LCD_WRITE_REG      0x02
00060 #define LCD_READ_REG       0x03
00061 #define MAX_POLY_CORNERS   200
00062 #define POLY_Y(Z)          ((int32_t)((Points + Z)->X))
00063 #define POLY_X(Z)          ((int32_t)((Points + Z)->Y))
00064 /**
00065   * @}
00066   */
00067
00068
00069 /** @defgroup STM3210C_EVAL_LCD_Private_Macros
00070   * @{
00071   */
00072 #define ABS(X)  ((X) > 0 ? (X) : -(X))
00073 /**
00074   * @}
00075   */
00076
00077
00078 /** @defgroup STM3210C_EVAL_LCD_Private_Variables
00079   * @{
00080   */
00081 static sFONT *LCD_Currentfonts;
00082 /* Global variables to set the written text color */
00083 static  __IO uint16_t TextColor = 0x0000, BackColor = 0xFFFF;
00084 /**
00085   * @}
00086   */
00087
00088
00089 /** @defgroup STM3210C_EVAL_LCD_Private_FunctionPrototypes
00090   * @{
00091   */
00092 #ifndef USE_Delay
00093 static void delay(__IO uint32_t nCount);
00094 #endif /* USE_Delay*/
00095 static void PutPixel(int16_t x, int16_t y);
00096 static void LCD_PolyLineRelativeClosed(pPoint Points, uint16_t PointCount, uint16_t Closed);
00097 /**
00098   * @}
00099   */
00100
00101
00102 /** @defgroup STM3210C_EVAL_LCD_Private_Functions
00103   * @{
00104   */
00105
00106 /**
00107   * @brief  DeInitializes the LCD.
00108   * @param  None
00109   * @retval None
00110   */
00111 void LCD_DeInit(void)
00112 {
00113   GPIO_InitTypeDef GPIO_InitStructure;
00114
00115   /*!< LCD Display Off */
00116   LCD_DisplayOff();
00117
00118   /*!< LCD_SPI disable */
00119   SPI_Cmd(LCD_SPI, DISABLE);
00120
00121   /*!< LCD_SPI DeInit */
00122   SPI_I2S_DeInit(LCD_SPI);
00123
00124   /*!< Disable SPI clock  */
00125   RCC_APB1PeriphClockCmd(LCD_SPI_CLK, DISABLE);
00126   GPIO_PinRemapConfig(GPIO_Remap_SPI3, DISABLE);
00127
00128   /* Configure NCS in Output Push-Pull mode */
00129   GPIO_InitStructure.GPIO_Pin = LCD_NCS_PIN;
00130   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
00131   GPIO_Init(LCD_NCS_GPIO_PORT, &GPIO_InitStructure);
00132
00133   /* Configure SPI pins: SCK, MISO and MOSI */
00134   GPIO_InitStructure.GPIO_Pin = LCD_SPI_SCK_PIN;
00135   GPIO_Init(LCD_SPI_SCK_GPIO_PORT, &GPIO_InitStructure);
00136
00137   GPIO_InitStructure.GPIO_Pin = LCD_SPI_MISO_PIN;
00138   GPIO_Init(LCD_SPI_MISO_GPIO_PORT, &GPIO_InitStructure);
00139
00140   GPIO_InitStructure.GPIO_Pin = LCD_SPI_MOSI_PIN;
00141   GPIO_Init(LCD_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure);
00142 }
00143
00144 /**
00145   * @brief  Setups the LCD.
00146   * @param  None
00147   * @retval None
00148   */
00149 void LCD_Setup(void)
00150 {
00151 /* Configure the LCD Control pins --------------------------------------------*/
00152   LCD_CtrlLinesConfig();
00153
00154 /* Configure the LCD_SPI interface ----------------------------------------------*/
00155   LCD_SPIConfig();
00156   _delay_(5); /* Delay 50 ms */
00157   /* Start Initial Sequence ------------------------------------------------*/
00158   LCD_WriteReg(LCD_REG_229, 0x8000); /* Set the internal vcore voltage */
00159   LCD_WriteReg(LCD_REG_0,  0x0001); /* Start internal OSC. */
00160   LCD_WriteReg(LCD_REG_1,  0x0100); /* set SS and SM bit */
00161   LCD_WriteReg(LCD_REG_2,  0x0700); /* set 1 line inversion */
00162   LCD_WriteReg(LCD_REG_3,  0x1030); /* set GRAM write direction and BGR=1. */
00163   LCD_WriteReg(LCD_REG_4,  0x0000); /* Resize register */
00164   LCD_WriteReg(LCD_REG_8,  0x0202); /* set the back porch and front porch */
00165   LCD_WriteReg(LCD_REG_9,  0x0000); /* set non-display area refresh cycle ISC[3:0] */
00166   LCD_WriteReg(LCD_REG_10, 0x0000); /* FMARK function */
00167   LCD_WriteReg(LCD_REG_12, 0x0000); /* RGB interface setting */
00168   LCD_WriteReg(LCD_REG_13, 0x0000); /* Frame marker Position */
00169   LCD_WriteReg(LCD_REG_15, 0x0000); /* RGB interface polarity */
00170   /* Power On sequence -----------------------------------------------------*/
00171   LCD_WriteReg(LCD_REG_16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
00172   LCD_WriteReg(LCD_REG_17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */
00173   LCD_WriteReg(LCD_REG_18, 0x0000); /* VREG1OUT voltage */
00174   LCD_WriteReg(LCD_REG_19, 0x0000); /* VDV[4:0] for VCOM amplitude */
00175   _delay_(20);                 /* Dis-charge capacitor power voltage (200ms) */
00176   LCD_WriteReg(LCD_REG_16, 0x17B0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
00177   LCD_WriteReg(LCD_REG_17, 0x0137); /* DC1[2:0], DC0[2:0], VC[2:0] */
00178   _delay_(5);                  /* Delay 50 ms */
00179   LCD_WriteReg(LCD_REG_18, 0x0139); /* VREG1OUT voltage */
00180   _delay_(5);                  /* Delay 50 ms */
00181   LCD_WriteReg(LCD_REG_19, 0x1d00); /* VDV[4:0] for VCOM amplitude */
00182   LCD_WriteReg(LCD_REG_41, 0x0013); /* VCM[4:0] for VCOMH */
00183   _delay_(5);                  /* Delay 50 ms */
00184   LCD_WriteReg(LCD_REG_32, 0x0000); /* GRAM horizontal Address */
00185   LCD_WriteReg(LCD_REG_33, 0x0000); /* GRAM Vertical Address */
00186   /* Adjust the Gamma Curve ------------------------------------------------*/
00187   LCD_WriteReg(LCD_REG_48, 0x0006);
00188   LCD_WriteReg(LCD_REG_49, 0x0101);
00189   LCD_WriteReg(LCD_REG_50, 0x0003);
00190   LCD_WriteReg(LCD_REG_53, 0x0106);
00191   LCD_WriteReg(LCD_REG_54, 0x0b02);
00192   LCD_WriteReg(LCD_REG_55, 0x0302);
00193   LCD_WriteReg(LCD_REG_56, 0x0707);
00194   LCD_WriteReg(LCD_REG_57, 0x0007);
00195   LCD_WriteReg(LCD_REG_60, 0x0600);
00196   LCD_WriteReg(LCD_REG_61, 0x020b);
00197
00198   /* Set GRAM area ---------------------------------------------------------*/
00199   LCD_WriteReg(LCD_REG_80, 0x0000); /* Horizontal GRAM Start Address */
00200   LCD_WriteReg(LCD_REG_81, 0x00EF); /* Horizontal GRAM End Address */
00201   LCD_WriteReg(LCD_REG_82, 0x0000); /* Vertical GRAM Start Address */
00202   LCD_WriteReg(LCD_REG_83, 0x013F); /* Vertical GRAM End Address */
00203   LCD_WriteReg(LCD_REG_96,  0x2700); /* Gate Scan Line */
00204   LCD_WriteReg(LCD_REG_97,  0x0001); /* NDL,VLE, REV */
00205   LCD_WriteReg(LCD_REG_106, 0x0000); /* set scrolling line */
00206   /* Partial Display Control -----------------------------------------------*/
00207   LCD_WriteReg(LCD_REG_128, 0x0000);
00208   LCD_WriteReg(LCD_REG_129, 0x0000);
00209   LCD_WriteReg(LCD_REG_130, 0x0000);
00210   LCD_WriteReg(LCD_REG_131, 0x0000);
00211   LCD_WriteReg(LCD_REG_132, 0x0000);
00212   LCD_WriteReg(LCD_REG_133, 0x0000);
00213   /* Panel Control ---------------------------------------------------------*/
00214   LCD_WriteReg(LCD_REG_144, 0x0010);
00215   LCD_WriteReg(LCD_REG_146, 0x0000);
00216   LCD_WriteReg(LCD_REG_147, 0x0003);
00217   LCD_WriteReg(LCD_REG_149, 0x0110);
00218   LCD_WriteReg(LCD_REG_151, 0x0000);
00219   LCD_WriteReg(LCD_REG_152, 0x0000);
00220   /* Set GRAM write direction and BGR = 1 */
00221   /* I/D=01 (Horizontal : increment, Vertical : decrement) */
00222   /* AM=1 (address is updated in vertical writing direction) */
00223   LCD_WriteReg(LCD_REG_3, 0x1018);
00224   LCD_WriteReg(LCD_REG_7, 0x0173); /* 262K color and display ON */
00225 }
00226
00227
00228 /**
00229   * @brief  Initializes the LCD.
00230   * @param  None
00231   * @retval None
00232   */
00233 void STM3210C_LCD_Init(void)
00234 {
00235   /* Setups the LCD */
00236   LCD_Setup();
00237   LCD_SetFont(&LCD_DEFAULT_FONT);
00238 }
00239
00240 /**
00241   * @brief  Sets the LCD Text and Background colors.
00242   * @param  _TextColor: specifies the Text Color.
00243   * @param  _BackColor: specifies the Background Color.
00244   * @retval None
00245   */
00246 void LCD_SetColors(__IO uint16_t _TextColor, __IO uint16_t _BackColor)
00247 {
00248   TextColor = _TextColor;
00249   BackColor = _BackColor;
00250 }
00251
00252 /**
00253   * @brief  Gets the LCD Text and Background colors.
00254   * @param  _TextColor: pointer to the variable that will contain the Text
00255             Color.
00256   * @param  _BackColor: pointer to the variable that will contain the Background
00257             Color.
00258   * @retval None
00259   */
00260 void LCD_GetColors(__IO uint16_t *_TextColor, __IO uint16_t *_BackColor)
00261 {
00262   *_TextColor = TextColor; *_BackColor = BackColor;
00263 }
00264
00265 /**
00266   * @brief  Sets the Text color.
00267   * @param  Color: specifies the Text color code RGB(5-6-5).
00268   * @retval None
00269   */
00270 void LCD_SetTextColor(__IO uint16_t Color)
00271 {
00272   TextColor = Color;
00273 }
00274
00275
00276 /**
00277   * @brief  Sets the Background color.
00278   * @param  Color: specifies the Background color code RGB(5-6-5).
00279   * @retval None
00280   */
00281 void LCD_SetBackColor(__IO uint16_t Color)
00282 {
00283   BackColor = Color;
00284 }
00285
00286 /**
00287   * @brief  Sets the Text Font.
00288   * @param  fonts: specifies the font to be used.
00289   * @retval None
00290   */
00291 void LCD_SetFont(sFONT *fonts)
00292 {
00293   LCD_Currentfonts = fonts;
00294 }
00295
00296 /**
00297   * @brief  Gets the Text Font.
00298   * @param  None.
00299   * @retval the used font.
00300   */
00301 sFONT *LCD_GetFont(void)
00302 {
00303   return LCD_Currentfonts;
00304 }
00305
00306 /**
00307   * @brief  Clears the selected line.
00308   * @param  Line: the Line to be cleared.
00309   *   This parameter can be one of the following values:
00310   *     @arg Linex: where x can be 0..n
00311   * @retval None
00312   */
00313 void LCD_ClearLine(uint8_t Line)
00314 {
00315   uint16_t refcolumn = LCD_PIXEL_WIDTH - 1;
00316   /* Send the string character by character on lCD */
00317   while (((refcolumn + 1)& 0xFFFF) >= LCD_Currentfonts->Width)
00318   {
00319     /* Display one character on LCD */
00320     LCD_DisplayChar(Line, refcolumn, ' ');
00321     /* Decrement the column position by 16 */
00322     refcolumn -= LCD_Currentfonts->Width;
00323   }
00324 }
00325
00326
00327 /**
00328   * @brief  Clears the hole LCD.
00329   * @param  Color: the color of the background.
00330   * @retval None
00331   */
00332 void LCD_Clear(uint16_t Color)
00333 {
00334   uint32_t index = 0;
00335
00336   LCD_SetCursor(0x00, 0x013F);
00337   LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
00338   for(index = 0; index < 76800; index++)
00339   {
00340     LCD_WriteRAM(Color);
00341   }
00342   LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
00343
00344 }
00345
00346
00347 /**
00348   * @brief  Sets the cursor position.
00349   * @param  Xpos: specifies the X position.
00350   * @param  Ypos: specifies the Y position.
00351   * @retval None
00352   */
00353 void LCD_SetCursor(uint8_t Xpos, uint16_t Ypos)
00354 {
00355  LCD_WriteReg(LCD_REG_32, Xpos);
00356  LCD_WriteReg(LCD_REG_33, Ypos);
00357 }
00358
00359
00360 /**
00361   * @brief  Draws a character on LCD.
00362   * @param  Xpos: the Line where to display the character shape.
00363   * @param  Ypos: start column address.
00364   * @param  c: pointer to the character data.
00365   * @retval None
00366   */
00367 void LCD_DrawChar(uint8_t Xpos, uint16_t Ypos, const uint16_t *c)
00368 {
00369   uint32_t index = 0, i = 0;
00370   uint8_t Xaddress = 0;
00371
00372   Xaddress = Xpos;
00373
00374   LCD_SetCursor(Xaddress, Ypos);
00375
00376   for(index = 0; index < LCD_Currentfonts->Height; index++)
00377   {
00378     LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
00379     for(i = 0; i < LCD_Currentfonts->Width; i++)
00380     {
00381       if((((c[index] & ((0x80 << ((LCD_Currentfonts->Width / 12 ) * 8 ) ) >> i)) == 0x00) &&(LCD_Currentfonts->Width <= 12))||
00382         (((c[index] & (0x1 << i)) == 0x00)&&(LCD_Currentfonts->Width > 12 )))
00383
00384       {
00385         LCD_WriteRAM(BackColor);
00386       }
00387       else
00388       {
00389         LCD_WriteRAM(TextColor);
00390       }
00391     }
00392     LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
00393     Xaddress++;
00394     LCD_SetCursor(Xaddress, Ypos);
00395   }
00396 }
00397
00398
00399 /**
00400   * @brief  Displays one character (16dots width, 24dots height).
00401   * @param  Line: the Line where to display the character shape .
00402   *   This parameter can be one of the following values:
00403   *     @arg Linex: where x can be 0..9
00404   * @param  Column: start column address.
00405   * @param  Ascii: character ascii code, must be between 0x20 and 0x7E.
00406   * @retval None
00407   */
00408 void LCD_DisplayChar(uint8_t Line, uint16_t Column, uint8_t Ascii)
00409 {
00410   Ascii -= 32;
00411   LCD_DrawChar(Line, Column, &LCD_Currentfonts->table[Ascii * LCD_Currentfonts->Height]);
00412 }
00413
00414
00415 /**
00416   * @brief  Displays a maximum of 20 char on the LCD.
00417   * @param  Line: the Line where to display the character shape .
00418   *   This parameter can be one of the following values:
00419   *     @arg Linex: where x can be 0..9
00420   * @param  *ptr: pointer to string to display on LCD.
00421   * @retval None
00422   */
00423 void LCD_DisplayStringLine(uint8_t Line, uint8_t *ptr)
00424 {
00425   uint16_t refcolumn = LCD_PIXEL_WIDTH - 1;
00426
00427   /* Send the string character by character on lCD */
00428   while ((*ptr != 0) & (((refcolumn + 1) & 0xFFFF) >= LCD_Currentfonts->Width))
00429   {
00430     /* Display one character on LCD */
00431     LCD_DisplayChar(Line, refcolumn, *ptr);
00432     /* Decrement the column position by 16 */
00433     refcolumn -= LCD_Currentfonts->Width;
00434     /* Point on the next character */
00435     ptr++;
00436   }
00437 }
00438
00439
00440 /**
00441   * @brief  Sets a display window
00442   * @param  Xpos: specifies the X buttom left position.
00443   * @param  Ypos: specifies the Y buttom left position.
00444   * @param  Height: display window height.
00445   * @param  Width: display window width.
00446   * @retval None
00447   */
00448 void LCD_SetDisplayWindow(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width)
00449 {
00450   /* Horizontal GRAM Start Address */
00451   if(Xpos >= Height)
00452   {
00453     LCD_WriteReg(LCD_REG_80, (Xpos - Height + 1));
00454   }
00455   else
00456   {
00457     LCD_WriteReg(LCD_REG_80, 0);
00458   }
00459   /* Horizontal GRAM End Address */
00460   LCD_WriteReg(LCD_REG_81, Xpos);
00461   /* Vertical GRAM Start Address */
00462   if(Ypos >= Width)
00463   {
00464     LCD_WriteReg(LCD_REG_82, (Ypos - Width + 1));
00465   }
00466   else
00467   {
00468     LCD_WriteReg(LCD_REG_82, 0);
00469   }
00470   /* Vertical GRAM End Address */
00471   LCD_WriteReg(LCD_REG_83, Ypos);
00472   LCD_SetCursor(Xpos, Ypos);
00473 }
00474
00475
00476 /**
00477   * @brief  Disables LCD Window mode.
00478   * @param  None
00479   * @retval None
00480   */
00481 void LCD_WindowModeDisable(void)
00482 {
00483   LCD_SetDisplayWindow(239, 0x13F, 240, 320);
00484   LCD_WriteReg(LCD_REG_3, 0x1018);
00485 }
00486
00487
00488 /**
00489   * @brief  Displays a line.
00490   * @param  Xpos: specifies the X position.
00491   * @param  Ypos: specifies the Y position.
00492   * @param  Length: line length.
00493   * @param  Direction: line direction.
00494   *   This parameter can be one of the following values: Vertical or Horizontal.
00495   * @retval None
00496   */
00497 void LCD_DrawLine(uint8_t Xpos, uint16_t Ypos, uint16_t Length, uint8_t Direction)
00498 {
00499   uint32_t i = 0;
00500
00501   LCD_SetCursor(Xpos, Ypos);
00502   if(Direction == LCD_DIR_HORIZONTAL)
00503   {
00504     LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
00505     for(i = 0; i < Length; i++)
00506     {
00507       LCD_WriteRAM(TextColor);
00508     }
00509     LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
00510   }
00511   else
00512   {
00513     for(i = 0; i < Length; i++)
00514     {
00515       LCD_WriteRAMWord(TextColor);
00516       Xpos++;
00517       LCD_SetCursor(Xpos, Ypos);
00518     }
00519   }
00520 }
00521
00522
00523 /**
00524   * @brief  Displays a rectangle.
00525   * @param  Xpos: specifies the X position.
00526   * @param  Ypos: specifies the Y position.
00527   * @param  Height: display rectangle height.
00528   * @param  Width: display rectangle width.
00529   * @retval None
00530   */
00531 void LCD_DrawRect(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width)
00532 {
00533   LCD_DrawLine(Xpos, Ypos, Width, LCD_DIR_HORIZONTAL);
00534   LCD_DrawLine((Xpos + Height), Ypos, Width, LCD_DIR_HORIZONTAL);
00535
00536   LCD_DrawLine(Xpos, Ypos, Height, LCD_DIR_VERTICAL);
00537   LCD_DrawLine(Xpos, (Ypos - Width + 1), Height, LCD_DIR_VERTICAL);
00538 }
00539
00540
00541 /**
00542   * @brief  Displays a circle.
00543   * @param  Xpos: specifies the X position.
00544   * @param  Ypos: specifies the Y position.
00545   * @param  Radius
00546   * @retval None
00547   */
00548 void LCD_DrawCircle(uint8_t Xpos, uint16_t Ypos, uint16_t Radius)
00549 {
00550   s32  D;/* Decision Variable */
00551   uint32_t  CurX;/* Current X Value */
00552   uint32_t  CurY;/* Current Y Value */
00553
00554   D = 3 - (Radius << 1);
00555   CurX = 0;
00556   CurY = Radius;
00557
00558   while (CurX <= CurY)
00559   {
00560     LCD_SetCursor(Xpos + CurX, Ypos + CurY);
00561     LCD_WriteRAMWord(TextColor);
00562     LCD_SetCursor(Xpos + CurX, Ypos - CurY);
00563     LCD_WriteRAMWord(TextColor);
00564     LCD_SetCursor(Xpos - CurX, Ypos + CurY);
00565     LCD_WriteRAMWord(TextColor);
00566     LCD_SetCursor(Xpos - CurX, Ypos - CurY);
00567     LCD_WriteRAMWord(TextColor);
00568     LCD_SetCursor(Xpos + CurY, Ypos + CurX);
00569     LCD_WriteRAMWord(TextColor);
00570     LCD_SetCursor(Xpos + CurY, Ypos - CurX);
00571     LCD_WriteRAMWord(TextColor);
00572     LCD_SetCursor(Xpos - CurY, Ypos + CurX);
00573     LCD_WriteRAMWord(TextColor);
00574     LCD_SetCursor(Xpos - CurY, Ypos - CurX);
00575     LCD_WriteRAMWord(TextColor);
00576     if (D < 0)
00577     {
00578       D += (CurX << 2) + 6;
00579     }
00580     else
00581     {
00582       D += ((CurX - CurY) << 2) + 10;
00583       CurY--;
00584     }
00585     CurX++;
00586   }
00587 }
00588
00589 /**
00590   * @brief  Displays a monocolor picture.
00591   * @param  Pict: pointer to the picture array.
00592   * @retval None
00593   */
00594 void LCD_DrawMonoPict(const uint32_t *Pict)
00595 {
00596   uint32_t index = 0, i = 0;
00597   LCD_SetCursor(0, (LCD_PIXEL_WIDTH - 1));
00598   LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
00599   for(index = 0; index < 2400; index++)
00600   {
00601     for(i = 0; i < 32; i++)
00602     {
00603       if((Pict[index] & (1 << i)) == 0x00)
00604       {
00605         LCD_WriteRAM(BackColor);
00606       }
00607       else
00608       {
00609         LCD_WriteRAM(TextColor);
00610       }
00611     }
00612   }
00613   LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
00614 }
00615
00616 #ifdef USE_LCD_DrawBMP
00617 /**
00618   * @brief  Displays a bitmap picture loaded in the SPI Flash.
00619   * @param  BmpAddress: Bmp picture address in the SPI Flash.
00620   * @retval None
00621   */
00622 //void LCD_DrawBMP(uint32_t BmpAddress)
00623 //{
00624 //  uint32_t i = 0, size = 0;
00625 //
00626 //  /* Read bitmap size */
00627 //  sFLASH_ReadBuffer((uint8_t*)&size, BmpAddress + 2, 4);
00628 //
00629 //  /* get bitmap data address offset */
00630 //  sFLASH_ReadBuffer((uint8_t*)&i, BmpAddress + 10, 4);
00631 //
00632 //  size = (size - i)/2;
00633 //
00634 //  sFLASH_StartReadSequence(BmpAddress + i);
00635 //
00636 //  /* Disable LCD_SPI  */
00637 //  SPI_Cmd(LCD_SPI, DISABLE);
00638 //  /* SPI in 16-bit mode */
00639 //  SPI_DataSizeConfig(LCD_SPI, SPI_DataSize_16b);
00640 //
00641 //  /* Enable LCD_SPI  */
00642 //  SPI_Cmd(LCD_SPI, ENABLE);
00643 //
00644 //  /* Set GRAM write direction and BGR = 1 */
00645 //  /* I/D=00 (Horizontal : decrement, Vertical : decrement) */
00646 //  /* AM=1 (address is updated in vertical writing direction) */
00647 //  LCD_WriteReg(LCD_REG_3, 0x1008);
00648 //
00649 //  LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
00650 //
00651 //  /* Read bitmap data from SPI Flash and send them to LCD */
00652 //  for(i = 0; i < size; i++)
00653 //  {
00654 //    LCD_WriteRAM(__REV_HalfWord(sFLASH_SendHalfWord(0xA5A5)));
00655 //  }
00656 //
00657 //  LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
00658 //
00659 //  /* Deselect the FLASH: Chip Select high */
00660 //  sFLASH_CS_HIGH();
00661 //
00662 //  /* Disable LCD_SPI  */
00663 //  SPI_Cmd(LCD_SPI, DISABLE);
00664 //  /* SPI in 8-bit mode */
00665 //  SPI_DataSizeConfig(LCD_SPI, SPI_DataSize_8b);
00666 //
00667 //  /* Enable LCD_SPI  */
00668 //  SPI_Cmd(LCD_SPI, ENABLE);
00669 //
00670 //  /* Set GRAM write direction and BGR = 1 */
00671 //  /* I/D = 01 (Horizontal : increment, Vertical : decrement) */
00672 //  /* AM = 1 (address is updated in vertical writing direction) */
00673 //  LCD_WriteReg(LCD_REG_3, 0x1018);
00674 //}
00675
00676
00677 /**
00678   * @brief  Displays a bitmap picture loaded in the Internal FLASH.
00679   * @param  BmpAddress: Bmp picture address in the Internal FLASH.
00680   * @retval None
00681   */
00682 void LCD_DrawBMP(const uint16_t *BmpAddress)
00683 {
00684   uint32_t i = 0, size = 0;
00685   /* Read bitmap size */
00686   size = BmpAddress[1] | (BmpAddress[2] << 16);
00687   /* get bitmap data address offset */
00688   i = BmpAddress[5] | (BmpAddress[6] << 16);
00689   size = (size - i)/2;
00690   BmpAddress += i/2;
00691   /* Set GRAM write direction and BGR = 1 */
00692   /* I/D=00 (Horizontal : decrement, Vertical : decrement) */
00693   /* AM=1 (address is updated in vertical writing direction) */
00694   LCD_WriteReg(LCD_REG_3, 0x1008);
00695   LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
00696   /* Read bitmap data from SPI Flash and send them to LCD */
00697   for(i = 0; i < size; i++)
00698   {
00699     LCD_WriteRAM(BmpAddress[i]);
00700   }
00701   LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
00702   /* Set GRAM write direction and BGR = 1 */
00703   /* I/D = 01 (Horizontal : increment, Vertical : decrement) */
00704   /* AM = 1 (address is updated in vertical writing direction) */
00705   LCD_WriteReg(LCD_REG_3, 0x1018);
00706 }
00707 #endif
00708
00709 /**
00710   * @brief  Displays a full rectangle.
00711   * @param  Xpos: specifies the X position.
00712   * @param  Ypos: specifies the Y position.
00713   * @param  Height: rectangle height.
00714   * @param  Width: rectangle width.
00715   * @retval None
00716   */
00717 void LCD_DrawFullRect(uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height)
00718 {
00719   LCD_SetTextColor(TextColor);
00720
00721   LCD_DrawLine(Xpos, Ypos, Width, LCD_DIR_HORIZONTAL);
00722   LCD_DrawLine((Xpos + Height), Ypos, Width, LCD_DIR_HORIZONTAL);
00723
00724   LCD_DrawLine(Xpos, Ypos, Height, LCD_DIR_VERTICAL);
00725   LCD_DrawLine(Xpos, (Ypos - Width + 1), Height, LCD_DIR_VERTICAL);
00726
00727   Width -= 2;
00728   Height--;
00729   Ypos--;
00730
00731   LCD_SetTextColor(BackColor);
00732
00733   while(Height--)
00734   {
00735     LCD_DrawLine(++Xpos, Ypos, Width, LCD_DIR_HORIZONTAL);
00736   }
00737
00738   LCD_SetTextColor(TextColor);
00739 }
00740
00741 /**
00742   * @brief  Displays a full circle.
00743   * @param  Xpos: specifies the X position.
00744   * @param  Ypos: specifies the Y position.
00745   * @param  Radius
00746   * @retval None
00747   */
00748 void LCD_DrawFullCircle(uint16_t Xpos, uint16_t Ypos, uint16_t Radius)
00749 {
00750   int32_t  D;    /* Decision Variable */
00751   uint32_t  CurX;/* Current X Value */
00752   uint32_t  CurY;/* Current Y Value */
00753
00754   D = 3 - (Radius << 1);
00755
00756   CurX = 0;
00757   CurY = Radius;
00758
00759   LCD_SetTextColor(BackColor);
00760
00761   while (CurX <= CurY)
00762   {
00763     if(CurY > 0)
00764     {
00765       LCD_DrawLine(Xpos - CurX, Ypos + CurY, 2*CurY, LCD_DIR_HORIZONTAL);
00766       LCD_DrawLine(Xpos + CurX, Ypos + CurY, 2*CurY, LCD_DIR_HORIZONTAL);
00767     }
00768
00769     if(CurX > 0)
00770     {
00771       LCD_DrawLine(Xpos - CurY, Ypos + CurX, 2*CurX, LCD_DIR_HORIZONTAL);
00772       LCD_DrawLine(Xpos + CurY, Ypos + CurX, 2*CurX, LCD_DIR_HORIZONTAL);
00773     }
00774     if (D < 0)
00775     {
00776       D += (CurX << 2) + 6;
00777     }
00778     else
00779     {
00780       D += ((CurX - CurY) << 2) + 10;
00781       CurY--;
00782     }
00783     CurX++;
00784   }
00785
00786   LCD_SetTextColor(TextColor);
00787   LCD_DrawCircle(Xpos, Ypos, Radius);
00788 }
00789
00790 /**
00791   * @brief  Displays an uni line (between two points).
00792   * @param  x1: specifies the point 1 x position.
00793   * @param  y1: specifies the point 1 y position.
00794   * @param  x2: specifies the point 2 x position.
00795   * @param  y2: specifies the point 2 y position.
00796   * @retval None
00797   */
00798 void LCD_DrawUniLine(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2)
00799 {
00800   int16_t deltax = 0, deltay = 0, x = 0, y = 0, xinc1 = 0, xinc2 = 0,
00801   yinc1 = 0, yinc2 = 0, den = 0, num = 0, numadd = 0, numpixels = 0,
00802   curpixel = 0;
00803
00804   deltax = ABS(x2 - x1);        /* The difference between the x's */
00805   deltay = ABS(y2 - y1);        /* The difference between the y's */
00806   x = x1;                       /* Start x off at the first pixel */
00807   y = y1;                       /* Start y off at the first pixel */
00808
00809   if (x2 >= x1)                 /* The x-values are increasing */
00810   {
00811     xinc1 = 1;
00812     xinc2 = 1;
00813   }
00814   else                          /* The x-values are decreasing */
00815   {
00816     xinc1 = -1;
00817     xinc2 = -1;
00818   }
00819
00820   if (y2 >= y1)                 /* The y-values are increasing */
00821   {
00822     yinc1 = 1;
00823     yinc2 = 1;
00824   }
00825   else                          /* The y-values are decreasing */
00826   {
00827     yinc1 = -1;
00828     yinc2 = -1;
00829   }
00830
00831   if (deltax >= deltay)         /* There is at least one x-value for every y-value */
00832   {
00833     xinc1 = 0;                  /* Don't change the x when numerator >= denominator */
00834     yinc2 = 0;                  /* Don't change the y for every iteration */
00835     den = deltax;
00836     num = deltax / 2;
00837     numadd = deltay;
00838     numpixels = deltax;         /* There are more x-values than y-values */
00839   }
00840   else                          /* There is at least one y-value for every x-value */
00841   {
00842     xinc2 = 0;                  /* Don't change the x for every iteration */
00843     yinc1 = 0;                  /* Don't change the y when numerator >= denominator */
00844     den = deltay;
00845     num = deltay / 2;
00846     numadd = deltax;
00847     numpixels = deltay;         /* There are more y-values than x-values */
00848   }
00849
00850   for (curpixel = 0; curpixel <= numpixels; curpixel++)
00851   {
00852     PutPixel(x, y);             /* Draw the current pixel */
00853     num += numadd;              /* Increase the numerator by the top of the fraction */
00854     if (num >= den)             /* Check if numerator >= denominator */
00855     {
00856       num -= den;               /* Calculate the new numerator value */
00857       x += xinc1;               /* Change the x as appropriate */
00858       y += yinc1;               /* Change the y as appropriate */
00859     }
00860     x += xinc2;                 /* Change the x as appropriate */
00861     y += yinc2;                 /* Change the y as appropriate */
00862   }
00863 }
00864
00865 /**
00866   * @brief  Displays an polyline (between many points).
00867   * @param  Points: pointer to the points array.
00868   * @param  PointCount: Number of points.
00869   * @retval None
00870   */
00871 void LCD_PolyLine(pPoint Points, uint16_t PointCount)
00872 {
00873   int16_t X = 0, Y = 0;
00874
00875   if(PointCount < 2)
00876   {
00877     return;
00878   }
00879
00880   while(--PointCount)
00881   {
00882     X = Points->X;
00883     Y = Points->Y;
00884     Points++;
00885     LCD_DrawUniLine(X, Y, Points->X, Points->Y);
00886   }
00887 }
00888
00889 /**
00890   * @brief  Displays an relative polyline (between many points).
00891   * @param  Points: pointer to the points array.
00892   * @param  PointCount: Number of points.
00893   * @param  Closed: specifies if the draw is closed or not.
00894   *           1: closed, 0 : not closed.
00895   * @retval None
00896   */
00897 static void LCD_PolyLineRelativeClosed(pPoint Points, uint16_t PointCount, uint16_t Closed)
00898 {
00899   int16_t X = 0, Y = 0;
00900   pPoint First = Points;
00901
00902   if(PointCount < 2)
00903   {
00904     return;
00905   }
00906   X = Points->X;
00907   Y = Points->Y;
00908   while(--PointCount)
00909   {
00910     Points++;
00911     LCD_DrawUniLine(X, Y, X + Points->X, Y + Points->Y);
00912     X = X + Points->X;
00913     Y = Y + Points->Y;
00914   }
00915   if(Closed)
00916   {
00917     LCD_DrawUniLine(First->X, First->Y, X, Y);
00918   }
00919 }
00920
00921 /**
00922   * @brief  Displays a closed polyline (between many points).
00923   * @param  Points: pointer to the points array.
00924   * @param  PointCount: Number of points.
00925   * @retval None
00926   */
00927 void LCD_ClosedPolyLine(pPoint Points, uint16_t PointCount)
00928 {
00929   LCD_PolyLine(Points, PointCount);
00930   LCD_DrawUniLine(Points->X, Points->Y, (Points+PointCount-1)->X, (Points+PointCount-1)->Y);
00931 }
00932
00933 /**
00934   * @brief  Displays a relative polyline (between many points).
00935   * @param  Points: pointer to the points array.
00936   * @param  PointCount: Number of points.
00937   * @retval None
00938   */
00939 void LCD_PolyLineRelative(pPoint Points, uint16_t PointCount)
00940 {
00941   LCD_PolyLineRelativeClosed(Points, PointCount, 0);
00942 }
00943
00944 /**
00945   * @brief  Displays a closed relative polyline (between many points).
00946   * @param  Points: pointer to the points array.
00947   * @param  PointCount: Number of points.
00948   * @retval None
00949   */
00950 void LCD_ClosedPolyLineRelative(pPoint Points, uint16_t PointCount)
00951 {
00952   LCD_PolyLineRelativeClosed(Points, PointCount, 1);
00953 }
00954
00955
00956 /**
00957   * @brief  Displays a  full polyline (between many points).
00958   * @param  Points: pointer to the points array.
00959   * @param  PointCount: Number of points.
00960   * @retval None
00961   */
00962 void LCD_FillPolyLine(pPoint Points, uint16_t PointCount)
00963 {
00964   /*  public-domain code by Darel Rex Finley, 2007 */
00965   uint16_t  nodes = 0, nodeX[MAX_POLY_CORNERS], pixelX = 0, pixelY = 0, i = 0,
00966   j = 0, swap = 0;
00967   uint16_t  IMAGE_LEFT = 0, IMAGE_RIGHT = 0, IMAGE_TOP = 0, IMAGE_BOTTOM = 0;
00968
00969   IMAGE_LEFT = IMAGE_RIGHT = Points->X;
00970   IMAGE_TOP= IMAGE_BOTTOM = Points->Y;
00971
00972   for(i = 1; i < PointCount; i++)
00973   {
00974     pixelX = POLY_X(i);
00975     if(pixelX < IMAGE_LEFT)
00976     {
00977       IMAGE_LEFT = pixelX;
00978     }
00979     if(pixelX > IMAGE_RIGHT)
00980     {
00981       IMAGE_RIGHT = pixelX;
00982     }
00983
00984     pixelY = POLY_Y(i);
00985     if(pixelY < IMAGE_TOP)
00986     {
00987       IMAGE_TOP = pixelY;
00988     }
00989     if(pixelY > IMAGE_BOTTOM)
00990     {
00991       IMAGE_BOTTOM = pixelY;
00992     }
00993   }
00994
00995   LCD_SetTextColor(BackColor);
00996
00997   /*  Loop through the rows of the image. */
00998   for (pixelY = IMAGE_TOP; pixelY < IMAGE_BOTTOM; pixelY++)
00999   {
01000     /* Build a list of nodes. */
01001     nodes = 0; j = PointCount-1;
01002
01003     for (i = 0; i < PointCount; i++)
01004     {
01005       if (POLY_Y(i)<(double) pixelY && POLY_Y(j)>=(double) pixelY || POLY_Y(j)<(double) pixelY && POLY_Y(i)>=(double) pixelY)
01006       {
01007         nodeX[nodes++]=(int) (POLY_X(i)+((pixelY-POLY_Y(i))*(POLY_X(j)-POLY_X(i)))/(POLY_Y(j)-POLY_Y(i)));
01008       }
01009       j = i;
01010     }
01011
01012     /* Sort the nodes, via a simple "Bubble" sort. */
01013     i = 0;
01014     while (i < nodes-1)
01015     {
01016       if (nodeX[i]>nodeX[i+1])
01017       {
01018         swap = nodeX[i];
01019         nodeX[i] = nodeX[i+1];
01020         nodeX[i+1] = swap;
01021         if(i)
01022         {
01023           i--;
01024         }
01025       }
01026       else
01027       {
01028         i++;
01029       }
01030     }
01031
01032     /*  Fill the pixels between node pairs. */
01033     for (i = 0; i < nodes; i+=2)
01034     {
01035       if(nodeX[i] >= IMAGE_RIGHT)
01036       {
01037         break;
01038       }
01039       if(nodeX[i+1] > IMAGE_LEFT)
01040       {
01041         if (nodeX[i] < IMAGE_LEFT)
01042         {
01043           nodeX[i]=IMAGE_LEFT;
01044         }
01045         if(nodeX[i+1] > IMAGE_RIGHT)
01046         {
01047           nodeX[i+1] = IMAGE_RIGHT;
01048         }
01049         LCD_SetTextColor(BackColor);
01050         LCD_DrawLine(pixelY, nodeX[i+1], nodeX[i+1] - nodeX[i], LCD_DIR_HORIZONTAL);
01051         LCD_SetTextColor(TextColor);
01052         PutPixel(pixelY, nodeX[i+1]);
01053         PutPixel(pixelY, nodeX[i]);
01054         /* for (j=nodeX[i]; j<nodeX[i+1]; j++) PutPixel(j,pixelY); */
01055       }
01056     }
01057   }
01058
01059   /* draw the edges */
01060   LCD_SetTextColor(TextColor);
01061 }
01062
01063 /**
01064   * @brief  Reset LCD control line(/CS) and Send Start-Byte
01065   * @param  Start_Byte: the Start-Byte to be sent
01066   * @retval None
01067   */
01068 void LCD_nCS_StartByte(uint8_t Start_Byte)
01069 {
01070   LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_RESET);
01071   SPI_I2S_SendData(LCD_SPI, Start_Byte);
01072   while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
01073   {
01074   }
01075 }
01076
01077 /**
01078   * @brief  Writes index to select the LCD register.
01079   * @param  LCD_Reg: address of the selected register.
01080   * @retval None
01081   */
01082 void LCD_WriteRegIndex(uint8_t LCD_Reg)
01083 {
01084   /* Reset LCD control line(/CS) and Send Start-Byte */
01085   LCD_nCS_StartByte(START_BYTE | SET_INDEX);
01086   /* Write 16-bit Reg Index (High Byte is 0) */
01087   SPI_I2S_SendData(LCD_SPI, 0x00);
01088   while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
01089   {
01090   }
01091   SPI_I2S_SendData(LCD_SPI, LCD_Reg);
01092   while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
01093   {
01094   }
01095   LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
01096 }
01097
01098
01099 /**
01100   * @brief  Reads the selected LCD Register.
01101   * @param  None
01102   * @retval LCD Register Value.
01103   */
01104 uint16_t LCD_ReadReg(uint8_t LCD_Reg)
01105 {
01106   uint16_t tmp = 0;
01107   uint8_t i = 0;
01108
01109   /* LCD_SPI prescaler: 4 */
01110   LCD_SPI->CR1 &= 0xFFC7;
01111   LCD_SPI->CR1 |= 0x0008;
01112   /* Write 16-bit Index (then Read Reg) */
01113   LCD_WriteRegIndex(LCD_Reg);
01114   /* Read 16-bit Reg */
01115   /* Reset LCD control line(/CS) and Send Start-Byte */
01116   LCD_nCS_StartByte(START_BYTE | LCD_READ_REG);
01117
01118   for(i = 0; i < 5; i++)
01119   {
01120     SPI_I2S_SendData(LCD_SPI, 0xFF);
01121     while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
01122     {
01123     }
01124     /* One byte of invalid dummy data read after the start byte */
01125     while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_RXNE) == RESET)
01126     {
01127     }
01128     SPI_I2S_ReceiveData(LCD_SPI);
01129   }
01130   SPI_I2S_SendData(LCD_SPI, 0xFF);
01131   /* Read upper byte */
01132   while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
01133   {
01134   }
01135   /* Read lower byte */
01136   while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_RXNE) == RESET)
01137   {
01138   }
01139   tmp = SPI_I2S_ReceiveData(LCD_SPI);
01140
01141
01142   SPI_I2S_SendData(LCD_SPI, 0xFF);
01143   while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
01144   {
01145   }
01146   /* Read lower byte */
01147   while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_RXNE) == RESET)
01148   {
01149   }
01150   tmp = ((tmp & 0xFF) << 8) | SPI_I2S_ReceiveData(LCD_SPI);
01151   LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
01152   /* LCD_SPI prescaler: 2 */
01153   LCD_SPI->CR1 &= 0xFFC7;
01154   return tmp;
01155 }
01156
01157
01158 /**
01159   * @brief  Prepare to write to the LCD RAM.
01160   * @param  None
01161   * @retval None
01162   */
01163 void LCD_WriteRAM_Prepare(void)
01164 {
01165   LCD_WriteRegIndex(LCD_REG_34); /* Select GRAM Reg */
01166   /* Reset LCD control line(/CS) and Send Start-Byte */
01167   LCD_nCS_StartByte(START_BYTE | LCD_WRITE_REG);
01168 }
01169
01170
01171 /**
01172   * @brief  Writes 1 word to the LCD RAM.
01173   * @param  RGB_Code: the pixel color in RGB mode (5-6-5).
01174   * @retval None
01175   */
01176 void LCD_WriteRAMWord(uint16_t RGB_Code)
01177 {
01178   LCD_WriteRAM_Prepare();
01179   LCD_WriteRAM(RGB_Code);
01180   LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
01181 }
01182
01183
01184 /**
01185   * @brief  Writes to the selected LCD register.
01186   * @param  LCD_Reg: address of the selected register.
01187   * @param  LCD_RegValue: value to write to the selected register.
01188   * @retval None
01189   */
01190 void LCD_WriteReg(uint8_t LCD_Reg, uint16_t LCD_RegValue)
01191 {
01192   /* Write 16-bit Index (then Write Reg) */
01193   LCD_WriteRegIndex(LCD_Reg);
01194   /* Write 16-bit Reg */
01195   /* Reset LCD control line(/CS) and Send Start-Byte */
01196   LCD_nCS_StartByte(START_BYTE | LCD_WRITE_REG);
01197   SPI_I2S_SendData(LCD_SPI, LCD_RegValue>>8);
01198   while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
01199   {
01200   }
01201   SPI_I2S_SendData(LCD_SPI, (LCD_RegValue & 0xFF));
01202   while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
01203   {
01204   }
01205   LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
01206 }
01207
01208
01209 /**
01210   * @brief  Writes to the LCD RAM.
01211   * @param  RGB_Code: the pixel color in RGB mode (5-6-5).
01212   * @retval None
01213   */
01214 void LCD_WriteRAM(uint16_t RGB_Code)
01215 {
01216   SPI_I2S_SendData(LCD_SPI, RGB_Code >> 8);
01217   while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
01218   {
01219   }
01220   SPI_I2S_SendData(LCD_SPI, RGB_Code & 0xFF);
01221   while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
01222   {
01223   }
01224 }
01225
01226
01227 /**
01228   * @brief  Power on the LCD.
01229   * @param  None
01230   * @retval None
01231   */
01232 void LCD_PowerOn(void)
01233 {
01234   /* Power On sequence ---------------------------------------------------------*/
01235   LCD_WriteReg(LCD_REG_16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
01236   LCD_WriteReg(LCD_REG_17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */
01237   LCD_WriteReg(LCD_REG_18, 0x0000); /* VREG1OUT voltage */
01238   LCD_WriteReg(LCD_REG_19, 0x0000); /* VDV[4:0] for VCOM amplitude */
01239   _delay_(20);                 /* Dis-charge capacitor power voltage (200ms) */
01240   LCD_WriteReg(LCD_REG_16, 0x17B0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
01241   LCD_WriteReg(LCD_REG_17, 0x0137); /* DC1[2:0], DC0[2:0], VC[2:0] */
01242   _delay_(5);                  /* Delay 50 ms */
01243   LCD_WriteReg(LCD_REG_18, 0x0139); /* VREG1OUT voltage */
01244   _delay_(5);                  /* delay 50 ms */
01245   LCD_WriteReg(LCD_REG_19, 0x1d00); /* VDV[4:0] for VCOM amplitude */
01246   LCD_WriteReg(LCD_REG_41, 0x0013); /* VCM[4:0] for VCOMH */
01247   _delay_(5);                  /* delay 50 ms */
01248   LCD_WriteReg(LCD_REG_7, 0x0173);  /* 262K color and display ON */
01249 }
01250
01251 /**
01252   * @brief  Enables the Display.
01253   * @param  None
01254   * @retval None
01255   */
01256 void LCD_DisplayOn(void)
01257 {
01258   /* Display On */
01259   LCD_WriteReg(LCD_REG_7, 0x0173); /* 262K color and display ON */
01260
01261 }
01262
01263 /**
01264   * @brief  Disables the Display.
01265   * @param  None
01266   * @retval None
01267   */
01268 void LCD_DisplayOff(void)
01269 {
01270   /* Display Off */
01271   LCD_WriteReg(LCD_REG_7, 0x0);
01272 }
01273
01274 /**
01275   * @brief  Configures LCD control lines in Output Push-Pull mode.
01276   * @param  None
01277   * @retval None
01278   */
01279 void LCD_CtrlLinesConfig(void)
01280 {
01281   GPIO_InitTypeDef GPIO_InitStructure;
01282
01283   /* Enable GPIO clock */
01284   RCC_APB2PeriphClockCmd(LCD_NCS_GPIO_CLK, ENABLE);
01285
01286   /* Configure NCS in Output Push-Pull mode */
01287   GPIO_InitStructure.GPIO_Pin = LCD_NCS_PIN;
01288   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
01289   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
01290   GPIO_Init(LCD_NCS_GPIO_PORT, &GPIO_InitStructure);
01291 }
01292
01293 /**
01294   * @brief  Sets or reset LCD control lines.
01295   * @param  GPIOx: where x can be B or D to select the GPIO peripheral.
01296   * @param  CtrlPins: the Control line. This parameter can be:
01297   *     @arg LCD_NCS_PIN: Chip Select pin
01298   * @param  BitVal: specifies the value to be written to the selected bit.
01299   *   This parameter can be:
01300   *     @arg Bit_RESET: to clear the port pin
01301   *     @arg Bit_SET: to set the port pin
01302   * @retval None
01303   */
01304 void LCD_CtrlLinesWrite(GPIO_TypeDef* GPIOx, uint16_t CtrlPins, BitAction BitVal)
01305 {
01306   /* Set or Reset the control line */
01307   GPIO_WriteBit(GPIOx, CtrlPins, BitVal);
01308 }
01309
01310
01311 /**
01312   * @brief  Configures the LCD_SPI interface.
01313   * @param  None
01314   * @retval None
01315   */
01316 void LCD_SPIConfig(void)
01317 {
01318   SPI_InitTypeDef    SPI_InitStructure;
01319   GPIO_InitTypeDef   GPIO_InitStructure;
01320
01321   /* Enable GPIO clock */
01322   RCC_APB2PeriphClockCmd(LCD_SPI_SCK_GPIO_CLK | LCD_SPI_MISO_GPIO_CLK | LCD_SPI_MOSI_GPIO_CLK
01323                          | RCC_APB2Periph_AFIO, ENABLE);
01324   GPIO_PinRemapConfig(GPIO_Remap_SPI3, ENABLE);
01325
01326   /* Enable SPI clock  */
01327   RCC_APB1PeriphClockCmd(LCD_SPI_CLK, ENABLE);
01328
01329   /* Configure SPI pins: SCK, MISO and MOSI */
01330   GPIO_InitStructure.GPIO_Pin = LCD_SPI_SCK_PIN;
01331   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
01332   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
01333   GPIO_Init(LCD_SPI_SCK_GPIO_PORT, &GPIO_InitStructure);
01334
01335   GPIO_InitStructure.GPIO_Pin = LCD_SPI_MISO_PIN;
01336   GPIO_Init(LCD_SPI_MISO_GPIO_PORT, &GPIO_InitStructure);
01337
01338   GPIO_InitStructure.GPIO_Pin = LCD_SPI_MOSI_PIN;
01339   GPIO_Init(LCD_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure);
01340
01341   SPI_I2S_DeInit(LCD_SPI);
01342
01343   /* SPI Config */
01344   SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
01345   SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
01346   SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
01347   SPI_InitStructure.SPI_CPOL = SPI_CPOL_High;
01348   SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge;
01349   SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
01350   SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
01351   SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
01352   SPI_Init(LCD_SPI, &SPI_InitStructure);
01353
01354   /* SPI enable */
01355   SPI_Cmd(LCD_SPI, ENABLE);
01356 }
01357
01358 /**
01359   * @brief  Displays a pixel.
01360   * @param  x: pixel x.
01361   * @param  y: pixel y.
01362   * @retval None
01363   */
01364 static void PutPixel(int16_t x, int16_t y)
01365 {
01366   if(x < 0 || x > 239 || y < 0 || y > 319)
01367   {
01368     return;
01369   }
01370   LCD_DrawLine(x, y, 1, LCD_DIR_HORIZONTAL);
01371 }
01372
01373 #ifndef USE_Delay
01374 /**
01375   * @brief  Inserts a delay time.
01376   * @param  nCount: specifies the delay time length.
01377   * @retval None
01378   */
01379 static void delay(__IO uint32_t nCount)
01380 {
01381   __IO uint32_t index = 0;
01382   for(index = (100000 * nCount); index != 0; index--)
01383   {
01384   }
01385 }
01386 #endif /* USE_Delay*/
01387 /**
01388   * @}
01389   */
01390
01391 /**
01392   * @}
01393   */
01394
01395 /**
01396   * @}
01397   */
01398
01399 /**
01400   * @}
01401   */
01402
01403 /**
01404   * @}
01405   */
01406
01407 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm3210c_eval_lcd.h Source File

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stm3210c_eval_lcd.h

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00001 /**
00002   ******************************************************************************
00003   * @file    stm3210c_eval_lcd.h
00004   * @author  MCD Application Team
00005   * @version V4.5.0
00006   * @date    07-March-2011
00007   * @brief   This file contains all the functions prototypes for the lcd firmware driver.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __STM3210C_EVAL_LCD_H
00024 #define __STM3210C_EVAL_LCD_H
00025
00026 #ifdef __cplusplus
00027  extern "C" {
00028 #endif
00029
00030 /* Includes ------------------------------------------------------------------*/
00031 #include "stm32f10x.h"
00032 #include "../Common/fonts.h"
00033
00034 /** @addtogroup Utilities
00035   * @{
00036   */
00037
00038 /** @addtogroup STM32_EVAL
00039   * @{
00040   */
00041
00042 /** @addtogroup STM3210C_EVAL
00043   * @{
00044   */
00045
00046 /** @addtogroup STM3210C_EVAL_LCD
00047   * @{
00048   */
00049
00050
00051 /** @defgroup STM3210C_EVAL_LCD_Exported_Types
00052   * @{
00053   */
00054 typedef struct
00055 {
00056   int16_t X;
00057   int16_t Y;
00058 } Point, * pPoint;
00059 /**
00060   * @}
00061   */
00062
00063 /** @defgroup STM3210C_EVAL_LCD_Exported_Constants
00064   * @{
00065   */
00066
00067 /**
00068  * @brief Uncomment the line below if you want to use LCD_DrawBMP function to
00069  *        display a bitmap picture on the LCD. This function assumes that the bitmap
00070  *        file is loaded in the SPI Flash (mounted on STM3210C-EVAL board), however
00071  *        user can tailor it according to his application hardware requirement.
00072  */
00073 /*#define USE_LCD_DrawBMP*/
00074
00075 /**
00076  * @brief Uncomment the line below if you want to use user defined Delay function
00077  *        (for precise timing), otherwise default _delay_ function defined within
00078  *         this driver is used (less precise timing).
00079  */
00080 /* #define USE_Delay */
00081
00082 #ifdef USE_Delay
00083 #include "main.h"
00084
00085   #define _delay_     Delay  /* !< User can provide more timing precise _delay_ function
00086                                    (with 10ms time base), using SysTick for example */
00087 #else
00088   #define _delay_     delay      /* !< Default _delay_ function with less precise timing */
00089 #endif
00090
00091 /**
00092   * @brief  LCD Control pins
00093   */
00094 #define LCD_NCS_PIN             GPIO_Pin_2
00095 #define LCD_NCS_GPIO_PORT       GPIOB
00096 #define LCD_NCS_GPIO_CLK        RCC_APB2Periph_GPIOB
00097
00098 /**
00099   * @brief  LCD SPI Interface pins
00100   */
00101 #define LCD_SPI                             SPI3
00102 #define LCD_SPI_CLK                       RCC_APB1Periph_SPI3
00103 #define LCD_SPI_SCK_PIN         GPIO_Pin_10
00104 #define LCD_SPI_SCK_GPIO_PORT   GPIOC
00105 #define LCD_SPI_SCK_GPIO_CLK    RCC_APB2Periph_GPIOC
00106 #define LCD_SPI_MISO_PIN        GPIO_Pin_11
00107 #define LCD_SPI_MISO_GPIO_PORT  GPIOC
00108 #define LCD_SPI_MISO_GPIO_CLK   RCC_APB2Periph_GPIOC
00109 #define LCD_SPI_MOSI_PIN        GPIO_Pin_12
00110 #define LCD_SPI_MOSI_GPIO_PORT  GPIOC
00111 #define LCD_SPI_MOSI_GPIO_CLK   RCC_APB2Periph_GPIOC
00112
00113 /**
00114   * @brief  LCD Registers
00115   */
00116 #define LCD_REG_0             0x00
00117 #define LCD_REG_1             0x01
00118 #define LCD_REG_2             0x02
00119 #define LCD_REG_3             0x03
00120 #define LCD_REG_4             0x04
00121 #define LCD_REG_5             0x05
00122 #define LCD_REG_6             0x06
00123 #define LCD_REG_7             0x07
00124 #define LCD_REG_8             0x08
00125 #define LCD_REG_9             0x09
00126 #define LCD_REG_10            0x0A
00127 #define LCD_REG_12            0x0C
00128 #define LCD_REG_13            0x0D
00129 #define LCD_REG_14            0x0E
00130 #define LCD_REG_15            0x0F
00131 #define LCD_REG_16            0x10
00132 #define LCD_REG_17            0x11
00133 #define LCD_REG_18            0x12
00134 #define LCD_REG_19            0x13
00135 #define LCD_REG_20            0x14
00136 #define LCD_REG_21            0x15
00137 #define LCD_REG_22            0x16
00138 #define LCD_REG_23            0x17
00139 #define LCD_REG_24            0x18
00140 #define LCD_REG_25            0x19
00141 #define LCD_REG_26            0x1A
00142 #define LCD_REG_27            0x1B
00143 #define LCD_REG_28            0x1C
00144 #define LCD_REG_29            0x1D
00145 #define LCD_REG_30            0x1E
00146 #define LCD_REG_31            0x1F
00147 #define LCD_REG_32            0x20
00148 #define LCD_REG_33            0x21
00149 #define LCD_REG_34            0x22
00150 #define LCD_REG_36            0x24
00151 #define LCD_REG_37            0x25
00152 #define LCD_REG_40            0x28
00153 #define LCD_REG_41            0x29
00154 #define LCD_REG_43            0x2B
00155 #define LCD_REG_45            0x2D
00156 #define LCD_REG_48            0x30
00157 #define LCD_REG_49            0x31
00158 #define LCD_REG_50            0x32
00159 #define LCD_REG_51            0x33
00160 #define LCD_REG_52            0x34
00161 #define LCD_REG_53            0x35
00162 #define LCD_REG_54            0x36
00163 #define LCD_REG_55            0x37
00164 #define LCD_REG_56            0x38
00165 #define LCD_REG_57            0x39
00166 #define LCD_REG_59            0x3B
00167 #define LCD_REG_60            0x3C
00168 #define LCD_REG_61            0x3D
00169 #define LCD_REG_62            0x3E
00170 #define LCD_REG_63            0x3F
00171 #define LCD_REG_64            0x40
00172 #define LCD_REG_65            0x41
00173 #define LCD_REG_66            0x42
00174 #define LCD_REG_67            0x43
00175 #define LCD_REG_68            0x44
00176 #define LCD_REG_69            0x45
00177 #define LCD_REG_70            0x46
00178 #define LCD_REG_71            0x47
00179 #define LCD_REG_72            0x48
00180 #define LCD_REG_73            0x49
00181 #define LCD_REG_74            0x4A
00182 #define LCD_REG_75            0x4B
00183 #define LCD_REG_76            0x4C
00184 #define LCD_REG_77            0x4D
00185 #define LCD_REG_78            0x4E
00186 #define LCD_REG_79            0x4F
00187 #define LCD_REG_80            0x50
00188 #define LCD_REG_81            0x51
00189 #define LCD_REG_82            0x52
00190 #define LCD_REG_83            0x53
00191 #define LCD_REG_96            0x60
00192 #define LCD_REG_97            0x61
00193 #define LCD_REG_106           0x6A
00194 #define LCD_REG_118           0x76
00195 #define LCD_REG_128           0x80
00196 #define LCD_REG_129           0x81
00197 #define LCD_REG_130           0x82
00198 #define LCD_REG_131           0x83
00199 #define LCD_REG_132           0x84
00200 #define LCD_REG_133           0x85
00201 #define LCD_REG_134           0x86
00202 #define LCD_REG_135           0x87
00203 #define LCD_REG_136           0x88
00204 #define LCD_REG_137           0x89
00205 #define LCD_REG_139           0x8B
00206 #define LCD_REG_140           0x8C
00207 #define LCD_REG_141           0x8D
00208 #define LCD_REG_143           0x8F
00209 #define LCD_REG_144           0x90
00210 #define LCD_REG_145           0x91
00211 #define LCD_REG_146           0x92
00212 #define LCD_REG_147           0x93
00213 #define LCD_REG_148           0x94
00214 #define LCD_REG_149           0x95
00215 #define LCD_REG_150           0x96
00216 #define LCD_REG_151           0x97
00217 #define LCD_REG_152           0x98
00218 #define LCD_REG_153           0x99
00219 #define LCD_REG_154           0x9A
00220 #define LCD_REG_157           0x9D
00221 #define LCD_REG_192           0xC0
00222 #define LCD_REG_193           0xC1
00223 #define LCD_REG_229           0xE5
00224
00225 /**
00226   * @brief  LCD color
00227   */
00228 #define LCD_COLOR_WHITE          0xFFFF
00229 #define LCD_COLOR_BLACK          0x0000
00230 #define LCD_COLOR_GREY           0xF7DE
00231 #define LCD_COLOR_BLUE           0x001F
00232 #define LCD_COLOR_BLUE2          0x051F
00233 #define LCD_COLOR_RED            0xF800
00234 #define LCD_COLOR_MAGENTA        0xF81F
00235 #define LCD_COLOR_GREEN          0x07E0
00236 #define LCD_COLOR_CYAN           0x7FFF
00237 #define LCD_COLOR_YELLOW         0xFFE0
00238
00239 /**
00240   * @brief  LCD Lines depending on the chosen fonts.
00241   */
00242 #define LCD_LINE_0               LINE(0)
00243 #define LCD_LINE_1               LINE(1)
00244 #define LCD_LINE_2               LINE(2)
00245 #define LCD_LINE_3               LINE(3)
00246 #define LCD_LINE_4               LINE(4)
00247 #define LCD_LINE_5               LINE(5)
00248 #define LCD_LINE_6               LINE(6)
00249 #define LCD_LINE_7               LINE(7)
00250 #define LCD_LINE_8               LINE(8)
00251 #define LCD_LINE_9               LINE(9)
00252 #define LCD_LINE_10              LINE(10)
00253 #define LCD_LINE_11              LINE(11)
00254 #define LCD_LINE_12              LINE(12)
00255 #define LCD_LINE_13              LINE(13)
00256 #define LCD_LINE_14              LINE(14)
00257 #define LCD_LINE_15              LINE(15)
00258 #define LCD_LINE_16              LINE(16)
00259 #define LCD_LINE_17              LINE(17)
00260 #define LCD_LINE_18              LINE(18)
00261 #define LCD_LINE_19              LINE(19)
00262 #define LCD_LINE_20              LINE(20)
00263 #define LCD_LINE_21              LINE(21)
00264 #define LCD_LINE_22              LINE(22)
00265 #define LCD_LINE_23              LINE(23)
00266 #define LCD_LINE_24              LINE(24)
00267 #define LCD_LINE_25              LINE(25)
00268 #define LCD_LINE_26              LINE(26)
00269 #define LCD_LINE_27              LINE(27)
00270 #define LCD_LINE_28              LINE(28)
00271 #define LCD_LINE_29              LINE(29)
00272
00273 /**
00274   * @brief LCD default font
00275   */
00276 #define LCD_DEFAULT_FONT         Font16x24
00277
00278 /**
00279   * @brief  LCD Direction
00280   */
00281 #define LCD_DIR_HORIZONTAL       0x0000
00282 #define LCD_DIR_VERTICAL         0x0001
00283
00284 /**
00285   * @brief  LCD Size (Width and Height)
00286   */
00287 #define LCD_PIXEL_WIDTH          0x0140
00288 #define LCD_PIXEL_HEIGHT         0x00F0
00289
00290 /**
00291   * @}
00292   */
00293
00294 /** @defgroup STM3210C_EVAL_LCD_Exported_Macros
00295   * @{
00296   */
00297 #define ASSEMBLE_RGB(R, G, B)    ((((R)& 0xF8) << 8) | (((G) & 0xFC) << 3) | (((B) & 0xF8) >> 3))
00298 /**
00299   * @}
00300   */
00301
00302 /** @defgroup STM3210C_EVAL_LCD_Exported_Functions
00303   * @{
00304   */
00305 void LCD_DeInit(void);
00306 void LCD_Setup(void);
00307 void STM3210C_LCD_Init(void);
00308 void LCD_SetColors(__IO uint16_t _TextColor, __IO uint16_t _BackColor);
00309 void LCD_GetColors(__IO uint16_t *_TextColor, __IO uint16_t *_BackColor);
00310 void LCD_SetTextColor(__IO uint16_t Color);
00311 void LCD_SetBackColor(__IO uint16_t Color);
00312 void LCD_ClearLine(uint8_t Line);
00313 void LCD_Clear(uint16_t Color);
00314 void LCD_SetCursor(uint8_t Xpos, uint16_t Ypos);
00315 void LCD_DrawChar(uint8_t Xpos, uint16_t Ypos, const uint16_t *c);
00316 void LCD_DisplayChar(uint8_t Line, uint16_t Column, uint8_t Ascii);
00317 void LCD_SetFont(sFONT *fonts);
00318 sFONT *LCD_GetFont(void);
00319 void LCD_DisplayStringLine(uint8_t Line, uint8_t *ptr);
00320 void LCD_SetDisplayWindow(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width);
00321 void LCD_WindowModeDisable(void);
00322 void LCD_DrawLine(uint8_t Xpos, uint16_t Ypos, uint16_t Length, uint8_t Direction);
00323 void LCD_DrawRect(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width);
00324 void LCD_DrawCircle(uint8_t Xpos, uint16_t Ypos, uint16_t Radius);
00325 void LCD_DrawMonoPict(const uint32_t *Pict);
00326 #ifdef USE_LCD_DrawBMP
00327 //void LCD_DrawBMP(uint32_t BmpAddress);
00328 void LCD_DrawBMP(const uint16_t *BmpAddress);
00329 #endif
00330 void LCD_DrawUniLine(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2);
00331 void LCD_DrawFullRect(uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height);
00332 void LCD_DrawFullCircle(uint16_t Xpos, uint16_t Ypos, uint16_t Radius);
00333 void LCD_PolyLine(pPoint Points, uint16_t PointCount);
00334 void LCD_PolyLineRelative(pPoint Points, uint16_t PointCount);
00335 void LCD_ClosedPolyLine(pPoint Points, uint16_t PointCount);
00336 void LCD_ClosedPolyLineRelative(pPoint Points, uint16_t PointCount);
00337 void LCD_FillPolyLine(pPoint Points, uint16_t PointCount);
00338
00339 void LCD_nCS_StartByte(uint8_t Start_Byte);
00340 void LCD_WriteRegIndex(uint8_t LCD_Reg);
00341 void LCD_WriteReg(uint8_t LCD_Reg, uint16_t LCD_RegValue);
00342 void LCD_WriteRAM_Prepare(void);
00343 void LCD_WriteRAMWord(uint16_t RGB_Code);
00344 uint16_t LCD_ReadReg(uint8_t LCD_Reg);
00345 void LCD_WriteRAM(uint16_t RGB_Code);
00346 void LCD_PowerOn(void);
00347 void LCD_DisplayOn(void);
00348 void LCD_DisplayOff(void);
00349
00350 void LCD_CtrlLinesConfig(void);
00351 void LCD_CtrlLinesWrite(GPIO_TypeDef* GPIOx, uint16_t CtrlPins, BitAction BitVal);
00352 void LCD_SPIConfig(void);
00353
00354 #ifdef __cplusplus
00355 }
00356 #endif
00357
00358 #endif /* __STM3210C_EVAL_LCD_H */
00359 /**
00360   * @}
00361   */
00362
00363 /**
00364   * @}
00365   */
00366
00367 /**
00368   * @}
00369   */
00370
00371 /**
00372   * @}
00373   */
00374
00375 /**
00376   * @}
00377   */
00378
00379 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm3210e_eval.c Source File

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  • Utilities
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  • STM3210E_EVAL

stm3210e_eval.c

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00001 /**
00002   ******************************************************************************
00003   * @file    stm3210e_eval.c
00004   * @author  MCD Application Team
00005   * @version V4.5.0
00006   * @date    07-March-2011
00007   * @brief   This file provides
00008   *            - set of firmware functions to manage Leds, push-button and COM ports
00009   *            - low level initialization functions for SD card (on SDIO), SPI serial
00010   *              flash (sFLASH) and temperature sensor (LM75)
00011   *          available on STM3210E-EVAL evaluation board from STMicroelectronics.
00012   ******************************************************************************
00013   * @attention
00014   *
00015   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00016   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00017   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00018   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00019   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00020   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00021   *
00022   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00023   ******************************************************************************
00024   */
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm3210e_eval.h"
00028 #include "stm32f10x_spi.h"
00029 #include "stm32f10x_i2c.h"
00030 #include "stm32f10x_sdio.h"
00031 #include "stm32f10x_dma.h"
00032
00033 /** @addtogroup Utilities
00034   * @{
00035   */
00036
00037 /** @addtogroup STM32_EVAL
00038   * @{
00039   */
00040
00041 /** @addtogroup STM3210E_EVAL
00042   * @{
00043   */
00044
00045 /** @defgroup STM3210E_EVAL_LOW_LEVEL
00046   * @brief This file provides firmware functions to manage Leds, push-buttons,
00047   *        COM ports, SD card on SDIO, serial flash (sFLASH), serial EEPROM (sEE)
00048   *        and temperature sensor (LM75) available on STM3210E-EVAL evaluation
00049   *        board from STMicroelectronics.
00050   * @{
00051   */
00052
00053 /** @defgroup STM3210E_EVAL_LOW_LEVEL_Private_TypesDefinitions
00054   * @{
00055   */
00056 /**
00057   * @}
00058   */
00059
00060
00061 /** @defgroup STM3210E_EVAL_LOW_LEVEL_Private_Defines
00062   * @{
00063   */
00064 /**
00065   * @}
00066   */
00067
00068
00069 /** @defgroup STM3210E_EVAL_LOW_LEVEL_Private_Macros
00070   * @{
00071   */
00072 /**
00073   * @}
00074   */
00075
00076
00077 /** @defgroup STM3210E_EVAL_LOW_LEVEL_Private_Variables
00078   * @{
00079   */
00080 GPIO_TypeDef* GPIO_PORT[LEDn] = {LED1_GPIO_PORT, LED2_GPIO_PORT, LED3_GPIO_PORT,
00081                                  LED4_GPIO_PORT};
00082 const uint16_t GPIO_PIN[LEDn] = {LED1_PIN, LED2_PIN, LED3_PIN,
00083                                  LED4_PIN};
00084 const uint32_t GPIO_CLK[LEDn] = {LED1_GPIO_CLK, LED2_GPIO_CLK, LED3_GPIO_CLK,
00085                                  LED4_GPIO_CLK};
00086
00087 GPIO_TypeDef* BUTTON_PORT[BUTTONn] = {WAKEUP_BUTTON_GPIO_PORT, TAMPER_BUTTON_GPIO_PORT,
00088                                       KEY_BUTTON_GPIO_PORT, RIGHT_BUTTON_GPIO_PORT,
00089                                       LEFT_BUTTON_GPIO_PORT, UP_BUTTON_GPIO_PORT,
00090                                       DOWN_BUTTON_GPIO_PORT, SEL_BUTTON_GPIO_PORT};
00091
00092 const uint16_t BUTTON_PIN[BUTTONn] = {WAKEUP_BUTTON_PIN, TAMPER_BUTTON_PIN,
00093                                       KEY_BUTTON_PIN, RIGHT_BUTTON_PIN,
00094                                       LEFT_BUTTON_PIN, UP_BUTTON_PIN,
00095                                       DOWN_BUTTON_PIN, SEL_BUTTON_PIN};
00096
00097 const uint32_t BUTTON_CLK[BUTTONn] = {WAKEUP_BUTTON_GPIO_CLK, TAMPER_BUTTON_GPIO_CLK,
00098                                       KEY_BUTTON_GPIO_CLK, RIGHT_BUTTON_GPIO_CLK,
00099                                       LEFT_BUTTON_GPIO_CLK, UP_BUTTON_GPIO_CLK,
00100                                       DOWN_BUTTON_GPIO_CLK, SEL_BUTTON_GPIO_CLK};
00101
00102 const uint16_t BUTTON_EXTI_LINE[BUTTONn] = {WAKEUP_BUTTON_EXTI_LINE,
00103                                             TAMPER_BUTTON_EXTI_LINE,
00104                                             KEY_BUTTON_EXTI_LINE,
00105                                             RIGHT_BUTTON_EXTI_LINE,
00106                                             LEFT_BUTTON_EXTI_LINE,
00107                                             UP_BUTTON_EXTI_LINE,
00108                                             DOWN_BUTTON_EXTI_LINE,
00109                                             SEL_BUTTON_EXTI_LINE};
00110
00111 const uint16_t BUTTON_PORT_SOURCE[BUTTONn] = {WAKEUP_BUTTON_EXTI_PORT_SOURCE,
00112                                               TAMPER_BUTTON_EXTI_PORT_SOURCE,
00113                                               KEY_BUTTON_EXTI_PORT_SOURCE,
00114                                               RIGHT_BUTTON_EXTI_PORT_SOURCE,
00115                                               LEFT_BUTTON_EXTI_PORT_SOURCE,
00116                                               UP_BUTTON_EXTI_PORT_SOURCE,
00117                                               DOWN_BUTTON_EXTI_PORT_SOURCE,
00118                                               SEL_BUTTON_EXTI_PORT_SOURCE};
00119
00120 const uint16_t BUTTON_PIN_SOURCE[BUTTONn] = {WAKEUP_BUTTON_EXTI_PIN_SOURCE,
00121                                              TAMPER_BUTTON_EXTI_PIN_SOURCE,
00122                                              KEY_BUTTON_EXTI_PIN_SOURCE,
00123                                              RIGHT_BUTTON_EXTI_PIN_SOURCE,
00124                                              LEFT_BUTTON_EXTI_PIN_SOURCE,
00125                                              UP_BUTTON_EXTI_PIN_SOURCE,
00126                                              DOWN_BUTTON_EXTI_PIN_SOURCE,
00127                                              SEL_BUTTON_EXTI_PIN_SOURCE};
00128
00129 const uint16_t BUTTON_IRQn[BUTTONn] = {WAKEUP_BUTTON_EXTI_IRQn, TAMPER_BUTTON_EXTI_IRQn,
00130                                        KEY_BUTTON_EXTI_IRQn, RIGHT_BUTTON_EXTI_IRQn,
00131                                        LEFT_BUTTON_EXTI_IRQn, UP_BUTTON_EXTI_IRQn,
00132                                        DOWN_BUTTON_EXTI_IRQn, SEL_BUTTON_EXTI_IRQn};
00133
00134 USART_TypeDef* COM_USART[COMn] = {EVAL_COM1, EVAL_COM2};
00135
00136 GPIO_TypeDef* COM_TX_PORT[COMn] = {EVAL_COM1_TX_GPIO_PORT, EVAL_COM2_TX_GPIO_PORT};
00137
00138 GPIO_TypeDef* COM_RX_PORT[COMn] = {EVAL_COM1_RX_GPIO_PORT, EVAL_COM2_RX_GPIO_PORT};
00139
00140 const uint32_t COM_USART_CLK[COMn] = {EVAL_COM1_CLK, EVAL_COM2_CLK};
00141
00142 const uint32_t COM_TX_PORT_CLK[COMn] = {EVAL_COM1_TX_GPIO_CLK, EVAL_COM2_TX_GPIO_CLK};
00143
00144 const uint32_t COM_RX_PORT_CLK[COMn] = {EVAL_COM1_RX_GPIO_CLK, EVAL_COM2_RX_GPIO_CLK};
00145
00146 const uint16_t COM_TX_PIN[COMn] = {EVAL_COM1_TX_PIN, EVAL_COM2_TX_PIN};
00147
00148 const uint16_t COM_RX_PIN[COMn] = {EVAL_COM1_RX_PIN, EVAL_COM2_RX_PIN};
00149
00150 /**
00151   * @}
00152   */
00153
00154
00155 /** @defgroup STM3210E_EVAL_LOW_LEVEL_Private_FunctionPrototypes
00156   * @{
00157   */
00158
00159 /**
00160   * @}
00161   */
00162
00163
00164 /** @defgroup STM3210E_EVAL_LOW_LEVEL_Private_Functions
00165   * @{
00166   */
00167
00168 /**
00169   * @brief  Configures LED GPIO.
00170   * @param  Led: Specifies the Led to be configured.
00171   *   This parameter can be one of following parameters:
00172   *     @arg LED1
00173   *     @arg LED2
00174   *     @arg LED3
00175   *     @arg LED4
00176   * @retval None
00177   */
00178 void STM_EVAL_LEDInit(Led_TypeDef Led)
00179 {
00180   GPIO_InitTypeDef  GPIO_InitStructure;
00181
00182   /* Enable the GPIO_LED Clock */
00183   RCC_APB2PeriphClockCmd(GPIO_CLK[Led], ENABLE);
00184
00185   /* Configure the GPIO_LED pin */
00186   GPIO_InitStructure.GPIO_Pin = GPIO_PIN[Led];
00187   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
00188   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00189
00190   GPIO_Init(GPIO_PORT[Led], &GPIO_InitStructure);
00191 }
00192
00193 /**
00194   * @brief  Turns selected LED On.
00195   * @param  Led: Specifies the Led to be set on.
00196   *   This parameter can be one of following parameters:
00197   *     @arg LED1
00198   *     @arg LED2
00199   *     @arg LED3
00200   *     @arg LED4
00201   * @retval None
00202   */
00203 void STM_EVAL_LEDOn(Led_TypeDef Led)
00204 {
00205   GPIO_PORT[Led]->BSRR = GPIO_PIN[Led];
00206 }
00207
00208 /**
00209   * @brief  Turns selected LED Off.
00210   * @param  Led: Specifies the Led to be set off.
00211   *   This parameter can be one of following parameters:
00212   *     @arg LED1
00213   *     @arg LED2
00214   *     @arg LED3
00215   *     @arg LED4
00216   * @retval None
00217   */
00218 void STM_EVAL_LEDOff(Led_TypeDef Led)
00219 {
00220   GPIO_PORT[Led]->BRR = GPIO_PIN[Led];
00221 }
00222
00223 /**
00224   * @brief  Toggles the selected LED.
00225   * @param  Led: Specifies the Led to be toggled.
00226   *   This parameter can be one of following parameters:
00227   *     @arg LED1
00228   *     @arg LED2
00229   *     @arg LED3
00230   *     @arg LED4
00231   * @retval None
00232   */
00233 void STM_EVAL_LEDToggle(Led_TypeDef Led)
00234 {
00235   GPIO_PORT[Led]->ODR ^= GPIO_PIN[Led];
00236 }
00237
00238 /**
00239   * @brief  Configures Button GPIO and EXTI Line.
00240   * @param  Button: Specifies the Button to be configured.
00241   *   This parameter can be one of following parameters:
00242   *     @arg BUTTON_WAKEUP: Wakeup Push Button
00243   *     @arg BUTTON_TAMPER: Tamper Push Button
00244   *     @arg BUTTON_KEY: Key Push Button
00245   *     @arg BUTTON_RIGHT: Joystick Right Push Button
00246   *     @arg BUTTON_LEFT: Joystick Left Push Button
00247   *     @arg BUTTON_UP: Joystick Up Push Button
00248   *     @arg BUTTON_DOWN: Joystick Down Push Button
00249   *     @arg BUTTON_SEL: Joystick Sel Push Button
00250   * @param  Button_Mode: Specifies Button mode.
00251   *   This parameter can be one of following parameters:
00252   *     @arg BUTTON_MODE_GPIO: Button will be used as simple IO
00253   *     @arg BUTTON_MODE_EXTI: Button will be connected to EXTI line with interrupt
00254   *                     generation capability
00255   * @retval None
00256   */
00257 void STM_EVAL_PBInit(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode)
00258 {
00259   GPIO_InitTypeDef GPIO_InitStructure;
00260   EXTI_InitTypeDef EXTI_InitStructure;
00261   NVIC_InitTypeDef NVIC_InitStructure;
00262
00263   /* Enable the BUTTON Clock */
00264   RCC_APB2PeriphClockCmd(BUTTON_CLK[Button] | RCC_APB2Periph_AFIO, ENABLE);
00265
00266   /* Configure Button pin as input floating */
00267   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
00268   GPIO_InitStructure.GPIO_Pin = BUTTON_PIN[Button];
00269   GPIO_Init(BUTTON_PORT[Button], &GPIO_InitStructure);
00270
00271
00272   if (Button_Mode == BUTTON_MODE_EXTI)
00273   {
00274     /* Connect Button EXTI Line to Button GPIO Pin */
00275     GPIO_EXTILineConfig(BUTTON_PORT_SOURCE[Button], BUTTON_PIN_SOURCE[Button]);
00276
00277     /* Configure Button EXTI line */
00278     EXTI_InitStructure.EXTI_Line = BUTTON_EXTI_LINE[Button];
00279     EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
00280
00281     if(Button != BUTTON_WAKEUP)
00282     {
00283       EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling;
00284     }
00285     else
00286     {
00287       EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;
00288     }
00289     EXTI_InitStructure.EXTI_LineCmd = ENABLE;
00290     EXTI_Init(&EXTI_InitStructure);
00291
00292     /* Enable and set Button EXTI Interrupt to the lowest priority */
00293     NVIC_InitStructure.NVIC_IRQChannel = BUTTON_IRQn[Button];
00294     NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x0F;
00295     NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x0F;
00296     NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
00297
00298     NVIC_Init(&NVIC_InitStructure);
00299   }
00300 }
00301
00302 /**
00303   * @brief  Returns the selected Button state.
00304   * @param  Button: Specifies the Button to be checked.
00305   *   This parameter can be one of following parameters:
00306   *     @arg BUTTON_WAKEUP: Wakeup Push Button
00307   *     @arg BUTTON_TAMPER: Tamper Push Button
00308   *     @arg BUTTON_KEY: Key Push Button
00309   *     @arg BUTTON_RIGHT: Joystick Right Push Button
00310   *     @arg BUTTON_LEFT: Joystick Left Push Button
00311   *     @arg BUTTON_UP: Joystick Up Push Button
00312   *     @arg BUTTON_DOWN: Joystick Down Push Button
00313   *     @arg BUTTON_SEL: Joystick Sel Push Button
00314   * @retval The Button GPIO pin value.
00315   */
00316 uint32_t STM_EVAL_PBGetState(Button_TypeDef Button)
00317 {
00318   return GPIO_ReadInputDataBit(BUTTON_PORT[Button], BUTTON_PIN[Button]);
00319 }
00320
00321 /**
00322   * @brief  Configures COM port.
00323   * @param  COM: Specifies the COM port to be configured.
00324   *   This parameter can be one of following parameters:
00325   *     @arg COM1
00326   *     @arg COM2
00327   * @param  USART_InitStruct: pointer to a USART_InitTypeDef structure that
00328   *   contains the configuration information for the specified USART peripheral.
00329   * @retval None
00330   */
00331 void STM_EVAL_COMInit(COM_TypeDef COM, USART_InitTypeDef* USART_InitStruct)
00332 {
00333   GPIO_InitTypeDef GPIO_InitStructure;
00334
00335   /* Enable GPIO clock */
00336   RCC_APB2PeriphClockCmd(COM_TX_PORT_CLK[COM] | COM_RX_PORT_CLK[COM] | RCC_APB2Periph_AFIO, ENABLE);
00337
00338   /* Enable UART clock */
00339   if (COM == COM1)
00340   {
00341     RCC_APB2PeriphClockCmd(COM_USART_CLK[COM], ENABLE);
00342   }
00343   else
00344   {
00345     RCC_APB1PeriphClockCmd(COM_USART_CLK[COM], ENABLE);
00346   }
00347
00348   /* Configure USART Tx as alternate function push-pull */
00349   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
00350   GPIO_InitStructure.GPIO_Pin = COM_TX_PIN[COM];
00351   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00352   GPIO_Init(COM_TX_PORT[COM], &GPIO_InitStructure);
00353
00354   /* Configure USART Rx as input floating */
00355   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
00356   GPIO_InitStructure.GPIO_Pin = COM_RX_PIN[COM];
00357   GPIO_Init(COM_RX_PORT[COM], &GPIO_InitStructure);
00358
00359   /* USART configuration */
00360   USART_Init(COM_USART[COM], USART_InitStruct);
00361
00362   /* Enable USART */
00363   USART_Cmd(COM_USART[COM], ENABLE);
00364 }
00365
00366 /**
00367   * @brief  DeInitializes the SDIO interface.
00368   * @param  None
00369   * @retval None
00370   */
00371 void SD_LowLevel_DeInit(void)
00372 {
00373   GPIO_InitTypeDef  GPIO_InitStructure;
00374
00375   /*!< Disable SDIO Clock */
00376   SDIO_ClockCmd(DISABLE);
00377
00378   /*!< Set Power State to OFF */
00379   SDIO_SetPowerState(SDIO_PowerState_OFF);
00380
00381   /*!< DeInitializes the SDIO peripheral */
00382   SDIO_DeInit();
00383
00384   /*!< Disable the SDIO AHB Clock */
00385   RCC_AHBPeriphClockCmd(RCC_AHBPeriph_SDIO, DISABLE);
00386
00387   /*!< Configure PC.08, PC.09, PC.10, PC.11, PC.12 pin: D0, D1, D2, D3, CLK pin */
00388   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_12;
00389   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
00390   GPIO_Init(GPIOC, &GPIO_InitStructure);
00391
00392   /*!< Configure PD.02 CMD line */
00393   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
00394   GPIO_Init(GPIOD, &GPIO_InitStructure);
00395 }
00396
00397 /**
00398   * @brief  Initializes the SD Card and put it into StandBy State (Ready for
00399   *         data transfer).
00400   * @param  None
00401   * @retval None
00402   */
00403 void SD_LowLevel_Init(void)
00404 {
00405   GPIO_InitTypeDef  GPIO_InitStructure;
00406
00407   /*!< GPIOC and GPIOD Periph clock enable */
00408   RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC | RCC_APB2Periph_GPIOD | SD_DETECT_GPIO_CLK, ENABLE);
00409
00410   /*!< Configure PC.08, PC.09, PC.10, PC.11, PC.12 pin: D0, D1, D2, D3, CLK pin */
00411   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_12;
00412   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00413   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
00414   GPIO_Init(GPIOC, &GPIO_InitStructure);
00415
00416   /*!< Configure PD.02 CMD line */
00417   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
00418   GPIO_Init(GPIOD, &GPIO_InitStructure);
00419
00420   /*!< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin */
00421   GPIO_InitStructure.GPIO_Pin = SD_DETECT_PIN;
00422   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
00423   GPIO_Init(SD_DETECT_GPIO_PORT, &GPIO_InitStructure);
00424
00425   /*!< Enable the SDIO AHB Clock */
00426   RCC_AHBPeriphClockCmd(RCC_AHBPeriph_SDIO, ENABLE);
00427
00428   /*!< Enable the DMA2 Clock */
00429   RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA2, ENABLE);
00430 }
00431
00432 /**
00433   * @brief  Configures the DMA2 Channel4 for SDIO Tx request.
00434   * @param  BufferSRC: pointer to the source buffer
00435   * @param  BufferSize: buffer size
00436   * @retval None
00437   */
00438 void SD_LowLevel_DMA_TxConfig(uint32_t *BufferSRC, uint32_t BufferSize)
00439 {
00440
00441   DMA_InitTypeDef DMA_InitStructure;
00442
00443   DMA_ClearFlag(DMA2_FLAG_TC4 | DMA2_FLAG_TE4 | DMA2_FLAG_HT4 | DMA2_FLAG_GL4);
00444
00445   /*!< DMA2 Channel4 disable */
00446   DMA_Cmd(DMA2_Channel4, DISABLE);
00447
00448   /*!< DMA2 Channel4 Config */
00449   DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)SDIO_FIFO_ADDRESS;
00450   DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)BufferSRC;
00451   DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
00452   DMA_InitStructure.DMA_BufferSize = BufferSize / 4;
00453   DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
00454   DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
00455   DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Word;
00456   DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Word;
00457   DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
00458   DMA_InitStructure.DMA_Priority = DMA_Priority_High;
00459   DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
00460   DMA_Init(DMA2_Channel4, &DMA_InitStructure);
00461
00462   /*!< DMA2 Channel4 enable */
00463   DMA_Cmd(DMA2_Channel4, ENABLE);
00464 }
00465
00466 /**
00467   * @brief  Configures the DMA2 Channel4 for SDIO Rx request.
00468   * @param  BufferDST: pointer to the destination buffer
00469   * @param  BufferSize: buffer size
00470   * @retval None
00471   */
00472 void SD_LowLevel_DMA_RxConfig(uint32_t *BufferDST, uint32_t BufferSize)
00473 {
00474   DMA_InitTypeDef DMA_InitStructure;
00475
00476   DMA_ClearFlag(DMA2_FLAG_TC4 | DMA2_FLAG_TE4 | DMA2_FLAG_HT4 | DMA2_FLAG_GL4);
00477
00478   /*!< DMA2 Channel4 disable */
00479   DMA_Cmd(DMA2_Channel4, DISABLE);
00480
00481   /*!< DMA2 Channel4 Config */
00482   DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)SDIO_FIFO_ADDRESS;
00483   DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)BufferDST;
00484   DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
00485   DMA_InitStructure.DMA_BufferSize = BufferSize / 4;
00486   DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
00487   DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
00488   DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Word;
00489   DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Word;
00490   DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
00491   DMA_InitStructure.DMA_Priority = DMA_Priority_High;
00492   DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
00493   DMA_Init(DMA2_Channel4, &DMA_InitStructure);
00494
00495   /*!< DMA2 Channel4 enable */
00496   DMA_Cmd(DMA2_Channel4, ENABLE);
00497 }
00498
00499 /**
00500   * @brief  Returns the DMA End Of Transfer Status.
00501   * @param  None
00502   * @retval DMA SDIO Channel Status.
00503   */
00504 uint32_t SD_DMAEndOfTransferStatus(void)
00505 {
00506   return (uint32_t)DMA_GetFlagStatus(DMA2_FLAG_TC4);
00507 }
00508
00509 /**
00510   * @brief  DeInitializes the peripherals used by the SPI FLASH driver.
00511   * @param  None
00512   * @retval None
00513   */
00514 void sFLASH_LowLevel_DeInit(void)
00515 {
00516   GPIO_InitTypeDef GPIO_InitStructure;
00517
00518   /*!< Disable the sFLASH_SPI  */
00519   SPI_Cmd(sFLASH_SPI, DISABLE);
00520
00521   /*!< DeInitializes the sFLASH_SPI */
00522   SPI_I2S_DeInit(sFLASH_SPI);
00523
00524   /*!< sFLASH_SPI Periph clock disable */
00525   RCC_APB2PeriphClockCmd(sFLASH_SPI_CLK, DISABLE);
00526
00527   /*!< Configure sFLASH_SPI pins: SCK */
00528   GPIO_InitStructure.GPIO_Pin = sFLASH_SPI_SCK_PIN;
00529   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
00530   GPIO_Init(sFLASH_SPI_SCK_GPIO_PORT, &GPIO_InitStructure);
00531
00532   /*!< Configure sFLASH_SPI pins: MISO */
00533   GPIO_InitStructure.GPIO_Pin = sFLASH_SPI_MISO_PIN;
00534   GPIO_Init(sFLASH_SPI_MISO_GPIO_PORT, &GPIO_InitStructure);
00535
00536   /*!< Configure sFLASH_SPI pins: MOSI */
00537   GPIO_InitStructure.GPIO_Pin = sFLASH_SPI_MOSI_PIN;
00538   GPIO_Init(sFLASH_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure);
00539
00540   /*!< Configure sFLASH_CS_PIN pin: sFLASH Card CS pin */
00541   GPIO_InitStructure.GPIO_Pin = sFLASH_CS_PIN;
00542   GPIO_Init(sFLASH_CS_GPIO_PORT, &GPIO_InitStructure);
00543 }
00544
00545 /**
00546   * @brief  Initializes the peripherals used by the SPI FLASH driver.
00547   * @param  None
00548   * @retval None
00549   */
00550 void sFLASH_LowLevel_Init(void)
00551 {
00552   GPIO_InitTypeDef GPIO_InitStructure;
00553
00554   /*!< sFLASH_SPI_CS_GPIO, sFLASH_SPI_MOSI_GPIO, sFLASH_SPI_MISO_GPIO
00555        and sFLASH_SPI_SCK_GPIO Periph clock enable */
00556   RCC_APB2PeriphClockCmd(sFLASH_CS_GPIO_CLK | sFLASH_SPI_MOSI_GPIO_CLK | sFLASH_SPI_MISO_GPIO_CLK |
00557                          sFLASH_SPI_SCK_GPIO_CLK, ENABLE);
00558
00559   /*!< sFLASH_SPI Periph clock enable */
00560   RCC_APB2PeriphClockCmd(sFLASH_SPI_CLK, ENABLE);
00561
00562   /*!< Configure sFLASH_SPI pins: SCK */
00563   GPIO_InitStructure.GPIO_Pin = sFLASH_SPI_SCK_PIN;
00564   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00565   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
00566   GPIO_Init(sFLASH_SPI_SCK_GPIO_PORT, &GPIO_InitStructure);
00567
00568   /*!< Configure sFLASH_SPI pins: MOSI */
00569   GPIO_InitStructure.GPIO_Pin = sFLASH_SPI_MOSI_PIN;
00570   GPIO_Init(sFLASH_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure);
00571
00572   /*!< Configure sFLASH_SPI pins: MISO */
00573   GPIO_InitStructure.GPIO_Pin = sFLASH_SPI_MISO_PIN;
00574   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
00575   GPIO_Init(sFLASH_SPI_MISO_GPIO_PORT, &GPIO_InitStructure);
00576
00577   /*!< Configure sFLASH_CS_PIN pin: sFLASH Card CS pin */
00578   GPIO_InitStructure.GPIO_Pin = sFLASH_CS_PIN;
00579   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
00580   GPIO_Init(sFLASH_CS_GPIO_PORT, &GPIO_InitStructure);
00581 }
00582
00583 /**
00584   * @brief  DeInitializes the LM75_I2C.
00585   * @param  None
00586   * @retval None
00587   */
00588 void LM75_LowLevel_DeInit(void)
00589 {
00590   GPIO_InitTypeDef  GPIO_InitStructure;
00591
00592   /*!< Disable LM75_I2C */
00593   I2C_Cmd(LM75_I2C, DISABLE);
00594   /*!< DeInitializes the LM75_I2C */
00595   I2C_DeInit(LM75_I2C);
00596
00597   /*!< LM75_I2C Periph clock disable */
00598   RCC_APB1PeriphClockCmd(LM75_I2C_CLK, DISABLE);
00599
00600   /*!< Configure LM75_I2C pins: SCL */
00601   GPIO_InitStructure.GPIO_Pin = LM75_I2C_SCL_PIN;
00602   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
00603   GPIO_Init(LM75_I2C_SCL_GPIO_PORT, &GPIO_InitStructure);
00604
00605   /*!< Configure LM75_I2C pins: SDA */
00606   GPIO_InitStructure.GPIO_Pin = LM75_I2C_SDA_PIN;
00607   GPIO_Init(LM75_I2C_SDA_GPIO_PORT, &GPIO_InitStructure);
00608
00609   /*!< Configure LM75_I2C pin: SMBUS ALERT */
00610   GPIO_InitStructure.GPIO_Pin = LM75_I2C_SMBUSALERT_PIN;
00611   GPIO_Init(LM75_I2C_SMBUSALERT_GPIO_PORT, &GPIO_InitStructure);
00612 }
00613
00614 /**
00615   * @brief  Initializes the LM75_I2C..
00616   * @param  None
00617   * @retval None
00618   */
00619 void LM75_LowLevel_Init(void)
00620 {
00621   GPIO_InitTypeDef  GPIO_InitStructure;
00622
00623   /*!< LM75_I2C Periph clock enable */
00624   RCC_APB1PeriphClockCmd(LM75_I2C_CLK, ENABLE);
00625
00626   /*!< LM75_I2C_SCL_GPIO_CLK, LM75_I2C_SDA_GPIO_CLK
00627        and LM75_I2C_SMBUSALERT_GPIO_CLK Periph clock enable */
00628   RCC_APB2PeriphClockCmd(LM75_I2C_SCL_GPIO_CLK | LM75_I2C_SDA_GPIO_CLK |
00629                          LM75_I2C_SMBUSALERT_GPIO_CLK, ENABLE);
00630
00631   /*!< Configure LM75_I2C pins: SCL */
00632   GPIO_InitStructure.GPIO_Pin = LM75_I2C_SCL_PIN;
00633   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00634   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_OD;
00635   GPIO_Init(LM75_I2C_SCL_GPIO_PORT, &GPIO_InitStructure);
00636
00637   /*!< Configure LM75_I2C pins: SDA */
00638   GPIO_InitStructure.GPIO_Pin = LM75_I2C_SDA_PIN;
00639   GPIO_Init(LM75_I2C_SDA_GPIO_PORT, &GPIO_InitStructure);
00640
00641   /*!< Configure LM75_I2C pin: SMBUS ALERT */
00642   GPIO_InitStructure.GPIO_Pin = LM75_I2C_SMBUSALERT_PIN;
00643   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
00644   GPIO_Init(LM75_I2C_SMBUSALERT_GPIO_PORT, &GPIO_InitStructure);
00645 }
00646
00647 /**
00648   * @}
00649   */
00650
00651 /**
00652   * @}
00653   */
00654
00655 /**
00656   * @}
00657   */
00658
00659 /**
00660   * @}
00661   */
00662
00663 /**
00664   * @}
00665   */
00666
00667 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm3210e_eval.h Source File

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  • STM3210E_EVAL

stm3210e_eval.h

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00001 /**
00002   ******************************************************************************
00003   * @file    stm3210e_eval.h
00004   * @author  MCD Application Team
00005   * @version V4.5.0
00006   * @date    07-March-2011
00007   * @brief   This file contains definitions for STM3210E_EVAL's Leds, push-buttons
00008   *          COM ports, sFLASH (on SPI) and Temperature Sensor LM75 (on I2C)
00009   *          hardware resources.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Define to prevent recursive inclusion -------------------------------------*/
00025 #ifndef __STM3210E_EVAL_H
00026 #define __STM3210E_EVAL_H
00027
00028 #ifdef __cplusplus
00029  extern "C" {
00030 #endif
00031
00032 /* Includes ------------------------------------------------------------------*/
00033 #include "stm32_eval.h"
00034
00035 /** @addtogroup Utilities
00036   * @{
00037   */
00038
00039 /** @addtogroup STM32_EVAL
00040   * @{
00041   */
00042
00043 /** @addtogroup STM3210E_EVAL
00044   * @{
00045   */
00046
00047 /** @addtogroup STM3210E_EVAL_LOW_LEVEL
00048   * @{
00049   */
00050
00051 /** @defgroup STM3210E_EVAL_LOW_LEVEL_Exported_Types
00052   * @{
00053   */
00054 /**
00055   * @}
00056   */
00057
00058 /** @defgroup STM3210E_EVAL_LOW_LEVEL_Exported_Constants
00059   * @{
00060   */
00061 /** @addtogroup STM3210E_EVAL_LOW_LEVEL_LED
00062   * @{
00063   */
00064 #define LEDn                             4
00065
00066 #define LED1_PIN                         GPIO_Pin_6
00067 #define LED1_GPIO_PORT                   GPIOF
00068 #define LED1_GPIO_CLK                    RCC_APB2Periph_GPIOF
00069
00070 #define LED2_PIN                         GPIO_Pin_7
00071 #define LED2_GPIO_PORT                   GPIOF
00072 #define LED2_GPIO_CLK                    RCC_APB2Periph_GPIOF
00073
00074 #define LED3_PIN                         GPIO_Pin_8
00075 #define LED3_GPIO_PORT                   GPIOF
00076 #define LED3_GPIO_CLK                    RCC_APB2Periph_GPIOF
00077
00078 #define LED4_PIN                         GPIO_Pin_9
00079 #define LED4_GPIO_PORT                   GPIOF
00080 #define LED4_GPIO_CLK                    RCC_APB2Periph_GPIOF
00081
00082 /**
00083   * @}
00084   */
00085
00086 /** @addtogroup STM3210E_EVAL_LOW_LEVEL_BUTTON
00087   * @{
00088   */
00089 #define BUTTONn                          8
00090
00091 /**
00092  * @brief Wakeup push-button
00093  */
00094 #define WAKEUP_BUTTON_PIN                GPIO_Pin_0
00095 #define WAKEUP_BUTTON_GPIO_PORT          GPIOA
00096 #define WAKEUP_BUTTON_GPIO_CLK           RCC_APB2Periph_GPIOA
00097 #define WAKEUP_BUTTON_EXTI_LINE          EXTI_Line0
00098 #define WAKEUP_BUTTON_EXTI_PORT_SOURCE   GPIO_PortSourceGPIOA
00099 #define WAKEUP_BUTTON_EXTI_PIN_SOURCE    GPIO_PinSource0
00100 #define WAKEUP_BUTTON_EXTI_IRQn          EXTI0_IRQn
00101 /**
00102  * @brief Tamper push-button
00103  */
00104 #define TAMPER_BUTTON_PIN                GPIO_Pin_13
00105 #define TAMPER_BUTTON_GPIO_PORT          GPIOC
00106 #define TAMPER_BUTTON_GPIO_CLK           RCC_APB2Periph_GPIOC
00107 #define TAMPER_BUTTON_EXTI_LINE          EXTI_Line13
00108 #define TAMPER_BUTTON_EXTI_PORT_SOURCE   GPIO_PortSourceGPIOC
00109 #define TAMPER_BUTTON_EXTI_PIN_SOURCE    GPIO_PinSource13
00110 #define TAMPER_BUTTON_EXTI_IRQn          EXTI15_10_IRQn
00111 /**
00112  * @brief Key push-button
00113  */
00114 #define KEY_BUTTON_PIN                   GPIO_Pin_8
00115 #define KEY_BUTTON_GPIO_PORT             GPIOG
00116 #define KEY_BUTTON_GPIO_CLK              RCC_APB2Periph_GPIOG
00117 #define KEY_BUTTON_EXTI_LINE             EXTI_Line8
00118 #define KEY_BUTTON_EXTI_PORT_SOURCE      GPIO_PortSourceGPIOG
00119 #define KEY_BUTTON_EXTI_PIN_SOURCE       GPIO_PinSource8
00120 #define KEY_BUTTON_EXTI_IRQn             EXTI9_5_IRQn
00121 /**
00122  * @brief Joystick Right push-button
00123  */
00124 #define RIGHT_BUTTON_PIN                 GPIO_Pin_13
00125 #define RIGHT_BUTTON_GPIO_PORT           GPIOG
00126 #define RIGHT_BUTTON_GPIO_CLK            RCC_APB2Periph_GPIOG
00127 #define RIGHT_BUTTON_EXTI_LINE           EXTI_Line13
00128 #define RIGHT_BUTTON_EXTI_PORT_SOURCE    GPIO_PortSourceGPIOG
00129 #define RIGHT_BUTTON_EXTI_PIN_SOURCE     GPIO_PinSource13
00130 #define RIGHT_BUTTON_EXTI_IRQn           EXTI15_10_IRQn
00131 /**
00132  * @brief Joystick Left push-button
00133  */
00134 #define LEFT_BUTTON_PIN                  GPIO_Pin_14
00135 #define LEFT_BUTTON_GPIO_PORT            GPIOG
00136 #define LEFT_BUTTON_GPIO_CLK             RCC_APB2Periph_GPIOG
00137 #define LEFT_BUTTON_EXTI_LINE            EXTI_Line14
00138 #define LEFT_BUTTON_EXTI_PORT_SOURCE     GPIO_PortSourceGPIOG
00139 #define LEFT_BUTTON_EXTI_PIN_SOURCE      GPIO_PinSource14
00140 #define LEFT_BUTTON_EXTI_IRQn            EXTI15_10_IRQn
00141 /**
00142  * @brief Joystick Up push-button
00143  */
00144 #define UP_BUTTON_PIN                    GPIO_Pin_15
00145 #define UP_BUTTON_GPIO_PORT              GPIOG
00146 #define UP_BUTTON_GPIO_CLK               RCC_APB2Periph_GPIOG
00147 #define UP_BUTTON_EXTI_LINE              EXTI_Line15
00148 #define UP_BUTTON_EXTI_PORT_SOURCE       GPIO_PortSourceGPIOG
00149 #define UP_BUTTON_EXTI_PIN_SOURCE        GPIO_PinSource15
00150 #define UP_BUTTON_EXTI_IRQn              EXTI15_10_IRQn
00151 /**
00152  * @brief Joystick Down push-button
00153  */
00154 #define DOWN_BUTTON_PIN                  GPIO_Pin_3
00155 #define DOWN_BUTTON_GPIO_PORT            GPIOD
00156 #define DOWN_BUTTON_GPIO_CLK             RCC_APB2Periph_GPIOD
00157 #define DOWN_BUTTON_EXTI_LINE            EXTI_Line3
00158 #define DOWN_BUTTON_EXTI_PORT_SOURCE     GPIO_PortSourceGPIOD
00159 #define DOWN_BUTTON_EXTI_PIN_SOURCE      GPIO_PinSource3
00160 #define DOWN_BUTTON_EXTI_IRQn            EXTI3_IRQn
00161 /**
00162  * @brief Joystick Sel push-button
00163  */
00164 #define SEL_BUTTON_PIN                   GPIO_Pin_7
00165 #define SEL_BUTTON_GPIO_PORT             GPIOG
00166 #define SEL_BUTTON_GPIO_CLK              RCC_APB2Periph_GPIOG
00167 #define SEL_BUTTON_EXTI_LINE             EXTI_Line7
00168 #define SEL_BUTTON_EXTI_PORT_SOURCE      GPIO_PortSourceGPIOG
00169 #define SEL_BUTTON_EXTI_PIN_SOURCE       GPIO_PinSource7
00170 #define SEL_BUTTON_EXTI_IRQn             EXTI9_5_IRQn
00171 /**
00172   * @}
00173   */
00174
00175 /** @addtogroup STM3210E_EVAL_LOW_LEVEL_COM
00176   * @{
00177   */
00178 #define COMn                             2
00179
00180 /**
00181  * @brief Definition for COM port1, connected to USART1
00182  */
00183 #define EVAL_COM1                        USART1
00184 #define EVAL_COM1_CLK                    RCC_APB2Periph_USART1
00185 #define EVAL_COM1_TX_PIN                 GPIO_Pin_9
00186 #define EVAL_COM1_TX_GPIO_PORT           GPIOA
00187 #define EVAL_COM1_TX_GPIO_CLK            RCC_APB2Periph_GPIOA
00188 #define EVAL_COM1_RX_PIN                 GPIO_Pin_10
00189 #define EVAL_COM1_RX_GPIO_PORT           GPIOA
00190 #define EVAL_COM1_RX_GPIO_CLK            RCC_APB2Periph_GPIOA
00191 #define EVAL_COM1_IRQn                   USART1_IRQn
00192
00193 /**
00194  * @brief Definition for COM port2, connected to USART2
00195  */
00196 #define EVAL_COM2                        USART2
00197 #define EVAL_COM2_CLK                    RCC_APB1Periph_USART2
00198 #define EVAL_COM2_TX_PIN                 GPIO_Pin_2
00199 #define EVAL_COM2_TX_GPIO_PORT           GPIOA
00200 #define EVAL_COM2_TX_GPIO_CLK            RCC_APB2Periph_GPIOA
00201 #define EVAL_COM2_RX_PIN                 GPIO_Pin_3
00202 #define EVAL_COM2_RX_GPIO_PORT           GPIOA
00203 #define EVAL_COM2_RX_GPIO_CLK            RCC_APB2Periph_GPIOA
00204 #define EVAL_COM2_IRQn                   USART2_IRQn
00205
00206 /**
00207   * @}
00208   */
00209
00210 /** @addtogroup STM3210E_EVAL_LOW_LEVEL_SD_FLASH
00211   * @{
00212   */
00213 /**
00214   * @brief  SD FLASH SDIO Interface
00215   */
00216
00217 #define SD_DETECT_PIN                    GPIO_Pin_11                 /* PF.11 */
00218 #define SD_DETECT_GPIO_PORT              GPIOF                       /* GPIOF */
00219 #define SD_DETECT_GPIO_CLK               RCC_APB2Periph_GPIOF
00220
00221 #define SDIO_FIFO_ADDRESS                ((uint32_t)0x40018080)
00222 /**
00223   * @brief  SDIO Intialization Frequency (400KHz max)
00224   */
00225 #define SDIO_INIT_CLK_DIV                ((uint8_t)0xB2)
00226 /**
00227   * @brief  SDIO Data Transfer Frequency (25MHz max)
00228   */
00229 #define SDIO_TRANSFER_CLK_DIV            ((uint8_t)0x00)
00230
00231 /**
00232   * @}
00233   */
00234
00235 /** @addtogroup STM3210E_EVAL_LOW_LEVEL_M25P_FLASH_SPI
00236   * @{
00237   */
00238 /**
00239   * @brief  M25P FLASH SPI Interface pins
00240   */
00241 #define sFLASH_SPI                       SPI1
00242 #define sFLASH_SPI_CLK                   RCC_APB2Periph_SPI1
00243 #define sFLASH_SPI_SCK_PIN               GPIO_Pin_5                  /* PA.05 */
00244 #define sFLASH_SPI_SCK_GPIO_PORT         GPIOA                       /* GPIOA */
00245 #define sFLASH_SPI_SCK_GPIO_CLK          RCC_APB2Periph_GPIOA
00246 #define sFLASH_SPI_MISO_PIN              GPIO_Pin_6                  /* PA.06 */
00247 #define sFLASH_SPI_MISO_GPIO_PORT        GPIOA                       /* GPIOA */
00248 #define sFLASH_SPI_MISO_GPIO_CLK         RCC_APB2Periph_GPIOA
00249 #define sFLASH_SPI_MOSI_PIN              GPIO_Pin_7                  /* PA.07 */
00250 #define sFLASH_SPI_MOSI_GPIO_PORT        GPIOA                       /* GPIOA */
00251 #define sFLASH_SPI_MOSI_GPIO_CLK         RCC_APB2Periph_GPIOA
00252 #define sFLASH_CS_PIN                    GPIO_Pin_2                  /* PB.02 */
00253 #define sFLASH_CS_GPIO_PORT              GPIOB                       /* GPIOB */
00254 #define sFLASH_CS_GPIO_CLK               RCC_APB2Periph_GPIOB
00255
00256 /**
00257   * @}
00258   */
00259
00260 /** @addtogroup STM3210E_EVAL_LOW_LEVEL_TSENSOR_I2C
00261   * @{
00262   */
00263 /**
00264   * @brief  LM75 Temperature Sensor I2C Interface pins
00265   */
00266 #define LM75_I2C                         I2C1
00267 #define LM75_I2C_CLK                     RCC_APB1Periph_I2C1
00268 #define LM75_I2C_SCL_PIN                 GPIO_Pin_6                  /* PB.06 */
00269 #define LM75_I2C_SCL_GPIO_PORT           GPIOB                       /* GPIOB */
00270 #define LM75_I2C_SCL_GPIO_CLK            RCC_APB2Periph_GPIOB
00271 #define LM75_I2C_SDA_PIN                 GPIO_Pin_7                  /* PB.07 */
00272 #define LM75_I2C_SDA_GPIO_PORT           GPIOB                       /* GPIOB */
00273 #define LM75_I2C_SDA_GPIO_CLK            RCC_APB2Periph_GPIOB
00274 #define LM75_I2C_SMBUSALERT_PIN          GPIO_Pin_5                  /* PB.05 */
00275 #define LM75_I2C_SMBUSALERT_GPIO_PORT    GPIOB                       /* GPIOB */
00276 #define LM75_I2C_SMBUSALERT_GPIO_CLK     RCC_APB2Periph_GPIOB
00277 #define LM75_I2C_DR                      ((uint32_t)0x40005410)
00278
00279 #define LM75_DMA_CLK                     RCC_AHBPeriph_DMA1
00280 #define LM75_DMA_TX_CHANNEL              DMA1_Channel6
00281 #define LM75_DMA_RX_CHANNEL              DMA1_Channel7
00282 #define LM75_DMA_TX_TCFLAG               DMA1_FLAG_TC6
00283 #define LM75_DMA_RX_TCFLAG               DMA1_FLAG_TC7
00284 /**
00285   * @}
00286   */
00287
00288 /**
00289   * @}
00290   */
00291
00292 /** @defgroup STM3210E_EVAL_LOW_LEVEL_Exported_Macros
00293   * @{
00294   */
00295 /**
00296   * @}
00297   */
00298
00299 /** @defgroup STM3210E_EVAL_LOW_LEVEL_Exported_Functions
00300   * @{
00301   */
00302 void STM_EVAL_LEDInit(Led_TypeDef Led);
00303 void STM_EVAL_LEDOn(Led_TypeDef Led);
00304 void STM_EVAL_LEDOff(Led_TypeDef Led);
00305 void STM_EVAL_LEDToggle(Led_TypeDef Led);
00306 void STM_EVAL_PBInit(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode);
00307 uint32_t STM_EVAL_PBGetState(Button_TypeDef Button);
00308 void STM_EVAL_COMInit(COM_TypeDef COM, USART_InitTypeDef* USART_InitStruct);
00309 void SD_LowLevel_DeInit(void);
00310 void SD_LowLevel_Init(void);
00311 void SD_LowLevel_DMA_TxConfig(uint32_t *BufferSRC, uint32_t BufferSize);
00312 void SD_LowLevel_DMA_RxConfig(uint32_t *BufferDST, uint32_t BufferSize);
00313 uint32_t SD_DMAEndOfTransferStatus(void);
00314 void sFLASH_LowLevel_DeInit(void);
00315 void sFLASH_LowLevel_Init(void);
00316 void LM75_LowLevel_DeInit(void);
00317 void LM75_LowLevel_Init(void);
00318 /**
00319   * @}
00320   */
00321 #ifdef __cplusplus
00322 }
00323 #endif
00324
00325 #endif /* __STM3210E_EVAL_H */
00326 /**
00327   * @}
00328   */
00329
00330 /**
00331   * @}
00332   */
00333
00334 /**
00335   * @}
00336   */
00337
00338 /**
00339   * @}
00340   */
00341
00342 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm3210e_eval_fsmc_nand.c Source File

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stm3210e_eval_fsmc_nand.c

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00001 /**
00002   ******************************************************************************
00003   * @file    stm3210e_eval_fsmc_nand.c
00004   * @author  MCD Application Team
00005   * @version V4.5.0
00006   * @date    07-March-2011
00007   * @brief   This file provides a set of functions needed to drive the
00008   *          NAND512W3A2 memory mounted on STM3210E-EVAL board.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00013   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00014   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00015   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00016   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00017   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00018   *
00019   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00020   ******************************************************************************
00021   */
00022
00023 /* Includes ------------------------------------------------------------------*/
00024 #include "stm3210e_eval_fsmc_nand.h"
00025
00026 /** @addtogroup Utilities
00027   * @{
00028   */
00029
00030 /** @addtogroup STM32_EVAL
00031   * @{
00032   */
00033
00034 /** @addtogroup STM3210E_EVAL
00035   * @{
00036   */
00037
00038 /** @addtogroup STM3210E_EVAL_FSMC_NAND
00039   * @brief      This file provides a set of functions needed to drive the
00040   *             NAND512W3A2 memory mounted on STM3210E-EVAL board.
00041   * @{
00042   */
00043
00044 /** @defgroup STM3210E_EVAL_FSMC_NAND_Private_Types
00045   * @{
00046   */
00047 /**
00048   * @}
00049   */
00050
00051
00052 /** @defgroup STM3210E_EVAL_FSMC_NAND_Private_Defines
00053   * @{
00054   */
00055 /**
00056   * @brief  FSMC Bank 2
00057   */
00058 #define FSMC_Bank_NAND     FSMC_Bank2_NAND
00059 #define Bank_NAND_ADDR     Bank2_NAND_ADDR
00060 #define Bank2_NAND_ADDR    ((uint32_t)0x70000000)
00061 /**
00062   * @}
00063   */
00064
00065 /** @defgroup STM3210E_EVAL_FSMC_NAND_Private_Macros
00066   * @{
00067   */
00068 #define ROW_ADDRESS (Address.Page + (Address.Block + (Address.Zone * NAND_ZONE_SIZE)) * NAND_BLOCK_SIZE)
00069 /**
00070   * @}
00071   */
00072
00073
00074 /** @defgroup STM3210E_EVAL_FSMC_NAND_Private_Variables
00075   * @{
00076   */
00077 /**
00078   * @}
00079   */
00080
00081
00082 /** @defgroup STM3210E_EVAL_FSMC_NAND_Private_Function_Prototypes
00083   * @{
00084   */
00085 /**
00086   * @}
00087   */
00088
00089
00090 /** @defgroup STM3210E_EVAL_FSMC_NAND_Private_Functions
00091   * @{
00092   */
00093
00094 /**
00095   * @brief  Configures the FSMC and GPIOs to interface with the NAND memory.
00096   *         This function must be called before any write/read operation on the
00097   *         NAND.
00098   * @param  None
00099   * @retval None
00100   */
00101 void NAND_Init(void)
00102 {
00103   GPIO_InitTypeDef GPIO_InitStructure;
00104   FSMC_NANDInitTypeDef FSMC_NANDInitStructure;
00105   FSMC_NAND_PCCARDTimingInitTypeDef  p;
00106
00107   RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOE |
00108                          RCC_APB2Periph_GPIOF | RCC_APB2Periph_GPIOG, ENABLE);
00109
00110 /*-- GPIO Configuration ------------------------------------------------------*/
00111 /*!< CLE, ALE, D0->D3, NOE, NWE and NCE2  NAND pin configuration  */
00112   GPIO_InitStructure.GPIO_Pin =  GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_14 | GPIO_Pin_15 |
00113                                  GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_4 | GPIO_Pin_5 |
00114                                  GPIO_Pin_7;
00115   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00116   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
00117
00118   GPIO_Init(GPIOD, &GPIO_InitStructure);
00119
00120 /*!< D4->D7 NAND pin configuration  */
00121   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10;
00122
00123   GPIO_Init(GPIOE, &GPIO_InitStructure);
00124
00125
00126 /*!< NWAIT NAND pin configuration */
00127   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
00128   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00129   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
00130
00131   GPIO_Init(GPIOD, &GPIO_InitStructure);
00132
00133 /*!< INT2 NAND pin configuration */
00134   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
00135   GPIO_Init(GPIOG, &GPIO_InitStructure);
00136
00137   /*-- FSMC Configuration ------------------------------------------------------*/
00138   p.FSMC_SetupTime = 0x0;
00139   p.FSMC_WaitSetupTime = 0x2;
00140   p.FSMC_HoldSetupTime = 0x1;
00141   p.FSMC_HiZSetupTime = 0x0;
00142
00143   FSMC_NANDInitStructure.FSMC_Bank = FSMC_Bank2_NAND;
00144   FSMC_NANDInitStructure.FSMC_Waitfeature = FSMC_Waitfeature_Enable;
00145   FSMC_NANDInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
00146   FSMC_NANDInitStructure.FSMC_ECC = FSMC_ECC_Enable;
00147   FSMC_NANDInitStructure.FSMC_ECCPageSize = FSMC_ECCPageSize_512Bytes;
00148   FSMC_NANDInitStructure.FSMC_TCLRSetupTime = 0x00;
00149   FSMC_NANDInitStructure.FSMC_TARSetupTime = 0x00;
00150   FSMC_NANDInitStructure.FSMC_CommonSpaceTimingStruct = &p;
00151   FSMC_NANDInitStructure.FSMC_AttributeSpaceTimingStruct = &p;
00152
00153   FSMC_NANDInit(&FSMC_NANDInitStructure);
00154
00155   /*!< FSMC NAND Bank Cmd Test */
00156   FSMC_NANDCmd(FSMC_Bank2_NAND, ENABLE);
00157 }
00158
00159 /**
00160   * @brief  Reads NAND memory's ID.
00161   * @param  NAND_ID: pointer to a NAND_IDTypeDef structure which will hold
00162   *         the Manufacturer and Device ID.
00163   * @retval None
00164   */
00165 void NAND_ReadID(NAND_IDTypeDef* NAND_ID)
00166 {
00167   uint32_t data = 0;
00168
00169   /*!< Send Command to the command area */
00170   *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = 0x90;
00171   *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = 0x00;
00172
00173    /*!< Sequence to read ID from NAND flash */
00174    data = *(__IO uint32_t *)(Bank_NAND_ADDR | DATA_AREA);
00175
00176    NAND_ID->Maker_ID   = ADDR_1st_CYCLE (data);
00177    NAND_ID->Device_ID  = ADDR_2nd_CYCLE (data);
00178    NAND_ID->Third_ID   = ADDR_3rd_CYCLE (data);
00179    NAND_ID->Fourth_ID  = ADDR_4th_CYCLE (data);
00180 }
00181
00182 /**
00183   * @brief  This routine is for writing one or several 512 Bytes Page size.
00184   * @param  pBuffer: pointer on the Buffer containing data to be written
00185   * @param  Address: First page address
00186   * @param  NumPageToWrite: Number of page to write
00187   * @retval New status of the NAND operation. This parameter can be:
00188   *              - NAND_TIMEOUT_ERROR: when the previous operation generate
00189   *                a Timeout error
00190   *              - NAND_READY: when memory is ready for the next operation
00191   *                And the new status of the increment address operation. It can be:
00192   *              - NAND_VALID_ADDRESS: When the new address is valid address
00193   *              - NAND_INVALID_ADDRESS: When the new address is invalid address
00194   */
00195 uint32_t NAND_WriteSmallPage(uint8_t *pBuffer, NAND_ADDRESS Address, uint32_t NumPageToWrite)
00196 {
00197   uint32_t index = 0x00, numpagewritten = 0x00, addressstatus = NAND_VALID_ADDRESS;
00198   uint32_t status = NAND_READY, size = 0x00;
00199
00200   while((NumPageToWrite != 0x00) && (addressstatus == NAND_VALID_ADDRESS) && (status == NAND_READY))
00201   {
00202     /*!< Page write command and address */
00203     *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_AREA_A;
00204     *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_WRITE0;
00205
00206     *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = 0x00;
00207     *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(ROW_ADDRESS);
00208     *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_2nd_CYCLE(ROW_ADDRESS);
00209     *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_3rd_CYCLE(ROW_ADDRESS);
00210
00211     /*!< Calculate the size */
00212     size = NAND_PAGE_SIZE + (NAND_PAGE_SIZE * numpagewritten);
00213
00214     /*!< Write data */
00215     for(; index < size; index++)
00216     {
00217       *(__IO uint8_t *)(Bank_NAND_ADDR | DATA_AREA) = pBuffer[index];
00218     }
00219
00220     *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_WRITE_TRUE1;
00221
00222     /*!< Check status for successful operation */
00223     status = NAND_GetStatus();
00224
00225     if(status == NAND_READY)
00226     {
00227       numpagewritten++;
00228
00229       NumPageToWrite--;
00230
00231       /*!< Calculate Next small page Address */
00232       addressstatus = NAND_AddressIncrement(&Address);
00233     }
00234   }
00235
00236   return (status | addressstatus);
00237 }
00238
00239 /**
00240   * @brief  This routine is for sequential read from one or several 512 Bytes Page size.
00241   * @param  pBuffer: pointer on the Buffer to fill
00242   * @param  Address: First page address
00243   * @param  NumPageToRead: Number of page to read
00244   * @retval New status of the NAND operation. This parameter can be:
00245   *              - NAND_TIMEOUT_ERROR: when the previous operation generate
00246   *                a Timeout error
00247   *              - NAND_READY: when memory is ready for the next operation
00248   *                And the new status of the increment address operation. It can be:
00249   *              - NAND_VALID_ADDRESS: When the new address is valid address
00250   *              - NAND_INVALID_ADDRESS: When the new address is invalid address
00251   */
00252 uint32_t NAND_ReadSmallPage(uint8_t *pBuffer, NAND_ADDRESS Address, uint32_t NumPageToRead)
00253 {
00254   uint32_t index = 0x00, numpageread = 0x00, addressstatus = NAND_VALID_ADDRESS;
00255   uint32_t status = NAND_READY, size = 0x00;
00256
00257   while((NumPageToRead != 0x0) && (addressstatus == NAND_VALID_ADDRESS))
00258   {
00259     /*!< Page Read command and page address */
00260     *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_AREA_A;
00261
00262     *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = 0x00;
00263     *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(ROW_ADDRESS);
00264     *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_2nd_CYCLE(ROW_ADDRESS);
00265     *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_3rd_CYCLE(ROW_ADDRESS);
00266
00267     /*!< Calculate the size */
00268     size = NAND_PAGE_SIZE + (NAND_PAGE_SIZE * numpageread);
00269
00270     /*!< Get Data into Buffer */
00271     for(; index < size; index++)
00272     {
00273       pBuffer[index]= *(__IO uint8_t *)(Bank_NAND_ADDR | DATA_AREA);
00274     }
00275
00276     numpageread++;
00277
00278     NumPageToRead--;
00279
00280     /*!< Calculate page address */
00281     addressstatus = NAND_AddressIncrement(&Address);
00282   }
00283
00284   status = NAND_GetStatus();
00285
00286   return (status | addressstatus);
00287 }
00288
00289 /**
00290   * @brief  This routine write the spare area information for the specified
00291   *         pages addresses.
00292   * @param  pBuffer: pointer on the Buffer containing data to be written
00293   * @param  Address: First page address
00294   * @param  NumSpareAreaTowrite: Number of Spare Area to write
00295   * @retval New status of the NAND operation. This parameter can be:
00296   *              - NAND_TIMEOUT_ERROR: when the previous operation generate
00297   *                a Timeout error
00298   *              - NAND_READY: when memory is ready for the next operation
00299   *                And the new status of the increment address operation. It can be:
00300   *              - NAND_VALID_ADDRESS: When the new address is valid address
00301   *              - NAND_INVALID_ADDRESS: When the new address is invalid address
00302   */
00303 uint32_t NAND_WriteSpareArea(uint8_t *pBuffer, NAND_ADDRESS Address, uint32_t NumSpareAreaTowrite)
00304 {
00305   uint32_t index = 0x00, numsparesreawritten = 0x00, addressstatus = NAND_VALID_ADDRESS;
00306   uint32_t status = NAND_READY, size = 0x00;
00307
00308   while((NumSpareAreaTowrite != 0x00) && (addressstatus == NAND_VALID_ADDRESS) && (status == NAND_READY))
00309   {
00310     /*!< Page write Spare area command and address */
00311     *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_AREA_C;
00312     *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_WRITE0;
00313
00314     *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = 0x00;
00315     *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(ROW_ADDRESS);
00316     *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_2nd_CYCLE(ROW_ADDRESS);
00317     *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_3rd_CYCLE(ROW_ADDRESS);
00318
00319     /*!< Calculate the size */
00320     size = NAND_SPARE_AREA_SIZE + (NAND_SPARE_AREA_SIZE * numsparesreawritten);
00321
00322     /*!< Write the data */
00323     for(; index < size; index++)
00324     {
00325       *(__IO uint8_t *)(Bank_NAND_ADDR | DATA_AREA) = pBuffer[index];
00326     }
00327
00328     *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_WRITE_TRUE1;
00329
00330     /*!< Check status for successful operation */
00331     status = NAND_GetStatus();
00332
00333     if(status == NAND_READY)
00334     {
00335       numsparesreawritten++;
00336
00337       NumSpareAreaTowrite--;
00338
00339       /*!< Calculate Next page Address */
00340       addressstatus = NAND_AddressIncrement(&Address);
00341     }
00342   }
00343
00344   return (status | addressstatus);
00345 }
00346
00347 /**
00348   * @brief  This routine read the spare area information from the specified
00349   *         pages addresses.
00350   * @param  pBuffer: pointer on the Buffer to fill
00351   * @param  Address: First page address
00352   * @param  NumSpareAreaToRead: Number of Spare Area to read
00353   * @retval New status of the NAND operation. This parameter can be:
00354   *              - NAND_TIMEOUT_ERROR: when the previous operation generate
00355   *                a Timeout error
00356   *              - NAND_READY: when memory is ready for the next operation
00357   *                And the new status of the increment address operation. It can be:
00358   *              - NAND_VALID_ADDRESS: When the new address is valid address
00359   *              - NAND_INVALID_ADDRESS: When the new address is invalid address
00360   */
00361 uint32_t NAND_ReadSpareArea(uint8_t *pBuffer, NAND_ADDRESS Address, uint32_t NumSpareAreaToRead)
00362 {
00363   uint32_t numsparearearead = 0x00, index = 0x00, addressstatus = NAND_VALID_ADDRESS;
00364   uint32_t status = NAND_READY, size = 0x00;
00365
00366   while((NumSpareAreaToRead != 0x0) && (addressstatus == NAND_VALID_ADDRESS))
00367   {
00368     /*!< Page Read command and page address */
00369     *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_AREA_C;
00370
00371     *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = 0x00;
00372     *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(ROW_ADDRESS);
00373     *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_2nd_CYCLE(ROW_ADDRESS);
00374     *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_3rd_CYCLE(ROW_ADDRESS);
00375
00376     /*!< Data Read */
00377     size = NAND_SPARE_AREA_SIZE +  (NAND_SPARE_AREA_SIZE * numsparearearead);
00378
00379     /*!< Get Data into Buffer */
00380     for ( ;index < size; index++)
00381     {
00382       pBuffer[index] = *(__IO uint8_t *)(Bank_NAND_ADDR | DATA_AREA);
00383     }
00384
00385     numsparearearead++;
00386
00387     NumSpareAreaToRead--;
00388
00389     /*!< Calculate page address */
00390     addressstatus = NAND_AddressIncrement(&Address);
00391   }
00392
00393   status = NAND_GetStatus();
00394
00395   return (status | addressstatus);
00396 }
00397
00398 /**
00399   * @brief  This routine erase complete block from NAND FLASH
00400   * @param  Address: Any address into block to be erased
00401   * @retval New status of the NAND operation. This parameter can be:
00402   *              - NAND_TIMEOUT_ERROR: when the previous operation generate
00403   *                a Timeout error
00404   *              - NAND_READY: when memory is ready for the next operation
00405   */
00406 uint32_t NAND_EraseBlock(NAND_ADDRESS Address)
00407 {
00408   *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_ERASE0;
00409
00410   *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(ROW_ADDRESS);
00411   *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_2nd_CYCLE(ROW_ADDRESS);
00412   *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_3rd_CYCLE(ROW_ADDRESS);
00413
00414   *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_ERASE1;
00415
00416   return (NAND_GetStatus());
00417 }
00418
00419 /**
00420   * @brief  This routine reset the NAND FLASH.
00421   * @param  None
00422   * @retval NAND_READY
00423   */
00424 uint32_t NAND_Reset(void)
00425 {
00426   *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_RESET;
00427
00428   return (NAND_READY);
00429 }
00430
00431 /**
00432   * @brief  Get the NAND operation status.
00433   * @param  None
00434   * @retval New status of the NAND operation. This parameter can be:
00435   *              - NAND_TIMEOUT_ERROR: when the previous operation generate
00436   *                a Timeout error
00437   *              - NAND_READY: when memory is ready for the next operation
00438   */
00439 uint32_t NAND_GetStatus(void)
00440 {
00441   uint32_t timeout = 0x1000000, status = NAND_READY;
00442
00443   status = NAND_ReadStatus();
00444
00445   /*!< Wait for a NAND operation to complete or a TIMEOUT to occur */
00446   while ((status != NAND_READY) &&( timeout != 0x00))
00447   {
00448      status = NAND_ReadStatus();
00449      timeout --;
00450   }
00451
00452   if(timeout == 0x00)
00453   {
00454     status =  NAND_TIMEOUT_ERROR;
00455   }
00456
00457   /*!< Return the operation status */
00458   return (status);
00459 }
00460
00461 /**
00462   * @brief  Reads the NAND memory status using the Read status command.
00463   * @param  None
00464   * @retval The status of the NAND memory. This parameter can be:
00465   *              - NAND_BUSY: when memory is busy
00466   *              - NAND_READY: when memory is ready for the next operation
00467   *              - NAND_ERROR: when the previous operation gererates error
00468   */
00469 uint32_t NAND_ReadStatus(void)
00470 {
00471   uint32_t data = 0x00, status = NAND_BUSY;
00472
00473   /*!< Read status operation ------------------------------------ */
00474   *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_STATUS;
00475   data = *(__IO uint8_t *)(Bank_NAND_ADDR);
00476
00477   if((data & NAND_ERROR) == NAND_ERROR)
00478   {
00479     status = NAND_ERROR;
00480   }
00481   else if((data & NAND_READY) == NAND_READY)
00482   {
00483     status = NAND_READY;
00484   }
00485   else
00486   {
00487     status = NAND_BUSY;
00488   }
00489
00490   return (status);
00491 }
00492
00493 /**
00494   * @brief  Increment the NAND memory address.
00495   * @param  Address: address to be incremented.
00496   * @retval The new status of the increment address operation. It can be:
00497   *              - NAND_VALID_ADDRESS: When the new address is valid address
00498   *              - NAND_INVALID_ADDRESS: When the new address is invalid address
00499   */
00500 uint32_t NAND_AddressIncrement(NAND_ADDRESS* Address)
00501 {
00502   uint32_t status = NAND_VALID_ADDRESS;
00503
00504   Address->Page++;
00505
00506   if(Address->Page == NAND_BLOCK_SIZE)
00507   {
00508     Address->Page = 0;
00509     Address->Block++;
00510
00511     if(Address->Block == NAND_ZONE_SIZE)
00512     {
00513       Address->Block = 0;
00514       Address->Zone++;
00515
00516       if(Address->Zone == NAND_MAX_ZONE)
00517       {
00518         status = NAND_INVALID_ADDRESS;
00519       }
00520     }
00521   }
00522
00523   return (status);
00524 }
00525
00526 /**
00527   * @}
00528   */
00529
00530 /**
00531   * @}
00532   */
00533
00534 /**
00535   * @}
00536   */
00537
00538 /**
00539   * @}
00540   */
00541
00542 /**
00543   * @}
00544   */
00545
00546 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm3210e_eval_fsmc_nand.h Source File

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stm3210e_eval_fsmc_nand.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm3210e_eval_fsmc_nand.h
00004   * @author  MCD Application Team
00005   * @version V4.5.0
00006   * @date    07-March-2011
00007   * @brief   This file contains all the functions prototypes for the
00008   *          stm3210e_eval_fsmc_nand firmware driver.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00013   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00014   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00015   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00016   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00017   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00018   *
00019   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00020   ******************************************************************************
00021   */
00022
00023 /* Define to prevent recursive inclusion -------------------------------------*/
00024 #ifndef __STM3210E_EVAL_FSMC_NAND_H
00025 #define __STM3210E_EVAL_FSMC_NAND_H
00026
00027 #ifdef __cplusplus
00028  extern "C" {
00029 #endif
00030
00031 /* Includes ------------------------------------------------------------------*/
00032 #include "stm32f10x.h"
00033
00034 /** @addtogroup Utilities
00035   * @{
00036   */
00037
00038 /** @addtogroup STM32_EVAL
00039   * @{
00040   */
00041
00042 /** @addtogroup STM3210E_EVAL
00043   * @{
00044   */
00045
00046 /** @addtogroup STM3210E_EVAL_FSMC_NAND
00047   * @{
00048   */
00049
00050 /** @defgroup STM3210E_EVAL_FSMC_NAND_Exported_Types
00051   * @{
00052   */
00053 typedef struct
00054 {
00055   uint8_t Maker_ID;
00056   uint8_t Device_ID;
00057   uint8_t Third_ID;
00058   uint8_t Fourth_ID;
00059 }NAND_IDTypeDef;
00060
00061 typedef struct
00062 {
00063   uint16_t Zone;
00064   uint16_t Block;
00065   uint16_t Page;
00066 } NAND_ADDRESS;
00067 /**
00068   * @}
00069   */
00070
00071 /** @defgroup STM3210E_EVAL_FSMC_NAND_Exported_Constants
00072   * @{
00073   */
00074 /**
00075   * @brief  NAND Area definition  for STM3210E-EVAL Board RevD
00076   */
00077 #define CMD_AREA                   (uint32_t)(1<<16)  /* A16 = CLE  high */
00078 #define ADDR_AREA                  (uint32_t)(1<<17)  /* A17 = ALE high */
00079
00080 #define DATA_AREA                  ((uint32_t)0x00000000)
00081
00082 /**
00083   * @brief  FSMC NAND memory command
00084   */
00085 #define NAND_CMD_AREA_A            ((uint8_t)0x00)
00086 #define NAND_CMD_AREA_B            ((uint8_t)0x01)
00087 #define NAND_CMD_AREA_C            ((uint8_t)0x50)
00088
00089 #define NAND_CMD_WRITE0            ((uint8_t)0x80)
00090 #define NAND_CMD_WRITE_TRUE1       ((uint8_t)0x10)
00091
00092 #define NAND_CMD_ERASE0            ((uint8_t)0x60)
00093 #define NAND_CMD_ERASE1            ((uint8_t)0xD0)
00094
00095 #define NAND_CMD_READID            ((uint8_t)0x90)
00096 #define NAND_CMD_STATUS            ((uint8_t)0x70)
00097 #define NAND_CMD_LOCK_STATUS       ((uint8_t)0x7A)
00098 #define NAND_CMD_RESET             ((uint8_t)0xFF)
00099
00100 /**
00101   * @brief  NAND memory status
00102   */
00103 #define NAND_VALID_ADDRESS         ((uint32_t)0x00000100)
00104 #define NAND_INVALID_ADDRESS       ((uint32_t)0x00000200)
00105 #define NAND_TIMEOUT_ERROR         ((uint32_t)0x00000400)
00106 #define NAND_BUSY                  ((uint32_t)0x00000000)
00107 #define NAND_ERROR                 ((uint32_t)0x00000001)
00108 #define NAND_READY                 ((uint32_t)0x00000040)
00109
00110 /**
00111   * @brief  FSMC NAND memory parameters
00112   */
00113 #define NAND_PAGE_SIZE             ((uint16_t)0x0200) /* 512 bytes per page w/o Spare Area */
00114 #define NAND_BLOCK_SIZE            ((uint16_t)0x0020) /* 32x512 bytes pages per block */
00115 #define NAND_ZONE_SIZE             ((uint16_t)0x0400) /* 1024 Block per zone */
00116 #define NAND_SPARE_AREA_SIZE       ((uint16_t)0x0010) /* last 16 bytes as spare area */
00117 #define NAND_MAX_ZONE              ((uint16_t)0x0004) /* 4 zones of 1024 block */
00118
00119 /**
00120   * @brief  FSMC NAND memory address computation
00121   */
00122 #define ADDR_1st_CYCLE(ADDR)       (uint8_t)((ADDR)& 0xFF)               /* 1st addressing cycle */
00123 #define ADDR_2nd_CYCLE(ADDR)       (uint8_t)(((ADDR)& 0xFF00) >> 8)      /* 2nd addressing cycle */
00124 #define ADDR_3rd_CYCLE(ADDR)       (uint8_t)(((ADDR)& 0xFF0000) >> 16)   /* 3rd addressing cycle */
00125 #define ADDR_4th_CYCLE(ADDR)       (uint8_t)(((ADDR)& 0xFF000000) >> 24) /* 4th addressing cycle */
00126 /**
00127   * @}
00128   */
00129
00130 /** @defgroup STM3210E_EVAL_FSMC_NAND_Exported_Macros
00131   * @{
00132   */
00133 /**
00134   * @}
00135   */
00136
00137 /** @defgroup STM3210E_EVAL_FSMC_NAND_Exported_Functions
00138   * @{
00139   */
00140 void NAND_Init(void);
00141 void NAND_ReadID(NAND_IDTypeDef* NAND_ID);
00142 uint32_t NAND_WriteSmallPage(uint8_t *pBuffer, NAND_ADDRESS Address, uint32_t NumPageToWrite);
00143 uint32_t NAND_ReadSmallPage (uint8_t *pBuffer, NAND_ADDRESS Address, uint32_t NumPageToRead);
00144 uint32_t NAND_WriteSpareArea(uint8_t *pBuffer, NAND_ADDRESS Address, uint32_t NumSpareAreaTowrite);
00145 uint32_t NAND_ReadSpareArea(uint8_t *pBuffer, NAND_ADDRESS Address, uint32_t NumSpareAreaToRead);
00146 uint32_t NAND_EraseBlock(NAND_ADDRESS Address);
00147 uint32_t NAND_Reset(void);
00148 uint32_t NAND_GetStatus(void);
00149 uint32_t NAND_ReadStatus(void);
00150 uint32_t NAND_AddressIncrement(NAND_ADDRESS* Address);
00151
00152 #ifdef __cplusplus
00153 }
00154 #endif
00155
00156 #endif /* __STM3210E_EVAL_FSMC_NAND_H */
00157 /**
00158   * @}
00159   */
00160
00161 /**
00162   * @}
00163   */
00164
00165 /**
00166   * @}
00167   */
00168
00169 /**
00170   * @}
00171   */
00172
00173 /**
00174   * @}
00175   */
00176
00177 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm3210e_eval_fsmc_nor.c Source File

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  • Utilities
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  • STM3210E_EVAL

stm3210e_eval_fsmc_nor.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm3210e_eval_fsmc_nor.c
00004   * @author  MCD Application Team
00005   * @version V4.5.0
00006   * @date    07-March-2011
00007   * @brief   This file provides a set of functions needed to drive the M29W128FL,
00008   *          M29W128GL and S29GL128P NOR memories mounted on STM3210E-EVAL board.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00013   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00014   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00015   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00016   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00017   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00018   *
00019   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00020   ******************************************************************************
00021   */
00022
00023 /* Includes ------------------------------------------------------------------*/
00024 #include "stm3210e_eval_fsmc_nor.h"
00025
00026 /** @addtogroup Utilities
00027   * @{
00028   */
00029
00030 /** @addtogroup STM32_EVAL
00031   * @{
00032   */
00033
00034 /** @addtogroup STM3210E_EVAL
00035   * @{
00036   */
00037
00038 /** @addtogroup STM3210E_EVAL_FSMC_NOR
00039   * @brief      This file provides a set of functions needed to drive the M29W128FL,
00040   *             M29W128GL and S29GL128P NOR memories mounted on STM3210E-EVAL board.
00041   * @{
00042   */
00043
00044 /** @defgroup STM3210E_EVAL_FSMC_NOR_Private_Types
00045   * @{
00046   */
00047 /**
00048   * @}
00049   */
00050
00051 /** @defgroup STM3210E_EVAL_FSMC_NOR_Private_Defines
00052   * @{
00053   */
00054 /**
00055   * @brief  FSMC Bank 1 NOR/SRAM2
00056   */
00057 #define Bank1_NOR2_ADDR       ((uint32_t)0x64000000)
00058
00059 /* Delay definition */
00060 #define BlockErase_Timeout    ((uint32_t)0x00A00000)
00061 #define ChipErase_Timeout     ((uint32_t)0x30000000)
00062 #define Program_Timeout       ((uint32_t)0x00001400)
00063 /**
00064   * @}
00065   */
00066
00067
00068 /** @defgroup STM3210E_EVAL_FSMC_NOR_Private_Macros
00069   * @{
00070   */
00071 #define ADDR_SHIFT(A) (Bank1_NOR2_ADDR + (2 * (A)))
00072 #define NOR_WRITE(Address, Data)  (*(__IO uint16_t *)(Address) = (Data))
00073 /**
00074   * @}
00075   */
00076
00077
00078 /** @defgroup STM3210E_EVAL_FSMC_NOR_Private_Variables
00079   * @{
00080   */
00081 /**
00082   * @}
00083   */
00084
00085
00086 /** @defgroupSTM3210E_EVAL_FSMC_NOR_Private_Function_Prototypes
00087   * @{
00088   */
00089 /**
00090   * @}
00091   */
00092
00093
00094 /** @defgroup STM3210E_EVAL_FSMC_NOR_Private_Functions
00095   * @{
00096   */
00097
00098 /**
00099   * @brief  Configures the FSMC and GPIOs to interface with the NOR memory.
00100   *         This function must be called before any write/read operation
00101   *         on the NOR.
00102   * @param  None
00103   * @retval None
00104   */
00105 void NOR_Init(void)
00106 {
00107   FSMC_NORSRAMInitTypeDef  FSMC_NORSRAMInitStructure;
00108   FSMC_NORSRAMTimingInitTypeDef  p;
00109   GPIO_InitTypeDef GPIO_InitStructure;
00110
00111   RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOE |
00112                          RCC_APB2Periph_GPIOF | RCC_APB2Periph_GPIOG, ENABLE);
00113
00114   /*-- GPIO Configuration ------------------------------------------------------*/
00115   /*!< NOR Data lines configuration */
00116   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_8 | GPIO_Pin_9 |
00117                                 GPIO_Pin_10 | GPIO_Pin_14 | GPIO_Pin_15;
00118   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
00119   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00120   GPIO_Init(GPIOD, &GPIO_InitStructure);
00121
00122   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 |
00123                                 GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 |
00124                                 GPIO_Pin_14 | GPIO_Pin_15;
00125   GPIO_Init(GPIOE, &GPIO_InitStructure);
00126
00127   /*!< NOR Address lines configuration */
00128   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 |
00129                                 GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_12 | GPIO_Pin_13 |
00130                                 GPIO_Pin_14 | GPIO_Pin_15;
00131   GPIO_Init(GPIOF, &GPIO_InitStructure);
00132
00133   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 |
00134                                 GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5;
00135   GPIO_Init(GPIOG, &GPIO_InitStructure);
00136
00137   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13;
00138   GPIO_Init(GPIOD, &GPIO_InitStructure);
00139
00140   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_6;
00141   GPIO_Init(GPIOE, &GPIO_InitStructure);
00142
00143   /*!< NOE and NWE configuration */
00144   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4 | GPIO_Pin_5;
00145   GPIO_Init(GPIOD, &GPIO_InitStructure);
00146
00147   /*!< NE2 configuration */
00148   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;
00149   GPIO_Init(GPIOG, &GPIO_InitStructure);
00150
00151   /*!< Configure PD6 for NOR memory Ready/Busy signal */
00152   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
00153   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
00154   GPIO_Init(GPIOD, &GPIO_InitStructure);
00155
00156   /*-- FSMC Configuration ----------------------------------------------------*/
00157   p.FSMC_AddressSetupTime = 0x02;
00158   p.FSMC_AddressHoldTime = 0x00;
00159   p.FSMC_DataSetupTime = 0x05;
00160   p.FSMC_BusTurnAroundDuration = 0x00;
00161   p.FSMC_CLKDivision = 0x00;
00162   p.FSMC_DataLatency = 0x00;
00163   p.FSMC_AccessMode = FSMC_AccessMode_B;
00164
00165   FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2;
00166   FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
00167   FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_NOR;
00168   FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
00169   FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
00170   FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
00171   FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
00172   FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
00173   FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
00174   FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
00175   FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
00176   FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
00177   FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
00178   FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
00179   FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
00180
00181   FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);
00182
00183   /*!< Enable FSMC Bank1_NOR Bank */
00184   FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM2, ENABLE);
00185 }
00186
00187 /**
00188   * @brief  Reads NOR memory's Manufacturer and Device Code.
00189   * @param  NOR_ID: pointer to a NOR_IDTypeDef structure which will hold the
00190   *         Manufacturer and Device Code.
00191   * @retval None
00192   */
00193 void NOR_ReadID(NOR_IDTypeDef* NOR_ID)
00194 {
00195   NOR_WRITE(ADDR_SHIFT(0x0555), 0x00AA);
00196   NOR_WRITE(ADDR_SHIFT(0x02AA), 0x0055);
00197   NOR_WRITE(ADDR_SHIFT(0x0555), 0x0090);
00198
00199   NOR_ID->Manufacturer_Code = *(__IO uint16_t *) ADDR_SHIFT(0x0000);
00200   NOR_ID->Device_Code1 = *(__IO uint16_t *) ADDR_SHIFT(0x0001);
00201   NOR_ID->Device_Code2 = *(__IO uint16_t *) ADDR_SHIFT(0x000E);
00202   NOR_ID->Device_Code3 = *(__IO uint16_t *) ADDR_SHIFT(0x000F);
00203 }
00204
00205 /**
00206   * @brief  Erases the specified Nor memory block.
00207   * @param  BlockAddr: address of the block to erase.
00208   * @retval NOR_Status: The returned value can be: NOR_SUCCESS, NOR_ERROR
00209   *         or NOR_TIMEOUT
00210   */
00211 NOR_Status NOR_EraseBlock(uint32_t BlockAddr)
00212 {
00213   NOR_WRITE(ADDR_SHIFT(0x0555), 0x00AA);
00214   NOR_WRITE(ADDR_SHIFT(0x02AA), 0x0055);
00215   NOR_WRITE(ADDR_SHIFT(0x0555), 0x0080);
00216   NOR_WRITE(ADDR_SHIFT(0x0555), 0x00AA);
00217   NOR_WRITE(ADDR_SHIFT(0x02AA), 0x0055);
00218   NOR_WRITE((Bank1_NOR2_ADDR + BlockAddr), 0x30);
00219
00220   return (NOR_GetStatus(BlockErase_Timeout));
00221 }
00222
00223 /**
00224   * @brief  Erases the entire chip.
00225   * @param  None
00226   * @retval NOR_Status: The returned value can be: NOR_SUCCESS, NOR_ERROR
00227   *         or NOR_TIMEOUT
00228   */
00229 NOR_Status NOR_EraseChip(void)
00230 {
00231   NOR_WRITE(ADDR_SHIFT(0x0555), 0x00AA);
00232   NOR_WRITE(ADDR_SHIFT(0x02AA), 0x0055);
00233   NOR_WRITE(ADDR_SHIFT(0x0555), 0x0080);
00234   NOR_WRITE(ADDR_SHIFT(0x0555), 0x00AA);
00235   NOR_WRITE(ADDR_SHIFT(0x02AA), 0x0055);
00236   NOR_WRITE(ADDR_SHIFT(0x0555), 0x0010);
00237
00238   return (NOR_GetStatus(ChipErase_Timeout));
00239 }
00240
00241 /**
00242   * @brief  Writes a half-word to the NOR memory.
00243   * @param  WriteAddr: NOR memory internal address to write to.
00244   * @param  Data: Data to write.
00245   * @retval NOR_Status: The returned value can be: NOR_SUCCESS, NOR_ERROR
00246   *         or NOR_TIMEOUT
00247   */
00248 NOR_Status NOR_WriteHalfWord(uint32_t WriteAddr, uint16_t Data)
00249 {
00250   NOR_WRITE(ADDR_SHIFT(0x0555), 0x00AA);
00251   NOR_WRITE(ADDR_SHIFT(0x02AA), 0x0055);
00252   NOR_WRITE(ADDR_SHIFT(0x0555), 0x00A0);
00253   NOR_WRITE((Bank1_NOR2_ADDR + WriteAddr), Data);
00254
00255   return (NOR_GetStatus(Program_Timeout));
00256 }
00257
00258 /**
00259   * @brief  Writes a half-word buffer to the FSMC NOR memory.
00260   * @param  pBuffer: pointer to buffer.
00261   * @param  WriteAddr: NOR memory internal address from which the data will be
00262   *         written.
00263   * @param  NumHalfwordToWrite: number of Half words to write.
00264   * @retval NOR_Status: The returned value can be: NOR_SUCCESS, NOR_ERROR
00265   *         or NOR_TIMEOUT
00266   */
00267 NOR_Status NOR_WriteBuffer(uint16_t* pBuffer, uint32_t WriteAddr, uint32_t NumHalfwordToWrite)
00268 {
00269   NOR_Status status = NOR_ONGOING;
00270
00271   do
00272   {
00273     /*!< Transfer data to the memory */
00274     status = NOR_WriteHalfWord(WriteAddr, *pBuffer++);
00275     WriteAddr = WriteAddr + 2;
00276     NumHalfwordToWrite--;
00277   }
00278   while((status == NOR_SUCCESS) && (NumHalfwordToWrite != 0));
00279
00280   return (status);
00281 }
00282
00283 /**
00284   * @brief  Writes a half-word buffer to the FSMC NOR memory. This function
00285   *         must be used only with S29GL128P NOR memory.
00286   * @param  pBuffer: pointer to buffer.
00287   * @param  WriteAddr: NOR memory internal address from which the data will be
00288   *         written.
00289   * @param  NumHalfwordToWrite: number of Half words to write.
00290   *         The maximum allowed value is 32 Half words (64 bytes).
00291   * @retval NOR_Status: The returned value can be: NOR_SUCCESS, NOR_ERROR
00292   *         or NOR_TIMEOUT
00293   */
00294 NOR_Status NOR_ProgramBuffer(uint16_t* pBuffer, uint32_t WriteAddr, uint32_t NumHalfwordToWrite)
00295 {
00296   uint32_t lastloadedaddress = 0x00;
00297   uint32_t currentaddress = 0x00;
00298   uint32_t endaddress = 0x00;
00299
00300   /*!< Initialize variables */
00301   currentaddress = WriteAddr;
00302   endaddress = WriteAddr + NumHalfwordToWrite - 1;
00303   lastloadedaddress = WriteAddr;
00304
00305   /*!< Issue unlock command sequence */
00306   NOR_WRITE(ADDR_SHIFT(0x00555), 0x00AA);
00307
00308   NOR_WRITE(ADDR_SHIFT(0x02AA), 0x0055);
00309
00310   /*!< Write Write Buffer Load Command */
00311   NOR_WRITE(ADDR_SHIFT(WriteAddr), 0x0025);
00312   NOR_WRITE(ADDR_SHIFT(WriteAddr), (NumHalfwordToWrite - 1));
00313
00314   /*!< Load Data into NOR Buffer */
00315   while(currentaddress <= endaddress)
00316   {
00317     /*!< Store last loaded address & data value (for polling) */
00318     lastloadedaddress = currentaddress;
00319
00320     NOR_WRITE(ADDR_SHIFT(currentaddress), *pBuffer++);
00321     currentaddress += 1;
00322   }
00323
00324   NOR_WRITE(ADDR_SHIFT(lastloadedaddress), 0x29);
00325
00326   return(NOR_GetStatus(Program_Timeout));
00327 }
00328
00329 /**
00330   * @brief  Reads a half-word from the NOR memory.
00331   * @param  ReadAddr: NOR memory internal address to read from.
00332   * @retval Half-word read from the NOR memory
00333   */
00334 uint16_t NOR_ReadHalfWord(uint32_t ReadAddr)
00335 {
00336   NOR_WRITE(ADDR_SHIFT(0x00555), 0x00AA);
00337   NOR_WRITE(ADDR_SHIFT(0x002AA), 0x0055);
00338   NOR_WRITE((Bank1_NOR2_ADDR + ReadAddr), 0x00F0 );
00339
00340   return (*(__IO uint16_t *)((Bank1_NOR2_ADDR + ReadAddr)));
00341 }
00342
00343 /**
00344   * @brief  Reads a block of data from the FSMC NOR memory.
00345   * @param  pBuffer: pointer to the buffer that receives the data read from the
00346   *         NOR memory.
00347   * @param  ReadAddr: NOR memory internal address to read from.
00348   * @param  NumHalfwordToRead : number of Half word to read.
00349   * @retval None
00350   */
00351 void NOR_ReadBuffer(uint16_t* pBuffer, uint32_t ReadAddr, uint32_t NumHalfwordToRead)
00352 {
00353   NOR_WRITE(ADDR_SHIFT(0x0555), 0x00AA);
00354   NOR_WRITE(ADDR_SHIFT(0x02AA), 0x0055);
00355   NOR_WRITE((Bank1_NOR2_ADDR + ReadAddr), 0x00F0);
00356
00357   for(; NumHalfwordToRead != 0x00; NumHalfwordToRead--) /*!< while there is data to read */
00358   {
00359     /*!< Read a Halfword from the NOR */
00360     *pBuffer++ = *(__IO uint16_t *)((Bank1_NOR2_ADDR + ReadAddr));
00361     ReadAddr = ReadAddr + 2;
00362   }
00363 }
00364
00365 /**
00366   * @brief  Returns the NOR memory to Read mode.
00367   * @param  None
00368   * @retval NOR_SUCCESS
00369   */
00370 NOR_Status NOR_ReturnToReadMode(void)
00371 {
00372   NOR_WRITE(Bank1_NOR2_ADDR, 0x00F0);
00373
00374   return (NOR_SUCCESS);
00375 }
00376
00377 /**
00378   * @brief  Returns the NOR memory to Read mode and resets the errors in the NOR
00379   *         memory Status Register.
00380   * @param  None
00381   * @retval NOR_SUCCESS
00382   */
00383 NOR_Status NOR_Reset(void)
00384 {
00385   NOR_WRITE(ADDR_SHIFT(0x00555), 0x00AA);
00386   NOR_WRITE(ADDR_SHIFT(0x002AA), 0x0055);
00387   NOR_WRITE(Bank1_NOR2_ADDR, 0x00F0);
00388
00389   return (NOR_SUCCESS);
00390 }
00391
00392 /**
00393   * @brief  Returns the NOR operation status.
00394   * @param  Timeout: NOR progamming Timeout
00395   * @retval NOR_Status: The returned value can be: NOR_SUCCESS, NOR_ERROR
00396   *         or NOR_TIMEOUT
00397   */
00398 NOR_Status NOR_GetStatus(uint32_t Timeout)
00399 {
00400   uint16_t val1 = 0x00, val2 = 0x00;
00401   NOR_Status status = NOR_ONGOING;
00402   uint32_t timeout = Timeout;
00403
00404   /*!< Poll on NOR memory Ready/Busy signal ----------------------------------*/
00405   while((GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_6) != RESET) && (timeout > 0))
00406   {
00407     timeout--;
00408   }
00409
00410   timeout = Timeout;
00411
00412   while((GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_6) == RESET) && (timeout > 0))
00413   {
00414     timeout--;
00415   }
00416
00417   /*!< Get the NOR memory operation status -----------------------------------*/
00418   while((Timeout != 0x00) && (status != NOR_SUCCESS))
00419   {
00420     Timeout--;
00421
00422     /*!< Read DQ6 and DQ5 */
00423     val1 = *(__IO uint16_t *)(Bank1_NOR2_ADDR);
00424     val2 = *(__IO uint16_t *)(Bank1_NOR2_ADDR);
00425
00426     /*!< If DQ6 did not toggle between the two reads then return NOR_Success */
00427     if((val1 & 0x0040) == (val2 & 0x0040))
00428     {
00429       return NOR_SUCCESS;
00430     }
00431
00432     if((val1 & 0x0020) != 0x0020)
00433     {
00434       status = NOR_ONGOING;
00435     }
00436
00437     val1 = *(__IO uint16_t *)(Bank1_NOR2_ADDR);
00438     val2 = *(__IO uint16_t *)(Bank1_NOR2_ADDR);
00439
00440     if((val1 & 0x0040) == (val2 & 0x0040))
00441     {
00442       return NOR_SUCCESS;
00443     }
00444     else if((val1 & 0x0020) == 0x0020)
00445     {
00446       return NOR_ERROR;
00447     }
00448   }
00449
00450   if(Timeout == 0x00)
00451   {
00452     status = NOR_TIMEOUT;
00453   }
00454
00455   /*!< Return the operation status */
00456   return (status);
00457 }
00458
00459 /**
00460   * @}
00461   */
00462
00463 /**
00464   * @}
00465   */
00466
00467 /**
00468   * @}
00469   */
00470
00471 /**
00472   * @}
00473   */
00474
00475 /**
00476   * @}
00477   */
00478
00479 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm3210e_eval_fsmc_nor.h Source File

  • File List
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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • STM3210E_EVAL

stm3210e_eval_fsmc_nor.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm3210e_eval_fsmc_nor.h
00004   * @author  MCD Application Team
00005   * @version V4.5.0
00006   * @date    07-March-2011
00007   * @brief   This file contains all the functions prototypes for the
00008   *          stm3210e_eval_fsmc_nor firmware driver.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00013   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00014   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00015   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00016   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00017   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00018   *
00019   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00020   ******************************************************************************
00021   */
00022
00023 /* Define to prevent recursive inclusion -------------------------------------*/
00024 #ifndef __STM3210E_EVAL_FSMC_NOR_H
00025 #define __STM3210E_EVAL_FSMC_NOR_H
00026
00027 #ifdef __cplusplus
00028  extern "C" {
00029 #endif
00030
00031 /* Includes ------------------------------------------------------------------*/
00032 #include "stm32f10x.h"
00033
00034 /** @addtogroup Utilities
00035   * @{
00036   */
00037
00038 /** @addtogroup STM32_EVAL
00039   * @{
00040   */
00041
00042 /** @addtogroup STM3210E_EVAL
00043   * @{
00044   */
00045
00046 /** @addtogroup STM3210E_EVAL_FSMC_NOR
00047   * @{
00048   */
00049
00050 /** @defgroup STM3210E_EVAL_FSMC_NOR_Exported_Types
00051   * @{
00052   */
00053 typedef struct
00054 {
00055   uint16_t Manufacturer_Code;
00056   uint16_t Device_Code1;
00057   uint16_t Device_Code2;
00058   uint16_t Device_Code3;
00059 }NOR_IDTypeDef;
00060
00061 /* NOR Status */
00062 typedef enum
00063 {
00064   NOR_SUCCESS = 0,
00065   NOR_ONGOING,
00066   NOR_ERROR,
00067   NOR_TIMEOUT
00068 }NOR_Status;
00069 /**
00070   * @}
00071   */
00072
00073 /** @defgroup STM3210E_EVAL_FSMC_NOR_Exported_Constants
00074   * @{
00075   */
00076 /**
00077   * @}
00078   */
00079
00080 /** @defgroup STM3210E_EVAL_FSMC_NOR_Exported_Macros
00081   * @{
00082   */
00083 /**
00084   * @}
00085   */
00086
00087 /** @defgroup STM3210E_EVAL_FSMC_NOR_Exported_Functions
00088   * @{
00089   */
00090 void NOR_Init(void);
00091 void NOR_ReadID(NOR_IDTypeDef* NOR_ID);
00092 NOR_Status NOR_EraseBlock(uint32_t BlockAddr);
00093 NOR_Status NOR_EraseChip(void);
00094 NOR_Status NOR_WriteHalfWord(uint32_t WriteAddr, uint16_t Data);
00095 NOR_Status NOR_WriteBuffer(uint16_t* pBuffer, uint32_t WriteAddr, uint32_t NumHalfwordToWrite);
00096 NOR_Status NOR_ProgramBuffer(uint16_t* pBuffer, uint32_t WriteAddr, uint32_t NumHalfwordToWrite);
00097 uint16_t NOR_ReadHalfWord(uint32_t ReadAddr);
00098 void NOR_ReadBuffer(uint16_t* pBuffer, uint32_t ReadAddr, uint32_t NumHalfwordToRead);
00099 NOR_Status NOR_ReturnToReadMode(void);
00100 NOR_Status NOR_Reset(void);
00101 NOR_Status NOR_GetStatus(uint32_t Timeout);
00102
00103 #ifdef __cplusplus
00104 }
00105 #endif
00106
00107 #endif /* __STM3210E_EVAL_FSMC_NOR_H */
00108 /**
00109   * @}
00110   */
00111
00112 /**
00113   * @}
00114   */
00115
00116 /**
00117   * @}
00118   */
00119
00120 /**
00121   * @}
00122   */
00123
00124 /**
00125   * @}
00126   */
00127
00128 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm3210e_eval_fsmc_sram.c Source File

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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • STM3210E_EVAL

stm3210e_eval_fsmc_sram.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm3210e_eval_fsmc_sram.c
00004   * @author  MCD Application Team
00005   * @version V4.5.0
00006   * @date    07-March-2011
00007   * @brief   This file provides a set of functions needed to drive the
00008   *          IS61WV51216BLL SRAM memory mounted on STM3210E-EVAL board.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00013   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00014   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00015   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00016   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00017   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00018   *
00019   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00020   ******************************************************************************
00021   */
00022
00023 /* Includes ------------------------------------------------------------------*/
00024 #include "stm3210e_eval_fsmc_sram.h"
00025
00026 /** @addtogroup Utilities
00027   * @{
00028   */
00029
00030 /** @addtogroup STM32_EVAL
00031   * @{
00032   */
00033
00034 /** @addtogroup STM3210E_EVAL
00035   * @{
00036   */
00037
00038 /** @addtogroup STM3210E_EVAL_FSMC_SRAM
00039   * @brief      This file provides a set of functions needed to drive the
00040   *             IS61WV51216BLL SRAM memory mounted on STM3210E-EVAL board.
00041   * @{
00042   */
00043
00044 /** @defgroup STM3210E_EVAL_FSMC_SRAM_Private_Types
00045   * @{
00046   */
00047 /**
00048   * @}
00049   */
00050
00051
00052 /** @defgroup STM3210E_EVAL_FSMC_SRAM_Private_Defines
00053   * @{
00054   */
00055 /**
00056   * @brief  FSMC Bank 1 NOR/SRAM3
00057   */
00058 #define Bank1_SRAM3_ADDR    ((uint32_t)0x68000000)
00059 /**
00060   * @}
00061   */
00062
00063
00064 /** @defgroup STM3210E_EVAL_FSMC_SRAM_Private_Macros
00065   * @{
00066   */
00067 /**
00068   * @}
00069   */
00070
00071
00072 /** @defgroup STM3210E_EVAL_FSMC_SRAM_Private_Variables
00073   * @{
00074   */
00075 /**
00076   * @}
00077   */
00078
00079
00080 /** @defgroup STM3210E_EVAL_FSMC_SRAM_Private_Function_Prototypes
00081   * @{
00082   */
00083 /**
00084   * @}
00085   */
00086
00087
00088 /** @defgroup STM3210E_EVAL_FSMC_SRAM_Private_Functions
00089   * @{
00090   */
00091
00092 /**
00093   * @brief  Configures the FSMC and GPIOs to interface with the SRAM memory.
00094   *         This function must be called before any write/read operation
00095   *         on the SRAM.
00096   * @param  None
00097   * @retval None
00098   */
00099 void SRAM_Init(void)
00100 {
00101   FSMC_NORSRAMInitTypeDef  FSMC_NORSRAMInitStructure;
00102   FSMC_NORSRAMTimingInitTypeDef  p;
00103   GPIO_InitTypeDef GPIO_InitStructure;
00104
00105   RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOG | RCC_APB2Periph_GPIOE |
00106                          RCC_APB2Periph_GPIOF, ENABLE);
00107
00108 /*-- GPIO Configuration ------------------------------------------------------*/
00109   /*!< SRAM Data lines configuration */
00110   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_8 | GPIO_Pin_9 |
00111                                 GPIO_Pin_10 | GPIO_Pin_14 | GPIO_Pin_15;
00112   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
00113   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00114   GPIO_Init(GPIOD, &GPIO_InitStructure);
00115
00116   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 |
00117                                 GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 |
00118                                 GPIO_Pin_15;
00119   GPIO_Init(GPIOE, &GPIO_InitStructure);
00120
00121   /*!< SRAM Address lines configuration */
00122   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 |
00123                                 GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_12 | GPIO_Pin_13 |
00124                                 GPIO_Pin_14 | GPIO_Pin_15;
00125   GPIO_Init(GPIOF, &GPIO_InitStructure);
00126
00127   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 |
00128                                 GPIO_Pin_4 | GPIO_Pin_5;
00129   GPIO_Init(GPIOG, &GPIO_InitStructure);
00130
00131   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13;
00132   GPIO_Init(GPIOD, &GPIO_InitStructure);
00133
00134   /*!< NOE and NWE configuration */
00135   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4 |GPIO_Pin_5;
00136   GPIO_Init(GPIOD, &GPIO_InitStructure);
00137
00138   /*!< NE3 configuration */
00139   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10;
00140   GPIO_Init(GPIOG, &GPIO_InitStructure);
00141
00142   /*!< NBL0, NBL1 configuration */
00143   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1;
00144   GPIO_Init(GPIOE, &GPIO_InitStructure);
00145
00146 /*-- FSMC Configuration ------------------------------------------------------*/
00147   p.FSMC_AddressSetupTime = 0;
00148   p.FSMC_AddressHoldTime = 0;
00149   p.FSMC_DataSetupTime = 1;
00150   p.FSMC_BusTurnAroundDuration = 0;
00151   p.FSMC_CLKDivision = 0;
00152   p.FSMC_DataLatency = 0;
00153   p.FSMC_AccessMode = FSMC_AccessMode_A;
00154
00155   FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM3;
00156   FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
00157   FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM;
00158   FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
00159   FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
00160   FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
00161   FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
00162   FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
00163   FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
00164   FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
00165   FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
00166   FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
00167   FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
00168   FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
00169   FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
00170
00171   FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);
00172
00173   /*!< Enable FSMC Bank1_SRAM Bank */
00174   FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM3, ENABLE);
00175 }
00176
00177 /**
00178   * @brief  Writes a Half-word buffer to the FSMC SRAM memory.
00179   * @param  pBuffer : pointer to buffer.
00180   * @param  WriteAddr : SRAM memory internal address from which the data will be
00181   *         written.
00182   * @param  NumHalfwordToWrite : number of half-words to write.
00183   * @retval None
00184   */
00185 void SRAM_WriteBuffer(uint16_t* pBuffer, uint32_t WriteAddr, uint32_t NumHalfwordToWrite)
00186 {
00187   for(; NumHalfwordToWrite != 0; NumHalfwordToWrite--) /*!< while there is data to write */
00188   {
00189     /*!< Transfer data to the memory */
00190     *(uint16_t *) (Bank1_SRAM3_ADDR + WriteAddr) = *pBuffer++;
00191
00192     /*!< Increment the address*/
00193     WriteAddr += 2;
00194   }
00195 }
00196
00197 /**
00198   * @brief  Reads a block of data from the FSMC SRAM memory.
00199   * @param  pBuffer : pointer to the buffer that receives the data read from the
00200   *         SRAM memory.
00201   * @param  ReadAddr : SRAM memory internal address to read from.
00202   * @param  NumHalfwordToRead : number of half-words to read.
00203   * @retval None
00204   */
00205 void SRAM_ReadBuffer(uint16_t* pBuffer, uint32_t ReadAddr, uint32_t NumHalfwordToRead)
00206 {
00207   for(; NumHalfwordToRead != 0; NumHalfwordToRead--) /*!< while there is data to read */
00208   {
00209     /*!< Read a half-word from the memory */
00210     *pBuffer++ = *(__IO uint16_t*) (Bank1_SRAM3_ADDR + ReadAddr);
00211
00212     /*!< Increment the address*/
00213     ReadAddr += 2;
00214   }
00215 }
00216
00217 /**
00218   * @}
00219   */
00220
00221 /**
00222   * @}
00223   */
00224
00225 /**
00226   * @}
00227   */
00228
00229 /**
00230   * @}
00231   */
00232
00233 /**
00234   * @}
00235   */
00236
00237 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm3210e_eval_fsmc_sram.h Source File

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • STM3210E_EVAL

stm3210e_eval_fsmc_sram.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm3210e_eval_fsmc_sram.h
00004   * @author  MCD Application Team
00005   * @version V4.5.0
00006   * @date    07-March-2011
00007   * @brief   This file contains all the functions prototypes for the
00008   *          stm3210e_eval_fsmc_sram firmware driver.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00013   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00014   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00015   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00016   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00017   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00018   *
00019   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00020   ******************************************************************************
00021   */
00022
00023 /* Define to prevent recursive inclusion -------------------------------------*/
00024 #ifndef __STM3210E_EVAL_FSMC_SRAM_H
00025 #define __STM3210E_EVAL_FSMC_SRAM_H
00026
00027 #ifdef __cplusplus
00028  extern "C" {
00029 #endif
00030
00031 /* Includes ------------------------------------------------------------------*/
00032 #include "stm32f10x.h"
00033
00034 /** @addtogroup Utilities
00035   * @{
00036   */
00037
00038 /** @addtogroup STM32_EVAL
00039   * @{
00040   */
00041
00042 /** @addtogroup STM3210E_EVAL
00043   * @{
00044   */
00045
00046 /** @addtogroup STM3210E_EVAL_FSMC_SRAM
00047   * @{
00048   */
00049
00050 /** @defgroup STM3210E_EVAL_FSMC_SRAM_Exported_Types
00051   * @{
00052   */
00053 /**
00054   * @}
00055   */
00056
00057 /** @defgroup STM3210E_EVAL_FSMC_SRAM_Exported_Constants
00058   * @{
00059   */
00060 /**
00061   * @}
00062   */
00063
00064 /** @defgroup STM3210E_EVAL_FSMC_SRAM_Exported_Macros
00065   * @{
00066   */
00067 /**
00068   * @}
00069   */
00070
00071 /** @defgroup STM3210E_EVAL_FSMC_SRAM_Exported_Functions
00072   * @{
00073   */
00074
00075 void SRAM_Init(void);
00076 void SRAM_WriteBuffer(uint16_t* pBuffer, uint32_t WriteAddr, uint32_t NumHalfwordToWrite);
00077 void SRAM_ReadBuffer(uint16_t* pBuffer, uint32_t ReadAddr, uint32_t NumHalfwordToRead);
00078
00079 #ifdef __cplusplus
00080 }
00081 #endif
00082
00083 #endif /* __STM3210E_EVAL_FSMC_SRAM_H */
00084 /**
00085   * @}
00086   */
00087
00088 /**
00089   * @}
00090   */
00091
00092 /**
00093   * @}
00094   */
00095
00096 /**
00097   * @}
00098   */
00099
00100 /**
00101   * @}
00102   */
00103
00104 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm3210e_eval_lcd.c Source File

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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • STM3210E_EVAL

stm3210e_eval_lcd.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm3210e_eval_lcd.c
00004   * @author  MCD Application Team
00005   * @version V4.5.0
00006   * @date    07-March-2011
00007   * @brief   This file includes the LCD driver for AM-240320L8TNQW00H
00008   *          (LCD_ILI9320) and AM-240320LDTNQW00H (LCD_SPFD5408B) Liquid Crystal
00009   *          Display Module of STM3210E-EVAL board.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm3210e_eval_lcd.h"
00026 #include "../Common/fonts.c"
00027
00028 /** @addtogroup Utilities
00029   * @{
00030   */
00031
00032 /** @addtogroup STM32_EVAL
00033   * @{
00034   */
00035
00036 /** @addtogroup STM3210E_EVAL
00037   * @{
00038   */
00039
00040 /** @defgroup STM3210E_EVAL_LCD
00041   * @brief This file includes the LCD driver for AM-240320L8TNQW00H
00042   *        (LCD_ILI9320) and AM-240320LDTNQW00H (LCD_SPFD5408B) Liquid Crystal
00043   *        Display Module of STM3210E-EVAL board.
00044   * @{
00045   */
00046
00047 /** @defgroup STM3210E_EVAL_LCD_Private_TypesDefinitions
00048   * @{
00049   */
00050 typedef struct
00051 {
00052   __IO uint16_t LCD_REG;
00053   __IO uint16_t LCD_RAM;
00054 } LCD_TypeDef;
00055 /**
00056   * @}
00057   */
00058
00059
00060 /** @defgroup STM3210E_EVAL_LCD_Private_Defines
00061   * @{
00062   */
00063 /* Note: LCD /CS is CE4 - Bank 4 of NOR/SRAM Bank 1~4 */
00064 #define LCD_BASE           ((uint32_t)(0x60000000 | 0x0C000000))
00065 #define LCD                ((LCD_TypeDef *) LCD_BASE)
00066 #define MAX_POLY_CORNERS   200
00067 #define POLY_Y(Z)          ((int32_t)((Points + Z)->X))
00068 #define POLY_X(Z)          ((int32_t)((Points + Z)->Y))
00069 /**
00070   * @}
00071   */
00072
00073 /** @defgroup STM3210E_EVAL_LCD_Private_Macros
00074   * @{
00075   */
00076 #define ABS(X)  ((X) > 0 ? (X) : -(X))
00077 /**
00078   * @}
00079   */
00080
00081 /** @defgroup STM3210E_EVAL_LCD_Private_Variables
00082   * @{
00083   */
00084 static sFONT *LCD_Currentfonts;
00085 /* Global variables to set the written text color */
00086 static  __IO uint16_t TextColor = 0x0000, BackColor = 0xFFFF;
00087
00088 /**
00089   * @}
00090   */
00091
00092
00093 /** @defgroup STM3210E_EVAL_LCD_Private_FunctionPrototypes
00094   * @{
00095   */
00096 #ifndef USE_Delay
00097 static void delay(vu32 nCount);
00098 #endif /* USE_Delay*/
00099 static void PutPixel(int16_t x, int16_t y);
00100 static void LCD_PolyLineRelativeClosed(pPoint Points, uint16_t PointCount, uint16_t Closed);
00101 /**
00102   * @}
00103   */
00104
00105
00106 /** @defgroup STM3210E_EVAL_LCD_Private_Functions
00107   * @{
00108   */
00109
00110 /**
00111   * @brief  DeInitializes the LCD.
00112   * @param  None
00113   * @retval None
00114   */
00115 void LCD_DeInit(void)
00116 {
00117   GPIO_InitTypeDef GPIO_InitStructure;
00118
00119   /*!< LCD Display Off */
00120   LCD_DisplayOff();
00121
00122   /* BANK 4 (of NOR/SRAM Bank 1~4) is disabled */
00123   FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM4, ENABLE);
00124
00125   /*!< LCD_SPI DeInit */
00126   FSMC_NORSRAMDeInit(FSMC_Bank1_NORSRAM4);
00127
00128   /* Set PD.00(D2), PD.01(D3), PD.04(NOE), PD.05(NWE), PD.08(D13), PD.09(D14),
00129      PD.10(D15), PD.14(D0), PD.15(D1) as input floating */
00130   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_4 | GPIO_Pin_5 |
00131                                 GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_14 |
00132                                 GPIO_Pin_15;
00133   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
00134   GPIO_Init(GPIOD, &GPIO_InitStructure);
00135   /* Set PE.07(D4), PE.08(D5), PE.09(D6), PE.10(D7), PE.11(D8), PE.12(D9), PE.13(D10),
00136      PE.14(D11), PE.15(D12) as alternate function push pull */
00137   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 |
00138                                 GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 |
00139                                 GPIO_Pin_15;
00140   GPIO_Init(GPIOE, &GPIO_InitStructure);
00141   /* Set PF.00(A0 (RS)) as alternate function push pull */
00142   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0;
00143   GPIO_Init(GPIOF, &GPIO_InitStructure);
00144   /* Set PG.12(NE4 (LCD/CS)) as alternate function push pull - CE3(LCD /CS) */
00145   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12;
00146   GPIO_Init(GPIOG, &GPIO_InitStructure);
00147 }
00148
00149 /**
00150   * @brief  Initializes the LCD.
00151   * @param  None
00152   * @retval None
00153   */
00154 void STM3210E_LCD_Init(void)
00155 {
00156 /* Configure the LCD Control pins --------------------------------------------*/
00157   LCD_CtrlLinesConfig();
00158 /* Configure the FSMC Parallel interface -------------------------------------*/
00159   LCD_FSMCConfig();
00160
00161   _delay_(5); /* delay 50 ms */
00162   /* Check if the LCD is SPFD5408B Controller */
00163   if(LCD_ReadReg(0x00) == 0x5408)
00164   {
00165     /* Start Initial Sequence ------------------------------------------------*/
00166     LCD_WriteReg(LCD_REG_1, 0x0100);  /* Set SS bit */
00167     LCD_WriteReg(LCD_REG_2, 0x0700);  /* Set 1 line inversion */
00168     LCD_WriteReg(LCD_REG_3, 0x1030);  /* Set GRAM write direction and BGR=1. */
00169     LCD_WriteReg(LCD_REG_4, 0x0000);  /* Resize register */
00170     LCD_WriteReg(LCD_REG_8, 0x0202);  /* Set the back porch and front porch */
00171     LCD_WriteReg(LCD_REG_9, 0x0000);  /* Set non-display area refresh cycle ISC[3:0] */
00172     LCD_WriteReg(LCD_REG_10, 0x0000); /* FMARK function */
00173     LCD_WriteReg(LCD_REG_12, 0x0000); /* RGB 18-bit System interface setting */
00174     LCD_WriteReg(LCD_REG_13, 0x0000); /* Frame marker Position */
00175     LCD_WriteReg(LCD_REG_15, 0x0000); /* RGB interface polarity, no impact */
00176     /* Power On sequence -----------------------------------------------------*/
00177     LCD_WriteReg(LCD_REG_16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
00178     LCD_WriteReg(LCD_REG_17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */
00179     LCD_WriteReg(LCD_REG_18, 0x0000); /* VREG1OUT voltage */
00180     LCD_WriteReg(LCD_REG_19, 0x0000); /* VDV[4:0] for VCOM amplitude */
00181     _delay_(20);                 /* Dis-charge capacitor power voltage (200ms) */
00182     LCD_WriteReg(LCD_REG_17, 0x0007);  /* DC1[2:0], DC0[2:0], VC[2:0] */
00183     _delay_(5);                   /* Delay 50 ms */
00184     LCD_WriteReg(LCD_REG_16, 0x12B0);  /* SAP, BT[3:0], AP, DSTB, SLP, STB */
00185     _delay_(5);                  /* Delay 50 ms */
00186     LCD_WriteReg(LCD_REG_18, 0x01BD);  /* External reference voltage= Vci */
00187     _delay_(5);
00188     LCD_WriteReg(LCD_REG_19, 0x1400);  /* VDV[4:0] for VCOM amplitude */
00189     LCD_WriteReg(LCD_REG_41, 0x000E);  /* VCM[4:0] for VCOMH */
00190     _delay_(5);                   /* Delay 50 ms */
00191     LCD_WriteReg(LCD_REG_32, 0x0000); /* GRAM horizontal Address */
00192     LCD_WriteReg(LCD_REG_33, 0x013F); /* GRAM Vertical Address */
00193     /* Adjust the Gamma Curve (SPFD5408B)-------------------------------------*/
00194     LCD_WriteReg(LCD_REG_48, 0x0b0d);
00195     LCD_WriteReg(LCD_REG_49, 0x1923);
00196     LCD_WriteReg(LCD_REG_50, 0x1c26);
00197     LCD_WriteReg(LCD_REG_51, 0x261c);
00198     LCD_WriteReg(LCD_REG_52, 0x2419);
00199     LCD_WriteReg(LCD_REG_53, 0x0d0b);
00200     LCD_WriteReg(LCD_REG_54, 0x1006);
00201     LCD_WriteReg(LCD_REG_55, 0x0610);
00202     LCD_WriteReg(LCD_REG_56, 0x0706);
00203     LCD_WriteReg(LCD_REG_57, 0x0304);
00204     LCD_WriteReg(LCD_REG_58, 0x0e05);
00205     LCD_WriteReg(LCD_REG_59, 0x0e01);
00206     LCD_WriteReg(LCD_REG_60, 0x010e);
00207     LCD_WriteReg(LCD_REG_61, 0x050e);
00208     LCD_WriteReg(LCD_REG_62, 0x0403);
00209     LCD_WriteReg(LCD_REG_63, 0x0607);
00210     /* Set GRAM area ---------------------------------------------------------*/
00211     LCD_WriteReg(LCD_REG_80, 0x0000); /* Horizontal GRAM Start Address */
00212     LCD_WriteReg(LCD_REG_81, 0x00EF); /* Horizontal GRAM End Address */
00213     LCD_WriteReg(LCD_REG_82, 0x0000); /* Vertical GRAM Start Address */
00214     LCD_WriteReg(LCD_REG_83, 0x013F); /* Vertical GRAM End Address */
00215     LCD_WriteReg(LCD_REG_96,  0xA700); /* Gate Scan Line */
00216     LCD_WriteReg(LCD_REG_97,  0x0001); /* NDL, VLE, REV */
00217     LCD_WriteReg(LCD_REG_106, 0x0000); /* set scrolling line */
00218     /* Partial Display Control -----------------------------------------------*/
00219     LCD_WriteReg(LCD_REG_128, 0x0000);
00220     LCD_WriteReg(LCD_REG_129, 0x0000);
00221     LCD_WriteReg(LCD_REG_130, 0x0000);
00222     LCD_WriteReg(LCD_REG_131, 0x0000);
00223     LCD_WriteReg(LCD_REG_132, 0x0000);
00224     LCD_WriteReg(LCD_REG_133, 0x0000);
00225     /* Panel Control ---------------------------------------------------------*/
00226     LCD_WriteReg(LCD_REG_144, 0x0010);
00227     LCD_WriteReg(LCD_REG_146, 0x0000);
00228     LCD_WriteReg(LCD_REG_147, 0x0003);
00229     LCD_WriteReg(LCD_REG_149, 0x0110);
00230     LCD_WriteReg(LCD_REG_151, 0x0000);
00231     LCD_WriteReg(LCD_REG_152, 0x0000);
00232     /* Set GRAM write direction and BGR=1
00233        I/D=01 (Horizontal : increment, Vertical : decrement)
00234        AM=1 (address is updated in vertical writing direction) */
00235     LCD_WriteReg(LCD_REG_3, 0x1018);
00236     LCD_WriteReg(LCD_REG_7, 0x0112); /* 262K color and display ON */
00237     LCD_SetFont(&LCD_DEFAULT_FONT);
00238     return;
00239   }
00240 /* Start Initial Sequence ----------------------------------------------------*/
00241   LCD_WriteReg(LCD_REG_229,0x8000); /* Set the internal vcore voltage */
00242   LCD_WriteReg(LCD_REG_0,  0x0001); /* Start internal OSC. */
00243   LCD_WriteReg(LCD_REG_1,  0x0100); /* set SS and SM bit */
00244   LCD_WriteReg(LCD_REG_2,  0x0700); /* set 1 line inversion */
00245   LCD_WriteReg(LCD_REG_3,  0x1030); /* set GRAM write direction and BGR=1. */
00246   LCD_WriteReg(LCD_REG_4,  0x0000); /* Resize register */
00247   LCD_WriteReg(LCD_REG_8,  0x0202); /* set the back porch and front porch */
00248   LCD_WriteReg(LCD_REG_9,  0x0000); /* set non-display area refresh cycle ISC[3:0] */
00249   LCD_WriteReg(LCD_REG_10, 0x0000); /* FMARK function */
00250   LCD_WriteReg(LCD_REG_12, 0x0000); /* RGB interface setting */
00251   LCD_WriteReg(LCD_REG_13, 0x0000); /* Frame marker Position */
00252   LCD_WriteReg(LCD_REG_15, 0x0000); /* RGB interface polarity */
00253 /* Power On sequence ---------------------------------------------------------*/
00254   LCD_WriteReg(LCD_REG_16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
00255   LCD_WriteReg(LCD_REG_17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */
00256   LCD_WriteReg(LCD_REG_18, 0x0000); /* VREG1OUT voltage */
00257   LCD_WriteReg(LCD_REG_19, 0x0000); /* VDV[4:0] for VCOM amplitude */
00258   _delay_(20);                 /* Dis-charge capacitor power voltage (200ms) */
00259   LCD_WriteReg(LCD_REG_16, 0x17B0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
00260   LCD_WriteReg(LCD_REG_17, 0x0137); /* DC1[2:0], DC0[2:0], VC[2:0] */
00261   _delay_(5);                  /* Delay 50 ms */
00262   LCD_WriteReg(LCD_REG_18, 0x0139); /* VREG1OUT voltage */
00263   _delay_(5);                  /* Delay 50 ms */
00264   LCD_WriteReg(LCD_REG_19, 0x1d00); /* VDV[4:0] for VCOM amplitude */
00265   LCD_WriteReg(LCD_REG_41, 0x0013); /* VCM[4:0] for VCOMH */
00266   _delay_(5);                  /* Delay 50 ms */
00267   LCD_WriteReg(LCD_REG_32, 0x0000); /* GRAM horizontal Address */
00268   LCD_WriteReg(LCD_REG_33, 0x0000); /* GRAM Vertical Address */
00269 /* Adjust the Gamma Curve ----------------------------------------------------*/
00270   LCD_WriteReg(LCD_REG_48, 0x0006);
00271   LCD_WriteReg(LCD_REG_49, 0x0101);
00272   LCD_WriteReg(LCD_REG_50, 0x0003);
00273   LCD_WriteReg(LCD_REG_53, 0x0106);
00274   LCD_WriteReg(LCD_REG_54, 0x0b02);
00275   LCD_WriteReg(LCD_REG_55, 0x0302);
00276   LCD_WriteReg(LCD_REG_56, 0x0707);
00277   LCD_WriteReg(LCD_REG_57, 0x0007);
00278   LCD_WriteReg(LCD_REG_60, 0x0600);
00279   LCD_WriteReg(LCD_REG_61, 0x020b);
00280
00281 /* Set GRAM area -------------------------------------------------------------*/
00282   LCD_WriteReg(LCD_REG_80, 0x0000); /* Horizontal GRAM Start Address */
00283   LCD_WriteReg(LCD_REG_81, 0x00EF); /* Horizontal GRAM End Address */
00284   LCD_WriteReg(LCD_REG_82, 0x0000); /* Vertical GRAM Start Address */
00285   LCD_WriteReg(LCD_REG_83, 0x013F); /* Vertical GRAM End Address */
00286   LCD_WriteReg(LCD_REG_96,  0x2700); /* Gate Scan Line */
00287   LCD_WriteReg(LCD_REG_97,  0x0001); /* NDL,VLE, REV */
00288   LCD_WriteReg(LCD_REG_106, 0x0000); /* set scrolling line */
00289 /* Partial Display Control ---------------------------------------------------*/
00290   LCD_WriteReg(LCD_REG_128, 0x0000);
00291   LCD_WriteReg(LCD_REG_129, 0x0000);
00292   LCD_WriteReg(LCD_REG_130, 0x0000);
00293   LCD_WriteReg(LCD_REG_131, 0x0000);
00294   LCD_WriteReg(LCD_REG_132, 0x0000);
00295   LCD_WriteReg(LCD_REG_133, 0x0000);
00296 /* Panel Control -------------------------------------------------------------*/
00297   LCD_WriteReg(LCD_REG_144, 0x0010);
00298   LCD_WriteReg(LCD_REG_146, 0x0000);
00299   LCD_WriteReg(LCD_REG_147, 0x0003);
00300   LCD_WriteReg(LCD_REG_149, 0x0110);
00301   LCD_WriteReg(LCD_REG_151, 0x0000);
00302   LCD_WriteReg(LCD_REG_152, 0x0000);
00303   /* Set GRAM write direction and BGR = 1 */
00304   /* I/D=01 (Horizontal : increment, Vertical : decrement) */
00305   /* AM=1 (address is updated in vertical writing direction) */
00306   LCD_WriteReg(LCD_REG_3, 0x1018);
00307   LCD_WriteReg(LCD_REG_7, 0x0173); /* 262K color and display ON */
00308   LCD_SetFont(&LCD_DEFAULT_FONT);
00309 }
00310
00311 /**
00312   * @brief  Sets the LCD Text and Background colors.
00313   * @param  _TextColor: specifies the Text Color.
00314   * @param  _BackColor: specifies the Background Color.
00315   * @retval None
00316   */
00317 void LCD_SetColors(__IO uint16_t _TextColor, __IO uint16_t _BackColor)
00318 {
00319   TextColor = _TextColor;
00320   BackColor = _BackColor;
00321 }
00322
00323 /**
00324   * @brief  Gets the LCD Text and Background colors.
00325   * @param  _TextColor: pointer to the variable that will contain the Text
00326             Color.
00327   * @param  _BackColor: pointer to the variable that will contain the Background
00328             Color.
00329   * @retval None
00330   */
00331 void LCD_GetColors(__IO uint16_t *_TextColor, __IO uint16_t *_BackColor)
00332 {
00333   *_TextColor = TextColor; *_BackColor = BackColor;
00334 }
00335
00336 /**
00337   * @brief  Sets the Text color.
00338   * @param  Color: specifies the Text color code RGB(5-6-5).
00339   * @retval None
00340   */
00341 void LCD_SetTextColor(__IO uint16_t Color)
00342 {
00343   TextColor = Color;
00344 }
00345
00346
00347 /**
00348   * @brief  Sets the Background color.
00349   * @param  Color: specifies the Background color code RGB(5-6-5).
00350   * @retval None
00351   */
00352 void LCD_SetBackColor(__IO uint16_t Color)
00353 {
00354   BackColor = Color;
00355 }
00356
00357 /**
00358   * @brief  Sets the Text Font.
00359   * @param  fonts: specifies the font to be used.
00360   * @retval None
00361   */
00362 void LCD_SetFont(sFONT *fonts)
00363 {
00364   LCD_Currentfonts = fonts;
00365 }
00366
00367 /**
00368   * @brief  Gets the Text Font.
00369   * @param  None.
00370   * @retval the used font.
00371   */
00372 sFONT *LCD_GetFont(void)
00373 {
00374   return LCD_Currentfonts;
00375 }
00376
00377 /**
00378   * @brief  Clears the selected line.
00379   * @param  Line: the Line to be cleared.
00380   *   This parameter can be one of the following values:
00381   *     @arg Linex: where x can be 0..n
00382   * @retval None
00383   */
00384 void LCD_ClearLine(uint8_t Line)
00385 {
00386   uint16_t refcolumn = LCD_PIXEL_WIDTH - 1;
00387   /* Send the string character by character on lCD */
00388   while (((refcolumn + 1)&0xFFFF) >= LCD_Currentfonts->Width)
00389   {
00390     /* Display one character on LCD */
00391     LCD_DisplayChar(Line, refcolumn, ' ');
00392     /* Decrement the column position by 16 */
00393     refcolumn -= LCD_Currentfonts->Width;
00394   }
00395 }
00396
00397
00398 /**
00399   * @brief  Clears the hole LCD.
00400   * @param  Color: the color of the background.
00401   * @retval None
00402   */
00403 void LCD_Clear(uint16_t Color)
00404 {
00405   uint32_t index = 0;
00406
00407   LCD_SetCursor(0x00, 0x013F);
00408   LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
00409   for(index = 0; index < 76800; index++)
00410   {
00411     LCD->LCD_RAM = Color;
00412   }
00413 }
00414
00415
00416 /**
00417   * @brief  Sets the cursor position.
00418   * @param  Xpos: specifies the X position.
00419   * @param  Ypos: specifies the Y position.
00420   * @retval None
00421   */
00422 void LCD_SetCursor(uint8_t Xpos, uint16_t Ypos)
00423 {
00424   LCD_WriteReg(LCD_REG_32, Xpos);
00425   LCD_WriteReg(LCD_REG_33, Ypos);
00426 }
00427
00428
00429 /**
00430   * @brief  Draws a character on LCD.
00431   * @param  Xpos: the Line where to display the character shape.
00432   * @param  Ypos: start column address.
00433   * @param  c: pointer to the character data.
00434   * @retval None
00435   */
00436 void LCD_DrawChar(uint8_t Xpos, uint16_t Ypos, const uint16_t *c)
00437 {
00438   uint32_t index = 0, i = 0;
00439   uint8_t Xaddress = 0;
00440
00441   Xaddress = Xpos;
00442
00443   LCD_SetCursor(Xaddress, Ypos);
00444
00445   for(index = 0; index < LCD_Currentfonts->Height; index++)
00446   {
00447     LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
00448     for(i = 0; i < LCD_Currentfonts->Width; i++)
00449     {
00450       if((((c[index] & ((0x80 << ((LCD_Currentfonts->Width / 12 ) * 8 ) ) >> i)) == 0x00) &&(LCD_Currentfonts->Width <= 12))||
00451         (((c[index] & (0x1 << i)) == 0x00)&&(LCD_Currentfonts->Width > 12 )))
00452
00453       {
00454         LCD_WriteRAM(BackColor);
00455       }
00456       else
00457       {
00458         LCD_WriteRAM(TextColor);
00459       }
00460     }
00461     Xaddress++;
00462     LCD_SetCursor(Xaddress, Ypos);
00463   }
00464 }
00465
00466
00467 /**
00468   * @brief  Displays one character (16dots width, 24dots height).
00469   * @param  Line: the Line where to display the character shape .
00470   *   This parameter can be one of the following values:
00471   *     @arg Linex: where x can be 0..9
00472   * @param  Column: start column address.
00473   * @param  Ascii: character ascii code, must be between 0x20 and 0x7E.
00474   * @retval None
00475   */
00476 void LCD_DisplayChar(uint8_t Line, uint16_t Column, uint8_t Ascii)
00477 {
00478   Ascii -= 32;
00479   LCD_DrawChar(Line, Column, &LCD_Currentfonts->table[Ascii * LCD_Currentfonts->Height]);
00480 }
00481
00482
00483 /**
00484   * @brief  Displays a maximum of 20 char on the LCD.
00485   * @param  Line: the Line where to display the character shape .
00486   *   This parameter can be one of the following values:
00487   *     @arg Linex: where x can be 0..9
00488   * @param  *ptr: pointer to string to display on LCD.
00489   * @retval None
00490   */
00491 void LCD_DisplayStringLine(uint8_t Line, uint8_t *ptr)
00492 {
00493   uint16_t refcolumn = LCD_PIXEL_WIDTH - 1;
00494
00495   /* Send the string character by character on lCD */
00496   while ((*ptr != 0) & (((refcolumn + 1) & 0xFFFF) >= LCD_Currentfonts->Width))
00497   {
00498     /* Display one character on LCD */
00499     LCD_DisplayChar(Line, refcolumn, *ptr);
00500     /* Decrement the column position by 16 */
00501     refcolumn -= LCD_Currentfonts->Width;
00502     /* Point on the next character */
00503     ptr++;
00504   }
00505 }
00506
00507
00508 /**
00509   * @brief  Sets a display window
00510   * @param  Xpos: specifies the X buttom left position.
00511   * @param  Ypos: specifies the Y buttom left position.
00512   * @param  Height: display window height.
00513   * @param  Width: display window width.
00514   * @retval None
00515   */
00516 void LCD_SetDisplayWindow(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width)
00517 {
00518   /* Horizontal GRAM Start Address */
00519   if(Xpos >= Height)
00520   {
00521     LCD_WriteReg(LCD_REG_80, (Xpos - Height + 1));
00522   }
00523   else
00524   {
00525     LCD_WriteReg(LCD_REG_80, 0);
00526   }
00527   /* Horizontal GRAM End Address */
00528   LCD_WriteReg(LCD_REG_81, Xpos);
00529   /* Vertical GRAM Start Address */
00530   if(Ypos >= Width)
00531   {
00532     LCD_WriteReg(LCD_REG_82, (Ypos - Width + 1));
00533   }
00534   else
00535   {
00536     LCD_WriteReg(LCD_REG_82, 0);
00537   }
00538   /* Vertical GRAM End Address */
00539   LCD_WriteReg(LCD_REG_83, Ypos);
00540   LCD_SetCursor(Xpos, Ypos);
00541 }
00542
00543
00544 /**
00545   * @brief  Disables LCD Window mode.
00546   * @param  None
00547   * @retval None
00548   */
00549 void LCD_WindowModeDisable(void)
00550 {
00551   LCD_SetDisplayWindow(239, 0x13F, 240, 320);
00552   LCD_WriteReg(LCD_REG_3, 0x1018);
00553 }
00554
00555
00556 /**
00557   * @brief  Displays a line.
00558   * @param Xpos: specifies the X position.
00559   * @param Ypos: specifies the Y position.
00560   * @param Length: line length.
00561   * @param Direction: line direction.
00562   *   This parameter can be one of the following values: Vertical or Horizontal.
00563   * @retval None
00564   */
00565 void LCD_DrawLine(uint8_t Xpos, uint16_t Ypos, uint16_t Length, uint8_t Direction)
00566 {
00567   uint32_t i = 0;
00568
00569   LCD_SetCursor(Xpos, Ypos);
00570   if(Direction == LCD_DIR_HORIZONTAL)
00571   {
00572     LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
00573     for(i = 0; i < Length; i++)
00574     {
00575       LCD_WriteRAM(TextColor);
00576     }
00577   }
00578   else
00579   {
00580     for(i = 0; i < Length; i++)
00581     {
00582       LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
00583       LCD_WriteRAM(TextColor);
00584       Xpos++;
00585       LCD_SetCursor(Xpos, Ypos);
00586     }
00587   }
00588 }
00589
00590
00591 /**
00592   * @brief  Displays a rectangle.
00593   * @param  Xpos: specifies the X position.
00594   * @param  Ypos: specifies the Y position.
00595   * @param  Height: display rectangle height.
00596   * @param  Width: display rectangle width.
00597   * @retval None
00598   */
00599 void LCD_DrawRect(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width)
00600 {
00601   LCD_DrawLine(Xpos, Ypos, Width, LCD_DIR_HORIZONTAL);
00602   LCD_DrawLine((Xpos + Height), Ypos, Width, LCD_DIR_HORIZONTAL);
00603
00604   LCD_DrawLine(Xpos, Ypos, Height, LCD_DIR_VERTICAL);
00605   LCD_DrawLine(Xpos, (Ypos - Width + 1), Height, LCD_DIR_VERTICAL);
00606 }
00607
00608
00609 /**
00610   * @brief  Displays a circle.
00611   * @param  Xpos: specifies the X position.
00612   * @param  Ypos: specifies the Y position.
00613   * @param  Radius
00614   * @retval None
00615   */
00616 void LCD_DrawCircle(uint8_t Xpos, uint16_t Ypos, uint16_t Radius)
00617 {
00618   int32_t  D;/* Decision Variable */
00619   uint32_t  CurX;/* Current X Value */
00620   uint32_t  CurY;/* Current Y Value */
00621
00622   D = 3 - (Radius << 1);
00623   CurX = 0;
00624   CurY = Radius;
00625
00626   while (CurX <= CurY)
00627   {
00628     LCD_SetCursor(Xpos + CurX, Ypos + CurY);
00629     LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
00630     LCD_WriteRAM(TextColor);
00631     LCD_SetCursor(Xpos + CurX, Ypos - CurY);
00632     LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
00633     LCD_WriteRAM(TextColor);
00634     LCD_SetCursor(Xpos - CurX, Ypos + CurY);
00635     LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
00636     LCD_WriteRAM(TextColor);
00637     LCD_SetCursor(Xpos - CurX, Ypos - CurY);
00638     LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
00639     LCD_WriteRAM(TextColor);
00640     LCD_SetCursor(Xpos + CurY, Ypos + CurX);
00641     LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
00642     LCD_WriteRAM(TextColor);
00643     LCD_SetCursor(Xpos + CurY, Ypos - CurX);
00644     LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
00645     LCD_WriteRAM(TextColor);
00646     LCD_SetCursor(Xpos - CurY, Ypos + CurX);
00647     LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
00648     LCD_WriteRAM(TextColor);
00649     LCD_SetCursor(Xpos - CurY, Ypos - CurX);
00650     LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
00651     LCD_WriteRAM(TextColor);
00652     if (D < 0)
00653     {
00654       D += (CurX << 2) + 6;
00655     }
00656     else
00657     {
00658       D += ((CurX - CurY) << 2) + 10;
00659       CurY--;
00660     }
00661     CurX++;
00662   }
00663 }
00664
00665
00666 /**
00667   * @brief  Displays a monocolor picture.
00668   * @param  Pict: pointer to the picture array.
00669   * @retval None
00670   */
00671 void LCD_DrawMonoPict(const uint32_t *Pict)
00672 {
00673   uint32_t index = 0, i = 0;
00674   LCD_SetCursor(0, (LCD_PIXEL_WIDTH - 1));
00675   LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
00676   for(index = 0; index < 2400; index++)
00677   {
00678     for(i = 0; i < 32; i++)
00679     {
00680       if((Pict[index] & (1 << i)) == 0x00)
00681       {
00682         LCD_WriteRAM(BackColor);
00683       }
00684       else
00685       {
00686         LCD_WriteRAM(TextColor);
00687       }
00688     }
00689   }
00690 }
00691
00692
00693 /**
00694   * @brief  Displays a bitmap picture loaded in the internal Flash.
00695   * @param  BmpAddress: Bmp picture address in the internal Flash.
00696   * @retval None
00697   */
00698 void LCD_WriteBMP(uint32_t BmpAddress)
00699 {
00700   uint32_t index = 0, size = 0;
00701   /* Read bitmap size */
00702   size = *(__IO uint16_t *) (BmpAddress + 2);
00703   size |= (*(__IO uint16_t *) (BmpAddress + 4)) << 16;
00704   /* Get bitmap data address offset */
00705   index = *(__IO uint16_t *) (BmpAddress + 10);
00706   index |= (*(__IO uint16_t *) (BmpAddress + 12)) << 16;
00707   size = (size - index)/2;
00708   BmpAddress += index;
00709   /* Set GRAM write direction and BGR = 1 */
00710   /* I/D=00 (Horizontal : decrement, Vertical : decrement) */
00711   /* AM=1 (address is updated in vertical writing direction) */
00712   LCD_WriteReg(LCD_REG_3, 0x1008);
00713
00714   LCD_WriteRAM_Prepare();
00715
00716   for(index = 0; index < size; index++)
00717   {
00718     LCD_WriteRAM(*(__IO uint16_t *)BmpAddress);
00719     BmpAddress += 2;
00720   }
00721
00722   /* Set GRAM write direction and BGR = 1 */
00723   /* I/D = 01 (Horizontal : increment, Vertical : decrement) */
00724   /* AM = 1 (address is updated in vertical writing direction) */
00725   LCD_WriteReg(LCD_REG_3, 0x1018);
00726 }
00727
00728 /**
00729   * @brief  Displays a full rectangle.
00730   * @param  Xpos: specifies the X position.
00731   * @param  Ypos: specifies the Y position.
00732   * @param  Height: rectangle height.
00733   * @param  Width: rectangle width.
00734   * @retval None
00735   */
00736 void LCD_DrawFullRect(uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height)
00737 {
00738   LCD_SetTextColor(TextColor);
00739
00740   LCD_DrawLine(Xpos, Ypos, Width, LCD_DIR_HORIZONTAL);
00741   LCD_DrawLine((Xpos + Height), Ypos, Width, LCD_DIR_HORIZONTAL);
00742
00743   LCD_DrawLine(Xpos, Ypos, Height, LCD_DIR_VERTICAL);
00744   LCD_DrawLine(Xpos, (Ypos - Width + 1), Height, LCD_DIR_VERTICAL);
00745
00746   Width -= 2;
00747   Height--;
00748   Ypos--;
00749
00750   LCD_SetTextColor(BackColor);
00751
00752   while(Height--)
00753   {
00754     LCD_DrawLine(++Xpos, Ypos, Width, LCD_DIR_HORIZONTAL);
00755   }
00756
00757   LCD_SetTextColor(TextColor);
00758 }
00759
00760 /**
00761   * @brief  Displays a full circle.
00762   * @param  Xpos: specifies the X position.
00763   * @param  Ypos: specifies the Y position.
00764   * @param  Radius
00765   * @retval None
00766   */
00767 void LCD_DrawFullCircle(uint16_t Xpos, uint16_t Ypos, uint16_t Radius)
00768 {
00769   int32_t  D;    /* Decision Variable */
00770   uint32_t  CurX;/* Current X Value */
00771   uint32_t  CurY;/* Current Y Value */
00772
00773   D = 3 - (Radius << 1);
00774
00775   CurX = 0;
00776   CurY = Radius;
00777
00778   LCD_SetTextColor(BackColor);
00779
00780   while (CurX <= CurY)
00781   {
00782     if(CurY > 0)
00783     {
00784       LCD_DrawLine(Xpos - CurX, Ypos + CurY, 2*CurY, LCD_DIR_HORIZONTAL);
00785       LCD_DrawLine(Xpos + CurX, Ypos + CurY, 2*CurY, LCD_DIR_HORIZONTAL);
00786     }
00787
00788     if(CurX > 0)
00789     {
00790       LCD_DrawLine(Xpos - CurY, Ypos + CurX, 2*CurX, LCD_DIR_HORIZONTAL);
00791       LCD_DrawLine(Xpos + CurY, Ypos + CurX, 2*CurX, LCD_DIR_HORIZONTAL);
00792     }
00793     if (D < 0)
00794     {
00795       D += (CurX << 2) + 6;
00796     }
00797     else
00798     {
00799       D += ((CurX - CurY) << 2) + 10;
00800       CurY--;
00801     }
00802     CurX++;
00803   }
00804
00805   LCD_SetTextColor(TextColor);
00806   LCD_DrawCircle(Xpos, Ypos, Radius);
00807 }
00808
00809 /**
00810   * @brief  Displays an uni line (between two points).
00811   * @param  x1: specifies the point 1 x position.
00812   * @param  y1: specifies the point 1 y position.
00813   * @param  x2: specifies the point 2 x position.
00814   * @param  y2: specifies the point 2 y position.
00815   * @retval None
00816   */
00817 void LCD_DrawUniLine(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2)
00818 {
00819   int16_t deltax = 0, deltay = 0, x = 0, y = 0, xinc1 = 0, xinc2 = 0,
00820   yinc1 = 0, yinc2 = 0, den = 0, num = 0, numadd = 0, numpixels = 0,
00821   curpixel = 0;
00822
00823   deltax = ABS(x2 - x1);        /* The difference between the x's */
00824   deltay = ABS(y2 - y1);        /* The difference between the y's */
00825   x = x1;                       /* Start x off at the first pixel */
00826   y = y1;                       /* Start y off at the first pixel */
00827
00828   if (x2 >= x1)                 /* The x-values are increasing */
00829   {
00830     xinc1 = 1;
00831     xinc2 = 1;
00832   }
00833   else                          /* The x-values are decreasing */
00834   {
00835     xinc1 = -1;
00836     xinc2 = -1;
00837   }
00838
00839   if (y2 >= y1)                 /* The y-values are increasing */
00840   {
00841     yinc1 = 1;
00842     yinc2 = 1;
00843   }
00844   else                          /* The y-values are decreasing */
00845   {
00846     yinc1 = -1;
00847     yinc2 = -1;
00848   }
00849
00850   if (deltax >= deltay)         /* There is at least one x-value for every y-value */
00851   {
00852     xinc1 = 0;                  /* Don't change the x when numerator >= denominator */
00853     yinc2 = 0;                  /* Don't change the y for every iteration */
00854     den = deltax;
00855     num = deltax / 2;
00856     numadd = deltay;
00857     numpixels = deltax;         /* There are more x-values than y-values */
00858   }
00859   else                          /* There is at least one y-value for every x-value */
00860   {
00861     xinc2 = 0;                  /* Don't change the x for every iteration */
00862     yinc1 = 0;                  /* Don't change the y when numerator >= denominator */
00863     den = deltay;
00864     num = deltay / 2;
00865     numadd = deltax;
00866     numpixels = deltay;         /* There are more y-values than x-values */
00867   }
00868
00869   for (curpixel = 0; curpixel <= numpixels; curpixel++)
00870   {
00871     PutPixel(x, y);             /* Draw the current pixel */
00872     num += numadd;              /* Increase the numerator by the top of the fraction */
00873     if (num >= den)             /* Check if numerator >= denominator */
00874     {
00875       num -= den;               /* Calculate the new numerator value */
00876       x += xinc1;               /* Change the x as appropriate */
00877       y += yinc1;               /* Change the y as appropriate */
00878     }
00879     x += xinc2;                 /* Change the x as appropriate */
00880     y += yinc2;                 /* Change the y as appropriate */
00881   }
00882 }
00883
00884 /**
00885   * @brief  Displays an polyline (between many points).
00886   * @param  Points: pointer to the points array.
00887   * @param  PointCount: Number of points.
00888   * @retval None
00889   */
00890 void LCD_PolyLine(pPoint Points, uint16_t PointCount)
00891 {
00892   int16_t X = 0, Y = 0;
00893
00894   if(PointCount < 2)
00895   {
00896     return;
00897   }
00898
00899   while(--PointCount)
00900   {
00901     X = Points->X;
00902     Y = Points->Y;
00903     Points++;
00904     LCD_DrawUniLine(X, Y, Points->X, Points->Y);
00905   }
00906 }
00907
00908 /**
00909   * @brief  Displays an relative polyline (between many points).
00910   * @param  Points: pointer to the points array.
00911   * @param  PointCount: Number of points.
00912   * @param  Closed: specifies if the draw is closed or not.
00913   *           1: closed, 0 : not closed.
00914   * @retval None
00915   */
00916 static void LCD_PolyLineRelativeClosed(pPoint Points, uint16_t PointCount, uint16_t Closed)
00917 {
00918   int16_t X = 0, Y = 0;
00919   pPoint First = Points;
00920
00921   if(PointCount < 2)
00922   {
00923     return;
00924   }
00925   X = Points->X;
00926   Y = Points->Y;
00927   while(--PointCount)
00928   {
00929     Points++;
00930     LCD_DrawUniLine(X, Y, X + Points->X, Y + Points->Y);
00931     X = X + Points->X;
00932     Y = Y + Points->Y;
00933   }
00934   if(Closed)
00935   {
00936     LCD_DrawUniLine(First->X, First->Y, X, Y);
00937   }
00938 }
00939
00940 /**
00941   * @brief  Displays a closed polyline (between many points).
00942   * @param  Points: pointer to the points array.
00943   * @param  PointCount: Number of points.
00944   * @retval None
00945   */
00946 void LCD_ClosedPolyLine(pPoint Points, uint16_t PointCount)
00947 {
00948   LCD_PolyLine(Points, PointCount);
00949   LCD_DrawUniLine(Points->X, Points->Y, (Points+PointCount-1)->X, (Points+PointCount-1)->Y);
00950 }
00951
00952 /**
00953   * @brief  Displays a relative polyline (between many points).
00954   * @param  Points: pointer to the points array.
00955   * @param  PointCount: Number of points.
00956   * @retval None
00957   */
00958 void LCD_PolyLineRelative(pPoint Points, uint16_t PointCount)
00959 {
00960   LCD_PolyLineRelativeClosed(Points, PointCount, 0);
00961 }
00962
00963 /**
00964   * @brief  Displays a closed relative polyline (between many points).
00965   * @param  Points: pointer to the points array.
00966   * @param  PointCount: Number of points.
00967   * @retval None
00968   */
00969 void LCD_ClosedPolyLineRelative(pPoint Points, uint16_t PointCount)
00970 {
00971   LCD_PolyLineRelativeClosed(Points, PointCount, 1);
00972 }
00973
00974
00975 /**
00976   * @brief  Displays a  full polyline (between many points).
00977   * @param  Points: pointer to the points array.
00978   * @param  PointCount: Number of points.
00979   * @retval None
00980   */
00981 void LCD_FillPolyLine(pPoint Points, uint16_t PointCount)
00982 {
00983   /*  public-domain code by Darel Rex Finley, 2007 */
00984   uint16_t  nodes = 0, nodeX[MAX_POLY_CORNERS], pixelX = 0, pixelY = 0, i = 0,
00985   j = 0, swap = 0;
00986   uint16_t  IMAGE_LEFT = 0, IMAGE_RIGHT = 0, IMAGE_TOP = 0, IMAGE_BOTTOM = 0;
00987
00988   IMAGE_LEFT = IMAGE_RIGHT = Points->X;
00989   IMAGE_TOP= IMAGE_BOTTOM = Points->Y;
00990
00991   for(i = 1; i < PointCount; i++)
00992   {
00993     pixelX = POLY_X(i);
00994     if(pixelX < IMAGE_LEFT)
00995     {
00996       IMAGE_LEFT = pixelX;
00997     }
00998     if(pixelX > IMAGE_RIGHT)
00999     {
01000       IMAGE_RIGHT = pixelX;
01001     }
01002
01003     pixelY = POLY_Y(i);
01004     if(pixelY < IMAGE_TOP)
01005     {
01006       IMAGE_TOP = pixelY;
01007     }
01008     if(pixelY > IMAGE_BOTTOM)
01009     {
01010       IMAGE_BOTTOM = pixelY;
01011     }
01012   }
01013
01014   LCD_SetTextColor(BackColor);
01015
01016   /*  Loop through the rows of the image. */
01017   for (pixelY = IMAGE_TOP; pixelY < IMAGE_BOTTOM; pixelY++)
01018   {
01019     /* Build a list of nodes. */
01020     nodes = 0; j = PointCount-1;
01021
01022     for (i = 0; i < PointCount; i++)
01023     {
01024       if (POLY_Y(i)<(double) pixelY && POLY_Y(j)>=(double) pixelY || POLY_Y(j)<(double) pixelY && POLY_Y(i)>=(double) pixelY)
01025       {
01026         nodeX[nodes++]=(int) (POLY_X(i)+((pixelY-POLY_Y(i))*(POLY_X(j)-POLY_X(i)))/(POLY_Y(j)-POLY_Y(i)));
01027       }
01028       j = i;
01029     }
01030
01031     /* Sort the nodes, via a simple "Bubble" sort. */
01032     i = 0;
01033     while (i < nodes-1)
01034     {
01035       if (nodeX[i]>nodeX[i+1])
01036       {
01037         swap = nodeX[i];
01038         nodeX[i] = nodeX[i+1];
01039         nodeX[i+1] = swap;
01040         if(i)
01041         {
01042           i--;
01043         }
01044       }
01045       else
01046       {
01047         i++;
01048       }
01049     }
01050
01051     /*  Fill the pixels between node pairs. */
01052     for (i = 0; i < nodes; i+=2)
01053     {
01054       if(nodeX[i] >= IMAGE_RIGHT)
01055       {
01056         break;
01057       }
01058       if(nodeX[i+1] > IMAGE_LEFT)
01059       {
01060         if (nodeX[i] < IMAGE_LEFT)
01061         {
01062           nodeX[i]=IMAGE_LEFT;
01063         }
01064         if(nodeX[i+1] > IMAGE_RIGHT)
01065         {
01066           nodeX[i+1] = IMAGE_RIGHT;
01067         }
01068         LCD_SetTextColor(BackColor);
01069         LCD_DrawLine(pixelY, nodeX[i+1], nodeX[i+1] - nodeX[i], LCD_DIR_HORIZONTAL);
01070         LCD_SetTextColor(TextColor);
01071         PutPixel(pixelY, nodeX[i+1]);
01072         PutPixel(pixelY, nodeX[i]);
01073         /* for (j=nodeX[i]; j<nodeX[i+1]; j++) PutPixel(j,pixelY); */
01074       }
01075     }
01076   }
01077
01078   /* draw the edges */
01079   LCD_SetTextColor(TextColor);
01080 }
01081
01082 /**
01083   * @brief  Writes to the selected LCD register.
01084   * @param  LCD_Reg: address of the selected register.
01085   * @param  LCD_RegValue: value to write to the selected register.
01086   * @retval None
01087   */
01088 void LCD_WriteReg(uint8_t LCD_Reg, uint16_t LCD_RegValue)
01089 {
01090   /* Write 16-bit Index, then Write Reg */
01091   LCD->LCD_REG = LCD_Reg;
01092   /* Write 16-bit Reg */
01093   LCD->LCD_RAM = LCD_RegValue;
01094 }
01095
01096
01097 /**
01098   * @brief  Reads the selected LCD Register.
01099   * @param  LCD_Reg: address of the selected register.
01100   * @retval LCD Register Value.
01101   */
01102 uint16_t LCD_ReadReg(uint8_t LCD_Reg)
01103 {
01104   /* Write 16-bit Index (then Read Reg) */
01105   LCD->LCD_REG = LCD_Reg;
01106   /* Read 16-bit Reg */
01107   return (LCD->LCD_RAM);
01108 }
01109
01110
01111 /**
01112   * @brief  Prepare to write to the LCD RAM.
01113   * @param  None
01114   * @retval None
01115   */
01116 void LCD_WriteRAM_Prepare(void)
01117 {
01118   LCD->LCD_REG = LCD_REG_34;
01119 }
01120
01121
01122 /**
01123   * @brief  Writes to the LCD RAM.
01124   * @param  RGB_Code: the pixel color in RGB mode (5-6-5).
01125   * @retval None
01126   */
01127 void LCD_WriteRAM(uint16_t RGB_Code)
01128 {
01129   /* Write 16-bit GRAM Reg */
01130   LCD->LCD_RAM = RGB_Code;
01131 }
01132
01133
01134 /**
01135   * @brief  Reads the LCD RAM.
01136   * @param  None
01137   * @retval LCD RAM Value.
01138   */
01139 uint16_t LCD_ReadRAM(void)
01140 {
01141   /* Write 16-bit Index (then Read Reg) */
01142   LCD->LCD_REG = LCD_REG_34; /* Select GRAM Reg */
01143   /* Read 16-bit Reg */
01144   return LCD->LCD_RAM;
01145 }
01146
01147
01148 /**
01149   * @brief  Power on the LCD.
01150   * @param  None
01151   * @retval None
01152   */
01153 void LCD_PowerOn(void)
01154 {
01155 /* Power On sequence ---------------------------------------------------------*/
01156   LCD_WriteReg(LCD_REG_16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
01157   LCD_WriteReg(LCD_REG_17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */
01158   LCD_WriteReg(LCD_REG_18, 0x0000); /* VREG1OUT voltage */
01159   LCD_WriteReg(LCD_REG_19, 0x0000); /* VDV[4:0] for VCOM amplitude*/
01160   _delay_(20);                 /* Dis-charge capacitor power voltage (200ms) */
01161   LCD_WriteReg(LCD_REG_16, 0x17B0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
01162   LCD_WriteReg(LCD_REG_17, 0x0137); /* DC1[2:0], DC0[2:0], VC[2:0] */
01163   _delay_(5);                  /* Delay 50 ms */
01164   LCD_WriteReg(LCD_REG_18, 0x0139); /* VREG1OUT voltage */
01165   _delay_(5);                  /* Delay 50 ms */
01166   LCD_WriteReg(LCD_REG_19, 0x1d00); /* VDV[4:0] for VCOM amplitude */
01167   LCD_WriteReg(LCD_REG_41, 0x0013); /* VCM[4:0] for VCOMH */
01168   _delay_(5);                  /* Delay 50 ms */
01169   LCD_WriteReg(LCD_REG_7, 0x0173);  /* 262K color and display ON */
01170 }
01171
01172
01173 /**
01174   * @brief  Enables the Display.
01175   * @param  None
01176   * @retval None
01177   */
01178 void LCD_DisplayOn(void)
01179 {
01180   /* Display On */
01181   LCD_WriteReg(LCD_REG_7, 0x0173); /* 262K color and display ON */
01182 }
01183
01184
01185 /**
01186   * @brief  Disables the Display.
01187   * @param  None
01188   * @retval None
01189   */
01190 void LCD_DisplayOff(void)
01191 {
01192   /* Display Off */
01193   LCD_WriteReg(LCD_REG_7, 0x0);
01194 }
01195
01196
01197 /**
01198   * @brief  Configures LCD Control lines (FSMC Pins) in alternate function mode.
01199   * @param  None
01200   * @retval None
01201   */
01202 void LCD_CtrlLinesConfig(void)
01203 {
01204   GPIO_InitTypeDef GPIO_InitStructure;
01205   /* Enable FSMC, GPIOD, GPIOE, GPIOF, GPIOG and AFIO clocks */
01206   RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, ENABLE);
01207   RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOE |
01208                          RCC_APB2Periph_GPIOF | RCC_APB2Periph_GPIOG |
01209                          RCC_APB2Periph_AFIO, ENABLE);
01210   /* Set PD.00(D2), PD.01(D3), PD.04(NOE), PD.05(NWE), PD.08(D13), PD.09(D14),
01211      PD.10(D15), PD.14(D0), PD.15(D1) as alternate function push pull */
01212   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_4 | GPIO_Pin_5 |
01213                                 GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_14 |
01214                                 GPIO_Pin_15;
01215   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
01216   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
01217   GPIO_Init(GPIOD, &GPIO_InitStructure);
01218   /* Set PE.07(D4), PE.08(D5), PE.09(D6), PE.10(D7), PE.11(D8), PE.12(D9), PE.13(D10),
01219      PE.14(D11), PE.15(D12) as alternate function push pull */
01220   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 |
01221                                 GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 |
01222                                 GPIO_Pin_15;
01223   GPIO_Init(GPIOE, &GPIO_InitStructure);
01224   /* Set PF.00(A0 (RS)) as alternate function push pull */
01225   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0;
01226   GPIO_Init(GPIOF, &GPIO_InitStructure);
01227   /* Set PG.12(NE4 (LCD/CS)) as alternate function push pull - CE3(LCD /CS) */
01228   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12;
01229   GPIO_Init(GPIOG, &GPIO_InitStructure);
01230 }
01231
01232
01233 /**
01234   * @brief  Configures the Parallel interface (FSMC) for LCD(Parallel mode)
01235   * @param  None
01236   * @retval None
01237   */
01238 void LCD_FSMCConfig(void)
01239 {
01240   FSMC_NORSRAMInitTypeDef  FSMC_NORSRAMInitStructure;
01241   FSMC_NORSRAMTimingInitTypeDef  p;
01242 /*-- FSMC Configuration ------------------------------------------------------*/
01243 /*----------------------- SRAM Bank 4 ----------------------------------------*/
01244   /* FSMC_Bank1_NORSRAM4 configuration */
01245   p.FSMC_AddressSetupTime = 1;
01246   p.FSMC_AddressHoldTime = 0;
01247   p.FSMC_DataSetupTime = 2;
01248   p.FSMC_BusTurnAroundDuration = 0;
01249   p.FSMC_CLKDivision = 0;
01250   p.FSMC_DataLatency = 0;
01251   p.FSMC_AccessMode = FSMC_AccessMode_A;
01252   /* Color LCD configuration ------------------------------------
01253      LCD configured as follow:
01254         - Data/Address MUX = Disable
01255         - Memory Type = SRAM
01256         - Data Width = 16bit
01257         - Write Operation = Enable
01258         - Extended Mode = Enable
01259         - Asynchronous Wait = Disable */
01260   FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM4;
01261   FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
01262   FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM;
01263   FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
01264   FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
01265   FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
01266   FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
01267   FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
01268   FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
01269   FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
01270   FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
01271   FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
01272   FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
01273   FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
01274   FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
01275   FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);
01276   /* BANK 4 (of NOR/SRAM Bank 1~4) is enabled */
01277   FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM4, ENABLE);
01278 }
01279
01280 /**
01281   * @brief  Displays a pixel.
01282   * @param  x: pixel x.
01283   * @param  y: pixel y.
01284   * @retval None
01285   */
01286 static void PutPixel(int16_t x, int16_t y)
01287 {
01288   if(x < 0 || x > 239 || y < 0 || y > 319)
01289   {
01290     return;
01291   }
01292   LCD_DrawLine(x, y, 1, LCD_DIR_HORIZONTAL);
01293 }
01294
01295 #ifndef USE_Delay
01296 /**
01297   * @brief  Inserts a delay time.
01298   * @param  nCount: specifies the delay time length.
01299   * @retval None
01300   */
01301 static void delay(vu32 nCount)
01302 {
01303   vu32 index = 0;
01304   for(index = (100000 * nCount); index != 0; index--)
01305   {
01306   }
01307 }
01308 #endif /* USE_Delay*/
01309 /**
01310   * @}
01311   */
01312
01313 /**
01314   * @}
01315   */
01316
01317 /**
01318   * @}
01319   */
01320
01321 /**
01322   * @}
01323   */
01324
01325 /**
01326   * @}
01327   */
01328
01329 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm3210e_eval_lcd.h Source File

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • STM3210E_EVAL

stm3210e_eval_lcd.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm3210e_eval_lcd.h
00004   * @author  MCD Application Team
00005   * @version V4.5.0
00006   * @date    07-March-2011
00007   * @brief   This file contains all the functions prototypes for the stm3210e_eval_lcd
00008   *          firmware driver.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00013   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00014   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00015   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00016   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00017   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00018   *
00019   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00020   ******************************************************************************
00021   */
00022
00023 /* Define to prevent recursive inclusion -------------------------------------*/
00024 #ifndef __STM3210E_EVAL_LCD_H
00025 #define __STM3210E_EVAL_LCD_H
00026
00027 #ifdef __cplusplus
00028  extern "C" {
00029 #endif
00030
00031 /* Includes ------------------------------------------------------------------*/
00032 #include "stm32f10x.h"
00033 #include "../Common/fonts.h"
00034
00035 /** @addtogroup Utilities
00036   * @{
00037   */
00038
00039 /** @addtogroup STM32_EVAL
00040   * @{
00041   */
00042
00043 /** @addtogroup STM3210E_EVAL
00044   * @{
00045   */
00046
00047 /** @addtogroup STM3210E_EVAL_LCD
00048   * @{
00049   */
00050
00051 /** @defgroup STM3210E_EVAL_LCD_Exported_Types
00052   * @{
00053   */
00054 typedef struct
00055 {
00056   int16_t X;
00057   int16_t Y;
00058 } Point, * pPoint;
00059 /**
00060   * @}
00061   */
00062
00063 /** @defgroup STM3210E_EVAL_LCD_Exported_Constants
00064   * @{
00065   */
00066
00067 /**
00068  * @brief Uncomment the line below if you want to use user defined Delay function
00069  *        (for precise timing), otherwise default _delay_ function defined within
00070  *         this driver is used (less precise timing).
00071  */
00072 /* #define USE_Delay */
00073
00074 #ifdef USE_Delay
00075 #include "main.h"
00076   #define _delay_     Delay  /* !< User can provide more timing precise _delay_ function
00077                                    (with 10ms time base), using SysTick for example */
00078 #else
00079   #define _delay_     delay      /* !< Default _delay_ function with less precise timing */
00080 #endif
00081
00082 /**
00083   * @brief  LCD Registers
00084   */
00085 #define LCD_REG_0             0x00
00086 #define LCD_REG_1             0x01
00087 #define LCD_REG_2             0x02
00088 #define LCD_REG_3             0x03
00089 #define LCD_REG_4             0x04
00090 #define LCD_REG_5             0x05
00091 #define LCD_REG_6             0x06
00092 #define LCD_REG_7             0x07
00093 #define LCD_REG_8             0x08
00094 #define LCD_REG_9             0x09
00095 #define LCD_REG_10            0x0A
00096 #define LCD_REG_12            0x0C
00097 #define LCD_REG_13            0x0D
00098 #define LCD_REG_14            0x0E
00099 #define LCD_REG_15            0x0F
00100 #define LCD_REG_16            0x10
00101 #define LCD_REG_17            0x11
00102 #define LCD_REG_18            0x12
00103 #define LCD_REG_19            0x13
00104 #define LCD_REG_20            0x14
00105 #define LCD_REG_21            0x15
00106 #define LCD_REG_22            0x16
00107 #define LCD_REG_23            0x17
00108 #define LCD_REG_24            0x18
00109 #define LCD_REG_25            0x19
00110 #define LCD_REG_26            0x1A
00111 #define LCD_REG_27            0x1B
00112 #define LCD_REG_28            0x1C
00113 #define LCD_REG_29            0x1D
00114 #define LCD_REG_30            0x1E
00115 #define LCD_REG_31            0x1F
00116 #define LCD_REG_32            0x20
00117 #define LCD_REG_33            0x21
00118 #define LCD_REG_34            0x22
00119 #define LCD_REG_36            0x24
00120 #define LCD_REG_37            0x25
00121 #define LCD_REG_40            0x28
00122 #define LCD_REG_41            0x29
00123 #define LCD_REG_43            0x2B
00124 #define LCD_REG_45            0x2D
00125 #define LCD_REG_48            0x30
00126 #define LCD_REG_49            0x31
00127 #define LCD_REG_50            0x32
00128 #define LCD_REG_51            0x33
00129 #define LCD_REG_52            0x34
00130 #define LCD_REG_53            0x35
00131 #define LCD_REG_54            0x36
00132 #define LCD_REG_55            0x37
00133 #define LCD_REG_56            0x38
00134 #define LCD_REG_57            0x39
00135 #define LCD_REG_58            0x3A
00136 #define LCD_REG_59            0x3B
00137 #define LCD_REG_60            0x3C
00138 #define LCD_REG_61            0x3D
00139 #define LCD_REG_62            0x3E
00140 #define LCD_REG_63            0x3F
00141 #define LCD_REG_64            0x40
00142 #define LCD_REG_65            0x41
00143 #define LCD_REG_66            0x42
00144 #define LCD_REG_67            0x43
00145 #define LCD_REG_68            0x44
00146 #define LCD_REG_69            0x45
00147 #define LCD_REG_70            0x46
00148 #define LCD_REG_71            0x47
00149 #define LCD_REG_72            0x48
00150 #define LCD_REG_73            0x49
00151 #define LCD_REG_74            0x4A
00152 #define LCD_REG_75            0x4B
00153 #define LCD_REG_76            0x4C
00154 #define LCD_REG_77            0x4D
00155 #define LCD_REG_78            0x4E
00156 #define LCD_REG_79            0x4F
00157 #define LCD_REG_80            0x50
00158 #define LCD_REG_81            0x51
00159 #define LCD_REG_82            0x52
00160 #define LCD_REG_83            0x53
00161 #define LCD_REG_96            0x60
00162 #define LCD_REG_97            0x61
00163 #define LCD_REG_106           0x6A
00164 #define LCD_REG_118           0x76
00165 #define LCD_REG_128           0x80
00166 #define LCD_REG_129           0x81
00167 #define LCD_REG_130           0x82
00168 #define LCD_REG_131           0x83
00169 #define LCD_REG_132           0x84
00170 #define LCD_REG_133           0x85
00171 #define LCD_REG_134           0x86
00172 #define LCD_REG_135           0x87
00173 #define LCD_REG_136           0x88
00174 #define LCD_REG_137           0x89
00175 #define LCD_REG_139           0x8B
00176 #define LCD_REG_140           0x8C
00177 #define LCD_REG_141           0x8D
00178 #define LCD_REG_143           0x8F
00179 #define LCD_REG_144           0x90
00180 #define LCD_REG_145           0x91
00181 #define LCD_REG_146           0x92
00182 #define LCD_REG_147           0x93
00183 #define LCD_REG_148           0x94
00184 #define LCD_REG_149           0x95
00185 #define LCD_REG_150           0x96
00186 #define LCD_REG_151           0x97
00187 #define LCD_REG_152           0x98
00188 #define LCD_REG_153           0x99
00189 #define LCD_REG_154           0x9A
00190 #define LCD_REG_157           0x9D
00191 #define LCD_REG_192           0xC0
00192 #define LCD_REG_193           0xC1
00193 #define LCD_REG_229           0xE5
00194
00195 /**
00196   * @brief  LCD color
00197   */
00198 #define LCD_COLOR_WHITE          0xFFFF
00199 #define LCD_COLOR_BLACK          0x0000
00200 #define LCD_COLOR_GREY           0xF7DE
00201 #define LCD_COLOR_BLUE           0x001F
00202 #define LCD_COLOR_BLUE2          0x051F
00203 #define LCD_COLOR_RED            0xF800
00204 #define LCD_COLOR_MAGENTA        0xF81F
00205 #define LCD_COLOR_GREEN          0x07E0
00206 #define LCD_COLOR_CYAN           0x7FFF
00207 #define LCD_COLOR_YELLOW         0xFFE0
00208
00209 /**
00210   * @brief  LCD Lines depending on the chosen fonts.
00211   */
00212 #define LCD_LINE_0               LINE(0)
00213 #define LCD_LINE_1               LINE(1)
00214 #define LCD_LINE_2               LINE(2)
00215 #define LCD_LINE_3               LINE(3)
00216 #define LCD_LINE_4               LINE(4)
00217 #define LCD_LINE_5               LINE(5)
00218 #define LCD_LINE_6               LINE(6)
00219 #define LCD_LINE_7               LINE(7)
00220 #define LCD_LINE_8               LINE(8)
00221 #define LCD_LINE_9               LINE(9)
00222 #define LCD_LINE_10              LINE(10)
00223 #define LCD_LINE_11              LINE(11)
00224 #define LCD_LINE_12              LINE(12)
00225 #define LCD_LINE_13              LINE(13)
00226 #define LCD_LINE_14              LINE(14)
00227 #define LCD_LINE_15              LINE(15)
00228 #define LCD_LINE_16              LINE(16)
00229 #define LCD_LINE_17              LINE(17)
00230 #define LCD_LINE_18              LINE(18)
00231 #define LCD_LINE_19              LINE(19)
00232 #define LCD_LINE_20              LINE(20)
00233 #define LCD_LINE_21              LINE(21)
00234 #define LCD_LINE_22              LINE(22)
00235 #define LCD_LINE_23              LINE(23)
00236 #define LCD_LINE_24              LINE(24)
00237 #define LCD_LINE_25              LINE(25)
00238 #define LCD_LINE_26              LINE(26)
00239 #define LCD_LINE_27              LINE(27)
00240 #define LCD_LINE_28              LINE(28)
00241 #define LCD_LINE_29              LINE(29)
00242
00243 /**
00244   * @brief LCD default font
00245   */
00246 #define LCD_DEFAULT_FONT         Font16x24
00247
00248 /**
00249   * @brief  LCD Direction
00250   */
00251 #define LCD_DIR_HORIZONTAL       0x0000
00252 #define LCD_DIR_VERTICAL         0x0001
00253
00254 /**
00255   * @brief  LCD Size (Width and Height)
00256   */
00257 #define LCD_PIXEL_WIDTH          0x0140
00258 #define LCD_PIXEL_HEIGHT         0x00F0
00259
00260 /**
00261   * @}
00262   */
00263
00264 /** @defgroup STM3210E_EVAL_LCD_Exported_Macros
00265   * @{
00266   */
00267 #define ASSEMBLE_RGB(R, G, B)    ((((R)& 0xF8) << 8) | (((G) & 0xFC) << 3) | (((B) & 0xF8) >> 3))
00268 /**
00269   * @}
00270   */
00271
00272 /** @defgroup STM3210E_EVAL_LCD_Exported_Functions
00273   * @{
00274   */
00275 /** @defgroup
00276   * @{
00277   */
00278 void LCD_DeInit(void);
00279 void STM3210E_LCD_Init(void);
00280 void LCD_SetColors(__IO uint16_t _TextColor, __IO uint16_t _BackColor);
00281 void LCD_GetColors(__IO uint16_t *_TextColor, __IO uint16_t *_BackColor);
00282 void LCD_SetTextColor(__IO uint16_t Color);
00283 void LCD_SetBackColor(__IO uint16_t Color);
00284 void LCD_ClearLine(uint8_t Line);
00285 void LCD_Clear(uint16_t Color);
00286 void LCD_SetCursor(uint8_t Xpos, uint16_t Ypos);
00287 void LCD_DrawChar(uint8_t Xpos, uint16_t Ypos, const uint16_t *c);
00288 void LCD_DisplayChar(uint8_t Line, uint16_t Column, uint8_t Ascii);
00289 void LCD_SetFont(sFONT *fonts);
00290 sFONT *LCD_GetFont(void);
00291 void LCD_DisplayStringLine(uint8_t Line, uint8_t *ptr);
00292 void LCD_SetDisplayWindow(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width);
00293 void LCD_WindowModeDisable(void);
00294 void LCD_DrawLine(uint8_t Xpos, uint16_t Ypos, uint16_t Length, uint8_t Direction);
00295 void LCD_DrawRect(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width);
00296 void LCD_DrawCircle(uint8_t Xpos, uint16_t Ypos, uint16_t Radius);
00297 void LCD_DrawMonoPict(const uint32_t *Pict);
00298 void LCD_WriteBMP(uint32_t BmpAddress);
00299 void LCD_DrawUniLine(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2);
00300 void LCD_DrawFullRect(uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height);
00301 void LCD_DrawFullCircle(uint16_t Xpos, uint16_t Ypos, uint16_t Radius);
00302 void LCD_PolyLine(pPoint Points, uint16_t PointCount);
00303 void LCD_PolyLineRelative(pPoint Points, uint16_t PointCount);
00304 void LCD_ClosedPolyLine(pPoint Points, uint16_t PointCount);
00305 void LCD_ClosedPolyLineRelative(pPoint Points, uint16_t PointCount);
00306 void LCD_FillPolyLine(pPoint Points, uint16_t PointCount);
00307 /**
00308   * @}
00309   */
00310
00311 /** @defgroup
00312   * @{
00313   */
00314 void LCD_WriteReg(uint8_t LCD_Reg, uint16_t LCD_RegValue);
00315 uint16_t LCD_ReadReg(uint8_t LCD_Reg);
00316 void LCD_WriteRAM_Prepare(void);
00317 void LCD_WriteRAM(uint16_t RGB_Code);
00318 uint16_t LCD_ReadRAM(void);
00319 void LCD_PowerOn(void);
00320 void LCD_DisplayOn(void);
00321 void LCD_DisplayOff(void);
00322 /**
00323   * @}
00324   */
00325
00326 /** @defgroup
00327   * @{
00328   */
00329 void LCD_CtrlLinesConfig(void);
00330 void LCD_FSMCConfig(void);
00331 /**
00332   * @}
00333   */
00334
00335 /**
00336   * @}
00337   */
00338 #ifdef __cplusplus
00339 }
00340 #endif
00341
00342 #endif /* __STM3210E_EVAL_LCD_H */
00343 /**
00344   * @}
00345   */
00346
00347 /**
00348   * @}
00349   */
00350
00351 /**
00352   * @}
00353   */
00354
00355 /**
00356   * @}
00357   */
00358
00359 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32100b_eval.c Source File

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • STM32100B_EVAL

stm32100b_eval.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32100b_eval.c
00004   * @author  MCD Application Team
00005   * @version V4.5.0
00006   * @date    07-March-2011
00007   * @brief   This file provides
00008   *            - set of firmware functions to manage Leds, push-button and COM ports
00009   *            - low level initialization functions for SD card (on SPI), SPI serial
00010   *              flash (sFLASH) and temperature sensor (LM75)
00011   *          available on STM32100B-EVAL evaluation board from STMicroelectronics.
00012   ******************************************************************************
00013   * @attention
00014   *
00015   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00016   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00017   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00018   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00019   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00020   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00021   *
00022   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00023   ******************************************************************************
00024   */
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32100b_eval.h"
00028 #include "stm32f10x_spi.h"
00029 #include "stm32f10x_i2c.h"
00030
00031 /** @addtogroup Utilities
00032   * @{
00033   */
00034
00035 /** @addtogroup STM32_EVAL
00036   * @{
00037   */
00038
00039 /** @addtogroup STM32100B_EVAL
00040   * @{
00041   */
00042
00043 /** @defgroup STM32100B_EVAL_LOW_LEVEL
00044   * @brief This file provides firmware functions to manage Leds, push-buttons,
00045   *        COM ports, SD card on SPI, serial flash (sFLASH) and temperature
00046   *        sensor (LM75) available on STM32100B-EVAL evaluation board from
00047   *        STMicroelectronics.
00048   * @{
00049   */
00050
00051 /** @defgroup STM32100B_EVAL_LOW_LEVEL_Private_TypesDefinitions
00052   * @{
00053   */
00054 /**
00055   * @}
00056   */
00057
00058
00059 /** @defgroup STM32100B_EVAL_LOW_LEVEL_Private_Defines
00060   * @{
00061   */
00062 /**
00063   * @}
00064   */
00065
00066
00067 /** @defgroup STM32100B_EVAL_LOW_LEVEL_Private_Macros
00068   * @{
00069   */
00070 /**
00071   * @}
00072   */
00073
00074
00075 /** @defgroup STM32100B_EVAL_LOW_LEVEL_Private_Variables
00076   * @{
00077   */
00078 GPIO_TypeDef* GPIO_PORT[LEDn] = {LED1_GPIO_PORT, LED2_GPIO_PORT, LED3_GPIO_PORT,
00079                                  LED4_GPIO_PORT};
00080 const uint16_t GPIO_PIN[LEDn] = {LED1_PIN, LED2_PIN, LED3_PIN,
00081                                  LED4_PIN};
00082 const uint32_t GPIO_CLK[LEDn] = {LED1_GPIO_CLK, LED2_GPIO_CLK, LED3_GPIO_CLK,
00083                                  LED4_GPIO_CLK};
00084
00085 GPIO_TypeDef* BUTTON_PORT[BUTTONn] = {WAKEUP_BUTTON_GPIO_PORT, TAMPER_BUTTON_GPIO_PORT,
00086                                       KEY_BUTTON_GPIO_PORT, RIGHT_BUTTON_GPIO_PORT,
00087                                       LEFT_BUTTON_GPIO_PORT, UP_BUTTON_GPIO_PORT,
00088                                       DOWN_BUTTON_GPIO_PORT, SEL_BUTTON_GPIO_PORT};
00089
00090 const uint16_t BUTTON_PIN[BUTTONn] = {WAKEUP_BUTTON_PIN, TAMPER_BUTTON_PIN,
00091                                       KEY_BUTTON_PIN, RIGHT_BUTTON_PIN,
00092                                       LEFT_BUTTON_PIN, UP_BUTTON_PIN,
00093                                       DOWN_BUTTON_PIN, SEL_BUTTON_PIN};
00094
00095 const uint32_t BUTTON_CLK[BUTTONn] = {WAKEUP_BUTTON_GPIO_CLK, TAMPER_BUTTON_GPIO_CLK,
00096                                       KEY_BUTTON_GPIO_CLK, RIGHT_BUTTON_GPIO_CLK,
00097                                       LEFT_BUTTON_GPIO_CLK, UP_BUTTON_GPIO_CLK,
00098                                       DOWN_BUTTON_GPIO_CLK, SEL_BUTTON_GPIO_CLK};
00099
00100 const uint16_t BUTTON_EXTI_LINE[BUTTONn] = {WAKEUP_BUTTON_EXTI_LINE,
00101                                             TAMPER_BUTTON_EXTI_LINE,
00102                                             KEY_BUTTON_EXTI_LINE,
00103                                             RIGHT_BUTTON_EXTI_LINE,
00104                                             LEFT_BUTTON_EXTI_LINE,
00105                                             UP_BUTTON_EXTI_LINE,
00106                                             DOWN_BUTTON_EXTI_LINE,
00107                                             SEL_BUTTON_EXTI_LINE};
00108
00109 const uint16_t BUTTON_PORT_SOURCE[BUTTONn] = {WAKEUP_BUTTON_EXTI_PORT_SOURCE,
00110                                               TAMPER_BUTTON_EXTI_PORT_SOURCE,
00111                                               KEY_BUTTON_EXTI_PORT_SOURCE,
00112                                               RIGHT_BUTTON_EXTI_PORT_SOURCE,
00113                                               LEFT_BUTTON_EXTI_PORT_SOURCE,
00114                                               UP_BUTTON_EXTI_PORT_SOURCE,
00115                                               DOWN_BUTTON_EXTI_PORT_SOURCE,
00116                                               SEL_BUTTON_EXTI_PORT_SOURCE};
00117
00118 const uint16_t BUTTON_PIN_SOURCE[BUTTONn] = {WAKEUP_BUTTON_EXTI_PIN_SOURCE,
00119                                              TAMPER_BUTTON_EXTI_PIN_SOURCE,
00120                                              KEY_BUTTON_EXTI_PIN_SOURCE,
00121                                              RIGHT_BUTTON_EXTI_PIN_SOURCE,
00122                                              LEFT_BUTTON_EXTI_PIN_SOURCE,
00123                                              UP_BUTTON_EXTI_PIN_SOURCE,
00124                                              DOWN_BUTTON_EXTI_PIN_SOURCE,
00125                                              SEL_BUTTON_EXTI_PIN_SOURCE};
00126
00127 const uint16_t BUTTON_IRQn[BUTTONn] = {WAKEUP_BUTTON_EXTI_IRQn, TAMPER_BUTTON_EXTI_IRQn,
00128                                        KEY_BUTTON_EXTI_IRQn, RIGHT_BUTTON_EXTI_IRQn,
00129                                        LEFT_BUTTON_EXTI_IRQn, UP_BUTTON_EXTI_IRQn,
00130                                        DOWN_BUTTON_EXTI_IRQn, SEL_BUTTON_EXTI_IRQn};
00131
00132 USART_TypeDef* COM_USART[COMn] = {EVAL_COM1, EVAL_COM2};
00133
00134 GPIO_TypeDef* COM_TX_PORT[COMn] = {EVAL_COM1_TX_GPIO_PORT, EVAL_COM2_TX_GPIO_PORT};
00135
00136 GPIO_TypeDef* COM_RX_PORT[COMn] = {EVAL_COM1_RX_GPIO_PORT, EVAL_COM2_RX_GPIO_PORT};
00137
00138 const uint32_t COM_USART_CLK[COMn] = {EVAL_COM1_CLK, EVAL_COM2_CLK};
00139
00140 const uint32_t COM_TX_PORT_CLK[COMn] = {EVAL_COM1_TX_GPIO_CLK, EVAL_COM2_TX_GPIO_CLK};
00141
00142 const uint32_t COM_RX_PORT_CLK[COMn] = {EVAL_COM1_RX_GPIO_CLK, EVAL_COM2_RX_GPIO_CLK};
00143
00144 const uint16_t COM_TX_PIN[COMn] = {EVAL_COM1_TX_PIN, EVAL_COM2_TX_PIN};
00145
00146 const uint16_t COM_RX_PIN[COMn] = {EVAL_COM1_RX_PIN, EVAL_COM2_RX_PIN};
00147
00148 /**
00149   * @}
00150   */
00151
00152
00153 /** @defgroup STM32100B_EVAL_LOW_LEVEL_Private_FunctionPrototypes
00154   * @{
00155   */
00156
00157 /**
00158   * @}
00159   */
00160
00161
00162 /** @defgroup STM32100B_EVAL_LOW_LEVEL_Private_Functions
00163   * @{
00164   */
00165
00166 /**
00167   * @brief  Configures LED GPIO.
00168   * @param  Led: Specifies the Led to be configured.
00169   *   This parameter can be one of following parameters:
00170   *     @arg LED1
00171   *     @arg LED2
00172   *     @arg LED3
00173   *     @arg LED4
00174   * @retval None
00175   */
00176 void STM_EVAL_LEDInit(Led_TypeDef Led)
00177 {
00178   GPIO_InitTypeDef  GPIO_InitStructure;
00179
00180   /* Enable the GPIO_LED Clock */
00181   RCC_APB2PeriphClockCmd(GPIO_CLK[Led], ENABLE);
00182
00183   /* Configure the GPIO_LED pin */
00184   GPIO_InitStructure.GPIO_Pin = GPIO_PIN[Led];
00185
00186   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
00187   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00188   GPIO_Init(GPIO_PORT[Led], &GPIO_InitStructure);
00189 }
00190
00191 /**
00192   * @brief  Turns selected LED On.
00193   * @param  Led: Specifies the Led to be set on.
00194   *   This parameter can be one of following parameters:
00195   *     @arg LED1
00196   *     @arg LED2
00197   *     @arg LED3
00198   *     @arg LED4
00199   * @retval None
00200   */
00201 void STM_EVAL_LEDOn(Led_TypeDef Led)
00202 {
00203   GPIO_PORT[Led]->BSRR = GPIO_PIN[Led];
00204 }
00205
00206 /**
00207   * @brief  Turns selected LED Off.
00208   * @param  Led: Specifies the Led to be set off.
00209   *   This parameter can be one of following parameters:
00210   *     @arg LED1
00211   *     @arg LED2
00212   *     @arg LED3
00213   *     @arg LED4
00214   * @retval None
00215   */
00216 void STM_EVAL_LEDOff(Led_TypeDef Led)
00217 {
00218   GPIO_PORT[Led]->BRR = GPIO_PIN[Led];
00219 }
00220
00221 /**
00222   * @brief  Toggles the selected LED.
00223   * @param  Led: Specifies the Led to be toggled.
00224   *   This parameter can be one of following parameters:
00225   *     @arg LED1
00226   *     @arg LED2
00227   *     @arg LED3
00228   *     @arg LED4
00229   * @retval None
00230   */
00231 void STM_EVAL_LEDToggle(Led_TypeDef Led)
00232 {
00233   GPIO_PORT[Led]->ODR ^= GPIO_PIN[Led];
00234 }
00235
00236 /**
00237   * @brief  Configures Button GPIO and EXTI Line.
00238   * @param  Button: Specifies the Button to be configured.
00239   *   This parameter can be one of following parameters:
00240   *     @arg BUTTON_WAKEUP: Wakeup Push Button
00241   *     @arg BUTTON_TAMPER: Tamper Push Button
00242   *     @arg BUTTON_KEY: Key Push Button
00243   *     @arg BUTTON_RIGHT: Joystick Right Push Button
00244   *     @arg BUTTON_LEFT: Joystick Left Push Button
00245   *     @arg BUTTON_UP: Joystick Up Push Button
00246   *     @arg BUTTON_DOWN: Joystick Down Push Button
00247   *     @arg BUTTON_SEL: Joystick Sel Push Button
00248   * @param  Button_Mode: Specifies Button mode.
00249   *   This parameter can be one of following parameters:
00250   *     @arg BUTTON_MODE_GPIO: Button will be used as simple IO
00251   *     @arg BUTTON_MODE_EXTI: Button will be connected to EXTI line with interrupt
00252   *                     generation capability
00253   * @retval None
00254   */
00255 void STM_EVAL_PBInit(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode)
00256 {
00257   GPIO_InitTypeDef GPIO_InitStructure;
00258   EXTI_InitTypeDef EXTI_InitStructure;
00259   NVIC_InitTypeDef NVIC_InitStructure;
00260
00261   /* Enable the BUTTON Clock */
00262   RCC_APB2PeriphClockCmd(BUTTON_CLK[Button] | RCC_APB2Periph_AFIO, ENABLE);
00263
00264   /* Configure Button pin as input floating */
00265   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
00266   GPIO_InitStructure.GPIO_Pin = BUTTON_PIN[Button];
00267   GPIO_Init(BUTTON_PORT[Button], &GPIO_InitStructure);
00268
00269
00270   if (Button_Mode == BUTTON_MODE_EXTI)
00271   {
00272     /* Connect Button EXTI Line to Button GPIO Pin */
00273     GPIO_EXTILineConfig(BUTTON_PORT_SOURCE[Button], BUTTON_PIN_SOURCE[Button]);
00274
00275     /* Configure Button EXTI line */
00276     EXTI_InitStructure.EXTI_Line = BUTTON_EXTI_LINE[Button];
00277     EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
00278
00279     if(Button != BUTTON_WAKEUP)
00280     {
00281       EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling;
00282     }
00283     else
00284     {
00285       EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;
00286     }
00287     EXTI_InitStructure.EXTI_LineCmd = ENABLE;
00288     EXTI_Init(&EXTI_InitStructure);
00289
00290     /* Enable and set Button EXTI Interrupt to the lowest priority */
00291     NVIC_InitStructure.NVIC_IRQChannel = BUTTON_IRQn[Button];
00292     NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x0F;
00293     NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x0F;
00294     NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
00295
00296     NVIC_Init(&NVIC_InitStructure);
00297   }
00298 }
00299
00300 /**
00301   * @brief  Returns the selected Button state.
00302   * @param  Button: Specifies the Button to be checked.
00303   *   This parameter can be one of following parameters:
00304   *     @arg BUTTON_WAKEUP: Wakeup Push Button
00305   *     @arg BUTTON_TAMPER: Tamper Push Button
00306   *     @arg BUTTON_KEY: Key Push Button
00307   *     @arg BUTTON_RIGHT: Joystick Right Push Button
00308   *     @arg BUTTON_LEFT: Joystick Left Push Button
00309   *     @arg BUTTON_UP: Joystick Up Push Button
00310   *     @arg BUTTON_DOWN: Joystick Down Push Button
00311   *     @arg BUTTON_SEL: Joystick Sel Push Button
00312   * @retval The Button GPIO pin value.
00313   */
00314 uint32_t STM_EVAL_PBGetState(Button_TypeDef Button)
00315 {
00316   return GPIO_ReadInputDataBit(BUTTON_PORT[Button], BUTTON_PIN[Button]);
00317 }
00318
00319
00320 /**
00321   * @brief  Configures COM port.
00322   * @param  COM: Specifies the COM port to be configured.
00323   *   This parameter can be one of following parameters:
00324   *     @arg COM1
00325   *     @arg COM2
00326   * @param  USART_InitStruct: pointer to a USART_InitTypeDef structure that
00327   *   contains the configuration information for the specified USART peripheral.
00328   * @retval None
00329   */
00330 void STM_EVAL_COMInit(COM_TypeDef COM, USART_InitTypeDef* USART_InitStruct)
00331 {
00332   GPIO_InitTypeDef GPIO_InitStructure;
00333
00334   /* Enable GPIO clock */
00335   RCC_APB2PeriphClockCmd(COM_TX_PORT_CLK[COM] | COM_RX_PORT_CLK[COM] | RCC_APB2Periph_AFIO, ENABLE);
00336
00337
00338   /* Enable UART clock */
00339   if (COM == COM1)
00340   {
00341     RCC_APB2PeriphClockCmd(COM_USART_CLK[COM], ENABLE);
00342   }
00343   else
00344   {
00345     /* Enable the USART2 Pins Software Remapping */
00346     GPIO_PinRemapConfig(GPIO_Remap_USART2, ENABLE);
00347     RCC_APB1PeriphClockCmd(COM_USART_CLK[COM], ENABLE);
00348   }
00349
00350   /* Configure USART Tx as alternate function push-pull */
00351   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
00352   GPIO_InitStructure.GPIO_Pin = COM_TX_PIN[COM];
00353   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00354   GPIO_Init(COM_TX_PORT[COM], &GPIO_InitStructure);
00355
00356   /* Configure USART Rx as input floating */
00357   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
00358   GPIO_InitStructure.GPIO_Pin = COM_RX_PIN[COM];
00359   GPIO_Init(COM_RX_PORT[COM], &GPIO_InitStructure);
00360
00361   /* USART configuration */
00362   USART_Init(COM_USART[COM], USART_InitStruct);
00363
00364   /* Enable USART */
00365   USART_Cmd(COM_USART[COM], ENABLE);
00366 }
00367
00368 /**
00369   * @brief  DeInitializes the SD/SD communication.
00370   * @param  None
00371   * @retval None
00372   */
00373 void SD_LowLevel_DeInit(void)
00374 {
00375   GPIO_InitTypeDef  GPIO_InitStructure;
00376
00377   SPI_Cmd(SD_SPI, DISABLE); /*!< SD_SPI disable */
00378   SPI_I2S_DeInit(SD_SPI);   /*!< DeInitializes the SD_SPI */
00379
00380   /*!< SD_SPI Periph clock disable */
00381   RCC_APB2PeriphClockCmd(SD_SPI_CLK, DISABLE);
00382
00383   /*!< Configure SD_SPI pins: SCK */
00384   GPIO_InitStructure.GPIO_Pin = SD_SPI_SCK_PIN;
00385   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
00386   GPIO_Init(SD_SPI_SCK_GPIO_PORT, &GPIO_InitStructure);
00387
00388   /*!< Configure SD_SPI pins: MISO */
00389   GPIO_InitStructure.GPIO_Pin = SD_SPI_MISO_PIN;
00390   GPIO_Init(SD_SPI_MISO_GPIO_PORT, &GPIO_InitStructure);
00391
00392   /*!< Configure SD_SPI pins: MOSI */
00393   GPIO_InitStructure.GPIO_Pin = SD_SPI_MOSI_PIN;
00394   GPIO_Init(SD_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure);
00395
00396   /*!< Configure SD_SPI_CS_PIN pin: SD Card CS pin */
00397   GPIO_InitStructure.GPIO_Pin = SD_CS_PIN;
00398   GPIO_Init(SD_CS_GPIO_PORT, &GPIO_InitStructure);
00399
00400   /*!< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin */
00401   GPIO_InitStructure.GPIO_Pin = SD_DETECT_PIN;
00402   GPIO_Init(SD_DETECT_GPIO_PORT, &GPIO_InitStructure);
00403 }
00404
00405 /**
00406   * @brief  Initializes the SD_SPI and CS pins.
00407   * @param  None
00408   * @retval None
00409   */
00410 void SD_LowLevel_Init(void)
00411 {
00412   GPIO_InitTypeDef  GPIO_InitStructure;
00413   SPI_InitTypeDef   SPI_InitStructure;
00414
00415   /*!< SD_SPI_CS_GPIO, SD_SPI_MOSI_GPIO, SD_SPI_MISO_GPIO, SD_SPI_DETECT_GPIO
00416        and SD_SPI_SCK_GPIO Periph clock enable */
00417   RCC_APB2PeriphClockCmd(SD_CS_GPIO_CLK | SD_SPI_MOSI_GPIO_CLK | SD_SPI_MISO_GPIO_CLK |
00418                          SD_SPI_SCK_GPIO_CLK | SD_DETECT_GPIO_CLK, ENABLE);
00419
00420   /*!< SD_SPI Periph clock enable */
00421   RCC_APB2PeriphClockCmd(SD_SPI_CLK, ENABLE);
00422
00423
00424   /*!< Configure SD_SPI pins: SCK */
00425   GPIO_InitStructure.GPIO_Pin = SD_SPI_SCK_PIN;
00426   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00427   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
00428   GPIO_Init(SD_SPI_SCK_GPIO_PORT, &GPIO_InitStructure);
00429
00430   /*!< Configure SD_SPI pins: MOSI */
00431   GPIO_InitStructure.GPIO_Pin = SD_SPI_MOSI_PIN;
00432   GPIO_Init(SD_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure);
00433
00434   /*!< Configure SD_SPI pins: MISO */
00435   GPIO_InitStructure.GPIO_Pin = SD_SPI_MISO_PIN;
00436   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
00437   GPIO_Init(SD_SPI_MISO_GPIO_PORT, &GPIO_InitStructure);
00438
00439   /*!< Configure SD_SPI_CS_PIN pin: SD Card CS pin */
00440   GPIO_InitStructure.GPIO_Pin = SD_CS_PIN;
00441   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
00442   GPIO_Init(SD_CS_GPIO_PORT, &GPIO_InitStructure);
00443
00444   /*!< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin */
00445   GPIO_InitStructure.GPIO_Pin = SD_DETECT_PIN;
00446   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
00447   GPIO_Init(SD_DETECT_GPIO_PORT, &GPIO_InitStructure);
00448
00449   /*!< SD_SPI Config */
00450   SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
00451   SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
00452   SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
00453   SPI_InitStructure.SPI_CPOL = SPI_CPOL_High;
00454   SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge;
00455   SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
00456   SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
00457
00458   SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
00459   SPI_InitStructure.SPI_CRCPolynomial = 7;
00460   SPI_Init(SD_SPI, &SPI_InitStructure);
00461
00462   SPI_Cmd(SD_SPI, ENABLE); /*!< SD_SPI enable */
00463 }
00464
00465 /**
00466   * @brief  DeInitializes the peripherals used by the SPI FLASH driver.
00467   * @param  None
00468   * @retval None
00469   */
00470 void sFLASH_LowLevel_DeInit(void)
00471 {
00472   GPIO_InitTypeDef GPIO_InitStructure;
00473
00474   /*!< Disable the sFLASH_SPI  */
00475   SPI_Cmd(sFLASH_SPI, DISABLE);
00476
00477   /*!< DeInitializes the sFLASH_SPI */
00478   SPI_I2S_DeInit(sFLASH_SPI);
00479
00480   /*!< sFLASH_SPI Periph clock disable */
00481   RCC_APB2PeriphClockCmd(sFLASH_SPI_CLK, DISABLE);
00482
00483   /*!< Configure sFLASH_SPI pins: SCK */
00484   GPIO_InitStructure.GPIO_Pin = sFLASH_SPI_SCK_PIN;
00485   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
00486   GPIO_Init(sFLASH_SPI_SCK_GPIO_PORT, &GPIO_InitStructure);
00487
00488   /*!< Configure sFLASH_SPI pins: MISO */
00489   GPIO_InitStructure.GPIO_Pin = sFLASH_SPI_MISO_PIN;
00490   GPIO_Init(sFLASH_SPI_MISO_GPIO_PORT, &GPIO_InitStructure);
00491
00492   /*!< Configure sFLASH_SPI pins: MOSI */
00493   GPIO_InitStructure.GPIO_Pin = sFLASH_SPI_MOSI_PIN;
00494   GPIO_Init(sFLASH_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure);
00495
00496   /*!< Configure sFLASH_CS_PIN pin: sFLASH Card CS pin */
00497   GPIO_InitStructure.GPIO_Pin = sFLASH_CS_PIN;
00498   GPIO_Init(sFLASH_CS_GPIO_PORT, &GPIO_InitStructure);
00499 }
00500
00501 /**
00502   * @brief  Initializes the peripherals used by the SPI FLASH driver.
00503   * @param  None
00504   * @retval None
00505   */
00506 void sFLASH_LowLevel_Init(void)
00507 {
00508   GPIO_InitTypeDef GPIO_InitStructure;
00509
00510   /*!< sFLASH_SPI_CS_GPIO, sFLASH_SPI_MOSI_GPIO, sFLASH_SPI_MISO_GPIO
00511        and sFLASH_SPI_SCK_GPIO Periph clock enable */
00512   RCC_APB2PeriphClockCmd(sFLASH_CS_GPIO_CLK | sFLASH_SPI_MOSI_GPIO_CLK | sFLASH_SPI_MISO_GPIO_CLK |
00513                          sFLASH_SPI_SCK_GPIO_CLK, ENABLE);
00514
00515   /*!< sFLASH_SPI Periph clock enable */
00516   RCC_APB2PeriphClockCmd(sFLASH_SPI_CLK, ENABLE);
00517
00518   /*!< Configure sFLASH_SPI pins: SCK */
00519   GPIO_InitStructure.GPIO_Pin = sFLASH_SPI_SCK_PIN;
00520   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00521   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
00522   GPIO_Init(sFLASH_SPI_SCK_GPIO_PORT, &GPIO_InitStructure);
00523
00524   /*!< Configure sFLASH_SPI pins: MOSI */
00525   GPIO_InitStructure.GPIO_Pin = sFLASH_SPI_MOSI_PIN;
00526   GPIO_Init(sFLASH_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure);
00527
00528   /*!< Configure sFLASH_SPI pins: MISO */
00529   GPIO_InitStructure.GPIO_Pin = sFLASH_SPI_MISO_PIN;
00530   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
00531   GPIO_Init(sFLASH_SPI_MISO_GPIO_PORT, &GPIO_InitStructure);
00532
00533   /*!< Configure sFLASH_CS_PIN pin: sFLASH Card CS pin */
00534   GPIO_InitStructure.GPIO_Pin = sFLASH_CS_PIN;
00535   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
00536   GPIO_Init(sFLASH_CS_GPIO_PORT, &GPIO_InitStructure);
00537 }
00538
00539 /**
00540   * @brief  DeInitializes the LM75_I2C.
00541   * @param  None
00542   * @retval None
00543   */
00544 void LM75_LowLevel_DeInit(void)
00545 {
00546   GPIO_InitTypeDef  GPIO_InitStructure;
00547
00548   /*!< Disable LM75_I2C */
00549   I2C_Cmd(LM75_I2C, DISABLE);
00550   /*!< DeInitializes the LM75_I2C */
00551   I2C_DeInit(LM75_I2C);
00552
00553   /*!< LM75_I2C Periph clock disable */
00554   RCC_APB1PeriphClockCmd(LM75_I2C_CLK, DISABLE);
00555
00556   /*!< Configure LM75_I2C pins: SCL */
00557   GPIO_InitStructure.GPIO_Pin = LM75_I2C_SCL_PIN;
00558   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
00559   GPIO_Init(LM75_I2C_SCL_GPIO_PORT, &GPIO_InitStructure);
00560
00561   /*!< Configure LM75_I2C pins: SDA */
00562   GPIO_InitStructure.GPIO_Pin = LM75_I2C_SDA_PIN;
00563   GPIO_Init(LM75_I2C_SDA_GPIO_PORT, &GPIO_InitStructure);
00564
00565   /*!< Configure LM75_I2C pin: SMBUS ALERT */
00566   GPIO_InitStructure.GPIO_Pin = LM75_I2C_SMBUSALERT_PIN;
00567   GPIO_Init(LM75_I2C_SMBUSALERT_GPIO_PORT, &GPIO_InitStructure);
00568 }
00569
00570 /**
00571   * @brief  Initializes the LM75_I2C..
00572   * @param  None
00573   * @retval None
00574   */
00575 void LM75_LowLevel_Init(void)
00576 {
00577   GPIO_InitTypeDef  GPIO_InitStructure;
00578
00579   /*!< LM75_I2C Periph clock enable */
00580   RCC_APB1PeriphClockCmd(LM75_I2C_CLK, ENABLE);
00581
00582   /*!< LM75_I2C_SCL_GPIO_CLK, LM75_I2C_SDA_GPIO_CLK
00583        and LM75_I2C_SMBUSALERT_GPIO_CLK Periph clock enable */
00584   RCC_APB2PeriphClockCmd(LM75_I2C_SCL_GPIO_CLK | LM75_I2C_SDA_GPIO_CLK |
00585                          LM75_I2C_SMBUSALERT_GPIO_CLK, ENABLE);
00586
00587   /*!< Configure LM75_I2C pins: SCL */
00588   GPIO_InitStructure.GPIO_Pin = LM75_I2C_SCL_PIN;
00589   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00590   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_OD;
00591   GPIO_Init(LM75_I2C_SCL_GPIO_PORT, &GPIO_InitStructure);
00592
00593   /*!< Configure LM75_I2C pins: SDA */
00594   GPIO_InitStructure.GPIO_Pin = LM75_I2C_SDA_PIN;
00595   GPIO_Init(LM75_I2C_SDA_GPIO_PORT, &GPIO_InitStructure);
00596
00597   /*!< Configure LM75_I2C pin: SMBUS ALERT */
00598   GPIO_InitStructure.GPIO_Pin = LM75_I2C_SMBUSALERT_PIN;
00599   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
00600   GPIO_Init(LM75_I2C_SMBUSALERT_GPIO_PORT, &GPIO_InitStructure);
00601 }
00602
00603 /**
00604   * @}
00605   */
00606
00607
00608 /**
00609   * @}
00610   */
00611
00612 /**
00613   * @}
00614   */
00615
00616 /**
00617   * @}
00618   */
00619
00620 /**
00621   * @}
00622   */
00623
00624 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32100b_eval.h Source File

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • STM32100B_EVAL

stm32100b_eval.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32100b_eval.h
00004   * @author  MCD Application Team
00005   * @version V4.5.0
00006   * @date    07-March-2011
00007   * @brief   This file contains definitions for STM32100B_EVAL's Leds, push-buttons
00008   *          COM ports, SD Card on SPI, sFLASH on SPI and Temperature Sensor LM75 on I2C
00009   *          hardware resources.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Define to prevent recursive inclusion -------------------------------------*/
00025 #ifndef __STM32100B_EVAL_H
00026 #define __STM32100B_EVAL_H
00027
00028 #ifdef __cplusplus
00029  extern "C" {
00030 #endif
00031
00032 /* Includes ------------------------------------------------------------------*/
00033 #include "stm32_eval.h"
00034
00035 /** @addtogroup Utilities
00036   * @{
00037   */
00038
00039 /** @addtogroup STM32_EVAL
00040   * @{
00041   */
00042
00043 /** @addtogroup STM32100B_EVAL
00044   * @{
00045   */
00046
00047 /** @addtogroup STM32100B_EVAL_LOW_LEVEL
00048   * @{
00049   */
00050
00051 /** @defgroup STM32100B_EVAL_LOW_LEVEL_Exported_Types
00052   * @{
00053   */
00054 /**
00055   * @}
00056   */
00057
00058 /** @defgroup STM32100B_EVAL_LOW_LEVEL_Exported_Constants
00059   * @{
00060   */
00061 /** @addtogroup STM32100B_EVAL_LOW_LEVEL_LED
00062   * @{
00063   */
00064 #define LEDn                             4
00065 #define LED1_PIN                         GPIO_Pin_6
00066 #define LED1_GPIO_PORT                   GPIOC
00067 #define LED1_GPIO_CLK                    RCC_APB2Periph_GPIOC
00068
00069 #define LED2_PIN                         GPIO_Pin_7
00070 #define LED2_GPIO_PORT                   GPIOC
00071 #define LED2_GPIO_CLK                    RCC_APB2Periph_GPIOC
00072
00073 #define LED3_PIN                         GPIO_Pin_8
00074 #define LED3_GPIO_PORT                   GPIOC
00075 #define LED3_GPIO_CLK                    RCC_APB2Periph_GPIOC
00076
00077 #define LED4_PIN                         GPIO_Pin_9
00078 #define LED4_GPIO_PORT                   GPIOC
00079 #define LED4_GPIO_CLK                    RCC_APB2Periph_GPIOC
00080
00081 /**
00082   * @}
00083   */
00084
00085 /** @addtogroup STM32100B_EVAL_LOW_LEVEL_BUTTON
00086   * @{
00087   */
00088 #define BUTTONn                          8
00089
00090 /**
00091  * @brief Wakeup push-button
00092  */
00093 #define WAKEUP_BUTTON_PIN                GPIO_Pin_0
00094 #define WAKEUP_BUTTON_GPIO_PORT          GPIOA
00095 #define WAKEUP_BUTTON_GPIO_CLK           RCC_APB2Periph_GPIOA
00096 #define WAKEUP_BUTTON_EXTI_LINE          EXTI_Line0
00097 #define WAKEUP_BUTTON_EXTI_PORT_SOURCE   GPIO_PortSourceGPIOA
00098 #define WAKEUP_BUTTON_EXTI_PIN_SOURCE    GPIO_PinSource0
00099 #define WAKEUP_BUTTON_EXTI_IRQn          EXTI0_IRQn
00100 /**
00101  * @brief Tamper push-button
00102  */
00103 #define TAMPER_BUTTON_PIN                GPIO_Pin_13
00104 #define TAMPER_BUTTON_GPIO_PORT          GPIOC
00105 #define TAMPER_BUTTON_GPIO_CLK           RCC_APB2Periph_GPIOC
00106 #define TAMPER_BUTTON_EXTI_LINE          EXTI_Line13
00107 #define TAMPER_BUTTON_EXTI_PORT_SOURCE   GPIO_PortSourceGPIOC
00108 #define TAMPER_BUTTON_EXTI_PIN_SOURCE    GPIO_PinSource13
00109 #define TAMPER_BUTTON_EXTI_IRQn          EXTI15_10_IRQn
00110 /**
00111  * @brief Key push-button
00112  */
00113 #define KEY_BUTTON_PIN                   GPIO_Pin_9
00114 #define KEY_BUTTON_GPIO_PORT             GPIOB
00115 #define KEY_BUTTON_GPIO_CLK              RCC_APB2Periph_GPIOB
00116 #define KEY_BUTTON_EXTI_LINE             EXTI_Line9
00117 #define KEY_BUTTON_EXTI_PORT_SOURCE      GPIO_PortSourceGPIOB
00118 #define KEY_BUTTON_EXTI_PIN_SOURCE       GPIO_PinSource9
00119 #define KEY_BUTTON_EXTI_IRQn             EXTI9_5_IRQn
00120 /**
00121  * @brief Joystick Right push-button
00122  */
00123 #define RIGHT_BUTTON_PIN                 GPIO_Pin_1
00124 #define RIGHT_BUTTON_GPIO_PORT           GPIOE
00125 #define RIGHT_BUTTON_GPIO_CLK            RCC_APB2Periph_GPIOE
00126 #define RIGHT_BUTTON_EXTI_LINE           EXTI_Line1
00127 #define RIGHT_BUTTON_EXTI_PORT_SOURCE    GPIO_PortSourceGPIOE
00128 #define RIGHT_BUTTON_EXTI_PIN_SOURCE     GPIO_PinSource1
00129 #define RIGHT_BUTTON_EXTI_IRQn           EXTI1_IRQn
00130 /**
00131  * @brief Joystick Left push-button
00132  */
00133 #define LEFT_BUTTON_PIN                  GPIO_Pin_0
00134 #define LEFT_BUTTON_GPIO_PORT            GPIOE
00135 #define LEFT_BUTTON_GPIO_CLK             RCC_APB2Periph_GPIOE
00136 #define LEFT_BUTTON_EXTI_LINE            EXTI_Line0
00137 #define LEFT_BUTTON_EXTI_PORT_SOURCE     GPIO_PortSourceGPIOE
00138 #define LEFT_BUTTON_EXTI_PIN_SOURCE      GPIO_PinSource0
00139 #define LEFT_BUTTON_EXTI_IRQn            EXTI0_IRQn
00140 /**
00141  * @brief Joystick Up push-button
00142  */
00143 #define UP_BUTTON_PIN                    GPIO_Pin_8
00144 #define UP_BUTTON_GPIO_PORT              GPIOD
00145 #define UP_BUTTON_GPIO_CLK               RCC_APB2Periph_GPIOD
00146 #define UP_BUTTON_EXTI_LINE              EXTI_Line8
00147 #define UP_BUTTON_EXTI_PORT_SOURCE       GPIO_PortSourceGPIOD
00148 #define UP_BUTTON_EXTI_PIN_SOURCE        GPIO_PinSource8
00149 #define UP_BUTTON_EXTI_IRQn              EXTI9_5_IRQn
00150 /**
00151  * @brief Joystick Down push-button
00152  */
00153 #define DOWN_BUTTON_PIN                  GPIO_Pin_14
00154 #define DOWN_BUTTON_GPIO_PORT            GPIOD
00155 #define DOWN_BUTTON_GPIO_CLK             RCC_APB2Periph_GPIOD
00156 #define DOWN_BUTTON_EXTI_LINE            EXTI_Line14
00157 #define DOWN_BUTTON_EXTI_PORT_SOURCE     GPIO_PortSourceGPIOD
00158 #define DOWN_BUTTON_EXTI_PIN_SOURCE      GPIO_PinSource14
00159 #define DOWN_BUTTON_EXTI_IRQn            EXTI15_10_IRQn
00160 /**
00161  * @brief Joystick Sel push-button
00162  */
00163 #define SEL_BUTTON_PIN                   GPIO_Pin_12
00164 #define SEL_BUTTON_GPIO_PORT             GPIOD
00165 #define SEL_BUTTON_GPIO_CLK              RCC_APB2Periph_GPIOD
00166 #define SEL_BUTTON_EXTI_LINE             EXTI_Line12
00167 #define SEL_BUTTON_EXTI_PORT_SOURCE      GPIO_PortSourceGPIOD
00168 #define SEL_BUTTON_EXTI_PIN_SOURCE       GPIO_PinSource12
00169 #define SEL_BUTTON_EXTI_IRQn             EXTI15_10_IRQn
00170 /**
00171   * @}
00172   */
00173
00174 /** @addtogroup STM32100B_EVAL_LOW_LEVEL_COM
00175   * @{
00176   */
00177 #define COMn                             2
00178
00179 /**
00180  * @brief Definition for COM port1, connected to USART1
00181  */
00182 #define EVAL_COM1                        USART1
00183 #define EVAL_COM1_CLK                    RCC_APB2Periph_USART1
00184 #define EVAL_COM1_TX_PIN                 GPIO_Pin_9
00185 #define EVAL_COM1_TX_GPIO_PORT           GPIOA
00186 #define EVAL_COM1_TX_GPIO_CLK            RCC_APB2Periph_GPIOA
00187 #define EVAL_COM1_RX_PIN                 GPIO_Pin_10
00188 #define EVAL_COM1_RX_GPIO_PORT           GPIOA
00189 #define EVAL_COM1_RX_GPIO_CLK            RCC_APB2Periph_GPIOA
00190 #define EVAL_COM1_IRQn                   USART1_IRQn
00191
00192 /**
00193  * @brief Definition for COM port2, connected to USART2 (USART2 pins remapped on GPIOD)
00194  */
00195 #define EVAL_COM2                        USART2
00196 #define EVAL_COM2_CLK                    RCC_APB1Periph_USART2
00197 #define EVAL_COM2_TX_PIN                 GPIO_Pin_5
00198 #define EVAL_COM2_TX_GPIO_PORT           GPIOD
00199 #define EVAL_COM2_TX_GPIO_CLK            RCC_APB2Periph_GPIOD
00200 #define EVAL_COM2_RX_PIN                 GPIO_Pin_6
00201 #define EVAL_COM2_RX_GPIO_PORT           GPIOD
00202 #define EVAL_COM2_RX_GPIO_CLK            RCC_APB2Periph_GPIOD
00203 #define EVAL_COM2_IRQn                   USART2_IRQn
00204
00205 /**
00206   * @}
00207   */
00208
00209 /** @addtogroup STM32100B_EVAL_LOW_LEVEL_SD_SPI
00210   * @{
00211   */
00212 /**
00213   * @brief  SD SPI Interface pins
00214   */
00215 #define SD_SPI                           SPI1
00216 #define SD_SPI_CLK                       RCC_APB2Periph_SPI1
00217 #define SD_SPI_SCK_PIN                   GPIO_Pin_5                  /* PA.05 */
00218 #define SD_SPI_SCK_GPIO_PORT             GPIOA                       /* GPIOA */
00219 #define SD_SPI_SCK_GPIO_CLK              RCC_APB2Periph_GPIOA
00220 #define SD_SPI_MISO_PIN                  GPIO_Pin_6                  /* PA.06 */
00221 #define SD_SPI_MISO_GPIO_PORT            GPIOA                       /* GPIOA */
00222 #define SD_SPI_MISO_GPIO_CLK             RCC_APB2Periph_GPIOA
00223 #define SD_SPI_MOSI_PIN                  GPIO_Pin_7                  /* PA.07 */
00224 #define SD_SPI_MOSI_GPIO_PORT            GPIOA                       /* GPIOA */
00225 #define SD_SPI_MOSI_GPIO_CLK             RCC_APB2Periph_GPIOA
00226 #define SD_CS_PIN                        GPIO_Pin_12                 /* PC.12 */
00227 #define SD_CS_GPIO_PORT                  GPIOC                       /* GPIOC */
00228 #define SD_CS_GPIO_CLK                   RCC_APB2Periph_GPIOC
00229 #define SD_DETECT_PIN                    GPIO_Pin_7                  /* PE.07 */
00230 #define SD_DETECT_GPIO_PORT              GPIOE                       /* GPIOE */
00231 #define SD_DETECT_GPIO_CLK               RCC_APB2Periph_GPIOE
00232
00233 /**
00234   * @}
00235   */
00236
00237 /** @addtogroup STM32100B_EVAL_LOW_LEVEL_M25P_FLASH_SPI
00238   * @{
00239   */
00240 /**
00241   * @brief  M25P FLASH SPI Interface pins
00242   */
00243 #define sFLASH_SPI                       SPI1
00244 #define sFLASH_SPI_CLK                   RCC_APB2Periph_SPI1
00245 #define sFLASH_SPI_SCK_PIN               GPIO_Pin_5                  /* PA.05 */
00246 #define sFLASH_SPI_SCK_GPIO_PORT         GPIOA                       /* GPIOA */
00247 #define sFLASH_SPI_SCK_GPIO_CLK          RCC_APB2Periph_GPIOA
00248 #define sFLASH_SPI_MISO_PIN              GPIO_Pin_6                  /* PA.06 */
00249 #define sFLASH_SPI_MISO_GPIO_PORT        GPIOA                       /* GPIOA */
00250 #define sFLASH_SPI_MISO_GPIO_CLK         RCC_APB2Periph_GPIOA
00251 #define sFLASH_SPI_MOSI_PIN              GPIO_Pin_7                  /* PA.07 */
00252 #define sFLASH_SPI_MOSI_GPIO_PORT        GPIOA                       /* GPIOA */
00253 #define sFLASH_SPI_MOSI_GPIO_CLK         RCC_APB2Periph_GPIOA
00254 #define sFLASH_CS_PIN                    GPIO_Pin_9                  /* PD.09 */
00255 #define sFLASH_CS_GPIO_PORT              GPIOD                       /* GPIOD */
00256 #define sFLASH_CS_GPIO_CLK               RCC_APB2Periph_GPIOD
00257
00258 /**
00259   * @}
00260   */
00261
00262 /** @addtogroup STM32100B_EVAL_LOW_LEVEL_TSENSOR_I2C
00263   * @{
00264   */
00265 /**
00266   * @brief  LM75 Temperature Sensor I2C Interface pins
00267   */
00268 #define LM75_I2C                         I2C1
00269 #define LM75_I2C_CLK                     RCC_APB1Periph_I2C1
00270 #define LM75_I2C_SCL_PIN                 GPIO_Pin_6                  /* PB.06 */
00271 #define LM75_I2C_SCL_GPIO_PORT           GPIOB                       /* GPIOB */
00272 #define LM75_I2C_SCL_GPIO_CLK            RCC_APB2Periph_GPIOB
00273 #define LM75_I2C_SDA_PIN                 GPIO_Pin_7                  /* PB.07 */
00274 #define LM75_I2C_SDA_GPIO_PORT           GPIOB                       /* GPIOB */
00275 #define LM75_I2C_SDA_GPIO_CLK            RCC_APB2Periph_GPIOB
00276 #define LM75_I2C_SMBUSALERT_PIN          GPIO_Pin_5                  /* PB.05 */
00277 #define LM75_I2C_SMBUSALERT_GPIO_PORT    GPIOB                       /* GPIOB */
00278 #define LM75_I2C_SMBUSALERT_GPIO_CLK     RCC_APB2Periph_GPIOB
00279 #define LM75_I2C_DR                      ((uint32_t)0x40005410)
00280
00281 #define LM75_DMA_CLK                     RCC_AHBPeriph_DMA1
00282 #define LM75_DMA_TX_CHANNEL              DMA1_Channel6
00283 #define LM75_DMA_RX_CHANNEL              DMA1_Channel7
00284 #define LM75_DMA_TX_TCFLAG               DMA1_FLAG_TC6
00285 #define LM75_DMA_RX_TCFLAG               DMA1_FLAG_TC7
00286 /**
00287   * @}
00288   */
00289 /**
00290   * @}
00291   */
00292
00293 /** @defgroup STM32100B_EVAL_LOW_LEVEL_Exported_Macros
00294   * @{
00295   */
00296 /**
00297   * @}
00298   */
00299
00300 /** @defgroup STM32100B_EVAL_LOW_LEVEL_Exported_Functions
00301   * @{
00302   */
00303 void STM_EVAL_LEDInit(Led_TypeDef Led);
00304 void STM_EVAL_LEDOn(Led_TypeDef Led);
00305 void STM_EVAL_LEDOff(Led_TypeDef Led);
00306 void STM_EVAL_LEDToggle(Led_TypeDef Led);
00307 void STM_EVAL_PBInit(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode);
00308 uint32_t STM_EVAL_PBGetState(Button_TypeDef Button);
00309 void STM_EVAL_COMInit(COM_TypeDef COM, USART_InitTypeDef* USART_InitStruct);
00310 void SD_LowLevel_DeInit(void);
00311 void SD_LowLevel_Init(void);
00312 void sFLASH_LowLevel_DeInit(void);
00313 void sFLASH_LowLevel_Init(void);
00314 void LM75_LowLevel_DeInit(void);
00315 void LM75_LowLevel_Init(void);
00316 /**
00317   * @}
00318   */
00319
00320 #ifdef __cplusplus
00321 }
00322 #endif
00323
00324 #endif /* __STM32100B_EVAL_H */
00325 /**
00326   * @}
00327   */
00328
00329 /**
00330   * @}
00331   */
00332
00333 /**
00334   * @}
00335   */
00336
00337 /**
00338   * @}
00339   */
00340
00341 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32100b_eval_cec.c Source File

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • STM32100B_EVAL

stm32100b_eval_cec.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32100b_eval_cec.c
00004   * @author  MCD Application Team
00005   * @version V4.5.0
00006   * @date    07-March-2011
00007   * @brief   This file provides all the STM32100B-EVAL HDMI-CEC firmware functions.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32100b_eval_cec.h"
00024
00025 /** @addtogroup Utilities
00026   * @{
00027   */
00028
00029 /** @addtogroup STM32_EVAL
00030   * @{
00031   */
00032
00033 /** @addtogroup STM32100B_EVAL
00034   * @{
00035   */
00036
00037 /** @defgroup STM32100B_EVAL_CEC
00038   * @brief This file includes the CEC Stack driver for HDMI-CEC Module
00039   *        of STM32100B-EVAL board.
00040   * @{
00041   */
00042
00043 /** @defgroup STM32100B_EVAL_CEC_Private_Types
00044   * @{
00045   */
00046
00047 /**
00048   * @}
00049   */
00050
00051 /** @defgroup STM32100B_EVAL_CEC_Private_Defines
00052   * @{
00053   */
00054
00055
00056 /**
00057   * @}
00058   */
00059
00060 /** @defgroup STM32100B_EVAL_CEC_Private_Macros
00061   * @{
00062   */
00063 /**
00064   * @}
00065   */
00066
00067 /** @defgroup STM32100B_EVAL_CEC_Private_Variables
00068   * @{
00069   */
00070
00071 __IO uint32_t ReceivedFrame = 0;
00072 __IO uint32_t SendFrame = 0;
00073 __IO uint32_t BufferCount = 0, TxCounter = 0, RxCounter = 0;
00074 __IO uint8_t BufferPointer[15];
00075 __IO uint32_t ReceiveStatus = 0;
00076 __IO uint32_t SendStatus = 0;
00077 __IO uint8_t TransErrorCode = 0;
00078 __IO uint8_t RecepErrorCode = 0;
00079 __IO uint8_t MyLogicalAddress = 0;
00080 __IO uint16_t MyPhysicalAddress = 0;
00081 __IO uint8_t DeviceType = 0;
00082 #ifdef HDMI_CEC_USE_DDC
00083 __IO uint8_t pBuffer[256];
00084 __IO uint16_t NumByteToRead = 255;
00085 #endif
00086 __IO uint8_t CECDevicesNumber = 0;
00087
00088 HDMI_CEC_Message HDMI_CEC_TX_MessageStructPrivate;
00089 HDMI_CEC_Message HDMI_CEC_RX_MessageStructPrivate;
00090 HDMI_CEC_Message HDMI_CEC_TX_MessageStructure;
00091
00092 __IO uint8_t FeatureOpcode = 0;
00093 __IO uint8_t AbortReason = 0;
00094 __IO uint8_t DeviceCount = 0;
00095
00096 HDMI_CEC_Map HDMI_CEC_MapStruct;
00097 HDMI_CEC_Map HDMI_CEC_DeviceMap[14];
00098
00099 /* CEC follower addresses */
00100 uint8_t* HDMI_CEC_Follower_String[13][2] =
00101   {
00102     {(uint8_t *)"         TV         ", (uint8_t *)"0"},
00103     {(uint8_t *)"Recording Device 1  ", (uint8_t *)"0"},
00104     {(uint8_t *)"Recording Device 2  ", (uint8_t *)"0"},
00105     {(uint8_t *)"    Tuner 1         ", (uint8_t *)"0"},
00106     {(uint8_t *)" Playback Device 1  ", (uint8_t *)"0"},
00107     {(uint8_t *)"   Audio System     ", (uint8_t *)"0"},
00108     {(uint8_t *)"    Tuner 2         ", (uint8_t *)"0"},
00109     {(uint8_t *)"    Tuner 3         ", (uint8_t *)"0"},
00110     {(uint8_t *)" Playback Device 2  ", (uint8_t *)"0"},
00111     {(uint8_t *)"Recording Device 3  ", (uint8_t *)"0"},
00112     {(uint8_t *)"      Tuner 4       ", (uint8_t *)"0"},
00113     {(uint8_t *)" Playback Device 3  ", (uint8_t *)"0"},
00114     {(uint8_t *)"     Broadcast      ", (uint8_t *)"1"}
00115   };
00116
00117 /**
00118   * @}
00119   */
00120
00121
00122 /** @defgroup STM32100B_EVAL_CEC_Private_Function_Prototypes
00123   * @{
00124   */
00125 static HDMI_CEC_Error PhysicalAddressDiscovery(void);
00126 static HDMI_CEC_Error LogicalAddressAllocation(void);
00127
00128
00129 /**
00130   * @}
00131   */
00132
00133
00134 /** @defgroup STM32100B_EVAL_CEC_Private_Functions
00135   * @{
00136   */
00137
00138 /**
00139   * @brief  Initializes the HDMI CEC.
00140   * @param  None
00141   * @retval HDMI_CEC_Error: CEC Error code
00142   */
00143 HDMI_CEC_Error HDMI_CEC_Init(void)
00144 {
00145   GPIO_InitTypeDef GPIO_InitStructure;
00146   CEC_InitTypeDef CEC_InitStructure;
00147   HDMI_CEC_Error errorstatus = HDMI_CEC_OK;
00148   uint8_t sendcount = 0;
00149
00150 #ifdef HDMI_CEC_USE_DDC
00151   I2C_InitTypeDef  I2C_InitStructure;
00152   /* Enable CEC_I2C clocks */
00153   RCC_APB1PeriphClockCmd(HDMI_CEC_I2C_CLK, ENABLE);
00154
00155   /* Enable CEC_I2C_GPIO and CEC_HPD_GPIO clocks */
00156   RCC_APB2PeriphClockCmd(HDMI_CEC_I2C_GPIO_CLK | HDMI_CEC_HPD_GPIO_CLK, ENABLE);
00157 #endif
00158
00159   /* Enable CEC clocks */
00160   RCC_APB1PeriphClockCmd(RCC_APB1Periph_CEC, ENABLE);
00161
00162   /* Enable CEC_LINE_GPIO clocks */
00163   RCC_APB2PeriphClockCmd(HDMI_CEC_LINE_GPIO_CLK, ENABLE);
00164
00165   /* Configure CEC_LINE_GPIO as Output open drain */
00166   GPIO_InitStructure.GPIO_Pin = HDMI_CEC_LINE_PIN;
00167   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00168   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_OD;
00169   GPIO_Init(HDMI_CEC_LINE_GPIO_PORT, &GPIO_InitStructure);
00170
00171 #ifdef HDMI_CEC_USE_DDC
00172   /* Configure CEC_I2C_SCL_PIN and CEC_I2C_SDA_PIN  as Output open drain */
00173   GPIO_InitStructure.GPIO_Pin = HDMI_CEC_I2C_SCL_PIN | HDMI_CEC_I2C_SDA_PIN;
00174   GPIO_Init(HDMI_CEC_I2C_GPIO_PORT, &GPIO_InitStructure);
00175
00176 /* This configuration is only when the HDMI CEC is configured as source.
00177    The HDMI source has to provide the +5V Power signal to the sink.
00178    On STM32100B-EVAL borad, you have to solder the SB4 Solder bridge.
00179    Then, the source will wait for HPD signal to be asserted from the sink.
00180    Once the HPD signal is detected the source shall read the EDID structure
00181    throuhgh the DDC channel. */
00182   /* Configure CEC_HPD_GPIO as Input pull down */
00183   GPIO_InitStructure.GPIO_Pin = HDMI_CEC_HPD_PIN;
00184   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD;
00185   GPIO_Init(HDMI_CEC_HPD_GPIO_PORT, &GPIO_InitStructure);
00186
00187
00188 /* This configuration is only when the HDMI CEC is configured as sink.
00189    The HDMI sink has to wait for the +5V Power signal from the source.
00190    On STM32100B-EVAL borad, SB4 Solder bridge should be open (default configuration).
00191    Then, the sink will assert the HPD signal to inform the source that the EDID
00192    is ready for read through DDC channel. In this implementation, the EDID structure
00193    is not implemented. */
00194 /*  GPIO_InitStructure.GPIO_Pin = HDMI_CEC_HPD_PIN;
00195   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
00196   GPIO_Init(HDMI_CEC_HPD_GPIO_PORT, &GPIO_InitStructure);
00197
00198   HDMI_CEC_HPD_HIGH(); // Set the Hot plug detect signal */
00199
00200   /* Enable CEC_I2C */
00201   I2C_Cmd(HDMI_CEC_I2C, ENABLE);
00202
00203   /* I2C configuration */
00204   I2C_InitStructure.I2C_Mode = I2C_Mode_I2C;
00205   I2C_InitStructure.I2C_DutyCycle = I2C_DutyCycle_2;
00206   I2C_InitStructure.I2C_OwnAddress1 = HDMI_CEC_I2C_SLAVE_ADDRESS7;
00207   I2C_InitStructure.I2C_Ack = I2C_Ack_Enable;
00208   I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
00209   I2C_InitStructure.I2C_ClockSpeed = HDMI_CEC_I2C_CLOCK_SPEED;
00210   I2C_Init(HDMI_CEC_I2C, &I2C_InitStructure);
00211 #endif
00212
00213   /* Physical Address discovery */
00214   errorstatus = PhysicalAddressDiscovery();
00215
00216   if (errorstatus != HDMI_CEC_OK)
00217   {
00218     /* Device not connected (Physical Address lost) */
00219     return(errorstatus);
00220   }
00221
00222
00223   /* CEC DeInit */
00224   CEC_DeInit();
00225
00226   /* Configure CEC */
00227   CEC_InitStructure.CEC_BitTimingMode = CEC_BitTimingStdMode;
00228   CEC_InitStructure.CEC_BitPeriodMode = CEC_BitPeriodStdMode;
00229   CEC_Init(&CEC_InitStructure);
00230
00231   /* Set Prescaler value for APB1 clock = 24MHz */
00232   CEC_SetPrescaler(0x4AF);
00233
00234   /* Enable CEC */
00235   CEC_Cmd(ENABLE);
00236
00237   /* Logical Address Allocation */
00238   sendcount = 0;
00239   errorstatus = LogicalAddressAllocation();
00240
00241   while ((errorstatus != HDMI_CEC_OK) && sendcount < 0x5)
00242   {
00243     sendcount++;
00244     errorstatus = LogicalAddressAllocation();
00245   }
00246
00247   if (errorstatus != HDMI_CEC_OK)
00248   {
00249     /* Device Unregistred */
00250     return(errorstatus);
00251   }
00252
00253   HDMI_CEC_CheckConnectedDevices();
00254
00255   /* Set the CEC initiator address */
00256   CEC_OwnAddressConfig(MyLogicalAddress);
00257
00258   /* Activate CEC interrupts associated to the set of RBTF,RERR, TBTF, TERR flags */
00259   CEC_ITConfig(ENABLE);
00260
00261   /* Report physical address*/
00262   errorstatus = HDMI_CEC_ReportPhysicalAddress();
00263   sendcount = 0;
00264
00265   while ((errorstatus != HDMI_CEC_OK) && sendcount < 0x5)
00266   {
00267     sendcount++;
00268     errorstatus = HDMI_CEC_ReportPhysicalAddress();
00269   }
00270
00271   if (errorstatus != HDMI_CEC_OK)
00272   {
00273     /* Device Unregistred */
00274     return(errorstatus);
00275   }
00276
00277   return errorstatus;
00278 }
00279
00280 /**
00281   * @brief  Transmit message by taking  data from typedef struct CEC_Meassage
00282   * @param  CEC_TX_MessageStructure: pointer to an CEC_Message structure that contains
00283   *         the message to be sent.
00284   * @retval HDMI_CEC_Error: CEC Error code
00285   */
00286 HDMI_CEC_Error HDMI_CEC_TransmitMessage(HDMI_CEC_Message *HDMI_CEC_TX_MessageStructure)
00287 {
00288   HDMI_CEC_Error errorstatus = HDMI_CEC_OK;
00289   __IO uint32_t count = 0, j = 0;
00290
00291   SendFrame = 0;
00292   SendStatus = 0;
00293   TxCounter = 0;
00294   BufferCount = 0;
00295
00296   HDMI_CEC_TX_MessageStructPrivate =  *HDMI_CEC_TX_MessageStructure;
00297
00298   /* Initialize BufferPointer */
00299   for (j = 0; j < 15; j++)
00300   {
00301     BufferPointer[j] = 0;
00302   }
00303
00304   BufferPointer[0] =  HDMI_CEC_TX_MessageStructPrivate.Opcode;
00305
00306   for (BufferCount = 1; BufferCount < HDMI_CEC_TX_MessageStructPrivate.TxMessageLength + 1; BufferCount++)
00307   {
00308     BufferPointer[BufferCount] =  HDMI_CEC_TX_MessageStructPrivate.Operande[BufferCount-1];
00309   }
00310
00311   CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR);
00312
00313   /* Write single Data in the TX Buffer to Transmit through the CEC peripheral */
00314   CEC_SendDataByte(HDMI_CEC_TX_MessageStructPrivate.Header);
00315
00316   /* Initiate Message Transmission */
00317   CEC_StartOfMessage();
00318
00319   while ((SendFrame == 0) && (count < HDMI_CEC_TIMEOUT_VALUE))
00320   {
00321     count++;
00322   }
00323   if (count >= HDMI_CEC_TIMEOUT_VALUE)
00324   {
00325     errorstatus = HDMI_CEC_TIMEOUT;
00326     return(errorstatus);
00327   }
00328
00329   if (SendStatus == 0)
00330   {
00331     errorstatus = (HDMI_CEC_Error) TransErrorCode;
00332   }
00333
00334   return errorstatus;
00335 }
00336
00337
00338 /**
00339   * @brief  Get the ESR register status.
00340   * @param  None
00341   * @retval HDMI_CEC_Error: CEC Error code
00342   */
00343 HDMI_CEC_Error HDMI_CEC_GetErrorStatus (void)
00344 {
00345   HDMI_CEC_Error errorstatus = HDMI_CEC_OK;
00346
00347   /* Bit timing error case*/
00348   if (CEC_GetFlagStatus(CEC_FLAG_BTE) != RESET)
00349   {
00350     errorstatus = HDMI_CEC_BIT_TIMING;
00351   }
00352   /* Bit period error case */
00353   if (CEC_GetFlagStatus(CEC_FLAG_BPE) != RESET)
00354   {
00355     errorstatus = HDMI_CEC_BIT_PERIOD;
00356   }
00357   /* Recieve error case */
00358   if (CEC_GetFlagStatus(CEC_FLAG_RBTFE) != RESET)
00359   {
00360     errorstatus = HDMI_CEC_RX_BLOCK_FINISHED;
00361   }
00362   /* Start bit error case*/
00363   if (CEC_GetFlagStatus(CEC_FLAG_SBE) != RESET)
00364   {
00365     errorstatus = HDMI_CEC_START_BIT;
00366   }
00367   /* Acknowledge error case*/
00368   if (CEC_GetFlagStatus(CEC_FLAG_ACKE) != RESET)
00369   {
00370     errorstatus = HDMI_CEC_BLOCK_ACKNOWLEDGE;
00371   }
00372   /* Line error case */
00373   if (CEC_GetFlagStatus(CEC_FLAG_LINE) != RESET)
00374   {
00375     errorstatus = HDMI_CEC_LINE;
00376   }
00377   /* Transfert error case*/
00378   if (CEC_GetFlagStatus(CEC_FLAG_TBTFE) != RESET)
00379   {
00380     errorstatus = HDMI_CEC_TX_BLOCK_FINISHED;
00381   }
00382   /* Clear All errors */
00383   CEC_ClearFlag(CEC_FLAG_RERR);
00384   CEC_ClearFlag(CEC_FLAG_TERR);
00385   return errorstatus;
00386 }
00387
00388 /**
00389   * @brief  Allows to process all the interrupts that are high.
00390   * @param  None
00391   * @retval None
00392   */
00393 void HDMI_CEC_ProcessIRQSrc(void)
00394 {
00395   /********************** Reception *********************************************/
00396   /* Check if a reception error occured */
00397   if (CEC_GetFlagStatus(CEC_FLAG_RERR))
00398   {
00399     /* Set receive status bit (Error) */
00400     ReceiveStatus  = 0;
00401     ReceivedFrame  = 1;
00402     RecepErrorCode = HDMI_CEC_GetErrorStatus();
00403     CEC_ClearFlag(CEC_FLAG_RERR | CEC_FLAG_RSOM | CEC_FLAG_REOM  | CEC_FLAG_RBTF);
00404   }
00405   else if (CEC_GetFlagStatus(CEC_FLAG_RBTF))
00406   {
00407     /* Check if the byte received is the last one of the message */
00408     if (CEC_GetFlagStatus(CEC_FLAG_REOM))
00409     {
00410       HDMI_CEC_RX_MessageStructPrivate.Operande[RxCounter-1] = CEC_ReceiveDataByte();
00411       HDMI_CEC_RX_MessageStructPrivate.RxMessageLength = RxCounter;
00412       ReceiveStatus = SUCCESS;
00413       ReceivedFrame = 1;
00414     }
00415     /* Check if the byte received is a Header */
00416     else if (CEC_GetFlagStatus(CEC_FLAG_RSOM))
00417     {
00418       ReceiveStatus = 0;
00419       HDMI_CEC_RX_MessageStructPrivate.Header = CEC_ReceiveDataByte();
00420       RxCounter = 0;
00421     }
00422     /* Receive each byte except header in the reception buffer */
00423     else
00424     {
00425       if (RxCounter != 0)
00426       {
00427         HDMI_CEC_RX_MessageStructPrivate.Operande[RxCounter-1] = CEC_ReceiveDataByte();
00428         RxCounter++;
00429       }
00430       else
00431       {
00432         HDMI_CEC_RX_MessageStructPrivate.Opcode = CEC_ReceiveDataByte();
00433         RxCounter++;
00434       }
00435
00436     }
00437     /* Clear all reception flags */
00438     CEC_ClearFlag(CEC_FLAG_RSOM | CEC_FLAG_REOM  | CEC_FLAG_RBTF);
00439   }
00440
00441   /********************** Transmission ******************************************/
00442   /* Check if a transmission error occured */
00443   if (CEC_GetFlagStatus(CEC_FLAG_TERR))
00444   {
00445     TransErrorCode = HDMI_CEC_GetErrorStatus();
00446     CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR);
00447     SendFrame = 1;
00448     SendStatus = 0;
00449   }
00450   /* Check if end of message bit is set in the data to be transmitted */
00451   else if (CEC_GetFlagStatus(CEC_FLAG_TEOM))
00452   {
00453     CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_RBTF);
00454     CEC_EndOfMessageCmd(DISABLE);
00455     SendFrame = 1;
00456     SendStatus = SUCCESS;
00457   }
00458   /* Check if data byte has been sent */
00459   else if (CEC_GetFlagStatus(CEC_FLAG_TBTRF))
00460   {
00461     /* Set EOM bit if the byte to be transmitted is the last one of the TransmitBuffer */
00462     if (TxCounter == (HDMI_CEC_TX_MessageStructPrivate.TxMessageLength))
00463     {
00464       CEC_SendDataByte(BufferPointer[TxCounter]);
00465       TxCounter++;
00466       CEC_ClearFlag(CEC_FLAG_TBTRF);
00467       CEC_EndOfMessageCmd(ENABLE);
00468     }
00469     else
00470     {
00471       /* Put the byte in the TX Buffer */
00472       CEC_SendDataByte(BufferPointer[TxCounter]);
00473       TxCounter++;
00474       CEC_ClearFlag(CEC_FLAG_TBTRF);
00475     }
00476   }
00477 }
00478
00479 /**
00480   * @brief  Report physical address to all other devices thus allowing any
00481             device to create a map of the network.
00482   * @param  None
00483   * @retval HDMI_CEC_Error: CEC Error code.
00484   */
00485 HDMI_CEC_Error HDMI_CEC_ReportPhysicalAddress(void)
00486 {
00487   HDMI_CEC_Error errorstatus = HDMI_CEC_OK;
00488   HDMI_CEC_Message HDMI_CEC_TX_Message;
00489
00490   HDMI_CEC_TX_Message.Header = ((MyLogicalAddress << 4) | 0xF);
00491   HDMI_CEC_TX_Message.Opcode = HDMI_CEC_OPCODE_REPORT_PHYSICAL_ADDRESS;
00492   HDMI_CEC_TX_Message.Operande[0] = MyPhysicalAddress >> 8;
00493   HDMI_CEC_TX_Message.Operande[1] = MyPhysicalAddress & 0xFF;
00494   HDMI_CEC_TX_Message.Operande[2] = DeviceType;
00495   HDMI_CEC_TX_Message.TxMessageLength = 0x03;
00496
00497   errorstatus = HDMI_CEC_TransmitMessage(&HDMI_CEC_TX_Message);
00498
00499   return  errorstatus;
00500 }
00501
00502 /**
00503   * @brief  Handle CEC command receive callback.
00504   *         When receiving the STANDBY Opcode commande, the system is entred in
00505   *         Stop mode and when wakeup, the PLL is configured as system clock and
00506   *         the HSI is selected as PLL source.
00507   * @param  None
00508   * @retval None
00509   */
00510 void HDMI_CEC_CommandCallBack(void)
00511 {
00512   uint8_t i = 0, sendcount = 0;
00513   HDMI_CEC_Error errorstatus = HDMI_CEC_OK;
00514   EXTI_InitTypeDef EXTI_InitStructure;
00515
00516   switch (HDMI_CEC_RX_MessageStructPrivate.Opcode)
00517   {
00518     case HDMI_CEC_OPCODE_REPORT_PHYSICAL_ADDRESS:
00519       HDMI_CEC_MapStruct.PhysicalAddress_A = HDMI_CEC_RX_MessageStructPrivate.Operande[1] >> 4;
00520       HDMI_CEC_MapStruct.PhysicalAddress_B = HDMI_CEC_RX_MessageStructPrivate.Operande[1] & 0x0F;
00521       HDMI_CEC_MapStruct.PhysicalAddress_C = HDMI_CEC_RX_MessageStructPrivate.Operande[0] >> 4;
00522       HDMI_CEC_MapStruct.PhysicalAddress_D = HDMI_CEC_RX_MessageStructPrivate.Operande[0] & 0x0F;
00523       HDMI_CEC_MapStruct.LogicalAddress = (HDMI_CEC_RX_MessageStructPrivate.Header >> 0x4) & 0x0F;
00524       HDMI_CEC_MapStruct.DeviceType = HDMI_CEC_RX_MessageStructPrivate.Operande[2];
00525       HDMI_CEC_DeviceMap[DeviceCount] = HDMI_CEC_MapStruct;
00526       HDMI_CEC_Follower_String[(HDMI_CEC_DeviceMap[DeviceCount].LogicalAddress)][1] = (uint8_t *)"1";
00527       DeviceCount++;
00528       break;
00529
00530     case HDMI_CEC_OPCODE_STANDBY:
00531       /* CEC Line */
00532       GPIO_EXTILineConfig(GPIO_PortSourceGPIOB, GPIO_PinSource8);
00533       /* Configure the CEC Line as EXTI Line on Falling Edge */
00534       EXTI_ClearITPendingBit(EXTI_Line8);
00535       EXTI_InitStructure.EXTI_Line = EXTI_Line8;
00536       EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
00537       EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling;
00538       EXTI_InitStructure.EXTI_LineCmd = ENABLE;
00539       EXTI_Init(&EXTI_InitStructure);
00540       /* Request to enter Stop mode */
00541       PWR_EnterSTOPMode(PWR_Regulator_ON, PWR_STOPEntry_WFI);
00542
00543       /* Disable the CEC EXTI Line */
00544       EXTI_InitStructure.EXTI_LineCmd = DISABLE;
00545       EXTI_Init(&EXTI_InitStructure);
00546       /* Configure the PLL Source */
00547       RCC_PLLConfig(RCC_PLLSource_HSI_Div2, RCC_PLLMul_6);
00548
00549       /* Enable PLL */
00550       RCC_PLLCmd(ENABLE);
00551
00552       /* Wait till PLL is ready */
00553       while(RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET)
00554       {
00555       }
00556
00557       /* Select PLL as system clock source */
00558       RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
00559
00560       /* Wait till PLL is used as system clock source */
00561       while(RCC_GetSYSCLKSource() != 0x08)
00562       {
00563       }
00564       break;
00565
00566     case HDMI_CEC_OPCODE_GET_CEC_VERSION:
00567       /* Send the Used CEC version */
00568       HDMI_CEC_TX_MessageStructPrivate.Header = ((MyLogicalAddress << 4) | HDMI_CEC_RX_MessageStructPrivate.Header >> 4);
00569       HDMI_CEC_TX_MessageStructPrivate.Opcode = HDMI_CEC_OPCODE_CEC_VERSION;
00570       HDMI_CEC_TX_MessageStructPrivate.Operande[0] = HDMI_CEC_VERSION; /* CEC Version */
00571       HDMI_CEC_TX_MessageStructPrivate.TxMessageLength = 0x01;
00572       errorstatus = HDMI_CEC_TransmitMessage(&HDMI_CEC_TX_MessageStructPrivate);
00573
00574       /* Retransmit message until 5 time */
00575       while ((errorstatus != HDMI_CEC_OK) && sendcount < 0x5)
00576       {
00577         sendcount++;
00578         errorstatus = HDMI_CEC_TransmitMessage(&HDMI_CEC_TX_MessageStructPrivate);
00579       }
00580       break;
00581
00582     case HDMI_CEC_OPCODE_GIVE_PHYSICAL_ADDRESS:
00583       /* Send the Physical address */
00584       errorstatus = HDMI_CEC_ReportPhysicalAddress();
00585       sendcount = 0;
00586       /* Retransmit message until 5 time */
00587       while ((errorstatus != HDMI_CEC_OK) && sendcount < 0x5)
00588       {
00589         sendcount++;
00590         errorstatus = HDMI_CEC_ReportPhysicalAddress();
00591       }
00592       break;
00593
00594     case HDMI_CEC_OPCODE_FEATURE_ABORT:
00595       /* The device doesn't support the requested message type, or that it cannot
00596       execute it at the present time. */
00597       FeatureOpcode = HDMI_CEC_RX_MessageStructPrivate.Operande[0];
00598       AbortReason = HDMI_CEC_RX_MessageStructPrivate.Operande[1];
00599       break;
00600
00601     case HDMI_CEC_OPCODE_GIVE_OSD_NAME:
00602       /* Send the OSD name = STM32100B CEC*/
00603       HDMI_CEC_TX_MessageStructPrivate.Header = ((MyLogicalAddress << 4) | HDMI_CEC_RX_MessageStructPrivate.Header >> 4);
00604       HDMI_CEC_TX_MessageStructPrivate.Opcode = HDMI_CEC_OPCODE_SET_OSD_NAME;
00605       /* STM32100B*/
00606       HDMI_CEC_TX_MessageStructPrivate.Operande[0] = 0x53;
00607       HDMI_CEC_TX_MessageStructPrivate.Operande[1] = 0x54;
00608       HDMI_CEC_TX_MessageStructPrivate.Operande[2] = 0x4D;
00609       HDMI_CEC_TX_MessageStructPrivate.Operande[3] = 0x33;
00610       HDMI_CEC_TX_MessageStructPrivate.Operande[4] = 0x32;
00611       HDMI_CEC_TX_MessageStructPrivate.Operande[5] = 0x31;
00612       HDMI_CEC_TX_MessageStructPrivate.Operande[6] = 0x30;
00613       HDMI_CEC_TX_MessageStructPrivate.Operande[7] = 0x30;
00614       HDMI_CEC_TX_MessageStructPrivate.Operande[8] = 0x42;
00615       HDMI_CEC_TX_MessageStructPrivate.Operande[9] = 0x20;
00616       /* CEC */
00617       HDMI_CEC_TX_MessageStructPrivate.Operande[10] = 0x43;
00618       HDMI_CEC_TX_MessageStructPrivate.Operande[11] = 0x45;
00619       HDMI_CEC_TX_MessageStructPrivate.Operande[12] = 0x43;
00620       HDMI_CEC_TX_MessageStructPrivate.TxMessageLength = 13;
00621       errorstatus = HDMI_CEC_TransmitMessage(&HDMI_CEC_TX_MessageStructPrivate);
00622       sendcount = 0;
00623       /* Retransmit message until 5 time */
00624       while ((errorstatus != HDMI_CEC_OK) && sendcount < 0x5)
00625       {
00626         sendcount++;
00627         errorstatus = HDMI_CEC_TransmitMessage(&HDMI_CEC_TX_MessageStructPrivate);
00628       }
00629       break;
00630
00631     case HDMI_CEC_OPCODE_ROUTING_CHANGE:
00632       for (i = 0;i < 0x14;i++)
00633       {
00634         if ((HDMI_CEC_DeviceMap[i].PhysicalAddress_A == HDMI_CEC_RX_MessageStructPrivate.Operande[1] >> 4) &&
00635             (HDMI_CEC_DeviceMap[i].PhysicalAddress_B == HDMI_CEC_RX_MessageStructPrivate.Operande[1]&0x0F) &&
00636             (HDMI_CEC_DeviceMap[i].PhysicalAddress_C == HDMI_CEC_RX_MessageStructPrivate.Operande[0] >> 4) &&
00637             (HDMI_CEC_DeviceMap[i].PhysicalAddress_D == HDMI_CEC_RX_MessageStructPrivate.Operande[0]&0x0F))
00638         {
00639           HDMI_CEC_MapStruct.LogicalAddress = (HDMI_CEC_RX_MessageStructPrivate.Header >> 0x4) & 0x0F;
00640           HDMI_CEC_MapStruct.DeviceType = HDMI_CEC_RX_MessageStructPrivate.Operande[2];
00641           HDMI_CEC_DeviceMap[i] = HDMI_CEC_MapStruct;
00642         }
00643       }
00644       break;
00645
00646     default:
00647       /* Send Abort feature*/
00648       HDMI_CEC_TX_MessageStructPrivate.Header = ((MyLogicalAddress << 4) | HDMI_CEC_RX_MessageStructPrivate.Header >> 4);
00649       HDMI_CEC_TX_MessageStructPrivate.Opcode = HDMI_CEC_OPCODE_FEATURE_ABORT;
00650       HDMI_CEC_TX_MessageStructPrivate.Operande[0] = 0x02; /* defines command to be performed */
00651       HDMI_CEC_TX_MessageStructPrivate.Operande[1] = HDMI_CEC_REFUSED; /* Reason for abort feature */
00652       HDMI_CEC_TX_MessageStructPrivate.TxMessageLength = 0x02;
00653       errorstatus = HDMI_CEC_TransmitMessage(&HDMI_CEC_TX_MessageStructPrivate);
00654       sendcount = 0;
00655       /* Retransmit message until 5 time */
00656       while ((errorstatus != HDMI_CEC_OK) && sendcount < 0x5)
00657       {
00658         sendcount++;
00659         errorstatus = HDMI_CEC_TransmitMessage(&HDMI_CEC_TX_MessageStructPrivate);
00660       }
00661       break;
00662
00663   }
00664 }
00665
00666 /**
00667   * @brief  Check the connected CEC devices.
00668   * @param  None
00669   * @retval HDMI_CEC_Error
00670   */
00671 HDMI_CEC_Error HDMI_CEC_CheckConnectedDevices(void)
00672 {
00673   HDMI_CEC_Error errorstatus = HDMI_CEC_OK;
00674   uint32_t count = 0, i = 1;
00675
00676   /*----------------------------- TV device  ---------------------------*/
00677   CEC_OwnAddressConfig(MyLogicalAddress); /* Own address = MyLogicalAddress */
00678
00679   CEC_EndOfMessageCmd(ENABLE);
00680
00681   CEC_SendDataByte((MyLogicalAddress << 4) | 0x0);
00682
00683   /* Start of message */
00684   CEC_StartOfMessage();
00685
00686   /* Wait till the header message is sent */
00687   while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
00688   {
00689     count++;
00690   }
00691
00692   if (count >= HDMI_CEC_TIMEOUT_VALUE)
00693   {
00694     errorstatus = HDMI_CEC_TIMEOUT;
00695     return(errorstatus);
00696   }
00697
00698   errorstatus = HDMI_CEC_GetErrorStatus();
00699
00700   if (errorstatus == HDMI_CEC_OK)
00701   {
00702     HDMI_CEC_Follower_String[0][1] = (uint8_t *)"1";
00703     i++;
00704     errorstatus = HDMI_CEC_OK;
00705   }
00706
00707   /* Clear CEC CSR register */
00708   CEC_ClearFlag(CEC_FLAG_TBTRF);
00709   CEC_EndOfMessageCmd(DISABLE);
00710
00711   /*----------------------------- Recording device 1 ---------------------------*/
00712   CEC_OwnAddressConfig(MyLogicalAddress); /* Own address = MyLogicalAddress */
00713
00714   CEC_EndOfMessageCmd(ENABLE);
00715
00716   CEC_SendDataByte((MyLogicalAddress << 4) | 0x1);
00717
00718   /* Start of message */
00719   CEC_StartOfMessage();
00720
00721   /* Wait till the header message is sent */
00722   while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
00723   {
00724     count++;
00725   }
00726
00727   if (count >= HDMI_CEC_TIMEOUT_VALUE)
00728   {
00729     errorstatus = HDMI_CEC_TIMEOUT;
00730     return(errorstatus);
00731   }
00732
00733   errorstatus = HDMI_CEC_GetErrorStatus();
00734
00735   if (errorstatus == HDMI_CEC_OK)
00736   {
00737     HDMI_CEC_Follower_String[1][1] = (uint8_t *)"1";
00738     i++;
00739     errorstatus = HDMI_CEC_OK;
00740   }
00741
00742   /* Clear CEC CSR register */
00743   CEC_ClearFlag(CEC_FLAG_TBTRF);
00744   CEC_EndOfMessageCmd(DISABLE);
00745   /*----------------------------- Recording device 2 ---------------------------*/
00746   CEC_OwnAddressConfig(MyLogicalAddress); /* Own address = MyLogicalAddress */
00747
00748   CEC_EndOfMessageCmd(ENABLE);
00749
00750   CEC_SendDataByte((MyLogicalAddress << 4) | 0x2);
00751
00752   /* Start of message */
00753   CEC_StartOfMessage();
00754
00755   /* Wait till the header message is sent */
00756   while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
00757   {
00758     count++;
00759   }
00760
00761   if (count >= HDMI_CEC_TIMEOUT_VALUE)
00762   {
00763     errorstatus = HDMI_CEC_TIMEOUT;
00764     return(errorstatus);
00765   }
00766
00767   errorstatus = HDMI_CEC_GetErrorStatus();
00768
00769   if (errorstatus == HDMI_CEC_OK)
00770   {
00771     HDMI_CEC_Follower_String[2][1] = (uint8_t *)"1";
00772     i++;
00773     errorstatus = HDMI_CEC_OK;
00774   }
00775
00776   /* Clear CEC CSR register */
00777   CEC_ClearFlag(CEC_FLAG_TBTRF);
00778   CEC_EndOfMessageCmd(DISABLE);
00779
00780   /*----------------------------- Tuner 1 ---------------------------*/
00781   CEC_OwnAddressConfig(MyLogicalAddress); /* Own address = MyLogicalAddress */
00782
00783   CEC_EndOfMessageCmd(ENABLE);
00784
00785   CEC_SendDataByte((MyLogicalAddress << 4) | 0x3);
00786
00787   /* Start of message */
00788   CEC_StartOfMessage();
00789
00790   /* Wait till the header message is sent */
00791   while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
00792   {
00793     count++;
00794   }
00795
00796   if (count >= HDMI_CEC_TIMEOUT_VALUE)
00797   {
00798     errorstatus = HDMI_CEC_TIMEOUT;
00799     return(errorstatus);
00800   }
00801
00802   errorstatus = HDMI_CEC_GetErrorStatus();
00803
00804   if (errorstatus == HDMI_CEC_OK)
00805   {
00806     HDMI_CEC_Follower_String[3][1] = (uint8_t *)"1";
00807     i++;
00808     errorstatus = HDMI_CEC_OK;
00809   }
00810   /* Clear CEC CSR register */
00811   CEC_ClearFlag(CEC_FLAG_TBTRF);
00812   CEC_EndOfMessageCmd(DISABLE);
00813   /*----------------------------- Playback device 1 ---------------------------*/
00814   CEC_OwnAddressConfig(MyLogicalAddress); /* Own address = MyLogicalAddress */
00815
00816   CEC_EndOfMessageCmd(ENABLE);
00817
00818   CEC_SendDataByte((MyLogicalAddress << 4) | 0x4);
00819
00820   /* Start of message */
00821   CEC_StartOfMessage();
00822
00823   /* Wait till the header message is sent */
00824   while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
00825   {
00826     count++;
00827   }
00828
00829   if (count >= HDMI_CEC_TIMEOUT_VALUE)
00830   {
00831     errorstatus = HDMI_CEC_TIMEOUT;
00832     return(errorstatus);
00833   }
00834
00835   errorstatus = HDMI_CEC_GetErrorStatus();
00836
00837   if (errorstatus == HDMI_CEC_OK)
00838   {
00839     HDMI_CEC_Follower_String[4][1] = (uint8_t *)"1";
00840     i++;
00841     errorstatus = HDMI_CEC_OK;
00842   }
00843   /* Clear CEC CSR register */
00844   CEC_ClearFlag(CEC_FLAG_TBTRF);
00845   CEC_EndOfMessageCmd(DISABLE);
00846
00847   /*----------------------------- Audio system ---------------------------*/
00848   CEC_OwnAddressConfig(MyLogicalAddress); /* Own address = MyLogicalAddress */
00849
00850   CEC_EndOfMessageCmd(ENABLE);
00851
00852   CEC_SendDataByte((MyLogicalAddress << 4) | 0x5);
00853
00854   /* Start of message */
00855   CEC_StartOfMessage();
00856
00857   /* Wait till the header message is sent */
00858   while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
00859   {
00860     count++;
00861   }
00862
00863   if (count >= HDMI_CEC_TIMEOUT_VALUE)
00864   {
00865     errorstatus = HDMI_CEC_TIMEOUT;
00866     return(errorstatus);
00867   }
00868
00869   errorstatus = HDMI_CEC_GetErrorStatus();
00870
00871   if (errorstatus == HDMI_CEC_OK)
00872   {
00873     HDMI_CEC_Follower_String[5][1] = (uint8_t *)"1";
00874     i++;
00875     errorstatus = HDMI_CEC_OK;
00876   }
00877   /* Clear CEC CSR register */
00878   CEC_ClearFlag(CEC_FLAG_TBTRF);
00879   CEC_EndOfMessageCmd(DISABLE);
00880
00881   /*----------------------------- Tuner 2 ---------------------------*/
00882   CEC_OwnAddressConfig(MyLogicalAddress); /* Own address = MyLogicalAddress */
00883
00884   CEC_EndOfMessageCmd(ENABLE);
00885
00886   CEC_SendDataByte((MyLogicalAddress << 4) | 0x6);
00887
00888   /* Start of message */
00889   CEC_StartOfMessage();
00890
00891   /* Wait till the header message is sent */
00892   while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
00893   {
00894     count++;
00895   }
00896
00897   if (count >= HDMI_CEC_TIMEOUT_VALUE)
00898   {
00899     errorstatus = HDMI_CEC_TIMEOUT;
00900     return(errorstatus);
00901   }
00902
00903   errorstatus = HDMI_CEC_GetErrorStatus();
00904
00905   if (errorstatus == HDMI_CEC_OK)
00906   {
00907     HDMI_CEC_Follower_String[6][1] = (uint8_t *)"1";
00908     i++;
00909     errorstatus = HDMI_CEC_OK;
00910   }
00911   /* Clear CEC CSR register */
00912   CEC_ClearFlag(CEC_FLAG_TBTRF);
00913   CEC_EndOfMessageCmd(DISABLE);
00914
00915   /*----------------------------- Tuner 3 ---------------------------*/
00916   CEC_OwnAddressConfig(MyLogicalAddress); /* Own address = MyLogicalAddress */
00917
00918   CEC_EndOfMessageCmd(ENABLE);
00919
00920   CEC_SendDataByte((MyLogicalAddress << 4) | 0x7);
00921
00922   /* Start of message */
00923   CEC_StartOfMessage();
00924
00925   /* Wait till the header message is sent */
00926   while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
00927   {
00928     count++;
00929   }
00930
00931   if (count >= HDMI_CEC_TIMEOUT_VALUE)
00932   {
00933     errorstatus = HDMI_CEC_TIMEOUT;
00934     return(errorstatus);
00935   }
00936
00937   errorstatus = HDMI_CEC_GetErrorStatus();
00938
00939   if (errorstatus == HDMI_CEC_OK)
00940   {
00941     HDMI_CEC_Follower_String[7][1] = (uint8_t *)"1";
00942     i++;
00943     errorstatus = HDMI_CEC_OK;
00944   }
00945   /* Clear CEC CSR register */
00946   CEC_ClearFlag(CEC_FLAG_TBTRF);
00947   CEC_EndOfMessageCmd(DISABLE);
00948
00949   /*----------------------------- Playback device 2 ---------------------------*/
00950   CEC_OwnAddressConfig(MyLogicalAddress); /* Own address = MyLogicalAddress */
00951
00952   CEC_EndOfMessageCmd(ENABLE);
00953
00954   CEC_SendDataByte((MyLogicalAddress << 4) | 0x8);
00955
00956   /* Start of message */
00957   CEC_StartOfMessage();
00958
00959   /* Wait till the header message is sent */
00960   while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
00961   {
00962     count++;
00963   }
00964
00965   if (count >= HDMI_CEC_TIMEOUT_VALUE)
00966   {
00967     errorstatus = HDMI_CEC_TIMEOUT;
00968     return(errorstatus);
00969   }
00970
00971   errorstatus = HDMI_CEC_GetErrorStatus();
00972
00973   if (errorstatus == HDMI_CEC_OK)
00974   {
00975     HDMI_CEC_Follower_String[8][1] = (uint8_t *)"1";
00976     i++;
00977     errorstatus = HDMI_CEC_OK;
00978   }
00979   /* Clear CEC CSR register */
00980   CEC_ClearFlag(CEC_FLAG_TBTRF);
00981   CEC_EndOfMessageCmd(DISABLE);
00982
00983   /*----------------------------- Recording device 3 ---------------------------*/
00984   CEC_OwnAddressConfig(MyLogicalAddress); /* Own address = MyLogicalAddress */
00985
00986   CEC_EndOfMessageCmd(ENABLE);
00987
00988   CEC_SendDataByte((MyLogicalAddress << 4) | 0x9);
00989
00990   /* Start of message */
00991   CEC_StartOfMessage();
00992
00993   /* Wait till the header message is sent */
00994   while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
00995   {
00996     count++;
00997   }
00998
00999   if (count >= HDMI_CEC_TIMEOUT_VALUE)
01000   {
01001     errorstatus = HDMI_CEC_TIMEOUT;
01002     return(errorstatus);
01003   }
01004
01005   errorstatus = HDMI_CEC_GetErrorStatus();
01006
01007   if (errorstatus == HDMI_CEC_OK)
01008   {
01009     HDMI_CEC_Follower_String[9][1] = (uint8_t *)"1";
01010     i++;
01011     errorstatus = HDMI_CEC_OK;
01012   }
01013   /* Clear CEC CSR register */
01014   CEC_ClearFlag(CEC_FLAG_TBTRF);
01015   CEC_EndOfMessageCmd(DISABLE);
01016   /*----------------------------- Tuner 4 ---------------------------*/
01017   CEC_OwnAddressConfig(MyLogicalAddress); /* Own address = MyLogicalAddress */
01018
01019   CEC_EndOfMessageCmd(ENABLE);
01020
01021   CEC_SendDataByte((MyLogicalAddress << 4) | 0xA);
01022
01023   /* Start of message */
01024   CEC_StartOfMessage();
01025
01026   /* Wait till the header message is sent */
01027   while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
01028   {
01029     count++;
01030   }
01031
01032   if (count >= HDMI_CEC_TIMEOUT_VALUE)
01033   {
01034     errorstatus = HDMI_CEC_TIMEOUT;
01035     return(errorstatus);
01036   }
01037
01038   errorstatus = HDMI_CEC_GetErrorStatus();
01039
01040   if (errorstatus == HDMI_CEC_OK)
01041   {
01042     HDMI_CEC_Follower_String[10][1] = (uint8_t *)"1";
01043     i++;
01044     errorstatus = HDMI_CEC_OK;
01045   }
01046   /* Clear CEC CSR register */
01047   CEC_ClearFlag(CEC_FLAG_TBTRF);
01048   CEC_EndOfMessageCmd(DISABLE);
01049   /*----------------------------- Playback device 3 ---------------------------*/
01050   CEC_OwnAddressConfig(MyLogicalAddress); /* Own address = MyLogicalAddress */
01051
01052   CEC_EndOfMessageCmd(ENABLE);
01053
01054   CEC_SendDataByte((MyLogicalAddress << 4) | 0xB);
01055
01056   /* Start of message */
01057   CEC_StartOfMessage();
01058
01059   /* Wait till the header message is sent */
01060   while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
01061   {
01062     count++;
01063   }
01064
01065   if (count >= HDMI_CEC_TIMEOUT_VALUE)
01066   {
01067     errorstatus = HDMI_CEC_TIMEOUT;
01068     return(errorstatus);
01069   }
01070
01071   errorstatus = HDMI_CEC_GetErrorStatus();
01072
01073   if (errorstatus == HDMI_CEC_OK)
01074   {
01075     HDMI_CEC_Follower_String[11][1] = (uint8_t *)"1";
01076     i++;
01077     errorstatus = HDMI_CEC_OK;
01078   }
01079   /* Clear CEC CSR register */
01080   CEC_ClearFlag(CEC_FLAG_TBTRF);
01081   CEC_EndOfMessageCmd(DISABLE);
01082
01083   CECDevicesNumber = i - 1;
01084
01085   return errorstatus;
01086 }
01087
01088 /**
01089   * @brief  Physical address discovery.
01090   * @param  None
01091   * @retval HDMI_CEC_Error: CEC Error code.
01092   */
01093 static HDMI_CEC_Error PhysicalAddressDiscovery(void)
01094 {
01095   HDMI_CEC_Error errorstatus = HDMI_CEC_OK;
01096 #ifdef HDMI_CEC_USE_DDC
01097   uint32_t index = 0, i = 0;
01098 #endif
01099
01100   /*------------------------------ Physical address discovery -----------------*/
01101   if (HDMI_CEC_ROOT == 0x1)
01102   {
01103     MyPhysicalAddress = 0x0000;
01104     /* The HDMI-CEC here is configured as sink or as a repeater. The configuration
01105        of the +5V power signal and the HPD should be well configured.
01106        Implement here the EDID Structure to be sent to the HDMI source.
01107        For more details please refer to the HDMI specification.
01108        The EDID structure should be sent to the device source using the DDC Channel
01109        and using the HPD signal. */
01110   }
01111   else
01112   {
01113
01114 #ifdef HDMI_CEC_USE_DDC
01115     /* The HDMI-CEC here is configured as source or as a repeater. The configuration
01116        of the +5V power signal and the HPD should be well configured.
01117        The source should wait for HPD and then read the EDID structure. */
01118     while(GPIO_ReadInputDataBit(HDMI_CEC_HPD_GPIO_PORT, HDMI_CEC_HPD_PIN) == RESET)
01119     {
01120     }
01121     /* Wait for 100 ms after HPD was received */
01122     for(i = 0; i < 0x5FFFF; i++)
01123     {
01124     }
01125
01126     /* Return the physical address using the I2C  by reading the 2 bytes 24 and
01127       25 form the EDID */
01128     /* Read the EDID Block 0 and EDID Block 1 at address 0xA0 */
01129     /*!< While the bus is busy */
01130     while(I2C_GetFlagStatus(HDMI_CEC_I2C, I2C_FLAG_BUSY))
01131     {
01132     }
01133
01134     /*!< Send START condition */
01135     I2C_GenerateSTART(HDMI_CEC_I2C, ENABLE);
01136
01137     /*!< Test on EV5 and clear it */
01138     while(!I2C_CheckEvent(HDMI_CEC_I2C, I2C_EVENT_MASTER_MODE_SELECT))
01139     {
01140     }
01141
01142     /*!< Send EEPROM address for write */
01143     I2C_Send7bitAddress(HDMI_CEC_I2C, 0xA0, I2C_Direction_Transmitter);
01144
01145
01146     /*!< Test on EV6 and clear it */
01147     while(!I2C_CheckEvent(HDMI_CEC_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED))
01148     {
01149     }
01150
01151     /*!< Send the EEPROM's internal address to read from: Only one byte address */
01152     I2C_SendData(HDMI_CEC_I2C, 0x00);
01153
01154     /*!< Test on EV8 and clear it */
01155     while(!I2C_CheckEvent(HDMI_CEC_I2C, I2C_EVENT_MASTER_BYTE_TRANSMITTED))
01156     {
01157     }
01158
01159     /*!< Send STRAT condition a second time */
01160     I2C_GenerateSTART(HDMI_CEC_I2C, ENABLE);
01161
01162     /*!< Test on EV5 and clear it */
01163     while(!I2C_CheckEvent(HDMI_CEC_I2C, I2C_EVENT_MASTER_MODE_SELECT))
01164     {
01165     }
01166
01167     /*!< Send EEPROM address for read */
01168     I2C_Send7bitAddress(HDMI_CEC_I2C, 0xA1, I2C_Direction_Receiver);
01169
01170     /*!< Test on EV6 and clear it */
01171     while(!I2C_CheckEvent(HDMI_CEC_I2C, I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED))
01172     {
01173     }
01174
01175     /* While there is data to be read */
01176     while (NumByteToRead-- > 1)
01177     {
01178       while(I2C_CheckEvent(HDMI_CEC_I2C, I2C_EVENT_MASTER_BYTE_RECEIVED))
01179       {
01180       }
01181       for(i = 0; i < 0xFFF; i++)
01182       {
01183       }
01184       pBuffer[index++] = I2C_ReceiveData(HDMI_CEC_I2C);
01185     }
01186
01187     /* Disable Acknowledgement */
01188     I2C_AcknowledgeConfig(HDMI_CEC_I2C, DISABLE);
01189
01190     /* Send STOP Condition */
01191     I2C_GenerateSTOP(HDMI_CEC_I2C, ENABLE);
01192
01193     while(I2C_CheckEvent(HDMI_CEC_I2C, I2C_EVENT_MASTER_BYTE_RECEIVED));
01194     pBuffer[index] = I2C_ReceiveData(HDMI_CEC_I2C);
01195
01196     /* Enable Acknowledgement to be ready for another reception */
01197     I2C_AcknowledgeConfig(HDMI_CEC_I2C, ENABLE);
01198     MyPhysicalAddress = ((pBuffer[138] << 8) | pBuffer[137]);
01199 #else
01200     MyPhysicalAddress = 0x1000;
01201 #endif
01202   }
01203
01204   return errorstatus;
01205 }
01206 /**
01207   * @brief  Allocate the logical address.
01208   * @param  None
01209   * @retval HDMI_CEC_Error: CEC Error code.
01210   */
01211 static HDMI_CEC_Error LogicalAddressAllocation(void)
01212 {
01213   HDMI_CEC_Error errorstatus = HDMI_CEC_OK;
01214   uint32_t count = 0;
01215
01216   /*------------------ Logical address allocation -----------------------------*/
01217   /* Get the device type */
01218   /* Device type = CEC_TV */
01219   if (DeviceType == HDMI_CEC_TV)
01220   {
01221     if (HDMI_CEC_ROOT)
01222     {
01223       MyLogicalAddress = 0x00;
01224     }
01225     else
01226     {
01227       CEC_OwnAddressConfig(0xE); /* Own address = 0xE */
01228
01229       CEC_EndOfMessageCmd(ENABLE);
01230
01231       CEC_SendDataByte(0xEE);
01232
01233       /* Start of message */
01234       CEC_StartOfMessage();
01235
01236       /* Wait till the polling message is sent */
01237       while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
01238       {
01239         count++;
01240       }
01241
01242       if (count >= HDMI_CEC_TIMEOUT_VALUE)
01243       {
01244         errorstatus = HDMI_CEC_TIMEOUT;
01245         return(errorstatus);
01246       }
01247
01248       errorstatus = HDMI_CEC_GetErrorStatus();
01249
01250       if (errorstatus == HDMI_CEC_BLOCK_ACKNOWLEDGE)
01251       {
01252         MyLogicalAddress = 0x0E;
01253         errorstatus = HDMI_CEC_OK;
01254       }
01255       else if (errorstatus == HDMI_CEC_OK)
01256       {
01257         MyLogicalAddress = 0x0F;
01258         errorstatus = HDMI_CEC_DEVICE_UNREGISTRED;
01259       }
01260     }
01261     /* Clear CEC CSR register */
01262     CEC_ClearFlag(CEC_FLAG_TBTRF);
01263     CEC_EndOfMessageCmd(DISABLE);
01264   }
01265
01266   /* Device type = CEC_RECORDING */
01267   if (DeviceType == HDMI_CEC_RECORDING)
01268   {
01269     CEC_OwnAddressConfig(0x1); /* Own address = 0x1 */
01270
01271     CEC_EndOfMessageCmd(ENABLE);
01272
01273     CEC_SendDataByte(0x11);
01274
01275     /* Start of message */
01276     CEC_StartOfMessage();
01277
01278     /* Wait till the header message is sent */
01279     while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
01280     {
01281       count++;
01282     }
01283
01284     if (count >= HDMI_CEC_TIMEOUT_VALUE)
01285     {
01286       errorstatus = HDMI_CEC_TIMEOUT;
01287       return(errorstatus);
01288     }
01289
01290     errorstatus = HDMI_CEC_GetErrorStatus();
01291
01292     if (errorstatus == HDMI_CEC_BLOCK_ACKNOWLEDGE)
01293     {
01294       MyLogicalAddress = 0x01;
01295       errorstatus = HDMI_CEC_OK;
01296     }
01297     else if (errorstatus == HDMI_CEC_OK)
01298     {
01299       /* Clear CEC CSR register */
01300       CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR);
01301
01302       CEC_EndOfMessageCmd(DISABLE);
01303
01304       CEC_OwnAddressConfig(0x2); /* Own address = 0x2 */
01305
01306       CEC_EndOfMessageCmd(ENABLE);
01307
01308       CEC_SendDataByte(0x22);
01309
01310       /* Start of message */
01311       CEC_StartOfMessage();
01312
01313       count = 0;
01314
01315       /* Wait till the header message is sent */
01316       while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
01317       {
01318         count++;
01319       }
01320
01321       if (count >= HDMI_CEC_TIMEOUT_VALUE)
01322       {
01323         errorstatus = HDMI_CEC_TIMEOUT;
01324         return(errorstatus);
01325       }
01326       errorstatus = HDMI_CEC_GetErrorStatus();
01327
01328       if (errorstatus == HDMI_CEC_BLOCK_ACKNOWLEDGE)
01329       {
01330         MyLogicalAddress = 0x02;
01331         errorstatus = HDMI_CEC_OK;
01332       }
01333       else if (errorstatus == HDMI_CEC_OK)
01334       {
01335         /* Clear CEC CSR register */
01336         CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR);
01337
01338         CEC_EndOfMessageCmd(DISABLE);
01339
01340         CEC_OwnAddressConfig(0x9); /* Own address = 0x9 */
01341
01342         CEC_EndOfMessageCmd(ENABLE);
01343
01344         CEC_SendDataByte(0x99);
01345
01346         /* Start of message */
01347         CEC_StartOfMessage();
01348
01349         count = 0;
01350
01351         /* Wait till the header message is sent */
01352         while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
01353         {
01354           count++;
01355         }
01356
01357         if (count >= HDMI_CEC_TIMEOUT_VALUE)
01358         {
01359           errorstatus = HDMI_CEC_TIMEOUT;
01360           return(errorstatus);
01361         }
01362         errorstatus = HDMI_CEC_GetErrorStatus();
01363
01364         if (errorstatus == HDMI_CEC_BLOCK_ACKNOWLEDGE)
01365         {
01366           MyLogicalAddress = 0x09;
01367           errorstatus = HDMI_CEC_OK;
01368         }
01369         else if (errorstatus == HDMI_CEC_OK)
01370         {
01371           MyLogicalAddress = 0x0F;
01372           errorstatus = HDMI_CEC_DEVICE_UNREGISTRED;
01373         }
01374       }
01375     }
01376     /* Clear CEC CSR register */
01377     CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR);
01378     CEC_EndOfMessageCmd(DISABLE);
01379   }
01380
01381   /* Device type = CEC_TUNER */
01382   if (DeviceType == HDMI_CEC_TUNER)
01383   {
01384     CEC_OwnAddressConfig(0x3); /* Own address = 0x3 */
01385
01386     CEC_EndOfMessageCmd(ENABLE);
01387
01388     CEC_SendDataByte(0x33);
01389
01390     /* Start of message */
01391     CEC_StartOfMessage();
01392
01393     count = 0;
01394
01395     /* Wait till the header message is sent */
01396     while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
01397     {
01398       count++;
01399     }
01400
01401     if (count >= HDMI_CEC_TIMEOUT_VALUE)
01402     {
01403       errorstatus = HDMI_CEC_TIMEOUT;
01404       return(errorstatus);
01405     }
01406     errorstatus = HDMI_CEC_GetErrorStatus();
01407
01408     if (errorstatus == HDMI_CEC_BLOCK_ACKNOWLEDGE)
01409     {
01410       MyLogicalAddress = 0x03;
01411       errorstatus = HDMI_CEC_OK;
01412     }
01413     else if (errorstatus == HDMI_CEC_OK)
01414     {
01415       /* Clear CEC CSR register */
01416       CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR);
01417
01418       CEC_EndOfMessageCmd(DISABLE);
01419
01420       CEC_OwnAddressConfig(0x6); /* Own address = 0x6 */
01421
01422       CEC_EndOfMessageCmd(ENABLE);
01423
01424       CEC_SendDataByte(0x66);
01425
01426       /* Start of message */
01427       CEC_StartOfMessage();
01428
01429       count = 0;
01430
01431       /* Wait till the header message is sent */
01432       while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
01433       {
01434         count++;
01435       }
01436
01437       if (count >= HDMI_CEC_TIMEOUT_VALUE)
01438       {
01439         errorstatus = HDMI_CEC_TIMEOUT;
01440         return(errorstatus);
01441       }
01442       errorstatus = HDMI_CEC_GetErrorStatus();
01443
01444       if (errorstatus == HDMI_CEC_BLOCK_ACKNOWLEDGE)
01445       {
01446         MyLogicalAddress = 0x06;
01447         errorstatus = HDMI_CEC_OK;
01448       }
01449       else if (errorstatus == HDMI_CEC_OK)
01450       {
01451         /* Clear CEC CSR register */
01452         CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR);
01453
01454         CEC_EndOfMessageCmd(DISABLE);
01455
01456         CEC_OwnAddressConfig(0x7); /* Own address = 0x7 */
01457
01458         CEC_EndOfMessageCmd(ENABLE);
01459
01460         CEC_SendDataByte(0x77);
01461
01462         /* Start of message */
01463         CEC_StartOfMessage();
01464
01465         count = 0;
01466
01467         /* Wait till the header message is sent */
01468         while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
01469         {
01470           count++;
01471         }
01472
01473         if (count >= HDMI_CEC_TIMEOUT_VALUE)
01474         {
01475           errorstatus = HDMI_CEC_TIMEOUT;
01476           return(errorstatus);
01477         }
01478         errorstatus = HDMI_CEC_GetErrorStatus();
01479
01480         if (errorstatus == HDMI_CEC_BLOCK_ACKNOWLEDGE)
01481         {
01482           MyLogicalAddress = 0x07;
01483           errorstatus = HDMI_CEC_OK;
01484         }
01485         else if (errorstatus == HDMI_CEC_OK)
01486         {
01487           /* Clear CEC CSR register */
01488           CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR);
01489
01490           CEC_EndOfMessageCmd(DISABLE);
01491
01492           CEC_OwnAddressConfig(0xA); /* Own address = 0xA */
01493
01494           CEC_EndOfMessageCmd(ENABLE);
01495
01496           CEC_SendDataByte(0xAA);
01497
01498           /* Start of message */
01499           CEC_StartOfMessage();
01500
01501           count = 0;
01502
01503           /* Wait till the header message is sent */
01504           while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
01505           {
01506             count++;
01507           }
01508
01509           if (count >= HDMI_CEC_TIMEOUT_VALUE)
01510           {
01511             errorstatus = HDMI_CEC_TIMEOUT;
01512             return(errorstatus);
01513           }
01514           errorstatus = HDMI_CEC_GetErrorStatus();
01515
01516           if (errorstatus == HDMI_CEC_BLOCK_ACKNOWLEDGE)
01517           {
01518             MyLogicalAddress = 0x0A;
01519             errorstatus = HDMI_CEC_OK;
01520           }
01521           else if (errorstatus == HDMI_CEC_OK)
01522           {
01523             MyLogicalAddress = 0x0F;
01524             errorstatus = HDMI_CEC_DEVICE_UNREGISTRED;
01525           }
01526         }
01527       }
01528     }
01529     /* Clear CEC CSR register */
01530     CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR);
01531     CEC_EndOfMessageCmd(DISABLE);
01532   }
01533
01534   /* Device type = CEC_PLAYBACK */
01535   if (DeviceType == HDMI_CEC_PLAYBACK)
01536   {
01537     CEC_OwnAddressConfig(0x4); /* Own address = 0x4 */
01538
01539     CEC_EndOfMessageCmd(ENABLE);
01540
01541     CEC_SendDataByte(0x44);
01542
01543     /* Start of message */
01544     CEC_StartOfMessage();
01545
01546     count = 0;
01547
01548     /* Wait till the header message is sent */
01549     while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
01550     {
01551       count++;
01552     }
01553
01554     if (count >= HDMI_CEC_TIMEOUT_VALUE)
01555     {
01556       errorstatus = HDMI_CEC_TIMEOUT;
01557       return(errorstatus);
01558     }
01559
01560     errorstatus = HDMI_CEC_GetErrorStatus();
01561
01562     if (errorstatus == HDMI_CEC_BLOCK_ACKNOWLEDGE)
01563     {
01564       MyLogicalAddress = 0x04;
01565       errorstatus = HDMI_CEC_OK;
01566     }
01567     else if (errorstatus == HDMI_CEC_OK)
01568     {
01569       /* Clear CEC CSR register */
01570       CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR);
01571
01572       CEC_EndOfMessageCmd(DISABLE);
01573
01574       CEC_OwnAddressConfig(0x8); /* Own address = 0x8 */
01575
01576       CEC_EndOfMessageCmd(ENABLE);
01577
01578       CEC_SendDataByte(0x88);
01579
01580       /* Start of message */
01581       CEC_StartOfMessage();
01582
01583       count = 0;
01584
01585       /* Wait till the header message is sent */
01586       while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
01587       {
01588         count++;
01589       }
01590
01591       if (count >= HDMI_CEC_TIMEOUT_VALUE)
01592       {
01593         errorstatus = HDMI_CEC_TIMEOUT;
01594         return(errorstatus);
01595       }
01596       errorstatus = HDMI_CEC_GetErrorStatus();
01597
01598       if (errorstatus == HDMI_CEC_BLOCK_ACKNOWLEDGE)
01599       {
01600         MyLogicalAddress = 0x08;
01601         errorstatus = HDMI_CEC_OK;
01602       }
01603       else if (errorstatus == HDMI_CEC_OK)
01604       {
01605         /* Clear CEC CSR register */
01606         CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR);
01607
01608         CEC_EndOfMessageCmd(DISABLE);
01609
01610         CEC_OwnAddressConfig(0xB); /* Own address = 0xBB */
01611
01612         CEC_EndOfMessageCmd(ENABLE);
01613
01614         CEC_SendDataByte(0xBB);
01615
01616         /* Start of message */
01617         CEC_StartOfMessage();
01618
01619         count = 0;
01620
01621         /* Wait till the header message is sent */
01622         while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
01623         {
01624           count++;
01625         }
01626
01627         if (count >= HDMI_CEC_TIMEOUT_VALUE)
01628         {
01629           errorstatus = HDMI_CEC_TIMEOUT;
01630           return(errorstatus);
01631         }
01632
01633         errorstatus = HDMI_CEC_GetErrorStatus();
01634
01635         if (errorstatus == HDMI_CEC_BLOCK_ACKNOWLEDGE)
01636         {
01637           MyLogicalAddress = 0x0B;
01638           errorstatus = HDMI_CEC_OK;
01639         }
01640         else if (errorstatus == HDMI_CEC_OK)
01641         {
01642           MyLogicalAddress = 0x0F;
01643           errorstatus = HDMI_CEC_DEVICE_UNREGISTRED;
01644         }
01645       }
01646     }
01647
01648     /* Clear CEC CSR register */
01649     CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR);
01650     CEC_EndOfMessageCmd(DISABLE);
01651   }
01652
01653   /* Device type = CEC Audio System */
01654   if (DeviceType == HDMI_CEC_AUDIOSYSTEM)
01655   {
01656     CEC_OwnAddressConfig(0x5); /* Own address = 0x5 */
01657
01658     CEC_EndOfMessageCmd(ENABLE);
01659
01660     CEC_SendDataByte(0x55);
01661
01662     /* Start of message */
01663     CEC_StartOfMessage();
01664
01665     count = 0;
01666
01667     /* Wait till the header message is sent */
01668     while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
01669     {
01670       count++;
01671     }
01672
01673     if (count >= HDMI_CEC_TIMEOUT_VALUE)
01674     {
01675       errorstatus = HDMI_CEC_TIMEOUT;
01676       return(errorstatus);
01677     }
01678
01679     errorstatus = HDMI_CEC_GetErrorStatus();
01680
01681     if (errorstatus == HDMI_CEC_BLOCK_ACKNOWLEDGE)
01682     {
01683       MyLogicalAddress = 0x05;
01684       errorstatus = HDMI_CEC_OK;
01685     }
01686     else if (errorstatus == HDMI_CEC_OK)
01687     {
01688       MyLogicalAddress = 0x0F;
01689       errorstatus = HDMI_CEC_DEVICE_UNREGISTRED;
01690     }
01691
01692     /* Clear CEC CSR register */
01693     CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR);
01694     CEC_EndOfMessageCmd(DISABLE);
01695   }
01696
01697   return errorstatus;
01698 }
01699
01700 /**
01701   * @}
01702   */
01703
01704 /**
01705   * @}
01706   */
01707
01708 /**
01709   * @}
01710   */
01711
01712 /**
01713   * @}
01714   */
01715
01716 /**
01717   * @}
01718   */
01719
01720 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
01721
01722


STM32F10x Standard Peripherals Firmware Library: stm32100b_eval_cec.h Source File

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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • STM32100B_EVAL

stm32100b_eval_cec.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32100b_eval_cec.h
00004   * @author  MCD Application Team
00005   * @version V4.5.0
00006   * @date    07-March-2011
00007   * @brief   This file contains all the functions prototypes for the stm32100b_eval_cec
00008   *          firmware driver.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00013   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00014   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00015   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00016   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00017   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00018   *
00019   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00020   ******************************************************************************
00021   */
00022
00023 /* Define to prevent recursive inclusion -------------------------------------*/
00024 #ifndef __STM32100B_EVAL_CEC_H
00025 #define __STM32100B_EVAL_CEC_H
00026
00027 #ifdef __cplusplus
00028 extern "C"
00029 {
00030 #endif
00031
00032   /* Includes ------------------------------------------------------------------*/
00033 #include "stm32f10x.h"
00034
00035 /** @addtogroup Utilities
00036   * @{
00037   */
00038
00039 /** @addtogroup STM32_EVAL
00040   * @{
00041   */
00042
00043 /** @addtogroup STM32100B_EVAL
00044   * @{
00045   */
00046
00047 /** @defgroup STM32100B_EVAL_CEC
00048   * @{
00049   */
00050
00051 /** @defgroup STM32100B_EVAL_CEC_Exported_Types
00052   * @{
00053   */
00054 typedef enum
00055 {
00056   HDMI_CEC_BIT_TIMING              = (1), /*!< CEC Bit Timing Error */
00057   HDMI_CEC_BIT_PERIOD              = (2), /*!< CEC Bit Period Error */
00058   HDMI_CEC_RX_BLOCK_FINISHED       = (3), /*!< CEC Receive Block finished Error */
00059   HDMI_CEC_START_BIT               = (4), /*!< CEC Start Bit Error */
00060   HDMI_CEC_BLOCK_ACKNOWLEDGE       = (5), /*!< CEC Block Acknowledge Error */
00061   HDMI_CEC_LINE                    = (6), /*!< CEC Line Error */
00062   HDMI_CEC_TX_BLOCK_FINISHED       = (7), /*!< CEC Transmit Block Transfer finished Error */
00063   HDMI_CEC_DEVICE_UNREGISTRED      = (8), /*!< CEC Device Unregistred */
00064   HDMI_CEC_TIMEOUT                 = (9), /*!< CEC TimeOut */
00065   HDMI_CEC_OK                      = (10)  /*!< CEC OK */
00066 }HDMI_CEC_Error;
00067
00068 typedef struct
00069 {
00070   __IO uint8_t PhysicalAddress_A;
00071   __IO uint8_t PhysicalAddress_B;
00072   __IO uint8_t PhysicalAddress_C;
00073   __IO uint8_t PhysicalAddress_D;
00074   __IO uint8_t LogicalAddress;
00075   __IO uint8_t DeviceType;
00076 }HDMI_CEC_Map;
00077
00078
00079 #define HDMI_CEC_TX_MESSAGE_LENGTH_MAX       ((uint32_t)0x0000000E)
00080 #define HDMI_CEC_TIMEOUT_VALUE               ((uint32_t)0x001FFFFF)
00081
00082 /**
00083 * @brief  CEC Init Structure definition
00084 */
00085 typedef struct
00086 {
00087   __IO uint8_t Header;
00088   __IO uint8_t Opcode;
00089   __IO uint8_t Operande[HDMI_CEC_TX_MESSAGE_LENGTH_MAX];
00090   __IO uint8_t TxMessageLength;
00091   __IO uint8_t RxMessageLength;
00092 }HDMI_CEC_Message;
00093
00094 /**
00095 * @}
00096 */
00097
00098 /** @defgroup STM32100B_EVAL_CEC_Exported_Constants
00099   * @{
00100   */
00101
00102 /**
00103   * @brief CEC device types
00104   */
00105 #define HDMI_CEC_TV                                         0x00
00106 #define HDMI_CEC_RECORDING                                  0x01
00107 #define HDMI_CEC_TUNER                                      0x03
00108 #define HDMI_CEC_PLAYBACK                                   0x04
00109 #define HDMI_CEC_AUDIOSYSTEM                                0x05
00110
00111
00112 /**
00113   * @brief  HDMI CEC I2C Interface pins
00114   */
00115 #define HDMI_CEC_I2C_SCL_PIN                                GPIO_Pin_10
00116 #define HDMI_CEC_I2C_SDA_PIN                                GPIO_Pin_11
00117 #define HDMI_CEC_I2C_GPIO_PORT                              GPIOB
00118 #define HDMI_CEC_I2C_GPIO_CLK                               RCC_APB2Periph_GPIOB
00119 #define HDMI_CEC_I2C                                        I2C2
00120 #define HDMI_CEC_I2C_CLK                                    RCC_APB1Periph_I2C2
00121
00122 /**
00123   * @brief  HDMI CEC HPD (Hot Plug Detect) Interface pin
00124   */
00125 #define HDMI_CEC_HPD_PIN                                    GPIO_Pin_12
00126 #define HDMI_CEC_HPD_GPIO_PORT                              GPIOB
00127 #define HDMI_CEC_HPD_GPIO_CLK                               RCC_APB2Periph_GPIOB
00128
00129 /**
00130   * @brief  HDMI CEC Interface pin
00131   */
00132 #define HDMI_CEC_LINE_PIN                                   GPIO_Pin_8
00133 #define HDMI_CEC_LINE_GPIO_PORT                             GPIOB
00134 #define HDMI_CEC_LINE_GPIO_CLK                              RCC_APB2Periph_GPIOB
00135
00136 #define HDMI_CEC_I2C_SLAVE_ADDRESS7                         0xA0
00137 #define HDMI_CEC_I2C_CLOCK_SPEED                            100000
00138
00139 /**
00140   * @brief  HDMI CEC Root (Mainly for TV with a fixed physical address (0.0.0.0))
00141   *         If you want to configure the STM32100B-EVAL board as CEC Root (Sink)
00142   *         change the following define to 0x1
00143   */
00144 #define HDMI_CEC_ROOT                                       0x00
00145
00146 /**
00147   * @brief  To select if the DDC Channel will be used for physical address discovery
00148   *         or not. To use the DDC Channel to read the EDID structure uncomment
00149   *         the following line.
00150   *         If the device is configured as HMDI source it should read his own physical
00151   *         address from the sink that is connected to.
00152   */
00153 /* #define HDMI_CEC_USE_DDC */
00154
00155 /**
00156   * @brief  CEC version: V1.3a
00157   */
00158 #define HDMI_CEC_VERSION                                    0x04
00159
00160 /**
00161   * @brief  Reason for Abort feature
00162   */
00163 #define HDMI_CEC_UNRECOGNIZED_OPCODE                        0x00
00164 #define HDMI_CEC_NOT_CORRECT_MODETORESPOND                  0x01
00165 #define HDMI_CEC_CANNOTPROVIDE_SOURCE                       0x02
00166 #define HDMI_CEC_INVALID_OPERAND                            0x03
00167 #define HDMI_CEC_REFUSED                                    0x04
00168
00169 /**
00170   * @brief  HDMI CEC specific commands
00171   */
00172 #define HDMI_CEC_OPCODE_ACTIVE_SOURCE                       ((uint8_t) 0x82)
00173 #define HDMI_CEC_OPCODE_IMAGE_VIEW_ON                       ((uint8_t) 0x04)
00174 #define HDMI_CEC_OPCODE_TEXT_VIEW_ON                        ((uint8_t) 0x0D)
00175 #define HDMI_CEC_OPCODE_INACTIVE_SOURCE                     ((uint8_t) 0x9D)
00176 #define HDMI_CEC_OPCODE_REQUEST_ACTIVE_SOURCE               ((uint8_t) 0x85)
00177 #define HDMI_CEC_OPCODE_ROUTING_CHANGE                      ((uint8_t) 0x80)
00178 #define HDMI_CEC_OPCODE_ROUTING_INFORMATION                 ((uint8_t) 0x81)
00179 #define HDMI_CEC_OPCODE_SET_STREAM_PATH                     ((uint8_t) 0x86)
00180 #define HDMI_CEC_OPCODE_STANDBY                             ((uint8_t) 0x36)
00181 #define HDMI_CEC_OPCODE_RECORD_OFF                          ((uint8_t) 0x0B)
00182 #define HDMI_CEC_OPCODE_RECORD_ON                           ((uint8_t) 0x09)
00183 #define HDMI_CEC_OPCODE_RECORD_STATUS                       ((uint8_t) 0x0A)
00184 #define HDMI_CEC_OPCODE_RECORD_TV_SCREEN                    ((uint8_t) 0x0F)
00185 #define HDMI_CEC_OPCODE_CLEAR_ANALOGUE_TIMER                ((uint8_t) 0x33)
00186 #define HDMI_CEC_OPCODE_CLEAR_DIGITAL_TIMER                 ((uint8_t) 0x99)
00187 #define HDMI_CEC_OPCODE_CLEAR_EXTERNAL_TIMER                ((uint8_t) 0xA1)
00188 #define HDMI_CEC_OPCODE_SET_ANALOGUE_TIMER                  ((uint8_t) 0x34)
00189 #define HDMI_CEC_OPCODE_SET_DIGITAL_TIMER                   ((uint8_t) 0x97)
00190 #define HDMI_CEC_OPCODE_SET_EXTERNAL_TIMER                  ((uint8_t) 0xA2)
00191 #define HDMI_CEC_OPCODE_SET_TIMER_PROGRAM_TITLE             ((uint8_t) 0x67)
00192 #define HDMI_CEC_OPCODE_TIMER_CLEARED_STATUS                ((uint8_t) 0x43)
00193 #define HDMI_CEC_OPCODE_TIMER_STATUS                        ((uint8_t) 0x35)
00194 #define HDMI_CEC_OPCODE_CEC_VERSION                         ((uint8_t) 0x9E)
00195 #define HDMI_CEC_OPCODE_GET_CEC_VERSION                     ((uint8_t) 0x9F)
00196 #define HDMI_CEC_OPCODE_GIVE_PHYSICAL_ADDRESS               ((uint8_t) 0x83)
00197 #define HDMI_CEC_OPCODE_GET_MENU_LANGUAGE                   ((uint8_t) 0x91)
00198 #define HDMI_CEC_OPCODE_REPORT_PHYSICAL_ADDRESS             ((uint8_t) 0x84)
00199 #define HDMI_CEC_OPCODE_SET_MENU_LANGUAGE                   ((uint8_t) 0x32)
00200 #define HDMI_CEC_OPCODE_DECK_CONTROL                        ((uint8_t) 0x42)
00201 #define HDMI_CEC_OPCODE_DECK_STATUS                         ((uint8_t) 0x1B)
00202 #define HDMI_CEC_OPCODE_GIVE_DECK_STATUS                    ((uint8_t) 0x1A)
00203 #define HDMI_CEC_OPCODE_PLAY                                ((uint8_t) 0x41)
00204 #define HDMI_CEC_OPCODE_GIVE_TUNER_DEVICE_STATUS            ((uint8_t) 0x08)
00205 #define HDMI_CEC_OPCODE_SELECT_ANALOGUE_SERVICE             ((uint8_t) 0x92)
00206 #define HDMI_CEC_OPCODE_SELECT_DIGITAL_SERVICE              ((uint8_t) 0x93)
00207 #define HDMI_CEC_OPCODE_TUNER_DEVICE_STATUS                 ((uint8_t) 0x07)
00208 #define HDMI_CEC_OPCODE_TUNER_STEP_DECREMENT                ((uint8_t) 0x06)
00209 #define HDMI_CEC_OPCODE_TUNER_STEP_INCREMENT                ((uint8_t) 0x05)
00210 #define HDMI_CEC_OPCODE_DEVICE_VENDOR_ID                    ((uint8_t) 0x87)
00211 #define HDMI_CEC_OPCODE_GIVE_DEVICE_VENDOR_ID               ((uint8_t) 0x8C)
00212 #define HDMI_CEC_OPCODE_VENDOR_COMMAND                      ((uint8_t) 0x89)
00213 #define HDMI_CEC_OPCODE_VENDOR_COMMAND_WITH_ID              ((uint8_t) 0xA0)
00214 #define HDMI_CEC_OPCODE_VENDOR_REMOTE_BUTTON_DOWN           ((uint8_t) 0x8A)
00215 #define HDMI_CEC_OPCODE_VENDOR_REMOTE_BUTTON_UP             ((uint8_t) 0x8B)
00216 #define HDMI_CEC_OPCODE_SET_OSD_STRING                      ((uint8_t) 0x64)
00217 #define HDMI_CEC_OPCODE_GIVE_OSD_NAME                       ((uint8_t) 0x46)
00218 #define HDMI_CEC_OPCODE_SET_OSD_NAME                        ((uint8_t) 0x47)
00219 #define HDMI_CEC_OPCODE_MENU_REQUEST                        ((uint8_t) 0x8D)
00220 #define HDMI_CEC_OPCODE_MENU_STATUS                         ((uint8_t) 0x8E)
00221 #define HDMI_CEC_OPCODE_USER_CONTROL_PRESSED                ((uint8_t) 0x44)
00222 #define HDMI_CEC_OPCODE_USER_CONTROL_RELEASED               ((uint8_t) 0x45)
00223 #define HDMI_CEC_OPCODE_GIVE_DEVICE_POWER_STATUS            ((uint8_t) 0x8F)
00224 #define HDMI_CEC_OPCODE_REPORT_POWER_STATUS                 ((uint8_t) 0x90)
00225 #define HDMI_CEC_OPCODE_FEATURE_ABORT                       ((uint8_t) 0x00)
00226 #define HDMI_CEC_OPCODE_ABORT                               ((uint8_t) 0xFF)
00227 #define HDMI_CEC_OPCODE_GIVE_AUDIO_STATUS                   ((uint8_t) 0x71)
00228 #define HDMI_CEC_OPCODE_GIVE_SYSTEM_AUDIO_MODE_STATUS       ((uint8_t) 0x7D)
00229 #define HDMI_CEC_OPCODE_REPORT_AUDIO_STATUS                 ((uint8_t) 0x7A)
00230 #define HDMI_CEC_OPCODE_SET_SYSTEM_AUDIO_MODE               ((uint8_t) 0x72)
00231 #define HDMI_CEC_OPCODE_SYSTEM_AUDIO_MODE_REQUEST           ((uint8_t) 0x70)
00232 #define HDMI_CEC_OPCODE_SYSTEM_AUDIO_MODE_STATUS            ((uint8_t) 0x7E)
00233 #define HDMI_CEC_OPCODE_SET_AUDIO_RATE                      ((uint8_t) 0x9A)
00234
00235
00236 /**
00237   * @}
00238   */
00239
00240 /** @defgroup STM32100B_EVAL_CEC_Exported_Macros
00241   * @{
00242   */
00243 /* HDMI_CEC_HPD: HDMI HPD pin low  */
00244 #define HDMI_CEC_HPD_LOW()       GPIO_ResetBits(HDMI_CEC_HPD_GPIO_PORT, HDMI_CEC_HPD_PIN)
00245 /* HDMI_CEC_HPD: HDMI HPD pin high  */
00246 #define HDMI_CEC_HPD_HIGH()      GPIO_SetBits(HDMI_CEC_HPD_GPIO_PORT, HDMI_CEC_HPD_PIN)
00247
00248 /**
00249   * @}
00250   */
00251
00252 /** @defgroup STM32100B_EVAL_CEC_Exported_Functions
00253   * @{
00254   */
00255 HDMI_CEC_Error HDMI_CEC_Init(void);
00256 HDMI_CEC_Error HDMI_CEC_TransmitMessage(HDMI_CEC_Message *HDMI_CEC_TX_MessageStructure);
00257 HDMI_CEC_Error HDMI_CEC_GetErrorStatus (void);
00258 void HDMI_CEC_ProcessIRQSrc(void);
00259 HDMI_CEC_Error HDMI_CEC_ReportPhysicalAddress(void);
00260 void HDMI_CEC_CommandCallBack(void);
00261 HDMI_CEC_Error HDMI_CEC_CheckConnectedDevices(void);
00262
00263 #ifdef __cplusplus
00264 }
00265 #endif
00266
00267 #endif /* __STM32100B_EVAL_CEC_H */
00268
00269 /**
00270   * @}
00271   */
00272
00273 /**
00274   * @}
00275   */
00276
00277 /**
00278   * @}
00279   */
00280
00281 /**
00282   * @}
00283   */
00284
00285 /**
00286   * @}
00287   */
00288
00289 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
00290


STM32F10x Standard Peripherals Firmware Library: stm32100b_eval_lcd.c Source File

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • STM32100B_EVAL

stm32100b_eval_lcd.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32100b_eval_lcd.c
00004   * @author  MCD Application Team
00005   * @version V4.5.0
00006   * @date    07-March-2011
00007   * @brief   This file includes the LCD driver for AM-240320LTNQW00H (LCD_HX8312),
00008   *          AM-240320L8TNQW00H (LCD_ILI9320), AM-240320LDTNQW00H (LCD_SPFD5408B)
00009   *          Liquid Crystal Display Module of STM32100B-EVAL board.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32100b_eval_lcd.h"
00026 #include "../Common/fonts.c"
00027
00028 /** @addtogroup Utilities
00029   * @{
00030   */
00031
00032 /** @addtogroup STM32_EVAL
00033   * @{
00034   */
00035
00036 /** @addtogroup STM32100B_EVAL
00037   * @{
00038   */
00039
00040 /** @defgroup STM32100B_EVAL_LCD
00041   * @brief   This file includes the LCD driver for AM-240320LTNQW00H (LCD_HX8312),
00042   *          AM-240320L8TNQW00H (LCD_ILI9320), AM-240320LDTNQW00H (LCD_SPFD5408B)
00043   *          Liquid Crystal Display Module of STM32100B-EVAL board.
00044   * @{
00045   */
00046
00047 /** @defgroup STM32100B_EVAL_LCD_Private_Types
00048   * @{
00049   */
00050 /**
00051   * @}
00052   */
00053
00054 /** @defgroup STM32100B_EVAL_LCD_Private_Defines
00055   * @{
00056   */
00057 #define LCD_ILI9320        0x9320
00058 #define LCD_HX8312         0x8312
00059 #define LCD_SPFD5408       0x5408
00060 #define START_BYTE         0x70
00061 #define SET_INDEX          0x00
00062 #define READ_STATUS        0x01
00063 #define LCD_WRITE_REG      0x02
00064 #define LCD_READ_REG       0x03
00065 #define MAX_POLY_CORNERS   200
00066 #define POLY_Y(Z)          ((int32_t)((Points + Z)->X))
00067 #define POLY_X(Z)          ((int32_t)((Points + Z)->Y))
00068 /**
00069   * @}
00070   */
00071
00072 /** @defgroup STM32100B_EVAL_LCD_Private_Macros
00073   * @{
00074   */
00075 #define ABS(X)  ((X) > 0 ? (X) : -(X))
00076 /**
00077   * @}
00078   */
00079
00080 /** @defgroup STM32100B_EVAL_LCD_Private_Variables
00081   * @{
00082   */
00083 static sFONT *LCD_Currentfonts;
00084 /* Global variables to set the written text color */
00085 static __IO uint16_t TextColor = 0x0000, BackColor = 0xFFFF;
00086 static __IO uint32_t LCDType = LCD_ILI9320;
00087 /**
00088   * @}
00089   */
00090
00091 /** @defgroup STM32100B_EVAL_LCD_Private_Function_Prototypes
00092   * @{
00093   */
00094 #ifndef USE_Delay
00095 static void delay(vu32 nCount);
00096 #endif /* USE_Delay*/
00097
00098 static void LCD_WriteRegHX8312(uint8_t LCD_Reg, uint8_t LCD_RegValue);
00099 static void LCD_WriteRegILI9320(uint8_t LCD_Reg, uint16_t LCD_RegValue);
00100 static void PutPixel(int16_t x, int16_t y);
00101 static void LCD_PolyLineRelativeClosed(pPoint Points, uint16_t PointCount, uint16_t Closed);
00102
00103 /**
00104   * @}
00105   */
00106
00107 /** @defgroup STM32100B_EVAL_LCD_Private_Functions
00108   * @{
00109   */
00110
00111 /**
00112   * @brief  DeInitializes the LCD.
00113   * @param  None
00114   * @retval None
00115   */
00116 void LCD_DeInit(void)
00117 {
00118   GPIO_InitTypeDef GPIO_InitStructure;
00119
00120   /*!< LCD Display Off */
00121   LCD_DisplayOff();
00122
00123   /*!< LCD_SPI disable */
00124   SPI_Cmd(LCD_SPI, DISABLE);
00125
00126   /*!< LCD_SPI DeInit */
00127   SPI_I2S_DeInit(LCD_SPI);
00128
00129   /*!< Disable SPI clock  */
00130   RCC_APB1PeriphClockCmd(LCD_SPI_CLK, DISABLE);
00131
00132   /* Configure NCS in Output Push-Pull mode */
00133   GPIO_InitStructure.GPIO_Pin = LCD_NCS_PIN;
00134   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
00135   GPIO_Init(LCD_NCS_GPIO_PORT, &GPIO_InitStructure);
00136
00137   /* Configure NWR(RNW), RS in Output Push-Pull mode */
00138   GPIO_InitStructure.GPIO_Pin = LCD_RS_PIN;
00139   GPIO_Init(LCD_RS_GPIO_PORT, &GPIO_InitStructure);
00140
00141   GPIO_InitStructure.GPIO_Pin = LCD_NWR_PIN;
00142   GPIO_Init(LCD_NWR_GPIO_PORT, &GPIO_InitStructure);
00143
00144   /* Configure SPI pins: SCK, MISO and MOSI */
00145   GPIO_InitStructure.GPIO_Pin = LCD_SPI_SCK_PIN;
00146   GPIO_Init(LCD_SPI_SCK_GPIO_PORT, &GPIO_InitStructure);
00147
00148   GPIO_InitStructure.GPIO_Pin = LCD_SPI_MISO_PIN;
00149   GPIO_Init(LCD_SPI_MISO_GPIO_PORT, &GPIO_InitStructure);
00150
00151   GPIO_InitStructure.GPIO_Pin = LCD_SPI_MOSI_PIN;
00152   GPIO_Init(LCD_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure);
00153 }
00154
00155 /**
00156   * @brief  Setups the LCD.
00157   * @param  None
00158   * @retval None
00159   */
00160 void LCD_Setup(void)
00161 {
00162 /* Configure the LCD Control pins --------------------------------------------*/
00163   LCD_CtrlLinesConfig();
00164
00165 /* Configure the LCD_SPI interface ----------------------------------------------*/
00166   LCD_SPIConfig();
00167
00168   if(LCDType == LCD_ILI9320)
00169   {
00170     _delay_(5); /* Delay 50 ms */
00171     /* Start Initial Sequence ------------------------------------------------*/
00172     LCD_WriteReg(LCD_REG_229, 0x8000); /* Set the internal vcore voltage */
00173     LCD_WriteReg(LCD_REG_0,  0x0001); /* Start internal OSC. */
00174     LCD_WriteReg(LCD_REG_1,  0x0100); /* set SS and SM bit */
00175     LCD_WriteReg(LCD_REG_2,  0x0700); /* set 1 line inversion */
00176     LCD_WriteReg(LCD_REG_3,  0x1030); /* set GRAM write direction and BGR=1. */
00177     LCD_WriteReg(LCD_REG_4,  0x0000); /* Resize register */
00178     LCD_WriteReg(LCD_REG_8,  0x0202); /* set the back porch and front porch */
00179     LCD_WriteReg(LCD_REG_9,  0x0000); /* set non-display area refresh cycle ISC[3:0] */
00180     LCD_WriteReg(LCD_REG_10, 0x0000); /* FMARK function */
00181     LCD_WriteReg(LCD_REG_12, 0x0000); /* RGB interface setting */
00182     LCD_WriteReg(LCD_REG_13, 0x0000); /* Frame marker Position */
00183     LCD_WriteReg(LCD_REG_15, 0x0000); /* RGB interface polarity */
00184     /* Power On sequence -----------------------------------------------------*/
00185     LCD_WriteReg(LCD_REG_16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
00186     LCD_WriteReg(LCD_REG_17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */
00187     LCD_WriteReg(LCD_REG_18, 0x0000); /* VREG1OUT voltage */
00188     LCD_WriteReg(LCD_REG_19, 0x0000); /* VDV[4:0] for VCOM amplitude */
00189     _delay_(20);                      /* Dis-charge capacitor power voltage (200ms) */
00190     LCD_WriteReg(LCD_REG_16, 0x17B0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
00191     LCD_WriteReg(LCD_REG_17, 0x0137); /* DC1[2:0], DC0[2:0], VC[2:0] */
00192     _delay_(5);                       /* Delay 50 ms */
00193     LCD_WriteReg(LCD_REG_18, 0x0139); /* VREG1OUT voltage */
00194     _delay_(5);                       /* Delay 50 ms */
00195     LCD_WriteReg(LCD_REG_19, 0x1d00); /* VDV[4:0] for VCOM amplitude */
00196     LCD_WriteReg(LCD_REG_41, 0x0013); /* VCM[4:0] for VCOMH */
00197     _delay_(5);                       /* Delay 50 ms */
00198     LCD_WriteReg(LCD_REG_32, 0x0000); /* GRAM horizontal Address */
00199     LCD_WriteReg(LCD_REG_33, 0x0000); /* GRAM Vertical Address */
00200     /* Adjust the Gamma Curve ------------------------------------------------*/
00201     LCD_WriteReg(LCD_REG_48, 0x0006);
00202     LCD_WriteReg(LCD_REG_49, 0x0101);
00203     LCD_WriteReg(LCD_REG_50, 0x0003);
00204     LCD_WriteReg(LCD_REG_53, 0x0106);
00205     LCD_WriteReg(LCD_REG_54, 0x0b02);
00206     LCD_WriteReg(LCD_REG_55, 0x0302);
00207     LCD_WriteReg(LCD_REG_56, 0x0707);
00208     LCD_WriteReg(LCD_REG_57, 0x0007);
00209     LCD_WriteReg(LCD_REG_60, 0x0600);
00210     LCD_WriteReg(LCD_REG_61, 0x020b);
00211
00212     /* Set GRAM area ---------------------------------------------------------*/
00213     LCD_WriteReg(LCD_REG_80, 0x0000); /* Horizontal GRAM Start Address */
00214     LCD_WriteReg(LCD_REG_81, 0x00EF); /* Horizontal GRAM End Address */
00215     LCD_WriteReg(LCD_REG_82, 0x0000); /* Vertical GRAM Start Address */
00216     LCD_WriteReg(LCD_REG_83, 0x013F); /* Vertical GRAM End Address */
00217     LCD_WriteReg(LCD_REG_96,  0x2700); /* Gate Scan Line */
00218     LCD_WriteReg(LCD_REG_97,  0x0001); /* NDL,VLE, REV */
00219     LCD_WriteReg(LCD_REG_106, 0x0000); /* set scrolling line */
00220     /* Partial Display Control -----------------------------------------------*/
00221     LCD_WriteReg(LCD_REG_128, 0x0000);
00222     LCD_WriteReg(LCD_REG_129, 0x0000);
00223     LCD_WriteReg(LCD_REG_130, 0x0000);
00224     LCD_WriteReg(LCD_REG_131, 0x0000);
00225     LCD_WriteReg(LCD_REG_132, 0x0000);
00226     LCD_WriteReg(LCD_REG_133, 0x0000);
00227     /* Panel Control ---------------------------------------------------------*/
00228     LCD_WriteReg(LCD_REG_144, 0x0010);
00229     LCD_WriteReg(LCD_REG_146, 0x0000);
00230     LCD_WriteReg(LCD_REG_147, 0x0003);
00231     LCD_WriteReg(LCD_REG_149, 0x0110);
00232     LCD_WriteReg(LCD_REG_151, 0x0000);
00233     LCD_WriteReg(LCD_REG_152, 0x0000);
00234     /* Set GRAM write direction and BGR = 1 */
00235     /* I/D=01 (Horizontal : increment, Vertical : decrement) */
00236     /* AM=1 (address is updated in vertical writing direction) */
00237     LCD_WriteReg(LCD_REG_3, 0x1018);
00238     LCD_WriteReg(LCD_REG_7, 0x0173); /* 262K color and display ON */
00239   }
00240   else if(LCDType == LCD_SPFD5408)
00241   {
00242     /* Start Initial Sequence --------------------------------------------------*/
00243     LCD_WriteReg(LCD_REG_227, 0x3008); /* Set internal timing */
00244     LCD_WriteReg(LCD_REG_231, 0x0012); /* Set internal timing */
00245     LCD_WriteReg(LCD_REG_239, 0x1231); /* Set internal timing */
00246     LCD_WriteReg(LCD_REG_1, 0x0100);   /* Set SS and SM bit */
00247     LCD_WriteReg(LCD_REG_2, 0x0700);   /* Set 1 line inversion */
00248     LCD_WriteReg(LCD_REG_3, 0x1030);   /* Set GRAM write direction and BGR=1. */
00249     LCD_WriteReg(LCD_REG_4, 0x0000);   /* Resize register */
00250     LCD_WriteReg(LCD_REG_8, 0x0202);   /* Set the back porch and front porch */
00251     LCD_WriteReg(LCD_REG_9, 0x0000);   /* Set non-display area refresh cycle ISC[3:0] */
00252     LCD_WriteReg(LCD_REG_10, 0x0000);  /* FMARK function */
00253     LCD_WriteReg(LCD_REG_12, 0x0000);  /* RGB interface setting */
00254     LCD_WriteReg(LCD_REG_13, 0x0000);  /* Frame marker Position */
00255     LCD_WriteReg(LCD_REG_15, 0x0000);  /* RGB interface polarity */
00256     /* Power On sequence -------------------------------------------------------*/
00257     LCD_WriteReg(LCD_REG_16, 0x0000);  /* SAP, BT[3:0], AP, DSTB, SLP, STB */
00258     LCD_WriteReg(LCD_REG_17, 0x0000);  /* DC1[2:0], DC0[2:0], VC[2:0] */
00259     LCD_WriteReg(LCD_REG_18, 0x0000);  /* VREG1OUT voltage */
00260     LCD_WriteReg(LCD_REG_19, 0x0000);  /* VDV[4:0] for VCOM amplitude */
00261     _delay_(20);                /* Dis-charge capacitor power voltage (200ms) */
00262     LCD_WriteReg(LCD_REG_17, 0x0007);  /* DC1[2:0], DC0[2:0], VC[2:0] */
00263     _delay_(5);                 /* Delay 50 ms */
00264     LCD_WriteReg(LCD_REG_16, 0x12B0);  /* SAP, BT[3:0], AP, DSTB, SLP, STB */
00265     _delay_(5);                  /* Delay 50 ms */
00266     LCD_WriteReg(LCD_REG_18, 0x01BD);  /* External reference voltage= Vci */
00267     _delay_(5);                 /* Delay 50 ms */
00268     LCD_WriteReg(LCD_REG_19, 0x1400);       /* VDV[4:0] for VCOM amplitude */
00269     LCD_WriteReg(LCD_REG_41, 0x000E);  /* VCM[4:0] for VCOMH */
00270     _delay_(5);                 /* Delay 50 ms */
00271     LCD_WriteReg(LCD_REG_32, 0x0000);  /* GRAM horizontal Address */
00272     LCD_WriteReg(LCD_REG_33, 0x013F);  /* GRAM Vertical Address */
00273     /* Adjust the Gamma Curve --------------------------------------------------*/
00274     LCD_WriteReg(LCD_REG_48, 0x0007);
00275     LCD_WriteReg(LCD_REG_49, 0x0302);
00276     LCD_WriteReg(LCD_REG_50, 0x0105);
00277     LCD_WriteReg(LCD_REG_53, 0x0206);
00278     LCD_WriteReg(LCD_REG_54, 0x0808);
00279     LCD_WriteReg(LCD_REG_55, 0x0206);
00280     LCD_WriteReg(LCD_REG_56, 0x0504);
00281     LCD_WriteReg(LCD_REG_57, 0x0007);
00282     LCD_WriteReg(LCD_REG_60, 0x0105);
00283     LCD_WriteReg(LCD_REG_61, 0x0808);
00284     /* Set GRAM area -----------------------------------------------------------*/
00285     LCD_WriteReg(LCD_REG_80, 0x0000);  /* Horizontal GRAM Start Address */
00286     LCD_WriteReg(LCD_REG_81, 0x00EF);  /* Horizontal GRAM End Address */
00287     LCD_WriteReg(LCD_REG_82, 0x0000);  /* Vertical GRAM Start Address */
00288     LCD_WriteReg(LCD_REG_83, 0x013F);  /* Vertical GRAM End Address */
00289     LCD_WriteReg(LCD_REG_96,  0xA700); /* Gate Scan Line */
00290     LCD_WriteReg(LCD_REG_97,  0x0001); /* NDL,VLE, REV */
00291     LCD_WriteReg(LCD_REG_106, 0x0000); /* Set scrolling line */
00292     /* Partial Display Control -------------------------------------------------*/
00293     LCD_WriteReg(LCD_REG_128, 0x0000);
00294     LCD_WriteReg(LCD_REG_129, 0x0000);
00295     LCD_WriteReg(LCD_REG_130, 0x0000);
00296     LCD_WriteReg(LCD_REG_131, 0x0000);
00297     LCD_WriteReg(LCD_REG_132, 0x0000);
00298     LCD_WriteReg(LCD_REG_133, 0x0000);
00299     /* Panel Control -----------------------------------------------------------*/
00300     LCD_WriteReg(LCD_REG_144, 0x0010);
00301     LCD_WriteReg(LCD_REG_146, 0x0000);
00302     LCD_WriteReg(LCD_REG_147, 0x0003);
00303     LCD_WriteReg(LCD_REG_149, 0x0110);
00304     LCD_WriteReg(LCD_REG_151, 0x0000);
00305     LCD_WriteReg(LCD_REG_152, 0x0000);
00306     /* Set GRAM write direction and BGR = 1
00307        I/D=01 (Horizontal : increment, Vertical : decrement)
00308        AM=1 (address is updated in vertical writing direction) */
00309     LCD_WriteReg(LCD_REG_3, 0x1018);
00310     LCD_WriteReg(LCD_REG_7, 0x0112);   /* 262K color and display ON */
00311   }
00312   else if(LCDType == LCD_HX8312)
00313   {
00314     /* Enable the LCD Oscillator ---------------------------------------------*/
00315     LCD_WriteReg(LCD_REG_1, 0x10);
00316     LCD_WriteReg(LCD_REG_0, 0xA0);
00317     LCD_WriteReg(LCD_REG_3, 0x01);
00318     _delay_(1); /* Delay 10 ms */
00319     LCD_WriteReg(LCD_REG_3, 0x00);
00320     LCD_WriteReg(LCD_REG_43, 0x04);
00321
00322     LCD_WriteReg(LCD_REG_40, 0x18);
00323     LCD_WriteReg(LCD_REG_26, 0x05);
00324     LCD_WriteReg(LCD_REG_37, 0x05);
00325     LCD_WriteReg(LCD_REG_25, 0x00);
00326
00327     /* LCD Power On ----------------------------------------------------------*/
00328     LCD_WriteReg(LCD_REG_28, 0x73);
00329     LCD_WriteReg(LCD_REG_36, 0x74);
00330     LCD_WriteReg(LCD_REG_30, 0x01);
00331     LCD_WriteReg(LCD_REG_24, 0xC1);
00332     _delay_(1); /* Delay 10 ms */
00333     LCD_WriteReg(LCD_REG_24, 0xE1);
00334     LCD_WriteReg(LCD_REG_24, 0xF1);
00335     _delay_(6); /* Delay 60 ms */
00336     LCD_WriteReg(LCD_REG_24, 0xF5);
00337     _delay_(6); /* Delay 60 ms */
00338     LCD_WriteReg(LCD_REG_27, 0x09);
00339     _delay_(1); /* Delay 10 ms */
00340     LCD_WriteReg(LCD_REG_31, 0x11);
00341     LCD_WriteReg(LCD_REG_32, 0x0E);
00342     LCD_WriteReg(LCD_REG_30, 0x81);
00343     _delay_(1); /* Delay 10 ms */
00344
00345     /* Chip Set --------------------------------------------------------------*/
00346     LCD_WriteReg(LCD_REG_157, 0x00);
00347     LCD_WriteReg(LCD_REG_192, 0x00);
00348
00349     LCD_WriteReg(LCD_REG_14, 0x00);
00350     LCD_WriteReg(LCD_REG_15, 0x00);
00351     LCD_WriteReg(LCD_REG_16, 0x00);
00352     LCD_WriteReg(LCD_REG_17, 0x00);
00353     LCD_WriteReg(LCD_REG_18, 0x00);
00354     LCD_WriteReg(LCD_REG_19, 0x00);
00355     LCD_WriteReg(LCD_REG_20, 0x00);
00356     LCD_WriteReg(LCD_REG_21, 0x00);
00357     LCD_WriteReg(LCD_REG_22, 0x00);
00358     LCD_WriteReg(LCD_REG_23, 0x00);
00359
00360     LCD_WriteReg(LCD_REG_52, 0x01);
00361     LCD_WriteReg(LCD_REG_53, 0x00);
00362     LCD_WriteReg(LCD_REG_75, 0x00);
00363     LCD_WriteReg(LCD_REG_76, 0x00);
00364     LCD_WriteReg(LCD_REG_78, 0x00);
00365     LCD_WriteReg(LCD_REG_79, 0x00);
00366     LCD_WriteReg(LCD_REG_80, 0x00);
00367
00368     LCD_WriteReg(LCD_REG_60, 0x00);
00369     LCD_WriteReg(LCD_REG_61, 0x00);
00370     LCD_WriteReg(LCD_REG_62, 0x01);
00371     LCD_WriteReg(LCD_REG_63, 0x3F);
00372     LCD_WriteReg(LCD_REG_64, 0x02);
00373     LCD_WriteReg(LCD_REG_65, 0x02);
00374     LCD_WriteReg(LCD_REG_66, 0x00);
00375     LCD_WriteReg(LCD_REG_67, 0x00);
00376     LCD_WriteReg(LCD_REG_68, 0x00);
00377     LCD_WriteReg(LCD_REG_69, 0x00);
00378     LCD_WriteReg(LCD_REG_70, 0xEF);
00379     LCD_WriteReg(LCD_REG_71, 0x00);
00380     LCD_WriteReg(LCD_REG_72, 0x00);
00381     LCD_WriteReg(LCD_REG_73, 0x01);
00382     LCD_WriteReg(LCD_REG_74, 0x3F);
00383
00384     LCD_WriteReg(LCD_REG_29, 0x08);  /* R29:Gate scan direction setting */
00385
00386     LCD_WriteReg(LCD_REG_134, 0x00);
00387     LCD_WriteReg(LCD_REG_135, 0x30);
00388     LCD_WriteReg(LCD_REG_136, 0x02);
00389     LCD_WriteReg(LCD_REG_137, 0x05);
00390
00391     LCD_WriteReg(LCD_REG_141, 0x01);  /* R141:Register set-up mode for one line clock */
00392     LCD_WriteReg(LCD_REG_139, 0x20);  /* R139:One line SYSCLK number in one-line */
00393     LCD_WriteReg(LCD_REG_51, 0x01);  /* R51:N line inversion setting */
00394     LCD_WriteReg(LCD_REG_55, 0x01);  /* R55:Scanning method setting */
00395     LCD_WriteReg(LCD_REG_118, 0x00);
00396
00397     /* Gamma Set -------------------------------------------------------------*/
00398     LCD_WriteReg(LCD_REG_143, 0x10);
00399     LCD_WriteReg(LCD_REG_144, 0x67);
00400     LCD_WriteReg(LCD_REG_145, 0x07);
00401     LCD_WriteReg(LCD_REG_146, 0x65);
00402     LCD_WriteReg(LCD_REG_147, 0x07);
00403     LCD_WriteReg(LCD_REG_148, 0x01);
00404     LCD_WriteReg(LCD_REG_149, 0x76);
00405     LCD_WriteReg(LCD_REG_150, 0x56);
00406     LCD_WriteReg(LCD_REG_151, 0x00);
00407     LCD_WriteReg(LCD_REG_152, 0x06);
00408     LCD_WriteReg(LCD_REG_153, 0x03);
00409     LCD_WriteReg(LCD_REG_154, 0x00);
00410
00411     /* Display On ------------------------------------------------------------*/
00412     LCD_WriteReg(LCD_REG_1, 0x50);
00413     LCD_WriteReg(LCD_REG_5, 0x04);
00414     LCD_WriteReg(LCD_REG_0, 0x80);
00415     LCD_WriteReg(LCD_REG_59, 0x01);
00416     _delay_(4);  /* Delay 40 ms */
00417     LCD_WriteReg(LCD_REG_0, 0x20);
00418   }
00419 }
00420
00421
00422 /**
00423   * @brief  Initializes the LCD.
00424   * @param  None
00425   * @retval None
00426   */
00427 void STM32100B_LCD_Init(void)
00428 {
00429   /* Setups the LCD */
00430   LCD_Setup();
00431   /* Try to read new LCD controller ID 0x9320 */
00432   if (LCD_ReadReg(LCD_REG_0) == LCD_ILI9320)
00433   {
00434     LCDType = LCD_ILI9320;
00435   }
00436   else
00437   {
00438     LCDType = LCD_SPFD5408;
00439     /* Setups the LCD */
00440     LCD_Setup();
00441     /* Try to read new LCD controller ID 0x5408 */
00442     if (LCD_ReadReg(LCD_REG_0) != LCD_SPFD5408)
00443     {
00444       LCDType = LCD_HX8312;
00445       /* Setups the LCD */
00446       LCD_Setup();
00447     }
00448   }
00449   LCD_SetFont(&LCD_DEFAULT_FONT);
00450 }
00451
00452 /**
00453   * @brief  Sets the LCD Text and Background colors.
00454   * @param  _TextColor: specifies the Text Color.
00455   * @param  _BackColor: specifies the Background Color.
00456   * @retval None
00457   */
00458 void LCD_SetColors(__IO uint16_t _TextColor, __IO uint16_t _BackColor)
00459 {
00460   TextColor = _TextColor;
00461   BackColor = _BackColor;
00462 }
00463
00464 /**
00465   * @brief  Gets the LCD Text and Background colors.
00466   * @param  _TextColor: pointer to the variable that will contain the Text
00467             Color.
00468   * @param  _BackColor: pointer to the variable that will contain the Background
00469             Color.
00470   * @retval None
00471   */
00472 void LCD_GetColors(__IO uint16_t *_TextColor, __IO uint16_t *_BackColor)
00473 {
00474   *_TextColor = TextColor; *_BackColor = BackColor;
00475 }
00476
00477 /**
00478   * @brief  Sets the Text color.
00479   * @param  Color: specifies the Text color code RGB(5-6-5).
00480   * @retval None
00481   */
00482 void LCD_SetTextColor(__IO uint16_t Color)
00483 {
00484   TextColor = Color;
00485 }
00486
00487
00488 /**
00489   * @brief  Sets the Background color.
00490   * @param  Color: specifies the Background color code RGB(5-6-5).
00491   * @retval None
00492   */
00493 void LCD_SetBackColor(__IO uint16_t Color)
00494 {
00495   BackColor = Color;
00496 }
00497
00498 /**
00499   * @brief  Sets the Text Font.
00500   * @param  fonts: specifies the font to be used.
00501   * @retval None
00502   */
00503 void LCD_SetFont(sFONT *fonts)
00504 {
00505   LCD_Currentfonts = fonts;
00506 }
00507
00508 /**
00509   * @brief  Gets the Text Font.
00510   * @param  None.
00511   * @retval the used font.
00512   */
00513 sFONT *LCD_GetFont(void)
00514 {
00515   return LCD_Currentfonts;
00516 }
00517
00518 /**
00519   * @brief  Clears the selected line.
00520   * @param  Line: the Line to be cleared.
00521   *   This parameter can be one of the following values:
00522   *     @arg Linex: where x can be 0..n
00523   * @retval None
00524   */
00525 void LCD_ClearLine(uint8_t Line)
00526 {
00527   uint16_t refcolumn = LCD_PIXEL_WIDTH - 1;
00528   /* Send the string character by character on lCD */
00529   while (((refcolumn + 1) & 0xFFFF) >= LCD_Currentfonts->Width)
00530   {
00531     /* Display one character on LCD */
00532     LCD_DisplayChar(Line, refcolumn, ' ');
00533     /* Decrement the column position by 16 */
00534     refcolumn -= LCD_Currentfonts->Width;
00535   }
00536 }
00537
00538
00539 /**
00540   * @brief  Clears the hole LCD.
00541   * @param  Color: the color of the background.
00542   * @retval None
00543   */
00544 void LCD_Clear(uint16_t Color)
00545 {
00546   uint32_t index = 0;
00547
00548   LCD_SetCursor(0x00, 0x013F);
00549   if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
00550   {
00551     LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
00552   }
00553   for(index = 0; index < 76800; index++)
00554   {
00555     LCD_WriteRAM(Color);
00556   }
00557   if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
00558   {
00559     LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
00560   }
00561 }
00562
00563
00564 /**
00565   * @brief  Sets the cursor position.
00566   * @param  Xpos: specifies the X position.
00567   * @param  Ypos: specifies the Y position.
00568   * @retval None
00569   */
00570 void LCD_SetCursor(uint8_t Xpos, uint16_t Ypos)
00571 {
00572   if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
00573   {
00574     LCD_WriteReg(LCD_REG_32, Xpos);
00575     LCD_WriteReg(LCD_REG_33, Ypos);
00576   }
00577   else if(LCDType == LCD_HX8312)
00578   {
00579     LCD_WriteReg(LCD_REG_66, Xpos);
00580     LCD_WriteReg(LCD_REG_67, ((Ypos & 0x100)>> 8));
00581     LCD_WriteReg(LCD_REG_68, (Ypos & 0xFF));
00582   }
00583 }
00584
00585
00586 /**
00587   * @brief  Draws a character on LCD.
00588   * @param  Xpos: the Line where to display the character shape.
00589   * @param  Ypos: start column address.
00590   * @param  c: pointer to the character data.
00591   * @retval None
00592   */
00593 void LCD_DrawChar(uint8_t Xpos, uint16_t Ypos, const uint16_t *c)
00594 {
00595   uint32_t index = 0, i = 0;
00596   uint8_t Xaddress = 0;
00597
00598   Xaddress = Xpos;
00599
00600   LCD_SetCursor(Xaddress, Ypos);
00601
00602   for(index = 0; index < LCD_Currentfonts->Height; index++)
00603   {
00604     if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
00605     {
00606       LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
00607     }
00608     for(i = 0; i < LCD_Currentfonts->Width; i++)
00609     {
00610       if((((c[index] & ((0x80 << ((LCD_Currentfonts->Width / 12 ) * 8 ) ) >> i)) == 0x00) &&(LCD_Currentfonts->Width <= 12))||
00611         (((c[index] & (0x1 << i)) == 0x00)&&(LCD_Currentfonts->Width > 12 )))
00612
00613       {
00614         LCD_WriteRAM(BackColor);
00615       }
00616       else
00617       {
00618         LCD_WriteRAM(TextColor);
00619       }
00620     }
00621     if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
00622     {
00623       LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
00624     }
00625     Xaddress++;
00626     LCD_SetCursor(Xaddress, Ypos);
00627   }
00628 }
00629
00630
00631 /**
00632   * @brief  Displays one character (16dots width, 24dots height).
00633   * @param  Line: the Line where to display the character shape .
00634   *   This parameter can be one of the following values:
00635   *     @arg Linex: where x can be 0..9
00636   * @param  Column: start column address.
00637   * @param  Ascii: character ascii code, must be between 0x20 and 0x7E.
00638   * @retval None
00639   */
00640 void LCD_DisplayChar(uint8_t Line, uint16_t Column, uint8_t Ascii)
00641 {
00642   Ascii -= 32;
00643   LCD_DrawChar(Line, Column, &LCD_Currentfonts->table[Ascii * LCD_Currentfonts->Height]);
00644 }
00645
00646
00647 /**
00648   * @brief  Displays a maximum of 20 char on the LCD.
00649   * @param  Line: the Line where to display the character shape .
00650   *   This parameter can be one of the following values:
00651   *     @arg Linex: where x can be 0..9
00652   * @param  *ptr: pointer to string to display on LCD.
00653   * @retval None
00654   */
00655 void LCD_DisplayStringLine(uint8_t Line, uint8_t *ptr)
00656 {
00657   uint16_t refcolumn = LCD_PIXEL_WIDTH - 1;
00658
00659   /* Send the string character by character on lCD */
00660   while ((*ptr != 0) & (((refcolumn + 1) & 0xFFFF) >= LCD_Currentfonts->Width))
00661   {
00662     /* Display one character on LCD */
00663     LCD_DisplayChar(Line, refcolumn, *ptr);
00664     /* Decrement the column position by 16 */
00665     refcolumn -= LCD_Currentfonts->Width;
00666     /* Point on the next character */
00667     ptr++;
00668   }
00669 }
00670
00671
00672 /**
00673   * @brief  Sets a display window
00674   * @param  Xpos: specifies the X buttom left position.
00675   * @param  Ypos: specifies the Y buttom left position.
00676   * @param  Height: display window height.
00677   * @param  Width: display window width.
00678   * @retval None
00679   */
00680 void LCD_SetDisplayWindow(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width)
00681 {
00682   if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
00683   {
00684     /* Horizontal GRAM Start Address */
00685     if(Xpos >= Height)
00686     {
00687       LCD_WriteReg(LCD_REG_80, (Xpos - Height + 1));
00688     }
00689     else
00690     {
00691       LCD_WriteReg(LCD_REG_80, 0);
00692     }
00693     /* Horizontal GRAM End Address */
00694     LCD_WriteReg(LCD_REG_81, Xpos);
00695     /* Vertical GRAM Start Address */
00696     if(Ypos >= Width)
00697     {
00698       LCD_WriteReg(LCD_REG_82, (Ypos - Width + 1));
00699     }
00700     else
00701     {
00702       LCD_WriteReg(LCD_REG_82, 0);
00703     }
00704     /* Vertical GRAM End Address */
00705     LCD_WriteReg(LCD_REG_83, Ypos);
00706   }
00707   else if(LCDType == LCD_HX8312)
00708   {
00709     LCD_WriteReg(LCD_REG_1, 0xD0);
00710     LCD_WriteReg(LCD_REG_5, 0x14);
00711
00712     LCD_WriteReg(LCD_REG_69, (Xpos - Height + 1));
00713     LCD_WriteReg(LCD_REG_70, Xpos);
00714
00715     LCD_WriteReg(LCD_REG_71, (((Ypos - Width + 1) & 0x100)>> 8));
00716     LCD_WriteReg(LCD_REG_72, ((Ypos - Width + 1) & 0xFF));
00717     LCD_WriteReg(LCD_REG_73, ((Ypos & 0x100)>> 8));
00718     LCD_WriteReg(LCD_REG_74, (Ypos & 0xFF));
00719   }
00720   LCD_SetCursor(Xpos, Ypos);
00721 }
00722
00723
00724 /**
00725   * @brief  Disables LCD Window mode.
00726   * @param  None
00727   * @retval None
00728   */
00729 void LCD_WindowModeDisable(void)
00730 {
00731   if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
00732   {
00733     LCD_SetDisplayWindow(239, 0x13F, 240, 320);
00734     LCD_WriteReg(LCD_REG_3, 0x1018);
00735   }
00736   else if(LCDType == LCD_HX8312)
00737   {
00738     LCD_WriteReg(LCD_REG_1, 0x50);
00739     LCD_WriteReg(LCD_REG_5, 0x04);
00740   }
00741
00742 }
00743
00744 /**
00745   * @brief  Displays a line.
00746   * @param  Xpos: specifies the X position.
00747   * @param  Ypos: specifies the Y position.
00748   * @param  Length: line length.
00749   * @param  Direction: line direction.
00750   *   This parameter can be one of the following values: Vertical or Horizontal.
00751   * @retval None
00752   */
00753 void LCD_DrawLine(uint8_t Xpos, uint16_t Ypos, uint16_t Length, uint8_t Direction)
00754 {
00755   uint32_t i = 0;
00756
00757   LCD_SetCursor(Xpos, Ypos);
00758   if(Direction == LCD_DIR_HORIZONTAL)
00759   {
00760     if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
00761     {
00762       LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
00763     }
00764     for(i = 0; i < Length; i++)
00765     {
00766       LCD_WriteRAM(TextColor);
00767     }
00768     if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
00769     {
00770       LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
00771     }
00772   }
00773   else
00774   {
00775    for(i = 0; i < Length; i++)
00776     {
00777       if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
00778       {
00779         LCD_WriteRAMWord(TextColor);
00780       }
00781       else  if(LCDType == LCD_HX8312)
00782       {
00783         LCD_WriteRAM(TextColor);
00784       }
00785       Xpos++;
00786       LCD_SetCursor(Xpos, Ypos);
00787     }
00788   }
00789 }
00790
00791
00792 /**
00793   * @brief  Displays a rectangle.
00794   * @param  Xpos: specifies the X position.
00795   * @param  Ypos: specifies the Y position.
00796   * @param  Height: display rectangle height.
00797   * @param  Width: display rectangle width.
00798   * @retval None
00799   */
00800 void LCD_DrawRect(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width)
00801 {
00802   LCD_DrawLine(Xpos, Ypos, Width, LCD_DIR_HORIZONTAL);
00803   LCD_DrawLine((Xpos + Height), Ypos, Width, LCD_DIR_HORIZONTAL);
00804
00805   LCD_DrawLine(Xpos, Ypos, Height, LCD_DIR_VERTICAL);
00806   LCD_DrawLine(Xpos, (Ypos - Width + 1), Height, LCD_DIR_VERTICAL);
00807 }
00808
00809
00810 /**
00811   * @brief  Displays a circle.
00812   * @param  Xpos: specifies the X position.
00813   * @param  Ypos: specifies the Y position.
00814   * @param  Radius
00815   * @retval None
00816   */
00817 void LCD_DrawCircle(uint8_t Xpos, uint16_t Ypos, uint16_t Radius)
00818 {
00819   int32_t  D;/* Decision Variable */
00820   uint32_t  CurX;/* Current X Value */
00821   uint32_t  CurY;/* Current Y Value */
00822
00823   D = 3 - (Radius << 1);
00824   CurX = 0;
00825   CurY = Radius;
00826
00827   while (CurX <= CurY)
00828   {
00829     LCD_SetCursor(Xpos + CurX, Ypos + CurY);
00830     if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
00831     {
00832       LCD_WriteRAMWord(TextColor);
00833     }
00834     else if(LCDType == LCD_HX8312)
00835     {
00836       LCD_WriteRAM(TextColor);
00837     }
00838     LCD_SetCursor(Xpos + CurX, Ypos - CurY);
00839
00840     if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
00841     {
00842       LCD_WriteRAMWord(TextColor);
00843     }
00844     else if(LCDType == LCD_HX8312)
00845     {
00846       LCD_WriteRAM(TextColor);
00847     }
00848     LCD_SetCursor(Xpos - CurX, Ypos + CurY);
00849
00850     if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
00851     {
00852       LCD_WriteRAMWord(TextColor);
00853     }
00854     else if(LCDType == LCD_HX8312)
00855     {
00856       LCD_WriteRAM(TextColor);
00857     }
00858     LCD_SetCursor(Xpos - CurX, Ypos - CurY);
00859
00860     if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
00861     {
00862       LCD_WriteRAMWord(TextColor);
00863     }
00864     else if(LCDType == LCD_HX8312)
00865     {
00866       LCD_WriteRAM(TextColor);
00867     }
00868     LCD_SetCursor(Xpos + CurY, Ypos + CurX);
00869     if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
00870     {
00871       LCD_WriteRAMWord(TextColor);
00872     }
00873     else if(LCDType == LCD_HX8312)
00874     {
00875       LCD_WriteRAM(TextColor);
00876     }
00877     LCD_SetCursor(Xpos + CurY, Ypos - CurX);
00878
00879     if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
00880     {
00881       LCD_WriteRAMWord(TextColor);
00882     }
00883     else if(LCDType == LCD_HX8312)
00884     {
00885       LCD_WriteRAM(TextColor);
00886     }
00887     LCD_SetCursor(Xpos - CurY, Ypos + CurX);
00888
00889     if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
00890     {
00891       LCD_WriteRAMWord(TextColor);
00892     }
00893     else if(LCDType == LCD_HX8312)
00894     {
00895       LCD_WriteRAM(TextColor);
00896     }
00897     LCD_SetCursor(Xpos - CurY, Ypos - CurX);
00898
00899     if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
00900     {
00901       LCD_WriteRAMWord(TextColor);
00902     }
00903     else if(LCDType == LCD_HX8312)
00904     {
00905       LCD_WriteRAM(TextColor);
00906     }
00907     if (D < 0)
00908     {
00909       D += (CurX << 2) + 6;
00910     }
00911     else
00912     {
00913       D += ((CurX - CurY) << 2) + 10;
00914       CurY--;
00915     }
00916     CurX++;
00917   }
00918 }
00919
00920
00921 /**
00922   * @brief  Displays a monocolor picture.
00923   * @param  Pict: pointer to the picture array.
00924   * @retval None
00925   */
00926 void LCD_DrawMonoPict(const uint32_t *Pict)
00927 {
00928   uint32_t index = 0, i = 0;
00929   LCD_SetCursor(0, (LCD_PIXEL_WIDTH - 1));
00930
00931   if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
00932   {
00933     LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
00934   }
00935
00936   for(index = 0; index < 2400; index++)
00937   {
00938     for(i = 0; i < 32; i++)
00939     {
00940       if((Pict[index] & (1 << i)) == 0x00)
00941       {
00942         LCD_WriteRAM(BackColor);
00943       }
00944       else
00945       {
00946         LCD_WriteRAM(TextColor);
00947       }
00948     }
00949   }
00950
00951   if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
00952   {
00953     LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
00954   }
00955 }
00956
00957 #ifdef USE_LCD_DrawBMP
00958 /**
00959   * @brief  Displays a bitmap picture loaded in the SPI Flash.
00960   * @param  BmpAddress: Bmp picture address in the SPI Flash.
00961   * @retval None
00962   */
00963 void LCD_DrawBMP(uint32_t BmpAddress)
00964 {
00965   uint32_t i = 0, size = 0;
00966   /* Read bitmap size */
00967   sFLASH_ReadBuffer((uint8_t*)&size, BmpAddress + 2, 4);
00968   /* get bitmap data address offset */
00969   sFLASH_ReadBuffer((uint8_t*)&i, BmpAddress + 10, 4);
00970
00971   size = (size - i)/2;
00972   sFLASH_StartReadSequence(BmpAddress + i);
00973   /* Disable LCD_SPI  */
00974   SPI_Cmd(LCD_SPI, DISABLE);
00975   /* SPI in 16-bit mode */
00976   SPI_DataSizeConfig(LCD_SPI, SPI_DataSize_16b);
00977   /* Enable LCD_SPI  */
00978   SPI_Cmd(LCD_SPI, ENABLE);
00979
00980   if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
00981   {
00982     /* Set GRAM write direction and BGR = 1 */
00983     /* I/D=00 (Horizontal : decrement, Vertical : decrement) */
00984     /* AM=1 (address is updated in vertical writing direction) */
00985     LCD_WriteReg(LCD_REG_3, 0x1008);
00986     LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
00987   }
00988
00989   /* Read bitmap data from SPI Flash and send them to LCD */
00990   for(i = 0; i < size; i++)
00991   {
00992     LCD_WriteRAM(__REV16(sFLASH_SendHalfWord(0xA5A5)));
00993   }
00994   if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
00995   {
00996     LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
00997   }
00998
00999   /* Deselect the FLASH: Chip Select high */
01000   sFLASH_CS_HIGH();
01001   /* Disable LCD_SPI  */
01002   SPI_Cmd(LCD_SPI, DISABLE);
01003   /* SPI in 8-bit mode */
01004   SPI_DataSizeConfig(LCD_SPI, SPI_DataSize_8b);
01005   /* Enable LCD_SPI  */
01006   SPI_Cmd(LCD_SPI, ENABLE);
01007
01008   if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
01009   {
01010     /* Set GRAM write direction and BGR = 1 */
01011     /* I/D = 01 (Horizontal : increment, Vertical : decrement) */
01012     /* AM = 1 (address is updated in vertical writing direction) */
01013     LCD_WriteReg(LCD_REG_3, 0x1018);
01014   }
01015 }
01016 #endif /* USE_LCD_DrawBMP */
01017
01018 /**
01019   * @brief  Displays a full rectangle.
01020   * @param  Xpos: specifies the X position.
01021   * @param  Ypos: specifies the Y position.
01022   * @param  Height: rectangle height.
01023   * @param  Width: rectangle width.
01024   * @retval None
01025   */
01026 void LCD_DrawFullRect(uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height)
01027 {
01028   LCD_SetTextColor(TextColor);
01029
01030   LCD_DrawLine(Xpos, Ypos, Width, LCD_DIR_HORIZONTAL);
01031   LCD_DrawLine((Xpos + Height), Ypos, Width, LCD_DIR_HORIZONTAL);
01032
01033   LCD_DrawLine(Xpos, Ypos, Height, LCD_DIR_VERTICAL);
01034   LCD_DrawLine(Xpos, (Ypos - Width + 1), Height, LCD_DIR_VERTICAL);
01035
01036   Width -= 2;
01037   Height--;
01038   Ypos--;
01039
01040   LCD_SetTextColor(BackColor);
01041
01042   while(Height--)
01043   {
01044     LCD_DrawLine(++Xpos, Ypos, Width, LCD_DIR_HORIZONTAL);
01045   }
01046
01047   LCD_SetTextColor(TextColor);
01048 }
01049
01050 /**
01051   * @brief  Displays a full circle.
01052   * @param  Xpos: specifies the X position.
01053   * @param  Ypos: specifies the Y position.
01054   * @param  Radius
01055   * @retval None
01056   */
01057 void LCD_DrawFullCircle(uint16_t Xpos, uint16_t Ypos, uint16_t Radius)
01058 {
01059   int32_t  D;    /* Decision Variable */
01060   uint32_t  CurX;/* Current X Value */
01061   uint32_t  CurY;/* Current Y Value */
01062
01063   D = 3 - (Radius << 1);
01064
01065   CurX = 0;
01066   CurY = Radius;
01067
01068   LCD_SetTextColor(BackColor);
01069
01070   while (CurX <= CurY)
01071   {
01072     if(CurY > 0)
01073     {
01074       LCD_DrawLine(Xpos - CurX, Ypos + CurY, 2*CurY, LCD_DIR_HORIZONTAL);
01075       LCD_DrawLine(Xpos + CurX, Ypos + CurY, 2*CurY, LCD_DIR_HORIZONTAL);
01076     }
01077
01078     if(CurX > 0)
01079     {
01080       LCD_DrawLine(Xpos - CurY, Ypos + CurX, 2*CurX, LCD_DIR_HORIZONTAL);
01081       LCD_DrawLine(Xpos + CurY, Ypos + CurX, 2*CurX, LCD_DIR_HORIZONTAL);
01082     }
01083     if (D < 0)
01084     {
01085       D += (CurX << 2) + 6;
01086     }
01087     else
01088     {
01089       D += ((CurX - CurY) << 2) + 10;
01090       CurY--;
01091     }
01092     CurX++;
01093   }
01094
01095   LCD_SetTextColor(TextColor);
01096   LCD_DrawCircle(Xpos, Ypos, Radius);
01097 }
01098
01099 /**
01100   * @brief  Displays an uni line (between two points).
01101   * @param  x1: specifies the point 1 x position.
01102   * @param  y1: specifies the point 1 y position.
01103   * @param  x2: specifies the point 2 x position.
01104   * @param  y2: specifies the point 2 y position.
01105   * @retval None
01106   */
01107 void LCD_DrawUniLine(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2)
01108 {
01109   int16_t deltax = 0, deltay = 0, x = 0, y = 0, xinc1 = 0, xinc2 = 0,
01110   yinc1 = 0, yinc2 = 0, den = 0, num = 0, numadd = 0, numpixels = 0,
01111   curpixel = 0;
01112
01113   deltax = ABS(x2 - x1);        /* The difference between the x's */
01114   deltay = ABS(y2 - y1);        /* The difference between the y's */
01115   x = x1;                       /* Start x off at the first pixel */
01116   y = y1;                       /* Start y off at the first pixel */
01117
01118   if (x2 >= x1)                 /* The x-values are increasing */
01119   {
01120     xinc1 = 1;
01121     xinc2 = 1;
01122   }
01123   else                          /* The x-values are decreasing */
01124   {
01125     xinc1 = -1;
01126     xinc2 = -1;
01127   }
01128
01129   if (y2 >= y1)                 /* The y-values are increasing */
01130   {
01131     yinc1 = 1;
01132     yinc2 = 1;
01133   }
01134   else                          /* The y-values are decreasing */
01135   {
01136     yinc1 = -1;
01137     yinc2 = -1;
01138   }
01139
01140   if (deltax >= deltay)         /* There is at least one x-value for every y-value */
01141   {
01142     xinc1 = 0;                  /* Don't change the x when numerator >= denominator */
01143     yinc2 = 0;                  /* Don't change the y for every iteration */
01144     den = deltax;
01145     num = deltax / 2;
01146     numadd = deltay;
01147     numpixels = deltax;         /* There are more x-values than y-values */
01148   }
01149   else                          /* There is at least one y-value for every x-value */
01150   {
01151     xinc2 = 0;                  /* Don't change the x for every iteration */
01152     yinc1 = 0;                  /* Don't change the y when numerator >= denominator */
01153     den = deltay;
01154     num = deltay / 2;
01155     numadd = deltax;
01156     numpixels = deltay;         /* There are more y-values than x-values */
01157   }
01158
01159   for (curpixel = 0; curpixel <= numpixels; curpixel++)
01160   {
01161     PutPixel(x, y);             /* Draw the current pixel */
01162     num += numadd;              /* Increase the numerator by the top of the fraction */
01163     if (num >= den)             /* Check if numerator >= denominator */
01164     {
01165       num -= den;               /* Calculate the new numerator value */
01166       x += xinc1;               /* Change the x as appropriate */
01167       y += yinc1;               /* Change the y as appropriate */
01168     }
01169     x += xinc2;                 /* Change the x as appropriate */
01170     y += yinc2;                 /* Change the y as appropriate */
01171   }
01172 }
01173
01174 /**
01175   * @brief  Displays an polyline (between many points).
01176   * @param  Points: pointer to the points array.
01177   * @param  PointCount: Number of points.
01178   * @retval None
01179   */
01180 void LCD_PolyLine(pPoint Points, uint16_t PointCount)
01181 {
01182   int16_t X = 0, Y = 0;
01183
01184   if(PointCount < 2)
01185   {
01186     return;
01187   }
01188
01189   while(--PointCount)
01190   {
01191     X = Points->X;
01192     Y = Points->Y;
01193     Points++;
01194     LCD_DrawUniLine(X, Y, Points->X, Points->Y);
01195   }
01196 }
01197
01198 /**
01199   * @brief  Displays an relative polyline (between many points).
01200   * @param  Points: pointer to the points array.
01201   * @param  PointCount: Number of points.
01202   * @param  Closed: specifies if the draw is closed or not.
01203   *           1: closed, 0 : not closed.
01204   * @retval None
01205   */
01206 static void LCD_PolyLineRelativeClosed(pPoint Points, uint16_t PointCount, uint16_t Closed)
01207 {
01208   int16_t X = 0, Y = 0;
01209   pPoint First = Points;
01210
01211   if(PointCount < 2)
01212   {
01213     return;
01214   }
01215   X = Points->X;
01216   Y = Points->Y;
01217   while(--PointCount)
01218   {
01219     Points++;
01220     LCD_DrawUniLine(X, Y, X + Points->X, Y + Points->Y);
01221     X = X + Points->X;
01222     Y = Y + Points->Y;
01223   }
01224   if(Closed)
01225   {
01226     LCD_DrawUniLine(First->X, First->Y, X, Y);
01227   }
01228 }
01229
01230 /**
01231   * @brief  Displays a closed polyline (between many points).
01232   * @param  Points: pointer to the points array.
01233   * @param  PointCount: Number of points.
01234   * @retval None
01235   */
01236 void LCD_ClosedPolyLine(pPoint Points, uint16_t PointCount)
01237 {
01238   LCD_PolyLine(Points, PointCount);
01239   LCD_DrawUniLine(Points->X, Points->Y, (Points+PointCount-1)->X, (Points+PointCount-1)->Y);
01240 }
01241
01242 /**
01243   * @brief  Displays a relative polyline (between many points).
01244   * @param  Points: pointer to the points array.
01245   * @param  PointCount: Number of points.
01246   * @retval None
01247   */
01248 void LCD_PolyLineRelative(pPoint Points, uint16_t PointCount)
01249 {
01250   LCD_PolyLineRelativeClosed(Points, PointCount, 0);
01251 }
01252
01253 /**
01254   * @brief  Displays a closed relative polyline (between many points).
01255   * @param  Points: pointer to the points array.
01256   * @param  PointCount: Number of points.
01257   * @retval None
01258   */
01259 void LCD_ClosedPolyLineRelative(pPoint Points, uint16_t PointCount)
01260 {
01261   LCD_PolyLineRelativeClosed(Points, PointCount, 1);
01262 }
01263
01264
01265 /**
01266   * @brief  Displays a  full polyline (between many points).
01267   * @param  Points: pointer to the points array.
01268   * @param  PointCount: Number of points.
01269   * @retval None
01270   */
01271 void LCD_FillPolyLine(pPoint Points, uint16_t PointCount)
01272 {
01273   /*  public-domain code by Darel Rex Finley, 2007 */
01274   uint16_t  nodes = 0, nodeX[MAX_POLY_CORNERS], pixelX = 0, pixelY = 0, i = 0,
01275   j = 0, swap = 0;
01276   uint16_t  IMAGE_LEFT = 0, IMAGE_RIGHT = 0, IMAGE_TOP = 0, IMAGE_BOTTOM = 0;
01277
01278   IMAGE_LEFT = IMAGE_RIGHT = Points->X;
01279   IMAGE_TOP= IMAGE_BOTTOM = Points->Y;
01280
01281   for(i = 1; i < PointCount; i++)
01282   {
01283     pixelX = POLY_X(i);
01284     if(pixelX < IMAGE_LEFT)
01285     {
01286       IMAGE_LEFT = pixelX;
01287     }
01288     if(pixelX > IMAGE_RIGHT)
01289     {
01290       IMAGE_RIGHT = pixelX;
01291     }
01292
01293     pixelY = POLY_Y(i);
01294     if(pixelY < IMAGE_TOP)
01295     {
01296       IMAGE_TOP = pixelY;
01297     }
01298     if(pixelY > IMAGE_BOTTOM)
01299     {
01300       IMAGE_BOTTOM = pixelY;
01301     }
01302   }
01303
01304   LCD_SetTextColor(BackColor);
01305
01306   /*  Loop through the rows of the image. */
01307   for (pixelY = IMAGE_TOP; pixelY < IMAGE_BOTTOM; pixelY++)
01308   {
01309     /* Build a list of nodes. */
01310     nodes = 0; j = PointCount-1;
01311
01312     for (i = 0; i < PointCount; i++)
01313     {
01314       if (POLY_Y(i)<(double) pixelY && POLY_Y(j)>=(double) pixelY || POLY_Y(j)<(double) pixelY && POLY_Y(i)>=(double) pixelY)
01315       {
01316         nodeX[nodes++]=(int) (POLY_X(i)+((pixelY-POLY_Y(i))*(POLY_X(j)-POLY_X(i)))/(POLY_Y(j)-POLY_Y(i)));
01317       }
01318       j = i;
01319     }
01320
01321     /* Sort the nodes, via a simple "Bubble" sort. */
01322     i = 0;
01323     while (i < nodes-1)
01324     {
01325       if (nodeX[i]>nodeX[i+1])
01326       {
01327         swap = nodeX[i];
01328         nodeX[i] = nodeX[i+1];
01329         nodeX[i+1] = swap;
01330         if(i)
01331         {
01332           i--;
01333         }
01334       }
01335       else
01336       {
01337         i++;
01338       }
01339     }
01340
01341     /*  Fill the pixels between node pairs. */
01342     for (i = 0; i < nodes; i+=2)
01343     {
01344       if(nodeX[i] >= IMAGE_RIGHT)
01345       {
01346         break;
01347       }
01348       if(nodeX[i+1] > IMAGE_LEFT)
01349       {
01350         if (nodeX[i] < IMAGE_LEFT)
01351         {
01352           nodeX[i]=IMAGE_LEFT;
01353         }
01354         if(nodeX[i+1] > IMAGE_RIGHT)
01355         {
01356           nodeX[i+1] = IMAGE_RIGHT;
01357         }
01358         LCD_SetTextColor(BackColor);
01359         LCD_DrawLine(pixelY, nodeX[i+1], nodeX[i+1] - nodeX[i], LCD_DIR_HORIZONTAL);
01360         LCD_SetTextColor(TextColor);
01361         PutPixel(pixelY, nodeX[i+1]);
01362         PutPixel(pixelY, nodeX[i]);
01363         /* for (j=nodeX[i]; j<nodeX[i+1]; j++) PutPixel(j,pixelY); */
01364       }
01365     }
01366   }
01367
01368   /* draw the edges */
01369   LCD_SetTextColor(TextColor);
01370 }
01371
01372 /**
01373   * @brief  Reset LCD control line(/CS) and Send Start-Byte
01374   * @param  Start_Byte: the Start-Byte to be sent
01375   * @retval None
01376   */
01377 void LCD_nCS_StartByte(uint8_t Start_Byte)
01378 {
01379   LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_RESET);
01380
01381   SPI_I2S_SendData(LCD_SPI, Start_Byte);
01382
01383   while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
01384   {
01385   }
01386 }
01387
01388
01389 /**
01390   * @brief  Writes index to select the LCD register.
01391   * @param  LCD_Reg: address of the selected register.
01392   * @retval None
01393   */
01394 void LCD_WriteRegIndex(uint8_t LCD_Reg)
01395 {
01396   /* Reset LCD control line(/CS) and Send Start-Byte */
01397   LCD_nCS_StartByte(START_BYTE | SET_INDEX);
01398
01399   /* Write 16-bit Reg Index (High Byte is 0) */
01400   SPI_I2S_SendData(LCD_SPI, 0x00);
01401
01402   while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
01403   {
01404   }
01405
01406   SPI_I2S_SendData(LCD_SPI, LCD_Reg);
01407
01408   while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
01409   {
01410   }
01411
01412   LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
01413 }
01414
01415
01416 /**
01417   * @brief  Writes to the selected LCD ILI9320 register.
01418   * @param  LCD_Reg: address of the selected register.
01419   * @param  LCD_RegValue: value to write to the selected register.
01420   * @retval None
01421   */
01422 static void LCD_WriteRegILI9320(uint8_t LCD_Reg, uint16_t LCD_RegValue)
01423 {
01424   /* Write 16-bit Index (then Write Reg) */
01425   LCD_WriteRegIndex(LCD_Reg);
01426
01427   /* Write 16-bit Reg */
01428   /* Reset LCD control line(/CS) and Send Start-Byte */
01429   LCD_nCS_StartByte(START_BYTE | LCD_WRITE_REG);
01430
01431   SPI_I2S_SendData(LCD_SPI, LCD_RegValue>>8);
01432
01433   while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
01434   {
01435   }
01436
01437   SPI_I2S_SendData(LCD_SPI, (LCD_RegValue & 0xFF));
01438
01439   while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
01440   {
01441   }
01442
01443   LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
01444 }
01445
01446
01447 /**
01448   * @brief  Reads the selected LCD Register.
01449   * @param  LCD_Reg: address of the selected register.
01450   * @retval LCD Register Value.
01451   */
01452 uint16_t LCD_ReadReg(uint8_t LCD_Reg)
01453 {
01454   uint16_t tmp = 0;
01455   uint8_t i = 0;
01456
01457   /* LCD_SPI prescaler: 4 */
01458   LCD_SPI->CR1 &= 0xFFC7;
01459   LCD_SPI->CR1 |= 0x0008;
01460   /* Write 16-bit Index (then Read Reg) */
01461   LCD_WriteRegIndex(LCD_Reg);
01462   /* Read 16-bit Reg */
01463   /* Reset LCD control line(/CS) and Send Start-Byte */
01464   LCD_nCS_StartByte(START_BYTE | LCD_READ_REG);
01465
01466   for(i = 0; i < 5; i++)
01467   {
01468     SPI_I2S_SendData(LCD_SPI, 0xFF);
01469     while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
01470     {
01471     }
01472     /* One byte of invalid dummy data read after the start byte */
01473     while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_RXNE) == RESET)
01474     {
01475     }
01476     SPI_I2S_ReceiveData(LCD_SPI);
01477   }
01478
01479   SPI_I2S_SendData(LCD_SPI, 0xFF);
01480
01481   /* Read upper byte */
01482   while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
01483   {
01484   }
01485
01486   /* Read lower byte */
01487   while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_RXNE) == RESET)
01488   {
01489   }
01490   tmp = SPI_I2S_ReceiveData(LCD_SPI);
01491
01492
01493   SPI_I2S_SendData(LCD_SPI, 0xFF);
01494   while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
01495   {
01496   }
01497
01498   /* Read lower byte */
01499   while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_RXNE) == RESET)
01500   {
01501   }
01502
01503   tmp = ((tmp & 0xFF) << 8) | SPI_I2S_ReceiveData(LCD_SPI);
01504   LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
01505
01506   /* LCD_SPI prescaler: 2 */
01507   LCD_SPI->CR1 &= 0xFFC7;
01508
01509   return tmp;
01510 }
01511
01512
01513 /**
01514   * @brief  Prepare to write to the LCD RAM.
01515   * @param  None
01516   * @retval None
01517   */
01518 void LCD_WriteRAM_Prepare(void)
01519 {
01520   LCD_WriteRegIndex(LCD_REG_34); /* Select GRAM Reg */
01521
01522   /* Reset LCD control line(/CS) and Send Start-Byte */
01523   LCD_nCS_StartByte(START_BYTE | LCD_WRITE_REG);
01524 }
01525
01526
01527 /**
01528   * @brief  Writes 1 word to the LCD RAM.
01529   * @param  RGB_Code: the pixel color in RGB mode (5-6-5).
01530   * @retval None
01531   */
01532 void LCD_WriteRAMWord(uint16_t RGB_Code)
01533 {
01534
01535   LCD_WriteRAM_Prepare();
01536
01537   LCD_WriteRAM(RGB_Code);
01538
01539   LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
01540 }
01541
01542
01543 /**
01544   * @brief  Writes to the selected LCD HX8312 register.
01545   * @param  LCD_Reg: address of the selected register.
01546   * @param  LCD_RegValue: value to write to the selected register.
01547   * @retval None
01548   */
01549 static void LCD_WriteRegHX8312(uint8_t LCD_Reg, uint8_t LCD_RegValue)
01550 {
01551   uint16_t tmp = 0;
01552
01553   LCD_CtrlLinesWrite(LCD_NWR_GPIO_PORT, LCD_NWR_PIN, Bit_RESET);
01554   LCD_CtrlLinesWrite(LCD_RS_GPIO_PORT, LCD_RS_PIN, Bit_RESET);
01555   LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_RESET);
01556
01557   tmp = LCD_Reg << 8;
01558   tmp |= LCD_RegValue;
01559
01560   SPI_I2S_SendData(LCD_SPI, tmp);
01561
01562   while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
01563   {
01564   }
01565
01566   LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
01567 }
01568
01569
01570 /**
01571   * @brief  Writes to the selected LCD register.
01572   * @param  LCD_Reg: address of the selected register.
01573   * @param  LCD_RegValue: value to write to the selected register.
01574   * @retval None
01575   */
01576 void LCD_WriteReg(uint8_t LCD_Reg, uint16_t LCD_RegValue)
01577 {
01578   if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
01579   {
01580     LCD_WriteRegILI9320(LCD_Reg, LCD_RegValue);
01581   }
01582   else if(LCDType == LCD_HX8312)
01583   {
01584     LCD_WriteRegHX8312(LCD_Reg, ((uint8_t)LCD_RegValue));
01585   }
01586 }
01587
01588
01589 /**
01590   * @brief  Writes to the LCD RAM.
01591   * @param  RGB_Code: the pixel color in RGB mode (5-6-5).
01592   * @retval None
01593   */
01594 void LCD_WriteRAM(uint16_t RGB_Code)
01595 {
01596   if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
01597   {
01598     SPI_I2S_SendData(LCD_SPI, RGB_Code >> 8);
01599     while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
01600     {
01601     }
01602     SPI_I2S_SendData(LCD_SPI, RGB_Code & 0xFF);
01603     while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
01604     {
01605     }
01606   }
01607
01608   if(LCDType == LCD_HX8312)
01609   {
01610     LCD_CtrlLinesWrite(LCD_NWR_GPIO_PORT, LCD_NWR_PIN, Bit_RESET);
01611     LCD_CtrlLinesWrite(LCD_RS_GPIO_PORT, LCD_RS_PIN, Bit_SET);
01612     LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_RESET);
01613     SPI_I2S_SendData(LCD_SPI, RGB_Code);
01614
01615     while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
01616     {
01617     }
01618
01619     LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
01620   }
01621 }
01622
01623
01624 /**
01625   * @brief  Power on the LCD.
01626   * @param  None
01627   * @retval None
01628   */
01629 void LCD_PowerOn(void)
01630 {
01631   if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
01632   {
01633     /* Power On sequence ---------------------------------------------------------*/
01634     LCD_WriteReg(LCD_REG_16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
01635     LCD_WriteReg(LCD_REG_17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */
01636     LCD_WriteReg(LCD_REG_18, 0x0000); /* VREG1OUT voltage */
01637     LCD_WriteReg(LCD_REG_19, 0x0000); /* VDV[4:0] for VCOM amplitude */
01638     _delay_(20);               /* Dis-charge capacitor power voltage (200ms) */
01639     LCD_WriteReg(LCD_REG_16, 0x17B0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
01640     LCD_WriteReg(LCD_REG_17, 0x0137); /* DC1[2:0], DC0[2:0], VC[2:0] */
01641     _delay_(5);                /* Delay 50 ms */
01642     LCD_WriteReg(LCD_REG_18, 0x0139); /* VREG1OUT voltage */
01643     _delay_(5);                /* delay 50 ms */
01644     LCD_WriteReg(LCD_REG_19, 0x1d00); /* VDV[4:0] for VCOM amplitude */
01645     LCD_WriteReg(LCD_REG_41, 0x0013); /* VCM[4:0] for VCOMH */
01646     _delay_(5);                /* delay 50 ms */
01647     LCD_WriteReg(LCD_REG_7, 0x0173);  /* 262K color and display ON */
01648   }
01649   else if(LCDType == LCD_HX8312)
01650   {
01651     /* Power On Set */
01652     LCD_WriteReg(LCD_REG_28, 0x73);
01653     LCD_WriteReg(LCD_REG_36, 0x74);
01654     LCD_WriteReg(LCD_REG_30, 0x01);
01655     LCD_WriteReg(LCD_REG_24, 0xC1);
01656     _delay_(1); /* Delay 10 ms */
01657     LCD_WriteReg(LCD_REG_24, 0xE1);
01658     LCD_WriteReg(LCD_REG_24, 0xF1);
01659     _delay_(6); /* Delay 60 ms */
01660     LCD_WriteReg(LCD_REG_24, 0xF5);
01661     _delay_(6); /* Delay 60 ms */
01662     LCD_WriteReg(LCD_REG_27, 0x09);
01663     _delay_(1); /* Delay 10 ms */
01664     LCD_WriteReg(LCD_REG_31, 0x11);
01665     LCD_WriteReg(LCD_REG_32, 0x0E);
01666     LCD_WriteReg(LCD_REG_30, 0x81);
01667     _delay_(1); /* Delay 10 ms */
01668   }
01669 }
01670
01671
01672 /**
01673   * @brief  Enables the Display.
01674   * @param  None
01675   * @retval None
01676   */
01677 void LCD_DisplayOn(void)
01678 {
01679   if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
01680   {
01681     /* Display On */
01682     LCD_WriteReg(LCD_REG_7, 0x0173); /* 262K color and display ON */
01683   }
01684   else if(LCDType == LCD_HX8312)
01685   {
01686     LCD_WriteReg(LCD_REG_1, 0x50);
01687     LCD_WriteReg(LCD_REG_5, 0x04);
01688     /* Display On */
01689     LCD_WriteReg(LCD_REG_0, 0x80);
01690     LCD_WriteReg(LCD_REG_59, 0x01);
01691     _delay_(4); /* Delay 40 ms */
01692     LCD_WriteReg(LCD_REG_0, 0x20);
01693   }
01694 }
01695
01696
01697 /**
01698   * @brief  Disables the Display.
01699   * @param  None
01700   * @retval None
01701   */
01702 void LCD_DisplayOff(void)
01703 {
01704   if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
01705   {
01706     /* Display Off */
01707     LCD_WriteReg(LCD_REG_7, 0x0);
01708   }
01709   else if(LCDType == LCD_HX8312)
01710   {
01711     /* Display Off */
01712     LCD_WriteReg(LCD_REG_0, 0xA0);
01713     _delay_(4);  /* Delay 40 ms */
01714     LCD_WriteReg(LCD_REG_59, 0x00);
01715   }
01716 }
01717
01718
01719 /**
01720   * @brief  Configures LCD control lines in Output Push-Pull mode.
01721   * @param  None
01722   * @retval None
01723   */
01724 void LCD_CtrlLinesConfig(void)
01725 {
01726   GPIO_InitTypeDef GPIO_InitStructure;
01727
01728   /* Enable GPIO clock */
01729   RCC_APB2PeriphClockCmd(LCD_NCS_GPIO_CLK | LCD_NWR_GPIO_CLK | LCD_RS_GPIO_CLK, ENABLE);
01730
01731   /* Configure NCS in Output Push-Pull mode */
01732   GPIO_InitStructure.GPIO_Pin = LCD_NCS_PIN;
01733   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
01734   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
01735   GPIO_Init(LCD_NCS_GPIO_PORT, &GPIO_InitStructure);
01736
01737   /* Configure NWR(RNW), RS in Output Push-Pull mode */
01738   GPIO_InitStructure.GPIO_Pin = LCD_RS_PIN;
01739   GPIO_Init(LCD_RS_GPIO_PORT, &GPIO_InitStructure);
01740
01741   GPIO_InitStructure.GPIO_Pin = LCD_NWR_PIN;
01742   GPIO_Init(LCD_NWR_GPIO_PORT, &GPIO_InitStructure);
01743
01744   LCD_CtrlLinesWrite(LCD_NWR_GPIO_PORT, LCD_NWR_PIN, Bit_SET);
01745   LCD_CtrlLinesWrite(LCD_RS_GPIO_PORT, LCD_RS_PIN, Bit_SET);
01746 }
01747
01748
01749 /**
01750   * @brief  Sets or reset LCD control lines.
01751   * @param  GPIOx: where x can be B or D to select the GPIO peripheral.
01752   * @param  CtrlPins: the Control line.
01753   *   This parameter can be:
01754   *     @arg LCD_NCS_PIN: Chip Select pin
01755   *     @arg LCD_NWR_PIN: Read/Write Selection pin
01756   *     @arg LCD_RS_PIN: Register/RAM Selection pin
01757   * @param  BitVal: specifies the value to be written to the selected bit.
01758   *   This parameter can be:
01759   *     @arg Bit_RESET: to clear the port pin
01760   *     @arg Bit_SET: to set the port pin
01761   * @retval None
01762   */
01763 void LCD_CtrlLinesWrite(GPIO_TypeDef* GPIOx, uint16_t CtrlPins, BitAction BitVal)
01764 {
01765   /* Set or Reset the control line */
01766   GPIO_WriteBit(GPIOx, CtrlPins, BitVal);
01767 }
01768
01769
01770 /**
01771   * @brief  Configures the LCD_SPI interface.
01772   * @param  None
01773   * @retval None
01774   */
01775 void LCD_SPIConfig(void)
01776 {
01777   SPI_InitTypeDef    SPI_InitStructure;
01778   GPIO_InitTypeDef   GPIO_InitStructure;
01779
01780   /* Enable GPIO clock */
01781   RCC_APB2PeriphClockCmd(LCD_SPI_SCK_GPIO_CLK | LCD_SPI_MISO_GPIO_CLK | LCD_SPI_MOSI_GPIO_CLK, ENABLE);
01782
01783   /* Enable SPI clock  */
01784   RCC_APB1PeriphClockCmd(LCD_SPI_CLK, ENABLE);
01785
01786   /* Configure SPI pins: SCK, MISO and MOSI */
01787   GPIO_InitStructure.GPIO_Pin = LCD_SPI_SCK_PIN;
01788   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
01789   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
01790   GPIO_Init(LCD_SPI_SCK_GPIO_PORT, &GPIO_InitStructure);
01791
01792   GPIO_InitStructure.GPIO_Pin = LCD_SPI_MISO_PIN;
01793   GPIO_Init(LCD_SPI_MISO_GPIO_PORT, &GPIO_InitStructure);
01794
01795   GPIO_InitStructure.GPIO_Pin = LCD_SPI_MOSI_PIN;
01796   GPIO_Init(LCD_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure);
01797
01798   SPI_I2S_DeInit(LCD_SPI);
01799
01800   /* SPI Config */
01801   SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
01802   SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
01803
01804   if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
01805   {
01806     SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
01807     SPI_InitStructure.SPI_CPOL = SPI_CPOL_High;
01808     SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge;
01809   }
01810   else if(LCDType == LCD_HX8312)
01811   {
01812     SPI_InitStructure.SPI_DataSize = SPI_DataSize_16b;
01813     SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low;
01814     SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge;
01815   }
01816   SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
01817   SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
01818   SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
01819
01820   SPI_Init(LCD_SPI, &SPI_InitStructure);
01821
01822   /* SPI enable */
01823   SPI_Cmd(LCD_SPI, ENABLE);
01824 }
01825
01826 /**
01827   * @brief  Displays a pixel.
01828   * @param  x: pixel x.
01829   * @param  y: pixel y.
01830   * @retval None
01831   */
01832 static void PutPixel(int16_t x, int16_t y)
01833 {
01834   if(x < 0 || x > 239 || y < 0 || y > 319)
01835   {
01836     return;
01837   }
01838   LCD_DrawLine(x, y, 1, LCD_DIR_HORIZONTAL);
01839 }
01840
01841 #ifndef USE_Delay
01842 /**
01843   * @brief  Inserts a delay time.
01844   * @param  nCount: specifies the delay time length.
01845   * @retval None
01846   */
01847 static void delay(vu32 nCount)
01848 {
01849   vu32 index = 0;
01850   for(index = (34000 * nCount); index != 0; index--)
01851   {
01852   }
01853 }
01854 #endif /* USE_Delay*/
01855 /**
01856   * @}
01857   */
01858
01859 /**
01860   * @}
01861   */
01862
01863 /**
01864   * @}
01865   */
01866
01867 /**
01868   * @}
01869   */
01870
01871 /**
01872   * @}
01873   */
01874
01875 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32100b_eval_lcd.h Source File

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  • STM32100B_EVAL

stm32100b_eval_lcd.h

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32100b_eval_lcd.h
00004   * @author  MCD Application Team
00005   * @version V4.5.0
00006   * @date    07-March-2011
00007   * @brief   This file contains all the functions prototypes for the stm32100b_eval_lcd
00008   *          firmware driver.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00013   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00014   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00015   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00016   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00017   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00018   *
00019   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00020   ******************************************************************************
00021   */
00022
00023 /* Define to prevent recursive inclusion -------------------------------------*/
00024 #ifndef __STM32100B_EVAL_LCD_H
00025 #define __STM32100B_EVAL_LCD_H
00026
00027 #ifdef __cplusplus
00028  extern "C" {
00029 #endif
00030
00031 /* Includes ------------------------------------------------------------------*/
00032 #include "stm32f10x.h"
00033 #include "../Common/fonts.h"
00034
00035 /** @addtogroup Utilities
00036   * @{
00037   */
00038
00039 /** @addtogroup STM32_EVAL
00040   * @{
00041   */
00042
00043 /** @addtogroup STM32100B_EVAL
00044   * @{
00045   */
00046
00047 /** @addtogroup STM32100B_EVAL_LCD
00048   * @{
00049   */
00050
00051
00052 /** @defgroup STM32100B_EVAL_LCD_Exported_Types
00053   * @{
00054   */
00055 typedef struct
00056 {
00057   int16_t X;
00058   int16_t Y;
00059 } Point, * pPoint;
00060 /**
00061   * @}
00062   */
00063
00064 /** @defgroup STM32100B_EVAL_LCD_Exported_Constants
00065   * @{
00066   */
00067
00068 /**
00069  * @brief Uncomment the line below if you want to use LCD_DrawBMP function to
00070  *        display a bitmap picture on the LCD. This function assumes that the bitmap
00071  *        file is loaded in the SPI Flash (mounted on STM32100B-EVAL board), however
00072  *        user can tailor it according to his application hardware requirement.
00073  */
00074 /*#define USE_LCD_DrawBMP*/
00075
00076 /**
00077  * @brief Uncomment the line below if you want to use user defined Delay function
00078  *        (for precise timing), otherwise default _delay_ function defined within
00079  *         this driver is used (less precise timing).
00080  */
00081 /* #define USE_Delay */
00082
00083 #ifdef USE_Delay
00084 #include "main.h"
00085
00086   #define _delay_     Delay  /* !< User can provide more timing precise _delay_ function
00087                                    (with 10ms time base), using SysTick for example */
00088 #else
00089   #define _delay_     delay      /* !< Default _delay_ function with less precise timing */
00090 #endif
00091
00092
00093 /**
00094   * @brief  LCD Control pins
00095   */
00096 #define LCD_NCS_PIN             GPIO_Pin_2
00097 #define LCD_NCS_GPIO_PORT       GPIOB
00098 #define LCD_NCS_GPIO_CLK        RCC_APB2Periph_GPIOB
00099 #define LCD_NWR_PIN             GPIO_Pin_15
00100 #define LCD_NWR_GPIO_PORT       GPIOD
00101 #define LCD_NWR_GPIO_CLK        RCC_APB2Periph_GPIOD
00102 #define LCD_RS_PIN              GPIO_Pin_7
00103 #define LCD_RS_GPIO_PORT        GPIOD
00104 #define LCD_RS_GPIO_CLK         RCC_APB2Periph_GPIOD
00105
00106 /**
00107   * @brief  LCD SPI Interface pins
00108   */
00109 #define LCD_SPI                             SPI2
00110 #define LCD_SPI_CLK                       RCC_APB1Periph_SPI2
00111 #define LCD_SPI_SCK_PIN         GPIO_Pin_13
00112 #define LCD_SPI_SCK_GPIO_PORT   GPIOB
00113 #define LCD_SPI_SCK_GPIO_CLK    RCC_APB2Periph_GPIOB
00114 #define LCD_SPI_MISO_PIN        GPIO_Pin_14
00115 #define LCD_SPI_MISO_GPIO_PORT  GPIOB
00116 #define LCD_SPI_MISO_GPIO_CLK   RCC_APB2Periph_GPIOB
00117 #define LCD_SPI_MOSI_PIN        GPIO_Pin_15
00118 #define LCD_SPI_MOSI_GPIO_PORT  GPIOB
00119 #define LCD_SPI_MOSI_GPIO_CLK   RCC_APB2Periph_GPIOB
00120
00121
00122 /**
00123   * @brief  LCD Registers
00124   */
00125 #define LCD_REG_0             0x00
00126 #define LCD_REG_1             0x01
00127 #define LCD_REG_2             0x02
00128 #define LCD_REG_3             0x03
00129 #define LCD_REG_4             0x04
00130 #define LCD_REG_5             0x05
00131 #define LCD_REG_6             0x06
00132 #define LCD_REG_7             0x07
00133 #define LCD_REG_8             0x08
00134 #define LCD_REG_9             0x09
00135 #define LCD_REG_10            0x0A
00136 #define LCD_REG_12            0x0C
00137 #define LCD_REG_13            0x0D
00138 #define LCD_REG_14            0x0E
00139 #define LCD_REG_15            0x0F
00140 #define LCD_REG_16            0x10
00141 #define LCD_REG_17            0x11
00142 #define LCD_REG_18            0x12
00143 #define LCD_REG_19            0x13
00144 #define LCD_REG_20            0x14
00145 #define LCD_REG_21            0x15
00146 #define LCD_REG_22            0x16
00147 #define LCD_REG_23            0x17
00148 #define LCD_REG_24            0x18
00149 #define LCD_REG_25            0x19
00150 #define LCD_REG_26            0x1A
00151 #define LCD_REG_27            0x1B
00152 #define LCD_REG_28            0x1C
00153 #define LCD_REG_29            0x1D
00154 #define LCD_REG_30            0x1E
00155 #define LCD_REG_31            0x1F
00156 #define LCD_REG_32            0x20
00157 #define LCD_REG_33            0x21
00158 #define LCD_REG_34            0x22
00159 #define LCD_REG_36            0x24
00160 #define LCD_REG_37            0x25
00161 #define LCD_REG_40            0x28
00162 #define LCD_REG_41            0x29
00163 #define LCD_REG_43            0x2B
00164 #define LCD_REG_45            0x2D
00165 #define LCD_REG_48            0x30
00166 #define LCD_REG_49            0x31
00167 #define LCD_REG_50            0x32
00168 #define LCD_REG_51            0x33
00169 #define LCD_REG_52            0x34
00170 #define LCD_REG_53            0x35
00171 #define LCD_REG_54            0x36
00172 #define LCD_REG_55            0x37
00173 #define LCD_REG_56            0x38
00174 #define LCD_REG_57            0x39
00175 #define LCD_REG_59            0x3B
00176 #define LCD_REG_60            0x3C
00177 #define LCD_REG_61            0x3D
00178 #define LCD_REG_62            0x3E
00179 #define LCD_REG_63            0x3F
00180 #define LCD_REG_64            0x40
00181 #define LCD_REG_65            0x41
00182 #define LCD_REG_66            0x42
00183 #define LCD_REG_67            0x43
00184 #define LCD_REG_68            0x44
00185 #define LCD_REG_69            0x45
00186 #define LCD_REG_70            0x46
00187 #define LCD_REG_71            0x47
00188 #define LCD_REG_72            0x48
00189 #define LCD_REG_73            0x49
00190 #define LCD_REG_74            0x4A
00191 #define LCD_REG_75            0x4B
00192 #define LCD_REG_76            0x4C
00193 #define LCD_REG_77            0x4D
00194 #define LCD_REG_78            0x4E
00195 #define LCD_REG_79            0x4F
00196 #define LCD_REG_80            0x50
00197 #define LCD_REG_81            0x51
00198 #define LCD_REG_82            0x52
00199 #define LCD_REG_83            0x53
00200 #define LCD_REG_96            0x60
00201 #define LCD_REG_97            0x61
00202 #define LCD_REG_106           0x6A
00203 #define LCD_REG_118           0x76
00204 #define LCD_REG_128           0x80
00205 #define LCD_REG_129           0x81
00206 #define LCD_REG_130           0x82
00207 #define LCD_REG_131           0x83
00208 #define LCD_REG_132           0x84
00209 #define LCD_REG_133           0x85
00210 #define LCD_REG_134           0x86
00211 #define LCD_REG_135           0x87
00212 #define LCD_REG_136           0x88
00213 #define LCD_REG_137           0x89
00214 #define LCD_REG_139           0x8B
00215 #define LCD_REG_140           0x8C
00216 #define LCD_REG_141           0x8D
00217 #define LCD_REG_143           0x8F
00218 #define LCD_REG_144           0x90
00219 #define LCD_REG_145           0x91
00220 #define LCD_REG_146           0x92
00221 #define LCD_REG_147           0x93
00222 #define LCD_REG_148           0x94
00223 #define LCD_REG_149           0x95
00224 #define LCD_REG_150           0x96
00225 #define LCD_REG_151           0x97
00226 #define LCD_REG_152           0x98
00227 #define LCD_REG_153           0x99
00228 #define LCD_REG_154           0x9A
00229 #define LCD_REG_157           0x9D
00230 #define LCD_REG_192           0xC0
00231 #define LCD_REG_193           0xC1
00232 #define LCD_REG_227           0xE3
00233 #define LCD_REG_229           0xE5
00234 #define LCD_REG_231           0xE7
00235 #define LCD_REG_239           0xEF
00236
00237
00238 /**
00239   * @brief  LCD color
00240   */
00241 #define LCD_COLOR_WHITE          0xFFFF
00242 #define LCD_COLOR_BLACK          0x0000
00243 #define LCD_COLOR_GREY           0xF7DE
00244 #define LCD_COLOR_BLUE           0x001F
00245 #define LCD_COLOR_BLUE2          0x051F
00246 #define LCD_COLOR_RED            0xF800
00247 #define LCD_COLOR_MAGENTA        0xF81F
00248 #define LCD_COLOR_GREEN          0x07E0
00249 #define LCD_COLOR_CYAN           0x7FFF
00250 #define LCD_COLOR_YELLOW         0xFFE0
00251
00252 /**
00253   * @brief  LCD Lines depending on the chosen fonts.
00254   */
00255 #define LCD_LINE_0               LINE(0)
00256 #define LCD_LINE_1               LINE(1)
00257 #define LCD_LINE_2               LINE(2)
00258 #define LCD_LINE_3               LINE(3)
00259 #define LCD_LINE_4               LINE(4)
00260 #define LCD_LINE_5               LINE(5)
00261 #define LCD_LINE_6               LINE(6)
00262 #define LCD_LINE_7               LINE(7)
00263 #define LCD_LINE_8               LINE(8)
00264 #define LCD_LINE_9               LINE(9)
00265 #define LCD_LINE_10              LINE(10)
00266 #define LCD_LINE_11              LINE(11)
00267 #define LCD_LINE_12              LINE(12)
00268 #define LCD_LINE_13              LINE(13)
00269 #define LCD_LINE_14              LINE(14)
00270 #define LCD_LINE_15              LINE(15)
00271 #define LCD_LINE_16              LINE(16)
00272 #define LCD_LINE_17              LINE(17)
00273 #define LCD_LINE_18              LINE(18)
00274 #define LCD_LINE_19              LINE(19)
00275 #define LCD_LINE_20              LINE(20)
00276 #define LCD_LINE_21              LINE(21)
00277 #define LCD_LINE_22              LINE(22)
00278 #define LCD_LINE_23              LINE(23)
00279 #define LCD_LINE_24              LINE(24)
00280 #define LCD_LINE_25              LINE(25)
00281 #define LCD_LINE_26              LINE(26)
00282 #define LCD_LINE_27              LINE(27)
00283 #define LCD_LINE_28              LINE(28)
00284 #define LCD_LINE_29              LINE(29)
00285
00286
00287 /**
00288   * @brief LCD default font
00289   */
00290 #define LCD_DEFAULT_FONT         Font16x24
00291
00292 /**
00293   * @brief  LCD Direction
00294   */
00295 #define LCD_DIR_HORIZONTAL       0x0000
00296 #define LCD_DIR_VERTICAL         0x0001
00297
00298 /**
00299   * @brief  LCD Size (Width and Height)
00300   */
00301 #define LCD_PIXEL_WIDTH          0x0140
00302 #define LCD_PIXEL_HEIGHT         0x00F0
00303
00304 /**
00305   * @}
00306   */
00307
00308 /** @defgroup STM32100B_EVAL_LCD_Exported_Macros
00309   * @{
00310   */
00311 #define ASSEMBLE_RGB(R, G, B)    ((((R)& 0xF8) << 8) | (((G) & 0xFC) << 3) | (((B) & 0xF8) >> 3))
00312
00313 /**
00314   * @}
00315   */
00316
00317 /** @defgroup STM32100B_EVAL_LCD_Exported_Functions
00318   * @{
00319   */
00320 void LCD_DeInit(void);
00321 void LCD_Setup(void);
00322 void STM32100B_LCD_Init(void);
00323 void LCD_SetColors(__IO uint16_t _TextColor, __IO uint16_t _BackColor);
00324 void LCD_GetColors(__IO uint16_t *_TextColor, __IO uint16_t *_BackColor);
00325 void LCD_SetTextColor(__IO uint16_t Color);
00326 void LCD_SetBackColor(__IO uint16_t Color);
00327 void LCD_ClearLine(uint8_t Line);
00328 void LCD_Clear(uint16_t Color);
00329 void LCD_SetCursor(uint8_t Xpos, uint16_t Ypos);
00330 void LCD_DrawChar(uint8_t Xpos, uint16_t Ypos, const uint16_t *c);
00331 void LCD_DisplayChar(uint8_t Line, uint16_t Column, uint8_t Ascii);
00332 void LCD_SetFont(sFONT *fonts);
00333 sFONT *LCD_GetFont(void);
00334 void LCD_DisplayStringLine(uint8_t Line, uint8_t *ptr);
00335 void LCD_SetDisplayWindow(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width);
00336 void LCD_WindowModeDisable(void);
00337 void LCD_DrawLine(uint8_t Xpos, uint16_t Ypos, uint16_t Length, uint8_t Direction);
00338 void LCD_DrawRect(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width);
00339 void LCD_DrawCircle(uint8_t Xpos, uint16_t Ypos, uint16_t Radius);
00340 void LCD_DrawMonoPict(const uint32_t *Pict);
00341 void LCD_DrawBMP(uint32_t BmpAddress);
00342 void LCD_DrawUniLine(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2);
00343 void LCD_DrawFullRect(uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height);
00344 void LCD_DrawFullCircle(uint16_t Xpos, uint16_t Ypos, uint16_t Radius);
00345 void LCD_PolyLine(pPoint Points, uint16_t PointCount);
00346 void LCD_PolyLineRelative(pPoint Points, uint16_t PointCount);
00347 void LCD_ClosedPolyLine(pPoint Points, uint16_t PointCount);
00348 void LCD_ClosedPolyLineRelative(pPoint Points, uint16_t PointCount);
00349 void LCD_FillPolyLine(pPoint Points, uint16_t PointCount);
00350 void LCD_nCS_StartByte(uint8_t Start_Byte);
00351 void LCD_WriteRegIndex(uint8_t LCD_Reg);
00352 void LCD_WriteReg(uint8_t LCD_Reg, uint16_t LCD_RegValue);
00353 void LCD_WriteRAM_Prepare(void);
00354 void LCD_WriteRAMWord(uint16_t RGB_Code);
00355 uint16_t LCD_ReadReg(uint8_t LCD_Reg);
00356 void LCD_WriteRAM(uint16_t RGB_Code);
00357 void LCD_PowerOn(void);
00358 void LCD_DisplayOn(void);
00359 void LCD_DisplayOff(void);
00360
00361
00362 void LCD_CtrlLinesConfig(void);
00363 void LCD_CtrlLinesWrite(GPIO_TypeDef* GPIOx, uint16_t CtrlPins, BitAction BitVal);
00364 void LCD_SPIConfig(void);
00365
00366 /**
00367   * @}
00368   */
00369
00370 #ifdef __cplusplus
00371 }
00372 #endif
00373
00374 #endif /* __STM32100B_EVAL_LCD_H */
00375
00376
00377 /**
00378   * @}
00379   */
00380
00381 /**
00382   * @}
00383   */
00384
00385 /**
00386   * @}
00387   */
00388
00389 /**
00390   * @}
00391   */
00392
00393 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32100e_eval.c Source File

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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
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  • STM32100E_EVAL

stm32100e_eval.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32100e_eval.c
00004   * @author  MCD Application Team
00005   * @version V4.5.0
00006   * @date    07-March-2011
00007   * @brief   This file provides
00008   *            - set of firmware functions to manage Leds, push-button and COM ports
00009   *            - low level initialization functions for SD card (on SDIO), SPI serial
00010   *              flash (sFLASH) and temperature sensor (LM75)
00011   *          available on STM32100E-EVAL evaluation board from STMicroelectronics.
00012   ******************************************************************************
00013   * @attention
00014   *
00015   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00016   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00017   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00018   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00019   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00020   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00021   *
00022   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00023   ******************************************************************************
00024   */
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32100e_eval.h"
00028 #include "stm32f10x_spi.h"
00029 #include "stm32f10x_i2c.h"
00030 #include "stm32f10x_dma.h"
00031
00032 /** @addtogroup Utilities
00033   * @{
00034   */
00035
00036 /** @addtogroup STM32_EVAL
00037   * @{
00038   */
00039
00040 /** @addtogroup STM32100E_EVAL
00041   * @{
00042   */
00043
00044 /** @defgroup STM32100E_EVAL_LOW_LEVEL
00045   * @brief This file provides firmware functions to manage Leds, push-buttons,
00046   *        COM ports, SD card on SDIO, serial flash (sFLASH), serial EEPROM (sEE)
00047   *        and temperature sensor (LM75) available on STM32100E-EVAL evaluation
00048   *        board from STMicroelectronics.
00049   * @{
00050   */
00051
00052 /** @defgroup STM32100E_EVAL_LOW_LEVEL_Private_TypesDefinitions
00053   * @{
00054   */
00055 /**
00056   * @}
00057   */
00058
00059
00060 /** @defgroup STM32100E_EVAL_LOW_LEVEL_Private_Defines
00061   * @{
00062   */
00063 /**
00064   * @}
00065   */
00066
00067
00068 /** @defgroup STM32100E_EVAL_LOW_LEVEL_Private_Macros
00069   * @{
00070   */
00071 /**
00072   * @}
00073   */
00074
00075
00076 /** @defgroup STM32100E_EVAL_LOW_LEVEL_Private_Variables
00077   * @{
00078   */
00079 GPIO_TypeDef* GPIO_PORT[LEDn] = {LED1_GPIO_PORT, LED2_GPIO_PORT, LED3_GPIO_PORT,
00080                                  LED4_GPIO_PORT};
00081 const uint16_t GPIO_PIN[LEDn] = {LED1_PIN, LED2_PIN, LED3_PIN,
00082                                  LED4_PIN};
00083 const uint32_t GPIO_CLK[LEDn] = {LED1_GPIO_CLK, LED2_GPIO_CLK, LED3_GPIO_CLK,
00084                                  LED4_GPIO_CLK};
00085
00086 GPIO_TypeDef* BUTTON_PORT[BUTTONn] = {WAKEUP_BUTTON_GPIO_PORT, TAMPER_BUTTON_GPIO_PORT,
00087                                       KEY_BUTTON_GPIO_PORT, RIGHT_BUTTON_GPIO_PORT,
00088                                       LEFT_BUTTON_GPIO_PORT, UP_BUTTON_GPIO_PORT,
00089                                       DOWN_BUTTON_GPIO_PORT, SEL_BUTTON_GPIO_PORT};
00090
00091 const uint16_t BUTTON_PIN[BUTTONn] = {WAKEUP_BUTTON_PIN, TAMPER_BUTTON_PIN,
00092                                       KEY_BUTTON_PIN, RIGHT_BUTTON_PIN,
00093                                       LEFT_BUTTON_PIN, UP_BUTTON_PIN,
00094                                       DOWN_BUTTON_PIN, SEL_BUTTON_PIN};
00095
00096 const uint32_t BUTTON_CLK[BUTTONn] = {WAKEUP_BUTTON_GPIO_CLK, TAMPER_BUTTON_GPIO_CLK,
00097                                       KEY_BUTTON_GPIO_CLK, RIGHT_BUTTON_GPIO_CLK,
00098                                       LEFT_BUTTON_GPIO_CLK, UP_BUTTON_GPIO_CLK,
00099                                       DOWN_BUTTON_GPIO_CLK, SEL_BUTTON_GPIO_CLK};
00100
00101 const uint16_t BUTTON_EXTI_LINE[BUTTONn] = {WAKEUP_BUTTON_EXTI_LINE,
00102                                             TAMPER_BUTTON_EXTI_LINE,
00103                                             KEY_BUTTON_EXTI_LINE,
00104                                             RIGHT_BUTTON_EXTI_LINE,
00105                                             LEFT_BUTTON_EXTI_LINE,
00106                                             UP_BUTTON_EXTI_LINE,
00107                                             DOWN_BUTTON_EXTI_LINE,
00108                                             SEL_BUTTON_EXTI_LINE};
00109
00110 const uint16_t BUTTON_PORT_SOURCE[BUTTONn] = {WAKEUP_BUTTON_EXTI_PORT_SOURCE,
00111                                               TAMPER_BUTTON_EXTI_PORT_SOURCE,
00112                                               KEY_BUTTON_EXTI_PORT_SOURCE,
00113                                               RIGHT_BUTTON_EXTI_PORT_SOURCE,
00114                                               LEFT_BUTTON_EXTI_PORT_SOURCE,
00115                                               UP_BUTTON_EXTI_PORT_SOURCE,
00116                                               DOWN_BUTTON_EXTI_PORT_SOURCE,
00117                                               SEL_BUTTON_EXTI_PORT_SOURCE};
00118
00119 const uint16_t BUTTON_PIN_SOURCE[BUTTONn] = {WAKEUP_BUTTON_EXTI_PIN_SOURCE,
00120                                              TAMPER_BUTTON_EXTI_PIN_SOURCE,
00121                                              KEY_BUTTON_EXTI_PIN_SOURCE,
00122                                              RIGHT_BUTTON_EXTI_PIN_SOURCE,
00123                                              LEFT_BUTTON_EXTI_PIN_SOURCE,
00124                                              UP_BUTTON_EXTI_PIN_SOURCE,
00125                                              DOWN_BUTTON_EXTI_PIN_SOURCE,
00126                                              SEL_BUTTON_EXTI_PIN_SOURCE};
00127
00128 const uint16_t BUTTON_IRQn[BUTTONn] = {WAKEUP_BUTTON_EXTI_IRQn, TAMPER_BUTTON_EXTI_IRQn,
00129                                        KEY_BUTTON_EXTI_IRQn, RIGHT_BUTTON_EXTI_IRQn,
00130                                        LEFT_BUTTON_EXTI_IRQn, UP_BUTTON_EXTI_IRQn,
00131                                        DOWN_BUTTON_EXTI_IRQn, SEL_BUTTON_EXTI_IRQn};
00132
00133 USART_TypeDef* COM_USART[COMn] = {EVAL_COM1, EVAL_COM2};
00134
00135 GPIO_TypeDef* COM_TX_PORT[COMn] = {EVAL_COM1_TX_GPIO_PORT, EVAL_COM2_TX_GPIO_PORT};
00136
00137 GPIO_TypeDef* COM_RX_PORT[COMn] = {EVAL_COM1_RX_GPIO_PORT, EVAL_COM2_RX_GPIO_PORT};
00138
00139 const uint32_t COM_USART_CLK[COMn] = {EVAL_COM1_CLK, EVAL_COM2_CLK};
00140
00141 const uint32_t COM_TX_PORT_CLK[COMn] = {EVAL_COM1_TX_GPIO_CLK, EVAL_COM2_TX_GPIO_CLK};
00142
00143 const uint32_t COM_RX_PORT_CLK[COMn] = {EVAL_COM1_RX_GPIO_CLK, EVAL_COM2_RX_GPIO_CLK};
00144
00145 const uint16_t COM_TX_PIN[COMn] = {EVAL_COM1_TX_PIN, EVAL_COM2_TX_PIN};
00146
00147 const uint16_t COM_RX_PIN[COMn] = {EVAL_COM1_RX_PIN, EVAL_COM2_RX_PIN};
00148
00149 DMA_InitTypeDef   sEEDMA_InitStructure;
00150
00151 /**
00152   * @}
00153   */
00154
00155
00156 /** @defgroup STM32100E_EVAL_LOW_LEVEL_Private_FunctionPrototypes
00157   * @{
00158   */
00159
00160 /**
00161   * @}
00162   */
00163
00164
00165 /** @defgroup STM32100E_EVAL_LOW_LEVEL_Private_Functions
00166   * @{
00167   */
00168
00169 /**
00170   * @brief  Configures LED GPIO.
00171   * @param  Led: Specifies the Led to be configured.
00172   *   This parameter can be one of following parameters:
00173   *     @arg LED1
00174   *     @arg LED2
00175   *     @arg LED3
00176   *     @arg LED4
00177   * @retval None
00178   */
00179 void STM_EVAL_LEDInit(Led_TypeDef Led)
00180 {
00181   GPIO_InitTypeDef  GPIO_InitStructure;
00182
00183   /* Enable the GPIO_LED Clock */
00184   RCC_APB2PeriphClockCmd(GPIO_CLK[Led], ENABLE);
00185
00186   /* Configure the GPIO_LED pin */
00187   GPIO_InitStructure.GPIO_Pin = GPIO_PIN[Led];
00188   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
00189   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00190
00191   GPIO_Init(GPIO_PORT[Led], &GPIO_InitStructure);
00192 }
00193
00194 /**
00195   * @brief  Turns selected LED On.
00196   * @param  Led: Specifies the Led to be set on.
00197   *   This parameter can be one of following parameters:
00198   *     @arg LED1
00199   *     @arg LED2
00200   *     @arg LED3
00201   *     @arg LED4
00202   * @retval None
00203   */
00204 void STM_EVAL_LEDOn(Led_TypeDef Led)
00205 {
00206   GPIO_PORT[Led]->BSRR = GPIO_PIN[Led];
00207 }
00208
00209 /**
00210   * @brief  Turns selected LED Off.
00211   * @param  Led: Specifies the Led to be set off.
00212   *   This parameter can be one of following parameters:
00213   *     @arg LED1
00214   *     @arg LED2
00215   *     @arg LED3
00216   *     @arg LED4
00217   * @retval None
00218   */
00219 void STM_EVAL_LEDOff(Led_TypeDef Led)
00220 {
00221   GPIO_PORT[Led]->BRR = GPIO_PIN[Led];
00222 }
00223
00224 /**
00225   * @brief  Toggles the selected LED.
00226   * @param  Led: Specifies the Led to be toggled.
00227   *   This parameter can be one of following parameters:
00228   *     @arg LED1
00229   *     @arg LED2
00230   *     @arg LED3
00231   *     @arg LED4
00232   * @retval None
00233   */
00234 void STM_EVAL_LEDToggle(Led_TypeDef Led)
00235 {
00236   GPIO_PORT[Led]->ODR ^= GPIO_PIN[Led];
00237 }
00238
00239 /**
00240   * @brief  Configures Button GPIO and EXTI Line.
00241   * @param  Button: Specifies the Button to be configured.
00242   *   This parameter can be one of following parameters:
00243   *     @arg BUTTON_WAKEUP: Wakeup Push Button
00244   *     @arg BUTTON_TAMPER: Tamper Push Button
00245   *     @arg BUTTON_KEY: Key Push Button
00246   *     @arg BUTTON_RIGHT: Joystick Right Push Button
00247   *     @arg BUTTON_LEFT: Joystick Left Push Button
00248   *     @arg BUTTON_UP: Joystick Up Push Button
00249   *     @arg BUTTON_DOWN: Joystick Down Push Button
00250   *     @arg BUTTON_SEL: Joystick Sel Push Button
00251   * @param  Button_Mode: Specifies Button mode.
00252   *   This parameter can be one of following parameters:
00253   *     @arg BUTTON_MODE_GPIO: Button will be used as simple IO
00254   *     @arg BUTTON_MODE_EXTI: Button will be connected to EXTI line with interrupt
00255   *                     generation capability
00256   * @retval None
00257   */
00258 void STM_EVAL_PBInit(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode)
00259 {
00260   GPIO_InitTypeDef GPIO_InitStructure;
00261   EXTI_InitTypeDef EXTI_InitStructure;
00262   NVIC_InitTypeDef NVIC_InitStructure;
00263
00264   /* Enable the BUTTON Clock */
00265   RCC_APB2PeriphClockCmd(BUTTON_CLK[Button] | RCC_APB2Periph_AFIO, ENABLE);
00266
00267   /* Configure Button pin as input floating */
00268   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
00269   GPIO_InitStructure.GPIO_Pin = BUTTON_PIN[Button];
00270   GPIO_Init(BUTTON_PORT[Button], &GPIO_InitStructure);
00271
00272
00273   if (Button_Mode == BUTTON_MODE_EXTI)
00274   {
00275     /* Connect Button EXTI Line to Button GPIO Pin */
00276     GPIO_EXTILineConfig(BUTTON_PORT_SOURCE[Button], BUTTON_PIN_SOURCE[Button]);
00277
00278     /* Configure Button EXTI line */
00279     EXTI_InitStructure.EXTI_Line = BUTTON_EXTI_LINE[Button];
00280     EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
00281
00282     if(Button != BUTTON_WAKEUP)
00283     {
00284       EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling;
00285     }
00286     else
00287     {
00288       EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;
00289     }
00290     EXTI_InitStructure.EXTI_LineCmd = ENABLE;
00291     EXTI_Init(&EXTI_InitStructure);
00292
00293     /* Enable and set Button EXTI Interrupt to the lowest priority */
00294     NVIC_InitStructure.NVIC_IRQChannel = BUTTON_IRQn[Button];
00295     NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x0F;
00296     NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x0F;
00297     NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
00298
00299     NVIC_Init(&NVIC_InitStructure);
00300   }
00301 }
00302
00303 /**
00304   * @brief  Returns the selected Button state.
00305   * @param  Button: Specifies the Button to be checked.
00306   *   This parameter can be one of following parameters:
00307   *     @arg BUTTON_WAKEUP: Wakeup Push Button
00308   *     @arg BUTTON_TAMPER: Tamper Push Button
00309   *     @arg BUTTON_KEY: Key Push Button
00310   *     @arg BUTTON_RIGHT: Joystick Right Push Button
00311   *     @arg BUTTON_LEFT: Joystick Left Push Button
00312   *     @arg BUTTON_UP: Joystick Up Push Button
00313   *     @arg BUTTON_DOWN: Joystick Down Push Button
00314   *     @arg BUTTON_SEL: Joystick Sel Push Button
00315   * @retval The Button GPIO pin value.
00316   */
00317 uint32_t STM_EVAL_PBGetState(Button_TypeDef Button)
00318 {
00319   return GPIO_ReadInputDataBit(BUTTON_PORT[Button], BUTTON_PIN[Button]);
00320 }
00321
00322 /**
00323   * @brief  Configures COM port.
00324   * @param  COM: Specifies the COM port to be configured.
00325   *   This parameter can be one of following parameters:
00326   *     @arg COM1
00327   *     @arg COM2
00328   * @param  USART_InitStruct: pointer to a USART_InitTypeDef structure that
00329   *   contains the configuration information for the specified USART peripheral.
00330   * @retval None
00331   */
00332 void STM_EVAL_COMInit(COM_TypeDef COM, USART_InitTypeDef* USART_InitStruct)
00333 {
00334   GPIO_InitTypeDef GPIO_InitStructure;
00335
00336   /* Enable GPIO clock */
00337   RCC_APB2PeriphClockCmd(COM_TX_PORT_CLK[COM] | COM_RX_PORT_CLK[COM] | RCC_APB2Periph_AFIO, ENABLE);
00338
00339   /* Enable UART clock */
00340   if (COM == COM1)
00341   {
00342     RCC_APB2PeriphClockCmd(COM_USART_CLK[COM], ENABLE);
00343   }
00344   else
00345   {
00346     RCC_APB1PeriphClockCmd(COM_USART_CLK[COM], ENABLE);
00347   }
00348
00349   /* Configure USART Tx as alternate function push-pull */
00350   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
00351   GPIO_InitStructure.GPIO_Pin = COM_TX_PIN[COM];
00352   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00353   GPIO_Init(COM_TX_PORT[COM], &GPIO_InitStructure);
00354
00355   /* Configure USART Rx as input floating */
00356   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
00357   GPIO_InitStructure.GPIO_Pin = COM_RX_PIN[COM];
00358   GPIO_Init(COM_RX_PORT[COM], &GPIO_InitStructure);
00359
00360   /* USART configuration */
00361   USART_Init(COM_USART[COM], USART_InitStruct);
00362
00363   /* Enable USART */
00364   USART_Cmd(COM_USART[COM], ENABLE);
00365 }
00366
00367 /**
00368   * @brief  DeInitializes the SD/SD communication.
00369   * @param  None
00370   * @retval None
00371   */
00372 void SD_LowLevel_DeInit(void)
00373 {
00374   GPIO_InitTypeDef  GPIO_InitStructure;
00375
00376   SPI_Cmd(SD_SPI, DISABLE); /*!< SD_SPI disable */
00377   SPI_I2S_DeInit(SD_SPI);   /*!< DeInitializes the SD_SPI */
00378
00379   /*!< SD_SPI Periph clock disable */
00380   RCC_APB1PeriphClockCmd(SD_SPI_CLK, DISABLE);
00381
00382   /*!< Configure SD_SPI pins: SCK */
00383   GPIO_InitStructure.GPIO_Pin = SD_SPI_SCK_PIN;
00384   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
00385   GPIO_Init(SD_SPI_SCK_GPIO_PORT, &GPIO_InitStructure);
00386
00387   /*!< Configure SD_SPI pins: MISO */
00388   GPIO_InitStructure.GPIO_Pin = SD_SPI_MISO_PIN;
00389   GPIO_Init(SD_SPI_MISO_GPIO_PORT, &GPIO_InitStructure);
00390
00391   /*!< Configure SD_SPI pins: MOSI */
00392   GPIO_InitStructure.GPIO_Pin = SD_SPI_MOSI_PIN;
00393   GPIO_Init(SD_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure);
00394
00395   /*!< Configure SD_SPI_CS_PIN pin: SD Card CS pin */
00396   GPIO_InitStructure.GPIO_Pin = SD_CS_PIN;
00397   GPIO_Init(SD_CS_GPIO_PORT, &GPIO_InitStructure);
00398
00399   /*!< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin */
00400   GPIO_InitStructure.GPIO_Pin = SD_DETECT_PIN;
00401   GPIO_Init(SD_DETECT_GPIO_PORT, &GPIO_InitStructure);
00402 }
00403
00404 /**
00405   * @brief  Initializes the SD_SPI and CS pins.
00406   * @param  None
00407   * @retval None
00408   */
00409 void SD_LowLevel_Init(void)
00410 {
00411   GPIO_InitTypeDef  GPIO_InitStructure;
00412   SPI_InitTypeDef   SPI_InitStructure;
00413
00414   /*!< SD_SPI_CS_GPIO, SD_SPI_MOSI_GPIO, SD_SPI_MISO_GPIO, SD_SPI_DETECT_GPIO
00415        and SD_SPI_SCK_GPIO Periph clock enable */
00416   RCC_APB2PeriphClockCmd(SD_CS_GPIO_CLK | SD_SPI_MOSI_GPIO_CLK | SD_SPI_MISO_GPIO_CLK |
00417                          SD_SPI_SCK_GPIO_CLK | SD_DETECT_GPIO_CLK, ENABLE);
00418
00419   /*!< SD_SPI Periph clock enable */
00420   RCC_APB1PeriphClockCmd(SD_SPI_CLK, ENABLE);
00421
00422   /*!< Configure SD_SPI pins: SCK */
00423   GPIO_InitStructure.GPIO_Pin = SD_SPI_SCK_PIN;
00424   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00425   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
00426   GPIO_Init(SD_SPI_SCK_GPIO_PORT, &GPIO_InitStructure);
00427
00428   /*!< Configure SD_SPI pins: MOSI */
00429   GPIO_InitStructure.GPIO_Pin = SD_SPI_MOSI_PIN;
00430   GPIO_Init(SD_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure);
00431
00432   /*!< Configure SD_SPI pins: MISO */
00433   GPIO_InitStructure.GPIO_Pin = SD_SPI_MISO_PIN;
00434   GPIO_Init(SD_SPI_MISO_GPIO_PORT, &GPIO_InitStructure);
00435
00436   /*!< Configure SD_SPI_CS_PIN pin: SD Card CS pin */
00437   GPIO_InitStructure.GPIO_Pin = SD_CS_PIN;
00438   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
00439   GPIO_Init(SD_CS_GPIO_PORT, &GPIO_InitStructure);
00440
00441   /*!< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin */
00442   GPIO_InitStructure.GPIO_Pin = SD_DETECT_PIN;
00443   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
00444   GPIO_Init(SD_DETECT_GPIO_PORT, &GPIO_InitStructure);
00445
00446   /*!< SD_SPI Config */
00447   SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
00448   SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
00449   SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
00450   SPI_InitStructure.SPI_CPOL = SPI_CPOL_High;
00451   SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge;
00452   SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
00453   SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
00454   SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
00455   SPI_InitStructure.SPI_CRCPolynomial = 7;
00456   SPI_Init(SD_SPI, &SPI_InitStructure);
00457
00458   SPI_Cmd(SD_SPI, ENABLE); /*!< SD_SPI enable */
00459 }
00460
00461 /**
00462   * @brief  DeInitializes peripherals used by the I2C EEPROM driver.
00463   * @param  None
00464   * @retval None
00465   */
00466 void sEE_LowLevel_DeInit(void)
00467 {
00468   GPIO_InitTypeDef  GPIO_InitStructure;
00469   NVIC_InitTypeDef NVIC_InitStructure;
00470
00471   /* sEE_I2C Peripheral Disable */
00472   I2C_Cmd(sEE_I2C, DISABLE);
00473
00474   /* sEE_I2C DeInit */
00475   I2C_DeInit(sEE_I2C);
00476
00477   /*!< sEE_I2C Periph clock disable */
00478   RCC_APB1PeriphClockCmd(sEE_I2C_CLK, DISABLE);
00479
00480   /*!< GPIO configuration */
00481   /*!< Configure sEE_I2C pins: SCL */
00482   GPIO_InitStructure.GPIO_Pin = sEE_I2C_SCL_PIN;
00483   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
00484   GPIO_Init(sEE_I2C_SCL_GPIO_PORT, &GPIO_InitStructure);
00485
00486   /*!< Configure sEE_I2C pins: SDA */
00487   GPIO_InitStructure.GPIO_Pin = sEE_I2C_SDA_PIN;
00488   GPIO_Init(sEE_I2C_SDA_GPIO_PORT, &GPIO_InitStructure);
00489
00490   /* Configure and enable I2C DMA TX Channel interrupt */
00491   NVIC_InitStructure.NVIC_IRQChannel = sEE_I2C_DMA_TX_IRQn;
00492   NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = sEE_I2C_DMA_PREPRIO;
00493   NVIC_InitStructure.NVIC_IRQChannelSubPriority = sEE_I2C_DMA_SUBPRIO;
00494   NVIC_InitStructure.NVIC_IRQChannelCmd = DISABLE;
00495   NVIC_Init(&NVIC_InitStructure);
00496
00497   /* Configure and enable I2C DMA RX Channel interrupt */
00498   NVIC_InitStructure.NVIC_IRQChannel = sEE_I2C_DMA_RX_IRQn;
00499   NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = sEE_I2C_DMA_PREPRIO;
00500   NVIC_InitStructure.NVIC_IRQChannelSubPriority = sEE_I2C_DMA_SUBPRIO;
00501   NVIC_Init(&NVIC_InitStructure);
00502
00503   /* Disable and Deinitialize the DMA channels */
00504   DMA_Cmd(sEE_I2C_DMA_CHANNEL_TX, DISABLE);
00505   DMA_Cmd(sEE_I2C_DMA_CHANNEL_RX, DISABLE);
00506   DMA_DeInit(sEE_I2C_DMA_CHANNEL_TX);
00507   DMA_DeInit(sEE_I2C_DMA_CHANNEL_RX);
00508 }
00509
00510 /**
00511   * @brief  Initializes peripherals used by the I2C EEPROM driver.
00512   * @param  None
00513   * @retval None
00514   */
00515 void sEE_LowLevel_Init(void)
00516 {
00517   GPIO_InitTypeDef  GPIO_InitStructure;
00518   NVIC_InitTypeDef NVIC_InitStructure;
00519
00520   /*!< sEE_I2C_SCL_GPIO_CLK and sEE_I2C_SDA_GPIO_CLK Periph clock enable */
00521   RCC_APB2PeriphClockCmd(sEE_I2C_SCL_GPIO_CLK | sEE_I2C_SDA_GPIO_CLK, ENABLE);
00522
00523   /*!< sEE_I2C Periph clock enable */
00524   RCC_APB1PeriphClockCmd(sEE_I2C_CLK, ENABLE);
00525
00526   /*!< GPIO configuration */
00527   /*!< Configure sEE_I2C pins: SCL */
00528   GPIO_InitStructure.GPIO_Pin = sEE_I2C_SCL_PIN;
00529   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00530   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_OD;
00531   GPIO_Init(sEE_I2C_SCL_GPIO_PORT, &GPIO_InitStructure);
00532
00533   /*!< Configure sEE_I2C pins: SDA */
00534   GPIO_InitStructure.GPIO_Pin = sEE_I2C_SDA_PIN;
00535   GPIO_Init(sEE_I2C_SDA_GPIO_PORT, &GPIO_InitStructure);
00536
00537   /* Configure and enable I2C DMA TX Channel interrupt */
00538   NVIC_InitStructure.NVIC_IRQChannel = sEE_I2C_DMA_TX_IRQn;
00539   NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = sEE_I2C_DMA_PREPRIO;
00540   NVIC_InitStructure.NVIC_IRQChannelSubPriority = sEE_I2C_DMA_SUBPRIO;
00541   NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
00542   NVIC_Init(&NVIC_InitStructure);
00543
00544   /* Configure and enable I2C DMA RX Channel interrupt */
00545   NVIC_InitStructure.NVIC_IRQChannel = sEE_I2C_DMA_RX_IRQn;
00546   NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = sEE_I2C_DMA_PREPRIO;
00547   NVIC_InitStructure.NVIC_IRQChannelSubPriority = sEE_I2C_DMA_SUBPRIO;
00548   NVIC_Init(&NVIC_InitStructure);
00549
00550   /*!< I2C DMA TX and RX channels configuration */
00551   /* Enable the DMA clock */
00552   RCC_AHBPeriphClockCmd(sEE_I2C_DMA_CLK, ENABLE);
00553
00554   /* I2C TX DMA Channel configuration */
00555   DMA_DeInit(sEE_I2C_DMA_CHANNEL_TX);
00556   sEEDMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)sEE_I2C_DR_Address;
00557   sEEDMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)0;   /* This parameter will be configured durig communication */
00558   sEEDMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;    /* This parameter will be configured durig communication */
00559   sEEDMA_InitStructure.DMA_BufferSize = 0xFFFF;            /* This parameter will be configured durig communication */
00560   sEEDMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
00561   sEEDMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
00562   sEEDMA_InitStructure.DMA_PeripheralDataSize = DMA_MemoryDataSize_Byte;
00563   sEEDMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
00564   sEEDMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
00565   sEEDMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh;
00566   sEEDMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
00567   DMA_Init(sEE_I2C_DMA_CHANNEL_TX, &sEEDMA_InitStructure);
00568
00569   /* I2C RX DMA Channel configuration */
00570   DMA_DeInit(sEE_I2C_DMA_CHANNEL_RX);
00571   DMA_Init(sEE_I2C_DMA_CHANNEL_RX, &sEEDMA_InitStructure);
00572
00573   /* Enable the DMA Channels Interrupts */
00574   DMA_ITConfig(sEE_I2C_DMA_CHANNEL_TX, DMA_IT_TC, ENABLE);
00575   DMA_ITConfig(sEE_I2C_DMA_CHANNEL_RX, DMA_IT_TC, ENABLE);
00576 }
00577
00578 /**
00579   * @brief  Initializes DMA channel used by the I2C EEPROM driver.
00580   * @param  None
00581   * @retval None
00582   */
00583 void sEE_LowLevel_DMAConfig(uint32_t pBuffer, uint32_t BufferSize, uint32_t Direction)
00584 {
00585   /* Initialize the DMA with the new parameters */
00586   if (Direction == sEE_DIRECTION_TX)
00587   {
00588     /* Configure the DMA Tx Channel with the buffer address and the buffer size */
00589     sEEDMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)pBuffer;
00590     sEEDMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
00591     sEEDMA_InitStructure.DMA_BufferSize = (uint32_t)BufferSize;
00592     DMA_Init(sEE_I2C_DMA_CHANNEL_TX, &sEEDMA_InitStructure);
00593   }
00594   else
00595   {
00596     /* Configure the DMA Rx Channel with the buffer address and the buffer size */
00597     sEEDMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)pBuffer;
00598     sEEDMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
00599     sEEDMA_InitStructure.DMA_BufferSize = (uint32_t)BufferSize;
00600     DMA_Init(sEE_I2C_DMA_CHANNEL_RX, &sEEDMA_InitStructure);
00601   }
00602 }
00603
00604 /**
00605   * @brief  DeInitializes the peripherals used by the SPI FLASH driver.
00606   * @param  None
00607   * @retval None
00608   */
00609 void sFLASH_LowLevel_DeInit(void)
00610 {
00611   GPIO_InitTypeDef GPIO_InitStructure;
00612
00613   /*!< Disable the sFLASH_SPI  */
00614   SPI_Cmd(sFLASH_SPI, DISABLE);
00615
00616   /*!< DeInitializes the sFLASH_SPI */
00617   SPI_I2S_DeInit(sFLASH_SPI);
00618
00619   /*!< sFLASH_SPI Periph clock disable */
00620   RCC_APB2PeriphClockCmd(sFLASH_SPI_CLK, DISABLE);
00621
00622   /*!< Configure sFLASH_SPI pins: SCK */
00623   GPIO_InitStructure.GPIO_Pin = sFLASH_SPI_SCK_PIN;
00624   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
00625   GPIO_Init(sFLASH_SPI_SCK_GPIO_PORT, &GPIO_InitStructure);
00626
00627   /*!< Configure sFLASH_SPI pins: MISO */
00628   GPIO_InitStructure.GPIO_Pin = sFLASH_SPI_MISO_PIN;
00629   GPIO_Init(sFLASH_SPI_MISO_GPIO_PORT, &GPIO_InitStructure);
00630
00631   /*!< Configure sFLASH_SPI pins: MOSI */
00632   GPIO_InitStructure.GPIO_Pin = sFLASH_SPI_MOSI_PIN;
00633   GPIO_Init(sFLASH_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure);
00634
00635   /*!< Configure sFLASH_CS_PIN pin: sFLASH Card CS pin */
00636   GPIO_InitStructure.GPIO_Pin = sFLASH_CS_PIN;
00637   GPIO_Init(sFLASH_CS_GPIO_PORT, &GPIO_InitStructure);
00638 }
00639
00640 /**
00641   * @brief  Initializes the peripherals used by the SPI FLASH driver.
00642   * @param  None
00643   * @retval None
00644   */
00645 void sFLASH_LowLevel_Init(void)
00646 {
00647   GPIO_InitTypeDef GPIO_InitStructure;
00648
00649   /*!< sFLASH_SPI_CS_GPIO, sFLASH_SPI_MOSI_GPIO, sFLASH_SPI_MISO_GPIO
00650        and sFLASH_SPI_SCK_GPIO Periph clock enable */
00651   RCC_APB2PeriphClockCmd(sFLASH_CS_GPIO_CLK | sFLASH_SPI_MOSI_GPIO_CLK | sFLASH_SPI_MISO_GPIO_CLK |
00652                          sFLASH_SPI_SCK_GPIO_CLK, ENABLE);
00653
00654   /*!< sFLASH_SPI Periph clock enable */
00655   RCC_APB2PeriphClockCmd(sFLASH_SPI_CLK, ENABLE);
00656
00657   /*!< Configure sFLASH_SPI pins: SCK */
00658   GPIO_InitStructure.GPIO_Pin = sFLASH_SPI_SCK_PIN;
00659   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00660   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
00661   GPIO_Init(sFLASH_SPI_SCK_GPIO_PORT, &GPIO_InitStructure);
00662
00663   /*!< Configure sFLASH_SPI pins: MOSI */
00664   GPIO_InitStructure.GPIO_Pin = sFLASH_SPI_MOSI_PIN;
00665   GPIO_Init(sFLASH_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure);
00666
00667   /*!< Configure sFLASH_SPI pins: MISO */
00668   GPIO_InitStructure.GPIO_Pin = sFLASH_SPI_MISO_PIN;
00669   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
00670   GPIO_Init(sFLASH_SPI_MISO_GPIO_PORT, &GPIO_InitStructure);
00671
00672   /*!< Configure sFLASH_CS_PIN pin: sFLASH Card CS pin */
00673   GPIO_InitStructure.GPIO_Pin = sFLASH_CS_PIN;
00674   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
00675   GPIO_Init(sFLASH_CS_GPIO_PORT, &GPIO_InitStructure);
00676 }
00677
00678 /**
00679   * @brief  DeInitializes the LM75_I2C.
00680   * @param  None
00681   * @retval None
00682   */
00683 void LM75_LowLevel_DeInit(void)
00684 {
00685   GPIO_InitTypeDef  GPIO_InitStructure;
00686
00687   /*!< Disable LM75_I2C */
00688   I2C_Cmd(LM75_I2C, DISABLE);
00689   /*!< DeInitializes the LM75_I2C */
00690   I2C_DeInit(LM75_I2C);
00691
00692   /*!< LM75_I2C Periph clock disable */
00693   RCC_APB1PeriphClockCmd(LM75_I2C_CLK, DISABLE);
00694
00695   /*!< Configure LM75_I2C pins: SCL */
00696   GPIO_InitStructure.GPIO_Pin = LM75_I2C_SCL_PIN;
00697   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
00698   GPIO_Init(LM75_I2C_SCL_GPIO_PORT, &GPIO_InitStructure);
00699
00700   /*!< Configure LM75_I2C pins: SDA */
00701   GPIO_InitStructure.GPIO_Pin = LM75_I2C_SDA_PIN;
00702   GPIO_Init(LM75_I2C_SDA_GPIO_PORT, &GPIO_InitStructure);
00703
00704   /*!< Configure LM75_I2C pin: SMBUS ALERT */
00705   GPIO_InitStructure.GPIO_Pin = LM75_I2C_SMBUSALERT_PIN;
00706   GPIO_Init(LM75_I2C_SMBUSALERT_GPIO_PORT, &GPIO_InitStructure);
00707 }
00708
00709 /**
00710   * @brief  Initializes the LM75_I2C..
00711   * @param  None
00712   * @retval None
00713   */
00714 void LM75_LowLevel_Init(void)
00715 {
00716   GPIO_InitTypeDef  GPIO_InitStructure;
00717
00718   /*!< LM75_I2C Periph clock enable */
00719   RCC_APB1PeriphClockCmd(LM75_I2C_CLK, ENABLE);
00720
00721   /*!< LM75_I2C_SCL_GPIO_CLK, LM75_I2C_SDA_GPIO_CLK
00722        and LM75_I2C_SMBUSALERT_GPIO_CLK Periph clock enable */
00723   RCC_APB2PeriphClockCmd(LM75_I2C_SCL_GPIO_CLK | LM75_I2C_SDA_GPIO_CLK |
00724                          LM75_I2C_SMBUSALERT_GPIO_CLK, ENABLE);
00725
00726   /*!< Configure LM75_I2C pins: SCL */
00727   GPIO_InitStructure.GPIO_Pin = LM75_I2C_SCL_PIN;
00728   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00729   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_OD;
00730   GPIO_Init(LM75_I2C_SCL_GPIO_PORT, &GPIO_InitStructure);
00731
00732   /*!< Configure LM75_I2C pins: SDA */
00733   GPIO_InitStructure.GPIO_Pin = LM75_I2C_SDA_PIN;
00734   GPIO_Init(LM75_I2C_SDA_GPIO_PORT, &GPIO_InitStructure);
00735
00736   /*!< Configure LM75_I2C pin: SMBUS ALERT */
00737   GPIO_InitStructure.GPIO_Pin = LM75_I2C_SMBUSALERT_PIN;
00738   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
00739   GPIO_Init(LM75_I2C_SMBUSALERT_GPIO_PORT, &GPIO_InitStructure);
00740 }
00741
00742 /**
00743   * @}
00744   */
00745
00746 /**
00747   * @}
00748   */
00749
00750 /**
00751   * @}
00752   */
00753
00754 /**
00755   * @}
00756   */
00757
00758 /**
00759   * @}
00760   */
00761
00762 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32100e_eval.h Source File

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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • STM32100E_EVAL

stm32100e_eval.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32100e_eval.h
00004   * @author  MCD Application Team
00005   * @version V4.5.0
00006   * @date    07-March-2011
00007   * @brief   This file contains definitions for STM32100E_EVAL's Leds, push-buttons
00008   *          COM ports, sFLASH (on SPI) and Temperature Sensor LM75 (on I2C)
00009   *          hardware resources.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Define to prevent recursive inclusion -------------------------------------*/
00025 #ifndef __STM32100E_EVAL_H
00026 #define __STM32100E_EVAL_H
00027
00028 #ifdef __cplusplus
00029  extern "C" {
00030 #endif
00031
00032 /* Includes ------------------------------------------------------------------*/
00033 #include "stm32_eval.h"
00034
00035 /** @addtogroup Utilities
00036   * @{
00037   */
00038
00039 /** @addtogroup STM32_EVAL
00040   * @{
00041   */
00042
00043 /** @addtogroup STM32100E_EVAL
00044   * @{
00045   */
00046
00047 /** @addtogroup STM32100E_EVAL_LOW_LEVEL
00048   * @{
00049   */
00050
00051 /** @defgroup STM32100E_EVAL_LOW_LEVEL_Exported_Types
00052   * @{
00053   */
00054 /**
00055   * @}
00056   */
00057
00058 /** @defgroup STM32100E_EVAL_LOW_LEVEL_Exported_Constants
00059   * @{
00060   */
00061 /** @addtogroup STM32100E_EVAL_LOW_LEVEL_LED
00062   * @{
00063   */
00064 #define LEDn                             4
00065
00066 #define LED1_PIN                         GPIO_Pin_6
00067 #define LED1_GPIO_PORT                   GPIOF
00068 #define LED1_GPIO_CLK                    RCC_APB2Periph_GPIOF
00069
00070 #define LED2_PIN                         GPIO_Pin_7
00071 #define LED2_GPIO_PORT                   GPIOF
00072 #define LED2_GPIO_CLK                    RCC_APB2Periph_GPIOF
00073
00074 #define LED3_PIN                         GPIO_Pin_8
00075 #define LED3_GPIO_PORT                   GPIOF
00076 #define LED3_GPIO_CLK                    RCC_APB2Periph_GPIOF
00077
00078 #define LED4_PIN                         GPIO_Pin_9
00079 #define LED4_GPIO_PORT                   GPIOF
00080 #define LED4_GPIO_CLK                    RCC_APB2Periph_GPIOF
00081
00082 /**
00083   * @}
00084   */
00085
00086 /** @addtogroup STM32100E_EVAL_LOW_LEVEL_BUTTON
00087   * @{
00088   */
00089 #define BUTTONn                          8
00090
00091 /**
00092  * @brief Wakeup push-button
00093  */
00094 #define WAKEUP_BUTTON_PIN                GPIO_Pin_0
00095 #define WAKEUP_BUTTON_GPIO_PORT          GPIOA
00096 #define WAKEUP_BUTTON_GPIO_CLK           RCC_APB2Periph_GPIOA
00097 #define WAKEUP_BUTTON_EXTI_LINE          EXTI_Line0
00098 #define WAKEUP_BUTTON_EXTI_PORT_SOURCE   GPIO_PortSourceGPIOA
00099 #define WAKEUP_BUTTON_EXTI_PIN_SOURCE    GPIO_PinSource0
00100 #define WAKEUP_BUTTON_EXTI_IRQn          EXTI0_IRQn
00101 /**
00102  * @brief Tamper push-button
00103  */
00104 #define TAMPER_BUTTON_PIN                GPIO_Pin_13
00105 #define TAMPER_BUTTON_GPIO_PORT          GPIOC
00106 #define TAMPER_BUTTON_GPIO_CLK           RCC_APB2Periph_GPIOC
00107 #define TAMPER_BUTTON_EXTI_LINE          EXTI_Line13
00108 #define TAMPER_BUTTON_EXTI_PORT_SOURCE   GPIO_PortSourceGPIOC
00109 #define TAMPER_BUTTON_EXTI_PIN_SOURCE    GPIO_PinSource13
00110 #define TAMPER_BUTTON_EXTI_IRQn          EXTI15_10_IRQn
00111 /**
00112  * @brief Key push-button
00113  */
00114 #define KEY_BUTTON_PIN                   GPIO_Pin_8
00115 #define KEY_BUTTON_GPIO_PORT             GPIOG
00116 #define KEY_BUTTON_GPIO_CLK              RCC_APB2Periph_GPIOG
00117 #define KEY_BUTTON_EXTI_LINE             EXTI_Line8
00118 #define KEY_BUTTON_EXTI_PORT_SOURCE      GPIO_PortSourceGPIOG
00119 #define KEY_BUTTON_EXTI_PIN_SOURCE       GPIO_PinSource8
00120 #define KEY_BUTTON_EXTI_IRQn             EXTI9_5_IRQn
00121 /**
00122  * @brief Joystick Right push-button
00123  */
00124 #define RIGHT_BUTTON_PIN                 GPIO_Pin_13
00125 #define RIGHT_BUTTON_GPIO_PORT           GPIOG
00126 #define RIGHT_BUTTON_GPIO_CLK            RCC_APB2Periph_GPIOG
00127 #define RIGHT_BUTTON_EXTI_LINE           EXTI_Line13
00128 #define RIGHT_BUTTON_EXTI_PORT_SOURCE    GPIO_PortSourceGPIOG
00129 #define RIGHT_BUTTON_EXTI_PIN_SOURCE     GPIO_PinSource13
00130 #define RIGHT_BUTTON_EXTI_IRQn           EXTI15_10_IRQn
00131 /**
00132  * @brief Joystick Left push-button
00133  */
00134 #define LEFT_BUTTON_PIN                  GPIO_Pin_14
00135 #define LEFT_BUTTON_GPIO_PORT            GPIOG
00136 #define LEFT_BUTTON_GPIO_CLK             RCC_APB2Periph_GPIOG
00137 #define LEFT_BUTTON_EXTI_LINE            EXTI_Line14
00138 #define LEFT_BUTTON_EXTI_PORT_SOURCE     GPIO_PortSourceGPIOG
00139 #define LEFT_BUTTON_EXTI_PIN_SOURCE      GPIO_PinSource14
00140 #define LEFT_BUTTON_EXTI_IRQn            EXTI15_10_IRQn
00141 /**
00142  * @brief Joystick Up push-button
00143  */
00144 #define UP_BUTTON_PIN                    GPIO_Pin_15
00145 #define UP_BUTTON_GPIO_PORT              GPIOG
00146 #define UP_BUTTON_GPIO_CLK               RCC_APB2Periph_GPIOG
00147 #define UP_BUTTON_EXTI_LINE              EXTI_Line15
00148 #define UP_BUTTON_EXTI_PORT_SOURCE       GPIO_PortSourceGPIOG
00149 #define UP_BUTTON_EXTI_PIN_SOURCE        GPIO_PinSource15
00150 #define UP_BUTTON_EXTI_IRQn              EXTI15_10_IRQn
00151 /**
00152  * @brief Joystick Down push-button
00153  */
00154 #define DOWN_BUTTON_PIN                  GPIO_Pin_11
00155 #define DOWN_BUTTON_GPIO_PORT            GPIOG
00156 #define DOWN_BUTTON_GPIO_CLK             RCC_APB2Periph_GPIOG
00157 #define DOWN_BUTTON_EXTI_LINE            EXTI_Line11
00158 #define DOWN_BUTTON_EXTI_PORT_SOURCE     GPIO_PortSourceGPIOG
00159 #define DOWN_BUTTON_EXTI_PIN_SOURCE      GPIO_PinSource11
00160 #define DOWN_BUTTON_EXTI_IRQn            EXTI15_10_IRQn
00161 /**
00162  * @brief Joystick Sel push-button
00163  */
00164 #define SEL_BUTTON_PIN                   GPIO_Pin_7
00165 #define SEL_BUTTON_GPIO_PORT             GPIOG
00166 #define SEL_BUTTON_GPIO_CLK              RCC_APB2Periph_GPIOG
00167 #define SEL_BUTTON_EXTI_LINE             EXTI_Line7
00168 #define SEL_BUTTON_EXTI_PORT_SOURCE      GPIO_PortSourceGPIOG
00169 #define SEL_BUTTON_EXTI_PIN_SOURCE       GPIO_PinSource7
00170 #define SEL_BUTTON_EXTI_IRQn             EXTI9_5_IRQn
00171 /**
00172   * @}
00173   */
00174
00175 /** @addtogroup STM32100E_EVAL_LOW_LEVEL_COM
00176   * @{
00177   */
00178 #define COMn                             2
00179
00180 /**
00181  * @brief Definition for COM port1, connected to USART1
00182  */
00183 #define EVAL_COM1                        USART1
00184 #define EVAL_COM1_CLK                    RCC_APB2Periph_USART1
00185 #define EVAL_COM1_TX_PIN                 GPIO_Pin_9
00186 #define EVAL_COM1_TX_GPIO_PORT           GPIOA
00187 #define EVAL_COM1_TX_GPIO_CLK            RCC_APB2Periph_GPIOA
00188 #define EVAL_COM1_RX_PIN                 GPIO_Pin_10
00189 #define EVAL_COM1_RX_GPIO_PORT           GPIOA
00190 #define EVAL_COM1_RX_GPIO_CLK            RCC_APB2Periph_GPIOA
00191 #define EVAL_COM1_IRQn                   USART1_IRQn
00192
00193 /**
00194  * @brief Definition for COM port2, connected to USART2
00195  */
00196 #define EVAL_COM2                        USART2
00197 #define EVAL_COM2_CLK                    RCC_APB1Periph_USART2
00198 #define EVAL_COM2_TX_PIN                 GPIO_Pin_2
00199 #define EVAL_COM2_TX_GPIO_PORT           GPIOA
00200 #define EVAL_COM2_TX_GPIO_CLK            RCC_APB2Periph_GPIOA
00201 #define EVAL_COM2_RX_PIN                 GPIO_Pin_3
00202 #define EVAL_COM2_RX_GPIO_PORT           GPIOA
00203 #define EVAL_COM2_RX_GPIO_CLK            RCC_APB2Periph_GPIOA
00204 #define EVAL_COM2_IRQn                   USART2_IRQn
00205
00206 /**
00207   * @}
00208   */
00209
00210 /** @addtogroup STM32100E_EVAL_LOW_LEVEL_SD_FLASH
00211   * @{
00212   */
00213 /**
00214   * @brief  SD SPI Interface pins
00215   */
00216 #define SD_SPI                           SPI2
00217 #define SD_SPI_CLK                       RCC_APB1Periph_SPI2
00218 #define SD_SPI_SCK_PIN                   GPIO_Pin_13                 /* PC.13 */
00219 #define SD_SPI_SCK_GPIO_PORT             GPIOB                       /* GPIOB */
00220 #define SD_SPI_SCK_GPIO_CLK              RCC_APB2Periph_GPIOB
00221 #define SD_SPI_MISO_PIN                  GPIO_Pin_14                 /* PC.14 */
00222 #define SD_SPI_MISO_GPIO_PORT            GPIOB                       /* GPIOB */
00223 #define SD_SPI_MISO_GPIO_CLK             RCC_APB2Periph_GPIOB
00224 #define SD_SPI_MOSI_PIN                  GPIO_Pin_15                 /* PB.15 */
00225 #define SD_SPI_MOSI_GPIO_PORT            GPIOB                       /* GPIOB */
00226 #define SD_SPI_MOSI_GPIO_CLK             RCC_APB2Periph_GPIOB
00227 #define SD_CS_PIN                        GPIO_Pin_6                  /* PG.06 */
00228 #define SD_CS_GPIO_PORT                  GPIOG                       /* GPIOG */
00229 #define SD_CS_GPIO_CLK                   RCC_APB2Periph_GPIOG
00230 #define SD_DETECT_PIN                    GPIO_Pin_11                 /* PF.11 */
00231 #define SD_DETECT_GPIO_PORT              GPIOF                       /* GPIOF */
00232 #define SD_DETECT_GPIO_CLK               RCC_APB2Periph_GPIOF
00233
00234 /**
00235   * @}
00236   */
00237
00238 /** @addtogroup STM3210C_EVAL_LOW_LEVEL_I2C_EE
00239   * @{
00240   */
00241 /**
00242   * @brief  I2C EEPROM Interface pins
00243   */
00244 #define sEE_I2C                          I2C2
00245 #define sEE_I2C_CLK                      RCC_APB1Periph_I2C2
00246 #define sEE_I2C_SCL_PIN                  GPIO_Pin_10                 /* PB.10 */
00247 #define sEE_I2C_SCL_GPIO_PORT            GPIOB                       /* GPIOB */
00248 #define sEE_I2C_SCL_GPIO_CLK             RCC_APB2Periph_GPIOB
00249 #define sEE_I2C_SDA_PIN                  GPIO_Pin_11                  /* PB.11 */
00250 #define sEE_I2C_SDA_GPIO_PORT            GPIOB                       /* GPIOB */
00251 #define sEE_I2C_SDA_GPIO_CLK             RCC_APB2Periph_GPIOB
00252 #define sEE_M24C64_32
00253
00254 #define sEE_I2C_DMA                      DMA1
00255 #define sEE_I2C_DMA_CHANNEL_TX           DMA1_Channel4
00256 #define sEE_I2C_DMA_CHANNEL_RX           DMA1_Channel5
00257 #define sEE_I2C_DMA_FLAG_TX_TC           DMA1_IT_TC4
00258 #define sEE_I2C_DMA_FLAG_TX_GL           DMA1_IT_GL4
00259 #define sEE_I2C_DMA_FLAG_RX_TC           DMA1_IT_TC5
00260 #define sEE_I2C_DMA_FLAG_RX_GL           DMA1_IT_GL5
00261 #define sEE_I2C_DMA_CLK                  RCC_AHBPeriph_DMA1
00262 #define sEE_I2C_DR_Address               ((uint32_t)0x40005810)
00263 #define sEE_USE_DMA
00264
00265 #define sEE_I2C_DMA_TX_IRQn              DMA1_Channel4_IRQn
00266 #define sEE_I2C_DMA_RX_IRQn              DMA1_Channel5_IRQn
00267 #define sEE_I2C_DMA_TX_IRQHandler        DMA1_Channel4_IRQHandler
00268 #define sEE_I2C_DMA_RX_IRQHandler        DMA1_Channel5_IRQHandler
00269 #define sEE_I2C_DMA_PREPRIO              0
00270 #define sEE_I2C_DMA_SUBPRIO              0
00271
00272 #define sEE_DIRECTION_TX                 0
00273 #define sEE_DIRECTION_RX                 1
00274
00275 /* Time constant for the delay caclulation allowing to have a millisecond
00276    incrementing counter. This value should be equal to (System Clock / 1000).
00277    ie. if system clock = 24MHz then sEE_TIME_CONST should be 24. */
00278 #define sEE_TIME_CONST          24
00279
00280 /**
00281   * @}
00282   */
00283
00284 /** @addtogroup STM32100E_EVAL_LOW_LEVEL_M25P_FLASH_SPI
00285   * @{
00286   */
00287 /**
00288   * @brief  M25P FLASH SPI Interface pins
00289   */
00290 #define sFLASH_SPI                       SPI1
00291 #define sFLASH_SPI_CLK                   RCC_APB2Periph_SPI1
00292 #define sFLASH_SPI_SCK_PIN               GPIO_Pin_5                  /* PA.05 */
00293 #define sFLASH_SPI_SCK_GPIO_PORT         GPIOA                       /* GPIOA */
00294 #define sFLASH_SPI_SCK_GPIO_CLK          RCC_APB2Periph_GPIOA
00295 #define sFLASH_SPI_MISO_PIN              GPIO_Pin_6                  /* PA.06 */
00296 #define sFLASH_SPI_MISO_GPIO_PORT        GPIOA                       /* GPIOA */
00297 #define sFLASH_SPI_MISO_GPIO_CLK         RCC_APB2Periph_GPIOA
00298 #define sFLASH_SPI_MOSI_PIN              GPIO_Pin_7                  /* PA.07 */
00299 #define sFLASH_SPI_MOSI_GPIO_PORT        GPIOA                       /* GPIOA */
00300 #define sFLASH_SPI_MOSI_GPIO_CLK         RCC_APB2Periph_GPIOA
00301 #define sFLASH_CS_PIN                    GPIO_Pin_6                  /* PE.06 */
00302 #define sFLASH_CS_GPIO_PORT              GPIOE                       /* GPIOE */
00303 #define sFLASH_CS_GPIO_CLK               RCC_APB2Periph_GPIOE
00304
00305 /**
00306   * @}
00307   */
00308
00309
00310 /** @addtogroup STM32100E_EVAL_LOW_LEVEL_TSENSOR_I2C
00311   * @{
00312   */
00313 /**
00314   * @brief  LM75 Temperature Sensor I2C Interface pins
00315   */
00316 #define LM75_I2C                         I2C2
00317 #define LM75_I2C_CLK                     RCC_APB1Periph_I2C2
00318 #define LM75_I2C_SCL_PIN                 GPIO_Pin_10                 /* PB.10 */
00319 #define LM75_I2C_SCL_GPIO_PORT           GPIOB                       /* GPIOB */
00320 #define LM75_I2C_SCL_GPIO_CLK            RCC_APB2Periph_GPIOB
00321 #define LM75_I2C_SDA_PIN                 GPIO_Pin_11                 /* PB.11 */
00322 #define LM75_I2C_SDA_GPIO_PORT           GPIOB                       /* GPIOB */
00323 #define LM75_I2C_SDA_GPIO_CLK            RCC_APB2Periph_GPIOB
00324 #define LM75_I2C_SMBUSALERT_PIN          GPIO_Pin_12                 /* PB.12 */
00325 #define LM75_I2C_SMBUSALERT_GPIO_PORT    GPIOB                       /* GPIOB */
00326 #define LM75_I2C_SMBUSALERT_GPIO_CLK     RCC_APB2Periph_GPIOB
00327 #define LM75_I2C_DR                      ((uint32_t)0x40005810)
00328
00329 #define LM75_DMA_CLK                     RCC_AHBPeriph_DMA1
00330 #define LM75_DMA_TX_CHANNEL              DMA1_Channel4
00331 #define LM75_DMA_RX_CHANNEL              DMA1_Channel5
00332 #define LM75_DMA_TX_TCFLAG               DMA1_FLAG_TC4
00333 #define LM75_DMA_RX_TCFLAG               DMA1_FLAG_TC5
00334
00335 /**
00336   * @}
00337   */
00338
00339 /**
00340   * @}
00341   */
00342
00343 /** @defgroup STM32100E_EVAL_LOW_LEVEL_Exported_Macros
00344   * @{
00345   */
00346 /**
00347   * @}
00348   */
00349
00350 /** @defgroup STM32100E_EVAL_LOW_LEVEL_Exported_Functions
00351   * @{
00352   */
00353 void STM_EVAL_LEDInit(Led_TypeDef Led);
00354 void STM_EVAL_LEDOn(Led_TypeDef Led);
00355 void STM_EVAL_LEDOff(Led_TypeDef Led);
00356 void STM_EVAL_LEDToggle(Led_TypeDef Led);
00357 void STM_EVAL_PBInit(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode);
00358 uint32_t STM_EVAL_PBGetState(Button_TypeDef Button);
00359 void STM_EVAL_COMInit(COM_TypeDef COM, USART_InitTypeDef* USART_InitStruct);
00360 void SD_LowLevel_DeInit(void);
00361 void SD_LowLevel_Init(void);
00362 void sEE_LowLevel_DeInit(void);
00363 void sEE_LowLevel_Init(void);
00364 void sEE_LowLevel_DMAConfig(uint32_t pBuffer, uint32_t BufferSize, uint32_t Direction);
00365 void sFLASH_LowLevel_DeInit(void);
00366 void sFLASH_LowLevel_Init(void);
00367 void LM75_LowLevel_DeInit(void);
00368 void LM75_LowLevel_Init(void);
00369 /**
00370   * @}
00371   */
00372 #ifdef __cplusplus
00373 }
00374 #endif
00375
00376 #endif /* __STM32100E_EVAL_H */
00377 /**
00378   * @}
00379   */
00380
00381 /**
00382   * @}
00383   */
00384
00385 /**
00386   * @}
00387   */
00388
00389 /**
00390   * @}
00391   */
00392
00393 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32100e_eval_cec.c Source File

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  • STM32100E_EVAL

stm32100e_eval_cec.c

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32100e_eval_cec.c
00004   * @author  MCD Application Team
00005   * @version V4.5.0
00006   * @date    07-March-2011
00007   * @brief   This file provides all the STM32100E-EVAL HDMI-CEC firmware functions.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32100e_eval_cec.h"
00024
00025 /** @addtogroup Utilities
00026   * @{
00027   */
00028
00029 /** @addtogroup STM32_EVAL
00030   * @{
00031   */
00032
00033 /** @addtogroup STM32100E_EVAL
00034   * @{
00035   */
00036
00037 /** @defgroup STM32100E_EVAL_CEC
00038   * @brief This file includes the CEC Stack driver for HDMI-CEC Module
00039   *        of STM32100E-EVAL board.
00040   * @{
00041   */
00042
00043 /** @defgroup STM32100E_EVAL_CEC_Private_Types
00044   * @{
00045   */
00046
00047 /**
00048   * @}
00049   */
00050
00051 /** @defgroup STM32100E_EVAL_CEC_Private_Defines
00052   * @{
00053   */
00054
00055
00056 /**
00057   * @}
00058   */
00059
00060 /** @defgroup STM32100E_EVAL_CEC_Private_Macros
00061   * @{
00062   */
00063 /**
00064   * @}
00065   */
00066
00067 /** @defgroup STM32100E_EVAL_CEC_Private_Variables
00068   * @{
00069   */
00070
00071 __IO uint32_t ReceivedFrame = 0;
00072 __IO uint32_t SendFrame = 0;
00073 __IO uint32_t BufferCount = 0, TxCounter = 0, RxCounter = 0;
00074 __IO uint8_t BufferPointer[15];
00075 __IO uint32_t ReceiveStatus = 0;
00076 __IO uint32_t SendStatus = 0;
00077 __IO uint8_t TransErrorCode = 0;
00078 __IO uint8_t RecepErrorCode = 0;
00079 __IO uint8_t MyLogicalAddress = 0;
00080 __IO uint16_t MyPhysicalAddress = 0;
00081 __IO uint8_t DeviceType = 0;
00082 #ifdef HDMI_CEC_USE_DDC
00083 __IO uint8_t pBuffer[256];
00084 __IO uint16_t NumByteToRead = 255;
00085 #endif
00086 __IO uint8_t CECDevicesNumber = 0;
00087
00088 HDMI_CEC_Message HDMI_CEC_TX_MessageStructPrivate;
00089 HDMI_CEC_Message HDMI_CEC_RX_MessageStructPrivate;
00090 HDMI_CEC_Message HDMI_CEC_TX_MessageStructure;
00091
00092 __IO uint8_t FeatureOpcode = 0;
00093 __IO uint8_t AbortReason = 0;
00094 __IO uint8_t DeviceCount = 0;
00095
00096 HDMI_CEC_Map HDMI_CEC_MapStruct;
00097 HDMI_CEC_Map HDMI_CEC_DeviceMap[14];
00098
00099 /* CEC follower addresses */
00100 uint8_t* HDMI_CEC_Follower_String[13][2] =
00101   {
00102     {(uint8_t*)"         TV         ", (uint8_t*)"0"},
00103     {(uint8_t*)"Recording Device 1  ", (uint8_t*)"0"},
00104     {(uint8_t*)"Recording Device 2  ", (uint8_t*)"0"},
00105     {(uint8_t*)"    Tuner 1         ", (uint8_t*)"0"},
00106     {(uint8_t*)" Playback Device 1  ", (uint8_t*)"0"},
00107     {(uint8_t*)"   Audio System     ", (uint8_t*)"0"},
00108     {(uint8_t*)"    Tuner 2         ", (uint8_t*)"0"},
00109     {(uint8_t*)"    Tuner 3         ", (uint8_t*)"0"},
00110     {(uint8_t*)" Playback Device 2  ", (uint8_t*)"0"},
00111     {(uint8_t*)"Recording Device 3  ", (uint8_t*)"0"},
00112     {(uint8_t*)"      Tuner 4       ", (uint8_t*)"0"},
00113     {(uint8_t*)" Playback Device 3  ", (uint8_t*)"0"},
00114     {(uint8_t*)"     Broadcast      ", (uint8_t*)"1"}
00115   };
00116
00117 /**
00118   * @}
00119   */
00120
00121
00122 /** @defgroup STM32100E_EVAL_CEC_Private_Function_Prototypes
00123   * @{
00124   */
00125 static HDMI_CEC_Error PhysicalAddressDiscovery(void);
00126 static HDMI_CEC_Error LogicalAddressAllocation(void);
00127
00128
00129 /**
00130   * @}
00131   */
00132
00133
00134 /** @defgroup STM32100E_EVAL_CEC_Private_Functions
00135   * @{
00136   */
00137
00138 /**
00139   * @brief  Initializes the HDMI CEC.
00140   * @param  None
00141   * @retval HDMI_CEC_Error: CEC Error code
00142   */
00143 HDMI_CEC_Error HDMI_CEC_Init(void)
00144 {
00145   GPIO_InitTypeDef GPIO_InitStructure;
00146   CEC_InitTypeDef CEC_InitStructure;
00147   HDMI_CEC_Error errorstatus = HDMI_CEC_OK;
00148   uint8_t sendcount = 0;
00149
00150 #ifdef HDMI_CEC_USE_DDC
00151   I2C_InitTypeDef  I2C_InitStructure;
00152   /* Enable CEC_I2C clocks */
00153   RCC_APB1PeriphClockCmd(HDMI_CEC_I2C_CLK, ENABLE);
00154
00155   /* Enable CEC_I2C_GPIO and CEC_HPD_GPIO clocks */
00156   RCC_APB2PeriphClockCmd(HDMI_CEC_I2C_GPIO_CLK | HDMI_CEC_HPD_GPIO_CLK, ENABLE);
00157 #endif
00158
00159   /* Enable CEC clocks */
00160   RCC_APB1PeriphClockCmd(RCC_APB1Periph_CEC, ENABLE);
00161
00162   /* Enable CEC_LINE_GPIO clocks */
00163   RCC_APB2PeriphClockCmd(HDMI_CEC_LINE_GPIO_CLK, ENABLE);
00164
00165   /* Configure CEC_LINE_GPIO as Output open drain */
00166   GPIO_InitStructure.GPIO_Pin = HDMI_CEC_LINE_PIN;
00167   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00168   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_OD;
00169   GPIO_Init(HDMI_CEC_LINE_GPIO_PORT, &GPIO_InitStructure);
00170
00171 #ifdef HDMI_CEC_USE_DDC
00172   /* Configure CEC_I2C_SCL_PIN and CEC_I2C_SDA_PIN  as Output open drain */
00173   GPIO_InitStructure.GPIO_Pin = HDMI_CEC_I2C_SCL_PIN | HDMI_CEC_I2C_SDA_PIN;
00174   GPIO_Init(HDMI_CEC_I2C_GPIO_PORT, &GPIO_InitStructure);
00175
00176 /* This configuration is only when the HDMI CEC is configured as source.
00177    The HDMI source has to provide the +5V Power signal to the sink.
00178    On STM32100E-EVAL borad, you have to solder the SB4 Solder bridge.
00179    Then, the source will wait for HPD signal to be asserted from the sink.
00180    Once the HPD signal is detected the source shall read the EDID structure
00181    throuhgh the DDC channel. */
00182   /* Configure CEC_HPD_GPIO as Input pull down */
00183   GPIO_InitStructure.GPIO_Pin = HDMI_CEC_HPD_PIN;
00184   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD;
00185   GPIO_Init(HDMI_CEC_HPD_GPIO_PORT, &GPIO_InitStructure);
00186
00187
00188 /* This configuration is only when the HDMI CEC is configured as sink.
00189    The HDMI sink has to wait for the +5V Power signal from the source.
00190    On STM32100E-EVAL borad, SB4 Solder bridge should be open (default configuration).
00191    Then, the sink will assert the HPD signal to inform the source that the EDID
00192    is ready for read through DDC channel. In this implementation, the EDID structure
00193    is not implemented. */
00194 /*  GPIO_InitStructure.GPIO_Pin = HDMI_CEC_HPD_PIN;
00195   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
00196   GPIO_Init(HDMI_CEC_HPD_GPIO_PORT, &GPIO_InitStructure);
00197
00198   HDMI_CEC_HPD_HIGH(); // Set the Hot plug detect signal */
00199
00200   /* Enable CEC_I2C */
00201   I2C_Cmd(HDMI_CEC_I2C, ENABLE);
00202
00203   /* I2C configuration */
00204   I2C_InitStructure.I2C_Mode = I2C_Mode_I2C;
00205   I2C_InitStructure.I2C_DutyCycle = I2C_DutyCycle_2;
00206   I2C_InitStructure.I2C_OwnAddress1 = HDMI_CEC_I2C_SLAVE_ADDRESS7;
00207   I2C_InitStructure.I2C_Ack = I2C_Ack_Enable;
00208   I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
00209   I2C_InitStructure.I2C_ClockSpeed = HDMI_CEC_I2C_CLOCK_SPEED;
00210   I2C_Init(HDMI_CEC_I2C, &I2C_InitStructure);
00211 #endif
00212
00213   /* Physical Address discovery */
00214   errorstatus = PhysicalAddressDiscovery();
00215
00216   if (errorstatus != HDMI_CEC_OK)
00217   {
00218     /* Device not connected (Physical Address lost) */
00219     return(errorstatus);
00220   }
00221
00222
00223   /* CEC DeInit */
00224   CEC_DeInit();
00225
00226   /* Configure CEC */
00227   CEC_InitStructure.CEC_BitTimingMode = CEC_BitTimingStdMode;
00228   CEC_InitStructure.CEC_BitPeriodMode = CEC_BitPeriodStdMode;
00229   CEC_Init(&CEC_InitStructure);
00230
00231   /* Set Prescaler value for APB1 clock = 24MHz */
00232   CEC_SetPrescaler(0x4AF);
00233
00234   /* Enable CEC */
00235   CEC_Cmd(ENABLE);
00236
00237   /* Logical Address Allocation */
00238   sendcount = 0;
00239   errorstatus = LogicalAddressAllocation();
00240
00241   while ((errorstatus != HDMI_CEC_OK) && sendcount < 0x5)
00242   {
00243     sendcount++;
00244     errorstatus = LogicalAddressAllocation();
00245   }
00246
00247   if (errorstatus != HDMI_CEC_OK)
00248   {
00249     /* Device Unregistred */
00250     return(errorstatus);
00251   }
00252
00253   HDMI_CEC_CheckConnectedDevices();
00254
00255   /* Set the CEC initiator address */
00256   CEC_OwnAddressConfig(MyLogicalAddress);
00257
00258   /* Activate CEC interrupts associated to the set of RBTF,RERR, TBTF, TERR flags */
00259   CEC_ITConfig(ENABLE);
00260
00261   /* Report physical address*/
00262   errorstatus = HDMI_CEC_ReportPhysicalAddress();
00263   sendcount = 0;
00264
00265   while ((errorstatus != HDMI_CEC_OK) && sendcount < 0x5)
00266   {
00267     sendcount++;
00268     errorstatus = HDMI_CEC_ReportPhysicalAddress();
00269   }
00270
00271   if (errorstatus != HDMI_CEC_OK)
00272   {
00273     /* Device Unregistred */
00274     return(errorstatus);
00275   }
00276
00277   return errorstatus;
00278 }
00279
00280 /**
00281   * @brief  Transmit message by taking  data from typedef struct CEC_Meassage
00282   * @param  CEC_TX_MessageStructure: pointer to an CEC_Message structure that contains
00283   *         the message to be sent.
00284   * @retval HDMI_CEC_Error: CEC Error code
00285   */
00286 HDMI_CEC_Error HDMI_CEC_TransmitMessage(HDMI_CEC_Message *HDMI_CEC_TX_MessageStructure)
00287 {
00288   HDMI_CEC_Error errorstatus = HDMI_CEC_OK;
00289   __IO uint32_t count = 0, j = 0;
00290
00291   SendFrame = 0;
00292   SendStatus = 0;
00293   TxCounter = 0;
00294   BufferCount = 0;
00295
00296   HDMI_CEC_TX_MessageStructPrivate =  *HDMI_CEC_TX_MessageStructure;
00297
00298   /* Initialize BufferPointer */
00299   for (j = 0; j < 15; j++)
00300   {
00301     BufferPointer[j] = 0;
00302   }
00303
00304   BufferPointer[0] =  HDMI_CEC_TX_MessageStructPrivate.Opcode;
00305
00306   for (BufferCount = 1; BufferCount < HDMI_CEC_TX_MessageStructPrivate.TxMessageLength + 1; BufferCount++)
00307   {
00308     BufferPointer[BufferCount] =  HDMI_CEC_TX_MessageStructPrivate.Operande[BufferCount-1];
00309   }
00310
00311   CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR);
00312
00313   /* Write single Data in the TX Buffer to Transmit through the CEC peripheral */
00314   CEC_SendDataByte(HDMI_CEC_TX_MessageStructPrivate.Header);
00315
00316   /* Initiate Message Transmission */
00317   CEC_StartOfMessage();
00318
00319   while ((SendFrame == 0) && (count < HDMI_CEC_TIMEOUT_VALUE))
00320   {
00321     count++;
00322   }
00323   if (count >= HDMI_CEC_TIMEOUT_VALUE)
00324   {
00325     errorstatus = HDMI_CEC_TIMEOUT;
00326     return(errorstatus);
00327   }
00328
00329   if (SendStatus == 0)
00330   {
00331     errorstatus = (HDMI_CEC_Error) TransErrorCode;
00332   }
00333
00334   return errorstatus;
00335 }
00336
00337
00338 /**
00339   * @brief  Get the ESR register status.
00340   * @param  None
00341   * @retval HDMI_CEC_Error: CEC Error code
00342   */
00343 HDMI_CEC_Error HDMI_CEC_GetErrorStatus (void)
00344 {
00345   HDMI_CEC_Error errorstatus = HDMI_CEC_OK;
00346
00347   /* Bit timing error case*/
00348   if (CEC_GetFlagStatus(CEC_FLAG_BTE) != RESET)
00349   {
00350     errorstatus = HDMI_CEC_BIT_TIMING;
00351   }
00352   /* Bit period error case */
00353   if (CEC_GetFlagStatus(CEC_FLAG_BPE) != RESET)
00354   {
00355     errorstatus = HDMI_CEC_BIT_PERIOD;
00356   }
00357   /* Recieve error case */
00358   if (CEC_GetFlagStatus(CEC_FLAG_RBTFE) != RESET)
00359   {
00360     errorstatus = HDMI_CEC_RX_BLOCK_FINISHED;
00361   }
00362   /* Start bit error case*/
00363   if (CEC_GetFlagStatus(CEC_FLAG_SBE) != RESET)
00364   {
00365     errorstatus = HDMI_CEC_START_BIT;
00366   }
00367   /* Acknowledge error case*/
00368   if (CEC_GetFlagStatus(CEC_FLAG_ACKE) != RESET)
00369   {
00370     errorstatus = HDMI_CEC_BLOCK_ACKNOWLEDGE;
00371   }
00372   /* Line error case */
00373   if (CEC_GetFlagStatus(CEC_FLAG_LINE) != RESET)
00374   {
00375     errorstatus = HDMI_CEC_LINE;
00376   }
00377   /* Transfert error case*/
00378   if (CEC_GetFlagStatus(CEC_FLAG_TBTFE) != RESET)
00379   {
00380     errorstatus = HDMI_CEC_TX_BLOCK_FINISHED;
00381   }
00382   /* Clear All errors */
00383   CEC_ClearFlag(CEC_FLAG_RERR);
00384   CEC_ClearFlag(CEC_FLAG_TERR);
00385   return errorstatus;
00386 }
00387
00388 /**
00389   * @brief  Allows to process all the interrupts that are high.
00390   * @param  None
00391   * @retval None
00392   */
00393 void HDMI_CEC_ProcessIRQSrc(void)
00394 {
00395   /********************** Reception *********************************************/
00396   /* Check if a reception error occured */
00397   if (CEC_GetFlagStatus(CEC_FLAG_RERR))
00398   {
00399     /* Set receive status bit (Error) */
00400     ReceiveStatus  = 0;
00401     ReceivedFrame  = 1;
00402     RecepErrorCode = HDMI_CEC_GetErrorStatus();
00403     CEC_ClearFlag(CEC_FLAG_RERR | CEC_FLAG_RSOM | CEC_FLAG_REOM  | CEC_FLAG_RBTF);
00404   }
00405   else if (CEC_GetFlagStatus(CEC_FLAG_RBTF))
00406   {
00407     /* Check if the byte received is the last one of the message */
00408     if (CEC_GetFlagStatus(CEC_FLAG_REOM))
00409     {
00410       HDMI_CEC_RX_MessageStructPrivate.Operande[RxCounter-1] = CEC_ReceiveDataByte();
00411       HDMI_CEC_RX_MessageStructPrivate.RxMessageLength = RxCounter;
00412       ReceiveStatus = SUCCESS;
00413       ReceivedFrame = 1;
00414     }
00415     /* Check if the byte received is a Header */
00416     else if (CEC_GetFlagStatus(CEC_FLAG_RSOM))
00417     {
00418       ReceiveStatus = 0;
00419       HDMI_CEC_RX_MessageStructPrivate.Header = CEC_ReceiveDataByte();
00420       RxCounter = 0;
00421     }
00422     /* Receive each byte except header in the reception buffer */
00423     else
00424     {
00425       if (RxCounter != 0)
00426       {
00427         HDMI_CEC_RX_MessageStructPrivate.Operande[RxCounter-1] = CEC_ReceiveDataByte();
00428         RxCounter++;
00429       }
00430       else
00431       {
00432         HDMI_CEC_RX_MessageStructPrivate.Opcode = CEC_ReceiveDataByte();
00433         RxCounter++;
00434       }
00435
00436     }
00437     /* Clear all reception flags */
00438     CEC_ClearFlag(CEC_FLAG_RSOM | CEC_FLAG_REOM  | CEC_FLAG_RBTF);
00439   }
00440
00441   /********************** Transmission ******************************************/
00442   /* Check if a transmission error occured */
00443   if (CEC_GetFlagStatus(CEC_FLAG_TERR))
00444   {
00445     TransErrorCode = HDMI_CEC_GetErrorStatus();
00446     CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR);
00447     SendFrame = 1;
00448     SendStatus = 0;
00449   }
00450   /* Check if end of message bit is set in the data to be transmitted */
00451   else if (CEC_GetFlagStatus(CEC_FLAG_TEOM))
00452   {
00453     CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_RBTF);
00454     CEC_EndOfMessageCmd(DISABLE);
00455     SendFrame = 1;
00456     SendStatus = SUCCESS;
00457   }
00458   /* Check if data byte has been sent */
00459   else if (CEC_GetFlagStatus(CEC_FLAG_TBTRF))
00460   {
00461     /* Set EOM bit if the byte to be transmitted is the last one of the TransmitBuffer */
00462     if (TxCounter == (HDMI_CEC_TX_MessageStructPrivate.TxMessageLength))
00463     {
00464       CEC_SendDataByte(BufferPointer[TxCounter]);
00465       TxCounter++;
00466       CEC_ClearFlag(CEC_FLAG_TBTRF);
00467       CEC_EndOfMessageCmd(ENABLE);
00468     }
00469     else
00470     {
00471       /* Put the byte in the TX Buffer */
00472       CEC_SendDataByte(BufferPointer[TxCounter]);
00473       TxCounter++;
00474       CEC_ClearFlag(CEC_FLAG_TBTRF);
00475     }
00476   }
00477 }
00478
00479 /**
00480   * @brief  Report physical address to all other devices thus allowing any
00481             device to create a map of the network.
00482   * @param  None
00483   * @retval HDMI_CEC_Error: CEC Error code.
00484   */
00485 HDMI_CEC_Error HDMI_CEC_ReportPhysicalAddress(void)
00486 {
00487   HDMI_CEC_Error errorstatus = HDMI_CEC_OK;
00488   HDMI_CEC_Message HDMI_CEC_TX_Message;
00489
00490   HDMI_CEC_TX_Message.Header = ((MyLogicalAddress << 4) | 0xF);
00491   HDMI_CEC_TX_Message.Opcode = HDMI_CEC_OPCODE_REPORT_PHYSICAL_ADDRESS;
00492   HDMI_CEC_TX_Message.Operande[0] = MyPhysicalAddress >> 8;
00493   HDMI_CEC_TX_Message.Operande[1] = MyPhysicalAddress & 0xFF;
00494   HDMI_CEC_TX_Message.Operande[2] = DeviceType;
00495   HDMI_CEC_TX_Message.TxMessageLength = 0x03;
00496
00497   errorstatus = HDMI_CEC_TransmitMessage(&HDMI_CEC_TX_Message);
00498
00499   return  errorstatus;
00500 }
00501
00502 /**
00503   * @brief  Handle CEC command receive callback.
00504   *         When receiving the STANDBY Opcode commande, the system is entred in
00505   *         Stop mode and when wakeup, the PLL is configured as system clock and
00506   *         the HSI is selected as PLL source.
00507   * @param  None
00508   * @retval None
00509   */
00510 void HDMI_CEC_CommandCallBack(void)
00511 {
00512   uint8_t i = 0, sendcount = 0;
00513   HDMI_CEC_Error errorstatus = HDMI_CEC_OK;
00514   EXTI_InitTypeDef EXTI_InitStructure;
00515
00516   switch (HDMI_CEC_RX_MessageStructPrivate.Opcode)
00517   {
00518     case HDMI_CEC_OPCODE_REPORT_PHYSICAL_ADDRESS:
00519       HDMI_CEC_MapStruct.PhysicalAddress_A = HDMI_CEC_RX_MessageStructPrivate.Operande[1] >> 4;
00520       HDMI_CEC_MapStruct.PhysicalAddress_B = HDMI_CEC_RX_MessageStructPrivate.Operande[1] & 0x0F;
00521       HDMI_CEC_MapStruct.PhysicalAddress_C = HDMI_CEC_RX_MessageStructPrivate.Operande[0] >> 4;
00522       HDMI_CEC_MapStruct.PhysicalAddress_D = HDMI_CEC_RX_MessageStructPrivate.Operande[0] & 0x0F;
00523       HDMI_CEC_MapStruct.LogicalAddress = (HDMI_CEC_RX_MessageStructPrivate.Header >> 0x4) & 0x0F;
00524       HDMI_CEC_MapStruct.DeviceType = HDMI_CEC_RX_MessageStructPrivate.Operande[2];
00525       HDMI_CEC_DeviceMap[DeviceCount] = HDMI_CEC_MapStruct;
00526       HDMI_CEC_Follower_String[(HDMI_CEC_DeviceMap[DeviceCount].LogicalAddress)][1] = (uint8_t*)"1";
00527       DeviceCount++;
00528       break;
00529
00530     case HDMI_CEC_OPCODE_STANDBY:
00531       /* CEC Line */
00532       GPIO_EXTILineConfig(GPIO_PortSourceGPIOB, GPIO_PinSource8);
00533       /* Configure the CEC Line as EXTI Line on Falling Edge */
00534       EXTI_ClearITPendingBit(EXTI_Line8);
00535       EXTI_InitStructure.EXTI_Line = EXTI_Line8;
00536       EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
00537       EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling;
00538       EXTI_InitStructure.EXTI_LineCmd = ENABLE;
00539       EXTI_Init(&EXTI_InitStructure);
00540       /* Request to enter Stop mode */
00541       PWR_EnterSTOPMode(PWR_Regulator_ON, PWR_STOPEntry_WFI);
00542
00543       /* Disable the CEC EXTI Line */
00544       EXTI_InitStructure.EXTI_LineCmd = DISABLE;
00545       EXTI_Init(&EXTI_InitStructure);
00546       /* Configure the PLL Source */
00547       RCC_PLLConfig(RCC_PLLSource_HSI_Div2, RCC_PLLMul_6);
00548
00549       /* Enable PLL */
00550       RCC_PLLCmd(ENABLE);
00551
00552       /* Wait till PLL is ready */
00553       while(RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET)
00554       {
00555       }
00556
00557       /* Select PLL as system clock source */
00558       RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
00559
00560       /* Wait till PLL is used as system clock source */
00561       while(RCC_GetSYSCLKSource() != 0x08)
00562       {
00563       }
00564       break;
00565
00566     case HDMI_CEC_OPCODE_GET_CEC_VERSION:
00567       /* Send the Used CEC version */
00568       HDMI_CEC_TX_MessageStructPrivate.Header = ((MyLogicalAddress << 4) | HDMI_CEC_RX_MessageStructPrivate.Header >> 4);
00569       HDMI_CEC_TX_MessageStructPrivate.Opcode = HDMI_CEC_OPCODE_CEC_VERSION;
00570       HDMI_CEC_TX_MessageStructPrivate.Operande[0] = HDMI_CEC_VERSION; /* CEC Version */
00571       HDMI_CEC_TX_MessageStructPrivate.TxMessageLength = 0x01;
00572       errorstatus = HDMI_CEC_TransmitMessage(&HDMI_CEC_TX_MessageStructPrivate);
00573
00574       /* Retransmit message until 5 time */
00575       while ((errorstatus != HDMI_CEC_OK) && sendcount < 0x5)
00576       {
00577         sendcount++;
00578         errorstatus = HDMI_CEC_TransmitMessage(&HDMI_CEC_TX_MessageStructPrivate);
00579       }
00580       break;
00581
00582     case HDMI_CEC_OPCODE_GIVE_PHYSICAL_ADDRESS:
00583       /* Send the Physical address */
00584       errorstatus = HDMI_CEC_ReportPhysicalAddress();
00585       sendcount = 0;
00586       /* Retransmit message until 5 time */
00587       while ((errorstatus != HDMI_CEC_OK) && sendcount < 0x5)
00588       {
00589         sendcount++;
00590         errorstatus = HDMI_CEC_ReportPhysicalAddress();
00591       }
00592       break;
00593
00594     case HDMI_CEC_OPCODE_FEATURE_ABORT:
00595       /* The device doesn't support the requested message type, or that it cannot
00596       execute it at the present time. */
00597       FeatureOpcode = HDMI_CEC_RX_MessageStructPrivate.Operande[0];
00598       AbortReason = HDMI_CEC_RX_MessageStructPrivate.Operande[1];
00599       break;
00600
00601     case HDMI_CEC_OPCODE_GIVE_OSD_NAME:
00602       /* Send the OSD name = STM32100E CEC*/
00603       HDMI_CEC_TX_MessageStructPrivate.Header = ((MyLogicalAddress << 4) | HDMI_CEC_RX_MessageStructPrivate.Header >> 4);
00604       HDMI_CEC_TX_MessageStructPrivate.Opcode = HDMI_CEC_OPCODE_SET_OSD_NAME;
00605       /* STM32100E*/
00606       HDMI_CEC_TX_MessageStructPrivate.Operande[0] = 0x53;
00607       HDMI_CEC_TX_MessageStructPrivate.Operande[1] = 0x54;
00608       HDMI_CEC_TX_MessageStructPrivate.Operande[2] = 0x4D;
00609       HDMI_CEC_TX_MessageStructPrivate.Operande[3] = 0x33;
00610       HDMI_CEC_TX_MessageStructPrivate.Operande[4] = 0x32;
00611       HDMI_CEC_TX_MessageStructPrivate.Operande[5] = 0x31;
00612       HDMI_CEC_TX_MessageStructPrivate.Operande[6] = 0x30;
00613       HDMI_CEC_TX_MessageStructPrivate.Operande[7] = 0x30;
00614       HDMI_CEC_TX_MessageStructPrivate.Operande[8] = 0x45;
00615       HDMI_CEC_TX_MessageStructPrivate.Operande[9] = 0x20;
00616       /* CEC */
00617       HDMI_CEC_TX_MessageStructPrivate.Operande[10] = 0x43;
00618       HDMI_CEC_TX_MessageStructPrivate.Operande[11] = 0x45;
00619       HDMI_CEC_TX_MessageStructPrivate.Operande[12] = 0x43;
00620       HDMI_CEC_TX_MessageStructPrivate.TxMessageLength = 13;
00621       errorstatus = HDMI_CEC_TransmitMessage(&HDMI_CEC_TX_MessageStructPrivate);
00622       sendcount = 0;
00623       /* Retransmit message until 5 time */
00624       while ((errorstatus != HDMI_CEC_OK) && sendcount < 0x5)
00625       {
00626         sendcount++;
00627         errorstatus = HDMI_CEC_TransmitMessage(&HDMI_CEC_TX_MessageStructPrivate);
00628       }
00629       break;
00630
00631     case HDMI_CEC_OPCODE_ROUTING_CHANGE:
00632       for (i = 0;i < 0x14;i++)
00633       {
00634         if ((HDMI_CEC_DeviceMap[i].PhysicalAddress_A == HDMI_CEC_RX_MessageStructPrivate.Operande[1] >> 4) &&
00635             (HDMI_CEC_DeviceMap[i].PhysicalAddress_B == HDMI_CEC_RX_MessageStructPrivate.Operande[1]&0x0F) &&
00636             (HDMI_CEC_DeviceMap[i].PhysicalAddress_C == HDMI_CEC_RX_MessageStructPrivate.Operande[0] >> 4) &&
00637             (HDMI_CEC_DeviceMap[i].PhysicalAddress_D == HDMI_CEC_RX_MessageStructPrivate.Operande[0]&0x0F))
00638         {
00639           HDMI_CEC_MapStruct.LogicalAddress = (HDMI_CEC_RX_MessageStructPrivate.Header >> 0x4) & 0x0F;
00640           HDMI_CEC_MapStruct.DeviceType = HDMI_CEC_RX_MessageStructPrivate.Operande[2];
00641           HDMI_CEC_DeviceMap[i] = HDMI_CEC_MapStruct;
00642         }
00643       }
00644       break;
00645
00646     default:
00647       /* Send Abort feature*/
00648       HDMI_CEC_TX_MessageStructPrivate.Header = ((MyLogicalAddress << 4) | HDMI_CEC_RX_MessageStructPrivate.Header >> 4);
00649       HDMI_CEC_TX_MessageStructPrivate.Opcode = HDMI_CEC_OPCODE_FEATURE_ABORT;
00650       HDMI_CEC_TX_MessageStructPrivate.Operande[0] = 0x02; /* defines command to be performed */
00651       HDMI_CEC_TX_MessageStructPrivate.Operande[1] = HDMI_CEC_REFUSED; /* Reason for abort feature */
00652       HDMI_CEC_TX_MessageStructPrivate.TxMessageLength = 0x02;
00653       errorstatus = HDMI_CEC_TransmitMessage(&HDMI_CEC_TX_MessageStructPrivate);
00654       sendcount = 0;
00655       /* Retransmit message until 5 time */
00656       while ((errorstatus != HDMI_CEC_OK) && sendcount < 0x5)
00657       {
00658         sendcount++;
00659         errorstatus = HDMI_CEC_TransmitMessage(&HDMI_CEC_TX_MessageStructPrivate);
00660       }
00661       break;
00662
00663   }
00664 }
00665
00666 /**
00667   * @brief  Check the connected CEC devices.
00668   * @param  None
00669   * @retval HDMI_CEC_Error
00670   */
00671 HDMI_CEC_Error HDMI_CEC_CheckConnectedDevices(void)
00672 {
00673   HDMI_CEC_Error errorstatus = HDMI_CEC_OK;
00674   uint32_t count = 0, i = 1;
00675
00676   /*----------------------------- TV device  ---------------------------*/
00677   CEC_OwnAddressConfig(MyLogicalAddress); /* Own address = MyLogicalAddress */
00678
00679   CEC_EndOfMessageCmd(ENABLE);
00680
00681   CEC_SendDataByte((MyLogicalAddress << 4) | 0x0);
00682
00683   /* Start of message */
00684   CEC_StartOfMessage();
00685
00686   /* Wait till the header message is sent */
00687   while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
00688   {
00689     count++;
00690   }
00691
00692   if (count >= HDMI_CEC_TIMEOUT_VALUE)
00693   {
00694     errorstatus = HDMI_CEC_TIMEOUT;
00695     return(errorstatus);
00696   }
00697
00698   errorstatus = HDMI_CEC_GetErrorStatus();
00699
00700   if (errorstatus == HDMI_CEC_OK)
00701   {
00702     HDMI_CEC_Follower_String[0][1] = (uint8_t*)"1";
00703     i++;
00704     errorstatus = HDMI_CEC_OK;
00705   }
00706
00707   /* Clear CEC CSR register */
00708   CEC_ClearFlag(CEC_FLAG_TBTRF);
00709   CEC_EndOfMessageCmd(DISABLE);
00710
00711   /*----------------------------- Recording device 1 ---------------------------*/
00712   CEC_OwnAddressConfig(MyLogicalAddress); /* Own address = MyLogicalAddress */
00713
00714   CEC_EndOfMessageCmd(ENABLE);
00715
00716   CEC_SendDataByte((MyLogicalAddress << 4) | 0x1);
00717
00718   /* Start of message */
00719   CEC_StartOfMessage();
00720
00721   /* Wait till the header message is sent */
00722   while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
00723   {
00724     count++;
00725   }
00726
00727   if (count >= HDMI_CEC_TIMEOUT_VALUE)
00728   {
00729     errorstatus = HDMI_CEC_TIMEOUT;
00730     return(errorstatus);
00731   }
00732
00733   errorstatus = HDMI_CEC_GetErrorStatus();
00734
00735   if (errorstatus == HDMI_CEC_OK)
00736   {
00737     HDMI_CEC_Follower_String[1][1] = (uint8_t*)"1";
00738     i++;
00739     errorstatus = HDMI_CEC_OK;
00740   }
00741
00742   /* Clear CEC CSR register */
00743   CEC_ClearFlag(CEC_FLAG_TBTRF);
00744   CEC_EndOfMessageCmd(DISABLE);
00745   /*----------------------------- Recording device 2 ---------------------------*/
00746   CEC_OwnAddressConfig(MyLogicalAddress); /* Own address = MyLogicalAddress */
00747
00748   CEC_EndOfMessageCmd(ENABLE);
00749
00750   CEC_SendDataByte((MyLogicalAddress << 4) | 0x2);
00751
00752   /* Start of message */
00753   CEC_StartOfMessage();
00754
00755   /* Wait till the header message is sent */
00756   while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
00757   {
00758     count++;
00759   }
00760
00761   if (count >= HDMI_CEC_TIMEOUT_VALUE)
00762   {
00763     errorstatus = HDMI_CEC_TIMEOUT;
00764     return(errorstatus);
00765   }
00766
00767   errorstatus = HDMI_CEC_GetErrorStatus();
00768
00769   if (errorstatus == HDMI_CEC_OK)
00770   {
00771     HDMI_CEC_Follower_String[2][1] = (uint8_t*)"1";
00772     i++;
00773     errorstatus = HDMI_CEC_OK;
00774   }
00775
00776   /* Clear CEC CSR register */
00777   CEC_ClearFlag(CEC_FLAG_TBTRF);
00778   CEC_EndOfMessageCmd(DISABLE);
00779
00780   /*----------------------------- Tuner 1 ---------------------------*/
00781   CEC_OwnAddressConfig(MyLogicalAddress); /* Own address = MyLogicalAddress */
00782
00783   CEC_EndOfMessageCmd(ENABLE);
00784
00785   CEC_SendDataByte((MyLogicalAddress << 4) | 0x3);
00786
00787   /* Start of message */
00788   CEC_StartOfMessage();
00789
00790   /* Wait till the header message is sent */
00791   while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
00792   {
00793     count++;
00794   }
00795
00796   if (count >= HDMI_CEC_TIMEOUT_VALUE)
00797   {
00798     errorstatus = HDMI_CEC_TIMEOUT;
00799     return(errorstatus);
00800   }
00801
00802   errorstatus = HDMI_CEC_GetErrorStatus();
00803
00804   if (errorstatus == HDMI_CEC_OK)
00805   {
00806     HDMI_CEC_Follower_String[3][1] = (uint8_t *)"1";
00807     i++;
00808     errorstatus = HDMI_CEC_OK;
00809   }
00810   /* Clear CEC CSR register */
00811   CEC_ClearFlag(CEC_FLAG_TBTRF);
00812   CEC_EndOfMessageCmd(DISABLE);
00813   /*----------------------------- Playback device 1 ---------------------------*/
00814   CEC_OwnAddressConfig(MyLogicalAddress); /* Own address = MyLogicalAddress */
00815
00816   CEC_EndOfMessageCmd(ENABLE);
00817
00818   CEC_SendDataByte((MyLogicalAddress << 4) | 0x4);
00819
00820   /* Start of message */
00821   CEC_StartOfMessage();
00822
00823   /* Wait till the header message is sent */
00824   while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
00825   {
00826     count++;
00827   }
00828
00829   if (count >= HDMI_CEC_TIMEOUT_VALUE)
00830   {
00831     errorstatus = HDMI_CEC_TIMEOUT;
00832     return(errorstatus);
00833   }
00834
00835   errorstatus = HDMI_CEC_GetErrorStatus();
00836
00837   if (errorstatus == HDMI_CEC_OK)
00838   {
00839     HDMI_CEC_Follower_String[4][1] = (uint8_t *)"1";
00840     i++;
00841     errorstatus = HDMI_CEC_OK;
00842   }
00843   /* Clear CEC CSR register */
00844   CEC_ClearFlag(CEC_FLAG_TBTRF);
00845   CEC_EndOfMessageCmd(DISABLE);
00846
00847   /*----------------------------- Audio system ---------------------------*/
00848   CEC_OwnAddressConfig(MyLogicalAddress); /* Own address = MyLogicalAddress */
00849
00850   CEC_EndOfMessageCmd(ENABLE);
00851
00852   CEC_SendDataByte((MyLogicalAddress << 4) | 0x5);
00853
00854   /* Start of message */
00855   CEC_StartOfMessage();
00856
00857   /* Wait till the header message is sent */
00858   while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
00859   {
00860     count++;
00861   }
00862
00863   if (count >= HDMI_CEC_TIMEOUT_VALUE)
00864   {
00865     errorstatus = HDMI_CEC_TIMEOUT;
00866     return(errorstatus);
00867   }
00868
00869   errorstatus = HDMI_CEC_GetErrorStatus();
00870
00871   if (errorstatus == HDMI_CEC_OK)
00872   {
00873     HDMI_CEC_Follower_String[5][1] = (uint8_t *)"1";
00874     i++;
00875     errorstatus = HDMI_CEC_OK;
00876   }
00877   /* Clear CEC CSR register */
00878   CEC_ClearFlag(CEC_FLAG_TBTRF);
00879   CEC_EndOfMessageCmd(DISABLE);
00880
00881   /*----------------------------- Tuner 2 ---------------------------*/
00882   CEC_OwnAddressConfig(MyLogicalAddress); /* Own address = MyLogicalAddress */
00883
00884   CEC_EndOfMessageCmd(ENABLE);
00885
00886   CEC_SendDataByte((MyLogicalAddress << 4) | 0x6);
00887
00888   /* Start of message */
00889   CEC_StartOfMessage();
00890
00891   /* Wait till the header message is sent */
00892   while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
00893   {
00894     count++;
00895   }
00896
00897   if (count >= HDMI_CEC_TIMEOUT_VALUE)
00898   {
00899     errorstatus = HDMI_CEC_TIMEOUT;
00900     return(errorstatus);
00901   }
00902
00903   errorstatus = HDMI_CEC_GetErrorStatus();
00904
00905   if (errorstatus == HDMI_CEC_OK)
00906   {
00907     HDMI_CEC_Follower_String[6][1] = (uint8_t *)"1";
00908     i++;
00909     errorstatus = HDMI_CEC_OK;
00910   }
00911   /* Clear CEC CSR register */
00912   CEC_ClearFlag(CEC_FLAG_TBTRF);
00913   CEC_EndOfMessageCmd(DISABLE);
00914
00915   /*----------------------------- Tuner 3 ---------------------------*/
00916   CEC_OwnAddressConfig(MyLogicalAddress); /* Own address = MyLogicalAddress */
00917
00918   CEC_EndOfMessageCmd(ENABLE);
00919
00920   CEC_SendDataByte((MyLogicalAddress << 4) | 0x7);
00921
00922   /* Start of message */
00923   CEC_StartOfMessage();
00924
00925   /* Wait till the header message is sent */
00926   while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
00927   {
00928     count++;
00929   }
00930
00931   if (count >= HDMI_CEC_TIMEOUT_VALUE)
00932   {
00933     errorstatus = HDMI_CEC_TIMEOUT;
00934     return(errorstatus);
00935   }
00936
00937   errorstatus = HDMI_CEC_GetErrorStatus();
00938
00939   if (errorstatus == HDMI_CEC_OK)
00940   {
00941     HDMI_CEC_Follower_String[7][1] = (uint8_t *)"1";
00942     i++;
00943     errorstatus = HDMI_CEC_OK;
00944   }
00945   /* Clear CEC CSR register */
00946   CEC_ClearFlag(CEC_FLAG_TBTRF);
00947   CEC_EndOfMessageCmd(DISABLE);
00948
00949   /*----------------------------- Playback device 2 ---------------------------*/
00950   CEC_OwnAddressConfig(MyLogicalAddress); /* Own address = MyLogicalAddress */
00951
00952   CEC_EndOfMessageCmd(ENABLE);
00953
00954   CEC_SendDataByte((MyLogicalAddress << 4) | 0x8);
00955
00956   /* Start of message */
00957   CEC_StartOfMessage();
00958
00959   /* Wait till the header message is sent */
00960   while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
00961   {
00962     count++;
00963   }
00964
00965   if (count >= HDMI_CEC_TIMEOUT_VALUE)
00966   {
00967     errorstatus = HDMI_CEC_TIMEOUT;
00968     return(errorstatus);
00969   }
00970
00971   errorstatus = HDMI_CEC_GetErrorStatus();
00972
00973   if (errorstatus == HDMI_CEC_OK)
00974   {
00975     HDMI_CEC_Follower_String[8][1] = (uint8_t *)"1";
00976     i++;
00977     errorstatus = HDMI_CEC_OK;
00978   }
00979   /* Clear CEC CSR register */
00980   CEC_ClearFlag(CEC_FLAG_TBTRF);
00981   CEC_EndOfMessageCmd(DISABLE);
00982
00983   /*----------------------------- Recording device 3 ---------------------------*/
00984   CEC_OwnAddressConfig(MyLogicalAddress); /* Own address = MyLogicalAddress */
00985
00986   CEC_EndOfMessageCmd(ENABLE);
00987
00988   CEC_SendDataByte((MyLogicalAddress << 4) | 0x9);
00989
00990   /* Start of message */
00991   CEC_StartOfMessage();
00992
00993   /* Wait till the header message is sent */
00994   while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
00995   {
00996     count++;
00997   }
00998
00999   if (count >= HDMI_CEC_TIMEOUT_VALUE)
01000   {
01001     errorstatus = HDMI_CEC_TIMEOUT;
01002     return(errorstatus);
01003   }
01004
01005   errorstatus = HDMI_CEC_GetErrorStatus();
01006
01007   if (errorstatus == HDMI_CEC_OK)
01008   {
01009     HDMI_CEC_Follower_String[9][1] = (uint8_t *)"1";
01010     i++;
01011     errorstatus = HDMI_CEC_OK;
01012   }
01013   /* Clear CEC CSR register */
01014   CEC_ClearFlag(CEC_FLAG_TBTRF);
01015   CEC_EndOfMessageCmd(DISABLE);
01016   /*----------------------------- Tuner 4 ---------------------------*/
01017   CEC_OwnAddressConfig(MyLogicalAddress); /* Own address = MyLogicalAddress */
01018
01019   CEC_EndOfMessageCmd(ENABLE);
01020
01021   CEC_SendDataByte((MyLogicalAddress << 4) | 0xA);
01022
01023   /* Start of message */
01024   CEC_StartOfMessage();
01025
01026   /* Wait till the header message is sent */
01027   while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
01028   {
01029     count++;
01030   }
01031
01032   if (count >= HDMI_CEC_TIMEOUT_VALUE)
01033   {
01034     errorstatus = HDMI_CEC_TIMEOUT;
01035     return(errorstatus);
01036   }
01037
01038   errorstatus = HDMI_CEC_GetErrorStatus();
01039
01040   if (errorstatus == HDMI_CEC_OK)
01041   {
01042     HDMI_CEC_Follower_String[10][1] = (uint8_t *)"1";
01043     i++;
01044     errorstatus = HDMI_CEC_OK;
01045   }
01046   /* Clear CEC CSR register */
01047   CEC_ClearFlag(CEC_FLAG_TBTRF);
01048   CEC_EndOfMessageCmd(DISABLE);
01049   /*----------------------------- Playback device 3 ---------------------------*/
01050   CEC_OwnAddressConfig(MyLogicalAddress); /* Own address = MyLogicalAddress */
01051
01052   CEC_EndOfMessageCmd(ENABLE);
01053
01054   CEC_SendDataByte((MyLogicalAddress << 4) | 0xB);
01055
01056   /* Start of message */
01057   CEC_StartOfMessage();
01058
01059   /* Wait till the header message is sent */
01060   while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
01061   {
01062     count++;
01063   }
01064
01065   if (count >= HDMI_CEC_TIMEOUT_VALUE)
01066   {
01067     errorstatus = HDMI_CEC_TIMEOUT;
01068     return(errorstatus);
01069   }
01070
01071   errorstatus = HDMI_CEC_GetErrorStatus();
01072
01073   if (errorstatus == HDMI_CEC_OK)
01074   {
01075     HDMI_CEC_Follower_String[11][1] = (uint8_t *)"1";
01076     i++;
01077     errorstatus = HDMI_CEC_OK;
01078   }
01079   /* Clear CEC CSR register */
01080   CEC_ClearFlag(CEC_FLAG_TBTRF);
01081   CEC_EndOfMessageCmd(DISABLE);
01082
01083   CECDevicesNumber = i - 1;
01084
01085   return errorstatus;
01086 }
01087
01088 /**
01089   * @brief  Physical address discovery.
01090   * @param  None
01091   * @retval HDMI_CEC_Error: CEC Error code.
01092   */
01093 static HDMI_CEC_Error PhysicalAddressDiscovery(void)
01094 {
01095   HDMI_CEC_Error errorstatus = HDMI_CEC_OK;
01096 #ifdef HDMI_CEC_USE_DDC
01097   uint32_t index = 0, i = 0;
01098 #endif
01099
01100   /*------------------------------ Physical address discovery -----------------*/
01101   if (HDMI_CEC_ROOT == 0x1)
01102   {
01103     MyPhysicalAddress = 0x0000;
01104     /* The HDMI-CEC here is configured as sink or as a repeater. The configuration
01105        of the +5V power signal and the HPD should be well configured.
01106        Implement here the EDID Structure to be sent to the HDMI source.
01107        For more details please refer to the HDMI specification.
01108        The EDID structure should be sent to the device source using the DDC Channel
01109        and using the HPD signal. */
01110   }
01111   else
01112   {
01113
01114 #ifdef HDMI_CEC_USE_DDC
01115     /* The HDMI-CEC here is configured as source or as a repeater. The configuration
01116        of the +5V power signal and the HPD should be well configured.
01117        The source should wait for HPD and then read the EDID structure. */
01118     while(GPIO_ReadInputDataBit(HDMI_CEC_HPD_GPIO_PORT, HDMI_CEC_HPD_PIN) == RESET)
01119     {
01120     }
01121     /* Wait for 100 ms after HPD was received */
01122     for(i = 0; i < 0x5FFFF; i++)
01123     {
01124     }
01125
01126     /* Return the physical address using the I2C  by reading the 2 bytes 24 and
01127       25 form the EDID */
01128     /* Read the EDID Block 0 and EDID Block 1 at address 0xA0 */
01129     /*!< While the bus is busy */
01130     while(I2C_GetFlagStatus(HDMI_CEC_I2C, I2C_FLAG_BUSY))
01131     {
01132     }
01133
01134     /*!< Send START condition */
01135     I2C_GenerateSTART(HDMI_CEC_I2C, ENABLE);
01136
01137     /*!< Test on EV5 and clear it */
01138     while(!I2C_CheckEvent(HDMI_CEC_I2C, I2C_EVENT_MASTER_MODE_SELECT))
01139     {
01140     }
01141
01142     /*!< Send EEPROM address for write */
01143     I2C_Send7bitAddress(HDMI_CEC_I2C, 0xA0, I2C_Direction_Transmitter);
01144
01145
01146     /*!< Test on EV6 and clear it */
01147     while(!I2C_CheckEvent(HDMI_CEC_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED))
01148     {
01149     }
01150
01151     /*!< Send the EEPROM's internal address to read from: Only one byte address */
01152     I2C_SendData(HDMI_CEC_I2C, 0x00);
01153
01154     /*!< Test on EV8 and clear it */
01155     while(!I2C_CheckEvent(HDMI_CEC_I2C, I2C_EVENT_MASTER_BYTE_TRANSMITTED))
01156     {
01157     }
01158
01159     /*!< Send STRAT condition a second time */
01160     I2C_GenerateSTART(HDMI_CEC_I2C, ENABLE);
01161
01162     /*!< Test on EV5 and clear it */
01163     while(!I2C_CheckEvent(HDMI_CEC_I2C, I2C_EVENT_MASTER_MODE_SELECT))
01164     {
01165     }
01166
01167     /*!< Send EEPROM address for read */
01168     I2C_Send7bitAddress(HDMI_CEC_I2C, 0xA1, I2C_Direction_Receiver);
01169
01170     /*!< Test on EV6 and clear it */
01171     while(!I2C_CheckEvent(HDMI_CEC_I2C, I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED))
01172     {
01173     }
01174
01175     /* While there is data to be read */
01176     while (NumByteToRead-- > 1)
01177     {
01178       while(I2C_CheckEvent(HDMI_CEC_I2C, I2C_EVENT_MASTER_BYTE_RECEIVED))
01179       {
01180       }
01181       for(i = 0; i < 0xFFF; i++)
01182       {
01183       }
01184       pBuffer[index++] = I2C_ReceiveData(HDMI_CEC_I2C);
01185     }
01186
01187     /* Disable Acknowledgement */
01188     I2C_AcknowledgeConfig(HDMI_CEC_I2C, DISABLE);
01189
01190     /* Send STOP Condition */
01191     I2C_GenerateSTOP(HDMI_CEC_I2C, ENABLE);
01192
01193     while(I2C_CheckEvent(HDMI_CEC_I2C, I2C_EVENT_MASTER_BYTE_RECEIVED));
01194     pBuffer[index] = I2C_ReceiveData(HDMI_CEC_I2C);
01195
01196     /* Enable Acknowledgement to be ready for another reception */
01197     I2C_AcknowledgeConfig(HDMI_CEC_I2C, ENABLE);
01198     MyPhysicalAddress = ((pBuffer[138] << 8) | pBuffer[137]);
01199 #else
01200     MyPhysicalAddress = 0x1000;
01201 #endif
01202   }
01203
01204   return errorstatus;
01205 }
01206 /**
01207   * @brief  Allocate the logical address.
01208   * @param  None
01209   * @retval HDMI_CEC_Error: CEC Error code.
01210   */
01211 static HDMI_CEC_Error LogicalAddressAllocation(void)
01212 {
01213   HDMI_CEC_Error errorstatus = HDMI_CEC_OK;
01214   uint32_t count = 0;
01215
01216   /*------------------ Logical address allocation -----------------------------*/
01217   /* Get the device type */
01218   /* Device type = CEC_TV */
01219   if (DeviceType == HDMI_CEC_TV)
01220   {
01221     if (HDMI_CEC_ROOT)
01222     {
01223       MyLogicalAddress = 0x00;
01224     }
01225     else
01226     {
01227       CEC_OwnAddressConfig(0xE); /* Own address = 0xE */
01228
01229       CEC_EndOfMessageCmd(ENABLE);
01230
01231       CEC_SendDataByte(0xEE);
01232
01233       /* Start of message */
01234       CEC_StartOfMessage();
01235
01236       /* Wait till the polling message is sent */
01237       while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
01238       {
01239         count++;
01240       }
01241
01242       if (count >= HDMI_CEC_TIMEOUT_VALUE)
01243       {
01244         errorstatus = HDMI_CEC_TIMEOUT;
01245         return(errorstatus);
01246       }
01247
01248       errorstatus = HDMI_CEC_GetErrorStatus();
01249
01250       if (errorstatus == HDMI_CEC_BLOCK_ACKNOWLEDGE)
01251       {
01252         MyLogicalAddress = 0x0E;
01253         errorstatus = HDMI_CEC_OK;
01254       }
01255       else if (errorstatus == HDMI_CEC_OK)
01256       {
01257         MyLogicalAddress = 0x0F;
01258         errorstatus = HDMI_CEC_DEVICE_UNREGISTRED;
01259       }
01260     }
01261     /* Clear CEC CSR register */
01262     CEC_ClearFlag(CEC_FLAG_TBTRF);
01263     CEC_EndOfMessageCmd(DISABLE);
01264   }
01265
01266   /* Device type = CEC_RECORDING */
01267   if (DeviceType == HDMI_CEC_RECORDING)
01268   {
01269     CEC_OwnAddressConfig(0x1); /* Own address = 0x1 */
01270
01271     CEC_EndOfMessageCmd(ENABLE);
01272
01273     CEC_SendDataByte(0x11);
01274
01275     /* Start of message */
01276     CEC_StartOfMessage();
01277
01278     /* Wait till the header message is sent */
01279     while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
01280     {
01281       count++;
01282     }
01283
01284     if (count >= HDMI_CEC_TIMEOUT_VALUE)
01285     {
01286       errorstatus = HDMI_CEC_TIMEOUT;
01287       return(errorstatus);
01288     }
01289
01290     errorstatus = HDMI_CEC_GetErrorStatus();
01291
01292     if (errorstatus == HDMI_CEC_BLOCK_ACKNOWLEDGE)
01293     {
01294       MyLogicalAddress = 0x01;
01295       errorstatus = HDMI_CEC_OK;
01296     }
01297     else if (errorstatus == HDMI_CEC_OK)
01298     {
01299       /* Clear CEC CSR register */
01300       CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR);
01301
01302       CEC_EndOfMessageCmd(DISABLE);
01303
01304       CEC_OwnAddressConfig(0x2); /* Own address = 0x2 */
01305
01306       CEC_EndOfMessageCmd(ENABLE);
01307
01308       CEC_SendDataByte(0x22);
01309
01310       /* Start of message */
01311       CEC_StartOfMessage();
01312
01313       count = 0;
01314
01315       /* Wait till the header message is sent */
01316       while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
01317       {
01318         count++;
01319       }
01320
01321       if (count >= HDMI_CEC_TIMEOUT_VALUE)
01322       {
01323         errorstatus = HDMI_CEC_TIMEOUT;
01324         return(errorstatus);
01325       }
01326       errorstatus = HDMI_CEC_GetErrorStatus();
01327
01328       if (errorstatus == HDMI_CEC_BLOCK_ACKNOWLEDGE)
01329       {
01330         MyLogicalAddress = 0x02;
01331         errorstatus = HDMI_CEC_OK;
01332       }
01333       else if (errorstatus == HDMI_CEC_OK)
01334       {
01335         /* Clear CEC CSR register */
01336         CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR);
01337
01338         CEC_EndOfMessageCmd(DISABLE);
01339
01340         CEC_OwnAddressConfig(0x9); /* Own address = 0x9 */
01341
01342         CEC_EndOfMessageCmd(ENABLE);
01343
01344         CEC_SendDataByte(0x99);
01345
01346         /* Start of message */
01347         CEC_StartOfMessage();
01348
01349         count = 0;
01350
01351         /* Wait till the header message is sent */
01352         while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
01353         {
01354           count++;
01355         }
01356
01357         if (count >= HDMI_CEC_TIMEOUT_VALUE)
01358         {
01359           errorstatus = HDMI_CEC_TIMEOUT;
01360           return(errorstatus);
01361         }
01362         errorstatus = HDMI_CEC_GetErrorStatus();
01363
01364         if (errorstatus == HDMI_CEC_BLOCK_ACKNOWLEDGE)
01365         {
01366           MyLogicalAddress = 0x09;
01367           errorstatus = HDMI_CEC_OK;
01368         }
01369         else if (errorstatus == HDMI_CEC_OK)
01370         {
01371           MyLogicalAddress = 0x0F;
01372           errorstatus = HDMI_CEC_DEVICE_UNREGISTRED;
01373         }
01374       }
01375     }
01376     /* Clear CEC CSR register */
01377     CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR);
01378     CEC_EndOfMessageCmd(DISABLE);
01379   }
01380
01381   /* Device type = CEC_TUNER */
01382   if (DeviceType == HDMI_CEC_TUNER)
01383   {
01384     CEC_OwnAddressConfig(0x3); /* Own address = 0x3 */
01385
01386     CEC_EndOfMessageCmd(ENABLE);
01387
01388     CEC_SendDataByte(0x33);
01389
01390     /* Start of message */
01391     CEC_StartOfMessage();
01392
01393     count = 0;
01394
01395     /* Wait till the header message is sent */
01396     while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
01397     {
01398       count++;
01399     }
01400
01401     if (count >= HDMI_CEC_TIMEOUT_VALUE)
01402     {
01403       errorstatus = HDMI_CEC_TIMEOUT;
01404       return(errorstatus);
01405     }
01406     errorstatus = HDMI_CEC_GetErrorStatus();
01407
01408     if (errorstatus == HDMI_CEC_BLOCK_ACKNOWLEDGE)
01409     {
01410       MyLogicalAddress = 0x03;
01411       errorstatus = HDMI_CEC_OK;
01412     }
01413     else if (errorstatus == HDMI_CEC_OK)
01414     {
01415       /* Clear CEC CSR register */
01416       CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR);
01417
01418       CEC_EndOfMessageCmd(DISABLE);
01419
01420       CEC_OwnAddressConfig(0x6); /* Own address = 0x6 */
01421
01422       CEC_EndOfMessageCmd(ENABLE);
01423
01424       CEC_SendDataByte(0x66);
01425
01426       /* Start of message */
01427       CEC_StartOfMessage();
01428
01429       count = 0;
01430
01431       /* Wait till the header message is sent */
01432       while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
01433       {
01434         count++;
01435       }
01436
01437       if (count >= HDMI_CEC_TIMEOUT_VALUE)
01438       {
01439         errorstatus = HDMI_CEC_TIMEOUT;
01440         return(errorstatus);
01441       }
01442       errorstatus = HDMI_CEC_GetErrorStatus();
01443
01444       if (errorstatus == HDMI_CEC_BLOCK_ACKNOWLEDGE)
01445       {
01446         MyLogicalAddress = 0x06;
01447         errorstatus = HDMI_CEC_OK;
01448       }
01449       else if (errorstatus == HDMI_CEC_OK)
01450       {
01451         /* Clear CEC CSR register */
01452         CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR);
01453
01454         CEC_EndOfMessageCmd(DISABLE);
01455
01456         CEC_OwnAddressConfig(0x7); /* Own address = 0x7 */
01457
01458         CEC_EndOfMessageCmd(ENABLE);
01459
01460         CEC_SendDataByte(0x77);
01461
01462         /* Start of message */
01463         CEC_StartOfMessage();
01464
01465         count = 0;
01466
01467         /* Wait till the header message is sent */
01468         while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
01469         {
01470           count++;
01471         }
01472
01473         if (count >= HDMI_CEC_TIMEOUT_VALUE)
01474         {
01475           errorstatus = HDMI_CEC_TIMEOUT;
01476           return(errorstatus);
01477         }
01478         errorstatus = HDMI_CEC_GetErrorStatus();
01479
01480         if (errorstatus == HDMI_CEC_BLOCK_ACKNOWLEDGE)
01481         {
01482           MyLogicalAddress = 0x07;
01483           errorstatus = HDMI_CEC_OK;
01484         }
01485         else if (errorstatus == HDMI_CEC_OK)
01486         {
01487           /* Clear CEC CSR register */
01488           CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR);
01489
01490           CEC_EndOfMessageCmd(DISABLE);
01491
01492           CEC_OwnAddressConfig(0xA); /* Own address = 0xA */
01493
01494           CEC_EndOfMessageCmd(ENABLE);
01495
01496           CEC_SendDataByte(0xAA);
01497
01498           /* Start of message */
01499           CEC_StartOfMessage();
01500
01501           count = 0;
01502
01503           /* Wait till the header message is sent */
01504           while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
01505           {
01506             count++;
01507           }
01508
01509           if (count >= HDMI_CEC_TIMEOUT_VALUE)
01510           {
01511             errorstatus = HDMI_CEC_TIMEOUT;
01512             return(errorstatus);
01513           }
01514           errorstatus = HDMI_CEC_GetErrorStatus();
01515
01516           if (errorstatus == HDMI_CEC_BLOCK_ACKNOWLEDGE)
01517           {
01518             MyLogicalAddress = 0x0A;
01519             errorstatus = HDMI_CEC_OK;
01520           }
01521           else if (errorstatus == HDMI_CEC_OK)
01522           {
01523             MyLogicalAddress = 0x0F;
01524             errorstatus = HDMI_CEC_DEVICE_UNREGISTRED;
01525           }
01526         }
01527       }
01528     }
01529     /* Clear CEC CSR register */
01530     CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR);
01531     CEC_EndOfMessageCmd(DISABLE);
01532   }
01533
01534   /* Device type = CEC_PLAYBACK */
01535   if (DeviceType == HDMI_CEC_PLAYBACK)
01536   {
01537     CEC_OwnAddressConfig(0x4); /* Own address = 0x4 */
01538
01539     CEC_EndOfMessageCmd(ENABLE);
01540
01541     CEC_SendDataByte(0x44);
01542
01543     /* Start of message */
01544     CEC_StartOfMessage();
01545
01546     count = 0;
01547
01548     /* Wait till the header message is sent */
01549     while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
01550     {
01551       count++;
01552     }
01553
01554     if (count >= HDMI_CEC_TIMEOUT_VALUE)
01555     {
01556       errorstatus = HDMI_CEC_TIMEOUT;
01557       return(errorstatus);
01558     }
01559
01560     errorstatus = HDMI_CEC_GetErrorStatus();
01561
01562     if (errorstatus == HDMI_CEC_BLOCK_ACKNOWLEDGE)
01563     {
01564       MyLogicalAddress = 0x04;
01565       errorstatus = HDMI_CEC_OK;
01566     }
01567     else if (errorstatus == HDMI_CEC_OK)
01568     {
01569       /* Clear CEC CSR register */
01570       CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR);
01571
01572       CEC_EndOfMessageCmd(DISABLE);
01573
01574       CEC_OwnAddressConfig(0x8); /* Own address = 0x8 */
01575
01576       CEC_EndOfMessageCmd(ENABLE);
01577
01578       CEC_SendDataByte(0x88);
01579
01580       /* Start of message */
01581       CEC_StartOfMessage();
01582
01583       count = 0;
01584
01585       /* Wait till the header message is sent */
01586       while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
01587       {
01588         count++;
01589       }
01590
01591       if (count >= HDMI_CEC_TIMEOUT_VALUE)
01592       {
01593         errorstatus = HDMI_CEC_TIMEOUT;
01594         return(errorstatus);
01595       }
01596       errorstatus = HDMI_CEC_GetErrorStatus();
01597
01598       if (errorstatus == HDMI_CEC_BLOCK_ACKNOWLEDGE)
01599       {
01600         MyLogicalAddress = 0x08;
01601         errorstatus = HDMI_CEC_OK;
01602       }
01603       else if (errorstatus == HDMI_CEC_OK)
01604       {
01605         /* Clear CEC CSR register */
01606         CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR);
01607
01608         CEC_EndOfMessageCmd(DISABLE);
01609
01610         CEC_OwnAddressConfig(0xB); /* Own address = 0xBB */
01611
01612         CEC_EndOfMessageCmd(ENABLE);
01613
01614         CEC_SendDataByte(0xBB);
01615
01616         /* Start of message */
01617         CEC_StartOfMessage();
01618
01619         count = 0;
01620
01621         /* Wait till the header message is sent */
01622         while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
01623         {
01624           count++;
01625         }
01626
01627         if (count >= HDMI_CEC_TIMEOUT_VALUE)
01628         {
01629           errorstatus = HDMI_CEC_TIMEOUT;
01630           return(errorstatus);
01631         }
01632
01633         errorstatus = HDMI_CEC_GetErrorStatus();
01634
01635         if (errorstatus == HDMI_CEC_BLOCK_ACKNOWLEDGE)
01636         {
01637           MyLogicalAddress = 0x0B;
01638           errorstatus = HDMI_CEC_OK;
01639         }
01640         else if (errorstatus == HDMI_CEC_OK)
01641         {
01642           MyLogicalAddress = 0x0F;
01643           errorstatus = HDMI_CEC_DEVICE_UNREGISTRED;
01644         }
01645       }
01646     }
01647
01648     /* Clear CEC CSR register */
01649     CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR);
01650     CEC_EndOfMessageCmd(DISABLE);
01651   }
01652
01653   /* Device type = CEC Audio System */
01654   if (DeviceType == HDMI_CEC_AUDIOSYSTEM)
01655   {
01656     CEC_OwnAddressConfig(0x5); /* Own address = 0x5 */
01657
01658     CEC_EndOfMessageCmd(ENABLE);
01659
01660     CEC_SendDataByte(0x55);
01661
01662     /* Start of message */
01663     CEC_StartOfMessage();
01664
01665     count = 0;
01666
01667     /* Wait till the header message is sent */
01668     while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
01669     {
01670       count++;
01671     }
01672
01673     if (count >= HDMI_CEC_TIMEOUT_VALUE)
01674     {
01675       errorstatus = HDMI_CEC_TIMEOUT;
01676       return(errorstatus);
01677     }
01678
01679     errorstatus = HDMI_CEC_GetErrorStatus();
01680
01681     if (errorstatus == HDMI_CEC_BLOCK_ACKNOWLEDGE)
01682     {
01683       MyLogicalAddress = 0x05;
01684       errorstatus = HDMI_CEC_OK;
01685     }
01686     else if (errorstatus == HDMI_CEC_OK)
01687     {
01688       MyLogicalAddress = 0x0F;
01689       errorstatus = HDMI_CEC_DEVICE_UNREGISTRED;
01690     }
01691
01692     /* Clear CEC CSR register */
01693     CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR);
01694     CEC_EndOfMessageCmd(DISABLE);
01695   }
01696
01697   return errorstatus;
01698 }
01699
01700 /**
01701   * @}
01702   */
01703
01704 /**
01705   * @}
01706   */
01707
01708 /**
01709   * @}
01710   */
01711
01712 /**
01713   * @}
01714   */
01715
01716 /**
01717   * @}
01718   */
01719
01720 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
01721
01722


STM32F10x Standard Peripherals Firmware Library: stm32100e_eval_cec.h Source File

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • STM32100E_EVAL

stm32100e_eval_cec.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32100e_eval_cec.h
00004   * @author  MCD Application Team
00005   * @version V4.5.0
00006   * @date    07-March-2011
00007   * @brief   This file contains all the functions prototypes for the stm32100e_eval_cec
00008   *          firmware driver.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00013   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00014   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00015   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00016   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00017   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00018   *
00019   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00020   ******************************************************************************
00021   */
00022
00023 /* Define to prevent recursive inclusion -------------------------------------*/
00024 #ifndef __STM32100E_EVAL_CEC_H
00025 #define __STM32100E_EVAL_CEC_H
00026
00027 #ifdef __cplusplus
00028 extern "C"
00029 {
00030 #endif
00031
00032   /* Includes ------------------------------------------------------------------*/
00033 #include "stm32f10x.h"
00034
00035 /** @addtogroup Utilities
00036   * @{
00037   */
00038
00039 /** @addtogroup STM32_EVAL
00040   * @{
00041   */
00042
00043 /** @addtogroup STM32100E_EVAL
00044   * @{
00045   */
00046
00047 /** @defgroup STM32100E_EVAL_CEC
00048   * @{
00049   */
00050
00051 /** @defgroup STM32100E_EVAL_CEC_Exported_Types
00052   * @{
00053   */
00054 typedef enum
00055 {
00056   HDMI_CEC_BIT_TIMING              = (1), /*!< CEC Bit Timing Error */
00057   HDMI_CEC_BIT_PERIOD              = (2), /*!< CEC Bit Period Error */
00058   HDMI_CEC_RX_BLOCK_FINISHED       = (3), /*!< CEC Receive Block finished Error */
00059   HDMI_CEC_START_BIT               = (4), /*!< CEC Start Bit Error */
00060   HDMI_CEC_BLOCK_ACKNOWLEDGE       = (5), /*!< CEC Block Acknowledge Error */
00061   HDMI_CEC_LINE                    = (6), /*!< CEC Line Error */
00062   HDMI_CEC_TX_BLOCK_FINISHED       = (7), /*!< CEC Transmit Block Transfer finished Error */
00063   HDMI_CEC_DEVICE_UNREGISTRED      = (8), /*!< CEC Device Unregistred */
00064   HDMI_CEC_TIMEOUT                 = (9), /*!< CEC TimeOut */
00065   HDMI_CEC_OK                      = (10)  /*!< CEC OK */
00066 }HDMI_CEC_Error;
00067
00068 typedef struct
00069 {
00070   __IO uint8_t PhysicalAddress_A;
00071   __IO uint8_t PhysicalAddress_B;
00072   __IO uint8_t PhysicalAddress_C;
00073   __IO uint8_t PhysicalAddress_D;
00074   __IO uint8_t LogicalAddress;
00075   __IO uint8_t DeviceType;
00076 }HDMI_CEC_Map;
00077
00078
00079 #define HDMI_CEC_TX_MESSAGE_LENGTH_MAX       ((uint32_t)0x0000000E)
00080 #define HDMI_CEC_TIMEOUT_VALUE               ((uint32_t)0x001FFFFF)
00081
00082 /**
00083 * @brief  CEC Init Structure definition
00084 */
00085 typedef struct
00086 {
00087   __IO uint8_t Header;
00088   __IO uint8_t Opcode;
00089   __IO uint8_t Operande[HDMI_CEC_TX_MESSAGE_LENGTH_MAX];
00090   __IO uint8_t TxMessageLength;
00091   __IO uint8_t RxMessageLength;
00092 }HDMI_CEC_Message;
00093
00094 /**
00095 * @}
00096 */
00097
00098 /** @defgroup STM32100E_EVAL_CEC_Exported_Constants
00099   * @{
00100   */
00101
00102 /**
00103   * @brief CEC device types
00104   */
00105 #define HDMI_CEC_TV                                         0x00
00106 #define HDMI_CEC_RECORDING                                  0x01
00107 #define HDMI_CEC_TUNER                                      0x03
00108 #define HDMI_CEC_PLAYBACK                                   0x04
00109 #define HDMI_CEC_AUDIOSYSTEM                                0x05
00110
00111
00112 /**
00113   * @brief  HDMI CEC I2C Interface pins
00114   */
00115 #define HDMI_CEC_I2C_SCL_PIN                                GPIO_Pin_6
00116 #define HDMI_CEC_I2C_SDA_PIN                                GPIO_Pin_7
00117 #define HDMI_CEC_I2C_GPIO_PORT                              GPIOB
00118 #define HDMI_CEC_I2C_GPIO_CLK                               RCC_APB2Periph_GPIOB
00119 #define HDMI_CEC_I2C                                        I2C1
00120 #define HDMI_CEC_I2C_CLK                                    RCC_APB1Periph_I2C1
00121
00122 /**
00123   * @brief  HDMI CEC HPD (Hot Plug Detect) Interface pin
00124   */
00125 #define HDMI_CEC_HPD_PIN                                    GPIO_Pin_9
00126 #define HDMI_CEC_HPD_GPIO_PORT                              GPIOB
00127 #define HDMI_CEC_HPD_GPIO_CLK                               RCC_APB2Periph_GPIOB
00128
00129 /**
00130   * @brief  HDMI CEC Interface pin
00131   */
00132 #define HDMI_CEC_LINE_PIN                                   GPIO_Pin_8
00133 #define HDMI_CEC_LINE_GPIO_PORT                             GPIOB
00134 #define HDMI_CEC_LINE_GPIO_CLK                              RCC_APB2Periph_GPIOB
00135
00136 #define HDMI_CEC_I2C_SLAVE_ADDRESS7                         0xA0
00137 #define HDMI_CEC_I2C_CLOCK_SPEED                            100000
00138
00139 /**
00140   * @brief  HDMI CEC Root (Mainly for TV with a fixed physical address (0.0.0.0))
00141   *         If you want to configure the STM32100E-EVAL board as CEC Root (Sink)
00142   *         change the following define to 0x1
00143   */
00144 #define HDMI_CEC_ROOT                                       0x00
00145
00146 /**
00147   * @brief  To select if the DDC Channel will be used for physical address discovery
00148   *         or not. To use the DDC Channel to read the EDID structure uncomment
00149   *         the following line.
00150   *         If the device is configured as HMDI source it should read his own physical
00151   *         address from the sink that is connected to.
00152   */
00153 /* #define HDMI_CEC_USE_DDC */
00154
00155 /**
00156   * @brief  CEC version: V1.3a
00157   */
00158 #define HDMI_CEC_VERSION                                    0x04
00159
00160 /**
00161   * @brief  Reason for Abort feature
00162   */
00163 #define HDMI_CEC_UNRECOGNIZED_OPCODE                        0x00
00164 #define HDMI_CEC_NOT_CORRECT_MODETORESPOND                  0x01
00165 #define HDMI_CEC_CANNOTPROVIDE_SOURCE                       0x02
00166 #define HDMI_CEC_INVALID_OPERAND                            0x03
00167 #define HDMI_CEC_REFUSED                                    0x04
00168
00169 /**
00170   * @brief  HDMI CEC specific commands
00171   */
00172 #define HDMI_CEC_OPCODE_ACTIVE_SOURCE                       ((uint8_t) 0x82)
00173 #define HDMI_CEC_OPCODE_IMAGE_VIEW_ON                       ((uint8_t) 0x04)
00174 #define HDMI_CEC_OPCODE_TEXT_VIEW_ON                        ((uint8_t) 0x0D)
00175 #define HDMI_CEC_OPCODE_INACTIVE_SOURCE                     ((uint8_t) 0x9D)
00176 #define HDMI_CEC_OPCODE_REQUEST_ACTIVE_SOURCE               ((uint8_t) 0x85)
00177 #define HDMI_CEC_OPCODE_ROUTING_CHANGE                      ((uint8_t) 0x80)
00178 #define HDMI_CEC_OPCODE_ROUTING_INFORMATION                 ((uint8_t) 0x81)
00179 #define HDMI_CEC_OPCODE_SET_STREAM_PATH                     ((uint8_t) 0x86)
00180 #define HDMI_CEC_OPCODE_STANDBY                             ((uint8_t) 0x36)
00181 #define HDMI_CEC_OPCODE_RECORD_OFF                          ((uint8_t) 0x0B)
00182 #define HDMI_CEC_OPCODE_RECORD_ON                           ((uint8_t) 0x09)
00183 #define HDMI_CEC_OPCODE_RECORD_STATUS                       ((uint8_t) 0x0A)
00184 #define HDMI_CEC_OPCODE_RECORD_TV_SCREEN                    ((uint8_t) 0x0F)
00185 #define HDMI_CEC_OPCODE_CLEAR_ANALOGUE_TIMER                ((uint8_t) 0x33)
00186 #define HDMI_CEC_OPCODE_CLEAR_DIGITAL_TIMER                 ((uint8_t) 0x99)
00187 #define HDMI_CEC_OPCODE_CLEAR_EXTERNAL_TIMER                ((uint8_t) 0xA1)
00188 #define HDMI_CEC_OPCODE_SET_ANALOGUE_TIMER                  ((uint8_t) 0x34)
00189 #define HDMI_CEC_OPCODE_SET_DIGITAL_TIMER                   ((uint8_t) 0x97)
00190 #define HDMI_CEC_OPCODE_SET_EXTERNAL_TIMER                  ((uint8_t) 0xA2)
00191 #define HDMI_CEC_OPCODE_SET_TIMER_PROGRAM_TITLE             ((uint8_t) 0x67)
00192 #define HDMI_CEC_OPCODE_TIMER_CLEARED_STATUS                ((uint8_t) 0x43)
00193 #define HDMI_CEC_OPCODE_TIMER_STATUS                        ((uint8_t) 0x35)
00194 #define HDMI_CEC_OPCODE_CEC_VERSION                         ((uint8_t) 0x9E)
00195 #define HDMI_CEC_OPCODE_GET_CEC_VERSION                     ((uint8_t) 0x9F)
00196 #define HDMI_CEC_OPCODE_GIVE_PHYSICAL_ADDRESS               ((uint8_t) 0x83)
00197 #define HDMI_CEC_OPCODE_GET_MENU_LANGUAGE                   ((uint8_t) 0x91)
00198 #define HDMI_CEC_OPCODE_REPORT_PHYSICAL_ADDRESS             ((uint8_t) 0x84)
00199 #define HDMI_CEC_OPCODE_SET_MENU_LANGUAGE                   ((uint8_t) 0x32)
00200 #define HDMI_CEC_OPCODE_DECK_CONTROL                        ((uint8_t) 0x42)
00201 #define HDMI_CEC_OPCODE_DECK_STATUS                         ((uint8_t) 0x1B)
00202 #define HDMI_CEC_OPCODE_GIVE_DECK_STATUS                    ((uint8_t) 0x1A)
00203 #define HDMI_CEC_OPCODE_PLAY                                ((uint8_t) 0x41)
00204 #define HDMI_CEC_OPCODE_GIVE_TUNER_DEVICE_STATUS            ((uint8_t) 0x08)
00205 #define HDMI_CEC_OPCODE_SELECT_ANALOGUE_SERVICE             ((uint8_t) 0x92)
00206 #define HDMI_CEC_OPCODE_SELECT_DIGITAL_SERVICE              ((uint8_t) 0x93)
00207 #define HDMI_CEC_OPCODE_TUNER_DEVICE_STATUS                 ((uint8_t) 0x07)
00208 #define HDMI_CEC_OPCODE_TUNER_STEP_DECREMENT                ((uint8_t) 0x06)
00209 #define HDMI_CEC_OPCODE_TUNER_STEP_INCREMENT                ((uint8_t) 0x05)
00210 #define HDMI_CEC_OPCODE_DEVICE_VENDOR_ID                    ((uint8_t) 0x87)
00211 #define HDMI_CEC_OPCODE_GIVE_DEVICE_VENDOR_ID               ((uint8_t) 0x8C)
00212 #define HDMI_CEC_OPCODE_VENDOR_COMMAND                      ((uint8_t) 0x89)
00213 #define HDMI_CEC_OPCODE_VENDOR_COMMAND_WITH_ID              ((uint8_t) 0xA0)
00214 #define HDMI_CEC_OPCODE_VENDOR_REMOTE_BUTTON_DOWN           ((uint8_t) 0x8A)
00215 #define HDMI_CEC_OPCODE_VENDOR_REMOTE_BUTTON_UP             ((uint8_t) 0x8B)
00216 #define HDMI_CEC_OPCODE_SET_OSD_STRING                      ((uint8_t) 0x64)
00217 #define HDMI_CEC_OPCODE_GIVE_OSD_NAME                       ((uint8_t) 0x46)
00218 #define HDMI_CEC_OPCODE_SET_OSD_NAME                        ((uint8_t) 0x47)
00219 #define HDMI_CEC_OPCODE_MENU_REQUEST                        ((uint8_t) 0x8D)
00220 #define HDMI_CEC_OPCODE_MENU_STATUS                         ((uint8_t) 0x8E)
00221 #define HDMI_CEC_OPCODE_USER_CONTROL_PRESSED                ((uint8_t) 0x44)
00222 #define HDMI_CEC_OPCODE_USER_CONTROL_RELEASED               ((uint8_t) 0x45)
00223 #define HDMI_CEC_OPCODE_GIVE_DEVICE_POWER_STATUS            ((uint8_t) 0x8F)
00224 #define HDMI_CEC_OPCODE_REPORT_POWER_STATUS                 ((uint8_t) 0x90)
00225 #define HDMI_CEC_OPCODE_FEATURE_ABORT                       ((uint8_t) 0x00)
00226 #define HDMI_CEC_OPCODE_ABORT                               ((uint8_t) 0xFF)
00227 #define HDMI_CEC_OPCODE_GIVE_AUDIO_STATUS                   ((uint8_t) 0x71)
00228 #define HDMI_CEC_OPCODE_GIVE_SYSTEM_AUDIO_MODE_STATUS       ((uint8_t) 0x7D)
00229 #define HDMI_CEC_OPCODE_REPORT_AUDIO_STATUS                 ((uint8_t) 0x7A)
00230 #define HDMI_CEC_OPCODE_SET_SYSTEM_AUDIO_MODE               ((uint8_t) 0x72)
00231 #define HDMI_CEC_OPCODE_SYSTEM_AUDIO_MODE_REQUEST           ((uint8_t) 0x70)
00232 #define HDMI_CEC_OPCODE_SYSTEM_AUDIO_MODE_STATUS            ((uint8_t) 0x7E)
00233 #define HDMI_CEC_OPCODE_SET_AUDIO_RATE                      ((uint8_t) 0x9A)
00234
00235
00236 /**
00237   * @}
00238   */
00239
00240 /** @defgroup STM32100E_EVAL_CEC_Exported_Macros
00241   * @{
00242   */
00243 /* HDMI_CEC_HPD: HDMI HPD pin low  */
00244 #define HDMI_CEC_HPD_LOW()       GPIO_ResetBits(HDMI_CEC_HPD_GPIO_PORT, HDMI_CEC_HPD_PIN)
00245 /* HDMI_CEC_HPD: HDMI HPD pin high  */
00246 #define HDMI_CEC_HPD_HIGH()      GPIO_SetBits(HDMI_CEC_HPD_GPIO_PORT, HDMI_CEC_HPD_PIN)
00247
00248 /**
00249   * @}
00250   */
00251
00252 /** @defgroup STM32100E_EVAL_CEC_Exported_Functions
00253   * @{
00254   */
00255 HDMI_CEC_Error HDMI_CEC_Init(void);
00256 HDMI_CEC_Error HDMI_CEC_TransmitMessage(HDMI_CEC_Message *HDMI_CEC_TX_MessageStructure);
00257 HDMI_CEC_Error HDMI_CEC_GetErrorStatus (void);
00258 void HDMI_CEC_ProcessIRQSrc(void);
00259 HDMI_CEC_Error HDMI_CEC_ReportPhysicalAddress(void);
00260 void HDMI_CEC_CommandCallBack(void);
00261 HDMI_CEC_Error HDMI_CEC_CheckConnectedDevices(void);
00262
00263 #ifdef __cplusplus
00264 }
00265 #endif
00266
00267 #endif /* __STM32100E_EVAL_CEC_H */
00268
00269 /**
00270   * @}
00271   */
00272
00273 /**
00274   * @}
00275   */
00276
00277 /**
00278   * @}
00279   */
00280
00281 /**
00282   * @}
00283   */
00284
00285 /**
00286   * @}
00287   */
00288
00289 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
00290


STM32F10x Standard Peripherals Firmware Library: stm32100e_eval_fsmc_onenand.c Source File

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • STM32100E_EVAL

stm32100e_eval_fsmc_onenand.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32100e_eval_fsmc_onenand.c
00004   * @author  MCD Application Team
00005   * @version V4.5.0
00006   * @date    07-March-2011
00007   * @brief   This file provides a set of functions needed to drive the
00008   *          KFG1216U2A/B-DIB6 OneNAND memory mounted on STM32100E-EVAL board.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00013   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00014   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00015   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00016   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00017   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00018   *
00019   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00020   ******************************************************************************
00021   */
00022
00023 /* Includes ------------------------------------------------------------------*/
00024 #include "stm32100e_eval_fsmc_onenand.h"
00025
00026 /** @addtogroup Utilities
00027   * @{
00028   */
00029
00030 /** @addtogroup STM32_EVAL
00031   * @{
00032   */
00033
00034 /** @addtogroup STM32100E_EVAL
00035   * @{
00036   */
00037
00038 /** @addtogroup STM32100E_EVAL_FSMC_ONENAND
00039   * @brief      This file provides a set of functions needed to drive the
00040   *             KFG1216x2A-xxB5 OneNAND memory mounted on STM32100E-EVAL board.
00041   * @{
00042   */
00043
00044 /** @defgroup STM32100E_EVAL_FSMC_ONENAND_Private_Types
00045   * @{
00046   */
00047 /**
00048   * @}
00049   */
00050
00051
00052 /** @defgroup STM32100E_EVAL_FSMC_ONENAND_Private_Defines
00053   * @{
00054   */
00055 #define BANK1_ONENAND1_ADDR           ((uint32_t)0x60000000)
00056 #define ONENAND_BOOTPARTITION_ADDR    ((uint32_t)BANK1_ONENAND1_ADDR)
00057
00058
00059 /**
00060   * @}
00061   */
00062
00063 /** @defgroup STM32100E_EVAL_FSMC_ONENAND_Private_Macros
00064   * @{
00065   */
00066 #define OneNAND_WRITE(Address, Data)  (*(__IO uint16_t *)(Address) = (Data))
00067
00068 /**
00069   * @}
00070   */
00071
00072
00073 /** @defgroup STM32100E_EVAL_FSMC_ONENAND_Private_Variables
00074   * @{
00075   */
00076 /**
00077   * @}
00078   */
00079
00080
00081 /** @defgroup STM32100E_EVAL_FSMC_ONENAND_Private_Function_Prototypes
00082   * @{
00083   */
00084 /**
00085   * @}
00086   */
00087
00088
00089 /** @defgroup STM32100E_EVAL_FSMC_ONENAND_Private_Functions
00090   * @{
00091   */
00092
00093 /**
00094   * @brief  Configures the FSMC and GPIOs to interface with the OneNAND memory.
00095   *         This function must be called before any write/read operation on the
00096   *         OneNAND.
00097   * @param  None
00098   * @retval None
00099   */
00100 void OneNAND_Init(void)
00101 {
00102   FSMC_NORSRAMInitTypeDef  FSMC_NORSRAMInitStructure;
00103   FSMC_NORSRAMTimingInitTypeDef  p;
00104   GPIO_InitTypeDef GPIO_InitStructure;
00105
00106
00107   RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, ENABLE);
00108
00109 /*-- GPIO Configuration ------------------------------------------------------*/
00110   /* OneNAND Data lines configuration */
00111   RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOG | RCC_APB2Periph_GPIOE |
00112                          RCC_APB2Periph_GPIOF | RCC_APB2Periph_GPIOB | RCC_APB2Periph_AFIO, ENABLE);
00113
00114 /*-- GPIO Configuration ------------------------------------------------------*/
00115   /*!< OneNAND Data lines configuration */
00116   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_8 | GPIO_Pin_9 |
00117                                 GPIO_Pin_10 | GPIO_Pin_14 | GPIO_Pin_15;
00118   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
00119   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00120   GPIO_Init(GPIOD, &GPIO_InitStructure);
00121
00122   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 |
00123                                 GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 |
00124                                 GPIO_Pin_15;
00125   GPIO_Init(GPIOE, &GPIO_InitStructure);
00126
00127   /*!< OneNAND Address lines configuration */
00128   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 |
00129                                 GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_12 | GPIO_Pin_13 |
00130                                 GPIO_Pin_14 | GPIO_Pin_15;
00131   GPIO_Init(GPIOF, &GPIO_InitStructure);
00132
00133   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 |
00134                                 GPIO_Pin_4 | GPIO_Pin_5;
00135   GPIO_Init(GPIOG, &GPIO_InitStructure);
00136
00137   /*!< CLK, NOE and NWE configuration */
00138   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3 | GPIO_Pin_4 |GPIO_Pin_5;
00139   GPIO_Init(GPIOD, &GPIO_InitStructure);
00140
00141   /*!< NE1 configuration */
00142   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7;
00143   GPIO_Init(GPIOD, &GPIO_InitStructure);
00144
00145   /*!< NL configuration */
00146   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7;
00147   GPIO_Init(GPIOB, &GPIO_InitStructure);
00148   GPIO_PinRemapConfig(GPIO_Remap_FSMC_NADV, DISABLE);
00149
00150   /*!< NWAIT configuration */
00151   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
00152   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
00153   GPIO_Init(GPIOD, &GPIO_InitStructure);
00154
00155   /*-- FSMC Configuration ----------------------------------------------------*/
00156   p.FSMC_AddressSetupTime = 0x01;
00157   p.FSMC_AddressHoldTime = 0x00;
00158   p.FSMC_DataSetupTime = 0x05;
00159   p.FSMC_BusTurnAroundDuration = 0x02;
00160   p.FSMC_CLKDivision = 0x1;
00161   p.FSMC_DataLatency = 0x01;
00162   p.FSMC_AccessMode = FSMC_AccessMode_B;
00163
00164   FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM1;
00165   FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
00166   FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_NOR;
00167   FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
00168   FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Enable;
00169   FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
00170   FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
00171   FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
00172   FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
00173   FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
00174   FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Enable;
00175   FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
00176   FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
00177   FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
00178   FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
00179
00180   FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);
00181   FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM1, ENABLE);
00182 }
00183
00184 /**
00185   * @brief  Resets the OneNAND memory.
00186   * @param  None
00187   * @retval None
00188   */
00189 void OneNAND_Reset(void)
00190 {
00191   OneNAND_WRITE(ONENAND_BOOTPARTITION_ADDR, OneNAND_CMD_RESET);
00192 }
00193
00194 /**
00195   * @brief  Reads OneNAND memory's Manufacturer and Device Code.
00196   * @param  OneNAND_ID: pointer to a OneNAND_IDTypeDef structure which will hold
00197   *         the Manufacturer and Device Code.
00198   * @retval None
00199   */
00200 void OneNAND_ReadID(OneNAND_IDTypeDef* OneNAND_ID)
00201 {
00202   uint16_t status = 0x0;
00203
00204   /* Wait till no ongoing operation */
00205   status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS);
00206
00207   while((status & 0x8000) == 0x8000)
00208   {
00209     status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS);
00210   }
00211
00212   /* Read ID data */
00213   OneNAND_ID->Manufacturer_ID = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_MANUFACTERID);
00214   OneNAND_ID->Device_ID = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_DEVICEID);
00215
00216   *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_SYSTEMCONFIGURATION) = 0x40E0;
00217 }
00218
00219 /**
00220   * @brief  Unlocks the specified OneNAND memory block (128Kb).
00221   * @param  BlockNumber: specifies the block number to be erased. This parameter
00222   *         should be between 0 and 511.
00223   * @retval OneNAND memory Interrupt Status.
00224   */
00225 uint16_t OneNAND_UnlockBlock(uint32_t BlockNumber)
00226 {
00227   uint16_t  status = 0;
00228
00229   /* Wait till no ongoing operation */
00230   status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS);
00231
00232   while((status & 0x8000) == 0x8000)
00233   {
00234     status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS);
00235   }
00236
00237   *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_STARTBLOCKADDRESS) = BlockNumber;
00238   *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT) = 0x0000;
00239   *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_COMMAND) = OneNAND_CMD_UNLOCK;
00240
00241   /* Wait till the command is completed */
00242   status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT);
00243
00244   while((status & 0x8000) != 0x8000)
00245   {
00246     status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT);
00247   }
00248
00249   /* Get the Controller Status */
00250   status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS);
00251
00252   return (status);
00253 }
00254
00255 /**
00256   * @brief  Erases the specified OneNAND memory block (128Kb).
00257   * @param  BlockNumber: specifies the block number to be erased. This parameter
00258   *         should be between 0 and 511.
00259   * @retval OneNAND memory Interrupt Status.
00260   */
00261 uint16_t OneNAND_EraseBlock(uint32_t BlockNumber)
00262 {
00263   uint16_t status = 0x0;
00264
00265   /* Wait till no ongoing operation */
00266   status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS);
00267
00268   while((status & 0x8000) == 0x8000)
00269   {
00270     status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS);
00271   }
00272
00273   /* Erase operation */
00274   *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_STARTADDRESS1) = BlockNumber;
00275   *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT) = 0x0000;
00276   *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_COMMAND) = OneNAND_CMD_ERASE;
00277
00278   /* Wait till no error is generated */
00279   status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS);
00280
00281   while((status & 0x0400) == 0x0400)
00282   {
00283     status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS);
00284   }
00285
00286   /* Wait till the command is completed */
00287   status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT);
00288
00289   while((status & 0x8000) != 0x8000)
00290   {
00291     status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT);
00292   }
00293
00294   /* Get the Controller Status */
00295   status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS);
00296
00297   return (status);
00298 }
00299
00300 /**
00301   * @brief  Writes a Half-word buffer to the OneNAND memory.
00302   * @param  pBuffer: pointer to buffer.
00303   * @param  WriteAddr: OneNAND memory internal address from which the data will be
00304   *         written.
00305   * @param  NumHalfwordToWrite: number of half-words to write.
00306   * @retval OneNAND memory Controller Status.
00307   */
00308 uint16_t OneNAND_WriteBuffer(uint16_t* pBuffer, OneNAND_ADDRESS Address, uint32_t NumHalfwordToWrite)
00309 {
00310   uint32_t datacounter = 0;
00311   uint16_t status = 0;
00312
00313   /* Load the buffer to be written into the DATA RAM0*/
00314   for(datacounter = 0; datacounter < NumHalfwordToWrite; datacounter++)
00315   {
00316     *(__IO uint16_t *)((BANK1_ONENAND1_ADDR + OneNAND_DATA_RAM_0_0_ADD) + (2*datacounter)) = pBuffer[datacounter];
00317   }
00318
00319   /* Write operation from DATA RAM0 to NAND address*/
00320   *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_STARTADDRESS1) = Address.Block; /* NAND Flash block address*/
00321   *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_STARTADDRESINT8_T) = (uint16_t)(Address.Page << 2);  /* NAND Flash start page address */
00322   *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_STARTBUFFER) = OneNAND_DATA_RAM_0_0_REG;/* BufferRAM Sector Count (BSC) and BufferRAM Sector Address (BSA).*/
00323   *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT) = 0x0000;
00324   *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_COMMAND) = OneNAND_CMD_PROGRAM; /* Command */
00325
00326   /* Wait till the command is completed */
00327   status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT);
00328
00329   while((status & 0x8000) != 0x8000)
00330   {
00331     status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT);
00332   }
00333
00334   /* Wait till the write interrupt is set */
00335   status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT);
00336
00337   while((status & 0x40) != 0x40)
00338   {
00339     status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT);
00340   }
00341
00342   /* Get the Controller Status */
00343   status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS);
00344
00345   return (status);
00346 }
00347
00348 /**
00349   * @brief  Reads a block of data from the OneNAND memory using asynchronous mode.
00350   * @param  pBuffer: pointer to the buffer that receives the data read from the
00351   *         OneNAND memory.
00352   * @param  ReadAddr: OneNAND memory internal address to read from.
00353   * @param  NumHalfwordToRead: number of half-words to read.
00354   * @retval None
00355   */
00356 void OneNAND_AsynchronousRead(uint16_t* pBuffer, OneNAND_ADDRESS Address, uint32_t NumHalfwordToRead)
00357 {
00358   uint16_t datatmp = 0x0, index = 0;
00359   uint16_t status = 0;
00360
00361   datatmp = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_SYSTEMCONFIGURATION);
00362
00363   /* Set the asynchronous read mode */
00364   OneNAND_WRITE(BANK1_ONENAND1_ADDR + OneNAND_REG_SYSTEMCONFIGURATION, (datatmp& 0x7FFF));
00365
00366   /* Load data from the read address to the DATA RAM 1 setor 1 */
00367   *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_STARTADDRESS1) = Address.Block; /* NAND Flash block address*/
00368   *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_STARTADDRESINT8_T) = (uint16_t)(Address.Page << 2);
00369   *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_STARTBUFFER) = OneNAND_DATA_RAM_1_0_REG;
00370   *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT) = 0x0000;
00371   *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_COMMAND) = OneNAND_CMD_LOAD; /* Command */
00372
00373   /* Wait till the command is completed */
00374   status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT);
00375
00376   while((status & 0x8000) != 0x8000)
00377   {
00378     status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT);
00379   }
00380
00381   /* Read Controller status */
00382   status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS);
00383
00384   /* Read data */
00385   for(; NumHalfwordToRead != 0x00; NumHalfwordToRead--) /* While there is data to read */
00386   {
00387     /* Read a Halfword from the memory */
00388     *pBuffer++ = *(__IO uint16_t *)((BANK1_ONENAND1_ADDR + OneNAND_DATA_RAM_1_0_ADD)+ 2*index);
00389     index++;
00390   }
00391 }
00392
00393 /**
00394   * @brief  Reads a block of data from the OneNAND memory using synchronous mode.
00395   * @param  pBuffer: pointer to the buffer that receives the data read from the
00396   *         OneNAND memory.
00397   * @param  ReadAddr: OneNAND memory internal address to read from.
00398   * @param  NumHalfwordToRead: number of half-words to read.
00399   * @retval None
00400   */
00401 void OneNAND_SynchronousRead(uint16_t* pBuffer, OneNAND_ADDRESS Address, uint32_t NumHalfwordToRead)
00402 {
00403   uint16_t index = 0;
00404   uint16_t status = 0;
00405
00406   /* Set the asynchronous read mode */
00407   OneNAND_WRITE(BANK1_ONENAND1_ADDR + OneNAND_REG_SYSTEMCONFIGURATION, 0xB4C0);
00408
00409
00410   /* Load data from the read address to the DATA RAM 1 setor 1 */
00411   *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_STARTADDRESS1) = Address.Block; /* NAND Flash block address*/
00412   *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_STARTADDRESINT8_T) = (uint16_t)(Address.Page << 2);
00413   *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_STARTBUFFER) = OneNAND_DATA_RAM_1_0_REG;
00414   *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT) = 0x0000;
00415   *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_COMMAND) = OneNAND_CMD_LOAD; /* Command */
00416
00417   /* Wait till the command is completed */
00418   status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT);
00419
00420   while((status & 0x8000) != 0x8000)
00421   {
00422     status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT);
00423   }
00424
00425   /* Read Controller status */
00426   status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS);
00427
00428   /* Read data */
00429   for(; NumHalfwordToRead != 0x00; NumHalfwordToRead--) /* While there is data to read */
00430   {
00431    *pBuffer++ = *(__IO uint16_t *)((BANK1_ONENAND1_ADDR + OneNAND_DATA_RAM_1_0_ADD + 2*index));
00432     index++;
00433   }
00434 }
00435
00436 /**
00437   * @brief  Reads the OneNAND memory Interrupt status.
00438   * @param  None
00439   * @retval OneNAND memory Interrupt Status.
00440   */
00441 uint16_t OneNAND_ReadStatus(void)
00442 {
00443   __IO uint16_t status = 0x0;
00444
00445   /* Read Status */
00446   return (status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT));
00447 }
00448
00449 /**
00450   * @brief  Reads the OneNAND Controller status.
00451   * @param  None
00452   * @retval OneNAND Controller Status.
00453   */
00454 uint16_t OneNAND_ReadControllerStatus(void)
00455 {
00456   __IO uint16_t status = 0x0;
00457
00458   /* Read Controller Status */
00459   return (status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS));
00460 }
00461
00462 /**
00463   * @}
00464   */
00465
00466 /**
00467   * @}
00468   */
00469
00470 /**
00471   * @}
00472   */
00473
00474 /**
00475   * @}
00476   */
00477
00478 /**
00479   * @}
00480   */
00481
00482 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32100e_eval_fsmc_onenand.h Source File

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  • Utilities
  • STM32_EVAL
  • STM32100E_EVAL

stm32100e_eval_fsmc_onenand.h

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32100e_eval_fsmc_onenand.h
00004   * @author  MCD Application Team
00005   * @version V4.5.0
00006   * @date    07-March-2011
00007   * @brief   This file contains all the functions prototypes for the
00008   *          stm32100e_eval_fsmc_onenand firmware driver.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00013   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00014   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00015   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00016   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00017   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00018   *
00019   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00020   ******************************************************************************
00021   */
00022
00023 /* Define to prevent recursive inclusion -------------------------------------*/
00024 #ifndef __STM32100E_EVAL_FSMC_ONENAND_H
00025 #define __STM32100E_EVAL_FSMC_ONENAND_H
00026
00027 #ifdef __cplusplus
00028  extern "C" {
00029 #endif
00030
00031 /* Includes ------------------------------------------------------------------*/
00032 #include "stm32f10x.h"
00033
00034 /** @addtogroup Utilities
00035   * @{
00036   */
00037
00038 /** @addtogroup STM32_EVAL
00039   * @{
00040   */
00041
00042 /** @addtogroup STM32100E_EVAL
00043   * @{
00044   */
00045
00046 /** @addtogroup STM32100E_EVAL_FSMC_ONENAND
00047   * @{
00048   */
00049
00050 /** @defgroup STM32100E_EVAL_FSMC_ONENAND_Exported_Types
00051   * @{
00052   */
00053 typedef struct
00054 {
00055   uint16_t Manufacturer_ID;
00056   uint16_t Device_ID;
00057 }OneNAND_IDTypeDef;
00058
00059 /* OneNand Status */
00060 typedef enum
00061 {
00062   OneNAND_SUCCESS = 0,
00063   OneNAND_ONGOING,
00064   OneNAND_ERROR,
00065   OneNAND_TIMEOUT
00066 }OneNAND_Status;
00067
00068 typedef struct
00069 {
00070   uint16_t Block;
00071   uint16_t Page;
00072 } OneNAND_ADDRESS;
00073 /**
00074   * @}
00075   */
00076
00077 /** @defgroup STM32100E_EVAL_FSMC_ONENAND_Exported_Constants
00078   * @{
00079   */
00080 /**
00081   * @brief  OneNAND memory command
00082   */
00083 #define OneNAND_CMD_ERASE                    ((uint16_t)0x0094)
00084 #define OneNAND_CMD_PROGRAM                  ((uint16_t)0x0080)
00085 #define OneNAND_CMD_RESET                    ((uint16_t)0x00F0)
00086 #define OneNAND_CMD_READ_ID                  ((uint16_t)0x0090)
00087 #define OneNAND_CMD_UNLOCK                   ((uint16_t)0x0023)
00088 #define OneNAND_CMD_LOAD                     ((uint16_t)0x0000)
00089
00090 /**
00091   * @brief OneNand Register description
00092   */
00093 #define OneNAND_REG_MANUFACTERID             ((uint32_t)0x1E000) /* Manufacturer identification */
00094 #define OneNAND_REG_DEVICEID                 ((uint32_t)0x1E002) /* Device identification */
00095 #define OneNAND_REG_DATABUFFERSIZE           ((uint32_t)0x1E006) /* Data Buffer size */
00096 #define OneNAND_REG_BOOTBUFFERSIZE           ((uint32_t)0x1E008) /* Boot Buffer size */
00097 #define OneNAND_REG_AMOUNTOFBUFFERS          ((uint32_t)0x1E00A) /* Amount of data/boot buffers */
00098 #define OneNAND_REG_TECHNOLOGY               ((uint32_t)0x1E00C) /* Info about technology */
00099 #define OneNAND_REG_STARTADDRESS1            ((uint32_t)0x1E200) /* Nand Flash Block Address */
00100 #define OneNAND_REG_STARTADDRESS3            ((uint32_t)0x1E204) /* Destination Block address for copy back program */
00101 #define OneNAND_REG_STARTADDRESS4            ((uint32_t)0x1E206) /* Destination Page & sector address for copy back program */
00102 #define OneNAND_REG_STARTADDRESINT8_T        ((uint32_t)0x1E20E) /* Nand Flash Page & sector address */
00103 #define OneNAND_REG_STARTBUFFER              ((uint32_t)0x1E400) /* The meaning is with which buffer to start and how many
00104                                                                      buffers to use for the data transfer */
00105 #define OneNAND_REG_COMMAND                  ((uint32_t)0x1E440) /* Host control and memory operation commands*/
00106 #define OneNAND_REG_SYSTEMCONFIGURATION      ((uint32_t)0x1E442) /* Memory and host interface configuration */
00107 #define OneNAND_REG_CONTROLSTATUS            ((uint32_t)0x1E480) /* Control status and result of memory operation */
00108 #define OneNAND_REG_INTERRUPT                ((uint32_t)0x1E482) /* Memory Command Completion Interrupt Status */
00109 #define OneNAND_REG_STARTBLOCKADDRESS        ((uint32_t)0x1E498) /* Start memory block address in Write Protection mode */
00110 #define OneNAND_REG_WRITEPROTECTIONSTATUS    ((uint32_t)0x1E49C) /* Current memory Write Protection status */
00111
00112 /**
00113   * @brief OneNand Memory partition description
00114   */
00115 #define OneNAND_DATA_RAM_0_0_ADD            ((uint32_t)0x0400) /* DataRAM Main page0/sector0 */
00116 #define OneNAND_DATA_RAM_0_0_REG            ((uint32_t)0x0800) /* DataRAM 0_0 is selected with 4 sector */
00117
00118 #define OneNAND_DATA_RAM_0_1_ADD            ((uint32_t)0x0600) /* DataRAM Main page0/sector1 */
00119 #define OneNAND_DATA_RAM_0_1_REG            ((uint32_t)0x0900) /* DataRAM 0_1 is selected with 4 sector */
00120
00121 #define OneNAND_DATA_RAM_0_2_ADD            ((uint32_t)0x0800) /* DataRAM Main page0/sector2 */
00122 #define OneNAND_DATA_RAM_0_2_REG            ((uint32_t)0x0A00) /* DataRAM 0_2 is selected with 4 sector */
00123
00124 #define OneNAND_DATA_RAM_0_3_ADD            ((uint32_t)0x0A00) /* DataRAM Main page0/sector3 */
00125 #define OneNAND_DATA_RAM_0_3_REG            ((uint32_t)0x0B00) /* DataRAM 0_3 is selected with 4 sector */
00126
00127 #define OneNAND_DATA_RAM_1_0_ADD            ((uint32_t)0x0C00) /* DataRAM Main page1/sector0 */
00128 #define OneNAND_DATA_RAM_1_0_REG            ((uint32_t)0x0C00) /* DataRAM 1_0 is selected with 4 sector */
00129
00130 #define OneNAND_DATA_RAM_1_1_ADD            ((uint32_t)0x0E00) /* DataRAM Main page1/sector1 */
00131 #define OneNAND_DATA_RAM_1_1_REG            ((uint32_t)0x0D00) /* DataRAM 1_1 is selected with 4 sector */
00132
00133 #define OneNAND_DATA_RAM_1_2_ADD            ((uint32_t)0x1000) /* DataRAM Main page1/sector2 */
00134 #define OneNAND_DATA_RAM_1_2_REG            ((uint32_t)0x0E00) /* DataRAM 1_2 is selected with 4 sector */
00135
00136 #define OneNAND_DATA_RAM_1_3_ADD            ((uint32_t)0x1200) /* DataRAM Main page1/sector3 */
00137 #define OneNAND_DATA_RAM_1_3_REG            ((uint32_t)0x0F00) /* DataRAM 1_3 is selected with 4 sector */
00138
00139 /**
00140   * @}
00141   */
00142
00143 /** @defgroup STM32100E_EVAL_FSMC_ONENAND_Exported_Macros
00144   * @{
00145   */
00146 /**
00147   * @}
00148   */
00149
00150 /** @defgroup STM32100E_EVAL_FSMC_ONENAND_Exported_Functions
00151   * @{
00152   */
00153 void OneNAND_Init(void);
00154 void OneNAND_Reset(void);
00155 void OneNAND_ReadID(OneNAND_IDTypeDef* OneNAND_ID);
00156 uint16_t OneNAND_UnlockBlock(uint32_t BlockNumber);
00157 uint16_t OneNAND_EraseBlock(uint32_t BlockNumber);
00158 uint16_t OneNAND_WriteBuffer(uint16_t* pBuffer, OneNAND_ADDRESS Address, uint32_t NumHalfwordToWrite);
00159 void OneNAND_AsynchronousRead(uint16_t* pBuffer, OneNAND_ADDRESS Address, uint32_t NumHalfwordToRead);
00160 void OneNAND_SynchronousRead(uint16_t* pBuffer, OneNAND_ADDRESS Address, uint32_t NumHalfwordToRead);
00161 uint16_t OneNAND_ReadStatus(void);
00162 uint16_t OneNAND_ReadControllerStatus(void);
00163
00164 #ifdef __cplusplus
00165 }
00166 #endif
00167
00168 #endif /* __STM32100E_EVAL_FSMC_ONENAND_H */
00169 /**
00170   * @}
00171   */
00172
00173 /**
00174   * @}
00175   */
00176
00177 /**
00178   * @}
00179   */
00180
00181 /**
00182   * @}
00183   */
00184
00185 /**
00186   * @}
00187   */
00188
00189 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32100e_eval_fsmc_sram.c Source File

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • STM32100E_EVAL

stm32100e_eval_fsmc_sram.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32100e_eval_fsmc_sram.c
00004   * @author  MCD Application Team
00005   * @version V4.5.0
00006   * @date    07-March-2011
00007   * @brief   This file provides a set of functions needed to drive the
00008   *          IS61WV102416BLL SRAM memory mounted on STM32100E-EVAL board.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00013   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00014   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00015   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00016   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00017   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00018   *
00019   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00020   ******************************************************************************
00021   */
00022
00023 /* Includes ------------------------------------------------------------------*/
00024 #include "stm32100e_eval_fsmc_sram.h"
00025
00026 /** @addtogroup Utilities
00027   * @{
00028   */
00029
00030 /** @addtogroup STM32_EVAL
00031   * @{
00032   */
00033
00034 /** @addtogroup STM32100E_EVAL
00035   * @{
00036   */
00037
00038 /** @addtogroup STM32100E_EVAL_FSMC_SRAM
00039   * @brief      This file provides a set of functions needed to drive the
00040   *             IS61WV102416BLL SRAM memory mounted on STM32100E-EVAL board.
00041   * @{
00042   */
00043
00044 /** @defgroup STM32100E_EVAL_FSMC_SRAM_Private_Types
00045   * @{
00046   */
00047 /**
00048   * @}
00049   */
00050
00051
00052 /** @defgroup STM32100E_EVAL_FSMC_SRAM_Private_Defines
00053   * @{
00054   */
00055 /**
00056   * @brief  FSMC Bank 1 NOR/SRAM3
00057   */
00058 #define Bank1_SRAM3_ADDR    ((uint32_t)0x68000000)
00059 /**
00060   * @}
00061   */
00062
00063
00064 /** @defgroup STM32100E_EVAL_FSMC_SRAM_Private_Macros
00065   * @{
00066   */
00067 /**
00068   * @}
00069   */
00070
00071
00072 /** @defgroup STM32100E_EVAL_FSMC_SRAM_Private_Variables
00073   * @{
00074   */
00075 /**
00076   * @}
00077   */
00078
00079
00080 /** @defgroup STM32100E_EVAL_FSMC_SRAM_Private_Function_Prototypes
00081   * @{
00082   */
00083 /**
00084   * @}
00085   */
00086
00087
00088 /** @defgroup STM32100E_EVAL_FSMC_SRAM_Private_Functions
00089   * @{
00090   */
00091
00092 /**
00093   * @brief  Configures the FSMC and GPIOs to interface with the SRAM memory.
00094   *         This function must be called before any write/read operation
00095   *         on the SRAM.
00096   * @param  None
00097   * @retval None
00098   */
00099 void SRAM_Init(void)
00100 {
00101   FSMC_NORSRAMInitTypeDef  FSMC_NORSRAMInitStructure;
00102   FSMC_NORSRAMTimingInitTypeDef  p;
00103   GPIO_InitTypeDef GPIO_InitStructure;
00104
00105   RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOG | RCC_APB2Periph_GPIOE |
00106                          RCC_APB2Periph_GPIOF, ENABLE);
00107
00108 /*-- GPIO Configuration ------------------------------------------------------*/
00109   /*!< SRAM Data lines configuration */
00110   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_8 | GPIO_Pin_9 |
00111                                 GPIO_Pin_10 | GPIO_Pin_14 | GPIO_Pin_15;
00112   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
00113   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00114   GPIO_Init(GPIOD, &GPIO_InitStructure);
00115
00116   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 |
00117                                 GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 |
00118                                 GPIO_Pin_15;
00119   GPIO_Init(GPIOE, &GPIO_InitStructure);
00120
00121   /*!< SRAM Address lines configuration */
00122   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 |
00123                                 GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_12 | GPIO_Pin_13 |
00124                                 GPIO_Pin_14 | GPIO_Pin_15;
00125   GPIO_Init(GPIOF, &GPIO_InitStructure);
00126
00127   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 |
00128                                 GPIO_Pin_4 | GPIO_Pin_5;
00129   GPIO_Init(GPIOG, &GPIO_InitStructure);
00130
00131   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13;
00132   GPIO_Init(GPIOD, &GPIO_InitStructure);
00133
00134   /*!< NOE and NWE configuration */
00135   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4 |GPIO_Pin_5;
00136   GPIO_Init(GPIOD, &GPIO_InitStructure);
00137
00138   /*!< NE3 configuration */
00139   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10;
00140   GPIO_Init(GPIOG, &GPIO_InitStructure);
00141
00142   /*!< NBL0, NBL1 configuration */
00143   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1;
00144   GPIO_Init(GPIOE, &GPIO_InitStructure);
00145
00146 /*-- FSMC Configuration ------------------------------------------------------*/
00147   p.FSMC_AddressSetupTime = 0;
00148   p.FSMC_AddressHoldTime = 0;
00149   p.FSMC_DataSetupTime = 3;
00150   p.FSMC_BusTurnAroundDuration = 0;
00151   p.FSMC_CLKDivision = 0;
00152   p.FSMC_DataLatency = 0;
00153   p.FSMC_AccessMode = FSMC_AccessMode_A;
00154
00155   FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM3;
00156   FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
00157   FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM;
00158   FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
00159   FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
00160   FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
00161   FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
00162   FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
00163   FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
00164   FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
00165   FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
00166   FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
00167   FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
00168   FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
00169   FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
00170
00171   FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);
00172
00173   /*!< Enable FSMC Bank1_SRAM Bank */
00174   FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM3, ENABLE);
00175 }
00176
00177 /**
00178   * @brief  Writes a Half-word buffer to the FSMC SRAM memory.
00179   * @param  pBuffer : pointer to buffer.
00180   * @param  WriteAddr : SRAM memory internal address from which the data will be
00181   *         written.
00182   * @param  NumHalfwordToWrite : number of half-words to write.
00183   * @retval None
00184   */
00185 void SRAM_WriteBuffer(uint16_t* pBuffer, uint32_t WriteAddr, uint32_t NumHalfwordToWrite)
00186 {
00187   for(; NumHalfwordToWrite != 0; NumHalfwordToWrite--) /*!< while there is data to write */
00188   {
00189     /*!< Transfer data to the memory */
00190     *(uint16_t *) (Bank1_SRAM3_ADDR + WriteAddr) = *pBuffer++;
00191
00192     /*!< Increment the address*/
00193     WriteAddr += 2;
00194   }
00195 }
00196
00197 /**
00198   * @brief  Reads a block of data from the FSMC SRAM memory.
00199   * @param  pBuffer : pointer to the buffer that receives the data read from the
00200   *         SRAM memory.
00201   * @param  ReadAddr : SRAM memory internal address to read from.
00202   * @param  NumHalfwordToRead : number of half-words to read.
00203   * @retval None
00204   */
00205 void SRAM_ReadBuffer(uint16_t* pBuffer, uint32_t ReadAddr, uint32_t NumHalfwordToRead)
00206 {
00207   for(; NumHalfwordToRead != 0; NumHalfwordToRead--) /*!< while there is data to read */
00208   {
00209     /*!< Read a half-word from the memory */
00210     *pBuffer++ = *(__IO uint16_t*) (Bank1_SRAM3_ADDR + ReadAddr);
00211
00212     /*!< Increment the address*/
00213     ReadAddr += 2;
00214   }
00215 }
00216
00217 /**
00218   * @}
00219   */
00220
00221 /**
00222   * @}
00223   */
00224
00225 /**
00226   * @}
00227   */
00228
00229 /**
00230   * @}
00231   */
00232
00233 /**
00234   * @}
00235   */
00236
00237 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32100e_eval_fsmc_sram.h Source File

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • STM32100E_EVAL

stm32100e_eval_fsmc_sram.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32100e_eval_fsmc_sram.h
00004   * @author  MCD Application Team
00005   * @version V4.5.0
00006   * @date    07-March-2011
00007   * @brief   This file contains all the functions prototypes for the
00008   *          stm32100e_eval_fsmc_sram firmware driver.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00013   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00014   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00015   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00016   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00017   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00018   *
00019   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00020   ******************************************************************************
00021   */
00022
00023 /* Define to prevent recursive inclusion -------------------------------------*/
00024 #ifndef __STM32100E_EVAL_FSMC_SRAM_H
00025 #define __STM32100E_EVAL_FSMC_SRAM_H
00026
00027 #ifdef __cplusplus
00028  extern "C" {
00029 #endif
00030
00031 /* Includes ------------------------------------------------------------------*/
00032 #include "stm32f10x.h"
00033
00034 /** @addtogroup Utilities
00035   * @{
00036   */
00037
00038 /** @addtogroup STM32_EVAL
00039   * @{
00040   */
00041
00042 /** @addtogroup STM32100E_EVAL
00043   * @{
00044   */
00045
00046 /** @addtogroup STM32100E_EVAL_FSMC_SRAM
00047   * @{
00048   */
00049
00050 /** @defgroup STM32100E_EVAL_FSMC_SRAM_Exported_Types
00051   * @{
00052   */
00053 /**
00054   * @}
00055   */
00056
00057 /** @defgroup STM32100E_EVAL_FSMC_SRAM_Exported_Constants
00058   * @{
00059   */
00060 /**
00061   * @}
00062   */
00063
00064 /** @defgroup STM32100E_EVAL_FSMC_SRAM_Exported_Macros
00065   * @{
00066   */
00067 /**
00068   * @}
00069   */
00070
00071 /** @defgroup STM32100E_EVAL_FSMC_SRAM_Exported_Functions
00072   * @{
00073   */
00074
00075 void SRAM_Init(void);
00076 void SRAM_WriteBuffer(uint16_t* pBuffer, uint32_t WriteAddr, uint32_t NumHalfwordToWrite);
00077 void SRAM_ReadBuffer(uint16_t* pBuffer, uint32_t ReadAddr, uint32_t NumHalfwordToRead);
00078
00079 #ifdef __cplusplus
00080 }
00081 #endif
00082
00083 #endif /* __STM32100E_EVAL_FSMC_SRAM_H */
00084 /**
00085   * @}
00086   */
00087
00088 /**
00089   * @}
00090   */
00091
00092 /**
00093   * @}
00094   */
00095
00096 /**
00097   * @}
00098   */
00099
00100 /**
00101   * @}
00102   */
00103
00104 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32100e_eval_ioe.c Source File

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • STM32100E_EVAL

stm32100e_eval_ioe.c

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32100e_eval_ioe.c
00004   * @author  MCD Application Team
00005   * @version V4.5.0
00006   * @date    07-March-2011
00007   * @brief   This file includes the IO Expander driver for STMPE811 IO Expander
00008   *          devices.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00013   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00014   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00015   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00016   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00017   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00018   *
00019   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00020   ******************************************************************************
00021   */
00022
00023   /* File Info : ---------------------------------------------------------------
00024
00025     Note:
00026     -----
00027     - This driver uses the DMA method for sending and receiving data on I2C bus
00028       which allow higher efficiency and reliability of the communication.
00029
00030     SUPPORTED FEATURES:
00031       - Touch Screen Features: Single point mode (Polling/Interrupt).
00032       - TempSensor Feature: accuracy not determined (Polling).
00033       - IO Read/write : Set/Reset and Read (Polling/Interrupt).
00034
00035     UNSUPPORTED FEATURES:
00036       - Row ADC Feature is not supported (not implemented on STM32100E-EVAL board)
00037       - Joystick: config and Read (Polling/Interrupt)
00038   ----------------------------------------------------------------------------*/
00039
00040 /* Includes ------------------------------------------------------------------*/
00041 #include "stm32100e_eval_ioe.h"
00042
00043 /** @addtogroup Utilities
00044   * @{
00045   */
00046
00047 /** @addtogroup STM32_EVAL
00048   * @{
00049   */
00050
00051 /** @addtogroup STM32100E_EVAL
00052   * @{
00053   */
00054
00055 /** @defgroup STM32100E_EVAL_IOE
00056   * @brief  This file includes the IO Expander driver for STMPE811 IO Expander
00057   *         devices.
00058   * @{
00059   */
00060
00061 /** @defgroup STM32100E_EVAL_IOE_Private_TypesDefinitions
00062   * @{
00063   */
00064 /**
00065   * @}
00066   */
00067
00068
00069 /** @defgroup STM32100E_EVAL_IOE_Private_Defines
00070   * @{
00071   */
00072 #define TIMEOUT_MAX    0x1000 /*<! The value of the maximal timeout for I2C waiting loops */
00073 /**
00074   * @}
00075   */
00076
00077
00078 /** @defgroup STM32100E_EVAL_IOE_Private_Macros
00079   * @{
00080   */
00081 /**
00082   * @}
00083   */
00084
00085
00086 /** @defgroup STM32100E_EVAL_IOE_Private_Variables
00087   * @{
00088   */
00089 TS_STATE TS_State;              /*<! The global structure holding the TS state */
00090
00091 uint32_t IOE_TimeOut = TIMEOUT_MAX; /*<! Value of Timeout when I2C communication fails */
00092 /**
00093   * @}
00094   */
00095
00096
00097 /** @defgroup STM32100E_EVAL_IOE_Private_FunctionPrototypes
00098   * @{
00099   */
00100 static uint16_t IOE_TS_Read_X(void);
00101 static uint16_t IOE_TS_Read_Y(void);
00102 static uint16_t IOE_TS_Read_Z(void);
00103
00104 static void IOE_GPIO_Config(void);
00105 static void IOE_I2C_Config(void);
00106 static void IOE_DMA_Config(IOE_DMADirection_TypeDef Direction, uint8_t* buffer);
00107 static void IOE_EXTI_Config(void);
00108
00109 #ifndef USE_Delay
00110 static void delay(__IO uint32_t nCount);
00111 #endif /* USE_Delay*/
00112 /**
00113   * @}
00114   */
00115
00116
00117 /** @defgroup STM32100E_EVAL_IOE_Private_Functions
00118   * @{
00119   */
00120
00121
00122 /**
00123   * @brief  Initializes and Configures the IO_Expanders Functionalities
00124   *         (Touch Screen ..) and configures all STM32100E-EVAL necessary
00125   *         hardware (GPIOs, APB clocks ..).
00126   * @param  None
00127   * @retval IOE_OK if all initializations done correctly. Other value if error.
00128   */
00129 uint8_t IOE_Config(void)
00130 {
00131   /* Configure the needed pins */
00132   IOE_GPIO_Config();
00133
00134   /* Configure I2C peripheral */
00135   IOE_I2C_Config();
00136
00137   /* Read IO Expander 1 ID  */
00138   if(IOE_IsOperational(IOE_1_ADDR))
00139   {
00140     return IOE1_NOT_OPERATIONAL;
00141   }
00142
00143   /* Generate IOExpander Software reset */
00144   IOE_Reset(IOE_1_ADDR);
00145
00146   /* ---------------------- IO Expander configuration --------------------- */
00147   /* Enable the GPIO, Touch Screen and ADC functionalities */
00148   IOE_FnctCmd(IOE_1_ADDR, IOE_TS_FCT | IOE_ADC_FCT | IOE_IO_FCT | IOE_TEMPSENS_FCT  , ENABLE);
00149
00150   /* Touch Screen controller configuration */
00151   IOE_TS_Config();
00152
00153   /* Temperature Sensor configuration */
00154   IOE_TempSens_Config();
00155
00156   /* ------------------------------------------------------------------------ */
00157
00158   /* Configuration is OK */
00159   return IOE_OK;
00160 }
00161
00162 /**
00163   * @brief  Configures The selected interrupts on the IO Expanders.
00164   * @param  IOE_ITSRC_Source: the source of the interrupts. Could be one or a
00165   *         combination of the following parameters:
00166   *   @arg  IOE_ITSRC_TSC: Touch Screen interrupts.
00167   * @retval IOE_OK: if all initializations are OK. Other value if error.
00168   */
00169 uint8_t IOE_ITConfig(uint32_t IOE_ITSRC_Source)
00170 {
00171   /* Configure the Interrupt output pin to generate low level (INT_CTRL) */
00172   IOE_ITOutConfig(Polarity_Low, Type_Level);
00173
00174   /* Manage the Touch Screen Interrupts */
00175   if (IOE_ITSRC_Source & IOE_ITSRC_TSC)
00176   {
00177     /* Enable the Global interrupt */
00178     IOE_GITCmd(IOE_1_ADDR, ENABLE);
00179
00180     /* Enable the Global GPIO Interrupt */
00181     IOE_GITConfig(IOE_1_ADDR, (uint8_t)(IOE_GIT_TOUCH | IOE_GIT_FTH | IOE_GIT_FOV), ENABLE);
00182
00183     /* Read the GPIO_IT_STA to clear all pending bits if any */
00184     I2C_ReadDeviceRegister(IOE_1_ADDR, IOE_REG_GPIO_INT_STA);
00185   }
00186
00187   /* Configure the Interrupt line as EXTI source */
00188   IOE_EXTI_Config();
00189
00190   /* If all OK return IOE_OK */
00191   return IOE_OK;
00192 }
00193
00194 /**
00195   * @brief  Writes a bit value to an output IO pin.
00196   * @param IO_Pin: The output pin to be set or reset.
00197   *                IO_Pin_x: Where x can be from 0 to 7.
00198   * @param BitVal: The value to be set. This parameter can be one of the
00199   *        following values: BitSet or BitReset. See IOE_BitVal_TypeDef.
00200   * @retval IOE_OK or PARAM_ERROR
00201   */
00202 uint8_t IOE_WriteIOPin(uint8_t IO_Pin, IOE_BitValue_TypeDef BitVal)
00203 {
00204   uint8_t DeviceAddr = 0;
00205
00206   /* Get the IO expander Address according to which pin is to be controlled */
00207   if (IO_Pin & IO1_OUT_ALL_PINS)
00208   {
00209     DeviceAddr = IOE_1_ADDR;
00210   }
00211   else
00212   {
00213     return PARAM_ERROR;
00214   }
00215
00216   /* Apply the bit value to the selected pin */
00217   if (BitVal == BitReset)
00218   {
00219     /* Set the register */
00220     I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_GPIO_CLR_PIN, IO_Pin);
00221   }
00222   else
00223   {
00224     /* Set the register */
00225     I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_GPIO_SET_PIN, IO_Pin);
00226   }
00227
00228   return IOE_OK;
00229 }
00230
00231
00232 /**
00233   * @brief  Returns the status of the selected input IO pin.
00234   * @param IO_Pin: The input pin to be read.
00235   *                IO_Pin_x: Where x can be from 0 to 7.
00236   *   @arg  JOY_IO_PINS: Joystick IO pins (use IOE_JoyStickGetState for these pins)
00237   * @retval None
00238   */
00239 uint8_t IOE_ReadIOPin(uint32_t IO_Pin)
00240 {
00241   uint8_t DeviceAddr = 0;
00242   uint8_t tmp = 0;
00243   if (IO_Pin & IO1_IN_ALL_PINS)
00244   {
00245     DeviceAddr = IOE_1_ADDR;
00246   }
00247    else
00248   {
00249     return PARAM_ERROR;
00250   }
00251
00252   /* Get all the Pins status */
00253   tmp = I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_GPIO_MP_STA);
00254   if ((tmp & (uint8_t)IO_Pin) != 0)
00255   {
00256     return BitSet;
00257   }
00258   else
00259   {
00260     return BitReset;
00261   }
00262 }
00263
00264
00265 /**
00266   * @brief  Returns Status and positions of the Touch screen.
00267   * @param  None
00268   * @retval Pointer to TS_STATE structure holding Touch Screen information.
00269   */
00270 TS_STATE* IOE_TS_GetState(void)
00271 {
00272   uint32_t xDiff, yDiff , x , y;
00273   static uint32_t _x = 0, _y = 0;
00274
00275   /* Check if the Touch detect event happenned */
00276   TS_State.TouchDetected = (I2C_ReadDeviceRegister(IOE_1_ADDR, IOE_REG_TSC_CTRL) & 0x80);
00277   if(TS_State.TouchDetected)
00278   {
00279     x = IOE_TS_Read_X();
00280     y = IOE_TS_Read_Y();
00281     xDiff = x > _x? (x - _x): (_x - x);
00282     yDiff = y > _y? (y - _y): (_y - y);
00283     if (xDiff + yDiff > 5)
00284     {
00285       _x = x;
00286       _y = y;
00287     }
00288   }
00289   /* Update the X position */
00290   TS_State.X = _x;
00291
00292   /* Update the Y position */
00293   TS_State.Y = _y;
00294   /* Update the Z Pression index */
00295   TS_State.Z = IOE_TS_Read_Z();
00296
00297   /* Clear the interrupt pending bit and enable the FIFO again */
00298   I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_FIFO_STA, 0x01);
00299   I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_FIFO_STA, 0x00);
00300
00301   /* Return pointer to the updated structure */
00302   return &TS_State;
00303 }
00304
00305 /**
00306   * @brief  Returns the temperature row value (in 16 bit format).
00307   * @param  None
00308   * @retval The temperature row value.
00309   */
00310 uint32_t IOE_TempSens_GetData(void)
00311 {
00312   static __IO uint32_t tmp = 0;
00313
00314   /* Aquire data enable */
00315   I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_TEMP_CTRL, 0x03);
00316
00317   /* Enable the TEMPSENS module */
00318   tmp = (uint32_t)((I2C_ReadDeviceRegister(IOE_1_ADDR, IOE_REG_TEMP_DATA) & 0x03) << 8);
00319   tmp |= (uint32_t)I2C_ReadDeviceRegister(IOE_1_ADDR, IOE_REG_TEMP_DATA + 1);
00320
00321   tmp = (uint32_t)((33 * tmp * 100) / 751);
00322   tmp = (uint32_t)((tmp + 5) / 10);
00323
00324   /* return the temprature row value */
00325   return tmp;
00326 }
00327
00328 /**
00329   * @brief  Checks the selected Global interrupt source pending bit
00330   * @param  DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR.
00331   * @param  Global_IT: the Global interrupt source to be checked, could be:
00332   *   @arg  Global_IT_GPIO : All IOs interrupt
00333   *   @arg  Global_IT_ADC : ADC interrupt
00334   *   @arg  Global_IT_TEMP : Temperature Sensor interrupts
00335   *   @arg  Global_IT_FE : Touch Screen Controller FIFO Error interrupt
00336   *   @arg  Global_IT_FF : Touch Screen Controller FIFO Full interrupt
00337   *   @arg  Global_IT_FOV : Touch Screen Controller FIFO Overrun interrupt
00338   *   @arg  Global_IT_FTH : Touch Screen Controller FIFO Threshold interrupt
00339   *   @arg  Global_IT_TOUCH : Touch Screen Controller Touch Detected interrupt
00340   * @retval Status of the checked flag. Could be SET or RESET.
00341   */
00342 FlagStatus IOE_GetGITStatus(uint8_t DeviceAddr, uint8_t Global_IT)
00343 {
00344   __IO uint8_t tmp = 0;
00345
00346   /* get the Interrupt status */
00347   tmp = I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_INT_STA);
00348
00349   if ((tmp & (uint8_t)Global_IT) != 0)
00350   {
00351     return SET;
00352   }
00353   else
00354   {
00355     return RESET;
00356   }
00357 }
00358
00359 /**
00360   * @brief  Clears the selected Global interrupt pending bit(s)
00361   * @param  DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR.
00362   * @param  Global_IT: the Global interrupt to be cleared, could be any combination
00363   *         of the following values:
00364   *   @arg  Global_IT_GPIO : All IOs interrupt
00365   *   @arg  Global_IT_ADC : ADC interrupt
00366   *   @arg  Global_IT_TEMP : Temperature Sensor interrupts
00367   *   @arg  Global_IT_FE : Touch Screen Controller FIFO Error interrupt
00368   *   @arg  Global_IT_FF : Touch Screen Controller FIFO Full interrupt
00369   *   @arg  Global_IT_FOV : Touch Screen Controller FIFO Overrun interrupt
00370   *   @arg  Global_IT_FTH : Touch Screen Controller FIFO Threshold interrupt
00371   *   @arg  Global_IT_TOUCH : Touch Screen Controller Touch Detected interrupt
00372   * @retval IOE_OK: if all initializations are OK. Other value if error.
00373   */
00374 uint8_t IOE_ClearGITPending(uint8_t DeviceAddr, uint8_t Global_IT)
00375 {
00376   /* Write 1 to the bits that have to be cleared */
00377   I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_INT_STA, Global_IT);
00378
00379   /* If all OK return IOE_OK */
00380   return IOE_OK;
00381 }
00382
00383 /**
00384   * @brief  Checks the status of the selected IO interrupt pending bit
00385   * @param  DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR.
00386   * @param  IO_IT: the IO interrupt to be checked could be IO_ITx Where x can be
00387   *         from 0 to 7.
00388   * @retval Status of the checked flag. Could be SET or RESET.
00389   */
00390 FlagStatus IOE_GetIOITStatus(uint8_t DeviceAddr, uint8_t IO_IT)
00391 {
00392   uint8_t tmp = 0;
00393
00394   /* get the Interrupt status */
00395   tmp = I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_GPIO_INT_STA);
00396
00397   if ((tmp & (uint8_t)IO_IT) != 0)
00398   {
00399     return SET;
00400   }
00401   else
00402   {
00403     return RESET;
00404   }
00405 }
00406
00407 /**
00408   * @brief  Clears the selected IO interrupt pending bit(s).
00409   * @param  DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR.
00410   * @param  IO_IT: the IO interrupt to be checked could be IO_ITx Where x can be
00411   *         from 0 to 7.
00412   * @retval IOE_OK: if all initializations are OK. Other value if error.
00413   */
00414 uint8_t IOE_ClearIOITPending(uint8_t DeviceAddr, uint8_t IO_IT)
00415 {
00416   /* Write 1 to the bits that have to be cleared */
00417   I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_GPIO_INT_STA, IO_IT);
00418
00419   /* Clear the Edge detection pending bit*/
00420   I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_GPIO_ED, IO_IT);
00421
00422   /* Clear the Rising edge pending bit */
00423   I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_GPIO_RE, IO_IT);
00424
00425   /* Clear the Falling edge pending bit */
00426   I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_GPIO_FE, IO_IT);
00427
00428   return IOE_OK;
00429
00430 }
00431 /**
00432   * @brief  Checks if the selected device is correctly configured and
00433   *         communicates correctly ont the I2C bus.
00434   * @param  DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR.
00435   * @retval IOE_OK if IOE is operational. Other value if failure.
00436   */
00437 uint8_t IOE_IsOperational(uint8_t DeviceAddr)
00438 {
00439   /* Return Error if the ID is not correct */
00440   if( IOE_ReadID(DeviceAddr) != (uint16_t)STMPE811_ID )
00441   {
00442     /* Check if a Timeout occured */
00443     if (IOE_TimeOut == 0)
00444     {
00445       return(IOE_TimeoutUserCallback());
00446     }
00447     else
00448     {
00449       return IOE_FAILURE; /* ID is not Correct */
00450     }
00451   }
00452   else
00453   {
00454     return IOE_OK; /* ID is correct */
00455   }
00456 }
00457
00458 /**
00459   * @brief  Resets the IO Expander by Software (SYS_CTRL1, RESET bit).
00460   * @param  DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR.
00461   * @retval IOE_OK: if all initializations are OK. Other value if error.
00462   */
00463 uint8_t IOE_Reset(uint8_t DeviceAddr)
00464 {
00465   /* Power Down the IO_Expander */
00466   I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_SYS_CTRL1, 0x02);
00467
00468   /* wait for a delay to insure registers erasing */
00469   _delay_(2);
00470
00471   /* Power On the Codec after the power off => all registers are reinitialized*/
00472   I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_SYS_CTRL1, 0x00);
00473
00474   /* If all OK return IOE_OK */
00475   return IOE_OK;
00476 }
00477
00478 /**
00479   * @brief  Reads the selected device's ID.
00480   * @param  DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR.
00481   * @retval The Device ID (two bytes).
00482   */
00483 uint16_t IOE_ReadID(uint8_t DeviceAddr)
00484 {
00485   uint16_t tmp = 0;
00486
00487   /* Read device ID  */
00488   tmp = I2C_ReadDeviceRegister(DeviceAddr, 0);
00489   tmp = (uint32_t)(tmp << 8);
00490   tmp |= (uint32_t)I2C_ReadDeviceRegister(DeviceAddr, 1);
00491
00492   /* Return the ID */
00493   return (uint16_t)tmp;
00494 }
00495
00496 /**
00497   * @brief  Configures the selcted IO Expander functionalities.
00498   * @param  DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR.
00499   * @param  Fct: the functions to be configured. could be any
00500   *         combination of the following values:
00501   *   @arg  IOE_IO_FCT : IO function
00502   *   @arg  IOE_TS_FCT : Touch Screen function
00503   *   @arg  IOE_ADC_FCT : ADC function
00504   *   @arg  IOE_TEMPSENS_FCT : Tempreature Sensor function
00505   * @retval IOE_OK: if all initializations are OK. Other value if error.
00506   */
00507 uint8_t IOE_FnctCmd(uint8_t DeviceAddr, uint8_t Fct, FunctionalState NewState)
00508 {
00509   uint8_t tmp = 0;
00510
00511   /* Get the register value */
00512   tmp = I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_SYS_CTRL2);
00513
00514   if (NewState != DISABLE)
00515   {
00516     /* Set the Functionalities to be Enabled */
00517     tmp &= ~(uint8_t)Fct;
00518   }
00519   else
00520   {
00521     /* Set the Functionalities to be Disabled */
00522     tmp |= (uint8_t)Fct;
00523   }
00524
00525   /* Set the register value */
00526   I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_SYS_CTRL2, tmp);
00527
00528   /* If all OK return IOE_OK */
00529   return IOE_OK;
00530 }
00531
00532 /**
00533   * @brief  Configures the selected pin direction (to be an input or an output)
00534   * @param  DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR.
00535   * @param  IO_Pin: IO_Pin_x: Where x can be from 0 to 7.
00536   * @param  Direction: could be Direction_IN or Direction_OUT.
00537   * @retval IOE_OK: if all initializations are OK. Other value if error.
00538   */
00539 uint8_t IOE_IOPinConfig(uint8_t DeviceAddr, uint8_t IO_Pin, uint8_t Direction)
00540 {
00541   uint8_t tmp = 0;
00542
00543   /* Get all the Pins direction */
00544   tmp = I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_GPIO_DIR);
00545
00546   if (Direction != Direction_IN)
00547   {
00548     tmp |= (uint8_t)IO_Pin;
00549   }
00550   else
00551   {
00552     tmp &= ~(uint8_t)IO_Pin;
00553   }
00554
00555   /* Write the register new value */
00556   I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_GPIO_DIR, tmp);
00557
00558   /* If all OK return IOE_OK */
00559   return IOE_OK;
00560 }
00561
00562 /**
00563   * @brief  Enables or disables the Global interrupt.
00564   * @param  DeviceAddr: The address of the IOExpander, could be :I OE_1_ADDR.
00565   * @param  NewState: could be ENABLE or DISABLE.
00566   * @retval IOE_OK: if all initializations are OK. Other value if error.
00567   */
00568 uint8_t IOE_GITCmd(uint8_t DeviceAddr, FunctionalState NewState)
00569 {
00570   uint8_t tmp = 0;
00571
00572   /* Read the Interrupt Control register  */
00573   I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_INT_CTRL);
00574
00575   if (NewState != DISABLE)
00576   {
00577     /* Set the global interrupts to be Enabled */
00578     tmp |= (uint8_t)IOE_GIT_EN;
00579   }
00580   else
00581   {
00582     /* Set the global interrupts to be Disabled */
00583     tmp &= ~(uint8_t)IOE_GIT_EN;
00584   }
00585
00586   /* Write Back the Interrupt Control register */
00587   I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_INT_CTRL, tmp);
00588
00589   /* If all OK return IOE_OK */
00590   return IOE_OK;
00591 }
00592
00593 /**
00594   * @brief  Configures the selected source to generate or not a global interrupt
00595   * @param DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR
00596   * @param Global_IT: the interrupt source to be configured, could be:
00597   *   @arg  Global_IT_GPIO : All IOs interrupt
00598   *   @arg  Global_IT_ADC : ADC interrupt
00599   *   @arg  Global_IT_TEMP : Temperature Sensor interrupts
00600   *   @arg  Global_IT_FE : Touch Screen Controller FIFO Error interrupt
00601   *   @arg  Global_IT_FF : Touch Screen Controller FIFO Full interrupt
00602   *   @arg  Global_IT_FOV : Touch Screen Controller FIFO Overrun interrupt
00603   *   @arg  Global_IT_FTH : Touch Screen Controller FIFO Threshold interrupt
00604   *   @arg  Global_IT_TOUCH : Touch Screen Controller Touch Detected interrupt
00605   * @retval IOE_OK: if all initializations are OK. Other value if error.
00606   */
00607 uint8_t IOE_GITConfig(uint8_t DeviceAddr, uint8_t Global_IT, FunctionalState NewState)
00608 {
00609   uint8_t tmp = 0;
00610
00611   /* Get the current value of the INT_EN register */
00612   tmp = I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_INT_EN);
00613
00614   if (NewState != DISABLE)
00615   {
00616     /* Set the interrupts to be Enabled */
00617     tmp |= (uint8_t)Global_IT;
00618   }
00619   else
00620   {
00621     /* Set the interrupts to be Disabled */
00622     tmp &= ~(uint8_t)Global_IT;
00623   }
00624   /* Set the register */
00625   I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_INT_EN, tmp);
00626
00627   /* If all OK return IOE_OK */
00628   return IOE_OK;
00629 }
00630
00631 /**
00632   * @brief  Configures the selected pins to generate an interrupt or not.
00633   * @param  DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR.
00634   * @param  IO_IT: The IO interrupt to be configured. This parameter could be any
00635   *         combination of the following values:
00636   *   @arg  IO_IT_x: where x can be from 0 to 7.
00637   * @param  NewState: could be ENABLE or DISABLE.
00638   * @retval IOE_OK: if all initializations are OK. Other value if error.
00639   */
00640 uint8_t IOE_IOITConfig(uint8_t DeviceAddr, uint8_t IO_IT, FunctionalState NewState)
00641 {
00642   uint8_t tmp = 0;
00643
00644   tmp = I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_GPIO_INT_EN);
00645
00646   if (NewState != DISABLE)
00647   {
00648     /* Set the interrupts to be Enabled */
00649     tmp |= (uint8_t)IO_IT;
00650   }
00651   else
00652   {
00653     /* Set the interrupts to be Disabled */
00654     tmp &= ~(uint8_t)IO_IT;
00655   }
00656
00657   /* Set the register */
00658   I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_GPIO_INT_EN, tmp);
00659
00660   /* If all OK return IOE_OK */
00661   return IOE_OK;
00662 }
00663
00664 /**
00665   * @brief  Configures the touch Screen Controller (Single point detection)
00666   * @param  None
00667   * @retval IOE_OK if all initializations are OK. Other value if error.
00668   */
00669 uint8_t IOE_TS_Config(void)
00670 {
00671   uint8_t tmp = 0;
00672
00673   /* Enable TSC Fct: already done in IOE_Config */
00674   tmp = I2C_ReadDeviceRegister(IOE_1_ADDR, IOE_REG_SYS_CTRL2);
00675   tmp &= ~(uint32_t)(IOE_TS_FCT | IOE_ADC_FCT);
00676   I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_SYS_CTRL2, tmp);
00677
00678   /* Enable the TSC gloabl interrupts */
00679   tmp = I2C_ReadDeviceRegister(IOE_1_ADDR, IOE_REG_INT_EN);
00680   tmp |= (uint32_t)(IOE_GIT_TOUCH | IOE_GIT_FTH | IOE_GIT_FOV);
00681   I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_INT_EN, tmp);
00682
00683   /* Select Sample Time, bit number and ADC Reference */
00684   I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_ADC_CTRL1, 0x49);
00685
00686   /* Wait for ~20 ms */
00687   _delay_(2);
00688
00689   /* Select the ADC clock speed: 3.25 MHz */
00690   I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_ADC_CTRL2, 0x01);
00691
00692   /* Select TSC pins in non default mode */
00693   tmp = I2C_ReadDeviceRegister(IOE_1_ADDR, IOE_REG_GPIO_AF);
00694   tmp &= ~(uint8_t)TOUCH_IO_ALL;
00695   I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_GPIO_AF, tmp);
00696
00697   /* Select 2 nF filter capacitor */
00698   I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_TSC_CFG, 0x9A);
00699
00700   /* Select single point reading  */
00701   I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_FIFO_TH, 0x01);
00702
00703   /* Write 0x01 to clear the FIFO memory content. */
00704   I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_FIFO_STA, 0x01);
00705
00706   /* Write 0x00 to put the FIFO back into operation mode  */
00707   I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_FIFO_STA, 0x00);
00708
00709   /* set the data format for Z value: 7 fractional part and 1 whole part */
00710   I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_TSC_FRACT_XYZ, 0x01);
00711
00712   /* set the driving capability of the device for TSC pins: 50mA */
00713   I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_TSC_I_DRIVE, 0x01);
00714
00715   /* Use no tracking index, touchscreen controller operation mode (XYZ) and
00716      enable the TSC */
00717   I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_TSC_CTRL, 0x01);
00718
00719   /*  Clear all the status pending bits */
00720   I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_INT_STA, 0xFF);
00721
00722   /* Initialize the TS structure to their default values */
00723   TS_State.TouchDetected = TS_State.X = TS_State.Y = TS_State.Z = 0;
00724
00725   /* All configuration done */
00726   return IOE_OK;
00727 }
00728
00729 /**
00730   * @brief  Configures and enables the Temperature sensor module.
00731   * @param  None
00732   * @retval IOE_OK if all initializations are OK. Other value if error.
00733   */
00734 uint8_t IOE_TempSens_Config(void)
00735 {
00736   __IO uint8_t tmp = 0;
00737
00738   /* Enable Temperature Sensor Fct: already done in IOE_Config */
00739   tmp = I2C_ReadDeviceRegister(IOE_1_ADDR, IOE_REG_SYS_CTRL2);
00740   tmp &= ~(uint32_t)(IOE_TEMPSENS_FCT | IOE_ADC_FCT);
00741   I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_SYS_CTRL2, tmp);
00742
00743   /* Enable the TEMPSENS module */
00744   I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_TEMP_CTRL, 0x01);
00745
00746   /* Aquire data enable */
00747   I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_TEMP_CTRL, 0x3);
00748
00749   /* All configuration done */
00750   return IOE_OK;
00751 }
00752
00753 /**
00754   * @brief  Configures the selected pin to be in Alternate function or not
00755   * @param  DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR.
00756   * @param  IO_Pin: IO_Pin_x, Where x can be from 0 to 7.
00757   * @param  NewState: State of the AF for the selected pin, could be
00758   *         ENABLE or DISABLE.
00759   * @retval IOE_OK: if all initializations are OK. Other value if error.
00760   */
00761 uint8_t IOE_IOAFConfig(uint8_t DeviceAddr, uint8_t IO_Pin, FunctionalState NewState)
00762 {
00763   uint8_t tmp = 0;
00764
00765   /* Get the current state of the GPIO_AF register */
00766   tmp = I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_GPIO_AF);
00767
00768   if (NewState != DISABLE)
00769   {
00770     /* Enable the selected pins alternate function */
00771     tmp |= (uint8_t)IO_Pin;
00772   }
00773   else
00774   {
00775     /* Disable the selected pins alternate function */
00776     tmp &= ~(uint8_t)IO_Pin;
00777   }
00778
00779   /* Write back the new valu in GPIO_AF register */
00780   I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_GPIO_AF, tmp);
00781
00782   /* If all OK return IOE_OK */
00783   return IOE_OK;
00784 }
00785
00786 /**
00787   * @brief  Configures the Edge for which a transition is detectable for the
00788   *         the selected pin.
00789   * @param  DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR.
00790   * @param  IO_Pin: IO_Pin_x, Where x can be from 0 to 7.
00791   * @param  Edge: The edge which will be detected. This parameter can be one or a
00792   *         a combination of follwing values: EDGE_FALLING and EDGE_RISING .
00793   * @retval IOE_OK: if all initializations are OK. Other value if error.
00794   */
00795 uint8_t IOE_IOEdgeConfig(uint8_t DeviceAddr, uint8_t IO_Pin, uint8_t Edge)
00796 {
00797   uint8_t tmp1 = 0, tmp2 = 0;
00798
00799   /* Get the registers values */
00800   tmp1 = I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_GPIO_FE);
00801   tmp2 = I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_GPIO_RE);
00802
00803   /* Disable the Falling Edge */
00804   tmp1 &= ~(uint8_t)IO_Pin;
00805   /* Disable the Falling Edge */
00806   tmp2 &= ~(uint8_t)IO_Pin;
00807
00808   /* Enable the Falling edge if selected */
00809   if (Edge & EDGE_FALLING)
00810   {
00811     tmp1 |= (uint8_t)IO_Pin;
00812   }
00813
00814   /* Enable the Rising edge if selected */
00815   if (Edge & EDGE_RISING)
00816   {
00817     tmp2 |= (uint8_t)IO_Pin;
00818   }
00819
00820   /* Write back the registers values */
00821   I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_GPIO_FE, tmp1);
00822   I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_GPIO_RE, tmp2);
00823
00824   /* if OK return 0 */
00825   return IOE_OK;
00826 }
00827
00828 /**
00829   * @brief  Configures the Interrupt line active state and format (level/edge)
00830   * @param  Polarity: could be
00831   *   @arg  Polarity_Low: Interrupt line is active Low/Falling edge
00832   *   @arg  Polarity_High: Interrupt line is active High/Rising edge
00833   * @param  Type: Interrupt line activity type, could be one of the following values
00834   *   @arg  Type_Level: Interrupt line is active in level model
00835   *   @arg  Type_Edge: Interrupt line is active in edge model
00836   * @retval IOE_OK: if all initializations are OK. Other value if error.
00837   */
00838 uint8_t IOE_ITOutConfig(uint8_t Polarity, uint8_t Type)
00839 {
00840   uint8_t tmp = 0;
00841
00842   /*  Get the register IOE_REG_INT_CTRL value */
00843   tmp = I2C_ReadDeviceRegister(IOE_1_ADDR, IOE_REG_INT_CTRL);
00844
00845   /* Mask the polarity and type bits */
00846   tmp &= ~(uint8_t)0x06;
00847
00848   /* Modify the Interrupt Output line configuration */
00849   tmp |= (uint8_t)(Polarity | Type);
00850
00851   /* Set the register */
00852   I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_INT_CTRL, tmp);
00853
00854   /* If all OK return IOE_OK */
00855   return IOE_OK;
00856 }
00857
00858 /**
00859   * @brief  Writes a value in a register of the device through I2C.
00860   * @param  DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR.
00861   * @param  RegisterAddr: The target register adress
00862   * @param  RegisterValue: The target register value to be written
00863   * @retval IOE_OK: if all operations are OK. Other value if error.
00864   */
00865 uint8_t I2C_WriteDeviceRegister(uint8_t DeviceAddr, uint8_t RegisterAddr, uint8_t RegisterValue)
00866 {
00867   uint32_t read_verif = 0;
00868   uint8_t IOE_BufferTX = 0;
00869
00870   /* Get Value to be written */
00871   IOE_BufferTX = RegisterValue;
00872
00873   /* Configure DMA Peripheral */
00874   IOE_DMA_Config(IOE_DMA_TX, (uint8_t*)(&IOE_BufferTX));
00875
00876   /* Enable the I2C peripheral */
00877   I2C_GenerateSTART(IOE_I2C, ENABLE);
00878
00879   /* Test on SB Flag */
00880   IOE_TimeOut = TIMEOUT_MAX;
00881   while (I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_SB) == RESET)
00882   {
00883     if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback());
00884   }
00885
00886   /* Transmit the slave address and enable writing operation */
00887   I2C_Send7bitAddress(IOE_I2C, DeviceAddr, I2C_Direction_Transmitter);
00888
00889   /* Test on ADDR Flag */
00890   IOE_TimeOut = TIMEOUT_MAX;
00891   while (!I2C_CheckEvent(IOE_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED))
00892   {
00893     if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback());
00894   }
00895
00896   /* Transmit the first address for r/w operations */
00897   I2C_SendData(IOE_I2C, RegisterAddr);
00898
00899   /* Test on TXE FLag (data dent) */
00900   IOE_TimeOut = TIMEOUT_MAX;
00901   while ((!I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_TXE)) && (!I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_BTF)))
00902   {
00903     if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback());
00904   }
00905
00906   /* Enable I2C DMA request */
00907   I2C_DMACmd(IOE_I2C,ENABLE);
00908
00909   /* Enable DMA TX Channel */
00910   DMA_Cmd(IOE_DMA_TX_CHANNEL, ENABLE);
00911
00912   /* Wait until DMA Transfer Complete */
00913   IOE_TimeOut = TIMEOUT_MAX;
00914   while (!DMA_GetFlagStatus(IOE_DMA_TX_TCFLAG))
00915   {
00916     if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback());
00917   }
00918
00919   /* Wait until BTF Flag is set before generating STOP */
00920   IOE_TimeOut = 2 * TIMEOUT_MAX;
00921   while ((!I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_BTF)))
00922   {
00923   }
00924
00925   /* Send STOP Condition */
00926   I2C_GenerateSTOP(IOE_I2C, ENABLE);
00927
00928   /* Disable DMA TX Channel */
00929   DMA_Cmd(IOE_DMA_TX_CHANNEL, DISABLE);
00930
00931   /* Disable I2C DMA request */
00932   I2C_DMACmd(IOE_I2C,DISABLE);
00933
00934   /* Clear DMA TX Transfer Complete Flag */
00935   DMA_ClearFlag(IOE_DMA_TX_TCFLAG);
00936
00937 #ifdef VERIFY_WRITTENDATA
00938   /* Verify (if needed) that the loaded data is correct  */
00939
00940   /* Read the just written register*/
00941   read_verif = I2C_ReadDeviceRegister(DeviceAddr, RegisterAddr);
00942   /* Load the register and verify its value  */
00943   if (read_verif != RegisterValue)
00944   {
00945     /* Control data wrongly tranfered */
00946     read_verif = IOE_FAILURE;
00947   }
00948   else
00949   {
00950     /* Control data correctly transfered */
00951     read_verif = 0;
00952   }
00953 #endif
00954
00955   /* Return the verifying value: 0 (Passed) or 1 (Failed) */
00956   return read_verif;
00957 }
00958
00959 /**
00960   * @brief  Reads a register of the device through I2C.
00961   * @param  DeviceAddr: The address of the device, could be : IOE_1_ADDR.
00962   * @param  RegisterAddr: The target register adress (between 00x and 0x24)
00963   * @retval The value of the read register (0xAA if Timout occured)
00964   */
00965 uint8_t I2C_ReadDeviceRegister(uint8_t DeviceAddr, uint8_t RegisterAddr)
00966 {
00967   uint8_t IOE_BufferRX[2] = {0x00, 0x00};
00968
00969   /* Configure DMA Peripheral */
00970   IOE_DMA_Config(IOE_DMA_RX, (uint8_t*)IOE_BufferRX);
00971
00972   /* Enable DMA NACK automatic generation */
00973   I2C_DMALastTransferCmd(IOE_I2C, ENABLE);
00974
00975   /* Enable the I2C peripheral */
00976   I2C_GenerateSTART(IOE_I2C, ENABLE);
00977
00978   /* Test on SB Flag */
00979   IOE_TimeOut = TIMEOUT_MAX;
00980   while (!I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_SB))
00981   {
00982     if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback());
00983   }
00984
00985   /* Send device address for write */
00986   I2C_Send7bitAddress(IOE_I2C, DeviceAddr, I2C_Direction_Transmitter);
00987
00988   /* Test on ADDR Flag */
00989   IOE_TimeOut = TIMEOUT_MAX;
00990   while (!I2C_CheckEvent(IOE_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED))
00991   {
00992     if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback());
00993   }
00994
00995   /* Send the device's internal address to write to */
00996   I2C_SendData(IOE_I2C, RegisterAddr);
00997
00998   /* Test on TXE FLag (data dent) */
00999   IOE_TimeOut = TIMEOUT_MAX;
01000   while ((!I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_TXE)) && (!I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_BTF)))
01001   {
01002     if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback());
01003   }
01004
01005   /* Send START condition a second time */
01006   I2C_GenerateSTART(IOE_I2C, ENABLE);
01007
01008   /* Test on SB Flag */
01009   IOE_TimeOut = TIMEOUT_MAX;
01010   while (!I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_SB))
01011   {
01012     if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback());
01013   }
01014
01015   /* Send IOExpander address for read */
01016   I2C_Send7bitAddress(IOE_I2C, DeviceAddr, I2C_Direction_Receiver);
01017
01018   /* Test on ADDR Flag */
01019   IOE_TimeOut = TIMEOUT_MAX;
01020   while (!I2C_CheckEvent(IOE_I2C, I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED))
01021   {
01022     if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback());
01023   }
01024
01025   /* Enable I2C DMA request */
01026   I2C_DMACmd(IOE_I2C,ENABLE);
01027
01028   /* Enable DMA RX Channel */
01029   DMA_Cmd(IOE_DMA_RX_CHANNEL, ENABLE);
01030
01031   /* Wait until DMA Transfer Complete */
01032   IOE_TimeOut = 2 * TIMEOUT_MAX;
01033   while (!DMA_GetFlagStatus(IOE_DMA_RX_TCFLAG))
01034   {
01035     if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback());
01036   }
01037
01038   /* Send STOP Condition */
01039   I2C_GenerateSTOP(IOE_I2C, ENABLE);
01040
01041   /* Disable DMA RX Channel */
01042   DMA_Cmd(IOE_DMA_RX_CHANNEL, DISABLE);
01043
01044   /* Disable I2C DMA request */
01045   I2C_DMACmd(IOE_I2C,DISABLE);
01046
01047   /* Clear DMA RX Transfer Complete Flag */
01048   DMA_ClearFlag(IOE_DMA_RX_TCFLAG);
01049
01050   /* return a pointer to the IOE_Buffer */
01051   return (uint8_t)IOE_BufferRX[0];
01052 }
01053
01054
01055 /**
01056   * @brief  Reads a buffer of 2 bytes from the device registers.
01057   * @param  DeviceAddr: The address of the device, could be : IOE_1_ADDR.
01058   * @param  RegisterAddr: The target register adress (between 00x and 0x24)
01059   * @retval A pointer to the buffer containing the two returned bytes (in halfword).
01060   */
01061 uint16_t I2C_ReadDataBuffer(uint8_t DeviceAddr, uint32_t RegisterAddr)
01062 {
01063   uint8_t tmp= 0;
01064   uint8_t IOE_BufferRX[2] = {0x00, 0x00};
01065
01066   /* Configure DMA Peripheral */
01067   IOE_DMA_Config(IOE_DMA_RX, (uint8_t*)IOE_BufferRX);
01068
01069   /* Enable DMA NACK automatic generation */
01070   I2C_DMALastTransferCmd(IOE_I2C, ENABLE);
01071
01072   /* Enable the I2C peripheral */
01073   I2C_GenerateSTART(IOE_I2C, ENABLE);
01074
01075   /* Test on SB Flag */
01076   IOE_TimeOut = TIMEOUT_MAX;
01077   while (!I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_SB))
01078   {
01079     if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback());
01080   }
01081
01082   /* Send device address for write */
01083   I2C_Send7bitAddress(IOE_I2C, DeviceAddr, I2C_Direction_Transmitter);
01084
01085   /* Test on ADDR Flag */
01086   IOE_TimeOut = TIMEOUT_MAX;
01087   while (!I2C_CheckEvent(IOE_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED))
01088   {
01089     if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback());
01090   }
01091
01092   /* Send the device's internal address to write to */
01093   I2C_SendData(IOE_I2C, RegisterAddr);
01094
01095   /* Test on TXE FLag (data dent) */
01096   IOE_TimeOut = TIMEOUT_MAX;
01097   while ((!I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_TXE)) && (!I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_BTF)))
01098   {
01099     if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback());
01100   }
01101
01102   /* Send START condition a second time */
01103   I2C_GenerateSTART(IOE_I2C, ENABLE);
01104
01105   /* Test on SB Flag */
01106   IOE_TimeOut = TIMEOUT_MAX;
01107   while (!I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_SB))
01108   {
01109     if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback());
01110   }
01111
01112   /* Send IOExpander address for read */
01113   I2C_Send7bitAddress(IOE_I2C, DeviceAddr, I2C_Direction_Receiver);
01114
01115   /* Test on ADDR Flag */
01116   IOE_TimeOut = TIMEOUT_MAX;
01117   while (!I2C_CheckEvent(IOE_I2C, I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED))
01118   {
01119     if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback());
01120   }
01121
01122   /* Enable I2C DMA request */
01123   I2C_DMACmd(IOE_I2C,ENABLE);
01124
01125   /* Enable DMA RX Channel */
01126   DMA_Cmd(IOE_DMA_RX_CHANNEL, ENABLE);
01127
01128   /* Wait until DMA Transfer Complete */
01129   IOE_TimeOut = 2 * TIMEOUT_MAX;
01130   while (!DMA_GetFlagStatus(IOE_DMA_RX_TCFLAG))
01131   {
01132     if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback());
01133   }
01134
01135   /* Send STOP Condition */
01136   I2C_GenerateSTOP(IOE_I2C, ENABLE);
01137
01138   /* Disable DMA RX Channel */
01139   DMA_Cmd(IOE_DMA_RX_CHANNEL, DISABLE);
01140
01141   /* Disable I2C DMA request */
01142   I2C_DMACmd(IOE_I2C,DISABLE);
01143
01144   /* Clear DMA RX Transfer Complete Flag */
01145   DMA_ClearFlag(IOE_DMA_RX_TCFLAG);
01146
01147   /* Reorganize received data */
01148   tmp = IOE_BufferRX[0];
01149   IOE_BufferRX[0] = IOE_BufferRX[1];
01150   IOE_BufferRX[1] = tmp;
01151
01152   /* return a pointer to the IOE_Buffer */
01153   return *(uint16_t *)IOE_BufferRX;
01154 }
01155
01156 /**
01157   * @brief  Return Touch Screen X position value
01158   * @param  None
01159   * @retval X position.
01160   */
01161 static uint16_t IOE_TS_Read_X(void)
01162 {
01163   int32_t x, xr;
01164
01165   x = I2C_ReadDataBuffer(IOE_1_ADDR, IOE_REG_TSC_DATA_Y);
01166
01167   /* first correction */
01168   xr =  (x * 320) >> 12;
01169   /* second correction */
01170   xr = ((xr * 32)/29) - 17;
01171
01172   if(xr <= 0)
01173     xr = 0;
01174
01175   return (uint16_t)(xr);
01176 }
01177
01178 /**
01179   * @brief  Return Touch Screen Y position value
01180   * @param  None
01181   * @retval Y position.
01182   */
01183 static uint16_t IOE_TS_Read_Y(void)
01184 {
01185   int32_t y, yr;
01186   y= I2C_ReadDataBuffer(IOE_1_ADDR, IOE_REG_TSC_DATA_X);
01187
01188   yr= (y * 240) >> 12;
01189   yr = ((yr * 240) / 217) - 12;
01190
01191   if(yr <= 0)
01192     yr = 0;
01193
01194   return (uint16_t)(yr);
01195 }
01196
01197 /**
01198   * @brief  Return Touch Screen Z position value
01199   * @param  None
01200   * @retval Z position.
01201   */
01202 static uint16_t IOE_TS_Read_Z(void)
01203 {
01204   uint32_t z;
01205   z = I2C_ReadDataBuffer(IOE_1_ADDR, IOE_REG_TSC_DATA_Z);
01206
01207
01208   if(z <= 0)
01209     z = 0;
01210
01211   return (uint16_t)(z);
01212 }
01213
01214 /**
01215   * @brief  Initializes the GPIO pins used by the IO expander.
01216   * @param  None
01217   * @retval None
01218   */
01219 static void IOE_GPIO_Config(void)
01220 {
01221   GPIO_InitTypeDef GPIO_InitStructure;
01222
01223   /* Enable IOE_I2C and IOE_I2C_PORT & Alternate Function clocks */
01224   RCC_APB1PeriphClockCmd(IOE_I2C_CLK, ENABLE);
01225   RCC_APB2PeriphClockCmd(IOE_I2C_SCL_GPIO_CLK | IOE_I2C_SDA_GPIO_CLK | IOE_IT_GPIO_CLK
01226                          | RCC_APB2Periph_AFIO, ENABLE);
01227
01228   /* Reset IOE_I2C IP */
01229   RCC_APB1PeriphResetCmd(IOE_I2C_CLK, ENABLE);
01230
01231   /* Release reset signal of IOE_I2C IP */
01232   RCC_APB1PeriphResetCmd(IOE_I2C_CLK, DISABLE);
01233
01234   /* IOE_I2C SCL and SDA pins configuration */
01235   GPIO_InitStructure.GPIO_Pin = IOE_I2C_SCL_PIN;
01236   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_10MHz;
01237   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_OD;
01238   GPIO_Init(IOE_I2C_SCL_GPIO_PORT, &GPIO_InitStructure);
01239
01240   /* IOE_I2C SCL and SDA pins configuration */
01241   GPIO_InitStructure.GPIO_Pin = IOE_I2C_SDA_PIN;
01242   GPIO_Init(IOE_I2C_SDA_GPIO_PORT, &GPIO_InitStructure);
01243
01244   /* Set EXTI pin as Input PullUp - IO_Expander_INT */
01245   GPIO_InitStructure.GPIO_Pin = IOE_IT_PIN;
01246   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
01247   GPIO_Init(IOE_IT_GPIO_PORT, &GPIO_InitStructure);
01248
01249   /* Connect IO Expander IT line to EXTI line */
01250   GPIO_EXTILineConfig(IOE_IT_EXTI_PORT_SOURCE, IOE_IT_EXTI_PIN_SOURCE);
01251 }
01252
01253
01254 /**
01255   * @brief  Configure the I2C Peripheral used to communicate with IO_Expanders.
01256   * @param  None
01257   * @retval None
01258   */
01259 static void IOE_I2C_Config(void)
01260 {
01261   I2C_InitTypeDef I2C_InitStructure;
01262
01263   /* IOE_I2C configuration */
01264   I2C_InitStructure.I2C_Mode = I2C_Mode_I2C;
01265   I2C_InitStructure.I2C_DutyCycle = I2C_DutyCycle_2;
01266   I2C_InitStructure.I2C_OwnAddress1 = 0x00;
01267   I2C_InitStructure.I2C_Ack = I2C_Ack_Enable;
01268   I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
01269   I2C_InitStructure.I2C_ClockSpeed = IOE_I2C_SPEED;
01270
01271   I2C_Init(IOE_I2C, &I2C_InitStructure);
01272 }
01273
01274
01275 /**
01276   * @brief  Configure the DMA Peripheral used to handle communication via I2C.
01277   * @param  None
01278   * @retval None
01279   */
01280
01281 static void IOE_DMA_Config(IOE_DMADirection_TypeDef Direction, uint8_t* buffer)
01282 {
01283   DMA_InitTypeDef DMA_InitStructure;
01284
01285   RCC_AHBPeriphClockCmd(IOE_DMA_CLK, ENABLE);
01286
01287   /* Initialize the DMA_PeripheralBaseAddr member */
01288   DMA_InitStructure.DMA_PeripheralBaseAddr = IOE_I2C_DR;
01289   /* Initialize the DMA_MemoryBaseAddr member */
01290   DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)buffer;
01291    /* Initialize the DMA_PeripheralInc member */
01292   DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
01293   /* Initialize the DMA_MemoryInc member */
01294   DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
01295   /* Initialize the DMA_PeripheralDataSize member */
01296   DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
01297   /* Initialize the DMA_MemoryDataSize member */
01298   DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
01299   /* Initialize the DMA_Mode member */
01300   DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
01301   /* Initialize the DMA_Priority member */
01302   DMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh;
01303   /* Initialize the DMA_M2M member */
01304   DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
01305
01306   /* If using DMA for Reception */
01307   if (Direction == IOE_DMA_RX)
01308   {
01309     /* Initialize the DMA_DIR member */
01310     DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
01311
01312     /* Initialize the DMA_BufferSize member */
01313     DMA_InitStructure.DMA_BufferSize = 2;
01314
01315     DMA_DeInit(IOE_DMA_RX_CHANNEL);
01316
01317     DMA_Init(IOE_DMA_RX_CHANNEL, &DMA_InitStructure);
01318   }
01319    /* If using DMA for Transmission */
01320   else if (Direction == IOE_DMA_TX)
01321   {
01322     /* Initialize the DMA_DIR member */
01323     DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
01324
01325     /* Initialize the DMA_BufferSize member */
01326     DMA_InitStructure.DMA_BufferSize = 1;
01327
01328     DMA_DeInit(IOE_DMA_TX_CHANNEL);
01329
01330     DMA_Init(IOE_DMA_TX_CHANNEL, &DMA_InitStructure);
01331   }
01332 }
01333
01334 /**
01335   * @brief  Configures the IO expander Interrupt line and GPIO in EXTI mode.
01336   * @param  None
01337   * @retval None
01338   */
01339 static void IOE_EXTI_Config(void)
01340 {
01341   GPIO_InitTypeDef GPIO_InitStructure;
01342   NVIC_InitTypeDef NVIC_InitStructure;
01343   EXTI_InitTypeDef EXTI_InitStructure;
01344
01345   /* Enable Button GPIO clock */
01346   RCC_APB2PeriphClockCmd(IOE_IT_GPIO_CLK | RCC_APB2Periph_AFIO, ENABLE);
01347
01348   /* Configure Button pin as input floating */
01349   GPIO_InitStructure.GPIO_Pin = IOE_IT_PIN;
01350   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
01351   GPIO_Init(IOE_IT_GPIO_PORT, &GPIO_InitStructure);
01352
01353   /* Connect Button EXTI Line to Button GPIO Pin */
01354   GPIO_EXTILineConfig(IOE_IT_EXTI_PORT_SOURCE, IOE_IT_EXTI_PIN_SOURCE);
01355
01356   /* Configure Button EXTI line */
01357   EXTI_InitStructure.EXTI_Line = IOE_IT_EXTI_LINE;
01358   EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
01359   EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising_Falling;
01360   EXTI_InitStructure.EXTI_LineCmd = ENABLE;
01361   EXTI_Init(&EXTI_InitStructure);
01362
01363   /* Enable and set Button EXTI Interrupt to the lowest priority */
01364   NVIC_InitStructure.NVIC_IRQChannel = IOE_IT_EXTI_IRQn;
01365   NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x0F;
01366   NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x0F;
01367   NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
01368   NVIC_Init(&NVIC_InitStructure);
01369 }
01370
01371 #ifndef USE_Delay
01372 /**
01373   * @brief  Inserts a delay time.
01374   * @param  nCount: specifies the delay time length.
01375   * @retval None
01376   */
01377 static void delay(__IO uint32_t nCount)
01378 {
01379   __IO uint32_t index = 0;
01380   for(index = (100000 * nCount); index != 0; index--)
01381   {
01382   }
01383 }
01384 #endif /* USE_Delay*/
01385 /**
01386   * @}
01387   */
01388
01389 /**
01390   * @}
01391   */
01392
01393 /**
01394   * @}
01395   */
01396
01397 /**
01398   * @}
01399   */
01400
01401 /**
01402   * @}
01403   */
01404
01405 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32100e_eval_ioe.h Source File

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stm32100e_eval_ioe.h

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32100e_eval_ioe.h
00004   * @author  MCD Application Team
00005   * @version V4.5.0
00006   * @date    07-March-2011
00007   * @brief   This file contains all the functions prototypes for the IO Expander
00008   *   firmware driver.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00013   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00014   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00015   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00016   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00017   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00018   *
00019   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00020   ******************************************************************************
00021   */
00022
00023   /* File Info : ---------------------------------------------------------------
00024     SUPPORTED FEATURES:
00025       - Touch Screen Features: Single point mode (Polling/Interrupt).
00026       - TempSensor Feature: accuracy not determined (Polling).
00027       - IO Read/write : Set/Reset and Read (Polling/Interrupt).
00028
00029     UNSUPPORTED FEATURES:
00030       - Row ADC Feature is not supported (not implemented on STM32100E-EVAL board)
00031       - Joystick: config and Read (Polling/Interrupt)
00032 ----------------------------------------------------------------------------*/
00033
00034
00035 /* Define to prevent recursive inclusion -------------------------------------*/
00036 #ifndef __STM32100E_EVAL_IOE_H
00037 #define __STM32100E_EVAL_IOE_H
00038
00039 #ifdef __cplusplus
00040  extern "C" {
00041 #endif
00042
00043 /* Includes ------------------------------------------------------------------*/
00044 #include "stm32f10x.h"
00045
00046 /** @addtogroup Utilities
00047   * @{
00048   */
00049
00050 /** @addtogroup STM32_EVAL
00051   * @{
00052   */
00053
00054 /** @addtogroup STM32100E_EVAL
00055   * @{
00056   */
00057
00058 /** @defgroup STM32100E_EVAL_IOE
00059   * @{
00060   */
00061
00062 /** @defgroup STM32100E_EVAL_IOE_Exported_Types
00063   * @{
00064   */
00065
00066 /**
00067   * @brief  Touch Screen Information structure
00068   */
00069 typedef struct
00070 {
00071   uint16_t TouchDetected;
00072   uint16_t X;
00073   uint16_t Y;
00074   uint16_t Z;
00075 }TS_STATE;
00076
00077
00078 /**
00079   * @brief  IO_Expander Error codes
00080   */
00081 typedef enum
00082 {
00083   IOE_OK = 0,
00084   IOE_FAILURE,
00085   IOE_TIMEOUT,
00086   PARAM_ERROR,
00087   IOE1_NOT_OPERATIONAL
00088 }IOE_Status_TypDef;
00089
00090 /**
00091   * @brief  IO bit values
00092   */
00093 typedef enum
00094 {
00095   BitReset = 0,
00096   BitSet = 1
00097 }IOE_BitValue_TypeDef;
00098
00099 /**
00100   * @brief  IOE DMA Direction
00101   */
00102 typedef enum
00103 {
00104   IOE_DMA_TX = 0,
00105   IOE_DMA_RX = 1
00106 }IOE_DMADirection_TypeDef;
00107
00108 /**
00109   * @}
00110   */
00111
00112 /** @defgroup STM32100E_EVAL_IOE_Exported_Constants
00113   * @{
00114   */
00115
00116 /**
00117  * @brief Uncomment the line below to enable verfying each written byte in write
00118  *        operation. The I2C_WriteDeviceRegister() function will then compare the
00119  *        written and read data and return error status if a mismatch occurs.
00120  */
00121 /* #define VERIFY_WRITTENDATA */
00122
00123 /**
00124  * @brief Uncomment the line below if you want to use user defined Delay function
00125  *        (for precise timing), otherwise default _delay_ function defined within
00126  *         this driver is used (less precise timing).
00127  */
00128 /* #define USE_Delay */
00129
00130 /**
00131  * @brief Uncomment the line below if you want to use user timeout callback.
00132  *        Function prototypes is declared in this file but function body may be
00133  *        implemented into user application.
00134  */
00135 /* #define USE_TIMEOUT_USER_CALLBACK */
00136
00137 #ifdef USE_Delay
00138 #include "main.h"
00139
00140   #define _delay_     Delay  /* !< User can provide more timing precise _delay_ function
00141                                    (with 10ms time base), using SysTick for example */
00142 #else
00143   #define _delay_     delay      /* !< Default _delay_ function with less precise timing */
00144 #endif
00145
00146 /*------------------------------------------------------------------------------
00147     Hardware Configuration
00148 ------------------------------------------------------------------------------*/
00149 /**
00150   * @brief  I2C port definitions
00151   */
00152 #define IOE_I2C                          I2C2
00153 #define IOE_I2C_CLK                      RCC_APB1Periph_I2C2
00154 #define IOE_I2C_SCL_PIN                  GPIO_Pin_10
00155 #define IOE_I2C_SCL_GPIO_PORT            GPIOB
00156 #define IOE_I2C_SCL_GPIO_CLK             RCC_APB2Periph_GPIOB
00157 #define IOE_I2C_SDA_PIN                  GPIO_Pin_11
00158 #define IOE_I2C_SDA_GPIO_PORT            GPIOB
00159 #define IOE_I2C_SDA_GPIO_CLK             RCC_APB2Periph_GPIOB
00160 #define IOE_I2C_DR                       ((uint32_t)0x40005810)
00161 #define IOE_I2C_SPEED                    300000
00162
00163 /**
00164   * @brief  IOE DMA definitions
00165   */
00166 #define IOE_DMA                          DMA1
00167 #define IOE_DMA_CLK                      RCC_AHBPeriph_DMA1
00168 #define IOE_DMA_TX_CHANNEL               DMA1_Channel4
00169 #define IOE_DMA_RX_CHANNEL               DMA1_Channel5
00170 #define IOE_DMA_TX_TCFLAG                DMA1_FLAG_TC4
00171 #define IOE_DMA_RX_TCFLAG                DMA1_FLAG_TC5
00172
00173
00174 /**
00175   * @brief  IO Expander Interrupt line on EXTI
00176   */
00177 #define IOE_IT_PIN                       GPIO_Pin_12
00178 #define IOE_IT_GPIO_PORT                 GPIOA
00179 #define IOE_IT_GPIO_CLK                  RCC_APB2Periph_GPIOA
00180 #define IOE_IT_EXTI_PORT_SOURCE          GPIO_PortSourceGPIOA
00181 #define IOE_IT_EXTI_PIN_SOURCE           GPIO_PinSource12
00182 #define IOE_IT_EXTI_LINE                 EXTI_Line12
00183 #define IOE_IT_EXTI_IRQn                 EXTI15_10_IRQn
00184
00185
00186 /**
00187   * @brief  The 7 bits IO Expanders adresses and chip IDs
00188   */
00189 #define IOE_1_ADDR                 0x82
00190 #define STMPE811_ID                0x0811
00191
00192
00193 /*------------------------------------------------------------------------------
00194     Functional and Interrupt Management
00195 ------------------------------------------------------------------------------*/
00196 /**
00197   * @brief  IO Expander Functionalities definitions
00198   */
00199 #define IOE_ADC_FCT              0x01
00200 #define IOE_TS_FCT               0x02
00201 #define IOE_IO_FCT               0x04
00202 #define IOE_TEMPSENS_FCT         0x08
00203
00204 /**
00205   * @brief  Interrupt source configuration definitons
00206   */
00207 #define IOE_ITSRC_TSC           0x01  /* IO_Exapnder 1 */
00208 #define IOE_ITSRC_TEMPSENS      0x08  /* IO_Exapnder 1 */
00209
00210 /**
00211   * @brief  Glaobal Interrupts definitions
00212   */
00213 #define IOE_GIT_GPIO             0x80
00214 #define IOE_GIT_ADC              0x40
00215 #define IOE_GIT_TEMP             0x20
00216 #define IOE_GIT_FE               0x10
00217 #define IOE_GIT_FF               0x08
00218 #define IOE_GIT_FOV              0x04
00219 #define IOE_GIT_FTH              0x02
00220 #define IOE_GIT_TOUCH            0x01
00221
00222 /**
00223   * @brief IO Exapanders Pins definition
00224   */
00225 #define IO1_IN_ALL_PINS          (uint32_t)(IO_Pin_ALL)
00226 #define IO1_OUT_ALL_PINS         (uint32_t)(IO_Pin_ALL)
00227
00228
00229 /*------------------------------------------------------------------------------
00230     STMPE811 device register definition
00231 ------------------------------------------------------------------------------*/
00232 /**
00233   * @brief  Identification registers
00234   */
00235 #define IOE_REG_CHP_ID             0x00
00236 #define IOE_REG_ID_VER             0x02
00237
00238 /**
00239   * @brief  General Control Registers
00240   */
00241 #define IOE_REG_SYS_CTRL1          0x03
00242 #define IOE_REG_SYS_CTRL2          0x04
00243 #define IOE_REG_SPI_CFG            0x08
00244
00245 /**
00246   * @brief  Interrupt Control register
00247   */
00248 #define IOE_REG_INT_CTRL           0x09
00249 #define IOE_REG_INT_EN             0x0A
00250 #define IOE_REG_INT_STA            0x0B
00251 #define IOE_REG_GPIO_INT_EN        0x0C
00252 #define IOE_REG_GPIO_INT_STA       0x0D
00253
00254 /**
00255   * @brief  GPIO Registers
00256   */
00257 #define IOE_REG_GPIO_SET_PIN       0x10
00258 #define IOE_REG_GPIO_CLR_PIN       0x11
00259 #define IOE_REG_GPIO_MP_STA        0x12
00260 #define IOE_REG_GPIO_DIR           0x13
00261 #define IOE_REG_GPIO_ED            0x14
00262 #define IOE_REG_GPIO_RE            0x15
00263 #define IOE_REG_GPIO_FE            0x16
00264 #define IOE_REG_GPIO_AF            0x17
00265
00266 /**
00267   * @brief  ADC Registers
00268   */
00269 #define IOE_REG_ADC_INT_EN         0x0E
00270 #define IOE_REG_ADC_INT_STA        0x0F
00271 #define IOE_REG_ADC_CTRL1          0x20
00272 #define IOE_REG_ADC_CTRL2          0x21
00273 #define IOE_REG_ADC_CAPT           0x22
00274 #define IOE_REG_ADC_DATA_CH0       0x30 /* 16-Bit register */
00275 #define IOE_REG_ADC_DATA_CH1       0x32 /* 16-Bit register */
00276 #define IOE_REG_ADC_DATA_CH2       0x34 /* 16-Bit register */
00277 #define IOE_REG_ADC_DATA_CH3       0x36 /* 16-Bit register */
00278 #define IOE_REG_ADC_DATA_CH4       0x38 /* 16-Bit register */
00279 #define IOE_REG_ADC_DATA_CH5       0x3A /* 16-Bit register */
00280 #define IOE_REG_ADC_DATA_CH6       0x3B /* 16-Bit register */
00281 #define IOE_REG_ADC_DATA_CH7       0x3C /* 16-Bit register */
00282
00283 /**
00284   * @brief  TouchScreen Registers
00285   */
00286 #define IOE_REG_TSC_CTRL           0x40
00287 #define IOE_REG_TSC_CFG            0x41
00288 #define IOE_REG_WDM_TR_X           0x42
00289 #define IOE_REG_WDM_TR_Y           0x44
00290 #define IOE_REG_WDM_BL_X           0x46
00291 #define IOE_REG_WDM_BL_Y           0x48
00292 #define IOE_REG_FIFO_TH            0x4A
00293 #define IOE_REG_FIFO_STA           0x4B
00294 #define IOE_REG_FIFO_SIZE          0x4C
00295 #define IOE_REG_TSC_DATA_X         0x4D
00296 #define IOE_REG_TSC_DATA_Y         0x4F
00297 #define IOE_REG_TSC_DATA_Z         0x51
00298 #define IOE_REG_TSC_DATA_XYZ       0x52
00299 #define IOE_REG_TSC_FRACT_XYZ      0x56
00300 #define IOE_REG_TSC_DATA           0x57
00301 #define IOE_REG_TSC_I_DRIVE        0x58
00302 #define IOE_REG_TSC_SHIELD         0x59
00303
00304 /**
00305   * @brief  Temperature Sensor registers
00306   */
00307 #define IOE_REG_TEMP_CTRL          0x60
00308 #define IOE_REG_TEMP_DATA          0x61
00309 #define IOE_REG_TEMP_TH            0x62
00310
00311 /*------------------------------------------------------------------------------
00312     Functions parameters defines
00313 ------------------------------------------------------------------------------*/
00314 /**
00315   * @brief Touch Screen Pins definition
00316   */
00317 #define TOUCH_YD                    IO_Pin_1 /* IO_Exapnader_1 */ /* Input */
00318 #define TOUCH_XD                    IO_Pin_2 /* IO_Exapnader_1 */ /* Input */
00319 #define TOUCH_YU                    IO_Pin_3 /* IO_Exapnader_1 */ /* Input */
00320 #define TOUCH_XU                    IO_Pin_4 /* IO_Exapnader_1 */ /* Input */
00321 #define TOUCH_IO_ALL                (uint32_t)(IO_Pin_1 | IO_Pin_2 | IO_Pin_3 | IO_Pin_4)
00322
00323 /**
00324   * @brief  IO Pins
00325   */
00326 #define IO_Pin_0                 0x01
00327 #define IO_Pin_1                 0x02
00328 #define IO_Pin_2                 0x04
00329 #define IO_Pin_3                 0x08
00330 #define IO_Pin_4                 0x10
00331 #define IO_Pin_5                 0x20
00332 #define IO_Pin_6                 0x40
00333 #define IO_Pin_7                 0x80
00334 #define IO_Pin_ALL               0xFF
00335
00336 /**
00337   * @brief  IO Pin directions
00338   */
00339 #define Direction_IN             0x00
00340 #define Direction_OUT            0x01
00341
00342 /**
00343   * @brief  Interrupt Line output parameters
00344   */
00345 #define Polarity_Low             0x00
00346 #define Polarity_High            0x04
00347 #define Type_Level               0x00
00348 #define Type_Edge                0x02
00349
00350 /**
00351   * @brief IO Interrupts
00352   */
00353 #define IO_IT_0                  0x01
00354 #define IO_IT_1                  0x02
00355 #define IO_IT_2                  0x04
00356 #define IO_IT_3                  0x08
00357 #define IO_IT_4                  0x10
00358 #define IO_IT_5                  0x20
00359 #define IO_IT_6                  0x40
00360 #define IO_IT_7                  0x80
00361 #define ALL_IT                   0xFF
00362 #define IOE_TS_IT                (uint8_t)(IO_IT_0 | IO_IT_1 | IO_IT_2)
00363
00364 /**
00365   * @brief  Edge detection value
00366   */
00367 #define EDGE_FALLING              0x01
00368 #define EDGE_RISING               0x02
00369
00370 /**
00371   * @brief  Global interrupt Enable bit
00372   */
00373 #define IOE_GIT_EN                0x01
00374
00375 /**
00376   * @}
00377   */
00378
00379
00380
00381 /** @defgroup STM32100E_EVAL_IOE_Exported_Macros
00382   * @{
00383   */
00384 /**
00385   * @}
00386   */
00387
00388
00389
00390 /** @defgroup STM32100E_EVAL_IOE_Exported_Functions
00391   * @{
00392   */
00393
00394 /**
00395   * @brief  Configuration and initialization functions
00396   */
00397 uint8_t IOE_Config(void);
00398 uint8_t IOE_ITConfig(uint32_t IOE_ITSRC_Source);
00399
00400 /**
00401   * @brief  Timeout user callback function. This function is called when a timeout
00402   *         condition occurs during communication with IO Expander. Only protoype
00403   *         of this function is decalred in IO Expander driver. Its implementation
00404   *         may be done into user application. This function may typically stop
00405   *         current operations and reset the I2C peripheral and IO Expander.
00406   *         To enable this function use uncomment the define USE_TIMEOUT_USER_CALLBACK
00407   *         at the top of this file.
00408   */
00409 #ifdef USE_TIMEOUT_USER_CALLBACK
00410  uint8_t IOE_TimeoutUserCallback(void);
00411 #else
00412  #define IOE_TimeoutUserCallback()  IOE_TIMEOUT
00413 #endif /* USE_TIMEOUT_USER_CALLBACK */
00414
00415 /**
00416   * @brief IO pins control functions
00417   */
00418 uint8_t IOE_WriteIOPin(uint8_t IO_Pin, IOE_BitValue_TypeDef BitVal);
00419 uint8_t IOE_ReadIOPin(uint32_t IO_Pin);
00420
00421 /**
00422   * @brief Touch Screen controller functions
00423   */
00424 TS_STATE* IOE_TS_GetState(void);
00425
00426 /**
00427   * @brief Interrupts Mangement functions
00428   */
00429 FlagStatus IOE_GetGITStatus(uint8_t DeviceAddr, uint8_t Global_IT);
00430 uint8_t IOE_ClearGITPending(uint8_t DeviceAddr, uint8_t IO_IT);
00431 FlagStatus IOE_GetIOITStatus(uint8_t DeviceAddr, uint8_t IO_IT);
00432 uint8_t IOE_ClearIOITPending(uint8_t DeviceAddr, uint8_t IO_IT);
00433
00434
00435 /**
00436   * @brief Temperature Sensor functions
00437   */
00438 uint32_t IOE_TempSens_GetData(void);
00439
00440
00441 /**
00442   * @brief IO-Expander Control functions
00443   */
00444 uint8_t IOE_IsOperational(uint8_t DeviceAddr);
00445 uint8_t IOE_Reset(uint8_t DeviceAddr);
00446 uint16_t IOE_ReadID(uint8_t DeviceAddr);
00447
00448 uint8_t IOE_FnctCmd(uint8_t DeviceAddr, uint8_t Fct, FunctionalState NewState);
00449 uint8_t IOE_IOPinConfig(uint8_t DeviceAddr, uint8_t IO_Pin, uint8_t Direction);
00450 uint8_t IOE_GITCmd(uint8_t DeviceAddr, FunctionalState NewState);
00451 uint8_t IOE_GITConfig(uint8_t DeviceAddr, uint8_t Global_IT, FunctionalState NewState);
00452 uint8_t IOE_IOITConfig(uint8_t DeviceAddr, uint8_t IO_IT, FunctionalState NewState);
00453
00454 /**
00455   * @brief Low Layer functions
00456   */
00457 uint8_t IOE_TS_Config(void);
00458 uint8_t IOE_TempSens_Config(void);
00459 uint8_t IOE_IOAFConfig(uint8_t DeviceAddr, uint8_t IO_Pin, FunctionalState NewState);
00460 uint8_t IOE_IOEdgeConfig(uint8_t DeviceAddr, uint8_t IO_Pin, uint8_t Edge);
00461 uint8_t IOE_ITOutConfig(uint8_t Polarity, uint8_t Type);
00462
00463 uint8_t I2C_WriteDeviceRegister(uint8_t DeviceAddr, uint8_t RegisterAddr, uint8_t RegisterValue);
00464 uint8_t I2C_ReadDeviceRegister(uint8_t DeviceAddr, uint8_t RegisterAddr);
00465 uint16_t I2C_ReadDataBuffer(uint8_t DeviceAddr, uint32_t RegisterAddr);
00466 #ifdef __cplusplus
00467 }
00468
00469 #endif
00470 #endif /* __STM32100E_EVAL_IOE_H */
00471
00472 /**
00473   * @}
00474   */
00475
00476 /**
00477   * @}
00478   */
00479
00480 /**
00481   * @}
00482   */
00483
00484 /**
00485   * @}
00486   */
00487
00488 /**
00489   * @}
00490   */
00491 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32100e_eval_lcd.c Source File

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  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Utilities
  • STM32_EVAL
  • STM32100E_EVAL

stm32100e_eval_lcd.c

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32100e_eval_lcd.c
00004   * @author  MCD Application Team
00005   * @version V4.5.0
00006   * @date    07-March-2011
00007   * @brief   This file includes the LCD driver for AM-240320L8TNQW00H
00008   *          (LCD_ILI9320), AM240320D5TOQW01H (LCD_ILI9325) and AM-240320LDTNQW00H
00009   *          (LCD_SPFD5408B) Liquid Crystal Display Module of STM32100E-EVAL board.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00014   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00015   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00016   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00017   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00018   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00019   *
00020   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32100e_eval_lcd.h"
00026 #include "../Common/fonts.c"
00027
00028 /** @addtogroup Utilities
00029   * @{
00030   */
00031
00032 /** @addtogroup STM32_EVAL
00033   * @{
00034   */
00035
00036 /** @addtogroup STM32100E_EVAL
00037   * @{
00038   */
00039
00040 /** @defgroup STM32100E_EVAL_LCD
00041   * @brief This file includes the LCD driver for AM-240320L8TNQW00H
00042   *        (LCD_ILI9320), AM240320D5TOQW01H (LCD_ILI9325) and AM-240320LDTNQW00H
00043   *        (LCD_SPFD5408B) Liquid Crystal Display Module of STM32100E-EVAL board.
00044   * @{
00045   */
00046
00047 /** @defgroup STM32100E_EVAL_LCD_Private_TypesDefinitions
00048   * @{
00049   */
00050 typedef struct
00051 {
00052   __IO uint16_t LCD_REG;
00053   __IO uint16_t LCD_RAM;
00054 } LCD_TypeDef;
00055 /**
00056   * @}
00057   */
00058
00059
00060 /** @defgroup STM32100E_EVAL_LCD_Private_Defines
00061   * @{
00062   */
00063 /* Note: LCD /CS is CE4 - Bank 4 of NOR/SRAM Bank 1~4 */
00064 #define LCD_BASE           ((uint32_t)(0x60000000 | 0x0C000000))
00065 #define LCD                ((LCD_TypeDef *) LCD_BASE)
00066 #define MAX_POLY_CORNERS   200
00067 #define POLY_Y(Z)          ((int32_t)((Points + Z)->X))
00068 #define POLY_X(Z)          ((int32_t)((Points + Z)->Y))
00069 /**
00070   * @}
00071   */
00072
00073 /** @defgroup STM32100E_EVAL_LCD_Private_Macros
00074   * @{
00075   */
00076 #define ABS(X)  ((X) > 0 ? (X) : -(X))
00077 /**
00078   * @}
00079   */
00080
00081 /** @defgroup STM32100E_EVAL_LCD_Private_Variables
00082   * @{
00083   */
00084 static sFONT *LCD_Currentfonts;
00085 /* Global variables to set the written text color */
00086 static  __IO uint16_t TextColor = 0x0000, BackColor = 0xFFFF;
00087
00088 /**
00089   * @}
00090   */
00091
00092
00093 /** @defgroup STM32100E_EVAL_LCD_Private_FunctionPrototypes
00094   * @{
00095   */
00096 #ifndef USE_Delay
00097 static void delay(vu32 nCount);
00098 #endif /* USE_Delay*/
00099 static void PutPixel(int16_t x, int16_t y);
00100 static void LCD_PolyLineRelativeClosed(pPoint Points, uint16_t PointCount, uint16_t Closed);
00101 /**
00102   * @}
00103   */
00104
00105
00106 /** @defgroup STM32100E_EVAL_LCD_Private_Functions
00107   * @{
00108   */
00109
00110 /**
00111   * @brief  DeInitializes the LCD.
00112   * @param  None
00113   * @retval None
00114   */
00115 void LCD_DeInit(void)
00116 {
00117   GPIO_InitTypeDef GPIO_InitStructure;
00118
00119   /*!< LCD Display Off */
00120   LCD_DisplayOff();
00121
00122   /* BANK 4 (of NOR/SRAM Bank 1~4) is disabled */
00123   FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM4, ENABLE);
00124
00125   /*!< LCD_SPI DeInit */
00126   FSMC_NORSRAMDeInit(FSMC_Bank1_NORSRAM4);
00127
00128   /* Set PD.00(D2), PD.01(D3), PD.04(NOE), PD.05(NWE), PD.08(D13), PD.09(D14),
00129      PD.10(D15), PD.14(D0), PD.15(D1) as input floating */
00130   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_4 | GPIO_Pin_5 |
00131                                 GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_14 |
00132                                 GPIO_Pin_15;
00133   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
00134   GPIO_Init(GPIOD, &GPIO_InitStructure);
00135   /* Set PE.07(D4), PE.08(D5), PE.09(D6), PE.10(D7), PE.11(D8), PE.12(D9), PE.13(D10),
00136      PE.14(D11), PE.15(D12) as alternate function push pull */
00137   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 |
00138                                 GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 |
00139                                 GPIO_Pin_15;
00140   GPIO_Init(GPIOE, &GPIO_InitStructure);
00141   /* Set PF.00(A0 (RS)) as alternate function push pull */
00142   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0;
00143   GPIO_Init(GPIOF, &GPIO_InitStructure);
00144   /* Set PG.12(NE4 (LCD/CS)) as alternate function push pull - CE3(LCD /CS) */
00145   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12;
00146   GPIO_Init(GPIOG, &GPIO_InitStructure);
00147 }
00148
00149 /**
00150   * @brief  Initializes the LCD.
00151   * @param  None
00152   * @retval None
00153   */
00154 void STM32100E_LCD_Init(void)
00155 {
00156   __IO uint32_t lcdid = 0;
00157
00158 /* Configure the LCD Control pins --------------------------------------------*/
00159   LCD_CtrlLinesConfig();
00160 /* Configure the FSMC Parallel interface -------------------------------------*/
00161   LCD_FSMCConfig();
00162
00163   _delay_(5); /* delay 50 ms */
00164
00165   /* Read the LCD ID */
00166   lcdid = LCD_ReadReg(0x00);
00167
00168   /* Check if the LCD is SPFD5408B Controller */
00169   if(lcdid == 0x5408)
00170   {
00171     /* Start Initial Sequence ------------------------------------------------*/
00172     LCD_WriteReg(LCD_REG_1, 0x0100);  /* Set SS bit */
00173     LCD_WriteReg(LCD_REG_2, 0x0700);  /* Set 1 line inversion */
00174     LCD_WriteReg(LCD_REG_3, 0x1030);  /* Set GRAM write direction and BGR=1. */
00175     LCD_WriteReg(LCD_REG_4, 0x0000);  /* Resize register */
00176     LCD_WriteReg(LCD_REG_8, 0x0202);  /* Set the back porch and front porch */
00177     LCD_WriteReg(LCD_REG_9, 0x0000);  /* Set non-display area refresh cycle ISC[3:0] */
00178     LCD_WriteReg(LCD_REG_10, 0x0000); /* FMARK function */
00179     LCD_WriteReg(LCD_REG_12, 0x0000); /* RGB 18-bit System interface setting */
00180     LCD_WriteReg(LCD_REG_13, 0x0000); /* Frame marker Position */
00181     LCD_WriteReg(LCD_REG_15, 0x0000); /* RGB interface polarity, no impact */
00182     /* Power On sequence -----------------------------------------------------*/
00183     LCD_WriteReg(LCD_REG_16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
00184     LCD_WriteReg(LCD_REG_17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */
00185     LCD_WriteReg(LCD_REG_18, 0x0000); /* VREG1OUT voltage */
00186     LCD_WriteReg(LCD_REG_19, 0x0000); /* VDV[4:0] for VCOM amplitude */
00187     _delay_(20);                 /* Dis-charge capacitor power voltage (200ms) */
00188     LCD_WriteReg(LCD_REG_17, 0x0007);  /* DC1[2:0], DC0[2:0], VC[2:0] */
00189     _delay_(5);                   /* Delay 50 ms */
00190     LCD_WriteReg(LCD_REG_16, 0x12B0);  /* SAP, BT[3:0], AP, DSTB, SLP, STB */
00191     _delay_(5);                  /* Delay 50 ms */
00192     LCD_WriteReg(LCD_REG_18, 0x01BD);  /* External reference voltage= Vci */
00193     _delay_(5);
00194     LCD_WriteReg(LCD_REG_19, 0x1400);  /* VDV[4:0] for VCOM amplitude */
00195     LCD_WriteReg(LCD_REG_41, 0x000E);  /* VCM[4:0] for VCOMH */
00196     _delay_(5);                   /* Delay 50 ms */
00197     LCD_WriteReg(LCD_REG_32, 0x0000); /* GRAM horizontal Address */
00198     LCD_WriteReg(LCD_REG_33, 0x013F); /* GRAM Vertical Address */
00199     /* Adjust the Gamma Curve (SPFD5408B)-------------------------------------*/
00200     LCD_WriteReg(LCD_REG_48, 0x0b0d);
00201     LCD_WriteReg(LCD_REG_49, 0x1923);
00202     LCD_WriteReg(LCD_REG_50, 0x1c26);
00203     LCD_WriteReg(LCD_REG_51, 0x261c);
00204     LCD_WriteReg(LCD_REG_52, 0x2419);
00205     LCD_WriteReg(LCD_REG_53, 0x0d0b);
00206     LCD_WriteReg(LCD_REG_54, 0x1006);
00207     LCD_WriteReg(LCD_REG_55, 0x0610);
00208     LCD_WriteReg(LCD_REG_56, 0x0706);
00209     LCD_WriteReg(LCD_REG_57, 0x0304);
00210     LCD_WriteReg(LCD_REG_58, 0x0e05);
00211     LCD_WriteReg(LCD_REG_59, 0x0e01);
00212     LCD_WriteReg(LCD_REG_60, 0x010e);
00213     LCD_WriteReg(LCD_REG_61, 0x050e);
00214     LCD_WriteReg(LCD_REG_62, 0x0403);
00215     LCD_WriteReg(LCD_REG_63, 0x0607);
00216     /* Set GRAM area ---------------------------------------------------------*/
00217     LCD_WriteReg(LCD_REG_80, 0x0000); /* Horizontal GRAM Start Address */
00218     LCD_WriteReg(LCD_REG_81, 0x00EF); /* Horizontal GRAM End Address */
00219     LCD_WriteReg(LCD_REG_82, 0x0000); /* Vertical GRAM Start Address */
00220     LCD_WriteReg(LCD_REG_83, 0x013F); /* Vertical GRAM End Address */
00221     LCD_WriteReg(LCD_REG_96,  0xA700); /* Gate Scan Line */
00222     LCD_WriteReg(LCD_REG_97,  0x0001); /* NDL, VLE, REV */
00223     LCD_WriteReg(LCD_REG_106, 0x0000); /* set scrolling line */
00224     /* Partial Display Control -----------------------------------------------*/
00225     LCD_WriteReg(LCD_REG_128, 0x0000);
00226     LCD_WriteReg(LCD_REG_129, 0x0000);
00227     LCD_WriteReg(LCD_REG_130, 0x0000);
00228     LCD_WriteReg(LCD_REG_131, 0x0000);
00229     LCD_WriteReg(LCD_REG_132, 0x0000);
00230     LCD_WriteReg(LCD_REG_133, 0x0000);
00231     /* Panel Control ---------------------------------------------------------*/
00232     LCD_WriteReg(LCD_REG_144, 0x0010);
00233     LCD_WriteReg(LCD_REG_146, 0x0000);
00234     LCD_WriteReg(LCD_REG_147, 0x0003);
00235     LCD_WriteReg(LCD_REG_149, 0x0110);
00236     LCD_WriteReg(LCD_REG_151, 0x0000);
00237     LCD_WriteReg(LCD_REG_152, 0x0000);
00238     /* Set GRAM write direction and BGR=1
00239        I/D=01 (Horizontal : increment, Vertical : decrement)
00240        AM=1 (address is updated in vertical writing direction) */
00241     LCD_WriteReg(LCD_REG_3, 0x1018);
00242     LCD_WriteReg(LCD_REG_7, 0x0112); /* 262K color and display ON */
00243     LCD_SetFont(&LCD_DEFAULT_FONT);
00244     return;
00245   }
00246   else if(lcdid == 0x9325) /* Check if the LCD is ILI9325 Controller */
00247   {
00248     /* Start Initial Sequence ------------------------------------------------*/
00249     LCD_WriteReg(LCD_REG_0, 0x0001); /* Start internal OSC. */
00250     LCD_WriteReg(LCD_REG_1, 0x0100); /* Set SS and SM bit */
00251     LCD_WriteReg(LCD_REG_2, 0x0700); /* Set 1 line inversion */
00252     LCD_WriteReg(LCD_REG_3, 0x1018); /* Set GRAM write direction and BGR=1. */
00253     LCD_WriteReg(LCD_REG_4, 0x0000); /* Resize register */
00254     LCD_WriteReg(LCD_REG_8, 0x0202); /* Set the back porch and front porch */
00255     LCD_WriteReg(LCD_REG_9, 0x0000); /* Set non-display area refresh cycle ISC[3:0] */
00256     LCD_WriteReg(LCD_REG_10, 0x0000); /* FMARK function */
00257     LCD_WriteReg(LCD_REG_12, 0x0000); /* RGB interface setting */
00258     LCD_WriteReg(LCD_REG_13, 0x0000); /* Frame marker Position */
00259     LCD_WriteReg(LCD_REG_15, 0x0000); /* RGB interface polarity */
00260
00261     /* Power On sequence -----------------------------------------------------*/
00262     LCD_WriteReg(LCD_REG_16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
00263     LCD_WriteReg(LCD_REG_17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */
00264     LCD_WriteReg(LCD_REG_18, 0x0000); /* VREG1OUT voltage */
00265     LCD_WriteReg(LCD_REG_19, 0x0000); /* VDV[4:0] for VCOM amplitude */
00266     _delay_(20);                      /* Dis-charge capacitor power voltage (200ms) */
00267     LCD_WriteReg(LCD_REG_16, 0x17B0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
00268     LCD_WriteReg(LCD_REG_17, 0x0137); /* DC1[2:0], DC0[2:0], VC[2:0] */
00269     _delay_(5);                       /* Delay 50 ms */
00270     LCD_WriteReg(LCD_REG_18, 0x0139); /* VREG1OUT voltage */
00271     _delay_(5);                       /* Delay 50 ms */
00272     LCD_WriteReg(LCD_REG_19, 0x1d00); /* VDV[4:0] for VCOM amplitude */
00273     LCD_WriteReg(LCD_REG_41, 0x0013); /* VCM[4:0] for VCOMH */
00274     _delay_(5);                       /* Delay 50 ms */
00275     LCD_WriteReg(LCD_REG_32, 0x0000); /* GRAM horizontal Address */
00276     LCD_WriteReg(LCD_REG_33, 0x0000); /* GRAM Vertical Address */
00277
00278     /* Adjust the Gamma Curve (ILI9325)---------------------------------------*/
00279     LCD_WriteReg(LCD_REG_48, 0x0007);
00280     LCD_WriteReg(LCD_REG_49, 0x0302);
00281     LCD_WriteReg(LCD_REG_50, 0x0105);
00282     LCD_WriteReg(LCD_REG_53, 0x0206);
00283     LCD_WriteReg(LCD_REG_54, 0x0808);
00284     LCD_WriteReg(LCD_REG_55, 0x0206);
00285     LCD_WriteReg(LCD_REG_56, 0x0504);
00286     LCD_WriteReg(LCD_REG_57, 0x0007);
00287     LCD_WriteReg(LCD_REG_60, 0x0105);
00288     LCD_WriteReg(LCD_REG_61, 0x0808);
00289
00290     /* Set GRAM area ---------------------------------------------------------*/
00291     LCD_WriteReg(LCD_REG_80, 0x0000); /* Horizontal GRAM Start Address */
00292     LCD_WriteReg(LCD_REG_81, 0x00EF); /* Horizontal GRAM End Address */
00293     LCD_WriteReg(LCD_REG_82, 0x0000); /* Vertical GRAM Start Address */
00294     LCD_WriteReg(LCD_REG_83, 0x013F); /* Vertical GRAM End Address */
00295
00296     LCD_WriteReg(LCD_REG_96,  0xA700); /* Gate Scan Line(GS=1, scan direction is G320~G1) */
00297     LCD_WriteReg(LCD_REG_97,  0x0001); /* NDL,VLE, REV */
00298     LCD_WriteReg(LCD_REG_106, 0x0000); /* set scrolling line */
00299
00300     /* Partial Display Control -----------------------------------------------*/
00301     LCD_WriteReg(LCD_REG_128, 0x0000);
00302     LCD_WriteReg(LCD_REG_129, 0x0000);
00303     LCD_WriteReg(LCD_REG_130, 0x0000);
00304     LCD_WriteReg(LCD_REG_131, 0x0000);
00305     LCD_WriteReg(LCD_REG_132, 0x0000);
00306     LCD_WriteReg(LCD_REG_133, 0x0000);
00307
00308     /* Panel Control ---------------------------------------------------------*/
00309     LCD_WriteReg(LCD_REG_144, 0x0010);
00310     LCD_WriteReg(LCD_REG_146, 0x0000);
00311     LCD_WriteReg(LCD_REG_147, 0x0003);
00312     LCD_WriteReg(LCD_REG_149, 0x0110);
00313     LCD_WriteReg(LCD_REG_151, 0x0000);
00314     LCD_WriteReg(LCD_REG_152, 0x0000);
00315
00316     /* set GRAM write direction and BGR = 1 */
00317     /* I/D=00 (Horizontal : increment, Vertical : decrement) */
00318     /* AM=1 (address is updated in vertical writing direction) */
00319     LCD_WriteReg(LCD_REG_3, 0x1018);
00320
00321     LCD_WriteReg(LCD_REG_7, 0x0133); /* 262K color and display ON */
00322     LCD_SetFont(&LCD_DEFAULT_FONT);
00323     return;
00324   }
00325   /* Check if the LCD is ILI9320 Controller */
00326 /* Start Initial Sequence ----------------------------------------------------*/
00327   LCD_WriteReg(LCD_REG_229,0x8000); /* Set the internal vcore voltage */
00328   LCD_WriteReg(LCD_REG_0,  0x0001); /* Start internal OSC. */
00329   LCD_WriteReg(LCD_REG_1,  0x0100); /* set SS and SM bit */
00330   LCD_WriteReg(LCD_REG_2,  0x0700); /* set 1 line inversion */
00331   LCD_WriteReg(LCD_REG_3,  0x1030); /* set GRAM write direction and BGR=1. */
00332   LCD_WriteReg(LCD_REG_4,  0x0000); /* Resize register */
00333   LCD_WriteReg(LCD_REG_8,  0x0202); /* set the back porch and front porch */
00334   LCD_WriteReg(LCD_REG_9,  0x0000); /* set non-display area refresh cycle ISC[3:0] */
00335   LCD_WriteReg(LCD_REG_10, 0x0000); /* FMARK function */
00336   LCD_WriteReg(LCD_REG_12, 0x0000); /* RGB interface setting */
00337   LCD_WriteReg(LCD_REG_13, 0x0000); /* Frame marker Position */
00338   LCD_WriteReg(LCD_REG_15, 0x0000); /* RGB interface polarity */
00339 /* Power On sequence ---------------------------------------------------------*/
00340   LCD_WriteReg(LCD_REG_16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
00341   LCD_WriteReg(LCD_REG_17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */
00342   LCD_WriteReg(LCD_REG_18, 0x0000); /* VREG1OUT voltage */
00343   LCD_WriteReg(LCD_REG_19, 0x0000); /* VDV[4:0] for VCOM amplitude */
00344   _delay_(20);                 /* Dis-charge capacitor power voltage (200ms) */
00345   LCD_WriteReg(LCD_REG_16, 0x17B0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
00346   LCD_WriteReg(LCD_REG_17, 0x0137); /* DC1[2:0], DC0[2:0], VC[2:0] */
00347   _delay_(5);                  /* Delay 50 ms */
00348   LCD_WriteReg(LCD_REG_18, 0x0139); /* VREG1OUT voltage */
00349   _delay_(5);                  /* Delay 50 ms */
00350   LCD_WriteReg(LCD_REG_19, 0x1d00); /* VDV[4:0] for VCOM amplitude */
00351   LCD_WriteReg(LCD_REG_41, 0x0013); /* VCM[4:0] for VCOMH */
00352   _delay_(5);                  /* Delay 50 ms */
00353   LCD_WriteReg(LCD_REG_32, 0x0000); /* GRAM horizontal Address */
00354   LCD_WriteReg(LCD_REG_33, 0x0000); /* GRAM Vertical Address */
00355 /* Adjust the Gamma Curve ----------------------------------------------------*/
00356   LCD_WriteReg(LCD_REG_48, 0x0006);
00357   LCD_WriteReg(LCD_REG_49, 0x0101);
00358   LCD_WriteReg(LCD_REG_50, 0x0003);
00359   LCD_WriteReg(LCD_REG_53, 0x0106);
00360   LCD_WriteReg(LCD_REG_54, 0x0b02);
00361   LCD_WriteReg(LCD_REG_55, 0x0302);
00362   LCD_WriteReg(LCD_REG_56, 0x0707);
00363   LCD_WriteReg(LCD_REG_57, 0x0007);
00364   LCD_WriteReg(LCD_REG_60, 0x0600);
00365   LCD_WriteReg(LCD_REG_61, 0x020b);
00366
00367 /* Set GRAM area -------------------------------------------------------------*/
00368   LCD_WriteReg(LCD_REG_80, 0x0000); /* Horizontal GRAM Start Address */
00369   LCD_WriteReg(LCD_REG_81, 0x00EF); /* Horizontal GRAM End Address */
00370   LCD_WriteReg(LCD_REG_82, 0x0000); /* Vertical GRAM Start Address */
00371   LCD_WriteReg(LCD_REG_83, 0x013F); /* Vertical GRAM End Address */
00372   LCD_WriteReg(LCD_REG_96,  0x2700); /* Gate Scan Line */
00373   LCD_WriteReg(LCD_REG_97,  0x0001); /* NDL,VLE, REV */
00374   LCD_WriteReg(LCD_REG_106, 0x0000); /* set scrolling line */
00375 /* Partial Display Control ---------------------------------------------------*/
00376   LCD_WriteReg(LCD_REG_128, 0x0000);
00377   LCD_WriteReg(LCD_REG_129, 0x0000);
00378   LCD_WriteReg(LCD_REG_130, 0x0000);
00379   LCD_WriteReg(LCD_REG_131, 0x0000);
00380   LCD_WriteReg(LCD_REG_132, 0x0000);
00381   LCD_WriteReg(LCD_REG_133, 0x0000);
00382 /* Panel Control -------------------------------------------------------------*/
00383   LCD_WriteReg(LCD_REG_144, 0x0010);
00384   LCD_WriteReg(LCD_REG_146, 0x0000);
00385   LCD_WriteReg(LCD_REG_147, 0x0003);
00386   LCD_WriteReg(LCD_REG_149, 0x0110);
00387   LCD_WriteReg(LCD_REG_151, 0x0000);
00388   LCD_WriteReg(LCD_REG_152, 0x0000);
00389   /* Set GRAM write direction and BGR = 1 */
00390   /* I/D=01 (Horizontal : increment, Vertical : decrement) */
00391   /* AM=1 (address is updated in vertical writing direction) */
00392   LCD_WriteReg(LCD_REG_3, 0x1018);
00393   LCD_WriteReg(LCD_REG_7, 0x0173); /* 262K color and display ON */
00394   LCD_SetFont(&LCD_DEFAULT_FONT);
00395 }
00396
00397 /**
00398   * @brief  Sets the LCD Text and Background colors.
00399   * @param  _TextColor: specifies the Text Color.
00400   * @param  _BackColor: specifies the Background Color.
00401   * @retval None
00402   */
00403 void LCD_SetColors(__IO uint16_t _TextColor, __IO uint16_t _BackColor)
00404 {
00405   TextColor = _TextColor;
00406   BackColor = _BackColor;
00407 }
00408
00409 /**
00410   * @brief  Gets the LCD Text and Background colors.
00411   * @param  _TextColor: pointer to the variable that will contain the Text
00412             Color.
00413   * @param  _BackColor: pointer to the variable that will contain the Background
00414             Color.
00415   * @retval None
00416   */
00417 void LCD_GetColors(__IO uint16_t *_TextColor, __IO uint16_t *_BackColor)
00418 {
00419   *_TextColor = TextColor; *_BackColor = BackColor;
00420 }
00421
00422 /**
00423   * @brief  Sets the Text color.
00424   * @param  Color: specifies the Text color code RGB(5-6-5).
00425   * @retval None
00426   */
00427 void LCD_SetTextColor(__IO uint16_t Color)
00428 {
00429   TextColor = Color;
00430 }
00431
00432
00433 /**
00434   * @brief  Sets the Background color.
00435   * @param  Color: specifies the Background color code RGB(5-6-5).
00436   * @retval None
00437   */
00438 void LCD_SetBackColor(__IO uint16_t Color)
00439 {
00440   BackColor = Color;
00441 }
00442
00443 /**
00444   * @brief  Sets the Text Font.
00445   * @param  fonts: specifies the font to be used.
00446   * @retval None
00447   */
00448 void LCD_SetFont(sFONT *fonts)
00449 {
00450   LCD_Currentfonts = fonts;
00451 }
00452
00453 /**
00454   * @brief  Gets the Text Font.
00455   * @param  None.
00456   * @retval the used font.
00457   */
00458 sFONT *LCD_GetFont(void)
00459 {
00460   return LCD_Currentfonts;
00461 }
00462
00463 /**
00464   * @brief  Clears the selected line.
00465   * @param  Line: the Line to be cleared.
00466   *   This parameter can be one of the following values:
00467   *     @arg Linex: where x can be 0..n
00468   * @retval None
00469   */
00470 void LCD_ClearLine(uint8_t Line)
00471 {
00472   uint16_t refcolumn = LCD_PIXEL_WIDTH - 1;
00473   /* Send the string character by character on lCD */
00474   while (((refcolumn + 1)&0xFFFF) >= LCD_Currentfonts->Width)
00475   {
00476     /* Display one character on LCD */
00477     LCD_DisplayChar(Line, refcolumn, ' ');
00478     /* Decrement the column position by 16 */
00479     refcolumn -= LCD_Currentfonts->Width;
00480   }
00481 }
00482
00483
00484 /**
00485   * @brief  Clears the hole LCD.
00486   * @param  Color: the color of the background.
00487   * @retval None
00488   */
00489 void LCD_Clear(uint16_t Color)
00490 {
00491   uint32_t index = 0;
00492
00493   LCD_SetCursor(0x00, 0x013F);
00494   LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
00495   for(index = 0; index < 76800; index++)
00496   {
00497     LCD->LCD_RAM = Color;
00498   }
00499 }
00500
00501
00502 /**
00503   * @brief  Sets the cursor position.
00504   * @param  Xpos: specifies the X position.
00505   * @param  Ypos: specifies the Y position.
00506   * @retval None
00507   */
00508 void LCD_SetCursor(uint8_t Xpos, uint16_t Ypos)
00509 {
00510   LCD_WriteReg(LCD_REG_32, Xpos);
00511   LCD_WriteReg(LCD_REG_33, Ypos);
00512 }
00513
00514
00515 /**
00516   * @brief  Draws a character on LCD.
00517   * @param  Xpos: the Line where to display the character shape.
00518   * @param  Ypos: start column address.
00519   * @param  c: pointer to the character data.
00520   * @retval None
00521   */
00522 void LCD_DrawChar(uint8_t Xpos, uint16_t Ypos, const uint16_t *c)
00523 {
00524   uint32_t index = 0, i = 0;
00525   uint8_t Xaddress = 0;
00526
00527   Xaddress = Xpos;
00528
00529   LCD_SetCursor(Xaddress, Ypos);
00530
00531   for(index = 0; index < LCD_Currentfonts->Height; index++)
00532   {
00533     LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
00534     for(i = 0; i < LCD_Currentfonts->Width; i++)
00535     {
00536       if((((c[index] & ((0x80 << ((LCD_Currentfonts->Width / 12 ) * 8 ) ) >> i)) == 0x00) &&(LCD_Currentfonts->Width <= 12))||
00537         (((c[index] & (0x1 << i)) == 0x00)&&(LCD_Currentfonts->Width > 12 )))
00538
00539       {
00540         LCD_WriteRAM(BackColor);
00541       }
00542       else
00543       {
00544         LCD_WriteRAM(TextColor);
00545       }
00546     }
00547     Xaddress++;
00548     LCD_SetCursor(Xaddress, Ypos);
00549   }
00550 }
00551
00552
00553 /**
00554   * @brief  Displays one character (16dots width, 24dots height).
00555   * @param  Line: the Line where to display the character shape .
00556   *   This parameter can be one of the following values:
00557   *     @arg Linex: where x can be 0..9
00558   * @param  Column: start column address.
00559   * @param  Ascii: character ascii code, must be between 0x20 and 0x7E.
00560   * @retval None
00561   */
00562 void LCD_DisplayChar(uint8_t Line, uint16_t Column, uint8_t Ascii)
00563 {
00564   Ascii -= 32;
00565   LCD_DrawChar(Line, Column, &LCD_Currentfonts->table[Ascii * LCD_Currentfonts->Height]);
00566 }
00567
00568
00569 /**
00570   * @brief  Displays a maximum of 20 char on the LCD.
00571   * @param  Line: the Line where to display the character shape .
00572   *   This parameter can be one of the following values:
00573   *     @arg Linex: where x can be 0..9
00574   * @param  *ptr: pointer to string to display on LCD.
00575   * @retval None
00576   */
00577 void LCD_DisplayStringLine(uint8_t Line, uint8_t *ptr)
00578 {
00579   uint16_t refcolumn = LCD_PIXEL_WIDTH - 1;
00580
00581   /* Send the string character by character on lCD */
00582   while ((*ptr != 0) & (((refcolumn + 1) & 0xFFFF) >= LCD_Currentfonts->Width))
00583   {
00584     /* Display one character on LCD */
00585     LCD_DisplayChar(Line, refcolumn, *ptr);
00586     /* Decrement the column position by 16 */
00587     refcolumn -= LCD_Currentfonts->Width;
00588     /* Point on the next character */
00589     ptr++;
00590   }
00591 }
00592
00593
00594 /**
00595   * @brief  Sets a display window
00596   * @param  Xpos: specifies the X buttom left position.
00597   * @param  Ypos: specifies the Y buttom left position.
00598   * @param  Height: display window height.
00599   * @param  Width: display window width.
00600   * @retval None
00601   */
00602 void LCD_SetDisplayWindow(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width)
00603 {
00604   /* Horizontal GRAM Start Address */
00605   if(Xpos >= Height)
00606   {
00607     LCD_WriteReg(LCD_REG_80, (Xpos - Height + 1));
00608   }
00609   else
00610   {
00611     LCD_WriteReg(LCD_REG_80, 0);
00612   }
00613   /* Horizontal GRAM End Address */
00614   LCD_WriteReg(LCD_REG_81, Xpos);
00615   /* Vertical GRAM Start Address */
00616   if(Ypos >= Width)
00617   {
00618     LCD_WriteReg(LCD_REG_82, (Ypos - Width + 1));
00619   }
00620   else
00621   {
00622     LCD_WriteReg(LCD_REG_82, 0);
00623   }
00624   /* Vertical GRAM End Address */
00625   LCD_WriteReg(LCD_REG_83, Ypos);
00626   LCD_SetCursor(Xpos, Ypos);
00627 }
00628
00629
00630 /**
00631   * @brief  Disables LCD Window mode.
00632   * @param  None
00633   * @retval None
00634   */
00635 void LCD_WindowModeDisable(void)
00636 {
00637   LCD_SetDisplayWindow(239, 0x13F, 240, 320);
00638   LCD_WriteReg(LCD_REG_3, 0x1018);
00639 }
00640
00641
00642 /**
00643   * @brief  Displays a line.
00644   * @param Xpos: specifies the X position.
00645   * @param Ypos: specifies the Y position.
00646   * @param Length: line length.
00647   * @param Direction: line direction.
00648   *   This parameter can be one of the following values: Vertical or Horizontal.
00649   * @retval None
00650   */
00651 void LCD_DrawLine(uint8_t Xpos, uint16_t Ypos, uint16_t Length, uint8_t Direction)
00652 {
00653   uint32_t i = 0;
00654
00655   LCD_SetCursor(Xpos, Ypos);
00656   if(Direction == LCD_DIR_HORIZONTAL)
00657   {
00658     LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
00659     for(i = 0; i < Length; i++)
00660     {
00661       LCD_WriteRAM(TextColor);
00662     }
00663   }
00664   else
00665   {
00666     for(i = 0; i < Length; i++)
00667     {
00668       LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
00669       LCD_WriteRAM(TextColor);
00670       Xpos++;
00671       LCD_SetCursor(Xpos, Ypos);
00672     }
00673   }
00674 }
00675
00676
00677 /**
00678   * @brief  Displays a rectangle.
00679   * @param  Xpos: specifies the X position.
00680   * @param  Ypos: specifies the Y position.
00681   * @param  Height: display rectangle height.
00682   * @param  Width: display rectangle width.
00683   * @retval None
00684   */
00685 void LCD_DrawRect(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width)
00686 {
00687   LCD_DrawLine(Xpos, Ypos, Width, LCD_DIR_HORIZONTAL);
00688   LCD_DrawLine((Xpos + Height), Ypos, Width, LCD_DIR_HORIZONTAL);
00689
00690   LCD_DrawLine(Xpos, Ypos, Height, LCD_DIR_VERTICAL);
00691   LCD_DrawLine(Xpos, (Ypos - Width + 1), Height, LCD_DIR_VERTICAL);
00692 }
00693
00694
00695 /**
00696   * @brief  Displays a circle.
00697   * @param  Xpos: specifies the X position.
00698   * @param  Ypos: specifies the Y position.
00699   * @param  Radius
00700   * @retval None
00701   */
00702 void LCD_DrawCircle(uint8_t Xpos, uint16_t Ypos, uint16_t Radius)
00703 {
00704   int32_t  D;/* Decision Variable */
00705   uint32_t  CurX;/* Current X Value */
00706   uint32_t  CurY;/* Current Y Value */
00707
00708   D = 3 - (Radius << 1);
00709   CurX = 0;
00710   CurY = Radius;
00711
00712   while (CurX <= CurY)
00713   {
00714     LCD_SetCursor(Xpos + CurX, Ypos + CurY);
00715     LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
00716     LCD_WriteRAM(TextColor);
00717     LCD_SetCursor(Xpos + CurX, Ypos - CurY);
00718     LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
00719     LCD_WriteRAM(TextColor);
00720     LCD_SetCursor(Xpos - CurX, Ypos + CurY);
00721     LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
00722     LCD_WriteRAM(TextColor);
00723     LCD_SetCursor(Xpos - CurX, Ypos - CurY);
00724     LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
00725     LCD_WriteRAM(TextColor);
00726     LCD_SetCursor(Xpos + CurY, Ypos + CurX);
00727     LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
00728     LCD_WriteRAM(TextColor);
00729     LCD_SetCursor(Xpos + CurY, Ypos - CurX);
00730     LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
00731     LCD_WriteRAM(TextColor);
00732     LCD_SetCursor(Xpos - CurY, Ypos + CurX);
00733     LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
00734     LCD_WriteRAM(TextColor);
00735     LCD_SetCursor(Xpos - CurY, Ypos - CurX);
00736     LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
00737     LCD_WriteRAM(TextColor);
00738     if (D < 0)
00739     {
00740       D += (CurX << 2) + 6;
00741     }
00742     else
00743     {
00744       D += ((CurX - CurY) << 2) + 10;
00745       CurY--;
00746     }
00747     CurX++;
00748   }
00749 }
00750
00751
00752 /**
00753   * @brief  Displays a monocolor picture.
00754   * @param  Pict: pointer to the picture array.
00755   * @retval None
00756   */
00757 void LCD_DrawMonoPict(const uint32_t *Pict)
00758 {
00759   uint32_t index = 0, i = 0;
00760   LCD_SetCursor(0, (LCD_PIXEL_WIDTH - 1));
00761   LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
00762   for(index = 0; index < 2400; index++)
00763   {
00764     for(i = 0; i < 32; i++)
00765     {
00766       if((Pict[index] & (1 << i)) == 0x00)
00767       {
00768         LCD_WriteRAM(BackColor);
00769       }
00770       else
00771       {
00772         LCD_WriteRAM(TextColor);
00773       }
00774     }
00775   }
00776 }
00777
00778
00779 /**
00780   * @brief  Displays a bitmap picture loaded in the internal Flash.
00781   * @param  BmpAddress: Bmp picture address in the internal Flash.
00782   * @retval None
00783   */
00784 void LCD_WriteBMP(uint32_t BmpAddress)
00785 {
00786   uint32_t index = 0, size = 0;
00787   /* Read bitmap size */
00788   size = *(__IO uint16_t *) (BmpAddress + 2);
00789   size |= (*(__IO uint16_t *) (BmpAddress + 4)) << 16;
00790   /* Get bitmap data address offset */
00791   index = *(__IO uint16_t *) (BmpAddress + 10);
00792   index |= (*(__IO uint16_t *) (BmpAddress + 12)) << 16;
00793   size = (size - index)/2;
00794   BmpAddress += index;
00795   /* Set GRAM write direction and BGR = 1 */
00796   /* I/D=00 (Horizontal : decrement, Vertical : decrement) */
00797   /* AM=1 (address is updated in vertical writing direction) */
00798   LCD_WriteReg(LCD_REG_3, 0x1008);
00799
00800   LCD_WriteRAM_Prepare();
00801
00802   for(index = 0; index < size; index++)
00803   {
00804     LCD_WriteRAM(*(__IO uint16_t *)BmpAddress);
00805     BmpAddress += 2;
00806   }
00807
00808   /* Set GRAM write direction and BGR = 1 */
00809   /* I/D = 01 (Horizontal : increment, Vertical : decrement) */
00810   /* AM = 1 (address is updated in vertical writing direction) */
00811   LCD_WriteReg(LCD_REG_3, 0x1018);
00812 }
00813
00814 /**
00815   * @brief  Displays a full rectangle.
00816   * @param  Xpos: specifies the X position.
00817   * @param  Ypos: specifies the Y position.
00818   * @param  Height: rectangle height.
00819   * @param  Width: rectangle width.
00820   * @retval None
00821   */
00822 void LCD_DrawFullRect(uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height)
00823 {
00824   LCD_SetTextColor(TextColor);
00825
00826   LCD_DrawLine(Xpos, Ypos, Width, LCD_DIR_HORIZONTAL);
00827   LCD_DrawLine((Xpos + Height), Ypos, Width, LCD_DIR_HORIZONTAL);
00828
00829   LCD_DrawLine(Xpos, Ypos, Height, LCD_DIR_VERTICAL);
00830   LCD_DrawLine(Xpos, (Ypos - Width + 1), Height, LCD_DIR_VERTICAL);
00831
00832   Width -= 2;
00833   Height--;
00834   Ypos--;
00835
00836   LCD_SetTextColor(BackColor);
00837
00838   while(Height--)
00839   {
00840     LCD_DrawLine(++Xpos, Ypos, Width, LCD_DIR_HORIZONTAL);
00841   }
00842
00843   LCD_SetTextColor(TextColor);
00844 }
00845
00846 /**
00847   * @brief  Displays a full circle.
00848   * @param  Xpos: specifies the X position.
00849   * @param  Ypos: specifies the Y position.
00850   * @param  Radius
00851   * @retval None
00852   */
00853 void LCD_DrawFullCircle(uint16_t Xpos, uint16_t Ypos, uint16_t Radius)
00854 {
00855   int32_t  D;    /* Decision Variable */
00856   uint32_t  CurX;/* Current X Value */
00857   uint32_t  CurY;/* Current Y Value */
00858
00859   D = 3 - (Radius << 1);
00860
00861   CurX = 0;
00862   CurY = Radius;
00863
00864   LCD_SetTextColor(BackColor);
00865
00866   while (CurX <= CurY)
00867   {
00868     if(CurY > 0)
00869     {
00870       LCD_DrawLine(Xpos - CurX, Ypos + CurY, 2*CurY, LCD_DIR_HORIZONTAL);
00871       LCD_DrawLine(Xpos + CurX, Ypos + CurY, 2*CurY, LCD_DIR_HORIZONTAL);
00872     }
00873
00874     if(CurX > 0)
00875     {
00876       LCD_DrawLine(Xpos - CurY, Ypos + CurX, 2*CurX, LCD_DIR_HORIZONTAL);
00877       LCD_DrawLine(Xpos + CurY, Ypos + CurX, 2*CurX, LCD_DIR_HORIZONTAL);
00878     }
00879     if (D < 0)
00880     {
00881       D += (CurX << 2) + 6;
00882     }
00883     else
00884     {
00885       D += ((CurX - CurY) << 2) + 10;
00886       CurY--;
00887     }
00888     CurX++;
00889   }
00890
00891   LCD_SetTextColor(TextColor);
00892   LCD_DrawCircle(Xpos, Ypos, Radius);
00893 }
00894
00895 /**
00896   * @brief  Displays an uni line (between two points).
00897   * @param  x1: specifies the point 1 x position.
00898   * @param  y1: specifies the point 1 y position.
00899   * @param  x2: specifies the point 2 x position.
00900   * @param  y2: specifies the point 2 y position.
00901   * @retval None
00902   */
00903 void LCD_DrawUniLine(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2)
00904 {
00905   int16_t deltax = 0, deltay = 0, x = 0, y = 0, xinc1 = 0, xinc2 = 0,
00906   yinc1 = 0, yinc2 = 0, den = 0, num = 0, numadd = 0, numpixels = 0,
00907   curpixel = 0;
00908
00909   deltax = ABS(x2 - x1);        /* The difference between the x's */
00910   deltay = ABS(y2 - y1);        /* The difference between the y's */
00911   x = x1;                       /* Start x off at the first pixel */
00912   y = y1;                       /* Start y off at the first pixel */
00913
00914   if (x2 >= x1)                 /* The x-values are increasing */
00915   {
00916     xinc1 = 1;
00917     xinc2 = 1;
00918   }
00919   else                          /* The x-values are decreasing */
00920   {
00921     xinc1 = -1;
00922     xinc2 = -1;
00923   }
00924
00925   if (y2 >= y1)                 /* The y-values are increasing */
00926   {
00927     yinc1 = 1;
00928     yinc2 = 1;
00929   }
00930   else                          /* The y-values are decreasing */
00931   {
00932     yinc1 = -1;
00933     yinc2 = -1;
00934   }
00935
00936   if (deltax >= deltay)         /* There is at least one x-value for every y-value */
00937   {
00938     xinc1 = 0;                  /* Don't change the x when numerator >= denominator */
00939     yinc2 = 0;                  /* Don't change the y for every iteration */
00940     den = deltax;
00941     num = deltax / 2;
00942     numadd = deltay;
00943     numpixels = deltax;         /* There are more x-values than y-values */
00944   }
00945   else                          /* There is at least one y-value for every x-value */
00946   {
00947     xinc2 = 0;                  /* Don't change the x for every iteration */
00948     yinc1 = 0;                  /* Don't change the y when numerator >= denominator */
00949     den = deltay;
00950     num = deltay / 2;
00951     numadd = deltax;
00952     numpixels = deltay;         /* There are more y-values than x-values */
00953   }
00954
00955   for (curpixel = 0; curpixel <= numpixels; curpixel++)
00956   {
00957     PutPixel(x, y);             /* Draw the current pixel */
00958     num += numadd;              /* Increase the numerator by the top of the fraction */
00959     if (num >= den)             /* Check if numerator >= denominator */
00960     {
00961       num -= den;               /* Calculate the new numerator value */
00962       x += xinc1;               /* Change the x as appropriate */
00963       y += yinc1;               /* Change the y as appropriate */
00964     }
00965     x += xinc2;                 /* Change the x as appropriate */
00966     y += yinc2;                 /* Change the y as appropriate */
00967   }
00968 }
00969
00970 /**
00971   * @brief  Displays an polyline (between many points).
00972   * @param  Points: pointer to the points array.
00973   * @param  PointCount: Number of points.
00974   * @retval None
00975   */
00976 void LCD_PolyLine(pPoint Points, uint16_t PointCount)
00977 {
00978   int16_t X = 0, Y = 0;
00979
00980   if(PointCount < 2)
00981   {
00982     return;
00983   }
00984
00985   while(--PointCount)
00986   {
00987     X = Points->X;
00988     Y = Points->Y;
00989     Points++;
00990     LCD_DrawUniLine(X, Y, Points->X, Points->Y);
00991   }
00992 }
00993
00994 /**
00995   * @brief  Displays an relative polyline (between many points).
00996   * @param  Points: pointer to the points array.
00997   * @param  PointCount: Number of points.
00998   * @param  Closed: specifies if the draw is closed or not.
00999   *           1: closed, 0 : not closed.
01000   * @retval None
01001   */
01002 static void LCD_PolyLineRelativeClosed(pPoint Points, uint16_t PointCount, uint16_t Closed)
01003 {
01004   int16_t X = 0, Y = 0;
01005   pPoint First = Points;
01006
01007   if(PointCount < 2)
01008   {
01009     return;
01010   }
01011   X = Points->X;
01012   Y = Points->Y;
01013   while(--PointCount)
01014   {
01015     Points++;
01016     LCD_DrawUniLine(X, Y, X + Points->X, Y + Points->Y);
01017     X = X + Points->X;
01018     Y = Y + Points->Y;
01019   }
01020   if(Closed)
01021   {
01022     LCD_DrawUniLine(First->X, First->Y, X, Y);
01023   }
01024 }
01025
01026 /**
01027   * @brief  Displays a closed polyline (between many points).
01028   * @param  Points: pointer to the points array.
01029   * @param  PointCount: Number of points.
01030   * @retval None
01031   */
01032 void LCD_ClosedPolyLine(pPoint Points, uint16_t PointCount)
01033 {
01034   LCD_PolyLine(Points, PointCount);
01035   LCD_DrawUniLine(Points->X, Points->Y, (Points+PointCount-1)->X, (Points+PointCount-1)->Y);
01036 }
01037
01038 /**
01039   * @brief  Displays a relative polyline (between many points).
01040   * @param  Points: pointer to the points array.
01041   * @param  PointCount: Number of points.
01042   * @retval None
01043   */
01044 void LCD_PolyLineRelative(pPoint Points, uint16_t PointCount)
01045 {
01046   LCD_PolyLineRelativeClosed(Points, PointCount, 0);
01047 }
01048
01049 /**
01050   * @brief  Displays a closed relative polyline (between many points).
01051   * @param  Points: pointer to the points array.
01052   * @param  PointCount: Number of points.
01053   * @retval None
01054   */
01055 void LCD_ClosedPolyLineRelative(pPoint Points, uint16_t PointCount)
01056 {
01057   LCD_PolyLineRelativeClosed(Points, PointCount, 1);
01058 }
01059
01060
01061 /**
01062   * @brief  Displays a  full polyline (between many points).
01063   * @param  Points: pointer to the points array.
01064   * @param  PointCount: Number of points.
01065   * @retval None
01066   */
01067 void LCD_FillPolyLine(pPoint Points, uint16_t PointCount)
01068 {
01069   /*  public-domain code by Darel Rex Finley, 2007 */
01070   uint16_t  nodes = 0, nodeX[MAX_POLY_CORNERS], pixelX = 0, pixelY = 0, i = 0,
01071   j = 0, swap = 0;
01072   uint16_t  IMAGE_LEFT = 0, IMAGE_RIGHT = 0, IMAGE_TOP = 0, IMAGE_BOTTOM = 0;
01073
01074   IMAGE_LEFT = IMAGE_RIGHT = Points->X;
01075   IMAGE_TOP= IMAGE_BOTTOM = Points->Y;
01076
01077   for(i = 1; i < PointCount; i++)
01078   {
01079     pixelX = POLY_X(i);
01080     if(pixelX < IMAGE_LEFT)
01081     {
01082       IMAGE_LEFT = pixelX;
01083     }
01084     if(pixelX > IMAGE_RIGHT)
01085     {
01086       IMAGE_RIGHT = pixelX;
01087     }
01088
01089     pixelY = POLY_Y(i);
01090     if(pixelY < IMAGE_TOP)
01091     {
01092       IMAGE_TOP = pixelY;
01093     }
01094     if(pixelY > IMAGE_BOTTOM)
01095     {
01096       IMAGE_BOTTOM = pixelY;
01097     }
01098   }
01099
01100   LCD_SetTextColor(BackColor);
01101
01102   /*  Loop through the rows of the image. */
01103   for (pixelY = IMAGE_TOP; pixelY < IMAGE_BOTTOM; pixelY++)
01104   {
01105     /* Build a list of nodes. */
01106     nodes = 0; j = PointCount-1;
01107
01108     for (i = 0; i < PointCount; i++)
01109     {
01110       if (POLY_Y(i)<(double) pixelY && POLY_Y(j)>=(double) pixelY || POLY_Y(j)<(double) pixelY && POLY_Y(i)>=(double) pixelY)
01111       {
01112         nodeX[nodes++]=(int) (POLY_X(i)+((pixelY-POLY_Y(i))*(POLY_X(j)-POLY_X(i)))/(POLY_Y(j)-POLY_Y(i)));
01113       }
01114       j = i;
01115     }
01116
01117     /* Sort the nodes, via a simple "Bubble" sort. */
01118     i = 0;
01119     while (i < nodes-1)
01120     {
01121       if (nodeX[i]>nodeX[i+1])
01122       {
01123         swap = nodeX[i];
01124         nodeX[i] = nodeX[i+1];
01125         nodeX[i+1] = swap;
01126         if(i)
01127         {
01128           i--;
01129         }
01130       }
01131       else
01132       {
01133         i++;
01134       }
01135     }
01136
01137     /*  Fill the pixels between node pairs. */
01138     for (i = 0; i < nodes; i+=2)
01139     {
01140       if(nodeX[i] >= IMAGE_RIGHT)
01141       {
01142         break;
01143       }
01144       if(nodeX[i+1] > IMAGE_LEFT)
01145       {
01146         if (nodeX[i] < IMAGE_LEFT)
01147         {
01148           nodeX[i]=IMAGE_LEFT;
01149         }
01150         if(nodeX[i+1] > IMAGE_RIGHT)
01151         {
01152           nodeX[i+1] = IMAGE_RIGHT;
01153         }
01154         LCD_SetTextColor(BackColor);
01155         LCD_DrawLine(pixelY, nodeX[i+1], nodeX[i+1] - nodeX[i], LCD_DIR_HORIZONTAL);
01156         LCD_SetTextColor(TextColor);
01157         PutPixel(pixelY, nodeX[i+1]);
01158         PutPixel(pixelY, nodeX[i]);
01159         /* for (j=nodeX[i]; j<nodeX[i+1]; j++) PutPixel(j,pixelY); */
01160       }
01161     }
01162   }
01163
01164   /* draw the edges */
01165   LCD_SetTextColor(TextColor);
01166 }
01167
01168 /**
01169   * @brief  Writes to the selected LCD register.
01170   * @param  LCD_Reg: address of the selected register.
01171   * @param  LCD_RegValue: value to write to the selected register.
01172   * @retval None
01173   */
01174 void LCD_WriteReg(uint8_t LCD_Reg, uint16_t LCD_RegValue)
01175 {
01176   /* Write 16-bit Index, then Write Reg */
01177   LCD->LCD_REG = LCD_Reg;
01178   /* Write 16-bit Reg */
01179   LCD->LCD_RAM = LCD_RegValue;
01180 }
01181
01182
01183 /**
01184   * @brief  Reads the selected LCD Register.
01185   * @param  LCD_Reg: address of the selected register.
01186   * @retval LCD Register Value.
01187   */
01188 uint16_t LCD_ReadReg(uint8_t LCD_Reg)
01189 {
01190   /* Write 16-bit Index (then Read Reg) */
01191   LCD->LCD_REG = LCD_Reg;
01192   /* Read 16-bit Reg */
01193   return (LCD->LCD_RAM);
01194 }
01195
01196
01197 /**
01198   * @brief  Prepare to write to the LCD RAM.
01199   * @param  None
01200   * @retval None
01201   */
01202 void LCD_WriteRAM_Prepare(void)
01203 {
01204   LCD->LCD_REG = LCD_REG_34;
01205 }
01206
01207
01208 /**
01209   * @brief  Writes to the LCD RAM.
01210   * @param  RGB_Code: the pixel color in RGB mode (5-6-5).
01211   * @retval None
01212   */
01213 void LCD_WriteRAM(uint16_t RGB_Code)
01214 {
01215   /* Write 16-bit GRAM Reg */
01216   LCD->LCD_RAM = RGB_Code;
01217 }
01218
01219
01220 /**
01221   * @brief  Reads the LCD RAM.
01222   * @param  None
01223   * @retval LCD RAM Value.
01224   */
01225 uint16_t LCD_ReadRAM(void)
01226 {
01227   /* Write 16-bit Index (then Read Reg) */
01228   LCD->LCD_REG = LCD_REG_34; /* Select GRAM Reg */
01229   /* Read 16-bit Reg */
01230   return LCD->LCD_RAM;
01231 }
01232
01233
01234 /**
01235   * @brief  Power on the LCD.
01236   * @param  None
01237   * @retval None
01238   */
01239 void LCD_PowerOn(void)
01240 {
01241 /* Power On sequence ---------------------------------------------------------*/
01242   LCD_WriteReg(LCD_REG_16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
01243   LCD_WriteReg(LCD_REG_17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */
01244   LCD_WriteReg(LCD_REG_18, 0x0000); /* VREG1OUT voltage */
01245   LCD_WriteReg(LCD_REG_19, 0x0000); /* VDV[4:0] for VCOM amplitude*/
01246   _delay_(20);                 /* Dis-charge capacitor power voltage (200ms) */
01247   LCD_WriteReg(LCD_REG_16, 0x17B0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
01248   LCD_WriteReg(LCD_REG_17, 0x0137); /* DC1[2:0], DC0[2:0], VC[2:0] */
01249   _delay_(5);                  /* Delay 50 ms */
01250   LCD_WriteReg(LCD_REG_18, 0x0139); /* VREG1OUT voltage */
01251   _delay_(5);                  /* Delay 50 ms */
01252   LCD_WriteReg(LCD_REG_19, 0x1d00); /* VDV[4:0] for VCOM amplitude */
01253   LCD_WriteReg(LCD_REG_41, 0x0013); /* VCM[4:0] for VCOMH */
01254   _delay_(5);                  /* Delay 50 ms */
01255   LCD_WriteReg(LCD_REG_7, 0x0173);  /* 262K color and display ON */
01256 }
01257
01258
01259 /**
01260   * @brief  Enables the Display.
01261   * @param  None
01262   * @retval None
01263   */
01264 void LCD_DisplayOn(void)
01265 {
01266   /* Display On */
01267   LCD_WriteReg(LCD_REG_7, 0x0173); /* 262K color and display ON */
01268 }
01269
01270
01271 /**
01272   * @brief  Disables the Display.
01273   * @param  None
01274   * @retval None
01275   */
01276 void LCD_DisplayOff(void)
01277 {
01278   /* Display Off */
01279   LCD_WriteReg(LCD_REG_7, 0x0);
01280 }
01281
01282
01283 /**
01284   * @brief  Configures LCD Control lines (FSMC Pins) in alternate function mode.
01285   * @param  None
01286   * @retval None
01287   */
01288 void LCD_CtrlLinesConfig(void)
01289 {
01290   GPIO_InitTypeDef GPIO_InitStructure;
01291
01292   /* Enable FSMC, GPIOD, GPIOE, GPIOF, GPIOG and AFIO clocks */
01293   RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, ENABLE);
01294   RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOE |
01295                          RCC_APB2Periph_GPIOF | RCC_APB2Periph_GPIOG |
01296                          RCC_APB2Periph_AFIO, ENABLE);
01297
01298   /* Set PD.00(D2), PD.01(D3), PD.04(NOE), PD.05(NWE), PD.08(D13), PD.09(D14),
01299      PD.10(D15), PD.14(D0), PD.15(D1) as alternate function push pull */
01300   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_4 | GPIO_Pin_5 |
01301                                 GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_14 |
01302                                 GPIO_Pin_15;
01303   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
01304   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
01305   GPIO_Init(GPIOD, &GPIO_InitStructure);
01306
01307   /* Set PE.07(D4), PE.08(D5), PE.09(D6), PE.10(D7), PE.11(D8), PE.12(D9), PE.13(D10),
01308      PE.14(D11), PE.15(D12) as alternate function push pull */
01309   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 |
01310                                 GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 |
01311                                 GPIO_Pin_15;
01312   GPIO_Init(GPIOE, &GPIO_InitStructure);
01313
01314   /* Set PF.00(A0 (RS)) as alternate function push pull */
01315   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0;
01316   GPIO_Init(GPIOF, &GPIO_InitStructure);
01317
01318   /* Set PG.12(NE4 (LCD/CS)) as alternate function push pull */
01319   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12;
01320   GPIO_Init(GPIOG, &GPIO_InitStructure);
01321 }
01322
01323 /**
01324   * @brief  Configures the Parallel interface (FSMC) for LCD(Parallel mode)
01325   * @param  None
01326   * @retval None
01327   */
01328 void LCD_FSMCConfig(void)
01329 {
01330   FSMC_NORSRAMInitTypeDef  FSMC_NORSRAMInitStructure;
01331   FSMC_NORSRAMTimingInitTypeDef  p;
01332 /*-- FSMC Configuration ------------------------------------------------------*/
01333 /*----------------------- SRAM Bank 4 ----------------------------------------*/
01334   /* FSMC_Bank1_NORSRAM4 configuration */
01335   p.FSMC_AddressSetupTime = 1;
01336   p.FSMC_AddressHoldTime = 0;
01337   p.FSMC_DataSetupTime = 2;
01338   p.FSMC_BusTurnAroundDuration = 0;
01339   p.FSMC_CLKDivision = 0;
01340   p.FSMC_DataLatency = 0;
01341   p.FSMC_AccessMode = FSMC_AccessMode_A;
01342   /* Color LCD configuration ------------------------------------
01343      LCD configured as follow:
01344         - Data/Address MUX = Disable
01345         - Memory Type = SRAM
01346         - Data Width = 16bit
01347         - Write Operation = Enable
01348         - Extended Mode = Enable
01349         - Asynchronous Wait = Disable */
01350   FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM4;
01351   FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
01352   FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM;
01353   FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
01354   FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
01355   FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
01356   FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
01357   FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
01358   FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
01359   FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
01360   FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
01361   FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
01362   FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
01363   FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
01364   FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
01365   FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);
01366   /* BANK 4 (of NOR/SRAM Bank) is enabled */
01367   FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM4, ENABLE);
01368 }
01369
01370 /**
01371   * @brief  Displays a pixel.
01372   * @param  x: pixel x.
01373   * @param  y: pixel y.
01374   * @retval None
01375   */
01376 static void PutPixel(int16_t x, int16_t y)
01377 {
01378   if(x < 0 || x > 239 || y < 0 || y > 319)
01379   {
01380     return;
01381   }
01382   LCD_DrawLine(x, y, 1, LCD_DIR_HORIZONTAL);
01383 }
01384
01385 #ifndef USE_Delay
01386 /**
01387   * @brief  Inserts a delay time.
01388   * @param  nCount: specifies the delay time length.
01389   * @retval None
01390   */
01391 static void delay(vu32 nCount)
01392 {
01393   vu32 index = 0;
01394   for(index = (34000 * nCount); index != 0; index--)
01395   {
01396   }
01397 }
01398 #endif /* USE_Delay*/
01399 /**
01400   * @}
01401   */
01402
01403 /**
01404   * @}
01405   */
01406
01407 /**
01408   * @}
01409   */
01410
01411 /**
01412   * @}
01413   */
01414
01415 /**
01416   * @}
01417   */
01418
01419 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: stm32100e_eval_lcd.h Source File

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  • STM32100E_EVAL

stm32100e_eval_lcd.h

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32100e_eval_lcd.h
00004   * @author  MCD Application Team
00005   * @version V4.5.0
00006   * @date    07-March-2011
00007   * @brief   This file contains all the functions prototypes for the stm32100e_eval_lcd
00008   *          firmware driver.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00013   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00014   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00015   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00016   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00017   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00018   *
00019   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00020   ******************************************************************************
00021   */
00022
00023 /* Define to prevent recursive inclusion -------------------------------------*/
00024 #ifndef __STM32100E_EVAL_LCD_H
00025 #define __STM32100E_EVAL_LCD_H
00026
00027 #ifdef __cplusplus
00028  extern "C" {
00029 #endif
00030
00031 /* Includes ------------------------------------------------------------------*/
00032 #include "stm32f10x.h"
00033 #include "../Common/fonts.h"
00034
00035 /** @addtogroup Utilities
00036   * @{
00037   */
00038
00039 /** @addtogroup STM32_EVAL
00040   * @{
00041   */
00042
00043 /** @addtogroup STM32100E_EVAL
00044   * @{
00045   */
00046
00047 /** @addtogroup STM32100E_EVAL_LCD
00048   * @{
00049   */
00050
00051 /** @defgroup STM32100E_EVAL_LCD_Exported_Types
00052   * @{
00053   */
00054 typedef struct
00055 {
00056   int16_t X;
00057   int16_t Y;
00058 } Point, * pPoint;
00059 /**
00060   * @}
00061   */
00062
00063 /** @defgroup STM32100E_EVAL_LCD_Exported_Constants
00064   * @{
00065   */
00066
00067 /**
00068  * @brief Uncomment the line below if you want to use user defined Delay function
00069  *        (for precise timing), otherwise default _delay_ function defined within
00070  *         this driver is used (less precise timing).
00071  */
00072 /* #define USE_Delay */
00073
00074 #ifdef USE_Delay
00075 #include "main.h"
00076   #define _delay_     Delay  /* !< User can provide more timing precise _delay_ function
00077                                    (with 10ms time base), using SysTick for example */
00078 #else
00079   #define _delay_     delay      /* !< Default _delay_ function with less precise timing */
00080 #endif
00081
00082 /**
00083   * @brief  LCD Registers
00084   */
00085 #define LCD_REG_0             0x00
00086 #define LCD_REG_1             0x01
00087 #define LCD_REG_2             0x02
00088 #define LCD_REG_3             0x03
00089 #define LCD_REG_4             0x04
00090 #define LCD_REG_5             0x05
00091 #define LCD_REG_6             0x06
00092 #define LCD_REG_7             0x07
00093 #define LCD_REG_8             0x08
00094 #define LCD_REG_9             0x09
00095 #define LCD_REG_10            0x0A
00096 #define LCD_REG_12            0x0C
00097 #define LCD_REG_13            0x0D
00098 #define LCD_REG_14            0x0E
00099 #define LCD_REG_15            0x0F
00100 #define LCD_REG_16            0x10
00101 #define LCD_REG_17            0x11
00102 #define LCD_REG_18            0x12
00103 #define LCD_REG_19            0x13
00104 #define LCD_REG_20            0x14
00105 #define LCD_REG_21            0x15
00106 #define LCD_REG_22            0x16
00107 #define LCD_REG_23            0x17
00108 #define LCD_REG_24            0x18
00109 #define LCD_REG_25            0x19
00110 #define LCD_REG_26            0x1A
00111 #define LCD_REG_27            0x1B
00112 #define LCD_REG_28            0x1C
00113 #define LCD_REG_29            0x1D
00114 #define LCD_REG_30            0x1E
00115 #define LCD_REG_31            0x1F
00116 #define LCD_REG_32            0x20
00117 #define LCD_REG_33            0x21
00118 #define LCD_REG_34            0x22
00119 #define LCD_REG_36            0x24
00120 #define LCD_REG_37            0x25
00121 #define LCD_REG_40            0x28
00122 #define LCD_REG_41            0x29
00123 #define LCD_REG_43            0x2B
00124 #define LCD_REG_45            0x2D
00125 #define LCD_REG_48            0x30
00126 #define LCD_REG_49            0x31
00127 #define LCD_REG_50            0x32
00128 #define LCD_REG_51            0x33
00129 #define LCD_REG_52            0x34
00130 #define LCD_REG_53            0x35
00131 #define LCD_REG_54            0x36
00132 #define LCD_REG_55            0x37
00133 #define LCD_REG_56            0x38
00134 #define LCD_REG_57            0x39
00135 #define LCD_REG_58            0x3A
00136 #define LCD_REG_59            0x3B
00137 #define LCD_REG_60            0x3C
00138 #define LCD_REG_61            0x3D
00139 #define LCD_REG_62            0x3E
00140 #define LCD_REG_63            0x3F
00141 #define LCD_REG_64            0x40
00142 #define LCD_REG_65            0x41
00143 #define LCD_REG_66            0x42
00144 #define LCD_REG_67            0x43
00145 #define LCD_REG_68            0x44
00146 #define LCD_REG_69            0x45
00147 #define LCD_REG_70            0x46
00148 #define LCD_REG_71            0x47
00149 #define LCD_REG_72            0x48
00150 #define LCD_REG_73            0x49
00151 #define LCD_REG_74            0x4A
00152 #define LCD_REG_75            0x4B
00153 #define LCD_REG_76            0x4C
00154 #define LCD_REG_77            0x4D
00155 #define LCD_REG_78            0x4E
00156 #define LCD_REG_79            0x4F
00157 #define LCD_REG_80            0x50
00158 #define LCD_REG_81            0x51
00159 #define LCD_REG_82            0x52
00160 #define LCD_REG_83            0x53
00161 #define LCD_REG_96            0x60
00162 #define LCD_REG_97            0x61
00163 #define LCD_REG_106           0x6A
00164 #define LCD_REG_118           0x76
00165 #define LCD_REG_128           0x80
00166 #define LCD_REG_129           0x81
00167 #define LCD_REG_130           0x82
00168 #define LCD_REG_131           0x83
00169 #define LCD_REG_132           0x84
00170 #define LCD_REG_133           0x85
00171 #define LCD_REG_134           0x86
00172 #define LCD_REG_135           0x87
00173 #define LCD_REG_136           0x88
00174 #define LCD_REG_137           0x89
00175 #define LCD_REG_139           0x8B
00176 #define LCD_REG_140           0x8C
00177 #define LCD_REG_141           0x8D
00178 #define LCD_REG_143           0x8F
00179 #define LCD_REG_144           0x90
00180 #define LCD_REG_145           0x91
00181 #define LCD_REG_146           0x92
00182 #define LCD_REG_147           0x93
00183 #define LCD_REG_148           0x94
00184 #define LCD_REG_149           0x95
00185 #define LCD_REG_150           0x96
00186 #define LCD_REG_151           0x97
00187 #define LCD_REG_152           0x98
00188 #define LCD_REG_153           0x99
00189 #define LCD_REG_154           0x9A
00190 #define LCD_REG_157           0x9D
00191 #define LCD_REG_192           0xC0
00192 #define LCD_REG_193           0xC1
00193 #define LCD_REG_229           0xE5
00194
00195 /**
00196   * @brief  LCD color
00197   */
00198 #define LCD_COLOR_WHITE          0xFFFF
00199 #define LCD_COLOR_BLACK          0x0000
00200 #define LCD_COLOR_GREY           0xF7DE
00201 #define LCD_COLOR_BLUE           0x001F
00202 #define LCD_COLOR_BLUE2          0x051F
00203 #define LCD_COLOR_RED            0xF800
00204 #define LCD_COLOR_MAGENTA        0xF81F
00205 #define LCD_COLOR_GREEN          0x07E0
00206 #define LCD_COLOR_CYAN           0x7FFF
00207 #define LCD_COLOR_YELLOW         0xFFE0
00208
00209 /**
00210   * @brief  LCD Lines depending on the chosen fonts.
00211   */
00212 #define LCD_LINE_0               LINE(0)
00213 #define LCD_LINE_1               LINE(1)
00214 #define LCD_LINE_2               LINE(2)
00215 #define LCD_LINE_3               LINE(3)
00216 #define LCD_LINE_4               LINE(4)
00217 #define LCD_LINE_5               LINE(5)
00218 #define LCD_LINE_6               LINE(6)
00219 #define LCD_LINE_7               LINE(7)
00220 #define LCD_LINE_8               LINE(8)
00221 #define LCD_LINE_9               LINE(9)
00222 #define LCD_LINE_10              LINE(10)
00223 #define LCD_LINE_11              LINE(11)
00224 #define LCD_LINE_12              LINE(12)
00225 #define LCD_LINE_13              LINE(13)
00226 #define LCD_LINE_14              LINE(14)
00227 #define LCD_LINE_15              LINE(15)
00228 #define LCD_LINE_16              LINE(16)
00229 #define LCD_LINE_17              LINE(17)
00230 #define LCD_LINE_18              LINE(18)
00231 #define LCD_LINE_19              LINE(19)
00232 #define LCD_LINE_20              LINE(20)
00233 #define LCD_LINE_21              LINE(21)
00234 #define LCD_LINE_22              LINE(22)
00235 #define LCD_LINE_23              LINE(23)
00236 #define LCD_LINE_24              LINE(24)
00237 #define LCD_LINE_25              LINE(25)
00238 #define LCD_LINE_26              LINE(26)
00239 #define LCD_LINE_27              LINE(27)
00240 #define LCD_LINE_28              LINE(28)
00241 #define LCD_LINE_29              LINE(29)
00242
00243 /**
00244   * @brief LCD default font
00245   */
00246 #define LCD_DEFAULT_FONT         Font16x24
00247
00248 /**
00249   * @brief  LCD Direction
00250   */
00251 #define LCD_DIR_HORIZONTAL       0x0000
00252 #define LCD_DIR_VERTICAL         0x0001
00253
00254 /**
00255   * @brief  LCD Size (Width and Height)
00256   */
00257 #define LCD_PIXEL_WIDTH          0x0140
00258 #define LCD_PIXEL_HEIGHT         0x00F0
00259
00260 /**
00261   * @}
00262   */
00263
00264 /** @defgroup STM32100E_EVAL_LCD_Exported_Macros
00265   * @{
00266   */
00267 #define ASSEMBLE_RGB(R, G, B)    ((((R)& 0xF8) << 8) | (((G) & 0xFC) << 3) | (((B) & 0xF8) >> 3))
00268 /**
00269   * @}
00270   */
00271
00272 /** @defgroup STM32100E_EVAL_LCD_Exported_Functions
00273   * @{
00274   */
00275 /** @defgroup
00276   * @{
00277   */
00278 void LCD_DeInit(void);
00279 void STM32100E_LCD_Init(void);
00280 void LCD_SetColors(__IO uint16_t _TextColor, __IO uint16_t _BackColor);
00281 void LCD_GetColors(__IO uint16_t *_TextColor, __IO uint16_t *_BackColor);
00282 void LCD_SetTextColor(__IO uint16_t Color);
00283 void LCD_SetBackColor(__IO uint16_t Color);
00284 void LCD_ClearLine(uint8_t Line);
00285 void LCD_Clear(uint16_t Color);
00286 void LCD_SetCursor(uint8_t Xpos, uint16_t Ypos);
00287 void LCD_DrawChar(uint8_t Xpos, uint16_t Ypos, const uint16_t *c);
00288 void LCD_DisplayChar(uint8_t Line, uint16_t Column, uint8_t Ascii);
00289 void LCD_SetFont(sFONT *fonts);
00290 sFONT *LCD_GetFont(void);
00291 void LCD_DisplayStringLine(uint8_t Line, uint8_t *ptr);
00292 void LCD_SetDisplayWindow(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width);
00293 void LCD_WindowModeDisable(void);
00294 void LCD_DrawLine(uint8_t Xpos, uint16_t Ypos, uint16_t Length, uint8_t Direction);
00295 void LCD_DrawRect(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width);
00296 void LCD_DrawCircle(uint8_t Xpos, uint16_t Ypos, uint16_t Radius);
00297 void LCD_DrawMonoPict(const uint32_t *Pict);
00298 void LCD_WriteBMP(uint32_t BmpAddress);
00299 void LCD_DrawUniLine(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2);
00300 void LCD_DrawFullRect(uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height);
00301 void LCD_DrawFullCircle(uint16_t Xpos, uint16_t Ypos, uint16_t Radius);
00302 void LCD_PolyLine(pPoint Points, uint16_t PointCount);
00303 void LCD_PolyLineRelative(pPoint Points, uint16_t PointCount);
00304 void LCD_ClosedPolyLine(pPoint Points, uint16_t PointCount);
00305 void LCD_ClosedPolyLineRelative(pPoint Points, uint16_t PointCount);
00306 void LCD_FillPolyLine(pPoint Points, uint16_t PointCount);
00307 /**
00308   * @}
00309   */
00310
00311 /** @defgroup
00312   * @{
00313   */
00314 void LCD_WriteReg(uint8_t LCD_Reg, uint16_t LCD_RegValue);
00315 uint16_t LCD_ReadReg(uint8_t LCD_Reg);
00316 void LCD_WriteRAM_Prepare(void);
00317 void LCD_WriteRAM(uint16_t RGB_Code);
00318 uint16_t LCD_ReadRAM(void);
00319 void LCD_PowerOn(void);
00320 void LCD_DisplayOn(void);
00321 void LCD_DisplayOff(void);
00322 /**
00323   * @}
00324   */
00325
00326 /** @defgroup
00327   * @{
00328   */
00329 void LCD_CtrlLinesConfig(void);
00330 void LCD_FSMCConfig(void);
00331 /**
00332   * @}
00333   */
00334
00335 /**
00336   * @}
00337   */
00338 #ifdef __cplusplus
00339 }
00340 #endif
00341
00342 #endif /* __STM32100E_EVAL_LCD_H */
00343 /**
00344   * @}
00345   */
00346
00347 /**
00348   * @}
00349   */
00350
00351 /**
00352   * @}
00353   */
00354
00355 /**
00356   * @}
00357   */
00358
00359 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: system_stm32f10x.h Source File

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Libraries
  • CMSIS
  • CM3
  • DeviceSupport
  • ST
  • STM32F10x

system_stm32f10x.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    system_stm32f10x.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    11-March-2011
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Header File.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /** @addtogroup CMSIS
00023   * @{
00024   */
00025
00026 /** @addtogroup stm32f10x_system
00027   * @{
00028   */
00029
00030 /**
00031   * @brief Define to prevent recursive inclusion
00032   */
00033 #ifndef __SYSTEM_STM32F10X_H
00034 #define __SYSTEM_STM32F10X_H
00035
00036 #ifdef __cplusplus
00037  extern "C" {
00038 #endif
00039
00040 /** @addtogroup STM32F10x_System_Includes
00041   * @{
00042   */
00043
00044 /**
00045   * @}
00046   */
00047
00048
00049 /** @addtogroup STM32F10x_System_Exported_types
00050   * @{
00051   */
00052
00053 extern uint32_t SystemCoreClock;          /*!< System Clock Frequency (Core Clock) */
00054
00055 /**
00056   * @}
00057   */
00058
00059 /** @addtogroup STM32F10x_System_Exported_Constants
00060   * @{
00061   */
00062
00063 /**
00064   * @}
00065   */
00066
00067 /** @addtogroup STM32F10x_System_Exported_Macros
00068   * @{
00069   */
00070
00071 /**
00072   * @}
00073   */
00074
00075 /** @addtogroup STM32F10x_System_Exported_Functions
00076   * @{
00077   */
00078
00079 extern void SystemInit(void);
00080 extern void SystemCoreClockUpdate(void);
00081 /**
00082   * @}
00083   */
00084
00085 #ifdef __cplusplus
00086 }
00087 #endif
00088
00089 #endif /*__SYSTEM_STM32F10X_H */
00090
00091 /**
00092   * @}
00093   */
00094
00095 /**
00096   * @}
00097   */
00098 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: main.h Source File

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  • Project
  • STM32F10x_StdPeriph_Examples
  • SysTick
  • TimeBase

SysTick/TimeBase/main.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    SysTick/TimeBase/main.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Header for main.c module
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __MAIN_H
00024 #define __MAIN_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32f10x.h"
00028 #include "stm32_eval.h"
00029
00030 /* Exported types ------------------------------------------------------------*/
00031 /* Exported constants --------------------------------------------------------*/
00032 /* Exported macro ------------------------------------------------------------*/
00033 /* Exported functions ------------------------------------------------------- */
00034 void TimingDelay_Decrement(void);
00035
00036 #endif /* __MAIN_H */
00037
00038 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: truestudio_project_template.txt File Reference

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  • Globals

truestudio_project_template.txt File Reference

STM32F10x Standard Peripherals Library: Footer

For complete documentation on STM32(CORTEX M3) 32-bit Microcontrollers platform visit www.st.com/STM32


STM32F10x Standard Peripherals Firmware Library: TrueSTUDIO Project Template

  • STM32F10x Standard Peripherals Project Template

TrueSTUDIO Project Template

  • STM32100E-EVAL
    • TrueSTUDIO Project Template for High-density Value line devices
  • STM32100B-EVAL
    • TrueSTUDIO Project Template for Medium-density Value line devices
  • STM3210B-EVAL
    • TrueSTUDIO Project Template for Medium-density devices
  • STM3210C-EVAL
    • TrueSTUDIO Project Template for Connectivity line devices
  • STM3210E-EVAL
    • TrueSTUDIO Project Template for High-density devices
  • STM3210E-EVAL_XL
    • TrueSTUDIO Project Template for XL-density devices


STM32F10x Standard Peripherals Firmware Library: platform_config.h Source File

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  • Project
  • STM32F10x_StdPeriph_Examples
  • USART
  • DMA_Interrupt

USART/DMA_Interrupt/platform_config.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    USART/DMA_Interrupt/platform_config.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Evaluation board specific configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __PLATFORM_CONFIG_H
00024 #define __PLATFORM_CONFIG_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027
00028 /* Exported types ------------------------------------------------------------*/
00029 /* Exported constants --------------------------------------------------------*/
00030 /* Uncomment the line corresponding to the STMicroelectronics evaluation board
00031    used to run the example */
00032 #if !defined (USE_STM32100B_EVAL) && !defined (USE_STM3210B_EVAL) &&  !defined (USE_STM3210E_EVAL) &&  !defined (USE_STM32100E_EVAL)
00033  //#define USE_STM32100B_EVAL
00034  //#define USE_STM3210B_EVAL
00035  //#define USE_STM3210E_EVAL
00036  //#define USE_STM32100E_EVAL
00037  #define USE_STM3210C_EVAL
00038 #endif
00039
00040 /* Define the STM32F10x hardware depending on the used evaluation board */
00041 #if defined(USE_STM3210B_EVAL) || defined (USE_STM32100B_EVAL)
00042
00043   #define USARTy                   USART1
00044   #define USARTy_GPIO              GPIOA
00045   #define USARTy_CLK               RCC_APB2Periph_USART1
00046   #define USARTy_GPIO_CLK          RCC_APB2Periph_GPIOA
00047   #define USARTy_RxPin             GPIO_Pin_10
00048   #define USARTy_TxPin             GPIO_Pin_9
00049   #define USARTy_Tx_DMA_Channel    DMA1_Channel4
00050   #define USARTy_Tx_DMA_FLAG       DMA1_FLAG_TC4
00051   #define USARTy_DR_Base           0x40013804
00052
00053   #define USARTz                   USART2
00054   #define USARTz_GPIO              GPIOD
00055   #define USARTz_CLK               RCC_APB1Periph_USART2
00056   #define USARTz_GPIO_CLK          RCC_APB2Periph_GPIOD
00057   #define USARTz_RxPin             GPIO_Pin_6
00058   #define USARTz_TxPin             GPIO_Pin_5
00059   #define USARTz_Tx_DMA_Channel    DMA1_Channel7
00060   #define USARTz_Tx_DMA_FLAG       DMA1_FLAG_TC7
00061   #define USARTz_DR_Base           0x40004404
00062   #define USARTz_IRQn              USART2_IRQn
00063
00064 #elif defined (USE_STM3210E_EVAL) || defined (USE_STM32100E_EVAL)
00065
00066   #define USARTy                   USART1
00067   #define USARTy_GPIO              GPIOA
00068   #define USARTy_CLK               RCC_APB2Periph_USART1
00069   #define USARTy_GPIO_CLK          RCC_APB2Periph_GPIOA
00070   #define USARTy_RxPin             GPIO_Pin_10
00071   #define USARTy_TxPin             GPIO_Pin_9
00072   #define USARTy_Tx_DMA_Channel    DMA1_Channel4
00073   #define USARTy_Tx_DMA_FLAG       DMA1_FLAG_TC4
00074   #define USARTy_DR_Base           0x40013804
00075
00076   #define USARTz                   USART2
00077   #define USARTz_GPIO              GPIOA
00078   #define USARTz_CLK               RCC_APB1Periph_USART2
00079   #define USARTz_GPIO_CLK          RCC_APB2Periph_GPIOA
00080   #define USARTz_RxPin             GPIO_Pin_3
00081   #define USARTz_TxPin             GPIO_Pin_2
00082   #define USARTz_Tx_DMA_Channel    DMA1_Channel7
00083   #define USARTz_Tx_DMA_FLAG       DMA1_FLAG_TC7
00084   #define USARTz_DR_Base           0x40004404
00085   #define USARTz_IRQn              USART2_IRQn
00086
00087 #elif defined USE_STM3210C_EVAL
00088
00089   #define USARTy                   USART2
00090   #define USARTy_GPIO              GPIOD
00091   #define USARTy_CLK               RCC_APB1Periph_USART2
00092   #define USARTy_GPIO_CLK          RCC_APB2Periph_GPIOD
00093   #define USARTy_RxPin             GPIO_Pin_6
00094   #define USARTy_TxPin             GPIO_Pin_5
00095   #define USARTy_Tx_DMA_Channel    DMA1_Channel7
00096   #define USARTy_Tx_DMA_FLAG       DMA1_FLAG_TC7
00097   #define USARTy_DR_Base           0x40004404
00098
00099   #define USARTz                   USART3
00100   #define USARTz_GPIO              GPIOC
00101   #define USARTz_CLK               RCC_APB1Periph_USART3
00102   #define USARTz_GPIO_CLK          RCC_APB2Periph_GPIOC
00103   #define USARTz_RxPin             GPIO_Pin_11
00104   #define USARTz_TxPin             GPIO_Pin_10
00105   #define USARTz_Tx_DMA_Channel    DMA1_Channel2
00106   #define USARTz_Tx_DMA_FLAG       DMA1_FLAG_TC2
00107   #define USARTz_DR_Base           0x40004804
00108   #define USARTz_IRQn              USART3_IRQn
00109
00110 #endif /* USE_STM3210B_EVAL */
00111
00112 /* Exported macro ------------------------------------------------------------*/
00113 /* Exported functions ------------------------------------------------------- */
00114
00115 #endif /* __PLATFORM_CONFIG_H */
00116
00117 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: platform_config.h Source File

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  • Project
  • STM32F10x_StdPeriph_Examples
  • USART
  • DMA_Polling

USART/DMA_Polling/platform_config.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    USART/DMA_Polling/platform_config.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Evaluation board specific configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __PLATFORM_CONFIG_H
00024 #define __PLATFORM_CONFIG_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027
00028 /* Exported types ------------------------------------------------------------*/
00029 /* Exported constants --------------------------------------------------------*/
00030 /* Uncomment the line corresponding to the STMicroelectronics evaluation board
00031    used to run the example */
00032 #if !defined (USE_STM32100B_EVAL) && !defined (USE_STM3210B_EVAL) &&  !defined (USE_STM3210E_EVAL) &&  !defined (USE_STM3210C_EVAL) &&  !defined (USE_STM32100E_EVAL)
00033  //#define USE_STM32100B_EVAL
00034  //#define USE_STM3210B_EVAL
00035  //#define USE_STM3210E_EVAL
00036  //#define USE_STM32100E_EVAL
00037  #define USE_STM3210C_EVAL
00038 #endif
00039
00040 /* Define the STM32F10x hardware depending on the used evaluation board */
00041 #if defined(USE_STM3210B_EVAL) || defined(USE_STM32100B_EVAL)
00042
00043   #define USARTy                   USART1
00044   #define USARTy_GPIO              GPIOA
00045   #define USARTy_CLK               RCC_APB2Periph_USART1
00046   #define USARTy_GPIO_CLK          RCC_APB2Periph_GPIOA
00047   #define USARTy_RxPin             GPIO_Pin_10
00048   #define USARTy_TxPin             GPIO_Pin_9
00049   #define USARTy_Tx_DMA_Channel    DMA1_Channel4
00050   #define USARTy_Tx_DMA_FLAG       DMA1_FLAG_TC4
00051   #define USARTy_Rx_DMA_Channel    DMA1_Channel5
00052   #define USARTy_Rx_DMA_FLAG       DMA1_FLAG_TC5
00053   #define USARTy_DR_Base           0x40013804
00054
00055   #define USARTz                   USART2
00056   #define USARTz_GPIO              GPIOD
00057   #define USARTz_CLK               RCC_APB1Periph_USART2
00058   #define USARTz_GPIO_CLK          RCC_APB2Periph_GPIOD
00059   #define USARTz_RxPin             GPIO_Pin_6
00060   #define USARTz_TxPin             GPIO_Pin_5
00061   #define USARTz_Tx_DMA_Channel    DMA1_Channel7
00062   #define USARTz_Tx_DMA_FLAG       DMA1_FLAG_TC7
00063   #define USARTz_Rx_DMA_Channel    DMA1_Channel6
00064   #define USARTz_Rx_DMA_FLAG       DMA1_FLAG_TC6
00065   #define USARTz_DR_Base           0x40004404
00066
00067 #elif defined USE_STM3210E_EVAL || defined(USE_STM32100E_EVAL)
00068
00069   #define USARTy                   USART1
00070   #define USARTy_GPIO              GPIOA
00071   #define USARTy_CLK               RCC_APB2Periph_USART1
00072   #define USARTy_GPIO_CLK          RCC_APB2Periph_GPIOA
00073   #define USARTy_RxPin             GPIO_Pin_10
00074   #define USARTy_TxPin             GPIO_Pin_9
00075   #define USARTy_Tx_DMA_Channel    DMA1_Channel4
00076   #define USARTy_Tx_DMA_FLAG       DMA1_FLAG_TC4
00077   #define USARTy_Rx_DMA_Channel    DMA1_Channel5
00078   #define USARTy_Rx_DMA_FLAG       DMA1_FLAG_TC5
00079   #define USARTy_DR_Base           0x40013804
00080
00081   #define USARTz                   USART2
00082   #define USARTz_GPIO              GPIOA
00083   #define USARTz_CLK               RCC_APB1Periph_USART2
00084   #define USARTz_GPIO_CLK          RCC_APB2Periph_GPIOA
00085   #define USARTz_RxPin             GPIO_Pin_3
00086   #define USARTz_TxPin             GPIO_Pin_2
00087   #define USARTz_Tx_DMA_Channel    DMA1_Channel7
00088   #define USARTz_Tx_DMA_FLAG       DMA1_FLAG_TC7
00089   #define USARTz_Rx_DMA_Channel    DMA1_Channel6
00090   #define USARTz_Rx_DMA_FLAG       DMA1_FLAG_TC6
00091   #define USARTz_DR_Base           0x40004404
00092
00093 #elif defined USE_STM3210C_EVAL
00094
00095   #define USARTy                   USART2
00096   #define USARTy_GPIO              GPIOD
00097   #define USARTy_CLK               RCC_APB1Periph_USART2
00098   #define USARTy_GPIO_CLK          RCC_APB2Periph_GPIOD
00099   #define USARTy_RxPin             GPIO_Pin_6
00100   #define USARTy_TxPin             GPIO_Pin_5
00101   #define USARTy_Tx_DMA_Channel    DMA1_Channel7
00102   #define USARTy_Tx_DMA_FLAG       DMA1_FLAG_TC7
00103   #define USARTy_Rx_DMA_Channel    DMA1_Channel6
00104   #define USARTy_Rx_DMA_FLAG       DMA1_FLAG_TC6
00105   #define USARTy_DR_Base           0x40004404
00106
00107   #define USARTz                   USART3
00108   #define USARTz_GPIO              GPIOC
00109   #define USARTz_CLK               RCC_APB1Periph_USART3
00110   #define USARTz_GPIO_CLK          RCC_APB2Periph_GPIOC
00111   #define USARTz_RxPin             GPIO_Pin_11
00112   #define USARTz_TxPin             GPIO_Pin_10
00113   #define USARTz_Tx_DMA_Channel    DMA1_Channel2
00114   #define USARTz_Tx_DMA_FLAG       DMA1_FLAG_TC2
00115   #define USARTz_Rx_DMA_Channel    DMA1_Channel3
00116   #define USARTz_Rx_DMA_FLAG       DMA1_FLAG_TC3
00117   #define USARTz_DR_Base           0x40004804
00118
00119 #endif /* USE_STM3210B_EVAL */
00120
00121 /* Exported macro ------------------------------------------------------------*/
00122 /* Exported functions ------------------------------------------------------- */
00123
00124 #endif /* __PLATFORM_CONFIG_H */
00125
00126 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: platform_config.h Source File

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  • HalfDuplex

USART/HalfDuplex/platform_config.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    USART/HalfDuplex/platform_config.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Evaluation board specific configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __PLATFORM_CONFIG_H
00024 #define __PLATFORM_CONFIG_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027
00028 /* Exported types ------------------------------------------------------------*/
00029 /* Exported constants --------------------------------------------------------*/
00030 /* Uncomment the line corresponding to the STMicroelectronics evaluation board
00031    used to run the example */
00032 #if !defined (USE_STM32100B_EVAL) && !defined (USE_STM3210B_EVAL) &&  !defined (USE_STM3210E_EVAL) &&  !defined (USE_STM3210C_EVAL) &&  !defined (USE_STM32100E_EVAL)
00033  //#define USE_STM32100B_EVAL
00034  //#define USE_STM3210B_EVAL
00035  //#define USE_STM3210E_EVAL
00036  //#define USE_STM32100E_EVAL
00037  #define USE_STM3210C_EVAL
00038 #endif
00039
00040 /* Define the STM32F10x hardware depending on the used evaluation board */
00041 #if defined(USE_STM3210B_EVAL) || defined (USE_STM32100B_EVAL)
00042
00043   #define USARTy                   USART1
00044   #define USARTy_GPIO              GPIOA
00045   #define USARTy_CLK               RCC_APB2Periph_USART1
00046   #define USARTy_GPIO_CLK          RCC_APB2Periph_GPIOA
00047   #define USARTy_TxPin             GPIO_Pin_9
00048
00049   #define USARTz                   USART2
00050   #define USARTz_GPIO              GPIOD
00051   #define USARTz_CLK               RCC_APB1Periph_USART2
00052   #define USARTz_GPIO_CLK          RCC_APB2Periph_GPIOD
00053   #define USARTz_TxPin             GPIO_Pin_5
00054
00055 #elif defined USE_STM3210E_EVAL || defined (USE_STM32100E_EVAL)
00056
00057   #define USARTy                   USART1
00058   #define USARTy_GPIO              GPIOA
00059   #define USARTy_CLK               RCC_APB2Periph_USART1
00060   #define USARTy_GPIO_CLK          RCC_APB2Periph_GPIOA
00061   #define USARTy_TxPin             GPIO_Pin_9
00062
00063   #define USARTz                   USART2
00064   #define USARTz_GPIO              GPIOA
00065   #define USARTz_CLK               RCC_APB1Periph_USART2
00066   #define USARTz_GPIO_CLK          RCC_APB2Periph_GPIOA
00067   #define USARTz_TxPin             GPIO_Pin_2
00068
00069 #elif defined USE_STM3210C_EVAL
00070
00071   #define USARTy                   USART2
00072   #define USARTy_GPIO              GPIOD
00073   #define USARTy_CLK               RCC_APB1Periph_USART2
00074   #define USARTy_GPIO_CLK          RCC_APB2Periph_GPIOD
00075   #define USARTy_TxPin             GPIO_Pin_5
00076
00077   #define USARTz                   USART3
00078   #define USARTz_GPIO              GPIOC
00079   #define USARTz_CLK               RCC_APB1Periph_USART3
00080   #define USARTz_GPIO_CLK          RCC_APB2Periph_GPIOC
00081   #define USARTz_TxPin             GPIO_Pin_10
00082
00083 #endif /* USE_STM3210B_EVAL */
00084
00085
00086 /* Exported macro ------------------------------------------------------------*/
00087 /* Exported functions ------------------------------------------------------- */
00088
00089 #endif /* __PLATFORM_CONFIG_H */
00090
00091 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: platform_config.h Source File

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USART/HyperTerminal_HwFlowControl/platform_config.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    USART/HyperTerminal_HwFlowControl/platform_config.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Evaluation board specific configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __PLATFORM_CONFIG_H
00024 #define __PLATFORM_CONFIG_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027
00028 /* Exported types ------------------------------------------------------------*/
00029 /* Exported constants --------------------------------------------------------*/
00030 /* Uncomment the line corresponding to the STMicroelectronics evaluation board
00031    used to run the example */
00032 #if !defined (USE_STM32100B_EVAL) && !defined (USE_STM3210B_EVAL) &&  !defined (USE_STM3210E_EVAL) &&  !defined (USE_STM32100E_EVAL)
00033  //#define USE_STM32100B_EVAL
00034  //#define USE_STM3210B_EVAL
00035  //#define USE_STM32100E_EVAL
00036  #define USE_STM3210E_EVAL
00037 #endif
00038
00039 /* Define the STM32F10x hardware depending on the used evaluation board */
00040 #if defined(USE_STM3210B_EVAL) || defined (USE_STM32100B_EVAL)
00041 #define  GPIOx                    GPIOD
00042 #define  RCC_APB2Periph_GPIOx     RCC_APB2Periph_GPIOD
00043 #define  GPIO_RTSPin              GPIO_Pin_4
00044 #define  GPIO_CTSPin              GPIO_Pin_3
00045 #define  GPIO_TxPin               GPIO_Pin_5
00046 #define  GPIO_RxPin               GPIO_Pin_6
00047 #elif defined (USE_STM3210E_EVAL) || defined (USE_STM32100E_EVAL)
00048 #define  GPIOx                    GPIOA
00049 #define  RCC_APB2Periph_GPIOx     RCC_APB2Periph_GPIOA
00050 #define  GPIO_RTSPin              GPIO_Pin_1
00051 #define  GPIO_CTSPin              GPIO_Pin_0
00052 #define  GPIO_TxPin               GPIO_Pin_2
00053 #define  GPIO_RxPin               GPIO_Pin_3
00054 #endif /* USE_STM3210B_EVAL */
00055
00056 /* Exported macro ------------------------------------------------------------*/
00057 /* Exported functions ------------------------------------------------------- */
00058
00059 #endif /* __PLATFORM_CONFIG_H */
00060
00061 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: platform_config.h Source File

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  • Interrupt

USART/Interrupt/platform_config.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    USART/Interrupt/platform_config.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Evaluation board specific configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __PLATFORM_CONFIG_H
00024 #define __PLATFORM_CONFIG_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027
00028 /* Exported types ------------------------------------------------------------*/
00029 /* Exported constants --------------------------------------------------------*/
00030 /* Uncomment the line corresponding to the STMicroelectronics evaluation board
00031    used to run the example */
00032 #if !defined (USE_STM3210B_EVAL) &&  !defined (USE_STM3210E_EVAL) &&  !defined (USE_STM3210C_EVAL) &&  !defined (USE_STM32100B_EVAL) &&  !defined (USE_STM32100E_EVAL)
00033  //#define USE_STM32100B_EVAL
00034  //#define USE_STM3210B_EVAL
00035  //#define USE_STM3210E_EVAL
00036  //#define USE_STM3210C_EVAL
00037  #define USE_STM32100E_EVAL
00038 #endif
00039
00040 /* Define the STM32F10x hardware depending on the used evaluation board */
00041 #ifdef USE_STM3210B_EVAL
00042
00043   #define USARTy                   USART1
00044   #define USARTy_GPIO              GPIOA
00045   #define USARTy_CLK               RCC_APB2Periph_USART1
00046   #define USARTy_GPIO_CLK          RCC_APB2Periph_GPIOA
00047   #define USARTy_RxPin             GPIO_Pin_10
00048   #define USARTy_TxPin             GPIO_Pin_9
00049   #define USARTy_IRQn              USART1_IRQn
00050   #define USARTy_IRQHandler        USART1_IRQHandler
00051
00052   #define USARTz                   USART2
00053   #define USARTz_GPIO              GPIOD
00054   #define USARTz_CLK               RCC_APB1Periph_USART2
00055   #define USARTz_GPIO_CLK          RCC_APB2Periph_GPIOD
00056   #define USARTz_RxPin             GPIO_Pin_6
00057   #define USARTz_TxPin             GPIO_Pin_5
00058   #define USARTz_IRQn              USART2_IRQn
00059   #define USARTz_IRQHandler        USART2_IRQHandler
00060
00061 #elif defined (USE_STM3210E_EVAL) || defined (USE_STM32100E_EVAL)
00062
00063   #define USARTy                   USART1
00064   #define USARTy_GPIO              GPIOA
00065   #define USARTy_CLK               RCC_APB2Periph_USART1
00066   #define USARTy_GPIO_CLK          RCC_APB2Periph_GPIOA
00067   #define USARTy_RxPin             GPIO_Pin_10
00068   #define USARTy_TxPin             GPIO_Pin_9
00069   #define USARTy_IRQn              USART1_IRQn
00070   #define USARTy_IRQHandler        USART1_IRQHandler
00071
00072   #define USARTz                   USART2
00073   #define USARTz_GPIO              GPIOA
00074   #define USARTz_CLK               RCC_APB1Periph_USART2
00075   #define USARTz_GPIO_CLK          RCC_APB2Periph_GPIOA
00076   #define USARTz_RxPin             GPIO_Pin_3
00077   #define USARTz_TxPin             GPIO_Pin_2
00078   #define USARTz_IRQn              USART2_IRQn
00079   #define USARTz_IRQHandler        USART2_IRQHandler
00080
00081 #elif defined USE_STM3210C_EVAL
00082
00083   #define USARTy                   USART2
00084   #define USARTy_GPIO              GPIOD
00085   #define USARTy_CLK               RCC_APB1Periph_USART2
00086   #define USARTy_GPIO_CLK          RCC_APB2Periph_GPIOD
00087   #define USARTy_RxPin             GPIO_Pin_6
00088   #define USARTy_TxPin             GPIO_Pin_5
00089   #define USARTy_IRQn              USART2_IRQn
00090   #define USARTy_IRQHandler        USART2_IRQHandler
00091
00092   #define USARTz                   USART3
00093   #define USARTz_GPIO              GPIOC
00094   #define USARTz_CLK               RCC_APB1Periph_USART3
00095   #define USARTz_GPIO_CLK          RCC_APB2Periph_GPIOC
00096   #define USARTz_RxPin             GPIO_Pin_11
00097   #define USARTz_TxPin             GPIO_Pin_10
00098   #define USARTz_IRQn              USART3_IRQn
00099   #define USARTz_IRQHandler        USART3_IRQHandler
00100
00101 #elif defined USE_STM32100B_EVAL
00102
00103   #define USARTy                   USART1
00104   #define USARTy_GPIO              GPIOA
00105   #define USARTy_CLK               RCC_APB2Periph_USART1
00106   #define USARTy_GPIO_CLK          RCC_APB2Periph_GPIOA
00107   #define USARTy_RxPin             GPIO_Pin_10
00108   #define USARTy_TxPin             GPIO_Pin_9
00109   #define USARTy_IRQn              USART1_IRQn
00110   #define USARTy_IRQHandler        USART1_IRQHandler
00111
00112   #define USARTz                   USART2
00113   #define USARTz_GPIO              GPIOD
00114   #define USARTz_CLK               RCC_APB1Periph_USART2
00115   #define USARTz_GPIO_CLK          RCC_APB2Periph_GPIOD
00116   #define USARTz_RxPin             GPIO_Pin_6
00117   #define USARTz_TxPin             GPIO_Pin_5
00118   #define USARTz_IRQn              USART2_IRQn
00119   #define USARTz_IRQHandler        USART2_IRQHandler
00120
00121 #endif /* USE_STM3210B_EVAL */
00122
00123 /* Exported macro ------------------------------------------------------------*/
00124 /* Exported functions ------------------------------------------------------- */
00125
00126 #endif /* __PLATFORM_CONFIG_H */
00127
00128 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: platform_config.h Source File

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  • Receive

USART/IrDA/Receive/platform_config.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    USART/IrDA/Receive/platform_config.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Evaluation board specific configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __PLATFORM_CONFIG_H
00024 #define __PLATFORM_CONFIG_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32_eval.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Uncomment the line corresponding to the STMicroelectronics evaluation board
00032    used to run the example */
00033 #if !defined (USE_STM32100B_EVAL) && !defined (USE_STM3210B_EVAL) &&  !defined (USE_STM32100E_EVAL) &&  !defined (USE_STM3210E_EVAL) &&  !defined (USE_STM3210C_EVAL)
00034  //#define USE_STM32100B_EVAL
00035  //#define USE_STM3210B_EVAL
00036  //#define USE_STM3210E_EVAL
00037  //#define USE_STM32100E_EVAL
00038  #define USE_STM3210C_EVAL
00039 #endif
00040
00041 /* Define the STM32F10x hardware depending on the used evaluation board */
00042 #if defined(USE_STM3210B_EVAL) || defined (USE_STM32100B_EVAL)
00043
00044   #define USARTy                   USART3
00045   #define USARTy_GPIO              GPIOC
00046   #define USARTy_CLK               RCC_APB1Periph_USART3
00047   #define USARTy_GPIO_CLK          RCC_APB2Periph_GPIOC
00048   #define USARTy_RxPin             GPIO_Pin_11
00049   #define USARTy_TxPin             GPIO_Pin_10
00050
00051 #elif defined USE_STM3210E_EVAL || defined USE_STM32100E_EVAL
00052
00053   #define USARTy                   USART3
00054   #define USARTy_GPIO              GPIOC
00055   #define USARTy_CLK               RCC_APB1Periph_USART3
00056   #define USARTy_GPIO_CLK          RCC_APB2Periph_GPIOC
00057   #define USARTy_RxPin             GPIO_Pin_11
00058   #define USARTy_TxPin             GPIO_Pin_10
00059
00060 #elif defined USE_STM3210C_EVAL
00061
00062   #define USARTy                   USART2
00063   #define USARTy_GPIO              GPIOD
00064   #define USARTy_CLK               RCC_APB1Periph_USART2
00065   #define USARTy_GPIO_CLK          RCC_APB2Periph_GPIOD
00066   #define USARTy_RxPin             GPIO_Pin_6
00067   #define USARTy_TxPin             GPIO_Pin_5
00068
00069 #endif /* USE_STM3210B_EVAL */
00070
00071 /* Exported macro ------------------------------------------------------------*/
00072 /* Exported functions ------------------------------------------------------- */
00073
00074 #endif /* __PLATFORM_CONFIG_H */
00075
00076 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: platform_config.h Source File

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  • Transmit

USART/IrDA/Transmit/platform_config.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    USART/IrDA/Transmit/platform_config.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Evaluation board specific configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __PLATFORM_CONFIG_H
00024 #define __PLATFORM_CONFIG_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32_eval.h"
00028 #ifdef USE_STM3210C_EVAL
00029  #include "stm3210c_eval_ioe.h"
00030 #endif
00031
00032 /* Exported types ------------------------------------------------------------*/
00033 /* Exported constants --------------------------------------------------------*/
00034 /* Uncomment the line corresponding to the STMicroelectronics evaluation board
00035    used to run the example */
00036 #if !defined (USE_STM32100B_EVAL) && !defined (USE_STM3210B_EVAL) &&  !defined (USE_STM3210E_EVAL) &&  !defined (USE_STM32100E_EVAL) &&  !defined (USE_STM3210C_EVAL)
00037  //#define USE_STM32100B_EVAL
00038  //#define USE_STM3210B_EVAL
00039  //#define USE_STM3210E_EVAL
00040  //#define USE_STM3210C_EVAL
00041  #define USE_STM32100E_EVAL
00042 #endif
00043
00044 /* Define the STM32F10x hardware depending on the used evaluation board */
00045 #if defined(USE_STM3210B_EVAL) || defined (USE_STM32100B_EVAL)
00046
00047   #define USARTy                   USART3
00048   #define USARTy_GPIO              GPIOC
00049   #define USARTy_CLK               RCC_APB1Periph_USART3
00050   #define USARTy_GPIO_CLK          RCC_APB2Periph_GPIOC
00051   #define USARTy_RxPin             GPIO_Pin_11
00052   #define USARTy_TxPin             GPIO_Pin_10
00053
00054 #elif defined USE_STM3210E_EVAL || defined USE_STM32100E_EVAL
00055
00056   #define USARTy                   USART3
00057   #define USARTy_GPIO              GPIOC
00058   #define USARTy_CLK               RCC_APB1Periph_USART3
00059   #define USARTy_GPIO_CLK          RCC_APB2Periph_GPIOC
00060   #define USARTy_RxPin             GPIO_Pin_11
00061   #define USARTy_TxPin             GPIO_Pin_10
00062
00063 #elif defined USE_STM3210C_EVAL
00064
00065   #define USARTy                   USART2
00066   #define USARTy_GPIO              GPIOD
00067   #define USARTy_CLK               RCC_APB1Periph_USART2
00068   #define USARTy_GPIO_CLK          RCC_APB2Periph_GPIOD
00069   #define USARTy_RxPin             GPIO_Pin_6
00070   #define USARTy_TxPin             GPIO_Pin_5
00071
00072 #endif /* USE_STM3210B_EVAL */
00073
00074 /* Exported macro ------------------------------------------------------------*/
00075 /* Exported functions ------------------------------------------------------- */
00076
00077 #endif /* __PLATFORM_CONFIG_H */
00078
00079 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: platform_config.h Source File

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  • USART
  • MultiProcessor

USART/MultiProcessor/platform_config.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    USART/MultiProcessor/platform_config.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Evaluation board specific configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __PLATFORM_CONFIG_H
00024 #define __PLATFORM_CONFIG_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32_eval.h"
00028
00029 /* Exported types ------------------------------------------------------------*/
00030 /* Exported constants --------------------------------------------------------*/
00031 /* Uncomment the line corresponding to the STMicroelectronics evaluation board
00032    used to run the example */
00033 #if !defined (USE_STM32100B_EVAL) && !defined (USE_STM3210B_EVAL) &&  !defined (USE_STM3210E_EVAL) &&  !defined (USE_STM3210C_EVAL) &&  !defined (USE_STM32100E_EVAL)
00034  //#define USE_STM32100B_EVAL
00035  //#define USE_STM3210B_EVAL
00036  //#define USE_STM3210E_EVAL
00037  //#define USE_STM32100E_EVAL
00038  #define USE_STM3210C_EVAL
00039 #endif
00040
00041 /* Define the STM32F10x hardware depending on the used evaluation board */
00042 #if defined(USE_STM3210B_EVAL) || defined (USE_STM32100B_EVAL)
00043
00044   #define USARTy                   USART1
00045   #define USARTy_GPIO              GPIOA
00046   #define USARTy_CLK               RCC_APB2Periph_USART1
00047   #define USARTy_GPIO_CLK          RCC_APB2Periph_GPIOA
00048   #define USARTy_RxPin             GPIO_Pin_10
00049   #define USARTy_TxPin             GPIO_Pin_9
00050
00051   #define USARTz                   USART2
00052   #define USARTz_GPIO              GPIOD
00053   #define USARTz_CLK               RCC_APB1Periph_USART2
00054   #define USARTz_GPIO_CLK          RCC_APB2Periph_GPIOD
00055   #define USARTz_RxPin             GPIO_Pin_6
00056   #define USARTz_TxPin             GPIO_Pin_5
00057
00058 #elif defined USE_STM3210E_EVAL || defined (USE_STM32100E_EVAL)
00059
00060   #define USARTy                   USART1
00061   #define USARTy_GPIO              GPIOA
00062   #define USARTy_CLK               RCC_APB2Periph_USART1
00063   #define USARTy_GPIO_CLK          RCC_APB2Periph_GPIOA
00064   #define USARTy_RxPin             GPIO_Pin_10
00065   #define USARTy_TxPin             GPIO_Pin_9
00066
00067   #define USARTz                   USART2
00068   #define USARTz_GPIO              GPIOA
00069   #define USARTz_CLK               RCC_APB1Periph_USART2
00070   #define USARTz_GPIO_CLK          RCC_APB2Periph_GPIOA
00071   #define USARTz_RxPin             GPIO_Pin_3
00072   #define USARTz_TxPin             GPIO_Pin_2
00073
00074 #elif defined USE_STM3210C_EVAL
00075
00076   #define USARTy                   USART2
00077   #define USARTy_GPIO              GPIOD
00078   #define USARTy_CLK               RCC_APB1Periph_USART2
00079   #define USARTy_GPIO_CLK          RCC_APB2Periph_GPIOD
00080   #define USARTy_RxPin             GPIO_Pin_6
00081   #define USARTy_TxPin             GPIO_Pin_5
00082
00083   #define USARTz                   USART3
00084   #define USARTz_GPIO              GPIOC
00085   #define USARTz_CLK               RCC_APB1Periph_USART3
00086   #define USARTz_GPIO_CLK          RCC_APB2Periph_GPIOC
00087   #define USARTz_RxPin             GPIO_Pin_11
00088   #define USARTz_TxPin             GPIO_Pin_10
00089
00090 #endif /* USE_STM3210B_EVAL */
00091
00092 /* Exported macro ------------------------------------------------------------*/
00093 /* Exported functions ------------------------------------------------------- */
00094
00095 #endif /* __PLATFORM_CONFIG_H */
00096
00097 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: platform_config.h Source File

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • USART
  • Polling

USART/Polling/platform_config.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    USART/Polling/platform_config.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Evaluation board specific configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __PLATFORM_CONFIG_H
00024 #define __PLATFORM_CONFIG_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027
00028 /* Exported types ------------------------------------------------------------*/
00029 /* Exported constants --------------------------------------------------------*/
00030 /* Uncomment the line corresponding to the STMicroelectronics evaluation board
00031    used to run the example */
00032 #if !defined (USE_STM32100B_EVAL) && !defined (USE_STM3210B_EVAL) &&  !defined (USE_STM3210E_EVAL) &&  !defined (USE_STM3210C_EVAL)&&  !defined (USE_STM32100E_EVAL)
00033  //#define USE_STM32100B_EVAL
00034  //#define USE_STM3210B_EVAL
00035  //#define USE_STM3210E_EVAL
00036  #define USE_STM3210C_EVAL
00037 #endif
00038
00039 /* Define the STM32F10x hardware depending on the used evaluation board */
00040 #if defined(USE_STM3210B_EVAL) || defined (USE_STM32100B_EVAL)
00041
00042   #define USARTy                   USART1
00043   #define USARTy_GPIO              GPIOA
00044   #define USARTy_CLK               RCC_APB2Periph_USART1
00045   #define USARTy_GPIO_CLK          RCC_APB2Periph_GPIOA
00046   #define USARTy_RxPin             GPIO_Pin_10
00047   #define USARTy_TxPin             GPIO_Pin_9
00048
00049   #define USARTz                   USART2
00050   #define USARTz_GPIO              GPIOD
00051   #define USARTz_CLK               RCC_APB1Periph_USART2
00052   #define USARTz_GPIO_CLK          RCC_APB2Periph_GPIOD
00053   #define USARTz_RxPin             GPIO_Pin_6
00054   #define USARTz_TxPin             GPIO_Pin_5
00055
00056 #elif defined USE_STM3210E_EVAL || defined (USE_STM32100E_EVAL)
00057
00058   #define USARTy                   USART1
00059   #define USARTy_GPIO              GPIOA
00060   #define USARTy_CLK               RCC_APB2Periph_USART1
00061   #define USARTy_GPIO_CLK          RCC_APB2Periph_GPIOA
00062   #define USARTy_RxPin             GPIO_Pin_10
00063   #define USARTy_TxPin             GPIO_Pin_9
00064
00065   #define USARTz                   USART2
00066   #define USARTz_GPIO              GPIOA
00067   #define USARTz_CLK               RCC_APB1Periph_USART2
00068   #define USARTz_GPIO_CLK          RCC_APB2Periph_GPIOA
00069   #define USARTz_RxPin             GPIO_Pin_3
00070   #define USARTz_TxPin             GPIO_Pin_2
00071
00072 #elif defined USE_STM3210C_EVAL
00073
00074   #define USARTy                   USART2
00075   #define USARTy_GPIO              GPIOD
00076   #define USARTy_CLK               RCC_APB1Periph_USART2
00077   #define USARTy_GPIO_CLK          RCC_APB2Periph_GPIOD
00078   #define USARTy_RxPin             GPIO_Pin_6
00079   #define USARTy_TxPin             GPIO_Pin_5
00080
00081   #define USARTz                   USART3
00082   #define USARTz_GPIO              GPIOC
00083   #define USARTz_CLK               RCC_APB1Periph_USART3
00084   #define USARTz_GPIO_CLK          RCC_APB2Periph_GPIOC
00085   #define USARTz_RxPin             GPIO_Pin_11
00086   #define USARTz_TxPin             GPIO_Pin_10
00087
00088 #endif /* USE_STM3210B_EVAL */
00089
00090 /* Exported macro ------------------------------------------------------------*/
00091 /* Exported functions ------------------------------------------------------- */
00092
00093 #endif /* __PLATFORM_CONFIG_H */
00094
00095 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: platform_config.h Source File

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • USART
  • Smartcard

USART/Smartcard/platform_config.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    USART/Smartcard/platform_config.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Evaluation board specific configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __PLATFORM_CONFIG_H
00024 #define __PLATFORM_CONFIG_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027
00028 /* Exported types ------------------------------------------------------------*/
00029 /* Exported constants --------------------------------------------------------*/
00030 /* Uncomment the line corresponding to the STMicroelectronics evaluation board
00031    used to run the example */
00032 #if !defined (USE_STM3210B_EVAL) &&  !defined (USE_STM3210E_EVAL) &&  !defined (USE_STM3210C_EVAL)
00033  //#define USE_STM3210B_EVAL
00034  //#define USE_STM3210E_EVAL
00035  #define USE_STM3210C_EVAL
00036 #endif
00037
00038 /* Define the STM32F10x hardware depending on the used evaluation board */
00039 #ifdef USE_STM3210B_EVAL
00040   /* Smartcard Inteface USART pins */
00041   #define SC_USART                 USART3
00042   #define SC_USART_GPIO            GPIOB
00043   #define SC_USART_CLK             RCC_APB1Periph_USART3
00044   #define SC_USART_GPIO_CLK        RCC_APB2Periph_GPIOB
00045   #define SC_USART_TxPin           GPIO_Pin_10
00046   #define SC_USART_ClkPin          GPIO_Pin_12
00047   #define SC_USART_IRQn            USART3_IRQn
00048   #define SC_USART_IRQHandler      USART3_IRQHandler
00049   /* Smartcard Inteface GPIO pins */
00050   #define SC_3_5V                  GPIO_Pin_11 /* GPIOD Pin 11 */
00051   #define SC_RESET                 GPIO_Pin_11 /* GPIOB Pin 11 */
00052   #define SC_CMDVCC                GPIO_Pin_7  /* GPIOE Pin 7  */
00053   #define SC_OFF                   GPIO_Pin_14 /* GPIOE Pin 14 */
00054   #define GPIO_3_5V                GPIOD
00055   #define GPIO_RESET               GPIOB
00056   #define GPIO_CMDVCC              GPIOE
00057   #define GPIO_OFF                 GPIOE
00058   #define RCC_APB2Periph_3_5V      RCC_APB2Periph_GPIOD
00059   #define RCC_APB2Periph_RESET     RCC_APB2Periph_GPIOB
00060   #define RCC_APB2Periph_CMDVCC    RCC_APB2Periph_GPIOE
00061   #define RCC_APB2Periph_OFF       RCC_APB2Periph_GPIOE
00062   #define SC_EXTI                  EXTI_Line14
00063   #define SC_PortSource            GPIO_PortSourceGPIOE
00064   #define SC_PinSource             GPIO_PinSource14
00065   #define SC_EXTI_IRQ              EXTI15_10_IRQn
00066 #elif defined USE_STM3210E_EVAL
00067   /* Smartcard Inteface USART pins */
00068   #define SC_USART                 USART3
00069   #define SC_USART_GPIO            GPIOB
00070   #define SC_USART_CLK             RCC_APB1Periph_USART3
00071   #define SC_USART_GPIO_CLK        RCC_APB2Periph_GPIOB
00072   #define SC_USART_TxPin           GPIO_Pin_10
00073   #define SC_USART_ClkPin          GPIO_Pin_12
00074   #define SC_USART_IRQn            USART3_IRQn
00075   #define SC_USART_IRQHandler      USART3_IRQHandler
00076   /* Smartcard Inteface GPIO pins */
00077   #define SC_3_5V                  GPIO_Pin_0  /* GPIOB Pin 0 */
00078   #define SC_RESET                 GPIO_Pin_11 /* GPIOB Pin 11 */
00079   #define SC_CMDVCC                GPIO_Pin_6  /* GPIOC Pin 6  */
00080   #define SC_OFF                   GPIO_Pin_7  /* GPIOC Pin 7 */
00081   #define GPIO_3_5V                GPIOB
00082   #define GPIO_RESET               GPIOB
00083   #define GPIO_CMDVCC              GPIOC
00084   #define GPIO_OFF                 GPIOC
00085   #define RCC_APB2Periph_3_5V      RCC_APB2Periph_GPIOB
00086   #define RCC_APB2Periph_RESET     RCC_APB2Periph_GPIOB
00087   #define RCC_APB2Periph_CMDVCC    RCC_APB2Periph_GPIOC
00088   #define RCC_APB2Periph_OFF       RCC_APB2Periph_GPIOC
00089   #define SC_EXTI                  EXTI_Line7
00090   #define SC_PortSource            GPIO_PortSourceGPIOC
00091   #define SC_PinSource             GPIO_PinSource7
00092   #define SC_EXTI_IRQ              EXTI9_5_IRQn
00093 #elif defined USE_STM3210C_EVAL
00094   /* Smartcard Inteface USART pins */
00095   #define SC_USART                 USART3
00096   #define SC_USART_GPIO            GPIOD
00097   #define SC_USART_CLK             RCC_APB1Periph_USART3
00098   #define SC_USART_GPIO_CLK        RCC_APB2Periph_GPIOD
00099   #define SC_USART_TxPin           GPIO_Pin_8
00100   #define SC_USART_ClkPin          GPIO_Pin_10
00101   #define SC_USART_IRQn            USART3_IRQn
00102   #define SC_USART_IRQHandler      USART3_IRQHandler
00103   /* Smartcard Inteface GPIO pins */
00104   #define SC_3_5V                  GPIO_Pin_0  /* GPIOC Pin 0 */
00105   #define SC_RESET                 GPIO_Pin_9  /* GPIOD Pin 9 */
00106   #define SC_CMDVCC                GPIO_Pin_7  /* GPIOD Pin 7  */
00107   #define SC_OFF                   GPIO_Pin_7  /* GPIOE Pin 7 */
00108   #define GPIO_3_5V                GPIOC
00109   #define GPIO_RESET               GPIOD
00110   #define GPIO_CMDVCC              GPIOD
00111   #define GPIO_OFF                 GPIOE
00112   #define RCC_APB2Periph_3_5V      RCC_APB2Periph_GPIOC
00113   #define RCC_APB2Periph_RESET     RCC_APB2Periph_GPIOD
00114   #define RCC_APB2Periph_CMDVCC    RCC_APB2Periph_GPIOD
00115   #define RCC_APB2Periph_OFF       RCC_APB2Periph_GPIOE
00116   #define SC_EXTI                  EXTI_Line7
00117   #define SC_PortSource            GPIO_PortSourceGPIOE
00118   #define SC_PinSource             GPIO_PinSource7
00119   #define SC_EXTI_IRQ              EXTI9_5_IRQn
00120 #endif /* USE_STM3210B_EVAL */
00121
00122 /* Exported macro ------------------------------------------------------------*/
00123 /* Exported functions ------------------------------------------------------- */
00124
00125 #endif /* __PLATFORM_CONFIG_H */
00126
00127 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


STM32F10x Standard Peripherals Firmware Library: platform_config.h Source File

  • File List
  • Globals
  • STM32F10x_StdPeriph_Lib_V3.5.0
  • Project
  • STM32F10x_StdPeriph_Examples
  • USART
  • Synchronous

USART/Synchronous/platform_config.h

Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    USART/Synchronous/platform_config.h
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    08-April-2011
00007   * @brief   Evaluation board specific configuration file.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021
00022 /* Define to prevent recursive inclusion -------------------------------------*/
00023 #ifndef __PLATFORM_CONFIG_H
00024 #define __PLATFORM_CONFIG_H
00025
00026 /* Includes ------------------------------------------------------------------*/
00027
00028 /* Exported types ------------------------------------------------------------*/
00029 /* Exported constants --------------------------------------------------------*/
00030 /* Uncomment the line corresponding to the STMicroelectronics evaluation board
00031    used to run the example */
00032 #if !defined (USE_STM32100B_EVAL) && !defined (USE_STM3210B_EVAL) &&  !defined (USE_STM3210E_EVAL) &&  !defined (USE_STM32100E_EVAL)
00033  //#define USE_STM32100B_EVAL
00034  //#define USE_STM3210B_EVAL
00035  //#define USE_STM32100E_EVAL
00036  #define USE_STM3210E_EVAL
00037 #endif
00038
00039 /* Define the STM32F10x hardware depending on the used evaluation board */
00040 #if defined(USE_STM3210B_EVAL) || defined (USE_STM32100B_EVAL)
00041
00042   #define USARTy                   USART1
00043   #define USARTy_GPIO              GPIOA
00044   #define USARTy_CLK               RCC_APB2Periph_USART1
00045   #define USARTy_GPIO_CLK          RCC_APB2Periph_GPIOA
00046   #define USARTy_RxPin             GPIO_Pin_10
00047   #define USARTy_TxPin             GPIO_Pin_9
00048   #define USARTy_ClkPin            GPIO_Pin_8
00049
00050   #define SPIy                     SPI1
00051   #define SPIy_GPIO                GPIOA
00052   #define SPIy_CLK                 RCC_APB2Periph_SPI1
00053   #define SPIy_GPIO_CLK            RCC_APB2Periph_GPIOA
00054   #define SPIy_SCKPin              GPIO_Pin_5
00055   #define SPIy_MISOPin             GPIO_Pin_6
00056   #define SPIy_MOSIPin             GPIO_Pin_7
00057
00058 #elif defined USE_STM3210E_EVAL || defined USE_STM32100E_EVAL
00059
00060   #define USARTy                   USART1
00061   #define USARTy_GPIO              GPIOA
00062   #define USARTy_CLK               RCC_APB2Periph_USART1
00063   #define USARTy_GPIO_CLK          RCC_APB2Periph_GPIOA
00064   #define USARTy_RxPin             GPIO_Pin_10
00065   #define USARTy_TxPin             GPIO_Pin_9
00066   #define USARTy_ClkPin            GPIO_Pin_8
00067
00068   #define SPIy                     SPI1
00069   #define SPIy_GPIO                GPIOA
00070   #define SPIy_CLK                 RCC_APB2Periph_SPI1
00071   #define SPIy_GPIO_CLK            RCC_APB2Periph_GPIOA
00072   #define SPIy_SCKPin              GPIO_Pin_5
00073   #define SPIy_MISOPin             GPIO_Pin_6
00074   #define SPIy_MOSIPin             GPIO_Pin_7
00075
00076 #endif /* USE_STM3210B_EVAL */
00077
00078 /* Exported macro ------------------------------------------------------------*/
00079 /* Exported functions ------------------------------------------------------- */
00080
00081 #endif /* __PLATFORM_CONFIG_H */
00082
00083 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/


CMSIS Changes

Changes to CMSIS version V1.20

1. Removed CMSIS Middelware packages

CMSIS Middleware is on hold from ARM side until a agreement between all CMSIS partners is found.

2. SystemFrequency renamed to SystemCoreClock

The variable name SystemCoreClock is more precise than SystemFrequency because the variable holds the clock value at which the core is running.

3. Changed startup concept

The old startup concept (calling SystemInit_ExtMemCtl from startup file and calling SystemInit from main) has the weakness that it does not work for controllers which need a already configuerd clock system to configure the external memory controller.

Changed startup concept

  • SystemInit() is called from startup file before premain.
  • SystemInit() configures the clock system and also configures an existing external memory controller.
  • SystemInit() must not use global variables.
  • SystemCoreClock is initialized with a correct predefined value.
  • Additional function void SystemCoreClockUpdate (void) is provided.
    SystemCoreClockUpdate() updates the variable SystemCoreClock and must be called whenever the core clock is changed.
    SystemCoreClockUpdate() evaluates the clock register settings and calculates the current core clock.

4. Advanced Debug Functions

ITM communication channel is only capable for OUT direction. To allow also communication for IN direction a simple concept is provided.

  • Global variable volatile int ITM_RxBuffer used for IN data.
  • Function int ITM_CheckChar (void) checks if a new character is available.
  • Function int ITM_ReceiveChar (void) retrieves the new character.

For detailed explanation see file CMSIS debug support.htm.

5. Core Register Bit Definitions

Files core_cm3.h and core_cm0.h contain now bit definitions for Core Registers. The name for the defines correspond with the Cortex-M Technical Reference Manual.

e.g. SysTick structure with bit definitions

/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick
  memory mapped structure for SysTick
  @{
 */
typedef struct
{
  __IO uint32_t CTRL;                         /*!< Offset: 0x00  SysTick Control and Status Register */
  __IO uint32_t LOAD;                         /*!< Offset: 0x04  SysTick Reload Value Register       */
  __IO uint32_t VAL;                          /*!< Offset: 0x08  SysTick Current Value Register      */
  __I  uint32_t CALIB;                        /*!< Offset: 0x0C  SysTick Calibration Register        */
} SysTick_Type;

/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk         (1ul << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */

#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk         (1ul << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */

#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk           (1ul << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */

#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk            (1ul << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */

/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */

/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFul << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */

/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk            (1ul << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */

#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk             (1ul << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */

#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFul << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
/*@}*/ /* end of group CMSIS_CM3_SysTick */

7. DoxyGen Tags

DoxyGen tags in files core_cm3.[c,h] and core_cm0.[c,h] are reworked to create proper documentation using DoxyGen.

8. Folder Structure

The folder structure is changed to differentiate the single support packages.

  • CM0
  • CM3
    • CoreSupport
    • DeviceSupport
      • Vendor
        • Device
          • Startup
            • Toolchain
            • Toolchain
            • ...
        • Device
        • ...
      • Vendor
      • ...
    • Example
      • Toolchain
        • Device
        • Device
        • ...
      • Toolchain
      • ...
  • Documentation

9. Open Points

Following points need to be clarified and solved:

  • Equivalent C and Assembler startup files.

    Is there a need for having C startup files although assembler startup files are very efficient and do not need to be changed?

  • Placing of HEAP in external RAM.

    It must be possible to place HEAP in external RAM if the device supports an external memory controller.

  • Placing of STACK /HEAP.

    STACK should always be placed at the end of internal RAM.

    If HEAP is placed in internal RAM than it should be placed after RW ZI section.

  • Removing core_cm3.c and core_cm0.c.

    On a long term the functions in core_cm3.c and core_cm0.c must be replaced with appropriate compiler intrinsics.

10. Limitations

The following limitations are not covered with the current CMSIS version:

  • No C startup files for ARM toolchain are provided.
  • No C startup files for GNU toolchain are provided.
  • No C startup files for IAR toolchain are provided.
  • No Tasking projects are provided yet.


Release Notes for STM32F10x CMSIS

Copyright 2011 STMicroelectronics

Contents

  1. STM32F10x CMSIS update History
  2. License

STM32F10x CMSIS update History

V3.5.0 / 11-March-2011

Main Changes

  • stm32f10x.h and startup_stm32f10x_hd_vl.s files: remove the FSMC interrupt definition for STM32F10x High-density Value line devices.
  • system_stm32f10x.c file provided within the CMSIS folder.

3.4.0 - 10/15/2010

  1. General
  • Add support for STM32F10x High-density Value line devices.
  2. STM32F10x CMSIS Device Peripheral Access Layer
  • STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer Header File: stm32f10x.h
    • Update to support High-density Value line devices
      • Add new define STM32F10X_HD_VL
      • RCC, AFIO, FSMC bits definition updated
    • All STM32 devices definitions are commented by default. User has to select the appropriate device before starting else an error will be signaled on compile time.
    • Add new IRQs definitons inside the IRQn_Type enumeration for STM23 High-density Value line devices.
    • "bool" type removed.
  • STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer System Files: system_stm32f10x.h and system_stm32f10x.c
    • "system_stm32f10x.c" moved to to "STM32F10x_StdPeriph_Template" directory. This file is also moved to each example directory under "STM32F10x_StdPeriph_Examples".
    • SystemInit_ExtMemCtl() function: update to support High-density Value line devices.
    • Add "VECT_TAB_SRAM" inside "system_stm32f10x.c" to select if the user want to place the Vector Table in internal SRAM. An additional define is also to specify the Vector Table offset "VECT_TAB_OFFSET".
  • STM32F10x CMSIS startup files:startup_stm32f10x_xx.s
    • Add three startup files for STM32 High-density Value line devices: startup_stm32f10x_hd_vl.s

3.3.0 - 04/16/2010

  1. General
  • Add support for STM32F10x XL-density devices.
  • Add startup files for TrueSTUDIO toolchain
  2. STM32F10x CMSIS Device Peripheral Access Layer
  • STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer Header File: stm32f10x.h
    • Update to support XL-density devices
      • Add new define STM32F10X_XL
      • Add new IRQs for TIM9..14
      • Update FLASH_TypeDef structure
      • Add new IP instances TIM9..14
      • RCC, AFIO, DBGMCU bits definition updated
    • Correct IRQs definition for MD-, LD-, MD_VL- and LD_VL-density devices (remove comma "," at the end of enum list)
  • STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer System Files: system_stm32f10x.h and system_stm32f10x.c
    • SystemInit_ExtMemCtl() function: update to support XL-density devices
    • SystemInit() function: swap the order of SetSysClock() and SystemInit_ExtMemCtl() functions.
  • STM32F10x CMSIS startup files:
    • add three startup files for STM32 XL-density devices: startup_stm32f10x_xl.s
    • startup_stm32f10x_md_vl.s for RIDE7: add USART3 IRQ Handler (was missing in previous version)
    • Add startup files for TrueSTUDIO toolchain

3.2.0 - 03/01/2010

  1. General
  • STM32F10x CMSIS files updated to CMSIS V1.30 release
  • Directory structure updated to be aligned with CMSIS V1.30
  • Add support for STM32 Low-density Value line (STM32F100x4/6) and Medium-density Value line (STM32F100x8/B) devices.
  2. CMSIS Core Peripheral Access Layer
  • Refer to CMSIS changes
  3. STM32F10x CMSIS Device Peripheral Access Layer
  • STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer Header File: stm32f10x.h
    • Update the stm32f10x.h file to support new Value line devices features: CEC peripheral, new General purpose timers TIM15, TIM16 and TIM17.
    • Peripherals Bits definitions updated to be in line with Value line devices available features.
    • HSE_Value, HSI_Value and HSEStartup_TimeOut changed to upper case: HSE_VALUE, HSI_VALUE and HSE_STARTUP_TIMEOUT. Old names are kept for legacy purposes.
  • STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer System Files: system_stm32f10x.h and system_stm32f10x.c
    • SystemFrequency variable name changed to SystemCoreClock
    • Default SystemCoreClock is changed to 24MHz when Value line devices are selected and to 72MHz on other devices.
    • All while(1) loop were removed from all clock setting functions. User has to handle the HSE startup failure.
    • Additional function void SystemCoreClockUpdate (void) is provided.
  • STM32F10x CMSIS Startup files: startup_stm32f10x_xx.s
    • Add new startup files for STM32 Low-density Value line devices: startup_stm32f10x_ld_vl.s
    • Add new startup files for STM32 Medium-density Value line devices: startup_stm32f10x_md_vl.s
    • SystemInit() function is called from startup file (startup_stm32f10x_xx.s) before to branch to application main.
      To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file
    • GNU startup file for Low density devices (startup_stm32f10x_ld.s) is updated to fix compilation errors.

License

The enclosed firmware and all the related documentation are not covered by a License Agreement, if you need such License you can contact your local STMicroelectronics office.

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

For complete documentation on STM32(CORTEX M3) 32-Bit Microcontrollers visit www.st.com/STM32


CMSIS: Cortex Microcontroller Software Interface Standard

Cortex Microcontroller Software Interface Standard

This file describes the Cortex Microcontroller Software Interface Standard (CMSIS).

Version: 1.30 - 30. October 2009

Information in this file, the accompany manuals, and software is
Copyright © ARM Ltd.
All rights reserved.

Revision History

  • Version 1.00: initial release.
  • Version 1.01: added __LDREXx, __STREXx, and __CLREX.
  • Version 1.02: added Cortex-M0.
  • Version 1.10: second review.
  • Version 1.20: third review.
  • Version 1.30 PRE-RELEASE: reworked Startup Concept, additional Debug Functionality.
  • Version 1.30 2nd PRE-RELEASE: changed folder structure, added doxyGen comments, added Bit definitions.
  • Version 1.30: updated Device Support Packages.

Contents

  1. About
  2. Coding Rules and Conventions
  3. CMSIS Files
  4. Core Peripheral Access Layer
  5. CMSIS Example

About

The Cortex Microcontroller Software Interface Standard (CMSIS) answers the challenges that are faced when software components are deployed to physical microcontroller devices based on a Cortex-M0 or Cortex-M3 processor. The CMSIS will be also expanded to future Cortex-M processor cores (the term Cortex-M is used to indicate that). The CMSIS is defined in close co-operation with various silicon and software vendors and provides a common approach to interface to peripherals, real-time operating systems, and middleware components.

ARM provides as part of the CMSIS the following software layers that are available for various compiler implementations:

  • Core Peripheral Access Layer: contains name definitions, address definitions and helper functions to access core registers and peripherals. It defines also a device independent interface for RTOS Kernels that includes debug channel definitions.

These software layers are expanded by Silicon partners with:

  • Device Peripheral Access Layer: provides definitions for all device peripherals
  • Access Functions for Peripherals (optional): provides additional helper functions for peripherals

CMSIS defines for a Cortex-M Microcontroller System:

  • A common way to access peripheral registers and a common way to define exception vectors.
  • The register names of the Core Peripherals and the names of the Core Exception Vectors.
  • An device independent interface for RTOS Kernels including a debug channel.

By using CMSIS compliant software components, the user can easier re-use template code. CMSIS is intended to enable the combination of software components from multiple middleware vendors.

Coding Rules and Conventions

The following section describes the coding rules and conventions used in the CMSIS implementation. It contains also information about data types and version number information.

Essentials

  • The CMSIS C code conforms to MISRA 2004 rules. In case of MISRA violations, there are disable and enable sequences for PC-LINT inserted.
  • ANSI standard data types defined in the ANSI C header file <stdint.h> are used.
  • #define constants that include expressions must be enclosed by parenthesis.
  • Variables and parameters have a complete data type.
  • All functions in the Core Peripheral Access Layer are re-entrant.
  • The Core Peripheral Access Layer has no blocking code (which means that wait/query loops are done at other software layers).
  • For each exception/interrupt there is definition for:
    • an exception/interrupt handler with the postfix _Handler (for exceptions) or _IRQHandler (for interrupts).
    • a default exception/interrupt handler (weak definition) that contains an endless loop.
    • a #define of the interrupt number with the postfix _IRQn.

Recommendations

The CMSIS recommends the following conventions for identifiers.

  • CAPITAL names to identify Core Registers, Peripheral Registers, and CPU Instructions.
  • CamelCase names to identify peripherals access functions and interrupts.
  • PERIPHERAL_ prefix to identify functions that belong to specify peripherals.
  • Doxygen comments for all functions are included as described under Function Comments below.
Comments
  • Comments use the ANSI C90 style (/* comment */) or C++ style (// comment). It is assumed that the programming tools support today consistently the C++ comment style.
  • Function Comments provide for each function the following information:
    • one-line brief function overview.
    • detailed parameter explanation.
    • detailed information about return values.
    • detailed description of the actual function.

    Doxygen Example:

    /**
 * @brief  Enable Interrupt in NVIC Interrupt Controller
 * @param  IRQn  interrupt number that specifies the interrupt
 * @return none.
 * Enable the specified interrupt in the NVIC Interrupt Controller.
 * Other settings of the interrupt such as priority are not affected.
 */

Data Types and IO Type Qualifiers

The Cortex-M HAL uses the standard types from the standard ANSI C header file <stdint.h>. IO Type Qualifiers are used to specify the access to peripheral variables. IO Type Qualifiers are indented to be used for automatic generation of debug information of peripheral registers.

IO Type Qualifier | #define | Description
__I | volatile const | Read access only
__O | volatile | Write access only
__IO | volatile | Read and write access

CMSIS Version Number

File core_cm3.h contains the version number of the CMSIS with the following define:

#define __CM3_CMSIS_VERSION_MAIN  (0x01)      /* [31:16] main version       */
#define __CM3_CMSIS_VERSION_SUB   (0x30)      /* [15:0]  sub version        */
#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB)

File core_cm0.h contains the version number of the CMSIS with the following define:

#define __CM0_CMSIS_VERSION_MAIN  (0x01)      /* [31:16] main version       */
#define __CM0_CMSIS_VERSION_SUB   (0x30)      /* [15:0]  sub version        */
#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16) | __CM0_CMSIS_VERSION_SUB)

CMSIS Cortex Core

File core_cm3.h contains the type of the CMSIS Cortex-M with the following define:

#define __CORTEX_M                (0x03)

File core_cm0.h contains the type of the CMSIS Cortex-M with the following define:

#define __CORTEX_M                (0x00)

CMSIS Files

This section describes the Files provided in context with the CMSIS to access the Cortex-M hardware and peripherals.

File | Provider | Description
device.h | Device specific (provided by silicon partner) | Defines the peripherals for the actual device. The file may use several other include files to define the peripherals of the actual device.
core_cm0.h | ARM (for RealView ARMCC, IAR, and GNU GCC) | Defines the core peripherals for the Cortex-M0 CPU and core peripherals.
core_cm3.h | ARM (for RealView ARMCC, IAR, and GNU GCC) | Defines the core peripherals for the Cortex-M3 CPU and core peripherals.
core_cm0.c | ARM (for RealView ARMCC, IAR, and GNU GCC) | Provides helper functions that access core registers.
core_cm3.c | ARM (for RealView ARMCC, IAR, and GNU GCC) | Provides helper functions that access core registers.
startup_device | ARM (adapted by compiler partner / silicon partner) | Provides the Cortex-M startup code and the complete (device specific) Interrupt Vector Table
system_device | ARM (adapted by silicon partner) | Provides a device specific configuration file for the device. It configures the device initializes typically the oscillator (PLL) that is part of the microcontroller device

device.h

The file device.h is provided by the silicon vendor and is the central include file that the application programmer is using in the C source code. This file contains:

  • Interrupt Number Definition: provides interrupt numbers (IRQn) for all core and device specific exceptions and interrupts.

  • Configuration for core_cm0.h / core_cm3.h: reflects the actual configuration of the Cortex-M processor that is part of the actual device. As such the file core_cm0.h / core_cm3.h is included that implements access to processor registers and core peripherals.

  • Device Peripheral Access Layer: provides definitions for all device peripherals. It contains all data structures and the address mapping for the device specific peripherals.

  • Access Functions for Peripherals (optional): provides additional helper functions for peripherals that are useful for programming of these peripherals. Access Functions may be provided as inline functions or can be extern references to a device specific library provided by the silicon vendor.

Interrupt Number Definition

To access the device specific interrupts the device.h file defines IRQn numbers for the complete device using a enum typedef as shown below:

typedef enum IRQn
{
/******  Cortex-M3 Processor Exceptions/Interrupt Numbers ************************************************/
  NonMaskableInt_IRQn             = -14,      /*!< 2 Non Maskable Interrupt                              */
  HardFault_IRQn                  = -13,      /*!< 3 Cortex-M3 Hard Fault Interrupt                      */
  MemoryManagement_IRQn           = -12,      /*!< 4 Cortex-M3 Memory Management Interrupt               */
  BusFault_IRQn                   = -11,      /*!< 5 Cortex-M3 Bus Fault Interrupt                       */
  UsageFault_IRQn                 = -10,      /*!< 6 Cortex-M3 Usage Fault Interrupt                     */
  SVCall_IRQn                     = -5,       /*!< 11 Cortex-M3 SV Call Interrupt                        */
  DebugMonitor_IRQn               = -4,       /*!< 12 Cortex-M3 Debug Monitor Interrupt                  */
  PendSV_IRQn                     = -2,       /*!< 14 Cortex-M3 Pend SV Interrupt                        */
  SysTick_IRQn                    = -1,       /*!< 15 Cortex-M3 System Tick Interrupt                    */
/******  STM32 specific Interrupt Numbers ****************************************************************/
  WWDG_STM_IRQn                   = 0,        /*!< Window WatchDog Interrupt                             */
  PVD_STM_IRQn                    = 1,        /*!< PVD through EXTI Line detection Interrupt             */
  :
  :
  } IRQn_Type;

Configuration for core_cm0.h / core_cm3.h

The Cortex-M core configuration options which are defined for each device implementation. Some configuration options are reflected in the CMSIS layer using the #define settings described below.

To access core peripherals file device.h includes file core_cm0.h / core_cm3.h. Several features in core_cm0.h / core_cm3.h are configured by the following defines that must be defined before #include <core_cm0.h> / #include <core_cm3.h> preprocessor command.

#define | File | Value | Description
__NVIC_PRIO_BITS | core_cm0.h | (2) | Number of priority bits implemented in the NVIC (device specific)
__NVIC_PRIO_BITS | core_cm3.h | (2 ... 8) | Number of priority bits implemented in the NVIC (device specific)
__MPU_PRESENT | core_cm0.h, core_cm3.h | (0, 1) | Defines if an MPU is present or not
__Vendor_SysTickConfig | core_cm0.h, core_cm3.h | (1) | When this define is setup to 1, the SysTickConfig function in core_cm3.h is excluded. In this case the device.h file must contain a vendor specific implementation of this function.

Device Peripheral Access Layer

Each peripheral uses a prefix which consists of <device abbreviation>_ and <peripheral name>_ to identify peripheral registers that access this specific peripheral. The intention of this is to avoid name collisions caused due to short names. If more than one peripheral of the same type exists, identifiers have a postfix (digit or letter). For example:

  • <device abbreviation>_UART_Type: defines the generic register layout for all UART channels in a device.
    typedef struct
{
  union {
  __I  uint8_t  RBR;                     /*!< Offset: 0x000   Receiver Buffer Register    */
  __O  uint8_t  THR;                     /*!< Offset: 0x000   Transmit Holding Register   */
  __IO uint8_t  DLL;                     /*!< Offset: 0x000   Divisor Latch LSB           */
       uint32_t RESERVED0;
  };
  union {
  __IO uint8_t  DLM;                     /*!< Offset: 0x004   Divisor Latch MSB           */
  __IO uint32_t IER;                     /*!< Offset: 0x004   Interrupt Enable Register   */
  };
  union {
  __I  uint32_t IIR;                     /*!< Offset: 0x008   Interrupt ID Register       */
  __O  uint8_t  FCR;                     /*!< Offset: 0x008   FIFO Control Register       */
  };
  __IO uint8_t  LCR;                     /*!< Offset: 0x00C   Line Control Register       */
       uint8_t  RESERVED1[7];
  __I  uint8_t  LSR;                     /*!< Offset: 0x014   Line Status Register        */
       uint8_t  RESERVED2[7];
  __IO uint8_t  SCR;                     /*!< Offset: 0x01C   Scratch Pad Register        */
       uint8_t  RESERVED3[3];
  __IO uint32_t ACR;                     /*!< Offset: 0x020   Autobaud Control Register   */
  __IO uint8_t  ICR;                     /*!< Offset: 0x024   IrDA Control Register       */
       uint8_t  RESERVED4[3];
  __IO uint8_t  FDR;                     /*!< Offset: 0x028   Fractional Divider Register */
       uint8_t  RESERVED5[7];
  __IO uint8_t  TER;                     /*!< Offset: 0x030   Transmit Enable Register    */
       uint8_t  RESERVED6[39];
  __I  uint8_t  FIFOLVL;                 /*!< Offset: 0x058   FIFO Level Register         */
} LPC_UART_TypeDef;
  • <device abbreviation>_UART1: is a pointer to a register structure that refers to a specific UART. For example UART1->DR is the data register of UART1.
    #define LPC_UART2             ((LPC_UART_TypeDef      *) LPC_UART2_BASE    )
#define LPC_UART3             ((LPC_UART_TypeDef      *) LPC_UART3_BASE    )
Minimal Requiements

To access the peripheral registers and related function in a device the files device.h and core_cm0.h / core_cm3.h defines as a minimum:

  • The Register Layout Typedef for each peripheral that defines all register names. Names that start with RESERVE are used to introduce space into the structure to adjust the addresses of the peripheral registers. For example:
    typedef struct {
  __IO uint32_t CTRL;      /* SysTick Control and Status Register */
  __IO uint32_t LOAD;      /* SysTick Reload Value Register       */
  __IO uint32_t VAL;       /* SysTick Current Value Register      */
  __I  uint32_t CALIB;     /* SysTick Calibration Register        */
  } SysTick_Type;
  • Base Address for each peripheral (in case of multiple peripherals that use the same register layout typedef multiple base addresses are defined). For example:
    #define SysTick_BASE (SCS_BASE + 0x0010)            /* SysTick Base Address */
  • Access Definition for each peripheral (in case of multiple peripherals that use the same register layout typedef multiple access definitions exist, i.e. LPC_UART0, LPC_UART2). For Example:
    #define SysTick ((SysTick_Type *) SysTick_BASE)     /* SysTick access definition */

These definitions allow to access the peripheral registers from user code with simple assignments like:

SysTick->CTRL = 0;
Optional Features

In addition the device.h file may define:

  • #define constants that simplify access to the peripheral registers. These constant define bit-positions or other specific patterns are that required for the programming of the peripheral registers. The identifiers used start with <device abbreviation>_ and <peripheral name>_. It is recommended to use CAPITAL letters for such #define constants.
  • Functions that perform more complex functions with the peripheral (i.e. status query before a sending register is accessed). Again these function start with <device abbreviation>_ and <peripheral name>_.

core_cm0.h and core_cm0.c

File core_cm0.h describes the data structures for the Cortex-M0 core peripherals and does the address mapping of this structures. It also provides basic access to the Cortex-M0 core registers and core peripherals with efficient functions (defined as static inline).

File core_cm0.c defines several helper functions that access processor registers.

Together these files implement the Core Peripheral Access Layer for a Cortex-M0.

core_cm3.h and core_cm3.c

File core_cm3.h describes the data structures for the Cortex-M3 core peripherals and does the address mapping of this structures. It also provides basic access to the Cortex-M3 core registers and core peripherals with efficient functions (defined as static inline).

File core_cm3.c defines several helper functions that access processor registers.

Together these files implement the Core Peripheral Access Layer for a Cortex-M3.

startup_device

A template file for startup_device is provided by ARM for each supported compiler. It is adapted by the silicon vendor to include interrupt vectors for all device specific interrupt handlers. Each interrupt handler is defined as weak function to an dummy handler. Therefore the interrupt handler can be directly used in application software without any requirements to adapt the startup_device file.

The following exception names are fixed and define the start of the vector table for a Cortex-M0:

__Vectors       DCD     __initial_sp              ; Top of Stack
                DCD     Reset_Handler             ; Reset Handler
                DCD     NMI_Handler               ; NMI Handler
                DCD     HardFault_Handler         ; Hard Fault Handler
                DCD     0                         ; Reserved
                DCD     0                         ; Reserved
                DCD     0                         ; Reserved
                DCD     0                         ; Reserved
                DCD     0                         ; Reserved
                DCD     0                         ; Reserved
                DCD     0                         ; Reserved
                DCD     SVC_Handler               ; SVCall Handler
                DCD     0                         ; Reserved
                DCD     0                         ; Reserved
                DCD     PendSV_Handler            ; PendSV Handler
                DCD     SysTick_Handler           ; SysTick Handler

The following exception names are fixed and define the start of the vector table for a Cortex-M3:

__Vectors       DCD     __initial_sp              ; Top of Stack
                DCD     Reset_Handler             ; Reset Handler
                DCD     NMI_Handler               ; NMI Handler
                DCD     HardFault_Handler         ; Hard Fault Handler
                DCD     MemManage_Handler         ; MPU Fault Handler
                DCD     BusFault_Handler          ; Bus Fault Handler
                DCD     UsageFault_Handler        ; Usage Fault Handler
                DCD     0                         ; Reserved
                DCD     0                         ; Reserved
                DCD     0                         ; Reserved
                DCD     0                         ; Reserved
                DCD     SVC_Handler               ; SVCall Handler
                DCD     DebugMon_Handler          ; Debug Monitor Handler
                DCD     0                         ; Reserved
                DCD     PendSV_Handler            ; PendSV Handler
                DCD     SysTick_Handler           ; SysTick Handler

In the following examples for device specific interrupts are shown:

; External Interrupts
                DCD     WWDG_IRQHandler           ; Window Watchdog
                DCD     PVD_IRQHandler            ; PVD through EXTI Line detect
                DCD     TAMPER_IRQHandler         ; Tamper

Device specific interrupts must have a dummy function that can be overwritten in user code. Below is an example for this dummy function.

Default_Handler PROC
                EXPORT WWDG_IRQHandler   [WEAK]
                EXPORT PVD_IRQHandler    [WEAK]
                EXPORT TAMPER_IRQHandler [WEAK]
                :
                :
                WWDG_IRQHandler
                PVD_IRQHandler
                TAMPER_IRQHandler
                :
                :
                B .
                ENDP

The user application may simply define an interrupt handler function by using the handler name as shown below.

void WWDG_IRQHandler(void)
{
  :
  :
}

system_device.c

A template file for system_device.c is provided by ARM but adapted by the silicon vendor to match their actual device. As a minimum requirement this file must provide a device specific system configuration function and a global variable that contains the system frequency. It configures the device and initializes typically the oscillator (PLL) that is part of the microcontroller device.

The file system_device.c must provide as a minimum requirement the SystemInit function as shown below.

Function Definition | Description
void SystemInit (void) | Setup the microcontroller system. Typically this function configures the oscillator (PLL) that is part of the microcontroller device. For systems with variable clock speed it also updates the variable SystemCoreClock. SystemInit is called from startup_device file.
void SystemCoreClockUpdate (void) | Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates the current core clock.

Also part of the file system_device.c is the variable SystemCoreClock which contains the current CPU clock speed shown below.

Variable Definition | Description
uint32_t SystemCoreClock | Contains the system core clock (which is the system clock frequency supplied to the SysTick timer and the processor core clock). This variable can be used by the user application to setup the SysTick timer or configure other parameters. It may also be used by debugger to query the frequency of the debug timer or configure the trace clock speed. SystemCoreClock is initialized with a correct predefined value. The compiler must be configured to avoid the removal of this variable in case that the application program is not using it. It is important for debug systems that the variable is physically present in memory so that it can be examined to configure the debugger.

Note

  • The above definitions are the minimum requirements for the file system_device.c. This file may export more functions or variables that provide a more flexible configuration of the microcontroller system.

Core Peripheral Access Layer

Cortex-M Core Register Access

The following functions are defined in core_cm0.h / core_cm3.h and provide access to Cortex-M core registers.

Function Definition | Core | Core Register | Description
void __enable_irq (void) | M0, M3 | PRIMASK = 0 | Global Interrupt enable (using the instruction CPSIE i)
void __disable_irq (void) | M0, M3 | PRIMASK = 1 | Global Interrupt disable (using the instruction CPSID i)
void __set_PRIMASK (uint32_t value) | M0, M3 | PRIMASK = value | Assign value to Priority Mask Register (using the instruction MSR)
uint32_t __get_PRIMASK (void) | M0, M3 | return PRIMASK | Return Priority Mask Register (using the instruction MRS)
void __enable_fault_irq (void) | M3 | FAULTMASK = 0 | Global Fault exception and Interrupt enable (using the instruction CPSIE f)
void __disable_fault_irq (void) | M3 | FAULTMASK = 1 | Global Fault exception and Interrupt disable (using the instruction CPSID f)
void __set_FAULTMASK (uint32_t value) | M3 | FAULTMASK = value | Assign value to Fault Mask Register (using the instruction MSR)
uint32_t __get_FAULTMASK (void) | M3 | return FAULTMASK | Return Fault Mask Register (using the instruction MRS)
void __set_BASEPRI (uint32_t value) | M3 | BASEPRI = value | Set Base Priority (using the instruction MSR)
uiuint32_t __get_BASEPRI (void) | M3 | return BASEPRI | Return Base Priority (using the instruction MRS)
void __set_CONTROL (uint32_t value) | M0, M3 | CONTROL = value | Set CONTROL register value (using the instruction MSR)
uint32_t __get_CONTROL (void) | M0, M3 | return CONTROL | Return Control Register Value (using the instruction MRS)
void __set_PSP (uint32_t TopOfProcStack) | M0, M3 | PSP = TopOfProcStack | Set Process Stack Pointer value (using the instruction MSR)
uint32_t __get_PSP (void) | M0, M3 | return PSP | Return Process Stack Pointer (using the instruction MRS)
void __set_MSP (uint32_t TopOfMainStack) | M0, M3 | MSP = TopOfMainStack | Set Main Stack Pointer (using the instruction MSR)
uint32_t __get_MSP (void) | M0, M3 | return MSP | Return Main Stack Pointer (using the instruction MRS)

Cortex-M Instruction Access

The following functions are defined in core_cm0.h / core_cm3.hand generate specific Cortex-M instructions. The functions are implemented in the file core_cm0.c / core_cm3.c.

Name | Core | Generated CPU Instruction | Description
void __NOP (void) | M0, M3 | NOP | No Operation
void __WFI (void) | M0, M3 | WFI | Wait for Interrupt
void __WFE (void) | M0, M3 | WFE | Wait for Event
void __SEV (void) | M0, M3 | SEV | Set Event
void __ISB (void) | M0, M3 | ISB | Instruction Synchronization Barrier
void __DSB (void) | M0, M3 | DSB | Data Synchronization Barrier
void __DMB (void) | M0, M3 | DMB | Data Memory Barrier
uint32_t __REV (uint32_t value) | M0, M3 | REV | Reverse byte order in integer value.
uint32_t __REV16 (uint16_t value) | M0, M3 | REV16 | Reverse byte order in unsigned short value.
sint32_t __REVSH (sint16_t value) | M0, M3 | REVSH | Reverse byte order in signed short value with sign extension to integer.
uint32_t __RBIT (uint32_t value) | M3 | RBIT | Reverse bit order of value
uint8_t __LDREXB (uint8_t *addr) | M3 | LDREXB | Load exclusive byte
uint16_t __LDREXH (uint16_t *addr) | M3 | LDREXH | Load exclusive half-word
uint32_t __LDREXW (uint32_t *addr) | M3 | LDREXW | Load exclusive word
uint32_t __STREXB (uint8_t value, uint8_t *addr) | M3 | STREXB | Store exclusive byte
uint32_t __STREXB (uint16_t value, uint16_t *addr) | M3 | STREXH | Store exclusive half-word
uint32_t __STREXB (uint32_t value, uint32_t *addr) | M3 | STREXW | Store exclusive word
void __CLREX (void) | M3 | CLREX | Remove the exclusive lock created by __LDREXB, __LDREXH, or __LDREXW

NVIC Access Functions

The CMSIS provides access to the NVIC via the register interface structure and several helper functions that simplify the setup of the NVIC. The CMSIS HAL uses IRQ numbers (IRQn) to identify the interrupts. The first device interrupt has the IRQn value 0. Therefore negative IRQn values are used for processor core exceptions.

For the IRQn values of core exceptions the file device.h provides the following enum names.

Core Exception enum Value | Core | IRQn | Description
NonMaskableInt_IRQn | M0, M3 | -14 | Cortex-M Non Maskable Interrupt
HardFault_IRQn | M0, M3 | -13 | Cortex-M Hard Fault Interrupt
MemoryManagement_IRQn | M3 | -12 | Cortex-M Memory Management Interrupt
BusFault_IRQn | M3 | -11 | Cortex-M Bus Fault Interrupt
UsageFault_IRQn | M3 | -10 | Cortex-M Usage Fault Interrupt
SVCall_IRQn | M0, M3 | -5 | Cortex-M SV Call Interrupt
DebugMonitor_IRQn | M3 | -4 | Cortex-M Debug Monitor Interrupt
PendSV_IRQn | M0, M3 | -2 | Cortex-M Pend SV Interrupt
SysTick_IRQn | M0, M3 | -1 | Cortex-M System Tick Interrupt

The following functions simplify the setup of the NVIC. The functions are defined as static inline.

Name | Core | Parameter | Description
void NVIC_SetPriorityGrouping (uint32_t PriorityGroup) | M3 | Priority Grouping Value | Set the Priority Grouping (Groups . Subgroups)
uint32_t NVIC_GetPriorityGrouping (void) | M3 | (void) | Get the Priority Grouping (Groups . Subgroups)
void NVIC_EnableIRQ (IRQn_Type IRQn) | M0, M3 | IRQ Number | Enable IRQn
void NVIC_DisableIRQ (IRQn_Type IRQn) | M0, M3 | IRQ Number | Disable IRQn
uint32_t NVIC_GetPendingIRQ (IRQn_Type IRQn) | M0, M3 | IRQ Number | Return 1 if IRQn is pending else 0
void NVIC_SetPendingIRQ (IRQn_Type IRQn) | M0, M3 | IRQ Number | Set IRQn Pending
void NVIC_ClearPendingIRQ (IRQn_Type IRQn) | M0, M3 | IRQ Number | Clear IRQn Pending Status
uint32_t NVIC_GetActive (IRQn_Type IRQn) | M3 | IRQ Number | Return 1 if IRQn is active else 0
void NVIC_SetPriority (IRQn_Type IRQn, uint32_t priority) | M0, M3 | IRQ Number, Priority | Set Priority for IRQn (not threadsafe for Cortex-M0)
uint32_t NVIC_GetPriority (IRQn_Type IRQn) | M0, M3 | IRQ Number | Get Priority for IRQn
uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) | M3 | IRQ Number, Priority Group, Preemptive Priority, Sub Priority | Encode priority for given group, preemptive and sub priority
NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) | M3 | IRQ Number, Priority, pointer to Priority Group, pointer to Preemptive Priority, pointer to Sub Priority | Deccode given priority to group, preemptive and sub priority
void NVIC_SystemReset (void) | M0, M3 | (void) | Resets the System

Note

  • The processor exceptions have negative enum values. Device specific interrupts have positive enum values and start with 0. The values are defined in device.h file.

  • The values for PreemptPriority and SubPriority used in functions NVIC_EncodePriority and NVIC_DecodePriority depend on the available __NVIC_PRIO_BITS implemented in the NVIC.

SysTick Configuration Function

The following function is used to configure the SysTick timer and start the SysTick interrupt.

Name | Parameter | Description
uint32_t SysTickConfig (uint32_t ticks) | ticks is SysTick counter reload value | Setup the SysTick timer and enable the SysTick interrupt. After this call the SysTick timer creates interrupts with the specified time interval. Return: 0 when successful, 1 on failure.

Cortex-M3 ITM Debug Access

The Cortex-M3 incorporates the Instrumented Trace Macrocell (ITM) that provides together with the Serial Viewer Output trace capabilities for the microcontroller system. The ITM has 32 communication channels; two ITM communication channels are used by CMSIS to output the following information:

  • ITM Channel 0: implements the ITM_SendChar function which can be used for printf-style output via the debug interface.
  • ITM Channel 31: is reserved for the RTOS kernel and can be used for kernel awareness debugging.

Note

  • The ITM channel 31 is selected for the RTOS kernel since some kernels may use the Privileged level for program execution. ITM channels have 4 groups with 8 channels each, whereby each group can be configured for access rights in the Unprivileged level. The ITM channel 0 may be therefore enabled for the user task whereas ITM channel 31 may be accessible only in Privileged level from the RTOS kernel itself.

The prototype of the ITM_SendChar routine is shown in the table below.

Name | Parameter | Description
void uint32_t ITM_SendChar(uint32_t chr) | character to output | The function outputs a character via the ITM channel 0. The function returns when no debugger is connected that has booked the output. It is blocking when a debugger is connected, but the previous character send is not transmitted. Return: the input character 'chr'.

Example for the usage of the ITM Channel 31 for RTOS Kernels:

  // check if debugger connected and ITM channel enabled for tracing
  if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA) &&
  (ITM->TCR & ITM_TCR_ITMENA) &&
  (ITM->TER & (1UL << 31))) {
    // transmit trace data
    while (ITM->PORT31_U32 == 0);
    ITM->PORT[31].u8 = task_id;      // id of next task
    while (ITM->PORT[31].u32 == 0);
    ITM->PORT[31].u32 = task_status; // status information
  }

Cortex-M3 additional Debug Access

CMSIS provides additional debug functions to enlarge the Cortex-M3 Debug Access. Data can be transmitted via a certain global buffer variable towards the target system.

The buffer variable and the prototypes of the additional functions are shown in the table below.

Name | Parameter | Description
extern volatile int ITM_RxBuffer |  | Buffer to transmit data towards debug system. Value 0x5AA55AA5 indicates that buffer is empty.
int ITM_ReceiveChar (void) | none | The nonblocking functions returns the character stored in ITM_RxBuffer. Return: -1 indicates that no character was received.
int ITM_CheckChar (void) | none | The function checks if a character is available in ITM_RxBuffer. Return: 1 indicates that a character is available, 0 indicates that no character is available.

CMSIS Example

The following section shows a typical example for using the CMSIS layer in user applications. The example is based on a STM32F10x Device.

#include "stm32f10x.h"

volatile uint32_t msTicks;                       /* timeTicks counter */

void SysTick_Handler(void) {
  msTicks++;                                     /* increment timeTicks counter */
}

__INLINE static void Delay (uint32_t dlyTicks) {
  uint32_t curTicks = msTicks;

  while ((msTicks - curTicks) < dlyTicks);
}

__INLINE static void LED_Config(void) {
  ;                                              /* Configure the LEDs */
}

__INLINE static void LED_On (uint32_t led) {
  ;                                              /* Turn On  LED */
}

__INLINE static void LED_Off (uint32_t led) {
  ;                                              /* Turn Off LED */
}

int main (void) {
  if (SysTick_Config (SystemCoreClock / 1000)) { /* Setup SysTick for 1 msec interrupts */
    ;                                            /* Handle Error */
    while (1);
  }

  LED_Config();                                  /* configure the LEDs */

  while(1) {
    LED_On (0x100);                              /* Turn  on the LED   */
    Delay (100);                                 /* delay  100 Msec    */
    LED_Off (0x100);                             /* Turn off the LED   */
    Delay (100);                                 /* delay  100 Msec    */
  }
}


Release Notes for STM32F10x Standard Peripherals Library Drivers

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Release Notes for STM32F10x Standard Peripherals Library Drivers (StdPeriph_Driver)

Copyright 2011 STMicroelectronics

Contents

  1. STM32F10x Standard Peripherals Library Drivers update History
  2. License

STM32F10x Standard Peripherals Library Drivers update History

V3.5.0 / 11-March-2011

Main Changes

  • stm32f10x_can.h/.c files:
    • Add 5 new functions
      • 3 new functions controlling the counter errors: CAN_GetLastErrorCode(), CAN_GetReceiveErrorCounter() and CAN_GetLSBTransmitErrorCounter().
      • 1 new function to select the CAN operating mode: CAN_OperatingModeRequest().
      • 1 new function to support CAN TT mode: CAN_TTComModeCmd().
    • CAN_TransmitStatus() function updated to support all CAN transmit intermediate states
  • stm32f10x_i2c.h/.c files:
    • Add 1 new function:
      • I2C_NACKPositionConfig(): This function configures the same bit (POS) as I2C_PECPositionConfig() but is intended to be used in I2C mode while I2C_PECPositionConfig() is intended to used in SMBUS mode.
  • stm32f10x_tim.h/.c files:
    • Change the TIM_DMABurstLength_xBytes definitions to TIM_DMABurstLength_xTansfers

3.4.0 - 10/15/2010

  1. General
  • Add support for STM32F10x High-density value line devices.
  2. STM32F10x_StdPeriph_Driver
  • stm32f10x_bkp.h/.c
    • Delete BKP registers definition from stm32f10x_bkp.c and use defines within stm32f10x.h file.
  • stm32f10x_can.h/.c
    • Delete CAN registers definition from stm32f10x_can.c and use defines within stm32f10x.h file.
    • Update the wording of some defines and Asserts macro.
    • CAN_GetFlagStatus() and CAN_ClearFlag() functions: updated to support new flags (were not supported in previous version). These flags are: CAN_FLAG_RQCP0, CAN_FLAG_RQCP1, CAN_FLAG_RQCP2, CAN_FLAG_FMP1, CAN_FLAG_FF1, CAN_FLAG_FOV1, CAN_FLAG_FMP0, CAN_FLAG_FF0, CAN_FLAG_FOV0, CAN_FLAG_WKU, CAN_FLAG_SLAK and CAN_FLAG_LEC.
    • CAN_GetITStatus() function: add a check of the interrupt enable bit before getting the status of corresponding interrupt pending bit.
    • CAN_ClearITPendingBit() function: correct the procedure to clear the interrupt pending bit.
  • stm32f10x_crc.h/.c
    • Delete CRC registers definition from stm32f10x_crc.c and use defines within stm32f10x.h file.
  • stm32f10x_dac.h/.c
    • Delete DAC registers definition from stm32f10x_dac.c and use defines within stm32f10x.h file.
  • stm32f10x_dbgmcu.h/.c
    • Delete DBGMCU registers definition from stm32f10x_dbgmcu.c and use defines within stm32f10x.h file.
  • stm32f10x_dma.h/.c
    • Delete DMA registers definition from stm32f10x_dma.c and use defines within stm32f10x.h file.
    • Add new function "void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber);"
  • stm32f10x_flash.h/.c
    • FLASH functions (Erase and Program) updated to always clear the "PG", "MER" and "PER" bits even in case of TimeOut Error.
  • stm32f10x_fsmc.h/.c
    • Add new member "FSMC_AsynchronousWait" in "FSMC_NORSRAMInitTypeDef" structure.
  • stm32f10x_gpio.h/.c
    • GPIO_PinRemapConfig() function: add new values for GPIO_Remap parameter, to support new remap for TIM6, TIM7 and DAC DMA requests, TIM12 and DAC Triggers / DMA2_Channel5 Interrupt mapping.
  • stm32f10x_pwr.h/.c
    • Delete PWR registers definition from stm32f10x_pwr.c and use defines within stm32f10x.h and core_cm3.h files.
  • stm32f10x_rtc.h/.c
    • Delete RTC registers definition from stm32f10x_rtc.c and use defines within stm32f10x.h file.
  • stm32f10x_spi.h/.c
    • Add new definition for I2S Audio Clock frequencies "I2S_AudioFreq_192k".
  • stm32f10x_tim.h/.c
    • Add new definition for TIM Input Capture Polarity "TIM_ICPolarity_BothEdge".

3.3.0 - 04/16/2010

  1. General
  • Add support for STM32F10x XL-density devices.
  • I2C driver: events description and management enhancement.
  2. STM32F10x_StdPeriph_Driver
  • stm32f10x_dbgmcu.h/.c
    • DBGMCU_Config() function: add new values DBGMCU_TIMx_STOP (x: 9..14) for DBGMCU_Periph parameter.
  • stm32f10x_flash.h/.c: updated to support Bank2 of XL-density devices (up to 1MByte of Flash memory). For more details, refer to the description provided within stm32f10x_flash.c file.
  • stm32f10x_gpio.h/.c
    • GPIO_PinRemapConfig() function: add new values for GPIO_Remap parameter, to support new remap for FSMC_NADV pin and TIM9..11,13,14.
  • stm32f10x_i2c.h/.c: I2C events description and management enhancement.
    • I2C_CheckEvent() function: updated to check whether the last event contains the I2C_EVENT (instead of check whether the last event is equal to I2C_EVENT)
    • Add detailed description of I2C events and how to manage them using the functions provided by this driver. For more information, refer to stm32f10x_i2c.h and stm32f10x_i2c.c files.
  • stm32f10x_rcc.h/.c: updated to support TIM9..TIM14 APB clock and reset configuration
  • stm32f10x_tim.h/.c: updated to support new Timers TIM9..TIM14.
  • stm32f10x_sdio.h:
    • SDIO_SetSDIOReadWaitMode() function: correct values of SDIO_ReadWaitMode parameter
      change
      #define SDIO_ReadWaitMode_CLK ((uint32_t)0x00000000)
      #define SDIO_ReadWaitMode_DATA2 ((uint32_t)0x00000001)
      by
      #define SDIO_ReadWaitMode_CLK ((uint32_t)0x00000001)
      #define SDIO_ReadWaitMode_DATA2 ((uint32_t)0x00000000)

3.2.0 - 03/01/2010

  1. General
  • Add support for STM32 Low-density Value line (STM32F100x4/6) and Medium-density Value line (STM32F100x8/B) devices.
  • Almost peripherals drivers were updated to support Value line devices features
  • Drivers limitations fix and enhancements.
  2. STM32F10x_StdPeriph_Driver
  • Add new firmware driver for CEC peripheral: stm32f10x_cec.h and stm32f10x_cec.c
  • Timers drivers stm32f10x_tim.h/.c: add support for new General Purpose Timers: TIM15, TIM16 and TIM17.
  • RCC driver: add support for new Value peripherals: HDMI-CEC, TIM15, TIM16 and TIM17.
  • GPIO driver: add new remap parameters for TIM1, TIM15, TIM16, TIM17 and HDMI-CEC: GPIO_Remap_TIM1_DMA, GPIO_Remap_TIM15, GPIO_Remap_TIM16, GPIO_Remap_TIM17, GPIO_Remap_CEC.
  • USART driver: add support for Oversampling by 8 mode and onebit method. 2 functions has been added: USART_OverSampling8Cmd() and USART_OneBitMethodCmd().
  • DAC driver: add new functions handling the DAC under run feature: DAC_ITConfig(), DAC_GetFlagStatus(), DAC_ClearFlag(), DAC_GetITStatus() and DAC_ClearITPendingBit().
  • DBGMCU driver: add new parameters for TIM15, TIM16 and TIM17: DBGMCU_TIM15_STOP, DBGMCU_TIM16_STOP, DBGMCU_TIM17_STOP.
  • FLASH driver: the FLASH_EraseOptionBytes() function updated. This is now just erasing the option bytes without modifying the RDP status either enabled or disabled.
  • PWR driver: the PWR_EnterSTOPMode() function updated. When woken up from STOP mode, this function resets again the SLEEPDEEP bit in the Cortex-M3 System Control register to allow Sleep mode entering.

License

The enclosed firmware and all the related documentation are not covered by a License Agreement, if you need such License you can contact your local STMicroelectronics office.

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

For complete documentation on STM32(CORTEX M3) 32-Bit Microcontrollers visit www.st.com/STM32


Release Notes for STM32F10x Standard Peripherals Library Examples

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Release Notes for STM32F10x Standard Peripherals Library Examples (StdPeriph_Examples)

Copyright 2011 STMicroelectronics

Contents

  1. STM32F10x Standard Peripherals Library Examples update History
  2. License

STM32F10x Standard Peripherals Library Examples update History

V3.5.0 / 08-April-2011

Main Changes

  • Add two new examples:
    • MPU: This example presents the MPU features on STM32F10x XL-density devices and it can be easily ported to any other STM32 device supporting MPU.
    • TIM DMA Burst:This example shows how to update the TIM1 channel1 period and the duty cycle using the TIM1 DMA burst feature.
  • FSMC OneNAND, GPIO IO Toggle, EXTI, Lib_DEBUG, IWDG, WWDG, NVIC, SDIO and SysTick examples updated.
    • FSMC OneNAND example updated according to the last stm32100e_eval_fsmc_onenand.h/.c driver modification
    • SDIO example enhanced according to the last stm32_eval_sdio_sd.h/.c driver enhancement: SD Card driver is running up to 24MHz. Refer to STM32_EVAL release notes.
    • GPIO IO Toggle is updated to achieve maximum IO toggling frequency (HLCK/4).
    • EXTI example updated to give more details on how to configure an external interrupt.
    • IWDG enhanced is updated to use accurate timeout thanks to LSI frequency measure with Timers.
    • NVIC and SysTick examples enhanced to provide more details on how to use them with CMSIS layer.
    • WWDG enhanced to provide more details on how to use the peripheral and how to use its interrupt.

3.4.0 - 10/15/2010

  1. General
  • Add support for STM32F10x High-density Value line devices.
  • "system_stm32f10x.c" placed in each example folder.
  • Add new examples:
    • FSMC OneNAND.
    • I2C EEPROM, I2C TSENSOR and I2C IOExpander.
  • Remove old I2C examples: DualAddress, 10bitAddress, Interrupt, M24C08_EEPROM and SMBus.
  • Update SPI GPIO Configurations in all SPI examples: MISO is configured as Input floating.
  2. STM32F10x_StdPeriph_Examples
  • FLASH
    • Write_Protection modified to keep user configuration (already protected pages) and when Options bytes are not erased.
  • FSMC
    • New example OneNAND: this example shows how to configure the FSMC to drive the OneNAND memory mounted on STM32100E-EVAL board.

  • I2C
    • Old Examples removed.
    • New example EEPROM (based on old M24C08_EEPROM example): Using the latest version of I2C EEPROM driver (use of DMA to manage transfer from/to I2C memory). For more details refer to STM32_EVAL release note "Release_Notes_for_STM32_EVAL.html".
    • New example "I2C TSENSOR": this example shows how to use the I2C to communicate with an STLM75 (or a compatible device) I2C temperature sensor mounted on the evaluation board and used to get instantaneous external temperature
      (-55°C to +125°C). This example uses the latest I2C TSensor driver       (use of DMA to manage transfer from/to I2C device). For more details refer to STM32_EVAL release note "Release_Notes_for_STM32_EVAL.html".
    • New example "I2C IOExpander": this example shows how to configure and to use the IO Expander STMPE811 in order to control input Joystick IOs, output IOs and the Touch Screen feature. This example uses the latest I2C IO Expander driver (use of DMA to manage transfer from/to I2C device). For more details refer to STM32_EVAL release note "Release_Notes_for_STM32_EVAL.html".
  • SPI
    • Update SPI GPIO Configurations in all SPI examples: MISO is configured as Input floating.

3.3.0 - 04/16/2010

  1. General
  • Add support for STM32F10x XL-density devices.
  • Add new examples: Flash Dual_Boot, TIM9_OCToggle and TIM10_PWMOutput.
  2. STM32F10x_StdPeriph_Examples
  • FLASH
    • New example "Dual_Boot": this example demonstrates the dual Flash boot capability of XL-Density devices;
      boot from Flash memory Bank1 or Bank2.
    • Update "Program" and "Write_Protection" to support XL-density devices (up to 1Mbyte of Flash memory).
  • I2C
    • M24C08_EEPROM: updated to use the latest version of I2C EEPROM driver (use of DMA to manage transfer from/to I2C memory).
  • TIM
    • New example "TIM9_OCToggle": this example shows how to configure the TIM9 peripheral to generate two different signals with two different frequencies.
    • New example "TIM10_PWMOutput": this example shows how to configure the TIM10 peripheral in PWM (Pulse Width Modulation) mode.

3.2.0 - 03/01/2010

  1. General
  • Add support for STM32 Low-density Value line (STM32F100x4/6) and Medium-density Value line (STM32F100x8/B) devices for almost examples.
  • Add new examples: HDMI-CEC, Dual CAN, PVD and TIM15 Complementary Signals.
  2. STM32F10x_StdPeriph_Examples
  • CAN
    • Add new example Dual CAN: This example shows how to configure the CAN1 and CAN2 peripherals to send and
      receive CAN frames in normal mode. The sent frames are used to control Leds by pressing KEY or Tamper push buttons.
    • CAN Normal example renamed to CAN Networking example.
  • CEC
    • New example: This example provides a basic communication between two HDMI-CEC devices using interrupts.
  • PWR
    • New example PVD: This example shows how to configure the programmable voltage detector using an external interrupt line.
  • TIM
    • New example TIM15 Complementary Signals: This example shows how to configure the TIM15 peripheral to generate one
      complementary TIM15 signal, to insert a defined dead time value, to use the break feature and to lock the desired parameters.
    • Cascade_Synchro,Parallel_Synchro, ExtTrigger_Synchro, TIM1_Synchro examples main files: Add TIM_SelectMasterSlaveMode() function call for all slaves and masters.
  • I2C
    • EEPROM example: the i2c_ee.h/.c files are removed. The example is using the new Serial EEPROM driver stm32_eval_i2c_ee.h/.c driver available under Utilities\STM32_EVAL\Common.
  • SPI
    • M25P64_FLASH example renamed to SPI_FLASH: the spi_flash.h/.c files are removed. The example is using the new Serial SPI FLASH driver stm32_eval_spi_flash.h/.c driver available under Utilities\STM32_EVAL\Common.
  • SDIO
    • The sdcard.h/.c files are removed. The example is using the new SD Card driver stm32_eval_sdio_sd.h/.c driver available under Utilities\STM32_EVAL\Common.
  • FSMC
    • All FSMC example: the fsmc_sram.h/.c, fsmc_nor.h/.c and fsmc_nand.h/.c files are removed. The examples are using the new FSMC memories drivers stm3210e_eval_fsmc_sram.h/.c, stm3210e_eval_fsmc_nor.h/.c and stm3210e_eval_fsmc_nand.h/.c drivers available under Utilities\STM32_EVAL\STM3210E_EVAL.
  • DMA
    • FSMC example: the fsmc_sram.h/.c files are removed. The example is using the new FSMC SRAM driver stm3210e_eval_fsmc_sram.h/.c driver available under Utilities\STM32_EVAL\STM3210E_EVAL.
  • ADC
    • All ADC examples are using a dedicated system_stm32f10x.c file to configure the system core clock to 56MHz.

License

The enclosed firmware and all the related documentation are not covered by a License Agreement, if you need such License you can contact your local STMicroelectronics office.

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

For complete documentation on STM32(CORTEX M3) 32-Bit Microcontrollers visit www.st.com/STM32


Release Notes for STM32F10x Standard Peripherals Library Template

Back to Release page

Release Notes for STM32F10x Standard Peripherals Library Template (StdPeriph_Template)

Copyright 2011 STMicroelectronics

Contents

  1. STM32F10x Standard Peripherals Library Template update History
  2. License

STM32F10x Standard Peripherals Library Template update History

V3.5.0 / 08-April-2011

Main Changes

  • Template projects updated to save configuration time and easy the examples use.
  • system_stm32f10x.c
    • Add more comments on how to use this driver.
  • stm32f10x_conf.h
    • All peripheral header files inclusion enabled.

3.4.0 - 10/15/2010

  1. General
  • Add support for STM32F10x High Density Value Line devices.
  • system_stm32f10x.c file moved to project template directory.
  • "STM32F10X_XL" workspace name changed to "STM3210E-EVAL_XL" in all projects.
  3. STM32F10x_StdPeriph_Template: Template projects
  • IAR Embedded Workbench for ARM (EWARM) toolchain
    • Used version: v5.50
      • A software patch is needed to use High-density value line devices with this version, click here to download
    • Add a new workspace for STM32F10x High-density value line devices: STM32F100E-EVAL
  • Hitex IDE/Debugger (HiTOP) toolchain
    • Used version: v5.40
    • Add a new workspace for STM32F10x High-density value line devices: STM32F100E-EVAL
  • RealView Microcontroller Development Kit (MDK-ARM) toolchain
    • Used version: v4.12
      • A software patch is needed to use High-density value line devices with this version, click here to download
    • Add a new workspace for STM32F10x High-density value line devices: STM32F100E-EVAL
  • Raisonance IDE RIDE7 (RIDE) toolchain
    • Used version: RIDE7 IDE:7.30.10, RKitARM for RIDE7:1.30.10 and later
    • Add a new workspace for STM32F10x High-density value line devices: STM32F100E-EVAL
  • Atollic TrueSTUDIO STM32 (TrueSTUDIO) toolchain
    • Used version: v1.4.0
      • A software patch is needed to use High-density value line devices with this version, click here to download
    • Add a new workspace for STM32F10x High-density value line devices: STM32F100E-EVAL

04/16/2010

  1. General
  • Add support for STM32F10x XL-density devices.
  • Add template project for TrueSTUDIO toolchain
  3. STM32F10x_StdPeriph_Template: Template projects
  • IAR Embedded Workbench for ARM (EWARM) toolchain
    • Used version: v5.41
      • A software patch is needed to use XL-density devices with this version, click here to download
    • Add a new workspace for STM32F10x XL-density devices: STM32F10X_XL
  • Hitex IDE/Debugger (HiTOP) toolchain
    • Used version: v5.32
    • Add a new workspace for STM32F10x XL-density devices: STM32F10X_XL
  • RealView Microcontroller Development Kit (MDK-ARM) toolchain
    • Used version: v4.10
      • A software patch is needed to use XL-density devices with this version, click here to download
    • Add a new workspace for STM32F10x XL-density devices: STM32F10X_XL
  • Raisonance IDE RIDE7 (RIDE) toolchain
    • Used version: RIDE7 IDE:7.28.10.0075, RKitARM for RIDE7:1.24.10 and later
    • Add a new workspace for STM32F10x XL-density devices: STM32F10X_XL
  • Atolic TrueSTUDIO toolchain
    • Used version: v1.1.0
      • A software patch is needed to use XL-density devices with this version, click here to download
    • Workspaces provided for all supported STM32F10x devices

3.2.0 - 03/01/2010

  1. General
  • Add support for STM32 Low-density Value line (STM32F100x4/6) and Medium-density Value line (STM32F100x8/B) devices.
  • Update different projects to the latest toolchains versions.
  2. STM32F10x_StdPeriph_Template: Template source
  • main.c file updated to support the STM32 Value line devices and STM32100B-EVAL board.
  3. STM32F10x_StdPeriph_Template: Template projects
  • IAR Embedded Workbench for ARM (EWARM) software toolchain
    • Version 5.41
    • Add a new workspace for STM32F10x Medium-density Value line devices: STM32100B-EVAL.
  • Hitex HiTOP IDE/Debugger (HiTOP) software toolchain
    • Version 5.32
    • Add a new workspace for STM32F10x Medium-density Value line devices: STM32100B-EVAL.
    • Add cstart_thumb2.asm file to support new CMSIS V1.30 version. This file includes the SystemInit() function call.
  • Raisonance IDE RIDE7 (RIDE) software toolchain
    • Version: RIDE7 IDE:7.24.09, RKitARM for RIDE7:1.24.10
    • Add a new workspace for STM32F10x Medium-density Value line devices: STM32100B-EVAL.
  • RealView Microcontroller Development Kit (RVMDK) software toolchain
    • Version 4.03
    • Add a new workspace for STM32F10x Medium-density Value line devices: STM32100B-EVAL.

License

The enclosed firmware and all the related documentation are not covered by a License Agreement, if you need such License you can contact your local STMicroelectronics office.

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

For complete documentation on STM32(CORTEX M3) 32-Bit Microcontrollers visit www.st.com/STM32


Release Notes for STM32 Standard Peripherals Library Utilities

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Release Notes for STM32 Standard Peripherals Library Utilities (Utilities)

Copyright 2011 STMicroelectronics

Contents

  1. STM32 Standard Peripherals Library Utilities update History
  2. License

STM32 Standard Peripherals Library Utilities update History

V4.5.0 / 07-March-2011

Main Changes

  • stm32_eval_sdio_sd.c\.h: driver improvement
    • SD Clock increased to 24MHz to improve the data transfer performance.
    • Add new functions to check the SDIO peripheral and SD Card status at any time: SD_WaitReadOperation(), SD_WaitWriteOperation(). The software sequence is little bit changed but without any impact on driver API. For more details, refer to the stm32_eval_sdio_sd.c driver description.
    • Add new structure containing the SD Status register parameters. This structure is called by the SD_SendSDStatus() function.
    • Transfers mode updated
      • Read/Write Block using Polling and DMA modes
      • Read/Write Multi Blocks using DMA mode only
      • Interrupt mode removed
    • Data transfer functions are managing only fixed Block size (512-byte)
  • STM32100B-EVAL
    • stm32100b_eval_cec.c: fix some strict ANSI-C errors
  • STM32100E-EVAL
    • stm32100e_eval_cec.c: fix some strict ANSI-C errors

V4.4.0 / 31-December-2010

Main Changes

  • Add new directory for STM32L152-EVAL board containing the following files:
    • stm32l152_eval.h/.c, stm32l152_eval_lcd.h/.c, stm32l152_eval_glass_lcd.h/.c, stm32l152_eval_i2c_ee.h/.c
  • Add support for the STM32100E-EVAL Rev B: SPI FLASH CS pin "sFLASH_CS_PIN" changed from PB.02 to PE.06.
  • stm32100e_eval_lcd.h/.c: Add support for "LCD_ILI9325" LCD controller.
  • stm32100e_eval_fsmc_onenand.h/.c driver updated to correct asynchronous and synchronous read operations procedures.

4.3.0 - 10/15/2010

  1. General
  • I2C EEPROM, Temperature Sensor and IOE Expander drivers updated to use the DMA for read/write transfer and add more robustness
  • SD Card (SDIO) driver updated to add more robustness
  • SPI Flash and SD Card (SPI) drivers: SPI MISO pin configuration changed to Input Floating
  2. Utilities
  • Add new directory for STM32100E-EVAL board containing the following files:
    • stm32100e_eval.h/.c, stm32100e_eval_lcd.h/.c, stm32100e_eval_cec.h/.c, stm32100e_eval_fsmc_onenand.h/.c, stm32100e_eval_fsmc_sram.h/.c, stm32100e_eval_ioe.h/.c
  • Common
    • stm32_eval_sdio_sd.c: Update the DMA End of Transfer Check loop inside the SD_ReadBlock(), SD_WriteBlock(), SD_ReadMultiBlocks() and SD_Write MultiBlocks().
    • stm32_eval_i2c_ee.c/.h
      • Enhanced sEE_WaitEepromStandbyState() function for more robustness.
      • Enhanced Read and Write operations to manage I2C limitations.
      • Add Timeout management with user callback implementation which allows recovering from I2C bus errors.
      • Add critical sections user callbacks allowing to disable then enable interrupts when I2C operation require to be not interrupted.
    • stm32_eval_i2c_tsensor.c/.h
      • Enhanced I2C communication functions by using DMA for registers Read and Write operations.
      • Add Timeout management with user callback implementation which allows recovering from I2C bus errors.
  • STM32100B_EVAL
    • stm32100b_eval.h: Add LM75 DMA defines.
    • stm32100b_eval_lcd.c: Change "SPI_FLASH" by "sFLASH" in LCD_DrawBMP() function.
  • STM3210B_EVAL
    • stm3210b_eval.h: Add LM75 DMA defines.
    • stm3210b_eval_lcd.c: Change "SPI_FLASH" by "sFLASH" in LCD_DrawBMP() function.
  • STM3210C_EVAL
    • stm3210c_eval.h: Add EEPROM driver Timeout define.
    • stm3210c_eval_lcd.c: Change "SPI_FLASH" by "sFLASH" in LCD_DrawBMP() function.
    • stm3210c_eval_i2c_ioe.c
      • Enhanced I2C communication functions by using DMA for registers Read and Write operations.
      • Add Timeout management with user callback implementation which allows recovering from I2C bus errors.
      • change IOE_I2C_SPEED from "400000" to "300000".
  • STM3210E_EVAL
    • stm3210e_eval.c: change "void SD_WaitForDMAEndOfTransfer(void)" to "uint32_t SD_DMAEndOfTransferStatus(void)".
    • stm3210e_eval.h: Add LM75 DMA defines.
    • stm3210e_eval_fsmc_nand.h: remove "NAND_CMD_AREA_TRUE1" define.
    • stm3210e_eval_fsmc_nand.c: Update FSMC timing in NAND_Init() function to be aligned with AN2784 application note.
    • stm3210e_eval_fsmc_nor.c
      • NOR_Init() function: add FSMC_AsynchronousWait field to FSMC_NORSRAMInitStructure
    • stm3210e_eval_fsmc_sram.c
      • Update FSMC timing in SRAM_Init() function to be aligned with AN2784 application note.
      • SRAM_Init() function: add FSMC_AsynchronousWait field to FSMC_NORSRAMInitStructure
    • stm3210e_eval_lcd.c
      • LCD_FSMCConfig() function: add FSMC_AsynchronousWait field to FSMC_NORSRAMInitStructure

4.2.0 - 04/16/2010

  1. General
  • I2C EEPROM driver update to use the DMA to perform data transfer to/from EEPROM memory.
  2. Utilities
  • STM32_EVAL
    • stm32_eval_i2c_ee.c: updated to use the DMA to perform data transfer to/from EEPROM memory. For more details, refer to the description provided within this file.
    • stm3210c_eval.c: add low level functions to configure the DMA (needed for I2C EEPROM driver)
    • stm3210c_eval_ioe.c: add a delay in IOE_TS_GetState() function to wait till the end of ADC conversion
    • stm3210e_eval_fsmc_nor.c: add PD6 pin configuration in NOR_Init() function
    • stm3210b_eval_lcd.c: remove the second ";" from "static void PutPixel(int16_t x, int16_t y);;"

4.1.0 - 03/01/2010

  1. General
  • Add support for STM32 Low-density Value line (STM32F100x4/6) and Medium-density Value line (STM32F100x8/B) devices.
  • Add support for the STMicroelectronics STM32100B-EVAL evaluation board.
  2. Utilities
  • STM32_EVAL
    • Add new directory "Common" containing a common drivers for all STM32 evaluation boards: fonts.h/.c, stm32_eval_i2c_ee.h/.c, stm32_eval_spi_flash.h/.c, stm32_eval_i2c_tsensor.h/.c, stm32_eval_spi_sd.h/.c and stm32_eval_sdio_sd.h/.c
    • Add new driver for the STM32100B-EVAL managing Leds, push button and COM ports.
    • New HDMI CEC High level driver.
    • For all LCD drivers new fonts has been added.
    • New FSMC memories drivers for STM3210E-EVAL board: stm3210e_eval_fsmc_sram.h/.c, stm3210e_eval_fsmc_nor.h/.c and stm3210e_eval_fsmc_nand.h/.c.

License

The enclosed firmware and all the related documentation are not covered by a License Agreement, if you need such License you can contact your local STMicroelectronics office.

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

For complete documentation on STMicroelectronics Microcontrollers visit www.st.com